LLVM: headers diff between 3.0 and 3.1 versions

	APFloat.h	APFloat.h

	skipping to change at line 323	skipping to change at line 323
	[-]0xh.hhhhp[+-]d. Return the number of characters written,	[-]0xh.hhhhp[+-]d. Return the number of characters written,
	excluding the terminating NUL. */	excluding the terminating NUL. */
	unsigned int convertToHexString(char *dst, unsigned int hexDigits,	unsigned int convertToHexString(char *dst, unsigned int hexDigits,
	bool upperCase, roundingMode) const;	bool upperCase, roundingMode) const;

	/* Simple queries. */	/* Simple queries. */
	fltCategory getCategory() const { return category; }	fltCategory getCategory() const { return category; }
	const fltSemantics &getSemantics() const { return *semantics; }	const fltSemantics &getSemantics() const { return *semantics; }
	bool isZero() const { return category == fcZero; }	bool isZero() const { return category == fcZero; }
	bool isNonZero() const { return category != fcZero; }	bool isNonZero() const { return category != fcZero; }

		bool isNormal() const { return category == fcNormal; }
	bool isNaN() const { return category == fcNaN; }	bool isNaN() const { return category == fcNaN; }
	bool isInfinity() const { return category == fcInfinity; }	bool isInfinity() const { return category == fcInfinity; }
	bool isNegative() const { return sign; }	bool isNegative() const { return sign; }
	bool isPosZero() const { return isZero() && !isNegative(); }	bool isPosZero() const { return isZero() && !isNegative(); }
	bool isNegZero() const { return isZero() && isNegative(); }	bool isNegZero() const { return isZero() && isNegative(); }

	APFloat& operator=(const APFloat &);	APFloat& operator=(const APFloat &);


	/* Return an arbitrary integer value usable for hashing. */	/// \brief Overload to compute a hash code for an APFloat value.
	uint32_t getHashValue() const;	///
		/// Note that the use of hash codes for floating point values is in gen
		eral
		/// frought with peril. Equality is hard to define for these values. Fo
		r
		/// example, should negative and positive zero hash to different codes?
		Are
		/// they equal or not? This hash value implementation specifically
		/// emphasizes producing different codes for different inputs in order
		to
		/// be used in canonicalization and memoization. As such, equality is
		/// bitwiseIsEqual, and 0 != -0.
		friend hash_code hash_value(const APFloat &Arg);

	/// Converts this value into a decimal string.	/// Converts this value into a decimal string.
	///	///
	/// \param FormatPrecision The maximum number of digits of	/// \param FormatPrecision The maximum number of digits of
	/// precision to output. If there are fewer digits available,	/// precision to output. If there are fewer digits available,
	/// zero padding will not be used unless the value is	/// zero padding will not be used unless the value is
	/// integral and small enough to be expressed in	/// integral and small enough to be expressed in
	/// FormatPrecision digits. 0 means to use the natural	/// FormatPrecision digits. 0 means to use the natural
	/// precision of the number.	/// precision of the number.
	/// \param FormatMaxPadding The maximum number of zeros to	/// \param FormatMaxPadding The maximum number of zeros to

End of changes. 2 change blocks.
	2 lines changed or deleted	15 lines changed or added

	APInt.h	APInt.h

	skipping to change at line 26	skipping to change at line 26
	#define LLVM_APINT_H	#define LLVM_APINT_H

	#include "llvm/ADT/ArrayRef.h"	#include "llvm/ADT/ArrayRef.h"
	#include "llvm/Support/MathExtras.h"	#include "llvm/Support/MathExtras.h"
	#include <cassert>	#include <cassert>
	#include <climits>	#include <climits>
	#include <cstring>	#include <cstring>
	#include <string>	#include <string>

	namespace llvm {	namespace llvm {

	class Serializer;
	class Deserializer;	class Deserializer;
	class FoldingSetNodeID;	class FoldingSetNodeID;

	class raw_ostream;	class Serializer;
	class StringRef;	class StringRef;

		class hash_code;
		class raw_ostream;

	template<typename T>	template<typename T>
	class SmallVectorImpl;	class SmallVectorImpl;

	// An unsigned host type used as a single part of a multi-part	// An unsigned host type used as a single part of a multi-part
	// bignum.	// bignum.
	typedef uint64_t integerPart;	typedef uint64_t integerPart;

	const unsigned int host_char_bit = 8;	const unsigned int host_char_bit = 8;
	const unsigned int integerPartWidth = host_char_bit *	const unsigned int integerPartWidth = host_char_bit *

	skipping to change at line 500	skipping to change at line 501
	/// @param loBitsSet the number of low-order bits set in the result.	/// @param loBitsSet the number of low-order bits set in the result.
	/// @brief Get a value with low bits set	/// @brief Get a value with low bits set
	static APInt getLowBitsSet(unsigned numBits, unsigned loBitsSet) {	static APInt getLowBitsSet(unsigned numBits, unsigned loBitsSet) {
	assert(loBitsSet <= numBits && "Too many bits to set!");	assert(loBitsSet <= numBits && "Too many bits to set!");
	// Handle a degenerate case, to avoid shifting by word size	// Handle a degenerate case, to avoid shifting by word size
	if (loBitsSet == 0)	if (loBitsSet == 0)
	return APInt(numBits, 0);	return APInt(numBits, 0);
	if (loBitsSet == APINT_BITS_PER_WORD)	if (loBitsSet == APINT_BITS_PER_WORD)
	return APInt(numBits, -1ULL);	return APInt(numBits, -1ULL);
	// For small values, return quickly.	// For small values, return quickly.

	if (numBits < APINT_BITS_PER_WORD)	if (loBitsSet <= APINT_BITS_PER_WORD)
	return APInt(numBits, (1ULL << loBitsSet) - 1);	return APInt(numBits, -1ULL >> (APINT_BITS_PER_WORD - loBitsSet));
	return getAllOnesValue(numBits).lshr(numBits - loBitsSet);	return getAllOnesValue(numBits).lshr(numBits - loBitsSet);
	}	}


	/// The hash value is computed as the sum of the words and the bit width.	/// \brief Overload to compute a hash_code for an APInt value.
	/// @returns A hash value computed from the sum of the APInt words.	friend hash_code hash_value(const APInt &Arg);
	/// @brief Get a hash value based on this APInt
	uint64_t getHashValue() const;

	/// This function returns a pointer to the internal storage of the APInt.	/// This function returns a pointer to the internal storage of the APInt.
	/// This is useful for writing out the APInt in binary form without any	/// This is useful for writing out the APInt in binary form without any
	/// conversions.	/// conversions.
	const uint64_t* getRawData() const {	const uint64_t* getRawData() const {
	if (isSingleWord())	if (isSingleWord())
	return &VAL;	return &VAL;
	return &pVal[0];	return &pVal[0];
	}	}


	skipping to change at line 565	skipping to change at line 564
	/// Negates *this using two's complement logic.	/// Negates *this using two's complement logic.
	/// @returns An APInt value representing the negation of *this.	/// @returns An APInt value representing the negation of *this.
	/// @brief Unary negation operator	/// @brief Unary negation operator
	APInt operator-() const {	APInt operator-() const {
	return APInt(BitWidth, 0) - (*this);	return APInt(BitWidth, 0) - (*this);
	}	}

	/// Performs logical negation operation on this APInt.	/// Performs logical negation operation on this APInt.
	/// @returns true if *this is zero, false otherwise.	/// @returns true if *this is zero, false otherwise.
	/// @brief Logical negation operator.	/// @brief Logical negation operator.

	bool operator!() const;	bool operator!() const {
		if (isSingleWord())
		return !VAL;

		for (unsigned i = 0; i != getNumWords(); ++i)
		if (pVal[i])
		return false;
		return true;
		}

	/// @}	/// @}
	/// @name Assignment Operators	/// @name Assignment Operators
	/// @{	/// @{
	/// @returns *this after assignment of RHS.	/// @returns *this after assignment of RHS.
	/// @brief Copy assignment operator.	/// @brief Copy assignment operator.
	APInt& operator=(const APInt& RHS) {	APInt& operator=(const APInt& RHS) {
	// If the bitwidths are the same, we can avoid mucking with memory	// If the bitwidths are the same, we can avoid mucking with memory
	if (isSingleWord() && RHS.isSingleWord()) {	if (isSingleWord() && RHS.isSingleWord()) {
	VAL = RHS.VAL;	VAL = RHS.VAL;

	skipping to change at line 837	skipping to change at line 844
	APInt uadd_ov(const APInt &RHS, bool &Overflow) const;	APInt uadd_ov(const APInt &RHS, bool &Overflow) const;
	APInt ssub_ov(const APInt &RHS, bool &Overflow) const;	APInt ssub_ov(const APInt &RHS, bool &Overflow) const;
	APInt usub_ov(const APInt &RHS, bool &Overflow) const;	APInt usub_ov(const APInt &RHS, bool &Overflow) const;
	APInt sdiv_ov(const APInt &RHS, bool &Overflow) const;	APInt sdiv_ov(const APInt &RHS, bool &Overflow) const;
	APInt smul_ov(const APInt &RHS, bool &Overflow) const;	APInt smul_ov(const APInt &RHS, bool &Overflow) const;
	APInt umul_ov(const APInt &RHS, bool &Overflow) const;	APInt umul_ov(const APInt &RHS, bool &Overflow) const;
	APInt sshl_ov(unsigned Amt, bool &Overflow) const;	APInt sshl_ov(unsigned Amt, bool &Overflow) const;

	/// @returns the bit value at bitPosition	/// @returns the bit value at bitPosition
	/// @brief Array-indexing support.	/// @brief Array-indexing support.

	bool operator[](unsigned bitPosition) const;	bool operator[](unsigned bitPosition) const {
		assert(bitPosition < getBitWidth() && "Bit position out of bounds!");
		return (maskBit(bitPosition) &
		(isSingleWord() ? VAL : pVal[whichWord(bitPosition)])) != 0;
		}

	/// @}	/// @}
	/// @name Comparison Operators	/// @name Comparison Operators
	/// @{	/// @{
	/// Compares this APInt with RHS for the validity of the equality	/// Compares this APInt with RHS for the validity of the equality
	/// relationship.	/// relationship.
	/// @brief Equality operator.	/// @brief Equality operator.
	bool operator==(const APInt& RHS) const {	bool operator==(const APInt& RHS) const {
	assert(BitWidth == RHS.BitWidth && "Comparison requires equal bit width s");	assert(BitWidth == RHS.BitWidth && "Comparison requires equal bit width s");
	if (isSingleWord())	if (isSingleWord())

	skipping to change at line 1055	skipping to change at line 1066
	/// Make this APInt have the bit width given by \p width. The value is si gn	/// Make this APInt have the bit width given by \p width. The value is si gn
	/// extended, truncated, or left alone to make it that width.	/// extended, truncated, or left alone to make it that width.
	/// @brief Sign extend or truncate to width	/// @brief Sign extend or truncate to width
	APInt sextOrTrunc(unsigned width) const;	APInt sextOrTrunc(unsigned width) const;

	/// Make this APInt have the bit width given by \p width. The value is ze ro	/// Make this APInt have the bit width given by \p width. The value is ze ro
	/// extended, truncated, or left alone to make it that width.	/// extended, truncated, or left alone to make it that width.
	/// @brief Zero extend or truncate to width	/// @brief Zero extend or truncate to width
	APInt zextOrTrunc(unsigned width) const;	APInt zextOrTrunc(unsigned width) const;


		/// Make this APInt have the bit width given by \p width. The value is si
		gn
		/// extended, or left alone to make it that width.
		/// @brief Sign extend or truncate to width
		APInt sextOrSelf(unsigned width) const;

		/// Make this APInt have the bit width given by \p width. The value is ze
		ro
		/// extended, or left alone to make it that width.
		/// @brief Zero extend or truncate to width
		APInt zextOrSelf(unsigned width) const;

	/// @}	/// @}
	/// @name Bit Manipulation Operators	/// @name Bit Manipulation Operators
	/// @{	/// @{
	/// @brief Set every bit to 1.	/// @brief Set every bit to 1.
	void setAllBits() {	void setAllBits() {
	if (isSingleWord())	if (isSingleWord())
	VAL = -1ULL;	VAL = -1ULL;
	else {	else {
	// Set all the bits in all the words.	// Set all the bits in all the words.
	for (unsigned i = 0; i < getNumWords(); ++i)	for (unsigned i = 0; i < getNumWords(); ++i)

End of changes. 8 change blocks.
	10 lines changed or deleted	33 lines changed or added

	Analysis.h	Analysis.h

	skipping to change at line 28	skipping to change at line 28

	#ifndef LLVM_C_ANALYSIS_H	#ifndef LLVM_C_ANALYSIS_H
	#define LLVM_C_ANALYSIS_H	#define LLVM_C_ANALYSIS_H

	#include "llvm-c/Core.h"	#include "llvm-c/Core.h"

	#ifdef __cplusplus	#ifdef __cplusplus
	extern "C" {	extern "C" {
	#endif	#endif


		/**
		* @defgroup LLVMCAnalysis Analysis
		* @ingroup LLVMC
		*
		* @{
		*/

	typedef enum {	typedef enum {
	LLVMAbortProcessAction, /* verifier will print to stderr and abort() */	LLVMAbortProcessAction, /* verifier will print to stderr and abort() */
	LLVMPrintMessageAction, /* verifier will print to stderr and return 1 */	LLVMPrintMessageAction, /* verifier will print to stderr and return 1 */
	LLVMReturnStatusAction /* verifier will just return 1 */	LLVMReturnStatusAction /* verifier will just return 1 */
	} LLVMVerifierFailureAction;	} LLVMVerifierFailureAction;

	/* Verifies that a module is valid, taking the specified action if not.	/* Verifies that a module is valid, taking the specified action if not.
	Optionally returns a human-readable description of any invalid construct s.	Optionally returns a human-readable description of any invalid construct s.
	OutMessage must be disposed with LLVMDisposeMessage. */	OutMessage must be disposed with LLVMDisposeMessage. */
	LLVMBool LLVMVerifyModule(LLVMModuleRef M, LLVMVerifierFailureAction Action ,	LLVMBool LLVMVerifyModule(LLVMModuleRef M, LLVMVerifierFailureAction Action ,

	skipping to change at line 49	skipping to change at line 56

	/* Verifies that a single function is valid, taking the specified action. U seful	/* Verifies that a single function is valid, taking the specified action. U seful
	for debugging. */	for debugging. */
	LLVMBool LLVMVerifyFunction(LLVMValueRef Fn, LLVMVerifierFailureAction Acti on);	LLVMBool LLVMVerifyFunction(LLVMValueRef Fn, LLVMVerifierFailureAction Acti on);

	/* Open up a ghostview window that displays the CFG of the current function .	/* Open up a ghostview window that displays the CFG of the current function .
	Useful for debugging. */	Useful for debugging. */
	void LLVMViewFunctionCFG(LLVMValueRef Fn);	void LLVMViewFunctionCFG(LLVMValueRef Fn);
	void LLVMViewFunctionCFGOnly(LLVMValueRef Fn);	void LLVMViewFunctionCFGOnly(LLVMValueRef Fn);


		/**
		* @}
		*/

	#ifdef __cplusplus	#ifdef __cplusplus
	}	}
	#endif	#endif

	#endif	#endif

End of changes. 2 change blocks.
	0 lines changed or deleted	11 lines changed or added

	Archive.h	Archive.h

	skipping to change at line 25	skipping to change at line 25
	#define LLVM_OBJECT_ARCHIVE_H	#define LLVM_OBJECT_ARCHIVE_H

	#include "llvm/Object/Binary.h"	#include "llvm/Object/Binary.h"
	#include "llvm/ADT/StringRef.h"	#include "llvm/ADT/StringRef.h"
	#include "llvm/Support/DataTypes.h"	#include "llvm/Support/DataTypes.h"

	namespace llvm {	namespace llvm {
	namespace object {	namespace object {

	class Archive : public Binary {	class Archive : public Binary {

		virtual void anchor();
	public:	public:
	class Child {	class Child {
	const Archive *Parent;	const Archive *Parent;
	StringRef Data;	StringRef Data;

	public:	public:
	Child(const Archive *p, StringRef d) : Parent(p), Data(d) {}	Child(const Archive *p, StringRef d) : Parent(p), Data(d) {}

	bool operator ==(const Child &other) const {	bool operator ==(const Child &other) const {
	return (Parent == other.Parent) && (Data.begin() == other.Data.begin( ));	return (Parent == other.Parent) && (Data.begin() == other.Data.begin( ));
	}	}


		bool operator <(const Child &other) const {
		return Data.begin() < other.Data.begin();
		}

	Child getNext() const;	Child getNext() const;
	error_code getName(StringRef &Result) const;	error_code getName(StringRef &Result) const;
	int getLastModified() const;	int getLastModified() const;
	int getUID() const;	int getUID() const;
	int getGID() const;	int getGID() const;
	int getAccessMode() const;	int getAccessMode() const;
	///! Return the size of the archive member without the header or paddin g.	///! Return the size of the archive member without the header or paddin g.
	uint64_t getSize() const;	uint64_t getSize() const;

	MemoryBuffer *getBuffer() const;	MemoryBuffer *getBuffer() const;
	error_code getAsBinary(OwningPtr<Binary> &Result) const;	error_code getAsBinary(OwningPtr<Binary> &Result) const;
	};	};

	class child_iterator {	class child_iterator {
	Child child;	Child child;
	public:	public:

		child_iterator() : child(Child(0, StringRef())) {}
	child_iterator(const Child &c) : child(c) {}	child_iterator(const Child &c) : child(c) {}
	const Child* operator->() const {	const Child* operator->() const {
	return &child;	return &child;
	}	}

	bool operator==(const child_iterator &other) const {	bool operator==(const child_iterator &other) const {
	return child == other.child;	return child == other.child;
	}	}

	bool operator!=(const child_iterator &other) const {	bool operator!=(const child_iterator &other) const {
	return !(*this == other);	return !(*this == other);
	}	}


		bool operator <(const child_iterator &other) const {
		return child < other.child;
		}

	child_iterator& operator++() { // Preincrement	child_iterator& operator++() { // Preincrement
	child = child.getNext();	child = child.getNext();
	return *this;	return *this;
	}	}
	};	};


		class Symbol {
		const Archive *Parent;
		uint32_t SymbolIndex;
		uint32_t StringIndex; // Extra index to the string.

		public:
		bool operator ==(const Symbol &other) const {
		return (Parent == other.Parent) && (SymbolIndex == other.SymbolIndex)
		;
		}

		Symbol(const Archive *p, uint32_t symi, uint32_t stri)
		: Parent(p)
		, SymbolIndex(symi)
		, StringIndex(stri) {}
		error_code getName(StringRef &Result) const;
		error_code getMember(child_iterator &Result) const;
		Symbol getNext() const;
		};

		class symbol_iterator {
		Symbol symbol;
		public:
		symbol_iterator(const Symbol &s) : symbol(s) {}
		const Symbol *operator->() const {
		return &symbol;
		}

		bool operator==(const symbol_iterator &other) const {
		return symbol == other.symbol;
		}

		bool operator!=(const symbol_iterator &other) const {
		return !(*this == other);
		}

		symbol_iterator& operator++() { // Preincrement
		symbol = symbol.getNext();
		return *this;
		}
		};

	Archive(MemoryBuffer *source, error_code &ec);	Archive(MemoryBuffer *source, error_code &ec);


	child_iterator begin_children() const;	child_iterator begin_children(bool skip_internal = true) const;
	child_iterator end_children() const;	child_iterator end_children() const;


		symbol_iterator begin_symbols() const;
		symbol_iterator end_symbols() const;

	// Cast methods.	// Cast methods.
	static inline bool classof(Archive const *v) { return true; }	static inline bool classof(Archive const *v) { return true; }
	static inline bool classof(Binary const *v) {	static inline bool classof(Binary const *v) {

	return v->getType() == Binary::isArchive;	return v->isArchive();
	}	}

	private:	private:

		child_iterator SymbolTable;
	child_iterator StringTable;	child_iterator StringTable;
	};	};

	}	}
	}	}

	#endif	#endif

End of changes. 9 change blocks.
	2 lines changed or deleted	58 lines changed or added

	ArrayRef.h	ArrayRef.h

	skipping to change at line 17	skipping to change at line 17
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_ADT_ARRAYREF_H	#ifndef LLVM_ADT_ARRAYREF_H
	#define LLVM_ADT_ARRAYREF_H	#define LLVM_ADT_ARRAYREF_H

	#include "llvm/ADT/SmallVector.h"	#include "llvm/ADT/SmallVector.h"
	#include <vector>	#include <vector>

	namespace llvm {	namespace llvm {

	class APInt;

	/// ArrayRef - Represent a constant reference to an array (0 or more elem ents	/// ArrayRef - Represent a constant reference to an array (0 or more elem ents
	/// consecutively in memory), i.e. a start pointer and a length. It allo ws	/// consecutively in memory), i.e. a start pointer and a length. It allo ws
	/// various APIs to take consecutive elements easily and conveniently.	/// various APIs to take consecutive elements easily and conveniently.
	///	///
	/// This class does not own the underlying data, it is expected to be use d in	/// This class does not own the underlying data, it is expected to be use d in
	/// situations where the data resides in some other buffer, whose lifetim e	/// situations where the data resides in some other buffer, whose lifetim e
	/// extends past that of the ArrayRef. For this reason, it is not in gene ral	/// extends past that of the ArrayRef. For this reason, it is not in gene ral
	/// safe to store an ArrayRef.	/// safe to store an ArrayRef.
	///	///

	skipping to change at line 114	skipping to change at line 113
	bool equals(ArrayRef RHS) const {	bool equals(ArrayRef RHS) const {
	if (Length != RHS.Length)	if (Length != RHS.Length)
	return false;	return false;
	for (size_type i = 0; i != Length; i++)	for (size_type i = 0; i != Length; i++)
	if (Data[i] != RHS.Data[i])	if (Data[i] != RHS.Data[i])
	return false;	return false;
	return true;	return true;
	}	}

	/// slice(n) - Chop off the first N elements of the array.	/// slice(n) - Chop off the first N elements of the array.

	ArrayRef<T> slice(unsigned N) {	ArrayRef<T> slice(unsigned N) const {
	assert(N <= size() && "Invalid specifier");	assert(N <= size() && "Invalid specifier");
	return ArrayRef<T>(data()+N, size()-N);	return ArrayRef<T>(data()+N, size()-N);
	}	}

	/// slice(n, m) - Chop off the first N elements of the array, and keep M	/// slice(n, m) - Chop off the first N elements of the array, and keep M
	/// elements in the array.	/// elements in the array.

	ArrayRef<T> slice(unsigned N, unsigned M) {	ArrayRef<T> slice(unsigned N, unsigned M) const {
	assert(N+M <= size() && "Invalid specifier");	assert(N+M <= size() && "Invalid specifier");
	return ArrayRef<T>(data()+N, M);	return ArrayRef<T>(data()+N, M);
	}	}

	/// @}	/// @}
	/// @name Operator Overloads	/// @name Operator Overloads
	/// @{	/// @{
	const T &operator[](size_t Index) const {	const T &operator[](size_t Index) const {
	assert(Index < Length && "Invalid index!");	assert(Index < Length && "Invalid index!");
	return Data[Index];	return Data[Index];

	skipping to change at line 151	skipping to change at line 150
	/// @}	/// @}
	/// @name Conversion operators	/// @name Conversion operators
	/// @{	/// @{
	operator std::vector<T>() const {	operator std::vector<T>() const {
	return std::vector<T>(Data, Data+Length);	return std::vector<T>(Data, Data+Length);
	}	}

	/// @}	/// @}
	};	};


		/// MutableArrayRef - Represent a mutable reference to an array (0 or mor
		e
		/// elements consecutively in memory), i.e. a start pointer and a length.
		It
		/// allows various APIs to take and modify consecutive elements easily an
		d
		/// conveniently.
		///
		/// This class does not own the underlying data, it is expected to be use
		d in
		/// situations where the data resides in some other buffer, whose lifetim
		e
		/// extends past that of the MutableArrayRef. For this reason, it is not
		in
		/// general safe to store a MutableArrayRef.
		///
		/// This is intended to be trivially copyable, so it should be passed by
		/// value.
		template<typename T>
		class MutableArrayRef : public ArrayRef<T> {
		public:
		typedef T *iterator;

		/// Construct an empty ArrayRef.
		/implicit/ MutableArrayRef() : ArrayRef<T>() {}

		/// Construct an MutableArrayRef from a single element.
		/implicit/ MutableArrayRef(T &OneElt) : ArrayRef<T>(OneElt) {}

		/// Construct an MutableArrayRef from a pointer and length.
		/implicit/ MutableArrayRef(T *data, size_t length)
		: ArrayRef<T>(data, length) {}

		/// Construct an MutableArrayRef from a range.
		MutableArrayRef(T begin, T end) : ArrayRef<T>(begin, end) {}

		/// Construct an MutableArrayRef from a SmallVector.
		/implicit/ MutableArrayRef(SmallVectorImpl<T> &Vec)
		: ArrayRef<T>(Vec) {}

		/// Construct a MutableArrayRef from a std::vector.
		/implicit/ MutableArrayRef(std::vector<T> &Vec)
		: ArrayRef<T>(Vec) {}

		/// Construct an MutableArrayRef from a C array.
		template <size_t N>
		/implicit/ MutableArrayRef(T (&Arr)[N])
		: ArrayRef<T>(Arr) {}

		T data() const { return const_cast<T>(ArrayRef<T>::data()); }

		iterator begin() const { return data(); }
		iterator end() const { return data() + this->size(); }

		/// front - Get the first element.
		T &front() const {
		assert(!this->empty());
		return data()[0];
		}

		/// back - Get the last element.
		T &back() const {
		assert(!this->empty());
		return data()[this->size()-1];
		}

		/// slice(n) - Chop off the first N elements of the array.
		MutableArrayRef<T> slice(unsigned N) const {
		assert(N <= this->size() && "Invalid specifier");
		return MutableArrayRef<T>(data()+N, this->size()-N);
		}

		/// slice(n, m) - Chop off the first N elements of the array, and keep
		M
		/// elements in the array.
		MutableArrayRef<T> slice(unsigned N, unsigned M) const {
		assert(N+M <= this->size() && "Invalid specifier");
		return MutableArrayRef<T>(data()+N, M);
		}

		/// @}
		/// @name Operator Overloads
		/// @{
		T &operator[](size_t Index) const {
		assert(Index < this->size() && "Invalid index!");
		return data()[Index];
		}
		};

	/// @name ArrayRef Convenience constructors	/// @name ArrayRef Convenience constructors
	/// @{	/// @{

	/// Construct an ArrayRef from a single element.	/// Construct an ArrayRef from a single element.
	template<typename T>	template<typename T>
	ArrayRef<T> makeArrayRef(const T &OneElt) {	ArrayRef<T> makeArrayRef(const T &OneElt) {
	return OneElt;	return OneElt;
	}	}

	/// Construct an ArrayRef from a pointer and length.	/// Construct an ArrayRef from a pointer and length.

End of changes. 4 change blocks.
	3 lines changed or deleted	91 lines changed or added

	AsmLexer.h	AsmLexer.h

	skipping to change at line 19	skipping to change at line 19
	//	//
	// This class declares the lexer for assembly files.	// This class declares the lexer for assembly files.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef ASMLEXER_H	#ifndef ASMLEXER_H
	#define ASMLEXER_H	#define ASMLEXER_H

	#include "llvm/ADT/StringRef.h"	#include "llvm/ADT/StringRef.h"
	#include "llvm/MC/MCParser/MCAsmLexer.h"	#include "llvm/MC/MCParser/MCAsmLexer.h"

	#include "llvm/MC/MCAsmInfo.h"
	#include "llvm/Support/DataTypes.h"	#include "llvm/Support/DataTypes.h"
	#include <string>	#include <string>

	#include <cassert>

	namespace llvm {	namespace llvm {
	class MemoryBuffer;	class MemoryBuffer;

	class SMLoc;
	class MCAsmInfo;	class MCAsmInfo;

	/// AsmLexer - Lexer class for assembly files.	/// AsmLexer - Lexer class for assembly files.
	class AsmLexer : public MCAsmLexer {	class AsmLexer : public MCAsmLexer {
	const MCAsmInfo &MAI;	const MCAsmInfo &MAI;

	const char *CurPtr;	const char *CurPtr;
	const MemoryBuffer *CurBuf;	const MemoryBuffer *CurBuf;
	bool isAtStartOfLine;	bool isAtStartOfLine;


End of changes. 3 change blocks.
	3 lines changed or deleted	0 lines changed or added

	AsmParsers.def	AsmParsers.def

	skipping to change at line 27	skipping to change at line 27
	// The set of targets supported by LLVM is generated at configuration	// The set of targets supported by LLVM is generated at configuration
	// time, at which point this header is generated. Do not modify this	// time, at which point this header is generated. Do not modify this
	// header directly.	// header directly.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_ASM_PARSER	#ifndef LLVM_ASM_PARSER
	# error Please define the macro LLVM_ASM_PARSER(TargetName)	# error Please define the macro LLVM_ASM_PARSER(TargetName)
	#endif	#endif


	LLVM_ASM_PARSER(MBlaze) LLVM_ASM_PARSER(ARM) LLVM_ASM_PARSER(X86)	LLVM_ASM_PARSER(MBlaze) LLVM_ASM_PARSER(Mips) LLVM_ASM_PARSER(ARM) LLVM_ASM _PARSER(X86)

	#undef LLVM_ASM_PARSER	#undef LLVM_ASM_PARSER

End of changes. 1 change blocks.
	1 lines changed or deleted	1 lines changed or added

	AsmPrinter.h	AsmPrinter.h

	skipping to change at line 21	skipping to change at line 21
	// asm writers. This class primarily handles common functionality used by	// asm writers. This class primarily handles common functionality used by
	// all asm writers.	// all asm writers.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_CODEGEN_ASMPRINTER_H	#ifndef LLVM_CODEGEN_ASMPRINTER_H
	#define LLVM_CODEGEN_ASMPRINTER_H	#define LLVM_CODEGEN_ASMPRINTER_H

	#include "llvm/CodeGen/MachineFunctionPass.h"	#include "llvm/CodeGen/MachineFunctionPass.h"
	#include "llvm/Support/DataTypes.h"	#include "llvm/Support/DataTypes.h"

		#include "llvm/Support/ErrorHandling.h"

	namespace llvm {	namespace llvm {
	class BlockAddress;	class BlockAddress;
	class GCStrategy;	class GCStrategy;
	class Constant;	class Constant;

	class ConstantArray;
	class ConstantFP;
	class ConstantInt;
	class ConstantStruct;
	class ConstantVector;
	class GCMetadataPrinter;	class GCMetadataPrinter;
	class GlobalValue;	class GlobalValue;
	class GlobalVariable;	class GlobalVariable;
	class MachineBasicBlock;	class MachineBasicBlock;
	class MachineFunction;	class MachineFunction;
	class MachineInstr;	class MachineInstr;
	class MachineLocation;	class MachineLocation;
	class MachineLoopInfo;	class MachineLoopInfo;
	class MachineLoop;	class MachineLoop;

	class MachineConstantPool;
	class MachineConstantPoolEntry;
	class MachineConstantPoolValue;	class MachineConstantPoolValue;
	class MachineJumpTableInfo;	class MachineJumpTableInfo;
	class MachineModuleInfo;	class MachineModuleInfo;
	class MachineMove;	class MachineMove;
	class MCAsmInfo;	class MCAsmInfo;

	class MCInst;
	class MCContext;	class MCContext;
	class MCSection;	class MCSection;
	class MCStreamer;	class MCStreamer;
	class MCSymbol;	class MCSymbol;
	class MDNode;	class MDNode;
	class DwarfDebug;	class DwarfDebug;
	class DwarfException;	class DwarfException;
	class Mangler;	class Mangler;
	class TargetLoweringObjectFile;	class TargetLoweringObjectFile;
	class TargetData;	class TargetData;
	class TargetMachine;	class TargetMachine;

	class Twine;
	class Type;

	/// AsmPrinter - This class is intended to be used as a driving class for all	/// AsmPrinter - This class is intended to be used as a driving class for all
	/// asm writers.	/// asm writers.
	class AsmPrinter : public MachineFunctionPass {	class AsmPrinter : public MachineFunctionPass {
	public:	public:
	/// Target machine description.	/// Target machine description.
	///	///
	TargetMachine &TM;	TargetMachine &TM;

	/// Target Asm Printer information.	/// Target Asm Printer information.

	skipping to change at line 100	skipping to change at line 91

	/// Name-mangler for global names.	/// Name-mangler for global names.
	///	///
	Mangler *Mang;	Mangler *Mang;

	/// The symbol for the current function. This is recalculated at the	/// The symbol for the current function. This is recalculated at the
	/// beginning of each call to runOnMachineFunction().	/// beginning of each call to runOnMachineFunction().
	///	///
	MCSymbol *CurrentFnSym;	MCSymbol *CurrentFnSym;


		/// The symbol used to represent the start of the current function for
		the
		/// purpose of calculating its size (e.g. using the .size directive). B
		y
		/// default, this is equal to CurrentFnSym.
		MCSymbol *CurrentFnSymForSize;

	private:	private:
	// GCMetadataPrinters - The garbage collection metadata printer table.	// GCMetadataPrinters - The garbage collection metadata printer table.
	void *GCMetadataPrinters; // Really a DenseMap.	void *GCMetadataPrinters; // Really a DenseMap.

	/// VerboseAsm - Emit comments in assembly output if this is true.	/// VerboseAsm - Emit comments in assembly output if this is true.
	///	///
	bool VerboseAsm;	bool VerboseAsm;
	static char ID;	static char ID;

	/// If VerboseAsm is set, a pointer to the loop info for this	/// If VerboseAsm is set, a pointer to the loop info for this

	skipping to change at line 196	skipping to change at line 192

	enum CFIMoveType {	enum CFIMoveType {
	CFI_M_None,	CFI_M_None,
	CFI_M_EH,	CFI_M_EH,
	CFI_M_Debug	CFI_M_Debug
	};	};
	CFIMoveType needsCFIMoves();	CFIMoveType needsCFIMoves();

	bool needsSEHMoves();	bool needsSEHMoves();


		/// needsRelocationsForDwarfStringPool - Specifies whether the object f
		ormat
		/// expects to use relocations to refer to debug entries. Alternatively
		we
		/// emit section offsets in bytes from the start of the string pool.
		bool needsRelocationsForDwarfStringPool() const;

	/// EmitConstantPool - Print to the current output stream assembly	/// EmitConstantPool - Print to the current output stream assembly
	/// representations of the constants in the constant pool MCP. This is	/// representations of the constants in the constant pool MCP. This is
	/// used to print out constants which have been "spilled to memory" by	/// used to print out constants which have been "spilled to memory" by
	/// the code generator.	/// the code generator.
	///	///
	virtual void EmitConstantPool();	virtual void EmitConstantPool();

	/// EmitJumpTableInfo - Print assembly representations of the jump tabl es	/// EmitJumpTableInfo - Print assembly representations of the jump tabl es
	/// used by the current function to the current output stream.	/// used by the current function to the current output stream.
	///	///

	skipping to change at line 257	skipping to change at line 258
	/// EmitFunctionBodyStart - Targets can override this to emit stuff bef ore	/// EmitFunctionBodyStart - Targets can override this to emit stuff bef ore
	/// the first basic block in the function.	/// the first basic block in the function.
	virtual void EmitFunctionBodyStart() {}	virtual void EmitFunctionBodyStart() {}

	/// EmitFunctionBodyEnd - Targets can override this to emit stuff after	/// EmitFunctionBodyEnd - Targets can override this to emit stuff after
	/// the last basic block in the function.	/// the last basic block in the function.
	virtual void EmitFunctionBodyEnd() {}	virtual void EmitFunctionBodyEnd() {}

	/// EmitInstruction - Targets should implement this to emit instruction s.	/// EmitInstruction - Targets should implement this to emit instruction s.
	virtual void EmitInstruction(const MachineInstr *) {	virtual void EmitInstruction(const MachineInstr *) {

	assert(0 && "EmitInstruction not implemented");	llvm_unreachable("EmitInstruction not implemented");
	}	}

	virtual void EmitFunctionEntryLabel();	virtual void EmitFunctionEntryLabel();

	virtual void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCP V);	virtual void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCP V);


		/// EmitXXStructor - Targets can override this to change how global
		/// constants that are part of a C++ static/global constructor list are
		/// emitted.
		virtual void EmitXXStructor(const Constant *CV) {
		EmitGlobalConstant(CV);
		}

	/// isBlockOnlyReachableByFallthough - Return true if the basic block h as	/// isBlockOnlyReachableByFallthough - Return true if the basic block h as
	/// exactly one predecessor and the control transfer mechanism between	/// exactly one predecessor and the control transfer mechanism between
	/// the predecessor and this block is a fall-through.	/// the predecessor and this block is a fall-through.
	virtual bool	virtual bool
	isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB) const;	isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB) const;

	//===------------------------------------------------------------------ ===//	//===------------------------------------------------------------------ ===//
	// Symbol Lowering Routines.	// Symbol Lowering Routines.
	//===------------------------------------------------------------------ ===//	//===------------------------------------------------------------------ ===//
	public:	public:

	skipping to change at line 466	skipping to change at line 474
	/// this is suported by the target.	/// this is suported by the target.
	void EmitVisibility(MCSymbol *Sym, unsigned Visibility,	void EmitVisibility(MCSymbol *Sym, unsigned Visibility,
	bool IsDefinition = true) const;	bool IsDefinition = true) const;

	void EmitLinkage(unsigned Linkage, MCSymbol *GVSym) const;	void EmitLinkage(unsigned Linkage, MCSymbol *GVSym) const;

	void EmitJumpTableEntry(const MachineJumpTableInfo *MJTI,	void EmitJumpTableEntry(const MachineJumpTableInfo *MJTI,
	const MachineBasicBlock *MBB,	const MachineBasicBlock *MBB,
	unsigned uid) const;	unsigned uid) const;
	void EmitLLVMUsedList(const Constant *List);	void EmitLLVMUsedList(const Constant *List);

	void EmitXXStructorList(const Constant *List);	void EmitXXStructorList(const Constant *List, bool isCtor);
	GCMetadataPrinter GetOrCreateGCPrinter(GCStrategy C);	GCMetadataPrinter GetOrCreateGCPrinter(GCStrategy C);
	};	};
	}	}

	#endif	#endif

End of changes. 10 change blocks.
	12 lines changed or deleted	24 lines changed or added

	AsmPrinters.def	AsmPrinters.def

	skipping to change at line 27	skipping to change at line 27
	// The set of targets supported by LLVM is generated at configuration	// The set of targets supported by LLVM is generated at configuration
	// time, at which point this header is generated. Do not modify this	// time, at which point this header is generated. Do not modify this
	// header directly.	// header directly.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_ASM_PRINTER	#ifndef LLVM_ASM_PRINTER
	# error Please define the macro LLVM_ASM_PRINTER(TargetName)	# error Please define the macro LLVM_ASM_PRINTER(TargetName)
	#endif	#endif


	LLVM_ASM_PRINTER(PTX) LLVM_ASM_PRINTER(MBlaze) LLVM_ASM_PRINTER(Blackfin) L LVM_ASM_PRINTER(SystemZ) LLVM_ASM_PRINTER(MSP430) LLVM_ASM_PRINTER(XCore) L LVM_ASM_PRINTER(CellSPU) LLVM_ASM_PRINTER(Mips) LLVM_ASM_PRINTER(ARM) LLVM_ ASM_PRINTER(Alpha) LLVM_ASM_PRINTER(PowerPC) LLVM_ASM_PRINTER(Sparc) LLVM_A SM_PRINTER(X86)	LLVM_ASM_PRINTER(Hexagon) LLVM_ASM_PRINTER(PTX) LLVM_ASM_PRINTER(MBlaze) LL VM_ASM_PRINTER(MSP430) LLVM_ASM_PRINTER(XCore) LLVM_ASM_PRINTER(CellSPU) LL VM_ASM_PRINTER(Mips) LLVM_ASM_PRINTER(ARM) LLVM_ASM_PRINTER(PowerPC) LLVM_A SM_PRINTER(Sparc) LLVM_ASM_PRINTER(X86)

	#undef LLVM_ASM_PRINTER	#undef LLVM_ASM_PRINTER

End of changes. 1 change blocks.
	1 lines changed or deleted	1 lines changed or added

	AssemblyAnnotationWriter.h	AssemblyAnnotationWriter.h

	skipping to change at line 25	skipping to change at line 25
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_ASSEMBLY_ASMANNOTATIONWRITER_H	#ifndef LLVM_ASSEMBLY_ASMANNOTATIONWRITER_H
	#define LLVM_ASSEMBLY_ASMANNOTATIONWRITER_H	#define LLVM_ASSEMBLY_ASMANNOTATIONWRITER_H

	namespace llvm {	namespace llvm {

	class Function;	class Function;
	class BasicBlock;	class BasicBlock;
	class Instruction;	class Instruction;

	class raw_ostream;	class Value;
	class formatted_raw_ostream;	class formatted_raw_ostream;

	class AssemblyAnnotationWriter {	class AssemblyAnnotationWriter {
	public:	public:

	virtual ~AssemblyAnnotationWriter();	virtual ~AssemblyAnnotationWriter();

	/// emitFunctionAnnot - This may be implemented to emit a string right be fore	/// emitFunctionAnnot - This may be implemented to emit a string right be fore
	/// the start of a function.	/// the start of a function.

	virtual void emitFunctionAnnot(const Function *F,	virtual void emitFunctionAnnot(const Function *,
	formatted_raw_ostream &OS) {}	formatted_raw_ostream &) {}

	/// emitBasicBlockStartAnnot - This may be implemented to emit a string r ight	/// emitBasicBlockStartAnnot - This may be implemented to emit a string r ight
	/// after the basic block label, but before the first instruction in the	/// after the basic block label, but before the first instruction in the
	/// block.	/// block.

	virtual void emitBasicBlockStartAnnot(const BasicBlock *BB,	virtual void emitBasicBlockStartAnnot(const BasicBlock *,
	formatted_raw_ostream &OS) {	formatted_raw_ostream &) {
	}	}

	/// emitBasicBlockEndAnnot - This may be implemented to emit a string rig ht	/// emitBasicBlockEndAnnot - This may be implemented to emit a string rig ht
	/// after the basic block.	/// after the basic block.

	virtual void emitBasicBlockEndAnnot(const BasicBlock *BB,	virtual void emitBasicBlockEndAnnot(const BasicBlock *,
	formatted_raw_ostream &OS) {	formatted_raw_ostream &) {
	}	}

	/// emitInstructionAnnot - This may be implemented to emit a string right	/// emitInstructionAnnot - This may be implemented to emit a string right
	/// before an instruction is emitted.	/// before an instruction is emitted.

	virtual void emitInstructionAnnot(const Instruction *I,	virtual void emitInstructionAnnot(const Instruction *,
	formatted_raw_ostream &OS) {}	formatted_raw_ostream &) {}

	/// printInfoComment - This may be implemented to emit a comment to the	/// printInfoComment - This may be implemented to emit a comment to the
	/// right of an instruction or global value.	/// right of an instruction or global value.

	virtual void printInfoComment(const Value &V, formatted_raw_ostream &OS) {}	virtual void printInfoComment(const Value &, formatted_raw_ostream &) {}
	};	};

	} // End llvm namespace	} // End llvm namespace

	#endif	#endif

End of changes. 6 change blocks.
	10 lines changed or deleted	10 lines changed or added

	Attributes.h	Attributes.h

	skipping to change at line 25	skipping to change at line 25
	#ifndef LLVM_ATTRIBUTES_H	#ifndef LLVM_ATTRIBUTES_H
	#define LLVM_ATTRIBUTES_H	#define LLVM_ATTRIBUTES_H

	#include "llvm/Support/MathExtras.h"	#include "llvm/Support/MathExtras.h"
	#include <cassert>	#include <cassert>
	#include <string>	#include <string>

	namespace llvm {	namespace llvm {
	class Type;	class Type;


		namespace Attribute {
		/// We use this proxy POD type to allow constructing Attributes constants
		/// using initializer lists. Do not use this class directly.
		struct AttrConst {
		uint64_t v;
		AttrConst operator \| (const AttrConst Attrs) const {
		AttrConst Res = {v \| Attrs.v};
		return Res;
		}
		AttrConst operator ~ () const {
		AttrConst Res = {~v};
		return Res;
		}
		};
		} // namespace Attribute

	/// Attributes - A bitset of attributes.	/// Attributes - A bitset of attributes.

	typedef unsigned Attributes;	class Attributes {
		public:
		Attributes() : Bits(0) { }
		explicit Attributes(uint64_t Val) : Bits(Val) { }
		/implicit/ Attributes(Attribute::AttrConst Val) : Bits(Val.v) { }
		Attributes(const Attributes &Attrs) : Bits(Attrs.Bits) { }
		// This is a "safe bool() operator".
		operator const void *() const { return Bits ? this : 0; }
		bool isEmptyOrSingleton() const { return (Bits & (Bits - 1)) == 0; }
		Attributes &operator = (const Attributes &Attrs) {
		Bits = Attrs.Bits;
		return *this;
		}
		bool operator == (const Attributes &Attrs) const {
		return Bits == Attrs.Bits;
		}
		bool operator != (const Attributes &Attrs) const {
		return Bits != Attrs.Bits;
		}
		Attributes operator \| (const Attributes &Attrs) const {
		return Attributes(Bits \| Attrs.Bits);
		}
		Attributes operator & (const Attributes &Attrs) const {
		return Attributes(Bits & Attrs.Bits);
		}
		Attributes operator ^ (const Attributes &Attrs) const {
		return Attributes(Bits ^ Attrs.Bits);
		}
		Attributes &operator \|= (const Attributes &Attrs) {
		Bits \|= Attrs.Bits;
		return *this;
		}
		Attributes &operator &= (const Attributes &Attrs) {
		Bits &= Attrs.Bits;
		return *this;
		}
		Attributes operator ~ () const { return Attributes(~Bits); }
		uint64_t Raw() const { return Bits; }
		private:
		// Currently, we need less than 64 bits.
		uint64_t Bits;
		};

	namespace Attribute {	namespace Attribute {

	/// Function parameters and results can have attributes to indicate how the y	/// Function parameters and results can have attributes to indicate how the y
	/// should be treated by optimizations and code generation. This enumeratio n	/// should be treated by optimizations and code generation. This enumeratio n
	/// lists the attributes that can be associated with parameters, function	/// lists the attributes that can be associated with parameters, function
	/// results or the function itself.	/// results or the function itself.
	/// @brief Function attributes.	/// @brief Function attributes.


	const Attributes None = 0; ///< No attributes have been set	// We declare AttrConst objects that will be used throughout the code
	const Attributes ZExt = 1<<0; ///< Zero extended before/after call	// and also raw uint64_t objects with _i suffix to be used below for other
	const Attributes SExt = 1<<1; ///< Sign extended before/after call	// constant declarations. This is done to avoid static CTORs and at the sam
	const Attributes NoReturn = 1<<2; ///< Mark the function as not returning	e
	const Attributes InReg = 1<<3; ///< Force argument to be passed in reg	// time to keep type-safety of Attributes.
	ister	#define DECLARE_LLVM_ATTRIBUTE(name, value) \
	const Attributes StructRet = 1<<4; ///< Hidden pointer to structure to ret	const uint64_t name##_i = value; \
	urn	const AttrConst name = {value};
	const Attributes NoUnwind = 1<<5; ///< Function doesn't unwind stack
	const Attributes NoAlias = 1<<6; ///< Considered to not alias after call	DECLARE_LLVM_ATTRIBUTE(None,0) ///< No attributes have been set
	const Attributes ByVal = 1<<7; ///< Pass structure by value	DECLARE_LLVM_ATTRIBUTE(ZExt,1<<0) ///< Zero extended before/after call
	const Attributes Nest = 1<<8; ///< Nested function static chain	DECLARE_LLVM_ATTRIBUTE(SExt,1<<1) ///< Sign extended before/after call
	const Attributes ReadNone = 1<<9; ///< Function does not access memory	DECLARE_LLVM_ATTRIBUTE(NoReturn,1<<2) ///< Mark the function as not returni
	const Attributes ReadOnly = 1<<10; ///< Function only reads from memory	ng
	const Attributes NoInline = 1<<11; ///< inline=never	DECLARE_LLVM_ATTRIBUTE(InReg,1<<3) ///< Force argument to be passed in regi
	const Attributes AlwaysInline = 1<<12; ///< inline=always	ster
	const Attributes OptimizeForSize = 1<<13; ///< opt_size	DECLARE_LLVM_ATTRIBUTE(StructRet,1<<4) ///< Hidden pointer to structure to
	const Attributes StackProtect = 1<<14; ///< Stack protection.	return
	const Attributes StackProtectReq = 1<<15; ///< Stack protection required.	DECLARE_LLVM_ATTRIBUTE(NoUnwind,1<<5) ///< Function doesn't unwind stack
	const Attributes Alignment = 31<<16; ///< Alignment of parameter (5 bits)	DECLARE_LLVM_ATTRIBUTE(NoAlias,1<<6) ///< Considered to not alias after cal
		l
		DECLARE_LLVM_ATTRIBUTE(ByVal,1<<7) ///< Pass structure by value
		DECLARE_LLVM_ATTRIBUTE(Nest,1<<8) ///< Nested function static chain
		DECLARE_LLVM_ATTRIBUTE(ReadNone,1<<9) ///< Function does not access memory
		DECLARE_LLVM_ATTRIBUTE(ReadOnly,1<<10) ///< Function only reads from memory
		DECLARE_LLVM_ATTRIBUTE(NoInline,1<<11) ///< inline=never
		DECLARE_LLVM_ATTRIBUTE(AlwaysInline,1<<12) ///< inline=always
		DECLARE_LLVM_ATTRIBUTE(OptimizeForSize,1<<13) ///< opt_size
		DECLARE_LLVM_ATTRIBUTE(StackProtect,1<<14) ///< Stack protection.
		DECLARE_LLVM_ATTRIBUTE(StackProtectReq,1<<15) ///< Stack protection require
		d.
		DECLARE_LLVM_ATTRIBUTE(Alignment,31<<16) ///< Alignment of parameter (5 bit
		s)
	// stored as log2 of alignment with +1 bias	// stored as log2 of alignment with +1 bias
	// 0 means unaligned different from al ign 1	// 0 means unaligned different from al ign 1

	const Attributes NoCapture = 1<<21; ///< Function creates no aliases of poi	DECLARE_LLVM_ATTRIBUTE(NoCapture,1<<21) ///< Function creates no aliases of
	nter	pointer
	const Attributes NoRedZone = 1<<22; /// disable redzone	DECLARE_LLVM_ATTRIBUTE(NoRedZone,1<<22) /// disable redzone
	const Attributes NoImplicitFloat = 1<<23; /// disable implicit floating poi	DECLARE_LLVM_ATTRIBUTE(NoImplicitFloat,1<<23) /// disable implicit floating
	nt	point
	/// instructions.	/// instructions.
	const Attributes Naked = 1<<24; ///< Naked function	DECLARE_LLVM_ATTRIBUTE(Naked,1<<24) ///< Naked function
	const Attributes InlineHint = 1<<25; ///< source said inlining was	DECLARE_LLVM_ATTRIBUTE(InlineHint,1<<25) ///< source said inlining was
	///desirable	///desirable
	const Attributes StackAlignment = 7<<26; ///< Alignment of stack for	DECLARE_LLVM_ATTRIBUTE(StackAlignment,7<<26) ///< Alignment of stack for
	///function (3 bits) stored as lo	///function (3 bits) stored as l
	g2	og2
	///of alignment with +1 bias	///of alignment with +1 bias
	///0 means unaligned (different f	///0 means unaligned (different
	rom	from
	///alignstack(1))	///alignstack= {1))
	const Attributes ReturnsTwice = 1<<29; ///< Function can return twice	DECLARE_LLVM_ATTRIBUTE(ReturnsTwice,1<<29) ///< Function can return twice
	const Attributes UWTable = 1<<30; ///< Function must be in a unwind	DECLARE_LLVM_ATTRIBUTE(UWTable,1<<30) ///< Function must be in a unwind
	///table	///table
	const Attributes NonLazyBind = 1U<<31; ///< Function is called early and	DECLARE_LLVM_ATTRIBUTE(NonLazyBind,1U<<31) ///< Function is called early an
	/or	d/or
	/// often, so lazy binding isn't	/// often, so lazy binding isn'
	/// worthwhile.	t
		/// worthwhile.
		DECLARE_LLVM_ATTRIBUTE(AddressSafety,1ULL<<32) ///< Address safety checking
		is on.

		#undef DECLARE_LLVM_ATTRIBUTE

	/// Note that uwtable is about the ABI or the user mandating an entry in th e	/// Note that uwtable is about the ABI or the user mandating an entry in th e
	/// unwind table. The nounwind attribute is about an exception passing by t he	/// unwind table. The nounwind attribute is about an exception passing by t he
	/// function.	/// function.
	/// In a theoretical system that uses tables for profiling and sjlj for	/// In a theoretical system that uses tables for profiling and sjlj for
	/// exceptions, they would be fully independent. In a normal system that	/// exceptions, they would be fully independent. In a normal system that
	/// uses tables for both, the semantics are:	/// uses tables for both, the semantics are:
	/// nil = Needs an entry because an exception might pass by.	/// nil = Needs an entry because an exception might pass by.
	/// nounwind = No need for an entry	/// nounwind = No need for an entry
	/// uwtable = Needs an entry because the ABI says so and because	/// uwtable = Needs an entry because the ABI says so and because
	/// an exception might pass by.	/// an exception might pass by.
	/// uwtable + nounwind = Needs an entry because the ABI says so.	/// uwtable + nounwind = Needs an entry because the ABI says so.

	/// @brief Attributes that only apply to function parameters.	/// @brief Attributes that only apply to function parameters.

	const Attributes ParameterOnly = ByVal \| Nest \| StructRet \| NoCapture;	const AttrConst ParameterOnly = {ByVal_i \| Nest_i \|
		StructRet_i \| NoCapture_i};

	/// @brief Attributes that may be applied to the function itself. These ca nnot	/// @brief Attributes that may be applied to the function itself. These ca nnot
	/// be used on return values or function parameters.	/// be used on return values or function parameters.

	const Attributes FunctionOnly = NoReturn \| NoUnwind \| ReadNone \| ReadOnly \|	const AttrConst FunctionOnly = {NoReturn_i \| NoUnwind_i \| ReadNone_i \|
	NoInline \| AlwaysInline \| OptimizeForSize \| StackProtect \| StackProtectRe	ReadOnly_i \| NoInline_i \| AlwaysInline_i \| OptimizeForSize_i \|
	q \|	StackProtect_i \| StackProtectReq_i \| NoRedZone_i \| NoImplicitFloat_i \|
	NoRedZone \| NoImplicitFloat \| Naked \| InlineHint \| StackAlignment \|	Naked_i \| InlineHint_i \| StackAlignment_i \|
	UWTable \| NonLazyBind \| ReturnsTwice;	UWTable_i \| NonLazyBind_i \| ReturnsTwice_i \| AddressSafety_i};

	/// @brief Parameter attributes that do not apply to vararg call arguments.	/// @brief Parameter attributes that do not apply to vararg call arguments.

	const Attributes VarArgsIncompatible = StructRet;	const AttrConst VarArgsIncompatible = {StructRet_i};

	/// @brief Attributes that are mutually incompatible.	/// @brief Attributes that are mutually incompatible.

	const Attributes MutuallyIncompatible[4] = {	const AttrConst MutuallyIncompatible[4] = {
	ByVal \| InReg \| Nest \| StructRet,	{ByVal_i \| InReg_i \| Nest_i \| StructRet_i},
	ZExt \| SExt,	{ZExt_i \| SExt_i},
	ReadNone \| ReadOnly,	{ReadNone_i \| ReadOnly_i},
	NoInline \| AlwaysInline	{NoInline_i \| AlwaysInline_i}
	};	};

	/// @brief Which attributes cannot be applied to a type.	/// @brief Which attributes cannot be applied to a type.
	Attributes typeIncompatible(Type *Ty);	Attributes typeIncompatible(Type *Ty);

	/// This turns an int alignment (a power of 2, normally) into the	/// This turns an int alignment (a power of 2, normally) into the
	/// form used internally in Attributes.	/// form used internally in Attributes.
	inline Attributes constructAlignmentFromInt(unsigned i) {	inline Attributes constructAlignmentFromInt(unsigned i) {
	// Default alignment, allow the target to define how to align it.	// Default alignment, allow the target to define how to align it.
	if (i == 0)	if (i == 0)

	return 0;	return None;

	assert(isPowerOf2_32(i) && "Alignment must be a power of two.");	assert(isPowerOf2_32(i) && "Alignment must be a power of two.");
	assert(i <= 0x40000000 && "Alignment too large.");	assert(i <= 0x40000000 && "Alignment too large.");

	return (Log2_32(i)+1) << 16;	return Attributes((Log2_32(i)+1) << 16);
	}	}

	/// This returns the alignment field of an attribute as a byte alignment va lue.	/// This returns the alignment field of an attribute as a byte alignment va lue.
	inline unsigned getAlignmentFromAttrs(Attributes A) {	inline unsigned getAlignmentFromAttrs(Attributes A) {
	Attributes Align = A & Attribute::Alignment;	Attributes Align = A & Attribute::Alignment;

	if (Align == 0)	if (!Align)
	return 0;	return 0;


	return 1U << ((Align >> 16) - 1);	return 1U << ((Align.Raw() >> 16) - 1);
	}	}

	/// This turns an int stack alignment (which must be a power of 2) into	/// This turns an int stack alignment (which must be a power of 2) into
	/// the form used internally in Attributes.	/// the form used internally in Attributes.
	inline Attributes constructStackAlignmentFromInt(unsigned i) {	inline Attributes constructStackAlignmentFromInt(unsigned i) {
	// Default alignment, allow the target to define how to align it.	// Default alignment, allow the target to define how to align it.
	if (i == 0)	if (i == 0)

	return 0;	return None;

	assert(isPowerOf2_32(i) && "Alignment must be a power of two.");	assert(isPowerOf2_32(i) && "Alignment must be a power of two.");
	assert(i <= 0x100 && "Alignment too large.");	assert(i <= 0x100 && "Alignment too large.");

	return (Log2_32(i)+1) << 26;	return Attributes((Log2_32(i)+1) << 26);
	}	}

	/// This returns the stack alignment field of an attribute as a byte alignm ent	/// This returns the stack alignment field of an attribute as a byte alignm ent
	/// value.	/// value.
	inline unsigned getStackAlignmentFromAttrs(Attributes A) {	inline unsigned getStackAlignmentFromAttrs(Attributes A) {
	Attributes StackAlign = A & Attribute::StackAlignment;	Attributes StackAlign = A & Attribute::StackAlignment;

	if (StackAlign == 0)	if (!StackAlign)
	return 0;	return 0;


	return 1U << ((StackAlign >> 26) - 1);	return 1U << ((StackAlign.Raw() >> 26) - 1);
	}	}

	/// The set of Attributes set in Attributes is converted to a	/// The set of Attributes set in Attributes is converted to a
	/// string of equivalent mnemonics. This is, presumably, for writing out	/// string of equivalent mnemonics. This is, presumably, for writing out
	/// the mnemonics for the assembly writer.	/// the mnemonics for the assembly writer.
	/// @brief Convert attribute bits to text	/// @brief Convert attribute bits to text
	std::string getAsString(Attributes Attrs);	std::string getAsString(Attributes Attrs);
	} // end namespace Attribute	} // end namespace Attribute

	/// This is just a pair of values to associate a set of attributes	/// This is just a pair of values to associate a set of attributes

	skipping to change at line 244	skipping to change at line 314
	}	}

	/// getFnAttributes - The function attributes are returned.	/// getFnAttributes - The function attributes are returned.
	Attributes getFnAttributes() const {	Attributes getFnAttributes() const {
	return getAttributes(~0U);	return getAttributes(~0U);
	}	}

	/// paramHasAttr - Return true if the specified parameter index has the	/// paramHasAttr - Return true if the specified parameter index has the
	/// specified attribute set.	/// specified attribute set.
	bool paramHasAttr(unsigned Idx, Attributes Attr) const {	bool paramHasAttr(unsigned Idx, Attributes Attr) const {

	return (getAttributes(Idx) & Attr) != 0;	return getAttributes(Idx) & Attr;
	}	}

	/// getParamAlignment - Return the alignment for the specified function	/// getParamAlignment - Return the alignment for the specified function
	/// parameter.	/// parameter.
	unsigned getParamAlignment(unsigned Idx) const {	unsigned getParamAlignment(unsigned Idx) const {
	return Attribute::getAlignmentFromAttrs(getAttributes(Idx));	return Attribute::getAlignmentFromAttrs(getAttributes(Idx));
	}	}

	/// hasAttrSomewhere - Return true if the specified attribute is set for at	/// hasAttrSomewhere - Return true if the specified attribute is set for at
	/// least one parameter or for the return value.	/// least one parameter or for the return value.

End of changes. 17 change blocks.
	65 lines changed or deleted	141 lines changed or added

	AutoUpgrade.h	AutoUpgrade.h

	skipping to change at line 42	skipping to change at line 42

	/// This is an auto-upgrade hook for any old intrinsic function syntaxes	/// This is an auto-upgrade hook for any old intrinsic function syntaxes
	/// which need to have both the function updated as well as all calls upd ated	/// which need to have both the function updated as well as all calls upd ated
	/// to the new function. This should only be run in a post-processing fas hion	/// to the new function. This should only be run in a post-processing fas hion
	/// so that it can update all calls to the old function.	/// so that it can update all calls to the old function.
	void UpgradeCallsToIntrinsic(Function* F);	void UpgradeCallsToIntrinsic(Function* F);

	/// This checks for global variables which should be upgraded. It returns true	/// This checks for global variables which should be upgraded. It returns true
	/// if it requires upgrading.	/// if it requires upgrading.
	bool UpgradeGlobalVariable(GlobalVariable *GV);	bool UpgradeGlobalVariable(GlobalVariable *GV);


	/// This function checks debug info intrinsics. If an intrinsic is invali
	d
	/// then this function simply removes the intrinsic.
	void CheckDebugInfoIntrinsics(Module *M);

	/// This function upgrades the old pre-3.0 exception handling system to t
	he
	/// new one. N.B. This will be removed in 3.1.
	void UpgradeExceptionHandling(Module *M);
	} // End llvm namespace	} // End llvm namespace

	#endif	#endif

End of changes. 1 change blocks.
	10 lines changed or deleted	0 lines changed or added

	Binary.h	Binary.h

	skipping to change at line 40	skipping to change at line 40
	Binary(const Binary &other); // = delete	Binary(const Binary &other); // = delete

	unsigned int TypeID;	unsigned int TypeID;

	protected:	protected:
	MemoryBuffer *Data;	MemoryBuffer *Data;

	Binary(unsigned int Type, MemoryBuffer *Source);	Binary(unsigned int Type, MemoryBuffer *Source);

	enum {	enum {

	isArchive,	ID_Archive,

	// Object and children.	// Object and children.

	isObject,	ID_StartObjects,
	isCOFF,	ID_COFF,
	isELF,	ID_ELF32L, // ELF 32-bit, little endian
	isMachO,	ID_ELF32B, // ELF 32-bit, big endian
	lastObject	ID_ELF64L, // ELF 64-bit, little endian
		ID_ELF64B, // ELF 64-bit, big endian
		ID_MachO,
		ID_EndObjects
	};	};


		static inline unsigned int getELFType(bool isLittleEndian, bool is64Bits)
		{
		if (isLittleEndian)
		return is64Bits ? ID_ELF64L : ID_ELF32L;
		else
		return is64Bits ? ID_ELF64B : ID_ELF32B;
		}

	public:	public:
	virtual ~Binary();	virtual ~Binary();

	StringRef getData() const;	StringRef getData() const;
	StringRef getFileName() const;	StringRef getFileName() const;

	// Cast methods.	// Cast methods.
	unsigned int getType() const { return TypeID; }	unsigned int getType() const { return TypeID; }
	static inline bool classof(const Binary *v) { return true; }	static inline bool classof(const Binary *v) { return true; }


		// Convenience methods
		bool isObject() const {
		return TypeID > ID_StartObjects && TypeID < ID_EndObjects;
		}

		bool isArchive() const {
		return TypeID == ID_Archive;
		}

		bool isELF() const {
		return TypeID >= ID_ELF32L && TypeID <= ID_ELF64B;
		}

		bool isMachO() const {
		return TypeID == ID_MachO;
		}

		bool isCOFF() const {
		return TypeID == ID_COFF;
		}
	};	};


		/// @brief Create a Binary from Source, autodetecting the file type.
		///
		/// @param Source The data to create the Binary from. Ownership is transfer
		ed
		/// to Result if successful. If an error is returned, Source is dest
		royed
		/// by createBinary before returning.
		/// @param Result A pointer to the resulting Binary if no error occured.
	error_code createBinary(MemoryBuffer *Source, OwningPtr<Binary> &Result);	error_code createBinary(MemoryBuffer *Source, OwningPtr<Binary> &Result);


	error_code createBinary(StringRef Path, OwningPtr<Binary> &Result);	error_code createBinary(StringRef Path, OwningPtr<Binary> &Result);

	}	}
	}	}

	#endif	#endif

End of changes. 6 change blocks.
	7 lines changed or deleted	47 lines changed or added

	BitCodes.h	BitCodes.h

	skipping to change at line 23	skipping to change at line 23
	// new features are added, they should have values added at the end of the	// new features are added, they should have values added at the end of the
	// respective lists.	// respective lists.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_BITCODE_BITCODES_H	#ifndef LLVM_BITCODE_BITCODES_H
	#define LLVM_BITCODE_BITCODES_H	#define LLVM_BITCODE_BITCODES_H

	#include "llvm/ADT/SmallVector.h"	#include "llvm/ADT/SmallVector.h"
	#include "llvm/Support/DataTypes.h"	#include "llvm/Support/DataTypes.h"

		#include "llvm/Support/ErrorHandling.h"
	#include <cassert>	#include <cassert>

	namespace llvm {	namespace llvm {
	namespace bitc {	namespace bitc {
	enum StandardWidths {	enum StandardWidths {
	BlockIDWidth = 8, // We use VBR-8 for block IDs.	BlockIDWidth = 8, // We use VBR-8 for block IDs.
	CodeLenWidth = 4, // Codelen are VBR-4.	CodeLenWidth = 4, // Codelen are VBR-4.
	BlockSizeWidth = 32 // BlockSize up to 2^32 32-bit words = 16GB per bl ock.	BlockSizeWidth = 32 // BlockSize up to 2^32 32-bit words = 16GB per bl ock.
	};	};


	skipping to change at line 117	skipping to change at line 118
	// Accessors for encoding info.	// Accessors for encoding info.
	Encoding getEncoding() const { assert(isEncoding()); return (Encoding)Enc ; }	Encoding getEncoding() const { assert(isEncoding()); return (Encoding)Enc ; }
	uint64_t getEncodingData() const {	uint64_t getEncodingData() const {
	assert(isEncoding() && hasEncodingData());	assert(isEncoding() && hasEncodingData());
	return Val;	return Val;
	}	}

	bool hasEncodingData() const { return hasEncodingData(getEncoding()); }	bool hasEncodingData() const { return hasEncodingData(getEncoding()); }
	static bool hasEncodingData(Encoding E) {	static bool hasEncodingData(Encoding E) {
	switch (E) {	switch (E) {

	default: assert(0 && "Unknown encoding");
	case Fixed:	case Fixed:
	case VBR:	case VBR:
	return true;	return true;
	case Array:	case Array:
	case Char6:	case Char6:
	case Blob:	case Blob:
	return false;	return false;
	}	}

		llvm_unreachable("Invalid encoding");
	}	}

	/// isChar6 - Return true if this character is legal in the Char6 encodin g.	/// isChar6 - Return true if this character is legal in the Char6 encodin g.
	static bool isChar6(char C) {	static bool isChar6(char C) {
	if (C >= 'a' && C <= 'z') return true;	if (C >= 'a' && C <= 'z') return true;
	if (C >= 'A' && C <= 'Z') return true;	if (C >= 'A' && C <= 'Z') return true;
	if (C >= '0' && C <= '9') return true;	if (C >= '0' && C <= '9') return true;
	if (C == '.' \|\| C == '_') return true;	if (C == '.' \|\| C == '_') return true;
	return false;	return false;
	}	}
	static unsigned EncodeChar6(char C) {	static unsigned EncodeChar6(char C) {
	if (C >= 'a' && C <= 'z') return C-'a';	if (C >= 'a' && C <= 'z') return C-'a';
	if (C >= 'A' && C <= 'Z') return C-'A'+26;	if (C >= 'A' && C <= 'Z') return C-'A'+26;
	if (C >= '0' && C <= '9') return C-'0'+26+26;	if (C >= '0' && C <= '9') return C-'0'+26+26;
	if (C == '.') return 62;	if (C == '.') return 62;
	if (C == '_') return 63;	if (C == '_') return 63;

	assert(0 && "Not a value Char6 character!");	llvm_unreachable("Not a value Char6 character!");
	return 0;
	}	}

	static char DecodeChar6(unsigned V) {	static char DecodeChar6(unsigned V) {
	assert((V & ~63) == 0 && "Not a Char6 encoded character!");	assert((V & ~63) == 0 && "Not a Char6 encoded character!");
	if (V < 26) return V+'a';	if (V < 26) return V+'a';
	if (V < 26+26) return V-26+'A';	if (V < 26+26) return V-26+'A';
	if (V < 26+26+10) return V-26-26+'0';	if (V < 26+26+10) return V-26-26+'0';
	if (V == 62) return '.';	if (V == 62) return '.';
	if (V == 63) return '_';	if (V == 63) return '_';

	assert(0 && "Not a value Char6 character!");	llvm_unreachable("Not a value Char6 character!");
	return ' ';
	}	}

	};	};


		template <> struct isPodLike<BitCodeAbbrevOp> { static const bool value=tru
		e; };

	/// BitCodeAbbrev - This class represents an abbreviation record. An	/// BitCodeAbbrev - This class represents an abbreviation record. An
	/// abbreviation allows a complex record that has redundancy to be stored i n a	/// abbreviation allows a complex record that has redundancy to be stored i n a
	/// specialized format instead of the fully-general, fully-vbr, format.	/// specialized format instead of the fully-general, fully-vbr, format.
	class BitCodeAbbrev {	class BitCodeAbbrev {

	SmallVector<BitCodeAbbrevOp, 8> OperandList;	SmallVector<BitCodeAbbrevOp, 32> OperandList;
	unsigned char RefCount; // Number of things using this.	unsigned char RefCount; // Number of things using this.
	~BitCodeAbbrev() {}	~BitCodeAbbrev() {}
	public:	public:
	BitCodeAbbrev() : RefCount(1) {}	BitCodeAbbrev() : RefCount(1) {}

	void addRef() { ++RefCount; }	void addRef() { ++RefCount; }
	void dropRef() { if (--RefCount == 0) delete this; }	void dropRef() { if (--RefCount == 0) delete this; }

	unsigned getNumOperandInfos() const {	unsigned getNumOperandInfos() const {
	return static_cast<unsigned>(OperandList.size());	return static_cast<unsigned>(OperandList.size());

End of changes. 7 change blocks.
	6 lines changed or deleted	8 lines changed or added

	BitReader.h	BitReader.h

	skipping to change at line 28	skipping to change at line 28

	#ifndef LLVM_C_BITCODEREADER_H	#ifndef LLVM_C_BITCODEREADER_H
	#define LLVM_C_BITCODEREADER_H	#define LLVM_C_BITCODEREADER_H

	#include "llvm-c/Core.h"	#include "llvm-c/Core.h"

	#ifdef __cplusplus	#ifdef __cplusplus
	extern "C" {	extern "C" {
	#endif	#endif


		/**
		* @defgroup LLVMCBitReader Bit Reader
		* @ingroup LLVMC
		*
		* @{
		*/

	/* Builds a module from the bitcode in the specified memory buffer, returni ng a	/* Builds a module from the bitcode in the specified memory buffer, returni ng a
	reference to the module via the OutModule parameter. Returns 0 on succes s.	reference to the module via the OutModule parameter. Returns 0 on succes s.
	Optionally returns a human-readable error message via OutMessage. */	Optionally returns a human-readable error message via OutMessage. */
	LLVMBool LLVMParseBitcode(LLVMMemoryBufferRef MemBuf,	LLVMBool LLVMParseBitcode(LLVMMemoryBufferRef MemBuf,
	LLVMModuleRef OutModule, char *OutMessage);	LLVMModuleRef OutModule, char *OutMessage);

	LLVMBool LLVMParseBitcodeInContext(LLVMContextRef ContextRef,	LLVMBool LLVMParseBitcodeInContext(LLVMContextRef ContextRef,
	LLVMMemoryBufferRef MemBuf,	LLVMMemoryBufferRef MemBuf,
	LLVMModuleRef OutModule, char *OutMess age);	LLVMModuleRef OutModule, char *OutMess age);


	skipping to change at line 60	skipping to change at line 67
	LLVMBool LLVMGetBitcodeModuleProviderInContext(LLVMContextRef ContextRef,	LLVMBool LLVMGetBitcodeModuleProviderInContext(LLVMContextRef ContextRef,
	LLVMMemoryBufferRef MemBuf,	LLVMMemoryBufferRef MemBuf,
	LLVMModuleProviderRef *OutMP ,	LLVMModuleProviderRef *OutMP ,
	char **OutMessage);	char **OutMessage);

	/** Deprecated: Use LLVMGetBitcodeModule instead. */	/** Deprecated: Use LLVMGetBitcodeModule instead. */
	LLVMBool LLVMGetBitcodeModuleProvider(LLVMMemoryBufferRef MemBuf,	LLVMBool LLVMGetBitcodeModuleProvider(LLVMMemoryBufferRef MemBuf,
	LLVMModuleProviderRef *OutMP,	LLVMModuleProviderRef *OutMP,
	char **OutMessage);	char **OutMessage);


		/**
		* @}
		*/

	#ifdef __cplusplus	#ifdef __cplusplus
	}	}
	#endif	#endif

	#endif	#endif

End of changes. 2 change blocks.
	0 lines changed or deleted	11 lines changed or added

	BitVector.h	BitVector.h

	skipping to change at line 17	skipping to change at line 17
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	//	//
	// This file implements the BitVector class.	// This file implements the BitVector class.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_ADT_BITVECTOR_H	#ifndef LLVM_ADT_BITVECTOR_H
	#define LLVM_ADT_BITVECTOR_H	#define LLVM_ADT_BITVECTOR_H


		#include "llvm/Support/ErrorHandling.h"
	#include "llvm/Support/MathExtras.h"	#include "llvm/Support/MathExtras.h"
	#include <algorithm>	#include <algorithm>
	#include <cassert>	#include <cassert>
	#include <climits>	#include <climits>
	#include <cstdlib>	#include <cstdlib>

	#include <cstring>

	namespace llvm {	namespace llvm {

	class BitVector {	class BitVector {
	typedef unsigned long BitWord;	typedef unsigned long BitWord;

	enum { BITWORD_SIZE = (unsigned)sizeof(BitWord) * CHAR_BIT };	enum { BITWORD_SIZE = (unsigned)sizeof(BitWord) * CHAR_BIT };

	BitWord *Bits; // Actual bits.	BitWord *Bits; // Actual bits.
	unsigned Size; // Size of bitvector in bits.	unsigned Size; // Size of bitvector in bits.

	skipping to change at line 118	skipping to change at line 118

	/// count - Returns the number of bits which are set.	/// count - Returns the number of bits which are set.
	unsigned count() const {	unsigned count() const {
	unsigned NumBits = 0;	unsigned NumBits = 0;
	for (unsigned i = 0; i < NumBitWords(size()); ++i)	for (unsigned i = 0; i < NumBitWords(size()); ++i)
	if (sizeof(BitWord) == 4)	if (sizeof(BitWord) == 4)
	NumBits += CountPopulation_32((uint32_t)Bits[i]);	NumBits += CountPopulation_32((uint32_t)Bits[i]);
	else if (sizeof(BitWord) == 8)	else if (sizeof(BitWord) == 8)
	NumBits += CountPopulation_64(Bits[i]);	NumBits += CountPopulation_64(Bits[i]);
	else	else

	assert(0 && "Unsupported!");	llvm_unreachable("Unsupported!");
	return NumBits;	return NumBits;
	}	}

	/// any - Returns true if any bit is set.	/// any - Returns true if any bit is set.
	bool any() const {	bool any() const {
	for (unsigned i = 0; i < NumBitWords(size()); ++i)	for (unsigned i = 0; i < NumBitWords(size()); ++i)
	if (Bits[i] != 0)	if (Bits[i] != 0)
	return true;	return true;
	return false;	return false;
	}	}

	skipping to change at line 148	skipping to change at line 148
	return !any();	return !any();
	}	}

	/// find_first - Returns the index of the first set bit, -1 if none	/// find_first - Returns the index of the first set bit, -1 if none
	/// of the bits are set.	/// of the bits are set.
	int find_first() const {	int find_first() const {
	for (unsigned i = 0; i < NumBitWords(size()); ++i)	for (unsigned i = 0; i < NumBitWords(size()); ++i)
	if (Bits[i] != 0) {	if (Bits[i] != 0) {
	if (sizeof(BitWord) == 4)	if (sizeof(BitWord) == 4)
	return i * BITWORD_SIZE + CountTrailingZeros_32((uint32_t)Bits[i] );	return i * BITWORD_SIZE + CountTrailingZeros_32((uint32_t)Bits[i] );

	else if (sizeof(BitWord) == 8)	if (sizeof(BitWord) == 8)
	return i * BITWORD_SIZE + CountTrailingZeros_64(Bits[i]);	return i * BITWORD_SIZE + CountTrailingZeros_64(Bits[i]);

	else	llvm_unreachable("Unsupported!");
	assert(0 && "Unsupported!");
	}	}
	return -1;	return -1;
	}	}

	/// find_next - Returns the index of the next set bit following the	/// find_next - Returns the index of the next set bit following the
	/// "Prev" bit. Returns -1 if the next set bit is not found.	/// "Prev" bit. Returns -1 if the next set bit is not found.
	int find_next(unsigned Prev) const {	int find_next(unsigned Prev) const {
	++Prev;	++Prev;
	if (Prev >= Size)	if (Prev >= Size)
	return -1;	return -1;

	unsigned WordPos = Prev / BITWORD_SIZE;	unsigned WordPos = Prev / BITWORD_SIZE;
	unsigned BitPos = Prev % BITWORD_SIZE;	unsigned BitPos = Prev % BITWORD_SIZE;
	BitWord Copy = Bits[WordPos];	BitWord Copy = Bits[WordPos];
	// Mask off previous bits.	// Mask off previous bits.
	Copy &= ~0L << BitPos;	Copy &= ~0L << BitPos;

	if (Copy != 0) {	if (Copy != 0) {
	if (sizeof(BitWord) == 4)	if (sizeof(BitWord) == 4)
	return WordPos * BITWORD_SIZE + CountTrailingZeros_32((uint32_t)Cop y);	return WordPos * BITWORD_SIZE + CountTrailingZeros_32((uint32_t)Cop y);

	else if (sizeof(BitWord) == 8)	if (sizeof(BitWord) == 8)
	return WordPos * BITWORD_SIZE + CountTrailingZeros_64(Copy);	return WordPos * BITWORD_SIZE + CountTrailingZeros_64(Copy);

	else	llvm_unreachable("Unsupported!");
	assert(0 && "Unsupported!");
	}	}

	// Check subsequent words.	// Check subsequent words.
	for (unsigned i = WordPos+1; i < NumBitWords(size()); ++i)	for (unsigned i = WordPos+1; i < NumBitWords(size()); ++i)
	if (Bits[i] != 0) {	if (Bits[i] != 0) {
	if (sizeof(BitWord) == 4)	if (sizeof(BitWord) == 4)
	return i * BITWORD_SIZE + CountTrailingZeros_32((uint32_t)Bits[i] );	return i * BITWORD_SIZE + CountTrailingZeros_32((uint32_t)Bits[i] );

	else if (sizeof(BitWord) == 8)	if (sizeof(BitWord) == 8)
	return i * BITWORD_SIZE + CountTrailingZeros_64(Bits[i]);	return i * BITWORD_SIZE + CountTrailingZeros_64(Bits[i]);

	else	llvm_unreachable("Unsupported!");
	assert(0 && "Unsupported!");
	}	}
	return -1;	return -1;
	}	}

	/// clear - Clear all bits.	/// clear - Clear all bits.
	void clear() {	void clear() {
	Size = 0;	Size = 0;
	}	}

	/// resize - Grow or shrink the bitvector.	/// resize - Grow or shrink the bitvector.

	skipping to change at line 320	skipping to change at line 317

	// Any bits that are just in this bitvector become zero, because they a ren't	// Any bits that are just in this bitvector become zero, because they a ren't
	// in the RHS bit vector. Any words only in RHS are ignored because th ey	// in the RHS bit vector. Any words only in RHS are ignored because th ey
	// are already zero in the LHS.	// are already zero in the LHS.
	for (; i != ThisWords; ++i)	for (; i != ThisWords; ++i)
	Bits[i] = 0;	Bits[i] = 0;

	return *this;	return *this;
	}	}


		// reset - Reset bits that are set in RHS. Same as *this &= ~RHS.
		BitVector &reset(const BitVector &RHS) {
		unsigned ThisWords = NumBitWords(size());
		unsigned RHSWords = NumBitWords(RHS.size());
		unsigned i;
		for (i = 0; i != std::min(ThisWords, RHSWords); ++i)
		Bits[i] &= ~RHS.Bits[i];
		return *this;
		}

	BitVector &operator\|=(const BitVector &RHS) {	BitVector &operator\|=(const BitVector &RHS) {
	if (size() < RHS.size())	if (size() < RHS.size())
	resize(RHS.size());	resize(RHS.size());
	for (size_t i = 0, e = NumBitWords(RHS.size()); i != e; ++i)	for (size_t i = 0, e = NumBitWords(RHS.size()); i != e; ++i)
	Bits[i] \|= RHS.Bits[i];	Bits[i] \|= RHS.Bits[i];
	return *this;	return *this;
	}	}

	BitVector &operator^=(const BitVector &RHS) {	BitVector &operator^=(const BitVector &RHS) {
	if (size() < RHS.size())	if (size() < RHS.size())

	skipping to change at line 367	skipping to change at line 374

	return *this;	return *this;
	}	}

	void swap(BitVector &RHS) {	void swap(BitVector &RHS) {
	std::swap(Bits, RHS.Bits);	std::swap(Bits, RHS.Bits);
	std::swap(Size, RHS.Size);	std::swap(Size, RHS.Size);
	std::swap(Capacity, RHS.Capacity);	std::swap(Capacity, RHS.Capacity);
	}	}


		//===--------------------------------------------------------------------
		===//
		// Portable bit mask operations.
		//===--------------------------------------------------------------------
		===//
		//
		// These methods all operate on arrays of uint32_t, each holding 32 bits.
		The
		// fixed word size makes it easier to work with literal bit vector consta
		nts
		// in portable code.
		//
		// The LSB in each word is the lowest numbered bit. The size of a portab
		le
		// bit mask is always a whole multiple of 32 bits. If no bit mask size i
		s
		// given, the bit mask is assumed to cover the entire BitVector.

		/// setBitsInMask - Add '1' bits from Mask to this vector. Don't resize.
		/// This computes "*this \|= Mask".
		void setBitsInMask(const uint32_t *Mask, unsigned MaskWords = ~0u) {
		applyMask<true, false>(Mask, MaskWords);
		}

		/// clearBitsInMask - Clear any bits in this vector that are set in Mask.
		/// Don't resize. This computes "*this &= ~Mask".
		void clearBitsInMask(const uint32_t *Mask, unsigned MaskWords = ~0u) {
		applyMask<false, false>(Mask, MaskWords);
		}

		/// setBitsNotInMask - Add a bit to this vector for every '0' bit in Mask
		.
		/// Don't resize. This computes "*this \|= ~Mask".
		void setBitsNotInMask(const uint32_t *Mask, unsigned MaskWords = ~0u) {
		applyMask<true, true>(Mask, MaskWords);
		}

		/// clearBitsNotInMask - Clear a bit in this vector for every '0' bit in
		Mask.
		/// Don't resize. This computes "*this &= Mask".
		void clearBitsNotInMask(const uint32_t *Mask, unsigned MaskWords = ~0u) {
		applyMask<false, true>(Mask, MaskWords);
		}

	private:	private:
	unsigned NumBitWords(unsigned S) const {	unsigned NumBitWords(unsigned S) const {
	return (S + BITWORD_SIZE-1) / BITWORD_SIZE;	return (S + BITWORD_SIZE-1) / BITWORD_SIZE;
	}	}

	// Set the unused bits in the high words.	// Set the unused bits in the high words.
	void set_unused_bits(bool t = true) {	void set_unused_bits(bool t = true) {
	// Set high words first.	// Set high words first.
	unsigned UsedWords = NumBitWords(Size);	unsigned UsedWords = NumBitWords(Size);
	if (Capacity > UsedWords)	if (Capacity > UsedWords)

	skipping to change at line 402	skipping to change at line 445
	void grow(unsigned NewSize) {	void grow(unsigned NewSize) {
	Capacity = std::max(NumBitWords(NewSize), Capacity * 2);	Capacity = std::max(NumBitWords(NewSize), Capacity * 2);
	Bits = (BitWord )std::realloc(Bits, Capacity sizeof(BitWord));	Bits = (BitWord )std::realloc(Bits, Capacity sizeof(BitWord));

	clear_unused_bits();	clear_unused_bits();
	}	}

	void init_words(BitWord *B, unsigned NumWords, bool t) {	void init_words(BitWord *B, unsigned NumWords, bool t) {
	memset(B, 0 - (int)t, NumWords*sizeof(BitWord));	memset(B, 0 - (int)t, NumWords*sizeof(BitWord));
	}	}


		template<bool AddBits, bool InvertMask>
		void applyMask(const uint32_t *Mask, unsigned MaskWords) {
		assert(BITWORD_SIZE % 32 == 0 && "Unsupported BitWord size.");
		MaskWords = std::min(MaskWords, (size() + 31) / 32);
		const unsigned Scale = BITWORD_SIZE / 32;
		unsigned i;
		for (i = 0; MaskWords >= Scale; ++i, MaskWords -= Scale) {
		BitWord BW = Bits[i];
		// This inner loop should unroll completely when BITWORD_SIZE > 32.
		for (unsigned b = 0; b != BITWORD_SIZE; b += 32) {
		uint32_t M = *Mask++;
		if (InvertMask) M = ~M;
		if (AddBits) BW \|= BitWord(M) << b;
		else BW &= ~(BitWord(M) << b);
		}
		Bits[i] = BW;
		}
		for (unsigned b = 0; MaskWords; b += 32, --MaskWords) {
		uint32_t M = *Mask++;
		if (InvertMask) M = ~M;
		if (AddBits) Bits[i] \|= BitWord(M) << b;
		else Bits[i] &= ~(BitWord(M) << b);
		}
		if (AddBits)
		clear_unused_bits();
		}
	};	};

	inline BitVector operator&(const BitVector &LHS, const BitVector &RHS) {	inline BitVector operator&(const BitVector &LHS, const BitVector &RHS) {
	BitVector Result(LHS);	BitVector Result(LHS);
	Result &= RHS;	Result &= RHS;
	return Result;	return Result;
	}	}

	inline BitVector operator\|(const BitVector &LHS, const BitVector &RHS) {	inline BitVector operator\|(const BitVector &LHS, const BitVector &RHS) {
	BitVector Result(LHS);	BitVector Result(LHS);

End of changes. 12 change blocks.
	11 lines changed or deleted	89 lines changed or added

	BitWriter.h	BitWriter.h

	skipping to change at line 28	skipping to change at line 28

	#ifndef LLVM_C_BITCODEWRITER_H	#ifndef LLVM_C_BITCODEWRITER_H
	#define LLVM_C_BITCODEWRITER_H	#define LLVM_C_BITCODEWRITER_H

	#include "llvm-c/Core.h"	#include "llvm-c/Core.h"

	#ifdef __cplusplus	#ifdef __cplusplus
	extern "C" {	extern "C" {
	#endif	#endif


		/**
		* @defgroup LLVMCBitWriter Bit Writer
		* @ingroup LLVMC
		*
		* @{
		*/

	/===-- Operations on modules --------------------------------------------- ===/	/===-- Operations on modules --------------------------------------------- ===/

	/** Writes a module to the specified path. Returns 0 on success. */	/** Writes a module to the specified path. Returns 0 on success. */
	int LLVMWriteBitcodeToFile(LLVMModuleRef M, const char *Path);	int LLVMWriteBitcodeToFile(LLVMModuleRef M, const char *Path);

	/** Writes a module to an open file descriptor. Returns 0 on success. */	/** Writes a module to an open file descriptor. Returns 0 on success. */
	int LLVMWriteBitcodeToFD(LLVMModuleRef M, int FD, int ShouldClose,	int LLVMWriteBitcodeToFD(LLVMModuleRef M, int FD, int ShouldClose,
	int Unbuffered);	int Unbuffered);

	/** Deprecated for LLVMWriteBitcodeToFD. Writes a module to an open file	/** Deprecated for LLVMWriteBitcodeToFD. Writes a module to an open file
	descriptor. Returns 0 on success. Closes the Handle. */	descriptor. Returns 0 on success. Closes the Handle. */
	int LLVMWriteBitcodeToFileHandle(LLVMModuleRef M, int Handle);	int LLVMWriteBitcodeToFileHandle(LLVMModuleRef M, int Handle);


		/**
		* @}
		*/

	#ifdef __cplusplus	#ifdef __cplusplus
	}	}
	#endif	#endif

	#endif	#endif

End of changes. 2 change blocks.
	0 lines changed or deleted	11 lines changed or added

	BitstreamReader.h	BitstreamReader.h

	skipping to change at line 18	skipping to change at line 18
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	//	//
	// This header defines the BitstreamReader class. This class can be used t o	// This header defines the BitstreamReader class. This class can be used t o
	// read an arbitrary bitstream, regardless of its contents.	// read an arbitrary bitstream, regardless of its contents.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef BITSTREAM_READER_H	#ifndef BITSTREAM_READER_H
	#define BITSTREAM_READER_H	#define BITSTREAM_READER_H


		#include "llvm/ADT/OwningPtr.h"
	#include "llvm/Bitcode/BitCodes.h"	#include "llvm/Bitcode/BitCodes.h"

		#include "llvm/Support/Endian.h"
		#include "llvm/Support/StreamableMemoryObject.h"
	#include <climits>	#include <climits>
	#include <string>	#include <string>
	#include <vector>	#include <vector>

	namespace llvm {	namespace llvm {

	class Deserializer;	class Deserializer;

	class BitstreamReader {	class BitstreamReader {
	public:	public:
	/// BlockInfo - This contains information emitted to BLOCKINFO_BLOCK bloc ks.	/// BlockInfo - This contains information emitted to BLOCKINFO_BLOCK bloc ks.
	/// These describe abbreviations that all blocks of the specified ID inhe rit.	/// These describe abbreviations that all blocks of the specified ID inhe rit.
	struct BlockInfo {	struct BlockInfo {
	unsigned BlockID;	unsigned BlockID;
	std::vector<BitCodeAbbrev*> Abbrevs;	std::vector<BitCodeAbbrev*> Abbrevs;
	std::string Name;	std::string Name;

	std::vector<std::pair<unsigned, std::string> > RecordNames;	std::vector<std::pair<unsigned, std::string> > RecordNames;
	};	};
	private:	private:

	/// FirstChar/LastChar - This remembers the first and last bytes of the	OwningPtr<StreamableMemoryObject> BitcodeBytes;
	/// stream.
	const unsigned char FirstChar, LastChar;

	std::vector<BlockInfo> BlockInfoRecords;	std::vector<BlockInfo> BlockInfoRecords;

	/// IgnoreBlockInfoNames - This is set to true if we don't care about the	/// IgnoreBlockInfoNames - This is set to true if we don't care about the
	/// block/record name information in the BlockInfo block. Only llvm-bcana lyzer	/// block/record name information in the BlockInfo block. Only llvm-bcana lyzer
	/// uses this.	/// uses this.
	bool IgnoreBlockInfoNames;	bool IgnoreBlockInfoNames;


	BitstreamReader(const BitstreamReader&); // NOT IMPLEMENTED	BitstreamReader(const BitstreamReader&); // DO NOT IMPLEMENT
	void operator=(const BitstreamReader&); // NOT IMPLEMENTED	void operator=(const BitstreamReader&); // DO NOT IMPLEMENT
	public:	public:

	BitstreamReader() : FirstChar(0), LastChar(0), IgnoreBlockInfoNames(true) {	BitstreamReader() : IgnoreBlockInfoNames(true) {
	}	}

	BitstreamReader(const unsigned char Start, const unsigned char End) {	BitstreamReader(const unsigned char Start, const unsigned char End) {
	IgnoreBlockInfoNames = true;	IgnoreBlockInfoNames = true;
	init(Start, End);	init(Start, End);
	}	}


		BitstreamReader(StreamableMemoryObject *bytes) {
		BitcodeBytes.reset(bytes);
		}

	void init(const unsigned char Start, const unsigned char End) {	void init(const unsigned char Start, const unsigned char End) {

	FirstChar = Start;
	LastChar = End;
	assert(((End-Start) & 3) == 0 &&"Bitcode stream not a multiple of 4 byt es");	assert(((End-Start) & 3) == 0 &&"Bitcode stream not a multiple of 4 byt es");

		BitcodeBytes.reset(getNonStreamedMemoryObject(Start, End));
	}	}


		StreamableMemoryObject &getBitcodeBytes() { return *BitcodeBytes; }

	~BitstreamReader() {	~BitstreamReader() {
	// Free the BlockInfoRecords.	// Free the BlockInfoRecords.
	while (!BlockInfoRecords.empty()) {	while (!BlockInfoRecords.empty()) {
	BlockInfo &Info = BlockInfoRecords.back();	BlockInfo &Info = BlockInfoRecords.back();
	// Free blockinfo abbrev info.	// Free blockinfo abbrev info.
	for (unsigned i = 0, e = static_cast<unsigned>(Info.Abbrevs.size());	for (unsigned i = 0, e = static_cast<unsigned>(Info.Abbrevs.size());
	i != e; ++i)	i != e; ++i)
	Info.Abbrevs[i]->dropRef();	Info.Abbrevs[i]->dropRef();
	BlockInfoRecords.pop_back();	BlockInfoRecords.pop_back();
	}	}
	}	}


	const unsigned char *getFirstChar() const { return FirstChar; }
	const unsigned char *getLastChar() const { return LastChar; }

	/// CollectBlockInfoNames - This is called by clients that want block/rec ord	/// CollectBlockInfoNames - This is called by clients that want block/rec ord
	/// name information.	/// name information.
	void CollectBlockInfoNames() { IgnoreBlockInfoNames = false; }	void CollectBlockInfoNames() { IgnoreBlockInfoNames = false; }
	bool isIgnoringBlockInfoNames() { return IgnoreBlockInfoNames; }	bool isIgnoringBlockInfoNames() { return IgnoreBlockInfoNames; }

	//===-------------------------------------------------------------------- ===//	//===-------------------------------------------------------------------- ===//
	// Block Manipulation	// Block Manipulation
	//===-------------------------------------------------------------------- ===//	//===-------------------------------------------------------------------- ===//

	/// hasBlockInfoRecords - Return true if we've already read and processed the	/// hasBlockInfoRecords - Return true if we've already read and processed the

	skipping to change at line 125	skipping to change at line 128
	BlockInfoRecords.push_back(BlockInfo());	BlockInfoRecords.push_back(BlockInfo());
	BlockInfoRecords.back().BlockID = BlockID;	BlockInfoRecords.back().BlockID = BlockID;
	return BlockInfoRecords.back();	return BlockInfoRecords.back();
	}	}

	};	};

	class BitstreamCursor {	class BitstreamCursor {
	friend class Deserializer;	friend class Deserializer;
	BitstreamReader *BitStream;	BitstreamReader *BitStream;

	const unsigned char *NextChar;	size_t NextChar;

	/// CurWord - This is the current data we have pulled from the stream but have	/// CurWord - This is the current data we have pulled from the stream but have
	/// not returned to the client.	/// not returned to the client.
	uint32_t CurWord;	uint32_t CurWord;

	/// BitsInCurWord - This is the number of bits in CurWord that are valid. This	/// BitsInCurWord - This is the number of bits in CurWord that are valid. This
	/// is always from [0...31] inclusive.	/// is always from [0...31] inclusive.
	unsigned BitsInCurWord;	unsigned BitsInCurWord;

	// CurCodeSize - This is the declared size of code values used for the cu rrent	// CurCodeSize - This is the declared size of code values used for the cu rrent

	skipping to change at line 159	skipping to change at line 162
	SmallVector<Block, 8> BlockScope;	SmallVector<Block, 8> BlockScope;

	public:	public:
	BitstreamCursor() : BitStream(0), NextChar(0) {	BitstreamCursor() : BitStream(0), NextChar(0) {
	}	}
	BitstreamCursor(const BitstreamCursor &RHS) : BitStream(0), NextChar(0) {	BitstreamCursor(const BitstreamCursor &RHS) : BitStream(0), NextChar(0) {
	operator=(RHS);	operator=(RHS);
	}	}

	explicit BitstreamCursor(BitstreamReader &R) : BitStream(&R) {	explicit BitstreamCursor(BitstreamReader &R) : BitStream(&R) {

	NextChar = R.getFirstChar();	NextChar = 0;
	assert(NextChar && "Bitstream not initialized yet");
	CurWord = 0;	CurWord = 0;
	BitsInCurWord = 0;	BitsInCurWord = 0;
	CurCodeSize = 2;	CurCodeSize = 2;
	}	}

	void init(BitstreamReader &R) {	void init(BitstreamReader &R) {
	freeState();	freeState();

	BitStream = &R;	BitStream = &R;

	NextChar = R.getFirstChar();	NextChar = 0;
	assert(NextChar && "Bitstream not initialized yet");
	CurWord = 0;	CurWord = 0;
	BitsInCurWord = 0;	BitsInCurWord = 0;
	CurCodeSize = 2;	CurCodeSize = 2;
	}	}

	~BitstreamCursor() {	~BitstreamCursor() {
	freeState();	freeState();
	}	}

	void operator=(const BitstreamCursor &RHS) {	void operator=(const BitstreamCursor &RHS) {

	skipping to change at line 228	skipping to change at line 229
	for (unsigned i = 0, e = static_cast<unsigned>(Abbrevs.size());	for (unsigned i = 0, e = static_cast<unsigned>(Abbrevs.size());
	i != e; ++i)	i != e; ++i)
	Abbrevs[i]->dropRef();	Abbrevs[i]->dropRef();
	}	}
	BlockScope.clear();	BlockScope.clear();
	}	}

	/// GetAbbrevIDWidth - Return the number of bits used to encode an abbrev #.	/// GetAbbrevIDWidth - Return the number of bits used to encode an abbrev #.
	unsigned GetAbbrevIDWidth() const { return CurCodeSize; }	unsigned GetAbbrevIDWidth() const { return CurCodeSize; }


	bool AtEndOfStream() const {	bool isEndPos(size_t pos) {
	return NextChar == BitStream->getLastChar() && BitsInCurWord == 0;	return BitStream->getBitcodeBytes().isObjectEnd(static_cast<uint64_t>(p
		os));
		}

		bool canSkipToPos(size_t pos) const {
		// pos can be skipped to if it is a valid address or one byte past the
		end.
		return pos == 0 \|\| BitStream->getBitcodeBytes().isValidAddress(
		static_cast<uint64_t>(pos - 1));
		}

		unsigned char getByte(size_t pos) {
		uint8_t byte = -1;
		BitStream->getBitcodeBytes().readByte(pos, &byte);
		return byte;
		}

		uint32_t getWord(size_t pos) {
		uint8_t buf[sizeof(uint32_t)];
		memset(buf, 0xFF, sizeof(buf));
		BitStream->getBitcodeBytes().readBytes(pos,
		sizeof(buf),
		buf,
		NULL);
		return reinterpret_cast<support::ulittle32_t >(buf);
		}

		bool AtEndOfStream() {
		return isEndPos(NextChar) && BitsInCurWord == 0;
	}	}

	/// GetCurrentBitNo - Return the bit # of the bit we are reading.	/// GetCurrentBitNo - Return the bit # of the bit we are reading.
	uint64_t GetCurrentBitNo() const {	uint64_t GetCurrentBitNo() const {

	return (NextChar-BitStream->getFirstChar())*CHAR_BIT - BitsInCurWord;	return NextChar*CHAR_BIT - BitsInCurWord;
	}	}

	BitstreamReader *getBitStreamReader() {	BitstreamReader *getBitStreamReader() {
	return BitStream;	return BitStream;
	}	}
	const BitstreamReader *getBitStreamReader() const {	const BitstreamReader *getBitStreamReader() const {
	return BitStream;	return BitStream;
	}	}

	/// JumpToBit - Reset the stream to the specified bit number.	/// JumpToBit - Reset the stream to the specified bit number.
	void JumpToBit(uint64_t BitNo) {	void JumpToBit(uint64_t BitNo) {
	uintptr_t ByteNo = uintptr_t(BitNo/8) & ~3;	uintptr_t ByteNo = uintptr_t(BitNo/8) & ~3;
	uintptr_t WordBitNo = uintptr_t(BitNo) & 31;	uintptr_t WordBitNo = uintptr_t(BitNo) & 31;

	assert(ByteNo <= (uintptr_t)(BitStream->getLastChar()-	assert(canSkipToPos(ByteNo) && "Invalid location");
	BitStream->getFirstChar()) &&
	"Invalid location");

	// Move the cursor to the right word.	// Move the cursor to the right word.

	NextChar = BitStream->getFirstChar()+ByteNo;	NextChar = ByteNo;
	BitsInCurWord = 0;	BitsInCurWord = 0;
	CurWord = 0;	CurWord = 0;

	// Skip over any bits that are already consumed.	// Skip over any bits that are already consumed.
	if (WordBitNo)	if (WordBitNo)
	Read(static_cast<unsigned>(WordBitNo));	Read(static_cast<unsigned>(WordBitNo));
	}	}

	uint32_t Read(unsigned NumBits) {	uint32_t Read(unsigned NumBits) {
	assert(NumBits <= 32 && "Cannot return more than 32 bits!");	assert(NumBits <= 32 && "Cannot return more than 32 bits!");
	// If the field is fully contained by CurWord, return it quickly.	// If the field is fully contained by CurWord, return it quickly.
	if (BitsInCurWord >= NumBits) {	if (BitsInCurWord >= NumBits) {
	uint32_t R = CurWord & ((1U << NumBits)-1);	uint32_t R = CurWord & ((1U << NumBits)-1);
	CurWord >>= NumBits;	CurWord >>= NumBits;
	BitsInCurWord -= NumBits;	BitsInCurWord -= NumBits;
	return R;	return R;
	}	}

	// If we run out of data, stop at the end of the stream.	// If we run out of data, stop at the end of the stream.

	if (NextChar == BitStream->getLastChar()) {	if (isEndPos(NextChar)) {
	CurWord = 0;	CurWord = 0;
	BitsInCurWord = 0;	BitsInCurWord = 0;
	return 0;	return 0;
	}	}

	unsigned R = CurWord;	unsigned R = CurWord;

	// Read the next word from the stream.	// Read the next word from the stream.

	CurWord = (NextChar[0] << 0) \| (NextChar[1] << 8) \|	CurWord = getWord(NextChar);
	(NextChar[2] << 16) \| (NextChar[3] << 24);
	NextChar += 4;	NextChar += 4;

	// Extract NumBits-BitsInCurWord from what we just read.	// Extract NumBits-BitsInCurWord from what we just read.
	unsigned BitsLeft = NumBits-BitsInCurWord;	unsigned BitsLeft = NumBits-BitsInCurWord;

	// Be careful here, BitsLeft is in the range [1..32] inclusive.	// Be careful here, BitsLeft is in the range [1..32] inclusive.
	R \|= (CurWord & (~0U >> (32-BitsLeft))) << BitsInCurWord;	R \|= (CurWord & (~0U >> (32-BitsLeft))) << BitsInCurWord;

	// BitsLeft bits have just been used up from CurWord.	// BitsLeft bits have just been used up from CurWord.
	if (BitsLeft != 32)	if (BitsLeft != 32)

	skipping to change at line 376	skipping to change at line 400
	/// true.	/// true.
	bool SkipBlock() {	bool SkipBlock() {
	// Read and ignore the codelen value. Since we are skipping this block , we	// Read and ignore the codelen value. Since we are skipping this block , we
	// don't care what code widths are used inside of it.	// don't care what code widths are used inside of it.
	ReadVBR(bitc::CodeLenWidth);	ReadVBR(bitc::CodeLenWidth);
	SkipToWord();	SkipToWord();
	unsigned NumWords = Read(bitc::BlockSizeWidth);	unsigned NumWords = Read(bitc::BlockSizeWidth);

	// Check that the block wasn't partially defined, and that the offset i sn't	// Check that the block wasn't partially defined, and that the offset i sn't
	// bogus.	// bogus.

	const unsigned char const SkipTo = NextChar + NumWords4;	size_t SkipTo = NextChar + NumWords*4;
	if (AtEndOfStream() \|\| SkipTo > BitStream->getLastChar() \|\|	if (AtEndOfStream() \|\| !canSkipToPos(SkipTo))
	SkipTo < BitStream->getFirstChar())
	return true;	return true;

	NextChar = SkipTo;	NextChar = SkipTo;
	return false;	return false;
	}	}

	/// EnterSubBlock - Having read the ENTER_SUBBLOCK abbrevid, enter	/// EnterSubBlock - Having read the ENTER_SUBBLOCK abbrevid, enter
	/// the block, and return true if the block is valid.	/// the block, and return true if the block is valid.
	bool EnterSubBlock(unsigned BlockID, unsigned *NumWordsP = 0) {	bool EnterSubBlock(unsigned BlockID, unsigned *NumWordsP = 0) {
	// Save the current block's state on BlockScope.	// Save the current block's state on BlockScope.

	skipping to change at line 409	skipping to change at line 432
	}	}
	}	}

	// Get the codesize of this block.	// Get the codesize of this block.
	CurCodeSize = ReadVBR(bitc::CodeLenWidth);	CurCodeSize = ReadVBR(bitc::CodeLenWidth);
	SkipToWord();	SkipToWord();
	unsigned NumWords = Read(bitc::BlockSizeWidth);	unsigned NumWords = Read(bitc::BlockSizeWidth);
	if (NumWordsP) *NumWordsP = NumWords;	if (NumWordsP) *NumWordsP = NumWords;

	// Validate that this block is sane.	// Validate that this block is sane.

	if (CurCodeSize == 0 \|\| AtEndOfStream() \|\|	if (CurCodeSize == 0 \|\| AtEndOfStream())
	NextChar+NumWords*4 > BitStream->getLastChar())
	return true;	return true;

	return false;	return false;
	}	}

	bool ReadBlockEnd() {	bool ReadBlockEnd() {
	if (BlockScope.empty()) return true;	if (BlockScope.empty()) return true;

	// Block tail:	// Block tail:
	// [END_BLOCK, <align4bytes>]	// [END_BLOCK, <align4bytes>]

	skipping to change at line 458	skipping to change at line 480
	// If the abbrev specifies the literal value to use, use it.	// If the abbrev specifies the literal value to use, use it.
	Vals.push_back(Op.getLiteralValue());	Vals.push_back(Op.getLiteralValue());
	}	}

	void ReadAbbreviatedField(const BitCodeAbbrevOp &Op,	void ReadAbbreviatedField(const BitCodeAbbrevOp &Op,
	SmallVectorImpl<uint64_t> &Vals) {	SmallVectorImpl<uint64_t> &Vals) {
	assert(!Op.isLiteral() && "Use ReadAbbreviatedLiteral for literals!");	assert(!Op.isLiteral() && "Use ReadAbbreviatedLiteral for literals!");

	// Decode the value as we are commanded.	// Decode the value as we are commanded.
	switch (Op.getEncoding()) {	switch (Op.getEncoding()) {

	default: assert(0 && "Unknown encoding!");	default: llvm_unreachable("Unknown encoding!");
	case BitCodeAbbrevOp::Fixed:	case BitCodeAbbrevOp::Fixed:
	Vals.push_back(Read((unsigned)Op.getEncodingData()));	Vals.push_back(Read((unsigned)Op.getEncodingData()));
	break;	break;
	case BitCodeAbbrevOp::VBR:	case BitCodeAbbrevOp::VBR:
	Vals.push_back(ReadVBR64((unsigned)Op.getEncodingData()));	Vals.push_back(ReadVBR64((unsigned)Op.getEncodingData()));
	break;	break;
	case BitCodeAbbrevOp::Char6:	case BitCodeAbbrevOp::Char6:
	Vals.push_back(BitCodeAbbrevOp::DecodeChar6(Read(6)));	Vals.push_back(BitCodeAbbrevOp::DecodeChar6(Read(6)));
	break;	break;
	}	}

	skipping to change at line 512	skipping to change at line 534

	// Read all the elements.	// Read all the elements.
	for (; NumElts; --NumElts)	for (; NumElts; --NumElts)
	ReadAbbreviatedField(EltEnc, Vals);	ReadAbbreviatedField(EltEnc, Vals);
	} else if (Op.getEncoding() == BitCodeAbbrevOp::Blob) {	} else if (Op.getEncoding() == BitCodeAbbrevOp::Blob) {
	// Blob case. Read the number of bytes as a vbr6.	// Blob case. Read the number of bytes as a vbr6.
	unsigned NumElts = ReadVBR(6);	unsigned NumElts = ReadVBR(6);
	SkipToWord(); // 32-bit alignment	SkipToWord(); // 32-bit alignment

	// Figure out where the end of this blob will be including tail pad ding.	// Figure out where the end of this blob will be including tail pad ding.

	const unsigned char *NewEnd = NextChar+((NumElts+3)&~3);	size_t NewEnd = NextChar+((NumElts+3)&~3);

	// If this would read off the end of the bitcode file, just set the	// If this would read off the end of the bitcode file, just set the
	// record to empty and return.	// record to empty and return.

	if (NewEnd > BitStream->getLastChar()) {	if (!canSkipToPos(NewEnd)) {
	Vals.append(NumElts, 0);	Vals.append(NumElts, 0);

	NextChar = BitStream->getLastChar();	NextChar = BitStream->getBitcodeBytes().getExtent();
	break;	break;
	}	}

	// Otherwise, read the number of bytes. If we can return a referen ce to	// Otherwise, read the number of bytes. If we can return a referen ce to
	// the data, do so to avoid copying it.	// the data, do so to avoid copying it.
	if (BlobStart) {	if (BlobStart) {

	BlobStart = (const char)NextChar;	BlobStart = (const char)BitStream->getBitcodeBytes().getPointer
		(
		NextChar, NumElts);
	*BlobLen = NumElts;	*BlobLen = NumElts;
	} else {	} else {
	for (; NumElts; ++NextChar, --NumElts)	for (; NumElts; ++NextChar, --NumElts)

	Vals.push_back(*NextChar);	Vals.push_back(getByte(NextChar));
	}	}
	// Skip over tail padding.	// Skip over tail padding.
	NextChar = NewEnd;	NextChar = NewEnd;
	} else {	} else {
	ReadAbbreviatedField(Op, Vals);	ReadAbbreviatedField(Op, Vals);
	}	}
	}	}

	unsigned Code = (unsigned)Vals[0];	unsigned Code = (unsigned)Vals[0];
	Vals.erase(Vals.begin());	Vals.erase(Vals.begin());

End of changes. 27 change blocks.
	37 lines changed or deleted	63 lines changed or added

	BitstreamWriter.h	BitstreamWriter.h

	skipping to change at line 19	skipping to change at line 19
	//	//
	// This header defines the BitstreamWriter class. This class can be used t o	// This header defines the BitstreamWriter class. This class can be used t o
	// write an arbitrary bitstream, regardless of its contents.	// write an arbitrary bitstream, regardless of its contents.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef BITSTREAM_WRITER_H	#ifndef BITSTREAM_WRITER_H
	#define BITSTREAM_WRITER_H	#define BITSTREAM_WRITER_H

	#include "llvm/ADT/StringRef.h"	#include "llvm/ADT/StringRef.h"

		#include "llvm/ADT/SmallVector.h"
	#include "llvm/Bitcode/BitCodes.h"	#include "llvm/Bitcode/BitCodes.h"
	#include <vector>	#include <vector>

	namespace llvm {	namespace llvm {

	class BitstreamWriter {	class BitstreamWriter {

	std::vector<unsigned char> &Out;	SmallVectorImpl<char> &Out;

	/// CurBit - Always between 0 and 31 inclusive, specifies the next bit to use.	/// CurBit - Always between 0 and 31 inclusive, specifies the next bit to use.
	unsigned CurBit;	unsigned CurBit;

	/// CurValue - The current value. Only bits < CurBit are valid.	/// CurValue - The current value. Only bits < CurBit are valid.
	uint32_t CurValue;	uint32_t CurValue;

	/// CurCodeSize - This is the declared size of code values used for the	/// CurCodeSize - This is the declared size of code values used for the
	/// current block, in bits.	/// current block, in bits.
	unsigned CurCodeSize;	unsigned CurCodeSize;

	skipping to change at line 62	skipping to change at line 63
	std::vector<Block> BlockScope;	std::vector<Block> BlockScope;

	/// BlockInfo - This contains information emitted to BLOCKINFO_BLOCK bloc ks.	/// BlockInfo - This contains information emitted to BLOCKINFO_BLOCK bloc ks.
	/// These describe abbreviations that all blocks of the specified ID inhe rit.	/// These describe abbreviations that all blocks of the specified ID inhe rit.
	struct BlockInfo {	struct BlockInfo {
	unsigned BlockID;	unsigned BlockID;
	std::vector<BitCodeAbbrev*> Abbrevs;	std::vector<BitCodeAbbrev*> Abbrevs;
	};	};
	std::vector<BlockInfo> BlockInfoRecords;	std::vector<BlockInfo> BlockInfoRecords;


		// BackpatchWord - Backpatch a 32-bit word in the output with the specifi
		ed
		// value.
		void BackpatchWord(unsigned ByteNo, unsigned NewWord) {
		Out[ByteNo++] = (unsigned char)(NewWord >> 0);
		Out[ByteNo++] = (unsigned char)(NewWord >> 8);
		Out[ByteNo++] = (unsigned char)(NewWord >> 16);
		Out[ByteNo ] = (unsigned char)(NewWord >> 24);
		}

		void WriteByte(unsigned char Value) {
		Out.push_back(Value);
		}

		void WriteWord(unsigned Value) {
		unsigned char Bytes[4] = {
		(unsigned char)(Value >> 0),
		(unsigned char)(Value >> 8),
		(unsigned char)(Value >> 16),
		(unsigned char)(Value >> 24) };
		Out.append(&Bytes[0], &Bytes[4]);
		}

		unsigned GetBufferOffset() const {
		return Out.size();
		}

		unsigned GetWordIndex() const {
		unsigned Offset = GetBufferOffset();
		assert((Offset & 3) == 0 && "Not 32-bit aligned");
		return Offset / 4;
		}

	public:	public:

	explicit BitstreamWriter(std::vector<unsigned char> &O)	explicit BitstreamWriter(SmallVectorImpl<char> &O)
	: Out(O), CurBit(0), CurValue(0), CurCodeSize(2) {}	: Out(O), CurBit(0), CurValue(0), CurCodeSize(2) {}

	~BitstreamWriter() {	~BitstreamWriter() {
	assert(CurBit == 0 && "Unflused data remaining");	assert(CurBit == 0 && "Unflused data remaining");
	assert(BlockScope.empty() && CurAbbrevs.empty() && "Block imbalance");	assert(BlockScope.empty() && CurAbbrevs.empty() && "Block imbalance");

	// Free the BlockInfoRecords.	// Free the BlockInfoRecords.
	while (!BlockInfoRecords.empty()) {	while (!BlockInfoRecords.empty()) {
	BlockInfo &Info = BlockInfoRecords.back();	BlockInfo &Info = BlockInfoRecords.back();
	// Free blockinfo abbrev info.	// Free blockinfo abbrev info.
	for (unsigned i = 0, e = static_cast<unsigned>(Info.Abbrevs.size());	for (unsigned i = 0, e = static_cast<unsigned>(Info.Abbrevs.size());
	i != e; ++i)	i != e; ++i)
	Info.Abbrevs[i]->dropRef();	Info.Abbrevs[i]->dropRef();
	BlockInfoRecords.pop_back();	BlockInfoRecords.pop_back();
	}	}
	}	}


	std::vector<unsigned char> &getBuffer() { return Out; }

	/// \brief Retrieve the current position in the stream, in bits.	/// \brief Retrieve the current position in the stream, in bits.

	uint64_t GetCurrentBitNo() const { return Out.size() * 8 + CurBit; }	uint64_t GetCurrentBitNo() const { return GetBufferOffset() * 8 + CurBit; }

	//===-------------------------------------------------------------------- ===//	//===-------------------------------------------------------------------- ===//
	// Basic Primitives for emitting bits to the stream.	// Basic Primitives for emitting bits to the stream.
	//===-------------------------------------------------------------------- ===//	//===-------------------------------------------------------------------- ===//

	void Emit(uint32_t Val, unsigned NumBits) {	void Emit(uint32_t Val, unsigned NumBits) {
	assert(NumBits && NumBits <= 32 && "Invalid value size!");	assert(NumBits && NumBits <= 32 && "Invalid value size!");
	assert((Val & ~(~0U >> (32-NumBits))) == 0 && "High bits set!");	assert((Val & ~(~0U >> (32-NumBits))) == 0 && "High bits set!");
	CurValue \|= Val << CurBit;	CurValue \|= Val << CurBit;
	if (CurBit + NumBits < 32) {	if (CurBit + NumBits < 32) {
	CurBit += NumBits;	CurBit += NumBits;
	return;	return;
	}	}

	// Add the current word.	// Add the current word.

	unsigned V = CurValue;	WriteWord(CurValue);
	Out.push_back((unsigned char)(V >> 0));
	Out.push_back((unsigned char)(V >> 8));
	Out.push_back((unsigned char)(V >> 16));
	Out.push_back((unsigned char)(V >> 24));

	if (CurBit)	if (CurBit)
	CurValue = Val >> (32-CurBit);	CurValue = Val >> (32-CurBit);
	else	else
	CurValue = 0;	CurValue = 0;
	CurBit = (CurBit+NumBits) & 31;	CurBit = (CurBit+NumBits) & 31;
	}	}

	void Emit64(uint64_t Val, unsigned NumBits) {	void Emit64(uint64_t Val, unsigned NumBits) {
	if (NumBits <= 32)	if (NumBits <= 32)
	Emit((uint32_t)Val, NumBits);	Emit((uint32_t)Val, NumBits);
	else {	else {
	Emit((uint32_t)Val, 32);	Emit((uint32_t)Val, 32);
	Emit((uint32_t)(Val >> 32), NumBits-32);	Emit((uint32_t)(Val >> 32), NumBits-32);
	}	}
	}	}

	void FlushToWord() {	void FlushToWord() {
	if (CurBit) {	if (CurBit) {

	unsigned V = CurValue;	WriteWord(CurValue);
	Out.push_back((unsigned char)(V >> 0));
	Out.push_back((unsigned char)(V >> 8));
	Out.push_back((unsigned char)(V >> 16));
	Out.push_back((unsigned char)(V >> 24));
	CurBit = 0;	CurBit = 0;
	CurValue = 0;	CurValue = 0;
	}	}
	}	}

	void EmitVBR(uint32_t Val, unsigned NumBits) {	void EmitVBR(uint32_t Val, unsigned NumBits) {
	uint32_t Threshold = 1U << (NumBits-1);	uint32_t Threshold = 1U << (NumBits-1);

	// Emit the bits with VBR encoding, NumBits-1 bits at a time.	// Emit the bits with VBR encoding, NumBits-1 bits at a time.
	while (Val >= Threshold) {	while (Val >= Threshold) {

	skipping to change at line 167	skipping to change at line 190
	}	}

	Emit((uint32_t)Val, NumBits);	Emit((uint32_t)Val, NumBits);
	}	}

	/// EmitCode - Emit the specified code.	/// EmitCode - Emit the specified code.
	void EmitCode(unsigned Val) {	void EmitCode(unsigned Val) {
	Emit(Val, CurCodeSize);	Emit(Val, CurCodeSize);
	}	}


	// BackpatchWord - Backpatch a 32-bit word in the output with the specifi
	ed
	// value.
	void BackpatchWord(unsigned ByteNo, unsigned NewWord) {
	Out[ByteNo++] = (unsigned char)(NewWord >> 0);
	Out[ByteNo++] = (unsigned char)(NewWord >> 8);
	Out[ByteNo++] = (unsigned char)(NewWord >> 16);
	Out[ByteNo ] = (unsigned char)(NewWord >> 24);
	}

	//===-------------------------------------------------------------------- ===//	//===-------------------------------------------------------------------- ===//
	// Block Manipulation	// Block Manipulation
	//===-------------------------------------------------------------------- ===//	//===-------------------------------------------------------------------- ===//

	/// getBlockInfo - If there is block info for the specified ID, return it ,	/// getBlockInfo - If there is block info for the specified ID, return it ,
	/// otherwise return null.	/// otherwise return null.
	BlockInfo *getBlockInfo(unsigned BlockID) {	BlockInfo *getBlockInfo(unsigned BlockID) {
	// Common case, the most recent entry matches BlockID.	// Common case, the most recent entry matches BlockID.
	if (!BlockInfoRecords.empty() && BlockInfoRecords.back().BlockID == Blo ckID)	if (!BlockInfoRecords.empty() && BlockInfoRecords.back().BlockID == Blo ckID)
	return &BlockInfoRecords.back();	return &BlockInfoRecords.back();

	skipping to change at line 202	skipping to change at line 216
	}	}

	void EnterSubblock(unsigned BlockID, unsigned CodeLen) {	void EnterSubblock(unsigned BlockID, unsigned CodeLen) {
	// Block header:	// Block header:
	// [ENTER_SUBBLOCK, blockid, newcodelen, <align4bytes>, blocklen]	// [ENTER_SUBBLOCK, blockid, newcodelen, <align4bytes>, blocklen]
	EmitCode(bitc::ENTER_SUBBLOCK);	EmitCode(bitc::ENTER_SUBBLOCK);
	EmitVBR(BlockID, bitc::BlockIDWidth);	EmitVBR(BlockID, bitc::BlockIDWidth);
	EmitVBR(CodeLen, bitc::CodeLenWidth);	EmitVBR(CodeLen, bitc::CodeLenWidth);
	FlushToWord();	FlushToWord();


	unsigned BlockSizeWordLoc = static_cast<unsigned>(Out.size());	unsigned BlockSizeWordIndex = GetWordIndex();
	unsigned OldCodeSize = CurCodeSize;	unsigned OldCodeSize = CurCodeSize;

	// Emit a placeholder, which will be replaced when the block is popped.	// Emit a placeholder, which will be replaced when the block is popped.
	Emit(0, bitc::BlockSizeWidth);	Emit(0, bitc::BlockSizeWidth);

	CurCodeSize = CodeLen;	CurCodeSize = CodeLen;

	// Push the outer block's abbrev set onto the stack, start out with an	// Push the outer block's abbrev set onto the stack, start out with an
	// empty abbrev set.	// empty abbrev set.

	BlockScope.push_back(Block(OldCodeSize, BlockSizeWordLoc/4));	BlockScope.push_back(Block(OldCodeSize, BlockSizeWordIndex));
	BlockScope.back().PrevAbbrevs.swap(CurAbbrevs);	BlockScope.back().PrevAbbrevs.swap(CurAbbrevs);

	// If there is a blockinfo for this BlockID, add all the predefined abb revs	// If there is a blockinfo for this BlockID, add all the predefined abb revs
	// to the abbrev list.	// to the abbrev list.
	if (BlockInfo *Info = getBlockInfo(BlockID)) {	if (BlockInfo *Info = getBlockInfo(BlockID)) {
	for (unsigned i = 0, e = static_cast<unsigned>(Info->Abbrevs.size());	for (unsigned i = 0, e = static_cast<unsigned>(Info->Abbrevs.size());
	i != e; ++i) {	i != e; ++i) {
	CurAbbrevs.push_back(Info->Abbrevs[i]);	CurAbbrevs.push_back(Info->Abbrevs[i]);
	Info->Abbrevs[i]->addRef();	Info->Abbrevs[i]->addRef();
	}	}

	skipping to change at line 242	skipping to change at line 256
	CurAbbrevs[i]->dropRef();	CurAbbrevs[i]->dropRef();

	const Block &B = BlockScope.back();	const Block &B = BlockScope.back();

	// Block tail:	// Block tail:
	// [END_BLOCK, <align4bytes>]	// [END_BLOCK, <align4bytes>]
	EmitCode(bitc::END_BLOCK);	EmitCode(bitc::END_BLOCK);
	FlushToWord();	FlushToWord();

	// Compute the size of the block, in words, not counting the size field .	// Compute the size of the block, in words, not counting the size field .

	unsigned SizeInWords= static_cast<unsigned>(Out.size())/4-B.StartSizeWo rd-1;	unsigned SizeInWords = GetWordIndex() - B.StartSizeWord - 1;
	unsigned ByteNo = B.StartSizeWord*4;	unsigned ByteNo = B.StartSizeWord*4;

	// Update the block size field in the header of this sub-block.	// Update the block size field in the header of this sub-block.
	BackpatchWord(ByteNo, SizeInWords);	BackpatchWord(ByteNo, SizeInWords);

	// Restore the inner block's code size and abbrev table.	// Restore the inner block's code size and abbrev table.
	CurCodeSize = B.PrevCodeSize;	CurCodeSize = B.PrevCodeSize;
	BlockScope.back().PrevAbbrevs.swap(CurAbbrevs);	BlockScope.back().PrevAbbrevs.swap(CurAbbrevs);
	BlockScope.pop_back();	BlockScope.pop_back();
	}	}

	skipping to change at line 278	skipping to change at line 292
	}	}

	/// EmitAbbreviatedField - Emit a single scalar field value with the spec ified	/// EmitAbbreviatedField - Emit a single scalar field value with the spec ified
	/// encoding.	/// encoding.
	template<typename uintty>	template<typename uintty>
	void EmitAbbreviatedField(const BitCodeAbbrevOp &Op, uintty V) {	void EmitAbbreviatedField(const BitCodeAbbrevOp &Op, uintty V) {
	assert(!Op.isLiteral() && "Literals should use EmitAbbreviatedLiteral!" );	assert(!Op.isLiteral() && "Literals should use EmitAbbreviatedLiteral!" );

	// Encode the value as we are commanded.	// Encode the value as we are commanded.
	switch (Op.getEncoding()) {	switch (Op.getEncoding()) {

	default: assert(0 && "Unknown encoding!");	default: llvm_unreachable("Unknown encoding!");
	case BitCodeAbbrevOp::Fixed:	case BitCodeAbbrevOp::Fixed:
	if (Op.getEncodingData())	if (Op.getEncodingData())
	Emit((unsigned)V, (unsigned)Op.getEncodingData());	Emit((unsigned)V, (unsigned)Op.getEncodingData());
	break;	break;
	case BitCodeAbbrevOp::VBR:	case BitCodeAbbrevOp::VBR:
	if (Op.getEncodingData())	if (Op.getEncodingData())
	EmitVBR64(V, (unsigned)Op.getEncodingData());	EmitVBR64(V, (unsigned)Op.getEncodingData());
	break;	break;
	case BitCodeAbbrevOp::Char6:	case BitCodeAbbrevOp::Char6:
	Emit(BitCodeAbbrevOp::EncodeChar6((char)V), 6);	Emit(BitCodeAbbrevOp::EncodeChar6((char)V), 6);

	skipping to change at line 358	skipping to change at line 372
	if (BlobData) {	if (BlobData) {
	EmitVBR(static_cast<uint32_t>(BlobLen), 6);	EmitVBR(static_cast<uint32_t>(BlobLen), 6);
	assert(RecordIdx == Vals.size() &&	assert(RecordIdx == Vals.size() &&
	"Blob data and record entries specified for blob operand!" );	"Blob data and record entries specified for blob operand!" );
	} else {	} else {
	EmitVBR(static_cast<uint32_t>(Vals.size()-RecordIdx), 6);	EmitVBR(static_cast<uint32_t>(Vals.size()-RecordIdx), 6);
	}	}

	// Flush to a 32-bit alignment boundary.	// Flush to a 32-bit alignment boundary.
	FlushToWord();	FlushToWord();

	assert((Out.size() & 3) == 0 && "Not 32-bit aligned");

	// Emit each field as a literal byte.	// Emit each field as a literal byte.
	if (BlobData) {	if (BlobData) {
	for (unsigned i = 0; i != BlobLen; ++i)	for (unsigned i = 0; i != BlobLen; ++i)

	Out.push_back((unsigned char)BlobData[i]);	WriteByte((unsigned char)BlobData[i]);

	// Know that blob data is consumed for assertion below.	// Know that blob data is consumed for assertion below.
	BlobData = 0;	BlobData = 0;
	} else {	} else {
	for (unsigned e = Vals.size(); RecordIdx != e; ++RecordIdx) {	for (unsigned e = Vals.size(); RecordIdx != e; ++RecordIdx) {
	assert(Vals[RecordIdx] < 256 && "Value too large to emit as blo b");	assert(Vals[RecordIdx] < 256 && "Value too large to emit as blo b");

	Out.push_back((unsigned char)Vals[RecordIdx]);	WriteByte((unsigned char)Vals[RecordIdx]);
	}	}
	}	}

	// Align end to 32-bits.
	while (Out.size() & 3)
	Out.push_back(0);


		// Align end to 32-bits.
		while (GetBufferOffset() & 3)
		WriteByte(0);
	} else { // Single scalar field.	} else { // Single scalar field.
	assert(RecordIdx < Vals.size() && "Invalid abbrev/record");	assert(RecordIdx < Vals.size() && "Invalid abbrev/record");
	EmitAbbreviatedField(Op, Vals[RecordIdx]);	EmitAbbreviatedField(Op, Vals[RecordIdx]);
	++RecordIdx;	++RecordIdx;
	}	}
	}	}
	assert(RecordIdx == Vals.size() && "Not all record operands emitted!");	assert(RecordIdx == Vals.size() && "Not all record operands emitted!");
	assert(BlobData == 0 &&	assert(BlobData == 0 &&
	"Blob data specified for record that doesn't use it!");	"Blob data specified for record that doesn't use it!");
	}	}

	skipping to change at line 491	skipping to change at line 504
	bitc::FIRST_APPLICATION_ABBREV;	bitc::FIRST_APPLICATION_ABBREV;
	}	}

	//===-------------------------------------------------------------------- ===//	//===-------------------------------------------------------------------- ===//
	// BlockInfo Block Emission	// BlockInfo Block Emission
	//===-------------------------------------------------------------------- ===//	//===-------------------------------------------------------------------- ===//

	/// EnterBlockInfoBlock - Start emitting the BLOCKINFO_BLOCK.	/// EnterBlockInfoBlock - Start emitting the BLOCKINFO_BLOCK.
	void EnterBlockInfoBlock(unsigned CodeWidth) {	void EnterBlockInfoBlock(unsigned CodeWidth) {
	EnterSubblock(bitc::BLOCKINFO_BLOCK_ID, CodeWidth);	EnterSubblock(bitc::BLOCKINFO_BLOCK_ID, CodeWidth);

	BlockInfoCurBID = -1U;	BlockInfoCurBID = ~0U;
	}	}
	private:	private:
	/// SwitchToBlockID - If we aren't already talking about the specified bl ock	/// SwitchToBlockID - If we aren't already talking about the specified bl ock
	/// ID, emit a BLOCKINFO_CODE_SETBID record.	/// ID, emit a BLOCKINFO_CODE_SETBID record.
	void SwitchToBlockID(unsigned BlockID) {	void SwitchToBlockID(unsigned BlockID) {
	if (BlockInfoCurBID == BlockID) return;	if (BlockInfoCurBID == BlockID) return;
	SmallVector<unsigned, 2> V;	SmallVector<unsigned, 2> V;
	V.push_back(BlockID);	V.push_back(BlockID);
	EmitRecord(bitc::BLOCKINFO_CODE_SETBID, V);	EmitRecord(bitc::BLOCKINFO_CODE_SETBID, V);
	BlockInfoCurBID = BlockID;	BlockInfoCurBID = BlockID;

End of changes. 19 change blocks.
	36 lines changed or deleted	49 lines changed or added

	BlockFrequency.h	BlockFrequency.h

	skipping to change at line 17	skipping to change at line 17
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	//	//
	// This file implements Block Frequency class.	// This file implements Block Frequency class.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_SUPPORT_BLOCKFREQUENCY_H	#ifndef LLVM_SUPPORT_BLOCKFREQUENCY_H
	#define LLVM_SUPPORT_BLOCKFREQUENCY_H	#define LLVM_SUPPORT_BLOCKFREQUENCY_H


		#include "llvm/Support/DataTypes.h"

	namespace llvm {	namespace llvm {

	class raw_ostream;	class raw_ostream;
	class BranchProbability;	class BranchProbability;

	// This class represents Block Frequency as a 64-bit value.	// This class represents Block Frequency as a 64-bit value.
	class BlockFrequency {	class BlockFrequency {

	uint64_t Frequency;	uint64_t Frequency;
	static const int64_t ENTRY_FREQ = 1024;	static const int64_t ENTRY_FREQ = 1024;

End of changes. 1 change blocks.
	0 lines changed or deleted	2 lines changed or added

	BlockFrequencyImpl.h	BlockFrequencyImpl.h

	skipping to change at line 27	skipping to change at line 27
	#include "llvm/BasicBlock.h"	#include "llvm/BasicBlock.h"
	#include "llvm/ADT/DenseMap.h"	#include "llvm/ADT/DenseMap.h"
	#include "llvm/ADT/PostOrderIterator.h"	#include "llvm/ADT/PostOrderIterator.h"
	#include "llvm/CodeGen/MachineBasicBlock.h"	#include "llvm/CodeGen/MachineBasicBlock.h"
	#include "llvm/CodeGen/MachineFunction.h"	#include "llvm/CodeGen/MachineFunction.h"
	#include "llvm/Support/BlockFrequency.h"	#include "llvm/Support/BlockFrequency.h"
	#include "llvm/Support/BranchProbability.h"	#include "llvm/Support/BranchProbability.h"
	#include "llvm/Support/Debug.h"	#include "llvm/Support/Debug.h"
	#include "llvm/Support/raw_ostream.h"	#include "llvm/Support/raw_ostream.h"
	#include <vector>	#include <vector>

	#include <sstream>
	#include <string>	#include <string>

	namespace llvm {	namespace llvm {

	class BlockFrequencyInfo;	class BlockFrequencyInfo;
	class MachineBlockFrequencyInfo;	class MachineBlockFrequencyInfo;

	/// BlockFrequencyImpl implements block frequency algorithm for IR and	/// BlockFrequencyImpl implements block frequency algorithm for IR and
	/// Machine Instructions. Algorithm starts with value 1024 (START_FREQ)	/// Machine Instructions. Algorithm starts with value 1024 (START_FREQ)
	/// for the entry block and then propagates frequencies using branch weight s	/// for the entry block and then propagates frequencies using branch weight s
	/// from (Machine)BranchProbabilityInfo. LoopInfo is not required because	/// from (Machine)BranchProbabilityInfo. LoopInfo is not required because
	/// algorithm can find "backedges" by itself.	/// algorithm can find "backedges" by itself.
	template<class BlockT, class FunctionT, class BlockProbInfoT>	template<class BlockT, class FunctionT, class BlockProbInfoT>
	class BlockFrequencyImpl {	class BlockFrequencyImpl {


	DenseMap<BlockT *, BlockFrequency> Freqs;	DenseMap<const BlockT *, BlockFrequency> Freqs;

	BlockProbInfoT *BPI;	BlockProbInfoT *BPI;

	FunctionT *Fn;	FunctionT *Fn;

	typedef GraphTraits< Inverse<BlockT *> > GT;	typedef GraphTraits< Inverse<BlockT *> > GT;

	const uint32_t EntryFreq;	const uint32_t EntryFreq;

	std::string getBlockName(BasicBlock *BB) const {	std::string getBlockName(BasicBlock *BB) const {

	return BB->getNameStr();	return BB->getName().str();
	}	}

	std::string getBlockName(MachineBasicBlock *MBB) const {	std::string getBlockName(MachineBasicBlock *MBB) const {

	std::stringstream ss;	std::string str;
		raw_string_ostream ss(str);
	ss << "BB#" << MBB->getNumber();	ss << "BB#" << MBB->getNumber();

	if (const BasicBlock *BB = MBB->getBasicBlock())	if (const BasicBlock *BB = MBB->getBasicBlock())

	ss << " derived from LLVM BB " << BB->getNameStr();	ss << " derived from LLVM BB " << BB->getName();

	return ss.str();	return ss.str();
	}	}

	void setBlockFreq(BlockT *BB, BlockFrequency Freq) {	void setBlockFreq(BlockT *BB, BlockFrequency Freq) {
	Freqs[BB] = Freq;	Freqs[BB] = Freq;
	DEBUG(dbgs() << "Frequency(" << getBlockName(BB) << ") = " << Freq << " \n");	DEBUG(dbgs() << "Frequency(" << getBlockName(BB) << ") = " << Freq << " \n");
	}	}

	/// getEdgeFreq - Return edge frequency based on SRC frequency and Src -> Dst	/// getEdgeFreq - Return edge frequency based on SRC frequency and Src -> Dst

	skipping to change at line 309	skipping to change at line 309
	doLoop(BB, LastTail);	doLoop(BB, LastTail);
	}	}

	// At the end assume the whole function as a loop, and travel over it o nce	// At the end assume the whole function as a loop, and travel over it o nce
	// again.	// again.
	doLoop((rpot_begin()), (pot_begin()));	doLoop((rpot_begin()), (pot_begin()));
	}	}

	public:	public:
	/// getBlockFreq - Return block frequency. Return 0 if we don't have it.	/// getBlockFreq - Return block frequency. Return 0 if we don't have it.

	BlockFrequency getBlockFreq(BlockT *BB) const {	BlockFrequency getBlockFreq(const BlockT *BB) const {
	typename DenseMap<BlockT *, BlockFrequency>::const_iterator I = Freqs.f	typename DenseMap<const BlockT *, BlockFrequency>::const_iterator
	ind(BB);	I = Freqs.find(BB);
	if (I != Freqs.end())	if (I != Freqs.end())
	return I->second;	return I->second;
	return 0;	return 0;
	}	}

	void print(raw_ostream &OS) const {	void print(raw_ostream &OS) const {
	OS << "\n\n---- Block Freqs ----\n";	OS << "\n\n---- Block Freqs ----\n";
	for (typename FunctionT::iterator I = Fn->begin(), E = Fn->end(); I != E;) {	for (typename FunctionT::iterator I = Fn->begin(), E = Fn->end(); I != E;) {
	BlockT *BB = I++;	BlockT *BB = I++;
	OS << " " << getBlockName(BB) << " = " << getBlockFreq(BB) << "\n";	OS << " " << getBlockName(BB) << " = " << getBlockFreq(BB) << "\n";

End of changes. 6 change blocks.
	8 lines changed or deleted	8 lines changed or added

	BlockFrequencyInfo.h	BlockFrequencyInfo.h

	skipping to change at line 50	skipping to change at line 50
	void getAnalysisUsage(AnalysisUsage &AU) const;	void getAnalysisUsage(AnalysisUsage &AU) const;

	bool runOnFunction(Function &F);	bool runOnFunction(Function &F);
	void print(raw_ostream &O, const Module *M) const;	void print(raw_ostream &O, const Module *M) const;

	/// getblockFreq - Return block frequency. Return 0 if we don't have the	/// getblockFreq - Return block frequency. Return 0 if we don't have the
	/// information. Please note that initial frequency is equal to 1024. It means	/// information. Please note that initial frequency is equal to 1024. It means
	/// that we should not rely on the value itself, but only on the comparis on to	/// that we should not rely on the value itself, but only on the comparis on to
	/// the other block frequencies. We do this to avoid using of floating po ints.	/// the other block frequencies. We do this to avoid using of floating po ints.
	///	///

	BlockFrequency getBlockFreq(BasicBlock *BB) const;	BlockFrequency getBlockFreq(const BasicBlock *BB) const;
	};	};

	}	}

	#endif	#endif

End of changes. 1 change blocks.
	1 lines changed or deleted	1 lines changed or added

	BranchProbability.h	BranchProbability.h

	skipping to change at line 18	skipping to change at line 18
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	//	//
	// Definition of BranchProbability shared by IR and Machine Instructions.	// Definition of BranchProbability shared by IR and Machine Instructions.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_SUPPORT_BRANCHPROBABILITY_H	#ifndef LLVM_SUPPORT_BRANCHPROBABILITY_H
	#define LLVM_SUPPORT_BRANCHPROBABILITY_H	#define LLVM_SUPPORT_BRANCHPROBABILITY_H

	#include "llvm/Support/DataTypes.h"	#include "llvm/Support/DataTypes.h"

		#include <cassert>

	namespace llvm {	namespace llvm {

	class raw_ostream;	class raw_ostream;

	// This class represents Branch Probability as a non-negative fraction.	// This class represents Branch Probability as a non-negative fraction.
	class BranchProbability {	class BranchProbability {


	// Numerator	// Numerator
	uint32_t N;	uint32_t N;

	// Denominator	// Denominator
	uint32_t D;	uint32_t D;

	public:	public:

	BranchProbability(uint32_t n, uint32_t d);	BranchProbability(uint32_t n, uint32_t d) : N(n), D(d) {
		assert(d > 0 && "Denomiator cannot be 0!");
		assert(n <= d && "Probability cannot be bigger than 1!");
		}

		static BranchProbability getZero() { return BranchProbability(0, 1); }
		static BranchProbability getOne() { return BranchProbability(1, 1); }

	uint32_t getNumerator() const { return N; }	uint32_t getNumerator() const { return N; }
	uint32_t getDenominator() const { return D; }	uint32_t getDenominator() const { return D; }

	// Return (1 - Probability).	// Return (1 - Probability).

	BranchProbability getCompl() {	BranchProbability getCompl() const {
	return BranchProbability(D - N, D);	return BranchProbability(D - N, D);
	}	}

	void print(raw_ostream &OS) const;	void print(raw_ostream &OS) const;

	void dump() const;	void dump() const;


		bool operator==(BranchProbability RHS) const {
		return (uint64_t)N * RHS.D == (uint64_t)D * RHS.N;
		}
		bool operator!=(BranchProbability RHS) const {
		return !(*this == RHS);
		}
		bool operator<(BranchProbability RHS) const {
		return (uint64_t)N * RHS.D < (uint64_t)D * RHS.N;
		}
		bool operator>(BranchProbability RHS) const {
		return RHS < *this;
		}
		bool operator<=(BranchProbability RHS) const {
		return (uint64_t)N * RHS.D <= (uint64_t)D * RHS.N;
		}
		bool operator>=(BranchProbability RHS) const {
		return RHS <= *this;
		}
	};	};

	raw_ostream &operator<<(raw_ostream &OS, const BranchProbability &Prob);	raw_ostream &operator<<(raw_ostream &OS, const BranchProbability &Prob);

	}	}

	#endif	#endif

End of changes. 5 change blocks.
	3 lines changed or deleted	28 lines changed or added

	BranchProbabilityInfo.h	BranchProbabilityInfo.h

	skipping to change at line 20	skipping to change at line 20
	// This pass is used to evaluate branch probabilties.	// This pass is used to evaluate branch probabilties.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_ANALYSIS_BRANCHPROBABILITYINFO_H	#ifndef LLVM_ANALYSIS_BRANCHPROBABILITYINFO_H
	#define LLVM_ANALYSIS_BRANCHPROBABILITYINFO_H	#define LLVM_ANALYSIS_BRANCHPROBABILITYINFO_H

	#include "llvm/InitializePasses.h"	#include "llvm/InitializePasses.h"
	#include "llvm/Pass.h"	#include "llvm/Pass.h"
	#include "llvm/ADT/DenseMap.h"	#include "llvm/ADT/DenseMap.h"

		#include "llvm/ADT/SmallPtrSet.h"
	#include "llvm/Support/BranchProbability.h"	#include "llvm/Support/BranchProbability.h"

	namespace llvm {	namespace llvm {

		class LoopInfo;
	class raw_ostream;	class raw_ostream;


		/// \brief Analysis pass providing branch probability information.
		///
		/// This is a function analysis pass which provides information on the rela
		tive
		/// probabilities of each "edge" in the function's CFG where such an edge i
		s
		/// defined by a pair of basic blocks. The probability for a given block an
		d
		/// a successor block are always relative to the probabilities of the other
		/// successor blocks. Another way of looking at it is that the probabilitie
		s
		/// for a given block B and each of its successors should sum to exactly
		/// one (100%).
	class BranchProbabilityInfo : public FunctionPass {	class BranchProbabilityInfo : public FunctionPass {


	// Default weight value. Used when we don't have information about the ed
	ge.
	// TODO: DEFAULT_WEIGHT makes sense during static predication, when none
	of
	// the successors have a weight yet. But it doesn't make sense when provi
	ding
	// weight to an edge that may have siblings with non-zero weights. This c
	an
	// be handled various ways, but it's probably fine for an edge with unkno
	wn
	// weight to just "inherit" the non-zero weight of an adjacent successor.
	static const uint32_t DEFAULT_WEIGHT = 16;

	typedef std::pair<const BasicBlock , const BasicBlock > Edge;

	DenseMap<Edge, uint32_t> Weights;

	// Get sum of the block successors' weights.
	uint32_t getSumForBlock(const BasicBlock *BB) const;

	public:	public:
	static char ID;	static char ID;

	BranchProbabilityInfo() : FunctionPass(ID) {	BranchProbabilityInfo() : FunctionPass(ID) {
	initializeBranchProbabilityInfoPass(*PassRegistry::getPassRegistry());	initializeBranchProbabilityInfoPass(*PassRegistry::getPassRegistry());
	}	}

	void getAnalysisUsage(AnalysisUsage &AU) const;	void getAnalysisUsage(AnalysisUsage &AU) const;


	bool runOnFunction(Function &F);	bool runOnFunction(Function &F);

		void print(raw_ostream &OS, const Module *M = 0) const;

		/// \brief Get an edge's probability, relative to other out-edges of the
		Src.
		///
		/// This routine provides access to the fractional probability between ze
		ro
		/// (0%) and one (100%) of this edge executing, relative to other edges
		/// leaving the 'Src' block. The returned probability is never zero, and
		can
		/// only be one if the source block has only one successor.
		BranchProbability getEdgeProbability(const BasicBlock *Src,
		const BasicBlock *Dst) const;

		/// \brief Test if an edge is hot relative to other out-edges of the Src.
		///
		/// Check whether this edge out of the source block is 'hot'. We define h
		ot
		/// as having a relative probability >= 80%.
		bool isEdgeHot(const BasicBlock Src, const BasicBlock Dst) const;

		/// \brief Retrieve the hot successor of a block if one exists.
		///
		/// Given a basic block, look through its successors and if one exists fo
		r
		/// which \see isEdgeHot would return true, return that successor block.
		BasicBlock getHotSucc(BasicBlock BB) const;


	// Returned value is between 1 and UINT32_MAX. Look at	/// \brief Print an edge's probability.
	// BranchProbabilityInfo.cpp for details.	///
		/// Retrieves an edge's probability similarly to \see getEdgeProbability,
		but
		/// then prints that probability to the provided stream. That stream is t
		hen
		/// returned.
		raw_ostream &printEdgeProbability(raw_ostream &OS, const BasicBlock *Src,
		const BasicBlock *Dst) const;

		/// \brief Get the raw edge weight calculated for the block pair.
		///
		/// This returns the raw edge weight. It is guaranteed to fall between 1
		and
		/// UINT32_MAX. Note that the raw edge weight is not meaningful in isolat
		ion.
		/// This interface should be very carefully, and primarily by routines th
		at
		/// are updating the analysis by later calling setEdgeWeight.
	uint32_t getEdgeWeight(const BasicBlock Src, const BasicBlock Dst) cons t;	uint32_t getEdgeWeight(const BasicBlock Src, const BasicBlock Dst) cons t;


	// Look at BranchProbabilityInfo.cpp for details. Use it with caution!	/// \brief Set the raw edge weight for the block pair.
		///
		/// This allows a pass to explicitly set the edge weight for a block. It
		can
		/// be used when updating the CFG to update and preserve the branch
		/// probability information. Read the implementation of how these edge
		/// weights are calculated carefully before using!
	void setEdgeWeight(const BasicBlock Src, const BasicBlock Dst,	void setEdgeWeight(const BasicBlock Src, const BasicBlock Dst,
	uint32_t Weight);	uint32_t Weight);


	// A 'Hot' edge is an edge which probability is >= 80%.	private:
	bool isEdgeHot(const BasicBlock Src, const BasicBlock Dst) const;	typedef std::pair<const BasicBlock , const BasicBlock > Edge;


	// Return a hot successor for the block BB or null if there isn't one.	// Default weight value. Used when we don't have information about the ed
	BasicBlock getHotSucc(BasicBlock BB) const;	ge.
		// TODO: DEFAULT_WEIGHT makes sense during static predication, when none
		of
		// the successors have a weight yet. But it doesn't make sense when provi
		ding
		// weight to an edge that may have siblings with non-zero weights. This c
		an
		// be handled various ways, but it's probably fine for an edge with unkno
		wn
		// weight to just "inherit" the non-zero weight of an adjacent successor.
		static const uint32_t DEFAULT_WEIGHT = 16;


	// Return a probability as a fraction between 0 (0% probability) and	DenseMap<Edge, uint32_t> Weights;
	// 1 (100% probability), however the value is never equal to 0, and can b
	e 1	/// \brief Handle to the LoopInfo analysis.
	// only iff SRC block has only one successor.	LoopInfo *LI;
	BranchProbability getEdgeProbability(const BasicBlock *Src,
	const BasicBlock *Dst) const;	/// \brief Track the last function we run over for printing.
		Function *LastF;

		/// \brief Track the set of blocks directly succeeded by a returning bloc
		k.
		SmallPtrSet<BasicBlock *, 16> PostDominatedByUnreachable;

		/// \brief Get sum of the block successors' weights.
		uint32_t getSumForBlock(const BasicBlock *BB) const;


	// Print value between 0 (0% probability) and 1 (100% probability),	bool calcUnreachableHeuristics(BasicBlock *BB);
	// however the value is never equal to 0, and can be 1 only iff SRC block	bool calcMetadataWeights(BasicBlock *BB);
	// has only one successor.	bool calcPointerHeuristics(BasicBlock *BB);
	raw_ostream &printEdgeProbability(raw_ostream &OS, BasicBlock *Src,	bool calcLoopBranchHeuristics(BasicBlock *BB);
	BasicBlock *Dst) const;	bool calcZeroHeuristics(BasicBlock *BB);
		bool calcFloatingPointHeuristics(BasicBlock *BB);
	};	};

	}	}

	#endif	#endif

End of changes. 12 change blocks.
	41 lines changed or deleted	102 lines changed or added

	Briggs.h	Briggs.h

	skipping to change at line 421	skipping to change at line 421

	void initializeNode(Graph::NodeItr nItr) {	void initializeNode(Graph::NodeItr nItr) {
	NodeData &nd = getHeuristicNodeData(nItr);	NodeData &nd = getHeuristicNodeData(nItr);

	if (nd.isInitialized)	if (nd.isInitialized)
	return; // Node data is already up to date.	return; // Node data is already up to date.

	unsigned numRegs = getGraph().getNodeCosts(nItr).getLength() - 1;	unsigned numRegs = getGraph().getNodeCosts(nItr).getLength() - 1;

	nd.numDenied = 0;	nd.numDenied = 0;

		const Vector& nCosts = getGraph().getNodeCosts(nItr);
		for (unsigned i = 1; i < nCosts.getLength(); ++i) {
		if (nCosts[i] == std::numeric_limits<PBQPNum>::infinity())
		++nd.numDenied;
		}

	nd.numSafe = numRegs;	nd.numSafe = numRegs;
	nd.unsafeDegrees.resize(numRegs, 0);	nd.unsafeDegrees.resize(numRegs, 0);

	typedef HeuristicSolverImpl<Briggs>::SolverEdgeItr SolverEdgeItr;	typedef HeuristicSolverImpl<Briggs>::SolverEdgeItr SolverEdgeItr;

	for (SolverEdgeItr aeItr = getSolver().solverEdgesBegin(nItr),	for (SolverEdgeItr aeItr = getSolver().solverEdgesBegin(nItr),
	aeEnd = getSolver().solverEdgesEnd(nItr);	aeEnd = getSolver().solverEdgesEnd(nItr);
	aeItr != aeEnd; ++aeItr) {	aeItr != aeEnd; ++aeItr) {

	Graph::EdgeItr eItr = *aeItr;	Graph::EdgeItr eItr = *aeItr;

End of changes. 1 change blocks.
	0 lines changed or deleted	6 lines changed or added

	CFGPrinter.h	CFGPrinter.h

	skipping to change at line 32	skipping to change at line 32
	#include "llvm/Support/CFG.h"	#include "llvm/Support/CFG.h"
	#include "llvm/Support/GraphWriter.h"	#include "llvm/Support/GraphWriter.h"

	namespace llvm {	namespace llvm {
	template<>	template<>
	struct DOTGraphTraits<const Function*> : public DefaultDOTGraphTraits {	struct DOTGraphTraits<const Function*> : public DefaultDOTGraphTraits {

	DOTGraphTraits (bool isSimple=false) : DefaultDOTGraphTraits(isSimple) {}	DOTGraphTraits (bool isSimple=false) : DefaultDOTGraphTraits(isSimple) {}

	static std::string getGraphName(const Function *F) {	static std::string getGraphName(const Function *F) {

	return "CFG for '" + F->getNameStr() + "' function";	return "CFG for '" + F->getName().str() + "' function";
	}	}

	static std::string getSimpleNodeLabel(const BasicBlock *Node,	static std::string getSimpleNodeLabel(const BasicBlock *Node,

	const Function *Graph) {	const Function *) {
	if (!Node->getName().empty())	if (!Node->getName().empty())

	return Node->getNameStr();	return Node->getName().str();

	std::string Str;	std::string Str;
	raw_string_ostream OS(Str);	raw_string_ostream OS(Str);

	WriteAsOperand(OS, Node, false);	WriteAsOperand(OS, Node, false);
	return OS.str();	return OS.str();
	}	}

	static std::string getCompleteNodeLabel(const BasicBlock *Node,	static std::string getCompleteNodeLabel(const BasicBlock *Node,

	const Function *Graph) {	const Function *) {
	std::string Str;	std::string Str;
	raw_string_ostream OS(Str);	raw_string_ostream OS(Str);

	if (Node->getName().empty()) {	if (Node->getName().empty()) {
	WriteAsOperand(OS, Node, false);	WriteAsOperand(OS, Node, false);
	OS << ":";	OS << ":";
	}	}

	OS << *Node;	OS << *Node;
	std::string OutStr = OS.str();	std::string OutStr = OS.str();

	skipping to change at line 98	skipping to change at line 98
	return (I == succ_begin(Node)) ? "T" : "F";	return (I == succ_begin(Node)) ? "T" : "F";

	// Label source of switch edges with the associated value.	// Label source of switch edges with the associated value.
	if (const SwitchInst *SI = dyn_cast<SwitchInst>(Node->getTerminator())) {	if (const SwitchInst *SI = dyn_cast<SwitchInst>(Node->getTerminator())) {
	unsigned SuccNo = I.getSuccessorIndex();	unsigned SuccNo = I.getSuccessorIndex();

	if (SuccNo == 0) return "def";	if (SuccNo == 0) return "def";

	std::string Str;	std::string Str;
	raw_string_ostream OS(Str);	raw_string_ostream OS(Str);

	OS << SI->getCaseValue(SuccNo)->getValue();	SwitchInst::ConstCaseIt Case =
		SwitchInst::ConstCaseIt::fromSuccessorIndex(SI, SuccNo);
		OS << Case.getCaseValue()->getValue();
	return OS.str();	return OS.str();
	}	}
	return "";	return "";
	}	}
	};	};
	} // End llvm namespace	} // End llvm namespace

	namespace llvm {	namespace llvm {
	class FunctionPass;	class FunctionPass;
	FunctionPass *createCFGPrinterPass ();	FunctionPass *createCFGPrinterPass ();

End of changes. 5 change blocks.
	5 lines changed or deleted	7 lines changed or added

	COFF.h	COFF.h

	skipping to change at line 22	skipping to change at line 22
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_OBJECT_COFF_H	#ifndef LLVM_OBJECT_COFF_H
	#define LLVM_OBJECT_COFF_H	#define LLVM_OBJECT_COFF_H

	#include "llvm/Object/ObjectFile.h"	#include "llvm/Object/ObjectFile.h"
	#include "llvm/Support/COFF.h"	#include "llvm/Support/COFF.h"
	#include "llvm/Support/Endian.h"	#include "llvm/Support/Endian.h"

	namespace llvm {	namespace llvm {

		template <typename T>
		class ArrayRef;

	namespace object {	namespace object {

	struct coff_file_header {	struct coff_file_header {
	support::ulittle16_t Machine;	support::ulittle16_t Machine;
	support::ulittle16_t NumberOfSections;	support::ulittle16_t NumberOfSections;
	support::ulittle32_t TimeDateStamp;	support::ulittle32_t TimeDateStamp;
	support::ulittle32_t PointerToSymbolTable;	support::ulittle32_t PointerToSymbolTable;
	support::ulittle32_t NumberOfSymbols;	support::ulittle32_t NumberOfSymbols;
	support::ulittle16_t SizeOfOptionalHeader;	support::ulittle16_t SizeOfOptionalHeader;
	support::ulittle16_t Characteristics;	support::ulittle16_t Characteristics;

	skipping to change at line 48	skipping to change at line 51
	};	};

	union {	union {
	char ShortName[8];	char ShortName[8];
	StringTableOffset Offset;	StringTableOffset Offset;
	} Name;	} Name;

	support::ulittle32_t Value;	support::ulittle32_t Value;
	support::little16_t SectionNumber;	support::little16_t SectionNumber;


	struct {	support::ulittle16_t Type;
	support::ulittle8_t BaseType;
	support::ulittle8_t ComplexType;
	} Type;

	support::ulittle8_t StorageClass;	support::ulittle8_t StorageClass;
	support::ulittle8_t NumberOfAuxSymbols;	support::ulittle8_t NumberOfAuxSymbols;


		uint8_t getBaseType() const {
		return Type & 0x0F;
		}

		uint8_t getComplexType() const {
		return (Type & 0xF0) >> 4;
		}
	};	};

	struct coff_section {	struct coff_section {
	char Name[8];	char Name[8];
	support::ulittle32_t VirtualSize;	support::ulittle32_t VirtualSize;
	support::ulittle32_t VirtualAddress;	support::ulittle32_t VirtualAddress;
	support::ulittle32_t SizeOfRawData;	support::ulittle32_t SizeOfRawData;
	support::ulittle32_t PointerToRawData;	support::ulittle32_t PointerToRawData;
	support::ulittle32_t PointerToRelocations;	support::ulittle32_t PointerToRelocations;
	support::ulittle32_t PointerToLinenumbers;	support::ulittle32_t PointerToLinenumbers;

	skipping to change at line 76	skipping to change at line 84
	support::ulittle16_t NumberOfLinenumbers;	support::ulittle16_t NumberOfLinenumbers;
	support::ulittle32_t Characteristics;	support::ulittle32_t Characteristics;
	};	};

	struct coff_relocation {	struct coff_relocation {
	support::ulittle32_t VirtualAddress;	support::ulittle32_t VirtualAddress;
	support::ulittle32_t SymbolTableIndex;	support::ulittle32_t SymbolTableIndex;
	support::ulittle16_t Type;	support::ulittle16_t Type;
	};	};


		struct coff_aux_section_definition {
		support::ulittle32_t Length;
		support::ulittle16_t NumberOfRelocations;
		support::ulittle16_t NumberOfLinenumbers;
		support::ulittle32_t CheckSum;
		support::ulittle16_t Number;
		support::ulittle8_t Selection;
		char Unused[3];
		};

	class COFFObjectFile : public ObjectFile {	class COFFObjectFile : public ObjectFile {
	private:	private:
	const coff_file_header *Header;	const coff_file_header *Header;
	const coff_section *SectionTable;	const coff_section *SectionTable;
	const coff_symbol *SymbolTable;	const coff_symbol *SymbolTable;
	const char *StringTable;	const char *StringTable;
	uint32_t StringTableSize;	uint32_t StringTableSize;


	error_code getSection(int32_t index,
	const coff_section *&Res) const;
	error_code getString(uint32_t offset, StringRef &Res) const;	error_code getString(uint32_t offset, StringRef &Res) const;

	error_code getSymbol(uint32_t index,
	const coff_symbol *&Res) const;

	const coff_symbol *toSymb(DataRefImpl Symb) const;	const coff_symbol *toSymb(DataRefImpl Symb) const;
	const coff_section *toSec(DataRefImpl Sec) const;	const coff_section *toSec(DataRefImpl Sec) const;
	const coff_relocation *toRel(DataRefImpl Rel) const;	const coff_relocation *toRel(DataRefImpl Rel) const;

	protected:	protected:
	virtual error_code getSymbolNext(DataRefImpl Symb, SymbolRef &Res) const;	virtual error_code getSymbolNext(DataRefImpl Symb, SymbolRef &Res) const;
	virtual error_code getSymbolName(DataRefImpl Symb, StringRef &Res) const;	virtual error_code getSymbolName(DataRefImpl Symb, StringRef &Res) const;

	virtual error_code getSymbolOffset(DataRefImpl Symb, uint64_t &Res) const ;	virtual error_code getSymbolFileOffset(DataRefImpl Symb, uint64_t &Res) c onst;
	virtual error_code getSymbolAddress(DataRefImpl Symb, uint64_t &Res) cons t;	virtual error_code getSymbolAddress(DataRefImpl Symb, uint64_t &Res) cons t;
	virtual error_code getSymbolSize(DataRefImpl Symb, uint64_t &Res) const;	virtual error_code getSymbolSize(DataRefImpl Symb, uint64_t &Res) const;
	virtual error_code getSymbolNMTypeChar(DataRefImpl Symb, char &Res) const ;	virtual error_code getSymbolNMTypeChar(DataRefImpl Symb, char &Res) const ;

	virtual error_code isSymbolInternal(DataRefImpl Symb, bool &Res) const;	virtual error_code getSymbolFlags(DataRefImpl Symb, uint32_t &Res) const;
	virtual error_code isSymbolGlobal(DataRefImpl Symb, bool &Res) const;	virtual error_code getSymbolType(DataRefImpl Symb, SymbolRef::Type &Res)
	virtual error_code getSymbolType(DataRefImpl Symb, SymbolRef::SymbolType	const;
	&Res) const;	virtual error_code getSymbolSection(DataRefImpl Symb,
		section_iterator &Res) const;

	virtual error_code getSectionNext(DataRefImpl Sec, SectionRef &Res) const ;	virtual error_code getSectionNext(DataRefImpl Sec, SectionRef &Res) const ;
	virtual error_code getSectionName(DataRefImpl Sec, StringRef &Res) const;	virtual error_code getSectionName(DataRefImpl Sec, StringRef &Res) const;
	virtual error_code getSectionAddress(DataRefImpl Sec, uint64_t &Res) cons t;	virtual error_code getSectionAddress(DataRefImpl Sec, uint64_t &Res) cons t;
	virtual error_code getSectionSize(DataRefImpl Sec, uint64_t &Res) const;	virtual error_code getSectionSize(DataRefImpl Sec, uint64_t &Res) const;
	virtual error_code getSectionContents(DataRefImpl Sec, StringRef &Res) co nst;	virtual error_code getSectionContents(DataRefImpl Sec, StringRef &Res) co nst;
	virtual error_code getSectionAlignment(DataRefImpl Sec, uint64_t &Res) co nst;	virtual error_code getSectionAlignment(DataRefImpl Sec, uint64_t &Res) co nst;
	virtual error_code isSectionText(DataRefImpl Sec, bool &Res) const;	virtual error_code isSectionText(DataRefImpl Sec, bool &Res) const;
	virtual error_code isSectionData(DataRefImpl Sec, bool &Res) const;	virtual error_code isSectionData(DataRefImpl Sec, bool &Res) const;
	virtual error_code isSectionBSS(DataRefImpl Sec, bool &Res) const;	virtual error_code isSectionBSS(DataRefImpl Sec, bool &Res) const;

		virtual error_code isSectionVirtual(DataRefImpl Sec, bool &Res) const;
		virtual error_code isSectionZeroInit(DataRefImpl Sec, bool &Res) const;
		virtual error_code isSectionRequiredForExecution(DataRefImpl Sec,
		bool &Res) const;
	virtual error_code sectionContainsSymbol(DataRefImpl Sec, DataRefImpl Sym b,	virtual error_code sectionContainsSymbol(DataRefImpl Sec, DataRefImpl Sym b,
	bool &Result) const;	bool &Result) const;
	virtual relocation_iterator getSectionRelBegin(DataRefImpl Sec) const;	virtual relocation_iterator getSectionRelBegin(DataRefImpl Sec) const;
	virtual relocation_iterator getSectionRelEnd(DataRefImpl Sec) const;	virtual relocation_iterator getSectionRelEnd(DataRefImpl Sec) const;

	virtual error_code getRelocationNext(DataRefImpl Rel,	virtual error_code getRelocationNext(DataRefImpl Rel,
	RelocationRef &Res) const;	RelocationRef &Res) const;
	virtual error_code getRelocationAddress(DataRefImpl Rel,	virtual error_code getRelocationAddress(DataRefImpl Rel,
	uint64_t &Res) const;	uint64_t &Res) const;

		virtual error_code getRelocationOffset(DataRefImpl Rel,
		uint64_t &Res) const;
	virtual error_code getRelocationSymbol(DataRefImpl Rel,	virtual error_code getRelocationSymbol(DataRefImpl Rel,
	SymbolRef &Res) const;	SymbolRef &Res) const;
	virtual error_code getRelocationType(DataRefImpl Rel,	virtual error_code getRelocationType(DataRefImpl Rel,

	uint32_t &Res) const;	uint64_t &Res) const;
	virtual error_code getRelocationTypeName(DataRefImpl Rel,	virtual error_code getRelocationTypeName(DataRefImpl Rel,
	SmallVectorImpl<char> &Result) c onst;	SmallVectorImpl<char> &Result) c onst;
	virtual error_code getRelocationAdditionalInfo(DataRefImpl Rel,	virtual error_code getRelocationAdditionalInfo(DataRefImpl Rel,
	int64_t &Res) const;	int64_t &Res) const;
	virtual error_code getRelocationValueString(DataRefImpl Rel,	virtual error_code getRelocationValueString(DataRefImpl Rel,
	SmallVectorImpl<char> &Result) c onst;	SmallVectorImpl<char> &Result) c onst;


		virtual error_code getLibraryNext(DataRefImpl LibData,
		LibraryRef &Result) const;
		virtual error_code getLibraryPath(DataRefImpl LibData,
		StringRef &Result) const;

	public:	public:
	COFFObjectFile(MemoryBuffer *Object, error_code &ec);	COFFObjectFile(MemoryBuffer *Object, error_code &ec);
	virtual symbol_iterator begin_symbols() const;	virtual symbol_iterator begin_symbols() const;
	virtual symbol_iterator end_symbols() const;	virtual symbol_iterator end_symbols() const;

		virtual symbol_iterator begin_dynamic_symbols() const;
		virtual symbol_iterator end_dynamic_symbols() const;
		virtual library_iterator begin_libraries_needed() const;
		virtual library_iterator end_libraries_needed() const;
	virtual section_iterator begin_sections() const;	virtual section_iterator begin_sections() const;
	virtual section_iterator end_sections() const;	virtual section_iterator end_sections() const;

	virtual uint8_t getBytesInAddress() const;	virtual uint8_t getBytesInAddress() const;
	virtual StringRef getFileFormatName() const;	virtual StringRef getFileFormatName() const;
	virtual unsigned getArch() const;	virtual unsigned getArch() const;

		virtual StringRef getLoadName() const;

		error_code getHeader(const coff_file_header *&Res) const;
		error_code getSection(int32_t index, const coff_section *&Res) const;
		error_code getSymbol(uint32_t index, const coff_symbol *&Res) const;
		template <typename T>
		error_code getAuxSymbol(uint32_t index, const T *&Res) const {
		const coff_symbol *s;
		error_code ec = getSymbol(index, s);
		Res = reinterpret_cast<const T*>(s);
		return ec;
		}
		error_code getSymbolName(const coff_symbol *symbol, StringRef &Res) const
		;
		error_code getSectionName(const coff_section *Sec, StringRef &Res) const;
		error_code getSectionContents(const coff_section *Sec,
		ArrayRef<uint8_t> &Res) const;

		static inline bool classof(const Binary *v) {
		return v->isCOFF();
		}
		static inline bool classof(const COFFObjectFile *v) { return true; }
	};	};

	}	}
	}	}

	#endif	#endif

End of changes. 14 change blocks.
	14 lines changed or deleted	66 lines changed or added

	CallSite.h	CallSite.h

	skipping to change at line 240	skipping to change at line 240
	bool doesNotThrow() const {	bool doesNotThrow() const {
	CALLSITE_DELEGATE_GETTER(doesNotThrow());	CALLSITE_DELEGATE_GETTER(doesNotThrow());
	}	}
	void setDoesNotThrow(bool doesNotThrow = true) {	void setDoesNotThrow(bool doesNotThrow = true) {
	CALLSITE_DELEGATE_SETTER(setDoesNotThrow(doesNotThrow));	CALLSITE_DELEGATE_SETTER(setDoesNotThrow(doesNotThrow));
	}	}

	#undef CALLSITE_DELEGATE_GETTER	#undef CALLSITE_DELEGATE_GETTER
	#undef CALLSITE_DELEGATE_SETTER	#undef CALLSITE_DELEGATE_SETTER


		/// @brief Determine whether this argument is not captured.
		bool doesNotCapture(unsigned ArgNo) const {
		return paramHasAttr(ArgNo + 1, Attribute::NoCapture);
		}

		/// @brief Determine whether this argument is passed by value.
		bool isByValArgument(unsigned ArgNo) const {
		return paramHasAttr(ArgNo + 1, Attribute::ByVal);
		}

	/// hasArgument - Returns true if this CallSite passes the given Value* a s an	/// hasArgument - Returns true if this CallSite passes the given Value* a s an
	/// argument to the called function.	/// argument to the called function.
	bool hasArgument(const Value *Arg) const {	bool hasArgument(const Value *Arg) const {
	for (arg_iterator AI = this->arg_begin(), E = this->arg_end(); AI != E;	for (arg_iterator AI = this->arg_begin(), E = this->arg_end(); AI != E;
	++AI)	++AI)
	if (AI->get() == Arg)	if (AI->get() == Arg)
	return true;	return true;
	return false;	return false;
	}	}


End of changes. 1 change blocks.
	0 lines changed or deleted	10 lines changed or added

	CallingConvLower.h	CallingConvLower.h

	skipping to change at line 232	skipping to change at line 232
	/// incorporating info about the passed values into this state.	/// incorporating info about the passed values into this state.
	void AnalyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins,	void AnalyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins,
	CCAssignFn Fn);	CCAssignFn Fn);

	/// AnalyzeCallResult - Same as above except it's specialized for calls w hich	/// AnalyzeCallResult - Same as above except it's specialized for calls w hich
	/// produce a single value.	/// produce a single value.
	void AnalyzeCallResult(MVT VT, CCAssignFn Fn);	void AnalyzeCallResult(MVT VT, CCAssignFn Fn);

	/// getFirstUnallocated - Return the first unallocated register in the se t, or	/// getFirstUnallocated - Return the first unallocated register in the se t, or
	/// NumRegs if they are all allocated.	/// NumRegs if they are all allocated.

	unsigned getFirstUnallocated(const unsigned *Regs, unsigned NumRegs) cons t {	unsigned getFirstUnallocated(const uint16_t *Regs, unsigned NumRegs) cons t {
	for (unsigned i = 0; i != NumRegs; ++i)	for (unsigned i = 0; i != NumRegs; ++i)
	if (!isAllocated(Regs[i]))	if (!isAllocated(Regs[i]))
	return i;	return i;
	return NumRegs;	return NumRegs;
	}	}

	/// AllocateReg - Attempt to allocate one register. If it is not availab le,	/// AllocateReg - Attempt to allocate one register. If it is not availab le,
	/// return zero. Otherwise, return the register, marking it and any alia ses	/// return zero. Otherwise, return the register, marking it and any alia ses
	/// as allocated.	/// as allocated.
	unsigned AllocateReg(unsigned Reg) {	unsigned AllocateReg(unsigned Reg) {

	skipping to change at line 259	skipping to change at line 259
	unsigned AllocateReg(unsigned Reg, unsigned ShadowReg) {	unsigned AllocateReg(unsigned Reg, unsigned ShadowReg) {
	if (isAllocated(Reg)) return 0;	if (isAllocated(Reg)) return 0;
	MarkAllocated(Reg);	MarkAllocated(Reg);
	MarkAllocated(ShadowReg);	MarkAllocated(ShadowReg);
	return Reg;	return Reg;
	}	}

	/// AllocateReg - Attempt to allocate one of the specified registers. If none	/// AllocateReg - Attempt to allocate one of the specified registers. If none
	/// are available, return zero. Otherwise, return the first one availabl e,	/// are available, return zero. Otherwise, return the first one availabl e,
	/// marking it and any aliases as allocated.	/// marking it and any aliases as allocated.

	unsigned AllocateReg(const unsigned *Regs, unsigned NumRegs) {	unsigned AllocateReg(const uint16_t *Regs, unsigned NumRegs) {
	unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs);	unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs);
	if (FirstUnalloc == NumRegs)	if (FirstUnalloc == NumRegs)
	return 0; // Didn't find the reg.	return 0; // Didn't find the reg.

	// Mark the register and any aliases as allocated.	// Mark the register and any aliases as allocated.
	unsigned Reg = Regs[FirstUnalloc];	unsigned Reg = Regs[FirstUnalloc];
	MarkAllocated(Reg);	MarkAllocated(Reg);
	return Reg;	return Reg;
	}	}

	/// Version of AllocateReg with list of registers to be shadowed.	/// Version of AllocateReg with list of registers to be shadowed.

	unsigned AllocateReg(const unsigned Regs, const unsigned ShadowRegs,	unsigned AllocateReg(const uint16_t Regs, const uint16_t ShadowRegs,
	unsigned NumRegs) {	unsigned NumRegs) {
	unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs);	unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs);
	if (FirstUnalloc == NumRegs)	if (FirstUnalloc == NumRegs)
	return 0; // Didn't find the reg.	return 0; // Didn't find the reg.

	// Mark the register and any aliases as allocated.	// Mark the register and any aliases as allocated.
	unsigned Reg = Regs[FirstUnalloc], ShadowReg = ShadowRegs[FirstUnalloc] ;	unsigned Reg = Regs[FirstUnalloc], ShadowReg = ShadowRegs[FirstUnalloc] ;
	MarkAllocated(Reg);	MarkAllocated(Reg);
	MarkAllocated(ShadowReg);	MarkAllocated(ShadowReg);
	return Reg;	return Reg;

	skipping to change at line 309	skipping to change at line 309

	// HandleByVal - Allocate a stack slot large enough to pass an argument b y	// HandleByVal - Allocate a stack slot large enough to pass an argument b y
	// value. The size and alignment information of the argument is encoded i n its	// value. The size and alignment information of the argument is encoded i n its
	// parameter attribute.	// parameter attribute.
	void HandleByVal(unsigned ValNo, MVT ValVT,	void HandleByVal(unsigned ValNo, MVT ValVT,
	MVT LocVT, CCValAssign::LocInfo LocInfo,	MVT LocVT, CCValAssign::LocInfo LocInfo,
	int MinSize, int MinAlign, ISD::ArgFlagsTy ArgFlags);	int MinSize, int MinAlign, ISD::ArgFlagsTy ArgFlags);

	// First GPR that carries part of a byval aggregate that's split	// First GPR that carries part of a byval aggregate that's split
	// between registers and memory.	// between registers and memory.

	unsigned getFirstByValReg() { return FirstByValRegValid ? FirstByValReg : 0; }	unsigned getFirstByValReg() const { return FirstByValRegValid ? FirstByVa lReg : 0; }
	void setFirstByValReg(unsigned r) { FirstByValReg = r; FirstByValRegValid = true; }	void setFirstByValReg(unsigned r) { FirstByValReg = r; FirstByValRegValid = true; }
	void clearFirstByValReg() { FirstByValReg = 0; FirstByValRegValid = false ; }	void clearFirstByValReg() { FirstByValReg = 0; FirstByValRegValid = false ; }

	bool isFirstByValRegValid() { return FirstByValRegValid; }	bool isFirstByValRegValid() const { return FirstByValRegValid; }


	ParmContext getCallOrPrologue() { return CallOrPrologue; }	ParmContext getCallOrPrologue() const { return CallOrPrologue; }

	private:	private:
	/// MarkAllocated - Mark a register and all of its aliases as allocated.	/// MarkAllocated - Mark a register and all of its aliases as allocated.
	void MarkAllocated(unsigned Reg);	void MarkAllocated(unsigned Reg);
	};	};

	} // end namespace llvm	} // end namespace llvm

	#endif	#endif

End of changes. 6 change blocks.
	6 lines changed or deleted	6 lines changed or added

	Capacity.h	Capacity.h

	skipping to change at line 18	skipping to change at line 18
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	//	//
	// This file defines the capacity function that computes the amount of	// This file defines the capacity function that computes the amount of
	// memory used by an ADT.	// memory used by an ADT.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_SUPPORT_CAPACITY_H	#ifndef LLVM_SUPPORT_CAPACITY_H
	#define LLVM_SUPPORT_CAPACITY_H	#define LLVM_SUPPORT_CAPACITY_H


		#include <cstddef>

	namespace llvm {	namespace llvm {

	template <typename T>	template <typename T>
	static inline size_t capacity_in_bytes(const T &x) {	static inline size_t capacity_in_bytes(const T &x) {
	// This default definition of capacity should work for things like std::v ector	// This default definition of capacity should work for things like std::v ector
	// and friends. More specialized versions will work for others.	// and friends. More specialized versions will work for others.
	return x.capacity() * sizeof(typename T::value_type);	return x.capacity() * sizeof(typename T::value_type);
	}	}

	} // end namespace llvm	} // end namespace llvm

End of changes. 1 change blocks.
	0 lines changed or deleted	2 lines changed or added

	CaptureTracking.h	CaptureTracking.h

	skipping to change at line 17	skipping to change at line 17
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	//	//
	// This file contains routines that help determine which pointers are captu red.	// This file contains routines that help determine which pointers are captu red.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_ANALYSIS_CAPTURETRACKING_H	#ifndef LLVM_ANALYSIS_CAPTURETRACKING_H
	#define LLVM_ANALYSIS_CAPTURETRACKING_H	#define LLVM_ANALYSIS_CAPTURETRACKING_H


	namespace llvm {	#include "llvm/Constants.h"
	class Value;	#include "llvm/Instructions.h"
		#include "llvm/Analysis/AliasAnalysis.h"
		#include "llvm/Support/CallSite.h"


		namespace llvm {
	/// PointerMayBeCaptured - Return true if this pointer value may be captu red	/// PointerMayBeCaptured - Return true if this pointer value may be captu red
	/// by the enclosing function (which is required to exist). This routine can	/// by the enclosing function (which is required to exist). This routine can
	/// be expensive, so consider caching the results. The boolean ReturnCap tures	/// be expensive, so consider caching the results. The boolean ReturnCap tures
	/// specifies whether returning the value (or part of it) from the functi on	/// specifies whether returning the value (or part of it) from the functi on
	/// counts as capturing it or not. The boolean StoreCaptures specified	/// counts as capturing it or not. The boolean StoreCaptures specified
	/// whether storing the value (or part of it) into memory anywhere	/// whether storing the value (or part of it) into memory anywhere
	/// automatically counts as capturing it or not.	/// automatically counts as capturing it or not.
	bool PointerMayBeCaptured(const Value *V,	bool PointerMayBeCaptured(const Value *V,
	bool ReturnCaptures,	bool ReturnCaptures,
	bool StoreCaptures);	bool StoreCaptures);


		/// This callback is used in conjunction with PointerMayBeCaptured. In
		/// addition to the interface here, you'll need to provide your own gette
		rs
		/// to see whether anything was captured.
		struct CaptureTracker {
		virtual ~CaptureTracker();

		/// tooManyUses - The depth of traversal has breached a limit. There ma
		y be
		/// capturing instructions that will not be passed into captured().
		virtual void tooManyUses() = 0;

		/// shouldExplore - This is the use of a value derived from the pointer
		.
		/// To prune the search (ie., assume that none of its users could possi
		bly
		/// capture) return false. To search it, return true.
		///
		/// U->getUser() is always an Instruction.
		virtual bool shouldExplore(Use *U) = 0;

		/// captured - Information about the pointer was captured by the user o
		f
		/// use U. Return true to stop the traversal or false to continue looki
		ng
		/// for more capturing instructions.
		virtual bool captured(Use *U) = 0;
		};

		/// PointerMayBeCaptured - Visit the value and the values derived from it
		and
		/// find values which appear to be capturing the pointer value. This feed
		s
		/// results into and is controlled by the CaptureTracker object.
		void PointerMayBeCaptured(const Value V, CaptureTracker Tracker);
	} // end namespace llvm	} // end namespace llvm

	#endif	#endif

End of changes. 3 change blocks.
	2 lines changed or deleted	40 lines changed or added

	Cloning.h	Cloning.h

	skipping to change at line 59	skipping to change at line 59
	Module CloneModule(const Module M);	Module CloneModule(const Module M);
	Module CloneModule(const Module M, ValueToValueMapTy &VMap);	Module CloneModule(const Module M, ValueToValueMapTy &VMap);

	/// ClonedCodeInfo - This struct can be used to capture information about c ode	/// ClonedCodeInfo - This struct can be used to capture information about c ode
	/// being cloned, while it is being cloned.	/// being cloned, while it is being cloned.
	struct ClonedCodeInfo {	struct ClonedCodeInfo {
	/// ContainsCalls - This is set to true if the cloned code contains a nor mal	/// ContainsCalls - This is set to true if the cloned code contains a nor mal
	/// call instruction.	/// call instruction.
	bool ContainsCalls;	bool ContainsCalls;


	/// ContainsUnwinds - This is set to true if the cloned code contains an
	/// unwind instruction.
	bool ContainsUnwinds;

	/// ContainsDynamicAllocas - This is set to true if the cloned code conta ins	/// ContainsDynamicAllocas - This is set to true if the cloned code conta ins
	/// a 'dynamic' alloca. Dynamic allocas are allocas that are either not in	/// a 'dynamic' alloca. Dynamic allocas are allocas that are either not in
	/// the entry block or they are in the entry block but are not a constant	/// the entry block or they are in the entry block but are not a constant
	/// size.	/// size.
	bool ContainsDynamicAllocas;	bool ContainsDynamicAllocas;


	ClonedCodeInfo() {	ClonedCodeInfo() : ContainsCalls(false), ContainsDynamicAllocas(false) {}
	ContainsCalls = false;
	ContainsUnwinds = false;
	ContainsDynamicAllocas = false;
	}
	};	};

	/// CloneBasicBlock - Return a copy of the specified basic block, but witho ut	/// CloneBasicBlock - Return a copy of the specified basic block, but witho ut
	/// embedding the block into a particular function. The block returned is an	/// embedding the block into a particular function. The block returned is an
	/// exact copy of the specified basic block, without any remapping having b een	/// exact copy of the specified basic block, without any remapping having b een
	/// performed. Because of this, this is only suitable for applications whe re	/// performed. Because of this, this is only suitable for applications whe re
	/// the basic block will be inserted into the same function that it was clo ned	/// the basic block will be inserted into the same function that it was clo ned
	/// from (loop unrolling would use this, for example).	/// from (loop unrolling would use this, for example).
	///	///
	/// Also, note that this function makes a direct copy of the basic block, a nd	/// Also, note that this function makes a direct copy of the basic block, a nd

	skipping to change at line 136	skipping to change at line 128
	/// CloneFunction - Version of the function that doesn't need the VMap.	/// CloneFunction - Version of the function that doesn't need the VMap.
	///	///
	inline Function CloneFunction(const Function F, ClonedCodeInfo *CodeInfo = 0){	inline Function CloneFunction(const Function F, ClonedCodeInfo *CodeInfo = 0){
	ValueToValueMapTy VMap;	ValueToValueMapTy VMap;
	return CloneFunction(F, VMap, CodeInfo);	return CloneFunction(F, VMap, CodeInfo);
	}	}

	/// Clone OldFunc into NewFunc, transforming the old arguments into referen ces	/// Clone OldFunc into NewFunc, transforming the old arguments into referen ces
	/// to VMap values. Note that if NewFunc already has basic blocks, the one s	/// to VMap values. Note that if NewFunc already has basic blocks, the one s
	/// cloned into it will be added to the end of the function. This function	/// cloned into it will be added to the end of the function. This function

	/// fills in a list of return instructions, and can optionally append the	/// fills in a list of return instructions, and can optionally remap types
	/// specified suffix to all values cloned.	/// and/or append the specified suffix to all values cloned.
	///	///
	/// If ModuleLevelChanges is false, VMap contains no non-identity GlobalVal ue	/// If ModuleLevelChanges is false, VMap contains no non-identity GlobalVal ue
	/// mappings.	/// mappings.
	///	///
	void CloneFunctionInto(Function NewFunc, const Function OldFunc,	void CloneFunctionInto(Function NewFunc, const Function OldFunc,
	ValueToValueMapTy &VMap,	ValueToValueMapTy &VMap,
	bool ModuleLevelChanges,	bool ModuleLevelChanges,
	SmallVectorImpl<ReturnInst*> &Returns,	SmallVectorImpl<ReturnInst*> &Returns,
	const char *NameSuffix = "",	const char *NameSuffix = "",

	ClonedCodeInfo *CodeInfo = 0);	ClonedCodeInfo *CodeInfo = 0,
		ValueMapTypeRemapper *TypeMapper = 0);

	/// CloneAndPruneFunctionInto - This works exactly like CloneFunctionInto,	/// CloneAndPruneFunctionInto - This works exactly like CloneFunctionInto,
	/// except that it does some simple constant prop and DCE on the fly. The	/// except that it does some simple constant prop and DCE on the fly. The
	/// effect of this is to copy significantly less code in cases where (for	/// effect of this is to copy significantly less code in cases where (for
	/// example) a function call with constant arguments is inlined, and those	/// example) a function call with constant arguments is inlined, and those
	/// constant arguments cause a significant amount of code in the callee to be	/// constant arguments cause a significant amount of code in the callee to be
	/// dead. Since this doesn't produce an exactly copy of the input, it can' t be	/// dead. Since this doesn't produce an exactly copy of the input, it can' t be
	/// used for things like CloneFunction or CloneModule.	/// used for things like CloneFunction or CloneModule.
	///	///
	/// If ModuleLevelChanges is false, VMap contains no non-identity GlobalVal ue	/// If ModuleLevelChanges is false, VMap contains no non-identity GlobalVal ue

	skipping to change at line 205	skipping to change at line 198
	/// InlineFunction - This function inlines the called function into the bas ic	/// InlineFunction - This function inlines the called function into the bas ic
	/// block of the caller. This returns false if it is not possible to inlin e	/// block of the caller. This returns false if it is not possible to inlin e
	/// this call. The program is still in a well defined state if this occurs	/// this call. The program is still in a well defined state if this occurs
	/// though.	/// though.
	///	///
	/// Note that this only does one level of inlining. For example, if the	/// Note that this only does one level of inlining. For example, if the
	/// instruction 'call B' is inlined, and 'B' calls 'C', then the call to 'C ' now	/// instruction 'call B' is inlined, and 'B' calls 'C', then the call to 'C ' now
	/// exists in the instruction stream. Similarly this will inline a recursi ve	/// exists in the instruction stream. Similarly this will inline a recursi ve
	/// function by one level.	/// function by one level.
	///	///

	bool InlineFunction(CallInst *C, InlineFunctionInfo &IFI);	bool InlineFunction(CallInst *C, InlineFunctionInfo &IFI, bool InsertLifeti
	bool InlineFunction(InvokeInst *II, InlineFunctionInfo &IFI);	me = true);
	bool InlineFunction(CallSite CS, InlineFunctionInfo &IFI);	bool InlineFunction(InvokeInst *II, InlineFunctionInfo &IFI, bool InsertLif
		etime = true);
		bool InlineFunction(CallSite CS, InlineFunctionInfo &IFI, bool InsertLifeti
		me = true);

	} // End llvm namespace	} // End llvm namespace

	#endif	#endif

End of changes. 5 change blocks.
	15 lines changed or deleted	11 lines changed or added

	CodeGen.h	CodeGen.h

	skipping to change at line 30	skipping to change at line 30
	// Relocation model types.	// Relocation model types.
	namespace Reloc {	namespace Reloc {
	enum Model { Default, Static, PIC_, DynamicNoPIC };	enum Model { Default, Static, PIC_, DynamicNoPIC };
	}	}

	// Code model types.	// Code model types.
	namespace CodeModel {	namespace CodeModel {
	enum Model { Default, JITDefault, Small, Kernel, Medium, Large };	enum Model { Default, JITDefault, Small, Kernel, Medium, Large };
	}	}


		// TLS models.
		namespace TLSModel {
		enum Model {
		GeneralDynamic,
		LocalDynamic,
		InitialExec,
		LocalExec
		};
		}

		// Code generation optimization level.
		namespace CodeGenOpt {
		enum Level {
		None, // -O0
		Less, // -O1
		Default, // -O2, -Os
		Aggressive // -O3
		};
		}

	} // end llvm namespace	} // end llvm namespace

	#endif	#endif

End of changes. 1 change blocks.
	0 lines changed or deleted	20 lines changed or added

	CodeMetrics.h	CodeMetrics.h

	//===- CodeMetrics.h - Measures the weight of a function---------- C++ -- ===//	//===- CodeMetrics.h - Code cost measurements -------------------- C++ -- ===//
	//	//
	// The LLVM Compiler Infrastructure	// The LLVM Compiler Infrastructure
	//	//
	// This file is distributed under the University of Illinois Open Source	// This file is distributed under the University of Illinois Open Source
	// License. See LICENSE.TXT for details.	// License. See LICENSE.TXT for details.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	//	//
	// This file implements various weight measurements for code, helping	// This file implements various weight measurements for code, helping
	// the Inliner and other passes decide whether to duplicate its contents.	// the Inliner and other passes decide whether to duplicate its contents.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_ANALYSIS_CODEMETRICS_H	#ifndef LLVM_ANALYSIS_CODEMETRICS_H
	#define LLVM_ANALYSIS_CODEMETRICS_H	#define LLVM_ANALYSIS_CODEMETRICS_H

	#include "llvm/ADT/DenseMap.h"	#include "llvm/ADT/DenseMap.h"

	namespace llvm {	namespace llvm {

		class BasicBlock;
		class Function;
		class Instruction;
	class TargetData;	class TargetData;

		class Value;


	// CodeMetrics - Calculate size and a few similar metrics for a set of	/// \brief Check whether an instruction is likely to be "free" when lower
	// basic blocks.	ed.
	struct CodeMetrics {	bool isInstructionFree(const Instruction I, const TargetData TD = 0);
	/// NeverInline - True if this callee should never be inlined into a
	/// caller.
	// bool NeverInline;


	// True if this function contains a call to setjmp or _setjmp	/// \brief Check whether a call will lower to something small.
	bool callsSetJmp;	///
		/// This tests checks whether calls to this function will lower to someth
		ing
		/// significantly cheaper than a traditional call, often a single
		/// instruction.
		bool callIsSmall(const Function *F);


	// True if this function calls itself	/// \brief Utility to calculate the size and a few similar metrics for a
		set
		/// of basic blocks.
		struct CodeMetrics {
		/// \brief True if this function contains a call to setjmp or other fun
		ctions
		/// with attribute "returns twice" without having the attribute itself.
		bool exposesReturnsTwice;

		/// \brief True if this function calls itself.
	bool isRecursive;	bool isRecursive;


	// True if this function contains one or more indirect branches	/// \brief True if this function contains one or more indirect branches .
	bool containsIndirectBr;	bool containsIndirectBr;


	/// usesDynamicAlloca - True if this function calls alloca (in the C se nse).	/// \brief True if this function calls alloca (in the C sense).
	bool usesDynamicAlloca;	bool usesDynamicAlloca;


	/// NumInsts, NumBlocks - Keep track of how large each function is, whi	/// \brief Number of instructions in the analyzed blocks.
	ch	unsigned NumInsts;
	/// is used to estimate the code size cost of inlining it.
	unsigned NumInsts, NumBlocks;	/// \brief Number of analyzed blocks.
		unsigned NumBlocks;


	/// NumBBInsts - Keeps track of basic block code size estimates.	/// \brief Keeps track of basic block code size estimates.
	DenseMap<const BasicBlock *, unsigned> NumBBInsts;	DenseMap<const BasicBlock *, unsigned> NumBBInsts;


	/// NumCalls - Keep track of the number of calls to 'big' functions.	/// \brief Keep track of the number of calls to 'big' functions.
	unsigned NumCalls;	unsigned NumCalls;


	/// NumInlineCandidates - Keep track of the number of calls to internal	/// \brief The number of calls to internal functions with a single call
	/// functions with only a single caller. These are likely targets for	er.
	/// future inlining, likely exposed by interleaved devirtualization.	///
		/// These are likely targets for future inlining, likely exposed by
		/// interleaved devirtualization.
	unsigned NumInlineCandidates;	unsigned NumInlineCandidates;


	/// NumVectorInsts - Keep track of how many instructions produce vector	/// \brief How many instructions produce vector values.
	/// values. The inliner is being more aggressive with inlining vector	///
	/// kernels.	/// The inliner is more aggressive with inlining vector kernels.
	unsigned NumVectorInsts;	unsigned NumVectorInsts;


	/// NumRets - Keep track of how many Ret instructions the block contain s.	/// \brief How many 'ret' instructions the blocks contain.
	unsigned NumRets;	unsigned NumRets;


	CodeMetrics() : callsSetJmp(false), isRecursive(false),	CodeMetrics() : exposesReturnsTwice(false), isRecursive(false),
	containsIndirectBr(false), usesDynamicAlloca(false),	containsIndirectBr(false), usesDynamicAlloca(false),
	NumInsts(0), NumBlocks(0), NumCalls(0),	NumInsts(0), NumBlocks(0), NumCalls(0),
	NumInlineCandidates(0), NumVectorInsts(0),	NumInlineCandidates(0), NumVectorInsts(0),
	NumRets(0) {}	NumRets(0) {}


	/// analyzeBasicBlock - Add information about the specified basic block	/// \brief Add information about a block to the current state.
	/// to the current structure.
	void analyzeBasicBlock(const BasicBlock BB, const TargetData TD = 0);	void analyzeBasicBlock(const BasicBlock BB, const TargetData TD = 0);


	/// analyzeFunction - Add information about the specified function	/// \brief Add information about a function to the current state.
	/// to the current structure.
	void analyzeFunction(Function F, const TargetData TD = 0);	void analyzeFunction(Function F, const TargetData TD = 0);


	/// CountCodeReductionForConstant - Figure out an approximation for how
	/// many instructions will be constant folded if the specified value is
	/// constant.
	unsigned CountCodeReductionForConstant(Value *V);

	/// CountBonusForConstant - Figure out an approximation for how much
	/// per-call performance boost we can expect if the specified value is
	/// constant.
	unsigned CountBonusForConstant(Value *V);

	/// CountCodeReductionForAlloca - Figure out an approximation of how mu
	ch
	/// smaller the function will be if it is inlined into a context where
	an
	/// argument becomes an alloca.
	///
	unsigned CountCodeReductionForAlloca(Value *V);
	};	};
	}	}

	#endif	#endif

End of changes. 18 change blocks.
	49 lines changed or deleted	46 lines changed or added

	CommandLine.h	CommandLine.h

	skipping to change at line 43	skipping to change at line 43
	namespace llvm {	namespace llvm {

	/// cl Namespace - This namespace contains all of the command line option	/// cl Namespace - This namespace contains all of the command line option
	/// processing machinery. It is intentionally a short name to make qualifi ed	/// processing machinery. It is intentionally a short name to make qualifi ed
	/// usage concise.	/// usage concise.
	namespace cl {	namespace cl {

	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	// ParseCommandLineOptions - Command line option processing entry point.	// ParseCommandLineOptions - Command line option processing entry point.
	//	//

	void ParseCommandLineOptions(int argc, char **argv,	void ParseCommandLineOptions(int argc, const char * const *argv,
	const char *Overview = 0,	const char *Overview = 0,
	bool ReadResponseFiles = false);	bool ReadResponseFiles = false);

	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	// ParseEnvironmentOptions - Environment variable option processing alterna te	// ParseEnvironmentOptions - Environment variable option processing alterna te
	// entry point.	// entry point.
	//	//
	void ParseEnvironmentOptions(const char progName, const char envvar,	void ParseEnvironmentOptions(const char progName, const char envvar,
	const char *Overview = 0,	const char *Overview = 0,
	bool ReadResponseFiles = false);	bool ReadResponseFiles = false);

	skipping to change at line 85	skipping to change at line 85
	void PrintOptionValues();	void PrintOptionValues();

	// MarkOptionsChanged - Internal helper function.	// MarkOptionsChanged - Internal helper function.
	void MarkOptionsChanged();	void MarkOptionsChanged();

	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	// Flags permitted to be passed to command line arguments	// Flags permitted to be passed to command line arguments
	//	//

	enum NumOccurrencesFlag { // Flags for the number of occurrences allow ed	enum NumOccurrencesFlag { // Flags for the number of occurrences allow ed

	Optional = 0x01, // Zero or One occurrence	Optional = 0x00, // Zero or One occurrence
	ZeroOrMore = 0x02, // Zero or more occurrences allowed	ZeroOrMore = 0x01, // Zero or more occurrences allowed
	Required = 0x03, // One occurrence required	Required = 0x02, // One occurrence required
	OneOrMore = 0x04, // One or more occurrences required	OneOrMore = 0x03, // One or more occurrences required

	// ConsumeAfter - Indicates that this option is fed anything that follows the	// ConsumeAfter - Indicates that this option is fed anything that follows the
	// last positional argument required by the application (it is an error i f	// last positional argument required by the application (it is an error i f
	// there are zero positional arguments, and a ConsumeAfter option is used ).	// there are zero positional arguments, and a ConsumeAfter option is used ).
	// Thus, for example, all arguments to LLI are processed until a filename is	// Thus, for example, all arguments to LLI are processed until a filename is
	// found. Once a filename is found, all of the succeeding arguments are	// found. Once a filename is found, all of the succeeding arguments are
	// passed, unprocessed, to the ConsumeAfter option.	// passed, unprocessed, to the ConsumeAfter option.
	//	//

	ConsumeAfter = 0x05,	ConsumeAfter = 0x04

	OccurrencesMask = 0x07
	};	};

	enum ValueExpected { // Is a value required for the option?	enum ValueExpected { // Is a value required for the option?

	ValueOptional = 0x08, // The value can appear... or not	// zero reserved for the unspecified value
	ValueRequired = 0x10, // The value is required to appear!	ValueOptional = 0x01, // The value can appear... or not
	ValueDisallowed = 0x18, // A value may not be specified (for flags)	ValueRequired = 0x02, // The value is required to appear!
	ValueMask = 0x18	ValueDisallowed = 0x03 // A value may not be specified (for flags)
	};	};

	enum OptionHidden { // Control whether -help shows this option	enum OptionHidden { // Control whether -help shows this option

	NotHidden = 0x20, // Option included in -help & -help-hidden	NotHidden = 0x00, // Option included in -help & -help-hidden
	Hidden = 0x40, // -help doesn't, but -help-hidden does	Hidden = 0x01, // -help doesn't, but -help-hidden does
	ReallyHidden = 0x60, // Neither -help nor -help-hidden show this	ReallyHidden = 0x02 // Neither -help nor -help-hidden show this
	arg	arg
	HiddenMask = 0x60
	};	};

	// Formatting flags - This controls special features that the option might have	// Formatting flags - This controls special features that the option might have
	// that cause it to be parsed differently...	// that cause it to be parsed differently...
	//	//
	// Prefix - This option allows arguments that are otherwise unrecognized to be	// Prefix - This option allows arguments that are otherwise unrecognized to be
	// matched by options that are a prefix of the actual value. This is usefu l for	// matched by options that are a prefix of the actual value. This is usefu l for
	// cases like a linker, where options are typically of the form '-lfoo' or	// cases like a linker, where options are typically of the form '-lfoo' or
	// '-L../../include' where -l or -L are the actual flags. When prefix is	// '-L../../include' where -l or -L are the actual flags. When prefix is
	// enabled, and used, the value for the flag comes from the suffix of the	// enabled, and used, the value for the flag comes from the suffix of the
	// argument.	// argument.
	//	//
	// Grouping - With this option enabled, multiple letter options are allowed to	// Grouping - With this option enabled, multiple letter options are allowed to
	// bunch together with only a single hyphen for the whole group. This allo ws	// bunch together with only a single hyphen for the whole group. This allo ws
	// emulation of the behavior that ls uses for example: ls -la === ls -l -a	// emulation of the behavior that ls uses for example: ls -la === ls -l -a
	//	//

	enum FormattingFlags {	enum FormattingFlags {

	NormalFormatting = 0x000, // Nothing special	NormalFormatting = 0x00, // Nothing special
	Positional = 0x080, // Is a positional argument, no '-' require	Positional = 0x01, // Is a positional argument, no '-' required
	d	Prefix = 0x02, // Can this option directly prefix its value
	Prefix = 0x100, // Can this option directly prefix its valu	?
	e?	Grouping = 0x03 // Can this option group with other options?
	Grouping = 0x180, // Can this option group with other options
	?
	FormattingMask = 0x180 // Union of the above flags.
	};	};

	enum MiscFlags { // Miscellaneous flags to adjust argument	enum MiscFlags { // Miscellaneous flags to adjust argument

	CommaSeparated = 0x200, // Should this cl::list split between commas	CommaSeparated = 0x01, // Should this cl::list split between commas?
	?	PositionalEatsArgs = 0x02, // Should this positional cl::list eat -args?
	PositionalEatsArgs = 0x400, // Should this positional cl::list eat -args	Sink = 0x04 // Should this cl::list eat all unknown optio
	?	ns?
	Sink = 0x800, // Should this cl::list eat all unknown opti
	ons?
	MiscMask = 0xE00 // Union of the above flags.
	};	};

	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	// Option Base class	// Option Base class
	//	//
	class alias;	class alias;
	class Option {	class Option {
	friend class alias;	friend class alias;

	// handleOccurrences - Overriden by subclasses to handle the value passed into	// handleOccurrences - Overriden by subclasses to handle the value passed into

	skipping to change at line 168	skipping to change at line 163
	StringRef Arg) = 0;	StringRef Arg) = 0;

	virtual enum ValueExpected getValueExpectedFlagDefault() const {	virtual enum ValueExpected getValueExpectedFlagDefault() const {
	return ValueOptional;	return ValueOptional;
	}	}

	// Out of line virtual function to provide home for the class.	// Out of line virtual function to provide home for the class.
	virtual void anchor();	virtual void anchor();

	int NumOccurrences; // The number of times specified	int NumOccurrences; // The number of times specified

	int Flags; // Flags for the argument	// Occurrences, HiddenFlag, and Formatting are all enum types but to avoi
		d
		// problems with signed enums in bitfields.
		unsigned Occurrences : 3; // enum NumOccurrencesFlag
		// not using the enum type for 'Value' because zero is an implementation
		// detail representing the non-value
		unsigned Value : 2;
		unsigned HiddenFlag : 2; // enum OptionHidden
		unsigned Formatting : 2; // enum FormattingFlags
		unsigned Misc : 3;
	unsigned Position; // Position of last occurrence of the option	unsigned Position; // Position of last occurrence of the option
	unsigned AdditionalVals;// Greater than 0 for multi-valued option.	unsigned AdditionalVals;// Greater than 0 for multi-valued option.
	Option *NextRegistered; // Singly linked list of registered options.	Option *NextRegistered; // Singly linked list of registered options.
	public:	public:
	const char *ArgStr; // The argument string itself (ex: "help", "o")	const char *ArgStr; // The argument string itself (ex: "help", "o")
	const char *HelpStr; // The descriptive text message for -help	const char *HelpStr; // The descriptive text message for -help
	const char *ValueStr; // String describing what the value of this optio n is	const char *ValueStr; // String describing what the value of this optio n is

	inline enum NumOccurrencesFlag getNumOccurrencesFlag() const {	inline enum NumOccurrencesFlag getNumOccurrencesFlag() const {

	return static_cast<enum NumOccurrencesFlag>(Flags & OccurrencesMask);	return (enum NumOccurrencesFlag)Occurrences;
	}	}
	inline enum ValueExpected getValueExpectedFlag() const {	inline enum ValueExpected getValueExpectedFlag() const {

	int VE = Flags & ValueMask;	return Value ? ((enum ValueExpected)Value)
	return VE ? static_cast<enum ValueExpected>(VE)
	: getValueExpectedFlagDefault();	: getValueExpectedFlagDefault();
	}	}
	inline enum OptionHidden getOptionHiddenFlag() const {	inline enum OptionHidden getOptionHiddenFlag() const {

	return static_cast<enum OptionHidden>(Flags & HiddenMask);	return (enum OptionHidden)HiddenFlag;
	}	}
	inline enum FormattingFlags getFormattingFlag() const {	inline enum FormattingFlags getFormattingFlag() const {

	return static_cast<enum FormattingFlags>(Flags & FormattingMask);	return (enum FormattingFlags)Formatting;
	}	}
	inline unsigned getMiscFlags() const {	inline unsigned getMiscFlags() const {

	return Flags & MiscMask;	return Misc;
	}	}
	inline unsigned getPosition() const { return Position; }	inline unsigned getPosition() const { return Position; }
	inline unsigned getNumAdditionalVals() const { return AdditionalVals; }	inline unsigned getNumAdditionalVals() const { return AdditionalVals; }

	// hasArgStr - Return true if the argstr != ""	// hasArgStr - Return true if the argstr != ""
	bool hasArgStr() const { return ArgStr[0] != 0; }	bool hasArgStr() const { return ArgStr[0] != 0; }

	//----------------------------------------------------------------------- --===	//----------------------------------------------------------------------- --===
	// Accessor functions set by OptionModifiers	// Accessor functions set by OptionModifiers
	//	//
	void setArgStr(const char *S) { ArgStr = S; }	void setArgStr(const char *S) { ArgStr = S; }
	void setDescription(const char *S) { HelpStr = S; }	void setDescription(const char *S) { HelpStr = S; }
	void setValueStr(const char *S) { ValueStr = S; }	void setValueStr(const char *S) { ValueStr = S; }


	void setFlag(unsigned Flag, unsigned FlagMask) {
	Flags &= ~FlagMask;
	Flags \|= Flag;
	}

	void setNumOccurrencesFlag(enum NumOccurrencesFlag Val) {	void setNumOccurrencesFlag(enum NumOccurrencesFlag Val) {

	setFlag(Val, OccurrencesMask);	Occurrences = Val;
	}	}

	void setValueExpectedFlag(enum ValueExpected Val) { setFlag(Val, ValueMas	void setValueExpectedFlag(enum ValueExpected Val) { Value = Val; }
	k); }	void setHiddenFlag(enum OptionHidden Val) { HiddenFlag = Val; }
	void setHiddenFlag(enum OptionHidden Val) { setFlag(Val, HiddenMask); }	void setFormattingFlag(enum FormattingFlags V) { Formatting = V; }
	void setFormattingFlag(enum FormattingFlags V) { setFlag(V, FormattingMas	void setMiscFlag(enum MiscFlags M) { Misc \|= M; }
	k); }
	void setMiscFlag(enum MiscFlags M) { setFlag(M, M); }
	void setPosition(unsigned pos) { Position = pos; }	void setPosition(unsigned pos) { Position = pos; }
	protected:	protected:

	explicit Option(unsigned DefaultFlags)	explicit Option(enum NumOccurrencesFlag Occurrences,
	: NumOccurrences(0), Flags(DefaultFlags \| NormalFormatting), Position(0	enum OptionHidden Hidden)
	),	: NumOccurrences(0), Occurrences(Occurrences), HiddenFlag(Hidden),
		Formatting(NormalFormatting), Position(0),
	AdditionalVals(0), NextRegistered(0),	AdditionalVals(0), NextRegistered(0),
	ArgStr(""), HelpStr(""), ValueStr("") {	ArgStr(""), HelpStr(""), ValueStr("") {

	assert(getNumOccurrencesFlag() != 0 &&
	getOptionHiddenFlag() != 0 && "Not all default flags specified!"
	);
	}	}

	inline void setNumAdditionalVals(unsigned n) { AdditionalVals = n; }	inline void setNumAdditionalVals(unsigned n) { AdditionalVals = n; }
	public:	public:
	// addArgument - Register this argument with the commandline system.	// addArgument - Register this argument with the commandline system.
	//	//
	void addArgument();	void addArgument();

	Option *getNextRegisteredOption() const { return NextRegistered; }	Option *getNextRegisteredOption() const { return NextRegistered; }


	skipping to change at line 323	skipping to change at line 319
	template<class Ty>	template<class Ty>
	LocationClass<Ty> location(Ty &L) { return LocationClass<Ty>(L); }	LocationClass<Ty> location(Ty &L) { return LocationClass<Ty>(L); }

	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	// OptionValue class	// OptionValue class

	// Support value comparison outside the template.	// Support value comparison outside the template.
	struct GenericOptionValue {	struct GenericOptionValue {
	virtual ~GenericOptionValue() {}	virtual ~GenericOptionValue() {}
	virtual bool compare(const GenericOptionValue &V) const = 0;	virtual bool compare(const GenericOptionValue &V) const = 0;

		private:
		virtual void anchor();
	};	};

	template<class DataType> struct OptionValue;	template<class DataType> struct OptionValue;

	// The default value safely does nothing. Option value printing is only	// The default value safely does nothing. Option value printing is only
	// best-effort.	// best-effort.
	template<class DataType, bool isClass>	template<class DataType, bool isClass>
	struct OptionValueBase : public GenericOptionValue {	struct OptionValueBase : public GenericOptionValue {
	// Temporary storage for argument passing.	// Temporary storage for argument passing.
	typedef OptionValue<DataType> WrapperType;	typedef OptionValue<DataType> WrapperType;

	bool hasValue() const { return false; }	bool hasValue() const { return false; }


	const DataType &getValue() const { assert(false && "no default value"); }	const DataType &getValue() const { llvm_unreachable("no default value"); }

	// Some options may take their value from a different data type.	// Some options may take their value from a different data type.
	template<class DT>	template<class DT>
	void setValue(const DT& /V/) {}	void setValue(const DT& /V/) {}

	bool compare(const DataType &/V/) const { return false; }	bool compare(const DataType &/V/) const { return false; }

	virtual bool compare(const GenericOptionValue& /V/) const { return fals e; }	virtual bool compare(const GenericOptionValue& /V/) const { return fals e; }
	};	};


	skipping to change at line 413	skipping to change at line 411

	OptionValue() {}	OptionValue() {}

	OptionValue(const cl::boolOrDefault& V) {	OptionValue(const cl::boolOrDefault& V) {
	this->setValue(V);	this->setValue(V);
	}	}
	OptionValue<cl::boolOrDefault> &operator=(const cl::boolOrDefault& V) {	OptionValue<cl::boolOrDefault> &operator=(const cl::boolOrDefault& V) {
	setValue(V);	setValue(V);
	return *this;	return *this;
	}	}

		private:
		virtual void anchor();
	};	};

	template<>	template<>
	struct OptionValue<std::string> : OptionValueCopy<std::string> {	struct OptionValue<std::string> : OptionValueCopy<std::string> {
	typedef StringRef WrapperType;	typedef StringRef WrapperType;

	OptionValue() {}	OptionValue() {}

	OptionValue(const std::string& V) {	OptionValue(const std::string& V) {
	this->setValue(V);	this->setValue(V);
	}	}
	OptionValue<std::string> &operator=(const std::string& V) {	OptionValue<std::string> &operator=(const std::string& V) {
	setValue(V);	setValue(V);
	return *this;	return *this;
	}	}

		private:
		virtual void anchor();
	};	};

	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	// Enum valued command line option	// Enum valued command line option
	//	//
	#define clEnumVal(ENUMVAL, DESC) #ENUMVAL, int(ENUMVAL), DESC	#define clEnumVal(ENUMVAL, DESC) #ENUMVAL, int(ENUMVAL), DESC
	#define clEnumValN(ENUMVAL, FLAGNAME, DESC) FLAGNAME, int(ENUMVAL), DESC	#define clEnumValN(ENUMVAL, FLAGNAME, DESC) FLAGNAME, int(ENUMVAL), DESC
	#define clEnumValEnd (reinterpret_cast<void*>(0))	#define clEnumValEnd (reinterpret_cast<void*>(0))

	// values - For custom data types, allow specifying a group of values toget her	// values - For custom data types, allow specifying a group of values toget her

	skipping to change at line 1165	skipping to change at line 1167
	ParserClass &getParser() { return Parser; }	ParserClass &getParser() { return Parser; }

	template<class T>	template<class T>
	DataType &operator=(const T &Val) {	DataType &operator=(const T &Val) {
	this->setValue(Val);	this->setValue(Val);
	return this->getValue();	return this->getValue();
	}	}

	// One option...	// One option...
	template<class M0t>	template<class M0t>

	explicit opt(const M0t &M0) : Option(Optional \| NotHidden) {	explicit opt(const M0t &M0) : Option(Optional, NotHidden) {
	apply(M0, this);	apply(M0, this);
	done();	done();
	}	}

	// Two options...	// Two options...
	template<class M0t, class M1t>	template<class M0t, class M1t>

	opt(const M0t &M0, const M1t &M1) : Option(Optional \| NotHidden) {	opt(const M0t &M0, const M1t &M1) : Option(Optional, NotHidden) {
	apply(M0, this); apply(M1, this);	apply(M0, this); apply(M1, this);
	done();	done();
	}	}

	// Three options...	// Three options...
	template<class M0t, class M1t, class M2t>	template<class M0t, class M1t, class M2t>
	opt(const M0t &M0, const M1t &M1,	opt(const M0t &M0, const M1t &M1,

	const M2t &M2) : Option(Optional \| NotHidden) {	const M2t &M2) : Option(Optional, NotHidden) {
	apply(M0, this); apply(M1, this); apply(M2, this);	apply(M0, this); apply(M1, this); apply(M2, this);
	done();	done();
	}	}
	// Four options...	// Four options...
	template<class M0t, class M1t, class M2t, class M3t>	template<class M0t, class M1t, class M2t, class M3t>
	opt(const M0t &M0, const M1t &M1, const M2t &M2,	opt(const M0t &M0, const M1t &M1, const M2t &M2,

	const M3t &M3) : Option(Optional \| NotHidden) {	const M3t &M3) : Option(Optional, NotHidden) {
	apply(M0, this); apply(M1, this); apply(M2, this); apply(M3, this);	apply(M0, this); apply(M1, this); apply(M2, this); apply(M3, this);
	done();	done();
	}	}
	// Five options...	// Five options...
	template<class M0t, class M1t, class M2t, class M3t, class M4t>	template<class M0t, class M1t, class M2t, class M3t, class M4t>
	opt(const M0t &M0, const M1t &M1, const M2t &M2, const M3t &M3,	opt(const M0t &M0, const M1t &M1, const M2t &M2, const M3t &M3,

	const M4t &M4) : Option(Optional \| NotHidden) {	const M4t &M4) : Option(Optional, NotHidden) {
	apply(M0, this); apply(M1, this); apply(M2, this); apply(M3, this);	apply(M0, this); apply(M1, this); apply(M2, this); apply(M3, this);
	apply(M4, this);	apply(M4, this);
	done();	done();
	}	}
	// Six options...	// Six options...
	template<class M0t, class M1t, class M2t, class M3t,	template<class M0t, class M1t, class M2t, class M3t,
	class M4t, class M5t>	class M4t, class M5t>
	opt(const M0t &M0, const M1t &M1, const M2t &M2, const M3t &M3,	opt(const M0t &M0, const M1t &M1, const M2t &M2, const M3t &M3,

	const M4t &M4, const M5t &M5) : Option(Optional \| NotHidden) {	const M4t &M4, const M5t &M5) : Option(Optional, NotHidden) {
	apply(M0, this); apply(M1, this); apply(M2, this); apply(M3, this);	apply(M0, this); apply(M1, this); apply(M2, this); apply(M3, this);
	apply(M4, this); apply(M5, this);	apply(M4, this); apply(M5, this);
	done();	done();
	}	}
	// Seven options...	// Seven options...
	template<class M0t, class M1t, class M2t, class M3t,	template<class M0t, class M1t, class M2t, class M3t,
	class M4t, class M5t, class M6t>	class M4t, class M5t, class M6t>
	opt(const M0t &M0, const M1t &M1, const M2t &M2, const M3t &M3,	opt(const M0t &M0, const M1t &M1, const M2t &M2, const M3t &M3,
	const M4t &M4, const M5t &M5,	const M4t &M4, const M5t &M5,

	const M6t &M6) : Option(Optional \| NotHidden) {	const M6t &M6) : Option(Optional, NotHidden) {
	apply(M0, this); apply(M1, this); apply(M2, this); apply(M3, this);	apply(M0, this); apply(M1, this); apply(M2, this); apply(M3, this);
	apply(M4, this); apply(M5, this); apply(M6, this);	apply(M4, this); apply(M5, this); apply(M6, this);
	done();	done();
	}	}
	// Eight options...	// Eight options...
	template<class M0t, class M1t, class M2t, class M3t,	template<class M0t, class M1t, class M2t, class M3t,
	class M4t, class M5t, class M6t, class M7t>	class M4t, class M5t, class M6t, class M7t>
	opt(const M0t &M0, const M1t &M1, const M2t &M2, const M3t &M3,	opt(const M0t &M0, const M1t &M1, const M2t &M2, const M3t &M3,
	const M4t &M4, const M5t &M5, const M6t &M6,	const M4t &M4, const M5t &M5, const M6t &M6,

	const M7t &M7) : Option(Optional \| NotHidden) {	const M7t &M7) : Option(Optional, NotHidden) {
	apply(M0, this); apply(M1, this); apply(M2, this); apply(M3, this);	apply(M0, this); apply(M1, this); apply(M2, this); apply(M3, this);
	apply(M4, this); apply(M5, this); apply(M6, this); apply(M7, this);	apply(M4, this); apply(M5, this); apply(M6, this); apply(M7, this);
	done();	done();
	}	}
	};	};

	EXTERN_TEMPLATE_INSTANTIATION(class opt<unsigned>);	EXTERN_TEMPLATE_INSTANTIATION(class opt<unsigned>);
	EXTERN_TEMPLATE_INSTANTIATION(class opt<int>);	EXTERN_TEMPLATE_INSTANTIATION(class opt<int>);
	EXTERN_TEMPLATE_INSTANTIATION(class opt<std::string>);	EXTERN_TEMPLATE_INSTANTIATION(class opt<std::string>);
	EXTERN_TEMPLATE_INSTANTIATION(class opt<char>);	EXTERN_TEMPLATE_INSTANTIATION(class opt<char>);

	skipping to change at line 1330	skipping to change at line 1332
	assert(optnum < this->size() && "Invalid option index");	assert(optnum < this->size() && "Invalid option index");
	return Positions[optnum];	return Positions[optnum];
	}	}

	void setNumAdditionalVals(unsigned n) {	void setNumAdditionalVals(unsigned n) {
	Option::setNumAdditionalVals(n);	Option::setNumAdditionalVals(n);
	}	}

	// One option...	// One option...
	template<class M0t>	template<class M0t>

	explicit list(const M0t &M0) : Option(ZeroOrMore \| NotHidden) {	explicit list(const M0t &M0) : Option(ZeroOrMore, NotHidden) {
	apply(M0, this);	apply(M0, this);
	done();	done();
	}	}
	// Two options...	// Two options...
	template<class M0t, class M1t>	template<class M0t, class M1t>

	list(const M0t &M0, const M1t &M1) : Option(ZeroOrMore \| NotHidden) {	list(const M0t &M0, const M1t &M1) : Option(ZeroOrMore, NotHidden) {
	apply(M0, this); apply(M1, this);	apply(M0, this); apply(M1, this);
	done();	done();
	}	}
	// Three options...	// Three options...
	template<class M0t, class M1t, class M2t>	template<class M0t, class M1t, class M2t>
	list(const M0t &M0, const M1t &M1, const M2t &M2)	list(const M0t &M0, const M1t &M1, const M2t &M2)

	: Option(ZeroOrMore \| NotHidden) {	: Option(ZeroOrMore, NotHidden) {
	apply(M0, this); apply(M1, this); apply(M2, this);	apply(M0, this); apply(M1, this); apply(M2, this);
	done();	done();
	}	}
	// Four options...	// Four options...
	template<class M0t, class M1t, class M2t, class M3t>	template<class M0t, class M1t, class M2t, class M3t>
	list(const M0t &M0, const M1t &M1, const M2t &M2, const M3t &M3)	list(const M0t &M0, const M1t &M1, const M2t &M2, const M3t &M3)

	: Option(ZeroOrMore \| NotHidden) {	: Option(ZeroOrMore, NotHidden) {
	apply(M0, this); apply(M1, this); apply(M2, this); apply(M3, this);	apply(M0, this); apply(M1, this); apply(M2, this); apply(M3, this);
	done();	done();
	}	}
	// Five options...	// Five options...
	template<class M0t, class M1t, class M2t, class M3t, class M4t>	template<class M0t, class M1t, class M2t, class M3t, class M4t>
	list(const M0t &M0, const M1t &M1, const M2t &M2, const M3t &M3,	list(const M0t &M0, const M1t &M1, const M2t &M2, const M3t &M3,

	const M4t &M4) : Option(ZeroOrMore \| NotHidden) {	const M4t &M4) : Option(ZeroOrMore, NotHidden) {
	apply(M0, this); apply(M1, this); apply(M2, this); apply(M3, this);	apply(M0, this); apply(M1, this); apply(M2, this); apply(M3, this);
	apply(M4, this);	apply(M4, this);
	done();	done();
	}	}
	// Six options...	// Six options...
	template<class M0t, class M1t, class M2t, class M3t,	template<class M0t, class M1t, class M2t, class M3t,
	class M4t, class M5t>	class M4t, class M5t>
	list(const M0t &M0, const M1t &M1, const M2t &M2, const M3t &M3,	list(const M0t &M0, const M1t &M1, const M2t &M2, const M3t &M3,

	const M4t &M4, const M5t &M5) : Option(ZeroOrMore \| NotHidden) {	const M4t &M4, const M5t &M5) : Option(ZeroOrMore, NotHidden) {
	apply(M0, this); apply(M1, this); apply(M2, this); apply(M3, this);	apply(M0, this); apply(M1, this); apply(M2, this); apply(M3, this);
	apply(M4, this); apply(M5, this);	apply(M4, this); apply(M5, this);
	done();	done();
	}	}
	// Seven options...	// Seven options...
	template<class M0t, class M1t, class M2t, class M3t,	template<class M0t, class M1t, class M2t, class M3t,
	class M4t, class M5t, class M6t>	class M4t, class M5t, class M6t>
	list(const M0t &M0, const M1t &M1, const M2t &M2, const M3t &M3,	list(const M0t &M0, const M1t &M1, const M2t &M2, const M3t &M3,
	const M4t &M4, const M5t &M5, const M6t &M6)	const M4t &M4, const M5t &M5, const M6t &M6)

	: Option(ZeroOrMore \| NotHidden) {	: Option(ZeroOrMore, NotHidden) {
	apply(M0, this); apply(M1, this); apply(M2, this); apply(M3, this);	apply(M0, this); apply(M1, this); apply(M2, this); apply(M3, this);
	apply(M4, this); apply(M5, this); apply(M6, this);	apply(M4, this); apply(M5, this); apply(M6, this);
	done();	done();
	}	}
	// Eight options...	// Eight options...
	template<class M0t, class M1t, class M2t, class M3t,	template<class M0t, class M1t, class M2t, class M3t,
	class M4t, class M5t, class M6t, class M7t>	class M4t, class M5t, class M6t, class M7t>
	list(const M0t &M0, const M1t &M1, const M2t &M2, const M3t &M3,	list(const M0t &M0, const M1t &M1, const M2t &M2, const M3t &M3,
	const M4t &M4, const M5t &M5, const M6t &M6,	const M4t &M4, const M5t &M5, const M6t &M6,

	const M7t &M7) : Option(ZeroOrMore \| NotHidden) {	const M7t &M7) : Option(ZeroOrMore, NotHidden) {
	apply(M0, this); apply(M1, this); apply(M2, this); apply(M3, this);	apply(M0, this); apply(M1, this); apply(M2, this); apply(M3, this);
	apply(M4, this); apply(M5, this); apply(M6, this); apply(M7, this);	apply(M4, this); apply(M5, this); apply(M6, this); apply(M7, this);
	done();	done();
	}	}
	};	};

	// multi_val - Modifier to set the number of additional values.	// multi_val - Modifier to set the number of additional values.
	struct multi_val {	struct multi_val {
	unsigned AdditionalVals;	unsigned AdditionalVals;
	explicit multi_val(unsigned N) : AdditionalVals(N) {}	explicit multi_val(unsigned N) : AdditionalVals(N) {}

	skipping to change at line 1525	skipping to change at line 1527
	public:	public:
	ParserClass &getParser() { return Parser; }	ParserClass &getParser() { return Parser; }

	unsigned getPosition(unsigned optnum) const {	unsigned getPosition(unsigned optnum) const {
	assert(optnum < this->size() && "Invalid option index");	assert(optnum < this->size() && "Invalid option index");
	return Positions[optnum];	return Positions[optnum];
	}	}

	// One option...	// One option...
	template<class M0t>	template<class M0t>

	explicit bits(const M0t &M0) : Option(ZeroOrMore \| NotHidden) {	explicit bits(const M0t &M0) : Option(ZeroOrMore, NotHidden) {
	apply(M0, this);	apply(M0, this);
	done();	done();
	}	}
	// Two options...	// Two options...
	template<class M0t, class M1t>	template<class M0t, class M1t>

	bits(const M0t &M0, const M1t &M1) : Option(ZeroOrMore \| NotHidden) {	bits(const M0t &M0, const M1t &M1) : Option(ZeroOrMore, NotHidden) {
	apply(M0, this); apply(M1, this);	apply(M0, this); apply(M1, this);
	done();	done();
	}	}
	// Three options...	// Three options...
	template<class M0t, class M1t, class M2t>	template<class M0t, class M1t, class M2t>
	bits(const M0t &M0, const M1t &M1, const M2t &M2)	bits(const M0t &M0, const M1t &M1, const M2t &M2)

	: Option(ZeroOrMore \| NotHidden) {	: Option(ZeroOrMore, NotHidden) {
	apply(M0, this); apply(M1, this); apply(M2, this);	apply(M0, this); apply(M1, this); apply(M2, this);
	done();	done();
	}	}
	// Four options...	// Four options...
	template<class M0t, class M1t, class M2t, class M3t>	template<class M0t, class M1t, class M2t, class M3t>
	bits(const M0t &M0, const M1t &M1, const M2t &M2, const M3t &M3)	bits(const M0t &M0, const M1t &M1, const M2t &M2, const M3t &M3)

	: Option(ZeroOrMore \| NotHidden) {	: Option(ZeroOrMore, NotHidden) {
	apply(M0, this); apply(M1, this); apply(M2, this); apply(M3, this);	apply(M0, this); apply(M1, this); apply(M2, this); apply(M3, this);
	done();	done();
	}	}
	// Five options...	// Five options...
	template<class M0t, class M1t, class M2t, class M3t, class M4t>	template<class M0t, class M1t, class M2t, class M3t, class M4t>
	bits(const M0t &M0, const M1t &M1, const M2t &M2, const M3t &M3,	bits(const M0t &M0, const M1t &M1, const M2t &M2, const M3t &M3,

	const M4t &M4) : Option(ZeroOrMore \| NotHidden) {	const M4t &M4) : Option(ZeroOrMore, NotHidden) {
	apply(M0, this); apply(M1, this); apply(M2, this); apply(M3, this);	apply(M0, this); apply(M1, this); apply(M2, this); apply(M3, this);
	apply(M4, this);	apply(M4, this);
	done();	done();
	}	}
	// Six options...	// Six options...
	template<class M0t, class M1t, class M2t, class M3t,	template<class M0t, class M1t, class M2t, class M3t,
	class M4t, class M5t>	class M4t, class M5t>
	bits(const M0t &M0, const M1t &M1, const M2t &M2, const M3t &M3,	bits(const M0t &M0, const M1t &M1, const M2t &M2, const M3t &M3,

	const M4t &M4, const M5t &M5) : Option(ZeroOrMore \| NotHidden) {	const M4t &M4, const M5t &M5) : Option(ZeroOrMore, NotHidden) {
	apply(M0, this); apply(M1, this); apply(M2, this); apply(M3, this);	apply(M0, this); apply(M1, this); apply(M2, this); apply(M3, this);
	apply(M4, this); apply(M5, this);	apply(M4, this); apply(M5, this);
	done();	done();
	}	}
	// Seven options...	// Seven options...
	template<class M0t, class M1t, class M2t, class M3t,	template<class M0t, class M1t, class M2t, class M3t,
	class M4t, class M5t, class M6t>	class M4t, class M5t, class M6t>
	bits(const M0t &M0, const M1t &M1, const M2t &M2, const M3t &M3,	bits(const M0t &M0, const M1t &M1, const M2t &M2, const M3t &M3,
	const M4t &M4, const M5t &M5, const M6t &M6)	const M4t &M4, const M5t &M5, const M6t &M6)

	: Option(ZeroOrMore \| NotHidden) {	: Option(ZeroOrMore, NotHidden) {
	apply(M0, this); apply(M1, this); apply(M2, this); apply(M3, this);	apply(M0, this); apply(M1, this); apply(M2, this); apply(M3, this);
	apply(M4, this); apply(M5, this); apply(M6, this);	apply(M4, this); apply(M5, this); apply(M6, this);
	done();	done();
	}	}
	// Eight options...	// Eight options...
	template<class M0t, class M1t, class M2t, class M3t,	template<class M0t, class M1t, class M2t, class M3t,
	class M4t, class M5t, class M6t, class M7t>	class M4t, class M5t, class M6t, class M7t>
	bits(const M0t &M0, const M1t &M1, const M2t &M2, const M3t &M3,	bits(const M0t &M0, const M1t &M1, const M2t &M2, const M3t &M3,
	const M4t &M4, const M5t &M5, const M6t &M6,	const M4t &M4, const M5t &M5, const M6t &M6,

	const M7t &M7) : Option(ZeroOrMore \| NotHidden) {	const M7t &M7) : Option(ZeroOrMore, NotHidden) {
	apply(M0, this); apply(M1, this); apply(M2, this); apply(M3, this);	apply(M0, this); apply(M1, this); apply(M2, this); apply(M3, this);
	apply(M4, this); apply(M5, this); apply(M6, this); apply(M7, this);	apply(M4, this); apply(M5, this); apply(M6, this); apply(M7, this);
	done();	done();
	}	}
	};	};

	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	// Aliased command line option (alias this name to a preexisting name)	// Aliased command line option (alias this name to a preexisting name)
	//	//


	skipping to change at line 1621	skipping to change at line 1623
	}	}
	public:	public:
	void setAliasFor(Option &O) {	void setAliasFor(Option &O) {
	if (AliasFor)	if (AliasFor)
	error("cl::alias must only have one cl::aliasopt(...) specified!");	error("cl::alias must only have one cl::aliasopt(...) specified!");
	AliasFor = &O;	AliasFor = &O;
	}	}

	// One option...	// One option...
	template<class M0t>	template<class M0t>

	explicit alias(const M0t &M0) : Option(Optional \| Hidden), AliasFor(0) {	explicit alias(const M0t &M0) : Option(Optional, Hidden), AliasFor(0) {
	apply(M0, this);	apply(M0, this);
	done();	done();
	}	}
	// Two options...	// Two options...
	template<class M0t, class M1t>	template<class M0t, class M1t>

	alias(const M0t &M0, const M1t &M1) : Option(Optional \| Hidden), AliasFor (0) {	alias(const M0t &M0, const M1t &M1) : Option(Optional, Hidden), AliasFor( 0) {
	apply(M0, this); apply(M1, this);	apply(M0, this); apply(M1, this);
	done();	done();
	}	}
	// Three options...	// Three options...
	template<class M0t, class M1t, class M2t>	template<class M0t, class M1t, class M2t>
	alias(const M0t &M0, const M1t &M1, const M2t &M2)	alias(const M0t &M0, const M1t &M1, const M2t &M2)

	: Option(Optional \| Hidden), AliasFor(0) {	: Option(Optional, Hidden), AliasFor(0) {
	apply(M0, this); apply(M1, this); apply(M2, this);	apply(M0, this); apply(M1, this); apply(M2, this);
	done();	done();
	}	}
	// Four options...	// Four options...
	template<class M0t, class M1t, class M2t, class M3t>	template<class M0t, class M1t, class M2t, class M3t>
	alias(const M0t &M0, const M1t &M1, const M2t &M2, const M3t &M3)	alias(const M0t &M0, const M1t &M1, const M2t &M2, const M3t &M3)

	: Option(Optional \| Hidden), AliasFor(0) {	: Option(Optional, Hidden), AliasFor(0) {
	apply(M0, this); apply(M1, this); apply(M2, this); apply(M3, this);	apply(M0, this); apply(M1, this); apply(M2, this); apply(M3, this);
	done();	done();
	}	}
	};	};

	// aliasfor - Modifier to set the option an alias aliases.	// aliasfor - Modifier to set the option an alias aliases.
	struct aliasopt {	struct aliasopt {
	Option &Opt;	Option &Opt;
	explicit aliasopt(Option &O) : Opt(O) {}	explicit aliasopt(Option &O) : Opt(O) {}
	void apply(alias &A) const { A.setAliasFor(Opt); }	void apply(alias &A) const { A.setAliasFor(Opt); }

End of changes. 50 change blocks.
	87 lines changed or deleted	82 lines changed or added

	Compiler.h	Compiler.h

	skipping to change at line 52	skipping to change at line 52
	// However, it shouldn't be used for unused variables, as those have a mu ch	// However, it shouldn't be used for unused variables, as those have a mu ch
	// more portable solution:	// more portable solution:
	// (void)unused_var_name;	// (void)unused_var_name;
	// Prefer cast-to-void wherever it is sufficient.	// Prefer cast-to-void wherever it is sufficient.
	#if (__GNUC__ >= 4 \|\| (__GNUC__ == 3 && __GNUC_MINOR__ >= 1))	#if (__GNUC__ >= 4 \|\| (__GNUC__ == 3 && __GNUC_MINOR__ >= 1))
	#define LLVM_ATTRIBUTE_UNUSED __attribute__((__unused__))	#define LLVM_ATTRIBUTE_UNUSED __attribute__((__unused__))
	#else	#else
	#define LLVM_ATTRIBUTE_UNUSED	#define LLVM_ATTRIBUTE_UNUSED
	#endif	#endif


	#ifdef __GNUC__ // aka 'ATTRIBUTE_CONST' but following LLVM Conventions.	#if (__GNUC__ >= 4) && !defined(__MINGW32__) && !defined(__CYGWIN__)
	#define LLVM_ATTRIBUTE_READNONE __attribute__((__const__))	#define LLVM_ATTRIBUTE_WEAK __attribute__((__weak__))
	#else	#else

	#define LLVM_ATTRIBUTE_READNONE	#define LLVM_ATTRIBUTE_WEAK
	#endif	#endif


	#ifdef __GNUC__ // aka 'ATTRIBUTE_PURE' but following LLVM Conventions.	#ifdef __GNUC__ // aka 'CONST' but following LLVM Conventions.
	#define LLVM_ATTRIBUTE_READONLY __attribute__((__pure__))	#define LLVM_READNONE __attribute__((__const__))
	#else	#else

	#define LLVM_ATTRIBUTE_READONLY	#define LLVM_READNONE
		#endif

		#ifdef __GNUC__ // aka 'PURE' but following LLVM Conventions.
		#define LLVM_READONLY __attribute__((__pure__))
		#else
		#define LLVM_READONLY
	#endif	#endif

	#if (__GNUC__ >= 4)	#if (__GNUC__ >= 4)
	#define BUILTIN_EXPECT(EXPR, VALUE) __builtin_expect((EXPR), (VALUE))	#define BUILTIN_EXPECT(EXPR, VALUE) __builtin_expect((EXPR), (VALUE))
	#else	#else
	#define BUILTIN_EXPECT(EXPR, VALUE) (EXPR)	#define BUILTIN_EXPECT(EXPR, VALUE) (EXPR)
	#endif	#endif

	// C++ doesn't support 'extern template' of template specializations. GCC does,	// C++ doesn't support 'extern template' of template specializations. GCC does,
	// but requires __extension__ before it. In the header, use this:	// but requires __extension__ before it. In the header, use this:

	skipping to change at line 113	skipping to change at line 119
	#endif	#endif

	#ifdef __GNUC__	#ifdef __GNUC__
	#define LLVM_ATTRIBUTE_NORETURN __attribute__((noreturn))	#define LLVM_ATTRIBUTE_NORETURN __attribute__((noreturn))
	#elif defined(_MSC_VER)	#elif defined(_MSC_VER)
	#define LLVM_ATTRIBUTE_NORETURN __declspec(noreturn)	#define LLVM_ATTRIBUTE_NORETURN __declspec(noreturn)
	#else	#else
	#define LLVM_ATTRIBUTE_NORETURN	#define LLVM_ATTRIBUTE_NORETURN
	#endif	#endif


		// LLVM_EXTENSION - Support compilers where we have a keyword to suppress
		// pedantic diagnostics.
		#ifdef __GNUC__
		#define LLVM_EXTENSION __extension__
		#else
		#define LLVM_EXTENSION
		#endif

	// LLVM_ATTRIBUTE_DEPRECATED(decl, "message")	// LLVM_ATTRIBUTE_DEPRECATED(decl, "message")
	#if __has_feature(attribute_deprecated_with_message)	#if __has_feature(attribute_deprecated_with_message)
	# define LLVM_ATTRIBUTE_DEPRECATED(decl, message) \	# define LLVM_ATTRIBUTE_DEPRECATED(decl, message) \
	decl __attribute__((deprecated(message)))	decl __attribute__((deprecated(message)))
	#elif defined(__GNUC__)	#elif defined(__GNUC__)
	# define LLVM_ATTRIBUTE_DEPRECATED(decl, message) \	# define LLVM_ATTRIBUTE_DEPRECATED(decl, message) \
	decl __attribute__((deprecated))	decl __attribute__((deprecated))
	#elif defined(_MSC_VER)	#elif defined(_MSC_VER)
	# define LLVM_ATTRIBUTE_DEPRECATED(decl, message) \	# define LLVM_ATTRIBUTE_DEPRECATED(decl, message) \
	__declspec(deprecated(message)) decl	__declspec(deprecated(message)) decl

End of changes. 5 change blocks.
	6 lines changed or deleted	20 lines changed or added

	ConstantFolding.h	ConstantFolding.h

	skipping to change at line 28	skipping to change at line 28
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_ANALYSIS_CONSTANTFOLDING_H	#ifndef LLVM_ANALYSIS_CONSTANTFOLDING_H
	#define LLVM_ANALYSIS_CONSTANTFOLDING_H	#define LLVM_ANALYSIS_CONSTANTFOLDING_H

	namespace llvm {	namespace llvm {
	class Constant;	class Constant;
	class ConstantExpr;	class ConstantExpr;
	class Instruction;	class Instruction;
	class TargetData;	class TargetData;

		class TargetLibraryInfo;
	class Function;	class Function;
	class Type;	class Type;
	template<typename T>	template<typename T>
	class ArrayRef;	class ArrayRef;

	/// ConstantFoldInstruction - Try to constant fold the specified instructio n.	/// ConstantFoldInstruction - Try to constant fold the specified instructio n.
	/// If successful, the constant result is returned, if not, null is returne d.	/// If successful, the constant result is returned, if not, null is returne d.
	/// Note that this fails if not all of the operands are constant. Otherwis e,	/// Note that this fails if not all of the operands are constant. Otherwis e,
	/// this function can only fail when attempting to fold instructions like l oads	/// this function can only fail when attempting to fold instructions like l oads
	/// and stores, which have no constant expression form.	/// and stores, which have no constant expression form.

	Constant ConstantFoldInstruction(Instruction I, const TargetData *TD = 0)	Constant ConstantFoldInstruction(Instruction I, const TargetData *TD = 0,
	;	const TargetLibraryInfo *TLI = 0);

	/// ConstantFoldConstantExpression - Attempt to fold the constant expressio n	/// ConstantFoldConstantExpression - Attempt to fold the constant expressio n
	/// using the specified TargetData. If successful, the constant result is	/// using the specified TargetData. If successful, the constant result is
	/// result is returned, if not, null is returned.	/// result is returned, if not, null is returned.
	Constant ConstantFoldConstantExpression(const ConstantExpr CE,	Constant ConstantFoldConstantExpression(const ConstantExpr CE,

	const TargetData *TD = 0);	const TargetData *TD = 0,
		const TargetLibraryInfo *TLI = 0);

	/// ConstantFoldInstOperands - Attempt to constant fold an instruction with the	/// ConstantFoldInstOperands - Attempt to constant fold an instruction with the
	/// specified operands. If successful, the constant result is returned, if not,	/// specified operands. If successful, the constant result is returned, if not,
	/// null is returned. Note that this function can fail when attempting to	/// null is returned. Note that this function can fail when attempting to
	/// fold instructions like loads and stores, which have no constant express ion	/// fold instructions like loads and stores, which have no constant express ion
	/// form.	/// form.
	///	///
	Constant ConstantFoldInstOperands(unsigned Opcode, Type DestTy,	Constant ConstantFoldInstOperands(unsigned Opcode, Type DestTy,
	ArrayRef<Constant *> Ops,	ArrayRef<Constant *> Ops,

	const TargetData *TD = 0);	const TargetData *TD = 0,
		const TargetLibraryInfo *TLI = 0);

	/// ConstantFoldCompareInstOperands - Attempt to constant fold a compare	/// ConstantFoldCompareInstOperands - Attempt to constant fold a compare
	/// instruction (icmp/fcmp) with the specified operands. If it fails, it	/// instruction (icmp/fcmp) with the specified operands. If it fails, it
	/// returns a constant expression of the specified operands.	/// returns a constant expression of the specified operands.
	///	///
	Constant *ConstantFoldCompareInstOperands(unsigned Predicate,	Constant *ConstantFoldCompareInstOperands(unsigned Predicate,
	Constant LHS, Constant RHS,	Constant LHS, Constant RHS,

	const TargetData *TD = 0);	const TargetData *TD = 0,
		const TargetLibraryInfo *TLI = 0)
		;

	/// ConstantFoldInsertValueInstruction - Attempt to constant fold an insert value	/// ConstantFoldInsertValueInstruction - Attempt to constant fold an insert value
	/// instruction with the specified operands and indices. The constant resu lt is	/// instruction with the specified operands and indices. The constant resu lt is
	/// returned if successful; if not, null is returned.	/// returned if successful; if not, null is returned.
	Constant ConstantFoldInsertValueInstruction(Constant Agg, Constant *Val,	Constant ConstantFoldInsertValueInstruction(Constant Agg, Constant *Val,
	ArrayRef<unsigned> Idxs);	ArrayRef<unsigned> Idxs);

	/// ConstantFoldLoadFromConstPtr - Return the value that a load from C woul d	/// ConstantFoldLoadFromConstPtr - Return the value that a load from C woul d
	/// produce if it is constant and determinable. If this is not determinabl e,	/// produce if it is constant and determinable. If this is not determinabl e,
	/// return null.	/// return null.
	Constant ConstantFoldLoadFromConstPtr(Constant C, const TargetData *TD = 0);	Constant ConstantFoldLoadFromConstPtr(Constant C, const TargetData *TD = 0);

	/// ConstantFoldLoadThroughGEPConstantExpr - Given a constant and a	/// ConstantFoldLoadThroughGEPConstantExpr - Given a constant and a
	/// getelementptr constantexpr, return the constant value being addressed b y the	/// getelementptr constantexpr, return the constant value being addressed b y the
	/// constant expression, or null if something is funny and we can't decide.	/// constant expression, or null if something is funny and we can't decide.
	Constant ConstantFoldLoadThroughGEPConstantExpr(Constant C, ConstantExpr *CE);	Constant ConstantFoldLoadThroughGEPConstantExpr(Constant C, ConstantExpr *CE);


		/// ConstantFoldLoadThroughGEPIndices - Given a constant and getelementptr
		/// indices (with an implied zero pointer index that is not in the list),
		/// return the constant value being addressed by a virtual load, or null if
		/// something is funny and we can't decide.
		Constant ConstantFoldLoadThroughGEPIndices(Constant C,
		ArrayRef<Constant*> Indices);

	/// canConstantFoldCallTo - Return true if its even possible to fold a call to	/// canConstantFoldCallTo - Return true if its even possible to fold a call to
	/// the specified function.	/// the specified function.
	bool canConstantFoldCallTo(const Function *F);	bool canConstantFoldCallTo(const Function *F);

	/// ConstantFoldCall - Attempt to constant fold a call to the specified fun ction	/// ConstantFoldCall - Attempt to constant fold a call to the specified fun ction
	/// with the specified arguments, returning null if unsuccessful.	/// with the specified arguments, returning null if unsuccessful.

	Constant *	Constant ConstantFoldCall(Function F, ArrayRef<Constant *> Operands,
	ConstantFoldCall(Function F, ArrayRef<Constant > Operands);	const TargetLibraryInfo *TLI = 0);
	}	}

	#endif	#endif

End of changes. 7 change blocks.
	7 lines changed or deleted	19 lines changed or added

	Constants.h	Constants.h

	skipping to change at line 37	skipping to change at line 37
	#include "llvm/ADT/APFloat.h"	#include "llvm/ADT/APFloat.h"
	#include "llvm/ADT/ArrayRef.h"	#include "llvm/ADT/ArrayRef.h"

	namespace llvm {	namespace llvm {

	class ArrayType;	class ArrayType;
	class IntegerType;	class IntegerType;
	class StructType;	class StructType;
	class PointerType;	class PointerType;
	class VectorType;	class VectorType;

		class SequentialType;

	template<class ConstantClass, class TypeClass, class ValType>	template<class ConstantClass, class TypeClass, class ValType>
	struct ConstantCreator;	struct ConstantCreator;
	template<class ConstantClass, class TypeClass>	template<class ConstantClass, class TypeClass>

		struct ConstantArrayCreator;
		template<class ConstantClass, class TypeClass>
	struct ConvertConstantType;	struct ConvertConstantType;

	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	/// This is the shared class of boolean and integer constants. This class	/// This is the shared class of boolean and integer constants. This class
	/// represents both boolean and integral constants.	/// represents both boolean and integral constants.
	/// @brief Class for constant integers.	/// @brief Class for constant integers.
	class ConstantInt : public Constant {	class ConstantInt : public Constant {

		virtual void anchor();
	void *operator new(size_t, unsigned); // DO NOT IMPLEMENT	void *operator new(size_t, unsigned); // DO NOT IMPLEMENT
	ConstantInt(const ConstantInt &); // DO NOT IMPLEMENT	ConstantInt(const ConstantInt &); // DO NOT IMPLEMENT
	ConstantInt(IntegerType *Ty, const APInt& V);	ConstantInt(IntegerType *Ty, const APInt& V);
	APInt Val;	APInt Val;
	protected:	protected:
	// allocate space for exactly zero operands	// allocate space for exactly zero operands
	void *operator new(size_t s) {	void *operator new(size_t s) {
	return User::operator new(s, 0);	return User::operator new(s, 0);
	}	}
	public:	public:

	skipping to change at line 231	skipping to change at line 235
	static bool classof(const Value *V) {	static bool classof(const Value *V) {
	return V->getValueID() == ConstantIntVal;	return V->getValueID() == ConstantIntVal;
	}	}
	};	};

	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	/// ConstantFP - Floating Point Values [float, double]	/// ConstantFP - Floating Point Values [float, double]
	///	///
	class ConstantFP : public Constant {	class ConstantFP : public Constant {
	APFloat Val;	APFloat Val;

		virtual void anchor();
	void *operator new(size_t, unsigned);// DO NOT IMPLEMENT	void *operator new(size_t, unsigned);// DO NOT IMPLEMENT
	ConstantFP(const ConstantFP &); // DO NOT IMPLEMENT	ConstantFP(const ConstantFP &); // DO NOT IMPLEMENT
	friend class LLVMContextImpl;	friend class LLVMContextImpl;
	protected:	protected:
	ConstantFP(Type *Ty, const APFloat& V);	ConstantFP(Type *Ty, const APFloat& V);
	protected:	protected:
	// allocate space for exactly zero operands	// allocate space for exactly zero operands
	void *operator new(size_t s) {	void *operator new(size_t s) {
	return User::operator new(s, 0);	return User::operator new(s, 0);
	}	}

	skipping to change at line 298	skipping to change at line 303
	static inline bool classof(const ConstantFP *) { return true; }	static inline bool classof(const ConstantFP *) { return true; }
	static bool classof(const Value *V) {	static bool classof(const Value *V) {
	return V->getValueID() == ConstantFPVal;	return V->getValueID() == ConstantFPVal;
	}	}
	};	};

	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	/// ConstantAggregateZero - All zero aggregate value	/// ConstantAggregateZero - All zero aggregate value
	///	///
	class ConstantAggregateZero : public Constant {	class ConstantAggregateZero : public Constant {

	friend struct ConstantCreator<ConstantAggregateZero, Type, char>;
	void *operator new(size_t, unsigned); // DO NOT IMPL EMENT	void *operator new(size_t, unsigned); // DO NOT IMPL EMENT
	ConstantAggregateZero(const ConstantAggregateZero &); // DO NOT IMPL EMENT	ConstantAggregateZero(const ConstantAggregateZero &); // DO NOT IMPL EMENT
	protected:	protected:
	explicit ConstantAggregateZero(Type *ty)	explicit ConstantAggregateZero(Type *ty)
	: Constant(ty, ConstantAggregateZeroVal, 0, 0) {}	: Constant(ty, ConstantAggregateZeroVal, 0, 0) {}
	protected:	protected:
	// allocate space for exactly zero operands	// allocate space for exactly zero operands
	void *operator new(size_t s) {	void *operator new(size_t s) {
	return User::operator new(s, 0);	return User::operator new(s, 0);
	}	}
	public:	public:

	static ConstantAggregateZero* get(Type *Ty);	static ConstantAggregateZero get(Type Ty);

	virtual void destroyConstant();	virtual void destroyConstant();


		/// getSequentialElement - If this CAZ has array or vector type, return a
		zero
		/// with the right element type.
		Constant *getSequentialElement() const;

		/// getStructElement - If this CAZ has struct type, return a zero with th
		e
		/// right element type for the specified element.
		Constant *getStructElement(unsigned Elt) const;

		/// getElementValue - Return a zero of the right value for the specified
		GEP
		/// index.
		Constant getElementValue(Constant C) const;

		/// getElementValue - Return a zero of the right value for the specified
		GEP
		/// index.
		Constant *getElementValue(unsigned Idx) const;

	/// Methods for support type inquiry through isa, cast, and dyn_cast:	/// Methods for support type inquiry through isa, cast, and dyn_cast:
	///	///
	static bool classof(const ConstantAggregateZero *) { return true; }	static bool classof(const ConstantAggregateZero *) { return true; }
	static bool classof(const Value *V) {	static bool classof(const Value *V) {
	return V->getValueID() == ConstantAggregateZeroVal;	return V->getValueID() == ConstantAggregateZeroVal;
	}	}
	};	};

	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	/// ConstantArray - Constant Array Declarations	/// ConstantArray - Constant Array Declarations
	///	///
	class ConstantArray : public Constant {	class ConstantArray : public Constant {

	friend struct ConstantCreator<ConstantArray, ArrayType,	friend struct ConstantArrayCreator<ConstantArray, ArrayType>;
	std::vector<Constant*> >;
	ConstantArray(const ConstantArray &); // DO NOT IMPLEMENT	ConstantArray(const ConstantArray &); // DO NOT IMPLEMENT
	protected:	protected:
	ConstantArray(ArrayType T, ArrayRef<Constant > Val);	ConstantArray(ArrayType T, ArrayRef<Constant > Val);
	public:	public:
	// ConstantArray accessors	// ConstantArray accessors
	static Constant get(ArrayType T, ArrayRef<Constant*> V);	static Constant get(ArrayType T, ArrayRef<Constant*> V);


	/// This method constructs a ConstantArray and initializes it with a text
	/// string. The default behavior (AddNull==true) causes a null terminator
	to
	/// be placed at the end of the array. This effectively increases the len
	gth
	/// of the array by one (you've been warned). However, in some situation
	s
	/// this is not desired so if AddNull==false then the string is copied wi
	thout
	/// null termination.
	static Constant *get(LLVMContext &Context, StringRef Initializer,
	bool AddNull = true);

	/// Transparently provide more efficient getOperand methods.	/// Transparently provide more efficient getOperand methods.
	DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Constant);	DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Constant);

	/// getType - Specialize the getType() method to always return an ArrayTy pe,	/// getType - Specialize the getType() method to always return an ArrayTy pe,
	/// which reduces the amount of casting needed in parts of the compiler.	/// which reduces the amount of casting needed in parts of the compiler.
	///	///
	inline ArrayType *getType() const {	inline ArrayType *getType() const {
	return reinterpret_cast<ArrayType*>(Value::getType());	return reinterpret_cast<ArrayType*>(Value::getType());
	}	}


	/// isString - This method returns true if the array is an array of i8 an
	d
	/// the elements of the array are all ConstantInt's.
	bool isString() const;

	/// isCString - This method returns true if the array is a string (see
	/// @verbatim
	/// isString) and it ends in a null byte \0 and does not contains any oth
	er
	/// @endverbatim
	/// null bytes except its terminator.
	bool isCString() const;

	/// getAsString - If this array is isString(), then this method converts
	the
	/// array to an std::string and returns it. Otherwise, it asserts out.
	///
	std::string getAsString() const;

	/// getAsCString - If this array is isCString(), then this method convert
	s the
	/// array (without the trailing null byte) to an std::string and returns
	it.
	/// Otherwise, it asserts out.
	///
	std::string getAsCString() const;

	virtual void destroyConstant();	virtual void destroyConstant();
	virtual void replaceUsesOfWithOnConstant(Value From, Value To, Use *U);	virtual void replaceUsesOfWithOnConstant(Value From, Value To, Use *U);

	/// Methods for support type inquiry through isa, cast, and dyn_cast:	/// Methods for support type inquiry through isa, cast, and dyn_cast:
	static inline bool classof(const ConstantArray *) { return true; }	static inline bool classof(const ConstantArray *) { return true; }
	static bool classof(const Value *V) {	static bool classof(const Value *V) {
	return V->getValueID() == ConstantArrayVal;	return V->getValueID() == ConstantArrayVal;
	}	}
	};	};


	skipping to change at line 397	skipping to change at line 385
	struct OperandTraits<ConstantArray> :	struct OperandTraits<ConstantArray> :
	public VariadicOperandTraits<ConstantArray> {	public VariadicOperandTraits<ConstantArray> {
	};	};

	DEFINE_TRANSPARENT_OPERAND_ACCESSORS(ConstantArray, Constant)	DEFINE_TRANSPARENT_OPERAND_ACCESSORS(ConstantArray, Constant)

	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	// ConstantStruct - Constant Struct Declarations	// ConstantStruct - Constant Struct Declarations
	//	//
	class ConstantStruct : public Constant {	class ConstantStruct : public Constant {

	friend struct ConstantCreator<ConstantStruct, StructType,	friend struct ConstantArrayCreator<ConstantStruct, StructType>;
	std::vector<Constant*> >;
	ConstantStruct(const ConstantStruct &); // DO NOT IMPLEMENT	ConstantStruct(const ConstantStruct &); // DO NOT IMPLEMENT
	protected:	protected:
	ConstantStruct(StructType T, ArrayRef<Constant > Val);	ConstantStruct(StructType T, ArrayRef<Constant > Val);
	public:	public:
	// ConstantStruct accessors	// ConstantStruct accessors
	static Constant get(StructType T, ArrayRef<Constant*> V);	static Constant get(StructType T, ArrayRef<Constant*> V);
	static Constant get(StructType T, ...) END_WITH_NULL;	static Constant get(StructType T, ...) END_WITH_NULL;

	/// getAnon - Return an anonymous struct that has the specified	/// getAnon - Return an anonymous struct that has the specified
	/// elements. If the struct is possibly empty, then you must specify a	/// elements. If the struct is possibly empty, then you must specify a

	skipping to change at line 457	skipping to change at line 444
	struct OperandTraits<ConstantStruct> :	struct OperandTraits<ConstantStruct> :
	public VariadicOperandTraits<ConstantStruct> {	public VariadicOperandTraits<ConstantStruct> {
	};	};

	DEFINE_TRANSPARENT_OPERAND_ACCESSORS(ConstantStruct, Constant)	DEFINE_TRANSPARENT_OPERAND_ACCESSORS(ConstantStruct, Constant)

	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	/// ConstantVector - Constant Vector Declarations	/// ConstantVector - Constant Vector Declarations
	///	///
	class ConstantVector : public Constant {	class ConstantVector : public Constant {

	friend struct ConstantCreator<ConstantVector, VectorType,	friend struct ConstantArrayCreator<ConstantVector, VectorType>;
	std::vector<Constant*> >;
	ConstantVector(const ConstantVector &); // DO NOT IMPLEMENT	ConstantVector(const ConstantVector &); // DO NOT IMPLEMENT
	protected:	protected:
	ConstantVector(VectorType T, ArrayRef<Constant > Val);	ConstantVector(VectorType T, ArrayRef<Constant > Val);
	public:	public:
	// ConstantVector accessors	// ConstantVector accessors
	static Constant get(ArrayRef<Constant> V);	static Constant get(ArrayRef<Constant> V);


		/// getSplat - Return a ConstantVector with the specified constant in eac
		h
		/// element.
		static Constant getSplat(unsigned NumElts, Constant Elt);

	/// Transparently provide more efficient getOperand methods.	/// Transparently provide more efficient getOperand methods.
	DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Constant);	DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Constant);

	/// getType - Specialize the getType() method to always return a VectorTy pe,	/// getType - Specialize the getType() method to always return a VectorTy pe,
	/// which reduces the amount of casting needed in parts of the compiler.	/// which reduces the amount of casting needed in parts of the compiler.
	///	///
	inline VectorType *getType() const {	inline VectorType *getType() const {
	return reinterpret_cast<VectorType*>(Value::getType());	return reinterpret_cast<VectorType*>(Value::getType());
	}	}


	/// This function will return true iff every element in this vector const
	ant
	/// is set to all ones.
	/// @returns true iff this constant's emements are all set to all ones.
	/// @brief Determine if the value is all ones.
	bool isAllOnesValue() const;

	/// getSplatValue - If this is a splat constant, meaning that all of the	/// getSplatValue - If this is a splat constant, meaning that all of the
	/// elements have the same value, return that value. Otherwise return NUL L.	/// elements have the same value, return that value. Otherwise return NUL L.
	Constant *getSplatValue() const;	Constant *getSplatValue() const;

	virtual void destroyConstant();	virtual void destroyConstant();
	virtual void replaceUsesOfWithOnConstant(Value From, Value To, Use *U);	virtual void replaceUsesOfWithOnConstant(Value From, Value To, Use *U);

	/// Methods for support type inquiry through isa, cast, and dyn_cast:	/// Methods for support type inquiry through isa, cast, and dyn_cast:
	static inline bool classof(const ConstantVector *) { return true; }	static inline bool classof(const ConstantVector *) { return true; }
	static bool classof(const Value *V) {	static bool classof(const Value *V) {

	skipping to change at line 507	skipping to change at line 491
	struct OperandTraits<ConstantVector> :	struct OperandTraits<ConstantVector> :
	public VariadicOperandTraits<ConstantVector> {	public VariadicOperandTraits<ConstantVector> {
	};	};

	DEFINE_TRANSPARENT_OPERAND_ACCESSORS(ConstantVector, Constant)	DEFINE_TRANSPARENT_OPERAND_ACCESSORS(ConstantVector, Constant)

	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	/// ConstantPointerNull - a constant pointer value that points to null	/// ConstantPointerNull - a constant pointer value that points to null
	///	///
	class ConstantPointerNull : public Constant {	class ConstantPointerNull : public Constant {

	friend struct ConstantCreator<ConstantPointerNull, PointerType, char>;
	void *operator new(size_t, unsigned); // DO NOT IMPLEMEN T	void *operator new(size_t, unsigned); // DO NOT IMPLEMEN T
	ConstantPointerNull(const ConstantPointerNull &); // DO NOT IMPLEMEN T	ConstantPointerNull(const ConstantPointerNull &); // DO NOT IMPLEMEN T
	protected:	protected:
	explicit ConstantPointerNull(PointerType *T)	explicit ConstantPointerNull(PointerType *T)
	: Constant(reinterpret_cast<Type*>(T),	: Constant(reinterpret_cast<Type*>(T),
	Value::ConstantPointerNullVal, 0, 0) {}	Value::ConstantPointerNullVal, 0, 0) {}

	protected:	protected:
	// allocate space for exactly zero operands	// allocate space for exactly zero operands
	void *operator new(size_t s) {	void *operator new(size_t s) {

	skipping to change at line 540	skipping to change at line 523
	return reinterpret_cast<PointerType*>(Value::getType());	return reinterpret_cast<PointerType*>(Value::getType());
	}	}

	/// Methods for support type inquiry through isa, cast, and dyn_cast:	/// Methods for support type inquiry through isa, cast, and dyn_cast:
	static inline bool classof(const ConstantPointerNull *) { return true; }	static inline bool classof(const ConstantPointerNull *) { return true; }
	static bool classof(const Value *V) {	static bool classof(const Value *V) {
	return V->getValueID() == ConstantPointerNullVal;	return V->getValueID() == ConstantPointerNullVal;
	}	}
	};	};


		//===----------------------------------------------------------------------
		===//
		/// ConstantDataSequential - A vector or array constant whose element type
		is a
		/// simple 1/2/4/8-byte integer or float/double, and whose elements are jus
		t
		/// simple data values (i.e. ConstantInt/ConstantFP). This Constant node h
		as no
		/// operands because it stores all of the elements of the constant as dense
		ly
		/// packed data, instead of as Value*'s.
		///
		/// This is the common base class of ConstantDataArray and ConstantDataVect
		or.
		///
		class ConstantDataSequential : public Constant {
		friend class LLVMContextImpl;
		/// DataElements - A pointer to the bytes underlying this constant (which
		is
		/// owned by the uniquing StringMap).
		const char *DataElements;

		/// Next - This forms a link list of ConstantDataSequential nodes that ha
		ve
		/// the same value but different type. For example, 0,0,0,1 could be a 4
		/// element array of i8, or a 1-element array of i32. They'll both end u
		p in
		/// the same StringMap bucket, linked up.
		ConstantDataSequential *Next;
		void *operator new(size_t, unsigned); // DO NOT IMPL
		EMENT
		ConstantDataSequential(const ConstantDataSequential &); // DO NOT IMPL
		EMENT
		protected:
		explicit ConstantDataSequential(Type ty, ValueTy VT, const char Data)
		: Constant(ty, VT, 0, 0), DataElements(Data), Next(0) {}
		~ConstantDataSequential() { delete Next; }

		static Constant getImpl(StringRef Bytes, Type Ty);

		protected:
		// allocate space for exactly zero operands.
		void *operator new(size_t s) {
		return User::operator new(s, 0);
		}
		public:

		/// isElementTypeCompatible - Return true if a ConstantDataSequential can
		be
		/// formed with a vector or array of the specified element type.
		/// ConstantDataArray only works with normal float and int types that are
		/// stored densely in memory, not with things like i42 or x86_f80.
		static bool isElementTypeCompatible(const Type *Ty);

		/// getElementAsInteger - If this is a sequential container of integers (
		of
		/// any size), return the specified element in the low bits of a uint64_t
		.
		uint64_t getElementAsInteger(unsigned i) const;

		/// getElementAsAPFloat - If this is a sequential container of floating p
		oint
		/// type, return the specified element as an APFloat.
		APFloat getElementAsAPFloat(unsigned i) const;

		/// getElementAsFloat - If this is an sequential container of floats, ret
		urn
		/// the specified element as a float.
		float getElementAsFloat(unsigned i) const;

		/// getElementAsDouble - If this is an sequential container of doubles, r
		eturn
		/// the specified element as a double.
		double getElementAsDouble(unsigned i) const;

		/// getElementAsConstant - Return a Constant for a specified index's elem
		ent.
		/// Note that this has to compute a new constant to return, so it isn't a
		s
		/// efficient as getElementAsInteger/Float/Double.
		Constant *getElementAsConstant(unsigned i) const;

		/// getType - Specialize the getType() method to always return a
		/// SequentialType, which reduces the amount of casting needed in parts o
		f the
		/// compiler.
		inline SequentialType *getType() const {
		return reinterpret_cast<SequentialType*>(Value::getType());
		}

		/// getElementType - Return the element type of the array/vector.
		Type *getElementType() const;

		/// getNumElements - Return the number of elements in the array or vector
		.
		unsigned getNumElements() const;

		/// getElementByteSize - Return the size (in bytes) of each element in th
		e
		/// array/vector. The size of the elements is known to be a multiple of
		one
		/// byte.
		uint64_t getElementByteSize() const;

		/// isString - This method returns true if this is an array of i8.
		bool isString() const;

		/// isCString - This method returns true if the array "isString", ends wi
		th a
		/// nul byte, and does not contains any other nul bytes.
		bool isCString() const;

		/// getAsString - If this array is isString(), then this method returns t
		he
		/// array as a StringRef. Otherwise, it asserts out.
		///
		StringRef getAsString() const {
		assert(isString() && "Not a string");
		return getRawDataValues();
		}

		/// getAsCString - If this array is isCString(), then this method returns
		the
		/// array (without the trailing null byte) as a StringRef. Otherwise, it
		/// asserts out.
		///
		StringRef getAsCString() const {
		assert(isCString() && "Isn't a C string");
		StringRef Str = getAsString();
		return Str.substr(0, Str.size()-1);
		}

		/// getRawDataValues - Return the raw, underlying, bytes of this data. N
		ote
		/// that this is an extremely tricky thing to work with, as it exposes th
		e
		/// host endianness of the data elements.
		StringRef getRawDataValues() const;

		virtual void destroyConstant();

		/// Methods for support type inquiry through isa, cast, and dyn_cast:
		///
		static bool classof(const ConstantDataSequential *) { return true; }
		static bool classof(const Value *V) {
		return V->getValueID() == ConstantDataArrayVal \|\|
		V->getValueID() == ConstantDataVectorVal;
		}
		private:
		const char *getElementPointer(unsigned Elt) const;
		};

		//===----------------------------------------------------------------------
		===//
		/// ConstantDataArray - An array constant whose element type is a simple
		/// 1/2/4/8-byte integer or float/double, and whose elements are just simpl
		e
		/// data values (i.e. ConstantInt/ConstantFP). This Constant node has no
		/// operands because it stores all of the elements of the constant as dense
		ly
		/// packed data, instead of as Value*'s.
		class ConstantDataArray : public ConstantDataSequential {
		void *operator new(size_t, unsigned); // DO NOT IMPLEMENT
		ConstantDataArray(const ConstantDataArray &); // DO NOT IMPLEMENT
		virtual void anchor();
		friend class ConstantDataSequential;
		explicit ConstantDataArray(Type ty, const char Data)
		: ConstantDataSequential(ty, ConstantDataArrayVal, Data) {}
		protected:
		// allocate space for exactly zero operands.
		void *operator new(size_t s) {
		return User::operator new(s, 0);
		}
		public:

		/// get() constructors - Return a constant with array type with an elemen
		t
		/// count and element type matching the ArrayRef passed in. Note that th
		is
		/// can return a ConstantAggregateZero object.
		static Constant *get(LLVMContext &Context, ArrayRef<uint8_t> Elts);
		static Constant *get(LLVMContext &Context, ArrayRef<uint16_t> Elts);
		static Constant *get(LLVMContext &Context, ArrayRef<uint32_t> Elts);
		static Constant *get(LLVMContext &Context, ArrayRef<uint64_t> Elts);
		static Constant *get(LLVMContext &Context, ArrayRef<float> Elts);
		static Constant *get(LLVMContext &Context, ArrayRef<double> Elts);

		/// getString - This method constructs a CDS and initializes it with a te
		xt
		/// string. The default behavior (AddNull==true) causes a null terminator
		to
		/// be placed at the end of the array (increasing the length of the strin
		g by
		/// one more than the StringRef would normally indicate. Pass AddNull=fa
		lse
		/// to disable this behavior.
		static Constant *getString(LLVMContext &Context, StringRef Initializer,
		bool AddNull = true);

		/// getType - Specialize the getType() method to always return an ArrayTy
		pe,
		/// which reduces the amount of casting needed in parts of the compiler.
		///
		inline ArrayType *getType() const {
		return reinterpret_cast<ArrayType*>(Value::getType());
		}

		/// Methods for support type inquiry through isa, cast, and dyn_cast:
		///
		static bool classof(const ConstantDataArray *) { return true; }
		static bool classof(const Value *V) {
		return V->getValueID() == ConstantDataArrayVal;
		}
		};

		//===----------------------------------------------------------------------
		===//
		/// ConstantDataVector - A vector constant whose element type is a simple
		/// 1/2/4/8-byte integer or float/double, and whose elements are just simpl
		e
		/// data values (i.e. ConstantInt/ConstantFP). This Constant node has no
		/// operands because it stores all of the elements of the constant as dense
		ly
		/// packed data, instead of as Value*'s.
		class ConstantDataVector : public ConstantDataSequential {
		void *operator new(size_t, unsigned); // DO NOT IMPLEMENT
		ConstantDataVector(const ConstantDataVector &); // DO NOT IMPLEMENT
		virtual void anchor();
		friend class ConstantDataSequential;
		explicit ConstantDataVector(Type ty, const char Data)
		: ConstantDataSequential(ty, ConstantDataVectorVal, Data) {}
		protected:
		// allocate space for exactly zero operands.
		void *operator new(size_t s) {
		return User::operator new(s, 0);
		}
		public:

		/// get() constructors - Return a constant with vector type with an eleme
		nt
		/// count and element type matching the ArrayRef passed in. Note that th
		is
		/// can return a ConstantAggregateZero object.
		static Constant *get(LLVMContext &Context, ArrayRef<uint8_t> Elts);
		static Constant *get(LLVMContext &Context, ArrayRef<uint16_t> Elts);
		static Constant *get(LLVMContext &Context, ArrayRef<uint32_t> Elts);
		static Constant *get(LLVMContext &Context, ArrayRef<uint64_t> Elts);
		static Constant *get(LLVMContext &Context, ArrayRef<float> Elts);
		static Constant *get(LLVMContext &Context, ArrayRef<double> Elts);

		/// getSplat - Return a ConstantVector with the specified constant in eac
		h
		/// element. The specified constant has to be a of a compatible type (i8
		/i16/
		/// i32/i64/float/double) and must be a ConstantFP or ConstantInt.
		static Constant getSplat(unsigned NumElts, Constant Elt);

		/// getSplatValue - If this is a splat constant, meaning that all of the
		/// elements have the same value, return that value. Otherwise return NUL
		L.
		Constant *getSplatValue() const;

		/// getType - Specialize the getType() method to always return a VectorTy
		pe,
		/// which reduces the amount of casting needed in parts of the compiler.
		///
		inline VectorType *getType() const {
		return reinterpret_cast<VectorType*>(Value::getType());
		}

		/// Methods for support type inquiry through isa, cast, and dyn_cast:
		///
		static bool classof(const ConstantDataVector *) { return true; }
		static bool classof(const Value *V) {
		return V->getValueID() == ConstantDataVectorVal;
		}
		};

	/// BlockAddress - The address of a basic block.	/// BlockAddress - The address of a basic block.
	///	///
	class BlockAddress : public Constant {	class BlockAddress : public Constant {
	void *operator new(size_t, unsigned); // DO NOT IMPLEMEN T	void *operator new(size_t, unsigned); // DO NOT IMPLEMEN T
	void *operator new(size_t s) { return User::operator new(s, 2); }	void *operator new(size_t s) { return User::operator new(s, 2); }
	BlockAddress(Function F, BasicBlock BB);	BlockAddress(Function F, BasicBlock BB);
	public:	public:
	/// get - Return a BlockAddress for the specified function and basic bloc k.	/// get - Return a BlockAddress for the specified function and basic bloc k.
	static BlockAddress get(Function F, BasicBlock *BB);	static BlockAddress get(Function F, BasicBlock *BB);


	skipping to change at line 896	skipping to change at line 1110
	/// UndefValue - 'undef' values are things that do not have specified conte nts.	/// UndefValue - 'undef' values are things that do not have specified conte nts.
	/// These are used for a variety of purposes, including global variable	/// These are used for a variety of purposes, including global variable
	/// initializers and operands to instructions. 'undef' values can occur wi th	/// initializers and operands to instructions. 'undef' values can occur wi th
	/// any first-class type.	/// any first-class type.
	///	///
	/// Undef values aren't exactly constants; if they have multiple uses, they	/// Undef values aren't exactly constants; if they have multiple uses, they
	/// can appear to have different bit patterns at each use. See	/// can appear to have different bit patterns at each use. See
	/// LangRef.html#undefvalues for details.	/// LangRef.html#undefvalues for details.
	///	///
	class UndefValue : public Constant {	class UndefValue : public Constant {

	friend struct ConstantCreator<UndefValue, Type, char>;
	void *operator new(size_t, unsigned); // DO NOT IMPLEMENT	void *operator new(size_t, unsigned); // DO NOT IMPLEMENT
	UndefValue(const UndefValue &); // DO NOT IMPLEMENT	UndefValue(const UndefValue &); // DO NOT IMPLEMENT
	protected:	protected:
	explicit UndefValue(Type *T) : Constant(T, UndefValueVal, 0, 0) {}	explicit UndefValue(Type *T) : Constant(T, UndefValueVal, 0, 0) {}
	protected:	protected:
	// allocate space for exactly zero operands	// allocate space for exactly zero operands
	void *operator new(size_t s) {	void *operator new(size_t s) {
	return User::operator new(s, 0);	return User::operator new(s, 0);
	}	}
	public:	public:
	/// get() - Static factory methods - Return an 'undef' object of the spec ified	/// get() - Static factory methods - Return an 'undef' object of the spec ified
	/// type.	/// type.
	///	///
	static UndefValue get(Type T);	static UndefValue get(Type T);


		/// getSequentialElement - If this Undef has array or vector type, return
		a
		/// undef with the right element type.
		UndefValue *getSequentialElement() const;

		/// getStructElement - If this undef has struct type, return a undef with
		the
		/// right element type for the specified element.
		UndefValue *getStructElement(unsigned Elt) const;

		/// getElementValue - Return an undef of the right value for the specifie
		d GEP
		/// index.
		UndefValue getElementValue(Constant C) const;

		/// getElementValue - Return an undef of the right value for the specifie
		d GEP
		/// index.
		UndefValue *getElementValue(unsigned Idx) const;

	virtual void destroyConstant();	virtual void destroyConstant();

	/// Methods for support type inquiry through isa, cast, and dyn_cast:	/// Methods for support type inquiry through isa, cast, and dyn_cast:
	static inline bool classof(const UndefValue *) { return true; }	static inline bool classof(const UndefValue *) { return true; }
	static bool classof(const Value *V) {	static bool classof(const Value *V) {
	return V->getValueID() == UndefValueVal;	return V->getValueID() == UndefValueVal;
	}	}
	};	};

	} // End llvm namespace	} // End llvm namespace

End of changes. 18 change blocks.
	57 lines changed or deleted	332 lines changed or added

	Core.h	Core.h

	skipping to change at line 13	skipping to change at line 13
	\|* The LLVM Compiler Infrastructure *\|	\|* The LLVM Compiler Infrastructure *\|
	\|* *\|	\|* *\|
	\|* This file is distributed under the University of Illinois Open Source *\|	\|* This file is distributed under the University of Illinois Open Source *\|
	\|* License. See LICENSE.TXT for details. *\|	\|* License. See LICENSE.TXT for details. *\|
	\|* *\|	\|* *\|
	\|===---------------------------------------------------------------------- ===\|	\|===---------------------------------------------------------------------- ===\|
	\|* *\|	\|* *\|
	\|* This header declares the C interface to libLLVMCore.a, which implements *\|	\|* This header declares the C interface to libLLVMCore.a, which implements *\|
	\|* the LLVM intermediate representation. *\|	\|* the LLVM intermediate representation. *\|
	\|* *\|	\|* *\|

	\|* LLVM uses a polymorphic type hierarchy which C cannot represent, therefo
	re *\|
	\|* parameters must be passed as base types. Despite the declared types, mos
	t *\|
	\|* of the functions provided operate only on branches of the type hierarchy
	. *\|
	\|* The declared parameter names are descriptive and specify which type is
	*\|
	\|* required. Additionally, each type hierarchy is documented along with the
	*\|
	\|* functions that operate upon it. For more detail, refer to LLVM's C++ cod
	e. *\|
	\|* If in doubt, refer to Core.cpp, which performs paramter downcasts in the
	*\|
	\|* form unwrap<RequiredType>(Param).
	*\|
	\|*
	*\|
	\|* Many exotic languages can interoperate with C code but have a harder tim
	e *\|
	\|* with C++ due to name mangling. So in addition to C, this interface enabl
	es *\|
	\|* tools written in such languages.
	*\|
	\|*
	*\|
	\|* When included into a C++ source file, also declares 'wrap' and 'unwrap'
	*\|
	\|* helpers to perform opaque reference<-->pointer conversions. These helper
	s *\|
	\|* are shorter and more tightly typed than writing the casts by hand when
	*\|
	\|* authoring bindings. In assert builds, they will do runtime type checking
	. *\|
	\|*
	*\|
	\===---------------------------------------------------------------------- ===/	\===---------------------------------------------------------------------- ===/

	#ifndef LLVM_C_CORE_H	#ifndef LLVM_C_CORE_H
	#define LLVM_C_CORE_H	#define LLVM_C_CORE_H

	#include "llvm/Support/DataTypes.h"	#include "llvm/Support/DataTypes.h"

	#ifdef __cplusplus	#ifdef __cplusplus

	/* Need these includes to support the LLVM 'cast' template for the C++ 'wra p'	/* Need these includes to support the LLVM 'cast' template for the C++ 'wra p'
	and 'unwrap' conversion functions. */	and 'unwrap' conversion functions. */
	#include "llvm/Module.h"	#include "llvm/Module.h"
	#include "llvm/PassRegistry.h"	#include "llvm/PassRegistry.h"
	#include "llvm/Support/IRBuilder.h"	#include "llvm/Support/IRBuilder.h"

	extern "C" {	extern "C" {
	#endif	#endif


		/**
		* @defgroup LLVMC LLVM-C: C interface to LLVM
		*
		* This module exposes parts of the LLVM library as a C API.
		*
		* @{
		*/

		/**
		* @defgroup LLVMCTransforms Transforms
		*/

		/**
		* @defgroup LLVMCCore Core
		*
		* This modules provide an interface to libLLVMCore, which implements
		* the LLVM intermediate representation as well as other related types
		* and utilities.
		*
		* LLVM uses a polymorphic type hierarchy which C cannot represent, therefo
		re
		* parameters must be passed as base types. Despite the declared types, mos
		t
		* of the functions provided operate only on branches of the type hierarchy
		.
		* The declared parameter names are descriptive and specify which type is
		* required. Additionally, each type hierarchy is documented along with the
		* functions that operate upon it. For more detail, refer to LLVM's C++ cod
		e.
		* If in doubt, refer to Core.cpp, which performs paramter downcasts in the
		* form unwrap<RequiredType>(Param).
		*
		* Many exotic languages can interoperate with C code but have a harder tim
		e
		* with C++ due to name mangling. So in addition to C, this interface enabl
		es
		* tools written in such languages.
		*
		* When included into a C++ source file, also declares 'wrap' and 'unwrap'
		* helpers to perform opaque reference<-->pointer conversions. These helper
		s
		* are shorter and more tightly typed than writing the casts by hand when
		* authoring bindings. In assert builds, they will do runtime type checking
		.
		*
		* @{
		*/

		/**
		* @defgroup LLVMCCoreTypes Types and Enumerations
		*
		* @{
		*/

	typedef int LLVMBool;	typedef int LLVMBool;

	/* Opaque types. */	/* Opaque types. */

	/**	/**

	* The top-level container for all LLVM global data. See the LLVMContext c lass.	* The top-level container for all LLVM global data. See the LLVMContext cl ass.
	*/	*/
	typedef struct LLVMOpaqueContext *LLVMContextRef;	typedef struct LLVMOpaqueContext *LLVMContextRef;

	/**	/**
	* The top-level container for all other LLVM Intermediate Representation ( IR)	* The top-level container for all other LLVM Intermediate Representation ( IR)

	* objects. See the llvm::Module class.	* objects.
		*
		* @see llvm::Module
	*/	*/
	typedef struct LLVMOpaqueModule *LLVMModuleRef;	typedef struct LLVMOpaqueModule *LLVMModuleRef;

	/**	/**

	* Each value in the LLVM IR has a type, an LLVMTypeRef. See the llvm::Type	* Each value in the LLVM IR has a type, an LLVMTypeRef.
	* class.	*
		* @see llvm::Type
	*/	*/
	typedef struct LLVMOpaqueType *LLVMTypeRef;	typedef struct LLVMOpaqueType *LLVMTypeRef;


		/**
		* Represents an individual value in LLVM IR.
		*
		* This models llvm::Value.
		*/
	typedef struct LLVMOpaqueValue *LLVMValueRef;	typedef struct LLVMOpaqueValue *LLVMValueRef;


		/**
		* Represents a basic block of instruction in LLVM IR.
		*
		* This models llvm::BasicBlock.
		*/
	typedef struct LLVMOpaqueBasicBlock *LLVMBasicBlockRef;	typedef struct LLVMOpaqueBasicBlock *LLVMBasicBlockRef;


		/**
		* Represents an LLVM basic block builder.
		*
		* This models llvm::IRBuilder.
		*/
	typedef struct LLVMOpaqueBuilder *LLVMBuilderRef;	typedef struct LLVMOpaqueBuilder *LLVMBuilderRef;


	/* Interface used to provide a module to JIT or interpreter. This is now j	/**
	ust a	* Interface used to provide a module to JIT or interpreter.
	* synonym for llvm::Module, but we have to keep using the different type t	* This is now just a synonym for llvm::Module, but we have to keep using t
	o	he
	* keep binary compatibility.	* different type to keep binary compatibility.
	*/	*/
	typedef struct LLVMOpaqueModuleProvider *LLVMModuleProviderRef;	typedef struct LLVMOpaqueModuleProvider *LLVMModuleProviderRef;


	/* Used to provide a module to JIT or interpreter.	/**
	* See the llvm::MemoryBuffer class.	* Used to provide a module to JIT or interpreter.
		*
		* @see llvm::MemoryBuffer
	*/	*/
	typedef struct LLVMOpaqueMemoryBuffer *LLVMMemoryBufferRef;	typedef struct LLVMOpaqueMemoryBuffer *LLVMMemoryBufferRef;


	/** See the llvm::PassManagerBase class. */	/** @see llvm::PassManagerBase */
	typedef struct LLVMOpaquePassManager *LLVMPassManagerRef;	typedef struct LLVMOpaquePassManager *LLVMPassManagerRef;


	/** See the llvm::PassRegistry class. */	/** @see llvm::PassRegistry */
	typedef struct LLVMOpaquePassRegistry *LLVMPassRegistryRef;	typedef struct LLVMOpaquePassRegistry *LLVMPassRegistryRef;


	/** Used to get the users and usees of a Value. See the llvm::Use class. */	/**
		* Used to get the users and usees of a Value.
		*
		* @see llvm::Use */
	typedef struct LLVMOpaqueUse *LLVMUseRef;	typedef struct LLVMOpaqueUse *LLVMUseRef;

	typedef enum {	typedef enum {
	LLVMZExtAttribute = 1<<0,	LLVMZExtAttribute = 1<<0,
	LLVMSExtAttribute = 1<<1,	LLVMSExtAttribute = 1<<1,
	LLVMNoReturnAttribute = 1<<2,	LLVMNoReturnAttribute = 1<<2,
	LLVMInRegAttribute = 1<<3,	LLVMInRegAttribute = 1<<3,
	LLVMStructRetAttribute = 1<<4,	LLVMStructRetAttribute = 1<<4,
	LLVMNoUnwindAttribute = 1<<5,	LLVMNoUnwindAttribute = 1<<5,
	LLVMNoAliasAttribute = 1<<6,	LLVMNoAliasAttribute = 1<<6,

	skipping to change at line 121	skipping to change at line 175
	LLVMAlignment = 31<<16,	LLVMAlignment = 31<<16,
	LLVMNoCaptureAttribute = 1<<21,	LLVMNoCaptureAttribute = 1<<21,
	LLVMNoRedZoneAttribute = 1<<22,	LLVMNoRedZoneAttribute = 1<<22,
	LLVMNoImplicitFloatAttribute = 1<<23,	LLVMNoImplicitFloatAttribute = 1<<23,
	LLVMNakedAttribute = 1<<24,	LLVMNakedAttribute = 1<<24,
	LLVMInlineHintAttribute = 1<<25,	LLVMInlineHintAttribute = 1<<25,
	LLVMStackAlignment = 7<<26,	LLVMStackAlignment = 7<<26,
	LLVMReturnsTwice = 1 << 29,	LLVMReturnsTwice = 1 << 29,
	LLVMUWTable = 1 << 30,	LLVMUWTable = 1 << 30,
	LLVMNonLazyBind = 1 << 31	LLVMNonLazyBind = 1 << 31


		// FIXME: This attribute is currently not included in the C API as
		// a temporary measure until the API/ABI impact to the C API is underst
		ood
		// and the path forward agreed upon.
		//LLVMAddressSafety = 1ULL << 32
	} LLVMAttribute;	} LLVMAttribute;

	typedef enum {	typedef enum {
	/* Terminator Instructions */	/* Terminator Instructions */
	LLVMRet = 1,	LLVMRet = 1,
	LLVMBr = 2,	LLVMBr = 2,
	LLVMSwitch = 3,	LLVMSwitch = 3,
	LLVMIndirectBr = 4,	LLVMIndirectBr = 4,
	LLVMInvoke = 5,	LLVMInvoke = 5,
	/* removed 6 due to API changes */	/* removed 6 due to API changes */

	skipping to change at line 197	skipping to change at line 256
	LLVMExtractValue = 53,	LLVMExtractValue = 53,
	LLVMInsertValue = 54,	LLVMInsertValue = 54,

	/* Atomic operators */	/* Atomic operators */
	LLVMFence = 55,	LLVMFence = 55,
	LLVMAtomicCmpXchg = 56,	LLVMAtomicCmpXchg = 56,
	LLVMAtomicRMW = 57,	LLVMAtomicRMW = 57,

	/* Exception Handling Operators */	/* Exception Handling Operators */
	LLVMResume = 58,	LLVMResume = 58,

	LLVMLandingPad = 59,	LLVMLandingPad = 59
	LLVMUnwind = 60

	} LLVMOpcode;	} LLVMOpcode;

	typedef enum {	typedef enum {
	LLVMVoidTypeKind, /*< type with no size /	LLVMVoidTypeKind, /*< type with no size /

		LLVMHalfTypeKind, /*< 16 bit floating point type /
	LLVMFloatTypeKind, /*< 32 bit floating point type /	LLVMFloatTypeKind, /*< 32 bit floating point type /
	LLVMDoubleTypeKind, /*< 64 bit floating point type /	LLVMDoubleTypeKind, /*< 64 bit floating point type /
	LLVMX86_FP80TypeKind, /*< 80 bit floating point type (X87) /	LLVMX86_FP80TypeKind, /*< 80 bit floating point type (X87) /
	LLVMFP128TypeKind, /*< 128 bit floating point type (112-bit mantis sa)/	LLVMFP128TypeKind, /*< 128 bit floating point type (112-bit mantis sa)/
	LLVMPPC_FP128TypeKind, /*< 128 bit floating point type (two 64-bits) /	LLVMPPC_FP128TypeKind, /*< 128 bit floating point type (two 64-bits) /
	LLVMLabelTypeKind, /*< Labels /	LLVMLabelTypeKind, /*< Labels /
	LLVMIntegerTypeKind, /*< Arbitrary bit width integers /	LLVMIntegerTypeKind, /*< Arbitrary bit width integers /
	LLVMFunctionTypeKind, /*< Functions /	LLVMFunctionTypeKind, /*< Functions /
	LLVMStructTypeKind, /*< Structures /	LLVMStructTypeKind, /*< Structures /
	LLVMArrayTypeKind, /*< Arrays /	LLVMArrayTypeKind, /*< Arrays /

	skipping to change at line 295	skipping to change at line 354
	LLVMRealULE, /*< True if unordered, less than, or equal /	LLVMRealULE, /*< True if unordered, less than, or equal /
	LLVMRealUNE, /*< True if unordered or not equal /	LLVMRealUNE, /*< True if unordered or not equal /
	LLVMRealPredicateTrue /*< Always true (always folded) /	LLVMRealPredicateTrue /*< Always true (always folded) /
	} LLVMRealPredicate;	} LLVMRealPredicate;

	typedef enum {	typedef enum {
	LLVMLandingPadCatch, /*< A catch clause /	LLVMLandingPadCatch, /*< A catch clause /
	LLVMLandingPadFilter /*< A filter clause /	LLVMLandingPadFilter /*< A filter clause /
	} LLVMLandingPadClauseTy;	} LLVMLandingPadClauseTy;


		/**
		* @}
		*/

	void LLVMInitializeCore(LLVMPassRegistryRef R);	void LLVMInitializeCore(LLVMPassRegistryRef R);

	/===-- Error handling ---------------------------------------------------- ===/	/===-- Error handling ---------------------------------------------------- ===/

	void LLVMDisposeMessage(char *Message);	void LLVMDisposeMessage(char *Message);


	/*===-- Contexts ----------------------------------------------------------	/**
	===*/	* @defgroup LLVMCCoreContext Contexts
		*
		* Contexts are execution states for the core LLVM IR system.
		*
		* Most types are tied to a context instance. Multiple contexts can
		* exist simultaneously. A single context is not thread safe. However,
		* different contexts can execute on different threads simultaneously.
		*
		* @{
		*/


	/* Create and destroy contexts. */	/**
		* Create a new context.
		*
		* Every call to this function should be paired with a call to
		* LLVMContextDispose() or the context will leak memory.
		*/
	LLVMContextRef LLVMContextCreate(void);	LLVMContextRef LLVMContextCreate(void);


		/**
		* Obtain the global context instance.
		*/
	LLVMContextRef LLVMGetGlobalContext(void);	LLVMContextRef LLVMGetGlobalContext(void);


		/**
		* Destroy a context instance.
		*
		* This should be called for every call to LLVMContextCreate() or memory
		* will be leaked.
		*/
	void LLVMContextDispose(LLVMContextRef C);	void LLVMContextDispose(LLVMContextRef C);

	unsigned LLVMGetMDKindIDInContext(LLVMContextRef C, const char* Name,	unsigned LLVMGetMDKindIDInContext(LLVMContextRef C, const char* Name,
	unsigned SLen);	unsigned SLen);
	unsigned LLVMGetMDKindID(const char* Name, unsigned SLen);	unsigned LLVMGetMDKindID(const char* Name, unsigned SLen);


	/*===-- Modules -----------------------------------------------------------	/**
	===*/	* @}
		*/

		/**
		* @defgroup LLVMCCoreModule Modules
		*
		* Modules represent the top-level structure in a LLVM program. An LLVM
		* module is effectively a translation unit or a collection of
		* translation units merged together.
		*
		* @{
		*/


	/* Create and destroy modules. */	/**
	/** See llvm::Module::Module. */	* Create a new, empty module in the global context.
		*
		* This is equivalent to calling LLVMModuleCreateWithNameInContext with
		* LLVMGetGlobalContext() as the context parameter.
		*
		* Every invocation should be paired with LLVMDisposeModule() or memory
		* will be leaked.
		*/
	LLVMModuleRef LLVMModuleCreateWithName(const char *ModuleID);	LLVMModuleRef LLVMModuleCreateWithName(const char *ModuleID);


		/**
		* Create a new, empty module in a specific context.
		*
		* Every invocation should be paired with LLVMDisposeModule() or memory
		* will be leaked.
		*/
	LLVMModuleRef LLVMModuleCreateWithNameInContext(const char *ModuleID,	LLVMModuleRef LLVMModuleCreateWithNameInContext(const char *ModuleID,
	LLVMContextRef C);	LLVMContextRef C);


	/** See llvm::Module::~Module. */	/**
		* Destroy a module instance.
		*
		* This must be called for every created module or memory will be
		* leaked.
		*/
	void LLVMDisposeModule(LLVMModuleRef M);	void LLVMDisposeModule(LLVMModuleRef M);


	/** Data layout. See Module::getDataLayout. */	/**
		* Obtain the data layout for a module.
		*
		* @see Module::getDataLayout()
		*/
	const char *LLVMGetDataLayout(LLVMModuleRef M);	const char *LLVMGetDataLayout(LLVMModuleRef M);


		/**
		* Set the data layout for a module.
		*
		* @see Module::setDataLayout()
		*/
	void LLVMSetDataLayout(LLVMModuleRef M, const char *Triple);	void LLVMSetDataLayout(LLVMModuleRef M, const char *Triple);


	/** Target triple. See Module::getTargetTriple. */	/**
		* Obtain the target triple for a module.
		*
		* @see Module::getTargetTriple()
		*/
	const char *LLVMGetTarget(LLVMModuleRef M);	const char *LLVMGetTarget(LLVMModuleRef M);


		/**
		* Set the target triple for a module.
		*
		* @see Module::setTargetTriple()
		*/
	void LLVMSetTarget(LLVMModuleRef M, const char *Triple);	void LLVMSetTarget(LLVMModuleRef M, const char *Triple);


	/** See Module::dump. */	/**
		* Dump a representation of a module to stderr.
		*
		* @see Module::dump()
		*/
	void LLVMDumpModule(LLVMModuleRef M);	void LLVMDumpModule(LLVMModuleRef M);


	/** See Module::setModuleInlineAsm. */	/**
		* Set inline assembly for a module.
		*
		* @see Module::setModuleInlineAsm()
		*/
	void LLVMSetModuleInlineAsm(LLVMModuleRef M, const char *Asm);	void LLVMSetModuleInlineAsm(LLVMModuleRef M, const char *Asm);


	/** See Module::getContext. */	/**
		* Obtain the context to which this module is associated.
		*
		* @see Module::getContext()
		*/
	LLVMContextRef LLVMGetModuleContext(LLVMModuleRef M);	LLVMContextRef LLVMGetModuleContext(LLVMModuleRef M);


	/*===-- Types -------------------------------------------------------------	/**
	===*/	* Obtain a Type from a module by its registered name.
		*/
		LLVMTypeRef LLVMGetTypeByName(LLVMModuleRef M, const char *Name);

		/**
		* Obtain the number of operands for named metadata in a module.
		*
		* @see llvm::Module::getNamedMetadata()
		*/
		unsigned LLVMGetNamedMetadataNumOperands(LLVMModuleRef M, const char* name)
		;

		/**
		* Obtain the named metadata operands for a module.
		*
		* The passed LLVMValueRef pointer should refer to an array of
		* LLVMValueRef at least LLVMGetNamedMetadataNumOperands long. This
		* array will be populated with the LLVMValueRef instances. Each
		* instance corresponds to a llvm::MDNode.
		*
		* @see llvm::Module::getNamedMetadata()
		* @see llvm::MDNode::getOperand()
		*/
		void LLVMGetNamedMetadataOperands(LLVMModuleRef M, const char* name, LLVMVa
		lueRef *Dest);

		/**
		* Add an operand to named metadata.
		*
		* @see llvm::Module::getNamedMetadata()
		* @see llvm::MDNode::addOperand()
		*/
		void LLVMAddNamedMetadataOperand(LLVMModuleRef M, const char* name,
		LLVMValueRef Val);

		/**
		* Add a function to a module under a specified name.
		*
		* @see llvm::Function::Create()
		*/
		LLVMValueRef LLVMAddFunction(LLVMModuleRef M, const char *Name,
		LLVMTypeRef FunctionTy);

		/**
		* Obtain a Function value from a Module by its name.
		*
		* The returned value corresponds to a llvm::Function value.
		*
		* @see llvm::Module::getFunction()
		*/
		LLVMValueRef LLVMGetNamedFunction(LLVMModuleRef M, const char *Name);

		/**
		* Obtain an iterator to the first Function in a Module.
		*
		* @see llvm::Module::begin()
		*/
		LLVMValueRef LLVMGetFirstFunction(LLVMModuleRef M);

		/**
		* Obtain an iterator to the last Function in a Module.
		*
		* @see llvm::Module::end()
		*/
		LLVMValueRef LLVMGetLastFunction(LLVMModuleRef M);

		/**
		* Advance a Function iterator to the next Function.
		*
		* Returns NULL if the iterator was already at the end and there are no mor
		e
		* functions.
		*/
		LLVMValueRef LLVMGetNextFunction(LLVMValueRef Fn);

		/**
		* Decrement a Function iterator to the previous Function.
		*
		* Returns NULL if the iterator was already at the beginning and there are
		* no previous functions.
		*/
		LLVMValueRef LLVMGetPreviousFunction(LLVMValueRef Fn);

		/**
		* @}
		*/


	/* LLVM types conform to the following hierarchy:	/**
		* @defgroup LLVMCCoreType Types
		*
		* Types represent the type of a value.
		*
		* Types are associated with a context instance. The context internally
		* deduplicates types so there is only 1 instance of a specific type
		* alive at a time. In other words, a unique type is shared among all
		* consumers within a context.
		*
		* A Type in the C API corresponds to llvm::Type.
		*
		* Types have the following hierarchy:
	*	*
	* types:	* types:
	* integer type	* integer type
	* real type	* real type
	* function type	* function type
	* sequence types:	* sequence types:
	* array type	* array type
	* pointer type	* pointer type
	* vector type	* vector type
	* void type	* void type
	* label type	* label type
	* opaque type	* opaque type

		*
		* @{
	*/	*/


	/** See llvm::LLVMTypeKind::getTypeID. */	/**
		* Obtain the enumerated type of a Type instance.
		*
		* @see llvm::Type:getTypeID()
		*/
	LLVMTypeKind LLVMGetTypeKind(LLVMTypeRef Ty);	LLVMTypeKind LLVMGetTypeKind(LLVMTypeRef Ty);


		/**
		* Whether the type has a known size.
		*
		* Things that don't have a size are abstract types, labels, and void.a
		*
		* @see llvm::Type::isSized()
		*/
	LLVMBool LLVMTypeIsSized(LLVMTypeRef Ty);	LLVMBool LLVMTypeIsSized(LLVMTypeRef Ty);


	/** See llvm::LLVMType::getContext. */	/**
		* Obtain the context to which this type instance is associated.
		*
		* @see llvm::Type::getContext()
		*/
	LLVMContextRef LLVMGetTypeContext(LLVMTypeRef Ty);	LLVMContextRef LLVMGetTypeContext(LLVMTypeRef Ty);


	/* Operations on integer types */	/**
		* @defgroup LLVMCCoreTypeInt Integer Types
		*
		* Functions in this section operate on integer types.
		*
		* @{
		*/

		/**
		* Obtain an integer type from a context with specified bit width.
		*/
	LLVMTypeRef LLVMInt1TypeInContext(LLVMContextRef C);	LLVMTypeRef LLVMInt1TypeInContext(LLVMContextRef C);
	LLVMTypeRef LLVMInt8TypeInContext(LLVMContextRef C);	LLVMTypeRef LLVMInt8TypeInContext(LLVMContextRef C);
	LLVMTypeRef LLVMInt16TypeInContext(LLVMContextRef C);	LLVMTypeRef LLVMInt16TypeInContext(LLVMContextRef C);
	LLVMTypeRef LLVMInt32TypeInContext(LLVMContextRef C);	LLVMTypeRef LLVMInt32TypeInContext(LLVMContextRef C);
	LLVMTypeRef LLVMInt64TypeInContext(LLVMContextRef C);	LLVMTypeRef LLVMInt64TypeInContext(LLVMContextRef C);
	LLVMTypeRef LLVMIntTypeInContext(LLVMContextRef C, unsigned NumBits);	LLVMTypeRef LLVMIntTypeInContext(LLVMContextRef C, unsigned NumBits);


		/**
		* Obtain an integer type from the global context with a specified bit
		* width.
		*/
	LLVMTypeRef LLVMInt1Type(void);	LLVMTypeRef LLVMInt1Type(void);
	LLVMTypeRef LLVMInt8Type(void);	LLVMTypeRef LLVMInt8Type(void);
	LLVMTypeRef LLVMInt16Type(void);	LLVMTypeRef LLVMInt16Type(void);
	LLVMTypeRef LLVMInt32Type(void);	LLVMTypeRef LLVMInt32Type(void);
	LLVMTypeRef LLVMInt64Type(void);	LLVMTypeRef LLVMInt64Type(void);
	LLVMTypeRef LLVMIntType(unsigned NumBits);	LLVMTypeRef LLVMIntType(unsigned NumBits);
	unsigned LLVMGetIntTypeWidth(LLVMTypeRef IntegerTy);	unsigned LLVMGetIntTypeWidth(LLVMTypeRef IntegerTy);


	/* Operations on real types */	/**
		* @}
		*/

		/**
		* @defgroup LLVMCCoreTypeFloat Floating Point Types
		*
		* @{
		*/

		/**
		* Obtain a 16-bit floating point type from a context.
		*/
		LLVMTypeRef LLVMHalfTypeInContext(LLVMContextRef C);

		/**
		* Obtain a 32-bit floating point type from a context.
		*/
	LLVMTypeRef LLVMFloatTypeInContext(LLVMContextRef C);	LLVMTypeRef LLVMFloatTypeInContext(LLVMContextRef C);


		/**
		* Obtain a 64-bit floating point type from a context.
		*/
	LLVMTypeRef LLVMDoubleTypeInContext(LLVMContextRef C);	LLVMTypeRef LLVMDoubleTypeInContext(LLVMContextRef C);


		/**
		* Obtain a 80-bit floating point type (X87) from a context.
		*/
	LLVMTypeRef LLVMX86FP80TypeInContext(LLVMContextRef C);	LLVMTypeRef LLVMX86FP80TypeInContext(LLVMContextRef C);


		/**
		* Obtain a 128-bit floating point type (112-bit mantissa) from a
		* context.
		*/
	LLVMTypeRef LLVMFP128TypeInContext(LLVMContextRef C);	LLVMTypeRef LLVMFP128TypeInContext(LLVMContextRef C);


		/**
		* Obtain a 128-bit floating point type (two 64-bits) from a context.
		*/
	LLVMTypeRef LLVMPPCFP128TypeInContext(LLVMContextRef C);	LLVMTypeRef LLVMPPCFP128TypeInContext(LLVMContextRef C);


		/**
		* Obtain a floating point type from the global context.
		*
		* These map to the functions in this group of the same name.
		*/
		LLVMTypeRef LLVMHalfType(void);
	LLVMTypeRef LLVMFloatType(void);	LLVMTypeRef LLVMFloatType(void);
	LLVMTypeRef LLVMDoubleType(void);	LLVMTypeRef LLVMDoubleType(void);
	LLVMTypeRef LLVMX86FP80Type(void);	LLVMTypeRef LLVMX86FP80Type(void);
	LLVMTypeRef LLVMFP128Type(void);	LLVMTypeRef LLVMFP128Type(void);
	LLVMTypeRef LLVMPPCFP128Type(void);	LLVMTypeRef LLVMPPCFP128Type(void);


	/* Operations on function types */	/**
		* @}
		*/

		/**
		* @defgroup LLVMCCoreTypeFunction Function Types
		*
		* @{
		*/

		/**
		* Obtain a function type consisting of a specified signature.
		*
		* The function is defined as a tuple of a return Type, a list of
		* parameter types, and whether the function is variadic.
		*/
	LLVMTypeRef LLVMFunctionType(LLVMTypeRef ReturnType,	LLVMTypeRef LLVMFunctionType(LLVMTypeRef ReturnType,
	LLVMTypeRef *ParamTypes, unsigned ParamCount,	LLVMTypeRef *ParamTypes, unsigned ParamCount,
	LLVMBool IsVarArg);	LLVMBool IsVarArg);


		/**
		* Returns whether a function type is variadic.
		*/
	LLVMBool LLVMIsFunctionVarArg(LLVMTypeRef FunctionTy);	LLVMBool LLVMIsFunctionVarArg(LLVMTypeRef FunctionTy);


		/**
		* Obtain the Type this function Type returns.
		*/
	LLVMTypeRef LLVMGetReturnType(LLVMTypeRef FunctionTy);	LLVMTypeRef LLVMGetReturnType(LLVMTypeRef FunctionTy);


		/**
		* Obtain the number of parameters this function accepts.
		*/
	unsigned LLVMCountParamTypes(LLVMTypeRef FunctionTy);	unsigned LLVMCountParamTypes(LLVMTypeRef FunctionTy);


		/**
		* Obtain the types of a function's parameters.
		*
		* The Dest parameter should point to a pre-allocated array of
		* LLVMTypeRef at least LLVMCountParamTypes() large. On return, the
		* first LLVMCountParamTypes() entries in the array will be populated
		* with LLVMTypeRef instances.
		*
		* @param FunctionTy The function type to operate on.
		* @param Dest Memory address of an array to be filled with result.
		*/
	void LLVMGetParamTypes(LLVMTypeRef FunctionTy, LLVMTypeRef *Dest);	void LLVMGetParamTypes(LLVMTypeRef FunctionTy, LLVMTypeRef *Dest);


	/* Operations on struct types */	/**
		* @}
		*/

		/**
		* @defgroup LLVMCCoreTypeStruct Structure Types
		*
		* These functions relate to LLVMTypeRef instances.
		*
		* @see llvm::StructType
		*
		* @{
		*/

		/**
		* Create a new structure type in a context.
		*
		* A structure is specified by a list of inner elements/types and
		* whether these can be packed together.
		*
		* @see llvm::StructType::create()
		*/
	LLVMTypeRef LLVMStructTypeInContext(LLVMContextRef C, LLVMTypeRef *ElementT ypes,	LLVMTypeRef LLVMStructTypeInContext(LLVMContextRef C, LLVMTypeRef *ElementT ypes,
	unsigned ElementCount, LLVMBool Packed) ;	unsigned ElementCount, LLVMBool Packed) ;


		/**
		* Create a new structure type in the global context.
		*
		* @see llvm::StructType::create()
		*/
	LLVMTypeRef LLVMStructType(LLVMTypeRef *ElementTypes, unsigned ElementCount ,	LLVMTypeRef LLVMStructType(LLVMTypeRef *ElementTypes, unsigned ElementCount ,
	LLVMBool Packed);	LLVMBool Packed);


		/**
		* Create an empty structure in a context having a specified name.
		*
		* @see llvm::StructType::create()
		*/
	LLVMTypeRef LLVMStructCreateNamed(LLVMContextRef C, const char *Name);	LLVMTypeRef LLVMStructCreateNamed(LLVMContextRef C, const char *Name);

	const char *LLVMGetStructName(LLVMTypeRef Ty);
	void LLVMStructSetBody(LLVMTypeRef StructTy, LLVMTypeRef *ElementTypes,
	unsigned ElementCount, LLVMBool Packed);


	unsigned LLVMCountStructElementTypes(LLVMTypeRef StructTy);	/**
		* Obtain the name of a structure.
		*
		* @see llvm::StructType::getName()
		*/
		const char *LLVMGetStructName(LLVMTypeRef Ty);

		/**
		* Set the contents of a structure type.
		*
		* @see llvm::StructType::setBody()
		*/
		void LLVMStructSetBody(LLVMTypeRef StructTy, LLVMTypeRef *ElementTypes,
		unsigned ElementCount, LLVMBool Packed);

		/**
		* Get the number of elements defined inside the structure.
		*
		* @see llvm::StructType::getNumElements()
		*/
		unsigned LLVMCountStructElementTypes(LLVMTypeRef StructTy);

		/**
		* Get the elements within a structure.
		*
		* The function is passed the address of a pre-allocated array of
		* LLVMTypeRef at least LLVMCountStructElementTypes() long. After
		* invocation, this array will be populated with the structure's
		* elements. The objects in the destination array will have a lifetime
		* of the structure type itself, which is the lifetime of the context it
		* is contained in.
		*/
	void LLVMGetStructElementTypes(LLVMTypeRef StructTy, LLVMTypeRef *Dest);	void LLVMGetStructElementTypes(LLVMTypeRef StructTy, LLVMTypeRef *Dest);


		/**
		* Determine whether a structure is packed.
		*
		* @see llvm::StructType::isPacked()
		*/
	LLVMBool LLVMIsPackedStruct(LLVMTypeRef StructTy);	LLVMBool LLVMIsPackedStruct(LLVMTypeRef StructTy);


		/**
		* Determine whether a structure is opaque.
		*
		* @see llvm::StructType::isOpaque()
		*/
	LLVMBool LLVMIsOpaqueStruct(LLVMTypeRef StructTy);	LLVMBool LLVMIsOpaqueStruct(LLVMTypeRef StructTy);


	LLVMTypeRef LLVMGetTypeByName(LLVMModuleRef M, const char *Name);	/**
		* @}
		*/


	/* Operations on array, pointer, and vector types (sequence types) */	/**
	LLVMTypeRef LLVMArrayType(LLVMTypeRef ElementType, unsigned ElementCount);	* @defgroup LLVMCCoreTypeSequential Sequential Types
	LLVMTypeRef LLVMPointerType(LLVMTypeRef ElementType, unsigned AddressSpace)	*
	;	* Sequential types represents "arrays" of types. This is a super class
	LLVMTypeRef LLVMVectorType(LLVMTypeRef ElementType, unsigned ElementCount);	* for array, vector, and pointer types.
		*
		* @{
		*/


		/**
		* Obtain the type of elements within a sequential type.
		*
		* This works on array, vector, and pointer types.
		*
		* @see llvm::SequentialType::getElementType()
		*/
	LLVMTypeRef LLVMGetElementType(LLVMTypeRef Ty);	LLVMTypeRef LLVMGetElementType(LLVMTypeRef Ty);


		/**
		* Create a fixed size array type that refers to a specific type.
		*
		* The created type will exist in the context that its element type
		* exists in.
		*
		* @see llvm::ArrayType::get()
		*/
		LLVMTypeRef LLVMArrayType(LLVMTypeRef ElementType, unsigned ElementCount);

		/**
		* Obtain the length of an array type.
		*
		* This only works on types that represent arrays.
		*
		* @see llvm::ArrayType::getNumElements()
		*/
	unsigned LLVMGetArrayLength(LLVMTypeRef ArrayTy);	unsigned LLVMGetArrayLength(LLVMTypeRef ArrayTy);


		/**
		* Create a pointer type that points to a defined type.
		*
		* The created type will exist in the context that its pointee type
		* exists in.
		*
		* @see llvm::PointerType::get()
		*/
		LLVMTypeRef LLVMPointerType(LLVMTypeRef ElementType, unsigned AddressSpace)
		;

		/**
		* Obtain the address space of a pointer type.
		*
		* This only works on types that represent pointers.
		*
		* @see llvm::PointerType::getAddressSpace()
		*/
	unsigned LLVMGetPointerAddressSpace(LLVMTypeRef PointerTy);	unsigned LLVMGetPointerAddressSpace(LLVMTypeRef PointerTy);


		/**
		* Create a vector type that contains a defined type and has a specific
		* number of elements.
		*
		* The created type will exist in the context thats its element type
		* exists in.
		*
		* @see llvm::VectorType::get()
		*/
		LLVMTypeRef LLVMVectorType(LLVMTypeRef ElementType, unsigned ElementCount);

		/**
		* Obtain the number of elements in a vector type.
		*
		* This only works on types that represent vectors.
		*
		* @see llvm::VectorType::getNumElements()
		*/
	unsigned LLVMGetVectorSize(LLVMTypeRef VectorTy);	unsigned LLVMGetVectorSize(LLVMTypeRef VectorTy);


	/* Operations on other types */	/**
		* @}
		*/

		/**
		* @defgroup LLVMCCoreTypeOther Other Types
		*
		* @{
		*/

		/**
		* Create a void type in a context.
		*/
	LLVMTypeRef LLVMVoidTypeInContext(LLVMContextRef C);	LLVMTypeRef LLVMVoidTypeInContext(LLVMContextRef C);


		/**
		* Create a label type in a context.
		*/
	LLVMTypeRef LLVMLabelTypeInContext(LLVMContextRef C);	LLVMTypeRef LLVMLabelTypeInContext(LLVMContextRef C);


		/**
		* Create a X86 MMX type in a context.
		*/
	LLVMTypeRef LLVMX86MMXTypeInContext(LLVMContextRef C);	LLVMTypeRef LLVMX86MMXTypeInContext(LLVMContextRef C);


		/**
		* These are similar to the above functions except they operate on the
		* global context.
		*/
	LLVMTypeRef LLVMVoidType(void);	LLVMTypeRef LLVMVoidType(void);
	LLVMTypeRef LLVMLabelType(void);	LLVMTypeRef LLVMLabelType(void);
	LLVMTypeRef LLVMX86MMXType(void);	LLVMTypeRef LLVMX86MMXType(void);


	/*===-- Values ------------------------------------------------------------	/**
	===*/	* @}
		*/

		/**
		* @}
		*/


	/* The bulk of LLVM's object model consists of values, which comprise a ver	/**
	y	* @defgroup LLVMCCoreValues Values
		*
		* The bulk of LLVM's object model consists of values, which comprise a ver
		y
	* rich type hierarchy.	* rich type hierarchy.

		*
		* LLVMValueRef essentially represents llvm::Value. There is a rich
		* hierarchy of classes within this type. Depending on the instance
		* obtain, not all APIs are available.
		*
		* Callers can determine the type of a LLVMValueRef by calling the
		* LLVMIsA* family of functions (e.g. LLVMIsAArgument()). These
		* functions are defined by a macro, so it isn't obvious which are
		* available by looking at the Doxygen source code. Instead, look at the
		* source definition of LLVM_FOR_EACH_VALUE_SUBCLASS and note the list
		* of value names given. These value names also correspond to classes in
		* the llvm::Value hierarchy.
		*
		* @{
	*/	*/

	#define LLVM_FOR_EACH_VALUE_SUBCLASS(macro) \	#define LLVM_FOR_EACH_VALUE_SUBCLASS(macro) \
	macro(Argument) \	macro(Argument) \
	macro(BasicBlock) \	macro(BasicBlock) \
	macro(InlineAsm) \	macro(InlineAsm) \
	macro(MDNode) \	macro(MDNode) \
	macro(MDString) \	macro(MDString) \
	macro(User) \	macro(User) \
	macro(Constant) \	macro(Constant) \

	skipping to change at line 472	skipping to change at line 1018
	macro(Function) \	macro(Function) \
	macro(GlobalAlias) \	macro(GlobalAlias) \
	macro(GlobalVariable) \	macro(GlobalVariable) \
	macro(UndefValue) \	macro(UndefValue) \
	macro(Instruction) \	macro(Instruction) \
	macro(BinaryOperator) \	macro(BinaryOperator) \
	macro(CallInst) \	macro(CallInst) \
	macro(IntrinsicInst) \	macro(IntrinsicInst) \
	macro(DbgInfoIntrinsic) \	macro(DbgInfoIntrinsic) \
	macro(DbgDeclareInst) \	macro(DbgDeclareInst) \

	macro(EHExceptionInst) \
	macro(EHSelectorInst) \
	macro(MemIntrinsic) \	macro(MemIntrinsic) \
	macro(MemCpyInst) \	macro(MemCpyInst) \
	macro(MemMoveInst) \	macro(MemMoveInst) \
	macro(MemSetInst) \	macro(MemSetInst) \
	macro(CmpInst) \	macro(CmpInst) \
	macro(FCmpInst) \	macro(FCmpInst) \
	macro(ICmpInst) \	macro(ICmpInst) \
	macro(ExtractElementInst) \	macro(ExtractElementInst) \
	macro(GetElementPtrInst) \	macro(GetElementPtrInst) \
	macro(InsertElementInst) \	macro(InsertElementInst) \

	skipping to change at line 517	skipping to change at line 1061
	macro(PtrToIntInst) \	macro(PtrToIntInst) \
	macro(SExtInst) \	macro(SExtInst) \
	macro(SIToFPInst) \	macro(SIToFPInst) \
	macro(TruncInst) \	macro(TruncInst) \
	macro(UIToFPInst) \	macro(UIToFPInst) \
	macro(ZExtInst) \	macro(ZExtInst) \
	macro(ExtractValueInst) \	macro(ExtractValueInst) \
	macro(LoadInst) \	macro(LoadInst) \
	macro(VAArgInst)	macro(VAArgInst)


	/* Operations on all values */	/**
		* @defgroup LLVMCCoreValueGeneral General APIs
		*
		* Functions in this section work on all LLVMValueRef instances,
		* regardless of their sub-type. They correspond to functions available
		* on llvm::Value.
		*
		* @{
		*/

		/**
		* Obtain the type of a value.
		*
		* @see llvm::Value::getType()
		*/
	LLVMTypeRef LLVMTypeOf(LLVMValueRef Val);	LLVMTypeRef LLVMTypeOf(LLVMValueRef Val);


		/**
		* Obtain the string name of a value.
		*
		* @see llvm::Value::getName()
		*/
	const char *LLVMGetValueName(LLVMValueRef Val);	const char *LLVMGetValueName(LLVMValueRef Val);


		/**
		* Set the string name of a value.
		*
		* @see llvm::Value::setName()
		*/
	void LLVMSetValueName(LLVMValueRef Val, const char *Name);	void LLVMSetValueName(LLVMValueRef Val, const char *Name);


		/**
		* Dump a representation of a value to stderr.
		*
		* @see llvm::Value::dump()
		*/
	void LLVMDumpValue(LLVMValueRef Val);	void LLVMDumpValue(LLVMValueRef Val);


		/**
		* Replace all uses of a value with another one.
		*
		* @see llvm::Value::replaceAllUsesWith()
		*/
	void LLVMReplaceAllUsesWith(LLVMValueRef OldVal, LLVMValueRef NewVal);	void LLVMReplaceAllUsesWith(LLVMValueRef OldVal, LLVMValueRef NewVal);

	int LLVMHasMetadata(LLVMValueRef Val);
	LLVMValueRef LLVMGetMetadata(LLVMValueRef Val, unsigned KindID);
	void LLVMSetMetadata(LLVMValueRef Val, unsigned KindID, LLVMValueRef Node);


	/* Conversion functions. Return the input value if it is an instance of the	/**
	specified class, otherwise NULL. See llvm::dyn_cast_or_null<>. */	* Determine whether the specified constant instance is constant.
		*/
		LLVMBool LLVMIsConstant(LLVMValueRef Val);

		/**
		* Determine whether a value instance is undefined.
		*/
		LLVMBool LLVMIsUndef(LLVMValueRef Val);

		/**
		* Convert value instances between types.
		*
		* Internally, a LLVMValueRef is "pinned" to a specific type. This
		* series of functions allows you to cast an instance to a specific
		* type.
		*
		* If the cast is not valid for the specified type, NULL is returned.
		*
		* @see llvm::dyn_cast_or_null<>
		*/
	#define LLVM_DECLARE_VALUE_CAST(name) \	#define LLVM_DECLARE_VALUE_CAST(name) \
	LLVMValueRef LLVMIsA##name(LLVMValueRef Val);	LLVMValueRef LLVMIsA##name(LLVMValueRef Val);
	LLVM_FOR_EACH_VALUE_SUBCLASS(LLVM_DECLARE_VALUE_CAST)	LLVM_FOR_EACH_VALUE_SUBCLASS(LLVM_DECLARE_VALUE_CAST)


	/* Operations on Uses */	/**
		* @}
		*/

		/**
		* @defgroup LLVMCCoreValueUses Usage
		*
		* This module defines functions that allow you to inspect the uses of a
		* LLVMValueRef.
		*
		* It is possible to obtain a LLVMUseRef for any LLVMValueRef instance.
		* Each LLVMUseRef (which corresponds to a llvm::Use instance) holds a
		* llvm::User and llvm::Value.
		*
		* @{
		*/

		/**
		* Obtain the first use of a value.
		*
		* Uses are obtained in an iterator fashion. First, call this function
		* to obtain a reference to the first use. Then, call LLVMGetNextUse()
		* on that instance and all subsequently obtained instances untl
		* LLVMGetNextUse() returns NULL.
		*
		* @see llvm::Value::use_begin()
		*/
	LLVMUseRef LLVMGetFirstUse(LLVMValueRef Val);	LLVMUseRef LLVMGetFirstUse(LLVMValueRef Val);


		/**
		* Obtain the next use of a value.
		*
		* This effectively advances the iterator. It returns NULL if you are on
		* the final use and no more are available.
		*/
	LLVMUseRef LLVMGetNextUse(LLVMUseRef U);	LLVMUseRef LLVMGetNextUse(LLVMUseRef U);


		/**
		* Obtain the user value for a user.
		*
		* The returned value corresponds to a llvm::User type.
		*
		* @see llvm::Use::getUser()
		*/
	LLVMValueRef LLVMGetUser(LLVMUseRef U);	LLVMValueRef LLVMGetUser(LLVMUseRef U);


		/**
		* Obtain the value this use corresponds to.
		*
		* @see llvm::Use::get().
		*/
	LLVMValueRef LLVMGetUsedValue(LLVMUseRef U);	LLVMValueRef LLVMGetUsedValue(LLVMUseRef U);


	/* Operations on Users */	/**
		* @}
		*/

		/**
		* @defgroup LLVMCCoreValueUser User value
		*
		* Function in this group pertain to LLVMValueRef instances that descent
		* from llvm::User. This includes constants, instructions, and
		* operators.
		*
		* @{
		*/

		/**
		* Obtain an operand at a specific index in a llvm::User value.
		*
		* @see llvm::User::getOperand()
		*/
	LLVMValueRef LLVMGetOperand(LLVMValueRef Val, unsigned Index);	LLVMValueRef LLVMGetOperand(LLVMValueRef Val, unsigned Index);


		/**
		* Set an operand at a specific index in a llvm::User value.
		*
		* @see llvm::User::setOperand()
		*/
	void LLVMSetOperand(LLVMValueRef User, unsigned Index, LLVMValueRef Val);	void LLVMSetOperand(LLVMValueRef User, unsigned Index, LLVMValueRef Val);


		/**
		* Obtain the number of operands in a llvm::User value.
		*
		* @see llvm::User::getNumOperands()
		*/
	int LLVMGetNumOperands(LLVMValueRef Val);	int LLVMGetNumOperands(LLVMValueRef Val);


	/* Operations on constants of any type */	/**
		* @}
		*/

		/**
		* @defgroup LLVMCCoreValueConstant Constants
		*
		* This section contains APIs for interacting with LLVMValueRef that
		* correspond to llvm::Constant instances.
		*
		* These functions will work for any LLVMValueRef in the llvm::Constant
		* class hierarchy.
		*
		* @{
		*/

		/**
		* Obtain a constant value referring to the null instance of a type.
		*
		* @see llvm::Constant::getNullValue()
		*/
	LLVMValueRef LLVMConstNull(LLVMTypeRef Ty); /* all zeroes */	LLVMValueRef LLVMConstNull(LLVMTypeRef Ty); /* all zeroes */

	LLVMValueRef LLVMConstAllOnes(LLVMTypeRef Ty); /* only for int/vector */
		/**
		* Obtain a constant value referring to the instance of a type
		* consisting of all ones.
		*
		* This is only valid for integer types.
		*
		* @see llvm::Constant::getAllOnesValue()
		*/
		LLVMValueRef LLVMConstAllOnes(LLVMTypeRef Ty);

		/**
		* Obtain a constant value referring to an undefined value of a type.
		*
		* @see llvm::UndefValue::get()
		*/
	LLVMValueRef LLVMGetUndef(LLVMTypeRef Ty);	LLVMValueRef LLVMGetUndef(LLVMTypeRef Ty);

	LLVMBool LLVMIsConstant(LLVMValueRef Val);
		/**
		* Determine whether a value instance is null.
		*
		* @see llvm::Constant::isNullValue()
		*/
	LLVMBool LLVMIsNull(LLVMValueRef Val);	LLVMBool LLVMIsNull(LLVMValueRef Val);

	LLVMBool LLVMIsUndef(LLVMValueRef Val);
		/**
		* Obtain a constant that is a constant pointer pointing to NULL for a
		* specified type.
		*/
	LLVMValueRef LLVMConstPointerNull(LLVMTypeRef Ty);	LLVMValueRef LLVMConstPointerNull(LLVMTypeRef Ty);


	/* Operations on metadata */	/**
	LLVMValueRef LLVMMDStringInContext(LLVMContextRef C, const char *Str,	* @defgroup LLVMCCoreValueConstantScalar Scalar constants
	unsigned SLen);	*
	LLVMValueRef LLVMMDString(const char *Str, unsigned SLen);	* Functions in this group model LLVMValueRef instances that correspond
	LLVMValueRef LLVMMDNodeInContext(LLVMContextRef C, LLVMValueRef *Vals,	* to constants referring to scalar types.
	unsigned Count);	*
	LLVMValueRef LLVMMDNode(LLVMValueRef *Vals, unsigned Count);	* For integer types, the LLVMTypeRef parameter should correspond to a
	const char LLVMGetMDString(LLVMValueRef V, unsigned Len);	* llvm::IntegerType instance and the returned LLVMValueRef will
	int LLVMGetMDNodeNumOperands(LLVMValueRef V);	* correspond to a llvm::ConstantInt.
	LLVMValueRef *LLVMGetMDNodeOperand(LLVMValueRef V, unsigned i);	*
	unsigned LLVMGetNamedMetadataNumOperands(LLVMModuleRef M, const char* name)	* For floating point types, the LLVMTypeRef returned corresponds to a
	;	* llvm::ConstantFP.
	void LLVMGetNamedMetadataOperands(LLVMModuleRef M, const char* name, LLVMVa	*
	lueRef *Dest);	* @{
		*/


	/* Operations on scalar constants */	/**
		* Obtain a constant value for an integer type.
		*
		* The returned value corresponds to a llvm::ConstantInt.
		*
		* @see llvm::ConstantInt::get()
		*
		* @param IntTy Integer type to obtain value of.
		* @param N The value the returned instance should refer to.
		* @param SignExtend Whether to sign extend the produced value.
		*/
	LLVMValueRef LLVMConstInt(LLVMTypeRef IntTy, unsigned long long N,	LLVMValueRef LLVMConstInt(LLVMTypeRef IntTy, unsigned long long N,
	LLVMBool SignExtend);	LLVMBool SignExtend);


		/**
		* Obtain a constant value for an integer of arbitrary precision.
		*
		* @see llvm::ConstantInt::get()
		*/
	LLVMValueRef LLVMConstIntOfArbitraryPrecision(LLVMTypeRef IntTy,	LLVMValueRef LLVMConstIntOfArbitraryPrecision(LLVMTypeRef IntTy,
	unsigned NumWords,	unsigned NumWords,
	const uint64_t Words[]);	const uint64_t Words[]);


		/**
		* Obtain a constant value for an integer parsed from a string.
		*
		* A similar API, LLVMConstIntOfStringAndSize is also available. If the
		* string's length is available, it is preferred to call that function
		* instead.
		*
		* @see llvm::ConstantInt::get()
		*/
	LLVMValueRef LLVMConstIntOfString(LLVMTypeRef IntTy, const char *Text,	LLVMValueRef LLVMConstIntOfString(LLVMTypeRef IntTy, const char *Text,
	uint8_t Radix);	uint8_t Radix);


		/**
		* Obtain a constant value for an integer parsed from a string with
		* specified length.
		*
		* @see llvm::ConstantInt::get()
		*/
	LLVMValueRef LLVMConstIntOfStringAndSize(LLVMTypeRef IntTy, const char *Tex t,	LLVMValueRef LLVMConstIntOfStringAndSize(LLVMTypeRef IntTy, const char *Tex t,
	unsigned SLen, uint8_t Radix);	unsigned SLen, uint8_t Radix);


		/**
		* Obtain a constant value referring to a double floating point value.
		*/
	LLVMValueRef LLVMConstReal(LLVMTypeRef RealTy, double N);	LLVMValueRef LLVMConstReal(LLVMTypeRef RealTy, double N);


		/**
		* Obtain a constant for a floating point value parsed from a string.
		*
		* A similar API, LLVMConstRealOfStringAndSize is also available. It
		* should be used if the input string's length is known.
		*/
	LLVMValueRef LLVMConstRealOfString(LLVMTypeRef RealTy, const char *Text);	LLVMValueRef LLVMConstRealOfString(LLVMTypeRef RealTy, const char *Text);


		/**
		* Obtain a constant for a floating point value parsed from a string.
		*/
	LLVMValueRef LLVMConstRealOfStringAndSize(LLVMTypeRef RealTy, const char *T ext,	LLVMValueRef LLVMConstRealOfStringAndSize(LLVMTypeRef RealTy, const char *T ext,
	unsigned SLen);	unsigned SLen);


		/**
		* Obtain the zero extended value for an integer constant value.
		*
		* @see llvm::ConstantInt::getZExtValue()
		*/
	unsigned long long LLVMConstIntGetZExtValue(LLVMValueRef ConstantVal);	unsigned long long LLVMConstIntGetZExtValue(LLVMValueRef ConstantVal);


		/**
		* Obtain the sign extended value for an integer constant value.
		*
		* @see llvm::ConstantInt::getSExtValue()
		*/
	long long LLVMConstIntGetSExtValue(LLVMValueRef ConstantVal);	long long LLVMConstIntGetSExtValue(LLVMValueRef ConstantVal);


	/* Operations on composite constants */	/**
		* @}
		*/

		/**
		* @defgroup LLVMCCoreValueConstantComposite Composite Constants
		*
		* Functions in this group operate on composite constants.
		*
		* @{
		*/

		/**
		* Create a ConstantDataSequential and initialize it with a string.
		*
		* @see llvm::ConstantDataArray::getString()
		*/
	LLVMValueRef LLVMConstStringInContext(LLVMContextRef C, const char *Str,	LLVMValueRef LLVMConstStringInContext(LLVMContextRef C, const char *Str,
	unsigned Length, LLVMBool DontNullTer minate);	unsigned Length, LLVMBool DontNullTer minate);


		/**
		* Create a ConstantDataSequential with string content in the global contex
		t.
		*
		* This is the same as LLVMConstStringInContext except it operates on the
		* global context.
		*
		* @see LLVMConstStringInContext()
		* @see llvm::ConstantDataArray::getString()
		*/
		LLVMValueRef LLVMConstString(const char *Str, unsigned Length,
		LLVMBool DontNullTerminate);

		/**
		* Create an anonymous ConstantStruct with the specified values.
		*
		* @see llvm::ConstantStruct::getAnon()
		*/
	LLVMValueRef LLVMConstStructInContext(LLVMContextRef C,	LLVMValueRef LLVMConstStructInContext(LLVMContextRef C,
	LLVMValueRef *ConstantVals,	LLVMValueRef *ConstantVals,
	unsigned Count, LLVMBool Packed);	unsigned Count, LLVMBool Packed);


	LLVMValueRef LLVMConstString(const char *Str, unsigned Length,	/**
	LLVMBool DontNullTerminate);	* Create a ConstantStruct in the global Context.
	LLVMValueRef LLVMConstArray(LLVMTypeRef ElementTy,	*
	LLVMValueRef *ConstantVals, unsigned Length);	* This is the same as LLVMConstStructInContext except it operates on the
		* global Context.
		*
		* @see LLVMConstStructInContext()
		*/
	LLVMValueRef LLVMConstStruct(LLVMValueRef *ConstantVals, unsigned Count,	LLVMValueRef LLVMConstStruct(LLVMValueRef *ConstantVals, unsigned Count,
	LLVMBool Packed);	LLVMBool Packed);


		/**
		* Create a ConstantArray from values.
		*
		* @see llvm::ConstantArray::get()
		*/
		LLVMValueRef LLVMConstArray(LLVMTypeRef ElementTy,
		LLVMValueRef *ConstantVals, unsigned Length);

		/**
		* Create a non-anonymous ConstantStruct from values.
		*
		* @see llvm::ConstantStruct::get()
		*/
	LLVMValueRef LLVMConstNamedStruct(LLVMTypeRef StructTy,	LLVMValueRef LLVMConstNamedStruct(LLVMTypeRef StructTy,
	LLVMValueRef *ConstantVals,	LLVMValueRef *ConstantVals,
	unsigned Count);	unsigned Count);


		/**
		* Create a ConstantVector from values.
		*
		* @see llvm::ConstantVector::get()
		*/
	LLVMValueRef LLVMConstVector(LLVMValueRef *ScalarConstantVals, unsigned Siz e);	LLVMValueRef LLVMConstVector(LLVMValueRef *ScalarConstantVals, unsigned Siz e);


	/* Constant expressions */	/**
		* @}
		*/

		/**
		* @defgroup LLVMCCoreValueConstantExpressions Constant Expressions
		*
		* Functions in this group correspond to APIs on llvm::ConstantExpr.
		*
		* @see llvm::ConstantExpr.
		*
		* @{
		*/
	LLVMOpcode LLVMGetConstOpcode(LLVMValueRef ConstantVal);	LLVMOpcode LLVMGetConstOpcode(LLVMValueRef ConstantVal);
	LLVMValueRef LLVMAlignOf(LLVMTypeRef Ty);	LLVMValueRef LLVMAlignOf(LLVMTypeRef Ty);
	LLVMValueRef LLVMSizeOf(LLVMTypeRef Ty);	LLVMValueRef LLVMSizeOf(LLVMTypeRef Ty);
	LLVMValueRef LLVMConstNeg(LLVMValueRef ConstantVal);	LLVMValueRef LLVMConstNeg(LLVMValueRef ConstantVal);
	LLVMValueRef LLVMConstNSWNeg(LLVMValueRef ConstantVal);	LLVMValueRef LLVMConstNSWNeg(LLVMValueRef ConstantVal);
	LLVMValueRef LLVMConstNUWNeg(LLVMValueRef ConstantVal);	LLVMValueRef LLVMConstNUWNeg(LLVMValueRef ConstantVal);
	LLVMValueRef LLVMConstFNeg(LLVMValueRef ConstantVal);	LLVMValueRef LLVMConstFNeg(LLVMValueRef ConstantVal);
	LLVMValueRef LLVMConstNot(LLVMValueRef ConstantVal);	LLVMValueRef LLVMConstNot(LLVMValueRef ConstantVal);
	LLVMValueRef LLVMConstAdd(LLVMValueRef LHSConstant, LLVMValueRef RHSConstan t);	LLVMValueRef LLVMConstAdd(LLVMValueRef LHSConstant, LLVMValueRef RHSConstan t);
	LLVMValueRef LLVMConstNSWAdd(LLVMValueRef LHSConstant, LLVMValueRef RHSCons tant);	LLVMValueRef LLVMConstNSWAdd(LLVMValueRef LHSConstant, LLVMValueRef RHSCons tant);

	skipping to change at line 688	skipping to change at line 1540
	LLVMValueRef LLVMConstExtractValue(LLVMValueRef AggConstant, unsigned *IdxL ist,	LLVMValueRef LLVMConstExtractValue(LLVMValueRef AggConstant, unsigned *IdxL ist,
	unsigned NumIdx);	unsigned NumIdx);
	LLVMValueRef LLVMConstInsertValue(LLVMValueRef AggConstant,	LLVMValueRef LLVMConstInsertValue(LLVMValueRef AggConstant,
	LLVMValueRef ElementValueConstant,	LLVMValueRef ElementValueConstant,
	unsigned *IdxList, unsigned NumIdx);	unsigned *IdxList, unsigned NumIdx);
	LLVMValueRef LLVMConstInlineAsm(LLVMTypeRef Ty,	LLVMValueRef LLVMConstInlineAsm(LLVMTypeRef Ty,
	const char AsmString, const char Constrai nts,	const char AsmString, const char Constrai nts,
	LLVMBool HasSideEffects, LLVMBool IsAlignSt ack);	LLVMBool HasSideEffects, LLVMBool IsAlignSt ack);
	LLVMValueRef LLVMBlockAddress(LLVMValueRef F, LLVMBasicBlockRef BB);	LLVMValueRef LLVMBlockAddress(LLVMValueRef F, LLVMBasicBlockRef BB);


	/* Operations on global variables, functions, and aliases (globals) */	/**
		* @}
		*/

		/**
		* @defgroup LLVMCCoreValueConstantGlobals Global Values
		*
		* This group contains functions that operate on global values. Functions i
		n
		* this group relate to functions in the llvm::GlobalValue class tree.
		*
		* @see llvm::GlobalValue
		*
		* @{
		*/

	LLVMModuleRef LLVMGetGlobalParent(LLVMValueRef Global);	LLVMModuleRef LLVMGetGlobalParent(LLVMValueRef Global);
	LLVMBool LLVMIsDeclaration(LLVMValueRef Global);	LLVMBool LLVMIsDeclaration(LLVMValueRef Global);
	LLVMLinkage LLVMGetLinkage(LLVMValueRef Global);	LLVMLinkage LLVMGetLinkage(LLVMValueRef Global);
	void LLVMSetLinkage(LLVMValueRef Global, LLVMLinkage Linkage);	void LLVMSetLinkage(LLVMValueRef Global, LLVMLinkage Linkage);
	const char *LLVMGetSection(LLVMValueRef Global);	const char *LLVMGetSection(LLVMValueRef Global);
	void LLVMSetSection(LLVMValueRef Global, const char *Section);	void LLVMSetSection(LLVMValueRef Global, const char *Section);
	LLVMVisibility LLVMGetVisibility(LLVMValueRef Global);	LLVMVisibility LLVMGetVisibility(LLVMValueRef Global);
	void LLVMSetVisibility(LLVMValueRef Global, LLVMVisibility Viz);	void LLVMSetVisibility(LLVMValueRef Global, LLVMVisibility Viz);
	unsigned LLVMGetAlignment(LLVMValueRef Global);	unsigned LLVMGetAlignment(LLVMValueRef Global);
	void LLVMSetAlignment(LLVMValueRef Global, unsigned Bytes);	void LLVMSetAlignment(LLVMValueRef Global, unsigned Bytes);


	/* Operations on global variables */	/**
		* @defgroup LLVMCoreValueConstantGlobalVariable Global Variables
		*
		* This group contains functions that operate on global variable values.
		*
		* @see llvm::GlobalVariable
		*
		* @{
		*/
	LLVMValueRef LLVMAddGlobal(LLVMModuleRef M, LLVMTypeRef Ty, const char *Nam e);	LLVMValueRef LLVMAddGlobal(LLVMModuleRef M, LLVMTypeRef Ty, const char *Nam e);
	LLVMValueRef LLVMAddGlobalInAddressSpace(LLVMModuleRef M, LLVMTypeRef Ty,	LLVMValueRef LLVMAddGlobalInAddressSpace(LLVMModuleRef M, LLVMTypeRef Ty,
	const char *Name,	const char *Name,
	unsigned AddressSpace);	unsigned AddressSpace);
	LLVMValueRef LLVMGetNamedGlobal(LLVMModuleRef M, const char *Name);	LLVMValueRef LLVMGetNamedGlobal(LLVMModuleRef M, const char *Name);
	LLVMValueRef LLVMGetFirstGlobal(LLVMModuleRef M);	LLVMValueRef LLVMGetFirstGlobal(LLVMModuleRef M);
	LLVMValueRef LLVMGetLastGlobal(LLVMModuleRef M);	LLVMValueRef LLVMGetLastGlobal(LLVMModuleRef M);
	LLVMValueRef LLVMGetNextGlobal(LLVMValueRef GlobalVar);	LLVMValueRef LLVMGetNextGlobal(LLVMValueRef GlobalVar);
	LLVMValueRef LLVMGetPreviousGlobal(LLVMValueRef GlobalVar);	LLVMValueRef LLVMGetPreviousGlobal(LLVMValueRef GlobalVar);
	void LLVMDeleteGlobal(LLVMValueRef GlobalVar);	void LLVMDeleteGlobal(LLVMValueRef GlobalVar);
	LLVMValueRef LLVMGetInitializer(LLVMValueRef GlobalVar);	LLVMValueRef LLVMGetInitializer(LLVMValueRef GlobalVar);
	void LLVMSetInitializer(LLVMValueRef GlobalVar, LLVMValueRef ConstantVal);	void LLVMSetInitializer(LLVMValueRef GlobalVar, LLVMValueRef ConstantVal);
	LLVMBool LLVMIsThreadLocal(LLVMValueRef GlobalVar);	LLVMBool LLVMIsThreadLocal(LLVMValueRef GlobalVar);
	void LLVMSetThreadLocal(LLVMValueRef GlobalVar, LLVMBool IsThreadLocal);	void LLVMSetThreadLocal(LLVMValueRef GlobalVar, LLVMBool IsThreadLocal);
	LLVMBool LLVMIsGlobalConstant(LLVMValueRef GlobalVar);	LLVMBool LLVMIsGlobalConstant(LLVMValueRef GlobalVar);
	void LLVMSetGlobalConstant(LLVMValueRef GlobalVar, LLVMBool IsConstant);	void LLVMSetGlobalConstant(LLVMValueRef GlobalVar, LLVMBool IsConstant);


	/* Operations on aliases */	/**
		* @}
		*/

		/**
		* @defgroup LLVMCoreValueConstantGlobalAlias Global Aliases
		*
		* This group contains function that operate on global alias values.
		*
		* @see llvm::GlobalAlias
		*
		* @{
		*/
	LLVMValueRef LLVMAddAlias(LLVMModuleRef M, LLVMTypeRef Ty, LLVMValueRef Ali asee,	LLVMValueRef LLVMAddAlias(LLVMModuleRef M, LLVMTypeRef Ty, LLVMValueRef Ali asee,
	const char *Name);	const char *Name);


	/* Operations on functions */	/**
	LLVMValueRef LLVMAddFunction(LLVMModuleRef M, const char *Name,	* @}
	LLVMTypeRef FunctionTy);	*/
	LLVMValueRef LLVMGetNamedFunction(LLVMModuleRef M, const char *Name);
	LLVMValueRef LLVMGetFirstFunction(LLVMModuleRef M);	/**
	LLVMValueRef LLVMGetLastFunction(LLVMModuleRef M);	* @defgroup LLVMCCoreValueFunction Function values
	LLVMValueRef LLVMGetNextFunction(LLVMValueRef Fn);	*
	LLVMValueRef LLVMGetPreviousFunction(LLVMValueRef Fn);	* Functions in this group operate on LLVMValueRef instances that
		* correspond to llvm::Function instances.
		*
		* @see llvm::Function
		*
		* @{
		*/

		/**
		* Remove a function from its containing module and deletes it.
		*
		* @see llvm::Function::eraseFromParent()
		*/
	void LLVMDeleteFunction(LLVMValueRef Fn);	void LLVMDeleteFunction(LLVMValueRef Fn);


		/**
		* Obtain the ID number from a function instance.
		*
		* @see llvm::Function::getIntrinsicID()
		*/
	unsigned LLVMGetIntrinsicID(LLVMValueRef Fn);	unsigned LLVMGetIntrinsicID(LLVMValueRef Fn);


		/**
		* Obtain the calling function of a function.
		*
		* The returned value corresponds to the LLVMCallConv enumeration.
		*
		* @see llvm::Function::getCallingConv()
		*/
	unsigned LLVMGetFunctionCallConv(LLVMValueRef Fn);	unsigned LLVMGetFunctionCallConv(LLVMValueRef Fn);


		/**
		* Set the calling convention of a function.
		*
		* @see llvm::Function::setCallingConv()
		*
		* @param Fn Function to operate on
		* @param CC LLVMCallConv to set calling convention to
		*/
	void LLVMSetFunctionCallConv(LLVMValueRef Fn, unsigned CC);	void LLVMSetFunctionCallConv(LLVMValueRef Fn, unsigned CC);


		/**
		* Obtain the name of the garbage collector to use during code
		* generation.
		*
		* @see llvm::Function::getGC()
		*/
	const char *LLVMGetGC(LLVMValueRef Fn);	const char *LLVMGetGC(LLVMValueRef Fn);


		/**
		* Define the garbage collector to use during code generation.
		*
		* @see llvm::Function::setGC()
		*/
	void LLVMSetGC(LLVMValueRef Fn, const char *Name);	void LLVMSetGC(LLVMValueRef Fn, const char *Name);


		/**
		* Add an attribute to a function.
		*
		* @see llvm::Function::addAttribute()
		*/
	void LLVMAddFunctionAttr(LLVMValueRef Fn, LLVMAttribute PA);	void LLVMAddFunctionAttr(LLVMValueRef Fn, LLVMAttribute PA);


		/**
		* Obtain an attribute from a function.
		*
		* @see llvm::Function::getAttributes()
		*/
	LLVMAttribute LLVMGetFunctionAttr(LLVMValueRef Fn);	LLVMAttribute LLVMGetFunctionAttr(LLVMValueRef Fn);


		/**
		* Remove an attribute from a function.
		*/
	void LLVMRemoveFunctionAttr(LLVMValueRef Fn, LLVMAttribute PA);	void LLVMRemoveFunctionAttr(LLVMValueRef Fn, LLVMAttribute PA);


	/* Operations on parameters */	/**
	unsigned LLVMCountParams(LLVMValueRef Fn);	* @defgroup LLVMCCoreValueFunctionParameters Function Parameters
	void LLVMGetParams(LLVMValueRef Fn, LLVMValueRef *Params);	*
	LLVMValueRef LLVMGetParam(LLVMValueRef Fn, unsigned Index);	* Functions in this group relate to arguments/parameters on functions.
	LLVMValueRef LLVMGetParamParent(LLVMValueRef Inst);	*
	LLVMValueRef LLVMGetFirstParam(LLVMValueRef Fn);	* Functions in this group expect LLVMValueRef instances that correspond
	LLVMValueRef LLVMGetLastParam(LLVMValueRef Fn);	* to llvm::Function instances.
	LLVMValueRef LLVMGetNextParam(LLVMValueRef Arg);	*
	LLVMValueRef LLVMGetPreviousParam(LLVMValueRef Arg);	* @{
	void LLVMAddAttribute(LLVMValueRef Arg, LLVMAttribute PA);	*/
	void LLVMRemoveAttribute(LLVMValueRef Arg, LLVMAttribute PA);
	LLVMAttribute LLVMGetAttribute(LLVMValueRef Arg);	/**
	void LLVMSetParamAlignment(LLVMValueRef Arg, unsigned align);	* Obtain the number of parameters in a function.
		*
		* @see llvm::Function::arg_size()
		*/
		unsigned LLVMCountParams(LLVMValueRef Fn);

		/**
		* Obtain the parameters in a function.
		*
		* The takes a pointer to a pre-allocated array of LLVMValueRef that is
		* at least LLVMCountParams() long. This array will be filled with
		* LLVMValueRef instances which correspond to the parameters the
		* function receives. Each LLVMValueRef corresponds to a llvm::Argument
		* instance.
		*
		* @see llvm::Function::arg_begin()
		*/
		void LLVMGetParams(LLVMValueRef Fn, LLVMValueRef *Params);

		/**
		* Obtain the parameter at the specified index.
		*
		* Parameters are indexed from 0.
		*
		* @see llvm::Function::arg_begin()
		*/
		LLVMValueRef LLVMGetParam(LLVMValueRef Fn, unsigned Index);

		/**
		* Obtain the function to which this argument belongs.
		*
		* Unlike other functions in this group, this one takes a LLVMValueRef
		* that corresponds to a llvm::Attribute.
		*
		* The returned LLVMValueRef is the llvm::Function to which this
		* argument belongs.
		*/
		LLVMValueRef LLVMGetParamParent(LLVMValueRef Inst);

		/**
		* Obtain the first parameter to a function.
		*
		* @see llvm::Function::arg_begin()
		*/
		LLVMValueRef LLVMGetFirstParam(LLVMValueRef Fn);

		/**
		* Obtain the last parameter to a function.
		*
		* @see llvm::Function::arg_end()
		*/
		LLVMValueRef LLVMGetLastParam(LLVMValueRef Fn);

		/**
		* Obtain the next parameter to a function.
		*
		* This takes a LLVMValueRef obtained from LLVMGetFirstParam() (which is
		* actually a wrapped iterator) and obtains the next parameter from the
		* underlying iterator.
		*/
		LLVMValueRef LLVMGetNextParam(LLVMValueRef Arg);

		/**
		* Obtain the previous parameter to a function.
		*
		* This is the opposite of LLVMGetNextParam().
		*/
		LLVMValueRef LLVMGetPreviousParam(LLVMValueRef Arg);

		/**
		* Add an attribute to a function argument.
		*
		* @see llvm::Argument::addAttr()
		*/
		void LLVMAddAttribute(LLVMValueRef Arg, LLVMAttribute PA);

		/**
		* Remove an attribute from a function argument.
		*
		* @see llvm::Argument::removeAttr()
		*/
		void LLVMRemoveAttribute(LLVMValueRef Arg, LLVMAttribute PA);

		/**
		* Get an attribute from a function argument.
		*/
		LLVMAttribute LLVMGetAttribute(LLVMValueRef Arg);

		/**
		* Set the alignment for a function parameter.
		*
		* @see llvm::Argument::addAttr()
		* @see llvm::Attribute::constructAlignmentFromInt()
		*/
		void LLVMSetParamAlignment(LLVMValueRef Arg, unsigned align);

		/**
		* @}
		*/

		/**
		* @}
		*/

		/**
		* @}
		*/

		/**
		* @}
		*/

		/**
		* @defgroup LLVMCCoreValueMetadata Metadata
		*
		* @{
		*/

		/**
		* Obtain a MDString value from a context.
		*
		* The returned instance corresponds to the llvm::MDString class.
		*
		* The instance is specified by string data of a specified length. The
		* string content is copied, so the backing memory can be freed after
		* this function returns.
		*/
		LLVMValueRef LLVMMDStringInContext(LLVMContextRef C, const char *Str,
		unsigned SLen);

		/**
		* Obtain a MDString value from the global context.
		*/
		LLVMValueRef LLVMMDString(const char *Str, unsigned SLen);

		/**
		* Obtain a MDNode value from a context.
		*
		* The returned value corresponds to the llvm::MDNode class.
		*/
		LLVMValueRef LLVMMDNodeInContext(LLVMContextRef C, LLVMValueRef *Vals,
		unsigned Count);

		/**
		* Obtain a MDNode value from the global context.
		*/
		LLVMValueRef LLVMMDNode(LLVMValueRef *Vals, unsigned Count);

		/**
		* Obtain the underlying string from a MDString value.
		*
		* @param V Instance to obtain string from.
		* @param Len Memory address which will hold length of returned string.
		* @return String data in MDString.
		*/
		const char LLVMGetMDString(LLVMValueRef V, unsigned Len);

		/**
		* @}
		*/

		/**
		* @defgroup LLVMCCoreValueBasicBlock Basic Block
		*
		* A basic block represents a single entry single exit section of code.
		* Basic blocks contain a list of instructions which form the body of
		* the block.
		*
		* Basic blocks belong to functions. They have the type of label.
		*
		* Basic blocks are themselves values. However, the C API models them as
		* LLVMBasicBlockRef.
		*
		* @see llvm::BasicBlock
		*
		* @{
		*/


	/* Operations on basic blocks */	/**
		* Convert a basic block instance to a value type.
		*/
	LLVMValueRef LLVMBasicBlockAsValue(LLVMBasicBlockRef BB);	LLVMValueRef LLVMBasicBlockAsValue(LLVMBasicBlockRef BB);


		/**
		* Determine whether a LLVMValueRef is itself a basic block.
		*/
	LLVMBool LLVMValueIsBasicBlock(LLVMValueRef Val);	LLVMBool LLVMValueIsBasicBlock(LLVMValueRef Val);


		/**
		* Convert a LLVMValueRef to a LLVMBasicBlockRef instance.
		*/
	LLVMBasicBlockRef LLVMValueAsBasicBlock(LLVMValueRef Val);	LLVMBasicBlockRef LLVMValueAsBasicBlock(LLVMValueRef Val);


		/**
		* Obtain the function to which a basic block belongs.
		*
		* @see llvm::BasicBlock::getParent()
		*/
	LLVMValueRef LLVMGetBasicBlockParent(LLVMBasicBlockRef BB);	LLVMValueRef LLVMGetBasicBlockParent(LLVMBasicBlockRef BB);


		/**
		* Obtain the terminator instruction for a basic block.
		*
		* If the basic block does not have a terminator (it is not well-formed
		* if it doesn't), then NULL is returned.
		*
		* The returned LLVMValueRef corresponds to a llvm::TerminatorInst.
		*
		* @see llvm::BasicBlock::getTerminator()
		*/
	LLVMValueRef LLVMGetBasicBlockTerminator(LLVMBasicBlockRef BB);	LLVMValueRef LLVMGetBasicBlockTerminator(LLVMBasicBlockRef BB);


		/**
		* Obtain the number of basic blocks in a function.
		*
		* @param Fn Function value to operate on.
		*/
	unsigned LLVMCountBasicBlocks(LLVMValueRef Fn);	unsigned LLVMCountBasicBlocks(LLVMValueRef Fn);


		/**
		* Obtain all of the basic blocks in a function.
		*
		* This operates on a function value. The BasicBlocks parameter is a
		* pointer to a pre-allocated array of LLVMBasicBlockRef of at least
		* LLVMCountBasicBlocks() in length. This array is populated with
		* LLVMBasicBlockRef instances.
		*/
	void LLVMGetBasicBlocks(LLVMValueRef Fn, LLVMBasicBlockRef *BasicBlocks);	void LLVMGetBasicBlocks(LLVMValueRef Fn, LLVMBasicBlockRef *BasicBlocks);


		/**
		* Obtain the first basic block in a function.
		*
		* The returned basic block can be used as an iterator. You will likely
		* eventually call into LLVMGetNextBasicBlock() with it.
		*
		* @see llvm::Function::begin()
		*/
	LLVMBasicBlockRef LLVMGetFirstBasicBlock(LLVMValueRef Fn);	LLVMBasicBlockRef LLVMGetFirstBasicBlock(LLVMValueRef Fn);


		/**
		* Obtain the last basic block in a function.
		*
		* @see llvm::Function::end()
		*/
	LLVMBasicBlockRef LLVMGetLastBasicBlock(LLVMValueRef Fn);	LLVMBasicBlockRef LLVMGetLastBasicBlock(LLVMValueRef Fn);


		/**
		* Advance a basic block iterator.
		*/
	LLVMBasicBlockRef LLVMGetNextBasicBlock(LLVMBasicBlockRef BB);	LLVMBasicBlockRef LLVMGetNextBasicBlock(LLVMBasicBlockRef BB);


		/**
		* Go backwards in a basic block iterator.
		*/
	LLVMBasicBlockRef LLVMGetPreviousBasicBlock(LLVMBasicBlockRef BB);	LLVMBasicBlockRef LLVMGetPreviousBasicBlock(LLVMBasicBlockRef BB);


		/**
		* Obtain the basic block that corresponds to the entry point of a
		* function.
		*
		* @see llvm::Function::getEntryBlock()
		*/
	LLVMBasicBlockRef LLVMGetEntryBasicBlock(LLVMValueRef Fn);	LLVMBasicBlockRef LLVMGetEntryBasicBlock(LLVMValueRef Fn);


		/**
		* Append a basic block to the end of a function.
		*
		* @see llvm::BasicBlock::Create()
		*/
	LLVMBasicBlockRef LLVMAppendBasicBlockInContext(LLVMContextRef C,	LLVMBasicBlockRef LLVMAppendBasicBlockInContext(LLVMContextRef C,
	LLVMValueRef Fn,	LLVMValueRef Fn,
	const char *Name);	const char *Name);


		/**
		* Append a basic block to the end of a function using the global
		* context.
		*
		* @see llvm::BasicBlock::Create()
		*/
		LLVMBasicBlockRef LLVMAppendBasicBlock(LLVMValueRef Fn, const char *Name);

		/**
		* Insert a basic block in a function before another basic block.
		*
		* The function to add to is determined by the function of the
		* passed basic block.
		*
		* @see llvm::BasicBlock::Create()
		*/
	LLVMBasicBlockRef LLVMInsertBasicBlockInContext(LLVMContextRef C,	LLVMBasicBlockRef LLVMInsertBasicBlockInContext(LLVMContextRef C,
	LLVMBasicBlockRef BB,	LLVMBasicBlockRef BB,
	const char *Name);	const char *Name);


	LLVMBasicBlockRef LLVMAppendBasicBlock(LLVMValueRef Fn, const char *Name);	/**
		* Insert a basic block in a function using the global context.
		*
		* @see llvm::BasicBlock::Create()
		*/
	LLVMBasicBlockRef LLVMInsertBasicBlock(LLVMBasicBlockRef InsertBeforeBB,	LLVMBasicBlockRef LLVMInsertBasicBlock(LLVMBasicBlockRef InsertBeforeBB,
	const char *Name);	const char *Name);


		/**
		* Remove a basic block from a function and delete it.
		*
		* This deletes the basic block from its containing function and deletes
		* the basic block itself.
		*
		* @see llvm::BasicBlock::eraseFromParent()
		*/
	void LLVMDeleteBasicBlock(LLVMBasicBlockRef BB);	void LLVMDeleteBasicBlock(LLVMBasicBlockRef BB);


		/**
		* Remove a basic block from a function.
		*
		* This deletes the basic block from its containing function but keep
		* the basic block alive.
		*
		* @see llvm::BasicBlock::removeFromParent()
		*/
	void LLVMRemoveBasicBlockFromParent(LLVMBasicBlockRef BB);	void LLVMRemoveBasicBlockFromParent(LLVMBasicBlockRef BB);


		/**
		* Move a basic block to before another one.
		*
		* @see llvm::BasicBlock::moveBefore()
		*/
	void LLVMMoveBasicBlockBefore(LLVMBasicBlockRef BB, LLVMBasicBlockRef MoveP os);	void LLVMMoveBasicBlockBefore(LLVMBasicBlockRef BB, LLVMBasicBlockRef MoveP os);


		/**
		* Move a basic block to after another one.
		*
		* @see llvm::BasicBlock::moveAfter()
		*/
	void LLVMMoveBasicBlockAfter(LLVMBasicBlockRef BB, LLVMBasicBlockRef MovePo s);	void LLVMMoveBasicBlockAfter(LLVMBasicBlockRef BB, LLVMBasicBlockRef MovePo s);


		/**
		* Obtain the first instruction in a basic block.
		*
		* The returned LLVMValueRef corresponds to a llvm::Instruction
		* instance.
		*/
	LLVMValueRef LLVMGetFirstInstruction(LLVMBasicBlockRef BB);	LLVMValueRef LLVMGetFirstInstruction(LLVMBasicBlockRef BB);


		/**
		* Obtain the last instruction in a basic block.
		*
		* The returned LLVMValueRef corresponds to a LLVM:Instruction.
		*/
	LLVMValueRef LLVMGetLastInstruction(LLVMBasicBlockRef BB);	LLVMValueRef LLVMGetLastInstruction(LLVMBasicBlockRef BB);


	/* Operations on instructions */	/**
		* @}
		*/

		/**
		* @defgroup LLVMCCoreValueInstruction Instructions
		*
		* Functions in this group relate to the inspection and manipulation of
		* individual instructions.
		*
		* In the C++ API, an instruction is modeled by llvm::Instruction. This
		* class has a large number of descendents. llvm::Instruction is a
		* llvm::Value and in the C API, instructions are modeled by
		* LLVMValueRef.
		*
		* This group also contains sub-groups which operate on specific
		* llvm::Instruction types, e.g. llvm::CallInst.
		*
		* @{
		*/

		/**
		* Determine whether an instruction has any metadata attached.
		*/
		int LLVMHasMetadata(LLVMValueRef Val);

		/**
		* Return metadata associated with an instruction value.
		*/
		LLVMValueRef LLVMGetMetadata(LLVMValueRef Val, unsigned KindID);

		/**
		* Set metadata associated with an instruction value.
		*/
		void LLVMSetMetadata(LLVMValueRef Val, unsigned KindID, LLVMValueRef Node);

		/**
		* Obtain the basic block to which an instruction belongs.
		*
		* @see llvm::Instruction::getParent()
		*/
	LLVMBasicBlockRef LLVMGetInstructionParent(LLVMValueRef Inst);	LLVMBasicBlockRef LLVMGetInstructionParent(LLVMValueRef Inst);


		/**
		* Obtain the instruction that occurs after the one specified.
		*
		* The next instruction will be from the same basic block.
		*
		* If this is the last instruction in a basic block, NULL will be
		* returned.
		*/
	LLVMValueRef LLVMGetNextInstruction(LLVMValueRef Inst);	LLVMValueRef LLVMGetNextInstruction(LLVMValueRef Inst);


		/**
		* Obtain the instruction that occured before this one.
		*
		* If the instruction is the first instruction in a basic block, NULL
		* will be returned.
		*/
	LLVMValueRef LLVMGetPreviousInstruction(LLVMValueRef Inst);	LLVMValueRef LLVMGetPreviousInstruction(LLVMValueRef Inst);


		/**
		* Remove and delete an instruction.
		*
		* The instruction specified is removed from its containing building
		* block and then deleted.
		*
		* @see llvm::Instruction::eraseFromParent()
		*/
	void LLVMInstructionEraseFromParent(LLVMValueRef Inst);	void LLVMInstructionEraseFromParent(LLVMValueRef Inst);


		/**
		* Obtain the code opcode for an individual instruction.
		*
		* @see llvm::Instruction::getOpCode()
		*/
	LLVMOpcode LLVMGetInstructionOpcode(LLVMValueRef Inst);	LLVMOpcode LLVMGetInstructionOpcode(LLVMValueRef Inst);


		/**
		* Obtain the predicate of an instruction.
		*
		* This is only valid for instructions that correspond to llvm::ICmpInst
		* or llvm::ConstantExpr whose opcode is llvm::Instruction::ICmp.
		*
		* @see llvm::ICmpInst::getPredicate()
		*/
	LLVMIntPredicate LLVMGetICmpPredicate(LLVMValueRef Inst);	LLVMIntPredicate LLVMGetICmpPredicate(LLVMValueRef Inst);


	/* Operations on call sites */	/**
		* @defgroup LLVMCCoreValueInstructionCall Call Sites and Invocations
		*
		* Functions in this group apply to instructions that refer to call
		* sites and invocations. These correspond to C++ types in the
		* llvm::CallInst class tree.
		*
		* @{
		*/

		/**
		* Set the calling convention for a call instruction.
		*
		* This expects an LLVMValueRef that corresponds to a llvm::CallInst or
		* llvm::InvokeInst.
		*
		* @see llvm::CallInst::setCallingConv()
		* @see llvm::InvokeInst::setCallingConv()
		*/
	void LLVMSetInstructionCallConv(LLVMValueRef Instr, unsigned CC);	void LLVMSetInstructionCallConv(LLVMValueRef Instr, unsigned CC);


		/**
		* Obtain the calling convention for a call instruction.
		*
		* This is the opposite of LLVMSetInstructionCallConv(). Reads its
		* usage.
		*
		* @see LLVMSetInstructionCallConv()
		*/
	unsigned LLVMGetInstructionCallConv(LLVMValueRef Instr);	unsigned LLVMGetInstructionCallConv(LLVMValueRef Instr);


	void LLVMAddInstrAttribute(LLVMValueRef Instr, unsigned index, LLVMAttribut e);	void LLVMAddInstrAttribute(LLVMValueRef Instr, unsigned index, LLVMAttribut e);
	void LLVMRemoveInstrAttribute(LLVMValueRef Instr, unsigned index,	void LLVMRemoveInstrAttribute(LLVMValueRef Instr, unsigned index,
	LLVMAttribute);	LLVMAttribute);
	void LLVMSetInstrParamAlignment(LLVMValueRef Instr, unsigned index,	void LLVMSetInstrParamAlignment(LLVMValueRef Instr, unsigned index,
	unsigned align);	unsigned align);


	/* Operations on call instructions (only) */	/**
		* Obtain whether a call instruction is a tail call.
		*
		* This only works on llvm::CallInst instructions.
		*
		* @see llvm::CallInst::isTailCall()
		*/
	LLVMBool LLVMIsTailCall(LLVMValueRef CallInst);	LLVMBool LLVMIsTailCall(LLVMValueRef CallInst);


		/**
		* Set whether a call instruction is a tail call.
		*
		* This only works on llvm::CallInst instructions.
		*
		* @see llvm::CallInst::setTailCall()
		*/
	void LLVMSetTailCall(LLVMValueRef CallInst, LLVMBool IsTailCall);	void LLVMSetTailCall(LLVMValueRef CallInst, LLVMBool IsTailCall);


	/* Operations on switch instructions (only) */	/**
		* @}
		*/

		/**
		* Obtain the default destination basic block of a switch instruction.
		*
		* This only works on llvm::SwitchInst instructions.
		*
		* @see llvm::SwitchInst::getDefaultDest()
		*/
	LLVMBasicBlockRef LLVMGetSwitchDefaultDest(LLVMValueRef SwitchInstr);	LLVMBasicBlockRef LLVMGetSwitchDefaultDest(LLVMValueRef SwitchInstr);


	/* Operations on phi nodes */	/**
		* @defgroup LLVMCCoreValueInstructionPHINode PHI Nodes
		*
		* Functions in this group only apply to instructions that map to
		* llvm::PHINode instances.
		*
		* @{
		*/

		/**
		* Add an incoming value to the end of a PHI list.
		*/
	void LLVMAddIncoming(LLVMValueRef PhiNode, LLVMValueRef *IncomingValues,	void LLVMAddIncoming(LLVMValueRef PhiNode, LLVMValueRef *IncomingValues,
	LLVMBasicBlockRef *IncomingBlocks, unsigned Count);	LLVMBasicBlockRef *IncomingBlocks, unsigned Count);


		/**
		* Obtain the number of incoming basic blocks to a PHI node.
		*/
	unsigned LLVMCountIncoming(LLVMValueRef PhiNode);	unsigned LLVMCountIncoming(LLVMValueRef PhiNode);


		/**
		* Obtain an incoming value to a PHI node as a LLVMValueRef.
		*/
	LLVMValueRef LLVMGetIncomingValue(LLVMValueRef PhiNode, unsigned Index);	LLVMValueRef LLVMGetIncomingValue(LLVMValueRef PhiNode, unsigned Index);


		/**
		* Obtain an incoming value to a PHI node as a LLVMBasicBlockRef.
		*/
	LLVMBasicBlockRef LLVMGetIncomingBlock(LLVMValueRef PhiNode, unsigned Index );	LLVMBasicBlockRef LLVMGetIncomingBlock(LLVMValueRef PhiNode, unsigned Index );


	/*===-- Instruction builders ----------------------------------------------	/**
	===*/	* @}
		*/

		/**
		* @}
		*/

		/**
		* @}
		*/


	/* An instruction builder represents a point within a basic block, and is t	/**
	he	* @defgroup LLVMCCoreInstructionBuilder Instruction Builders
	* exclusive means of building instructions using the C interface.	*
		* An instruction builder represents a point within a basic block and is
		* the exclusive means of building instructions using the C interface.
		*
		* @{
	*/	*/

	LLVMBuilderRef LLVMCreateBuilderInContext(LLVMContextRef C);	LLVMBuilderRef LLVMCreateBuilderInContext(LLVMContextRef C);
	LLVMBuilderRef LLVMCreateBuilder(void);	LLVMBuilderRef LLVMCreateBuilder(void);
	void LLVMPositionBuilder(LLVMBuilderRef Builder, LLVMBasicBlockRef Block,	void LLVMPositionBuilder(LLVMBuilderRef Builder, LLVMBasicBlockRef Block,
	LLVMValueRef Instr);	LLVMValueRef Instr);
	void LLVMPositionBuilderBefore(LLVMBuilderRef Builder, LLVMValueRef Instr);	void LLVMPositionBuilderBefore(LLVMBuilderRef Builder, LLVMValueRef Instr);
	void LLVMPositionBuilderAtEnd(LLVMBuilderRef Builder, LLVMBasicBlockRef Blo ck);	void LLVMPositionBuilderAtEnd(LLVMBuilderRef Builder, LLVMBasicBlockRef Blo ck);
	LLVMBasicBlockRef LLVMGetInsertBlock(LLVMBuilderRef Builder);	LLVMBasicBlockRef LLVMGetInsertBlock(LLVMBuilderRef Builder);
	void LLVMClearInsertionPosition(LLVMBuilderRef Builder);	void LLVMClearInsertionPosition(LLVMBuilderRef Builder);

	skipping to change at line 962	skipping to change at line 2397
	const char *Name);	const char *Name);
	LLVMValueRef LLVMBuildInBoundsGEP(LLVMBuilderRef B, LLVMValueRef Pointer,	LLVMValueRef LLVMBuildInBoundsGEP(LLVMBuilderRef B, LLVMValueRef Pointer,
	LLVMValueRef *Indices, unsigned NumIndice s,	LLVMValueRef *Indices, unsigned NumIndice s,
	const char *Name);	const char *Name);
	LLVMValueRef LLVMBuildStructGEP(LLVMBuilderRef B, LLVMValueRef Pointer,	LLVMValueRef LLVMBuildStructGEP(LLVMBuilderRef B, LLVMValueRef Pointer,
	unsigned Idx, const char *Name);	unsigned Idx, const char *Name);
	LLVMValueRef LLVMBuildGlobalString(LLVMBuilderRef B, const char *Str,	LLVMValueRef LLVMBuildGlobalString(LLVMBuilderRef B, const char *Str,
	const char *Name);	const char *Name);
	LLVMValueRef LLVMBuildGlobalStringPtr(LLVMBuilderRef B, const char *Str,	LLVMValueRef LLVMBuildGlobalStringPtr(LLVMBuilderRef B, const char *Str,
	const char *Name);	const char *Name);

		LLVMBool LLVMGetVolatile(LLVMValueRef MemoryAccessInst);
		void LLVMSetVolatile(LLVMValueRef MemoryAccessInst, LLVMBool IsVolatile);

	/* Casts */	/* Casts */
	LLVMValueRef LLVMBuildTrunc(LLVMBuilderRef, LLVMValueRef Val,	LLVMValueRef LLVMBuildTrunc(LLVMBuilderRef, LLVMValueRef Val,
	LLVMTypeRef DestTy, const char *Name);	LLVMTypeRef DestTy, const char *Name);
	LLVMValueRef LLVMBuildZExt(LLVMBuilderRef, LLVMValueRef Val,	LLVMValueRef LLVMBuildZExt(LLVMBuilderRef, LLVMValueRef Val,
	LLVMTypeRef DestTy, const char *Name);	LLVMTypeRef DestTy, const char *Name);
	LLVMValueRef LLVMBuildSExt(LLVMBuilderRef, LLVMValueRef Val,	LLVMValueRef LLVMBuildSExt(LLVMBuilderRef, LLVMValueRef Val,
	LLVMTypeRef DestTy, const char *Name);	LLVMTypeRef DestTy, const char *Name);
	LLVMValueRef LLVMBuildFPToUI(LLVMBuilderRef, LLVMValueRef Val,	LLVMValueRef LLVMBuildFPToUI(LLVMBuilderRef, LLVMValueRef Val,
	LLVMTypeRef DestTy, const char *Name);	LLVMTypeRef DestTy, const char *Name);

	skipping to change at line 1042	skipping to change at line 2479
	LLVMValueRef EltVal, unsigned Index,	LLVMValueRef EltVal, unsigned Index,
	const char *Name);	const char *Name);

	LLVMValueRef LLVMBuildIsNull(LLVMBuilderRef, LLVMValueRef Val,	LLVMValueRef LLVMBuildIsNull(LLVMBuilderRef, LLVMValueRef Val,
	const char *Name);	const char *Name);
	LLVMValueRef LLVMBuildIsNotNull(LLVMBuilderRef, LLVMValueRef Val,	LLVMValueRef LLVMBuildIsNotNull(LLVMBuilderRef, LLVMValueRef Val,
	const char *Name);	const char *Name);
	LLVMValueRef LLVMBuildPtrDiff(LLVMBuilderRef, LLVMValueRef LHS,	LLVMValueRef LLVMBuildPtrDiff(LLVMBuilderRef, LLVMValueRef LHS,
	LLVMValueRef RHS, const char *Name);	LLVMValueRef RHS, const char *Name);


	/*===-- Module providers --------------------------------------------------	/**
	===*/	* @}
		*/

		/**
		* @defgroup LLVMCCoreModuleProvider Module Providers
		*
		* @{
		*/


	/* Changes the type of M so it can be passed to FunctionPassManagers and th	/**
	e	* Changes the type of M so it can be passed to FunctionPassManagers and th
		e
	* JIT. They take ModuleProviders for historical reasons.	* JIT. They take ModuleProviders for historical reasons.
	*/	*/
	LLVMModuleProviderRef	LLVMModuleProviderRef
	LLVMCreateModuleProviderForExistingModule(LLVMModuleRef M);	LLVMCreateModuleProviderForExistingModule(LLVMModuleRef M);


	/* Destroys the module M.	/**
		* Destroys the module M.
	*/	*/
	void LLVMDisposeModuleProvider(LLVMModuleProviderRef M);	void LLVMDisposeModuleProvider(LLVMModuleProviderRef M);


	/*===-- Memory buffers ----------------------------------------------------	/**
	===*/	* @}
		*/

		/**
		* @defgroup LLVMCCoreMemoryBuffers Memory Buffers
		*
		* @{
		*/

	LLVMBool LLVMCreateMemoryBufferWithContentsOfFile(const char *Path,	LLVMBool LLVMCreateMemoryBufferWithContentsOfFile(const char *Path,
	LLVMMemoryBufferRef *OutM emBuf,	LLVMMemoryBufferRef *OutM emBuf,
	char **OutMessage);	char **OutMessage);
	LLVMBool LLVMCreateMemoryBufferWithSTDIN(LLVMMemoryBufferRef *OutMemBuf,	LLVMBool LLVMCreateMemoryBufferWithSTDIN(LLVMMemoryBufferRef *OutMemBuf,
	char **OutMessage);	char **OutMessage);
	void LLVMDisposeMemoryBuffer(LLVMMemoryBufferRef MemBuf);	void LLVMDisposeMemoryBuffer(LLVMMemoryBufferRef MemBuf);


	/*===-- Pass Registry -----------------------------------------------------	/**
	===*/	* @}
		*/

		/**
		* @defgroup LLVMCCorePassRegistry Pass Registry
		*
		* @{
		*/

	/** Return the global pass registry, for use with initialization functions.	/** Return the global pass registry, for use with initialization functions.

	See llvm::PassRegistry::getPassRegistry. */	@see llvm::PassRegistry::getPassRegistry */
	LLVMPassRegistryRef LLVMGetGlobalPassRegistry(void);	LLVMPassRegistryRef LLVMGetGlobalPassRegistry(void);


	/*===-- Pass Managers -----------------------------------------------------	/**
	===*/	* @}
		*/

		/**
		* @defgroup LLVMCCorePassManagers Pass Managers
		*
		* @{
		*/

	/** Constructs a new whole-module pass pipeline. This type of pipeline is	/** Constructs a new whole-module pass pipeline. This type of pipeline is
	suitable for link-time optimization and whole-module transformations.	suitable for link-time optimization and whole-module transformations.

	See llvm::PassManager::PassManager. */	@see llvm::PassManager::PassManager */
	LLVMPassManagerRef LLVMCreatePassManager(void);	LLVMPassManagerRef LLVMCreatePassManager(void);

	/** Constructs a new function-by-function pass pipeline over the module	/** Constructs a new function-by-function pass pipeline over the module
	provider. It does not take ownership of the module provider. This type of	provider. It does not take ownership of the module provider. This type of
	pipeline is suitable for code generation and JIT compilation tasks.	pipeline is suitable for code generation and JIT compilation tasks.

	See llvm::FunctionPassManager::FunctionPassManager. */	@see llvm::FunctionPassManager::FunctionPassManager */
	LLVMPassManagerRef LLVMCreateFunctionPassManagerForModule(LLVMModuleRef M);	LLVMPassManagerRef LLVMCreateFunctionPassManagerForModule(LLVMModuleRef M);

	/** Deprecated: Use LLVMCreateFunctionPassManagerForModule instead. */	/** Deprecated: Use LLVMCreateFunctionPassManagerForModule instead. */
	LLVMPassManagerRef LLVMCreateFunctionPassManager(LLVMModuleProviderRef MP);	LLVMPassManagerRef LLVMCreateFunctionPassManager(LLVMModuleProviderRef MP);

	/** Initializes, executes on the provided module, and finalizes all of the	/** Initializes, executes on the provided module, and finalizes all of the
	passes scheduled in the pass manager. Returns 1 if any of the passes	passes scheduled in the pass manager. Returns 1 if any of the passes

	modified the module, 0 otherwise. See llvm::PassManager::run(Module&).	modified the module, 0 otherwise.
	*/	@see llvm::PassManager::run(Module&) */
	LLVMBool LLVMRunPassManager(LLVMPassManagerRef PM, LLVMModuleRef M);	LLVMBool LLVMRunPassManager(LLVMPassManagerRef PM, LLVMModuleRef M);

	/** Initializes all of the function passes scheduled in the function pass	/** Initializes all of the function passes scheduled in the function pass
	manager. Returns 1 if any of the passes modified the module, 0 otherwis e.	manager. Returns 1 if any of the passes modified the module, 0 otherwis e.

	See llvm::FunctionPassManager::doInitialization. */	@see llvm::FunctionPassManager::doInitialization */
	LLVMBool LLVMInitializeFunctionPassManager(LLVMPassManagerRef FPM);	LLVMBool LLVMInitializeFunctionPassManager(LLVMPassManagerRef FPM);

	/** Executes all of the function passes scheduled in the function pass mana ger	/** Executes all of the function passes scheduled in the function pass mana ger
	on the provided function. Returns 1 if any of the passes modified the	on the provided function. Returns 1 if any of the passes modified the
	function, false otherwise.	function, false otherwise.

	See llvm::FunctionPassManager::run(Function&). */	@see llvm::FunctionPassManager::run(Function&) */
	LLVMBool LLVMRunFunctionPassManager(LLVMPassManagerRef FPM, LLVMValueRef F) ;	LLVMBool LLVMRunFunctionPassManager(LLVMPassManagerRef FPM, LLVMValueRef F) ;

	/** Finalizes all of the function passes scheduled in in the function pass	/** Finalizes all of the function passes scheduled in in the function pass
	manager. Returns 1 if any of the passes modified the module, 0 otherwis e.	manager. Returns 1 if any of the passes modified the module, 0 otherwis e.

	See llvm::FunctionPassManager::doFinalization. */	@see llvm::FunctionPassManager::doFinalization */
	LLVMBool LLVMFinalizeFunctionPassManager(LLVMPassManagerRef FPM);	LLVMBool LLVMFinalizeFunctionPassManager(LLVMPassManagerRef FPM);

	/** Frees the memory of a pass pipeline. For function pipelines, does not f ree	/** Frees the memory of a pass pipeline. For function pipelines, does not f ree
	the module provider.	the module provider.

	See llvm::PassManagerBase::~PassManagerBase. */	@see llvm::PassManagerBase::~PassManagerBase. */
	void LLVMDisposePassManager(LLVMPassManagerRef PM);	void LLVMDisposePassManager(LLVMPassManagerRef PM);


		/**
		* @}
		*/

		/**
		* @}
		*/

		/**
		* @}
		*/

	#ifdef __cplusplus	#ifdef __cplusplus
	}	}

	namespace llvm {	namespace llvm {
	class MemoryBuffer;	class MemoryBuffer;
	class PassManagerBase;	class PassManagerBase;

	#define DEFINE_SIMPLE_CONVERSION_FUNCTIONS(ty, ref) \	#define DEFINE_SIMPLE_CONVERSION_FUNCTIONS(ty, ref) \
	inline ty *unwrap(ref P) { \	inline ty *unwrap(ref P) { \
	return reinterpret_cast<ty*>(P); \	return reinterpret_cast<ty*>(P); \

End of changes. 174 change blocks.
	180 lines changed or deleted	1646 lines changed or added

	DAGDeltaAlgorithm.h	DAGDeltaAlgorithm.h

	skipping to change at line 39	skipping to change at line 39
	///	///
	/// P(S) => P(S union pred(S))	/// P(S) => P(S union pred(S))
	///	///
	/// The minization algorithm uses this dependency information to attempt to	/// The minization algorithm uses this dependency information to attempt to
	/// eagerly prune large subsets of changes. As with \see DeltaAlgorithm, th e DAG	/// eagerly prune large subsets of changes. As with \see DeltaAlgorithm, th e DAG
	/// is not required to satisfy this property, but the algorithm will run	/// is not required to satisfy this property, but the algorithm will run
	/// substantially fewer tests with appropriate dependencies. \see DeltaAlgo rithm	/// substantially fewer tests with appropriate dependencies. \see DeltaAlgo rithm
	/// for more information on the properties which the predicate function its elf	/// for more information on the properties which the predicate function its elf
	/// should satisfy.	/// should satisfy.
	class DAGDeltaAlgorithm {	class DAGDeltaAlgorithm {

		virtual void anchor();
	public:	public:
	typedef unsigned change_ty;	typedef unsigned change_ty;
	typedef std::pair<change_ty, change_ty> edge_ty;	typedef std::pair<change_ty, change_ty> edge_ty;

	// FIXME: Use a decent data structure.	// FIXME: Use a decent data structure.
	typedef std::set<change_ty> changeset_ty;	typedef std::set<change_ty> changeset_ty;
	typedef std::vector<changeset_ty> changesetlist_ty;	typedef std::vector<changeset_ty> changesetlist_ty;

	public:	public:
	virtual ~DAGDeltaAlgorithm() {}	virtual ~DAGDeltaAlgorithm() {}

End of changes. 1 change blocks.
	0 lines changed or deleted	1 lines changed or added

	DIBuilder.h	DIBuilder.h

	skipping to change at line 45	skipping to change at line 45
	class DIArray;	class DIArray;
	class DIGlobalVariable;	class DIGlobalVariable;
	class DINameSpace;	class DINameSpace;
	class DIVariable;	class DIVariable;
	class DISubrange;	class DISubrange;
	class DILexicalBlockFile;	class DILexicalBlockFile;
	class DILexicalBlock;	class DILexicalBlock;
	class DISubprogram;	class DISubprogram;
	class DITemplateTypeParameter;	class DITemplateTypeParameter;
	class DITemplateValueParameter;	class DITemplateValueParameter;

		class DIObjCProperty;

	class DIBuilder {	class DIBuilder {
	private:	private:
	Module &M;	Module &M;
	LLVMContext & VMContext;	LLVMContext & VMContext;
	MDNode *TheCU;	MDNode *TheCU;

	MDNode *TempEnumTypes;	MDNode *TempEnumTypes;
	MDNode *TempRetainTypes;	MDNode *TempRetainTypes;
	MDNode *TempSubprograms;	MDNode *TempSubprograms;

	skipping to change at line 193	skipping to change at line 194
	/// @param PropertyAttributes Objective C property attributes.	/// @param PropertyAttributes Objective C property attributes.
	DIType createObjCIVar(StringRef Name, DIFile File,	DIType createObjCIVar(StringRef Name, DIFile File,
	unsigned LineNo, uint64_t SizeInBits,	unsigned LineNo, uint64_t SizeInBits,
	uint64_t AlignInBits, uint64_t OffsetInBits,	uint64_t AlignInBits, uint64_t OffsetInBits,
	unsigned Flags, DIType Ty,	unsigned Flags, DIType Ty,
	StringRef PropertyName = StringRef(),	StringRef PropertyName = StringRef(),
	StringRef PropertyGetterName = StringRef(),	StringRef PropertyGetterName = StringRef(),
	StringRef PropertySetterName = StringRef(),	StringRef PropertySetterName = StringRef(),
	unsigned PropertyAttributes = 0);	unsigned PropertyAttributes = 0);


		/// createObjCIVar - Create debugging information entry for Objective-C
		/// instance variable.
		/// @param Name Member name.
		/// @param File File where this member is defined.
		/// @param LineNo Line number.
		/// @param SizeInBits Member size.
		/// @param AlignInBits Member alignment.
		/// @param OffsetInBits Member offset.
		/// @param Flags Flags to encode member attribute, e.g. private
		/// @param Ty Parent type.
		/// @param Property Property associated with this ivar.
		DIType createObjCIVar(StringRef Name, DIFile File,
		unsigned LineNo, uint64_t SizeInBits,
		uint64_t AlignInBits, uint64_t OffsetInBits,
		unsigned Flags, DIType Ty,
		MDNode *PropertyNode);

		/// createObjCProperty - Create debugging information entry for Objecti
		ve-C
		/// property.
		/// @param Name Property name.
		/// @param File File where this property is defined.
		/// @param LineNumber Line number.
		/// @param GetterName Name of the Objective C property getter selecto
		r.
		/// @param SetterName Name of the Objective C property setter selecto
		r.
		/// @param PropertyAttributes Objective C property attributes.
		/// @param Ty Type.
		DIObjCProperty createObjCProperty(StringRef Name,
		DIFile File, unsigned LineNumber,
		StringRef GetterName,
		StringRef SetterName,
		unsigned PropertyAttributes,
		DIType Ty);

	/// createClassType - Create debugging information entry for a class.	/// createClassType - Create debugging information entry for a class.
	/// @param Scope Scope in which this class is defined.	/// @param Scope Scope in which this class is defined.
	/// @param Name class name.	/// @param Name class name.
	/// @param File File where this member is defined.	/// @param File File where this member is defined.
	/// @param LineNo Line number.	/// @param LineNo Line number.
	/// @param SizeInBits Member size.	/// @param SizeInBits Member size.
	/// @param AlignInBits Member alignment.	/// @param AlignInBits Member alignment.
	/// @param OffsetInBits Member offset.	/// @param OffsetInBits Member offset.
	/// @param Flags Flags to encode member attribute, e.g. private	/// @param Flags Flags to encode member attribute, e.g. private
	/// @param Elements class members.	/// @param Elements class members.

	skipping to change at line 316	skipping to change at line 350
	/// includes return type at 0th index.	/// includes return type at 0th index.
	DIType createSubroutineType(DIFile File, DIArray ParameterTypes);	DIType createSubroutineType(DIFile File, DIArray ParameterTypes);

	/// createArtificialType - Create a new DIType with "artificial" flag s et.	/// createArtificialType - Create a new DIType with "artificial" flag s et.
	DIType createArtificialType(DIType Ty);	DIType createArtificialType(DIType Ty);

	/// createTemporaryType - Create a temporary forward-declared type.	/// createTemporaryType - Create a temporary forward-declared type.
	DIType createTemporaryType();	DIType createTemporaryType();
	DIType createTemporaryType(DIFile F);	DIType createTemporaryType(DIFile F);


		/// createForwardDecl - Create a temporary forward-declared type.
		DIType createForwardDecl(unsigned Tag, StringRef Name, DIFile F,
		unsigned Line, unsigned RuntimeLang = 0);

	/// retainType - Retain DIType in a module even if it is not referenced	/// retainType - Retain DIType in a module even if it is not referenced
	/// through debug info anchors.	/// through debug info anchors.
	void retainType(DIType T);	void retainType(DIType T);

	/// createUnspecifiedParameter - Create unspeicified type descriptor	/// createUnspecifiedParameter - Create unspeicified type descriptor
	/// for a subroutine type.	/// for a subroutine type.
	DIDescriptor createUnspecifiedParameter();	DIDescriptor createUnspecifiedParameter();

	/// getOrCreateArray - Get a DIArray, create one if required.	/// getOrCreateArray - Get a DIArray, create one if required.
	DIArray getOrCreateArray(ArrayRef<Value *> Elements);	DIArray getOrCreateArray(ArrayRef<Value *> Elements);

	skipping to change at line 407	skipping to change at line 445
	/// createFunction - Create a new descriptor for the specified subprogr am.	/// createFunction - Create a new descriptor for the specified subprogr am.
	/// See comments in DISubprogram for descriptions of these fields.	/// See comments in DISubprogram for descriptions of these fields.
	/// @param Scope Function scope.	/// @param Scope Function scope.
	/// @param Name Function name.	/// @param Name Function name.
	/// @param LinkageName Mangled function name.	/// @param LinkageName Mangled function name.
	/// @param File File where this variable is defined.	/// @param File File where this variable is defined.
	/// @param LineNo Line number.	/// @param LineNo Line number.
	/// @param Ty Function type.	/// @param Ty Function type.
	/// @param isLocalToUnit True if this function is not externally visibl e..	/// @param isLocalToUnit True if this function is not externally visibl e..
	/// @param isDefinition True if this is a function definition.	/// @param isDefinition True if this is a function definition.

		/// @param ScopeLine Set to the beginning of the scope this starts
	/// @param Flags e.g. is this function prototyped or not.	/// @param Flags e.g. is this function prototyped or not.
	/// This flags are used to emit dwarf attributes.	/// This flags are used to emit dwarf attributes.
	/// @param isOptimized True if optimization is ON.	/// @param isOptimized True if optimization is ON.
	/// @param Fn llvm::Function pointer.	/// @param Fn llvm::Function pointer.
	/// @param TParam Function template parameters.	/// @param TParam Function template parameters.
	DISubprogram createFunction(DIDescriptor Scope, StringRef Name,	DISubprogram createFunction(DIDescriptor Scope, StringRef Name,
	StringRef LinkageName,	StringRef LinkageName,
	DIFile File, unsigned LineNo,	DIFile File, unsigned LineNo,
	DIType Ty, bool isLocalToUnit,	DIType Ty, bool isLocalToUnit,
	bool isDefinition,	bool isDefinition,

		unsigned ScopeLine,
	unsigned Flags = 0,	unsigned Flags = 0,
	bool isOptimized = false,	bool isOptimized = false,
	Function *Fn = 0,	Function *Fn = 0,
	MDNode *TParam = 0,	MDNode *TParam = 0,
	MDNode *Decl = 0);	MDNode *Decl = 0);

	/// createMethod - Create a new descriptor for the specified C++ method .	/// createMethod - Create a new descriptor for the specified C++ method .
	/// See comments in DISubprogram for descriptions of these fields.	/// See comments in DISubprogram for descriptions of these fields.
	/// @param Scope Function scope.	/// @param Scope Function scope.
	/// @param Name Function name.	/// @param Name Function name.

	skipping to change at line 469	skipping to change at line 509
	/// @param LineNo Line number	/// @param LineNo Line number
	DINameSpace createNameSpace(DIDescriptor Scope, StringRef Name,	DINameSpace createNameSpace(DIDescriptor Scope, StringRef Name,
	DIFile File, unsigned LineNo);	DIFile File, unsigned LineNo);

	/// createLexicalBlockFile - This creates a descriptor for a lexical	/// createLexicalBlockFile - This creates a descriptor for a lexical
	/// block with a new file attached. This merely extends the existing	/// block with a new file attached. This merely extends the existing
	/// lexical block as it crosses a file.	/// lexical block as it crosses a file.
	/// @param Scope Lexical block.	/// @param Scope Lexical block.
	/// @param File Source file.	/// @param File Source file.
	DILexicalBlockFile createLexicalBlockFile(DIDescriptor Scope,	DILexicalBlockFile createLexicalBlockFile(DIDescriptor Scope,

	DIFile File);	DIFile File);

	/// createLexicalBlock - This creates a descriptor for a lexical block	/// createLexicalBlock - This creates a descriptor for a lexical block
	/// with the specified parent context.	/// with the specified parent context.
	/// @param Scope Parent lexical scope.	/// @param Scope Parent lexical scope.
	/// @param File Source file	/// @param File Source file
	/// @param Line Line number	/// @param Line Line number
	/// @param Col Column number	/// @param Col Column number
	DILexicalBlock createLexicalBlock(DIDescriptor Scope, DIFile File,	DILexicalBlock createLexicalBlock(DIDescriptor Scope, DIFile File,
	unsigned Line, unsigned Col);	unsigned Line, unsigned Col);


End of changes. 6 change blocks.
	1 lines changed or deleted	44 lines changed or added

	DOTGraphTraits.h	DOTGraphTraits.h

	skipping to change at line 45	skipping to change at line 45
	return IsSimple;	return IsSimple;
	}	}

	public:	public:
	explicit DefaultDOTGraphTraits(bool simple=false) : IsSimple (simple) {}	explicit DefaultDOTGraphTraits(bool simple=false) : IsSimple (simple) {}

	/// getGraphName - Return the label for the graph as a whole. Printed at the	/// getGraphName - Return the label for the graph as a whole. Printed at the
	/// top of the graph.	/// top of the graph.
	///	///
	template<typename GraphType>	template<typename GraphType>

	static std::string getGraphName(const GraphType& Graph) { return ""; }	static std::string getGraphName(const GraphType &) { return ""; }

	/// getGraphProperties - Return any custom properties that should be incl uded	/// getGraphProperties - Return any custom properties that should be incl uded
	/// in the top level graph structure for dot.	/// in the top level graph structure for dot.
	///	///
	template<typename GraphType>	template<typename GraphType>

	static std::string getGraphProperties(const GraphType& Graph) {	static std::string getGraphProperties(const GraphType &) {
	return "";	return "";
	}	}

	/// renderGraphFromBottomUp - If this function returns true, the graph is	/// renderGraphFromBottomUp - If this function returns true, the graph is
	/// emitted bottom-up instead of top-down. This requires graphviz 2.0 to work	/// emitted bottom-up instead of top-down. This requires graphviz 2.0 to work
	/// though.	/// though.
	static bool renderGraphFromBottomUp() {	static bool renderGraphFromBottomUp() {
	return false;	return false;
	}	}

	/// isNodeHidden - If the function returns true, the given node is not	/// isNodeHidden - If the function returns true, the given node is not
	/// displayed in the graph.	/// displayed in the graph.

	static bool isNodeHidden(const void *Node) {	static bool isNodeHidden(const void *) {
	return false;	return false;
	}	}

	/// getNodeLabel - Given a node and a pointer to the top level graph, ret urn	/// getNodeLabel - Given a node and a pointer to the top level graph, ret urn
	/// the label to print in the node.	/// the label to print in the node.
	template<typename GraphType>	template<typename GraphType>

	std::string getNodeLabel(const void *Node, const GraphType& Graph) {	std::string getNodeLabel(const void *, const GraphType &) {
	return "";	return "";
	}	}

	/// hasNodeAddressLabel - If this method returns true, the address of the node	/// hasNodeAddressLabel - If this method returns true, the address of the node
	/// is added to the label of the node.	/// is added to the label of the node.
	template<typename GraphType>	template<typename GraphType>

	static bool hasNodeAddressLabel(const void *Node, const GraphType& Graph) {	static bool hasNodeAddressLabel(const void *, const GraphType &) {
	return false;	return false;
	}	}

	/// If you want to specify custom node attributes, this is the place to d o so	/// If you want to specify custom node attributes, this is the place to d o so
	///	///
	template<typename GraphType>	template<typename GraphType>

	static std::string getNodeAttributes(const void *Node,	static std::string getNodeAttributes(const void *,
	const GraphType& Graph) {	const GraphType &) {
	return "";	return "";
	}	}

	/// If you want to override the dot attributes printed for a particular e dge,	/// If you want to override the dot attributes printed for a particular e dge,
	/// override this method.	/// override this method.
	template<typename EdgeIter, typename GraphType>	template<typename EdgeIter, typename GraphType>

	static std::string getEdgeAttributes(const void *Node, EdgeIter EI,	static std::string getEdgeAttributes(const void *, EdgeIter,
	const GraphType& Graph) {	const GraphType &) {
	return "";	return "";
	}	}

	/// getEdgeSourceLabel - If you want to label the edge source itself,	/// getEdgeSourceLabel - If you want to label the edge source itself,
	/// implement this method.	/// implement this method.
	template<typename EdgeIter>	template<typename EdgeIter>

	static std::string getEdgeSourceLabel(const void *Node, EdgeIter I) {	static std::string getEdgeSourceLabel(const void *, EdgeIter) {
	return "";	return "";
	}	}

	/// edgeTargetsEdgeSource - This method returns true if this outgoing edg e	/// edgeTargetsEdgeSource - This method returns true if this outgoing edg e
	/// should actually target another edge source, not a node. If this meth od is	/// should actually target another edge source, not a node. If this meth od is
	/// implemented, getEdgeTarget should be implemented.	/// implemented, getEdgeTarget should be implemented.
	template<typename EdgeIter>	template<typename EdgeIter>

	static bool edgeTargetsEdgeSource(const void *Node, EdgeIter I) {	static bool edgeTargetsEdgeSource(const void *, EdgeIter) {
	return false;	return false;
	}	}

	/// getEdgeTarget - If edgeTargetsEdgeSource returns true, this method is	/// getEdgeTarget - If edgeTargetsEdgeSource returns true, this method is
	/// called to determine which outgoing edge of Node is the target of this	/// called to determine which outgoing edge of Node is the target of this
	/// edge.	/// edge.
	template<typename EdgeIter>	template<typename EdgeIter>

	static EdgeIter getEdgeTarget(const void *Node, EdgeIter I) {	static EdgeIter getEdgeTarget(const void *, EdgeIter I) {
	return I;	return I;
	}	}

	/// hasEdgeDestLabels - If this function returns true, the graph is able	/// hasEdgeDestLabels - If this function returns true, the graph is able
	/// to provide labels for edge destinations.	/// to provide labels for edge destinations.
	static bool hasEdgeDestLabels() {	static bool hasEdgeDestLabels() {
	return false;	return false;
	}	}

	/// numEdgeDestLabels - If hasEdgeDestLabels, this function returns the	/// numEdgeDestLabels - If hasEdgeDestLabels, this function returns the
	/// number of incoming edge labels the given node has.	/// number of incoming edge labels the given node has.

	static unsigned numEdgeDestLabels(const void *Node) {	static unsigned numEdgeDestLabels(const void *) {
	return 0;	return 0;
	}	}

	/// getEdgeDestLabel - If hasEdgeDestLabels, this function returns the	/// getEdgeDestLabel - If hasEdgeDestLabels, this function returns the
	/// incoming edge label with the given index in the given node.	/// incoming edge label with the given index in the given node.

	static std::string getEdgeDestLabel(const void *Node, unsigned i) {	static std::string getEdgeDestLabel(const void *, unsigned) {
	return "";	return "";
	}	}

	/// addCustomGraphFeatures - If a graph is made up of more than just	/// addCustomGraphFeatures - If a graph is made up of more than just
	/// straight-forward nodes and edges, this is the place to put all of the	/// straight-forward nodes and edges, this is the place to put all of the
	/// custom stuff necessary. The GraphWriter object, instantiated with yo ur	/// custom stuff necessary. The GraphWriter object, instantiated with yo ur
	/// GraphType is passed in as an argument. You may call arbitrary method s on	/// GraphType is passed in as an argument. You may call arbitrary method s on
	/// it to add things to the output graph.	/// it to add things to the output graph.
	///	///
	template<typename GraphType, typename GraphWriter>	template<typename GraphType, typename GraphWriter>

	static void addCustomGraphFeatures(const GraphType& Graph, GraphWriter &G W) {}	static void addCustomGraphFeatures(const GraphType &, GraphWriter &) {}
	};	};

	/// DOTGraphTraits - Template class that can be specialized to customize ho w	/// DOTGraphTraits - Template class that can be specialized to customize ho w
	/// graphs are converted to 'dot' graphs. When specializing, you may inher it	/// graphs are converted to 'dot' graphs. When specializing, you may inher it
	/// from DefaultDOTGraphTraits if you don't need to override everything.	/// from DefaultDOTGraphTraits if you don't need to override everything.
	///	///
	template <typename Ty>	template <typename Ty>
	struct DOTGraphTraits : public DefaultDOTGraphTraits {	struct DOTGraphTraits : public DefaultDOTGraphTraits {
	DOTGraphTraits (bool simple=false) : DefaultDOTGraphTraits (simple) {}	DOTGraphTraits (bool simple=false) : DefaultDOTGraphTraits (simple) {}
	};	};

End of changes. 13 change blocks.
	15 lines changed or deleted	15 lines changed or added

	DOTGraphTraitsPass.h	DOTGraphTraitsPass.h

	skipping to change at line 34	skipping to change at line 34

	DOTGraphTraitsViewer(std::string GraphName, char &ID) : FunctionPass(ID) {	DOTGraphTraitsViewer(std::string GraphName, char &ID) : FunctionPass(ID) {
	Name = GraphName;	Name = GraphName;
	}	}

	virtual bool runOnFunction(Function &F) {	virtual bool runOnFunction(Function &F) {
	Analysis *Graph;	Analysis *Graph;
	std::string Title, GraphName;	std::string Title, GraphName;
	Graph = &getAnalysis<Analysis>();	Graph = &getAnalysis<Analysis>();
	GraphName = DOTGraphTraits<Analysis*>::getGraphName(Graph);	GraphName = DOTGraphTraits<Analysis*>::getGraphName(Graph);

	Title = GraphName + " for '" + F.getNameStr() + "' function";	Title = GraphName + " for '" + F.getName().str() + "' function";
	ViewGraph(Graph, Name, Simple, Title);	ViewGraph(Graph, Name, Simple, Title);

	return false;	return false;
	}	}

	virtual void getAnalysisUsage(AnalysisUsage &AU) const {	virtual void getAnalysisUsage(AnalysisUsage &AU) const {
	AU.setPreservesAll();	AU.setPreservesAll();
	AU.addRequired<Analysis>();	AU.addRequired<Analysis>();
	}	}
	};	};

	skipping to change at line 58	skipping to change at line 58

	std::string Name;	std::string Name;

	DOTGraphTraitsPrinter(std::string GraphName, char &ID)	DOTGraphTraitsPrinter(std::string GraphName, char &ID)
	: FunctionPass(ID) {	: FunctionPass(ID) {
	Name = GraphName;	Name = GraphName;
	}	}

	virtual bool runOnFunction(Function &F) {	virtual bool runOnFunction(Function &F) {
	Analysis *Graph;	Analysis *Graph;

	std::string Filename = Name + "." + F.getNameStr() + ".dot";	std::string Filename = Name + "." + F.getName().str() + ".dot";
	errs() << "Writing '" << Filename << "'...";	errs() << "Writing '" << Filename << "'...";

	std::string ErrorInfo;	std::string ErrorInfo;
	raw_fd_ostream File(Filename.c_str(), ErrorInfo);	raw_fd_ostream File(Filename.c_str(), ErrorInfo);
	Graph = &getAnalysis<Analysis>();	Graph = &getAnalysis<Analysis>();

	std::string Title, GraphName;	std::string Title, GraphName;
	GraphName = DOTGraphTraits<Analysis*>::getGraphName(Graph);	GraphName = DOTGraphTraits<Analysis*>::getGraphName(Graph);

	Title = GraphName + " for '" + F.getNameStr() + "' function";	Title = GraphName + " for '" + F.getName().str() + "' function";

	if (ErrorInfo.empty())	if (ErrorInfo.empty())
	WriteGraph(File, Graph, Simple, Title);	WriteGraph(File, Graph, Simple, Title);
	else	else
	errs() << " error opening file for writing!";	errs() << " error opening file for writing!";
	errs() << "\n";	errs() << "\n";
	return false;	return false;
	}	}

	virtual void getAnalysisUsage(AnalysisUsage &AU) const {	virtual void getAnalysisUsage(AnalysisUsage &AU) const {

End of changes. 3 change blocks.
	3 lines changed or deleted	3 lines changed or added

	DataTypes.h	DataTypes.h

	skipping to change at line 171	skipping to change at line 171
	#ifndef UINT32_C	#ifndef UINT32_C
	# define UINT32_C(C) C##ui32	# define UINT32_C(C) C##ui32
	#endif	#endif
	#ifndef INT64_C	#ifndef INT64_C
	# define INT64_C(C) C##i64	# define INT64_C(C) C##i64
	#endif	#endif
	#ifndef UINT64_C	#ifndef UINT64_C
	# define UINT64_C(C) C##ui64	# define UINT64_C(C) C##ui64
	#endif	#endif


		#ifndef PRId64
		# define PRId64 "I64d"
		#endif
		#ifndef PRIi64
		# define PRIi64 "I64i"
		#endif
		#ifndef PRIo64
		# define PRIo64 "I64o"
		#endif
		#ifndef PRIu64
		# define PRIu64 "I64u"
		#endif
	#ifndef PRIx64	#ifndef PRIx64
	# define PRIx64 "I64x"	# define PRIx64 "I64x"
	#endif	#endif

		#ifndef PRIX64
		# define PRIX64 "I64X"
		#endif

	#endif /* _MSC_VER */	#endif /* _MSC_VER */

	/* Set defaults for constants which we cannot find. */	/* Set defaults for constants which we cannot find. */
	#if !defined(INT64_MAX)	#if !defined(INT64_MAX)
	# define INT64_MAX 9223372036854775807LL	# define INT64_MAX 9223372036854775807LL
	#endif	#endif
	#if !defined(INT64_MIN)	#if !defined(INT64_MIN)
	# define INT64_MIN ((-INT64_MAX)-1)	# define INT64_MIN ((-INT64_MAX)-1)
	#endif	#endif

End of changes. 2 change blocks.
	0 lines changed or deleted	15 lines changed or added

	DebugInfo.h	DebugInfo.h

	skipping to change at line 46	skipping to change at line 46
	class NamedMDNode;	class NamedMDNode;
	class LLVMContext;	class LLVMContext;
	class raw_ostream;	class raw_ostream;

	class DIFile;	class DIFile;
	class DISubprogram;	class DISubprogram;
	class DILexicalBlock;	class DILexicalBlock;
	class DILexicalBlockFile;	class DILexicalBlockFile;
	class DIVariable;	class DIVariable;
	class DIType;	class DIType;

		class DIObjCProperty;

	/// DIDescriptor - A thin wraper around MDNode to access encoded debug in fo.	/// DIDescriptor - A thin wraper around MDNode to access encoded debug in fo.
	/// This should not be stored in a container, because underly MDNode may	/// This should not be stored in a container, because underly MDNode may
	/// change in certain situations.	/// change in certain situations.
	class DIDescriptor {	class DIDescriptor {
	public:	public:
	enum {	enum {
	FlagPrivate = 1 << 0,	FlagPrivate = 1 << 0,
	FlagProtected = 1 << 1,	FlagProtected = 1 << 1,
	FlagFwdDecl = 1 << 2,	FlagFwdDecl = 1 << 2,

	skipping to change at line 131	skipping to change at line 132
	bool isNameSpace() const;	bool isNameSpace() const;
	bool isLexicalBlockFile() const;	bool isLexicalBlockFile() const;
	bool isLexicalBlock() const;	bool isLexicalBlock() const;
	bool isSubrange() const;	bool isSubrange() const;
	bool isEnumerator() const;	bool isEnumerator() const;
	bool isType() const;	bool isType() const;
	bool isGlobal() const;	bool isGlobal() const;
	bool isUnspecifiedParameter() const;	bool isUnspecifiedParameter() const;
	bool isTemplateTypeParameter() const;	bool isTemplateTypeParameter() const;
	bool isTemplateValueParameter() const;	bool isTemplateValueParameter() const;

		bool isObjCProperty() const;
	};	};

	/// DISubrange - This is used to represent ranges, for array bounds.	/// DISubrange - This is used to represent ranges, for array bounds.
	class DISubrange : public DIDescriptor {	class DISubrange : public DIDescriptor {
	public:	public:
	explicit DISubrange(const MDNode *N = 0) : DIDescriptor(N) {}	explicit DISubrange(const MDNode *N = 0) : DIDescriptor(N) {}


	int64_t getLo() const { return (int64_t)getUInt64Field(1); }	uint64_t getLo() const { return getUInt64Field(1); }
	int64_t getHi() const { return (int64_t)getUInt64Field(2); }	uint64_t getHi() const { return getUInt64Field(2); }
	};	};

	/// DIArray - This descriptor holds an array of descriptors.	/// DIArray - This descriptor holds an array of descriptors.
	class DIArray : public DIDescriptor {	class DIArray : public DIDescriptor {
	public:	public:
	explicit DIArray(const MDNode *N = 0)	explicit DIArray(const MDNode *N = 0)
	: DIDescriptor(N) {}	: DIDescriptor(N) {}

	unsigned getNumElements() const;	unsigned getNumElements() const;
	DIDescriptor getElement(unsigned Idx) const {	DIDescriptor getElement(unsigned Idx) const {
	return getDescriptorField(Idx);	return getDescriptorField(Idx);
	}	}
	};	};

	/// DIScope - A base class for various scopes.	/// DIScope - A base class for various scopes.
	class DIScope : public DIDescriptor {	class DIScope : public DIDescriptor {

		virtual void anchor();
	public:	public:
	explicit DIScope(const MDNode *N = 0) : DIDescriptor (N) {}	explicit DIScope(const MDNode *N = 0) : DIDescriptor (N) {}
	virtual ~DIScope() {}	virtual ~DIScope() {}

	StringRef getFilename() const;	StringRef getFilename() const;
	StringRef getDirectory() const;	StringRef getDirectory() const;
	};	};

	/// DICompileUnit - A wrapper for a compile unit.	/// DICompileUnit - A wrapper for a compile unit.
	class DICompileUnit : public DIScope {	class DICompileUnit : public DIScope {

		virtual void anchor();
	public:	public:
	explicit DICompileUnit(const MDNode *N = 0) : DIScope(N) {}	explicit DICompileUnit(const MDNode *N = 0) : DIScope(N) {}

	unsigned getLanguage() const { return getUnsignedField(2); }	unsigned getLanguage() const { return getUnsignedField(2); }
	StringRef getFilename() const { return getStringField(3); }	StringRef getFilename() const { return getStringField(3); }
	StringRef getDirectory() const { return getStringField(4); }	StringRef getDirectory() const { return getStringField(4); }
	StringRef getProducer() const { return getStringField(5); }	StringRef getProducer() const { return getStringField(5); }

	/// isMain - Each input file is encoded as a separate compile unit in L LVM	/// isMain - Each input file is encoded as a separate compile unit in L LVM
	/// debugging information output. However, many target specific tool ch ains	/// debugging information output. However, many target specific tool ch ains

	skipping to change at line 205	skipping to change at line 209

	/// print - print compile unit.	/// print - print compile unit.
	void print(raw_ostream &OS) const;	void print(raw_ostream &OS) const;

	/// dump - print compile unit to dbgs() with a newline.	/// dump - print compile unit to dbgs() with a newline.
	void dump() const;	void dump() const;
	};	};

	/// DIFile - This is a wrapper for a file.	/// DIFile - This is a wrapper for a file.
	class DIFile : public DIScope {	class DIFile : public DIScope {

		virtual void anchor();
	public:	public:
	explicit DIFile(const MDNode *N = 0) : DIScope(N) {	explicit DIFile(const MDNode *N = 0) : DIScope(N) {
	if (DbgNode && !isFile())	if (DbgNode && !isFile())
	DbgNode = 0;	DbgNode = 0;
	}	}
	StringRef getFilename() const { return getStringField(1); }	StringRef getFilename() const { return getStringField(1); }
	StringRef getDirectory() const { return getStringField(2); }	StringRef getDirectory() const { return getStringField(2); }
	DICompileUnit getCompileUnit() const{	DICompileUnit getCompileUnit() const{
	assert (getVersion() <= LLVMDebugVersion10 && "Invalid CompileUnit!" );	assert (getVersion() <= LLVMDebugVersion10 && "Invalid CompileUnit!" );
	return getFieldAs<DICompileUnit>(3);	return getFieldAs<DICompileUnit>(3);

	skipping to change at line 233	skipping to change at line 238
	explicit DIEnumerator(const MDNode *N = 0) : DIDescriptor(N) {}	explicit DIEnumerator(const MDNode *N = 0) : DIDescriptor(N) {}

	StringRef getName() const { return getStringField(1); }	StringRef getName() const { return getStringField(1); }
	uint64_t getEnumValue() const { return getUInt64Field(2); }	uint64_t getEnumValue() const { return getUInt64Field(2); }
	};	};

	/// DIType - This is a wrapper for a type.	/// DIType - This is a wrapper for a type.
	/// FIXME: Types should be factored much better so that CV qualifiers and	/// FIXME: Types should be factored much better so that CV qualifiers and
	/// others do not require a huge and empty descriptor full of zeros.	/// others do not require a huge and empty descriptor full of zeros.
	class DIType : public DIScope {	class DIType : public DIScope {

	public:	virtual void anchor();
	protected:	protected:
	// This ctor is used when the Tag has already been validated by a deriv ed	// This ctor is used when the Tag has already been validated by a deriv ed
	// ctor.	// ctor.
	DIType(const MDNode *N, bool, bool) : DIScope(N) {}	DIType(const MDNode *N, bool, bool) : DIScope(N) {}

	public:	public:

	/// Verify - Verify that a type descriptor is well formed.	/// Verify - Verify that a type descriptor is well formed.
	bool Verify() const;	bool Verify() const;

	public:
	explicit DIType(const MDNode *N);	explicit DIType(const MDNode *N);
	explicit DIType() {}	explicit DIType() {}
	virtual ~DIType() {}	virtual ~DIType() {}

	DIScope getContext() const { return getFieldAs<DIScope>(1); }	DIScope getContext() const { return getFieldAs<DIScope>(1); }
	StringRef getName() const { return getStringField(2); }	StringRef getName() const { return getStringField(2); }
	DICompileUnit getCompileUnit() const{	DICompileUnit getCompileUnit() const{
	assert (getVersion() <= LLVMDebugVersion10 && "Invalid getCompileUnit !");	assert (getVersion() <= LLVMDebugVersion10 && "Invalid getCompileUnit !");
	if (getVersion() == llvm::LLVMDebugVersion7)	if (getVersion() == llvm::LLVMDebugVersion7)
	return getFieldAs<DICompileUnit>(3);	return getFieldAs<DICompileUnit>(3);

	skipping to change at line 323	skipping to change at line 327

	/// print - print type.	/// print - print type.
	void print(raw_ostream &OS) const;	void print(raw_ostream &OS) const;

	/// dump - print type to dbgs() with a newline.	/// dump - print type to dbgs() with a newline.
	void dump() const;	void dump() const;
	};	};

	/// DIBasicType - A basic type, like 'int' or 'float'.	/// DIBasicType - A basic type, like 'int' or 'float'.
	class DIBasicType : public DIType {	class DIBasicType : public DIType {

		virtual void anchor();
	public:	public:
	explicit DIBasicType(const MDNode *N = 0) : DIType(N) {}	explicit DIBasicType(const MDNode *N = 0) : DIType(N) {}

	unsigned getEncoding() const { return getUnsignedField(9); }	unsigned getEncoding() const { return getUnsignedField(9); }

	/// Verify - Verify that a basic type descriptor is well formed.	/// Verify - Verify that a basic type descriptor is well formed.
	bool Verify() const;	bool Verify() const;

	/// print - print basic type.	/// print - print basic type.
	void print(raw_ostream &OS) const;	void print(raw_ostream &OS) const;

	/// dump - print basic type to dbgs() with a newline.	/// dump - print basic type to dbgs() with a newline.
	void dump() const;	void dump() const;
	};	};

	/// DIDerivedType - A simple derived type, like a const qualified type,	/// DIDerivedType - A simple derived type, like a const qualified type,
	/// a typedef, a pointer or reference, etc.	/// a typedef, a pointer or reference, etc.
	class DIDerivedType : public DIType {	class DIDerivedType : public DIType {

		virtual void anchor();
	protected:	protected:
	explicit DIDerivedType(const MDNode *N, bool, bool)	explicit DIDerivedType(const MDNode *N, bool, bool)
	: DIType(N, true, true) {}	: DIType(N, true, true) {}
	public:	public:
	explicit DIDerivedType(const MDNode *N = 0)	explicit DIDerivedType(const MDNode *N = 0)
	: DIType(N, true, true) {}	: DIType(N, true, true) {}

	DIType getTypeDerivedFrom() const { return getFieldAs<DIType>(9); }	DIType getTypeDerivedFrom() const { return getFieldAs<DIType>(9); }

	/// getOriginalTypeSize - If this type is derived from a base type then	/// getOriginalTypeSize - If this type is derived from a base type then
	/// return base type size.	/// return base type size.
	uint64_t getOriginalTypeSize() const;	uint64_t getOriginalTypeSize() const;


	StringRef getObjCPropertyName() const { return getStringField(10); }	/// getObjCProperty - Return property node, if this ivar is
		/// associated with one.
		MDNode *getObjCProperty() const;

		StringRef getObjCPropertyName() const {
		if (getVersion() > LLVMDebugVersion11)
		return StringRef();
		return getStringField(10);
		}
	StringRef getObjCPropertyGetterName() const {	StringRef getObjCPropertyGetterName() const {

		assert (getVersion() <= LLVMDebugVersion11 && "Invalid Request");
	return getStringField(11);	return getStringField(11);
	}	}
	StringRef getObjCPropertySetterName() const {	StringRef getObjCPropertySetterName() const {

		assert (getVersion() <= LLVMDebugVersion11 && "Invalid Request");
	return getStringField(12);	return getStringField(12);
	}	}
	bool isReadOnlyObjCProperty() {	bool isReadOnlyObjCProperty() {

		assert (getVersion() <= LLVMDebugVersion11 && "Invalid Request");
	return (getUnsignedField(13) & dwarf::DW_APPLE_PROPERTY_readonly) != 0;	return (getUnsignedField(13) & dwarf::DW_APPLE_PROPERTY_readonly) != 0;
	}	}
	bool isReadWriteObjCProperty() {	bool isReadWriteObjCProperty() {

		assert (getVersion() <= LLVMDebugVersion11 && "Invalid Request");
	return (getUnsignedField(13) & dwarf::DW_APPLE_PROPERTY_readwrite) != 0;	return (getUnsignedField(13) & dwarf::DW_APPLE_PROPERTY_readwrite) != 0;
	}	}
	bool isAssignObjCProperty() {	bool isAssignObjCProperty() {

		assert (getVersion() <= LLVMDebugVersion11 && "Invalid Request");
	return (getUnsignedField(13) & dwarf::DW_APPLE_PROPERTY_assign) != 0;	return (getUnsignedField(13) & dwarf::DW_APPLE_PROPERTY_assign) != 0;
	}	}
	bool isRetainObjCProperty() {	bool isRetainObjCProperty() {

		assert (getVersion() <= LLVMDebugVersion11 && "Invalid Request");
	return (getUnsignedField(13) & dwarf::DW_APPLE_PROPERTY_retain) != 0;	return (getUnsignedField(13) & dwarf::DW_APPLE_PROPERTY_retain) != 0;
	}	}
	bool isCopyObjCProperty() {	bool isCopyObjCProperty() {

		assert (getVersion() <= LLVMDebugVersion11 && "Invalid Request");
	return (getUnsignedField(13) & dwarf::DW_APPLE_PROPERTY_copy) != 0;	return (getUnsignedField(13) & dwarf::DW_APPLE_PROPERTY_copy) != 0;
	}	}
	bool isNonAtomicObjCProperty() {	bool isNonAtomicObjCProperty() {

		assert (getVersion() <= LLVMDebugVersion11 && "Invalid Request");
	return (getUnsignedField(13) & dwarf::DW_APPLE_PROPERTY_nonatomic) != 0;	return (getUnsignedField(13) & dwarf::DW_APPLE_PROPERTY_nonatomic) != 0;
	}	}

	/// Verify - Verify that a derived type descriptor is well formed.	/// Verify - Verify that a derived type descriptor is well formed.
	bool Verify() const;	bool Verify() const;

	/// print - print derived type.	/// print - print derived type.
	void print(raw_ostream &OS) const;	void print(raw_ostream &OS) const;

	/// dump - print derived type to dbgs() with a newline.	/// dump - print derived type to dbgs() with a newline.
	void dump() const;	void dump() const;
	};	};

	/// DICompositeType - This descriptor holds a type that can refer to mult iple	/// DICompositeType - This descriptor holds a type that can refer to mult iple
	/// other types, like a function or struct.	/// other types, like a function or struct.
	/// FIXME: Why is this a DIDerivedType??	/// FIXME: Why is this a DIDerivedType??
	class DICompositeType : public DIDerivedType {	class DICompositeType : public DIDerivedType {

		virtual void anchor();
	public:	public:
	explicit DICompositeType(const MDNode *N = 0)	explicit DICompositeType(const MDNode *N = 0)
	: DIDerivedType(N, true, true) {	: DIDerivedType(N, true, true) {
	if (N && !isCompositeType())	if (N && !isCompositeType())
	DbgNode = 0;	DbgNode = 0;
	}	}

	DIArray getTypeArray() const { return getFieldAs<DIArray>(10); }	DIArray getTypeArray() const { return getFieldAs<DIArray>(10); }
	unsigned getRunTimeLang() const { return getUnsignedField(11); }	unsigned getRunTimeLang() const { return getUnsignedField(11); }
	DICompositeType getContainingType() const {	DICompositeType getContainingType() const {

	skipping to change at line 457	skipping to change at line 480
	}	}
	StringRef getDirectory() const {	StringRef getDirectory() const {
	return getFieldAs<DIFile>(5).getDirectory();	return getFieldAs<DIFile>(5).getDirectory();
	}	}
	unsigned getLineNumber() const { return getUnsignedField(6); }	unsigned getLineNumber() const { return getUnsignedField(6); }
	unsigned getColumnNumber() const { return getUnsignedField(7); }	unsigned getColumnNumber() const { return getUnsignedField(7); }
	};	};

	/// DISubprogram - This is a wrapper for a subprogram (e.g. a function).	/// DISubprogram - This is a wrapper for a subprogram (e.g. a function).
	class DISubprogram : public DIScope {	class DISubprogram : public DIScope {

		virtual void anchor();
	public:	public:
	explicit DISubprogram(const MDNode *N = 0) : DIScope(N) {}	explicit DISubprogram(const MDNode *N = 0) : DIScope(N) {}

	DIScope getContext() const { return getFieldAs<DIScope>(2); }	DIScope getContext() const { return getFieldAs<DIScope>(2); }
	StringRef getName() const { return getStringField(3); }	StringRef getName() const { return getStringField(3); }
	StringRef getDisplayName() const { return getStringField(4); }	StringRef getDisplayName() const { return getStringField(4); }
	StringRef getLinkageName() const { return getStringField(5); }	StringRef getLinkageName() const { return getStringField(5); }
	DICompileUnit getCompileUnit() const{	DICompileUnit getCompileUnit() const{
	assert (getVersion() <= LLVMDebugVersion10 && "Invalid getCompileUnit !");	assert (getVersion() <= LLVMDebugVersion10 && "Invalid getCompileUnit !");
	if (getVersion() == llvm::LLVMDebugVersion7)	if (getVersion() == llvm::LLVMDebugVersion7)

	skipping to change at line 498	skipping to change at line 522
	/// compile unit, like 'static' in C.	/// compile unit, like 'static' in C.
	unsigned isLocalToUnit() const { return getUnsignedField(9); }	unsigned isLocalToUnit() const { return getUnsignedField(9); }
	unsigned isDefinition() const { return getUnsignedField(10); }	unsigned isDefinition() const { return getUnsignedField(10); }

	unsigned getVirtuality() const { return getUnsignedField(11); }	unsigned getVirtuality() const { return getUnsignedField(11); }
	unsigned getVirtualIndex() const { return getUnsignedField(12); }	unsigned getVirtualIndex() const { return getUnsignedField(12); }

	DICompositeType getContainingType() const {	DICompositeType getContainingType() const {
	return getFieldAs<DICompositeType>(13);	return getFieldAs<DICompositeType>(13);
	}	}


	unsigned isArtificial() const {	unsigned isArtificial() const {
	if (getVersion() <= llvm::LLVMDebugVersion8)	if (getVersion() <= llvm::LLVMDebugVersion8)
	return getUnsignedField(14);	return getUnsignedField(14);
	return (getUnsignedField(14) & FlagArtificial) != 0;	return (getUnsignedField(14) & FlagArtificial) != 0;
	}	}
	/// isPrivate - Return true if this subprogram has "private"	/// isPrivate - Return true if this subprogram has "private"
	/// access specifier.	/// access specifier.
	bool isPrivate() const {	bool isPrivate() const {
	if (getVersion() <= llvm::LLVMDebugVersion8)	if (getVersion() <= llvm::LLVMDebugVersion8)
	return false;	return false;

	skipping to change at line 546	skipping to change at line 571
	return getFieldAs<DIFile>(6).getFilename();	return getFieldAs<DIFile>(6).getFilename();
	}	}

	StringRef getDirectory() const {	StringRef getDirectory() const {
	if (getVersion() == llvm::LLVMDebugVersion7)	if (getVersion() == llvm::LLVMDebugVersion7)
	return getCompileUnit().getFilename();	return getCompileUnit().getFilename();

	return getFieldAs<DIFile>(6).getDirectory();	return getFieldAs<DIFile>(6).getDirectory();
	}	}


		/// getScopeLineNumber - Get the beginning of the scope of the
		/// function, not necessarily where the name of the program
		/// starts.
		unsigned getScopeLineNumber() const { return getUnsignedField(20); }

	/// Verify - Verify that a subprogram descriptor is well formed.	/// Verify - Verify that a subprogram descriptor is well formed.
	bool Verify() const;	bool Verify() const;

	/// print - print subprogram.	/// print - print subprogram.
	void print(raw_ostream &OS) const;	void print(raw_ostream &OS) const;

	/// dump - print subprogram to dbgs() with a newline.	/// dump - print subprogram to dbgs() with a newline.
	void dump() const;	void dump() const;

	/// describes - Return true if this subprogram provides debugging	/// describes - Return true if this subprogram provides debugging

	skipping to change at line 624	skipping to change at line 654

	/// DIVariable - This is a wrapper for a variable (e.g. parameter, local,	/// DIVariable - This is a wrapper for a variable (e.g. parameter, local,
	/// global etc).	/// global etc).
	class DIVariable : public DIDescriptor {	class DIVariable : public DIDescriptor {
	public:	public:
	explicit DIVariable(const MDNode *N = 0)	explicit DIVariable(const MDNode *N = 0)
	: DIDescriptor(N) {}	: DIDescriptor(N) {}

	DIScope getContext() const { return getFieldAs<DIScope>(1); }	DIScope getContext() const { return getFieldAs<DIScope>(1); }
	StringRef getName() const { return getStringField(2); }	StringRef getName() const { return getStringField(2); }

	DICompileUnit getCompileUnit() const{	DICompileUnit getCompileUnit() const {
	assert (getVersion() <= LLVMDebugVersion10 && "Invalid getCompileUnit !");	assert (getVersion() <= LLVMDebugVersion10 && "Invalid getCompileUnit !");
	if (getVersion() == llvm::LLVMDebugVersion7)	if (getVersion() == llvm::LLVMDebugVersion7)
	return getFieldAs<DICompileUnit>(3);	return getFieldAs<DICompileUnit>(3);

	DIFile F = getFieldAs<DIFile>(3);	DIFile F = getFieldAs<DIFile>(3);
	return F.getCompileUnit();	return F.getCompileUnit();
	}	}
	unsigned getLineNumber() const {	unsigned getLineNumber() const {
	return (getUnsignedField(4) << 8) >> 8;	return (getUnsignedField(4) << 8) >> 8;
	}	}

	skipping to change at line 690	skipping to change at line 720
	void print(raw_ostream &OS) const;	void print(raw_ostream &OS) const;

	void printExtendedName(raw_ostream &OS) const;	void printExtendedName(raw_ostream &OS) const;

	/// dump - print variable to dbgs() with a newline.	/// dump - print variable to dbgs() with a newline.
	void dump() const;	void dump() const;
	};	};

	/// DILexicalBlock - This is a wrapper for a lexical block.	/// DILexicalBlock - This is a wrapper for a lexical block.
	class DILexicalBlock : public DIScope {	class DILexicalBlock : public DIScope {

		virtual void anchor();
	public:	public:
	explicit DILexicalBlock(const MDNode *N = 0) : DIScope(N) {}	explicit DILexicalBlock(const MDNode *N = 0) : DIScope(N) {}
	DIScope getContext() const { return getFieldAs<DIScope>(1); }	DIScope getContext() const { return getFieldAs<DIScope>(1); }
	unsigned getLineNumber() const { return getUnsignedField(2); }	unsigned getLineNumber() const { return getUnsignedField(2); }
	unsigned getColumnNumber() const { return getUnsignedField(3); }	unsigned getColumnNumber() const { return getUnsignedField(3); }
	StringRef getDirectory() const {	StringRef getDirectory() const {
	StringRef dir = getFieldAs<DIFile>(4).getDirectory();	StringRef dir = getFieldAs<DIFile>(4).getDirectory();
	return !dir.empty() ? dir : getContext().getDirectory();	return !dir.empty() ? dir : getContext().getDirectory();
	}	}
	StringRef getFilename() const {	StringRef getFilename() const {
	StringRef filename = getFieldAs<DIFile>(4).getFilename();	StringRef filename = getFieldAs<DIFile>(4).getFilename();
	return !filename.empty() ? filename : getContext().getFilename();	return !filename.empty() ? filename : getContext().getFilename();
	}	}
	};	};

	/// DILexicalBlockFile - This is a wrapper for a lexical block with	/// DILexicalBlockFile - This is a wrapper for a lexical block with
	/// a filename change.	/// a filename change.
	class DILexicalBlockFile : public DIScope {	class DILexicalBlockFile : public DIScope {

		virtual void anchor();
	public:	public:
	explicit DILexicalBlockFile(const MDNode *N = 0) : DIScope(N) {}	explicit DILexicalBlockFile(const MDNode *N = 0) : DIScope(N) {}
	DIScope getContext() const { return getScope().getContext(); }	DIScope getContext() const { return getScope().getContext(); }
	unsigned getLineNumber() const { return getScope().getLineNumber(); }	unsigned getLineNumber() const { return getScope().getLineNumber(); }
	unsigned getColumnNumber() const { return getScope().getColumnNumber(); }	unsigned getColumnNumber() const { return getScope().getColumnNumber(); }
	StringRef getDirectory() const {	StringRef getDirectory() const {
	StringRef dir = getFieldAs<DIFile>(2).getDirectory();	StringRef dir = getFieldAs<DIFile>(2).getDirectory();
	return !dir.empty() ? dir : getContext().getDirectory();	return !dir.empty() ? dir : getContext().getDirectory();
	}	}
	StringRef getFilename() const {	StringRef getFilename() const {
	StringRef filename = getFieldAs<DIFile>(2).getFilename();	StringRef filename = getFieldAs<DIFile>(2).getFilename();
	assert(!filename.empty() && "Why'd you create this then?");	assert(!filename.empty() && "Why'd you create this then?");
	return filename;	return filename;
	}	}
	DILexicalBlock getScope() const { return getFieldAs<DILexicalBlock>(1); }	DILexicalBlock getScope() const { return getFieldAs<DILexicalBlock>(1); }
	};	};

	/// DINameSpace - A wrapper for a C++ style name space.	/// DINameSpace - A wrapper for a C++ style name space.
	class DINameSpace : public DIScope {	class DINameSpace : public DIScope {

		virtual void anchor();
	public:	public:
	explicit DINameSpace(const MDNode *N = 0) : DIScope(N) {}	explicit DINameSpace(const MDNode *N = 0) : DIScope(N) {}
	DIScope getContext() const { return getFieldAs<DIScope>(1); }	DIScope getContext() const { return getFieldAs<DIScope>(1); }
	StringRef getName() const { return getStringField(2); }	StringRef getName() const { return getStringField(2); }
	StringRef getDirectory() const {	StringRef getDirectory() const {
	return getFieldAs<DIFile>(3).getDirectory();	return getFieldAs<DIFile>(3).getDirectory();
	}	}
	StringRef getFilename() const {	StringRef getFilename() const {
	return getFieldAs<DIFile>(3).getFilename();	return getFieldAs<DIFile>(3).getFilename();
	}	}

	skipping to change at line 763	skipping to change at line 796

	unsigned getLineNumber() const { return getUnsignedField(0); }	unsigned getLineNumber() const { return getUnsignedField(0); }
	unsigned getColumnNumber() const { return getUnsignedField(1); }	unsigned getColumnNumber() const { return getUnsignedField(1); }
	DIScope getScope() const { return getFieldAs<DIScope>(2); }	DIScope getScope() const { return getFieldAs<DIScope>(2); }
	DILocation getOrigLocation() const { return getFieldAs<DILocation>(3); }	DILocation getOrigLocation() const { return getFieldAs<DILocation>(3); }
	StringRef getFilename() const { return getScope().getFilename(); }	StringRef getFilename() const { return getScope().getFilename(); }
	StringRef getDirectory() const { return getScope().getDirectory(); }	StringRef getDirectory() const { return getScope().getDirectory(); }
	bool Verify() const;	bool Verify() const;
	};	};


		class DIObjCProperty : public DIDescriptor {
		public:
		explicit DIObjCProperty(const MDNode *N) : DIDescriptor(N) { }

		StringRef getObjCPropertyName() const { return getStringField(1); }
		DIFile getFile() const { return getFieldAs<DIFile>(2); }
		unsigned getLineNumber() const { return getUnsignedField(3); }

		StringRef getObjCPropertyGetterName() const {
		return getStringField(4);
		}
		StringRef getObjCPropertySetterName() const {
		return getStringField(5);
		}
		bool isReadOnlyObjCProperty() {
		return (getUnsignedField(6) & dwarf::DW_APPLE_PROPERTY_readonly) != 0
		;
		}
		bool isReadWriteObjCProperty() {
		return (getUnsignedField(6) & dwarf::DW_APPLE_PROPERTY_readwrite) !=
		0;
		}
		bool isAssignObjCProperty() {
		return (getUnsignedField(6) & dwarf::DW_APPLE_PROPERTY_assign) != 0;
		}
		bool isRetainObjCProperty() {
		return (getUnsignedField(6) & dwarf::DW_APPLE_PROPERTY_retain) != 0;
		}
		bool isCopyObjCProperty() {
		return (getUnsignedField(6) & dwarf::DW_APPLE_PROPERTY_copy) != 0;
		}
		bool isNonAtomicObjCProperty() {
		return (getUnsignedField(6) & dwarf::DW_APPLE_PROPERTY_nonatomic) !=
		0;
		}

		DIType getType() const { return getFieldAs<DIType>(7); }

		/// Verify - Verify that a derived type descriptor is well formed.
		bool Verify() const;

		/// print - print derived type.
		void print(raw_ostream &OS) const;

		/// dump - print derived type to dbgs() with a newline.
		void dump() const;
		};

	/// getDISubprogram - Find subprogram that is enclosing this scope.	/// getDISubprogram - Find subprogram that is enclosing this scope.
	DISubprogram getDISubprogram(const MDNode *Scope);	DISubprogram getDISubprogram(const MDNode *Scope);

	/// getDICompositeType - Find underlying composite type.	/// getDICompositeType - Find underlying composite type.
	DICompositeType getDICompositeType(DIType T);	DICompositeType getDICompositeType(DIType T);

	/// isSubprogramContext - Return true if Context is either a subprogram	/// isSubprogramContext - Return true if Context is either a subprogram
	/// or another context nested inside a subprogram.	/// or another context nested inside a subprogram.
	bool isSubprogramContext(const MDNode *Context);	bool isSubprogramContext(const MDNode *Context);


	skipping to change at line 819	skipping to change at line 897

	/// processLocation - Process DILocation.	/// processLocation - Process DILocation.
	void processLocation(DILocation Loc);	void processLocation(DILocation Loc);

	/// addCompileUnit - Add compile unit into CUs.	/// addCompileUnit - Add compile unit into CUs.
	bool addCompileUnit(DICompileUnit CU);	bool addCompileUnit(DICompileUnit CU);

	/// addGlobalVariable - Add global variable into GVs.	/// addGlobalVariable - Add global variable into GVs.
	bool addGlobalVariable(DIGlobalVariable DIG);	bool addGlobalVariable(DIGlobalVariable DIG);


	// addSubprogram - Add subprgoram into SPs.	// addSubprogram - Add subprogram into SPs.
	bool addSubprogram(DISubprogram SP);	bool addSubprogram(DISubprogram SP);

	/// addType - Add type into Tys.	/// addType - Add type into Tys.
	bool addType(DIType DT);	bool addType(DIType DT);

	public:	public:
	typedef SmallVector<MDNode *, 8>::const_iterator iterator;	typedef SmallVector<MDNode *, 8>::const_iterator iterator;
	iterator compile_unit_begin() const { return CUs.begin(); }	iterator compile_unit_begin() const { return CUs.begin(); }
	iterator compile_unit_end() const { return CUs.end(); }	iterator compile_unit_end() const { return CUs.end(); }
	iterator subprogram_begin() const { return SPs.begin(); }	iterator subprogram_begin() const { return SPs.begin(); }

End of changes. 29 change blocks.
	7 lines changed or deleted	88 lines changed or added

	DenseMap.h	DenseMap.h

	skipping to change at line 33	skipping to change at line 33
	#include <new>	#include <new>
	#include <utility>	#include <utility>
	#include <cassert>	#include <cassert>
	#include <cstddef>	#include <cstddef>
	#include <cstring>	#include <cstring>

	namespace llvm {	namespace llvm {

	template<typename KeyT, typename ValueT,	template<typename KeyT, typename ValueT,
	typename KeyInfoT = DenseMapInfo<KeyT>,	typename KeyInfoT = DenseMapInfo<KeyT>,

	typename ValueInfoT = DenseMapInfo<ValueT>, bool IsConst = false>	bool IsConst = false>
	class DenseMapIterator;	class DenseMapIterator;

	template<typename KeyT, typename ValueT,	template<typename KeyT, typename ValueT,

	typename KeyInfoT = DenseMapInfo<KeyT>,	typename KeyInfoT = DenseMapInfo<KeyT> >
	typename ValueInfoT = DenseMapInfo<ValueT> >
	class DenseMap {	class DenseMap {
	typedef std::pair<KeyT, ValueT> BucketT;	typedef std::pair<KeyT, ValueT> BucketT;
	unsigned NumBuckets;	unsigned NumBuckets;
	BucketT *Buckets;	BucketT *Buckets;

	unsigned NumEntries;	unsigned NumEntries;
	unsigned NumTombstones;	unsigned NumTombstones;
	public:	public:
	typedef KeyT key_type;	typedef KeyT key_type;
	typedef ValueT mapped_type;	typedef ValueT mapped_type;

	skipping to change at line 83	skipping to change at line 82
	}	}
	#ifndef NDEBUG	#ifndef NDEBUG
	if (NumBuckets)	if (NumBuckets)
	memset((void)Buckets, 0x5a, sizeof(BucketT)NumBuckets);	memset((void)Buckets, 0x5a, sizeof(BucketT)NumBuckets);
	#endif	#endif
	operator delete(Buckets);	operator delete(Buckets);
	}	}

	typedef DenseMapIterator<KeyT, ValueT, KeyInfoT> iterator;	typedef DenseMapIterator<KeyT, ValueT, KeyInfoT> iterator;
	typedef DenseMapIterator<KeyT, ValueT,	typedef DenseMapIterator<KeyT, ValueT,

	KeyInfoT, ValueInfoT, true> const_iterator;	KeyInfoT, true> const_iterator;
	inline iterator begin() {	inline iterator begin() {
	// When the map is empty, avoid the overhead of AdvancePastEmptyBuckets ().	// When the map is empty, avoid the overhead of AdvancePastEmptyBuckets ().
	return empty() ? end() : iterator(Buckets, Buckets+NumBuckets);	return empty() ? end() : iterator(Buckets, Buckets+NumBuckets);
	}	}
	inline iterator end() {	inline iterator end() {

	return iterator(Buckets+NumBuckets, Buckets+NumBuckets);	return iterator(Buckets+NumBuckets, Buckets+NumBuckets, true);
	}	}
	inline const_iterator begin() const {	inline const_iterator begin() const {
	return empty() ? end() : const_iterator(Buckets, Buckets+NumBuckets);	return empty() ? end() : const_iterator(Buckets, Buckets+NumBuckets);
	}	}
	inline const_iterator end() const {	inline const_iterator end() const {

	return const_iterator(Buckets+NumBuckets, Buckets+NumBuckets);	return const_iterator(Buckets+NumBuckets, Buckets+NumBuckets, true);
	}	}

	bool empty() const { return NumEntries == 0; }	bool empty() const { return NumEntries == 0; }
	unsigned size() const { return NumEntries; }	unsigned size() const { return NumEntries; }

	/// Grow the densemap so that it has at least Size buckets. Does not shri nk	/// Grow the densemap so that it has at least Size buckets. Does not shri nk
	void resize(size_t Size) {	void resize(size_t Size) {
	if (Size > NumBuckets)	if (Size > NumBuckets)
	grow(Size);	grow(Size);
	}	}

	skipping to change at line 140	skipping to change at line 139

	/// count - Return true if the specified key is in the map.	/// count - Return true if the specified key is in the map.
	bool count(const KeyT &Val) const {	bool count(const KeyT &Val) const {
	BucketT *TheBucket;	BucketT *TheBucket;
	return LookupBucketFor(Val, TheBucket);	return LookupBucketFor(Val, TheBucket);
	}	}

	iterator find(const KeyT &Val) {	iterator find(const KeyT &Val) {
	BucketT *TheBucket;	BucketT *TheBucket;
	if (LookupBucketFor(Val, TheBucket))	if (LookupBucketFor(Val, TheBucket))

	return iterator(TheBucket, Buckets+NumBuckets);	return iterator(TheBucket, Buckets+NumBuckets, true);
	return end();	return end();
	}	}
	const_iterator find(const KeyT &Val) const {	const_iterator find(const KeyT &Val) const {
	BucketT *TheBucket;	BucketT *TheBucket;
	if (LookupBucketFor(Val, TheBucket))	if (LookupBucketFor(Val, TheBucket))

	return const_iterator(TheBucket, Buckets+NumBuckets);	return const_iterator(TheBucket, Buckets+NumBuckets, true);
		return end();
		}

		/// Alternate version of find() which allows a different, and possibly
		/// less expensive, key type.
		/// The DenseMapInfo is responsible for supplying methods
		/// getHashValue(LookupKeyT) and isEqual(LookupKeyT, KeyT) for each key
		/// type used.
		template<class LookupKeyT>
		iterator find_as(const LookupKeyT &Val) {
		BucketT *TheBucket;
		if (LookupBucketFor(Val, TheBucket))
		return iterator(TheBucket, Buckets+NumBuckets, true);
		return end();
		}
		template<class LookupKeyT>
		const_iterator find_as(const LookupKeyT &Val) const {
		BucketT *TheBucket;
		if (LookupBucketFor(Val, TheBucket))
		return const_iterator(TheBucket, Buckets+NumBuckets, true);
	return end();	return end();
	}	}

	/// lookup - Return the entry for the specified key, or a default	/// lookup - Return the entry for the specified key, or a default
	/// constructed value if no such entry exists.	/// constructed value if no such entry exists.
	ValueT lookup(const KeyT &Val) const {	ValueT lookup(const KeyT &Val) const {
	BucketT *TheBucket;	BucketT *TheBucket;
	if (LookupBucketFor(Val, TheBucket))	if (LookupBucketFor(Val, TheBucket))
	return TheBucket->second;	return TheBucket->second;
	return ValueT();	return ValueT();
	}	}

	// Inserts key,value pair into the map if the key isn't already in the ma p.	// Inserts key,value pair into the map if the key isn't already in the ma p.
	// If the key is already in the map, it returns false and doesn't update the	// If the key is already in the map, it returns false and doesn't update the
	// value.	// value.
	std::pair<iterator, bool> insert(const std::pair<KeyT, ValueT> &KV) {	std::pair<iterator, bool> insert(const std::pair<KeyT, ValueT> &KV) {
	BucketT *TheBucket;	BucketT *TheBucket;
	if (LookupBucketFor(KV.first, TheBucket))	if (LookupBucketFor(KV.first, TheBucket))

	return std::make_pair(iterator(TheBucket, Buckets+NumBuckets),	return std::make_pair(iterator(TheBucket, Buckets+NumBuckets, true),
	false); // Already in map.	false); // Already in map.

	// Otherwise, insert the new element.	// Otherwise, insert the new element.
	TheBucket = InsertIntoBucket(KV.first, KV.second, TheBucket);	TheBucket = InsertIntoBucket(KV.first, KV.second, TheBucket);

	return std::make_pair(iterator(TheBucket, Buckets+NumBuckets),	return std::make_pair(iterator(TheBucket, Buckets+NumBuckets, true), tr
	true);	ue);
	}	}

	/// insert - Range insertion of pairs.	/// insert - Range insertion of pairs.
	template<typename InputIt>	template<typename InputIt>
	void insert(InputIt I, InputIt E) {	void insert(InputIt I, InputIt E) {
	for (; I != E; ++I)	for (; I != E; ++I)
	insert(*I);	insert(*I);
	}	}

	bool erase(const KeyT &Val) {	bool erase(const KeyT &Val) {

	skipping to change at line 239	skipping to change at line 257
	}	}

	/// getPointerIntoBucketsArray() - Return an opaque pointer into the buck ets	/// getPointerIntoBucketsArray() - Return an opaque pointer into the buck ets
	/// array. In conjunction with the previous method, this can be used to	/// array. In conjunction with the previous method, this can be used to
	/// determine whether an insertion caused the DenseMap to reallocate.	/// determine whether an insertion caused the DenseMap to reallocate.
	const void *getPointerIntoBucketsArray() const { return Buckets; }	const void *getPointerIntoBucketsArray() const { return Buckets; }

	private:	private:
	void CopyFrom(const DenseMap& other) {	void CopyFrom(const DenseMap& other) {
	if (NumBuckets != 0 &&	if (NumBuckets != 0 &&

	(!isPodLike<KeyInfoT>::value \|\| !isPodLike<ValueInfoT>::value)) {	(!isPodLike<KeyT>::value \|\| !isPodLike<ValueT>::value)) {
	const KeyT EmptyKey = getEmptyKey(), TombstoneKey = getTombstoneKey() ;	const KeyT EmptyKey = getEmptyKey(), TombstoneKey = getTombstoneKey() ;
	for (BucketT P = Buckets, E = Buckets+NumBuckets; P != E; ++P) {	for (BucketT P = Buckets, E = Buckets+NumBuckets; P != E; ++P) {
	if (!KeyInfoT::isEqual(P->first, EmptyKey) &&	if (!KeyInfoT::isEqual(P->first, EmptyKey) &&
	!KeyInfoT::isEqual(P->first, TombstoneKey))	!KeyInfoT::isEqual(P->first, TombstoneKey))
	P->second.~ValueT();	P->second.~ValueT();
	P->first.~KeyT();	P->first.~KeyT();
	}	}
	}	}

	NumEntries = other.NumEntries;	NumEntries = other.NumEntries;

	skipping to change at line 268	skipping to change at line 286

	NumBuckets = other.NumBuckets;	NumBuckets = other.NumBuckets;

	if (NumBuckets == 0) {	if (NumBuckets == 0) {
	Buckets = 0;	Buckets = 0;
	return;	return;
	}	}

	Buckets = static_cast<BucketT>(operator new(sizeof(BucketT) NumBucke ts));	Buckets = static_cast<BucketT>(operator new(sizeof(BucketT) NumBucke ts));


	if (isPodLike<KeyInfoT>::value && isPodLike<ValueInfoT>::value)	if (isPodLike<KeyT>::value && isPodLike<ValueT>::value)
	memcpy(Buckets, other.Buckets, NumBuckets * sizeof(BucketT));	memcpy(Buckets, other.Buckets, NumBuckets * sizeof(BucketT));
	else	else
	for (size_t i = 0; i < NumBuckets; ++i) {	for (size_t i = 0; i < NumBuckets; ++i) {
	new (&Buckets[i].first) KeyT(other.Buckets[i].first);	new (&Buckets[i].first) KeyT(other.Buckets[i].first);
	if (!KeyInfoT::isEqual(Buckets[i].first, getEmptyKey()) &&	if (!KeyInfoT::isEqual(Buckets[i].first, getEmptyKey()) &&
	!KeyInfoT::isEqual(Buckets[i].first, getTombstoneKey()))	!KeyInfoT::isEqual(Buckets[i].first, getTombstoneKey()))
	new (&Buckets[i].second) ValueT(other.Buckets[i].second);	new (&Buckets[i].second) ValueT(other.Buckets[i].second);
	}	}
	}	}


	skipping to change at line 312	skipping to change at line 330
	--NumTombstones;	--NumTombstones;

	TheBucket->first = Key;	TheBucket->first = Key;
	new (&TheBucket->second) ValueT(Value);	new (&TheBucket->second) ValueT(Value);
	return TheBucket;	return TheBucket;
	}	}

	static unsigned getHashValue(const KeyT &Val) {	static unsigned getHashValue(const KeyT &Val) {
	return KeyInfoT::getHashValue(Val);	return KeyInfoT::getHashValue(Val);
	}	}

		template<typename LookupKeyT>
		static unsigned getHashValue(const LookupKeyT &Val) {
		return KeyInfoT::getHashValue(Val);
		}
	static const KeyT getEmptyKey() {	static const KeyT getEmptyKey() {
	return KeyInfoT::getEmptyKey();	return KeyInfoT::getEmptyKey();
	}	}
	static const KeyT getTombstoneKey() {	static const KeyT getTombstoneKey() {
	return KeyInfoT::getTombstoneKey();	return KeyInfoT::getTombstoneKey();
	}	}

	/// LookupBucketFor - Lookup the appropriate bucket for Val, returning it in	/// LookupBucketFor - Lookup the appropriate bucket for Val, returning it in
	/// FoundBucket. If the bucket contains the key and a value, this return s	/// FoundBucket. If the bucket contains the key and a value, this return s
	/// true, otherwise it returns a bucket with an empty marker or tombstone and	/// true, otherwise it returns a bucket with an empty marker or tombstone and
	/// returns false.	/// returns false.

	bool LookupBucketFor(const KeyT &Val, BucketT *&FoundBucket) const {	template<typename LookupKeyT>
		bool LookupBucketFor(const LookupKeyT &Val, BucketT *&FoundBucket) const
		{
	unsigned BucketNo = getHashValue(Val);	unsigned BucketNo = getHashValue(Val);
	unsigned ProbeAmt = 1;	unsigned ProbeAmt = 1;
	BucketT *BucketsPtr = Buckets;	BucketT *BucketsPtr = Buckets;

	if (NumBuckets == 0) {	if (NumBuckets == 0) {
	FoundBucket = 0;	FoundBucket = 0;
	return false;	return false;
	}	}

	// FoundTombstone - Keep track of whether we find a tombstone while pro bing.	// FoundTombstone - Keep track of whether we find a tombstone while pro bing.
	BucketT *FoundTombstone = 0;	BucketT *FoundTombstone = 0;
	const KeyT EmptyKey = getEmptyKey();	const KeyT EmptyKey = getEmptyKey();
	const KeyT TombstoneKey = getTombstoneKey();	const KeyT TombstoneKey = getTombstoneKey();
	assert(!KeyInfoT::isEqual(Val, EmptyKey) &&	assert(!KeyInfoT::isEqual(Val, EmptyKey) &&
	!KeyInfoT::isEqual(Val, TombstoneKey) &&	!KeyInfoT::isEqual(Val, TombstoneKey) &&
	"Empty/Tombstone value shouldn't be inserted into map!");	"Empty/Tombstone value shouldn't be inserted into map!");

	while (1) {	while (1) {
	BucketT *ThisBucket = BucketsPtr + (BucketNo & (NumBuckets-1));	BucketT *ThisBucket = BucketsPtr + (BucketNo & (NumBuckets-1));
	// Found Val's bucket? If so, return it.	// Found Val's bucket? If so, return it.

	if (KeyInfoT::isEqual(ThisBucket->first, Val)) {	if (KeyInfoT::isEqual(Val, ThisBucket->first)) {
	FoundBucket = ThisBucket;	FoundBucket = ThisBucket;
	return true;	return true;
	}	}

	// If we found an empty bucket, the key doesn't exist in the set.	// If we found an empty bucket, the key doesn't exist in the set.
	// Insert it and return the default value.	// Insert it and return the default value.
	if (KeyInfoT::isEqual(ThisBucket->first, EmptyKey)) {	if (KeyInfoT::isEqual(ThisBucket->first, EmptyKey)) {
	// If we've already seen a tombstone while probing, fill it in inst ead	// If we've already seen a tombstone while probing, fill it in inst ead
	// of the empty bucket we eventually probed to.	// of the empty bucket we eventually probed to.
	if (FoundTombstone) ThisBucket = FoundTombstone;	if (FoundTombstone) ThisBucket = FoundTombstone;

	skipping to change at line 480	skipping to change at line 503
	/// Return the approximate size (in bytes) of the actual map.	/// Return the approximate size (in bytes) of the actual map.
	/// This is just the raw memory used by DenseMap.	/// This is just the raw memory used by DenseMap.
	/// If entries are pointers to objects, the size of the referenced object s	/// If entries are pointers to objects, the size of the referenced object s
	/// are not included.	/// are not included.
	size_t getMemorySize() const {	size_t getMemorySize() const {
	return NumBuckets * sizeof(BucketT);	return NumBuckets * sizeof(BucketT);
	}	}
	};	};

	template<typename KeyT, typename ValueT,	template<typename KeyT, typename ValueT,

	typename KeyInfoT, typename ValueInfoT, bool IsConst>	typename KeyInfoT, bool IsConst>
	class DenseMapIterator {	class DenseMapIterator {
	typedef std::pair<KeyT, ValueT> Bucket;	typedef std::pair<KeyT, ValueT> Bucket;
	typedef DenseMapIterator<KeyT, ValueT,	typedef DenseMapIterator<KeyT, ValueT,

	KeyInfoT, ValueInfoT, true> ConstIterator;	KeyInfoT, true> ConstIterator;
	friend class DenseMapIterator<KeyT, ValueT, KeyInfoT, ValueInfoT, true>;	friend class DenseMapIterator<KeyT, ValueT, KeyInfoT, true>;
	public:	public:
	typedef ptrdiff_t difference_type;	typedef ptrdiff_t difference_type;
	typedef typename conditional<IsConst, const Bucket, Bucket>::type value_t ype;	typedef typename conditional<IsConst, const Bucket, Bucket>::type value_t ype;
	typedef value_type *pointer;	typedef value_type *pointer;
	typedef value_type &reference;	typedef value_type &reference;
	typedef std::forward_iterator_tag iterator_category;	typedef std::forward_iterator_tag iterator_category;
	private:	private:
	pointer Ptr, End;	pointer Ptr, End;
	public:	public:
	DenseMapIterator() : Ptr(0), End(0) {}	DenseMapIterator() : Ptr(0), End(0) {}


	DenseMapIterator(pointer Pos, pointer E) : Ptr(Pos), End(E) {	DenseMapIterator(pointer Pos, pointer E, bool NoAdvance = false)
	AdvancePastEmptyBuckets();	: Ptr(Pos), End(E) {
		if (!NoAdvance) AdvancePastEmptyBuckets();
	}	}

	// If IsConst is true this is a converting constructor from iterator to	// If IsConst is true this is a converting constructor from iterator to
	// const_iterator and the default copy constructor is used.	// const_iterator and the default copy constructor is used.
	// Otherwise this is a copy constructor for iterator.	// Otherwise this is a copy constructor for iterator.
	DenseMapIterator(const DenseMapIterator<KeyT, ValueT,	DenseMapIterator(const DenseMapIterator<KeyT, ValueT,

	KeyInfoT, ValueInfoT, false>& I)	KeyInfoT, false>& I)
	: Ptr(I.Ptr), End(I.End) {}	: Ptr(I.Ptr), End(I.End) {}

	reference operator*() const {	reference operator*() const {
	return *Ptr;	return *Ptr;
	}	}
	pointer operator->() const {	pointer operator->() const {
	return Ptr;	return Ptr;
	}	}

	bool operator==(const ConstIterator &RHS) const {	bool operator==(const ConstIterator &RHS) const {

	skipping to change at line 543	skipping to change at line 567
	const KeyT Empty = KeyInfoT::getEmptyKey();	const KeyT Empty = KeyInfoT::getEmptyKey();
	const KeyT Tombstone = KeyInfoT::getTombstoneKey();	const KeyT Tombstone = KeyInfoT::getTombstoneKey();

	while (Ptr != End &&	while (Ptr != End &&
	(KeyInfoT::isEqual(Ptr->first, Empty) \|\|	(KeyInfoT::isEqual(Ptr->first, Empty) \|\|
	KeyInfoT::isEqual(Ptr->first, Tombstone)))	KeyInfoT::isEqual(Ptr->first, Tombstone)))
	++Ptr;	++Ptr;
	}	}
	};	};


	template<typename KeyT, typename ValueT, typename KeyInfoT, typename ValueI nfoT>	template<typename KeyT, typename ValueT, typename KeyInfoT>
	static inline size_t	static inline size_t

	capacity_in_bytes(const DenseMap<KeyT, ValueT, KeyInfoT, ValueInfoT> &X) {	capacity_in_bytes(const DenseMap<KeyT, ValueT, KeyInfoT> &X) {
	return X.getMemorySize();	return X.getMemorySize();
	}	}

	} // end namespace llvm	} // end namespace llvm

	#endif	#endif

End of changes. 20 change blocks.
	23 lines changed or deleted	49 lines changed or added

	DominanceFrontier.h	DominanceFrontier.h

	skipping to change at line 156	skipping to change at line 156

	/// dump - Dump the dominance frontier to dbgs().	/// dump - Dump the dominance frontier to dbgs().
	void dump() const;	void dump() const;
	};	};

	//===-------------------------------------	//===-------------------------------------
	/// DominanceFrontier Class - Concrete subclass of DominanceFrontierBase th at is	/// DominanceFrontier Class - Concrete subclass of DominanceFrontierBase th at is
	/// used to compute a forward dominator frontiers.	/// used to compute a forward dominator frontiers.
	///	///
	class DominanceFrontier : public DominanceFrontierBase {	class DominanceFrontier : public DominanceFrontierBase {

		virtual void anchor();
	public:	public:
	static char ID; // Pass ID, replacement for typeid	static char ID; // Pass ID, replacement for typeid
	DominanceFrontier() :	DominanceFrontier() :
	DominanceFrontierBase(ID, false) {	DominanceFrontierBase(ID, false) {
	initializeDominanceFrontierPass(*PassRegistry::getPassRegistry());	initializeDominanceFrontierPass(*PassRegistry::getPassRegistry());
	}	}

	BasicBlock *getRoot() const {	BasicBlock *getRoot() const {
	assert(Roots.size() == 1 && "Should always have entry node!");	assert(Roots.size() == 1 && "Should always have entry node!");
	return Roots[0];	return Roots[0];

End of changes. 1 change blocks.
	0 lines changed or deleted	1 lines changed or added

	Dominators.h	Dominators.h

	skipping to change at line 187	skipping to change at line 187
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	/// DominatorTree - Calculate the immediate dominator tree for a function.	/// DominatorTree - Calculate the immediate dominator tree for a function.
	///	///

	template<class FuncT, class N>	template<class FuncT, class N>
	void Calculate(DominatorTreeBase<typename GraphTraits<N>::NodeType>& DT,	void Calculate(DominatorTreeBase<typename GraphTraits<N>::NodeType>& DT,
	FuncT& F);	FuncT& F);

	template<class NodeT>	template<class NodeT>
	class DominatorTreeBase : public DominatorBase<NodeT> {	class DominatorTreeBase : public DominatorBase<NodeT> {

		bool dominatedBySlowTreeWalk(const DomTreeNodeBase<NodeT> *A,
		const DomTreeNodeBase<NodeT> *B) const {
		assert(A != B);
		assert(isReachableFromEntry(B));
		assert(isReachableFromEntry(A));

		const DomTreeNodeBase<NodeT> *IDom;
		while ((IDom = B->getIDom()) != 0 && IDom != A && IDom != B)
		B = IDom; // Walk up the tree
		return IDom != 0;
		}

	protected:	protected:
	typedef DenseMap<NodeT, DomTreeNodeBase<NodeT>> DomTreeNodeMapType;	typedef DenseMap<NodeT, DomTreeNodeBase<NodeT>> DomTreeNodeMapType;
	DomTreeNodeMapType DomTreeNodes;	DomTreeNodeMapType DomTreeNodes;
	DomTreeNodeBase<NodeT> *RootNode;	DomTreeNodeBase<NodeT> *RootNode;

	bool DFSInfoValid;	bool DFSInfoValid;
	unsigned int SlowQueries;	unsigned int SlowQueries;
	// Information record used during immediate dominators computation.	// Information record used during immediate dominators computation.
	struct InfoRec {	struct InfoRec {
	unsigned DFSNum;	unsigned DFSNum;

	skipping to change at line 323	skipping to change at line 335

	return false;	return false;
	}	}

	virtual void releaseMemory() { reset(); }	virtual void releaseMemory() { reset(); }

	/// getNode - return the (Post)DominatorTree node for the specified basic	/// getNode - return the (Post)DominatorTree node for the specified basic
	/// block. This is the same as using operator[] on this class.	/// block. This is the same as using operator[] on this class.
	///	///
	inline DomTreeNodeBase<NodeT> getNode(NodeT BB) const {	inline DomTreeNodeBase<NodeT> getNode(NodeT BB) const {

	typename DomTreeNodeMapType::const_iterator I = DomTreeNodes.find(BB);	return DomTreeNodes.lookup(BB);
	return I != DomTreeNodes.end() ? I->second : 0;
	}	}

	/// getRootNode - This returns the entry node for the CFG of the function . If	/// getRootNode - This returns the entry node for the CFG of the function . If
	/// this tree represents the post-dominance relations for a function, how ever,	/// this tree represents the post-dominance relations for a function, how ever,
	/// this root may be a node with the block == NULL. This is the case whe n	/// this root may be a node with the block == NULL. This is the case whe n
	/// there are multiple exit nodes from a particular function. Consumers of	/// there are multiple exit nodes from a particular function. Consumers of
	/// post-dominance information must be capable of dealing with this	/// post-dominance information must be capable of dealing with this
	/// possibility.	/// possibility.
	///	///
	DomTreeNodeBase<NodeT> *getRootNode() { return RootNode; }	DomTreeNodeBase<NodeT> *getRootNode() { return RootNode; }
	const DomTreeNodeBase<NodeT> *getRootNode() const { return RootNode; }	const DomTreeNodeBase<NodeT> *getRootNode() const { return RootNode; }

	/// properlyDominates - Returns true iff this dominates N and this != N.	/// properlyDominates - Returns true iff this dominates N and this != N.
	/// Note that this is not a constant time operation!	/// Note that this is not a constant time operation!
	///	///
	bool properlyDominates(const DomTreeNodeBase<NodeT> *A,	bool properlyDominates(const DomTreeNodeBase<NodeT> *A,

	const DomTreeNodeBase<NodeT> *B) const {	const DomTreeNodeBase<NodeT> *B) {
	if (A == 0 \|\| B == 0) return false;	if (A == 0 \|\| B == 0)
	return dominatedBySlowTreeWalk(A, B);	return false;
	}

	inline bool properlyDominates(const NodeT A, const NodeT B) {
	if (A == B)	if (A == B)
	return false;	return false;

		return dominates(A, B);
	// Cast away the const qualifiers here. This is ok since
	// this function doesn't actually return the values returned
	// from getNode.
	return properlyDominates(getNode(const_cast<NodeT *>(A)),
	getNode(const_cast<NodeT *>(B)));
	}	}


	bool dominatedBySlowTreeWalk(const DomTreeNodeBase<NodeT> *A,	bool properlyDominates(const NodeT A, const NodeT B);
	const DomTreeNodeBase<NodeT> *B) const {
	const DomTreeNodeBase<NodeT> *IDom;
	if (A == 0 \|\| B == 0) return false;
	while ((IDom = B->getIDom()) != 0 && IDom != A && IDom != B)
	B = IDom; // Walk up the tree
	return IDom != 0;
	}

	/// isReachableFromEntry - Return true if A is dominated by the entry	/// isReachableFromEntry - Return true if A is dominated by the entry
	/// block of the function containing it.	/// block of the function containing it.

	bool isReachableFromEntry(const NodeT* A) {	bool isReachableFromEntry(const NodeT* A) const {
	assert(!this->isPostDominator() &&	assert(!this->isPostDominator() &&
	"This is not implemented for post dominators");	"This is not implemented for post dominators");

	return dominates(&A->getParent()->front(), A);	return isReachableFromEntry(getNode(const_cast<NodeT *>(A)));
		}

		inline bool isReachableFromEntry(const DomTreeNodeBase<NodeT> *A) const {
		return A;
	}	}

	/// dominates - Returns true iff A dominates B. Note that this is not a	/// dominates - Returns true iff A dominates B. Note that this is not a
	/// constant time operation!	/// constant time operation!
	///	///
	inline bool dominates(const DomTreeNodeBase<NodeT> *A,	inline bool dominates(const DomTreeNodeBase<NodeT> *A,
	const DomTreeNodeBase<NodeT> *B) {	const DomTreeNodeBase<NodeT> *B) {

		// A node trivially dominates itself.
	if (B == A)	if (B == A)

	return true; // A node trivially dominates itself.	return true;


	if (A == 0 \|\| B == 0)	// An unreachable node is dominated by anything.
		if (!isReachableFromEntry(B))
		return true;

		// And dominates nothing.
		if (!isReachableFromEntry(A))
	return false;	return false;

	// Compare the result of the tree walk and the dfs numbers, if expensiv e	// Compare the result of the tree walk and the dfs numbers, if expensiv e
	// checks are enabled.	// checks are enabled.
	#ifdef XDEBUG	#ifdef XDEBUG
	assert((!DFSInfoValid \|\|	assert((!DFSInfoValid \|\|
	(dominatedBySlowTreeWalk(A, B) == B->DominatedBy(A))) &&	(dominatedBySlowTreeWalk(A, B) == B->DominatedBy(A))) &&
	"Tree walk disagrees with dfs numbers!");	"Tree walk disagrees with dfs numbers!");
	#endif	#endif


	skipping to change at line 407	skipping to change at line 413
	// DFS numbers on the theory that we are going to keep querying.	// DFS numbers on the theory that we are going to keep querying.
	SlowQueries++;	SlowQueries++;
	if (SlowQueries > 32) {	if (SlowQueries > 32) {
	updateDFSNumbers();	updateDFSNumbers();
	return B->DominatedBy(A);	return B->DominatedBy(A);
	}	}

	return dominatedBySlowTreeWalk(A, B);	return dominatedBySlowTreeWalk(A, B);
	}	}


	inline bool dominates(const NodeT A, const NodeT B) {	bool dominates(const NodeT A, const NodeT B);
	if (A == B)
	return true;

	// Cast away the const qualifiers here. This is ok since
	// this function doesn't actually return the values returned
	// from getNode.
	return dominates(getNode(const_cast<NodeT *>(A)),
	getNode(const_cast<NodeT *>(B)));
	}

	NodeT *getRoot() const {	NodeT *getRoot() const {
	assert(this->Roots.size() == 1 && "Should always have entry node!");	assert(this->Roots.size() == 1 && "Should always have entry node!");
	return this->Roots[0];	return this->Roots[0];
	}	}

	/// findNearestCommonDominator - Find nearest common dominator basic bloc k	/// findNearestCommonDominator - Find nearest common dominator basic bloc k
	/// for basic block A and B. If there is no such block then return NULL.	/// for basic block A and B. If there is no such block then return NULL.
	NodeT findNearestCommonDominator(NodeT A, NodeT *B) {	NodeT findNearestCommonDominator(NodeT A, NodeT *B) {
	assert(A->getParent() == B->getParent() &&	assert(A->getParent() == B->getParent() &&

	skipping to change at line 624	skipping to change at line 621
	WorkStack.push_back(std::make_pair(Child, Child->begin()));	WorkStack.push_back(std::make_pair(Child, Child->begin()));
	Child->DFSNumIn = DFSNum++;	Child->DFSNumIn = DFSNum++;
	}	}
	}	}

	SlowQueries = 0;	SlowQueries = 0;
	DFSInfoValid = true;	DFSInfoValid = true;
	}	}

	DomTreeNodeBase<NodeT> getNodeForBlock(NodeT BB) {	DomTreeNodeBase<NodeT> getNodeForBlock(NodeT BB) {

	typename DomTreeNodeMapType::iterator I = this->DomTreeNodes.find(BB);	if (DomTreeNodeBase<NodeT> *Node = getNode(BB))
	if (I != this->DomTreeNodes.end() && I->second)	return Node;
	return I->second;

	// Haven't calculated this node yet? Get or calculate the node for the	// Haven't calculated this node yet? Get or calculate the node for the
	// immediate dominator.	// immediate dominator.
	NodeT *IDom = getIDom(BB);	NodeT *IDom = getIDom(BB);

	assert(IDom \|\| this->DomTreeNodes[NULL]);	assert(IDom \|\| this->DomTreeNodes[NULL]);
	DomTreeNodeBase<NodeT> *IDomNode = getNodeForBlock(IDom);	DomTreeNodeBase<NodeT> *IDomNode = getNodeForBlock(IDom);

	// Add a new tree node for this BasicBlock, and link it as a child of	// Add a new tree node for this BasicBlock, and link it as a child of
	// IDomNode	// IDomNode
	DomTreeNodeBase<NodeT> *C = new DomTreeNodeBase<NodeT>(BB, IDomNode);	DomTreeNodeBase<NodeT> *C = new DomTreeNodeBase<NodeT>(BB, IDomNode);
	return this->DomTreeNodes[BB] = IDomNode->addChild(C);	return this->DomTreeNodes[BB] = IDomNode->addChild(C);
	}	}

	inline NodeT getIDom(NodeT BB) const {	inline NodeT getIDom(NodeT BB) const {

	typename DenseMap<NodeT, NodeT>::const_iterator I = IDoms.find(BB);	return IDoms.lookup(BB);
	return I != IDoms.end() ? I->second : 0;
	}	}

	inline void addRoot(NodeT* BB) {	inline void addRoot(NodeT* BB) {
	this->Roots.push_back(BB);	this->Roots.push_back(BB);
	}	}

	public:	public:
	/// recalculate - compute a dominator tree for the given function	/// recalculate - compute a dominator tree for the given function
	template<class FT>	template<class FT>
	void recalculate(FT& F) {	void recalculate(FT& F) {

		typedef GraphTraits<FT*> TraitsTy;
	reset();	reset();
	this->Vertex.push_back(0);	this->Vertex.push_back(0);

	if (!this->IsPostDominators) {	if (!this->IsPostDominators) {
	// Initialize root	// Initialize root

	this->Roots.push_back(&F.front());	NodeT *entry = TraitsTy::getEntryNode(&F);
	this->IDoms[&F.front()] = 0;	this->Roots.push_back(entry);
	this->DomTreeNodes[&F.front()] = 0;	this->IDoms[entry] = 0;
		this->DomTreeNodes[entry] = 0;

	Calculate<FT, NodeT>(this, F);	Calculate<FT, NodeT>(this, F);
	} else {	} else {
	// Initialize the roots list	// Initialize the roots list

	for (typename FT::iterator I = F.begin(), E = F.end(); I != E; ++I) {	for (typename TraitsTy::nodes_iterator I = TraitsTy::nodes_begin(&F),
	if (std::distance(GraphTraits<FT*>::child_begin(I),	E = TraitsTy::nodes_end(&F); I != E
	GraphTraits<FT*>::child_end(I)) == 0)	; ++I) {
		if (std::distance(TraitsTy::child_begin(I),
		TraitsTy::child_end(I)) == 0)
	addRoot(I);	addRoot(I);

	// Prepopulate maps so that we don't get iterator invalidation issu es later.	// Prepopulate maps so that we don't get iterator invalidation issu es later.
	this->IDoms[I] = 0;	this->IDoms[I] = 0;
	this->DomTreeNodes[I] = 0;	this->DomTreeNodes[I] = 0;
	}	}

	Calculate<FT, Inverse<NodeT> >(this, F);	Calculate<FT, Inverse<NodeT> >(this, F);
	}	}
	}	}
	};	};


		// These two functions are declared out of line as a workaround for buildin
		g
		// with old (< r147295) versions of clang because of pr11642.
		template<class NodeT>
		bool DominatorTreeBase<NodeT>::dominates(const NodeT A, const NodeT B) {
		if (A == B)
		return true;

		// Cast away the const qualifiers here. This is ok since
		// this function doesn't actually return the values returned
		// from getNode.
		return dominates(getNode(const_cast<NodeT *>(A)),
		getNode(const_cast<NodeT *>(B)));
		}
		template<class NodeT>
		bool
		DominatorTreeBase<NodeT>::properlyDominates(const NodeT A, const NodeT B)
		{
		if (A == B)
		return false;

		// Cast away the const qualifiers here. This is ok since
		// this function doesn't actually return the values returned
		// from getNode.
		return dominates(getNode(const_cast<NodeT *>(A)),
		getNode(const_cast<NodeT *>(B)));
		}

	EXTERN_TEMPLATE_INSTANTIATION(class DominatorTreeBase<BasicBlock>);	EXTERN_TEMPLATE_INSTANTIATION(class DominatorTreeBase<BasicBlock>);

	//===-------------------------------------	//===-------------------------------------
	/// DominatorTree Class - Concrete subclass of DominatorTreeBase that is us ed to	/// DominatorTree Class - Concrete subclass of DominatorTreeBase that is us ed to
	/// compute a normal dominator tree.	/// compute a normal dominator tree.
	///	///
	class DominatorTree : public FunctionPass {	class DominatorTree : public FunctionPass {
	public:	public:
	static char ID; // Pass ID, replacement for typeid	static char ID; // Pass ID, replacement for typeid
	DominatorTreeBase<BasicBlock>* DT;	DominatorTreeBase<BasicBlock>* DT;

	skipping to change at line 750	skipping to change at line 774
	}	}

	inline bool dominates(const DomTreeNode* A, const DomTreeNode* B) const {	inline bool dominates(const DomTreeNode* A, const DomTreeNode* B) const {
	return DT->dominates(A, B);	return DT->dominates(A, B);
	}	}

	inline bool dominates(const BasicBlock* A, const BasicBlock* B) const {	inline bool dominates(const BasicBlock* A, const BasicBlock* B) const {
	return DT->dominates(A, B);	return DT->dominates(A, B);
	}	}


	// dominates - Return true if A dominates B. This performs the	// dominates - Return true if Def dominates a use in User. This performs
	// special checks necessary if A and B are in the same basic block.	// the special checks necessary if Def and User are in the same basic blo
	bool dominates(const Instruction A, const Instruction B) const;	ck.
		// Note that Def doesn't dominate a use in Def itself!
		bool dominates(const Instruction *Def, const Use &U) const;
		bool dominates(const Instruction Def, const Instruction User) const;
		bool dominates(const Instruction Def, const BasicBlock BB) const;

	bool properlyDominates(const DomTreeNode A, const DomTreeNode B) const {	bool properlyDominates(const DomTreeNode A, const DomTreeNode B) const {
	return DT->properlyDominates(A, B);	return DT->properlyDominates(A, B);
	}	}

	bool properlyDominates(const BasicBlock A, const BasicBlock B) const {	bool properlyDominates(const BasicBlock A, const BasicBlock B) const {
	return DT->properlyDominates(A, B);	return DT->properlyDominates(A, B);
	}	}

	/// findNearestCommonDominator - Find nearest common dominator basic bloc k	/// findNearestCommonDominator - Find nearest common dominator basic bloc k

	skipping to change at line 815	skipping to change at line 842
	inline void eraseNode(BasicBlock *BB) {	inline void eraseNode(BasicBlock *BB) {
	DT->eraseNode(BB);	DT->eraseNode(BB);
	}	}

	/// splitBlock - BB is split and now it has one successor. Update dominat or	/// splitBlock - BB is split and now it has one successor. Update dominat or
	/// tree to reflect this change.	/// tree to reflect this change.
	inline void splitBlock(BasicBlock* NewBB) {	inline void splitBlock(BasicBlock* NewBB) {
	DT->splitBlock(NewBB);	DT->splitBlock(NewBB);
	}	}


	bool isReachableFromEntry(const BasicBlock* A) {	bool isReachableFromEntry(const BasicBlock* A) const {
	return DT->isReachableFromEntry(A);	return DT->isReachableFromEntry(A);
	}	}


		bool isReachableFromEntry(const Use &U) const;

	virtual void releaseMemory() {	virtual void releaseMemory() {
	DT->releaseMemory();	DT->releaseMemory();
	}	}

	virtual void print(raw_ostream &OS, const Module* M= 0) const;	virtual void print(raw_ostream &OS, const Module* M= 0) const;
	};	};

	//===-------------------------------------	//===-------------------------------------
	/// DominatorTree GraphTraits specialization so the DominatorTree can be	/// DominatorTree GraphTraits specialization so the DominatorTree can be
	/// iterable by generic graph iterators.	/// iterable by generic graph iterators.

End of changes. 20 change blocks.
	51 lines changed or deleted	84 lines changed or added

	Dwarf.h	Dwarf.h

	skipping to change at line 25	skipping to change at line 25

	#ifndef LLVM_SUPPORT_DWARF_H	#ifndef LLVM_SUPPORT_DWARF_H
	#define LLVM_SUPPORT_DWARF_H	#define LLVM_SUPPORT_DWARF_H

	namespace llvm {	namespace llvm {

	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	// Debug info constants.	// Debug info constants.

	enum {	enum {

	LLVMDebugVersion = (11 << 16), // Current version of debug informa	LLVMDebugVersion = (12 << 16), // Current version of debug informa
	tion.	tion.
		LLVMDebugVersion11 = (11 << 16), // Constant for version 11.
	LLVMDebugVersion10 = (10 << 16), // Constant for version 10.	LLVMDebugVersion10 = (10 << 16), // Constant for version 10.
	LLVMDebugVersion9 = (9 << 16), // Constant for version 9.	LLVMDebugVersion9 = (9 << 16), // Constant for version 9.
	LLVMDebugVersion8 = (8 << 16), // Constant for version 8.	LLVMDebugVersion8 = (8 << 16), // Constant for version 8.
	LLVMDebugVersion7 = (7 << 16), // Constant for version 7.	LLVMDebugVersion7 = (7 << 16), // Constant for version 7.
	LLVMDebugVersion6 = (6 << 16), // Constant for version 6.	LLVMDebugVersion6 = (6 << 16), // Constant for version 6.
	LLVMDebugVersion5 = (5 << 16), // Constant for version 5.	LLVMDebugVersion5 = (5 << 16), // Constant for version 5.
	LLVMDebugVersion4 = (4 << 16), // Constant for version 4.	LLVMDebugVersion4 = (4 << 16), // Constant for version 4.
	LLVMDebugVersionMask = 0xffff0000 // Mask for version number.	LLVMDebugVersionMask = 0xffff0000 // Mask for version number.
	};	};


	skipping to change at line 133	skipping to change at line 134
	DW_TAG_rvalue_reference_type = 0x42,	DW_TAG_rvalue_reference_type = 0x42,
	DW_TAG_template_alias = 0x43,	DW_TAG_template_alias = 0x43,
	DW_TAG_MIPS_loop = 0x4081,	DW_TAG_MIPS_loop = 0x4081,
	DW_TAG_format_label = 0x4101,	DW_TAG_format_label = 0x4101,
	DW_TAG_function_template = 0x4102,	DW_TAG_function_template = 0x4102,
	DW_TAG_class_template = 0x4103,	DW_TAG_class_template = 0x4103,
	DW_TAG_GNU_template_template_param = 0x4106,	DW_TAG_GNU_template_template_param = 0x4106,
	DW_TAG_GNU_template_parameter_pack = 0x4107,	DW_TAG_GNU_template_parameter_pack = 0x4107,
	DW_TAG_GNU_formal_parameter_pack = 0x4108,	DW_TAG_GNU_formal_parameter_pack = 0x4108,
	DW_TAG_lo_user = 0x4080,	DW_TAG_lo_user = 0x4080,

		DW_TAG_APPLE_property = 0x4200,
	DW_TAG_hi_user = 0xffff,	DW_TAG_hi_user = 0xffff,

	// Children flag	// Children flag
	DW_CHILDREN_no = 0x00,	DW_CHILDREN_no = 0x00,
	DW_CHILDREN_yes = 0x01,	DW_CHILDREN_yes = 0x01,

	// Attributes	// Attributes
	DW_AT_sibling = 0x01,	DW_AT_sibling = 0x01,
	DW_AT_location = 0x02,	DW_AT_location = 0x02,
	DW_AT_name = 0x03,	DW_AT_name = 0x03,

	skipping to change at line 272	skipping to change at line 274
	DW_AT_APPLE_isa = 0x3fe3,	DW_AT_APPLE_isa = 0x3fe3,
	DW_AT_APPLE_block = 0x3fe4,	DW_AT_APPLE_block = 0x3fe4,
	DW_AT_APPLE_major_runtime_vers = 0x3fe5,	DW_AT_APPLE_major_runtime_vers = 0x3fe5,
	DW_AT_APPLE_runtime_class = 0x3fe6,	DW_AT_APPLE_runtime_class = 0x3fe6,
	DW_AT_APPLE_omit_frame_ptr = 0x3fe7,	DW_AT_APPLE_omit_frame_ptr = 0x3fe7,
	DW_AT_APPLE_property_name = 0x3fe8,	DW_AT_APPLE_property_name = 0x3fe8,
	DW_AT_APPLE_property_getter = 0x3fe9,	DW_AT_APPLE_property_getter = 0x3fe9,
	DW_AT_APPLE_property_setter = 0x3fea,	DW_AT_APPLE_property_setter = 0x3fea,
	DW_AT_APPLE_property_attribute = 0x3feb,	DW_AT_APPLE_property_attribute = 0x3feb,
	DW_AT_APPLE_objc_complete_type = 0x3fec,	DW_AT_APPLE_objc_complete_type = 0x3fec,

		DW_AT_APPLE_property = 0x3fed,

	// Attribute form encodings	// Attribute form encodings
	DW_FORM_addr = 0x01,	DW_FORM_addr = 0x01,
	DW_FORM_block2 = 0x03,	DW_FORM_block2 = 0x03,
	DW_FORM_block4 = 0x04,	DW_FORM_block4 = 0x04,
	DW_FORM_data2 = 0x05,	DW_FORM_data2 = 0x05,
	DW_FORM_data4 = 0x06,	DW_FORM_data4 = 0x06,
	DW_FORM_data8 = 0x07,	DW_FORM_data8 = 0x07,
	DW_FORM_string = 0x08,	DW_FORM_string = 0x08,
	DW_FORM_block = 0x09,	DW_FORM_block = 0x09,

	skipping to change at line 529	skipping to change at line 532
	DW_LANG_C99 = 0x000c,	DW_LANG_C99 = 0x000c,
	DW_LANG_Ada95 = 0x000d,	DW_LANG_Ada95 = 0x000d,
	DW_LANG_Fortran95 = 0x000e,	DW_LANG_Fortran95 = 0x000e,
	DW_LANG_PLI = 0x000f,	DW_LANG_PLI = 0x000f,
	DW_LANG_ObjC = 0x0010,	DW_LANG_ObjC = 0x0010,
	DW_LANG_ObjC_plus_plus = 0x0011,	DW_LANG_ObjC_plus_plus = 0x0011,
	DW_LANG_UPC = 0x0012,	DW_LANG_UPC = 0x0012,
	DW_LANG_D = 0x0013,	DW_LANG_D = 0x0013,
	DW_LANG_Python = 0x0014,	DW_LANG_Python = 0x0014,
	DW_LANG_lo_user = 0x8000,	DW_LANG_lo_user = 0x8000,

		DW_LANG_Mips_Assembler = 0x8001,
	DW_LANG_hi_user = 0xffff,	DW_LANG_hi_user = 0xffff,

	// Identifier case codes	// Identifier case codes
	DW_ID_case_sensitive = 0x00,	DW_ID_case_sensitive = 0x00,
	DW_ID_up_case = 0x01,	DW_ID_up_case = 0x01,
	DW_ID_down_case = 0x02,	DW_ID_down_case = 0x02,
	DW_ID_case_insensitive = 0x03,	DW_ID_case_insensitive = 0x03,

	// Calling convention codes	// Calling convention codes
	DW_CC_normal = 0x01,	DW_CC_normal = 0x01,

End of changes. 4 change blocks.
	2 lines changed or deleted	6 lines changed or added

	ELF.h	ELF.h

	//===-- llvm/Support/ELF.h - ELF constants and data structures --- C++ -- ===//	//===- ELF.h - ELF object file implementation -------------------- C++ -- ===//
	//	//
	// The LLVM Compiler Infrastructure	// The LLVM Compiler Infrastructure
	//	//
	// This file is distributed under the University of Illinois Open Source	// This file is distributed under the University of Illinois Open Source
	// License. See LICENSE.TXT for details.	// License. See LICENSE.TXT for details.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	//	//

	// This header contains common, non-processor-specific data structures and	// This file declares the ELFObjectFile template class.
	// constants for the ELF file format.
	//
	// The details of the ELF32 bits in this file are largely based on the Tool
	// Interface Standard (TIS) Executable and Linking Format (ELF) Specificati
	on
	// Version 1.2, May 1995. The ELF64 stuff is based on ELF-64 Object File Fo
	rmat
	// Version 1.5, Draft 2, May 1998 as well as OpenBSD header files.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//


	#ifndef LLVM_SUPPORT_ELF_H	#ifndef LLVM_OBJECT_ELF_H
	#define LLVM_SUPPORT_ELF_H	#define LLVM_OBJECT_ELF_H


	#include "llvm/Support/DataTypes.h"	#include "llvm/ADT/SmallVector.h"
	#include <cstring>	#include "llvm/ADT/StringSwitch.h"
		#include "llvm/ADT/Triple.h"
		#include "llvm/ADT/DenseMap.h"
		#include "llvm/ADT/PointerIntPair.h"
		#include "llvm/Object/ObjectFile.h"
		#include "llvm/Support/Casting.h"
		#include "llvm/Support/ELF.h"
		#include "llvm/Support/Endian.h"
		#include "llvm/Support/ErrorHandling.h"
		#include "llvm/Support/MemoryBuffer.h"
		#include "llvm/Support/raw_ostream.h"
		#include <algorithm>
		#include <limits>
		#include <utility>

	namespace llvm {	namespace llvm {

		namespace object {

		// Subclasses of ELFObjectFile may need this for template instantiation
		inline std::pair<unsigned char, unsigned char>
		getElfArchType(MemoryBuffer *Object) {
		if (Object->getBufferSize() < ELF::EI_NIDENT)
		return std::make_pair((uint8_t)ELF::ELFCLASSNONE,(uint8_t)ELF::ELFDATAN
		ONE);
		return std::make_pair( (uint8_t)Object->getBufferStart()[ELF::EI_CLASS]
		, (uint8_t)Object->getBufferStart()[ELF::EI_DATA]);
		}

		// Templates to choose Elf_Addr and Elf_Off depending on is64Bits.
		template<support::endianness target_endianness>
		struct ELFDataTypeTypedefHelperCommon {
		typedef support::detail::packed_endian_specific_integral
		<uint16_t, target_endianness, support::aligned> Elf_Half;
		typedef support::detail::packed_endian_specific_integral
		<uint32_t, target_endianness, support::aligned> Elf_Word;
		typedef support::detail::packed_endian_specific_integral
		<int32_t, target_endianness, support::aligned> Elf_Sword;
		typedef support::detail::packed_endian_specific_integral
		<uint64_t, target_endianness, support::aligned> Elf_Xword;
		typedef support::detail::packed_endian_specific_integral
		<int64_t, target_endianness, support::aligned> Elf_Sxword;
		};

		template<support::endianness target_endianness, bool is64Bits>
		struct ELFDataTypeTypedefHelper;

		/// ELF 32bit types.
		template<support::endianness target_endianness>
		struct ELFDataTypeTypedefHelper<target_endianness, false>
		: ELFDataTypeTypedefHelperCommon<target_endianness> {
		typedef uint32_t value_type;
		typedef support::detail::packed_endian_specific_integral
		<value_type, target_endianness, support::aligned> Elf_Addr;
		typedef support::detail::packed_endian_specific_integral
		<value_type, target_endianness, support::aligned> Elf_Off;
		};

		/// ELF 64bit types.
		template<support::endianness target_endianness>
		struct ELFDataTypeTypedefHelper<target_endianness, true>
		: ELFDataTypeTypedefHelperCommon<target_endianness>{
		typedef uint64_t value_type;
		typedef support::detail::packed_endian_specific_integral
		<value_type, target_endianness, support::aligned> Elf_Addr;
		typedef support::detail::packed_endian_specific_integral
		<value_type, target_endianness, support::aligned> Elf_Off;
		};

		// I really don't like doing this, but the alternative is copypasta.
		#define LLVM_ELF_IMPORT_TYPES(target_endianness, is64Bits) \
		typedef typename \
		ELFDataTypeTypedefHelper<target_endianness, is64Bits>::Elf_Addr Elf_Addr;
		\
		typedef typename \
		ELFDataTypeTypedefHelper<target_endianness, is64Bits>::Elf_Off Elf_Off; \
		typedef typename \
		ELFDataTypeTypedefHelper<target_endianness, is64Bits>::Elf_Half Elf_Half;
		\
		typedef typename \
		ELFDataTypeTypedefHelper<target_endianness, is64Bits>::Elf_Word Elf_Word;
		\
		typedef typename \
		ELFDataTypeTypedefHelper<target_endianness, is64Bits>::Elf_Sword Elf_Swor
		d; \
		typedef typename \
		ELFDataTypeTypedefHelper<target_endianness, is64Bits>::Elf_Xword Elf_Xwor
		d; \
		typedef typename \
		ELFDataTypeTypedefHelper<target_endianness, is64Bits>::Elf_Sxword Elf_Sxw
		ord;

		// Section header.
		template<support::endianness target_endianness, bool is64Bits>
		struct Elf_Shdr_Base;

		template<support::endianness target_endianness>
		struct Elf_Shdr_Base<target_endianness, false> {
		LLVM_ELF_IMPORT_TYPES(target_endianness, false)
		Elf_Word sh_name; // Section name (index into string table)
		Elf_Word sh_type; // Section type (SHT_*)
		Elf_Word sh_flags; // Section flags (SHF_*)
		Elf_Addr sh_addr; // Address where section is to be loaded
		Elf_Off sh_offset; // File offset of section data, in bytes
		Elf_Word sh_size; // Size of section, in bytes
		Elf_Word sh_link; // Section type-specific header table index link
		Elf_Word sh_info; // Section type-specific extra information
		Elf_Word sh_addralign;// Section address alignment
		Elf_Word sh_entsize; // Size of records contained within the section
		};

		template<support::endianness target_endianness>
		struct Elf_Shdr_Base<target_endianness, true> {
		LLVM_ELF_IMPORT_TYPES(target_endianness, true)
		Elf_Word sh_name; // Section name (index into string table)
		Elf_Word sh_type; // Section type (SHT_*)
		Elf_Xword sh_flags; // Section flags (SHF_*)
		Elf_Addr sh_addr; // Address where section is to be loaded
		Elf_Off sh_offset; // File offset of section data, in bytes
		Elf_Xword sh_size; // Size of section, in bytes
		Elf_Word sh_link; // Section type-specific header table index link
		Elf_Word sh_info; // Section type-specific extra information
		Elf_Xword sh_addralign;// Section address alignment
		Elf_Xword sh_entsize; // Size of records contained within the section
		};

		template<support::endianness target_endianness, bool is64Bits>
		struct Elf_Shdr_Impl : Elf_Shdr_Base<target_endianness, is64Bits> {
		using Elf_Shdr_Base<target_endianness, is64Bits>::sh_entsize;
		using Elf_Shdr_Base<target_endianness, is64Bits>::sh_size;

		/// @brief Get the number of entities this section contains if it has any
		.
		unsigned getEntityCount() const {
		if (sh_entsize == 0)
		return 0;
		return sh_size / sh_entsize;
		}
		};

		template<support::endianness target_endianness, bool is64Bits>
		struct Elf_Sym_Base;


	namespace ELF {	template<support::endianness target_endianness>
		struct Elf_Sym_Base<target_endianness, false> {
		LLVM_ELF_IMPORT_TYPES(target_endianness, false)
		Elf_Word st_name; // Symbol name (index into string table)
		Elf_Addr st_value; // Value or address associated with the symbol
		Elf_Word st_size; // Size of the symbol
		unsigned char st_info; // Symbol's type and binding attributes
		unsigned char st_other; // Must be zero; reserved
		Elf_Half st_shndx; // Which section (header table index) it's define
		d in
		};


	typedef uint32_t Elf32_Addr; // Program address	template<support::endianness target_endianness>
	typedef uint32_t Elf32_Off; // File offset	struct Elf_Sym_Base<target_endianness, true> {
	typedef uint16_t Elf32_Half;	LLVM_ELF_IMPORT_TYPES(target_endianness, true)
	typedef uint32_t Elf32_Word;	Elf_Word st_name; // Symbol name (index into string table)
	typedef int32_t Elf32_Sword;

	typedef uint64_t Elf64_Addr;
	typedef uint64_t Elf64_Off;
	typedef uint16_t Elf64_Half;
	typedef uint32_t Elf64_Word;
	typedef int32_t Elf64_Sword;
	typedef uint64_t Elf64_Xword;
	typedef int64_t Elf64_Sxword;

	// Object file magic string.
	static const char ElfMagic[] = { 0x7f, 'E', 'L', 'F', '\0' };

	// e_ident size and indices.
	enum {
	EI_MAG0 = 0, // File identification index.
	EI_MAG1 = 1, // File identification index.
	EI_MAG2 = 2, // File identification index.
	EI_MAG3 = 3, // File identification index.
	EI_CLASS = 4, // File class.
	EI_DATA = 5, // Data encoding.
	EI_VERSION = 6, // File version.
	EI_OSABI = 7, // OS/ABI identification.
	EI_ABIVERSION = 8, // ABI version.
	EI_PAD = 9, // Start of padding bytes.
	EI_NIDENT = 16 // Number of bytes in e_ident.
	};

	struct Elf32_Ehdr {
	unsigned char e_ident[EI_NIDENT]; // ELF Identification bytes
	Elf32_Half e_type; // Type of file (see ET_* below)
	Elf32_Half e_machine; // Required architecture for this file (see EM
	_*)
	Elf32_Word e_version; // Must be equal to 1
	Elf32_Addr e_entry; // Address to jump to in order to start progra
	m
	Elf32_Off e_phoff; // Program header table's file offset, in byte
	s
	Elf32_Off e_shoff; // Section header table's file offset, in byte
	s
	Elf32_Word e_flags; // Processor-specific flags
	Elf32_Half e_ehsize; // Size of ELF header, in bytes
	Elf32_Half e_phentsize; // Size of an entry in the program header tabl
	e
	Elf32_Half e_phnum; // Number of entries in the program header tab
	le
	Elf32_Half e_shentsize; // Size of an entry in the section header tabl
	e
	Elf32_Half e_shnum; // Number of entries in the section header tab
	le
	Elf32_Half e_shstrndx; // Sect hdr table index of sect name string ta
	ble
	bool checkMagic() const {
	return (memcmp(e_ident, ElfMagic, strlen(ElfMagic))) == 0;
	}
	unsigned char getFileClass() const { return e_ident[EI_CLASS]; }
	unsigned char getDataEncoding() const { return e_ident[EI_DATA]; }
	};

	// 64-bit ELF header. Fields are the same as for ELF32, but with different
	// types (see above).
	struct Elf64_Ehdr {
	unsigned char e_ident[EI_NIDENT];
	Elf64_Half e_type;
	Elf64_Half e_machine;
	Elf64_Word e_version;
	Elf64_Addr e_entry;
	Elf64_Off e_phoff;
	Elf64_Off e_shoff;
	Elf64_Word e_flags;
	Elf64_Half e_ehsize;
	Elf64_Half e_phentsize;
	Elf64_Half e_phnum;
	Elf64_Half e_shentsize;
	Elf64_Half e_shnum;
	Elf64_Half e_shstrndx;
	bool checkMagic() const {
	return (memcmp(e_ident, ElfMagic, strlen(ElfMagic))) == 0;
	}
	unsigned char getFileClass() const { return e_ident[EI_CLASS]; }
	unsigned char getDataEncoding() const { return e_ident[EI_DATA]; }
	};

	// File types
	enum {
	ET_NONE = 0, // No file type
	ET_REL = 1, // Relocatable file
	ET_EXEC = 2, // Executable file
	ET_DYN = 3, // Shared object file
	ET_CORE = 4, // Core file
	ET_LOPROC = 0xff00, // Beginning of processor-specific codes
	ET_HIPROC = 0xffff // Processor-specific
	};

	// Versioning
	enum {
	EV_NONE = 0,
	EV_CURRENT = 1
	};

	// Machine architectures
	enum {
	EM_NONE = 0, // No machine
	EM_M32 = 1, // AT&T WE 32100
	EM_SPARC = 2, // SPARC
	EM_386 = 3, // Intel 386
	EM_68K = 4, // Motorola 68000
	EM_88K = 5, // Motorola 88000
	EM_486 = 6, // Intel 486 (deprecated)
	EM_860 = 7, // Intel 80860
	EM_MIPS = 8, // MIPS R3000
	EM_S370 = 9, // IBM System/370
	EM_MIPS_RS3_LE = 10, // MIPS RS3000 Little-endian
	EM_PARISC = 15, // Hewlett-Packard PA-RISC
	EM_VPP500 = 17, // Fujitsu VPP500
	EM_SPARC32PLUS = 18, // Enhanced instruction set SPARC
	EM_960 = 19, // Intel 80960
	EM_PPC = 20, // PowerPC
	EM_PPC64 = 21, // PowerPC64
	EM_S390 = 22, // IBM System/390
	EM_SPU = 23, // IBM SPU/SPC
	EM_V800 = 36, // NEC V800
	EM_FR20 = 37, // Fujitsu FR20
	EM_RH32 = 38, // TRW RH-32
	EM_RCE = 39, // Motorola RCE
	EM_ARM = 40, // ARM
	EM_ALPHA = 41, // DEC Alpha
	EM_SH = 42, // Hitachi SH
	EM_SPARCV9 = 43, // SPARC V9
	EM_TRICORE = 44, // Siemens TriCore
	EM_ARC = 45, // Argonaut RISC Core
	EM_H8_300 = 46, // Hitachi H8/300
	EM_H8_300H = 47, // Hitachi H8/300H
	EM_H8S = 48, // Hitachi H8S
	EM_H8_500 = 49, // Hitachi H8/500
	EM_IA_64 = 50, // Intel IA-64 processor architecture
	EM_MIPS_X = 51, // Stanford MIPS-X
	EM_COLDFIRE = 52, // Motorola ColdFire
	EM_68HC12 = 53, // Motorola M68HC12
	EM_MMA = 54, // Fujitsu MMA Multimedia Accelerator
	EM_PCP = 55, // Siemens PCP
	EM_NCPU = 56, // Sony nCPU embedded RISC processor
	EM_NDR1 = 57, // Denso NDR1 microprocessor
	EM_STARCORE = 58, // Motorola Star*Core processor
	EM_ME16 = 59, // Toyota ME16 processor
	EM_ST100 = 60, // STMicroelectronics ST100 processor
	EM_TINYJ = 61, // Advanced Logic Corp. TinyJ embedded processor f
	amily
	EM_X86_64 = 62, // AMD x86-64 architecture
	EM_PDSP = 63, // Sony DSP Processor
	EM_PDP10 = 64, // Digital Equipment Corp. PDP-10
	EM_PDP11 = 65, // Digital Equipment Corp. PDP-11
	EM_FX66 = 66, // Siemens FX66 microcontroller
	EM_ST9PLUS = 67, // STMicroelectronics ST9+ 8/16 bit microcontrolle
	r
	EM_ST7 = 68, // STMicroelectronics ST7 8-bit microcontroller
	EM_68HC16 = 69, // Motorola MC68HC16 Microcontroller
	EM_68HC11 = 70, // Motorola MC68HC11 Microcontroller
	EM_68HC08 = 71, // Motorola MC68HC08 Microcontroller
	EM_68HC05 = 72, // Motorola MC68HC05 Microcontroller
	EM_SVX = 73, // Silicon Graphics SVx
	EM_ST19 = 74, // STMicroelectronics ST19 8-bit microcontroller
	EM_VAX = 75, // Digital VAX
	EM_CRIS = 76, // Axis Communications 32-bit embedded processor
	EM_JAVELIN = 77, // Infineon Technologies 32-bit embedded processor
	EM_FIREPATH = 78, // Element 14 64-bit DSP Processor
	EM_ZSP = 79, // LSI Logic 16-bit DSP Processor
	EM_MMIX = 80, // Donald Knuth's educational 64-bit processor
	EM_HUANY = 81, // Harvard University machine-independent object f
	iles
	EM_PRISM = 82, // SiTera Prism
	EM_AVR = 83, // Atmel AVR 8-bit microcontroller
	EM_FR30 = 84, // Fujitsu FR30
	EM_D10V = 85, // Mitsubishi D10V
	EM_D30V = 86, // Mitsubishi D30V
	EM_V850 = 87, // NEC v850
	EM_M32R = 88, // Mitsubishi M32R
	EM_MN10300 = 89, // Matsushita MN10300
	EM_MN10200 = 90, // Matsushita MN10200
	EM_PJ = 91, // picoJava
	EM_OPENRISC = 92, // OpenRISC 32-bit embedded processor
	EM_ARC_COMPACT = 93, // ARC International ARCompact processor (old
	// spelling/synonym: EM_ARC_A5)
	EM_XTENSA = 94, // Tensilica Xtensa Architecture
	EM_VIDEOCORE = 95, // Alphamosaic VideoCore processor
	EM_TMM_GPP = 96, // Thompson Multimedia General Purpose Processor
	EM_NS32K = 97, // National Semiconductor 32000 series
	EM_TPC = 98, // Tenor Network TPC processor
	EM_SNP1K = 99, // Trebia SNP 1000 processor
	EM_ST200 = 100, // STMicroelectronics (www.st.com) ST200
	EM_IP2K = 101, // Ubicom IP2xxx microcontroller family
	EM_MAX = 102, // MAX Processor
	EM_CR = 103, // National Semiconductor CompactRISC microproces
	sor
	EM_F2MC16 = 104, // Fujitsu F2MC16
	EM_MSP430 = 105, // Texas Instruments embedded microcontroller msp
	430
	EM_BLACKFIN = 106, // Analog Devices Blackfin (DSP) processor
	EM_SE_C33 = 107, // S1C33 Family of Seiko Epson processors
	EM_SEP = 108, // Sharp embedded microprocessor
	EM_ARCA = 109, // Arca RISC Microprocessor
	EM_UNICORE = 110, // Microprocessor series from PKU-Unity Ltd. and
	MPRC
	// of Peking University
	EM_EXCESS = 111, // eXcess: 16/32/64-bit configurable embedded CPU
	EM_DXP = 112, // Icera Semiconductor Inc. Deep Execution Proces
	sor
	EM_ALTERA_NIOS2 = 113, // Altera Nios II soft-core processor
	EM_CRX = 114, // National Semiconductor CompactRISC CRX
	EM_XGATE = 115, // Motorola XGATE embedded processor
	EM_C166 = 116, // Infineon C16x/XC16x processor
	EM_M16C = 117, // Renesas M16C series microprocessors
	EM_DSPIC30F = 118, // Microchip Technology dsPIC30F Digital Signal
	// Controller
	EM_CE = 119, // Freescale Communication Engine RISC core
	EM_M32C = 120, // Renesas M32C series microprocessors
	EM_TSK3000 = 131, // Altium TSK3000 core
	EM_RS08 = 132, // Freescale RS08 embedded processor
	EM_SHARC = 133, // Analog Devices SHARC family of 32-bit DSP
	// processors
	EM_ECOG2 = 134, // Cyan Technology eCOG2 microprocessor
	EM_SCORE7 = 135, // Sunplus S+core7 RISC processor
	EM_DSP24 = 136, // New Japan Radio (NJR) 24-bit DSP Processor
	EM_VIDEOCORE3 = 137, // Broadcom VideoCore III processor
	EM_LATTICEMICO32 = 138, // RISC processor for Lattice FPGA architecture
	EM_SE_C17 = 139, // Seiko Epson C17 family
	EM_TI_C6000 = 140, // The Texas Instruments TMS320C6000 DSP family
	EM_TI_C2000 = 141, // The Texas Instruments TMS320C2000 DSP family
	EM_TI_C5500 = 142, // The Texas Instruments TMS320C55x DSP family
	EM_MMDSP_PLUS = 160, // STMicroelectronics 64bit VLIW Data Signal Proc
	essor
	EM_CYPRESS_M8C = 161, // Cypress M8C microprocessor
	EM_R32C = 162, // Renesas R32C series microprocessors
	EM_TRIMEDIA = 163, // NXP Semiconductors TriMedia architecture famil
	y
	EM_QDSP6 = 164, // QUALCOMM DSP6 Processor
	EM_8051 = 165, // Intel 8051 and variants
	EM_STXP7X = 166, // STMicroelectronics STxP7x family of configurab
	le
	// and extensible RISC processors
	EM_NDS32 = 167, // Andes Technology compact code size embedded RI
	SC
	// processor family
	EM_ECOG1 = 168, // Cyan Technology eCOG1X family
	EM_ECOG1X = 168, // Cyan Technology eCOG1X family
	EM_MAXQ30 = 169, // Dallas Semiconductor MAXQ30 Core Micro-control
	lers
	EM_XIMO16 = 170, // New Japan Radio (NJR) 16-bit DSP Processor
	EM_MANIK = 171, // M2000 Reconfigurable RISC Microprocessor
	EM_CRAYNV2 = 172, // Cray Inc. NV2 vector architecture
	EM_RX = 173, // Renesas RX family
	EM_METAG = 174, // Imagination Technologies META processor
	// architecture
	EM_MCST_ELBRUS = 175, // MCST Elbrus general purpose hardware architect
	ure
	EM_ECOG16 = 176, // Cyan Technology eCOG16 family
	EM_CR16 = 177, // National Semiconductor CompactRISC CR16 16-bit
	// microprocessor
	EM_ETPU = 178, // Freescale Extended Time Processing Unit
	EM_SLE9X = 179, // Infineon Technologies SLE9X core
	EM_L10M = 180, // Intel L10M
	EM_K10M = 181, // Intel K10M
	EM_AVR32 = 185, // Atmel Corporation 32-bit microprocessor family
	EM_STM8 = 186, // STMicroeletronics STM8 8-bit microcontroller
	EM_TILE64 = 187, // Tilera TILE64 multicore architecture family
	EM_TILEPRO = 188, // Tilera TILEPro multicore architecture family
	EM_MICROBLAZE = 189, // Xilinx MicroBlaze 32-bit RISC soft processor c
	ore
	EM_CUDA = 190, // NVIDIA CUDA architecture
	EM_TILEGX = 191, // Tilera TILE-Gx multicore architecture family
	EM_CLOUDSHIELD = 192, // CloudShield architecture family
	EM_COREA_1ST = 193, // KIPO-KAIST Core-A 1st generation processor fam
	ily
	EM_COREA_2ND = 194, // KIPO-KAIST Core-A 2nd generation processor fam
	ily
	EM_ARC_COMPACT2 = 195, // Synopsys ARCompact V2
	EM_OPEN8 = 196, // Open8 8-bit RISC soft processor core
	EM_RL78 = 197, // Renesas RL78 family
	EM_VIDEOCORE5 = 198, // Broadcom VideoCore V processor
	EM_78KOR = 199, // Renesas 78KOR family
	EM_56800EX = 200, // Freescale 56800EX Digital Signal Controller (D
	SC)
	EM_MBLAZE = 47787 // Xilinx MicroBlaze
	};

	// Object file classes.
	enum {
	ELFCLASSNONE = 0,
	ELFCLASS32 = 1, // 32-bit object file
	ELFCLASS64 = 2 // 64-bit object file
	};

	// Object file byte orderings.
	enum {
	ELFDATANONE = 0, // Invalid data encoding.
	ELFDATA2LSB = 1, // Little-endian object file
	ELFDATA2MSB = 2 // Big-endian object file
	};

	// OS ABI identification.
	enum {
	ELFOSABI_NONE = 0, // UNIX System V ABI
	ELFOSABI_HPUX = 1, // HP-UX operating system
	ELFOSABI_NETBSD = 2, // NetBSD
	ELFOSABI_LINUX = 3, // GNU/Linux
	ELFOSABI_HURD = 4, // GNU/Hurd
	ELFOSABI_SOLARIS = 6, // Solaris
	ELFOSABI_AIX = 7, // AIX
	ELFOSABI_IRIX = 8, // IRIX
	ELFOSABI_FREEBSD = 9, // FreeBSD
	ELFOSABI_TRU64 = 10, // TRU64 UNIX
	ELFOSABI_MODESTO = 11, // Novell Modesto
	ELFOSABI_OPENBSD = 12, // OpenBSD
	ELFOSABI_OPENVMS = 13, // OpenVMS
	ELFOSABI_NSK = 14, // Hewlett-Packard Non-Stop Kernel
	ELFOSABI_AROS = 15, // AROS
	ELFOSABI_FENIXOS = 16, // FenixOS
	ELFOSABI_C6000_ELFABI = 64, // Bare-metal TMS320C6000
	ELFOSABI_C6000_LINUX = 65, // Linux TMS320C6000
	ELFOSABI_ARM = 97, // ARM
	ELFOSABI_STANDALONE = 255 // Standalone (embedded) application
	};

	// X86_64 relocations.
	enum {
	R_X86_64_NONE = 0,
	R_X86_64_64 = 1,
	R_X86_64_PC32 = 2,
	R_X86_64_GOT32 = 3,
	R_X86_64_PLT32 = 4,
	R_X86_64_COPY = 5,
	R_X86_64_GLOB_DAT = 6,
	R_X86_64_JUMP_SLOT = 7,
	R_X86_64_RELATIVE = 8,
	R_X86_64_GOTPCREL = 9,
	R_X86_64_32 = 10,
	R_X86_64_32S = 11,
	R_X86_64_16 = 12,
	R_X86_64_PC16 = 13,
	R_X86_64_8 = 14,
	R_X86_64_PC8 = 15,
	R_X86_64_DTPMOD64 = 16,
	R_X86_64_DTPOFF64 = 17,
	R_X86_64_TPOFF64 = 18,
	R_X86_64_TLSGD = 19,
	R_X86_64_TLSLD = 20,
	R_X86_64_DTPOFF32 = 21,
	R_X86_64_GOTTPOFF = 22,
	R_X86_64_TPOFF32 = 23,
	R_X86_64_PC64 = 24,
	R_X86_64_GOTOFF64 = 25,
	R_X86_64_GOTPC32 = 26,
	R_X86_64_GOT64 = 27,
	R_X86_64_GOTPCREL64 = 28,
	R_X86_64_GOTPC64 = 29,
	R_X86_64_GOTPLT64 = 30,
	R_X86_64_PLTOFF64 = 31,
	R_X86_64_SIZE32 = 32,
	R_X86_64_SIZE64 = 33,
	R_X86_64_GOTPC32_TLSDESC = 34,
	R_X86_64_TLSDESC_CALL = 35,
	R_X86_64_TLSDESC = 36
	};

	// i386 relocations.
	// TODO: this is just a subset
	enum {
	R_386_NONE = 0,
	R_386_32 = 1,
	R_386_PC32 = 2,
	R_386_GOT32 = 3,
	R_386_PLT32 = 4,
	R_386_COPY = 5,
	R_386_GLOB_DAT = 6,
	R_386_JUMP_SLOT = 7,
	R_386_RELATIVE = 8,
	R_386_GOTOFF = 9,
	R_386_GOTPC = 10,
	R_386_32PLT = 11,
	R_386_TLS_TPOFF = 14,
	R_386_TLS_IE = 15,
	R_386_TLS_GOTIE = 16,
	R_386_TLS_LE = 17,
	R_386_TLS_GD = 18,
	R_386_TLS_LDM = 19,
	R_386_16 = 20,
	R_386_PC16 = 21,
	R_386_8 = 22,
	R_386_PC8 = 23,
	R_386_TLS_GD_32 = 24,
	R_386_TLS_GD_PUSH = 25,
	R_386_TLS_GD_CALL = 26,
	R_386_TLS_GD_POP = 27,
	R_386_TLS_LDM_32 = 28,
	R_386_TLS_LDM_PUSH = 29,
	R_386_TLS_LDM_CALL = 30,
	R_386_TLS_LDM_POP = 31,
	R_386_TLS_LDO_32 = 32,
	R_386_TLS_IE_32 = 33,
	R_386_TLS_LE_32 = 34,
	R_386_TLS_DTPMOD32 = 35,
	R_386_TLS_DTPOFF32 = 36,
	R_386_TLS_TPOFF32 = 37,
	R_386_TLS_GOTDESC = 39,
	R_386_TLS_DESC_CALL = 40,
	R_386_TLS_DESC = 41,
	R_386_IRELATIVE = 42,
	R_386_NUM = 43
	};

	// MBlaze relocations.
	enum {
	R_MICROBLAZE_NONE = 0,
	R_MICROBLAZE_32 = 1,
	R_MICROBLAZE_32_PCREL = 2,
	R_MICROBLAZE_64_PCREL = 3,
	R_MICROBLAZE_32_PCREL_LO = 4,
	R_MICROBLAZE_64 = 5,
	R_MICROBLAZE_32_LO = 6,
	R_MICROBLAZE_SRO32 = 7,
	R_MICROBLAZE_SRW32 = 8,
	R_MICROBLAZE_64_NONE = 9,
	R_MICROBLAZE_32_SYM_OP_SYM = 10,
	R_MICROBLAZE_GNU_VTINHERIT = 11,
	R_MICROBLAZE_GNU_VTENTRY = 12,
	R_MICROBLAZE_GOTPC_64 = 13,
	R_MICROBLAZE_GOT_64 = 14,
	R_MICROBLAZE_PLT_64 = 15,
	R_MICROBLAZE_REL = 16,
	R_MICROBLAZE_JUMP_SLOT = 17,
	R_MICROBLAZE_GLOB_DAT = 18,
	R_MICROBLAZE_GOTOFF_64 = 19,
	R_MICROBLAZE_GOTOFF_32 = 20,
	R_MICROBLAZE_COPY = 21
	};

	enum {
	R_PPC_NONE = 0, /* No relocation. */
	R_PPC_ADDR32 = 1,
	R_PPC_ADDR24 = 2,
	R_PPC_ADDR16 = 3,
	R_PPC_ADDR16_LO = 4,
	R_PPC_ADDR16_HI = 5,
	R_PPC_ADDR16_HA = 6,
	R_PPC_ADDR14 = 7,
	R_PPC_ADDR14_BRTAKEN = 8,
	R_PPC_ADDR14_BRNTAKEN = 9,
	R_PPC_REL24 = 10,
	R_PPC_REL14 = 11,
	R_PPC_REL14_BRTAKEN = 12,
	R_PPC_REL14_BRNTAKEN = 13,
	R_PPC_REL32 = 26
	};

	// ARM Specific e_flags
	enum { EF_ARM_EABIMASK = 0xFF000000U };

	// ELF Relocation types for ARM
	// Meets 2.08 ABI Specs.

	enum {
	R_ARM_NONE = 0x00,
	R_ARM_PC24 = 0x01,
	R_ARM_ABS32 = 0x02,
	R_ARM_REL32 = 0x03,
	R_ARM_LDR_PC_G0 = 0x04,
	R_ARM_ABS16 = 0x05,
	R_ARM_ABS12 = 0x06,
	R_ARM_THM_ABS5 = 0x07,
	R_ARM_ABS8 = 0x08,
	R_ARM_SBREL32 = 0x09,
	R_ARM_THM_CALL = 0x0a,
	R_ARM_THM_PC8 = 0x0b,
	R_ARM_BREL_ADJ = 0x0c,
	R_ARM_TLS_DESC = 0x0d,
	R_ARM_THM_SWI8 = 0x0e,
	R_ARM_XPC25 = 0x0f,
	R_ARM_THM_XPC22 = 0x10,
	R_ARM_TLS_DTPMOD32 = 0x11,
	R_ARM_TLS_DTPOFF32 = 0x12,
	R_ARM_TLS_TPOFF32 = 0x13,
	R_ARM_COPY = 0x14,
	R_ARM_GLOB_DAT = 0x15,
	R_ARM_JUMP_SLOT = 0x16,
	R_ARM_RELATIVE = 0x17,
	R_ARM_GOTOFF32 = 0x18,
	R_ARM_BASE_PREL = 0x19,
	R_ARM_GOT_BREL = 0x1a,
	R_ARM_PLT32 = 0x1b,
	R_ARM_CALL = 0x1c,
	R_ARM_JUMP24 = 0x1d,
	R_ARM_THM_JUMP24 = 0x1e,
	R_ARM_BASE_ABS = 0x1f,
	R_ARM_ALU_PCREL_7_0 = 0x20,
	R_ARM_ALU_PCREL_15_8 = 0x21,
	R_ARM_ALU_PCREL_23_15 = 0x22,
	R_ARM_LDR_SBREL_11_0_NC = 0x23,
	R_ARM_ALU_SBREL_19_12_NC = 0x24,
	R_ARM_ALU_SBREL_27_20_CK = 0x25,
	R_ARM_TARGET1 = 0x26,
	R_ARM_SBREL31 = 0x27,
	R_ARM_V4BX = 0x28,
	R_ARM_TARGET2 = 0x29,
	R_ARM_PREL31 = 0x2a,
	R_ARM_MOVW_ABS_NC = 0x2b,
	R_ARM_MOVT_ABS = 0x2c,
	R_ARM_MOVW_PREL_NC = 0x2d,
	R_ARM_MOVT_PREL = 0x2e,
	R_ARM_THM_MOVW_ABS_NC = 0x2f,
	R_ARM_THM_MOVT_ABS = 0x30,
	R_ARM_THM_MOVW_PREL_NC = 0x31,
	R_ARM_THM_MOVT_PREL = 0x32,
	R_ARM_THM_JUMP19 = 0x33,
	R_ARM_THM_JUMP6 = 0x34,
	R_ARM_THM_ALU_PREL_11_0 = 0x35,
	R_ARM_THM_PC12 = 0x36,
	R_ARM_ABS32_NOI = 0x37,
	R_ARM_REL32_NOI = 0x38,
	R_ARM_ALU_PC_G0_NC = 0x39,
	R_ARM_ALU_PC_G0 = 0x3a,
	R_ARM_ALU_PC_G1_NC = 0x3b,
	R_ARM_ALU_PC_G1 = 0x3c,
	R_ARM_ALU_PC_G2 = 0x3d,
	R_ARM_LDR_PC_G1 = 0x3e,
	R_ARM_LDR_PC_G2 = 0x3f,
	R_ARM_LDRS_PC_G0 = 0x40,
	R_ARM_LDRS_PC_G1 = 0x41,
	R_ARM_LDRS_PC_G2 = 0x42,
	R_ARM_LDC_PC_G0 = 0x43,
	R_ARM_LDC_PC_G1 = 0x44,
	R_ARM_LDC_PC_G2 = 0x45,
	R_ARM_ALU_SB_G0_NC = 0x46,
	R_ARM_ALU_SB_G0 = 0x47,
	R_ARM_ALU_SB_G1_NC = 0x48,
	R_ARM_ALU_SB_G1 = 0x49,
	R_ARM_ALU_SB_G2 = 0x4a,
	R_ARM_LDR_SB_G0 = 0x4b,
	R_ARM_LDR_SB_G1 = 0x4c,
	R_ARM_LDR_SB_G2 = 0x4d,
	R_ARM_LDRS_SB_G0 = 0x4e,
	R_ARM_LDRS_SB_G1 = 0x4f,
	R_ARM_LDRS_SB_G2 = 0x50,
	R_ARM_LDC_SB_G0 = 0x51,
	R_ARM_LDC_SB_G1 = 0x52,
	R_ARM_LDC_SB_G2 = 0x53,
	R_ARM_MOVW_BREL_NC = 0x54,
	R_ARM_MOVT_BREL = 0x55,
	R_ARM_MOVW_BREL = 0x56,
	R_ARM_THM_MOVW_BREL_NC = 0x57,
	R_ARM_THM_MOVT_BREL = 0x58,
	R_ARM_THM_MOVW_BREL = 0x59,
	R_ARM_TLS_GOTDESC = 0x5a,
	R_ARM_TLS_CALL = 0x5b,
	R_ARM_TLS_DESCSEQ = 0x5c,
	R_ARM_THM_TLS_CALL = 0x5d,
	R_ARM_PLT32_ABS = 0x5e,
	R_ARM_GOT_ABS = 0x5f,
	R_ARM_GOT_PREL = 0x60,
	R_ARM_GOT_BREL12 = 0x61,
	R_ARM_GOTOFF12 = 0x62,
	R_ARM_GOTRELAX = 0x63,
	R_ARM_GNU_VTENTRY = 0x64,
	R_ARM_GNU_VTINHERIT = 0x65,
	R_ARM_THM_JUMP11 = 0x66,
	R_ARM_THM_JUMP8 = 0x67,
	R_ARM_TLS_GD32 = 0x68,
	R_ARM_TLS_LDM32 = 0x69,
	R_ARM_TLS_LDO32 = 0x6a,
	R_ARM_TLS_IE32 = 0x6b,
	R_ARM_TLS_LE32 = 0x6c,
	R_ARM_TLS_LDO12 = 0x6d,
	R_ARM_TLS_LE12 = 0x6e,
	R_ARM_TLS_IE12GP = 0x6f,
	R_ARM_PRIVATE_0 = 0x70,
	R_ARM_PRIVATE_1 = 0x71,
	R_ARM_PRIVATE_2 = 0x72,
	R_ARM_PRIVATE_3 = 0x73,
	R_ARM_PRIVATE_4 = 0x74,
	R_ARM_PRIVATE_5 = 0x75,
	R_ARM_PRIVATE_6 = 0x76,
	R_ARM_PRIVATE_7 = 0x77,
	R_ARM_PRIVATE_8 = 0x78,
	R_ARM_PRIVATE_9 = 0x79,
	R_ARM_PRIVATE_10 = 0x7a,
	R_ARM_PRIVATE_11 = 0x7b,
	R_ARM_PRIVATE_12 = 0x7c,
	R_ARM_PRIVATE_13 = 0x7d,
	R_ARM_PRIVATE_14 = 0x7e,
	R_ARM_PRIVATE_15 = 0x7f,
	R_ARM_ME_TOO = 0x80,
	R_ARM_THM_TLS_DESCSEQ16 = 0x81,
	R_ARM_THM_TLS_DESCSEQ32 = 0x82
	};

	// ELF Relocation types for Mips
	enum {
	R_MIPS_NONE = 0,
	R_MIPS_16 = 1,
	R_MIPS_32 = 2,
	R_MIPS_REL32 = 3,
	R_MIPS_26 = 4,
	R_MIPS_HI16 = 5,
	R_MIPS_LO16 = 6,
	R_MIPS_GPREL16 = 7,
	R_MIPS_LITERAL = 8,
	R_MIPS_GOT16 = 9,
	R_MIPS_PC16 = 10,
	R_MIPS_CALL16 = 11,
	R_MIPS_GPREL32 = 12,
	R_MIPS_SHIFT5 = 16,
	R_MIPS_SHIFT6 = 17,
	R_MIPS_64 = 18,
	R_MIPS_GOT_DISP = 19,
	R_MIPS_GOT_PAGE = 20,
	R_MIPS_GOT_OFST = 21,
	R_MIPS_GOT_HI16 = 22,
	R_MIPS_GOT_LO16 = 23,
	R_MIPS_SUB = 24,
	R_MIPS_INSERT_A = 25,
	R_MIPS_INSERT_B = 26,
	R_MIPS_DELETE = 27,
	R_MIPS_HIGHER = 28,
	R_MIPS_HIGHEST = 29,
	R_MIPS_CALL_HI16 = 30,
	R_MIPS_CALL_LO16 = 31,
	R_MIPS_SCN_DISP = 32,
	R_MIPS_REL16 = 33,
	R_MIPS_ADD_IMMEDIATE = 34,
	R_MIPS_PJUMP = 35,
	R_MIPS_RELGOT = 36,
	R_MIPS_JALR = 37,
	R_MIPS_TLS_DTPMOD32 = 38,
	R_MIPS_TLS_DTPREL32 = 39,
	R_MIPS_TLS_DTPMOD64 = 40,
	R_MIPS_TLS_DTPREL64 = 41,
	R_MIPS_TLS_GD = 42,
	R_MIPS_TLS_LDM = 43,
	R_MIPS_TLS_DTPREL_HI16 = 44,
	R_MIPS_TLS_DTPREL_LO16 = 45,
	R_MIPS_TLS_GOTTPREL = 46,
	R_MIPS_TLS_TPREL32 = 47,
	R_MIPS_TLS_TPREL64 = 48,
	R_MIPS_TLS_TPREL_HI16 = 49,
	R_MIPS_TLS_TPREL_LO16 = 50,
	R_MIPS_GLOB_DAT = 51,
	R_MIPS_COPY = 126,
	R_MIPS_JUMP_SLOT = 127,
	R_MIPS_NUM = 218
	};

	// Section header.
	struct Elf32_Shdr {
	Elf32_Word sh_name; // Section name (index into string table)
	Elf32_Word sh_type; // Section type (SHT_*)
	Elf32_Word sh_flags; // Section flags (SHF_*)
	Elf32_Addr sh_addr; // Address where section is to be loaded
	Elf32_Off sh_offset; // File offset of section data, in bytes
	Elf32_Word sh_size; // Size of section, in bytes
	Elf32_Word sh_link; // Section type-specific header table index link
	Elf32_Word sh_info; // Section type-specific extra information
	Elf32_Word sh_addralign; // Section address alignment
	Elf32_Word sh_entsize; // Size of records contained within the section
	};

	// Section header for ELF64 - same fields as ELF32, different types.
	struct Elf64_Shdr {
	Elf64_Word sh_name;
	Elf64_Word sh_type;
	Elf64_Xword sh_flags;
	Elf64_Addr sh_addr;
	Elf64_Off sh_offset;
	Elf64_Xword sh_size;
	Elf64_Word sh_link;
	Elf64_Word sh_info;
	Elf64_Xword sh_addralign;
	Elf64_Xword sh_entsize;
	};

	// Special section indices.
	enum {
	SHN_UNDEF = 0, // Undefined, missing, irrelevant, or meaningless
	SHN_LORESERVE = 0xff00, // Lowest reserved index
	SHN_LOPROC = 0xff00, // Lowest processor-specific index
	SHN_HIPROC = 0xff1f, // Highest processor-specific index
	SHN_LOOS = 0xff20, // Lowest operating system-specific index
	SHN_HIOS = 0xff3f, // Highest operating system-specific index
	SHN_ABS = 0xfff1, // Symbol has absolute value; does not need reloc
	ation
	SHN_COMMON = 0xfff2, // FORTRAN COMMON or C external global variables
	SHN_XINDEX = 0xffff, // Mark that the index is >= SHN_LORESERVE
	SHN_HIRESERVE = 0xffff // Highest reserved index
	};

	// Section types.
	enum {
	SHT_NULL = 0, // No associated section (inactive entry).
	SHT_PROGBITS = 1, // Program-defined contents.
	SHT_SYMTAB = 2, // Symbol table.
	SHT_STRTAB = 3, // String table.
	SHT_RELA = 4, // Relocation entries; explicit addends.
	SHT_HASH = 5, // Symbol hash table.
	SHT_DYNAMIC = 6, // Information for dynamic linking.
	SHT_NOTE = 7, // Information about the file.
	SHT_NOBITS = 8, // Data occupies no space in the file.
	SHT_REL = 9, // Relocation entries; no explicit addends.
	SHT_SHLIB = 10, // Reserved.
	SHT_DYNSYM = 11, // Symbol table.
	SHT_INIT_ARRAY = 14, // Pointers to initialization functions.
	SHT_FINI_ARRAY = 15, // Pointers to termination functions.
	SHT_PREINIT_ARRAY = 16, // Pointers to pre-init functions.
	SHT_GROUP = 17, // Section group.
	SHT_SYMTAB_SHNDX = 18, // Indices for SHN_XINDEX entries.
	SHT_LOOS = 0x60000000, // Lowest operating system-specific type.
	SHT_HIOS = 0x6fffffff, // Highest operating system-specific type
	.
	SHT_LOPROC = 0x70000000, // Lowest processor architecture-specific
	type.
	// Fixme: All this is duplicated in MCSectionELF. Why??
	// Exception Index table
	SHT_ARM_EXIDX = 0x70000001U,
	// BPABI DLL dynamic linking pre-emption map
	SHT_ARM_PREEMPTMAP = 0x70000002U,
	// Object file compatibility attributes
	SHT_ARM_ATTRIBUTES = 0x70000003U,
	SHT_ARM_DEBUGOVERLAY = 0x70000004U,
	SHT_ARM_OVERLAYSECTION = 0x70000005U,

	SHT_X86_64_UNWIND = 0x70000001, // Unwind information

	SHT_HIPROC = 0x7fffffff, // Highest processor architecture-specifi
	c type.
	SHT_LOUSER = 0x80000000, // Lowest type reserved for applications.
	SHT_HIUSER = 0xffffffff // Highest type reserved for applications
	.
	};

	// Section flags.
	enum {
	// Section data should be writable during execution.
	SHF_WRITE = 0x1,

	// Section occupies memory during program execution.
	SHF_ALLOC = 0x2,

	// Section contains executable machine instructions.
	SHF_EXECINSTR = 0x4,

	// The data in this section may be merged.
	SHF_MERGE = 0x10,

	// The data in this section is null-terminated strings.
	SHF_STRINGS = 0x20,

	// A field in this section holds a section header table index.
	SHF_INFO_LINK = 0x40U,

	// Adds special ordering requirements for link editors.
	SHF_LINK_ORDER = 0x80U,

	// This section requires special OS-specific processing to avoid incorrec
	t
	// behavior.
	SHF_OS_NONCONFORMING = 0x100U,

	// This section is a member of a section group.
	SHF_GROUP = 0x200U,

	// This section holds Thread-Local Storage.
	SHF_TLS = 0x400U,

	// Start of target-specific flags.

	/// XCORE_SHF_CP_SECTION - All sections with the "c" flag are grouped
	/// together by the linker to form the constant pool and the cp register
	is
	/// set to the start of the constant pool by the boot code.
	XCORE_SHF_CP_SECTION = 0x800U,

	/// XCORE_SHF_DP_SECTION - All sections with the "d" flag are grouped
	/// together by the linker to form the data section and the dp register i
	s
	/// set to the start of the section by the boot code.
	XCORE_SHF_DP_SECTION = 0x1000U,

	SHF_MASKOS = 0x0ff00000,

	// Bits indicating processor-specific flags.
	SHF_MASKPROC = 0xf0000000,

	// If an object file section does not have this flag set, then it may not
	hold
	// more than 2GB and can be freely referred to in objects using smaller c
	ode
	// models. Otherwise, only objects using larger code models can refer to
	them.
	// For example, a medium code model object can refer to data in a section
	that
	// sets this flag besides being able to refer to data in a section that d
	oes
	// not set it; likewise, a small code model object can refer only to code
	in a
	// section that does not set this flag.
	SHF_X86_64_LARGE = 0x10000000
	};

	// Section Group Flags
	enum {
	GRP_COMDAT = 0x1,
	GRP_MASKOS = 0x0ff00000,
	GRP_MASKPROC = 0xf0000000
	};

	// Symbol table entries for ELF32.
	struct Elf32_Sym {
	Elf32_Word st_name; // Symbol name (index into string table)
	Elf32_Addr st_value; // Value or address associated with the symbol
	Elf32_Word st_size; // Size of the symbol
	unsigned char st_info; // Symbol's type and binding attributes	unsigned char st_info; // Symbol's type and binding attributes
	unsigned char st_other; // Must be zero; reserved	unsigned char st_other; // Must be zero; reserved

	Elf32_Half st_shndx; // Which section (header table index) it's define	Elf_Half st_shndx; // Which section (header table index) it's define
	d in	d in
		Elf_Addr st_value; // Value or address associated with the symbol
		Elf_Xword st_size; // Size of the symbol
		};

		template<support::endianness target_endianness, bool is64Bits>
		struct Elf_Sym_Impl : Elf_Sym_Base<target_endianness, is64Bits> {
		using Elf_Sym_Base<target_endianness, is64Bits>::st_info;

	// These accessors and mutators correspond to the ELF32_ST_BIND,	// These accessors and mutators correspond to the ELF32_ST_BIND,
	// ELF32_ST_TYPE, and ELF32_ST_INFO macros defined in the ELF specificati on:	// ELF32_ST_TYPE, and ELF32_ST_INFO macros defined in the ELF specificati on:
	unsigned char getBinding() const { return st_info >> 4; }	unsigned char getBinding() const { return st_info >> 4; }
	unsigned char getType() const { return st_info & 0x0f; }	unsigned char getType() const { return st_info & 0x0f; }
	void setBinding(unsigned char b) { setBindingAndType(b, getType()); }	void setBinding(unsigned char b) { setBindingAndType(b, getType()); }
	void setType(unsigned char t) { setBindingAndType(getBinding(), t); }	void setType(unsigned char t) { setBindingAndType(getBinding(), t); }
	void setBindingAndType(unsigned char b, unsigned char t) {	void setBindingAndType(unsigned char b, unsigned char t) {
	st_info = (b << 4) + (t & 0x0f);	st_info = (b << 4) + (t & 0x0f);
	}	}
	};	};


	// Symbol table entries for ELF64.	/// Elf_Versym: This is the structure of entries in the SHT_GNU_versym sect
	struct Elf64_Sym {	ion
	Elf64_Word st_name; // Symbol name (index into string table)	/// (.gnu.version). This structure is identical for ELF32 and ELF64.
	unsigned char st_info; // Symbol's type and binding attributes	template<support::endianness target_endianness, bool is64Bits>
	unsigned char st_other; // Must be zero; reserved	struct Elf_Versym_Impl {
	Elf64_Half st_shndx; // Which section (header table index) it's defi	LLVM_ELF_IMPORT_TYPES(target_endianness, is64Bits)
	ned in	Elf_Half vs_index; // Version index with flags (e.g. VERSYM_HIDDEN)
	Elf64_Addr st_value; // Value or address associated with the symbol	};
	Elf64_Xword st_size; // Size of the symbol
		template<support::endianness target_endianness, bool is64Bits>
	// These accessors and mutators are identical to those defined for ELF32	struct Elf_Verdaux_Impl;
	// symbol table entries.
	unsigned char getBinding() const { return st_info >> 4; }	/// Elf_Verdef: This is the structure of entries in the SHT_GNU_verdef sect
	unsigned char getType() const { return st_info & 0x0f; }	ion
	void setBinding(unsigned char b) { setBindingAndType(b, getType()); }	/// (.gnu.version_d). This structure is identical for ELF32 and ELF64.
	void setType(unsigned char t) { setBindingAndType(getBinding(), t); }	template<support::endianness target_endianness, bool is64Bits>
	void setBindingAndType(unsigned char b, unsigned char t) {	struct Elf_Verdef_Impl {
	st_info = (b << 4) + (t & 0x0f);	LLVM_ELF_IMPORT_TYPES(target_endianness, is64Bits)
		typedef Elf_Verdaux_Impl<target_endianness, is64Bits> Elf_Verdaux;
		Elf_Half vd_version; // Version of this structure (e.g. VER_DEF_CURRENT)
		Elf_Half vd_flags; // Bitwise flags (VER_DEF_*)
		Elf_Half vd_ndx; // Version index, used in .gnu.version entries
		Elf_Half vd_cnt; // Number of Verdaux entries
		Elf_Word vd_hash; // Hash of name
		Elf_Word vd_aux; // Offset to the first Verdaux entry (in bytes)
		Elf_Word vd_next; // Offset to the next Verdef entry (in bytes)

		/// Get the first Verdaux entry for this Verdef.
		const Elf_Verdaux *getAux() const {
		return reinterpret_cast<const Elf_Verdaux>((const char)this + vd_aux)
		;
	}	}
	};	};


	// The size (in bytes) of symbol table entries.	/// Elf_Verdaux: This is the structure of auxilary data in the SHT_GNU_verd
	enum {	ef
	SYMENTRY_SIZE32 = 16, // 32-bit symbol entry size	/// section (.gnu.version_d). This structure is identical for ELF32 and ELF
	SYMENTRY_SIZE64 = 24 // 64-bit symbol entry size.	64.
	};	template<support::endianness target_endianness, bool is64Bits>
		struct Elf_Verdaux_Impl {
	// Symbol bindings.	LLVM_ELF_IMPORT_TYPES(target_endianness, is64Bits)
	enum {	Elf_Word vda_name; // Version name (offset in string table)
	STB_LOCAL = 0, // Local symbol, not visible outside obj file containing	Elf_Word vda_next; // Offset to next Verdaux entry (in bytes)
	def	};
	STB_GLOBAL = 1, // Global symbol, visible to all object files being comb
	ined	/// Elf_Verneed: This is the structure of entries in the SHT_GNU_verneed
	STB_WEAK = 2, // Weak symbol, like global but lower-precedence	/// section (.gnu.version_r). This structure is identical for ELF32 and ELF
	STB_LOOS = 10, // Lowest operating system-specific binding type	64.
	STB_HIOS = 12, // Highest operating system-specific binding type	template<support::endianness target_endianness, bool is64Bits>
	STB_LOPROC = 13, // Lowest processor-specific binding type	struct Elf_Verneed_Impl {
	STB_HIPROC = 15 // Highest processor-specific binding type	LLVM_ELF_IMPORT_TYPES(target_endianness, is64Bits)
	};	Elf_Half vn_version; // Version of this structure (e.g. VER_NEED_CURRENT)
		Elf_Half vn_cnt; // Number of associated Vernaux entries
	// Symbol types.	Elf_Word vn_file; // Library name (string table offset)
	enum {	Elf_Word vn_aux; // Offset to first Vernaux entry (in bytes)
	STT_NOTYPE = 0, // Symbol's type is not specified	Elf_Word vn_next; // Offset to next Verneed entry (in bytes)
	STT_OBJECT = 1, // Symbol is a data object (variable, array, etc.)	};
	STT_FUNC = 2, // Symbol is executable code (function, etc.)
	STT_SECTION = 3, // Symbol refers to a section	/// Elf_Vernaux: This is the structure of auxiliary data in SHT_GNU_verneed
	STT_FILE = 4, // Local, absolute symbol that refers to a file	/// section (.gnu.version_r). This structure is identical for ELF32 and ELF
	STT_COMMON = 5, // An uninitialized common block	64.
	STT_TLS = 6, // Thread local data object	template<support::endianness target_endianness, bool is64Bits>
	STT_LOOS = 7, // Lowest operating system-specific symbol type	struct Elf_Vernaux_Impl {
	STT_HIOS = 8, // Highest operating system-specific symbol type	LLVM_ELF_IMPORT_TYPES(target_endianness, is64Bits)
	STT_LOPROC = 13, // Lowest processor-specific symbol type	Elf_Word vna_hash; // Hash of dependency name
	STT_HIPROC = 15 // Highest processor-specific symbol type	Elf_Half vna_flags; // Bitwise Flags (VER_FLAG_*)
	};	Elf_Half vna_other; // Version index, used in .gnu.version entries
		Elf_Word vna_name; // Dependency name
	enum {	Elf_Word vna_next; // Offset to next Vernaux entry (in bytes)
	STV_DEFAULT = 0, // Visibility is specified by binding type	};
	STV_INTERNAL = 1, // Defined by processor supplements
	STV_HIDDEN = 2, // Not visible to other components	/// Elf_Dyn_Base: This structure matches the form of entries in the dynamic
	STV_PROTECTED = 3 // Visible in other components but not preemptable	/// table section (.dynamic) look like.
	};	template<support::endianness target_endianness, bool is64Bits>
		struct Elf_Dyn_Base;
	// Relocation entry, without explicit addend.
	struct Elf32_Rel {	template<support::endianness target_endianness>
	Elf32_Addr r_offset; // Location (file byte offset, or program virtual ad	struct Elf_Dyn_Base<target_endianness, false> {
	dr)	LLVM_ELF_IMPORT_TYPES(target_endianness, false)
	Elf32_Word r_info; // Symbol table index and type of relocation to appl	Elf_Sword d_tag;
	y	union {
		Elf_Word d_val;
		Elf_Addr d_ptr;
		} d_un;
		};


	// These accessors and mutators correspond to the ELF32_R_SYM, ELF32_R_TY	template<support::endianness target_endianness>
	PE,	struct Elf_Dyn_Base<target_endianness, true> {
	// and ELF32_R_INFO macros defined in the ELF specification:	LLVM_ELF_IMPORT_TYPES(target_endianness, true)
	Elf32_Word getSymbol() const { return (r_info >> 8); }	Elf_Sxword d_tag;
	unsigned char getType() const { return (unsigned char) (r_info & 0x0ff);	union {
	}	Elf_Xword d_val;
	void setSymbol(Elf32_Word s) { setSymbolAndType(s, getType()); }	Elf_Addr d_ptr;
	void setType(unsigned char t) { setSymbolAndType(getSymbol(), t); }	} d_un;
	void setSymbolAndType(Elf32_Word s, unsigned char t) {
	r_info = (s << 8) + t;
	}
	};	};


	// Relocation entry with explicit addend.	/// Elf_Dyn_Impl: This inherits from Elf_Dyn_Base, adding getters and sette
	struct Elf32_Rela {	rs.
	Elf32_Addr r_offset; // Location (file byte offset, or program virtual a	template<support::endianness target_endianness, bool is64Bits>
	ddr)	struct Elf_Dyn_Impl : Elf_Dyn_Base<target_endianness, is64Bits> {
	Elf32_Word r_info; // Symbol table index and type of relocation to app	using Elf_Dyn_Base<target_endianness, is64Bits>::d_tag;
	ly	using Elf_Dyn_Base<target_endianness, is64Bits>::d_un;
	Elf32_Sword r_addend; // Compute value for relocatable field by adding th	int64_t getTag() const { return d_tag; }
	is	uint64_t getVal() const { return d_un.d_val; }
		uint64_t getPtr() const { return d_un.ptr; }
		};


	// These accessors and mutators correspond to the ELF32_R_SYM, ELF32_R_TY	template<support::endianness target_endianness, bool is64Bits>
	PE,	class ELFObjectFile;
	// and ELF32_R_INFO macros defined in the ELF specification:
	Elf32_Word getSymbol() const { return (r_info >> 8); }	// DynRefImpl: Reference to an entry in the dynamic table
	unsigned char getType() const { return (unsigned char) (r_info & 0x0ff);	// This is an ELF-specific interface.
	}	template<support::endianness target_endianness, bool is64Bits>
	void setSymbol(Elf32_Word s) { setSymbolAndType(s, getType()); }	class DynRefImpl {
	void setType(unsigned char t) { setSymbolAndType(getSymbol(), t); }	typedef Elf_Dyn_Impl<target_endianness, is64Bits> Elf_Dyn;
	void setSymbolAndType(Elf32_Word s, unsigned char t) {	typedef ELFObjectFile<target_endianness, is64Bits> OwningType;
	r_info = (s << 8) + t;
	}	DataRefImpl DynPimpl;
		const OwningType *OwningObject;

		public:
		DynRefImpl() : OwningObject(NULL) { }

		DynRefImpl(DataRefImpl DynP, const OwningType *Owner);

		bool operator==(const DynRefImpl &Other) const;
		bool operator <(const DynRefImpl &Other) const;

		error_code getNext(DynRefImpl &Result) const;
		int64_t getTag() const;
		uint64_t getVal() const;
		uint64_t getPtr() const;

		DataRefImpl getRawDataRefImpl() const;
	};	};


	// Relocation entry, without explicit addend.	// Elf_Rel: Elf Relocation
	struct Elf64_Rel {	template<support::endianness target_endianness, bool is64Bits, bool isRela>
	Elf64_Addr r_offset; // Location (file byte offset, or program virtual ad	struct Elf_Rel_Base;
	dr).
	Elf64_Xword r_info; // Symbol table index and type of relocation to app	template<support::endianness target_endianness>
	ly.	struct Elf_Rel_Base<target_endianness, false, false> {
		LLVM_ELF_IMPORT_TYPES(target_endianness, false)
		Elf_Addr r_offset; // Location (file byte offset, or program virtual
		addr)
		Elf_Word r_info; // Symbol table index and type of relocation to ap
		ply
		};

		template<support::endianness target_endianness>
		struct Elf_Rel_Base<target_endianness, true, false> {
		LLVM_ELF_IMPORT_TYPES(target_endianness, true)
		Elf_Addr r_offset; // Location (file byte offset, or program virtual
		addr)
		Elf_Xword r_info; // Symbol table index and type of relocation to a
		pply
		};

		template<support::endianness target_endianness>
		struct Elf_Rel_Base<target_endianness, false, true> {
		LLVM_ELF_IMPORT_TYPES(target_endianness, false)
		Elf_Addr r_offset; // Location (file byte offset, or program virtual
		addr)
		Elf_Word r_info; // Symbol table index and type of relocation to a
		pply
		Elf_Sword r_addend; // Compute value for relocatable field by adding
		this
		};

		template<support::endianness target_endianness>
		struct Elf_Rel_Base<target_endianness, true, true> {
		LLVM_ELF_IMPORT_TYPES(target_endianness, true)
		Elf_Addr r_offset; // Location (file byte offset, or program virtual
		addr)
		Elf_Xword r_info; // Symbol table index and type of relocation to a
		pply
		Elf_Sxword r_addend; // Compute value for relocatable field by adding
		this.
		};

		template<support::endianness target_endianness, bool is64Bits, bool isRela>
		struct Elf_Rel_Impl;

		template<support::endianness target_endianness, bool isRela>
		struct Elf_Rel_Impl<target_endianness, true, isRela>
		: Elf_Rel_Base<target_endianness, true, isRela> {
		using Elf_Rel_Base<target_endianness, true, isRela>::r_info;
		LLVM_ELF_IMPORT_TYPES(target_endianness, true)

	// These accessors and mutators correspond to the ELF64_R_SYM, ELF64_R_TY PE,	// These accessors and mutators correspond to the ELF64_R_SYM, ELF64_R_TY PE,
	// and ELF64_R_INFO macros defined in the ELF specification:	// and ELF64_R_INFO macros defined in the ELF specification:

	Elf64_Xword getSymbol() const { return (r_info >> 32); }	uint64_t getSymbol() const { return (r_info >> 32); }
	unsigned char getType() const {	unsigned char getType() const {
	return (unsigned char) (r_info & 0xffffffffL);	return (unsigned char) (r_info & 0xffffffffL);
	}	}

	void setSymbol(Elf32_Word s) { setSymbolAndType(s, getType()); }	void setSymbol(uint64_t s) { setSymbolAndType(s, getType()); }
	void setType(unsigned char t) { setSymbolAndType(getSymbol(), t); }	void setType(unsigned char t) { setSymbolAndType(getSymbol(), t); }

	void setSymbolAndType(Elf64_Xword s, unsigned char t) {	void setSymbolAndType(uint64_t s, unsigned char t) {
	r_info = (s << 32) + (t&0xffffffffL);	r_info = (s << 32) + (t&0xffffffffL);
	}	}
	};	};


	// Relocation entry with explicit addend.	template<support::endianness target_endianness, bool isRela>
	struct Elf64_Rela {	struct Elf_Rel_Impl<target_endianness, false, isRela>
	Elf64_Addr r_offset; // Location (file byte offset, or program virtual a	: Elf_Rel_Base<target_endianness, false, isRela> {
	ddr).	using Elf_Rel_Base<target_endianness, false, isRela>::r_info;
	Elf64_Xword r_info; // Symbol table index and type of relocation to ap	LLVM_ELF_IMPORT_TYPES(target_endianness, false)
	ply.
	Elf64_Sxword r_addend; // Compute value for relocatable field by adding t
	his.


	// These accessors and mutators correspond to the ELF64_R_SYM, ELF64_R_TY	// These accessors and mutators correspond to the ELF32_R_SYM, ELF32_R_TY
	PE,	PE,
	// and ELF64_R_INFO macros defined in the ELF specification:	// and ELF32_R_INFO macros defined in the ELF specification:
	Elf64_Xword getSymbol() const { return (r_info >> 32); }	uint32_t getSymbol() const { return (r_info >> 8); }
	unsigned char getType() const {	unsigned char getType() const { return (unsigned char) (r_info & 0x0ff);
	return (unsigned char) (r_info & 0xffffffffL);	}
	}	void setSymbol(uint32_t s) { setSymbolAndType(s, getType()); }
	void setSymbol(Elf64_Xword s) { setSymbolAndType(s, getType()); }
	void setType(unsigned char t) { setSymbolAndType(getSymbol(), t); }	void setType(unsigned char t) { setSymbolAndType(getSymbol(), t); }

	void setSymbolAndType(Elf64_Xword s, unsigned char t) {	void setSymbolAndType(uint32_t s, unsigned char t) {
	r_info = (s << 32) + (t&0xffffffffL);	r_info = (s << 8) + t;
	}	}
	};	};


	// Program header for ELF32.	template<support::endianness target_endianness, bool is64Bits>
	struct Elf32_Phdr {	class ELFObjectFile : public ObjectFile {
	Elf32_Word p_type; // Type of segment	LLVM_ELF_IMPORT_TYPES(target_endianness, is64Bits)
	Elf32_Off p_offset; // File offset where segment is located, in bytes
	Elf32_Addr p_vaddr; // Virtual address of beginning of segment	typedef Elf_Shdr_Impl<target_endianness, is64Bits> Elf_Shdr;
	Elf32_Addr p_paddr; // Physical address of beginning of segment (OS-spec	typedef Elf_Sym_Impl<target_endianness, is64Bits> Elf_Sym;
	ific)	typedef Elf_Dyn_Impl<target_endianness, is64Bits> Elf_Dyn;
	Elf32_Word p_filesz; // Num. of bytes in file image of segment (may be ze	typedef Elf_Rel_Impl<target_endianness, is64Bits, false> Elf_Rel;
	ro)	typedef Elf_Rel_Impl<target_endianness, is64Bits, true> Elf_Rela;
	Elf32_Word p_memsz; // Num. of bytes in mem image of segment (may be zer	typedef Elf_Verdef_Impl<target_endianness, is64Bits> Elf_Verdef;
	o)	typedef Elf_Verdaux_Impl<target_endianness, is64Bits> Elf_Verdaux;
	Elf32_Word p_flags; // Segment flags	typedef Elf_Verneed_Impl<target_endianness, is64Bits> Elf_Verneed;
	Elf32_Word p_align; // Segment alignment constraint	typedef Elf_Vernaux_Impl<target_endianness, is64Bits> Elf_Vernaux;
	};	typedef Elf_Versym_Impl<target_endianness, is64Bits> Elf_Versym;
		typedef DynRefImpl<target_endianness, is64Bits> DynRef;
	// Program header for ELF64.	typedef content_iterator<DynRef> dyn_iterator;
	struct Elf64_Phdr {
	Elf64_Word p_type; // Type of segment	protected:
	Elf64_Word p_flags; // Segment flags	struct Elf_Ehdr {
	Elf64_Off p_offset; // File offset where segment is located, in bytes	unsigned char e_ident[ELF::EI_NIDENT]; // ELF Identification bytes
	Elf64_Addr p_vaddr; // Virtual address of beginning of segment	Elf_Half e_type; // Type of file (see ET_*)
	Elf64_Addr p_paddr; // Physical address of beginning of segment (OS-sp	Elf_Half e_machine; // Required architecture for this file (see EM_*)
	ecific)	Elf_Word e_version; // Must be equal to 1
	Elf64_Xword p_filesz; // Num. of bytes in file image of segment (may be	Elf_Addr e_entry; // Address to jump to in order to start program
	zero)	Elf_Off e_phoff; // Program header table's file offset, in bytes
	Elf64_Xword p_memsz; // Num. of bytes in mem image of segment (may be z	Elf_Off e_shoff; // Section header table's file offset, in bytes
	ero)	Elf_Word e_flags; // Processor-specific flags
	Elf64_Xword p_align; // Segment alignment constraint	Elf_Half e_ehsize; // Size of ELF header, in bytes
	};	Elf_Half e_phentsize;// Size of an entry in the program header table
		Elf_Half e_phnum; // Number of entries in the program header table
	// Segment types.	Elf_Half e_shentsize;// Size of an entry in the section header table
	enum {	Elf_Half e_shnum; // Number of entries in the section header table
	PT_NULL = 0, // Unused segment.	Elf_Half e_shstrndx; // Section header table index of section name
	PT_LOAD = 1, // Loadable segment.	// string table
	PT_DYNAMIC = 2, // Dynamic linking information.	bool checkMagic() const {
	PT_INTERP = 3, // Interpreter pathname.	return (memcmp(e_ident, ELF::ElfMagic, strlen(ELF::ElfMagic))) == 0;
	PT_NOTE = 4, // Auxiliary information.	}
	PT_SHLIB = 5, // Reserved.	unsigned char getFileClass() const { return e_ident[ELF::EI_CLASS]; }
	PT_PHDR = 6, // The program header table itself.	unsigned char getDataEncoding() const { return e_ident[ELF::EI_DATA]; }
	PT_TLS = 7, // The thread-local storage template.	};
	PT_LOOS = 0x60000000, // Lowest operating system-specific pt entry typ	// This flag is used for classof, to distinguish ELFObjectFile from
	e.	// its subclass. If more subclasses will be created, this flag will
		// have to become an enum.
	// x86-64 program header types.	bool isDyldELFObject;
	// These all contain stack unwind tables.
	PT_GNU_EH_FRAME = 0x6474e550,	private:
	PT_SUNW_EH_FRAME = 0x6474e550,	typedef SmallVector<const Elf_Shdr*, 1> Sections_t;
	PT_SUNW_UNWIND = 0x6464e550,	typedef DenseMap<unsigned, unsigned> IndexMap_t;
		typedef DenseMap<const Elf_Shdr*, SmallVector<uint32_t, 1> > RelocMap_t;
	PT_HIOS = 0x6fffffff, // Highest operating system-specific pt entry ty
	pe.	const Elf_Ehdr *Header;
	PT_LOPROC = 0x70000000, // Lowest processor-specific program hdr entry t	const Elf_Shdr *SectionHeaderTable;
	ype.	const Elf_Shdr *dot_shstrtab_sec; // Section header string table.
	PT_HIPROC = 0x7fffffff // Highest processor-specific program hdr entry	const Elf_Shdr *dot_strtab_sec; // Symbol header string table.
	type.	const Elf_Shdr *dot_dynstr_sec; // Dynamic symbol string table.
	};
		// SymbolTableSections[0] always points to the dynamic string table secti
	// Segment flag bits.	on
	enum {	// header, or NULL if there is no dynamic string table.
	PF_X = 1, // Execute	Sections_t SymbolTableSections;
	PF_W = 2, // Write	IndexMap_t SymbolTableSectionsIndexMap;
	PF_R = 4, // Read	DenseMap<const Elf_Sym*, ELF::Elf64_Word> ExtendedSymbolTable;
	PF_MASKOS = 0x0ff00000,// Bits for operating system-specific semantics.
	PF_MASKPROC = 0xf0000000 // Bits for processor-specific semantics.	const Elf_Shdr *dot_dynamic_sec; // .dynamic
	};	const Elf_Shdr *dot_gnu_version_sec; // .gnu.version
		const Elf_Shdr *dot_gnu_version_r_sec; // .gnu.version_r
	// Dynamic table entry for ELF32.	const Elf_Shdr *dot_gnu_version_d_sec; // .gnu.version_d
	struct Elf32_Dyn
	{	// Pointer to SONAME entry in dynamic string table
	Elf32_Sword d_tag; // Type of dynamic table entry.	// This is set the first time getLoadName is called.
	union	mutable const char *dt_soname;
	{
	Elf32_Word d_val; // Integer value of entry.	// Records for each version index the corresponding Verdef or Vernaux ent
	Elf32_Addr d_ptr; // Pointer value of entry.	ry.
	} d_un;	// This is filled the first time LoadVersionMap() is called.
	};	class VersionMapEntry : public PointerIntPair<const void*, 1> {
		public:
		// If the integer is 0, this is an Elf_Verdef*.
		// If the integer is 1, this is an Elf_Vernaux*.
		VersionMapEntry() : PointerIntPair<const void*, 1>(NULL, 0) { }
		VersionMapEntry(const Elf_Verdef *verdef)
		: PointerIntPair<const void*, 1>(verdef, 0) { }
		VersionMapEntry(const Elf_Vernaux *vernaux)
		: PointerIntPair<const void*, 1>(vernaux, 1) { }
		bool isNull() const { return getPointer() == NULL; }
		bool isVerdef() const { return !isNull() && getInt() == 0; }
		bool isVernaux() const { return !isNull() && getInt() == 1; }
		const Elf_Verdef *getVerdef() const {
		return isVerdef() ? (const Elf_Verdef*)getPointer() : NULL;
		}
		const Elf_Vernaux *getVernaux() const {
		return isVernaux() ? (const Elf_Vernaux*)getPointer() : NULL;
		}
		};
		mutable SmallVector<VersionMapEntry, 16> VersionMap;
		void LoadVersionDefs(const Elf_Shdr *sec) const;
		void LoadVersionNeeds(const Elf_Shdr *ec) const;
		void LoadVersionMap() const;

		/// @brief Map sections to an array of relocation sections that reference
		/// them sorted by section index.
		RelocMap_t SectionRelocMap;

		/// @brief Get the relocation section that contains \a Rel.
		const Elf_Shdr *getRelSection(DataRefImpl Rel) const {
		return getSection(Rel.w.b);
		}


	// Dynamic table entry for ELF64.	bool isRelocationHasAddend(DataRefImpl Rel) const;
	struct Elf64_Dyn	template<typename T>
	{	const T *getEntry(uint16_t Section, uint32_t Entry) const;
	Elf64_Sxword d_tag; // Type of dynamic table entry.	template<typename T>
	union	const T getEntry(const Elf_Shdr Section, uint32_t Entry) const;
	{	const Elf_Shdr *getSection(DataRefImpl index) const;
	Elf64_Xword d_val; // Integer value of entry.	const Elf_Shdr *getSection(uint32_t index) const;
	Elf64_Addr d_ptr; // Pointer value of entry.	const Elf_Rel *getRel(DataRefImpl Rel) const;
	} d_un;	const Elf_Rela *getRela(DataRefImpl Rela) const;
		const char *getString(uint32_t section, uint32_t offset) const;
		const char getString(const Elf_Shdr section, uint32_t offset) const
		;
		error_code getSymbolName(const Elf_Shdr *section,
		const Elf_Sym *Symb,
		StringRef &Res) const;
		error_code getSymbolVersion(const Elf_Shdr *section,
		const Elf_Sym *Symb,
		StringRef &Version,
		bool &IsDefault) const;
		void VerifyStrTab(const Elf_Shdr *sh) const;

		protected:
		const Elf_Sym *getSymbol(DataRefImpl Symb) const; // FIXME: Should be pr
		ivate?
		void validateSymbol(DataRefImpl Symb) const;

		public:
		const Elf_Dyn *getDyn(DataRefImpl DynData) const;
		error_code getSymbolVersion(SymbolRef Symb, StringRef &Version,
		bool &IsDefault) const;
		protected:
		virtual error_code getSymbolNext(DataRefImpl Symb, SymbolRef &Res) const;
		virtual error_code getSymbolName(DataRefImpl Symb, StringRef &Res) const;
		virtual error_code getSymbolFileOffset(DataRefImpl Symb, uint64_t &Res) c
		onst;
		virtual error_code getSymbolAddress(DataRefImpl Symb, uint64_t &Res) cons
		t;
		virtual error_code getSymbolSize(DataRefImpl Symb, uint64_t &Res) const;
		virtual error_code getSymbolNMTypeChar(DataRefImpl Symb, char &Res) const
		;
		virtual error_code getSymbolFlags(DataRefImpl Symb, uint32_t &Res) const;
		virtual error_code getSymbolType(DataRefImpl Symb, SymbolRef::Type &Res)
		const;
		virtual error_code getSymbolSection(DataRefImpl Symb,
		section_iterator &Res) const;

		friend class DynRefImpl<target_endianness, is64Bits>;
		virtual error_code getDynNext(DataRefImpl DynData, DynRef &Result) const;

		virtual error_code getLibraryNext(DataRefImpl Data, LibraryRef &Result) c
		onst;
		virtual error_code getLibraryPath(DataRefImpl Data, StringRef &Res) const
		;

		virtual error_code getSectionNext(DataRefImpl Sec, SectionRef &Res) const
		;
		virtual error_code getSectionName(DataRefImpl Sec, StringRef &Res) const;
		virtual error_code getSectionAddress(DataRefImpl Sec, uint64_t &Res) cons
		t;
		virtual error_code getSectionSize(DataRefImpl Sec, uint64_t &Res) const;
		virtual error_code getSectionContents(DataRefImpl Sec, StringRef &Res) co
		nst;
		virtual error_code getSectionAlignment(DataRefImpl Sec, uint64_t &Res) co
		nst;
		virtual error_code isSectionText(DataRefImpl Sec, bool &Res) const;
		virtual error_code isSectionData(DataRefImpl Sec, bool &Res) const;
		virtual error_code isSectionBSS(DataRefImpl Sec, bool &Res) const;
		virtual error_code isSectionRequiredForExecution(DataRefImpl Sec,
		bool &Res) const;
		virtual error_code isSectionVirtual(DataRefImpl Sec, bool &Res) const;
		virtual error_code isSectionZeroInit(DataRefImpl Sec, bool &Res) const;
		virtual error_code sectionContainsSymbol(DataRefImpl Sec, DataRefImpl Sym
		b,
		bool &Result) const;
		virtual relocation_iterator getSectionRelBegin(DataRefImpl Sec) const;
		virtual relocation_iterator getSectionRelEnd(DataRefImpl Sec) const;

		virtual error_code getRelocationNext(DataRefImpl Rel,
		RelocationRef &Res) const;
		virtual error_code getRelocationAddress(DataRefImpl Rel,
		uint64_t &Res) const;
		virtual error_code getRelocationOffset(DataRefImpl Rel,
		uint64_t &Res) const;
		virtual error_code getRelocationSymbol(DataRefImpl Rel,
		SymbolRef &Res) const;
		virtual error_code getRelocationType(DataRefImpl Rel,
		uint64_t &Res) const;
		virtual error_code getRelocationTypeName(DataRefImpl Rel,
		SmallVectorImpl<char> &Result) c
		onst;
		virtual error_code getRelocationAdditionalInfo(DataRefImpl Rel,
		int64_t &Res) const;
		virtual error_code getRelocationValueString(DataRefImpl Rel,
		SmallVectorImpl<char> &Result) c
		onst;

		public:
		ELFObjectFile(MemoryBuffer *Object, error_code &ec);
		virtual symbol_iterator begin_symbols() const;
		virtual symbol_iterator end_symbols() const;

		virtual symbol_iterator begin_dynamic_symbols() const;
		virtual symbol_iterator end_dynamic_symbols() const;

		virtual section_iterator begin_sections() const;
		virtual section_iterator end_sections() const;

		virtual library_iterator begin_libraries_needed() const;
		virtual library_iterator end_libraries_needed() const;

		virtual dyn_iterator begin_dynamic_table() const;
		virtual dyn_iterator end_dynamic_table() const;

		virtual uint8_t getBytesInAddress() const;
		virtual StringRef getFileFormatName() const;
		virtual StringRef getObjectType() const { return "ELF"; }
		virtual unsigned getArch() const;
		virtual StringRef getLoadName() const;

		uint64_t getNumSections() const;
		uint64_t getStringTableIndex() const;
		ELF::Elf64_Word getSymbolTableIndex(const Elf_Sym *symb) const;
		const Elf_Shdr getSection(const Elf_Sym symb) const;

		// Methods for type inquiry through isa, cast, and dyn_cast
		bool isDyldType() const { return isDyldELFObject; }
		static inline bool classof(const Binary *v) {
		return v->getType() == getELFType(target_endianness == support::little,
		is64Bits);
		}
		static inline bool classof(const ELFObjectFile *v) { return true; }
	};	};


	// Dynamic table entry tags.	// Iterate through the version definitions, and place each Elf_Verdef
	enum {	// in the VersionMap according to its index.
	DT_NULL = 0, // Marks end of dynamic array.	template<support::endianness target_endianness, bool is64Bits>
	DT_NEEDED = 1, // String table offset of needed library.	void ELFObjectFile<target_endianness, is64Bits>::
	DT_PLTRELSZ = 2, // Size of relocation entries in PLT.	LoadVersionDefs(const Elf_Shdr *sec) const {
	DT_PLTGOT = 3, // Address associated with linkage table.	unsigned vd_size = sec->sh_size; // Size of section in bytes
	DT_HASH = 4, // Address of symbolic hash table.	unsigned vd_count = sec->sh_info; // Number of Verdef entries
	DT_STRTAB = 5, // Address of dynamic string table.	const char sec_start = (const char)base() + sec->sh_offset;
	DT_SYMTAB = 6, // Address of dynamic symbol table.	const char *sec_end = sec_start + vd_size;
	DT_RELA = 7, // Address of relocation table (Rela entries)	// The first Verdef entry is at the start of the section.
	.	const char *p = sec_start;
	DT_RELASZ = 8, // Size of Rela relocation table.	for (unsigned i = 0; i < vd_count; i++) {
	DT_RELAENT = 9, // Size of a Rela relocation entry.	if (p + sizeof(Elf_Verdef) > sec_end)
	DT_STRSZ = 10, // Total size of the string table.	report_fatal_error("Section ended unexpectedly while scanning "
	DT_SYMENT = 11, // Size of a symbol table entry.	"version definitions.");
	DT_INIT = 12, // Address of initialization function.	const Elf_Verdef vd = reinterpret_cast<const Elf_Verdef >(p);
	DT_FINI = 13, // Address of termination function.	if (vd->vd_version != ELF::VER_DEF_CURRENT)
	DT_SONAME = 14, // String table offset of a shared objects na	report_fatal_error("Unexpected verdef version");
	me.	size_t index = vd->vd_ndx & ELF::VERSYM_VERSION;
	DT_RPATH = 15, // String table offset of library search path	if (index >= VersionMap.size())
	.	VersionMap.resize(index+1);
	DT_SYMBOLIC = 16, // Changes symbol resolution algorithm.	VersionMap[index] = VersionMapEntry(vd);
	DT_REL = 17, // Address of relocation table (Rel entries).	p += vd->vd_next;
	DT_RELSZ = 18, // Size of Rel relocation table.	}
	DT_RELENT = 19, // Size of a Rel relocation entry.	}
	DT_PLTREL = 20, // Type of relocation entry used for linking.
	DT_DEBUG = 21, // Reserved for debugger.	// Iterate through the versions needed section, and place each Elf_Vernaux
	DT_TEXTREL = 22, // Relocations exist for non-writable segment	// in the VersionMap according to its index.
	s.	template<support::endianness target_endianness, bool is64Bits>
	DT_JMPREL = 23, // Address of relocations associated with PLT	void ELFObjectFile<target_endianness, is64Bits>::
	.	LoadVersionNeeds(const Elf_Shdr *sec) const {
	DT_BIND_NOW = 24, // Process all relocations before execution.	unsigned vn_size = sec->sh_size; // Size of section in bytes
	DT_INIT_ARRAY = 25, // Pointer to array of initialization functio	unsigned vn_count = sec->sh_info; // Number of Verneed entries
	ns.	const char sec_start = (const char)base() + sec->sh_offset;
	DT_FINI_ARRAY = 26, // Pointer to array of termination functions.	const char *sec_end = sec_start + vn_size;
	DT_INIT_ARRAYSZ = 27, // Size of DT_INIT_ARRAY.	// The first Verneed entry is at the start of the section.
	DT_FINI_ARRAYSZ = 28, // Size of DT_FINI_ARRAY.	const char *p = sec_start;
	DT_RUNPATH = 29, // String table offset of lib search path.	for (unsigned i = 0; i < vn_count; i++) {
	DT_FLAGS = 30, // Flags.	if (p + sizeof(Elf_Verneed) > sec_end)
	DT_ENCODING = 32, // Values from here to DT_LOOS follow the rul	report_fatal_error("Section ended unexpectedly while scanning "
	es	"version needed records.");
	// for the interpretation of the d_un union.	const Elf_Verneed vn = reinterpret_cast<const Elf_Verneed >(p);
		if (vn->vn_version != ELF::VER_NEED_CURRENT)
	DT_PREINIT_ARRAY = 32, // Pointer to array of preinit functions.	report_fatal_error("Unexpected verneed version");
	DT_PREINIT_ARRAYSZ = 33, // Size of the DT_PREINIT_ARRAY array.	// Iterate through the Vernaux entries
		const char *paux = p + vn->vn_aux;
	DT_LOOS = 0x60000000, // Start of environment specific tags.	for (unsigned j = 0; j < vn->vn_cnt; j++) {
	DT_HIOS = 0x6FFFFFFF, // End of environment specific tags.	if (paux + sizeof(Elf_Vernaux) > sec_end)
	DT_LOPROC = 0x70000000, // Start of processor specific tags.	report_fatal_error("Section ended unexpected while scanning auxilia
	DT_HIPROC = 0x7FFFFFFF // End of processor specific tags.	ry "
	};	"version needed records.");
		const Elf_Vernaux vna = reinterpret_cast<const Elf_Vernaux >(paux);
	// DT_FLAGS values.	size_t index = vna->vna_other & ELF::VERSYM_VERSION;
	enum {	if (index >= VersionMap.size())
	DF_ORIGIN = 0x01, // The object may reference $ORIGIN.	VersionMap.resize(index+1);
	DF_SYMBOLIC = 0x02, // Search the shared lib before searching the exe.	VersionMap[index] = VersionMapEntry(vna);
	DF_TEXTREL = 0x04, // Relocations may modify a non-writable segment.	paux += vna->vna_next;
	DF_BIND_NOW = 0x08, // Process all relocations on load.	}
	DF_STATIC_TLS = 0x10 // Reject attempts to load dynamically.	p += vn->vn_next;
	};	}
		}

		template<support::endianness target_endianness, bool is64Bits>
		void ELFObjectFile<target_endianness, is64Bits>::LoadVersionMap() const {
		// If there is no dynamic symtab or version table, there is nothing to do
		.
		if (SymbolTableSections[0] == NULL \|\| dot_gnu_version_sec == NULL)
		return;

		// Has the VersionMap already been loaded?
		if (VersionMap.size() > 0)
		return;

		// The first two version indexes are reserved.
		// Index 0 is LOCAL, index 1 is GLOBAL.
		VersionMap.push_back(VersionMapEntry());
		VersionMap.push_back(VersionMapEntry());

		if (dot_gnu_version_d_sec)
		LoadVersionDefs(dot_gnu_version_d_sec);

		if (dot_gnu_version_r_sec)
		LoadVersionNeeds(dot_gnu_version_r_sec);
		}

		template<support::endianness target_endianness, bool is64Bits>
		void ELFObjectFile<target_endianness, is64Bits>
		::validateSymbol(DataRefImpl Symb) const {
		const Elf_Sym *symb = getSymbol(Symb);
		const Elf_Shdr *SymbolTableSection = SymbolTableSections[Symb.d.b];
		// FIXME: We really need to do proper error handling in the case of an in
		valid
		// input file. Because we don't use exceptions, I think we'll just
		pass
		// an error object around.
		if (!( symb
		&& SymbolTableSection
		&& symb >= (const Elf_Sym*)(base()
		+ SymbolTableSection->sh_offset)
		&& symb < (const Elf_Sym*)(base()
		+ SymbolTableSection->sh_offset
		+ SymbolTableSection->sh_size)))
		// FIXME: Proper error handling.
		report_fatal_error("Symb must point to a valid symbol!");
		}

		template<support::endianness target_endianness, bool is64Bits>
		error_code ELFObjectFile<target_endianness, is64Bits>
		::getSymbolNext(DataRefImpl Symb,
		SymbolRef &Result) const {
		validateSymbol(Symb);
		const Elf_Shdr *SymbolTableSection = SymbolTableSections[Symb.d.b];

		++Symb.d.a;
		// Check to see if we are at the end of this symbol table.
		if (Symb.d.a >= SymbolTableSection->getEntityCount()) {
		// We are at the end. If there are other symbol tables, jump to them.
		// If the symbol table is .dynsym, we are iterating dynamic symbols,
		// and there is only one table of these.
		if (Symb.d.b != 0) {
		++Symb.d.b;
		Symb.d.a = 1; // The 0th symbol in ELF is fake.
		}
		// Otherwise return the terminator.
		if (Symb.d.b == 0 \|\| Symb.d.b >= SymbolTableSections.size()) {
		Symb.d.a = std::numeric_limits<uint32_t>::max();
		Symb.d.b = std::numeric_limits<uint32_t>::max();
		}
		}

		Result = SymbolRef(Symb, this);
		return object_error::success;
		}

		template<support::endianness target_endianness, bool is64Bits>
		error_code ELFObjectFile<target_endianness, is64Bits>
		::getSymbolName(DataRefImpl Symb,
		StringRef &Result) const {
		validateSymbol(Symb);
		const Elf_Sym *symb = getSymbol(Symb);
		return getSymbolName(SymbolTableSections[Symb.d.b], symb, Result);
		}

		template<support::endianness target_endianness, bool is64Bits>
		error_code ELFObjectFile<target_endianness, is64Bits>
		::getSymbolVersion(SymbolRef SymRef,
		StringRef &Version,
		bool &IsDefault) const {
		DataRefImpl Symb = SymRef.getRawDataRefImpl();
		validateSymbol(Symb);
		const Elf_Sym *symb = getSymbol(Symb);
		return getSymbolVersion(SymbolTableSections[Symb.d.b], symb,
		Version, IsDefault);
		}

		template<support::endianness target_endianness, bool is64Bits>
		ELF::Elf64_Word ELFObjectFile<target_endianness, is64Bits>
		::getSymbolTableIndex(const Elf_Sym *symb) const {
		if (symb->st_shndx == ELF::SHN_XINDEX)
		return ExtendedSymbolTable.lookup(symb);
		return symb->st_shndx;
		}

		template<support::endianness target_endianness, bool is64Bits>
		const typename ELFObjectFile<target_endianness, is64Bits>::Elf_Shdr *
		ELFObjectFile<target_endianness, is64Bits>
		::getSection(const Elf_Sym *symb) const {
		if (symb->st_shndx == ELF::SHN_XINDEX)
		return getSection(ExtendedSymbolTable.lookup(symb));
		if (symb->st_shndx >= ELF::SHN_LORESERVE)
		return 0;
		return getSection(symb->st_shndx);
		}

		template<support::endianness target_endianness, bool is64Bits>
		error_code ELFObjectFile<target_endianness, is64Bits>
		::getSymbolFileOffset(DataRefImpl Symb,
		uint64_t &Result) const {
		validateSymbol(Symb);
		const Elf_Sym *symb = getSymbol(Symb);
		const Elf_Shdr *Section;
		switch (getSymbolTableIndex(symb)) {
		case ELF::SHN_COMMON:
		// Unintialized symbols have no offset in the object file
		case ELF::SHN_UNDEF:
		Result = UnknownAddressOrSize;
		return object_error::success;
		case ELF::SHN_ABS:
		Result = symb->st_value;
		return object_error::success;
		default: Section = getSection(symb);
		}

		switch (symb->getType()) {
		case ELF::STT_SECTION:
		Result = Section ? Section->sh_addr : UnknownAddressOrSize;
		return object_error::success;
		case ELF::STT_FUNC:
		case ELF::STT_OBJECT:
		case ELF::STT_NOTYPE:
		Result = symb->st_value +
		(Section ? Section->sh_offset : 0);
		return object_error::success;
		default:
		Result = UnknownAddressOrSize;
		return object_error::success;
		}
		}

		template<support::endianness target_endianness, bool is64Bits>
		error_code ELFObjectFile<target_endianness, is64Bits>
		::getSymbolAddress(DataRefImpl Symb,
		uint64_t &Result) const {
		validateSymbol(Symb);
		const Elf_Sym *symb = getSymbol(Symb);
		const Elf_Shdr *Section;
		switch (getSymbolTableIndex(symb)) {
		case ELF::SHN_COMMON:
		case ELF::SHN_UNDEF:
		Result = UnknownAddressOrSize;
		return object_error::success;
		case ELF::SHN_ABS:
		Result = symb->st_value;
		return object_error::success;
		default: Section = getSection(symb);
		}

		switch (symb->getType()) {
		case ELF::STT_SECTION:
		Result = Section ? Section->sh_addr : UnknownAddressOrSize;
		return object_error::success;
		case ELF::STT_FUNC:
		case ELF::STT_OBJECT:
		case ELF::STT_NOTYPE:
		Result = symb->st_value + (Section ? Section->sh_addr : 0);
		return object_error::success;
		default:
		Result = UnknownAddressOrSize;
		return object_error::success;
		}
		}

		template<support::endianness target_endianness, bool is64Bits>
		error_code ELFObjectFile<target_endianness, is64Bits>
		::getSymbolSize(DataRefImpl Symb,
		uint64_t &Result) const {
		validateSymbol(Symb);
		const Elf_Sym *symb = getSymbol(Symb);
		if (symb->st_size == 0)
		Result = UnknownAddressOrSize;
		Result = symb->st_size;
		return object_error::success;
		}

		template<support::endianness target_endianness, bool is64Bits>
		error_code ELFObjectFile<target_endianness, is64Bits>
		::getSymbolNMTypeChar(DataRefImpl Symb,
		char &Result) const {
		validateSymbol(Symb);
		const Elf_Sym *symb = getSymbol(Symb);
		const Elf_Shdr *Section = getSection(symb);

		char ret = '?';

		if (Section) {
		switch (Section->sh_type) {
		case ELF::SHT_PROGBITS:
		case ELF::SHT_DYNAMIC:
		switch (Section->sh_flags) {
		case (ELF::SHF_ALLOC \| ELF::SHF_EXECINSTR):
		ret = 't'; break;
		case (ELF::SHF_ALLOC \| ELF::SHF_WRITE):
		ret = 'd'; break;
		case ELF::SHF_ALLOC:
		case (ELF::SHF_ALLOC \| ELF::SHF_MERGE):
		case (ELF::SHF_ALLOC \| ELF::SHF_MERGE \| ELF::SHF_STRINGS):
		ret = 'r'; break;
		}
		break;
		case ELF::SHT_NOBITS: ret = 'b';
		}
		}

		switch (getSymbolTableIndex(symb)) {
		case ELF::SHN_UNDEF:
		if (ret == '?')
		ret = 'U';
		break;
		case ELF::SHN_ABS: ret = 'a'; break;
		case ELF::SHN_COMMON: ret = 'c'; break;
		}

		switch (symb->getBinding()) {
		case ELF::STB_GLOBAL: ret = ::toupper(ret); break;
		case ELF::STB_WEAK:
		if (getSymbolTableIndex(symb) == ELF::SHN_UNDEF)
		ret = 'w';
		else
		if (symb->getType() == ELF::STT_OBJECT)
		ret = 'V';
		else
		ret = 'W';
		}

		if (ret == '?' && symb->getType() == ELF::STT_SECTION) {
		StringRef name;
		if (error_code ec = getSymbolName(Symb, name))
		return ec;
		Result = StringSwitch<char>(name)
		.StartsWith(".debug", 'N')
		.StartsWith(".note", 'n')
		.Default('?');
		return object_error::success;
		}

		Result = ret;
		return object_error::success;
		}

		template<support::endianness target_endianness, bool is64Bits>
		error_code ELFObjectFile<target_endianness, is64Bits>
		::getSymbolType(DataRefImpl Symb,
		SymbolRef::Type &Result) const {
		validateSymbol(Symb);
		const Elf_Sym *symb = getSymbol(Symb);

		switch (symb->getType()) {
		case ELF::STT_NOTYPE:
		Result = SymbolRef::ST_Unknown;
		break;
		case ELF::STT_SECTION:
		Result = SymbolRef::ST_Debug;
		break;
		case ELF::STT_FILE:
		Result = SymbolRef::ST_File;
		break;
		case ELF::STT_FUNC:
		Result = SymbolRef::ST_Function;
		break;
		case ELF::STT_OBJECT:
		case ELF::STT_COMMON:
		case ELF::STT_TLS:
		Result = SymbolRef::ST_Data;
		break;
		default:
		Result = SymbolRef::ST_Other;
		break;
		}
		return object_error::success;
		}

		template<support::endianness target_endianness, bool is64Bits>
		error_code ELFObjectFile<target_endianness, is64Bits>
		::getSymbolFlags(DataRefImpl Symb,
		uint32_t &Result) const {
		validateSymbol(Symb);
		const Elf_Sym *symb = getSymbol(Symb);

		Result = SymbolRef::SF_None;

		if (symb->getBinding() != ELF::STB_LOCAL)
		Result \|= SymbolRef::SF_Global;

		if (symb->getBinding() == ELF::STB_WEAK)
		Result \|= SymbolRef::SF_Weak;

		if (symb->st_shndx == ELF::SHN_ABS)
		Result \|= SymbolRef::SF_Absolute;

		if (symb->getType() == ELF::STT_FILE \|\|
		symb->getType() == ELF::STT_SECTION)
		Result \|= SymbolRef::SF_FormatSpecific;

		if (getSymbolTableIndex(symb) == ELF::SHN_UNDEF)
		Result \|= SymbolRef::SF_Undefined;

		if (symb->getType() == ELF::STT_COMMON \|\|
		getSymbolTableIndex(symb) == ELF::SHN_COMMON)
		Result \|= SymbolRef::SF_Common;

		if (symb->getType() == ELF::STT_TLS)
		Result \|= SymbolRef::SF_ThreadLocal;

		return object_error::success;
		}

		template<support::endianness target_endianness, bool is64Bits>
		error_code ELFObjectFile<target_endianness, is64Bits>
		::getSymbolSection(DataRefImpl Symb,
		section_iterator &Res) const {
		validateSymbol(Symb);
		const Elf_Sym *symb = getSymbol(Symb);
		const Elf_Shdr *sec = getSection(symb);
		if (!sec)
		Res = end_sections();
		else {
		DataRefImpl Sec;
		Sec.p = reinterpret_cast<intptr_t>(sec);
		Res = section_iterator(SectionRef(Sec, this));
		}
		return object_error::success;
		}

		template<support::endianness target_endianness, bool is64Bits>
		error_code ELFObjectFile<target_endianness, is64Bits>
		::getSectionNext(DataRefImpl Sec, SectionRef &Resul
		t) const {
		const uint8_t sec = reinterpret_cast<const uint8_t >(Sec.p);
		sec += Header->e_shentsize;
		Sec.p = reinterpret_cast<intptr_t>(sec);
		Result = SectionRef(Sec, this);
		return object_error::success;
		}

		template<support::endianness target_endianness, bool is64Bits>
		error_code ELFObjectFile<target_endianness, is64Bits>
		::getSectionName(DataRefImpl Sec,
		StringRef &Result) const {
		const Elf_Shdr sec = reinterpret_cast<const Elf_Shdr >(Sec.p);
		Result = StringRef(getString(dot_shstrtab_sec, sec->sh_name));
		return object_error::success;
		}

		template<support::endianness target_endianness, bool is64Bits>
		error_code ELFObjectFile<target_endianness, is64Bits>
		::getSectionAddress(DataRefImpl Sec,
		uint64_t &Result) const {
		const Elf_Shdr sec = reinterpret_cast<const Elf_Shdr >(Sec.p);
		Result = sec->sh_addr;
		return object_error::success;
		}

		template<support::endianness target_endianness, bool is64Bits>
		error_code ELFObjectFile<target_endianness, is64Bits>
		::getSectionSize(DataRefImpl Sec,
		uint64_t &Result) const {
		const Elf_Shdr sec = reinterpret_cast<const Elf_Shdr >(Sec.p);
		Result = sec->sh_size;
		return object_error::success;
		}

		template<support::endianness target_endianness, bool is64Bits>
		error_code ELFObjectFile<target_endianness, is64Bits>
		::getSectionContents(DataRefImpl Sec,
		StringRef &Result) const {
		const Elf_Shdr sec = reinterpret_cast<const Elf_Shdr >(Sec.p);
		const char start = (const char)base() + sec->sh_offset;
		Result = StringRef(start, sec->sh_size);
		return object_error::success;
		}

		template<support::endianness target_endianness, bool is64Bits>
		error_code ELFObjectFile<target_endianness, is64Bits>
		::getSectionAlignment(DataRefImpl Sec,
		uint64_t &Result) const {
		const Elf_Shdr sec = reinterpret_cast<const Elf_Shdr >(Sec.p);
		Result = sec->sh_addralign;
		return object_error::success;
		}

		template<support::endianness target_endianness, bool is64Bits>
		error_code ELFObjectFile<target_endianness, is64Bits>
		::isSectionText(DataRefImpl Sec,
		bool &Result) const {
		const Elf_Shdr sec = reinterpret_cast<const Elf_Shdr >(Sec.p);
		if (sec->sh_flags & ELF::SHF_EXECINSTR)
		Result = true;
		else
		Result = false;
		return object_error::success;
		}

		template<support::endianness target_endianness, bool is64Bits>
		error_code ELFObjectFile<target_endianness, is64Bits>
		::isSectionData(DataRefImpl Sec,
		bool &Result) const {
		const Elf_Shdr sec = reinterpret_cast<const Elf_Shdr >(Sec.p);
		if (sec->sh_flags & (ELF::SHF_ALLOC \| ELF::SHF_WRITE)
		&& sec->sh_type == ELF::SHT_PROGBITS)
		Result = true;
		else
		Result = false;
		return object_error::success;
		}

		template<support::endianness target_endianness, bool is64Bits>
		error_code ELFObjectFile<target_endianness, is64Bits>
		::isSectionBSS(DataRefImpl Sec,
		bool &Result) const {
		const Elf_Shdr sec = reinterpret_cast<const Elf_Shdr >(Sec.p);
		if (sec->sh_flags & (ELF::SHF_ALLOC \| ELF::SHF_WRITE)
		&& sec->sh_type == ELF::SHT_NOBITS)
		Result = true;
		else
		Result = false;
		return object_error::success;
		}

		template<support::endianness target_endianness, bool is64Bits>
		error_code ELFObjectFile<target_endianness, is64Bits>
		::isSectionRequiredForExecution(DataRefImpl Sec,
		bool &Result) const
		{
		const Elf_Shdr sec = reinterpret_cast<const Elf_Shdr >(Sec.p);
		if (sec->sh_flags & ELF::SHF_ALLOC)
		Result = true;
		else
		Result = false;
		return object_error::success;
		}

		template<support::endianness target_endianness, bool is64Bits>
		error_code ELFObjectFile<target_endianness, is64Bits>
		::isSectionVirtual(DataRefImpl Sec,
		bool &Result) const {
		const Elf_Shdr sec = reinterpret_cast<const Elf_Shdr >(Sec.p);
		if (sec->sh_type == ELF::SHT_NOBITS)
		Result = true;
		else
		Result = false;
		return object_error::success;
		}

		template<support::endianness target_endianness, bool is64Bits>
		error_code ELFObjectFile<target_endianness, is64Bits>::isSectionZeroInit(Da
		taRefImpl Sec,
		bool &Result) const {
		const Elf_Shdr sec = reinterpret_cast<const Elf_Shdr >(Sec.p);
		// For ELF, all zero-init sections are virtual (that is, they occupy no s
		pace
		// in the object image) and vice versa.
		if (sec->sh_flags & ELF::SHT_NOBITS)
		Result = true;
		else
		Result = false;
		return object_error::success;
		}

		template<support::endianness target_endianness, bool is64Bits>
		error_code ELFObjectFile<target_endianness, is64Bits>
		::sectionContainsSymbol(DataRefImpl Sec,
		DataRefImpl Symb,
		bool &Result) const {
		// FIXME: Unimplemented.
		Result = false;
		return object_error::success;
		}

		template<support::endianness target_endianness, bool is64Bits>
		relocation_iterator ELFObjectFile<target_endianness, is64Bits>
		::getSectionRelBegin(DataRefImpl Sec) cons
		t {
		DataRefImpl RelData;
		const Elf_Shdr sec = reinterpret_cast<const Elf_Shdr >(Sec.p);
		typename RelocMap_t::const_iterator ittr = SectionRelocMap.find(sec);
		if (sec != 0 && ittr != SectionRelocMap.end()) {
		RelData.w.a = getSection(ittr->second[0])->sh_info;
		RelData.w.b = ittr->second[0];
		RelData.w.c = 0;
		}
		return relocation_iterator(RelocationRef(RelData, this));
		}

		template<support::endianness target_endianness, bool is64Bits>
		relocation_iterator ELFObjectFile<target_endianness, is64Bits>
		::getSectionRelEnd(DataRefImpl Sec) const
		{
		DataRefImpl RelData;
		const Elf_Shdr sec = reinterpret_cast<const Elf_Shdr >(Sec.p);
		typename RelocMap_t::const_iterator ittr = SectionRelocMap.find(sec);
		if (sec != 0 && ittr != SectionRelocMap.end()) {
		// Get the index of the last relocation section for this section.
		std::size_t relocsecindex = ittr->second[ittr->second.size() - 1];
		const Elf_Shdr *relocsec = getSection(relocsecindex);
		RelData.w.a = relocsec->sh_info;
		RelData.w.b = relocsecindex;
		RelData.w.c = relocsec->sh_size / relocsec->sh_entsize;
		}
		return relocation_iterator(RelocationRef(RelData, this));
		}

		// Relocations
		template<support::endianness target_endianness, bool is64Bits>
		error_code ELFObjectFile<target_endianness, is64Bits>
		::getRelocationNext(DataRefImpl Rel,
		RelocationRef &Result) const {
		++Rel.w.c;
		const Elf_Shdr *relocsec = getSection(Rel.w.b);
		if (Rel.w.c >= (relocsec->sh_size / relocsec->sh_entsize)) {
		// We have reached the end of the relocations for this section. See if
		there
		// is another relocation section.
		typename RelocMap_t::mapped_type relocseclist =
		SectionRelocMap.lookup(getSection(Rel.w.a));

		// Do a binary search for the current reloc section index (which must b
		e
		// present). Then get the next one.
		typename RelocMap_t::mapped_type::const_iterator loc =
		std::lower_bound(relocseclist.begin(), relocseclist.end(), Rel.w.b);
		++loc;

		// If there is no next one, don't do anything. The ++Rel.w.c above sets
		Rel
		// to the end iterator.
		if (loc != relocseclist.end()) {
		Rel.w.b = *loc;
		Rel.w.a = 0;
		}
		}
		Result = RelocationRef(Rel, this);
		return object_error::success;
		}

		template<support::endianness target_endianness, bool is64Bits>
		error_code ELFObjectFile<target_endianness, is64Bits>
		::getRelocationSymbol(DataRefImpl Rel,
		SymbolRef &Result) const {
		uint32_t symbolIdx;
		const Elf_Shdr *sec = getSection(Rel.w.b);
		switch (sec->sh_type) {
		default :
		report_fatal_error("Invalid section type in Rel!");
		case ELF::SHT_REL : {
		symbolIdx = getRel(Rel)->getSymbol();
		break;
		}
		case ELF::SHT_RELA : {
		symbolIdx = getRela(Rel)->getSymbol();
		break;
		}
		}
		DataRefImpl SymbolData;
		IndexMap_t::const_iterator it = SymbolTableSectionsIndexMap.find(sec->sh_
		link);
		if (it == SymbolTableSectionsIndexMap.end())
		report_fatal_error("Relocation symbol table not found!");
		SymbolData.d.a = symbolIdx;
		SymbolData.d.b = it->second;
		Result = SymbolRef(SymbolData, this);
		return object_error::success;
		}

		template<support::endianness target_endianness, bool is64Bits>
		error_code ELFObjectFile<target_endianness, is64Bits>
		::getRelocationAddress(DataRefImpl Rel,
		uint64_t &Result) const {
		uint64_t offset;
		const Elf_Shdr *sec = getSection(Rel.w.b);
		switch (sec->sh_type) {
		default :
		report_fatal_error("Invalid section type in Rel!");
		case ELF::SHT_REL : {
		offset = getRel(Rel)->r_offset;
		break;
		}
		case ELF::SHT_RELA : {
		offset = getRela(Rel)->r_offset;
		break;
		}
		}

		Result = offset;
		return object_error::success;
		}

		template<support::endianness target_endianness, bool is64Bits>
		error_code ELFObjectFile<target_endianness, is64Bits>
		::getRelocationOffset(DataRefImpl Rel,
		uint64_t &Result) const {
		uint64_t offset;
		const Elf_Shdr *sec = getSection(Rel.w.b);
		switch (sec->sh_type) {
		default :
		report_fatal_error("Invalid section type in Rel!");
		case ELF::SHT_REL : {
		offset = getRel(Rel)->r_offset;
		break;
		}
		case ELF::SHT_RELA : {
		offset = getRela(Rel)->r_offset;
		break;
		}
		}

		Result = offset - sec->sh_addr;
		return object_error::success;
		}

		template<support::endianness target_endianness, bool is64Bits>
		error_code ELFObjectFile<target_endianness, is64Bits>
		::getRelocationType(DataRefImpl Rel,
		uint64_t &Result) const {
		const Elf_Shdr *sec = getSection(Rel.w.b);
		switch (sec->sh_type) {
		default :
		report_fatal_error("Invalid section type in Rel!");
		case ELF::SHT_REL : {
		Result = getRel(Rel)->getType();
		break;
		}
		case ELF::SHT_RELA : {
		Result = getRela(Rel)->getType();
		break;
		}
		}
		return object_error::success;
		}

		#define LLVM_ELF_SWITCH_RELOC_TYPE_NAME(enum) \
		case ELF::enum: res = #enum; break;

		template<support::endianness target_endianness, bool is64Bits>
		error_code ELFObjectFile<target_endianness, is64Bits>
		::getRelocationTypeName(DataRefImpl Rel,
		SmallVectorImpl<char> &Result) co
		nst {
		const Elf_Shdr *sec = getSection(Rel.w.b);
		uint8_t type;
		StringRef res;
		switch (sec->sh_type) {
		default :
		return object_error::parse_failed;
		case ELF::SHT_REL : {
		type = getRel(Rel)->getType();
		break;
		}
		case ELF::SHT_RELA : {
		type = getRela(Rel)->getType();
		break;
		}
		}
		switch (Header->e_machine) {
		case ELF::EM_X86_64:
		switch (type) {
		LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_X86_64_NONE);
		LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_X86_64_64);
		LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_X86_64_PC32);
		LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_X86_64_GOT32);
		LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_X86_64_PLT32);
		LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_X86_64_COPY);
		LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_X86_64_GLOB_DAT);
		LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_X86_64_JUMP_SLOT);
		LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_X86_64_RELATIVE);
		LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_X86_64_GOTPCREL);
		LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_X86_64_32);
		LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_X86_64_32S);
		LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_X86_64_16);
		LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_X86_64_PC16);
		LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_X86_64_8);
		LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_X86_64_PC8);
		LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_X86_64_DTPMOD64);
		LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_X86_64_DTPOFF64);
		LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_X86_64_TPOFF64);
		LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_X86_64_TLSGD);
		LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_X86_64_TLSLD);
		LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_X86_64_DTPOFF32);
		LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_X86_64_GOTTPOFF);
		LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_X86_64_TPOFF32);
		LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_X86_64_PC64);
		LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_X86_64_GOTOFF64);
		LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_X86_64_GOTPC32);
		LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_X86_64_SIZE32);
		LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_X86_64_SIZE64);
		LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_X86_64_GOTPC32_TLSDESC);
		LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_X86_64_TLSDESC_CALL);
		LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_X86_64_TLSDESC);
		default:
		res = "Unknown";
		}
		break;
		case ELF::EM_386:
		switch (type) {
		LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_NONE);
		LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_32);
		LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_PC32);
		LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_GOT32);
		LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_PLT32);
		LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_COPY);
		LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_GLOB_DAT);
		LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_JUMP_SLOT);
		LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_RELATIVE);
		LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_GOTOFF);
		LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_GOTPC);
		LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_32PLT);
		LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_TLS_TPOFF);
		LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_TLS_IE);
		LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_TLS_GOTIE);
		LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_TLS_LE);
		LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_TLS_GD);
		LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_TLS_LDM);
		LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_16);
		LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_PC16);
		LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_8);
		LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_PC8);
		LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_TLS_GD_32);
		LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_TLS_GD_PUSH);
		LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_TLS_GD_CALL);
		LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_TLS_GD_POP);
		LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_TLS_LDM_32);
		LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_TLS_LDM_PUSH);
		LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_TLS_LDM_CALL);
		LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_TLS_LDM_POP);
		LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_TLS_LDO_32);
		LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_TLS_IE_32);
		LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_TLS_LE_32);
		LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_TLS_DTPMOD32);
		LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_TLS_DTPOFF32);
		LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_TLS_TPOFF32);
		LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_TLS_GOTDESC);
		LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_TLS_DESC_CALL);
		LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_TLS_DESC);
		LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_IRELATIVE);
		default:
		res = "Unknown";
		}
		break;
		default:
		res = "Unknown";
		}
		Result.append(res.begin(), res.end());
		return object_error::success;
		}

		#undef LLVM_ELF_SWITCH_RELOC_TYPE_NAME

		template<support::endianness target_endianness, bool is64Bits>
		error_code ELFObjectFile<target_endianness, is64Bits>
		::getRelocationAdditionalInfo(DataRefImpl Rel,
		int64_t &Result) cons
		t {
		const Elf_Shdr *sec = getSection(Rel.w.b);
		switch (sec->sh_type) {
		default :
		report_fatal_error("Invalid section type in Rel!");
		case ELF::SHT_REL : {
		Result = 0;
		return object_error::success;
		}
		case ELF::SHT_RELA : {
		Result = getRela(Rel)->r_addend;
		return object_error::success;
		}
		}
		}

		template<support::endianness target_endianness, bool is64Bits>
		error_code ELFObjectFile<target_endianness, is64Bits>
		::getRelocationValueString(DataRefImpl Rel,
		SmallVectorImpl<char> &Result) co
		nst {
		const Elf_Shdr *sec = getSection(Rel.w.b);
		uint8_t type;
		StringRef res;
		int64_t addend = 0;
		uint16_t symbol_index = 0;
		switch (sec->sh_type) {
		default :
		return object_error::parse_failed;
		case ELF::SHT_REL : {
		type = getRel(Rel)->getType();
		symbol_index = getRel(Rel)->getSymbol();
		// TODO: Read implicit addend from section data.
		break;
		}
		case ELF::SHT_RELA : {
		type = getRela(Rel)->getType();
		symbol_index = getRela(Rel)->getSymbol();
		addend = getRela(Rel)->r_addend;
		break;
		}
		}
		const Elf_Sym *symb = getEntry<Elf_Sym>(sec->sh_link, symbol_index);
		StringRef symname;
		if (error_code ec = getSymbolName(getSection(sec->sh_link), symb, symname
		))
		return ec;
		switch (Header->e_machine) {
		case ELF::EM_X86_64:
		switch (type) {
		case ELF::R_X86_64_32S:
		res = symname;
		break;
		case ELF::R_X86_64_PC32: {
		std::string fmtbuf;
		raw_string_ostream fmt(fmtbuf);
		fmt << symname << (addend < 0 ? "" : "+") << addend << "-P";
		fmt.flush();
		Result.append(fmtbuf.begin(), fmtbuf.end());
		}
		break;
		default:
		res = "Unknown";
		}
		break;
		default:
		res = "Unknown";
		}
		if (Result.empty())
		Result.append(res.begin(), res.end());
		return object_error::success;
		}

		// Verify that the last byte in the string table in a null.
		template<support::endianness target_endianness, bool is64Bits>
		void ELFObjectFile<target_endianness, is64Bits>
		::VerifyStrTab(const Elf_Shdr *sh) const {
		const char strtab = (const char)base() + sh->sh_offset;
		if (strtab[sh->sh_size - 1] != 0)
		// FIXME: Proper error handling.
		report_fatal_error("String table must end with a null terminator!");
		}

		template<support::endianness target_endianness, bool is64Bits>
		ELFObjectFile<target_endianness, is64Bits>::ELFObjectFile(MemoryBuffer *Obj
		ect
		, error_code &ec)
		: ObjectFile(getELFType(target_endianness == support::little, is64Bits),
		Object, ec)
		, isDyldELFObject(false)
		, SectionHeaderTable(0)
		, dot_shstrtab_sec(0)
		, dot_strtab_sec(0)
		, dot_dynstr_sec(0)
		, dot_dynamic_sec(0)
		, dot_gnu_version_sec(0)
		, dot_gnu_version_r_sec(0)
		, dot_gnu_version_d_sec(0)
		, dt_soname(0)
		{

		const uint64_t FileSize = Data->getBufferSize();

		if (sizeof(Elf_Ehdr) > FileSize)
		// FIXME: Proper error handling.
		report_fatal_error("File too short!");

		Header = reinterpret_cast<const Elf_Ehdr *>(base());

		if (Header->e_shoff == 0)
		return;

		const uint64_t SectionTableOffset = Header->e_shoff;

		if (SectionTableOffset + sizeof(Elf_Shdr) > FileSize)
		// FIXME: Proper error handling.
		report_fatal_error("Section header table goes past end of file!");

		// The getNumSections() call below depends on SectionHeaderTable being se
		t.
		SectionHeaderTable =
		reinterpret_cast<const Elf_Shdr *>(base() + SectionTableOffset);
		const uint64_t SectionTableSize = getNumSections() * Header->e_shentsize;

		if (SectionTableOffset + SectionTableSize > FileSize)
		// FIXME: Proper error handling.
		report_fatal_error("Section table goes past end of file!");

		// To find the symbol tables we walk the section table to find SHT_SYMTAB
		.
		const Elf_Shdr* SymbolTableSectionHeaderIndex = 0;
		const Elf_Shdr* sh = SectionHeaderTable;

		// Reserve SymbolTableSections[0] for .dynsym
		SymbolTableSections.push_back(NULL);

		for (uint64_t i = 0, e = getNumSections(); i != e; ++i) {
		switch (sh->sh_type) {
		case ELF::SHT_SYMTAB_SHNDX: {
		if (SymbolTableSectionHeaderIndex)
		// FIXME: Proper error handling.
		report_fatal_error("More than one .symtab_shndx!");
		SymbolTableSectionHeaderIndex = sh;
		break;
		}
		case ELF::SHT_SYMTAB: {
		SymbolTableSectionsIndexMap[i] = SymbolTableSections.size();
		SymbolTableSections.push_back(sh);
		break;
		}
		case ELF::SHT_DYNSYM: {
		if (SymbolTableSections[0] != NULL)
		// FIXME: Proper error handling.
		report_fatal_error("More than one .dynsym!");
		SymbolTableSectionsIndexMap[i] = 0;
		SymbolTableSections[0] = sh;
		break;
		}
		case ELF::SHT_REL:
		case ELF::SHT_RELA: {
		SectionRelocMap[getSection(sh->sh_info)].push_back(i);
		break;
		}
		case ELF::SHT_DYNAMIC: {
		if (dot_dynamic_sec != NULL)
		// FIXME: Proper error handling.
		report_fatal_error("More than one .dynamic!");
		dot_dynamic_sec = sh;
		break;
		}
		case ELF::SHT_GNU_versym: {
		if (dot_gnu_version_sec != NULL)
		// FIXME: Proper error handling.
		report_fatal_error("More than one .gnu.version section!");
		dot_gnu_version_sec = sh;
		break;
		}
		case ELF::SHT_GNU_verdef: {
		if (dot_gnu_version_d_sec != NULL)
		// FIXME: Proper error handling.
		report_fatal_error("More than one .gnu.version_d section!");
		dot_gnu_version_d_sec = sh;
		break;
		}
		case ELF::SHT_GNU_verneed: {
		if (dot_gnu_version_r_sec != NULL)
		// FIXME: Proper error handling.
		report_fatal_error("More than one .gnu.version_r section!");
		dot_gnu_version_r_sec = sh;
		break;
		}
		}
		++sh;
		}

		// Sort section relocation lists by index.
		for (typename RelocMap_t::iterator i = SectionRelocMap.begin(),
		e = SectionRelocMap.end(); i != e; ++i
		) {
		std::sort(i->second.begin(), i->second.end());
		}

		// Get string table sections.
		dot_shstrtab_sec = getSection(getStringTableIndex());
		if (dot_shstrtab_sec) {
		// Verify that the last byte in the string table in a null.
		VerifyStrTab(dot_shstrtab_sec);
		}

		// Merge this into the above loop.
		for (const char i = reinterpret_cast<const char >(SectionHeaderTable),
		e = i + getNumSections() Header->e_shentsize;
		i != e; i += Header->e_shentsize) {
		const Elf_Shdr sh = reinterpret_cast<const Elf_Shdr>(i);
		if (sh->sh_type == ELF::SHT_STRTAB) {
		StringRef SectionName(getString(dot_shstrtab_sec, sh->sh_name));
		if (SectionName == ".strtab") {
		if (dot_strtab_sec != 0)
		// FIXME: Proper error handling.
		report_fatal_error("Already found section named .strtab!");
		dot_strtab_sec = sh;
		VerifyStrTab(dot_strtab_sec);
		} else if (SectionName == ".dynstr") {
		if (dot_dynstr_sec != 0)
		// FIXME: Proper error handling.
		report_fatal_error("Already found section named .dynstr!");
		dot_dynstr_sec = sh;
		VerifyStrTab(dot_dynstr_sec);
		}
		}
		}

		// Build symbol name side-mapping if there is one.
		if (SymbolTableSectionHeaderIndex) {
		const Elf_Word ShndxTable = reinterpret_cast<const Elf_Word>(base() +
		SymbolTableSectionHeaderIndex->sh_off
		set);
		error_code ec;
		for (symbol_iterator si = begin_symbols(),
		se = end_symbols(); si != se; si.increment(ec)) {
		if (ec)
		report_fatal_error("Fewer extended symbol table entries than symbol
		s!");
		if (*ShndxTable != ELF::SHN_UNDEF)
		ExtendedSymbolTable[getSymbol(si->getRawDataRefImpl())] = *ShndxTab
		le;
		++ShndxTable;
		}
		}
		}

		template<support::endianness target_endianness, bool is64Bits>
		symbol_iterator ELFObjectFile<target_endianness, is64Bits>
		::begin_symbols() const {
		DataRefImpl SymbolData;
		if (SymbolTableSections.size() <= 1) {
		SymbolData.d.a = std::numeric_limits<uint32_t>::max();
		SymbolData.d.b = std::numeric_limits<uint32_t>::max();
		} else {
		SymbolData.d.a = 1; // The 0th symbol in ELF is fake.
		SymbolData.d.b = 1; // The 0th table is .dynsym
		}
		return symbol_iterator(SymbolRef(SymbolData, this));
		}

		template<support::endianness target_endianness, bool is64Bits>
		symbol_iterator ELFObjectFile<target_endianness, is64Bits>
		::end_symbols() const {
		DataRefImpl SymbolData;
		SymbolData.d.a = std::numeric_limits<uint32_t>::max();
		SymbolData.d.b = std::numeric_limits<uint32_t>::max();
		return symbol_iterator(SymbolRef(SymbolData, this));
		}

		template<support::endianness target_endianness, bool is64Bits>
		symbol_iterator ELFObjectFile<target_endianness, is64Bits>
		::begin_dynamic_symbols() const {
		DataRefImpl SymbolData;
		if (SymbolTableSections[0] == NULL) {
		SymbolData.d.a = std::numeric_limits<uint32_t>::max();
		SymbolData.d.b = std::numeric_limits<uint32_t>::max();
		} else {
		SymbolData.d.a = 1; // The 0th symbol in ELF is fake.
		SymbolData.d.b = 0; // The 0th table is .dynsym
		}
		return symbol_iterator(SymbolRef(SymbolData, this));
		}

		template<support::endianness target_endianness, bool is64Bits>
		symbol_iterator ELFObjectFile<target_endianness, is64Bits>
		::end_dynamic_symbols() const {
		DataRefImpl SymbolData;
		SymbolData.d.a = std::numeric_limits<uint32_t>::max();
		SymbolData.d.b = std::numeric_limits<uint32_t>::max();
		return symbol_iterator(SymbolRef(SymbolData, this));
		}

		template<support::endianness target_endianness, bool is64Bits>
		section_iterator ELFObjectFile<target_endianness, is64Bits>
		::begin_sections() const {
		DataRefImpl ret;
		ret.p = reinterpret_cast<intptr_t>(base() + Header->e_shoff);
		return section_iterator(SectionRef(ret, this));
		}

		template<support::endianness target_endianness, bool is64Bits>
		section_iterator ELFObjectFile<target_endianness, is64Bits>
		::end_sections() const {
		DataRefImpl ret;
		ret.p = reinterpret_cast<intptr_t>(base()
		+ Header->e_shoff
		+ (Header->e_shentsize*getNumSections(
		)));
		return section_iterator(SectionRef(ret, this));
		}

		template<support::endianness target_endianness, bool is64Bits>
		typename ELFObjectFile<target_endianness, is64Bits>::dyn_iterator
		ELFObjectFile<target_endianness, is64Bits>::begin_dynamic_table() const {
		DataRefImpl DynData;
		if (dot_dynamic_sec == NULL \|\| dot_dynamic_sec->sh_size == 0) {
		DynData.d.a = std::numeric_limits<uint32_t>::max();
		} else {
		DynData.d.a = 0;
		}
		return dyn_iterator(DynRef(DynData, this));
		}

		template<support::endianness target_endianness, bool is64Bits>
		typename ELFObjectFile<target_endianness, is64Bits>::dyn_iterator
		ELFObjectFile<target_endianness, is64Bits>
		::end_dynamic_table() const {
		DataRefImpl DynData;
		DynData.d.a = std::numeric_limits<uint32_t>::max();
		return dyn_iterator(DynRef(DynData, this));
		}

		template<support::endianness target_endianness, bool is64Bits>
		error_code ELFObjectFile<target_endianness, is64Bits>
		::getDynNext(DataRefImpl DynData,
		DynRef &Result) const {
		++DynData.d.a;

		// Check to see if we are at the end of .dynamic
		if (DynData.d.a >= dot_dynamic_sec->getEntityCount()) {
		// We are at the end. Return the terminator.
		DynData.d.a = std::numeric_limits<uint32_t>::max();
		}

		Result = DynRef(DynData, this);
		return object_error::success;
		}

		template<support::endianness target_endianness, bool is64Bits>
		StringRef
		ELFObjectFile<target_endianness, is64Bits>::getLoadName() const {
		if (!dt_soname) {
		// Find the DT_SONAME entry
		dyn_iterator it = begin_dynamic_table();
		dyn_iterator ie = end_dynamic_table();
		error_code ec;
		while (it != ie) {
		if (it->getTag() == ELF::DT_SONAME)
		break;
		it.increment(ec);
		if (ec)
		report_fatal_error("dynamic table iteration failed");
		}
		if (it != ie) {
		if (dot_dynstr_sec == NULL)
		report_fatal_error("Dynamic string table is missing");
		dt_soname = getString(dot_dynstr_sec, it->getVal());
		} else {
		dt_soname = "";
		}
		}
		return dt_soname;
		}

		template<support::endianness target_endianness, bool is64Bits>
		library_iterator ELFObjectFile<target_endianness, is64Bits>
		::begin_libraries_needed() const {
		// Find the first DT_NEEDED entry
		dyn_iterator i = begin_dynamic_table();
		dyn_iterator e = end_dynamic_table();
		error_code ec;
		while (i != e) {
		if (i->getTag() == ELF::DT_NEEDED)
		break;
		i.increment(ec);
		if (ec)
		report_fatal_error("dynamic table iteration failed");
		}
		// Use the same DataRefImpl format as DynRef.
		return library_iterator(LibraryRef(i->getRawDataRefImpl(), this));
		}

		template<support::endianness target_endianness, bool is64Bits>
		error_code ELFObjectFile<target_endianness, is64Bits>
		::getLibraryNext(DataRefImpl Data,
		LibraryRef &Result) const {
		// Use the same DataRefImpl format as DynRef.
		dyn_iterator i = dyn_iterator(DynRef(Data, this));
		dyn_iterator e = end_dynamic_table();

		// Skip the current dynamic table entry.
		error_code ec;
		if (i != e) {
		i.increment(ec);
		// TODO: proper error handling
		if (ec)
		report_fatal_error("dynamic table iteration failed");
		}

		// Find the next DT_NEEDED entry.
		while (i != e) {
		if (i->getTag() == ELF::DT_NEEDED)
		break;
		i.increment(ec);
		if (ec)
		report_fatal_error("dynamic table iteration failed");
		}
		Result = LibraryRef(i->getRawDataRefImpl(), this);
		return object_error::success;
		}

		template<support::endianness target_endianness, bool is64Bits>
		error_code ELFObjectFile<target_endianness, is64Bits>
		::getLibraryPath(DataRefImpl Data, StringRef &Res) const {
		dyn_iterator i = dyn_iterator(DynRef(Data, this));
		if (i == end_dynamic_table())
		report_fatal_error("getLibraryPath() called on iterator end");

		if (i->getTag() != ELF::DT_NEEDED)
		report_fatal_error("Invalid library_iterator");

		// This uses .dynstr to lookup the name of the DT_NEEDED entry.
		// THis works as long as DT_STRTAB == .dynstr. This is true most of
		// the time, but the specification allows exceptions.
		// TODO: This should really use DT_STRTAB instead. Doing this requires
		// reading the program headers.
		if (dot_dynstr_sec == NULL)
		report_fatal_error("Dynamic string table is missing");
		Res = getString(dot_dynstr_sec, i->getVal());
		return object_error::success;
		}

		template<support::endianness target_endianness, bool is64Bits>
		library_iterator ELFObjectFile<target_endianness, is64Bits>
		::end_libraries_needed() const {
		dyn_iterator e = end_dynamic_table();
		// Use the same DataRefImpl format as DynRef.
		return library_iterator(LibraryRef(e->getRawDataRefImpl(), this));
		}

		template<support::endianness target_endianness, bool is64Bits>
		uint8_t ELFObjectFile<target_endianness, is64Bits>::getBytesInAddress() con
		st {
		return is64Bits ? 8 : 4;
		}

		template<support::endianness target_endianness, bool is64Bits>
		StringRef ELFObjectFile<target_endianness, is64Bits>
		::getFileFormatName() const {
		switch(Header->e_ident[ELF::EI_CLASS]) {
		case ELF::ELFCLASS32:
		switch(Header->e_machine) {
		case ELF::EM_386:
		return "ELF32-i386";
		case ELF::EM_X86_64:
		return "ELF32-x86-64";
		case ELF::EM_ARM:
		return "ELF32-arm";
		default:
		return "ELF32-unknown";
		}
		case ELF::ELFCLASS64:
		switch(Header->e_machine) {
		case ELF::EM_386:
		return "ELF64-i386";
		case ELF::EM_X86_64:
		return "ELF64-x86-64";
		default:
		return "ELF64-unknown";
		}
		default:
		// FIXME: Proper error handling.
		report_fatal_error("Invalid ELFCLASS!");
		}
		}

		template<support::endianness target_endianness, bool is64Bits>
		unsigned ELFObjectFile<target_endianness, is64Bits>::getArch() const {
		switch(Header->e_machine) {
		case ELF::EM_386:
		return Triple::x86;
		case ELF::EM_X86_64:
		return Triple::x86_64;
		case ELF::EM_ARM:
		return Triple::arm;
		default:
		return Triple::UnknownArch;
		}
		}

		template<support::endianness target_endianness, bool is64Bits>
		uint64_t ELFObjectFile<target_endianness, is64Bits>::getNumSections() const
		{
		assert(Header && "Header not initialized!");
		if (Header->e_shnum == ELF::SHN_UNDEF) {
		assert(SectionHeaderTable && "SectionHeaderTable not initialized!");
		return SectionHeaderTable->sh_size;
		}
		return Header->e_shnum;
		}

		template<support::endianness target_endianness, bool is64Bits>
		uint64_t
		ELFObjectFile<target_endianness, is64Bits>::getStringTableIndex() const {
		if (Header->e_shnum == ELF::SHN_UNDEF) {
		if (Header->e_shstrndx == ELF::SHN_HIRESERVE)
		return SectionHeaderTable->sh_link;
		if (Header->e_shstrndx >= getNumSections())
		return 0;
		}
		return Header->e_shstrndx;
		}

		template<support::endianness target_endianness, bool is64Bits>
		template<typename T>
		inline const T *
		ELFObjectFile<target_endianness, is64Bits>::getEntry(uint16_t Section,
		uint32_t Entry) const
		{
		return getEntry<T>(getSection(Section), Entry);
		}

		template<support::endianness target_endianness, bool is64Bits>
		template<typename T>
		inline const T *
		ELFObjectFile<target_endianness, is64Bits>::getEntry(const Elf_Shdr * Secti
		on,
		uint32_t Entry) const
		{
		return reinterpret_cast<const T *>(
		base()
		+ Section->sh_offset
		+ (Entry * Section->sh_entsize));
		}

		template<support::endianness target_endianness, bool is64Bits>
		const typename ELFObjectFile<target_endianness, is64Bits>::Elf_Sym *
		ELFObjectFile<target_endianness, is64Bits>::getSymbol(DataRefImpl Symb) con
		st {
		return getEntry<Elf_Sym>(SymbolTableSections[Symb.d.b], Symb.d.a);
		}

		template<support::endianness target_endianness, bool is64Bits>
		const typename ELFObjectFile<target_endianness, is64Bits>::Elf_Dyn *
		ELFObjectFile<target_endianness, is64Bits>::getDyn(DataRefImpl DynData) con
		st {
		return getEntry<Elf_Dyn>(dot_dynamic_sec, DynData.d.a);
		}

		template<support::endianness target_endianness, bool is64Bits>
		const typename ELFObjectFile<target_endianness, is64Bits>::Elf_Rel *
		ELFObjectFile<target_endianness, is64Bits>::getRel(DataRefImpl Rel) const {
		return getEntry<Elf_Rel>(Rel.w.b, Rel.w.c);
		}

		template<support::endianness target_endianness, bool is64Bits>
		const typename ELFObjectFile<target_endianness, is64Bits>::Elf_Rela *
		ELFObjectFile<target_endianness, is64Bits>::getRela(DataRefImpl Rela) const
		{
		return getEntry<Elf_Rela>(Rela.w.b, Rela.w.c);
		}

		template<support::endianness target_endianness, bool is64Bits>
		const typename ELFObjectFile<target_endianness, is64Bits>::Elf_Shdr *
		ELFObjectFile<target_endianness, is64Bits>::getSection(DataRefImpl Symb) co
		nst {
		const Elf_Shdr *sec = getSection(Symb.d.b);
		if (sec->sh_type != ELF::SHT_SYMTAB \|\| sec->sh_type != ELF::SHT_DYNSYM)
		// FIXME: Proper error handling.
		report_fatal_error("Invalid symbol table section!");
		return sec;
		}

		template<support::endianness target_endianness, bool is64Bits>
		const typename ELFObjectFile<target_endianness, is64Bits>::Elf_Shdr *
		ELFObjectFile<target_endianness, is64Bits>::getSection(uint32_t index) cons
		t {
		if (index == 0)
		return 0;
		if (!SectionHeaderTable \|\| index >= getNumSections())
		// FIXME: Proper error handling.
		report_fatal_error("Invalid section index!");

		return reinterpret_cast<const Elf_Shdr *>(
		reinterpret_cast<const char *>(SectionHeaderTable)
		+ (index * Header->e_shentsize));
		}

		template<support::endianness target_endianness, bool is64Bits>
		const char *ELFObjectFile<target_endianness, is64Bits>
		::getString(uint32_t section,
		ELF::Elf32_Word offset) const {
		return getString(getSection(section), offset);
		}

		template<support::endianness target_endianness, bool is64Bits>
		const char *ELFObjectFile<target_endianness, is64Bits>
		::getString(const Elf_Shdr *section,
		ELF::Elf32_Word offset) const {
		assert(section && section->sh_type == ELF::SHT_STRTAB && "Invalid section
		!");
		if (offset >= section->sh_size)
		// FIXME: Proper error handling.
		report_fatal_error("Symbol name offset outside of string table!");
		return (const char *)base() + section->sh_offset + offset;
		}

		template<support::endianness target_endianness, bool is64Bits>
		error_code ELFObjectFile<target_endianness, is64Bits>
		::getSymbolName(const Elf_Shdr *section,
		const Elf_Sym *symb,
		StringRef &Result) const {
		if (symb->st_name == 0) {
		const Elf_Shdr *section = getSection(symb);
		if (!section)
		Result = "";
		else
		Result = getString(dot_shstrtab_sec, section->sh_name);
		return object_error::success;
		}

		if (section == SymbolTableSections[0]) {
		// Symbol is in .dynsym, use .dynstr string table
		Result = getString(dot_dynstr_sec, symb->st_name);
		} else {
		// Use the default symbol table name section.
		Result = getString(dot_strtab_sec, symb->st_name);
		}
		return object_error::success;
		}

		template<support::endianness target_endianness, bool is64Bits>
		error_code ELFObjectFile<target_endianness, is64Bits>
		::getSymbolVersion(const Elf_Shdr *section,
		const Elf_Sym *symb,
		StringRef &Version,
		bool &IsDefault) const {
		// Handle non-dynamic symbols.
		if (section != SymbolTableSections[0]) {
		// Non-dynamic symbols can have versions in their names
		// A name of the form 'foo@V1' indicates version 'V1', non-default.
		// A name of the form 'foo@@V2' indicates version 'V2', default version
		.
		StringRef Name;
		error_code ec = getSymbolName(section, symb, Name);
		if (ec != object_error::success)
		return ec;
		size_t atpos = Name.find('@');
		if (atpos == StringRef::npos) {
		Version = "";
		IsDefault = false;
		return object_error::success;
		}
		++atpos;
		if (atpos < Name.size() && Name[atpos] == '@') {
		IsDefault = true;
		++atpos;
		} else {
		IsDefault = false;
		}
		Version = Name.substr(atpos);
		return object_error::success;
		}

		// This is a dynamic symbol. Look in the GNU symbol version table.
		if (dot_gnu_version_sec == NULL) {
		// No version table.
		Version = "";
		IsDefault = false;
		return object_error::success;
		}

		// Determine the position in the symbol table of this entry.
		const char sec_start = (const char)base() + section->sh_offset;
		size_t entry_index = ((const char*)symb - sec_start)/section->sh_entsize;

		// Get the corresponding version index entry
		const Elf_Versym *vs = getEntry<Elf_Versym>(dot_gnu_version_sec, entry_in
		dex);
		size_t version_index = vs->vs_index & ELF::VERSYM_VERSION;

		// Special markers for unversioned symbols.
		if (version_index == ELF::VER_NDX_LOCAL \|\|
		version_index == ELF::VER_NDX_GLOBAL) {
		Version = "";
		IsDefault = false;
		return object_error::success;
		}

		// Lookup this symbol in the version table
		LoadVersionMap();
		if (version_index >= VersionMap.size() \|\| VersionMap[version_index].isNul
		l())
		report_fatal_error("Symbol has version index without corresponding "
		"define or reference entry");
		const VersionMapEntry &entry = VersionMap[version_index];

		// Get the version name string
		size_t name_offset;
		if (entry.isVerdef()) {
		// The first Verdaux entry holds the name.
		name_offset = entry.getVerdef()->getAux()->vda_name;
		} else {
		name_offset = entry.getVernaux()->vna_name;
		}
		Version = getString(dot_dynstr_sec, name_offset);

		// Set IsDefault
		if (entry.isVerdef()) {
		IsDefault = !(vs->vs_index & ELF::VERSYM_HIDDEN);
		} else {
		IsDefault = false;
		}

		return object_error::success;
		}

		template<support::endianness target_endianness, bool is64Bits>
		inline DynRefImpl<target_endianness, is64Bits>
		::DynRefImpl(DataRefImpl DynP, const OwningType *Owner)
		: DynPimpl(DynP)
		, OwningObject(Owner) {}

		template<support::endianness target_endianness, bool is64Bits>
		inline bool DynRefImpl<target_endianness, is64Bits>
		::operator==(const DynRefImpl &Other) const {
		return DynPimpl == Other.DynPimpl;
		}

		template<support::endianness target_endianness, bool is64Bits>
		inline bool DynRefImpl<target_endianness, is64Bits>
		::operator <(const DynRefImpl &Other) const {
		return DynPimpl < Other.DynPimpl;
		}

		template<support::endianness target_endianness, bool is64Bits>
		inline error_code DynRefImpl<target_endianness, is64Bits>
		::getNext(DynRefImpl &Result) const {
		return OwningObject->getDynNext(DynPimpl, Result);
		}

		template<support::endianness target_endianness, bool is64Bits>
		inline int64_t DynRefImpl<target_endianness, is64Bits>
		::getTag() const {
		return OwningObject->getDyn(DynPimpl)->d_tag;
		}

		template<support::endianness target_endianness, bool is64Bits>
		inline uint64_t DynRefImpl<target_endianness, is64Bits>
		::getVal() const {
		return OwningObject->getDyn(DynPimpl)->d_un.d_val;
		}

		template<support::endianness target_endianness, bool is64Bits>
		inline uint64_t DynRefImpl<target_endianness, is64Bits>
		::getPtr() const {
		return OwningObject->getDyn(DynPimpl)->d_un.d_ptr;
		}

		template<support::endianness target_endianness, bool is64Bits>
		inline DataRefImpl DynRefImpl<target_endianness, is64Bits>
		::getRawDataRefImpl() const {
		return DynPimpl;
		}

		/// This is a generic interface for retrieving GNU symbol version
		/// information from an ELFObjectFile.
		static inline error_code GetELFSymbolVersion(const ObjectFile *Obj,
		const SymbolRef &Sym,
		StringRef &Version,
		bool &IsDefault) {
		// Little-endian 32-bit
		if (const ELFObjectFile<support::little, false> *ELFObj =
		dyn_cast<ELFObjectFile<support::little, false> >(Obj))
		return ELFObj->getSymbolVersion(Sym, Version, IsDefault);

		// Big-endian 32-bit
		if (const ELFObjectFile<support::big, false> *ELFObj =
		dyn_cast<ELFObjectFile<support::big, false> >(Obj))
		return ELFObj->getSymbolVersion(Sym, Version, IsDefault);

		// Little-endian 64-bit
		if (const ELFObjectFile<support::little, true> *ELFObj =
		dyn_cast<ELFObjectFile<support::little, true> >(Obj))
		return ELFObj->getSymbolVersion(Sym, Version, IsDefault);

		// Big-endian 64-bit
		if (const ELFObjectFile<support::big, true> *ELFObj =
		dyn_cast<ELFObjectFile<support::big, true> >(Obj))
		return ELFObj->getSymbolVersion(Sym, Version, IsDefault);


	} // end namespace ELF	llvm_unreachable("Object passed to GetELFSymbolVersion() is not ELF");
		}


	} // end namespace llvm	}
		}

	#endif	#endif

End of changes. 25 change blocks.
	1107 lines changed or deleted	2241 lines changed or added

	EdgeBundles.h	EdgeBundles.h

	skipping to change at line 21	skipping to change at line 21
	// edges leaving a machine basic block are in the same bundle, and all edge s	// edges leaving a machine basic block are in the same bundle, and all edge s
	// leaving a basic block are in the same bundle.	// leaving a basic block are in the same bundle.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_CODEGEN_EDGEBUNDLES_H	#ifndef LLVM_CODEGEN_EDGEBUNDLES_H
	#define LLVM_CODEGEN_EDGEBUNDLES_H	#define LLVM_CODEGEN_EDGEBUNDLES_H

	#include "llvm/ADT/ArrayRef.h"	#include "llvm/ADT/ArrayRef.h"
	#include "llvm/ADT/IntEqClasses.h"	#include "llvm/ADT/IntEqClasses.h"

		#include "llvm/ADT/Twine.h"
	#include "llvm/CodeGen/MachineFunctionPass.h"	#include "llvm/CodeGen/MachineFunctionPass.h"

	namespace llvm {	namespace llvm {

	class EdgeBundles : public MachineFunctionPass {	class EdgeBundles : public MachineFunctionPass {
	const MachineFunction *MF;	const MachineFunction *MF;

	/// EC - Each edge bundle is an equivalence class. The keys are:	/// EC - Each edge bundle is an equivalence class. The keys are:
	/// 2*BB->getNumber() -> Ingoing bundle.	/// 2*BB->getNumber() -> Ingoing bundle.
	/// 2*BB->getNumber()+1 -> Outgoing bundle.	/// 2*BB->getNumber()+1 -> Outgoing bundle.

	skipping to change at line 64	skipping to change at line 65
	void view() const;	void view() const;

	private:	private:
	virtual bool runOnMachineFunction(MachineFunction&);	virtual bool runOnMachineFunction(MachineFunction&);
	virtual void getAnalysisUsage(AnalysisUsage&) const;	virtual void getAnalysisUsage(AnalysisUsage&) const;
	};	};

	/// Specialize WriteGraph, the standard implementation won't work.	/// Specialize WriteGraph, the standard implementation won't work.
	raw_ostream &WriteGraph(raw_ostream &O, const EdgeBundles &G,	raw_ostream &WriteGraph(raw_ostream &O, const EdgeBundles &G,
	bool ShortNames = false,	bool ShortNames = false,

	const std::string &Title = "");	const Twine &Title = "");

	} // end namespace llvm	} // end namespace llvm

	#endif	#endif

End of changes. 2 change blocks.
	1 lines changed or deleted	2 lines changed or added

	Endian.h	Endian.h

	skipping to change at line 101	skipping to change at line 101
	endianness endian,	endianness endian,
	alignment align>	alignment align>
	class packed_endian_specific_integral;	class packed_endian_specific_integral;

	template<typename value_type>	template<typename value_type>
	class packed_endian_specific_integral<value_type, little, unaligned> {	class packed_endian_specific_integral<value_type, little, unaligned> {
	public:	public:
	operator value_type() const {	operator value_type() const {
	return endian::read_le<value_type, unaligned>(Value);	return endian::read_le<value_type, unaligned>(Value);
	}	}

		void operator=(value_type newValue) {
		endian::write_le<value_type, unaligned>((void *)&Value, newValue);
		}
	private:	private:
	uint8_t Value[sizeof(value_type)];	uint8_t Value[sizeof(value_type)];
	};	};

	template<typename value_type>	template<typename value_type>
	class packed_endian_specific_integral<value_type, big, unaligned> {	class packed_endian_specific_integral<value_type, big, unaligned> {
	public:	public:
	operator value_type() const {	operator value_type() const {
	return endian::read_be<value_type, unaligned>(Value);	return endian::read_be<value_type, unaligned>(Value);
	}	}

		void operator=(value_type newValue) {
		endian::write_be<value_type, unaligned>((void *)&Value, newValue);
		}
	private:	private:
	uint8_t Value[sizeof(value_type)];	uint8_t Value[sizeof(value_type)];
	};	};

	template<typename value_type>	template<typename value_type>
	class packed_endian_specific_integral<value_type, little, aligned> {	class packed_endian_specific_integral<value_type, little, aligned> {
	public:	public:
	operator value_type() const {	operator value_type() const {
	return endian::read_le<value_type, aligned>(&Value);	return endian::read_le<value_type, aligned>(&Value);
	}	}

		void operator=(value_type newValue) {
		endian::write_le<value_type, aligned>((void *)&Value, newValue);
		}
	private:	private:
	value_type Value;	value_type Value;
	};	};

	template<typename value_type>	template<typename value_type>
	class packed_endian_specific_integral<value_type, big, aligned> {	class packed_endian_specific_integral<value_type, big, aligned> {
	public:	public:
	operator value_type() const {	operator value_type() const {
	return endian::read_be<value_type, aligned>(&Value);	return endian::read_be<value_type, aligned>(&Value);
	}	}

		void operator=(value_type newValue) {
		endian::write_be<value_type, aligned>((void *)&Value, newValue);
		}
	private:	private:
	value_type Value;	value_type Value;
	};	};

	} // end namespace detail	} // end namespace detail

	typedef detail::packed_endian_specific_integral	typedef detail::packed_endian_specific_integral
	<uint8_t, little, unaligned> ulittle8_t;	<uint8_t, little, unaligned> ulittle8_t;
	typedef detail::packed_endian_specific_integral	typedef detail::packed_endian_specific_integral
	<uint16_t, little, unaligned> ulittle16_t;	<uint16_t, little, unaligned> ulittle16_t;

End of changes. 4 change blocks.
	0 lines changed or deleted	12 lines changed or added

	EnhancedDisassembly.h	EnhancedDisassembly.h

	skipping to change at line 28	skipping to change at line 28

	#ifndef LLVM_C_ENHANCEDDISASSEMBLY_H	#ifndef LLVM_C_ENHANCEDDISASSEMBLY_H
	#define LLVM_C_ENHANCEDDISASSEMBLY_H	#define LLVM_C_ENHANCEDDISASSEMBLY_H

	#include "llvm/Support/DataTypes.h"	#include "llvm/Support/DataTypes.h"

	#ifdef __cplusplus	#ifdef __cplusplus
	extern "C" {	extern "C" {
	#endif	#endif


		/**
		* @defgroup LLVMCEnhancedDisassembly Enhanced Disassembly
		* @ingroup LLVMC
		* @deprecated
		*
		* This module contains an interface to the Enhanced Disassembly (edis)
		* library. The edis library is deprecated and will likely disappear in
		* the near future. You should use the @ref LLVMCDisassembler interface
		* instead.
		*
		* @{
		*/

	/*!	/*!
	@typedef EDByteReaderCallback	@typedef EDByteReaderCallback
	Interface to memory from which instructions may be read.	Interface to memory from which instructions may be read.
	@param byte A pointer whose target should be filled in with the data retur ned.	@param byte A pointer whose target should be filled in with the data retur ned.
	@param address The address of the byte to be read.	@param address The address of the byte to be read.
	@param arg An anonymous argument for client use.	@param arg An anonymous argument for client use.
	@result 0 on success; -1 otherwise.	@result 0 on success; -1 otherwise.
	*/	*/
	typedef int (EDByteReaderCallback)(uint8_t byte, uint64_t address, void * arg);	typedef int (EDByteReaderCallback)(uint8_t byte, uint64_t address, void * arg);


	skipping to change at line 507	skipping to change at line 520
	@function EDBlockVisitTokens	@function EDBlockVisitTokens
	Visits every token with a visitor.	Visits every token with a visitor.
	@param inst The instruction with the tokens to be visited.	@param inst The instruction with the tokens to be visited.
	@param visitor The visitor.	@param visitor The visitor.
	@result 0 if the visit ended normally; -1 if the visitor encountered an er ror	@result 0 if the visit ended normally; -1 if the visitor encountered an er ror
	or there was some other error.	or there was some other error.
	*/	*/
	int EDBlockVisitTokens(EDInstRef inst,	int EDBlockVisitTokens(EDInstRef inst,
	EDTokenVisitor_t visitor);	EDTokenVisitor_t visitor);


		/**
		* @}
		*/

	#endif	#endif

	#ifdef __cplusplus	#ifdef __cplusplus
	}	}
	#endif	#endif

	#endif	#endif

End of changes. 2 change blocks.
	0 lines changed or deleted	17 lines changed or added

	ExecutionEngine.h	ExecutionEngine.h

	skipping to change at line 29	skipping to change at line 29
	#ifndef LLVM_C_EXECUTIONENGINE_H	#ifndef LLVM_C_EXECUTIONENGINE_H
	#define LLVM_C_EXECUTIONENGINE_H	#define LLVM_C_EXECUTIONENGINE_H

	#include "llvm-c/Core.h"	#include "llvm-c/Core.h"
	#include "llvm-c/Target.h"	#include "llvm-c/Target.h"

	#ifdef __cplusplus	#ifdef __cplusplus
	extern "C" {	extern "C" {
	#endif	#endif


		/**
		* @defgroup LLVMCExecutionEngine Execution Engine
		* @ingroup LLVMC
		*
		* @{
		*/

	void LLVMLinkInJIT(void);	void LLVMLinkInJIT(void);
	void LLVMLinkInInterpreter(void);	void LLVMLinkInInterpreter(void);

	typedef struct LLVMOpaqueGenericValue *LLVMGenericValueRef;	typedef struct LLVMOpaqueGenericValue *LLVMGenericValueRef;
	typedef struct LLVMOpaqueExecutionEngine *LLVMExecutionEngineRef;	typedef struct LLVMOpaqueExecutionEngine *LLVMExecutionEngineRef;

	/===-- Operations on generic values -------------------------------------- ===/	/===-- Operations on generic values -------------------------------------- ===/

	LLVMGenericValueRef LLVMCreateGenericValueOfInt(LLVMTypeRef Ty,	LLVMGenericValueRef LLVMCreateGenericValueOfInt(LLVMTypeRef Ty,
	unsigned long long N,	unsigned long long N,

	skipping to change at line 128	skipping to change at line 135

	void *LLVMRecompileAndRelinkFunction(LLVMExecutionEngineRef EE, LLVMValueRe f Fn);	void *LLVMRecompileAndRelinkFunction(LLVMExecutionEngineRef EE, LLVMValueRe f Fn);

	LLVMTargetDataRef LLVMGetExecutionEngineTargetData(LLVMExecutionEngineRef E E);	LLVMTargetDataRef LLVMGetExecutionEngineTargetData(LLVMExecutionEngineRef E E);

	void LLVMAddGlobalMapping(LLVMExecutionEngineRef EE, LLVMValueRef Global,	void LLVMAddGlobalMapping(LLVMExecutionEngineRef EE, LLVMValueRef Global,
	void* Addr);	void* Addr);

	void *LLVMGetPointerToGlobal(LLVMExecutionEngineRef EE, LLVMValueRef Global );	void *LLVMGetPointerToGlobal(LLVMExecutionEngineRef EE, LLVMValueRef Global );


		/**
		* @}
		*/

	#ifdef __cplusplus	#ifdef __cplusplus
	}	}

	namespace llvm {	namespace llvm {
	struct GenericValue;	struct GenericValue;
	class ExecutionEngine;	class ExecutionEngine;

	#define DEFINE_SIMPLE_CONVERSION_FUNCTIONS(ty, ref) \	#define DEFINE_SIMPLE_CONVERSION_FUNCTIONS(ty, ref) \
	inline ty *unwrap(ref P) { \	inline ty *unwrap(ref P) { \
	return reinterpret_cast<ty*>(P); \	return reinterpret_cast<ty*>(P); \

End of changes. 2 change blocks.
	0 lines changed or deleted	11 lines changed or added

	FastISel.h	FastISel.h

	skipping to change at line 24	skipping to change at line 24
	#ifndef LLVM_CODEGEN_FASTISEL_H	#ifndef LLVM_CODEGEN_FASTISEL_H
	#define LLVM_CODEGEN_FASTISEL_H	#define LLVM_CODEGEN_FASTISEL_H

	#include "llvm/ADT/DenseMap.h"	#include "llvm/ADT/DenseMap.h"
	#include "llvm/CodeGen/ValueTypes.h"	#include "llvm/CodeGen/ValueTypes.h"
	#include "llvm/CodeGen/MachineBasicBlock.h"	#include "llvm/CodeGen/MachineBasicBlock.h"

	namespace llvm {	namespace llvm {

	class AllocaInst;	class AllocaInst;

		class Constant;
	class ConstantFP;	class ConstantFP;
	class FunctionLoweringInfo;	class FunctionLoweringInfo;
	class Instruction;	class Instruction;

		class LoadInst;
	class MachineBasicBlock;	class MachineBasicBlock;
	class MachineConstantPool;	class MachineConstantPool;
	class MachineFunction;	class MachineFunction;
	class MachineInstr;	class MachineInstr;
	class MachineFrameInfo;	class MachineFrameInfo;
	class MachineRegisterInfo;	class MachineRegisterInfo;
	class TargetData;	class TargetData;
	class TargetInstrInfo;	class TargetInstrInfo;
	class TargetLowering;	class TargetLowering;
	class TargetMachine;	class TargetMachine;
	class TargetRegisterClass;	class TargetRegisterClass;
	class TargetRegisterInfo;	class TargetRegisterInfo;

	class LoadInst;	class User;
		class Value;

	/// FastISel - This is a fast-path instruction selection class that	/// FastISel - This is a fast-path instruction selection class that
	/// generates poor code and doesn't support illegal types or non-trivial	/// generates poor code and doesn't support illegal types or non-trivial
	/// lowering, but runs quickly.	/// lowering, but runs quickly.
	class FastISel {	class FastISel {
	protected:	protected:
	DenseMap<const Value *, unsigned> LocalValueMap;	DenseMap<const Value *, unsigned> LocalValueMap;
	FunctionLoweringInfo &FuncInfo;	FunctionLoweringInfo &FuncInfo;
	MachineRegisterInfo &MRI;	MachineRegisterInfo &MRI;
	MachineFrameInfo &MFI;	MachineFrameInfo &MFI;

	skipping to change at line 361	skipping to change at line 364
	bool SelectGetElementPtr(const User *I);	bool SelectGetElementPtr(const User *I);

	bool SelectCall(const User *I);	bool SelectCall(const User *I);

	bool SelectBitCast(const User *I);	bool SelectBitCast(const User *I);

	bool SelectCast(const User *I, unsigned Opcode);	bool SelectCast(const User *I, unsigned Opcode);

	bool SelectExtractValue(const User *I);	bool SelectExtractValue(const User *I);


		bool SelectInsertValue(const User *I);

	/// HandlePHINodesInSuccessorBlocks - Handle PHI nodes in successor block s.	/// HandlePHINodesInSuccessorBlocks - Handle PHI nodes in successor block s.
	/// Emit code to ensure constants are copied into registers when needed.	/// Emit code to ensure constants are copied into registers when needed.
	/// Remember the virtual registers that need to be added to the Machine P HI	/// Remember the virtual registers that need to be added to the Machine P HI
	/// nodes as input. We cannot just directly add them, because expansion	/// nodes as input. We cannot just directly add them, because expansion
	/// might result in multiple MBB's for one BB. As such, the start of the	/// might result in multiple MBB's for one BB. As such, the start of the
	/// BB might correspond to a different MBB than the end.	/// BB might correspond to a different MBB than the end.
	bool HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB);	bool HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB);

	/// materializeRegForValue - Helper for getRegForVale. This function is	/// materializeRegForValue - Helper for getRegForVale. This function is
	/// called when the value isn't already available in a register and must	/// called when the value isn't already available in a register and must
	/// be materialized with new instructions.	/// be materialized with new instructions.
	unsigned materializeRegForValue(const Value *V, MVT VT);	unsigned materializeRegForValue(const Value *V, MVT VT);

	/// flushLocalValueMap - clears LocalValueMap and moves the area for the	/// flushLocalValueMap - clears LocalValueMap and moves the area for the
	/// new local variables to the beginning of the block. It helps to avoid	/// new local variables to the beginning of the block. It helps to avoid
	/// spilling cached variables across heavy instructions like calls.	/// spilling cached variables across heavy instructions like calls.
	void flushLocalValueMap();	void flushLocalValueMap();

	/// hasTrivialKill - Test whether the given value has exactly one use.	/// hasTrivialKill - Test whether the given value has exactly one use.
	bool hasTrivialKill(const Value *V) const;	bool hasTrivialKill(const Value *V) const;


		/// removeDeadCode - Remove all dead instructions between the I and E.
		void removeDeadCode(MachineBasicBlock::iterator I,
		MachineBasicBlock::iterator E);
	};	};

	}	}

	#endif	#endif

End of changes. 5 change blocks.
	1 lines changed or deleted	10 lines changed or added

	FileSystem.h	FileSystem.h

	skipping to change at line 30	skipping to change at line 30
	// listed codes, but it does guarantee that if any of the explicitly listed	// listed codes, but it does guarantee that if any of the explicitly listed
	// errors occur, the correct error_code will be used ]. All functions may	// errors occur, the correct error_code will be used ]. All functions may
	// return errc::not_enough_memory if there is not enough memory to complete the	// return errc::not_enough_memory if there is not enough memory to complete the
	// operation.	// operation.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_SUPPORT_FILE_SYSTEM_H	#ifndef LLVM_SUPPORT_FILE_SYSTEM_H
	#define LLVM_SUPPORT_FILE_SYSTEM_H	#define LLVM_SUPPORT_FILE_SYSTEM_H


		#include "llvm/ADT/IntrusiveRefCntPtr.h"
	#include "llvm/ADT/SmallString.h"	#include "llvm/ADT/SmallString.h"
	#include "llvm/ADT/Twine.h"	#include "llvm/ADT/Twine.h"
	#include "llvm/Support/DataTypes.h"	#include "llvm/Support/DataTypes.h"

	#include "llvm/Support/PathV1.h"	#include "llvm/Support/ErrorHandling.h"
	#include "llvm/Support/system_error.h"	#include "llvm/Support/system_error.h"
	#include <ctime>	#include <ctime>
	#include <iterator>	#include <iterator>

		#include <stack>
	#include <string>	#include <string>

		#include <vector>

		#if HAVE_SYS_STAT_H
		#include <sys/stat.h>
		#endif

	namespace llvm {	namespace llvm {
	namespace sys {	namespace sys {
	namespace fs {	namespace fs {

	/// file_type - An "enum class" enumeration for the file system's view of t he	/// file_type - An "enum class" enumeration for the file system's view of t he
	/// type.	/// type.
	struct file_type {	struct file_type {
	enum _ {	enum _ {
	status_error,	status_error,

	skipping to change at line 94	skipping to change at line 101
	struct space_info {	struct space_info {
	uint64_t capacity;	uint64_t capacity;
	uint64_t free;	uint64_t free;
	uint64_t available;	uint64_t available;
	};	};

	/// file_status - Represents the result of a call to stat and friends. It h as	/// file_status - Represents the result of a call to stat and friends. It h as
	/// a platform specific member to store the result.	/// a platform specific member to store the result.
	class file_status	class file_status
	{	{

	// implementation defined status field.	#if defined(LLVM_ON_UNIX)
		dev_t st_dev;
		ino_t st_ino;
		#elif defined (LLVM_ON_WIN32)
		uint32_t LastWriteTimeHigh;
		uint32_t LastWriteTimeLow;
		uint32_t VolumeSerialNumber;
		uint32_t FileSizeHigh;
		uint32_t FileSizeLow;
		uint32_t FileIndexHigh;
		uint32_t FileIndexLow;
		#endif
		friend bool equivalent(file_status A, file_status B);
		friend error_code status(const Twine &path, file_status &result);
	file_type Type;	file_type Type;
	public:	public:
	explicit file_status(file_type v=file_type::status_error)	explicit file_status(file_type v=file_type::status_error)
	: Type(v) {}	: Type(v) {}

	file_type type() const { return Type; }	file_type type() const { return Type; }
	void type(file_type v) { Type = v; }	void type(file_type v) { Type = v; }
	};	};


		/// file_magic - An "enum class" enumeration of file types based on magic (
		the first
		/// N bytes of the file).
		struct file_magic {
		enum _ {
		unknown = 0, ///< Unrecognized file
		bitcode, ///< Bitcode file
		archive, ///< ar style archive file
		elf_relocatable, ///< ELF Relocatable object file
		elf_executable, ///< ELF Executable image
		elf_shared_object, ///< ELF dynamically linked shared lib
		elf_core, ///< ELF core image
		macho_object, ///< Mach-O Object file
		macho_executable, ///< Mach-O Executable
		macho_fixed_virtual_memory_shared_lib, ///< Mach-O Shared Lib, FVM
		macho_core, ///< Mach-O Core File
		macho_preload_executabl, ///< Mach-O Preloaded Executable
		macho_dynamically_linked_shared_lib, ///< Mach-O dynlinked shared lib
		macho_dynamic_linker, ///< The Mach-O dynamic linker
		macho_bundle, ///< Mach-O Bundle file
		macho_dynamically_linked_shared_lib_stub, ///< Mach-O Shared lib stub
		macho_dsym_companion, ///< Mach-O dSYM companion file
		coff_object, ///< COFF object file
		pecoff_executable ///< PECOFF executable file
		};

		bool is_object() const {
		return v_ == unknown ? false : true;
		}

		file_magic() : v_(unknown) {}
		file_magic(_ v) : v_(v) {}
		explicit file_magic(int v) : v_(_(v)) {}
		operator int() const {return v_;}

		private:
		int v_;
		};

	/// @}	/// @}
	/// @name Physical Operators	/// @name Physical Operators
	/// @{	/// @{

	/// @brief Make \a path an absolute path.	/// @brief Make \a path an absolute path.
	///	///
	/// Makes \a path absolute using the current directory if it is not already . An	/// Makes \a path absolute using the current directory if it is not already . An
	/// empty \a path will result in the current directory.	/// empty \a path will result in the current directory.
	///	///
	/// /absolute/path => /absolute/path	/// /absolute/path => /absolute/path

	skipping to change at line 244	skipping to change at line 302
	/// @param B Input file_status.	/// @param B Input file_status.
	///	///
	/// assert(status_known(A) \|\| status_known(B));	/// assert(status_known(A) \|\| status_known(B));
	///	///
	/// @results True if A and B both represent the same file system entity, fa lse	/// @results True if A and B both represent the same file system entity, fa lse
	/// otherwise.	/// otherwise.
	bool equivalent(file_status A, file_status B);	bool equivalent(file_status A, file_status B);

	/// @brief Do paths represent the same thing?	/// @brief Do paths represent the same thing?
	///	///

		/// assert(status_known(A) \|\| status_known(B));
		///
	/// @param A Input path A.	/// @param A Input path A.
	/// @param B Input path B.	/// @param B Input path B.
	/// @param result Set to true if stat(A) and stat(B) have the same device a nd	/// @param result Set to true if stat(A) and stat(B) have the same device a nd
	/// inode (or equivalent).	/// inode (or equivalent).
	/// @results errc::success if result has been successfully set, otherwise a	/// @results errc::success if result has been successfully set, otherwise a
	/// platform specific error_code.	/// platform specific error_code.
	error_code equivalent(const Twine &A, const Twine &B, bool &result);	error_code equivalent(const Twine &A, const Twine &B, bool &result);

	/// @brief Get file size.	/// @brief Get file size.
	///	///

	skipping to change at line 400	skipping to change at line 460
	/// @param len Number of magic bytes to get.	/// @param len Number of magic bytes to get.
	/// @param result Set to the first \a len bytes in the file pointed to by	/// @param result Set to the first \a len bytes in the file pointed to by
	/// \a path. Or the entire file if file_size(path) < len, in which	/// \a path. Or the entire file if file_size(path) < len, in which
	/// case result.size() returns the size of the file.	/// case result.size() returns the size of the file.
	/// @results errc::success if result has been successfully set,	/// @results errc::success if result has been successfully set,
	/// errc::value_too_large if len is larger then the file pointed t o by	/// errc::value_too_large if len is larger then the file pointed t o by
	/// \a path, otherwise a platform specific error_code.	/// \a path, otherwise a platform specific error_code.
	error_code get_magic(const Twine &path, uint32_t len,	error_code get_magic(const Twine &path, uint32_t len,
	SmallVectorImpl<char> &result);	SmallVectorImpl<char> &result);


		/// @brief Identify the type of a binary file based on how magical it is.
		file_magic identify_magic(StringRef magic);

	/// @brief Get and identify \a path's type based on its content.	/// @brief Get and identify \a path's type based on its content.
	///	///
	/// @param path Input path.	/// @param path Input path.
	/// @param result Set to the type of file, or LLVMFileType::Unknown_FileTyp e.	/// @param result Set to the type of file, or LLVMFileType::Unknown_FileTyp e.
	/// @results errc::success if result has been successfully set, otherwise a	/// @results errc::success if result has been successfully set, otherwise a
	/// platform specific error_code.	/// platform specific error_code.

	error_code identify_magic(const Twine &path, LLVMFileType &result);	error_code identify_magic(const Twine &path, file_magic &result);

	/// @brief Get library paths the system linker uses.	/// @brief Get library paths the system linker uses.
	///	///
	/// @param result Set to the list of system library paths.	/// @param result Set to the list of system library paths.
	/// @results errc::success if result has been successfully set, otherwise a	/// @results errc::success if result has been successfully set, otherwise a
	/// platform specific error_code.	/// platform specific error_code.
	error_code GetSystemLibraryPaths(SmallVectorImpl<std::string> &result);	error_code GetSystemLibraryPaths(SmallVectorImpl<std::string> &result);

	/// @brief Get bitcode library paths the system linker uses	/// @brief Get bitcode library paths the system linker uses
	/// + LLVM_LIB_SEARCH_PATH + LLVM_LIBDIR.	/// + LLVM_LIB_SEARCH_PATH + LLVM_LIBDIR.

	skipping to change at line 482	skipping to change at line 545
	error_code status(file_status &result) const;	error_code status(file_status &result) const;

	bool operator==(const directory_entry& rhs) const { return Path == rhs.Pa th; }	bool operator==(const directory_entry& rhs) const { return Path == rhs.Pa th; }
	bool operator!=(const directory_entry& rhs) const { return !(*this == rhs ); }	bool operator!=(const directory_entry& rhs) const { return !(*this == rhs ); }
	bool operator< (const directory_entry& rhs) const;	bool operator< (const directory_entry& rhs) const;
	bool operator<=(const directory_entry& rhs) const;	bool operator<=(const directory_entry& rhs) const;
	bool operator> (const directory_entry& rhs) const;	bool operator> (const directory_entry& rhs) const;
	bool operator>=(const directory_entry& rhs) const;	bool operator>=(const directory_entry& rhs) const;
	};	};


		namespace detail {
		struct DirIterState;

		error_code directory_iterator_construct(DirIterState&, StringRef);
		error_code directory_iterator_increment(DirIterState&);
		error_code directory_iterator_destruct(DirIterState&);

		/// DirIterState - Keeps state for the directory_iterator. It is referenc
		e
		/// counted in order to preserve InputIterator semantics on copy.
		struct DirIterState : public RefCountedBase<DirIterState> {
		DirIterState()
		: IterationHandle(0) {}

		~DirIterState() {
		directory_iterator_destruct(*this);
		}

		intptr_t IterationHandle;
		directory_entry CurrentEntry;
		};
		}

	/// directory_iterator - Iterates through the entries in path. There is no	/// directory_iterator - Iterates through the entries in path. There is no
	/// operator++ because we need an error_code. If it's really needed we can make	/// operator++ because we need an error_code. If it's really needed we can make
	/// it call report_fatal_error on error.	/// it call report_fatal_error on error.
	class directory_iterator {	class directory_iterator {

	intptr_t IterationHandle;	IntrusiveRefCntPtr<detail::DirIterState> State;
	directory_entry CurrentEntry;

	// Platform implementations implement these functions to handle iteration
	.
	friend error_code directory_iterator_construct(directory_iterator &it,
	StringRef path);
	friend error_code directory_iterator_increment(directory_iterator &it);
	friend error_code directory_iterator_destruct(directory_iterator &it);

	public:	public:

	explicit directory_iterator(const Twine &path, error_code &ec)	explicit directory_iterator(const Twine &path, error_code &ec) {
	: IterationHandle(0) {	State = new detail::DirIterState;
	SmallString<128> path_storage;	SmallString<128> path_storage;

	ec = directory_iterator_construct(*this, path.toStringRef(path_storage)	ec = detail::directory_iterator_construct(*State,
	);	path.toStringRef(path_storage));
	}	}


	/// Construct end iterator.	explicit directory_iterator(const directory_entry &de, error_code &ec) {
	directory_iterator() : IterationHandle(0) {}	State = new detail::DirIterState;
		ec = detail::directory_iterator_construct(*State, de.path());
	~directory_iterator() {
	directory_iterator_destruct(*this);
	}	}


		/// Construct end iterator.
		directory_iterator() : State(new detail::DirIterState) {}

	// No operator++ because we need error_code.	// No operator++ because we need error_code.
	directory_iterator &increment(error_code &ec) {	directory_iterator &increment(error_code &ec) {

	ec = directory_iterator_increment(*this);	ec = directory_iterator_increment(*State);
	return *this;	return *this;
	}	}


	const directory_entry &operator*() const { return CurrentEntry; }	const directory_entry &operator*() const { return State->CurrentEntry; }
	const directory_entry *operator->() const { return &CurrentEntry; }	const directory_entry *operator->() const { return &State->CurrentEntry;
		}

		bool operator==(const directory_iterator &RHS) const {
		return State->CurrentEntry == RHS.State->CurrentEntry;
		}

	bool operator!=(const directory_iterator &RHS) const {	bool operator!=(const directory_iterator &RHS) const {

	return CurrentEntry != RHS.CurrentEntry;	return !(*this == RHS);
	}	}
	// Other members as required by	// Other members as required by
	// C++ Std, 24.1.1 Input iterators [input.iterators]	// C++ Std, 24.1.1 Input iterators [input.iterators]
	};	};


		namespace detail {
		/// RecDirIterState - Keeps state for the recursive_directory_iterator. I
		t is
		/// reference counted in order to preserve InputIterator semantics on cop
		y.
		struct RecDirIterState : public RefCountedBase<RecDirIterState> {
		RecDirIterState()
		: Level(0)
		, HasNoPushRequest(false) {}

		std::stack<directory_iterator, std::vector<directory_iterator> > Stack;
		uint16_t Level;
		bool HasNoPushRequest;
		};
		}

	/// recursive_directory_iterator - Same as directory_iterator except for it	/// recursive_directory_iterator - Same as directory_iterator except for it
	/// recurses down into child directories.	/// recurses down into child directories.
	class recursive_directory_iterator {	class recursive_directory_iterator {

	uint16_t Level;	IntrusiveRefCntPtr<detail::RecDirIterState> State;
	bool HasNoPushRequest;
	// implementation directory iterator status

	public:	public:

	explicit recursive_directory_iterator(const Twine &path, error_code &ec);	recursive_directory_iterator() {}
		explicit recursive_directory_iterator(const Twine &path, error_code &ec)
		: State(new detail::RecDirIterState) {
		State->Stack.push(directory_iterator(path, ec));
		if (State->Stack.top() == directory_iterator())
		State.reset();
		}
	// No operator++ because we need error_code.	// No operator++ because we need error_code.

	directory_iterator &increment(error_code &ec);	recursive_directory_iterator &increment(error_code &ec) {
		static const directory_iterator end_itr;


	const directory_entry &operator*() const;	if (State->HasNoPushRequest)
	const directory_entry *operator->() const;	State->HasNoPushRequest = false;
		else {
		file_status st;
		if ((ec = State->Stack.top()->status(st))) return *this;
		if (is_directory(st)) {
		State->Stack.push(directory_iterator(*State->Stack.top(), ec));
		if (ec) return *this;
		if (State->Stack.top() != end_itr) {
		++State->Level;
		return *this;
		}
		State->Stack.pop();
		}
		}

		while (!State->Stack.empty()
		&& State->Stack.top().increment(ec) == end_itr) {
		State->Stack.pop();
		--State->Level;
		}

		// Check if we are done. If so, create an end iterator.
		if (State->Stack.empty())
		State.reset();

		return *this;
		}

		const directory_entry &operator() const { return State->Stack.top(); }
		const directory_entry operator->() const { return &State->Stack.top();
		}

	// observers	// observers

	/// Gets the current level. path is at level 0.	/// Gets the current level. Starting path is at level 0.
	int level() const;	int level() const { return State->Level; }

	/// Returns true if no_push has been called for this directory_entry.	/// Returns true if no_push has been called for this directory_entry.

	bool no_push_request() const;	bool no_push_request() const { return State->HasNoPushRequest; }

	// modifiers	// modifiers
	/// Goes up one level if Level > 0.	/// Goes up one level if Level > 0.

	void pop();	void pop() {
		assert(State && "Cannot pop and end itertor!");
		assert(State->Level > 0 && "Cannot pop an iterator with level < 1");

		static const directory_iterator end_itr;
		error_code ec;
		do {
		if (ec)
		report_fatal_error("Error incrementing directory iterator.");
		State->Stack.pop();
		--State->Level;
		} while (!State->Stack.empty()
		&& State->Stack.top().increment(ec) == end_itr);

		// Check if we are done. If so, create an end iterator.
		if (State->Stack.empty())
		State.reset();
		}

	/// Does not go down into the current directory_entry.	/// Does not go down into the current directory_entry.

	void no_push();	void no_push() { State->HasNoPushRequest = true; }


		bool operator==(const recursive_directory_iterator &RHS) const {
		return State == RHS.State;
		}

		bool operator!=(const recursive_directory_iterator &RHS) const {
		return !(*this == RHS);
		}
	// Other members as required by	// Other members as required by
	// C++ Std, 24.1.1 Input iterators [input.iterators]	// C++ Std, 24.1.1 Input iterators [input.iterators]
	};	};

	/// @}	/// @}

	} // end namespace fs	} // end namespace fs
	} // end namespace sys	} // end namespace sys
	} // end namespace llvm	} // end namespace llvm


End of changes. 28 change blocks.
	37 lines changed or deleted	199 lines changed or added

	FunctionLoweringInfo.h	FunctionLoweringInfo.h

	skipping to change at line 24	skipping to change at line 24

	#ifndef LLVM_CODEGEN_FUNCTIONLOWERINGINFO_H	#ifndef LLVM_CODEGEN_FUNCTIONLOWERINGINFO_H
	#define LLVM_CODEGEN_FUNCTIONLOWERINGINFO_H	#define LLVM_CODEGEN_FUNCTIONLOWERINGINFO_H

	#include "llvm/InlineAsm.h"	#include "llvm/InlineAsm.h"
	#include "llvm/Instructions.h"	#include "llvm/Instructions.h"
	#include "llvm/ADT/APInt.h"	#include "llvm/ADT/APInt.h"
	#include "llvm/ADT/DenseMap.h"	#include "llvm/ADT/DenseMap.h"
	#include "llvm/ADT/DenseSet.h"	#include "llvm/ADT/DenseSet.h"
	#include "llvm/ADT/IndexedMap.h"	#include "llvm/ADT/IndexedMap.h"

		#include "llvm/ADT/SmallPtrSet.h"
	#include "llvm/ADT/SmallVector.h"	#include "llvm/ADT/SmallVector.h"

	#ifndef NDEBUG
	#include "llvm/ADT/SmallSet.h"
	#endif
	#include "llvm/Analysis/BranchProbabilityInfo.h"	#include "llvm/Analysis/BranchProbabilityInfo.h"
	#include "llvm/CodeGen/ValueTypes.h"	#include "llvm/CodeGen/ValueTypes.h"
	#include "llvm/CodeGen/ISDOpcodes.h"	#include "llvm/CodeGen/ISDOpcodes.h"
	#include "llvm/CodeGen/MachineBasicBlock.h"	#include "llvm/CodeGen/MachineBasicBlock.h"
	#include "llvm/Support/CallSite.h"	#include "llvm/Support/CallSite.h"
	#include "llvm/Target/TargetRegisterInfo.h"	#include "llvm/Target/TargetRegisterInfo.h"
	#include <vector>	#include <vector>

	namespace llvm {	namespace llvm {


	skipping to change at line 101	skipping to change at line 99
	/// RegFixups - Registers which need to be replaced after isel is done.	/// RegFixups - Registers which need to be replaced after isel is done.
	DenseMap<unsigned, unsigned> RegFixups;	DenseMap<unsigned, unsigned> RegFixups;

	/// MBB - The current block.	/// MBB - The current block.
	MachineBasicBlock *MBB;	MachineBasicBlock *MBB;

	/// MBB - The current insert position inside the current block.	/// MBB - The current insert position inside the current block.
	MachineBasicBlock::iterator InsertPt;	MachineBasicBlock::iterator InsertPt;

	#ifndef NDEBUG	#ifndef NDEBUG

	SmallSet<const Instruction *, 8> CatchInfoLost;	SmallPtrSet<const Instruction *, 8> CatchInfoLost;
	SmallSet<const Instruction *, 8> CatchInfoFound;	SmallPtrSet<const Instruction *, 8> CatchInfoFound;
	#endif	#endif

	struct LiveOutInfo {	struct LiveOutInfo {
	unsigned NumSignBits : 31;	unsigned NumSignBits : 31;
	bool IsValid : 1;	bool IsValid : 1;
	APInt KnownOne, KnownZero;	APInt KnownOne, KnownZero;
	LiveOutInfo() : NumSignBits(0), IsValid(true), KnownOne(1, 0),	LiveOutInfo() : NumSignBits(0), IsValid(true), KnownOne(1, 0),
	KnownZero(1, 0) {}	KnownZero(1, 0) {}
	};	};

	/// VisitedBBs - The set of basic blocks visited thus far by instruction	/// VisitedBBs - The set of basic blocks visited thus far by instruction
	/// selection.	/// selection.

	DenseSet<const BasicBlock*> VisitedBBs;	SmallPtrSet<const BasicBlock*, 4> VisitedBBs;

	/// PHINodesToUpdate - A list of phi instructions whose operand list will	/// PHINodesToUpdate - A list of phi instructions whose operand list will
	/// be updated after processing the current basic block.	/// be updated after processing the current basic block.
	/// TODO: This isn't per-function state, it's per-basic-block state. But	/// TODO: This isn't per-function state, it's per-basic-block state. But
	/// there's no other convenient place for it to live right now.	/// there's no other convenient place for it to live right now.
	std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;	std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;

	explicit FunctionLoweringInfo(const TargetLowering &TLI);	explicit FunctionLoweringInfo(const TargetLowering &TLI);

	/// set - Initialize this FunctionLoweringInfo with the given Function	/// set - Initialize this FunctionLoweringInfo with the given Function

	skipping to change at line 214	skipping to change at line 212
	void setArgumentFrameIndex(const Argument *A, int FI);	void setArgumentFrameIndex(const Argument *A, int FI);

	/// getArgumentFrameIndex - Get frame index for the byval argument.	/// getArgumentFrameIndex - Get frame index for the byval argument.
	int getArgumentFrameIndex(const Argument *A);	int getArgumentFrameIndex(const Argument *A);

	private:	private:
	/// LiveOutRegInfo - Information about live out vregs.	/// LiveOutRegInfo - Information about live out vregs.
	IndexedMap<LiveOutInfo, VirtReg2IndexFunctor> LiveOutRegInfo;	IndexedMap<LiveOutInfo, VirtReg2IndexFunctor> LiveOutRegInfo;
	};	};


		/// ComputeUsesVAFloatArgument - Determine if any floating-point values are
		/// being passed to this variadic function, and set the MachineModuleInfo's
		/// usesVAFloatArgument flag if so. This flag is used to emit an undefined
		/// reference to _fltused on Windows, which will link in MSVCRT's
		/// floating-point support.
		void ComputeUsesVAFloatArgument(const CallInst &I, MachineModuleInfo *MMI);

	/// AddCatchInfo - Extract the personality and type infos from an eh.select or	/// AddCatchInfo - Extract the personality and type infos from an eh.select or
	/// call, and add them to the specified machine basic block.	/// call, and add them to the specified machine basic block.
	void AddCatchInfo(const CallInst &I,	void AddCatchInfo(const CallInst &I,
	MachineModuleInfo MMI, MachineBasicBlock MBB);	MachineModuleInfo MMI, MachineBasicBlock MBB);


	/// CopyCatchInfo - Copy catch information from SuccBB (or one of its
	/// successors) to LPad.
	void CopyCatchInfo(const BasicBlock SuccBB, const BasicBlock LPad,
	MachineModuleInfo *MMI, FunctionLoweringInfo &FLI);

	/// AddLandingPadInfo - Extract the exception handling information from the	/// AddLandingPadInfo - Extract the exception handling information from the
	/// landingpad instruction and add them to the specified machine module inf o.	/// landingpad instruction and add them to the specified machine module inf o.
	void AddLandingPadInfo(const LandingPadInst &I, MachineModuleInfo &MMI,	void AddLandingPadInfo(const LandingPadInst &I, MachineModuleInfo &MMI,
	MachineBasicBlock *MBB);	MachineBasicBlock *MBB);

	} // end namespace llvm	} // end namespace llvm

	#endif	#endif

End of changes. 6 change blocks.
	11 lines changed or deleted	11 lines changed or added

	Graph.h	Graph.h

	skipping to change at line 352	skipping to change at line 352
	--numEdges;	--numEdges;
	}	}

	/// \brief Remove all nodes and edges from the graph.	/// \brief Remove all nodes and edges from the graph.
	void clear() {	void clear() {
	nodes.clear();	nodes.clear();
	edges.clear();	edges.clear();
	numNodes = numEdges = 0;	numNodes = numEdges = 0;
	}	}


		/// \brief Dump a graph to an output stream.
		template <typename OStream>
		void dump(OStream &os) {
		os << getNumNodes() << " " << getNumEdges() << "\n";

		for (NodeItr nodeItr = nodesBegin(), nodeEnd = nodesEnd();
		nodeItr != nodeEnd; ++nodeItr) {
		const Vector& v = getNodeCosts(nodeItr);
		os << "\n" << v.getLength() << "\n";
		assert(v.getLength() != 0 && "Empty vector in graph.");
		os << v[0];
		for (unsigned i = 1; i < v.getLength(); ++i) {
		os << " " << v[i];
		}
		os << "\n";
		}

		for (EdgeItr edgeItr = edgesBegin(), edgeEnd = edgesEnd();
		edgeItr != edgeEnd; ++edgeItr) {
		unsigned n1 = std::distance(nodesBegin(), getEdgeNode1(edgeItr));
		unsigned n2 = std::distance(nodesBegin(), getEdgeNode2(edgeItr));
		assert(n1 != n2 && "PBQP graphs shound not have self-edges.");
		const Matrix& m = getEdgeCosts(edgeItr);
		os << "\n" << n1 << " " << n2 << "\n"
		<< m.getRows() << " " << m.getCols() << "\n";
		assert(m.getRows() != 0 && "No rows in matrix.");
		assert(m.getCols() != 0 && "No cols in matrix.");
		for (unsigned i = 0; i < m.getRows(); ++i) {
		os << m[i][0];
		for (unsigned j = 1; j < m.getCols(); ++j) {
		os << " " << m[i][j];
		}
		os << "\n";
		}
		}
		}

	/// \brief Print a representation of this graph in DOT format.	/// \brief Print a representation of this graph in DOT format.
	/// @param os Output stream to print on.	/// @param os Output stream to print on.
	template <typename OStream>	template <typename OStream>
	void printDot(OStream &os) {	void printDot(OStream &os) {

	os << "graph {\n";	os << "graph {\n";

	for (NodeItr nodeItr = nodesBegin(), nodeEnd = nodesEnd();	for (NodeItr nodeItr = nodesBegin(), nodeEnd = nodesEnd();
	nodeItr != nodeEnd; ++nodeItr) {	nodeItr != nodeEnd; ++nodeItr) {


End of changes. 1 change blocks.
	0 lines changed or deleted	37 lines changed or added

	GraphWriter.h	GraphWriter.h

	skipping to change at line 299	skipping to change at line 299
	/// getOStream - Get the raw output stream into the graph file. Useful to	/// getOStream - Get the raw output stream into the graph file. Useful to
	/// write fancy things using addCustomGraphFeatures().	/// write fancy things using addCustomGraphFeatures().
	raw_ostream &getOStream() {	raw_ostream &getOStream() {
	return O;	return O;
	}	}
	};	};

	template<typename GraphType>	template<typename GraphType>
	raw_ostream &WriteGraph(raw_ostream &O, const GraphType &G,	raw_ostream &WriteGraph(raw_ostream &O, const GraphType &G,
	bool ShortNames = false,	bool ShortNames = false,

	const std::string &Title = "") {	const Twine &Title = "") {
	// Start the graph emission process...	// Start the graph emission process...
	GraphWriter<GraphType> W(O, G, ShortNames);	GraphWriter<GraphType> W(O, G, ShortNames);

	// Emit the graph.	// Emit the graph.

	W.writeGraph(Title);	W.writeGraph(Title.str());

	return O;	return O;
	}	}

	template<typename GraphType>	template<typename GraphType>

	sys::Path WriteGraph(const GraphType &G, const std::string &Name,	sys::Path WriteGraph(const GraphType &G, const Twine &Name,
	bool ShortNames = false, const std::string &Title = ""	bool ShortNames = false, const Twine &Title = "") {
	) {
	std::string ErrMsg;	std::string ErrMsg;
	sys::Path Filename = sys::Path::GetTemporaryDirectory(&ErrMsg);	sys::Path Filename = sys::Path::GetTemporaryDirectory(&ErrMsg);
	if (Filename.isEmpty()) {	if (Filename.isEmpty()) {
	errs() << "Error: " << ErrMsg << "\n";	errs() << "Error: " << ErrMsg << "\n";
	return Filename;	return Filename;
	}	}

	Filename.appendComponent(Name + ".dot");	Filename.appendComponent((Name + ".dot").str());
	if (Filename.makeUnique(true,&ErrMsg)) {	if (Filename.makeUnique(true,&ErrMsg)) {
	errs() << "Error: " << ErrMsg << "\n";	errs() << "Error: " << ErrMsg << "\n";
	return sys::Path();	return sys::Path();
	}	}

	errs() << "Writing '" << Filename.str() << "'... ";	errs() << "Writing '" << Filename.str() << "'... ";

	std::string ErrorInfo;	std::string ErrorInfo;
	raw_fd_ostream O(Filename.c_str(), ErrorInfo);	raw_fd_ostream O(Filename.c_str(), ErrorInfo);


	skipping to change at line 344	skipping to change at line 344
	Filename.clear();	Filename.clear();
	}	}

	return Filename;	return Filename;
	}	}

	/// ViewGraph - Emit a dot graph, run 'dot', run gv on the postscript file,	/// ViewGraph - Emit a dot graph, run 'dot', run gv on the postscript file,
	/// then cleanup. For use from the debugger.	/// then cleanup. For use from the debugger.
	///	///
	template<typename GraphType>	template<typename GraphType>

	void ViewGraph(const GraphType &G, const std::string &Name,	void ViewGraph(const GraphType &G, const Twine &Name,
	bool ShortNames = false, const std::string &Title = "",	bool ShortNames = false, const Twine &Title = "",
	GraphProgram::Name Program = GraphProgram::DOT) {	GraphProgram::Name Program = GraphProgram::DOT) {
	sys::Path Filename = llvm::WriteGraph(G, Name, ShortNames, Title);	sys::Path Filename = llvm::WriteGraph(G, Name, ShortNames, Title);

	if (Filename.isEmpty())	if (Filename.isEmpty())
	return;	return;

	DisplayGraph(Filename, true, Program);	DisplayGraph(Filename, true, Program);
	}	}

	} // End llvm namespace	} // End llvm namespace

End of changes. 5 change blocks.
	8 lines changed or deleted	7 lines changed or added

	Host.h	Host.h

	skipping to change at line 36	skipping to change at line 36
	char c;	char c;
	};	};
	i = 1;	i = 1;
	return c;	return c;
	}	}

	inline bool isBigEndianHost() {	inline bool isBigEndianHost() {
	return !isLittleEndianHost();	return !isLittleEndianHost();
	}	}


	/// getHostTriple() - Return the target triple of the running	/// getDefaultTargetTriple() - Return the default target triple the compi
	/// system.	ler
		/// has been configured to produce code for.
	///	///
	/// The target triple is a string in the format of:	/// The target triple is a string in the format of:
	/// CPU_TYPE-VENDOR-OPERATING_SYSTEM	/// CPU_TYPE-VENDOR-OPERATING_SYSTEM
	/// or	/// or
	/// CPU_TYPE-VENDOR-KERNEL-OPERATING_SYSTEM	/// CPU_TYPE-VENDOR-KERNEL-OPERATING_SYSTEM

	std::string getHostTriple();	std::string getDefaultTargetTriple();

	/// getHostCPUName - Get the LLVM name for the host CPU. The particular f ormat	/// getHostCPUName - Get the LLVM name for the host CPU. The particular f ormat
	/// of the name is target dependent, and suitable for passing as -mcpu to the	/// of the name is target dependent, and suitable for passing as -mcpu to the
	/// target which matches the host.	/// target which matches the host.
	///	///
	/// \return - The host CPU name, or empty if the CPU could not be determi ned.	/// \return - The host CPU name, or empty if the CPU could not be determi ned.
	std::string getHostCPUName();	std::string getHostCPUName();

	/// getHostCPUFeatures - Get the LLVM names for the host CPU features.	/// getHostCPUFeatures - Get the LLVM names for the host CPU features.
	/// The particular format of the names are target dependent, and suitable for	/// The particular format of the names are target dependent, and suitable for

End of changes. 2 change blocks.
	3 lines changed or deleted	4 lines changed or added

	IRReader.h	IRReader.h

	skipping to change at line 43	skipping to change at line 43
	/// parse it as LLVM Assembly and return a fully populated Module. This	/// parse it as LLVM Assembly and return a fully populated Module. This
	/// function always takes ownership of the given MemoryBuffer.	/// function always takes ownership of the given MemoryBuffer.
	inline Module getLazyIRModule(MemoryBuffer Buffer,	inline Module getLazyIRModule(MemoryBuffer Buffer,
	SMDiagnostic &Err,	SMDiagnostic &Err,
	LLVMContext &Context) {	LLVMContext &Context) {
	if (isBitcode((const unsigned char *)Buffer->getBufferStart(),	if (isBitcode((const unsigned char *)Buffer->getBufferStart(),
	(const unsigned char *)Buffer->getBufferEnd())) {	(const unsigned char *)Buffer->getBufferEnd())) {
	std::string ErrMsg;	std::string ErrMsg;
	Module *M = getLazyBitcodeModule(Buffer, Context, &ErrMsg);	Module *M = getLazyBitcodeModule(Buffer, Context, &ErrMsg);
	if (M == 0) {	if (M == 0) {

	Err = SMDiagnostic(Buffer->getBufferIdentifier(), ErrMsg);	Err = SMDiagnostic(Buffer->getBufferIdentifier(), SourceMgr::DK_Err
		or,
		ErrMsg);
	// ParseBitcodeFile does not take ownership of the Buffer in the	// ParseBitcodeFile does not take ownership of the Buffer in the
	// case of an error.	// case of an error.
	delete Buffer;	delete Buffer;
	}	}
	return M;	return M;
	}	}

	return ParseAssembly(Buffer, 0, Err, Context);	return ParseAssembly(Buffer, 0, Err, Context);
	}	}

	/// If the given file holds a bitcode image, return a Module	/// If the given file holds a bitcode image, return a Module
	/// for it which does lazy deserialization of function bodies. Otherwise ,	/// for it which does lazy deserialization of function bodies. Otherwise ,
	/// attempt to parse it as LLVM Assembly and return a fully populated	/// attempt to parse it as LLVM Assembly and return a fully populated
	/// Module.	/// Module.
	inline Module *getLazyIRFileModule(const std::string &Filename,	inline Module *getLazyIRFileModule(const std::string &Filename,
	SMDiagnostic &Err,	SMDiagnostic &Err,
	LLVMContext &Context) {	LLVMContext &Context) {
	OwningPtr<MemoryBuffer> File;	OwningPtr<MemoryBuffer> File;
	if (error_code ec = MemoryBuffer::getFileOrSTDIN(Filename.c_str(), File )) {	if (error_code ec = MemoryBuffer::getFileOrSTDIN(Filename.c_str(), File )) {

	Err = SMDiagnostic(Filename,	Err = SMDiagnostic(Filename, SourceMgr::DK_Error,
	"Could not open input file: " + ec.message());	"Could not open input file: " + ec.message());
	return 0;	return 0;
	}	}

	return getLazyIRModule(File.take(), Err, Context);	return getLazyIRModule(File.take(), Err, Context);
	}	}

	/// If the given MemoryBuffer holds a bitcode image, return a Module	/// If the given MemoryBuffer holds a bitcode image, return a Module
	/// for it. Otherwise, attempt to parse it as LLVM Assembly and return	/// for it. Otherwise, attempt to parse it as LLVM Assembly and return
	/// a Module for it. This function always takes ownership of the given	/// a Module for it. This function always takes ownership of the given
	/// MemoryBuffer.	/// MemoryBuffer.
	inline Module ParseIR(MemoryBuffer Buffer,	inline Module ParseIR(MemoryBuffer Buffer,
	SMDiagnostic &Err,	SMDiagnostic &Err,
	LLVMContext &Context) {	LLVMContext &Context) {
	if (isBitcode((const unsigned char *)Buffer->getBufferStart(),	if (isBitcode((const unsigned char *)Buffer->getBufferStart(),
	(const unsigned char *)Buffer->getBufferEnd())) {	(const unsigned char *)Buffer->getBufferEnd())) {
	std::string ErrMsg;	std::string ErrMsg;
	Module *M = ParseBitcodeFile(Buffer, Context, &ErrMsg);	Module *M = ParseBitcodeFile(Buffer, Context, &ErrMsg);
	if (M == 0)	if (M == 0)

	Err = SMDiagnostic(Buffer->getBufferIdentifier(), ErrMsg);	Err = SMDiagnostic(Buffer->getBufferIdentifier(), SourceMgr::DK_Err
		or,
		ErrMsg);
	// ParseBitcodeFile does not take ownership of the Buffer.	// ParseBitcodeFile does not take ownership of the Buffer.
	delete Buffer;	delete Buffer;
	return M;	return M;
	}	}

	return ParseAssembly(Buffer, 0, Err, Context);	return ParseAssembly(Buffer, 0, Err, Context);
	}	}

	/// If the given file holds a bitcode image, return a Module for it.	/// If the given file holds a bitcode image, return a Module for it.
	/// Otherwise, attempt to parse it as LLVM Assembly and return a Module	/// Otherwise, attempt to parse it as LLVM Assembly and return a Module
	/// for it.	/// for it.
	inline Module *ParseIRFile(const std::string &Filename,	inline Module *ParseIRFile(const std::string &Filename,
	SMDiagnostic &Err,	SMDiagnostic &Err,
	LLVMContext &Context) {	LLVMContext &Context) {
	OwningPtr<MemoryBuffer> File;	OwningPtr<MemoryBuffer> File;
	if (error_code ec = MemoryBuffer::getFileOrSTDIN(Filename.c_str(), File )) {	if (error_code ec = MemoryBuffer::getFileOrSTDIN(Filename.c_str(), File )) {

	Err = SMDiagnostic(Filename,	Err = SMDiagnostic(Filename, SourceMgr::DK_Error,
	"Could not open input file: " + ec.message());	"Could not open input file: " + ec.message());
	return 0;	return 0;
	}	}

	return ParseIR(File.take(), Err, Context);	return ParseIR(File.take(), Err, Context);
	}	}

	}	}

	#endif	#endif

End of changes. 4 change blocks.
	4 lines changed or deleted	8 lines changed or added

	ISDOpcodes.h	ISDOpcodes.h

	skipping to change at line 60	skipping to change at line 60
	TokenFactor,	TokenFactor,

	// AssertSext, AssertZext - These nodes record if a register contains a	// AssertSext, AssertZext - These nodes record if a register contains a
	// value that has already been zero or sign extended from a narrower ty pe.	// value that has already been zero or sign extended from a narrower ty pe.
	// These nodes take two operands. The first is the node that has alrea dy	// These nodes take two operands. The first is the node that has alrea dy
	// been extended, and the second is a value type node indicating the wi dth	// been extended, and the second is a value type node indicating the wi dth
	// of the extension	// of the extension
	AssertSext, AssertZext,	AssertSext, AssertZext,

	// Various leaf nodes.	// Various leaf nodes.

	BasicBlock, VALUETYPE, CONDCODE, Register,	BasicBlock, VALUETYPE, CONDCODE, Register, RegisterMask,
	Constant, ConstantFP,	Constant, ConstantFP,
	GlobalAddress, GlobalTLSAddress, FrameIndex,	GlobalAddress, GlobalTLSAddress, FrameIndex,
	JumpTable, ConstantPool, ExternalSymbol, BlockAddress,	JumpTable, ConstantPool, ExternalSymbol, BlockAddress,

	// The address of the GOT	// The address of the GOT
	GLOBAL_OFFSET_TABLE,	GLOBAL_OFFSET_TABLE,

	// FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and	// FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and
	// llvm.returnaddress on the DAG. These nodes take one operand, the in dex	// llvm.returnaddress on the DAG. These nodes take one operand, the in dex
	// of the frame or return address to return. An index of zero correspo nds	// of the frame or return address to return. An index of zero correspo nds

	skipping to change at line 110	skipping to change at line 110
	// It takes an input chain and a pointer to the jump buffer as inputs	// It takes an input chain and a pointer to the jump buffer as inputs
	// and returns an outchain.	// and returns an outchain.
	EH_SJLJ_SETJMP,	EH_SJLJ_SETJMP,

	// OUTCHAIN = EH_SJLJ_LONGJMP(INCHAIN, buffer)	// OUTCHAIN = EH_SJLJ_LONGJMP(INCHAIN, buffer)
	// This corresponds to the eh.sjlj.longjmp intrinsic.	// This corresponds to the eh.sjlj.longjmp intrinsic.
	// It takes an input chain and a pointer to the jump buffer as inputs	// It takes an input chain and a pointer to the jump buffer as inputs
	// and returns an outchain.	// and returns an outchain.
	EH_SJLJ_LONGJMP,	EH_SJLJ_LONGJMP,


	// OUTCHAIN = EH_SJLJ_DISPATCHSETUP(INCHAIN, setjmpval)
	// This corresponds to the eh.sjlj.dispatchsetup intrinsic. It takes an
	// input chain and the value returning from setjmp as inputs and return
	s an
	// outchain. By default, this does nothing. Targets can lower this to u
	nwind
	// setup code if needed.
	EH_SJLJ_DISPATCHSETUP,

	// TargetConstant* - Like Constant*, but the DAG does not do any foldin g,	// TargetConstant* - Like Constant*, but the DAG does not do any foldin g,
	// simplification, or lowering of the constant. They are used for const ants	// simplification, or lowering of the constant. They are used for const ants
	// which are known to fit in the immediate fields of their users, or fo r	// which are known to fit in the immediate fields of their users, or fo r
	// carrying magic numbers which are not values which need to be materia lized	// carrying magic numbers which are not values which need to be materia lized
	// in registers.	// in registers.
	TargetConstant,	TargetConstant,
	TargetConstantFP,	TargetConstantFP,

	// TargetGlobalAddress - Like GlobalAddress, but the DAG does no foldin g or	// TargetGlobalAddress - Like GlobalAddress, but the DAG does no foldin g or
	// anything else with this node, and this is valid in the target-specif ic	// anything else with this node, and this is valid in the target-specif ic

	skipping to change at line 322	skipping to change at line 315
	/// large enough. TLI.getShiftAmountTy() is i8 on some targets, but be fore	/// large enough. TLI.getShiftAmountTy() is i8 on some targets, but be fore
	/// legalization, types like i1024 can occur and i8 doesn't have enough bits	/// legalization, types like i1024 can occur and i8 doesn't have enough bits
	/// to represent the shift amount. By convention, DAGCombine and	/// to represent the shift amount. By convention, DAGCombine and
	/// SelectionDAGBuilder forces these shift amounts to i32 for simplicit y.	/// SelectionDAGBuilder forces these shift amounts to i32 for simplicit y.
	///	///
	SHL, SRA, SRL, ROTL, ROTR,	SHL, SRA, SRL, ROTL, ROTR,

	/// Byte Swap and Counting operators.	/// Byte Swap and Counting operators.
	BSWAP, CTTZ, CTLZ, CTPOP,	BSWAP, CTTZ, CTLZ, CTPOP,


		/// Bit counting operators with an undefined result for zero inputs.
		CTTZ_ZERO_UNDEF, CTLZ_ZERO_UNDEF,

	// Select(COND, TRUEVAL, FALSEVAL). If the type of the boolean COND is not	// Select(COND, TRUEVAL, FALSEVAL). If the type of the boolean COND is not
	// i1 then the high bits must conform to getBooleanContents.	// i1 then the high bits must conform to getBooleanContents.
	SELECT,	SELECT,

	// Select with a vector condition (op #0) and two vector operands (ops #1	// Select with a vector condition (op #0) and two vector operands (ops #1
	// and #2), returning a vector result. All vectors have the same lengt h.	// and #2), returning a vector result. All vectors have the same lengt h.
	// Much like the scalar select and setcc, each bit in the condition sel ects	// Much like the scalar select and setcc, each bit in the condition sel ects
	// whether the corresponding result element is taken from op #1 or op # 2.	// whether the corresponding result element is taken from op #1 or op # 2.

		// At first, the VSELECT condition is of vXi1 type. Later, targets may
		change
		// the condition type in order to match the VSELECT node using a a patt
		ern.
		// The condition follows the BooleanContent format of the target.
	VSELECT,	VSELECT,

	// Select with condition operator - This selects between a true value a nd	// Select with condition operator - This selects between a true value a nd
	// a false value (ops #2 and #3) based on the boolean result of compari ng	// a false value (ops #2 and #3) based on the boolean result of compari ng
	// the lhs and rhs (ops #0 and #1) of a conditional expression with the	// the lhs and rhs (ops #0 and #1) of a conditional expression with the
	// condition code in op #4, a CondCodeSDNode.	// condition code in op #4, a CondCodeSDNode.
	SELECT_CC,	SELECT_CC,

	// SetCC operator - This evaluates to a true value iff the condition is	// SetCC operator - This evaluates to a true value iff the condition is
	// true. If the result value type is not i1 then the high bits conform	// true. If the result value type is not i1 then the high bits conform

End of changes. 4 change blocks.
	10 lines changed or deleted	9 lines changed or added

	IVUsers.h	IVUsers.h

	skipping to change at line 169	skipping to change at line 169
	const SCEV getStride(const IVStrideUse &IU, const Loop L) const;	const SCEV getStride(const IVStrideUse &IU, const Loop L) const;

	typedef ilist<IVStrideUse>::iterator iterator;	typedef ilist<IVStrideUse>::iterator iterator;
	typedef ilist<IVStrideUse>::const_iterator const_iterator;	typedef ilist<IVStrideUse>::const_iterator const_iterator;
	iterator begin() { return IVUses.begin(); }	iterator begin() { return IVUses.begin(); }
	iterator end() { return IVUses.end(); }	iterator end() { return IVUses.end(); }
	const_iterator begin() const { return IVUses.begin(); }	const_iterator begin() const { return IVUses.begin(); }
	const_iterator end() const { return IVUses.end(); }	const_iterator end() const { return IVUses.end(); }
	bool empty() const { return IVUses.empty(); }	bool empty() const { return IVUses.empty(); }


		bool isIVUserOrOperand(Instruction *Inst) const {
		return Processed.count(Inst);
		}

	void print(raw_ostream &OS, const Module* = 0) const;	void print(raw_ostream &OS, const Module* = 0) const;

	/// dump - This method is used for debugging.	/// dump - This method is used for debugging.
	void dump() const;	void dump() const;

		protected:
		bool AddUsersImpl(Instruction I, SmallPtrSet<Loop,16> &SimpleLoopNests)
		;
	};	};

	Pass *createIVUsersPass();	Pass *createIVUsersPass();

	}	}

	#endif	#endif

End of changes. 2 change blocks.
	0 lines changed or deleted	7 lines changed or added

	ImmutableSet.h	ImmutableSet.h

	skipping to change at line 21	skipping to change at line 21
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_ADT_IMSET_H	#ifndef LLVM_ADT_IMSET_H
	#define LLVM_ADT_IMSET_H	#define LLVM_ADT_IMSET_H

	#include "llvm/Support/Allocator.h"	#include "llvm/Support/Allocator.h"
	#include "llvm/ADT/DenseMap.h"	#include "llvm/ADT/DenseMap.h"
	#include "llvm/ADT/FoldingSet.h"	#include "llvm/ADT/FoldingSet.h"
	#include "llvm/Support/DataTypes.h"	#include "llvm/Support/DataTypes.h"

		#include "llvm/Support/ErrorHandling.h"
	#include <cassert>	#include <cassert>
	#include <functional>	#include <functional>
	#include <vector>	#include <vector>
	#include <stdio.h>	#include <stdio.h>

	namespace llvm {	namespace llvm {

	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	// Immutable AVL-Tree Definition.	// Immutable AVL-Tree Definition.
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	skipping to change at line 348	skipping to change at line 349
	left->release();	left->release();
	if (right)	if (right)
	right->release();	right->release();
	if (IsCanonicalized) {	if (IsCanonicalized) {
	if (next)	if (next)
	next->prev = prev;	next->prev = prev;

	if (prev)	if (prev)
	prev->next = next;	prev->next = next;
	else	else

	factory->Cache[computeDigest()] = next;	factory->Cache[factory->maskCacheIndex(computeDigest())] = next;
	}	}

	// We need to clear the mutability bit in case we are	// We need to clear the mutability bit in case we are
	// destroying the node as part of a sweep in ImutAVLFactory::recoverNod es().	// destroying the node as part of a sweep in ImutAVLFactory::recoverNod es().
	IsMutable = false;	IsMutable = false;
	factory->freeNodes.push_back(this);	factory->freeNodes.push_back(this);
	}	}
	};	};

	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	skipping to change at line 430	skipping to change at line 431
	// These have succinct names so that the balancing code	// These have succinct names so that the balancing code
	// is as terse (and readable) as possible.	// is as terse (and readable) as possible.
	//===--------------------------------------------------===//	//===--------------------------------------------------===//

	bool isEmpty(TreeTy* T) const { return !T; }	bool isEmpty(TreeTy* T) const { return !T; }
	unsigned getHeight(TreeTy* T) const { return T ? T->getHeight() : 0; }	unsigned getHeight(TreeTy* T) const { return T ? T->getHeight() : 0; }
	TreeTy* getLeft(TreeTy* T) const { return T->getLeft(); }	TreeTy* getLeft(TreeTy* T) const { return T->getLeft(); }
	TreeTy* getRight(TreeTy* T) const { return T->getRight(); }	TreeTy* getRight(TreeTy* T) const { return T->getRight(); }
	value_type_ref getValue(TreeTy* T) const { return T->value; }	value_type_ref getValue(TreeTy* T) const { return T->value; }


		// Make sure the index is not the Tombstone or Entry key of the DenseMap.
		static inline unsigned maskCacheIndex(unsigned I) {
		return (I & ~0x02);
		}

	unsigned incrementHeight(TreeTy* L, TreeTy* R) const {	unsigned incrementHeight(TreeTy* L, TreeTy* R) const {
	unsigned hl = getHeight(L);	unsigned hl = getHeight(L);
	unsigned hr = getHeight(R);	unsigned hr = getHeight(R);
	return (hl > hr ? hl : hr) + 1;	return (hl > hr ? hl : hr) + 1;
	}	}

	static bool compareTreeWithSection(TreeTy* T,	static bool compareTreeWithSection(TreeTy* T,
	typename TreeTy::iterator& TI,	typename TreeTy::iterator& TI,
	typename TreeTy::iterator& TE) {	typename TreeTy::iterator& TE) {
	typename TreeTy::iterator I = T->begin(), E = T->end();	typename TreeTy::iterator I = T->begin(), E = T->end();

	skipping to change at line 612	skipping to change at line 618
	TreeTy getCanonicalTree(TreeTy TNew) {	TreeTy getCanonicalTree(TreeTy TNew) {
	if (!TNew)	if (!TNew)
	return 0;	return 0;

	if (TNew->IsCanonicalized)	if (TNew->IsCanonicalized)
	return TNew;	return TNew;

	// Search the hashtable for another tree with the same digest, and	// Search the hashtable for another tree with the same digest, and
	// if find a collision compare those trees by their contents.	// if find a collision compare those trees by their contents.
	unsigned digest = TNew->computeDigest();	unsigned digest = TNew->computeDigest();

	TreeTy *&entry = Cache[digest];	TreeTy *&entry = Cache[maskCacheIndex(digest)];
	do {	do {
	if (!entry)	if (!entry)
	break;	break;
	for (TreeTy *T = entry ; T != 0; T = T->next) {	for (TreeTy *T = entry ; T != 0; T = T->next) {
	// Compare the Contents('T') with Contents('TNew')	// Compare the Contents('T') with Contents('TNew')
	typename TreeTy::iterator TI = T->begin(), TE = T->end();	typename TreeTy::iterator TI = T->begin(), TE = T->end();
	if (!compareTreeWithSection(TNew, TI, TE))	if (!compareTreeWithSection(TNew, TI, TE))
	continue;	continue;
	if (TI != TE)	if (TI != TE)
	continue; // T has more contents than TNew.	continue; // T has more contents than TNew.

	skipping to change at line 687	skipping to change at line 693
	if (stack.empty())	if (stack.empty())
	return;	return;
	switch (getVisitState()) {	switch (getVisitState()) {
	case VisitedNone:	case VisitedNone:
	stack.back() \|= VisitedLeft;	stack.back() \|= VisitedLeft;
	break;	break;
	case VisitedLeft:	case VisitedLeft:
	stack.back() \|= VisitedRight;	stack.back() \|= VisitedRight;
	break;	break;
	default:	default:

	assert(false && "Unreachable.");	llvm_unreachable("Unreachable.");
	}	}
	}	}

	inline bool operator==(const _Self& x) const {	inline bool operator==(const _Self& x) const {
	if (stack.size() != x.stack.size())	if (stack.size() != x.stack.size())
	return false;	return false;
	for (unsigned i = 0 ; i < stack.size(); i++)	for (unsigned i = 0 ; i < stack.size(); i++)
	if (stack[i] != x.stack[i])	if (stack[i] != x.stack[i])
	return false;	return false;
	return true;	return true;

	skipping to change at line 723	skipping to change at line 729
	case VisitedLeft:	case VisitedLeft:
	if (TreeTy* R = Current->getRight())	if (TreeTy* R = Current->getRight())
	stack.push_back(reinterpret_cast<uintptr_t>(R));	stack.push_back(reinterpret_cast<uintptr_t>(R));
	else	else
	stack.back() \|= VisitedRight;	stack.back() \|= VisitedRight;
	break;	break;
	case VisitedRight:	case VisitedRight:
	skipToParent();	skipToParent();
	break;	break;
	default:	default:

	assert(false && "Unreachable.");	llvm_unreachable("Unreachable.");
	}	}
	return *this;	return *this;
	}	}

	_Self& operator--() {	_Self& operator--() {
	assert(!stack.empty());	assert(!stack.empty());
	TreeTy* Current = reinterpret_cast<TreeTy*>(stack.back() & ~Flags);	TreeTy* Current = reinterpret_cast<TreeTy*>(stack.back() & ~Flags);
	assert(Current);	assert(Current);
	switch (getVisitState()) {	switch (getVisitState()) {
	case VisitedNone:	case VisitedNone:

	skipping to change at line 748	skipping to change at line 754
	if (TreeTy* L = Current->getLeft())	if (TreeTy* L = Current->getLeft())
	stack.push_back(reinterpret_cast<uintptr_t>(L) \| VisitedRight);	stack.push_back(reinterpret_cast<uintptr_t>(L) \| VisitedRight);
	break;	break;
	case VisitedRight:	case VisitedRight:
	stack.back() &= ~Flags;	stack.back() &= ~Flags;
	stack.back() \|= VisitedLeft;	stack.back() \|= VisitedLeft;
	if (TreeTy* R = Current->getRight())	if (TreeTy* R = Current->getRight())
	stack.push_back(reinterpret_cast<uintptr_t>(R) \| VisitedRight);	stack.push_back(reinterpret_cast<uintptr_t>(R) \| VisitedRight);
	break;	break;
	default:	default:

	assert(false && "Unreachable.");	llvm_unreachable("Unreachable.");
	}	}
	return *this;	return *this;
	}	}
	};	};

	template <typename ImutInfo>	template <typename ImutInfo>
	class ImutAVLTreeInOrderIterator {	class ImutAVLTreeInOrderIterator {
	typedef ImutAVLTreeGenericIterator<ImutInfo> InternalIteratorTy;	typedef ImutAVLTreeGenericIterator<ImutInfo> InternalIteratorTy;
	InternalIteratorTy InternalItr;	InternalIteratorTy InternalItr;


End of changes. 7 change blocks.
	5 lines changed or deleted	11 lines changed or added

	Initialization.h	Initialization.h

	skipping to change at line 25	skipping to change at line 25

	#ifndef LLVM_C_INITIALIZEPASSES_H	#ifndef LLVM_C_INITIALIZEPASSES_H
	#define LLVM_C_INITIALIZEPASSES_H	#define LLVM_C_INITIALIZEPASSES_H

	#include "llvm-c/Core.h"	#include "llvm-c/Core.h"

	#ifdef __cplusplus	#ifdef __cplusplus
	extern "C" {	extern "C" {
	#endif	#endif


		/**
		* @defgroup LLVMCInitialization Initialization Routines
		* @ingroup LLVMC
		*
		* This module contains routines used to initialize the LLVM system.
		*
		* @{
		*/

	void LLVMInitializeCore(LLVMPassRegistryRef R);	void LLVMInitializeCore(LLVMPassRegistryRef R);
	void LLVMInitializeTransformUtils(LLVMPassRegistryRef R);	void LLVMInitializeTransformUtils(LLVMPassRegistryRef R);
	void LLVMInitializeScalarOpts(LLVMPassRegistryRef R);	void LLVMInitializeScalarOpts(LLVMPassRegistryRef R);

		void LLVMInitializeVectorization(LLVMPassRegistryRef R);
	void LLVMInitializeInstCombine(LLVMPassRegistryRef R);	void LLVMInitializeInstCombine(LLVMPassRegistryRef R);
	void LLVMInitializeIPO(LLVMPassRegistryRef R);	void LLVMInitializeIPO(LLVMPassRegistryRef R);
	void LLVMInitializeInstrumentation(LLVMPassRegistryRef R);	void LLVMInitializeInstrumentation(LLVMPassRegistryRef R);
	void LLVMInitializeAnalysis(LLVMPassRegistryRef R);	void LLVMInitializeAnalysis(LLVMPassRegistryRef R);
	void LLVMInitializeIPA(LLVMPassRegistryRef R);	void LLVMInitializeIPA(LLVMPassRegistryRef R);
	void LLVMInitializeCodeGen(LLVMPassRegistryRef R);	void LLVMInitializeCodeGen(LLVMPassRegistryRef R);
	void LLVMInitializeTarget(LLVMPassRegistryRef R);	void LLVMInitializeTarget(LLVMPassRegistryRef R);


		/**
		* @}
		*/

	#ifdef __cplusplus	#ifdef __cplusplus
	}	}
	#endif	#endif

	#endif	#endif

End of changes. 3 change blocks.
	0 lines changed or deleted	14 lines changed or added

	InlineAsm.h	InlineAsm.h

	skipping to change at line 20	skipping to change at line 20
	// This class represents the inline asm strings, which are Value*'s that ar e	// This class represents the inline asm strings, which are Value*'s that ar e
	// used as the callee operand of call instructions. InlineAsm's are unique d	// used as the callee operand of call instructions. InlineAsm's are unique d
	// like constants, and created via InlineAsm::get(...).	// like constants, and created via InlineAsm::get(...).
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_INLINEASM_H	#ifndef LLVM_INLINEASM_H
	#define LLVM_INLINEASM_H	#define LLVM_INLINEASM_H

	#include "llvm/Value.h"	#include "llvm/Value.h"

		#include "llvm/ADT/StringRef.h"
	#include <vector>	#include <vector>

	namespace llvm {	namespace llvm {

	class PointerType;	class PointerType;
	class FunctionType;	class FunctionType;
	class Module;	class Module;
	struct InlineAsmKeyType;	struct InlineAsmKeyType;
	template<class ValType, class ValRefType, class TypeClass, class ConstantCl ass,	template<class ValType, class ValRefType, class TypeClass, class ConstantCl ass,
	bool HasLargeKey>	bool HasLargeKey>

End of changes. 1 change blocks.
	0 lines changed or deleted	1 lines changed or added

	InlineCost.h	InlineCost.h

	skipping to change at line 17	skipping to change at line 17
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	//	//
	// This file implements heuristics for inlining decisions.	// This file implements heuristics for inlining decisions.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_ANALYSIS_INLINECOST_H	#ifndef LLVM_ANALYSIS_INLINECOST_H
	#define LLVM_ANALYSIS_INLINECOST_H	#define LLVM_ANALYSIS_INLINECOST_H


	#include <cassert>	#include "llvm/Function.h"
	#include <climits>
	#include <vector>
	#include "llvm/ADT/DenseMap.h"	#include "llvm/ADT/DenseMap.h"

		#include "llvm/ADT/SmallPtrSet.h"
	#include "llvm/ADT/ValueMap.h"	#include "llvm/ADT/ValueMap.h"
	#include "llvm/Analysis/CodeMetrics.h"	#include "llvm/Analysis/CodeMetrics.h"

		#include <cassert>
		#include <climits>
		#include <vector>

	namespace llvm {	namespace llvm {


	class Value;
	class Function;
	class BasicBlock;
	class CallSite;	class CallSite;

	template<class PtrType, unsigned SmallSize>
	class SmallPtrSet;
	class TargetData;	class TargetData;

	namespace InlineConstants {	namespace InlineConstants {
	// Various magic constants used to adjust heuristics.	// Various magic constants used to adjust heuristics.
	const int InstrCost = 5;	const int InstrCost = 5;

	const int IndirectCallBonus = -100;	const int IndirectCallThreshold = 100;
	const int CallPenalty = 25;	const int CallPenalty = 25;
	const int LastCallToStaticBonus = -15000;	const int LastCallToStaticBonus = -15000;
	const int ColdccPenalty = 2000;	const int ColdccPenalty = 2000;
	const int NoreturnPenalty = 10000;	const int NoreturnPenalty = 10000;
	}	}


	/// InlineCost - Represent the cost of inlining a function. This	/// \brief Represents the cost of inlining a function.
	/// supports special values for functions which should "always" or	///
	/// "never" be inlined. Otherwise, the cost represents a unitless	/// This supports special values for functions which should "always" or
	/// amount; smaller values increase the likelihood of the function	/// "never" be inlined. Otherwise, the cost represents a unitless amount;
	/// being inlined.	/// smaller values increase the likelihood of the function being inlined.
		///
		/// Objects of this type also provide the adjusted threshold for inlining
		/// based on the information available for a particular callsite. They ca
		n be
		/// directly tested to determine if inlining should occur given the cost
		and
		/// threshold for this cost metric.
	class InlineCost {	class InlineCost {

	enum Kind {	enum SentinelValues {
	Value,	AlwaysInlineCost = INT_MIN,
	Always,	NeverInlineCost = INT_MAX
	Never
	};	};


	// This is a do-it-yourself implementation of	/// \brief The estimated cost of inlining this callsite.
	// int Cost : 30;	const int Cost;
	// unsigned Type : 2;
	// We used to use bitfields, but they were sometimes miscompiled (PR382
	2).
	enum { TYPE_BITS = 2 };
	enum { COST_BITS = unsigned(sizeof(unsigned)) * CHAR_BIT - TYPE_BITS };
	unsigned TypedCost; // int Cost : COST_BITS; unsigned Type : TYPE_BITS;


	Kind getType() const {	/// \brief The adjusted threshold against which this cost was computed.
	return Kind(TypedCost >> COST_BITS);	const int Threshold;
	}


	int getCost() const {	// Trivial constructor, interesting logic in the factory functions belo
	// Sign-extend the bottom COST_BITS bits.	w.
	return (int(TypedCost << TYPE_BITS)) >> TYPE_BITS;	InlineCost(int Cost, int Threshold)
	}	: Cost(Cost), Threshold(Threshold) {}


	InlineCost(int C, int T) {
	TypedCost = (unsigned(C << TYPE_BITS) >> TYPE_BITS) \| (T << COST_BITS
	);
	assert(getCost() == C && "Cost exceeds InlineCost precision");
	}
	public:	public:

	static InlineCost get(int Cost) { return InlineCost(Cost, Value); }	static InlineCost get(int Cost, int Threshold) {
	static InlineCost getAlways() { return InlineCost(0, Always); }	assert(Cost > AlwaysInlineCost && "Cost crosses sentinel value");
	static InlineCost getNever() { return InlineCost(0, Never); }	assert(Cost < NeverInlineCost && "Cost crosses sentinel value");
		return InlineCost(Cost, Threshold);
	bool isVariable() const { return getType() == Value; }	}
	bool isAlways() const { return getType() == Always; }	static InlineCost getAlways() {
	bool isNever() const { return getType() == Never; }	return InlineCost(AlwaysInlineCost, 0);
		}
	/// getValue() - Return a "variable" inline cost's amount. It is	static InlineCost getNever() {
	/// an error to call this on an "always" or "never" InlineCost.	return InlineCost(NeverInlineCost, 0);
	int getValue() const {
	assert(getType() == Value && "Invalid access of InlineCost");
	return getCost();
	}	}

	};


	/// InlineCostAnalyzer - Cost analyzer used by inliner.	/// \brief Test whether the inline cost is low enough for inlining.
	class InlineCostAnalyzer {	operator bool() const {
	struct ArgInfo {	return Cost < Threshold;
	public:	}
	unsigned ConstantWeight;
	unsigned AllocaWeight;

	ArgInfo(unsigned CWeight, unsigned AWeight)
	: ConstantWeight(CWeight), AllocaWeight(AWeight)
	{}
	};


	struct FunctionInfo {	bool isAlways() const { return Cost == AlwaysInlineCost; }
	CodeMetrics Metrics;	bool isNever() const { return Cost == NeverInlineCost; }
		bool isVariable() const { return !isAlways() && !isNever(); }


	/// ArgumentWeights - Each formal argument of the function is inspect	/// \brief Get the inline cost estimate.
	ed to	/// It is an error to call this on an "always" or "never" InlineCost.
	/// see if it is used in any contexts where making it a constant or a	int getCost() const {
	lloca	assert(isVariable() && "Invalid access of InlineCost");
	/// would reduce the code size. If so, we add some value to the argu	return Cost;
	ment	}
	/// entry here.
	std::vector<ArgInfo> ArgumentWeights;

	/// analyzeFunction - Add information about the specified function
	/// to the current structure.
	void analyzeFunction(Function F, const TargetData TD);

	/// NeverInline - Returns true if the function should never be
	/// inlined into any caller.
	bool NeverInline();
	};


	// The Function* for a function can be changed (by ArgumentPromotion);	/// \brief Get the cost delta from the threshold for inlining.
	// the ValueMap will update itself when this happens.	/// Only valid if the cost is of the variable kind. Returns a negative
	ValueMap<const Function *, FunctionInfo> CachedFunctionInfo;	/// value if the cost is too high to inline.
		int getCostDelta() const { return Threshold - getCost(); }
		};


		/// InlineCostAnalyzer - Cost analyzer used by inliner.
		class InlineCostAnalyzer {
	// TargetData if available, or null.	// TargetData if available, or null.
	const TargetData *TD;	const TargetData *TD;


	int CountBonusForConstant(Value V, Constant C = NULL);
	int ConstantFunctionBonus(CallSite CS, Constant *C);
	int getInlineSize(CallSite CS, Function *Callee);
	int getInlineBonuses(CallSite CS, Function *Callee);
	public:	public:
	InlineCostAnalyzer(): TD(0) {}	InlineCostAnalyzer(): TD(0) {}

	void setTargetData(const TargetData *TData) { TD = TData; }	void setTargetData(const TargetData *TData) { TD = TData; }


	/// getInlineCost - The heuristic used to determine if we should inline	/// \brief Get an InlineCost object representing the cost of inlining t
	the	his
	/// function call or not.	/// callsite.
	///	///

	InlineCost getInlineCost(CallSite CS,	/// Note that threshold is passed into this function. Only costs below
	SmallPtrSet<const Function *, 16> &NeverInline	the
	);	/// threshold are computed with any accuracy. The threshold can be used
		to
		/// bound the computation necessary to determine whether the cost is
		/// sufficiently low to warrant inlining.
		InlineCost getInlineCost(CallSite CS, int Threshold);
	/// getCalledFunction - The heuristic used to determine if we should in line	/// getCalledFunction - The heuristic used to determine if we should in line
	/// the function call or not. The callee is explicitly specified, to a llow	/// the function call or not. The callee is explicitly specified, to a llow

	/// you to calculate the cost of inlining a function via a pointer. Th	/// you to calculate the cost of inlining a function via a pointer. Th
	e	is
	/// result assumes that the inlined version will always be used. You s	/// behaves exactly as the version with no explicit callee parameter in
	hould	all
	/// weight it yourself in cases where this callee will not always be ca	/// other respects.
	lled.	//
	InlineCost getInlineCost(CallSite CS,	// Note: This is used by out-of-tree passes, please do not remove with
	Function *Callee,	out
	SmallPtrSet<const Function *, 16> &NeverInline	// adding a replacement API.
	);	InlineCost getInlineCost(CallSite CS, Function *Callee, int Threshold);

	/// getSpecializationBonus - The heuristic used to determine the per-ca
	ll
	/// performance boost for using a specialization of Callee with argumen
	t
	/// SpecializedArgNos replaced by a constant.
	int getSpecializationBonus(Function *Callee,
	SmallVectorImpl<unsigned> &SpecializedArgNo);

	/// getSpecializationCost - The heuristic used to determine the code-si
	ze
	/// impact of creating a specialized version of Callee with argument
	/// SpecializedArgNo replaced by a constant.
	InlineCost getSpecializationCost(Function *Callee,
	SmallVectorImpl<unsigned> &SpecializedArgNo);

	/// getInlineFudgeFactor - Return a > 1.0 factor if the inliner should
	use a
	/// higher threshold to determine if the function call should be inline
	d.
	float getInlineFudgeFactor(CallSite CS);

	/// resetCachedFunctionInfo - erase any cached cost info for this funct
	ion.
	void resetCachedCostInfo(Function* Caller) {
	CachedFunctionInfo[Caller] = FunctionInfo();
	}

	/// growCachedCostInfo - update the cached cost info for Caller after C
	allee
	/// has been inlined. If Callee is NULL it means a dead call has been
	/// eliminated.
	void growCachedCostInfo(Function* Caller, Function* Callee);

	/// clear - empty the cache of inline costs
	void clear();
	};	};

	/// callIsSmall - If a call is likely to lower to a single target instruc tion,	/// callIsSmall - If a call is likely to lower to a single target instruc tion,
	/// or is otherwise deemed small return true.	/// or is otherwise deemed small return true.
	bool callIsSmall(const Function *Callee);	bool callIsSmall(const Function *Callee);
	}	}

	#endif	#endif

End of changes. 23 change blocks.
	141 lines changed or deleted	79 lines changed or added

	InlinerPass.h	InlinerPass.h

	skipping to change at line 34	skipping to change at line 34
	class TargetData;	class TargetData;
	class InlineCost;	class InlineCost;
	template<class PtrType, unsigned SmallSize>	template<class PtrType, unsigned SmallSize>
	class SmallPtrSet;	class SmallPtrSet;

	/// Inliner - This class contains all of the helper code which is used to	/// Inliner - This class contains all of the helper code which is used to
	/// perform the inlining operations that do not depend on the policy.	/// perform the inlining operations that do not depend on the policy.
	///	///
	struct Inliner : public CallGraphSCCPass {	struct Inliner : public CallGraphSCCPass {
	explicit Inliner(char &ID);	explicit Inliner(char &ID);

	explicit Inliner(char &ID, int Threshold);	explicit Inliner(char &ID, int Threshold, bool InsertLifetime);

	/// getAnalysisUsage - For this class, we declare that we require and pre serve	/// getAnalysisUsage - For this class, we declare that we require and pre serve
	/// the call graph. If the derived class implements this method, it shou ld	/// the call graph. If the derived class implements this method, it shou ld
	/// always explicitly call the implementation here.	/// always explicitly call the implementation here.
	virtual void getAnalysisUsage(AnalysisUsage &Info) const;	virtual void getAnalysisUsage(AnalysisUsage &Info) const;

	// Main run interface method, this implements the interface required by t he	// Main run interface method, this implements the interface required by t he
	// Pass class.	// Pass class.
	virtual bool runOnSCC(CallGraphSCC &SCC);	virtual bool runOnSCC(CallGraphSCC &SCC);


	skipping to change at line 68	skipping to change at line 68
	///	///
	unsigned getInlineThreshold(CallSite CS) const;	unsigned getInlineThreshold(CallSite CS) const;

	/// getInlineCost - This method must be implemented by the subclass to	/// getInlineCost - This method must be implemented by the subclass to
	/// determine the cost of inlining the specified call site. If the cost	/// determine the cost of inlining the specified call site. If the cost
	/// returned is greater than the current inline threshold, the call site is	/// returned is greater than the current inline threshold, the call site is
	/// not inlined.	/// not inlined.
	///	///
	virtual InlineCost getInlineCost(CallSite CS) = 0;	virtual InlineCost getInlineCost(CallSite CS) = 0;


	// getInlineFudgeFactor - Return a > 1.0 factor if the inliner should use	/// removeDeadFunctions - Remove dead functions.
	a
	// higher threshold to determine if the function call should be inlined.
	///	///

	virtual float getInlineFudgeFactor(CallSite CS) = 0;	/// This also includes a hack in the form of the 'AlwaysInlineOnly' flag
		/// which restricts it to deleting functions with an 'AlwaysInline'
		/// attribute. This is useful for the InlineAlways pass that only wants t
		o
		/// deal with that subset of the functions.
		bool removeDeadFunctions(CallGraph &CG, bool AlwaysInlineOnly = false);


	/// resetCachedCostInfo - erase any cached cost data from the derived cla
	ss.
	/// If the derived class has no such data this can be empty.
	///
	virtual void resetCachedCostInfo(Function* Caller) = 0;

	/// growCachedCostInfo - update the cached cost info for Caller after Cal
	lee
	/// has been inlined.
	virtual void growCachedCostInfo(Function Caller, Function Callee) = 0;

	/// removeDeadFunctions - Remove dead functions that are not included in
	/// DNR (Do Not Remove) list.
	bool removeDeadFunctions(CallGraph &CG,
	SmallPtrSet<const Function , 16> DNR = NULL);
	private:	private:
	// InlineThreshold - Cache the value here for easy access.	// InlineThreshold - Cache the value here for easy access.
	unsigned InlineThreshold;	unsigned InlineThreshold;


		// InsertLifetime - Insert @llvm.lifetime intrinsics.
		bool InsertLifetime;

	/// shouldInline - Return true if the inliner should attempt to	/// shouldInline - Return true if the inliner should attempt to
	/// inline at the given CallSite.	/// inline at the given CallSite.
	bool shouldInline(CallSite CS);	bool shouldInline(CallSite CS);
	};	};

	} // End llvm namespace	} // End llvm namespace

	#endif	#endif

End of changes. 5 change blocks.
	20 lines changed or deleted	11 lines changed or added

	InstVisitor.h	InstVisitor.h

	skipping to change at line 16	skipping to change at line 16
	// License. See LICENSE.TXT for details.	// License. See LICENSE.TXT for details.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_SUPPORT_INSTVISITOR_H	#ifndef LLVM_SUPPORT_INSTVISITOR_H
	#define LLVM_SUPPORT_INSTVISITOR_H	#define LLVM_SUPPORT_INSTVISITOR_H

	#include "llvm/Function.h"	#include "llvm/Function.h"
	#include "llvm/Instructions.h"	#include "llvm/Instructions.h"
	#include "llvm/Module.h"	#include "llvm/Module.h"

		#include "llvm/Support/CallSite.h"
	#include "llvm/Support/ErrorHandling.h"	#include "llvm/Support/ErrorHandling.h"

	namespace llvm {	namespace llvm {

	// We operate on opaque instruction classes, so forward declare all instruc tion	// We operate on opaque instruction classes, so forward declare all instruc tion
	// types now...	// types now...
	//	//
	#define HANDLE_INST(NUM, OPCODE, CLASS) class CLASS;	#define HANDLE_INST(NUM, OPCODE, CLASS) class CLASS;
	#include "llvm/Instruction.def"	#include "llvm/Instruction.def"


	skipping to change at line 158	skipping to change at line 159
	// generic version) without multiply defined symbols and recursion. To h andle	// generic version) without multiply defined symbols and recursion. To h andle
	// this, we do not autoexpand "Other" instructions, we do it manually.	// this, we do not autoexpand "Other" instructions, we do it manually.
	//	//
	#define HANDLE_INST(NUM, OPCODE, CLASS) \	#define HANDLE_INST(NUM, OPCODE, CLASS) \
	RetTy visit##OPCODE(CLASS &I) { DELEGATE(CLASS); }	RetTy visit##OPCODE(CLASS &I) { DELEGATE(CLASS); }
	#include "llvm/Instruction.def"	#include "llvm/Instruction.def"

	// Specific Instruction type classes... note that all of the casts are	// Specific Instruction type classes... note that all of the casts are
	// necessary because we use the instruction classes as opaque types...	// necessary because we use the instruction classes as opaque types...
	//	//

	RetTy visitReturnInst(ReturnInst &I) { DELEGATE(TerminatorIn	RetTy visitReturnInst(ReturnInst &I) { DELEGATE(TerminatorInst
	st);}	);}
	RetTy visitBranchInst(BranchInst &I) { DELEGATE(TerminatorIn	RetTy visitBranchInst(BranchInst &I) { DELEGATE(TerminatorInst
	st);}	);}
	RetTy visitSwitchInst(SwitchInst &I) { DELEGATE(TerminatorIn	RetTy visitSwitchInst(SwitchInst &I) { DELEGATE(TerminatorInst
	st);}	);}
	RetTy visitIndirectBrInst(IndirectBrInst &I) { DELEGATE(TerminatorIn	RetTy visitIndirectBrInst(IndirectBrInst &I) { DELEGATE(TerminatorInst
	st);}	);}
	RetTy visitInvokeInst(InvokeInst &I) { DELEGATE(TerminatorIn	RetTy visitResumeInst(ResumeInst &I) { DELEGATE(TerminatorInst
	st);}	);}
	RetTy visitUnwindInst(UnwindInst &I) { DELEGATE(TerminatorIn	RetTy visitUnreachableInst(UnreachableInst &I) { DELEGATE(TerminatorInst
	st);}	);}
	RetTy visitResumeInst(ResumeInst &I) { DELEGATE(TerminatorIn	RetTy visitICmpInst(ICmpInst &I) { DELEGATE(CmpInst);}
	st);}	RetTy visitFCmpInst(FCmpInst &I) { DELEGATE(CmpInst);}
	RetTy visitUnreachableInst(UnreachableInst &I) { DELEGATE(TerminatorIn	RetTy visitAllocaInst(AllocaInst &I) { DELEGATE(UnaryInstructi
	st);}	on);}
	RetTy visitICmpInst(ICmpInst &I) { DELEGATE(CmpInst);}	RetTy visitLoadInst(LoadInst &I) { DELEGATE(UnaryInstructi
	RetTy visitFCmpInst(FCmpInst &I) { DELEGATE(CmpInst);}	on);}
	RetTy visitAllocaInst(AllocaInst &I) { DELEGATE(Instruction)	RetTy visitStoreInst(StoreInst &I) { DELEGATE(Instruction);}
	; }	RetTy visitAtomicCmpXchgInst(AtomicCmpXchgInst &I) { DELEGATE(Instruction
	RetTy visitLoadInst(LoadInst &I) { DELEGATE(Instruction)	);}
	; }	RetTy visitAtomicRMWInst(AtomicRMWInst &I) { DELEGATE(Instruction);}
	RetTy visitStoreInst(StoreInst &I) { DELEGATE(Instruction)	RetTy visitFenceInst(FenceInst &I) { DELEGATE(Instruction);}
	; }	RetTy visitGetElementPtrInst(GetElementPtrInst &I){ DELEGATE(Instruction)
	RetTy visitAtomicCmpXchgInst(AtomicCmpXchgInst &I){ DELEGATE(Instruction)	;}
	; }	RetTy visitPHINode(PHINode &I) { DELEGATE(Instruction);}
	RetTy visitAtomicRMWInst(AtomicRMWInst &I) { DELEGATE(Instruction)	RetTy visitTruncInst(TruncInst &I) { DELEGATE(CastInst);}
	; }	RetTy visitZExtInst(ZExtInst &I) { DELEGATE(CastInst);}
	RetTy visitFenceInst(FenceInst &I) { DELEGATE(Instruction)	RetTy visitSExtInst(SExtInst &I) { DELEGATE(CastInst);}
	; }	RetTy visitFPTruncInst(FPTruncInst &I) { DELEGATE(CastInst);}
	RetTy visitGetElementPtrInst(GetElementPtrInst &I){ DELEGATE(Instruction)	RetTy visitFPExtInst(FPExtInst &I) { DELEGATE(CastInst);}
	; }	RetTy visitFPToUIInst(FPToUIInst &I) { DELEGATE(CastInst);}
	RetTy visitPHINode(PHINode &I) { DELEGATE(Instruction)	RetTy visitFPToSIInst(FPToSIInst &I) { DELEGATE(CastInst);}
	; }	RetTy visitUIToFPInst(UIToFPInst &I) { DELEGATE(CastInst);}
	RetTy visitTruncInst(TruncInst &I) { DELEGATE(CastInst); }	RetTy visitSIToFPInst(SIToFPInst &I) { DELEGATE(CastInst);}
	RetTy visitZExtInst(ZExtInst &I) { DELEGATE(CastInst); }	RetTy visitPtrToIntInst(PtrToIntInst &I) { DELEGATE(CastInst);}
	RetTy visitSExtInst(SExtInst &I) { DELEGATE(CastInst); }	RetTy visitIntToPtrInst(IntToPtrInst &I) { DELEGATE(CastInst);}
	RetTy visitFPTruncInst(FPTruncInst &I) { DELEGATE(CastInst); }	RetTy visitBitCastInst(BitCastInst &I) { DELEGATE(CastInst);}
	RetTy visitFPExtInst(FPExtInst &I) { DELEGATE(CastInst); }	RetTy visitSelectInst(SelectInst &I) { DELEGATE(Instruction);}
	RetTy visitFPToUIInst(FPToUIInst &I) { DELEGATE(CastInst); }	RetTy visitVAArgInst(VAArgInst &I) { DELEGATE(UnaryInstructi
	RetTy visitFPToSIInst(FPToSIInst &I) { DELEGATE(CastInst); }	on);}
	RetTy visitUIToFPInst(UIToFPInst &I) { DELEGATE(CastInst); }
	RetTy visitSIToFPInst(SIToFPInst &I) { DELEGATE(CastInst); }
	RetTy visitPtrToIntInst(PtrToIntInst &I) { DELEGATE(CastInst); }
	RetTy visitIntToPtrInst(IntToPtrInst &I) { DELEGATE(CastInst); }
	RetTy visitBitCastInst(BitCastInst &I) { DELEGATE(CastInst); }
	RetTy visitSelectInst(SelectInst &I) { DELEGATE(Instruction)
	; }
	RetTy visitCallInst(CallInst &I) { DELEGATE(Instruction)
	; }
	RetTy visitVAArgInst(VAArgInst &I) { DELEGATE(Instruction)
	; }
	RetTy visitExtractElementInst(ExtractElementInst &I) { DELEGATE(Instructi on);}	RetTy visitExtractElementInst(ExtractElementInst &I) { DELEGATE(Instructi on);}

	RetTy visitInsertElementInst(InsertElementInst &I) { DELEGATE(Instruction	RetTy visitInsertElementInst(InsertElementInst &I) { DELEGATE(Instruction
	); }	);}
	RetTy visitShuffleVectorInst(ShuffleVectorInst &I) { DELEGATE(Instruction	RetTy visitShuffleVectorInst(ShuffleVectorInst &I) { DELEGATE(Instruction
	); }	);}
	RetTy visitExtractValueInst(ExtractValueInst &I) { DELEGATE(Instruction)	RetTy visitExtractValueInst(ExtractValueInst &I){ DELEGATE(UnaryInstructi
	;}	on);}
	RetTy visitInsertValueInst(InsertValueInst &I) { DELEGATE(Instruction)	RetTy visitInsertValueInst(InsertValueInst &I) { DELEGATE(Instruction);
	; }	}
	RetTy visitLandingPadInst(LandingPadInst &I) { DELEGATE(Instruction)	RetTy visitLandingPadInst(LandingPadInst &I) { DELEGATE(Instruction);
	; }	}

		// Call and Invoke are slightly different as they delegate first through
		// a generic CallSite visitor.
		RetTy visitCallInst(CallInst &I) {
		return static_cast<SubClass*>(this)->visitCallSite(&I);
		}
		RetTy visitInvokeInst(InvokeInst &I) {
		return static_cast<SubClass*>(this)->visitCallSite(&I);
		}

	// Next level propagators: If the user does not overload a specific	// Next level propagators: If the user does not overload a specific
	// instruction type, they can overload one of these to get the whole clas s	// instruction type, they can overload one of these to get the whole clas s
	// of instructions...	// of instructions...
	//	//

	RetTy visitTerminatorInst(TerminatorInst &I) { DELEGATE(Instruction); }	RetTy visitCastInst(CastInst &I) { DELEGATE(UnaryInstructi
	RetTy visitBinaryOperator(BinaryOperator &I) { DELEGATE(Instruction); }	on);}
	RetTy visitCmpInst(CmpInst &I) { DELEGATE(Instruction); }	RetTy visitBinaryOperator(BinaryOperator &I) { DELEGATE(Instruction);}
	RetTy visitCastInst(CastInst &I) { DELEGATE(Instruction); }	RetTy visitCmpInst(CmpInst &I) { DELEGATE(Instruction);}
		RetTy visitTerminatorInst(TerminatorInst &I) { DELEGATE(Instruction);}
		RetTy visitUnaryInstruction(UnaryInstruction &I){ DELEGATE(Instruction);}

		// Provide a special visitor for a 'callsite' that visits both calls and
		// invokes. When unimplemented, properly delegates to either the terminat
		or or
		// regular instruction visitor.
		RetTy visitCallSite(CallSite CS) {
		assert(CS);
		Instruction &I = *CS.getInstruction();
		if (CS.isCall())
		DELEGATE(Instruction);

		assert(CS.isInvoke());
		DELEGATE(TerminatorInst);
		}

	// If the user wants a 'default' case, they can choose to override this	// If the user wants a 'default' case, they can choose to override this
	// function. If this function is not overloaded in the user's subclass, then	// function. If this function is not overloaded in the user's subclass, then
	// this instruction just gets ignored.	// this instruction just gets ignored.
	//	//
	// Note that you MUST override this function if your return type is not v oid.	// Note that you MUST override this function if your return type is not v oid.
	//	//
	void visitInstruction(Instruction &I) {} // Ignore unhandled instruction s	void visitInstruction(Instruction &I) {} // Ignore unhandled instruction s
	};	};


End of changes. 4 change blocks.
	66 lines changed or deleted	81 lines changed or added

	Instruction.def	Instruction.def

	skipping to change at line 101	skipping to change at line 101
	// Terminator Instructions - These instructions are used to terminate a bas ic	// Terminator Instructions - These instructions are used to terminate a bas ic
	// block of the program. Every basic block must end with one of these	// block of the program. Every basic block must end with one of these
	// instructions for it to be a well formed basic block.	// instructions for it to be a well formed basic block.
	//	//
	FIRST_TERM_INST ( 1)	FIRST_TERM_INST ( 1)
	HANDLE_TERM_INST ( 1, Ret , ReturnInst)	HANDLE_TERM_INST ( 1, Ret , ReturnInst)
	HANDLE_TERM_INST ( 2, Br , BranchInst)	HANDLE_TERM_INST ( 2, Br , BranchInst)
	HANDLE_TERM_INST ( 3, Switch , SwitchInst)	HANDLE_TERM_INST ( 3, Switch , SwitchInst)
	HANDLE_TERM_INST ( 4, IndirectBr , IndirectBrInst)	HANDLE_TERM_INST ( 4, IndirectBr , IndirectBrInst)
	HANDLE_TERM_INST ( 5, Invoke , InvokeInst)	HANDLE_TERM_INST ( 5, Invoke , InvokeInst)

	HANDLE_TERM_INST ( 6, Unwind , UnwindInst)	HANDLE_TERM_INST ( 6, Resume , ResumeInst)
	HANDLE_TERM_INST ( 7, Resume , ResumeInst)	HANDLE_TERM_INST ( 7, Unreachable, UnreachableInst)
	HANDLE_TERM_INST ( 8, Unreachable, UnreachableInst)	LAST_TERM_INST ( 7)
	LAST_TERM_INST ( 8)

	// Standard binary operators...	// Standard binary operators...

	FIRST_BINARY_INST( 9)	FIRST_BINARY_INST( 8)
	HANDLE_BINARY_INST( 9, Add , BinaryOperator)	HANDLE_BINARY_INST( 8, Add , BinaryOperator)
	HANDLE_BINARY_INST(10, FAdd , BinaryOperator)	HANDLE_BINARY_INST( 9, FAdd , BinaryOperator)
	HANDLE_BINARY_INST(11, Sub , BinaryOperator)	HANDLE_BINARY_INST(10, Sub , BinaryOperator)
	HANDLE_BINARY_INST(12, FSub , BinaryOperator)	HANDLE_BINARY_INST(11, FSub , BinaryOperator)
	HANDLE_BINARY_INST(13, Mul , BinaryOperator)	HANDLE_BINARY_INST(12, Mul , BinaryOperator)
	HANDLE_BINARY_INST(14, FMul , BinaryOperator)	HANDLE_BINARY_INST(13, FMul , BinaryOperator)
	HANDLE_BINARY_INST(15, UDiv , BinaryOperator)	HANDLE_BINARY_INST(14, UDiv , BinaryOperator)
	HANDLE_BINARY_INST(16, SDiv , BinaryOperator)	HANDLE_BINARY_INST(15, SDiv , BinaryOperator)
	HANDLE_BINARY_INST(17, FDiv , BinaryOperator)	HANDLE_BINARY_INST(16, FDiv , BinaryOperator)
	HANDLE_BINARY_INST(18, URem , BinaryOperator)	HANDLE_BINARY_INST(17, URem , BinaryOperator)
	HANDLE_BINARY_INST(19, SRem , BinaryOperator)	HANDLE_BINARY_INST(18, SRem , BinaryOperator)
	HANDLE_BINARY_INST(20, FRem , BinaryOperator)	HANDLE_BINARY_INST(19, FRem , BinaryOperator)

	// Logical operators (integer operands)	// Logical operators (integer operands)

	HANDLE_BINARY_INST(21, Shl , BinaryOperator) // Shift left (logical)	HANDLE_BINARY_INST(20, Shl , BinaryOperator) // Shift left (logical)
	HANDLE_BINARY_INST(22, LShr , BinaryOperator) // Shift right (logical)	HANDLE_BINARY_INST(21, LShr , BinaryOperator) // Shift right (logical)
	HANDLE_BINARY_INST(23, AShr , BinaryOperator) // Shift right (arithmetic)	HANDLE_BINARY_INST(22, AShr , BinaryOperator) // Shift right (arithmetic)
	HANDLE_BINARY_INST(24, And , BinaryOperator)	HANDLE_BINARY_INST(23, And , BinaryOperator)
	HANDLE_BINARY_INST(25, Or , BinaryOperator)	HANDLE_BINARY_INST(24, Or , BinaryOperator)
	HANDLE_BINARY_INST(26, Xor , BinaryOperator)	HANDLE_BINARY_INST(25, Xor , BinaryOperator)
	LAST_BINARY_INST(26)	LAST_BINARY_INST(25)

	// Memory operators...	// Memory operators...

	FIRST_MEMORY_INST(27)	FIRST_MEMORY_INST(26)
	HANDLE_MEMORY_INST(27, Alloca, AllocaInst) // Stack management	HANDLE_MEMORY_INST(26, Alloca, AllocaInst) // Stack management
	HANDLE_MEMORY_INST(28, Load , LoadInst ) // Memory manipulation instrs	HANDLE_MEMORY_INST(27, Load , LoadInst ) // Memory manipulation instrs
	HANDLE_MEMORY_INST(29, Store , StoreInst )	HANDLE_MEMORY_INST(28, Store , StoreInst )
	HANDLE_MEMORY_INST(30, GetElementPtr, GetElementPtrInst)	HANDLE_MEMORY_INST(29, GetElementPtr, GetElementPtrInst)
	HANDLE_MEMORY_INST(31, Fence , FenceInst )	HANDLE_MEMORY_INST(30, Fence , FenceInst )
	HANDLE_MEMORY_INST(32, AtomicCmpXchg , AtomicCmpXchgInst )	HANDLE_MEMORY_INST(31, AtomicCmpXchg , AtomicCmpXchgInst )
	HANDLE_MEMORY_INST(33, AtomicRMW , AtomicRMWInst )	HANDLE_MEMORY_INST(32, AtomicRMW , AtomicRMWInst )
	LAST_MEMORY_INST(33)	LAST_MEMORY_INST(32)

	// Cast operators ...	// Cast operators ...
	// NOTE: The order matters here because CastInst::isEliminableCastPair	// NOTE: The order matters here because CastInst::isEliminableCastPair
	// NOTE: (see Instructions.cpp) encodes a table based on this ordering.	// NOTE: (see Instructions.cpp) encodes a table based on this ordering.

	FIRST_CAST_INST(34)	FIRST_CAST_INST(33)
	HANDLE_CAST_INST(34, Trunc , TruncInst ) // Truncate integers	HANDLE_CAST_INST(33, Trunc , TruncInst ) // Truncate integers
	HANDLE_CAST_INST(35, ZExt , ZExtInst ) // Zero extend integers	HANDLE_CAST_INST(34, ZExt , ZExtInst ) // Zero extend integers
	HANDLE_CAST_INST(36, SExt , SExtInst ) // Sign extend integers	HANDLE_CAST_INST(35, SExt , SExtInst ) // Sign extend integers
	HANDLE_CAST_INST(37, FPToUI , FPToUIInst ) // floating point -> UInt	HANDLE_CAST_INST(36, FPToUI , FPToUIInst ) // floating point -> UInt
	HANDLE_CAST_INST(38, FPToSI , FPToSIInst ) // floating point -> SInt	HANDLE_CAST_INST(37, FPToSI , FPToSIInst ) // floating point -> SInt
	HANDLE_CAST_INST(39, UIToFP , UIToFPInst ) // UInt -> floating point	HANDLE_CAST_INST(38, UIToFP , UIToFPInst ) // UInt -> floating point
	HANDLE_CAST_INST(40, SIToFP , SIToFPInst ) // SInt -> floating point	HANDLE_CAST_INST(39, SIToFP , SIToFPInst ) // SInt -> floating point
	HANDLE_CAST_INST(41, FPTrunc , FPTruncInst ) // Truncate floating point	HANDLE_CAST_INST(40, FPTrunc , FPTruncInst ) // Truncate floating point
	HANDLE_CAST_INST(42, FPExt , FPExtInst ) // Extend floating point	HANDLE_CAST_INST(41, FPExt , FPExtInst ) // Extend floating point
	HANDLE_CAST_INST(43, PtrToInt, PtrToIntInst) // Pointer -> Integer	HANDLE_CAST_INST(42, PtrToInt, PtrToIntInst) // Pointer -> Integer
	HANDLE_CAST_INST(44, IntToPtr, IntToPtrInst) // Integer -> Pointer	HANDLE_CAST_INST(43, IntToPtr, IntToPtrInst) // Integer -> Pointer
	HANDLE_CAST_INST(45, BitCast , BitCastInst ) // Type cast	HANDLE_CAST_INST(44, BitCast , BitCastInst ) // Type cast
	LAST_CAST_INST(45)	LAST_CAST_INST(44)

	// Other operators...	// Other operators...

	FIRST_OTHER_INST(46)	FIRST_OTHER_INST(45)
	HANDLE_OTHER_INST(46, ICmp , ICmpInst ) // Integer comparison instruct	HANDLE_OTHER_INST(45, ICmp , ICmpInst ) // Integer comparison instruct
	ion	ion
	HANDLE_OTHER_INST(47, FCmp , FCmpInst ) // Floating point comparison i	HANDLE_OTHER_INST(46, FCmp , FCmpInst ) // Floating point comparison i
	nstr.	nstr.
	HANDLE_OTHER_INST(48, PHI , PHINode ) // PHI node instruction	HANDLE_OTHER_INST(47, PHI , PHINode ) // PHI node instruction
	HANDLE_OTHER_INST(49, Call , CallInst ) // Call a function	HANDLE_OTHER_INST(48, Call , CallInst ) // Call a function
	HANDLE_OTHER_INST(50, Select , SelectInst ) // select instruction	HANDLE_OTHER_INST(49, Select , SelectInst ) // select instruction
	HANDLE_OTHER_INST(51, UserOp1, Instruction) // May be used internally in a	HANDLE_OTHER_INST(50, UserOp1, Instruction) // May be used internally in a
	pass	pass
	HANDLE_OTHER_INST(52, UserOp2, Instruction) // Internal to passes only	HANDLE_OTHER_INST(51, UserOp2, Instruction) // Internal to passes only
	HANDLE_OTHER_INST(53, VAArg , VAArgInst ) // vaarg instruction	HANDLE_OTHER_INST(52, VAArg , VAArgInst ) // vaarg instruction
	HANDLE_OTHER_INST(54, ExtractElement, ExtractElementInst)// extract from ve	HANDLE_OTHER_INST(53, ExtractElement, ExtractElementInst)// extract from ve
	ctor	ctor
	HANDLE_OTHER_INST(55, InsertElement, InsertElementInst) // insert into vec	HANDLE_OTHER_INST(54, InsertElement, InsertElementInst) // insert into vec
	tor	tor
	HANDLE_OTHER_INST(56, ShuffleVector, ShuffleVectorInst) // shuffle two vec	HANDLE_OTHER_INST(55, ShuffleVector, ShuffleVectorInst) // shuffle two vec
	tors.	tors.
	HANDLE_OTHER_INST(57, ExtractValue, ExtractValueInst)// extract from aggreg	HANDLE_OTHER_INST(56, ExtractValue, ExtractValueInst)// extract from aggreg
	ate	ate
	HANDLE_OTHER_INST(58, InsertValue, InsertValueInst) // insert into aggrega	HANDLE_OTHER_INST(57, InsertValue, InsertValueInst) // insert into aggrega
	te	te
	HANDLE_OTHER_INST(59, LandingPad, LandingPadInst) // Landing pad instructi	HANDLE_OTHER_INST(58, LandingPad, LandingPadInst) // Landing pad instructi
	on.	on.
	LAST_OTHER_INST(59)	LAST_OTHER_INST(58)

	#undef FIRST_TERM_INST	#undef FIRST_TERM_INST
	#undef HANDLE_TERM_INST	#undef HANDLE_TERM_INST
	#undef LAST_TERM_INST	#undef LAST_TERM_INST

	#undef FIRST_BINARY_INST	#undef FIRST_BINARY_INST
	#undef HANDLE_BINARY_INST	#undef HANDLE_BINARY_INST
	#undef LAST_BINARY_INST	#undef LAST_BINARY_INST

	#undef FIRST_MEMORY_INST	#undef FIRST_MEMORY_INST

End of changes. 6 change blocks.
	72 lines changed or deleted	71 lines changed or added

	Instruction.h	Instruction.h

	skipping to change at line 146	skipping to change at line 146

	/// getMetadata - Get the metadata of given kind attached to this Instruc tion.	/// getMetadata - Get the metadata of given kind attached to this Instruc tion.
	/// If the metadata is not found then return null.	/// If the metadata is not found then return null.
	MDNode *getMetadata(unsigned KindID) const {	MDNode *getMetadata(unsigned KindID) const {
	if (!hasMetadata()) return 0;	if (!hasMetadata()) return 0;
	return getMetadataImpl(KindID);	return getMetadataImpl(KindID);
	}	}

	/// getMetadata - Get the metadata of given kind attached to this Instruc tion.	/// getMetadata - Get the metadata of given kind attached to this Instruc tion.
	/// If the metadata is not found then return null.	/// If the metadata is not found then return null.

	MDNode getMetadata(const char Kind) const {	MDNode *getMetadata(StringRef Kind) const {
	if (!hasMetadata()) return 0;	if (!hasMetadata()) return 0;
	return getMetadataImpl(Kind);	return getMetadataImpl(Kind);
	}	}

	/// getAllMetadata - Get all metadata attached to this Instruction. The first	/// getAllMetadata - Get all metadata attached to this Instruction. The first
	/// element of each pair returned is the KindID, the second element is th e	/// element of each pair returned is the KindID, the second element is th e
	/// metadata value. This list is returned sorted by the KindID.	/// metadata value. This list is returned sorted by the KindID.
	void getAllMetadata(SmallVectorImpl<std::pair<unsigned, MDNode*> > &MDs)c onst{	void getAllMetadata(SmallVectorImpl<std::pair<unsigned, MDNode*> > &MDs)c onst{
	if (hasMetadata())	if (hasMetadata())
	getAllMetadataImpl(MDs);	getAllMetadataImpl(MDs);

	skipping to change at line 171	skipping to change at line 171
	void getAllMetadataOtherThanDebugLoc(SmallVectorImpl<std::pair<unsigned,	void getAllMetadataOtherThanDebugLoc(SmallVectorImpl<std::pair<unsigned,
	MDNode*> > &MDs) const {	MDNode*> > &MDs) const {
	if (hasMetadataOtherThanDebugLoc())	if (hasMetadataOtherThanDebugLoc())
	getAllMetadataOtherThanDebugLocImpl(MDs);	getAllMetadataOtherThanDebugLocImpl(MDs);
	}	}

	/// setMetadata - Set the metadata of the specified kind to the specified	/// setMetadata - Set the metadata of the specified kind to the specified
	/// node. This updates/replaces metadata if already present, or removes it if	/// node. This updates/replaces metadata if already present, or removes it if
	/// Node is null.	/// Node is null.
	void setMetadata(unsigned KindID, MDNode *Node);	void setMetadata(unsigned KindID, MDNode *Node);

	void setMetadata(const char Kind, MDNode Node);	void setMetadata(StringRef Kind, MDNode *Node);

	/// setDebugLoc - Set the debug location information for this instruction .	/// setDebugLoc - Set the debug location information for this instruction .
	void setDebugLoc(const DebugLoc &Loc) { DbgLoc = Loc; }	void setDebugLoc(const DebugLoc &Loc) { DbgLoc = Loc; }

	/// getDebugLoc - Return the debug location for this node as a DebugLoc.	/// getDebugLoc - Return the debug location for this node as a DebugLoc.
	const DebugLoc &getDebugLoc() const { return DbgLoc; }	const DebugLoc &getDebugLoc() const { return DbgLoc; }

	private:	private:
	/// hasMetadataHashEntry - Return true if we have an entry in the on-the- side	/// hasMetadataHashEntry - Return true if we have an entry in the on-the- side
	/// metadata hash.	/// metadata hash.
	bool hasMetadataHashEntry() const {	bool hasMetadataHashEntry() const {
	return (getSubclassDataFromValue() & HasMetadataBit) != 0;	return (getSubclassDataFromValue() & HasMetadataBit) != 0;
	}	}

	// These are all implemented in Metadata.cpp.	// These are all implemented in Metadata.cpp.
	MDNode *getMetadataImpl(unsigned KindID) const;	MDNode *getMetadataImpl(unsigned KindID) const;

	MDNode getMetadataImpl(const char Kind) const;	MDNode *getMetadataImpl(StringRef Kind) const;
	void getAllMetadataImpl(SmallVectorImpl<std::pair<unsigned,MDNode*> > &)c onst;	void getAllMetadataImpl(SmallVectorImpl<std::pair<unsigned,MDNode*> > &)c onst;
	void getAllMetadataOtherThanDebugLocImpl(SmallVectorImpl<std::pair<unsign ed,	void getAllMetadataOtherThanDebugLocImpl(SmallVectorImpl<std::pair<unsign ed,
	MDNode*> > &) const;	MDNode*> > &) const;
	void clearMetadataHashEntries();	void clearMetadataHashEntries();
	public:	public:
	//===-------------------------------------------------------------------- ===//	//===-------------------------------------------------------------------- ===//
	// Predicates and helper methods.	// Predicates and helper methods.
	//===-------------------------------------------------------------------- ===//	//===-------------------------------------------------------------------- ===//

	/// isAssociative - Return true if the instruction is associative:	/// isAssociative - Return true if the instruction is associative:

	skipping to change at line 246	skipping to change at line 246
	/// mayHaveSideEffects - Return true if the instruction may have side eff ects.	/// mayHaveSideEffects - Return true if the instruction may have side eff ects.
	///	///
	/// Note that this does not consider malloc and alloca to have side	/// Note that this does not consider malloc and alloca to have side
	/// effects because the newly allocated memory is completely invisible to	/// effects because the newly allocated memory is completely invisible to
	/// instructions which don't used the returned value. For cases where th is	/// instructions which don't used the returned value. For cases where th is
	/// matters, isSafeToSpeculativelyExecute may be more appropriate.	/// matters, isSafeToSpeculativelyExecute may be more appropriate.
	bool mayHaveSideEffects() const {	bool mayHaveSideEffects() const {
	return mayWriteToMemory() \|\| mayThrow();	return mayWriteToMemory() \|\| mayThrow();
	}	}


	/// isSafeToSpeculativelyExecute - Return true if the instruction does no
	t
	/// have any effects besides calculating the result and does not have
	/// undefined behavior.
	///
	/// This method never returns true for an instruction that returns true f
	or
	/// mayHaveSideEffects; however, this method also does some other checks
	in
	/// addition. It checks for undefined behavior, like dividing by zero or
	/// loading from an invalid pointer (but not for undefined results, like
	a
	/// shift with a shift amount larger than the width of the result). It ch
	ecks
	/// for malloc and alloca because speculatively executing them might caus
	e a
	/// memory leak. It also returns false for instructions related to contro
	l
	/// flow, specifically terminators and PHI nodes.
	///
	/// This method only looks at the instruction itself and its operands, so
	if
	/// this method returns true, it is safe to move the instruction as long
	as
	/// the correct dominance relationships for the operands and users hold.
	/// However, this method can return true for instructions that read memor
	y;
	/// for such instructions, moving them may change the resulting value.
	bool isSafeToSpeculativelyExecute() const;

	/// clone() - Create a copy of 'this' instruction that is identical in al l	/// clone() - Create a copy of 'this' instruction that is identical in al l
	/// ways except the following:	/// ways except the following:
	/// * The instruction has no parent	/// * The instruction has no parent
	/// * The instruction has no name	/// * The instruction has no name
	///	///
	Instruction *clone() const;	Instruction *clone() const;

	/// isIdenticalTo - Return true if the specified instruction is exactly	/// isIdenticalTo - Return true if the specified instruction is exactly
	/// identical to the current one. This means that all operands match and any	/// identical to the current one. This means that all operands match and any
	/// extra information (e.g. load is volatile) agree.	/// extra information (e.g. load is volatile) agree.

End of changes. 4 change blocks.
	33 lines changed or deleted	3 lines changed or added

	InstructionSimplify.h	InstructionSimplify.h

	skipping to change at line 23	skipping to change at line 23
	// returning a constant ("and i32 %x, 0" -> "0") or an already existing val ue	// returning a constant ("and i32 %x, 0" -> "0") or an already existing val ue
	// ("and i32 %x, %x" -> "%x"). If the simplification is also an instructio n	// ("and i32 %x, %x" -> "%x"). If the simplification is also an instructio n
	// then it dominates the original instruction.	// then it dominates the original instruction.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_ANALYSIS_INSTRUCTIONSIMPLIFY_H	#ifndef LLVM_ANALYSIS_INSTRUCTIONSIMPLIFY_H
	#define LLVM_ANALYSIS_INSTRUCTIONSIMPLIFY_H	#define LLVM_ANALYSIS_INSTRUCTIONSIMPLIFY_H

	namespace llvm {	namespace llvm {

		template<typename T>
		class ArrayRef;
	class DominatorTree;	class DominatorTree;
	class Instruction;	class Instruction;

	class Value;
	class TargetData;	class TargetData;

	template<typename T>	class TargetLibraryInfo;
	class ArrayRef;	class Type;
		class Value;

	/// SimplifyAddInst - Given operands for an Add, see if we can	/// SimplifyAddInst - Given operands for an Add, see if we can
	/// fold the result. If not, this returns null.	/// fold the result. If not, this returns null.
	Value SimplifyAddInst(Value LHS, Value *RHS, bool isNSW, bool isNUW,	Value SimplifyAddInst(Value LHS, Value *RHS, bool isNSW, bool isNUW,

	const TargetData TD = 0, const DominatorTree DT	const TargetData *TD = 0,
	= 0);	const TargetLibraryInfo *TLI = 0,
		const DominatorTree *DT = 0);

	/// SimplifySubInst - Given operands for a Sub, see if we can	/// SimplifySubInst - Given operands for a Sub, see if we can
	/// fold the result. If not, this returns null.	/// fold the result. If not, this returns null.
	Value SimplifySubInst(Value LHS, Value *RHS, bool isNSW, bool isNUW,	Value SimplifySubInst(Value LHS, Value *RHS, bool isNSW, bool isNUW,

	const TargetData TD = 0, const DominatorTree DT	const TargetData *TD = 0,
	= 0);	const TargetLibraryInfo *TLI = 0,
		const DominatorTree *DT = 0);

	/// SimplifyMulInst - Given operands for a Mul, see if we can	/// SimplifyMulInst - Given operands for a Mul, see if we can
	/// fold the result. If not, this returns null.	/// fold the result. If not, this returns null.
	Value SimplifyMulInst(Value LHS, Value RHS, const TargetData TD = 0,	Value SimplifyMulInst(Value LHS, Value RHS, const TargetData TD = 0,

		const TargetLibraryInfo *TLI = 0,
	const DominatorTree *DT = 0);	const DominatorTree *DT = 0);

	/// SimplifySDivInst - Given operands for an SDiv, see if we can	/// SimplifySDivInst - Given operands for an SDiv, see if we can
	/// fold the result. If not, this returns null.	/// fold the result. If not, this returns null.
	Value SimplifySDivInst(Value LHS, Value RHS, const TargetData TD = 0,	Value SimplifySDivInst(Value LHS, Value RHS, const TargetData TD = 0,

		const TargetLibraryInfo *TLI = 0,
	const DominatorTree *DT = 0);	const DominatorTree *DT = 0);

	/// SimplifyUDivInst - Given operands for a UDiv, see if we can	/// SimplifyUDivInst - Given operands for a UDiv, see if we can
	/// fold the result. If not, this returns null.	/// fold the result. If not, this returns null.
	Value SimplifyUDivInst(Value LHS, Value RHS, const TargetData TD = 0,	Value SimplifyUDivInst(Value LHS, Value RHS, const TargetData TD = 0,

		const TargetLibraryInfo *TLI = 0,
	const DominatorTree *DT = 0);	const DominatorTree *DT = 0);

	/// SimplifyFDivInst - Given operands for an FDiv, see if we can	/// SimplifyFDivInst - Given operands for an FDiv, see if we can
	/// fold the result. If not, this returns null.	/// fold the result. If not, this returns null.
	Value SimplifyFDivInst(Value LHS, Value RHS, const TargetData TD = 0,	Value SimplifyFDivInst(Value LHS, Value RHS, const TargetData TD = 0,

		const TargetLibraryInfo *TLI = 0,
	const DominatorTree *DT = 0);	const DominatorTree *DT = 0);

	/// SimplifySRemInst - Given operands for an SRem, see if we can	/// SimplifySRemInst - Given operands for an SRem, see if we can
	/// fold the result. If not, this returns null.	/// fold the result. If not, this returns null.
	Value SimplifySRemInst(Value LHS, Value RHS, const TargetData TD = 0,	Value SimplifySRemInst(Value LHS, Value RHS, const TargetData TD = 0,

		const TargetLibraryInfo *TLI = 0,
	const DominatorTree *DT = 0);	const DominatorTree *DT = 0);

	/// SimplifyURemInst - Given operands for a URem, see if we can	/// SimplifyURemInst - Given operands for a URem, see if we can
	/// fold the result. If not, this returns null.	/// fold the result. If not, this returns null.
	Value SimplifyURemInst(Value LHS, Value RHS, const TargetData TD = 0,	Value SimplifyURemInst(Value LHS, Value RHS, const TargetData TD = 0,

		const TargetLibraryInfo *TLI = 0,
	const DominatorTree *DT = 0);	const DominatorTree *DT = 0);

	/// SimplifyFRemInst - Given operands for an FRem, see if we can	/// SimplifyFRemInst - Given operands for an FRem, see if we can
	/// fold the result. If not, this returns null.	/// fold the result. If not, this returns null.
	Value SimplifyFRemInst(Value LHS, Value RHS, const TargetData TD = 0,	Value SimplifyFRemInst(Value LHS, Value RHS, const TargetData TD = 0,

		const TargetLibraryInfo *TLI = 0,
	const DominatorTree *DT = 0);	const DominatorTree *DT = 0);

	/// SimplifyShlInst - Given operands for a Shl, see if we can	/// SimplifyShlInst - Given operands for a Shl, see if we can
	/// fold the result. If not, this returns null.	/// fold the result. If not, this returns null.
	Value SimplifyShlInst(Value Op0, Value *Op1, bool isNSW, bool isNUW,	Value SimplifyShlInst(Value Op0, Value *Op1, bool isNSW, bool isNUW,

	const TargetData TD = 0, const DominatorTree DT	const TargetData *TD = 0,
	= 0);	const TargetLibraryInfo *TLI = 0,
		const DominatorTree *DT = 0);

	/// SimplifyLShrInst - Given operands for a LShr, see if we can	/// SimplifyLShrInst - Given operands for a LShr, see if we can
	/// fold the result. If not, this returns null.	/// fold the result. If not, this returns null.
	Value SimplifyLShrInst(Value Op0, Value *Op1, bool isExact,	Value SimplifyLShrInst(Value Op0, Value *Op1, bool isExact,

	const TargetData TD = 0, const DominatorTree DT	const TargetData *TD = 0,
	=0);	const TargetLibraryInfo *TLI = 0,
		const DominatorTree *DT = 0);

	/// SimplifyAShrInst - Given operands for a AShr, see if we can	/// SimplifyAShrInst - Given operands for a AShr, see if we can
	/// fold the result. If not, this returns null.	/// fold the result. If not, this returns null.
	Value SimplifyAShrInst(Value Op0, Value *Op1, bool isExact,	Value SimplifyAShrInst(Value Op0, Value *Op1, bool isExact,
	const TargetData *TD = 0,	const TargetData *TD = 0,

		const TargetLibraryInfo *TLI = 0,
	const DominatorTree *DT = 0);	const DominatorTree *DT = 0);

	/// SimplifyAndInst - Given operands for an And, see if we can	/// SimplifyAndInst - Given operands for an And, see if we can
	/// fold the result. If not, this returns null.	/// fold the result. If not, this returns null.
	Value SimplifyAndInst(Value LHS, Value RHS, const TargetData TD = 0,	Value SimplifyAndInst(Value LHS, Value RHS, const TargetData TD = 0,

		const TargetLibraryInfo *TLI = 0,
	const DominatorTree *DT = 0);	const DominatorTree *DT = 0);

	/// SimplifyOrInst - Given operands for an Or, see if we can	/// SimplifyOrInst - Given operands for an Or, see if we can
	/// fold the result. If not, this returns null.	/// fold the result. If not, this returns null.
	Value SimplifyOrInst(Value LHS, Value RHS, const TargetData TD = 0,	Value SimplifyOrInst(Value LHS, Value RHS, const TargetData TD = 0,

		const TargetLibraryInfo *TLI = 0,
	const DominatorTree *DT = 0);	const DominatorTree *DT = 0);

	/// SimplifyXorInst - Given operands for a Xor, see if we can	/// SimplifyXorInst - Given operands for a Xor, see if we can
	/// fold the result. If not, this returns null.	/// fold the result. If not, this returns null.
	Value SimplifyXorInst(Value LHS, Value RHS, const TargetData TD = 0,	Value SimplifyXorInst(Value LHS, Value RHS, const TargetData TD = 0,

		const TargetLibraryInfo *TLI = 0,
	const DominatorTree *DT = 0);	const DominatorTree *DT = 0);

	/// SimplifyICmpInst - Given operands for an ICmpInst, see if we can	/// SimplifyICmpInst - Given operands for an ICmpInst, see if we can
	/// fold the result. If not, this returns null.	/// fold the result. If not, this returns null.
	Value SimplifyICmpInst(unsigned Predicate, Value LHS, Value *RHS,	Value SimplifyICmpInst(unsigned Predicate, Value LHS, Value *RHS,
	const TargetData *TD = 0,	const TargetData *TD = 0,

		const TargetLibraryInfo *TLI = 0,
	const DominatorTree *DT = 0);	const DominatorTree *DT = 0);

	/// SimplifyFCmpInst - Given operands for an FCmpInst, see if we can	/// SimplifyFCmpInst - Given operands for an FCmpInst, see if we can
	/// fold the result. If not, this returns null.	/// fold the result. If not, this returns null.
	Value SimplifyFCmpInst(unsigned Predicate, Value LHS, Value *RHS,	Value SimplifyFCmpInst(unsigned Predicate, Value LHS, Value *RHS,
	const TargetData *TD = 0,	const TargetData *TD = 0,

		const TargetLibraryInfo *TLI = 0,
	const DominatorTree *DT = 0);	const DominatorTree *DT = 0);

	/// SimplifySelectInst - Given operands for a SelectInst, see if we can f old	/// SimplifySelectInst - Given operands for a SelectInst, see if we can f old
	/// the result. If not, this returns null.	/// the result. If not, this returns null.
	Value SimplifySelectInst(Value Cond, Value TrueVal, Value FalseVal,	Value SimplifySelectInst(Value Cond, Value TrueVal, Value FalseVal,
	const TargetData *TD = 0,	const TargetData *TD = 0,

		const TargetLibraryInfo *TLI = 0,
	const DominatorTree *DT = 0);	const DominatorTree *DT = 0);

	/// SimplifyGEPInst - Given operands for an GetElementPtrInst, see if we can	/// SimplifyGEPInst - Given operands for an GetElementPtrInst, see if we can
	/// fold the result. If not, this returns null.	/// fold the result. If not, this returns null.

	Value SimplifyGEPInst(ArrayRef<Value > Ops,	Value SimplifyGEPInst(ArrayRef<Value > Ops, const TargetData *TD = 0,
	const TargetData TD = 0, const DominatorTree DT	const TargetLibraryInfo *TLI = 0,
	= 0);	const DominatorTree *DT = 0);

	/// SimplifyInsertValueInst - Given operands for an InsertValueInst, see if we	/// SimplifyInsertValueInst - Given operands for an InsertValueInst, see if we
	/// can fold the result. If not, this returns null.	/// can fold the result. If not, this returns null.
	Value SimplifyInsertValueInst(Value Agg, Value *Val,	Value SimplifyInsertValueInst(Value Agg, Value *Val,
	ArrayRef<unsigned> Idxs,	ArrayRef<unsigned> Idxs,
	const TargetData *TD = 0,	const TargetData *TD = 0,

		const TargetLibraryInfo *TLI = 0,
	const DominatorTree *DT = 0);	const DominatorTree *DT = 0);


		/// SimplifyTruncInst - Given operands for an TruncInst, see if we can fo
		ld
		/// the result. If not, this returns null.
		Value SimplifyTruncInst(Value Op, Type Ty, const TargetData TD = 0,
		const TargetLibraryInfo *TLI = 0,
		const DominatorTree *DT = 0);

	//=== Helper functions for higher up the class hierarchy.	//=== Helper functions for higher up the class hierarchy.

	/// SimplifyCmpInst - Given operands for a CmpInst, see if we can	/// SimplifyCmpInst - Given operands for a CmpInst, see if we can
	/// fold the result. If not, this returns null.	/// fold the result. If not, this returns null.
	Value SimplifyCmpInst(unsigned Predicate, Value LHS, Value *RHS,	Value SimplifyCmpInst(unsigned Predicate, Value LHS, Value *RHS,

	const TargetData TD = 0, const DominatorTree DT	const TargetData *TD = 0,
	= 0);	const TargetLibraryInfo *TLI = 0,
		const DominatorTree *DT = 0);

	/// SimplifyBinOp - Given operands for a BinaryOperator, see if we can	/// SimplifyBinOp - Given operands for a BinaryOperator, see if we can
	/// fold the result. If not, this returns null.	/// fold the result. If not, this returns null.
	Value SimplifyBinOp(unsigned Opcode, Value LHS, Value *RHS,	Value SimplifyBinOp(unsigned Opcode, Value LHS, Value *RHS,

	const TargetData TD = 0, const DominatorTree DT =	const TargetData *TD = 0,
	0);	const TargetLibraryInfo *TLI = 0,
		const DominatorTree *DT = 0);

	/// SimplifyInstruction - See if we can compute a simplified version of t his	/// SimplifyInstruction - See if we can compute a simplified version of t his
	/// instruction. If not, this returns null.	/// instruction. If not, this returns null.
	Value SimplifyInstruction(Instruction I, const TargetData *TD = 0,	Value SimplifyInstruction(Instruction I, const TargetData *TD = 0,

		const TargetLibraryInfo *TLI = 0,
	const DominatorTree *DT = 0);	const DominatorTree *DT = 0);


	/// ReplaceAndSimplifyAllUses - Perform From->replaceAllUsesWith(To) and	/// \brief Replace all uses of 'I' with 'SimpleV' and simplify the uses
	then	/// recursively.
	/// delete the From instruction. In addition to a basic RAUW, this does
	a
	/// recursive simplification of the updated instructions. This catches
	/// things where one simplification exposes other opportunities. This on
	ly
	/// simplifies and deletes scalar operations, it does not change the CFG.
	///	///

	void ReplaceAndSimplifyAllUses(Instruction From, Value To,	/// This first performs a normal RAUW of I with SimpleV. It then recursiv
	const TargetData *TD = 0,	ely
	const DominatorTree *DT = 0);	/// attempts to simplify those users updated by the operation. The 'I'
		/// instruction must not be equal to the simplified value 'SimpleV'.
		///
		/// The function returns true if any simplifications were performed.
		bool replaceAndRecursivelySimplify(Instruction I, Value SimpleV,
		const TargetData *TD = 0,
		const TargetLibraryInfo *TLI = 0,
		const DominatorTree *DT = 0);

		/// \brief Recursively attempt to simplify an instruction.
		///
		/// This routine uses SimplifyInstruction to simplify 'I', and if success
		ful
		/// replaces uses of 'I' with the simplified value. It then recurses on e
		ach
		/// of the users impacted. It returns true if any simplifications were
		/// performed.
		bool recursivelySimplifyInstruction(Instruction *I,
		const TargetData *TD = 0,
		const TargetLibraryInfo *TLI = 0,
		const DominatorTree *DT = 0);
	} // end namespace llvm	} // end namespace llvm

	#endif	#endif

End of changes. 29 change blocks.
	29 lines changed or deleted	74 lines changed or added

	Instructions.h	Instructions.h

	skipping to change at line 775	skipping to change at line 775
	/// getIndexedType - Returns the type of the element that would be loaded with	/// getIndexedType - Returns the type of the element that would be loaded with
	/// a load instruction with the specified parameters.	/// a load instruction with the specified parameters.
	///	///
	/// Null is returned if the indices are invalid for the specified	/// Null is returned if the indices are invalid for the specified
	/// pointer type.	/// pointer type.
	///	///
	static Type getIndexedType(Type Ptr, ArrayRef<Value *> IdxList);	static Type getIndexedType(Type Ptr, ArrayRef<Value *> IdxList);
	static Type getIndexedType(Type Ptr, ArrayRef<Constant *> IdxList);	static Type getIndexedType(Type Ptr, ArrayRef<Constant *> IdxList);
	static Type getIndexedType(Type Ptr, ArrayRef<uint64_t> IdxList);	static Type getIndexedType(Type Ptr, ArrayRef<uint64_t> IdxList);


		/// getIndexedType - Returns the address space used by the GEP pointer.
		///
		static unsigned getAddressSpace(Value *Ptr);

	inline op_iterator idx_begin() { return op_begin()+1; }	inline op_iterator idx_begin() { return op_begin()+1; }
	inline const_op_iterator idx_begin() const { return op_begin()+1; }	inline const_op_iterator idx_begin() const { return op_begin()+1; }
	inline op_iterator idx_end() { return op_end(); }	inline op_iterator idx_end() { return op_end(); }
	inline const_op_iterator idx_end() const { return op_end(); }	inline const_op_iterator idx_end() const { return op_end(); }

	Value *getPointerOperand() {	Value *getPointerOperand() {
	return getOperand(0);	return getOperand(0);
	}	}
	const Value *getPointerOperand() const {	const Value *getPointerOperand() const {
	return getOperand(0);	return getOperand(0);
	}	}
	static unsigned getPointerOperandIndex() {	static unsigned getPointerOperandIndex() {

	return 0U; // get index for modifying correct oper and	return 0U; // get index for modifying correct operand.
	}	}

	unsigned getPointerAddressSpace() const {	unsigned getPointerAddressSpace() const {
	return cast<PointerType>(getType())->getAddressSpace();	return cast<PointerType>(getType())->getAddressSpace();
	}	}

	/// getPointerOperandType - Method to return the pointer operand as a	/// getPointerOperandType - Method to return the pointer operand as a
	/// PointerType.	/// PointerType.

	PointerType *getPointerOperandType() const {	Type *getPointerOperandType() const {
	return reinterpret_cast<PointerType*>(getPointerOperand()->getType());	return getPointerOperand()->getType();
		}

		/// GetGEPReturnType - Returns the pointer type returned by the GEP
		/// instruction, which may be a vector of pointers.
		static Type getGEPReturnType(Value Ptr, ArrayRef<Value *> IdxList) {
		Type *PtrTy = PointerType::get(checkGEPType(
		getIndexedType(Ptr->getType(), IdxList))
		,
		getAddressSpace(Ptr));
		// Vector GEP
		if (Ptr->getType()->isVectorTy()) {
		unsigned NumElem = cast<VectorType>(Ptr->getType())->getNumElements()
		;
		return VectorType::get(PtrTy, NumElem);
		}

		// Scalar GEP
		return PtrTy;
	}	}

	unsigned getNumIndices() const { // Note: always non-negative	unsigned getNumIndices() const { // Note: always non-negative
	return getNumOperands() - 1;	return getNumOperands() - 1;
	}	}

	bool hasIndices() const {	bool hasIndices() const {
	return getNumOperands() > 1;	return getNumOperands() > 1;
	}	}


	skipping to change at line 845	skipping to change at line 865
	template <>	template <>
	struct OperandTraits<GetElementPtrInst> :	struct OperandTraits<GetElementPtrInst> :
	public VariadicOperandTraits<GetElementPtrInst, 1> {	public VariadicOperandTraits<GetElementPtrInst, 1> {
	};	};

	GetElementPtrInst::GetElementPtrInst(Value *Ptr,	GetElementPtrInst::GetElementPtrInst(Value *Ptr,
	ArrayRef<Value *> IdxList,	ArrayRef<Value *> IdxList,
	unsigned Values,	unsigned Values,
	const Twine &NameStr,	const Twine &NameStr,
	Instruction *InsertBefore)	Instruction *InsertBefore)

	: Instruction(PointerType::get(checkGEPType(	: Instruction(getGEPReturnType(Ptr, IdxList),
	getIndexedType(Ptr->getType(), IdxList))
	,
	cast<PointerType>(Ptr->getType())
	->getAddressSpace()),
	GetElementPtr,	GetElementPtr,
	OperandTraits<GetElementPtrInst>::op_end(this) - Values,	OperandTraits<GetElementPtrInst>::op_end(this) - Values,
	Values, InsertBefore) {	Values, InsertBefore) {
	init(Ptr, IdxList, NameStr);	init(Ptr, IdxList, NameStr);
	}	}
	GetElementPtrInst::GetElementPtrInst(Value *Ptr,	GetElementPtrInst::GetElementPtrInst(Value *Ptr,
	ArrayRef<Value *> IdxList,	ArrayRef<Value *> IdxList,
	unsigned Values,	unsigned Values,
	const Twine &NameStr,	const Twine &NameStr,
	BasicBlock *InsertAtEnd)	BasicBlock *InsertAtEnd)

	: Instruction(PointerType::get(checkGEPType(	: Instruction(getGEPReturnType(Ptr, IdxList),
	getIndexedType(Ptr->getType(), IdxList))
	,
	cast<PointerType>(Ptr->getType())
	->getAddressSpace()),
	GetElementPtr,	GetElementPtr,
	OperandTraits<GetElementPtrInst>::op_end(this) - Values,	OperandTraits<GetElementPtrInst>::op_end(this) - Values,
	Values, InsertAtEnd) {	Values, InsertAtEnd) {
	init(Ptr, IdxList, NameStr);	init(Ptr, IdxList, NameStr);
	}	}

	DEFINE_TRANSPARENT_OPERAND_ACCESSORS(GetElementPtrInst, Value)	DEFINE_TRANSPARENT_OPERAND_ACCESSORS(GetElementPtrInst, Value)

	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	// ICmpInst Class	// ICmpInst Class

	skipping to change at line 901	skipping to change at line 915
	) : CmpInst(makeCmpResultType(LHS->getType()),	) : CmpInst(makeCmpResultType(LHS->getType()),
	Instruction::ICmp, pred, LHS, RHS, NameStr,	Instruction::ICmp, pred, LHS, RHS, NameStr,
	InsertBefore) {	InsertBefore) {
	assert(pred >= CmpInst::FIRST_ICMP_PREDICATE &&	assert(pred >= CmpInst::FIRST_ICMP_PREDICATE &&
	pred <= CmpInst::LAST_ICMP_PREDICATE &&	pred <= CmpInst::LAST_ICMP_PREDICATE &&
	"Invalid ICmp predicate value");	"Invalid ICmp predicate value");
	assert(getOperand(0)->getType() == getOperand(1)->getType() &&	assert(getOperand(0)->getType() == getOperand(1)->getType() &&
	"Both operands to ICmp instruction are not of the same type!");	"Both operands to ICmp instruction are not of the same type!");
	// Check that the operands are the right type	// Check that the operands are the right type
	assert((getOperand(0)->getType()->isIntOrIntVectorTy() \|\|	assert((getOperand(0)->getType()->isIntOrIntVectorTy() \|\|

	getOperand(0)->getType()->isPointerTy()) &&	getOperand(0)->getType()->getScalarType()->isPointerTy()) &&
	"Invalid operand types for ICmp instruction");	"Invalid operand types for ICmp instruction");
	}	}

	/// @brief Constructor with insert-at-end semantics.	/// @brief Constructor with insert-at-end semantics.
	ICmpInst(	ICmpInst(
	BasicBlock &InsertAtEnd, ///< Block to insert into.	BasicBlock &InsertAtEnd, ///< Block to insert into.
	Predicate pred, ///< The predicate to use for the comparison	Predicate pred, ///< The predicate to use for the comparison
	Value *LHS, ///< The left-hand-side of the expression	Value *LHS, ///< The left-hand-side of the expression
	Value *RHS, ///< The right-hand-side of the expression	Value *RHS, ///< The right-hand-side of the expression
	const Twine &NameStr = "" ///< Name of the instruction	const Twine &NameStr = "" ///< Name of the instruction

	skipping to change at line 941	skipping to change at line 955
	const Twine &NameStr = "" ///< Name of the instruction	const Twine &NameStr = "" ///< Name of the instruction
	) : CmpInst(makeCmpResultType(LHS->getType()),	) : CmpInst(makeCmpResultType(LHS->getType()),
	Instruction::ICmp, pred, LHS, RHS, NameStr) {	Instruction::ICmp, pred, LHS, RHS, NameStr) {
	assert(pred >= CmpInst::FIRST_ICMP_PREDICATE &&	assert(pred >= CmpInst::FIRST_ICMP_PREDICATE &&
	pred <= CmpInst::LAST_ICMP_PREDICATE &&	pred <= CmpInst::LAST_ICMP_PREDICATE &&
	"Invalid ICmp predicate value");	"Invalid ICmp predicate value");
	assert(getOperand(0)->getType() == getOperand(1)->getType() &&	assert(getOperand(0)->getType() == getOperand(1)->getType() &&
	"Both operands to ICmp instruction are not of the same type!");	"Both operands to ICmp instruction are not of the same type!");
	// Check that the operands are the right type	// Check that the operands are the right type
	assert((getOperand(0)->getType()->isIntOrIntVectorTy() \|\|	assert((getOperand(0)->getType()->isIntOrIntVectorTy() \|\|

	getOperand(0)->getType()->isPointerTy()) &&	getOperand(0)->getType()->getScalarType()->isPointerTy()) &&
	"Invalid operand types for ICmp instruction");	"Invalid operand types for ICmp instruction");
	}	}

	/// For example, EQ->EQ, SLE->SLE, UGT->SGT, etc.	/// For example, EQ->EQ, SLE->SLE, UGT->SGT, etc.
	/// @returns the predicate that would be the result if the operand were	/// @returns the predicate that would be the result if the operand were
	/// regarded as signed.	/// regarded as signed.
	/// @brief Return the signed version of the predicate	/// @brief Return the signed version of the predicate
	Predicate getSignedPredicate() const {	Predicate getSignedPredicate() const {
	return getSignedPredicate(getPredicate());	return getSignedPredicate(getPredicate());
	}	}

	skipping to change at line 1651	skipping to change at line 1665

	/// getType - Overload to return most specific vector type.	/// getType - Overload to return most specific vector type.
	///	///
	VectorType *getType() const {	VectorType *getType() const {
	return reinterpret_cast<VectorType*>(Instruction::getType());	return reinterpret_cast<VectorType*>(Instruction::getType());
	}	}

	/// Transparently provide more efficient getOperand methods.	/// Transparently provide more efficient getOperand methods.
	DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value);	DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value);


		Constant *getMask() const {
		return reinterpret_cast<Constant*>(getOperand(2));
		}

	/// getMaskValue - Return the index from the shuffle mask for the specifi ed	/// getMaskValue - Return the index from the shuffle mask for the specifi ed
	/// output result. This is either -1 if the element is undef or a number less	/// output result. This is either -1 if the element is undef or a number less
	/// than 2*numelements.	/// than 2*numelements.

	int getMaskValue(unsigned i) const;	static int getMaskValue(Constant *Mask, unsigned i);

		int getMaskValue(unsigned i) const {
		return getMaskValue(getMask(), i);
		}

		/// getShuffleMask - Return the full mask for this instruction, where eac
		h
		/// element is the element number and undef's are returned as -1.
		static void getShuffleMask(Constant *Mask, SmallVectorImpl<int> &Result);

		void getShuffleMask(SmallVectorImpl<int> &Result) const {
		return getShuffleMask(getMask(), Result);
		}

		SmallVector<int, 16> getShuffleMask() const {
		SmallVector<int, 16> Mask;
		getShuffleMask(Mask);
		return Mask;
		}

	// Methods for support type inquiry through isa, cast, and dyn_cast:	// Methods for support type inquiry through isa, cast, and dyn_cast:
	static inline bool classof(const ShuffleVectorInst *) { return true; }	static inline bool classof(const ShuffleVectorInst *) { return true; }
	static inline bool classof(const Instruction *I) {	static inline bool classof(const Instruction *I) {
	return I->getOpcode() == Instruction::ShuffleVector;	return I->getOpcode() == Instruction::ShuffleVector;
	}	}
	static inline bool classof(const Value *V) {	static inline bool classof(const Value *V) {
	return isa<Instruction>(V) && classof(cast<Instruction>(V));	return isa<Instruction>(V) && classof(cast<Instruction>(V));
	}	}
	};	};

	skipping to change at line 2424	skipping to change at line 2460

	/// SwitchInst ctor - Create a new switch instruction, specifying a value to	/// SwitchInst ctor - Create a new switch instruction, specifying a value to
	/// switch on and a default destination. The number of additional cases can	/// switch on and a default destination. The number of additional cases can
	/// be specified here to make memory allocation more efficient. This	/// be specified here to make memory allocation more efficient. This
	/// constructor also autoinserts at the end of the specified BasicBlock.	/// constructor also autoinserts at the end of the specified BasicBlock.
	SwitchInst(Value Value, BasicBlock Default, unsigned NumCases,	SwitchInst(Value Value, BasicBlock Default, unsigned NumCases,
	BasicBlock *InsertAtEnd);	BasicBlock *InsertAtEnd);
	protected:	protected:
	virtual SwitchInst *clone_impl() const;	virtual SwitchInst *clone_impl() const;
	public:	public:


		// -2
		static const unsigned DefaultPseudoIndex = static_cast<unsigned>(~0L-1);

		template <class SwitchInstTy, class ConstantIntTy, class BasicBlockTy>
		class CaseIteratorT {
		protected:

		SwitchInstTy *SI;
		unsigned Index;

		public:

		typedef CaseIteratorT<SwitchInstTy, ConstantIntTy, BasicBlockTy> Self;

		/// Initializes case iterator for given SwitchInst and for given
		/// case number.
		CaseIteratorT(SwitchInstTy *SI, unsigned CaseNum) {
		this->SI = SI;
		Index = CaseNum;
		}

		/// Initializes case iterator for given SwitchInst and for given
		/// TerminatorInst's successor index.
		static Self fromSuccessorIndex(SwitchInstTy *SI, unsigned SuccessorInde
		x) {
		assert(SuccessorIndex < SI->getNumSuccessors() &&
		"Successor index # out of range!");
		return SuccessorIndex != 0 ?
		Self(SI, SuccessorIndex - 1) :
		Self(SI, DefaultPseudoIndex);
		}

		/// Resolves case value for current case.
		ConstantIntTy *getCaseValue() {
		assert(Index < SI->getNumCases() && "Index out the number of cases.")
		;
		return reinterpret_cast<ConstantIntTy>(SI->getOperand(2 + Index2));
		}

		/// Resolves successor for current case.
		BasicBlockTy *getCaseSuccessor() {
		assert((Index < SI->getNumCases() \|\|
		Index == DefaultPseudoIndex) &&
		"Index out the number of cases.");
		return SI->getSuccessor(getSuccessorIndex());
		}

		/// Returns number of current case.
		unsigned getCaseIndex() const { return Index; }

		/// Returns TerminatorInst's successor index for current case successor
		.
		unsigned getSuccessorIndex() const {
		assert((Index == DefaultPseudoIndex \|\| Index < SI->getNumCases()) &&
		"Index out the number of cases.");
		return Index != DefaultPseudoIndex ? Index + 1 : 0;
		}

		Self operator++() {
		// Check index correctness after increment.
		// Note: Index == getNumCases() means end().
		assert(Index+1 <= SI->getNumCases() && "Index out the number of cases
		.");
		++Index;
		return *this;
		}
		Self operator++(int) {
		Self tmp = *this;
		++(*this);
		return tmp;
		}
		Self operator--() {
		// Check index correctness after decrement.
		// Note: Index == getNumCases() means end().
		// Also allow "-1" iterator here. That will became valid after ++.
		assert((Index == 0 \|\| Index-1 <= SI->getNumCases()) &&
		"Index out the number of cases.");
		--Index;
		return *this;
		}
		Self operator--(int) {
		Self tmp = *this;
		--(*this);
		return tmp;
		}
		bool operator==(const Self& RHS) const {
		assert(RHS.SI == SI && "Incompatible operators.");
		return RHS.Index == Index;
		}
		bool operator!=(const Self& RHS) const {
		assert(RHS.SI == SI && "Incompatible operators.");
		return RHS.Index != Index;
		}
		};

		typedef CaseIteratorT<const SwitchInst, const ConstantInt, const BasicBlo
		ck>
		ConstCaseIt;

		class CaseIt : public CaseIteratorT<SwitchInst, ConstantInt, BasicBlock>
		{

		typedef CaseIteratorT<SwitchInst, ConstantInt, BasicBlock> ParentTy;

		public:

		CaseIt(const ParentTy& Src) : ParentTy(Src) {}
		CaseIt(SwitchInst *SI, unsigned CaseNum) : ParentTy(SI, CaseNum) {}

		/// Sets the new value for current case.
		void setValue(ConstantInt *V) {
		assert(Index < SI->getNumCases() && "Index out the number of cases.")
		;
		SI->setOperand(2 + Index2, reinterpret_cast<Value>(V));
		}

		/// Sets the new successor for current case.
		void setSuccessor(BasicBlock *S) {
		SI->setSuccessor(getSuccessorIndex(), S);
		}
		};

	static SwitchInst Create(Value Value, BasicBlock *Default,	static SwitchInst Create(Value Value, BasicBlock *Default,
	unsigned NumCases, Instruction *InsertBefore = 0) {	unsigned NumCases, Instruction *InsertBefore = 0) {
	return new SwitchInst(Value, Default, NumCases, InsertBefore);	return new SwitchInst(Value, Default, NumCases, InsertBefore);
	}	}
	static SwitchInst Create(Value Value, BasicBlock *Default,	static SwitchInst Create(Value Value, BasicBlock *Default,
	unsigned NumCases, BasicBlock *InsertAtEnd) {	unsigned NumCases, BasicBlock *InsertAtEnd) {
	return new SwitchInst(Value, Default, NumCases, InsertAtEnd);	return new SwitchInst(Value, Default, NumCases, InsertAtEnd);
	}	}


	~SwitchInst();	~SwitchInst();

	/// Provide fast operand accessors	/// Provide fast operand accessors
	DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value);	DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value);

	// Accessor Methods for Switch stmt	// Accessor Methods for Switch stmt
	Value *getCondition() const { return getOperand(0); }	Value *getCondition() const { return getOperand(0); }
	void setCondition(Value *V) { setOperand(0, V); }	void setCondition(Value *V) { setOperand(0, V); }

	BasicBlock *getDefaultDest() const {	BasicBlock *getDefaultDest() const {
	return cast<BasicBlock>(getOperand(1));	return cast<BasicBlock>(getOperand(1));
	}	}


	/// getNumCases - return the number of 'cases' in this switch instruction	void setDefaultDest(BasicBlock *DefaultCase) {
	.	setOperand(1, reinterpret_cast<Value*>(DefaultCase));
	/// Note that case #0 is always the default case.
	unsigned getNumCases() const {
	return getNumOperands()/2;
	}	}


	/// getCaseValue - Return the specified case value. Note that case #0, t	/// getNumCases - return the number of 'cases' in this switch instruction
	he	,
	/// default destination, does not have a case value.	/// except the default case
	ConstantInt *getCaseValue(unsigned i) {	unsigned getNumCases() const {
	assert(i && i < getNumCases() && "Illegal case value to get!");	return getNumOperands()/2 - 1;
	return getSuccessorValue(i);
	}	}


	/// getCaseValue - Return the specified case value. Note that case #0, t	/// Returns a read/write iterator that points to the first
	he	/// case in SwitchInst.
	/// default destination, does not have a case value.	CaseIt case_begin() {
	const ConstantInt *getCaseValue(unsigned i) const {	return CaseIt(this, 0);
	assert(i && i < getNumCases() && "Illegal case value to get!");	}
	return getSuccessorValue(i);	/// Returns a read-only iterator that points to the first
		/// case in the SwitchInst.
		ConstCaseIt case_begin() const {
		return ConstCaseIt(this, 0);
		}

		/// Returns a read/write iterator that points one past the last
		/// in the SwitchInst.
		CaseIt case_end() {
		return CaseIt(this, getNumCases());
		}
		/// Returns a read-only iterator that points one past the last
		/// in the SwitchInst.
		ConstCaseIt case_end() const {
		return ConstCaseIt(this, getNumCases());
		}
		/// Returns an iterator that points to the default case.
		/// Note: this iterator allows to resolve successor only. Attempt
		/// to resolve case value causes an assertion.
		/// Also note, that increment and decrement also causes an assertion and
		/// makes iterator invalid.
		CaseIt case_default() {
		return CaseIt(this, DefaultPseudoIndex);
		}
		ConstCaseIt case_default() const {
		return ConstCaseIt(this, DefaultPseudoIndex);
	}	}

	/// findCaseValue - Search all of the case values for the specified const ant.	/// findCaseValue - Search all of the case values for the specified const ant.

	/// If it is explicitly handled, return the case number of it, otherwise	/// If it is explicitly handled, return the case iterator of it, otherwis
	/// return 0 to indicate that it is handled by the default handler.	e
	unsigned findCaseValue(const ConstantInt *C) const {	/// return default case iterator to indicate
	for (unsigned i = 1, e = getNumCases(); i != e; ++i)	/// that it is handled by the default handler.
	if (getCaseValue(i) == C)	CaseIt findCaseValue(const ConstantInt *C) {
		for (CaseIt i = case_begin(), e = case_end(); i != e; ++i)
		if (i.getCaseValue() == C)
	return i;	return i;

	return 0;	return case_default();
		}
		ConstCaseIt findCaseValue(const ConstantInt *C) const {
		for (ConstCaseIt i = case_begin(), e = case_end(); i != e; ++i)
		if (i.getCaseValue() == C)
		return i;
		return case_default();
	}	}

	/// findCaseDest - Finds the unique case value for a given successor. Ret urns	/// findCaseDest - Finds the unique case value for a given successor. Ret urns
	/// null if the successor is not found, not unique, or is the default cas e.	/// null if the successor is not found, not unique, or is the default cas e.
	ConstantInt findCaseDest(BasicBlock BB) {	ConstantInt findCaseDest(BasicBlock BB) {
	if (BB == getDefaultDest()) return NULL;	if (BB == getDefaultDest()) return NULL;

	ConstantInt *CI = NULL;	ConstantInt *CI = NULL;

	for (unsigned i = 1, e = getNumCases(); i != e; ++i) {	for (CaseIt i = case_begin(), e = case_end(); i != e; ++i) {
	if (getSuccessor(i) == BB) {	if (i.getCaseSuccessor() == BB) {
	if (CI) return NULL; // Multiple cases lead to BB.	if (CI) return NULL; // Multiple cases lead to BB.

	else CI = getCaseValue(i);	else CI = i.getCaseValue();
	}	}
	}	}
	return CI;	return CI;
	}	}

	/// addCase - Add an entry to the switch instruction...	/// addCase - Add an entry to the switch instruction...

	///	/// Note:
		/// This action invalidates case_end(). Old case_end() iterator will
		/// point to the added case.
	void addCase(ConstantInt OnVal, BasicBlock Dest);	void addCase(ConstantInt OnVal, BasicBlock Dest);


	/// removeCase - This method removes the specified successor from the swi	/// removeCase - This method removes the specified case and its successor
	tch	/// from the switch instruction. Note that this operation may reorder the
	/// instruction. Note that this cannot be used to remove the default
	/// destination (successor #0). Also note that this operation may reorder
	the
	/// remaining cases at index idx and above.	/// remaining cases at index idx and above.

	///	/// Note:
	void removeCase(unsigned idx);	/// This action invalidates iterators for all cases following the one rem
		oved,
		/// including the case_end() iterator.
		void removeCase(CaseIt i);

	unsigned getNumSuccessors() const { return getNumOperands()/2; }	unsigned getNumSuccessors() const { return getNumOperands()/2; }
	BasicBlock *getSuccessor(unsigned idx) const {	BasicBlock *getSuccessor(unsigned idx) const {
	assert(idx < getNumSuccessors() &&"Successor idx out of range for switc h!");	assert(idx < getNumSuccessors() &&"Successor idx out of range for switc h!");
	return cast<BasicBlock>(getOperand(idx*2+1));	return cast<BasicBlock>(getOperand(idx*2+1));
	}	}
	void setSuccessor(unsigned idx, BasicBlock *NewSucc) {	void setSuccessor(unsigned idx, BasicBlock *NewSucc) {
	assert(idx < getNumSuccessors() && "Successor # out of range for switch !");	assert(idx < getNumSuccessors() && "Successor # out of range for switch !");
	setOperand(idx2+1, (Value)NewSucc);	setOperand(idx2+1, (Value)NewSucc);
	}	}


	// getSuccessorValue - Return the value associated with the specified
	// successor.
	ConstantInt *getSuccessorValue(unsigned idx) const {
	assert(idx < getNumSuccessors() && "Successor # out of range!");
	return reinterpret_cast<ConstantInt>(getOperand(idx2));
	}

	// setSuccessorValue - Updates the value associated with the specified
	// successor.
	void setSuccessorValue(unsigned idx, ConstantInt* SuccessorValue) {
	assert(idx < getNumSuccessors() && "Successor # out of range!");
	setOperand(idx2, reinterpret_cast<Value>(SuccessorValue));
	}

	// Methods for support type inquiry through isa, cast, and dyn_cast:	// Methods for support type inquiry through isa, cast, and dyn_cast:
	static inline bool classof(const SwitchInst *) { return true; }	static inline bool classof(const SwitchInst *) { return true; }
	static inline bool classof(const Instruction *I) {	static inline bool classof(const Instruction *I) {
	return I->getOpcode() == Instruction::Switch;	return I->getOpcode() == Instruction::Switch;
	}	}
	static inline bool classof(const Value *V) {	static inline bool classof(const Value *V) {
	return isa<Instruction>(V) && classof(cast<Instruction>(V));	return isa<Instruction>(V) && classof(cast<Instruction>(V));
	}	}
	private:	private:
	virtual BasicBlock *getSuccessorV(unsigned idx) const;	virtual BasicBlock *getSuccessorV(unsigned idx) const;

	skipping to change at line 2880	skipping to change at line 3052
	->getElementType())->getReturnType(),	->getElementType())->getReturnType(),
	Instruction::Invoke,	Instruction::Invoke,
	OperandTraits<InvokeInst>::op_end(this) - Values,	OperandTraits<InvokeInst>::op_end(this) - Values,
	Values, InsertAtEnd) {	Values, InsertAtEnd) {
	init(Func, IfNormal, IfException, Args, NameStr);	init(Func, IfNormal, IfException, Args, NameStr);
	}	}

	DEFINE_TRANSPARENT_OPERAND_ACCESSORS(InvokeInst, Value)	DEFINE_TRANSPARENT_OPERAND_ACCESSORS(InvokeInst, Value)

	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	// UnwindInst Class
	//===----------------------------------------------------------------------
	===//

	//===----------------------------------------------------------------------
	-----
	/// UnwindInst - Immediately exit the current function, unwinding the stack
	/// until an invoke instruction is found.
	///
	class UnwindInst : public TerminatorInst {
	void *operator new(size_t, unsigned); // DO NOT IMPLEMENT
	protected:
	virtual UnwindInst *clone_impl() const;
	public:
	// allocate space for exactly zero operands
	void *operator new(size_t s) {
	return User::operator new(s, 0);
	}
	explicit UnwindInst(LLVMContext &C, Instruction *InsertBefore = 0);
	explicit UnwindInst(LLVMContext &C, BasicBlock *InsertAtEnd);

	unsigned getNumSuccessors() const { return 0; }

	// Methods for support type inquiry through isa, cast, and dyn_cast:
	static inline bool classof(const UnwindInst *) { return true; }
	static inline bool classof(const Instruction *I) {
	return I->getOpcode() == Instruction::Unwind;
	}
	static inline bool classof(const Value *V) {
	return isa<Instruction>(V) && classof(cast<Instruction>(V));
	}
	private:
	virtual BasicBlock *getSuccessorV(unsigned idx) const;
	virtual unsigned getNumSuccessorsV() const;
	virtual void setSuccessorV(unsigned idx, BasicBlock *B);
	};

	//===----------------------------------------------------------------------
	===//
	// ResumeInst Class	// ResumeInst Class
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	//===---------------------------------------------------------------------- -----	//===---------------------------------------------------------------------- -----
	/// ResumeInst - Resume the propagation of an exception.	/// ResumeInst - Resume the propagation of an exception.
	///	///
	class ResumeInst : public TerminatorInst {	class ResumeInst : public TerminatorInst {
	ResumeInst(const ResumeInst &RI);	ResumeInst(const ResumeInst &RI);

	explicit ResumeInst(Value Exn, Instruction InsertBefore=0);	explicit ResumeInst(Value Exn, Instruction InsertBefore=0);

End of changes. 23 change blocks.
	103 lines changed or deleted	242 lines changed or added

	Instrumentation.h	Instrumentation.h

	skipping to change at line 20	skipping to change at line 20
	// This file defines constructor functions for instrumentation passes.	// This file defines constructor functions for instrumentation passes.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_TRANSFORMS_INSTRUMENTATION_H	#ifndef LLVM_TRANSFORMS_INSTRUMENTATION_H
	#define LLVM_TRANSFORMS_INSTRUMENTATION_H	#define LLVM_TRANSFORMS_INSTRUMENTATION_H

	namespace llvm {	namespace llvm {

	class ModulePass;	class ModulePass;

		class FunctionPass;

	// Insert edge profiling instrumentation	// Insert edge profiling instrumentation
	ModulePass *createEdgeProfilerPass();	ModulePass *createEdgeProfilerPass();

	// Insert optimal edge profiling instrumentation	// Insert optimal edge profiling instrumentation
	ModulePass *createOptimalEdgeProfilerPass();	ModulePass *createOptimalEdgeProfilerPass();

	// Insert path profiling instrumentation	// Insert path profiling instrumentation
	ModulePass *createPathProfilerPass();	ModulePass *createPathProfilerPass();

	// Insert GCOV profiling instrumentation	// Insert GCOV profiling instrumentation
	ModulePass *createGCOVProfilerPass(bool EmitNotes = true, bool EmitData = t rue,	ModulePass *createGCOVProfilerPass(bool EmitNotes = true, bool EmitData = t rue,

	bool Use402Format = false);	bool Use402Format = false,
		bool UseExtraChecksum = false);

		// Insert AddressSanitizer (address sanity checking) instrumentation
		ModulePass *createAddressSanitizerPass();
		// Insert ThreadSanitizer (race detection) instrumentation
		FunctionPass *createThreadSanitizerPass();

	} // End llvm namespace	} // End llvm namespace

	#endif	#endif

End of changes. 2 change blocks.
	1 lines changed or deleted	8 lines changed or added

	IntervalIterator.h	IntervalIterator.h

	skipping to change at line 100	skipping to change at line 100
	bool IOwnMem; // If True, delete intervals when done with them	bool IOwnMem; // If True, delete intervals when done with them
	// See file header for conditions of use	// See file header for conditions of use
	public:	public:
	typedef IntervalIterator<NodeTy, OrigContainer_t> _Self;	typedef IntervalIterator<NodeTy, OrigContainer_t> _Self;
	typedef std::forward_iterator_tag iterator_category;	typedef std::forward_iterator_tag iterator_category;

	IntervalIterator() {} // End iterator, empty stack	IntervalIterator() {} // End iterator, empty stack
	IntervalIterator(Function *M, bool OwnMemory) : IOwnMem(OwnMemory) {	IntervalIterator(Function *M, bool OwnMemory) : IOwnMem(OwnMemory) {
	OrigContainer = M;	OrigContainer = M;
	if (!ProcessInterval(&M->front())) {	if (!ProcessInterval(&M->front())) {

	assert(0 && "ProcessInterval should never fail for first interval!");	llvm_unreachable("ProcessInterval should never fail for first interva l!");
	}	}
	}	}

	IntervalIterator(IntervalPartition &IP, bool OwnMemory) : IOwnMem(OwnMemo ry) {	IntervalIterator(IntervalPartition &IP, bool OwnMemory) : IOwnMem(OwnMemo ry) {
	OrigContainer = &IP;	OrigContainer = &IP;
	if (!ProcessInterval(IP.getRootInterval())) {	if (!ProcessInterval(IP.getRootInterval())) {

	assert(0 && "ProcessInterval should never fail for first interval!");	llvm_unreachable("ProcessInterval should never fail for first interva l!");
	}	}
	}	}

	inline ~IntervalIterator() {	inline ~IntervalIterator() {
	if (IOwnMem)	if (IOwnMem)
	while (!IntStack.empty()) {	while (!IntStack.empty()) {
	delete operator*();	delete operator*();
	IntStack.pop_back();	IntStack.pop_back();
	}	}
	}	}

End of changes. 2 change blocks.
	2 lines changed or deleted	2 lines changed or added

	IntervalMap.h	IntervalMap.h

	skipping to change at line 737	skipping to change at line 737
	}	}
	};	};

	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	//--- IntervalMapImpl::Path ---//	//--- IntervalMapImpl::Path ---//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	//	//
	// A Path is used by iterators to represent a position in a B+-tree, and th e	// A Path is used by iterators to represent a position in a B+-tree, and th e
	// path to get there from the root.	// path to get there from the root.
	//	//

	// The Path class also constains the tree navigation code that doesn't have to	// The Path class also contains the tree navigation code that doesn't have to
	// be templatized.	// be templatized.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	class Path {	class Path {
	/// Entry - Each step in the path is a node pointer and an offset into th at	/// Entry - Each step in the path is a node pointer and an offset into th at
	/// node.	/// node.
	struct Entry {	struct Entry {
	void *node;	void *node;
	unsigned size;	unsigned size;

	skipping to change at line 1972	skipping to change at line 1972
	}	}

	// Do we need to allocate a new node?	// Do we need to allocate a new node?
	unsigned NewNode = 0;	unsigned NewNode = 0;
	if (Elements + 1 > Nodes * NodeT::Capacity) {	if (Elements + 1 > Nodes * NodeT::Capacity) {
	// Insert NewNode at the penultimate position, or after a single node.	// Insert NewNode at the penultimate position, or after a single node.
	NewNode = Nodes == 1 ? 1 : Nodes - 1;	NewNode = Nodes == 1 ? 1 : Nodes - 1;
	CurSize[Nodes] = CurSize[NewNode];	CurSize[Nodes] = CurSize[NewNode];
	Node[Nodes] = Node[NewNode];	Node[Nodes] = Node[NewNode];
	CurSize[NewNode] = 0;	CurSize[NewNode] = 0;

	Node[NewNode] = this->map->newNode<NodeT>();	Node[NewNode] = this->map->template newNode<NodeT>();
	++Nodes;	++Nodes;
	}	}

	// Compute the new element distribution.	// Compute the new element distribution.
	unsigned NewSize[4];	unsigned NewSize[4];
	IdxPair NewOffset = distribute(Nodes, Elements, NodeT::Capacity,	IdxPair NewOffset = distribute(Nodes, Elements, NodeT::Capacity,
	CurSize, NewSize, Offset, true);	CurSize, NewSize, Offset, true);
	adjustSiblingSizes(Node, Nodes, CurSize, NewSize);	adjustSiblingSizes(Node, Nodes, CurSize, NewSize);

	// Move current location to the leftmost node.	// Move current location to the leftmost node.

End of changes. 2 change blocks.
	2 lines changed or deleted	2 lines changed or added

	IntrinsicInst.h	IntrinsicInst.h

	skipping to change at line 279	skipping to change at line 279
	// Methods for support type inquiry through isa, cast, and dyn_cast:	// Methods for support type inquiry through isa, cast, and dyn_cast:
	static inline bool classof(const MemMoveInst *) { return true; }	static inline bool classof(const MemMoveInst *) { return true; }
	static inline bool classof(const IntrinsicInst *I) {	static inline bool classof(const IntrinsicInst *I) {
	return I->getIntrinsicID() == Intrinsic::memmove;	return I->getIntrinsicID() == Intrinsic::memmove;
	}	}
	static inline bool classof(const Value *V) {	static inline bool classof(const Value *V) {
	return isa<IntrinsicInst>(V) && classof(cast<IntrinsicInst>(V));	return isa<IntrinsicInst>(V) && classof(cast<IntrinsicInst>(V));
	}	}
	};	};


	/// EHExceptionInst - This represents the llvm.eh.exception instruction.
	///
	class EHExceptionInst : public IntrinsicInst {
	public:
	// Methods for support type inquiry through isa, cast, and dyn_cast:
	static inline bool classof(const EHExceptionInst *) { return true; }
	static inline bool classof(const IntrinsicInst *I) {
	return I->getIntrinsicID() == Intrinsic::eh_exception;
	}
	static inline bool classof(const Value *V) {
	return isa<IntrinsicInst>(V) && classof(cast<IntrinsicInst>(V));
	}
	};

	/// EHSelectorInst - This represents the llvm.eh.selector instruction.
	///
	class EHSelectorInst : public IntrinsicInst {
	public:
	// Methods for support type inquiry through isa, cast, and dyn_cast:
	static inline bool classof(const EHSelectorInst *) { return true; }
	static inline bool classof(const IntrinsicInst *I) {
	return I->getIntrinsicID() == Intrinsic::eh_selector;
	}
	static inline bool classof(const Value *V) {
	return isa<IntrinsicInst>(V) && classof(cast<IntrinsicInst>(V));
	}
	};

	}	}

	#endif	#endif

End of changes. 1 change blocks.
	28 lines changed or deleted	0 lines changed or added

	Intrinsics.gen	Intrinsics.gen

	skipping to change at line 20	skipping to change at line 20
	#if defined(_MSC_VER) && defined(setjmp) && \	#if defined(_MSC_VER) && defined(setjmp) && \
	!defined(setjmp_undefined_for_msvc)	!defined(setjmp_undefined_for_msvc)
	# pragma push_macro("setjmp")	# pragma push_macro("setjmp")
	# undef setjmp	# undef setjmp
	# define setjmp_undefined_for_msvc	# define setjmp_undefined_for_msvc
	#endif	#endif

	// Enum values for Intrinsics.h	// Enum values for Intrinsics.h
	#ifdef GET_INTRINSIC_ENUM_VALUES	#ifdef GET_INTRINSIC_ENUM_VALUES
	adjust_trampoline, // llvm.adjust.trampoline	adjust_trampoline, // llvm.adjust.trampoline

	alpha_umulh, // llvm.alpha.umulh
	annotation, // llvm.annotation	annotation, // llvm.annotation
	arm_cdp, // llvm.arm.cdp	arm_cdp, // llvm.arm.cdp
	arm_cdp2, // llvm.arm.cdp2	arm_cdp2, // llvm.arm.cdp2
	arm_get_fpscr, // llvm.arm.get.fpscr	arm_get_fpscr, // llvm.arm.get.fpscr
	arm_ldrexd, // llvm.arm.ldrexd	arm_ldrexd, // llvm.arm.ldrexd
	arm_mcr, // llvm.arm.mcr	arm_mcr, // llvm.arm.mcr
	arm_mcr2, // llvm.arm.mcr2	arm_mcr2, // llvm.arm.mcr2
	arm_mcrr, // llvm.arm.mcrr	arm_mcrr, // llvm.arm.mcrr
	arm_mcrr2, // llvm.arm.mcrr2	arm_mcrr2, // llvm.arm.mcrr2
	arm_mrc, // llvm.arm.mrc	arm_mrc, // llvm.arm.mrc

	skipping to change at line 163	skipping to change at line 162
	convertuif, // llvm.convertuif	convertuif, // llvm.convertuif
	convertus, // llvm.convertus	convertus, // llvm.convertus
	convertuu, // llvm.convertuu	convertuu, // llvm.convertuu
	cos, // llvm.cos	cos, // llvm.cos
	ctlz, // llvm.ctlz	ctlz, // llvm.ctlz
	ctpop, // llvm.ctpop	ctpop, // llvm.ctpop
	cttz, // llvm.cttz	cttz, // llvm.cttz
	dbg_declare, // llvm.dbg.declare	dbg_declare, // llvm.dbg.declare
	dbg_value, // llvm.dbg.value	dbg_value, // llvm.dbg.value
	eh_dwarf_cfa, // llvm.eh.dwarf.cfa	eh_dwarf_cfa, // llvm.eh.dwarf.cfa

	eh_exception, // llvm.eh.exception
	eh_resume, // llvm.eh.resume
	eh_return_i32, // llvm.eh.return.i32	eh_return_i32, // llvm.eh.return.i32
	eh_return_i64, // llvm.eh.return.i64	eh_return_i64, // llvm.eh.return.i64

	eh_selector, // llvm.eh.selector
	eh_sjlj_callsite, // llvm.eh.sjlj.callsite	eh_sjlj_callsite, // llvm.eh.sjlj.callsite

	eh_sjlj_dispatch_setup, // llvm.eh.sjlj.dispatch.setu p
	eh_sjlj_functioncontext, // llvm.eh.sjlj.functionconte xt	eh_sjlj_functioncontext, // llvm.eh.sjlj.functionconte xt
	eh_sjlj_longjmp, // llvm.eh.sjlj.longjmp	eh_sjlj_longjmp, // llvm.eh.sjlj.longjmp
	eh_sjlj_lsda, // llvm.eh.sjlj.lsda	eh_sjlj_lsda, // llvm.eh.sjlj.lsda
	eh_sjlj_setjmp, // llvm.eh.sjlj.setjmp	eh_sjlj_setjmp, // llvm.eh.sjlj.setjmp
	eh_typeid_for, // llvm.eh.typeid.for	eh_typeid_for, // llvm.eh.typeid.for
	eh_unwind_init, // llvm.eh.unwind.init	eh_unwind_init, // llvm.eh.unwind.init
	exp, // llvm.exp	exp, // llvm.exp
	exp2, // llvm.exp2	exp2, // llvm.exp2
	expect, // llvm.expect	expect, // llvm.expect
	flt_rounds, // llvm.flt.rounds	flt_rounds, // llvm.flt.rounds
	fma, // llvm.fma	fma, // llvm.fma
	frameaddress, // llvm.frameaddress	frameaddress, // llvm.frameaddress
	gcread, // llvm.gcread	gcread, // llvm.gcread
	gcroot, // llvm.gcroot	gcroot, // llvm.gcroot
	gcwrite, // llvm.gcwrite	gcwrite, // llvm.gcwrite

		hexagon_A2_abs, // llvm.hexagon.A2.abs
		hexagon_A2_absp, // llvm.hexagon.A2.absp
		hexagon_A2_abssat, // llvm.hexagon.A2.abssat
		hexagon_A2_add, // llvm.hexagon.A2.add
		hexagon_A2_addh_h16_hh, // llvm.hexagon.A2.addh.h16.h
		h
		hexagon_A2_addh_h16_hl, // llvm.hexagon.A2.addh.h16.h
		l
		hexagon_A2_addh_h16_lh, // llvm.hexagon.A2.addh.h16.l
		h
		hexagon_A2_addh_h16_ll, // llvm.hexagon.A2.addh.h16.l
		l
		hexagon_A2_addh_h16_sat_hh, // llvm.hexagon.A2.addh.h16.s
		at.hh
		hexagon_A2_addh_h16_sat_hl, // llvm.hexagon.A2.addh.h16.s
		at.hl
		hexagon_A2_addh_h16_sat_lh, // llvm.hexagon.A2.addh.h16.s
		at.lh
		hexagon_A2_addh_h16_sat_ll, // llvm.hexagon.A2.addh.h16.s
		at.ll
		hexagon_A2_addh_l16_hh, // llvm.hexagon.A2.addh.l16.h
		h
		hexagon_A2_addh_l16_hl, // llvm.hexagon.A2.addh.l16.h
		l
		hexagon_A2_addh_l16_lh, // llvm.hexagon.A2.addh.l16.l
		h
		hexagon_A2_addh_l16_ll, // llvm.hexagon.A2.addh.l16.l
		l
		hexagon_A2_addh_l16_sat_hh, // llvm.hexagon.A2.addh.l16.s
		at.hh
		hexagon_A2_addh_l16_sat_hl, // llvm.hexagon.A2.addh.l16.s
		at.hl
		hexagon_A2_addh_l16_sat_lh, // llvm.hexagon.A2.addh.l16.s
		at.lh
		hexagon_A2_addh_l16_sat_ll, // llvm.hexagon.A2.addh.l16.s
		at.ll
		hexagon_A2_addi, // llvm.hexagon.A2.addi
		hexagon_A2_addp, // llvm.hexagon.A2.addp
		hexagon_A2_addpsat, // llvm.hexagon.A2.addpsat
		hexagon_A2_addsat, // llvm.hexagon.A2.addsat
		hexagon_A2_addsp, // llvm.hexagon.A2.addsp
		hexagon_A2_and, // llvm.hexagon.A2.and
		hexagon_A2_andir, // llvm.hexagon.A2.andir
		hexagon_A2_andp, // llvm.hexagon.A2.andp
		hexagon_A2_aslh, // llvm.hexagon.A2.aslh
		hexagon_A2_asrh, // llvm.hexagon.A2.asrh
		hexagon_A2_combine_hh, // llvm.hexagon.A2.combine.hh
		hexagon_A2_combine_hl, // llvm.hexagon.A2.combine.hl
		hexagon_A2_combine_lh, // llvm.hexagon.A2.combine.lh
		hexagon_A2_combine_ll, // llvm.hexagon.A2.combine.ll
		hexagon_A2_combineii, // llvm.hexagon.A2.combineii
		hexagon_A2_combinew, // llvm.hexagon.A2.combinew
		hexagon_A2_max, // llvm.hexagon.A2.max
		hexagon_A2_maxp, // llvm.hexagon.A2.maxp
		hexagon_A2_maxu, // llvm.hexagon.A2.maxu
		hexagon_A2_maxup, // llvm.hexagon.A2.maxup
		hexagon_A2_min, // llvm.hexagon.A2.min
		hexagon_A2_minp, // llvm.hexagon.A2.minp
		hexagon_A2_minu, // llvm.hexagon.A2.minu
		hexagon_A2_minup, // llvm.hexagon.A2.minup
		hexagon_A2_neg, // llvm.hexagon.A2.neg
		hexagon_A2_negp, // llvm.hexagon.A2.negp
		hexagon_A2_negsat, // llvm.hexagon.A2.negsat
		hexagon_A2_not, // llvm.hexagon.A2.not
		hexagon_A2_notp, // llvm.hexagon.A2.notp
		hexagon_A2_or, // llvm.hexagon.A2.or
		hexagon_A2_orir, // llvm.hexagon.A2.orir
		hexagon_A2_orp, // llvm.hexagon.A2.orp
		hexagon_A2_sat, // llvm.hexagon.A2.sat
		hexagon_A2_satb, // llvm.hexagon.A2.satb
		hexagon_A2_sath, // llvm.hexagon.A2.sath
		hexagon_A2_satub, // llvm.hexagon.A2.satub
		hexagon_A2_satuh, // llvm.hexagon.A2.satuh
		hexagon_A2_sub, // llvm.hexagon.A2.sub
		hexagon_A2_subh_h16_hh, // llvm.hexagon.A2.subh.h16.h
		h
		hexagon_A2_subh_h16_hl, // llvm.hexagon.A2.subh.h16.h
		l
		hexagon_A2_subh_h16_lh, // llvm.hexagon.A2.subh.h16.l
		h
		hexagon_A2_subh_h16_ll, // llvm.hexagon.A2.subh.h16.l
		l
		hexagon_A2_subh_h16_sat_hh, // llvm.hexagon.A2.subh.h16.s
		at.hh
		hexagon_A2_subh_h16_sat_hl, // llvm.hexagon.A2.subh.h16.s
		at.hl
		hexagon_A2_subh_h16_sat_lh, // llvm.hexagon.A2.subh.h16.s
		at.lh
		hexagon_A2_subh_h16_sat_ll, // llvm.hexagon.A2.subh.h16.s
		at.ll
		hexagon_A2_subh_l16_hl, // llvm.hexagon.A2.subh.l16.h
		l
		hexagon_A2_subh_l16_ll, // llvm.hexagon.A2.subh.l16.l
		l
		hexagon_A2_subh_l16_sat_hl, // llvm.hexagon.A2.subh.l16.s
		at.hl
		hexagon_A2_subh_l16_sat_ll, // llvm.hexagon.A2.subh.l16.s
		at.ll
		hexagon_A2_subp, // llvm.hexagon.A2.subp
		hexagon_A2_subri, // llvm.hexagon.A2.subri
		hexagon_A2_subsat, // llvm.hexagon.A2.subsat
		hexagon_A2_svaddh, // llvm.hexagon.A2.svaddh
		hexagon_A2_svaddhs, // llvm.hexagon.A2.svaddhs
		hexagon_A2_svadduhs, // llvm.hexagon.A2.svadduhs
		hexagon_A2_svavgh, // llvm.hexagon.A2.svavgh
		hexagon_A2_svavghs, // llvm.hexagon.A2.svavghs
		hexagon_A2_svnavgh, // llvm.hexagon.A2.svnavgh
		hexagon_A2_svsubh, // llvm.hexagon.A2.svsubh
		hexagon_A2_svsubhs, // llvm.hexagon.A2.svsubhs
		hexagon_A2_svsubuhs, // llvm.hexagon.A2.svsubuhs
		hexagon_A2_swiz, // llvm.hexagon.A2.swiz
		hexagon_A2_sxtb, // llvm.hexagon.A2.sxtb
		hexagon_A2_sxth, // llvm.hexagon.A2.sxth
		hexagon_A2_sxtw, // llvm.hexagon.A2.sxtw
		hexagon_A2_tfr, // llvm.hexagon.A2.tfr
		hexagon_A2_tfrih, // llvm.hexagon.A2.tfrih
		hexagon_A2_tfril, // llvm.hexagon.A2.tfril
		hexagon_A2_tfrp, // llvm.hexagon.A2.tfrp
		hexagon_A2_tfrpi, // llvm.hexagon.A2.tfrpi
		hexagon_A2_tfrsi, // llvm.hexagon.A2.tfrsi
		hexagon_A2_vabsh, // llvm.hexagon.A2.vabsh
		hexagon_A2_vabshsat, // llvm.hexagon.A2.vabshsat
		hexagon_A2_vabsw, // llvm.hexagon.A2.vabsw
		hexagon_A2_vabswsat, // llvm.hexagon.A2.vabswsat
		hexagon_A2_vaddh, // llvm.hexagon.A2.vaddh
		hexagon_A2_vaddhs, // llvm.hexagon.A2.vaddhs
		hexagon_A2_vaddub, // llvm.hexagon.A2.vaddub
		hexagon_A2_vaddubs, // llvm.hexagon.A2.vaddubs
		hexagon_A2_vadduhs, // llvm.hexagon.A2.vadduhs
		hexagon_A2_vaddw, // llvm.hexagon.A2.vaddw
		hexagon_A2_vaddws, // llvm.hexagon.A2.vaddws
		hexagon_A2_vavgh, // llvm.hexagon.A2.vavgh
		hexagon_A2_vavghcr, // llvm.hexagon.A2.vavghcr
		hexagon_A2_vavghr, // llvm.hexagon.A2.vavghr
		hexagon_A2_vavgub, // llvm.hexagon.A2.vavgub
		hexagon_A2_vavgubr, // llvm.hexagon.A2.vavgubr
		hexagon_A2_vavguh, // llvm.hexagon.A2.vavguh
		hexagon_A2_vavguhr, // llvm.hexagon.A2.vavguhr
		hexagon_A2_vavguw, // llvm.hexagon.A2.vavguw
		hexagon_A2_vavguwr, // llvm.hexagon.A2.vavguwr
		hexagon_A2_vavgw, // llvm.hexagon.A2.vavgw
		hexagon_A2_vavgwcr, // llvm.hexagon.A2.vavgwcr
		hexagon_A2_vavgwr, // llvm.hexagon.A2.vavgwr
		hexagon_A2_vcmpbeq, // llvm.hexagon.A2.vcmpbeq
		hexagon_A2_vcmpbgtu, // llvm.hexagon.A2.vcmpbgtu
		hexagon_A2_vcmpheq, // llvm.hexagon.A2.vcmpheq
		hexagon_A2_vcmphgt, // llvm.hexagon.A2.vcmphgt
		hexagon_A2_vcmphgtu, // llvm.hexagon.A2.vcmphgtu
		hexagon_A2_vcmpweq, // llvm.hexagon.A2.vcmpweq
		hexagon_A2_vcmpwgt, // llvm.hexagon.A2.vcmpwgt
		hexagon_A2_vcmpwgtu, // llvm.hexagon.A2.vcmpwgtu
		hexagon_A2_vconj, // llvm.hexagon.A2.vconj
		hexagon_A2_vmaxh, // llvm.hexagon.A2.vmaxh
		hexagon_A2_vmaxub, // llvm.hexagon.A2.vmaxub
		hexagon_A2_vmaxuh, // llvm.hexagon.A2.vmaxuh
		hexagon_A2_vmaxuw, // llvm.hexagon.A2.vmaxuw
		hexagon_A2_vmaxw, // llvm.hexagon.A2.vmaxw
		hexagon_A2_vminh, // llvm.hexagon.A2.vminh
		hexagon_A2_vminub, // llvm.hexagon.A2.vminub
		hexagon_A2_vminuh, // llvm.hexagon.A2.vminuh
		hexagon_A2_vminuw, // llvm.hexagon.A2.vminuw
		hexagon_A2_vminw, // llvm.hexagon.A2.vminw
		hexagon_A2_vnavgh, // llvm.hexagon.A2.vnavgh
		hexagon_A2_vnavghcr, // llvm.hexagon.A2.vnavghcr
		hexagon_A2_vnavghr, // llvm.hexagon.A2.vnavghr
		hexagon_A2_vnavgw, // llvm.hexagon.A2.vnavgw
		hexagon_A2_vnavgwcr, // llvm.hexagon.A2.vnavgwcr
		hexagon_A2_vnavgwr, // llvm.hexagon.A2.vnavgwr
		hexagon_A2_vraddub, // llvm.hexagon.A2.vraddub
		hexagon_A2_vraddub_acc, // llvm.hexagon.A2.vraddub.ac
		c
		hexagon_A2_vrsadub, // llvm.hexagon.A2.vrsadub
		hexagon_A2_vrsadub_acc, // llvm.hexagon.A2.vrsadub.ac
		c
		hexagon_A2_vsubh, // llvm.hexagon.A2.vsubh
		hexagon_A2_vsubhs, // llvm.hexagon.A2.vsubhs
		hexagon_A2_vsubub, // llvm.hexagon.A2.vsubub
		hexagon_A2_vsububs, // llvm.hexagon.A2.vsububs
		hexagon_A2_vsubuhs, // llvm.hexagon.A2.vsubuhs
		hexagon_A2_vsubw, // llvm.hexagon.A2.vsubw
		hexagon_A2_vsubws, // llvm.hexagon.A2.vsubws
		hexagon_A2_xor, // llvm.hexagon.A2.xor
		hexagon_A2_xorp, // llvm.hexagon.A2.xorp
		hexagon_A2_zxtb, // llvm.hexagon.A2.zxtb
		hexagon_A2_zxth, // llvm.hexagon.A2.zxth
		hexagon_A4_andn, // llvm.hexagon.A4.andn
		hexagon_A4_andnp, // llvm.hexagon.A4.andnp
		hexagon_A4_combineir, // llvm.hexagon.A4.combineir
		hexagon_A4_combineri, // llvm.hexagon.A4.combineri
		hexagon_A4_cround_ri, // llvm.hexagon.A4.cround.ri
		hexagon_A4_cround_rr, // llvm.hexagon.A4.cround.rr
		hexagon_A4_modwrapu, // llvm.hexagon.A4.modwrapu
		hexagon_A4_orn, // llvm.hexagon.A4.orn
		hexagon_A4_ornp, // llvm.hexagon.A4.ornp
		hexagon_A4_rcmpeq, // llvm.hexagon.A4.rcmpeq
		hexagon_A4_rcmpeqi, // llvm.hexagon.A4.rcmpeqi
		hexagon_A4_rcmpneq, // llvm.hexagon.A4.rcmpneq
		hexagon_A4_rcmpneqi, // llvm.hexagon.A4.rcmpneqi
		hexagon_A4_round_ri, // llvm.hexagon.A4.round.ri
		hexagon_A4_round_ri_sat, // llvm.hexagon.A4.round.ri.s
		at
		hexagon_A4_round_rr, // llvm.hexagon.A4.round.rr
		hexagon_A4_round_rr_sat, // llvm.hexagon.A4.round.rr.s
		at
		hexagon_C2_all8, // llvm.hexagon.C2.all8
		hexagon_C2_and, // llvm.hexagon.C2.and
		hexagon_C2_andn, // llvm.hexagon.C2.andn
		hexagon_C2_any8, // llvm.hexagon.C2.any8
		hexagon_C2_bitsclr, // llvm.hexagon.C2.bitsclr
		hexagon_C2_bitsclri, // llvm.hexagon.C2.bitsclri
		hexagon_C2_bitsset, // llvm.hexagon.C2.bitsset
		hexagon_C2_cmpeq, // llvm.hexagon.C2.cmpeq
		hexagon_C2_cmpeqi, // llvm.hexagon.C2.cmpeqi
		hexagon_C2_cmpeqp, // llvm.hexagon.C2.cmpeqp
		hexagon_C2_cmpgei, // llvm.hexagon.C2.cmpgei
		hexagon_C2_cmpgeui, // llvm.hexagon.C2.cmpgeui
		hexagon_C2_cmpgt, // llvm.hexagon.C2.cmpgt
		hexagon_C2_cmpgti, // llvm.hexagon.C2.cmpgti
		hexagon_C2_cmpgtp, // llvm.hexagon.C2.cmpgtp
		hexagon_C2_cmpgtu, // llvm.hexagon.C2.cmpgtu
		hexagon_C2_cmpgtui, // llvm.hexagon.C2.cmpgtui
		hexagon_C2_cmpgtup, // llvm.hexagon.C2.cmpgtup
		hexagon_C2_cmplt, // llvm.hexagon.C2.cmplt
		hexagon_C2_cmpltu, // llvm.hexagon.C2.cmpltu
		hexagon_C2_mask, // llvm.hexagon.C2.mask
		hexagon_C2_mux, // llvm.hexagon.C2.mux
		hexagon_C2_muxii, // llvm.hexagon.C2.muxii
		hexagon_C2_muxir, // llvm.hexagon.C2.muxir
		hexagon_C2_muxri, // llvm.hexagon.C2.muxri
		hexagon_C2_not, // llvm.hexagon.C2.not
		hexagon_C2_or, // llvm.hexagon.C2.or
		hexagon_C2_orn, // llvm.hexagon.C2.orn
		hexagon_C2_pxfer_map, // llvm.hexagon.C2.pxfer.map
		hexagon_C2_tfrpr, // llvm.hexagon.C2.tfrpr
		hexagon_C2_tfrrp, // llvm.hexagon.C2.tfrrp
		hexagon_C2_vitpack, // llvm.hexagon.C2.vitpack
		hexagon_C2_vmux, // llvm.hexagon.C2.vmux
		hexagon_C2_xor, // llvm.hexagon.C2.xor
		hexagon_C4_and_and, // llvm.hexagon.C4.and.and
		hexagon_C4_and_andn, // llvm.hexagon.C4.and.andn
		hexagon_C4_and_or, // llvm.hexagon.C4.and.or
		hexagon_C4_and_orn, // llvm.hexagon.C4.and.orn
		hexagon_C4_cmplte, // llvm.hexagon.C4.cmplte
		hexagon_C4_cmpltei, // llvm.hexagon.C4.cmpltei
		hexagon_C4_cmplteu, // llvm.hexagon.C4.cmplteu
		hexagon_C4_cmplteui, // llvm.hexagon.C4.cmplteui
		hexagon_C4_cmpneq, // llvm.hexagon.C4.cmpneq
		hexagon_C4_cmpneqi, // llvm.hexagon.C4.cmpneqi
		hexagon_C4_fastcorner9, // llvm.hexagon.C4.fastcorner
		9
		hexagon_C4_fastcorner9_not, // llvm.hexagon.C4.fastcorner
		9.not
		hexagon_C4_or_and, // llvm.hexagon.C4.or.and
		hexagon_C4_or_andn, // llvm.hexagon.C4.or.andn
		hexagon_C4_or_or, // llvm.hexagon.C4.or.or
		hexagon_C4_or_orn, // llvm.hexagon.C4.or.orn
		hexagon_M2_acci, // llvm.hexagon.M2.acci
		hexagon_M2_accii, // llvm.hexagon.M2.accii
		hexagon_M2_cmaci_s0, // llvm.hexagon.M2.cmaci.s0
		hexagon_M2_cmacr_s0, // llvm.hexagon.M2.cmacr.s0
		hexagon_M2_cmacs_s0, // llvm.hexagon.M2.cmacs.s0
		hexagon_M2_cmacs_s1, // llvm.hexagon.M2.cmacs.s1
		hexagon_M2_cmacsc_s0, // llvm.hexagon.M2.cmacsc.s0
		hexagon_M2_cmacsc_s1, // llvm.hexagon.M2.cmacsc.s1
		hexagon_M2_cmpyi_s0, // llvm.hexagon.M2.cmpyi.s0
		hexagon_M2_cmpyr_s0, // llvm.hexagon.M2.cmpyr.s0
		hexagon_M2_cmpyrs_s0, // llvm.hexagon.M2.cmpyrs.s0
		hexagon_M2_cmpyrs_s1, // llvm.hexagon.M2.cmpyrs.s1
		hexagon_M2_cmpyrsc_s0, // llvm.hexagon.M2.cmpyrsc.s0
		hexagon_M2_cmpyrsc_s1, // llvm.hexagon.M2.cmpyrsc.s1
		hexagon_M2_cmpys_s0, // llvm.hexagon.M2.cmpys.s0
		hexagon_M2_cmpys_s1, // llvm.hexagon.M2.cmpys.s1
		hexagon_M2_cmpysc_s0, // llvm.hexagon.M2.cmpysc.s0
		hexagon_M2_cmpysc_s1, // llvm.hexagon.M2.cmpysc.s1
		hexagon_M2_cnacs_s0, // llvm.hexagon.M2.cnacs.s0
		hexagon_M2_cnacs_s1, // llvm.hexagon.M2.cnacs.s1
		hexagon_M2_cnacsc_s0, // llvm.hexagon.M2.cnacsc.s0
		hexagon_M2_cnacsc_s1, // llvm.hexagon.M2.cnacsc.s1
		hexagon_M2_dpmpyss_acc_s0, // llvm.hexagon.M2.dpmpyss.ac
		c.s0
		hexagon_M2_dpmpyss_nac_s0, // llvm.hexagon.M2.dpmpyss.na
		c.s0
		hexagon_M2_dpmpyss_rnd_s0, // llvm.hexagon.M2.dpmpyss.rn
		d.s0
		hexagon_M2_dpmpyss_s0, // llvm.hexagon.M2.dpmpyss.s0
		hexagon_M2_dpmpyuu_acc_s0, // llvm.hexagon.M2.dpmpyuu.ac
		c.s0
		hexagon_M2_dpmpyuu_nac_s0, // llvm.hexagon.M2.dpmpyuu.na
		c.s0
		hexagon_M2_dpmpyuu_s0, // llvm.hexagon.M2.dpmpyuu.s0
		hexagon_M2_hmmpyh_rs1, // llvm.hexagon.M2.hmmpyh.rs1
		hexagon_M2_hmmpyl_rs1, // llvm.hexagon.M2.hmmpyl.rs1
		hexagon_M2_maci, // llvm.hexagon.M2.maci
		hexagon_M2_macsin, // llvm.hexagon.M2.macsin
		hexagon_M2_macsip, // llvm.hexagon.M2.macsip
		hexagon_M2_mmachs_rs0, // llvm.hexagon.M2.mmachs.rs0
		hexagon_M2_mmachs_rs1, // llvm.hexagon.M2.mmachs.rs1
		hexagon_M2_mmachs_s0, // llvm.hexagon.M2.mmachs.s0
		hexagon_M2_mmachs_s1, // llvm.hexagon.M2.mmachs.s1
		hexagon_M2_mmacls_rs0, // llvm.hexagon.M2.mmacls.rs0
		hexagon_M2_mmacls_rs1, // llvm.hexagon.M2.mmacls.rs1
		hexagon_M2_mmacls_s0, // llvm.hexagon.M2.mmacls.s0
		hexagon_M2_mmacls_s1, // llvm.hexagon.M2.mmacls.s1
		hexagon_M2_mmacuhs_rs0, // llvm.hexagon.M2.mmacuhs.rs
		0
		hexagon_M2_mmacuhs_rs1, // llvm.hexagon.M2.mmacuhs.rs
		1
		hexagon_M2_mmacuhs_s0, // llvm.hexagon.M2.mmacuhs.s0
		hexagon_M2_mmacuhs_s1, // llvm.hexagon.M2.mmacuhs.s1
		hexagon_M2_mmaculs_rs0, // llvm.hexagon.M2.mmaculs.rs
		0
		hexagon_M2_mmaculs_rs1, // llvm.hexagon.M2.mmaculs.rs
		1
		hexagon_M2_mmaculs_s0, // llvm.hexagon.M2.mmaculs.s0
		hexagon_M2_mmaculs_s1, // llvm.hexagon.M2.mmaculs.s1
		hexagon_M2_mmpyh_rs0, // llvm.hexagon.M2.mmpyh.rs0
		hexagon_M2_mmpyh_rs1, // llvm.hexagon.M2.mmpyh.rs1
		hexagon_M2_mmpyh_s0, // llvm.hexagon.M2.mmpyh.s0
		hexagon_M2_mmpyh_s1, // llvm.hexagon.M2.mmpyh.s1
		hexagon_M2_mmpyl_rs0, // llvm.hexagon.M2.mmpyl.rs0
		hexagon_M2_mmpyl_rs1, // llvm.hexagon.M2.mmpyl.rs1
		hexagon_M2_mmpyl_s0, // llvm.hexagon.M2.mmpyl.s0
		hexagon_M2_mmpyl_s1, // llvm.hexagon.M2.mmpyl.s1
		hexagon_M2_mmpyuh_rs0, // llvm.hexagon.M2.mmpyuh.rs0
		hexagon_M2_mmpyuh_rs1, // llvm.hexagon.M2.mmpyuh.rs1
		hexagon_M2_mmpyuh_s0, // llvm.hexagon.M2.mmpyuh.s0
		hexagon_M2_mmpyuh_s1, // llvm.hexagon.M2.mmpyuh.s1
		hexagon_M2_mmpyul_rs0, // llvm.hexagon.M2.mmpyul.rs0
		hexagon_M2_mmpyul_rs1, // llvm.hexagon.M2.mmpyul.rs1
		hexagon_M2_mmpyul_s0, // llvm.hexagon.M2.mmpyul.s0
		hexagon_M2_mmpyul_s1, // llvm.hexagon.M2.mmpyul.s1
		hexagon_M2_mpy_acc_hh_s0, // llvm.hexagon.M2.mpy.acc.hh
		.s0
		hexagon_M2_mpy_acc_hh_s1, // llvm.hexagon.M2.mpy.acc.hh
		.s1
		hexagon_M2_mpy_acc_hl_s0, // llvm.hexagon.M2.mpy.acc.hl
		.s0
		hexagon_M2_mpy_acc_hl_s1, // llvm.hexagon.M2.mpy.acc.hl
		.s1
		hexagon_M2_mpy_acc_lh_s0, // llvm.hexagon.M2.mpy.acc.lh
		.s0
		hexagon_M2_mpy_acc_lh_s1, // llvm.hexagon.M2.mpy.acc.lh
		.s1
		hexagon_M2_mpy_acc_ll_s0, // llvm.hexagon.M2.mpy.acc.ll
		.s0
		hexagon_M2_mpy_acc_ll_s1, // llvm.hexagon.M2.mpy.acc.ll
		.s1
		hexagon_M2_mpy_acc_sat_hh_s0, // llvm.hexagon.M2.mpy.acc.sa
		t.hh.s0
		hexagon_M2_mpy_acc_sat_hh_s1, // llvm.hexagon.M2.mpy.acc.sa
		t.hh.s1
		hexagon_M2_mpy_acc_sat_hl_s0, // llvm.hexagon.M2.mpy.acc.sa
		t.hl.s0
		hexagon_M2_mpy_acc_sat_hl_s1, // llvm.hexagon.M2.mpy.acc.sa
		t.hl.s1
		hexagon_M2_mpy_acc_sat_lh_s0, // llvm.hexagon.M2.mpy.acc.sa
		t.lh.s0
		hexagon_M2_mpy_acc_sat_lh_s1, // llvm.hexagon.M2.mpy.acc.sa
		t.lh.s1
		hexagon_M2_mpy_acc_sat_ll_s0, // llvm.hexagon.M2.mpy.acc.sa
		t.ll.s0
		hexagon_M2_mpy_acc_sat_ll_s1, // llvm.hexagon.M2.mpy.acc.sa
		t.ll.s1
		hexagon_M2_mpy_hh_s0, // llvm.hexagon.M2.mpy.hh.s0
		hexagon_M2_mpy_hh_s1, // llvm.hexagon.M2.mpy.hh.s1
		hexagon_M2_mpy_hl_s0, // llvm.hexagon.M2.mpy.hl.s0
		hexagon_M2_mpy_hl_s1, // llvm.hexagon.M2.mpy.hl.s1
		hexagon_M2_mpy_lh_s0, // llvm.hexagon.M2.mpy.lh.s0
		hexagon_M2_mpy_lh_s1, // llvm.hexagon.M2.mpy.lh.s1
		hexagon_M2_mpy_ll_s0, // llvm.hexagon.M2.mpy.ll.s0
		hexagon_M2_mpy_ll_s1, // llvm.hexagon.M2.mpy.ll.s1
		hexagon_M2_mpy_nac_hh_s0, // llvm.hexagon.M2.mpy.nac.hh
		.s0
		hexagon_M2_mpy_nac_hh_s1, // llvm.hexagon.M2.mpy.nac.hh
		.s1
		hexagon_M2_mpy_nac_hl_s0, // llvm.hexagon.M2.mpy.nac.hl
		.s0
		hexagon_M2_mpy_nac_hl_s1, // llvm.hexagon.M2.mpy.nac.hl
		.s1
		hexagon_M2_mpy_nac_lh_s0, // llvm.hexagon.M2.mpy.nac.lh
		.s0
		hexagon_M2_mpy_nac_lh_s1, // llvm.hexagon.M2.mpy.nac.lh
		.s1
		hexagon_M2_mpy_nac_ll_s0, // llvm.hexagon.M2.mpy.nac.ll
		.s0
		hexagon_M2_mpy_nac_ll_s1, // llvm.hexagon.M2.mpy.nac.ll
		.s1
		hexagon_M2_mpy_nac_sat_hh_s0, // llvm.hexagon.M2.mpy.nac.sa
		t.hh.s0
		hexagon_M2_mpy_nac_sat_hh_s1, // llvm.hexagon.M2.mpy.nac.sa
		t.hh.s1
		hexagon_M2_mpy_nac_sat_hl_s0, // llvm.hexagon.M2.mpy.nac.sa
		t.hl.s0
		hexagon_M2_mpy_nac_sat_hl_s1, // llvm.hexagon.M2.mpy.nac.sa
		t.hl.s1
		hexagon_M2_mpy_nac_sat_lh_s0, // llvm.hexagon.M2.mpy.nac.sa
		t.lh.s0
		hexagon_M2_mpy_nac_sat_lh_s1, // llvm.hexagon.M2.mpy.nac.sa
		t.lh.s1
		hexagon_M2_mpy_nac_sat_ll_s0, // llvm.hexagon.M2.mpy.nac.sa
		t.ll.s0
		hexagon_M2_mpy_nac_sat_ll_s1, // llvm.hexagon.M2.mpy.nac.sa
		t.ll.s1
		hexagon_M2_mpy_rnd_hh_s0, // llvm.hexagon.M2.mpy.rnd.hh
		.s0
		hexagon_M2_mpy_rnd_hh_s1, // llvm.hexagon.M2.mpy.rnd.hh
		.s1
		hexagon_M2_mpy_rnd_hl_s0, // llvm.hexagon.M2.mpy.rnd.hl
		.s0
		hexagon_M2_mpy_rnd_hl_s1, // llvm.hexagon.M2.mpy.rnd.hl
		.s1
		hexagon_M2_mpy_rnd_lh_s0, // llvm.hexagon.M2.mpy.rnd.lh
		.s0
		hexagon_M2_mpy_rnd_lh_s1, // llvm.hexagon.M2.mpy.rnd.lh
		.s1
		hexagon_M2_mpy_rnd_ll_s0, // llvm.hexagon.M2.mpy.rnd.ll
		.s0
		hexagon_M2_mpy_rnd_ll_s1, // llvm.hexagon.M2.mpy.rnd.ll
		.s1
		hexagon_M2_mpy_sat_hh_s0, // llvm.hexagon.M2.mpy.sat.hh
		.s0
		hexagon_M2_mpy_sat_hh_s1, // llvm.hexagon.M2.mpy.sat.hh
		.s1
		hexagon_M2_mpy_sat_hl_s0, // llvm.hexagon.M2.mpy.sat.hl
		.s0
		hexagon_M2_mpy_sat_hl_s1, // llvm.hexagon.M2.mpy.sat.hl
		.s1
		hexagon_M2_mpy_sat_lh_s0, // llvm.hexagon.M2.mpy.sat.lh
		.s0
		hexagon_M2_mpy_sat_lh_s1, // llvm.hexagon.M2.mpy.sat.lh
		.s1
		hexagon_M2_mpy_sat_ll_s0, // llvm.hexagon.M2.mpy.sat.ll
		.s0
		hexagon_M2_mpy_sat_ll_s1, // llvm.hexagon.M2.mpy.sat.ll
		.s1
		hexagon_M2_mpy_sat_rnd_hh_s0, // llvm.hexagon.M2.mpy.sat.rn
		d.hh.s0
		hexagon_M2_mpy_sat_rnd_hh_s1, // llvm.hexagon.M2.mpy.sat.rn
		d.hh.s1
		hexagon_M2_mpy_sat_rnd_hl_s0, // llvm.hexagon.M2.mpy.sat.rn
		d.hl.s0
		hexagon_M2_mpy_sat_rnd_hl_s1, // llvm.hexagon.M2.mpy.sat.rn
		d.hl.s1
		hexagon_M2_mpy_sat_rnd_lh_s0, // llvm.hexagon.M2.mpy.sat.rn
		d.lh.s0
		hexagon_M2_mpy_sat_rnd_lh_s1, // llvm.hexagon.M2.mpy.sat.rn
		d.lh.s1
		hexagon_M2_mpy_sat_rnd_ll_s0, // llvm.hexagon.M2.mpy.sat.rn
		d.ll.s0
		hexagon_M2_mpy_sat_rnd_ll_s1, // llvm.hexagon.M2.mpy.sat.rn
		d.ll.s1
		hexagon_M2_mpy_up, // llvm.hexagon.M2.mpy.up
		hexagon_M2_mpyd_acc_hh_s0, // llvm.hexagon.M2.mpyd.acc.h
		h.s0
		hexagon_M2_mpyd_acc_hh_s1, // llvm.hexagon.M2.mpyd.acc.h
		h.s1
		hexagon_M2_mpyd_acc_hl_s0, // llvm.hexagon.M2.mpyd.acc.h
		l.s0
		hexagon_M2_mpyd_acc_hl_s1, // llvm.hexagon.M2.mpyd.acc.h
		l.s1
		hexagon_M2_mpyd_acc_lh_s0, // llvm.hexagon.M2.mpyd.acc.l
		h.s0
		hexagon_M2_mpyd_acc_lh_s1, // llvm.hexagon.M2.mpyd.acc.l
		h.s1
		hexagon_M2_mpyd_acc_ll_s0, // llvm.hexagon.M2.mpyd.acc.l
		l.s0
		hexagon_M2_mpyd_acc_ll_s1, // llvm.hexagon.M2.mpyd.acc.l
		l.s1
		hexagon_M2_mpyd_hh_s0, // llvm.hexagon.M2.mpyd.hh.s0
		hexagon_M2_mpyd_hh_s1, // llvm.hexagon.M2.mpyd.hh.s1
		hexagon_M2_mpyd_hl_s0, // llvm.hexagon.M2.mpyd.hl.s0
		hexagon_M2_mpyd_hl_s1, // llvm.hexagon.M2.mpyd.hl.s1
		hexagon_M2_mpyd_lh_s0, // llvm.hexagon.M2.mpyd.lh.s0
		hexagon_M2_mpyd_lh_s1, // llvm.hexagon.M2.mpyd.lh.s1
		hexagon_M2_mpyd_ll_s0, // llvm.hexagon.M2.mpyd.ll.s0
		hexagon_M2_mpyd_ll_s1, // llvm.hexagon.M2.mpyd.ll.s1
		hexagon_M2_mpyd_nac_hh_s0, // llvm.hexagon.M2.mpyd.nac.h
		h.s0
		hexagon_M2_mpyd_nac_hh_s1, // llvm.hexagon.M2.mpyd.nac.h
		h.s1
		hexagon_M2_mpyd_nac_hl_s0, // llvm.hexagon.M2.mpyd.nac.h
		l.s0
		hexagon_M2_mpyd_nac_hl_s1, // llvm.hexagon.M2.mpyd.nac.h
		l.s1
		hexagon_M2_mpyd_nac_lh_s0, // llvm.hexagon.M2.mpyd.nac.l
		h.s0
		hexagon_M2_mpyd_nac_lh_s1, // llvm.hexagon.M2.mpyd.nac.l
		h.s1
		hexagon_M2_mpyd_nac_ll_s0, // llvm.hexagon.M2.mpyd.nac.l
		l.s0
		hexagon_M2_mpyd_nac_ll_s1, // llvm.hexagon.M2.mpyd.nac.l
		l.s1
		hexagon_M2_mpyd_rnd_hh_s0, // llvm.hexagon.M2.mpyd.rnd.h
		h.s0
		hexagon_M2_mpyd_rnd_hh_s1, // llvm.hexagon.M2.mpyd.rnd.h
		h.s1
		hexagon_M2_mpyd_rnd_hl_s0, // llvm.hexagon.M2.mpyd.rnd.h
		l.s0
		hexagon_M2_mpyd_rnd_hl_s1, // llvm.hexagon.M2.mpyd.rnd.h
		l.s1
		hexagon_M2_mpyd_rnd_lh_s0, // llvm.hexagon.M2.mpyd.rnd.l
		h.s0
		hexagon_M2_mpyd_rnd_lh_s1, // llvm.hexagon.M2.mpyd.rnd.l
		h.s1
		hexagon_M2_mpyd_rnd_ll_s0, // llvm.hexagon.M2.mpyd.rnd.l
		l.s0
		hexagon_M2_mpyd_rnd_ll_s1, // llvm.hexagon.M2.mpyd.rnd.l
		l.s1
		hexagon_M2_mpyi, // llvm.hexagon.M2.mpyi
		hexagon_M2_mpysmi, // llvm.hexagon.M2.mpysmi
		hexagon_M2_mpyu_acc_hh_s0, // llvm.hexagon.M2.mpyu.acc.h
		h.s0
		hexagon_M2_mpyu_acc_hh_s1, // llvm.hexagon.M2.mpyu.acc.h
		h.s1
		hexagon_M2_mpyu_acc_hl_s0, // llvm.hexagon.M2.mpyu.acc.h
		l.s0
		hexagon_M2_mpyu_acc_hl_s1, // llvm.hexagon.M2.mpyu.acc.h
		l.s1
		hexagon_M2_mpyu_acc_lh_s0, // llvm.hexagon.M2.mpyu.acc.l
		h.s0
		hexagon_M2_mpyu_acc_lh_s1, // llvm.hexagon.M2.mpyu.acc.l
		h.s1
		hexagon_M2_mpyu_acc_ll_s0, // llvm.hexagon.M2.mpyu.acc.l
		l.s0
		hexagon_M2_mpyu_acc_ll_s1, // llvm.hexagon.M2.mpyu.acc.l
		l.s1
		hexagon_M2_mpyu_hh_s0, // llvm.hexagon.M2.mpyu.hh.s0
		hexagon_M2_mpyu_hh_s1, // llvm.hexagon.M2.mpyu.hh.s1
		hexagon_M2_mpyu_hl_s0, // llvm.hexagon.M2.mpyu.hl.s0
		hexagon_M2_mpyu_hl_s1, // llvm.hexagon.M2.mpyu.hl.s1
		hexagon_M2_mpyu_lh_s0, // llvm.hexagon.M2.mpyu.lh.s0
		hexagon_M2_mpyu_lh_s1, // llvm.hexagon.M2.mpyu.lh.s1
		hexagon_M2_mpyu_ll_s0, // llvm.hexagon.M2.mpyu.ll.s0
		hexagon_M2_mpyu_ll_s1, // llvm.hexagon.M2.mpyu.ll.s1
		hexagon_M2_mpyu_nac_hh_s0, // llvm.hexagon.M2.mpyu.nac.h
		h.s0
		hexagon_M2_mpyu_nac_hh_s1, // llvm.hexagon.M2.mpyu.nac.h
		h.s1
		hexagon_M2_mpyu_nac_hl_s0, // llvm.hexagon.M2.mpyu.nac.h
		l.s0
		hexagon_M2_mpyu_nac_hl_s1, // llvm.hexagon.M2.mpyu.nac.h
		l.s1
		hexagon_M2_mpyu_nac_lh_s0, // llvm.hexagon.M2.mpyu.nac.l
		h.s0
		hexagon_M2_mpyu_nac_lh_s1, // llvm.hexagon.M2.mpyu.nac.l
		h.s1
		hexagon_M2_mpyu_nac_ll_s0, // llvm.hexagon.M2.mpyu.nac.l
		l.s0
		hexagon_M2_mpyu_nac_ll_s1, // llvm.hexagon.M2.mpyu.nac.l
		l.s1
		hexagon_M2_mpyu_up, // llvm.hexagon.M2.mpyu.up
		hexagon_M2_mpyud_acc_hh_s0, // llvm.hexagon.M2.mpyud.acc.
		hh.s0
		hexagon_M2_mpyud_acc_hh_s1, // llvm.hexagon.M2.mpyud.acc.
		hh.s1
		hexagon_M2_mpyud_acc_hl_s0, // llvm.hexagon.M2.mpyud.acc.
		hl.s0
		hexagon_M2_mpyud_acc_hl_s1, // llvm.hexagon.M2.mpyud.acc.
		hl.s1
		hexagon_M2_mpyud_acc_lh_s0, // llvm.hexagon.M2.mpyud.acc.
		lh.s0
		hexagon_M2_mpyud_acc_lh_s1, // llvm.hexagon.M2.mpyud.acc.
		lh.s1
		hexagon_M2_mpyud_acc_ll_s0, // llvm.hexagon.M2.mpyud.acc.
		ll.s0
		hexagon_M2_mpyud_acc_ll_s1, // llvm.hexagon.M2.mpyud.acc.
		ll.s1
		hexagon_M2_mpyud_hh_s0, // llvm.hexagon.M2.mpyud.hh.s
		0
		hexagon_M2_mpyud_hh_s1, // llvm.hexagon.M2.mpyud.hh.s
		1
		hexagon_M2_mpyud_hl_s0, // llvm.hexagon.M2.mpyud.hl.s
		0
		hexagon_M2_mpyud_hl_s1, // llvm.hexagon.M2.mpyud.hl.s
		1
		hexagon_M2_mpyud_lh_s0, // llvm.hexagon.M2.mpyud.lh.s
		0
		hexagon_M2_mpyud_lh_s1, // llvm.hexagon.M2.mpyud.lh.s
		1
		hexagon_M2_mpyud_ll_s0, // llvm.hexagon.M2.mpyud.ll.s
		0
		hexagon_M2_mpyud_ll_s1, // llvm.hexagon.M2.mpyud.ll.s
		1
		hexagon_M2_mpyud_nac_hh_s0, // llvm.hexagon.M2.mpyud.nac.
		hh.s0
		hexagon_M2_mpyud_nac_hh_s1, // llvm.hexagon.M2.mpyud.nac.
		hh.s1
		hexagon_M2_mpyud_nac_hl_s0, // llvm.hexagon.M2.mpyud.nac.
		hl.s0
		hexagon_M2_mpyud_nac_hl_s1, // llvm.hexagon.M2.mpyud.nac.
		hl.s1
		hexagon_M2_mpyud_nac_lh_s0, // llvm.hexagon.M2.mpyud.nac.
		lh.s0
		hexagon_M2_mpyud_nac_lh_s1, // llvm.hexagon.M2.mpyud.nac.
		lh.s1
		hexagon_M2_mpyud_nac_ll_s0, // llvm.hexagon.M2.mpyud.nac.
		ll.s0
		hexagon_M2_mpyud_nac_ll_s1, // llvm.hexagon.M2.mpyud.nac.
		ll.s1
		hexagon_M2_mpyui, // llvm.hexagon.M2.mpyui
		hexagon_M2_nacci, // llvm.hexagon.M2.nacci
		hexagon_M2_naccii, // llvm.hexagon.M2.naccii
		hexagon_M2_subacc, // llvm.hexagon.M2.subacc
		hexagon_M2_vabsdiffh, // llvm.hexagon.M2.vabsdiffh
		hexagon_M2_vabsdiffw, // llvm.hexagon.M2.vabsdiffw
		hexagon_M2_vcmac_s0_sat_i, // llvm.hexagon.M2.vcmac.s0.s
		at.i
		hexagon_M2_vcmac_s0_sat_r, // llvm.hexagon.M2.vcmac.s0.s
		at.r
		hexagon_M2_vcmpy_s0_sat_i, // llvm.hexagon.M2.vcmpy.s0.s
		at.i
		hexagon_M2_vcmpy_s0_sat_r, // llvm.hexagon.M2.vcmpy.s0.s
		at.r
		hexagon_M2_vcmpy_s1_sat_i, // llvm.hexagon.M2.vcmpy.s1.s
		at.i
		hexagon_M2_vcmpy_s1_sat_r, // llvm.hexagon.M2.vcmpy.s1.s
		at.r
		hexagon_M2_vdmacs_s0, // llvm.hexagon.M2.vdmacs.s0
		hexagon_M2_vdmacs_s1, // llvm.hexagon.M2.vdmacs.s1
		hexagon_M2_vdmpyrs_s0, // llvm.hexagon.M2.vdmpyrs.s0
		hexagon_M2_vdmpyrs_s1, // llvm.hexagon.M2.vdmpyrs.s1
		hexagon_M2_vdmpys_s0, // llvm.hexagon.M2.vdmpys.s0
		hexagon_M2_vdmpys_s1, // llvm.hexagon.M2.vdmpys.s1
		hexagon_M2_vmac2, // llvm.hexagon.M2.vmac2
		hexagon_M2_vmac2es, // llvm.hexagon.M2.vmac2es
		hexagon_M2_vmac2es_s0, // llvm.hexagon.M2.vmac2es.s0
		hexagon_M2_vmac2es_s1, // llvm.hexagon.M2.vmac2es.s1
		hexagon_M2_vmac2s_s0, // llvm.hexagon.M2.vmac2s.s0
		hexagon_M2_vmac2s_s1, // llvm.hexagon.M2.vmac2s.s1
		hexagon_M2_vmpy2es_s0, // llvm.hexagon.M2.vmpy2es.s0
		hexagon_M2_vmpy2es_s1, // llvm.hexagon.M2.vmpy2es.s1
		hexagon_M2_vmpy2s_s0, // llvm.hexagon.M2.vmpy2s.s0
		hexagon_M2_vmpy2s_s0pack, // llvm.hexagon.M2.vmpy2s.s0p
		ack
		hexagon_M2_vmpy2s_s1, // llvm.hexagon.M2.vmpy2s.s1
		hexagon_M2_vmpy2s_s1pack, // llvm.hexagon.M2.vmpy2s.s1p
		ack
		hexagon_M2_vradduh, // llvm.hexagon.M2.vradduh
		hexagon_M2_vrcmaci_s0, // llvm.hexagon.M2.vrcmaci.s0
		hexagon_M2_vrcmaci_s0c, // llvm.hexagon.M2.vrcmaci.s0
		c
		hexagon_M2_vrcmacr_s0, // llvm.hexagon.M2.vrcmacr.s0
		hexagon_M2_vrcmacr_s0c, // llvm.hexagon.M2.vrcmacr.s0
		c
		hexagon_M2_vrcmpyi_s0, // llvm.hexagon.M2.vrcmpyi.s0
		hexagon_M2_vrcmpyi_s0c, // llvm.hexagon.M2.vrcmpyi.s0
		c
		hexagon_M2_vrcmpyr_s0, // llvm.hexagon.M2.vrcmpyr.s0
		hexagon_M2_vrcmpyr_s0c, // llvm.hexagon.M2.vrcmpyr.s0
		c
		hexagon_M2_vrcmpys_acc_s1, // llvm.hexagon.M2.vrcmpys.ac
		c.s1
		hexagon_M2_vrcmpys_s1, // llvm.hexagon.M2.vrcmpys.s1
		hexagon_M2_vrcmpys_s1rp, // llvm.hexagon.M2.vrcmpys.s1
		rp
		hexagon_M2_vrmac_s0, // llvm.hexagon.M2.vrmac.s0
		hexagon_M2_vrmpy_s0, // llvm.hexagon.M2.vrmpy.s0
		hexagon_M2_xor_xacc, // llvm.hexagon.M2.xor.xacc
		hexagon_M4_and_and, // llvm.hexagon.M4.and.and
		hexagon_M4_and_andn, // llvm.hexagon.M4.and.andn
		hexagon_M4_and_or, // llvm.hexagon.M4.and.or
		hexagon_M4_and_xor, // llvm.hexagon.M4.and.xor
		hexagon_M4_or_and, // llvm.hexagon.M4.or.and
		hexagon_M4_or_andn, // llvm.hexagon.M4.or.andn
		hexagon_M4_or_or, // llvm.hexagon.M4.or.or
		hexagon_M4_or_xor, // llvm.hexagon.M4.or.xor
		hexagon_M4_xor_and, // llvm.hexagon.M4.xor.and
		hexagon_M4_xor_andn, // llvm.hexagon.M4.xor.andn
		hexagon_M4_xor_or, // llvm.hexagon.M4.xor.or
		hexagon_M4_xor_xacc, // llvm.hexagon.M4.xor.xacc
		hexagon_S2_addasl_rrri, // llvm.hexagon.S2.addasl.rrr
		i
		hexagon_S2_asl_i_p, // llvm.hexagon.S2.asl.i.p
		hexagon_S2_asl_i_p_acc, // llvm.hexagon.S2.asl.i.p.ac
		c
		hexagon_S2_asl_i_p_and, // llvm.hexagon.S2.asl.i.p.an
		d
		hexagon_S2_asl_i_p_nac, // llvm.hexagon.S2.asl.i.p.na
		c
		hexagon_S2_asl_i_p_or, // llvm.hexagon.S2.asl.i.p.or
		hexagon_S2_asl_i_p_xacc, // llvm.hexagon.S2.asl.i.p.xa
		cc
		hexagon_S2_asl_i_r, // llvm.hexagon.S2.asl.i.r
		hexagon_S2_asl_i_r_acc, // llvm.hexagon.S2.asl.i.r.ac
		c
		hexagon_S2_asl_i_r_and, // llvm.hexagon.S2.asl.i.r.an
		d
		hexagon_S2_asl_i_r_nac, // llvm.hexagon.S2.asl.i.r.na
		c
		hexagon_S2_asl_i_r_or, // llvm.hexagon.S2.asl.i.r.or
		hexagon_S2_asl_i_r_sat, // llvm.hexagon.S2.asl.i.r.sa
		t
		hexagon_S2_asl_i_r_xacc, // llvm.hexagon.S2.asl.i.r.xa
		cc
		hexagon_S2_asl_i_vh, // llvm.hexagon.S2.asl.i.vh
		hexagon_S2_asl_i_vw, // llvm.hexagon.S2.asl.i.vw
		hexagon_S2_asl_r_p, // llvm.hexagon.S2.asl.r.p
		hexagon_S2_asl_r_p_acc, // llvm.hexagon.S2.asl.r.p.ac
		c
		hexagon_S2_asl_r_p_and, // llvm.hexagon.S2.asl.r.p.an
		d
		hexagon_S2_asl_r_p_nac, // llvm.hexagon.S2.asl.r.p.na
		c
		hexagon_S2_asl_r_p_or, // llvm.hexagon.S2.asl.r.p.or
		hexagon_S2_asl_r_r, // llvm.hexagon.S2.asl.r.r
		hexagon_S2_asl_r_r_acc, // llvm.hexagon.S2.asl.r.r.ac
		c
		hexagon_S2_asl_r_r_and, // llvm.hexagon.S2.asl.r.r.an
		d
		hexagon_S2_asl_r_r_nac, // llvm.hexagon.S2.asl.r.r.na
		c
		hexagon_S2_asl_r_r_or, // llvm.hexagon.S2.asl.r.r.or
		hexagon_S2_asl_r_r_sat, // llvm.hexagon.S2.asl.r.r.sa
		t
		hexagon_S2_asl_r_vh, // llvm.hexagon.S2.asl.r.vh
		hexagon_S2_asl_r_vw, // llvm.hexagon.S2.asl.r.vw
		hexagon_S2_asr_i_p, // llvm.hexagon.S2.asr.i.p
		hexagon_S2_asr_i_p_acc, // llvm.hexagon.S2.asr.i.p.ac
		c
		hexagon_S2_asr_i_p_and, // llvm.hexagon.S2.asr.i.p.an
		d
		hexagon_S2_asr_i_p_nac, // llvm.hexagon.S2.asr.i.p.na
		c
		hexagon_S2_asr_i_p_or, // llvm.hexagon.S2.asr.i.p.or
		hexagon_S2_asr_i_r, // llvm.hexagon.S2.asr.i.r
		hexagon_S2_asr_i_r_acc, // llvm.hexagon.S2.asr.i.r.ac
		c
		hexagon_S2_asr_i_r_and, // llvm.hexagon.S2.asr.i.r.an
		d
		hexagon_S2_asr_i_r_nac, // llvm.hexagon.S2.asr.i.r.na
		c
		hexagon_S2_asr_i_r_or, // llvm.hexagon.S2.asr.i.r.or
		hexagon_S2_asr_i_r_rnd, // llvm.hexagon.S2.asr.i.r.rn
		d
		hexagon_S2_asr_i_r_rnd_goodsyntax, // llvm.hexagon.S2.asr.i.r.rn
		d.goodsyntax
		hexagon_S2_asr_i_svw_trun, // llvm.hexagon.S2.asr.i.svw.
		trun
		hexagon_S2_asr_i_vh, // llvm.hexagon.S2.asr.i.vh
		hexagon_S2_asr_i_vw, // llvm.hexagon.S2.asr.i.vw
		hexagon_S2_asr_r_p, // llvm.hexagon.S2.asr.r.p
		hexagon_S2_asr_r_p_acc, // llvm.hexagon.S2.asr.r.p.ac
		c
		hexagon_S2_asr_r_p_and, // llvm.hexagon.S2.asr.r.p.an
		d
		hexagon_S2_asr_r_p_nac, // llvm.hexagon.S2.asr.r.p.na
		c
		hexagon_S2_asr_r_p_or, // llvm.hexagon.S2.asr.r.p.or
		hexagon_S2_asr_r_r, // llvm.hexagon.S2.asr.r.r
		hexagon_S2_asr_r_r_acc, // llvm.hexagon.S2.asr.r.r.ac
		c
		hexagon_S2_asr_r_r_and, // llvm.hexagon.S2.asr.r.r.an
		d
		hexagon_S2_asr_r_r_nac, // llvm.hexagon.S2.asr.r.r.na
		c
		hexagon_S2_asr_r_r_or, // llvm.hexagon.S2.asr.r.r.or
		hexagon_S2_asr_r_r_sat, // llvm.hexagon.S2.asr.r.r.sa
		t
		hexagon_S2_asr_r_svw_trun, // llvm.hexagon.S2.asr.r.svw.
		trun
		hexagon_S2_asr_r_vh, // llvm.hexagon.S2.asr.r.vh
		hexagon_S2_asr_r_vw, // llvm.hexagon.S2.asr.r.vw
		hexagon_S2_brev, // llvm.hexagon.S2.brev
		hexagon_S2_cl0, // llvm.hexagon.S2.cl0
		hexagon_S2_cl0p, // llvm.hexagon.S2.cl0p
		hexagon_S2_cl1, // llvm.hexagon.S2.cl1
		hexagon_S2_cl1p, // llvm.hexagon.S2.cl1p
		hexagon_S2_clb, // llvm.hexagon.S2.clb
		hexagon_S2_clbnorm, // llvm.hexagon.S2.clbnorm
		hexagon_S2_clbp, // llvm.hexagon.S2.clbp
		hexagon_S2_clrbit_i, // llvm.hexagon.S2.clrbit.i
		hexagon_S2_clrbit_r, // llvm.hexagon.S2.clrbit.r
		hexagon_S2_ct0, // llvm.hexagon.S2.ct0
		hexagon_S2_ct1, // llvm.hexagon.S2.ct1
		hexagon_S2_deinterleave, // llvm.hexagon.S2.deinterlea
		ve
		hexagon_S2_extractu, // llvm.hexagon.S2.extractu
		hexagon_S2_extractu_rp, // llvm.hexagon.S2.extractu.r
		p
		hexagon_S2_extractup, // llvm.hexagon.S2.extractup
		hexagon_S2_extractup_rp, // llvm.hexagon.S2.extractup.
		rp
		hexagon_S2_insert, // llvm.hexagon.S2.insert
		hexagon_S2_insert_rp, // llvm.hexagon.S2.insert.rp
		hexagon_S2_insertp, // llvm.hexagon.S2.insertp
		hexagon_S2_insertp_rp, // llvm.hexagon.S2.insertp.rp
		hexagon_S2_interleave, // llvm.hexagon.S2.interleave
		hexagon_S2_lfsp, // llvm.hexagon.S2.lfsp
		hexagon_S2_lsl_r_p, // llvm.hexagon.S2.lsl.r.p
		hexagon_S2_lsl_r_p_acc, // llvm.hexagon.S2.lsl.r.p.ac
		c
		hexagon_S2_lsl_r_p_and, // llvm.hexagon.S2.lsl.r.p.an
		d
		hexagon_S2_lsl_r_p_nac, // llvm.hexagon.S2.lsl.r.p.na
		c
		hexagon_S2_lsl_r_p_or, // llvm.hexagon.S2.lsl.r.p.or
		hexagon_S2_lsl_r_r, // llvm.hexagon.S2.lsl.r.r
		hexagon_S2_lsl_r_r_acc, // llvm.hexagon.S2.lsl.r.r.ac
		c
		hexagon_S2_lsl_r_r_and, // llvm.hexagon.S2.lsl.r.r.an
		d
		hexagon_S2_lsl_r_r_nac, // llvm.hexagon.S2.lsl.r.r.na
		c
		hexagon_S2_lsl_r_r_or, // llvm.hexagon.S2.lsl.r.r.or
		hexagon_S2_lsl_r_vh, // llvm.hexagon.S2.lsl.r.vh
		hexagon_S2_lsl_r_vw, // llvm.hexagon.S2.lsl.r.vw
		hexagon_S2_lsr_i_p, // llvm.hexagon.S2.lsr.i.p
		hexagon_S2_lsr_i_p_acc, // llvm.hexagon.S2.lsr.i.p.ac
		c
		hexagon_S2_lsr_i_p_and, // llvm.hexagon.S2.lsr.i.p.an
		d
		hexagon_S2_lsr_i_p_nac, // llvm.hexagon.S2.lsr.i.p.na
		c
		hexagon_S2_lsr_i_p_or, // llvm.hexagon.S2.lsr.i.p.or
		hexagon_S2_lsr_i_p_xacc, // llvm.hexagon.S2.lsr.i.p.xa
		cc
		hexagon_S2_lsr_i_r, // llvm.hexagon.S2.lsr.i.r
		hexagon_S2_lsr_i_r_acc, // llvm.hexagon.S2.lsr.i.r.ac
		c
		hexagon_S2_lsr_i_r_and, // llvm.hexagon.S2.lsr.i.r.an
		d
		hexagon_S2_lsr_i_r_nac, // llvm.hexagon.S2.lsr.i.r.na
		c
		hexagon_S2_lsr_i_r_or, // llvm.hexagon.S2.lsr.i.r.or
		hexagon_S2_lsr_i_r_xacc, // llvm.hexagon.S2.lsr.i.r.xa
		cc
		hexagon_S2_lsr_i_vh, // llvm.hexagon.S2.lsr.i.vh
		hexagon_S2_lsr_i_vw, // llvm.hexagon.S2.lsr.i.vw
		hexagon_S2_lsr_r_p, // llvm.hexagon.S2.lsr.r.p
		hexagon_S2_lsr_r_p_acc, // llvm.hexagon.S2.lsr.r.p.ac
		c
		hexagon_S2_lsr_r_p_and, // llvm.hexagon.S2.lsr.r.p.an
		d
		hexagon_S2_lsr_r_p_nac, // llvm.hexagon.S2.lsr.r.p.na
		c
		hexagon_S2_lsr_r_p_or, // llvm.hexagon.S2.lsr.r.p.or
		hexagon_S2_lsr_r_r, // llvm.hexagon.S2.lsr.r.r
		hexagon_S2_lsr_r_r_acc, // llvm.hexagon.S2.lsr.r.r.ac
		c
		hexagon_S2_lsr_r_r_and, // llvm.hexagon.S2.lsr.r.r.an
		d
		hexagon_S2_lsr_r_r_nac, // llvm.hexagon.S2.lsr.r.r.na
		c
		hexagon_S2_lsr_r_r_or, // llvm.hexagon.S2.lsr.r.r.or
		hexagon_S2_lsr_r_vh, // llvm.hexagon.S2.lsr.r.vh
		hexagon_S2_lsr_r_vw, // llvm.hexagon.S2.lsr.r.vw
		hexagon_S2_packhl, // llvm.hexagon.S2.packhl
		hexagon_S2_parityp, // llvm.hexagon.S2.parityp
		hexagon_S2_setbit_i, // llvm.hexagon.S2.setbit.i
		hexagon_S2_setbit_r, // llvm.hexagon.S2.setbit.r
		hexagon_S2_shuffeb, // llvm.hexagon.S2.shuffeb
		hexagon_S2_shuffeh, // llvm.hexagon.S2.shuffeh
		hexagon_S2_shuffob, // llvm.hexagon.S2.shuffob
		hexagon_S2_shuffoh, // llvm.hexagon.S2.shuffoh
		hexagon_S2_svsathb, // llvm.hexagon.S2.svsathb
		hexagon_S2_svsathub, // llvm.hexagon.S2.svsathub
		hexagon_S2_tableidxb_goodsyntax, // llvm.hexagon.S2.tableidxb.
		goodsyntax
		hexagon_S2_tableidxd_goodsyntax, // llvm.hexagon.S2.tableidxd.
		goodsyntax
		hexagon_S2_tableidxh_goodsyntax, // llvm.hexagon.S2.tableidxh.
		goodsyntax
		hexagon_S2_tableidxw_goodsyntax, // llvm.hexagon.S2.tableidxw.
		goodsyntax
		hexagon_S2_togglebit_i, // llvm.hexagon.S2.togglebit.
		i
		hexagon_S2_togglebit_r, // llvm.hexagon.S2.togglebit.
		r
		hexagon_S2_tstbit_i, // llvm.hexagon.S2.tstbit.i
		hexagon_S2_tstbit_r, // llvm.hexagon.S2.tstbit.r
		hexagon_S2_valignib, // llvm.hexagon.S2.valignib
		hexagon_S2_valignrb, // llvm.hexagon.S2.valignrb
		hexagon_S2_vcrotate, // llvm.hexagon.S2.vcrotate
		hexagon_S2_vrndpackwh, // llvm.hexagon.S2.vrndpackwh
		hexagon_S2_vrndpackwhs, // llvm.hexagon.S2.vrndpackwh
		s
		hexagon_S2_vsathb, // llvm.hexagon.S2.vsathb
		hexagon_S2_vsathb_nopack, // llvm.hexagon.S2.vsathb.nop
		ack
		hexagon_S2_vsathub, // llvm.hexagon.S2.vsathub
		hexagon_S2_vsathub_nopack, // llvm.hexagon.S2.vsathub.no
		pack
		hexagon_S2_vsatwh, // llvm.hexagon.S2.vsatwh
		hexagon_S2_vsatwh_nopack, // llvm.hexagon.S2.vsatwh.nop
		ack
		hexagon_S2_vsatwuh, // llvm.hexagon.S2.vsatwuh
		hexagon_S2_vsatwuh_nopack, // llvm.hexagon.S2.vsatwuh.no
		pack
		hexagon_S2_vsplatrb, // llvm.hexagon.S2.vsplatrb
		hexagon_S2_vsplatrh, // llvm.hexagon.S2.vsplatrh
		hexagon_S2_vspliceib, // llvm.hexagon.S2.vspliceib
		hexagon_S2_vsplicerb, // llvm.hexagon.S2.vsplicerb
		hexagon_S2_vsxtbh, // llvm.hexagon.S2.vsxtbh
		hexagon_S2_vsxthw, // llvm.hexagon.S2.vsxthw
		hexagon_S2_vtrunehb, // llvm.hexagon.S2.vtrunehb
		hexagon_S2_vtrunewh, // llvm.hexagon.S2.vtrunewh
		hexagon_S2_vtrunohb, // llvm.hexagon.S2.vtrunohb
		hexagon_S2_vtrunowh, // llvm.hexagon.S2.vtrunowh
		hexagon_S2_vzxtbh, // llvm.hexagon.S2.vzxtbh
		hexagon_S2_vzxthw, // llvm.hexagon.S2.vzxthw
		hexagon_S4_addaddi, // llvm.hexagon.S4.addaddi
		hexagon_S4_andnp, // llvm.hexagon.S4.andnp
		hexagon_S4_or_andi, // llvm.hexagon.S4.or.andi
		hexagon_S4_or_andix, // llvm.hexagon.S4.or.andix
		hexagon_S4_or_ori, // llvm.hexagon.S4.or.ori
		hexagon_S4_ornp, // llvm.hexagon.S4.ornp
		hexagon_S4_subaddi, // llvm.hexagon.S4.subaddi
		hexagon_SI_to_SXTHI_asrh, // llvm.hexagon.SI.to.SXTHI.a
		srh
	init_trampoline, // llvm.init.trampoline	init_trampoline, // llvm.init.trampoline
	invariant_end, // llvm.invariant.end	invariant_end, // llvm.invariant.end
	invariant_start, // llvm.invariant.start	invariant_start, // llvm.invariant.start
	lifetime_end, // llvm.lifetime.end	lifetime_end, // llvm.lifetime.end
	lifetime_start, // llvm.lifetime.start	lifetime_start, // llvm.lifetime.start
	log, // llvm.log	log, // llvm.log
	log10, // llvm.log10	log10, // llvm.log10
	log2, // llvm.log2	log2, // llvm.log2
	longjmp, // llvm.longjmp	longjmp, // llvm.longjmp
	memcpy, // llvm.memcpy	memcpy, // llvm.memcpy

	skipping to change at line 526	skipping to change at line 1184
	x86_3dnowa_pfnacc, // llvm.x86.3dnowa.pfnacc	x86_3dnowa_pfnacc, // llvm.x86.3dnowa.pfnacc
	x86_3dnowa_pfpnacc, // llvm.x86.3dnowa.pfpnacc	x86_3dnowa_pfpnacc, // llvm.x86.3dnowa.pfpnacc
	x86_3dnowa_pi2fw, // llvm.x86.3dnowa.pi2fw	x86_3dnowa_pi2fw, // llvm.x86.3dnowa.pi2fw
	x86_3dnowa_pswapd, // llvm.x86.3dnowa.pswapd	x86_3dnowa_pswapd, // llvm.x86.3dnowa.pswapd
	x86_aesni_aesdec, // llvm.x86.aesni.aesdec	x86_aesni_aesdec, // llvm.x86.aesni.aesdec
	x86_aesni_aesdeclast, // llvm.x86.aesni.aesdeclast	x86_aesni_aesdeclast, // llvm.x86.aesni.aesdeclast
	x86_aesni_aesenc, // llvm.x86.aesni.aesenc	x86_aesni_aesenc, // llvm.x86.aesni.aesenc
	x86_aesni_aesenclast, // llvm.x86.aesni.aesenclast	x86_aesni_aesenclast, // llvm.x86.aesni.aesenclast
	x86_aesni_aesimc, // llvm.x86.aesni.aesimc	x86_aesni_aesimc, // llvm.x86.aesni.aesimc
	x86_aesni_aeskeygenassist, // llvm.x86.aesni.aeskeygenas sist	x86_aesni_aeskeygenassist, // llvm.x86.aesni.aeskeygenas sist

		x86_avx2_maskload_d, // llvm.x86.avx2.maskload.d
		x86_avx2_maskload_d_256, // llvm.x86.avx2.maskload.d.2
		56
		x86_avx2_maskload_q, // llvm.x86.avx2.maskload.q
		x86_avx2_maskload_q_256, // llvm.x86.avx2.maskload.q.2
		56
		x86_avx2_maskstore_d, // llvm.x86.avx2.maskstore.d
		x86_avx2_maskstore_d_256, // llvm.x86.avx2.maskstore.d.
		256
		x86_avx2_maskstore_q, // llvm.x86.avx2.maskstore.q
		x86_avx2_maskstore_q_256, // llvm.x86.avx2.maskstore.q.
		256
		x86_avx2_movntdqa, // llvm.x86.avx2.movntdqa
		x86_avx2_mpsadbw, // llvm.x86.avx2.mpsadbw
		x86_avx2_pabs_b, // llvm.x86.avx2.pabs.b
		x86_avx2_pabs_d, // llvm.x86.avx2.pabs.d
		x86_avx2_pabs_w, // llvm.x86.avx2.pabs.w
		x86_avx2_packssdw, // llvm.x86.avx2.packssdw
		x86_avx2_packsswb, // llvm.x86.avx2.packsswb
		x86_avx2_packusdw, // llvm.x86.avx2.packusdw
		x86_avx2_packuswb, // llvm.x86.avx2.packuswb
		x86_avx2_padds_b, // llvm.x86.avx2.padds.b
		x86_avx2_padds_w, // llvm.x86.avx2.padds.w
		x86_avx2_paddus_b, // llvm.x86.avx2.paddus.b
		x86_avx2_paddus_w, // llvm.x86.avx2.paddus.w
		x86_avx2_pavg_b, // llvm.x86.avx2.pavg.b
		x86_avx2_pavg_w, // llvm.x86.avx2.pavg.w
		x86_avx2_pblendd_128, // llvm.x86.avx2.pblendd.128
		x86_avx2_pblendd_256, // llvm.x86.avx2.pblendd.256
		x86_avx2_pblendvb, // llvm.x86.avx2.pblendvb
		x86_avx2_pblendw, // llvm.x86.avx2.pblendw
		x86_avx2_pbroadcastb_128, // llvm.x86.avx2.pbroadcastb.
		128
		x86_avx2_pbroadcastb_256, // llvm.x86.avx2.pbroadcastb.
		256
		x86_avx2_pbroadcastd_128, // llvm.x86.avx2.pbroadcastd.
		128
		x86_avx2_pbroadcastd_256, // llvm.x86.avx2.pbroadcastd.
		256
		x86_avx2_pbroadcastq_128, // llvm.x86.avx2.pbroadcastq.
		128
		x86_avx2_pbroadcastq_256, // llvm.x86.avx2.pbroadcastq.
		256
		x86_avx2_pbroadcastw_128, // llvm.x86.avx2.pbroadcastw.
		128
		x86_avx2_pbroadcastw_256, // llvm.x86.avx2.pbroadcastw.
		256
		x86_avx2_permd, // llvm.x86.avx2.permd
		x86_avx2_permps, // llvm.x86.avx2.permps
		x86_avx2_phadd_d, // llvm.x86.avx2.phadd.d
		x86_avx2_phadd_sw, // llvm.x86.avx2.phadd.sw
		x86_avx2_phadd_w, // llvm.x86.avx2.phadd.w
		x86_avx2_phsub_d, // llvm.x86.avx2.phsub.d
		x86_avx2_phsub_sw, // llvm.x86.avx2.phsub.sw
		x86_avx2_phsub_w, // llvm.x86.avx2.phsub.w
		x86_avx2_pmadd_ub_sw, // llvm.x86.avx2.pmadd.ub.sw
		x86_avx2_pmadd_wd, // llvm.x86.avx2.pmadd.wd
		x86_avx2_pmaxs_b, // llvm.x86.avx2.pmaxs.b
		x86_avx2_pmaxs_d, // llvm.x86.avx2.pmaxs.d
		x86_avx2_pmaxs_w, // llvm.x86.avx2.pmaxs.w
		x86_avx2_pmaxu_b, // llvm.x86.avx2.pmaxu.b
		x86_avx2_pmaxu_d, // llvm.x86.avx2.pmaxu.d
		x86_avx2_pmaxu_w, // llvm.x86.avx2.pmaxu.w
		x86_avx2_pmins_b, // llvm.x86.avx2.pmins.b
		x86_avx2_pmins_d, // llvm.x86.avx2.pmins.d
		x86_avx2_pmins_w, // llvm.x86.avx2.pmins.w
		x86_avx2_pminu_b, // llvm.x86.avx2.pminu.b
		x86_avx2_pminu_d, // llvm.x86.avx2.pminu.d
		x86_avx2_pminu_w, // llvm.x86.avx2.pminu.w
		x86_avx2_pmovmskb, // llvm.x86.avx2.pmovmskb
		x86_avx2_pmovsxbd, // llvm.x86.avx2.pmovsxbd
		x86_avx2_pmovsxbq, // llvm.x86.avx2.pmovsxbq
		x86_avx2_pmovsxbw, // llvm.x86.avx2.pmovsxbw
		x86_avx2_pmovsxdq, // llvm.x86.avx2.pmovsxdq
		x86_avx2_pmovsxwd, // llvm.x86.avx2.pmovsxwd
		x86_avx2_pmovsxwq, // llvm.x86.avx2.pmovsxwq
		x86_avx2_pmovzxbd, // llvm.x86.avx2.pmovzxbd
		x86_avx2_pmovzxbq, // llvm.x86.avx2.pmovzxbq
		x86_avx2_pmovzxbw, // llvm.x86.avx2.pmovzxbw
		x86_avx2_pmovzxdq, // llvm.x86.avx2.pmovzxdq
		x86_avx2_pmovzxwd, // llvm.x86.avx2.pmovzxwd
		x86_avx2_pmovzxwq, // llvm.x86.avx2.pmovzxwq
		x86_avx2_pmul_dq, // llvm.x86.avx2.pmul.dq
		x86_avx2_pmul_hr_sw, // llvm.x86.avx2.pmul.hr.sw
		x86_avx2_pmulh_w, // llvm.x86.avx2.pmulh.w
		x86_avx2_pmulhu_w, // llvm.x86.avx2.pmulhu.w
		x86_avx2_pmulu_dq, // llvm.x86.avx2.pmulu.dq
		x86_avx2_psad_bw, // llvm.x86.avx2.psad.bw
		x86_avx2_pshuf_b, // llvm.x86.avx2.pshuf.b
		x86_avx2_psign_b, // llvm.x86.avx2.psign.b
		x86_avx2_psign_d, // llvm.x86.avx2.psign.d
		x86_avx2_psign_w, // llvm.x86.avx2.psign.w
		x86_avx2_psll_d, // llvm.x86.avx2.psll.d
		x86_avx2_psll_dq, // llvm.x86.avx2.psll.dq
		x86_avx2_psll_dq_bs, // llvm.x86.avx2.psll.dq.bs
		x86_avx2_psll_q, // llvm.x86.avx2.psll.q
		x86_avx2_psll_w, // llvm.x86.avx2.psll.w
		x86_avx2_pslli_d, // llvm.x86.avx2.pslli.d
		x86_avx2_pslli_q, // llvm.x86.avx2.pslli.q
		x86_avx2_pslli_w, // llvm.x86.avx2.pslli.w
		x86_avx2_psllv_d, // llvm.x86.avx2.psllv.d
		x86_avx2_psllv_d_256, // llvm.x86.avx2.psllv.d.256
		x86_avx2_psllv_q, // llvm.x86.avx2.psllv.q
		x86_avx2_psllv_q_256, // llvm.x86.avx2.psllv.q.256
		x86_avx2_psra_d, // llvm.x86.avx2.psra.d
		x86_avx2_psra_w, // llvm.x86.avx2.psra.w
		x86_avx2_psrai_d, // llvm.x86.avx2.psrai.d
		x86_avx2_psrai_w, // llvm.x86.avx2.psrai.w
		x86_avx2_psrav_d, // llvm.x86.avx2.psrav.d
		x86_avx2_psrav_d_256, // llvm.x86.avx2.psrav.d.256
		x86_avx2_psrl_d, // llvm.x86.avx2.psrl.d
		x86_avx2_psrl_dq, // llvm.x86.avx2.psrl.dq
		x86_avx2_psrl_dq_bs, // llvm.x86.avx2.psrl.dq.bs
		x86_avx2_psrl_q, // llvm.x86.avx2.psrl.q
		x86_avx2_psrl_w, // llvm.x86.avx2.psrl.w
		x86_avx2_psrli_d, // llvm.x86.avx2.psrli.d
		x86_avx2_psrli_q, // llvm.x86.avx2.psrli.q
		x86_avx2_psrli_w, // llvm.x86.avx2.psrli.w
		x86_avx2_psrlv_d, // llvm.x86.avx2.psrlv.d
		x86_avx2_psrlv_d_256, // llvm.x86.avx2.psrlv.d.256
		x86_avx2_psrlv_q, // llvm.x86.avx2.psrlv.q
		x86_avx2_psrlv_q_256, // llvm.x86.avx2.psrlv.q.256
		x86_avx2_psubs_b, // llvm.x86.avx2.psubs.b
		x86_avx2_psubs_w, // llvm.x86.avx2.psubs.w
		x86_avx2_psubus_b, // llvm.x86.avx2.psubus.b
		x86_avx2_psubus_w, // llvm.x86.avx2.psubus.w
		x86_avx2_vbroadcast_sd_pd_256, // llvm.x86.avx2.vbroadcast.s
		d.pd.256
		x86_avx2_vbroadcast_ss_ps, // llvm.x86.avx2.vbroadcast.s
		s.ps
		x86_avx2_vbroadcast_ss_ps_256, // llvm.x86.avx2.vbroadcast.s
		s.ps.256
		x86_avx2_vbroadcasti128, // llvm.x86.avx2.vbroadcasti1
		28
		x86_avx2_vextracti128, // llvm.x86.avx2.vextracti128
		x86_avx2_vinserti128, // llvm.x86.avx2.vinserti128
		x86_avx2_vperm2i128, // llvm.x86.avx2.vperm2i128
	x86_avx_addsub_pd_256, // llvm.x86.avx.addsub.pd.256	x86_avx_addsub_pd_256, // llvm.x86.avx.addsub.pd.256
	x86_avx_addsub_ps_256, // llvm.x86.avx.addsub.ps.256	x86_avx_addsub_ps_256, // llvm.x86.avx.addsub.ps.256
	x86_avx_blend_pd_256, // llvm.x86.avx.blend.pd.256	x86_avx_blend_pd_256, // llvm.x86.avx.blend.pd.256
	x86_avx_blend_ps_256, // llvm.x86.avx.blend.ps.256	x86_avx_blend_ps_256, // llvm.x86.avx.blend.ps.256
	x86_avx_blendv_pd_256, // llvm.x86.avx.blendv.pd.256	x86_avx_blendv_pd_256, // llvm.x86.avx.blendv.pd.256
	x86_avx_blendv_ps_256, // llvm.x86.avx.blendv.ps.256	x86_avx_blendv_ps_256, // llvm.x86.avx.blendv.ps.256
	x86_avx_cmp_pd_256, // llvm.x86.avx.cmp.pd.256	x86_avx_cmp_pd_256, // llvm.x86.avx.cmp.pd.256
	x86_avx_cmp_ps_256, // llvm.x86.avx.cmp.ps.256	x86_avx_cmp_ps_256, // llvm.x86.avx.cmp.ps.256
	x86_avx_cvt_pd2_ps_256, // llvm.x86.avx.cvt.pd2.ps.25 6	x86_avx_cvt_pd2_ps_256, // llvm.x86.avx.cvt.pd2.ps.25 6
	x86_avx_cvt_pd2dq_256, // llvm.x86.avx.cvt.pd2dq.256	x86_avx_cvt_pd2dq_256, // llvm.x86.avx.cvt.pd2dq.256

	skipping to change at line 548	skipping to change at line 1327
	x86_avx_cvtdq2_pd_256, // llvm.x86.avx.cvtdq2.pd.256	x86_avx_cvtdq2_pd_256, // llvm.x86.avx.cvtdq2.pd.256
	x86_avx_cvtdq2_ps_256, // llvm.x86.avx.cvtdq2.ps.256	x86_avx_cvtdq2_ps_256, // llvm.x86.avx.cvtdq2.ps.256
	x86_avx_cvtt_pd2dq_256, // llvm.x86.avx.cvtt.pd2dq.25 6	x86_avx_cvtt_pd2dq_256, // llvm.x86.avx.cvtt.pd2dq.25 6
	x86_avx_cvtt_ps2dq_256, // llvm.x86.avx.cvtt.ps2dq.25 6	x86_avx_cvtt_ps2dq_256, // llvm.x86.avx.cvtt.ps2dq.25 6
	x86_avx_dp_ps_256, // llvm.x86.avx.dp.ps.256	x86_avx_dp_ps_256, // llvm.x86.avx.dp.ps.256
	x86_avx_hadd_pd_256, // llvm.x86.avx.hadd.pd.256	x86_avx_hadd_pd_256, // llvm.x86.avx.hadd.pd.256
	x86_avx_hadd_ps_256, // llvm.x86.avx.hadd.ps.256	x86_avx_hadd_ps_256, // llvm.x86.avx.hadd.ps.256
	x86_avx_hsub_pd_256, // llvm.x86.avx.hsub.pd.256	x86_avx_hsub_pd_256, // llvm.x86.avx.hsub.pd.256
	x86_avx_hsub_ps_256, // llvm.x86.avx.hsub.ps.256	x86_avx_hsub_ps_256, // llvm.x86.avx.hsub.ps.256
	x86_avx_ldu_dq_256, // llvm.x86.avx.ldu.dq.256	x86_avx_ldu_dq_256, // llvm.x86.avx.ldu.dq.256

	x86_avx_loadu_dq_256, // llvm.x86.avx.loadu.dq.256
	x86_avx_loadu_pd_256, // llvm.x86.avx.loadu.pd.256
	x86_avx_loadu_ps_256, // llvm.x86.avx.loadu.ps.256
	x86_avx_maskload_pd, // llvm.x86.avx.maskload.pd	x86_avx_maskload_pd, // llvm.x86.avx.maskload.pd
	x86_avx_maskload_pd_256, // llvm.x86.avx.maskload.pd.2 56	x86_avx_maskload_pd_256, // llvm.x86.avx.maskload.pd.2 56
	x86_avx_maskload_ps, // llvm.x86.avx.maskload.ps	x86_avx_maskload_ps, // llvm.x86.avx.maskload.ps
	x86_avx_maskload_ps_256, // llvm.x86.avx.maskload.ps.2 56	x86_avx_maskload_ps_256, // llvm.x86.avx.maskload.ps.2 56
	x86_avx_maskstore_pd, // llvm.x86.avx.maskstore.pd	x86_avx_maskstore_pd, // llvm.x86.avx.maskstore.pd
	x86_avx_maskstore_pd_256, // llvm.x86.avx.maskstore.pd. 256	x86_avx_maskstore_pd_256, // llvm.x86.avx.maskstore.pd. 256
	x86_avx_maskstore_ps, // llvm.x86.avx.maskstore.ps	x86_avx_maskstore_ps, // llvm.x86.avx.maskstore.ps
	x86_avx_maskstore_ps_256, // llvm.x86.avx.maskstore.ps. 256	x86_avx_maskstore_ps_256, // llvm.x86.avx.maskstore.ps. 256
	x86_avx_max_pd_256, // llvm.x86.avx.max.pd.256	x86_avx_max_pd_256, // llvm.x86.avx.max.pd.256
	x86_avx_max_ps_256, // llvm.x86.avx.max.ps.256	x86_avx_max_ps_256, // llvm.x86.avx.max.ps.256

	skipping to change at line 581	skipping to change at line 1357
	x86_avx_rcp_ps_256, // llvm.x86.avx.rcp.ps.256	x86_avx_rcp_ps_256, // llvm.x86.avx.rcp.ps.256
	x86_avx_round_pd_256, // llvm.x86.avx.round.pd.256	x86_avx_round_pd_256, // llvm.x86.avx.round.pd.256
	x86_avx_round_ps_256, // llvm.x86.avx.round.ps.256	x86_avx_round_ps_256, // llvm.x86.avx.round.ps.256
	x86_avx_rsqrt_ps_256, // llvm.x86.avx.rsqrt.ps.256	x86_avx_rsqrt_ps_256, // llvm.x86.avx.rsqrt.ps.256
	x86_avx_sqrt_pd_256, // llvm.x86.avx.sqrt.pd.256	x86_avx_sqrt_pd_256, // llvm.x86.avx.sqrt.pd.256
	x86_avx_sqrt_ps_256, // llvm.x86.avx.sqrt.ps.256	x86_avx_sqrt_ps_256, // llvm.x86.avx.sqrt.ps.256
	x86_avx_storeu_dq_256, // llvm.x86.avx.storeu.dq.256	x86_avx_storeu_dq_256, // llvm.x86.avx.storeu.dq.256
	x86_avx_storeu_pd_256, // llvm.x86.avx.storeu.pd.256	x86_avx_storeu_pd_256, // llvm.x86.avx.storeu.pd.256
	x86_avx_storeu_ps_256, // llvm.x86.avx.storeu.ps.256	x86_avx_storeu_ps_256, // llvm.x86.avx.storeu.ps.256
	x86_avx_vbroadcast_sd_256, // llvm.x86.avx.vbroadcast.sd .256	x86_avx_vbroadcast_sd_256, // llvm.x86.avx.vbroadcast.sd .256

		x86_avx_vbroadcast_ss, // llvm.x86.avx.vbroadcast.ss
		x86_avx_vbroadcast_ss_256, // llvm.x86.avx.vbroadcast.ss
		.256
	x86_avx_vbroadcastf128_pd_256, // llvm.x86.avx.vbroadcastf12 8.pd.256	x86_avx_vbroadcastf128_pd_256, // llvm.x86.avx.vbroadcastf12 8.pd.256
	x86_avx_vbroadcastf128_ps_256, // llvm.x86.avx.vbroadcastf12 8.ps.256	x86_avx_vbroadcastf128_ps_256, // llvm.x86.avx.vbroadcastf12 8.ps.256

	x86_avx_vbroadcastss, // llvm.x86.avx.vbroadcastss
	x86_avx_vbroadcastss_256, // llvm.x86.avx.vbroadcastss.
	256
	x86_avx_vextractf128_pd_256, // llvm.x86.avx.vextractf128. pd.256	x86_avx_vextractf128_pd_256, // llvm.x86.avx.vextractf128. pd.256
	x86_avx_vextractf128_ps_256, // llvm.x86.avx.vextractf128. ps.256	x86_avx_vextractf128_ps_256, // llvm.x86.avx.vextractf128. ps.256
	x86_avx_vextractf128_si_256, // llvm.x86.avx.vextractf128. si.256	x86_avx_vextractf128_si_256, // llvm.x86.avx.vextractf128. si.256
	x86_avx_vinsertf128_pd_256, // llvm.x86.avx.vinsertf128.p d.256	x86_avx_vinsertf128_pd_256, // llvm.x86.avx.vinsertf128.p d.256
	x86_avx_vinsertf128_ps_256, // llvm.x86.avx.vinsertf128.p s.256	x86_avx_vinsertf128_ps_256, // llvm.x86.avx.vinsertf128.p s.256
	x86_avx_vinsertf128_si_256, // llvm.x86.avx.vinsertf128.s i.256	x86_avx_vinsertf128_si_256, // llvm.x86.avx.vinsertf128.s i.256
	x86_avx_vperm2f128_pd_256, // llvm.x86.avx.vperm2f128.pd .256	x86_avx_vperm2f128_pd_256, // llvm.x86.avx.vperm2f128.pd .256
	x86_avx_vperm2f128_ps_256, // llvm.x86.avx.vperm2f128.ps .256	x86_avx_vperm2f128_ps_256, // llvm.x86.avx.vperm2f128.ps .256
	x86_avx_vperm2f128_si_256, // llvm.x86.avx.vperm2f128.si .256	x86_avx_vperm2f128_si_256, // llvm.x86.avx.vperm2f128.si .256

	x86_avx_vpermil_pd, // llvm.x86.avx.vpermil.pd
	x86_avx_vpermil_pd_256, // llvm.x86.avx.vpermil.pd.25
	6
	x86_avx_vpermil_ps, // llvm.x86.avx.vpermil.ps
	x86_avx_vpermil_ps_256, // llvm.x86.avx.vpermil.ps.25
	6
	x86_avx_vpermilvar_pd, // llvm.x86.avx.vpermilvar.pd	x86_avx_vpermilvar_pd, // llvm.x86.avx.vpermilvar.pd
	x86_avx_vpermilvar_pd_256, // llvm.x86.avx.vpermilvar.pd .256	x86_avx_vpermilvar_pd_256, // llvm.x86.avx.vpermilvar.pd .256
	x86_avx_vpermilvar_ps, // llvm.x86.avx.vpermilvar.ps	x86_avx_vpermilvar_ps, // llvm.x86.avx.vpermilvar.ps
	x86_avx_vpermilvar_ps_256, // llvm.x86.avx.vpermilvar.ps .256	x86_avx_vpermilvar_ps_256, // llvm.x86.avx.vpermilvar.ps .256
	x86_avx_vtestc_pd, // llvm.x86.avx.vtestc.pd	x86_avx_vtestc_pd, // llvm.x86.avx.vtestc.pd
	x86_avx_vtestc_pd_256, // llvm.x86.avx.vtestc.pd.256	x86_avx_vtestc_pd_256, // llvm.x86.avx.vtestc.pd.256
	x86_avx_vtestc_ps, // llvm.x86.avx.vtestc.ps	x86_avx_vtestc_ps, // llvm.x86.avx.vtestc.ps
	x86_avx_vtestc_ps_256, // llvm.x86.avx.vtestc.ps.256	x86_avx_vtestc_ps_256, // llvm.x86.avx.vtestc.ps.256
	x86_avx_vtestnzc_pd, // llvm.x86.avx.vtestnzc.pd	x86_avx_vtestnzc_pd, // llvm.x86.avx.vtestnzc.pd
	x86_avx_vtestnzc_pd_256, // llvm.x86.avx.vtestnzc.pd.2 56	x86_avx_vtestnzc_pd_256, // llvm.x86.avx.vtestnzc.pd.2 56
	x86_avx_vtestnzc_ps, // llvm.x86.avx.vtestnzc.ps	x86_avx_vtestnzc_ps, // llvm.x86.avx.vtestnzc.ps
	x86_avx_vtestnzc_ps_256, // llvm.x86.avx.vtestnzc.ps.2 56	x86_avx_vtestnzc_ps_256, // llvm.x86.avx.vtestnzc.ps.2 56
	x86_avx_vtestz_pd, // llvm.x86.avx.vtestz.pd	x86_avx_vtestz_pd, // llvm.x86.avx.vtestz.pd
	x86_avx_vtestz_pd_256, // llvm.x86.avx.vtestz.pd.256	x86_avx_vtestz_pd_256, // llvm.x86.avx.vtestz.pd.256
	x86_avx_vtestz_ps, // llvm.x86.avx.vtestz.ps	x86_avx_vtestz_ps, // llvm.x86.avx.vtestz.ps
	x86_avx_vtestz_ps_256, // llvm.x86.avx.vtestz.ps.256	x86_avx_vtestz_ps_256, // llvm.x86.avx.vtestz.ps.256
	x86_avx_vzeroall, // llvm.x86.avx.vzeroall	x86_avx_vzeroall, // llvm.x86.avx.vzeroall
	x86_avx_vzeroupper, // llvm.x86.avx.vzeroupper	x86_avx_vzeroupper, // llvm.x86.avx.vzeroupper

		x86_bmi_bextr_32, // llvm.x86.bmi.bextr.32
		x86_bmi_bextr_64, // llvm.x86.bmi.bextr.64
		x86_bmi_bzhi_32, // llvm.x86.bmi.bzhi.32
		x86_bmi_bzhi_64, // llvm.x86.bmi.bzhi.64
		x86_bmi_pdep_32, // llvm.x86.bmi.pdep.32
		x86_bmi_pdep_64, // llvm.x86.bmi.pdep.64
		x86_bmi_pext_32, // llvm.x86.bmi.pext.32
		x86_bmi_pext_64, // llvm.x86.bmi.pext.64
		x86_fma4_vfmadd_pd, // llvm.x86.fma4.vfmadd.pd
		x86_fma4_vfmadd_pd_256, // llvm.x86.fma4.vfmadd.pd.25
		6
		x86_fma4_vfmadd_ps, // llvm.x86.fma4.vfmadd.ps
		x86_fma4_vfmadd_ps_256, // llvm.x86.fma4.vfmadd.ps.25
		6
		x86_fma4_vfmadd_sd, // llvm.x86.fma4.vfmadd.sd
		x86_fma4_vfmadd_ss, // llvm.x86.fma4.vfmadd.ss
		x86_fma4_vfmaddsub_pd, // llvm.x86.fma4.vfmaddsub.pd
		x86_fma4_vfmaddsub_pd_256, // llvm.x86.fma4.vfmaddsub.pd
		.256
		x86_fma4_vfmaddsub_ps, // llvm.x86.fma4.vfmaddsub.ps
		x86_fma4_vfmaddsub_ps_256, // llvm.x86.fma4.vfmaddsub.ps
		.256
		x86_fma4_vfmsub_pd, // llvm.x86.fma4.vfmsub.pd
		x86_fma4_vfmsub_pd_256, // llvm.x86.fma4.vfmsub.pd.25
		6
		x86_fma4_vfmsub_ps, // llvm.x86.fma4.vfmsub.ps
		x86_fma4_vfmsub_ps_256, // llvm.x86.fma4.vfmsub.ps.25
		6
		x86_fma4_vfmsub_sd, // llvm.x86.fma4.vfmsub.sd
		x86_fma4_vfmsub_ss, // llvm.x86.fma4.vfmsub.ss
		x86_fma4_vfmsubadd_pd, // llvm.x86.fma4.vfmsubadd.pd
		x86_fma4_vfmsubadd_pd_256, // llvm.x86.fma4.vfmsubadd.pd
		.256
		x86_fma4_vfmsubadd_ps, // llvm.x86.fma4.vfmsubadd.ps
		x86_fma4_vfmsubadd_ps_256, // llvm.x86.fma4.vfmsubadd.ps
		.256
		x86_fma4_vfnmadd_pd, // llvm.x86.fma4.vfnmadd.pd
		x86_fma4_vfnmadd_pd_256, // llvm.x86.fma4.vfnmadd.pd.2
		56
		x86_fma4_vfnmadd_ps, // llvm.x86.fma4.vfnmadd.ps
		x86_fma4_vfnmadd_ps_256, // llvm.x86.fma4.vfnmadd.ps.2
		56
		x86_fma4_vfnmadd_sd, // llvm.x86.fma4.vfnmadd.sd
		x86_fma4_vfnmadd_ss, // llvm.x86.fma4.vfnmadd.ss
		x86_fma4_vfnmsub_pd, // llvm.x86.fma4.vfnmsub.pd
		x86_fma4_vfnmsub_pd_256, // llvm.x86.fma4.vfnmsub.pd.2
		56
		x86_fma4_vfnmsub_ps, // llvm.x86.fma4.vfnmsub.ps
		x86_fma4_vfnmsub_ps_256, // llvm.x86.fma4.vfnmsub.ps.2
		56
		x86_fma4_vfnmsub_sd, // llvm.x86.fma4.vfnmsub.sd
		x86_fma4_vfnmsub_ss, // llvm.x86.fma4.vfnmsub.ss
	x86_int, // llvm.x86.int	x86_int, // llvm.x86.int
	x86_mmx_emms, // llvm.x86.mmx.emms	x86_mmx_emms, // llvm.x86.mmx.emms
	x86_mmx_femms, // llvm.x86.mmx.femms	x86_mmx_femms, // llvm.x86.mmx.femms
	x86_mmx_maskmovq, // llvm.x86.mmx.maskmovq	x86_mmx_maskmovq, // llvm.x86.mmx.maskmovq
	x86_mmx_movnt_dq, // llvm.x86.mmx.movnt.dq	x86_mmx_movnt_dq, // llvm.x86.mmx.movnt.dq
	x86_mmx_packssdw, // llvm.x86.mmx.packssdw	x86_mmx_packssdw, // llvm.x86.mmx.packssdw
	x86_mmx_packsswb, // llvm.x86.mmx.packsswb	x86_mmx_packsswb, // llvm.x86.mmx.packsswb
	x86_mmx_packuswb, // llvm.x86.mmx.packuswb	x86_mmx_packuswb, // llvm.x86.mmx.packuswb
	x86_mmx_padd_b, // llvm.x86.mmx.padd.b	x86_mmx_padd_b, // llvm.x86.mmx.padd.b
	x86_mmx_padd_d, // llvm.x86.mmx.padd.d	x86_mmx_padd_d, // llvm.x86.mmx.padd.d

	skipping to change at line 688	skipping to change at line 1500
	x86_mmx_psubs_w, // llvm.x86.mmx.psubs.w	x86_mmx_psubs_w, // llvm.x86.mmx.psubs.w
	x86_mmx_psubus_b, // llvm.x86.mmx.psubus.b	x86_mmx_psubus_b, // llvm.x86.mmx.psubus.b
	x86_mmx_psubus_w, // llvm.x86.mmx.psubus.w	x86_mmx_psubus_w, // llvm.x86.mmx.psubus.w
	x86_mmx_punpckhbw, // llvm.x86.mmx.punpckhbw	x86_mmx_punpckhbw, // llvm.x86.mmx.punpckhbw
	x86_mmx_punpckhdq, // llvm.x86.mmx.punpckhdq	x86_mmx_punpckhdq, // llvm.x86.mmx.punpckhdq
	x86_mmx_punpckhwd, // llvm.x86.mmx.punpckhwd	x86_mmx_punpckhwd, // llvm.x86.mmx.punpckhwd
	x86_mmx_punpcklbw, // llvm.x86.mmx.punpcklbw	x86_mmx_punpcklbw, // llvm.x86.mmx.punpcklbw
	x86_mmx_punpckldq, // llvm.x86.mmx.punpckldq	x86_mmx_punpckldq, // llvm.x86.mmx.punpckldq
	x86_mmx_punpcklwd, // llvm.x86.mmx.punpcklwd	x86_mmx_punpcklwd, // llvm.x86.mmx.punpcklwd
	x86_mmx_pxor, // llvm.x86.mmx.pxor	x86_mmx_pxor, // llvm.x86.mmx.pxor

		x86_rdfsbase_32, // llvm.x86.rdfsbase.32
		x86_rdfsbase_64, // llvm.x86.rdfsbase.64
		x86_rdgsbase_32, // llvm.x86.rdgsbase.32
		x86_rdgsbase_64, // llvm.x86.rdgsbase.64
	x86_sse2_add_sd, // llvm.x86.sse2.add.sd	x86_sse2_add_sd, // llvm.x86.sse2.add.sd
	x86_sse2_clflush, // llvm.x86.sse2.clflush	x86_sse2_clflush, // llvm.x86.sse2.clflush
	x86_sse2_cmp_pd, // llvm.x86.sse2.cmp.pd	x86_sse2_cmp_pd, // llvm.x86.sse2.cmp.pd
	x86_sse2_cmp_sd, // llvm.x86.sse2.cmp.sd	x86_sse2_cmp_sd, // llvm.x86.sse2.cmp.sd
	x86_sse2_comieq_sd, // llvm.x86.sse2.comieq.sd	x86_sse2_comieq_sd, // llvm.x86.sse2.comieq.sd
	x86_sse2_comige_sd, // llvm.x86.sse2.comige.sd	x86_sse2_comige_sd, // llvm.x86.sse2.comige.sd
	x86_sse2_comigt_sd, // llvm.x86.sse2.comigt.sd	x86_sse2_comigt_sd, // llvm.x86.sse2.comigt.sd
	x86_sse2_comile_sd, // llvm.x86.sse2.comile.sd	x86_sse2_comile_sd, // llvm.x86.sse2.comile.sd
	x86_sse2_comilt_sd, // llvm.x86.sse2.comilt.sd	x86_sse2_comilt_sd, // llvm.x86.sse2.comilt.sd
	x86_sse2_comineq_sd, // llvm.x86.sse2.comineq.sd	x86_sse2_comineq_sd, // llvm.x86.sse2.comineq.sd

	skipping to change at line 733	skipping to change at line 1549
	x86_sse2_mul_sd, // llvm.x86.sse2.mul.sd	x86_sse2_mul_sd, // llvm.x86.sse2.mul.sd
	x86_sse2_packssdw_128, // llvm.x86.sse2.packssdw.128	x86_sse2_packssdw_128, // llvm.x86.sse2.packssdw.128
	x86_sse2_packsswb_128, // llvm.x86.sse2.packsswb.128	x86_sse2_packsswb_128, // llvm.x86.sse2.packsswb.128
	x86_sse2_packuswb_128, // llvm.x86.sse2.packuswb.128	x86_sse2_packuswb_128, // llvm.x86.sse2.packuswb.128
	x86_sse2_padds_b, // llvm.x86.sse2.padds.b	x86_sse2_padds_b, // llvm.x86.sse2.padds.b
	x86_sse2_padds_w, // llvm.x86.sse2.padds.w	x86_sse2_padds_w, // llvm.x86.sse2.padds.w
	x86_sse2_paddus_b, // llvm.x86.sse2.paddus.b	x86_sse2_paddus_b, // llvm.x86.sse2.paddus.b
	x86_sse2_paddus_w, // llvm.x86.sse2.paddus.w	x86_sse2_paddus_w, // llvm.x86.sse2.paddus.w
	x86_sse2_pavg_b, // llvm.x86.sse2.pavg.b	x86_sse2_pavg_b, // llvm.x86.sse2.pavg.b
	x86_sse2_pavg_w, // llvm.x86.sse2.pavg.w	x86_sse2_pavg_w, // llvm.x86.sse2.pavg.w

	x86_sse2_pcmpeq_b, // llvm.x86.sse2.pcmpeq.b
	x86_sse2_pcmpeq_d, // llvm.x86.sse2.pcmpeq.d
	x86_sse2_pcmpeq_w, // llvm.x86.sse2.pcmpeq.w
	x86_sse2_pcmpgt_b, // llvm.x86.sse2.pcmpgt.b
	x86_sse2_pcmpgt_d, // llvm.x86.sse2.pcmpgt.d
	x86_sse2_pcmpgt_w, // llvm.x86.sse2.pcmpgt.w
	x86_sse2_pmadd_wd, // llvm.x86.sse2.pmadd.wd	x86_sse2_pmadd_wd, // llvm.x86.sse2.pmadd.wd
	x86_sse2_pmaxs_w, // llvm.x86.sse2.pmaxs.w	x86_sse2_pmaxs_w, // llvm.x86.sse2.pmaxs.w
	x86_sse2_pmaxu_b, // llvm.x86.sse2.pmaxu.b	x86_sse2_pmaxu_b, // llvm.x86.sse2.pmaxu.b
	x86_sse2_pmins_w, // llvm.x86.sse2.pmins.w	x86_sse2_pmins_w, // llvm.x86.sse2.pmins.w
	x86_sse2_pminu_b, // llvm.x86.sse2.pminu.b	x86_sse2_pminu_b, // llvm.x86.sse2.pminu.b
	x86_sse2_pmovmskb_128, // llvm.x86.sse2.pmovmskb.128	x86_sse2_pmovmskb_128, // llvm.x86.sse2.pmovmskb.128
	x86_sse2_pmulh_w, // llvm.x86.sse2.pmulh.w	x86_sse2_pmulh_w, // llvm.x86.sse2.pmulh.w
	x86_sse2_pmulhu_w, // llvm.x86.sse2.pmulhu.w	x86_sse2_pmulhu_w, // llvm.x86.sse2.pmulhu.w
	x86_sse2_pmulu_dq, // llvm.x86.sse2.pmulu.dq	x86_sse2_pmulu_dq, // llvm.x86.sse2.pmulu.dq
	x86_sse2_psad_bw, // llvm.x86.sse2.psad.bw	x86_sse2_psad_bw, // llvm.x86.sse2.psad.bw

	skipping to change at line 807	skipping to change at line 1617
	x86_sse41_blendvps, // llvm.x86.sse41.blendvps	x86_sse41_blendvps, // llvm.x86.sse41.blendvps
	x86_sse41_dppd, // llvm.x86.sse41.dppd	x86_sse41_dppd, // llvm.x86.sse41.dppd
	x86_sse41_dpps, // llvm.x86.sse41.dpps	x86_sse41_dpps, // llvm.x86.sse41.dpps
	x86_sse41_extractps, // llvm.x86.sse41.extractps	x86_sse41_extractps, // llvm.x86.sse41.extractps
	x86_sse41_insertps, // llvm.x86.sse41.insertps	x86_sse41_insertps, // llvm.x86.sse41.insertps
	x86_sse41_movntdqa, // llvm.x86.sse41.movntdqa	x86_sse41_movntdqa, // llvm.x86.sse41.movntdqa
	x86_sse41_mpsadbw, // llvm.x86.sse41.mpsadbw	x86_sse41_mpsadbw, // llvm.x86.sse41.mpsadbw
	x86_sse41_packusdw, // llvm.x86.sse41.packusdw	x86_sse41_packusdw, // llvm.x86.sse41.packusdw
	x86_sse41_pblendvb, // llvm.x86.sse41.pblendvb	x86_sse41_pblendvb, // llvm.x86.sse41.pblendvb
	x86_sse41_pblendw, // llvm.x86.sse41.pblendw	x86_sse41_pblendw, // llvm.x86.sse41.pblendw

	x86_sse41_pcmpeqq, // llvm.x86.sse41.pcmpeqq
	x86_sse41_pextrb, // llvm.x86.sse41.pextrb	x86_sse41_pextrb, // llvm.x86.sse41.pextrb
	x86_sse41_pextrd, // llvm.x86.sse41.pextrd	x86_sse41_pextrd, // llvm.x86.sse41.pextrd
	x86_sse41_pextrq, // llvm.x86.sse41.pextrq	x86_sse41_pextrq, // llvm.x86.sse41.pextrq
	x86_sse41_phminposuw, // llvm.x86.sse41.phminposuw	x86_sse41_phminposuw, // llvm.x86.sse41.phminposuw
	x86_sse41_pmaxsb, // llvm.x86.sse41.pmaxsb	x86_sse41_pmaxsb, // llvm.x86.sse41.pmaxsb
	x86_sse41_pmaxsd, // llvm.x86.sse41.pmaxsd	x86_sse41_pmaxsd, // llvm.x86.sse41.pmaxsd
	x86_sse41_pmaxud, // llvm.x86.sse41.pmaxud	x86_sse41_pmaxud, // llvm.x86.sse41.pmaxud
	x86_sse41_pmaxuw, // llvm.x86.sse41.pmaxuw	x86_sse41_pmaxuw, // llvm.x86.sse41.pmaxuw
	x86_sse41_pminsb, // llvm.x86.sse41.pminsb	x86_sse41_pminsb, // llvm.x86.sse41.pminsb
	x86_sse41_pminsd, // llvm.x86.sse41.pminsd	x86_sse41_pminsd, // llvm.x86.sse41.pminsd

	skipping to change at line 852	skipping to change at line 1661
	x86_sse42_crc32_32_8, // llvm.x86.sse42.crc32.32.8	x86_sse42_crc32_32_8, // llvm.x86.sse42.crc32.32.8
	x86_sse42_crc32_64_64, // llvm.x86.sse42.crc32.64.64	x86_sse42_crc32_64_64, // llvm.x86.sse42.crc32.64.64
	x86_sse42_crc32_64_8, // llvm.x86.sse42.crc32.64.8	x86_sse42_crc32_64_8, // llvm.x86.sse42.crc32.64.8
	x86_sse42_pcmpestri128, // llvm.x86.sse42.pcmpestri12 8	x86_sse42_pcmpestri128, // llvm.x86.sse42.pcmpestri12 8
	x86_sse42_pcmpestria128, // llvm.x86.sse42.pcmpestria1 28	x86_sse42_pcmpestria128, // llvm.x86.sse42.pcmpestria1 28
	x86_sse42_pcmpestric128, // llvm.x86.sse42.pcmpestric1 28	x86_sse42_pcmpestric128, // llvm.x86.sse42.pcmpestric1 28
	x86_sse42_pcmpestrio128, // llvm.x86.sse42.pcmpestrio1 28	x86_sse42_pcmpestrio128, // llvm.x86.sse42.pcmpestrio1 28
	x86_sse42_pcmpestris128, // llvm.x86.sse42.pcmpestris1 28	x86_sse42_pcmpestris128, // llvm.x86.sse42.pcmpestris1 28
	x86_sse42_pcmpestriz128, // llvm.x86.sse42.pcmpestriz1 28	x86_sse42_pcmpestriz128, // llvm.x86.sse42.pcmpestriz1 28
	x86_sse42_pcmpestrm128, // llvm.x86.sse42.pcmpestrm12 8	x86_sse42_pcmpestrm128, // llvm.x86.sse42.pcmpestrm12 8

	x86_sse42_pcmpgtq, // llvm.x86.sse42.pcmpgtq
	x86_sse42_pcmpistri128, // llvm.x86.sse42.pcmpistri12 8	x86_sse42_pcmpistri128, // llvm.x86.sse42.pcmpistri12 8
	x86_sse42_pcmpistria128, // llvm.x86.sse42.pcmpistria1 28	x86_sse42_pcmpistria128, // llvm.x86.sse42.pcmpistria1 28
	x86_sse42_pcmpistric128, // llvm.x86.sse42.pcmpistric1 28	x86_sse42_pcmpistric128, // llvm.x86.sse42.pcmpistric1 28
	x86_sse42_pcmpistrio128, // llvm.x86.sse42.pcmpistrio1 28	x86_sse42_pcmpistrio128, // llvm.x86.sse42.pcmpistrio1 28
	x86_sse42_pcmpistris128, // llvm.x86.sse42.pcmpistris1 28	x86_sse42_pcmpistris128, // llvm.x86.sse42.pcmpistris1 28
	x86_sse42_pcmpistriz128, // llvm.x86.sse42.pcmpistriz1 28	x86_sse42_pcmpistriz128, // llvm.x86.sse42.pcmpistriz1 28
	x86_sse42_pcmpistrm128, // llvm.x86.sse42.pcmpistrm12 8	x86_sse42_pcmpistrm128, // llvm.x86.sse42.pcmpistrm12 8
	x86_sse_add_ss, // llvm.x86.sse.add.ss	x86_sse_add_ss, // llvm.x86.sse.add.ss
	x86_sse_cmp_ps, // llvm.x86.sse.cmp.ps	x86_sse_cmp_ps, // llvm.x86.sse.cmp.ps
	x86_sse_cmp_ss, // llvm.x86.sse.cmp.ss	x86_sse_cmp_ss, // llvm.x86.sse.cmp.ss

	skipping to change at line 936	skipping to change at line 1744
	x86_ssse3_pmul_hr_sw, // llvm.x86.ssse3.pmul.hr.sw	x86_ssse3_pmul_hr_sw, // llvm.x86.ssse3.pmul.hr.sw
	x86_ssse3_pmul_hr_sw_128, // llvm.x86.ssse3.pmul.hr.sw. 128	x86_ssse3_pmul_hr_sw_128, // llvm.x86.ssse3.pmul.hr.sw. 128
	x86_ssse3_pshuf_b, // llvm.x86.ssse3.pshuf.b	x86_ssse3_pshuf_b, // llvm.x86.ssse3.pshuf.b
	x86_ssse3_pshuf_b_128, // llvm.x86.ssse3.pshuf.b.128	x86_ssse3_pshuf_b_128, // llvm.x86.ssse3.pshuf.b.128
	x86_ssse3_psign_b, // llvm.x86.ssse3.psign.b	x86_ssse3_psign_b, // llvm.x86.ssse3.psign.b
	x86_ssse3_psign_b_128, // llvm.x86.ssse3.psign.b.128	x86_ssse3_psign_b_128, // llvm.x86.ssse3.psign.b.128
	x86_ssse3_psign_d, // llvm.x86.ssse3.psign.d	x86_ssse3_psign_d, // llvm.x86.ssse3.psign.d
	x86_ssse3_psign_d_128, // llvm.x86.ssse3.psign.d.128	x86_ssse3_psign_d_128, // llvm.x86.ssse3.psign.d.128
	x86_ssse3_psign_w, // llvm.x86.ssse3.psign.w	x86_ssse3_psign_w, // llvm.x86.ssse3.psign.w
	x86_ssse3_psign_w_128, // llvm.x86.ssse3.psign.w.128	x86_ssse3_psign_w_128, // llvm.x86.ssse3.psign.w.128

		x86_vcvtph2ps_128, // llvm.x86.vcvtph2ps.128
		x86_vcvtph2ps_256, // llvm.x86.vcvtph2ps.256
		x86_vcvtps2ph_128, // llvm.x86.vcvtps2ph.128
		x86_vcvtps2ph_256, // llvm.x86.vcvtps2ph.256
		x86_wrfsbase_32, // llvm.x86.wrfsbase.32
		x86_wrfsbase_64, // llvm.x86.wrfsbase.64
		x86_wrgsbase_32, // llvm.x86.wrgsbase.32
		x86_wrgsbase_64, // llvm.x86.wrgsbase.64
		x86_xop_vfrcz_pd, // llvm.x86.xop.vfrcz.pd
		x86_xop_vfrcz_pd_256, // llvm.x86.xop.vfrcz.pd.256
		x86_xop_vfrcz_ps, // llvm.x86.xop.vfrcz.ps
		x86_xop_vfrcz_ps_256, // llvm.x86.xop.vfrcz.ps.256
		x86_xop_vfrcz_sd, // llvm.x86.xop.vfrcz.sd
		x86_xop_vfrcz_ss, // llvm.x86.xop.vfrcz.ss
		x86_xop_vpcmov, // llvm.x86.xop.vpcmov
		x86_xop_vpcmov_256, // llvm.x86.xop.vpcmov.256
		x86_xop_vpcomeqb, // llvm.x86.xop.vpcomeqb
		x86_xop_vpcomeqd, // llvm.x86.xop.vpcomeqd
		x86_xop_vpcomeqq, // llvm.x86.xop.vpcomeqq
		x86_xop_vpcomequb, // llvm.x86.xop.vpcomequb
		x86_xop_vpcomequd, // llvm.x86.xop.vpcomequd
		x86_xop_vpcomequq, // llvm.x86.xop.vpcomequq
		x86_xop_vpcomequw, // llvm.x86.xop.vpcomequw
		x86_xop_vpcomeqw, // llvm.x86.xop.vpcomeqw
		x86_xop_vpcomfalseb, // llvm.x86.xop.vpcomfalseb
		x86_xop_vpcomfalsed, // llvm.x86.xop.vpcomfalsed
		x86_xop_vpcomfalseq, // llvm.x86.xop.vpcomfalseq
		x86_xop_vpcomfalseub, // llvm.x86.xop.vpcomfalseub
		x86_xop_vpcomfalseud, // llvm.x86.xop.vpcomfalseud
		x86_xop_vpcomfalseuq, // llvm.x86.xop.vpcomfalseuq
		x86_xop_vpcomfalseuw, // llvm.x86.xop.vpcomfalseuw
		x86_xop_vpcomfalsew, // llvm.x86.xop.vpcomfalsew
		x86_xop_vpcomgeb, // llvm.x86.xop.vpcomgeb
		x86_xop_vpcomged, // llvm.x86.xop.vpcomged
		x86_xop_vpcomgeq, // llvm.x86.xop.vpcomgeq
		x86_xop_vpcomgeub, // llvm.x86.xop.vpcomgeub
		x86_xop_vpcomgeud, // llvm.x86.xop.vpcomgeud
		x86_xop_vpcomgeuq, // llvm.x86.xop.vpcomgeuq
		x86_xop_vpcomgeuw, // llvm.x86.xop.vpcomgeuw
		x86_xop_vpcomgew, // llvm.x86.xop.vpcomgew
		x86_xop_vpcomgtb, // llvm.x86.xop.vpcomgtb
		x86_xop_vpcomgtd, // llvm.x86.xop.vpcomgtd
		x86_xop_vpcomgtq, // llvm.x86.xop.vpcomgtq
		x86_xop_vpcomgtub, // llvm.x86.xop.vpcomgtub
		x86_xop_vpcomgtud, // llvm.x86.xop.vpcomgtud
		x86_xop_vpcomgtuq, // llvm.x86.xop.vpcomgtuq
		x86_xop_vpcomgtuw, // llvm.x86.xop.vpcomgtuw
		x86_xop_vpcomgtw, // llvm.x86.xop.vpcomgtw
		x86_xop_vpcomleb, // llvm.x86.xop.vpcomleb
		x86_xop_vpcomled, // llvm.x86.xop.vpcomled
		x86_xop_vpcomleq, // llvm.x86.xop.vpcomleq
		x86_xop_vpcomleub, // llvm.x86.xop.vpcomleub
		x86_xop_vpcomleud, // llvm.x86.xop.vpcomleud
		x86_xop_vpcomleuq, // llvm.x86.xop.vpcomleuq
		x86_xop_vpcomleuw, // llvm.x86.xop.vpcomleuw
		x86_xop_vpcomlew, // llvm.x86.xop.vpcomlew
		x86_xop_vpcomltb, // llvm.x86.xop.vpcomltb
		x86_xop_vpcomltd, // llvm.x86.xop.vpcomltd
		x86_xop_vpcomltq, // llvm.x86.xop.vpcomltq
		x86_xop_vpcomltub, // llvm.x86.xop.vpcomltub
		x86_xop_vpcomltud, // llvm.x86.xop.vpcomltud
		x86_xop_vpcomltuq, // llvm.x86.xop.vpcomltuq
		x86_xop_vpcomltuw, // llvm.x86.xop.vpcomltuw
		x86_xop_vpcomltw, // llvm.x86.xop.vpcomltw
		x86_xop_vpcomneb, // llvm.x86.xop.vpcomneb
		x86_xop_vpcomned, // llvm.x86.xop.vpcomned
		x86_xop_vpcomneq, // llvm.x86.xop.vpcomneq
		x86_xop_vpcomneub, // llvm.x86.xop.vpcomneub
		x86_xop_vpcomneud, // llvm.x86.xop.vpcomneud
		x86_xop_vpcomneuq, // llvm.x86.xop.vpcomneuq
		x86_xop_vpcomneuw, // llvm.x86.xop.vpcomneuw
		x86_xop_vpcomnew, // llvm.x86.xop.vpcomnew
		x86_xop_vpcomtrueb, // llvm.x86.xop.vpcomtrueb
		x86_xop_vpcomtrued, // llvm.x86.xop.vpcomtrued
		x86_xop_vpcomtrueq, // llvm.x86.xop.vpcomtrueq
		x86_xop_vpcomtrueub, // llvm.x86.xop.vpcomtrueub
		x86_xop_vpcomtrueud, // llvm.x86.xop.vpcomtrueud
		x86_xop_vpcomtrueuq, // llvm.x86.xop.vpcomtrueuq
		x86_xop_vpcomtrueuw, // llvm.x86.xop.vpcomtrueuw
		x86_xop_vpcomtruew, // llvm.x86.xop.vpcomtruew
		x86_xop_vpermil2pd, // llvm.x86.xop.vpermil2pd
		x86_xop_vpermil2pd_256, // llvm.x86.xop.vpermil2pd.25
		6
		x86_xop_vpermil2ps, // llvm.x86.xop.vpermil2ps
		x86_xop_vpermil2ps_256, // llvm.x86.xop.vpermil2ps.25
		6
		x86_xop_vphaddbd, // llvm.x86.xop.vphaddbd
		x86_xop_vphaddbq, // llvm.x86.xop.vphaddbq
		x86_xop_vphaddbw, // llvm.x86.xop.vphaddbw
		x86_xop_vphadddq, // llvm.x86.xop.vphadddq
		x86_xop_vphaddubd, // llvm.x86.xop.vphaddubd
		x86_xop_vphaddubq, // llvm.x86.xop.vphaddubq
		x86_xop_vphaddubw, // llvm.x86.xop.vphaddubw
		x86_xop_vphaddudq, // llvm.x86.xop.vphaddudq
		x86_xop_vphadduwd, // llvm.x86.xop.vphadduwd
		x86_xop_vphadduwq, // llvm.x86.xop.vphadduwq
		x86_xop_vphaddwd, // llvm.x86.xop.vphaddwd
		x86_xop_vphaddwq, // llvm.x86.xop.vphaddwq
		x86_xop_vphsubbw, // llvm.x86.xop.vphsubbw
		x86_xop_vphsubdq, // llvm.x86.xop.vphsubdq
		x86_xop_vphsubwd, // llvm.x86.xop.vphsubwd
		x86_xop_vpmacsdd, // llvm.x86.xop.vpmacsdd
		x86_xop_vpmacsdqh, // llvm.x86.xop.vpmacsdqh
		x86_xop_vpmacsdql, // llvm.x86.xop.vpmacsdql
		x86_xop_vpmacssdd, // llvm.x86.xop.vpmacssdd
		x86_xop_vpmacssdqh, // llvm.x86.xop.vpmacssdqh
		x86_xop_vpmacssdql, // llvm.x86.xop.vpmacssdql
		x86_xop_vpmacsswd, // llvm.x86.xop.vpmacsswd
		x86_xop_vpmacssww, // llvm.x86.xop.vpmacssww
		x86_xop_vpmacswd, // llvm.x86.xop.vpmacswd
		x86_xop_vpmacsww, // llvm.x86.xop.vpmacsww
		x86_xop_vpmadcsswd, // llvm.x86.xop.vpmadcsswd
		x86_xop_vpmadcswd, // llvm.x86.xop.vpmadcswd
		x86_xop_vpperm, // llvm.x86.xop.vpperm
		x86_xop_vprotb, // llvm.x86.xop.vprotb
		x86_xop_vprotd, // llvm.x86.xop.vprotd
		x86_xop_vprotq, // llvm.x86.xop.vprotq
		x86_xop_vprotw, // llvm.x86.xop.vprotw
		x86_xop_vpshab, // llvm.x86.xop.vpshab
		x86_xop_vpshad, // llvm.x86.xop.vpshad
		x86_xop_vpshaq, // llvm.x86.xop.vpshaq
		x86_xop_vpshaw, // llvm.x86.xop.vpshaw
		x86_xop_vpshlb, // llvm.x86.xop.vpshlb
		x86_xop_vpshld, // llvm.x86.xop.vpshld
		x86_xop_vpshlq, // llvm.x86.xop.vpshlq
		x86_xop_vpshlw, // llvm.x86.xop.vpshlw
	xcore_bitrev, // llvm.xcore.bitrev	xcore_bitrev, // llvm.xcore.bitrev
	xcore_checkevent, // llvm.xcore.checkevent	xcore_checkevent, // llvm.xcore.checkevent
	xcore_chkct, // llvm.xcore.chkct	xcore_chkct, // llvm.xcore.chkct
	xcore_clre, // llvm.xcore.clre	xcore_clre, // llvm.xcore.clre
	xcore_clrsr, // llvm.xcore.clrsr	xcore_clrsr, // llvm.xcore.clrsr
	xcore_crc32, // llvm.xcore.crc32	xcore_crc32, // llvm.xcore.crc32
	xcore_crc8, // llvm.xcore.crc8	xcore_crc8, // llvm.xcore.crc8
	xcore_eeu, // llvm.xcore.eeu	xcore_eeu, // llvm.xcore.eeu
	xcore_endin, // llvm.xcore.endin	xcore_endin, // llvm.xcore.endin
	xcore_freer, // llvm.xcore.freer	xcore_freer, // llvm.xcore.freer

	skipping to change at line 993	skipping to change at line 1925
	xcore_testct, // llvm.xcore.testct	xcore_testct, // llvm.xcore.testct
	xcore_testwct, // llvm.xcore.testwct	xcore_testwct, // llvm.xcore.testwct
	xcore_waitevent, // llvm.xcore.waitevent	xcore_waitevent, // llvm.xcore.waitevent
	xcore_zext // llvm.xcore.zext	xcore_zext // llvm.xcore.zext
	#endif	#endif

	// Intrinsic ID to name table	// Intrinsic ID to name table
	#ifdef GET_INTRINSIC_NAME_TABLE	#ifdef GET_INTRINSIC_NAME_TABLE
	// Note that entry #0 is the invalid intrinsic!	// Note that entry #0 is the invalid intrinsic!
	"llvm.adjust.trampoline",	"llvm.adjust.trampoline",

	"llvm.alpha.umulh",
	"llvm.annotation",	"llvm.annotation",
	"llvm.arm.cdp",	"llvm.arm.cdp",
	"llvm.arm.cdp2",	"llvm.arm.cdp2",
	"llvm.arm.get.fpscr",	"llvm.arm.get.fpscr",
	"llvm.arm.ldrexd",	"llvm.arm.ldrexd",
	"llvm.arm.mcr",	"llvm.arm.mcr",
	"llvm.arm.mcr2",	"llvm.arm.mcr2",
	"llvm.arm.mcrr",	"llvm.arm.mcrr",
	"llvm.arm.mcrr2",	"llvm.arm.mcrr2",
	"llvm.arm.mrc",	"llvm.arm.mrc",

	skipping to change at line 1136	skipping to change at line 2067
	"llvm.convertuif",	"llvm.convertuif",
	"llvm.convertus",	"llvm.convertus",
	"llvm.convertuu",	"llvm.convertuu",
	"llvm.cos",	"llvm.cos",
	"llvm.ctlz",	"llvm.ctlz",
	"llvm.ctpop",	"llvm.ctpop",
	"llvm.cttz",	"llvm.cttz",
	"llvm.dbg.declare",	"llvm.dbg.declare",
	"llvm.dbg.value",	"llvm.dbg.value",
	"llvm.eh.dwarf.cfa",	"llvm.eh.dwarf.cfa",

	"llvm.eh.exception",
	"llvm.eh.resume",
	"llvm.eh.return.i32",	"llvm.eh.return.i32",
	"llvm.eh.return.i64",	"llvm.eh.return.i64",

	"llvm.eh.selector",
	"llvm.eh.sjlj.callsite",	"llvm.eh.sjlj.callsite",

	"llvm.eh.sjlj.dispatch.setup",
	"llvm.eh.sjlj.functioncontext",	"llvm.eh.sjlj.functioncontext",
	"llvm.eh.sjlj.longjmp",	"llvm.eh.sjlj.longjmp",
	"llvm.eh.sjlj.lsda",	"llvm.eh.sjlj.lsda",
	"llvm.eh.sjlj.setjmp",	"llvm.eh.sjlj.setjmp",
	"llvm.eh.typeid.for",	"llvm.eh.typeid.for",
	"llvm.eh.unwind.init",	"llvm.eh.unwind.init",
	"llvm.exp",	"llvm.exp",
	"llvm.exp2",	"llvm.exp2",
	"llvm.expect",	"llvm.expect",
	"llvm.flt.rounds",	"llvm.flt.rounds",
	"llvm.fma",	"llvm.fma",
	"llvm.frameaddress",	"llvm.frameaddress",
	"llvm.gcread",	"llvm.gcread",
	"llvm.gcroot",	"llvm.gcroot",
	"llvm.gcwrite",	"llvm.gcwrite",

		"llvm.hexagon.A2.abs",
		"llvm.hexagon.A2.absp",
		"llvm.hexagon.A2.abssat",
		"llvm.hexagon.A2.add",
		"llvm.hexagon.A2.addh.h16.hh",
		"llvm.hexagon.A2.addh.h16.hl",
		"llvm.hexagon.A2.addh.h16.lh",
		"llvm.hexagon.A2.addh.h16.ll",
		"llvm.hexagon.A2.addh.h16.sat.hh",
		"llvm.hexagon.A2.addh.h16.sat.hl",
		"llvm.hexagon.A2.addh.h16.sat.lh",
		"llvm.hexagon.A2.addh.h16.sat.ll",
		"llvm.hexagon.A2.addh.l16.hh",
		"llvm.hexagon.A2.addh.l16.hl",
		"llvm.hexagon.A2.addh.l16.lh",
		"llvm.hexagon.A2.addh.l16.ll",
		"llvm.hexagon.A2.addh.l16.sat.hh",
		"llvm.hexagon.A2.addh.l16.sat.hl",
		"llvm.hexagon.A2.addh.l16.sat.lh",
		"llvm.hexagon.A2.addh.l16.sat.ll",
		"llvm.hexagon.A2.addi",
		"llvm.hexagon.A2.addp",
		"llvm.hexagon.A2.addpsat",
		"llvm.hexagon.A2.addsat",
		"llvm.hexagon.A2.addsp",
		"llvm.hexagon.A2.and",
		"llvm.hexagon.A2.andir",
		"llvm.hexagon.A2.andp",
		"llvm.hexagon.A2.aslh",
		"llvm.hexagon.A2.asrh",
		"llvm.hexagon.A2.combine.hh",
		"llvm.hexagon.A2.combine.hl",
		"llvm.hexagon.A2.combine.lh",
		"llvm.hexagon.A2.combine.ll",
		"llvm.hexagon.A2.combineii",
		"llvm.hexagon.A2.combinew",
		"llvm.hexagon.A2.max",
		"llvm.hexagon.A2.maxp",
		"llvm.hexagon.A2.maxu",
		"llvm.hexagon.A2.maxup",
		"llvm.hexagon.A2.min",
		"llvm.hexagon.A2.minp",
		"llvm.hexagon.A2.minu",
		"llvm.hexagon.A2.minup",
		"llvm.hexagon.A2.neg",
		"llvm.hexagon.A2.negp",
		"llvm.hexagon.A2.negsat",
		"llvm.hexagon.A2.not",
		"llvm.hexagon.A2.notp",
		"llvm.hexagon.A2.or",
		"llvm.hexagon.A2.orir",
		"llvm.hexagon.A2.orp",
		"llvm.hexagon.A2.sat",
		"llvm.hexagon.A2.satb",
		"llvm.hexagon.A2.sath",
		"llvm.hexagon.A2.satub",
		"llvm.hexagon.A2.satuh",
		"llvm.hexagon.A2.sub",
		"llvm.hexagon.A2.subh.h16.hh",
		"llvm.hexagon.A2.subh.h16.hl",
		"llvm.hexagon.A2.subh.h16.lh",
		"llvm.hexagon.A2.subh.h16.ll",
		"llvm.hexagon.A2.subh.h16.sat.hh",
		"llvm.hexagon.A2.subh.h16.sat.hl",
		"llvm.hexagon.A2.subh.h16.sat.lh",
		"llvm.hexagon.A2.subh.h16.sat.ll",
		"llvm.hexagon.A2.subh.l16.hl",
		"llvm.hexagon.A2.subh.l16.ll",
		"llvm.hexagon.A2.subh.l16.sat.hl",
		"llvm.hexagon.A2.subh.l16.sat.ll",
		"llvm.hexagon.A2.subp",
		"llvm.hexagon.A2.subri",
		"llvm.hexagon.A2.subsat",
		"llvm.hexagon.A2.svaddh",
		"llvm.hexagon.A2.svaddhs",
		"llvm.hexagon.A2.svadduhs",
		"llvm.hexagon.A2.svavgh",
		"llvm.hexagon.A2.svavghs",
		"llvm.hexagon.A2.svnavgh",
		"llvm.hexagon.A2.svsubh",
		"llvm.hexagon.A2.svsubhs",
		"llvm.hexagon.A2.svsubuhs",
		"llvm.hexagon.A2.swiz",
		"llvm.hexagon.A2.sxtb",
		"llvm.hexagon.A2.sxth",
		"llvm.hexagon.A2.sxtw",
		"llvm.hexagon.A2.tfr",
		"llvm.hexagon.A2.tfrih",
		"llvm.hexagon.A2.tfril",
		"llvm.hexagon.A2.tfrp",
		"llvm.hexagon.A2.tfrpi",
		"llvm.hexagon.A2.tfrsi",
		"llvm.hexagon.A2.vabsh",
		"llvm.hexagon.A2.vabshsat",
		"llvm.hexagon.A2.vabsw",
		"llvm.hexagon.A2.vabswsat",
		"llvm.hexagon.A2.vaddh",
		"llvm.hexagon.A2.vaddhs",
		"llvm.hexagon.A2.vaddub",
		"llvm.hexagon.A2.vaddubs",
		"llvm.hexagon.A2.vadduhs",
		"llvm.hexagon.A2.vaddw",
		"llvm.hexagon.A2.vaddws",
		"llvm.hexagon.A2.vavgh",
		"llvm.hexagon.A2.vavghcr",
		"llvm.hexagon.A2.vavghr",
		"llvm.hexagon.A2.vavgub",
		"llvm.hexagon.A2.vavgubr",
		"llvm.hexagon.A2.vavguh",
		"llvm.hexagon.A2.vavguhr",
		"llvm.hexagon.A2.vavguw",
		"llvm.hexagon.A2.vavguwr",
		"llvm.hexagon.A2.vavgw",
		"llvm.hexagon.A2.vavgwcr",
		"llvm.hexagon.A2.vavgwr",
		"llvm.hexagon.A2.vcmpbeq",
		"llvm.hexagon.A2.vcmpbgtu",
		"llvm.hexagon.A2.vcmpheq",
		"llvm.hexagon.A2.vcmphgt",
		"llvm.hexagon.A2.vcmphgtu",
		"llvm.hexagon.A2.vcmpweq",
		"llvm.hexagon.A2.vcmpwgt",
		"llvm.hexagon.A2.vcmpwgtu",
		"llvm.hexagon.A2.vconj",
		"llvm.hexagon.A2.vmaxh",
		"llvm.hexagon.A2.vmaxub",
		"llvm.hexagon.A2.vmaxuh",
		"llvm.hexagon.A2.vmaxuw",
		"llvm.hexagon.A2.vmaxw",
		"llvm.hexagon.A2.vminh",
		"llvm.hexagon.A2.vminub",
		"llvm.hexagon.A2.vminuh",
		"llvm.hexagon.A2.vminuw",
		"llvm.hexagon.A2.vminw",
		"llvm.hexagon.A2.vnavgh",
		"llvm.hexagon.A2.vnavghcr",
		"llvm.hexagon.A2.vnavghr",
		"llvm.hexagon.A2.vnavgw",
		"llvm.hexagon.A2.vnavgwcr",
		"llvm.hexagon.A2.vnavgwr",
		"llvm.hexagon.A2.vraddub",
		"llvm.hexagon.A2.vraddub.acc",
		"llvm.hexagon.A2.vrsadub",
		"llvm.hexagon.A2.vrsadub.acc",
		"llvm.hexagon.A2.vsubh",
		"llvm.hexagon.A2.vsubhs",
		"llvm.hexagon.A2.vsubub",
		"llvm.hexagon.A2.vsububs",
		"llvm.hexagon.A2.vsubuhs",
		"llvm.hexagon.A2.vsubw",
		"llvm.hexagon.A2.vsubws",
		"llvm.hexagon.A2.xor",
		"llvm.hexagon.A2.xorp",
		"llvm.hexagon.A2.zxtb",
		"llvm.hexagon.A2.zxth",
		"llvm.hexagon.A4.andn",
		"llvm.hexagon.A4.andnp",
		"llvm.hexagon.A4.combineir",
		"llvm.hexagon.A4.combineri",
		"llvm.hexagon.A4.cround.ri",
		"llvm.hexagon.A4.cround.rr",
		"llvm.hexagon.A4.modwrapu",
		"llvm.hexagon.A4.orn",
		"llvm.hexagon.A4.ornp",
		"llvm.hexagon.A4.rcmpeq",
		"llvm.hexagon.A4.rcmpeqi",
		"llvm.hexagon.A4.rcmpneq",
		"llvm.hexagon.A4.rcmpneqi",
		"llvm.hexagon.A4.round.ri",
		"llvm.hexagon.A4.round.ri.sat",
		"llvm.hexagon.A4.round.rr",
		"llvm.hexagon.A4.round.rr.sat",
		"llvm.hexagon.C2.all8",
		"llvm.hexagon.C2.and",
		"llvm.hexagon.C2.andn",
		"llvm.hexagon.C2.any8",
		"llvm.hexagon.C2.bitsclr",
		"llvm.hexagon.C2.bitsclri",
		"llvm.hexagon.C2.bitsset",
		"llvm.hexagon.C2.cmpeq",
		"llvm.hexagon.C2.cmpeqi",
		"llvm.hexagon.C2.cmpeqp",
		"llvm.hexagon.C2.cmpgei",
		"llvm.hexagon.C2.cmpgeui",
		"llvm.hexagon.C2.cmpgt",
		"llvm.hexagon.C2.cmpgti",
		"llvm.hexagon.C2.cmpgtp",
		"llvm.hexagon.C2.cmpgtu",
		"llvm.hexagon.C2.cmpgtui",
		"llvm.hexagon.C2.cmpgtup",
		"llvm.hexagon.C2.cmplt",
		"llvm.hexagon.C2.cmpltu",
		"llvm.hexagon.C2.mask",
		"llvm.hexagon.C2.mux",
		"llvm.hexagon.C2.muxii",
		"llvm.hexagon.C2.muxir",
		"llvm.hexagon.C2.muxri",
		"llvm.hexagon.C2.not",
		"llvm.hexagon.C2.or",
		"llvm.hexagon.C2.orn",
		"llvm.hexagon.C2.pxfer.map",
		"llvm.hexagon.C2.tfrpr",
		"llvm.hexagon.C2.tfrrp",
		"llvm.hexagon.C2.vitpack",
		"llvm.hexagon.C2.vmux",
		"llvm.hexagon.C2.xor",
		"llvm.hexagon.C4.and.and",
		"llvm.hexagon.C4.and.andn",
		"llvm.hexagon.C4.and.or",
		"llvm.hexagon.C4.and.orn",
		"llvm.hexagon.C4.cmplte",
		"llvm.hexagon.C4.cmpltei",
		"llvm.hexagon.C4.cmplteu",
		"llvm.hexagon.C4.cmplteui",
		"llvm.hexagon.C4.cmpneq",
		"llvm.hexagon.C4.cmpneqi",
		"llvm.hexagon.C4.fastcorner9",
		"llvm.hexagon.C4.fastcorner9.not",
		"llvm.hexagon.C4.or.and",
		"llvm.hexagon.C4.or.andn",
		"llvm.hexagon.C4.or.or",
		"llvm.hexagon.C4.or.orn",
		"llvm.hexagon.M2.acci",
		"llvm.hexagon.M2.accii",
		"llvm.hexagon.M2.cmaci.s0",
		"llvm.hexagon.M2.cmacr.s0",
		"llvm.hexagon.M2.cmacs.s0",
		"llvm.hexagon.M2.cmacs.s1",
		"llvm.hexagon.M2.cmacsc.s0",
		"llvm.hexagon.M2.cmacsc.s1",
		"llvm.hexagon.M2.cmpyi.s0",
		"llvm.hexagon.M2.cmpyr.s0",
		"llvm.hexagon.M2.cmpyrs.s0",
		"llvm.hexagon.M2.cmpyrs.s1",
		"llvm.hexagon.M2.cmpyrsc.s0",
		"llvm.hexagon.M2.cmpyrsc.s1",
		"llvm.hexagon.M2.cmpys.s0",
		"llvm.hexagon.M2.cmpys.s1",
		"llvm.hexagon.M2.cmpysc.s0",
		"llvm.hexagon.M2.cmpysc.s1",
		"llvm.hexagon.M2.cnacs.s0",
		"llvm.hexagon.M2.cnacs.s1",
		"llvm.hexagon.M2.cnacsc.s0",
		"llvm.hexagon.M2.cnacsc.s1",
		"llvm.hexagon.M2.dpmpyss.acc.s0",
		"llvm.hexagon.M2.dpmpyss.nac.s0",
		"llvm.hexagon.M2.dpmpyss.rnd.s0",
		"llvm.hexagon.M2.dpmpyss.s0",
		"llvm.hexagon.M2.dpmpyuu.acc.s0",
		"llvm.hexagon.M2.dpmpyuu.nac.s0",
		"llvm.hexagon.M2.dpmpyuu.s0",
		"llvm.hexagon.M2.hmmpyh.rs1",
		"llvm.hexagon.M2.hmmpyl.rs1",
		"llvm.hexagon.M2.maci",
		"llvm.hexagon.M2.macsin",
		"llvm.hexagon.M2.macsip",
		"llvm.hexagon.M2.mmachs.rs0",
		"llvm.hexagon.M2.mmachs.rs1",
		"llvm.hexagon.M2.mmachs.s0",
		"llvm.hexagon.M2.mmachs.s1",
		"llvm.hexagon.M2.mmacls.rs0",
		"llvm.hexagon.M2.mmacls.rs1",
		"llvm.hexagon.M2.mmacls.s0",
		"llvm.hexagon.M2.mmacls.s1",
		"llvm.hexagon.M2.mmacuhs.rs0",
		"llvm.hexagon.M2.mmacuhs.rs1",
		"llvm.hexagon.M2.mmacuhs.s0",
		"llvm.hexagon.M2.mmacuhs.s1",
		"llvm.hexagon.M2.mmaculs.rs0",
		"llvm.hexagon.M2.mmaculs.rs1",
		"llvm.hexagon.M2.mmaculs.s0",
		"llvm.hexagon.M2.mmaculs.s1",
		"llvm.hexagon.M2.mmpyh.rs0",
		"llvm.hexagon.M2.mmpyh.rs1",
		"llvm.hexagon.M2.mmpyh.s0",
		"llvm.hexagon.M2.mmpyh.s1",
		"llvm.hexagon.M2.mmpyl.rs0",
		"llvm.hexagon.M2.mmpyl.rs1",
		"llvm.hexagon.M2.mmpyl.s0",
		"llvm.hexagon.M2.mmpyl.s1",
		"llvm.hexagon.M2.mmpyuh.rs0",
		"llvm.hexagon.M2.mmpyuh.rs1",
		"llvm.hexagon.M2.mmpyuh.s0",
		"llvm.hexagon.M2.mmpyuh.s1",
		"llvm.hexagon.M2.mmpyul.rs0",
		"llvm.hexagon.M2.mmpyul.rs1",
		"llvm.hexagon.M2.mmpyul.s0",
		"llvm.hexagon.M2.mmpyul.s1",
		"llvm.hexagon.M2.mpy.acc.hh.s0",
		"llvm.hexagon.M2.mpy.acc.hh.s1",
		"llvm.hexagon.M2.mpy.acc.hl.s0",
		"llvm.hexagon.M2.mpy.acc.hl.s1",
		"llvm.hexagon.M2.mpy.acc.lh.s0",
		"llvm.hexagon.M2.mpy.acc.lh.s1",
		"llvm.hexagon.M2.mpy.acc.ll.s0",
		"llvm.hexagon.M2.mpy.acc.ll.s1",
		"llvm.hexagon.M2.mpy.acc.sat.hh.s0",
		"llvm.hexagon.M2.mpy.acc.sat.hh.s1",
		"llvm.hexagon.M2.mpy.acc.sat.hl.s0",
		"llvm.hexagon.M2.mpy.acc.sat.hl.s1",
		"llvm.hexagon.M2.mpy.acc.sat.lh.s0",
		"llvm.hexagon.M2.mpy.acc.sat.lh.s1",
		"llvm.hexagon.M2.mpy.acc.sat.ll.s0",
		"llvm.hexagon.M2.mpy.acc.sat.ll.s1",
		"llvm.hexagon.M2.mpy.hh.s0",
		"llvm.hexagon.M2.mpy.hh.s1",
		"llvm.hexagon.M2.mpy.hl.s0",
		"llvm.hexagon.M2.mpy.hl.s1",
		"llvm.hexagon.M2.mpy.lh.s0",
		"llvm.hexagon.M2.mpy.lh.s1",
		"llvm.hexagon.M2.mpy.ll.s0",
		"llvm.hexagon.M2.mpy.ll.s1",
		"llvm.hexagon.M2.mpy.nac.hh.s0",
		"llvm.hexagon.M2.mpy.nac.hh.s1",
		"llvm.hexagon.M2.mpy.nac.hl.s0",
		"llvm.hexagon.M2.mpy.nac.hl.s1",
		"llvm.hexagon.M2.mpy.nac.lh.s0",
		"llvm.hexagon.M2.mpy.nac.lh.s1",
		"llvm.hexagon.M2.mpy.nac.ll.s0",
		"llvm.hexagon.M2.mpy.nac.ll.s1",
		"llvm.hexagon.M2.mpy.nac.sat.hh.s0",
		"llvm.hexagon.M2.mpy.nac.sat.hh.s1",
		"llvm.hexagon.M2.mpy.nac.sat.hl.s0",
		"llvm.hexagon.M2.mpy.nac.sat.hl.s1",
		"llvm.hexagon.M2.mpy.nac.sat.lh.s0",
		"llvm.hexagon.M2.mpy.nac.sat.lh.s1",
		"llvm.hexagon.M2.mpy.nac.sat.ll.s0",
		"llvm.hexagon.M2.mpy.nac.sat.ll.s1",
		"llvm.hexagon.M2.mpy.rnd.hh.s0",
		"llvm.hexagon.M2.mpy.rnd.hh.s1",
		"llvm.hexagon.M2.mpy.rnd.hl.s0",
		"llvm.hexagon.M2.mpy.rnd.hl.s1",
		"llvm.hexagon.M2.mpy.rnd.lh.s0",
		"llvm.hexagon.M2.mpy.rnd.lh.s1",
		"llvm.hexagon.M2.mpy.rnd.ll.s0",
		"llvm.hexagon.M2.mpy.rnd.ll.s1",
		"llvm.hexagon.M2.mpy.sat.hh.s0",
		"llvm.hexagon.M2.mpy.sat.hh.s1",
		"llvm.hexagon.M2.mpy.sat.hl.s0",
		"llvm.hexagon.M2.mpy.sat.hl.s1",
		"llvm.hexagon.M2.mpy.sat.lh.s0",
		"llvm.hexagon.M2.mpy.sat.lh.s1",
		"llvm.hexagon.M2.mpy.sat.ll.s0",
		"llvm.hexagon.M2.mpy.sat.ll.s1",
		"llvm.hexagon.M2.mpy.sat.rnd.hh.s0",
		"llvm.hexagon.M2.mpy.sat.rnd.hh.s1",
		"llvm.hexagon.M2.mpy.sat.rnd.hl.s0",
		"llvm.hexagon.M2.mpy.sat.rnd.hl.s1",
		"llvm.hexagon.M2.mpy.sat.rnd.lh.s0",
		"llvm.hexagon.M2.mpy.sat.rnd.lh.s1",
		"llvm.hexagon.M2.mpy.sat.rnd.ll.s0",
		"llvm.hexagon.M2.mpy.sat.rnd.ll.s1",
		"llvm.hexagon.M2.mpy.up",
		"llvm.hexagon.M2.mpyd.acc.hh.s0",
		"llvm.hexagon.M2.mpyd.acc.hh.s1",
		"llvm.hexagon.M2.mpyd.acc.hl.s0",
		"llvm.hexagon.M2.mpyd.acc.hl.s1",
		"llvm.hexagon.M2.mpyd.acc.lh.s0",
		"llvm.hexagon.M2.mpyd.acc.lh.s1",
		"llvm.hexagon.M2.mpyd.acc.ll.s0",
		"llvm.hexagon.M2.mpyd.acc.ll.s1",
		"llvm.hexagon.M2.mpyd.hh.s0",
		"llvm.hexagon.M2.mpyd.hh.s1",
		"llvm.hexagon.M2.mpyd.hl.s0",
		"llvm.hexagon.M2.mpyd.hl.s1",
		"llvm.hexagon.M2.mpyd.lh.s0",
		"llvm.hexagon.M2.mpyd.lh.s1",
		"llvm.hexagon.M2.mpyd.ll.s0",
		"llvm.hexagon.M2.mpyd.ll.s1",
		"llvm.hexagon.M2.mpyd.nac.hh.s0",
		"llvm.hexagon.M2.mpyd.nac.hh.s1",
		"llvm.hexagon.M2.mpyd.nac.hl.s0",
		"llvm.hexagon.M2.mpyd.nac.hl.s1",
		"llvm.hexagon.M2.mpyd.nac.lh.s0",
		"llvm.hexagon.M2.mpyd.nac.lh.s1",
		"llvm.hexagon.M2.mpyd.nac.ll.s0",
		"llvm.hexagon.M2.mpyd.nac.ll.s1",
		"llvm.hexagon.M2.mpyd.rnd.hh.s0",
		"llvm.hexagon.M2.mpyd.rnd.hh.s1",
		"llvm.hexagon.M2.mpyd.rnd.hl.s0",
		"llvm.hexagon.M2.mpyd.rnd.hl.s1",
		"llvm.hexagon.M2.mpyd.rnd.lh.s0",
		"llvm.hexagon.M2.mpyd.rnd.lh.s1",
		"llvm.hexagon.M2.mpyd.rnd.ll.s0",
		"llvm.hexagon.M2.mpyd.rnd.ll.s1",
		"llvm.hexagon.M2.mpyi",
		"llvm.hexagon.M2.mpysmi",
		"llvm.hexagon.M2.mpyu.acc.hh.s0",
		"llvm.hexagon.M2.mpyu.acc.hh.s1",
		"llvm.hexagon.M2.mpyu.acc.hl.s0",
		"llvm.hexagon.M2.mpyu.acc.hl.s1",
		"llvm.hexagon.M2.mpyu.acc.lh.s0",
		"llvm.hexagon.M2.mpyu.acc.lh.s1",
		"llvm.hexagon.M2.mpyu.acc.ll.s0",
		"llvm.hexagon.M2.mpyu.acc.ll.s1",
		"llvm.hexagon.M2.mpyu.hh.s0",
		"llvm.hexagon.M2.mpyu.hh.s1",
		"llvm.hexagon.M2.mpyu.hl.s0",
		"llvm.hexagon.M2.mpyu.hl.s1",
		"llvm.hexagon.M2.mpyu.lh.s0",
		"llvm.hexagon.M2.mpyu.lh.s1",
		"llvm.hexagon.M2.mpyu.ll.s0",
		"llvm.hexagon.M2.mpyu.ll.s1",
		"llvm.hexagon.M2.mpyu.nac.hh.s0",
		"llvm.hexagon.M2.mpyu.nac.hh.s1",
		"llvm.hexagon.M2.mpyu.nac.hl.s0",
		"llvm.hexagon.M2.mpyu.nac.hl.s1",
		"llvm.hexagon.M2.mpyu.nac.lh.s0",
		"llvm.hexagon.M2.mpyu.nac.lh.s1",
		"llvm.hexagon.M2.mpyu.nac.ll.s0",
		"llvm.hexagon.M2.mpyu.nac.ll.s1",
		"llvm.hexagon.M2.mpyu.up",
		"llvm.hexagon.M2.mpyud.acc.hh.s0",
		"llvm.hexagon.M2.mpyud.acc.hh.s1",
		"llvm.hexagon.M2.mpyud.acc.hl.s0",
		"llvm.hexagon.M2.mpyud.acc.hl.s1",
		"llvm.hexagon.M2.mpyud.acc.lh.s0",
		"llvm.hexagon.M2.mpyud.acc.lh.s1",
		"llvm.hexagon.M2.mpyud.acc.ll.s0",
		"llvm.hexagon.M2.mpyud.acc.ll.s1",
		"llvm.hexagon.M2.mpyud.hh.s0",
		"llvm.hexagon.M2.mpyud.hh.s1",
		"llvm.hexagon.M2.mpyud.hl.s0",
		"llvm.hexagon.M2.mpyud.hl.s1",
		"llvm.hexagon.M2.mpyud.lh.s0",
		"llvm.hexagon.M2.mpyud.lh.s1",
		"llvm.hexagon.M2.mpyud.ll.s0",
		"llvm.hexagon.M2.mpyud.ll.s1",
		"llvm.hexagon.M2.mpyud.nac.hh.s0",
		"llvm.hexagon.M2.mpyud.nac.hh.s1",
		"llvm.hexagon.M2.mpyud.nac.hl.s0",
		"llvm.hexagon.M2.mpyud.nac.hl.s1",
		"llvm.hexagon.M2.mpyud.nac.lh.s0",
		"llvm.hexagon.M2.mpyud.nac.lh.s1",
		"llvm.hexagon.M2.mpyud.nac.ll.s0",
		"llvm.hexagon.M2.mpyud.nac.ll.s1",
		"llvm.hexagon.M2.mpyui",
		"llvm.hexagon.M2.nacci",
		"llvm.hexagon.M2.naccii",
		"llvm.hexagon.M2.subacc",
		"llvm.hexagon.M2.vabsdiffh",
		"llvm.hexagon.M2.vabsdiffw",
		"llvm.hexagon.M2.vcmac.s0.sat.i",
		"llvm.hexagon.M2.vcmac.s0.sat.r",
		"llvm.hexagon.M2.vcmpy.s0.sat.i",
		"llvm.hexagon.M2.vcmpy.s0.sat.r",
		"llvm.hexagon.M2.vcmpy.s1.sat.i",
		"llvm.hexagon.M2.vcmpy.s1.sat.r",
		"llvm.hexagon.M2.vdmacs.s0",
		"llvm.hexagon.M2.vdmacs.s1",
		"llvm.hexagon.M2.vdmpyrs.s0",
		"llvm.hexagon.M2.vdmpyrs.s1",
		"llvm.hexagon.M2.vdmpys.s0",
		"llvm.hexagon.M2.vdmpys.s1",
		"llvm.hexagon.M2.vmac2",
		"llvm.hexagon.M2.vmac2es",
		"llvm.hexagon.M2.vmac2es.s0",
		"llvm.hexagon.M2.vmac2es.s1",
		"llvm.hexagon.M2.vmac2s.s0",
		"llvm.hexagon.M2.vmac2s.s1",
		"llvm.hexagon.M2.vmpy2es.s0",
		"llvm.hexagon.M2.vmpy2es.s1",
		"llvm.hexagon.M2.vmpy2s.s0",
		"llvm.hexagon.M2.vmpy2s.s0pack",
		"llvm.hexagon.M2.vmpy2s.s1",
		"llvm.hexagon.M2.vmpy2s.s1pack",
		"llvm.hexagon.M2.vradduh",
		"llvm.hexagon.M2.vrcmaci.s0",
		"llvm.hexagon.M2.vrcmaci.s0c",
		"llvm.hexagon.M2.vrcmacr.s0",
		"llvm.hexagon.M2.vrcmacr.s0c",
		"llvm.hexagon.M2.vrcmpyi.s0",
		"llvm.hexagon.M2.vrcmpyi.s0c",
		"llvm.hexagon.M2.vrcmpyr.s0",
		"llvm.hexagon.M2.vrcmpyr.s0c",
		"llvm.hexagon.M2.vrcmpys.acc.s1",
		"llvm.hexagon.M2.vrcmpys.s1",
		"llvm.hexagon.M2.vrcmpys.s1rp",
		"llvm.hexagon.M2.vrmac.s0",
		"llvm.hexagon.M2.vrmpy.s0",
		"llvm.hexagon.M2.xor.xacc",
		"llvm.hexagon.M4.and.and",
		"llvm.hexagon.M4.and.andn",
		"llvm.hexagon.M4.and.or",
		"llvm.hexagon.M4.and.xor",
		"llvm.hexagon.M4.or.and",
		"llvm.hexagon.M4.or.andn",
		"llvm.hexagon.M4.or.or",
		"llvm.hexagon.M4.or.xor",
		"llvm.hexagon.M4.xor.and",
		"llvm.hexagon.M4.xor.andn",
		"llvm.hexagon.M4.xor.or",
		"llvm.hexagon.M4.xor.xacc",
		"llvm.hexagon.S2.addasl.rrri",
		"llvm.hexagon.S2.asl.i.p",
		"llvm.hexagon.S2.asl.i.p.acc",
		"llvm.hexagon.S2.asl.i.p.and",
		"llvm.hexagon.S2.asl.i.p.nac",
		"llvm.hexagon.S2.asl.i.p.or",
		"llvm.hexagon.S2.asl.i.p.xacc",
		"llvm.hexagon.S2.asl.i.r",
		"llvm.hexagon.S2.asl.i.r.acc",
		"llvm.hexagon.S2.asl.i.r.and",
		"llvm.hexagon.S2.asl.i.r.nac",
		"llvm.hexagon.S2.asl.i.r.or",
		"llvm.hexagon.S2.asl.i.r.sat",
		"llvm.hexagon.S2.asl.i.r.xacc",
		"llvm.hexagon.S2.asl.i.vh",
		"llvm.hexagon.S2.asl.i.vw",
		"llvm.hexagon.S2.asl.r.p",
		"llvm.hexagon.S2.asl.r.p.acc",
		"llvm.hexagon.S2.asl.r.p.and",
		"llvm.hexagon.S2.asl.r.p.nac",
		"llvm.hexagon.S2.asl.r.p.or",
		"llvm.hexagon.S2.asl.r.r",
		"llvm.hexagon.S2.asl.r.r.acc",
		"llvm.hexagon.S2.asl.r.r.and",
		"llvm.hexagon.S2.asl.r.r.nac",
		"llvm.hexagon.S2.asl.r.r.or",
		"llvm.hexagon.S2.asl.r.r.sat",
		"llvm.hexagon.S2.asl.r.vh",
		"llvm.hexagon.S2.asl.r.vw",
		"llvm.hexagon.S2.asr.i.p",
		"llvm.hexagon.S2.asr.i.p.acc",
		"llvm.hexagon.S2.asr.i.p.and",
		"llvm.hexagon.S2.asr.i.p.nac",
		"llvm.hexagon.S2.asr.i.p.or",
		"llvm.hexagon.S2.asr.i.r",
		"llvm.hexagon.S2.asr.i.r.acc",
		"llvm.hexagon.S2.asr.i.r.and",
		"llvm.hexagon.S2.asr.i.r.nac",
		"llvm.hexagon.S2.asr.i.r.or",
		"llvm.hexagon.S2.asr.i.r.rnd",
		"llvm.hexagon.S2.asr.i.r.rnd.goodsyntax",
		"llvm.hexagon.S2.asr.i.svw.trun",
		"llvm.hexagon.S2.asr.i.vh",
		"llvm.hexagon.S2.asr.i.vw",
		"llvm.hexagon.S2.asr.r.p",
		"llvm.hexagon.S2.asr.r.p.acc",
		"llvm.hexagon.S2.asr.r.p.and",
		"llvm.hexagon.S2.asr.r.p.nac",
		"llvm.hexagon.S2.asr.r.p.or",
		"llvm.hexagon.S2.asr.r.r",
		"llvm.hexagon.S2.asr.r.r.acc",
		"llvm.hexagon.S2.asr.r.r.and",
		"llvm.hexagon.S2.asr.r.r.nac",
		"llvm.hexagon.S2.asr.r.r.or",
		"llvm.hexagon.S2.asr.r.r.sat",
		"llvm.hexagon.S2.asr.r.svw.trun",
		"llvm.hexagon.S2.asr.r.vh",
		"llvm.hexagon.S2.asr.r.vw",
		"llvm.hexagon.S2.brev",
		"llvm.hexagon.S2.cl0",
		"llvm.hexagon.S2.cl0p",
		"llvm.hexagon.S2.cl1",
		"llvm.hexagon.S2.cl1p",
		"llvm.hexagon.S2.clb",
		"llvm.hexagon.S2.clbnorm",
		"llvm.hexagon.S2.clbp",
		"llvm.hexagon.S2.clrbit.i",
		"llvm.hexagon.S2.clrbit.r",
		"llvm.hexagon.S2.ct0",
		"llvm.hexagon.S2.ct1",
		"llvm.hexagon.S2.deinterleave",
		"llvm.hexagon.S2.extractu",
		"llvm.hexagon.S2.extractu.rp",
		"llvm.hexagon.S2.extractup",
		"llvm.hexagon.S2.extractup.rp",
		"llvm.hexagon.S2.insert",
		"llvm.hexagon.S2.insert.rp",
		"llvm.hexagon.S2.insertp",
		"llvm.hexagon.S2.insertp.rp",
		"llvm.hexagon.S2.interleave",
		"llvm.hexagon.S2.lfsp",
		"llvm.hexagon.S2.lsl.r.p",
		"llvm.hexagon.S2.lsl.r.p.acc",
		"llvm.hexagon.S2.lsl.r.p.and",
		"llvm.hexagon.S2.lsl.r.p.nac",
		"llvm.hexagon.S2.lsl.r.p.or",
		"llvm.hexagon.S2.lsl.r.r",
		"llvm.hexagon.S2.lsl.r.r.acc",
		"llvm.hexagon.S2.lsl.r.r.and",
		"llvm.hexagon.S2.lsl.r.r.nac",
		"llvm.hexagon.S2.lsl.r.r.or",
		"llvm.hexagon.S2.lsl.r.vh",
		"llvm.hexagon.S2.lsl.r.vw",
		"llvm.hexagon.S2.lsr.i.p",
		"llvm.hexagon.S2.lsr.i.p.acc",
		"llvm.hexagon.S2.lsr.i.p.and",
		"llvm.hexagon.S2.lsr.i.p.nac",
		"llvm.hexagon.S2.lsr.i.p.or",
		"llvm.hexagon.S2.lsr.i.p.xacc",
		"llvm.hexagon.S2.lsr.i.r",
		"llvm.hexagon.S2.lsr.i.r.acc",
		"llvm.hexagon.S2.lsr.i.r.and",
		"llvm.hexagon.S2.lsr.i.r.nac",
		"llvm.hexagon.S2.lsr.i.r.or",
		"llvm.hexagon.S2.lsr.i.r.xacc",
		"llvm.hexagon.S2.lsr.i.vh",
		"llvm.hexagon.S2.lsr.i.vw",
		"llvm.hexagon.S2.lsr.r.p",
		"llvm.hexagon.S2.lsr.r.p.acc",
		"llvm.hexagon.S2.lsr.r.p.and",
		"llvm.hexagon.S2.lsr.r.p.nac",
		"llvm.hexagon.S2.lsr.r.p.or",
		"llvm.hexagon.S2.lsr.r.r",
		"llvm.hexagon.S2.lsr.r.r.acc",
		"llvm.hexagon.S2.lsr.r.r.and",
		"llvm.hexagon.S2.lsr.r.r.nac",
		"llvm.hexagon.S2.lsr.r.r.or",
		"llvm.hexagon.S2.lsr.r.vh",
		"llvm.hexagon.S2.lsr.r.vw",
		"llvm.hexagon.S2.packhl",
		"llvm.hexagon.S2.parityp",
		"llvm.hexagon.S2.setbit.i",
		"llvm.hexagon.S2.setbit.r",
		"llvm.hexagon.S2.shuffeb",
		"llvm.hexagon.S2.shuffeh",
		"llvm.hexagon.S2.shuffob",
		"llvm.hexagon.S2.shuffoh",
		"llvm.hexagon.S2.svsathb",
		"llvm.hexagon.S2.svsathub",
		"llvm.hexagon.S2.tableidxb.goodsyntax",
		"llvm.hexagon.S2.tableidxd.goodsyntax",
		"llvm.hexagon.S2.tableidxh.goodsyntax",
		"llvm.hexagon.S2.tableidxw.goodsyntax",
		"llvm.hexagon.S2.togglebit.i",
		"llvm.hexagon.S2.togglebit.r",
		"llvm.hexagon.S2.tstbit.i",
		"llvm.hexagon.S2.tstbit.r",
		"llvm.hexagon.S2.valignib",
		"llvm.hexagon.S2.valignrb",
		"llvm.hexagon.S2.vcrotate",
		"llvm.hexagon.S2.vrndpackwh",
		"llvm.hexagon.S2.vrndpackwhs",
		"llvm.hexagon.S2.vsathb",
		"llvm.hexagon.S2.vsathb.nopack",
		"llvm.hexagon.S2.vsathub",
		"llvm.hexagon.S2.vsathub.nopack",
		"llvm.hexagon.S2.vsatwh",
		"llvm.hexagon.S2.vsatwh.nopack",
		"llvm.hexagon.S2.vsatwuh",
		"llvm.hexagon.S2.vsatwuh.nopack",
		"llvm.hexagon.S2.vsplatrb",
		"llvm.hexagon.S2.vsplatrh",
		"llvm.hexagon.S2.vspliceib",
		"llvm.hexagon.S2.vsplicerb",
		"llvm.hexagon.S2.vsxtbh",
		"llvm.hexagon.S2.vsxthw",
		"llvm.hexagon.S2.vtrunehb",
		"llvm.hexagon.S2.vtrunewh",
		"llvm.hexagon.S2.vtrunohb",
		"llvm.hexagon.S2.vtrunowh",
		"llvm.hexagon.S2.vzxtbh",
		"llvm.hexagon.S2.vzxthw",
		"llvm.hexagon.S4.addaddi",
		"llvm.hexagon.S4.andnp",
		"llvm.hexagon.S4.or.andi",
		"llvm.hexagon.S4.or.andix",
		"llvm.hexagon.S4.or.ori",
		"llvm.hexagon.S4.ornp",
		"llvm.hexagon.S4.subaddi",
		"llvm.hexagon.SI.to.SXTHI.asrh",
	"llvm.init.trampoline",	"llvm.init.trampoline",
	"llvm.invariant.end",	"llvm.invariant.end",
	"llvm.invariant.start",	"llvm.invariant.start",
	"llvm.lifetime.end",	"llvm.lifetime.end",
	"llvm.lifetime.start",	"llvm.lifetime.start",
	"llvm.log",	"llvm.log",
	"llvm.log10",	"llvm.log10",
	"llvm.log2",	"llvm.log2",
	"llvm.longjmp",	"llvm.longjmp",
	"llvm.memcpy",	"llvm.memcpy",

	skipping to change at line 1499	skipping to change at line 3089
	"llvm.x86.3dnowa.pfnacc",	"llvm.x86.3dnowa.pfnacc",
	"llvm.x86.3dnowa.pfpnacc",	"llvm.x86.3dnowa.pfpnacc",
	"llvm.x86.3dnowa.pi2fw",	"llvm.x86.3dnowa.pi2fw",
	"llvm.x86.3dnowa.pswapd",	"llvm.x86.3dnowa.pswapd",
	"llvm.x86.aesni.aesdec",	"llvm.x86.aesni.aesdec",
	"llvm.x86.aesni.aesdeclast",	"llvm.x86.aesni.aesdeclast",
	"llvm.x86.aesni.aesenc",	"llvm.x86.aesni.aesenc",
	"llvm.x86.aesni.aesenclast",	"llvm.x86.aesni.aesenclast",
	"llvm.x86.aesni.aesimc",	"llvm.x86.aesni.aesimc",
	"llvm.x86.aesni.aeskeygenassist",	"llvm.x86.aesni.aeskeygenassist",

		"llvm.x86.avx2.maskload.d",
		"llvm.x86.avx2.maskload.d.256",
		"llvm.x86.avx2.maskload.q",
		"llvm.x86.avx2.maskload.q.256",
		"llvm.x86.avx2.maskstore.d",
		"llvm.x86.avx2.maskstore.d.256",
		"llvm.x86.avx2.maskstore.q",
		"llvm.x86.avx2.maskstore.q.256",
		"llvm.x86.avx2.movntdqa",
		"llvm.x86.avx2.mpsadbw",
		"llvm.x86.avx2.pabs.b",
		"llvm.x86.avx2.pabs.d",
		"llvm.x86.avx2.pabs.w",
		"llvm.x86.avx2.packssdw",
		"llvm.x86.avx2.packsswb",
		"llvm.x86.avx2.packusdw",
		"llvm.x86.avx2.packuswb",
		"llvm.x86.avx2.padds.b",
		"llvm.x86.avx2.padds.w",
		"llvm.x86.avx2.paddus.b",
		"llvm.x86.avx2.paddus.w",
		"llvm.x86.avx2.pavg.b",
		"llvm.x86.avx2.pavg.w",
		"llvm.x86.avx2.pblendd.128",
		"llvm.x86.avx2.pblendd.256",
		"llvm.x86.avx2.pblendvb",
		"llvm.x86.avx2.pblendw",
		"llvm.x86.avx2.pbroadcastb.128",
		"llvm.x86.avx2.pbroadcastb.256",
		"llvm.x86.avx2.pbroadcastd.128",
		"llvm.x86.avx2.pbroadcastd.256",
		"llvm.x86.avx2.pbroadcastq.128",
		"llvm.x86.avx2.pbroadcastq.256",
		"llvm.x86.avx2.pbroadcastw.128",
		"llvm.x86.avx2.pbroadcastw.256",
		"llvm.x86.avx2.permd",
		"llvm.x86.avx2.permps",
		"llvm.x86.avx2.phadd.d",
		"llvm.x86.avx2.phadd.sw",
		"llvm.x86.avx2.phadd.w",
		"llvm.x86.avx2.phsub.d",
		"llvm.x86.avx2.phsub.sw",
		"llvm.x86.avx2.phsub.w",
		"llvm.x86.avx2.pmadd.ub.sw",
		"llvm.x86.avx2.pmadd.wd",
		"llvm.x86.avx2.pmaxs.b",
		"llvm.x86.avx2.pmaxs.d",
		"llvm.x86.avx2.pmaxs.w",
		"llvm.x86.avx2.pmaxu.b",
		"llvm.x86.avx2.pmaxu.d",
		"llvm.x86.avx2.pmaxu.w",
		"llvm.x86.avx2.pmins.b",
		"llvm.x86.avx2.pmins.d",
		"llvm.x86.avx2.pmins.w",
		"llvm.x86.avx2.pminu.b",
		"llvm.x86.avx2.pminu.d",
		"llvm.x86.avx2.pminu.w",
		"llvm.x86.avx2.pmovmskb",
		"llvm.x86.avx2.pmovsxbd",
		"llvm.x86.avx2.pmovsxbq",
		"llvm.x86.avx2.pmovsxbw",
		"llvm.x86.avx2.pmovsxdq",
		"llvm.x86.avx2.pmovsxwd",
		"llvm.x86.avx2.pmovsxwq",
		"llvm.x86.avx2.pmovzxbd",
		"llvm.x86.avx2.pmovzxbq",
		"llvm.x86.avx2.pmovzxbw",
		"llvm.x86.avx2.pmovzxdq",
		"llvm.x86.avx2.pmovzxwd",
		"llvm.x86.avx2.pmovzxwq",
		"llvm.x86.avx2.pmul.dq",
		"llvm.x86.avx2.pmul.hr.sw",
		"llvm.x86.avx2.pmulh.w",
		"llvm.x86.avx2.pmulhu.w",
		"llvm.x86.avx2.pmulu.dq",
		"llvm.x86.avx2.psad.bw",
		"llvm.x86.avx2.pshuf.b",
		"llvm.x86.avx2.psign.b",
		"llvm.x86.avx2.psign.d",
		"llvm.x86.avx2.psign.w",
		"llvm.x86.avx2.psll.d",
		"llvm.x86.avx2.psll.dq",
		"llvm.x86.avx2.psll.dq.bs",
		"llvm.x86.avx2.psll.q",
		"llvm.x86.avx2.psll.w",
		"llvm.x86.avx2.pslli.d",
		"llvm.x86.avx2.pslli.q",
		"llvm.x86.avx2.pslli.w",
		"llvm.x86.avx2.psllv.d",
		"llvm.x86.avx2.psllv.d.256",
		"llvm.x86.avx2.psllv.q",
		"llvm.x86.avx2.psllv.q.256",
		"llvm.x86.avx2.psra.d",
		"llvm.x86.avx2.psra.w",
		"llvm.x86.avx2.psrai.d",
		"llvm.x86.avx2.psrai.w",
		"llvm.x86.avx2.psrav.d",
		"llvm.x86.avx2.psrav.d.256",
		"llvm.x86.avx2.psrl.d",
		"llvm.x86.avx2.psrl.dq",
		"llvm.x86.avx2.psrl.dq.bs",
		"llvm.x86.avx2.psrl.q",
		"llvm.x86.avx2.psrl.w",
		"llvm.x86.avx2.psrli.d",
		"llvm.x86.avx2.psrli.q",
		"llvm.x86.avx2.psrli.w",
		"llvm.x86.avx2.psrlv.d",
		"llvm.x86.avx2.psrlv.d.256",
		"llvm.x86.avx2.psrlv.q",
		"llvm.x86.avx2.psrlv.q.256",
		"llvm.x86.avx2.psubs.b",
		"llvm.x86.avx2.psubs.w",
		"llvm.x86.avx2.psubus.b",
		"llvm.x86.avx2.psubus.w",
		"llvm.x86.avx2.vbroadcast.sd.pd.256",
		"llvm.x86.avx2.vbroadcast.ss.ps",
		"llvm.x86.avx2.vbroadcast.ss.ps.256",
		"llvm.x86.avx2.vbroadcasti128",
		"llvm.x86.avx2.vextracti128",
		"llvm.x86.avx2.vinserti128",
		"llvm.x86.avx2.vperm2i128",
	"llvm.x86.avx.addsub.pd.256",	"llvm.x86.avx.addsub.pd.256",
	"llvm.x86.avx.addsub.ps.256",	"llvm.x86.avx.addsub.ps.256",
	"llvm.x86.avx.blend.pd.256",	"llvm.x86.avx.blend.pd.256",
	"llvm.x86.avx.blend.ps.256",	"llvm.x86.avx.blend.ps.256",
	"llvm.x86.avx.blendv.pd.256",	"llvm.x86.avx.blendv.pd.256",
	"llvm.x86.avx.blendv.ps.256",	"llvm.x86.avx.blendv.ps.256",
	"llvm.x86.avx.cmp.pd.256",	"llvm.x86.avx.cmp.pd.256",
	"llvm.x86.avx.cmp.ps.256",	"llvm.x86.avx.cmp.ps.256",
	"llvm.x86.avx.cvt.pd2.ps.256",	"llvm.x86.avx.cvt.pd2.ps.256",
	"llvm.x86.avx.cvt.pd2dq.256",	"llvm.x86.avx.cvt.pd2dq.256",

	skipping to change at line 1521	skipping to change at line 3232
	"llvm.x86.avx.cvtdq2.pd.256",	"llvm.x86.avx.cvtdq2.pd.256",
	"llvm.x86.avx.cvtdq2.ps.256",	"llvm.x86.avx.cvtdq2.ps.256",
	"llvm.x86.avx.cvtt.pd2dq.256",	"llvm.x86.avx.cvtt.pd2dq.256",
	"llvm.x86.avx.cvtt.ps2dq.256",	"llvm.x86.avx.cvtt.ps2dq.256",
	"llvm.x86.avx.dp.ps.256",	"llvm.x86.avx.dp.ps.256",
	"llvm.x86.avx.hadd.pd.256",	"llvm.x86.avx.hadd.pd.256",
	"llvm.x86.avx.hadd.ps.256",	"llvm.x86.avx.hadd.ps.256",
	"llvm.x86.avx.hsub.pd.256",	"llvm.x86.avx.hsub.pd.256",
	"llvm.x86.avx.hsub.ps.256",	"llvm.x86.avx.hsub.ps.256",
	"llvm.x86.avx.ldu.dq.256",	"llvm.x86.avx.ldu.dq.256",

	"llvm.x86.avx.loadu.dq.256",
	"llvm.x86.avx.loadu.pd.256",
	"llvm.x86.avx.loadu.ps.256",
	"llvm.x86.avx.maskload.pd",	"llvm.x86.avx.maskload.pd",
	"llvm.x86.avx.maskload.pd.256",	"llvm.x86.avx.maskload.pd.256",
	"llvm.x86.avx.maskload.ps",	"llvm.x86.avx.maskload.ps",
	"llvm.x86.avx.maskload.ps.256",	"llvm.x86.avx.maskload.ps.256",
	"llvm.x86.avx.maskstore.pd",	"llvm.x86.avx.maskstore.pd",
	"llvm.x86.avx.maskstore.pd.256",	"llvm.x86.avx.maskstore.pd.256",
	"llvm.x86.avx.maskstore.ps",	"llvm.x86.avx.maskstore.ps",
	"llvm.x86.avx.maskstore.ps.256",	"llvm.x86.avx.maskstore.ps.256",
	"llvm.x86.avx.max.pd.256",	"llvm.x86.avx.max.pd.256",
	"llvm.x86.avx.max.ps.256",	"llvm.x86.avx.max.ps.256",

	skipping to change at line 1554	skipping to change at line 3262
	"llvm.x86.avx.rcp.ps.256",	"llvm.x86.avx.rcp.ps.256",
	"llvm.x86.avx.round.pd.256",	"llvm.x86.avx.round.pd.256",
	"llvm.x86.avx.round.ps.256",	"llvm.x86.avx.round.ps.256",
	"llvm.x86.avx.rsqrt.ps.256",	"llvm.x86.avx.rsqrt.ps.256",
	"llvm.x86.avx.sqrt.pd.256",	"llvm.x86.avx.sqrt.pd.256",
	"llvm.x86.avx.sqrt.ps.256",	"llvm.x86.avx.sqrt.ps.256",
	"llvm.x86.avx.storeu.dq.256",	"llvm.x86.avx.storeu.dq.256",
	"llvm.x86.avx.storeu.pd.256",	"llvm.x86.avx.storeu.pd.256",
	"llvm.x86.avx.storeu.ps.256",	"llvm.x86.avx.storeu.ps.256",
	"llvm.x86.avx.vbroadcast.sd.256",	"llvm.x86.avx.vbroadcast.sd.256",

		"llvm.x86.avx.vbroadcast.ss",
		"llvm.x86.avx.vbroadcast.ss.256",
	"llvm.x86.avx.vbroadcastf128.pd.256",	"llvm.x86.avx.vbroadcastf128.pd.256",
	"llvm.x86.avx.vbroadcastf128.ps.256",	"llvm.x86.avx.vbroadcastf128.ps.256",

	"llvm.x86.avx.vbroadcastss",
	"llvm.x86.avx.vbroadcastss.256",
	"llvm.x86.avx.vextractf128.pd.256",	"llvm.x86.avx.vextractf128.pd.256",
	"llvm.x86.avx.vextractf128.ps.256",	"llvm.x86.avx.vextractf128.ps.256",
	"llvm.x86.avx.vextractf128.si.256",	"llvm.x86.avx.vextractf128.si.256",
	"llvm.x86.avx.vinsertf128.pd.256",	"llvm.x86.avx.vinsertf128.pd.256",
	"llvm.x86.avx.vinsertf128.ps.256",	"llvm.x86.avx.vinsertf128.ps.256",
	"llvm.x86.avx.vinsertf128.si.256",	"llvm.x86.avx.vinsertf128.si.256",
	"llvm.x86.avx.vperm2f128.pd.256",	"llvm.x86.avx.vperm2f128.pd.256",
	"llvm.x86.avx.vperm2f128.ps.256",	"llvm.x86.avx.vperm2f128.ps.256",
	"llvm.x86.avx.vperm2f128.si.256",	"llvm.x86.avx.vperm2f128.si.256",

	"llvm.x86.avx.vpermil.pd",
	"llvm.x86.avx.vpermil.pd.256",
	"llvm.x86.avx.vpermil.ps",
	"llvm.x86.avx.vpermil.ps.256",
	"llvm.x86.avx.vpermilvar.pd",	"llvm.x86.avx.vpermilvar.pd",
	"llvm.x86.avx.vpermilvar.pd.256",	"llvm.x86.avx.vpermilvar.pd.256",
	"llvm.x86.avx.vpermilvar.ps",	"llvm.x86.avx.vpermilvar.ps",
	"llvm.x86.avx.vpermilvar.ps.256",	"llvm.x86.avx.vpermilvar.ps.256",
	"llvm.x86.avx.vtestc.pd",	"llvm.x86.avx.vtestc.pd",
	"llvm.x86.avx.vtestc.pd.256",	"llvm.x86.avx.vtestc.pd.256",
	"llvm.x86.avx.vtestc.ps",	"llvm.x86.avx.vtestc.ps",
	"llvm.x86.avx.vtestc.ps.256",	"llvm.x86.avx.vtestc.ps.256",
	"llvm.x86.avx.vtestnzc.pd",	"llvm.x86.avx.vtestnzc.pd",
	"llvm.x86.avx.vtestnzc.pd.256",	"llvm.x86.avx.vtestnzc.pd.256",
	"llvm.x86.avx.vtestnzc.ps",	"llvm.x86.avx.vtestnzc.ps",
	"llvm.x86.avx.vtestnzc.ps.256",	"llvm.x86.avx.vtestnzc.ps.256",
	"llvm.x86.avx.vtestz.pd",	"llvm.x86.avx.vtestz.pd",
	"llvm.x86.avx.vtestz.pd.256",	"llvm.x86.avx.vtestz.pd.256",
	"llvm.x86.avx.vtestz.ps",	"llvm.x86.avx.vtestz.ps",
	"llvm.x86.avx.vtestz.ps.256",	"llvm.x86.avx.vtestz.ps.256",
	"llvm.x86.avx.vzeroall",	"llvm.x86.avx.vzeroall",
	"llvm.x86.avx.vzeroupper",	"llvm.x86.avx.vzeroupper",

		"llvm.x86.bmi.bextr.32",
		"llvm.x86.bmi.bextr.64",
		"llvm.x86.bmi.bzhi.32",
		"llvm.x86.bmi.bzhi.64",
		"llvm.x86.bmi.pdep.32",
		"llvm.x86.bmi.pdep.64",
		"llvm.x86.bmi.pext.32",
		"llvm.x86.bmi.pext.64",
		"llvm.x86.fma4.vfmadd.pd",
		"llvm.x86.fma4.vfmadd.pd.256",
		"llvm.x86.fma4.vfmadd.ps",
		"llvm.x86.fma4.vfmadd.ps.256",
		"llvm.x86.fma4.vfmadd.sd",
		"llvm.x86.fma4.vfmadd.ss",
		"llvm.x86.fma4.vfmaddsub.pd",
		"llvm.x86.fma4.vfmaddsub.pd.256",
		"llvm.x86.fma4.vfmaddsub.ps",
		"llvm.x86.fma4.vfmaddsub.ps.256",
		"llvm.x86.fma4.vfmsub.pd",
		"llvm.x86.fma4.vfmsub.pd.256",
		"llvm.x86.fma4.vfmsub.ps",
		"llvm.x86.fma4.vfmsub.ps.256",
		"llvm.x86.fma4.vfmsub.sd",
		"llvm.x86.fma4.vfmsub.ss",
		"llvm.x86.fma4.vfmsubadd.pd",
		"llvm.x86.fma4.vfmsubadd.pd.256",
		"llvm.x86.fma4.vfmsubadd.ps",
		"llvm.x86.fma4.vfmsubadd.ps.256",
		"llvm.x86.fma4.vfnmadd.pd",
		"llvm.x86.fma4.vfnmadd.pd.256",
		"llvm.x86.fma4.vfnmadd.ps",
		"llvm.x86.fma4.vfnmadd.ps.256",
		"llvm.x86.fma4.vfnmadd.sd",
		"llvm.x86.fma4.vfnmadd.ss",
		"llvm.x86.fma4.vfnmsub.pd",
		"llvm.x86.fma4.vfnmsub.pd.256",
		"llvm.x86.fma4.vfnmsub.ps",
		"llvm.x86.fma4.vfnmsub.ps.256",
		"llvm.x86.fma4.vfnmsub.sd",
		"llvm.x86.fma4.vfnmsub.ss",
	"llvm.x86.int",	"llvm.x86.int",
	"llvm.x86.mmx.emms",	"llvm.x86.mmx.emms",
	"llvm.x86.mmx.femms",	"llvm.x86.mmx.femms",
	"llvm.x86.mmx.maskmovq",	"llvm.x86.mmx.maskmovq",
	"llvm.x86.mmx.movnt.dq",	"llvm.x86.mmx.movnt.dq",
	"llvm.x86.mmx.packssdw",	"llvm.x86.mmx.packssdw",
	"llvm.x86.mmx.packsswb",	"llvm.x86.mmx.packsswb",
	"llvm.x86.mmx.packuswb",	"llvm.x86.mmx.packuswb",
	"llvm.x86.mmx.padd.b",	"llvm.x86.mmx.padd.b",
	"llvm.x86.mmx.padd.d",	"llvm.x86.mmx.padd.d",

	skipping to change at line 1661	skipping to change at line 3405
	"llvm.x86.mmx.psubs.w",	"llvm.x86.mmx.psubs.w",
	"llvm.x86.mmx.psubus.b",	"llvm.x86.mmx.psubus.b",
	"llvm.x86.mmx.psubus.w",	"llvm.x86.mmx.psubus.w",
	"llvm.x86.mmx.punpckhbw",	"llvm.x86.mmx.punpckhbw",
	"llvm.x86.mmx.punpckhdq",	"llvm.x86.mmx.punpckhdq",
	"llvm.x86.mmx.punpckhwd",	"llvm.x86.mmx.punpckhwd",
	"llvm.x86.mmx.punpcklbw",	"llvm.x86.mmx.punpcklbw",
	"llvm.x86.mmx.punpckldq",	"llvm.x86.mmx.punpckldq",
	"llvm.x86.mmx.punpcklwd",	"llvm.x86.mmx.punpcklwd",
	"llvm.x86.mmx.pxor",	"llvm.x86.mmx.pxor",

		"llvm.x86.rdfsbase.32",
		"llvm.x86.rdfsbase.64",
		"llvm.x86.rdgsbase.32",
		"llvm.x86.rdgsbase.64",
	"llvm.x86.sse2.add.sd",	"llvm.x86.sse2.add.sd",
	"llvm.x86.sse2.clflush",	"llvm.x86.sse2.clflush",
	"llvm.x86.sse2.cmp.pd",	"llvm.x86.sse2.cmp.pd",
	"llvm.x86.sse2.cmp.sd",	"llvm.x86.sse2.cmp.sd",
	"llvm.x86.sse2.comieq.sd",	"llvm.x86.sse2.comieq.sd",
	"llvm.x86.sse2.comige.sd",	"llvm.x86.sse2.comige.sd",
	"llvm.x86.sse2.comigt.sd",	"llvm.x86.sse2.comigt.sd",
	"llvm.x86.sse2.comile.sd",	"llvm.x86.sse2.comile.sd",
	"llvm.x86.sse2.comilt.sd",	"llvm.x86.sse2.comilt.sd",
	"llvm.x86.sse2.comineq.sd",	"llvm.x86.sse2.comineq.sd",

	skipping to change at line 1706	skipping to change at line 3454
	"llvm.x86.sse2.mul.sd",	"llvm.x86.sse2.mul.sd",
	"llvm.x86.sse2.packssdw.128",	"llvm.x86.sse2.packssdw.128",
	"llvm.x86.sse2.packsswb.128",	"llvm.x86.sse2.packsswb.128",
	"llvm.x86.sse2.packuswb.128",	"llvm.x86.sse2.packuswb.128",
	"llvm.x86.sse2.padds.b",	"llvm.x86.sse2.padds.b",
	"llvm.x86.sse2.padds.w",	"llvm.x86.sse2.padds.w",
	"llvm.x86.sse2.paddus.b",	"llvm.x86.sse2.paddus.b",
	"llvm.x86.sse2.paddus.w",	"llvm.x86.sse2.paddus.w",
	"llvm.x86.sse2.pavg.b",	"llvm.x86.sse2.pavg.b",
	"llvm.x86.sse2.pavg.w",	"llvm.x86.sse2.pavg.w",

	"llvm.x86.sse2.pcmpeq.b",
	"llvm.x86.sse2.pcmpeq.d",
	"llvm.x86.sse2.pcmpeq.w",
	"llvm.x86.sse2.pcmpgt.b",
	"llvm.x86.sse2.pcmpgt.d",
	"llvm.x86.sse2.pcmpgt.w",
	"llvm.x86.sse2.pmadd.wd",	"llvm.x86.sse2.pmadd.wd",
	"llvm.x86.sse2.pmaxs.w",	"llvm.x86.sse2.pmaxs.w",
	"llvm.x86.sse2.pmaxu.b",	"llvm.x86.sse2.pmaxu.b",
	"llvm.x86.sse2.pmins.w",	"llvm.x86.sse2.pmins.w",
	"llvm.x86.sse2.pminu.b",	"llvm.x86.sse2.pminu.b",
	"llvm.x86.sse2.pmovmskb.128",	"llvm.x86.sse2.pmovmskb.128",
	"llvm.x86.sse2.pmulh.w",	"llvm.x86.sse2.pmulh.w",
	"llvm.x86.sse2.pmulhu.w",	"llvm.x86.sse2.pmulhu.w",
	"llvm.x86.sse2.pmulu.dq",	"llvm.x86.sse2.pmulu.dq",
	"llvm.x86.sse2.psad.bw",	"llvm.x86.sse2.psad.bw",

	skipping to change at line 1780	skipping to change at line 3522
	"llvm.x86.sse41.blendvps",	"llvm.x86.sse41.blendvps",
	"llvm.x86.sse41.dppd",	"llvm.x86.sse41.dppd",
	"llvm.x86.sse41.dpps",	"llvm.x86.sse41.dpps",
	"llvm.x86.sse41.extractps",	"llvm.x86.sse41.extractps",
	"llvm.x86.sse41.insertps",	"llvm.x86.sse41.insertps",
	"llvm.x86.sse41.movntdqa",	"llvm.x86.sse41.movntdqa",
	"llvm.x86.sse41.mpsadbw",	"llvm.x86.sse41.mpsadbw",
	"llvm.x86.sse41.packusdw",	"llvm.x86.sse41.packusdw",
	"llvm.x86.sse41.pblendvb",	"llvm.x86.sse41.pblendvb",
	"llvm.x86.sse41.pblendw",	"llvm.x86.sse41.pblendw",

	"llvm.x86.sse41.pcmpeqq",
	"llvm.x86.sse41.pextrb",	"llvm.x86.sse41.pextrb",
	"llvm.x86.sse41.pextrd",	"llvm.x86.sse41.pextrd",
	"llvm.x86.sse41.pextrq",	"llvm.x86.sse41.pextrq",
	"llvm.x86.sse41.phminposuw",	"llvm.x86.sse41.phminposuw",
	"llvm.x86.sse41.pmaxsb",	"llvm.x86.sse41.pmaxsb",
	"llvm.x86.sse41.pmaxsd",	"llvm.x86.sse41.pmaxsd",
	"llvm.x86.sse41.pmaxud",	"llvm.x86.sse41.pmaxud",
	"llvm.x86.sse41.pmaxuw",	"llvm.x86.sse41.pmaxuw",
	"llvm.x86.sse41.pminsb",	"llvm.x86.sse41.pminsb",
	"llvm.x86.sse41.pminsd",	"llvm.x86.sse41.pminsd",

	skipping to change at line 1825	skipping to change at line 3566
	"llvm.x86.sse42.crc32.32.8",	"llvm.x86.sse42.crc32.32.8",
	"llvm.x86.sse42.crc32.64.64",	"llvm.x86.sse42.crc32.64.64",
	"llvm.x86.sse42.crc32.64.8",	"llvm.x86.sse42.crc32.64.8",
	"llvm.x86.sse42.pcmpestri128",	"llvm.x86.sse42.pcmpestri128",
	"llvm.x86.sse42.pcmpestria128",	"llvm.x86.sse42.pcmpestria128",
	"llvm.x86.sse42.pcmpestric128",	"llvm.x86.sse42.pcmpestric128",
	"llvm.x86.sse42.pcmpestrio128",	"llvm.x86.sse42.pcmpestrio128",
	"llvm.x86.sse42.pcmpestris128",	"llvm.x86.sse42.pcmpestris128",
	"llvm.x86.sse42.pcmpestriz128",	"llvm.x86.sse42.pcmpestriz128",
	"llvm.x86.sse42.pcmpestrm128",	"llvm.x86.sse42.pcmpestrm128",

	"llvm.x86.sse42.pcmpgtq",
	"llvm.x86.sse42.pcmpistri128",	"llvm.x86.sse42.pcmpistri128",
	"llvm.x86.sse42.pcmpistria128",	"llvm.x86.sse42.pcmpistria128",
	"llvm.x86.sse42.pcmpistric128",	"llvm.x86.sse42.pcmpistric128",
	"llvm.x86.sse42.pcmpistrio128",	"llvm.x86.sse42.pcmpistrio128",
	"llvm.x86.sse42.pcmpistris128",	"llvm.x86.sse42.pcmpistris128",
	"llvm.x86.sse42.pcmpistriz128",	"llvm.x86.sse42.pcmpistriz128",
	"llvm.x86.sse42.pcmpistrm128",	"llvm.x86.sse42.pcmpistrm128",
	"llvm.x86.sse.add.ss",	"llvm.x86.sse.add.ss",
	"llvm.x86.sse.cmp.ps",	"llvm.x86.sse.cmp.ps",
	"llvm.x86.sse.cmp.ss",	"llvm.x86.sse.cmp.ss",

	skipping to change at line 1909	skipping to change at line 3649
	"llvm.x86.ssse3.pmul.hr.sw",	"llvm.x86.ssse3.pmul.hr.sw",
	"llvm.x86.ssse3.pmul.hr.sw.128",	"llvm.x86.ssse3.pmul.hr.sw.128",
	"llvm.x86.ssse3.pshuf.b",	"llvm.x86.ssse3.pshuf.b",
	"llvm.x86.ssse3.pshuf.b.128",	"llvm.x86.ssse3.pshuf.b.128",
	"llvm.x86.ssse3.psign.b",	"llvm.x86.ssse3.psign.b",
	"llvm.x86.ssse3.psign.b.128",	"llvm.x86.ssse3.psign.b.128",
	"llvm.x86.ssse3.psign.d",	"llvm.x86.ssse3.psign.d",
	"llvm.x86.ssse3.psign.d.128",	"llvm.x86.ssse3.psign.d.128",
	"llvm.x86.ssse3.psign.w",	"llvm.x86.ssse3.psign.w",
	"llvm.x86.ssse3.psign.w.128",	"llvm.x86.ssse3.psign.w.128",

		"llvm.x86.vcvtph2ps.128",
		"llvm.x86.vcvtph2ps.256",
		"llvm.x86.vcvtps2ph.128",
		"llvm.x86.vcvtps2ph.256",
		"llvm.x86.wrfsbase.32",
		"llvm.x86.wrfsbase.64",
		"llvm.x86.wrgsbase.32",
		"llvm.x86.wrgsbase.64",
		"llvm.x86.xop.vfrcz.pd",
		"llvm.x86.xop.vfrcz.pd.256",
		"llvm.x86.xop.vfrcz.ps",
		"llvm.x86.xop.vfrcz.ps.256",
		"llvm.x86.xop.vfrcz.sd",
		"llvm.x86.xop.vfrcz.ss",
		"llvm.x86.xop.vpcmov",
		"llvm.x86.xop.vpcmov.256",
		"llvm.x86.xop.vpcomeqb",
		"llvm.x86.xop.vpcomeqd",
		"llvm.x86.xop.vpcomeqq",
		"llvm.x86.xop.vpcomequb",
		"llvm.x86.xop.vpcomequd",
		"llvm.x86.xop.vpcomequq",
		"llvm.x86.xop.vpcomequw",
		"llvm.x86.xop.vpcomeqw",
		"llvm.x86.xop.vpcomfalseb",
		"llvm.x86.xop.vpcomfalsed",
		"llvm.x86.xop.vpcomfalseq",
		"llvm.x86.xop.vpcomfalseub",
		"llvm.x86.xop.vpcomfalseud",
		"llvm.x86.xop.vpcomfalseuq",
		"llvm.x86.xop.vpcomfalseuw",
		"llvm.x86.xop.vpcomfalsew",
		"llvm.x86.xop.vpcomgeb",
		"llvm.x86.xop.vpcomged",
		"llvm.x86.xop.vpcomgeq",
		"llvm.x86.xop.vpcomgeub",
		"llvm.x86.xop.vpcomgeud",
		"llvm.x86.xop.vpcomgeuq",
		"llvm.x86.xop.vpcomgeuw",
		"llvm.x86.xop.vpcomgew",
		"llvm.x86.xop.vpcomgtb",
		"llvm.x86.xop.vpcomgtd",
		"llvm.x86.xop.vpcomgtq",
		"llvm.x86.xop.vpcomgtub",
		"llvm.x86.xop.vpcomgtud",
		"llvm.x86.xop.vpcomgtuq",
		"llvm.x86.xop.vpcomgtuw",
		"llvm.x86.xop.vpcomgtw",
		"llvm.x86.xop.vpcomleb",
		"llvm.x86.xop.vpcomled",
		"llvm.x86.xop.vpcomleq",
		"llvm.x86.xop.vpcomleub",
		"llvm.x86.xop.vpcomleud",
		"llvm.x86.xop.vpcomleuq",
		"llvm.x86.xop.vpcomleuw",
		"llvm.x86.xop.vpcomlew",
		"llvm.x86.xop.vpcomltb",
		"llvm.x86.xop.vpcomltd",
		"llvm.x86.xop.vpcomltq",
		"llvm.x86.xop.vpcomltub",
		"llvm.x86.xop.vpcomltud",
		"llvm.x86.xop.vpcomltuq",
		"llvm.x86.xop.vpcomltuw",
		"llvm.x86.xop.vpcomltw",
		"llvm.x86.xop.vpcomneb",
		"llvm.x86.xop.vpcomned",
		"llvm.x86.xop.vpcomneq",
		"llvm.x86.xop.vpcomneub",
		"llvm.x86.xop.vpcomneud",
		"llvm.x86.xop.vpcomneuq",
		"llvm.x86.xop.vpcomneuw",
		"llvm.x86.xop.vpcomnew",
		"llvm.x86.xop.vpcomtrueb",
		"llvm.x86.xop.vpcomtrued",
		"llvm.x86.xop.vpcomtrueq",
		"llvm.x86.xop.vpcomtrueub",
		"llvm.x86.xop.vpcomtrueud",
		"llvm.x86.xop.vpcomtrueuq",
		"llvm.x86.xop.vpcomtrueuw",
		"llvm.x86.xop.vpcomtruew",
		"llvm.x86.xop.vpermil2pd",
		"llvm.x86.xop.vpermil2pd.256",
		"llvm.x86.xop.vpermil2ps",
		"llvm.x86.xop.vpermil2ps.256",
		"llvm.x86.xop.vphaddbd",
		"llvm.x86.xop.vphaddbq",
		"llvm.x86.xop.vphaddbw",
		"llvm.x86.xop.vphadddq",
		"llvm.x86.xop.vphaddubd",
		"llvm.x86.xop.vphaddubq",
		"llvm.x86.xop.vphaddubw",
		"llvm.x86.xop.vphaddudq",
		"llvm.x86.xop.vphadduwd",
		"llvm.x86.xop.vphadduwq",
		"llvm.x86.xop.vphaddwd",
		"llvm.x86.xop.vphaddwq",
		"llvm.x86.xop.vphsubbw",
		"llvm.x86.xop.vphsubdq",
		"llvm.x86.xop.vphsubwd",
		"llvm.x86.xop.vpmacsdd",
		"llvm.x86.xop.vpmacsdqh",
		"llvm.x86.xop.vpmacsdql",
		"llvm.x86.xop.vpmacssdd",
		"llvm.x86.xop.vpmacssdqh",
		"llvm.x86.xop.vpmacssdql",
		"llvm.x86.xop.vpmacsswd",
		"llvm.x86.xop.vpmacssww",
		"llvm.x86.xop.vpmacswd",
		"llvm.x86.xop.vpmacsww",
		"llvm.x86.xop.vpmadcsswd",
		"llvm.x86.xop.vpmadcswd",
		"llvm.x86.xop.vpperm",
		"llvm.x86.xop.vprotb",
		"llvm.x86.xop.vprotd",
		"llvm.x86.xop.vprotq",
		"llvm.x86.xop.vprotw",
		"llvm.x86.xop.vpshab",
		"llvm.x86.xop.vpshad",
		"llvm.x86.xop.vpshaq",
		"llvm.x86.xop.vpshaw",
		"llvm.x86.xop.vpshlb",
		"llvm.x86.xop.vpshld",
		"llvm.x86.xop.vpshlq",
		"llvm.x86.xop.vpshlw",
	"llvm.xcore.bitrev",	"llvm.xcore.bitrev",
	"llvm.xcore.checkevent",	"llvm.xcore.checkevent",
	"llvm.xcore.chkct",	"llvm.xcore.chkct",
	"llvm.xcore.clre",	"llvm.xcore.clre",
	"llvm.xcore.clrsr",	"llvm.xcore.clrsr",
	"llvm.xcore.crc32",	"llvm.xcore.crc32",
	"llvm.xcore.crc8",	"llvm.xcore.crc8",
	"llvm.xcore.eeu",	"llvm.xcore.eeu",
	"llvm.xcore.endin",	"llvm.xcore.endin",
	"llvm.xcore.freer",	"llvm.xcore.freer",

	skipping to change at line 1962	skipping to change at line 3826
	"llvm.xcore.setv",	"llvm.xcore.setv",
	"llvm.xcore.sext",	"llvm.xcore.sext",
	"llvm.xcore.ssync",	"llvm.xcore.ssync",
	"llvm.xcore.syncr",	"llvm.xcore.syncr",
	"llvm.xcore.testct",	"llvm.xcore.testct",
	"llvm.xcore.testwct",	"llvm.xcore.testwct",
	"llvm.xcore.waitevent",	"llvm.xcore.waitevent",
	"llvm.xcore.zext",	"llvm.xcore.zext",
	#endif	#endif


	// Intrinsic ID to overload table	// Intrinsic ID to overload bitset
	#ifdef GET_INTRINSIC_OVERLOAD_TABLE	#ifdef GET_INTRINSIC_OVERLOAD_TABLE

	// Note that entry #0 is the invalid intrinsic!	static const uint8_t OTable[] = {
	false,	0 \| (1<<2),
	false,	0 \| (1<<5) \| (1<<6) \| (1<<7),
	true,	0 \| (1<<4) \| (1<<5) \| (1<<6) \| (1<<7),
	false,	0 \| (1<<0) \| (1<<1) \| (1<<3) \| (1<<4) \| (1<<6) \| (1<<7),
	false,	0 \| (1<<0) \| (1<<1) \| (1<<2) \| (1<<3) \| (1<<4) \| (1<<5) \| (1<<6) \| (1<<7)
	false,	,
	false,	0 \| (1<<0) \| (1<<1) \| (1<<2) \| (1<<3) \| (1<<4) \| (1<<5) \| (1<<6) \| (1<<7)
	false,	,
	false,	0 \| (1<<0) \| (1<<1) \| (1<<2) \| (1<<3) \| (1<<4) \| (1<<5) \| (1<<6) \| (1<<7)
	false,	,
	false,	0 \| (1<<0) \| (1<<1) \| (1<<2) \| (1<<3) \| (1<<4) \| (1<<5) \| (1<<6) \| (1<<7)
	false,	,
	false,	0 \| (1<<0) \| (1<<1) \| (1<<2) \| (1<<3) \| (1<<4) \| (1<<5) \| (1<<6) \| (1<<7)
	true,	,
	true,	0 \| (1<<0) \| (1<<1) \| (1<<2) \| (1<<3) \| (1<<4) \| (1<<5) \| (1<<6) \| (1<<7)
	true,	,
	false,	0 \| (1<<0) \| (1<<1) \| (1<<2) \| (1<<3) \| (1<<4) \| (1<<5) \| (1<<6) \| (1<<7)
	false,	,
	false,	0 \| (1<<0) \| (1<<1) \| (1<<2) \| (1<<3) \| (1<<4) \| (1<<5) \| (1<<6) \| (1<<7)
	false,	,
	true,	0 \| (1<<0) \| (1<<1) \| (1<<2) \| (1<<3) \| (1<<4) \| (1<<5) \| (1<<6) \| (1<<7)
	true,	,
	true,	0 \| (1<<0) \| (1<<1) \| (1<<2) \| (1<<3),
	true,	0,
	true,	0 \| (1<<3) \| (1<<4) \| (1<<5),
	true,	0 \| (1<<0) \| (1<<1) \| (1<<2) \| (1<<3) \| (1<<4) \| (1<<5) \| (1<<6) \| (1<<7)
	false,	,
	true,	0 \| (1<<0) \| (1<<1) \| (1<<2) \| (1<<3) \| (1<<4),
	true,	0,
	false,	0 \| (1<<1) \| (1<<2) \| (1<<3) \| (1<<5),
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0 \| (1<<6) \| (1<<7),
	false,	0 \| (1<<0) \| (1<<2) \| (1<<3) \| (1<<4) \| (1<<5) \| (1<<7),
	false,	0 \| (1<<0),
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	true,	0,
	true,	0,
	true,	0,
	false,	0,
	false,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0 \| (1<<6),
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0 \| (1<<3) \| (1<<7),
	true,	0 \| (1<<0),
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0 \| (1<<3) \| (1<<4),
	false,	0 \| (1<<1) \| (1<<2) \| (1<<3),
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	true,	0,
	true,	0,
	true,	0,
	false,	0,
	true,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	true,	0,
	true,	0,
	true,	0,
	false,	0,
	true,	0,
	true,	0,
	true,	0,
	true,	0,
	false,	0,
	true,	0,
	true,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0,
	false,	0 \| (1<<4),
	false,	0 \| (1<<1) \| (1<<2) \| (1<<3),
	false,	0 \| (1<<0) \| (1<<1) \| (1<<2) \| (1<<3) \| (1<<4) \| (1<<5) \| (1<<6) \| (1<<7)
	false,	,
	false,	0 \| (1<<0) \| (1<<1) \| (1<<2) \| (1<<3) \| (1<<4) \| (1<<5) \| (1<<6) \| (1<<7)
	false,	,
	false,	0 \| (1<<0) \| (1<<1) \| (1<<2) \| (1<<3) \| (1<<4) \| (1<<5) \| (1<<6),
	false,	0 \| (1<<0) \| (1<<1) \| (1<<2) \| (1<<4) \| (1<<5),
	false,	0 \| (1<<0) \| (1<<1) \| (1<<2)
	false,	};
	false,
	false,	return (OTable[id/8] & (1 << (id%8))) != 0;
	false,
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	#endif	#endif

	// Function name -> enum value recognizer code.	// Function name -> enum value recognizer code.
	#ifdef GET_FUNCTION_RECOGNIZER	#ifdef GET_FUNCTION_RECOGNIZER
	StringRef NameR(Name+6, Len-6); // Skip over 'llvm.'	StringRef NameR(Name+6, Len-6); // Skip over 'llvm.'
	switch (Name[5]) { // Dispatch on first letter.	switch (Name[5]) { // Dispatch on first letter.
	default: break;	default: break;
	case 'a':	case 'a':
	if (NameR.startswith("nnotation.")) return Intrinsic::annotation;	if (NameR.startswith("nnotation.")) return Intrinsic::annotation;
	if (NameR.startswith("rm.neon.vabds.")) return Intrinsic::arm_neon_vabd s;	if (NameR.startswith("rm.neon.vabds.")) return Intrinsic::arm_neon_vabd s;

	skipping to change at line 3130	skipping to change at line 4267
	case 'l': // 1 string to match.	case 'l': // 1 string to match.
	if (NameR.substr(4, 5) != "drexd")	if (NameR.substr(4, 5) != "drexd")
	break;	break;
	return Intrinsic::arm_ldrexd; // "rm.ldrexd"	return Intrinsic::arm_ldrexd; // "rm.ldrexd"
	case 's': // 1 string to match.	case 's': // 1 string to match.
	if (NameR.substr(4, 5) != "trexd")	if (NameR.substr(4, 5) != "trexd")
	break;	break;
	return Intrinsic::arm_strexd; // "rm.strexd"	return Intrinsic::arm_strexd; // "rm.strexd"
	}	}
	break;	break;

	case 10: // 1 string to match.
	if (NameR.substr(0, 10) != "lpha.umulh")
	break;
	return Intrinsic::alpha_umulh; // "lpha.umulh"
	case 12: // 2 strings to match.	case 12: // 2 strings to match.
	if (NameR.substr(0, 3) != "rm.")	if (NameR.substr(0, 3) != "rm.")
	break;	break;
	switch (NameR[3]) {	switch (NameR[3]) {
	default: break;	default: break;
	case 'g': // 1 string to match.	case 'g': // 1 string to match.
	if (NameR.substr(4, 8) != "et.fpscr")	if (NameR.substr(4, 8) != "et.fpscr")
	break;	break;
	return Intrinsic::arm_get_fpscr; // "rm.get.fpscr"	return Intrinsic::arm_get_fpscr; // "rm.get.fpscr"
	case 's': // 1 string to match.	case 's': // 1 string to match.

	skipping to change at line 3287	skipping to change at line 4420
	break;	break;
	return Intrinsic::dbg_declare; // "bg.declare"	return Intrinsic::dbg_declare; // "bg.declare"
	}	}
	break; // end of 'd' case.	break; // end of 'd' case.
	case 'e':	case 'e':
	if (NameR.startswith("xp.")) return Intrinsic::exp;	if (NameR.startswith("xp.")) return Intrinsic::exp;
	if (NameR.startswith("xp2.")) return Intrinsic::exp2;	if (NameR.startswith("xp2.")) return Intrinsic::exp2;
	if (NameR.startswith("xpect.")) return Intrinsic::expect;	if (NameR.startswith("xpect.")) return Intrinsic::expect;
	switch (NameR.size()) {	switch (NameR.size()) {
	default: break;	default: break;

	case 8: // 1 string to match.	case 11: // 2 strings to match.
	if (NameR.substr(0, 8) != "h.resume")
	break;
	return Intrinsic::eh_resume; // "h.resume"
	case 10: // 1 string to match.
	if (NameR.substr(0, 10) != "h.selector")
	break;
	return Intrinsic::eh_selector; // "h.selector"
	case 11: // 3 strings to match.
	if (NameR.substr(0, 2) != "h.")	if (NameR.substr(0, 2) != "h.")
	break;	break;
	switch (NameR[2]) {	switch (NameR[2]) {
	default: break;	default: break;
	case 'd': // 1 string to match.	case 'd': // 1 string to match.
	if (NameR.substr(3, 8) != "warf.cfa")	if (NameR.substr(3, 8) != "warf.cfa")
	break;	break;
	return Intrinsic::eh_dwarf_cfa; // "h.dwarf.cfa"	return Intrinsic::eh_dwarf_cfa; // "h.dwarf.cfa"

	case 'e': // 1 string to match.
	if (NameR.substr(3, 8) != "xception")
	break;
	return Intrinsic::eh_exception; // "h.exception"
	case 's': // 1 string to match.	case 's': // 1 string to match.
	if (NameR.substr(3, 8) != "jlj.lsda")	if (NameR.substr(3, 8) != "jlj.lsda")
	break;	break;
	return Intrinsic::eh_sjlj_lsda; // "h.sjlj.lsda"	return Intrinsic::eh_sjlj_lsda; // "h.sjlj.lsda"
	}	}
	break;	break;
	case 12: // 3 strings to match.	case 12: // 3 strings to match.
	if (NameR.substr(0, 2) != "h.")	if (NameR.substr(0, 2) != "h.")
	break;	break;
	switch (NameR[2]) {	switch (NameR[2]) {

	skipping to change at line 3363	skipping to change at line 4484
	}	}
	break;	break;
	case 14: // 1 string to match.	case 14: // 1 string to match.
	if (NameR.substr(0, 14) != "h.sjlj.longjmp")	if (NameR.substr(0, 14) != "h.sjlj.longjmp")
	break;	break;
	return Intrinsic::eh_sjlj_longjmp; // "h.sjlj.longjmp"	return Intrinsic::eh_sjlj_longjmp; // "h.sjlj.longjmp"
	case 15: // 1 string to match.	case 15: // 1 string to match.
	if (NameR.substr(0, 15) != "h.sjlj.callsite")	if (NameR.substr(0, 15) != "h.sjlj.callsite")
	break;	break;
	return Intrinsic::eh_sjlj_callsite; // "h.sjlj.callsite"	return Intrinsic::eh_sjlj_callsite; // "h.sjlj.callsite"

	case 21: // 1 string to match.
	if (NameR.substr(0, 21) != "h.sjlj.dispatch.setup")
	break;
	return Intrinsic::eh_sjlj_dispatch_setup; // "h.sjlj.dispatch
	.setup"
	case 22: // 1 string to match.	case 22: // 1 string to match.
	if (NameR.substr(0, 22) != "h.sjlj.functioncontext")	if (NameR.substr(0, 22) != "h.sjlj.functioncontext")
	break;	break;
	return Intrinsic::eh_sjlj_functioncontext; // "h.sjlj.function context"	return Intrinsic::eh_sjlj_functioncontext; // "h.sjlj.function context"
	}	}
	break; // end of 'e' case.	break; // end of 'e' case.
	case 'f':	case 'f':
	if (NameR.startswith("ma.")) return Intrinsic::fma;	if (NameR.startswith("ma.")) return Intrinsic::fma;
	switch (NameR.size()) {	switch (NameR.size()) {
	default: break;	default: break;

	skipping to change at line 3411	skipping to change at line 4528
	break;	break;
	return Intrinsic::gcroot; // "croot"	return Intrinsic::gcroot; // "croot"
	}	}
	break;	break;
	case 6: // 1 string to match.	case 6: // 1 string to match.
	if (NameR.substr(0, 6) != "cwrite")	if (NameR.substr(0, 6) != "cwrite")
	break;	break;
	return Intrinsic::gcwrite; // "cwrite"	return Intrinsic::gcwrite; // "cwrite"
	}	}
	break; // end of 'g' case.	break; // end of 'g' case.

	case 'i':	case 'h':
	switch (NameR.size()) {	switch (NameR.size()) {
	default: break;	default: break;

	case 12: // 1 string to match.	case 12: // 2 strings to match.
	if (NameR.substr(0, 12) != "nvariant.end")	if (NameR.substr(0, 7) != "exagon.")
	break;
	return Intrinsic::invariant_end; // "nvariant.end"
	case 14: // 2 strings to match.
	if (NameR[0] != 'n')
	break;	break;

	switch (NameR[1]) {	switch (NameR[7]) {
	default: break;	default: break;

	case 'i': // 1 string to match.	case 'A': // 1 string to match.
	if (NameR.substr(2, 12) != "t.trampoline")	if (NameR.substr(8, 4) != "2.or")
	break;	break;

	return Intrinsic::init_trampoline; // "nit.trampoline"	return Intrinsic::hexagon_A2_or; // "exagon.A2.or"
	case 'v': // 1 string to match.	case 'C': // 1 string to match.
	if (NameR.substr(2, 12) != "ariant.start")	if (NameR.substr(8, 4) != "2.or")
	break;	break;

	return Intrinsic::invariant_start; // "nvariant.start"	return Intrinsic::hexagon_C2_or; // "exagon.C2.or"
	}	}
	break;	break;

	}	case 13: // 23 strings to match.
	break; // end of 'i' case.	if (NameR.substr(0, 7) != "exagon.")
	case 'l':
	if (NameR.startswith("og.")) return Intrinsic::log;
	if (NameR.startswith("og10.")) return Intrinsic::log10;
	if (NameR.startswith("og2.")) return Intrinsic::log2;
	switch (NameR.size()) {
	default: break;
	case 6: // 1 string to match.
	if (NameR.substr(0, 6) != "ongjmp")
	break;
	return Intrinsic::longjmp; // "ongjmp"
	case 11: // 1 string to match.
	if (NameR.substr(0, 11) != "ifetime.end")
	break;
	return Intrinsic::lifetime_end; // "ifetime.end"
	case 13: // 1 string to match.
	if (NameR.substr(0, 13) != "ifetime.start")
	break;	break;

	return Intrinsic::lifetime_start; // "ifetime.start"	switch (NameR[7]) {
	}
	break; // end of 'l' case.
	case 'm':
	if (NameR.startswith("emcpy.")) return Intrinsic::memcpy;
	if (NameR.startswith("emmove.")) return Intrinsic::memmove;
	if (NameR.startswith("emset.")) return Intrinsic::memset;
	break; // end of 'm' case.
	case 'o':
	if (NameR.startswith("bjectsize.")) return Intrinsic::objectsize;
	break; // end of 'o' case.
	case 'p':
	if (NameR.startswith("ow.")) return Intrinsic::pow;
	if (NameR.startswith("owi.")) return Intrinsic::powi;
	if (NameR.startswith("tr.annotation.")) return Intrinsic::ptr_annotatio
	n;
	switch (NameR.size()) {
	default: break;
	case 7: // 8 strings to match.
	switch (NameR[0]) {
	default: break;	default: break;

	case 'c': // 1 string to match.	case 'A': // 13 strings to match.
	if (NameR.substr(1, 6) != "marker")	switch (NameR[8]) {
	break;
	return Intrinsic::pcmarker; // "cmarker"
	case 'p': // 6 strings to match.
	if (NameR.substr(1, 2) != "c.")
	break;
	switch (NameR[3]) {
	default: break;	default: break;

	case 'd': // 5 strings to match.	case '2': // 12 strings to match.
	if (NameR.substr(4, 2) != "cb")	if (NameR[9] != '.')
	break;	break;

	switch (NameR[6]) {	switch (NameR[10]) {
	default: break;	default: break;

	case 'a': // 1 string to match.	case 'a': // 3 strings to match.
	return Intrinsic::ppc_dcba; // "pc.dcba"	switch (NameR[11]) {
	case 'f': // 1 string to match.	default: break;
	return Intrinsic::ppc_dcbf; // "pc.dcbf"	case 'b': // 1 string to match.
	case 'i': // 1 string to match.	if (NameR[12] != 's')
	return Intrinsic::ppc_dcbi; // "pc.dcbi"	break;
		return Intrinsic::hexagon_A2_abs; // "exagon.A2.abs"
		case 'd': // 1 string to match.
		if (NameR[12] != 'd')
		break;
		return Intrinsic::hexagon_A2_add; // "exagon.A2.add"
		case 'n': // 1 string to match.
		if (NameR[12] != 'd')
		break;
		return Intrinsic::hexagon_A2_and; // "exagon.A2.and"
		}
		break;
		case 'm': // 2 strings to match.
		switch (NameR[11]) {
		default: break;
		case 'a': // 1 string to match.
		if (NameR[12] != 'x')
		break;
		return Intrinsic::hexagon_A2_max; // "exagon.A2.max"
		case 'i': // 1 string to match.
		if (NameR[12] != 'n')
		break;
		return Intrinsic::hexagon_A2_min; // "exagon.A2.min"
		}
		break;
		case 'n': // 2 strings to match.
		switch (NameR[11]) {
		default: break;
		case 'e': // 1 string to match.
		if (NameR[12] != 'g')
		break;
		return Intrinsic::hexagon_A2_neg; // "exagon.A2.neg"
		case 'o': // 1 string to match.
		if (NameR[12] != 't')
		break;
		return Intrinsic::hexagon_A2_not; // "exagon.A2.not"
		}
		break;
		case 'o': // 1 string to match.
		if (NameR.substr(11, 2) != "rp")
		break;
		return Intrinsic::hexagon_A2_orp; // "exagon.A2.orp"
		case 's': // 2 strings to match.
		switch (NameR[11]) {
		default: break;
		case 'a': // 1 string to match.
		if (NameR[12] != 't')
		break;
		return Intrinsic::hexagon_A2_sat; // "exagon.A2.sat"
		case 'u': // 1 string to match.
		if (NameR[12] != 'b')
		break;
		return Intrinsic::hexagon_A2_sub; // "exagon.A2.sub"
		}
		break;
	case 't': // 1 string to match.	case 't': // 1 string to match.

	return Intrinsic::ppc_dcbt; // "pc.dcbt"	if (NameR.substr(11, 2) != "fr")
	case 'z': // 1 string to match.	break;
	return Intrinsic::ppc_dcbz; // "pc.dcbz"	return Intrinsic::hexagon_A2_tfr; // "exagon.A2.tfr"
		case 'x': // 1 string to match.
		if (NameR.substr(11, 2) != "or")
		break;
		return Intrinsic::hexagon_A2_xor; // "exagon.A2.xor"
	}	}
	break;	break;

	case 's': // 1 string to match.	case '4': // 1 string to match.
	if (NameR.substr(4, 3) != "ync")	if (NameR.substr(9, 4) != ".orn")
	break;	break;

	return Intrinsic::ppc_sync; // "pc.sync"	return Intrinsic::hexagon_A4_orn; // "exagon.A4.orn"
	}	}
	break;	break;

	case 'r': // 1 string to match.	case 'C': // 5 strings to match.
	if (NameR.substr(1, 6) != "efetch")	if (NameR.substr(8, 2) != "2.")
	break;
	return Intrinsic::prefetch; // "refetch"
	}
	break;
	case 8: // 2 strings to match.
	if (NameR.substr(0, 6) != "pc.dcb")
	break;
	switch (NameR[6]) {
	default: break;
	case 's': // 1 string to match.
	if (NameR[7] != 't')
	break;
	return Intrinsic::ppc_dcbst; // "pc.dcbst"
	case 'z': // 1 string to match.
	if (NameR[7] != 'l')
	break;
	return Intrinsic::ppc_dcbzl; // "pc.dcbzl"
	}
	break;
	case 9: // 1 string to match.
	if (NameR.substr(0, 9) != "pc.dcbtst")
	break;
	return Intrinsic::ppc_dcbtst; // "pc.dcbtst"
	case 11: // 5 strings to match.
	if (NameR.substr(0, 3) != "tx.")
	break;
	switch (NameR[3]) {
	default: break;
	case 'b': // 1 string to match.
	if (NameR.substr(4, 7) != "ar.sync")
	break;
	return Intrinsic::ptx_bar_sync; // "tx.bar.sync"
	case 'r': // 4 strings to match.
	if (NameR.substr(4, 6) != "ead.pm")
	break;	break;
	switch (NameR[10]) {	switch (NameR[10]) {
	default: break;	default: break;

	case '0': // 1 string to match.	case 'a': // 1 string to match.
	return Intrinsic::ptx_read_pm0; // "tx.read.pm0"	if (NameR.substr(11, 2) != "nd")
	case '1': // 1 string to match.	break;
	return Intrinsic::ptx_read_pm1; // "tx.read.pm1"	return Intrinsic::hexagon_C2_and; // "exagon.C2.and"
	case '2': // 1 string to match.	case 'm': // 1 string to match.
	return Intrinsic::ptx_read_pm2; // "tx.read.pm2"	if (NameR.substr(11, 2) != "ux")
	case '3': // 1 string to match.	break;
	return Intrinsic::ptx_read_pm3; // "tx.read.pm3"	return Intrinsic::hexagon_C2_mux; // "exagon.C2.mux"
	}	case 'n': // 1 string to match.
	break;	if (NameR.substr(11, 2) != "ot")
	}	break;
	break;	return Intrinsic::hexagon_C2_not; // "exagon.C2.not"
	case 12: // 1 string to match.	case 'o': // 1 string to match.
	if (NameR.substr(0, 12) != "tx.read.smid")	if (NameR.substr(11, 2) != "rn")
	break;	break;
	return Intrinsic::ptx_read_smid; // "tx.read.smid"	return Intrinsic::hexagon_C2_orn; // "exagon.C2.orn"
	case 13: // 6 strings to match.
	if (NameR.substr(0, 8) != "tx.read.")
	break;
	switch (NameR[8]) {
	default: break;
	case 'c': // 1 string to match.
	if (NameR.substr(9, 4) != "lock")
	break;
	return Intrinsic::ptx_read_clock; // "tx.read.clock"
	case 'n': // 1 string to match.
	if (NameR.substr(9, 4) != "smid")
	break;
	return Intrinsic::ptx_read_nsmid; // "tx.read.nsmid"
	case 't': // 4 strings to match.
	if (NameR.substr(9, 3) != "id.")
	break;
	switch (NameR[12]) {
	default: break;
	case 'w': // 1 string to match.
	return Intrinsic::ptx_read_tid_w; // "tx.read.tid.w"
	case 'x': // 1 string to match.	case 'x': // 1 string to match.

	return Intrinsic::ptx_read_tid_x; // "tx.read.tid.x"	if (NameR.substr(11, 2) != "or")
	case 'y': // 1 string to match.	break;
	return Intrinsic::ptx_read_tid_y; // "tx.read.tid.y"	return Intrinsic::hexagon_C2_xor; // "exagon.C2.xor"
	case 'z': // 1 string to match.
	return Intrinsic::ptx_read_tid_z; // "tx.read.tid.z"
	}	}
	break;	break;

	}	case 'S': // 5 strings to match.
	break;	if (NameR.substr(8, 3) != "2.c")
	case 14: // 12 strings to match.
	switch (NameR[0]) {
	default: break;
	case 'p': // 5 strings to match.
	if (NameR.substr(1, 10) != "c.altivec.")
	break;	break;
	switch (NameR[11]) {	switch (NameR[11]) {
	default: break;	default: break;

	case 'd': // 2 strings to match.	case 'l': // 3 strings to match.
	if (NameR[12] != 's')	switch (NameR[12]) {
	break;
	switch (NameR[13]) {
	default: break;	default: break;

	case 's': // 1 string to match.	case '0': // 1 string to match.
	return Intrinsic::ppc_altivec_dss; // "pc.altivec.dss"	return Intrinsic::hexagon_S2_cl0; // "exagon.S2.cl0"
	case 't': // 1 string to match.	case '1': // 1 string to match.
	return Intrinsic::ppc_altivec_dst; // "pc.altivec.dst"	return Intrinsic::hexagon_S2_cl1; // "exagon.S2.cl1"
		case 'b': // 1 string to match.
		return Intrinsic::hexagon_S2_clb; // "exagon.S2.clb"
	}	}
	break;	break;

	case 'l': // 1 string to match.	case 't': // 2 strings to match.
	if (NameR.substr(12, 2) != "vx")	switch (NameR[12]) {
	break;
	return Intrinsic::ppc_altivec_lvx; // "pc.altivec.lvx"
	case 'v': // 2 strings to match.
	if (NameR[12] != 's')
	break;
	switch (NameR[13]) {
	default: break;	default: break;

	case 'l': // 1 string to match.	case '0': // 1 string to match.
	return Intrinsic::ppc_altivec_vsl; // "pc.altivec.vsl"	return Intrinsic::hexagon_S2_ct0; // "exagon.S2.ct0"
	case 'r': // 1 string to match.	case '1': // 1 string to match.
	return Intrinsic::ppc_altivec_vsr; // "pc.altivec.vsr"	return Intrinsic::hexagon_S2_ct1; // "exagon.S2.ct1"
	}	}
	break;	break;
	}	}
	break;	break;

	case 't': // 7 strings to match.
	if (NameR.substr(1, 7) != "x.read.")
	break;
	switch (NameR[8]) {
	default: break;
	case 'g': // 1 string to match.
	if (NameR.substr(9, 5) != "ridid")
	break;
	return Intrinsic::ptx_read_gridid; // "tx.read.gridid"
	case 'l': // 1 string to match.
	if (NameR.substr(9, 5) != "aneid")
	break;
	return Intrinsic::ptx_read_laneid; // "tx.read.laneid"
	case 'n': // 4 strings to match.
	if (NameR.substr(9, 4) != "tid.")
	break;
	switch (NameR[13]) {
	default: break;
	case 'w': // 1 string to match.
	return Intrinsic::ptx_read_ntid_w; // "tx.read.ntid.w"
	case 'x': // 1 string to match.
	return Intrinsic::ptx_read_ntid_x; // "tx.read.ntid.x"
	case 'y': // 1 string to match.
	return Intrinsic::ptx_read_ntid_y; // "tx.read.ntid.y"
	case 'z': // 1 string to match.
	return Intrinsic::ptx_read_ntid_z; // "tx.read.ntid.z"
	}
	break;
	case 'w': // 1 string to match.
	if (NameR.substr(9, 5) != "arpid")
	break;
	return Intrinsic::ptx_read_warpid; // "tx.read.warpid"
	}
	break;
	}	}
	break;	break;

	case 15: // 23 strings to match.	case 14: // 40 strings to match.
	switch (NameR[0]) {	if (NameR.substr(0, 7) != "exagon.")
		break;
		switch (NameR[7]) {
	default: break;	default: break;

	case 'p': // 17 strings to match.	case 'A': // 26 strings to match.
	if (NameR.substr(1, 10) != "c.altivec.")	switch (NameR[8]) {
	break;
	switch (NameR[11]) {
	default: break;	default: break;

	case 'd': // 1 string to match.	case '2': // 24 strings to match.
	if (NameR.substr(12, 3) != "stt")	if (NameR[9] != '.')
	break;
	return Intrinsic::ppc_altivec_dstt; // "pc.altivec.dstt"
	case 'l': // 3 strings to match.
	if (NameR[12] != 'v')
	break;	break;

	switch (NameR[13]) {	switch (NameR[10]) {
	default: break;	default: break;

	case 's': // 2 strings to match.	case 'a': // 6 strings to match.
	switch (NameR[14]) {	switch (NameR[11]) {
	default: break;	default: break;

	case 'l': // 1 string to match.	case 'b': // 1 string to match.
	return Intrinsic::ppc_altivec_lvsl; // "pc.altivec.lvsl	if (NameR.substr(12, 2) != "sp")
	"	break;
	case 'r': // 1 string to match.	return Intrinsic::hexagon_A2_absp; // "exagon.A2.absp"
	return Intrinsic::ppc_altivec_lvsr; // "pc.altivec.lvsr	case 'd': // 2 strings to match.
	"	if (NameR[12] != 'd')
		break;
		switch (NameR[13]) {
		default: break;
		case 'i': // 1 string to match.
		return Intrinsic::hexagon_A2_addi; // "exagon.A2.addi"
		case 'p': // 1 string to match.
		return Intrinsic::hexagon_A2_addp; // "exagon.A2.addp"
		}
		break;
		case 'n': // 1 string to match.
		if (NameR.substr(12, 2) != "dp")
		break;
		return Intrinsic::hexagon_A2_andp; // "exagon.A2.andp"
		case 's': // 2 strings to match.
		switch (NameR[12]) {
		default: break;
		case 'l': // 1 string to match.
		if (NameR[13] != 'h')
		break;
		return Intrinsic::hexagon_A2_aslh; // "exagon.A2.aslh"
		case 'r': // 1 string to match.
		if (NameR[13] != 'h')
		break;
		return Intrinsic::hexagon_A2_asrh; // "exagon.A2.asrh"
		}
		break;
	}	}
	break;	break;

	case 'x': // 1 string to match.	case 'm': // 4 strings to match.
	if (NameR[14] != 'l')	switch (NameR[11]) {
		default: break;
		case 'a': // 2 strings to match.
		if (NameR[12] != 'x')
		break;
		switch (NameR[13]) {
		default: break;
		case 'p': // 1 string to match.
		return Intrinsic::hexagon_A2_maxp; // "exagon.A2.maxp"
		case 'u': // 1 string to match.
		return Intrinsic::hexagon_A2_maxu; // "exagon.A2.maxu"
		}
	break;	break;

	return Intrinsic::ppc_altivec_lvxl; // "pc.altivec.lvxl	case 'i': // 2 strings to match.
	"	if (NameR[12] != 'n')
	}	break;
	break;	switch (NameR[13]) {
	case 's': // 1 string to match.	default: break;
	if (NameR.substr(12, 3) != "tvx")	case 'p': // 1 string to match.
	break;	return Intrinsic::hexagon_A2_minp; // "exagon.A2.minp"
	return Intrinsic::ppc_altivec_stvx; // "pc.altivec.stvx"	case 'u': // 1 string to match.
	case 'v': // 12 strings to match.	return Intrinsic::hexagon_A2_minu; // "exagon.A2.minu"
	switch (NameR[12]) {	}
	default: break;
	case 'r': // 3 strings to match.
	if (NameR[13] != 'l')
	break;	break;

	switch (NameR[14]) {
	default: break;
	case 'b': // 1 string to match.
	return Intrinsic::ppc_altivec_vrlb; // "pc.altivec.vrlb
	"
	case 'h': // 1 string to match.
	return Intrinsic::ppc_altivec_vrlh; // "pc.altivec.vrlh
	"
	case 'w': // 1 string to match.
	return Intrinsic::ppc_altivec_vrlw; // "pc.altivec.vrlw
	"
	}	}
	break;	break;

	case 's': // 9 strings to match.	case 'n': // 2 strings to match.
	switch (NameR[13]) {	switch (NameR[11]) {
	default: break;	default: break;
	case 'e': // 1 string to match.	case 'e': // 1 string to match.

	if (NameR[14] != 'l')	if (NameR.substr(12, 2) != "gp")
	break;	break;

	return Intrinsic::ppc_altivec_vsel; // "pc.altivec.vsel	return Intrinsic::hexagon_A2_negp; // "exagon.A2.negp"
	"	case 'o': // 1 string to match.
	case 'l': // 4 strings to match.	if (NameR.substr(12, 2) != "tp")
	switch (NameR[14]) {	break;
		return Intrinsic::hexagon_A2_notp; // "exagon.A2.notp"
		}
		break;
		case 'o': // 1 string to match.
		if (NameR.substr(11, 3) != "rir")
		break;
		return Intrinsic::hexagon_A2_orir; // "exagon.A2.orir"
		case 's': // 7 strings to match.
		switch (NameR[11]) {
		default: break;
		case 'a': // 2 strings to match.
		if (NameR[12] != 't')
		break;
		switch (NameR[13]) {
	default: break;	default: break;
	case 'b': // 1 string to match.	case 'b': // 1 string to match.

	return Intrinsic::ppc_altivec_vslb; // "pc.altivec.vslb "	return Intrinsic::hexagon_A2_satb; // "exagon.A2.satb"
	case 'h': // 1 string to match.	case 'h': // 1 string to match.

	return Intrinsic::ppc_altivec_vslh; // "pc.altivec.vslh	return Intrinsic::hexagon_A2_sath; // "exagon.A2.sath"
	"
	case 'o': // 1 string to match.
	return Intrinsic::ppc_altivec_vslo; // "pc.altivec.vslo
	"
	case 'w': // 1 string to match.
	return Intrinsic::ppc_altivec_vslw; // "pc.altivec.vslw
	"
	}	}
	break;	break;

	case 'r': // 4 strings to match.	case 'u': // 1 string to match.
	switch (NameR[14]) {	if (NameR.substr(12, 2) != "bp")
		break;
		return Intrinsic::hexagon_A2_subp; // "exagon.A2.subp"
		case 'w': // 1 string to match.
		if (NameR.substr(12, 2) != "iz")
		break;
		return Intrinsic::hexagon_A2_swiz; // "exagon.A2.swiz"
		case 'x': // 3 strings to match.
		if (NameR[12] != 't')
		break;
		switch (NameR[13]) {
	default: break;	default: break;
	case 'b': // 1 string to match.	case 'b': // 1 string to match.

	return Intrinsic::ppc_altivec_vsrb; // "pc.altivec.vsrb "	return Intrinsic::hexagon_A2_sxtb; // "exagon.A2.sxtb"
	case 'h': // 1 string to match.	case 'h': // 1 string to match.

	return Intrinsic::ppc_altivec_vsrh; // "pc.altivec.vsrh	return Intrinsic::hexagon_A2_sxth; // "exagon.A2.sxth"
	"
	case 'o': // 1 string to match.
	return Intrinsic::ppc_altivec_vsro; // "pc.altivec.vsro
	"
	case 'w': // 1 string to match.	case 'w': // 1 string to match.

	return Intrinsic::ppc_altivec_vsrw; // "pc.altivec.vsrw "	return Intrinsic::hexagon_A2_sxtw; // "exagon.A2.sxtw"
	}	}
	break;	break;
	}	}
	break;	break;

		case 't': // 1 string to match.
		if (NameR.substr(11, 3) != "frp")
		break;
		return Intrinsic::hexagon_A2_tfrp; // "exagon.A2.tfrp"
		case 'x': // 1 string to match.
		if (NameR.substr(11, 3) != "orp")
		break;
		return Intrinsic::hexagon_A2_xorp; // "exagon.A2.xorp"
		case 'z': // 2 strings to match.
		if (NameR.substr(11, 2) != "xt")
		break;
		switch (NameR[13]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::hexagon_A2_zxtb; // "exagon.A2.zxtb"
		case 'h': // 1 string to match.
		return Intrinsic::hexagon_A2_zxth; // "exagon.A2.zxth"
		}
		break;
		}
		break;
		case '4': // 2 strings to match.
		if (NameR[9] != '.')
		break;
		switch (NameR[10]) {
		default: break;
		case 'a': // 1 string to match.
		if (NameR.substr(11, 3) != "ndn")
		break;
		return Intrinsic::hexagon_A4_andn; // "exagon.A4.andn"
		case 'o': // 1 string to match.
		if (NameR.substr(11, 3) != "rnp")
		break;
		return Intrinsic::hexagon_A4_ornp; // "exagon.A4.ornp"
	}	}
	break;	break;
	}	}
	break;	break;

	case 't': // 6 strings to match.	case 'C': // 5 strings to match.
	if (NameR.substr(1, 7) != "x.read.")	if (NameR.substr(8, 2) != "2.")
	break;	break;

	switch (NameR[8]) {	switch (NameR[10]) {
	default: break;	default: break;

	case 'c': // 5 strings to match.	case 'a': // 3 strings to match.
	switch (NameR[9]) {	switch (NameR[11]) {
	default: break;	default: break;
	case 'l': // 1 string to match.	case 'l': // 1 string to match.

	if (NameR.substr(10, 5) != "ock64")	if (NameR.substr(12, 2) != "l8")
	break;
	return Intrinsic::ptx_read_clock64; // "tx.read.clock64
	"
	case 't': // 4 strings to match.
	if (NameR.substr(10, 4) != "aid.")
	break;	break;

	switch (NameR[14]) {	return Intrinsic::hexagon_C2_all8; // "exagon.C2.all8"
		case 'n': // 2 strings to match.
		switch (NameR[12]) {
	default: break;	default: break;

	case 'w': // 1 string to match.	case 'd': // 1 string to match.
	return Intrinsic::ptx_read_ctaid_w; // "tx.read.ctaid.w	if (NameR[13] != 'n')
	"	break;
	case 'x': // 1 string to match.	return Intrinsic::hexagon_C2_andn; // "exagon.C2.andn"
	return Intrinsic::ptx_read_ctaid_x; // "tx.read.ctaid.x
	"
	case 'y': // 1 string to match.	case 'y': // 1 string to match.

	return Intrinsic::ptx_read_ctaid_y; // "tx.read.ctaid.y	if (NameR[13] != '8')
	"	break;
	case 'z': // 1 string to match.	return Intrinsic::hexagon_C2_any8; // "exagon.C2.any8"
	return Intrinsic::ptx_read_ctaid_z; // "tx.read.ctaid.z
	"
	}	}
	break;	break;
	}	}
	break;	break;

	case 'n': // 1 string to match.	case 'm': // 1 string to match.
	if (NameR.substr(9, 6) != "warpid")	if (NameR.substr(11, 3) != "ask")
	break;	break;

	return Intrinsic::ptx_read_nwarpid; // "tx.read.nwarpid"	return Intrinsic::hexagon_C2_mask; // "exagon.C2.mask"
		case 'v': // 1 string to match.
		if (NameR.substr(11, 3) != "mux")
		break;
		return Intrinsic::hexagon_C2_vmux; // "exagon.C2.vmux"
	}	}
	break;	break;

	}	case 'M': // 3 strings to match.
	break;	if (NameR.substr(8, 2) != "2.")
	case 16: // 21 strings to match.
	switch (NameR[0]) {
	default: break;
	case 'p': // 17 strings to match.
	if (NameR.substr(1, 10) != "c.altivec.")
	break;	break;

	switch (NameR[11]) {	switch (NameR[10]) {
	default: break;	default: break;

	case 'd': // 1 string to match.	case 'a': // 1 string to match.
	if (NameR.substr(12, 4) != "stst")	if (NameR.substr(11, 3) != "cci")
	break;
	return Intrinsic::ppc_altivec_dstst; // "pc.altivec.dstst"
	case 'l': // 3 strings to match.
	if (NameR.substr(12, 2) != "ve")
	break;	break;

	switch (NameR[14]) {	return Intrinsic::hexagon_M2_acci; // "exagon.M2.acci"
		case 'm': // 2 strings to match.
		switch (NameR[11]) {
	default: break;	default: break;

	case 'b': // 1 string to match.	case 'a': // 1 string to match.
	if (NameR[15] != 'x')	if (NameR.substr(12, 2) != "ci")
	break;
	return Intrinsic::ppc_altivec_lvebx; // "pc.altivec.lveb
	x"
	case 'h': // 1 string to match.
	if (NameR[15] != 'x')
	break;	break;

	return Intrinsic::ppc_altivec_lvehx; // "pc.altivec.lveh	return Intrinsic::hexagon_M2_maci; // "exagon.M2.maci"
	x"	case 'p': // 1 string to match.
	case 'w': // 1 string to match.	if (NameR.substr(12, 2) != "yi")
	if (NameR[15] != 'x')
	break;	break;

	return Intrinsic::ppc_altivec_lvewx; // "pc.altivec.lvew x"	return Intrinsic::hexagon_M2_mpyi; // "exagon.M2.mpyi"
	}	}
	break;	break;

	case 's': // 1 string to match.	}
	if (NameR.substr(12, 4) != "tvxl")	break;
		case 'S': // 6 strings to match.
		switch (NameR[8]) {
		default: break;
		case '2': // 5 strings to match.
		if (NameR[9] != '.')
	break;	break;

	return Intrinsic::ppc_altivec_stvxl; // "pc.altivec.stvxl"	switch (NameR[10]) {
	case 'v': // 12 strings to match.
	switch (NameR[12]) {
	default: break;	default: break;

	case 'c': // 2 strings to match.	case 'b': // 1 string to match.
	if (NameR[13] != 'f')	if (NameR.substr(11, 3) != "rev")
	break;	break;

	switch (NameR[14]) {	return Intrinsic::hexagon_S2_brev; // "exagon.S2.brev"
		case 'c': // 3 strings to match.
		if (NameR[11] != 'l')
		break;
		switch (NameR[12]) {
	default: break;	default: break;

	case 's': // 1 string to match.	case '0': // 1 string to match.
	if (NameR[15] != 'x')	if (NameR[13] != 'p')
	break;	break;

	return Intrinsic::ppc_altivec_vcfsx; // "pc.altivec.vcfs	return Intrinsic::hexagon_S2_cl0p; // "exagon.S2.cl0p"
	x"	case '1': // 1 string to match.
	case 'u': // 1 string to match.	if (NameR[13] != 'p')
	if (NameR[15] != 'x')
	break;	break;

	return Intrinsic::ppc_altivec_vcfux; // "pc.altivec.vcfu	return Intrinsic::hexagon_S2_cl1p; // "exagon.S2.cl1p"
	x"	case 'b': // 1 string to match.
		if (NameR[13] != 'p')
		break;
		return Intrinsic::hexagon_S2_clbp; // "exagon.S2.clbp"
	}	}
	break;	break;

	case 'p': // 2 strings to match.	case 'l': // 1 string to match.
	switch (NameR[13]) {	if (NameR.substr(11, 3) != "fsp")
	default: break;
	case 'e': // 1 string to match.
	if (NameR.substr(14, 2) != "rm")
	break;
	return Intrinsic::ppc_altivec_vperm; // "pc.altivec.vper
	m"
	case 'k': // 1 string to match.
	if (NameR.substr(14, 2) != "px")
	break;
	return Intrinsic::ppc_altivec_vpkpx; // "pc.altivec.vpkp
	x"
	}
	break;
	case 'r': // 5 strings to match.
	switch (NameR[13]) {
	default: break;
	case 'e': // 1 string to match.
	if (NameR.substr(14, 2) != "fp")
	break;
	return Intrinsic::ppc_altivec_vrefp; // "pc.altivec.vref
	p"
	case 'f': // 4 strings to match.
	if (NameR[14] != 'i')
	break;
	switch (NameR[15]) {
	default: break;
	case 'm': // 1 string to match.
	return Intrinsic::ppc_altivec_vrfim; // "pc.altivec.vrfi
	m"
	case 'n': // 1 string to match.
	return Intrinsic::ppc_altivec_vrfin; // "pc.altivec.vrfi
	n"
	case 'p': // 1 string to match.
	return Intrinsic::ppc_altivec_vrfip; // "pc.altivec.vrfi
	p"
	case 'z': // 1 string to match.
	return Intrinsic::ppc_altivec_vrfiz; // "pc.altivec.vrfi
	z"
	}
	break;
	}
	break;
	case 's': // 3 strings to match.
	if (NameR.substr(13, 2) != "ra")
	break;	break;

	switch (NameR[15]) {	return Intrinsic::hexagon_S2_lfsp; // "exagon.S2.lfsp"
	default: break;
	case 'b': // 1 string to match.
	return Intrinsic::ppc_altivec_vsrab; // "pc.altivec.vsra
	b"
	case 'h': // 1 string to match.
	return Intrinsic::ppc_altivec_vsrah; // "pc.altivec.vsra
	h"
	case 'w': // 1 string to match.
	return Intrinsic::ppc_altivec_vsraw; // "pc.altivec.vsra
	w"
	}
	break;
	}	}
	break;	break;

	}	case '4': // 1 string to match.
	break;	if (NameR.substr(9, 5) != ".ornp")
	case 't': // 4 strings to match.	break;
	if (NameR.substr(1, 14) != "x.read.nctaid.")	return Intrinsic::hexagon_S4_ornp; // "exagon.S4.ornp"
	break;
	switch (NameR[15]) {
	default: break;
	case 'w': // 1 string to match.
	return Intrinsic::ptx_read_nctaid_w; // "tx.read.nctaid.w"
	case 'x': // 1 string to match.
	return Intrinsic::ptx_read_nctaid_x; // "tx.read.nctaid.x"
	case 'y': // 1 string to match.
	return Intrinsic::ptx_read_nctaid_y; // "tx.read.nctaid.y"
	case 'z': // 1 string to match.
	return Intrinsic::ptx_read_nctaid_z; // "tx.read.nctaid.z"
	}	}
	break;	break;
	}	}
	break;	break;

	case 17: // 29 strings to match.	case 15: // 40 strings to match.
	if (NameR.substr(0, 11) != "pc.altivec.")	if (NameR.substr(0, 7) != "exagon.")
	break;	break;

	switch (NameR[11]) {	switch (NameR[7]) {
	default: break;	default: break;

	case 'd': // 2 strings to match.	case 'A': // 25 strings to match.
	if (NameR[12] != 's')	switch (NameR[8]) {
	break;
	switch (NameR[13]) {
	default: break;
	case 's': // 1 string to match.
	if (NameR.substr(14, 3) != "all")
	break;
	return Intrinsic::ppc_altivec_dssall; // "pc.altivec.dssa
	ll"
	case 't': // 1 string to match.
	if (NameR.substr(14, 3) != "stt")
	break;
	return Intrinsic::ppc_altivec_dststt; // "pc.altivec.dsts
	tt"
	}
	break;
	case 'm': // 2 strings to match.
	switch (NameR[12]) {
	default: break;
	case 'f': // 1 string to match.
	if (NameR.substr(13, 4) != "vscr")
	break;
	return Intrinsic::ppc_altivec_mfvscr; // "pc.altivec.mfvs
	cr"
	case 't': // 1 string to match.
	if (NameR.substr(13, 4) != "vscr")
	break;
	return Intrinsic::ppc_altivec_mtvscr; // "pc.altivec.mtvs
	cr"
	}
	break;
	case 's': // 3 strings to match.
	if (NameR.substr(12, 3) != "tve")
	break;
	switch (NameR[15]) {
	default: break;
	case 'b': // 1 string to match.
	if (NameR[16] != 'x')
	break;
	return Intrinsic::ppc_altivec_stvebx; // "pc.altivec.stve
	bx"
	case 'h': // 1 string to match.
	if (NameR[16] != 'x')
	break;
	return Intrinsic::ppc_altivec_stvehx; // "pc.altivec.stve
	hx"
	case 'w': // 1 string to match.
	if (NameR[16] != 'x')
	break;
	return Intrinsic::ppc_altivec_stvewx; // "pc.altivec.stve
	wx"
	}
	break;
	case 'v': // 22 strings to match.
	switch (NameR[12]) {
	default: break;	default: break;

	case 'a': // 6 strings to match.	case '2': // 24 strings to match.
	if (NameR.substr(13, 2) != "vg")	if (NameR[9] != '.')
	break;	break;

	switch (NameR[15]) {	switch (NameR[10]) {
	default: break;	default: break;

	case 's': // 3 strings to match.	case 'a': // 2 strings to match.
	switch (NameR[16]) {	switch (NameR[11]) {
	default: break;	default: break;

	case 'b': // 1 string to match.	case 'd': // 1 string to match.
	return Intrinsic::ppc_altivec_vavgsb; // "pc.altivec.vavg	if (NameR.substr(12, 3) != "dsp")
	sb"	break;
	case 'h': // 1 string to match.	return Intrinsic::hexagon_A2_addsp; // "exagon.A2.addsp
	return Intrinsic::ppc_altivec_vavgsh; // "pc.altivec.vavg	"
	sh"	case 'n': // 1 string to match.
	case 'w': // 1 string to match.	if (NameR.substr(12, 3) != "dir")
	return Intrinsic::ppc_altivec_vavgsw; // "pc.altivec.vavg	break;
	sw"	return Intrinsic::hexagon_A2_andir; // "exagon.A2.andir
		"
	}	}
	break;	break;

	case 'u': // 3 strings to match.	case 'm': // 2 strings to match.
	switch (NameR[16]) {	switch (NameR[11]) {
	default: break;	default: break;

	case 'b': // 1 string to match.	case 'a': // 1 string to match.
	return Intrinsic::ppc_altivec_vavgub; // "pc.altivec.vavg	if (NameR.substr(12, 3) != "xup")
	ub"	break;
	case 'h': // 1 string to match.	return Intrinsic::hexagon_A2_maxup; // "exagon.A2.maxup
	return Intrinsic::ppc_altivec_vavguh; // "pc.altivec.vavg	"
	uh"	case 'i': // 1 string to match.
	case 'w': // 1 string to match.	if (NameR.substr(12, 3) != "nup")
	return Intrinsic::ppc_altivec_vavguw; // "pc.altivec.vavg	break;
	uw"	return Intrinsic::hexagon_A2_minup; // "exagon.A2.minup
		"
	}	}
	break;	break;

	}	case 's': // 3 strings to match.
	break;	switch (NameR[11]) {
	case 'c': // 2 strings to match.
	if (NameR[13] != 't')
	break;
	switch (NameR[14]) {
	default: break;
	case 's': // 1 string to match.
	if (NameR.substr(15, 2) != "xs")
	break;
	return Intrinsic::ppc_altivec_vctsxs; // "pc.altivec.vcts
	xs"
	case 'u': // 1 string to match.
	if (NameR.substr(15, 2) != "xs")
	break;
	return Intrinsic::ppc_altivec_vctuxs; // "pc.altivec.vctu
	xs"
	}
	break;
	case 'm': // 14 strings to match.
	switch (NameR[13]) {
	default: break;
	case 'a': // 7 strings to match.
	if (NameR[14] != 'x')
	break;
	switch (NameR[15]) {
	default: break;	default: break;

	case 'f': // 1 string to match.	case 'a': // 2 strings to match.
	if (NameR[16] != 'p')	if (NameR.substr(12, 2) != "tu")
	break;	break;

	return Intrinsic::ppc_altivec_vmaxfp; // "pc.altivec.vmax	switch (NameR[14]) {
	fp"
	case 's': // 3 strings to match.
	switch (NameR[16]) {
	default: break;
	case 'b': // 1 string to match.
	return Intrinsic::ppc_altivec_vmaxsb; // "pc.altivec.vmax
	sb"
	case 'h': // 1 string to match.
	return Intrinsic::ppc_altivec_vmaxsh; // "pc.altivec.vmax
	sh"
	case 'w': // 1 string to match.
	return Intrinsic::ppc_altivec_vmaxsw; // "pc.altivec.vmax
	sw"
	}
	break;
	case 'u': // 3 strings to match.
	switch (NameR[16]) {
	default: break;	default: break;
	case 'b': // 1 string to match.	case 'b': // 1 string to match.

	return Intrinsic::ppc_altivec_vmaxub; // "pc.altivec.vmax ub"	return Intrinsic::hexagon_A2_satub; // "exagon.A2.satub "
	case 'h': // 1 string to match.	case 'h': // 1 string to match.

	return Intrinsic::ppc_altivec_vmaxuh; // "pc.altivec.vmax	return Intrinsic::hexagon_A2_satuh; // "exagon.A2.satuh
	uh"	"
	case 'w': // 1 string to match.
	return Intrinsic::ppc_altivec_vmaxuw; // "pc.altivec.vmax
	uw"
	}	}
	break;	break;

		case 'u': // 1 string to match.
		if (NameR.substr(12, 3) != "bri")
		break;
		return Intrinsic::hexagon_A2_subri; // "exagon.A2.subri
		"
	}	}
	break;	break;

	case 'i': // 7 strings to match.	case 't': // 4 strings to match.
	if (NameR[14] != 'n')	if (NameR.substr(11, 2) != "fr")
	break;	break;

	switch (NameR[15]) {	switch (NameR[13]) {
	default: break;	default: break;

	case 'f': // 1 string to match.	case 'i': // 2 strings to match.
	if (NameR[16] != 'p')	switch (NameR[14]) {
	break;
	return Intrinsic::ppc_altivec_vminfp; // "pc.altivec.vmin
	fp"
	case 's': // 3 strings to match.
	switch (NameR[16]) {
	default: break;
	case 'b': // 1 string to match.
	return Intrinsic::ppc_altivec_vminsb; // "pc.altivec.vmin
	sb"
	case 'h': // 1 string to match.
	return Intrinsic::ppc_altivec_vminsh; // "pc.altivec.vmin
	sh"
	case 'w': // 1 string to match.
	return Intrinsic::ppc_altivec_vminsw; // "pc.altivec.vmin
	sw"
	}
	break;
	case 'u': // 3 strings to match.
	switch (NameR[16]) {
	default: break;	default: break;

	case 'b': // 1 string to match.
	return Intrinsic::ppc_altivec_vminub; // "pc.altivec.vmin
	ub"
	case 'h': // 1 string to match.	case 'h': // 1 string to match.

	return Intrinsic::ppc_altivec_vminuh; // "pc.altivec.vmin	return Intrinsic::hexagon_A2_tfrih; // "exagon.A2.tfrih
	uh"	"
	case 'w': // 1 string to match.	case 'l': // 1 string to match.
	return Intrinsic::ppc_altivec_vminuw; // "pc.altivec.vmin	return Intrinsic::hexagon_A2_tfril; // "exagon.A2.tfril
	uw"	"
	}	}
	break;	break;

		case 'p': // 1 string to match.
		if (NameR[14] != 'i')
		break;
		return Intrinsic::hexagon_A2_tfrpi; // "exagon.A2.tfrpi
		"
		case 's': // 1 string to match.
		if (NameR[14] != 'i')
		break;
		return Intrinsic::hexagon_A2_tfrsi; // "exagon.A2.tfrsi
		"
	}	}
	break;	break;

	}	case 'v': // 13 strings to match.
	break;	switch (NameR[11]) {
	}
	break;
	}
	break;
	case 18: // 38 strings to match.
	if (NameR.substr(0, 12) != "pc.altivec.v")
	break;
	switch (NameR[12]) {
	default: break;
	case 'a': // 7 strings to match.
	if (NameR.substr(13, 2) != "dd")
	break;
	switch (NameR[15]) {
	default: break;
	case 'c': // 1 string to match.
	if (NameR.substr(16, 2) != "uw")
	break;
	return Intrinsic::ppc_altivec_vaddcuw; // "pc.altivec.vadd
	cuw"
	case 's': // 3 strings to match.
	switch (NameR[16]) {
	default: break;
	case 'b': // 1 string to match.
	if (NameR[17] != 's')
	break;
	return Intrinsic::ppc_altivec_vaddsbs; // "pc.altivec.vadd
	sbs"
	case 'h': // 1 string to match.
	if (NameR[17] != 's')
	break;
	return Intrinsic::ppc_altivec_vaddshs; // "pc.altivec.vadd
	shs"
	case 'w': // 1 string to match.
	if (NameR[17] != 's')
	break;
	return Intrinsic::ppc_altivec_vaddsws; // "pc.altivec.vadd
	sws"
	}
	break;
	case 'u': // 3 strings to match.
	switch (NameR[16]) {
	default: break;
	case 'b': // 1 string to match.
	if (NameR[17] != 's')
	break;
	return Intrinsic::ppc_altivec_vaddubs; // "pc.altivec.vadd
	ubs"
	case 'h': // 1 string to match.
	if (NameR[17] != 's')
	break;
	return Intrinsic::ppc_altivec_vadduhs; // "pc.altivec.vadd
	uhs"
	case 'w': // 1 string to match.
	if (NameR[17] != 's')
	break;
	return Intrinsic::ppc_altivec_vadduws; // "pc.altivec.vadd
	uws"
	}
	break;
	}
	break;
	case 'c': // 1 string to match.
	if (NameR.substr(13, 5) != "mpbfp")
	break;
	return Intrinsic::ppc_altivec_vcmpbfp; // "pc.altivec.vcmpbfp"
	case 'l': // 1 string to match.
	if (NameR.substr(13, 5) != "ogefp")
	break;
	return Intrinsic::ppc_altivec_vlogefp; // "pc.altivec.vlogefp"
	case 'm': // 9 strings to match.
	switch (NameR[13]) {
	default: break;
	case 'a': // 1 string to match.
	if (NameR.substr(14, 4) != "ddfp")
	break;
	return Intrinsic::ppc_altivec_vmaddfp; // "pc.altivec.vmad
	dfp"
	case 'u': // 8 strings to match.
	if (NameR[14] != 'l')
	break;
	switch (NameR[15]) {
	default: break;
	case 'e': // 4 strings to match.
	switch (NameR[16]) {
	default: break;	default: break;

	case 's': // 2 strings to match.	case 'a': // 6 strings to match.
	switch (NameR[17]) {	switch (NameR[12]) {
	default: break;	default: break;

	case 'b': // 1 string to match.	case 'b': // 2 strings to match.
	return Intrinsic::ppc_altivec_vmulesb; // "pc.altivec.vmul	if (NameR[13] != 's')
	esb"	break;
	case 'h': // 1 string to match.	switch (NameR[14]) {
	return Intrinsic::ppc_altivec_vmulesh; // "pc.altivec.vmul	default: break;
	esh"	case 'h': // 1 string to match.
		return Intrinsic::hexagon_A2_vabsh; // "exagon.A2.vabsh
		"
		case 'w': // 1 string to match.
		return Intrinsic::hexagon_A2_vabsw; // "exagon.A2.vabsw
		"
		}
		break;
		case 'd': // 2 strings to match.
		if (NameR[13] != 'd')
		break;
		switch (NameR[14]) {
		default: break;
		case 'h': // 1 string to match.
		return Intrinsic::hexagon_A2_vaddh; // "exagon.A2.vaddh
		"
		case 'w': // 1 string to match.
		return Intrinsic::hexagon_A2_vaddw; // "exagon.A2.vaddw
		"
		}
		break;
		case 'v': // 2 strings to match.
		if (NameR[13] != 'g')
		break;
		switch (NameR[14]) {
		default: break;
		case 'h': // 1 string to match.
		return Intrinsic::hexagon_A2_vavgh; // "exagon.A2.vavgh
		"
		case 'w': // 1 string to match.
		return Intrinsic::hexagon_A2_vavgw; // "exagon.A2.vavgw
		"
		}
		break;
	}	}
	break;	break;

	case 'u': // 2 strings to match.	case 'c': // 1 string to match.
	switch (NameR[17]) {	if (NameR.substr(12, 3) != "onj")
		break;
		return Intrinsic::hexagon_A2_vconj; // "exagon.A2.vconj
		"
		case 'm': // 4 strings to match.
		switch (NameR[12]) {
	default: break;	default: break;

	case 'b': // 1 string to match.	case 'a': // 2 strings to match.
	return Intrinsic::ppc_altivec_vmuleub; // "pc.altivec.vmul	if (NameR[13] != 'x')
	eub"	break;
	case 'h': // 1 string to match.	switch (NameR[14]) {
	return Intrinsic::ppc_altivec_vmuleuh; // "pc.altivec.vmul	default: break;
	euh"	case 'h': // 1 string to match.
		return Intrinsic::hexagon_A2_vmaxh; // "exagon.A2.vmaxh
		"
		case 'w': // 1 string to match.
		return Intrinsic::hexagon_A2_vmaxw; // "exagon.A2.vmaxw
		"
		}
		break;
		case 'i': // 2 strings to match.
		if (NameR[13] != 'n')
		break;
		switch (NameR[14]) {
		default: break;
		case 'h': // 1 string to match.
		return Intrinsic::hexagon_A2_vminh; // "exagon.A2.vminh
		"
		case 'w': // 1 string to match.
		return Intrinsic::hexagon_A2_vminw; // "exagon.A2.vminw
		"
		}
		break;
	}	}
	break;	break;

	}
	break;
	case 'o': // 4 strings to match.
	switch (NameR[16]) {
	default: break;
	case 's': // 2 strings to match.	case 's': // 2 strings to match.

	switch (NameR[17]) {	if (NameR.substr(12, 2) != "ub")
	default: break;	break;
	case 'b': // 1 string to match.	switch (NameR[14]) {
	return Intrinsic::ppc_altivec_vmulosb; // "pc.altivec.vmul
	osb"
	case 'h': // 1 string to match.
	return Intrinsic::ppc_altivec_vmulosh; // "pc.altivec.vmul
	osh"
	}
	break;
	case 'u': // 2 strings to match.
	switch (NameR[17]) {
	default: break;	default: break;

	case 'b': // 1 string to match.
	return Intrinsic::ppc_altivec_vmuloub; // "pc.altivec.vmul
	oub"
	case 'h': // 1 string to match.	case 'h': // 1 string to match.

	return Intrinsic::ppc_altivec_vmulouh; // "pc.altivec.vmul	return Intrinsic::hexagon_A2_vsubh; // "exagon.A2.vsubh
	ouh"	"
		case 'w': // 1 string to match.
		return Intrinsic::hexagon_A2_vsubw; // "exagon.A2.vsubw
		"
	}	}
	break;	break;
	}	}
	break;	break;
	}	}
	break;	break;

		case '4': // 1 string to match.
		if (NameR.substr(9, 6) != ".andnp")
		break;
		return Intrinsic::hexagon_A4_andnp; // "exagon.A4.andnp"
	}	}
	break;	break;

	case 'p': // 6 strings to match.	case 'C': // 9 strings to match.
	if (NameR[13] != 'k')	switch (NameR[8]) {
	break;
	switch (NameR[14]) {
	default: break;	default: break;

	case 's': // 4 strings to match.	case '2': // 8 strings to match.
	switch (NameR[15]) {	if (NameR[9] != '.')
		break;
		switch (NameR[10]) {
	default: break;	default: break;

	case 'h': // 2 strings to match.	case 'c': // 3 strings to match.
	switch (NameR[16]) {	if (NameR.substr(11, 2) != "mp")
		break;
		switch (NameR[13]) {
	default: break;	default: break;

	case 's': // 1 string to match.	case 'e': // 1 string to match.
	if (NameR[17] != 's')	if (NameR[14] != 'q')
	break;	break;

	return Intrinsic::ppc_altivec_vpkshss; // "pc.altivec.vpks	return Intrinsic::hexagon_C2_cmpeq; // "exagon.C2.cmpeq
	hss"	"
	case 'u': // 1 string to match.	case 'g': // 1 string to match.
	if (NameR[17] != 's')	if (NameR[14] != 't')
	break;	break;

	return Intrinsic::ppc_altivec_vpkshus; // "pc.altivec.vpks	return Intrinsic::hexagon_C2_cmpgt; // "exagon.C2.cmpgt
	hus"	"
		case 'l': // 1 string to match.
		if (NameR[14] != 't')
		break;
		return Intrinsic::hexagon_C2_cmplt; // "exagon.C2.cmplt
		"
	}	}
	break;	break;

	case 'w': // 2 strings to match.	case 'm': // 3 strings to match.
	switch (NameR[16]) {	if (NameR.substr(11, 2) != "ux")
		break;
		switch (NameR[13]) {
	default: break;	default: break;

	case 's': // 1 string to match.	case 'i': // 2 strings to match.
	if (NameR[17] != 's')	switch (NameR[14]) {
		default: break;
		case 'i': // 1 string to match.
		return Intrinsic::hexagon_C2_muxii; // "exagon.C2.muxii
		"
		case 'r': // 1 string to match.
		return Intrinsic::hexagon_C2_muxir; // "exagon.C2.muxir
		"
		}
		break;
		case 'r': // 1 string to match.
		if (NameR[14] != 'i')
	break;	break;

	return Intrinsic::ppc_altivec_vpkswss; // "pc.altivec.vpks	return Intrinsic::hexagon_C2_muxri; // "exagon.C2.muxri
	wss"	"
	case 'u': // 1 string to match.	}
	if (NameR[17] != 's')	break;
		case 't': // 2 strings to match.
		if (NameR.substr(11, 2) != "fr")
		break;
		switch (NameR[13]) {
		default: break;
		case 'p': // 1 string to match.
		if (NameR[14] != 'r')
	break;	break;

	return Intrinsic::ppc_altivec_vpkswus; // "pc.altivec.vpks	return Intrinsic::hexagon_C2_tfrpr; // "exagon.C2.tfrpr
	wus"	"
		case 'r': // 1 string to match.
		if (NameR[14] != 'p')
		break;
		return Intrinsic::hexagon_C2_tfrrp; // "exagon.C2.tfrrp
		"
	}	}
	break;	break;
	}	}
	break;	break;

	case 'u': // 2 strings to match.	case '4': // 1 string to match.
	switch (NameR[15]) {	if (NameR.substr(9, 6) != ".or.or")
		break;
		return Intrinsic::hexagon_C4_or_or; // "exagon.C4.or.or"
		}
		break;
		case 'M': // 5 strings to match.
		switch (NameR[8]) {
		default: break;
		case '2': // 4 strings to match.
		if (NameR[9] != '.')
		break;
		switch (NameR[10]) {
	default: break;	default: break;

	case 'h': // 1 string to match.	case 'a': // 1 string to match.
	if (NameR.substr(16, 2) != "us")	if (NameR.substr(11, 4) != "ccii")
	break;	break;

	return Intrinsic::ppc_altivec_vpkuhus; // "pc.altivec.vpku	return Intrinsic::hexagon_M2_accii; // "exagon.M2.accii
	hus"	"
	case 'w': // 1 string to match.	case 'm': // 1 string to match.
	if (NameR.substr(16, 2) != "us")	if (NameR.substr(11, 4) != "pyui")
	break;	break;

	return Intrinsic::ppc_altivec_vpkuwus; // "pc.altivec.vpku	return Intrinsic::hexagon_M2_mpyui; // "exagon.M2.mpyui
	wus"	"
		case 'n': // 1 string to match.
		if (NameR.substr(11, 4) != "acci")
		break;
		return Intrinsic::hexagon_M2_nacci; // "exagon.M2.nacci
		"
		case 'v': // 1 string to match.
		if (NameR.substr(11, 4) != "mac2")
		break;
		return Intrinsic::hexagon_M2_vmac2; // "exagon.M2.vmac2
		"
	}	}
	break;	break;

		case '4': // 1 string to match.
		if (NameR.substr(9, 6) != ".or.or")
		break;
		return Intrinsic::hexagon_M4_or_or; // "exagon.M4.or.or"
	}	}
	break;	break;

	case 's': // 8 strings to match.	case 'S': // 1 string to match.
	if (NameR[13] != 'u')	if (NameR.substr(8, 7) != "4.andnp")
	break;	break;

	switch (NameR[14]) {	return Intrinsic::hexagon_S4_andnp; // "exagon.S4.andnp"
		}
		break;
		case 16: // 58 strings to match.
		if (NameR.substr(0, 7) != "exagon.")
		break;
		switch (NameR[7]) {
		default: break;
		case 'A': // 27 strings to match.
		switch (NameR[8]) {
	default: break;	default: break;

	case 'b': // 7 strings to match.	case '2': // 26 strings to match.
	switch (NameR[15]) {	if (NameR[9] != '.')
		break;
		switch (NameR[10]) {
	default: break;	default: break;

	case 'c': // 1 string to match.	case 'a': // 2 strings to match.
	if (NameR.substr(16, 2) != "uw")	switch (NameR[11]) {
	break;
	return Intrinsic::ppc_altivec_vsubcuw; // "pc.altivec.vsub
	cuw"
	case 's': // 3 strings to match.
	switch (NameR[16]) {
	default: break;	default: break;
	case 'b': // 1 string to match.	case 'b': // 1 string to match.

	if (NameR[17] != 's')	if (NameR.substr(12, 4) != "ssat")
	break;
	return Intrinsic::ppc_altivec_vsubsbs; // "pc.altivec.vsub
	sbs"
	case 'h': // 1 string to match.
	if (NameR[17] != 's')
	break;	break;

	return Intrinsic::ppc_altivec_vsubshs; // "pc.altivec.vsub	return Intrinsic::hexagon_A2_abssat; // "exagon.A2.abssa
	shs"	t"
	case 'w': // 1 string to match.	case 'd': // 1 string to match.
	if (NameR[17] != 's')	if (NameR.substr(12, 4) != "dsat")
	break;	break;

	return Intrinsic::ppc_altivec_vsubsws; // "pc.altivec.vsub sws"	return Intrinsic::hexagon_A2_addsat; // "exagon.A2.addsa t"
	}	}
	break;	break;

	case 'u': // 3 strings to match.	case 'n': // 1 string to match.
	switch (NameR[16]) {	if (NameR.substr(11, 5) != "egsat")
	default: break;
	case 'b': // 1 string to match.
	if (NameR[17] != 's')
	break;
	return Intrinsic::ppc_altivec_vsububs; // "pc.altivec.vsub
	ubs"
	case 'h': // 1 string to match.
	if (NameR[17] != 's')
	break;
	return Intrinsic::ppc_altivec_vsubuhs; // "pc.altivec.vsub
	uhs"
	case 'w': // 1 string to match.
	if (NameR[17] != 's')
	break;
	return Intrinsic::ppc_altivec_vsubuws; // "pc.altivec.vsub
	uws"
	}
	break;
	}
	break;
	case 'm': // 1 string to match.
	if (NameR.substr(15, 3) != "sws")
	break;
	return Intrinsic::ppc_altivec_vsumsws; // "pc.altivec.vsum
	sws"
	}
	break;
	case 'u': // 6 strings to match.
	if (NameR.substr(13, 2) != "pk")
	break;
	switch (NameR[15]) {
	default: break;
	case 'h': // 3 strings to match.
	switch (NameR[16]) {
	default: break;
	case 'p': // 1 string to match.
	if (NameR[17] != 'x')
	break;
	return Intrinsic::ppc_altivec_vupkhpx; // "pc.altivec.vupk
	hpx"
	case 's': // 2 strings to match.
	switch (NameR[17]) {
	default: break;
	case 'b': // 1 string to match.
	return Intrinsic::ppc_altivec_vupkhsb; // "pc.altivec.vupk
	hsb"
	case 'h': // 1 string to match.
	return Intrinsic::ppc_altivec_vupkhsh; // "pc.altivec.vupk
	hsh"
	}
	break;
	}
	break;
	case 'l': // 3 strings to match.
	switch (NameR[16]) {
	default: break;
	case 'p': // 1 string to match.
	if (NameR[17] != 'x')
	break;
	return Intrinsic::ppc_altivec_vupklpx; // "pc.altivec.vupk
	lpx"
	case 's': // 2 strings to match.
	switch (NameR[17]) {
	default: break;
	case 'b': // 1 string to match.
	return Intrinsic::ppc_altivec_vupklsb; // "pc.altivec.vupk
	lsb"
	case 'h': // 1 string to match.
	return Intrinsic::ppc_altivec_vupklsh; // "pc.altivec.vupk
	lsh"
	}
	break;
	}
	break;
	}
	break;
	}
	break;
	case 19: // 29 strings to match.
	switch (NameR[0]) {
	default: break;
	case 'p': // 24 strings to match.
	if (NameR.substr(1, 11) != "c.altivec.v")
	break;
	switch (NameR[12]) {
	default: break;
	case 'c': // 12 strings to match.
	if (NameR.substr(13, 2) != "mp")
	break;
	switch (NameR[15]) {
	default: break;
	case 'e': // 4 strings to match.
	if (NameR[16] != 'q')
	break;	break;

	switch (NameR[17]) {	return Intrinsic::hexagon_A2_negsat; // "exagon.A2.negsa
		t"
		case 's': // 4 strings to match.
		switch (NameR[11]) {
	default: break;	default: break;

	case 'f': // 1 string to match.	case 'u': // 1 string to match.
	if (NameR[18] != 'p')	if (NameR.substr(12, 4) != "bsat")
	break;	break;

	return Intrinsic::ppc_altivec_vcmpeqfp; // "pc.altivec.vcmp	return Intrinsic::hexagon_A2_subsat; // "exagon.A2.subsa
	eqfp"	t"
	case 'u': // 3 strings to match.	case 'v': // 3 strings to match.
	switch (NameR[18]) {	switch (NameR[12]) {
	default: break;	default: break;

	case 'b': // 1 string to match.	case 'a': // 2 strings to match.
	return Intrinsic::ppc_altivec_vcmpequb; // "pc.alti	switch (NameR[13]) {
	vec.vcmpequb"	default: break;
	case 'h': // 1 string to match.	case 'd': // 1 string to match.
	return Intrinsic::ppc_altivec_vcmpequh; // "pc.alti	if (NameR.substr(14, 2) != "dh")
	vec.vcmpequh"	break;
	case 'w': // 1 string to match.	return Intrinsic::hexagon_A2_svaddh; // "exagon.A2.svadd
	return Intrinsic::ppc_altivec_vcmpequw; // "pc.alti	h"
	vec.vcmpequw"	case 'v': // 1 string to match.
		if (NameR.substr(14, 2) != "gh")
		break;
		return Intrinsic::hexagon_A2_svavgh; // "exagon.A2.svavg
		h"
		}
		break;
		case 's': // 1 string to match.
		if (NameR.substr(13, 3) != "ubh")
		break;
		return Intrinsic::hexagon_A2_svsubh; // "exagon.A2.svsub
		h"
	}	}
	break;	break;
	}	}
	break;	break;

	case 'g': // 8 strings to match.	case 'v': // 19 strings to match.
	switch (NameR[16]) {	switch (NameR[11]) {
	default: break;	default: break;

	case 'e': // 1 string to match.	case 'a': // 8 strings to match.
	if (NameR.substr(17, 2) != "fp")	switch (NameR[12]) {
		default: break;
		case 'd': // 3 strings to match.
		if (NameR[13] != 'd')
		break;
		switch (NameR[14]) {
		default: break;
		case 'h': // 1 string to match.
		if (NameR[15] != 's')
		break;
		return Intrinsic::hexagon_A2_vaddhs; // "exagon.A2.vaddh
		s"
		case 'u': // 1 string to match.
		if (NameR[15] != 'b')
		break;
		return Intrinsic::hexagon_A2_vaddub; // "exagon.A2.vaddu
		b"
		case 'w': // 1 string to match.
		if (NameR[15] != 's')
		break;
		return Intrinsic::hexagon_A2_vaddws; // "exagon.A2.vaddw
		s"
		}
	break;	break;

	return Intrinsic::ppc_altivec_vcmpgefp; // "pc.altivec.vcmp	case 'v': // 5 strings to match.
	gefp"	if (NameR[13] != 'g')
	case 't': // 7 strings to match.	break;
	switch (NameR[17]) {	switch (NameR[14]) {
		default: break;
		case 'h': // 1 string to match.
		if (NameR[15] != 'r')
		break;
		return Intrinsic::hexagon_A2_vavghr; // "exagon.A2.vavgh
		r"
		case 'u': // 3 strings to match.
		switch (NameR[15]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::hexagon_A2_vavgub; // "exagon.
		A2.vavgub"
		case 'h': // 1 string to match.
		return Intrinsic::hexagon_A2_vavguh; // "exagon.
		A2.vavguh"
		case 'w': // 1 string to match.
		return Intrinsic::hexagon_A2_vavguw; // "exagon.
		A2.vavguw"
		}
		break;
		case 'w': // 1 string to match.
		if (NameR[15] != 'r')
		break;
		return Intrinsic::hexagon_A2_vavgwr; // "exagon.A2.vavgw
		r"
		}
		break;
		}
		break;
		case 'm': // 6 strings to match.
		switch (NameR[12]) {
	default: break;	default: break;

	case 'f': // 1 string to match.	case 'a': // 3 strings to match.
	if (NameR[18] != 'p')	if (NameR.substr(13, 2) != "xu")
	break;	break;

	return Intrinsic::ppc_altivec_vcmpgtfp; // "pc.alti	switch (NameR[15]) {
	vec.vcmpgtfp"
	case 's': // 3 strings to match.
	switch (NameR[18]) {
	default: break;	default: break;
	case 'b': // 1 string to match.	case 'b': // 1 string to match.

	return Intrinsic::ppc_altivec_vcmpgtsb; // "pc.alti vec.vcmpgtsb"	return Intrinsic::hexagon_A2_vmaxub; // "exagon.A2.vmaxu b"
	case 'h': // 1 string to match.	case 'h': // 1 string to match.

	return Intrinsic::ppc_altivec_vcmpgtsh; // "pc.alti vec.vcmpgtsh"	return Intrinsic::hexagon_A2_vmaxuh; // "exagon.A2.vmaxu h"
	case 'w': // 1 string to match.	case 'w': // 1 string to match.

	return Intrinsic::ppc_altivec_vcmpgtsw; // "pc.alti vec.vcmpgtsw"	return Intrinsic::hexagon_A2_vmaxuw; // "exagon.A2.vmaxu w"
	}	}
	break;	break;

	case 'u': // 3 strings to match.	case 'i': // 3 strings to match.
	switch (NameR[18]) {	if (NameR.substr(13, 2) != "nu")
		break;
		switch (NameR[15]) {
	default: break;	default: break;
	case 'b': // 1 string to match.	case 'b': // 1 string to match.

	return Intrinsic::ppc_altivec_vcmpgtub; // "pc.alti vec.vcmpgtub"	return Intrinsic::hexagon_A2_vminub; // "exagon.A2.vminu b"
	case 'h': // 1 string to match.	case 'h': // 1 string to match.

	return Intrinsic::ppc_altivec_vcmpgtuh; // "pc.alti vec.vcmpgtuh"	return Intrinsic::hexagon_A2_vminuh; // "exagon.A2.vminu h"
	case 'w': // 1 string to match.	case 'w': // 1 string to match.

	return Intrinsic::ppc_altivec_vcmpgtuw; // "pc.alti vec.vcmpgtuw"	return Intrinsic::hexagon_A2_vminuw; // "exagon.A2.vminu w"
	}	}
	break;	break;
	}	}
	break;	break;

		case 'n': // 2 strings to match.
		if (NameR.substr(12, 3) != "avg")
		break;
		switch (NameR[15]) {
		default: break;
		case 'h': // 1 string to match.
		return Intrinsic::hexagon_A2_vnavgh; // "exagon.A2.vnavg
		h"
		case 'w': // 1 string to match.
		return Intrinsic::hexagon_A2_vnavgw; // "exagon.A2.vnavg
		w"
		}
		break;
		case 's': // 3 strings to match.
		if (NameR.substr(12, 2) != "ub")
		break;
		switch (NameR[14]) {
		default: break;
		case 'h': // 1 string to match.
		if (NameR[15] != 's')
		break;
		return Intrinsic::hexagon_A2_vsubhs; // "exagon.A2.vsubh
		s"
		case 'u': // 1 string to match.
		if (NameR[15] != 'b')
		break;
		return Intrinsic::hexagon_A2_vsubub; // "exagon.A2.vsubu
		b"
		case 'w': // 1 string to match.
		if (NameR[15] != 's')
		break;
		return Intrinsic::hexagon_A2_vsubws; // "exagon.A2.vsubw
		s"
		}
		break;
	}	}
	break;	break;
	}	}
	break;	break;

	case 'e': // 1 string to match.	case '4': // 1 string to match.
	if (NameR.substr(13, 6) != "xptefp")	if (NameR.substr(9, 7) != ".rcmpeq")
	break;	break;

	return Intrinsic::ppc_altivec_vexptefp; // "pc.altivec.vexp	return Intrinsic::hexagon_A4_rcmpeq; // "exagon.A4.rcmpeq"
	tefp"	}
	case 'm': // 6 strings to match.	break;
	if (NameR.substr(13, 3) != "sum")	case 'C': // 12 strings to match.
		switch (NameR[8]) {
		default: break;
		case '2': // 7 strings to match.
		if (NameR.substr(9, 4) != ".cmp")
	break;	break;

	switch (NameR[16]) {	switch (NameR[13]) {
	default: break;	default: break;

	case 'm': // 1 string to match.	case 'e': // 2 strings to match.
	if (NameR.substr(17, 2) != "bm")	if (NameR[14] != 'q')
	break;
	return Intrinsic::ppc_altivec_vmsummbm; // "pc.altivec.vmsu
	mmbm"
	case 's': // 2 strings to match.
	if (NameR[17] != 'h')
	break;	break;

	switch (NameR[18]) {	switch (NameR[15]) {
	default: break;	default: break;

	case 'm': // 1 string to match.	case 'i': // 1 string to match.
	return Intrinsic::ppc_altivec_vmsumshm; // "pc.altivec.vmsu	return Intrinsic::hexagon_C2_cmpeqi; // "exagon.C2.cmpeq
	mshm"	i"
	case 's': // 1 string to match.	case 'p': // 1 string to match.
	return Intrinsic::ppc_altivec_vmsumshs; // "pc.altivec.vmsu	return Intrinsic::hexagon_C2_cmpeqp; // "exagon.C2.cmpeq
	mshs"	p"
	}	}
	break;	break;

	case 'u': // 3 strings to match.	case 'g': // 4 strings to match.
	switch (NameR[17]) {	switch (NameR[14]) {
	default: break;	default: break;

	case 'b': // 1 string to match.	case 'e': // 1 string to match.
	if (NameR[18] != 'm')	if (NameR[15] != 'i')
	break;	break;

	return Intrinsic::ppc_altivec_vmsumubm; // "pc.altivec.vmsu	return Intrinsic::hexagon_C2_cmpgei; // "exagon.C2.cmpge
	mubm"	i"
	case 'h': // 2 strings to match.	case 't': // 3 strings to match.
	switch (NameR[18]) {	switch (NameR[15]) {
	default: break;	default: break;

	case 'm': // 1 string to match.	case 'i': // 1 string to match.
	return Intrinsic::ppc_altivec_vmsumuhm; // "pc.alti	return Intrinsic::hexagon_C2_cmpgti; // "exagon.C2.cmpgt
	vec.vmsumuhm"	i"
	case 's': // 1 string to match.	case 'p': // 1 string to match.
	return Intrinsic::ppc_altivec_vmsumuhs; // "pc.alti	return Intrinsic::hexagon_C2_cmpgtp; // "exagon.C2.cmpgt
	vec.vmsumuhs"	p"
		case 'u': // 1 string to match.
		return Intrinsic::hexagon_C2_cmpgtu; // "exagon.C2.cmpgt
		u"
	}	}
	break;	break;
	}	}
	break;	break;

		case 'l': // 1 string to match.
		if (NameR.substr(14, 2) != "tu")
		break;
		return Intrinsic::hexagon_C2_cmpltu; // "exagon.C2.cmplt
		u"
	}	}
	break;	break;

	case 'n': // 1 string to match.	case '4': // 5 strings to match.
	if (NameR.substr(13, 6) != "msubfp")	if (NameR[9] != '.')
	break;
	return Intrinsic::ppc_altivec_vnmsubfp; // "pc.altivec.vnms
	ubfp"
	case 's': // 4 strings to match.
	if (NameR.substr(13, 2) != "um")
	break;	break;

	switch (NameR[15]) {	switch (NameR[10]) {
	default: break;	default: break;

	case '2': // 1 string to match.	case 'a': // 1 string to match.
	if (NameR.substr(16, 3) != "sws")	if (NameR.substr(11, 5) != "nd.or")
	break;	break;

	return Intrinsic::ppc_altivec_vsum2sws; // "pc.altivec.vsum	return Intrinsic::hexagon_C4_and_or; // "exagon.C4.and.o
	2sws"	r"
	case '4': // 3 strings to match.	case 'c': // 2 strings to match.
	switch (NameR[16]) {	if (NameR.substr(11, 2) != "mp")
		break;
		switch (NameR[13]) {
	default: break;	default: break;

	case 's': // 2 strings to match.	case 'l': // 1 string to match.
	switch (NameR[17]) {	if (NameR.substr(14, 2) != "te")
	default: break;	break;
	case 'b': // 1 string to match.	return Intrinsic::hexagon_C4_cmplte; // "exagon.C4.cmplt
	if (NameR[18] != 's')	e"
	break;	case 'n': // 1 string to match.
	return Intrinsic::ppc_altivec_vsum4sbs; // "pc.alti	if (NameR.substr(14, 2) != "eq")
	vec.vsum4sbs"	break;
	case 'h': // 1 string to match.	return Intrinsic::hexagon_C4_cmpneq; // "exagon.C4.cmpne
	if (NameR[18] != 's')	q"
	break;	}
	return Intrinsic::ppc_altivec_vsum4shs; // "pc.alti	break;
	vec.vsum4shs"	case 'o': // 2 strings to match.
	}	if (NameR.substr(11, 2) != "r.")
	break;	break;

	case 'u': // 1 string to match.	switch (NameR[13]) {
	if (NameR.substr(17, 2) != "bs")	default: break;
		case 'a': // 1 string to match.
		if (NameR.substr(14, 2) != "nd")
	break;	break;

	return Intrinsic::ppc_altivec_vsum4ubs; // "pc.altivec.vsum	return Intrinsic::hexagon_C4_or_and; // "exagon.C4.or.an
	4ubs"	d"
		case 'o': // 1 string to match.
		if (NameR.substr(14, 2) != "rn")
		break;
		return Intrinsic::hexagon_C4_or_orn; // "exagon.C4.or.or
		n"
	}	}
	break;	break;
	}	}
	break;	break;
	}	}
	break;	break;

	case 't': // 5 strings to match.	case 'M': // 10 strings to match.
	if (NameR.substr(1, 16) != "x.read.lanemask.")	switch (NameR[8]) {
	break;
	switch (NameR[17]) {
	default: break;	default: break;

	case 'e': // 1 string to match.	case '2': // 6 strings to match.
	if (NameR[18] != 'q')	if (NameR[9] != '.')
	break;	break;

	return Intrinsic::ptx_read_lanemask_eq; // "tx.read.lanemas	switch (NameR[10]) {
	k.eq"
	case 'g': // 2 strings to match.
	switch (NameR[18]) {
	default: break;
	case 'e': // 1 string to match.
	return Intrinsic::ptx_read_lanemask_ge; // "tx.read.lanemas
	k.ge"
	case 't': // 1 string to match.
	return Intrinsic::ptx_read_lanemask_gt; // "tx.read.lanemas
	k.gt"
	}
	break;
	case 'l': // 2 strings to match.
	switch (NameR[18]) {
	default: break;	default: break;

	case 'e': // 1 string to match.	case 'm': // 4 strings to match.
	return Intrinsic::ptx_read_lanemask_le; // "tx.read.lanemas	switch (NameR[11]) {
	k.le"	default: break;
	case 't': // 1 string to match.	case 'a': // 2 strings to match.
	return Intrinsic::ptx_read_lanemask_lt; // "tx.read.lanemas	if (NameR.substr(12, 3) != "csi")
	k.lt"	break;
	}	switch (NameR[15]) {
	break;	default: break;
	}	case 'n': // 1 string to match.
	break;	return Intrinsic::hexagon_M2_macsin; // "exagon.M2.macsi
	}	n"
	break;	case 'p': // 1 string to match.
	case 20: // 4 strings to match.	return Intrinsic::hexagon_M2_macsip; // "exagon.M2.macsi
	if (NameR.substr(0, 12) != "pc.altivec.v")	p"
	break;	}
	switch (NameR[12]) {	break;
	default: break;	case 'p': // 2 strings to match.
	case 'c': // 1 string to match.	if (NameR[12] != 'y')
	if (NameR.substr(13, 7) != "mpbfp.p")	break;
	break;	switch (NameR[13]) {
	return Intrinsic::ppc_altivec_vcmpbfp_p; // "pc.altivec.vcmp	default: break;
	bfp.p"	case '.': // 1 string to match.
	case 'm': // 2 strings to match.	if (NameR.substr(14, 2) != "up")
	switch (NameR[13]) {	break;
	default: break;	return Intrinsic::hexagon_M2_mpy_up; // "exagon.M2.mpy.u
	case 'h': // 1 string to match.	p"
	if (NameR.substr(14, 6) != "addshs")	case 's': // 1 string to match.
	break;	if (NameR.substr(14, 2) != "mi")
	return Intrinsic::ppc_altivec_vmhaddshs; // "pc.altivec.vmha	break;
	ddshs"	return Intrinsic::hexagon_M2_mpysmi; // "exagon.M2.mpysm
	case 'l': // 1 string to match.	i"
	if (NameR.substr(14, 6) != "adduhm")	}
		break;
		}
	break;	break;

	return Intrinsic::ppc_altivec_vmladduhm; // "pc.altivec.vmla	case 'n': // 1 string to match.
	dduhm"	if (NameR.substr(11, 5) != "accii")
	}	break;
	break;	return Intrinsic::hexagon_M2_naccii; // "exagon.M2.nacci
	case 'r': // 1 string to match.	i"
	if (NameR.substr(13, 7) != "sqrtefp")	case 's': // 1 string to match.
	break;	if (NameR.substr(11, 5) != "ubacc")
	return Intrinsic::ppc_altivec_vrsqrtefp; // "pc.altivec.vrsq	break;
	rtefp"	return Intrinsic::hexagon_M2_subacc; // "exagon.M2.subac
	}	c"
	break;	}
	case 21: // 13 strings to match.
	if (NameR.substr(0, 12) != "pc.altivec.v")
	break;
	switch (NameR[12]) {
	default: break;
	case 'c': // 12 strings to match.
	if (NameR.substr(13, 2) != "mp")
	break;	break;

	switch (NameR[15]) {	case '4': // 4 strings to match.
	default: break;	if (NameR[9] != '.')
	case 'e': // 4 strings to match.
	if (NameR[16] != 'q')
	break;	break;

	switch (NameR[17]) {	switch (NameR[10]) {
	default: break;	default: break;

	case 'f': // 1 string to match.	case 'a': // 1 string to match.
	if (NameR.substr(18, 3) != "p.p")	if (NameR.substr(11, 5) != "nd.or")
	break;	break;

	return Intrinsic::ppc_altivec_vcmpeqfp_p; // "pc.altivec.vcmp	return Intrinsic::hexagon_M4_and_or; // "exagon.M4.and.o
	eqfp.p"	r"
	case 'u': // 3 strings to match.	case 'o': // 2 strings to match.
	switch (NameR[18]) {	if (NameR.substr(11, 2) != "r.")
		break;
		switch (NameR[13]) {
	default: break;	default: break;

	case 'b': // 1 string to match.	case 'a': // 1 string to match.
	if (NameR.substr(19, 2) != ".p")	if (NameR.substr(14, 2) != "nd")
	break;
	return Intrinsic::ppc_altivec_vcmpequb_p; // "pc.alti
	vec.vcmpequb.p"
	case 'h': // 1 string to match.
	if (NameR.substr(19, 2) != ".p")
	break;	break;

	return Intrinsic::ppc_altivec_vcmpequh_p; // "pc.alti	return Intrinsic::hexagon_M4_or_and; // "exagon.M4.or.an
	vec.vcmpequh.p"	d"
	case 'w': // 1 string to match.	case 'x': // 1 string to match.
	if (NameR.substr(19, 2) != ".p")	if (NameR.substr(14, 2) != "or")
	break;	break;

	return Intrinsic::ppc_altivec_vcmpequw_p; // "pc.alti vec.vcmpequw.p"	return Intrinsic::hexagon_M4_or_xor; // "exagon.M4.or.xo r"
	}	}
	break;	break;

		case 'x': // 1 string to match.
		if (NameR.substr(11, 5) != "or.or")
		break;
		return Intrinsic::hexagon_M4_xor_or; // "exagon.M4.xor.o
		r"
	}	}
	break;	break;

	case 'g': // 8 strings to match.	}
	switch (NameR[16]) {	break;
		case 'S': // 9 strings to match.
		switch (NameR[8]) {
		default: break;
		case '2': // 8 strings to match.
		if (NameR[9] != '.')
		break;
		switch (NameR[10]) {
	default: break;	default: break;

	case 'e': // 1 string to match.	case 'i': // 1 string to match.
	if (NameR.substr(17, 4) != "fp.p")	if (NameR.substr(11, 5) != "nsert")
	break;	break;

	return Intrinsic::ppc_altivec_vcmpgefp_p; // "pc.altivec.vcmp	return Intrinsic::hexagon_S2_insert; // "exagon.S2.inser
	gefp.p"	t"
	case 't': // 7 strings to match.	case 'p': // 1 string to match.
	switch (NameR[17]) {	if (NameR.substr(11, 5) != "ackhl")
		break;
		return Intrinsic::hexagon_S2_packhl; // "exagon.S2.packh
		l"
		case 'v': // 6 strings to match.
		switch (NameR[11]) {
	default: break;	default: break;

	case 'f': // 1 string to match.	case 's': // 4 strings to match.
	if (NameR.substr(18, 3) != "p.p")	switch (NameR[12]) {
	break;
	return Intrinsic::ppc_altivec_vcmpgtfp_p; // "pc.alti
	vec.vcmpgtfp.p"
	case 's': // 3 strings to match.
	switch (NameR[18]) {
	default: break;	default: break;

	case 'b': // 1 string to match.	case 'a': // 2 strings to match.
	if (NameR.substr(19, 2) != ".p")	if (NameR[13] != 't')
	break;
	return Intrinsic::ppc_altivec_vcmpgtsb_p; // "pc.alti
	vec.vcmpgtsb.p"
	case 'h': // 1 string to match.
	if (NameR.substr(19, 2) != ".p")
	break;	break;

	return Intrinsic::ppc_altivec_vcmpgtsh_p; // "pc.alti	switch (NameR[14]) {
	vec.vcmpgtsh.p"	default: break;
	case 'w': // 1 string to match.	case 'h': // 1 string to match.
	if (NameR.substr(19, 2) != ".p")	if (NameR[15] != 'b')
		break;
		return Intrinsic::hexagon_S2_vsathb; // "exagon.S2.vsath
		b"
		case 'w': // 1 string to match.
		if (NameR[15] != 'h')
		break;
		return Intrinsic::hexagon_S2_vsatwh; // "exagon.S2.vsatw
		h"
		}
		break;
		case 'x': // 2 strings to match.
		if (NameR[13] != 't')
	break;	break;

	return Intrinsic::ppc_altivec_vcmpgtsw_p; // "pc.alti	switch (NameR[14]) {
	vec.vcmpgtsw.p"	default: break;
		case 'b': // 1 string to match.
		if (NameR[15] != 'h')
		break;
		return Intrinsic::hexagon_S2_vsxtbh; // "exagon.S2.vsxtb
		h"
		case 'h': // 1 string to match.
		if (NameR[15] != 'w')
		break;
		return Intrinsic::hexagon_S2_vsxthw; // "exagon.S2.vsxth
		w"
		}
		break;
	}	}
	break;	break;

	case 'u': // 3 strings to match.	case 'z': // 2 strings to match.
	switch (NameR[18]) {	if (NameR.substr(12, 2) != "xt")
		break;
		switch (NameR[14]) {
	default: break;	default: break;
	case 'b': // 1 string to match.	case 'b': // 1 string to match.

	if (NameR.substr(19, 2) != ".p")	if (NameR[15] != 'h')
	break;	break;

	return Intrinsic::ppc_altivec_vcmpgtub_p; // "pc.alti vec.vcmpgtub.p"	return Intrinsic::hexagon_S2_vzxtbh; // "exagon.S2.vzxtb h"
	case 'h': // 1 string to match.	case 'h': // 1 string to match.

	if (NameR.substr(19, 2) != ".p")	if (NameR[15] != 'w')
	break;
	return Intrinsic::ppc_altivec_vcmpgtuh_p; // "pc.alti
	vec.vcmpgtuh.p"
	case 'w': // 1 string to match.
	if (NameR.substr(19, 2) != ".p")
	break;	break;

	return Intrinsic::ppc_altivec_vcmpgtuw_p; // "pc.alti vec.vcmpgtuw.p"	return Intrinsic::hexagon_S2_vzxthw; // "exagon.S2.vzxth w"
	}	}
	break;	break;
	}	}
	break;	break;
	}	}
	break;	break;

		case '4': // 1 string to match.
		if (NameR.substr(9, 7) != ".or.ori")
		break;
		return Intrinsic::hexagon_S4_or_ori; // "exagon.S4.or.ori"
	}	}
	break;	break;

	case 'm': // 1 string to match.
	if (NameR.substr(13, 8) != "hraddshs")
	break;
	return Intrinsic::ppc_altivec_vmhraddshs; // "pc.altivec.vmhr
	addshs"
	}	}
	break;	break;

	}	case 17: // 71 strings to match.
	break; // end of 'p' case.	if (NameR.substr(0, 7) != "exagon.")
	case 'r':
	switch (NameR.size()) {
	default: break;
	case 12: // 1 string to match.
	if (NameR.substr(0, 12) != "eturnaddress")
	break;
	return Intrinsic::returnaddress; // "eturnaddress"
	case 15: // 1 string to match.
	if (NameR.substr(0, 15) != "eadcyclecounter")
	break;
	return Intrinsic::readcyclecounter; // "eadcyclecounter"
	}
	break; // end of 'r' case.
	case 's':
	if (NameR.startswith("add.with.overflow.")) return Intrinsic::sadd_with
	_overflow;
	if (NameR.startswith("in.")) return Intrinsic::sin;
	if (NameR.startswith("mul.with.overflow.")) return Intrinsic::smul_with
	_overflow;
	if (NameR.startswith("qrt.")) return Intrinsic::sqrt;
	if (NameR.startswith("sub.with.overflow.")) return Intrinsic::ssub_with
	_overflow;
	switch (NameR.size()) {
	default: break;
	case 5: // 1 string to match.
	if (NameR.substr(0, 5) != "etjmp")
	break;
	return Intrinsic::setjmp; // "etjmp"
	case 7: // 1 string to match.
	if (NameR.substr(0, 7) != "pu.si.a")
	break;	break;

	return Intrinsic::spu_si_a; // "pu.si.a"	switch (NameR[7]) {
	case 8: // 11 strings to match.
	switch (NameR[0]) {
	default: break;	default: break;

	case 'i': // 1 string to match.	case 'A': // 25 strings to match.
	if (NameR.substr(1, 7) != "gsetjmp")	switch (NameR[8]) {
	break;
	return Intrinsic::sigsetjmp; // "igsetjmp"
	case 'p': // 9 strings to match.
	if (NameR.substr(1, 5) != "u.si.")
	break;
	switch (NameR[6]) {
	default: break;	default: break;

	case 'a': // 2 strings to match.	case '2': // 23 strings to match.
	switch (NameR[7]) {	if (NameR[9] != '.')
		break;
		switch (NameR[10]) {
	default: break;	default: break;

	case 'h': // 1 string to match.	case 'a': // 1 string to match.
	return Intrinsic::spu_si_ah; // "pu.si.ah"	if (NameR.substr(11, 6) != "ddpsat")
	case 'i': // 1 string to match.	break;
	return Intrinsic::spu_si_ai; // "pu.si.ai"	return Intrinsic::hexagon_A2_addpsat; // "exagon.A2.addps
	}	at"
	break;	case 's': // 4 strings to match.
	case 'b': // 1 string to match.	if (NameR[11] != 'v')
	if (NameR[7] != 'g')	break;
		switch (NameR[12]) {
		default: break;
		case 'a': // 2 strings to match.
		switch (NameR[13]) {
		default: break;
		case 'd': // 1 string to match.
		if (NameR.substr(14, 3) != "dhs")
		break;
		return Intrinsic::hexagon_A2_svaddhs; // "exagon.A2.svadd
		hs"
		case 'v': // 1 string to match.
		if (NameR.substr(14, 3) != "ghs")
		break;
		return Intrinsic::hexagon_A2_svavghs; // "exagon.A2.svavg
		hs"
		}
		break;
		case 'n': // 1 string to match.
		if (NameR.substr(13, 4) != "avgh")
		break;
		return Intrinsic::hexagon_A2_svnavgh; // "exagon.A2.svnav
		gh"
		case 's': // 1 string to match.
		if (NameR.substr(13, 4) != "ubhs")
		break;
		return Intrinsic::hexagon_A2_svsubhs; // "exagon.A2.svsub
		hs"
		}
	break;	break;

	return Intrinsic::spu_si_bg; // "pu.si.bg"	case 'v': // 18 strings to match.
	case 'c': // 1 string to match.	switch (NameR[11]) {
	if (NameR[7] != 'g')	default: break;
		case 'a': // 7 strings to match.
		switch (NameR[12]) {
		default: break;
		case 'd': // 2 strings to match.
		if (NameR.substr(13, 2) != "du")
		break;
		switch (NameR[15]) {
		default: break;
		case 'b': // 1 string to match.
		if (NameR[16] != 's')
		break;
		return Intrinsic::hexagon_A2_vaddubs; // "exagon.
		A2.vaddubs"
		case 'h': // 1 string to match.
		if (NameR[16] != 's')
		break;
		return Intrinsic::hexagon_A2_vadduhs; // "exagon.
		A2.vadduhs"
		}
		break;
		case 'v': // 5 strings to match.
		if (NameR[13] != 'g')
		break;
		switch (NameR[14]) {
		default: break;
		case 'h': // 1 string to match.
		if (NameR.substr(15, 2) != "cr")
		break;
		return Intrinsic::hexagon_A2_vavghcr; // "exagon.
		A2.vavghcr"
		case 'u': // 3 strings to match.
		switch (NameR[15]) {
		default: break;
		case 'b': // 1 string to match.
		if (NameR[16] != 'r')
		break;
		return Intrinsic::hexagon_A2_vavgubr; // "exagon.
		A2.vavgubr"
		case 'h': // 1 string to match.
		if (NameR[16] != 'r')
		break;
		return Intrinsic::hexagon_A2_vavguhr; // "exagon.
		A2.vavguhr"
		case 'w': // 1 string to match.
		if (NameR[16] != 'r')
		break;
		return Intrinsic::hexagon_A2_vavguwr; // "exagon.
		A2.vavguwr"
		}
		break;
		case 'w': // 1 string to match.
		if (NameR.substr(15, 2) != "cr")
		break;
		return Intrinsic::hexagon_A2_vavgwcr; // "exagon.
		A2.vavgwcr"
		}
		break;
		}
		break;
		case 'c': // 5 strings to match.
		if (NameR.substr(12, 2) != "mp")
		break;
		switch (NameR[14]) {
		default: break;
		case 'b': // 1 string to match.
		if (NameR.substr(15, 2) != "eq")
		break;
		return Intrinsic::hexagon_A2_vcmpbeq; // "exagon.A2.vcmpb
		eq"
		case 'h': // 2 strings to match.
		switch (NameR[15]) {
		default: break;
		case 'e': // 1 string to match.
		if (NameR[16] != 'q')
		break;
		return Intrinsic::hexagon_A2_vcmpheq; // "exagon.
		A2.vcmpheq"
		case 'g': // 1 string to match.
		if (NameR[16] != 't')
		break;
		return Intrinsic::hexagon_A2_vcmphgt; // "exagon.
		A2.vcmphgt"
		}
		break;
		case 'w': // 2 strings to match.
		switch (NameR[15]) {
		default: break;
		case 'e': // 1 string to match.
		if (NameR[16] != 'q')
		break;
		return Intrinsic::hexagon_A2_vcmpweq; // "exagon.
		A2.vcmpweq"
		case 'g': // 1 string to match.
		if (NameR[16] != 't')
		break;
		return Intrinsic::hexagon_A2_vcmpwgt; // "exagon.
		A2.vcmpwgt"
		}
		break;
		}
		break;
		case 'n': // 2 strings to match.
		if (NameR.substr(12, 3) != "avg")
		break;
		switch (NameR[15]) {
		default: break;
		case 'h': // 1 string to match.
		if (NameR[16] != 'r')
		break;
		return Intrinsic::hexagon_A2_vnavghr; // "exagon.A2.vnavg
		hr"
		case 'w': // 1 string to match.
		if (NameR[16] != 'r')
		break;
		return Intrinsic::hexagon_A2_vnavgwr; // "exagon.A2.vnavg
		wr"
		}
		break;
		case 'r': // 2 strings to match.
		switch (NameR[12]) {
		default: break;
		case 'a': // 1 string to match.
		if (NameR.substr(13, 4) != "ddub")
		break;
		return Intrinsic::hexagon_A2_vraddub; // "exagon.A2.vradd
		ub"
		case 's': // 1 string to match.
		if (NameR.substr(13, 4) != "adub")
		break;
		return Intrinsic::hexagon_A2_vrsadub; // "exagon.A2.vrsad
		ub"
		}
		break;
		case 's': // 2 strings to match.
		if (NameR.substr(12, 3) != "ubu")
		break;
		switch (NameR[15]) {
		default: break;
		case 'b': // 1 string to match.
		if (NameR[16] != 's')
		break;
		return Intrinsic::hexagon_A2_vsububs; // "exagon.A2.vsubu
		bs"
		case 'h': // 1 string to match.
		if (NameR[16] != 's')
		break;
		return Intrinsic::hexagon_A2_vsubuhs; // "exagon.A2.vsubu
		hs"
		}
		break;
		}
	break;	break;

	return Intrinsic::spu_si_cg; // "pu.si.cg"
	case 'f': // 3 strings to match.
	switch (NameR[7]) {
	default: break;
	case 'a': // 1 string to match.
	return Intrinsic::spu_si_fa; // "pu.si.fa"
	case 'm': // 1 string to match.
	return Intrinsic::spu_si_fm; // "pu.si.fm"
	case 's': // 1 string to match.
	return Intrinsic::spu_si_fs; // "pu.si.fs"
	}	}
	break;	break;

	case 'o': // 1 string to match.	case '4': // 2 strings to match.
	if (NameR[7] != 'r')	if (NameR.substr(9, 5) != ".rcmp")
	break;
	return Intrinsic::spu_si_or; // "pu.si.or"
	case 's': // 1 string to match.
	if (NameR[7] != 'f')
	break;	break;

	return Intrinsic::spu_si_sf; // "pu.si.sf"	switch (NameR[14]) {
		default: break;
		case 'e': // 1 string to match.
		if (NameR.substr(15, 2) != "qi")
		break;
		return Intrinsic::hexagon_A4_rcmpeqi; // "exagon.A4.rcmpe
		qi"
		case 'n': // 1 string to match.
		if (NameR.substr(15, 2) != "eq")
		break;
		return Intrinsic::hexagon_A4_rcmpneq; // "exagon.A4.rcmpn
		eq"
		}
		break;
	}	}
	break;	break;

	case 't': // 1 string to match.	case 'C': // 12 strings to match.
	if (NameR.substr(1, 7) != "acksave")	switch (NameR[8]) {
	break;
	return Intrinsic::stacksave; // "tacksave"
	}
	break;
	case 9: // 20 strings to match.
	switch (NameR[0]) {
	default: break;
	case 'i': // 1 string to match.
	if (NameR.substr(1, 8) != "glongjmp")
	break;
	return Intrinsic::siglongjmp; // "iglongjmp"
	case 'p': // 19 strings to match.
	if (NameR.substr(1, 5) != "u.si.")
	break;
	switch (NameR[6]) {
	default: break;	default: break;

	case 'a': // 2 strings to match.	case '2': // 6 strings to match.
	switch (NameR[7]) {	if (NameR[9] != '.')
		break;
		switch (NameR[10]) {
	default: break;	default: break;

	case 'h': // 1 string to match.	case 'b': // 2 strings to match.
	if (NameR[8] != 'i')	if (NameR.substr(11, 3) != "its")
	break;	break;

	return Intrinsic::spu_si_ahi; // "pu.si.ahi"	switch (NameR[14]) {
	case 'n': // 1 string to match.	default: break;
	if (NameR[8] != 'd')	case 'c': // 1 string to match.
		if (NameR.substr(15, 2) != "lr")
		break;
		return Intrinsic::hexagon_C2_bitsclr; // "exagon.C2.bitsc
		lr"
		case 's': // 1 string to match.
		if (NameR.substr(15, 2) != "et")
		break;
		return Intrinsic::hexagon_C2_bitsset; // "exagon.C2.bitss
		et"
		}
		break;
		case 'c': // 3 strings to match.
		if (NameR.substr(11, 3) != "mpg")
	break;	break;

	return Intrinsic::spu_si_and; // "pu.si.and"	switch (NameR[14]) {
		default: break;
		case 'e': // 1 string to match.
		if (NameR.substr(15, 2) != "ui")
		break;
		return Intrinsic::hexagon_C2_cmpgeui; // "exagon.C2.cmpge
		ui"
		case 't': // 2 strings to match.
		if (NameR[15] != 'u')
		break;
		switch (NameR[16]) {
		default: break;
		case 'i': // 1 string to match.
		return Intrinsic::hexagon_C2_cmpgtui; // "exagon.C2.cmpgt
		ui"
		case 'p': // 1 string to match.
		return Intrinsic::hexagon_C2_cmpgtup; // "exagon.C2.cmpgt
		up"
		}
		break;
		}
		break;
		case 'v': // 1 string to match.
		if (NameR.substr(11, 6) != "itpack")
		break;
		return Intrinsic::hexagon_C2_vitpack; // "exagon.C2.vitpa
		ck"
	}	}
	break;	break;

	case 'b': // 1 string to match.	case '4': // 6 strings to match.
	if (NameR.substr(7, 2) != "gx")	if (NameR[9] != '.')
	break;	break;

	return Intrinsic::spu_si_bgx; // "pu.si.bgx"	switch (NameR[10]) {
	case 'c': // 3 strings to match.
	switch (NameR[7]) {
	default: break;	default: break;

	case 'e': // 1 string to match.	case 'a': // 2 strings to match.
	if (NameR[8] != 'q')	if (NameR.substr(11, 3) != "nd.")
	break;	break;

	return Intrinsic::spu_si_ceq; // "pu.si.ceq"	switch (NameR[14]) {
	case 'g': // 2 strings to match.
	switch (NameR[8]) {
	default: break;	default: break;

	case 't': // 1 string to match.	case 'a': // 1 string to match.
	return Intrinsic::spu_si_cgt; // "pu.si.cgt"	if (NameR.substr(15, 2) != "nd")
	case 'x': // 1 string to match.	break;
	return Intrinsic::spu_si_cgx; // "pu.si.cgx"	return Intrinsic::hexagon_C4_and_and; // "exagon.C4.and.a
		nd"
		case 'o': // 1 string to match.
		if (NameR.substr(15, 2) != "rn")
		break;
		return Intrinsic::hexagon_C4_and_orn; // "exagon.C4.and.o
		rn"
		}
		break;
		case 'c': // 3 strings to match.
		if (NameR.substr(11, 2) != "mp")
		break;
		switch (NameR[13]) {
		default: break;
		case 'l': // 2 strings to match.
		if (NameR.substr(14, 2) != "te")
		break;
		switch (NameR[16]) {
		default: break;
		case 'i': // 1 string to match.
		return Intrinsic::hexagon_C4_cmpltei; // "exagon.C4.cmplt
		ei"
		case 'u': // 1 string to match.
		return Intrinsic::hexagon_C4_cmplteu; // "exagon.C4.cmplt
		eu"
		}
		break;
		case 'n': // 1 string to match.
		if (NameR.substr(14, 3) != "eqi")
		break;
		return Intrinsic::hexagon_C4_cmpneqi; // "exagon.C4.cmpne
		qi"
	}	}
	break;	break;

		case 'o': // 1 string to match.
		if (NameR.substr(11, 6) != "r.andn")
		break;
		return Intrinsic::hexagon_C4_or_andn; // "exagon.C4.or.an
		dn"
	}	}
	break;	break;

	case 'd': // 3 strings to match.	}
	if (NameR[7] != 'f')	break;
		case 'M': // 7 strings to match.
		switch (NameR[8]) {
		default: break;
		case '2': // 3 strings to match.
		if (NameR[9] != '.')
	break;	break;

	switch (NameR[8]) {	switch (NameR[10]) {
	default: break;	default: break;

	case 'a': // 1 string to match.
	return Intrinsic::spu_si_dfa; // "pu.si.dfa"
	case 'm': // 1 string to match.	case 'm': // 1 string to match.

	return Intrinsic::spu_si_dfm; // "pu.si.dfm"	if (NameR.substr(11, 6) != "pyu.up")
	case 's': // 1 string to match.	break;
	return Intrinsic::spu_si_dfs; // "pu.si.dfs"	return Intrinsic::hexagon_M2_mpyu_up; // "exagon.M2.mpyu.
		up"
		case 'v': // 2 strings to match.
		switch (NameR[11]) {
		default: break;
		case 'm': // 1 string to match.
		if (NameR.substr(12, 5) != "ac2es")
		break;
		return Intrinsic::hexagon_M2_vmac2es; // "exagon.M2.vmac2
		es"
		case 'r': // 1 string to match.
		if (NameR.substr(12, 5) != "adduh")
		break;
		return Intrinsic::hexagon_M2_vradduh; // "exagon.M2.vradd
		uh"
		}
		break;
	}	}
	break;	break;

	case 'f': // 2 strings to match.	case '4': // 4 strings to match.
	if (NameR[7] != 'm')	if (NameR[9] != '.')
	break;	break;

	switch (NameR[8]) {	switch (NameR[10]) {
	default: break;	default: break;

	case 'a': // 1 string to match.	case 'a': // 2 strings to match.
	return Intrinsic::spu_si_fma; // "pu.si.fma"	if (NameR.substr(11, 3) != "nd.")
	case 's': // 1 string to match.	break;
	return Intrinsic::spu_si_fms; // "pu.si.fms"	switch (NameR[14]) {
		default: break;
		case 'a': // 1 string to match.
		if (NameR.substr(15, 2) != "nd")
		break;
		return Intrinsic::hexagon_M4_and_and; // "exagon.M4.and.a
		nd"
		case 'x': // 1 string to match.
		if (NameR.substr(15, 2) != "or")
		break;
		return Intrinsic::hexagon_M4_and_xor; // "exagon.M4.and.x
		or"
		}
		break;
		case 'o': // 1 string to match.
		if (NameR.substr(11, 6) != "r.andn")
		break;
		return Intrinsic::hexagon_M4_or_andn; // "exagon.M4.or.an
		dn"
		case 'x': // 1 string to match.
		if (NameR.substr(11, 6) != "or.and")
		break;
		return Intrinsic::hexagon_M4_xor_and; // "exagon.M4.xor.a
		nd"
	}	}
	break;	break;

	case 'm': // 1 string to match.	}
	if (NameR.substr(7, 2) != "py")	break;
	break;	case 'S': // 27 strings to match.
	return Intrinsic::spu_si_mpy; // "pu.si.mpy"	switch (NameR[8]) {
	case 'n': // 1 string to match.	default: break;
	if (NameR.substr(7, 2) != "or")	case '2': // 24 strings to match.
	break;	if (NameR[9] != '.')
	return Intrinsic::spu_si_nor; // "pu.si.nor"
	case 'o': // 2 strings to match.
	if (NameR[7] != 'r')
	break;	break;

	switch (NameR[8]) {	switch (NameR[10]) {
	default: break;	default: break;

		case 'a': // 8 strings to match.
		if (NameR[11] != 's')
		break;
		switch (NameR[12]) {
		default: break;
		case 'l': // 4 strings to match.
		if (NameR[13] != '.')
		break;
		switch (NameR[14]) {
		default: break;
		case 'i': // 2 strings to match.
		if (NameR[15] != '.')
		break;
		switch (NameR[16]) {
		default: break;
		case 'p': // 1 string to match.
		return Intrinsic::hexagon_S2_asl_i_p; // "exagon.
		S2.asl.i.p"
		case 'r': // 1 string to match.
		return Intrinsic::hexagon_S2_asl_i_r; // "exagon.
		S2.asl.i.r"
		}
		break;
		case 'r': // 2 strings to match.
		if (NameR[15] != '.')
		break;
		switch (NameR[16]) {
		default: break;
		case 'p': // 1 string to match.
		return Intrinsic::hexagon_S2_asl_r_p; // "exagon.
		S2.asl.r.p"
		case 'r': // 1 string to match.
		return Intrinsic::hexagon_S2_asl_r_r; // "exagon.
		S2.asl.r.r"
		}
		break;
		}
		break;
		case 'r': // 4 strings to match.
		if (NameR[13] != '.')
		break;
		switch (NameR[14]) {
		default: break;
		case 'i': // 2 strings to match.
		if (NameR[15] != '.')
		break;
		switch (NameR[16]) {
		default: break;
		case 'p': // 1 string to match.
		return Intrinsic::hexagon_S2_asr_i_p; // "exagon.
		S2.asr.i.p"
		case 'r': // 1 string to match.
		return Intrinsic::hexagon_S2_asr_i_r; // "exagon.
		S2.asr.i.r"
		}
		break;
		case 'r': // 2 strings to match.
		if (NameR[15] != '.')
		break;
		switch (NameR[16]) {
		default: break;
		case 'p': // 1 string to match.
		return Intrinsic::hexagon_S2_asr_r_p; // "exagon.
		S2.asr.r.p"
		case 'r': // 1 string to match.
		return Intrinsic::hexagon_S2_asr_r_r; // "exagon.
		S2.asr.r.r"
		}
		break;
		}
		break;
		}
		break;
	case 'c': // 1 string to match.	case 'c': // 1 string to match.

	return Intrinsic::spu_si_orc; // "pu.si.orc"	if (NameR.substr(11, 6) != "lbnorm")
		break;
		return Intrinsic::hexagon_S2_clbnorm; // "exagon.S2.clbno
		rm"
	case 'i': // 1 string to match.	case 'i': // 1 string to match.

	return Intrinsic::spu_si_ori; // "pu.si.ori"	if (NameR.substr(11, 6) != "nsertp")
		break;
		return Intrinsic::hexagon_S2_insertp; // "exagon.S2.inser
		tp"
		case 'l': // 6 strings to match.
		if (NameR[11] != 's')
		break;
		switch (NameR[12]) {
		default: break;
		case 'l': // 2 strings to match.
		if (NameR.substr(13, 3) != ".r.")
		break;
		switch (NameR[16]) {
		default: break;
		case 'p': // 1 string to match.
		return Intrinsic::hexagon_S2_lsl_r_p; // "exagon.S2.lsl.r
		.p"
		case 'r': // 1 string to match.
		return Intrinsic::hexagon_S2_lsl_r_r; // "exagon.S2.lsl.r
		.r"
		}
		break;
		case 'r': // 4 strings to match.
		if (NameR[13] != '.')
		break;
		switch (NameR[14]) {
		default: break;
		case 'i': // 2 strings to match.
		if (NameR[15] != '.')
		break;
		switch (NameR[16]) {
		default: break;
		case 'p': // 1 string to match.
		return Intrinsic::hexagon_S2_lsr_i_p; // "exagon.
		S2.lsr.i.p"
		case 'r': // 1 string to match.
		return Intrinsic::hexagon_S2_lsr_i_r; // "exagon.
		S2.lsr.i.r"
		}
		break;
		case 'r': // 2 strings to match.
		if (NameR[15] != '.')
		break;
		switch (NameR[16]) {
		default: break;
		case 'p': // 1 string to match.
		return Intrinsic::hexagon_S2_lsr_r_p; // "exagon.
		S2.lsr.r.p"
		case 'r': // 1 string to match.
		return Intrinsic::hexagon_S2_lsr_r_r; // "exagon.
		S2.lsr.r.r"
		}
		break;
		}
		break;
		}
		break;
		case 'p': // 1 string to match.
		if (NameR.substr(11, 6) != "arityp")
		break;
		return Intrinsic::hexagon_S2_parityp; // "exagon.S2.parit
		yp"
		case 's': // 5 strings to match.
		switch (NameR[11]) {
		default: break;
		case 'h': // 4 strings to match.
		if (NameR.substr(12, 3) != "uff")
		break;
		switch (NameR[15]) {
		default: break;
		case 'e': // 2 strings to match.
		switch (NameR[16]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::hexagon_S2_shuffeb; // "exagon.
		S2.shuffeb"
		case 'h': // 1 string to match.
		return Intrinsic::hexagon_S2_shuffeh; // "exagon.
		S2.shuffeh"
		}
		break;
		case 'o': // 2 strings to match.
		switch (NameR[16]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::hexagon_S2_shuffob; // "exagon.
		S2.shuffob"
		case 'h': // 1 string to match.
		return Intrinsic::hexagon_S2_shuffoh; // "exagon.
		S2.shuffoh"
		}
		break;
		}
		break;
		case 'v': // 1 string to match.
		if (NameR.substr(12, 5) != "sathb")
		break;
		return Intrinsic::hexagon_S2_svsathb; // "exagon.S2.svsat
		hb"
		}
		break;
		case 'v': // 2 strings to match.
		if (NameR.substr(11, 3) != "sat")
		break;
		switch (NameR[14]) {
		default: break;
		case 'h': // 1 string to match.
		if (NameR.substr(15, 2) != "ub")
		break;
		return Intrinsic::hexagon_S2_vsathub; // "exagon.S2.vsath
		ub"
		case 'w': // 1 string to match.
		if (NameR.substr(15, 2) != "uh")
		break;
		return Intrinsic::hexagon_S2_vsatwuh; // "exagon.S2.vsatw
		uh"
		}
		break;
	}	}
	break;	break;

	case 's': // 3 strings to match.	case '4': // 3 strings to match.
	if (NameR[7] != 'f')	if (NameR[9] != '.')
	break;	break;

	switch (NameR[8]) {	switch (NameR[10]) {
	default: break;	default: break;

	case 'h': // 1 string to match.	case 'a': // 1 string to match.
	return Intrinsic::spu_si_sfh; // "pu.si.sfh"	if (NameR.substr(11, 6) != "ddaddi")
	case 'i': // 1 string to match.	break;
	return Intrinsic::spu_si_sfi; // "pu.si.sfi"	return Intrinsic::hexagon_S4_addaddi; // "exagon.S4.addad
	case 'x': // 1 string to match.	di"
	return Intrinsic::spu_si_sfx; // "pu.si.sfx"	case 'o': // 1 string to match.
		if (NameR.substr(11, 6) != "r.andi")
		break;
		return Intrinsic::hexagon_S4_or_andi; // "exagon.S4.or.an
		di"
		case 's': // 1 string to match.
		if (NameR.substr(11, 6) != "ubaddi")
		break;
		return Intrinsic::hexagon_S4_subaddi; // "exagon.S4.subad
		di"
	}	}
	break;	break;

	case 'x': // 1 string to match.
	if (NameR.substr(7, 2) != "or")
	break;
	return Intrinsic::spu_si_xor; // "pu.si.xor"
	}	}
	break;	break;
	}	}
	break;	break;

	case 10: // 26 strings to match.	case 18: // 69 strings to match.
	if (NameR.substr(0, 6) != "pu.si.")	if (NameR.substr(0, 7) != "exagon.")
	break;	break;

	switch (NameR[6]) {	switch (NameR[7]) {
	default: break;	default: break;

	case 'a': // 3 strings to match.	case 'A': // 14 strings to match.
	switch (NameR[7]) {	switch (NameR[8]) {
	default: break;	default: break;

	case 'd': // 1 string to match.	case '2': // 10 strings to match.
	if (NameR.substr(8, 2) != "dx")	if (NameR[9] != '.')
	break;
	return Intrinsic::spu_si_addx; // "pu.si.addx"
	case 'n': // 2 strings to match.
	if (NameR[8] != 'd')
	break;	break;

	switch (NameR[9]) {	switch (NameR[10]) {
	default: break;	default: break;
	case 'c': // 1 string to match.	case 'c': // 1 string to match.

	return Intrinsic::spu_si_andc; // "pu.si.andc"	if (NameR.substr(11, 7) != "ombinew")
	case 'i': // 1 string to match.	break;
	return Intrinsic::spu_si_andi; // "pu.si.andi"	return Intrinsic::hexagon_A2_combinew; // "exagon.A2.combi
	}	new"
	break;	case 's': // 2 strings to match.
	}	if (NameR[11] != 'v')
	break;	break;
	case 'c': // 7 strings to match.	switch (NameR[12]) {
	switch (NameR[7]) {	default: break;
	default: break;	case 'a': // 1 string to match.
	case 'e': // 3 strings to match.	if (NameR.substr(13, 5) != "dduhs")
	if (NameR[8] != 'q')	break;
		return Intrinsic::hexagon_A2_svadduhs; // "exagon.A2.svadd
		uhs"
		case 's': // 1 string to match.
		if (NameR.substr(13, 5) != "ubuhs")
		break;
		return Intrinsic::hexagon_A2_svsubuhs; // "exagon.A2.svsub
		uhs"
		}
		break;
		case 'v': // 7 strings to match.
		switch (NameR[11]) {
		default: break;
		case 'a': // 2 strings to match.
		if (NameR.substr(12, 2) != "bs")
		break;
		switch (NameR[14]) {
		default: break;
		case 'h': // 1 string to match.
		if (NameR.substr(15, 3) != "sat")
		break;
		return Intrinsic::hexagon_A2_vabshsat; // "exagon.A2.vabsh
		sat"
		case 'w': // 1 string to match.
		if (NameR.substr(15, 3) != "sat")
		break;
		return Intrinsic::hexagon_A2_vabswsat; // "exagon.A2.vabsw
		sat"
		}
		break;
		case 'c': // 3 strings to match.
		if (NameR.substr(12, 2) != "mp")
		break;
		switch (NameR[14]) {
		default: break;
		case 'b': // 1 string to match.
		if (NameR.substr(15, 3) != "gtu")
		break;
		return Intrinsic::hexagon_A2_vcmpbgtu; // "exagon.A2.vcmpb
		gtu"
		case 'h': // 1 string to match.
		if (NameR.substr(15, 3) != "gtu")
		break;
		return Intrinsic::hexagon_A2_vcmphgtu; // "exagon.A2.vcmph
		gtu"
		case 'w': // 1 string to match.
		if (NameR.substr(15, 3) != "gtu")
		break;
		return Intrinsic::hexagon_A2_vcmpwgtu; // "exagon.A2.vcmpw
		gtu"
		}
		break;
		case 'n': // 2 strings to match.
		if (NameR.substr(12, 3) != "avg")
		break;
		switch (NameR[15]) {
		default: break;
		case 'h': // 1 string to match.
		if (NameR.substr(16, 2) != "cr")
		break;
		return Intrinsic::hexagon_A2_vnavghcr; // "exagon.A2.vnavg
		hcr"
		case 'w': // 1 string to match.
		if (NameR.substr(16, 2) != "cr")
		break;
		return Intrinsic::hexagon_A2_vnavgwcr; // "exagon.A2.vnavg
		wcr"
		}
		break;
		}
	break;	break;

	switch (NameR[9]) {
	default: break;
	case 'b': // 1 string to match.
	return Intrinsic::spu_si_ceqb; // "pu.si.ceqb"
	case 'h': // 1 string to match.
	return Intrinsic::spu_si_ceqh; // "pu.si.ceqh"
	case 'i': // 1 string to match.
	return Intrinsic::spu_si_ceqi; // "pu.si.ceqi"
	}	}
	break;	break;

	case 'g': // 3 strings to match.	case '4': // 4 strings to match.
	if (NameR[8] != 't')	if (NameR[9] != '.')
	break;	break;

	switch (NameR[9]) {	switch (NameR[10]) {
	default: break;	default: break;

	case 'b': // 1 string to match.	case 'm': // 1 string to match.
	return Intrinsic::spu_si_cgtb; // "pu.si.cgtb"	if (NameR.substr(11, 7) != "odwrapu")
	case 'h': // 1 string to match.
	return Intrinsic::spu_si_cgth; // "pu.si.cgth"
	case 'i': // 1 string to match.
	return Intrinsic::spu_si_cgti; // "pu.si.cgti"
	}
	break;
	case 'l': // 1 string to match.
	if (NameR.substr(8, 2) != "gt")
	break;
	return Intrinsic::spu_si_clgt; // "pu.si.clgt"
	}
	break;
	case 'd': // 2 strings to match.
	if (NameR.substr(7, 2) != "fm")
	break;
	switch (NameR[9]) {
	default: break;
	case 'a': // 1 string to match.
	return Intrinsic::spu_si_dfma; // "pu.si.dfma"
	case 's': // 1 string to match.
	return Intrinsic::spu_si_dfms; // "pu.si.dfms"
	}
	break;
	case 'f': // 3 strings to match.
	switch (NameR[7]) {
	default: break;
	case 'c': // 2 strings to match.
	switch (NameR[8]) {
	default: break;
	case 'e': // 1 string to match.
	if (NameR[9] != 'q')
	break;	break;

	return Intrinsic::spu_si_fceq; // "pu.si.fceq"	return Intrinsic::hexagon_A4_modwrapu; // "exagon.A4.modwr
	case 'g': // 1 string to match.	apu"
	if (NameR[9] != 't')	case 'r': // 3 strings to match.
		switch (NameR[11]) {
		default: break;
		case 'c': // 1 string to match.
		if (NameR.substr(12, 6) != "mpneqi")
		break;
		return Intrinsic::hexagon_A4_rcmpneqi; // "exagon.A4.rcmpn
		eqi"
		case 'o': // 2 strings to match.
		if (NameR.substr(12, 5) != "und.r")
		break;
		switch (NameR[17]) {
		default: break;
		case 'i': // 1 string to match.
		return Intrinsic::hexagon_A4_round_ri; // "exagon.A4.round
		.ri"
		case 'r': // 1 string to match.
		return Intrinsic::hexagon_A4_round_rr; // "exagon.A4.round
		.rr"
		}
	break;	break;

	return Intrinsic::spu_si_fcgt; // "pu.si.fcgt"	}
	}
	break;
	case 'n': // 1 string to match.
	if (NameR.substr(8, 2) != "ms")
	break;	break;

	return Intrinsic::spu_si_fnms; // "pu.si.fnms"	}
	}
	break;
	case 'm': // 5 strings to match.
	if (NameR.substr(7, 2) != "py")
	break;	break;

	switch (NameR[9]) {
	default: break;
	case 'a': // 1 string to match.
	return Intrinsic::spu_si_mpya; // "pu.si.mpya"
	case 'h': // 1 string to match.
	return Intrinsic::spu_si_mpyh; // "pu.si.mpyh"
	case 'i': // 1 string to match.
	return Intrinsic::spu_si_mpyi; // "pu.si.mpyi"
	case 's': // 1 string to match.
	return Intrinsic::spu_si_mpys; // "pu.si.mpys"
	case 'u': // 1 string to match.
	return Intrinsic::spu_si_mpyu; // "pu.si.mpyu"
	}	}
	break;	break;

	case 'n': // 1 string to match.	case 'C': // 3 strings to match.
	if (NameR.substr(7, 3) != "and")
	break;
	return Intrinsic::spu_si_nand; // "pu.si.nand"
	case 'o': // 2 strings to match.
	if (NameR[7] != 'r')
	break;
	switch (NameR[8]) {	switch (NameR[8]) {
	default: break;	default: break;

	case 'b': // 1 string to match.	case '2': // 1 string to match.
	if (NameR[9] != 'i')	if (NameR.substr(9, 9) != ".bitsclri")
	break;
	return Intrinsic::spu_si_orbi; // "pu.si.orbi"
	case 'h': // 1 string to match.
	if (NameR[9] != 'i')
	break;
	return Intrinsic::spu_si_orhi; // "pu.si.orhi"
	}
	break;
	case 's': // 2 strings to match.
	switch (NameR[7]) {
	default: break;
	case 'f': // 1 string to match.
	if (NameR.substr(8, 2) != "hi")
	break;
	return Intrinsic::spu_si_sfhi; // "pu.si.sfhi"
	case 'h': // 1 string to match.
	if (NameR.substr(8, 2) != "li")
	break;	break;

	return Intrinsic::spu_si_shli; // "pu.si.shli"	return Intrinsic::hexagon_C2_bitsclri; // "exagon.C2.bitsc
	}	lri"
	break;	case '4': // 2 strings to match.
	case 'x': // 1 string to match.	if (NameR[9] != '.')
	if (NameR.substr(7, 3) != "ori")
	break;
	return Intrinsic::spu_si_xori; // "pu.si.xori"
	}
	break;
	case 11: // 19 strings to match.
	switch (NameR[0]) {
	default: break;
	case 'p': // 18 strings to match.
	if (NameR.substr(1, 5) != "u.si.")
	break;
	switch (NameR[6]) {
	default: break;
	case 'a': // 2 strings to match.
	if (NameR.substr(7, 2) != "nd")
	break;	break;

	switch (NameR[9]) {	switch (NameR[10]) {
	default: break;	default: break;

	case 'b': // 1 string to match.	case 'a': // 1 string to match.
	if (NameR[10] != 'i')	if (NameR.substr(11, 7) != "nd.andn")
	break;	break;

	return Intrinsic::spu_si_andbi; // "pu.si.andbi"	return Intrinsic::hexagon_C4_and_andn; // "exagon.C4.and.a
	case 'h': // 1 string to match.	ndn"
	if (NameR[10] != 'i')	case 'c': // 1 string to match.
		if (NameR.substr(11, 7) != "mplteui")
	break;	break;

	return Intrinsic::spu_si_andhi; // "pu.si.andhi"	return Intrinsic::hexagon_C4_cmplteui; // "exagon.C4.cmplt eui"
	}	}
	break;	break;

	case 'c': // 7 strings to match.	}
	switch (NameR[7]) {	break;
		case 'M': // 20 strings to match.
		switch (NameR[8]) {
		default: break;
		case '2': // 17 strings to match.
		if (NameR[9] != '.')
		break;
		switch (NameR[10]) {
	default: break;	default: break;

	case 'e': // 2 strings to match.	case 'c': // 10 strings to match.
	if (NameR[8] != 'q')	switch (NameR[11]) {
	break;
	switch (NameR[9]) {
	default: break;	default: break;

	case 'b': // 1 string to match.	case 'm': // 8 strings to match.
	if (NameR[10] != 'i')	switch (NameR[12]) {
		default: break;
		case 'a': // 4 strings to match.
		if (NameR[13] != 'c')
		break;
		switch (NameR[14]) {
		default: break;
		case 'i': // 1 string to match.
		if (NameR.substr(15, 3) != ".s0")
		break;
		return Intrinsic::hexagon_M2_cmaci_s0; // "exagon.
		M2.cmaci.s0"
		case 'r': // 1 string to match.
		if (NameR.substr(15, 3) != ".s0")
		break;
		return Intrinsic::hexagon_M2_cmacr_s0; // "exagon.
		M2.cmacr.s0"
		case 's': // 2 strings to match.
		if (NameR.substr(15, 2) != ".s")
		break;
		switch (NameR[17]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_cmacs_s0; // "exagon.
		M2.cmacs.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_cmacs_s1; // "exagon.
		M2.cmacs.s1"
		}
		break;
		}
	break;	break;

	return Intrinsic::spu_si_ceqbi; // "pu.si.ceqbi"	case 'p': // 4 strings to match.
	case 'h': // 1 string to match.	if (NameR[13] != 'y')
	if (NameR[10] != 'i')	break;
		switch (NameR[14]) {
		default: break;
		case 'i': // 1 string to match.
		if (NameR.substr(15, 3) != ".s0")
		break;
		return Intrinsic::hexagon_M2_cmpyi_s0; // "exagon.
		M2.cmpyi.s0"
		case 'r': // 1 string to match.
		if (NameR.substr(15, 3) != ".s0")
		break;
		return Intrinsic::hexagon_M2_cmpyr_s0; // "exagon.
		M2.cmpyr.s0"
		case 's': // 2 strings to match.
		if (NameR.substr(15, 2) != ".s")
		break;
		switch (NameR[17]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_cmpys_s0; // "exagon.
		M2.cmpys.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_cmpys_s1; // "exagon.
		M2.cmpys.s1"
		}
		break;
		}
	break;	break;

	return Intrinsic::spu_si_ceqhi; // "pu.si.ceqhi"	}
		break;
		case 'n': // 2 strings to match.
		if (NameR.substr(12, 5) != "acs.s")
		break;
		switch (NameR[17]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_cnacs_s0; // "exagon.M2.cnacs
		.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_cnacs_s1; // "exagon.M2.cnacs
		.s1"
		}
		break;
	}	}
	break;	break;

	case 'g': // 2 strings to match.	case 'm': // 4 strings to match.
	if (NameR[8] != 't')	if (NameR.substr(11, 3) != "mpy")
	break;	break;

	switch (NameR[9]) {	switch (NameR[14]) {
	default: break;	default: break;

	case 'b': // 1 string to match.	case 'h': // 2 strings to match.
	if (NameR[10] != 'i')	if (NameR.substr(15, 2) != ".s")
	break;	break;

	return Intrinsic::spu_si_cgtbi; // "pu.si.cgtbi"	switch (NameR[17]) {
	case 'h': // 1 string to match.	default: break;
	if (NameR[10] != 'i')	case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mmpyh_s0; // "exagon.M2.mmpyh
		.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mmpyh_s1; // "exagon.M2.mmpyh
		.s1"
		}
		break;
		case 'l': // 2 strings to match.
		if (NameR.substr(15, 2) != ".s")
	break;	break;

	return Intrinsic::spu_si_cgthi; // "pu.si.cgthi"	switch (NameR[17]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mmpyl_s0; // "exagon.M2.mmpyl
		.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mmpyl_s1; // "exagon.M2.mmpyl
		.s1"
		}
		break;
	}	}
	break;	break;

	case 'l': // 3 strings to match.	case 'v': // 2 strings to match.
	if (NameR.substr(8, 2) != "gt")	if (NameR.substr(11, 2) != "rm")
	break;	break;

	switch (NameR[10]) {	switch (NameR[13]) {
	default: break;	default: break;

	case 'b': // 1 string to match.	case 'a': // 1 string to match.
	return Intrinsic::spu_si_clgtb; // "pu.si.clgtb"	if (NameR.substr(14, 4) != "c.s0")
	case 'h': // 1 string to match.	break;
	return Intrinsic::spu_si_clgth; // "pu.si.clgth"	return Intrinsic::hexagon_M2_vrmac_s0; // "exagon.M2.vrmac
	case 'i': // 1 string to match.	.s0"
	return Intrinsic::spu_si_clgti; // "pu.si.clgti"	case 'p': // 1 string to match.
		if (NameR.substr(14, 4) != "y.s0")
		break;
		return Intrinsic::hexagon_M2_vrmpy_s0; // "exagon.M2.vrmpy
		.s0"
	}	}
	break;	break;

		case 'x': // 1 string to match.
		if (NameR.substr(11, 7) != "or.xacc")
		break;
		return Intrinsic::hexagon_M2_xor_xacc; // "exagon.M2.xor.x
		acc"
	}	}
	break;	break;

	case 'd': // 2 strings to match.	case '4': // 3 strings to match.
	if (NameR.substr(7, 3) != "fnm")	if (NameR[9] != '.')
	break;	break;
	switch (NameR[10]) {	switch (NameR[10]) {
	default: break;	default: break;
	case 'a': // 1 string to match.	case 'a': // 1 string to match.

	return Intrinsic::spu_si_dfnma; // "pu.si.dfnma"	if (NameR.substr(11, 7) != "nd.andn")
	case 's': // 1 string to match.
	return Intrinsic::spu_si_dfnms; // "pu.si.dfnms"
	}
	break;
	case 'f': // 3 strings to match.
	switch (NameR[7]) {
	default: break;
	case 'c': // 2 strings to match.
	if (NameR[8] != 'm')
	break;	break;

	switch (NameR[9]) {	return Intrinsic::hexagon_M4_and_andn; // "exagon.M4.and.a
		ndn"
		case 'x': // 2 strings to match.
		if (NameR.substr(11, 3) != "or.")
		break;
		switch (NameR[14]) {
	default: break;	default: break;

	case 'e': // 1 string to match.	case 'a': // 1 string to match.
	if (NameR[10] != 'q')	if (NameR.substr(15, 3) != "ndn")
	break;	break;

	return Intrinsic::spu_si_fcmeq; // "pu.si.fcmeq"	return Intrinsic::hexagon_M4_xor_andn; // "exagon.M4.xor.a
	case 'g': // 1 string to match.	ndn"
	if (NameR[10] != 't')	case 'x': // 1 string to match.
		if (NameR.substr(15, 3) != "acc")
	break;	break;

	return Intrinsic::spu_si_fcmgt; // "pu.si.fcmgt"	return Intrinsic::hexagon_M4_xor_xacc; // "exagon.M4.xor.x acc"
	}	}
	break;	break;

	case 's': // 1 string to match.
	if (NameR.substr(8, 3) != "mbi")
	break;
	return Intrinsic::spu_si_fsmbi; // "pu.si.fsmbi"
	}	}
	break;	break;

	case 'm': // 2 strings to match.	}
	if (NameR.substr(7, 2) != "py")	break;
		case 'S': // 32 strings to match.
		switch (NameR[8]) {
		default: break;
		case '2': // 31 strings to match.
		if (NameR[9] != '.')
	break;	break;

	switch (NameR[9]) {	switch (NameR[10]) {
	default: break;	default: break;

	case 'h': // 1 string to match.	case 'a': // 8 strings to match.
	if (NameR[10] != 'h')	if (NameR[11] != 's')
	break;	break;

	return Intrinsic::spu_si_mpyhh; // "pu.si.mpyhh"	switch (NameR[12]) {
	case 'u': // 1 string to match.	default: break;
	if (NameR[10] != 'i')	case 'l': // 4 strings to match.
		if (NameR[13] != '.')
		break;
		switch (NameR[14]) {
		default: break;
		case 'i': // 2 strings to match.
		if (NameR.substr(15, 2) != ".v")
		break;
		switch (NameR[17]) {
		default: break;
		case 'h': // 1 string to match.
		return Intrinsic::hexagon_S2_asl_i_vh; // "exagon.
		S2.asl.i.vh"
		case 'w': // 1 string to match.
		return Intrinsic::hexagon_S2_asl_i_vw; // "exagon.
		S2.asl.i.vw"
		}
		break;
		case 'r': // 2 strings to match.
		if (NameR.substr(15, 2) != ".v")
		break;
		switch (NameR[17]) {
		default: break;
		case 'h': // 1 string to match.
		return Intrinsic::hexagon_S2_asl_r_vh; // "exagon.
		S2.asl.r.vh"
		case 'w': // 1 string to match.
		return Intrinsic::hexagon_S2_asl_r_vw; // "exagon.
		S2.asl.r.vw"
		}
		break;
		}
	break;	break;

	return Intrinsic::spu_si_mpyui; // "pu.si.mpyui"	case 'r': // 4 strings to match.
	}	if (NameR[13] != '.')
	break;	break;
	case 'x': // 2 strings to match.	switch (NameR[14]) {
	if (NameR.substr(7, 2) != "or")	default: break;
		case 'i': // 2 strings to match.
		if (NameR.substr(15, 2) != ".v")
		break;
		switch (NameR[17]) {
		default: break;
		case 'h': // 1 string to match.
		return Intrinsic::hexagon_S2_asr_i_vh; // "exagon.
		S2.asr.i.vh"
		case 'w': // 1 string to match.
		return Intrinsic::hexagon_S2_asr_i_vw; // "exagon.
		S2.asr.i.vw"
		}
		break;
		case 'r': // 2 strings to match.
		if (NameR.substr(15, 2) != ".v")
		break;
		switch (NameR[17]) {
		default: break;
		case 'h': // 1 string to match.
		return Intrinsic::hexagon_S2_asr_r_vh; // "exagon.
		S2.asr.r.vh"
		case 'w': // 1 string to match.
		return Intrinsic::hexagon_S2_asr_r_vw; // "exagon.
		S2.asr.r.vw"
		}
		break;
		}
		break;
		}
	break;	break;

	switch (NameR[9]) {	case 'c': // 2 strings to match.
	default: break;	if (NameR.substr(11, 6) != "lrbit.")
	case 'b': // 1 string to match.
	if (NameR[10] != 'i')
	break;	break;

	return Intrinsic::spu_si_xorbi; // "pu.si.xorbi"	switch (NameR[17]) {
	case 'h': // 1 string to match.	default: break;
	if (NameR[10] != 'i')	case 'i': // 1 string to match.
		return Intrinsic::hexagon_S2_clrbit_i; // "exagon.S2.clrbi
		t.i"
		case 'r': // 1 string to match.
		return Intrinsic::hexagon_S2_clrbit_r; // "exagon.S2.clrbi
		t.r"
		}
		break;
		case 'e': // 1 string to match.
		if (NameR.substr(11, 7) != "xtractu")
	break;	break;

	return Intrinsic::spu_si_xorhi; // "pu.si.xorhi"	return Intrinsic::hexagon_S2_extractu; // "exagon.S2.extra
	}	ctu"
	break;	case 'l': // 6 strings to match.
	}	if (NameR[11] != 's')
	break;	break;
	case 't': // 1 string to match.	switch (NameR[12]) {
	if (NameR.substr(1, 10) != "ackrestore")	default: break;
	break;	case 'l': // 2 strings to match.
	return Intrinsic::stackrestore; // "tackrestore"	if (NameR.substr(13, 4) != ".r.v")
	}	break;
	break;	switch (NameR[17]) {
	case 12: // 6 strings to match.	default: break;
	if (NameR.substr(0, 6) != "pu.si.")	case 'h': // 1 string to match.
	break;	return Intrinsic::hexagon_S2_lsl_r_vh; // "exagon.S2.lsl.r
	switch (NameR[6]) {	.vh"
	default: break;	case 'w': // 1 string to match.
	case 'c': // 2 strings to match.	return Intrinsic::hexagon_S2_lsl_r_vw; // "exagon.S2.lsl.r
	if (NameR.substr(7, 3) != "lgt")	.vw"
	break;	}
	switch (NameR[10]) {	break;
	default: break;	case 'r': // 4 strings to match.
	case 'b': // 1 string to match.	if (NameR[13] != '.')
	if (NameR[11] != 'i')	break;
		switch (NameR[14]) {
		default: break;
		case 'i': // 2 strings to match.
		if (NameR.substr(15, 2) != ".v")
		break;
		switch (NameR[17]) {
		default: break;
		case 'h': // 1 string to match.
		return Intrinsic::hexagon_S2_lsr_i_vh; // "exagon.
		S2.lsr.i.vh"
		case 'w': // 1 string to match.
		return Intrinsic::hexagon_S2_lsr_i_vw; // "exagon.
		S2.lsr.i.vw"
		}
		break;
		case 'r': // 2 strings to match.
		if (NameR.substr(15, 2) != ".v")
		break;
		switch (NameR[17]) {
		default: break;
		case 'h': // 1 string to match.
		return Intrinsic::hexagon_S2_lsr_r_vh; // "exagon.
		S2.lsr.r.vh"
		case 'w': // 1 string to match.
		return Intrinsic::hexagon_S2_lsr_r_vw; // "exagon.
		S2.lsr.r.vw"
		}
		break;
		}
		break;
		}
	break;	break;

	return Intrinsic::spu_si_clgtbi; // "pu.si.clgtbi"	case 's': // 3 strings to match.
	case 'h': // 1 string to match.	switch (NameR[11]) {
	if (NameR[11] != 'i')	default: break;
		case 'e': // 2 strings to match.
		if (NameR.substr(12, 5) != "tbit.")
		break;
		switch (NameR[17]) {
		default: break;
		case 'i': // 1 string to match.
		return Intrinsic::hexagon_S2_setbit_i; // "exagon.S2.setbi
		t.i"
		case 'r': // 1 string to match.
		return Intrinsic::hexagon_S2_setbit_r; // "exagon.S2.setbi
		t.r"
		}
		break;
		case 'v': // 1 string to match.
		if (NameR.substr(12, 6) != "sathub")
		break;
		return Intrinsic::hexagon_S2_svsathub; // "exagon.S2.svsat
		hub"
		}
	break;	break;

	return Intrinsic::spu_si_clgthi; // "pu.si.clgthi"	case 't': // 2 strings to match.
	}	if (NameR.substr(11, 6) != "stbit.")
	break;	break;
	case 'm': // 2 strings to match.	switch (NameR[17]) {
	if (NameR.substr(7, 4) != "pyhh")	default: break;
	break;	case 'i': // 1 string to match.
	switch (NameR[11]) {	return Intrinsic::hexagon_S2_tstbit_i; // "exagon.S2.tstbi
	default: break;	t.i"
	case 'a': // 1 string to match.	case 'r': // 1 string to match.
	return Intrinsic::spu_si_mpyhha; // "pu.si.mpyhha"	return Intrinsic::hexagon_S2_tstbit_r; // "exagon.S2.tstbi
	case 'u': // 1 string to match.	t.r"
	return Intrinsic::spu_si_mpyhhu; // "pu.si.mpyhhu"	}
	}	break;
	break;	case 'v': // 9 strings to match.
	case 's': // 2 strings to match.	switch (NameR[11]) {
	if (NameR.substr(7, 4) != "hlqb")	default: break;
		case 'a': // 2 strings to match.
		if (NameR.substr(12, 4) != "lign")
		break;
		switch (NameR[16]) {
		default: break;
		case 'i': // 1 string to match.
		if (NameR[17] != 'b')
		break;
		return Intrinsic::hexagon_S2_valignib; // "exagon.S2.valig
		nib"
		case 'r': // 1 string to match.
		if (NameR[17] != 'b')
		break;
		return Intrinsic::hexagon_S2_valignrb; // "exagon.S2.valig
		nrb"
		}
		break;
		case 'c': // 1 string to match.
		if (NameR.substr(12, 6) != "rotate")
		break;
		return Intrinsic::hexagon_S2_vcrotate; // "exagon.S2.vcrot
		ate"
		case 's': // 2 strings to match.
		if (NameR.substr(12, 5) != "platr")
		break;
		switch (NameR[17]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::hexagon_S2_vsplatrb; // "exagon.S2.vspla
		trb"
		case 'h': // 1 string to match.
		return Intrinsic::hexagon_S2_vsplatrh; // "exagon.S2.vspla
		trh"
		}
		break;
		case 't': // 4 strings to match.
		if (NameR.substr(12, 3) != "run")
		break;
		switch (NameR[15]) {
		default: break;
		case 'e': // 2 strings to match.
		switch (NameR[16]) {
		default: break;
		case 'h': // 1 string to match.
		if (NameR[17] != 'b')
		break;
		return Intrinsic::hexagon_S2_vtrunehb; // "exagon.
		S2.vtrunehb"
		case 'w': // 1 string to match.
		if (NameR[17] != 'h')
		break;
		return Intrinsic::hexagon_S2_vtrunewh; // "exagon.
		S2.vtrunewh"
		}
		break;
		case 'o': // 2 strings to match.
		switch (NameR[16]) {
		default: break;
		case 'h': // 1 string to match.
		if (NameR[17] != 'b')
		break;
		return Intrinsic::hexagon_S2_vtrunohb; // "exagon.
		S2.vtrunohb"
		case 'w': // 1 string to match.
		if (NameR[17] != 'h')
		break;
		return Intrinsic::hexagon_S2_vtrunowh; // "exagon.
		S2.vtrunowh"
		}
		break;
		}
		break;
		}
		break;
		}
	break;	break;

	switch (NameR[11]) {	case '4': // 1 string to match.
	default: break;	if (NameR.substr(9, 9) != ".or.andix")
	case 'i': // 1 string to match.	break;
	return Intrinsic::spu_si_shlqbi; // "pu.si.shlqbi"	return Intrinsic::hexagon_S4_or_andix; // "exagon.S4.or.an
	case 'y': // 1 string to match.	dix"
	return Intrinsic::spu_si_shlqby; // "pu.si.shlqby"
	}	}
	break;	break;
	}	}
	break;	break;

	case 13: // 4 strings to match.	case 19: // 48 strings to match.
	switch (NameR[0]) {	if (NameR.substr(0, 7) != "exagon.")
		break;
		switch (NameR[7]) {
	default: break;	default: break;

	case 'p': // 3 strings to match.	case 'A': // 5 strings to match.
	if (NameR.substr(1, 5) != "u.si.")	switch (NameR[8]) {
	break;
	switch (NameR[6]) {
	default: break;	default: break;

	case 'm': // 1 string to match.	case '2': // 1 string to match.
	if (NameR.substr(7, 6) != "pyhhau")	if (NameR.substr(9, 10) != ".combineii")
	break;	break;

	return Intrinsic::spu_si_mpyhhau; // "pu.si.mpyhhau"	return Intrinsic::hexagon_A2_combineii; // "exagon.A2.combi
	case 's': // 2 strings to match.	neii"
	if (NameR.substr(7, 4) != "hlqb")	case '4': // 4 strings to match.
		if (NameR.substr(9, 2) != ".c")
	break;	break;
	switch (NameR[11]) {	switch (NameR[11]) {
	default: break;	default: break;

	case 'i': // 1 string to match.	case 'o': // 2 strings to match.
	if (NameR[12] != 'i')	if (NameR.substr(12, 5) != "mbine")
	break;	break;

	return Intrinsic::spu_si_shlqbii; // "pu.si.shlqbii"	switch (NameR[17]) {
	case 'y': // 1 string to match.	default: break;
	if (NameR[12] != 'i')	case 'i': // 1 string to match.
		if (NameR[18] != 'r')
		break;
		return Intrinsic::hexagon_A4_combineir; // "exagon.A4.combi
		neir"
		case 'r': // 1 string to match.
		if (NameR[18] != 'i')
		break;
		return Intrinsic::hexagon_A4_combineri; // "exagon.A4.combi
		neri"
		}
		break;
		case 'r': // 2 strings to match.
		if (NameR.substr(12, 6) != "ound.r")
	break;	break;

	return Intrinsic::spu_si_shlqbyi; // "pu.si.shlqbyi"	switch (NameR[18]) {
		default: break;
		case 'i': // 1 string to match.
		return Intrinsic::hexagon_A4_cround_ri; // "exagon.A4.croun
		d.ri"
		case 'r': // 1 string to match.
		return Intrinsic::hexagon_A4_cround_rr; // "exagon.A4.croun
		d.rr"
		}
		break;
	}	}
	break;	break;
	}	}
	break;	break;

	case 't': // 1 string to match.	case 'C': // 1 string to match.
	if (NameR.substr(1, 12) != "ackprotector")	if (NameR.substr(8, 11) != "2.pxfer.map")
	break;	break;

	return Intrinsic::stackprotector; // "tackprotector"	return Intrinsic::hexagon_C2_pxfer_map; // "exagon.C2.pxfer
	}	.map"
	break;	case 'M': // 38 strings to match.
	}	if (NameR.substr(8, 2) != "2.")
	break; // end of 's' case.
	case 't':
	switch (NameR.size()) {
	default: break;
	case 3: // 1 string to match.
	if (NameR.substr(0, 3) != "rap")
	break;
	return Intrinsic::trap; // "rap"
	}
	break; // end of 't' case.
	case 'u':
	if (NameR.startswith("add.with.overflow.")) return Intrinsic::uadd_with
	_overflow;
	if (NameR.startswith("mul.with.overflow.")) return Intrinsic::umul_with
	_overflow;
	if (NameR.startswith("sub.with.overflow.")) return Intrinsic::usub_with
	_overflow;
	break; // end of 'u' case.
	case 'v':
	switch (NameR.size()) {
	default: break;
	case 5: // 1 string to match.
	if (NameR.substr(0, 5) != "a_end")
	break;
	return Intrinsic::vaend; // "a_end"
	case 6: // 1 string to match.
	if (NameR.substr(0, 6) != "a_copy")
	break;
	return Intrinsic::vacopy; // "a_copy"
	case 7: // 1 string to match.
	if (NameR.substr(0, 7) != "a_start")
	break;
	return Intrinsic::vastart; // "a_start"
	case 13: // 1 string to match.
	if (NameR.substr(0, 13) != "ar.annotation")
	break;
	return Intrinsic::var_annotation; // "ar.annotation"
	}
	break; // end of 'v' case.
	case 'x':
	if (NameR.startswith("core.chkct.")) return Intrinsic::xcore_chkct;
	if (NameR.startswith("core.eeu.")) return Intrinsic::xcore_eeu;
	if (NameR.startswith("core.endin.")) return Intrinsic::xcore_endin;
	if (NameR.startswith("core.freer.")) return Intrinsic::xcore_freer;
	if (NameR.startswith("core.getr.")) return Intrinsic::xcore_getr;
	if (NameR.startswith("core.getst.")) return Intrinsic::xcore_getst;
	if (NameR.startswith("core.getts.")) return Intrinsic::xcore_getts;
	if (NameR.startswith("core.in.")) return Intrinsic::xcore_in;
	if (NameR.startswith("core.inct.")) return Intrinsic::xcore_inct;
	if (NameR.startswith("core.initcp.")) return Intrinsic::xcore_initcp;
	if (NameR.startswith("core.initdp.")) return Intrinsic::xcore_initdp;
	if (NameR.startswith("core.initlr.")) return Intrinsic::xcore_initlr;
	if (NameR.startswith("core.initpc.")) return Intrinsic::xcore_initpc;
	if (NameR.startswith("core.initsp.")) return Intrinsic::xcore_initsp;
	if (NameR.startswith("core.inshr.")) return Intrinsic::xcore_inshr;
	if (NameR.startswith("core.int.")) return Intrinsic::xcore_int;
	if (NameR.startswith("core.mjoin.")) return Intrinsic::xcore_mjoin;
	if (NameR.startswith("core.msync.")) return Intrinsic::xcore_msync;
	if (NameR.startswith("core.out.")) return Intrinsic::xcore_out;
	if (NameR.startswith("core.outct.")) return Intrinsic::xcore_outct;
	if (NameR.startswith("core.outshr.")) return Intrinsic::xcore_outshr;
	if (NameR.startswith("core.outt.")) return Intrinsic::xcore_outt;
	if (NameR.startswith("core.peek.")) return Intrinsic::xcore_peek;
	if (NameR.startswith("core.setc.")) return Intrinsic::xcore_setc;
	if (NameR.startswith("core.setclk.")) return Intrinsic::xcore_setclk;
	if (NameR.startswith("core.setd.")) return Intrinsic::xcore_setd;
	if (NameR.startswith("core.setev.")) return Intrinsic::xcore_setev;
	if (NameR.startswith("core.setpsc.")) return Intrinsic::xcore_setpsc;
	if (NameR.startswith("core.setpt.")) return Intrinsic::xcore_setpt;
	if (NameR.startswith("core.setrdy.")) return Intrinsic::xcore_setrdy;
	if (NameR.startswith("core.settw.")) return Intrinsic::xcore_settw;
	if (NameR.startswith("core.setv.")) return Intrinsic::xcore_setv;
	if (NameR.startswith("core.syncr.")) return Intrinsic::xcore_syncr;
	if (NameR.startswith("core.testct.")) return Intrinsic::xcore_testct;
	if (NameR.startswith("core.testwct.")) return Intrinsic::xcore_testwct;
	switch (NameR.size()) {
	default: break;
	case 6: // 1 string to match.
	if (NameR.substr(0, 6) != "86.int")
	break;
	return Intrinsic::x86_int; // "86.int"
	case 9: // 4 strings to match.
	if (NameR.substr(0, 5) != "core.")
	break;
	switch (NameR[5]) {
	default: break;
	case 'c': // 2 strings to match.
	switch (NameR[6]) {
	default: break;
	case 'l': // 1 string to match.
	if (NameR.substr(7, 2) != "re")
	break;
	return Intrinsic::xcore_clre; // "core.clre"
	case 'r': // 1 string to match.
	if (NameR.substr(7, 2) != "c8")
	break;
	return Intrinsic::xcore_crc8; // "core.crc8"
	}
	break;
	case 's': // 1 string to match.
	if (NameR.substr(6, 3) != "ext")
	break;
	return Intrinsic::xcore_sext; // "core.sext"
	case 'z': // 1 string to match.
	if (NameR.substr(6, 3) != "ext")
	break;
	return Intrinsic::xcore_zext; // "core.zext"
	}
	break;
	case 10: // 10 strings to match.
	switch (NameR[0]) {
	default: break;
	case '8': // 1 string to match.
	if (NameR.substr(1, 9) != "6.mmx.por")
	break;
	return Intrinsic::x86_mmx_por; // "86.mmx.por"
	case 'c': // 9 strings to match.
	if (NameR.substr(1, 4) != "ore.")
	break;	break;

	switch (NameR[5]) {	switch (NameR[10]) {
	default: break;	default: break;

	case 'c': // 2 strings to match.	case 'c': // 8 strings to match.
	switch (NameR[6]) {	switch (NameR[11]) {
	default: break;	default: break;

	case 'l': // 1 string to match.	case 'm': // 6 strings to match.
	if (NameR.substr(7, 3) != "rsr")	switch (NameR[12]) {
		default: break;
		case 'a': // 2 strings to match.
		if (NameR.substr(13, 5) != "csc.s")
		break;
		switch (NameR[18]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_cmacsc_s0; // "exagon.
		M2.cmacsc.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_cmacsc_s1; // "exagon.
		M2.cmacsc.s1"
		}
	break;	break;

	return Intrinsic::xcore_clrsr; // "core.clrsr"	case 'p': // 4 strings to match.
	case 'r': // 1 string to match.	if (NameR[13] != 'y')
	if (NameR.substr(7, 3) != "c32")	break;
		switch (NameR[14]) {
		default: break;
		case 'r': // 2 strings to match.
		if (NameR.substr(15, 3) != "s.s")
		break;
		switch (NameR[18]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_cmpyrs_s0; // "exagon.
		M2.cmpyrs.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_cmpyrs_s1; // "exagon.
		M2.cmpyrs.s1"
		}
		break;
		case 's': // 2 strings to match.
		if (NameR.substr(15, 3) != "c.s")
		break;
		switch (NameR[18]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_cmpysc_s0; // "exagon.
		M2.cmpysc.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_cmpysc_s1; // "exagon.
		M2.cmpysc.s1"
		}
		break;
		}
	break;	break;

	return Intrinsic::xcore_crc32; // "core.crc32"	}
	}
	break;
	case 'g': // 4 strings to match.
	if (NameR.substr(6, 2) != "et")
	break;	break;

	switch (NameR[8]) {	case 'n': // 2 strings to match.
	default: break;	if (NameR.substr(12, 6) != "acsc.s")
	case 'e': // 2 strings to match.	break;
	switch (NameR[9]) {	switch (NameR[18]) {
	default: break;	default: break;

	case 'd': // 1 string to match.	case '0': // 1 string to match.
	return Intrinsic::xcore_geted; // "core.geted"	return Intrinsic::hexagon_M2_cnacsc_s0; // "exagon.M2.cnacs
	case 't': // 1 string to match.	c.s0"
	return Intrinsic::xcore_getet; // "core.getet"	case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_cnacsc_s1; // "exagon.M2.cnacs
		c.s1"
	}	}
	break;	break;

	case 'i': // 1 string to match.
	if (NameR[9] != 'd')
	break;
	return Intrinsic::xcore_getid; // "core.getid"
	case 'p': // 1 string to match.
	if (NameR[9] != 's')
	break;
	return Intrinsic::xcore_getps; // "core.getps"
	}	}
	break;	break;

	case 's': // 3 strings to match.	case 'm': // 20 strings to match.
	switch (NameR[6]) {	switch (NameR[11]) {
	default: break;	default: break;

	case 'e': // 2 strings to match.	case 'm': // 12 strings to match.
	if (NameR[7] != 't')	switch (NameR[12]) {
	break;
	switch (NameR[8]) {
	default: break;	default: break;

	case 'p': // 1 string to match.	case 'a': // 4 strings to match.
	if (NameR[9] != 's')	if (NameR[13] != 'c')
	break;	break;

	return Intrinsic::xcore_setps; // "core.setps"	switch (NameR[14]) {
	case 's': // 1 string to match.	default: break;
	if (NameR[9] != 'r')	case 'h': // 2 strings to match.
		if (NameR.substr(15, 3) != "s.s")
		break;
		switch (NameR[18]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mmachs_s0; // "exagon.
		M2.mmachs.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mmachs_s1; // "exagon.
		M2.mmachs.s1"
		}
	break;	break;

	return Intrinsic::xcore_setsr; // "core.setsr"	case 'l': // 2 strings to match.
		if (NameR.substr(15, 3) != "s.s")
		break;
		switch (NameR[18]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mmacls_s0; // "exagon.
		M2.mmacls.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mmacls_s1; // "exagon.
		M2.mmacls.s1"
		}
		break;
		}
		break;
		case 'p': // 8 strings to match.
		if (NameR[13] != 'y')
		break;
		switch (NameR[14]) {
		default: break;
		case 'h': // 2 strings to match.
		if (NameR.substr(15, 3) != ".rs")
		break;
		switch (NameR[18]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mmpyh_rs0; // "exagon.
		M2.mmpyh.rs0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mmpyh_rs1; // "exagon.
		M2.mmpyh.rs1"
		}
		break;
		case 'l': // 2 strings to match.
		if (NameR.substr(15, 3) != ".rs")
		break;
		switch (NameR[18]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mmpyl_rs0; // "exagon.
		M2.mmpyl.rs0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mmpyl_rs1; // "exagon.
		M2.mmpyl.rs1"
		}
		break;
		case 'u': // 4 strings to match.
		switch (NameR[15]) {
		default: break;
		case 'h': // 2 strings to match.
		if (NameR.substr(16, 2) != ".s")
		break;
		switch (NameR[18]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mmpyuh_s0; // "exagon.
		M2.mmpyuh.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mmpyuh_s1; // "exagon.
		M2.mmpyuh.s1"
		}
		break;
		case 'l': // 2 strings to match.
		if (NameR.substr(16, 2) != ".s")
		break;
		switch (NameR[18]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mmpyul_s0; // "exagon.
		M2.mmpyul.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mmpyul_s1; // "exagon.
		M2.mmpyul.s1"
		}
		break;
		}
		break;
		}
		break;
	}	}
	break;	break;

	case 's': // 1 string to match.	case 'p': // 8 strings to match.
	if (NameR.substr(7, 3) != "ync")	if (NameR.substr(12, 2) != "y.")
	break;	break;

	return Intrinsic::xcore_ssync; // "core.ssync"	switch (NameR[14]) {
	}
	break;
	}
	break;
	}
	break;
	case 11: // 4 strings to match.
	switch (NameR[0]) {
	default: break;
	case '8': // 3 strings to match.
	if (NameR.substr(1, 6) != "6.mmx.")
	break;
	switch (NameR[7]) {
	default: break;
	case 'e': // 1 string to match.
	if (NameR.substr(8, 3) != "mms")
	break;
	return Intrinsic::x86_mmx_emms; // "86.mmx.emms"
	case 'p': // 2 strings to match.
	switch (NameR[8]) {
	default: break;
	case 'a': // 1 string to match.
	if (NameR.substr(9, 2) != "nd")
	break;
	return Intrinsic::x86_mmx_pand; // "86.mmx.pand"
	case 'x': // 1 string to match.
	if (NameR.substr(9, 2) != "or")
	break;
	return Intrinsic::x86_mmx_pxor; // "86.mmx.pxor"
	}
	break;
	}
	break;
	case 'c': // 1 string to match.
	if (NameR.substr(1, 10) != "ore.bitrev")
	break;
	return Intrinsic::xcore_bitrev; // "core.bitrev"
	}
	break;
	case 12: // 2 strings to match.
	if (NameR.substr(0, 7) != "86.mmx.")
	break;
	switch (NameR[7]) {
	default: break;
	case 'f': // 1 string to match.
	if (NameR.substr(8, 4) != "emms")
	break;
	return Intrinsic::x86_mmx_femms; // "86.mmx.femms"
	case 'p': // 1 string to match.
	if (NameR.substr(8, 4) != "andn")
	break;
	return Intrinsic::x86_mmx_pandn; // "86.mmx.pandn"
	}
	break;
	case 13: // 34 strings to match.
	if (NameR.substr(0, 3) != "86.")
	break;
	switch (NameR[3]) {
	default: break;
	case 'm': // 18 strings to match.
	if (NameR.substr(4, 4) != "mx.p")
	break;
	switch (NameR[8]) {
	default: break;
	case 'a': // 6 strings to match.
	switch (NameR[9]) {
	default: break;
	case 'd': // 4 strings to match.
	if (NameR.substr(10, 2) != "d.")
	break;
	switch (NameR[12]) {
	default: break;	default: break;

	case 'b': // 1 string to match.	case 'h': // 4 strings to match.
	return Intrinsic::x86_mmx_padd_b; // "86.mmx.padd.b"	switch (NameR[15]) {
	case 'd': // 1 string to match.	default: break;
	return Intrinsic::x86_mmx_padd_d; // "86.mmx.padd.d"	case 'h': // 2 strings to match.
	case 'q': // 1 string to match.	if (NameR.substr(16, 2) != ".s")
	return Intrinsic::x86_mmx_padd_q; // "86.mmx.padd.q"	break;
	case 'w': // 1 string to match.	switch (NameR[18]) {
	return Intrinsic::x86_mmx_padd_w; // "86.mmx.padd.w"	default: break;
	}	case '0': // 1 string to match.
	break;	return Intrinsic::hexagon_M2_mpy_hh_s0; // "exagon.
	case 'v': // 2 strings to match.	M2.mpy.hh.s0"
	if (NameR.substr(10, 2) != "g.")	case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_hh_s1; // "exagon.
		M2.mpy.hh.s1"
		}
		break;
		case 'l': // 2 strings to match.
		if (NameR.substr(16, 2) != ".s")
		break;
		switch (NameR[18]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_hl_s0; // "exagon.
		M2.mpy.hl.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_hl_s1; // "exagon.
		M2.mpy.hl.s1"
		}
		break;
		}
		break;
		case 'l': // 4 strings to match.
		switch (NameR[15]) {
		default: break;
		case 'h': // 2 strings to match.
		if (NameR.substr(16, 2) != ".s")
		break;
		switch (NameR[18]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_lh_s0; // "exagon.
		M2.mpy.lh.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_lh_s1; // "exagon.
		M2.mpy.lh.s1"
		}
		break;
		case 'l': // 2 strings to match.
		if (NameR.substr(16, 2) != ".s")
		break;
		switch (NameR[18]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_ll_s0; // "exagon.
		M2.mpy.ll.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_ll_s1; // "exagon.
		M2.mpy.ll.s1"
		}
		break;
		}
	break;	break;

	switch (NameR[12]) {
	default: break;
	case 'b': // 1 string to match.
	return Intrinsic::x86_mmx_pavg_b; // "86.mmx.pavg.b"
	case 'w': // 1 string to match.
	return Intrinsic::x86_mmx_pavg_w; // "86.mmx.pavg.w"
	}	}
	break;	break;
	}	}
	break;	break;

	case 's': // 12 strings to match.	case 'v': // 10 strings to match.
	switch (NameR[9]) {	switch (NameR[11]) {
	default: break;	default: break;

	case 'l': // 3 strings to match.	case 'a': // 2 strings to match.
	if (NameR.substr(10, 2) != "l.")	if (NameR.substr(12, 6) != "bsdiff")
	break;	break;

	switch (NameR[12]) {	switch (NameR[18]) {
	default: break;	default: break;

	case 'd': // 1 string to match.	case 'h': // 1 string to match.
	return Intrinsic::x86_mmx_psll_d; // "86.mmx.psll.d"	return Intrinsic::hexagon_M2_vabsdiffh; // "exagon.M2.vabsd
	case 'q': // 1 string to match.	iffh"
	return Intrinsic::x86_mmx_psll_q; // "86.mmx.psll.q"
	case 'w': // 1 string to match.	case 'w': // 1 string to match.

	return Intrinsic::x86_mmx_psll_w; // "86.mmx.psll.w"	return Intrinsic::hexagon_M2_vabsdiffw; // "exagon.M2.vabsd iffw"
	}	}
	break;	break;

	case 'r': // 5 strings to match.	case 'd': // 4 strings to match.
	switch (NameR[10]) {	if (NameR[12] != 'm')
		break;
		switch (NameR[13]) {
	default: break;	default: break;
	case 'a': // 2 strings to match.	case 'a': // 2 strings to match.

	if (NameR[11] != '.')	if (NameR.substr(14, 4) != "cs.s")
	break;	break;

	switch (NameR[12]) {	switch (NameR[18]) {
	default: break;	default: break;

	case 'd': // 1 string to match.	case '0': // 1 string to match.
	return Intrinsic::x86_mmx_psra_d; // "86.mmx.psra.d"	return Intrinsic::hexagon_M2_vdmacs_s0; // "exagon.
	case 'w': // 1 string to match.	M2.vdmacs.s0"
	return Intrinsic::x86_mmx_psra_w; // "86.mmx.psra.w"	case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_vdmacs_s1; // "exagon.
		M2.vdmacs.s1"
	}	}
	break;	break;

	case 'l': // 3 strings to match.	case 'p': // 2 strings to match.
	if (NameR[11] != '.')	if (NameR.substr(14, 4) != "ys.s")
	break;	break;

	switch (NameR[12]) {	switch (NameR[18]) {
	default: break;	default: break;

	case 'd': // 1 string to match.	case '0': // 1 string to match.
	return Intrinsic::x86_mmx_psrl_d; // "86.mmx.psrl.d"	return Intrinsic::hexagon_M2_vdmpys_s0; // "exagon.
	case 'q': // 1 string to match.	M2.vdmpys.s0"
	return Intrinsic::x86_mmx_psrl_q; // "86.mmx.psrl.q"	case '1': // 1 string to match.
	case 'w': // 1 string to match.	return Intrinsic::hexagon_M2_vdmpys_s1; // "exagon.
	return Intrinsic::x86_mmx_psrl_w; // "86.mmx.psrl.w"	M2.vdmpys.s1"
	}	}
	break;	break;
	}	}
	break;	break;

	case 'u': // 4 strings to match.	case 'm': // 4 strings to match.
	if (NameR.substr(10, 2) != "b.")
	break;
	switch (NameR[12]) {	switch (NameR[12]) {
	default: break;	default: break;

	case 'b': // 1 string to match.	case 'a': // 2 strings to match.
	return Intrinsic::x86_mmx_psub_b; // "86.mmx.psub.b"	if (NameR.substr(13, 5) != "c2s.s")
	case 'd': // 1 string to match.	break;
	return Intrinsic::x86_mmx_psub_d; // "86.mmx.psub.d"	switch (NameR[18]) {
	case 'q': // 1 string to match.	default: break;
	return Intrinsic::x86_mmx_psub_q; // "86.mmx.psub.q"	case '0': // 1 string to match.
	case 'w': // 1 string to match.	return Intrinsic::hexagon_M2_vmac2s_s0; // "exagon.
	return Intrinsic::x86_mmx_psub_w; // "86.mmx.psub.w"	M2.vmac2s.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_vmac2s_s1; // "exagon.
		M2.vmac2s.s1"
		}
		break;
		case 'p': // 2 strings to match.
		if (NameR.substr(13, 5) != "y2s.s")
		break;
		switch (NameR[18]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_vmpy2s_s0; // "exagon.
		M2.vmpy2s.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_vmpy2s_s1; // "exagon.
		M2.vmpy2s.s1"
		}
		break;
	}	}
	break;	break;
	}	}
	break;	break;
	}	}
	break;	break;

	case 's': // 16 strings to match.	case 'S': // 4 strings to match.
	if (NameR.substr(4, 2) != "se")	if (NameR.substr(8, 2) != "2.")
	break;	break;

	switch (NameR[6]) {	switch (NameR[10]) {
	default: break;	default: break;

	case '.': // 13 strings to match.	case 'e': // 1 string to match.
	switch (NameR[7]) {	if (NameR.substr(11, 8) != "xtractup")
		break;
		return Intrinsic::hexagon_S2_extractup; // "exagon.S2.extra
		ctup"
		case 'i': // 1 string to match.
		if (NameR.substr(11, 8) != "nsert.rp")
		break;
		return Intrinsic::hexagon_S2_insert_rp; // "exagon.S2.inser
		t.rp"
		case 'v': // 2 strings to match.
		if (NameR.substr(11, 6) != "splice")
		break;
		switch (NameR[17]) {
	default: break;	default: break;

	case 'a': // 1 string to match.	case 'i': // 1 string to match.
	if (NameR.substr(8, 5) != "dd.ss")	if (NameR[18] != 'b')
	break;	break;

	return Intrinsic::x86_sse_add_ss; // "86.sse.add.ss"	return Intrinsic::hexagon_S2_vspliceib; // "exagon.S2.vspli
	case 'c': // 2 strings to match.	ceib"
	if (NameR.substr(8, 3) != "mp.")	case 'r': // 1 string to match.
		if (NameR[18] != 'b')
	break;	break;

	switch (NameR[11]) {	return Intrinsic::hexagon_S2_vsplicerb; // "exagon.S2.vspli
	default: break;	cerb"
	case 'p': // 1 string to match.	}
	if (NameR[12] != 's')	break;
	break;	}
	return Intrinsic::x86_sse_cmp_ps; // "86.sse.cmp.ps"	break;
	case 's': // 1 string to match.	}
	if (NameR[12] != 's')	break;
	break;	case 20: // 66 strings to match.
	return Intrinsic::x86_sse_cmp_ss; // "86.sse.cmp.ss"	if (NameR.substr(0, 7) != "exagon.")
	}	break;
		switch (NameR[7]) {
		default: break;
		case 'A': // 4 strings to match.
		if (NameR.substr(8, 10) != "2.combine.")
		break;
		switch (NameR[18]) {
		default: break;
		case 'h': // 2 strings to match.
		switch (NameR[19]) {
		default: break;
		case 'h': // 1 string to match.
		return Intrinsic::hexagon_A2_combine_hh; // "exagon.A2.combi
		ne.hh"
		case 'l': // 1 string to match.
		return Intrinsic::hexagon_A2_combine_hl; // "exagon.A2.combi
		ne.hl"
		}
		break;
		case 'l': // 2 strings to match.
		switch (NameR[19]) {
		default: break;
		case 'h': // 1 string to match.
		return Intrinsic::hexagon_A2_combine_lh; // "exagon.A2.combi
		ne.lh"
		case 'l': // 1 string to match.
		return Intrinsic::hexagon_A2_combine_ll; // "exagon.A2.combi
		ne.ll"
		}
		break;
		}
		break;
		case 'M': // 45 strings to match.
		if (NameR.substr(8, 2) != "2.")
		break;
		switch (NameR[10]) {
		default: break;
		case 'c': // 2 strings to match.
		if (NameR.substr(11, 8) != "mpyrsc.s")
	break;	break;

	case 'd': // 1 string to match.	switch (NameR[19]) {
	if (NameR.substr(8, 5) != "iv.ss")	default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_cmpyrsc_s0; // "exagon.M2.cmpyr
		sc.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_cmpyrsc_s1; // "exagon.M2.cmpyr
		sc.s1"
		}
		break;
		case 'd': // 2 strings to match.
		if (NameR.substr(11, 4) != "pmpy")
		break;
		switch (NameR[15]) {
		default: break;
		case 's': // 1 string to match.
		if (NameR.substr(16, 4) != "s.s0")
	break;	break;

	return Intrinsic::x86_sse_div_ss; // "86.sse.div.ss"	return Intrinsic::hexagon_M2_dpmpyss_s0; // "exagon.M2.dpmpy
	case 'm': // 5 strings to match.	ss.s0"
	switch (NameR[8]) {	case 'u': // 1 string to match.
		if (NameR.substr(16, 4) != "u.s0")
		break;
		return Intrinsic::hexagon_M2_dpmpyuu_s0; // "exagon.M2.dpmpy
		uu.s0"
		}
		break;
		case 'h': // 2 strings to match.
		if (NameR.substr(11, 4) != "mmpy")
		break;
		switch (NameR[15]) {
		default: break;
		case 'h': // 1 string to match.
		if (NameR.substr(16, 4) != ".rs1")
		break;
		return Intrinsic::hexagon_M2_hmmpyh_rs1; // "exagon.M2.hmmpy
		h.rs1"
		case 'l': // 1 string to match.
		if (NameR.substr(16, 4) != ".rs1")
		break;
		return Intrinsic::hexagon_M2_hmmpyl_rs1; // "exagon.M2.hmmpy
		l.rs1"
		}
		break;
		case 'm': // 28 strings to match.
		switch (NameR[11]) {
		default: break;
		case 'm': // 12 strings to match.
		switch (NameR[12]) {
	default: break;	default: break;

	case 'a': // 2 strings to match.	case 'a': // 8 strings to match.
	if (NameR.substr(9, 2) != "x.")	if (NameR[13] != 'c')
	break;	break;

	switch (NameR[11]) {	switch (NameR[14]) {
	default: break;	default: break;

	case 'p': // 1 string to match.	case 'h': // 2 strings to match.
	if (NameR[12] != 's')	if (NameR.substr(15, 4) != "s.rs")
	break;	break;

	return Intrinsic::x86_sse_max_ps; // "86.sse.max.ps"	switch (NameR[19]) {
	case 's': // 1 string to match.	default: break;
	if (NameR[12] != 's')	case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mmachs_rs0; // "exagon.
		M2.mmachs.rs0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mmachs_rs1; // "exagon.
		M2.mmachs.rs1"
		}
		break;
		case 'l': // 2 strings to match.
		if (NameR.substr(15, 4) != "s.rs")
	break;	break;

	return Intrinsic::x86_sse_max_ss; // "86.sse.max.ss"	switch (NameR[19]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mmacls_rs0; // "exagon.
		M2.mmacls.rs0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mmacls_rs1; // "exagon.
		M2.mmacls.rs1"
		}
		break;
		case 'u': // 4 strings to match.
		switch (NameR[15]) {
		default: break;
		case 'h': // 2 strings to match.
		if (NameR.substr(16, 3) != "s.s")
		break;
		switch (NameR[19]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mmacuhs_s0; // "exagon.
		M2.mmacuhs.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mmacuhs_s1; // "exagon.
		M2.mmacuhs.s1"
		}
		break;
		case 'l': // 2 strings to match.
		if (NameR.substr(16, 3) != "s.s")
		break;
		switch (NameR[19]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mmaculs_s0; // "exagon.
		M2.mmaculs.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mmaculs_s1; // "exagon.
		M2.mmaculs.s1"
		}
		break;
		}
		break;
	}	}
	break;	break;

	case 'i': // 2 strings to match.	case 'p': // 4 strings to match.
	if (NameR.substr(9, 2) != "n.")	if (NameR.substr(13, 2) != "yu")
	break;	break;

	switch (NameR[11]) {	switch (NameR[15]) {
	default: break;	default: break;

	case 'p': // 1 string to match.	case 'h': // 2 strings to match.
	if (NameR[12] != 's')	if (NameR.substr(16, 3) != ".rs")
	break;	break;

	return Intrinsic::x86_sse_min_ps; // "86.sse.min.ps"	switch (NameR[19]) {
	case 's': // 1 string to match.	default: break;
	if (NameR[12] != 's')	case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mmpyuh_rs0; // "exagon.
		M2.mmpyuh.rs0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mmpyuh_rs1; // "exagon.
		M2.mmpyuh.rs1"
		}
		break;
		case 'l': // 2 strings to match.
		if (NameR.substr(16, 3) != ".rs")
	break;	break;

	return Intrinsic::x86_sse_min_ss; // "86.sse.min.ss"	switch (NameR[19]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mmpyul_rs0; // "exagon.
		M2.mmpyul.rs0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mmpyul_rs1; // "exagon.
		M2.mmpyul.rs1"
		}
		break;
	}	}
	break;	break;

	case 'u': // 1 string to match.
	if (NameR.substr(9, 4) != "l.ss")
	break;
	return Intrinsic::x86_sse_mul_ss; // "86.sse.mul.ss"
	}	}
	break;	break;

	case 'r': // 2 strings to match.	case 'p': // 16 strings to match.
	if (NameR.substr(8, 3) != "cp.")	if (NameR[12] != 'y')
	break;	break;

	switch (NameR[11]) {	switch (NameR[13]) {
	default: break;
	case 'p': // 1 string to match.
	if (NameR[12] != 's')
	break;
	return Intrinsic::x86_sse_rcp_ps; // "86.sse.rcp.ps"
	case 's': // 1 string to match.
	if (NameR[12] != 's')
	break;
	return Intrinsic::x86_sse_rcp_ss; // "86.sse.rcp.ss"
	}
	break;
	case 's': // 2 strings to match.
	switch (NameR[8]) {
	default: break;
	case 'f': // 1 string to match.
	if (NameR.substr(9, 4) != "ence")
	break;
	return Intrinsic::x86_sse_sfence; // "86.sse.sfence"
	case 'u': // 1 string to match.
	if (NameR.substr(9, 4) != "b.ss")
	break;
	return Intrinsic::x86_sse_sub_ss; // "86.sse.sub.ss"
	}
	break;
	}
	break;
	case '3': // 1 string to match.
	if (NameR.substr(7, 6) != ".mwait")
	break;
	return Intrinsic::x86_sse3_mwait; // "86.sse3.mwait"
	case '4': // 2 strings to match.
	if (NameR.substr(7, 5) != "1.dpp")
	break;
	switch (NameR[12]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::x86_sse41_dppd; // "86.sse41.dppd"
	case 's': // 1 string to match.
	return Intrinsic::x86_sse41_dpps; // "86.sse41.dpps"
	}
	break;
	}
	break;
	}
	break;
	case 14: // 59 strings to match.
	switch (NameR[0]) {
	default: break;
	case '8': // 58 strings to match.
	if (NameR.substr(1, 2) != "6.")
	break;
	switch (NameR[3]) {
	default: break;
	case '3': // 9 strings to match.
	if (NameR.substr(4, 6) != "dnow.p")
	break;
	switch (NameR[10]) {
	default: break;
	case 'f': // 8 strings to match.
	switch (NameR[11]) {
	default: break;	default: break;

	case '2': // 1 string to match.	case 'd': // 8 strings to match.
	if (NameR.substr(12, 2) != "id")	if (NameR[14] != '.')
	break;	break;

	return Intrinsic::x86_3dnow_pf2id; // "86.3dnow.pf2id"	switch (NameR[15]) {
	case 'a': // 2 strings to match.
	switch (NameR[12]) {
	default: break;	default: break;

	case 'c': // 1 string to match.	case 'h': // 4 strings to match.
	if (NameR[13] != 'c')	switch (NameR[16]) {
		default: break;
		case 'h': // 2 strings to match.
		if (NameR.substr(17, 2) != ".s")
		break;
		switch (NameR[19]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyd_hh_s0; // "exagon.
		M2.mpyd.hh.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyd_hh_s1; // "exagon.
		M2.mpyd.hh.s1"
		}
	break;	break;

	return Intrinsic::x86_3dnow_pfacc; // "86.3dnow.pfacc"	case 'l': // 2 strings to match.
	case 'd': // 1 string to match.	if (NameR.substr(17, 2) != ".s")
	if (NameR[13] != 'd')	break;
		switch (NameR[19]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyd_hl_s0; // "exagon.
		M2.mpyd.hl.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyd_hl_s1; // "exagon.
		M2.mpyd.hl.s1"
		}
	break;	break;

	return Intrinsic::x86_3dnow_pfadd; // "86.3dnow.pfadd"	}
		break;
		case 'l': // 4 strings to match.
		switch (NameR[16]) {
		default: break;
		case 'h': // 2 strings to match.
		if (NameR.substr(17, 2) != ".s")
		break;
		switch (NameR[19]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyd_lh_s0; // "exagon.
		M2.mpyd.lh.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyd_lh_s1; // "exagon.
		M2.mpyd.lh.s1"
		}
		break;
		case 'l': // 2 strings to match.
		if (NameR.substr(17, 2) != ".s")
		break;
		switch (NameR[19]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyd_ll_s0; // "exagon.
		M2.mpyd.ll.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyd_ll_s1; // "exagon.
		M2.mpyd.ll.s1"
		}
		break;
		}
		break;
	}	}
	break;	break;

	case 'm': // 3 strings to match.	case 'u': // 8 strings to match.
	switch (NameR[12]) {	if (NameR[14] != '.')
		break;
		switch (NameR[15]) {
	default: break;	default: break;

	case 'a': // 1 string to match.	case 'h': // 4 strings to match.
	if (NameR[13] != 'x')	switch (NameR[16]) {
		default: break;
		case 'h': // 2 strings to match.
		if (NameR.substr(17, 2) != ".s")
		break;
		switch (NameR[19]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyu_hh_s0; // "exagon.
		M2.mpyu.hh.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyu_hh_s1; // "exagon.
		M2.mpyu.hh.s1"
		}
	break;	break;

	return Intrinsic::x86_3dnow_pfmax; // "86.3dnow.pfmax"	case 'l': // 2 strings to match.
	case 'i': // 1 string to match.	if (NameR.substr(17, 2) != ".s")
	if (NameR[13] != 'n')	break;
		switch (NameR[19]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyu_hl_s0; // "exagon.
		M2.mpyu.hl.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyu_hl_s1; // "exagon.
		M2.mpyu.hl.s1"
		}
	break;	break;

	return Intrinsic::x86_3dnow_pfmin; // "86.3dnow.pfmin"	}
	case 'u': // 1 string to match.	break;
	if (NameR[13] != 'l')	case 'l': // 4 strings to match.
		switch (NameR[16]) {
		default: break;
		case 'h': // 2 strings to match.
		if (NameR.substr(17, 2) != ".s")
		break;
		switch (NameR[19]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyu_lh_s0; // "exagon.
		M2.mpyu.lh.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyu_lh_s1; // "exagon.
		M2.mpyu.lh.s1"
		}
	break;	break;

	return Intrinsic::x86_3dnow_pfmul; // "86.3dnow.pfmul"	case 'l': // 2 strings to match.
		if (NameR.substr(17, 2) != ".s")
		break;
		switch (NameR[19]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyu_ll_s0; // "exagon.
		M2.mpyu.ll.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyu_ll_s1; // "exagon.
		M2.mpyu.ll.s1"
		}
		break;
		}
		break;
	}	}
	break;	break;

	case 'r': // 1 string to match.
	if (NameR.substr(12, 2) != "cp")
	break;
	return Intrinsic::x86_3dnow_pfrcp; // "86.3dnow.pfrcp"
	case 's': // 1 string to match.
	if (NameR.substr(12, 2) != "ub")
	break;
	return Intrinsic::x86_3dnow_pfsub; // "86.3dnow.pfsub"
	}	}
	break;	break;

	case 'i': // 1 string to match.
	if (NameR.substr(11, 3) != "2fd")
	break;
	return Intrinsic::x86_3dnow_pi2fd; // "86.3dnow.pi2fd"
	}	}
	break;	break;

	case 'm': // 21 strings to match.	case 'v': // 11 strings to match.
	if (NameR.substr(4, 4) != "mx.p")	switch (NameR[11]) {
	break;
	switch (NameR[8]) {
	default: break;	default: break;

	case 'a': // 2 strings to match.	case 'd': // 2 strings to match.
	if (NameR.substr(9, 4) != "dds.")	if (NameR.substr(12, 7) != "mpyrs.s")
	break;	break;

	switch (NameR[13]) {	switch (NameR[19]) {
	default: break;	default: break;

	case 'b': // 1 string to match.	case '0': // 1 string to match.
	return Intrinsic::x86_mmx_padds_b; // "86.mmx.padds.b"	return Intrinsic::hexagon_M2_vdmpyrs_s0; // "exagon.M2.vdmpy
	case 'w': // 1 string to match.	rs.s0"
	return Intrinsic::x86_mmx_padds_w; // "86.mmx.padds.w"	case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_vdmpyrs_s1; // "exagon.M2.vdmpy
		rs.s1"
	}	}
	break;	break;

	case 'e': // 1 string to match.	case 'm': // 4 strings to match.
	if (NameR.substr(9, 5) != "xtr.w")	switch (NameR[12]) {
		default: break;
		case 'a': // 2 strings to match.
		if (NameR.substr(13, 6) != "c2es.s")
		break;
		switch (NameR[19]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_vmac2es_s0; // "exagon.
		M2.vmac2es.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_vmac2es_s1; // "exagon.
		M2.vmac2es.s1"
		}
	break;	break;

	return Intrinsic::x86_mmx_pextr_w; // "86.mmx.pextr.w"	case 'p': // 2 strings to match.
	case 'i': // 1 string to match.	if (NameR.substr(13, 6) != "y2es.s")
	if (NameR.substr(9, 5) != "nsr.w")	break;
		switch (NameR[19]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_vmpy2es_s0; // "exagon.
		M2.vmpy2es.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_vmpy2es_s1; // "exagon.
		M2.vmpy2es.s1"
		}
	break;	break;

	return Intrinsic::x86_mmx_pinsr_w; // "86.mmx.pinsr.w"	}
	case 'm': // 6 strings to match.	break;
	switch (NameR[9]) {	case 'r': // 5 strings to match.
		if (NameR.substr(12, 2) != "cm")
		break;
		switch (NameR[14]) {
	default: break;	default: break;
	case 'a': // 2 strings to match.	case 'a': // 2 strings to match.

	if (NameR[10] != 'x')	if (NameR[15] != 'c')
	break;	break;

	switch (NameR[11]) {	switch (NameR[16]) {
	default: break;	default: break;

	case 's': // 1 string to match.	case 'i': // 1 string to match.
	if (NameR.substr(12, 2) != ".w")	if (NameR.substr(17, 3) != ".s0")
	break;	break;

	return Intrinsic::x86_mmx_pmaxs_w; // "86.mmx.pmaxs.w"	return Intrinsic::hexagon_M2_vrcmaci_s0; // "exagon.
	case 'u': // 1 string to match.	M2.vrcmaci.s0"
	if (NameR.substr(12, 2) != ".b")	case 'r': // 1 string to match.
		if (NameR.substr(17, 3) != ".s0")
	break;	break;

	return Intrinsic::x86_mmx_pmaxu_b; // "86.mmx.pmaxu.b"	return Intrinsic::hexagon_M2_vrcmacr_s0; // "exagon. M2.vrcmacr.s0"
	}	}
	break;	break;

	case 'i': // 2 strings to match.	case 'p': // 3 strings to match.
	if (NameR[10] != 'n')	if (NameR[15] != 'y')
	break;	break;

	switch (NameR[11]) {	switch (NameR[16]) {
	default: break;	default: break;

		case 'i': // 1 string to match.
		if (NameR.substr(17, 3) != ".s0")
		break;
		return Intrinsic::hexagon_M2_vrcmpyi_s0; // "exagon.
		M2.vrcmpyi.s0"
		case 'r': // 1 string to match.
		if (NameR.substr(17, 3) != ".s0")
		break;
		return Intrinsic::hexagon_M2_vrcmpyr_s0; // "exagon.
		M2.vrcmpyr.s0"
	case 's': // 1 string to match.	case 's': // 1 string to match.

	if (NameR.substr(12, 2) != ".w")	if (NameR.substr(17, 3) != ".s1")
	break;	break;

	return Intrinsic::x86_mmx_pmins_w; // "86.mmx.pmins.w"	return Intrinsic::hexagon_M2_vrcmpys_s1; // "exagon.
	case 'u': // 1 string to match.	M2.vrcmpys.s1"
	if (NameR.substr(12, 2) != ".b")	}
		break;
		}
		break;
		}
		break;
		}
		break;
		case 'S': // 17 strings to match.
		if (NameR.substr(8, 2) != "2.")
		break;
		switch (NameR[10]) {
		default: break;
		case 'a': // 8 strings to match.
		if (NameR[11] != 's')
		break;
		switch (NameR[12]) {
		default: break;
		case 'l': // 4 strings to match.
		if (NameR[13] != '.')
		break;
		switch (NameR[14]) {
		default: break;
		case 'i': // 2 strings to match.
		if (NameR[15] != '.')
		break;
		switch (NameR[16]) {
		default: break;
		case 'p': // 1 string to match.
		if (NameR.substr(17, 3) != ".or")
	break;	break;

	return Intrinsic::x86_mmx_pminu_b; // "86.mmx.pminu.b"	return Intrinsic::hexagon_S2_asl_i_p_or; // "exagon.
		S2.asl.i.p.or"
		case 'r': // 1 string to match.
		if (NameR.substr(17, 3) != ".or")
		break;
		return Intrinsic::hexagon_S2_asl_i_r_or; // "exagon.
		S2.asl.i.r.or"
	}	}
	break;	break;

	case 'u': // 2 strings to match.	case 'r': // 2 strings to match.
	if (NameR[10] != 'l')	if (NameR[15] != '.')
	break;	break;

	switch (NameR[11]) {	switch (NameR[16]) {
	default: break;	default: break;

	case 'h': // 1 string to match.	case 'p': // 1 string to match.
	if (NameR.substr(12, 2) != ".w")	if (NameR.substr(17, 3) != ".or")
	break;	break;

	return Intrinsic::x86_mmx_pmulh_w; // "86.mmx.pmulh.w"	return Intrinsic::hexagon_S2_asl_r_p_or; // "exagon.
	case 'l': // 1 string to match.	S2.asl.r.p.or"
	if (NameR.substr(12, 2) != ".w")	case 'r': // 1 string to match.
		if (NameR.substr(17, 3) != ".or")
	break;	break;

	return Intrinsic::x86_mmx_pmull_w; // "86.mmx.pmull.w"	return Intrinsic::hexagon_S2_asl_r_r_or; // "exagon. S2.asl.r.r.or"
	}	}
	break;	break;
	}	}
	break;	break;

	case 's': // 11 strings to match.	case 'r': // 4 strings to match.
	switch (NameR[9]) {	if (NameR[13] != '.')
		break;
		switch (NameR[14]) {
	default: break;	default: break;

	case 'a': // 1 string to match.	case 'i': // 2 strings to match.
	if (NameR.substr(10, 4) != "d.bw")	if (NameR[15] != '.')
	break;
	return Intrinsic::x86_mmx_psad_bw; // "86.mmx.psad.bw"
	case 'l': // 3 strings to match.
	if (NameR.substr(10, 3) != "li.")
	break;	break;

	switch (NameR[13]) {	switch (NameR[16]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::x86_mmx_pslli_d; // "86.mmx.pslli.d"
	case 'q': // 1 string to match.
	return Intrinsic::x86_mmx_pslli_q; // "86.mmx.pslli.q"
	case 'w': // 1 string to match.
	return Intrinsic::x86_mmx_pslli_w; // "86.mmx.pslli.w"
	}
	break;
	case 'r': // 5 strings to match.
	switch (NameR[10]) {
	default: break;	default: break;

	case 'a': // 2 strings to match.	case 'p': // 1 string to match.
	if (NameR.substr(11, 2) != "i.")	if (NameR.substr(17, 3) != ".or")
	break;	break;

	switch (NameR[13]) {	return Intrinsic::hexagon_S2_asr_i_p_or; // "exagon.
	default: break;	S2.asr.i.p.or"
	case 'd': // 1 string to match.	case 'r': // 1 string to match.
	return Intrinsic::x86_mmx_psrai_d; // "86.mmx.psrai.d"	if (NameR.substr(17, 3) != ".or")
	case 'w': // 1 string to match.
	return Intrinsic::x86_mmx_psrai_w; // "86.mmx.psrai.w"
	}
	break;
	case 'l': // 3 strings to match.
	if (NameR.substr(11, 2) != "i.")
	break;	break;

	switch (NameR[13]) {	return Intrinsic::hexagon_S2_asr_i_r_or; // "exagon.
	default: break;	S2.asr.i.r.or"
	case 'd': // 1 string to match.
	return Intrinsic::x86_mmx_psrli_d; // "86.mmx.psrli.d"
	case 'q': // 1 string to match.
	return Intrinsic::x86_mmx_psrli_q; // "86.mmx.psrli.q"
	case 'w': // 1 string to match.
	return Intrinsic::x86_mmx_psrli_w; // "86.mmx.psrli.w"
	}
	break;
	}	}
	break;	break;

	case 'u': // 2 strings to match.	case 'r': // 2 strings to match.
	if (NameR.substr(10, 3) != "bs.")	if (NameR[15] != '.')
	break;	break;

	switch (NameR[13]) {	switch (NameR[16]) {
	default: break;	default: break;

	case 'b': // 1 string to match.	case 'p': // 1 string to match.
	return Intrinsic::x86_mmx_psubs_b; // "86.mmx.psubs.b"	if (NameR.substr(17, 3) != ".or")
	case 'w': // 1 string to match.	break;
	return Intrinsic::x86_mmx_psubs_w; // "86.mmx.psubs.w"	return Intrinsic::hexagon_S2_asr_r_p_or; // "exagon.
		S2.asr.r.p.or"
		case 'r': // 1 string to match.
		if (NameR.substr(17, 3) != ".or")
		break;
		return Intrinsic::hexagon_S2_asr_r_r_or; // "exagon.
		S2.asr.r.r.or"
	}	}
	break;	break;
	}	}
	break;	break;
	}	}
	break;	break;

	case 's': // 28 strings to match.	case 'i': // 2 strings to match.
	if (NameR.substr(4, 2) != "se")	if (NameR[11] != 'n')
	break;	break;

	switch (NameR[6]) {	switch (NameR[12]) {
	default: break;	default: break;

	case '.': // 5 strings to match.	case 's': // 1 string to match.
	switch (NameR[7]) {	if (NameR.substr(13, 7) != "ertp.rp")
		break;
		return Intrinsic::hexagon_S2_insertp_rp; // "exagon.S2.inser
		tp.rp"
		case 't': // 1 string to match.
		if (NameR.substr(13, 7) != "erleave")
		break;
		return Intrinsic::hexagon_S2_interleave; // "exagon.S2.inter
		leave"
		}
		break;
		case 'l': // 6 strings to match.
		if (NameR[11] != 's')
		break;
		switch (NameR[12]) {
		default: break;
		case 'l': // 2 strings to match.
		if (NameR.substr(13, 3) != ".r.")
		break;
		switch (NameR[16]) {
	default: break;	default: break;

	case 'l': // 1 string to match.
	if (NameR.substr(8, 6) != "dmxcsr")
	break;
	return Intrinsic::x86_sse_ldmxcsr; // "86.sse.ldmxcsr"
	case 'p': // 1 string to match.	case 'p': // 1 string to match.

	if (NameR.substr(8, 6) != "shuf.w")	if (NameR.substr(17, 3) != ".or")
	break;	break;

	return Intrinsic::x86_sse_pshuf_w; // "86.sse.pshuf.w"	return Intrinsic::hexagon_S2_lsl_r_p_or; // "exagon.S2.lsl.r
	case 's': // 3 strings to match.	.p.or"
	switch (NameR[8]) {	case 'r': // 1 string to match.
	default: break;	if (NameR.substr(17, 3) != ".or")
	case 'q': // 2 strings to match.
	if (NameR.substr(9, 3) != "rt.")
	break;
	switch (NameR[12]) {
	default: break;
	case 'p': // 1 string to match.
	if (NameR[13] != 's')
	break;
	return Intrinsic::x86_sse_sqrt_ps; // "86.sse.sqrt.ps"
	case 's': // 1 string to match.
	if (NameR[13] != 's')
	break;
	return Intrinsic::x86_sse_sqrt_ss; // "86.sse.sqrt.ss"
	}
	break;	break;

	case 't': // 1 string to match.	return Intrinsic::hexagon_S2_lsl_r_r_or; // "exagon.S2.lsl.r
	if (NameR.substr(9, 5) != "mxcsr")	.r.or"
	break;
	return Intrinsic::x86_sse_stmxcsr; // "86.sse.stmxcsr"
	}
	break;
	}	}
	break;	break;

	case '2': // 22 strings to match.	case 'r': // 4 strings to match.
	if (NameR[7] != '.')	if (NameR[13] != '.')
	break;	break;

	switch (NameR[8]) {	switch (NameR[14]) {
	default: break;	default: break;

	case 'a': // 1 string to match.	case 'i': // 2 strings to match.
	if (NameR.substr(9, 5) != "dd.sd")	if (NameR[15] != '.')
	break;
	return Intrinsic::x86_sse2_add_sd; // "86.sse2.add.sd"
	case 'c': // 2 strings to match.
	if (NameR.substr(9, 3) != "mp.")
	break;	break;

	switch (NameR[12]) {	switch (NameR[16]) {
	default: break;	default: break;
	case 'p': // 1 string to match.	case 'p': // 1 string to match.

	if (NameR[13] != 'd')	if (NameR.substr(17, 3) != ".or")
	break;	break;

	return Intrinsic::x86_sse2_cmp_pd; // "86.sse2.cmp.pd"	return Intrinsic::hexagon_S2_lsr_i_p_or; // "exagon.
	case 's': // 1 string to match.	S2.lsr.i.p.or"
	if (NameR[13] != 'd')	case 'r': // 1 string to match.
		if (NameR.substr(17, 3) != ".or")
	break;	break;

	return Intrinsic::x86_sse2_cmp_sd; // "86.sse2.cmp.sd"	return Intrinsic::hexagon_S2_lsr_i_r_or; // "exagon. S2.lsr.i.r.or"
	}	}
	break;	break;

	case 'd': // 1 string to match.	case 'r': // 2 strings to match.
	if (NameR.substr(9, 5) != "iv.sd")	if (NameR[15] != '.')
	break;	break;

	return Intrinsic::x86_sse2_div_sd; // "86.sse2.div.sd"	switch (NameR[16]) {
	case 'l': // 1 string to match.
	if (NameR.substr(9, 5) != "fence")
	break;
	return Intrinsic::x86_sse2_lfence; // "86.sse2.lfence"
	case 'm': // 6 strings to match.
	switch (NameR[9]) {
	default: break;	default: break;

	case 'a': // 2 strings to match.	case 'p': // 1 string to match.
	if (NameR.substr(10, 2) != "x.")	if (NameR.substr(17, 3) != ".or")
	break;
	switch (NameR[12]) {
	default: break;
	case 'p': // 1 string to match.
	if (NameR[13] != 'd')
	break;
	return Intrinsic::x86_sse2_max_pd; // "86.sse2.max.pd"
	case 's': // 1 string to match.
	if (NameR[13] != 'd')
	break;
	return Intrinsic::x86_sse2_max_sd; // "86.sse2.max.sd"
	}
	break;
	case 'f': // 1 string to match.
	if (NameR.substr(10, 4) != "ence")
	break;
	return Intrinsic::x86_sse2_mfence; // "86.sse2.mfence"
	case 'i': // 2 strings to match.
	if (NameR.substr(10, 2) != "n.")
	break;	break;

	switch (NameR[12]) {	return Intrinsic::hexagon_S2_lsr_r_p_or; // "exagon.
	default: break;	S2.lsr.r.p.or"
	case 'p': // 1 string to match.	case 'r': // 1 string to match.
	if (NameR[13] != 'd')	if (NameR.substr(17, 3) != ".or")
	break;
	return Intrinsic::x86_sse2_min_pd; // "86.sse2.min.pd"
	case 's': // 1 string to match.
	if (NameR[13] != 'd')
	break;
	return Intrinsic::x86_sse2_min_sd; // "86.sse2.min.sd"
	}
	break;
	case 'u': // 1 string to match.
	if (NameR.substr(10, 4) != "l.sd")
	break;	break;

	return Intrinsic::x86_sse2_mul_sd; // "86.sse2.mul.sd"	return Intrinsic::hexagon_S2_lsr_r_r_or; // "exagon. S2.lsr.r.r.or"
	}	}
	break;	break;

	case 'p': // 10 strings to match.	}
	switch (NameR[9]) {	break;
		}
		break;
		case 'v': // 1 string to match.
		if (NameR.substr(11, 9) != "rndpackwh")
		break;
		return Intrinsic::hexagon_S2_vrndpackwh; // "exagon.S2.vrndp
		ackwh"
		}
		break;
		}
		break;
		case 21: // 84 strings to match.
		if (NameR.substr(0, 7) != "exagon.")
		break;
		switch (NameR[7]) {
		default: break;
		case 'A': // 16 strings to match.
		if (NameR.substr(8, 2) != "2.")
		break;
		switch (NameR[10]) {
		default: break;
		case 'a': // 8 strings to match.
		if (NameR.substr(11, 4) != "ddh.")
		break;
		switch (NameR[15]) {
		default: break;
		case 'h': // 4 strings to match.
		if (NameR.substr(16, 3) != "16.")
		break;
		switch (NameR[19]) {
		default: break;
		case 'h': // 2 strings to match.
		switch (NameR[20]) {
	default: break;	default: break;

	case 'a': // 2 strings to match.	case 'h': // 1 string to match.
	if (NameR.substr(10, 3) != "vg.")	return Intrinsic::hexagon_A2_addh_h16_hh; // "exagon.
	break;	A2.addh.h16.hh"
	switch (NameR[13]) {	case 'l': // 1 string to match.
	default: break;	return Intrinsic::hexagon_A2_addh_h16_hl; // "exagon.
	case 'b': // 1 string to match.	A2.addh.h16.hl"
	return Intrinsic::x86_sse2_pavg_b; // "86.sse2.pavg.b"	}
	case 'w': // 1 string to match.	break;
	return Intrinsic::x86_sse2_pavg_w; // "86.sse2.pavg.w"	case 'l': // 2 strings to match.
	}	switch (NameR[20]) {
	break;	default: break;
	case 's': // 8 strings to match.	case 'h': // 1 string to match.
	switch (NameR[10]) {	return Intrinsic::hexagon_A2_addh_h16_lh; // "exagon.
	default: break;	A2.addh.h16.lh"
	case 'l': // 3 strings to match.	case 'l': // 1 string to match.
	if (NameR.substr(11, 2) != "l.")	return Intrinsic::hexagon_A2_addh_h16_ll; // "exagon.
	break;	A2.addh.h16.ll"
	switch (NameR[13]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::x86_sse2_psll_d; // "86.sse2.psll.d"
	case 'q': // 1 string to match.
	return Intrinsic::x86_sse2_psll_q; // "86.sse2.psll.q"
	case 'w': // 1 string to match.
	return Intrinsic::x86_sse2_psll_w; // "86.sse2.psll.w"
	}
	break;
	case 'r': // 5 strings to match.
	switch (NameR[11]) {
	default: break;
	case 'a': // 2 strings to match.
	if (NameR[12] != '.')
	break;
	switch (NameR[13]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::x86_sse2_psra_d; // "86.sse2
	.psra.d"
	case 'w': // 1 string to match.
	return Intrinsic::x86_sse2_psra_w; // "86.sse2
	.psra.w"
	}
	break;
	case 'l': // 3 strings to match.
	if (NameR[12] != '.')
	break;
	switch (NameR[13]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::x86_sse2_psrl_d; // "86.sse2
	.psrl.d"
	case 'q': // 1 string to match.
	return Intrinsic::x86_sse2_psrl_q; // "86.sse2
	.psrl.q"
	case 'w': // 1 string to match.
	return Intrinsic::x86_sse2_psrl_w; // "86.sse2
	.psrl.w"
	}
	break;
	}
	break;
	}
	break;
	}	}
	break;	break;

	case 's': // 1 string to match.
	if (NameR.substr(9, 5) != "ub.sd")
	break;
	return Intrinsic::x86_sse2_sub_sd; // "86.sse2.sub.sd"
	}	}
	break;	break;

	case '3': // 1 string to match.	case 'l': // 4 strings to match.
	if (NameR.substr(7, 7) != ".ldu.dq")	if (NameR.substr(16, 3) != "16.")
	break;	break;

	return Intrinsic::x86_sse3_ldu_dq; // "86.sse3.ldu.dq"	switch (NameR[19]) {
		default: break;
		case 'h': // 2 strings to match.
		switch (NameR[20]) {
		default: break;
		case 'h': // 1 string to match.
		return Intrinsic::hexagon_A2_addh_l16_hh; // "exagon.
		A2.addh.l16.hh"
		case 'l': // 1 string to match.
		return Intrinsic::hexagon_A2_addh_l16_hl; // "exagon.
		A2.addh.l16.hl"
		}
		break;
		case 'l': // 2 strings to match.
		switch (NameR[20]) {
		default: break;
		case 'h': // 1 string to match.
		return Intrinsic::hexagon_A2_addh_l16_lh; // "exagon.
		A2.addh.l16.lh"
		case 'l': // 1 string to match.
		return Intrinsic::hexagon_A2_addh_l16_ll; // "exagon.
		A2.addh.l16.ll"
		}
		break;
		}
		break;
	}	}
	break;	break;

	}	case 's': // 6 strings to match.
	break;	if (NameR.substr(11, 4) != "ubh.")
	case 'c': // 1 string to match.
	if (NameR.substr(1, 13) != "ore.waitevent")
	break;
	return Intrinsic::xcore_waitevent; // "core.waitevent"
	}
	break;
	case 15: // 80 strings to match.
	switch (NameR[0]) {
	default: break;
	case '8': // 79 strings to match.
	if (NameR.substr(1, 2) != "6.")
	break;
	switch (NameR[3]) {
	default: break;
	case '3': // 3 strings to match.
	if (NameR.substr(4, 4) != "dnow")
	break;	break;

	switch (NameR[8]) {	switch (NameR[15]) {
	default: break;	default: break;

	case '.': // 1 string to match.	case 'h': // 4 strings to match.
	if (NameR.substr(9, 6) != "pfsubr")	if (NameR.substr(16, 3) != "16.")
	break;	break;

	return Intrinsic::x86_3dnow_pfsubr; // "86.3dnow.pfsubr	switch (NameR[19]) {
	"	default: break;
	case 'a': // 2 strings to match.	case 'h': // 2 strings to match.
	if (NameR.substr(9, 2) != ".p")	switch (NameR[20]) {
		default: break;
		case 'h': // 1 string to match.
		return Intrinsic::hexagon_A2_subh_h16_hh; // "exagon.
		A2.subh.h16.hh"
		case 'l': // 1 string to match.
		return Intrinsic::hexagon_A2_subh_h16_hl; // "exagon.
		A2.subh.h16.hl"
		}
	break;	break;

	switch (NameR[11]) {	case 'l': // 2 strings to match.
		switch (NameR[20]) {
		default: break;
		case 'h': // 1 string to match.
		return Intrinsic::hexagon_A2_subh_h16_lh; // "exagon.
		A2.subh.h16.lh"
		case 'l': // 1 string to match.
		return Intrinsic::hexagon_A2_subh_h16_ll; // "exagon.
		A2.subh.h16.ll"
		}
		break;
		}
		break;
		case 'l': // 2 strings to match.
		if (NameR.substr(16, 3) != "16.")
		break;
		switch (NameR[19]) {
	default: break;	default: break;

	case 'f': // 1 string to match.	case 'h': // 1 string to match.
	if (NameR.substr(12, 3) != "2iw")	if (NameR[20] != 'l')
	break;	break;

	return Intrinsic::x86_3dnowa_pf2iw; // "86.3dnowa.pf2iw	return Intrinsic::hexagon_A2_subh_l16_hl; // "exagon.
	"	A2.subh.l16.hl"
	case 'i': // 1 string to match.	case 'l': // 1 string to match.
	if (NameR.substr(12, 3) != "2fw")	if (NameR[20] != 'l')
	break;	break;

	return Intrinsic::x86_3dnowa_pi2fw; // "86.3dnowa.pi2fw "	return Intrinsic::hexagon_A2_subh_l16_ll; // "exagon. A2.subh.l16.ll"
	}	}
	break;	break;
	}	}
	break;	break;

	case 'a': // 4 strings to match.	case 'v': // 2 strings to match.
	switch (NameR[4]) {	if (NameR[11] != 'r')
		break;
		switch (NameR[12]) {
	default: break;	default: break;

	case 'e': // 3 strings to match.	case 'a': // 1 string to match.
	if (NameR.substr(5, 7) != "sni.aes")	if (NameR.substr(13, 8) != "ddub.acc")
	break;	break;

	switch (NameR[12]) {	return Intrinsic::hexagon_A2_vraddub_acc; // "exagon.A2.vradd
	default: break;	ub.acc"
	case 'd': // 1 string to match.	case 's': // 1 string to match.
	if (NameR.substr(13, 2) != "ec")	if (NameR.substr(13, 8) != "adub.acc")
	break;
	return Intrinsic::x86_aesni_aesdec; // "86.aesni.aesdec
	"
	case 'e': // 1 string to match.
	if (NameR.substr(13, 2) != "nc")
	break;
	return Intrinsic::x86_aesni_aesenc; // "86.aesni.aesenc
	"
	case 'i': // 1 string to match.
	if (NameR.substr(13, 2) != "mc")
	break;
	return Intrinsic::x86_aesni_aesimc; // "86.aesni.aesimc
	"
	}
	break;
	case 'v': // 1 string to match.
	if (NameR.substr(5, 10) != "x.vzeroall")
	break;	break;

	return Intrinsic::x86_avx_vzeroall; // "86.avx.vzeroall "	return Intrinsic::hexagon_A2_vrsadub_acc; // "exagon.A2.vrsad ub.acc"
	}	}
	break;	break;

	case 'm': // 19 strings to match.	}
	if (NameR.substr(4, 3) != "mx.")	break;
	break;	case 'C': // 1 string to match.
	switch (NameR[7]) {	if (NameR.substr(8, 13) != "4.fastcorner9")
		break;
		return Intrinsic::hexagon_C4_fastcorner9; // "exagon.C4.fastc
		orner9"
		case 'M': // 16 strings to match.
		if (NameR.substr(8, 2) != "2.")
		break;
		switch (NameR[10]) {
		default: break;
		case 'm': // 12 strings to match.
		switch (NameR[11]) {
	default: break;	default: break;

	case 'm': // 2 strings to match.	case 'm': // 4 strings to match.
	switch (NameR[8]) {	if (NameR.substr(12, 3) != "acu")
		break;
		switch (NameR[15]) {
	default: break;	default: break;

	case 'a': // 1 string to match.	case 'h': // 2 strings to match.
	if (NameR.substr(9, 6) != "skmovq")	if (NameR.substr(16, 4) != "s.rs")
	break;	break;

	return Intrinsic::x86_mmx_maskmovq; // "86.mmx.maskmovq	switch (NameR[20]) {
	"	default: break;
	case 'o': // 1 string to match.	case '0': // 1 string to match.
	if (NameR.substr(9, 6) != "vnt.dq")	return Intrinsic::hexagon_M2_mmacuhs_rs0; // "exagon.
		M2.mmacuhs.rs0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mmacuhs_rs1; // "exagon.
		M2.mmacuhs.rs1"
		}
		break;
		case 'l': // 2 strings to match.
		if (NameR.substr(16, 4) != "s.rs")
	break;	break;

	return Intrinsic::x86_mmx_movnt_dq; // "86.mmx.movnt.dq	switch (NameR[20]) {
	"	default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mmaculs_rs0; // "exagon.
		M2.mmaculs.rs0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mmaculs_rs1; // "exagon.
		M2.mmaculs.rs1"
		}
		break;
	}	}
	break;	break;

	case 'p': // 17 strings to match.	case 'p': // 8 strings to match.
	switch (NameR[8]) {	if (NameR.substr(12, 4) != "yud.")
		break;
		switch (NameR[16]) {
	default: break;	default: break;

	case 'a': // 5 strings to match.	case 'h': // 4 strings to match.
	switch (NameR[9]) {	switch (NameR[17]) {
	default: break;	default: break;

	case 'c': // 3 strings to match.	case 'h': // 2 strings to match.
	if (NameR[10] != 'k')	if (NameR.substr(18, 2) != ".s")
	break;	break;

	switch (NameR[11]) {	switch (NameR[20]) {
	default: break;	default: break;

	case 's': // 2 strings to match.	case '0': // 1 string to match.
	if (NameR[12] != 's')	return Intrinsic::hexagon_M2_mpyud_hh_s0; // "exagon.
	break;	M2.mpyud.hh.s0"
	switch (NameR[13]) {	case '1': // 1 string to match.
	default: break;	return Intrinsic::hexagon_M2_mpyud_hh_s1; // "exagon.
	case 'd': // 1 string to match.	M2.mpyud.hh.s1"
	if (NameR[14] != 'w')
	break;
	return Intrinsic::x86_mmx_packssdw; // "86.mmx.
	packssdw"
	case 'w': // 1 string to match.
	if (NameR[14] != 'b')
	break;
	return Intrinsic::x86_mmx_packsswb; // "86.mmx.
	packsswb"
	}
	break;
	case 'u': // 1 string to match.
	if (NameR.substr(12, 3) != "swb")
	break;
	return Intrinsic::x86_mmx_packuswb; // "86.mmx.packuswb
	"
	}	}
	break;	break;

	case 'd': // 2 strings to match.	case 'l': // 2 strings to match.
	if (NameR.substr(10, 4) != "dus.")	if (NameR.substr(18, 2) != ".s")
	break;	break;

	switch (NameR[14]) {	switch (NameR[20]) {
	default: break;	default: break;

	case 'b': // 1 string to match.	case '0': // 1 string to match.
	return Intrinsic::x86_mmx_paddus_b; // "86.mmx.paddus.b	return Intrinsic::hexagon_M2_mpyud_hl_s0; // "exagon.
	"	M2.mpyud.hl.s0"
	case 'w': // 1 string to match.	case '1': // 1 string to match.
	return Intrinsic::x86_mmx_paddus_w; // "86.mmx.paddus.w	return Intrinsic::hexagon_M2_mpyud_hl_s1; // "exagon.
	"	M2.mpyud.hl.s1"
	}	}
	break;	break;
	}	}
	break;	break;

	case 'c': // 6 strings to match.	case 'l': // 4 strings to match.
	if (NameR.substr(9, 2) != "mp")	switch (NameR[17]) {
	break;
	switch (NameR[11]) {
	default: break;	default: break;

	case 'e': // 3 strings to match.	case 'h': // 2 strings to match.
	if (NameR.substr(12, 2) != "q.")	if (NameR.substr(18, 2) != ".s")
	break;	break;

	switch (NameR[14]) {	switch (NameR[20]) {
	default: break;	default: break;

	case 'b': // 1 string to match.	case '0': // 1 string to match.
	return Intrinsic::x86_mmx_pcmpeq_b; // "86.mmx.pcmpeq.b	return Intrinsic::hexagon_M2_mpyud_lh_s0; // "exagon.
	"	M2.mpyud.lh.s0"
	case 'd': // 1 string to match.	case '1': // 1 string to match.
	return Intrinsic::x86_mmx_pcmpeq_d; // "86.mmx.pcmpeq.d	return Intrinsic::hexagon_M2_mpyud_lh_s1; // "exagon.
	"	M2.mpyud.lh.s1"
	case 'w': // 1 string to match.
	return Intrinsic::x86_mmx_pcmpeq_w; // "86.mmx.pcmpeq.w
	"
	}	}
	break;	break;

	case 'g': // 3 strings to match.	case 'l': // 2 strings to match.
	if (NameR.substr(12, 2) != "t.")	if (NameR.substr(18, 2) != ".s")
	break;	break;

	switch (NameR[14]) {	switch (NameR[20]) {
	default: break;	default: break;

	case 'b': // 1 string to match.	case '0': // 1 string to match.
	return Intrinsic::x86_mmx_pcmpgt_b; // "86.mmx.pcmpgt.b	return Intrinsic::hexagon_M2_mpyud_ll_s0; // "exagon.
	"	M2.mpyud.ll.s0"
	case 'd': // 1 string to match.	case '1': // 1 string to match.
	return Intrinsic::x86_mmx_pcmpgt_d; // "86.mmx.pcmpgt.d	return Intrinsic::hexagon_M2_mpyud_ll_s1; // "exagon.
	"	M2.mpyud.ll.s1"
	case 'w': // 1 string to match.
	return Intrinsic::x86_mmx_pcmpgt_w; // "86.mmx.pcmpgt.w
	"
	}	}
	break;	break;
	}	}
	break;	break;

	case 'm': // 4 strings to match.	}
	switch (NameR[9]) {	break;
	default: break;	}
	case 'a': // 1 string to match.	break;
	if (NameR.substr(10, 5) != "dd.wd")	case 'v': // 4 strings to match.
	break;	if (NameR.substr(11, 3) != "rcm")
	return Intrinsic::x86_mmx_pmadd_wd; // "86.mmx.pmadd.wd	break;
	"	switch (NameR[14]) {
	case 'o': // 1 string to match.	default: break;
	if (NameR.substr(10, 5) != "vmskb")	case 'a': // 2 strings to match.
	break;	if (NameR[15] != 'c')
	return Intrinsic::x86_mmx_pmovmskb; // "86.mmx.pmovmskb
	"
	case 'u': // 2 strings to match.
	if (NameR[10] != 'l')
	break;
	switch (NameR[11]) {
	default: break;
	case 'h': // 1 string to match.
	if (NameR.substr(12, 3) != "u.w")
	break;
	return Intrinsic::x86_mmx_pmulhu_w; // "86.mmx.pmulhu.w
	"
	case 'u': // 1 string to match.
	if (NameR.substr(12, 3) != ".dq")
	break;
	return Intrinsic::x86_mmx_pmulu_dq; // "86.mmx.pmulu.dq
	"
	}
	break;
	}
	break;	break;

	case 's': // 2 strings to match.	switch (NameR[16]) {
	if (NameR.substr(9, 5) != "ubus.")	default: break;
		case 'i': // 1 string to match.
		if (NameR.substr(17, 4) != ".s0c")
	break;	break;

	switch (NameR[14]) {	return Intrinsic::hexagon_M2_vrcmaci_s0c; // "exagon.
	default: break;	M2.vrcmaci.s0c"
	case 'b': // 1 string to match.	case 'r': // 1 string to match.
	return Intrinsic::x86_mmx_psubus_b; // "86.mmx.psubus.b	if (NameR.substr(17, 4) != ".s0c")
	"	break;
	case 'w': // 1 string to match.	return Intrinsic::hexagon_M2_vrcmacr_s0c; // "exagon.
	return Intrinsic::x86_mmx_psubus_w; // "86.mmx.psubus.w	M2.vrcmacr.s0c"
	"	}
	}	break;
		case 'p': // 2 strings to match.
		if (NameR[15] != 'y')
	break;	break;

		switch (NameR[16]) {
		default: break;
		case 'i': // 1 string to match.
		if (NameR.substr(17, 4) != ".s0c")
		break;
		return Intrinsic::hexagon_M2_vrcmpyi_s0c; // "exagon.
		M2.vrcmpyi.s0c"
		case 'r': // 1 string to match.
		if (NameR.substr(17, 4) != ".s0c")
		break;
		return Intrinsic::hexagon_M2_vrcmpyr_s0c; // "exagon.
		M2.vrcmpyr.s0c"
	}	}
	break;	break;
	}	}
	break;	break;

	case 's': // 53 strings to match.	}
	if (NameR[4] != 's')	break;
	break;	case 'S': // 51 strings to match.
	switch (NameR[5]) {	if (NameR.substr(8, 2) != "2.")
		break;
		switch (NameR[10]) {
		default: break;
		case 'a': // 29 strings to match.
		switch (NameR[11]) {
	default: break;	default: break;

	case 'e': // 50 strings to match.	case 'd': // 1 string to match.
	switch (NameR[6]) {	if (NameR.substr(12, 9) != "dasl.rrri")
		break;
		return Intrinsic::hexagon_S2_addasl_rrri; // "exagon.S2.addas
		l.rrri"
		case 's': // 28 strings to match.
		switch (NameR[12]) {
	default: break;	default: break;

	case '.': // 8 strings to match.	case 'l': // 14 strings to match.
	switch (NameR[7]) {	if (NameR[13] != '.')
		break;
		switch (NameR[14]) {
	default: break;	default: break;

	case 'c': // 6 strings to match.	case 'i': // 7 strings to match.
	if (NameR.substr(8, 2) != "vt")	if (NameR[15] != '.')
	break;	break;

	switch (NameR[10]) {	switch (NameR[16]) {
	default: break;	default: break;

	case 'p': // 4 strings to match.	case 'p': // 3 strings to match.
	switch (NameR[11]) {	if (NameR[17] != '.')
		break;
		switch (NameR[18]) {
	default: break;	default: break;

	case 'd': // 1 string to match.	case 'a': // 2 strings to match.
	if (NameR.substr(12, 3) != "2pi")	switch (NameR[19]) {
	break;
	return Intrinsic::x86_sse_cvtpd2pi; // "86.sse.
	cvtpd2pi"
	case 'i': // 2 strings to match.
	if (NameR.substr(12, 2) != "2p")
	break;
	switch (NameR[14]) {
	default: break;	default: break;

	case 'd': // 1 string to match.	case 'c': // 1 string to match.
	return Intrinsic::x86_sse_cvtpi2pd; // "86.sse.	if (NameR[20] != 'c')
	cvtpi2pd"	break;
	case 's': // 1 string to match.	return Intrinsic::hexagon_S2_asl_i_p_acc; //
	return Intrinsic::x86_sse_cvtpi2ps; // "86.sse.	"exagon.S2.asl.i.p.acc"
	cvtpi2ps"	case 'n': // 1 string to match.
		if (NameR[20] != 'd')
		break;
		return Intrinsic::hexagon_S2_asl_i_p_and; //
		"exagon.S2.asl.i.p.and"
	}	}
	break;	break;

	case 's': // 1 string to match.	case 'n': // 1 string to match.
	if (NameR.substr(12, 3) != "2pi")	if (NameR.substr(19, 2) != "ac")
	break;	break;

	return Intrinsic::x86_sse_cvtps2pi; // "86.sse. cvtps2pi"	return Intrinsic::hexagon_S2_asl_i_p_nac; // "exagon. S2.asl.i.p.nac"
	}	}
	break;	break;

	case 's': // 2 strings to match.	case 'r': // 4 strings to match.
	switch (NameR[11]) {	if (NameR[17] != '.')
		break;
		switch (NameR[18]) {
	default: break;	default: break;

	case 'i': // 1 string to match.	case 'a': // 2 strings to match.
	if (NameR.substr(12, 3) != "2ss")	switch (NameR[19]) {
		default: break;
		case 'c': // 1 string to match.
		if (NameR[20] != 'c')
		break;
		return Intrinsic::hexagon_S2_asl_i_r_acc; //
		"exagon.S2.asl.i.r.acc"
		case 'n': // 1 string to match.
		if (NameR[20] != 'd')
		break;
		return Intrinsic::hexagon_S2_asl_i_r_and; //
		"exagon.S2.asl.i.r.and"
		}
		break;
		case 'n': // 1 string to match.
		if (NameR.substr(19, 2) != "ac")
	break;	break;

	return Intrinsic::x86_sse_cvtsi2ss; // "86.sse. cvtsi2ss"	return Intrinsic::hexagon_S2_asl_i_r_nac; // "exagon. S2.asl.i.r.nac"
	case 's': // 1 string to match.	case 's': // 1 string to match.

	if (NameR.substr(12, 3) != "2si")	if (NameR.substr(19, 2) != "at")
	break;	break;

	return Intrinsic::x86_sse_cvtss2si; // "86.sse. cvtss2si"	return Intrinsic::hexagon_S2_asl_i_r_sat; // "exagon. S2.asl.i.r.sat"
	}	}
	break;	break;
	}	}
	break;	break;

	case 'r': // 2 strings to match.	case 'r': // 7 strings to match.
	if (NameR.substr(8, 5) != "sqrt.")	if (NameR[15] != '.')
	break;	break;

	switch (NameR[13]) {	switch (NameR[16]) {
	default: break;	default: break;

	case 'p': // 1 string to match.	case 'p': // 3 strings to match.
	if (NameR[14] != 's')	if (NameR[17] != '.')
	break;	break;

	return Intrinsic::x86_sse_rsqrt_ps; // "86.sse.rsqrt.ps	switch (NameR[18]) {
	"	default: break;
	case 's': // 1 string to match.	case 'a': // 2 strings to match.
	if (NameR[14] != 's')	switch (NameR[19]) {
		default: break;
		case 'c': // 1 string to match.
		if (NameR[20] != 'c')
		break;
		return Intrinsic::hexagon_S2_asl_r_p_acc; //
		"exagon.S2.asl.r.p.acc"
		case 'n': // 1 string to match.
		if (NameR[20] != 'd')
		break;
		return Intrinsic::hexagon_S2_asl_r_p_and; //
		"exagon.S2.asl.r.p.and"
		}
	break;	break;

	return Intrinsic::x86_sse_rsqrt_ss; // "86.sse.rsqrt.ss	case 'n': // 1 string to match.
	"	if (NameR.substr(19, 2) != "ac")
		break;
		return Intrinsic::hexagon_S2_asl_r_p_nac; // "exagon.
		S2.asl.r.p.nac"
		}
		break;
		case 'r': // 4 strings to match.
		if (NameR[17] != '.')
		break;
		switch (NameR[18]) {
		default: break;
		case 'a': // 2 strings to match.
		switch (NameR[19]) {
		default: break;
		case 'c': // 1 string to match.
		if (NameR[20] != 'c')
		break;
		return Intrinsic::hexagon_S2_asl_r_r_acc; //
		"exagon.S2.asl.r.r.acc"
		case 'n': // 1 string to match.
		if (NameR[20] != 'd')
		break;
		return Intrinsic::hexagon_S2_asl_r_r_and; //
		"exagon.S2.asl.r.r.and"
		}
		break;
		case 'n': // 1 string to match.
		if (NameR.substr(19, 2) != "ac")
		break;
		return Intrinsic::hexagon_S2_asl_r_r_nac; // "exagon.
		S2.asl.r.r.nac"
		case 's': // 1 string to match.
		if (NameR.substr(19, 2) != "at")
		break;
		return Intrinsic::hexagon_S2_asl_r_r_sat; // "exagon.
		S2.asl.r.r.sat"
		}
		break;
	}	}
	break;	break;
	}	}
	break;	break;

	case '2': // 23 strings to match.	case 'r': // 14 strings to match.
	if (NameR[7] != '.')	if (NameR[13] != '.')
	break;	break;

	switch (NameR[8]) {	switch (NameR[14]) {
	default: break;	default: break;

	case 'c': // 1 string to match.	case 'i': // 7 strings to match.
	if (NameR.substr(9, 6) != "lflush")	if (NameR[15] != '.')
	break;	break;

	return Intrinsic::x86_sse2_clflush; // "86.sse2.clflush	switch (NameR[16]) {
	"
	case 'p': // 20 strings to match.
	switch (NameR[9]) {
	default: break;	default: break;

	case 'a': // 2 strings to match.	case 'p': // 3 strings to match.
	if (NameR.substr(10, 4) != "dds.")	if (NameR[17] != '.')
	break;	break;

	switch (NameR[14]) {	switch (NameR[18]) {
	default: break;
	case 'b': // 1 string to match.
	return Intrinsic::x86_sse2_padds_b; // "86.sse2
	.padds.b"
	case 'w': // 1 string to match.
	return Intrinsic::x86_sse2_padds_w; // "86.sse2
	.padds.w"
	}
	break;
	case 'm': // 5 strings to match.
	switch (NameR[10]) {
	default: break;	default: break;
	case 'a': // 2 strings to match.	case 'a': // 2 strings to match.

	if (NameR[11] != 'x')	switch (NameR[19]) {
	break;
	switch (NameR[12]) {
	default: break;	default: break;

	case 's': // 1 string to match.	case 'c': // 1 string to match.
	if (NameR.substr(13, 2) != ".w")	if (NameR[20] != 'c')
	break;	break;

	return Intrinsic::x86_sse2_pmaxs_w; // "86.sse2	return Intrinsic::hexagon_S2_asr_i_p_acc; //
	.pmaxs.w"	"exagon.S2.asr.i.p.acc"
	case 'u': // 1 string to match.	case 'n': // 1 string to match.
	if (NameR.substr(13, 2) != ".b")	if (NameR[20] != 'd')
	break;	break;

	return Intrinsic::x86_sse2_pmaxu_b; // "86.sse2 .pmaxu.b"	return Intrinsic::hexagon_S2_asr_i_p_and; // "exagon.S2.asr.i.p.and"
	}	}
	break;	break;

	case 'i': // 2 strings to match.	case 'n': // 1 string to match.
	if (NameR[11] != 'n')	if (NameR.substr(19, 2) != "ac")
	break;	break;

	switch (NameR[12]) {	return Intrinsic::hexagon_S2_asr_i_p_nac; // "exagon.
		S2.asr.i.p.nac"
		}
		break;
		case 'r': // 4 strings to match.
		if (NameR[17] != '.')
		break;
		switch (NameR[18]) {
		default: break;
		case 'a': // 2 strings to match.
		switch (NameR[19]) {
	default: break;	default: break;

	case 's': // 1 string to match.	case 'c': // 1 string to match.
	if (NameR.substr(13, 2) != ".w")	if (NameR[20] != 'c')
	break;	break;

	return Intrinsic::x86_sse2_pmins_w; // "86.sse2	return Intrinsic::hexagon_S2_asr_i_r_acc; //
	.pmins.w"	"exagon.S2.asr.i.r.acc"
	case 'u': // 1 string to match.	case 'n': // 1 string to match.
	if (NameR.substr(13, 2) != ".b")	if (NameR[20] != 'd')
	break;	break;

	return Intrinsic::x86_sse2_pminu_b; // "86.sse2 .pminu.b"	return Intrinsic::hexagon_S2_asr_i_r_and; // "exagon.S2.asr.i.r.and"
	}	}
	break;	break;

	case 'u': // 1 string to match.	case 'n': // 1 string to match.
	if (NameR.substr(11, 4) != "lh.w")	if (NameR.substr(19, 2) != "ac")
	break;	break;

	return Intrinsic::x86_sse2_pmulh_w; // "86.sse2	return Intrinsic::hexagon_S2_asr_i_r_nac; // "exagon.
	.pmulh.w"	S2.asr.i.r.nac"
		case 'r': // 1 string to match.
		if (NameR.substr(19, 2) != "nd")
		break;
		return Intrinsic::hexagon_S2_asr_i_r_rnd; // "exagon.
		S2.asr.i.r.rnd"
	}	}
	break;	break;

	case 's': // 13 strings to match.	}
	switch (NameR[10]) {	break;
		case 'r': // 7 strings to match.
		if (NameR[15] != '.')
		break;
		switch (NameR[16]) {
		default: break;
		case 'p': // 3 strings to match.
		if (NameR[17] != '.')
		break;
		switch (NameR[18]) {
	default: break;	default: break;

	case 'a': // 1 string to match.	case 'a': // 2 strings to match.
	if (NameR.substr(11, 4) != "d.bw")	switch (NameR[19]) {
	break;
	return Intrinsic::x86_sse2_psad_bw; // "86.sse2
	.psad.bw"
	case 'l': // 4 strings to match.
	if (NameR[11] != 'l')
	break;
	switch (NameR[12]) {
	default: break;	default: break;

	case '.': // 1 string to match.	case 'c': // 1 string to match.
	if (NameR.substr(13, 2) != "dq")	if (NameR[20] != 'c')
	break;	break;

	return Intrinsic::x86_sse2_psll_dq; // "86.sse2	return Intrinsic::hexagon_S2_asr_r_p_acc; //
	.psll.dq"	"exagon.S2.asr.r.p.acc"
	case 'i': // 3 strings to match.	case 'n': // 1 string to match.
	if (NameR[13] != '.')	if (NameR[20] != 'd')
	break;	break;

	switch (NameR[14]) {	return Intrinsic::hexagon_S2_asr_r_p_and; //
	default: break;	"exagon.S2.asr.r.p.and"
	case 'd': // 1 string to match.
	return Intrinsic::x86_sse2_pslli_d; // "86.sse2
	.pslli.d"
	case 'q': // 1 string to match.
	return Intrinsic::x86_sse2_pslli_q; // "86.sse2
	.pslli.q"
	case 'w': // 1 string to match.
	return Intrinsic::x86_sse2_pslli_w; // "86.sse2
	.pslli.w"
	}
	break;
	}	}
	break;	break;

	case 'r': // 6 strings to match.	case 'n': // 1 string to match.
	switch (NameR[11]) {	if (NameR.substr(19, 2) != "ac")
		break;
		return Intrinsic::hexagon_S2_asr_r_p_nac; // "exagon.
		S2.asr.r.p.nac"
		}
		break;
		case 'r': // 4 strings to match.
		if (NameR[17] != '.')
		break;
		switch (NameR[18]) {
		default: break;
		case 'a': // 2 strings to match.
		switch (NameR[19]) {
	default: break;	default: break;

	case 'a': // 2 strings to match.	case 'c': // 1 string to match.
	if (NameR.substr(12, 2) != "i.")	if (NameR[20] != 'c')
	break;	break;

	switch (NameR[14]) {	return Intrinsic::hexagon_S2_asr_r_r_acc; //
	default: break;	"exagon.S2.asr.r.r.acc"
	case 'd': // 1 string to match.	case 'n': // 1 string to match.
	return Intrinsic::x86_sse2_psrai_d; // "86.sse2	if (NameR[20] != 'd')
	.psrai.d"
	case 'w': // 1 string to match.
	return Intrinsic::x86_sse2_psrai_w; // "86.sse2
	.psrai.w"
	}
	break;
	case 'l': // 4 strings to match.
	switch (NameR[12]) {
	default: break;
	case '.': // 1 string to match.
	if (NameR.substr(13, 2) != "dq")
	break;
	return Intrinsic::x86_sse2_psrl_dq; // "86.sse2
	.psrl.dq"
	case 'i': // 3 strings to match.
	if (NameR[13] != '.')
	break;
	switch (NameR[14]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::x86_sse2_psrli_d; // "86.sse2
	.psrli.d"
	case 'q': // 1 string to match.
	return Intrinsic::x86_sse2_psrli_q; // "86.sse2
	.psrli.q"
	case 'w': // 1 string to match.
	return Intrinsic::x86_sse2_psrli_w; // "86.sse2
	.psrli.w"
	}
	break;	break;

	}	return Intrinsic::hexagon_S2_asr_r_r_and; //
	break;	"exagon.S2.asr.r.r.and"
	}	}
	break;	break;

	case 'u': // 2 strings to match.	case 'n': // 1 string to match.
	if (NameR.substr(11, 3) != "bs.")	if (NameR.substr(19, 2) != "ac")
	break;	break;

	switch (NameR[14]) {	return Intrinsic::hexagon_S2_asr_r_r_nac; // "exagon.
	default: break;	S2.asr.r.r.nac"
	case 'b': // 1 string to match.	case 's': // 1 string to match.
	return Intrinsic::x86_sse2_psubs_b; // "86.sse2	if (NameR.substr(19, 2) != "at")
	.psubs.b"	break;
	case 'w': // 1 string to match.	return Intrinsic::hexagon_S2_asr_r_r_sat; // "exagon.
	return Intrinsic::x86_sse2_psubs_w; // "86.sse2	S2.asr.r.r.sat"
	.psubs.w"
	}
	break;
	}	}
	break;	break;
	}	}
	break;	break;

	case 's': // 2 strings to match.	}
	if (NameR.substr(9, 4) != "qrt.")	break;
	break;	}
	switch (NameR[13]) {	break;
		}
		break;
		case 'e': // 1 string to match.
		if (NameR.substr(11, 10) != "xtractu.rp")
		break;
		return Intrinsic::hexagon_S2_extractu_rp; // "exagon.S2.extra
		ctu.rp"
		case 'l': // 18 strings to match.
		if (NameR[11] != 's')
		break;
		switch (NameR[12]) {
		default: break;
		case 'l': // 6 strings to match.
		if (NameR.substr(13, 3) != ".r.")
		break;
		switch (NameR[16]) {
		default: break;
		case 'p': // 3 strings to match.
		if (NameR[17] != '.')
		break;
		switch (NameR[18]) {
		default: break;
		case 'a': // 2 strings to match.
		switch (NameR[19]) {
	default: break;	default: break;

	case 'p': // 1 string to match.	case 'c': // 1 string to match.
	if (NameR[14] != 'd')	if (NameR[20] != 'c')
	break;	break;

	return Intrinsic::x86_sse2_sqrt_pd; // "86.sse2.sqrt.pd	return Intrinsic::hexagon_S2_lsl_r_p_acc; // "exagon.
	"	S2.lsl.r.p.acc"
	case 's': // 1 string to match.	case 'n': // 1 string to match.
	if (NameR[14] != 'd')	if (NameR[20] != 'd')
	break;	break;

	return Intrinsic::x86_sse2_sqrt_sd; // "86.sse2.sqrt.sd "	return Intrinsic::hexagon_S2_lsl_r_p_and; // "exagon. S2.lsl.r.p.and"
	}	}
	break;	break;

		case 'n': // 1 string to match.
		if (NameR.substr(19, 2) != "ac")
		break;
		return Intrinsic::hexagon_S2_lsl_r_p_nac; // "exagon.
		S2.lsl.r.p.nac"
	}	}
	break;	break;

	case '3': // 5 strings to match.	case 'r': // 3 strings to match.
	if (NameR[7] != '.')	if (NameR[17] != '.')
	break;	break;

	switch (NameR[8]) {	switch (NameR[18]) {
	default: break;	default: break;

	case 'h': // 4 strings to match.	case 'a': // 2 strings to match.
	switch (NameR[9]) {	switch (NameR[19]) {
	default: break;	default: break;

	case 'a': // 2 strings to match.	case 'c': // 1 string to match.
	if (NameR.substr(10, 4) != "dd.p")	if (NameR[20] != 'c')
	break;	break;

	switch (NameR[14]) {	return Intrinsic::hexagon_S2_lsl_r_r_acc; // "exagon.
	default: break;	S2.lsl.r.r.acc"
	case 'd': // 1 string to match.	case 'n': // 1 string to match.
	return Intrinsic::x86_sse3_hadd_pd; // "86.sse3	if (NameR[20] != 'd')
	.hadd.pd"
	case 's': // 1 string to match.
	return Intrinsic::x86_sse3_hadd_ps; // "86.sse3
	.hadd.ps"
	}
	break;
	case 's': // 2 strings to match.
	if (NameR.substr(10, 4) != "ub.p")
	break;	break;

	switch (NameR[14]) {	return Intrinsic::hexagon_S2_lsl_r_r_and; // "exagon.
	default: break;	S2.lsl.r.r.and"
	case 'd': // 1 string to match.
	return Intrinsic::x86_sse3_hsub_pd; // "86.sse3
	.hsub.pd"
	case 's': // 1 string to match.
	return Intrinsic::x86_sse3_hsub_ps; // "86.sse3
	.hsub.ps"
	}
	break;
	}	}
	break;	break;

	case 'm': // 1 string to match.	case 'n': // 1 string to match.
	if (NameR.substr(9, 6) != "onitor")	if (NameR.substr(19, 2) != "ac")
	break;	break;

	return Intrinsic::x86_sse3_monitor; // "86.sse3.monitor "	return Intrinsic::hexagon_S2_lsl_r_r_nac; // "exagon. S2.lsl.r.r.nac"
	}	}
	break;	break;

	case '4': // 14 strings to match.	}
	if (NameR.substr(7, 3) != "1.p")	break;
		case 'r': // 12 strings to match.
		if (NameR[13] != '.')
		break;
		switch (NameR[14]) {
		default: break;
		case 'i': // 6 strings to match.
		if (NameR[15] != '.')
	break;	break;

	switch (NameR[10]) {	switch (NameR[16]) {
	default: break;	default: break;

	case 'e': // 3 strings to match.	case 'p': // 3 strings to match.
	if (NameR.substr(11, 3) != "xtr")	if (NameR[17] != '.')
	break;	break;

	switch (NameR[14]) {	switch (NameR[18]) {
	default: break;	default: break;

	case 'b': // 1 string to match.	case 'a': // 2 strings to match.
	return Intrinsic::x86_sse41_pextrb; // "86.sse41.pextrb	switch (NameR[19]) {
	"	default: break;
	case 'd': // 1 string to match.	case 'c': // 1 string to match.
	return Intrinsic::x86_sse41_pextrd; // "86.sse41.pextrd	if (NameR[20] != 'c')
	"	break;
	case 'q': // 1 string to match.	return Intrinsic::hexagon_S2_lsr_i_p_acc; // "exagon.
	return Intrinsic::x86_sse41_pextrq; // "86.sse41.pextrq	S2.lsr.i.p.acc"
	"	case 'n': // 1 string to match.
		if (NameR[20] != 'd')
		break;
		return Intrinsic::hexagon_S2_lsr_i_p_and; // "exagon.
		S2.lsr.i.p.and"
		}
		break;
		case 'n': // 1 string to match.
		if (NameR.substr(19, 2) != "ac")
		break;
		return Intrinsic::hexagon_S2_lsr_i_p_nac; // "exagon.
		S2.lsr.i.p.nac"
	}	}
	break;	break;

	case 'm': // 9 strings to match.	case 'r': // 3 strings to match.
	switch (NameR[11]) {	if (NameR[17] != '.')
		break;
		switch (NameR[18]) {
	default: break;	default: break;

	case 'a': // 4 strings to match.	case 'a': // 2 strings to match.
	if (NameR[12] != 'x')	switch (NameR[19]) {
	break;
	switch (NameR[13]) {
	default: break;	default: break;

	case 's': // 2 strings to match.	case 'c': // 1 string to match.
	switch (NameR[14]) {	if (NameR[20] != 'c')
	default: break;	break;
	case 'b': // 1 string to match.	return Intrinsic::hexagon_S2_lsr_i_r_acc; // "exagon.
	return Intrinsic::x86_sse41_pmaxsb; // "86.sse4	S2.lsr.i.r.acc"
	1.pmaxsb"	case 'n': // 1 string to match.
	case 'd': // 1 string to match.	if (NameR[20] != 'd')
	return Intrinsic::x86_sse41_pmaxsd; // "86.sse4	break;
	1.pmaxsd"	return Intrinsic::hexagon_S2_lsr_i_r_and; // "exagon.
	}	S2.lsr.i.r.and"
	break;
	case 'u': // 2 strings to match.
	switch (NameR[14]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::x86_sse41_pmaxud; // "86.sse4
	1.pmaxud"
	case 'w': // 1 string to match.
	return Intrinsic::x86_sse41_pmaxuw; // "86.sse4
	1.pmaxuw"
	}
	break;
	}	}
	break;	break;

	case 'i': // 4 strings to match.	case 'n': // 1 string to match.
	if (NameR[12] != 'n')	if (NameR.substr(19, 2) != "ac")
	break;	break;

	switch (NameR[13]) {	return Intrinsic::hexagon_S2_lsr_i_r_nac; // "exagon.
		S2.lsr.i.r.nac"
		}
		break;
		}
		break;
		case 'r': // 6 strings to match.
		if (NameR[15] != '.')
		break;
		switch (NameR[16]) {
		default: break;
		case 'p': // 3 strings to match.
		if (NameR[17] != '.')
		break;
		switch (NameR[18]) {
		default: break;
		case 'a': // 2 strings to match.
		switch (NameR[19]) {
	default: break;	default: break;

	case 's': // 2 strings to match.	case 'c': // 1 string to match.
	switch (NameR[14]) {	if (NameR[20] != 'c')
	default: break;	break;
	case 'b': // 1 string to match.	return Intrinsic::hexagon_S2_lsr_r_p_acc; // "exagon.
	return Intrinsic::x86_sse41_pminsb; // "86.sse4	S2.lsr.r.p.acc"
	1.pminsb"	case 'n': // 1 string to match.
	case 'd': // 1 string to match.	if (NameR[20] != 'd')
	return Intrinsic::x86_sse41_pminsd; // "86.sse4	break;
	1.pminsd"	return Intrinsic::hexagon_S2_lsr_r_p_and; // "exagon.
	}	S2.lsr.r.p.and"
	break;
	case 'u': // 2 strings to match.
	switch (NameR[14]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::x86_sse41_pminud; // "86.sse4
	1.pminud"
	case 'w': // 1 string to match.
	return Intrinsic::x86_sse41_pminuw; // "86.sse4
	1.pminuw"
	}
	break;
	}	}
	break;	break;

	case 'u': // 1 string to match.	case 'n': // 1 string to match.
	if (NameR.substr(12, 3) != "ldq")	if (NameR.substr(19, 2) != "ac")
	break;	break;

	return Intrinsic::x86_sse41_pmuldq; // "86.sse41.pmuldq "	return Intrinsic::hexagon_S2_lsr_r_p_nac; // "exagon. S2.lsr.r.p.nac"
	}	}
	break;	break;

	case 't': // 2 strings to match.	case 'r': // 3 strings to match.
	if (NameR.substr(11, 3) != "est")	if (NameR[17] != '.')
	break;	break;

	switch (NameR[14]) {	switch (NameR[18]) {
	default: break;	default: break;

	case 'c': // 1 string to match.	case 'a': // 2 strings to match.
	return Intrinsic::x86_sse41_ptestc; // "86.sse41.ptestc	switch (NameR[19]) {
	"	default: break;
	case 'z': // 1 string to match.	case 'c': // 1 string to match.
	return Intrinsic::x86_sse41_ptestz; // "86.sse41.ptestz	if (NameR[20] != 'c')
	"	break;
		return Intrinsic::hexagon_S2_lsr_r_r_acc; // "exagon.
		S2.lsr.r.r.acc"
		case 'n': // 1 string to match.
		if (NameR[20] != 'd')
		break;
		return Intrinsic::hexagon_S2_lsr_r_r_and; // "exagon.
		S2.lsr.r.r.and"
		}
		break;
		case 'n': // 1 string to match.
		if (NameR.substr(19, 2) != "ac")
		break;
		return Intrinsic::hexagon_S2_lsr_r_r_nac; // "exagon.
		S2.lsr.r.r.nac"
	}	}
	break;	break;
	}	}
	break;	break;
	}	}
	break;	break;

	case 's': // 3 strings to match.	}
	if (NameR.substr(6, 8) != "e3.pabs.")	break;
	break;	case 't': // 2 strings to match.
	switch (NameR[14]) {	if (NameR.substr(11, 9) != "ogglebit.")
	default: break;
	case 'b': // 1 string to match.
	return Intrinsic::x86_ssse3_pabs_b; // "86.ssse3.pabs.b
	"
	case 'd': // 1 string to match.
	return Intrinsic::x86_ssse3_pabs_d; // "86.ssse3.pabs.d
	"
	case 'w': // 1 string to match.
	return Intrinsic::x86_ssse3_pabs_w; // "86.ssse3.pabs.w
	"
	}
	break;	break;

		switch (NameR[20]) {
		default: break;
		case 'i': // 1 string to match.
		return Intrinsic::hexagon_S2_togglebit_i; // "exagon.S2.toggl
		ebit.i"
		case 'r': // 1 string to match.
		return Intrinsic::hexagon_S2_togglebit_r; // "exagon.S2.toggl
		ebit.r"
	}	}
	break;	break;

		case 'v': // 1 string to match.
		if (NameR.substr(11, 10) != "rndpackwhs")
		break;
		return Intrinsic::hexagon_S2_vrndpackwhs; // "exagon.S2.vrndp
		ackwhs"
	}	}
	break;	break;

	case 'c': // 1 string to match.
	if (NameR.substr(1, 14) != "ore.checkevent")
	break;
	return Intrinsic::xcore_checkevent; // "core.checkevent"
	}	}
	break;	break;

	case 16: // 67 strings to match.	case 22: // 9 strings to match.
	if (NameR.substr(0, 3) != "86.")	if (NameR.substr(0, 7) != "exagon.")
	break;	break;

	switch (NameR[3]) {	switch (NameR[7]) {
	default: break;	default: break;

	case '3': // 8 strings to match.	case 'A': // 2 strings to match.
	if (NameR.substr(4, 4) != "dnow")	if (NameR.substr(8, 9) != "4.round.r")
	break;	break;

	switch (NameR[8]) {	switch (NameR[17]) {
	default: break;	default: break;

	case '.': // 6 strings to match.	case 'i': // 1 string to match.
	if (NameR[9] != 'p')	if (NameR.substr(18, 4) != ".sat")
	break;	break;

	switch (NameR[10]) {	return Intrinsic::hexagon_A4_round_ri_sat; // "exagon.A4.round
		.ri.sat"
		case 'r': // 1 string to match.
		if (NameR.substr(18, 4) != ".sat")
		break;
		return Intrinsic::hexagon_A4_round_rr_sat; // "exagon.A4.round
		.rr.sat"
		}
		break;
		case 'M': // 1 string to match.
		if (NameR.substr(8, 14) != "2.vrcmpys.s1rp")
		break;
		return Intrinsic::hexagon_M2_vrcmpys_s1rp; // "exagon.M2.vrcmp
		ys.s1rp"
		case 'S': // 6 strings to match.
		if (NameR.substr(8, 2) != "2.")
		break;
		switch (NameR[10]) {
		default: break;
		case 'a': // 2 strings to match.
		if (NameR.substr(11, 5) != "sl.i.")
		break;
		switch (NameR[16]) {
	default: break;	default: break;

	case 'a': // 1 string to match.	case 'p': // 1 string to match.
	if (NameR.substr(11, 5) != "vgusb")	if (NameR.substr(17, 5) != ".xacc")
	break;	break;

	return Intrinsic::x86_3dnow_pavgusb; // "86.3dnow.pavgus	return Intrinsic::hexagon_S2_asl_i_p_xacc; // "exagon.S2.asl.i
	b"	.p.xacc"
	case 'f': // 4 strings to match.	case 'r': // 1 string to match.
	switch (NameR[11]) {	if (NameR.substr(17, 5) != ".xacc")
	default: break;
	case 'c': // 3 strings to match.
	if (NameR.substr(12, 2) != "mp")
	break;
	switch (NameR[14]) {
	default: break;
	case 'e': // 1 string to match.
	if (NameR[15] != 'q')
	break;
	return Intrinsic::x86_3dnow_pfcmpeq; // "86.3dnow.pfcmpe
	q"
	case 'g': // 2 strings to match.
	switch (NameR[15]) {
	default: break;
	case 'e': // 1 string to match.
	return Intrinsic::x86_3dnow_pfcmpge; // "86.3dnow.pfcmpg
	e"
	case 't': // 1 string to match.
	return Intrinsic::x86_3dnow_pfcmpgt; // "86.3dnow.pfcmpg
	t"
	}
	break;
	}
	break;	break;

	case 'r': // 1 string to match.	return Intrinsic::hexagon_S2_asl_i_r_xacc; // "exagon.S2.asl.i
	if (NameR.substr(12, 4) != "sqrt")	.r.xacc"
	break;
	return Intrinsic::x86_3dnow_pfrsqrt; // "86.3dnow.pfrsqr
	t"
	}
	break;
	case 'm': // 1 string to match.
	if (NameR.substr(11, 5) != "ulhrw")
	break;
	return Intrinsic::x86_3dnow_pmulhrw; // "86.3dnow.pmulhr
	w"
	}
	break;
	case 'a': // 2 strings to match.
	if (NameR.substr(9, 2) != ".p")
	break;
	switch (NameR[11]) {
	default: break;
	case 'f': // 1 string to match.
	if (NameR.substr(12, 4) != "nacc")
	break;
	return Intrinsic::x86_3dnowa_pfnacc; // "86.3dnowa.pfnac
	c"
	case 's': // 1 string to match.
	if (NameR.substr(12, 4) != "wapd")
	break;
	return Intrinsic::x86_3dnowa_pswapd; // "86.3dnowa.pswap
	d"
	}	}
	break;	break;

	}
	break;
	case 'a': // 5 strings to match.
	if (NameR.substr(4, 3) != "vx.")
	break;
	switch (NameR[7]) {
	default: break;
	case 'd': // 1 string to match.	case 'd': // 1 string to match.

	if (NameR.substr(8, 8) != "p.ps.256")	if (NameR.substr(11, 11) != "einterleave")
	break;	break;

	return Intrinsic::x86_avx_dp_ps_256; // "86.avx.dp.ps.256"	return Intrinsic::hexagon_S2_deinterleave; // "exagon.S2.deint
	case 'v': // 4 strings to match.	erleave"
	if (NameR.substr(8, 4) != "test")	case 'e': // 1 string to match.
		if (NameR.substr(11, 11) != "xtractup.rp")
	break;	break;

	switch (NameR[12]) {	return Intrinsic::hexagon_S2_extractup_rp; // "exagon.S2.extra
		ctup.rp"
		case 'l': // 2 strings to match.
		if (NameR.substr(11, 5) != "sr.i.")
		break;
		switch (NameR[16]) {
	default: break;	default: break;

	case 'c': // 2 strings to match.	case 'p': // 1 string to match.
	if (NameR.substr(13, 2) != ".p")	if (NameR.substr(17, 5) != ".xacc")
	break;	break;

	switch (NameR[15]) {	return Intrinsic::hexagon_S2_lsr_i_p_xacc; // "exagon.S2.lsr.i
	default: break;	.p.xacc"
	case 'd': // 1 string to match.	case 'r': // 1 string to match.
	return Intrinsic::x86_avx_vtestc_pd; // "86.avx.vtestc.p	if (NameR.substr(17, 5) != ".xacc")
	d"
	case 's': // 1 string to match.
	return Intrinsic::x86_avx_vtestc_ps; // "86.avx.vtestc.p
	s"
	}
	break;
	case 'z': // 2 strings to match.
	if (NameR.substr(13, 2) != ".p")
	break;	break;

	switch (NameR[15]) {	return Intrinsic::hexagon_S2_lsr_i_r_xacc; // "exagon.S2.lsr.i
	default: break;	.r.xacc"
	case 'd': // 1 string to match.
	return Intrinsic::x86_avx_vtestz_pd; // "86.avx.vtestz.p
	d"
	case 's': // 1 string to match.
	return Intrinsic::x86_avx_vtestz_ps; // "86.avx.vtestz.p
	s"
	}
	break;
	}	}
	break;	break;
	}	}
	break;	break;

	case 'm': // 7 strings to match.	}
	if (NameR.substr(4, 4) != "mx.p")	break;
		case 23: // 37 strings to match.
		if (NameR.substr(0, 7) != "exagon.")
		break;
		switch (NameR[7]) {
		default: break;
		case 'M': // 34 strings to match.
		if (NameR.substr(8, 2) != "2.")
	break;	break;

	switch (NameR[8]) {	switch (NameR[10]) {
	default: break;	default: break;

	case 'a': // 1 string to match.	case 'm': // 32 strings to match.
	if (NameR.substr(9, 7) != "lignr.b")	if (NameR.substr(11, 3) != "py.")
	break;
	return Intrinsic::x86_mmx_palignr_b; // "86.mmx.palignr.b"
	case 'u': // 6 strings to match.
	if (NameR.substr(9, 4) != "npck")
	break;	break;

	switch (NameR[13]) {	switch (NameR[14]) {
	default: break;	default: break;

	case 'h': // 3 strings to match.	case 'a': // 8 strings to match.
	switch (NameR[14]) {	if (NameR.substr(15, 3) != "cc.")
		break;
		switch (NameR[18]) {
	default: break;	default: break;

	case 'b': // 1 string to match.	case 'h': // 4 strings to match.
	if (NameR[15] != 'w')	switch (NameR[19]) {
		default: break;
		case 'h': // 2 strings to match.
		if (NameR.substr(20, 2) != ".s")
		break;
		switch (NameR[22]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_acc_hh_s0; // "exagon.
		M2.mpy.acc.hh.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_acc_hh_s1; // "exagon.
		M2.mpy.acc.hh.s1"
		}
	break;	break;

	return Intrinsic::x86_mmx_punpckhbw; // "86.mmx.punpckhb	case 'l': // 2 strings to match.
	w"	if (NameR.substr(20, 2) != ".s")
	case 'd': // 1 string to match.	break;
	if (NameR[15] != 'q')	switch (NameR[22]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_acc_hl_s0; // "exagon.
		M2.mpy.acc.hl.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_acc_hl_s1; // "exagon.
		M2.mpy.acc.hl.s1"
		}
	break;	break;

	return Intrinsic::x86_mmx_punpckhdq; // "86.mmx.punpckhd	}
	q"	break;
	case 'w': // 1 string to match.	case 'l': // 4 strings to match.
	if (NameR[15] != 'd')	switch (NameR[19]) {
		default: break;
		case 'h': // 2 strings to match.
		if (NameR.substr(20, 2) != ".s")
		break;
		switch (NameR[22]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_acc_lh_s0; // "exagon.
		M2.mpy.acc.lh.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_acc_lh_s1; // "exagon.
		M2.mpy.acc.lh.s1"
		}
	break;	break;

	return Intrinsic::x86_mmx_punpckhwd; // "86.mmx.punpckhw	case 'l': // 2 strings to match.
	d"	if (NameR.substr(20, 2) != ".s")
		break;
		switch (NameR[22]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_acc_ll_s0; // "exagon.
		M2.mpy.acc.ll.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_acc_ll_s1; // "exagon.
		M2.mpy.acc.ll.s1"
		}
		break;
		}
		break;
	}	}
	break;	break;

	case 'l': // 3 strings to match.	case 'n': // 8 strings to match.
	switch (NameR[14]) {	if (NameR.substr(15, 3) != "ac.")
		break;
		switch (NameR[18]) {
	default: break;	default: break;

	case 'b': // 1 string to match.	case 'h': // 4 strings to match.
	if (NameR[15] != 'w')	switch (NameR[19]) {
		default: break;
		case 'h': // 2 strings to match.
		if (NameR.substr(20, 2) != ".s")
		break;
		switch (NameR[22]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_nac_hh_s0; // "exagon.
		M2.mpy.nac.hh.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_nac_hh_s1; // "exagon.
		M2.mpy.nac.hh.s1"
		}
	break;	break;

	return Intrinsic::x86_mmx_punpcklbw; // "86.mmx.punpcklb	case 'l': // 2 strings to match.
	w"	if (NameR.substr(20, 2) != ".s")
	case 'd': // 1 string to match.	break;
	if (NameR[15] != 'q')	switch (NameR[22]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_nac_hl_s0; // "exagon.
		M2.mpy.nac.hl.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_nac_hl_s1; // "exagon.
		M2.mpy.nac.hl.s1"
		}
	break;	break;

	return Intrinsic::x86_mmx_punpckldq; // "86.mmx.punpckld	}
	q"	break;
	case 'w': // 1 string to match.	case 'l': // 4 strings to match.
	if (NameR[15] != 'd')	switch (NameR[19]) {
		default: break;
		case 'h': // 2 strings to match.
		if (NameR.substr(20, 2) != ".s")
		break;
		switch (NameR[22]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_nac_lh_s0; // "exagon.
		M2.mpy.nac.lh.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_nac_lh_s1; // "exagon.
		M2.mpy.nac.lh.s1"
		}
	break;	break;

	return Intrinsic::x86_mmx_punpcklwd; // "86.mmx.punpcklw	case 'l': // 2 strings to match.
	d"	if (NameR.substr(20, 2) != ".s")
		break;
		switch (NameR[22]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_nac_ll_s0; // "exagon.
		M2.mpy.nac.ll.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_nac_ll_s1; // "exagon.
		M2.mpy.nac.ll.s1"
		}
		break;
		}
		break;
	}	}
	break;	break;

	}	case 'r': // 8 strings to match.
	break;	if (NameR.substr(15, 3) != "nd.")
	}	break;
	break;	switch (NameR[18]) {
	case 's': // 47 strings to match.
	if (NameR[4] != 's')
	break;
	switch (NameR[5]) {
	default: break;
	case 'e': // 39 strings to match.
	switch (NameR[6]) {
	default: break;
	case '.': // 10 strings to match.
	switch (NameR[7]) {
	default: break;	default: break;

	case 'c': // 8 strings to match.	case 'h': // 4 strings to match.
	switch (NameR[8]) {	switch (NameR[19]) {
	default: break;	default: break;

	case 'o': // 5 strings to match.	case 'h': // 2 strings to match.
	if (NameR.substr(9, 2) != "mi")	if (NameR.substr(20, 2) != ".s")
	break;	break;

	switch (NameR[11]) {	switch (NameR[22]) {
	default: break;	default: break;

	case 'e': // 1 string to match.	case '0': // 1 string to match.
	if (NameR.substr(12, 4) != "q.ss")	return Intrinsic::hexagon_M2_mpy_rnd_hh_s0; // "exagon.
	break;	M2.mpy.rnd.hh.s0"
	return Intrinsic::x86_sse_comieq_ss; // "86.sse.comieq.s	case '1': // 1 string to match.
	s"	return Intrinsic::hexagon_M2_mpy_rnd_hh_s1; // "exagon.
	case 'g': // 2 strings to match.	M2.mpy.rnd.hh.s1"
	switch (NameR[12]) {
	default: break;
	case 'e': // 1 string to match.
	if (NameR.substr(13, 3) != ".ss")
	break;
	return Intrinsic::x86_sse_comige_ss; // "86.sse.
	comige.ss"
	case 't': // 1 string to match.
	if (NameR.substr(13, 3) != ".ss")
	break;
	return Intrinsic::x86_sse_comigt_ss; // "86.sse.
	comigt.ss"
	}
	break;
	case 'l': // 2 strings to match.
	switch (NameR[12]) {
	default: break;
	case 'e': // 1 string to match.
	if (NameR.substr(13, 3) != ".ss")
	break;
	return Intrinsic::x86_sse_comile_ss; // "86.sse.
	comile.ss"
	case 't': // 1 string to match.
	if (NameR.substr(13, 3) != ".ss")
	break;
	return Intrinsic::x86_sse_comilt_ss; // "86.sse.
	comilt.ss"
	}
	break;
	}	}
	break;	break;

	case 'v': // 3 strings to match.	case 'l': // 2 strings to match.
	if (NameR.substr(9, 2) != "tt")	if (NameR.substr(20, 2) != ".s")
	break;	break;

	switch (NameR[11]) {	switch (NameR[22]) {
	default: break;	default: break;

	case 'p': // 2 strings to match.	case '0': // 1 string to match.
	switch (NameR[12]) {	return Intrinsic::hexagon_M2_mpy_rnd_hl_s0; // "exagon.
	default: break;	M2.mpy.rnd.hl.s0"
	case 'd': // 1 string to match.	case '1': // 1 string to match.
	if (NameR.substr(13, 3) != "2pi")	return Intrinsic::hexagon_M2_mpy_rnd_hl_s1; // "exagon.
	break;	M2.mpy.rnd.hl.s1"
	return Intrinsic::x86_sse_cvttpd2pi; // "86.sse.
	cvttpd2pi"
	case 's': // 1 string to match.
	if (NameR.substr(13, 3) != "2pi")
	break;
	return Intrinsic::x86_sse_cvttps2pi; // "86.sse.
	cvttps2pi"
	}
	break;
	case 's': // 1 string to match.
	if (NameR.substr(12, 4) != "s2si")
	break;
	return Intrinsic::x86_sse_cvttss2si; // "86.sse.cvttss2s
	i"
	}	}
	break;	break;
	}	}
	break;	break;

	case 'm': // 1 string to match.	case 'l': // 4 strings to match.
	if (NameR.substr(8, 8) != "ovmsk.ps")	switch (NameR[19]) {
		default: break;
		case 'h': // 2 strings to match.
		if (NameR.substr(20, 2) != ".s")
		break;
		switch (NameR[22]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_rnd_lh_s0; // "exagon.
		M2.mpy.rnd.lh.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_rnd_lh_s1; // "exagon.
		M2.mpy.rnd.lh.s1"
		}
	break;	break;

	return Intrinsic::x86_sse_movmsk_ps; // "86.sse.movmsk.p	case 'l': // 2 strings to match.
	s"	if (NameR.substr(20, 2) != ".s")
	case 's': // 1 string to match.	break;
	if (NameR.substr(8, 8) != "toreu.ps")	switch (NameR[22]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_rnd_ll_s0; // "exagon.
		M2.mpy.rnd.ll.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_rnd_ll_s1; // "exagon.
		M2.mpy.rnd.ll.s1"
		}
	break;	break;

	return Intrinsic::x86_sse_storeu_ps; // "86.sse.storeu.p	}
	s"	break;
	}	}
	break;	break;

	case '2': // 23 strings to match.	case 's': // 8 strings to match.
	if (NameR[7] != '.')	if (NameR.substr(15, 3) != "at.")
	break;	break;

	switch (NameR[8]) {	switch (NameR[18]) {
	default: break;	default: break;

	case 'c': // 10 strings to match.	case 'h': // 4 strings to match.
	if (NameR.substr(9, 2) != "vt")	switch (NameR[19]) {
	break;
	switch (NameR[11]) {
	default: break;	default: break;

	case 'd': // 2 strings to match.	case 'h': // 2 strings to match.
	if (NameR.substr(12, 3) != "q2p")	if (NameR.substr(20, 2) != ".s")
	break;	break;

	switch (NameR[15]) {	switch (NameR[22]) {
	default: break;	default: break;

	case 'd': // 1 string to match.	case '0': // 1 string to match.
	return Intrinsic::x86_sse2_cvtdq2pd; // "86.sse2.cvtdq2p	return Intrinsic::hexagon_M2_mpy_sat_hh_s0; // "exagon.
	d"	M2.mpy.sat.hh.s0"
	case 's': // 1 string to match.	case '1': // 1 string to match.
	return Intrinsic::x86_sse2_cvtdq2ps; // "86.sse2.cvtdq2p	return Intrinsic::hexagon_M2_mpy_sat_hh_s1; // "exagon.
	s"	M2.mpy.sat.hh.s1"
	}	}
	break;	break;

	case 'p': // 4 strings to match.	case 'l': // 2 strings to match.
	switch (NameR[12]) {	if (NameR.substr(20, 2) != ".s")
		break;
		switch (NameR[22]) {
	default: break;	default: break;

	case 'd': // 2 strings to match.	case '0': // 1 string to match.
	if (NameR[13] != '2')	return Intrinsic::hexagon_M2_mpy_sat_hl_s0; // "exagon.
		M2.mpy.sat.hl.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_sat_hl_s1; // "exagon.
		M2.mpy.sat.hl.s1"
		}
		break;
		}
		break;
		case 'l': // 4 strings to match.
		switch (NameR[19]) {
		default: break;
		case 'h': // 2 strings to match.
		if (NameR.substr(20, 2) != ".s")
		break;
		switch (NameR[22]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_sat_lh_s0; // "exagon.
		M2.mpy.sat.lh.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_sat_lh_s1; // "exagon.
		M2.mpy.sat.lh.s1"
		}
		break;
		case 'l': // 2 strings to match.
		if (NameR.substr(20, 2) != ".s")
		break;
		switch (NameR[22]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_sat_ll_s0; // "exagon.
		M2.mpy.sat.ll.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_sat_ll_s1; // "exagon.
		M2.mpy.sat.ll.s1"
		}
		break;
		}
		break;
		}
		break;
		}
		break;
		case 'v': // 2 strings to match.
		if (NameR.substr(11, 7) != "mpy2s.s")
		break;
		switch (NameR[18]) {
		default: break;
		case '0': // 1 string to match.
		if (NameR.substr(19, 4) != "pack")
		break;
		return Intrinsic::hexagon_M2_vmpy2s_s0pack; // "exagon.
		M2.vmpy2s.s0pack"
		case '1': // 1 string to match.
		if (NameR.substr(19, 4) != "pack")
		break;
		return Intrinsic::hexagon_M2_vmpy2s_s1pack; // "exagon.
		M2.vmpy2s.s1pack"
		}
		break;
		}
		break;
		case 'S': // 3 strings to match.
		switch (NameR[8]) {
		default: break;
		case '2': // 2 strings to match.
		if (NameR.substr(9, 5) != ".vsat")
		break;
		switch (NameR[14]) {
		default: break;
		case 'h': // 1 string to match.
		if (NameR.substr(15, 8) != "b.nopack")
		break;
		return Intrinsic::hexagon_S2_vsathb_nopack; // "exagon.
		S2.vsathb.nopack"
		case 'w': // 1 string to match.
		if (NameR.substr(15, 8) != "h.nopack")
		break;
		return Intrinsic::hexagon_S2_vsatwh_nopack; // "exagon.
		S2.vsatwh.nopack"
		}
		break;
		case 'I': // 1 string to match.
		if (NameR.substr(9, 14) != ".to.SXTHI.asrh")
		break;
		return Intrinsic::hexagon_SI_to_SXTHI_asrh; // "exagon.SI.to.SX
		THI.asrh"
		}
		break;
		}
		break;
		case 24: // 56 strings to match.
		if (NameR.substr(0, 7) != "exagon.")
		break;
		switch (NameR[7]) {
		default: break;
		case 'M': // 52 strings to match.
		if (NameR.substr(8, 2) != "2.")
		break;
		switch (NameR[10]) {
		default: break;
		case 'd': // 5 strings to match.
		if (NameR.substr(11, 4) != "pmpy")
		break;
		switch (NameR[15]) {
		default: break;
		case 's': // 3 strings to match.
		if (NameR.substr(16, 2) != "s.")
		break;
		switch (NameR[18]) {
		default: break;
		case 'a': // 1 string to match.
		if (NameR.substr(19, 5) != "cc.s0")
		break;
		return Intrinsic::hexagon_M2_dpmpyss_acc_s0; // "exagon.
		M2.dpmpyss.acc.s0"
		case 'n': // 1 string to match.
		if (NameR.substr(19, 5) != "ac.s0")
		break;
		return Intrinsic::hexagon_M2_dpmpyss_nac_s0; // "exagon.
		M2.dpmpyss.nac.s0"
		case 'r': // 1 string to match.
		if (NameR.substr(19, 5) != "nd.s0")
		break;
		return Intrinsic::hexagon_M2_dpmpyss_rnd_s0; // "exagon.
		M2.dpmpyss.rnd.s0"
		}
		break;
		case 'u': // 2 strings to match.
		if (NameR.substr(16, 2) != "u.")
		break;
		switch (NameR[18]) {
		default: break;
		case 'a': // 1 string to match.
		if (NameR.substr(19, 5) != "cc.s0")
		break;
		return Intrinsic::hexagon_M2_dpmpyuu_acc_s0; // "exagon.
		M2.dpmpyuu.acc.s0"
		case 'n': // 1 string to match.
		if (NameR.substr(19, 5) != "ac.s0")
		break;
		return Intrinsic::hexagon_M2_dpmpyuu_nac_s0; // "exagon.
		M2.dpmpyuu.nac.s0"
		}
		break;
		}
		break;
		case 'm': // 40 strings to match.
		if (NameR.substr(11, 2) != "py")
		break;
		switch (NameR[13]) {
		default: break;
		case 'd': // 24 strings to match.
		if (NameR[14] != '.')
		break;
		switch (NameR[15]) {
		default: break;
		case 'a': // 8 strings to match.
		if (NameR.substr(16, 3) != "cc.")
		break;
		switch (NameR[19]) {
		default: break;
		case 'h': // 4 strings to match.
		switch (NameR[20]) {
		default: break;
		case 'h': // 2 strings to match.
		if (NameR.substr(21, 2) != ".s")
	break;	break;

	switch (NameR[14]) {	switch (NameR[23]) {
	default: break;	default: break;

	case 'd': // 1 string to match.	case '0': // 1 string to match.
	if (NameR[15] != 'q')	return Intrinsic::hexagon_M2_mpyd_acc_hh_s0; //
	break;	"exagon.M2.mpyd.acc.hh.s0"
	return Intrinsic::x86_sse2_cvtpd2dq; // "86.sse2	case '1': // 1 string to match.
	.cvtpd2dq"	return Intrinsic::hexagon_M2_mpyd_acc_hh_s1; //
	case 'p': // 1 string to match.	"exagon.M2.mpyd.acc.hh.s1"
	if (NameR[15] != 's')
	break;
	return Intrinsic::x86_sse2_cvtpd2ps; // "86.sse2
	.cvtpd2ps"
	}	}
	break;	break;

	case 's': // 2 strings to match.	case 'l': // 2 strings to match.
	if (NameR[13] != '2')	if (NameR.substr(21, 2) != ".s")
	break;	break;

	switch (NameR[14]) {	switch (NameR[23]) {
	default: break;	default: break;

	case 'd': // 1 string to match.	case '0': // 1 string to match.
	if (NameR[15] != 'q')	return Intrinsic::hexagon_M2_mpyd_acc_hl_s0; //
	break;	"exagon.M2.mpyd.acc.hl.s0"
	return Intrinsic::x86_sse2_cvtps2dq; // "86.sse2	case '1': // 1 string to match.
	.cvtps2dq"	return Intrinsic::hexagon_M2_mpyd_acc_hl_s1; //
	case 'p': // 1 string to match.	"exagon.M2.mpyd.acc.hl.s1"
	if (NameR[15] != 'd')
	break;
	return Intrinsic::x86_sse2_cvtps2pd; // "86.sse2
	.cvtps2pd"
	}	}
	break;	break;
	}	}
	break;	break;

	case 's': // 4 strings to match.	case 'l': // 4 strings to match.
	switch (NameR[12]) {	switch (NameR[20]) {
	default: break;	default: break;

	case 'd': // 2 strings to match.	case 'h': // 2 strings to match.
	if (NameR.substr(13, 2) != "2s")	if (NameR.substr(21, 2) != ".s")
	break;	break;

	switch (NameR[15]) {	switch (NameR[23]) {
	default: break;	default: break;

	case 'i': // 1 string to match.	case '0': // 1 string to match.
	return Intrinsic::x86_sse2_cvtsd2si; // "86.sse2	return Intrinsic::hexagon_M2_mpyd_acc_lh_s0; //
	.cvtsd2si"	"exagon.M2.mpyd.acc.lh.s0"
	case 's': // 1 string to match.	case '1': // 1 string to match.
	return Intrinsic::x86_sse2_cvtsd2ss; // "86.sse2	return Intrinsic::hexagon_M2_mpyd_acc_lh_s1; //
	.cvtsd2ss"	"exagon.M2.mpyd.acc.lh.s1"
	}	}
	break;	break;

	case 'i': // 1 string to match.	case 'l': // 2 strings to match.
	if (NameR.substr(13, 3) != "2sd")	if (NameR.substr(21, 2) != ".s")
	break;
	return Intrinsic::x86_sse2_cvtsi2sd; // "86.sse2.cvtsi2s
	d"
	case 's': // 1 string to match.
	if (NameR.substr(13, 3) != "2sd")
	break;	break;

	return Intrinsic::x86_sse2_cvtss2sd; // "86.sse2.cvtss2s	switch (NameR[23]) {
	d"	default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyd_acc_ll_s0; //
		"exagon.M2.mpyd.acc.ll.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyd_acc_ll_s1; //
		"exagon.M2.mpyd.acc.ll.s1"
		}
		break;
	}	}
	break;	break;
	}	}
	break;	break;

	case 'p': // 13 strings to match.	case 'n': // 8 strings to match.
	switch (NameR[9]) {	if (NameR.substr(16, 3) != "ac.")
		break;
		switch (NameR[19]) {
	default: break;	default: break;

	case 'a': // 2 strings to match.	case 'h': // 4 strings to match.
	if (NameR.substr(10, 5) != "ddus.")	switch (NameR[20]) {
	break;
	switch (NameR[15]) {
	default: break;	default: break;

	case 'b': // 1 string to match.	case 'h': // 2 strings to match.
	return Intrinsic::x86_sse2_paddus_b; // "86.sse2.paddus.	if (NameR.substr(21, 2) != ".s")
	b"	break;
	case 'w': // 1 string to match.	switch (NameR[23]) {
	return Intrinsic::x86_sse2_paddus_w; // "86.sse2.paddus.	default: break;
	w"	case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyd_nac_hh_s0; //
		"exagon.M2.mpyd.nac.hh.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyd_nac_hh_s1; //
		"exagon.M2.mpyd.nac.hh.s1"
		}
		break;
		case 'l': // 2 strings to match.
		if (NameR.substr(21, 2) != ".s")
		break;
		switch (NameR[23]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyd_nac_hl_s0; //
		"exagon.M2.mpyd.nac.hl.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyd_nac_hl_s1; //
		"exagon.M2.mpyd.nac.hl.s1"
		}
		break;
	}	}
	break;	break;

	case 'c': // 6 strings to match.	case 'l': // 4 strings to match.
	if (NameR.substr(10, 2) != "mp")	switch (NameR[20]) {
	break;
	switch (NameR[12]) {
	default: break;	default: break;

	case 'e': // 3 strings to match.	case 'h': // 2 strings to match.
	if (NameR.substr(13, 2) != "q.")	if (NameR.substr(21, 2) != ".s")
	break;	break;

	switch (NameR[15]) {	switch (NameR[23]) {
	default: break;	default: break;

	case 'b': // 1 string to match.	case '0': // 1 string to match.
	return Intrinsic::x86_sse2_pcmpeq_b; // "86.sse2	return Intrinsic::hexagon_M2_mpyd_nac_lh_s0; //
	.pcmpeq.b"	"exagon.M2.mpyd.nac.lh.s0"
	case 'd': // 1 string to match.	case '1': // 1 string to match.
	return Intrinsic::x86_sse2_pcmpeq_d; // "86.sse2	return Intrinsic::hexagon_M2_mpyd_nac_lh_s1; //
	.pcmpeq.d"	"exagon.M2.mpyd.nac.lh.s1"
	case 'w': // 1 string to match.
	return Intrinsic::x86_sse2_pcmpeq_w; // "86.sse2
	.pcmpeq.w"
	}	}
	break;	break;

	case 'g': // 3 strings to match.	case 'l': // 2 strings to match.
	if (NameR.substr(13, 2) != "t.")	if (NameR.substr(21, 2) != ".s")
	break;	break;

	switch (NameR[15]) {	switch (NameR[23]) {
	default: break;	default: break;

	case 'b': // 1 string to match.	case '0': // 1 string to match.
	return Intrinsic::x86_sse2_pcmpgt_b; // "86.sse2	return Intrinsic::hexagon_M2_mpyd_nac_ll_s0; //
	.pcmpgt.b"	"exagon.M2.mpyd.nac.ll.s0"
	case 'd': // 1 string to match.	case '1': // 1 string to match.
	return Intrinsic::x86_sse2_pcmpgt_d; // "86.sse2	return Intrinsic::hexagon_M2_mpyd_nac_ll_s1; //
	.pcmpgt.d"	"exagon.M2.mpyd.nac.ll.s1"
	case 'w': // 1 string to match.
	return Intrinsic::x86_sse2_pcmpgt_w; // "86.sse2
	.pcmpgt.w"
	}	}
	break;	break;
	}	}
	break;	break;

	case 'm': // 3 strings to match.	}
	switch (NameR[10]) {	break;
		case 'r': // 8 strings to match.
		if (NameR.substr(16, 3) != "nd.")
		break;
		switch (NameR[19]) {
		default: break;
		case 'h': // 4 strings to match.
		switch (NameR[20]) {
	default: break;	default: break;

	case 'a': // 1 string to match.	case 'h': // 2 strings to match.
	if (NameR.substr(11, 5) != "dd.wd")	if (NameR.substr(21, 2) != ".s")
	break;	break;

	return Intrinsic::x86_sse2_pmadd_wd; // "86.sse2.pmadd.w	switch (NameR[23]) {
	d"	default: break;
	case 'u': // 2 strings to match.	case '0': // 1 string to match.
	if (NameR[11] != 'l')	return Intrinsic::hexagon_M2_mpyd_rnd_hh_s0; //
		"exagon.M2.mpyd.rnd.hh.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyd_rnd_hh_s1; //
		"exagon.M2.mpyd.rnd.hh.s1"
		}
		break;
		case 'l': // 2 strings to match.
		if (NameR.substr(21, 2) != ".s")
	break;	break;

	switch (NameR[12]) {	switch (NameR[23]) {
	default: break;	default: break;

	case 'h': // 1 string to match.	case '0': // 1 string to match.
	if (NameR.substr(13, 3) != "u.w")	return Intrinsic::hexagon_M2_mpyd_rnd_hl_s0; //
	break;	"exagon.M2.mpyd.rnd.hl.s0"
	return Intrinsic::x86_sse2_pmulhu_w; // "86.sse2	case '1': // 1 string to match.
	.pmulhu.w"	return Intrinsic::hexagon_M2_mpyd_rnd_hl_s1; //
	case 'u': // 1 string to match.	"exagon.M2.mpyd.rnd.hl.s1"
	if (NameR.substr(13, 3) != ".dq")
	break;
	return Intrinsic::x86_sse2_pmulu_dq; // "86.sse2
	.pmulu.dq"
	}	}
	break;	break;
	}	}
	break;	break;

	case 's': // 2 strings to match.	case 'l': // 4 strings to match.
	if (NameR.substr(10, 5) != "ubus.")	switch (NameR[20]) {
	break;
	switch (NameR[15]) {
	default: break;	default: break;

	case 'b': // 1 string to match.	case 'h': // 2 strings to match.
	return Intrinsic::x86_sse2_psubus_b; // "86.sse2.psubus.	if (NameR.substr(21, 2) != ".s")
	b"	break;
	case 'w': // 1 string to match.	switch (NameR[23]) {
	return Intrinsic::x86_sse2_psubus_w; // "86.sse2.psubus.	default: break;
	w"	case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyd_rnd_lh_s0; //
		"exagon.M2.mpyd.rnd.lh.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyd_rnd_lh_s1; //
		"exagon.M2.mpyd.rnd.lh.s1"
		}
		break;
		case 'l': // 2 strings to match.
		if (NameR.substr(21, 2) != ".s")
		break;
		switch (NameR[23]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyd_rnd_ll_s0; //
		"exagon.M2.mpyd.rnd.ll.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyd_rnd_ll_s1; //
		"exagon.M2.mpyd.rnd.ll.s1"
		}
		break;
	}	}
	break;	break;
	}	}
	break;	break;
	}	}
	break;	break;

	case '4': // 6 strings to match.	case 'u': // 16 strings to match.
	switch (NameR[7]) {	if (NameR[14] != '.')
		break;
		switch (NameR[15]) {
	default: break;	default: break;

	case '1': // 5 strings to match.	case 'a': // 8 strings to match.
	if (NameR[8] != '.')	if (NameR.substr(16, 3) != "cc.")
	break;	break;

	switch (NameR[9]) {	switch (NameR[19]) {
	default: break;	default: break;

	case 'b': // 2 strings to match.	case 'h': // 4 strings to match.
	if (NameR.substr(10, 5) != "lendp")	switch (NameR[20]) {
	break;
	switch (NameR[15]) {
	default: break;	default: break;

	case 'd': // 1 string to match.	case 'h': // 2 strings to match.
	return Intrinsic::x86_sse41_blendpd; // "86.sse41.blendp	if (NameR.substr(21, 2) != ".s")
	d"	break;
	case 's': // 1 string to match.	switch (NameR[23]) {
	return Intrinsic::x86_sse41_blendps; // "86.sse41.blendp	default: break;
	s"	case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyu_acc_hh_s0; //
		"exagon.M2.mpyu.acc.hh.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyu_acc_hh_s1; //
		"exagon.M2.mpyu.acc.hh.s1"
		}
		break;
		case 'l': // 2 strings to match.
		if (NameR.substr(21, 2) != ".s")
		break;
		switch (NameR[23]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyu_acc_hl_s0; //
		"exagon.M2.mpyu.acc.hl.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyu_acc_hl_s1; //
		"exagon.M2.mpyu.acc.hl.s1"
		}
		break;
	}	}
	break;	break;

	case 'm': // 1 string to match.	case 'l': // 4 strings to match.
	if (NameR.substr(10, 6) != "psadbw")	switch (NameR[20]) {
	break;
	return Intrinsic::x86_sse41_mpsadbw; // "86.sse41.mpsadb
	w"
	case 'p': // 2 strings to match.
	switch (NameR[10]) {
	default: break;	default: break;

	case 'b': // 1 string to match.	case 'h': // 2 strings to match.
	if (NameR.substr(11, 5) != "lendw")	if (NameR.substr(21, 2) != ".s")
	break;	break;

	return Intrinsic::x86_sse41_pblendw; // "86.sse41.pblend	switch (NameR[23]) {
	w"	default: break;
	case 'c': // 1 string to match.	case '0': // 1 string to match.
	if (NameR.substr(11, 5) != "mpeqq")	return Intrinsic::hexagon_M2_mpyu_acc_lh_s0; //
		"exagon.M2.mpyu.acc.lh.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyu_acc_lh_s1; //
		"exagon.M2.mpyu.acc.lh.s1"
		}
		break;
		case 'l': // 2 strings to match.
		if (NameR.substr(21, 2) != ".s")
	break;	break;

	return Intrinsic::x86_sse41_pcmpeqq; // "86.sse41.pcmpeq	switch (NameR[23]) {
	q"	default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyu_acc_ll_s0; //
		"exagon.M2.mpyu.acc.ll.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyu_acc_ll_s1; //
		"exagon.M2.mpyu.acc.ll.s1"
		}
		break;
	}	}
	break;	break;
	}	}
	break;	break;

	case '2': // 1 string to match.	case 'n': // 8 strings to match.
	if (NameR.substr(8, 8) != ".pcmpgtq")	if (NameR.substr(16, 3) != "ac.")
	break;	break;

	return Intrinsic::x86_sse42_pcmpgtq; // "86.sse42.pcmpgt	switch (NameR[19]) {
	q"
	}
	break;
	}
	break;
	case 's': // 8 strings to match.
	if (NameR.substr(6, 4) != "e3.p")
	break;
	switch (NameR[10]) {
	default: break;
	case 'h': // 4 strings to match.
	switch (NameR[11]) {
	default: break;
	case 'a': // 2 strings to match.
	if (NameR.substr(12, 3) != "dd.")
	break;
	switch (NameR[15]) {
	default: break;	default: break;

	case 'd': // 1 string to match.	case 'h': // 4 strings to match.
	return Intrinsic::x86_ssse3_phadd_d; // "86.ssse3.phadd.	switch (NameR[20]) {
	d"	default: break;
	case 'w': // 1 string to match.	case 'h': // 2 strings to match.
	return Intrinsic::x86_ssse3_phadd_w; // "86.ssse3.phadd.	if (NameR.substr(21, 2) != ".s")
	w"	break;
	}	switch (NameR[23]) {
	break;	default: break;
	case 's': // 2 strings to match.	case '0': // 1 string to match.
	if (NameR.substr(12, 3) != "ub.")	return Intrinsic::hexagon_M2_mpyu_nac_hh_s0; //
		"exagon.M2.mpyu.nac.hh.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyu_nac_hh_s1; //
		"exagon.M2.mpyu.nac.hh.s1"
		}
		break;
		case 'l': // 2 strings to match.
		if (NameR.substr(21, 2) != ".s")
		break;
		switch (NameR[23]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyu_nac_hl_s0; //
		"exagon.M2.mpyu.nac.hl.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyu_nac_hl_s1; //
		"exagon.M2.mpyu.nac.hl.s1"
		}
		break;
		}
		break;
		case 'l': // 4 strings to match.
		switch (NameR[20]) {
		default: break;
		case 'h': // 2 strings to match.
		if (NameR.substr(21, 2) != ".s")
		break;
		switch (NameR[23]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyu_nac_lh_s0; //
		"exagon.M2.mpyu.nac.lh.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyu_nac_lh_s1; //
		"exagon.M2.mpyu.nac.lh.s1"
		}
		break;
		case 'l': // 2 strings to match.
		if (NameR.substr(21, 2) != ".s")
		break;
		switch (NameR[23]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyu_nac_ll_s0; //
		"exagon.M2.mpyu.nac.ll.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyu_nac_ll_s1; //
		"exagon.M2.mpyu.nac.ll.s1"
		}
		break;
		}
	break;	break;

	switch (NameR[15]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::x86_ssse3_phsub_d; // "86.ssse3.phsub.
	d"
	case 'w': // 1 string to match.
	return Intrinsic::x86_ssse3_phsub_w; // "86.ssse3.phsub.
	w"
	}	}
	break;	break;
	}	}
	break;	break;

	case 's': // 4 strings to match.	}
	switch (NameR[11]) {	break;
		case 'v': // 7 strings to match.
		switch (NameR[11]) {
		default: break;
		case 'c': // 6 strings to match.
		if (NameR[12] != 'm')
		break;
		switch (NameR[13]) {
	default: break;	default: break;

	case 'h': // 1 string to match.	case 'a': // 2 strings to match.
	if (NameR.substr(12, 4) != "uf.b")	if (NameR.substr(14, 9) != "c.s0.sat.")
	break;	break;

	return Intrinsic::x86_ssse3_pshuf_b; // "86.ssse3.pshuf.	switch (NameR[23]) {
	b"	default: break;
	case 'i': // 3 strings to match.	case 'i': // 1 string to match.
	if (NameR.substr(12, 3) != "gn.")	return Intrinsic::hexagon_M2_vcmac_s0_sat_i; // "exagon.
		M2.vcmac.s0.sat.i"
		case 'r': // 1 string to match.
		return Intrinsic::hexagon_M2_vcmac_s0_sat_r; // "exagon.
		M2.vcmac.s0.sat.r"
		}
		break;
		case 'p': // 4 strings to match.
		if (NameR.substr(14, 3) != "y.s")
	break;	break;

	switch (NameR[15]) {	switch (NameR[17]) {
	default: break;	default: break;

	case 'b': // 1 string to match.	case '0': // 2 strings to match.
	return Intrinsic::x86_ssse3_psign_b; // "86.ssse3.psign.	if (NameR.substr(18, 5) != ".sat.")
	b"	break;
	case 'd': // 1 string to match.	switch (NameR[23]) {
	return Intrinsic::x86_ssse3_psign_d; // "86.ssse3.psign.	default: break;
	d"	case 'i': // 1 string to match.
	case 'w': // 1 string to match.	return Intrinsic::hexagon_M2_vcmpy_s0_sat_i; // "exagon.
	return Intrinsic::x86_ssse3_psign_w; // "86.ssse3.psign.	M2.vcmpy.s0.sat.i"
	w"	case 'r': // 1 string to match.
		return Intrinsic::hexagon_M2_vcmpy_s0_sat_r; // "exagon.
		M2.vcmpy.s0.sat.r"
		}
		break;
		case '1': // 2 strings to match.
		if (NameR.substr(18, 5) != ".sat.")
		break;
		switch (NameR[23]) {
		default: break;
		case 'i': // 1 string to match.
		return Intrinsic::hexagon_M2_vcmpy_s1_sat_i; // "exagon.
		M2.vcmpy.s1.sat.i"
		case 'r': // 1 string to match.
		return Intrinsic::hexagon_M2_vcmpy_s1_sat_r; // "exagon.
		M2.vcmpy.s1.sat.r"
		}
		break;
	}	}
	break;	break;
	}	}
	break;	break;

		case 'r': // 1 string to match.
		if (NameR.substr(12, 12) != "cmpys.acc.s1")
		break;
		return Intrinsic::hexagon_M2_vrcmpys_acc_s1; // "exagon.
		M2.vrcmpys.acc.s1"
	}	}
	break;	break;
	}	}
	break;	break;

	}	case 'S': // 4 strings to match.
	break;	if (NameR.substr(8, 2) != "2.")
	case 17: // 64 strings to match.
	if (NameR.substr(0, 3) != "86.")
	break;
	switch (NameR[3]) {
	default: break;
	case '3': // 4 strings to match.
	if (NameR.substr(4, 4) != "dnow")
	break;	break;

	switch (NameR[8]) {	switch (NameR[10]) {
	default: break;	default: break;

	case '.': // 3 strings to match.	case 'a': // 2 strings to match.
	if (NameR.substr(9, 3) != "pfr")	if (NameR.substr(11, 3) != "sr.")
	break;	break;

	switch (NameR[12]) {	switch (NameR[14]) {
	default: break;	default: break;

	case 'c': // 2 strings to match.	case 'i': // 1 string to match.
	if (NameR.substr(13, 3) != "pit")	if (NameR.substr(15, 9) != ".svw.trun")
	break;	break;

	switch (NameR[16]) {	return Intrinsic::hexagon_S2_asr_i_svw_trun; // "exagon.
	default: break;	S2.asr.i.svw.trun"
	case '1': // 1 string to match.	case 'r': // 1 string to match.
	return Intrinsic::x86_3dnow_pfrcpit1; // "86.3dnow.pfrcpi	if (NameR.substr(15, 9) != ".svw.trun")
	t1"
	case '2': // 1 string to match.
	return Intrinsic::x86_3dnow_pfrcpit2; // "86.3dnow.pfrcpi
	t2"
	}
	break;
	case 's': // 1 string to match.
	if (NameR.substr(13, 4) != "qit1")
	break;	break;

	return Intrinsic::x86_3dnow_pfrsqit1; // "86.3dnow.pfrsqi t1"	return Intrinsic::hexagon_S2_asr_r_svw_trun; // "exagon. S2.asr.r.svw.trun"
	}	}
	break;	break;

	case 'a': // 1 string to match.	case 'v': // 2 strings to match.
	if (NameR.substr(9, 8) != ".pfpnacc")	if (NameR.substr(11, 3) != "sat")
	break;
	return Intrinsic::x86_3dnowa_pfpnacc; // "86.3dnowa.pfpna
	cc"
	}
	break;
	case 'a': // 13 strings to match.
	if (NameR.substr(4, 3) != "vx.")
	break;
	switch (NameR[7]) {
	default: break;
	case 'c': // 2 strings to match.
	if (NameR.substr(8, 4) != "mp.p")
	break;	break;

	switch (NameR[12]) {	switch (NameR[14]) {
	default: break;	default: break;

	case 'd': // 1 string to match.	case 'h': // 1 string to match.
	if (NameR.substr(13, 4) != ".256")	if (NameR.substr(15, 9) != "ub.nopack")
	break;	break;

	return Intrinsic::x86_avx_cmp_pd_256; // "86.avx.cmp.pd.2	return Intrinsic::hexagon_S2_vsathub_nopack; // "exagon.
	56"	S2.vsathub.nopack"
	case 's': // 1 string to match.	case 'w': // 1 string to match.
	if (NameR.substr(13, 4) != ".256")	if (NameR.substr(15, 9) != "uh.nopack")
	break;	break;

	return Intrinsic::x86_avx_cmp_ps_256; // "86.avx.cmp.ps.2 56"	return Intrinsic::hexagon_S2_vsatwuh_nopack; // "exagon. S2.vsatwuh.nopack"
	}	}
	break;	break;

	case 'l': // 1 string to match.	}
	if (NameR.substr(8, 9) != "du.dq.256")	break;
		}
		break;
		case 25: // 31 strings to match.
		if (NameR.substr(0, 7) != "exagon.")
		break;
		switch (NameR[7]) {
		default: break;
		case 'A': // 14 strings to match.
		if (NameR.substr(8, 2) != "2.")
		break;
		switch (NameR[10]) {
		default: break;
		case 'a': // 8 strings to match.
		if (NameR.substr(11, 4) != "ddh.")
	break;	break;

	return Intrinsic::x86_avx_ldu_dq_256; // "86.avx.ldu.dq.2	switch (NameR[15]) {
	56"
	case 'm': // 4 strings to match.
	switch (NameR[8]) {
	default: break;	default: break;

	case 'a': // 2 strings to match.	case 'h': // 4 strings to match.
	if (NameR.substr(9, 3) != "x.p")	if (NameR.substr(16, 7) != "16.sat.")
	break;	break;

	switch (NameR[12]) {	switch (NameR[23]) {
	default: break;	default: break;

	case 'd': // 1 string to match.	case 'h': // 2 strings to match.
	if (NameR.substr(13, 4) != ".256")	switch (NameR[24]) {
	break;	default: break;
	return Intrinsic::x86_avx_max_pd_256; // "86.avx.max.pd.2	case 'h': // 1 string to match.
	56"	return Intrinsic::hexagon_A2_addh_h16_sat_hh; // "exagon.
	case 's': // 1 string to match.	A2.addh.h16.sat.hh"
	if (NameR.substr(13, 4) != ".256")	case 'l': // 1 string to match.
	break;	return Intrinsic::hexagon_A2_addh_h16_sat_hl; // "exagon.
	return Intrinsic::x86_avx_max_ps_256; // "86.avx.max.ps.2	A2.addh.h16.sat.hl"
	56"	}
		break;
		case 'l': // 2 strings to match.
		switch (NameR[24]) {
		default: break;
		case 'h': // 1 string to match.
		return Intrinsic::hexagon_A2_addh_h16_sat_lh; // "exagon.
		A2.addh.h16.sat.lh"
		case 'l': // 1 string to match.
		return Intrinsic::hexagon_A2_addh_h16_sat_ll; // "exagon.
		A2.addh.h16.sat.ll"
		}
		break;
	}	}
	break;	break;

	case 'i': // 2 strings to match.	case 'l': // 4 strings to match.
	if (NameR.substr(9, 3) != "n.p")	if (NameR.substr(16, 7) != "16.sat.")
	break;	break;

	switch (NameR[12]) {	switch (NameR[23]) {
	default: break;	default: break;

	case 'd': // 1 string to match.	case 'h': // 2 strings to match.
	if (NameR.substr(13, 4) != ".256")	switch (NameR[24]) {
	break;	default: break;
	return Intrinsic::x86_avx_min_pd_256; // "86.avx.min.pd.2	case 'h': // 1 string to match.
	56"	return Intrinsic::hexagon_A2_addh_l16_sat_hh; // "exagon.
	case 's': // 1 string to match.	A2.addh.l16.sat.hh"
	if (NameR.substr(13, 4) != ".256")	case 'l': // 1 string to match.
	break;	return Intrinsic::hexagon_A2_addh_l16_sat_hl; // "exagon.
	return Intrinsic::x86_avx_min_ps_256; // "86.avx.min.ps.2	A2.addh.l16.sat.hl"
	56"	}
		break;
		case 'l': // 2 strings to match.
		switch (NameR[24]) {
		default: break;
		case 'h': // 1 string to match.
		return Intrinsic::hexagon_A2_addh_l16_sat_lh; // "exagon.
		A2.addh.l16.sat.lh"
		case 'l': // 1 string to match.
		return Intrinsic::hexagon_A2_addh_l16_sat_ll; // "exagon.
		A2.addh.l16.sat.ll"
		}
		break;
	}	}
	break;	break;
	}	}
	break;	break;

	case 'p': // 2 strings to match.	case 's': // 6 strings to match.
	if (NameR.substr(8, 4) != "test")	if (NameR.substr(11, 4) != "ubh.")
	break;	break;

	switch (NameR[12]) {	switch (NameR[15]) {
	default: break;	default: break;

	case 'c': // 1 string to match.	case 'h': // 4 strings to match.
	if (NameR.substr(13, 4) != ".256")	if (NameR.substr(16, 7) != "16.sat.")
	break;	break;

	return Intrinsic::x86_avx_ptestc_256; // "86.avx.ptestc.2	switch (NameR[23]) {
	56"	default: break;
	case 'z': // 1 string to match.	case 'h': // 2 strings to match.
	if (NameR.substr(13, 4) != ".256")	switch (NameR[24]) {
		default: break;
		case 'h': // 1 string to match.
		return Intrinsic::hexagon_A2_subh_h16_sat_hh; // "exagon.
		A2.subh.h16.sat.hh"
		case 'l': // 1 string to match.
		return Intrinsic::hexagon_A2_subh_h16_sat_hl; // "exagon.
		A2.subh.h16.sat.hl"
		}
	break;	break;

	return Intrinsic::x86_avx_ptestz_256; // "86.avx.ptestz.2	case 'l': // 2 strings to match.
	56"	switch (NameR[24]) {
	}	default: break;
	break;	case 'h': // 1 string to match.
	case 'r': // 1 string to match.	return Intrinsic::hexagon_A2_subh_h16_sat_lh; // "exagon.
	if (NameR.substr(8, 9) != "cp.ps.256")	A2.subh.h16.sat.lh"
		case 'l': // 1 string to match.
		return Intrinsic::hexagon_A2_subh_h16_sat_ll; // "exagon.
		A2.subh.h16.sat.ll"
		}
		break;
		}
	break;	break;

	return Intrinsic::x86_avx_rcp_ps_256; // "86.avx.rcp.ps.2	case 'l': // 2 strings to match.
	56"	if (NameR.substr(16, 7) != "16.sat.")
	case 'v': // 3 strings to match.
	switch (NameR[8]) {
	default: break;
	case 'p': // 2 strings to match.
	if (NameR.substr(9, 7) != "ermil.p")
	break;	break;

	switch (NameR[16]) {	switch (NameR[23]) {
	default: break;	default: break;

	case 'd': // 1 string to match.	case 'h': // 1 string to match.
	return Intrinsic::x86_avx_vpermil_pd; // "86.avx.vpermil.	if (NameR[24] != 'l')
	pd"	break;
	case 's': // 1 string to match.	return Intrinsic::hexagon_A2_subh_l16_sat_hl; // "exagon.
	return Intrinsic::x86_avx_vpermil_ps; // "86.avx.vpermil.	A2.subh.l16.sat.hl"
	ps"	case 'l': // 1 string to match.
		if (NameR[24] != 'l')
		break;
		return Intrinsic::hexagon_A2_subh_l16_sat_ll; // "exagon.
		A2.subh.l16.sat.ll"
	}	}
	break;	break;

	case 'z': // 1 string to match.
	if (NameR.substr(9, 8) != "eroupper")
	break;
	return Intrinsic::x86_avx_vzeroupper; // "86.avx.vzeroupp
	er"
	}	}
	break;	break;
	}	}
	break;	break;

	case 's': // 47 strings to match.	case 'C': // 1 string to match.
	if (NameR[4] != 's')	if (NameR.substr(8, 17) != "4.fastcorner9.not")
	break;	break;

	switch (NameR[5]) {	return Intrinsic::hexagon_C4_fastcorner9_not; // "exagon.C4.fastc
		orner9.not"
		case 'M': // 16 strings to match.
		if (NameR.substr(8, 8) != "2.mpyud.")
		break;
		switch (NameR[16]) {
	default: break;	default: break;

	case 'e': // 45 strings to match.	case 'a': // 8 strings to match.
	switch (NameR[6]) {	if (NameR.substr(17, 3) != "cc.")
		break;
		switch (NameR[20]) {
	default: break;	default: break;

	case '.': // 8 strings to match.	case 'h': // 4 strings to match.
	switch (NameR[7]) {	switch (NameR[21]) {
	default: break;	default: break;

	case 'c': // 3 strings to match.	case 'h': // 2 strings to match.
	switch (NameR[8]) {	if (NameR.substr(22, 2) != ".s")
		break;
		switch (NameR[24]) {
	default: break;	default: break;

	case 'o': // 1 string to match.	case '0': // 1 string to match.
	if (NameR.substr(9, 8) != "mineq.ss")	return Intrinsic::hexagon_M2_mpyud_acc_hh_s0; // "exagon.
	break;	M2.mpyud.acc.hh.s0"
	return Intrinsic::x86_sse_comineq_ss; // "86.sse.comineq.	case '1': // 1 string to match.
	ss"	return Intrinsic::hexagon_M2_mpyud_acc_hh_s1; // "exagon.
	case 'v': // 2 strings to match.	M2.mpyud.acc.hh.s1"
	if (NameR.substr(9, 2) != "ts")
	break;
	switch (NameR[11]) {
	default: break;
	case 'i': // 1 string to match.
	if (NameR.substr(12, 5) != "642ss")
	break;
	return Intrinsic::x86_sse_cvtsi642ss; // "86.sse.
	cvtsi642ss"
	case 's': // 1 string to match.
	if (NameR.substr(12, 5) != "2si64")
	break;
	return Intrinsic::x86_sse_cvtss2si64; // "86.sse.
	cvtss2si64"
	}
	break;
	}	}
	break;	break;

	case 'u': // 5 strings to match.	case 'l': // 2 strings to match.
	if (NameR.substr(8, 4) != "comi")	if (NameR.substr(22, 2) != ".s")
	break;	break;

	switch (NameR[12]) {	switch (NameR[24]) {
	default: break;	default: break;

	case 'e': // 1 string to match.	case '0': // 1 string to match.
	if (NameR.substr(13, 4) != "q.ss")	return Intrinsic::hexagon_M2_mpyud_acc_hl_s0; // "exagon.
	break;	M2.mpyud.acc.hl.s0"
	return Intrinsic::x86_sse_ucomieq_ss; // "86.sse.ucomieq.	case '1': // 1 string to match.
	ss"	return Intrinsic::hexagon_M2_mpyud_acc_hl_s1; // "exagon.
	case 'g': // 2 strings to match.	M2.mpyud.acc.hl.s1"
	switch (NameR[13]) {
	default: break;
	case 'e': // 1 string to match.
	if (NameR.substr(14, 3) != ".ss")
	break;
	return Intrinsic::x86_sse_ucomige_ss; // "86.sse.
	ucomige.ss"
	case 't': // 1 string to match.
	if (NameR.substr(14, 3) != ".ss")
	break;
	return Intrinsic::x86_sse_ucomigt_ss; // "86.sse.
	ucomigt.ss"
	}
	break;
	case 'l': // 2 strings to match.
	switch (NameR[13]) {
	default: break;
	case 'e': // 1 string to match.
	if (NameR.substr(14, 3) != ".ss")
	break;
	return Intrinsic::x86_sse_ucomile_ss; // "86.sse.
	ucomile.ss"
	case 't': // 1 string to match.
	if (NameR.substr(14, 3) != ".ss")
	break;
	return Intrinsic::x86_sse_ucomilt_ss; // "86.sse.
	ucomilt.ss"
	}
	break;
	}	}
	break;	break;
	}	}
	break;	break;

	case '2': // 12 strings to match.	case 'l': // 4 strings to match.
	if (NameR[7] != '.')	switch (NameR[21]) {
	break;
	switch (NameR[8]) {
	default: break;	default: break;

	case 'c': // 8 strings to match.	case 'h': // 2 strings to match.
	switch (NameR[9]) {	if (NameR.substr(22, 2) != ".s")
		break;
		switch (NameR[24]) {
	default: break;	default: break;

	case 'o': // 5 strings to match.	case '0': // 1 string to match.
	if (NameR.substr(10, 2) != "mi")	return Intrinsic::hexagon_M2_mpyud_acc_lh_s0; // "exagon.
	break;	M2.mpyud.acc.lh.s0"
	switch (NameR[12]) {	case '1': // 1 string to match.
	default: break;	return Intrinsic::hexagon_M2_mpyud_acc_lh_s1; // "exagon.
	case 'e': // 1 string to match.	M2.mpyud.acc.lh.s1"
	if (NameR.substr(13, 4) != "q.sd")	}
	break;	break;
	return Intrinsic::x86_sse2_comieq_sd; // "86.sse2	case 'l': // 2 strings to match.
	.comieq.sd"	if (NameR.substr(22, 2) != ".s")
	case 'g': // 2 strings to match.
	switch (NameR[13]) {
	default: break;
	case 'e': // 1 string to match.
	if (NameR.substr(14, 3) != ".sd")
	break;
	return Intrinsic::x86_sse2_comige_sd; // "86.sse2
	.comige.sd"
	case 't': // 1 string to match.
	if (NameR.substr(14, 3) != ".sd")
	break;
	return Intrinsic::x86_sse2_comigt_sd; // "86.sse2
	.comigt.sd"
	}
	break;
	case 'l': // 2 strings to match.
	switch (NameR[13]) {
	default: break;
	case 'e': // 1 string to match.
	if (NameR.substr(14, 3) != ".sd")
	break;
	return Intrinsic::x86_sse2_comile_sd; // "86.sse2
	.comile.sd"
	case 't': // 1 string to match.
	if (NameR.substr(14, 3) != ".sd")
	break;
	return Intrinsic::x86_sse2_comilt_sd; // "86.sse2
	.comilt.sd"
	}
	break;
	}
	break;	break;

	case 'v': // 3 strings to match.	switch (NameR[24]) {
	if (NameR.substr(10, 2) != "tt")	default: break;
	break;	case '0': // 1 string to match.
	switch (NameR[12]) {	return Intrinsic::hexagon_M2_mpyud_acc_ll_s0; // "exagon.
	default: break;	M2.mpyud.acc.ll.s0"
	case 'p': // 2 strings to match.	case '1': // 1 string to match.
	switch (NameR[13]) {	return Intrinsic::hexagon_M2_mpyud_acc_ll_s1; // "exagon.
	default: break;	M2.mpyud.acc.ll.s1"
	case 'd': // 1 string to match.	}
	if (NameR.substr(14, 3) != "2dq")	break;
	break;	}
	return Intrinsic::x86_sse2_cvttpd2dq; // "86.sse2	break;
	.cvttpd2dq"	}
	case 's': // 1 string to match.	break;
	if (NameR.substr(14, 3) != "2dq")	case 'n': // 8 strings to match.
	break;	if (NameR.substr(17, 3) != "ac.")
	return Intrinsic::x86_sse2_cvttps2dq; // "86.sse2	break;
	.cvttps2dq"	switch (NameR[20]) {
	}	default: break;
	break;	case 'h': // 4 strings to match.
	case 's': // 1 string to match.	switch (NameR[21]) {
	if (NameR.substr(13, 4) != "d2si")	default: break;
	break;	case 'h': // 2 strings to match.
	return Intrinsic::x86_sse2_cvttsd2si; // "86.sse2	if (NameR.substr(22, 2) != ".s")
	.cvttsd2si"
	}
	break;	break;

		switch (NameR[24]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyud_nac_hh_s0; // "exagon.
		M2.mpyud.nac.hh.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyud_nac_hh_s1; // "exagon.
		M2.mpyud.nac.hh.s1"
	}	}
	break;	break;

	case 'm': // 1 string to match.	case 'l': // 2 strings to match.
	if (NameR.substr(9, 8) != "ovmsk.pd")	if (NameR.substr(22, 2) != ".s")
	break;	break;

	return Intrinsic::x86_sse2_movmsk_pd; // "86.sse2.movmsk.	switch (NameR[24]) {
	pd"	default: break;
	case 's': // 3 strings to match.	case '0': // 1 string to match.
	if (NameR.substr(9, 4) != "tore")	return Intrinsic::hexagon_M2_mpyud_nac_hl_s0; // "exagon.
		M2.mpyud.nac.hl.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyud_nac_hl_s1; // "exagon.
		M2.mpyud.nac.hl.s1"
		}
		break;
		}
		break;
		case 'l': // 4 strings to match.
		switch (NameR[21]) {
		default: break;
		case 'h': // 2 strings to match.
		if (NameR.substr(22, 2) != ".s")
	break;	break;

	switch (NameR[13]) {	switch (NameR[24]) {
	default: break;	default: break;

	case 'l': // 1 string to match.	case '0': // 1 string to match.
	if (NameR.substr(14, 3) != ".dq")	return Intrinsic::hexagon_M2_mpyud_nac_lh_s0; // "exagon.
	break;	M2.mpyud.nac.lh.s0"
	return Intrinsic::x86_sse2_storel_dq; // "86.sse2.storel.	case '1': // 1 string to match.
	dq"	return Intrinsic::hexagon_M2_mpyud_nac_lh_s1; // "exagon.
	case 'u': // 2 strings to match.	M2.mpyud.nac.lh.s1"
	if (NameR[14] != '.')	}
	break;	break;
	switch (NameR[15]) {	case 'l': // 2 strings to match.
	default: break;	if (NameR.substr(22, 2) != ".s")
	case 'd': // 1 string to match.
	if (NameR[16] != 'q')
	break;
	return Intrinsic::x86_sse2_storeu_dq; // "86.sse2
	.storeu.dq"
	case 'p': // 1 string to match.
	if (NameR[16] != 'd')
	break;
	return Intrinsic::x86_sse2_storeu_pd; // "86.sse2
	.storeu.pd"
	}
	break;	break;

		switch (NameR[24]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyud_nac_ll_s0; // "exagon.
		M2.mpyud.nac.ll.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyud_nac_ll_s1; // "exagon.
		M2.mpyud.nac.ll.s1"
	}	}
	break;	break;
	}	}
	break;	break;

	case '3': // 2 strings to match.	}
	if (NameR.substr(7, 9) != ".addsub.p")	break;
		}
		break;
		}
		break;
		case 27: // 24 strings to match.
		if (NameR.substr(0, 14) != "exagon.M2.mpy.")
		break;
		switch (NameR[14]) {
		default: break;
		case 'a': // 8 strings to match.
		if (NameR.substr(15, 7) != "cc.sat.")
		break;
		switch (NameR[22]) {
		default: break;
		case 'h': // 4 strings to match.
		switch (NameR[23]) {
		default: break;
		case 'h': // 2 strings to match.
		if (NameR.substr(24, 2) != ".s")
	break;	break;

	switch (NameR[16]) {	switch (NameR[26]) {
	default: break;	default: break;

	case 'd': // 1 string to match.	case '0': // 1 string to match.
	return Intrinsic::x86_sse3_addsub_pd; // "86.sse3.addsub.	return Intrinsic::hexagon_M2_mpy_acc_sat_hh_s0; // "exagon.
	pd"	M2.mpy.acc.sat.hh.s0"
	case 's': // 1 string to match.	case '1': // 1 string to match.
	return Intrinsic::x86_sse3_addsub_ps; // "86.sse3.addsub.	return Intrinsic::hexagon_M2_mpy_acc_sat_hh_s1; // "exagon.
	ps"	M2.mpy.acc.sat.hh.s1"
	}	}
	break;	break;

	case '4': // 23 strings to match.	case 'l': // 2 strings to match.
	if (NameR.substr(7, 2) != "1.")	if (NameR.substr(24, 2) != ".s")
	break;	break;

	switch (NameR[9]) {	switch (NameR[26]) {
	default: break;	default: break;

	case 'b': // 2 strings to match.	case '0': // 1 string to match.
	if (NameR.substr(10, 6) != "lendvp")	return Intrinsic::hexagon_M2_mpy_acc_sat_hl_s0; // "exagon.
	break;	M2.mpy.acc.sat.hl.s0"
	switch (NameR[16]) {	case '1': // 1 string to match.
	default: break;	return Intrinsic::hexagon_M2_mpy_acc_sat_hl_s1; // "exagon.
	case 'd': // 1 string to match.	M2.mpy.acc.sat.hl.s1"
	return Intrinsic::x86_sse41_blendvpd; // "86.sse41.blendv	}
	pd"	break;
	case 's': // 1 string to match.	}
	return Intrinsic::x86_sse41_blendvps; // "86.sse41.blendv	break;
	ps"	case 'l': // 4 strings to match.
	}	switch (NameR[23]) {
	break;	default: break;
	case 'i': // 1 string to match.	case 'h': // 2 strings to match.
	if (NameR.substr(10, 7) != "nsertps")	if (NameR.substr(24, 2) != ".s")
	break;
	return Intrinsic::x86_sse41_insertps; // "86.sse41.insert
	ps"
	case 'm': // 1 string to match.
	if (NameR.substr(10, 7) != "ovntdqa")
	break;
	return Intrinsic::x86_sse41_movntdqa; // "86.sse41.movntd
	qa"
	case 'p': // 15 strings to match.
	switch (NameR[10]) {
	default: break;
	case 'a': // 1 string to match.
	if (NameR.substr(11, 6) != "ckusdw")
	break;
	return Intrinsic::x86_sse41_packusdw; // "86.sse41.packus
	dw"
	case 'b': // 1 string to match.
	if (NameR.substr(11, 6) != "lendvb")
	break;
	return Intrinsic::x86_sse41_pblendvb; // "86.sse41.pblend
	vb"
	case 'm': // 12 strings to match.
	if (NameR.substr(11, 2) != "ov")
	break;
	switch (NameR[13]) {
	default: break;
	case 's': // 6 strings to match.
	if (NameR[14] != 'x')
	break;
	switch (NameR[15]) {
	default: break;
	case 'b': // 3 strings to match.
	switch (NameR[16]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::x86_sse41_pmovsxbd; // "86.sse4
	1.pmovsxbd"
	case 'q': // 1 string to match.
	return Intrinsic::x86_sse41_pmovsxbq; // "86.sse4
	1.pmovsxbq"
	case 'w': // 1 string to match.
	return Intrinsic::x86_sse41_pmovsxbw; // "86.sse4
	1.pmovsxbw"
	}
	break;
	case 'd': // 1 string to match.
	if (NameR[16] != 'q')
	break;
	return Intrinsic::x86_sse41_pmovsxdq; // "86.sse4
	1.pmovsxdq"
	case 'w': // 2 strings to match.
	switch (NameR[16]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::x86_sse41_pmovsxwd; // "86.sse4
	1.pmovsxwd"
	case 'q': // 1 string to match.
	return Intrinsic::x86_sse41_pmovsxwq; // "86.sse4
	1.pmovsxwq"
	}
	break;
	}
	break;
	case 'z': // 6 strings to match.
	if (NameR[14] != 'x')
	break;
	switch (NameR[15]) {
	default: break;
	case 'b': // 3 strings to match.
	switch (NameR[16]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::x86_sse41_pmovzxbd; // "86.sse4
	1.pmovzxbd"
	case 'q': // 1 string to match.
	return Intrinsic::x86_sse41_pmovzxbq; // "86.sse4
	1.pmovzxbq"
	case 'w': // 1 string to match.
	return Intrinsic::x86_sse41_pmovzxbw; // "86.sse4
	1.pmovzxbw"
	}
	break;
	case 'd': // 1 string to match.
	if (NameR[16] != 'q')
	break;
	return Intrinsic::x86_sse41_pmovzxdq; // "86.sse4
	1.pmovzxdq"
	case 'w': // 2 strings to match.
	switch (NameR[16]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::x86_sse41_pmovzxwd; // "86.sse4
	1.pmovzxwd"
	case 'q': // 1 string to match.
	return Intrinsic::x86_sse41_pmovzxwq; // "86.sse4
	1.pmovzxwq"
	}
	break;
	}
	break;
	}
	break;
	case 't': // 1 string to match.
	if (NameR.substr(11, 6) != "estnzc")
	break;
	return Intrinsic::x86_sse41_ptestnzc; // "86.sse41.ptestn
	zc"
	}
	break;
	case 'r': // 4 strings to match.
	if (NameR.substr(10, 5) != "ound.")
	break;
	switch (NameR[15]) {
	default: break;
	case 'p': // 2 strings to match.
	switch (NameR[16]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::x86_sse41_round_pd; // "86.sse4
	1.round.pd"
	case 's': // 1 string to match.
	return Intrinsic::x86_sse41_round_ps; // "86.sse4
	1.round.ps"
	}
	break;
	case 's': // 2 strings to match.
	switch (NameR[16]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::x86_sse41_round_sd; // "86.sse4
	1.round.sd"
	case 's': // 1 string to match.
	return Intrinsic::x86_sse41_round_ss; // "86.sse4
	1.round.ss"
	}
	break;
	}
	break;	break;

		switch (NameR[26]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_acc_sat_lh_s0; // "exagon.
		M2.mpy.acc.sat.lh.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_acc_sat_lh_s1; // "exagon.
		M2.mpy.acc.sat.lh.s1"
	}	}
	break;	break;

	}	case 'l': // 2 strings to match.
	break;	if (NameR.substr(24, 2) != ".s")
	case 's': // 2 strings to match.
	if (NameR.substr(6, 5) != "e3.ph")
	break;
	switch (NameR[11]) {
	default: break;
	case 'a': // 1 string to match.
	if (NameR.substr(12, 5) != "dd.sw")
	break;
	return Intrinsic::x86_ssse3_phadd_sw; // "86.ssse3.phadd.
	sw"
	case 's': // 1 string to match.
	if (NameR.substr(12, 5) != "ub.sw")
	break;	break;

	return Intrinsic::x86_ssse3_phsub_sw; // "86.ssse3.phsub.	switch (NameR[26]) {
	sw"	default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_acc_sat_ll_s0; // "exagon.
		M2.mpy.acc.sat.ll.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_acc_sat_ll_s1; // "exagon.
		M2.mpy.acc.sat.ll.s1"
		}
		break;
	}	}
	break;	break;
	}	}
	break;	break;

	}	case 'n': // 8 strings to match.
	break;	if (NameR.substr(15, 7) != "ac.sat.")
	case 18: // 23 strings to match.
	if (NameR.substr(0, 3) != "86.")
	break;
	switch (NameR[3]) {
	default: break;
	case 'a': // 10 strings to match.
	if (NameR.substr(4, 3) != "vx.")
	break;	break;

	switch (NameR[7]) {	switch (NameR[22]) {
	default: break;	default: break;
	case 'h': // 4 strings to match.	case 'h': // 4 strings to match.

	switch (NameR[8]) {	switch (NameR[23]) {
	default: break;	default: break;

	case 'a': // 2 strings to match.	case 'h': // 2 strings to match.
	if (NameR.substr(9, 4) != "dd.p")	if (NameR.substr(24, 2) != ".s")
	break;	break;

	switch (NameR[13]) {	switch (NameR[26]) {
	default: break;	default: break;

	case 'd': // 1 string to match.	case '0': // 1 string to match.
	if (NameR.substr(14, 4) != ".256")	return Intrinsic::hexagon_M2_mpy_nac_sat_hh_s0; // "exagon.
	break;	M2.mpy.nac.sat.hh.s0"
	return Intrinsic::x86_avx_hadd_pd_256; // "86.avx.hadd.pd.	case '1': // 1 string to match.
	256"	return Intrinsic::hexagon_M2_mpy_nac_sat_hh_s1; // "exagon.
	case 's': // 1 string to match.	M2.mpy.nac.sat.hh.s1"
	if (NameR.substr(14, 4) != ".256")
	break;
	return Intrinsic::x86_avx_hadd_ps_256; // "86.avx.hadd.ps.
	256"
	}	}
	break;	break;

	case 's': // 2 strings to match.	case 'l': // 2 strings to match.
	if (NameR.substr(9, 4) != "ub.p")	if (NameR.substr(24, 2) != ".s")
	break;	break;

	switch (NameR[13]) {	switch (NameR[26]) {
	default: break;	default: break;

	case 'd': // 1 string to match.	case '0': // 1 string to match.
	if (NameR.substr(14, 4) != ".256")	return Intrinsic::hexagon_M2_mpy_nac_sat_hl_s0; // "exagon.
	break;	M2.mpy.nac.sat.hl.s0"
	return Intrinsic::x86_avx_hsub_pd_256; // "86.avx.hsub.pd.	case '1': // 1 string to match.
	256"	return Intrinsic::hexagon_M2_mpy_nac_sat_hl_s1; // "exagon.
	case 's': // 1 string to match.	M2.mpy.nac.sat.hl.s1"
	if (NameR.substr(14, 4) != ".256")
	break;
	return Intrinsic::x86_avx_hsub_ps_256; // "86.avx.hsub.ps.
	256"
	}	}
	break;	break;
	}	}
	break;	break;

	case 'm': // 2 strings to match.	case 'l': // 4 strings to match.
	if (NameR.substr(8, 9) != "askload.p")	switch (NameR[23]) {
	break;
	switch (NameR[17]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::x86_avx_maskload_pd; // "86.avx.maskload
	.pd"
	case 's': // 1 string to match.
	return Intrinsic::x86_avx_maskload_ps; // "86.avx.maskload
	.ps"
	}
	break;
	case 's': // 2 strings to match.
	if (NameR.substr(8, 5) != "qrt.p")
	break;
	switch (NameR[13]) {
	default: break;	default: break;

	case 'd': // 1 string to match.	case 'h': // 2 strings to match.
	if (NameR.substr(14, 4) != ".256")	if (NameR.substr(24, 2) != ".s")
	break;	break;

	return Intrinsic::x86_avx_sqrt_pd_256; // "86.avx.sqrt.pd.	switch (NameR[26]) {
	256"	default: break;
	case 's': // 1 string to match.	case '0': // 1 string to match.
	if (NameR.substr(14, 4) != ".256")	return Intrinsic::hexagon_M2_mpy_nac_sat_lh_s0; // "exagon.
		M2.mpy.nac.sat.lh.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_nac_sat_lh_s1; // "exagon.
		M2.mpy.nac.sat.lh.s1"
		}
		break;
		case 'l': // 2 strings to match.
		if (NameR.substr(24, 2) != ".s")
	break;	break;

	return Intrinsic::x86_avx_sqrt_ps_256; // "86.avx.sqrt.ps.	switch (NameR[26]) {
	256"	default: break;
	}	case '0': // 1 string to match.
	break;	return Intrinsic::hexagon_M2_mpy_nac_sat_ll_s0; // "exagon.
	case 'v': // 2 strings to match.	M2.mpy.nac.sat.ll.s0"
	if (NameR.substr(8, 9) != "testnzc.p")	case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_nac_sat_ll_s1; // "exagon.
		M2.mpy.nac.sat.ll.s1"
		}
	break;	break;

	switch (NameR[17]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::x86_avx_vtestnzc_pd; // "86.avx.vtestnzc
	.pd"
	case 's': // 1 string to match.
	return Intrinsic::x86_avx_vtestnzc_ps; // "86.avx.vtestnzc
	.ps"
	}	}
	break;	break;
	}	}
	break;	break;

	case 's': // 13 strings to match.	case 's': // 8 strings to match.
	if (NameR.substr(4, 2) != "se")	if (NameR.substr(15, 7) != "at.rnd.")
	break;	break;

	switch (NameR[6]) {	switch (NameR[22]) {
	default: break;	default: break;

	case '.': // 2 strings to match.	case 'h': // 4 strings to match.
	switch (NameR[7]) {	switch (NameR[23]) {
	default: break;	default: break;

	case 'c': // 1 string to match.	case 'h': // 2 strings to match.
	if (NameR.substr(8, 10) != "vttss2si64")	if (NameR.substr(24, 2) != ".s")
	break;	break;

	return Intrinsic::x86_sse_cvttss2si64; // "86.sse.cvttss2s	switch (NameR[26]) {
	i64"	default: break;
	case 'u': // 1 string to match.	case '0': // 1 string to match.
	if (NameR.substr(8, 10) != "comineq.ss")	return Intrinsic::hexagon_M2_mpy_sat_rnd_hh_s0; // "exagon.
		M2.mpy.sat.rnd.hh.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_sat_rnd_hh_s1; // "exagon.
		M2.mpy.sat.rnd.hh.s1"
		}
		break;
		case 'l': // 2 strings to match.
		if (NameR.substr(24, 2) != ".s")
	break;	break;

	return Intrinsic::x86_sse_ucomineq_ss; // "86.sse.ucomineq	switch (NameR[26]) {
	.ss"	default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_sat_rnd_hl_s0; // "exagon.
		M2.mpy.sat.rnd.hl.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_sat_rnd_hl_s1; // "exagon.
		M2.mpy.sat.rnd.hl.s1"
		}
		break;
	}	}
	break;	break;

	case '2': // 10 strings to match.	case 'l': // 4 strings to match.
	if (NameR[7] != '.')	switch (NameR[23]) {
	break;
	switch (NameR[8]) {
	default: break;	default: break;

	case 'c': // 3 strings to match.	case 'h': // 2 strings to match.
	switch (NameR[9]) {	if (NameR.substr(24, 2) != ".s")
	default: break;
	case 'o': // 1 string to match.
	if (NameR.substr(10, 8) != "mineq.sd")
	break;
	return Intrinsic::x86_sse2_comineq_sd; // "86.sse2.comineq
	.sd"
	case 'v': // 2 strings to match.
	if (NameR.substr(10, 2) != "ts")
	break;
	switch (NameR[12]) {
	default: break;
	case 'd': // 1 string to match.
	if (NameR.substr(13, 5) != "2si64")
	break;
	return Intrinsic::x86_sse2_cvtsd2si64; // "86.sse2.cvtsd2s
	i64"
	case 'i': // 1 string to match.
	if (NameR.substr(13, 5) != "642sd")
	break;
	return Intrinsic::x86_sse2_cvtsi642sd; // "86.sse2.cvtsi64
	2sd"
	}
	break;	break;

		switch (NameR[26]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_sat_rnd_lh_s0; // "exagon.
		M2.mpy.sat.rnd.lh.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_sat_rnd_lh_s1; // "exagon.
		M2.mpy.sat.rnd.lh.s1"
	}	}
	break;	break;

	case 'p': // 2 strings to match.	case 'l': // 2 strings to match.
	if (NameR[9] != 's')	if (NameR.substr(24, 2) != ".s")
	break;	break;

	switch (NameR[10]) {	switch (NameR[26]) {
	default: break;	default: break;

	case 'l': // 1 string to match.	case '0': // 1 string to match.
	if (NameR.substr(11, 7) != "l.dq.bs")	return Intrinsic::hexagon_M2_mpy_sat_rnd_ll_s0; // "exagon.
	break;	M2.mpy.sat.rnd.ll.s0"
	return Intrinsic::x86_sse2_psll_dq_bs; // "86.sse2.psll.dq	case '1': // 1 string to match.
	.bs"	return Intrinsic::hexagon_M2_mpy_sat_rnd_ll_s1; // "exagon.
	case 'r': // 1 string to match.	M2.mpy.sat.rnd.ll.s1"
	if (NameR.substr(11, 7) != "l.dq.bs")
	break;
	return Intrinsic::x86_sse2_psrl_dq_bs; // "86.sse2.psrl.dq
	.bs"
	}	}
	break;	break;

	case 'u': // 5 strings to match.	}
	if (NameR.substr(9, 4) != "comi")	break;
	break;	}
	switch (NameR[13]) {	break;
	default: break;	}
	case 'e': // 1 string to match.	break;
	if (NameR.substr(14, 4) != "q.sd")	case 30: // 4 strings to match.
	break;	if (NameR.substr(0, 18) != "exagon.S2.tableidx")
	return Intrinsic::x86_sse2_ucomieq_sd; // "86.sse2.ucomieq	break;
	.sd"	switch (NameR[18]) {
	case 'g': // 2 strings to match.	default: break;
	switch (NameR[14]) {	case 'b': // 1 string to match.
	default: break;	if (NameR.substr(19, 11) != ".goodsyntax")
	case 'e': // 1 string to match.	break;
	if (NameR.substr(15, 3) != ".sd")	return Intrinsic::hexagon_S2_tableidxb_goodsyntax; // "exagon.
	break;	S2.tableidxb.goodsyntax"
	return Intrinsic::x86_sse2_ucomige_sd; // "86.sse2.ucomige	case 'd': // 1 string to match.
	.sd"	if (NameR.substr(19, 11) != ".goodsyntax")
	case 't': // 1 string to match.	break;
	if (NameR.substr(15, 3) != ".sd")	return Intrinsic::hexagon_S2_tableidxd_goodsyntax; // "exagon.
	break;	S2.tableidxd.goodsyntax"
	return Intrinsic::x86_sse2_ucomigt_sd; // "86.sse2.ucomigt	case 'h': // 1 string to match.
	.sd"	if (NameR.substr(19, 11) != ".goodsyntax")
	}	break;
	break;	return Intrinsic::hexagon_S2_tableidxh_goodsyntax; // "exagon.
	case 'l': // 2 strings to match.	S2.tableidxh.goodsyntax"
	switch (NameR[14]) {	case 'w': // 1 string to match.
	default: break;	if (NameR.substr(19, 11) != ".goodsyntax")
	case 'e': // 1 string to match.	break;
	if (NameR.substr(15, 3) != ".sd")	return Intrinsic::hexagon_S2_tableidxw_goodsyntax; // "exagon.
	break;	S2.tableidxw.goodsyntax"
	return Intrinsic::x86_sse2_ucomile_sd; // "86.sse2.ucomile	}
	.sd"	break;
	case 't': // 1 string to match.	case 32: // 1 string to match.
	if (NameR.substr(15, 3) != ".sd")	if (NameR.substr(0, 32) != "exagon.S2.asr.i.r.rnd.goodsyntax")
	break;	break;
	return Intrinsic::x86_sse2_ucomilt_sd; // "86.sse2.ucomilt	return Intrinsic::hexagon_S2_asr_i_r_rnd_goodsyntax; // "exagon.
	.sd"	S2.asr.i.r.rnd.goodsyntax"
	}	}
	break;	break; // end of 'h' case.
	}	case 'i':
		switch (NameR.size()) {
		default: break;
		case 12: // 1 string to match.
		if (NameR.substr(0, 12) != "nvariant.end")
		break;
		return Intrinsic::invariant_end; // "nvariant.end"
		case 14: // 2 strings to match.
		if (NameR[0] != 'n')
		break;
		switch (NameR[1]) {
		default: break;
		case 'i': // 1 string to match.
		if (NameR.substr(2, 12) != "t.trampoline")
		break;
		return Intrinsic::init_trampoline; // "nit.trampoline"
		case 'v': // 1 string to match.
		if (NameR.substr(2, 12) != "ariant.start")
		break;
		return Intrinsic::invariant_start; // "nvariant.start"
		}
		break;
		}
		break; // end of 'i' case.
		case 'l':
		if (NameR.startswith("og.")) return Intrinsic::log;
		if (NameR.startswith("og10.")) return Intrinsic::log10;
		if (NameR.startswith("og2.")) return Intrinsic::log2;
		switch (NameR.size()) {
		default: break;
		case 6: // 1 string to match.
		if (NameR.substr(0, 6) != "ongjmp")
		break;
		return Intrinsic::longjmp; // "ongjmp"
		case 11: // 1 string to match.
		if (NameR.substr(0, 11) != "ifetime.end")
		break;
		return Intrinsic::lifetime_end; // "ifetime.end"
		case 13: // 1 string to match.
		if (NameR.substr(0, 13) != "ifetime.start")
		break;
		return Intrinsic::lifetime_start; // "ifetime.start"
		}
		break; // end of 'l' case.
		case 'm':
		if (NameR.startswith("emcpy.")) return Intrinsic::memcpy;
		if (NameR.startswith("emmove.")) return Intrinsic::memmove;
		if (NameR.startswith("emset.")) return Intrinsic::memset;
		break; // end of 'm' case.
		case 'o':
		if (NameR.startswith("bjectsize.")) return Intrinsic::objectsize;
		break; // end of 'o' case.
		case 'p':
		if (NameR.startswith("ow.")) return Intrinsic::pow;
		if (NameR.startswith("owi.")) return Intrinsic::powi;
		if (NameR.startswith("tr.annotation.")) return Intrinsic::ptr_annotatio
		n;
		switch (NameR.size()) {
		default: break;
		case 7: // 8 strings to match.
		switch (NameR[0]) {
		default: break;
		case 'c': // 1 string to match.
		if (NameR.substr(1, 6) != "marker")
		break;
		return Intrinsic::pcmarker; // "cmarker"
		case 'p': // 6 strings to match.
		if (NameR.substr(1, 2) != "c.")
		break;
		switch (NameR[3]) {
		default: break;
		case 'd': // 5 strings to match.
		if (NameR.substr(4, 2) != "cb")
	break;	break;

		switch (NameR[6]) {
		default: break;
		case 'a': // 1 string to match.
		return Intrinsic::ppc_dcba; // "pc.dcba"
		case 'f': // 1 string to match.
		return Intrinsic::ppc_dcbf; // "pc.dcbf"
		case 'i': // 1 string to match.
		return Intrinsic::ppc_dcbi; // "pc.dcbi"
		case 't': // 1 string to match.
		return Intrinsic::ppc_dcbt; // "pc.dcbt"
		case 'z': // 1 string to match.
		return Intrinsic::ppc_dcbz; // "pc.dcbz"
	}	}
	break;	break;

	case '4': // 1 string to match.	case 's': // 1 string to match.
	if (NameR.substr(7, 11) != "1.extractps")	if (NameR.substr(4, 3) != "ync")
	break;	break;

	return Intrinsic::x86_sse41_extractps; // "86.sse41.extrac tps"	return Intrinsic::ppc_sync; // "pc.sync"
	}	}
	break;	break;

		case 'r': // 1 string to match.
		if (NameR.substr(1, 6) != "efetch")
		break;
		return Intrinsic::prefetch; // "refetch"
	}	}
	break;	break;

	case 19: // 27 strings to match.	case 8: // 2 strings to match.
	if (NameR.substr(0, 3) != "86.")	if (NameR.substr(0, 6) != "pc.dcb")
		break;
		switch (NameR[6]) {
		default: break;
		case 's': // 1 string to match.
		if (NameR[7] != 't')
		break;
		return Intrinsic::ppc_dcbst; // "pc.dcbst"
		case 'z': // 1 string to match.
		if (NameR[7] != 'l')
		break;
		return Intrinsic::ppc_dcbzl; // "pc.dcbzl"
		}
		break;
		case 9: // 1 string to match.
		if (NameR.substr(0, 9) != "pc.dcbtst")
		break;
		return Intrinsic::ppc_dcbtst; // "pc.dcbtst"
		case 11: // 5 strings to match.
		if (NameR.substr(0, 3) != "tx.")
	break;	break;
	switch (NameR[3]) {	switch (NameR[3]) {
	default: break;	default: break;

	case 'a': // 17 strings to match.	case 'b': // 1 string to match.
	switch (NameR[4]) {	if (NameR.substr(4, 7) != "ar.sync")
		break;
		return Intrinsic::ptx_bar_sync; // "tx.bar.sync"
		case 'r': // 4 strings to match.
		if (NameR.substr(4, 6) != "ead.pm")
		break;
		switch (NameR[10]) {
	default: break;	default: break;

	case 'e': // 2 strings to match.	case '0': // 1 string to match.
	if (NameR.substr(5, 7) != "sni.aes")	return Intrinsic::ptx_read_pm0; // "tx.read.pm0"
		case '1': // 1 string to match.
		return Intrinsic::ptx_read_pm1; // "tx.read.pm1"
		case '2': // 1 string to match.
		return Intrinsic::ptx_read_pm2; // "tx.read.pm2"
		case '3': // 1 string to match.
		return Intrinsic::ptx_read_pm3; // "tx.read.pm3"
		}
		break;
		}
		break;
		case 12: // 1 string to match.
		if (NameR.substr(0, 12) != "tx.read.smid")
		break;
		return Intrinsic::ptx_read_smid; // "tx.read.smid"
		case 13: // 6 strings to match.
		if (NameR.substr(0, 8) != "tx.read.")
		break;
		switch (NameR[8]) {
		default: break;
		case 'c': // 1 string to match.
		if (NameR.substr(9, 4) != "lock")
		break;
		return Intrinsic::ptx_read_clock; // "tx.read.clock"
		case 'n': // 1 string to match.
		if (NameR.substr(9, 4) != "smid")
		break;
		return Intrinsic::ptx_read_nsmid; // "tx.read.nsmid"
		case 't': // 4 strings to match.
		if (NameR.substr(9, 3) != "id.")
		break;
		switch (NameR[12]) {
		default: break;
		case 'w': // 1 string to match.
		return Intrinsic::ptx_read_tid_w; // "tx.read.tid.w"
		case 'x': // 1 string to match.
		return Intrinsic::ptx_read_tid_x; // "tx.read.tid.x"
		case 'y': // 1 string to match.
		return Intrinsic::ptx_read_tid_y; // "tx.read.tid.y"
		case 'z': // 1 string to match.
		return Intrinsic::ptx_read_tid_z; // "tx.read.tid.z"
		}
		break;
		}
		break;
		case 14: // 12 strings to match.
		switch (NameR[0]) {
		default: break;
		case 'p': // 5 strings to match.
		if (NameR.substr(1, 10) != "c.altivec.")
		break;
		switch (NameR[11]) {
		default: break;
		case 'd': // 2 strings to match.
		if (NameR[12] != 's')
	break;	break;

	switch (NameR[12]) {	switch (NameR[13]) {
	default: break;	default: break;

	case 'd': // 1 string to match.	case 's': // 1 string to match.
	if (NameR.substr(13, 6) != "eclast")	return Intrinsic::ppc_altivec_dss; // "pc.altivec.dss"
	break;	case 't': // 1 string to match.
	return Intrinsic::x86_aesni_aesdeclast; // "86.aesni.aesdec	return Intrinsic::ppc_altivec_dst; // "pc.altivec.dst"
	last"
	case 'e': // 1 string to match.
	if (NameR.substr(13, 6) != "nclast")
	break;
	return Intrinsic::x86_aesni_aesenclast; // "86.aesni.aesenc
	last"
	}	}
	break;	break;

	case 'v': // 15 strings to match.	case 'l': // 1 string to match.
	if (NameR.substr(5, 2) != "x.")	if (NameR.substr(12, 2) != "vx")
	break;	break;

	switch (NameR[7]) {	return Intrinsic::ppc_altivec_lvx; // "pc.altivec.lvx"
		case 'v': // 2 strings to match.
		if (NameR[12] != 's')
		break;
		switch (NameR[13]) {
	default: break;	default: break;

	case 'b': // 2 strings to match.	case 'l': // 1 string to match.
	if (NameR.substr(8, 6) != "lend.p")	return Intrinsic::ppc_altivec_vsl; // "pc.altivec.vsl"
	break;	case 'r': // 1 string to match.
	switch (NameR[14]) {	return Intrinsic::ppc_altivec_vsr; // "pc.altivec.vsr"
	default: break;	}
	case 'd': // 1 string to match.	break;
	if (NameR.substr(15, 4) != ".256")	}
	break;	break;
	return Intrinsic::x86_avx_blend_pd_256; // "86.avx.blend.pd	case 't': // 7 strings to match.
	.256"	if (NameR.substr(1, 7) != "x.read.")
	case 's': // 1 string to match.	break;
	if (NameR.substr(15, 4) != ".256")	switch (NameR[8]) {
	break;	default: break;
	return Intrinsic::x86_avx_blend_ps_256; // "86.avx.blend.ps	case 'g': // 1 string to match.
	.256"	if (NameR.substr(9, 5) != "ridid")
	}
	break;	break;

	case 'l': // 3 strings to match.	return Intrinsic::ptx_read_gridid; // "tx.read.gridid"
	if (NameR.substr(8, 5) != "oadu.")	case 'l': // 1 string to match.
	break;	if (NameR.substr(9, 5) != "aneid")
	switch (NameR[13]) {
	default: break;
	case 'd': // 1 string to match.
	if (NameR.substr(14, 5) != "q.256")
	break;
	return Intrinsic::x86_avx_loadu_dq_256; // "86.avx.loadu.dq
	.256"
	case 'p': // 2 strings to match.
	switch (NameR[14]) {
	default: break;
	case 'd': // 1 string to match.
	if (NameR.substr(15, 4) != ".256")
	break;
	return Intrinsic::x86_avx_loadu_pd_256; // "86.avx.
	loadu.pd.256"
	case 's': // 1 string to match.
	if (NameR.substr(15, 4) != ".256")
	break;
	return Intrinsic::x86_avx_loadu_ps_256; // "86.avx.
	loadu.ps.256"
	}
	break;
	}
	break;
	case 'm': // 5 strings to match.
	switch (NameR[8]) {
	default: break;
	case 'a': // 2 strings to match.
	if (NameR.substr(9, 9) != "skstore.p")
	break;
	switch (NameR[18]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::x86_avx_maskstore_pd; // "86.avx.
	maskstore.pd"
	case 's': // 1 string to match.
	return Intrinsic::x86_avx_maskstore_ps; // "86.avx.
	maskstore.ps"
	}
	break;
	case 'o': // 3 strings to match.
	if (NameR.substr(9, 4) != "vnt.")
	break;
	switch (NameR[13]) {
	default: break;
	case 'd': // 1 string to match.
	if (NameR.substr(14, 5) != "q.256")
	break;
	return Intrinsic::x86_avx_movnt_dq_256; // "86.avx.
	movnt.dq.256"
	case 'p': // 2 strings to match.
	switch (NameR[14]) {
	default: break;
	case 'd': // 1 string to match.
	if (NameR.substr(15, 4) != ".256")
	break;
	return Intrinsic::x86_avx_movnt_pd_256; // "86.avx.
	movnt.pd.256"
	case 's': // 1 string to match.
	if (NameR.substr(15, 4) != ".256")
	break;
	return Intrinsic::x86_avx_movnt_ps_256; // "86.avx.
	movnt.ps.256"
	}
	break;
	}
	break;
	}
	break;	break;

	case 'p': // 1 string to match.	return Intrinsic::ptx_read_laneid; // "tx.read.laneid"
	if (NameR.substr(8, 11) != "testnzc.256")	case 'n': // 4 strings to match.
	break;	if (NameR.substr(9, 4) != "tid.")
	return Intrinsic::x86_avx_ptestnzc_256; // "86.avx.ptestnzc
	.256"
	case 'r': // 3 strings to match.
	switch (NameR[8]) {
	default: break;
	case 'o': // 2 strings to match.
	if (NameR.substr(9, 5) != "und.p")
	break;
	switch (NameR[14]) {
	default: break;
	case 'd': // 1 string to match.
	if (NameR.substr(15, 4) != ".256")
	break;
	return Intrinsic::x86_avx_round_pd_256; // "86.avx.
	round.pd.256"
	case 's': // 1 string to match.
	if (NameR.substr(15, 4) != ".256")
	break;
	return Intrinsic::x86_avx_round_ps_256; // "86.avx.
	round.ps.256"
	}
	break;
	case 's': // 1 string to match.
	if (NameR.substr(9, 10) != "qrt.ps.256")
	break;
	return Intrinsic::x86_avx_rsqrt_ps_256; // "86.avx.rsqrt.ps
	.256"
	}
	break;	break;

	case 'v': // 1 string to match.	switch (NameR[13]) {
	if (NameR.substr(8, 11) != "broadcastss")	default: break;
	break;	case 'w': // 1 string to match.
	return Intrinsic::x86_avx_vbroadcastss; // "86.avx.vbroadca	return Intrinsic::ptx_read_ntid_w; // "tx.read.ntid.w"
	stss"	case 'x': // 1 string to match.
		return Intrinsic::ptx_read_ntid_x; // "tx.read.ntid.x"
		case 'y': // 1 string to match.
		return Intrinsic::ptx_read_ntid_y; // "tx.read.ntid.y"
		case 'z': // 1 string to match.
		return Intrinsic::ptx_read_ntid_z; // "tx.read.ntid.z"
	}	}
	break;	break;

		case 'w': // 1 string to match.
		if (NameR.substr(9, 5) != "arpid")
		break;
		return Intrinsic::ptx_read_warpid; // "tx.read.warpid"
	}	}
	break;	break;

	case 's': // 10 strings to match.	}
	if (NameR[4] != 's')	break;
		case 15: // 23 strings to match.
		switch (NameR[0]) {
		default: break;
		case 'p': // 17 strings to match.
		if (NameR.substr(1, 10) != "c.altivec.")
	break;	break;

	switch (NameR[5]) {	switch (NameR[11]) {
	default: break;	default: break;

	case 'e': // 6 strings to match.	case 'd': // 1 string to match.
	switch (NameR[6]) {	if (NameR.substr(12, 3) != "stt")
		break;
		return Intrinsic::ppc_altivec_dstt; // "pc.altivec.dstt"
		case 'l': // 3 strings to match.
		if (NameR[12] != 'v')
		break;
		switch (NameR[13]) {
	default: break;	default: break;

	case '2': // 3 strings to match.	case 's': // 2 strings to match.
	if (NameR[7] != '.')	switch (NameR[14]) {
		default: break;
		case 'l': // 1 string to match.
		return Intrinsic::ppc_altivec_lvsl; // "pc.altivec.lvsl
		"
		case 'r': // 1 string to match.
		return Intrinsic::ppc_altivec_lvsr; // "pc.altivec.lvsr
		"
		}
		break;
		case 'x': // 1 string to match.
		if (NameR[14] != 'l')
	break;	break;

	switch (NameR[8]) {	return Intrinsic::ppc_altivec_lvxl; // "pc.altivec.lvxl
		"
		}
		break;
		case 's': // 1 string to match.
		if (NameR.substr(12, 3) != "tvx")
		break;
		return Intrinsic::ppc_altivec_stvx; // "pc.altivec.stvx"
		case 'v': // 12 strings to match.
		switch (NameR[12]) {
		default: break;
		case 'r': // 3 strings to match.
		if (NameR[13] != 'l')
		break;
		switch (NameR[14]) {
	default: break;	default: break;

	case 'c': // 1 string to match.	case 'b': // 1 string to match.
	if (NameR.substr(9, 10) != "vttsd2si64")	return Intrinsic::ppc_altivec_vrlb; // "pc.altivec.vrlb
	break;	"
	return Intrinsic::x86_sse2_cvttsd2si64; // "86.sse2.cvttsd2	case 'h': // 1 string to match.
	si64"	return Intrinsic::ppc_altivec_vrlh; // "pc.altivec.vrlh
	case 'm': // 1 string to match.	"
	if (NameR.substr(9, 10) != "askmov.dqu")	case 'w': // 1 string to match.
	break;	return Intrinsic::ppc_altivec_vrlw; // "pc.altivec.vrlw
	return Intrinsic::x86_sse2_maskmov_dqu; // "86.sse2.maskmov	"
	.dqu"
	case 'u': // 1 string to match.
	if (NameR.substr(9, 10) != "comineq.sd")
	break;
	return Intrinsic::x86_sse2_ucomineq_sd; // "86.sse2.ucomine
	q.sd"
	}	}
	break;	break;

	case '4': // 3 strings to match.	case 's': // 9 strings to match.
	switch (NameR[7]) {	switch (NameR[13]) {
	default: break;	default: break;

	case '1': // 1 string to match.	case 'e': // 1 string to match.
	if (NameR.substr(8, 11) != ".phminposuw")	if (NameR[14] != 'l')
	break;
	return Intrinsic::x86_sse41_phminposuw; // "86.sse41.phminp
	osuw"
	case '2': // 2 strings to match.
	if (NameR.substr(8, 7) != ".crc32.")
	break;	break;

	switch (NameR[15]) {	return Intrinsic::ppc_altivec_vsel; // "pc.altivec.vsel
		"
		case 'l': // 4 strings to match.
		switch (NameR[14]) {
	default: break;	default: break;

	case '3': // 1 string to match.	case 'b': // 1 string to match.
	if (NameR.substr(16, 3) != "2.8")	return Intrinsic::ppc_altivec_vslb; // "pc.altivec.vslb
	break;	"
	return Intrinsic::x86_sse42_crc32_32_8; // "86.sse4	case 'h': // 1 string to match.
	2.crc32.32.8"	return Intrinsic::ppc_altivec_vslh; // "pc.altivec.vslh
	case '6': // 1 string to match.	"
	if (NameR.substr(16, 3) != "4.8")	case 'o': // 1 string to match.
	break;	return Intrinsic::ppc_altivec_vslo; // "pc.altivec.vslo
	return Intrinsic::x86_sse42_crc32_64_8; // "86.sse4	"
	2.crc32.64.8"	case 'w': // 1 string to match.
		return Intrinsic::ppc_altivec_vslw; // "pc.altivec.vslw
		"
		}
		break;
		case 'r': // 4 strings to match.
		switch (NameR[14]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::ppc_altivec_vsrb; // "pc.altivec.vsrb
		"
		case 'h': // 1 string to match.
		return Intrinsic::ppc_altivec_vsrh; // "pc.altivec.vsrh
		"
		case 'o': // 1 string to match.
		return Intrinsic::ppc_altivec_vsro; // "pc.altivec.vsro
		"
		case 'w': // 1 string to match.
		return Intrinsic::ppc_altivec_vsrw; // "pc.altivec.vsrw
		"
	}	}
	break;	break;
	}	}
	break;	break;
	}	}
	break;	break;

	case 's': // 4 strings to match.	}
	if (NameR.substr(6, 4) != "e3.p")	break;
	break;	case 't': // 6 strings to match.
	switch (NameR[10]) {	if (NameR.substr(1, 7) != "x.read.")
		break;
		switch (NameR[8]) {
		default: break;
		case 'c': // 5 strings to match.
		switch (NameR[9]) {
	default: break;	default: break;

	case 'a': // 3 strings to match.	case 'l': // 1 string to match.
	if (NameR.substr(11, 3) != "bs.")	if (NameR.substr(10, 5) != "ock64")
		break;
		return Intrinsic::ptx_read_clock64; // "tx.read.clock64
		"
		case 't': // 4 strings to match.
		if (NameR.substr(10, 4) != "aid.")
	break;	break;
	switch (NameR[14]) {	switch (NameR[14]) {
	default: break;	default: break;

	case 'b': // 1 string to match.
	if (NameR.substr(15, 4) != ".128")
	break;
	return Intrinsic::x86_ssse3_pabs_b_128; // "86.ssse3.pabs.b
	.128"
	case 'd': // 1 string to match.
	if (NameR.substr(15, 4) != ".128")
	break;
	return Intrinsic::x86_ssse3_pabs_d_128; // "86.ssse3.pabs.d
	.128"
	case 'w': // 1 string to match.	case 'w': // 1 string to match.

	if (NameR.substr(15, 4) != ".128")	return Intrinsic::ptx_read_ctaid_w; // "tx.read.ctaid.w
	break;	"
	return Intrinsic::x86_ssse3_pabs_w_128; // "86.ssse3.pabs.w	case 'x': // 1 string to match.
	.128"	return Intrinsic::ptx_read_ctaid_x; // "tx.read.ctaid.x
		"
		case 'y': // 1 string to match.
		return Intrinsic::ptx_read_ctaid_y; // "tx.read.ctaid.y
		"
		case 'z': // 1 string to match.
		return Intrinsic::ptx_read_ctaid_z; // "tx.read.ctaid.z
		"
	}	}
	break;	break;

	case 'm': // 1 string to match.
	if (NameR.substr(11, 8) != "ul.hr.sw")
	break;
	return Intrinsic::x86_ssse3_pmul_hr_sw; // "86.ssse3.pmul.h
	r.sw"
	}	}
	break;	break;

		case 'n': // 1 string to match.
		if (NameR.substr(9, 6) != "warpid")
		break;
		return Intrinsic::ptx_read_nwarpid; // "tx.read.nwarpid"
	}	}
	break;	break;
	}	}
	break;	break;

	case 20: // 35 strings to match.	case 16: // 21 strings to match.
	if (NameR.substr(0, 3) != "86.")	switch (NameR[0]) {
	break;
	switch (NameR[3]) {
	default: break;	default: break;

	case 'a': // 19 strings to match.	case 'p': // 17 strings to match.
	if (NameR.substr(4, 3) != "vx.")	if (NameR.substr(1, 10) != "c.altivec.")
	break;	break;

	switch (NameR[7]) {	switch (NameR[11]) {
	default: break;	default: break;

	case 'a': // 2 strings to match.	case 'd': // 1 string to match.
	if (NameR.substr(8, 7) != "ddsub.p")	if (NameR.substr(12, 4) != "stst")
	break;	break;

	switch (NameR[15]) {	return Intrinsic::ppc_altivec_dstst; // "pc.altivec.dstst"
	default: break;	case 'l': // 3 strings to match.
	case 'd': // 1 string to match.	if (NameR.substr(12, 2) != "ve")
	if (NameR.substr(16, 4) != ".256")
	break;
	return Intrinsic::x86_avx_addsub_pd_256; // "86.avx.addsub.p
	d.256"
	case 's': // 1 string to match.
	if (NameR.substr(16, 4) != ".256")
	break;
	return Intrinsic::x86_avx_addsub_ps_256; // "86.avx.addsub.p
	s.256"
	}
	break;
	case 'b': // 2 strings to match.
	if (NameR.substr(8, 7) != "lendv.p")
	break;	break;

	switch (NameR[15]) {	switch (NameR[14]) {
	default: break;	default: break;

	case 'd': // 1 string to match.	case 'b': // 1 string to match.
	if (NameR.substr(16, 4) != ".256")	if (NameR[15] != 'x')
	break;	break;

	return Intrinsic::x86_avx_blendv_pd_256; // "86.avx.blendv.p	return Intrinsic::ppc_altivec_lvebx; // "pc.altivec.lveb
	d.256"	x"
	case 's': // 1 string to match.	case 'h': // 1 string to match.
	if (NameR.substr(16, 4) != ".256")	if (NameR[15] != 'x')
		break;
		return Intrinsic::ppc_altivec_lvehx; // "pc.altivec.lveh
		x"
		case 'w': // 1 string to match.
		if (NameR[15] != 'x')
	break;	break;

	return Intrinsic::x86_avx_blendv_ps_256; // "86.avx.blendv.p s.256"	return Intrinsic::ppc_altivec_lvewx; // "pc.altivec.lvew x"
	}	}
	break;	break;

	case 'c': // 4 strings to match.	case 's': // 1 string to match.
	if (NameR.substr(8, 2) != "vt")	if (NameR.substr(12, 4) != "tvxl")
	break;	break;

	switch (NameR[10]) {	return Intrinsic::ppc_altivec_stvxl; // "pc.altivec.stvxl"
		case 'v': // 12 strings to match.
		switch (NameR[12]) {
	default: break;	default: break;

	case '.': // 2 strings to match.	case 'c': // 2 strings to match.
	if (NameR[11] != 'p')	if (NameR[13] != 'f')
	break;	break;

	switch (NameR[12]) {	switch (NameR[14]) {
	default: break;	default: break;

	case 'd': // 1 string to match.
	if (NameR.substr(13, 7) != "2dq.256")
	break;
	return Intrinsic::x86_avx_cvt_pd2dq_256; // "86.avx.cvt.pd2d
	q.256"
	case 's': // 1 string to match.	case 's': // 1 string to match.

	if (NameR.substr(13, 7) != "2dq.256")	if (NameR[15] != 'x')
	break;
	return Intrinsic::x86_avx_cvt_ps2dq_256; // "86.avx.cvt.ps2d
	q.256"
	}
	break;
	case 'd': // 2 strings to match.
	if (NameR.substr(11, 4) != "q2.p")
	break;
	switch (NameR[15]) {
	default: break;
	case 'd': // 1 string to match.
	if (NameR.substr(16, 4) != ".256")
	break;	break;

	return Intrinsic::x86_avx_cvtdq2_pd_256; // "86.avx.cvtdq2.p	return Intrinsic::ppc_altivec_vcfsx; // "pc.altivec.vcfs
	d.256"	x"
	case 's': // 1 string to match.	case 'u': // 1 string to match.
	if (NameR.substr(16, 4) != ".256")	if (NameR[15] != 'x')
	break;	break;

	return Intrinsic::x86_avx_cvtdq2_ps_256; // "86.avx.cvtdq2.p s.256"	return Intrinsic::ppc_altivec_vcfux; // "pc.altivec.vcfu x"
	}	}
	break;	break;

	}
	break;
	case 'm': // 2 strings to match.
	if (NameR.substr(8, 7) != "ovmsk.p")
	break;
	switch (NameR[15]) {
	default: break;
	case 'd': // 1 string to match.
	if (NameR.substr(16, 4) != ".256")
	break;
	return Intrinsic::x86_avx_movmsk_pd_256; // "86.avx.movmsk.p
	d.256"
	case 's': // 1 string to match.
	if (NameR.substr(16, 4) != ".256")
	break;
	return Intrinsic::x86_avx_movmsk_ps_256; // "86.avx.movmsk.p
	s.256"
	}
	break;
	case 's': // 3 strings to match.
	if (NameR.substr(8, 6) != "toreu.")
	break;
	switch (NameR[14]) {
	default: break;
	case 'd': // 1 string to match.
	if (NameR.substr(15, 5) != "q.256")
	break;
	return Intrinsic::x86_avx_storeu_dq_256; // "86.avx.storeu.d
	q.256"
	case 'p': // 2 strings to match.	case 'p': // 2 strings to match.

	switch (NameR[15]) {	switch (NameR[13]) {
	default: break;	default: break;

	case 'd': // 1 string to match.	case 'e': // 1 string to match.
	if (NameR.substr(16, 4) != ".256")	if (NameR.substr(14, 2) != "rm")
	break;	break;

	return Intrinsic::x86_avx_storeu_pd_256; // "86.avx.storeu.p	return Intrinsic::ppc_altivec_vperm; // "pc.altivec.vper
	d.256"	m"
	case 's': // 1 string to match.	case 'k': // 1 string to match.
	if (NameR.substr(16, 4) != ".256")	if (NameR.substr(14, 2) != "px")
	break;	break;

	return Intrinsic::x86_avx_storeu_ps_256; // "86.avx.storeu.p	return Intrinsic::ppc_altivec_vpkpx; // "pc.altivec.vpkp
	s.256"	x"
	}
	break;
	}
	break;
	case 'v': // 6 strings to match.
	switch (NameR[8]) {
	default: break;
	case 'p': // 2 strings to match.
	if (NameR.substr(9, 10) != "ermilvar.p")
	break;
	switch (NameR[19]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::x86_avx_vpermilvar_pd; // "86.avx.vpermilv
	ar.pd"
	case 's': // 1 string to match.
	return Intrinsic::x86_avx_vpermilvar_ps; // "86.avx.vpermilv
	ar.ps"
	}	}
	break;	break;

	case 't': // 4 strings to match.	case 'r': // 5 strings to match.
	if (NameR.substr(9, 3) != "est")	switch (NameR[13]) {
	break;
	switch (NameR[12]) {
	default: break;	default: break;

	case 'c': // 2 strings to match.	case 'e': // 1 string to match.
	if (NameR.substr(13, 2) != ".p")	if (NameR.substr(14, 2) != "fp")
	break;	break;

	switch (NameR[15]) {	return Intrinsic::ppc_altivec_vrefp; // "pc.altivec.vref
	default: break;	p"
	case 'd': // 1 string to match.	case 'f': // 4 strings to match.
	if (NameR.substr(16, 4) != ".256")	if (NameR[14] != 'i')
	break;
	return Intrinsic::x86_avx_vtestc_pd_256; // "86.avx.
	vtestc.pd.256"
	case 's': // 1 string to match.
	if (NameR.substr(16, 4) != ".256")
	break;
	return Intrinsic::x86_avx_vtestc_ps_256; // "86.avx.
	vtestc.ps.256"
	}
	break;
	case 'z': // 2 strings to match.
	if (NameR.substr(13, 2) != ".p")
	break;	break;
	switch (NameR[15]) {	switch (NameR[15]) {
	default: break;	default: break;

	case 'd': // 1 string to match.	case 'm': // 1 string to match.
	if (NameR.substr(16, 4) != ".256")	return Intrinsic::ppc_altivec_vrfim; // "pc.altivec.vrfi
	break;	m"
	return Intrinsic::x86_avx_vtestz_pd_256; // "86.avx.	case 'n': // 1 string to match.
	vtestz.pd.256"	return Intrinsic::ppc_altivec_vrfin; // "pc.altivec.vrfi
	case 's': // 1 string to match.	n"
	if (NameR.substr(16, 4) != ".256")	case 'p': // 1 string to match.
	break;	return Intrinsic::ppc_altivec_vrfip; // "pc.altivec.vrfi
	return Intrinsic::x86_avx_vtestz_ps_256; // "86.avx.	p"
	vtestz.ps.256"	case 'z': // 1 string to match.
	}	return Intrinsic::ppc_altivec_vrfiz; // "pc.altivec.vrfi
	break;	z"
	}
	break;
	}
	break;
	}
	break;
	case 's': // 16 strings to match.
	if (NameR[4] != 's')
	break;
	switch (NameR[5]) {
	default: break;
	case 'e': // 7 strings to match.
	switch (NameR[6]) {
	default: break;
	case '2': // 4 strings to match.
	if (NameR.substr(7, 2) != ".p")
	break;
	switch (NameR[9]) {
	default: break;
	case 'a': // 3 strings to match.
	if (NameR.substr(10, 2) != "ck")
	break;
	switch (NameR[12]) {
	default: break;
	case 's': // 2 strings to match.
	if (NameR[13] != 's')
	break;
	switch (NameR[14]) {
	default: break;
	case 'd': // 1 string to match.
	if (NameR.substr(15, 5) != "w.128")
	break;
	return Intrinsic::x86_sse2_packssdw_128; // "86.sse2
	.packssdw.128"
	case 'w': // 1 string to match.
	if (NameR.substr(15, 5) != "b.128")
	break;
	return Intrinsic::x86_sse2_packsswb_128; // "86.sse2
	.packsswb.128"
	}
	break;
	case 'u': // 1 string to match.
	if (NameR.substr(13, 7) != "swb.128")
	break;
	return Intrinsic::x86_sse2_packuswb_128; // "86.sse2
	.packuswb.128"
	}	}
	break;	break;

	case 'm': // 1 string to match.
	if (NameR.substr(10, 10) != "ovmskb.128")
	break;
	return Intrinsic::x86_sse2_pmovmskb_128; // "86.sse2.pmovmsk
	b.128"
	}	}
	break;	break;

	case '4': // 3 strings to match.	case 's': // 3 strings to match.
	if (NameR.substr(7, 8) != "2.crc32.")	if (NameR.substr(13, 2) != "ra")
	break;	break;
	switch (NameR[15]) {	switch (NameR[15]) {
	default: break;	default: break;

	case '3': // 2 strings to match.	case 'b': // 1 string to match.
	if (NameR.substr(16, 2) != "2.")	return Intrinsic::ppc_altivec_vsrab; // "pc.altivec.vsra
	break;	b"
	switch (NameR[18]) {	case 'h': // 1 string to match.
	default: break;	return Intrinsic::ppc_altivec_vsrah; // "pc.altivec.vsra
	case '1': // 1 string to match.	h"
	if (NameR[19] != '6')	case 'w': // 1 string to match.
	break;	return Intrinsic::ppc_altivec_vsraw; // "pc.altivec.vsra
	return Intrinsic::x86_sse42_crc32_32_16; // "86.sse4	w"
	2.crc32.32.16"
	case '3': // 1 string to match.
	if (NameR[19] != '2')
	break;
	return Intrinsic::x86_sse42_crc32_32_32; // "86.sse4
	2.crc32.32.32"
	}
	break;
	case '6': // 1 string to match.
	if (NameR.substr(16, 4) != "4.64")
	break;
	return Intrinsic::x86_sse42_crc32_64_64; // "86.sse42.crc32.
	64.64"
	}	}
	break;	break;
	}	}
	break;	break;

	case 's': // 9 strings to match.	}
	if (NameR.substr(6, 4) != "e3.p")	break;
		case 't': // 4 strings to match.
		if (NameR.substr(1, 14) != "x.read.nctaid.")
		break;
		switch (NameR[15]) {
		default: break;
		case 'w': // 1 string to match.
		return Intrinsic::ptx_read_nctaid_w; // "tx.read.nctaid.w"
		case 'x': // 1 string to match.
		return Intrinsic::ptx_read_nctaid_x; // "tx.read.nctaid.x"
		case 'y': // 1 string to match.
		return Intrinsic::ptx_read_nctaid_y; // "tx.read.nctaid.y"
		case 'z': // 1 string to match.
		return Intrinsic::ptx_read_nctaid_z; // "tx.read.nctaid.z"
		}
		break;
		}
		break;
		case 17: // 29 strings to match.
		if (NameR.substr(0, 11) != "pc.altivec.")
		break;
		switch (NameR[11]) {
		default: break;
		case 'd': // 2 strings to match.
		if (NameR[12] != 's')
		break;
		switch (NameR[13]) {
		default: break;
		case 's': // 1 string to match.
		if (NameR.substr(14, 3) != "all")
	break;	break;

	switch (NameR[10]) {	return Intrinsic::ppc_altivec_dssall; // "pc.altivec.dssa
	default: break;	ll"
	case 'h': // 4 strings to match.	case 't': // 1 string to match.
	switch (NameR[11]) {	if (NameR.substr(14, 3) != "stt")
	default: break;	break;
	case 'a': // 2 strings to match.	return Intrinsic::ppc_altivec_dststt; // "pc.altivec.dsts
	if (NameR.substr(12, 3) != "dd.")	tt"
		}
		break;
		case 'm': // 2 strings to match.
		switch (NameR[12]) {
		default: break;
		case 'f': // 1 string to match.
		if (NameR.substr(13, 4) != "vscr")
		break;
		return Intrinsic::ppc_altivec_mfvscr; // "pc.altivec.mfvs
		cr"
		case 't': // 1 string to match.
		if (NameR.substr(13, 4) != "vscr")
		break;
		return Intrinsic::ppc_altivec_mtvscr; // "pc.altivec.mtvs
		cr"
		}
		break;
		case 's': // 3 strings to match.
		if (NameR.substr(12, 3) != "tve")
		break;
		switch (NameR[15]) {
		default: break;
		case 'b': // 1 string to match.
		if (NameR[16] != 'x')
		break;
		return Intrinsic::ppc_altivec_stvebx; // "pc.altivec.stve
		bx"
		case 'h': // 1 string to match.
		if (NameR[16] != 'x')
		break;
		return Intrinsic::ppc_altivec_stvehx; // "pc.altivec.stve
		hx"
		case 'w': // 1 string to match.
		if (NameR[16] != 'x')
		break;
		return Intrinsic::ppc_altivec_stvewx; // "pc.altivec.stve
		wx"
		}
		break;
		case 'v': // 22 strings to match.
		switch (NameR[12]) {
		default: break;
		case 'a': // 6 strings to match.
		if (NameR.substr(13, 2) != "vg")
		break;
		switch (NameR[15]) {
		default: break;
		case 's': // 3 strings to match.
		switch (NameR[16]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::ppc_altivec_vavgsb; // "pc.altivec.vavg
		sb"
		case 'h': // 1 string to match.
		return Intrinsic::ppc_altivec_vavgsh; // "pc.altivec.vavg
		sh"
		case 'w': // 1 string to match.
		return Intrinsic::ppc_altivec_vavgsw; // "pc.altivec.vavg
		sw"
		}
		break;
		case 'u': // 3 strings to match.
		switch (NameR[16]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::ppc_altivec_vavgub; // "pc.altivec.vavg
		ub"
		case 'h': // 1 string to match.
		return Intrinsic::ppc_altivec_vavguh; // "pc.altivec.vavg
		uh"
		case 'w': // 1 string to match.
		return Intrinsic::ppc_altivec_vavguw; // "pc.altivec.vavg
		uw"
		}
		break;
		}
		break;
		case 'c': // 2 strings to match.
		if (NameR[13] != 't')
		break;
		switch (NameR[14]) {
		default: break;
		case 's': // 1 string to match.
		if (NameR.substr(15, 2) != "xs")
		break;
		return Intrinsic::ppc_altivec_vctsxs; // "pc.altivec.vcts
		xs"
		case 'u': // 1 string to match.
		if (NameR.substr(15, 2) != "xs")
		break;
		return Intrinsic::ppc_altivec_vctuxs; // "pc.altivec.vctu
		xs"
		}
		break;
		case 'm': // 14 strings to match.
		switch (NameR[13]) {
		default: break;
		case 'a': // 7 strings to match.
		if (NameR[14] != 'x')
		break;
		switch (NameR[15]) {
		default: break;
		case 'f': // 1 string to match.
		if (NameR[16] != 'p')
	break;	break;

	switch (NameR[15]) {	return Intrinsic::ppc_altivec_vmaxfp; // "pc.altivec.vmax
		fp"
		case 's': // 3 strings to match.
		switch (NameR[16]) {
	default: break;	default: break;

	case 'd': // 1 string to match.	case 'b': // 1 string to match.
	if (NameR.substr(16, 4) != ".128")	return Intrinsic::ppc_altivec_vmaxsb; // "pc.altivec.vmax
	break;	sb"
	return Intrinsic::x86_ssse3_phadd_d_128; // "86.ssse	case 'h': // 1 string to match.
	3.phadd.d.128"	return Intrinsic::ppc_altivec_vmaxsh; // "pc.altivec.vmax
		sh"
	case 'w': // 1 string to match.	case 'w': // 1 string to match.

	if (NameR.substr(16, 4) != ".128")	return Intrinsic::ppc_altivec_vmaxsw; // "pc.altivec.vmax
	break;	sw"
	return Intrinsic::x86_ssse3_phadd_w_128; // "86.ssse
	3.phadd.w.128"
	}	}
	break;	break;

	case 's': // 2 strings to match.	case 'u': // 3 strings to match.
	if (NameR.substr(12, 3) != "ub.")	switch (NameR[16]) {
	break;
	switch (NameR[15]) {
	default: break;	default: break;

	case 'd': // 1 string to match.	case 'b': // 1 string to match.
	if (NameR.substr(16, 4) != ".128")	return Intrinsic::ppc_altivec_vmaxub; // "pc.altivec.vmax
	break;	ub"
	return Intrinsic::x86_ssse3_phsub_d_128; // "86.ssse	case 'h': // 1 string to match.
	3.phsub.d.128"	return Intrinsic::ppc_altivec_vmaxuh; // "pc.altivec.vmax
		uh"
	case 'w': // 1 string to match.	case 'w': // 1 string to match.

	if (NameR.substr(16, 4) != ".128")	return Intrinsic::ppc_altivec_vmaxuw; // "pc.altivec.vmax
	break;	uw"
	return Intrinsic::x86_ssse3_phsub_w_128; // "86.ssse
	3.phsub.w.128"
	}	}
	break;	break;
	}	}
	break;	break;

	case 'm': // 1 string to match.	case 'i': // 7 strings to match.
	if (NameR.substr(11, 9) != "add.ub.sw")	if (NameR[14] != 'n')
	break;	break;

	return Intrinsic::x86_ssse3_pmadd_ub_sw; // "86.ssse3.pmadd.	switch (NameR[15]) {
	ub.sw"
	case 's': // 4 strings to match.
	switch (NameR[11]) {
	default: break;	default: break;

	case 'h': // 1 string to match.	case 'f': // 1 string to match.
	if (NameR.substr(12, 8) != "uf.b.128")	if (NameR[16] != 'p')
	break;
	return Intrinsic::x86_ssse3_pshuf_b_128; // "86.ssse3.pshuf.
	b.128"
	case 'i': // 3 strings to match.
	if (NameR.substr(12, 3) != "gn.")
	break;	break;

	switch (NameR[15]) {	return Intrinsic::ppc_altivec_vminfp; // "pc.altivec.vmin
		fp"
		case 's': // 3 strings to match.
		switch (NameR[16]) {
	default: break;	default: break;
	case 'b': // 1 string to match.	case 'b': // 1 string to match.

	if (NameR.substr(16, 4) != ".128")	return Intrinsic::ppc_altivec_vminsb; // "pc.altivec.vmin
	break;	sb"
	return Intrinsic::x86_ssse3_psign_b_128; // "86.ssse	case 'h': // 1 string to match.
	3.psign.b.128"	return Intrinsic::ppc_altivec_vminsh; // "pc.altivec.vmin
	case 'd': // 1 string to match.	sh"
	if (NameR.substr(16, 4) != ".128")
	break;
	return Intrinsic::x86_ssse3_psign_d_128; // "86.ssse
	3.psign.d.128"
	case 'w': // 1 string to match.	case 'w': // 1 string to match.

	if (NameR.substr(16, 4) != ".128")	return Intrinsic::ppc_altivec_vminsw; // "pc.altivec.vmin
	break;	sw"
	return Intrinsic::x86_ssse3_psign_w_128; // "86.ssse	}
	3.psign.w.128"	break;
		case 'u': // 3 strings to match.
		switch (NameR[16]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::ppc_altivec_vminub; // "pc.altivec.vmin
		ub"
		case 'h': // 1 string to match.
		return Intrinsic::ppc_altivec_vminuh; // "pc.altivec.vmin
		uh"
		case 'w': // 1 string to match.
		return Intrinsic::ppc_altivec_vminuw; // "pc.altivec.vmin
		uw"
	}	}
	break;	break;
	}	}
	break;	break;
	}	}
	break;	break;
	}	}
	break;	break;
	}	}
	break;	break;

	case 21: // 12 strings to match.	case 18: // 38 strings to match.
	if (NameR.substr(0, 3) != "86.")	if (NameR.substr(0, 12) != "pc.altivec.v")
	break;	break;

	switch (NameR[3]) {	switch (NameR[12]) {
	default: break;	default: break;

	case 'a': // 6 strings to match.	case 'a': // 7 strings to match.
	if (NameR.substr(4, 3) != "vx.")	if (NameR.substr(13, 2) != "dd")
	break;	break;

	switch (NameR[7]) {	switch (NameR[15]) {
	default: break;	default: break;

	case 'c': // 4 strings to match.	case 'c': // 1 string to match.
	if (NameR.substr(8, 2) != "vt")	if (NameR.substr(16, 2) != "uw")
	break;	break;

	switch (NameR[10]) {	return Intrinsic::ppc_altivec_vaddcuw; // "pc.altivec.vadd
		cuw"
		case 's': // 3 strings to match.
		switch (NameR[16]) {
	default: break;	default: break;

	case '.': // 2 strings to match.	case 'b': // 1 string to match.
	if (NameR[11] != 'p')	if (NameR[17] != 's')
	break;	break;

	switch (NameR[12]) {	return Intrinsic::ppc_altivec_vaddsbs; // "pc.altivec.vadd
	default: break;	sbs"
	case 'd': // 1 string to match.	case 'h': // 1 string to match.
	if (NameR.substr(13, 8) != "2.ps.256")	if (NameR[17] != 's')
	break;
	return Intrinsic::x86_avx_cvt_pd2_ps_256; // "86.avx.
	cvt.pd2.ps.256"
	case 's': // 1 string to match.
	if (NameR.substr(13, 8) != "2.pd.256")
	break;
	return Intrinsic::x86_avx_cvt_ps2_pd_256; // "86.avx.
	cvt.ps2.pd.256"
	}
	break;
	case 't': // 2 strings to match.
	if (NameR.substr(11, 2) != ".p")
	break;	break;

	switch (NameR[13]) {	return Intrinsic::ppc_altivec_vaddshs; // "pc.altivec.vadd
	default: break;	shs"
	case 'd': // 1 string to match.	case 'w': // 1 string to match.
	if (NameR.substr(14, 7) != "2dq.256")	if (NameR[17] != 's')
	break;	break;
	return Intrinsic::x86_avx_cvtt_pd2dq_256; // "86.avx.	return Intrinsic::ppc_altivec_vaddsws; // "pc.altivec.vadd
	cvtt.pd2dq.256"	sws"
	case 's': // 1 string to match.
	if (NameR.substr(14, 7) != "2dq.256")
	break;
	return Intrinsic::x86_avx_cvtt_ps2dq_256; // "86.avx.
	cvtt.ps2dq.256"
	}
	break;
	}	}
	break;	break;

	case 'v': // 2 strings to match.	case 'u': // 3 strings to match.
	if (NameR.substr(8, 8) != "permil.p")
	break;
	switch (NameR[16]) {	switch (NameR[16]) {
	default: break;	default: break;

	case 'd': // 1 string to match.	case 'b': // 1 string to match.
	if (NameR.substr(17, 4) != ".256")	if (NameR[17] != 's')
	break;	break;

	return Intrinsic::x86_avx_vpermil_pd_256; // "86.avx.vpermil.	return Intrinsic::ppc_altivec_vaddubs; // "pc.altivec.vadd
	pd.256"	ubs"
	case 's': // 1 string to match.	case 'h': // 1 string to match.
	if (NameR.substr(17, 4) != ".256")	if (NameR[17] != 's')
		break;
		return Intrinsic::ppc_altivec_vadduhs; // "pc.altivec.vadd
		uhs"
		case 'w': // 1 string to match.
		if (NameR[17] != 's')
	break;	break;

	return Intrinsic::x86_avx_vpermil_ps_256; // "86.avx.vpermil. ps.256"	return Intrinsic::ppc_altivec_vadduws; // "pc.altivec.vadd uws"
	}	}
	break;	break;
	}	}
	break;	break;

	case 's': // 6 strings to match.	case 'c': // 1 string to match.
	if (NameR[4] != 's')	if (NameR.substr(13, 5) != "mpbfp")
	break;	break;

	switch (NameR[5]) {	return Intrinsic::ppc_altivec_vcmpbfp; // "pc.altivec.vcmpbfp"
		case 'l': // 1 string to match.
		if (NameR.substr(13, 5) != "ogefp")
		break;
		return Intrinsic::ppc_altivec_vlogefp; // "pc.altivec.vlogefp"
		case 'm': // 9 strings to match.
		switch (NameR[13]) {
	default: break;	default: break;

	case 'e': // 4 strings to match.	case 'a': // 1 string to match.
	if (NameR.substr(6, 7) != "42.pcmp")	if (NameR.substr(14, 4) != "ddfp")
	break;	break;

	switch (NameR[13]) {	return Intrinsic::ppc_altivec_vmaddfp; // "pc.altivec.vmad
	default: break;	dfp"
	case 'e': // 2 strings to match.	case 'u': // 8 strings to match.
	if (NameR.substr(14, 3) != "str")	if (NameR[14] != 'l')
		break;
		switch (NameR[15]) {
		default: break;
		case 'e': // 4 strings to match.
		switch (NameR[16]) {
		default: break;
		case 's': // 2 strings to match.
		switch (NameR[17]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::ppc_altivec_vmulesb; // "pc.altivec.vmul
		esb"
		case 'h': // 1 string to match.
		return Intrinsic::ppc_altivec_vmulesh; // "pc.altivec.vmul
		esh"
		}
	break;	break;

	switch (NameR[17]) {	case 'u': // 2 strings to match.
		switch (NameR[17]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::ppc_altivec_vmuleub; // "pc.altivec.vmul
		eub"
		case 'h': // 1 string to match.
		return Intrinsic::ppc_altivec_vmuleuh; // "pc.altivec.vmul
		euh"
		}
		break;
		}
		break;
		case 'o': // 4 strings to match.
		switch (NameR[16]) {
	default: break;	default: break;

	case 'i': // 1 string to match.	case 's': // 2 strings to match.
	if (NameR.substr(18, 3) != "128")	switch (NameR[17]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::ppc_altivec_vmulosb; // "pc.altivec.vmul
		osb"
		case 'h': // 1 string to match.
		return Intrinsic::ppc_altivec_vmulosh; // "pc.altivec.vmul
		osh"
		}
		break;
		case 'u': // 2 strings to match.
		switch (NameR[17]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::ppc_altivec_vmuloub; // "pc.altivec.vmul
		oub"
		case 'h': // 1 string to match.
		return Intrinsic::ppc_altivec_vmulouh; // "pc.altivec.vmul
		ouh"
		}
		break;
		}
		break;
		}
		break;
		}
		break;
		case 'p': // 6 strings to match.
		if (NameR[13] != 'k')
		break;
		switch (NameR[14]) {
		default: break;
		case 's': // 4 strings to match.
		switch (NameR[15]) {
		default: break;
		case 'h': // 2 strings to match.
		switch (NameR[16]) {
		default: break;
		case 's': // 1 string to match.
		if (NameR[17] != 's')
	break;	break;

	return Intrinsic::x86_sse42_pcmpestri128; // "86.sse4	return Intrinsic::ppc_altivec_vpkshss; // "pc.altivec.vpks
	2.pcmpestri128"	hss"
	case 'm': // 1 string to match.	case 'u': // 1 string to match.
	if (NameR.substr(18, 3) != "128")	if (NameR[17] != 's')
	break;	break;

	return Intrinsic::x86_sse42_pcmpestrm128; // "86.sse4 2.pcmpestrm128"	return Intrinsic::ppc_altivec_vpkshus; // "pc.altivec.vpks hus"
	}	}
	break;	break;

	case 'i': // 2 strings to match.	case 'w': // 2 strings to match.
	if (NameR.substr(14, 3) != "str")	switch (NameR[16]) {
	break;
	switch (NameR[17]) {
	default: break;	default: break;

	case 'i': // 1 string to match.	case 's': // 1 string to match.
	if (NameR.substr(18, 3) != "128")	if (NameR[17] != 's')
	break;	break;

	return Intrinsic::x86_sse42_pcmpistri128; // "86.sse4	return Intrinsic::ppc_altivec_vpkswss; // "pc.altivec.vpks
	2.pcmpistri128"	wss"
	case 'm': // 1 string to match.	case 'u': // 1 string to match.
	if (NameR.substr(18, 3) != "128")	if (NameR[17] != 's')
	break;	break;

	return Intrinsic::x86_sse42_pcmpistrm128; // "86.sse4 2.pcmpistrm128"	return Intrinsic::ppc_altivec_vpkswus; // "pc.altivec.vpks wus"
	}	}
	break;	break;
	}	}
	break;	break;

	case 's': // 2 strings to match.	case 'u': // 2 strings to match.
	if (NameR.substr(6, 5) != "e3.ph")	switch (NameR[15]) {
	break;
	switch (NameR[11]) {
	default: break;	default: break;

	case 'a': // 1 string to match.	case 'h': // 1 string to match.
	if (NameR.substr(12, 9) != "dd.sw.128")	if (NameR.substr(16, 2) != "us")
	break;	break;

	return Intrinsic::x86_ssse3_phadd_sw_128; // "86.ssse3.phadd.	return Intrinsic::ppc_altivec_vpkuhus; // "pc.altivec.vpku
	sw.128"	hus"
	case 's': // 1 string to match.	case 'w': // 1 string to match.
	if (NameR.substr(12, 9) != "ub.sw.128")	if (NameR.substr(16, 2) != "us")
	break;	break;

	return Intrinsic::x86_ssse3_phsub_sw_128; // "86.ssse3.phsub. sw.128"	return Intrinsic::ppc_altivec_vpkuwus; // "pc.altivec.vpku wus"
	}	}
	break;	break;
	}	}
	break;	break;

	}	case 's': // 8 strings to match.
	break;	if (NameR[13] != 'u')
	case 22: // 14 strings to match.
	if (NameR.substr(0, 3) != "86.")
	break;
	switch (NameR[3]) {
	default: break;
	case 'a': // 4 strings to match.
	if (NameR.substr(4, 3) != "vx.")
	break;	break;

	switch (NameR[7]) {	switch (NameR[14]) {
	default: break;	default: break;

	case 'm': // 2 strings to match.	case 'b': // 7 strings to match.
	if (NameR.substr(8, 9) != "askload.p")	switch (NameR[15]) {
	break;
	switch (NameR[17]) {
	default: break;	default: break;

	case 'd': // 1 string to match.	case 'c': // 1 string to match.
	if (NameR.substr(18, 4) != ".256")	if (NameR.substr(16, 2) != "uw")
	break;
	return Intrinsic::x86_avx_maskload_pd_256; // "86.avx.maskload
	.pd.256"
	case 's': // 1 string to match.
	if (NameR.substr(18, 4) != ".256")
	break;	break;

	return Intrinsic::x86_avx_maskload_ps_256; // "86.avx.maskload	return Intrinsic::ppc_altivec_vsubcuw; // "pc.altivec.vsub
	.ps.256"	cuw"
		case 's': // 3 strings to match.
		switch (NameR[16]) {
		default: break;
		case 'b': // 1 string to match.
		if (NameR[17] != 's')
		break;
		return Intrinsic::ppc_altivec_vsubsbs; // "pc.altivec.vsub
		sbs"
		case 'h': // 1 string to match.
		if (NameR[17] != 's')
		break;
		return Intrinsic::ppc_altivec_vsubshs; // "pc.altivec.vsub
		shs"
		case 'w': // 1 string to match.
		if (NameR[17] != 's')
		break;
		return Intrinsic::ppc_altivec_vsubsws; // "pc.altivec.vsub
		sws"
		}
		break;
		case 'u': // 3 strings to match.
		switch (NameR[16]) {
		default: break;
		case 'b': // 1 string to match.
		if (NameR[17] != 's')
		break;
		return Intrinsic::ppc_altivec_vsububs; // "pc.altivec.vsub
		ubs"
		case 'h': // 1 string to match.
		if (NameR[17] != 's')
		break;
		return Intrinsic::ppc_altivec_vsubuhs; // "pc.altivec.vsub
		uhs"
		case 'w': // 1 string to match.
		if (NameR[17] != 's')
		break;
		return Intrinsic::ppc_altivec_vsubuws; // "pc.altivec.vsub
		uws"
		}
		break;
	}	}
	break;	break;

	case 'v': // 2 strings to match.	case 'm': // 1 string to match.
	if (NameR.substr(8, 9) != "testnzc.p")	if (NameR.substr(15, 3) != "sws")
	break;	break;

	switch (NameR[17]) {	return Intrinsic::ppc_altivec_vsumsws; // "pc.altivec.vsum
		sws"
		}
		break;
		case 'u': // 6 strings to match.
		if (NameR.substr(13, 2) != "pk")
		break;
		switch (NameR[15]) {
		default: break;
		case 'h': // 3 strings to match.
		switch (NameR[16]) {
	default: break;	default: break;

	case 'd': // 1 string to match.	case 'p': // 1 string to match.
	if (NameR.substr(18, 4) != ".256")	if (NameR[17] != 'x')
	break;	break;

	return Intrinsic::x86_avx_vtestnzc_pd_256; // "86.avx.vtestnzc	return Intrinsic::ppc_altivec_vupkhpx; // "pc.altivec.vupk
	.pd.256"	hpx"
	case 's': // 1 string to match.	case 's': // 2 strings to match.
	if (NameR.substr(18, 4) != ".256")	switch (NameR[17]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::ppc_altivec_vupkhsb; // "pc.altivec.vupk
		hsb"
		case 'h': // 1 string to match.
		return Intrinsic::ppc_altivec_vupkhsh; // "pc.altivec.vupk
		hsh"
		}
		break;
		}
		break;
		case 'l': // 3 strings to match.
		switch (NameR[16]) {
		default: break;
		case 'p': // 1 string to match.
		if (NameR[17] != 'x')
	break;	break;

	return Intrinsic::x86_avx_vtestnzc_ps_256; // "86.avx.vtestnzc	return Intrinsic::ppc_altivec_vupklpx; // "pc.altivec.vupk
	.ps.256"	lpx"
		case 's': // 2 strings to match.
		switch (NameR[17]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::ppc_altivec_vupklsb; // "pc.altivec.vupk
		lsb"
		case 'h': // 1 string to match.
		return Intrinsic::ppc_altivec_vupklsh; // "pc.altivec.vupk
		lsh"
		}
		break;
	}	}
	break;	break;
	}	}
	break;	break;

	case 's': // 10 strings to match.	}
	if (NameR.substr(4, 9) != "se42.pcmp")	break;
		case 19: // 29 strings to match.
		switch (NameR[0]) {
		default: break;
		case 'p': // 24 strings to match.
		if (NameR.substr(1, 11) != "c.altivec.v")
	break;	break;

	switch (NameR[13]) {	switch (NameR[12]) {
	default: break;	default: break;

	case 'e': // 5 strings to match.	case 'c': // 12 strings to match.
	if (NameR.substr(14, 4) != "stri")	if (NameR.substr(13, 2) != "mp")
	break;	break;

	switch (NameR[18]) {	switch (NameR[15]) {
	default: break;	default: break;

	case 'a': // 1 string to match.	case 'e': // 4 strings to match.
	if (NameR.substr(19, 3) != "128")	if (NameR[16] != 'q')
	break;
	return Intrinsic::x86_sse42_pcmpestria128; // "86.sse42.pcmpes
	tria128"
	case 'c': // 1 string to match.
	if (NameR.substr(19, 3) != "128")
	break;
	return Intrinsic::x86_sse42_pcmpestric128; // "86.sse42.pcmpes
	tric128"
	case 'o': // 1 string to match.
	if (NameR.substr(19, 3) != "128")
	break;
	return Intrinsic::x86_sse42_pcmpestrio128; // "86.sse42.pcmpes
	trio128"
	case 's': // 1 string to match.
	if (NameR.substr(19, 3) != "128")
	break;	break;

	return Intrinsic::x86_sse42_pcmpestris128; // "86.sse42.pcmpes	switch (NameR[17]) {
	tris128"	default: break;
	case 'z': // 1 string to match.	case 'f': // 1 string to match.
	if (NameR.substr(19, 3) != "128")	if (NameR[18] != 'p')
		break;
		return Intrinsic::ppc_altivec_vcmpeqfp; // "pc.altivec.vcmp
		eqfp"
		case 'u': // 3 strings to match.
		switch (NameR[18]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::ppc_altivec_vcmpequb; // "pc.alti
		vec.vcmpequb"
		case 'h': // 1 string to match.
		return Intrinsic::ppc_altivec_vcmpequh; // "pc.alti
		vec.vcmpequh"
		case 'w': // 1 string to match.
		return Intrinsic::ppc_altivec_vcmpequw; // "pc.alti
		vec.vcmpequw"
		}
	break;	break;

	return Intrinsic::x86_sse42_pcmpestriz128; // "86.sse42.pcmpes	}
	triz128"
	}
	break;
	case 'i': // 5 strings to match.
	if (NameR.substr(14, 4) != "stri")
	break;	break;

	switch (NameR[18]) {	case 'g': // 8 strings to match.
	default: break;	switch (NameR[16]) {
	case 'a': // 1 string to match.	default: break;
	if (NameR.substr(19, 3) != "128")	case 'e': // 1 string to match.
	break;	if (NameR.substr(17, 2) != "fp")
	return Intrinsic::x86_sse42_pcmpistria128; // "86.sse42.pcmpis	break;
	tria128"	return Intrinsic::ppc_altivec_vcmpgefp; // "pc.altivec.vcmp
	case 'c': // 1 string to match.	gefp"
	if (NameR.substr(19, 3) != "128")	case 't': // 7 strings to match.
	break;	switch (NameR[17]) {
	return Intrinsic::x86_sse42_pcmpistric128; // "86.sse42.pcmpis	default: break;
	tric128"	case 'f': // 1 string to match.
	case 'o': // 1 string to match.	if (NameR[18] != 'p')
	if (NameR.substr(19, 3) != "128")	break;
	break;	return Intrinsic::ppc_altivec_vcmpgtfp; // "pc.alti
	return Intrinsic::x86_sse42_pcmpistrio128; // "86.sse42.pcmpis	vec.vcmpgtfp"
	trio128"	case 's': // 3 strings to match.
	case 's': // 1 string to match.	switch (NameR[18]) {
	if (NameR.substr(19, 3) != "128")	default: break;
	break;	case 'b': // 1 string to match.
	return Intrinsic::x86_sse42_pcmpistris128; // "86.sse42.pcmpis	return Intrinsic::ppc_altivec_vcmpgtsb; // "pc.alti
	tris128"	vec.vcmpgtsb"
	case 'z': // 1 string to match.	case 'h': // 1 string to match.
	if (NameR.substr(19, 3) != "128")	return Intrinsic::ppc_altivec_vcmpgtsh; // "pc.alti
		vec.vcmpgtsh"
		case 'w': // 1 string to match.
		return Intrinsic::ppc_altivec_vcmpgtsw; // "pc.alti
		vec.vcmpgtsw"
		}
		break;
		case 'u': // 3 strings to match.
		switch (NameR[18]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::ppc_altivec_vcmpgtub; // "pc.alti
		vec.vcmpgtub"
		case 'h': // 1 string to match.
		return Intrinsic::ppc_altivec_vcmpgtuh; // "pc.alti
		vec.vcmpgtuh"
		case 'w': // 1 string to match.
		return Intrinsic::ppc_altivec_vcmpgtuw; // "pc.alti
		vec.vcmpgtuw"
		}
		break;
		}
	break;	break;

	return Intrinsic::x86_sse42_pcmpistriz128; // "86.sse42.pcmpis	}
	triz128"
	}
	break;
	}
	break;
	}
	break;
	case 23: // 4 strings to match.
	if (NameR.substr(0, 3) != "86.")
	break;
	switch (NameR[3]) {
	default: break;
	case 'a': // 3 strings to match.
	if (NameR.substr(4, 3) != "vx.")
	break;
	switch (NameR[7]) {
	default: break;
	case 'm': // 2 strings to match.
	if (NameR.substr(8, 10) != "askstore.p")
	break;	break;

	switch (NameR[18]) {
	default: break;
	case 'd': // 1 string to match.
	if (NameR.substr(19, 4) != ".256")
	break;
	return Intrinsic::x86_avx_maskstore_pd_256; // "86.avx.
	maskstore.pd.256"
	case 's': // 1 string to match.
	if (NameR.substr(19, 4) != ".256")
	break;
	return Intrinsic::x86_avx_maskstore_ps_256; // "86.avx.
	maskstore.ps.256"
	}	}
	break;	break;

	case 'v': // 1 string to match.
	if (NameR.substr(8, 15) != "broadcastss.256")
	break;
	return Intrinsic::x86_avx_vbroadcastss_256; // "86.avx.vbroadca
	stss.256"
	}
	break;
	case 's': // 1 string to match.
	if (NameR.substr(4, 19) != "sse3.pmul.hr.sw.128")
	break;
	return Intrinsic::x86_ssse3_pmul_hr_sw_128; // "86.ssse3.pmul.h
	r.sw.128"
	}
	break;
	case 24: // 8 strings to match.
	if (NameR.substr(0, 3) != "86.")
	break;
	switch (NameR[3]) {
	default: break;
	case 'a': // 7 strings to match.
	switch (NameR[4]) {
	default: break;
	case 'e': // 1 string to match.	case 'e': // 1 string to match.

	if (NameR.substr(5, 19) != "sni.aeskeygenassist")	if (NameR.substr(13, 6) != "xptefp")
	break;	break;

	return Intrinsic::x86_aesni_aeskeygenassist; // "86.aesni.aeskey	return Intrinsic::ppc_altivec_vexptefp; // "pc.altivec.vexp
	genassist"	tefp"
	case 'v': // 6 strings to match.	case 'm': // 6 strings to match.
	if (NameR.substr(5, 3) != "x.v")	if (NameR.substr(13, 3) != "sum")
	break;	break;

	switch (NameR[8]) {	switch (NameR[16]) {
	default: break;	default: break;

	case 'b': // 1 string to match.	case 'm': // 1 string to match.
	if (NameR.substr(9, 15) != "roadcast.sd.256")	if (NameR.substr(17, 2) != "bm")
	break;	break;

	return Intrinsic::x86_avx_vbroadcast_sd_256; // "86.avx.	return Intrinsic::ppc_altivec_vmsummbm; // "pc.altivec.vmsu
	vbroadcast.sd.256"	mmbm"
	case 'p': // 5 strings to match.	case 's': // 2 strings to match.
	if (NameR.substr(9, 3) != "erm")	if (NameR[17] != 'h')
	break;	break;

	switch (NameR[12]) {	switch (NameR[18]) {
		default: break;
		case 'm': // 1 string to match.
		return Intrinsic::ppc_altivec_vmsumshm; // "pc.altivec.vmsu
		mshm"
		case 's': // 1 string to match.
		return Intrinsic::ppc_altivec_vmsumshs; // "pc.altivec.vmsu
		mshs"
		}
		break;
		case 'u': // 3 strings to match.
		switch (NameR[17]) {
	default: break;	default: break;

	case '2': // 3 strings to match.	case 'b': // 1 string to match.
	if (NameR.substr(13, 5) != "f128.")	if (NameR[18] != 'm')
	break;	break;

		return Intrinsic::ppc_altivec_vmsumubm; // "pc.altivec.vmsu
		mubm"
		case 'h': // 2 strings to match.
	switch (NameR[18]) {	switch (NameR[18]) {
	default: break;	default: break;

	case 'p': // 2 strings to match.	case 'm': // 1 string to match.
	switch (NameR[19]) {	return Intrinsic::ppc_altivec_vmsumuhm; // "pc.alti
	default: break;	vec.vmsumuhm"
	case 'd': // 1 string to match.
	if (NameR.substr(20, 4) != ".256")
	break;
	return Intrinsic::x86_avx_vperm2f128_pd_256; // "86.avx.
	vperm2f128.pd.256"
	case 's': // 1 string to match.
	if (NameR.substr(20, 4) != ".256")
	break;
	return Intrinsic::x86_avx_vperm2f128_ps_256; // "86.avx.
	vperm2f128.ps.256"
	}
	break;
	case 's': // 1 string to match.	case 's': // 1 string to match.

	if (NameR.substr(19, 5) != "i.256")	return Intrinsic::ppc_altivec_vmsumuhs; // "pc.alti
	break;	vec.vmsumuhs"
	return Intrinsic::x86_avx_vperm2f128_si_256; // "86.avx.
	vperm2f128.si.256"
	}	}
	break;	break;

	case 'i': // 2 strings to match.	}
	if (NameR.substr(13, 6) != "lvar.p")	break;
	break;	}
	switch (NameR[19]) {	break;
		case 'n': // 1 string to match.
		if (NameR.substr(13, 6) != "msubfp")
		break;
		return Intrinsic::ppc_altivec_vnmsubfp; // "pc.altivec.vnms
		ubfp"
		case 's': // 4 strings to match.
		if (NameR.substr(13, 2) != "um")
		break;
		switch (NameR[15]) {
		default: break;
		case '2': // 1 string to match.
		if (NameR.substr(16, 3) != "sws")
		break;
		return Intrinsic::ppc_altivec_vsum2sws; // "pc.altivec.vsum
		2sws"
		case '4': // 3 strings to match.
		switch (NameR[16]) {
		default: break;
		case 's': // 2 strings to match.
		switch (NameR[17]) {
	default: break;	default: break;

	case 'd': // 1 string to match.	case 'b': // 1 string to match.
	if (NameR.substr(20, 4) != ".256")	if (NameR[18] != 's')
	break;	break;

	return Intrinsic::x86_avx_vpermilvar_pd_256; // "86.avx.	return Intrinsic::ppc_altivec_vsum4sbs; // "pc.alti
	vpermilvar.pd.256"	vec.vsum4sbs"
	case 's': // 1 string to match.	case 'h': // 1 string to match.
	if (NameR.substr(20, 4) != ".256")	if (NameR[18] != 's')
	break;	break;

	return Intrinsic::x86_avx_vpermilvar_ps_256; // "86.avx. vpermilvar.ps.256"	return Intrinsic::ppc_altivec_vsum4shs; // "pc.alti vec.vsum4shs"
	}	}
	break;	break;

		case 'u': // 1 string to match.
		if (NameR.substr(17, 2) != "bs")
		break;
		return Intrinsic::ppc_altivec_vsum4ubs; // "pc.altivec.vsum
		4ubs"
	}	}
	break;	break;
	}	}
	break;	break;
	}	}
	break;	break;

	case 's': // 1 string to match.	case 't': // 5 strings to match.
	if (NameR.substr(4, 20) != "sse3.pmadd.ub.sw.128")	if (NameR.substr(1, 16) != "x.read.lanemask.")
	break;	break;

	return Intrinsic::x86_ssse3_pmadd_ub_sw_128; // "86.ssse3.pmadd.	switch (NameR[17]) {
	ub.sw.128"	default: break;
		case 'e': // 1 string to match.
		if (NameR[18] != 'q')
		break;
		return Intrinsic::ptx_read_lanemask_eq; // "tx.read.lanemas
		k.eq"
		case 'g': // 2 strings to match.
		switch (NameR[18]) {
		default: break;
		case 'e': // 1 string to match.
		return Intrinsic::ptx_read_lanemask_ge; // "tx.read.lanemas
		k.ge"
		case 't': // 1 string to match.
		return Intrinsic::ptx_read_lanemask_gt; // "tx.read.lanemas
		k.gt"
		}
		break;
		case 'l': // 2 strings to match.
		switch (NameR[18]) {
		default: break;
		case 'e': // 1 string to match.
		return Intrinsic::ptx_read_lanemask_le; // "tx.read.lanemas
		k.le"
		case 't': // 1 string to match.
		return Intrinsic::ptx_read_lanemask_lt; // "tx.read.lanemas
		k.lt"
		}
		break;
		}
		break;
	}	}
	break;	break;

	case 25: // 3 strings to match.	case 20: // 4 strings to match.
	if (NameR.substr(0, 19) != "86.avx.vinsertf128.")	if (NameR.substr(0, 12) != "pc.altivec.v")
	break;	break;

	switch (NameR[19]) {	switch (NameR[12]) {
	default: break;	default: break;

	case 'p': // 2 strings to match.	case 'c': // 1 string to match.
	switch (NameR[20]) {	if (NameR.substr(13, 7) != "mpbfp.p")
		break;
		return Intrinsic::ppc_altivec_vcmpbfp_p; // "pc.altivec.vcmp
		bfp.p"
		case 'm': // 2 strings to match.
		switch (NameR[13]) {
	default: break;	default: break;

	case 'd': // 1 string to match.	case 'h': // 1 string to match.
	if (NameR.substr(21, 4) != ".256")	if (NameR.substr(14, 6) != "addshs")
	break;	break;

	return Intrinsic::x86_avx_vinsertf128_pd_256; // "86.avx.	return Intrinsic::ppc_altivec_vmhaddshs; // "pc.altivec.vmha
	vinsertf128.pd.256"	ddshs"
	case 's': // 1 string to match.	case 'l': // 1 string to match.
	if (NameR.substr(21, 4) != ".256")	if (NameR.substr(14, 6) != "adduhm")
	break;	break;

	return Intrinsic::x86_avx_vinsertf128_ps_256; // "86.avx. vinsertf128.ps.256"	return Intrinsic::ppc_altivec_vmladduhm; // "pc.altivec.vmla dduhm"
	}	}
	break;	break;

	case 's': // 1 string to match.	case 'r': // 1 string to match.
	if (NameR.substr(20, 5) != "i.256")	if (NameR.substr(13, 7) != "sqrtefp")
	break;	break;

	return Intrinsic::x86_avx_vinsertf128_si_256; // "86.avx.vinsertf 128.si.256"	return Intrinsic::ppc_altivec_vrsqrtefp; // "pc.altivec.vrsq rtefp"
	}	}
	break;	break;

	case 26: // 3 strings to match.	case 21: // 13 strings to match.
	if (NameR.substr(0, 20) != "86.avx.vextractf128.")	if (NameR.substr(0, 12) != "pc.altivec.v")
	break;	break;

	switch (NameR[20]) {	switch (NameR[12]) {
	default: break;	default: break;

	case 'p': // 2 strings to match.	case 'c': // 12 strings to match.
	switch (NameR[21]) {	if (NameR.substr(13, 2) != "mp")
		break;
		switch (NameR[15]) {
	default: break;	default: break;

	case 'd': // 1 string to match.	case 'e': // 4 strings to match.
	if (NameR.substr(22, 4) != ".256")	if (NameR[16] != 'q')
	break;	break;

	return Intrinsic::x86_avx_vextractf128_pd_256; // "86.avx.	switch (NameR[17]) {
	vextractf128.pd.256"	default: break;
	case 's': // 1 string to match.	case 'f': // 1 string to match.
	if (NameR.substr(22, 4) != ".256")	if (NameR.substr(18, 3) != "p.p")
		break;
		return Intrinsic::ppc_altivec_vcmpeqfp_p; // "pc.altivec.vcmp
		eqfp.p"
		case 'u': // 3 strings to match.
		switch (NameR[18]) {
		default: break;
		case 'b': // 1 string to match.
		if (NameR.substr(19, 2) != ".p")
		break;
		return Intrinsic::ppc_altivec_vcmpequb_p; // "pc.alti
		vec.vcmpequb.p"
		case 'h': // 1 string to match.
		if (NameR.substr(19, 2) != ".p")
		break;
		return Intrinsic::ppc_altivec_vcmpequh_p; // "pc.alti
		vec.vcmpequh.p"
		case 'w': // 1 string to match.
		if (NameR.substr(19, 2) != ".p")
		break;
		return Intrinsic::ppc_altivec_vcmpequw_p; // "pc.alti
		vec.vcmpequw.p"
		}
	break;	break;

	return Intrinsic::x86_avx_vextractf128_ps_256; // "86.avx.	}
	vextractf128.ps.256"	break;
		case 'g': // 8 strings to match.
		switch (NameR[16]) {
		default: break;
		case 'e': // 1 string to match.
		if (NameR.substr(17, 4) != "fp.p")
		break;
		return Intrinsic::ppc_altivec_vcmpgefp_p; // "pc.altivec.vcmp
		gefp.p"
		case 't': // 7 strings to match.
		switch (NameR[17]) {
		default: break;
		case 'f': // 1 string to match.
		if (NameR.substr(18, 3) != "p.p")
		break;
		return Intrinsic::ppc_altivec_vcmpgtfp_p; // "pc.alti
		vec.vcmpgtfp.p"
		case 's': // 3 strings to match.
		switch (NameR[18]) {
		default: break;
		case 'b': // 1 string to match.
		if (NameR.substr(19, 2) != ".p")
		break;
		return Intrinsic::ppc_altivec_vcmpgtsb_p; // "pc.alti
		vec.vcmpgtsb.p"
		case 'h': // 1 string to match.
		if (NameR.substr(19, 2) != ".p")
		break;
		return Intrinsic::ppc_altivec_vcmpgtsh_p; // "pc.alti
		vec.vcmpgtsh.p"
		case 'w': // 1 string to match.
		if (NameR.substr(19, 2) != ".p")
		break;
		return Intrinsic::ppc_altivec_vcmpgtsw_p; // "pc.alti
		vec.vcmpgtsw.p"
		}
		break;
		case 'u': // 3 strings to match.
		switch (NameR[18]) {
		default: break;
		case 'b': // 1 string to match.
		if (NameR.substr(19, 2) != ".p")
		break;
		return Intrinsic::ppc_altivec_vcmpgtub_p; // "pc.alti
		vec.vcmpgtub.p"
		case 'h': // 1 string to match.
		if (NameR.substr(19, 2) != ".p")
		break;
		return Intrinsic::ppc_altivec_vcmpgtuh_p; // "pc.alti
		vec.vcmpgtuh.p"
		case 'w': // 1 string to match.
		if (NameR.substr(19, 2) != ".p")
		break;
		return Intrinsic::ppc_altivec_vcmpgtuw_p; // "pc.alti
		vec.vcmpgtuw.p"
		}
		break;
		}
		break;
		}
		break;
	}	}
	break;	break;

	case 's': // 1 string to match.	case 'm': // 1 string to match.
	if (NameR.substr(21, 5) != "i.256")	if (NameR.substr(13, 8) != "hraddshs")
	break;	break;

	return Intrinsic::x86_avx_vextractf128_si_256; // "86.avx.vextract f128.si.256"	return Intrinsic::ppc_altivec_vmhraddshs; // "pc.altivec.vmhr addshs"
	}	}
	break;	break;

	case 28: // 2 strings to match.	}
	if (NameR.substr(0, 23) != "86.avx.vbroadcastf128.p")	break; // end of 'p' case.
		case 'r':
		switch (NameR.size()) {
		default: break;
		case 12: // 1 string to match.
		if (NameR.substr(0, 12) != "eturnaddress")
		break;
		return Intrinsic::returnaddress; // "eturnaddress"
		case 15: // 1 string to match.
		if (NameR.substr(0, 15) != "eadcyclecounter")
		break;
		return Intrinsic::readcyclecounter; // "eadcyclecounter"
		}
		break; // end of 'r' case.
		case 's':
		if (NameR.startswith("add.with.overflow.")) return Intrinsic::sadd_with
		_overflow;
		if (NameR.startswith("in.")) return Intrinsic::sin;
		if (NameR.startswith("mul.with.overflow.")) return Intrinsic::smul_with
		_overflow;
		if (NameR.startswith("qrt.")) return Intrinsic::sqrt;
		if (NameR.startswith("sub.with.overflow.")) return Intrinsic::ssub_with
		_overflow;
		switch (NameR.size()) {
		default: break;
		case 5: // 1 string to match.
		if (NameR.substr(0, 5) != "etjmp")
	break;	break;

	switch (NameR[23]) {	return Intrinsic::setjmp; // "etjmp"
		case 7: // 1 string to match.
		if (NameR.substr(0, 7) != "pu.si.a")
		break;
		return Intrinsic::spu_si_a; // "pu.si.a"
		case 8: // 11 strings to match.
		switch (NameR[0]) {
	default: break;	default: break;

	case 'd': // 1 string to match.	case 'i': // 1 string to match.
	if (NameR.substr(24, 4) != ".256")	if (NameR.substr(1, 7) != "gsetjmp")
	break;	break;

	return Intrinsic::x86_avx_vbroadcastf128_pd_256; // "86.avx.	return Intrinsic::sigsetjmp; // "igsetjmp"
	vbroadcastf128.pd.256"	case 'p': // 9 strings to match.
	case 's': // 1 string to match.	if (NameR.substr(1, 5) != "u.si.")
	if (NameR.substr(24, 4) != ".256")	break;
		switch (NameR[6]) {
		default: break;
		case 'a': // 2 strings to match.
		switch (NameR[7]) {
		default: break;
		case 'h': // 1 string to match.
		return Intrinsic::spu_si_ah; // "pu.si.ah"
		case 'i': // 1 string to match.
		return Intrinsic::spu_si_ai; // "pu.si.ai"
		}
		break;
		case 'b': // 1 string to match.
		if (NameR[7] != 'g')
		break;
		return Intrinsic::spu_si_bg; // "pu.si.bg"
		case 'c': // 1 string to match.
		if (NameR[7] != 'g')
		break;
		return Intrinsic::spu_si_cg; // "pu.si.cg"
		case 'f': // 3 strings to match.
		switch (NameR[7]) {
		default: break;
		case 'a': // 1 string to match.
		return Intrinsic::spu_si_fa; // "pu.si.fa"
		case 'm': // 1 string to match.
		return Intrinsic::spu_si_fm; // "pu.si.fm"
		case 's': // 1 string to match.
		return Intrinsic::spu_si_fs; // "pu.si.fs"
		}
		break;
		case 'o': // 1 string to match.
		if (NameR[7] != 'r')
		break;
		return Intrinsic::spu_si_or; // "pu.si.or"
		case 's': // 1 string to match.
		if (NameR[7] != 'f')
		break;
		return Intrinsic::spu_si_sf; // "pu.si.sf"
		}
		break;
		case 't': // 1 string to match.
		if (NameR.substr(1, 7) != "acksave")
	break;	break;

	return Intrinsic::x86_avx_vbroadcastf128_ps_256; // "86.avx. vbroadcastf128.ps.256"	return Intrinsic::stacksave; // "tacksave"
	}	}
	break;	break;

	}	case 9: // 20 strings to match.
	break; // end of 'x' case.	switch (NameR[0]) {
	}	default: break;
	#endif	case 'i': // 1 string to match.
		if (NameR.substr(1, 8) != "glongjmp")
	// Verifier::visitIntrinsicFunctionCall code.	break;
	#ifdef GET_INTRINSIC_VERIFIER	return Intrinsic::siglongjmp; // "iglongjmp"
	switch (ID) {	case 'p': // 19 strings to match.
	default: assert(0 && "Invalid intrinsic!");	if (NameR.substr(1, 5) != "u.si.")
	case Intrinsic::eh_unwind_init: // llvm.eh.unwind.init	break;
	case Intrinsic::ppc_altivec_dssall: // llvm.ppc.altivec.dssall	switch (NameR[6]) {
	case Intrinsic::ppc_sync: // llvm.ppc.sync	default: break;
	case Intrinsic::trap: // llvm.trap	case 'a': // 2 strings to match.
	case Intrinsic::x86_avx_vzeroall: // llvm.x86.avx.vzeroall	switch (NameR[7]) {
	case Intrinsic::x86_avx_vzeroupper: // llvm.x86.avx.vzeroupper	default: break;
	case Intrinsic::x86_mmx_emms: // llvm.x86.mmx.emms	case 'h': // 1 string to match.
	case Intrinsic::x86_mmx_femms: // llvm.x86.mmx.femms	if (NameR[8] != 'i')
	case Intrinsic::x86_sse2_lfence: // llvm.x86.sse2.lfence	break;
	case Intrinsic::x86_sse2_mfence: // llvm.x86.sse2.mfence	return Intrinsic::spu_si_ahi; // "pu.si.ahi"
	case Intrinsic::x86_sse_sfence: // llvm.x86.sse.sfence	case 'n': // 1 string to match.
	case Intrinsic::xcore_clre: // llvm.xcore.clre	if (NameR[8] != 'd')
	case Intrinsic::xcore_ssync: // llvm.xcore.ssync	break;
	VerifyIntrinsicPrototype(ID, IF, 0, 0);	return Intrinsic::spu_si_and; // "pu.si.and"
	break;	}
	case Intrinsic::xcore_eeu: // llvm.xcore.eeu	break;
	case Intrinsic::xcore_freer: // llvm.xcore.freer	case 'b': // 1 string to match.
	case Intrinsic::xcore_mjoin: // llvm.xcore.mjoin	if (NameR.substr(7, 2) != "gx")
	case Intrinsic::xcore_msync: // llvm.xcore.msync	break;
	case Intrinsic::xcore_syncr: // llvm.xcore.syncr	return Intrinsic::spu_si_bgx; // "pu.si.bgx"
	VerifyIntrinsicPrototype(ID, IF, 0, 1, MVT::iPTRAny);	case 'c': // 3 strings to match.
	break;	switch (NameR[7]) {
	case Intrinsic::xcore_setclk: // llvm.xcore.setclk	default: break;
	case Intrinsic::xcore_setrdy: // llvm.xcore.setrdy	case 'e': // 1 string to match.
	VerifyIntrinsicPrototype(ID, IF, 0, 2, MVT::iPTRAny, MVT::iPTRAny);	if (NameR[8] != 'q')
	break;	break;
	case Intrinsic::memcpy: // llvm.memcpy	return Intrinsic::spu_si_ceq; // "pu.si.ceq"
	case Intrinsic::memmove: // llvm.memmove	case 'g': // 2 strings to match.
	VerifyIntrinsicPrototype(ID, IF, 0, 5, MVT::iPTRAny, MVT::iPTRAny, MVT:	switch (NameR[8]) {
	:iAny, MVT::i32, MVT::i1);	default: break;
	break;	case 't': // 1 string to match.
	case Intrinsic::xcore_chkct: // llvm.xcore.chkct	return Intrinsic::spu_si_cgt; // "pu.si.cgt"
	case Intrinsic::xcore_out: // llvm.xcore.out	case 'x': // 1 string to match.
	case Intrinsic::xcore_outct: // llvm.xcore.outct	return Intrinsic::spu_si_cgx; // "pu.si.cgx"
	case Intrinsic::xcore_outt: // llvm.xcore.outt	}
	case Intrinsic::xcore_setc: // llvm.xcore.setc	break;
	case Intrinsic::xcore_setd: // llvm.xcore.setd	}
	case Intrinsic::xcore_setpsc: // llvm.xcore.setpsc	break;
	case Intrinsic::xcore_setpt: // llvm.xcore.setpt	case 'd': // 3 strings to match.
	case Intrinsic::xcore_settw: // llvm.xcore.settw	if (NameR[7] != 'f')
	VerifyIntrinsicPrototype(ID, IF, 0, 2, MVT::iPTRAny, MVT::i32);	break;
	break;	switch (NameR[8]) {
	case Intrinsic::memset: // llvm.memset	default: break;
	VerifyIntrinsicPrototype(ID, IF, 0, 5, MVT::iPTRAny, MVT::i8, MVT::iAny	case 'a': // 1 string to match.
	, MVT::i32, MVT::i1);	return Intrinsic::spu_si_dfa; // "pu.si.dfa"
	break;	case 'm': // 1 string to match.
	case Intrinsic::xcore_initcp: // llvm.xcore.initcp	return Intrinsic::spu_si_dfm; // "pu.si.dfm"
	case Intrinsic::xcore_initdp: // llvm.xcore.initdp	case 's': // 1 string to match.
		return Intrinsic::spu_si_dfs; // "pu.si.dfs"
		}
		break;
		case 'f': // 2 strings to match.
		if (NameR[7] != 'm')
		break;
		switch (NameR[8]) {
		default: break;
		case 'a': // 1 string to match.
		return Intrinsic::spu_si_fma; // "pu.si.fma"
		case 's': // 1 string to match.
		return Intrinsic::spu_si_fms; // "pu.si.fms"
		}
		break;
		case 'm': // 1 string to match.
		if (NameR.substr(7, 2) != "py")
		break;
		return Intrinsic::spu_si_mpy; // "pu.si.mpy"
		case 'n': // 1 string to match.
		if (NameR.substr(7, 2) != "or")
		break;
		return Intrinsic::spu_si_nor; // "pu.si.nor"
		case 'o': // 2 strings to match.
		if (NameR[7] != 'r')
		break;
		switch (NameR[8]) {
		default: break;
		case 'c': // 1 string to match.
		return Intrinsic::spu_si_orc; // "pu.si.orc"
		case 'i': // 1 string to match.
		return Intrinsic::spu_si_ori; // "pu.si.ori"
		}
		break;
		case 's': // 3 strings to match.
		if (NameR[7] != 'f')
		break;
		switch (NameR[8]) {
		default: break;
		case 'h': // 1 string to match.
		return Intrinsic::spu_si_sfh; // "pu.si.sfh"
		case 'i': // 1 string to match.
		return Intrinsic::spu_si_sfi; // "pu.si.sfi"
		case 'x': // 1 string to match.
		return Intrinsic::spu_si_sfx; // "pu.si.sfx"
		}
		break;
		case 'x': // 1 string to match.
		if (NameR.substr(7, 2) != "or")
		break;
		return Intrinsic::spu_si_xor; // "pu.si.xor"
		}
		break;
		}
		break;
		case 10: // 26 strings to match.
		if (NameR.substr(0, 6) != "pu.si.")
		break;
		switch (NameR[6]) {
		default: break;
		case 'a': // 3 strings to match.
		switch (NameR[7]) {
		default: break;
		case 'd': // 1 string to match.
		if (NameR.substr(8, 2) != "dx")
		break;
		return Intrinsic::spu_si_addx; // "pu.si.addx"
		case 'n': // 2 strings to match.
		if (NameR[8] != 'd')
		break;
		switch (NameR[9]) {
		default: break;
		case 'c': // 1 string to match.
		return Intrinsic::spu_si_andc; // "pu.si.andc"
		case 'i': // 1 string to match.
		return Intrinsic::spu_si_andi; // "pu.si.andi"
		}
		break;
		}
		break;
		case 'c': // 7 strings to match.
		switch (NameR[7]) {
		default: break;
		case 'e': // 3 strings to match.
		if (NameR[8] != 'q')
		break;
		switch (NameR[9]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::spu_si_ceqb; // "pu.si.ceqb"
		case 'h': // 1 string to match.
		return Intrinsic::spu_si_ceqh; // "pu.si.ceqh"
		case 'i': // 1 string to match.
		return Intrinsic::spu_si_ceqi; // "pu.si.ceqi"
		}
		break;
		case 'g': // 3 strings to match.
		if (NameR[8] != 't')
		break;
		switch (NameR[9]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::spu_si_cgtb; // "pu.si.cgtb"
		case 'h': // 1 string to match.
		return Intrinsic::spu_si_cgth; // "pu.si.cgth"
		case 'i': // 1 string to match.
		return Intrinsic::spu_si_cgti; // "pu.si.cgti"
		}
		break;
		case 'l': // 1 string to match.
		if (NameR.substr(8, 2) != "gt")
		break;
		return Intrinsic::spu_si_clgt; // "pu.si.clgt"
		}
		break;
		case 'd': // 2 strings to match.
		if (NameR.substr(7, 2) != "fm")
		break;
		switch (NameR[9]) {
		default: break;
		case 'a': // 1 string to match.
		return Intrinsic::spu_si_dfma; // "pu.si.dfma"
		case 's': // 1 string to match.
		return Intrinsic::spu_si_dfms; // "pu.si.dfms"
		}
		break;
		case 'f': // 3 strings to match.
		switch (NameR[7]) {
		default: break;
		case 'c': // 2 strings to match.
		switch (NameR[8]) {
		default: break;
		case 'e': // 1 string to match.
		if (NameR[9] != 'q')
		break;
		return Intrinsic::spu_si_fceq; // "pu.si.fceq"
		case 'g': // 1 string to match.
		if (NameR[9] != 't')
		break;
		return Intrinsic::spu_si_fcgt; // "pu.si.fcgt"
		}
		break;
		case 'n': // 1 string to match.
		if (NameR.substr(8, 2) != "ms")
		break;
		return Intrinsic::spu_si_fnms; // "pu.si.fnms"
		}
		break;
		case 'm': // 5 strings to match.
		if (NameR.substr(7, 2) != "py")
		break;
		switch (NameR[9]) {
		default: break;
		case 'a': // 1 string to match.
		return Intrinsic::spu_si_mpya; // "pu.si.mpya"
		case 'h': // 1 string to match.
		return Intrinsic::spu_si_mpyh; // "pu.si.mpyh"
		case 'i': // 1 string to match.
		return Intrinsic::spu_si_mpyi; // "pu.si.mpyi"
		case 's': // 1 string to match.
		return Intrinsic::spu_si_mpys; // "pu.si.mpys"
		case 'u': // 1 string to match.
		return Intrinsic::spu_si_mpyu; // "pu.si.mpyu"
		}
		break;
		case 'n': // 1 string to match.
		if (NameR.substr(7, 3) != "and")
		break;
		return Intrinsic::spu_si_nand; // "pu.si.nand"
		case 'o': // 2 strings to match.
		if (NameR[7] != 'r')
		break;
		switch (NameR[8]) {
		default: break;
		case 'b': // 1 string to match.
		if (NameR[9] != 'i')
		break;
		return Intrinsic::spu_si_orbi; // "pu.si.orbi"
		case 'h': // 1 string to match.
		if (NameR[9] != 'i')
		break;
		return Intrinsic::spu_si_orhi; // "pu.si.orhi"
		}
		break;
		case 's': // 2 strings to match.
		switch (NameR[7]) {
		default: break;
		case 'f': // 1 string to match.
		if (NameR.substr(8, 2) != "hi")
		break;
		return Intrinsic::spu_si_sfhi; // "pu.si.sfhi"
		case 'h': // 1 string to match.
		if (NameR.substr(8, 2) != "li")
		break;
		return Intrinsic::spu_si_shli; // "pu.si.shli"
		}
		break;
		case 'x': // 1 string to match.
		if (NameR.substr(7, 3) != "ori")
		break;
		return Intrinsic::spu_si_xori; // "pu.si.xori"
		}
		break;
		case 11: // 19 strings to match.
		switch (NameR[0]) {
		default: break;
		case 'p': // 18 strings to match.
		if (NameR.substr(1, 5) != "u.si.")
		break;
		switch (NameR[6]) {
		default: break;
		case 'a': // 2 strings to match.
		if (NameR.substr(7, 2) != "nd")
		break;
		switch (NameR[9]) {
		default: break;
		case 'b': // 1 string to match.
		if (NameR[10] != 'i')
		break;
		return Intrinsic::spu_si_andbi; // "pu.si.andbi"
		case 'h': // 1 string to match.
		if (NameR[10] != 'i')
		break;
		return Intrinsic::spu_si_andhi; // "pu.si.andhi"
		}
		break;
		case 'c': // 7 strings to match.
		switch (NameR[7]) {
		default: break;
		case 'e': // 2 strings to match.
		if (NameR[8] != 'q')
		break;
		switch (NameR[9]) {
		default: break;
		case 'b': // 1 string to match.
		if (NameR[10] != 'i')
		break;
		return Intrinsic::spu_si_ceqbi; // "pu.si.ceqbi"
		case 'h': // 1 string to match.
		if (NameR[10] != 'i')
		break;
		return Intrinsic::spu_si_ceqhi; // "pu.si.ceqhi"
		}
		break;
		case 'g': // 2 strings to match.
		if (NameR[8] != 't')
		break;
		switch (NameR[9]) {
		default: break;
		case 'b': // 1 string to match.
		if (NameR[10] != 'i')
		break;
		return Intrinsic::spu_si_cgtbi; // "pu.si.cgtbi"
		case 'h': // 1 string to match.
		if (NameR[10] != 'i')
		break;
		return Intrinsic::spu_si_cgthi; // "pu.si.cgthi"
		}
		break;
		case 'l': // 3 strings to match.
		if (NameR.substr(8, 2) != "gt")
		break;
		switch (NameR[10]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::spu_si_clgtb; // "pu.si.clgtb"
		case 'h': // 1 string to match.
		return Intrinsic::spu_si_clgth; // "pu.si.clgth"
		case 'i': // 1 string to match.
		return Intrinsic::spu_si_clgti; // "pu.si.clgti"
		}
		break;
		}
		break;
		case 'd': // 2 strings to match.
		if (NameR.substr(7, 3) != "fnm")
		break;
		switch (NameR[10]) {
		default: break;
		case 'a': // 1 string to match.
		return Intrinsic::spu_si_dfnma; // "pu.si.dfnma"
		case 's': // 1 string to match.
		return Intrinsic::spu_si_dfnms; // "pu.si.dfnms"
		}
		break;
		case 'f': // 3 strings to match.
		switch (NameR[7]) {
		default: break;
		case 'c': // 2 strings to match.
		if (NameR[8] != 'm')
		break;
		switch (NameR[9]) {
		default: break;
		case 'e': // 1 string to match.
		if (NameR[10] != 'q')
		break;
		return Intrinsic::spu_si_fcmeq; // "pu.si.fcmeq"
		case 'g': // 1 string to match.
		if (NameR[10] != 't')
		break;
		return Intrinsic::spu_si_fcmgt; // "pu.si.fcmgt"
		}
		break;
		case 's': // 1 string to match.
		if (NameR.substr(8, 3) != "mbi")
		break;
		return Intrinsic::spu_si_fsmbi; // "pu.si.fsmbi"
		}
		break;
		case 'm': // 2 strings to match.
		if (NameR.substr(7, 2) != "py")
		break;
		switch (NameR[9]) {
		default: break;
		case 'h': // 1 string to match.
		if (NameR[10] != 'h')
		break;
		return Intrinsic::spu_si_mpyhh; // "pu.si.mpyhh"
		case 'u': // 1 string to match.
		if (NameR[10] != 'i')
		break;
		return Intrinsic::spu_si_mpyui; // "pu.si.mpyui"
		}
		break;
		case 'x': // 2 strings to match.
		if (NameR.substr(7, 2) != "or")
		break;
		switch (NameR[9]) {
		default: break;
		case 'b': // 1 string to match.
		if (NameR[10] != 'i')
		break;
		return Intrinsic::spu_si_xorbi; // "pu.si.xorbi"
		case 'h': // 1 string to match.
		if (NameR[10] != 'i')
		break;
		return Intrinsic::spu_si_xorhi; // "pu.si.xorhi"
		}
		break;
		}
		break;
		case 't': // 1 string to match.
		if (NameR.substr(1, 10) != "ackrestore")
		break;
		return Intrinsic::stackrestore; // "tackrestore"
		}
		break;
		case 12: // 6 strings to match.
		if (NameR.substr(0, 6) != "pu.si.")
		break;
		switch (NameR[6]) {
		default: break;
		case 'c': // 2 strings to match.
		if (NameR.substr(7, 3) != "lgt")
		break;
		switch (NameR[10]) {
		default: break;
		case 'b': // 1 string to match.
		if (NameR[11] != 'i')
		break;
		return Intrinsic::spu_si_clgtbi; // "pu.si.clgtbi"
		case 'h': // 1 string to match.
		if (NameR[11] != 'i')
		break;
		return Intrinsic::spu_si_clgthi; // "pu.si.clgthi"
		}
		break;
		case 'm': // 2 strings to match.
		if (NameR.substr(7, 4) != "pyhh")
		break;
		switch (NameR[11]) {
		default: break;
		case 'a': // 1 string to match.
		return Intrinsic::spu_si_mpyhha; // "pu.si.mpyhha"
		case 'u': // 1 string to match.
		return Intrinsic::spu_si_mpyhhu; // "pu.si.mpyhhu"
		}
		break;
		case 's': // 2 strings to match.
		if (NameR.substr(7, 4) != "hlqb")
		break;
		switch (NameR[11]) {
		default: break;
		case 'i': // 1 string to match.
		return Intrinsic::spu_si_shlqbi; // "pu.si.shlqbi"
		case 'y': // 1 string to match.
		return Intrinsic::spu_si_shlqby; // "pu.si.shlqby"
		}
		break;
		}
		break;
		case 13: // 4 strings to match.
		switch (NameR[0]) {
		default: break;
		case 'p': // 3 strings to match.
		if (NameR.substr(1, 5) != "u.si.")
		break;
		switch (NameR[6]) {
		default: break;
		case 'm': // 1 string to match.
		if (NameR.substr(7, 6) != "pyhhau")
		break;
		return Intrinsic::spu_si_mpyhhau; // "pu.si.mpyhhau"
		case 's': // 2 strings to match.
		if (NameR.substr(7, 4) != "hlqb")
		break;
		switch (NameR[11]) {
		default: break;
		case 'i': // 1 string to match.
		if (NameR[12] != 'i')
		break;
		return Intrinsic::spu_si_shlqbii; // "pu.si.shlqbii"
		case 'y': // 1 string to match.
		if (NameR[12] != 'i')
		break;
		return Intrinsic::spu_si_shlqbyi; // "pu.si.shlqbyi"
		}
		break;
		}
		break;
		case 't': // 1 string to match.
		if (NameR.substr(1, 12) != "ackprotector")
		break;
		return Intrinsic::stackprotector; // "tackprotector"
		}
		break;
		}
		break; // end of 's' case.
		case 't':
		switch (NameR.size()) {
		default: break;
		case 3: // 1 string to match.
		if (NameR.substr(0, 3) != "rap")
		break;
		return Intrinsic::trap; // "rap"
		}
		break; // end of 't' case.
		case 'u':
		if (NameR.startswith("add.with.overflow.")) return Intrinsic::uadd_with
		_overflow;
		if (NameR.startswith("mul.with.overflow.")) return Intrinsic::umul_with
		_overflow;
		if (NameR.startswith("sub.with.overflow.")) return Intrinsic::usub_with
		_overflow;
		break; // end of 'u' case.
		case 'v':
		switch (NameR.size()) {
		default: break;
		case 5: // 1 string to match.
		if (NameR.substr(0, 5) != "a_end")
		break;
		return Intrinsic::vaend; // "a_end"
		case 6: // 1 string to match.
		if (NameR.substr(0, 6) != "a_copy")
		break;
		return Intrinsic::vacopy; // "a_copy"
		case 7: // 1 string to match.
		if (NameR.substr(0, 7) != "a_start")
		break;
		return Intrinsic::vastart; // "a_start"
		case 13: // 1 string to match.
		if (NameR.substr(0, 13) != "ar.annotation")
		break;
		return Intrinsic::var_annotation; // "ar.annotation"
		}
		break; // end of 'v' case.
		case 'x':
		if (NameR.startswith("core.chkct.")) return Intrinsic::xcore_chkct;
		if (NameR.startswith("core.eeu.")) return Intrinsic::xcore_eeu;
		if (NameR.startswith("core.endin.")) return Intrinsic::xcore_endin;
		if (NameR.startswith("core.freer.")) return Intrinsic::xcore_freer;
		if (NameR.startswith("core.getr.")) return Intrinsic::xcore_getr;
		if (NameR.startswith("core.getst.")) return Intrinsic::xcore_getst;
		if (NameR.startswith("core.getts.")) return Intrinsic::xcore_getts;
		if (NameR.startswith("core.in.")) return Intrinsic::xcore_in;
		if (NameR.startswith("core.inct.")) return Intrinsic::xcore_inct;
		if (NameR.startswith("core.initcp.")) return Intrinsic::xcore_initcp;
		if (NameR.startswith("core.initdp.")) return Intrinsic::xcore_initdp;
		if (NameR.startswith("core.initlr.")) return Intrinsic::xcore_initlr;
		if (NameR.startswith("core.initpc.")) return Intrinsic::xcore_initpc;
		if (NameR.startswith("core.initsp.")) return Intrinsic::xcore_initsp;
		if (NameR.startswith("core.inshr.")) return Intrinsic::xcore_inshr;
		if (NameR.startswith("core.int.")) return Intrinsic::xcore_int;
		if (NameR.startswith("core.mjoin.")) return Intrinsic::xcore_mjoin;
		if (NameR.startswith("core.msync.")) return Intrinsic::xcore_msync;
		if (NameR.startswith("core.out.")) return Intrinsic::xcore_out;
		if (NameR.startswith("core.outct.")) return Intrinsic::xcore_outct;
		if (NameR.startswith("core.outshr.")) return Intrinsic::xcore_outshr;
		if (NameR.startswith("core.outt.")) return Intrinsic::xcore_outt;
		if (NameR.startswith("core.peek.")) return Intrinsic::xcore_peek;
		if (NameR.startswith("core.setc.")) return Intrinsic::xcore_setc;
		if (NameR.startswith("core.setclk.")) return Intrinsic::xcore_setclk;
		if (NameR.startswith("core.setd.")) return Intrinsic::xcore_setd;
		if (NameR.startswith("core.setev.")) return Intrinsic::xcore_setev;
		if (NameR.startswith("core.setpsc.")) return Intrinsic::xcore_setpsc;
		if (NameR.startswith("core.setpt.")) return Intrinsic::xcore_setpt;
		if (NameR.startswith("core.setrdy.")) return Intrinsic::xcore_setrdy;
		if (NameR.startswith("core.settw.")) return Intrinsic::xcore_settw;
		if (NameR.startswith("core.setv.")) return Intrinsic::xcore_setv;
		if (NameR.startswith("core.syncr.")) return Intrinsic::xcore_syncr;
		if (NameR.startswith("core.testct.")) return Intrinsic::xcore_testct;
		if (NameR.startswith("core.testwct.")) return Intrinsic::xcore_testwct;
		switch (NameR.size()) {
		default: break;
		case 6: // 1 string to match.
		if (NameR.substr(0, 6) != "86.int")
		break;
		return Intrinsic::x86_int; // "86.int"
		case 9: // 4 strings to match.
		if (NameR.substr(0, 5) != "core.")
		break;
		switch (NameR[5]) {
		default: break;
		case 'c': // 2 strings to match.
		switch (NameR[6]) {
		default: break;
		case 'l': // 1 string to match.
		if (NameR.substr(7, 2) != "re")
		break;
		return Intrinsic::xcore_clre; // "core.clre"
		case 'r': // 1 string to match.
		if (NameR.substr(7, 2) != "c8")
		break;
		return Intrinsic::xcore_crc8; // "core.crc8"
		}
		break;
		case 's': // 1 string to match.
		if (NameR.substr(6, 3) != "ext")
		break;
		return Intrinsic::xcore_sext; // "core.sext"
		case 'z': // 1 string to match.
		if (NameR.substr(6, 3) != "ext")
		break;
		return Intrinsic::xcore_zext; // "core.zext"
		}
		break;
		case 10: // 10 strings to match.
		switch (NameR[0]) {
		default: break;
		case '8': // 1 string to match.
		if (NameR.substr(1, 9) != "6.mmx.por")
		break;
		return Intrinsic::x86_mmx_por; // "86.mmx.por"
		case 'c': // 9 strings to match.
		if (NameR.substr(1, 4) != "ore.")
		break;
		switch (NameR[5]) {
		default: break;
		case 'c': // 2 strings to match.
		switch (NameR[6]) {
		default: break;
		case 'l': // 1 string to match.
		if (NameR.substr(7, 3) != "rsr")
		break;
		return Intrinsic::xcore_clrsr; // "core.clrsr"
		case 'r': // 1 string to match.
		if (NameR.substr(7, 3) != "c32")
		break;
		return Intrinsic::xcore_crc32; // "core.crc32"
		}
		break;
		case 'g': // 4 strings to match.
		if (NameR.substr(6, 2) != "et")
		break;
		switch (NameR[8]) {
		default: break;
		case 'e': // 2 strings to match.
		switch (NameR[9]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::xcore_geted; // "core.geted"
		case 't': // 1 string to match.
		return Intrinsic::xcore_getet; // "core.getet"
		}
		break;
		case 'i': // 1 string to match.
		if (NameR[9] != 'd')
		break;
		return Intrinsic::xcore_getid; // "core.getid"
		case 'p': // 1 string to match.
		if (NameR[9] != 's')
		break;
		return Intrinsic::xcore_getps; // "core.getps"
		}
		break;
		case 's': // 3 strings to match.
		switch (NameR[6]) {
		default: break;
		case 'e': // 2 strings to match.
		if (NameR[7] != 't')
		break;
		switch (NameR[8]) {
		default: break;
		case 'p': // 1 string to match.
		if (NameR[9] != 's')
		break;
		return Intrinsic::xcore_setps; // "core.setps"
		case 's': // 1 string to match.
		if (NameR[9] != 'r')
		break;
		return Intrinsic::xcore_setsr; // "core.setsr"
		}
		break;
		case 's': // 1 string to match.
		if (NameR.substr(7, 3) != "ync")
		break;
		return Intrinsic::xcore_ssync; // "core.ssync"
		}
		break;
		}
		break;
		}
		break;
		case 11: // 4 strings to match.
		switch (NameR[0]) {
		default: break;
		case '8': // 3 strings to match.
		if (NameR.substr(1, 6) != "6.mmx.")
		break;
		switch (NameR[7]) {
		default: break;
		case 'e': // 1 string to match.
		if (NameR.substr(8, 3) != "mms")
		break;
		return Intrinsic::x86_mmx_emms; // "86.mmx.emms"
		case 'p': // 2 strings to match.
		switch (NameR[8]) {
		default: break;
		case 'a': // 1 string to match.
		if (NameR.substr(9, 2) != "nd")
		break;
		return Intrinsic::x86_mmx_pand; // "86.mmx.pand"
		case 'x': // 1 string to match.
		if (NameR.substr(9, 2) != "or")
		break;
		return Intrinsic::x86_mmx_pxor; // "86.mmx.pxor"
		}
		break;
		}
		break;
		case 'c': // 1 string to match.
		if (NameR.substr(1, 10) != "ore.bitrev")
		break;
		return Intrinsic::xcore_bitrev; // "core.bitrev"
		}
		break;
		case 12: // 2 strings to match.
		if (NameR.substr(0, 7) != "86.mmx.")
		break;
		switch (NameR[7]) {
		default: break;
		case 'f': // 1 string to match.
		if (NameR.substr(8, 4) != "emms")
		break;
		return Intrinsic::x86_mmx_femms; // "86.mmx.femms"
		case 'p': // 1 string to match.
		if (NameR.substr(8, 4) != "andn")
		break;
		return Intrinsic::x86_mmx_pandn; // "86.mmx.pandn"
		}
		break;
		case 13: // 49 strings to match.
		if (NameR.substr(0, 3) != "86.")
		break;
		switch (NameR[3]) {
		default: break;
		case 'a': // 1 string to match.
		if (NameR.substr(4, 9) != "vx2.permd")
		break;
		return Intrinsic::x86_avx2_permd; // "86.avx2.permd"
		case 'm': // 18 strings to match.
		if (NameR.substr(4, 4) != "mx.p")
		break;
		switch (NameR[8]) {
		default: break;
		case 'a': // 6 strings to match.
		switch (NameR[9]) {
		default: break;
		case 'd': // 4 strings to match.
		if (NameR.substr(10, 2) != "d.")
		break;
		switch (NameR[12]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::x86_mmx_padd_b; // "86.mmx.padd.b"
		case 'd': // 1 string to match.
		return Intrinsic::x86_mmx_padd_d; // "86.mmx.padd.d"
		case 'q': // 1 string to match.
		return Intrinsic::x86_mmx_padd_q; // "86.mmx.padd.q"
		case 'w': // 1 string to match.
		return Intrinsic::x86_mmx_padd_w; // "86.mmx.padd.w"
		}
		break;
		case 'v': // 2 strings to match.
		if (NameR.substr(10, 2) != "g.")
		break;
		switch (NameR[12]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::x86_mmx_pavg_b; // "86.mmx.pavg.b"
		case 'w': // 1 string to match.
		return Intrinsic::x86_mmx_pavg_w; // "86.mmx.pavg.w"
		}
		break;
		}
		break;
		case 's': // 12 strings to match.
		switch (NameR[9]) {
		default: break;
		case 'l': // 3 strings to match.
		if (NameR.substr(10, 2) != "l.")
		break;
		switch (NameR[12]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_mmx_psll_d; // "86.mmx.psll.d"
		case 'q': // 1 string to match.
		return Intrinsic::x86_mmx_psll_q; // "86.mmx.psll.q"
		case 'w': // 1 string to match.
		return Intrinsic::x86_mmx_psll_w; // "86.mmx.psll.w"
		}
		break;
		case 'r': // 5 strings to match.
		switch (NameR[10]) {
		default: break;
		case 'a': // 2 strings to match.
		if (NameR[11] != '.')
		break;
		switch (NameR[12]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_mmx_psra_d; // "86.mmx.psra.d"
		case 'w': // 1 string to match.
		return Intrinsic::x86_mmx_psra_w; // "86.mmx.psra.w"
		}
		break;
		case 'l': // 3 strings to match.
		if (NameR[11] != '.')
		break;
		switch (NameR[12]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_mmx_psrl_d; // "86.mmx.psrl.d"
		case 'q': // 1 string to match.
		return Intrinsic::x86_mmx_psrl_q; // "86.mmx.psrl.q"
		case 'w': // 1 string to match.
		return Intrinsic::x86_mmx_psrl_w; // "86.mmx.psrl.w"
		}
		break;
		}
		break;
		case 'u': // 4 strings to match.
		if (NameR.substr(10, 2) != "b.")
		break;
		switch (NameR[12]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::x86_mmx_psub_b; // "86.mmx.psub.b"
		case 'd': // 1 string to match.
		return Intrinsic::x86_mmx_psub_d; // "86.mmx.psub.d"
		case 'q': // 1 string to match.
		return Intrinsic::x86_mmx_psub_q; // "86.mmx.psub.q"
		case 'w': // 1 string to match.
		return Intrinsic::x86_mmx_psub_w; // "86.mmx.psub.w"
		}
		break;
		}
		break;
		}
		break;
		case 's': // 16 strings to match.
		if (NameR.substr(4, 2) != "se")
		break;
		switch (NameR[6]) {
		default: break;
		case '.': // 13 strings to match.
		switch (NameR[7]) {
		default: break;
		case 'a': // 1 string to match.
		if (NameR.substr(8, 5) != "dd.ss")
		break;
		return Intrinsic::x86_sse_add_ss; // "86.sse.add.ss"
		case 'c': // 2 strings to match.
		if (NameR.substr(8, 3) != "mp.")
		break;
		switch (NameR[11]) {
		default: break;
		case 'p': // 1 string to match.
		if (NameR[12] != 's')
		break;
		return Intrinsic::x86_sse_cmp_ps; // "86.sse.cmp.ps"
		case 's': // 1 string to match.
		if (NameR[12] != 's')
		break;
		return Intrinsic::x86_sse_cmp_ss; // "86.sse.cmp.ss"
		}
		break;
		case 'd': // 1 string to match.
		if (NameR.substr(8, 5) != "iv.ss")
		break;
		return Intrinsic::x86_sse_div_ss; // "86.sse.div.ss"
		case 'm': // 5 strings to match.
		switch (NameR[8]) {
		default: break;
		case 'a': // 2 strings to match.
		if (NameR.substr(9, 2) != "x.")
		break;
		switch (NameR[11]) {
		default: break;
		case 'p': // 1 string to match.
		if (NameR[12] != 's')
		break;
		return Intrinsic::x86_sse_max_ps; // "86.sse.max.ps"
		case 's': // 1 string to match.
		if (NameR[12] != 's')
		break;
		return Intrinsic::x86_sse_max_ss; // "86.sse.max.ss"
		}
		break;
		case 'i': // 2 strings to match.
		if (NameR.substr(9, 2) != "n.")
		break;
		switch (NameR[11]) {
		default: break;
		case 'p': // 1 string to match.
		if (NameR[12] != 's')
		break;
		return Intrinsic::x86_sse_min_ps; // "86.sse.min.ps"
		case 's': // 1 string to match.
		if (NameR[12] != 's')
		break;
		return Intrinsic::x86_sse_min_ss; // "86.sse.min.ss"
		}
		break;
		case 'u': // 1 string to match.
		if (NameR.substr(9, 4) != "l.ss")
		break;
		return Intrinsic::x86_sse_mul_ss; // "86.sse.mul.ss"
		}
		break;
		case 'r': // 2 strings to match.
		if (NameR.substr(8, 3) != "cp.")
		break;
		switch (NameR[11]) {
		default: break;
		case 'p': // 1 string to match.
		if (NameR[12] != 's')
		break;
		return Intrinsic::x86_sse_rcp_ps; // "86.sse.rcp.ps"
		case 's': // 1 string to match.
		if (NameR[12] != 's')
		break;
		return Intrinsic::x86_sse_rcp_ss; // "86.sse.rcp.ss"
		}
		break;
		case 's': // 2 strings to match.
		switch (NameR[8]) {
		default: break;
		case 'f': // 1 string to match.
		if (NameR.substr(9, 4) != "ence")
		break;
		return Intrinsic::x86_sse_sfence; // "86.sse.sfence"
		case 'u': // 1 string to match.
		if (NameR.substr(9, 4) != "b.ss")
		break;
		return Intrinsic::x86_sse_sub_ss; // "86.sse.sub.ss"
		}
		break;
		}
		break;
		case '3': // 1 string to match.
		if (NameR.substr(7, 6) != ".mwait")
		break;
		return Intrinsic::x86_sse3_mwait; // "86.sse3.mwait"
		case '4': // 2 strings to match.
		if (NameR.substr(7, 5) != "1.dpp")
		break;
		switch (NameR[12]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_sse41_dppd; // "86.sse41.dppd"
		case 's': // 1 string to match.
		return Intrinsic::x86_sse41_dpps; // "86.sse41.dpps"
		}
		break;
		}
		break;
		case 'x': // 14 strings to match.
		if (NameR.substr(4, 5) != "op.vp")
		break;
		switch (NameR[9]) {
		default: break;
		case 'c': // 1 string to match.
		if (NameR.substr(10, 3) != "mov")
		break;
		return Intrinsic::x86_xop_vpcmov; // "86.xop.vpcmov"
		case 'p': // 1 string to match.
		if (NameR.substr(10, 3) != "erm")
		break;
		return Intrinsic::x86_xop_vpperm; // "86.xop.vpperm"
		case 'r': // 4 strings to match.
		if (NameR.substr(10, 2) != "ot")
		break;
		switch (NameR[12]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::x86_xop_vprotb; // "86.xop.vprotb"
		case 'd': // 1 string to match.
		return Intrinsic::x86_xop_vprotd; // "86.xop.vprotd"
		case 'q': // 1 string to match.
		return Intrinsic::x86_xop_vprotq; // "86.xop.vprotq"
		case 'w': // 1 string to match.
		return Intrinsic::x86_xop_vprotw; // "86.xop.vprotw"
		}
		break;
		case 's': // 8 strings to match.
		if (NameR[10] != 'h')
		break;
		switch (NameR[11]) {
		default: break;
		case 'a': // 4 strings to match.
		switch (NameR[12]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::x86_xop_vpshab; // "86.xop.vpshab"
		case 'd': // 1 string to match.
		return Intrinsic::x86_xop_vpshad; // "86.xop.vpshad"
		case 'q': // 1 string to match.
		return Intrinsic::x86_xop_vpshaq; // "86.xop.vpshaq"
		case 'w': // 1 string to match.
		return Intrinsic::x86_xop_vpshaw; // "86.xop.vpshaw"
		}
		break;
		case 'l': // 4 strings to match.
		switch (NameR[12]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::x86_xop_vpshlb; // "86.xop.vpshlb"
		case 'd': // 1 string to match.
		return Intrinsic::x86_xop_vpshld; // "86.xop.vpshld"
		case 'q': // 1 string to match.
		return Intrinsic::x86_xop_vpshlq; // "86.xop.vpshlq"
		case 'w': // 1 string to match.
		return Intrinsic::x86_xop_vpshlw; // "86.xop.vpshlw"
		}
		break;
		}
		break;
		}
		break;
		}
		break;
		case 14: // 87 strings to match.
		switch (NameR[0]) {
		default: break;
		case '8': // 86 strings to match.
		if (NameR.substr(1, 2) != "6.")
		break;
		switch (NameR[3]) {
		default: break;
		case '3': // 9 strings to match.
		if (NameR.substr(4, 6) != "dnow.p")
		break;
		switch (NameR[10]) {
		default: break;
		case 'f': // 8 strings to match.
		switch (NameR[11]) {
		default: break;
		case '2': // 1 string to match.
		if (NameR.substr(12, 2) != "id")
		break;
		return Intrinsic::x86_3dnow_pf2id; // "86.3dnow.pf2id"
		case 'a': // 2 strings to match.
		switch (NameR[12]) {
		default: break;
		case 'c': // 1 string to match.
		if (NameR[13] != 'c')
		break;
		return Intrinsic::x86_3dnow_pfacc; // "86.3dnow.pfacc"
		case 'd': // 1 string to match.
		if (NameR[13] != 'd')
		break;
		return Intrinsic::x86_3dnow_pfadd; // "86.3dnow.pfadd"
		}
		break;
		case 'm': // 3 strings to match.
		switch (NameR[12]) {
		default: break;
		case 'a': // 1 string to match.
		if (NameR[13] != 'x')
		break;
		return Intrinsic::x86_3dnow_pfmax; // "86.3dnow.pfmax"
		case 'i': // 1 string to match.
		if (NameR[13] != 'n')
		break;
		return Intrinsic::x86_3dnow_pfmin; // "86.3dnow.pfmin"
		case 'u': // 1 string to match.
		if (NameR[13] != 'l')
		break;
		return Intrinsic::x86_3dnow_pfmul; // "86.3dnow.pfmul"
		}
		break;
		case 'r': // 1 string to match.
		if (NameR.substr(12, 2) != "cp")
		break;
		return Intrinsic::x86_3dnow_pfrcp; // "86.3dnow.pfrcp"
		case 's': // 1 string to match.
		if (NameR.substr(12, 2) != "ub")
		break;
		return Intrinsic::x86_3dnow_pfsub; // "86.3dnow.pfsub"
		}
		break;
		case 'i': // 1 string to match.
		if (NameR.substr(11, 3) != "2fd")
		break;
		return Intrinsic::x86_3dnow_pi2fd; // "86.3dnow.pi2fd"
		}
		break;
		case 'a': // 14 strings to match.
		if (NameR.substr(4, 5) != "vx2.p")
		break;
		switch (NameR[9]) {
		default: break;
		case 'a': // 5 strings to match.
		switch (NameR[10]) {
		default: break;
		case 'b': // 3 strings to match.
		if (NameR.substr(11, 2) != "s.")
		break;
		switch (NameR[13]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::x86_avx2_pabs_b; // "86.avx2.pabs.b"
		case 'd': // 1 string to match.
		return Intrinsic::x86_avx2_pabs_d; // "86.avx2.pabs.d"
		case 'w': // 1 string to match.
		return Intrinsic::x86_avx2_pabs_w; // "86.avx2.pabs.w"
		}
		break;
		case 'v': // 2 strings to match.
		if (NameR.substr(11, 2) != "g.")
		break;
		switch (NameR[13]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::x86_avx2_pavg_b; // "86.avx2.pavg.b"
		case 'w': // 1 string to match.
		return Intrinsic::x86_avx2_pavg_w; // "86.avx2.pavg.w"
		}
		break;
		}
		break;
		case 'e': // 1 string to match.
		if (NameR.substr(10, 4) != "rmps")
		break;
		return Intrinsic::x86_avx2_permps; // "86.avx2.permps"
		case 's': // 8 strings to match.
		switch (NameR[10]) {
		default: break;
		case 'l': // 3 strings to match.
		if (NameR.substr(11, 2) != "l.")
		break;
		switch (NameR[13]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_avx2_psll_d; // "86.avx2.psll.d"
		case 'q': // 1 string to match.
		return Intrinsic::x86_avx2_psll_q; // "86.avx2.psll.q"
		case 'w': // 1 string to match.
		return Intrinsic::x86_avx2_psll_w; // "86.avx2.psll.w"
		}
		break;
		case 'r': // 5 strings to match.
		switch (NameR[11]) {
		default: break;
		case 'a': // 2 strings to match.
		if (NameR[12] != '.')
		break;
		switch (NameR[13]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_avx2_psra_d; // "86.avx2.psra.d"
		case 'w': // 1 string to match.
		return Intrinsic::x86_avx2_psra_w; // "86.avx2.psra.w"
		}
		break;
		case 'l': // 3 strings to match.
		if (NameR[12] != '.')
		break;
		switch (NameR[13]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_avx2_psrl_d; // "86.avx2.psrl.d"
		case 'q': // 1 string to match.
		return Intrinsic::x86_avx2_psrl_q; // "86.avx2.psrl.q"
		case 'w': // 1 string to match.
		return Intrinsic::x86_avx2_psrl_w; // "86.avx2.psrl.w"
		}
		break;
		}
		break;
		}
		break;
		}
		break;
		case 'b': // 6 strings to match.
		if (NameR.substr(4, 3) != "mi.")
		break;
		switch (NameR[7]) {
		default: break;
		case 'b': // 2 strings to match.
		if (NameR.substr(8, 4) != "zhi.")
		break;
		switch (NameR[12]) {
		default: break;
		case '3': // 1 string to match.
		if (NameR[13] != '2')
		break;
		return Intrinsic::x86_bmi_bzhi_32; // "86.bmi.bzhi.32"
		case '6': // 1 string to match.
		if (NameR[13] != '4')
		break;
		return Intrinsic::x86_bmi_bzhi_64; // "86.bmi.bzhi.64"
		}
		break;
		case 'p': // 4 strings to match.
		switch (NameR[8]) {
		default: break;
		case 'd': // 2 strings to match.
		if (NameR.substr(9, 3) != "ep.")
		break;
		switch (NameR[12]) {
		default: break;
		case '3': // 1 string to match.
		if (NameR[13] != '2')
		break;
		return Intrinsic::x86_bmi_pdep_32; // "86.bmi.pdep.32"
		case '6': // 1 string to match.
		if (NameR[13] != '4')
		break;
		return Intrinsic::x86_bmi_pdep_64; // "86.bmi.pdep.64"
		}
		break;
		case 'e': // 2 strings to match.
		if (NameR.substr(9, 3) != "xt.")
		break;
		switch (NameR[12]) {
		default: break;
		case '3': // 1 string to match.
		if (NameR[13] != '2')
		break;
		return Intrinsic::x86_bmi_pext_32; // "86.bmi.pext.32"
		case '6': // 1 string to match.
		if (NameR[13] != '4')
		break;
		return Intrinsic::x86_bmi_pext_64; // "86.bmi.pext.64"
		}
		break;
		}
		break;
		}
		break;
		case 'm': // 21 strings to match.
		if (NameR.substr(4, 4) != "mx.p")
		break;
		switch (NameR[8]) {
		default: break;
		case 'a': // 2 strings to match.
		if (NameR.substr(9, 4) != "dds.")
		break;
		switch (NameR[13]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::x86_mmx_padds_b; // "86.mmx.padds.b"
		case 'w': // 1 string to match.
		return Intrinsic::x86_mmx_padds_w; // "86.mmx.padds.w"
		}
		break;
		case 'e': // 1 string to match.
		if (NameR.substr(9, 5) != "xtr.w")
		break;
		return Intrinsic::x86_mmx_pextr_w; // "86.mmx.pextr.w"
		case 'i': // 1 string to match.
		if (NameR.substr(9, 5) != "nsr.w")
		break;
		return Intrinsic::x86_mmx_pinsr_w; // "86.mmx.pinsr.w"
		case 'm': // 6 strings to match.
		switch (NameR[9]) {
		default: break;
		case 'a': // 2 strings to match.
		if (NameR[10] != 'x')
		break;
		switch (NameR[11]) {
		default: break;
		case 's': // 1 string to match.
		if (NameR.substr(12, 2) != ".w")
		break;
		return Intrinsic::x86_mmx_pmaxs_w; // "86.mmx.pmaxs.w"
		case 'u': // 1 string to match.
		if (NameR.substr(12, 2) != ".b")
		break;
		return Intrinsic::x86_mmx_pmaxu_b; // "86.mmx.pmaxu.b"
		}
		break;
		case 'i': // 2 strings to match.
		if (NameR[10] != 'n')
		break;
		switch (NameR[11]) {
		default: break;
		case 's': // 1 string to match.
		if (NameR.substr(12, 2) != ".w")
		break;
		return Intrinsic::x86_mmx_pmins_w; // "86.mmx.pmins.w"
		case 'u': // 1 string to match.
		if (NameR.substr(12, 2) != ".b")
		break;
		return Intrinsic::x86_mmx_pminu_b; // "86.mmx.pminu.b"
		}
		break;
		case 'u': // 2 strings to match.
		if (NameR[10] != 'l')
		break;
		switch (NameR[11]) {
		default: break;
		case 'h': // 1 string to match.
		if (NameR.substr(12, 2) != ".w")
		break;
		return Intrinsic::x86_mmx_pmulh_w; // "86.mmx.pmulh.w"
		case 'l': // 1 string to match.
		if (NameR.substr(12, 2) != ".w")
		break;
		return Intrinsic::x86_mmx_pmull_w; // "86.mmx.pmull.w"
		}
		break;
		}
		break;
		case 's': // 11 strings to match.
		switch (NameR[9]) {
		default: break;
		case 'a': // 1 string to match.
		if (NameR.substr(10, 4) != "d.bw")
		break;
		return Intrinsic::x86_mmx_psad_bw; // "86.mmx.psad.bw"
		case 'l': // 3 strings to match.
		if (NameR.substr(10, 3) != "li.")
		break;
		switch (NameR[13]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_mmx_pslli_d; // "86.mmx.pslli.d"
		case 'q': // 1 string to match.
		return Intrinsic::x86_mmx_pslli_q; // "86.mmx.pslli.q"
		case 'w': // 1 string to match.
		return Intrinsic::x86_mmx_pslli_w; // "86.mmx.pslli.w"
		}
		break;
		case 'r': // 5 strings to match.
		switch (NameR[10]) {
		default: break;
		case 'a': // 2 strings to match.
		if (NameR.substr(11, 2) != "i.")
		break;
		switch (NameR[13]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_mmx_psrai_d; // "86.mmx.psrai.d"
		case 'w': // 1 string to match.
		return Intrinsic::x86_mmx_psrai_w; // "86.mmx.psrai.w"
		}
		break;
		case 'l': // 3 strings to match.
		if (NameR.substr(11, 2) != "i.")
		break;
		switch (NameR[13]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_mmx_psrli_d; // "86.mmx.psrli.d"
		case 'q': // 1 string to match.
		return Intrinsic::x86_mmx_psrli_q; // "86.mmx.psrli.q"
		case 'w': // 1 string to match.
		return Intrinsic::x86_mmx_psrli_w; // "86.mmx.psrli.w"
		}
		break;
		}
		break;
		case 'u': // 2 strings to match.
		if (NameR.substr(10, 3) != "bs.")
		break;
		switch (NameR[13]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::x86_mmx_psubs_b; // "86.mmx.psubs.b"
		case 'w': // 1 string to match.
		return Intrinsic::x86_mmx_psubs_w; // "86.mmx.psubs.w"
		}
		break;
		}
		break;
		}
		break;
		case 'r': // 4 strings to match.
		if (NameR[4] != 'd')
		break;
		switch (NameR[5]) {
		default: break;
		case 'f': // 2 strings to match.
		if (NameR.substr(6, 6) != "sbase.")
		break;
		switch (NameR[12]) {
		default: break;
		case '3': // 1 string to match.
		if (NameR[13] != '2')
		break;
		return Intrinsic::x86_rdfsbase_32; // "86.rdfsbase.32"
		case '6': // 1 string to match.
		if (NameR[13] != '4')
		break;
		return Intrinsic::x86_rdfsbase_64; // "86.rdfsbase.64"
		}
		break;
		case 'g': // 2 strings to match.
		if (NameR.substr(6, 6) != "sbase.")
		break;
		switch (NameR[12]) {
		default: break;
		case '3': // 1 string to match.
		if (NameR[13] != '2')
		break;
		return Intrinsic::x86_rdgsbase_32; // "86.rdgsbase.32"
		case '6': // 1 string to match.
		if (NameR[13] != '4')
		break;
		return Intrinsic::x86_rdgsbase_64; // "86.rdgsbase.64"
		}
		break;
		}
		break;
		case 's': // 28 strings to match.
		if (NameR.substr(4, 2) != "se")
		break;
		switch (NameR[6]) {
		default: break;
		case '.': // 5 strings to match.
		switch (NameR[7]) {
		default: break;
		case 'l': // 1 string to match.
		if (NameR.substr(8, 6) != "dmxcsr")
		break;
		return Intrinsic::x86_sse_ldmxcsr; // "86.sse.ldmxcsr"
		case 'p': // 1 string to match.
		if (NameR.substr(8, 6) != "shuf.w")
		break;
		return Intrinsic::x86_sse_pshuf_w; // "86.sse.pshuf.w"
		case 's': // 3 strings to match.
		switch (NameR[8]) {
		default: break;
		case 'q': // 2 strings to match.
		if (NameR.substr(9, 3) != "rt.")
		break;
		switch (NameR[12]) {
		default: break;
		case 'p': // 1 string to match.
		if (NameR[13] != 's')
		break;
		return Intrinsic::x86_sse_sqrt_ps; // "86.sse.sqrt.ps"
		case 's': // 1 string to match.
		if (NameR[13] != 's')
		break;
		return Intrinsic::x86_sse_sqrt_ss; // "86.sse.sqrt.ss"
		}
		break;
		case 't': // 1 string to match.
		if (NameR.substr(9, 5) != "mxcsr")
		break;
		return Intrinsic::x86_sse_stmxcsr; // "86.sse.stmxcsr"
		}
		break;
		}
		break;
		case '2': // 22 strings to match.
		if (NameR[7] != '.')
		break;
		switch (NameR[8]) {
		default: break;
		case 'a': // 1 string to match.
		if (NameR.substr(9, 5) != "dd.sd")
		break;
		return Intrinsic::x86_sse2_add_sd; // "86.sse2.add.sd"
		case 'c': // 2 strings to match.
		if (NameR.substr(9, 3) != "mp.")
		break;
		switch (NameR[12]) {
		default: break;
		case 'p': // 1 string to match.
		if (NameR[13] != 'd')
		break;
		return Intrinsic::x86_sse2_cmp_pd; // "86.sse2.cmp.pd"
		case 's': // 1 string to match.
		if (NameR[13] != 'd')
		break;
		return Intrinsic::x86_sse2_cmp_sd; // "86.sse2.cmp.sd"
		}
		break;
		case 'd': // 1 string to match.
		if (NameR.substr(9, 5) != "iv.sd")
		break;
		return Intrinsic::x86_sse2_div_sd; // "86.sse2.div.sd"
		case 'l': // 1 string to match.
		if (NameR.substr(9, 5) != "fence")
		break;
		return Intrinsic::x86_sse2_lfence; // "86.sse2.lfence"
		case 'm': // 6 strings to match.
		switch (NameR[9]) {
		default: break;
		case 'a': // 2 strings to match.
		if (NameR.substr(10, 2) != "x.")
		break;
		switch (NameR[12]) {
		default: break;
		case 'p': // 1 string to match.
		if (NameR[13] != 'd')
		break;
		return Intrinsic::x86_sse2_max_pd; // "86.sse2.max.pd"
		case 's': // 1 string to match.
		if (NameR[13] != 'd')
		break;
		return Intrinsic::x86_sse2_max_sd; // "86.sse2.max.sd"
		}
		break;
		case 'f': // 1 string to match.
		if (NameR.substr(10, 4) != "ence")
		break;
		return Intrinsic::x86_sse2_mfence; // "86.sse2.mfence"
		case 'i': // 2 strings to match.
		if (NameR.substr(10, 2) != "n.")
		break;
		switch (NameR[12]) {
		default: break;
		case 'p': // 1 string to match.
		if (NameR[13] != 'd')
		break;
		return Intrinsic::x86_sse2_min_pd; // "86.sse2.min.pd"
		case 's': // 1 string to match.
		if (NameR[13] != 'd')
		break;
		return Intrinsic::x86_sse2_min_sd; // "86.sse2.min.sd"
		}
		break;
		case 'u': // 1 string to match.
		if (NameR.substr(10, 4) != "l.sd")
		break;
		return Intrinsic::x86_sse2_mul_sd; // "86.sse2.mul.sd"
		}
		break;
		case 'p': // 10 strings to match.
		switch (NameR[9]) {
		default: break;
		case 'a': // 2 strings to match.
		if (NameR.substr(10, 3) != "vg.")
		break;
		switch (NameR[13]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::x86_sse2_pavg_b; // "86.sse2.pavg.b"
		case 'w': // 1 string to match.
		return Intrinsic::x86_sse2_pavg_w; // "86.sse2.pavg.w"
		}
		break;
		case 's': // 8 strings to match.
		switch (NameR[10]) {
		default: break;
		case 'l': // 3 strings to match.
		if (NameR.substr(11, 2) != "l.")
		break;
		switch (NameR[13]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_sse2_psll_d; // "86.sse2.psll.d"
		case 'q': // 1 string to match.
		return Intrinsic::x86_sse2_psll_q; // "86.sse2.psll.q"
		case 'w': // 1 string to match.
		return Intrinsic::x86_sse2_psll_w; // "86.sse2.psll.w"
		}
		break;
		case 'r': // 5 strings to match.
		switch (NameR[11]) {
		default: break;
		case 'a': // 2 strings to match.
		if (NameR[12] != '.')
		break;
		switch (NameR[13]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_sse2_psra_d; // "86.sse2
		.psra.d"
		case 'w': // 1 string to match.
		return Intrinsic::x86_sse2_psra_w; // "86.sse2
		.psra.w"
		}
		break;
		case 'l': // 3 strings to match.
		if (NameR[12] != '.')
		break;
		switch (NameR[13]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_sse2_psrl_d; // "86.sse2
		.psrl.d"
		case 'q': // 1 string to match.
		return Intrinsic::x86_sse2_psrl_q; // "86.sse2
		.psrl.q"
		case 'w': // 1 string to match.
		return Intrinsic::x86_sse2_psrl_w; // "86.sse2
		.psrl.w"
		}
		break;
		}
		break;
		}
		break;
		}
		break;
		case 's': // 1 string to match.
		if (NameR.substr(9, 5) != "ub.sd")
		break;
		return Intrinsic::x86_sse2_sub_sd; // "86.sse2.sub.sd"
		}
		break;
		case '3': // 1 string to match.
		if (NameR.substr(7, 7) != ".ldu.dq")
		break;
		return Intrinsic::x86_sse3_ldu_dq; // "86.sse3.ldu.dq"
		}
		break;
		case 'w': // 4 strings to match.
		if (NameR[4] != 'r')
		break;
		switch (NameR[5]) {
		default: break;
		case 'f': // 2 strings to match.
		if (NameR.substr(6, 6) != "sbase.")
		break;
		switch (NameR[12]) {
		default: break;
		case '3': // 1 string to match.
		if (NameR[13] != '2')
		break;
		return Intrinsic::x86_wrfsbase_32; // "86.wrfsbase.32"
		case '6': // 1 string to match.
		if (NameR[13] != '4')
		break;
		return Intrinsic::x86_wrfsbase_64; // "86.wrfsbase.64"
		}
		break;
		case 'g': // 2 strings to match.
		if (NameR.substr(6, 6) != "sbase.")
		break;
		switch (NameR[12]) {
		default: break;
		case '3': // 1 string to match.
		if (NameR[13] != '2')
		break;
		return Intrinsic::x86_wrgsbase_32; // "86.wrgsbase.32"
		case '6': // 1 string to match.
		if (NameR[13] != '4')
		break;
		return Intrinsic::x86_wrgsbase_64; // "86.wrgsbase.64"
		}
		break;
		}
		break;
		}
		break;
		case 'c': // 1 string to match.
		if (NameR.substr(1, 13) != "ore.waitevent")
		break;
		return Intrinsic::xcore_waitevent; // "core.waitevent"
		}
		break;
		case 15: // 166 strings to match.
		switch (NameR[0]) {
		default: break;
		case '8': // 165 strings to match.
		if (NameR.substr(1, 2) != "6.")
		break;
		switch (NameR[3]) {
		default: break;
		case '3': // 3 strings to match.
		if (NameR.substr(4, 4) != "dnow")
		break;
		switch (NameR[8]) {
		default: break;
		case '.': // 1 string to match.
		if (NameR.substr(9, 6) != "pfsubr")
		break;
		return Intrinsic::x86_3dnow_pfsubr; // "86.3dnow.pfsubr
		"
		case 'a': // 2 strings to match.
		if (NameR.substr(9, 2) != ".p")
		break;
		switch (NameR[11]) {
		default: break;
		case 'f': // 1 string to match.
		if (NameR.substr(12, 3) != "2iw")
		break;
		return Intrinsic::x86_3dnowa_pf2iw; // "86.3dnowa.pf2iw
		"
		case 'i': // 1 string to match.
		if (NameR.substr(12, 3) != "2fw")
		break;
		return Intrinsic::x86_3dnowa_pi2fw; // "86.3dnowa.pi2fw
		"
		}
		break;
		}
		break;
		case 'a': // 48 strings to match.
		switch (NameR[4]) {
		default: break;
		case 'e': // 3 strings to match.
		if (NameR.substr(5, 7) != "sni.aes")
		break;
		switch (NameR[12]) {
		default: break;
		case 'd': // 1 string to match.
		if (NameR.substr(13, 2) != "ec")
		break;
		return Intrinsic::x86_aesni_aesdec; // "86.aesni.aesdec
		"
		case 'e': // 1 string to match.
		if (NameR.substr(13, 2) != "nc")
		break;
		return Intrinsic::x86_aesni_aesenc; // "86.aesni.aesenc
		"
		case 'i': // 1 string to match.
		if (NameR.substr(13, 2) != "mc")
		break;
		return Intrinsic::x86_aesni_aesimc; // "86.aesni.aesimc
		"
		}
		break;
		case 'v': // 45 strings to match.
		if (NameR[5] != 'x')
		break;
		switch (NameR[6]) {
		default: break;
		case '.': // 1 string to match.
		if (NameR.substr(7, 8) != "vzeroall")
		break;
		return Intrinsic::x86_avx_vzeroall; // "86.avx.vzeroall
		"
		case '2': // 44 strings to match.
		if (NameR[7] != '.')
		break;
		switch (NameR[8]) {
		default: break;
		case 'm': // 1 string to match.
		if (NameR.substr(9, 6) != "psadbw")
		break;
		return Intrinsic::x86_avx2_mpsadbw; // "86.avx2.mpsadbw
		"
		case 'p': // 43 strings to match.
		switch (NameR[9]) {
		default: break;
		case 'a': // 2 strings to match.
		if (NameR.substr(10, 4) != "dds.")
		break;
		switch (NameR[14]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::x86_avx2_padds_b; // "86.avx2
		.padds.b"
		case 'w': // 1 string to match.
		return Intrinsic::x86_avx2_padds_w; // "86.avx2
		.padds.w"
		}
		break;
		case 'b': // 1 string to match.
		if (NameR.substr(10, 5) != "lendw")
		break;
		return Intrinsic::x86_avx2_pblendw; // "86.avx2.pblendw
		"
		case 'h': // 4 strings to match.
		switch (NameR[10]) {
		default: break;
		case 'a': // 2 strings to match.
		if (NameR.substr(11, 3) != "dd.")
		break;
		switch (NameR[14]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_avx2_phadd_d; // "86.avx2
		.phadd.d"
		case 'w': // 1 string to match.
		return Intrinsic::x86_avx2_phadd_w; // "86.avx2
		.phadd.w"
		}
		break;
		case 's': // 2 strings to match.
		if (NameR.substr(11, 3) != "ub.")
		break;
		switch (NameR[14]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_avx2_phsub_d; // "86.avx2
		.phsub.d"
		case 'w': // 1 string to match.
		return Intrinsic::x86_avx2_phsub_w; // "86.avx2
		.phsub.w"
		}
		break;
		}
		break;
		case 'm': // 14 strings to match.
		switch (NameR[10]) {
		default: break;
		case 'a': // 6 strings to match.
		if (NameR[11] != 'x')
		break;
		switch (NameR[12]) {
		default: break;
		case 's': // 3 strings to match.
		if (NameR[13] != '.')
		break;
		switch (NameR[14]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::x86_avx2_pmaxs_b; // "86.avx2
		.pmaxs.b"
		case 'd': // 1 string to match.
		return Intrinsic::x86_avx2_pmaxs_d; // "86.avx2
		.pmaxs.d"
		case 'w': // 1 string to match.
		return Intrinsic::x86_avx2_pmaxs_w; // "86.avx2
		.pmaxs.w"
		}
		break;
		case 'u': // 3 strings to match.
		if (NameR[13] != '.')
		break;
		switch (NameR[14]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::x86_avx2_pmaxu_b; // "86.avx2
		.pmaxu.b"
		case 'd': // 1 string to match.
		return Intrinsic::x86_avx2_pmaxu_d; // "86.avx2
		.pmaxu.d"
		case 'w': // 1 string to match.
		return Intrinsic::x86_avx2_pmaxu_w; // "86.avx2
		.pmaxu.w"
		}
		break;
		}
		break;
		case 'i': // 6 strings to match.
		if (NameR[11] != 'n')
		break;
		switch (NameR[12]) {
		default: break;
		case 's': // 3 strings to match.
		if (NameR[13] != '.')
		break;
		switch (NameR[14]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::x86_avx2_pmins_b; // "86.avx2
		.pmins.b"
		case 'd': // 1 string to match.
		return Intrinsic::x86_avx2_pmins_d; // "86.avx2
		.pmins.d"
		case 'w': // 1 string to match.
		return Intrinsic::x86_avx2_pmins_w; // "86.avx2
		.pmins.w"
		}
		break;
		case 'u': // 3 strings to match.
		if (NameR[13] != '.')
		break;
		switch (NameR[14]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::x86_avx2_pminu_b; // "86.avx2
		.pminu.b"
		case 'd': // 1 string to match.
		return Intrinsic::x86_avx2_pminu_d; // "86.avx2
		.pminu.d"
		case 'w': // 1 string to match.
		return Intrinsic::x86_avx2_pminu_w; // "86.avx2
		.pminu.w"
		}
		break;
		}
		break;
		case 'u': // 2 strings to match.
		if (NameR[11] != 'l')
		break;
		switch (NameR[12]) {
		default: break;
		case '.': // 1 string to match.
		if (NameR.substr(13, 2) != "dq")
		break;
		return Intrinsic::x86_avx2_pmul_dq; // "86.avx2
		.pmul.dq"
		case 'h': // 1 string to match.
		if (NameR.substr(13, 2) != ".w")
		break;
		return Intrinsic::x86_avx2_pmulh_w; // "86.avx2
		.pmulh.w"
		}
		break;
		}
		break;
		case 's': // 22 strings to match.
		switch (NameR[10]) {
		default: break;
		case 'a': // 1 string to match.
		if (NameR.substr(11, 4) != "d.bw")
		break;
		return Intrinsic::x86_avx2_psad_bw; // "86.avx2
		.psad.bw"
		case 'h': // 1 string to match.
		if (NameR.substr(11, 4) != "uf.b")
		break;
		return Intrinsic::x86_avx2_pshuf_b; // "86.avx2
		.pshuf.b"
		case 'i': // 3 strings to match.
		if (NameR.substr(11, 3) != "gn.")
		break;
		switch (NameR[14]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::x86_avx2_psign_b; // "86.avx2
		.psign.b"
		case 'd': // 1 string to match.
		return Intrinsic::x86_avx2_psign_d; // "86.avx2
		.psign.d"
		case 'w': // 1 string to match.
		return Intrinsic::x86_avx2_psign_w; // "86.avx2
		.psign.w"
		}
		break;
		case 'l': // 6 strings to match.
		if (NameR[11] != 'l')
		break;
		switch (NameR[12]) {
		default: break;
		case '.': // 1 string to match.
		if (NameR.substr(13, 2) != "dq")
		break;
		return Intrinsic::x86_avx2_psll_dq; // "86.avx2
		.psll.dq"
		case 'i': // 3 strings to match.
		if (NameR[13] != '.')
		break;
		switch (NameR[14]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_avx2_pslli_d; // "86.avx2
		.pslli.d"
		case 'q': // 1 string to match.
		return Intrinsic::x86_avx2_pslli_q; // "86.avx2
		.pslli.q"
		case 'w': // 1 string to match.
		return Intrinsic::x86_avx2_pslli_w; // "86.avx2
		.pslli.w"
		}
		break;
		case 'v': // 2 strings to match.
		if (NameR[13] != '.')
		break;
		switch (NameR[14]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_avx2_psllv_d; // "86.avx2
		.psllv.d"
		case 'q': // 1 string to match.
		return Intrinsic::x86_avx2_psllv_q; // "86.avx2
		.psllv.q"
		}
		break;
		}
		break;
		case 'r': // 9 strings to match.
		switch (NameR[11]) {
		default: break;
		case 'a': // 3 strings to match.
		switch (NameR[12]) {
		default: break;
		case 'i': // 2 strings to match.
		if (NameR[13] != '.')
		break;
		switch (NameR[14]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_avx2_psrai_d; // "86.avx2
		.psrai.d"
		case 'w': // 1 string to match.
		return Intrinsic::x86_avx2_psrai_w; // "86.avx2
		.psrai.w"
		}
		break;
		case 'v': // 1 string to match.
		if (NameR.substr(13, 2) != ".d")
		break;
		return Intrinsic::x86_avx2_psrav_d; // "86.avx2
		.psrav.d"
		}
		break;
		case 'l': // 6 strings to match.
		switch (NameR[12]) {
		default: break;
		case '.': // 1 string to match.
		if (NameR.substr(13, 2) != "dq")
		break;
		return Intrinsic::x86_avx2_psrl_dq; // "86.avx2
		.psrl.dq"
		case 'i': // 3 strings to match.
		if (NameR[13] != '.')
		break;
		switch (NameR[14]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_avx2_psrli_d; // "86.avx2
		.psrli.d"
		case 'q': // 1 string to match.
		return Intrinsic::x86_avx2_psrli_q; // "86.avx2
		.psrli.q"
		case 'w': // 1 string to match.
		return Intrinsic::x86_avx2_psrli_w; // "86.avx2
		.psrli.w"
		}
		break;
		case 'v': // 2 strings to match.
		if (NameR[13] != '.')
		break;
		switch (NameR[14]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_avx2_psrlv_d; // "86.avx2
		.psrlv.d"
		case 'q': // 1 string to match.
		return Intrinsic::x86_avx2_psrlv_q; // "86.avx2
		.psrlv.q"
		}
		break;
		}
		break;
		}
		break;
		case 'u': // 2 strings to match.
		if (NameR.substr(11, 3) != "bs.")
		break;
		switch (NameR[14]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::x86_avx2_psubs_b; // "86.avx2
		.psubs.b"
		case 'w': // 1 string to match.
		return Intrinsic::x86_avx2_psubs_w; // "86.avx2
		.psubs.w"
		}
		break;
		}
		break;
		}
		break;
		}
		break;
		}
		break;
		}
		break;
		case 'b': // 2 strings to match.
		if (NameR.substr(4, 9) != "mi.bextr.")
		break;
		switch (NameR[13]) {
		default: break;
		case '3': // 1 string to match.
		if (NameR[14] != '2')
		break;
		return Intrinsic::x86_bmi_bextr_32; // "86.bmi.bextr.32
		"
		case '6': // 1 string to match.
		if (NameR[14] != '4')
		break;
		return Intrinsic::x86_bmi_bextr_64; // "86.bmi.bextr.64
		"
		}
		break;
		case 'm': // 19 strings to match.
		if (NameR.substr(4, 3) != "mx.")
		break;
		switch (NameR[7]) {
		default: break;
		case 'm': // 2 strings to match.
		switch (NameR[8]) {
		default: break;
		case 'a': // 1 string to match.
		if (NameR.substr(9, 6) != "skmovq")
		break;
		return Intrinsic::x86_mmx_maskmovq; // "86.mmx.maskmovq
		"
		case 'o': // 1 string to match.
		if (NameR.substr(9, 6) != "vnt.dq")
		break;
		return Intrinsic::x86_mmx_movnt_dq; // "86.mmx.movnt.dq
		"
		}
		break;
		case 'p': // 17 strings to match.
		switch (NameR[8]) {
		default: break;
		case 'a': // 5 strings to match.
		switch (NameR[9]) {
		default: break;
		case 'c': // 3 strings to match.
		if (NameR[10] != 'k')
		break;
		switch (NameR[11]) {
		default: break;
		case 's': // 2 strings to match.
		if (NameR[12] != 's')
		break;
		switch (NameR[13]) {
		default: break;
		case 'd': // 1 string to match.
		if (NameR[14] != 'w')
		break;
		return Intrinsic::x86_mmx_packssdw; // "86.mmx.
		packssdw"
		case 'w': // 1 string to match.
		if (NameR[14] != 'b')
		break;
		return Intrinsic::x86_mmx_packsswb; // "86.mmx.
		packsswb"
		}
		break;
		case 'u': // 1 string to match.
		if (NameR.substr(12, 3) != "swb")
		break;
		return Intrinsic::x86_mmx_packuswb; // "86.mmx.packuswb
		"
		}
		break;
		case 'd': // 2 strings to match.
		if (NameR.substr(10, 4) != "dus.")
		break;
		switch (NameR[14]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::x86_mmx_paddus_b; // "86.mmx.paddus.b
		"
		case 'w': // 1 string to match.
		return Intrinsic::x86_mmx_paddus_w; // "86.mmx.paddus.w
		"
		}
		break;
		}
		break;
		case 'c': // 6 strings to match.
		if (NameR.substr(9, 2) != "mp")
		break;
		switch (NameR[11]) {
		default: break;
		case 'e': // 3 strings to match.
		if (NameR.substr(12, 2) != "q.")
		break;
		switch (NameR[14]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::x86_mmx_pcmpeq_b; // "86.mmx.pcmpeq.b
		"
		case 'd': // 1 string to match.
		return Intrinsic::x86_mmx_pcmpeq_d; // "86.mmx.pcmpeq.d
		"
		case 'w': // 1 string to match.
		return Intrinsic::x86_mmx_pcmpeq_w; // "86.mmx.pcmpeq.w
		"
		}
		break;
		case 'g': // 3 strings to match.
		if (NameR.substr(12, 2) != "t.")
		break;
		switch (NameR[14]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::x86_mmx_pcmpgt_b; // "86.mmx.pcmpgt.b
		"
		case 'd': // 1 string to match.
		return Intrinsic::x86_mmx_pcmpgt_d; // "86.mmx.pcmpgt.d
		"
		case 'w': // 1 string to match.
		return Intrinsic::x86_mmx_pcmpgt_w; // "86.mmx.pcmpgt.w
		"
		}
		break;
		}
		break;
		case 'm': // 4 strings to match.
		switch (NameR[9]) {
		default: break;
		case 'a': // 1 string to match.
		if (NameR.substr(10, 5) != "dd.wd")
		break;
		return Intrinsic::x86_mmx_pmadd_wd; // "86.mmx.pmadd.wd
		"
		case 'o': // 1 string to match.
		if (NameR.substr(10, 5) != "vmskb")
		break;
		return Intrinsic::x86_mmx_pmovmskb; // "86.mmx.pmovmskb
		"
		case 'u': // 2 strings to match.
		if (NameR[10] != 'l')
		break;
		switch (NameR[11]) {
		default: break;
		case 'h': // 1 string to match.
		if (NameR.substr(12, 3) != "u.w")
		break;
		return Intrinsic::x86_mmx_pmulhu_w; // "86.mmx.pmulhu.w
		"
		case 'u': // 1 string to match.
		if (NameR.substr(12, 3) != ".dq")
		break;
		return Intrinsic::x86_mmx_pmulu_dq; // "86.mmx.pmulu.dq
		"
		}
		break;
		}
		break;
		case 's': // 2 strings to match.
		if (NameR.substr(9, 5) != "ubus.")
		break;
		switch (NameR[14]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::x86_mmx_psubus_b; // "86.mmx.psubus.b
		"
		case 'w': // 1 string to match.
		return Intrinsic::x86_mmx_psubus_w; // "86.mmx.psubus.w
		"
		}
		break;
		}
		break;
		}
		break;
		case 's': // 53 strings to match.
		if (NameR[4] != 's')
		break;
		switch (NameR[5]) {
		default: break;
		case 'e': // 50 strings to match.
		switch (NameR[6]) {
		default: break;
		case '.': // 8 strings to match.
		switch (NameR[7]) {
		default: break;
		case 'c': // 6 strings to match.
		if (NameR.substr(8, 2) != "vt")
		break;
		switch (NameR[10]) {
		default: break;
		case 'p': // 4 strings to match.
		switch (NameR[11]) {
		default: break;
		case 'd': // 1 string to match.
		if (NameR.substr(12, 3) != "2pi")
		break;
		return Intrinsic::x86_sse_cvtpd2pi; // "86.sse.
		cvtpd2pi"
		case 'i': // 2 strings to match.
		if (NameR.substr(12, 2) != "2p")
		break;
		switch (NameR[14]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_sse_cvtpi2pd; // "86.sse.
		cvtpi2pd"
		case 's': // 1 string to match.
		return Intrinsic::x86_sse_cvtpi2ps; // "86.sse.
		cvtpi2ps"
		}
		break;
		case 's': // 1 string to match.
		if (NameR.substr(12, 3) != "2pi")
		break;
		return Intrinsic::x86_sse_cvtps2pi; // "86.sse.
		cvtps2pi"
		}
		break;
		case 's': // 2 strings to match.
		switch (NameR[11]) {
		default: break;
		case 'i': // 1 string to match.
		if (NameR.substr(12, 3) != "2ss")
		break;
		return Intrinsic::x86_sse_cvtsi2ss; // "86.sse.
		cvtsi2ss"
		case 's': // 1 string to match.
		if (NameR.substr(12, 3) != "2si")
		break;
		return Intrinsic::x86_sse_cvtss2si; // "86.sse.
		cvtss2si"
		}
		break;
		}
		break;
		case 'r': // 2 strings to match.
		if (NameR.substr(8, 5) != "sqrt.")
		break;
		switch (NameR[13]) {
		default: break;
		case 'p': // 1 string to match.
		if (NameR[14] != 's')
		break;
		return Intrinsic::x86_sse_rsqrt_ps; // "86.sse.rsqrt.ps
		"
		case 's': // 1 string to match.
		if (NameR[14] != 's')
		break;
		return Intrinsic::x86_sse_rsqrt_ss; // "86.sse.rsqrt.ss
		"
		}
		break;
		}
		break;
		case '2': // 23 strings to match.
		if (NameR[7] != '.')
		break;
		switch (NameR[8]) {
		default: break;
		case 'c': // 1 string to match.
		if (NameR.substr(9, 6) != "lflush")
		break;
		return Intrinsic::x86_sse2_clflush; // "86.sse2.clflush
		"
		case 'p': // 20 strings to match.
		switch (NameR[9]) {
		default: break;
		case 'a': // 2 strings to match.
		if (NameR.substr(10, 4) != "dds.")
		break;
		switch (NameR[14]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::x86_sse2_padds_b; // "86.sse2
		.padds.b"
		case 'w': // 1 string to match.
		return Intrinsic::x86_sse2_padds_w; // "86.sse2
		.padds.w"
		}
		break;
		case 'm': // 5 strings to match.
		switch (NameR[10]) {
		default: break;
		case 'a': // 2 strings to match.
		if (NameR[11] != 'x')
		break;
		switch (NameR[12]) {
		default: break;
		case 's': // 1 string to match.
		if (NameR.substr(13, 2) != ".w")
		break;
		return Intrinsic::x86_sse2_pmaxs_w; // "86.sse2
		.pmaxs.w"
		case 'u': // 1 string to match.
		if (NameR.substr(13, 2) != ".b")
		break;
		return Intrinsic::x86_sse2_pmaxu_b; // "86.sse2
		.pmaxu.b"
		}
		break;
		case 'i': // 2 strings to match.
		if (NameR[11] != 'n')
		break;
		switch (NameR[12]) {
		default: break;
		case 's': // 1 string to match.
		if (NameR.substr(13, 2) != ".w")
		break;
		return Intrinsic::x86_sse2_pmins_w; // "86.sse2
		.pmins.w"
		case 'u': // 1 string to match.
		if (NameR.substr(13, 2) != ".b")
		break;
		return Intrinsic::x86_sse2_pminu_b; // "86.sse2
		.pminu.b"
		}
		break;
		case 'u': // 1 string to match.
		if (NameR.substr(11, 4) != "lh.w")
		break;
		return Intrinsic::x86_sse2_pmulh_w; // "86.sse2
		.pmulh.w"
		}
		break;
		case 's': // 13 strings to match.
		switch (NameR[10]) {
		default: break;
		case 'a': // 1 string to match.
		if (NameR.substr(11, 4) != "d.bw")
		break;
		return Intrinsic::x86_sse2_psad_bw; // "86.sse2
		.psad.bw"
		case 'l': // 4 strings to match.
		if (NameR[11] != 'l')
		break;
		switch (NameR[12]) {
		default: break;
		case '.': // 1 string to match.
		if (NameR.substr(13, 2) != "dq")
		break;
		return Intrinsic::x86_sse2_psll_dq; // "86.sse2
		.psll.dq"
		case 'i': // 3 strings to match.
		if (NameR[13] != '.')
		break;
		switch (NameR[14]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_sse2_pslli_d; // "86.sse2
		.pslli.d"
		case 'q': // 1 string to match.
		return Intrinsic::x86_sse2_pslli_q; // "86.sse2
		.pslli.q"
		case 'w': // 1 string to match.
		return Intrinsic::x86_sse2_pslli_w; // "86.sse2
		.pslli.w"
		}
		break;
		}
		break;
		case 'r': // 6 strings to match.
		switch (NameR[11]) {
		default: break;
		case 'a': // 2 strings to match.
		if (NameR.substr(12, 2) != "i.")
		break;
		switch (NameR[14]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_sse2_psrai_d; // "86.sse2
		.psrai.d"
		case 'w': // 1 string to match.
		return Intrinsic::x86_sse2_psrai_w; // "86.sse2
		.psrai.w"
		}
		break;
		case 'l': // 4 strings to match.
		switch (NameR[12]) {
		default: break;
		case '.': // 1 string to match.
		if (NameR.substr(13, 2) != "dq")
		break;
		return Intrinsic::x86_sse2_psrl_dq; // "86.sse2
		.psrl.dq"
		case 'i': // 3 strings to match.
		if (NameR[13] != '.')
		break;
		switch (NameR[14]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_sse2_psrli_d; // "86.sse2
		.psrli.d"
		case 'q': // 1 string to match.
		return Intrinsic::x86_sse2_psrli_q; // "86.sse2
		.psrli.q"
		case 'w': // 1 string to match.
		return Intrinsic::x86_sse2_psrli_w; // "86.sse2
		.psrli.w"
		}
		break;
		}
		break;
		}
		break;
		case 'u': // 2 strings to match.
		if (NameR.substr(11, 3) != "bs.")
		break;
		switch (NameR[14]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::x86_sse2_psubs_b; // "86.sse2
		.psubs.b"
		case 'w': // 1 string to match.
		return Intrinsic::x86_sse2_psubs_w; // "86.sse2
		.psubs.w"
		}
		break;
		}
		break;
		}
		break;
		case 's': // 2 strings to match.
		if (NameR.substr(9, 4) != "qrt.")
		break;
		switch (NameR[13]) {
		default: break;
		case 'p': // 1 string to match.
		if (NameR[14] != 'd')
		break;
		return Intrinsic::x86_sse2_sqrt_pd; // "86.sse2.sqrt.pd
		"
		case 's': // 1 string to match.
		if (NameR[14] != 'd')
		break;
		return Intrinsic::x86_sse2_sqrt_sd; // "86.sse2.sqrt.sd
		"
		}
		break;
		}
		break;
		case '3': // 5 strings to match.
		if (NameR[7] != '.')
		break;
		switch (NameR[8]) {
		default: break;
		case 'h': // 4 strings to match.
		switch (NameR[9]) {
		default: break;
		case 'a': // 2 strings to match.
		if (NameR.substr(10, 4) != "dd.p")
		break;
		switch (NameR[14]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_sse3_hadd_pd; // "86.sse3
		.hadd.pd"
		case 's': // 1 string to match.
		return Intrinsic::x86_sse3_hadd_ps; // "86.sse3
		.hadd.ps"
		}
		break;
		case 's': // 2 strings to match.
		if (NameR.substr(10, 4) != "ub.p")
		break;
		switch (NameR[14]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_sse3_hsub_pd; // "86.sse3
		.hsub.pd"
		case 's': // 1 string to match.
		return Intrinsic::x86_sse3_hsub_ps; // "86.sse3
		.hsub.ps"
		}
		break;
		}
		break;
		case 'm': // 1 string to match.
		if (NameR.substr(9, 6) != "onitor")
		break;
		return Intrinsic::x86_sse3_monitor; // "86.sse3.monitor
		"
		}
		break;
		case '4': // 14 strings to match.
		if (NameR.substr(7, 3) != "1.p")
		break;
		switch (NameR[10]) {
		default: break;
		case 'e': // 3 strings to match.
		if (NameR.substr(11, 3) != "xtr")
		break;
		switch (NameR[14]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::x86_sse41_pextrb; // "86.sse41.pextrb
		"
		case 'd': // 1 string to match.
		return Intrinsic::x86_sse41_pextrd; // "86.sse41.pextrd
		"
		case 'q': // 1 string to match.
		return Intrinsic::x86_sse41_pextrq; // "86.sse41.pextrq
		"
		}
		break;
		case 'm': // 9 strings to match.
		switch (NameR[11]) {
		default: break;
		case 'a': // 4 strings to match.
		if (NameR[12] != 'x')
		break;
		switch (NameR[13]) {
		default: break;
		case 's': // 2 strings to match.
		switch (NameR[14]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::x86_sse41_pmaxsb; // "86.sse4
		1.pmaxsb"
		case 'd': // 1 string to match.
		return Intrinsic::x86_sse41_pmaxsd; // "86.sse4
		1.pmaxsd"
		}
		break;
		case 'u': // 2 strings to match.
		switch (NameR[14]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_sse41_pmaxud; // "86.sse4
		1.pmaxud"
		case 'w': // 1 string to match.
		return Intrinsic::x86_sse41_pmaxuw; // "86.sse4
		1.pmaxuw"
		}
		break;
		}
		break;
		case 'i': // 4 strings to match.
		if (NameR[12] != 'n')
		break;
		switch (NameR[13]) {
		default: break;
		case 's': // 2 strings to match.
		switch (NameR[14]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::x86_sse41_pminsb; // "86.sse4
		1.pminsb"
		case 'd': // 1 string to match.
		return Intrinsic::x86_sse41_pminsd; // "86.sse4
		1.pminsd"
		}
		break;
		case 'u': // 2 strings to match.
		switch (NameR[14]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_sse41_pminud; // "86.sse4
		1.pminud"
		case 'w': // 1 string to match.
		return Intrinsic::x86_sse41_pminuw; // "86.sse4
		1.pminuw"
		}
		break;
		}
		break;
		case 'u': // 1 string to match.
		if (NameR.substr(12, 3) != "ldq")
		break;
		return Intrinsic::x86_sse41_pmuldq; // "86.sse41.pmuldq
		"
		}
		break;
		case 't': // 2 strings to match.
		if (NameR.substr(11, 3) != "est")
		break;
		switch (NameR[14]) {
		default: break;
		case 'c': // 1 string to match.
		return Intrinsic::x86_sse41_ptestc; // "86.sse41.ptestc
		"
		case 'z': // 1 string to match.
		return Intrinsic::x86_sse41_ptestz; // "86.sse41.ptestz
		"
		}
		break;
		}
		break;
		}
		break;
		case 's': // 3 strings to match.
		if (NameR.substr(6, 8) != "e3.pabs.")
		break;
		switch (NameR[14]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::x86_ssse3_pabs_b; // "86.ssse3.pabs.b
		"
		case 'd': // 1 string to match.
		return Intrinsic::x86_ssse3_pabs_d; // "86.ssse3.pabs.d
		"
		case 'w': // 1 string to match.
		return Intrinsic::x86_ssse3_pabs_w; // "86.ssse3.pabs.w
		"
		}
		break;
		}
		break;
		case 'x': // 40 strings to match.
		if (NameR.substr(4, 4) != "op.v")
		break;
		switch (NameR[8]) {
		default: break;
		case 'f': // 4 strings to match.
		if (NameR.substr(9, 4) != "rcz.")
		break;
		switch (NameR[13]) {
		default: break;
		case 'p': // 2 strings to match.
		switch (NameR[14]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_xop_vfrcz_pd; // "86.xop.vfrcz.pd
		"
		case 's': // 1 string to match.
		return Intrinsic::x86_xop_vfrcz_ps; // "86.xop.vfrcz.ps
		"
		}
		break;
		case 's': // 2 strings to match.
		switch (NameR[14]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_xop_vfrcz_sd; // "86.xop.vfrcz.sd
		"
		case 's': // 1 string to match.
		return Intrinsic::x86_xop_vfrcz_ss; // "86.xop.vfrcz.ss
		"
		}
		break;
		}
		break;
		case 'p': // 36 strings to match.
		switch (NameR[9]) {
		default: break;
		case 'c': // 24 strings to match.
		if (NameR.substr(10, 2) != "om")
		break;
		switch (NameR[12]) {
		default: break;
		case 'e': // 4 strings to match.
		if (NameR[13] != 'q')
		break;
		switch (NameR[14]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::x86_xop_vpcomeqb; // "86.xop.vpcomeqb
		"
		case 'd': // 1 string to match.
		return Intrinsic::x86_xop_vpcomeqd; // "86.xop.vpcomeqd
		"
		case 'q': // 1 string to match.
		return Intrinsic::x86_xop_vpcomeqq; // "86.xop.vpcomeqq
		"
		case 'w': // 1 string to match.
		return Intrinsic::x86_xop_vpcomeqw; // "86.xop.vpcomeqw
		"
		}
		break;
		case 'g': // 8 strings to match.
		switch (NameR[13]) {
		default: break;
		case 'e': // 4 strings to match.
		switch (NameR[14]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::x86_xop_vpcomgeb; // "86.xop.
		vpcomgeb"
		case 'd': // 1 string to match.
		return Intrinsic::x86_xop_vpcomged; // "86.xop.
		vpcomged"
		case 'q': // 1 string to match.
		return Intrinsic::x86_xop_vpcomgeq; // "86.xop.
		vpcomgeq"
		case 'w': // 1 string to match.
		return Intrinsic::x86_xop_vpcomgew; // "86.xop.
		vpcomgew"
		}
		break;
		case 't': // 4 strings to match.
		switch (NameR[14]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::x86_xop_vpcomgtb; // "86.xop.
		vpcomgtb"
		case 'd': // 1 string to match.
		return Intrinsic::x86_xop_vpcomgtd; // "86.xop.
		vpcomgtd"
		case 'q': // 1 string to match.
		return Intrinsic::x86_xop_vpcomgtq; // "86.xop.
		vpcomgtq"
		case 'w': // 1 string to match.
		return Intrinsic::x86_xop_vpcomgtw; // "86.xop.
		vpcomgtw"
		}
		break;
		}
		break;
		case 'l': // 8 strings to match.
		switch (NameR[13]) {
		default: break;
		case 'e': // 4 strings to match.
		switch (NameR[14]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::x86_xop_vpcomleb; // "86.xop.
		vpcomleb"
		case 'd': // 1 string to match.
		return Intrinsic::x86_xop_vpcomled; // "86.xop.
		vpcomled"
		case 'q': // 1 string to match.
		return Intrinsic::x86_xop_vpcomleq; // "86.xop.
		vpcomleq"
		case 'w': // 1 string to match.
		return Intrinsic::x86_xop_vpcomlew; // "86.xop.
		vpcomlew"
		}
		break;
		case 't': // 4 strings to match.
		switch (NameR[14]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::x86_xop_vpcomltb; // "86.xop.
		vpcomltb"
		case 'd': // 1 string to match.
		return Intrinsic::x86_xop_vpcomltd; // "86.xop.
		vpcomltd"
		case 'q': // 1 string to match.
		return Intrinsic::x86_xop_vpcomltq; // "86.xop.
		vpcomltq"
		case 'w': // 1 string to match.
		return Intrinsic::x86_xop_vpcomltw; // "86.xop.
		vpcomltw"
		}
		break;
		}
		break;
		case 'n': // 4 strings to match.
		if (NameR[13] != 'e')
		break;
		switch (NameR[14]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::x86_xop_vpcomneb; // "86.xop.vpcomneb
		"
		case 'd': // 1 string to match.
		return Intrinsic::x86_xop_vpcomned; // "86.xop.vpcomned
		"
		case 'q': // 1 string to match.
		return Intrinsic::x86_xop_vpcomneq; // "86.xop.vpcomneq
		"
		case 'w': // 1 string to match.
		return Intrinsic::x86_xop_vpcomnew; // "86.xop.vpcomnew
		"
		}
		break;
		}
		break;
		case 'h': // 9 strings to match.
		switch (NameR[10]) {
		default: break;
		case 'a': // 6 strings to match.
		if (NameR.substr(11, 2) != "dd")
		break;
		switch (NameR[13]) {
		default: break;
		case 'b': // 3 strings to match.
		switch (NameR[14]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_xop_vphaddbd; // "86.xop.
		vphaddbd"
		case 'q': // 1 string to match.
		return Intrinsic::x86_xop_vphaddbq; // "86.xop.
		vphaddbq"
		case 'w': // 1 string to match.
		return Intrinsic::x86_xop_vphaddbw; // "86.xop.
		vphaddbw"
		}
		break;
		case 'd': // 1 string to match.
		if (NameR[14] != 'q')
		break;
		return Intrinsic::x86_xop_vphadddq; // "86.xop.vphadddq
		"
		case 'w': // 2 strings to match.
		switch (NameR[14]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_xop_vphaddwd; // "86.xop.
		vphaddwd"
		case 'q': // 1 string to match.
		return Intrinsic::x86_xop_vphaddwq; // "86.xop.
		vphaddwq"
		}
		break;
		}
		break;
		case 's': // 3 strings to match.
		if (NameR.substr(11, 2) != "ub")
		break;
		switch (NameR[13]) {
		default: break;
		case 'b': // 1 string to match.
		if (NameR[14] != 'w')
		break;
		return Intrinsic::x86_xop_vphsubbw; // "86.xop.vphsubbw
		"
		case 'd': // 1 string to match.
		if (NameR[14] != 'q')
		break;
		return Intrinsic::x86_xop_vphsubdq; // "86.xop.vphsubdq
		"
		case 'w': // 1 string to match.
		if (NameR[14] != 'd')
		break;
		return Intrinsic::x86_xop_vphsubwd; // "86.xop.vphsubwd
		"
		}
		break;
		}
		break;
		case 'm': // 3 strings to match.
		if (NameR.substr(10, 3) != "acs")
		break;
		switch (NameR[13]) {
		default: break;
		case 'd': // 1 string to match.
		if (NameR[14] != 'd')
		break;
		return Intrinsic::x86_xop_vpmacsdd; // "86.xop.vpmacsdd
		"
		case 'w': // 2 strings to match.
		switch (NameR[14]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_xop_vpmacswd; // "86.xop.vpmacswd
		"
		case 'w': // 1 string to match.
		return Intrinsic::x86_xop_vpmacsww; // "86.xop.vpmacsww
		"
		}
		break;
		}
		break;
		}
		break;
		}
		break;
		}
		break;
		case 'c': // 1 string to match.
		if (NameR.substr(1, 14) != "ore.checkevent")
		break;
		return Intrinsic::xcore_checkevent; // "core.checkevent"
		}
		break;
		case 16: // 127 strings to match.
		if (NameR.substr(0, 3) != "86.")
		break;
		switch (NameR[3]) {
		default: break;
		case '3': // 8 strings to match.
		if (NameR.substr(4, 4) != "dnow")
		break;
		switch (NameR[8]) {
		default: break;
		case '.': // 6 strings to match.
		if (NameR[9] != 'p')
		break;
		switch (NameR[10]) {
		default: break;
		case 'a': // 1 string to match.
		if (NameR.substr(11, 5) != "vgusb")
		break;
		return Intrinsic::x86_3dnow_pavgusb; // "86.3dnow.pavgus
		b"
		case 'f': // 4 strings to match.
		switch (NameR[11]) {
		default: break;
		case 'c': // 3 strings to match.
		if (NameR.substr(12, 2) != "mp")
		break;
		switch (NameR[14]) {
		default: break;
		case 'e': // 1 string to match.
		if (NameR[15] != 'q')
		break;
		return Intrinsic::x86_3dnow_pfcmpeq; // "86.3dnow.pfcmpe
		q"
		case 'g': // 2 strings to match.
		switch (NameR[15]) {
		default: break;
		case 'e': // 1 string to match.
		return Intrinsic::x86_3dnow_pfcmpge; // "86.3dnow.pfcmpg
		e"
		case 't': // 1 string to match.
		return Intrinsic::x86_3dnow_pfcmpgt; // "86.3dnow.pfcmpg
		t"
		}
		break;
		}
		break;
		case 'r': // 1 string to match.
		if (NameR.substr(12, 4) != "sqrt")
		break;
		return Intrinsic::x86_3dnow_pfrsqrt; // "86.3dnow.pfrsqr
		t"
		}
		break;
		case 'm': // 1 string to match.
		if (NameR.substr(11, 5) != "ulhrw")
		break;
		return Intrinsic::x86_3dnow_pmulhrw; // "86.3dnow.pmulhr
		w"
		}
		break;
		case 'a': // 2 strings to match.
		if (NameR.substr(9, 2) != ".p")
		break;
		switch (NameR[11]) {
		default: break;
		case 'f': // 1 string to match.
		if (NameR.substr(12, 4) != "nacc")
		break;
		return Intrinsic::x86_3dnowa_pfnacc; // "86.3dnowa.pfnac
		c"
		case 's': // 1 string to match.
		if (NameR.substr(12, 4) != "wapd")
		break;
		return Intrinsic::x86_3dnowa_pswapd; // "86.3dnowa.pswap
		d"
		}
		break;
		}
		break;
		case 'a': // 33 strings to match.
		if (NameR.substr(4, 2) != "vx")
		break;
		switch (NameR[6]) {
		default: break;
		case '.': // 5 strings to match.
		switch (NameR[7]) {
		default: break;
		case 'd': // 1 string to match.
		if (NameR.substr(8, 8) != "p.ps.256")
		break;
		return Intrinsic::x86_avx_dp_ps_256; // "86.avx.dp.ps.25
		6"
		case 'v': // 4 strings to match.
		if (NameR.substr(8, 4) != "test")
		break;
		switch (NameR[12]) {
		default: break;
		case 'c': // 2 strings to match.
		if (NameR.substr(13, 2) != ".p")
		break;
		switch (NameR[15]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_avx_vtestc_pd; // "86.avx.vtestc.p
		d"
		case 's': // 1 string to match.
		return Intrinsic::x86_avx_vtestc_ps; // "86.avx.vtestc.p
		s"
		}
		break;
		case 'z': // 2 strings to match.
		if (NameR.substr(13, 2) != ".p")
		break;
		switch (NameR[15]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_avx_vtestz_pd; // "86.avx.vtestz.p
		d"
		case 's': // 1 string to match.
		return Intrinsic::x86_avx_vtestz_ps; // "86.avx.vtestz.p
		s"
		}
		break;
		}
		break;
		}
		break;
		case '2': // 28 strings to match.
		if (NameR[7] != '.')
		break;
		switch (NameR[8]) {
		default: break;
		case 'm': // 1 string to match.
		if (NameR.substr(9, 7) != "ovntdqa")
		break;
		return Intrinsic::x86_avx2_movntdqa; // "86.avx2.movntdq
		a"
		case 'p': // 27 strings to match.
		switch (NameR[9]) {
		default: break;
		case 'a': // 6 strings to match.
		switch (NameR[10]) {
		default: break;
		case 'c': // 4 strings to match.
		if (NameR[11] != 'k')
		break;
		switch (NameR[12]) {
		default: break;
		case 's': // 2 strings to match.
		if (NameR[13] != 's')
		break;
		switch (NameR[14]) {
		default: break;
		case 'd': // 1 string to match.
		if (NameR[15] != 'w')
		break;
		return Intrinsic::x86_avx2_packssdw; // "86.avx2
		.packssdw"
		case 'w': // 1 string to match.
		if (NameR[15] != 'b')
		break;
		return Intrinsic::x86_avx2_packsswb; // "86.avx2
		.packsswb"
		}
		break;
		case 'u': // 2 strings to match.
		if (NameR[13] != 's')
		break;
		switch (NameR[14]) {
		default: break;
		case 'd': // 1 string to match.
		if (NameR[15] != 'w')
		break;
		return Intrinsic::x86_avx2_packusdw; // "86.avx2
		.packusdw"
		case 'w': // 1 string to match.
		if (NameR[15] != 'b')
		break;
		return Intrinsic::x86_avx2_packuswb; // "86.avx2
		.packuswb"
		}
		break;
		}
		break;
		case 'd': // 2 strings to match.
		if (NameR.substr(11, 4) != "dus.")
		break;
		switch (NameR[15]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::x86_avx2_paddus_b; // "86.avx2.paddus.
		b"
		case 'w': // 1 string to match.
		return Intrinsic::x86_avx2_paddus_w; // "86.avx2.paddus.
		w"
		}
		break;
		}
		break;
		case 'b': // 1 string to match.
		if (NameR.substr(10, 6) != "lendvb")
		break;
		return Intrinsic::x86_avx2_pblendvb; // "86.avx2.pblendv
		b"
		case 'h': // 2 strings to match.
		switch (NameR[10]) {
		default: break;
		case 'a': // 1 string to match.
		if (NameR.substr(11, 5) != "dd.sw")
		break;
		return Intrinsic::x86_avx2_phadd_sw; // "86.avx2.phadd.s
		w"
		case 's': // 1 string to match.
		if (NameR.substr(11, 5) != "ub.sw")
		break;
		return Intrinsic::x86_avx2_phsub_sw; // "86.avx2.phsub.s
		w"
		}
		break;
		case 'm': // 16 strings to match.
		switch (NameR[10]) {
		default: break;
		case 'a': // 1 string to match.
		if (NameR.substr(11, 5) != "dd.wd")
		break;
		return Intrinsic::x86_avx2_pmadd_wd; // "86.avx2.pmadd.w
		d"
		case 'o': // 13 strings to match.
		if (NameR[11] != 'v')
		break;
		switch (NameR[12]) {
		default: break;
		case 'm': // 1 string to match.
		if (NameR.substr(13, 3) != "skb")
		break;
		return Intrinsic::x86_avx2_pmovmskb; // "86.avx2.pmovmsk
		b"
		case 's': // 6 strings to match.
		if (NameR[13] != 'x')
		break;
		switch (NameR[14]) {
		default: break;
		case 'b': // 3 strings to match.
		switch (NameR[15]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_avx2_pmovsxbd; // "86.avx2
		.pmovsxbd"
		case 'q': // 1 string to match.
		return Intrinsic::x86_avx2_pmovsxbq; // "86.avx2
		.pmovsxbq"
		case 'w': // 1 string to match.
		return Intrinsic::x86_avx2_pmovsxbw; // "86.avx2
		.pmovsxbw"
		}
		break;
		case 'd': // 1 string to match.
		if (NameR[15] != 'q')
		break;
		return Intrinsic::x86_avx2_pmovsxdq; // "86.avx2
		.pmovsxdq"
		case 'w': // 2 strings to match.
		switch (NameR[15]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_avx2_pmovsxwd; // "86.avx2
		.pmovsxwd"
		case 'q': // 1 string to match.
		return Intrinsic::x86_avx2_pmovsxwq; // "86.avx2
		.pmovsxwq"
		}
		break;
		}
		break;
		case 'z': // 6 strings to match.
		if (NameR[13] != 'x')
		break;
		switch (NameR[14]) {
		default: break;
		case 'b': // 3 strings to match.
		switch (NameR[15]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_avx2_pmovzxbd; // "86.avx2
		.pmovzxbd"
		case 'q': // 1 string to match.
		return Intrinsic::x86_avx2_pmovzxbq; // "86.avx2
		.pmovzxbq"
		case 'w': // 1 string to match.
		return Intrinsic::x86_avx2_pmovzxbw; // "86.avx2
		.pmovzxbw"
		}
		break;
		case 'd': // 1 string to match.
		if (NameR[15] != 'q')
		break;
		return Intrinsic::x86_avx2_pmovzxdq; // "86.avx2
		.pmovzxdq"
		case 'w': // 2 strings to match.
		switch (NameR[15]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_avx2_pmovzxwd; // "86.avx2
		.pmovzxwd"
		case 'q': // 1 string to match.
		return Intrinsic::x86_avx2_pmovzxwq; // "86.avx2
		.pmovzxwq"
		}
		break;
		}
		break;
		}
		break;
		case 'u': // 2 strings to match.
		if (NameR[11] != 'l')
		break;
		switch (NameR[12]) {
		default: break;
		case 'h': // 1 string to match.
		if (NameR.substr(13, 3) != "u.w")
		break;
		return Intrinsic::x86_avx2_pmulhu_w; // "86.avx2.pmulhu.
		w"
		case 'u': // 1 string to match.
		if (NameR.substr(13, 3) != ".dq")
		break;
		return Intrinsic::x86_avx2_pmulu_dq; // "86.avx2.pmulu.d
		q"
		}
		break;
		}
		break;
		case 's': // 2 strings to match.
		if (NameR.substr(10, 5) != "ubus.")
		break;
		switch (NameR[15]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::x86_avx2_psubus_b; // "86.avx2.psubus.
		b"
		case 'w': // 1 string to match.
		return Intrinsic::x86_avx2_psubus_w; // "86.avx2.psubus.
		w"
		}
		break;
		}
		break;
		}
		break;
		}
		break;
		case 'm': // 7 strings to match.
		if (NameR.substr(4, 4) != "mx.p")
		break;
		switch (NameR[8]) {
		default: break;
		case 'a': // 1 string to match.
		if (NameR.substr(9, 7) != "lignr.b")
		break;
		return Intrinsic::x86_mmx_palignr_b; // "86.mmx.palignr.b"
		case 'u': // 6 strings to match.
		if (NameR.substr(9, 4) != "npck")
		break;
		switch (NameR[13]) {
		default: break;
		case 'h': // 3 strings to match.
		switch (NameR[14]) {
		default: break;
		case 'b': // 1 string to match.
		if (NameR[15] != 'w')
		break;
		return Intrinsic::x86_mmx_punpckhbw; // "86.mmx.punpckhb
		w"
		case 'd': // 1 string to match.
		if (NameR[15] != 'q')
		break;
		return Intrinsic::x86_mmx_punpckhdq; // "86.mmx.punpckhd
		q"
		case 'w': // 1 string to match.
		if (NameR[15] != 'd')
		break;
		return Intrinsic::x86_mmx_punpckhwd; // "86.mmx.punpckhw
		d"
		}
		break;
		case 'l': // 3 strings to match.
		switch (NameR[14]) {
		default: break;
		case 'b': // 1 string to match.
		if (NameR[15] != 'w')
		break;
		return Intrinsic::x86_mmx_punpcklbw; // "86.mmx.punpcklb
		w"
		case 'd': // 1 string to match.
		if (NameR[15] != 'q')
		break;
		return Intrinsic::x86_mmx_punpckldq; // "86.mmx.punpckld
		q"
		case 'w': // 1 string to match.
		if (NameR[15] != 'd')
		break;
		return Intrinsic::x86_mmx_punpcklwd; // "86.mmx.punpcklw
		d"
		}
		break;
		}
		break;
		}
		break;
		case 's': // 39 strings to match.
		if (NameR[4] != 's')
		break;
		switch (NameR[5]) {
		default: break;
		case 'e': // 31 strings to match.
		switch (NameR[6]) {
		default: break;
		case '.': // 10 strings to match.
		switch (NameR[7]) {
		default: break;
		case 'c': // 8 strings to match.
		switch (NameR[8]) {
		default: break;
		case 'o': // 5 strings to match.
		if (NameR.substr(9, 2) != "mi")
		break;
		switch (NameR[11]) {
		default: break;
		case 'e': // 1 string to match.
		if (NameR.substr(12, 4) != "q.ss")
		break;
		return Intrinsic::x86_sse_comieq_ss; // "86.sse.comieq.s
		s"
		case 'g': // 2 strings to match.
		switch (NameR[12]) {
		default: break;
		case 'e': // 1 string to match.
		if (NameR.substr(13, 3) != ".ss")
		break;
		return Intrinsic::x86_sse_comige_ss; // "86.sse.
		comige.ss"
		case 't': // 1 string to match.
		if (NameR.substr(13, 3) != ".ss")
		break;
		return Intrinsic::x86_sse_comigt_ss; // "86.sse.
		comigt.ss"
		}
		break;
		case 'l': // 2 strings to match.
		switch (NameR[12]) {
		default: break;
		case 'e': // 1 string to match.
		if (NameR.substr(13, 3) != ".ss")
		break;
		return Intrinsic::x86_sse_comile_ss; // "86.sse.
		comile.ss"
		case 't': // 1 string to match.
		if (NameR.substr(13, 3) != ".ss")
		break;
		return Intrinsic::x86_sse_comilt_ss; // "86.sse.
		comilt.ss"
		}
		break;
		}
		break;
		case 'v': // 3 strings to match.
		if (NameR.substr(9, 2) != "tt")
		break;
		switch (NameR[11]) {
		default: break;
		case 'p': // 2 strings to match.
		switch (NameR[12]) {
		default: break;
		case 'd': // 1 string to match.
		if (NameR.substr(13, 3) != "2pi")
		break;
		return Intrinsic::x86_sse_cvttpd2pi; // "86.sse.
		cvttpd2pi"
		case 's': // 1 string to match.
		if (NameR.substr(13, 3) != "2pi")
		break;
		return Intrinsic::x86_sse_cvttps2pi; // "86.sse.
		cvttps2pi"
		}
		break;
		case 's': // 1 string to match.
		if (NameR.substr(12, 4) != "s2si")
		break;
		return Intrinsic::x86_sse_cvttss2si; // "86.sse.cvttss2s
		i"
		}
		break;
		}
		break;
		case 'm': // 1 string to match.
		if (NameR.substr(8, 8) != "ovmsk.ps")
		break;
		return Intrinsic::x86_sse_movmsk_ps; // "86.sse.movmsk.p
		s"
		case 's': // 1 string to match.
		if (NameR.substr(8, 8) != "toreu.ps")
		break;
		return Intrinsic::x86_sse_storeu_ps; // "86.sse.storeu.p
		s"
		}
		break;
		case '2': // 17 strings to match.
		if (NameR[7] != '.')
		break;
		switch (NameR[8]) {
		default: break;
		case 'c': // 10 strings to match.
		if (NameR.substr(9, 2) != "vt")
		break;
		switch (NameR[11]) {
		default: break;
		case 'd': // 2 strings to match.
		if (NameR.substr(12, 3) != "q2p")
		break;
		switch (NameR[15]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_sse2_cvtdq2pd; // "86.sse2.cvtdq2p
		d"
		case 's': // 1 string to match.
		return Intrinsic::x86_sse2_cvtdq2ps; // "86.sse2.cvtdq2p
		s"
		}
		break;
		case 'p': // 4 strings to match.
		switch (NameR[12]) {
		default: break;
		case 'd': // 2 strings to match.
		if (NameR[13] != '2')
		break;
		switch (NameR[14]) {
		default: break;
		case 'd': // 1 string to match.
		if (NameR[15] != 'q')
		break;
		return Intrinsic::x86_sse2_cvtpd2dq; // "86.sse2
		.cvtpd2dq"
		case 'p': // 1 string to match.
		if (NameR[15] != 's')
		break;
		return Intrinsic::x86_sse2_cvtpd2ps; // "86.sse2
		.cvtpd2ps"
		}
		break;
		case 's': // 2 strings to match.
		if (NameR[13] != '2')
		break;
		switch (NameR[14]) {
		default: break;
		case 'd': // 1 string to match.
		if (NameR[15] != 'q')
		break;
		return Intrinsic::x86_sse2_cvtps2dq; // "86.sse2
		.cvtps2dq"
		case 'p': // 1 string to match.
		if (NameR[15] != 'd')
		break;
		return Intrinsic::x86_sse2_cvtps2pd; // "86.sse2
		.cvtps2pd"
		}
		break;
		}
		break;
		case 's': // 4 strings to match.
		switch (NameR[12]) {
		default: break;
		case 'd': // 2 strings to match.
		if (NameR.substr(13, 2) != "2s")
		break;
		switch (NameR[15]) {
		default: break;
		case 'i': // 1 string to match.
		return Intrinsic::x86_sse2_cvtsd2si; // "86.sse2
		.cvtsd2si"
		case 's': // 1 string to match.
		return Intrinsic::x86_sse2_cvtsd2ss; // "86.sse2
		.cvtsd2ss"
		}
		break;
		case 'i': // 1 string to match.
		if (NameR.substr(13, 3) != "2sd")
		break;
		return Intrinsic::x86_sse2_cvtsi2sd; // "86.sse2.cvtsi2s
		d"
		case 's': // 1 string to match.
		if (NameR.substr(13, 3) != "2sd")
		break;
		return Intrinsic::x86_sse2_cvtss2sd; // "86.sse2.cvtss2s
		d"
		}
		break;
		}
		break;
		case 'p': // 7 strings to match.
		switch (NameR[9]) {
		default: break;
		case 'a': // 2 strings to match.
		if (NameR.substr(10, 5) != "ddus.")
		break;
		switch (NameR[15]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::x86_sse2_paddus_b; // "86.sse2.paddus.
		b"
		case 'w': // 1 string to match.
		return Intrinsic::x86_sse2_paddus_w; // "86.sse2.paddus.
		w"
		}
		break;
		case 'm': // 3 strings to match.
		switch (NameR[10]) {
		default: break;
		case 'a': // 1 string to match.
		if (NameR.substr(11, 5) != "dd.wd")
		break;
		return Intrinsic::x86_sse2_pmadd_wd; // "86.sse2.pmadd.w
		d"
		case 'u': // 2 strings to match.
		if (NameR[11] != 'l')
		break;
		switch (NameR[12]) {
		default: break;
		case 'h': // 1 string to match.
		if (NameR.substr(13, 3) != "u.w")
		break;
		return Intrinsic::x86_sse2_pmulhu_w; // "86.sse2
		.pmulhu.w"
		case 'u': // 1 string to match.
		if (NameR.substr(13, 3) != ".dq")
		break;
		return Intrinsic::x86_sse2_pmulu_dq; // "86.sse2
		.pmulu.dq"
		}
		break;
		}
		break;
		case 's': // 2 strings to match.
		if (NameR.substr(10, 5) != "ubus.")
		break;
		switch (NameR[15]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::x86_sse2_psubus_b; // "86.sse2.psubus.
		b"
		case 'w': // 1 string to match.
		return Intrinsic::x86_sse2_psubus_w; // "86.sse2.psubus.
		w"
		}
		break;
		}
		break;
		}
		break;
		case '4': // 4 strings to match.
		if (NameR.substr(7, 2) != "1.")
		break;
		switch (NameR[9]) {
		default: break;
		case 'b': // 2 strings to match.
		if (NameR.substr(10, 5) != "lendp")
		break;
		switch (NameR[15]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_sse41_blendpd; // "86.sse41.blendp
		d"
		case 's': // 1 string to match.
		return Intrinsic::x86_sse41_blendps; // "86.sse41.blendp
		s"
		}
		break;
		case 'm': // 1 string to match.
		if (NameR.substr(10, 6) != "psadbw")
		break;
		return Intrinsic::x86_sse41_mpsadbw; // "86.sse41.mpsadb
		w"
		case 'p': // 1 string to match.
		if (NameR.substr(10, 6) != "blendw")
		break;
		return Intrinsic::x86_sse41_pblendw; // "86.sse41.pblend
		w"
		}
		break;
		}
		break;
		case 's': // 8 strings to match.
		if (NameR.substr(6, 4) != "e3.p")
		break;
		switch (NameR[10]) {
		default: break;
		case 'h': // 4 strings to match.
		switch (NameR[11]) {
		default: break;
		case 'a': // 2 strings to match.
		if (NameR.substr(12, 3) != "dd.")
		break;
		switch (NameR[15]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_ssse3_phadd_d; // "86.ssse3.phadd.
		d"
		case 'w': // 1 string to match.
		return Intrinsic::x86_ssse3_phadd_w; // "86.ssse3.phadd.
		w"
		}
		break;
		case 's': // 2 strings to match.
		if (NameR.substr(12, 3) != "ub.")
		break;
		switch (NameR[15]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_ssse3_phsub_d; // "86.ssse3.phsub.
		d"
		case 'w': // 1 string to match.
		return Intrinsic::x86_ssse3_phsub_w; // "86.ssse3.phsub.
		w"
		}
		break;
		}
		break;
		case 's': // 4 strings to match.
		switch (NameR[11]) {
		default: break;
		case 'h': // 1 string to match.
		if (NameR.substr(12, 4) != "uf.b")
		break;
		return Intrinsic::x86_ssse3_pshuf_b; // "86.ssse3.pshuf.
		b"
		case 'i': // 3 strings to match.
		if (NameR.substr(12, 3) != "gn.")
		break;
		switch (NameR[15]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::x86_ssse3_psign_b; // "86.ssse3.psign.
		b"
		case 'd': // 1 string to match.
		return Intrinsic::x86_ssse3_psign_d; // "86.ssse3.psign.
		d"
		case 'w': // 1 string to match.
		return Intrinsic::x86_ssse3_psign_w; // "86.ssse3.psign.
		w"
		}
		break;
		}
		break;
		}
		break;
		}
		break;
		case 'v': // 4 strings to match.
		if (NameR.substr(4, 4) != "cvtp")
		break;
		switch (NameR[8]) {
		default: break;
		case 'h': // 2 strings to match.
		if (NameR.substr(9, 4) != "2ps.")
		break;
		switch (NameR[13]) {
		default: break;
		case '1': // 1 string to match.
		if (NameR.substr(14, 2) != "28")
		break;
		return Intrinsic::x86_vcvtph2ps_128; // "86.vcvtph2ps.12
		8"
		case '2': // 1 string to match.
		if (NameR.substr(14, 2) != "56")
		break;
		return Intrinsic::x86_vcvtph2ps_256; // "86.vcvtph2ps.25
		6"
		}
		break;
		case 's': // 2 strings to match.
		if (NameR.substr(9, 4) != "2ph.")
		break;
		switch (NameR[13]) {
		default: break;
		case '1': // 1 string to match.
		if (NameR.substr(14, 2) != "28")
		break;
		return Intrinsic::x86_vcvtps2ph_128; // "86.vcvtps2ph.12
		8"
		case '2': // 1 string to match.
		if (NameR.substr(14, 2) != "56")
		break;
		return Intrinsic::x86_vcvtps2ph_256; // "86.vcvtps2ph.25
		6"
		}
		break;
		}
		break;
		case 'x': // 36 strings to match.
		if (NameR.substr(4, 5) != "op.vp")
		break;
		switch (NameR[9]) {
		default: break;
		case 'c': // 24 strings to match.
		if (NameR.substr(10, 2) != "om")
		break;
		switch (NameR[12]) {
		default: break;
		case 'e': // 4 strings to match.
		if (NameR.substr(13, 2) != "qu")
		break;
		switch (NameR[15]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::x86_xop_vpcomequb; // "86.xop.vpcomequ
		b"
		case 'd': // 1 string to match.
		return Intrinsic::x86_xop_vpcomequd; // "86.xop.vpcomequ
		d"
		case 'q': // 1 string to match.
		return Intrinsic::x86_xop_vpcomequq; // "86.xop.vpcomequ
		q"
		case 'w': // 1 string to match.
		return Intrinsic::x86_xop_vpcomequw; // "86.xop.vpcomequ
		w"
		}
		break;
		case 'g': // 8 strings to match.
		switch (NameR[13]) {
		default: break;
		case 'e': // 4 strings to match.
		if (NameR[14] != 'u')
		break;
		switch (NameR[15]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::x86_xop_vpcomgeub; // "86.xop.vpcomgeu
		b"
		case 'd': // 1 string to match.
		return Intrinsic::x86_xop_vpcomgeud; // "86.xop.vpcomgeu
		d"
		case 'q': // 1 string to match.
		return Intrinsic::x86_xop_vpcomgeuq; // "86.xop.vpcomgeu
		q"
		case 'w': // 1 string to match.
		return Intrinsic::x86_xop_vpcomgeuw; // "86.xop.vpcomgeu
		w"
		}
		break;
		case 't': // 4 strings to match.
		if (NameR[14] != 'u')
		break;
		switch (NameR[15]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::x86_xop_vpcomgtub; // "86.xop.vpcomgtu
		b"
		case 'd': // 1 string to match.
		return Intrinsic::x86_xop_vpcomgtud; // "86.xop.vpcomgtu
		d"
		case 'q': // 1 string to match.
		return Intrinsic::x86_xop_vpcomgtuq; // "86.xop.vpcomgtu
		q"
		case 'w': // 1 string to match.
		return Intrinsic::x86_xop_vpcomgtuw; // "86.xop.vpcomgtu
		w"
		}
		break;
		}
		break;
		case 'l': // 8 strings to match.
		switch (NameR[13]) {
		default: break;
		case 'e': // 4 strings to match.
		if (NameR[14] != 'u')
		break;
		switch (NameR[15]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::x86_xop_vpcomleub; // "86.xop.vpcomleu
		b"
		case 'd': // 1 string to match.
		return Intrinsic::x86_xop_vpcomleud; // "86.xop.vpcomleu
		d"
		case 'q': // 1 string to match.
		return Intrinsic::x86_xop_vpcomleuq; // "86.xop.vpcomleu
		q"
		case 'w': // 1 string to match.
		return Intrinsic::x86_xop_vpcomleuw; // "86.xop.vpcomleu
		w"
		}
		break;
		case 't': // 4 strings to match.
		if (NameR[14] != 'u')
		break;
		switch (NameR[15]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::x86_xop_vpcomltub; // "86.xop.vpcomltu
		b"
		case 'd': // 1 string to match.
		return Intrinsic::x86_xop_vpcomltud; // "86.xop.vpcomltu
		d"
		case 'q': // 1 string to match.
		return Intrinsic::x86_xop_vpcomltuq; // "86.xop.vpcomltu
		q"
		case 'w': // 1 string to match.
		return Intrinsic::x86_xop_vpcomltuw; // "86.xop.vpcomltu
		w"
		}
		break;
		}
		break;
		case 'n': // 4 strings to match.
		if (NameR.substr(13, 2) != "eu")
		break;
		switch (NameR[15]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::x86_xop_vpcomneub; // "86.xop.vpcomneu
		b"
		case 'd': // 1 string to match.
		return Intrinsic::x86_xop_vpcomneud; // "86.xop.vpcomneu
		d"
		case 'q': // 1 string to match.
		return Intrinsic::x86_xop_vpcomneuq; // "86.xop.vpcomneu
		q"
		case 'w': // 1 string to match.
		return Intrinsic::x86_xop_vpcomneuw; // "86.xop.vpcomneu
		w"
		}
		break;
		}
		break;
		case 'h': // 6 strings to match.
		if (NameR.substr(10, 4) != "addu")
		break;
		switch (NameR[14]) {
		default: break;
		case 'b': // 3 strings to match.
		switch (NameR[15]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_xop_vphaddubd; // "86.xop.vphaddub
		d"
		case 'q': // 1 string to match.
		return Intrinsic::x86_xop_vphaddubq; // "86.xop.vphaddub
		q"
		case 'w': // 1 string to match.
		return Intrinsic::x86_xop_vphaddubw; // "86.xop.vphaddub
		w"
		}
		break;
		case 'd': // 1 string to match.
		if (NameR[15] != 'q')
		break;
		return Intrinsic::x86_xop_vphaddudq; // "86.xop.vphaddud
		q"
		case 'w': // 2 strings to match.
		switch (NameR[15]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_xop_vphadduwd; // "86.xop.vphadduw
		d"
		case 'q': // 1 string to match.
		return Intrinsic::x86_xop_vphadduwq; // "86.xop.vphadduw
		q"
		}
		break;
		}
		break;
		case 'm': // 6 strings to match.
		if (NameR[10] != 'a')
		break;
		switch (NameR[11]) {
		default: break;
		case 'c': // 5 strings to match.
		if (NameR[12] != 's')
		break;
		switch (NameR[13]) {
		default: break;
		case 'd': // 2 strings to match.
		if (NameR[14] != 'q')
		break;
		switch (NameR[15]) {
		default: break;
		case 'h': // 1 string to match.
		return Intrinsic::x86_xop_vpmacsdqh; // "86.xop.vpmacsdq
		h"
		case 'l': // 1 string to match.
		return Intrinsic::x86_xop_vpmacsdql; // "86.xop.vpmacsdq
		l"
		}
		break;
		case 's': // 3 strings to match.
		switch (NameR[14]) {
		default: break;
		case 'd': // 1 string to match.
		if (NameR[15] != 'd')
		break;
		return Intrinsic::x86_xop_vpmacssdd; // "86.xop.vpmacssd
		d"
		case 'w': // 2 strings to match.
		switch (NameR[15]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_xop_vpmacsswd; // "86.xop.vpmacssw
		d"
		case 'w': // 1 string to match.
		return Intrinsic::x86_xop_vpmacssww; // "86.xop.vpmacssw
		w"
		}
		break;
		}
		break;
		}
		break;
		case 'd': // 1 string to match.
		if (NameR.substr(12, 4) != "cswd")
		break;
		return Intrinsic::x86_xop_vpmadcswd; // "86.xop.vpmadcsw
		d"
		}
		break;
		}
		break;
		}
		break;
		case 17: // 80 strings to match.
		if (NameR.substr(0, 3) != "86.")
		break;
		switch (NameR[3]) {
		default: break;
		case '3': // 4 strings to match.
		if (NameR.substr(4, 4) != "dnow")
		break;
		switch (NameR[8]) {
		default: break;
		case '.': // 3 strings to match.
		if (NameR.substr(9, 3) != "pfr")
		break;
		switch (NameR[12]) {
		default: break;
		case 'c': // 2 strings to match.
		if (NameR.substr(13, 3) != "pit")
		break;
		switch (NameR[16]) {
		default: break;
		case '1': // 1 string to match.
		return Intrinsic::x86_3dnow_pfrcpit1; // "86.3dnow.pfrcpi
		t1"
		case '2': // 1 string to match.
		return Intrinsic::x86_3dnow_pfrcpit2; // "86.3dnow.pfrcpi
		t2"
		}
		break;
		case 's': // 1 string to match.
		if (NameR.substr(13, 4) != "qit1")
		break;
		return Intrinsic::x86_3dnow_pfrsqit1; // "86.3dnow.pfrsqi
		t1"
		}
		break;
		case 'a': // 1 string to match.
		if (NameR.substr(9, 8) != ".pfpnacc")
		break;
		return Intrinsic::x86_3dnowa_pfpnacc; // "86.3dnowa.pfpna
		cc"
		}
		break;
		case 'a': // 11 strings to match.
		if (NameR.substr(4, 3) != "vx.")
		break;
		switch (NameR[7]) {
		default: break;
		case 'c': // 2 strings to match.
		if (NameR.substr(8, 4) != "mp.p")
		break;
		switch (NameR[12]) {
		default: break;
		case 'd': // 1 string to match.
		if (NameR.substr(13, 4) != ".256")
		break;
		return Intrinsic::x86_avx_cmp_pd_256; // "86.avx.cmp.pd.2
		56"
		case 's': // 1 string to match.
		if (NameR.substr(13, 4) != ".256")
		break;
		return Intrinsic::x86_avx_cmp_ps_256; // "86.avx.cmp.ps.2
		56"
		}
		break;
		case 'l': // 1 string to match.
		if (NameR.substr(8, 9) != "du.dq.256")
		break;
		return Intrinsic::x86_avx_ldu_dq_256; // "86.avx.ldu.dq.2
		56"
		case 'm': // 4 strings to match.
		switch (NameR[8]) {
		default: break;
		case 'a': // 2 strings to match.
		if (NameR.substr(9, 3) != "x.p")
		break;
		switch (NameR[12]) {
		default: break;
		case 'd': // 1 string to match.
		if (NameR.substr(13, 4) != ".256")
		break;
		return Intrinsic::x86_avx_max_pd_256; // "86.avx.max.pd.2
		56"
		case 's': // 1 string to match.
		if (NameR.substr(13, 4) != ".256")
		break;
		return Intrinsic::x86_avx_max_ps_256; // "86.avx.max.ps.2
		56"
		}
		break;
		case 'i': // 2 strings to match.
		if (NameR.substr(9, 3) != "n.p")
		break;
		switch (NameR[12]) {
		default: break;
		case 'd': // 1 string to match.
		if (NameR.substr(13, 4) != ".256")
		break;
		return Intrinsic::x86_avx_min_pd_256; // "86.avx.min.pd.2
		56"
		case 's': // 1 string to match.
		if (NameR.substr(13, 4) != ".256")
		break;
		return Intrinsic::x86_avx_min_ps_256; // "86.avx.min.ps.2
		56"
		}
		break;
		}
		break;
		case 'p': // 2 strings to match.
		if (NameR.substr(8, 4) != "test")
		break;
		switch (NameR[12]) {
		default: break;
		case 'c': // 1 string to match.
		if (NameR.substr(13, 4) != ".256")
		break;
		return Intrinsic::x86_avx_ptestc_256; // "86.avx.ptestc.2
		56"
		case 'z': // 1 string to match.
		if (NameR.substr(13, 4) != ".256")
		break;
		return Intrinsic::x86_avx_ptestz_256; // "86.avx.ptestz.2
		56"
		}
		break;
		case 'r': // 1 string to match.
		if (NameR.substr(8, 9) != "cp.ps.256")
		break;
		return Intrinsic::x86_avx_rcp_ps_256; // "86.avx.rcp.ps.2
		56"
		case 'v': // 1 string to match.
		if (NameR.substr(8, 9) != "zeroupper")
		break;
		return Intrinsic::x86_avx_vzeroupper; // "86.avx.vzeroupp
		er"
		}
		break;
		case 'f': // 8 strings to match.
		if (NameR.substr(4, 7) != "ma4.vfm")
		break;
		switch (NameR[11]) {
		default: break;
		case 'a': // 4 strings to match.
		if (NameR.substr(12, 3) != "dd.")
		break;
		switch (NameR[15]) {
		default: break;
		case 'p': // 2 strings to match.
		switch (NameR[16]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_fma4_vfmadd_pd; // "86.fma4.vfmadd.
		pd"
		case 's': // 1 string to match.
		return Intrinsic::x86_fma4_vfmadd_ps; // "86.fma4.vfmadd.
		ps"
		}
		break;
		case 's': // 2 strings to match.
		switch (NameR[16]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_fma4_vfmadd_sd; // "86.fma4.vfmadd.
		sd"
		case 's': // 1 string to match.
		return Intrinsic::x86_fma4_vfmadd_ss; // "86.fma4.vfmadd.
		ss"
		}
		break;
		}
		break;
		case 's': // 4 strings to match.
		if (NameR.substr(12, 3) != "ub.")
		break;
		switch (NameR[15]) {
		default: break;
		case 'p': // 2 strings to match.
		switch (NameR[16]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_fma4_vfmsub_pd; // "86.fma4.vfmsub.
		pd"
		case 's': // 1 string to match.
		return Intrinsic::x86_fma4_vfmsub_ps; // "86.fma4.vfmsub.
		ps"
		}
		break;
		case 's': // 2 strings to match.
		switch (NameR[16]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_fma4_vfmsub_sd; // "86.fma4.vfmsub.
		sd"
		case 's': // 1 string to match.
		return Intrinsic::x86_fma4_vfmsub_ss; // "86.fma4.vfmsub.
		ss"
		}
		break;
		}
		break;
		}
		break;
		case 's': // 47 strings to match.
		if (NameR[4] != 's')
		break;
		switch (NameR[5]) {
		default: break;
		case 'e': // 45 strings to match.
		switch (NameR[6]) {
		default: break;
		case '.': // 8 strings to match.
		switch (NameR[7]) {
		default: break;
		case 'c': // 3 strings to match.
		switch (NameR[8]) {
		default: break;
		case 'o': // 1 string to match.
		if (NameR.substr(9, 8) != "mineq.ss")
		break;
		return Intrinsic::x86_sse_comineq_ss; // "86.sse.comineq.
		ss"
		case 'v': // 2 strings to match.
		if (NameR.substr(9, 2) != "ts")
		break;
		switch (NameR[11]) {
		default: break;
		case 'i': // 1 string to match.
		if (NameR.substr(12, 5) != "642ss")
		break;
		return Intrinsic::x86_sse_cvtsi642ss; // "86.sse.
		cvtsi642ss"
		case 's': // 1 string to match.
		if (NameR.substr(12, 5) != "2si64")
		break;
		return Intrinsic::x86_sse_cvtss2si64; // "86.sse.
		cvtss2si64"
		}
		break;
		}
		break;
		case 'u': // 5 strings to match.
		if (NameR.substr(8, 4) != "comi")
		break;
		switch (NameR[12]) {
		default: break;
		case 'e': // 1 string to match.
		if (NameR.substr(13, 4) != "q.ss")
		break;
		return Intrinsic::x86_sse_ucomieq_ss; // "86.sse.ucomieq.
		ss"
		case 'g': // 2 strings to match.
		switch (NameR[13]) {
		default: break;
		case 'e': // 1 string to match.
		if (NameR.substr(14, 3) != ".ss")
		break;
		return Intrinsic::x86_sse_ucomige_ss; // "86.sse.
		ucomige.ss"
		case 't': // 1 string to match.
		if (NameR.substr(14, 3) != ".ss")
		break;
		return Intrinsic::x86_sse_ucomigt_ss; // "86.sse.
		ucomigt.ss"
		}
		break;
		case 'l': // 2 strings to match.
		switch (NameR[13]) {
		default: break;
		case 'e': // 1 string to match.
		if (NameR.substr(14, 3) != ".ss")
		break;
		return Intrinsic::x86_sse_ucomile_ss; // "86.sse.
		ucomile.ss"
		case 't': // 1 string to match.
		if (NameR.substr(14, 3) != ".ss")
		break;
		return Intrinsic::x86_sse_ucomilt_ss; // "86.sse.
		ucomilt.ss"
		}
		break;
		}
		break;
		}
		break;
		case '2': // 12 strings to match.
		if (NameR[7] != '.')
		break;
		switch (NameR[8]) {
		default: break;
		case 'c': // 8 strings to match.
		switch (NameR[9]) {
		default: break;
		case 'o': // 5 strings to match.
		if (NameR.substr(10, 2) != "mi")
		break;
		switch (NameR[12]) {
		default: break;
		case 'e': // 1 string to match.
		if (NameR.substr(13, 4) != "q.sd")
		break;
		return Intrinsic::x86_sse2_comieq_sd; // "86.sse2
		.comieq.sd"
		case 'g': // 2 strings to match.
		switch (NameR[13]) {
		default: break;
		case 'e': // 1 string to match.
		if (NameR.substr(14, 3) != ".sd")
		break;
		return Intrinsic::x86_sse2_comige_sd; // "86.sse2
		.comige.sd"
		case 't': // 1 string to match.
		if (NameR.substr(14, 3) != ".sd")
		break;
		return Intrinsic::x86_sse2_comigt_sd; // "86.sse2
		.comigt.sd"
		}
		break;
		case 'l': // 2 strings to match.
		switch (NameR[13]) {
		default: break;
		case 'e': // 1 string to match.
		if (NameR.substr(14, 3) != ".sd")
		break;
		return Intrinsic::x86_sse2_comile_sd; // "86.sse2
		.comile.sd"
		case 't': // 1 string to match.
		if (NameR.substr(14, 3) != ".sd")
		break;
		return Intrinsic::x86_sse2_comilt_sd; // "86.sse2
		.comilt.sd"
		}
		break;
		}
		break;
		case 'v': // 3 strings to match.
		if (NameR.substr(10, 2) != "tt")
		break;
		switch (NameR[12]) {
		default: break;
		case 'p': // 2 strings to match.
		switch (NameR[13]) {
		default: break;
		case 'd': // 1 string to match.
		if (NameR.substr(14, 3) != "2dq")
		break;
		return Intrinsic::x86_sse2_cvttpd2dq; // "86.sse2
		.cvttpd2dq"
		case 's': // 1 string to match.
		if (NameR.substr(14, 3) != "2dq")
		break;
		return Intrinsic::x86_sse2_cvttps2dq; // "86.sse2
		.cvttps2dq"
		}
		break;
		case 's': // 1 string to match.
		if (NameR.substr(13, 4) != "d2si")
		break;
		return Intrinsic::x86_sse2_cvttsd2si; // "86.sse2
		.cvttsd2si"
		}
		break;
		}
		break;
		case 'm': // 1 string to match.
		if (NameR.substr(9, 8) != "ovmsk.pd")
		break;
		return Intrinsic::x86_sse2_movmsk_pd; // "86.sse2.movmsk.
		pd"
		case 's': // 3 strings to match.
		if (NameR.substr(9, 4) != "tore")
		break;
		switch (NameR[13]) {
		default: break;
		case 'l': // 1 string to match.
		if (NameR.substr(14, 3) != ".dq")
		break;
		return Intrinsic::x86_sse2_storel_dq; // "86.sse2.storel.
		dq"
		case 'u': // 2 strings to match.
		if (NameR[14] != '.')
		break;
		switch (NameR[15]) {
		default: break;
		case 'd': // 1 string to match.
		if (NameR[16] != 'q')
		break;
		return Intrinsic::x86_sse2_storeu_dq; // "86.sse2
		.storeu.dq"
		case 'p': // 1 string to match.
		if (NameR[16] != 'd')
		break;
		return Intrinsic::x86_sse2_storeu_pd; // "86.sse2
		.storeu.pd"
		}
		break;
		}
		break;
		}
		break;
		case '3': // 2 strings to match.
		if (NameR.substr(7, 9) != ".addsub.p")
		break;
		switch (NameR[16]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_sse3_addsub_pd; // "86.sse3.addsub.
		pd"
		case 's': // 1 string to match.
		return Intrinsic::x86_sse3_addsub_ps; // "86.sse3.addsub.
		ps"
		}
		break;
		case '4': // 23 strings to match.
		if (NameR.substr(7, 2) != "1.")
		break;
		switch (NameR[9]) {
		default: break;
		case 'b': // 2 strings to match.
		if (NameR.substr(10, 6) != "lendvp")
		break;
		switch (NameR[16]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_sse41_blendvpd; // "86.sse41.blendv
		pd"
		case 's': // 1 string to match.
		return Intrinsic::x86_sse41_blendvps; // "86.sse41.blendv
		ps"
		}
		break;
		case 'i': // 1 string to match.
		if (NameR.substr(10, 7) != "nsertps")
		break;
		return Intrinsic::x86_sse41_insertps; // "86.sse41.insert
		ps"
		case 'm': // 1 string to match.
		if (NameR.substr(10, 7) != "ovntdqa")
		break;
		return Intrinsic::x86_sse41_movntdqa; // "86.sse41.movntd
		qa"
		case 'p': // 15 strings to match.
		switch (NameR[10]) {
		default: break;
		case 'a': // 1 string to match.
		if (NameR.substr(11, 6) != "ckusdw")
		break;
		return Intrinsic::x86_sse41_packusdw; // "86.sse41.packus
		dw"
		case 'b': // 1 string to match.
		if (NameR.substr(11, 6) != "lendvb")
		break;
		return Intrinsic::x86_sse41_pblendvb; // "86.sse41.pblend
		vb"
		case 'm': // 12 strings to match.
		if (NameR.substr(11, 2) != "ov")
		break;
		switch (NameR[13]) {
		default: break;
		case 's': // 6 strings to match.
		if (NameR[14] != 'x')
		break;
		switch (NameR[15]) {
		default: break;
		case 'b': // 3 strings to match.
		switch (NameR[16]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_sse41_pmovsxbd; // "86.sse4
		1.pmovsxbd"
		case 'q': // 1 string to match.
		return Intrinsic::x86_sse41_pmovsxbq; // "86.sse4
		1.pmovsxbq"
		case 'w': // 1 string to match.
		return Intrinsic::x86_sse41_pmovsxbw; // "86.sse4
		1.pmovsxbw"
		}
		break;
		case 'd': // 1 string to match.
		if (NameR[16] != 'q')
		break;
		return Intrinsic::x86_sse41_pmovsxdq; // "86.sse4
		1.pmovsxdq"
		case 'w': // 2 strings to match.
		switch (NameR[16]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_sse41_pmovsxwd; // "86.sse4
		1.pmovsxwd"
		case 'q': // 1 string to match.
		return Intrinsic::x86_sse41_pmovsxwq; // "86.sse4
		1.pmovsxwq"
		}
		break;
		}
		break;
		case 'z': // 6 strings to match.
		if (NameR[14] != 'x')
		break;
		switch (NameR[15]) {
		default: break;
		case 'b': // 3 strings to match.
		switch (NameR[16]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_sse41_pmovzxbd; // "86.sse4
		1.pmovzxbd"
		case 'q': // 1 string to match.
		return Intrinsic::x86_sse41_pmovzxbq; // "86.sse4
		1.pmovzxbq"
		case 'w': // 1 string to match.
		return Intrinsic::x86_sse41_pmovzxbw; // "86.sse4
		1.pmovzxbw"
		}
		break;
		case 'd': // 1 string to match.
		if (NameR[16] != 'q')
		break;
		return Intrinsic::x86_sse41_pmovzxdq; // "86.sse4
		1.pmovzxdq"
		case 'w': // 2 strings to match.
		switch (NameR[16]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_sse41_pmovzxwd; // "86.sse4
		1.pmovzxwd"
		case 'q': // 1 string to match.
		return Intrinsic::x86_sse41_pmovzxwq; // "86.sse4
		1.pmovzxwq"
		}
		break;
		}
		break;
		}
		break;
		case 't': // 1 string to match.
		if (NameR.substr(11, 6) != "estnzc")
		break;
		return Intrinsic::x86_sse41_ptestnzc; // "86.sse41.ptestn
		zc"
		}
		break;
		case 'r': // 4 strings to match.
		if (NameR.substr(10, 5) != "ound.")
		break;
		switch (NameR[15]) {
		default: break;
		case 'p': // 2 strings to match.
		switch (NameR[16]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_sse41_round_pd; // "86.sse4
		1.round.pd"
		case 's': // 1 string to match.
		return Intrinsic::x86_sse41_round_ps; // "86.sse4
		1.round.ps"
		}
		break;
		case 's': // 2 strings to match.
		switch (NameR[16]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_sse41_round_sd; // "86.sse4
		1.round.sd"
		case 's': // 1 string to match.
		return Intrinsic::x86_sse41_round_ss; // "86.sse4
		1.round.ss"
		}
		break;
		}
		break;
		}
		break;
		}
		break;
		case 's': // 2 strings to match.
		if (NameR.substr(6, 5) != "e3.ph")
		break;
		switch (NameR[11]) {
		default: break;
		case 'a': // 1 string to match.
		if (NameR.substr(12, 5) != "dd.sw")
		break;
		return Intrinsic::x86_ssse3_phadd_sw; // "86.ssse3.phadd.
		sw"
		case 's': // 1 string to match.
		if (NameR.substr(12, 5) != "ub.sw")
		break;
		return Intrinsic::x86_ssse3_phsub_sw; // "86.ssse3.phsub.
		sw"
		}
		break;
		}
		break;
		case 'x': // 10 strings to match.
		if (NameR.substr(4, 5) != "op.vp")
		break;
		switch (NameR[9]) {
		default: break;
		case 'c': // 5 strings to match.
		switch (NameR[10]) {
		default: break;
		case 'm': // 1 string to match.
		if (NameR.substr(11, 6) != "ov.256")
		break;
		return Intrinsic::x86_xop_vpcmov_256; // "86.xop.vpcmov.2
		56"
		case 'o': // 4 strings to match.
		if (NameR.substr(11, 5) != "mtrue")
		break;
		switch (NameR[16]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::x86_xop_vpcomtrueb; // "86.xop.vpcomtru
		eb"
		case 'd': // 1 string to match.
		return Intrinsic::x86_xop_vpcomtrued; // "86.xop.vpcomtru
		ed"
		case 'q': // 1 string to match.
		return Intrinsic::x86_xop_vpcomtrueq; // "86.xop.vpcomtru
		eq"
		case 'w': // 1 string to match.
		return Intrinsic::x86_xop_vpcomtruew; // "86.xop.vpcomtru
		ew"
		}
		break;
		}
		break;
		case 'e': // 2 strings to match.
		if (NameR.substr(10, 6) != "rmil2p")
		break;
		switch (NameR[16]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_xop_vpermil2pd; // "86.xop.vpermil2
		pd"
		case 's': // 1 string to match.
		return Intrinsic::x86_xop_vpermil2ps; // "86.xop.vpermil2
		ps"
		}
		break;
		case 'm': // 3 strings to match.
		if (NameR[10] != 'a')
		break;
		switch (NameR[11]) {
		default: break;
		case 'c': // 2 strings to match.
		if (NameR.substr(12, 4) != "ssdq")
		break;
		switch (NameR[16]) {
		default: break;
		case 'h': // 1 string to match.
		return Intrinsic::x86_xop_vpmacssdqh; // "86.xop.vpmacssd
		qh"
		case 'l': // 1 string to match.
		return Intrinsic::x86_xop_vpmacssdql; // "86.xop.vpmacssd
		ql"
		}
		break;
		case 'd': // 1 string to match.
		if (NameR.substr(12, 5) != "csswd")
		break;
		return Intrinsic::x86_xop_vpmadcsswd; // "86.xop.vpmadcss
		wd"
		}
		break;
		}
		break;
		}
		break;
		case 18: // 45 strings to match.
		if (NameR.substr(0, 3) != "86.")
		break;
		switch (NameR[3]) {
		default: break;
		case 'a': // 16 strings to match.
		if (NameR.substr(4, 2) != "vx")
		break;
		switch (NameR[6]) {
		default: break;
		case '.': // 10 strings to match.
		switch (NameR[7]) {
		default: break;
		case 'h': // 4 strings to match.
		switch (NameR[8]) {
		default: break;
		case 'a': // 2 strings to match.
		if (NameR.substr(9, 4) != "dd.p")
		break;
		switch (NameR[13]) {
		default: break;
		case 'd': // 1 string to match.
		if (NameR.substr(14, 4) != ".256")
		break;
		return Intrinsic::x86_avx_hadd_pd_256; // "86.avx.hadd.pd.
		256"
		case 's': // 1 string to match.
		if (NameR.substr(14, 4) != ".256")
		break;
		return Intrinsic::x86_avx_hadd_ps_256; // "86.avx.hadd.ps.
		256"
		}
		break;
		case 's': // 2 strings to match.
		if (NameR.substr(9, 4) != "ub.p")
		break;
		switch (NameR[13]) {
		default: break;
		case 'd': // 1 string to match.
		if (NameR.substr(14, 4) != ".256")
		break;
		return Intrinsic::x86_avx_hsub_pd_256; // "86.avx.hsub.pd.
		256"
		case 's': // 1 string to match.
		if (NameR.substr(14, 4) != ".256")
		break;
		return Intrinsic::x86_avx_hsub_ps_256; // "86.avx.hsub.ps.
		256"
		}
		break;
		}
		break;
		case 'm': // 2 strings to match.
		if (NameR.substr(8, 9) != "askload.p")
		break;
		switch (NameR[17]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_avx_maskload_pd; // "86.avx.maskload
		.pd"
		case 's': // 1 string to match.
		return Intrinsic::x86_avx_maskload_ps; // "86.avx.maskload
		.ps"
		}
		break;
		case 's': // 2 strings to match.
		if (NameR.substr(8, 5) != "qrt.p")
		break;
		switch (NameR[13]) {
		default: break;
		case 'd': // 1 string to match.
		if (NameR.substr(14, 4) != ".256")
		break;
		return Intrinsic::x86_avx_sqrt_pd_256; // "86.avx.sqrt.pd.
		256"
		case 's': // 1 string to match.
		if (NameR.substr(14, 4) != ".256")
		break;
		return Intrinsic::x86_avx_sqrt_ps_256; // "86.avx.sqrt.ps.
		256"
		}
		break;
		case 'v': // 2 strings to match.
		if (NameR.substr(8, 9) != "testnzc.p")
		break;
		switch (NameR[17]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_avx_vtestnzc_pd; // "86.avx.vtestnzc
		.pd"
		case 's': // 1 string to match.
		return Intrinsic::x86_avx_vtestnzc_ps; // "86.avx.vtestnzc
		.ps"
		}
		break;
		}
		break;
		case '2': // 6 strings to match.
		if (NameR[7] != '.')
		break;
		switch (NameR[8]) {
		default: break;
		case 'm': // 2 strings to match.
		if (NameR.substr(9, 8) != "askload.")
		break;
		switch (NameR[17]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_avx2_maskload_d; // "86.avx2.maskloa
		d.d"
		case 'q': // 1 string to match.
		return Intrinsic::x86_avx2_maskload_q; // "86.avx2.maskloa
		d.q"
		}
		break;
		case 'p': // 3 strings to match.
		switch (NameR[9]) {
		default: break;
		case 'm': // 1 string to match.
		if (NameR.substr(10, 8) != "ul.hr.sw")
		break;
		return Intrinsic::x86_avx2_pmul_hr_sw; // "86.avx2.pmul.hr
		.sw"
		case 's': // 2 strings to match.
		switch (NameR[10]) {
		default: break;
		case 'l': // 1 string to match.
		if (NameR.substr(11, 7) != "l.dq.bs")
		break;
		return Intrinsic::x86_avx2_psll_dq_bs; // "86.avx2.psll.dq
		.bs"
		case 'r': // 1 string to match.
		if (NameR.substr(11, 7) != "l.dq.bs")
		break;
		return Intrinsic::x86_avx2_psrl_dq_bs; // "86.avx2.psrl.dq
		.bs"
		}
		break;
		}
		break;
		case 'v': // 1 string to match.
		if (NameR.substr(9, 9) != "perm2i128")
		break;
		return Intrinsic::x86_avx2_vperm2i128; // "86.avx2.vperm2i
		128"
		}
		break;
		}
		break;
		case 'f': // 8 strings to match.
		if (NameR.substr(4, 8) != "ma4.vfnm")
		break;
		switch (NameR[12]) {
		default: break;
		case 'a': // 4 strings to match.
		if (NameR.substr(13, 3) != "dd.")
		break;
		switch (NameR[16]) {
		default: break;
		case 'p': // 2 strings to match.
		switch (NameR[17]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_fma4_vfnmadd_pd; // "86.fma4.vfnmadd
		.pd"
		case 's': // 1 string to match.
		return Intrinsic::x86_fma4_vfnmadd_ps; // "86.fma4.vfnmadd
		.ps"
		}
		break;
		case 's': // 2 strings to match.
		switch (NameR[17]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_fma4_vfnmadd_sd; // "86.fma4.vfnmadd
		.sd"
		case 's': // 1 string to match.
		return Intrinsic::x86_fma4_vfnmadd_ss; // "86.fma4.vfnmadd
		.ss"
		}
		break;
		}
		break;
		case 's': // 4 strings to match.
		if (NameR.substr(13, 3) != "ub.")
		break;
		switch (NameR[16]) {
		default: break;
		case 'p': // 2 strings to match.
		switch (NameR[17]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_fma4_vfnmsub_pd; // "86.fma4.vfnmsub
		.pd"
		case 's': // 1 string to match.
		return Intrinsic::x86_fma4_vfnmsub_ps; // "86.fma4.vfnmsub
		.ps"
		}
		break;
		case 's': // 2 strings to match.
		switch (NameR[17]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_fma4_vfnmsub_sd; // "86.fma4.vfnmsub
		.sd"
		case 's': // 1 string to match.
		return Intrinsic::x86_fma4_vfnmsub_ss; // "86.fma4.vfnmsub
		.ss"
		}
		break;
		}
		break;
		}
		break;
		case 's': // 13 strings to match.
		if (NameR.substr(4, 2) != "se")
		break;
		switch (NameR[6]) {
		default: break;
		case '.': // 2 strings to match.
		switch (NameR[7]) {
		default: break;
		case 'c': // 1 string to match.
		if (NameR.substr(8, 10) != "vttss2si64")
		break;
		return Intrinsic::x86_sse_cvttss2si64; // "86.sse.cvttss2s
		i64"
		case 'u': // 1 string to match.
		if (NameR.substr(8, 10) != "comineq.ss")
		break;
		return Intrinsic::x86_sse_ucomineq_ss; // "86.sse.ucomineq
		.ss"
		}
		break;
		case '2': // 10 strings to match.
		if (NameR[7] != '.')
		break;
		switch (NameR[8]) {
		default: break;
		case 'c': // 3 strings to match.
		switch (NameR[9]) {
		default: break;
		case 'o': // 1 string to match.
		if (NameR.substr(10, 8) != "mineq.sd")
		break;
		return Intrinsic::x86_sse2_comineq_sd; // "86.sse2.comineq
		.sd"
		case 'v': // 2 strings to match.
		if (NameR.substr(10, 2) != "ts")
		break;
		switch (NameR[12]) {
		default: break;
		case 'd': // 1 string to match.
		if (NameR.substr(13, 5) != "2si64")
		break;
		return Intrinsic::x86_sse2_cvtsd2si64; // "86.sse2.cvtsd2s
		i64"
		case 'i': // 1 string to match.
		if (NameR.substr(13, 5) != "642sd")
		break;
		return Intrinsic::x86_sse2_cvtsi642sd; // "86.sse2.cvtsi64
		2sd"
		}
		break;
		}
		break;
		case 'p': // 2 strings to match.
		if (NameR[9] != 's')
		break;
		switch (NameR[10]) {
		default: break;
		case 'l': // 1 string to match.
		if (NameR.substr(11, 7) != "l.dq.bs")
		break;
		return Intrinsic::x86_sse2_psll_dq_bs; // "86.sse2.psll.dq
		.bs"
		case 'r': // 1 string to match.
		if (NameR.substr(11, 7) != "l.dq.bs")
		break;
		return Intrinsic::x86_sse2_psrl_dq_bs; // "86.sse2.psrl.dq
		.bs"
		}
		break;
		case 'u': // 5 strings to match.
		if (NameR.substr(9, 4) != "comi")
		break;
		switch (NameR[13]) {
		default: break;
		case 'e': // 1 string to match.
		if (NameR.substr(14, 4) != "q.sd")
		break;
		return Intrinsic::x86_sse2_ucomieq_sd; // "86.sse2.ucomieq
		.sd"
		case 'g': // 2 strings to match.
		switch (NameR[14]) {
		default: break;
		case 'e': // 1 string to match.
		if (NameR.substr(15, 3) != ".sd")
		break;
		return Intrinsic::x86_sse2_ucomige_sd; // "86.sse2.ucomige
		.sd"
		case 't': // 1 string to match.
		if (NameR.substr(15, 3) != ".sd")
		break;
		return Intrinsic::x86_sse2_ucomigt_sd; // "86.sse2.ucomigt
		.sd"
		}
		break;
		case 'l': // 2 strings to match.
		switch (NameR[14]) {
		default: break;
		case 'e': // 1 string to match.
		if (NameR.substr(15, 3) != ".sd")
		break;
		return Intrinsic::x86_sse2_ucomile_sd; // "86.sse2.ucomile
		.sd"
		case 't': // 1 string to match.
		if (NameR.substr(15, 3) != ".sd")
		break;
		return Intrinsic::x86_sse2_ucomilt_sd; // "86.sse2.ucomilt
		.sd"
		}
		break;
		}
		break;
		}
		break;
		case '4': // 1 string to match.
		if (NameR.substr(7, 11) != "1.extractps")
		break;
		return Intrinsic::x86_sse41_extractps; // "86.sse41.extrac
		tps"
		}
		break;
		case 'x': // 8 strings to match.
		if (NameR.substr(4, 8) != "op.vpcom")
		break;
		switch (NameR[12]) {
		default: break;
		case 'f': // 4 strings to match.
		if (NameR.substr(13, 4) != "alse")
		break;
		switch (NameR[17]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::x86_xop_vpcomfalseb; // "86.xop.vpcomfal
		seb"
		case 'd': // 1 string to match.
		return Intrinsic::x86_xop_vpcomfalsed; // "86.xop.vpcomfal
		sed"
		case 'q': // 1 string to match.
		return Intrinsic::x86_xop_vpcomfalseq; // "86.xop.vpcomfal
		seq"
		case 'w': // 1 string to match.
		return Intrinsic::x86_xop_vpcomfalsew; // "86.xop.vpcomfal
		sew"
		}
		break;
		case 't': // 4 strings to match.
		if (NameR.substr(13, 4) != "rueu")
		break;
		switch (NameR[17]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::x86_xop_vpcomtrueub; // "86.xop.vpcomtru
		eub"
		case 'd': // 1 string to match.
		return Intrinsic::x86_xop_vpcomtrueud; // "86.xop.vpcomtru
		eud"
		case 'q': // 1 string to match.
		return Intrinsic::x86_xop_vpcomtrueuq; // "86.xop.vpcomtru
		euq"
		case 'w': // 1 string to match.
		return Intrinsic::x86_xop_vpcomtrueuw; // "86.xop.vpcomtru
		euw"
		}
		break;
		}
		break;
		}
		break;
		case 19: // 40 strings to match.
		if (NameR.substr(0, 3) != "86.")
		break;
		switch (NameR[3]) {
		default: break;
		case 'a': // 24 strings to match.
		switch (NameR[4]) {
		default: break;
		case 'e': // 2 strings to match.
		if (NameR.substr(5, 7) != "sni.aes")
		break;
		switch (NameR[12]) {
		default: break;
		case 'd': // 1 string to match.
		if (NameR.substr(13, 6) != "eclast")
		break;
		return Intrinsic::x86_aesni_aesdeclast; // "86.aesni.aesdec
		last"
		case 'e': // 1 string to match.
		if (NameR.substr(13, 6) != "nclast")
		break;
		return Intrinsic::x86_aesni_aesenclast; // "86.aesni.aesenc
		last"
		}
		break;
		case 'v': // 22 strings to match.
		if (NameR[5] != 'x')
		break;
		switch (NameR[6]) {
		default: break;
		case '.': // 11 strings to match.
		switch (NameR[7]) {
		default: break;
		case 'b': // 2 strings to match.
		if (NameR.substr(8, 6) != "lend.p")
		break;
		switch (NameR[14]) {
		default: break;
		case 'd': // 1 string to match.
		if (NameR.substr(15, 4) != ".256")
		break;
		return Intrinsic::x86_avx_blend_pd_256; // "86.avx.
		blend.pd.256"
		case 's': // 1 string to match.
		if (NameR.substr(15, 4) != ".256")
		break;
		return Intrinsic::x86_avx_blend_ps_256; // "86.avx.
		blend.ps.256"
		}
		break;
		case 'm': // 5 strings to match.
		switch (NameR[8]) {
		default: break;
		case 'a': // 2 strings to match.
		if (NameR.substr(9, 9) != "skstore.p")
		break;
		switch (NameR[18]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_avx_maskstore_pd; // "86.avx.
		maskstore.pd"
		case 's': // 1 string to match.
		return Intrinsic::x86_avx_maskstore_ps; // "86.avx.
		maskstore.ps"
		}
		break;
		case 'o': // 3 strings to match.
		if (NameR.substr(9, 4) != "vnt.")
		break;
		switch (NameR[13]) {
		default: break;
		case 'd': // 1 string to match.
		if (NameR.substr(14, 5) != "q.256")
		break;
		return Intrinsic::x86_avx_movnt_dq_256; // "86.avx.
		movnt.dq.256"
		case 'p': // 2 strings to match.
		switch (NameR[14]) {
		default: break;
		case 'd': // 1 string to match.
		if (NameR.substr(15, 4) != ".256")
		break;
		return Intrinsic::x86_avx_movnt_pd_256; // "86.avx.
		movnt.pd.256"
		case 's': // 1 string to match.
		if (NameR.substr(15, 4) != ".256")
		break;
		return Intrinsic::x86_avx_movnt_ps_256; // "86.avx.
		movnt.ps.256"
		}
		break;
		}
		break;
		}
		break;
		case 'p': // 1 string to match.
		if (NameR.substr(8, 11) != "testnzc.256")
		break;
		return Intrinsic::x86_avx_ptestnzc_256; // "86.avx.ptestnzc
		.256"
		case 'r': // 3 strings to match.
		switch (NameR[8]) {
		default: break;
		case 'o': // 2 strings to match.
		if (NameR.substr(9, 5) != "und.p")
		break;
		switch (NameR[14]) {
		default: break;
		case 'd': // 1 string to match.
		if (NameR.substr(15, 4) != ".256")
		break;
		return Intrinsic::x86_avx_round_pd_256; // "86.avx.
		round.pd.256"
		case 's': // 1 string to match.
		if (NameR.substr(15, 4) != ".256")
		break;
		return Intrinsic::x86_avx_round_ps_256; // "86.avx.
		round.ps.256"
		}
		break;
		case 's': // 1 string to match.
		if (NameR.substr(9, 10) != "qrt.ps.256")
		break;
		return Intrinsic::x86_avx_rsqrt_ps_256; // "86.avx.
		rsqrt.ps.256"
		}
		break;
		}
		break;
		case '2': // 11 strings to match.
		if (NameR[7] != '.')
		break;
		switch (NameR[8]) {
		default: break;
		case 'm': // 2 strings to match.
		if (NameR.substr(9, 9) != "askstore.")
		break;
		switch (NameR[18]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_avx2_maskstore_d; // "86.avx2
		.maskstore.d"
		case 'q': // 1 string to match.
		return Intrinsic::x86_avx2_maskstore_q; // "86.avx2
		.maskstore.q"
		}
		break;
		case 'p': // 8 strings to match.
		switch (NameR[9]) {
		default: break;
		case 'b': // 2 strings to match.
		if (NameR.substr(10, 6) != "lendd.")
		break;
		switch (NameR[16]) {
		default: break;
		case '1': // 1 string to match.
		if (NameR.substr(17, 2) != "28")
		break;
		return Intrinsic::x86_avx2_pblendd_128; // "86.avx2
		.pblendd.128"
		case '2': // 1 string to match.
		if (NameR.substr(17, 2) != "56")
		break;
		return Intrinsic::x86_avx2_pblendd_256; // "86.avx2
		.pblendd.256"
		}
		break;
		case 'm': // 1 string to match.
		if (NameR.substr(10, 9) != "add.ub.sw")
		break;
		return Intrinsic::x86_avx2_pmadd_ub_sw; // "86.avx2
		.pmadd.ub.sw"
		case 's': // 5 strings to match.
		switch (NameR[10]) {
		default: break;
		case 'l': // 2 strings to match.
		if (NameR.substr(11, 3) != "lv.")
		break;
		switch (NameR[14]) {
		default: break;
		case 'd': // 1 string to match.
		if (NameR.substr(15, 4) != ".256")
		break;
		return Intrinsic::x86_avx2_psllv_d_256; // "86.avx2
		.psllv.d.256"
		case 'q': // 1 string to match.
		if (NameR.substr(15, 4) != ".256")
		break;
		return Intrinsic::x86_avx2_psllv_q_256; // "86.avx2
		.psllv.q.256"
		}
		break;
		case 'r': // 3 strings to match.
		switch (NameR[11]) {
		default: break;
		case 'a': // 1 string to match.
		if (NameR.substr(12, 7) != "v.d.256")
		break;
		return Intrinsic::x86_avx2_psrav_d_256; // "86.avx2
		.psrav.d.256"
		case 'l': // 2 strings to match.
		if (NameR.substr(12, 2) != "v.")
		break;
		switch (NameR[14]) {
		default: break;
		case 'd': // 1 string to match.
		if (NameR.substr(15, 4) != ".256")
		break;
		return Intrinsic::x86_avx2_psrlv_d_256; // "86.avx2
		.psrlv.d.256"
		case 'q': // 1 string to match.
		if (NameR.substr(15, 4) != ".256")
		break;
		return Intrinsic::x86_avx2_psrlv_q_256; // "86.avx2
		.psrlv.q.256"
		}
		break;
		}
		break;
		}
		break;
		}
		break;
		case 'v': // 1 string to match.
		if (NameR.substr(9, 10) != "inserti128")
		break;
		return Intrinsic::x86_avx2_vinserti128; // "86.avx2.vinsert
		i128"
		}
		break;
		}
		break;
		}
		break;
		case 's': // 10 strings to match.
		if (NameR[4] != 's')
		break;
		switch (NameR[5]) {
		default: break;
		case 'e': // 6 strings to match.
		switch (NameR[6]) {
		default: break;
		case '2': // 3 strings to match.
		if (NameR[7] != '.')
		break;
		switch (NameR[8]) {
		default: break;
		case 'c': // 1 string to match.
		if (NameR.substr(9, 10) != "vttsd2si64")
		break;
		return Intrinsic::x86_sse2_cvttsd2si64; // "86.sse2.cvttsd2
		si64"
		case 'm': // 1 string to match.
		if (NameR.substr(9, 10) != "askmov.dqu")
		break;
		return Intrinsic::x86_sse2_maskmov_dqu; // "86.sse2.maskmov
		.dqu"
		case 'u': // 1 string to match.
		if (NameR.substr(9, 10) != "comineq.sd")
		break;
		return Intrinsic::x86_sse2_ucomineq_sd; // "86.sse2.ucomine
		q.sd"
		}
		break;
		case '4': // 3 strings to match.
		switch (NameR[7]) {
		default: break;
		case '1': // 1 string to match.
		if (NameR.substr(8, 11) != ".phminposuw")
		break;
		return Intrinsic::x86_sse41_phminposuw; // "86.sse41.phminp
		osuw"
		case '2': // 2 strings to match.
		if (NameR.substr(8, 7) != ".crc32.")
		break;
		switch (NameR[15]) {
		default: break;
		case '3': // 1 string to match.
		if (NameR.substr(16, 3) != "2.8")
		break;
		return Intrinsic::x86_sse42_crc32_32_8; // "86.sse4
		2.crc32.32.8"
		case '6': // 1 string to match.
		if (NameR.substr(16, 3) != "4.8")
		break;
		return Intrinsic::x86_sse42_crc32_64_8; // "86.sse4
		2.crc32.64.8"
		}
		break;
		}
		break;
		}
		break;
		case 's': // 4 strings to match.
		if (NameR.substr(6, 4) != "e3.p")
		break;
		switch (NameR[10]) {
		default: break;
		case 'a': // 3 strings to match.
		if (NameR.substr(11, 3) != "bs.")
		break;
		switch (NameR[14]) {
		default: break;
		case 'b': // 1 string to match.
		if (NameR.substr(15, 4) != ".128")
		break;
		return Intrinsic::x86_ssse3_pabs_b_128; // "86.ssse3.pabs.b
		.128"
		case 'd': // 1 string to match.
		if (NameR.substr(15, 4) != ".128")
		break;
		return Intrinsic::x86_ssse3_pabs_d_128; // "86.ssse3.pabs.d
		.128"
		case 'w': // 1 string to match.
		if (NameR.substr(15, 4) != ".128")
		break;
		return Intrinsic::x86_ssse3_pabs_w_128; // "86.ssse3.pabs.w
		.128"
		}
		break;
		case 'm': // 1 string to match.
		if (NameR.substr(11, 8) != "ul.hr.sw")
		break;
		return Intrinsic::x86_ssse3_pmul_hr_sw; // "86.ssse3.pmul.h
		r.sw"
		}
		break;
		}
		break;
		case 'x': // 6 strings to match.
		if (NameR.substr(4, 4) != "op.v")
		break;
		switch (NameR[8]) {
		default: break;
		case 'f': // 2 strings to match.
		if (NameR.substr(9, 5) != "rcz.p")
		break;
		switch (NameR[14]) {
		default: break;
		case 'd': // 1 string to match.
		if (NameR.substr(15, 4) != ".256")
		break;
		return Intrinsic::x86_xop_vfrcz_pd_256; // "86.xop.vfrcz.pd
		.256"
		case 's': // 1 string to match.
		if (NameR.substr(15, 4) != ".256")
		break;
		return Intrinsic::x86_xop_vfrcz_ps_256; // "86.xop.vfrcz.ps
		.256"
		}
		break;
		case 'p': // 4 strings to match.
		if (NameR.substr(9, 9) != "comfalseu")
		break;
		switch (NameR[18]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::x86_xop_vpcomfalseub; // "86.xop.vpcomfal
		seub"
		case 'd': // 1 string to match.
		return Intrinsic::x86_xop_vpcomfalseud; // "86.xop.vpcomfal
		seud"
		case 'q': // 1 string to match.
		return Intrinsic::x86_xop_vpcomfalseuq; // "86.xop.vpcomfal
		seuq"
		case 'w': // 1 string to match.
		return Intrinsic::x86_xop_vpcomfalseuw; // "86.xop.vpcomfal
		seuw"
		}
		break;
		}
		break;
		}
		break;
		case 20: // 41 strings to match.
		if (NameR.substr(0, 3) != "86.")
		break;
		switch (NameR[3]) {
		default: break;
		case 'a': // 21 strings to match.
		if (NameR.substr(4, 2) != "vx")
		break;
		switch (NameR[6]) {
		default: break;
		case '.': // 20 strings to match.
		switch (NameR[7]) {
		default: break;
		case 'a': // 2 strings to match.
		if (NameR.substr(8, 7) != "ddsub.p")
		break;
		switch (NameR[15]) {
		default: break;
		case 'd': // 1 string to match.
		if (NameR.substr(16, 4) != ".256")
		break;
		return Intrinsic::x86_avx_addsub_pd_256; // "86.avx.addsub.p
		d.256"
		case 's': // 1 string to match.
		if (NameR.substr(16, 4) != ".256")
		break;
		return Intrinsic::x86_avx_addsub_ps_256; // "86.avx.addsub.p
		s.256"
		}
		break;
		case 'b': // 2 strings to match.
		if (NameR.substr(8, 7) != "lendv.p")
		break;
		switch (NameR[15]) {
		default: break;
		case 'd': // 1 string to match.
		if (NameR.substr(16, 4) != ".256")
		break;
		return Intrinsic::x86_avx_blendv_pd_256; // "86.avx.blendv.p
		d.256"
		case 's': // 1 string to match.
		if (NameR.substr(16, 4) != ".256")
		break;
		return Intrinsic::x86_avx_blendv_ps_256; // "86.avx.blendv.p
		s.256"
		}
		break;
		case 'c': // 4 strings to match.
		if (NameR.substr(8, 2) != "vt")
		break;
		switch (NameR[10]) {
		default: break;
		case '.': // 2 strings to match.
		if (NameR[11] != 'p')
		break;
		switch (NameR[12]) {
		default: break;
		case 'd': // 1 string to match.
		if (NameR.substr(13, 7) != "2dq.256")
		break;
		return Intrinsic::x86_avx_cvt_pd2dq_256; // "86.avx.
		cvt.pd2dq.256"
		case 's': // 1 string to match.
		if (NameR.substr(13, 7) != "2dq.256")
		break;
		return Intrinsic::x86_avx_cvt_ps2dq_256; // "86.avx.
		cvt.ps2dq.256"
		}
		break;
		case 'd': // 2 strings to match.
		if (NameR.substr(11, 4) != "q2.p")
		break;
		switch (NameR[15]) {
		default: break;
		case 'd': // 1 string to match.
		if (NameR.substr(16, 4) != ".256")
		break;
		return Intrinsic::x86_avx_cvtdq2_pd_256; // "86.avx.
		cvtdq2.pd.256"
		case 's': // 1 string to match.
		if (NameR.substr(16, 4) != ".256")
		break;
		return Intrinsic::x86_avx_cvtdq2_ps_256; // "86.avx.
		cvtdq2.ps.256"
		}
		break;
		}
		break;
		case 'm': // 2 strings to match.
		if (NameR.substr(8, 7) != "ovmsk.p")
		break;
		switch (NameR[15]) {
		default: break;
		case 'd': // 1 string to match.
		if (NameR.substr(16, 4) != ".256")
		break;
		return Intrinsic::x86_avx_movmsk_pd_256; // "86.avx.movmsk.p
		d.256"
		case 's': // 1 string to match.
		if (NameR.substr(16, 4) != ".256")
		break;
		return Intrinsic::x86_avx_movmsk_ps_256; // "86.avx.movmsk.p
		s.256"
		}
		break;
		case 's': // 3 strings to match.
		if (NameR.substr(8, 6) != "toreu.")
		break;
		switch (NameR[14]) {
		default: break;
		case 'd': // 1 string to match.
		if (NameR.substr(15, 5) != "q.256")
		break;
		return Intrinsic::x86_avx_storeu_dq_256; // "86.avx.storeu.d
		q.256"
		case 'p': // 2 strings to match.
		switch (NameR[15]) {
		default: break;
		case 'd': // 1 string to match.
		if (NameR.substr(16, 4) != ".256")
		break;
		return Intrinsic::x86_avx_storeu_pd_256; // "86.avx.
		storeu.pd.256"
		case 's': // 1 string to match.
		if (NameR.substr(16, 4) != ".256")
		break;
		return Intrinsic::x86_avx_storeu_ps_256; // "86.avx.
		storeu.ps.256"
		}
		break;
		}
		break;
		case 'v': // 7 strings to match.
		switch (NameR[8]) {
		default: break;
		case 'b': // 1 string to match.
		if (NameR.substr(9, 11) != "roadcast.ss")
		break;
		return Intrinsic::x86_avx_vbroadcast_ss; // "86.avx.vbroadca
		st.ss"
		case 'p': // 2 strings to match.
		if (NameR.substr(9, 10) != "ermilvar.p")
		break;
		switch (NameR[19]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_avx_vpermilvar_pd; // "86.avx.
		vpermilvar.pd"
		case 's': // 1 string to match.
		return Intrinsic::x86_avx_vpermilvar_ps; // "86.avx.
		vpermilvar.ps"
		}
		break;
		case 't': // 4 strings to match.
		if (NameR.substr(9, 3) != "est")
		break;
		switch (NameR[12]) {
		default: break;
		case 'c': // 2 strings to match.
		if (NameR.substr(13, 2) != ".p")
		break;
		switch (NameR[15]) {
		default: break;
		case 'd': // 1 string to match.
		if (NameR.substr(16, 4) != ".256")
		break;
		return Intrinsic::x86_avx_vtestc_pd_256; // "86.avx.
		vtestc.pd.256"
		case 's': // 1 string to match.
		if (NameR.substr(16, 4) != ".256")
		break;
		return Intrinsic::x86_avx_vtestc_ps_256; // "86.avx.
		vtestc.ps.256"
		}
		break;
		case 'z': // 2 strings to match.
		if (NameR.substr(13, 2) != ".p")
		break;
		switch (NameR[15]) {
		default: break;
		case 'd': // 1 string to match.
		if (NameR.substr(16, 4) != ".256")
		break;
		return Intrinsic::x86_avx_vtestz_pd_256; // "86.avx.
		vtestz.pd.256"
		case 's': // 1 string to match.
		if (NameR.substr(16, 4) != ".256")
		break;
		return Intrinsic::x86_avx_vtestz_ps_256; // "86.avx.
		vtestz.ps.256"
		}
		break;
		}
		break;
		}
		break;
		}
		break;
		case '2': // 1 string to match.
		if (NameR.substr(7, 13) != ".vextracti128")
		break;
		return Intrinsic::x86_avx2_vextracti128; // "86.avx2.vextrac
		ti128"
		}
		break;
		case 'f': // 4 strings to match.
		if (NameR.substr(4, 7) != "ma4.vfm")
		break;
		switch (NameR[11]) {
		default: break;
		case 'a': // 2 strings to match.
		if (NameR.substr(12, 7) != "ddsub.p")
		break;
		switch (NameR[19]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_fma4_vfmaddsub_pd; // "86.fma4.vfmadds
		ub.pd"
		case 's': // 1 string to match.
		return Intrinsic::x86_fma4_vfmaddsub_ps; // "86.fma4.vfmadds
		ub.ps"
		}
		break;
		case 's': // 2 strings to match.
		if (NameR.substr(12, 7) != "ubadd.p")
		break;
		switch (NameR[19]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_fma4_vfmsubadd_pd; // "86.fma4.vfmsuba
		dd.pd"
		case 's': // 1 string to match.
		return Intrinsic::x86_fma4_vfmsubadd_ps; // "86.fma4.vfmsuba
		dd.ps"
		}
		break;
		}
		break;
		case 's': // 16 strings to match.
		if (NameR[4] != 's')
		break;
		switch (NameR[5]) {
		default: break;
		case 'e': // 7 strings to match.
		switch (NameR[6]) {
		default: break;
		case '2': // 4 strings to match.
		if (NameR.substr(7, 2) != ".p")
		break;
		switch (NameR[9]) {
		default: break;
		case 'a': // 3 strings to match.
		if (NameR.substr(10, 2) != "ck")
		break;
		switch (NameR[12]) {
		default: break;
		case 's': // 2 strings to match.
		if (NameR[13] != 's')
		break;
		switch (NameR[14]) {
		default: break;
		case 'd': // 1 string to match.
		if (NameR.substr(15, 5) != "w.128")
		break;
		return Intrinsic::x86_sse2_packssdw_128; // "86.sse2
		.packssdw.128"
		case 'w': // 1 string to match.
		if (NameR.substr(15, 5) != "b.128")
		break;
		return Intrinsic::x86_sse2_packsswb_128; // "86.sse2
		.packsswb.128"
		}
		break;
		case 'u': // 1 string to match.
		if (NameR.substr(13, 7) != "swb.128")
		break;
		return Intrinsic::x86_sse2_packuswb_128; // "86.sse2
		.packuswb.128"
		}
		break;
		case 'm': // 1 string to match.
		if (NameR.substr(10, 10) != "ovmskb.128")
		break;
		return Intrinsic::x86_sse2_pmovmskb_128; // "86.sse2.pmovmsk
		b.128"
		}
		break;
		case '4': // 3 strings to match.
		if (NameR.substr(7, 8) != "2.crc32.")
		break;
		switch (NameR[15]) {
		default: break;
		case '3': // 2 strings to match.
		if (NameR.substr(16, 2) != "2.")
		break;
		switch (NameR[18]) {
		default: break;
		case '1': // 1 string to match.
		if (NameR[19] != '6')
		break;
		return Intrinsic::x86_sse42_crc32_32_16; // "86.sse4
		2.crc32.32.16"
		case '3': // 1 string to match.
		if (NameR[19] != '2')
		break;
		return Intrinsic::x86_sse42_crc32_32_32; // "86.sse4
		2.crc32.32.32"
		}
		break;
		case '6': // 1 string to match.
		if (NameR.substr(16, 4) != "4.64")
		break;
		return Intrinsic::x86_sse42_crc32_64_64; // "86.sse42.crc32.
		64.64"
		}
		break;
		}
		break;
		case 's': // 9 strings to match.
		if (NameR.substr(6, 4) != "e3.p")
		break;
		switch (NameR[10]) {
		default: break;
		case 'h': // 4 strings to match.
		switch (NameR[11]) {
		default: break;
		case 'a': // 2 strings to match.
		if (NameR.substr(12, 3) != "dd.")
		break;
		switch (NameR[15]) {
		default: break;
		case 'd': // 1 string to match.
		if (NameR.substr(16, 4) != ".128")
		break;
		return Intrinsic::x86_ssse3_phadd_d_128; // "86.ssse
		3.phadd.d.128"
		case 'w': // 1 string to match.
		if (NameR.substr(16, 4) != ".128")
		break;
		return Intrinsic::x86_ssse3_phadd_w_128; // "86.ssse
		3.phadd.w.128"
		}
		break;
		case 's': // 2 strings to match.
		if (NameR.substr(12, 3) != "ub.")
		break;
		switch (NameR[15]) {
		default: break;
		case 'd': // 1 string to match.
		if (NameR.substr(16, 4) != ".128")
		break;
		return Intrinsic::x86_ssse3_phsub_d_128; // "86.ssse
		3.phsub.d.128"
		case 'w': // 1 string to match.
		if (NameR.substr(16, 4) != ".128")
		break;
		return Intrinsic::x86_ssse3_phsub_w_128; // "86.ssse
		3.phsub.w.128"
		}
		break;
		}
		break;
		case 'm': // 1 string to match.
		if (NameR.substr(11, 9) != "add.ub.sw")
		break;
		return Intrinsic::x86_ssse3_pmadd_ub_sw; // "86.ssse3.pmadd.
		ub.sw"
		case 's': // 4 strings to match.
		switch (NameR[11]) {
		default: break;
		case 'h': // 1 string to match.
		if (NameR.substr(12, 8) != "uf.b.128")
		break;
		return Intrinsic::x86_ssse3_pshuf_b_128; // "86.ssse3.pshuf.
		b.128"
		case 'i': // 3 strings to match.
		if (NameR.substr(12, 3) != "gn.")
		break;
		switch (NameR[15]) {
		default: break;
		case 'b': // 1 string to match.
		if (NameR.substr(16, 4) != ".128")
		break;
		return Intrinsic::x86_ssse3_psign_b_128; // "86.ssse
		3.psign.b.128"
		case 'd': // 1 string to match.
		if (NameR.substr(16, 4) != ".128")
		break;
		return Intrinsic::x86_ssse3_psign_d_128; // "86.ssse
		3.psign.d.128"
		case 'w': // 1 string to match.
		if (NameR.substr(16, 4) != ".128")
		break;
		return Intrinsic::x86_ssse3_psign_w_128; // "86.ssse
		3.psign.w.128"
		}
		break;
		}
		break;
		}
		break;
		}
		break;
		}
		break;
		case 21: // 16 strings to match.
		if (NameR.substr(0, 3) != "86.")
		break;
		switch (NameR[3]) {
		default: break;
		case 'a': // 4 strings to match.
		if (NameR.substr(4, 6) != "vx.cvt")
		break;
		switch (NameR[10]) {
		default: break;
		case '.': // 2 strings to match.
		if (NameR[11] != 'p')
		break;
		switch (NameR[12]) {
		default: break;
		case 'd': // 1 string to match.
		if (NameR.substr(13, 8) != "2.ps.256")
		break;
		return Intrinsic::x86_avx_cvt_pd2_ps_256; // "86.avx.cvt.pd2.
		ps.256"
		case 's': // 1 string to match.
		if (NameR.substr(13, 8) != "2.pd.256")
		break;
		return Intrinsic::x86_avx_cvt_ps2_pd_256; // "86.avx.cvt.ps2.
		pd.256"
		}
		break;
		case 't': // 2 strings to match.
		if (NameR.substr(11, 2) != ".p")
		break;
		switch (NameR[13]) {
		default: break;
		case 'd': // 1 string to match.
		if (NameR.substr(14, 7) != "2dq.256")
		break;
		return Intrinsic::x86_avx_cvtt_pd2dq_256; // "86.avx.cvtt.pd2
		dq.256"
		case 's': // 1 string to match.
		if (NameR.substr(14, 7) != "2dq.256")
		break;
		return Intrinsic::x86_avx_cvtt_ps2dq_256; // "86.avx.cvtt.ps2
		dq.256"
		}
		break;
		}
		break;
		case 'f': // 4 strings to match.
		if (NameR.substr(4, 7) != "ma4.vfm")
		break;
		switch (NameR[11]) {
		default: break;
		case 'a': // 2 strings to match.
		if (NameR.substr(12, 4) != "dd.p")
		break;
		switch (NameR[16]) {
		default: break;
		case 'd': // 1 string to match.
		if (NameR.substr(17, 4) != ".256")
		break;
		return Intrinsic::x86_fma4_vfmadd_pd_256; // "86.fma4.vfmadd.
		pd.256"
		case 's': // 1 string to match.
		if (NameR.substr(17, 4) != ".256")
		break;
		return Intrinsic::x86_fma4_vfmadd_ps_256; // "86.fma4.vfmadd.
		ps.256"
		}
		break;
		case 's': // 2 strings to match.
		if (NameR.substr(12, 4) != "ub.p")
		break;
		switch (NameR[16]) {
		default: break;
		case 'd': // 1 string to match.
		if (NameR.substr(17, 4) != ".256")
		break;
		return Intrinsic::x86_fma4_vfmsub_pd_256; // "86.fma4.vfmsub.
		pd.256"
		case 's': // 1 string to match.
		if (NameR.substr(17, 4) != ".256")
		break;
		return Intrinsic::x86_fma4_vfmsub_ps_256; // "86.fma4.vfmsub.
		ps.256"
		}
		break;
		}
		break;
		case 's': // 6 strings to match.
		if (NameR[4] != 's')
		break;
		switch (NameR[5]) {
		default: break;
		case 'e': // 4 strings to match.
		if (NameR.substr(6, 7) != "42.pcmp")
		break;
		switch (NameR[13]) {
		default: break;
		case 'e': // 2 strings to match.
		if (NameR.substr(14, 3) != "str")
		break;
		switch (NameR[17]) {
		default: break;
		case 'i': // 1 string to match.
		if (NameR.substr(18, 3) != "128")
		break;
		return Intrinsic::x86_sse42_pcmpestri128; // "86.sse4
		2.pcmpestri128"
		case 'm': // 1 string to match.
		if (NameR.substr(18, 3) != "128")
		break;
		return Intrinsic::x86_sse42_pcmpestrm128; // "86.sse4
		2.pcmpestrm128"
		}
		break;
		case 'i': // 2 strings to match.
		if (NameR.substr(14, 3) != "str")
		break;
		switch (NameR[17]) {
		default: break;
		case 'i': // 1 string to match.
		if (NameR.substr(18, 3) != "128")
		break;
		return Intrinsic::x86_sse42_pcmpistri128; // "86.sse4
		2.pcmpistri128"
		case 'm': // 1 string to match.
		if (NameR.substr(18, 3) != "128")
		break;
		return Intrinsic::x86_sse42_pcmpistrm128; // "86.sse4
		2.pcmpistrm128"
		}
		break;
		}
		break;
		case 's': // 2 strings to match.
		if (NameR.substr(6, 5) != "e3.ph")
		break;
		switch (NameR[11]) {
		default: break;
		case 'a': // 1 string to match.
		if (NameR.substr(12, 9) != "dd.sw.128")
		break;
		return Intrinsic::x86_ssse3_phadd_sw_128; // "86.ssse3.phadd.
		sw.128"
		case 's': // 1 string to match.
		if (NameR.substr(12, 9) != "ub.sw.128")
		break;
		return Intrinsic::x86_ssse3_phsub_sw_128; // "86.ssse3.phsub.
		sw.128"
		}
		break;
		}
		break;
		case 'x': // 2 strings to match.
		if (NameR.substr(4, 12) != "op.vpermil2p")
		break;
		switch (NameR[16]) {
		default: break;
		case 'd': // 1 string to match.
		if (NameR.substr(17, 4) != ".256")
		break;
		return Intrinsic::x86_xop_vpermil2pd_256; // "86.xop.vpermil2
		pd.256"
		case 's': // 1 string to match.
		if (NameR.substr(17, 4) != ".256")
		break;
		return Intrinsic::x86_xop_vpermil2ps_256; // "86.xop.vpermil2
		ps.256"
		}
		break;
		}
		break;
		case 22: // 21 strings to match.
		if (NameR.substr(0, 3) != "86.")
		break;
		switch (NameR[3]) {
		default: break;
		case 'a': // 7 strings to match.
		if (NameR.substr(4, 2) != "vx")
		break;
		switch (NameR[6]) {
		default: break;
		case '.': // 4 strings to match.
		switch (NameR[7]) {
		default: break;
		case 'm': // 2 strings to match.
		if (NameR.substr(8, 9) != "askload.p")
		break;
		switch (NameR[17]) {
		default: break;
		case 'd': // 1 string to match.
		if (NameR.substr(18, 4) != ".256")
		break;
		return Intrinsic::x86_avx_maskload_pd_256; // "86.avx.
		maskload.pd.256"
		case 's': // 1 string to match.
		if (NameR.substr(18, 4) != ".256")
		break;
		return Intrinsic::x86_avx_maskload_ps_256; // "86.avx.
		maskload.ps.256"
		}
		break;
		case 'v': // 2 strings to match.
		if (NameR.substr(8, 9) != "testnzc.p")
		break;
		switch (NameR[17]) {
		default: break;
		case 'd': // 1 string to match.
		if (NameR.substr(18, 4) != ".256")
		break;
		return Intrinsic::x86_avx_vtestnzc_pd_256; // "86.avx.
		vtestnzc.pd.256"
		case 's': // 1 string to match.
		if (NameR.substr(18, 4) != ".256")
		break;
		return Intrinsic::x86_avx_vtestnzc_ps_256; // "86.avx.
		vtestnzc.ps.256"
		}
		break;
		}
		break;
		case '2': // 3 strings to match.
		if (NameR[7] != '.')
		break;
		switch (NameR[8]) {
		default: break;
		case 'm': // 2 strings to match.
		if (NameR.substr(9, 8) != "askload.")
		break;
		switch (NameR[17]) {
		default: break;
		case 'd': // 1 string to match.
		if (NameR.substr(18, 4) != ".256")
		break;
		return Intrinsic::x86_avx2_maskload_d_256; // "86.avx2
		.maskload.d.256"
		case 'q': // 1 string to match.
		if (NameR.substr(18, 4) != ".256")
		break;
		return Intrinsic::x86_avx2_maskload_q_256; // "86.avx2
		.maskload.q.256"
		}
		break;
		case 'v': // 1 string to match.
		if (NameR.substr(9, 13) != "broadcasti128")
		break;
		return Intrinsic::x86_avx2_vbroadcasti128; // "86.avx2.vbroadc
		asti128"
		}
		break;
		}
		break;
		case 'f': // 4 strings to match.
		if (NameR.substr(4, 8) != "ma4.vfnm")
		break;
		switch (NameR[12]) {
		default: break;
		case 'a': // 2 strings to match.
		if (NameR.substr(13, 4) != "dd.p")
		break;
		switch (NameR[17]) {
		default: break;
		case 'd': // 1 string to match.
		if (NameR.substr(18, 4) != ".256")
		break;
		return Intrinsic::x86_fma4_vfnmadd_pd_256; // "86.fma4.vfnmadd
		.pd.256"
		case 's': // 1 string to match.
		if (NameR.substr(18, 4) != ".256")
		break;
		return Intrinsic::x86_fma4_vfnmadd_ps_256; // "86.fma4.vfnmadd
		.ps.256"
		}
		break;
		case 's': // 2 strings to match.
		if (NameR.substr(13, 4) != "ub.p")
		break;
		switch (NameR[17]) {
		default: break;
		case 'd': // 1 string to match.
		if (NameR.substr(18, 4) != ".256")
		break;
		return Intrinsic::x86_fma4_vfnmsub_pd_256; // "86.fma4.vfnmsub
		.pd.256"
		case 's': // 1 string to match.
		if (NameR.substr(18, 4) != ".256")
		break;
		return Intrinsic::x86_fma4_vfnmsub_ps_256; // "86.fma4.vfnmsub
		.ps.256"
		}
		break;
		}
		break;
		case 's': // 10 strings to match.
		if (NameR.substr(4, 9) != "se42.pcmp")
		break;
		switch (NameR[13]) {
		default: break;
		case 'e': // 5 strings to match.
		if (NameR.substr(14, 4) != "stri")
		break;
		switch (NameR[18]) {
		default: break;
		case 'a': // 1 string to match.
		if (NameR.substr(19, 3) != "128")
		break;
		return Intrinsic::x86_sse42_pcmpestria128; // "86.sse42.pcmpes
		tria128"
		case 'c': // 1 string to match.
		if (NameR.substr(19, 3) != "128")
		break;
		return Intrinsic::x86_sse42_pcmpestric128; // "86.sse42.pcmpes
		tric128"
		case 'o': // 1 string to match.
		if (NameR.substr(19, 3) != "128")
		break;
		return Intrinsic::x86_sse42_pcmpestrio128; // "86.sse42.pcmpes
		trio128"
		case 's': // 1 string to match.
		if (NameR.substr(19, 3) != "128")
		break;
		return Intrinsic::x86_sse42_pcmpestris128; // "86.sse42.pcmpes
		tris128"
		case 'z': // 1 string to match.
		if (NameR.substr(19, 3) != "128")
		break;
		return Intrinsic::x86_sse42_pcmpestriz128; // "86.sse42.pcmpes
		triz128"
		}
		break;
		case 'i': // 5 strings to match.
		if (NameR.substr(14, 4) != "stri")
		break;
		switch (NameR[18]) {
		default: break;
		case 'a': // 1 string to match.
		if (NameR.substr(19, 3) != "128")
		break;
		return Intrinsic::x86_sse42_pcmpistria128; // "86.sse42.pcmpis
		tria128"
		case 'c': // 1 string to match.
		if (NameR.substr(19, 3) != "128")
		break;
		return Intrinsic::x86_sse42_pcmpistric128; // "86.sse42.pcmpis
		tric128"
		case 'o': // 1 string to match.
		if (NameR.substr(19, 3) != "128")
		break;
		return Intrinsic::x86_sse42_pcmpistrio128; // "86.sse42.pcmpis
		trio128"
		case 's': // 1 string to match.
		if (NameR.substr(19, 3) != "128")
		break;
		return Intrinsic::x86_sse42_pcmpistris128; // "86.sse42.pcmpis
		tris128"
		case 'z': // 1 string to match.
		if (NameR.substr(19, 3) != "128")
		break;
		return Intrinsic::x86_sse42_pcmpistriz128; // "86.sse42.pcmpis
		triz128"
		}
		break;
		}
		break;
		}
		break;
		case 23: // 13 strings to match.
		if (NameR.substr(0, 3) != "86.")
		break;
		switch (NameR[3]) {
		default: break;
		case 'a': // 12 strings to match.
		if (NameR.substr(4, 2) != "vx")
		break;
		switch (NameR[6]) {
		default: break;
		case '.': // 2 strings to match.
		if (NameR.substr(7, 11) != "maskstore.p")
		break;
		switch (NameR[18]) {
		default: break;
		case 'd': // 1 string to match.
		if (NameR.substr(19, 4) != ".256")
		break;
		return Intrinsic::x86_avx_maskstore_pd_256; // "86.avx.
		maskstore.pd.256"
		case 's': // 1 string to match.
		if (NameR.substr(19, 4) != ".256")
		break;
		return Intrinsic::x86_avx_maskstore_ps_256; // "86.avx.
		maskstore.ps.256"
		}
		break;
		case '2': // 10 strings to match.
		if (NameR[7] != '.')
		break;
		switch (NameR[8]) {
		default: break;
		case 'm': // 2 strings to match.
		if (NameR.substr(9, 9) != "askstore.")
		break;
		switch (NameR[18]) {
		default: break;
		case 'd': // 1 string to match.
		if (NameR.substr(19, 4) != ".256")
		break;
		return Intrinsic::x86_avx2_maskstore_d_256; // "86.avx2
		.maskstore.d.256"
		case 'q': // 1 string to match.
		if (NameR.substr(19, 4) != ".256")
		break;
		return Intrinsic::x86_avx2_maskstore_q_256; // "86.avx2
		.maskstore.q.256"
		}
		break;
		case 'p': // 8 strings to match.
		if (NameR.substr(9, 9) != "broadcast")
		break;
		switch (NameR[18]) {
		default: break;
		case 'b': // 2 strings to match.
		if (NameR[19] != '.')
		break;
		switch (NameR[20]) {
		default: break;
		case '1': // 1 string to match.
		if (NameR.substr(21, 2) != "28")
		break;
		return Intrinsic::x86_avx2_pbroadcastb_128; // "86.avx2
		.pbroadcastb.128"
		case '2': // 1 string to match.
		if (NameR.substr(21, 2) != "56")
		break;
		return Intrinsic::x86_avx2_pbroadcastb_256; // "86.avx2
		.pbroadcastb.256"
		}
		break;
		case 'd': // 2 strings to match.
		if (NameR[19] != '.')
		break;
		switch (NameR[20]) {
		default: break;
		case '1': // 1 string to match.
		if (NameR.substr(21, 2) != "28")
		break;
		return Intrinsic::x86_avx2_pbroadcastd_128; // "86.avx2
		.pbroadcastd.128"
		case '2': // 1 string to match.
		if (NameR.substr(21, 2) != "56")
		break;
		return Intrinsic::x86_avx2_pbroadcastd_256; // "86.avx2
		.pbroadcastd.256"
		}
		break;
		case 'q': // 2 strings to match.
		if (NameR[19] != '.')
		break;
		switch (NameR[20]) {
		default: break;
		case '1': // 1 string to match.
		if (NameR.substr(21, 2) != "28")
		break;
		return Intrinsic::x86_avx2_pbroadcastq_128; // "86.avx2
		.pbroadcastq.128"
		case '2': // 1 string to match.
		if (NameR.substr(21, 2) != "56")
		break;
		return Intrinsic::x86_avx2_pbroadcastq_256; // "86.avx2
		.pbroadcastq.256"
		}
		break;
		case 'w': // 2 strings to match.
		if (NameR[19] != '.')
		break;
		switch (NameR[20]) {
		default: break;
		case '1': // 1 string to match.
		if (NameR.substr(21, 2) != "28")
		break;
		return Intrinsic::x86_avx2_pbroadcastw_128; // "86.avx2
		.pbroadcastw.128"
		case '2': // 1 string to match.
		if (NameR.substr(21, 2) != "56")
		break;
		return Intrinsic::x86_avx2_pbroadcastw_256; // "86.avx2
		.pbroadcastw.256"
		}
		break;
		}
		break;
		}
		break;
		}
		break;
		case 's': // 1 string to match.
		if (NameR.substr(4, 19) != "sse3.pmul.hr.sw.128")
		break;
		return Intrinsic::x86_ssse3_pmul_hr_sw_128; // "86.ssse3.pmul.h
		r.sw.128"
		}
		break;
		case 24: // 14 strings to match.
		if (NameR.substr(0, 3) != "86.")
		break;
		switch (NameR[3]) {
		default: break;
		case 'a': // 9 strings to match.
		switch (NameR[4]) {
		default: break;
		case 'e': // 1 string to match.
		if (NameR.substr(5, 19) != "sni.aeskeygenassist")
		break;
		return Intrinsic::x86_aesni_aeskeygenassist; // "86.aesni.aeskey
		genassist"
		case 'v': // 8 strings to match.
		if (NameR[5] != 'x')
		break;
		switch (NameR[6]) {
		default: break;
		case '.': // 7 strings to match.
		if (NameR[7] != 'v')
		break;
		switch (NameR[8]) {
		default: break;
		case 'b': // 2 strings to match.
		if (NameR.substr(9, 10) != "roadcast.s")
		break;
		switch (NameR[19]) {
		default: break;
		case 'd': // 1 string to match.
		if (NameR.substr(20, 4) != ".256")
		break;
		return Intrinsic::x86_avx_vbroadcast_sd_256; // "86.avx.
		vbroadcast.sd.256"
		case 's': // 1 string to match.
		if (NameR.substr(20, 4) != ".256")
		break;
		return Intrinsic::x86_avx_vbroadcast_ss_256; // "86.avx.
		vbroadcast.ss.256"
		}
		break;
		case 'p': // 5 strings to match.
		if (NameR.substr(9, 3) != "erm")
		break;
		switch (NameR[12]) {
		default: break;
		case '2': // 3 strings to match.
		if (NameR.substr(13, 5) != "f128.")
		break;
		switch (NameR[18]) {
		default: break;
		case 'p': // 2 strings to match.
		switch (NameR[19]) {
		default: break;
		case 'd': // 1 string to match.
		if (NameR.substr(20, 4) != ".256")
		break;
		return Intrinsic::x86_avx_vperm2f128_pd_256; //
		"86.avx.vperm2f128.pd.256"
		case 's': // 1 string to match.
		if (NameR.substr(20, 4) != ".256")
		break;
		return Intrinsic::x86_avx_vperm2f128_ps_256; //
		"86.avx.vperm2f128.ps.256"
		}
		break;
		case 's': // 1 string to match.
		if (NameR.substr(19, 5) != "i.256")
		break;
		return Intrinsic::x86_avx_vperm2f128_si_256; // "86.avx.
		vperm2f128.si.256"
		}
		break;
		case 'i': // 2 strings to match.
		if (NameR.substr(13, 6) != "lvar.p")
		break;
		switch (NameR[19]) {
		default: break;
		case 'd': // 1 string to match.
		if (NameR.substr(20, 4) != ".256")
		break;
		return Intrinsic::x86_avx_vpermilvar_pd_256; // "86.avx.
		vpermilvar.pd.256"
		case 's': // 1 string to match.
		if (NameR.substr(20, 4) != ".256")
		break;
		return Intrinsic::x86_avx_vpermilvar_ps_256; // "86.avx.
		vpermilvar.ps.256"
		}
		break;
		}
		break;
		}
		break;
		case '2': // 1 string to match.
		if (NameR.substr(7, 17) != ".vbroadcast.ss.ps")
		break;
		return Intrinsic::x86_avx2_vbroadcast_ss_ps; // "86.avx2
		.vbroadcast.ss.ps"
		}
		break;
		}
		break;
		case 'f': // 4 strings to match.
		if (NameR.substr(4, 7) != "ma4.vfm")
		break;
		switch (NameR[11]) {
		default: break;
		case 'a': // 2 strings to match.
		if (NameR.substr(12, 7) != "ddsub.p")
		break;
		switch (NameR[19]) {
		default: break;
		case 'd': // 1 string to match.
		if (NameR.substr(20, 4) != ".256")
		break;
		return Intrinsic::x86_fma4_vfmaddsub_pd_256; // "86.fma4
		.vfmaddsub.pd.256"
		case 's': // 1 string to match.
		if (NameR.substr(20, 4) != ".256")
		break;
		return Intrinsic::x86_fma4_vfmaddsub_ps_256; // "86.fma4
		.vfmaddsub.ps.256"
		}
		break;
		case 's': // 2 strings to match.
		if (NameR.substr(12, 7) != "ubadd.p")
		break;
		switch (NameR[19]) {
		default: break;
		case 'd': // 1 string to match.
		if (NameR.substr(20, 4) != ".256")
		break;
		return Intrinsic::x86_fma4_vfmsubadd_pd_256; // "86.fma4
		.vfmsubadd.pd.256"
		case 's': // 1 string to match.
		if (NameR.substr(20, 4) != ".256")
		break;
		return Intrinsic::x86_fma4_vfmsubadd_ps_256; // "86.fma4
		.vfmsubadd.ps.256"
		}
		break;
		}
		break;
		case 's': // 1 string to match.
		if (NameR.substr(4, 20) != "sse3.pmadd.ub.sw.128")
		break;
		return Intrinsic::x86_ssse3_pmadd_ub_sw_128; // "86.ssse3.pmadd.
		ub.sw.128"
		}
		break;
		case 25: // 3 strings to match.
		if (NameR.substr(0, 19) != "86.avx.vinsertf128.")
		break;
		switch (NameR[19]) {
		default: break;
		case 'p': // 2 strings to match.
		switch (NameR[20]) {
		default: break;
		case 'd': // 1 string to match.
		if (NameR.substr(21, 4) != ".256")
		break;
		return Intrinsic::x86_avx_vinsertf128_pd_256; // "86.avx.
		vinsertf128.pd.256"
		case 's': // 1 string to match.
		if (NameR.substr(21, 4) != ".256")
		break;
		return Intrinsic::x86_avx_vinsertf128_ps_256; // "86.avx.
		vinsertf128.ps.256"
		}
		break;
		case 's': // 1 string to match.
		if (NameR.substr(20, 5) != "i.256")
		break;
		return Intrinsic::x86_avx_vinsertf128_si_256; // "86.avx.vinsertf
		128.si.256"
		}
		break;
		case 26: // 3 strings to match.
		if (NameR.substr(0, 20) != "86.avx.vextractf128.")
		break;
		switch (NameR[20]) {
		default: break;
		case 'p': // 2 strings to match.
		switch (NameR[21]) {
		default: break;
		case 'd': // 1 string to match.
		if (NameR.substr(22, 4) != ".256")
		break;
		return Intrinsic::x86_avx_vextractf128_pd_256; // "86.avx.
		vextractf128.pd.256"
		case 's': // 1 string to match.
		if (NameR.substr(22, 4) != ".256")
		break;
		return Intrinsic::x86_avx_vextractf128_ps_256; // "86.avx.
		vextractf128.ps.256"
		}
		break;
		case 's': // 1 string to match.
		if (NameR.substr(21, 5) != "i.256")
		break;
		return Intrinsic::x86_avx_vextractf128_si_256; // "86.avx.vextract
		f128.si.256"
		}
		break;
		case 28: // 4 strings to match.
		if (NameR.substr(0, 6) != "86.avx")
		break;
		switch (NameR[6]) {
		default: break;
		case '.': // 2 strings to match.
		if (NameR.substr(7, 16) != "vbroadcastf128.p")
		break;
		switch (NameR[23]) {
		default: break;
		case 'd': // 1 string to match.
		if (NameR.substr(24, 4) != ".256")
		break;
		return Intrinsic::x86_avx_vbroadcastf128_pd_256; // "86.avx.
		vbroadcastf128.pd.256"
		case 's': // 1 string to match.
		if (NameR.substr(24, 4) != ".256")
		break;
		return Intrinsic::x86_avx_vbroadcastf128_ps_256; // "86.avx.
		vbroadcastf128.ps.256"
		}
		break;
		case '2': // 2 strings to match.
		if (NameR.substr(7, 13) != ".vbroadcast.s")
		break;
		switch (NameR[20]) {
		default: break;
		case 'd': // 1 string to match.
		if (NameR.substr(21, 7) != ".pd.256")
		break;
		return Intrinsic::x86_avx2_vbroadcast_sd_pd_256; // "86.avx2
		.vbroadcast.sd.pd.256"
		case 's': // 1 string to match.
		if (NameR.substr(21, 7) != ".ps.256")
		break;
		return Intrinsic::x86_avx2_vbroadcast_ss_ps_256; // "86.avx2
		.vbroadcast.ss.ps.256"
		}
		break;
		}
		break;
		}
		break; // end of 'x' case.
		}
		#endif

		// Verifier::visitIntrinsicFunctionCall code.
		#ifdef GET_INTRINSIC_VERIFIER
		switch (ID) {
		default: llvm_unreachable("Invalid intrinsic!");
		case Intrinsic::eh_unwind_init: // llvm.eh.unwind.init
		case Intrinsic::ppc_altivec_dssall: // llvm.ppc.altivec.dssall
		case Intrinsic::ppc_sync: // llvm.ppc.sync
		case Intrinsic::trap: // llvm.trap
		case Intrinsic::x86_avx_vzeroall: // llvm.x86.avx.vzeroall
		case Intrinsic::x86_avx_vzeroupper: // llvm.x86.avx.vzeroupper
		case Intrinsic::x86_mmx_emms: // llvm.x86.mmx.emms
		case Intrinsic::x86_mmx_femms: // llvm.x86.mmx.femms
		case Intrinsic::x86_sse2_lfence: // llvm.x86.sse2.lfence
		case Intrinsic::x86_sse2_mfence: // llvm.x86.sse2.mfence
		case Intrinsic::x86_sse_sfence: // llvm.x86.sse.sfence
		case Intrinsic::xcore_clre: // llvm.xcore.clre
		case Intrinsic::xcore_ssync: // llvm.xcore.ssync
		VerifyIntrinsicPrototype(ID, IF, 0, 0);
		break;
		case Intrinsic::xcore_eeu: // llvm.xcore.eeu
		case Intrinsic::xcore_freer: // llvm.xcore.freer
		case Intrinsic::xcore_mjoin: // llvm.xcore.mjoin
		case Intrinsic::xcore_msync: // llvm.xcore.msync
		case Intrinsic::xcore_syncr: // llvm.xcore.syncr
		VerifyIntrinsicPrototype(ID, IF, 0, 1, MVT::iPTRAny);
		break;
		case Intrinsic::xcore_setclk: // llvm.xcore.setclk
		case Intrinsic::xcore_setrdy: // llvm.xcore.setrdy
		VerifyIntrinsicPrototype(ID, IF, 0, 2, MVT::iPTRAny, MVT::iPTRAny);
		break;
		case Intrinsic::memcpy: // llvm.memcpy
		case Intrinsic::memmove: // llvm.memmove
		VerifyIntrinsicPrototype(ID, IF, 0, 5, MVT::iPTRAny, MVT::iPTRAny, MVT:
		:iAny, MVT::i32, MVT::i1);
		break;
		case Intrinsic::xcore_chkct: // llvm.xcore.chkct
		case Intrinsic::xcore_out: // llvm.xcore.out
		case Intrinsic::xcore_outct: // llvm.xcore.outct
		case Intrinsic::xcore_outt: // llvm.xcore.outt
		case Intrinsic::xcore_setc: // llvm.xcore.setc
		case Intrinsic::xcore_setd: // llvm.xcore.setd
		case Intrinsic::xcore_setpsc: // llvm.xcore.setpsc
		case Intrinsic::xcore_setpt: // llvm.xcore.setpt
		case Intrinsic::xcore_settw: // llvm.xcore.settw
		VerifyIntrinsicPrototype(ID, IF, 0, 2, MVT::iPTRAny, MVT::i32);
		break;
		case Intrinsic::memset: // llvm.memset
		VerifyIntrinsicPrototype(ID, IF, 0, 5, MVT::iPTRAny, MVT::i8, MVT::iAny
		, MVT::i32, MVT::i1);
		break;
		case Intrinsic::xcore_initcp: // llvm.xcore.initcp
		case Intrinsic::xcore_initdp: // llvm.xcore.initdp
	case Intrinsic::xcore_initlr: // llvm.xcore.initlr	case Intrinsic::xcore_initlr: // llvm.xcore.initlr
	case Intrinsic::xcore_initpc: // llvm.xcore.initpc	case Intrinsic::xcore_initpc: // llvm.xcore.initpc
	case Intrinsic::xcore_initsp: // llvm.xcore.initsp	case Intrinsic::xcore_initsp: // llvm.xcore.initsp
	case Intrinsic::xcore_setev: // llvm.xcore.setev	case Intrinsic::xcore_setev: // llvm.xcore.setev
	case Intrinsic::xcore_setv: // llvm.xcore.setv	case Intrinsic::xcore_setv: // llvm.xcore.setv
	VerifyIntrinsicPrototype(ID, IF, 0, 2, MVT::iPTRAny, MVT::iPTR);	VerifyIntrinsicPrototype(ID, IF, 0, 2, MVT::iPTRAny, MVT::iPTR);
	break;	break;
	case Intrinsic::invariant_end: // llvm.invariant.end	case Intrinsic::invariant_end: // llvm.invariant.end
	VerifyIntrinsicPrototype(ID, IF, 0, 3, MVT::iPTR, MVT::i64, MVT::iPTR);	VerifyIntrinsicPrototype(ID, IF, 0, 3, MVT::iPTR, MVT::i64, MVT::iPTR);
	break;	break;
	case Intrinsic::arm_set_fpscr: // llvm.arm.set.fpscr	case Intrinsic::arm_set_fpscr: // llvm.arm.set.fpscr
	case Intrinsic::eh_sjlj_callsite: // llvm.eh.sjlj.callsite	case Intrinsic::eh_sjlj_callsite: // llvm.eh.sjlj.callsite

	case Intrinsic::eh_sjlj_dispatch_setup: // llvm.eh.sjlj.disp atch.setup
	case Intrinsic::pcmarker: // llvm.pcmarker	case Intrinsic::pcmarker: // llvm.pcmarker
	case Intrinsic::ppc_altivec_dss: // llvm.ppc.altivec.dss	case Intrinsic::ppc_altivec_dss: // llvm.ppc.altivec.dss
	case Intrinsic::ptx_bar_sync: // llvm.ptx.bar.sync	case Intrinsic::ptx_bar_sync: // llvm.ptx.bar.sync

		case Intrinsic::x86_wrfsbase_32: // llvm.x86.wrfsbase.32
		case Intrinsic::x86_wrgsbase_32: // llvm.x86.wrgsbase.32
	case Intrinsic::xcore_clrsr: // llvm.xcore.clrsr	case Intrinsic::xcore_clrsr: // llvm.xcore.clrsr
	case Intrinsic::xcore_setsr: // llvm.xcore.setsr	case Intrinsic::xcore_setsr: // llvm.xcore.setsr
	VerifyIntrinsicPrototype(ID, IF, 0, 1, MVT::i32);	VerifyIntrinsicPrototype(ID, IF, 0, 1, MVT::i32);
	break;	break;
	case Intrinsic::x86_sse3_mwait: // llvm.x86.sse3.mwait	case Intrinsic::x86_sse3_mwait: // llvm.x86.sse3.mwait
	case Intrinsic::xcore_setps: // llvm.xcore.setps	case Intrinsic::xcore_setps: // llvm.xcore.setps
	VerifyIntrinsicPrototype(ID, IF, 0, 2, MVT::i32, MVT::i32);	VerifyIntrinsicPrototype(ID, IF, 0, 2, MVT::i32, MVT::i32);
	break;	break;
	case Intrinsic::arm_mcrr: // llvm.arm.mcrr	case Intrinsic::arm_mcrr: // llvm.arm.mcrr
	case Intrinsic::arm_mcrr2: // llvm.arm.mcrr2	case Intrinsic::arm_mcrr2: // llvm.arm.mcrr2

	skipping to change at line 8944	skipping to change at line 17158
	break;	break;
	case Intrinsic::arm_cdp: // llvm.arm.cdp	case Intrinsic::arm_cdp: // llvm.arm.cdp
	case Intrinsic::arm_cdp2: // llvm.arm.cdp2	case Intrinsic::arm_cdp2: // llvm.arm.cdp2
	case Intrinsic::arm_mcr: // llvm.arm.mcr	case Intrinsic::arm_mcr: // llvm.arm.mcr
	case Intrinsic::arm_mcr2: // llvm.arm.mcr2	case Intrinsic::arm_mcr2: // llvm.arm.mcr2
	VerifyIntrinsicPrototype(ID, IF, 0, 6, MVT::i32, MVT::i32, MVT::i32, MV T::i32, MVT::i32, MVT::i32);	VerifyIntrinsicPrototype(ID, IF, 0, 6, MVT::i32, MVT::i32, MVT::i32, MV T::i32, MVT::i32, MVT::i32);
	break;	break;
	case Intrinsic::eh_return_i32: // llvm.eh.return.i32	case Intrinsic::eh_return_i32: // llvm.eh.return.i32
	VerifyIntrinsicPrototype(ID, IF, 0, 2, MVT::i32, MVT::iPTR);	VerifyIntrinsicPrototype(ID, IF, 0, 2, MVT::i32, MVT::iPTR);
	break;	break;

		case Intrinsic::x86_wrfsbase_64: // llvm.x86.wrfsbase.64
		case Intrinsic::x86_wrgsbase_64: // llvm.x86.wrgsbase.64
		VerifyIntrinsicPrototype(ID, IF, 0, 1, MVT::i64);
		break;
	case Intrinsic::eh_return_i64: // llvm.eh.return.i64	case Intrinsic::eh_return_i64: // llvm.eh.return.i64
	case Intrinsic::lifetime_end: // llvm.lifetime.end	case Intrinsic::lifetime_end: // llvm.lifetime.end
	case Intrinsic::lifetime_start: // llvm.lifetime.start	case Intrinsic::lifetime_start: // llvm.lifetime.start
	VerifyIntrinsicPrototype(ID, IF, 0, 2, MVT::i64, MVT::iPTR);	VerifyIntrinsicPrototype(ID, IF, 0, 2, MVT::i64, MVT::iPTR);
	break;	break;
	case Intrinsic::x86_int: // llvm.x86.int	case Intrinsic::x86_int: // llvm.x86.int
	VerifyIntrinsicPrototype(ID, IF, 0, 1, MVT::i8);	VerifyIntrinsicPrototype(ID, IF, 0, 1, MVT::i8);
	break;	break;
	case Intrinsic::dbg_value: // llvm.dbg.value	case Intrinsic::dbg_value: // llvm.dbg.value
	VerifyIntrinsicPrototype(ID, IF, 0, 3, MVT::Metadata, MVT::i64, MVT::Me tadata);	VerifyIntrinsicPrototype(ID, IF, 0, 3, MVT::Metadata, MVT::i64, MVT::Me tadata);

	skipping to change at line 8997	skipping to change at line 17215
	break;	break;
	case Intrinsic::arm_neon_vst3lane: // llvm.arm.neon.vst3lane	case Intrinsic::arm_neon_vst3lane: // llvm.arm.neon.vst3lane
	VerifyIntrinsicPrototype(ID, IF, 0, 6, MVT::iPTR, MVT::vAny, ~1, ~1, MV T::i32, MVT::i32);	VerifyIntrinsicPrototype(ID, IF, 0, 6, MVT::iPTR, MVT::vAny, ~1, ~1, MV T::i32, MVT::i32);
	break;	break;
	case Intrinsic::arm_neon_vst4lane: // llvm.arm.neon.vst4lane	case Intrinsic::arm_neon_vst4lane: // llvm.arm.neon.vst4lane
	VerifyIntrinsicPrototype(ID, IF, 0, 7, MVT::iPTR, MVT::vAny, ~1, ~1, ~1 , MVT::i32, MVT::i32);	VerifyIntrinsicPrototype(ID, IF, 0, 7, MVT::iPTR, MVT::vAny, ~1, ~1, ~1 , MVT::i32, MVT::i32);
	break;	break;
	case Intrinsic::arm_neon_vst1: // llvm.arm.neon.vst1	case Intrinsic::arm_neon_vst1: // llvm.arm.neon.vst1
	VerifyIntrinsicPrototype(ID, IF, 0, 3, MVT::iPTR, MVT::vAny, MVT::i32);	VerifyIntrinsicPrototype(ID, IF, 0, 3, MVT::iPTR, MVT::vAny, MVT::i32);
	break;	break;

	case Intrinsic::eh_resume: // llvm.eh.resume
	case Intrinsic::longjmp: // llvm.longjmp	case Intrinsic::longjmp: // llvm.longjmp
	case Intrinsic::siglongjmp: // llvm.siglongjmp	case Intrinsic::siglongjmp: // llvm.siglongjmp
	VerifyIntrinsicPrototype(ID, IF, 0, 2, MVT::iPTR, MVT::i32);	VerifyIntrinsicPrototype(ID, IF, 0, 2, MVT::iPTR, MVT::i32);
	break;	break;
	case Intrinsic::ppc_altivec_dst: // llvm.ppc.altivec.dst	case Intrinsic::ppc_altivec_dst: // llvm.ppc.altivec.dst
	case Intrinsic::ppc_altivec_dstst: // llvm.ppc.altivec.dstst	case Intrinsic::ppc_altivec_dstst: // llvm.ppc.altivec.dstst
	case Intrinsic::ppc_altivec_dststt: // llvm.ppc.altivec.dststt	case Intrinsic::ppc_altivec_dststt: // llvm.ppc.altivec.dststt
	case Intrinsic::ppc_altivec_dstt: // llvm.ppc.altivec.dstt	case Intrinsic::ppc_altivec_dstt: // llvm.ppc.altivec.dstt
	case Intrinsic::x86_sse3_monitor: // llvm.x86.sse3.monitor	case Intrinsic::x86_sse3_monitor: // llvm.x86.sse3.monitor
	VerifyIntrinsicPrototype(ID, IF, 0, 3, MVT::iPTR, MVT::i32, MVT::i32);	VerifyIntrinsicPrototype(ID, IF, 0, 3, MVT::iPTR, MVT::i32, MVT::i32);

	skipping to change at line 9036	skipping to change at line 17253
	break;	break;
	case Intrinsic::x86_sse2_storeu_dq: // llvm.x86.sse2.storeu.dq	case Intrinsic::x86_sse2_storeu_dq: // llvm.x86.sse2.storeu.dq
	VerifyIntrinsicPrototype(ID, IF, 0, 2, MVT::iPTR, MVT::v16i8);	VerifyIntrinsicPrototype(ID, IF, 0, 2, MVT::iPTR, MVT::v16i8);
	break;	break;
	case Intrinsic::x86_sse2_storeu_pd: // llvm.x86.sse2.storeu.pd	case Intrinsic::x86_sse2_storeu_pd: // llvm.x86.sse2.storeu.pd
	VerifyIntrinsicPrototype(ID, IF, 0, 2, MVT::iPTR, MVT::v2f64);	VerifyIntrinsicPrototype(ID, IF, 0, 2, MVT::iPTR, MVT::v2f64);
	break;	break;
	case Intrinsic::x86_avx_maskstore_pd: // llvm.x86.avx.mask store.pd	case Intrinsic::x86_avx_maskstore_pd: // llvm.x86.avx.mask store.pd
	VerifyIntrinsicPrototype(ID, IF, 0, 3, MVT::iPTR, MVT::v2f64, MVT::v2f6 4);	VerifyIntrinsicPrototype(ID, IF, 0, 3, MVT::iPTR, MVT::v2f64, MVT::v2f6 4);
	break;	break;

		case Intrinsic::x86_avx2_maskstore_q: // llvm.x86.avx2.mas
		kstore.q
		VerifyIntrinsicPrototype(ID, IF, 0, 3, MVT::iPTR, MVT::v2i64, MVT::v2i6
		4);
		break;
	case Intrinsic::x86_avx_storeu_dq_256: // llvm.x86.avx.stor eu.dq.256	case Intrinsic::x86_avx_storeu_dq_256: // llvm.x86.avx.stor eu.dq.256
	VerifyIntrinsicPrototype(ID, IF, 0, 2, MVT::iPTR, MVT::v32i8);	VerifyIntrinsicPrototype(ID, IF, 0, 2, MVT::iPTR, MVT::v32i8);
	break;	break;
	case Intrinsic::x86_sse_storeu_ps: // llvm.x86.sse.storeu.ps	case Intrinsic::x86_sse_storeu_ps: // llvm.x86.sse.storeu.ps
	VerifyIntrinsicPrototype(ID, IF, 0, 2, MVT::iPTR, MVT::v4f32);	VerifyIntrinsicPrototype(ID, IF, 0, 2, MVT::iPTR, MVT::v4f32);
	break;	break;
	case Intrinsic::x86_avx_maskstore_ps: // llvm.x86.avx.mask store.ps	case Intrinsic::x86_avx_maskstore_ps: // llvm.x86.avx.mask store.ps
	VerifyIntrinsicPrototype(ID, IF, 0, 3, MVT::iPTR, MVT::v4f32, MVT::v4f3 2);	VerifyIntrinsicPrototype(ID, IF, 0, 3, MVT::iPTR, MVT::v4f32, MVT::v4f3 2);
	break;	break;
	case Intrinsic::x86_avx_movnt_pd_256: // llvm.x86.avx.movn t.pd.256	case Intrinsic::x86_avx_movnt_pd_256: // llvm.x86.avx.movn t.pd.256
	case Intrinsic::x86_avx_storeu_pd_256: // llvm.x86.avx.stor eu.pd.256	case Intrinsic::x86_avx_storeu_pd_256: // llvm.x86.avx.stor eu.pd.256
	VerifyIntrinsicPrototype(ID, IF, 0, 2, MVT::iPTR, MVT::v4f64);	VerifyIntrinsicPrototype(ID, IF, 0, 2, MVT::iPTR, MVT::v4f64);
	break;	break;
	case Intrinsic::x86_avx_maskstore_pd_256: // llvm.x86.avx.mask store.pd.256	case Intrinsic::x86_avx_maskstore_pd_256: // llvm.x86.avx.mask store.pd.256
	VerifyIntrinsicPrototype(ID, IF, 0, 3, MVT::iPTR, MVT::v4f64, MVT::v4f6 4);	VerifyIntrinsicPrototype(ID, IF, 0, 3, MVT::iPTR, MVT::v4f64, MVT::v4f6 4);
	break;	break;
	case Intrinsic::x86_sse2_storel_dq: // llvm.x86.sse2.storel.dq	case Intrinsic::x86_sse2_storel_dq: // llvm.x86.sse2.storel.dq
	VerifyIntrinsicPrototype(ID, IF, 0, 2, MVT::iPTR, MVT::v4i32);	VerifyIntrinsicPrototype(ID, IF, 0, 2, MVT::iPTR, MVT::v4i32);
	break;	break;

		case Intrinsic::x86_avx2_maskstore_d: // llvm.x86.avx2.mas
		kstore.d
		VerifyIntrinsicPrototype(ID, IF, 0, 3, MVT::iPTR, MVT::v4i32, MVT::v4i3
		2);
		break;
	case Intrinsic::x86_avx_movnt_dq_256: // llvm.x86.avx.movn t.dq.256	case Intrinsic::x86_avx_movnt_dq_256: // llvm.x86.avx.movn t.dq.256
	VerifyIntrinsicPrototype(ID, IF, 0, 2, MVT::iPTR, MVT::v4i64);	VerifyIntrinsicPrototype(ID, IF, 0, 2, MVT::iPTR, MVT::v4i64);
	break;	break;

		case Intrinsic::x86_avx2_maskstore_q_256: // llvm.x86.avx2.mas
		kstore.q.256
		VerifyIntrinsicPrototype(ID, IF, 0, 3, MVT::iPTR, MVT::v4i64, MVT::v4i6
		4);
		break;
	case Intrinsic::x86_avx_movnt_ps_256: // llvm.x86.avx.movn t.ps.256	case Intrinsic::x86_avx_movnt_ps_256: // llvm.x86.avx.movn t.ps.256
	case Intrinsic::x86_avx_storeu_ps_256: // llvm.x86.avx.stor eu.ps.256	case Intrinsic::x86_avx_storeu_ps_256: // llvm.x86.avx.stor eu.ps.256
	VerifyIntrinsicPrototype(ID, IF, 0, 2, MVT::iPTR, MVT::v8f32);	VerifyIntrinsicPrototype(ID, IF, 0, 2, MVT::iPTR, MVT::v8f32);
	break;	break;
	case Intrinsic::x86_avx_maskstore_ps_256: // llvm.x86.avx.mask store.ps.256	case Intrinsic::x86_avx_maskstore_ps_256: // llvm.x86.avx.mask store.ps.256
	VerifyIntrinsicPrototype(ID, IF, 0, 3, MVT::iPTR, MVT::v8f32, MVT::v8f3 2);	VerifyIntrinsicPrototype(ID, IF, 0, 3, MVT::iPTR, MVT::v8f32, MVT::v8f3 2);
	break;	break;

		case Intrinsic::x86_avx2_maskstore_d_256: // llvm.x86.avx2.mas
		kstore.d.256
		VerifyIntrinsicPrototype(ID, IF, 0, 3, MVT::iPTR, MVT::v8i32, MVT::v8i3
		2);
		break;
	case Intrinsic::gcroot: // llvm.gcroot	case Intrinsic::gcroot: // llvm.gcroot
	VerifyIntrinsicPrototype(ID, IF, 0, 2, MVT::iPTR, MVT::iPTR);	VerifyIntrinsicPrototype(ID, IF, 0, 2, MVT::iPTR, MVT::iPTR);
	break;	break;
	case Intrinsic::x86_mmx_movnt_dq: // llvm.x86.mmx.movnt.dq	case Intrinsic::x86_mmx_movnt_dq: // llvm.x86.mmx.movnt.dq
	VerifyIntrinsicPrototype(ID, IF, 0, 2, MVT::iPTR, MVT::x86mmx);	VerifyIntrinsicPrototype(ID, IF, 0, 2, MVT::iPTR, MVT::x86mmx);
	break;	break;
	case Intrinsic::ppc_altivec_stvebx: // llvm.ppc.altivec.stvebx	case Intrinsic::ppc_altivec_stvebx: // llvm.ppc.altivec.stvebx
	VerifyIntrinsicPrototype(ID, IF, 0, 2, MVT::v16i8, MVT::iPTR);	VerifyIntrinsicPrototype(ID, IF, 0, 2, MVT::v16i8, MVT::iPTR);
	break;	break;
	case Intrinsic::x86_sse2_maskmov_dqu: // llvm.x86.sse2.mas kmov.dqu	case Intrinsic::x86_sse2_maskmov_dqu: // llvm.x86.sse2.mas kmov.dqu

	skipping to change at line 9148	skipping to change at line 17377
	case Intrinsic::expect: // llvm.expect	case Intrinsic::expect: // llvm.expect
	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::iAny, ~0, ~0);	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::iAny, ~0, ~0);
	break;	break;
	case Intrinsic::bswap: // llvm.bswap	case Intrinsic::bswap: // llvm.bswap
	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::iAny, ~0);	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::iAny, ~0);
	break;	break;
	case Intrinsic::ctpop: // llvm.ctpop	case Intrinsic::ctpop: // llvm.ctpop
	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::iAny, ~0);	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::iAny, ~0);
	break;	break;
	case Intrinsic::ctlz: // llvm.ctlz	case Intrinsic::ctlz: // llvm.ctlz

	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::iAny, ~0);	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::iAny, ~0, MVT::i1);
	break;	break;
	case Intrinsic::cttz: // llvm.cttz	case Intrinsic::cttz: // llvm.cttz

	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::iAny, ~0);	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::iAny, ~0, MVT::i1);
	break;	break;
	case Intrinsic::annotation: // llvm.annotation	case Intrinsic::annotation: // llvm.annotation
	VerifyIntrinsicPrototype(ID, IF, 1, 4, MVT::iAny, ~0, MVT::iPTR, MVT::i PTR, MVT::i32);	VerifyIntrinsicPrototype(ID, IF, 1, 4, MVT::iAny, ~0, MVT::iPTR, MVT::i PTR, MVT::i32);
	break;	break;
	case Intrinsic::arm_neon_vcvtfp2fxs: // llvm.arm.neon.vcvtfp2fxs	case Intrinsic::arm_neon_vcvtfp2fxs: // llvm.arm.neon.vcvtfp2fxs
	case Intrinsic::arm_neon_vcvtfp2fxu: // llvm.arm.neon.vcvtfp2fxu	case Intrinsic::arm_neon_vcvtfp2fxu: // llvm.arm.neon.vcvtfp2fxu
	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::iAny, MVT::fAny, MVT::i32);	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::iAny, MVT::fAny, MVT::i32);
	break;	break;
	case Intrinsic::convertsif: // llvm.convertsif	case Intrinsic::convertsif: // llvm.convertsif
	case Intrinsic::convertuif: // llvm.convertuif	case Intrinsic::convertuif: // llvm.convertuif

	skipping to change at line 9322	skipping to change at line 17551
	case Intrinsic::arm_vcvtr: // llvm.arm.vcvtr	case Intrinsic::arm_vcvtr: // llvm.arm.vcvtr
	case Intrinsic::arm_vcvtru: // llvm.arm.vcvtru	case Intrinsic::arm_vcvtru: // llvm.arm.vcvtru
	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::f32, MVT::fAny);	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::f32, MVT::fAny);
	break;	break;
	case Intrinsic::convert_from_fp16: // llvm.convert.from.fp16	case Intrinsic::convert_from_fp16: // llvm.convert.from.fp16
	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::f32, MVT::i16);	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::f32, MVT::i16);
	break;	break;
	case Intrinsic::convert_to_fp16: // llvm.convert.to.fp16	case Intrinsic::convert_to_fp16: // llvm.convert.to.fp16
	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::i16, MVT::f32);	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::i16, MVT::f32);
	break;	break;

		case Intrinsic::hexagon_C2_all8: // llvm.hexagon.C2.all8
		case Intrinsic::hexagon_C2_any8: // llvm.hexagon.C2.any8
		case Intrinsic::hexagon_C2_not: // llvm.hexagon.C2.not
		case Intrinsic::hexagon_C2_pxfer_map: // llvm.hexagon.C2.p
		xfer.map
		case Intrinsic::hexagon_C2_tfrrp: // llvm.hexagon.C2.tfrrp
		VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::i1, MVT::i32);
		break;
		case Intrinsic::hexagon_C2_and: // llvm.hexagon.C2.and
		case Intrinsic::hexagon_C2_andn: // llvm.hexagon.C2.andn
		case Intrinsic::hexagon_C2_bitsclr: // llvm.hexagon.C2.bitsclr
		case Intrinsic::hexagon_C2_bitsclri: // llvm.hexagon.C2.bitsclri
		case Intrinsic::hexagon_C2_bitsset: // llvm.hexagon.C2.bitsset
		case Intrinsic::hexagon_C2_cmpeq: // llvm.hexagon.C2.cmpeq
		case Intrinsic::hexagon_C2_cmpeqi: // llvm.hexagon.C2.cmpeqi
		case Intrinsic::hexagon_C2_cmpgei: // llvm.hexagon.C2.cmpgei
		case Intrinsic::hexagon_C2_cmpgeui: // llvm.hexagon.C2.cmpgeui
		case Intrinsic::hexagon_C2_cmpgt: // llvm.hexagon.C2.cmpgt
		case Intrinsic::hexagon_C2_cmpgti: // llvm.hexagon.C2.cmpgti
		case Intrinsic::hexagon_C2_cmpgtu: // llvm.hexagon.C2.cmpgtu
		case Intrinsic::hexagon_C2_cmpgtui: // llvm.hexagon.C2.cmpgtui
		case Intrinsic::hexagon_C2_cmplt: // llvm.hexagon.C2.cmplt
		case Intrinsic::hexagon_C2_cmpltu: // llvm.hexagon.C2.cmpltu
		case Intrinsic::hexagon_C2_or: // llvm.hexagon.C2.or
		case Intrinsic::hexagon_C2_orn: // llvm.hexagon.C2.orn
		case Intrinsic::hexagon_C2_xor: // llvm.hexagon.C2.xor
		case Intrinsic::hexagon_C4_cmplte: // llvm.hexagon.C4.cmplte
		case Intrinsic::hexagon_C4_cmpltei: // llvm.hexagon.C4.cmpltei
		case Intrinsic::hexagon_C4_cmplteu: // llvm.hexagon.C4.cmplteu
		case Intrinsic::hexagon_C4_cmplteui: // llvm.hexagon.C4.cmplteui
		case Intrinsic::hexagon_C4_cmpneq: // llvm.hexagon.C4.cmpneq
		case Intrinsic::hexagon_C4_cmpneqi: // llvm.hexagon.C4.cmpneqi
		case Intrinsic::hexagon_C4_fastcorner9: // llvm.hexagon.C4.f
		astcorner9
		case Intrinsic::hexagon_C4_fastcorner9_not: // llvm.hexagon.C4.f
		astcorner9.not
		case Intrinsic::hexagon_S2_tstbit_i: // llvm.hexagon.S2.tstbit.i
		case Intrinsic::hexagon_S2_tstbit_r: // llvm.hexagon.S2.tstbit.r
		VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::i1, MVT::i32, MVT::i32);
		break;
		case Intrinsic::hexagon_C4_and_and: // llvm.hexagon.C4.and.and
		case Intrinsic::hexagon_C4_and_andn: // llvm.hexagon.C4.and.andn
		case Intrinsic::hexagon_C4_and_or: // llvm.hexagon.C4.and.or
		case Intrinsic::hexagon_C4_and_orn: // llvm.hexagon.C4.and.orn
		case Intrinsic::hexagon_C4_or_and: // llvm.hexagon.C4.or.and
		case Intrinsic::hexagon_C4_or_andn: // llvm.hexagon.C4.or.andn
		case Intrinsic::hexagon_C4_or_or: // llvm.hexagon.C4.or.or
		case Intrinsic::hexagon_C4_or_orn: // llvm.hexagon.C4.or.orn
		VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::i1, MVT::i32, MVT::i32, MVT
		::i32);
		break;
		case Intrinsic::hexagon_A2_vcmpbeq: // llvm.hexagon.A2.vcmpbeq
		case Intrinsic::hexagon_A2_vcmpbgtu: // llvm.hexagon.A2.vcmpbgtu
		case Intrinsic::hexagon_A2_vcmpheq: // llvm.hexagon.A2.vcmpheq
		case Intrinsic::hexagon_A2_vcmphgt: // llvm.hexagon.A2.vcmphgt
		case Intrinsic::hexagon_A2_vcmphgtu: // llvm.hexagon.A2.vcmphgtu
		case Intrinsic::hexagon_A2_vcmpweq: // llvm.hexagon.A2.vcmpweq
		case Intrinsic::hexagon_A2_vcmpwgt: // llvm.hexagon.A2.vcmpwgt
		case Intrinsic::hexagon_A2_vcmpwgtu: // llvm.hexagon.A2.vcmpwgtu
		case Intrinsic::hexagon_C2_cmpeqp: // llvm.hexagon.C2.cmpeqp
		case Intrinsic::hexagon_C2_cmpgtp: // llvm.hexagon.C2.cmpgtp
		case Intrinsic::hexagon_C2_cmpgtup: // llvm.hexagon.C2.cmpgtup
		VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::i1, MVT::i64, MVT::i64);
		break;
	case Intrinsic::arm_get_fpscr: // llvm.arm.get.fpscr	case Intrinsic::arm_get_fpscr: // llvm.arm.get.fpscr
	case Intrinsic::flt_rounds: // llvm.flt.rounds	case Intrinsic::flt_rounds: // llvm.flt.rounds
	case Intrinsic::ptx_read_clock: // llvm.ptx.read.clock	case Intrinsic::ptx_read_clock: // llvm.ptx.read.clock
	case Intrinsic::ptx_read_ctaid_w: // llvm.ptx.read.ctaid.w	case Intrinsic::ptx_read_ctaid_w: // llvm.ptx.read.ctaid.w
	case Intrinsic::ptx_read_ctaid_x: // llvm.ptx.read.ctaid.x	case Intrinsic::ptx_read_ctaid_x: // llvm.ptx.read.ctaid.x
	case Intrinsic::ptx_read_ctaid_y: // llvm.ptx.read.ctaid.y	case Intrinsic::ptx_read_ctaid_y: // llvm.ptx.read.ctaid.y
	case Intrinsic::ptx_read_ctaid_z: // llvm.ptx.read.ctaid.z	case Intrinsic::ptx_read_ctaid_z: // llvm.ptx.read.ctaid.z
	case Intrinsic::ptx_read_gridid: // llvm.ptx.read.gridid	case Intrinsic::ptx_read_gridid: // llvm.ptx.read.gridid
	case Intrinsic::ptx_read_laneid: // llvm.ptx.read.laneid	case Intrinsic::ptx_read_laneid: // llvm.ptx.read.laneid
	case Intrinsic::ptx_read_lanemask_eq: // llvm.ptx.read.lan emask.eq	case Intrinsic::ptx_read_lanemask_eq: // llvm.ptx.read.lan emask.eq

	skipping to change at line 9356	skipping to change at line 17645
	case Intrinsic::ptx_read_pm0: // llvm.ptx.read.pm0	case Intrinsic::ptx_read_pm0: // llvm.ptx.read.pm0
	case Intrinsic::ptx_read_pm1: // llvm.ptx.read.pm1	case Intrinsic::ptx_read_pm1: // llvm.ptx.read.pm1
	case Intrinsic::ptx_read_pm2: // llvm.ptx.read.pm2	case Intrinsic::ptx_read_pm2: // llvm.ptx.read.pm2
	case Intrinsic::ptx_read_pm3: // llvm.ptx.read.pm3	case Intrinsic::ptx_read_pm3: // llvm.ptx.read.pm3
	case Intrinsic::ptx_read_smid: // llvm.ptx.read.smid	case Intrinsic::ptx_read_smid: // llvm.ptx.read.smid
	case Intrinsic::ptx_read_tid_w: // llvm.ptx.read.tid.w	case Intrinsic::ptx_read_tid_w: // llvm.ptx.read.tid.w
	case Intrinsic::ptx_read_tid_x: // llvm.ptx.read.tid.x	case Intrinsic::ptx_read_tid_x: // llvm.ptx.read.tid.x
	case Intrinsic::ptx_read_tid_y: // llvm.ptx.read.tid.y	case Intrinsic::ptx_read_tid_y: // llvm.ptx.read.tid.y
	case Intrinsic::ptx_read_tid_z: // llvm.ptx.read.tid.z	case Intrinsic::ptx_read_tid_z: // llvm.ptx.read.tid.z
	case Intrinsic::ptx_read_warpid: // llvm.ptx.read.warpid	case Intrinsic::ptx_read_warpid: // llvm.ptx.read.warpid

		case Intrinsic::x86_rdfsbase_32: // llvm.x86.rdfsbase.32
		case Intrinsic::x86_rdgsbase_32: // llvm.x86.rdgsbase.32
	case Intrinsic::xcore_geted: // llvm.xcore.geted	case Intrinsic::xcore_geted: // llvm.xcore.geted
	case Intrinsic::xcore_getet: // llvm.xcore.getet	case Intrinsic::xcore_getet: // llvm.xcore.getet
	case Intrinsic::xcore_getid: // llvm.xcore.getid	case Intrinsic::xcore_getid: // llvm.xcore.getid
	VerifyIntrinsicPrototype(ID, IF, 1, 0, MVT::i32);	VerifyIntrinsicPrototype(ID, IF, 1, 0, MVT::i32);
	break;	break;
	case Intrinsic::xcore_endin: // llvm.xcore.endin	case Intrinsic::xcore_endin: // llvm.xcore.endin
	case Intrinsic::xcore_getts: // llvm.xcore.getts	case Intrinsic::xcore_getts: // llvm.xcore.getts
	case Intrinsic::xcore_in: // llvm.xcore.in	case Intrinsic::xcore_in: // llvm.xcore.in
	case Intrinsic::xcore_inct: // llvm.xcore.inct	case Intrinsic::xcore_inct: // llvm.xcore.inct
	case Intrinsic::xcore_int: // llvm.xcore.int	case Intrinsic::xcore_int: // llvm.xcore.int
	case Intrinsic::xcore_peek: // llvm.xcore.peek	case Intrinsic::xcore_peek: // llvm.xcore.peek
	case Intrinsic::xcore_testct: // llvm.xcore.testct	case Intrinsic::xcore_testct: // llvm.xcore.testct
	case Intrinsic::xcore_testwct: // llvm.xcore.testwct	case Intrinsic::xcore_testwct: // llvm.xcore.testwct
	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::i32, MVT::iPTRAny);	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::i32, MVT::iPTRAny);
	break;	break;
	case Intrinsic::xcore_inshr: // llvm.xcore.inshr	case Intrinsic::xcore_inshr: // llvm.xcore.inshr
	case Intrinsic::xcore_outshr: // llvm.xcore.outshr	case Intrinsic::xcore_outshr: // llvm.xcore.outshr
	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::i32, MVT::iPTRAny, MVT::i32 );	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::i32, MVT::iPTRAny, MVT::i32 );
	break;	break;

		case Intrinsic::hexagon_A2_abs: // llvm.hexagon.A2.abs
		case Intrinsic::hexagon_A2_abssat: // llvm.hexagon.A2.abssat
		case Intrinsic::hexagon_A2_aslh: // llvm.hexagon.A2.aslh
		case Intrinsic::hexagon_A2_asrh: // llvm.hexagon.A2.asrh
		case Intrinsic::hexagon_A2_neg: // llvm.hexagon.A2.neg
		case Intrinsic::hexagon_A2_negsat: // llvm.hexagon.A2.negsat
		case Intrinsic::hexagon_A2_not: // llvm.hexagon.A2.not
		case Intrinsic::hexagon_A2_satb: // llvm.hexagon.A2.satb
		case Intrinsic::hexagon_A2_sath: // llvm.hexagon.A2.sath
		case Intrinsic::hexagon_A2_satub: // llvm.hexagon.A2.satub
		case Intrinsic::hexagon_A2_satuh: // llvm.hexagon.A2.satuh
		case Intrinsic::hexagon_A2_swiz: // llvm.hexagon.A2.swiz
		case Intrinsic::hexagon_A2_sxtb: // llvm.hexagon.A2.sxtb
		case Intrinsic::hexagon_A2_sxth: // llvm.hexagon.A2.sxth
		case Intrinsic::hexagon_A2_tfr: // llvm.hexagon.A2.tfr
		case Intrinsic::hexagon_A2_tfrsi: // llvm.hexagon.A2.tfrsi
		case Intrinsic::hexagon_A2_zxtb: // llvm.hexagon.A2.zxtb
		case Intrinsic::hexagon_A2_zxth: // llvm.hexagon.A2.zxth
		case Intrinsic::hexagon_C2_tfrpr: // llvm.hexagon.C2.tfrpr
		case Intrinsic::hexagon_S2_brev: // llvm.hexagon.S2.brev
		case Intrinsic::hexagon_S2_cl0: // llvm.hexagon.S2.cl0
		case Intrinsic::hexagon_S2_cl1: // llvm.hexagon.S2.cl1
		case Intrinsic::hexagon_S2_clb: // llvm.hexagon.S2.clb
		case Intrinsic::hexagon_S2_clbnorm: // llvm.hexagon.S2.clbnorm
		case Intrinsic::hexagon_S2_ct0: // llvm.hexagon.S2.ct0
		case Intrinsic::hexagon_S2_ct1: // llvm.hexagon.S2.ct1
		case Intrinsic::hexagon_S2_svsathb: // llvm.hexagon.S2.svsathb
		case Intrinsic::hexagon_S2_svsathub: // llvm.hexagon.S2.svsathub
		case Intrinsic::hexagon_S2_vsplatrb: // llvm.hexagon.S2.vsplatrb
		case Intrinsic::hexagon_SI_to_SXTHI_asrh: // llvm.hexagon.SI.t
		o.SXTHI.asrh
	case Intrinsic::xcore_bitrev: // llvm.xcore.bitrev	case Intrinsic::xcore_bitrev: // llvm.xcore.bitrev
	case Intrinsic::xcore_getps: // llvm.xcore.getps	case Intrinsic::xcore_getps: // llvm.xcore.getps
	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::i32, MVT::i32);	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::i32, MVT::i32);
	break;	break;
	case Intrinsic::x86_sse42_crc32_32_16: // llvm.x86.sse42.cr c32.32.16	case Intrinsic::x86_sse42_crc32_32_16: // llvm.x86.sse42.cr c32.32.16
	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::i32, MVT::i32, MVT::i16);	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::i32, MVT::i32, MVT::i16);
	break;	break;
	case Intrinsic::arm_qadd: // llvm.arm.qadd	case Intrinsic::arm_qadd: // llvm.arm.qadd
	case Intrinsic::arm_qsub: // llvm.arm.qsub	case Intrinsic::arm_qsub: // llvm.arm.qsub
	case Intrinsic::arm_ssat: // llvm.arm.ssat	case Intrinsic::arm_ssat: // llvm.arm.ssat
	case Intrinsic::arm_usat: // llvm.arm.usat	case Intrinsic::arm_usat: // llvm.arm.usat

		case Intrinsic::hexagon_A2_add: // llvm.hexagon.A2.add
		case Intrinsic::hexagon_A2_addh_h16_hh: // llvm.hexagon.A2.a
		ddh.h16.hh
		case Intrinsic::hexagon_A2_addh_h16_hl: // llvm.hexagon.A2.a
		ddh.h16.hl
		case Intrinsic::hexagon_A2_addh_h16_lh: // llvm.hexagon.A2.a
		ddh.h16.lh
		case Intrinsic::hexagon_A2_addh_h16_ll: // llvm.hexagon.A2.a
		ddh.h16.ll
		case Intrinsic::hexagon_A2_addh_h16_sat_hh: // llvm.hexagon.A2.a
		ddh.h16.sat.hh
		case Intrinsic::hexagon_A2_addh_h16_sat_hl: // llvm.hexagon.A2.a
		ddh.h16.sat.hl
		case Intrinsic::hexagon_A2_addh_h16_sat_lh: // llvm.hexagon.A2.a
		ddh.h16.sat.lh
		case Intrinsic::hexagon_A2_addh_h16_sat_ll: // llvm.hexagon.A2.a
		ddh.h16.sat.ll
		case Intrinsic::hexagon_A2_addh_l16_hh: // llvm.hexagon.A2.a
		ddh.l16.hh
		case Intrinsic::hexagon_A2_addh_l16_hl: // llvm.hexagon.A2.a
		ddh.l16.hl
		case Intrinsic::hexagon_A2_addh_l16_lh: // llvm.hexagon.A2.a
		ddh.l16.lh
		case Intrinsic::hexagon_A2_addh_l16_ll: // llvm.hexagon.A2.a
		ddh.l16.ll
		case Intrinsic::hexagon_A2_addh_l16_sat_hh: // llvm.hexagon.A2.a
		ddh.l16.sat.hh
		case Intrinsic::hexagon_A2_addh_l16_sat_hl: // llvm.hexagon.A2.a
		ddh.l16.sat.hl
		case Intrinsic::hexagon_A2_addh_l16_sat_lh: // llvm.hexagon.A2.a
		ddh.l16.sat.lh
		case Intrinsic::hexagon_A2_addh_l16_sat_ll: // llvm.hexagon.A2.a
		ddh.l16.sat.ll
		case Intrinsic::hexagon_A2_addi: // llvm.hexagon.A2.addi
		case Intrinsic::hexagon_A2_addsat: // llvm.hexagon.A2.addsat
		case Intrinsic::hexagon_A2_and: // llvm.hexagon.A2.and
		case Intrinsic::hexagon_A2_andir: // llvm.hexagon.A2.andir
		case Intrinsic::hexagon_A2_combine_hh: // llvm.hexagon.A2.c
		ombine.hh
		case Intrinsic::hexagon_A2_combine_hl: // llvm.hexagon.A2.c
		ombine.hl
		case Intrinsic::hexagon_A2_combine_lh: // llvm.hexagon.A2.c
		ombine.lh
		case Intrinsic::hexagon_A2_combine_ll: // llvm.hexagon.A2.c
		ombine.ll
		case Intrinsic::hexagon_A2_max: // llvm.hexagon.A2.max
		case Intrinsic::hexagon_A2_maxu: // llvm.hexagon.A2.maxu
		case Intrinsic::hexagon_A2_min: // llvm.hexagon.A2.min
		case Intrinsic::hexagon_A2_minu: // llvm.hexagon.A2.minu
		case Intrinsic::hexagon_A2_or: // llvm.hexagon.A2.or
		case Intrinsic::hexagon_A2_orir: // llvm.hexagon.A2.orir
		case Intrinsic::hexagon_A2_sub: // llvm.hexagon.A2.sub
		case Intrinsic::hexagon_A2_subh_h16_hh: // llvm.hexagon.A2.s
		ubh.h16.hh
		case Intrinsic::hexagon_A2_subh_h16_hl: // llvm.hexagon.A2.s
		ubh.h16.hl
		case Intrinsic::hexagon_A2_subh_h16_lh: // llvm.hexagon.A2.s
		ubh.h16.lh
		case Intrinsic::hexagon_A2_subh_h16_ll: // llvm.hexagon.A2.s
		ubh.h16.ll
		case Intrinsic::hexagon_A2_subh_h16_sat_hh: // llvm.hexagon.A2.s
		ubh.h16.sat.hh
		case Intrinsic::hexagon_A2_subh_h16_sat_hl: // llvm.hexagon.A2.s
		ubh.h16.sat.hl
		case Intrinsic::hexagon_A2_subh_h16_sat_lh: // llvm.hexagon.A2.s
		ubh.h16.sat.lh
		case Intrinsic::hexagon_A2_subh_h16_sat_ll: // llvm.hexagon.A2.s
		ubh.h16.sat.ll
		case Intrinsic::hexagon_A2_subh_l16_hl: // llvm.hexagon.A2.s
		ubh.l16.hl
		case Intrinsic::hexagon_A2_subh_l16_ll: // llvm.hexagon.A2.s
		ubh.l16.ll
		case Intrinsic::hexagon_A2_subh_l16_sat_hl: // llvm.hexagon.A2.s
		ubh.l16.sat.hl
		case Intrinsic::hexagon_A2_subh_l16_sat_ll: // llvm.hexagon.A2.s
		ubh.l16.sat.ll
		case Intrinsic::hexagon_A2_subri: // llvm.hexagon.A2.subri
		case Intrinsic::hexagon_A2_subsat: // llvm.hexagon.A2.subsat
		case Intrinsic::hexagon_A2_svaddh: // llvm.hexagon.A2.svaddh
		case Intrinsic::hexagon_A2_svaddhs: // llvm.hexagon.A2.svaddhs
		case Intrinsic::hexagon_A2_svadduhs: // llvm.hexagon.A2.svadduhs
		case Intrinsic::hexagon_A2_svavgh: // llvm.hexagon.A2.svavgh
		case Intrinsic::hexagon_A2_svavghs: // llvm.hexagon.A2.svavghs
		case Intrinsic::hexagon_A2_svnavgh: // llvm.hexagon.A2.svnavgh
		case Intrinsic::hexagon_A2_svsubh: // llvm.hexagon.A2.svsubh
		case Intrinsic::hexagon_A2_svsubhs: // llvm.hexagon.A2.svsubhs
		case Intrinsic::hexagon_A2_svsubuhs: // llvm.hexagon.A2.svsubuhs
		case Intrinsic::hexagon_A2_tfrih: // llvm.hexagon.A2.tfrih
		case Intrinsic::hexagon_A2_tfril: // llvm.hexagon.A2.tfril
		case Intrinsic::hexagon_A2_xor: // llvm.hexagon.A2.xor
		case Intrinsic::hexagon_A4_andn: // llvm.hexagon.A4.andn
		case Intrinsic::hexagon_A4_cround_ri: // llvm.hexagon.A4.c
		round.ri
		case Intrinsic::hexagon_A4_cround_rr: // llvm.hexagon.A4.c
		round.rr
		case Intrinsic::hexagon_A4_modwrapu: // llvm.hexagon.A4.modwrapu
		case Intrinsic::hexagon_A4_orn: // llvm.hexagon.A4.orn
		case Intrinsic::hexagon_A4_rcmpeq: // llvm.hexagon.A4.rcmpeq
		case Intrinsic::hexagon_A4_rcmpeqi: // llvm.hexagon.A4.rcmpeqi
		case Intrinsic::hexagon_A4_rcmpneq: // llvm.hexagon.A4.rcmpneq
		case Intrinsic::hexagon_A4_rcmpneqi: // llvm.hexagon.A4.rcmpneqi
		case Intrinsic::hexagon_A4_round_ri: // llvm.hexagon.A4.round.ri
		case Intrinsic::hexagon_A4_round_ri_sat: // llvm.hexagon.A4.r
		ound.ri.sat
		case Intrinsic::hexagon_A4_round_rr: // llvm.hexagon.A4.round.rr
		case Intrinsic::hexagon_A4_round_rr_sat: // llvm.hexagon.A4.r
		ound.rr.sat
		case Intrinsic::hexagon_C2_vitpack: // llvm.hexagon.C2.vitpack
		case Intrinsic::hexagon_M2_cmpyrs_s0: // llvm.hexagon.M2.c
		mpyrs.s0
		case Intrinsic::hexagon_M2_cmpyrs_s1: // llvm.hexagon.M2.c
		mpyrs.s1
		case Intrinsic::hexagon_M2_cmpyrsc_s0: // llvm.hexagon.M2.c
		mpyrsc.s0
		case Intrinsic::hexagon_M2_cmpyrsc_s1: // llvm.hexagon.M2.c
		mpyrsc.s1
		case Intrinsic::hexagon_M2_dpmpyss_rnd_s0: // llvm.hexagon.M2.d
		pmpyss.rnd.s0
		case Intrinsic::hexagon_M2_hmmpyh_rs1: // llvm.hexagon.M2.h
		mmpyh.rs1
		case Intrinsic::hexagon_M2_hmmpyl_rs1: // llvm.hexagon.M2.h
		mmpyl.rs1
		case Intrinsic::hexagon_M2_mpy_hh_s0: // llvm.hexagon.M2.m
		py.hh.s0
		case Intrinsic::hexagon_M2_mpy_hh_s1: // llvm.hexagon.M2.m
		py.hh.s1
		case Intrinsic::hexagon_M2_mpy_hl_s0: // llvm.hexagon.M2.m
		py.hl.s0
		case Intrinsic::hexagon_M2_mpy_hl_s1: // llvm.hexagon.M2.m
		py.hl.s1
		case Intrinsic::hexagon_M2_mpy_lh_s0: // llvm.hexagon.M2.m
		py.lh.s0
		case Intrinsic::hexagon_M2_mpy_lh_s1: // llvm.hexagon.M2.m
		py.lh.s1
		case Intrinsic::hexagon_M2_mpy_ll_s0: // llvm.hexagon.M2.m
		py.ll.s0
		case Intrinsic::hexagon_M2_mpy_ll_s1: // llvm.hexagon.M2.m
		py.ll.s1
		case Intrinsic::hexagon_M2_mpy_rnd_hh_s0: // llvm.hexagon.M2.m
		py.rnd.hh.s0
		case Intrinsic::hexagon_M2_mpy_rnd_hh_s1: // llvm.hexagon.M2.m
		py.rnd.hh.s1
		case Intrinsic::hexagon_M2_mpy_rnd_hl_s0: // llvm.hexagon.M2.m
		py.rnd.hl.s0
		case Intrinsic::hexagon_M2_mpy_rnd_hl_s1: // llvm.hexagon.M2.m
		py.rnd.hl.s1
		case Intrinsic::hexagon_M2_mpy_rnd_lh_s0: // llvm.hexagon.M2.m
		py.rnd.lh.s0
		case Intrinsic::hexagon_M2_mpy_rnd_lh_s1: // llvm.hexagon.M2.m
		py.rnd.lh.s1
		case Intrinsic::hexagon_M2_mpy_rnd_ll_s0: // llvm.hexagon.M2.m
		py.rnd.ll.s0
		case Intrinsic::hexagon_M2_mpy_rnd_ll_s1: // llvm.hexagon.M2.m
		py.rnd.ll.s1
		case Intrinsic::hexagon_M2_mpy_sat_hh_s0: // llvm.hexagon.M2.m
		py.sat.hh.s0
		case Intrinsic::hexagon_M2_mpy_sat_hh_s1: // llvm.hexagon.M2.m
		py.sat.hh.s1
		case Intrinsic::hexagon_M2_mpy_sat_hl_s0: // llvm.hexagon.M2.m
		py.sat.hl.s0
		case Intrinsic::hexagon_M2_mpy_sat_hl_s1: // llvm.hexagon.M2.m
		py.sat.hl.s1
		case Intrinsic::hexagon_M2_mpy_sat_lh_s0: // llvm.hexagon.M2.m
		py.sat.lh.s0
		case Intrinsic::hexagon_M2_mpy_sat_lh_s1: // llvm.hexagon.M2.m
		py.sat.lh.s1
		case Intrinsic::hexagon_M2_mpy_sat_ll_s0: // llvm.hexagon.M2.m
		py.sat.ll.s0
		case Intrinsic::hexagon_M2_mpy_sat_ll_s1: // llvm.hexagon.M2.m
		py.sat.ll.s1
		case Intrinsic::hexagon_M2_mpy_sat_rnd_hh_s0: // llvm.hexa
		gon.M2.mpy.sat.rnd.hh.s0
		case Intrinsic::hexagon_M2_mpy_sat_rnd_hh_s1: // llvm.hexa
		gon.M2.mpy.sat.rnd.hh.s1
		case Intrinsic::hexagon_M2_mpy_sat_rnd_hl_s0: // llvm.hexa
		gon.M2.mpy.sat.rnd.hl.s0
		case Intrinsic::hexagon_M2_mpy_sat_rnd_hl_s1: // llvm.hexa
		gon.M2.mpy.sat.rnd.hl.s1
		case Intrinsic::hexagon_M2_mpy_sat_rnd_lh_s0: // llvm.hexa
		gon.M2.mpy.sat.rnd.lh.s0
		case Intrinsic::hexagon_M2_mpy_sat_rnd_lh_s1: // llvm.hexa
		gon.M2.mpy.sat.rnd.lh.s1
		case Intrinsic::hexagon_M2_mpy_sat_rnd_ll_s0: // llvm.hexa
		gon.M2.mpy.sat.rnd.ll.s0
		case Intrinsic::hexagon_M2_mpy_sat_rnd_ll_s1: // llvm.hexa
		gon.M2.mpy.sat.rnd.ll.s1
		case Intrinsic::hexagon_M2_mpy_up: // llvm.hexagon.M2.mpy.up
		case Intrinsic::hexagon_M2_mpyi: // llvm.hexagon.M2.mpyi
		case Intrinsic::hexagon_M2_mpysmi: // llvm.hexagon.M2.mpysmi
		case Intrinsic::hexagon_M2_mpyu_hh_s0: // llvm.hexagon.M2.m
		pyu.hh.s0
		case Intrinsic::hexagon_M2_mpyu_hh_s1: // llvm.hexagon.M2.m
		pyu.hh.s1
		case Intrinsic::hexagon_M2_mpyu_hl_s0: // llvm.hexagon.M2.m
		pyu.hl.s0
		case Intrinsic::hexagon_M2_mpyu_hl_s1: // llvm.hexagon.M2.m
		pyu.hl.s1
		case Intrinsic::hexagon_M2_mpyu_lh_s0: // llvm.hexagon.M2.m
		pyu.lh.s0
		case Intrinsic::hexagon_M2_mpyu_lh_s1: // llvm.hexagon.M2.m
		pyu.lh.s1
		case Intrinsic::hexagon_M2_mpyu_ll_s0: // llvm.hexagon.M2.m
		pyu.ll.s0
		case Intrinsic::hexagon_M2_mpyu_ll_s1: // llvm.hexagon.M2.m
		pyu.ll.s1
		case Intrinsic::hexagon_M2_mpyu_up: // llvm.hexagon.M2.mpyu.up
		case Intrinsic::hexagon_M2_mpyui: // llvm.hexagon.M2.mpyui
		case Intrinsic::hexagon_M2_vmpy2s_s0pack: // llvm.hexagon.M2.v
		mpy2s.s0pack
		case Intrinsic::hexagon_M2_vmpy2s_s1pack: // llvm.hexagon.M2.v
		mpy2s.s1pack
		case Intrinsic::hexagon_S2_asl_i_r: // llvm.hexagon.S2.asl.i.r
		case Intrinsic::hexagon_S2_asl_i_r_sat: // llvm.hexagon.S2.a
		sl.i.r.sat
		case Intrinsic::hexagon_S2_asl_r_r: // llvm.hexagon.S2.asl.r.r
		case Intrinsic::hexagon_S2_asl_r_r_sat: // llvm.hexagon.S2.a
		sl.r.r.sat
		case Intrinsic::hexagon_S2_asr_i_r: // llvm.hexagon.S2.asr.i.r
		case Intrinsic::hexagon_S2_asr_i_r_rnd: // llvm.hexagon.S2.a
		sr.i.r.rnd
		case Intrinsic::hexagon_S2_asr_i_r_rnd_goodsyntax: // llvm.hexa
		gon.S2.asr.i.r.rnd.goodsyntax
		case Intrinsic::hexagon_S2_asr_r_r: // llvm.hexagon.S2.asr.r.r
		case Intrinsic::hexagon_S2_asr_r_r_sat: // llvm.hexagon.S2.a
		sr.r.r.sat
		case Intrinsic::hexagon_S2_clrbit_i: // llvm.hexagon.S2.clrbit.i
		case Intrinsic::hexagon_S2_clrbit_r: // llvm.hexagon.S2.clrbit.r
		case Intrinsic::hexagon_S2_lsl_r_r: // llvm.hexagon.S2.lsl.r.r
		case Intrinsic::hexagon_S2_lsr_i_r: // llvm.hexagon.S2.lsr.i.r
		case Intrinsic::hexagon_S2_lsr_r_r: // llvm.hexagon.S2.lsr.r.r
		case Intrinsic::hexagon_S2_setbit_i: // llvm.hexagon.S2.setbit.i
		case Intrinsic::hexagon_S2_setbit_r: // llvm.hexagon.S2.setbit.r
		case Intrinsic::hexagon_S2_togglebit_i: // llvm.hexagon.S2.t
		ogglebit.i
		case Intrinsic::hexagon_S2_togglebit_r: // llvm.hexagon.S2.t
		ogglebit.r
		case Intrinsic::x86_bmi_bextr_32: // llvm.x86.bmi.bextr.32
		case Intrinsic::x86_bmi_bzhi_32: // llvm.x86.bmi.bzhi.32
		case Intrinsic::x86_bmi_pdep_32: // llvm.x86.bmi.pdep.32
		case Intrinsic::x86_bmi_pext_32: // llvm.x86.bmi.pext.32
	case Intrinsic::x86_sse42_crc32_32_32: // llvm.x86.sse42.cr c32.32.32	case Intrinsic::x86_sse42_crc32_32_32: // llvm.x86.sse42.cr c32.32.32
	case Intrinsic::xcore_sext: // llvm.xcore.sext	case Intrinsic::xcore_sext: // llvm.xcore.sext
	case Intrinsic::xcore_zext: // llvm.xcore.zext	case Intrinsic::xcore_zext: // llvm.xcore.zext
	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::i32, MVT::i32, MVT::i32);	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::i32, MVT::i32, MVT::i32);
	break;	break;

		case Intrinsic::hexagon_C2_mux: // llvm.hexagon.C2.mux
		case Intrinsic::hexagon_C2_muxii: // llvm.hexagon.C2.muxii
		case Intrinsic::hexagon_C2_muxir: // llvm.hexagon.C2.muxir
		case Intrinsic::hexagon_C2_muxri: // llvm.hexagon.C2.muxri
		case Intrinsic::hexagon_M2_acci: // llvm.hexagon.M2.acci
		case Intrinsic::hexagon_M2_accii: // llvm.hexagon.M2.accii
		case Intrinsic::hexagon_M2_maci: // llvm.hexagon.M2.maci
		case Intrinsic::hexagon_M2_macsin: // llvm.hexagon.M2.macsin
		case Intrinsic::hexagon_M2_macsip: // llvm.hexagon.M2.macsip
		case Intrinsic::hexagon_M2_mpy_acc_hh_s0: // llvm.hexagon.M2.m
		py.acc.hh.s0
		case Intrinsic::hexagon_M2_mpy_acc_hh_s1: // llvm.hexagon.M2.m
		py.acc.hh.s1
		case Intrinsic::hexagon_M2_mpy_acc_hl_s0: // llvm.hexagon.M2.m
		py.acc.hl.s0
		case Intrinsic::hexagon_M2_mpy_acc_hl_s1: // llvm.hexagon.M2.m
		py.acc.hl.s1
		case Intrinsic::hexagon_M2_mpy_acc_lh_s0: // llvm.hexagon.M2.m
		py.acc.lh.s0
		case Intrinsic::hexagon_M2_mpy_acc_lh_s1: // llvm.hexagon.M2.m
		py.acc.lh.s1
		case Intrinsic::hexagon_M2_mpy_acc_ll_s0: // llvm.hexagon.M2.m
		py.acc.ll.s0
		case Intrinsic::hexagon_M2_mpy_acc_ll_s1: // llvm.hexagon.M2.m
		py.acc.ll.s1
		case Intrinsic::hexagon_M2_mpy_acc_sat_hh_s0: // llvm.hexa
		gon.M2.mpy.acc.sat.hh.s0
		case Intrinsic::hexagon_M2_mpy_acc_sat_hh_s1: // llvm.hexa
		gon.M2.mpy.acc.sat.hh.s1
		case Intrinsic::hexagon_M2_mpy_acc_sat_hl_s0: // llvm.hexa
		gon.M2.mpy.acc.sat.hl.s0
		case Intrinsic::hexagon_M2_mpy_acc_sat_hl_s1: // llvm.hexa
		gon.M2.mpy.acc.sat.hl.s1
		case Intrinsic::hexagon_M2_mpy_acc_sat_lh_s0: // llvm.hexa
		gon.M2.mpy.acc.sat.lh.s0
		case Intrinsic::hexagon_M2_mpy_acc_sat_lh_s1: // llvm.hexa
		gon.M2.mpy.acc.sat.lh.s1
		case Intrinsic::hexagon_M2_mpy_acc_sat_ll_s0: // llvm.hexa
		gon.M2.mpy.acc.sat.ll.s0
		case Intrinsic::hexagon_M2_mpy_acc_sat_ll_s1: // llvm.hexa
		gon.M2.mpy.acc.sat.ll.s1
		case Intrinsic::hexagon_M2_mpy_nac_hh_s0: // llvm.hexagon.M2.m
		py.nac.hh.s0
		case Intrinsic::hexagon_M2_mpy_nac_hh_s1: // llvm.hexagon.M2.m
		py.nac.hh.s1
		case Intrinsic::hexagon_M2_mpy_nac_hl_s0: // llvm.hexagon.M2.m
		py.nac.hl.s0
		case Intrinsic::hexagon_M2_mpy_nac_hl_s1: // llvm.hexagon.M2.m
		py.nac.hl.s1
		case Intrinsic::hexagon_M2_mpy_nac_lh_s0: // llvm.hexagon.M2.m
		py.nac.lh.s0
		case Intrinsic::hexagon_M2_mpy_nac_lh_s1: // llvm.hexagon.M2.m
		py.nac.lh.s1
		case Intrinsic::hexagon_M2_mpy_nac_ll_s0: // llvm.hexagon.M2.m
		py.nac.ll.s0
		case Intrinsic::hexagon_M2_mpy_nac_ll_s1: // llvm.hexagon.M2.m
		py.nac.ll.s1
		case Intrinsic::hexagon_M2_mpy_nac_sat_hh_s0: // llvm.hexa
		gon.M2.mpy.nac.sat.hh.s0
		case Intrinsic::hexagon_M2_mpy_nac_sat_hh_s1: // llvm.hexa
		gon.M2.mpy.nac.sat.hh.s1
		case Intrinsic::hexagon_M2_mpy_nac_sat_hl_s0: // llvm.hexa
		gon.M2.mpy.nac.sat.hl.s0
		case Intrinsic::hexagon_M2_mpy_nac_sat_hl_s1: // llvm.hexa
		gon.M2.mpy.nac.sat.hl.s1
		case Intrinsic::hexagon_M2_mpy_nac_sat_lh_s0: // llvm.hexa
		gon.M2.mpy.nac.sat.lh.s0
		case Intrinsic::hexagon_M2_mpy_nac_sat_lh_s1: // llvm.hexa
		gon.M2.mpy.nac.sat.lh.s1
		case Intrinsic::hexagon_M2_mpy_nac_sat_ll_s0: // llvm.hexa
		gon.M2.mpy.nac.sat.ll.s0
		case Intrinsic::hexagon_M2_mpy_nac_sat_ll_s1: // llvm.hexa
		gon.M2.mpy.nac.sat.ll.s1
		case Intrinsic::hexagon_M2_mpyu_acc_hh_s0: // llvm.hexagon.M2.m
		pyu.acc.hh.s0
		case Intrinsic::hexagon_M2_mpyu_acc_hh_s1: // llvm.hexagon.M2.m
		pyu.acc.hh.s1
		case Intrinsic::hexagon_M2_mpyu_acc_hl_s0: // llvm.hexagon.M2.m
		pyu.acc.hl.s0
		case Intrinsic::hexagon_M2_mpyu_acc_hl_s1: // llvm.hexagon.M2.m
		pyu.acc.hl.s1
		case Intrinsic::hexagon_M2_mpyu_acc_lh_s0: // llvm.hexagon.M2.m
		pyu.acc.lh.s0
		case Intrinsic::hexagon_M2_mpyu_acc_lh_s1: // llvm.hexagon.M2.m
		pyu.acc.lh.s1
		case Intrinsic::hexagon_M2_mpyu_acc_ll_s0: // llvm.hexagon.M2.m
		pyu.acc.ll.s0
		case Intrinsic::hexagon_M2_mpyu_acc_ll_s1: // llvm.hexagon.M2.m
		pyu.acc.ll.s1
		case Intrinsic::hexagon_M2_mpyu_nac_hh_s0: // llvm.hexagon.M2.m
		pyu.nac.hh.s0
		case Intrinsic::hexagon_M2_mpyu_nac_hh_s1: // llvm.hexagon.M2.m
		pyu.nac.hh.s1
		case Intrinsic::hexagon_M2_mpyu_nac_hl_s0: // llvm.hexagon.M2.m
		pyu.nac.hl.s0
		case Intrinsic::hexagon_M2_mpyu_nac_hl_s1: // llvm.hexagon.M2.m
		pyu.nac.hl.s1
		case Intrinsic::hexagon_M2_mpyu_nac_lh_s0: // llvm.hexagon.M2.m
		pyu.nac.lh.s0
		case Intrinsic::hexagon_M2_mpyu_nac_lh_s1: // llvm.hexagon.M2.m
		pyu.nac.lh.s1
		case Intrinsic::hexagon_M2_mpyu_nac_ll_s0: // llvm.hexagon.M2.m
		pyu.nac.ll.s0
		case Intrinsic::hexagon_M2_mpyu_nac_ll_s1: // llvm.hexagon.M2.m
		pyu.nac.ll.s1
		case Intrinsic::hexagon_M2_nacci: // llvm.hexagon.M2.nacci
		case Intrinsic::hexagon_M2_naccii: // llvm.hexagon.M2.naccii
		case Intrinsic::hexagon_M2_subacc: // llvm.hexagon.M2.subacc
		case Intrinsic::hexagon_M2_xor_xacc: // llvm.hexagon.M2.xor.xacc
		case Intrinsic::hexagon_M4_and_and: // llvm.hexagon.M4.and.and
		case Intrinsic::hexagon_M4_and_andn: // llvm.hexagon.M4.and.andn
		case Intrinsic::hexagon_M4_and_or: // llvm.hexagon.M4.and.or
		case Intrinsic::hexagon_M4_and_xor: // llvm.hexagon.M4.and.xor
		case Intrinsic::hexagon_M4_or_and: // llvm.hexagon.M4.or.and
		case Intrinsic::hexagon_M4_or_andn: // llvm.hexagon.M4.or.andn
		case Intrinsic::hexagon_M4_or_or: // llvm.hexagon.M4.or.or
		case Intrinsic::hexagon_M4_or_xor: // llvm.hexagon.M4.or.xor
		case Intrinsic::hexagon_M4_xor_and: // llvm.hexagon.M4.xor.and
		case Intrinsic::hexagon_M4_xor_andn: // llvm.hexagon.M4.xor.andn
		case Intrinsic::hexagon_M4_xor_or: // llvm.hexagon.M4.xor.or
		case Intrinsic::hexagon_S2_addasl_rrri: // llvm.hexagon.S2.a
		ddasl.rrri
		case Intrinsic::hexagon_S2_asl_i_r_acc: // llvm.hexagon.S2.a
		sl.i.r.acc
		case Intrinsic::hexagon_S2_asl_i_r_and: // llvm.hexagon.S2.a
		sl.i.r.and
		case Intrinsic::hexagon_S2_asl_i_r_nac: // llvm.hexagon.S2.a
		sl.i.r.nac
		case Intrinsic::hexagon_S2_asl_i_r_or: // llvm.hexagon.S2.a
		sl.i.r.or
		case Intrinsic::hexagon_S2_asl_i_r_xacc: // llvm.hexagon.S2.a
		sl.i.r.xacc
		case Intrinsic::hexagon_S2_asl_r_r_acc: // llvm.hexagon.S2.a
		sl.r.r.acc
		case Intrinsic::hexagon_S2_asl_r_r_and: // llvm.hexagon.S2.a
		sl.r.r.and
		case Intrinsic::hexagon_S2_asl_r_r_nac: // llvm.hexagon.S2.a
		sl.r.r.nac
		case Intrinsic::hexagon_S2_asl_r_r_or: // llvm.hexagon.S2.a
		sl.r.r.or
		case Intrinsic::hexagon_S2_asr_i_r_acc: // llvm.hexagon.S2.a
		sr.i.r.acc
		case Intrinsic::hexagon_S2_asr_i_r_and: // llvm.hexagon.S2.a
		sr.i.r.and
		case Intrinsic::hexagon_S2_asr_i_r_nac: // llvm.hexagon.S2.a
		sr.i.r.nac
		case Intrinsic::hexagon_S2_asr_i_r_or: // llvm.hexagon.S2.a
		sr.i.r.or
		case Intrinsic::hexagon_S2_asr_r_r_acc: // llvm.hexagon.S2.a
		sr.r.r.acc
		case Intrinsic::hexagon_S2_asr_r_r_and: // llvm.hexagon.S2.a
		sr.r.r.and
		case Intrinsic::hexagon_S2_asr_r_r_nac: // llvm.hexagon.S2.a
		sr.r.r.nac
		case Intrinsic::hexagon_S2_asr_r_r_or: // llvm.hexagon.S2.a
		sr.r.r.or
		case Intrinsic::hexagon_S2_extractu: // llvm.hexagon.S2.extractu
		case Intrinsic::hexagon_S2_lsl_r_r_acc: // llvm.hexagon.S2.l
		sl.r.r.acc
		case Intrinsic::hexagon_S2_lsl_r_r_and: // llvm.hexagon.S2.l
		sl.r.r.and
		case Intrinsic::hexagon_S2_lsl_r_r_nac: // llvm.hexagon.S2.l
		sl.r.r.nac
		case Intrinsic::hexagon_S2_lsl_r_r_or: // llvm.hexagon.S2.l
		sl.r.r.or
		case Intrinsic::hexagon_S2_lsr_i_r_acc: // llvm.hexagon.S2.l
		sr.i.r.acc
		case Intrinsic::hexagon_S2_lsr_i_r_and: // llvm.hexagon.S2.l
		sr.i.r.and
		case Intrinsic::hexagon_S2_lsr_i_r_nac: // llvm.hexagon.S2.l
		sr.i.r.nac
		case Intrinsic::hexagon_S2_lsr_i_r_or: // llvm.hexagon.S2.l
		sr.i.r.or
		case Intrinsic::hexagon_S2_lsr_i_r_xacc: // llvm.hexagon.S2.l
		sr.i.r.xacc
		case Intrinsic::hexagon_S2_lsr_r_r_acc: // llvm.hexagon.S2.l
		sr.r.r.acc
		case Intrinsic::hexagon_S2_lsr_r_r_and: // llvm.hexagon.S2.l
		sr.r.r.and
		case Intrinsic::hexagon_S2_lsr_r_r_nac: // llvm.hexagon.S2.l
		sr.r.r.nac
		case Intrinsic::hexagon_S2_lsr_r_r_or: // llvm.hexagon.S2.l
		sr.r.r.or
		case Intrinsic::hexagon_S4_addaddi: // llvm.hexagon.S4.addaddi
		case Intrinsic::hexagon_S4_or_andi: // llvm.hexagon.S4.or.andi
		case Intrinsic::hexagon_S4_or_andix: // llvm.hexagon.S4.or.andix
		case Intrinsic::hexagon_S4_or_ori: // llvm.hexagon.S4.or.ori
		case Intrinsic::hexagon_S4_subaddi: // llvm.hexagon.S4.subaddi
	case Intrinsic::xcore_crc32: // llvm.xcore.crc32	case Intrinsic::xcore_crc32: // llvm.xcore.crc32
	VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::i32, MVT::i32, MVT::i32, MV T::i32);	VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::i32, MVT::i32, MVT::i32, MV T::i32);
	break;	break;

		case Intrinsic::hexagon_S2_insert: // llvm.hexagon.S2.insert
		case Intrinsic::hexagon_S2_tableidxb_goodsyntax: // llvm.hexa
		gon.S2.tableidxb.goodsyntax
		case Intrinsic::hexagon_S2_tableidxd_goodsyntax: // llvm.hexa
		gon.S2.tableidxd.goodsyntax
		case Intrinsic::hexagon_S2_tableidxh_goodsyntax: // llvm.hexa
		gon.S2.tableidxh.goodsyntax
		case Intrinsic::hexagon_S2_tableidxw_goodsyntax: // llvm.hexa
		gon.S2.tableidxw.goodsyntax
		VerifyIntrinsicPrototype(ID, IF, 1, 4, MVT::i32, MVT::i32, MVT::i32, MV
		T::i32, MVT::i32);
		break;
	case Intrinsic::arm_mrc: // llvm.arm.mrc	case Intrinsic::arm_mrc: // llvm.arm.mrc
	case Intrinsic::arm_mrc2: // llvm.arm.mrc2	case Intrinsic::arm_mrc2: // llvm.arm.mrc2
	VerifyIntrinsicPrototype(ID, IF, 1, 5, MVT::i32, MVT::i32, MVT::i32, MV T::i32, MVT::i32, MVT::i32);	VerifyIntrinsicPrototype(ID, IF, 1, 5, MVT::i32, MVT::i32, MVT::i32, MV T::i32, MVT::i32, MVT::i32);
	break;	break;

		case Intrinsic::hexagon_S2_insert_rp: // llvm.hexagon.S2.i
		nsert.rp
		VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::i32, MVT::i32, MVT::i32, MV
		T::i64);
		break;
	case Intrinsic::arm_strexd: // llvm.arm.strexd	case Intrinsic::arm_strexd: // llvm.arm.strexd
	VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::i32, MVT::i32, MVT::i32, MV T::iPTR);	VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::i32, MVT::i32, MVT::i32, MV T::iPTR);
	break;	break;

		case Intrinsic::hexagon_S2_extractu_rp: // llvm.hexagon.S2.e
		xtractu.rp
		VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::i32, MVT::i32, MVT::i64);
		break;
	case Intrinsic::x86_sse42_crc32_32_8: // llvm.x86.sse42.cr c32.32.8	case Intrinsic::x86_sse42_crc32_32_8: // llvm.x86.sse42.cr c32.32.8
	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::i32, MVT::i32, MVT::i8);	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::i32, MVT::i32, MVT::i8);
	break;	break;
	case Intrinsic::ppc_altivec_vcmpequb_p: // llvm.ppc.altivec. vcmpequb.p	case Intrinsic::ppc_altivec_vcmpequb_p: // llvm.ppc.altivec. vcmpequb.p
	case Intrinsic::ppc_altivec_vcmpgtsb_p: // llvm.ppc.altivec. vcmpgtsb.p	case Intrinsic::ppc_altivec_vcmpgtsb_p: // llvm.ppc.altivec. vcmpgtsb.p
	case Intrinsic::ppc_altivec_vcmpgtub_p: // llvm.ppc.altivec. vcmpgtub.p	case Intrinsic::ppc_altivec_vcmpgtub_p: // llvm.ppc.altivec. vcmpgtub.p
	VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::i32, MVT::i32, MVT::v16i8, MVT::v16i8);	VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::i32, MVT::i32, MVT::v16i8, MVT::v16i8);
	break;	break;
	case Intrinsic::ppc_altivec_vcmpbfp_p: // llvm.ppc.altivec. vcmpbfp.p	case Intrinsic::ppc_altivec_vcmpbfp_p: // llvm.ppc.altivec. vcmpbfp.p
	case Intrinsic::ppc_altivec_vcmpeqfp_p: // llvm.ppc.altivec. vcmpeqfp.p	case Intrinsic::ppc_altivec_vcmpeqfp_p: // llvm.ppc.altivec. vcmpeqfp.p

	skipping to change at line 9425	skipping to change at line 18016
	case Intrinsic::ppc_altivec_vcmpequw_p: // llvm.ppc.altivec. vcmpequw.p	case Intrinsic::ppc_altivec_vcmpequw_p: // llvm.ppc.altivec. vcmpequw.p
	case Intrinsic::ppc_altivec_vcmpgtsw_p: // llvm.ppc.altivec. vcmpgtsw.p	case Intrinsic::ppc_altivec_vcmpgtsw_p: // llvm.ppc.altivec. vcmpgtsw.p
	case Intrinsic::ppc_altivec_vcmpgtuw_p: // llvm.ppc.altivec. vcmpgtuw.p	case Intrinsic::ppc_altivec_vcmpgtuw_p: // llvm.ppc.altivec. vcmpgtuw.p
	VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::i32, MVT::i32, MVT::v4i32, MVT::v4i32);	VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::i32, MVT::i32, MVT::v4i32, MVT::v4i32);
	break;	break;
	case Intrinsic::ppc_altivec_vcmpequh_p: // llvm.ppc.altivec. vcmpequh.p	case Intrinsic::ppc_altivec_vcmpequh_p: // llvm.ppc.altivec. vcmpequh.p
	case Intrinsic::ppc_altivec_vcmpgtsh_p: // llvm.ppc.altivec. vcmpgtsh.p	case Intrinsic::ppc_altivec_vcmpgtsh_p: // llvm.ppc.altivec. vcmpgtsh.p
	case Intrinsic::ppc_altivec_vcmpgtuh_p: // llvm.ppc.altivec. vcmpgtuh.p	case Intrinsic::ppc_altivec_vcmpgtuh_p: // llvm.ppc.altivec. vcmpgtuh.p
	VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::i32, MVT::i32, MVT::v8i16, MVT::v8i16);	VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::i32, MVT::i32, MVT::v8i16, MVT::v8i16);
	break;	break;

		case Intrinsic::hexagon_A2_sat: // llvm.hexagon.A2.sat
		case Intrinsic::hexagon_S2_cl0p: // llvm.hexagon.S2.cl0p
		case Intrinsic::hexagon_S2_cl1p: // llvm.hexagon.S2.cl1p
		case Intrinsic::hexagon_S2_clbp: // llvm.hexagon.S2.clbp
		case Intrinsic::hexagon_S2_vrndpackwh: // llvm.hexagon.S2.v
		rndpackwh
		case Intrinsic::hexagon_S2_vrndpackwhs: // llvm.hexagon.S2.v
		rndpackwhs
		case Intrinsic::hexagon_S2_vsathb: // llvm.hexagon.S2.vsathb
		case Intrinsic::hexagon_S2_vsathub: // llvm.hexagon.S2.vsathub
		case Intrinsic::hexagon_S2_vsatwh: // llvm.hexagon.S2.vsatwh
		case Intrinsic::hexagon_S2_vsatwuh: // llvm.hexagon.S2.vsatwuh
		case Intrinsic::hexagon_S2_vtrunehb: // llvm.hexagon.S2.vtrunehb
		case Intrinsic::hexagon_S2_vtrunohb: // llvm.hexagon.S2.vtrunohb
		VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::i32, MVT::i64);
		break;
		case Intrinsic::hexagon_M2_vrcmpys_s1rp: // llvm.hexagon.M2.v
		rcmpys.s1rp
		case Intrinsic::hexagon_S2_asr_i_svw_trun: // llvm.hexagon.S2.a
		sr.i.svw.trun
		case Intrinsic::hexagon_S2_asr_r_svw_trun: // llvm.hexagon.S2.a
		sr.r.svw.trun
		VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::i32, MVT::i64, MVT::i32);
		break;
		case Intrinsic::hexagon_M2_vdmpyrs_s0: // llvm.hexagon.M2.v
		dmpyrs.s0
		case Intrinsic::hexagon_M2_vdmpyrs_s1: // llvm.hexagon.M2.v
		dmpyrs.s1
		case Intrinsic::hexagon_M2_vradduh: // llvm.hexagon.M2.vradduh
		case Intrinsic::hexagon_S2_parityp: // llvm.hexagon.S2.parityp
		VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::i32, MVT::i64, MVT::i64);
		break;
	case Intrinsic::eh_sjlj_setjmp: // llvm.eh.sjlj.setjmp	case Intrinsic::eh_sjlj_setjmp: // llvm.eh.sjlj.setjmp
	case Intrinsic::eh_typeid_for: // llvm.eh.typeid.for	case Intrinsic::eh_typeid_for: // llvm.eh.typeid.for
	case Intrinsic::setjmp: // llvm.setjmp	case Intrinsic::setjmp: // llvm.setjmp
	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::i32, MVT::iPTR);	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::i32, MVT::iPTR);
	break;	break;
	case Intrinsic::sigsetjmp: // llvm.sigsetjmp	case Intrinsic::sigsetjmp: // llvm.sigsetjmp
	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::i32, MVT::iPTR, MVT::i32);	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::i32, MVT::iPTR, MVT::i32);
	break;	break;

	case Intrinsic::eh_selector: // llvm.eh.selector
	VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::i32, MVT::iPTR, MVT::iPTR,
	MVT::isVoid);
	break;
	case Intrinsic::x86_sse2_pmovmskb_128: // llvm.x86.sse2.pmo vmskb.128	case Intrinsic::x86_sse2_pmovmskb_128: // llvm.x86.sse2.pmo vmskb.128
	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::i32, MVT::v16i8);	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::i32, MVT::v16i8);
	break;	break;
	case Intrinsic::x86_sse41_pextrb: // llvm.x86.sse41.pextrb	case Intrinsic::x86_sse41_pextrb: // llvm.x86.sse41.pextrb
	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::i32, MVT::v16i8, MVT::i32);	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::i32, MVT::v16i8, MVT::i32);
	break;	break;
	case Intrinsic::x86_sse42_pcmpestri128: // llvm.x86.sse42.pc mpestri128	case Intrinsic::x86_sse42_pcmpestri128: // llvm.x86.sse42.pc mpestri128
	case Intrinsic::x86_sse42_pcmpestria128: // llvm.x86.sse42.pc mpestria128	case Intrinsic::x86_sse42_pcmpestria128: // llvm.x86.sse42.pc mpestria128
	case Intrinsic::x86_sse42_pcmpestric128: // llvm.x86.sse42.pc mpestric128	case Intrinsic::x86_sse42_pcmpestric128: // llvm.x86.sse42.pc mpestric128
	case Intrinsic::x86_sse42_pcmpestrio128: // llvm.x86.sse42.pc mpestrio128	case Intrinsic::x86_sse42_pcmpestrio128: // llvm.x86.sse42.pc mpestrio128

	skipping to change at line 9480	skipping to change at line 18093
	case Intrinsic::x86_sse2_comilt_sd: // llvm.x86.sse2.comilt.sd	case Intrinsic::x86_sse2_comilt_sd: // llvm.x86.sse2.comilt.sd
	case Intrinsic::x86_sse2_comineq_sd: // llvm.x86.sse2.comineq.sd	case Intrinsic::x86_sse2_comineq_sd: // llvm.x86.sse2.comineq.sd
	case Intrinsic::x86_sse2_ucomieq_sd: // llvm.x86.sse2.ucomieq.sd	case Intrinsic::x86_sse2_ucomieq_sd: // llvm.x86.sse2.ucomieq.sd
	case Intrinsic::x86_sse2_ucomige_sd: // llvm.x86.sse2.ucomige.sd	case Intrinsic::x86_sse2_ucomige_sd: // llvm.x86.sse2.ucomige.sd
	case Intrinsic::x86_sse2_ucomigt_sd: // llvm.x86.sse2.ucomigt.sd	case Intrinsic::x86_sse2_ucomigt_sd: // llvm.x86.sse2.ucomigt.sd
	case Intrinsic::x86_sse2_ucomile_sd: // llvm.x86.sse2.ucomile.sd	case Intrinsic::x86_sse2_ucomile_sd: // llvm.x86.sse2.ucomile.sd
	case Intrinsic::x86_sse2_ucomilt_sd: // llvm.x86.sse2.ucomilt.sd	case Intrinsic::x86_sse2_ucomilt_sd: // llvm.x86.sse2.ucomilt.sd
	case Intrinsic::x86_sse2_ucomineq_sd: // llvm.x86.sse2.uco mineq.sd	case Intrinsic::x86_sse2_ucomineq_sd: // llvm.x86.sse2.uco mineq.sd
	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::i32, MVT::v2f64, MVT::v2f64 );	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::i32, MVT::v2f64, MVT::v2f64 );
	break;	break;

		case Intrinsic::x86_sse41_ptestc: // llvm.x86.sse41.ptestc
		case Intrinsic::x86_sse41_ptestnzc: // llvm.x86.sse41.ptestnzc
		case Intrinsic::x86_sse41_ptestz: // llvm.x86.sse41.ptestz
		VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::i32, MVT::v2i64, MVT::v2i64
		);
		break;
		case Intrinsic::x86_avx2_pmovmskb: // llvm.x86.avx2.pmovmskb
		VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::i32, MVT::v32i8);
		break;
	case Intrinsic::x86_sse_cvtss2si: // llvm.x86.sse.cvtss2si	case Intrinsic::x86_sse_cvtss2si: // llvm.x86.sse.cvtss2si
	case Intrinsic::x86_sse_cvttss2si: // llvm.x86.sse.cvttss2si	case Intrinsic::x86_sse_cvttss2si: // llvm.x86.sse.cvttss2si
	case Intrinsic::x86_sse_movmsk_ps: // llvm.x86.sse.movmsk.ps	case Intrinsic::x86_sse_movmsk_ps: // llvm.x86.sse.movmsk.ps
	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::i32, MVT::v4f32);	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::i32, MVT::v4f32);
	break;	break;
	case Intrinsic::x86_sse41_extractps: // llvm.x86.sse41.extractps	case Intrinsic::x86_sse41_extractps: // llvm.x86.sse41.extractps
	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::i32, MVT::v4f32, MVT::i32);	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::i32, MVT::v4f32, MVT::i32);
	break;	break;
	case Intrinsic::x86_avx_vtestc_ps: // llvm.x86.avx.vtestc.ps	case Intrinsic::x86_avx_vtestc_ps: // llvm.x86.avx.vtestc.ps
	case Intrinsic::x86_avx_vtestnzc_ps: // llvm.x86.avx.vtestnzc.ps	case Intrinsic::x86_avx_vtestnzc_ps: // llvm.x86.avx.vtestnzc.ps
	case Intrinsic::x86_avx_vtestz_ps: // llvm.x86.avx.vtestz.ps	case Intrinsic::x86_avx_vtestz_ps: // llvm.x86.avx.vtestz.ps

	case Intrinsic::x86_sse41_ptestc: // llvm.x86.sse41.ptestc
	case Intrinsic::x86_sse41_ptestnzc: // llvm.x86.sse41.ptestnzc
	case Intrinsic::x86_sse41_ptestz: // llvm.x86.sse41.ptestz
	case Intrinsic::x86_sse_comieq_ss: // llvm.x86.sse.comieq.ss	case Intrinsic::x86_sse_comieq_ss: // llvm.x86.sse.comieq.ss
	case Intrinsic::x86_sse_comige_ss: // llvm.x86.sse.comige.ss	case Intrinsic::x86_sse_comige_ss: // llvm.x86.sse.comige.ss
	case Intrinsic::x86_sse_comigt_ss: // llvm.x86.sse.comigt.ss	case Intrinsic::x86_sse_comigt_ss: // llvm.x86.sse.comigt.ss
	case Intrinsic::x86_sse_comile_ss: // llvm.x86.sse.comile.ss	case Intrinsic::x86_sse_comile_ss: // llvm.x86.sse.comile.ss
	case Intrinsic::x86_sse_comilt_ss: // llvm.x86.sse.comilt.ss	case Intrinsic::x86_sse_comilt_ss: // llvm.x86.sse.comilt.ss
	case Intrinsic::x86_sse_comineq_ss: // llvm.x86.sse.comineq.ss	case Intrinsic::x86_sse_comineq_ss: // llvm.x86.sse.comineq.ss
	case Intrinsic::x86_sse_ucomieq_ss: // llvm.x86.sse.ucomieq.ss	case Intrinsic::x86_sse_ucomieq_ss: // llvm.x86.sse.ucomieq.ss
	case Intrinsic::x86_sse_ucomige_ss: // llvm.x86.sse.ucomige.ss	case Intrinsic::x86_sse_ucomige_ss: // llvm.x86.sse.ucomige.ss
	case Intrinsic::x86_sse_ucomigt_ss: // llvm.x86.sse.ucomigt.ss	case Intrinsic::x86_sse_ucomigt_ss: // llvm.x86.sse.ucomigt.ss
	case Intrinsic::x86_sse_ucomile_ss: // llvm.x86.sse.ucomile.ss	case Intrinsic::x86_sse_ucomile_ss: // llvm.x86.sse.ucomile.ss

	skipping to change at line 9546	skipping to change at line 18164
	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::i32, MVT::x86mmx, MVT::i32) ;	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::i32, MVT::x86mmx, MVT::i32) ;
	break;	break;
	case Intrinsic::xcore_crc8: // llvm.xcore.crc8	case Intrinsic::xcore_crc8: // llvm.xcore.crc8
	VerifyIntrinsicPrototype(ID, IF, 2, 3, MVT::i32, MVT::i32, MVT::i32, MV T::i32, MVT::i32);	VerifyIntrinsicPrototype(ID, IF, 2, 3, MVT::i32, MVT::i32, MVT::i32, MV T::i32, MVT::i32);
	break;	break;
	case Intrinsic::arm_ldrexd: // llvm.arm.ldrexd	case Intrinsic::arm_ldrexd: // llvm.arm.ldrexd
	VerifyIntrinsicPrototype(ID, IF, 2, 1, MVT::i32, MVT::i32, MVT::iPTR);	VerifyIntrinsicPrototype(ID, IF, 2, 1, MVT::i32, MVT::i32, MVT::iPTR);
	break;	break;
	case Intrinsic::ptx_read_clock64: // llvm.ptx.read.clock64	case Intrinsic::ptx_read_clock64: // llvm.ptx.read.clock64
	case Intrinsic::readcyclecounter: // llvm.readcyclecounter	case Intrinsic::readcyclecounter: // llvm.readcyclecounter

		case Intrinsic::x86_rdfsbase_64: // llvm.x86.rdfsbase.64
		case Intrinsic::x86_rdgsbase_64: // llvm.x86.rdgsbase.64
	VerifyIntrinsicPrototype(ID, IF, 1, 0, MVT::i64);	VerifyIntrinsicPrototype(ID, IF, 1, 0, MVT::i64);
	break;	break;

	case Intrinsic::alpha_umulh: // llvm.alpha.umulh	case Intrinsic::hexagon_A2_sxtw: // llvm.hexagon.A2.sxtw
		case Intrinsic::hexagon_A2_tfrpi: // llvm.hexagon.A2.tfrpi
		case Intrinsic::hexagon_C2_mask: // llvm.hexagon.C2.mask
		case Intrinsic::hexagon_S2_vsplatrh: // llvm.hexagon.S2.vsplatrh
		case Intrinsic::hexagon_S2_vsxtbh: // llvm.hexagon.S2.vsxtbh
		case Intrinsic::hexagon_S2_vsxthw: // llvm.hexagon.S2.vsxthw
		case Intrinsic::hexagon_S2_vzxtbh: // llvm.hexagon.S2.vzxtbh
		case Intrinsic::hexagon_S2_vzxthw: // llvm.hexagon.S2.vzxthw
		VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::i64, MVT::i32);
		break;
		case Intrinsic::hexagon_A2_combineii: // llvm.hexagon.A2.c
		ombineii
		case Intrinsic::hexagon_A2_combinew: // llvm.hexagon.A2.combinew
		case Intrinsic::hexagon_A4_combineir: // llvm.hexagon.A4.c
		ombineir
		case Intrinsic::hexagon_A4_combineri: // llvm.hexagon.A4.c
		ombineri
		case Intrinsic::hexagon_M2_cmpyi_s0: // llvm.hexagon.M2.cmpyi.s0
		case Intrinsic::hexagon_M2_cmpyr_s0: // llvm.hexagon.M2.cmpyr.s0
		case Intrinsic::hexagon_M2_cmpys_s0: // llvm.hexagon.M2.cmpys.s0
		case Intrinsic::hexagon_M2_cmpys_s1: // llvm.hexagon.M2.cmpys.s1
		case Intrinsic::hexagon_M2_cmpysc_s0: // llvm.hexagon.M2.c
		mpysc.s0
		case Intrinsic::hexagon_M2_cmpysc_s1: // llvm.hexagon.M2.c
		mpysc.s1
		case Intrinsic::hexagon_M2_dpmpyss_s0: // llvm.hexagon.M2.d
		pmpyss.s0
		case Intrinsic::hexagon_M2_dpmpyuu_s0: // llvm.hexagon.M2.d
		pmpyuu.s0
		case Intrinsic::hexagon_M2_mpyd_hh_s0: // llvm.hexagon.M2.m
		pyd.hh.s0
		case Intrinsic::hexagon_M2_mpyd_hh_s1: // llvm.hexagon.M2.m
		pyd.hh.s1
		case Intrinsic::hexagon_M2_mpyd_hl_s0: // llvm.hexagon.M2.m
		pyd.hl.s0
		case Intrinsic::hexagon_M2_mpyd_hl_s1: // llvm.hexagon.M2.m
		pyd.hl.s1
		case Intrinsic::hexagon_M2_mpyd_lh_s0: // llvm.hexagon.M2.m
		pyd.lh.s0
		case Intrinsic::hexagon_M2_mpyd_lh_s1: // llvm.hexagon.M2.m
		pyd.lh.s1
		case Intrinsic::hexagon_M2_mpyd_ll_s0: // llvm.hexagon.M2.m
		pyd.ll.s0
		case Intrinsic::hexagon_M2_mpyd_ll_s1: // llvm.hexagon.M2.m
		pyd.ll.s1
		case Intrinsic::hexagon_M2_mpyd_rnd_hh_s0: // llvm.hexagon.M2.m
		pyd.rnd.hh.s0
		case Intrinsic::hexagon_M2_mpyd_rnd_hh_s1: // llvm.hexagon.M2.m
		pyd.rnd.hh.s1
		case Intrinsic::hexagon_M2_mpyd_rnd_hl_s0: // llvm.hexagon.M2.m
		pyd.rnd.hl.s0
		case Intrinsic::hexagon_M2_mpyd_rnd_hl_s1: // llvm.hexagon.M2.m
		pyd.rnd.hl.s1
		case Intrinsic::hexagon_M2_mpyd_rnd_lh_s0: // llvm.hexagon.M2.m
		pyd.rnd.lh.s0
		case Intrinsic::hexagon_M2_mpyd_rnd_lh_s1: // llvm.hexagon.M2.m
		pyd.rnd.lh.s1
		case Intrinsic::hexagon_M2_mpyd_rnd_ll_s0: // llvm.hexagon.M2.m
		pyd.rnd.ll.s0
		case Intrinsic::hexagon_M2_mpyd_rnd_ll_s1: // llvm.hexagon.M2.m
		pyd.rnd.ll.s1
		case Intrinsic::hexagon_M2_mpyud_hh_s0: // llvm.hexagon.M2.m
		pyud.hh.s0
		case Intrinsic::hexagon_M2_mpyud_hh_s1: // llvm.hexagon.M2.m
		pyud.hh.s1
		case Intrinsic::hexagon_M2_mpyud_hl_s0: // llvm.hexagon.M2.m
		pyud.hl.s0
		case Intrinsic::hexagon_M2_mpyud_hl_s1: // llvm.hexagon.M2.m
		pyud.hl.s1
		case Intrinsic::hexagon_M2_mpyud_lh_s0: // llvm.hexagon.M2.m
		pyud.lh.s0
		case Intrinsic::hexagon_M2_mpyud_lh_s1: // llvm.hexagon.M2.m
		pyud.lh.s1
		case Intrinsic::hexagon_M2_mpyud_ll_s0: // llvm.hexagon.M2.m
		pyud.ll.s0
		case Intrinsic::hexagon_M2_mpyud_ll_s1: // llvm.hexagon.M2.m
		pyud.ll.s1
		case Intrinsic::hexagon_M2_vmpy2s_s0: // llvm.hexagon.M2.v
		mpy2s.s0
		case Intrinsic::hexagon_M2_vmpy2s_s1: // llvm.hexagon.M2.v
		mpy2s.s1
		case Intrinsic::hexagon_S2_packhl: // llvm.hexagon.S2.packhl
		VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::i64, MVT::i32, MVT::i32);
		break;
		case Intrinsic::hexagon_A2_addsp: // llvm.hexagon.A2.addsp
		VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::i64, MVT::i32, MVT::i64);
		break;
		case Intrinsic::hexagon_C2_vmux: // llvm.hexagon.C2.vmux
		VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::i64, MVT::i32, MVT::i64, MV
		T::i64);
		break;
		case Intrinsic::hexagon_A2_absp: // llvm.hexagon.A2.absp
		case Intrinsic::hexagon_A2_negp: // llvm.hexagon.A2.negp
		case Intrinsic::hexagon_A2_notp: // llvm.hexagon.A2.notp
		case Intrinsic::hexagon_A2_tfrp: // llvm.hexagon.A2.tfrp
		case Intrinsic::hexagon_A2_vabsh: // llvm.hexagon.A2.vabsh
		case Intrinsic::hexagon_A2_vabshsat: // llvm.hexagon.A2.vabshsat
		case Intrinsic::hexagon_A2_vabsw: // llvm.hexagon.A2.vabsw
		case Intrinsic::hexagon_A2_vabswsat: // llvm.hexagon.A2.vabswsat
		case Intrinsic::hexagon_A2_vconj: // llvm.hexagon.A2.vconj
		case Intrinsic::hexagon_S2_deinterleave: // llvm.hexagon.S2.d
		einterleave
		case Intrinsic::hexagon_S2_interleave: // llvm.hexagon.S2.i
		nterleave
		case Intrinsic::hexagon_S2_vsathb_nopack: // llvm.hexagon.S2.v
		sathb.nopack
		case Intrinsic::hexagon_S2_vsathub_nopack: // llvm.hexagon.S2.v
		sathub.nopack
		case Intrinsic::hexagon_S2_vsatwh_nopack: // llvm.hexagon.S2.v
		satwh.nopack
		case Intrinsic::hexagon_S2_vsatwuh_nopack: // llvm.hexagon.S2.v
		satwuh.nopack
		VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::i64, MVT::i64);
		break;
		case Intrinsic::hexagon_M2_vrcmpys_s1: // llvm.hexagon.M2.v
		rcmpys.s1
		case Intrinsic::hexagon_S2_asl_i_p: // llvm.hexagon.S2.asl.i.p
		case Intrinsic::hexagon_S2_asl_i_vh: // llvm.hexagon.S2.asl.i.vh
		case Intrinsic::hexagon_S2_asl_i_vw: // llvm.hexagon.S2.asl.i.vw
		case Intrinsic::hexagon_S2_asl_r_p: // llvm.hexagon.S2.asl.r.p
		case Intrinsic::hexagon_S2_asl_r_vh: // llvm.hexagon.S2.asl.r.vh
		case Intrinsic::hexagon_S2_asl_r_vw: // llvm.hexagon.S2.asl.r.vw
		case Intrinsic::hexagon_S2_asr_i_p: // llvm.hexagon.S2.asr.i.p
		case Intrinsic::hexagon_S2_asr_i_vh: // llvm.hexagon.S2.asr.i.vh
		case Intrinsic::hexagon_S2_asr_i_vw: // llvm.hexagon.S2.asr.i.vw
		case Intrinsic::hexagon_S2_asr_r_p: // llvm.hexagon.S2.asr.r.p
		case Intrinsic::hexagon_S2_asr_r_vh: // llvm.hexagon.S2.asr.r.vh
		case Intrinsic::hexagon_S2_asr_r_vw: // llvm.hexagon.S2.asr.r.vw
		case Intrinsic::hexagon_S2_lsl_r_p: // llvm.hexagon.S2.lsl.r.p
		case Intrinsic::hexagon_S2_lsl_r_vh: // llvm.hexagon.S2.lsl.r.vh
		case Intrinsic::hexagon_S2_lsl_r_vw: // llvm.hexagon.S2.lsl.r.vw
		case Intrinsic::hexagon_S2_lsr_i_p: // llvm.hexagon.S2.lsr.i.p
		case Intrinsic::hexagon_S2_lsr_i_vh: // llvm.hexagon.S2.lsr.i.vh
		case Intrinsic::hexagon_S2_lsr_i_vw: // llvm.hexagon.S2.lsr.i.vw
		case Intrinsic::hexagon_S2_lsr_r_p: // llvm.hexagon.S2.lsr.r.p
		case Intrinsic::hexagon_S2_lsr_r_vh: // llvm.hexagon.S2.lsr.r.vh
		case Intrinsic::hexagon_S2_lsr_r_vw: // llvm.hexagon.S2.lsr.r.vw
		case Intrinsic::hexagon_S2_vcrotate: // llvm.hexagon.S2.vcrotate
		VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::i64, MVT::i64, MVT::i32);
		break;
		case Intrinsic::hexagon_M2_cmaci_s0: // llvm.hexagon.M2.cmaci.s0
		case Intrinsic::hexagon_M2_cmacr_s0: // llvm.hexagon.M2.cmacr.s0
		case Intrinsic::hexagon_M2_cmacs_s0: // llvm.hexagon.M2.cmacs.s0
		case Intrinsic::hexagon_M2_cmacs_s1: // llvm.hexagon.M2.cmacs.s1
		case Intrinsic::hexagon_M2_cmacsc_s0: // llvm.hexagon.M2.c
		macsc.s0
		case Intrinsic::hexagon_M2_cmacsc_s1: // llvm.hexagon.M2.c
		macsc.s1
		case Intrinsic::hexagon_M2_cnacs_s0: // llvm.hexagon.M2.cnacs.s0
		case Intrinsic::hexagon_M2_cnacs_s1: // llvm.hexagon.M2.cnacs.s1
		case Intrinsic::hexagon_M2_cnacsc_s0: // llvm.hexagon.M2.c
		nacsc.s0
		case Intrinsic::hexagon_M2_cnacsc_s1: // llvm.hexagon.M2.c
		nacsc.s1
		case Intrinsic::hexagon_M2_dpmpyss_acc_s0: // llvm.hexagon.M2.d
		pmpyss.acc.s0
		case Intrinsic::hexagon_M2_dpmpyss_nac_s0: // llvm.hexagon.M2.d
		pmpyss.nac.s0
		case Intrinsic::hexagon_M2_dpmpyuu_acc_s0: // llvm.hexagon.M2.d
		pmpyuu.acc.s0
		case Intrinsic::hexagon_M2_dpmpyuu_nac_s0: // llvm.hexagon.M2.d
		pmpyuu.nac.s0
		case Intrinsic::hexagon_M2_mpyd_acc_hh_s0: // llvm.hexagon.M2.m
		pyd.acc.hh.s0
		case Intrinsic::hexagon_M2_mpyd_acc_hh_s1: // llvm.hexagon.M2.m
		pyd.acc.hh.s1
		case Intrinsic::hexagon_M2_mpyd_acc_hl_s0: // llvm.hexagon.M2.m
		pyd.acc.hl.s0
		case Intrinsic::hexagon_M2_mpyd_acc_hl_s1: // llvm.hexagon.M2.m
		pyd.acc.hl.s1
		case Intrinsic::hexagon_M2_mpyd_acc_lh_s0: // llvm.hexagon.M2.m
		pyd.acc.lh.s0
		case Intrinsic::hexagon_M2_mpyd_acc_lh_s1: // llvm.hexagon.M2.m
		pyd.acc.lh.s1
		case Intrinsic::hexagon_M2_mpyd_acc_ll_s0: // llvm.hexagon.M2.m
		pyd.acc.ll.s0
		case Intrinsic::hexagon_M2_mpyd_acc_ll_s1: // llvm.hexagon.M2.m
		pyd.acc.ll.s1
		case Intrinsic::hexagon_M2_mpyd_nac_hh_s0: // llvm.hexagon.M2.m
		pyd.nac.hh.s0
		case Intrinsic::hexagon_M2_mpyd_nac_hh_s1: // llvm.hexagon.M2.m
		pyd.nac.hh.s1
		case Intrinsic::hexagon_M2_mpyd_nac_hl_s0: // llvm.hexagon.M2.m
		pyd.nac.hl.s0
		case Intrinsic::hexagon_M2_mpyd_nac_hl_s1: // llvm.hexagon.M2.m
		pyd.nac.hl.s1
		case Intrinsic::hexagon_M2_mpyd_nac_lh_s0: // llvm.hexagon.M2.m
		pyd.nac.lh.s0
		case Intrinsic::hexagon_M2_mpyd_nac_lh_s1: // llvm.hexagon.M2.m
		pyd.nac.lh.s1
		case Intrinsic::hexagon_M2_mpyd_nac_ll_s0: // llvm.hexagon.M2.m
		pyd.nac.ll.s0
		case Intrinsic::hexagon_M2_mpyd_nac_ll_s1: // llvm.hexagon.M2.m
		pyd.nac.ll.s1
		case Intrinsic::hexagon_M2_mpyud_acc_hh_s0: // llvm.hexagon.M2.m
		pyud.acc.hh.s0
		case Intrinsic::hexagon_M2_mpyud_acc_hh_s1: // llvm.hexagon.M2.m
		pyud.acc.hh.s1
		case Intrinsic::hexagon_M2_mpyud_acc_hl_s0: // llvm.hexagon.M2.m
		pyud.acc.hl.s0
		case Intrinsic::hexagon_M2_mpyud_acc_hl_s1: // llvm.hexagon.M2.m
		pyud.acc.hl.s1
		case Intrinsic::hexagon_M2_mpyud_acc_lh_s0: // llvm.hexagon.M2.m
		pyud.acc.lh.s0
		case Intrinsic::hexagon_M2_mpyud_acc_lh_s1: // llvm.hexagon.M2.m
		pyud.acc.lh.s1
		case Intrinsic::hexagon_M2_mpyud_acc_ll_s0: // llvm.hexagon.M2.m
		pyud.acc.ll.s0
		case Intrinsic::hexagon_M2_mpyud_acc_ll_s1: // llvm.hexagon.M2.m
		pyud.acc.ll.s1
		case Intrinsic::hexagon_M2_mpyud_nac_hh_s0: // llvm.hexagon.M2.m
		pyud.nac.hh.s0
		case Intrinsic::hexagon_M2_mpyud_nac_hh_s1: // llvm.hexagon.M2.m
		pyud.nac.hh.s1
		case Intrinsic::hexagon_M2_mpyud_nac_hl_s0: // llvm.hexagon.M2.m
		pyud.nac.hl.s0
		case Intrinsic::hexagon_M2_mpyud_nac_hl_s1: // llvm.hexagon.M2.m
		pyud.nac.hl.s1
		case Intrinsic::hexagon_M2_mpyud_nac_lh_s0: // llvm.hexagon.M2.m
		pyud.nac.lh.s0
		case Intrinsic::hexagon_M2_mpyud_nac_lh_s1: // llvm.hexagon.M2.m
		pyud.nac.lh.s1
		case Intrinsic::hexagon_M2_mpyud_nac_ll_s0: // llvm.hexagon.M2.m
		pyud.nac.ll.s0
		case Intrinsic::hexagon_M2_mpyud_nac_ll_s1: // llvm.hexagon.M2.m
		pyud.nac.ll.s1
		case Intrinsic::hexagon_M2_vmac2: // llvm.hexagon.M2.vmac2
		case Intrinsic::hexagon_M2_vmac2s_s0: // llvm.hexagon.M2.v
		mac2s.s0
		case Intrinsic::hexagon_M2_vmac2s_s1: // llvm.hexagon.M2.v
		mac2s.s1
		case Intrinsic::hexagon_S2_extractup: // llvm.hexagon.S2.e
		xtractup
		VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::i64, MVT::i64, MVT::i32, MV
		T::i32);
		break;
		case Intrinsic::hexagon_A2_addp: // llvm.hexagon.A2.addp
		case Intrinsic::hexagon_A2_addpsat: // llvm.hexagon.A2.addpsat
		case Intrinsic::hexagon_A2_andp: // llvm.hexagon.A2.andp
		case Intrinsic::hexagon_A2_maxp: // llvm.hexagon.A2.maxp
		case Intrinsic::hexagon_A2_maxup: // llvm.hexagon.A2.maxup
		case Intrinsic::hexagon_A2_minp: // llvm.hexagon.A2.minp
		case Intrinsic::hexagon_A2_minup: // llvm.hexagon.A2.minup
		case Intrinsic::hexagon_A2_orp: // llvm.hexagon.A2.orp
		case Intrinsic::hexagon_A2_subp: // llvm.hexagon.A2.subp
		case Intrinsic::hexagon_A2_vaddh: // llvm.hexagon.A2.vaddh
		case Intrinsic::hexagon_A2_vaddhs: // llvm.hexagon.A2.vaddhs
		case Intrinsic::hexagon_A2_vaddub: // llvm.hexagon.A2.vaddub
		case Intrinsic::hexagon_A2_vaddubs: // llvm.hexagon.A2.vaddubs
		case Intrinsic::hexagon_A2_vadduhs: // llvm.hexagon.A2.vadduhs
		case Intrinsic::hexagon_A2_vaddw: // llvm.hexagon.A2.vaddw
		case Intrinsic::hexagon_A2_vaddws: // llvm.hexagon.A2.vaddws
		case Intrinsic::hexagon_A2_vavgh: // llvm.hexagon.A2.vavgh
		case Intrinsic::hexagon_A2_vavghcr: // llvm.hexagon.A2.vavghcr
		case Intrinsic::hexagon_A2_vavghr: // llvm.hexagon.A2.vavghr
		case Intrinsic::hexagon_A2_vavgub: // llvm.hexagon.A2.vavgub
		case Intrinsic::hexagon_A2_vavgubr: // llvm.hexagon.A2.vavgubr
		case Intrinsic::hexagon_A2_vavguh: // llvm.hexagon.A2.vavguh
		case Intrinsic::hexagon_A2_vavguhr: // llvm.hexagon.A2.vavguhr
		case Intrinsic::hexagon_A2_vavguw: // llvm.hexagon.A2.vavguw
		case Intrinsic::hexagon_A2_vavguwr: // llvm.hexagon.A2.vavguwr
		case Intrinsic::hexagon_A2_vavgw: // llvm.hexagon.A2.vavgw
		case Intrinsic::hexagon_A2_vavgwcr: // llvm.hexagon.A2.vavgwcr
		case Intrinsic::hexagon_A2_vavgwr: // llvm.hexagon.A2.vavgwr
		case Intrinsic::hexagon_A2_vmaxh: // llvm.hexagon.A2.vmaxh
		case Intrinsic::hexagon_A2_vmaxub: // llvm.hexagon.A2.vmaxub
		case Intrinsic::hexagon_A2_vmaxuh: // llvm.hexagon.A2.vmaxuh
		case Intrinsic::hexagon_A2_vmaxuw: // llvm.hexagon.A2.vmaxuw
		case Intrinsic::hexagon_A2_vmaxw: // llvm.hexagon.A2.vmaxw
		case Intrinsic::hexagon_A2_vminh: // llvm.hexagon.A2.vminh
		case Intrinsic::hexagon_A2_vminub: // llvm.hexagon.A2.vminub
		case Intrinsic::hexagon_A2_vminuh: // llvm.hexagon.A2.vminuh
		case Intrinsic::hexagon_A2_vminuw: // llvm.hexagon.A2.vminuw
		case Intrinsic::hexagon_A2_vminw: // llvm.hexagon.A2.vminw
		case Intrinsic::hexagon_A2_vnavgh: // llvm.hexagon.A2.vnavgh
		case Intrinsic::hexagon_A2_vnavghcr: // llvm.hexagon.A2.vnavghcr
		case Intrinsic::hexagon_A2_vnavghr: // llvm.hexagon.A2.vnavghr
		case Intrinsic::hexagon_A2_vnavgw: // llvm.hexagon.A2.vnavgw
		case Intrinsic::hexagon_A2_vnavgwcr: // llvm.hexagon.A2.vnavgwcr
		case Intrinsic::hexagon_A2_vnavgwr: // llvm.hexagon.A2.vnavgwr
		case Intrinsic::hexagon_A2_vraddub: // llvm.hexagon.A2.vraddub
		case Intrinsic::hexagon_A2_vrsadub: // llvm.hexagon.A2.vrsadub
		case Intrinsic::hexagon_A2_vsubh: // llvm.hexagon.A2.vsubh
		case Intrinsic::hexagon_A2_vsubhs: // llvm.hexagon.A2.vsubhs
		case Intrinsic::hexagon_A2_vsubub: // llvm.hexagon.A2.vsubub
		case Intrinsic::hexagon_A2_vsububs: // llvm.hexagon.A2.vsububs
		case Intrinsic::hexagon_A2_vsubuhs: // llvm.hexagon.A2.vsubuhs
		case Intrinsic::hexagon_A2_vsubw: // llvm.hexagon.A2.vsubw
		case Intrinsic::hexagon_A2_vsubws: // llvm.hexagon.A2.vsubws
		case Intrinsic::hexagon_A2_xorp: // llvm.hexagon.A2.xorp
		case Intrinsic::hexagon_A4_andnp: // llvm.hexagon.A4.andnp
		case Intrinsic::hexagon_A4_ornp: // llvm.hexagon.A4.ornp
		case Intrinsic::hexagon_M2_mmpyh_rs0: // llvm.hexagon.M2.m
		mpyh.rs0
		case Intrinsic::hexagon_M2_mmpyh_rs1: // llvm.hexagon.M2.m
		mpyh.rs1
		case Intrinsic::hexagon_M2_mmpyh_s0: // llvm.hexagon.M2.mmpyh.s0
		case Intrinsic::hexagon_M2_mmpyh_s1: // llvm.hexagon.M2.mmpyh.s1
		case Intrinsic::hexagon_M2_mmpyl_rs0: // llvm.hexagon.M2.m
		mpyl.rs0
		case Intrinsic::hexagon_M2_mmpyl_rs1: // llvm.hexagon.M2.m
		mpyl.rs1
		case Intrinsic::hexagon_M2_mmpyl_s0: // llvm.hexagon.M2.mmpyl.s0
		case Intrinsic::hexagon_M2_mmpyl_s1: // llvm.hexagon.M2.mmpyl.s1
		case Intrinsic::hexagon_M2_mmpyuh_rs0: // llvm.hexagon.M2.m
		mpyuh.rs0
		case Intrinsic::hexagon_M2_mmpyuh_rs1: // llvm.hexagon.M2.m
		mpyuh.rs1
		case Intrinsic::hexagon_M2_mmpyuh_s0: // llvm.hexagon.M2.m
		mpyuh.s0
		case Intrinsic::hexagon_M2_mmpyuh_s1: // llvm.hexagon.M2.m
		mpyuh.s1
		case Intrinsic::hexagon_M2_mmpyul_rs0: // llvm.hexagon.M2.m
		mpyul.rs0
		case Intrinsic::hexagon_M2_mmpyul_rs1: // llvm.hexagon.M2.m
		mpyul.rs1
		case Intrinsic::hexagon_M2_mmpyul_s0: // llvm.hexagon.M2.m
		mpyul.s0
		case Intrinsic::hexagon_M2_mmpyul_s1: // llvm.hexagon.M2.m
		mpyul.s1
		case Intrinsic::hexagon_M2_vabsdiffh: // llvm.hexagon.M2.v
		absdiffh
		case Intrinsic::hexagon_M2_vabsdiffw: // llvm.hexagon.M2.v
		absdiffw
		case Intrinsic::hexagon_M2_vcmpy_s0_sat_i: // llvm.hexagon.M2.v
		cmpy.s0.sat.i
		case Intrinsic::hexagon_M2_vcmpy_s0_sat_r: // llvm.hexagon.M2.v
		cmpy.s0.sat.r
		case Intrinsic::hexagon_M2_vcmpy_s1_sat_i: // llvm.hexagon.M2.v
		cmpy.s1.sat.i
		case Intrinsic::hexagon_M2_vcmpy_s1_sat_r: // llvm.hexagon.M2.v
		cmpy.s1.sat.r
		case Intrinsic::hexagon_M2_vdmpys_s0: // llvm.hexagon.M2.v
		dmpys.s0
		case Intrinsic::hexagon_M2_vdmpys_s1: // llvm.hexagon.M2.v
		dmpys.s1
		case Intrinsic::hexagon_M2_vmpy2es_s0: // llvm.hexagon.M2.v
		mpy2es.s0
		case Intrinsic::hexagon_M2_vmpy2es_s1: // llvm.hexagon.M2.v
		mpy2es.s1
		case Intrinsic::hexagon_M2_vrcmpyi_s0: // llvm.hexagon.M2.v
		rcmpyi.s0
		case Intrinsic::hexagon_M2_vrcmpyi_s0c: // llvm.hexagon.M2.v
		rcmpyi.s0c
		case Intrinsic::hexagon_M2_vrcmpyr_s0: // llvm.hexagon.M2.v
		rcmpyr.s0
		case Intrinsic::hexagon_M2_vrcmpyr_s0c: // llvm.hexagon.M2.v
		rcmpyr.s0c
		case Intrinsic::hexagon_M2_vrmpy_s0: // llvm.hexagon.M2.vrmpy.s0
		case Intrinsic::hexagon_S2_extractup_rp: // llvm.hexagon.S2.e
		xtractup.rp
		case Intrinsic::hexagon_S2_lfsp: // llvm.hexagon.S2.lfsp
		case Intrinsic::hexagon_S2_shuffeb: // llvm.hexagon.S2.shuffeb
		case Intrinsic::hexagon_S2_shuffeh: // llvm.hexagon.S2.shuffeh
		case Intrinsic::hexagon_S2_shuffob: // llvm.hexagon.S2.shuffob
		case Intrinsic::hexagon_S2_shuffoh: // llvm.hexagon.S2.shuffoh
		case Intrinsic::hexagon_S2_vtrunewh: // llvm.hexagon.S2.vtrunewh
		case Intrinsic::hexagon_S2_vtrunowh: // llvm.hexagon.S2.vtrunowh
		case Intrinsic::hexagon_S4_andnp: // llvm.hexagon.S4.andnp
		case Intrinsic::hexagon_S4_ornp: // llvm.hexagon.S4.ornp
		case Intrinsic::x86_bmi_bextr_64: // llvm.x86.bmi.bextr.64
		case Intrinsic::x86_bmi_bzhi_64: // llvm.x86.bmi.bzhi.64
		case Intrinsic::x86_bmi_pdep_64: // llvm.x86.bmi.pdep.64
		case Intrinsic::x86_bmi_pext_64: // llvm.x86.bmi.pext.64
	case Intrinsic::x86_sse42_crc32_64_64: // llvm.x86.sse42.cr c32.64.64	case Intrinsic::x86_sse42_crc32_64_64: // llvm.x86.sse42.cr c32.64.64
	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::i64, MVT::i64, MVT::i64);	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::i64, MVT::i64, MVT::i64);
	break;	break;

		case Intrinsic::hexagon_M2_vrcmpys_acc_s1: // llvm.hexagon.M2.v
		rcmpys.acc.s1
		case Intrinsic::hexagon_S2_asl_i_p_acc: // llvm.hexagon.S2.a
		sl.i.p.acc
		case Intrinsic::hexagon_S2_asl_i_p_and: // llvm.hexagon.S2.a
		sl.i.p.and
		case Intrinsic::hexagon_S2_asl_i_p_nac: // llvm.hexagon.S2.a
		sl.i.p.nac
		case Intrinsic::hexagon_S2_asl_i_p_or: // llvm.hexagon.S2.a
		sl.i.p.or
		case Intrinsic::hexagon_S2_asl_i_p_xacc: // llvm.hexagon.S2.a
		sl.i.p.xacc
		case Intrinsic::hexagon_S2_asl_r_p_acc: // llvm.hexagon.S2.a
		sl.r.p.acc
		case Intrinsic::hexagon_S2_asl_r_p_and: // llvm.hexagon.S2.a
		sl.r.p.and
		case Intrinsic::hexagon_S2_asl_r_p_nac: // llvm.hexagon.S2.a
		sl.r.p.nac
		case Intrinsic::hexagon_S2_asl_r_p_or: // llvm.hexagon.S2.a
		sl.r.p.or
		case Intrinsic::hexagon_S2_asr_i_p_acc: // llvm.hexagon.S2.a
		sr.i.p.acc
		case Intrinsic::hexagon_S2_asr_i_p_and: // llvm.hexagon.S2.a
		sr.i.p.and
		case Intrinsic::hexagon_S2_asr_i_p_nac: // llvm.hexagon.S2.a
		sr.i.p.nac
		case Intrinsic::hexagon_S2_asr_i_p_or: // llvm.hexagon.S2.a
		sr.i.p.or
		case Intrinsic::hexagon_S2_asr_r_p_acc: // llvm.hexagon.S2.a
		sr.r.p.acc
		case Intrinsic::hexagon_S2_asr_r_p_and: // llvm.hexagon.S2.a
		sr.r.p.and
		case Intrinsic::hexagon_S2_asr_r_p_nac: // llvm.hexagon.S2.a
		sr.r.p.nac
		case Intrinsic::hexagon_S2_asr_r_p_or: // llvm.hexagon.S2.a
		sr.r.p.or
		case Intrinsic::hexagon_S2_lsl_r_p_acc: // llvm.hexagon.S2.l
		sl.r.p.acc
		case Intrinsic::hexagon_S2_lsl_r_p_and: // llvm.hexagon.S2.l
		sl.r.p.and
		case Intrinsic::hexagon_S2_lsl_r_p_nac: // llvm.hexagon.S2.l
		sl.r.p.nac
		case Intrinsic::hexagon_S2_lsl_r_p_or: // llvm.hexagon.S2.l
		sl.r.p.or
		case Intrinsic::hexagon_S2_lsr_i_p_acc: // llvm.hexagon.S2.l
		sr.i.p.acc
		case Intrinsic::hexagon_S2_lsr_i_p_and: // llvm.hexagon.S2.l
		sr.i.p.and
		case Intrinsic::hexagon_S2_lsr_i_p_nac: // llvm.hexagon.S2.l
		sr.i.p.nac
		case Intrinsic::hexagon_S2_lsr_i_p_or: // llvm.hexagon.S2.l
		sr.i.p.or
		case Intrinsic::hexagon_S2_lsr_i_p_xacc: // llvm.hexagon.S2.l
		sr.i.p.xacc
		case Intrinsic::hexagon_S2_lsr_r_p_acc: // llvm.hexagon.S2.l
		sr.r.p.acc
		case Intrinsic::hexagon_S2_lsr_r_p_and: // llvm.hexagon.S2.l
		sr.r.p.and
		case Intrinsic::hexagon_S2_lsr_r_p_nac: // llvm.hexagon.S2.l
		sr.r.p.nac
		case Intrinsic::hexagon_S2_lsr_r_p_or: // llvm.hexagon.S2.l
		sr.r.p.or
		case Intrinsic::hexagon_S2_valignib: // llvm.hexagon.S2.valignib
		case Intrinsic::hexagon_S2_valignrb: // llvm.hexagon.S2.valignrb
		case Intrinsic::hexagon_S2_vspliceib: // llvm.hexagon.S2.v
		spliceib
		case Intrinsic::hexagon_S2_vsplicerb: // llvm.hexagon.S2.v
		splicerb
		VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::i64, MVT::i64, MVT::i64, MV
		T::i32);
		break;
		case Intrinsic::hexagon_S2_insertp: // llvm.hexagon.S2.insertp
		VerifyIntrinsicPrototype(ID, IF, 1, 4, MVT::i64, MVT::i64, MVT::i64, MV
		T::i32, MVT::i32);
		break;
		case Intrinsic::hexagon_A2_vraddub_acc: // llvm.hexagon.A2.v
		raddub.acc
		case Intrinsic::hexagon_A2_vrsadub_acc: // llvm.hexagon.A2.v
		rsadub.acc
		case Intrinsic::hexagon_M2_mmachs_rs0: // llvm.hexagon.M2.m
		machs.rs0
		case Intrinsic::hexagon_M2_mmachs_rs1: // llvm.hexagon.M2.m
		machs.rs1
		case Intrinsic::hexagon_M2_mmachs_s0: // llvm.hexagon.M2.m
		machs.s0
		case Intrinsic::hexagon_M2_mmachs_s1: // llvm.hexagon.M2.m
		machs.s1
		case Intrinsic::hexagon_M2_mmacls_rs0: // llvm.hexagon.M2.m
		macls.rs0
		case Intrinsic::hexagon_M2_mmacls_rs1: // llvm.hexagon.M2.m
		macls.rs1
		case Intrinsic::hexagon_M2_mmacls_s0: // llvm.hexagon.M2.m
		macls.s0
		case Intrinsic::hexagon_M2_mmacls_s1: // llvm.hexagon.M2.m
		macls.s1
		case Intrinsic::hexagon_M2_mmacuhs_rs0: // llvm.hexagon.M2.m
		macuhs.rs0
		case Intrinsic::hexagon_M2_mmacuhs_rs1: // llvm.hexagon.M2.m
		macuhs.rs1
		case Intrinsic::hexagon_M2_mmacuhs_s0: // llvm.hexagon.M2.m
		macuhs.s0
		case Intrinsic::hexagon_M2_mmacuhs_s1: // llvm.hexagon.M2.m
		macuhs.s1
		case Intrinsic::hexagon_M2_mmaculs_rs0: // llvm.hexagon.M2.m
		maculs.rs0
		case Intrinsic::hexagon_M2_mmaculs_rs1: // llvm.hexagon.M2.m
		maculs.rs1
		case Intrinsic::hexagon_M2_mmaculs_s0: // llvm.hexagon.M2.m
		maculs.s0
		case Intrinsic::hexagon_M2_mmaculs_s1: // llvm.hexagon.M2.m
		maculs.s1
		case Intrinsic::hexagon_M2_vcmac_s0_sat_i: // llvm.hexagon.M2.v
		cmac.s0.sat.i
		case Intrinsic::hexagon_M2_vcmac_s0_sat_r: // llvm.hexagon.M2.v
		cmac.s0.sat.r
		case Intrinsic::hexagon_M2_vdmacs_s0: // llvm.hexagon.M2.v
		dmacs.s0
		case Intrinsic::hexagon_M2_vdmacs_s1: // llvm.hexagon.M2.v
		dmacs.s1
		case Intrinsic::hexagon_M2_vmac2es: // llvm.hexagon.M2.vmac2es
		case Intrinsic::hexagon_M2_vmac2es_s0: // llvm.hexagon.M2.v
		mac2es.s0
		case Intrinsic::hexagon_M2_vmac2es_s1: // llvm.hexagon.M2.v
		mac2es.s1
		case Intrinsic::hexagon_M2_vrcmaci_s0: // llvm.hexagon.M2.v
		rcmaci.s0
		case Intrinsic::hexagon_M2_vrcmaci_s0c: // llvm.hexagon.M2.v
		rcmaci.s0c
		case Intrinsic::hexagon_M2_vrcmacr_s0: // llvm.hexagon.M2.v
		rcmacr.s0
		case Intrinsic::hexagon_M2_vrcmacr_s0c: // llvm.hexagon.M2.v
		rcmacr.s0c
		case Intrinsic::hexagon_M2_vrmac_s0: // llvm.hexagon.M2.vrmac.s0
		case Intrinsic::hexagon_M4_xor_xacc: // llvm.hexagon.M4.xor.xacc
		case Intrinsic::hexagon_S2_insertp_rp: // llvm.hexagon.S2.i
		nsertp.rp
		VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::i64, MVT::i64, MVT::i64, MV
		T::i64);
		break;
	case Intrinsic::x86_sse42_crc32_64_8: // llvm.x86.sse42.cr c32.64.8	case Intrinsic::x86_sse42_crc32_64_8: // llvm.x86.sse42.cr c32.64.8
	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::i64, MVT::i64, MVT::i8);	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::i64, MVT::i64, MVT::i8);
	break;	break;
	case Intrinsic::x86_sse2_cvtsd2si64: // llvm.x86.sse2.cvtsd2si64	case Intrinsic::x86_sse2_cvtsd2si64: // llvm.x86.sse2.cvtsd2si64
	case Intrinsic::x86_sse2_cvttsd2si64: // llvm.x86.sse2.cvt tsd2si64	case Intrinsic::x86_sse2_cvttsd2si64: // llvm.x86.sse2.cvt tsd2si64
	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::i64, MVT::v2f64);	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::i64, MVT::v2f64);
	break;	break;
	case Intrinsic::x86_sse41_pextrq: // llvm.x86.sse41.pextrq	case Intrinsic::x86_sse41_pextrq: // llvm.x86.sse41.pextrq
	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::i64, MVT::v2i64, MVT::i32);	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::i64, MVT::v2i64, MVT::i32);
	break;	break;
	case Intrinsic::x86_sse_cvtss2si64: // llvm.x86.sse.cvtss2si64	case Intrinsic::x86_sse_cvtss2si64: // llvm.x86.sse.cvtss2si64
	case Intrinsic::x86_sse_cvttss2si64: // llvm.x86.sse.cvttss2si64	case Intrinsic::x86_sse_cvttss2si64: // llvm.x86.sse.cvttss2si64
	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::i64, MVT::v4f32);	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::i64, MVT::v4f32);
	break;	break;
	case Intrinsic::arm_thread_pointer: // llvm.arm.thread.pointer	case Intrinsic::arm_thread_pointer: // llvm.arm.thread.pointer

	case Intrinsic::eh_exception: // llvm.eh.exception
	case Intrinsic::eh_sjlj_lsda: // llvm.eh.sjlj.lsda	case Intrinsic::eh_sjlj_lsda: // llvm.eh.sjlj.lsda
	case Intrinsic::stacksave: // llvm.stacksave	case Intrinsic::stacksave: // llvm.stacksave
	case Intrinsic::xcore_waitevent: // llvm.xcore.waitevent	case Intrinsic::xcore_waitevent: // llvm.xcore.waitevent
	VerifyIntrinsicPrototype(ID, IF, 1, 0, MVT::iPTR);	VerifyIntrinsicPrototype(ID, IF, 1, 0, MVT::iPTR);
	break;	break;
	case Intrinsic::eh_dwarf_cfa: // llvm.eh.dwarf.cfa	case Intrinsic::eh_dwarf_cfa: // llvm.eh.dwarf.cfa
	case Intrinsic::frameaddress: // llvm.frameaddress	case Intrinsic::frameaddress: // llvm.frameaddress
	case Intrinsic::returnaddress: // llvm.returnaddress	case Intrinsic::returnaddress: // llvm.returnaddress
	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::iPTR, MVT::i32);	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::iPTR, MVT::i32);
	break;	break;
	case Intrinsic::adjust_trampoline: // llvm.adjust.trampoline	case Intrinsic::adjust_trampoline: // llvm.adjust.trampoline
	case Intrinsic::xcore_checkevent: // llvm.xcore.checkevent	case Intrinsic::xcore_checkevent: // llvm.xcore.checkevent
	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::iPTR, MVT::iPTR);	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::iPTR, MVT::iPTR);
	break;	break;
	case Intrinsic::gcread: // llvm.gcread	case Intrinsic::gcread: // llvm.gcread
	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::iPTR, MVT::iPTR, MVT::iPTR) ;	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::iPTR, MVT::iPTR, MVT::iPTR) ;
	break;	break;

		case Intrinsic::x86_avx2_pabs_w: // llvm.x86.avx2.pabs.w
		VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v16i16, MVT::v16i16);
		break;
		case Intrinsic::x86_avx2_pslli_w: // llvm.x86.avx2.pslli.w
		case Intrinsic::x86_avx2_psrai_w: // llvm.x86.avx2.psrai.w
		case Intrinsic::x86_avx2_psrli_w: // llvm.x86.avx2.psrli.w
		VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v16i16, MVT::v16i16, MVT::i
		32);
		break;
		case Intrinsic::x86_avx2_padds_w: // llvm.x86.avx2.padds.w
		case Intrinsic::x86_avx2_paddus_w: // llvm.x86.avx2.paddus.w
		case Intrinsic::x86_avx2_pavg_w: // llvm.x86.avx2.pavg.w
		case Intrinsic::x86_avx2_phadd_sw: // llvm.x86.avx2.phadd.sw
		case Intrinsic::x86_avx2_phadd_w: // llvm.x86.avx2.phadd.w
		case Intrinsic::x86_avx2_phsub_sw: // llvm.x86.avx2.phsub.sw
		case Intrinsic::x86_avx2_phsub_w: // llvm.x86.avx2.phsub.w
		case Intrinsic::x86_avx2_pmaxs_w: // llvm.x86.avx2.pmaxs.w
		case Intrinsic::x86_avx2_pmaxu_w: // llvm.x86.avx2.pmaxu.w
		case Intrinsic::x86_avx2_pmins_w: // llvm.x86.avx2.pmins.w
		case Intrinsic::x86_avx2_pminu_w: // llvm.x86.avx2.pminu.w
		case Intrinsic::x86_avx2_pmul_hr_sw: // llvm.x86.avx2.pmul.hr.sw
		case Intrinsic::x86_avx2_pmulh_w: // llvm.x86.avx2.pmulh.w
		case Intrinsic::x86_avx2_pmulhu_w: // llvm.x86.avx2.pmulhu.w
		case Intrinsic::x86_avx2_psign_w: // llvm.x86.avx2.psign.w
		case Intrinsic::x86_avx2_psubs_w: // llvm.x86.avx2.psubs.w
		case Intrinsic::x86_avx2_psubus_w: // llvm.x86.avx2.psubus.w
		VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v16i16, MVT::v16i16, MVT::v
		16i16);
		break;
		case Intrinsic::x86_avx2_pblendw: // llvm.x86.avx2.pblendw
		VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v16i16, MVT::v16i16, MVT::v
		16i16, MVT::i32);
		break;
		case Intrinsic::x86_avx2_psll_w: // llvm.x86.avx2.psll.w
		case Intrinsic::x86_avx2_psra_w: // llvm.x86.avx2.psra.w
		case Intrinsic::x86_avx2_psrl_w: // llvm.x86.avx2.psrl.w
		VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v16i16, MVT::v16i16, MVT::v
		8i16);
		break;
		case Intrinsic::x86_avx2_pmovsxbw: // llvm.x86.avx2.pmovsxbw
		case Intrinsic::x86_avx2_pmovzxbw: // llvm.x86.avx2.pmovzxbw
		VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v16i16, MVT::v16i8);
		break;
		case Intrinsic::x86_avx2_pmadd_ub_sw: // llvm.x86.avx2.pma
		dd.ub.sw
		VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v16i16, MVT::v32i8, MVT::v3
		2i8);
		break;
		case Intrinsic::x86_avx2_mpsadbw: // llvm.x86.avx2.mpsadbw
		VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v16i16, MVT::v32i8, MVT::v3
		2i8, MVT::i32);
		break;
		case Intrinsic::x86_avx2_pbroadcastw_256: // llvm.x86.avx2.pbr
		oadcastw.256
		VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v16i16, MVT::v8i16);
		break;
		case Intrinsic::x86_avx2_packssdw: // llvm.x86.avx2.packssdw
		case Intrinsic::x86_avx2_packusdw: // llvm.x86.avx2.packusdw
		VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v16i16, MVT::v8i32, MVT::v8
		i32);
		break;
	case Intrinsic::ppc_altivec_lvebx: // llvm.ppc.altivec.lvebx	case Intrinsic::ppc_altivec_lvebx: // llvm.ppc.altivec.lvebx
	case Intrinsic::ppc_altivec_lvsl: // llvm.ppc.altivec.lvsl	case Intrinsic::ppc_altivec_lvsl: // llvm.ppc.altivec.lvsl
	case Intrinsic::ppc_altivec_lvsr: // llvm.ppc.altivec.lvsr	case Intrinsic::ppc_altivec_lvsr: // llvm.ppc.altivec.lvsr
	case Intrinsic::x86_sse3_ldu_dq: // llvm.x86.sse3.ldu.dq	case Intrinsic::x86_sse3_ldu_dq: // llvm.x86.sse3.ldu.dq
	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v16i8, MVT::iPTR);	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v16i8, MVT::iPTR);
	break;	break;

		case Intrinsic::x86_avx2_pbroadcastb_128: // llvm.x86.avx2.pbr oadcastb.128
	case Intrinsic::x86_ssse3_pabs_b_128: // llvm.x86.ssse3.pa bs.b.128	case Intrinsic::x86_ssse3_pabs_b_128: // llvm.x86.ssse3.pa bs.b.128
	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v16i8, MVT::v16i8);	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v16i8, MVT::v16i8);
	break;	break;
	case Intrinsic::spu_si_shlqbii: // llvm.spu.si.shlqbii	case Intrinsic::spu_si_shlqbii: // llvm.spu.si.shlqbii
	case Intrinsic::spu_si_shlqbyi: // llvm.spu.si.shlqbyi	case Intrinsic::spu_si_shlqbyi: // llvm.spu.si.shlqbyi
	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v16i8, MVT::v16i8, MVT::i8) ;	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v16i8, MVT::v16i8, MVT::i8) ;
	break;	break;
	case Intrinsic::x86_sse42_pcmpestrm128: // llvm.x86.sse42.pc mpestrm128	case Intrinsic::x86_sse42_pcmpestrm128: // llvm.x86.sse42.pc mpestrm128
	VerifyIntrinsicPrototype(ID, IF, 1, 5, MVT::v16i8, MVT::v16i8, MVT::i32 , MVT::v16i8, MVT::i32, MVT::i8);	VerifyIntrinsicPrototype(ID, IF, 1, 5, MVT::v16i8, MVT::v16i8, MVT::i32 , MVT::v16i8, MVT::i32, MVT::i8);
	break;	break;

	skipping to change at line 9632	skipping to change at line 18629
	case Intrinsic::ppc_altivec_vsrab: // llvm.ppc.altivec.vsrab	case Intrinsic::ppc_altivec_vsrab: // llvm.ppc.altivec.vsrab
	case Intrinsic::ppc_altivec_vsrb: // llvm.ppc.altivec.vsrb	case Intrinsic::ppc_altivec_vsrb: // llvm.ppc.altivec.vsrb
	case Intrinsic::ppc_altivec_vsubsbs: // llvm.ppc.altivec.vsubsbs	case Intrinsic::ppc_altivec_vsubsbs: // llvm.ppc.altivec.vsubsbs
	case Intrinsic::ppc_altivec_vsububs: // llvm.ppc.altivec.vsububs	case Intrinsic::ppc_altivec_vsububs: // llvm.ppc.altivec.vsububs
	case Intrinsic::spu_si_ceqb: // llvm.spu.si.ceqb	case Intrinsic::spu_si_ceqb: // llvm.spu.si.ceqb
	case Intrinsic::spu_si_cgtb: // llvm.spu.si.cgtb	case Intrinsic::spu_si_cgtb: // llvm.spu.si.cgtb
	case Intrinsic::spu_si_clgtb: // llvm.spu.si.clgtb	case Intrinsic::spu_si_clgtb: // llvm.spu.si.clgtb
	case Intrinsic::x86_sse2_padds_b: // llvm.x86.sse2.padds.b	case Intrinsic::x86_sse2_padds_b: // llvm.x86.sse2.padds.b
	case Intrinsic::x86_sse2_paddus_b: // llvm.x86.sse2.paddus.b	case Intrinsic::x86_sse2_paddus_b: // llvm.x86.sse2.paddus.b
	case Intrinsic::x86_sse2_pavg_b: // llvm.x86.sse2.pavg.b	case Intrinsic::x86_sse2_pavg_b: // llvm.x86.sse2.pavg.b

	case Intrinsic::x86_sse2_pcmpeq_b: // llvm.x86.sse2.pcmpeq.b
	case Intrinsic::x86_sse2_pcmpgt_b: // llvm.x86.sse2.pcmpgt.b
	case Intrinsic::x86_sse2_pmaxu_b: // llvm.x86.sse2.pmaxu.b	case Intrinsic::x86_sse2_pmaxu_b: // llvm.x86.sse2.pmaxu.b
	case Intrinsic::x86_sse2_pminu_b: // llvm.x86.sse2.pminu.b	case Intrinsic::x86_sse2_pminu_b: // llvm.x86.sse2.pminu.b
	case Intrinsic::x86_sse2_psubs_b: // llvm.x86.sse2.psubs.b	case Intrinsic::x86_sse2_psubs_b: // llvm.x86.sse2.psubs.b
	case Intrinsic::x86_sse2_psubus_b: // llvm.x86.sse2.psubus.b	case Intrinsic::x86_sse2_psubus_b: // llvm.x86.sse2.psubus.b
	case Intrinsic::x86_sse41_pmaxsb: // llvm.x86.sse41.pmaxsb	case Intrinsic::x86_sse41_pmaxsb: // llvm.x86.sse41.pmaxsb
	case Intrinsic::x86_sse41_pminsb: // llvm.x86.sse41.pminsb	case Intrinsic::x86_sse41_pminsb: // llvm.x86.sse41.pminsb
	case Intrinsic::x86_ssse3_pshuf_b_128: // llvm.x86.ssse3.ps huf.b.128	case Intrinsic::x86_ssse3_pshuf_b_128: // llvm.x86.ssse3.ps huf.b.128
	case Intrinsic::x86_ssse3_psign_b_128: // llvm.x86.ssse3.ps ign.b.128	case Intrinsic::x86_ssse3_psign_b_128: // llvm.x86.ssse3.ps ign.b.128

		case Intrinsic::x86_xop_vpcomeqb: // llvm.x86.xop.vpcomeqb
		case Intrinsic::x86_xop_vpcomequb: // llvm.x86.xop.vpcomequb
		case Intrinsic::x86_xop_vpcomfalseb: // llvm.x86.xop.vpcomfalseb
		case Intrinsic::x86_xop_vpcomfalseub: // llvm.x86.xop.vpco
		mfalseub
		case Intrinsic::x86_xop_vpcomgeb: // llvm.x86.xop.vpcomgeb
		case Intrinsic::x86_xop_vpcomgeub: // llvm.x86.xop.vpcomgeub
		case Intrinsic::x86_xop_vpcomgtb: // llvm.x86.xop.vpcomgtb
		case Intrinsic::x86_xop_vpcomgtub: // llvm.x86.xop.vpcomgtub
		case Intrinsic::x86_xop_vpcomleb: // llvm.x86.xop.vpcomleb
		case Intrinsic::x86_xop_vpcomleub: // llvm.x86.xop.vpcomleub
		case Intrinsic::x86_xop_vpcomltb: // llvm.x86.xop.vpcomltb
		case Intrinsic::x86_xop_vpcomltub: // llvm.x86.xop.vpcomltub
		case Intrinsic::x86_xop_vpcomneb: // llvm.x86.xop.vpcomneb
		case Intrinsic::x86_xop_vpcomneub: // llvm.x86.xop.vpcomneub
		case Intrinsic::x86_xop_vpcomtrueb: // llvm.x86.xop.vpcomtrueb
		case Intrinsic::x86_xop_vpcomtrueub: // llvm.x86.xop.vpcomtrueub
		case Intrinsic::x86_xop_vprotb: // llvm.x86.xop.vprotb
		case Intrinsic::x86_xop_vpshab: // llvm.x86.xop.vpshab
		case Intrinsic::x86_xop_vpshlb: // llvm.x86.xop.vpshlb
	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v16i8, MVT::v16i8, MVT::v16 i8);	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v16i8, MVT::v16i8, MVT::v16 i8);
	break;	break;

	case Intrinsic::x86_sse41_mpsadbw: // llvm.x86.sse41.mpsadbw
	VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v16i8, MVT::v16i8, MVT::v16
	i8, MVT::i32);
	break;
	case Intrinsic::x86_sse42_pcmpistrm128: // llvm.x86.sse42.pc mpistrm128	case Intrinsic::x86_sse42_pcmpistrm128: // llvm.x86.sse42.pc mpistrm128
	VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v16i8, MVT::v16i8, MVT::v16 i8, MVT::i8);	VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v16i8, MVT::v16i8, MVT::v16 i8, MVT::i8);
	break;	break;
	case Intrinsic::x86_sse41_pblendvb: // llvm.x86.sse41.pblendvb	case Intrinsic::x86_sse41_pblendvb: // llvm.x86.sse41.pblendvb

		case Intrinsic::x86_xop_vpperm: // llvm.x86.xop.vpperm
	VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v16i8, MVT::v16i8, MVT::v16 i8, MVT::v16i8);	VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v16i8, MVT::v16i8, MVT::v16 i8, MVT::v16i8);
	break;	break;
	case Intrinsic::ppc_altivec_vpkswss: // llvm.ppc.altivec.vpkswss	case Intrinsic::ppc_altivec_vpkswss: // llvm.ppc.altivec.vpkswss
	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v16i8, MVT::v4i32, MVT::v4i 32);	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v16i8, MVT::v4i32, MVT::v4i 32);
	break;	break;
	case Intrinsic::ppc_altivec_vpkshss: // llvm.ppc.altivec.vpkshss	case Intrinsic::ppc_altivec_vpkshss: // llvm.ppc.altivec.vpkshss
	case Intrinsic::ppc_altivec_vpkshus: // llvm.ppc.altivec.vpkshus	case Intrinsic::ppc_altivec_vpkshus: // llvm.ppc.altivec.vpkshus
	case Intrinsic::ppc_altivec_vpkuhus: // llvm.ppc.altivec.vpkuhus	case Intrinsic::ppc_altivec_vpkuhus: // llvm.ppc.altivec.vpkuhus
	case Intrinsic::x86_sse2_packsswb_128: // llvm.x86.sse2.pac ksswb.128	case Intrinsic::x86_sse2_packsswb_128: // llvm.x86.sse2.pac ksswb.128
	case Intrinsic::x86_sse2_packuswb_128: // llvm.x86.sse2.pac kuswb.128	case Intrinsic::x86_sse2_packuswb_128: // llvm.x86.sse2.pac kuswb.128
	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v16i8, MVT::v8i16, MVT::v8i 16);	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v16i8, MVT::v8i16, MVT::v8i 16);
	break;	break;
	case Intrinsic::x86_avx_maskload_pd: // llvm.x86.avx.maskload.pd	case Intrinsic::x86_avx_maskload_pd: // llvm.x86.avx.maskload.pd
	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v2f64, MVT::iPTR, MVT::v2f6 4);	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v2f64, MVT::iPTR, MVT::v2f6 4);
	break;	break;
	case Intrinsic::x86_sse2_sqrt_pd: // llvm.x86.sse2.sqrt.pd	case Intrinsic::x86_sse2_sqrt_pd: // llvm.x86.sse2.sqrt.pd
	case Intrinsic::x86_sse2_sqrt_sd: // llvm.x86.sse2.sqrt.sd	case Intrinsic::x86_sse2_sqrt_sd: // llvm.x86.sse2.sqrt.sd

		case Intrinsic::x86_xop_vfrcz_pd: // llvm.x86.xop.vfrcz.pd
	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v2f64, MVT::v2f64);	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v2f64, MVT::v2f64);
	break;	break;
	case Intrinsic::x86_sse2_cvtsi2sd: // llvm.x86.sse2.cvtsi2sd	case Intrinsic::x86_sse2_cvtsi2sd: // llvm.x86.sse2.cvtsi2sd
	case Intrinsic::x86_sse41_round_pd: // llvm.x86.sse41.round.pd	case Intrinsic::x86_sse41_round_pd: // llvm.x86.sse41.round.pd
	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v2f64, MVT::v2f64, MVT::i32 );	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v2f64, MVT::v2f64, MVT::i32 );
	break;	break;
	case Intrinsic::x86_sse2_cvtsi642sd: // llvm.x86.sse2.cvtsi642sd	case Intrinsic::x86_sse2_cvtsi642sd: // llvm.x86.sse2.cvtsi642sd
	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v2f64, MVT::v2f64, MVT::i64 );	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v2f64, MVT::v2f64, MVT::i64 );
	break;	break;

	case Intrinsic::x86_avx_vpermil_pd: // llvm.x86.avx.vpermil.pd
	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v2f64, MVT::v2f64, MVT::i8)
	;
	break;
	case Intrinsic::spu_si_dfa: // llvm.spu.si.dfa	case Intrinsic::spu_si_dfa: // llvm.spu.si.dfa
	case Intrinsic::spu_si_dfm: // llvm.spu.si.dfm	case Intrinsic::spu_si_dfm: // llvm.spu.si.dfm
	case Intrinsic::spu_si_dfma: // llvm.spu.si.dfma	case Intrinsic::spu_si_dfma: // llvm.spu.si.dfma
	case Intrinsic::spu_si_dfms: // llvm.spu.si.dfms	case Intrinsic::spu_si_dfms: // llvm.spu.si.dfms
	case Intrinsic::spu_si_dfnma: // llvm.spu.si.dfnma	case Intrinsic::spu_si_dfnma: // llvm.spu.si.dfnma
	case Intrinsic::spu_si_dfnms: // llvm.spu.si.dfnms	case Intrinsic::spu_si_dfnms: // llvm.spu.si.dfnms
	case Intrinsic::spu_si_dfs: // llvm.spu.si.dfs	case Intrinsic::spu_si_dfs: // llvm.spu.si.dfs
	case Intrinsic::x86_sse2_add_sd: // llvm.x86.sse2.add.sd	case Intrinsic::x86_sse2_add_sd: // llvm.x86.sse2.add.sd
	case Intrinsic::x86_sse2_div_sd: // llvm.x86.sse2.div.sd	case Intrinsic::x86_sse2_div_sd: // llvm.x86.sse2.div.sd
	case Intrinsic::x86_sse2_max_pd: // llvm.x86.sse2.max.pd	case Intrinsic::x86_sse2_max_pd: // llvm.x86.sse2.max.pd
	case Intrinsic::x86_sse2_max_sd: // llvm.x86.sse2.max.sd	case Intrinsic::x86_sse2_max_sd: // llvm.x86.sse2.max.sd
	case Intrinsic::x86_sse2_min_pd: // llvm.x86.sse2.min.pd	case Intrinsic::x86_sse2_min_pd: // llvm.x86.sse2.min.pd
	case Intrinsic::x86_sse2_min_sd: // llvm.x86.sse2.min.sd	case Intrinsic::x86_sse2_min_sd: // llvm.x86.sse2.min.sd
	case Intrinsic::x86_sse2_mul_sd: // llvm.x86.sse2.mul.sd	case Intrinsic::x86_sse2_mul_sd: // llvm.x86.sse2.mul.sd
	case Intrinsic::x86_sse2_sub_sd: // llvm.x86.sse2.sub.sd	case Intrinsic::x86_sse2_sub_sd: // llvm.x86.sse2.sub.sd
	case Intrinsic::x86_sse3_addsub_pd: // llvm.x86.sse3.addsub.pd	case Intrinsic::x86_sse3_addsub_pd: // llvm.x86.sse3.addsub.pd
	case Intrinsic::x86_sse3_hadd_pd: // llvm.x86.sse3.hadd.pd	case Intrinsic::x86_sse3_hadd_pd: // llvm.x86.sse3.hadd.pd
	case Intrinsic::x86_sse3_hsub_pd: // llvm.x86.sse3.hsub.pd	case Intrinsic::x86_sse3_hsub_pd: // llvm.x86.sse3.hsub.pd

		case Intrinsic::x86_xop_vfrcz_sd: // llvm.x86.xop.vfrcz.sd
	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v2f64, MVT::v2f64, MVT::v2f 64);	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v2f64, MVT::v2f64, MVT::v2f 64);
	break;	break;
	case Intrinsic::x86_sse41_blendpd: // llvm.x86.sse41.blendpd	case Intrinsic::x86_sse41_blendpd: // llvm.x86.sse41.blendpd
	case Intrinsic::x86_sse41_dppd: // llvm.x86.sse41.dppd	case Intrinsic::x86_sse41_dppd: // llvm.x86.sse41.dppd
	case Intrinsic::x86_sse41_round_sd: // llvm.x86.sse41.round.sd	case Intrinsic::x86_sse41_round_sd: // llvm.x86.sse41.round.sd
	VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v2f64, MVT::v2f64, MVT::v2f 64, MVT::i32);	VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v2f64, MVT::v2f64, MVT::v2f 64, MVT::i32);
	break;	break;
	case Intrinsic::x86_sse2_cmp_pd: // llvm.x86.sse2.cmp.pd	case Intrinsic::x86_sse2_cmp_pd: // llvm.x86.sse2.cmp.pd
	case Intrinsic::x86_sse2_cmp_sd: // llvm.x86.sse2.cmp.sd	case Intrinsic::x86_sse2_cmp_sd: // llvm.x86.sse2.cmp.sd
	VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v2f64, MVT::v2f64, MVT::v2f 64, MVT::i8);	VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v2f64, MVT::v2f64, MVT::v2f 64, MVT::i8);
	break;	break;

		case Intrinsic::x86_fma4_vfmadd_pd: // llvm.x86.fma4.vfmadd.pd
		case Intrinsic::x86_fma4_vfmadd_sd: // llvm.x86.fma4.vfmadd.sd
		case Intrinsic::x86_fma4_vfmaddsub_pd: // llvm.x86.fma4.vfm
		addsub.pd
		case Intrinsic::x86_fma4_vfmsub_pd: // llvm.x86.fma4.vfmsub.pd
		case Intrinsic::x86_fma4_vfmsub_sd: // llvm.x86.fma4.vfmsub.sd
		case Intrinsic::x86_fma4_vfmsubadd_pd: // llvm.x86.fma4.vfm
		subadd.pd
		case Intrinsic::x86_fma4_vfnmadd_pd: // llvm.x86.fma4.vfnmadd.pd
		case Intrinsic::x86_fma4_vfnmadd_sd: // llvm.x86.fma4.vfnmadd.sd
		case Intrinsic::x86_fma4_vfnmsub_pd: // llvm.x86.fma4.vfnmsub.pd
		case Intrinsic::x86_fma4_vfnmsub_sd: // llvm.x86.fma4.vfnmsub.sd
	case Intrinsic::x86_sse41_blendvpd: // llvm.x86.sse41.blendvpd	case Intrinsic::x86_sse41_blendvpd: // llvm.x86.sse41.blendvpd
	VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v2f64, MVT::v2f64, MVT::v2f 64, MVT::v2f64);	VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v2f64, MVT::v2f64, MVT::v2f 64, MVT::v2f64);
	break;	break;

		case Intrinsic::x86_xop_vpermil2pd: // llvm.x86.xop.vpermil2pd
		VerifyIntrinsicPrototype(ID, IF, 1, 4, MVT::v2f64, MVT::v2f64, MVT::v2f
		64, MVT::v2f64, MVT::i8);
		break;
	case Intrinsic::x86_avx_vpermilvar_pd: // llvm.x86.avx.vper milvar.pd	case Intrinsic::x86_avx_vpermilvar_pd: // llvm.x86.avx.vper milvar.pd
	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v2f64, MVT::v2f64, MVT::v2i 64);	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v2f64, MVT::v2f64, MVT::v2i 64);
	break;	break;
	case Intrinsic::x86_sse2_cvtss2sd: // llvm.x86.sse2.cvtss2sd	case Intrinsic::x86_sse2_cvtss2sd: // llvm.x86.sse2.cvtss2sd
	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v2f64, MVT::v2f64, MVT::v4f 32);	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v2f64, MVT::v2f64, MVT::v4f 32);
	break;	break;
	case Intrinsic::x86_sse2_cvtps2pd: // llvm.x86.sse2.cvtps2pd	case Intrinsic::x86_sse2_cvtps2pd: // llvm.x86.sse2.cvtps2pd
	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v2f64, MVT::v4f32);	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v2f64, MVT::v4f32);
	break;	break;
	case Intrinsic::x86_avx_vextractf128_pd_256: // llvm.x86.avx.vext ractf128.pd.256	case Intrinsic::x86_avx_vextractf128_pd_256: // llvm.x86.avx.vext ractf128.pd.256

	skipping to change at line 9737	skipping to change at line 18761
	case Intrinsic::x86_sse_cvtpi2pd: // llvm.x86.sse.cvtpi2pd	case Intrinsic::x86_sse_cvtpi2pd: // llvm.x86.sse.cvtpi2pd
	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v2f64, MVT::x86mmx);	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v2f64, MVT::x86mmx);
	break;	break;
	case Intrinsic::arm_neon_vacged: // llvm.arm.neon.vacged	case Intrinsic::arm_neon_vacged: // llvm.arm.neon.vacged
	case Intrinsic::arm_neon_vacgtd: // llvm.arm.neon.vacgtd	case Intrinsic::arm_neon_vacgtd: // llvm.arm.neon.vacgtd
	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v2i32, MVT::v2f32, MVT::v2f 32);	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v2i32, MVT::v2f32, MVT::v2f 32);
	break;	break;
	case Intrinsic::x86_sse41_movntdqa: // llvm.x86.sse41.movntdqa	case Intrinsic::x86_sse41_movntdqa: // llvm.x86.sse41.movntdqa
	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v2i64, MVT::iPTR);	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v2i64, MVT::iPTR);
	break;	break;

		case Intrinsic::x86_avx2_maskload_q: // llvm.x86.avx2.maskload.q
		VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v2i64, MVT::iPTR, MVT::v2i6
		4);
		break;
	case Intrinsic::x86_sse41_pmovsxbq: // llvm.x86.sse41.pmovsxbq	case Intrinsic::x86_sse41_pmovsxbq: // llvm.x86.sse41.pmovsxbq
	case Intrinsic::x86_sse41_pmovzxbq: // llvm.x86.sse41.pmovzxbq	case Intrinsic::x86_sse41_pmovzxbq: // llvm.x86.sse41.pmovzxbq

		case Intrinsic::x86_xop_vphaddbq: // llvm.x86.xop.vphaddbq
		case Intrinsic::x86_xop_vphaddubq: // llvm.x86.xop.vphaddubq
	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v2i64, MVT::v16i8);	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v2i64, MVT::v16i8);
	break;	break;
	case Intrinsic::x86_sse2_psad_bw: // llvm.x86.sse2.psad.bw	case Intrinsic::x86_sse2_psad_bw: // llvm.x86.sse2.psad.bw
	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v2i64, MVT::v16i8, MVT::v16 i8);	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v2i64, MVT::v16i8, MVT::v16 i8);
	break;	break;
	case Intrinsic::x86_aesni_aesimc: // llvm.x86.aesni.aesimc	case Intrinsic::x86_aesni_aesimc: // llvm.x86.aesni.aesimc

		case Intrinsic::x86_avx2_pbroadcastq_128: // llvm.x86.avx2.pbr oadcastq.128
	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v2i64, MVT::v2i64);	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v2i64, MVT::v2i64);
	break;	break;
	case Intrinsic::x86_sse2_psll_dq: // llvm.x86.sse2.psll.dq	case Intrinsic::x86_sse2_psll_dq: // llvm.x86.sse2.psll.dq
	case Intrinsic::x86_sse2_psll_dq_bs: // llvm.x86.sse2.psll.dq.bs	case Intrinsic::x86_sse2_psll_dq_bs: // llvm.x86.sse2.psll.dq.bs
	case Intrinsic::x86_sse2_pslli_q: // llvm.x86.sse2.pslli.q	case Intrinsic::x86_sse2_pslli_q: // llvm.x86.sse2.pslli.q
	case Intrinsic::x86_sse2_psrl_dq: // llvm.x86.sse2.psrl.dq	case Intrinsic::x86_sse2_psrl_dq: // llvm.x86.sse2.psrl.dq
	case Intrinsic::x86_sse2_psrl_dq_bs: // llvm.x86.sse2.psrl.dq.bs	case Intrinsic::x86_sse2_psrl_dq_bs: // llvm.x86.sse2.psrl.dq.bs
	case Intrinsic::x86_sse2_psrli_q: // llvm.x86.sse2.psrli.q	case Intrinsic::x86_sse2_psrli_q: // llvm.x86.sse2.psrli.q
	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v2i64, MVT::v2i64, MVT::i32 );	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v2i64, MVT::v2i64, MVT::i32 );
	break;	break;
	case Intrinsic::x86_aesni_aeskeygenassist: // llvm.x86.aesni.ae skeygenassist	case Intrinsic::x86_aesni_aeskeygenassist: // llvm.x86.aesni.ae skeygenassist
	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v2i64, MVT::v2i64, MVT::i8) ;	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v2i64, MVT::v2i64, MVT::i8) ;
	break;	break;
	case Intrinsic::x86_aesni_aesdec: // llvm.x86.aesni.aesdec	case Intrinsic::x86_aesni_aesdec: // llvm.x86.aesni.aesdec
	case Intrinsic::x86_aesni_aesdeclast: // llvm.x86.aesni.ae sdeclast	case Intrinsic::x86_aesni_aesdeclast: // llvm.x86.aesni.ae sdeclast
	case Intrinsic::x86_aesni_aesenc: // llvm.x86.aesni.aesenc	case Intrinsic::x86_aesni_aesenc: // llvm.x86.aesni.aesenc
	case Intrinsic::x86_aesni_aesenclast: // llvm.x86.aesni.ae senclast	case Intrinsic::x86_aesni_aesenclast: // llvm.x86.aesni.ae senclast

		case Intrinsic::x86_avx2_psllv_q: // llvm.x86.avx2.psllv.q
		case Intrinsic::x86_avx2_psrlv_q: // llvm.x86.avx2.psrlv.q
	case Intrinsic::x86_sse2_psll_q: // llvm.x86.sse2.psll.q	case Intrinsic::x86_sse2_psll_q: // llvm.x86.sse2.psll.q
	case Intrinsic::x86_sse2_psrl_q: // llvm.x86.sse2.psrl.q	case Intrinsic::x86_sse2_psrl_q: // llvm.x86.sse2.psrl.q

	case Intrinsic::x86_sse41_pcmpeqq: // llvm.x86.sse41.pcmpeqq	case Intrinsic::x86_xop_vpcomeqq: // llvm.x86.xop.vpcomeqq
	case Intrinsic::x86_sse42_pcmpgtq: // llvm.x86.sse42.pcmpgtq	case Intrinsic::x86_xop_vpcomequq: // llvm.x86.xop.vpcomequq
		case Intrinsic::x86_xop_vpcomfalseq: // llvm.x86.xop.vpcomfalseq
		case Intrinsic::x86_xop_vpcomfalseuq: // llvm.x86.xop.vpco
		mfalseuq
		case Intrinsic::x86_xop_vpcomgeq: // llvm.x86.xop.vpcomgeq
		case Intrinsic::x86_xop_vpcomgeuq: // llvm.x86.xop.vpcomgeuq
		case Intrinsic::x86_xop_vpcomgtq: // llvm.x86.xop.vpcomgtq
		case Intrinsic::x86_xop_vpcomgtuq: // llvm.x86.xop.vpcomgtuq
		case Intrinsic::x86_xop_vpcomleq: // llvm.x86.xop.vpcomleq
		case Intrinsic::x86_xop_vpcomleuq: // llvm.x86.xop.vpcomleuq
		case Intrinsic::x86_xop_vpcomltq: // llvm.x86.xop.vpcomltq
		case Intrinsic::x86_xop_vpcomltuq: // llvm.x86.xop.vpcomltuq
		case Intrinsic::x86_xop_vpcomneq: // llvm.x86.xop.vpcomneq
		case Intrinsic::x86_xop_vpcomneuq: // llvm.x86.xop.vpcomneuq
		case Intrinsic::x86_xop_vpcomtrueq: // llvm.x86.xop.vpcomtrueq
		case Intrinsic::x86_xop_vpcomtrueuq: // llvm.x86.xop.vpcomtrueuq
		case Intrinsic::x86_xop_vprotq: // llvm.x86.xop.vprotq
		case Intrinsic::x86_xop_vpshaq: // llvm.x86.xop.vpshaq
		case Intrinsic::x86_xop_vpshlq: // llvm.x86.xop.vpshlq
	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v2i64, MVT::v2i64, MVT::v2i 64);	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v2i64, MVT::v2i64, MVT::v2i 64);
	break;	break;

		case Intrinsic::x86_xop_vpcmov: // llvm.x86.xop.vpcmov
		VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v2i64, MVT::v2i64, MVT::v2i
		64, MVT::v2i64);
		break;
	case Intrinsic::x86_sse41_pmovsxdq: // llvm.x86.sse41.pmovsxdq	case Intrinsic::x86_sse41_pmovsxdq: // llvm.x86.sse41.pmovsxdq
	case Intrinsic::x86_sse41_pmovzxdq: // llvm.x86.sse41.pmovzxdq	case Intrinsic::x86_sse41_pmovzxdq: // llvm.x86.sse41.pmovzxdq

		case Intrinsic::x86_xop_vphadddq: // llvm.x86.xop.vphadddq
		case Intrinsic::x86_xop_vphaddudq: // llvm.x86.xop.vphaddudq
		case Intrinsic::x86_xop_vphsubdq: // llvm.x86.xop.vphsubdq
	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v2i64, MVT::v4i32);	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v2i64, MVT::v4i32);
	break;	break;
	case Intrinsic::x86_sse2_pmulu_dq: // llvm.x86.sse2.pmulu.dq	case Intrinsic::x86_sse2_pmulu_dq: // llvm.x86.sse2.pmulu.dq
	case Intrinsic::x86_sse41_pmuldq: // llvm.x86.sse41.pmuldq	case Intrinsic::x86_sse41_pmuldq: // llvm.x86.sse41.pmuldq
	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v2i64, MVT::v4i32, MVT::v4i 32);	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v2i64, MVT::v4i32, MVT::v4i 32);
	break;	break;

		case Intrinsic::x86_xop_vpmacsdqh: // llvm.x86.xop.vpmacsdqh
		case Intrinsic::x86_xop_vpmacsdql: // llvm.x86.xop.vpmacsdql
		case Intrinsic::x86_xop_vpmacssdqh: // llvm.x86.xop.vpmacssdqh
		case Intrinsic::x86_xop_vpmacssdql: // llvm.x86.xop.vpmacssdql
		VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v2i64, MVT::v4i32, MVT::v4i
		32, MVT::v2i64);
		break;
		case Intrinsic::x86_avx2_vextracti128: // llvm.x86.avx2.vex
		tracti128
		VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v2i64, MVT::v4i64, MVT::i8)
		;
		break;
	case Intrinsic::x86_sse41_pmovsxwq: // llvm.x86.sse41.pmovsxwq	case Intrinsic::x86_sse41_pmovsxwq: // llvm.x86.sse41.pmovsxwq
	case Intrinsic::x86_sse41_pmovzxwq: // llvm.x86.sse41.pmovzxwq	case Intrinsic::x86_sse41_pmovzxwq: // llvm.x86.sse41.pmovzxwq

		case Intrinsic::x86_xop_vphadduwq: // llvm.x86.xop.vphadduwq
		case Intrinsic::x86_xop_vphaddwq: // llvm.x86.xop.vphaddwq
	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v2i64, MVT::v8i16);	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v2i64, MVT::v8i16);
	break;	break;
	case Intrinsic::x86_avx_ldu_dq_256: // llvm.x86.avx.ldu.dq.256	case Intrinsic::x86_avx_ldu_dq_256: // llvm.x86.avx.ldu.dq.256

	case Intrinsic::x86_avx_loadu_dq_256: // llvm.x86.avx.load u.dq.256
	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v32i8, MVT::iPTR);	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v32i8, MVT::iPTR);
	break;	break;

	case Intrinsic::x86_avx_vbroadcastss: // llvm.x86.avx.vbro	case Intrinsic::x86_avx2_packsswb: // llvm.x86.avx2.packsswb
	adcastss	case Intrinsic::x86_avx2_packuswb: // llvm.x86.avx2.packuswb
		VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v32i8, MVT::v16i16, MVT::v1
		6i16);
		break;
		case Intrinsic::x86_avx2_pbroadcastb_256: // llvm.x86.avx2.pbr
		oadcastb.256
		VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v32i8, MVT::v16i8);
		break;
		case Intrinsic::x86_avx2_pabs_b: // llvm.x86.avx2.pabs.b
		VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v32i8, MVT::v32i8);
		break;
		case Intrinsic::x86_avx2_padds_b: // llvm.x86.avx2.padds.b
		case Intrinsic::x86_avx2_paddus_b: // llvm.x86.avx2.paddus.b
		case Intrinsic::x86_avx2_pavg_b: // llvm.x86.avx2.pavg.b
		case Intrinsic::x86_avx2_pmaxs_b: // llvm.x86.avx2.pmaxs.b
		case Intrinsic::x86_avx2_pmaxu_b: // llvm.x86.avx2.pmaxu.b
		case Intrinsic::x86_avx2_pmins_b: // llvm.x86.avx2.pmins.b
		case Intrinsic::x86_avx2_pminu_b: // llvm.x86.avx2.pminu.b
		case Intrinsic::x86_avx2_pshuf_b: // llvm.x86.avx2.pshuf.b
		case Intrinsic::x86_avx2_psign_b: // llvm.x86.avx2.psign.b
		case Intrinsic::x86_avx2_psubs_b: // llvm.x86.avx2.psubs.b
		case Intrinsic::x86_avx2_psubus_b: // llvm.x86.avx2.psubus.b
		VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v32i8, MVT::v32i8, MVT::v32
		i8);
		break;
		case Intrinsic::x86_avx2_pblendvb: // llvm.x86.avx2.pblendvb
		VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v32i8, MVT::v32i8, MVT::v32
		i8, MVT::v32i8);
		break;
		case Intrinsic::x86_avx_vbroadcast_ss: // llvm.x86.avx.vbro
		adcast.ss
	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v4f32, MVT::iPTR);	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v4f32, MVT::iPTR);
	break;	break;
	case Intrinsic::x86_avx_maskload_ps: // llvm.x86.avx.maskload.ps	case Intrinsic::x86_avx_maskload_ps: // llvm.x86.avx.maskload.ps
	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4f32, MVT::iPTR, MVT::v4f3 2);	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4f32, MVT::iPTR, MVT::v4f3 2);
	break;	break;
	case Intrinsic::x86_sse2_cvtpd2ps: // llvm.x86.sse2.cvtpd2ps	case Intrinsic::x86_sse2_cvtpd2ps: // llvm.x86.sse2.cvtpd2ps
	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v4f32, MVT::v2f64);	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v4f32, MVT::v2f64);
	break;	break;
	case Intrinsic::ppc_altivec_vexptefp: // llvm.ppc.altivec. vexptefp	case Intrinsic::ppc_altivec_vexptefp: // llvm.ppc.altivec. vexptefp
	case Intrinsic::ppc_altivec_vlogefp: // llvm.ppc.altivec.vlogefp	case Intrinsic::ppc_altivec_vlogefp: // llvm.ppc.altivec.vlogefp
	case Intrinsic::ppc_altivec_vrefp: // llvm.ppc.altivec.vrefp	case Intrinsic::ppc_altivec_vrefp: // llvm.ppc.altivec.vrefp
	case Intrinsic::ppc_altivec_vrfim: // llvm.ppc.altivec.vrfim	case Intrinsic::ppc_altivec_vrfim: // llvm.ppc.altivec.vrfim
	case Intrinsic::ppc_altivec_vrfin: // llvm.ppc.altivec.vrfin	case Intrinsic::ppc_altivec_vrfin: // llvm.ppc.altivec.vrfin
	case Intrinsic::ppc_altivec_vrfip: // llvm.ppc.altivec.vrfip	case Intrinsic::ppc_altivec_vrfip: // llvm.ppc.altivec.vrfip
	case Intrinsic::ppc_altivec_vrfiz: // llvm.ppc.altivec.vrfiz	case Intrinsic::ppc_altivec_vrfiz: // llvm.ppc.altivec.vrfiz
	case Intrinsic::ppc_altivec_vrsqrtefp: // llvm.ppc.altivec. vrsqrtefp	case Intrinsic::ppc_altivec_vrsqrtefp: // llvm.ppc.altivec. vrsqrtefp

		case Intrinsic::x86_avx2_vbroadcast_ss_ps: // llvm.x86.avx2.vbr oadcast.ss.ps
	case Intrinsic::x86_sse_rcp_ps: // llvm.x86.sse.rcp.ps	case Intrinsic::x86_sse_rcp_ps: // llvm.x86.sse.rcp.ps
	case Intrinsic::x86_sse_rcp_ss: // llvm.x86.sse.rcp.ss	case Intrinsic::x86_sse_rcp_ss: // llvm.x86.sse.rcp.ss
	case Intrinsic::x86_sse_rsqrt_ps: // llvm.x86.sse.rsqrt.ps	case Intrinsic::x86_sse_rsqrt_ps: // llvm.x86.sse.rsqrt.ps
	case Intrinsic::x86_sse_rsqrt_ss: // llvm.x86.sse.rsqrt.ss	case Intrinsic::x86_sse_rsqrt_ss: // llvm.x86.sse.rsqrt.ss
	case Intrinsic::x86_sse_sqrt_ps: // llvm.x86.sse.sqrt.ps	case Intrinsic::x86_sse_sqrt_ps: // llvm.x86.sse.sqrt.ps
	case Intrinsic::x86_sse_sqrt_ss: // llvm.x86.sse.sqrt.ss	case Intrinsic::x86_sse_sqrt_ss: // llvm.x86.sse.sqrt.ss

		case Intrinsic::x86_xop_vfrcz_ps: // llvm.x86.xop.vfrcz.ps
	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v4f32, MVT::v4f32);	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v4f32, MVT::v4f32);
	break;	break;
	case Intrinsic::x86_sse41_round_ps: // llvm.x86.sse41.round.ps	case Intrinsic::x86_sse41_round_ps: // llvm.x86.sse41.round.ps
	case Intrinsic::x86_sse_cvtsi2ss: // llvm.x86.sse.cvtsi2ss	case Intrinsic::x86_sse_cvtsi2ss: // llvm.x86.sse.cvtsi2ss
	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4f32, MVT::v4f32, MVT::i32 );	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4f32, MVT::v4f32, MVT::i32 );
	break;	break;
	case Intrinsic::x86_sse_cvtsi642ss: // llvm.x86.sse.cvtsi642ss	case Intrinsic::x86_sse_cvtsi642ss: // llvm.x86.sse.cvtsi642ss
	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4f32, MVT::v4f32, MVT::i64 );	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4f32, MVT::v4f32, MVT::i64 );
	break;	break;

	case Intrinsic::x86_avx_vpermil_ps: // llvm.x86.avx.vpermil.ps
	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4f32, MVT::v4f32, MVT::i8)
	;
	break;
	case Intrinsic::x86_sse2_cvtsd2ss: // llvm.x86.sse2.cvtsd2ss	case Intrinsic::x86_sse2_cvtsd2ss: // llvm.x86.sse2.cvtsd2ss
	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4f32, MVT::v4f32, MVT::v2f 64);	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4f32, MVT::v4f32, MVT::v2f 64);
	break;	break;
	case Intrinsic::ppc_altivec_vmaxfp: // llvm.ppc.altivec.vmaxfp	case Intrinsic::ppc_altivec_vmaxfp: // llvm.ppc.altivec.vmaxfp
	case Intrinsic::ppc_altivec_vminfp: // llvm.ppc.altivec.vminfp	case Intrinsic::ppc_altivec_vminfp: // llvm.ppc.altivec.vminfp
	case Intrinsic::spu_si_fa: // llvm.spu.si.fa	case Intrinsic::spu_si_fa: // llvm.spu.si.fa
	case Intrinsic::spu_si_fceq: // llvm.spu.si.fceq	case Intrinsic::spu_si_fceq: // llvm.spu.si.fceq
	case Intrinsic::spu_si_fcgt: // llvm.spu.si.fcgt	case Intrinsic::spu_si_fcgt: // llvm.spu.si.fcgt
	case Intrinsic::spu_si_fcmeq: // llvm.spu.si.fcmeq	case Intrinsic::spu_si_fcmeq: // llvm.spu.si.fcmeq
	case Intrinsic::spu_si_fcmgt: // llvm.spu.si.fcmgt	case Intrinsic::spu_si_fcmgt: // llvm.spu.si.fcmgt

	skipping to change at line 9842	skipping to change at line 18932
	case Intrinsic::x86_sse3_hadd_ps: // llvm.x86.sse3.hadd.ps	case Intrinsic::x86_sse3_hadd_ps: // llvm.x86.sse3.hadd.ps
	case Intrinsic::x86_sse3_hsub_ps: // llvm.x86.sse3.hsub.ps	case Intrinsic::x86_sse3_hsub_ps: // llvm.x86.sse3.hsub.ps
	case Intrinsic::x86_sse_add_ss: // llvm.x86.sse.add.ss	case Intrinsic::x86_sse_add_ss: // llvm.x86.sse.add.ss
	case Intrinsic::x86_sse_div_ss: // llvm.x86.sse.div.ss	case Intrinsic::x86_sse_div_ss: // llvm.x86.sse.div.ss
	case Intrinsic::x86_sse_max_ps: // llvm.x86.sse.max.ps	case Intrinsic::x86_sse_max_ps: // llvm.x86.sse.max.ps
	case Intrinsic::x86_sse_max_ss: // llvm.x86.sse.max.ss	case Intrinsic::x86_sse_max_ss: // llvm.x86.sse.max.ss
	case Intrinsic::x86_sse_min_ps: // llvm.x86.sse.min.ps	case Intrinsic::x86_sse_min_ps: // llvm.x86.sse.min.ps
	case Intrinsic::x86_sse_min_ss: // llvm.x86.sse.min.ss	case Intrinsic::x86_sse_min_ss: // llvm.x86.sse.min.ss
	case Intrinsic::x86_sse_mul_ss: // llvm.x86.sse.mul.ss	case Intrinsic::x86_sse_mul_ss: // llvm.x86.sse.mul.ss
	case Intrinsic::x86_sse_sub_ss: // llvm.x86.sse.sub.ss	case Intrinsic::x86_sse_sub_ss: // llvm.x86.sse.sub.ss

		case Intrinsic::x86_xop_vfrcz_ss: // llvm.x86.xop.vfrcz.ss
	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4f32, MVT::v4f32, MVT::v4f 32);	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4f32, MVT::v4f32, MVT::v4f 32);
	break;	break;
	case Intrinsic::x86_sse41_blendps: // llvm.x86.sse41.blendps	case Intrinsic::x86_sse41_blendps: // llvm.x86.sse41.blendps
	case Intrinsic::x86_sse41_dpps: // llvm.x86.sse41.dpps	case Intrinsic::x86_sse41_dpps: // llvm.x86.sse41.dpps
	case Intrinsic::x86_sse41_insertps: // llvm.x86.sse41.insertps	case Intrinsic::x86_sse41_insertps: // llvm.x86.sse41.insertps
	case Intrinsic::x86_sse41_round_ss: // llvm.x86.sse41.round.ss	case Intrinsic::x86_sse41_round_ss: // llvm.x86.sse41.round.ss
	VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v4f32, MVT::v4f32, MVT::v4f 32, MVT::i32);	VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v4f32, MVT::v4f32, MVT::v4f 32, MVT::i32);
	break;	break;
	case Intrinsic::x86_sse_cmp_ps: // llvm.x86.sse.cmp.ps	case Intrinsic::x86_sse_cmp_ps: // llvm.x86.sse.cmp.ps
	case Intrinsic::x86_sse_cmp_ss: // llvm.x86.sse.cmp.ss	case Intrinsic::x86_sse_cmp_ss: // llvm.x86.sse.cmp.ss
	VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v4f32, MVT::v4f32, MVT::v4f 32, MVT::i8);	VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v4f32, MVT::v4f32, MVT::v4f 32, MVT::i8);
	break;	break;
	case Intrinsic::ppc_altivec_vmaddfp: // llvm.ppc.altivec.vmaddfp	case Intrinsic::ppc_altivec_vmaddfp: // llvm.ppc.altivec.vmaddfp
	case Intrinsic::ppc_altivec_vnmsubfp: // llvm.ppc.altivec. vnmsubfp	case Intrinsic::ppc_altivec_vnmsubfp: // llvm.ppc.altivec. vnmsubfp
	case Intrinsic::spu_si_fma: // llvm.spu.si.fma	case Intrinsic::spu_si_fma: // llvm.spu.si.fma
	case Intrinsic::spu_si_fms: // llvm.spu.si.fms	case Intrinsic::spu_si_fms: // llvm.spu.si.fms
	case Intrinsic::spu_si_fnms: // llvm.spu.si.fnms	case Intrinsic::spu_si_fnms: // llvm.spu.si.fnms

		case Intrinsic::x86_fma4_vfmadd_ps: // llvm.x86.fma4.vfmadd.ps
		case Intrinsic::x86_fma4_vfmadd_ss: // llvm.x86.fma4.vfmadd.ss
		case Intrinsic::x86_fma4_vfmaddsub_ps: // llvm.x86.fma4.vfm
		addsub.ps
		case Intrinsic::x86_fma4_vfmsub_ps: // llvm.x86.fma4.vfmsub.ps
		case Intrinsic::x86_fma4_vfmsub_ss: // llvm.x86.fma4.vfmsub.ss
		case Intrinsic::x86_fma4_vfmsubadd_ps: // llvm.x86.fma4.vfm
		subadd.ps
		case Intrinsic::x86_fma4_vfnmadd_ps: // llvm.x86.fma4.vfnmadd.ps
		case Intrinsic::x86_fma4_vfnmadd_ss: // llvm.x86.fma4.vfnmadd.ss
		case Intrinsic::x86_fma4_vfnmsub_ps: // llvm.x86.fma4.vfnmsub.ps
		case Intrinsic::x86_fma4_vfnmsub_ss: // llvm.x86.fma4.vfnmsub.ss
	case Intrinsic::x86_sse41_blendvps: // llvm.x86.sse41.blendvps	case Intrinsic::x86_sse41_blendvps: // llvm.x86.sse41.blendvps
	VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v4f32, MVT::v4f32, MVT::v4f 32, MVT::v4f32);	VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v4f32, MVT::v4f32, MVT::v4f 32, MVT::v4f32);
	break;	break;

		case Intrinsic::x86_xop_vpermil2ps: // llvm.x86.xop.vpermil2ps
		VerifyIntrinsicPrototype(ID, IF, 1, 4, MVT::v4f32, MVT::v4f32, MVT::v4f
		32, MVT::v4f32, MVT::i8);
		break;
	case Intrinsic::x86_avx_vpermilvar_ps: // llvm.x86.avx.vper milvar.ps	case Intrinsic::x86_avx_vpermilvar_ps: // llvm.x86.avx.vper milvar.ps
	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4f32, MVT::v4f32, MVT::v4i 32);	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4f32, MVT::v4f32, MVT::v4i 32);
	break;	break;
	case Intrinsic::x86_sse_cvtpi2ps: // llvm.x86.sse.cvtpi2ps	case Intrinsic::x86_sse_cvtpi2ps: // llvm.x86.sse.cvtpi2ps
	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4f32, MVT::v4f32, MVT::x86 mmx);	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4f32, MVT::v4f32, MVT::x86 mmx);
	break;	break;
	case Intrinsic::x86_avx_cvt_pd2_ps_256: // llvm.x86.avx.cvt. pd2.ps.256	case Intrinsic::x86_avx_cvt_pd2_ps_256: // llvm.x86.avx.cvt. pd2.ps.256
	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v4f32, MVT::v4f64);	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v4f32, MVT::v4f64);
	break;	break;
	case Intrinsic::arm_neon_vcvthf2fp: // llvm.arm.neon.vcvthf2fp	case Intrinsic::arm_neon_vcvthf2fp: // llvm.arm.neon.vcvthf2fp

	skipping to change at line 9884	skipping to change at line 18988
	case Intrinsic::x86_sse2_cvtdq2ps: // llvm.x86.sse2.cvtdq2ps	case Intrinsic::x86_sse2_cvtdq2ps: // llvm.x86.sse2.cvtdq2ps
	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v4f32, MVT::v4i32);	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v4f32, MVT::v4i32);
	break;	break;
	case Intrinsic::ppc_altivec_vcfsx: // llvm.ppc.altivec.vcfsx	case Intrinsic::ppc_altivec_vcfsx: // llvm.ppc.altivec.vcfsx
	case Intrinsic::ppc_altivec_vcfux: // llvm.ppc.altivec.vcfux	case Intrinsic::ppc_altivec_vcfux: // llvm.ppc.altivec.vcfux
	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4f32, MVT::v4i32, MVT::i32 );	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4f32, MVT::v4i32, MVT::i32 );
	break;	break;
	case Intrinsic::x86_avx_vextractf128_ps_256: // llvm.x86.avx.vext ractf128.ps.256	case Intrinsic::x86_avx_vextractf128_ps_256: // llvm.x86.avx.vext ractf128.ps.256
	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4f32, MVT::v8f32, MVT::i8) ;	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4f32, MVT::v8f32, MVT::i8) ;
	break;	break;

	case Intrinsic::x86_avx_loadu_pd_256: // llvm.x86.avx.load	case Intrinsic::x86_vcvtph2ps_128: // llvm.x86.vcvtph2ps.128
	u.pd.256	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v4f32, MVT::v8i16);
		break;
	case Intrinsic::x86_avx_vbroadcast_sd_256: // llvm.x86.avx.vbro adcast.sd.256	case Intrinsic::x86_avx_vbroadcast_sd_256: // llvm.x86.avx.vbro adcast.sd.256
	case Intrinsic::x86_avx_vbroadcastf128_pd_256: // llvm.x86. avx.vbroadcastf128.pd.256	case Intrinsic::x86_avx_vbroadcastf128_pd_256: // llvm.x86. avx.vbroadcastf128.pd.256
	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v4f64, MVT::iPTR);	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v4f64, MVT::iPTR);
	break;	break;
	case Intrinsic::x86_avx_maskload_pd_256: // llvm.x86.avx.mask load.pd.256	case Intrinsic::x86_avx_maskload_pd_256: // llvm.x86.avx.mask load.pd.256
	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4f64, MVT::iPTR, MVT::v4f6 4);	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4f64, MVT::iPTR, MVT::v4f6 4);
	break;	break;

		case Intrinsic::x86_avx2_vbroadcast_sd_pd_256: // llvm.x86.
		avx2.vbroadcast.sd.pd.256
		VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v4f64, MVT::v2f64);
		break;
	case Intrinsic::x86_avx_cvt_ps2_pd_256: // llvm.x86.avx.cvt. ps2.pd.256	case Intrinsic::x86_avx_cvt_ps2_pd_256: // llvm.x86.avx.cvt. ps2.pd.256
	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v4f64, MVT::v4f32);	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v4f64, MVT::v4f32);
	break;	break;
	case Intrinsic::x86_avx_sqrt_pd_256: // llvm.x86.avx.sqrt.pd.256	case Intrinsic::x86_avx_sqrt_pd_256: // llvm.x86.avx.sqrt.pd.256

		case Intrinsic::x86_xop_vfrcz_pd_256: // llvm.x86.xop.vfrc z.pd.256
	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v4f64, MVT::v4f64);	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v4f64, MVT::v4f64);
	break;	break;
	case Intrinsic::x86_avx_round_pd_256: // llvm.x86.avx.roun d.pd.256	case Intrinsic::x86_avx_round_pd_256: // llvm.x86.avx.roun d.pd.256
	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4f64, MVT::v4f64, MVT::i32 );	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4f64, MVT::v4f64, MVT::i32 );
	break;	break;

	case Intrinsic::x86_avx_vpermil_pd_256: // llvm.x86.avx.vper
	mil.pd.256
	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4f64, MVT::v4f64, MVT::i8)
	;
	break;
	case Intrinsic::x86_avx_vinsertf128_pd_256: // llvm.x86.avx.vins ertf128.pd.256	case Intrinsic::x86_avx_vinsertf128_pd_256: // llvm.x86.avx.vins ertf128.pd.256
	VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v4f64, MVT::v4f64, MVT::v2f 64, MVT::i8);	VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v4f64, MVT::v4f64, MVT::v2f 64, MVT::i8);
	break;	break;
	case Intrinsic::x86_avx_addsub_pd_256: // llvm.x86.avx.adds ub.pd.256	case Intrinsic::x86_avx_addsub_pd_256: // llvm.x86.avx.adds ub.pd.256
	case Intrinsic::x86_avx_hadd_pd_256: // llvm.x86.avx.hadd.pd.256	case Intrinsic::x86_avx_hadd_pd_256: // llvm.x86.avx.hadd.pd.256
	case Intrinsic::x86_avx_hsub_pd_256: // llvm.x86.avx.hsub.pd.256	case Intrinsic::x86_avx_hsub_pd_256: // llvm.x86.avx.hsub.pd.256
	case Intrinsic::x86_avx_max_pd_256: // llvm.x86.avx.max.pd.256	case Intrinsic::x86_avx_max_pd_256: // llvm.x86.avx.max.pd.256
	case Intrinsic::x86_avx_min_pd_256: // llvm.x86.avx.min.pd.256	case Intrinsic::x86_avx_min_pd_256: // llvm.x86.avx.min.pd.256
	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4f64, MVT::v4f64, MVT::v4f 64);	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4f64, MVT::v4f64, MVT::v4f 64);
	break;	break;
	case Intrinsic::x86_avx_blend_pd_256: // llvm.x86.avx.blen d.pd.256	case Intrinsic::x86_avx_blend_pd_256: // llvm.x86.avx.blen d.pd.256
	VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v4f64, MVT::v4f64, MVT::v4f 64, MVT::i32);	VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v4f64, MVT::v4f64, MVT::v4f 64, MVT::i32);
	break;	break;
	case Intrinsic::x86_avx_cmp_pd_256: // llvm.x86.avx.cmp.pd.256	case Intrinsic::x86_avx_cmp_pd_256: // llvm.x86.avx.cmp.pd.256
	case Intrinsic::x86_avx_vperm2f128_pd_256: // llvm.x86.avx.vper m2f128.pd.256	case Intrinsic::x86_avx_vperm2f128_pd_256: // llvm.x86.avx.vper m2f128.pd.256
	VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v4f64, MVT::v4f64, MVT::v4f 64, MVT::i8);	VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v4f64, MVT::v4f64, MVT::v4f 64, MVT::i8);
	break;	break;
	case Intrinsic::x86_avx_blendv_pd_256: // llvm.x86.avx.blen dv.pd.256	case Intrinsic::x86_avx_blendv_pd_256: // llvm.x86.avx.blen dv.pd.256

		case Intrinsic::x86_fma4_vfmadd_pd_256: // llvm.x86.fma4.vfm
		add.pd.256
		case Intrinsic::x86_fma4_vfmaddsub_pd_256: // llvm.x86.fma4.vfm
		addsub.pd.256
		case Intrinsic::x86_fma4_vfmsub_pd_256: // llvm.x86.fma4.vfm
		sub.pd.256
		case Intrinsic::x86_fma4_vfmsubadd_pd_256: // llvm.x86.fma4.vfm
		subadd.pd.256
		case Intrinsic::x86_fma4_vfnmadd_pd_256: // llvm.x86.fma4.vfn
		madd.pd.256
		case Intrinsic::x86_fma4_vfnmsub_pd_256: // llvm.x86.fma4.vfn
		msub.pd.256
	VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v4f64, MVT::v4f64, MVT::v4f 64, MVT::v4f64);	VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v4f64, MVT::v4f64, MVT::v4f 64, MVT::v4f64);
	break;	break;

		case Intrinsic::x86_xop_vpermil2pd_256: // llvm.x86.xop.vper
		mil2pd.256
		VerifyIntrinsicPrototype(ID, IF, 1, 4, MVT::v4f64, MVT::v4f64, MVT::v4f
		64, MVT::v4f64, MVT::i8);
		break;
	case Intrinsic::x86_avx_vpermilvar_pd_256: // llvm.x86.avx.vper milvar.pd.256	case Intrinsic::x86_avx_vpermilvar_pd_256: // llvm.x86.avx.vper milvar.pd.256
	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4f64, MVT::v4f64, MVT::v4i 64);	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4f64, MVT::v4f64, MVT::v4i 64);
	break;	break;
	case Intrinsic::x86_avx_cvtdq2_pd_256: // llvm.x86.avx.cvtd q2.pd.256	case Intrinsic::x86_avx_cvtdq2_pd_256: // llvm.x86.avx.cvtd q2.pd.256
	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v4f64, MVT::v4i32);	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v4f64, MVT::v4i32);
	break;	break;
	case Intrinsic::arm_neon_vcvtfp2hf: // llvm.arm.neon.vcvtfp2hf	case Intrinsic::arm_neon_vcvtfp2hf: // llvm.arm.neon.vcvtfp2hf
	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v4i16, MVT::v4f32);	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v4i16, MVT::v4f32);
	break;	break;
	case Intrinsic::ppc_altivec_lvewx: // llvm.ppc.altivec.lvewx	case Intrinsic::ppc_altivec_lvewx: // llvm.ppc.altivec.lvewx
	case Intrinsic::ppc_altivec_lvx: // llvm.ppc.altivec.lvx	case Intrinsic::ppc_altivec_lvx: // llvm.ppc.altivec.lvx
	case Intrinsic::ppc_altivec_lvxl: // llvm.ppc.altivec.lvxl	case Intrinsic::ppc_altivec_lvxl: // llvm.ppc.altivec.lvxl
	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v4i32, MVT::iPTR);	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v4i32, MVT::iPTR);
	break;	break;

		case Intrinsic::x86_avx2_maskload_d: // llvm.x86.avx2.maskload.d
		VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4i32, MVT::iPTR, MVT::v4i3
		2);
		break;
	case Intrinsic::x86_sse41_pmovsxbd: // llvm.x86.sse41.pmovsxbd	case Intrinsic::x86_sse41_pmovsxbd: // llvm.x86.sse41.pmovsxbd
	case Intrinsic::x86_sse41_pmovzxbd: // llvm.x86.sse41.pmovzxbd	case Intrinsic::x86_sse41_pmovzxbd: // llvm.x86.sse41.pmovzxbd

		case Intrinsic::x86_xop_vphaddbd: // llvm.x86.xop.vphaddbd
		case Intrinsic::x86_xop_vphaddubd: // llvm.x86.xop.vphaddubd
	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v4i32, MVT::v16i8);	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v4i32, MVT::v16i8);
	break;	break;
	case Intrinsic::ppc_altivec_vmsummbm: // llvm.ppc.altivec. vmsummbm	case Intrinsic::ppc_altivec_vmsummbm: // llvm.ppc.altivec. vmsummbm
	case Intrinsic::ppc_altivec_vmsumubm: // llvm.ppc.altivec. vmsumubm	case Intrinsic::ppc_altivec_vmsumubm: // llvm.ppc.altivec. vmsumubm
	VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v4i32, MVT::v16i8, MVT::v16 i8, MVT::v4i32);	VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v4i32, MVT::v16i8, MVT::v16 i8, MVT::v4i32);
	break;	break;
	case Intrinsic::ppc_altivec_vsum4sbs: // llvm.ppc.altivec. vsum4sbs	case Intrinsic::ppc_altivec_vsum4sbs: // llvm.ppc.altivec. vsum4sbs
	case Intrinsic::ppc_altivec_vsum4ubs: // llvm.ppc.altivec. vsum4ubs	case Intrinsic::ppc_altivec_vsum4ubs: // llvm.ppc.altivec. vsum4ubs
	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4i32, MVT::v16i8, MVT::v4i 32);	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4i32, MVT::v16i8, MVT::v4i 32);
	break;	break;

	skipping to change at line 9974	skipping to change at line 19095
	case Intrinsic::ppc_altivec_vcmpbfp: // llvm.ppc.altivec.vcmpbfp	case Intrinsic::ppc_altivec_vcmpbfp: // llvm.ppc.altivec.vcmpbfp
	case Intrinsic::ppc_altivec_vcmpeqfp: // llvm.ppc.altivec. vcmpeqfp	case Intrinsic::ppc_altivec_vcmpeqfp: // llvm.ppc.altivec. vcmpeqfp
	case Intrinsic::ppc_altivec_vcmpgefp: // llvm.ppc.altivec. vcmpgefp	case Intrinsic::ppc_altivec_vcmpgefp: // llvm.ppc.altivec. vcmpgefp
	case Intrinsic::ppc_altivec_vcmpgtfp: // llvm.ppc.altivec. vcmpgtfp	case Intrinsic::ppc_altivec_vcmpgtfp: // llvm.ppc.altivec. vcmpgtfp
	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4i32, MVT::v4f32, MVT::v4f 32);	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4i32, MVT::v4f32, MVT::v4f 32);
	break;	break;
	case Intrinsic::x86_avx_cvt_pd2dq_256: // llvm.x86.avx.cvt. pd2dq.256	case Intrinsic::x86_avx_cvt_pd2dq_256: // llvm.x86.avx.cvt. pd2dq.256
	case Intrinsic::x86_avx_cvtt_pd2dq_256: // llvm.x86.avx.cvtt .pd2dq.256	case Intrinsic::x86_avx_cvtt_pd2dq_256: // llvm.x86.avx.cvtt .pd2dq.256
	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v4i32, MVT::v4f64);	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v4i32, MVT::v4f64);
	break;	break;

		case Intrinsic::x86_avx2_pbroadcastd_128: // llvm.x86.avx2.pbr oadcastd.128
	case Intrinsic::x86_ssse3_pabs_d_128: // llvm.x86.ssse3.pa bs.d.128	case Intrinsic::x86_ssse3_pabs_d_128: // llvm.x86.ssse3.pa bs.d.128
	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v4i32, MVT::v4i32);	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v4i32, MVT::v4i32);
	break;	break;
	case Intrinsic::spu_si_shli: // llvm.spu.si.shli	case Intrinsic::spu_si_shli: // llvm.spu.si.shli
	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4i32, MVT::v4i32, MVT::i8) ;	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4i32, MVT::v4i32, MVT::i8) ;
	break;	break;
	case Intrinsic::spu_si_ai: // llvm.spu.si.ai	case Intrinsic::spu_si_ai: // llvm.spu.si.ai
	case Intrinsic::spu_si_andi: // llvm.spu.si.andi	case Intrinsic::spu_si_andi: // llvm.spu.si.andi
	case Intrinsic::spu_si_ceqi: // llvm.spu.si.ceqi	case Intrinsic::spu_si_ceqi: // llvm.spu.si.ceqi
	case Intrinsic::spu_si_cgti: // llvm.spu.si.cgti	case Intrinsic::spu_si_cgti: // llvm.spu.si.cgti

	skipping to change at line 10038	skipping to change at line 19160
	case Intrinsic::spu_si_cgt: // llvm.spu.si.cgt	case Intrinsic::spu_si_cgt: // llvm.spu.si.cgt
	case Intrinsic::spu_si_cgx: // llvm.spu.si.cgx	case Intrinsic::spu_si_cgx: // llvm.spu.si.cgx
	case Intrinsic::spu_si_clgt: // llvm.spu.si.clgt	case Intrinsic::spu_si_clgt: // llvm.spu.si.clgt
	case Intrinsic::spu_si_nand: // llvm.spu.si.nand	case Intrinsic::spu_si_nand: // llvm.spu.si.nand
	case Intrinsic::spu_si_nor: // llvm.spu.si.nor	case Intrinsic::spu_si_nor: // llvm.spu.si.nor
	case Intrinsic::spu_si_or: // llvm.spu.si.or	case Intrinsic::spu_si_or: // llvm.spu.si.or
	case Intrinsic::spu_si_orc: // llvm.spu.si.orc	case Intrinsic::spu_si_orc: // llvm.spu.si.orc
	case Intrinsic::spu_si_sf: // llvm.spu.si.sf	case Intrinsic::spu_si_sf: // llvm.spu.si.sf
	case Intrinsic::spu_si_sfx: // llvm.spu.si.sfx	case Intrinsic::spu_si_sfx: // llvm.spu.si.sfx
	case Intrinsic::spu_si_xor: // llvm.spu.si.xor	case Intrinsic::spu_si_xor: // llvm.spu.si.xor

	case Intrinsic::x86_sse2_pcmpeq_d: // llvm.x86.sse2.pcmpeq.d	case Intrinsic::x86_avx2_psllv_d: // llvm.x86.avx2.psllv.d
	case Intrinsic::x86_sse2_pcmpgt_d: // llvm.x86.sse2.pcmpgt.d	case Intrinsic::x86_avx2_psrav_d: // llvm.x86.avx2.psrav.d
		case Intrinsic::x86_avx2_psrlv_d: // llvm.x86.avx2.psrlv.d
	case Intrinsic::x86_sse2_psll_d: // llvm.x86.sse2.psll.d	case Intrinsic::x86_sse2_psll_d: // llvm.x86.sse2.psll.d
	case Intrinsic::x86_sse2_psra_d: // llvm.x86.sse2.psra.d	case Intrinsic::x86_sse2_psra_d: // llvm.x86.sse2.psra.d
	case Intrinsic::x86_sse2_psrl_d: // llvm.x86.sse2.psrl.d	case Intrinsic::x86_sse2_psrl_d: // llvm.x86.sse2.psrl.d
	case Intrinsic::x86_sse41_pmaxsd: // llvm.x86.sse41.pmaxsd	case Intrinsic::x86_sse41_pmaxsd: // llvm.x86.sse41.pmaxsd
	case Intrinsic::x86_sse41_pmaxud: // llvm.x86.sse41.pmaxud	case Intrinsic::x86_sse41_pmaxud: // llvm.x86.sse41.pmaxud
	case Intrinsic::x86_sse41_pminsd: // llvm.x86.sse41.pminsd	case Intrinsic::x86_sse41_pminsd: // llvm.x86.sse41.pminsd
	case Intrinsic::x86_sse41_pminud: // llvm.x86.sse41.pminud	case Intrinsic::x86_sse41_pminud: // llvm.x86.sse41.pminud
	case Intrinsic::x86_ssse3_phadd_d_128: // llvm.x86.ssse3.ph add.d.128	case Intrinsic::x86_ssse3_phadd_d_128: // llvm.x86.ssse3.ph add.d.128

	case Intrinsic::x86_ssse3_phadd_sw_128: // llvm.x86.ssse3.ph add.sw.128
	case Intrinsic::x86_ssse3_phsub_d_128: // llvm.x86.ssse3.ph sub.d.128	case Intrinsic::x86_ssse3_phsub_d_128: // llvm.x86.ssse3.ph sub.d.128
	case Intrinsic::x86_ssse3_psign_d_128: // llvm.x86.ssse3.ps ign.d.128	case Intrinsic::x86_ssse3_psign_d_128: // llvm.x86.ssse3.ps ign.d.128

		case Intrinsic::x86_xop_vpcomeqd: // llvm.x86.xop.vpcomeqd
		case Intrinsic::x86_xop_vpcomequd: // llvm.x86.xop.vpcomequd
		case Intrinsic::x86_xop_vpcomfalsed: // llvm.x86.xop.vpcomfalsed
		case Intrinsic::x86_xop_vpcomfalseud: // llvm.x86.xop.vpco
		mfalseud
		case Intrinsic::x86_xop_vpcomged: // llvm.x86.xop.vpcomged
		case Intrinsic::x86_xop_vpcomgeud: // llvm.x86.xop.vpcomgeud
		case Intrinsic::x86_xop_vpcomgtd: // llvm.x86.xop.vpcomgtd
		case Intrinsic::x86_xop_vpcomgtud: // llvm.x86.xop.vpcomgtud
		case Intrinsic::x86_xop_vpcomled: // llvm.x86.xop.vpcomled
		case Intrinsic::x86_xop_vpcomleud: // llvm.x86.xop.vpcomleud
		case Intrinsic::x86_xop_vpcomltd: // llvm.x86.xop.vpcomltd
		case Intrinsic::x86_xop_vpcomltud: // llvm.x86.xop.vpcomltud
		case Intrinsic::x86_xop_vpcomned: // llvm.x86.xop.vpcomned
		case Intrinsic::x86_xop_vpcomneud: // llvm.x86.xop.vpcomneud
		case Intrinsic::x86_xop_vpcomtrued: // llvm.x86.xop.vpcomtrued
		case Intrinsic::x86_xop_vpcomtrueud: // llvm.x86.xop.vpcomtrueud
		case Intrinsic::x86_xop_vprotd: // llvm.x86.xop.vprotd
		case Intrinsic::x86_xop_vpshad: // llvm.x86.xop.vpshad
		case Intrinsic::x86_xop_vpshld: // llvm.x86.xop.vpshld
	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4i32, MVT::v4i32, MVT::v4i 32);	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4i32, MVT::v4i32, MVT::v4i 32);
	break;	break;

		case Intrinsic::x86_avx2_pblendd_128: // llvm.x86.avx2.pbl
		endd.128
		VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v4i32, MVT::v4i32, MVT::v4i
		32, MVT::i32);
		break;
	case Intrinsic::ppc_altivec_vperm: // llvm.ppc.altivec.vperm	case Intrinsic::ppc_altivec_vperm: // llvm.ppc.altivec.vperm
	VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v4i32, MVT::v4i32, MVT::v4i 32, MVT::v16i8);	VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v4i32, MVT::v4i32, MVT::v4i 32, MVT::v16i8);
	break;	break;
	case Intrinsic::ppc_altivec_vsel: // llvm.ppc.altivec.vsel	case Intrinsic::ppc_altivec_vsel: // llvm.ppc.altivec.vsel

		case Intrinsic::x86_xop_vpmacsdd: // llvm.x86.xop.vpmacsdd
		case Intrinsic::x86_xop_vpmacssdd: // llvm.x86.xop.vpmacssdd
	VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v4i32, MVT::v4i32, MVT::v4i 32, MVT::v4i32);	VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v4i32, MVT::v4i32, MVT::v4i 32, MVT::v4i32);
	break;	break;
	case Intrinsic::spu_si_mpyh: // llvm.spu.si.mpyh	case Intrinsic::spu_si_mpyh: // llvm.spu.si.mpyh
	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4i32, MVT::v4i32, MVT::v8i 16);	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4i32, MVT::v4i32, MVT::v8i 16);
	break;	break;
	case Intrinsic::ppc_altivec_vupkhpx: // llvm.ppc.altivec.vupkhpx	case Intrinsic::ppc_altivec_vupkhpx: // llvm.ppc.altivec.vupkhpx
	case Intrinsic::ppc_altivec_vupkhsh: // llvm.ppc.altivec.vupkhsh	case Intrinsic::ppc_altivec_vupkhsh: // llvm.ppc.altivec.vupkhsh
	case Intrinsic::ppc_altivec_vupklpx: // llvm.ppc.altivec.vupklpx	case Intrinsic::ppc_altivec_vupklpx: // llvm.ppc.altivec.vupklpx
	case Intrinsic::ppc_altivec_vupklsh: // llvm.ppc.altivec.vupklsh	case Intrinsic::ppc_altivec_vupklsh: // llvm.ppc.altivec.vupklsh
	case Intrinsic::x86_sse41_pmovsxwd: // llvm.x86.sse41.pmovsxwd	case Intrinsic::x86_sse41_pmovsxwd: // llvm.x86.sse41.pmovsxwd
	case Intrinsic::x86_sse41_pmovzxwd: // llvm.x86.sse41.pmovzxwd	case Intrinsic::x86_sse41_pmovzxwd: // llvm.x86.sse41.pmovzxwd

		case Intrinsic::x86_xop_vphadduwd: // llvm.x86.xop.vphadduwd
		case Intrinsic::x86_xop_vphaddwd: // llvm.x86.xop.vphaddwd
		case Intrinsic::x86_xop_vphsubwd: // llvm.x86.xop.vphsubwd
	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v4i32, MVT::v8i16);	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v4i32, MVT::v8i16);
	break;	break;
	case Intrinsic::spu_si_mpyi: // llvm.spu.si.mpyi	case Intrinsic::spu_si_mpyi: // llvm.spu.si.mpyi
	case Intrinsic::spu_si_mpyui: // llvm.spu.si.mpyui	case Intrinsic::spu_si_mpyui: // llvm.spu.si.mpyui
	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4i32, MVT::v8i16, MVT::i16 );	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4i32, MVT::v8i16, MVT::i16 );
	break;	break;
	case Intrinsic::ppc_altivec_vsum4shs: // llvm.ppc.altivec. vsum4shs	case Intrinsic::ppc_altivec_vsum4shs: // llvm.ppc.altivec. vsum4shs
	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4i32, MVT::v8i16, MVT::v4i 32);	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4i32, MVT::v8i16, MVT::v4i 32);
	break;	break;
	case Intrinsic::ppc_altivec_vmulesh: // llvm.ppc.altivec.vmulesh	case Intrinsic::ppc_altivec_vmulesh: // llvm.ppc.altivec.vmulesh

	skipping to change at line 10095	skipping to change at line 19244
	case Intrinsic::spu_si_mpyhhu: // llvm.spu.si.mpyhhu	case Intrinsic::spu_si_mpyhhu: // llvm.spu.si.mpyhhu
	case Intrinsic::spu_si_mpys: // llvm.spu.si.mpys	case Intrinsic::spu_si_mpys: // llvm.spu.si.mpys
	case Intrinsic::spu_si_mpyu: // llvm.spu.si.mpyu	case Intrinsic::spu_si_mpyu: // llvm.spu.si.mpyu
	case Intrinsic::x86_sse2_pmadd_wd: // llvm.x86.sse2.pmadd.wd	case Intrinsic::x86_sse2_pmadd_wd: // llvm.x86.sse2.pmadd.wd
	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4i32, MVT::v8i16, MVT::v8i 16);	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4i32, MVT::v8i16, MVT::v8i 16);
	break;	break;
	case Intrinsic::ppc_altivec_vmsumshm: // llvm.ppc.altivec. vmsumshm	case Intrinsic::ppc_altivec_vmsumshm: // llvm.ppc.altivec. vmsumshm
	case Intrinsic::ppc_altivec_vmsumshs: // llvm.ppc.altivec. vmsumshs	case Intrinsic::ppc_altivec_vmsumshs: // llvm.ppc.altivec. vmsumshs
	case Intrinsic::ppc_altivec_vmsumuhm: // llvm.ppc.altivec. vmsumuhm	case Intrinsic::ppc_altivec_vmsumuhm: // llvm.ppc.altivec. vmsumuhm
	case Intrinsic::ppc_altivec_vmsumuhs: // llvm.ppc.altivec. vmsumuhs	case Intrinsic::ppc_altivec_vmsumuhs: // llvm.ppc.altivec. vmsumuhs

		case Intrinsic::x86_xop_vpmacsswd: // llvm.x86.xop.vpmacsswd
		case Intrinsic::x86_xop_vpmacswd: // llvm.x86.xop.vpmacswd
		case Intrinsic::x86_xop_vpmadcsswd: // llvm.x86.xop.vpmadcsswd
		case Intrinsic::x86_xop_vpmadcswd: // llvm.x86.xop.vpmadcswd
	VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v4i32, MVT::v8i16, MVT::v8i 16, MVT::v4i32);	VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v4i32, MVT::v8i16, MVT::v8i 16, MVT::v4i32);
	break;	break;
	case Intrinsic::spu_si_mpya: // llvm.spu.si.mpya	case Intrinsic::spu_si_mpya: // llvm.spu.si.mpya
	VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v4i32, MVT::v8i16, MVT::v8i 16, MVT::v8i16);	VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v4i32, MVT::v8i16, MVT::v8i 16, MVT::v8i16);
	break;	break;
	case Intrinsic::x86_avx_vextractf128_si_256: // llvm.x86.avx.vext ractf128.si.256	case Intrinsic::x86_avx_vextractf128_si_256: // llvm.x86.avx.vext ractf128.si.256
	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4i32, MVT::v8i32, MVT::i8) ;	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4i32, MVT::v8i32, MVT::i8) ;
	break;	break;

	case Intrinsic::x86_avx_loadu_ps_256: // llvm.x86.avx.load	case Intrinsic::x86_avx2_movntdqa: // llvm.x86.avx2.movntdqa
	u.ps.256	case Intrinsic::x86_avx2_vbroadcasti128: // llvm.x86.avx2.vbr
		oadcasti128
		VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v4i64, MVT::iPTR);
		break;
		case Intrinsic::x86_avx2_maskload_q_256: // llvm.x86.avx2.mas
		kload.q.256
		VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4i64, MVT::iPTR, MVT::v4i6
		4);
		break;
		case Intrinsic::x86_avx2_pmovsxbq: // llvm.x86.avx2.pmovsxbq
		case Intrinsic::x86_avx2_pmovzxbq: // llvm.x86.avx2.pmovzxbq
		VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v4i64, MVT::v16i8);
		break;
		case Intrinsic::x86_avx2_pbroadcastq_256: // llvm.x86.avx2.pbr
		oadcastq.256
		VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v4i64, MVT::v2i64);
		break;
		case Intrinsic::x86_avx2_psad_bw: // llvm.x86.avx2.psad.bw
		VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4i64, MVT::v32i8, MVT::v32
		i8);
		break;
		case Intrinsic::x86_avx2_pmovsxdq: // llvm.x86.avx2.pmovsxdq
		case Intrinsic::x86_avx2_pmovzxdq: // llvm.x86.avx2.pmovzxdq
		VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v4i64, MVT::v4i32);
		break;
		case Intrinsic::x86_avx2_psll_dq: // llvm.x86.avx2.psll.dq
		case Intrinsic::x86_avx2_psll_dq_bs: // llvm.x86.avx2.psll.dq.bs
		case Intrinsic::x86_avx2_pslli_q: // llvm.x86.avx2.pslli.q
		case Intrinsic::x86_avx2_psrl_dq: // llvm.x86.avx2.psrl.dq
		case Intrinsic::x86_avx2_psrl_dq_bs: // llvm.x86.avx2.psrl.dq.bs
		case Intrinsic::x86_avx2_psrli_q: // llvm.x86.avx2.psrli.q
		VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4i64, MVT::v4i64, MVT::i32
		);
		break;
		case Intrinsic::x86_avx2_psll_q: // llvm.x86.avx2.psll.q
		case Intrinsic::x86_avx2_psrl_q: // llvm.x86.avx2.psrl.q
		VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4i64, MVT::v4i64, MVT::v2i
		64);
		break;
		case Intrinsic::x86_avx2_vinserti128: // llvm.x86.avx2.vin
		serti128
		VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v4i64, MVT::v4i64, MVT::v2i
		64, MVT::i8);
		break;
		case Intrinsic::x86_avx2_psllv_q_256: // llvm.x86.avx2.psl
		lv.q.256
		case Intrinsic::x86_avx2_psrlv_q_256: // llvm.x86.avx2.psr
		lv.q.256
		VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4i64, MVT::v4i64, MVT::v4i
		64);
		break;
		case Intrinsic::x86_avx2_vperm2i128: // llvm.x86.avx2.vperm2i128
		VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v4i64, MVT::v4i64, MVT::v4i
		64, MVT::i8);
		break;
		case Intrinsic::x86_xop_vpcmov_256: // llvm.x86.xop.vpcmov.256
		VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v4i64, MVT::v4i64, MVT::v4i
		64, MVT::v4i64);
		break;
		case Intrinsic::x86_avx2_pmovsxwq: // llvm.x86.avx2.pmovsxwq
		case Intrinsic::x86_avx2_pmovzxwq: // llvm.x86.avx2.pmovzxwq
		VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v4i64, MVT::v8i16);
		break;
		case Intrinsic::x86_avx2_pmul_dq: // llvm.x86.avx2.pmul.dq
		case Intrinsic::x86_avx2_pmulu_dq: // llvm.x86.avx2.pmulu.dq
		VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4i64, MVT::v8i32, MVT::v8i
		32);
		break;
		case Intrinsic::x86_avx_vbroadcast_ss_256: // llvm.x86.avx.vbro
		adcast.ss.256
	case Intrinsic::x86_avx_vbroadcastf128_ps_256: // llvm.x86. avx.vbroadcastf128.ps.256	case Intrinsic::x86_avx_vbroadcastf128_ps_256: // llvm.x86. avx.vbroadcastf128.ps.256

	case Intrinsic::x86_avx_vbroadcastss_256: // llvm.x86.avx.vbro adcastss.256
	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v8f32, MVT::iPTR);	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v8f32, MVT::iPTR);
	break;	break;
	case Intrinsic::x86_avx_maskload_ps_256: // llvm.x86.avx.mask load.ps.256	case Intrinsic::x86_avx_maskload_ps_256: // llvm.x86.avx.mask load.ps.256
	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v8f32, MVT::iPTR, MVT::v8f3 2);	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v8f32, MVT::iPTR, MVT::v8f3 2);
	break;	break;

		case Intrinsic::x86_avx2_vbroadcast_ss_ps_256: // llvm.x86.
		avx2.vbroadcast.ss.ps.256
		VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v8f32, MVT::v4f32);
		break;
	case Intrinsic::x86_avx_rcp_ps_256: // llvm.x86.avx.rcp.ps.256	case Intrinsic::x86_avx_rcp_ps_256: // llvm.x86.avx.rcp.ps.256
	case Intrinsic::x86_avx_rsqrt_ps_256: // llvm.x86.avx.rsqr t.ps.256	case Intrinsic::x86_avx_rsqrt_ps_256: // llvm.x86.avx.rsqr t.ps.256
	case Intrinsic::x86_avx_sqrt_ps_256: // llvm.x86.avx.sqrt.ps.256	case Intrinsic::x86_avx_sqrt_ps_256: // llvm.x86.avx.sqrt.ps.256

		case Intrinsic::x86_xop_vfrcz_ps_256: // llvm.x86.xop.vfrc z.ps.256
	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v8f32, MVT::v8f32);	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v8f32, MVT::v8f32);
	break;	break;
	case Intrinsic::x86_avx_round_ps_256: // llvm.x86.avx.roun d.ps.256	case Intrinsic::x86_avx_round_ps_256: // llvm.x86.avx.roun d.ps.256
	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v8f32, MVT::v8f32, MVT::i32 );	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v8f32, MVT::v8f32, MVT::i32 );
	break;	break;

	case Intrinsic::x86_avx_vpermil_ps_256: // llvm.x86.avx.vper
	mil.ps.256
	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v8f32, MVT::v8f32, MVT::i8)
	;
	break;
	case Intrinsic::x86_avx_vinsertf128_ps_256: // llvm.x86.avx.vins ertf128.ps.256	case Intrinsic::x86_avx_vinsertf128_ps_256: // llvm.x86.avx.vins ertf128.ps.256
	VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v8f32, MVT::v8f32, MVT::v4f 32, MVT::i8);	VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v8f32, MVT::v8f32, MVT::v4f 32, MVT::i8);
	break;	break;

		case Intrinsic::x86_avx2_permps: // llvm.x86.avx2.permps
	case Intrinsic::x86_avx_addsub_ps_256: // llvm.x86.avx.adds ub.ps.256	case Intrinsic::x86_avx_addsub_ps_256: // llvm.x86.avx.adds ub.ps.256
	case Intrinsic::x86_avx_hadd_ps_256: // llvm.x86.avx.hadd.ps.256	case Intrinsic::x86_avx_hadd_ps_256: // llvm.x86.avx.hadd.ps.256
	case Intrinsic::x86_avx_hsub_ps_256: // llvm.x86.avx.hsub.ps.256	case Intrinsic::x86_avx_hsub_ps_256: // llvm.x86.avx.hsub.ps.256
	case Intrinsic::x86_avx_max_ps_256: // llvm.x86.avx.max.ps.256	case Intrinsic::x86_avx_max_ps_256: // llvm.x86.avx.max.ps.256
	case Intrinsic::x86_avx_min_ps_256: // llvm.x86.avx.min.ps.256	case Intrinsic::x86_avx_min_ps_256: // llvm.x86.avx.min.ps.256
	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v8f32, MVT::v8f32, MVT::v8f 32);	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v8f32, MVT::v8f32, MVT::v8f 32);
	break;	break;
	case Intrinsic::x86_avx_blend_ps_256: // llvm.x86.avx.blen d.ps.256	case Intrinsic::x86_avx_blend_ps_256: // llvm.x86.avx.blen d.ps.256
	case Intrinsic::x86_avx_dp_ps_256: // llvm.x86.avx.dp.ps.256	case Intrinsic::x86_avx_dp_ps_256: // llvm.x86.avx.dp.ps.256
	VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v8f32, MVT::v8f32, MVT::v8f 32, MVT::i32);	VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v8f32, MVT::v8f32, MVT::v8f 32, MVT::i32);
	break;	break;
	case Intrinsic::x86_avx_cmp_ps_256: // llvm.x86.avx.cmp.ps.256	case Intrinsic::x86_avx_cmp_ps_256: // llvm.x86.avx.cmp.ps.256
	case Intrinsic::x86_avx_vperm2f128_ps_256: // llvm.x86.avx.vper m2f128.ps.256	case Intrinsic::x86_avx_vperm2f128_ps_256: // llvm.x86.avx.vper m2f128.ps.256
	VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v8f32, MVT::v8f32, MVT::v8f 32, MVT::i8);	VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v8f32, MVT::v8f32, MVT::v8f 32, MVT::i8);
	break;	break;
	case Intrinsic::x86_avx_blendv_ps_256: // llvm.x86.avx.blen dv.ps.256	case Intrinsic::x86_avx_blendv_ps_256: // llvm.x86.avx.blen dv.ps.256

		case Intrinsic::x86_fma4_vfmadd_ps_256: // llvm.x86.fma4.vfm
		add.ps.256
		case Intrinsic::x86_fma4_vfmaddsub_ps_256: // llvm.x86.fma4.vfm
		addsub.ps.256
		case Intrinsic::x86_fma4_vfmsub_ps_256: // llvm.x86.fma4.vfm
		sub.ps.256
		case Intrinsic::x86_fma4_vfmsubadd_ps_256: // llvm.x86.fma4.vfm
		subadd.ps.256
		case Intrinsic::x86_fma4_vfnmadd_ps_256: // llvm.x86.fma4.vfn
		madd.ps.256
		case Intrinsic::x86_fma4_vfnmsub_ps_256: // llvm.x86.fma4.vfn
		msub.ps.256
	VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v8f32, MVT::v8f32, MVT::v8f 32, MVT::v8f32);	VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v8f32, MVT::v8f32, MVT::v8f 32, MVT::v8f32);
	break;	break;

		case Intrinsic::x86_xop_vpermil2ps_256: // llvm.x86.xop.vper
		mil2ps.256
		VerifyIntrinsicPrototype(ID, IF, 1, 4, MVT::v8f32, MVT::v8f32, MVT::v8f
		32, MVT::v8f32, MVT::i8);
		break;
	case Intrinsic::x86_avx_vpermilvar_ps_256: // llvm.x86.avx.vper milvar.ps.256	case Intrinsic::x86_avx_vpermilvar_ps_256: // llvm.x86.avx.vper milvar.ps.256
	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v8f32, MVT::v8f32, MVT::v8i 32);	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v8f32, MVT::v8f32, MVT::v8i 32);
	break;	break;

		case Intrinsic::x86_vcvtph2ps_256: // llvm.x86.vcvtph2ps.256
		VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v8f32, MVT::v8i16);
		break;
	case Intrinsic::x86_avx_cvtdq2_ps_256: // llvm.x86.avx.cvtd q2.ps.256	case Intrinsic::x86_avx_cvtdq2_ps_256: // llvm.x86.avx.cvtd q2.ps.256
	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v8f32, MVT::v8i32);	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v8f32, MVT::v8i32);
	break;	break;
	case Intrinsic::ppc_altivec_mfvscr: // llvm.ppc.altivec.mfvscr	case Intrinsic::ppc_altivec_mfvscr: // llvm.ppc.altivec.mfvscr
	VerifyIntrinsicPrototype(ID, IF, 1, 0, MVT::v8i16);	VerifyIntrinsicPrototype(ID, IF, 1, 0, MVT::v8i16);
	break;	break;
	case Intrinsic::ppc_altivec_lvehx: // llvm.ppc.altivec.lvehx	case Intrinsic::ppc_altivec_lvehx: // llvm.ppc.altivec.lvehx
	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v8i16, MVT::iPTR);	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v8i16, MVT::iPTR);
	break;	break;
	case Intrinsic::ppc_altivec_vupkhsb: // llvm.ppc.altivec.vupkhsb	case Intrinsic::ppc_altivec_vupkhsb: // llvm.ppc.altivec.vupkhsb
	case Intrinsic::ppc_altivec_vupklsb: // llvm.ppc.altivec.vupklsb	case Intrinsic::ppc_altivec_vupklsb: // llvm.ppc.altivec.vupklsb
	case Intrinsic::x86_sse41_pmovsxbw: // llvm.x86.sse41.pmovsxbw	case Intrinsic::x86_sse41_pmovsxbw: // llvm.x86.sse41.pmovsxbw
	case Intrinsic::x86_sse41_pmovzxbw: // llvm.x86.sse41.pmovzxbw	case Intrinsic::x86_sse41_pmovzxbw: // llvm.x86.sse41.pmovzxbw

		case Intrinsic::x86_xop_vphaddbw: // llvm.x86.xop.vphaddbw
		case Intrinsic::x86_xop_vphaddubw: // llvm.x86.xop.vphaddubw
		case Intrinsic::x86_xop_vphsubbw: // llvm.x86.xop.vphsubbw
	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v8i16, MVT::v16i8);	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v8i16, MVT::v16i8);
	break;	break;
	case Intrinsic::ppc_altivec_vmulesb: // llvm.ppc.altivec.vmulesb	case Intrinsic::ppc_altivec_vmulesb: // llvm.ppc.altivec.vmulesb
	case Intrinsic::ppc_altivec_vmuleub: // llvm.ppc.altivec.vmuleub	case Intrinsic::ppc_altivec_vmuleub: // llvm.ppc.altivec.vmuleub
	case Intrinsic::ppc_altivec_vmulosb: // llvm.ppc.altivec.vmulosb	case Intrinsic::ppc_altivec_vmulosb: // llvm.ppc.altivec.vmulosb
	case Intrinsic::ppc_altivec_vmuloub: // llvm.ppc.altivec.vmuloub	case Intrinsic::ppc_altivec_vmuloub: // llvm.ppc.altivec.vmuloub

		case Intrinsic::x86_ssse3_pmadd_ub_sw_128: // llvm.x86.ssse3.pm add.ub.sw.128
	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v8i16, MVT::v16i8, MVT::v16 i8);	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v8i16, MVT::v16i8, MVT::v16 i8);
	break;	break;

		case Intrinsic::x86_sse41_mpsadbw: // llvm.x86.sse41.mpsadbw
		VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v8i16, MVT::v16i8, MVT::v16
		i8, MVT::i32);
		break;
		case Intrinsic::x86_vcvtps2ph_128: // llvm.x86.vcvtps2ph.128
		VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v8i16, MVT::v4f32, MVT::i32
		);
		break;
	case Intrinsic::ppc_altivec_vpkpx: // llvm.ppc.altivec.vpkpx	case Intrinsic::ppc_altivec_vpkpx: // llvm.ppc.altivec.vpkpx
	case Intrinsic::ppc_altivec_vpkswus: // llvm.ppc.altivec.vpkswus	case Intrinsic::ppc_altivec_vpkswus: // llvm.ppc.altivec.vpkswus
	case Intrinsic::ppc_altivec_vpkuwus: // llvm.ppc.altivec.vpkuwus	case Intrinsic::ppc_altivec_vpkuwus: // llvm.ppc.altivec.vpkuwus
	case Intrinsic::x86_sse2_packssdw_128: // llvm.x86.sse2.pac kssdw.128	case Intrinsic::x86_sse2_packssdw_128: // llvm.x86.sse2.pac kssdw.128
	case Intrinsic::x86_sse41_packusdw: // llvm.x86.sse41.packusdw	case Intrinsic::x86_sse41_packusdw: // llvm.x86.sse41.packusdw
	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v8i16, MVT::v4i32, MVT::v4i 32);	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v8i16, MVT::v4i32, MVT::v4i 32);
	break;	break;

		case Intrinsic::x86_vcvtps2ph_256: // llvm.x86.vcvtps2ph.256
		VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v8i16, MVT::v8f32, MVT::i32
		);
		break;
		case Intrinsic::x86_avx2_pbroadcastw_128: // llvm.x86.avx2.pbr
		oadcastw.128
	case Intrinsic::x86_sse41_phminposuw: // llvm.x86.sse41.ph minposuw	case Intrinsic::x86_sse41_phminposuw: // llvm.x86.sse41.ph minposuw
	case Intrinsic::x86_ssse3_pabs_w_128: // llvm.x86.ssse3.pa bs.w.128	case Intrinsic::x86_ssse3_pabs_w_128: // llvm.x86.ssse3.pa bs.w.128
	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v8i16, MVT::v8i16);	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v8i16, MVT::v8i16);
	break;	break;
	case Intrinsic::spu_si_ahi: // llvm.spu.si.ahi	case Intrinsic::spu_si_ahi: // llvm.spu.si.ahi
	case Intrinsic::spu_si_andhi: // llvm.spu.si.andhi	case Intrinsic::spu_si_andhi: // llvm.spu.si.andhi
	case Intrinsic::spu_si_ceqhi: // llvm.spu.si.ceqhi	case Intrinsic::spu_si_ceqhi: // llvm.spu.si.ceqhi
	case Intrinsic::spu_si_cgthi: // llvm.spu.si.cgthi	case Intrinsic::spu_si_cgthi: // llvm.spu.si.cgthi
	case Intrinsic::spu_si_clgthi: // llvm.spu.si.clgthi	case Intrinsic::spu_si_clgthi: // llvm.spu.si.clgthi
	case Intrinsic::spu_si_fsmbi: // llvm.spu.si.fsmbi	case Intrinsic::spu_si_fsmbi: // llvm.spu.si.fsmbi

	skipping to change at line 10221	skipping to change at line 19455
	case Intrinsic::ppc_altivec_vsubshs: // llvm.ppc.altivec.vsubshs	case Intrinsic::ppc_altivec_vsubshs: // llvm.ppc.altivec.vsubshs
	case Intrinsic::ppc_altivec_vsubuhs: // llvm.ppc.altivec.vsubuhs	case Intrinsic::ppc_altivec_vsubuhs: // llvm.ppc.altivec.vsubuhs
	case Intrinsic::spu_si_ah: // llvm.spu.si.ah	case Intrinsic::spu_si_ah: // llvm.spu.si.ah
	case Intrinsic::spu_si_ceqh: // llvm.spu.si.ceqh	case Intrinsic::spu_si_ceqh: // llvm.spu.si.ceqh
	case Intrinsic::spu_si_cgth: // llvm.spu.si.cgth	case Intrinsic::spu_si_cgth: // llvm.spu.si.cgth
	case Intrinsic::spu_si_clgth: // llvm.spu.si.clgth	case Intrinsic::spu_si_clgth: // llvm.spu.si.clgth
	case Intrinsic::spu_si_sfh: // llvm.spu.si.sfh	case Intrinsic::spu_si_sfh: // llvm.spu.si.sfh
	case Intrinsic::x86_sse2_padds_w: // llvm.x86.sse2.padds.w	case Intrinsic::x86_sse2_padds_w: // llvm.x86.sse2.padds.w
	case Intrinsic::x86_sse2_paddus_w: // llvm.x86.sse2.paddus.w	case Intrinsic::x86_sse2_paddus_w: // llvm.x86.sse2.paddus.w
	case Intrinsic::x86_sse2_pavg_w: // llvm.x86.sse2.pavg.w	case Intrinsic::x86_sse2_pavg_w: // llvm.x86.sse2.pavg.w

	case Intrinsic::x86_sse2_pcmpeq_w: // llvm.x86.sse2.pcmpeq.w
	case Intrinsic::x86_sse2_pcmpgt_w: // llvm.x86.sse2.pcmpgt.w
	case Intrinsic::x86_sse2_pmaxs_w: // llvm.x86.sse2.pmaxs.w	case Intrinsic::x86_sse2_pmaxs_w: // llvm.x86.sse2.pmaxs.w
	case Intrinsic::x86_sse2_pmins_w: // llvm.x86.sse2.pmins.w	case Intrinsic::x86_sse2_pmins_w: // llvm.x86.sse2.pmins.w
	case Intrinsic::x86_sse2_pmulh_w: // llvm.x86.sse2.pmulh.w	case Intrinsic::x86_sse2_pmulh_w: // llvm.x86.sse2.pmulh.w
	case Intrinsic::x86_sse2_pmulhu_w: // llvm.x86.sse2.pmulhu.w	case Intrinsic::x86_sse2_pmulhu_w: // llvm.x86.sse2.pmulhu.w
	case Intrinsic::x86_sse2_psll_w: // llvm.x86.sse2.psll.w	case Intrinsic::x86_sse2_psll_w: // llvm.x86.sse2.psll.w
	case Intrinsic::x86_sse2_psra_w: // llvm.x86.sse2.psra.w	case Intrinsic::x86_sse2_psra_w: // llvm.x86.sse2.psra.w
	case Intrinsic::x86_sse2_psrl_w: // llvm.x86.sse2.psrl.w	case Intrinsic::x86_sse2_psrl_w: // llvm.x86.sse2.psrl.w
	case Intrinsic::x86_sse2_psubs_w: // llvm.x86.sse2.psubs.w	case Intrinsic::x86_sse2_psubs_w: // llvm.x86.sse2.psubs.w
	case Intrinsic::x86_sse2_psubus_w: // llvm.x86.sse2.psubus.w	case Intrinsic::x86_sse2_psubus_w: // llvm.x86.sse2.psubus.w
	case Intrinsic::x86_sse41_pmaxuw: // llvm.x86.sse41.pmaxuw	case Intrinsic::x86_sse41_pmaxuw: // llvm.x86.sse41.pmaxuw
	case Intrinsic::x86_sse41_pminuw: // llvm.x86.sse41.pminuw	case Intrinsic::x86_sse41_pminuw: // llvm.x86.sse41.pminuw

		case Intrinsic::x86_ssse3_phadd_sw_128: // llvm.x86.ssse3.ph add.sw.128
	case Intrinsic::x86_ssse3_phadd_w_128: // llvm.x86.ssse3.ph add.w.128	case Intrinsic::x86_ssse3_phadd_w_128: // llvm.x86.ssse3.ph add.w.128
	case Intrinsic::x86_ssse3_phsub_sw_128: // llvm.x86.ssse3.ph sub.sw.128	case Intrinsic::x86_ssse3_phsub_sw_128: // llvm.x86.ssse3.ph sub.sw.128
	case Intrinsic::x86_ssse3_phsub_w_128: // llvm.x86.ssse3.ph sub.w.128	case Intrinsic::x86_ssse3_phsub_w_128: // llvm.x86.ssse3.ph sub.w.128

	case Intrinsic::x86_ssse3_pmadd_ub_sw_128: // llvm.x86.ssse3.pm add.ub.sw.128
	case Intrinsic::x86_ssse3_pmul_hr_sw_128: // llvm.x86.ssse3.pm ul.hr.sw.128	case Intrinsic::x86_ssse3_pmul_hr_sw_128: // llvm.x86.ssse3.pm ul.hr.sw.128
	case Intrinsic::x86_ssse3_psign_w_128: // llvm.x86.ssse3.ps ign.w.128	case Intrinsic::x86_ssse3_psign_w_128: // llvm.x86.ssse3.ps ign.w.128

		case Intrinsic::x86_xop_vpcomequw: // llvm.x86.xop.vpcomequw
		case Intrinsic::x86_xop_vpcomeqw: // llvm.x86.xop.vpcomeqw
		case Intrinsic::x86_xop_vpcomfalseuw: // llvm.x86.xop.vpco
		mfalseuw
		case Intrinsic::x86_xop_vpcomfalsew: // llvm.x86.xop.vpcomfalsew
		case Intrinsic::x86_xop_vpcomgeuw: // llvm.x86.xop.vpcomgeuw
		case Intrinsic::x86_xop_vpcomgew: // llvm.x86.xop.vpcomgew
		case Intrinsic::x86_xop_vpcomgtuw: // llvm.x86.xop.vpcomgtuw
		case Intrinsic::x86_xop_vpcomgtw: // llvm.x86.xop.vpcomgtw
		case Intrinsic::x86_xop_vpcomleuw: // llvm.x86.xop.vpcomleuw
		case Intrinsic::x86_xop_vpcomlew: // llvm.x86.xop.vpcomlew
		case Intrinsic::x86_xop_vpcomltuw: // llvm.x86.xop.vpcomltuw
		case Intrinsic::x86_xop_vpcomltw: // llvm.x86.xop.vpcomltw
		case Intrinsic::x86_xop_vpcomneuw: // llvm.x86.xop.vpcomneuw
		case Intrinsic::x86_xop_vpcomnew: // llvm.x86.xop.vpcomnew
		case Intrinsic::x86_xop_vpcomtrueuw: // llvm.x86.xop.vpcomtrueuw
		case Intrinsic::x86_xop_vpcomtruew: // llvm.x86.xop.vpcomtruew
		case Intrinsic::x86_xop_vprotw: // llvm.x86.xop.vprotw
		case Intrinsic::x86_xop_vpshaw: // llvm.x86.xop.vpshaw
		case Intrinsic::x86_xop_vpshlw: // llvm.x86.xop.vpshlw
	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v8i16, MVT::v8i16, MVT::v8i 16);	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v8i16, MVT::v8i16, MVT::v8i 16);
	break;	break;
	case Intrinsic::x86_sse41_pblendw: // llvm.x86.sse41.pblendw	case Intrinsic::x86_sse41_pblendw: // llvm.x86.sse41.pblendw
	VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v8i16, MVT::v8i16, MVT::v8i 16, MVT::i32);	VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v8i16, MVT::v8i16, MVT::v8i 16, MVT::i32);
	break;	break;
	case Intrinsic::ppc_altivec_vmhaddshs: // llvm.ppc.altivec. vmhaddshs	case Intrinsic::ppc_altivec_vmhaddshs: // llvm.ppc.altivec. vmhaddshs
	case Intrinsic::ppc_altivec_vmhraddshs: // llvm.ppc.altivec. vmhraddshs	case Intrinsic::ppc_altivec_vmhraddshs: // llvm.ppc.altivec. vmhraddshs
	case Intrinsic::ppc_altivec_vmladduhm: // llvm.ppc.altivec. vmladduhm	case Intrinsic::ppc_altivec_vmladduhm: // llvm.ppc.altivec. vmladduhm

		case Intrinsic::x86_xop_vpmacssww: // llvm.x86.xop.vpmacssww
		case Intrinsic::x86_xop_vpmacsww: // llvm.x86.xop.vpmacsww
	VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v8i16, MVT::v8i16, MVT::v8i 16, MVT::v8i16);	VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v8i16, MVT::v8i16, MVT::v8i 16, MVT::v8i16);
	break;	break;

		case Intrinsic::x86_avx2_maskload_d_256: // llvm.x86.avx2.mas
		kload.d.256
		VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v8i32, MVT::iPTR, MVT::v8i3
		2);
		break;
		case Intrinsic::x86_avx2_pmadd_wd: // llvm.x86.avx2.pmadd.wd
		VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v8i32, MVT::v16i16, MVT::v1
		6i16);
		break;
		case Intrinsic::x86_avx2_pmovsxbd: // llvm.x86.avx2.pmovsxbd
		case Intrinsic::x86_avx2_pmovzxbd: // llvm.x86.avx2.pmovzxbd
		VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v8i32, MVT::v16i8);
		break;
		case Intrinsic::x86_avx2_pbroadcastd_256: // llvm.x86.avx2.pbr
		oadcastd.256
		VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v8i32, MVT::v4i32);
		break;
	case Intrinsic::x86_avx_cvt_ps2dq_256: // llvm.x86.avx.cvt. ps2dq.256	case Intrinsic::x86_avx_cvt_ps2dq_256: // llvm.x86.avx.cvt. ps2dq.256
	case Intrinsic::x86_avx_cvtt_ps2dq_256: // llvm.x86.avx.cvtt .ps2dq.256	case Intrinsic::x86_avx_cvtt_ps2dq_256: // llvm.x86.avx.cvtt .ps2dq.256
	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v8i32, MVT::v8f32);	VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v8i32, MVT::v8f32);
	break;	break;

		case Intrinsic::x86_avx2_pmovsxwd: // llvm.x86.avx2.pmovsxwd
		case Intrinsic::x86_avx2_pmovzxwd: // llvm.x86.avx2.pmovzxwd
		VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v8i32, MVT::v8i16);
		break;
		case Intrinsic::x86_avx2_pabs_d: // llvm.x86.avx2.pabs.d
		VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v8i32, MVT::v8i32);
		break;
		case Intrinsic::x86_avx2_pslli_d: // llvm.x86.avx2.pslli.d
		case Intrinsic::x86_avx2_psrai_d: // llvm.x86.avx2.psrai.d
		case Intrinsic::x86_avx2_psrli_d: // llvm.x86.avx2.psrli.d
		VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v8i32, MVT::v8i32, MVT::i32
		);
		break;
		case Intrinsic::x86_avx2_psll_d: // llvm.x86.avx2.psll.d
		case Intrinsic::x86_avx2_psra_d: // llvm.x86.avx2.psra.d
		case Intrinsic::x86_avx2_psrl_d: // llvm.x86.avx2.psrl.d
		VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v8i32, MVT::v8i32, MVT::v4i
		32);
		break;
	case Intrinsic::x86_avx_vinsertf128_si_256: // llvm.x86.avx.vins ertf128.si.256	case Intrinsic::x86_avx_vinsertf128_si_256: // llvm.x86.avx.vins ertf128.si.256
	VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v8i32, MVT::v8i32, MVT::v4i 32, MVT::i8);	VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v8i32, MVT::v8i32, MVT::v4i 32, MVT::i8);
	break;	break;

		case Intrinsic::x86_avx2_permd: // llvm.x86.avx2.permd
		case Intrinsic::x86_avx2_phadd_d: // llvm.x86.avx2.phadd.d
		case Intrinsic::x86_avx2_phsub_d: // llvm.x86.avx2.phsub.d
		case Intrinsic::x86_avx2_pmaxs_d: // llvm.x86.avx2.pmaxs.d
		case Intrinsic::x86_avx2_pmaxu_d: // llvm.x86.avx2.pmaxu.d
		case Intrinsic::x86_avx2_pmins_d: // llvm.x86.avx2.pmins.d
		case Intrinsic::x86_avx2_pminu_d: // llvm.x86.avx2.pminu.d
		case Intrinsic::x86_avx2_psign_d: // llvm.x86.avx2.psign.d
		case Intrinsic::x86_avx2_psllv_d_256: // llvm.x86.avx2.psl
		lv.d.256
		case Intrinsic::x86_avx2_psrav_d_256: // llvm.x86.avx2.psr
		av.d.256
		case Intrinsic::x86_avx2_psrlv_d_256: // llvm.x86.avx2.psr
		lv.d.256
		VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v8i32, MVT::v8i32, MVT::v8i
		32);
		break;
		case Intrinsic::x86_avx2_pblendd_256: // llvm.x86.avx2.pbl
		endd.256
		VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v8i32, MVT::v8i32, MVT::v8i
		32, MVT::i32);
		break;
	case Intrinsic::x86_avx_vperm2f128_si_256: // llvm.x86.avx.vper m2f128.si.256	case Intrinsic::x86_avx_vperm2f128_si_256: // llvm.x86.avx.vper m2f128.si.256
	VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v8i32, MVT::v8i32, MVT::v8i 32, MVT::i8);	VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v8i32, MVT::v8i32, MVT::v8i 32, MVT::i8);
	break;	break;
	case Intrinsic::arm_neon_vtbl1: // llvm.arm.neon.vtbl1	case Intrinsic::arm_neon_vtbl1: // llvm.arm.neon.vtbl1
	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v8i8, MVT::v8i8, MVT::v8i8) ;	VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v8i8, MVT::v8i8, MVT::v8i8) ;
	break;	break;
	case Intrinsic::arm_neon_vtbl2: // llvm.arm.neon.vtbl2	case Intrinsic::arm_neon_vtbl2: // llvm.arm.neon.vtbl2
	case Intrinsic::arm_neon_vtbx1: // llvm.arm.neon.vtbx1	case Intrinsic::arm_neon_vtbx1: // llvm.arm.neon.vtbx1
	VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v8i8, MVT::v8i8, MVT::v8i8, MVT::v8i8);	VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v8i8, MVT::v8i8, MVT::v8i8, MVT::v8i8);
	break;	break;

	skipping to change at line 10409	skipping to change at line 19708
	break;	break;
	case Intrinsic::x86_mmx_palignr_b: // llvm.x86.mmx.palignr.b	case Intrinsic::x86_mmx_palignr_b: // llvm.x86.mmx.palignr.b
	VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::x86mmx, MVT::x86mmx, MVT::x 86mmx, MVT::i8);	VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::x86mmx, MVT::x86mmx, MVT::x 86mmx, MVT::i8);
	break;	break;
	}	}
	#endif	#endif

	// Code for generating Intrinsic function declarations.	// Code for generating Intrinsic function declarations.
	#ifdef GET_INTRINSIC_GENERATOR	#ifdef GET_INTRINSIC_GENERATOR
	switch (id) {	switch (id) {

	default: assert(0 && "Invalid intrinsic!");	default: llvm_unreachable("Invalid intrinsic!");
	case Intrinsic::eh_unwind_init: // llvm.eh.unwind.init	case Intrinsic::eh_unwind_init: // llvm.eh.unwind.init
	case Intrinsic::ppc_altivec_dssall: // llvm.ppc.altivec.dssall	case Intrinsic::ppc_altivec_dssall: // llvm.ppc.altivec.dssall
	case Intrinsic::ppc_sync: // llvm.ppc.sync	case Intrinsic::ppc_sync: // llvm.ppc.sync
	case Intrinsic::trap: // llvm.trap	case Intrinsic::trap: // llvm.trap
	case Intrinsic::x86_avx_vzeroall: // llvm.x86.avx.vzeroall	case Intrinsic::x86_avx_vzeroall: // llvm.x86.avx.vzeroall
	case Intrinsic::x86_avx_vzeroupper: // llvm.x86.avx.vzeroupper	case Intrinsic::x86_avx_vzeroupper: // llvm.x86.avx.vzeroupper
	case Intrinsic::x86_mmx_emms: // llvm.x86.mmx.emms	case Intrinsic::x86_mmx_emms: // llvm.x86.mmx.emms
	case Intrinsic::x86_mmx_femms: // llvm.x86.mmx.femms	case Intrinsic::x86_mmx_femms: // llvm.x86.mmx.femms
	case Intrinsic::x86_sse2_lfence: // llvm.x86.sse2.lfence	case Intrinsic::x86_sse2_lfence: // llvm.x86.sse2.lfence
	case Intrinsic::x86_sse2_mfence: // llvm.x86.sse2.mfence	case Intrinsic::x86_sse2_mfence: // llvm.x86.sse2.mfence

	skipping to change at line 10488	skipping to change at line 19787
	ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));	ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
	break;	break;
	case Intrinsic::invariant_end: // llvm.invariant.end	case Intrinsic::invariant_end: // llvm.invariant.end
	ResultTy = Type::getVoidTy(Context);	ResultTy = Type::getVoidTy(Context);
	ArgTys.push_back(PointerType::getUnqual(StructType::get(Context)));	ArgTys.push_back(PointerType::getUnqual(StructType::get(Context)));
	ArgTys.push_back(IntegerType::get(Context, 64));	ArgTys.push_back(IntegerType::get(Context, 64));
	ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));	ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
	break;	break;
	case Intrinsic::arm_set_fpscr: // llvm.arm.set.fpscr	case Intrinsic::arm_set_fpscr: // llvm.arm.set.fpscr
	case Intrinsic::eh_sjlj_callsite: // llvm.eh.sjlj.callsite	case Intrinsic::eh_sjlj_callsite: // llvm.eh.sjlj.callsite

	case Intrinsic::eh_sjlj_dispatch_setup: // llvm.eh.sjlj.disp atch.setup
	case Intrinsic::pcmarker: // llvm.pcmarker	case Intrinsic::pcmarker: // llvm.pcmarker
	case Intrinsic::ppc_altivec_dss: // llvm.ppc.altivec.dss	case Intrinsic::ppc_altivec_dss: // llvm.ppc.altivec.dss
	case Intrinsic::ptx_bar_sync: // llvm.ptx.bar.sync	case Intrinsic::ptx_bar_sync: // llvm.ptx.bar.sync

		case Intrinsic::x86_wrfsbase_32: // llvm.x86.wrfsbase.32
		case Intrinsic::x86_wrgsbase_32: // llvm.x86.wrgsbase.32
	case Intrinsic::xcore_clrsr: // llvm.xcore.clrsr	case Intrinsic::xcore_clrsr: // llvm.xcore.clrsr
	case Intrinsic::xcore_setsr: // llvm.xcore.setsr	case Intrinsic::xcore_setsr: // llvm.xcore.setsr
	ResultTy = Type::getVoidTy(Context);	ResultTy = Type::getVoidTy(Context);
	ArgTys.push_back(IntegerType::get(Context, 32));	ArgTys.push_back(IntegerType::get(Context, 32));
	break;	break;
	case Intrinsic::x86_sse3_mwait: // llvm.x86.sse3.mwait	case Intrinsic::x86_sse3_mwait: // llvm.x86.sse3.mwait
	case Intrinsic::xcore_setps: // llvm.xcore.setps	case Intrinsic::xcore_setps: // llvm.xcore.setps
	ResultTy = Type::getVoidTy(Context);	ResultTy = Type::getVoidTy(Context);
	ArgTys.push_back(IntegerType::get(Context, 32));	ArgTys.push_back(IntegerType::get(Context, 32));
	ArgTys.push_back(IntegerType::get(Context, 32));	ArgTys.push_back(IntegerType::get(Context, 32));

	skipping to change at line 10529	skipping to change at line 19829
	ArgTys.push_back(IntegerType::get(Context, 32));	ArgTys.push_back(IntegerType::get(Context, 32));
	ArgTys.push_back(IntegerType::get(Context, 32));	ArgTys.push_back(IntegerType::get(Context, 32));
	ArgTys.push_back(IntegerType::get(Context, 32));	ArgTys.push_back(IntegerType::get(Context, 32));
	ArgTys.push_back(IntegerType::get(Context, 32));	ArgTys.push_back(IntegerType::get(Context, 32));
	break;	break;
	case Intrinsic::eh_return_i32: // llvm.eh.return.i32	case Intrinsic::eh_return_i32: // llvm.eh.return.i32
	ResultTy = Type::getVoidTy(Context);	ResultTy = Type::getVoidTy(Context);
	ArgTys.push_back(IntegerType::get(Context, 32));	ArgTys.push_back(IntegerType::get(Context, 32));
	ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));	ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
	break;	break;

		case Intrinsic::x86_wrfsbase_64: // llvm.x86.wrfsbase.64
		case Intrinsic::x86_wrgsbase_64: // llvm.x86.wrgsbase.64
		ResultTy = Type::getVoidTy(Context);
		ArgTys.push_back(IntegerType::get(Context, 64));
		break;
	case Intrinsic::eh_return_i64: // llvm.eh.return.i64	case Intrinsic::eh_return_i64: // llvm.eh.return.i64
	case Intrinsic::lifetime_end: // llvm.lifetime.end	case Intrinsic::lifetime_end: // llvm.lifetime.end
	case Intrinsic::lifetime_start: // llvm.lifetime.start	case Intrinsic::lifetime_start: // llvm.lifetime.start
	ResultTy = Type::getVoidTy(Context);	ResultTy = Type::getVoidTy(Context);
	ArgTys.push_back(IntegerType::get(Context, 64));	ArgTys.push_back(IntegerType::get(Context, 64));
	ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));	ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
	break;	break;
	case Intrinsic::x86_int: // llvm.x86.int	case Intrinsic::x86_int: // llvm.x86.int
	ResultTy = Type::getVoidTy(Context);	ResultTy = Type::getVoidTy(Context);
	ArgTys.push_back(IntegerType::get(Context, 8));	ArgTys.push_back(IntegerType::get(Context, 8));

	skipping to change at line 10627	skipping to change at line 19932
	ArgTys.push_back(Tys[0]);	ArgTys.push_back(Tys[0]);
	ArgTys.push_back(IntegerType::get(Context, 32));	ArgTys.push_back(IntegerType::get(Context, 32));
	ArgTys.push_back(IntegerType::get(Context, 32));	ArgTys.push_back(IntegerType::get(Context, 32));
	break;	break;
	case Intrinsic::arm_neon_vst1: // llvm.arm.neon.vst1	case Intrinsic::arm_neon_vst1: // llvm.arm.neon.vst1
	ResultTy = Type::getVoidTy(Context);	ResultTy = Type::getVoidTy(Context);
	ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));	ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
	ArgTys.push_back(Tys[0]);	ArgTys.push_back(Tys[0]);
	ArgTys.push_back(IntegerType::get(Context, 32));	ArgTys.push_back(IntegerType::get(Context, 32));
	break;	break;

	case Intrinsic::eh_resume: // llvm.eh.resume
	case Intrinsic::longjmp: // llvm.longjmp	case Intrinsic::longjmp: // llvm.longjmp
	case Intrinsic::siglongjmp: // llvm.siglongjmp	case Intrinsic::siglongjmp: // llvm.siglongjmp
	ResultTy = Type::getVoidTy(Context);	ResultTy = Type::getVoidTy(Context);
	ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));	ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
	ArgTys.push_back(IntegerType::get(Context, 32));	ArgTys.push_back(IntegerType::get(Context, 32));
	break;	break;
	case Intrinsic::ppc_altivec_dst: // llvm.ppc.altivec.dst	case Intrinsic::ppc_altivec_dst: // llvm.ppc.altivec.dst
	case Intrinsic::ppc_altivec_dstst: // llvm.ppc.altivec.dstst	case Intrinsic::ppc_altivec_dstst: // llvm.ppc.altivec.dstst
	case Intrinsic::ppc_altivec_dststt: // llvm.ppc.altivec.dststt	case Intrinsic::ppc_altivec_dststt: // llvm.ppc.altivec.dststt
	case Intrinsic::ppc_altivec_dstt: // llvm.ppc.altivec.dstt	case Intrinsic::ppc_altivec_dstt: // llvm.ppc.altivec.dstt

	skipping to change at line 10696	skipping to change at line 20000
	ResultTy = Type::getVoidTy(Context);	ResultTy = Type::getVoidTy(Context);
	ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));	ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
	break;	break;
	case Intrinsic::x86_avx_maskstore_pd: // llvm.x86.avx.mask store.pd	case Intrinsic::x86_avx_maskstore_pd: // llvm.x86.avx.mask store.pd
	ResultTy = Type::getVoidTy(Context);	ResultTy = Type::getVoidTy(Context);
	ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));	ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
	break;	break;

		case Intrinsic::x86_avx2_maskstore_q: // llvm.x86.avx2.mas
		kstore.q
		ResultTy = Type::getVoidTy(Context);
		ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 2));
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 2));
		break;
	case Intrinsic::x86_avx_storeu_dq_256: // llvm.x86.avx.stor eu.dq.256	case Intrinsic::x86_avx_storeu_dq_256: // llvm.x86.avx.stor eu.dq.256
	ResultTy = Type::getVoidTy(Context);	ResultTy = Type::getVoidTy(Context);
	ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));	ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 32));	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 32));
	break;	break;
	case Intrinsic::x86_sse_storeu_ps: // llvm.x86.sse.storeu.ps	case Intrinsic::x86_sse_storeu_ps: // llvm.x86.sse.storeu.ps
	ResultTy = Type::getVoidTy(Context);	ResultTy = Type::getVoidTy(Context);
	ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));	ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
	break;	break;

	skipping to change at line 10729	skipping to change at line 20039
	ResultTy = Type::getVoidTy(Context);	ResultTy = Type::getVoidTy(Context);
	ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));	ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 4));	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 4));
	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 4));	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 4));
	break;	break;
	case Intrinsic::x86_sse2_storel_dq: // llvm.x86.sse2.storel.dq	case Intrinsic::x86_sse2_storel_dq: // llvm.x86.sse2.storel.dq
	ResultTy = Type::getVoidTy(Context);	ResultTy = Type::getVoidTy(Context);
	ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));	ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
	break;	break;

		case Intrinsic::x86_avx2_maskstore_d: // llvm.x86.avx2.mas
		kstore.d
		ResultTy = Type::getVoidTy(Context);
		ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
		break;
	case Intrinsic::x86_avx_movnt_dq_256: // llvm.x86.avx.movn t.dq.256	case Intrinsic::x86_avx_movnt_dq_256: // llvm.x86.avx.movn t.dq.256
	ResultTy = Type::getVoidTy(Context);	ResultTy = Type::getVoidTy(Context);
	ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));	ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 4));	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 4));
	break;	break;

		case Intrinsic::x86_avx2_maskstore_q_256: // llvm.x86.avx2.mas
		kstore.q.256
		ResultTy = Type::getVoidTy(Context);
		ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 4));
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 4));
		break;
	case Intrinsic::x86_avx_movnt_ps_256: // llvm.x86.avx.movn t.ps.256	case Intrinsic::x86_avx_movnt_ps_256: // llvm.x86.avx.movn t.ps.256
	case Intrinsic::x86_avx_storeu_ps_256: // llvm.x86.avx.stor eu.ps.256	case Intrinsic::x86_avx_storeu_ps_256: // llvm.x86.avx.stor eu.ps.256
	ResultTy = Type::getVoidTy(Context);	ResultTy = Type::getVoidTy(Context);
	ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));	ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 8));	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 8));
	break;	break;
	case Intrinsic::x86_avx_maskstore_ps_256: // llvm.x86.avx.mask store.ps.256	case Intrinsic::x86_avx_maskstore_ps_256: // llvm.x86.avx.mask store.ps.256
	ResultTy = Type::getVoidTy(Context);	ResultTy = Type::getVoidTy(Context);
	ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));	ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 8));	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 8));
	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 8));	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 8));
	break;	break;

		case Intrinsic::x86_avx2_maskstore_d_256: // llvm.x86.avx2.mas
		kstore.d.256
		ResultTy = Type::getVoidTy(Context);
		ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 8));
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 8));
		break;
	case Intrinsic::gcroot: // llvm.gcroot	case Intrinsic::gcroot: // llvm.gcroot
	ResultTy = Type::getVoidTy(Context);	ResultTy = Type::getVoidTy(Context);
	ArgTys.push_back(PointerType::getUnqual(PointerType::getUnqual(IntegerT ype::get(Context, 8))));	ArgTys.push_back(PointerType::getUnqual(PointerType::getUnqual(IntegerT ype::get(Context, 8))));
	ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));	ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
	break;	break;
	case Intrinsic::x86_mmx_movnt_dq: // llvm.x86.mmx.movnt.dq	case Intrinsic::x86_mmx_movnt_dq: // llvm.x86.mmx.movnt.dq
	ResultTy = Type::getVoidTy(Context);	ResultTy = Type::getVoidTy(Context);
	ArgTys.push_back(PointerType::getUnqual(Type::getX86_MMXTy(Context)));	ArgTys.push_back(PointerType::getUnqual(Type::getX86_MMXTy(Context)));
	ArgTys.push_back(Type::getX86_MMXTy(Context));	ArgTys.push_back(Type::getX86_MMXTy(Context));
	break;	break;

	skipping to change at line 10879	skipping to change at line 20207
	ResultTy = Tys[0];	ResultTy = Tys[0];
	ArgTys.push_back(Tys[0]);	ArgTys.push_back(Tys[0]);
	break;	break;
	case Intrinsic::ctpop: // llvm.ctpop	case Intrinsic::ctpop: // llvm.ctpop
	ResultTy = Tys[0];	ResultTy = Tys[0];
	ArgTys.push_back(Tys[0]);	ArgTys.push_back(Tys[0]);
	break;	break;
	case Intrinsic::ctlz: // llvm.ctlz	case Intrinsic::ctlz: // llvm.ctlz
	ResultTy = Tys[0];	ResultTy = Tys[0];
	ArgTys.push_back(Tys[0]);	ArgTys.push_back(Tys[0]);

		ArgTys.push_back(IntegerType::get(Context, 1));
	break;	break;
	case Intrinsic::cttz: // llvm.cttz	case Intrinsic::cttz: // llvm.cttz
	ResultTy = Tys[0];	ResultTy = Tys[0];
	ArgTys.push_back(Tys[0]);	ArgTys.push_back(Tys[0]);

		ArgTys.push_back(IntegerType::get(Context, 1));
	break;	break;
	case Intrinsic::annotation: // llvm.annotation	case Intrinsic::annotation: // llvm.annotation
	ResultTy = Tys[0];	ResultTy = Tys[0];
	ArgTys.push_back(Tys[0]);	ArgTys.push_back(Tys[0]);
	ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));	ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
	ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));	ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
	ArgTys.push_back(IntegerType::get(Context, 32));	ArgTys.push_back(IntegerType::get(Context, 32));
	break;	break;
	case Intrinsic::arm_neon_vcvtfp2fxs: // llvm.arm.neon.vcvtfp2fxs	case Intrinsic::arm_neon_vcvtfp2fxs: // llvm.arm.neon.vcvtfp2fxs
	case Intrinsic::arm_neon_vcvtfp2fxu: // llvm.arm.neon.vcvtfp2fxu	case Intrinsic::arm_neon_vcvtfp2fxu: // llvm.arm.neon.vcvtfp2fxu

	skipping to change at line 11131	skipping to change at line 20461
	ArgTys.push_back(Tys[0]);	ArgTys.push_back(Tys[0]);
	break;	break;
	case Intrinsic::convert_from_fp16: // llvm.convert.from.fp16	case Intrinsic::convert_from_fp16: // llvm.convert.from.fp16
	ResultTy = Type::getFloatTy(Context);	ResultTy = Type::getFloatTy(Context);
	ArgTys.push_back(IntegerType::get(Context, 16));	ArgTys.push_back(IntegerType::get(Context, 16));
	break;	break;
	case Intrinsic::convert_to_fp16: // llvm.convert.to.fp16	case Intrinsic::convert_to_fp16: // llvm.convert.to.fp16
	ResultTy = IntegerType::get(Context, 16);	ResultTy = IntegerType::get(Context, 16);
	ArgTys.push_back(Type::getFloatTy(Context));	ArgTys.push_back(Type::getFloatTy(Context));
	break;	break;

		case Intrinsic::hexagon_C2_all8: // llvm.hexagon.C2.all8
		case Intrinsic::hexagon_C2_any8: // llvm.hexagon.C2.any8
		case Intrinsic::hexagon_C2_not: // llvm.hexagon.C2.not
		case Intrinsic::hexagon_C2_pxfer_map: // llvm.hexagon.C2.p
		xfer.map
		case Intrinsic::hexagon_C2_tfrrp: // llvm.hexagon.C2.tfrrp
		ResultTy = IntegerType::get(Context, 1);
		ArgTys.push_back(IntegerType::get(Context, 32));
		break;
		case Intrinsic::hexagon_C2_and: // llvm.hexagon.C2.and
		case Intrinsic::hexagon_C2_andn: // llvm.hexagon.C2.andn
		case Intrinsic::hexagon_C2_bitsclr: // llvm.hexagon.C2.bitsclr
		case Intrinsic::hexagon_C2_bitsclri: // llvm.hexagon.C2.bitsclri
		case Intrinsic::hexagon_C2_bitsset: // llvm.hexagon.C2.bitsset
		case Intrinsic::hexagon_C2_cmpeq: // llvm.hexagon.C2.cmpeq
		case Intrinsic::hexagon_C2_cmpeqi: // llvm.hexagon.C2.cmpeqi
		case Intrinsic::hexagon_C2_cmpgei: // llvm.hexagon.C2.cmpgei
		case Intrinsic::hexagon_C2_cmpgeui: // llvm.hexagon.C2.cmpgeui
		case Intrinsic::hexagon_C2_cmpgt: // llvm.hexagon.C2.cmpgt
		case Intrinsic::hexagon_C2_cmpgti: // llvm.hexagon.C2.cmpgti
		case Intrinsic::hexagon_C2_cmpgtu: // llvm.hexagon.C2.cmpgtu
		case Intrinsic::hexagon_C2_cmpgtui: // llvm.hexagon.C2.cmpgtui
		case Intrinsic::hexagon_C2_cmplt: // llvm.hexagon.C2.cmplt
		case Intrinsic::hexagon_C2_cmpltu: // llvm.hexagon.C2.cmpltu
		case Intrinsic::hexagon_C2_or: // llvm.hexagon.C2.or
		case Intrinsic::hexagon_C2_orn: // llvm.hexagon.C2.orn
		case Intrinsic::hexagon_C2_xor: // llvm.hexagon.C2.xor
		case Intrinsic::hexagon_C4_cmplte: // llvm.hexagon.C4.cmplte
		case Intrinsic::hexagon_C4_cmpltei: // llvm.hexagon.C4.cmpltei
		case Intrinsic::hexagon_C4_cmplteu: // llvm.hexagon.C4.cmplteu
		case Intrinsic::hexagon_C4_cmplteui: // llvm.hexagon.C4.cmplteui
		case Intrinsic::hexagon_C4_cmpneq: // llvm.hexagon.C4.cmpneq
		case Intrinsic::hexagon_C4_cmpneqi: // llvm.hexagon.C4.cmpneqi
		case Intrinsic::hexagon_C4_fastcorner9: // llvm.hexagon.C4.f
		astcorner9
		case Intrinsic::hexagon_C4_fastcorner9_not: // llvm.hexagon.C4.f
		astcorner9.not
		case Intrinsic::hexagon_S2_tstbit_i: // llvm.hexagon.S2.tstbit.i
		case Intrinsic::hexagon_S2_tstbit_r: // llvm.hexagon.S2.tstbit.r
		ResultTy = IntegerType::get(Context, 1);
		ArgTys.push_back(IntegerType::get(Context, 32));
		ArgTys.push_back(IntegerType::get(Context, 32));
		break;
		case Intrinsic::hexagon_C4_and_and: // llvm.hexagon.C4.and.and
		case Intrinsic::hexagon_C4_and_andn: // llvm.hexagon.C4.and.andn
		case Intrinsic::hexagon_C4_and_or: // llvm.hexagon.C4.and.or
		case Intrinsic::hexagon_C4_and_orn: // llvm.hexagon.C4.and.orn
		case Intrinsic::hexagon_C4_or_and: // llvm.hexagon.C4.or.and
		case Intrinsic::hexagon_C4_or_andn: // llvm.hexagon.C4.or.andn
		case Intrinsic::hexagon_C4_or_or: // llvm.hexagon.C4.or.or
		case Intrinsic::hexagon_C4_or_orn: // llvm.hexagon.C4.or.orn
		ResultTy = IntegerType::get(Context, 1);
		ArgTys.push_back(IntegerType::get(Context, 32));
		ArgTys.push_back(IntegerType::get(Context, 32));
		ArgTys.push_back(IntegerType::get(Context, 32));
		break;
		case Intrinsic::hexagon_A2_vcmpbeq: // llvm.hexagon.A2.vcmpbeq
		case Intrinsic::hexagon_A2_vcmpbgtu: // llvm.hexagon.A2.vcmpbgtu
		case Intrinsic::hexagon_A2_vcmpheq: // llvm.hexagon.A2.vcmpheq
		case Intrinsic::hexagon_A2_vcmphgt: // llvm.hexagon.A2.vcmphgt
		case Intrinsic::hexagon_A2_vcmphgtu: // llvm.hexagon.A2.vcmphgtu
		case Intrinsic::hexagon_A2_vcmpweq: // llvm.hexagon.A2.vcmpweq
		case Intrinsic::hexagon_A2_vcmpwgt: // llvm.hexagon.A2.vcmpwgt
		case Intrinsic::hexagon_A2_vcmpwgtu: // llvm.hexagon.A2.vcmpwgtu
		case Intrinsic::hexagon_C2_cmpeqp: // llvm.hexagon.C2.cmpeqp
		case Intrinsic::hexagon_C2_cmpgtp: // llvm.hexagon.C2.cmpgtp
		case Intrinsic::hexagon_C2_cmpgtup: // llvm.hexagon.C2.cmpgtup
		ResultTy = IntegerType::get(Context, 1);
		ArgTys.push_back(IntegerType::get(Context, 64));
		ArgTys.push_back(IntegerType::get(Context, 64));
		break;
	case Intrinsic::arm_get_fpscr: // llvm.arm.get.fpscr	case Intrinsic::arm_get_fpscr: // llvm.arm.get.fpscr
	case Intrinsic::flt_rounds: // llvm.flt.rounds	case Intrinsic::flt_rounds: // llvm.flt.rounds
	case Intrinsic::ptx_read_clock: // llvm.ptx.read.clock	case Intrinsic::ptx_read_clock: // llvm.ptx.read.clock
	case Intrinsic::ptx_read_ctaid_w: // llvm.ptx.read.ctaid.w	case Intrinsic::ptx_read_ctaid_w: // llvm.ptx.read.ctaid.w
	case Intrinsic::ptx_read_ctaid_x: // llvm.ptx.read.ctaid.x	case Intrinsic::ptx_read_ctaid_x: // llvm.ptx.read.ctaid.x
	case Intrinsic::ptx_read_ctaid_y: // llvm.ptx.read.ctaid.y	case Intrinsic::ptx_read_ctaid_y: // llvm.ptx.read.ctaid.y
	case Intrinsic::ptx_read_ctaid_z: // llvm.ptx.read.ctaid.z	case Intrinsic::ptx_read_ctaid_z: // llvm.ptx.read.ctaid.z
	case Intrinsic::ptx_read_gridid: // llvm.ptx.read.gridid	case Intrinsic::ptx_read_gridid: // llvm.ptx.read.gridid
	case Intrinsic::ptx_read_laneid: // llvm.ptx.read.laneid	case Intrinsic::ptx_read_laneid: // llvm.ptx.read.laneid
	case Intrinsic::ptx_read_lanemask_eq: // llvm.ptx.read.lan emask.eq	case Intrinsic::ptx_read_lanemask_eq: // llvm.ptx.read.lan emask.eq

	skipping to change at line 11165	skipping to change at line 20563
	case Intrinsic::ptx_read_pm0: // llvm.ptx.read.pm0	case Intrinsic::ptx_read_pm0: // llvm.ptx.read.pm0
	case Intrinsic::ptx_read_pm1: // llvm.ptx.read.pm1	case Intrinsic::ptx_read_pm1: // llvm.ptx.read.pm1
	case Intrinsic::ptx_read_pm2: // llvm.ptx.read.pm2	case Intrinsic::ptx_read_pm2: // llvm.ptx.read.pm2
	case Intrinsic::ptx_read_pm3: // llvm.ptx.read.pm3	case Intrinsic::ptx_read_pm3: // llvm.ptx.read.pm3
	case Intrinsic::ptx_read_smid: // llvm.ptx.read.smid	case Intrinsic::ptx_read_smid: // llvm.ptx.read.smid
	case Intrinsic::ptx_read_tid_w: // llvm.ptx.read.tid.w	case Intrinsic::ptx_read_tid_w: // llvm.ptx.read.tid.w
	case Intrinsic::ptx_read_tid_x: // llvm.ptx.read.tid.x	case Intrinsic::ptx_read_tid_x: // llvm.ptx.read.tid.x
	case Intrinsic::ptx_read_tid_y: // llvm.ptx.read.tid.y	case Intrinsic::ptx_read_tid_y: // llvm.ptx.read.tid.y
	case Intrinsic::ptx_read_tid_z: // llvm.ptx.read.tid.z	case Intrinsic::ptx_read_tid_z: // llvm.ptx.read.tid.z
	case Intrinsic::ptx_read_warpid: // llvm.ptx.read.warpid	case Intrinsic::ptx_read_warpid: // llvm.ptx.read.warpid

		case Intrinsic::x86_rdfsbase_32: // llvm.x86.rdfsbase.32
		case Intrinsic::x86_rdgsbase_32: // llvm.x86.rdgsbase.32
	case Intrinsic::xcore_geted: // llvm.xcore.geted	case Intrinsic::xcore_geted: // llvm.xcore.geted
	case Intrinsic::xcore_getet: // llvm.xcore.getet	case Intrinsic::xcore_getet: // llvm.xcore.getet
	case Intrinsic::xcore_getid: // llvm.xcore.getid	case Intrinsic::xcore_getid: // llvm.xcore.getid
	ResultTy = IntegerType::get(Context, 32);	ResultTy = IntegerType::get(Context, 32);
	break;	break;
	case Intrinsic::xcore_endin: // llvm.xcore.endin	case Intrinsic::xcore_endin: // llvm.xcore.endin
	case Intrinsic::xcore_getts: // llvm.xcore.getts	case Intrinsic::xcore_getts: // llvm.xcore.getts
	case Intrinsic::xcore_in: // llvm.xcore.in	case Intrinsic::xcore_in: // llvm.xcore.in
	case Intrinsic::xcore_inct: // llvm.xcore.inct	case Intrinsic::xcore_inct: // llvm.xcore.inct
	case Intrinsic::xcore_int: // llvm.xcore.int	case Intrinsic::xcore_int: // llvm.xcore.int

	skipping to change at line 11187	skipping to change at line 20587
	case Intrinsic::xcore_testwct: // llvm.xcore.testwct	case Intrinsic::xcore_testwct: // llvm.xcore.testwct
	ResultTy = IntegerType::get(Context, 32);	ResultTy = IntegerType::get(Context, 32);
	ArgTys.push_back((0 < Tys.size()) ? Tys[0] : PointerType::getUnqual(Int egerType::get(Context, 8)));	ArgTys.push_back((0 < Tys.size()) ? Tys[0] : PointerType::getUnqual(Int egerType::get(Context, 8)));
	break;	break;
	case Intrinsic::xcore_inshr: // llvm.xcore.inshr	case Intrinsic::xcore_inshr: // llvm.xcore.inshr
	case Intrinsic::xcore_outshr: // llvm.xcore.outshr	case Intrinsic::xcore_outshr: // llvm.xcore.outshr
	ResultTy = IntegerType::get(Context, 32);	ResultTy = IntegerType::get(Context, 32);
	ArgTys.push_back((0 < Tys.size()) ? Tys[0] : PointerType::getUnqual(Int egerType::get(Context, 8)));	ArgTys.push_back((0 < Tys.size()) ? Tys[0] : PointerType::getUnqual(Int egerType::get(Context, 8)));
	ArgTys.push_back(IntegerType::get(Context, 32));	ArgTys.push_back(IntegerType::get(Context, 32));
	break;	break;

		case Intrinsic::hexagon_A2_abs: // llvm.hexagon.A2.abs
		case Intrinsic::hexagon_A2_abssat: // llvm.hexagon.A2.abssat
		case Intrinsic::hexagon_A2_aslh: // llvm.hexagon.A2.aslh
		case Intrinsic::hexagon_A2_asrh: // llvm.hexagon.A2.asrh
		case Intrinsic::hexagon_A2_neg: // llvm.hexagon.A2.neg
		case Intrinsic::hexagon_A2_negsat: // llvm.hexagon.A2.negsat
		case Intrinsic::hexagon_A2_not: // llvm.hexagon.A2.not
		case Intrinsic::hexagon_A2_satb: // llvm.hexagon.A2.satb
		case Intrinsic::hexagon_A2_sath: // llvm.hexagon.A2.sath
		case Intrinsic::hexagon_A2_satub: // llvm.hexagon.A2.satub
		case Intrinsic::hexagon_A2_satuh: // llvm.hexagon.A2.satuh
		case Intrinsic::hexagon_A2_swiz: // llvm.hexagon.A2.swiz
		case Intrinsic::hexagon_A2_sxtb: // llvm.hexagon.A2.sxtb
		case Intrinsic::hexagon_A2_sxth: // llvm.hexagon.A2.sxth
		case Intrinsic::hexagon_A2_tfr: // llvm.hexagon.A2.tfr
		case Intrinsic::hexagon_A2_tfrsi: // llvm.hexagon.A2.tfrsi
		case Intrinsic::hexagon_A2_zxtb: // llvm.hexagon.A2.zxtb
		case Intrinsic::hexagon_A2_zxth: // llvm.hexagon.A2.zxth
		case Intrinsic::hexagon_C2_tfrpr: // llvm.hexagon.C2.tfrpr
		case Intrinsic::hexagon_S2_brev: // llvm.hexagon.S2.brev
		case Intrinsic::hexagon_S2_cl0: // llvm.hexagon.S2.cl0
		case Intrinsic::hexagon_S2_cl1: // llvm.hexagon.S2.cl1
		case Intrinsic::hexagon_S2_clb: // llvm.hexagon.S2.clb
		case Intrinsic::hexagon_S2_clbnorm: // llvm.hexagon.S2.clbnorm
		case Intrinsic::hexagon_S2_ct0: // llvm.hexagon.S2.ct0
		case Intrinsic::hexagon_S2_ct1: // llvm.hexagon.S2.ct1
		case Intrinsic::hexagon_S2_svsathb: // llvm.hexagon.S2.svsathb
		case Intrinsic::hexagon_S2_svsathub: // llvm.hexagon.S2.svsathub
		case Intrinsic::hexagon_S2_vsplatrb: // llvm.hexagon.S2.vsplatrb
		case Intrinsic::hexagon_SI_to_SXTHI_asrh: // llvm.hexagon.SI.t
		o.SXTHI.asrh
	case Intrinsic::xcore_bitrev: // llvm.xcore.bitrev	case Intrinsic::xcore_bitrev: // llvm.xcore.bitrev
	case Intrinsic::xcore_getps: // llvm.xcore.getps	case Intrinsic::xcore_getps: // llvm.xcore.getps
	ResultTy = IntegerType::get(Context, 32);	ResultTy = IntegerType::get(Context, 32);
	ArgTys.push_back(IntegerType::get(Context, 32));	ArgTys.push_back(IntegerType::get(Context, 32));
	break;	break;
	case Intrinsic::x86_sse42_crc32_32_16: // llvm.x86.sse42.cr c32.32.16	case Intrinsic::x86_sse42_crc32_32_16: // llvm.x86.sse42.cr c32.32.16
	ResultTy = IntegerType::get(Context, 32);	ResultTy = IntegerType::get(Context, 32);
	ArgTys.push_back(IntegerType::get(Context, 32));	ArgTys.push_back(IntegerType::get(Context, 32));
	ArgTys.push_back(IntegerType::get(Context, 16));	ArgTys.push_back(IntegerType::get(Context, 16));
	break;	break;
	case Intrinsic::arm_qadd: // llvm.arm.qadd	case Intrinsic::arm_qadd: // llvm.arm.qadd
	case Intrinsic::arm_qsub: // llvm.arm.qsub	case Intrinsic::arm_qsub: // llvm.arm.qsub
	case Intrinsic::arm_ssat: // llvm.arm.ssat	case Intrinsic::arm_ssat: // llvm.arm.ssat
	case Intrinsic::arm_usat: // llvm.arm.usat	case Intrinsic::arm_usat: // llvm.arm.usat

		case Intrinsic::hexagon_A2_add: // llvm.hexagon.A2.add
		case Intrinsic::hexagon_A2_addh_h16_hh: // llvm.hexagon.A2.a
		ddh.h16.hh
		case Intrinsic::hexagon_A2_addh_h16_hl: // llvm.hexagon.A2.a
		ddh.h16.hl
		case Intrinsic::hexagon_A2_addh_h16_lh: // llvm.hexagon.A2.a
		ddh.h16.lh
		case Intrinsic::hexagon_A2_addh_h16_ll: // llvm.hexagon.A2.a
		ddh.h16.ll
		case Intrinsic::hexagon_A2_addh_h16_sat_hh: // llvm.hexagon.A2.a
		ddh.h16.sat.hh
		case Intrinsic::hexagon_A2_addh_h16_sat_hl: // llvm.hexagon.A2.a
		ddh.h16.sat.hl
		case Intrinsic::hexagon_A2_addh_h16_sat_lh: // llvm.hexagon.A2.a
		ddh.h16.sat.lh
		case Intrinsic::hexagon_A2_addh_h16_sat_ll: // llvm.hexagon.A2.a
		ddh.h16.sat.ll
		case Intrinsic::hexagon_A2_addh_l16_hh: // llvm.hexagon.A2.a
		ddh.l16.hh
		case Intrinsic::hexagon_A2_addh_l16_hl: // llvm.hexagon.A2.a
		ddh.l16.hl
		case Intrinsic::hexagon_A2_addh_l16_lh: // llvm.hexagon.A2.a
		ddh.l16.lh
		case Intrinsic::hexagon_A2_addh_l16_ll: // llvm.hexagon.A2.a
		ddh.l16.ll
		case Intrinsic::hexagon_A2_addh_l16_sat_hh: // llvm.hexagon.A2.a
		ddh.l16.sat.hh
		case Intrinsic::hexagon_A2_addh_l16_sat_hl: // llvm.hexagon.A2.a
		ddh.l16.sat.hl
		case Intrinsic::hexagon_A2_addh_l16_sat_lh: // llvm.hexagon.A2.a
		ddh.l16.sat.lh
		case Intrinsic::hexagon_A2_addh_l16_sat_ll: // llvm.hexagon.A2.a
		ddh.l16.sat.ll
		case Intrinsic::hexagon_A2_addi: // llvm.hexagon.A2.addi
		case Intrinsic::hexagon_A2_addsat: // llvm.hexagon.A2.addsat
		case Intrinsic::hexagon_A2_and: // llvm.hexagon.A2.and
		case Intrinsic::hexagon_A2_andir: // llvm.hexagon.A2.andir
		case Intrinsic::hexagon_A2_combine_hh: // llvm.hexagon.A2.c
		ombine.hh
		case Intrinsic::hexagon_A2_combine_hl: // llvm.hexagon.A2.c
		ombine.hl
		case Intrinsic::hexagon_A2_combine_lh: // llvm.hexagon.A2.c
		ombine.lh
		case Intrinsic::hexagon_A2_combine_ll: // llvm.hexagon.A2.c
		ombine.ll
		case Intrinsic::hexagon_A2_max: // llvm.hexagon.A2.max
		case Intrinsic::hexagon_A2_maxu: // llvm.hexagon.A2.maxu
		case Intrinsic::hexagon_A2_min: // llvm.hexagon.A2.min
		case Intrinsic::hexagon_A2_minu: // llvm.hexagon.A2.minu
		case Intrinsic::hexagon_A2_or: // llvm.hexagon.A2.or
		case Intrinsic::hexagon_A2_orir: // llvm.hexagon.A2.orir
		case Intrinsic::hexagon_A2_sub: // llvm.hexagon.A2.sub
		case Intrinsic::hexagon_A2_subh_h16_hh: // llvm.hexagon.A2.s
		ubh.h16.hh
		case Intrinsic::hexagon_A2_subh_h16_hl: // llvm.hexagon.A2.s
		ubh.h16.hl
		case Intrinsic::hexagon_A2_subh_h16_lh: // llvm.hexagon.A2.s
		ubh.h16.lh
		case Intrinsic::hexagon_A2_subh_h16_ll: // llvm.hexagon.A2.s
		ubh.h16.ll
		case Intrinsic::hexagon_A2_subh_h16_sat_hh: // llvm.hexagon.A2.s
		ubh.h16.sat.hh
		case Intrinsic::hexagon_A2_subh_h16_sat_hl: // llvm.hexagon.A2.s
		ubh.h16.sat.hl
		case Intrinsic::hexagon_A2_subh_h16_sat_lh: // llvm.hexagon.A2.s
		ubh.h16.sat.lh
		case Intrinsic::hexagon_A2_subh_h16_sat_ll: // llvm.hexagon.A2.s
		ubh.h16.sat.ll
		case Intrinsic::hexagon_A2_subh_l16_hl: // llvm.hexagon.A2.s
		ubh.l16.hl
		case Intrinsic::hexagon_A2_subh_l16_ll: // llvm.hexagon.A2.s
		ubh.l16.ll
		case Intrinsic::hexagon_A2_subh_l16_sat_hl: // llvm.hexagon.A2.s
		ubh.l16.sat.hl
		case Intrinsic::hexagon_A2_subh_l16_sat_ll: // llvm.hexagon.A2.s
		ubh.l16.sat.ll
		case Intrinsic::hexagon_A2_subri: // llvm.hexagon.A2.subri
		case Intrinsic::hexagon_A2_subsat: // llvm.hexagon.A2.subsat
		case Intrinsic::hexagon_A2_svaddh: // llvm.hexagon.A2.svaddh
		case Intrinsic::hexagon_A2_svaddhs: // llvm.hexagon.A2.svaddhs
		case Intrinsic::hexagon_A2_svadduhs: // llvm.hexagon.A2.svadduhs
		case Intrinsic::hexagon_A2_svavgh: // llvm.hexagon.A2.svavgh
		case Intrinsic::hexagon_A2_svavghs: // llvm.hexagon.A2.svavghs
		case Intrinsic::hexagon_A2_svnavgh: // llvm.hexagon.A2.svnavgh
		case Intrinsic::hexagon_A2_svsubh: // llvm.hexagon.A2.svsubh
		case Intrinsic::hexagon_A2_svsubhs: // llvm.hexagon.A2.svsubhs
		case Intrinsic::hexagon_A2_svsubuhs: // llvm.hexagon.A2.svsubuhs
		case Intrinsic::hexagon_A2_tfrih: // llvm.hexagon.A2.tfrih
		case Intrinsic::hexagon_A2_tfril: // llvm.hexagon.A2.tfril
		case Intrinsic::hexagon_A2_xor: // llvm.hexagon.A2.xor
		case Intrinsic::hexagon_A4_andn: // llvm.hexagon.A4.andn
		case Intrinsic::hexagon_A4_cround_ri: // llvm.hexagon.A4.c
		round.ri
		case Intrinsic::hexagon_A4_cround_rr: // llvm.hexagon.A4.c
		round.rr
		case Intrinsic::hexagon_A4_modwrapu: // llvm.hexagon.A4.modwrapu
		case Intrinsic::hexagon_A4_orn: // llvm.hexagon.A4.orn
		case Intrinsic::hexagon_A4_rcmpeq: // llvm.hexagon.A4.rcmpeq
		case Intrinsic::hexagon_A4_rcmpeqi: // llvm.hexagon.A4.rcmpeqi
		case Intrinsic::hexagon_A4_rcmpneq: // llvm.hexagon.A4.rcmpneq
		case Intrinsic::hexagon_A4_rcmpneqi: // llvm.hexagon.A4.rcmpneqi
		case Intrinsic::hexagon_A4_round_ri: // llvm.hexagon.A4.round.ri
		case Intrinsic::hexagon_A4_round_ri_sat: // llvm.hexagon.A4.r
		ound.ri.sat
		case Intrinsic::hexagon_A4_round_rr: // llvm.hexagon.A4.round.rr
		case Intrinsic::hexagon_A4_round_rr_sat: // llvm.hexagon.A4.r
		ound.rr.sat
		case Intrinsic::hexagon_C2_vitpack: // llvm.hexagon.C2.vitpack
		case Intrinsic::hexagon_M2_cmpyrs_s0: // llvm.hexagon.M2.c
		mpyrs.s0
		case Intrinsic::hexagon_M2_cmpyrs_s1: // llvm.hexagon.M2.c
		mpyrs.s1
		case Intrinsic::hexagon_M2_cmpyrsc_s0: // llvm.hexagon.M2.c
		mpyrsc.s0
		case Intrinsic::hexagon_M2_cmpyrsc_s1: // llvm.hexagon.M2.c
		mpyrsc.s1
		case Intrinsic::hexagon_M2_dpmpyss_rnd_s0: // llvm.hexagon.M2.d
		pmpyss.rnd.s0
		case Intrinsic::hexagon_M2_hmmpyh_rs1: // llvm.hexagon.M2.h
		mmpyh.rs1
		case Intrinsic::hexagon_M2_hmmpyl_rs1: // llvm.hexagon.M2.h
		mmpyl.rs1
		case Intrinsic::hexagon_M2_mpy_hh_s0: // llvm.hexagon.M2.m
		py.hh.s0
		case Intrinsic::hexagon_M2_mpy_hh_s1: // llvm.hexagon.M2.m
		py.hh.s1
		case Intrinsic::hexagon_M2_mpy_hl_s0: // llvm.hexagon.M2.m
		py.hl.s0
		case Intrinsic::hexagon_M2_mpy_hl_s1: // llvm.hexagon.M2.m
		py.hl.s1
		case Intrinsic::hexagon_M2_mpy_lh_s0: // llvm.hexagon.M2.m
		py.lh.s0
		case Intrinsic::hexagon_M2_mpy_lh_s1: // llvm.hexagon.M2.m
		py.lh.s1
		case Intrinsic::hexagon_M2_mpy_ll_s0: // llvm.hexagon.M2.m
		py.ll.s0
		case Intrinsic::hexagon_M2_mpy_ll_s1: // llvm.hexagon.M2.m
		py.ll.s1
		case Intrinsic::hexagon_M2_mpy_rnd_hh_s0: // llvm.hexagon.M2.m
		py.rnd.hh.s0
		case Intrinsic::hexagon_M2_mpy_rnd_hh_s1: // llvm.hexagon.M2.m
		py.rnd.hh.s1
		case Intrinsic::hexagon_M2_mpy_rnd_hl_s0: // llvm.hexagon.M2.m
		py.rnd.hl.s0
		case Intrinsic::hexagon_M2_mpy_rnd_hl_s1: // llvm.hexagon.M2.m
		py.rnd.hl.s1
		case Intrinsic::hexagon_M2_mpy_rnd_lh_s0: // llvm.hexagon.M2.m
		py.rnd.lh.s0
		case Intrinsic::hexagon_M2_mpy_rnd_lh_s1: // llvm.hexagon.M2.m
		py.rnd.lh.s1
		case Intrinsic::hexagon_M2_mpy_rnd_ll_s0: // llvm.hexagon.M2.m
		py.rnd.ll.s0
		case Intrinsic::hexagon_M2_mpy_rnd_ll_s1: // llvm.hexagon.M2.m
		py.rnd.ll.s1
		case Intrinsic::hexagon_M2_mpy_sat_hh_s0: // llvm.hexagon.M2.m
		py.sat.hh.s0
		case Intrinsic::hexagon_M2_mpy_sat_hh_s1: // llvm.hexagon.M2.m
		py.sat.hh.s1
		case Intrinsic::hexagon_M2_mpy_sat_hl_s0: // llvm.hexagon.M2.m
		py.sat.hl.s0
		case Intrinsic::hexagon_M2_mpy_sat_hl_s1: // llvm.hexagon.M2.m
		py.sat.hl.s1
		case Intrinsic::hexagon_M2_mpy_sat_lh_s0: // llvm.hexagon.M2.m
		py.sat.lh.s0
		case Intrinsic::hexagon_M2_mpy_sat_lh_s1: // llvm.hexagon.M2.m
		py.sat.lh.s1
		case Intrinsic::hexagon_M2_mpy_sat_ll_s0: // llvm.hexagon.M2.m
		py.sat.ll.s0
		case Intrinsic::hexagon_M2_mpy_sat_ll_s1: // llvm.hexagon.M2.m
		py.sat.ll.s1
		case Intrinsic::hexagon_M2_mpy_sat_rnd_hh_s0: // llvm.hexa
		gon.M2.mpy.sat.rnd.hh.s0
		case Intrinsic::hexagon_M2_mpy_sat_rnd_hh_s1: // llvm.hexa
		gon.M2.mpy.sat.rnd.hh.s1
		case Intrinsic::hexagon_M2_mpy_sat_rnd_hl_s0: // llvm.hexa
		gon.M2.mpy.sat.rnd.hl.s0
		case Intrinsic::hexagon_M2_mpy_sat_rnd_hl_s1: // llvm.hexa
		gon.M2.mpy.sat.rnd.hl.s1
		case Intrinsic::hexagon_M2_mpy_sat_rnd_lh_s0: // llvm.hexa
		gon.M2.mpy.sat.rnd.lh.s0
		case Intrinsic::hexagon_M2_mpy_sat_rnd_lh_s1: // llvm.hexa
		gon.M2.mpy.sat.rnd.lh.s1
		case Intrinsic::hexagon_M2_mpy_sat_rnd_ll_s0: // llvm.hexa
		gon.M2.mpy.sat.rnd.ll.s0
		case Intrinsic::hexagon_M2_mpy_sat_rnd_ll_s1: // llvm.hexa
		gon.M2.mpy.sat.rnd.ll.s1
		case Intrinsic::hexagon_M2_mpy_up: // llvm.hexagon.M2.mpy.up
		case Intrinsic::hexagon_M2_mpyi: // llvm.hexagon.M2.mpyi
		case Intrinsic::hexagon_M2_mpysmi: // llvm.hexagon.M2.mpysmi
		case Intrinsic::hexagon_M2_mpyu_hh_s0: // llvm.hexagon.M2.m
		pyu.hh.s0
		case Intrinsic::hexagon_M2_mpyu_hh_s1: // llvm.hexagon.M2.m
		pyu.hh.s1
		case Intrinsic::hexagon_M2_mpyu_hl_s0: // llvm.hexagon.M2.m
		pyu.hl.s0
		case Intrinsic::hexagon_M2_mpyu_hl_s1: // llvm.hexagon.M2.m
		pyu.hl.s1
		case Intrinsic::hexagon_M2_mpyu_lh_s0: // llvm.hexagon.M2.m
		pyu.lh.s0
		case Intrinsic::hexagon_M2_mpyu_lh_s1: // llvm.hexagon.M2.m
		pyu.lh.s1
		case Intrinsic::hexagon_M2_mpyu_ll_s0: // llvm.hexagon.M2.m
		pyu.ll.s0
		case Intrinsic::hexagon_M2_mpyu_ll_s1: // llvm.hexagon.M2.m
		pyu.ll.s1
		case Intrinsic::hexagon_M2_mpyu_up: // llvm.hexagon.M2.mpyu.up
		case Intrinsic::hexagon_M2_mpyui: // llvm.hexagon.M2.mpyui
		case Intrinsic::hexagon_M2_vmpy2s_s0pack: // llvm.hexagon.M2.v
		mpy2s.s0pack
		case Intrinsic::hexagon_M2_vmpy2s_s1pack: // llvm.hexagon.M2.v
		mpy2s.s1pack
		case Intrinsic::hexagon_S2_asl_i_r: // llvm.hexagon.S2.asl.i.r
		case Intrinsic::hexagon_S2_asl_i_r_sat: // llvm.hexagon.S2.a
		sl.i.r.sat
		case Intrinsic::hexagon_S2_asl_r_r: // llvm.hexagon.S2.asl.r.r
		case Intrinsic::hexagon_S2_asl_r_r_sat: // llvm.hexagon.S2.a
		sl.r.r.sat
		case Intrinsic::hexagon_S2_asr_i_r: // llvm.hexagon.S2.asr.i.r
		case Intrinsic::hexagon_S2_asr_i_r_rnd: // llvm.hexagon.S2.a
		sr.i.r.rnd
		case Intrinsic::hexagon_S2_asr_i_r_rnd_goodsyntax: // llvm.hexa
		gon.S2.asr.i.r.rnd.goodsyntax
		case Intrinsic::hexagon_S2_asr_r_r: // llvm.hexagon.S2.asr.r.r
		case Intrinsic::hexagon_S2_asr_r_r_sat: // llvm.hexagon.S2.a
		sr.r.r.sat
		case Intrinsic::hexagon_S2_clrbit_i: // llvm.hexagon.S2.clrbit.i
		case Intrinsic::hexagon_S2_clrbit_r: // llvm.hexagon.S2.clrbit.r
		case Intrinsic::hexagon_S2_lsl_r_r: // llvm.hexagon.S2.lsl.r.r
		case Intrinsic::hexagon_S2_lsr_i_r: // llvm.hexagon.S2.lsr.i.r
		case Intrinsic::hexagon_S2_lsr_r_r: // llvm.hexagon.S2.lsr.r.r
		case Intrinsic::hexagon_S2_setbit_i: // llvm.hexagon.S2.setbit.i
		case Intrinsic::hexagon_S2_setbit_r: // llvm.hexagon.S2.setbit.r
		case Intrinsic::hexagon_S2_togglebit_i: // llvm.hexagon.S2.t
		ogglebit.i
		case Intrinsic::hexagon_S2_togglebit_r: // llvm.hexagon.S2.t
		ogglebit.r
		case Intrinsic::x86_bmi_bextr_32: // llvm.x86.bmi.bextr.32
		case Intrinsic::x86_bmi_bzhi_32: // llvm.x86.bmi.bzhi.32
		case Intrinsic::x86_bmi_pdep_32: // llvm.x86.bmi.pdep.32
		case Intrinsic::x86_bmi_pext_32: // llvm.x86.bmi.pext.32
	case Intrinsic::x86_sse42_crc32_32_32: // llvm.x86.sse42.cr c32.32.32	case Intrinsic::x86_sse42_crc32_32_32: // llvm.x86.sse42.cr c32.32.32
	case Intrinsic::xcore_sext: // llvm.xcore.sext	case Intrinsic::xcore_sext: // llvm.xcore.sext
	case Intrinsic::xcore_zext: // llvm.xcore.zext	case Intrinsic::xcore_zext: // llvm.xcore.zext
	ResultTy = IntegerType::get(Context, 32);	ResultTy = IntegerType::get(Context, 32);
	ArgTys.push_back(IntegerType::get(Context, 32));	ArgTys.push_back(IntegerType::get(Context, 32));
	ArgTys.push_back(IntegerType::get(Context, 32));	ArgTys.push_back(IntegerType::get(Context, 32));
	break;	break;

		case Intrinsic::hexagon_C2_mux: // llvm.hexagon.C2.mux
		case Intrinsic::hexagon_C2_muxii: // llvm.hexagon.C2.muxii
		case Intrinsic::hexagon_C2_muxir: // llvm.hexagon.C2.muxir
		case Intrinsic::hexagon_C2_muxri: // llvm.hexagon.C2.muxri
		case Intrinsic::hexagon_M2_acci: // llvm.hexagon.M2.acci
		case Intrinsic::hexagon_M2_accii: // llvm.hexagon.M2.accii
		case Intrinsic::hexagon_M2_maci: // llvm.hexagon.M2.maci
		case Intrinsic::hexagon_M2_macsin: // llvm.hexagon.M2.macsin
		case Intrinsic::hexagon_M2_macsip: // llvm.hexagon.M2.macsip
		case Intrinsic::hexagon_M2_mpy_acc_hh_s0: // llvm.hexagon.M2.m
		py.acc.hh.s0
		case Intrinsic::hexagon_M2_mpy_acc_hh_s1: // llvm.hexagon.M2.m
		py.acc.hh.s1
		case Intrinsic::hexagon_M2_mpy_acc_hl_s0: // llvm.hexagon.M2.m
		py.acc.hl.s0
		case Intrinsic::hexagon_M2_mpy_acc_hl_s1: // llvm.hexagon.M2.m
		py.acc.hl.s1
		case Intrinsic::hexagon_M2_mpy_acc_lh_s0: // llvm.hexagon.M2.m
		py.acc.lh.s0
		case Intrinsic::hexagon_M2_mpy_acc_lh_s1: // llvm.hexagon.M2.m
		py.acc.lh.s1
		case Intrinsic::hexagon_M2_mpy_acc_ll_s0: // llvm.hexagon.M2.m
		py.acc.ll.s0
		case Intrinsic::hexagon_M2_mpy_acc_ll_s1: // llvm.hexagon.M2.m
		py.acc.ll.s1
		case Intrinsic::hexagon_M2_mpy_acc_sat_hh_s0: // llvm.hexa
		gon.M2.mpy.acc.sat.hh.s0
		case Intrinsic::hexagon_M2_mpy_acc_sat_hh_s1: // llvm.hexa
		gon.M2.mpy.acc.sat.hh.s1
		case Intrinsic::hexagon_M2_mpy_acc_sat_hl_s0: // llvm.hexa
		gon.M2.mpy.acc.sat.hl.s0
		case Intrinsic::hexagon_M2_mpy_acc_sat_hl_s1: // llvm.hexa
		gon.M2.mpy.acc.sat.hl.s1
		case Intrinsic::hexagon_M2_mpy_acc_sat_lh_s0: // llvm.hexa
		gon.M2.mpy.acc.sat.lh.s0
		case Intrinsic::hexagon_M2_mpy_acc_sat_lh_s1: // llvm.hexa
		gon.M2.mpy.acc.sat.lh.s1
		case Intrinsic::hexagon_M2_mpy_acc_sat_ll_s0: // llvm.hexa
		gon.M2.mpy.acc.sat.ll.s0
		case Intrinsic::hexagon_M2_mpy_acc_sat_ll_s1: // llvm.hexa
		gon.M2.mpy.acc.sat.ll.s1
		case Intrinsic::hexagon_M2_mpy_nac_hh_s0: // llvm.hexagon.M2.m
		py.nac.hh.s0
		case Intrinsic::hexagon_M2_mpy_nac_hh_s1: // llvm.hexagon.M2.m
		py.nac.hh.s1
		case Intrinsic::hexagon_M2_mpy_nac_hl_s0: // llvm.hexagon.M2.m
		py.nac.hl.s0
		case Intrinsic::hexagon_M2_mpy_nac_hl_s1: // llvm.hexagon.M2.m
		py.nac.hl.s1
		case Intrinsic::hexagon_M2_mpy_nac_lh_s0: // llvm.hexagon.M2.m
		py.nac.lh.s0
		case Intrinsic::hexagon_M2_mpy_nac_lh_s1: // llvm.hexagon.M2.m
		py.nac.lh.s1
		case Intrinsic::hexagon_M2_mpy_nac_ll_s0: // llvm.hexagon.M2.m
		py.nac.ll.s0
		case Intrinsic::hexagon_M2_mpy_nac_ll_s1: // llvm.hexagon.M2.m
		py.nac.ll.s1
		case Intrinsic::hexagon_M2_mpy_nac_sat_hh_s0: // llvm.hexa
		gon.M2.mpy.nac.sat.hh.s0
		case Intrinsic::hexagon_M2_mpy_nac_sat_hh_s1: // llvm.hexa
		gon.M2.mpy.nac.sat.hh.s1
		case Intrinsic::hexagon_M2_mpy_nac_sat_hl_s0: // llvm.hexa
		gon.M2.mpy.nac.sat.hl.s0
		case Intrinsic::hexagon_M2_mpy_nac_sat_hl_s1: // llvm.hexa
		gon.M2.mpy.nac.sat.hl.s1
		case Intrinsic::hexagon_M2_mpy_nac_sat_lh_s0: // llvm.hexa
		gon.M2.mpy.nac.sat.lh.s0
		case Intrinsic::hexagon_M2_mpy_nac_sat_lh_s1: // llvm.hexa
		gon.M2.mpy.nac.sat.lh.s1
		case Intrinsic::hexagon_M2_mpy_nac_sat_ll_s0: // llvm.hexa
		gon.M2.mpy.nac.sat.ll.s0
		case Intrinsic::hexagon_M2_mpy_nac_sat_ll_s1: // llvm.hexa
		gon.M2.mpy.nac.sat.ll.s1
		case Intrinsic::hexagon_M2_mpyu_acc_hh_s0: // llvm.hexagon.M2.m
		pyu.acc.hh.s0
		case Intrinsic::hexagon_M2_mpyu_acc_hh_s1: // llvm.hexagon.M2.m
		pyu.acc.hh.s1
		case Intrinsic::hexagon_M2_mpyu_acc_hl_s0: // llvm.hexagon.M2.m
		pyu.acc.hl.s0
		case Intrinsic::hexagon_M2_mpyu_acc_hl_s1: // llvm.hexagon.M2.m
		pyu.acc.hl.s1
		case Intrinsic::hexagon_M2_mpyu_acc_lh_s0: // llvm.hexagon.M2.m
		pyu.acc.lh.s0
		case Intrinsic::hexagon_M2_mpyu_acc_lh_s1: // llvm.hexagon.M2.m
		pyu.acc.lh.s1
		case Intrinsic::hexagon_M2_mpyu_acc_ll_s0: // llvm.hexagon.M2.m
		pyu.acc.ll.s0
		case Intrinsic::hexagon_M2_mpyu_acc_ll_s1: // llvm.hexagon.M2.m
		pyu.acc.ll.s1
		case Intrinsic::hexagon_M2_mpyu_nac_hh_s0: // llvm.hexagon.M2.m
		pyu.nac.hh.s0
		case Intrinsic::hexagon_M2_mpyu_nac_hh_s1: // llvm.hexagon.M2.m
		pyu.nac.hh.s1
		case Intrinsic::hexagon_M2_mpyu_nac_hl_s0: // llvm.hexagon.M2.m
		pyu.nac.hl.s0
		case Intrinsic::hexagon_M2_mpyu_nac_hl_s1: // llvm.hexagon.M2.m
		pyu.nac.hl.s1
		case Intrinsic::hexagon_M2_mpyu_nac_lh_s0: // llvm.hexagon.M2.m
		pyu.nac.lh.s0
		case Intrinsic::hexagon_M2_mpyu_nac_lh_s1: // llvm.hexagon.M2.m
		pyu.nac.lh.s1
		case Intrinsic::hexagon_M2_mpyu_nac_ll_s0: // llvm.hexagon.M2.m
		pyu.nac.ll.s0
		case Intrinsic::hexagon_M2_mpyu_nac_ll_s1: // llvm.hexagon.M2.m
		pyu.nac.ll.s1
		case Intrinsic::hexagon_M2_nacci: // llvm.hexagon.M2.nacci
		case Intrinsic::hexagon_M2_naccii: // llvm.hexagon.M2.naccii
		case Intrinsic::hexagon_M2_subacc: // llvm.hexagon.M2.subacc
		case Intrinsic::hexagon_M2_xor_xacc: // llvm.hexagon.M2.xor.xacc
		case Intrinsic::hexagon_M4_and_and: // llvm.hexagon.M4.and.and
		case Intrinsic::hexagon_M4_and_andn: // llvm.hexagon.M4.and.andn
		case Intrinsic::hexagon_M4_and_or: // llvm.hexagon.M4.and.or
		case Intrinsic::hexagon_M4_and_xor: // llvm.hexagon.M4.and.xor
		case Intrinsic::hexagon_M4_or_and: // llvm.hexagon.M4.or.and
		case Intrinsic::hexagon_M4_or_andn: // llvm.hexagon.M4.or.andn
		case Intrinsic::hexagon_M4_or_or: // llvm.hexagon.M4.or.or
		case Intrinsic::hexagon_M4_or_xor: // llvm.hexagon.M4.or.xor
		case Intrinsic::hexagon_M4_xor_and: // llvm.hexagon.M4.xor.and
		case Intrinsic::hexagon_M4_xor_andn: // llvm.hexagon.M4.xor.andn
		case Intrinsic::hexagon_M4_xor_or: // llvm.hexagon.M4.xor.or
		case Intrinsic::hexagon_S2_addasl_rrri: // llvm.hexagon.S2.a
		ddasl.rrri
		case Intrinsic::hexagon_S2_asl_i_r_acc: // llvm.hexagon.S2.a
		sl.i.r.acc
		case Intrinsic::hexagon_S2_asl_i_r_and: // llvm.hexagon.S2.a
		sl.i.r.and
		case Intrinsic::hexagon_S2_asl_i_r_nac: // llvm.hexagon.S2.a
		sl.i.r.nac
		case Intrinsic::hexagon_S2_asl_i_r_or: // llvm.hexagon.S2.a
		sl.i.r.or
		case Intrinsic::hexagon_S2_asl_i_r_xacc: // llvm.hexagon.S2.a
		sl.i.r.xacc
		case Intrinsic::hexagon_S2_asl_r_r_acc: // llvm.hexagon.S2.a
		sl.r.r.acc
		case Intrinsic::hexagon_S2_asl_r_r_and: // llvm.hexagon.S2.a
		sl.r.r.and
		case Intrinsic::hexagon_S2_asl_r_r_nac: // llvm.hexagon.S2.a
		sl.r.r.nac
		case Intrinsic::hexagon_S2_asl_r_r_or: // llvm.hexagon.S2.a
		sl.r.r.or
		case Intrinsic::hexagon_S2_asr_i_r_acc: // llvm.hexagon.S2.a
		sr.i.r.acc
		case Intrinsic::hexagon_S2_asr_i_r_and: // llvm.hexagon.S2.a
		sr.i.r.and
		case Intrinsic::hexagon_S2_asr_i_r_nac: // llvm.hexagon.S2.a
		sr.i.r.nac
		case Intrinsic::hexagon_S2_asr_i_r_or: // llvm.hexagon.S2.a
		sr.i.r.or
		case Intrinsic::hexagon_S2_asr_r_r_acc: // llvm.hexagon.S2.a
		sr.r.r.acc
		case Intrinsic::hexagon_S2_asr_r_r_and: // llvm.hexagon.S2.a
		sr.r.r.and
		case Intrinsic::hexagon_S2_asr_r_r_nac: // llvm.hexagon.S2.a
		sr.r.r.nac
		case Intrinsic::hexagon_S2_asr_r_r_or: // llvm.hexagon.S2.a
		sr.r.r.or
		case Intrinsic::hexagon_S2_extractu: // llvm.hexagon.S2.extractu
		case Intrinsic::hexagon_S2_lsl_r_r_acc: // llvm.hexagon.S2.l
		sl.r.r.acc
		case Intrinsic::hexagon_S2_lsl_r_r_and: // llvm.hexagon.S2.l
		sl.r.r.and
		case Intrinsic::hexagon_S2_lsl_r_r_nac: // llvm.hexagon.S2.l
		sl.r.r.nac
		case Intrinsic::hexagon_S2_lsl_r_r_or: // llvm.hexagon.S2.l
		sl.r.r.or
		case Intrinsic::hexagon_S2_lsr_i_r_acc: // llvm.hexagon.S2.l
		sr.i.r.acc
		case Intrinsic::hexagon_S2_lsr_i_r_and: // llvm.hexagon.S2.l
		sr.i.r.and
		case Intrinsic::hexagon_S2_lsr_i_r_nac: // llvm.hexagon.S2.l
		sr.i.r.nac
		case Intrinsic::hexagon_S2_lsr_i_r_or: // llvm.hexagon.S2.l
		sr.i.r.or
		case Intrinsic::hexagon_S2_lsr_i_r_xacc: // llvm.hexagon.S2.l
		sr.i.r.xacc
		case Intrinsic::hexagon_S2_lsr_r_r_acc: // llvm.hexagon.S2.l
		sr.r.r.acc
		case Intrinsic::hexagon_S2_lsr_r_r_and: // llvm.hexagon.S2.l
		sr.r.r.and
		case Intrinsic::hexagon_S2_lsr_r_r_nac: // llvm.hexagon.S2.l
		sr.r.r.nac
		case Intrinsic::hexagon_S2_lsr_r_r_or: // llvm.hexagon.S2.l
		sr.r.r.or
		case Intrinsic::hexagon_S4_addaddi: // llvm.hexagon.S4.addaddi
		case Intrinsic::hexagon_S4_or_andi: // llvm.hexagon.S4.or.andi
		case Intrinsic::hexagon_S4_or_andix: // llvm.hexagon.S4.or.andix
		case Intrinsic::hexagon_S4_or_ori: // llvm.hexagon.S4.or.ori
		case Intrinsic::hexagon_S4_subaddi: // llvm.hexagon.S4.subaddi
	case Intrinsic::xcore_crc32: // llvm.xcore.crc32	case Intrinsic::xcore_crc32: // llvm.xcore.crc32
	ResultTy = IntegerType::get(Context, 32);	ResultTy = IntegerType::get(Context, 32);
	ArgTys.push_back(IntegerType::get(Context, 32));	ArgTys.push_back(IntegerType::get(Context, 32));
	ArgTys.push_back(IntegerType::get(Context, 32));	ArgTys.push_back(IntegerType::get(Context, 32));
	ArgTys.push_back(IntegerType::get(Context, 32));	ArgTys.push_back(IntegerType::get(Context, 32));
	break;	break;

		case Intrinsic::hexagon_S2_insert: // llvm.hexagon.S2.insert
		case Intrinsic::hexagon_S2_tableidxb_goodsyntax: // llvm.hexa
		gon.S2.tableidxb.goodsyntax
		case Intrinsic::hexagon_S2_tableidxd_goodsyntax: // llvm.hexa
		gon.S2.tableidxd.goodsyntax
		case Intrinsic::hexagon_S2_tableidxh_goodsyntax: // llvm.hexa
		gon.S2.tableidxh.goodsyntax
		case Intrinsic::hexagon_S2_tableidxw_goodsyntax: // llvm.hexa
		gon.S2.tableidxw.goodsyntax
		ResultTy = IntegerType::get(Context, 32);
		ArgTys.push_back(IntegerType::get(Context, 32));
		ArgTys.push_back(IntegerType::get(Context, 32));
		ArgTys.push_back(IntegerType::get(Context, 32));
		ArgTys.push_back(IntegerType::get(Context, 32));
		break;
	case Intrinsic::arm_mrc: // llvm.arm.mrc	case Intrinsic::arm_mrc: // llvm.arm.mrc
	case Intrinsic::arm_mrc2: // llvm.arm.mrc2	case Intrinsic::arm_mrc2: // llvm.arm.mrc2
	ResultTy = IntegerType::get(Context, 32);	ResultTy = IntegerType::get(Context, 32);
	ArgTys.push_back(IntegerType::get(Context, 32));	ArgTys.push_back(IntegerType::get(Context, 32));
	ArgTys.push_back(IntegerType::get(Context, 32));	ArgTys.push_back(IntegerType::get(Context, 32));
	ArgTys.push_back(IntegerType::get(Context, 32));	ArgTys.push_back(IntegerType::get(Context, 32));
	ArgTys.push_back(IntegerType::get(Context, 32));	ArgTys.push_back(IntegerType::get(Context, 32));
	ArgTys.push_back(IntegerType::get(Context, 32));	ArgTys.push_back(IntegerType::get(Context, 32));
	break;	break;

		case Intrinsic::hexagon_S2_insert_rp: // llvm.hexagon.S2.i
		nsert.rp
		ResultTy = IntegerType::get(Context, 32);
		ArgTys.push_back(IntegerType::get(Context, 32));
		ArgTys.push_back(IntegerType::get(Context, 32));
		ArgTys.push_back(IntegerType::get(Context, 64));
		break;
	case Intrinsic::arm_strexd: // llvm.arm.strexd	case Intrinsic::arm_strexd: // llvm.arm.strexd
	ResultTy = IntegerType::get(Context, 32);	ResultTy = IntegerType::get(Context, 32);
	ArgTys.push_back(IntegerType::get(Context, 32));	ArgTys.push_back(IntegerType::get(Context, 32));
	ArgTys.push_back(IntegerType::get(Context, 32));	ArgTys.push_back(IntegerType::get(Context, 32));
	ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));	ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
	break;	break;

		case Intrinsic::hexagon_S2_extractu_rp: // llvm.hexagon.S2.e
		xtractu.rp
		ResultTy = IntegerType::get(Context, 32);
		ArgTys.push_back(IntegerType::get(Context, 32));
		ArgTys.push_back(IntegerType::get(Context, 64));
		break;
	case Intrinsic::x86_sse42_crc32_32_8: // llvm.x86.sse42.cr c32.32.8	case Intrinsic::x86_sse42_crc32_32_8: // llvm.x86.sse42.cr c32.32.8
	ResultTy = IntegerType::get(Context, 32);	ResultTy = IntegerType::get(Context, 32);
	ArgTys.push_back(IntegerType::get(Context, 32));	ArgTys.push_back(IntegerType::get(Context, 32));
	ArgTys.push_back(IntegerType::get(Context, 8));	ArgTys.push_back(IntegerType::get(Context, 8));
	break;	break;
	case Intrinsic::ppc_altivec_vcmpequb_p: // llvm.ppc.altivec. vcmpequb.p	case Intrinsic::ppc_altivec_vcmpequb_p: // llvm.ppc.altivec. vcmpequb.p
	case Intrinsic::ppc_altivec_vcmpgtsb_p: // llvm.ppc.altivec. vcmpgtsb.p	case Intrinsic::ppc_altivec_vcmpgtsb_p: // llvm.ppc.altivec. vcmpgtsb.p
	case Intrinsic::ppc_altivec_vcmpgtub_p: // llvm.ppc.altivec. vcmpgtub.p	case Intrinsic::ppc_altivec_vcmpgtub_p: // llvm.ppc.altivec. vcmpgtub.p
	ResultTy = IntegerType::get(Context, 32);	ResultTy = IntegerType::get(Context, 32);
	ArgTys.push_back(IntegerType::get(Context, 32));	ArgTys.push_back(IntegerType::get(Context, 32));

	skipping to change at line 11267	skipping to change at line 20976
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
	break;	break;
	case Intrinsic::ppc_altivec_vcmpequh_p: // llvm.ppc.altivec. vcmpequh.p	case Intrinsic::ppc_altivec_vcmpequh_p: // llvm.ppc.altivec. vcmpequh.p
	case Intrinsic::ppc_altivec_vcmpgtsh_p: // llvm.ppc.altivec. vcmpgtsh.p	case Intrinsic::ppc_altivec_vcmpgtsh_p: // llvm.ppc.altivec. vcmpgtsh.p
	case Intrinsic::ppc_altivec_vcmpgtuh_p: // llvm.ppc.altivec. vcmpgtuh.p	case Intrinsic::ppc_altivec_vcmpgtuh_p: // llvm.ppc.altivec. vcmpgtuh.p
	ResultTy = IntegerType::get(Context, 32);	ResultTy = IntegerType::get(Context, 32);
	ArgTys.push_back(IntegerType::get(Context, 32));	ArgTys.push_back(IntegerType::get(Context, 32));
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
	break;	break;

		case Intrinsic::hexagon_A2_sat: // llvm.hexagon.A2.sat
		case Intrinsic::hexagon_S2_cl0p: // llvm.hexagon.S2.cl0p
		case Intrinsic::hexagon_S2_cl1p: // llvm.hexagon.S2.cl1p
		case Intrinsic::hexagon_S2_clbp: // llvm.hexagon.S2.clbp
		case Intrinsic::hexagon_S2_vrndpackwh: // llvm.hexagon.S2.v
		rndpackwh
		case Intrinsic::hexagon_S2_vrndpackwhs: // llvm.hexagon.S2.v
		rndpackwhs
		case Intrinsic::hexagon_S2_vsathb: // llvm.hexagon.S2.vsathb
		case Intrinsic::hexagon_S2_vsathub: // llvm.hexagon.S2.vsathub
		case Intrinsic::hexagon_S2_vsatwh: // llvm.hexagon.S2.vsatwh
		case Intrinsic::hexagon_S2_vsatwuh: // llvm.hexagon.S2.vsatwuh
		case Intrinsic::hexagon_S2_vtrunehb: // llvm.hexagon.S2.vtrunehb
		case Intrinsic::hexagon_S2_vtrunohb: // llvm.hexagon.S2.vtrunohb
		ResultTy = IntegerType::get(Context, 32);
		ArgTys.push_back(IntegerType::get(Context, 64));
		break;
		case Intrinsic::hexagon_M2_vrcmpys_s1rp: // llvm.hexagon.M2.v
		rcmpys.s1rp
		case Intrinsic::hexagon_S2_asr_i_svw_trun: // llvm.hexagon.S2.a
		sr.i.svw.trun
		case Intrinsic::hexagon_S2_asr_r_svw_trun: // llvm.hexagon.S2.a
		sr.r.svw.trun
		ResultTy = IntegerType::get(Context, 32);
		ArgTys.push_back(IntegerType::get(Context, 64));
		ArgTys.push_back(IntegerType::get(Context, 32));
		break;
		case Intrinsic::hexagon_M2_vdmpyrs_s0: // llvm.hexagon.M2.v
		dmpyrs.s0
		case Intrinsic::hexagon_M2_vdmpyrs_s1: // llvm.hexagon.M2.v
		dmpyrs.s1
		case Intrinsic::hexagon_M2_vradduh: // llvm.hexagon.M2.vradduh
		case Intrinsic::hexagon_S2_parityp: // llvm.hexagon.S2.parityp
		ResultTy = IntegerType::get(Context, 32);
		ArgTys.push_back(IntegerType::get(Context, 64));
		ArgTys.push_back(IntegerType::get(Context, 64));
		break;
	case Intrinsic::eh_sjlj_setjmp: // llvm.eh.sjlj.setjmp	case Intrinsic::eh_sjlj_setjmp: // llvm.eh.sjlj.setjmp
	case Intrinsic::eh_typeid_for: // llvm.eh.typeid.for	case Intrinsic::eh_typeid_for: // llvm.eh.typeid.for
	case Intrinsic::setjmp: // llvm.setjmp	case Intrinsic::setjmp: // llvm.setjmp
	ResultTy = IntegerType::get(Context, 32);	ResultTy = IntegerType::get(Context, 32);
	ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));	ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
	break;	break;
	case Intrinsic::sigsetjmp: // llvm.sigsetjmp	case Intrinsic::sigsetjmp: // llvm.sigsetjmp
	ResultTy = IntegerType::get(Context, 32);	ResultTy = IntegerType::get(Context, 32);
	ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));	ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
	ArgTys.push_back(IntegerType::get(Context, 32));	ArgTys.push_back(IntegerType::get(Context, 32));
	break;	break;

	case Intrinsic::eh_selector: // llvm.eh.selector
	IsVarArg = true;
	ResultTy = IntegerType::get(Context, 32);
	ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
	ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
	break;
	case Intrinsic::x86_sse2_pmovmskb_128: // llvm.x86.sse2.pmo vmskb.128	case Intrinsic::x86_sse2_pmovmskb_128: // llvm.x86.sse2.pmo vmskb.128
	ResultTy = IntegerType::get(Context, 32);	ResultTy = IntegerType::get(Context, 32);
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
	break;	break;
	case Intrinsic::x86_sse41_pextrb: // llvm.x86.sse41.pextrb	case Intrinsic::x86_sse41_pextrb: // llvm.x86.sse41.pextrb
	ResultTy = IntegerType::get(Context, 32);	ResultTy = IntegerType::get(Context, 32);
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
	ArgTys.push_back(IntegerType::get(Context, 32));	ArgTys.push_back(IntegerType::get(Context, 32));
	break;	break;
	case Intrinsic::x86_sse42_pcmpestri128: // llvm.x86.sse42.pc mpestri128	case Intrinsic::x86_sse42_pcmpestri128: // llvm.x86.sse42.pc mpestri128

	skipping to change at line 11342	skipping to change at line 21075
	case Intrinsic::x86_sse2_ucomieq_sd: // llvm.x86.sse2.ucomieq.sd	case Intrinsic::x86_sse2_ucomieq_sd: // llvm.x86.sse2.ucomieq.sd
	case Intrinsic::x86_sse2_ucomige_sd: // llvm.x86.sse2.ucomige.sd	case Intrinsic::x86_sse2_ucomige_sd: // llvm.x86.sse2.ucomige.sd
	case Intrinsic::x86_sse2_ucomigt_sd: // llvm.x86.sse2.ucomigt.sd	case Intrinsic::x86_sse2_ucomigt_sd: // llvm.x86.sse2.ucomigt.sd
	case Intrinsic::x86_sse2_ucomile_sd: // llvm.x86.sse2.ucomile.sd	case Intrinsic::x86_sse2_ucomile_sd: // llvm.x86.sse2.ucomile.sd
	case Intrinsic::x86_sse2_ucomilt_sd: // llvm.x86.sse2.ucomilt.sd	case Intrinsic::x86_sse2_ucomilt_sd: // llvm.x86.sse2.ucomilt.sd
	case Intrinsic::x86_sse2_ucomineq_sd: // llvm.x86.sse2.uco mineq.sd	case Intrinsic::x86_sse2_ucomineq_sd: // llvm.x86.sse2.uco mineq.sd
	ResultTy = IntegerType::get(Context, 32);	ResultTy = IntegerType::get(Context, 32);
	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
	break;	break;

		case Intrinsic::x86_sse41_ptestc: // llvm.x86.sse41.ptestc
		case Intrinsic::x86_sse41_ptestnzc: // llvm.x86.sse41.ptestnzc
		case Intrinsic::x86_sse41_ptestz: // llvm.x86.sse41.ptestz
		ResultTy = IntegerType::get(Context, 32);
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 2));
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 2));
		break;
		case Intrinsic::x86_avx2_pmovmskb: // llvm.x86.avx2.pmovmskb
		ResultTy = IntegerType::get(Context, 32);
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 32));
		break;
	case Intrinsic::x86_sse_cvtss2si: // llvm.x86.sse.cvtss2si	case Intrinsic::x86_sse_cvtss2si: // llvm.x86.sse.cvtss2si
	case Intrinsic::x86_sse_cvttss2si: // llvm.x86.sse.cvttss2si	case Intrinsic::x86_sse_cvttss2si: // llvm.x86.sse.cvttss2si
	case Intrinsic::x86_sse_movmsk_ps: // llvm.x86.sse.movmsk.ps	case Intrinsic::x86_sse_movmsk_ps: // llvm.x86.sse.movmsk.ps
	ResultTy = IntegerType::get(Context, 32);	ResultTy = IntegerType::get(Context, 32);
	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
	break;	break;
	case Intrinsic::x86_sse41_extractps: // llvm.x86.sse41.extractps	case Intrinsic::x86_sse41_extractps: // llvm.x86.sse41.extractps
	ResultTy = IntegerType::get(Context, 32);	ResultTy = IntegerType::get(Context, 32);
	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
	ArgTys.push_back(IntegerType::get(Context, 32));	ArgTys.push_back(IntegerType::get(Context, 32));
	break;	break;
	case Intrinsic::x86_avx_vtestc_ps: // llvm.x86.avx.vtestc.ps	case Intrinsic::x86_avx_vtestc_ps: // llvm.x86.avx.vtestc.ps
	case Intrinsic::x86_avx_vtestnzc_ps: // llvm.x86.avx.vtestnzc.ps	case Intrinsic::x86_avx_vtestnzc_ps: // llvm.x86.avx.vtestnzc.ps
	case Intrinsic::x86_avx_vtestz_ps: // llvm.x86.avx.vtestz.ps	case Intrinsic::x86_avx_vtestz_ps: // llvm.x86.avx.vtestz.ps

	case Intrinsic::x86_sse41_ptestc: // llvm.x86.sse41.ptestc
	case Intrinsic::x86_sse41_ptestnzc: // llvm.x86.sse41.ptestnzc
	case Intrinsic::x86_sse41_ptestz: // llvm.x86.sse41.ptestz
	case Intrinsic::x86_sse_comieq_ss: // llvm.x86.sse.comieq.ss	case Intrinsic::x86_sse_comieq_ss: // llvm.x86.sse.comieq.ss
	case Intrinsic::x86_sse_comige_ss: // llvm.x86.sse.comige.ss	case Intrinsic::x86_sse_comige_ss: // llvm.x86.sse.comige.ss
	case Intrinsic::x86_sse_comigt_ss: // llvm.x86.sse.comigt.ss	case Intrinsic::x86_sse_comigt_ss: // llvm.x86.sse.comigt.ss
	case Intrinsic::x86_sse_comile_ss: // llvm.x86.sse.comile.ss	case Intrinsic::x86_sse_comile_ss: // llvm.x86.sse.comile.ss
	case Intrinsic::x86_sse_comilt_ss: // llvm.x86.sse.comilt.ss	case Intrinsic::x86_sse_comilt_ss: // llvm.x86.sse.comilt.ss
	case Intrinsic::x86_sse_comineq_ss: // llvm.x86.sse.comineq.ss	case Intrinsic::x86_sse_comineq_ss: // llvm.x86.sse.comineq.ss
	case Intrinsic::x86_sse_ucomieq_ss: // llvm.x86.sse.ucomieq.ss	case Intrinsic::x86_sse_ucomieq_ss: // llvm.x86.sse.ucomieq.ss
	case Intrinsic::x86_sse_ucomige_ss: // llvm.x86.sse.ucomige.ss	case Intrinsic::x86_sse_ucomige_ss: // llvm.x86.sse.ucomige.ss
	case Intrinsic::x86_sse_ucomigt_ss: // llvm.x86.sse.ucomigt.ss	case Intrinsic::x86_sse_ucomigt_ss: // llvm.x86.sse.ucomigt.ss
	case Intrinsic::x86_sse_ucomile_ss: // llvm.x86.sse.ucomile.ss	case Intrinsic::x86_sse_ucomile_ss: // llvm.x86.sse.ucomile.ss

	skipping to change at line 11430	skipping to change at line 21171
	ArgTys.push_back(IntegerType::get(Context, 32));	ArgTys.push_back(IntegerType::get(Context, 32));
	ArgTys.push_back(IntegerType::get(Context, 32));	ArgTys.push_back(IntegerType::get(Context, 32));
	ArgTys.push_back(IntegerType::get(Context, 32));	ArgTys.push_back(IntegerType::get(Context, 32));
	break;	break;
	case Intrinsic::arm_ldrexd: // llvm.arm.ldrexd	case Intrinsic::arm_ldrexd: // llvm.arm.ldrexd
	ResultTy = StructType::get(IntegerType::get(Context, 32), IntegerType:: get(Context, 32), NULL);	ResultTy = StructType::get(IntegerType::get(Context, 32), IntegerType:: get(Context, 32), NULL);
	ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));	ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
	break;	break;
	case Intrinsic::ptx_read_clock64: // llvm.ptx.read.clock64	case Intrinsic::ptx_read_clock64: // llvm.ptx.read.clock64
	case Intrinsic::readcyclecounter: // llvm.readcyclecounter	case Intrinsic::readcyclecounter: // llvm.readcyclecounter

		case Intrinsic::x86_rdfsbase_64: // llvm.x86.rdfsbase.64
		case Intrinsic::x86_rdgsbase_64: // llvm.x86.rdgsbase.64
		ResultTy = IntegerType::get(Context, 64);
		break;
		case Intrinsic::hexagon_A2_sxtw: // llvm.hexagon.A2.sxtw
		case Intrinsic::hexagon_A2_tfrpi: // llvm.hexagon.A2.tfrpi
		case Intrinsic::hexagon_C2_mask: // llvm.hexagon.C2.mask
		case Intrinsic::hexagon_S2_vsplatrh: // llvm.hexagon.S2.vsplatrh
		case Intrinsic::hexagon_S2_vsxtbh: // llvm.hexagon.S2.vsxtbh
		case Intrinsic::hexagon_S2_vsxthw: // llvm.hexagon.S2.vsxthw
		case Intrinsic::hexagon_S2_vzxtbh: // llvm.hexagon.S2.vzxtbh
		case Intrinsic::hexagon_S2_vzxthw: // llvm.hexagon.S2.vzxthw
		ResultTy = IntegerType::get(Context, 64);
		ArgTys.push_back(IntegerType::get(Context, 32));
		break;
		case Intrinsic::hexagon_A2_combineii: // llvm.hexagon.A2.c
		ombineii
		case Intrinsic::hexagon_A2_combinew: // llvm.hexagon.A2.combinew
		case Intrinsic::hexagon_A4_combineir: // llvm.hexagon.A4.c
		ombineir
		case Intrinsic::hexagon_A4_combineri: // llvm.hexagon.A4.c
		ombineri
		case Intrinsic::hexagon_M2_cmpyi_s0: // llvm.hexagon.M2.cmpyi.s0
		case Intrinsic::hexagon_M2_cmpyr_s0: // llvm.hexagon.M2.cmpyr.s0
		case Intrinsic::hexagon_M2_cmpys_s0: // llvm.hexagon.M2.cmpys.s0
		case Intrinsic::hexagon_M2_cmpys_s1: // llvm.hexagon.M2.cmpys.s1
		case Intrinsic::hexagon_M2_cmpysc_s0: // llvm.hexagon.M2.c
		mpysc.s0
		case Intrinsic::hexagon_M2_cmpysc_s1: // llvm.hexagon.M2.c
		mpysc.s1
		case Intrinsic::hexagon_M2_dpmpyss_s0: // llvm.hexagon.M2.d
		pmpyss.s0
		case Intrinsic::hexagon_M2_dpmpyuu_s0: // llvm.hexagon.M2.d
		pmpyuu.s0
		case Intrinsic::hexagon_M2_mpyd_hh_s0: // llvm.hexagon.M2.m
		pyd.hh.s0
		case Intrinsic::hexagon_M2_mpyd_hh_s1: // llvm.hexagon.M2.m
		pyd.hh.s1
		case Intrinsic::hexagon_M2_mpyd_hl_s0: // llvm.hexagon.M2.m
		pyd.hl.s0
		case Intrinsic::hexagon_M2_mpyd_hl_s1: // llvm.hexagon.M2.m
		pyd.hl.s1
		case Intrinsic::hexagon_M2_mpyd_lh_s0: // llvm.hexagon.M2.m
		pyd.lh.s0
		case Intrinsic::hexagon_M2_mpyd_lh_s1: // llvm.hexagon.M2.m
		pyd.lh.s1
		case Intrinsic::hexagon_M2_mpyd_ll_s0: // llvm.hexagon.M2.m
		pyd.ll.s0
		case Intrinsic::hexagon_M2_mpyd_ll_s1: // llvm.hexagon.M2.m
		pyd.ll.s1
		case Intrinsic::hexagon_M2_mpyd_rnd_hh_s0: // llvm.hexagon.M2.m
		pyd.rnd.hh.s0
		case Intrinsic::hexagon_M2_mpyd_rnd_hh_s1: // llvm.hexagon.M2.m
		pyd.rnd.hh.s1
		case Intrinsic::hexagon_M2_mpyd_rnd_hl_s0: // llvm.hexagon.M2.m
		pyd.rnd.hl.s0
		case Intrinsic::hexagon_M2_mpyd_rnd_hl_s1: // llvm.hexagon.M2.m
		pyd.rnd.hl.s1
		case Intrinsic::hexagon_M2_mpyd_rnd_lh_s0: // llvm.hexagon.M2.m
		pyd.rnd.lh.s0
		case Intrinsic::hexagon_M2_mpyd_rnd_lh_s1: // llvm.hexagon.M2.m
		pyd.rnd.lh.s1
		case Intrinsic::hexagon_M2_mpyd_rnd_ll_s0: // llvm.hexagon.M2.m
		pyd.rnd.ll.s0
		case Intrinsic::hexagon_M2_mpyd_rnd_ll_s1: // llvm.hexagon.M2.m
		pyd.rnd.ll.s1
		case Intrinsic::hexagon_M2_mpyud_hh_s0: // llvm.hexagon.M2.m
		pyud.hh.s0
		case Intrinsic::hexagon_M2_mpyud_hh_s1: // llvm.hexagon.M2.m
		pyud.hh.s1
		case Intrinsic::hexagon_M2_mpyud_hl_s0: // llvm.hexagon.M2.m
		pyud.hl.s0
		case Intrinsic::hexagon_M2_mpyud_hl_s1: // llvm.hexagon.M2.m
		pyud.hl.s1
		case Intrinsic::hexagon_M2_mpyud_lh_s0: // llvm.hexagon.M2.m
		pyud.lh.s0
		case Intrinsic::hexagon_M2_mpyud_lh_s1: // llvm.hexagon.M2.m
		pyud.lh.s1
		case Intrinsic::hexagon_M2_mpyud_ll_s0: // llvm.hexagon.M2.m
		pyud.ll.s0
		case Intrinsic::hexagon_M2_mpyud_ll_s1: // llvm.hexagon.M2.m
		pyud.ll.s1
		case Intrinsic::hexagon_M2_vmpy2s_s0: // llvm.hexagon.M2.v
		mpy2s.s0
		case Intrinsic::hexagon_M2_vmpy2s_s1: // llvm.hexagon.M2.v
		mpy2s.s1
		case Intrinsic::hexagon_S2_packhl: // llvm.hexagon.S2.packhl
		ResultTy = IntegerType::get(Context, 64);
		ArgTys.push_back(IntegerType::get(Context, 32));
		ArgTys.push_back(IntegerType::get(Context, 32));
		break;
		case Intrinsic::hexagon_A2_addsp: // llvm.hexagon.A2.addsp
		ResultTy = IntegerType::get(Context, 64);
		ArgTys.push_back(IntegerType::get(Context, 32));
		ArgTys.push_back(IntegerType::get(Context, 64));
		break;
		case Intrinsic::hexagon_C2_vmux: // llvm.hexagon.C2.vmux
	ResultTy = IntegerType::get(Context, 64);	ResultTy = IntegerType::get(Context, 64);

		ArgTys.push_back(IntegerType::get(Context, 32));
		ArgTys.push_back(IntegerType::get(Context, 64));
		ArgTys.push_back(IntegerType::get(Context, 64));
		break;
		case Intrinsic::hexagon_A2_absp: // llvm.hexagon.A2.absp
		case Intrinsic::hexagon_A2_negp: // llvm.hexagon.A2.negp
		case Intrinsic::hexagon_A2_notp: // llvm.hexagon.A2.notp
		case Intrinsic::hexagon_A2_tfrp: // llvm.hexagon.A2.tfrp
		case Intrinsic::hexagon_A2_vabsh: // llvm.hexagon.A2.vabsh
		case Intrinsic::hexagon_A2_vabshsat: // llvm.hexagon.A2.vabshsat
		case Intrinsic::hexagon_A2_vabsw: // llvm.hexagon.A2.vabsw
		case Intrinsic::hexagon_A2_vabswsat: // llvm.hexagon.A2.vabswsat
		case Intrinsic::hexagon_A2_vconj: // llvm.hexagon.A2.vconj
		case Intrinsic::hexagon_S2_deinterleave: // llvm.hexagon.S2.d
		einterleave
		case Intrinsic::hexagon_S2_interleave: // llvm.hexagon.S2.i
		nterleave
		case Intrinsic::hexagon_S2_vsathb_nopack: // llvm.hexagon.S2.v
		sathb.nopack
		case Intrinsic::hexagon_S2_vsathub_nopack: // llvm.hexagon.S2.v
		sathub.nopack
		case Intrinsic::hexagon_S2_vsatwh_nopack: // llvm.hexagon.S2.v
		satwh.nopack
		case Intrinsic::hexagon_S2_vsatwuh_nopack: // llvm.hexagon.S2.v
		satwuh.nopack
		ResultTy = IntegerType::get(Context, 64);
		ArgTys.push_back(IntegerType::get(Context, 64));
		break;
		case Intrinsic::hexagon_M2_vrcmpys_s1: // llvm.hexagon.M2.v
		rcmpys.s1
		case Intrinsic::hexagon_S2_asl_i_p: // llvm.hexagon.S2.asl.i.p
		case Intrinsic::hexagon_S2_asl_i_vh: // llvm.hexagon.S2.asl.i.vh
		case Intrinsic::hexagon_S2_asl_i_vw: // llvm.hexagon.S2.asl.i.vw
		case Intrinsic::hexagon_S2_asl_r_p: // llvm.hexagon.S2.asl.r.p
		case Intrinsic::hexagon_S2_asl_r_vh: // llvm.hexagon.S2.asl.r.vh
		case Intrinsic::hexagon_S2_asl_r_vw: // llvm.hexagon.S2.asl.r.vw
		case Intrinsic::hexagon_S2_asr_i_p: // llvm.hexagon.S2.asr.i.p
		case Intrinsic::hexagon_S2_asr_i_vh: // llvm.hexagon.S2.asr.i.vh
		case Intrinsic::hexagon_S2_asr_i_vw: // llvm.hexagon.S2.asr.i.vw
		case Intrinsic::hexagon_S2_asr_r_p: // llvm.hexagon.S2.asr.r.p
		case Intrinsic::hexagon_S2_asr_r_vh: // llvm.hexagon.S2.asr.r.vh
		case Intrinsic::hexagon_S2_asr_r_vw: // llvm.hexagon.S2.asr.r.vw
		case Intrinsic::hexagon_S2_lsl_r_p: // llvm.hexagon.S2.lsl.r.p
		case Intrinsic::hexagon_S2_lsl_r_vh: // llvm.hexagon.S2.lsl.r.vh
		case Intrinsic::hexagon_S2_lsl_r_vw: // llvm.hexagon.S2.lsl.r.vw
		case Intrinsic::hexagon_S2_lsr_i_p: // llvm.hexagon.S2.lsr.i.p
		case Intrinsic::hexagon_S2_lsr_i_vh: // llvm.hexagon.S2.lsr.i.vh
		case Intrinsic::hexagon_S2_lsr_i_vw: // llvm.hexagon.S2.lsr.i.vw
		case Intrinsic::hexagon_S2_lsr_r_p: // llvm.hexagon.S2.lsr.r.p
		case Intrinsic::hexagon_S2_lsr_r_vh: // llvm.hexagon.S2.lsr.r.vh
		case Intrinsic::hexagon_S2_lsr_r_vw: // llvm.hexagon.S2.lsr.r.vw
		case Intrinsic::hexagon_S2_vcrotate: // llvm.hexagon.S2.vcrotate
		ResultTy = IntegerType::get(Context, 64);
		ArgTys.push_back(IntegerType::get(Context, 64));
		ArgTys.push_back(IntegerType::get(Context, 32));
		break;
		case Intrinsic::hexagon_M2_cmaci_s0: // llvm.hexagon.M2.cmaci.s0
		case Intrinsic::hexagon_M2_cmacr_s0: // llvm.hexagon.M2.cmacr.s0
		case Intrinsic::hexagon_M2_cmacs_s0: // llvm.hexagon.M2.cmacs.s0
		case Intrinsic::hexagon_M2_cmacs_s1: // llvm.hexagon.M2.cmacs.s1
		case Intrinsic::hexagon_M2_cmacsc_s0: // llvm.hexagon.M2.c
		macsc.s0
		case Intrinsic::hexagon_M2_cmacsc_s1: // llvm.hexagon.M2.c
		macsc.s1
		case Intrinsic::hexagon_M2_cnacs_s0: // llvm.hexagon.M2.cnacs.s0
		case Intrinsic::hexagon_M2_cnacs_s1: // llvm.hexagon.M2.cnacs.s1
		case Intrinsic::hexagon_M2_cnacsc_s0: // llvm.hexagon.M2.c
		nacsc.s0
		case Intrinsic::hexagon_M2_cnacsc_s1: // llvm.hexagon.M2.c
		nacsc.s1
		case Intrinsic::hexagon_M2_dpmpyss_acc_s0: // llvm.hexagon.M2.d
		pmpyss.acc.s0
		case Intrinsic::hexagon_M2_dpmpyss_nac_s0: // llvm.hexagon.M2.d
		pmpyss.nac.s0
		case Intrinsic::hexagon_M2_dpmpyuu_acc_s0: // llvm.hexagon.M2.d
		pmpyuu.acc.s0
		case Intrinsic::hexagon_M2_dpmpyuu_nac_s0: // llvm.hexagon.M2.d
		pmpyuu.nac.s0
		case Intrinsic::hexagon_M2_mpyd_acc_hh_s0: // llvm.hexagon.M2.m
		pyd.acc.hh.s0
		case Intrinsic::hexagon_M2_mpyd_acc_hh_s1: // llvm.hexagon.M2.m
		pyd.acc.hh.s1
		case Intrinsic::hexagon_M2_mpyd_acc_hl_s0: // llvm.hexagon.M2.m
		pyd.acc.hl.s0
		case Intrinsic::hexagon_M2_mpyd_acc_hl_s1: // llvm.hexagon.M2.m
		pyd.acc.hl.s1
		case Intrinsic::hexagon_M2_mpyd_acc_lh_s0: // llvm.hexagon.M2.m
		pyd.acc.lh.s0
		case Intrinsic::hexagon_M2_mpyd_acc_lh_s1: // llvm.hexagon.M2.m
		pyd.acc.lh.s1
		case Intrinsic::hexagon_M2_mpyd_acc_ll_s0: // llvm.hexagon.M2.m
		pyd.acc.ll.s0
		case Intrinsic::hexagon_M2_mpyd_acc_ll_s1: // llvm.hexagon.M2.m
		pyd.acc.ll.s1
		case Intrinsic::hexagon_M2_mpyd_nac_hh_s0: // llvm.hexagon.M2.m
		pyd.nac.hh.s0
		case Intrinsic::hexagon_M2_mpyd_nac_hh_s1: // llvm.hexagon.M2.m
		pyd.nac.hh.s1
		case Intrinsic::hexagon_M2_mpyd_nac_hl_s0: // llvm.hexagon.M2.m
		pyd.nac.hl.s0
		case Intrinsic::hexagon_M2_mpyd_nac_hl_s1: // llvm.hexagon.M2.m
		pyd.nac.hl.s1
		case Intrinsic::hexagon_M2_mpyd_nac_lh_s0: // llvm.hexagon.M2.m
		pyd.nac.lh.s0
		case Intrinsic::hexagon_M2_mpyd_nac_lh_s1: // llvm.hexagon.M2.m
		pyd.nac.lh.s1
		case Intrinsic::hexagon_M2_mpyd_nac_ll_s0: // llvm.hexagon.M2.m
		pyd.nac.ll.s0
		case Intrinsic::hexagon_M2_mpyd_nac_ll_s1: // llvm.hexagon.M2.m
		pyd.nac.ll.s1
		case Intrinsic::hexagon_M2_mpyud_acc_hh_s0: // llvm.hexagon.M2.m
		pyud.acc.hh.s0
		case Intrinsic::hexagon_M2_mpyud_acc_hh_s1: // llvm.hexagon.M2.m
		pyud.acc.hh.s1
		case Intrinsic::hexagon_M2_mpyud_acc_hl_s0: // llvm.hexagon.M2.m
		pyud.acc.hl.s0
		case Intrinsic::hexagon_M2_mpyud_acc_hl_s1: // llvm.hexagon.M2.m
		pyud.acc.hl.s1
		case Intrinsic::hexagon_M2_mpyud_acc_lh_s0: // llvm.hexagon.M2.m
		pyud.acc.lh.s0
		case Intrinsic::hexagon_M2_mpyud_acc_lh_s1: // llvm.hexagon.M2.m
		pyud.acc.lh.s1
		case Intrinsic::hexagon_M2_mpyud_acc_ll_s0: // llvm.hexagon.M2.m
		pyud.acc.ll.s0
		case Intrinsic::hexagon_M2_mpyud_acc_ll_s1: // llvm.hexagon.M2.m
		pyud.acc.ll.s1
		case Intrinsic::hexagon_M2_mpyud_nac_hh_s0: // llvm.hexagon.M2.m
		pyud.nac.hh.s0
		case Intrinsic::hexagon_M2_mpyud_nac_hh_s1: // llvm.hexagon.M2.m
		pyud.nac.hh.s1
		case Intrinsic::hexagon_M2_mpyud_nac_hl_s0: // llvm.hexagon.M2.m
		pyud.nac.hl.s0
		case Intrinsic::hexagon_M2_mpyud_nac_hl_s1: // llvm.hexagon.M2.m
		pyud.nac.hl.s1
		case Intrinsic::hexagon_M2_mpyud_nac_lh_s0: // llvm.hexagon.M2.m
		pyud.nac.lh.s0
		case Intrinsic::hexagon_M2_mpyud_nac_lh_s1: // llvm.hexagon.M2.m
		pyud.nac.lh.s1
		case Intrinsic::hexagon_M2_mpyud_nac_ll_s0: // llvm.hexagon.M2.m
		pyud.nac.ll.s0
		case Intrinsic::hexagon_M2_mpyud_nac_ll_s1: // llvm.hexagon.M2.m
		pyud.nac.ll.s1
		case Intrinsic::hexagon_M2_vmac2: // llvm.hexagon.M2.vmac2
		case Intrinsic::hexagon_M2_vmac2s_s0: // llvm.hexagon.M2.v
		mac2s.s0
		case Intrinsic::hexagon_M2_vmac2s_s1: // llvm.hexagon.M2.v
		mac2s.s1
		case Intrinsic::hexagon_S2_extractup: // llvm.hexagon.S2.e
		xtractup
		ResultTy = IntegerType::get(Context, 64);
		ArgTys.push_back(IntegerType::get(Context, 64));
		ArgTys.push_back(IntegerType::get(Context, 32));
		ArgTys.push_back(IntegerType::get(Context, 32));
	break;	break;

	case Intrinsic::alpha_umulh: // llvm.alpha.umulh	case Intrinsic::hexagon_A2_addp: // llvm.hexagon.A2.addp
		case Intrinsic::hexagon_A2_addpsat: // llvm.hexagon.A2.addpsat
		case Intrinsic::hexagon_A2_andp: // llvm.hexagon.A2.andp
		case Intrinsic::hexagon_A2_maxp: // llvm.hexagon.A2.maxp
		case Intrinsic::hexagon_A2_maxup: // llvm.hexagon.A2.maxup
		case Intrinsic::hexagon_A2_minp: // llvm.hexagon.A2.minp
		case Intrinsic::hexagon_A2_minup: // llvm.hexagon.A2.minup
		case Intrinsic::hexagon_A2_orp: // llvm.hexagon.A2.orp
		case Intrinsic::hexagon_A2_subp: // llvm.hexagon.A2.subp
		case Intrinsic::hexagon_A2_vaddh: // llvm.hexagon.A2.vaddh
		case Intrinsic::hexagon_A2_vaddhs: // llvm.hexagon.A2.vaddhs
		case Intrinsic::hexagon_A2_vaddub: // llvm.hexagon.A2.vaddub
		case Intrinsic::hexagon_A2_vaddubs: // llvm.hexagon.A2.vaddubs
		case Intrinsic::hexagon_A2_vadduhs: // llvm.hexagon.A2.vadduhs
		case Intrinsic::hexagon_A2_vaddw: // llvm.hexagon.A2.vaddw
		case Intrinsic::hexagon_A2_vaddws: // llvm.hexagon.A2.vaddws
		case Intrinsic::hexagon_A2_vavgh: // llvm.hexagon.A2.vavgh
		case Intrinsic::hexagon_A2_vavghcr: // llvm.hexagon.A2.vavghcr
		case Intrinsic::hexagon_A2_vavghr: // llvm.hexagon.A2.vavghr
		case Intrinsic::hexagon_A2_vavgub: // llvm.hexagon.A2.vavgub
		case Intrinsic::hexagon_A2_vavgubr: // llvm.hexagon.A2.vavgubr
		case Intrinsic::hexagon_A2_vavguh: // llvm.hexagon.A2.vavguh
		case Intrinsic::hexagon_A2_vavguhr: // llvm.hexagon.A2.vavguhr
		case Intrinsic::hexagon_A2_vavguw: // llvm.hexagon.A2.vavguw
		case Intrinsic::hexagon_A2_vavguwr: // llvm.hexagon.A2.vavguwr
		case Intrinsic::hexagon_A2_vavgw: // llvm.hexagon.A2.vavgw
		case Intrinsic::hexagon_A2_vavgwcr: // llvm.hexagon.A2.vavgwcr
		case Intrinsic::hexagon_A2_vavgwr: // llvm.hexagon.A2.vavgwr
		case Intrinsic::hexagon_A2_vmaxh: // llvm.hexagon.A2.vmaxh
		case Intrinsic::hexagon_A2_vmaxub: // llvm.hexagon.A2.vmaxub
		case Intrinsic::hexagon_A2_vmaxuh: // llvm.hexagon.A2.vmaxuh
		case Intrinsic::hexagon_A2_vmaxuw: // llvm.hexagon.A2.vmaxuw
		case Intrinsic::hexagon_A2_vmaxw: // llvm.hexagon.A2.vmaxw
		case Intrinsic::hexagon_A2_vminh: // llvm.hexagon.A2.vminh
		case Intrinsic::hexagon_A2_vminub: // llvm.hexagon.A2.vminub
		case Intrinsic::hexagon_A2_vminuh: // llvm.hexagon.A2.vminuh
		case Intrinsic::hexagon_A2_vminuw: // llvm.hexagon.A2.vminuw
		case Intrinsic::hexagon_A2_vminw: // llvm.hexagon.A2.vminw
		case Intrinsic::hexagon_A2_vnavgh: // llvm.hexagon.A2.vnavgh
		case Intrinsic::hexagon_A2_vnavghcr: // llvm.hexagon.A2.vnavghcr
		case Intrinsic::hexagon_A2_vnavghr: // llvm.hexagon.A2.vnavghr
		case Intrinsic::hexagon_A2_vnavgw: // llvm.hexagon.A2.vnavgw
		case Intrinsic::hexagon_A2_vnavgwcr: // llvm.hexagon.A2.vnavgwcr
		case Intrinsic::hexagon_A2_vnavgwr: // llvm.hexagon.A2.vnavgwr
		case Intrinsic::hexagon_A2_vraddub: // llvm.hexagon.A2.vraddub
		case Intrinsic::hexagon_A2_vrsadub: // llvm.hexagon.A2.vrsadub
		case Intrinsic::hexagon_A2_vsubh: // llvm.hexagon.A2.vsubh
		case Intrinsic::hexagon_A2_vsubhs: // llvm.hexagon.A2.vsubhs
		case Intrinsic::hexagon_A2_vsubub: // llvm.hexagon.A2.vsubub
		case Intrinsic::hexagon_A2_vsububs: // llvm.hexagon.A2.vsububs
		case Intrinsic::hexagon_A2_vsubuhs: // llvm.hexagon.A2.vsubuhs
		case Intrinsic::hexagon_A2_vsubw: // llvm.hexagon.A2.vsubw
		case Intrinsic::hexagon_A2_vsubws: // llvm.hexagon.A2.vsubws
		case Intrinsic::hexagon_A2_xorp: // llvm.hexagon.A2.xorp
		case Intrinsic::hexagon_A4_andnp: // llvm.hexagon.A4.andnp
		case Intrinsic::hexagon_A4_ornp: // llvm.hexagon.A4.ornp
		case Intrinsic::hexagon_M2_mmpyh_rs0: // llvm.hexagon.M2.m
		mpyh.rs0
		case Intrinsic::hexagon_M2_mmpyh_rs1: // llvm.hexagon.M2.m
		mpyh.rs1
		case Intrinsic::hexagon_M2_mmpyh_s0: // llvm.hexagon.M2.mmpyh.s0
		case Intrinsic::hexagon_M2_mmpyh_s1: // llvm.hexagon.M2.mmpyh.s1
		case Intrinsic::hexagon_M2_mmpyl_rs0: // llvm.hexagon.M2.m
		mpyl.rs0
		case Intrinsic::hexagon_M2_mmpyl_rs1: // llvm.hexagon.M2.m
		mpyl.rs1
		case Intrinsic::hexagon_M2_mmpyl_s0: // llvm.hexagon.M2.mmpyl.s0
		case Intrinsic::hexagon_M2_mmpyl_s1: // llvm.hexagon.M2.mmpyl.s1
		case Intrinsic::hexagon_M2_mmpyuh_rs0: // llvm.hexagon.M2.m
		mpyuh.rs0
		case Intrinsic::hexagon_M2_mmpyuh_rs1: // llvm.hexagon.M2.m
		mpyuh.rs1
		case Intrinsic::hexagon_M2_mmpyuh_s0: // llvm.hexagon.M2.m
		mpyuh.s0
		case Intrinsic::hexagon_M2_mmpyuh_s1: // llvm.hexagon.M2.m
		mpyuh.s1
		case Intrinsic::hexagon_M2_mmpyul_rs0: // llvm.hexagon.M2.m
		mpyul.rs0
		case Intrinsic::hexagon_M2_mmpyul_rs1: // llvm.hexagon.M2.m
		mpyul.rs1
		case Intrinsic::hexagon_M2_mmpyul_s0: // llvm.hexagon.M2.m
		mpyul.s0
		case Intrinsic::hexagon_M2_mmpyul_s1: // llvm.hexagon.M2.m
		mpyul.s1
		case Intrinsic::hexagon_M2_vabsdiffh: // llvm.hexagon.M2.v
		absdiffh
		case Intrinsic::hexagon_M2_vabsdiffw: // llvm.hexagon.M2.v
		absdiffw
		case Intrinsic::hexagon_M2_vcmpy_s0_sat_i: // llvm.hexagon.M2.v
		cmpy.s0.sat.i
		case Intrinsic::hexagon_M2_vcmpy_s0_sat_r: // llvm.hexagon.M2.v
		cmpy.s0.sat.r
		case Intrinsic::hexagon_M2_vcmpy_s1_sat_i: // llvm.hexagon.M2.v
		cmpy.s1.sat.i
		case Intrinsic::hexagon_M2_vcmpy_s1_sat_r: // llvm.hexagon.M2.v
		cmpy.s1.sat.r
		case Intrinsic::hexagon_M2_vdmpys_s0: // llvm.hexagon.M2.v
		dmpys.s0
		case Intrinsic::hexagon_M2_vdmpys_s1: // llvm.hexagon.M2.v
		dmpys.s1
		case Intrinsic::hexagon_M2_vmpy2es_s0: // llvm.hexagon.M2.v
		mpy2es.s0
		case Intrinsic::hexagon_M2_vmpy2es_s1: // llvm.hexagon.M2.v
		mpy2es.s1
		case Intrinsic::hexagon_M2_vrcmpyi_s0: // llvm.hexagon.M2.v
		rcmpyi.s0
		case Intrinsic::hexagon_M2_vrcmpyi_s0c: // llvm.hexagon.M2.v
		rcmpyi.s0c
		case Intrinsic::hexagon_M2_vrcmpyr_s0: // llvm.hexagon.M2.v
		rcmpyr.s0
		case Intrinsic::hexagon_M2_vrcmpyr_s0c: // llvm.hexagon.M2.v
		rcmpyr.s0c
		case Intrinsic::hexagon_M2_vrmpy_s0: // llvm.hexagon.M2.vrmpy.s0
		case Intrinsic::hexagon_S2_extractup_rp: // llvm.hexagon.S2.e
		xtractup.rp
		case Intrinsic::hexagon_S2_lfsp: // llvm.hexagon.S2.lfsp
		case Intrinsic::hexagon_S2_shuffeb: // llvm.hexagon.S2.shuffeb
		case Intrinsic::hexagon_S2_shuffeh: // llvm.hexagon.S2.shuffeh
		case Intrinsic::hexagon_S2_shuffob: // llvm.hexagon.S2.shuffob
		case Intrinsic::hexagon_S2_shuffoh: // llvm.hexagon.S2.shuffoh
		case Intrinsic::hexagon_S2_vtrunewh: // llvm.hexagon.S2.vtrunewh
		case Intrinsic::hexagon_S2_vtrunowh: // llvm.hexagon.S2.vtrunowh
		case Intrinsic::hexagon_S4_andnp: // llvm.hexagon.S4.andnp
		case Intrinsic::hexagon_S4_ornp: // llvm.hexagon.S4.ornp
		case Intrinsic::x86_bmi_bextr_64: // llvm.x86.bmi.bextr.64
		case Intrinsic::x86_bmi_bzhi_64: // llvm.x86.bmi.bzhi.64
		case Intrinsic::x86_bmi_pdep_64: // llvm.x86.bmi.pdep.64
		case Intrinsic::x86_bmi_pext_64: // llvm.x86.bmi.pext.64
	case Intrinsic::x86_sse42_crc32_64_64: // llvm.x86.sse42.cr c32.64.64	case Intrinsic::x86_sse42_crc32_64_64: // llvm.x86.sse42.cr c32.64.64
	ResultTy = IntegerType::get(Context, 64);	ResultTy = IntegerType::get(Context, 64);
	ArgTys.push_back(IntegerType::get(Context, 64));	ArgTys.push_back(IntegerType::get(Context, 64));
	ArgTys.push_back(IntegerType::get(Context, 64));	ArgTys.push_back(IntegerType::get(Context, 64));
	break;	break;

		case Intrinsic::hexagon_M2_vrcmpys_acc_s1: // llvm.hexagon.M2.v
		rcmpys.acc.s1
		case Intrinsic::hexagon_S2_asl_i_p_acc: // llvm.hexagon.S2.a
		sl.i.p.acc
		case Intrinsic::hexagon_S2_asl_i_p_and: // llvm.hexagon.S2.a
		sl.i.p.and
		case Intrinsic::hexagon_S2_asl_i_p_nac: // llvm.hexagon.S2.a
		sl.i.p.nac
		case Intrinsic::hexagon_S2_asl_i_p_or: // llvm.hexagon.S2.a
		sl.i.p.or
		case Intrinsic::hexagon_S2_asl_i_p_xacc: // llvm.hexagon.S2.a
		sl.i.p.xacc
		case Intrinsic::hexagon_S2_asl_r_p_acc: // llvm.hexagon.S2.a
		sl.r.p.acc
		case Intrinsic::hexagon_S2_asl_r_p_and: // llvm.hexagon.S2.a
		sl.r.p.and
		case Intrinsic::hexagon_S2_asl_r_p_nac: // llvm.hexagon.S2.a
		sl.r.p.nac
		case Intrinsic::hexagon_S2_asl_r_p_or: // llvm.hexagon.S2.a
		sl.r.p.or
		case Intrinsic::hexagon_S2_asr_i_p_acc: // llvm.hexagon.S2.a
		sr.i.p.acc
		case Intrinsic::hexagon_S2_asr_i_p_and: // llvm.hexagon.S2.a
		sr.i.p.and
		case Intrinsic::hexagon_S2_asr_i_p_nac: // llvm.hexagon.S2.a
		sr.i.p.nac
		case Intrinsic::hexagon_S2_asr_i_p_or: // llvm.hexagon.S2.a
		sr.i.p.or
		case Intrinsic::hexagon_S2_asr_r_p_acc: // llvm.hexagon.S2.a
		sr.r.p.acc
		case Intrinsic::hexagon_S2_asr_r_p_and: // llvm.hexagon.S2.a
		sr.r.p.and
		case Intrinsic::hexagon_S2_asr_r_p_nac: // llvm.hexagon.S2.a
		sr.r.p.nac
		case Intrinsic::hexagon_S2_asr_r_p_or: // llvm.hexagon.S2.a
		sr.r.p.or
		case Intrinsic::hexagon_S2_lsl_r_p_acc: // llvm.hexagon.S2.l
		sl.r.p.acc
		case Intrinsic::hexagon_S2_lsl_r_p_and: // llvm.hexagon.S2.l
		sl.r.p.and
		case Intrinsic::hexagon_S2_lsl_r_p_nac: // llvm.hexagon.S2.l
		sl.r.p.nac
		case Intrinsic::hexagon_S2_lsl_r_p_or: // llvm.hexagon.S2.l
		sl.r.p.or
		case Intrinsic::hexagon_S2_lsr_i_p_acc: // llvm.hexagon.S2.l
		sr.i.p.acc
		case Intrinsic::hexagon_S2_lsr_i_p_and: // llvm.hexagon.S2.l
		sr.i.p.and
		case Intrinsic::hexagon_S2_lsr_i_p_nac: // llvm.hexagon.S2.l
		sr.i.p.nac
		case Intrinsic::hexagon_S2_lsr_i_p_or: // llvm.hexagon.S2.l
		sr.i.p.or
		case Intrinsic::hexagon_S2_lsr_i_p_xacc: // llvm.hexagon.S2.l
		sr.i.p.xacc
		case Intrinsic::hexagon_S2_lsr_r_p_acc: // llvm.hexagon.S2.l
		sr.r.p.acc
		case Intrinsic::hexagon_S2_lsr_r_p_and: // llvm.hexagon.S2.l
		sr.r.p.and
		case Intrinsic::hexagon_S2_lsr_r_p_nac: // llvm.hexagon.S2.l
		sr.r.p.nac
		case Intrinsic::hexagon_S2_lsr_r_p_or: // llvm.hexagon.S2.l
		sr.r.p.or
		case Intrinsic::hexagon_S2_valignib: // llvm.hexagon.S2.valignib
		case Intrinsic::hexagon_S2_valignrb: // llvm.hexagon.S2.valignrb
		case Intrinsic::hexagon_S2_vspliceib: // llvm.hexagon.S2.v
		spliceib
		case Intrinsic::hexagon_S2_vsplicerb: // llvm.hexagon.S2.v
		splicerb
		ResultTy = IntegerType::get(Context, 64);
		ArgTys.push_back(IntegerType::get(Context, 64));
		ArgTys.push_back(IntegerType::get(Context, 64));
		ArgTys.push_back(IntegerType::get(Context, 32));
		break;
		case Intrinsic::hexagon_S2_insertp: // llvm.hexagon.S2.insertp
		ResultTy = IntegerType::get(Context, 64);
		ArgTys.push_back(IntegerType::get(Context, 64));
		ArgTys.push_back(IntegerType::get(Context, 64));
		ArgTys.push_back(IntegerType::get(Context, 32));
		ArgTys.push_back(IntegerType::get(Context, 32));
		break;
		case Intrinsic::hexagon_A2_vraddub_acc: // llvm.hexagon.A2.v
		raddub.acc
		case Intrinsic::hexagon_A2_vrsadub_acc: // llvm.hexagon.A2.v
		rsadub.acc
		case Intrinsic::hexagon_M2_mmachs_rs0: // llvm.hexagon.M2.m
		machs.rs0
		case Intrinsic::hexagon_M2_mmachs_rs1: // llvm.hexagon.M2.m
		machs.rs1
		case Intrinsic::hexagon_M2_mmachs_s0: // llvm.hexagon.M2.m
		machs.s0
		case Intrinsic::hexagon_M2_mmachs_s1: // llvm.hexagon.M2.m
		machs.s1
		case Intrinsic::hexagon_M2_mmacls_rs0: // llvm.hexagon.M2.m
		macls.rs0
		case Intrinsic::hexagon_M2_mmacls_rs1: // llvm.hexagon.M2.m
		macls.rs1
		case Intrinsic::hexagon_M2_mmacls_s0: // llvm.hexagon.M2.m
		macls.s0
		case Intrinsic::hexagon_M2_mmacls_s1: // llvm.hexagon.M2.m
		macls.s1
		case Intrinsic::hexagon_M2_mmacuhs_rs0: // llvm.hexagon.M2.m
		macuhs.rs0
		case Intrinsic::hexagon_M2_mmacuhs_rs1: // llvm.hexagon.M2.m
		macuhs.rs1
		case Intrinsic::hexagon_M2_mmacuhs_s0: // llvm.hexagon.M2.m
		macuhs.s0
		case Intrinsic::hexagon_M2_mmacuhs_s1: // llvm.hexagon.M2.m
		macuhs.s1
		case Intrinsic::hexagon_M2_mmaculs_rs0: // llvm.hexagon.M2.m
		maculs.rs0
		case Intrinsic::hexagon_M2_mmaculs_rs1: // llvm.hexagon.M2.m
		maculs.rs1
		case Intrinsic::hexagon_M2_mmaculs_s0: // llvm.hexagon.M2.m
		maculs.s0
		case Intrinsic::hexagon_M2_mmaculs_s1: // llvm.hexagon.M2.m
		maculs.s1
		case Intrinsic::hexagon_M2_vcmac_s0_sat_i: // llvm.hexagon.M2.v
		cmac.s0.sat.i
		case Intrinsic::hexagon_M2_vcmac_s0_sat_r: // llvm.hexagon.M2.v
		cmac.s0.sat.r
		case Intrinsic::hexagon_M2_vdmacs_s0: // llvm.hexagon.M2.v
		dmacs.s0
		case Intrinsic::hexagon_M2_vdmacs_s1: // llvm.hexagon.M2.v
		dmacs.s1
		case Intrinsic::hexagon_M2_vmac2es: // llvm.hexagon.M2.vmac2es
		case Intrinsic::hexagon_M2_vmac2es_s0: // llvm.hexagon.M2.v
		mac2es.s0
		case Intrinsic::hexagon_M2_vmac2es_s1: // llvm.hexagon.M2.v
		mac2es.s1
		case Intrinsic::hexagon_M2_vrcmaci_s0: // llvm.hexagon.M2.v
		rcmaci.s0
		case Intrinsic::hexagon_M2_vrcmaci_s0c: // llvm.hexagon.M2.v
		rcmaci.s0c
		case Intrinsic::hexagon_M2_vrcmacr_s0: // llvm.hexagon.M2.v
		rcmacr.s0
		case Intrinsic::hexagon_M2_vrcmacr_s0c: // llvm.hexagon.M2.v
		rcmacr.s0c
		case Intrinsic::hexagon_M2_vrmac_s0: // llvm.hexagon.M2.vrmac.s0
		case Intrinsic::hexagon_M4_xor_xacc: // llvm.hexagon.M4.xor.xacc
		case Intrinsic::hexagon_S2_insertp_rp: // llvm.hexagon.S2.i
		nsertp.rp
		ResultTy = IntegerType::get(Context, 64);
		ArgTys.push_back(IntegerType::get(Context, 64));
		ArgTys.push_back(IntegerType::get(Context, 64));
		ArgTys.push_back(IntegerType::get(Context, 64));
		break;
	case Intrinsic::x86_sse42_crc32_64_8: // llvm.x86.sse42.cr c32.64.8	case Intrinsic::x86_sse42_crc32_64_8: // llvm.x86.sse42.cr c32.64.8
	ResultTy = IntegerType::get(Context, 64);	ResultTy = IntegerType::get(Context, 64);
	ArgTys.push_back(IntegerType::get(Context, 64));	ArgTys.push_back(IntegerType::get(Context, 64));
	ArgTys.push_back(IntegerType::get(Context, 8));	ArgTys.push_back(IntegerType::get(Context, 8));
	break;	break;
	case Intrinsic::x86_sse2_cvtsd2si64: // llvm.x86.sse2.cvtsd2si64	case Intrinsic::x86_sse2_cvtsd2si64: // llvm.x86.sse2.cvtsd2si64
	case Intrinsic::x86_sse2_cvttsd2si64: // llvm.x86.sse2.cvt tsd2si64	case Intrinsic::x86_sse2_cvttsd2si64: // llvm.x86.sse2.cvt tsd2si64
	ResultTy = IntegerType::get(Context, 64);	ResultTy = IntegerType::get(Context, 64);
	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
	break;	break;

	skipping to change at line 11459	skipping to change at line 21551
	ResultTy = IntegerType::get(Context, 64);	ResultTy = IntegerType::get(Context, 64);
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 2));	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 2));
	ArgTys.push_back(IntegerType::get(Context, 32));	ArgTys.push_back(IntegerType::get(Context, 32));
	break;	break;
	case Intrinsic::x86_sse_cvtss2si64: // llvm.x86.sse.cvtss2si64	case Intrinsic::x86_sse_cvtss2si64: // llvm.x86.sse.cvtss2si64
	case Intrinsic::x86_sse_cvttss2si64: // llvm.x86.sse.cvttss2si64	case Intrinsic::x86_sse_cvttss2si64: // llvm.x86.sse.cvttss2si64
	ResultTy = IntegerType::get(Context, 64);	ResultTy = IntegerType::get(Context, 64);
	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
	break;	break;
	case Intrinsic::arm_thread_pointer: // llvm.arm.thread.pointer	case Intrinsic::arm_thread_pointer: // llvm.arm.thread.pointer

	case Intrinsic::eh_exception: // llvm.eh.exception
	case Intrinsic::eh_sjlj_lsda: // llvm.eh.sjlj.lsda	case Intrinsic::eh_sjlj_lsda: // llvm.eh.sjlj.lsda
	case Intrinsic::stacksave: // llvm.stacksave	case Intrinsic::stacksave: // llvm.stacksave
	case Intrinsic::xcore_waitevent: // llvm.xcore.waitevent	case Intrinsic::xcore_waitevent: // llvm.xcore.waitevent
	ResultTy = PointerType::getUnqual(IntegerType::get(Context, 8));	ResultTy = PointerType::getUnqual(IntegerType::get(Context, 8));
	break;	break;
	case Intrinsic::eh_dwarf_cfa: // llvm.eh.dwarf.cfa	case Intrinsic::eh_dwarf_cfa: // llvm.eh.dwarf.cfa
	case Intrinsic::frameaddress: // llvm.frameaddress	case Intrinsic::frameaddress: // llvm.frameaddress
	case Intrinsic::returnaddress: // llvm.returnaddress	case Intrinsic::returnaddress: // llvm.returnaddress
	ResultTy = PointerType::getUnqual(IntegerType::get(Context, 8));	ResultTy = PointerType::getUnqual(IntegerType::get(Context, 8));
	ArgTys.push_back(IntegerType::get(Context, 32));	ArgTys.push_back(IntegerType::get(Context, 32));
	break;	break;
	case Intrinsic::adjust_trampoline: // llvm.adjust.trampoline	case Intrinsic::adjust_trampoline: // llvm.adjust.trampoline
	case Intrinsic::xcore_checkevent: // llvm.xcore.checkevent	case Intrinsic::xcore_checkevent: // llvm.xcore.checkevent
	ResultTy = PointerType::getUnqual(IntegerType::get(Context, 8));	ResultTy = PointerType::getUnqual(IntegerType::get(Context, 8));
	ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));	ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
	break;	break;

	case Intrinsic::gcread: // llvm.gcread	case Intrinsic::gcread: // llvm.gcread
	ResultTy = PointerType::getUnqual(IntegerType::get(Context, 8));	ResultTy = PointerType::getUnqual(IntegerType::get(Context, 8));
	ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));	ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
	ArgTys.push_back(PointerType::getUnqual(PointerType::getUnqual(IntegerT	ArgTys.push_back(PointerType::getUnqual(PointerType::getUnqual(IntegerT
	ype::get(Context, 8))));	ype::get(Context, 8))));
		break;
		case Intrinsic::x86_avx2_pabs_w: // llvm.x86.avx2.pabs.w
		ResultTy = VectorType::get(IntegerType::get(Context, 16), 16);
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 16));
		break;
		case Intrinsic::x86_avx2_pslli_w: // llvm.x86.avx2.pslli.w
		case Intrinsic::x86_avx2_psrai_w: // llvm.x86.avx2.psrai.w
		case Intrinsic::x86_avx2_psrli_w: // llvm.x86.avx2.psrli.w
		ResultTy = VectorType::get(IntegerType::get(Context, 16), 16);
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 16));
		ArgTys.push_back(IntegerType::get(Context, 32));
		break;
		case Intrinsic::x86_avx2_padds_w: // llvm.x86.avx2.padds.w
		case Intrinsic::x86_avx2_paddus_w: // llvm.x86.avx2.paddus.w
		case Intrinsic::x86_avx2_pavg_w: // llvm.x86.avx2.pavg.w
		case Intrinsic::x86_avx2_phadd_sw: // llvm.x86.avx2.phadd.sw
		case Intrinsic::x86_avx2_phadd_w: // llvm.x86.avx2.phadd.w
		case Intrinsic::x86_avx2_phsub_sw: // llvm.x86.avx2.phsub.sw
		case Intrinsic::x86_avx2_phsub_w: // llvm.x86.avx2.phsub.w
		case Intrinsic::x86_avx2_pmaxs_w: // llvm.x86.avx2.pmaxs.w
		case Intrinsic::x86_avx2_pmaxu_w: // llvm.x86.avx2.pmaxu.w
		case Intrinsic::x86_avx2_pmins_w: // llvm.x86.avx2.pmins.w
		case Intrinsic::x86_avx2_pminu_w: // llvm.x86.avx2.pminu.w
		case Intrinsic::x86_avx2_pmul_hr_sw: // llvm.x86.avx2.pmul.hr.sw
		case Intrinsic::x86_avx2_pmulh_w: // llvm.x86.avx2.pmulh.w
		case Intrinsic::x86_avx2_pmulhu_w: // llvm.x86.avx2.pmulhu.w
		case Intrinsic::x86_avx2_psign_w: // llvm.x86.avx2.psign.w
		case Intrinsic::x86_avx2_psubs_w: // llvm.x86.avx2.psubs.w
		case Intrinsic::x86_avx2_psubus_w: // llvm.x86.avx2.psubus.w
		ResultTy = VectorType::get(IntegerType::get(Context, 16), 16);
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 16));
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 16));
		break;
		case Intrinsic::x86_avx2_pblendw: // llvm.x86.avx2.pblendw
		ResultTy = VectorType::get(IntegerType::get(Context, 16), 16);
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 16));
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 16));
		ArgTys.push_back(IntegerType::get(Context, 32));
		break;
		case Intrinsic::x86_avx2_psll_w: // llvm.x86.avx2.psll.w
		case Intrinsic::x86_avx2_psra_w: // llvm.x86.avx2.psra.w
		case Intrinsic::x86_avx2_psrl_w: // llvm.x86.avx2.psrl.w
		ResultTy = VectorType::get(IntegerType::get(Context, 16), 16);
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 16));
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
		break;
		case Intrinsic::x86_avx2_pmovsxbw: // llvm.x86.avx2.pmovsxbw
		case Intrinsic::x86_avx2_pmovzxbw: // llvm.x86.avx2.pmovzxbw
		ResultTy = VectorType::get(IntegerType::get(Context, 16), 16);
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
		break;
		case Intrinsic::x86_avx2_pmadd_ub_sw: // llvm.x86.avx2.pma
		dd.ub.sw
		ResultTy = VectorType::get(IntegerType::get(Context, 16), 16);
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 32));
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 32));
		break;
		case Intrinsic::x86_avx2_mpsadbw: // llvm.x86.avx2.mpsadbw
		ResultTy = VectorType::get(IntegerType::get(Context, 16), 16);
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 32));
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 32));
		ArgTys.push_back(IntegerType::get(Context, 32));
		break;
		case Intrinsic::x86_avx2_pbroadcastw_256: // llvm.x86.avx2.pbr
		oadcastw.256
		ResultTy = VectorType::get(IntegerType::get(Context, 16), 16);
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
		break;
		case Intrinsic::x86_avx2_packssdw: // llvm.x86.avx2.packssdw
		case Intrinsic::x86_avx2_packusdw: // llvm.x86.avx2.packusdw
		ResultTy = VectorType::get(IntegerType::get(Context, 16), 16);
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 8));
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 8));
	break;	break;
	case Intrinsic::ppc_altivec_lvebx: // llvm.ppc.altivec.lvebx	case Intrinsic::ppc_altivec_lvebx: // llvm.ppc.altivec.lvebx
	case Intrinsic::ppc_altivec_lvsl: // llvm.ppc.altivec.lvsl	case Intrinsic::ppc_altivec_lvsl: // llvm.ppc.altivec.lvsl
	case Intrinsic::ppc_altivec_lvsr: // llvm.ppc.altivec.lvsr	case Intrinsic::ppc_altivec_lvsr: // llvm.ppc.altivec.lvsr
	case Intrinsic::x86_sse3_ldu_dq: // llvm.x86.sse3.ldu.dq	case Intrinsic::x86_sse3_ldu_dq: // llvm.x86.sse3.ldu.dq
	ResultTy = VectorType::get(IntegerType::get(Context, 8), 16);	ResultTy = VectorType::get(IntegerType::get(Context, 8), 16);
	ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));	ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
	break;	break;

		case Intrinsic::x86_avx2_pbroadcastb_128: // llvm.x86.avx2.pbr oadcastb.128
	case Intrinsic::x86_ssse3_pabs_b_128: // llvm.x86.ssse3.pa bs.b.128	case Intrinsic::x86_ssse3_pabs_b_128: // llvm.x86.ssse3.pa bs.b.128
	ResultTy = VectorType::get(IntegerType::get(Context, 8), 16);	ResultTy = VectorType::get(IntegerType::get(Context, 8), 16);
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
	break;	break;
	case Intrinsic::spu_si_shlqbii: // llvm.spu.si.shlqbii	case Intrinsic::spu_si_shlqbii: // llvm.spu.si.shlqbii
	case Intrinsic::spu_si_shlqbyi: // llvm.spu.si.shlqbyi	case Intrinsic::spu_si_shlqbyi: // llvm.spu.si.shlqbyi
	ResultTy = VectorType::get(IntegerType::get(Context, 8), 16);	ResultTy = VectorType::get(IntegerType::get(Context, 8), 16);
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
	ArgTys.push_back(IntegerType::get(Context, 8));	ArgTys.push_back(IntegerType::get(Context, 8));
	break;	break;

	skipping to change at line 11539	skipping to change at line 21702
	case Intrinsic::ppc_altivec_vsrab: // llvm.ppc.altivec.vsrab	case Intrinsic::ppc_altivec_vsrab: // llvm.ppc.altivec.vsrab
	case Intrinsic::ppc_altivec_vsrb: // llvm.ppc.altivec.vsrb	case Intrinsic::ppc_altivec_vsrb: // llvm.ppc.altivec.vsrb
	case Intrinsic::ppc_altivec_vsubsbs: // llvm.ppc.altivec.vsubsbs	case Intrinsic::ppc_altivec_vsubsbs: // llvm.ppc.altivec.vsubsbs
	case Intrinsic::ppc_altivec_vsububs: // llvm.ppc.altivec.vsububs	case Intrinsic::ppc_altivec_vsububs: // llvm.ppc.altivec.vsububs
	case Intrinsic::spu_si_ceqb: // llvm.spu.si.ceqb	case Intrinsic::spu_si_ceqb: // llvm.spu.si.ceqb
	case Intrinsic::spu_si_cgtb: // llvm.spu.si.cgtb	case Intrinsic::spu_si_cgtb: // llvm.spu.si.cgtb
	case Intrinsic::spu_si_clgtb: // llvm.spu.si.clgtb	case Intrinsic::spu_si_clgtb: // llvm.spu.si.clgtb
	case Intrinsic::x86_sse2_padds_b: // llvm.x86.sse2.padds.b	case Intrinsic::x86_sse2_padds_b: // llvm.x86.sse2.padds.b
	case Intrinsic::x86_sse2_paddus_b: // llvm.x86.sse2.paddus.b	case Intrinsic::x86_sse2_paddus_b: // llvm.x86.sse2.paddus.b
	case Intrinsic::x86_sse2_pavg_b: // llvm.x86.sse2.pavg.b	case Intrinsic::x86_sse2_pavg_b: // llvm.x86.sse2.pavg.b

	case Intrinsic::x86_sse2_pcmpeq_b: // llvm.x86.sse2.pcmpeq.b
	case Intrinsic::x86_sse2_pcmpgt_b: // llvm.x86.sse2.pcmpgt.b
	case Intrinsic::x86_sse2_pmaxu_b: // llvm.x86.sse2.pmaxu.b	case Intrinsic::x86_sse2_pmaxu_b: // llvm.x86.sse2.pmaxu.b
	case Intrinsic::x86_sse2_pminu_b: // llvm.x86.sse2.pminu.b	case Intrinsic::x86_sse2_pminu_b: // llvm.x86.sse2.pminu.b
	case Intrinsic::x86_sse2_psubs_b: // llvm.x86.sse2.psubs.b	case Intrinsic::x86_sse2_psubs_b: // llvm.x86.sse2.psubs.b
	case Intrinsic::x86_sse2_psubus_b: // llvm.x86.sse2.psubus.b	case Intrinsic::x86_sse2_psubus_b: // llvm.x86.sse2.psubus.b
	case Intrinsic::x86_sse41_pmaxsb: // llvm.x86.sse41.pmaxsb	case Intrinsic::x86_sse41_pmaxsb: // llvm.x86.sse41.pmaxsb
	case Intrinsic::x86_sse41_pminsb: // llvm.x86.sse41.pminsb	case Intrinsic::x86_sse41_pminsb: // llvm.x86.sse41.pminsb
	case Intrinsic::x86_ssse3_pshuf_b_128: // llvm.x86.ssse3.ps huf.b.128	case Intrinsic::x86_ssse3_pshuf_b_128: // llvm.x86.ssse3.ps huf.b.128
	case Intrinsic::x86_ssse3_psign_b_128: // llvm.x86.ssse3.ps ign.b.128	case Intrinsic::x86_ssse3_psign_b_128: // llvm.x86.ssse3.ps ign.b.128

		case Intrinsic::x86_xop_vpcomeqb: // llvm.x86.xop.vpcomeqb
		case Intrinsic::x86_xop_vpcomequb: // llvm.x86.xop.vpcomequb
		case Intrinsic::x86_xop_vpcomfalseb: // llvm.x86.xop.vpcomfalseb
		case Intrinsic::x86_xop_vpcomfalseub: // llvm.x86.xop.vpco
		mfalseub
		case Intrinsic::x86_xop_vpcomgeb: // llvm.x86.xop.vpcomgeb
		case Intrinsic::x86_xop_vpcomgeub: // llvm.x86.xop.vpcomgeub
		case Intrinsic::x86_xop_vpcomgtb: // llvm.x86.xop.vpcomgtb
		case Intrinsic::x86_xop_vpcomgtub: // llvm.x86.xop.vpcomgtub
		case Intrinsic::x86_xop_vpcomleb: // llvm.x86.xop.vpcomleb
		case Intrinsic::x86_xop_vpcomleub: // llvm.x86.xop.vpcomleub
		case Intrinsic::x86_xop_vpcomltb: // llvm.x86.xop.vpcomltb
		case Intrinsic::x86_xop_vpcomltub: // llvm.x86.xop.vpcomltub
		case Intrinsic::x86_xop_vpcomneb: // llvm.x86.xop.vpcomneb
		case Intrinsic::x86_xop_vpcomneub: // llvm.x86.xop.vpcomneub
		case Intrinsic::x86_xop_vpcomtrueb: // llvm.x86.xop.vpcomtrueb
		case Intrinsic::x86_xop_vpcomtrueub: // llvm.x86.xop.vpcomtrueub
		case Intrinsic::x86_xop_vprotb: // llvm.x86.xop.vprotb
		case Intrinsic::x86_xop_vpshab: // llvm.x86.xop.vpshab
		case Intrinsic::x86_xop_vpshlb: // llvm.x86.xop.vpshlb
	ResultTy = VectorType::get(IntegerType::get(Context, 8), 16);	ResultTy = VectorType::get(IntegerType::get(Context, 8), 16);
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
	break;	break;

	case Intrinsic::x86_sse41_mpsadbw: // llvm.x86.sse41.mpsadbw
	ResultTy = VectorType::get(IntegerType::get(Context, 8), 16);
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
	ArgTys.push_back(IntegerType::get(Context, 32));
	break;
	case Intrinsic::x86_sse42_pcmpistrm128: // llvm.x86.sse42.pc mpistrm128	case Intrinsic::x86_sse42_pcmpistrm128: // llvm.x86.sse42.pc mpistrm128
	ResultTy = VectorType::get(IntegerType::get(Context, 8), 16);	ResultTy = VectorType::get(IntegerType::get(Context, 8), 16);
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
	ArgTys.push_back(IntegerType::get(Context, 8));	ArgTys.push_back(IntegerType::get(Context, 8));
	break;	break;
	case Intrinsic::x86_sse41_pblendvb: // llvm.x86.sse41.pblendvb	case Intrinsic::x86_sse41_pblendvb: // llvm.x86.sse41.pblendvb

		case Intrinsic::x86_xop_vpperm: // llvm.x86.xop.vpperm
	ResultTy = VectorType::get(IntegerType::get(Context, 8), 16);	ResultTy = VectorType::get(IntegerType::get(Context, 8), 16);
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
	break;	break;
	case Intrinsic::ppc_altivec_vpkswss: // llvm.ppc.altivec.vpkswss	case Intrinsic::ppc_altivec_vpkswss: // llvm.ppc.altivec.vpkswss
	ResultTy = VectorType::get(IntegerType::get(Context, 8), 16);	ResultTy = VectorType::get(IntegerType::get(Context, 8), 16);
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
	break;	break;

	skipping to change at line 11592	skipping to change at line 21767
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
	break;	break;
	case Intrinsic::x86_avx_maskload_pd: // llvm.x86.avx.maskload.pd	case Intrinsic::x86_avx_maskload_pd: // llvm.x86.avx.maskload.pd
	ResultTy = VectorType::get(Type::getDoubleTy(Context), 2);	ResultTy = VectorType::get(Type::getDoubleTy(Context), 2);
	ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));	ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
	break;	break;
	case Intrinsic::x86_sse2_sqrt_pd: // llvm.x86.sse2.sqrt.pd	case Intrinsic::x86_sse2_sqrt_pd: // llvm.x86.sse2.sqrt.pd
	case Intrinsic::x86_sse2_sqrt_sd: // llvm.x86.sse2.sqrt.sd	case Intrinsic::x86_sse2_sqrt_sd: // llvm.x86.sse2.sqrt.sd

		case Intrinsic::x86_xop_vfrcz_pd: // llvm.x86.xop.vfrcz.pd
	ResultTy = VectorType::get(Type::getDoubleTy(Context), 2);	ResultTy = VectorType::get(Type::getDoubleTy(Context), 2);
	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
	break;	break;
	case Intrinsic::x86_sse2_cvtsi2sd: // llvm.x86.sse2.cvtsi2sd	case Intrinsic::x86_sse2_cvtsi2sd: // llvm.x86.sse2.cvtsi2sd
	case Intrinsic::x86_sse41_round_pd: // llvm.x86.sse41.round.pd	case Intrinsic::x86_sse41_round_pd: // llvm.x86.sse41.round.pd
	ResultTy = VectorType::get(Type::getDoubleTy(Context), 2);	ResultTy = VectorType::get(Type::getDoubleTy(Context), 2);
	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
	ArgTys.push_back(IntegerType::get(Context, 32));	ArgTys.push_back(IntegerType::get(Context, 32));
	break;	break;
	case Intrinsic::x86_sse2_cvtsi642sd: // llvm.x86.sse2.cvtsi642sd	case Intrinsic::x86_sse2_cvtsi642sd: // llvm.x86.sse2.cvtsi642sd
	ResultTy = VectorType::get(Type::getDoubleTy(Context), 2);	ResultTy = VectorType::get(Type::getDoubleTy(Context), 2);
	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
	ArgTys.push_back(IntegerType::get(Context, 64));	ArgTys.push_back(IntegerType::get(Context, 64));
	break;	break;

	case Intrinsic::x86_avx_vpermil_pd: // llvm.x86.avx.vpermil.pd
	ResultTy = VectorType::get(Type::getDoubleTy(Context), 2);
	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
	ArgTys.push_back(IntegerType::get(Context, 8));
	break;
	case Intrinsic::spu_si_dfa: // llvm.spu.si.dfa	case Intrinsic::spu_si_dfa: // llvm.spu.si.dfa
	case Intrinsic::spu_si_dfm: // llvm.spu.si.dfm	case Intrinsic::spu_si_dfm: // llvm.spu.si.dfm
	case Intrinsic::spu_si_dfma: // llvm.spu.si.dfma	case Intrinsic::spu_si_dfma: // llvm.spu.si.dfma
	case Intrinsic::spu_si_dfms: // llvm.spu.si.dfms	case Intrinsic::spu_si_dfms: // llvm.spu.si.dfms
	case Intrinsic::spu_si_dfnma: // llvm.spu.si.dfnma	case Intrinsic::spu_si_dfnma: // llvm.spu.si.dfnma
	case Intrinsic::spu_si_dfnms: // llvm.spu.si.dfnms	case Intrinsic::spu_si_dfnms: // llvm.spu.si.dfnms
	case Intrinsic::spu_si_dfs: // llvm.spu.si.dfs	case Intrinsic::spu_si_dfs: // llvm.spu.si.dfs
	case Intrinsic::x86_sse2_add_sd: // llvm.x86.sse2.add.sd	case Intrinsic::x86_sse2_add_sd: // llvm.x86.sse2.add.sd
	case Intrinsic::x86_sse2_div_sd: // llvm.x86.sse2.div.sd	case Intrinsic::x86_sse2_div_sd: // llvm.x86.sse2.div.sd
	case Intrinsic::x86_sse2_max_pd: // llvm.x86.sse2.max.pd	case Intrinsic::x86_sse2_max_pd: // llvm.x86.sse2.max.pd
	case Intrinsic::x86_sse2_max_sd: // llvm.x86.sse2.max.sd	case Intrinsic::x86_sse2_max_sd: // llvm.x86.sse2.max.sd
	case Intrinsic::x86_sse2_min_pd: // llvm.x86.sse2.min.pd	case Intrinsic::x86_sse2_min_pd: // llvm.x86.sse2.min.pd
	case Intrinsic::x86_sse2_min_sd: // llvm.x86.sse2.min.sd	case Intrinsic::x86_sse2_min_sd: // llvm.x86.sse2.min.sd
	case Intrinsic::x86_sse2_mul_sd: // llvm.x86.sse2.mul.sd	case Intrinsic::x86_sse2_mul_sd: // llvm.x86.sse2.mul.sd
	case Intrinsic::x86_sse2_sub_sd: // llvm.x86.sse2.sub.sd	case Intrinsic::x86_sse2_sub_sd: // llvm.x86.sse2.sub.sd
	case Intrinsic::x86_sse3_addsub_pd: // llvm.x86.sse3.addsub.pd	case Intrinsic::x86_sse3_addsub_pd: // llvm.x86.sse3.addsub.pd
	case Intrinsic::x86_sse3_hadd_pd: // llvm.x86.sse3.hadd.pd	case Intrinsic::x86_sse3_hadd_pd: // llvm.x86.sse3.hadd.pd
	case Intrinsic::x86_sse3_hsub_pd: // llvm.x86.sse3.hsub.pd	case Intrinsic::x86_sse3_hsub_pd: // llvm.x86.sse3.hsub.pd

		case Intrinsic::x86_xop_vfrcz_sd: // llvm.x86.xop.vfrcz.sd
	ResultTy = VectorType::get(Type::getDoubleTy(Context), 2);	ResultTy = VectorType::get(Type::getDoubleTy(Context), 2);
	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
	break;	break;
	case Intrinsic::x86_sse41_blendpd: // llvm.x86.sse41.blendpd	case Intrinsic::x86_sse41_blendpd: // llvm.x86.sse41.blendpd
	case Intrinsic::x86_sse41_dppd: // llvm.x86.sse41.dppd	case Intrinsic::x86_sse41_dppd: // llvm.x86.sse41.dppd
	case Intrinsic::x86_sse41_round_sd: // llvm.x86.sse41.round.sd	case Intrinsic::x86_sse41_round_sd: // llvm.x86.sse41.round.sd
	ResultTy = VectorType::get(Type::getDoubleTy(Context), 2);	ResultTy = VectorType::get(Type::getDoubleTy(Context), 2);
	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
	ArgTys.push_back(IntegerType::get(Context, 32));	ArgTys.push_back(IntegerType::get(Context, 32));
	break;	break;
	case Intrinsic::x86_sse2_cmp_pd: // llvm.x86.sse2.cmp.pd	case Intrinsic::x86_sse2_cmp_pd: // llvm.x86.sse2.cmp.pd
	case Intrinsic::x86_sse2_cmp_sd: // llvm.x86.sse2.cmp.sd	case Intrinsic::x86_sse2_cmp_sd: // llvm.x86.sse2.cmp.sd
	ResultTy = VectorType::get(Type::getDoubleTy(Context), 2);	ResultTy = VectorType::get(Type::getDoubleTy(Context), 2);
	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
	ArgTys.push_back(IntegerType::get(Context, 8));	ArgTys.push_back(IntegerType::get(Context, 8));
	break;	break;

		case Intrinsic::x86_fma4_vfmadd_pd: // llvm.x86.fma4.vfmadd.pd
		case Intrinsic::x86_fma4_vfmadd_sd: // llvm.x86.fma4.vfmadd.sd
		case Intrinsic::x86_fma4_vfmaddsub_pd: // llvm.x86.fma4.vfm
		addsub.pd
		case Intrinsic::x86_fma4_vfmsub_pd: // llvm.x86.fma4.vfmsub.pd
		case Intrinsic::x86_fma4_vfmsub_sd: // llvm.x86.fma4.vfmsub.sd
		case Intrinsic::x86_fma4_vfmsubadd_pd: // llvm.x86.fma4.vfm
		subadd.pd
		case Intrinsic::x86_fma4_vfnmadd_pd: // llvm.x86.fma4.vfnmadd.pd
		case Intrinsic::x86_fma4_vfnmadd_sd: // llvm.x86.fma4.vfnmadd.sd
		case Intrinsic::x86_fma4_vfnmsub_pd: // llvm.x86.fma4.vfnmsub.pd
		case Intrinsic::x86_fma4_vfnmsub_sd: // llvm.x86.fma4.vfnmsub.sd
	case Intrinsic::x86_sse41_blendvpd: // llvm.x86.sse41.blendvpd	case Intrinsic::x86_sse41_blendvpd: // llvm.x86.sse41.blendvpd
	ResultTy = VectorType::get(Type::getDoubleTy(Context), 2);	ResultTy = VectorType::get(Type::getDoubleTy(Context), 2);
	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
	break;	break;

		case Intrinsic::x86_xop_vpermil2pd: // llvm.x86.xop.vpermil2pd
		ResultTy = VectorType::get(Type::getDoubleTy(Context), 2);
		ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
		ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
		ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
		ArgTys.push_back(IntegerType::get(Context, 8));
		break;
	case Intrinsic::x86_avx_vpermilvar_pd: // llvm.x86.avx.vper milvar.pd	case Intrinsic::x86_avx_vpermilvar_pd: // llvm.x86.avx.vper milvar.pd
	ResultTy = VectorType::get(Type::getDoubleTy(Context), 2);	ResultTy = VectorType::get(Type::getDoubleTy(Context), 2);
	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 2));	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 2));
	break;	break;
	case Intrinsic::x86_sse2_cvtss2sd: // llvm.x86.sse2.cvtss2sd	case Intrinsic::x86_sse2_cvtss2sd: // llvm.x86.sse2.cvtss2sd
	ResultTy = VectorType::get(Type::getDoubleTy(Context), 2);	ResultTy = VectorType::get(Type::getDoubleTy(Context), 2);
	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
	break;	break;

	skipping to change at line 11691	skipping to change at line 21880
	case Intrinsic::arm_neon_vacged: // llvm.arm.neon.vacged	case Intrinsic::arm_neon_vacged: // llvm.arm.neon.vacged
	case Intrinsic::arm_neon_vacgtd: // llvm.arm.neon.vacgtd	case Intrinsic::arm_neon_vacgtd: // llvm.arm.neon.vacgtd
	ResultTy = VectorType::get(IntegerType::get(Context, 32), 2);	ResultTy = VectorType::get(IntegerType::get(Context, 32), 2);
	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 2));	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 2));
	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 2));	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 2));
	break;	break;
	case Intrinsic::x86_sse41_movntdqa: // llvm.x86.sse41.movntdqa	case Intrinsic::x86_sse41_movntdqa: // llvm.x86.sse41.movntdqa
	ResultTy = VectorType::get(IntegerType::get(Context, 64), 2);	ResultTy = VectorType::get(IntegerType::get(Context, 64), 2);
	ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));	ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
	break;	break;

		case Intrinsic::x86_avx2_maskload_q: // llvm.x86.avx2.maskload.q
		ResultTy = VectorType::get(IntegerType::get(Context, 64), 2);
		ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 2));
		break;
	case Intrinsic::x86_sse41_pmovsxbq: // llvm.x86.sse41.pmovsxbq	case Intrinsic::x86_sse41_pmovsxbq: // llvm.x86.sse41.pmovsxbq
	case Intrinsic::x86_sse41_pmovzxbq: // llvm.x86.sse41.pmovzxbq	case Intrinsic::x86_sse41_pmovzxbq: // llvm.x86.sse41.pmovzxbq

		case Intrinsic::x86_xop_vphaddbq: // llvm.x86.xop.vphaddbq
		case Intrinsic::x86_xop_vphaddubq: // llvm.x86.xop.vphaddubq
	ResultTy = VectorType::get(IntegerType::get(Context, 64), 2);	ResultTy = VectorType::get(IntegerType::get(Context, 64), 2);
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
	break;	break;
	case Intrinsic::x86_sse2_psad_bw: // llvm.x86.sse2.psad.bw	case Intrinsic::x86_sse2_psad_bw: // llvm.x86.sse2.psad.bw
	ResultTy = VectorType::get(IntegerType::get(Context, 64), 2);	ResultTy = VectorType::get(IntegerType::get(Context, 64), 2);
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
	break;	break;
	case Intrinsic::x86_aesni_aesimc: // llvm.x86.aesni.aesimc	case Intrinsic::x86_aesni_aesimc: // llvm.x86.aesni.aesimc

		case Intrinsic::x86_avx2_pbroadcastq_128: // llvm.x86.avx2.pbr oadcastq.128
	ResultTy = VectorType::get(IntegerType::get(Context, 64), 2);	ResultTy = VectorType::get(IntegerType::get(Context, 64), 2);
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 2));	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 2));
	break;	break;
	case Intrinsic::x86_sse2_psll_dq: // llvm.x86.sse2.psll.dq	case Intrinsic::x86_sse2_psll_dq: // llvm.x86.sse2.psll.dq
	case Intrinsic::x86_sse2_psll_dq_bs: // llvm.x86.sse2.psll.dq.bs	case Intrinsic::x86_sse2_psll_dq_bs: // llvm.x86.sse2.psll.dq.bs
	case Intrinsic::x86_sse2_pslli_q: // llvm.x86.sse2.pslli.q	case Intrinsic::x86_sse2_pslli_q: // llvm.x86.sse2.pslli.q
	case Intrinsic::x86_sse2_psrl_dq: // llvm.x86.sse2.psrl.dq	case Intrinsic::x86_sse2_psrl_dq: // llvm.x86.sse2.psrl.dq
	case Intrinsic::x86_sse2_psrl_dq_bs: // llvm.x86.sse2.psrl.dq.bs	case Intrinsic::x86_sse2_psrl_dq_bs: // llvm.x86.sse2.psrl.dq.bs
	case Intrinsic::x86_sse2_psrli_q: // llvm.x86.sse2.psrli.q	case Intrinsic::x86_sse2_psrli_q: // llvm.x86.sse2.psrli.q
	ResultTy = VectorType::get(IntegerType::get(Context, 64), 2);	ResultTy = VectorType::get(IntegerType::get(Context, 64), 2);

	skipping to change at line 11724	skipping to change at line 21921
	break;	break;
	case Intrinsic::x86_aesni_aeskeygenassist: // llvm.x86.aesni.ae skeygenassist	case Intrinsic::x86_aesni_aeskeygenassist: // llvm.x86.aesni.ae skeygenassist
	ResultTy = VectorType::get(IntegerType::get(Context, 64), 2);	ResultTy = VectorType::get(IntegerType::get(Context, 64), 2);
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 2));	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 2));
	ArgTys.push_back(IntegerType::get(Context, 8));	ArgTys.push_back(IntegerType::get(Context, 8));
	break;	break;
	case Intrinsic::x86_aesni_aesdec: // llvm.x86.aesni.aesdec	case Intrinsic::x86_aesni_aesdec: // llvm.x86.aesni.aesdec
	case Intrinsic::x86_aesni_aesdeclast: // llvm.x86.aesni.ae sdeclast	case Intrinsic::x86_aesni_aesdeclast: // llvm.x86.aesni.ae sdeclast
	case Intrinsic::x86_aesni_aesenc: // llvm.x86.aesni.aesenc	case Intrinsic::x86_aesni_aesenc: // llvm.x86.aesni.aesenc
	case Intrinsic::x86_aesni_aesenclast: // llvm.x86.aesni.ae senclast	case Intrinsic::x86_aesni_aesenclast: // llvm.x86.aesni.ae senclast

		case Intrinsic::x86_avx2_psllv_q: // llvm.x86.avx2.psllv.q
		case Intrinsic::x86_avx2_psrlv_q: // llvm.x86.avx2.psrlv.q
	case Intrinsic::x86_sse2_psll_q: // llvm.x86.sse2.psll.q	case Intrinsic::x86_sse2_psll_q: // llvm.x86.sse2.psll.q
	case Intrinsic::x86_sse2_psrl_q: // llvm.x86.sse2.psrl.q	case Intrinsic::x86_sse2_psrl_q: // llvm.x86.sse2.psrl.q

	case Intrinsic::x86_sse41_pcmpeqq: // llvm.x86.sse41.pcmpeqq	case Intrinsic::x86_xop_vpcomeqq: // llvm.x86.xop.vpcomeqq
	case Intrinsic::x86_sse42_pcmpgtq: // llvm.x86.sse42.pcmpgtq	case Intrinsic::x86_xop_vpcomequq: // llvm.x86.xop.vpcomequq
		case Intrinsic::x86_xop_vpcomfalseq: // llvm.x86.xop.vpcomfalseq
		case Intrinsic::x86_xop_vpcomfalseuq: // llvm.x86.xop.vpco
		mfalseuq
		case Intrinsic::x86_xop_vpcomgeq: // llvm.x86.xop.vpcomgeq
		case Intrinsic::x86_xop_vpcomgeuq: // llvm.x86.xop.vpcomgeuq
		case Intrinsic::x86_xop_vpcomgtq: // llvm.x86.xop.vpcomgtq
		case Intrinsic::x86_xop_vpcomgtuq: // llvm.x86.xop.vpcomgtuq
		case Intrinsic::x86_xop_vpcomleq: // llvm.x86.xop.vpcomleq
		case Intrinsic::x86_xop_vpcomleuq: // llvm.x86.xop.vpcomleuq
		case Intrinsic::x86_xop_vpcomltq: // llvm.x86.xop.vpcomltq
		case Intrinsic::x86_xop_vpcomltuq: // llvm.x86.xop.vpcomltuq
		case Intrinsic::x86_xop_vpcomneq: // llvm.x86.xop.vpcomneq
		case Intrinsic::x86_xop_vpcomneuq: // llvm.x86.xop.vpcomneuq
		case Intrinsic::x86_xop_vpcomtrueq: // llvm.x86.xop.vpcomtrueq
		case Intrinsic::x86_xop_vpcomtrueuq: // llvm.x86.xop.vpcomtrueuq
		case Intrinsic::x86_xop_vprotq: // llvm.x86.xop.vprotq
		case Intrinsic::x86_xop_vpshaq: // llvm.x86.xop.vpshaq
		case Intrinsic::x86_xop_vpshlq: // llvm.x86.xop.vpshlq
		ResultTy = VectorType::get(IntegerType::get(Context, 64), 2);
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 2));
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 2));
		break;
		case Intrinsic::x86_xop_vpcmov: // llvm.x86.xop.vpcmov
	ResultTy = VectorType::get(IntegerType::get(Context, 64), 2);	ResultTy = VectorType::get(IntegerType::get(Context, 64), 2);
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 2));	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 2));
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 2));	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 2));

		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 2));
	break;	break;
	case Intrinsic::x86_sse41_pmovsxdq: // llvm.x86.sse41.pmovsxdq	case Intrinsic::x86_sse41_pmovsxdq: // llvm.x86.sse41.pmovsxdq
	case Intrinsic::x86_sse41_pmovzxdq: // llvm.x86.sse41.pmovzxdq	case Intrinsic::x86_sse41_pmovzxdq: // llvm.x86.sse41.pmovzxdq

		case Intrinsic::x86_xop_vphadddq: // llvm.x86.xop.vphadddq
		case Intrinsic::x86_xop_vphaddudq: // llvm.x86.xop.vphaddudq
		case Intrinsic::x86_xop_vphsubdq: // llvm.x86.xop.vphsubdq
	ResultTy = VectorType::get(IntegerType::get(Context, 64), 2);	ResultTy = VectorType::get(IntegerType::get(Context, 64), 2);
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
	break;	break;
	case Intrinsic::x86_sse2_pmulu_dq: // llvm.x86.sse2.pmulu.dq	case Intrinsic::x86_sse2_pmulu_dq: // llvm.x86.sse2.pmulu.dq
	case Intrinsic::x86_sse41_pmuldq: // llvm.x86.sse41.pmuldq	case Intrinsic::x86_sse41_pmuldq: // llvm.x86.sse41.pmuldq
	ResultTy = VectorType::get(IntegerType::get(Context, 64), 2);	ResultTy = VectorType::get(IntegerType::get(Context, 64), 2);
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
	break;	break;

		case Intrinsic::x86_xop_vpmacsdqh: // llvm.x86.xop.vpmacsdqh
		case Intrinsic::x86_xop_vpmacsdql: // llvm.x86.xop.vpmacsdql
		case Intrinsic::x86_xop_vpmacssdqh: // llvm.x86.xop.vpmacssdqh
		case Intrinsic::x86_xop_vpmacssdql: // llvm.x86.xop.vpmacssdql
		ResultTy = VectorType::get(IntegerType::get(Context, 64), 2);
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 2));
		break;
		case Intrinsic::x86_avx2_vextracti128: // llvm.x86.avx2.vex
		tracti128
		ResultTy = VectorType::get(IntegerType::get(Context, 64), 2);
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 4));
		ArgTys.push_back(IntegerType::get(Context, 8));
		break;
	case Intrinsic::x86_sse41_pmovsxwq: // llvm.x86.sse41.pmovsxwq	case Intrinsic::x86_sse41_pmovsxwq: // llvm.x86.sse41.pmovsxwq
	case Intrinsic::x86_sse41_pmovzxwq: // llvm.x86.sse41.pmovzxwq	case Intrinsic::x86_sse41_pmovzxwq: // llvm.x86.sse41.pmovzxwq

		case Intrinsic::x86_xop_vphadduwq: // llvm.x86.xop.vphadduwq
		case Intrinsic::x86_xop_vphaddwq: // llvm.x86.xop.vphaddwq
	ResultTy = VectorType::get(IntegerType::get(Context, 64), 2);	ResultTy = VectorType::get(IntegerType::get(Context, 64), 2);
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
	break;	break;
	case Intrinsic::x86_avx_ldu_dq_256: // llvm.x86.avx.ldu.dq.256	case Intrinsic::x86_avx_ldu_dq_256: // llvm.x86.avx.ldu.dq.256

	case Intrinsic::x86_avx_loadu_dq_256: // llvm.x86.avx.load u.dq.256
	ResultTy = VectorType::get(IntegerType::get(Context, 8), 32);	ResultTy = VectorType::get(IntegerType::get(Context, 8), 32);
	ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));	ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
	break;	break;

	case Intrinsic::x86_avx_vbroadcastss: // llvm.x86.avx.vbro	case Intrinsic::x86_avx2_packsswb: // llvm.x86.avx2.packsswb
	adcastss	case Intrinsic::x86_avx2_packuswb: // llvm.x86.avx2.packuswb
		ResultTy = VectorType::get(IntegerType::get(Context, 8), 32);
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 16));
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 16));
		break;
		case Intrinsic::x86_avx2_pbroadcastb_256: // llvm.x86.avx2.pbr
		oadcastb.256
		ResultTy = VectorType::get(IntegerType::get(Context, 8), 32);
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
		break;
		case Intrinsic::x86_avx2_pabs_b: // llvm.x86.avx2.pabs.b
		ResultTy = VectorType::get(IntegerType::get(Context, 8), 32);
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 32));
		break;
		case Intrinsic::x86_avx2_padds_b: // llvm.x86.avx2.padds.b
		case Intrinsic::x86_avx2_paddus_b: // llvm.x86.avx2.paddus.b
		case Intrinsic::x86_avx2_pavg_b: // llvm.x86.avx2.pavg.b
		case Intrinsic::x86_avx2_pmaxs_b: // llvm.x86.avx2.pmaxs.b
		case Intrinsic::x86_avx2_pmaxu_b: // llvm.x86.avx2.pmaxu.b
		case Intrinsic::x86_avx2_pmins_b: // llvm.x86.avx2.pmins.b
		case Intrinsic::x86_avx2_pminu_b: // llvm.x86.avx2.pminu.b
		case Intrinsic::x86_avx2_pshuf_b: // llvm.x86.avx2.pshuf.b
		case Intrinsic::x86_avx2_psign_b: // llvm.x86.avx2.psign.b
		case Intrinsic::x86_avx2_psubs_b: // llvm.x86.avx2.psubs.b
		case Intrinsic::x86_avx2_psubus_b: // llvm.x86.avx2.psubus.b
		ResultTy = VectorType::get(IntegerType::get(Context, 8), 32);
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 32));
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 32));
		break;
		case Intrinsic::x86_avx2_pblendvb: // llvm.x86.avx2.pblendvb
		ResultTy = VectorType::get(IntegerType::get(Context, 8), 32);
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 32));
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 32));
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 32));
		break;
		case Intrinsic::x86_avx_vbroadcast_ss: // llvm.x86.avx.vbro
		adcast.ss
	ResultTy = VectorType::get(Type::getFloatTy(Context), 4);	ResultTy = VectorType::get(Type::getFloatTy(Context), 4);
	ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));	ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
	break;	break;
	case Intrinsic::x86_avx_maskload_ps: // llvm.x86.avx.maskload.ps	case Intrinsic::x86_avx_maskload_ps: // llvm.x86.avx.maskload.ps
	ResultTy = VectorType::get(Type::getFloatTy(Context), 4);	ResultTy = VectorType::get(Type::getFloatTy(Context), 4);
	ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));	ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
	break;	break;
	case Intrinsic::x86_sse2_cvtpd2ps: // llvm.x86.sse2.cvtpd2ps	case Intrinsic::x86_sse2_cvtpd2ps: // llvm.x86.sse2.cvtpd2ps
	ResultTy = VectorType::get(Type::getFloatTy(Context), 4);	ResultTy = VectorType::get(Type::getFloatTy(Context), 4);
	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
	break;	break;
	case Intrinsic::ppc_altivec_vexptefp: // llvm.ppc.altivec. vexptefp	case Intrinsic::ppc_altivec_vexptefp: // llvm.ppc.altivec. vexptefp
	case Intrinsic::ppc_altivec_vlogefp: // llvm.ppc.altivec.vlogefp	case Intrinsic::ppc_altivec_vlogefp: // llvm.ppc.altivec.vlogefp
	case Intrinsic::ppc_altivec_vrefp: // llvm.ppc.altivec.vrefp	case Intrinsic::ppc_altivec_vrefp: // llvm.ppc.altivec.vrefp
	case Intrinsic::ppc_altivec_vrfim: // llvm.ppc.altivec.vrfim	case Intrinsic::ppc_altivec_vrfim: // llvm.ppc.altivec.vrfim
	case Intrinsic::ppc_altivec_vrfin: // llvm.ppc.altivec.vrfin	case Intrinsic::ppc_altivec_vrfin: // llvm.ppc.altivec.vrfin
	case Intrinsic::ppc_altivec_vrfip: // llvm.ppc.altivec.vrfip	case Intrinsic::ppc_altivec_vrfip: // llvm.ppc.altivec.vrfip
	case Intrinsic::ppc_altivec_vrfiz: // llvm.ppc.altivec.vrfiz	case Intrinsic::ppc_altivec_vrfiz: // llvm.ppc.altivec.vrfiz
	case Intrinsic::ppc_altivec_vrsqrtefp: // llvm.ppc.altivec. vrsqrtefp	case Intrinsic::ppc_altivec_vrsqrtefp: // llvm.ppc.altivec. vrsqrtefp

		case Intrinsic::x86_avx2_vbroadcast_ss_ps: // llvm.x86.avx2.vbr oadcast.ss.ps
	case Intrinsic::x86_sse_rcp_ps: // llvm.x86.sse.rcp.ps	case Intrinsic::x86_sse_rcp_ps: // llvm.x86.sse.rcp.ps
	case Intrinsic::x86_sse_rcp_ss: // llvm.x86.sse.rcp.ss	case Intrinsic::x86_sse_rcp_ss: // llvm.x86.sse.rcp.ss
	case Intrinsic::x86_sse_rsqrt_ps: // llvm.x86.sse.rsqrt.ps	case Intrinsic::x86_sse_rsqrt_ps: // llvm.x86.sse.rsqrt.ps
	case Intrinsic::x86_sse_rsqrt_ss: // llvm.x86.sse.rsqrt.ss	case Intrinsic::x86_sse_rsqrt_ss: // llvm.x86.sse.rsqrt.ss
	case Intrinsic::x86_sse_sqrt_ps: // llvm.x86.sse.sqrt.ps	case Intrinsic::x86_sse_sqrt_ps: // llvm.x86.sse.sqrt.ps
	case Intrinsic::x86_sse_sqrt_ss: // llvm.x86.sse.sqrt.ss	case Intrinsic::x86_sse_sqrt_ss: // llvm.x86.sse.sqrt.ss

		case Intrinsic::x86_xop_vfrcz_ps: // llvm.x86.xop.vfrcz.ps
	ResultTy = VectorType::get(Type::getFloatTy(Context), 4);	ResultTy = VectorType::get(Type::getFloatTy(Context), 4);
	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
	break;	break;
	case Intrinsic::x86_sse41_round_ps: // llvm.x86.sse41.round.ps	case Intrinsic::x86_sse41_round_ps: // llvm.x86.sse41.round.ps
	case Intrinsic::x86_sse_cvtsi2ss: // llvm.x86.sse.cvtsi2ss	case Intrinsic::x86_sse_cvtsi2ss: // llvm.x86.sse.cvtsi2ss
	ResultTy = VectorType::get(Type::getFloatTy(Context), 4);	ResultTy = VectorType::get(Type::getFloatTy(Context), 4);
	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
	ArgTys.push_back(IntegerType::get(Context, 32));	ArgTys.push_back(IntegerType::get(Context, 32));
	break;	break;
	case Intrinsic::x86_sse_cvtsi642ss: // llvm.x86.sse.cvtsi642ss	case Intrinsic::x86_sse_cvtsi642ss: // llvm.x86.sse.cvtsi642ss
	ResultTy = VectorType::get(Type::getFloatTy(Context), 4);	ResultTy = VectorType::get(Type::getFloatTy(Context), 4);
	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
	ArgTys.push_back(IntegerType::get(Context, 64));	ArgTys.push_back(IntegerType::get(Context, 64));
	break;	break;

	case Intrinsic::x86_avx_vpermil_ps: // llvm.x86.avx.vpermil.ps
	ResultTy = VectorType::get(Type::getFloatTy(Context), 4);
	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
	ArgTys.push_back(IntegerType::get(Context, 8));
	break;
	case Intrinsic::x86_sse2_cvtsd2ss: // llvm.x86.sse2.cvtsd2ss	case Intrinsic::x86_sse2_cvtsd2ss: // llvm.x86.sse2.cvtsd2ss
	ResultTy = VectorType::get(Type::getFloatTy(Context), 4);	ResultTy = VectorType::get(Type::getFloatTy(Context), 4);
	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
	break;	break;
	case Intrinsic::ppc_altivec_vmaxfp: // llvm.ppc.altivec.vmaxfp	case Intrinsic::ppc_altivec_vmaxfp: // llvm.ppc.altivec.vmaxfp
	case Intrinsic::ppc_altivec_vminfp: // llvm.ppc.altivec.vminfp	case Intrinsic::ppc_altivec_vminfp: // llvm.ppc.altivec.vminfp
	case Intrinsic::spu_si_fa: // llvm.spu.si.fa	case Intrinsic::spu_si_fa: // llvm.spu.si.fa
	case Intrinsic::spu_si_fceq: // llvm.spu.si.fceq	case Intrinsic::spu_si_fceq: // llvm.spu.si.fceq
	case Intrinsic::spu_si_fcgt: // llvm.spu.si.fcgt	case Intrinsic::spu_si_fcgt: // llvm.spu.si.fcgt

	skipping to change at line 11824	skipping to change at line 22096
	case Intrinsic::x86_sse3_hadd_ps: // llvm.x86.sse3.hadd.ps	case Intrinsic::x86_sse3_hadd_ps: // llvm.x86.sse3.hadd.ps
	case Intrinsic::x86_sse3_hsub_ps: // llvm.x86.sse3.hsub.ps	case Intrinsic::x86_sse3_hsub_ps: // llvm.x86.sse3.hsub.ps
	case Intrinsic::x86_sse_add_ss: // llvm.x86.sse.add.ss	case Intrinsic::x86_sse_add_ss: // llvm.x86.sse.add.ss
	case Intrinsic::x86_sse_div_ss: // llvm.x86.sse.div.ss	case Intrinsic::x86_sse_div_ss: // llvm.x86.sse.div.ss
	case Intrinsic::x86_sse_max_ps: // llvm.x86.sse.max.ps	case Intrinsic::x86_sse_max_ps: // llvm.x86.sse.max.ps
	case Intrinsic::x86_sse_max_ss: // llvm.x86.sse.max.ss	case Intrinsic::x86_sse_max_ss: // llvm.x86.sse.max.ss
	case Intrinsic::x86_sse_min_ps: // llvm.x86.sse.min.ps	case Intrinsic::x86_sse_min_ps: // llvm.x86.sse.min.ps
	case Intrinsic::x86_sse_min_ss: // llvm.x86.sse.min.ss	case Intrinsic::x86_sse_min_ss: // llvm.x86.sse.min.ss
	case Intrinsic::x86_sse_mul_ss: // llvm.x86.sse.mul.ss	case Intrinsic::x86_sse_mul_ss: // llvm.x86.sse.mul.ss
	case Intrinsic::x86_sse_sub_ss: // llvm.x86.sse.sub.ss	case Intrinsic::x86_sse_sub_ss: // llvm.x86.sse.sub.ss

		case Intrinsic::x86_xop_vfrcz_ss: // llvm.x86.xop.vfrcz.ss
	ResultTy = VectorType::get(Type::getFloatTy(Context), 4);	ResultTy = VectorType::get(Type::getFloatTy(Context), 4);
	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
	break;	break;
	case Intrinsic::x86_sse41_blendps: // llvm.x86.sse41.blendps	case Intrinsic::x86_sse41_blendps: // llvm.x86.sse41.blendps
	case Intrinsic::x86_sse41_dpps: // llvm.x86.sse41.dpps	case Intrinsic::x86_sse41_dpps: // llvm.x86.sse41.dpps
	case Intrinsic::x86_sse41_insertps: // llvm.x86.sse41.insertps	case Intrinsic::x86_sse41_insertps: // llvm.x86.sse41.insertps
	case Intrinsic::x86_sse41_round_ss: // llvm.x86.sse41.round.ss	case Intrinsic::x86_sse41_round_ss: // llvm.x86.sse41.round.ss
	ResultTy = VectorType::get(Type::getFloatTy(Context), 4);	ResultTy = VectorType::get(Type::getFloatTy(Context), 4);
	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));

	skipping to change at line 11849	skipping to change at line 22122
	ResultTy = VectorType::get(Type::getFloatTy(Context), 4);	ResultTy = VectorType::get(Type::getFloatTy(Context), 4);
	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
	ArgTys.push_back(IntegerType::get(Context, 8));	ArgTys.push_back(IntegerType::get(Context, 8));
	break;	break;
	case Intrinsic::ppc_altivec_vmaddfp: // llvm.ppc.altivec.vmaddfp	case Intrinsic::ppc_altivec_vmaddfp: // llvm.ppc.altivec.vmaddfp
	case Intrinsic::ppc_altivec_vnmsubfp: // llvm.ppc.altivec. vnmsubfp	case Intrinsic::ppc_altivec_vnmsubfp: // llvm.ppc.altivec. vnmsubfp
	case Intrinsic::spu_si_fma: // llvm.spu.si.fma	case Intrinsic::spu_si_fma: // llvm.spu.si.fma
	case Intrinsic::spu_si_fms: // llvm.spu.si.fms	case Intrinsic::spu_si_fms: // llvm.spu.si.fms
	case Intrinsic::spu_si_fnms: // llvm.spu.si.fnms	case Intrinsic::spu_si_fnms: // llvm.spu.si.fnms

		case Intrinsic::x86_fma4_vfmadd_ps: // llvm.x86.fma4.vfmadd.ps
		case Intrinsic::x86_fma4_vfmadd_ss: // llvm.x86.fma4.vfmadd.ss
		case Intrinsic::x86_fma4_vfmaddsub_ps: // llvm.x86.fma4.vfm
		addsub.ps
		case Intrinsic::x86_fma4_vfmsub_ps: // llvm.x86.fma4.vfmsub.ps
		case Intrinsic::x86_fma4_vfmsub_ss: // llvm.x86.fma4.vfmsub.ss
		case Intrinsic::x86_fma4_vfmsubadd_ps: // llvm.x86.fma4.vfm
		subadd.ps
		case Intrinsic::x86_fma4_vfnmadd_ps: // llvm.x86.fma4.vfnmadd.ps
		case Intrinsic::x86_fma4_vfnmadd_ss: // llvm.x86.fma4.vfnmadd.ss
		case Intrinsic::x86_fma4_vfnmsub_ps: // llvm.x86.fma4.vfnmsub.ps
		case Intrinsic::x86_fma4_vfnmsub_ss: // llvm.x86.fma4.vfnmsub.ss
	case Intrinsic::x86_sse41_blendvps: // llvm.x86.sse41.blendvps	case Intrinsic::x86_sse41_blendvps: // llvm.x86.sse41.blendvps
	ResultTy = VectorType::get(Type::getFloatTy(Context), 4);	ResultTy = VectorType::get(Type::getFloatTy(Context), 4);
	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
	break;	break;

		case Intrinsic::x86_xop_vpermil2ps: // llvm.x86.xop.vpermil2ps
		ResultTy = VectorType::get(Type::getFloatTy(Context), 4);
		ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
		ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
		ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
		ArgTys.push_back(IntegerType::get(Context, 8));
		break;
	case Intrinsic::x86_avx_vpermilvar_ps: // llvm.x86.avx.vper milvar.ps	case Intrinsic::x86_avx_vpermilvar_ps: // llvm.x86.avx.vper milvar.ps
	ResultTy = VectorType::get(Type::getFloatTy(Context), 4);	ResultTy = VectorType::get(Type::getFloatTy(Context), 4);
	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
	break;	break;
	case Intrinsic::x86_sse_cvtpi2ps: // llvm.x86.sse.cvtpi2ps	case Intrinsic::x86_sse_cvtpi2ps: // llvm.x86.sse.cvtpi2ps
	ResultTy = VectorType::get(Type::getFloatTy(Context), 4);	ResultTy = VectorType::get(Type::getFloatTy(Context), 4);
	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
	ArgTys.push_back(Type::getX86_MMXTy(Context));	ArgTys.push_back(Type::getX86_MMXTy(Context));
	break;	break;

	skipping to change at line 11888	skipping to change at line 22178
	case Intrinsic::ppc_altivec_vcfux: // llvm.ppc.altivec.vcfux	case Intrinsic::ppc_altivec_vcfux: // llvm.ppc.altivec.vcfux
	ResultTy = VectorType::get(Type::getFloatTy(Context), 4);	ResultTy = VectorType::get(Type::getFloatTy(Context), 4);
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
	ArgTys.push_back(IntegerType::get(Context, 32));	ArgTys.push_back(IntegerType::get(Context, 32));
	break;	break;
	case Intrinsic::x86_avx_vextractf128_ps_256: // llvm.x86.avx.vext ractf128.ps.256	case Intrinsic::x86_avx_vextractf128_ps_256: // llvm.x86.avx.vext ractf128.ps.256
	ResultTy = VectorType::get(Type::getFloatTy(Context), 4);	ResultTy = VectorType::get(Type::getFloatTy(Context), 4);
	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 8));	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 8));
	ArgTys.push_back(IntegerType::get(Context, 8));	ArgTys.push_back(IntegerType::get(Context, 8));
	break;	break;

	case Intrinsic::x86_avx_loadu_pd_256: // llvm.x86.avx.load	case Intrinsic::x86_vcvtph2ps_128: // llvm.x86.vcvtph2ps.128
	u.pd.256	ResultTy = VectorType::get(Type::getFloatTy(Context), 4);
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
		break;
	case Intrinsic::x86_avx_vbroadcast_sd_256: // llvm.x86.avx.vbro adcast.sd.256	case Intrinsic::x86_avx_vbroadcast_sd_256: // llvm.x86.avx.vbro adcast.sd.256
	case Intrinsic::x86_avx_vbroadcastf128_pd_256: // llvm.x86. avx.vbroadcastf128.pd.256	case Intrinsic::x86_avx_vbroadcastf128_pd_256: // llvm.x86. avx.vbroadcastf128.pd.256
	ResultTy = VectorType::get(Type::getDoubleTy(Context), 4);	ResultTy = VectorType::get(Type::getDoubleTy(Context), 4);
	ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));	ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
	break;	break;
	case Intrinsic::x86_avx_maskload_pd_256: // llvm.x86.avx.mask load.pd.256	case Intrinsic::x86_avx_maskload_pd_256: // llvm.x86.avx.mask load.pd.256
	ResultTy = VectorType::get(Type::getDoubleTy(Context), 4);	ResultTy = VectorType::get(Type::getDoubleTy(Context), 4);
	ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));	ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 4));	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 4));
	break;	break;

		case Intrinsic::x86_avx2_vbroadcast_sd_pd_256: // llvm.x86.
		avx2.vbroadcast.sd.pd.256
		ResultTy = VectorType::get(Type::getDoubleTy(Context), 4);
		ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
		break;
	case Intrinsic::x86_avx_cvt_ps2_pd_256: // llvm.x86.avx.cvt. ps2.pd.256	case Intrinsic::x86_avx_cvt_ps2_pd_256: // llvm.x86.avx.cvt. ps2.pd.256
	ResultTy = VectorType::get(Type::getDoubleTy(Context), 4);	ResultTy = VectorType::get(Type::getDoubleTy(Context), 4);
	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
	break;	break;
	case Intrinsic::x86_avx_sqrt_pd_256: // llvm.x86.avx.sqrt.pd.256	case Intrinsic::x86_avx_sqrt_pd_256: // llvm.x86.avx.sqrt.pd.256

		case Intrinsic::x86_xop_vfrcz_pd_256: // llvm.x86.xop.vfrc z.pd.256
	ResultTy = VectorType::get(Type::getDoubleTy(Context), 4);	ResultTy = VectorType::get(Type::getDoubleTy(Context), 4);
	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 4));	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 4));
	break;	break;
	case Intrinsic::x86_avx_round_pd_256: // llvm.x86.avx.roun d.pd.256	case Intrinsic::x86_avx_round_pd_256: // llvm.x86.avx.roun d.pd.256
	ResultTy = VectorType::get(Type::getDoubleTy(Context), 4);	ResultTy = VectorType::get(Type::getDoubleTy(Context), 4);
	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 4));	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 4));
	ArgTys.push_back(IntegerType::get(Context, 32));	ArgTys.push_back(IntegerType::get(Context, 32));
	break;	break;

	case Intrinsic::x86_avx_vpermil_pd_256: // llvm.x86.avx.vper
	mil.pd.256
	ResultTy = VectorType::get(Type::getDoubleTy(Context), 4);
	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 4));
	ArgTys.push_back(IntegerType::get(Context, 8));
	break;
	case Intrinsic::x86_avx_vinsertf128_pd_256: // llvm.x86.avx.vins ertf128.pd.256	case Intrinsic::x86_avx_vinsertf128_pd_256: // llvm.x86.avx.vins ertf128.pd.256
	ResultTy = VectorType::get(Type::getDoubleTy(Context), 4);	ResultTy = VectorType::get(Type::getDoubleTy(Context), 4);
	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 4));	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 4));
	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
	ArgTys.push_back(IntegerType::get(Context, 8));	ArgTys.push_back(IntegerType::get(Context, 8));
	break;	break;
	case Intrinsic::x86_avx_addsub_pd_256: // llvm.x86.avx.adds ub.pd.256	case Intrinsic::x86_avx_addsub_pd_256: // llvm.x86.avx.adds ub.pd.256
	case Intrinsic::x86_avx_hadd_pd_256: // llvm.x86.avx.hadd.pd.256	case Intrinsic::x86_avx_hadd_pd_256: // llvm.x86.avx.hadd.pd.256
	case Intrinsic::x86_avx_hsub_pd_256: // llvm.x86.avx.hsub.pd.256	case Intrinsic::x86_avx_hsub_pd_256: // llvm.x86.avx.hsub.pd.256
	case Intrinsic::x86_avx_max_pd_256: // llvm.x86.avx.max.pd.256	case Intrinsic::x86_avx_max_pd_256: // llvm.x86.avx.max.pd.256

	skipping to change at line 11946	skipping to change at line 22239
	ArgTys.push_back(IntegerType::get(Context, 32));	ArgTys.push_back(IntegerType::get(Context, 32));
	break;	break;
	case Intrinsic::x86_avx_cmp_pd_256: // llvm.x86.avx.cmp.pd.256	case Intrinsic::x86_avx_cmp_pd_256: // llvm.x86.avx.cmp.pd.256
	case Intrinsic::x86_avx_vperm2f128_pd_256: // llvm.x86.avx.vper m2f128.pd.256	case Intrinsic::x86_avx_vperm2f128_pd_256: // llvm.x86.avx.vper m2f128.pd.256
	ResultTy = VectorType::get(Type::getDoubleTy(Context), 4);	ResultTy = VectorType::get(Type::getDoubleTy(Context), 4);
	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 4));	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 4));
	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 4));	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 4));
	ArgTys.push_back(IntegerType::get(Context, 8));	ArgTys.push_back(IntegerType::get(Context, 8));
	break;	break;
	case Intrinsic::x86_avx_blendv_pd_256: // llvm.x86.avx.blen dv.pd.256	case Intrinsic::x86_avx_blendv_pd_256: // llvm.x86.avx.blen dv.pd.256

		case Intrinsic::x86_fma4_vfmadd_pd_256: // llvm.x86.fma4.vfm
		add.pd.256
		case Intrinsic::x86_fma4_vfmaddsub_pd_256: // llvm.x86.fma4.vfm
		addsub.pd.256
		case Intrinsic::x86_fma4_vfmsub_pd_256: // llvm.x86.fma4.vfm
		sub.pd.256
		case Intrinsic::x86_fma4_vfmsubadd_pd_256: // llvm.x86.fma4.vfm
		subadd.pd.256
		case Intrinsic::x86_fma4_vfnmadd_pd_256: // llvm.x86.fma4.vfn
		madd.pd.256
		case Intrinsic::x86_fma4_vfnmsub_pd_256: // llvm.x86.fma4.vfn
		msub.pd.256
		ResultTy = VectorType::get(Type::getDoubleTy(Context), 4);
		ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 4));
		ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 4));
		ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 4));
		break;
		case Intrinsic::x86_xop_vpermil2pd_256: // llvm.x86.xop.vper
		mil2pd.256
	ResultTy = VectorType::get(Type::getDoubleTy(Context), 4);	ResultTy = VectorType::get(Type::getDoubleTy(Context), 4);
	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 4));	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 4));
	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 4));	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 4));
	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 4));	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 4));

		ArgTys.push_back(IntegerType::get(Context, 8));
	break;	break;
	case Intrinsic::x86_avx_vpermilvar_pd_256: // llvm.x86.avx.vper milvar.pd.256	case Intrinsic::x86_avx_vpermilvar_pd_256: // llvm.x86.avx.vper milvar.pd.256
	ResultTy = VectorType::get(Type::getDoubleTy(Context), 4);	ResultTy = VectorType::get(Type::getDoubleTy(Context), 4);
	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 4));	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 4));
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 4));	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 4));
	break;	break;
	case Intrinsic::x86_avx_cvtdq2_pd_256: // llvm.x86.avx.cvtd q2.pd.256	case Intrinsic::x86_avx_cvtdq2_pd_256: // llvm.x86.avx.cvtd q2.pd.256
	ResultTy = VectorType::get(Type::getDoubleTy(Context), 4);	ResultTy = VectorType::get(Type::getDoubleTy(Context), 4);
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
	break;	break;
	case Intrinsic::arm_neon_vcvtfp2hf: // llvm.arm.neon.vcvtfp2hf	case Intrinsic::arm_neon_vcvtfp2hf: // llvm.arm.neon.vcvtfp2hf
	ResultTy = VectorType::get(IntegerType::get(Context, 16), 4);	ResultTy = VectorType::get(IntegerType::get(Context, 16), 4);
	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
	break;	break;
	case Intrinsic::ppc_altivec_lvewx: // llvm.ppc.altivec.lvewx	case Intrinsic::ppc_altivec_lvewx: // llvm.ppc.altivec.lvewx
	case Intrinsic::ppc_altivec_lvx: // llvm.ppc.altivec.lvx	case Intrinsic::ppc_altivec_lvx: // llvm.ppc.altivec.lvx
	case Intrinsic::ppc_altivec_lvxl: // llvm.ppc.altivec.lvxl	case Intrinsic::ppc_altivec_lvxl: // llvm.ppc.altivec.lvxl
	ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);	ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);
	ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));	ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
	break;	break;

		case Intrinsic::x86_avx2_maskload_d: // llvm.x86.avx2.maskload.d
		ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);
		ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
		break;
	case Intrinsic::x86_sse41_pmovsxbd: // llvm.x86.sse41.pmovsxbd	case Intrinsic::x86_sse41_pmovsxbd: // llvm.x86.sse41.pmovsxbd
	case Intrinsic::x86_sse41_pmovzxbd: // llvm.x86.sse41.pmovzxbd	case Intrinsic::x86_sse41_pmovzxbd: // llvm.x86.sse41.pmovzxbd

		case Intrinsic::x86_xop_vphaddbd: // llvm.x86.xop.vphaddbd
		case Intrinsic::x86_xop_vphaddubd: // llvm.x86.xop.vphaddubd
	ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);	ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
	break;	break;
	case Intrinsic::ppc_altivec_vmsummbm: // llvm.ppc.altivec. vmsummbm	case Intrinsic::ppc_altivec_vmsummbm: // llvm.ppc.altivec. vmsummbm
	case Intrinsic::ppc_altivec_vmsumubm: // llvm.ppc.altivec. vmsumubm	case Intrinsic::ppc_altivec_vmsumubm: // llvm.ppc.altivec. vmsumubm
	ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);	ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
	break;	break;

	skipping to change at line 12019	skipping to change at line 22332
	case Intrinsic::ppc_altivec_vcmpgtfp: // llvm.ppc.altivec. vcmpgtfp	case Intrinsic::ppc_altivec_vcmpgtfp: // llvm.ppc.altivec. vcmpgtfp
	ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);	ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);
	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
	break;	break;
	case Intrinsic::x86_avx_cvt_pd2dq_256: // llvm.x86.avx.cvt. pd2dq.256	case Intrinsic::x86_avx_cvt_pd2dq_256: // llvm.x86.avx.cvt. pd2dq.256
	case Intrinsic::x86_avx_cvtt_pd2dq_256: // llvm.x86.avx.cvtt .pd2dq.256	case Intrinsic::x86_avx_cvtt_pd2dq_256: // llvm.x86.avx.cvtt .pd2dq.256
	ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);	ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);
	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 4));	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 4));
	break;	break;

		case Intrinsic::x86_avx2_pbroadcastd_128: // llvm.x86.avx2.pbr oadcastd.128
	case Intrinsic::x86_ssse3_pabs_d_128: // llvm.x86.ssse3.pa bs.d.128	case Intrinsic::x86_ssse3_pabs_d_128: // llvm.x86.ssse3.pa bs.d.128
	ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);	ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
	break;	break;
	case Intrinsic::spu_si_shli: // llvm.spu.si.shli	case Intrinsic::spu_si_shli: // llvm.spu.si.shli
	ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);	ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
	ArgTys.push_back(IntegerType::get(Context, 8));	ArgTys.push_back(IntegerType::get(Context, 8));
	break;	break;
	case Intrinsic::spu_si_ai: // llvm.spu.si.ai	case Intrinsic::spu_si_ai: // llvm.spu.si.ai

	skipping to change at line 12090	skipping to change at line 22404
	case Intrinsic::spu_si_cgt: // llvm.spu.si.cgt	case Intrinsic::spu_si_cgt: // llvm.spu.si.cgt
	case Intrinsic::spu_si_cgx: // llvm.spu.si.cgx	case Intrinsic::spu_si_cgx: // llvm.spu.si.cgx
	case Intrinsic::spu_si_clgt: // llvm.spu.si.clgt	case Intrinsic::spu_si_clgt: // llvm.spu.si.clgt
	case Intrinsic::spu_si_nand: // llvm.spu.si.nand	case Intrinsic::spu_si_nand: // llvm.spu.si.nand
	case Intrinsic::spu_si_nor: // llvm.spu.si.nor	case Intrinsic::spu_si_nor: // llvm.spu.si.nor
	case Intrinsic::spu_si_or: // llvm.spu.si.or	case Intrinsic::spu_si_or: // llvm.spu.si.or
	case Intrinsic::spu_si_orc: // llvm.spu.si.orc	case Intrinsic::spu_si_orc: // llvm.spu.si.orc
	case Intrinsic::spu_si_sf: // llvm.spu.si.sf	case Intrinsic::spu_si_sf: // llvm.spu.si.sf
	case Intrinsic::spu_si_sfx: // llvm.spu.si.sfx	case Intrinsic::spu_si_sfx: // llvm.spu.si.sfx
	case Intrinsic::spu_si_xor: // llvm.spu.si.xor	case Intrinsic::spu_si_xor: // llvm.spu.si.xor

	case Intrinsic::x86_sse2_pcmpeq_d: // llvm.x86.sse2.pcmpeq.d	case Intrinsic::x86_avx2_psllv_d: // llvm.x86.avx2.psllv.d
	case Intrinsic::x86_sse2_pcmpgt_d: // llvm.x86.sse2.pcmpgt.d	case Intrinsic::x86_avx2_psrav_d: // llvm.x86.avx2.psrav.d
		case Intrinsic::x86_avx2_psrlv_d: // llvm.x86.avx2.psrlv.d
	case Intrinsic::x86_sse2_psll_d: // llvm.x86.sse2.psll.d	case Intrinsic::x86_sse2_psll_d: // llvm.x86.sse2.psll.d
	case Intrinsic::x86_sse2_psra_d: // llvm.x86.sse2.psra.d	case Intrinsic::x86_sse2_psra_d: // llvm.x86.sse2.psra.d
	case Intrinsic::x86_sse2_psrl_d: // llvm.x86.sse2.psrl.d	case Intrinsic::x86_sse2_psrl_d: // llvm.x86.sse2.psrl.d
	case Intrinsic::x86_sse41_pmaxsd: // llvm.x86.sse41.pmaxsd	case Intrinsic::x86_sse41_pmaxsd: // llvm.x86.sse41.pmaxsd
	case Intrinsic::x86_sse41_pmaxud: // llvm.x86.sse41.pmaxud	case Intrinsic::x86_sse41_pmaxud: // llvm.x86.sse41.pmaxud
	case Intrinsic::x86_sse41_pminsd: // llvm.x86.sse41.pminsd	case Intrinsic::x86_sse41_pminsd: // llvm.x86.sse41.pminsd
	case Intrinsic::x86_sse41_pminud: // llvm.x86.sse41.pminud	case Intrinsic::x86_sse41_pminud: // llvm.x86.sse41.pminud
	case Intrinsic::x86_ssse3_phadd_d_128: // llvm.x86.ssse3.ph add.d.128	case Intrinsic::x86_ssse3_phadd_d_128: // llvm.x86.ssse3.ph add.d.128

	case Intrinsic::x86_ssse3_phadd_sw_128: // llvm.x86.ssse3.ph add.sw.128
	case Intrinsic::x86_ssse3_phsub_d_128: // llvm.x86.ssse3.ph sub.d.128	case Intrinsic::x86_ssse3_phsub_d_128: // llvm.x86.ssse3.ph sub.d.128
	case Intrinsic::x86_ssse3_psign_d_128: // llvm.x86.ssse3.ps ign.d.128	case Intrinsic::x86_ssse3_psign_d_128: // llvm.x86.ssse3.ps ign.d.128

		case Intrinsic::x86_xop_vpcomeqd: // llvm.x86.xop.vpcomeqd
		case Intrinsic::x86_xop_vpcomequd: // llvm.x86.xop.vpcomequd
		case Intrinsic::x86_xop_vpcomfalsed: // llvm.x86.xop.vpcomfalsed
		case Intrinsic::x86_xop_vpcomfalseud: // llvm.x86.xop.vpco
		mfalseud
		case Intrinsic::x86_xop_vpcomged: // llvm.x86.xop.vpcomged
		case Intrinsic::x86_xop_vpcomgeud: // llvm.x86.xop.vpcomgeud
		case Intrinsic::x86_xop_vpcomgtd: // llvm.x86.xop.vpcomgtd
		case Intrinsic::x86_xop_vpcomgtud: // llvm.x86.xop.vpcomgtud
		case Intrinsic::x86_xop_vpcomled: // llvm.x86.xop.vpcomled
		case Intrinsic::x86_xop_vpcomleud: // llvm.x86.xop.vpcomleud
		case Intrinsic::x86_xop_vpcomltd: // llvm.x86.xop.vpcomltd
		case Intrinsic::x86_xop_vpcomltud: // llvm.x86.xop.vpcomltud
		case Intrinsic::x86_xop_vpcomned: // llvm.x86.xop.vpcomned
		case Intrinsic::x86_xop_vpcomneud: // llvm.x86.xop.vpcomneud
		case Intrinsic::x86_xop_vpcomtrued: // llvm.x86.xop.vpcomtrued
		case Intrinsic::x86_xop_vpcomtrueud: // llvm.x86.xop.vpcomtrueud
		case Intrinsic::x86_xop_vprotd: // llvm.x86.xop.vprotd
		case Intrinsic::x86_xop_vpshad: // llvm.x86.xop.vpshad
		case Intrinsic::x86_xop_vpshld: // llvm.x86.xop.vpshld
		ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
		break;
		case Intrinsic::x86_avx2_pblendd_128: // llvm.x86.avx2.pbl
		endd.128
		ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
		ArgTys.push_back(IntegerType::get(Context, 32));
		break;
		case Intrinsic::ppc_altivec_vperm: // llvm.ppc.altivec.vperm
		ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
		break;
		case Intrinsic::ppc_altivec_vsel: // llvm.ppc.altivec.vsel
		case Intrinsic::x86_xop_vpmacsdd: // llvm.x86.xop.vpmacsdd
		case Intrinsic::x86_xop_vpmacssdd: // llvm.x86.xop.vpmacssdd
		ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
		break;
		case Intrinsic::spu_si_mpyh: // llvm.spu.si.mpyh
		ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
		break;
		case Intrinsic::ppc_altivec_vupkhpx: // llvm.ppc.altivec.vupkhpx
		case Intrinsic::ppc_altivec_vupkhsh: // llvm.ppc.altivec.vupkhsh
		case Intrinsic::ppc_altivec_vupklpx: // llvm.ppc.altivec.vupklpx
		case Intrinsic::ppc_altivec_vupklsh: // llvm.ppc.altivec.vupklsh
		case Intrinsic::x86_sse41_pmovsxwd: // llvm.x86.sse41.pmovsxwd
		case Intrinsic::x86_sse41_pmovzxwd: // llvm.x86.sse41.pmovzxwd
		case Intrinsic::x86_xop_vphadduwd: // llvm.x86.xop.vphadduwd
		case Intrinsic::x86_xop_vphaddwd: // llvm.x86.xop.vphaddwd
		case Intrinsic::x86_xop_vphsubwd: // llvm.x86.xop.vphsubwd
		ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
		break;
		case Intrinsic::spu_si_mpyi: // llvm.spu.si.mpyi
		case Intrinsic::spu_si_mpyui: // llvm.spu.si.mpyui
		ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
		ArgTys.push_back(IntegerType::get(Context, 16));
		break;
		case Intrinsic::ppc_altivec_vsum4shs: // llvm.ppc.altivec.
		vsum4shs
		ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
		break;
		case Intrinsic::ppc_altivec_vmulesh: // llvm.ppc.altivec.vmulesh
		case Intrinsic::ppc_altivec_vmuleuh: // llvm.ppc.altivec.vmuleuh
		case Intrinsic::ppc_altivec_vmulosh: // llvm.ppc.altivec.vmulosh
		case Intrinsic::ppc_altivec_vmulouh: // llvm.ppc.altivec.vmulouh
		case Intrinsic::spu_si_mpy: // llvm.spu.si.mpy
		case Intrinsic::spu_si_mpyhh: // llvm.spu.si.mpyhh
		case Intrinsic::spu_si_mpyhha: // llvm.spu.si.mpyhha
		case Intrinsic::spu_si_mpyhhau: // llvm.spu.si.mpyhhau
		case Intrinsic::spu_si_mpyhhu: // llvm.spu.si.mpyhhu
		case Intrinsic::spu_si_mpys: // llvm.spu.si.mpys
		case Intrinsic::spu_si_mpyu: // llvm.spu.si.mpyu
		case Intrinsic::x86_sse2_pmadd_wd: // llvm.x86.sse2.pmadd.wd
		ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
		break;
		case Intrinsic::ppc_altivec_vmsumshm: // llvm.ppc.altivec.
		vmsumshm
		case Intrinsic::ppc_altivec_vmsumshs: // llvm.ppc.altivec.
		vmsumshs
		case Intrinsic::ppc_altivec_vmsumuhm: // llvm.ppc.altivec.
		vmsumuhm
		case Intrinsic::ppc_altivec_vmsumuhs: // llvm.ppc.altivec.
		vmsumuhs
		case Intrinsic::x86_xop_vpmacsswd: // llvm.x86.xop.vpmacsswd
		case Intrinsic::x86_xop_vpmacswd: // llvm.x86.xop.vpmacswd
		case Intrinsic::x86_xop_vpmadcsswd: // llvm.x86.xop.vpmadcsswd
		case Intrinsic::x86_xop_vpmadcswd: // llvm.x86.xop.vpmadcswd
	ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);	ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);

		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));

		break;
		case Intrinsic::spu_si_mpya: // llvm.spu.si.mpya
		ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
		break;
		case Intrinsic::x86_avx_vextractf128_si_256: // llvm.x86.avx.vext
		ractf128.si.256
		ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 8));
		ArgTys.push_back(IntegerType::get(Context, 8));
		break;
		case Intrinsic::x86_avx2_movntdqa: // llvm.x86.avx2.movntdqa
		case Intrinsic::x86_avx2_vbroadcasti128: // llvm.x86.avx2.vbr
		oadcasti128
		ResultTy = VectorType::get(IntegerType::get(Context, 64), 4);
		ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
		break;
		case Intrinsic::x86_avx2_maskload_q_256: // llvm.x86.avx2.mas
		kload.q.256
		ResultTy = VectorType::get(IntegerType::get(Context, 64), 4);
		ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 4));
		break;
		case Intrinsic::x86_avx2_pmovsxbq: // llvm.x86.avx2.pmovsxbq
		case Intrinsic::x86_avx2_pmovzxbq: // llvm.x86.avx2.pmovzxbq
		ResultTy = VectorType::get(IntegerType::get(Context, 64), 4);
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
		break;
		case Intrinsic::x86_avx2_pbroadcastq_256: // llvm.x86.avx2.pbr
		oadcastq.256
		ResultTy = VectorType::get(IntegerType::get(Context, 64), 4);
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 2));
		break;
		case Intrinsic::x86_avx2_psad_bw: // llvm.x86.avx2.psad.bw
		ResultTy = VectorType::get(IntegerType::get(Context, 64), 4);
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 32));
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 32));
		break;
		case Intrinsic::x86_avx2_pmovsxdq: // llvm.x86.avx2.pmovsxdq
		case Intrinsic::x86_avx2_pmovzxdq: // llvm.x86.avx2.pmovzxdq
		ResultTy = VectorType::get(IntegerType::get(Context, 64), 4);
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
	break;	break;

	case Intrinsic::ppc_altivec_vperm: // llvm.ppc.altivec.vperm	case Intrinsic::x86_avx2_psll_dq: // llvm.x86.avx2.psll.dq
	ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);	case Intrinsic::x86_avx2_psll_dq_bs: // llvm.x86.avx2.psll.dq.bs
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));	case Intrinsic::x86_avx2_pslli_q: // llvm.x86.avx2.pslli.q
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));	case Intrinsic::x86_avx2_psrl_dq: // llvm.x86.avx2.psrl.dq
		case Intrinsic::x86_avx2_psrl_dq_bs: // llvm.x86.avx2.psrl.dq.bs
		case Intrinsic::x86_avx2_psrli_q: // llvm.x86.avx2.psrli.q
		ResultTy = VectorType::get(IntegerType::get(Context, 64), 4);
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 4));
		ArgTys.push_back(IntegerType::get(Context, 32));
		break;
		case Intrinsic::x86_avx2_psll_q: // llvm.x86.avx2.psll.q
		case Intrinsic::x86_avx2_psrl_q: // llvm.x86.avx2.psrl.q
		ResultTy = VectorType::get(IntegerType::get(Context, 64), 4);
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 4));
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 2));
		break;
		case Intrinsic::x86_avx2_vinserti128: // llvm.x86.avx2.vin
		serti128
		ResultTy = VectorType::get(IntegerType::get(Context, 64), 4);
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 4));
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 2));
		ArgTys.push_back(IntegerType::get(Context, 8));
		break;
		case Intrinsic::x86_avx2_psllv_q_256: // llvm.x86.avx2.psl
		lv.q.256
		case Intrinsic::x86_avx2_psrlv_q_256: // llvm.x86.avx2.psr
		lv.q.256
		ResultTy = VectorType::get(IntegerType::get(Context, 64), 4);
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 4));
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 4));
		break;
		case Intrinsic::x86_avx2_vperm2i128: // llvm.x86.avx2.vperm2i128
		ResultTy = VectorType::get(IntegerType::get(Context, 64), 4);
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 4));
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 4));
		ArgTys.push_back(IntegerType::get(Context, 8));
		break;
		case Intrinsic::x86_xop_vpcmov_256: // llvm.x86.xop.vpcmov.256
		ResultTy = VectorType::get(IntegerType::get(Context, 64), 4);
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 4));
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 4));
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 4));
		break;
		case Intrinsic::x86_avx2_pmovsxwq: // llvm.x86.avx2.pmovsxwq
		case Intrinsic::x86_avx2_pmovzxwq: // llvm.x86.avx2.pmovzxwq
		ResultTy = VectorType::get(IntegerType::get(Context, 64), 4);
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
		break;
		case Intrinsic::x86_avx2_pmul_dq: // llvm.x86.avx2.pmul.dq
		case Intrinsic::x86_avx2_pmulu_dq: // llvm.x86.avx2.pmulu.dq
		ResultTy = VectorType::get(IntegerType::get(Context, 64), 4);
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 8));
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 8));
		break;
		case Intrinsic::x86_avx_vbroadcast_ss_256: // llvm.x86.avx.vbro
		adcast.ss.256
		case Intrinsic::x86_avx_vbroadcastf128_ps_256: // llvm.x86.
		avx.vbroadcastf128.ps.256
		ResultTy = VectorType::get(Type::getFloatTy(Context), 8);
		ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
		break;
		case Intrinsic::x86_avx_maskload_ps_256: // llvm.x86.avx.mask
		load.ps.256
		ResultTy = VectorType::get(Type::getFloatTy(Context), 8);
		ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
		ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 8));
		break;
		case Intrinsic::x86_avx2_vbroadcast_ss_ps_256: // llvm.x86.
		avx2.vbroadcast.ss.ps.256
		ResultTy = VectorType::get(Type::getFloatTy(Context), 8);
		ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
		break;
		case Intrinsic::x86_avx_rcp_ps_256: // llvm.x86.avx.rcp.ps.256
		case Intrinsic::x86_avx_rsqrt_ps_256: // llvm.x86.avx.rsqr
		t.ps.256
		case Intrinsic::x86_avx_sqrt_ps_256: // llvm.x86.avx.sqrt.ps.256
		case Intrinsic::x86_xop_vfrcz_ps_256: // llvm.x86.xop.vfrc
		z.ps.256
		ResultTy = VectorType::get(Type::getFloatTy(Context), 8);
		ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 8));
		break;
		case Intrinsic::x86_avx_round_ps_256: // llvm.x86.avx.roun
		d.ps.256
		ResultTy = VectorType::get(Type::getFloatTy(Context), 8);
		ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 8));
		ArgTys.push_back(IntegerType::get(Context, 32));
		break;
		case Intrinsic::x86_avx_vinsertf128_ps_256: // llvm.x86.avx.vins
		ertf128.ps.256
		ResultTy = VectorType::get(Type::getFloatTy(Context), 8);
		ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 8));
		ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
		ArgTys.push_back(IntegerType::get(Context, 8));
		break;
		case Intrinsic::x86_avx2_permps: // llvm.x86.avx2.permps
		case Intrinsic::x86_avx_addsub_ps_256: // llvm.x86.avx.adds
		ub.ps.256
		case Intrinsic::x86_avx_hadd_ps_256: // llvm.x86.avx.hadd.ps.256
		case Intrinsic::x86_avx_hsub_ps_256: // llvm.x86.avx.hsub.ps.256
		case Intrinsic::x86_avx_max_ps_256: // llvm.x86.avx.max.ps.256
		case Intrinsic::x86_avx_min_ps_256: // llvm.x86.avx.min.ps.256
		ResultTy = VectorType::get(Type::getFloatTy(Context), 8);
		ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 8));
		ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 8));
		break;
		case Intrinsic::x86_avx_blend_ps_256: // llvm.x86.avx.blen
		d.ps.256
		case Intrinsic::x86_avx_dp_ps_256: // llvm.x86.avx.dp.ps.256
		ResultTy = VectorType::get(Type::getFloatTy(Context), 8);
		ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 8));
		ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 8));
		ArgTys.push_back(IntegerType::get(Context, 32));
		break;
		case Intrinsic::x86_avx_cmp_ps_256: // llvm.x86.avx.cmp.ps.256
		case Intrinsic::x86_avx_vperm2f128_ps_256: // llvm.x86.avx.vper
		m2f128.ps.256
		ResultTy = VectorType::get(Type::getFloatTy(Context), 8);
		ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 8));
		ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 8));
		ArgTys.push_back(IntegerType::get(Context, 8));
		break;
		case Intrinsic::x86_avx_blendv_ps_256: // llvm.x86.avx.blen
		dv.ps.256
		case Intrinsic::x86_fma4_vfmadd_ps_256: // llvm.x86.fma4.vfm
		add.ps.256
		case Intrinsic::x86_fma4_vfmaddsub_ps_256: // llvm.x86.fma4.vfm
		addsub.ps.256
		case Intrinsic::x86_fma4_vfmsub_ps_256: // llvm.x86.fma4.vfm
		sub.ps.256
		case Intrinsic::x86_fma4_vfmsubadd_ps_256: // llvm.x86.fma4.vfm
		subadd.ps.256
		case Intrinsic::x86_fma4_vfnmadd_ps_256: // llvm.x86.fma4.vfn
		madd.ps.256
		case Intrinsic::x86_fma4_vfnmsub_ps_256: // llvm.x86.fma4.vfn
		msub.ps.256
		ResultTy = VectorType::get(Type::getFloatTy(Context), 8);
		ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 8));
		ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 8));
		ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 8));
		break;
		case Intrinsic::x86_xop_vpermil2ps_256: // llvm.x86.xop.vper
		mil2ps.256
		ResultTy = VectorType::get(Type::getFloatTy(Context), 8);
		ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 8));
		ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 8));
		ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 8));
		ArgTys.push_back(IntegerType::get(Context, 8));
		break;
		case Intrinsic::x86_avx_vpermilvar_ps_256: // llvm.x86.avx.vper
		milvar.ps.256
		ResultTy = VectorType::get(Type::getFloatTy(Context), 8);
		ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 8));
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 8));
		break;
		case Intrinsic::x86_vcvtph2ps_256: // llvm.x86.vcvtph2ps.256
		ResultTy = VectorType::get(Type::getFloatTy(Context), 8);
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
		break;
		case Intrinsic::x86_avx_cvtdq2_ps_256: // llvm.x86.avx.cvtd
		q2.ps.256
		ResultTy = VectorType::get(Type::getFloatTy(Context), 8);
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 8));
		break;
		case Intrinsic::ppc_altivec_mfvscr: // llvm.ppc.altivec.mfvscr
		ResultTy = VectorType::get(IntegerType::get(Context, 16), 8);
		break;
		case Intrinsic::ppc_altivec_lvehx: // llvm.ppc.altivec.lvehx
		ResultTy = VectorType::get(IntegerType::get(Context, 16), 8);
		ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
		break;
		case Intrinsic::ppc_altivec_vupkhsb: // llvm.ppc.altivec.vupkhsb
		case Intrinsic::ppc_altivec_vupklsb: // llvm.ppc.altivec.vupklsb
		case Intrinsic::x86_sse41_pmovsxbw: // llvm.x86.sse41.pmovsxbw
		case Intrinsic::x86_sse41_pmovzxbw: // llvm.x86.sse41.pmovzxbw
		case Intrinsic::x86_xop_vphaddbw: // llvm.x86.xop.vphaddbw
		case Intrinsic::x86_xop_vphaddubw: // llvm.x86.xop.vphaddubw
		case Intrinsic::x86_xop_vphsubbw: // llvm.x86.xop.vphsubbw
		ResultTy = VectorType::get(IntegerType::get(Context, 16), 8);
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
	break;	break;

	case Intrinsic::ppc_altivec_vsel: // llvm.ppc.altivec.vsel	case Intrinsic::ppc_altivec_vmulesb: // llvm.ppc.altivec.vmulesb
	ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);	case Intrinsic::ppc_altivec_vmuleub: // llvm.ppc.altivec.vmuleub
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));	case Intrinsic::ppc_altivec_vmulosb: // llvm.ppc.altivec.vmulosb
		case Intrinsic::ppc_altivec_vmuloub: // llvm.ppc.altivec.vmuloub
		case Intrinsic::x86_ssse3_pmadd_ub_sw_128: // llvm.x86.ssse3.pm
		add.ub.sw.128
		ResultTy = VectorType::get(IntegerType::get(Context, 16), 8);
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
		break;
		case Intrinsic::x86_sse41_mpsadbw: // llvm.x86.sse41.mpsadbw
		ResultTy = VectorType::get(IntegerType::get(Context, 16), 8);
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
		ArgTys.push_back(IntegerType::get(Context, 32));
		break;
		case Intrinsic::x86_vcvtps2ph_128: // llvm.x86.vcvtps2ph.128
		ResultTy = VectorType::get(IntegerType::get(Context, 16), 8);
		ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
		ArgTys.push_back(IntegerType::get(Context, 32));
		break;
		case Intrinsic::ppc_altivec_vpkpx: // llvm.ppc.altivec.vpkpx
		case Intrinsic::ppc_altivec_vpkswus: // llvm.ppc.altivec.vpkswus
		case Intrinsic::ppc_altivec_vpkuwus: // llvm.ppc.altivec.vpkuwus
		case Intrinsic::x86_sse2_packssdw_128: // llvm.x86.sse2.pac
		kssdw.128
		case Intrinsic::x86_sse41_packusdw: // llvm.x86.sse41.packusdw
		ResultTy = VectorType::get(IntegerType::get(Context, 16), 8);
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
	break;	break;

	case Intrinsic::spu_si_mpyh: // llvm.spu.si.mpyh	case Intrinsic::x86_vcvtps2ph_256: // llvm.x86.vcvtps2ph.256
	ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);	ResultTy = VectorType::get(IntegerType::get(Context, 16), 8);
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 8));
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));	ArgTys.push_back(IntegerType::get(Context, 32));
	break;	break;

	case Intrinsic::ppc_altivec_vupkhpx: // llvm.ppc.altivec.vupkhpx	case Intrinsic::x86_avx2_pbroadcastw_128: // llvm.x86.avx2.pbr
	case Intrinsic::ppc_altivec_vupkhsh: // llvm.ppc.altivec.vupkhsh	oadcastw.128
	case Intrinsic::ppc_altivec_vupklpx: // llvm.ppc.altivec.vupklpx	case Intrinsic::x86_sse41_phminposuw: // llvm.x86.sse41.ph
	case Intrinsic::ppc_altivec_vupklsh: // llvm.ppc.altivec.vupklsh	minposuw
	case Intrinsic::x86_sse41_pmovsxwd: // llvm.x86.sse41.pmovsxwd	case Intrinsic::x86_ssse3_pabs_w_128: // llvm.x86.ssse3.pa
	case Intrinsic::x86_sse41_pmovzxwd: // llvm.x86.sse41.pmovzxwd	bs.w.128
	ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);	ResultTy = VectorType::get(IntegerType::get(Context, 16), 8);
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
	break;	break;

	case Intrinsic::spu_si_mpyi: // llvm.spu.si.mpyi	case Intrinsic::spu_si_ahi: // llvm.spu.si.ahi
	case Intrinsic::spu_si_mpyui: // llvm.spu.si.mpyui	case Intrinsic::spu_si_andhi: // llvm.spu.si.andhi
	ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);	case Intrinsic::spu_si_ceqhi: // llvm.spu.si.ceqhi
		case Intrinsic::spu_si_cgthi: // llvm.spu.si.cgthi
		case Intrinsic::spu_si_clgthi: // llvm.spu.si.clgthi
		case Intrinsic::spu_si_fsmbi: // llvm.spu.si.fsmbi
		case Intrinsic::spu_si_orhi: // llvm.spu.si.orhi
		case Intrinsic::spu_si_sfhi: // llvm.spu.si.sfhi
		case Intrinsic::spu_si_xorhi: // llvm.spu.si.xorhi
		ResultTy = VectorType::get(IntegerType::get(Context, 16), 8);
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
	ArgTys.push_back(IntegerType::get(Context, 16));	ArgTys.push_back(IntegerType::get(Context, 16));
	break;	break;

	case Intrinsic::ppc_altivec_vsum4shs: // llvm.ppc.altivec.	case Intrinsic::spu_si_shlqbi: // llvm.spu.si.shlqbi
	vsum4shs	case Intrinsic::spu_si_shlqby: // llvm.spu.si.shlqby
	ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);	case Intrinsic::x86_sse2_pslli_w: // llvm.x86.sse2.pslli.w
		case Intrinsic::x86_sse2_psrai_w: // llvm.x86.sse2.psrai.w
		case Intrinsic::x86_sse2_psrli_w: // llvm.x86.sse2.psrli.w
		ResultTy = VectorType::get(IntegerType::get(Context, 16), 8);
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));

	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));	ArgTys.push_back(IntegerType::get(Context, 32));
	break;	break;

	case Intrinsic::ppc_altivec_vmulesh: // llvm.ppc.altivec.vmulesh	case Intrinsic::ppc_altivec_vaddshs: // llvm.ppc.altivec.vaddshs
	case Intrinsic::ppc_altivec_vmuleuh: // llvm.ppc.altivec.vmuleuh	case Intrinsic::ppc_altivec_vadduhs: // llvm.ppc.altivec.vadduhs
	case Intrinsic::ppc_altivec_vmulosh: // llvm.ppc.altivec.vmulosh	case Intrinsic::ppc_altivec_vavgsh: // llvm.ppc.altivec.vavgsh
	case Intrinsic::ppc_altivec_vmulouh: // llvm.ppc.altivec.vmulouh	case Intrinsic::ppc_altivec_vavguh: // llvm.ppc.altivec.vavguh
	case Intrinsic::spu_si_mpy: // llvm.spu.si.mpy	case Intrinsic::ppc_altivec_vcmpequh: // llvm.ppc.altivec.
	case Intrinsic::spu_si_mpyhh: // llvm.spu.si.mpyhh	vcmpequh
	case Intrinsic::spu_si_mpyhha: // llvm.spu.si.mpyhha	case Intrinsic::ppc_altivec_vcmpgtsh: // llvm.ppc.altivec.
	case Intrinsic::spu_si_mpyhhau: // llvm.spu.si.mpyhhau	vcmpgtsh
	case Intrinsic::spu_si_mpyhhu: // llvm.spu.si.mpyhhu	case Intrinsic::ppc_altivec_vcmpgtuh: // llvm.ppc.altivec.
	case Intrinsic::spu_si_mpys: // llvm.spu.si.mpys	vcmpgtuh
	case Intrinsic::spu_si_mpyu: // llvm.spu.si.mpyu	case Intrinsic::ppc_altivec_vmaxsh: // llvm.ppc.altivec.vmaxsh
	case Intrinsic::x86_sse2_pmadd_wd: // llvm.x86.sse2.pmadd.wd	case Intrinsic::ppc_altivec_vmaxuh: // llvm.ppc.altivec.vmaxuh
	ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);	case Intrinsic::ppc_altivec_vminsh: // llvm.ppc.altivec.vminsh
		case Intrinsic::ppc_altivec_vminuh: // llvm.ppc.altivec.vminuh
		case Intrinsic::ppc_altivec_vrlh: // llvm.ppc.altivec.vrlh
		case Intrinsic::ppc_altivec_vslh: // llvm.ppc.altivec.vslh
		case Intrinsic::ppc_altivec_vsrah: // llvm.ppc.altivec.vsrah
		case Intrinsic::ppc_altivec_vsrh: // llvm.ppc.altivec.vsrh
		case Intrinsic::ppc_altivec_vsubshs: // llvm.ppc.altivec.vsubshs
		case Intrinsic::ppc_altivec_vsubuhs: // llvm.ppc.altivec.vsubuhs
		case Intrinsic::spu_si_ah: // llvm.spu.si.ah
		case Intrinsic::spu_si_ceqh: // llvm.spu.si.ceqh
		case Intrinsic::spu_si_cgth: // llvm.spu.si.cgth
		case Intrinsic::spu_si_clgth: // llvm.spu.si.clgth
		case Intrinsic::spu_si_sfh: // llvm.spu.si.sfh
		case Intrinsic::x86_sse2_padds_w: // llvm.x86.sse2.padds.w
		case Intrinsic::x86_sse2_paddus_w: // llvm.x86.sse2.paddus.w
		case Intrinsic::x86_sse2_pavg_w: // llvm.x86.sse2.pavg.w
		case Intrinsic::x86_sse2_pmaxs_w: // llvm.x86.sse2.pmaxs.w
		case Intrinsic::x86_sse2_pmins_w: // llvm.x86.sse2.pmins.w
		case Intrinsic::x86_sse2_pmulh_w: // llvm.x86.sse2.pmulh.w
		case Intrinsic::x86_sse2_pmulhu_w: // llvm.x86.sse2.pmulhu.w
		case Intrinsic::x86_sse2_psll_w: // llvm.x86.sse2.psll.w
		case Intrinsic::x86_sse2_psra_w: // llvm.x86.sse2.psra.w
		case Intrinsic::x86_sse2_psrl_w: // llvm.x86.sse2.psrl.w
		case Intrinsic::x86_sse2_psubs_w: // llvm.x86.sse2.psubs.w
		case Intrinsic::x86_sse2_psubus_w: // llvm.x86.sse2.psubus.w
		case Intrinsic::x86_sse41_pmaxuw: // llvm.x86.sse41.pmaxuw
		case Intrinsic::x86_sse41_pminuw: // llvm.x86.sse41.pminuw
		case Intrinsic::x86_ssse3_phadd_sw_128: // llvm.x86.ssse3.ph
		add.sw.128
		case Intrinsic::x86_ssse3_phadd_w_128: // llvm.x86.ssse3.ph
		add.w.128
		case Intrinsic::x86_ssse3_phsub_sw_128: // llvm.x86.ssse3.ph
		sub.sw.128
		case Intrinsic::x86_ssse3_phsub_w_128: // llvm.x86.ssse3.ph
		sub.w.128
		case Intrinsic::x86_ssse3_pmul_hr_sw_128: // llvm.x86.ssse3.pm
		ul.hr.sw.128
		case Intrinsic::x86_ssse3_psign_w_128: // llvm.x86.ssse3.ps
		ign.w.128
		case Intrinsic::x86_xop_vpcomequw: // llvm.x86.xop.vpcomequw
		case Intrinsic::x86_xop_vpcomeqw: // llvm.x86.xop.vpcomeqw
		case Intrinsic::x86_xop_vpcomfalseuw: // llvm.x86.xop.vpco
		mfalseuw
		case Intrinsic::x86_xop_vpcomfalsew: // llvm.x86.xop.vpcomfalsew
		case Intrinsic::x86_xop_vpcomgeuw: // llvm.x86.xop.vpcomgeuw
		case Intrinsic::x86_xop_vpcomgew: // llvm.x86.xop.vpcomgew
		case Intrinsic::x86_xop_vpcomgtuw: // llvm.x86.xop.vpcomgtuw
		case Intrinsic::x86_xop_vpcomgtw: // llvm.x86.xop.vpcomgtw
		case Intrinsic::x86_xop_vpcomleuw: // llvm.x86.xop.vpcomleuw
		case Intrinsic::x86_xop_vpcomlew: // llvm.x86.xop.vpcomlew
		case Intrinsic::x86_xop_vpcomltuw: // llvm.x86.xop.vpcomltuw
		case Intrinsic::x86_xop_vpcomltw: // llvm.x86.xop.vpcomltw
		case Intrinsic::x86_xop_vpcomneuw: // llvm.x86.xop.vpcomneuw
		case Intrinsic::x86_xop_vpcomnew: // llvm.x86.xop.vpcomnew
		case Intrinsic::x86_xop_vpcomtrueuw: // llvm.x86.xop.vpcomtrueuw
		case Intrinsic::x86_xop_vpcomtruew: // llvm.x86.xop.vpcomtruew
		case Intrinsic::x86_xop_vprotw: // llvm.x86.xop.vprotw
		case Intrinsic::x86_xop_vpshaw: // llvm.x86.xop.vpshaw
		case Intrinsic::x86_xop_vpshlw: // llvm.x86.xop.vpshlw
		ResultTy = VectorType::get(IntegerType::get(Context, 16), 8);
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
	break;	break;

	case Intrinsic::ppc_altivec_vmsumshm: // llvm.ppc.altivec.	case Intrinsic::x86_sse41_pblendw: // llvm.x86.sse41.pblendw
	vmsumshm	ResultTy = VectorType::get(IntegerType::get(Context, 16), 8);
	case Intrinsic::ppc_altivec_vmsumshs: // llvm.ppc.altivec.
	vmsumshs
	case Intrinsic::ppc_altivec_vmsumuhm: // llvm.ppc.altivec.
	vmsumuhm
	case Intrinsic::ppc_altivec_vmsumuhs: // llvm.ppc.altivec.
	vmsumuhs
	ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));

	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));	ArgTys.push_back(IntegerType::get(Context, 32));
	break;	break;

	case Intrinsic::spu_si_mpya: // llvm.spu.si.mpya	case Intrinsic::ppc_altivec_vmhaddshs: // llvm.ppc.altivec.
	ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);	vmhaddshs
		case Intrinsic::ppc_altivec_vmhraddshs: // llvm.ppc.altivec.
		vmhraddshs
		case Intrinsic::ppc_altivec_vmladduhm: // llvm.ppc.altivec.
		vmladduhm
		case Intrinsic::x86_xop_vpmacssww: // llvm.x86.xop.vpmacssww
		case Intrinsic::x86_xop_vpmacsww: // llvm.x86.xop.vpmacsww
		ResultTy = VectorType::get(IntegerType::get(Context, 16), 8);
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
	break;	break;

	case Intrinsic::x86_avx_vextractf128_si_256: // llvm.x86.avx.vext	case Intrinsic::x86_avx2_maskload_d_256: // llvm.x86.avx2.mas
	ractf128.si.256	kload.d.256
	ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);	ResultTy = VectorType::get(IntegerType::get(Context, 32), 8);
		ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 8));	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 8));

	ArgTys.push_back(IntegerType::get(Context, 8));
	break;	break;

	case Intrinsic::x86_avx_loadu_ps_256: // llvm.x86.avx.load	case Intrinsic::x86_avx2_pmadd_wd: // llvm.x86.avx2.pmadd.wd
	u.ps.256	ResultTy = VectorType::get(IntegerType::get(Context, 32), 8);
	case Intrinsic::x86_avx_vbroadcastf128_ps_256: // llvm.x86.	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 16));
	avx.vbroadcastf128.ps.256	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 16));
	case Intrinsic::x86_avx_vbroadcastss_256: // llvm.x86.avx.vbro
	adcastss.256
	ResultTy = VectorType::get(Type::getFloatTy(Context), 8);
	ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
	break;	break;

	case Intrinsic::x86_avx_maskload_ps_256: // llvm.x86.avx.mask	case Intrinsic::x86_avx2_pmovsxbd: // llvm.x86.avx2.pmovsxbd
	load.ps.256	case Intrinsic::x86_avx2_pmovzxbd: // llvm.x86.avx2.pmovzxbd
	ResultTy = VectorType::get(Type::getFloatTy(Context), 8);	ResultTy = VectorType::get(IntegerType::get(Context, 32), 8);
	ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
		break;
		case Intrinsic::x86_avx2_pbroadcastd_256: // llvm.x86.avx2.pbr
		oadcastd.256
		ResultTy = VectorType::get(IntegerType::get(Context, 32), 8);
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
		break;
		case Intrinsic::x86_avx_cvt_ps2dq_256: // llvm.x86.avx.cvt.
		ps2dq.256
		case Intrinsic::x86_avx_cvtt_ps2dq_256: // llvm.x86.avx.cvtt
		.ps2dq.256
		ResultTy = VectorType::get(IntegerType::get(Context, 32), 8);
	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 8));	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 8));
	break;	break;

	case Intrinsic::x86_avx_rcp_ps_256: // llvm.x86.avx.rcp.ps.256	case Intrinsic::x86_avx2_pmovsxwd: // llvm.x86.avx2.pmovsxwd
	case Intrinsic::x86_avx_rsqrt_ps_256: // llvm.x86.avx.rsqr	case Intrinsic::x86_avx2_pmovzxwd: // llvm.x86.avx2.pmovzxwd
	t.ps.256	ResultTy = VectorType::get(IntegerType::get(Context, 32), 8);
	case Intrinsic::x86_avx_sqrt_ps_256: // llvm.x86.avx.sqrt.ps.256	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
	ResultTy = VectorType::get(Type::getFloatTy(Context), 8);	break;
	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 8));	case Intrinsic::x86_avx2_pabs_d: // llvm.x86.avx2.pabs.d
		ResultTy = VectorType::get(IntegerType::get(Context, 32), 8);
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 8));
		break;
		case Intrinsic::x86_avx2_pslli_d: // llvm.x86.avx2.pslli.d
		case Intrinsic::x86_avx2_psrai_d: // llvm.x86.avx2.psrai.d
		case Intrinsic::x86_avx2_psrli_d: // llvm.x86.avx2.psrli.d
		ResultTy = VectorType::get(IntegerType::get(Context, 32), 8);
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 8));
		ArgTys.push_back(IntegerType::get(Context, 32));
		break;
		case Intrinsic::x86_avx2_psll_d: // llvm.x86.avx2.psll.d
		case Intrinsic::x86_avx2_psra_d: // llvm.x86.avx2.psra.d
		case Intrinsic::x86_avx2_psrl_d: // llvm.x86.avx2.psrl.d
		ResultTy = VectorType::get(IntegerType::get(Context, 32), 8);
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 8));
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
		break;
		case Intrinsic::x86_avx_vinsertf128_si_256: // llvm.x86.avx.vins
		ertf128.si.256
		ResultTy = VectorType::get(IntegerType::get(Context, 32), 8);
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 8));
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
		ArgTys.push_back(IntegerType::get(Context, 8));
		break;
		case Intrinsic::x86_avx2_permd: // llvm.x86.avx2.permd
		case Intrinsic::x86_avx2_phadd_d: // llvm.x86.avx2.phadd.d
		case Intrinsic::x86_avx2_phsub_d: // llvm.x86.avx2.phsub.d
		case Intrinsic::x86_avx2_pmaxs_d: // llvm.x86.avx2.pmaxs.d
		case Intrinsic::x86_avx2_pmaxu_d: // llvm.x86.avx2.pmaxu.d
		case Intrinsic::x86_avx2_pmins_d: // llvm.x86.avx2.pmins.d
		case Intrinsic::x86_avx2_pminu_d: // llvm.x86.avx2.pminu.d
		case Intrinsic::x86_avx2_psign_d: // llvm.x86.avx2.psign.d
		case Intrinsic::x86_avx2_psllv_d_256: // llvm.x86.avx2.psl
		lv.d.256
		case Intrinsic::x86_avx2_psrav_d_256: // llvm.x86.avx2.psr
		av.d.256
		case Intrinsic::x86_avx2_psrlv_d_256: // llvm.x86.avx2.psr
		lv.d.256
		ResultTy = VectorType::get(IntegerType::get(Context, 32), 8);
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 8));
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 8));
		break;
		case Intrinsic::x86_avx2_pblendd_256: // llvm.x86.avx2.pbl
		endd.256
		ResultTy = VectorType::get(IntegerType::get(Context, 32), 8);
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 8));
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 8));
		ArgTys.push_back(IntegerType::get(Context, 32));
		break;
		case Intrinsic::x86_avx_vperm2f128_si_256: // llvm.x86.avx.vper
		m2f128.si.256
		ResultTy = VectorType::get(IntegerType::get(Context, 32), 8);
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 8));
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 8));
		ArgTys.push_back(IntegerType::get(Context, 8));
		break;
		case Intrinsic::arm_neon_vtbl1: // llvm.arm.neon.vtbl1
		ResultTy = VectorType::get(IntegerType::get(Context, 8), 8);
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));
		break;
		case Intrinsic::arm_neon_vtbl2: // llvm.arm.neon.vtbl2
		case Intrinsic::arm_neon_vtbx1: // llvm.arm.neon.vtbx1
		ResultTy = VectorType::get(IntegerType::get(Context, 8), 8);
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));
		break;
		case Intrinsic::arm_neon_vtbl3: // llvm.arm.neon.vtbl3
		case Intrinsic::arm_neon_vtbx2: // llvm.arm.neon.vtbx2
		ResultTy = VectorType::get(IntegerType::get(Context, 8), 8);
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));
		break;
		case Intrinsic::arm_neon_vtbl4: // llvm.arm.neon.vtbl4
		case Intrinsic::arm_neon_vtbx3: // llvm.arm.neon.vtbx3
		ResultTy = VectorType::get(IntegerType::get(Context, 8), 8);
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));
	break;	break;

	case Intrinsic::x86_avx_round_ps_256: // llvm.x86.avx.roun	case Intrinsic::arm_neon_vtbx4: // llvm.arm.neon.vtbx4
	d.ps.256	ResultTy = VectorType::get(IntegerType::get(Context, 8), 8);
	ResultTy = VectorType::get(Type::getFloatTy(Context), 8);	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));
	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 8));	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));
	ArgTys.push_back(IntegerType::get(Context, 32));	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));
		ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));
	break;	break;

	case Intrinsic::x86_avx_vpermil_ps_256: // llvm.x86.avx.vper	case Intrinsic::x86_sse_cvtpd2pi: // llvm.x86.sse.cvtpd2pi
	mil.ps.256	case Intrinsic::x86_sse_cvttpd2pi: // llvm.x86.sse.cvttpd2pi
	ResultTy = VectorType::get(Type::getFloatTy(Context), 8);	ResultTy = Type::getX86_MMXTy(Context);
	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 8));	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
	ArgTys.push_back(IntegerType::get(Context, 8));
	break;	break;

	case Intrinsic::x86_avx_vinsertf128_ps_256: // llvm.x86.avx.vins	case Intrinsic::x86_sse_cvtps2pi: // llvm.x86.sse.cvtps2pi
	ertf128.ps.256	case Intrinsic::x86_sse_cvttps2pi: // llvm.x86.sse.cvttps2pi
	ResultTy = VectorType::get(Type::getFloatTy(Context), 8);	ResultTy = Type::getX86_MMXTy(Context);
	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 8));
	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));

	ArgTys.push_back(IntegerType::get(Context, 8));
	break;	break;

	case Intrinsic::x86_avx_addsub_ps_256: // llvm.x86.avx.adds	case Intrinsic::x86_3dnow_pf2id: // llvm.x86.3dnow.pf2id
	ub.ps.256	case Intrinsic::x86_3dnow_pfrcp: // llvm.x86.3dnow.pfrcp
	case Intrinsic::x86_avx_hadd_ps_256: // llvm.x86.avx.hadd.ps.256	case Intrinsic::x86_3dnow_pfrsqrt: // llvm.x86.3dnow.pfrsqrt
	case Intrinsic::x86_avx_hsub_ps_256: // llvm.x86.avx.hsub.ps.256	case Intrinsic::x86_3dnow_pi2fd: // llvm.x86.3dnow.pi2fd
	case Intrinsic::x86_avx_max_ps_256: // llvm.x86.avx.max.ps.256	case Intrinsic::x86_3dnowa_pf2iw: // llvm.x86.3dnowa.pf2iw
	case Intrinsic::x86_avx_min_ps_256: // llvm.x86.avx.min.ps.256	case Intrinsic::x86_3dnowa_pi2fw: // llvm.x86.3dnowa.pi2fw
	ResultTy = VectorType::get(Type::getFloatTy(Context), 8);	case Intrinsic::x86_3dnowa_pswapd: // llvm.x86.3dnowa.pswapd
	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 8));	case Intrinsic::x86_ssse3_pabs_b: // llvm.x86.ssse3.pabs.b
	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 8));	case Intrinsic::x86_ssse3_pabs_d: // llvm.x86.ssse3.pabs.d
		case Intrinsic::x86_ssse3_pabs_w: // llvm.x86.ssse3.pabs.w
		ResultTy = Type::getX86_MMXTy(Context);
		ArgTys.push_back(Type::getX86_MMXTy(Context));
	break;	break;

	case Intrinsic::x86_avx_blend_ps_256: // llvm.x86.avx.blen	case Intrinsic::x86_mmx_pslli_d: // llvm.x86.mmx.pslli.d
	d.ps.256	case Intrinsic::x86_mmx_pslli_q: // llvm.x86.mmx.pslli.q
	case Intrinsic::x86_avx_dp_ps_256: // llvm.x86.avx.dp.ps.256	case Intrinsic::x86_mmx_pslli_w: // llvm.x86.mmx.pslli.w
	ResultTy = VectorType::get(Type::getFloatTy(Context), 8);	case Intrinsic::x86_mmx_psrai_d: // llvm.x86.mmx.psrai.d
	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 8));	case Intrinsic::x86_mmx_psrai_w: // llvm.x86.mmx.psrai.w
	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 8));	case Intrinsic::x86_mmx_psrli_d: // llvm.x86.mmx.psrli.d
		case Intrinsic::x86_mmx_psrli_q: // llvm.x86.mmx.psrli.q
		case Intrinsic::x86_mmx_psrli_w: // llvm.x86.mmx.psrli.w
		ResultTy = Type::getX86_MMXTy(Context);
		ArgTys.push_back(Type::getX86_MMXTy(Context));
	ArgTys.push_back(IntegerType::get(Context, 32));	ArgTys.push_back(IntegerType::get(Context, 32));
	break;	break;

	case Intrinsic::x86_avx_cmp_ps_256: // llvm.x86.avx.cmp.ps.256	case Intrinsic::x86_mmx_pinsr_w: // llvm.x86.mmx.pinsr.w
	case Intrinsic::x86_avx_vperm2f128_ps_256: // llvm.x86.avx.vper	ResultTy = Type::getX86_MMXTy(Context);
	m2f128.ps.256	ArgTys.push_back(Type::getX86_MMXTy(Context));
	ResultTy = VectorType::get(Type::getFloatTy(Context), 8);	ArgTys.push_back(IntegerType::get(Context, 32));
	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 8));	ArgTys.push_back(IntegerType::get(Context, 32));
	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 8));
	ArgTys.push_back(IntegerType::get(Context, 8));
	break;
	case Intrinsic::x86_avx_blendv_ps_256: // llvm.x86.avx.blen
	dv.ps.256
	ResultTy = VectorType::get(Type::getFloatTy(Context), 8);
	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 8));
	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 8));
	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 8));
	break;
	case Intrinsic::x86_avx_vpermilvar_ps_256: // llvm.x86.avx.vper
	milvar.ps.256
	ResultTy = VectorType::get(Type::getFloatTy(Context), 8);
	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 8));
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 8));
	break;	break;

	case Intrinsic::x86_avx_cvtdq2_ps_256: // llvm.x86.avx.cvtd	case Intrinsic::x86_sse_pshuf_w: // llvm.x86.sse.pshuf.w
	q2.ps.256	ResultTy = Type::getX86_MMXTy(Context);
	ResultTy = VectorType::get(Type::getFloatTy(Context), 8);	ArgTys.push_back(Type::getX86_MMXTy(Context));
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 8));	ArgTys.push_back(IntegerType::get(Context, 8));
	break;	break;

	case Intrinsic::ppc_altivec_mfvscr: // llvm.ppc.altivec.mfvscr	case Intrinsic::x86_3dnow_pavgusb: // llvm.x86.3dnow.pavgusb
	ResultTy = VectorType::get(IntegerType::get(Context, 16), 8);	case Intrinsic::x86_3dnow_pfacc: // llvm.x86.3dnow.pfacc
		case Intrinsic::x86_3dnow_pfadd: // llvm.x86.3dnow.pfadd
		case Intrinsic::x86_3dnow_pfcmpeq: // llvm.x86.3dnow.pfcmpeq
		case Intrinsic::x86_3dnow_pfcmpge: // llvm.x86.3dnow.pfcmpge
		case Intrinsic::x86_3dnow_pfcmpgt: // llvm.x86.3dnow.pfcmpgt
		case Intrinsic::x86_3dnow_pfmax: // llvm.x86.3dnow.pfmax
		case Intrinsic::x86_3dnow_pfmin: // llvm.x86.3dnow.pfmin
		case Intrinsic::x86_3dnow_pfmul: // llvm.x86.3dnow.pfmul
		case Intrinsic::x86_3dnow_pfrcpit1: // llvm.x86.3dnow.pfrcpit1
		case Intrinsic::x86_3dnow_pfrcpit2: // llvm.x86.3dnow.pfrcpit2
		case Intrinsic::x86_3dnow_pfrsqit1: // llvm.x86.3dnow.pfrsqit1
		case Intrinsic::x86_3dnow_pfsub: // llvm.x86.3dnow.pfsub
		case Intrinsic::x86_3dnow_pfsubr: // llvm.x86.3dnow.pfsubr
		case Intrinsic::x86_3dnow_pmulhrw: // llvm.x86.3dnow.pmulhrw
		case Intrinsic::x86_3dnowa_pfnacc: // llvm.x86.3dnowa.pfnacc
		case Intrinsic::x86_3dnowa_pfpnacc: // llvm.x86.3dnowa.pfpnacc
		case Intrinsic::x86_mmx_packssdw: // llvm.x86.mmx.packssdw
		case Intrinsic::x86_mmx_packsswb: // llvm.x86.mmx.packsswb
		case Intrinsic::x86_mmx_packuswb: // llvm.x86.mmx.packuswb
		case Intrinsic::x86_mmx_padd_b: // llvm.x86.mmx.padd.b
		case Intrinsic::x86_mmx_padd_d: // llvm.x86.mmx.padd.d
		case Intrinsic::x86_mmx_padd_q: // llvm.x86.mmx.padd.q
		case Intrinsic::x86_mmx_padd_w: // llvm.x86.mmx.padd.w
		case Intrinsic::x86_mmx_padds_b: // llvm.x86.mmx.padds.b
		case Intrinsic::x86_mmx_padds_w: // llvm.x86.mmx.padds.w
		case Intrinsic::x86_mmx_paddus_b: // llvm.x86.mmx.paddus.b
		case Intrinsic::x86_mmx_paddus_w: // llvm.x86.mmx.paddus.w
		case Intrinsic::x86_mmx_pand: // llvm.x86.mmx.pand
		case Intrinsic::x86_mmx_pandn: // llvm.x86.mmx.pandn
		case Intrinsic::x86_mmx_pavg_b: // llvm.x86.mmx.pavg.b
		case Intrinsic::x86_mmx_pavg_w: // llvm.x86.mmx.pavg.w
		case Intrinsic::x86_mmx_pcmpeq_b: // llvm.x86.mmx.pcmpeq.b
		case Intrinsic::x86_mmx_pcmpeq_d: // llvm.x86.mmx.pcmpeq.d
		case Intrinsic::x86_mmx_pcmpeq_w: // llvm.x86.mmx.pcmpeq.w
		case Intrinsic::x86_mmx_pcmpgt_b: // llvm.x86.mmx.pcmpgt.b
		case Intrinsic::x86_mmx_pcmpgt_d: // llvm.x86.mmx.pcmpgt.d
		case Intrinsic::x86_mmx_pcmpgt_w: // llvm.x86.mmx.pcmpgt.w
		case Intrinsic::x86_mmx_pmadd_wd: // llvm.x86.mmx.pmadd.wd
		case Intrinsic::x86_mmx_pmaxs_w: // llvm.x86.mmx.pmaxs.w
		case Intrinsic::x86_mmx_pmaxu_b: // llvm.x86.mmx.pmaxu.b
		case Intrinsic::x86_mmx_pmins_w: // llvm.x86.mmx.pmins.w
		case Intrinsic::x86_mmx_pminu_b: // llvm.x86.mmx.pminu.b
		case Intrinsic::x86_mmx_pmulh_w: // llvm.x86.mmx.pmulh.w
		case Intrinsic::x86_mmx_pmulhu_w: // llvm.x86.mmx.pmulhu.w
		case Intrinsic::x86_mmx_pmull_w: // llvm.x86.mmx.pmull.w
		case Intrinsic::x86_mmx_pmulu_dq: // llvm.x86.mmx.pmulu.dq
		case Intrinsic::x86_mmx_por: // llvm.x86.mmx.por
		case Intrinsic::x86_mmx_psad_bw: // llvm.x86.mmx.psad.bw
		case Intrinsic::x86_mmx_psll_d: // llvm.x86.mmx.psll.d
		case Intrinsic::x86_mmx_psll_q: // llvm.x86.mmx.psll.q
		case Intrinsic::x86_mmx_psll_w: // llvm.x86.mmx.psll.w
		case Intrinsic::x86_mmx_psra_d: // llvm.x86.mmx.psra.d
		case Intrinsic::x86_mmx_psra_w: // llvm.x86.mmx.psra.w
		case Intrinsic::x86_mmx_psrl_d: // llvm.x86.mmx.psrl.d
		case Intrinsic::x86_mmx_psrl_q: // llvm.x86.mmx.psrl.q
		case Intrinsic::x86_mmx_psrl_w: // llvm.x86.mmx.psrl.w
		case Intrinsic::x86_mmx_psub_b: // llvm.x86.mmx.psub.b
		case Intrinsic::x86_mmx_psub_d: // llvm.x86.mmx.psub.d
		case Intrinsic::x86_mmx_psub_q: // llvm.x86.mmx.psub.q
		case Intrinsic::x86_mmx_psub_w: // llvm.x86.mmx.psub.w
		case Intrinsic::x86_mmx_psubs_b: // llvm.x86.mmx.psubs.b
		case Intrinsic::x86_mmx_psubs_w: // llvm.x86.mmx.psubs.w
		case Intrinsic::x86_mmx_psubus_b: // llvm.x86.mmx.psubus.b
		case Intrinsic::x86_mmx_psubus_w: // llvm.x86.mmx.psubus.w
		case Intrinsic::x86_mmx_punpckhbw: // llvm.x86.mmx.punpckhbw
		case Intrinsic::x86_mmx_punpckhdq: // llvm.x86.mmx.punpckhdq
		case Intrinsic::x86_mmx_punpckhwd: // llvm.x86.mmx.punpckhwd
		case Intrinsic::x86_mmx_punpcklbw: // llvm.x86.mmx.punpcklbw
		case Intrinsic::x86_mmx_punpckldq: // llvm.x86.mmx.punpckldq
		case Intrinsic::x86_mmx_punpcklwd: // llvm.x86.mmx.punpcklwd
		case Intrinsic::x86_mmx_pxor: // llvm.x86.mmx.pxor
		case Intrinsic::x86_ssse3_phadd_d: // llvm.x86.ssse3.phadd.d
		case Intrinsic::x86_ssse3_phadd_sw: // llvm.x86.ssse3.phadd.sw
		case Intrinsic::x86_ssse3_phadd_w: // llvm.x86.ssse3.phadd.w
		case Intrinsic::x86_ssse3_phsub_d: // llvm.x86.ssse3.phsub.d
		case Intrinsic::x86_ssse3_phsub_sw: // llvm.x86.ssse3.phsub.sw
		case Intrinsic::x86_ssse3_phsub_w: // llvm.x86.ssse3.phsub.w
		case Intrinsic::x86_ssse3_pmadd_ub_sw: // llvm.x86.ssse3.pm
		add.ub.sw
		case Intrinsic::x86_ssse3_pmul_hr_sw: // llvm.x86.ssse3.pm
		ul.hr.sw
		case Intrinsic::x86_ssse3_pshuf_b: // llvm.x86.ssse3.pshuf.b
		case Intrinsic::x86_ssse3_psign_b: // llvm.x86.ssse3.psign.b
		case Intrinsic::x86_ssse3_psign_d: // llvm.x86.ssse3.psign.d
		case Intrinsic::x86_ssse3_psign_w: // llvm.x86.ssse3.psign.w
		ResultTy = Type::getX86_MMXTy(Context);
		ArgTys.push_back(Type::getX86_MMXTy(Context));
		ArgTys.push_back(Type::getX86_MMXTy(Context));
	break;	break;

	case Intrinsic::ppc_altivec_lvehx: // llvm.ppc.altivec.lvehx	case Intrinsic::x86_mmx_palignr_b: // llvm.x86.mmx.palignr.b
	ResultTy = VectorType::get(IntegerType::get(Context, 16), 8);	ResultTy = Type::getX86_MMXTy(Context);
	ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));	ArgTys.push_back(Type::getX86_MMXTy(Context));
		ArgTys.push_back(Type::getX86_MMXTy(Context));
		ArgTys.push_back(IntegerType::get(Context, 8));
	break;	break;

	case Intrinsic::ppc_altivec_vupkhsb: // llvm.ppc.altivec.vupkhsb	}
	case Intrinsic::ppc_altivec_vupklsb: // llvm.ppc.altivec.vupklsb	#endif
	case Intrinsic::x86_sse41_pmovsxbw: // llvm.x86.sse41.pmovsxbw
	case Intrinsic::x86_sse41_pmovzxbw: // llvm.x86.sse41.pmovzxbw	// Add parameter attributes that are not common to all intrinsics.
	ResultTy = VectorType::get(IntegerType::get(Context, 16), 8);	#ifdef GET_INTRINSIC_ATTRIBUTES
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));	AttrListPtr Intrinsic::getAttributes(ID id) {
		static const uint8_t IntrinsicsToAttributesMap[] = {
		1, // llvm.adjust.trampoline
		2, // llvm.annotation
		2, // llvm.arm.cdp
		2, // llvm.arm.cdp2
		3, // llvm.arm.get.fpscr
		1, // llvm.arm.ldrexd
		2, // llvm.arm.mcr
		2, // llvm.arm.mcr2
		2, // llvm.arm.mcrr
		2, // llvm.arm.mcrr2
		2, // llvm.arm.mrc
		2, // llvm.arm.mrc2
		3, // llvm.arm.neon.vabds
		3, // llvm.arm.neon.vabdu
		3, // llvm.arm.neon.vabs
		3, // llvm.arm.neon.vacged
		3, // llvm.arm.neon.vacgeq
		3, // llvm.arm.neon.vacgtd
		3, // llvm.arm.neon.vacgtq
		3, // llvm.arm.neon.vaddhn
		3, // llvm.arm.neon.vcls
		3, // llvm.arm.neon.vclz
		3, // llvm.arm.neon.vcnt
		3, // llvm.arm.neon.vcvtfp2fxs
		3, // llvm.arm.neon.vcvtfp2fxu
		3, // llvm.arm.neon.vcvtfp2hf
		3, // llvm.arm.neon.vcvtfxs2fp
		3, // llvm.arm.neon.vcvtfxu2fp
		3, // llvm.arm.neon.vcvthf2fp
		3, // llvm.arm.neon.vhadds
		3, // llvm.arm.neon.vhaddu
		3, // llvm.arm.neon.vhsubs
		3, // llvm.arm.neon.vhsubu
		1, // llvm.arm.neon.vld1
		1, // llvm.arm.neon.vld2
		1, // llvm.arm.neon.vld2lane
		1, // llvm.arm.neon.vld3
		1, // llvm.arm.neon.vld3lane
		1, // llvm.arm.neon.vld4
		1, // llvm.arm.neon.vld4lane
		3, // llvm.arm.neon.vmaxs
		3, // llvm.arm.neon.vmaxu
		3, // llvm.arm.neon.vmins
		3, // llvm.arm.neon.vminu
		3, // llvm.arm.neon.vmullp
		3, // llvm.arm.neon.vmulls
		3, // llvm.arm.neon.vmullu
		3, // llvm.arm.neon.vmulp
		3, // llvm.arm.neon.vpadals
		3, // llvm.arm.neon.vpadalu
		3, // llvm.arm.neon.vpadd
		3, // llvm.arm.neon.vpaddls
		3, // llvm.arm.neon.vpaddlu
		3, // llvm.arm.neon.vpmaxs
		3, // llvm.arm.neon.vpmaxu
		3, // llvm.arm.neon.vpmins
		3, // llvm.arm.neon.vpminu
		3, // llvm.arm.neon.vqabs
		3, // llvm.arm.neon.vqadds
		3, // llvm.arm.neon.vqaddu
		3, // llvm.arm.neon.vqdmlal
		3, // llvm.arm.neon.vqdmlsl
		3, // llvm.arm.neon.vqdmulh
		3, // llvm.arm.neon.vqdmull
		3, // llvm.arm.neon.vqmovns
		3, // llvm.arm.neon.vqmovnsu
		3, // llvm.arm.neon.vqmovnu
		3, // llvm.arm.neon.vqneg
		3, // llvm.arm.neon.vqrdmulh
		3, // llvm.arm.neon.vqrshiftns
		3, // llvm.arm.neon.vqrshiftnsu
		3, // llvm.arm.neon.vqrshiftnu
		3, // llvm.arm.neon.vqrshifts
		3, // llvm.arm.neon.vqrshiftu
		3, // llvm.arm.neon.vqshiftns
		3, // llvm.arm.neon.vqshiftnsu
		3, // llvm.arm.neon.vqshiftnu
		3, // llvm.arm.neon.vqshifts
		3, // llvm.arm.neon.vqshiftsu
		3, // llvm.arm.neon.vqshiftu
		3, // llvm.arm.neon.vqsubs
		3, // llvm.arm.neon.vqsubu
		3, // llvm.arm.neon.vraddhn
		3, // llvm.arm.neon.vrecpe
		3, // llvm.arm.neon.vrecps
		3, // llvm.arm.neon.vrhadds
		3, // llvm.arm.neon.vrhaddu
		3, // llvm.arm.neon.vrshiftn
		3, // llvm.arm.neon.vrshifts
		3, // llvm.arm.neon.vrshiftu
		3, // llvm.arm.neon.vrsqrte
		3, // llvm.arm.neon.vrsqrts
		3, // llvm.arm.neon.vrsubhn
		3, // llvm.arm.neon.vshiftins
		3, // llvm.arm.neon.vshiftls
		3, // llvm.arm.neon.vshiftlu
		3, // llvm.arm.neon.vshiftn
		3, // llvm.arm.neon.vshifts
		3, // llvm.arm.neon.vshiftu
		2, // llvm.arm.neon.vst1
		2, // llvm.arm.neon.vst2
		2, // llvm.arm.neon.vst2lane
		2, // llvm.arm.neon.vst3
		2, // llvm.arm.neon.vst3lane
		2, // llvm.arm.neon.vst4
		2, // llvm.arm.neon.vst4lane
		3, // llvm.arm.neon.vsubhn
		3, // llvm.arm.neon.vtbl1
		3, // llvm.arm.neon.vtbl2
		3, // llvm.arm.neon.vtbl3
		3, // llvm.arm.neon.vtbl4
		3, // llvm.arm.neon.vtbx1
		3, // llvm.arm.neon.vtbx2
		3, // llvm.arm.neon.vtbx3
		3, // llvm.arm.neon.vtbx4
		3, // llvm.arm.qadd
		3, // llvm.arm.qsub
		2, // llvm.arm.set.fpscr
		3, // llvm.arm.ssat
		2, // llvm.arm.strexd
		3, // llvm.arm.thread.pointer
		3, // llvm.arm.usat
		3, // llvm.arm.vcvtr
		3, // llvm.arm.vcvtru
		3, // llvm.bswap
		3, // llvm.convert.from.fp16
		3, // llvm.convert.to.fp16
		2, // llvm.convertff
		2, // llvm.convertfsi
		2, // llvm.convertfui
		2, // llvm.convertsif
		2, // llvm.convertss
		2, // llvm.convertsu
		2, // llvm.convertuif
		2, // llvm.convertus
		2, // llvm.convertuu
		1, // llvm.cos
		3, // llvm.ctlz
		3, // llvm.ctpop
		3, // llvm.cttz
		3, // llvm.dbg.declare
		3, // llvm.dbg.value
		2, // llvm.eh.dwarf.cfa
		2, // llvm.eh.return.i32
		2, // llvm.eh.return.i64
		3, // llvm.eh.sjlj.callsite
		2, // llvm.eh.sjlj.functioncontext
		2, // llvm.eh.sjlj.longjmp
		3, // llvm.eh.sjlj.lsda
		2, // llvm.eh.sjlj.setjmp
		3, // llvm.eh.typeid.for
		2, // llvm.eh.unwind.init
		1, // llvm.exp
		1, // llvm.exp2
		3, // llvm.expect
		2, // llvm.flt.rounds
		3, // llvm.fma
		3, // llvm.frameaddress
		1, // llvm.gcread
		2, // llvm.gcroot
		4, // llvm.gcwrite
		3, // llvm.hexagon.A2.abs
		3, // llvm.hexagon.A2.absp
		3, // llvm.hexagon.A2.abssat
		3, // llvm.hexagon.A2.add
		3, // llvm.hexagon.A2.addh.h16.hh
		3, // llvm.hexagon.A2.addh.h16.hl
		3, // llvm.hexagon.A2.addh.h16.lh
		3, // llvm.hexagon.A2.addh.h16.ll
		3, // llvm.hexagon.A2.addh.h16.sat.hh
		3, // llvm.hexagon.A2.addh.h16.sat.hl
		3, // llvm.hexagon.A2.addh.h16.sat.lh
		3, // llvm.hexagon.A2.addh.h16.sat.ll
		3, // llvm.hexagon.A2.addh.l16.hh
		3, // llvm.hexagon.A2.addh.l16.hl
		3, // llvm.hexagon.A2.addh.l16.lh
		3, // llvm.hexagon.A2.addh.l16.ll
		3, // llvm.hexagon.A2.addh.l16.sat.hh
		3, // llvm.hexagon.A2.addh.l16.sat.hl
		3, // llvm.hexagon.A2.addh.l16.sat.lh
		3, // llvm.hexagon.A2.addh.l16.sat.ll
		3, // llvm.hexagon.A2.addi
		3, // llvm.hexagon.A2.addp
		3, // llvm.hexagon.A2.addpsat
		3, // llvm.hexagon.A2.addsat
		3, // llvm.hexagon.A2.addsp
		3, // llvm.hexagon.A2.and
		3, // llvm.hexagon.A2.andir
		3, // llvm.hexagon.A2.andp
		3, // llvm.hexagon.A2.aslh
		3, // llvm.hexagon.A2.asrh
		3, // llvm.hexagon.A2.combine.hh
		3, // llvm.hexagon.A2.combine.hl
		3, // llvm.hexagon.A2.combine.lh
		3, // llvm.hexagon.A2.combine.ll
		3, // llvm.hexagon.A2.combineii
		3, // llvm.hexagon.A2.combinew
		3, // llvm.hexagon.A2.max
		3, // llvm.hexagon.A2.maxp
		3, // llvm.hexagon.A2.maxu
		3, // llvm.hexagon.A2.maxup
		3, // llvm.hexagon.A2.min
		3, // llvm.hexagon.A2.minp
		3, // llvm.hexagon.A2.minu
		3, // llvm.hexagon.A2.minup
		3, // llvm.hexagon.A2.neg
		3, // llvm.hexagon.A2.negp
		3, // llvm.hexagon.A2.negsat
		3, // llvm.hexagon.A2.not
		3, // llvm.hexagon.A2.notp
		3, // llvm.hexagon.A2.or
		3, // llvm.hexagon.A2.orir
		3, // llvm.hexagon.A2.orp
		3, // llvm.hexagon.A2.sat
		3, // llvm.hexagon.A2.satb
		3, // llvm.hexagon.A2.sath
		3, // llvm.hexagon.A2.satub
		3, // llvm.hexagon.A2.satuh
		3, // llvm.hexagon.A2.sub
		3, // llvm.hexagon.A2.subh.h16.hh
		3, // llvm.hexagon.A2.subh.h16.hl
		3, // llvm.hexagon.A2.subh.h16.lh
		3, // llvm.hexagon.A2.subh.h16.ll
		3, // llvm.hexagon.A2.subh.h16.sat.hh
		3, // llvm.hexagon.A2.subh.h16.sat.hl
		3, // llvm.hexagon.A2.subh.h16.sat.lh
		3, // llvm.hexagon.A2.subh.h16.sat.ll
		3, // llvm.hexagon.A2.subh.l16.hl
		3, // llvm.hexagon.A2.subh.l16.ll
		3, // llvm.hexagon.A2.subh.l16.sat.hl
		3, // llvm.hexagon.A2.subh.l16.sat.ll
		3, // llvm.hexagon.A2.subp
		3, // llvm.hexagon.A2.subri
		3, // llvm.hexagon.A2.subsat
		3, // llvm.hexagon.A2.svaddh
		3, // llvm.hexagon.A2.svaddhs
		3, // llvm.hexagon.A2.svadduhs
		3, // llvm.hexagon.A2.svavgh
		3, // llvm.hexagon.A2.svavghs
		3, // llvm.hexagon.A2.svnavgh
		3, // llvm.hexagon.A2.svsubh
		3, // llvm.hexagon.A2.svsubhs
		3, // llvm.hexagon.A2.svsubuhs
		3, // llvm.hexagon.A2.swiz
		3, // llvm.hexagon.A2.sxtb
		3, // llvm.hexagon.A2.sxth
		3, // llvm.hexagon.A2.sxtw
		3, // llvm.hexagon.A2.tfr
		3, // llvm.hexagon.A2.tfrih
		3, // llvm.hexagon.A2.tfril
		3, // llvm.hexagon.A2.tfrp
		3, // llvm.hexagon.A2.tfrpi
		3, // llvm.hexagon.A2.tfrsi
		3, // llvm.hexagon.A2.vabsh
		3, // llvm.hexagon.A2.vabshsat
		3, // llvm.hexagon.A2.vabsw
		3, // llvm.hexagon.A2.vabswsat
		3, // llvm.hexagon.A2.vaddh
		3, // llvm.hexagon.A2.vaddhs
		3, // llvm.hexagon.A2.vaddub
		3, // llvm.hexagon.A2.vaddubs
		3, // llvm.hexagon.A2.vadduhs
		3, // llvm.hexagon.A2.vaddw
		3, // llvm.hexagon.A2.vaddws
		3, // llvm.hexagon.A2.vavgh
		3, // llvm.hexagon.A2.vavghcr
		3, // llvm.hexagon.A2.vavghr
		3, // llvm.hexagon.A2.vavgub
		3, // llvm.hexagon.A2.vavgubr
		3, // llvm.hexagon.A2.vavguh
		3, // llvm.hexagon.A2.vavguhr
		3, // llvm.hexagon.A2.vavguw
		3, // llvm.hexagon.A2.vavguwr
		3, // llvm.hexagon.A2.vavgw
		3, // llvm.hexagon.A2.vavgwcr
		3, // llvm.hexagon.A2.vavgwr
		3, // llvm.hexagon.A2.vcmpbeq
		3, // llvm.hexagon.A2.vcmpbgtu
		3, // llvm.hexagon.A2.vcmpheq
		3, // llvm.hexagon.A2.vcmphgt
		3, // llvm.hexagon.A2.vcmphgtu
		3, // llvm.hexagon.A2.vcmpweq
		3, // llvm.hexagon.A2.vcmpwgt
		3, // llvm.hexagon.A2.vcmpwgtu
		3, // llvm.hexagon.A2.vconj
		3, // llvm.hexagon.A2.vmaxh
		3, // llvm.hexagon.A2.vmaxub
		3, // llvm.hexagon.A2.vmaxuh
		3, // llvm.hexagon.A2.vmaxuw
		3, // llvm.hexagon.A2.vmaxw
		3, // llvm.hexagon.A2.vminh
		3, // llvm.hexagon.A2.vminub
		3, // llvm.hexagon.A2.vminuh
		3, // llvm.hexagon.A2.vminuw
		3, // llvm.hexagon.A2.vminw
		3, // llvm.hexagon.A2.vnavgh
		3, // llvm.hexagon.A2.vnavghcr
		3, // llvm.hexagon.A2.vnavghr
		3, // llvm.hexagon.A2.vnavgw
		3, // llvm.hexagon.A2.vnavgwcr
		3, // llvm.hexagon.A2.vnavgwr
		3, // llvm.hexagon.A2.vraddub
		3, // llvm.hexagon.A2.vraddub.acc
		3, // llvm.hexagon.A2.vrsadub
		3, // llvm.hexagon.A2.vrsadub.acc
		3, // llvm.hexagon.A2.vsubh
		3, // llvm.hexagon.A2.vsubhs
		3, // llvm.hexagon.A2.vsubub
		3, // llvm.hexagon.A2.vsububs
		3, // llvm.hexagon.A2.vsubuhs
		3, // llvm.hexagon.A2.vsubw
		3, // llvm.hexagon.A2.vsubws
		3, // llvm.hexagon.A2.xor
		3, // llvm.hexagon.A2.xorp
		3, // llvm.hexagon.A2.zxtb
		3, // llvm.hexagon.A2.zxth
		3, // llvm.hexagon.A4.andn
		3, // llvm.hexagon.A4.andnp
		3, // llvm.hexagon.A4.combineir
		3, // llvm.hexagon.A4.combineri
		3, // llvm.hexagon.A4.cround.ri
		3, // llvm.hexagon.A4.cround.rr
		3, // llvm.hexagon.A4.modwrapu
		3, // llvm.hexagon.A4.orn
		3, // llvm.hexagon.A4.ornp
		3, // llvm.hexagon.A4.rcmpeq
		3, // llvm.hexagon.A4.rcmpeqi
		3, // llvm.hexagon.A4.rcmpneq
		3, // llvm.hexagon.A4.rcmpneqi
		3, // llvm.hexagon.A4.round.ri
		3, // llvm.hexagon.A4.round.ri.sat
		3, // llvm.hexagon.A4.round.rr
		3, // llvm.hexagon.A4.round.rr.sat
		3, // llvm.hexagon.C2.all8
		3, // llvm.hexagon.C2.and
		3, // llvm.hexagon.C2.andn
		3, // llvm.hexagon.C2.any8
		3, // llvm.hexagon.C2.bitsclr
		3, // llvm.hexagon.C2.bitsclri
		3, // llvm.hexagon.C2.bitsset
		3, // llvm.hexagon.C2.cmpeq
		3, // llvm.hexagon.C2.cmpeqi
		3, // llvm.hexagon.C2.cmpeqp
		3, // llvm.hexagon.C2.cmpgei
		3, // llvm.hexagon.C2.cmpgeui
		3, // llvm.hexagon.C2.cmpgt
		3, // llvm.hexagon.C2.cmpgti
		3, // llvm.hexagon.C2.cmpgtp
		3, // llvm.hexagon.C2.cmpgtu
		3, // llvm.hexagon.C2.cmpgtui
		3, // llvm.hexagon.C2.cmpgtup
		3, // llvm.hexagon.C2.cmplt
		3, // llvm.hexagon.C2.cmpltu
		3, // llvm.hexagon.C2.mask
		3, // llvm.hexagon.C2.mux
		3, // llvm.hexagon.C2.muxii
		3, // llvm.hexagon.C2.muxir
		3, // llvm.hexagon.C2.muxri
		3, // llvm.hexagon.C2.not
		3, // llvm.hexagon.C2.or
		3, // llvm.hexagon.C2.orn
		3, // llvm.hexagon.C2.pxfer.map
		3, // llvm.hexagon.C2.tfrpr
		3, // llvm.hexagon.C2.tfrrp
		3, // llvm.hexagon.C2.vitpack
		3, // llvm.hexagon.C2.vmux
		3, // llvm.hexagon.C2.xor
		3, // llvm.hexagon.C4.and.and
		3, // llvm.hexagon.C4.and.andn
		3, // llvm.hexagon.C4.and.or
		3, // llvm.hexagon.C4.and.orn
		3, // llvm.hexagon.C4.cmplte
		3, // llvm.hexagon.C4.cmpltei
		3, // llvm.hexagon.C4.cmplteu
		3, // llvm.hexagon.C4.cmplteui
		3, // llvm.hexagon.C4.cmpneq
		3, // llvm.hexagon.C4.cmpneqi
		3, // llvm.hexagon.C4.fastcorner9
		3, // llvm.hexagon.C4.fastcorner9.not
		3, // llvm.hexagon.C4.or.and
		3, // llvm.hexagon.C4.or.andn
		3, // llvm.hexagon.C4.or.or
		3, // llvm.hexagon.C4.or.orn
		3, // llvm.hexagon.M2.acci
		3, // llvm.hexagon.M2.accii
		3, // llvm.hexagon.M2.cmaci.s0
		3, // llvm.hexagon.M2.cmacr.s0
		3, // llvm.hexagon.M2.cmacs.s0
		3, // llvm.hexagon.M2.cmacs.s1
		3, // llvm.hexagon.M2.cmacsc.s0
		3, // llvm.hexagon.M2.cmacsc.s1
		3, // llvm.hexagon.M2.cmpyi.s0
		3, // llvm.hexagon.M2.cmpyr.s0
		3, // llvm.hexagon.M2.cmpyrs.s0
		3, // llvm.hexagon.M2.cmpyrs.s1
		3, // llvm.hexagon.M2.cmpyrsc.s0
		3, // llvm.hexagon.M2.cmpyrsc.s1
		3, // llvm.hexagon.M2.cmpys.s0
		3, // llvm.hexagon.M2.cmpys.s1
		3, // llvm.hexagon.M2.cmpysc.s0
		3, // llvm.hexagon.M2.cmpysc.s1
		3, // llvm.hexagon.M2.cnacs.s0
		3, // llvm.hexagon.M2.cnacs.s1
		3, // llvm.hexagon.M2.cnacsc.s0
		3, // llvm.hexagon.M2.cnacsc.s1
		3, // llvm.hexagon.M2.dpmpyss.acc.s0
		3, // llvm.hexagon.M2.dpmpyss.nac.s0
		3, // llvm.hexagon.M2.dpmpyss.rnd.s0
		3, // llvm.hexagon.M2.dpmpyss.s0
		3, // llvm.hexagon.M2.dpmpyuu.acc.s0
		3, // llvm.hexagon.M2.dpmpyuu.nac.s0
		3, // llvm.hexagon.M2.dpmpyuu.s0
		3, // llvm.hexagon.M2.hmmpyh.rs1
		3, // llvm.hexagon.M2.hmmpyl.rs1
		3, // llvm.hexagon.M2.maci
		3, // llvm.hexagon.M2.macsin
		3, // llvm.hexagon.M2.macsip
		3, // llvm.hexagon.M2.mmachs.rs0
		3, // llvm.hexagon.M2.mmachs.rs1
		3, // llvm.hexagon.M2.mmachs.s0
		3, // llvm.hexagon.M2.mmachs.s1
		3, // llvm.hexagon.M2.mmacls.rs0
		3, // llvm.hexagon.M2.mmacls.rs1
		3, // llvm.hexagon.M2.mmacls.s0
		3, // llvm.hexagon.M2.mmacls.s1
		3, // llvm.hexagon.M2.mmacuhs.rs0
		3, // llvm.hexagon.M2.mmacuhs.rs1
		3, // llvm.hexagon.M2.mmacuhs.s0
		3, // llvm.hexagon.M2.mmacuhs.s1
		3, // llvm.hexagon.M2.mmaculs.rs0
		3, // llvm.hexagon.M2.mmaculs.rs1
		3, // llvm.hexagon.M2.mmaculs.s0
		3, // llvm.hexagon.M2.mmaculs.s1
		3, // llvm.hexagon.M2.mmpyh.rs0
		3, // llvm.hexagon.M2.mmpyh.rs1
		3, // llvm.hexagon.M2.mmpyh.s0
		3, // llvm.hexagon.M2.mmpyh.s1
		3, // llvm.hexagon.M2.mmpyl.rs0
		3, // llvm.hexagon.M2.mmpyl.rs1
		3, // llvm.hexagon.M2.mmpyl.s0
		3, // llvm.hexagon.M2.mmpyl.s1
		3, // llvm.hexagon.M2.mmpyuh.rs0
		3, // llvm.hexagon.M2.mmpyuh.rs1
		3, // llvm.hexagon.M2.mmpyuh.s0
		3, // llvm.hexagon.M2.mmpyuh.s1
		3, // llvm.hexagon.M2.mmpyul.rs0
		3, // llvm.hexagon.M2.mmpyul.rs1
		3, // llvm.hexagon.M2.mmpyul.s0
		3, // llvm.hexagon.M2.mmpyul.s1
		3, // llvm.hexagon.M2.mpy.acc.hh.s0
		3, // llvm.hexagon.M2.mpy.acc.hh.s1
		3, // llvm.hexagon.M2.mpy.acc.hl.s0
		3, // llvm.hexagon.M2.mpy.acc.hl.s1
		3, // llvm.hexagon.M2.mpy.acc.lh.s0
		3, // llvm.hexagon.M2.mpy.acc.lh.s1
		3, // llvm.hexagon.M2.mpy.acc.ll.s0
		3, // llvm.hexagon.M2.mpy.acc.ll.s1
		3, // llvm.hexagon.M2.mpy.acc.sat.hh.s0
		3, // llvm.hexagon.M2.mpy.acc.sat.hh.s1
		3, // llvm.hexagon.M2.mpy.acc.sat.hl.s0
		3, // llvm.hexagon.M2.mpy.acc.sat.hl.s1
		3, // llvm.hexagon.M2.mpy.acc.sat.lh.s0
		3, // llvm.hexagon.M2.mpy.acc.sat.lh.s1
		3, // llvm.hexagon.M2.mpy.acc.sat.ll.s0
		3, // llvm.hexagon.M2.mpy.acc.sat.ll.s1
		3, // llvm.hexagon.M2.mpy.hh.s0
		3, // llvm.hexagon.M2.mpy.hh.s1
		3, // llvm.hexagon.M2.mpy.hl.s0
		3, // llvm.hexagon.M2.mpy.hl.s1
		3, // llvm.hexagon.M2.mpy.lh.s0
		3, // llvm.hexagon.M2.mpy.lh.s1
		3, // llvm.hexagon.M2.mpy.ll.s0
		3, // llvm.hexagon.M2.mpy.ll.s1
		3, // llvm.hexagon.M2.mpy.nac.hh.s0
		3, // llvm.hexagon.M2.mpy.nac.hh.s1
		3, // llvm.hexagon.M2.mpy.nac.hl.s0
		3, // llvm.hexagon.M2.mpy.nac.hl.s1
		3, // llvm.hexagon.M2.mpy.nac.lh.s0
		3, // llvm.hexagon.M2.mpy.nac.lh.s1
		3, // llvm.hexagon.M2.mpy.nac.ll.s0
		3, // llvm.hexagon.M2.mpy.nac.ll.s1
		3, // llvm.hexagon.M2.mpy.nac.sat.hh.s0
		3, // llvm.hexagon.M2.mpy.nac.sat.hh.s1
		3, // llvm.hexagon.M2.mpy.nac.sat.hl.s0
		3, // llvm.hexagon.M2.mpy.nac.sat.hl.s1
		3, // llvm.hexagon.M2.mpy.nac.sat.lh.s0
		3, // llvm.hexagon.M2.mpy.nac.sat.lh.s1
		3, // llvm.hexagon.M2.mpy.nac.sat.ll.s0
		3, // llvm.hexagon.M2.mpy.nac.sat.ll.s1
		3, // llvm.hexagon.M2.mpy.rnd.hh.s0
		3, // llvm.hexagon.M2.mpy.rnd.hh.s1
		3, // llvm.hexagon.M2.mpy.rnd.hl.s0
		3, // llvm.hexagon.M2.mpy.rnd.hl.s1
		3, // llvm.hexagon.M2.mpy.rnd.lh.s0
		3, // llvm.hexagon.M2.mpy.rnd.lh.s1
		3, // llvm.hexagon.M2.mpy.rnd.ll.s0
		3, // llvm.hexagon.M2.mpy.rnd.ll.s1
		3, // llvm.hexagon.M2.mpy.sat.hh.s0
		3, // llvm.hexagon.M2.mpy.sat.hh.s1
		3, // llvm.hexagon.M2.mpy.sat.hl.s0
		3, // llvm.hexagon.M2.mpy.sat.hl.s1
		3, // llvm.hexagon.M2.mpy.sat.lh.s0
		3, // llvm.hexagon.M2.mpy.sat.lh.s1
		3, // llvm.hexagon.M2.mpy.sat.ll.s0
		3, // llvm.hexagon.M2.mpy.sat.ll.s1
		3, // llvm.hexagon.M2.mpy.sat.rnd.hh.s0
		3, // llvm.hexagon.M2.mpy.sat.rnd.hh.s1
		3, // llvm.hexagon.M2.mpy.sat.rnd.hl.s0
		3, // llvm.hexagon.M2.mpy.sat.rnd.hl.s1
		3, // llvm.hexagon.M2.mpy.sat.rnd.lh.s0
		3, // llvm.hexagon.M2.mpy.sat.rnd.lh.s1
		3, // llvm.hexagon.M2.mpy.sat.rnd.ll.s0
		3, // llvm.hexagon.M2.mpy.sat.rnd.ll.s1
		3, // llvm.hexagon.M2.mpy.up
		3, // llvm.hexagon.M2.mpyd.acc.hh.s0
		3, // llvm.hexagon.M2.mpyd.acc.hh.s1
		3, // llvm.hexagon.M2.mpyd.acc.hl.s0
		3, // llvm.hexagon.M2.mpyd.acc.hl.s1
		3, // llvm.hexagon.M2.mpyd.acc.lh.s0
		3, // llvm.hexagon.M2.mpyd.acc.lh.s1
		3, // llvm.hexagon.M2.mpyd.acc.ll.s0
		3, // llvm.hexagon.M2.mpyd.acc.ll.s1
		3, // llvm.hexagon.M2.mpyd.hh.s0
		3, // llvm.hexagon.M2.mpyd.hh.s1
		3, // llvm.hexagon.M2.mpyd.hl.s0
		3, // llvm.hexagon.M2.mpyd.hl.s1
		3, // llvm.hexagon.M2.mpyd.lh.s0
		3, // llvm.hexagon.M2.mpyd.lh.s1
		3, // llvm.hexagon.M2.mpyd.ll.s0
		3, // llvm.hexagon.M2.mpyd.ll.s1
		3, // llvm.hexagon.M2.mpyd.nac.hh.s0
		3, // llvm.hexagon.M2.mpyd.nac.hh.s1
		3, // llvm.hexagon.M2.mpyd.nac.hl.s0
		3, // llvm.hexagon.M2.mpyd.nac.hl.s1
		3, // llvm.hexagon.M2.mpyd.nac.lh.s0
		3, // llvm.hexagon.M2.mpyd.nac.lh.s1
		3, // llvm.hexagon.M2.mpyd.nac.ll.s0
		3, // llvm.hexagon.M2.mpyd.nac.ll.s1
		3, // llvm.hexagon.M2.mpyd.rnd.hh.s0
		3, // llvm.hexagon.M2.mpyd.rnd.hh.s1
		3, // llvm.hexagon.M2.mpyd.rnd.hl.s0
		3, // llvm.hexagon.M2.mpyd.rnd.hl.s1
		3, // llvm.hexagon.M2.mpyd.rnd.lh.s0
		3, // llvm.hexagon.M2.mpyd.rnd.lh.s1
		3, // llvm.hexagon.M2.mpyd.rnd.ll.s0
		3, // llvm.hexagon.M2.mpyd.rnd.ll.s1
		3, // llvm.hexagon.M2.mpyi
		3, // llvm.hexagon.M2.mpysmi
		3, // llvm.hexagon.M2.mpyu.acc.hh.s0
		3, // llvm.hexagon.M2.mpyu.acc.hh.s1
		3, // llvm.hexagon.M2.mpyu.acc.hl.s0
		3, // llvm.hexagon.M2.mpyu.acc.hl.s1
		3, // llvm.hexagon.M2.mpyu.acc.lh.s0
		3, // llvm.hexagon.M2.mpyu.acc.lh.s1
		3, // llvm.hexagon.M2.mpyu.acc.ll.s0
		3, // llvm.hexagon.M2.mpyu.acc.ll.s1
		3, // llvm.hexagon.M2.mpyu.hh.s0
		3, // llvm.hexagon.M2.mpyu.hh.s1
		3, // llvm.hexagon.M2.mpyu.hl.s0
		3, // llvm.hexagon.M2.mpyu.hl.s1
		3, // llvm.hexagon.M2.mpyu.lh.s0
		3, // llvm.hexagon.M2.mpyu.lh.s1
		3, // llvm.hexagon.M2.mpyu.ll.s0
		3, // llvm.hexagon.M2.mpyu.ll.s1
		3, // llvm.hexagon.M2.mpyu.nac.hh.s0
		3, // llvm.hexagon.M2.mpyu.nac.hh.s1
		3, // llvm.hexagon.M2.mpyu.nac.hl.s0
		3, // llvm.hexagon.M2.mpyu.nac.hl.s1
		3, // llvm.hexagon.M2.mpyu.nac.lh.s0
		3, // llvm.hexagon.M2.mpyu.nac.lh.s1
		3, // llvm.hexagon.M2.mpyu.nac.ll.s0
		3, // llvm.hexagon.M2.mpyu.nac.ll.s1
		3, // llvm.hexagon.M2.mpyu.up
		3, // llvm.hexagon.M2.mpyud.acc.hh.s0
		3, // llvm.hexagon.M2.mpyud.acc.hh.s1
		3, // llvm.hexagon.M2.mpyud.acc.hl.s0
		3, // llvm.hexagon.M2.mpyud.acc.hl.s1
		3, // llvm.hexagon.M2.mpyud.acc.lh.s0
		3, // llvm.hexagon.M2.mpyud.acc.lh.s1
		3, // llvm.hexagon.M2.mpyud.acc.ll.s0
		3, // llvm.hexagon.M2.mpyud.acc.ll.s1
		3, // llvm.hexagon.M2.mpyud.hh.s0
		3, // llvm.hexagon.M2.mpyud.hh.s1
		3, // llvm.hexagon.M2.mpyud.hl.s0
		3, // llvm.hexagon.M2.mpyud.hl.s1
		3, // llvm.hexagon.M2.mpyud.lh.s0
		3, // llvm.hexagon.M2.mpyud.lh.s1
		3, // llvm.hexagon.M2.mpyud.ll.s0
		3, // llvm.hexagon.M2.mpyud.ll.s1
		3, // llvm.hexagon.M2.mpyud.nac.hh.s0
		3, // llvm.hexagon.M2.mpyud.nac.hh.s1
		3, // llvm.hexagon.M2.mpyud.nac.hl.s0
		3, // llvm.hexagon.M2.mpyud.nac.hl.s1
		3, // llvm.hexagon.M2.mpyud.nac.lh.s0
		3, // llvm.hexagon.M2.mpyud.nac.lh.s1
		3, // llvm.hexagon.M2.mpyud.nac.ll.s0
		3, // llvm.hexagon.M2.mpyud.nac.ll.s1
		3, // llvm.hexagon.M2.mpyui
		3, // llvm.hexagon.M2.nacci
		3, // llvm.hexagon.M2.naccii
		3, // llvm.hexagon.M2.subacc
		3, // llvm.hexagon.M2.vabsdiffh
		3, // llvm.hexagon.M2.vabsdiffw
		3, // llvm.hexagon.M2.vcmac.s0.sat.i
		3, // llvm.hexagon.M2.vcmac.s0.sat.r
		3, // llvm.hexagon.M2.vcmpy.s0.sat.i
		3, // llvm.hexagon.M2.vcmpy.s0.sat.r
		3, // llvm.hexagon.M2.vcmpy.s1.sat.i
		3, // llvm.hexagon.M2.vcmpy.s1.sat.r
		3, // llvm.hexagon.M2.vdmacs.s0
		3, // llvm.hexagon.M2.vdmacs.s1
		3, // llvm.hexagon.M2.vdmpyrs.s0
		3, // llvm.hexagon.M2.vdmpyrs.s1
		3, // llvm.hexagon.M2.vdmpys.s0
		3, // llvm.hexagon.M2.vdmpys.s1
		3, // llvm.hexagon.M2.vmac2
		3, // llvm.hexagon.M2.vmac2es
		3, // llvm.hexagon.M2.vmac2es.s0
		3, // llvm.hexagon.M2.vmac2es.s1
		3, // llvm.hexagon.M2.vmac2s.s0
		3, // llvm.hexagon.M2.vmac2s.s1
		3, // llvm.hexagon.M2.vmpy2es.s0
		3, // llvm.hexagon.M2.vmpy2es.s1
		3, // llvm.hexagon.M2.vmpy2s.s0
		3, // llvm.hexagon.M2.vmpy2s.s0pack
		3, // llvm.hexagon.M2.vmpy2s.s1
		3, // llvm.hexagon.M2.vmpy2s.s1pack
		3, // llvm.hexagon.M2.vradduh
		3, // llvm.hexagon.M2.vrcmaci.s0
		3, // llvm.hexagon.M2.vrcmaci.s0c
		3, // llvm.hexagon.M2.vrcmacr.s0
		3, // llvm.hexagon.M2.vrcmacr.s0c
		3, // llvm.hexagon.M2.vrcmpyi.s0
		3, // llvm.hexagon.M2.vrcmpyi.s0c
		3, // llvm.hexagon.M2.vrcmpyr.s0
		3, // llvm.hexagon.M2.vrcmpyr.s0c
		3, // llvm.hexagon.M2.vrcmpys.acc.s1
		3, // llvm.hexagon.M2.vrcmpys.s1
		3, // llvm.hexagon.M2.vrcmpys.s1rp
		3, // llvm.hexagon.M2.vrmac.s0
		3, // llvm.hexagon.M2.vrmpy.s0
		3, // llvm.hexagon.M2.xor.xacc
		3, // llvm.hexagon.M4.and.and
		3, // llvm.hexagon.M4.and.andn
		3, // llvm.hexagon.M4.and.or
		3, // llvm.hexagon.M4.and.xor
		3, // llvm.hexagon.M4.or.and
		3, // llvm.hexagon.M4.or.andn
		3, // llvm.hexagon.M4.or.or
		3, // llvm.hexagon.M4.or.xor
		3, // llvm.hexagon.M4.xor.and
		3, // llvm.hexagon.M4.xor.andn
		3, // llvm.hexagon.M4.xor.or
		3, // llvm.hexagon.M4.xor.xacc
		3, // llvm.hexagon.S2.addasl.rrri
		3, // llvm.hexagon.S2.asl.i.p
		3, // llvm.hexagon.S2.asl.i.p.acc
		3, // llvm.hexagon.S2.asl.i.p.and
		3, // llvm.hexagon.S2.asl.i.p.nac
		3, // llvm.hexagon.S2.asl.i.p.or
		3, // llvm.hexagon.S2.asl.i.p.xacc
		3, // llvm.hexagon.S2.asl.i.r
		3, // llvm.hexagon.S2.asl.i.r.acc
		3, // llvm.hexagon.S2.asl.i.r.and
		3, // llvm.hexagon.S2.asl.i.r.nac
		3, // llvm.hexagon.S2.asl.i.r.or
		3, // llvm.hexagon.S2.asl.i.r.sat
		3, // llvm.hexagon.S2.asl.i.r.xacc
		3, // llvm.hexagon.S2.asl.i.vh
		3, // llvm.hexagon.S2.asl.i.vw
		3, // llvm.hexagon.S2.asl.r.p
		3, // llvm.hexagon.S2.asl.r.p.acc
		3, // llvm.hexagon.S2.asl.r.p.and
		3, // llvm.hexagon.S2.asl.r.p.nac
		3, // llvm.hexagon.S2.asl.r.p.or
		3, // llvm.hexagon.S2.asl.r.r
		3, // llvm.hexagon.S2.asl.r.r.acc
		3, // llvm.hexagon.S2.asl.r.r.and
		3, // llvm.hexagon.S2.asl.r.r.nac
		3, // llvm.hexagon.S2.asl.r.r.or
		3, // llvm.hexagon.S2.asl.r.r.sat
		3, // llvm.hexagon.S2.asl.r.vh
		3, // llvm.hexagon.S2.asl.r.vw
		3, // llvm.hexagon.S2.asr.i.p
		3, // llvm.hexagon.S2.asr.i.p.acc
		3, // llvm.hexagon.S2.asr.i.p.and
		3, // llvm.hexagon.S2.asr.i.p.nac
		3, // llvm.hexagon.S2.asr.i.p.or
		3, // llvm.hexagon.S2.asr.i.r
		3, // llvm.hexagon.S2.asr.i.r.acc
		3, // llvm.hexagon.S2.asr.i.r.and
		3, // llvm.hexagon.S2.asr.i.r.nac
		3, // llvm.hexagon.S2.asr.i.r.or
		3, // llvm.hexagon.S2.asr.i.r.rnd
		3, // llvm.hexagon.S2.asr.i.r.rnd.goodsyntax
		3, // llvm.hexagon.S2.asr.i.svw.trun
		3, // llvm.hexagon.S2.asr.i.vh
		3, // llvm.hexagon.S2.asr.i.vw
		3, // llvm.hexagon.S2.asr.r.p
		3, // llvm.hexagon.S2.asr.r.p.acc
		3, // llvm.hexagon.S2.asr.r.p.and
		3, // llvm.hexagon.S2.asr.r.p.nac
		3, // llvm.hexagon.S2.asr.r.p.or
		3, // llvm.hexagon.S2.asr.r.r
		3, // llvm.hexagon.S2.asr.r.r.acc
		3, // llvm.hexagon.S2.asr.r.r.and
		3, // llvm.hexagon.S2.asr.r.r.nac
		3, // llvm.hexagon.S2.asr.r.r.or
		3, // llvm.hexagon.S2.asr.r.r.sat
		3, // llvm.hexagon.S2.asr.r.svw.trun
		3, // llvm.hexagon.S2.asr.r.vh
		3, // llvm.hexagon.S2.asr.r.vw
		3, // llvm.hexagon.S2.brev
		3, // llvm.hexagon.S2.cl0
		3, // llvm.hexagon.S2.cl0p
		3, // llvm.hexagon.S2.cl1
		3, // llvm.hexagon.S2.cl1p
		3, // llvm.hexagon.S2.clb
		3, // llvm.hexagon.S2.clbnorm
		3, // llvm.hexagon.S2.clbp
		3, // llvm.hexagon.S2.clrbit.i
		3, // llvm.hexagon.S2.clrbit.r
		3, // llvm.hexagon.S2.ct0
		3, // llvm.hexagon.S2.ct1
		3, // llvm.hexagon.S2.deinterleave
		3, // llvm.hexagon.S2.extractu
		3, // llvm.hexagon.S2.extractu.rp
		3, // llvm.hexagon.S2.extractup
		3, // llvm.hexagon.S2.extractup.rp
		3, // llvm.hexagon.S2.insert
		3, // llvm.hexagon.S2.insert.rp
		3, // llvm.hexagon.S2.insertp
		3, // llvm.hexagon.S2.insertp.rp
		3, // llvm.hexagon.S2.interleave
		3, // llvm.hexagon.S2.lfsp
		3, // llvm.hexagon.S2.lsl.r.p
		3, // llvm.hexagon.S2.lsl.r.p.acc
		3, // llvm.hexagon.S2.lsl.r.p.and
		3, // llvm.hexagon.S2.lsl.r.p.nac
		3, // llvm.hexagon.S2.lsl.r.p.or
		3, // llvm.hexagon.S2.lsl.r.r
		3, // llvm.hexagon.S2.lsl.r.r.acc
		3, // llvm.hexagon.S2.lsl.r.r.and
		3, // llvm.hexagon.S2.lsl.r.r.nac
		3, // llvm.hexagon.S2.lsl.r.r.or
		3, // llvm.hexagon.S2.lsl.r.vh
		3, // llvm.hexagon.S2.lsl.r.vw
		3, // llvm.hexagon.S2.lsr.i.p
		3, // llvm.hexagon.S2.lsr.i.p.acc
		3, // llvm.hexagon.S2.lsr.i.p.and
		3, // llvm.hexagon.S2.lsr.i.p.nac
		3, // llvm.hexagon.S2.lsr.i.p.or
		3, // llvm.hexagon.S2.lsr.i.p.xacc
		3, // llvm.hexagon.S2.lsr.i.r
		3, // llvm.hexagon.S2.lsr.i.r.acc
		3, // llvm.hexagon.S2.lsr.i.r.and
		3, // llvm.hexagon.S2.lsr.i.r.nac
		3, // llvm.hexagon.S2.lsr.i.r.or
		3, // llvm.hexagon.S2.lsr.i.r.xacc
		3, // llvm.hexagon.S2.lsr.i.vh
		3, // llvm.hexagon.S2.lsr.i.vw
		3, // llvm.hexagon.S2.lsr.r.p
		3, // llvm.hexagon.S2.lsr.r.p.acc
		3, // llvm.hexagon.S2.lsr.r.p.and
		3, // llvm.hexagon.S2.lsr.r.p.nac
		3, // llvm.hexagon.S2.lsr.r.p.or
		3, // llvm.hexagon.S2.lsr.r.r
		3, // llvm.hexagon.S2.lsr.r.r.acc
		3, // llvm.hexagon.S2.lsr.r.r.and
		3, // llvm.hexagon.S2.lsr.r.r.nac
		3, // llvm.hexagon.S2.lsr.r.r.or
		3, // llvm.hexagon.S2.lsr.r.vh
		3, // llvm.hexagon.S2.lsr.r.vw
		3, // llvm.hexagon.S2.packhl
		3, // llvm.hexagon.S2.parityp
		3, // llvm.hexagon.S2.setbit.i
		3, // llvm.hexagon.S2.setbit.r
		3, // llvm.hexagon.S2.shuffeb
		3, // llvm.hexagon.S2.shuffeh
		3, // llvm.hexagon.S2.shuffob
		3, // llvm.hexagon.S2.shuffoh
		3, // llvm.hexagon.S2.svsathb
		3, // llvm.hexagon.S2.svsathub
		3, // llvm.hexagon.S2.tableidxb.goodsyntax
		3, // llvm.hexagon.S2.tableidxd.goodsyntax
		3, // llvm.hexagon.S2.tableidxh.goodsyntax
		3, // llvm.hexagon.S2.tableidxw.goodsyntax
		3, // llvm.hexagon.S2.togglebit.i
		3, // llvm.hexagon.S2.togglebit.r
		3, // llvm.hexagon.S2.tstbit.i
		3, // llvm.hexagon.S2.tstbit.r
		3, // llvm.hexagon.S2.valignib
		3, // llvm.hexagon.S2.valignrb
		3, // llvm.hexagon.S2.vcrotate
		3, // llvm.hexagon.S2.vrndpackwh
		3, // llvm.hexagon.S2.vrndpackwhs
		3, // llvm.hexagon.S2.vsathb
		3, // llvm.hexagon.S2.vsathb.nopack
		3, // llvm.hexagon.S2.vsathub
		3, // llvm.hexagon.S2.vsathub.nopack
		3, // llvm.hexagon.S2.vsatwh
		3, // llvm.hexagon.S2.vsatwh.nopack
		3, // llvm.hexagon.S2.vsatwuh
		3, // llvm.hexagon.S2.vsatwuh.nopack
		3, // llvm.hexagon.S2.vsplatrb
		3, // llvm.hexagon.S2.vsplatrh
		3, // llvm.hexagon.S2.vspliceib
		3, // llvm.hexagon.S2.vsplicerb
		3, // llvm.hexagon.S2.vsxtbh
		3, // llvm.hexagon.S2.vsxthw
		3, // llvm.hexagon.S2.vtrunehb
		3, // llvm.hexagon.S2.vtrunewh
		3, // llvm.hexagon.S2.vtrunohb
		3, // llvm.hexagon.S2.vtrunowh
		3, // llvm.hexagon.S2.vzxtbh
		3, // llvm.hexagon.S2.vzxthw
		3, // llvm.hexagon.S4.addaddi
		3, // llvm.hexagon.S4.andnp
		3, // llvm.hexagon.S4.or.andi
		3, // llvm.hexagon.S4.or.andix
		3, // llvm.hexagon.S4.or.ori
		3, // llvm.hexagon.S4.ornp
		3, // llvm.hexagon.S4.subaddi
		3, // llvm.hexagon.SI.to.SXTHI.asrh
		5, // llvm.init.trampoline
		6, // llvm.invariant.end
		7, // llvm.invariant.start
		7, // llvm.lifetime.end
		7, // llvm.lifetime.start
		1, // llvm.log
		1, // llvm.log10
		1, // llvm.log2
		2, // llvm.longjmp
		8, // llvm.memcpy
		8, // llvm.memmove
		5, // llvm.memset
		3, // llvm.objectsize
		2, // llvm.pcmarker
		1, // llvm.pow
		1, // llvm.powi
		2, // llvm.ppc.altivec.dss
		2, // llvm.ppc.altivec.dssall
		2, // llvm.ppc.altivec.dst
		2, // llvm.ppc.altivec.dstst
		2, // llvm.ppc.altivec.dststt
		2, // llvm.ppc.altivec.dstt
		1, // llvm.ppc.altivec.lvebx
		1, // llvm.ppc.altivec.lvehx
		1, // llvm.ppc.altivec.lvewx
		3, // llvm.ppc.altivec.lvsl
		3, // llvm.ppc.altivec.lvsr
		1, // llvm.ppc.altivec.lvx
		1, // llvm.ppc.altivec.lvxl
		1, // llvm.ppc.altivec.mfvscr
		2, // llvm.ppc.altivec.mtvscr
		2, // llvm.ppc.altivec.stvebx
		2, // llvm.ppc.altivec.stvehx
		2, // llvm.ppc.altivec.stvewx
		2, // llvm.ppc.altivec.stvx
		2, // llvm.ppc.altivec.stvxl
		3, // llvm.ppc.altivec.vaddcuw
		3, // llvm.ppc.altivec.vaddsbs
		3, // llvm.ppc.altivec.vaddshs
		3, // llvm.ppc.altivec.vaddsws
		3, // llvm.ppc.altivec.vaddubs
		3, // llvm.ppc.altivec.vadduhs
		3, // llvm.ppc.altivec.vadduws
		3, // llvm.ppc.altivec.vavgsb
		3, // llvm.ppc.altivec.vavgsh
		3, // llvm.ppc.altivec.vavgsw
		3, // llvm.ppc.altivec.vavgub
		3, // llvm.ppc.altivec.vavguh
		3, // llvm.ppc.altivec.vavguw
		3, // llvm.ppc.altivec.vcfsx
		3, // llvm.ppc.altivec.vcfux
		3, // llvm.ppc.altivec.vcmpbfp
		3, // llvm.ppc.altivec.vcmpbfp.p
		3, // llvm.ppc.altivec.vcmpeqfp
		3, // llvm.ppc.altivec.vcmpeqfp.p
		3, // llvm.ppc.altivec.vcmpequb
		3, // llvm.ppc.altivec.vcmpequb.p
		3, // llvm.ppc.altivec.vcmpequh
		3, // llvm.ppc.altivec.vcmpequh.p
		3, // llvm.ppc.altivec.vcmpequw
		3, // llvm.ppc.altivec.vcmpequw.p
		3, // llvm.ppc.altivec.vcmpgefp
		3, // llvm.ppc.altivec.vcmpgefp.p
		3, // llvm.ppc.altivec.vcmpgtfp
		3, // llvm.ppc.altivec.vcmpgtfp.p
		3, // llvm.ppc.altivec.vcmpgtsb
		3, // llvm.ppc.altivec.vcmpgtsb.p
		3, // llvm.ppc.altivec.vcmpgtsh
		3, // llvm.ppc.altivec.vcmpgtsh.p
		3, // llvm.ppc.altivec.vcmpgtsw
		3, // llvm.ppc.altivec.vcmpgtsw.p
		3, // llvm.ppc.altivec.vcmpgtub
		3, // llvm.ppc.altivec.vcmpgtub.p
		3, // llvm.ppc.altivec.vcmpgtuh
		3, // llvm.ppc.altivec.vcmpgtuh.p
		3, // llvm.ppc.altivec.vcmpgtuw
		3, // llvm.ppc.altivec.vcmpgtuw.p
		3, // llvm.ppc.altivec.vctsxs
		3, // llvm.ppc.altivec.vctuxs
		3, // llvm.ppc.altivec.vexptefp
		3, // llvm.ppc.altivec.vlogefp
		3, // llvm.ppc.altivec.vmaddfp
		3, // llvm.ppc.altivec.vmaxfp
		3, // llvm.ppc.altivec.vmaxsb
		3, // llvm.ppc.altivec.vmaxsh
		3, // llvm.ppc.altivec.vmaxsw
		3, // llvm.ppc.altivec.vmaxub
		3, // llvm.ppc.altivec.vmaxuh
		3, // llvm.ppc.altivec.vmaxuw
		3, // llvm.ppc.altivec.vmhaddshs
		3, // llvm.ppc.altivec.vmhraddshs
		3, // llvm.ppc.altivec.vminfp
		3, // llvm.ppc.altivec.vminsb
		3, // llvm.ppc.altivec.vminsh
		3, // llvm.ppc.altivec.vminsw
		3, // llvm.ppc.altivec.vminub
		3, // llvm.ppc.altivec.vminuh
		3, // llvm.ppc.altivec.vminuw
		3, // llvm.ppc.altivec.vmladduhm
		3, // llvm.ppc.altivec.vmsummbm
		3, // llvm.ppc.altivec.vmsumshm
		3, // llvm.ppc.altivec.vmsumshs
		3, // llvm.ppc.altivec.vmsumubm
		3, // llvm.ppc.altivec.vmsumuhm
		3, // llvm.ppc.altivec.vmsumuhs
		3, // llvm.ppc.altivec.vmulesb
		3, // llvm.ppc.altivec.vmulesh
		3, // llvm.ppc.altivec.vmuleub
		3, // llvm.ppc.altivec.vmuleuh
		3, // llvm.ppc.altivec.vmulosb
		3, // llvm.ppc.altivec.vmulosh
		3, // llvm.ppc.altivec.vmuloub
		3, // llvm.ppc.altivec.vmulouh
		3, // llvm.ppc.altivec.vnmsubfp
		3, // llvm.ppc.altivec.vperm
		3, // llvm.ppc.altivec.vpkpx
		3, // llvm.ppc.altivec.vpkshss
		3, // llvm.ppc.altivec.vpkshus
		3, // llvm.ppc.altivec.vpkswss
		3, // llvm.ppc.altivec.vpkswus
		3, // llvm.ppc.altivec.vpkuhus
		3, // llvm.ppc.altivec.vpkuwus
		3, // llvm.ppc.altivec.vrefp
		3, // llvm.ppc.altivec.vrfim
		3, // llvm.ppc.altivec.vrfin
		3, // llvm.ppc.altivec.vrfip
		3, // llvm.ppc.altivec.vrfiz
		3, // llvm.ppc.altivec.vrlb
		3, // llvm.ppc.altivec.vrlh
		3, // llvm.ppc.altivec.vrlw
		3, // llvm.ppc.altivec.vrsqrtefp
		3, // llvm.ppc.altivec.vsel
		3, // llvm.ppc.altivec.vsl
		3, // llvm.ppc.altivec.vslb
		3, // llvm.ppc.altivec.vslh
		3, // llvm.ppc.altivec.vslo
		3, // llvm.ppc.altivec.vslw
		3, // llvm.ppc.altivec.vsr
		3, // llvm.ppc.altivec.vsrab
		3, // llvm.ppc.altivec.vsrah
		3, // llvm.ppc.altivec.vsraw
		3, // llvm.ppc.altivec.vsrb
		3, // llvm.ppc.altivec.vsrh
		3, // llvm.ppc.altivec.vsro
		3, // llvm.ppc.altivec.vsrw
		3, // llvm.ppc.altivec.vsubcuw
		3, // llvm.ppc.altivec.vsubsbs
		3, // llvm.ppc.altivec.vsubshs
		3, // llvm.ppc.altivec.vsubsws
		3, // llvm.ppc.altivec.vsububs
		3, // llvm.ppc.altivec.vsubuhs
		3, // llvm.ppc.altivec.vsubuws
		3, // llvm.ppc.altivec.vsum2sws
		3, // llvm.ppc.altivec.vsum4sbs
		3, // llvm.ppc.altivec.vsum4shs
		3, // llvm.ppc.altivec.vsum4ubs
		3, // llvm.ppc.altivec.vsumsws
		3, // llvm.ppc.altivec.vupkhpx
		3, // llvm.ppc.altivec.vupkhsb
		3, // llvm.ppc.altivec.vupkhsh
		3, // llvm.ppc.altivec.vupklpx
		3, // llvm.ppc.altivec.vupklsb
		3, // llvm.ppc.altivec.vupklsh
		2, // llvm.ppc.dcba
		2, // llvm.ppc.dcbf
		2, // llvm.ppc.dcbi
		2, // llvm.ppc.dcbst
		2, // llvm.ppc.dcbt
		2, // llvm.ppc.dcbtst
		2, // llvm.ppc.dcbz
		2, // llvm.ppc.dcbzl
		2, // llvm.ppc.sync
		5, // llvm.prefetch
		2, // llvm.ptr.annotation
		2, // llvm.ptx.bar.sync
		3, // llvm.ptx.read.clock
		3, // llvm.ptx.read.clock64
		3, // llvm.ptx.read.ctaid.w
		3, // llvm.ptx.read.ctaid.x
		3, // llvm.ptx.read.ctaid.y
		3, // llvm.ptx.read.ctaid.z
		3, // llvm.ptx.read.gridid
		3, // llvm.ptx.read.laneid
		3, // llvm.ptx.read.lanemask.eq
		3, // llvm.ptx.read.lanemask.ge
		3, // llvm.ptx.read.lanemask.gt
		3, // llvm.ptx.read.lanemask.le
		3, // llvm.ptx.read.lanemask.lt
		3, // llvm.ptx.read.nctaid.w
		3, // llvm.ptx.read.nctaid.x
		3, // llvm.ptx.read.nctaid.y
		3, // llvm.ptx.read.nctaid.z
		3, // llvm.ptx.read.nsmid
		3, // llvm.ptx.read.ntid.w
		3, // llvm.ptx.read.ntid.x
		3, // llvm.ptx.read.ntid.y
		3, // llvm.ptx.read.ntid.z
		3, // llvm.ptx.read.nwarpid
		3, // llvm.ptx.read.pm0
		3, // llvm.ptx.read.pm1
		3, // llvm.ptx.read.pm2
		3, // llvm.ptx.read.pm3
		3, // llvm.ptx.read.smid
		3, // llvm.ptx.read.tid.w
		3, // llvm.ptx.read.tid.x
		3, // llvm.ptx.read.tid.y
		3, // llvm.ptx.read.tid.z
		3, // llvm.ptx.read.warpid
		2, // llvm.readcyclecounter
		3, // llvm.returnaddress
		3, // llvm.sadd.with.overflow
		2, // llvm.setjmp
		2, // llvm.siglongjmp
		2, // llvm.sigsetjmp
		1, // llvm.sin
		3, // llvm.smul.with.overflow
		3, // llvm.spu.si.a
		3, // llvm.spu.si.addx
		3, // llvm.spu.si.ah
		3, // llvm.spu.si.ahi
		3, // llvm.spu.si.ai
		3, // llvm.spu.si.and
		3, // llvm.spu.si.andbi
		3, // llvm.spu.si.andc
		3, // llvm.spu.si.andhi
		3, // llvm.spu.si.andi
		3, // llvm.spu.si.bg
		3, // llvm.spu.si.bgx
		3, // llvm.spu.si.ceq
		3, // llvm.spu.si.ceqb
		3, // llvm.spu.si.ceqbi
		3, // llvm.spu.si.ceqh
		3, // llvm.spu.si.ceqhi
		3, // llvm.spu.si.ceqi
		3, // llvm.spu.si.cg
		3, // llvm.spu.si.cgt
		3, // llvm.spu.si.cgtb
		3, // llvm.spu.si.cgtbi
		3, // llvm.spu.si.cgth
		3, // llvm.spu.si.cgthi
		3, // llvm.spu.si.cgti
		3, // llvm.spu.si.cgx
		3, // llvm.spu.si.clgt
		3, // llvm.spu.si.clgtb
		3, // llvm.spu.si.clgtbi
		3, // llvm.spu.si.clgth
		3, // llvm.spu.si.clgthi
		3, // llvm.spu.si.clgti
		3, // llvm.spu.si.dfa
		3, // llvm.spu.si.dfm
		3, // llvm.spu.si.dfma
		3, // llvm.spu.si.dfms
		3, // llvm.spu.si.dfnma
		3, // llvm.spu.si.dfnms
		3, // llvm.spu.si.dfs
		3, // llvm.spu.si.fa
		3, // llvm.spu.si.fceq
		3, // llvm.spu.si.fcgt
		3, // llvm.spu.si.fcmeq
		3, // llvm.spu.si.fcmgt
		3, // llvm.spu.si.fm
		3, // llvm.spu.si.fma
		3, // llvm.spu.si.fms
		3, // llvm.spu.si.fnms
		3, // llvm.spu.si.fs
		3, // llvm.spu.si.fsmbi
		3, // llvm.spu.si.mpy
		3, // llvm.spu.si.mpya
		3, // llvm.spu.si.mpyh
		3, // llvm.spu.si.mpyhh
		3, // llvm.spu.si.mpyhha
		3, // llvm.spu.si.mpyhhau
		3, // llvm.spu.si.mpyhhu
		3, // llvm.spu.si.mpyi
		3, // llvm.spu.si.mpys
		3, // llvm.spu.si.mpyu
		3, // llvm.spu.si.mpyui
		3, // llvm.spu.si.nand
		3, // llvm.spu.si.nor
		3, // llvm.spu.si.or
		3, // llvm.spu.si.orbi
		3, // llvm.spu.si.orc
		3, // llvm.spu.si.orhi
		3, // llvm.spu.si.ori
		3, // llvm.spu.si.sf
		3, // llvm.spu.si.sfh
		3, // llvm.spu.si.sfhi
		3, // llvm.spu.si.sfi
		3, // llvm.spu.si.sfx
		3, // llvm.spu.si.shli
		3, // llvm.spu.si.shlqbi
		3, // llvm.spu.si.shlqbii
		3, // llvm.spu.si.shlqby
		3, // llvm.spu.si.shlqbyi
		3, // llvm.spu.si.xor
		3, // llvm.spu.si.xorbi
		3, // llvm.spu.si.xorhi
		3, // llvm.spu.si.xori
		1, // llvm.sqrt
		3, // llvm.ssub.with.overflow
		2, // llvm.stackprotector
		2, // llvm.stackrestore
		2, // llvm.stacksave
		2, // llvm.trap
		3, // llvm.uadd.with.overflow
		3, // llvm.umul.with.overflow
		3, // llvm.usub.with.overflow
		2, // llvm.va_copy
		2, // llvm.va_end
		2, // llvm.var.annotation
		2, // llvm.va_start
		3, // llvm.x86.3dnow.pavgusb
		3, // llvm.x86.3dnow.pf2id
		3, // llvm.x86.3dnow.pfacc
		3, // llvm.x86.3dnow.pfadd
		3, // llvm.x86.3dnow.pfcmpeq
		3, // llvm.x86.3dnow.pfcmpge
		3, // llvm.x86.3dnow.pfcmpgt
		3, // llvm.x86.3dnow.pfmax
		3, // llvm.x86.3dnow.pfmin
		3, // llvm.x86.3dnow.pfmul
		3, // llvm.x86.3dnow.pfrcp
		3, // llvm.x86.3dnow.pfrcpit1
		3, // llvm.x86.3dnow.pfrcpit2
		3, // llvm.x86.3dnow.pfrsqit1
		3, // llvm.x86.3dnow.pfrsqrt
		3, // llvm.x86.3dnow.pfsub
		3, // llvm.x86.3dnow.pfsubr
		3, // llvm.x86.3dnow.pi2fd
		3, // llvm.x86.3dnow.pmulhrw
		3, // llvm.x86.3dnowa.pf2iw
		3, // llvm.x86.3dnowa.pfnacc
		3, // llvm.x86.3dnowa.pfpnacc
		3, // llvm.x86.3dnowa.pi2fw
		3, // llvm.x86.3dnowa.pswapd
		3, // llvm.x86.aesni.aesdec
		3, // llvm.x86.aesni.aesdeclast
		3, // llvm.x86.aesni.aesenc
		3, // llvm.x86.aesni.aesenclast
		3, // llvm.x86.aesni.aesimc
		3, // llvm.x86.aesni.aeskeygenassist
		1, // llvm.x86.avx2.maskload.d
		1, // llvm.x86.avx2.maskload.d.256
		1, // llvm.x86.avx2.maskload.q
		1, // llvm.x86.avx2.maskload.q.256
		2, // llvm.x86.avx2.maskstore.d
		2, // llvm.x86.avx2.maskstore.d.256
		2, // llvm.x86.avx2.maskstore.q
		2, // llvm.x86.avx2.maskstore.q.256
		1, // llvm.x86.avx2.movntdqa
		3, // llvm.x86.avx2.mpsadbw
		3, // llvm.x86.avx2.pabs.b
		3, // llvm.x86.avx2.pabs.d
		3, // llvm.x86.avx2.pabs.w
		3, // llvm.x86.avx2.packssdw
		3, // llvm.x86.avx2.packsswb
		3, // llvm.x86.avx2.packusdw
		3, // llvm.x86.avx2.packuswb
		3, // llvm.x86.avx2.padds.b
		3, // llvm.x86.avx2.padds.w
		3, // llvm.x86.avx2.paddus.b
		3, // llvm.x86.avx2.paddus.w
		3, // llvm.x86.avx2.pavg.b
		3, // llvm.x86.avx2.pavg.w
		3, // llvm.x86.avx2.pblendd.128
		3, // llvm.x86.avx2.pblendd.256
		3, // llvm.x86.avx2.pblendvb
		3, // llvm.x86.avx2.pblendw
		3, // llvm.x86.avx2.pbroadcastb.128
		3, // llvm.x86.avx2.pbroadcastb.256
		3, // llvm.x86.avx2.pbroadcastd.128
		3, // llvm.x86.avx2.pbroadcastd.256
		3, // llvm.x86.avx2.pbroadcastq.128
		3, // llvm.x86.avx2.pbroadcastq.256
		3, // llvm.x86.avx2.pbroadcastw.128
		3, // llvm.x86.avx2.pbroadcastw.256
		3, // llvm.x86.avx2.permd
		3, // llvm.x86.avx2.permps
		3, // llvm.x86.avx2.phadd.d
		3, // llvm.x86.avx2.phadd.sw
		3, // llvm.x86.avx2.phadd.w
		3, // llvm.x86.avx2.phsub.d
		3, // llvm.x86.avx2.phsub.sw
		3, // llvm.x86.avx2.phsub.w
		3, // llvm.x86.avx2.pmadd.ub.sw
		3, // llvm.x86.avx2.pmadd.wd
		3, // llvm.x86.avx2.pmaxs.b
		3, // llvm.x86.avx2.pmaxs.d
		3, // llvm.x86.avx2.pmaxs.w
		3, // llvm.x86.avx2.pmaxu.b
		3, // llvm.x86.avx2.pmaxu.d
		3, // llvm.x86.avx2.pmaxu.w
		3, // llvm.x86.avx2.pmins.b
		3, // llvm.x86.avx2.pmins.d
		3, // llvm.x86.avx2.pmins.w
		3, // llvm.x86.avx2.pminu.b
		3, // llvm.x86.avx2.pminu.d
		3, // llvm.x86.avx2.pminu.w
		3, // llvm.x86.avx2.pmovmskb
		3, // llvm.x86.avx2.pmovsxbd
		3, // llvm.x86.avx2.pmovsxbq
		3, // llvm.x86.avx2.pmovsxbw
		3, // llvm.x86.avx2.pmovsxdq
		3, // llvm.x86.avx2.pmovsxwd
		3, // llvm.x86.avx2.pmovsxwq
		3, // llvm.x86.avx2.pmovzxbd
		3, // llvm.x86.avx2.pmovzxbq
		3, // llvm.x86.avx2.pmovzxbw
		3, // llvm.x86.avx2.pmovzxdq
		3, // llvm.x86.avx2.pmovzxwd
		3, // llvm.x86.avx2.pmovzxwq
		3, // llvm.x86.avx2.pmul.dq
		3, // llvm.x86.avx2.pmul.hr.sw
		3, // llvm.x86.avx2.pmulh.w
		3, // llvm.x86.avx2.pmulhu.w
		3, // llvm.x86.avx2.pmulu.dq
		3, // llvm.x86.avx2.psad.bw
		3, // llvm.x86.avx2.pshuf.b
		3, // llvm.x86.avx2.psign.b
		3, // llvm.x86.avx2.psign.d
		3, // llvm.x86.avx2.psign.w
		3, // llvm.x86.avx2.psll.d
		3, // llvm.x86.avx2.psll.dq
		3, // llvm.x86.avx2.psll.dq.bs
		3, // llvm.x86.avx2.psll.q
		3, // llvm.x86.avx2.psll.w
		3, // llvm.x86.avx2.pslli.d
		3, // llvm.x86.avx2.pslli.q
		3, // llvm.x86.avx2.pslli.w
		3, // llvm.x86.avx2.psllv.d
		3, // llvm.x86.avx2.psllv.d.256
		3, // llvm.x86.avx2.psllv.q
		3, // llvm.x86.avx2.psllv.q.256
		3, // llvm.x86.avx2.psra.d
		3, // llvm.x86.avx2.psra.w
		3, // llvm.x86.avx2.psrai.d
		3, // llvm.x86.avx2.psrai.w
		3, // llvm.x86.avx2.psrav.d
		3, // llvm.x86.avx2.psrav.d.256
		3, // llvm.x86.avx2.psrl.d
		3, // llvm.x86.avx2.psrl.dq
		3, // llvm.x86.avx2.psrl.dq.bs
		3, // llvm.x86.avx2.psrl.q
		3, // llvm.x86.avx2.psrl.w
		3, // llvm.x86.avx2.psrli.d
		3, // llvm.x86.avx2.psrli.q
		3, // llvm.x86.avx2.psrli.w
		3, // llvm.x86.avx2.psrlv.d
		3, // llvm.x86.avx2.psrlv.d.256
		3, // llvm.x86.avx2.psrlv.q
		3, // llvm.x86.avx2.psrlv.q.256
		3, // llvm.x86.avx2.psubs.b
		3, // llvm.x86.avx2.psubs.w
		3, // llvm.x86.avx2.psubus.b
		3, // llvm.x86.avx2.psubus.w
		3, // llvm.x86.avx2.vbroadcast.sd.pd.256
		3, // llvm.x86.avx2.vbroadcast.ss.ps
		3, // llvm.x86.avx2.vbroadcast.ss.ps.256
		1, // llvm.x86.avx2.vbroadcasti128
		3, // llvm.x86.avx2.vextracti128
		3, // llvm.x86.avx2.vinserti128
		3, // llvm.x86.avx2.vperm2i128
		3, // llvm.x86.avx.addsub.pd.256
		3, // llvm.x86.avx.addsub.ps.256
		3, // llvm.x86.avx.blend.pd.256
		3, // llvm.x86.avx.blend.ps.256
		3, // llvm.x86.avx.blendv.pd.256
		3, // llvm.x86.avx.blendv.ps.256
		3, // llvm.x86.avx.cmp.pd.256
		3, // llvm.x86.avx.cmp.ps.256
		3, // llvm.x86.avx.cvt.pd2.ps.256
		3, // llvm.x86.avx.cvt.pd2dq.256
		3, // llvm.x86.avx.cvt.ps2.pd.256
		3, // llvm.x86.avx.cvt.ps2dq.256
		3, // llvm.x86.avx.cvtdq2.pd.256
		3, // llvm.x86.avx.cvtdq2.ps.256
		3, // llvm.x86.avx.cvtt.pd2dq.256
		3, // llvm.x86.avx.cvtt.ps2dq.256
		3, // llvm.x86.avx.dp.ps.256
		3, // llvm.x86.avx.hadd.pd.256
		3, // llvm.x86.avx.hadd.ps.256
		3, // llvm.x86.avx.hsub.pd.256
		3, // llvm.x86.avx.hsub.ps.256
		1, // llvm.x86.avx.ldu.dq.256
		1, // llvm.x86.avx.maskload.pd
		1, // llvm.x86.avx.maskload.pd.256
		1, // llvm.x86.avx.maskload.ps
		1, // llvm.x86.avx.maskload.ps.256
		2, // llvm.x86.avx.maskstore.pd
		2, // llvm.x86.avx.maskstore.pd.256
		2, // llvm.x86.avx.maskstore.ps
		2, // llvm.x86.avx.maskstore.ps.256
		3, // llvm.x86.avx.max.pd.256
		3, // llvm.x86.avx.max.ps.256
		3, // llvm.x86.avx.min.pd.256
		3, // llvm.x86.avx.min.ps.256
		3, // llvm.x86.avx.movmsk.pd.256
		3, // llvm.x86.avx.movmsk.ps.256
		2, // llvm.x86.avx.movnt.dq.256
		2, // llvm.x86.avx.movnt.pd.256
		2, // llvm.x86.avx.movnt.ps.256
		3, // llvm.x86.avx.ptestc.256
		3, // llvm.x86.avx.ptestnzc.256
		3, // llvm.x86.avx.ptestz.256
		3, // llvm.x86.avx.rcp.ps.256
		3, // llvm.x86.avx.round.pd.256
		3, // llvm.x86.avx.round.ps.256
		3, // llvm.x86.avx.rsqrt.ps.256
		3, // llvm.x86.avx.sqrt.pd.256
		3, // llvm.x86.avx.sqrt.ps.256
		2, // llvm.x86.avx.storeu.dq.256
		2, // llvm.x86.avx.storeu.pd.256
		2, // llvm.x86.avx.storeu.ps.256
		1, // llvm.x86.avx.vbroadcast.sd.256
		1, // llvm.x86.avx.vbroadcast.ss
		1, // llvm.x86.avx.vbroadcast.ss.256
		1, // llvm.x86.avx.vbroadcastf128.pd.256
		1, // llvm.x86.avx.vbroadcastf128.ps.256
		3, // llvm.x86.avx.vextractf128.pd.256
		3, // llvm.x86.avx.vextractf128.ps.256
		3, // llvm.x86.avx.vextractf128.si.256
		3, // llvm.x86.avx.vinsertf128.pd.256
		3, // llvm.x86.avx.vinsertf128.ps.256
		3, // llvm.x86.avx.vinsertf128.si.256
		3, // llvm.x86.avx.vperm2f128.pd.256
		3, // llvm.x86.avx.vperm2f128.ps.256
		3, // llvm.x86.avx.vperm2f128.si.256
		3, // llvm.x86.avx.vpermilvar.pd
		3, // llvm.x86.avx.vpermilvar.pd.256
		3, // llvm.x86.avx.vpermilvar.ps
		3, // llvm.x86.avx.vpermilvar.ps.256
		3, // llvm.x86.avx.vtestc.pd
		3, // llvm.x86.avx.vtestc.pd.256
		3, // llvm.x86.avx.vtestc.ps
		3, // llvm.x86.avx.vtestc.ps.256
		3, // llvm.x86.avx.vtestnzc.pd
		3, // llvm.x86.avx.vtestnzc.pd.256
		3, // llvm.x86.avx.vtestnzc.ps
		3, // llvm.x86.avx.vtestnzc.ps.256
		3, // llvm.x86.avx.vtestz.pd
		3, // llvm.x86.avx.vtestz.pd.256
		3, // llvm.x86.avx.vtestz.ps
		3, // llvm.x86.avx.vtestz.ps.256
		2, // llvm.x86.avx.vzeroall
		2, // llvm.x86.avx.vzeroupper
		3, // llvm.x86.bmi.bextr.32
		3, // llvm.x86.bmi.bextr.64
		3, // llvm.x86.bmi.bzhi.32
		3, // llvm.x86.bmi.bzhi.64
		3, // llvm.x86.bmi.pdep.32
		3, // llvm.x86.bmi.pdep.64
		3, // llvm.x86.bmi.pext.32
		3, // llvm.x86.bmi.pext.64
		3, // llvm.x86.fma4.vfmadd.pd
		3, // llvm.x86.fma4.vfmadd.pd.256
		3, // llvm.x86.fma4.vfmadd.ps
		3, // llvm.x86.fma4.vfmadd.ps.256
		3, // llvm.x86.fma4.vfmadd.sd
		3, // llvm.x86.fma4.vfmadd.ss
		3, // llvm.x86.fma4.vfmaddsub.pd
		3, // llvm.x86.fma4.vfmaddsub.pd.256
		3, // llvm.x86.fma4.vfmaddsub.ps
		3, // llvm.x86.fma4.vfmaddsub.ps.256
		3, // llvm.x86.fma4.vfmsub.pd
		3, // llvm.x86.fma4.vfmsub.pd.256
		3, // llvm.x86.fma4.vfmsub.ps
		3, // llvm.x86.fma4.vfmsub.ps.256
		3, // llvm.x86.fma4.vfmsub.sd
		3, // llvm.x86.fma4.vfmsub.ss
		3, // llvm.x86.fma4.vfmsubadd.pd
		3, // llvm.x86.fma4.vfmsubadd.pd.256
		3, // llvm.x86.fma4.vfmsubadd.ps
		3, // llvm.x86.fma4.vfmsubadd.ps.256
		3, // llvm.x86.fma4.vfnmadd.pd
		3, // llvm.x86.fma4.vfnmadd.pd.256
		3, // llvm.x86.fma4.vfnmadd.ps
		3, // llvm.x86.fma4.vfnmadd.ps.256
		3, // llvm.x86.fma4.vfnmadd.sd
		3, // llvm.x86.fma4.vfnmadd.ss
		3, // llvm.x86.fma4.vfnmsub.pd
		3, // llvm.x86.fma4.vfnmsub.pd.256
		3, // llvm.x86.fma4.vfnmsub.ps
		3, // llvm.x86.fma4.vfnmsub.ps.256
		3, // llvm.x86.fma4.vfnmsub.sd
		3, // llvm.x86.fma4.vfnmsub.ss
		2, // llvm.x86.int
		2, // llvm.x86.mmx.emms
		2, // llvm.x86.mmx.femms
		2, // llvm.x86.mmx.maskmovq
		2, // llvm.x86.mmx.movnt.dq
		3, // llvm.x86.mmx.packssdw
		3, // llvm.x86.mmx.packsswb
		3, // llvm.x86.mmx.packuswb
		3, // llvm.x86.mmx.padd.b
		3, // llvm.x86.mmx.padd.d
		3, // llvm.x86.mmx.padd.q
		3, // llvm.x86.mmx.padd.w
		3, // llvm.x86.mmx.padds.b
		3, // llvm.x86.mmx.padds.w
		3, // llvm.x86.mmx.paddus.b
		3, // llvm.x86.mmx.paddus.w
		3, // llvm.x86.mmx.palignr.b
		3, // llvm.x86.mmx.pand
		3, // llvm.x86.mmx.pandn
		3, // llvm.x86.mmx.pavg.b
		3, // llvm.x86.mmx.pavg.w
		3, // llvm.x86.mmx.pcmpeq.b
		3, // llvm.x86.mmx.pcmpeq.d
		3, // llvm.x86.mmx.pcmpeq.w
		3, // llvm.x86.mmx.pcmpgt.b
		3, // llvm.x86.mmx.pcmpgt.d
		3, // llvm.x86.mmx.pcmpgt.w
		3, // llvm.x86.mmx.pextr.w
		3, // llvm.x86.mmx.pinsr.w
		3, // llvm.x86.mmx.pmadd.wd
		3, // llvm.x86.mmx.pmaxs.w
		3, // llvm.x86.mmx.pmaxu.b
		3, // llvm.x86.mmx.pmins.w
		3, // llvm.x86.mmx.pminu.b
		3, // llvm.x86.mmx.pmovmskb
		3, // llvm.x86.mmx.pmulh.w
		3, // llvm.x86.mmx.pmulhu.w
		3, // llvm.x86.mmx.pmull.w
		3, // llvm.x86.mmx.pmulu.dq
		3, // llvm.x86.mmx.por
		3, // llvm.x86.mmx.psad.bw
		3, // llvm.x86.mmx.psll.d
		3, // llvm.x86.mmx.psll.q
		3, // llvm.x86.mmx.psll.w
		3, // llvm.x86.mmx.pslli.d
		3, // llvm.x86.mmx.pslli.q
		3, // llvm.x86.mmx.pslli.w
		3, // llvm.x86.mmx.psra.d
		3, // llvm.x86.mmx.psra.w
		3, // llvm.x86.mmx.psrai.d
		3, // llvm.x86.mmx.psrai.w
		3, // llvm.x86.mmx.psrl.d
		3, // llvm.x86.mmx.psrl.q
		3, // llvm.x86.mmx.psrl.w
		3, // llvm.x86.mmx.psrli.d
		3, // llvm.x86.mmx.psrli.q
		3, // llvm.x86.mmx.psrli.w
		3, // llvm.x86.mmx.psub.b
		3, // llvm.x86.mmx.psub.d
		3, // llvm.x86.mmx.psub.q
		3, // llvm.x86.mmx.psub.w
		3, // llvm.x86.mmx.psubs.b
		3, // llvm.x86.mmx.psubs.w
		3, // llvm.x86.mmx.psubus.b
		3, // llvm.x86.mmx.psubus.w
		3, // llvm.x86.mmx.punpckhbw
		3, // llvm.x86.mmx.punpckhdq
		3, // llvm.x86.mmx.punpckhwd
		3, // llvm.x86.mmx.punpcklbw
		3, // llvm.x86.mmx.punpckldq
		3, // llvm.x86.mmx.punpcklwd
		3, // llvm.x86.mmx.pxor
		2, // llvm.x86.rdfsbase.32
		2, // llvm.x86.rdfsbase.64
		2, // llvm.x86.rdgsbase.32
		2, // llvm.x86.rdgsbase.64
		3, // llvm.x86.sse2.add.sd
		2, // llvm.x86.sse2.clflush
		3, // llvm.x86.sse2.cmp.pd
		3, // llvm.x86.sse2.cmp.sd
		3, // llvm.x86.sse2.comieq.sd
		3, // llvm.x86.sse2.comige.sd
		3, // llvm.x86.sse2.comigt.sd
		3, // llvm.x86.sse2.comile.sd
		3, // llvm.x86.sse2.comilt.sd
		3, // llvm.x86.sse2.comineq.sd
		3, // llvm.x86.sse2.cvtdq2pd
		3, // llvm.x86.sse2.cvtdq2ps
		3, // llvm.x86.sse2.cvtpd2dq
		3, // llvm.x86.sse2.cvtpd2ps
		3, // llvm.x86.sse2.cvtps2dq
		3, // llvm.x86.sse2.cvtps2pd
		3, // llvm.x86.sse2.cvtsd2si
		3, // llvm.x86.sse2.cvtsd2si64
		3, // llvm.x86.sse2.cvtsd2ss
		3, // llvm.x86.sse2.cvtsi2sd
		3, // llvm.x86.sse2.cvtsi642sd
		3, // llvm.x86.sse2.cvtss2sd
		3, // llvm.x86.sse2.cvttpd2dq
		3, // llvm.x86.sse2.cvttps2dq
		3, // llvm.x86.sse2.cvttsd2si
		3, // llvm.x86.sse2.cvttsd2si64
		3, // llvm.x86.sse2.div.sd
		2, // llvm.x86.sse2.lfence
		2, // llvm.x86.sse2.maskmov.dqu
		3, // llvm.x86.sse2.max.pd
		3, // llvm.x86.sse2.max.sd
		2, // llvm.x86.sse2.mfence
		3, // llvm.x86.sse2.min.pd
		3, // llvm.x86.sse2.min.sd
		3, // llvm.x86.sse2.movmsk.pd
		3, // llvm.x86.sse2.mul.sd
		3, // llvm.x86.sse2.packssdw.128
		3, // llvm.x86.sse2.packsswb.128
		3, // llvm.x86.sse2.packuswb.128
		3, // llvm.x86.sse2.padds.b
		3, // llvm.x86.sse2.padds.w
		3, // llvm.x86.sse2.paddus.b
		3, // llvm.x86.sse2.paddus.w
		3, // llvm.x86.sse2.pavg.b
		3, // llvm.x86.sse2.pavg.w
		3, // llvm.x86.sse2.pmadd.wd
		3, // llvm.x86.sse2.pmaxs.w
		3, // llvm.x86.sse2.pmaxu.b
		3, // llvm.x86.sse2.pmins.w
		3, // llvm.x86.sse2.pminu.b
		3, // llvm.x86.sse2.pmovmskb.128
		3, // llvm.x86.sse2.pmulh.w
		3, // llvm.x86.sse2.pmulhu.w
		3, // llvm.x86.sse2.pmulu.dq
		3, // llvm.x86.sse2.psad.bw
		3, // llvm.x86.sse2.psll.d
		3, // llvm.x86.sse2.psll.dq
		3, // llvm.x86.sse2.psll.dq.bs
		3, // llvm.x86.sse2.psll.q
		3, // llvm.x86.sse2.psll.w
		3, // llvm.x86.sse2.pslli.d
		3, // llvm.x86.sse2.pslli.q
		3, // llvm.x86.sse2.pslli.w
		3, // llvm.x86.sse2.psra.d
		3, // llvm.x86.sse2.psra.w
		3, // llvm.x86.sse2.psrai.d
		3, // llvm.x86.sse2.psrai.w
		3, // llvm.x86.sse2.psrl.d
		3, // llvm.x86.sse2.psrl.dq
		3, // llvm.x86.sse2.psrl.dq.bs
		3, // llvm.x86.sse2.psrl.q
		3, // llvm.x86.sse2.psrl.w
		3, // llvm.x86.sse2.psrli.d
		3, // llvm.x86.sse2.psrli.q
		3, // llvm.x86.sse2.psrli.w
		3, // llvm.x86.sse2.psubs.b
		3, // llvm.x86.sse2.psubs.w
		3, // llvm.x86.sse2.psubus.b
		3, // llvm.x86.sse2.psubus.w
		3, // llvm.x86.sse2.sqrt.pd
		3, // llvm.x86.sse2.sqrt.sd
		2, // llvm.x86.sse2.storel.dq
		2, // llvm.x86.sse2.storeu.dq
		2, // llvm.x86.sse2.storeu.pd
		3, // llvm.x86.sse2.sub.sd
		3, // llvm.x86.sse2.ucomieq.sd
		3, // llvm.x86.sse2.ucomige.sd
		3, // llvm.x86.sse2.ucomigt.sd
		3, // llvm.x86.sse2.ucomile.sd
		3, // llvm.x86.sse2.ucomilt.sd
		3, // llvm.x86.sse2.ucomineq.sd
		3, // llvm.x86.sse3.addsub.pd
		3, // llvm.x86.sse3.addsub.ps
		3, // llvm.x86.sse3.hadd.pd
		3, // llvm.x86.sse3.hadd.ps
		3, // llvm.x86.sse3.hsub.pd
		3, // llvm.x86.sse3.hsub.ps
		1, // llvm.x86.sse3.ldu.dq
		2, // llvm.x86.sse3.monitor
		2, // llvm.x86.sse3.mwait
		3, // llvm.x86.sse41.blendpd
		3, // llvm.x86.sse41.blendps
		3, // llvm.x86.sse41.blendvpd
		3, // llvm.x86.sse41.blendvps
		3, // llvm.x86.sse41.dppd
		3, // llvm.x86.sse41.dpps
		3, // llvm.x86.sse41.extractps
		3, // llvm.x86.sse41.insertps
		1, // llvm.x86.sse41.movntdqa
		3, // llvm.x86.sse41.mpsadbw
		3, // llvm.x86.sse41.packusdw
		3, // llvm.x86.sse41.pblendvb
		3, // llvm.x86.sse41.pblendw
		3, // llvm.x86.sse41.pextrb
		3, // llvm.x86.sse41.pextrd
		3, // llvm.x86.sse41.pextrq
		3, // llvm.x86.sse41.phminposuw
		3, // llvm.x86.sse41.pmaxsb
		3, // llvm.x86.sse41.pmaxsd
		3, // llvm.x86.sse41.pmaxud
		3, // llvm.x86.sse41.pmaxuw
		3, // llvm.x86.sse41.pminsb
		3, // llvm.x86.sse41.pminsd
		3, // llvm.x86.sse41.pminud
		3, // llvm.x86.sse41.pminuw
		3, // llvm.x86.sse41.pmovsxbd
		3, // llvm.x86.sse41.pmovsxbq
		3, // llvm.x86.sse41.pmovsxbw
		3, // llvm.x86.sse41.pmovsxdq
		3, // llvm.x86.sse41.pmovsxwd
		3, // llvm.x86.sse41.pmovsxwq
		3, // llvm.x86.sse41.pmovzxbd
		3, // llvm.x86.sse41.pmovzxbq
		3, // llvm.x86.sse41.pmovzxbw
		3, // llvm.x86.sse41.pmovzxdq
		3, // llvm.x86.sse41.pmovzxwd
		3, // llvm.x86.sse41.pmovzxwq
		3, // llvm.x86.sse41.pmuldq
		3, // llvm.x86.sse41.ptestc
		3, // llvm.x86.sse41.ptestnzc
		3, // llvm.x86.sse41.ptestz
		3, // llvm.x86.sse41.round.pd
		3, // llvm.x86.sse41.round.ps
		3, // llvm.x86.sse41.round.sd
		3, // llvm.x86.sse41.round.ss
		3, // llvm.x86.sse42.crc32.32.16
		3, // llvm.x86.sse42.crc32.32.32
		3, // llvm.x86.sse42.crc32.32.8
		3, // llvm.x86.sse42.crc32.64.64
		3, // llvm.x86.sse42.crc32.64.8
		3, // llvm.x86.sse42.pcmpestri128
		3, // llvm.x86.sse42.pcmpestria128
		3, // llvm.x86.sse42.pcmpestric128
		3, // llvm.x86.sse42.pcmpestrio128
		3, // llvm.x86.sse42.pcmpestris128
		3, // llvm.x86.sse42.pcmpestriz128
		3, // llvm.x86.sse42.pcmpestrm128
		3, // llvm.x86.sse42.pcmpistri128
		3, // llvm.x86.sse42.pcmpistria128
		3, // llvm.x86.sse42.pcmpistric128
		3, // llvm.x86.sse42.pcmpistrio128
		3, // llvm.x86.sse42.pcmpistris128
		3, // llvm.x86.sse42.pcmpistriz128
		3, // llvm.x86.sse42.pcmpistrm128
		3, // llvm.x86.sse.add.ss
		3, // llvm.x86.sse.cmp.ps
		3, // llvm.x86.sse.cmp.ss
		3, // llvm.x86.sse.comieq.ss
		3, // llvm.x86.sse.comige.ss
		3, // llvm.x86.sse.comigt.ss
		3, // llvm.x86.sse.comile.ss
		3, // llvm.x86.sse.comilt.ss
		3, // llvm.x86.sse.comineq.ss
		3, // llvm.x86.sse.cvtpd2pi
		3, // llvm.x86.sse.cvtpi2pd
		3, // llvm.x86.sse.cvtpi2ps
		3, // llvm.x86.sse.cvtps2pi
		3, // llvm.x86.sse.cvtsi2ss
		3, // llvm.x86.sse.cvtsi642ss
		3, // llvm.x86.sse.cvtss2si
		3, // llvm.x86.sse.cvtss2si64
		3, // llvm.x86.sse.cvttpd2pi
		3, // llvm.x86.sse.cvttps2pi
		3, // llvm.x86.sse.cvttss2si
		3, // llvm.x86.sse.cvttss2si64
		3, // llvm.x86.sse.div.ss
		2, // llvm.x86.sse.ldmxcsr
		3, // llvm.x86.sse.max.ps
		3, // llvm.x86.sse.max.ss
		3, // llvm.x86.sse.min.ps
		3, // llvm.x86.sse.min.ss
		3, // llvm.x86.sse.movmsk.ps
		3, // llvm.x86.sse.mul.ss
		3, // llvm.x86.sse.pshuf.w
		3, // llvm.x86.sse.rcp.ps
		3, // llvm.x86.sse.rcp.ss
		3, // llvm.x86.sse.rsqrt.ps
		3, // llvm.x86.sse.rsqrt.ss
		2, // llvm.x86.sse.sfence
		3, // llvm.x86.sse.sqrt.ps
		3, // llvm.x86.sse.sqrt.ss
		2, // llvm.x86.sse.stmxcsr
		2, // llvm.x86.sse.storeu.ps
		3, // llvm.x86.sse.sub.ss
		3, // llvm.x86.sse.ucomieq.ss
		3, // llvm.x86.sse.ucomige.ss
		3, // llvm.x86.sse.ucomigt.ss
		3, // llvm.x86.sse.ucomile.ss
		3, // llvm.x86.sse.ucomilt.ss
		3, // llvm.x86.sse.ucomineq.ss
		3, // llvm.x86.ssse3.pabs.b
		3, // llvm.x86.ssse3.pabs.b.128
		3, // llvm.x86.ssse3.pabs.d
		3, // llvm.x86.ssse3.pabs.d.128
		3, // llvm.x86.ssse3.pabs.w
		3, // llvm.x86.ssse3.pabs.w.128
		3, // llvm.x86.ssse3.phadd.d
		3, // llvm.x86.ssse3.phadd.d.128
		3, // llvm.x86.ssse3.phadd.sw
		3, // llvm.x86.ssse3.phadd.sw.128
		3, // llvm.x86.ssse3.phadd.w
		3, // llvm.x86.ssse3.phadd.w.128
		3, // llvm.x86.ssse3.phsub.d
		3, // llvm.x86.ssse3.phsub.d.128
		3, // llvm.x86.ssse3.phsub.sw
		3, // llvm.x86.ssse3.phsub.sw.128
		3, // llvm.x86.ssse3.phsub.w
		3, // llvm.x86.ssse3.phsub.w.128
		3, // llvm.x86.ssse3.pmadd.ub.sw
		3, // llvm.x86.ssse3.pmadd.ub.sw.128
		3, // llvm.x86.ssse3.pmul.hr.sw
		3, // llvm.x86.ssse3.pmul.hr.sw.128
		3, // llvm.x86.ssse3.pshuf.b
		3, // llvm.x86.ssse3.pshuf.b.128
		3, // llvm.x86.ssse3.psign.b
		3, // llvm.x86.ssse3.psign.b.128
		3, // llvm.x86.ssse3.psign.d
		3, // llvm.x86.ssse3.psign.d.128
		3, // llvm.x86.ssse3.psign.w
		3, // llvm.x86.ssse3.psign.w.128
		3, // llvm.x86.vcvtph2ps.128
		3, // llvm.x86.vcvtph2ps.256
		3, // llvm.x86.vcvtps2ph.128
		3, // llvm.x86.vcvtps2ph.256
		2, // llvm.x86.wrfsbase.32
		2, // llvm.x86.wrfsbase.64
		2, // llvm.x86.wrgsbase.32
		2, // llvm.x86.wrgsbase.64
		3, // llvm.x86.xop.vfrcz.pd
		3, // llvm.x86.xop.vfrcz.pd.256
		3, // llvm.x86.xop.vfrcz.ps
		3, // llvm.x86.xop.vfrcz.ps.256
		3, // llvm.x86.xop.vfrcz.sd
		3, // llvm.x86.xop.vfrcz.ss
		3, // llvm.x86.xop.vpcmov
		3, // llvm.x86.xop.vpcmov.256
		3, // llvm.x86.xop.vpcomeqb
		3, // llvm.x86.xop.vpcomeqd
		3, // llvm.x86.xop.vpcomeqq
		3, // llvm.x86.xop.vpcomequb
		3, // llvm.x86.xop.vpcomequd
		3, // llvm.x86.xop.vpcomequq
		3, // llvm.x86.xop.vpcomequw
		3, // llvm.x86.xop.vpcomeqw
		3, // llvm.x86.xop.vpcomfalseb
		3, // llvm.x86.xop.vpcomfalsed
		3, // llvm.x86.xop.vpcomfalseq
		3, // llvm.x86.xop.vpcomfalseub
		3, // llvm.x86.xop.vpcomfalseud
		3, // llvm.x86.xop.vpcomfalseuq
		3, // llvm.x86.xop.vpcomfalseuw
		3, // llvm.x86.xop.vpcomfalsew
		3, // llvm.x86.xop.vpcomgeb
		3, // llvm.x86.xop.vpcomged
		3, // llvm.x86.xop.vpcomgeq
		3, // llvm.x86.xop.vpcomgeub
		3, // llvm.x86.xop.vpcomgeud
		3, // llvm.x86.xop.vpcomgeuq
		3, // llvm.x86.xop.vpcomgeuw
		3, // llvm.x86.xop.vpcomgew
		3, // llvm.x86.xop.vpcomgtb
		3, // llvm.x86.xop.vpcomgtd
		3, // llvm.x86.xop.vpcomgtq
		3, // llvm.x86.xop.vpcomgtub
		3, // llvm.x86.xop.vpcomgtud
		3, // llvm.x86.xop.vpcomgtuq
		3, // llvm.x86.xop.vpcomgtuw
		3, // llvm.x86.xop.vpcomgtw
		3, // llvm.x86.xop.vpcomleb
		3, // llvm.x86.xop.vpcomled
		3, // llvm.x86.xop.vpcomleq
		3, // llvm.x86.xop.vpcomleub
		3, // llvm.x86.xop.vpcomleud
		3, // llvm.x86.xop.vpcomleuq
		3, // llvm.x86.xop.vpcomleuw
		3, // llvm.x86.xop.vpcomlew
		3, // llvm.x86.xop.vpcomltb
		3, // llvm.x86.xop.vpcomltd
		3, // llvm.x86.xop.vpcomltq
		3, // llvm.x86.xop.vpcomltub
		3, // llvm.x86.xop.vpcomltud
		3, // llvm.x86.xop.vpcomltuq
		3, // llvm.x86.xop.vpcomltuw
		3, // llvm.x86.xop.vpcomltw
		3, // llvm.x86.xop.vpcomneb
		3, // llvm.x86.xop.vpcomned
		3, // llvm.x86.xop.vpcomneq
		3, // llvm.x86.xop.vpcomneub
		3, // llvm.x86.xop.vpcomneud
		3, // llvm.x86.xop.vpcomneuq
		3, // llvm.x86.xop.vpcomneuw
		3, // llvm.x86.xop.vpcomnew
		3, // llvm.x86.xop.vpcomtrueb
		3, // llvm.x86.xop.vpcomtrued
		3, // llvm.x86.xop.vpcomtrueq
		3, // llvm.x86.xop.vpcomtrueub
		3, // llvm.x86.xop.vpcomtrueud
		3, // llvm.x86.xop.vpcomtrueuq
		3, // llvm.x86.xop.vpcomtrueuw
		3, // llvm.x86.xop.vpcomtruew
		3, // llvm.x86.xop.vpermil2pd
		3, // llvm.x86.xop.vpermil2pd.256
		3, // llvm.x86.xop.vpermil2ps
		3, // llvm.x86.xop.vpermil2ps.256
		3, // llvm.x86.xop.vphaddbd
		3, // llvm.x86.xop.vphaddbq
		3, // llvm.x86.xop.vphaddbw
		3, // llvm.x86.xop.vphadddq
		3, // llvm.x86.xop.vphaddubd
		3, // llvm.x86.xop.vphaddubq
		3, // llvm.x86.xop.vphaddubw
		3, // llvm.x86.xop.vphaddudq
		3, // llvm.x86.xop.vphadduwd
		3, // llvm.x86.xop.vphadduwq
		3, // llvm.x86.xop.vphaddwd
		3, // llvm.x86.xop.vphaddwq
		3, // llvm.x86.xop.vphsubbw
		3, // llvm.x86.xop.vphsubdq
		3, // llvm.x86.xop.vphsubwd
		3, // llvm.x86.xop.vpmacsdd
		3, // llvm.x86.xop.vpmacsdqh
		3, // llvm.x86.xop.vpmacsdql
		3, // llvm.x86.xop.vpmacssdd
		3, // llvm.x86.xop.vpmacssdqh
		3, // llvm.x86.xop.vpmacssdql
		3, // llvm.x86.xop.vpmacsswd
		3, // llvm.x86.xop.vpmacssww
		3, // llvm.x86.xop.vpmacswd
		3, // llvm.x86.xop.vpmacsww
		3, // llvm.x86.xop.vpmadcsswd
		3, // llvm.x86.xop.vpmadcswd
		3, // llvm.x86.xop.vpperm
		3, // llvm.x86.xop.vprotb
		3, // llvm.x86.xop.vprotd
		3, // llvm.x86.xop.vprotq
		3, // llvm.x86.xop.vprotw
		3, // llvm.x86.xop.vpshab
		3, // llvm.x86.xop.vpshad
		3, // llvm.x86.xop.vpshaq
		3, // llvm.x86.xop.vpshaw
		3, // llvm.x86.xop.vpshlb
		3, // llvm.x86.xop.vpshld
		3, // llvm.x86.xop.vpshlq
		3, // llvm.x86.xop.vpshlw
		3, // llvm.xcore.bitrev
		2, // llvm.xcore.checkevent
		5, // llvm.xcore.chkct
		2, // llvm.xcore.clre
		2, // llvm.xcore.clrsr
		3, // llvm.xcore.crc32
		3, // llvm.xcore.crc8
		5, // llvm.xcore.eeu
		5, // llvm.xcore.endin
		5, // llvm.xcore.freer
		2, // llvm.xcore.geted
		2, // llvm.xcore.getet
		3, // llvm.xcore.getid
		2, // llvm.xcore.getps
		2, // llvm.xcore.getr
		5, // llvm.xcore.getst
		5, // llvm.xcore.getts
		5, // llvm.xcore.in
		5, // llvm.xcore.inct
		5, // llvm.xcore.initcp
		5, // llvm.xcore.initdp
		5, // llvm.xcore.initlr
		5, // llvm.xcore.initpc
		5, // llvm.xcore.initsp
		5, // llvm.xcore.inshr
		5, // llvm.xcore.int
		5, // llvm.xcore.mjoin
		5, // llvm.xcore.msync
		5, // llvm.xcore.out
		5, // llvm.xcore.outct
		5, // llvm.xcore.outshr
		5, // llvm.xcore.outt
		5, // llvm.xcore.peek
		5, // llvm.xcore.setc
		8, // llvm.xcore.setclk
		5, // llvm.xcore.setd
		5, // llvm.xcore.setev
		2, // llvm.xcore.setps
		5, // llvm.xcore.setpsc
		5, // llvm.xcore.setpt
		8, // llvm.xcore.setrdy
		2, // llvm.xcore.setsr
		5, // llvm.xcore.settw
		5, // llvm.xcore.setv
		3, // llvm.xcore.sext
		2, // llvm.xcore.ssync
		5, // llvm.xcore.syncr
		5, // llvm.xcore.testct
		5, // llvm.xcore.testwct
		1, // llvm.xcore.waitevent
		3, // llvm.xcore.zext
		};

		AttributeWithIndex AWI[3];
		unsigned NumAttrs = 0;
		if (id != 0) {
		switch(IntrinsicsToAttributesMap[id - 1]) {
		default: llvm_unreachable("Invalid attribute number");
		case 3:
		AWI[0] = AttributeWithIndex::get(~0, Attribute::NoUnwind\|Attribute::R
		eadNone);
		NumAttrs = 1;
		break;
		case 1:
		AWI[0] = AttributeWithIndex::get(~0, Attribute::NoUnwind\|Attribute::R
		eadOnly);
		NumAttrs = 1;
		break;
		case 2:
		AWI[0] = AttributeWithIndex::get(~0, Attribute::NoUnwind);
		NumAttrs = 1;
		break;
		case 5:
		AWI[0] = AttributeWithIndex::get(1, Attribute::NoCapture);
		AWI[1] = AttributeWithIndex::get(~0, Attribute::NoUnwind);
		NumAttrs = 2;
		break;
		case 8:
		AWI[0] = AttributeWithIndex::get(1, Attribute::NoCapture);
		AWI[1] = AttributeWithIndex::get(2, Attribute::NoCapture);
		AWI[2] = AttributeWithIndex::get(~0, Attribute::NoUnwind);
		NumAttrs = 3;
		break;
		case 7:
		AWI[0] = AttributeWithIndex::get(2, Attribute::NoCapture);
		AWI[1] = AttributeWithIndex::get(~0, Attribute::NoUnwind);
		NumAttrs = 2;
		break;
		case 4:
		AWI[0] = AttributeWithIndex::get(2, Attribute::NoCapture);
		AWI[1] = AttributeWithIndex::get(3, Attribute::NoCapture);
		AWI[2] = AttributeWithIndex::get(~0, Attribute::NoUnwind);
		NumAttrs = 3;
		break;
		case 6:
		AWI[0] = AttributeWithIndex::get(3, Attribute::NoCapture);
		AWI[1] = AttributeWithIndex::get(~0, Attribute::NoUnwind);
		NumAttrs = 2;
		break;
		}
		}
		return AttrListPtr::get(AWI, NumAttrs);
		}
		#endif // GET_INTRINSIC_ATTRIBUTES

		// Determine intrinsic alias analysis mod/ref behavior.
		#ifdef GET_INTRINSIC_MODREF_BEHAVIOR
		assert(iid <= Intrinsic::xcore_zext && "Unknown intrinsic.");

		static const uint8_t IntrinsicModRefBehavior[] = {
		/* invalid */ UnknownModRefBehavior,
		/* adjust_trampoline */ OnlyReadsArgumentPointees,
		/* annotation */ UnknownModRefBehavior,
		/* arm_cdp */ UnknownModRefBehavior,
		/* arm_cdp2 */ UnknownModRefBehavior,
		/* arm_get_fpscr */ DoesNotAccessMemory,
		/* arm_ldrexd */ OnlyReadsArgumentPointees,
		/* arm_mcr */ UnknownModRefBehavior,
		/* arm_mcr2 */ UnknownModRefBehavior,
		/* arm_mcrr */ UnknownModRefBehavior,
		/* arm_mcrr2 */ UnknownModRefBehavior,
		/* arm_mrc */ UnknownModRefBehavior,
		/* arm_mrc2 */ UnknownModRefBehavior,
		/* arm_neon_vabds */ DoesNotAccessMemory,
		/* arm_neon_vabdu */ DoesNotAccessMemory,
		/* arm_neon_vabs */ DoesNotAccessMemory,
		/* arm_neon_vacged */ DoesNotAccessMemory,
		/* arm_neon_vacgeq */ DoesNotAccessMemory,
		/* arm_neon_vacgtd */ DoesNotAccessMemory,
		/* arm_neon_vacgtq */ DoesNotAccessMemory,
		/* arm_neon_vaddhn */ DoesNotAccessMemory,
		/* arm_neon_vcls */ DoesNotAccessMemory,
		/* arm_neon_vclz */ DoesNotAccessMemory,
		/* arm_neon_vcnt */ DoesNotAccessMemory,
		/* arm_neon_vcvtfp2fxs */ DoesNotAccessMemory,
		/* arm_neon_vcvtfp2fxu */ DoesNotAccessMemory,
		/* arm_neon_vcvtfp2hf */ DoesNotAccessMemory,
		/* arm_neon_vcvtfxs2fp */ DoesNotAccessMemory,
		/* arm_neon_vcvtfxu2fp */ DoesNotAccessMemory,
		/* arm_neon_vcvthf2fp */ DoesNotAccessMemory,
		/* arm_neon_vhadds */ DoesNotAccessMemory,
		/* arm_neon_vhaddu */ DoesNotAccessMemory,
		/* arm_neon_vhsubs */ DoesNotAccessMemory,
		/* arm_neon_vhsubu */ DoesNotAccessMemory,
		/* arm_neon_vld1 */ OnlyReadsArgumentPointees,
		/* arm_neon_vld2 */ OnlyReadsArgumentPointees,
		/* arm_neon_vld2lane */ OnlyReadsArgumentPointees,
		/* arm_neon_vld3 */ OnlyReadsArgumentPointees,
		/* arm_neon_vld3lane */ OnlyReadsArgumentPointees,
		/* arm_neon_vld4 */ OnlyReadsArgumentPointees,
		/* arm_neon_vld4lane */ OnlyReadsArgumentPointees,
		/* arm_neon_vmaxs */ DoesNotAccessMemory,
		/* arm_neon_vmaxu */ DoesNotAccessMemory,
		/* arm_neon_vmins */ DoesNotAccessMemory,
		/* arm_neon_vminu */ DoesNotAccessMemory,
		/* arm_neon_vmullp */ DoesNotAccessMemory,
		/* arm_neon_vmulls */ DoesNotAccessMemory,
		/* arm_neon_vmullu */ DoesNotAccessMemory,
		/* arm_neon_vmulp */ DoesNotAccessMemory,
		/* arm_neon_vpadals */ DoesNotAccessMemory,
		/* arm_neon_vpadalu */ DoesNotAccessMemory,
		/* arm_neon_vpadd */ DoesNotAccessMemory,
		/* arm_neon_vpaddls */ DoesNotAccessMemory,
		/* arm_neon_vpaddlu */ DoesNotAccessMemory,
		/* arm_neon_vpmaxs */ DoesNotAccessMemory,
		/* arm_neon_vpmaxu */ DoesNotAccessMemory,
		/* arm_neon_vpmins */ DoesNotAccessMemory,
		/* arm_neon_vpminu */ DoesNotAccessMemory,
		/* arm_neon_vqabs */ DoesNotAccessMemory,
		/* arm_neon_vqadds */ DoesNotAccessMemory,
		/* arm_neon_vqaddu */ DoesNotAccessMemory,
		/* arm_neon_vqdmlal */ DoesNotAccessMemory,
		/* arm_neon_vqdmlsl */ DoesNotAccessMemory,
		/* arm_neon_vqdmulh */ DoesNotAccessMemory,
		/* arm_neon_vqdmull */ DoesNotAccessMemory,
		/* arm_neon_vqmovns */ DoesNotAccessMemory,
		/* arm_neon_vqmovnsu */ DoesNotAccessMemory,
		/* arm_neon_vqmovnu */ DoesNotAccessMemory,
		/* arm_neon_vqneg */ DoesNotAccessMemory,
		/* arm_neon_vqrdmulh */ DoesNotAccessMemory,
		/* arm_neon_vqrshiftns */ DoesNotAccessMemory,
		/* arm_neon_vqrshiftnsu */ DoesNotAccessMemory,
		/* arm_neon_vqrshiftnu */ DoesNotAccessMemory,
		/* arm_neon_vqrshifts */ DoesNotAccessMemory,
		/* arm_neon_vqrshiftu */ DoesNotAccessMemory,
		/* arm_neon_vqshiftns */ DoesNotAccessMemory,
		/* arm_neon_vqshiftnsu */ DoesNotAccessMemory,
		/* arm_neon_vqshiftnu */ DoesNotAccessMemory,
		/* arm_neon_vqshifts */ DoesNotAccessMemory,
		/* arm_neon_vqshiftsu */ DoesNotAccessMemory,
		/* arm_neon_vqshiftu */ DoesNotAccessMemory,
		/* arm_neon_vqsubs */ DoesNotAccessMemory,
		/* arm_neon_vqsubu */ DoesNotAccessMemory,
		/* arm_neon_vraddhn */ DoesNotAccessMemory,
		/* arm_neon_vrecpe */ DoesNotAccessMemory,
		/* arm_neon_vrecps */ DoesNotAccessMemory,
		/* arm_neon_vrhadds */ DoesNotAccessMemory,
		/* arm_neon_vrhaddu */ DoesNotAccessMemory,
		/* arm_neon_vrshiftn */ DoesNotAccessMemory,
		/* arm_neon_vrshifts */ DoesNotAccessMemory,
		/* arm_neon_vrshiftu */ DoesNotAccessMemory,
		/* arm_neon_vrsqrte */ DoesNotAccessMemory,
		/* arm_neon_vrsqrts */ DoesNotAccessMemory,
		/* arm_neon_vrsubhn */ DoesNotAccessMemory,
		/* arm_neon_vshiftins */ DoesNotAccessMemory,
		/* arm_neon_vshiftls */ DoesNotAccessMemory,
		/* arm_neon_vshiftlu */ DoesNotAccessMemory,
		/* arm_neon_vshiftn */ DoesNotAccessMemory,
		/* arm_neon_vshifts */ DoesNotAccessMemory,
		/* arm_neon_vshiftu */ DoesNotAccessMemory,
		/* arm_neon_vst1 */ OnlyAccessesArgumentPointees,
		/* arm_neon_vst2 */ OnlyAccessesArgumentPointees,
		/* arm_neon_vst2lane */ OnlyAccessesArgumentPointees,
		/* arm_neon_vst3 */ OnlyAccessesArgumentPointees,
		/* arm_neon_vst3lane */ OnlyAccessesArgumentPointees,
		/* arm_neon_vst4 */ OnlyAccessesArgumentPointees,
		/* arm_neon_vst4lane */ OnlyAccessesArgumentPointees,
		/* arm_neon_vsubhn */ DoesNotAccessMemory,
		/* arm_neon_vtbl1 */ DoesNotAccessMemory,
		/* arm_neon_vtbl2 */ DoesNotAccessMemory,
		/* arm_neon_vtbl3 */ DoesNotAccessMemory,
		/* arm_neon_vtbl4 */ DoesNotAccessMemory,
		/* arm_neon_vtbx1 */ DoesNotAccessMemory,
		/* arm_neon_vtbx2 */ DoesNotAccessMemory,
		/* arm_neon_vtbx3 */ DoesNotAccessMemory,
		/* arm_neon_vtbx4 */ DoesNotAccessMemory,
		/* arm_qadd */ DoesNotAccessMemory,
		/* arm_qsub */ DoesNotAccessMemory,
		/* arm_set_fpscr */ UnknownModRefBehavior,
		/* arm_ssat */ DoesNotAccessMemory,
		/* arm_strexd */ OnlyAccessesArgumentPointees,
		/* arm_thread_pointer */ DoesNotAccessMemory,
		/* arm_usat */ DoesNotAccessMemory,
		/* arm_vcvtr */ DoesNotAccessMemory,
		/* arm_vcvtru */ DoesNotAccessMemory,
		/* bswap */ DoesNotAccessMemory,
		/* convert_from_fp16 */ DoesNotAccessMemory,
		/* convert_to_fp16 */ DoesNotAccessMemory,
		/* convertff */ UnknownModRefBehavior,
		/* convertfsi */ UnknownModRefBehavior,
		/* convertfui */ UnknownModRefBehavior,
		/* convertsif */ UnknownModRefBehavior,
		/* convertss */ UnknownModRefBehavior,
		/* convertsu */ UnknownModRefBehavior,
		/* convertuif */ UnknownModRefBehavior,
		/* convertus */ UnknownModRefBehavior,
		/* convertuu */ UnknownModRefBehavior,
		/* cos */ OnlyReadsMemory,
		/* ctlz */ DoesNotAccessMemory,
		/* ctpop */ DoesNotAccessMemory,
		/* cttz */ DoesNotAccessMemory,
		/* dbg_declare */ DoesNotAccessMemory,
		/* dbg_value */ DoesNotAccessMemory,
		/* eh_dwarf_cfa */ UnknownModRefBehavior,
		/* eh_return_i32 */ UnknownModRefBehavior,
		/* eh_return_i64 */ UnknownModRefBehavior,
		/* eh_sjlj_callsite */ DoesNotAccessMemory,
		/* eh_sjlj_functioncontext */ UnknownModRefBehavior,
		/* eh_sjlj_longjmp */ UnknownModRefBehavior,
		/* eh_sjlj_lsda */ DoesNotAccessMemory,
		/* eh_sjlj_setjmp */ UnknownModRefBehavior,
		/* eh_typeid_for */ DoesNotAccessMemory,
		/* eh_unwind_init */ UnknownModRefBehavior,
		/* exp */ OnlyReadsMemory,
		/* exp2 */ OnlyReadsMemory,
		/* expect */ DoesNotAccessMemory,
		/* flt_rounds */ UnknownModRefBehavior,
		/* fma */ DoesNotAccessMemory,
		/* frameaddress */ DoesNotAccessMemory,
		/* gcread */ OnlyReadsArgumentPointees,
		/* gcroot */ UnknownModRefBehavior,
		/* gcwrite */ OnlyAccessesArgumentPointees,
		/* hexagon_A2_abs */ DoesNotAccessMemory,
		/* hexagon_A2_absp */ DoesNotAccessMemory,
		/* hexagon_A2_abssat */ DoesNotAccessMemory,
		/* hexagon_A2_add */ DoesNotAccessMemory,
		/* hexagon_A2_addh_h16_hh */ DoesNotAccessMemory,
		/* hexagon_A2_addh_h16_hl */ DoesNotAccessMemory,
		/* hexagon_A2_addh_h16_lh */ DoesNotAccessMemory,
		/* hexagon_A2_addh_h16_ll */ DoesNotAccessMemory,
		/* hexagon_A2_addh_h16_sat_hh */ DoesNotAccessMemory,
		/* hexagon_A2_addh_h16_sat_hl */ DoesNotAccessMemory,
		/* hexagon_A2_addh_h16_sat_lh */ DoesNotAccessMemory,
		/* hexagon_A2_addh_h16_sat_ll */ DoesNotAccessMemory,
		/* hexagon_A2_addh_l16_hh */ DoesNotAccessMemory,
		/* hexagon_A2_addh_l16_hl */ DoesNotAccessMemory,
		/* hexagon_A2_addh_l16_lh */ DoesNotAccessMemory,
		/* hexagon_A2_addh_l16_ll */ DoesNotAccessMemory,
		/* hexagon_A2_addh_l16_sat_hh */ DoesNotAccessMemory,
		/* hexagon_A2_addh_l16_sat_hl */ DoesNotAccessMemory,
		/* hexagon_A2_addh_l16_sat_lh */ DoesNotAccessMemory,
		/* hexagon_A2_addh_l16_sat_ll */ DoesNotAccessMemory,
		/* hexagon_A2_addi */ DoesNotAccessMemory,
		/* hexagon_A2_addp */ DoesNotAccessMemory,
		/* hexagon_A2_addpsat */ DoesNotAccessMemory,
		/* hexagon_A2_addsat */ DoesNotAccessMemory,
		/* hexagon_A2_addsp */ DoesNotAccessMemory,
		/* hexagon_A2_and */ DoesNotAccessMemory,
		/* hexagon_A2_andir */ DoesNotAccessMemory,
		/* hexagon_A2_andp */ DoesNotAccessMemory,
		/* hexagon_A2_aslh */ DoesNotAccessMemory,
		/* hexagon_A2_asrh */ DoesNotAccessMemory,
		/* hexagon_A2_combine_hh */ DoesNotAccessMemory,
		/* hexagon_A2_combine_hl */ DoesNotAccessMemory,
		/* hexagon_A2_combine_lh */ DoesNotAccessMemory,
		/* hexagon_A2_combine_ll */ DoesNotAccessMemory,
		/* hexagon_A2_combineii */ DoesNotAccessMemory,
		/* hexagon_A2_combinew */ DoesNotAccessMemory,
		/* hexagon_A2_max */ DoesNotAccessMemory,
		/* hexagon_A2_maxp */ DoesNotAccessMemory,
		/* hexagon_A2_maxu */ DoesNotAccessMemory,
		/* hexagon_A2_maxup */ DoesNotAccessMemory,
		/* hexagon_A2_min */ DoesNotAccessMemory,
		/* hexagon_A2_minp */ DoesNotAccessMemory,
		/* hexagon_A2_minu */ DoesNotAccessMemory,
		/* hexagon_A2_minup */ DoesNotAccessMemory,
		/* hexagon_A2_neg */ DoesNotAccessMemory,
		/* hexagon_A2_negp */ DoesNotAccessMemory,
		/* hexagon_A2_negsat */ DoesNotAccessMemory,
		/* hexagon_A2_not */ DoesNotAccessMemory,
		/* hexagon_A2_notp */ DoesNotAccessMemory,
		/* hexagon_A2_or */ DoesNotAccessMemory,
		/* hexagon_A2_orir */ DoesNotAccessMemory,
		/* hexagon_A2_orp */ DoesNotAccessMemory,
		/* hexagon_A2_sat */ DoesNotAccessMemory,
		/* hexagon_A2_satb */ DoesNotAccessMemory,
		/* hexagon_A2_sath */ DoesNotAccessMemory,
		/* hexagon_A2_satub */ DoesNotAccessMemory,
		/* hexagon_A2_satuh */ DoesNotAccessMemory,
		/* hexagon_A2_sub */ DoesNotAccessMemory,
		/* hexagon_A2_subh_h16_hh */ DoesNotAccessMemory,
		/* hexagon_A2_subh_h16_hl */ DoesNotAccessMemory,
		/* hexagon_A2_subh_h16_lh */ DoesNotAccessMemory,
		/* hexagon_A2_subh_h16_ll */ DoesNotAccessMemory,
		/* hexagon_A2_subh_h16_sat_hh */ DoesNotAccessMemory,
		/* hexagon_A2_subh_h16_sat_hl */ DoesNotAccessMemory,
		/* hexagon_A2_subh_h16_sat_lh */ DoesNotAccessMemory,
		/* hexagon_A2_subh_h16_sat_ll */ DoesNotAccessMemory,
		/* hexagon_A2_subh_l16_hl */ DoesNotAccessMemory,
		/* hexagon_A2_subh_l16_ll */ DoesNotAccessMemory,
		/* hexagon_A2_subh_l16_sat_hl */ DoesNotAccessMemory,
		/* hexagon_A2_subh_l16_sat_ll */ DoesNotAccessMemory,
		/* hexagon_A2_subp */ DoesNotAccessMemory,
		/* hexagon_A2_subri */ DoesNotAccessMemory,
		/* hexagon_A2_subsat */ DoesNotAccessMemory,
		/* hexagon_A2_svaddh */ DoesNotAccessMemory,
		/* hexagon_A2_svaddhs */ DoesNotAccessMemory,
		/* hexagon_A2_svadduhs */ DoesNotAccessMemory,
		/* hexagon_A2_svavgh */ DoesNotAccessMemory,
		/* hexagon_A2_svavghs */ DoesNotAccessMemory,
		/* hexagon_A2_svnavgh */ DoesNotAccessMemory,
		/* hexagon_A2_svsubh */ DoesNotAccessMemory,
		/* hexagon_A2_svsubhs */ DoesNotAccessMemory,
		/* hexagon_A2_svsubuhs */ DoesNotAccessMemory,
		/* hexagon_A2_swiz */ DoesNotAccessMemory,
		/* hexagon_A2_sxtb */ DoesNotAccessMemory,
		/* hexagon_A2_sxth */ DoesNotAccessMemory,
		/* hexagon_A2_sxtw */ DoesNotAccessMemory,
		/* hexagon_A2_tfr */ DoesNotAccessMemory,
		/* hexagon_A2_tfrih */ DoesNotAccessMemory,
		/* hexagon_A2_tfril */ DoesNotAccessMemory,
		/* hexagon_A2_tfrp */ DoesNotAccessMemory,
		/* hexagon_A2_tfrpi */ DoesNotAccessMemory,
		/* hexagon_A2_tfrsi */ DoesNotAccessMemory,
		/* hexagon_A2_vabsh */ DoesNotAccessMemory,
		/* hexagon_A2_vabshsat */ DoesNotAccessMemory,
		/* hexagon_A2_vabsw */ DoesNotAccessMemory,
		/* hexagon_A2_vabswsat */ DoesNotAccessMemory,
		/* hexagon_A2_vaddh */ DoesNotAccessMemory,
		/* hexagon_A2_vaddhs */ DoesNotAccessMemory,
		/* hexagon_A2_vaddub */ DoesNotAccessMemory,
		/* hexagon_A2_vaddubs */ DoesNotAccessMemory,
		/* hexagon_A2_vadduhs */ DoesNotAccessMemory,
		/* hexagon_A2_vaddw */ DoesNotAccessMemory,
		/* hexagon_A2_vaddws */ DoesNotAccessMemory,
		/* hexagon_A2_vavgh */ DoesNotAccessMemory,
		/* hexagon_A2_vavghcr */ DoesNotAccessMemory,
		/* hexagon_A2_vavghr */ DoesNotAccessMemory,
		/* hexagon_A2_vavgub */ DoesNotAccessMemory,
		/* hexagon_A2_vavgubr */ DoesNotAccessMemory,
		/* hexagon_A2_vavguh */ DoesNotAccessMemory,
		/* hexagon_A2_vavguhr */ DoesNotAccessMemory,
		/* hexagon_A2_vavguw */ DoesNotAccessMemory,
		/* hexagon_A2_vavguwr */ DoesNotAccessMemory,
		/* hexagon_A2_vavgw */ DoesNotAccessMemory,
		/* hexagon_A2_vavgwcr */ DoesNotAccessMemory,
		/* hexagon_A2_vavgwr */ DoesNotAccessMemory,
		/* hexagon_A2_vcmpbeq */ DoesNotAccessMemory,
		/* hexagon_A2_vcmpbgtu */ DoesNotAccessMemory,
		/* hexagon_A2_vcmpheq */ DoesNotAccessMemory,
		/* hexagon_A2_vcmphgt */ DoesNotAccessMemory,
		/* hexagon_A2_vcmphgtu */ DoesNotAccessMemory,
		/* hexagon_A2_vcmpweq */ DoesNotAccessMemory,
		/* hexagon_A2_vcmpwgt */ DoesNotAccessMemory,
		/* hexagon_A2_vcmpwgtu */ DoesNotAccessMemory,
		/* hexagon_A2_vconj */ DoesNotAccessMemory,
		/* hexagon_A2_vmaxh */ DoesNotAccessMemory,
		/* hexagon_A2_vmaxub */ DoesNotAccessMemory,
		/* hexagon_A2_vmaxuh */ DoesNotAccessMemory,
		/* hexagon_A2_vmaxuw */ DoesNotAccessMemory,
		/* hexagon_A2_vmaxw */ DoesNotAccessMemory,
		/* hexagon_A2_vminh */ DoesNotAccessMemory,
		/* hexagon_A2_vminub */ DoesNotAccessMemory,
		/* hexagon_A2_vminuh */ DoesNotAccessMemory,
		/* hexagon_A2_vminuw */ DoesNotAccessMemory,
		/* hexagon_A2_vminw */ DoesNotAccessMemory,
		/* hexagon_A2_vnavgh */ DoesNotAccessMemory,
		/* hexagon_A2_vnavghcr */ DoesNotAccessMemory,
		/* hexagon_A2_vnavghr */ DoesNotAccessMemory,
		/* hexagon_A2_vnavgw */ DoesNotAccessMemory,
		/* hexagon_A2_vnavgwcr */ DoesNotAccessMemory,
		/* hexagon_A2_vnavgwr */ DoesNotAccessMemory,
		/* hexagon_A2_vraddub */ DoesNotAccessMemory,
		/* hexagon_A2_vraddub_acc */ DoesNotAccessMemory,
		/* hexagon_A2_vrsadub */ DoesNotAccessMemory,
		/* hexagon_A2_vrsadub_acc */ DoesNotAccessMemory,
		/* hexagon_A2_vsubh */ DoesNotAccessMemory,
		/* hexagon_A2_vsubhs */ DoesNotAccessMemory,
		/* hexagon_A2_vsubub */ DoesNotAccessMemory,
		/* hexagon_A2_vsububs */ DoesNotAccessMemory,
		/* hexagon_A2_vsubuhs */ DoesNotAccessMemory,
		/* hexagon_A2_vsubw */ DoesNotAccessMemory,
		/* hexagon_A2_vsubws */ DoesNotAccessMemory,
		/* hexagon_A2_xor */ DoesNotAccessMemory,
		/* hexagon_A2_xorp */ DoesNotAccessMemory,
		/* hexagon_A2_zxtb */ DoesNotAccessMemory,
		/* hexagon_A2_zxth */ DoesNotAccessMemory,
		/* hexagon_A4_andn */ DoesNotAccessMemory,
		/* hexagon_A4_andnp */ DoesNotAccessMemory,
		/* hexagon_A4_combineir */ DoesNotAccessMemory,
		/* hexagon_A4_combineri */ DoesNotAccessMemory,
		/* hexagon_A4_cround_ri */ DoesNotAccessMemory,
		/* hexagon_A4_cround_rr */ DoesNotAccessMemory,
		/* hexagon_A4_modwrapu */ DoesNotAccessMemory,
		/* hexagon_A4_orn */ DoesNotAccessMemory,
		/* hexagon_A4_ornp */ DoesNotAccessMemory,
		/* hexagon_A4_rcmpeq */ DoesNotAccessMemory,
		/* hexagon_A4_rcmpeqi */ DoesNotAccessMemory,
		/* hexagon_A4_rcmpneq */ DoesNotAccessMemory,
		/* hexagon_A4_rcmpneqi */ DoesNotAccessMemory,
		/* hexagon_A4_round_ri */ DoesNotAccessMemory,
		/* hexagon_A4_round_ri_sat */ DoesNotAccessMemory,
		/* hexagon_A4_round_rr */ DoesNotAccessMemory,
		/* hexagon_A4_round_rr_sat */ DoesNotAccessMemory,
		/* hexagon_C2_all8 */ DoesNotAccessMemory,
		/* hexagon_C2_and */ DoesNotAccessMemory,
		/* hexagon_C2_andn */ DoesNotAccessMemory,
		/* hexagon_C2_any8 */ DoesNotAccessMemory,
		/* hexagon_C2_bitsclr */ DoesNotAccessMemory,
		/* hexagon_C2_bitsclri */ DoesNotAccessMemory,
		/* hexagon_C2_bitsset */ DoesNotAccessMemory,
		/* hexagon_C2_cmpeq */ DoesNotAccessMemory,
		/* hexagon_C2_cmpeqi */ DoesNotAccessMemory,
		/* hexagon_C2_cmpeqp */ DoesNotAccessMemory,
		/* hexagon_C2_cmpgei */ DoesNotAccessMemory,
		/* hexagon_C2_cmpgeui */ DoesNotAccessMemory,
		/* hexagon_C2_cmpgt */ DoesNotAccessMemory,
		/* hexagon_C2_cmpgti */ DoesNotAccessMemory,
		/* hexagon_C2_cmpgtp */ DoesNotAccessMemory,
		/* hexagon_C2_cmpgtu */ DoesNotAccessMemory,
		/* hexagon_C2_cmpgtui */ DoesNotAccessMemory,
		/* hexagon_C2_cmpgtup */ DoesNotAccessMemory,
		/* hexagon_C2_cmplt */ DoesNotAccessMemory,
		/* hexagon_C2_cmpltu */ DoesNotAccessMemory,
		/* hexagon_C2_mask */ DoesNotAccessMemory,
		/* hexagon_C2_mux */ DoesNotAccessMemory,
		/* hexagon_C2_muxii */ DoesNotAccessMemory,
		/* hexagon_C2_muxir */ DoesNotAccessMemory,
		/* hexagon_C2_muxri */ DoesNotAccessMemory,
		/* hexagon_C2_not */ DoesNotAccessMemory,
		/* hexagon_C2_or */ DoesNotAccessMemory,
		/* hexagon_C2_orn */ DoesNotAccessMemory,
		/* hexagon_C2_pxfer_map */ DoesNotAccessMemory,
		/* hexagon_C2_tfrpr */ DoesNotAccessMemory,
		/* hexagon_C2_tfrrp */ DoesNotAccessMemory,
		/* hexagon_C2_vitpack */ DoesNotAccessMemory,
		/* hexagon_C2_vmux */ DoesNotAccessMemory,
		/* hexagon_C2_xor */ DoesNotAccessMemory,
		/* hexagon_C4_and_and */ DoesNotAccessMemory,
		/* hexagon_C4_and_andn */ DoesNotAccessMemory,
		/* hexagon_C4_and_or */ DoesNotAccessMemory,
		/* hexagon_C4_and_orn */ DoesNotAccessMemory,
		/* hexagon_C4_cmplte */ DoesNotAccessMemory,
		/* hexagon_C4_cmpltei */ DoesNotAccessMemory,
		/* hexagon_C4_cmplteu */ DoesNotAccessMemory,
		/* hexagon_C4_cmplteui */ DoesNotAccessMemory,
		/* hexagon_C4_cmpneq */ DoesNotAccessMemory,
		/* hexagon_C4_cmpneqi */ DoesNotAccessMemory,
		/* hexagon_C4_fastcorner9 */ DoesNotAccessMemory,
		/* hexagon_C4_fastcorner9_not */ DoesNotAccessMemory,
		/* hexagon_C4_or_and */ DoesNotAccessMemory,
		/* hexagon_C4_or_andn */ DoesNotAccessMemory,
		/* hexagon_C4_or_or */ DoesNotAccessMemory,
		/* hexagon_C4_or_orn */ DoesNotAccessMemory,
		/* hexagon_M2_acci */ DoesNotAccessMemory,
		/* hexagon_M2_accii */ DoesNotAccessMemory,
		/* hexagon_M2_cmaci_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_cmacr_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_cmacs_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_cmacs_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_cmacsc_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_cmacsc_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_cmpyi_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_cmpyr_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_cmpyrs_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_cmpyrs_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_cmpyrsc_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_cmpyrsc_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_cmpys_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_cmpys_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_cmpysc_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_cmpysc_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_cnacs_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_cnacs_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_cnacsc_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_cnacsc_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_dpmpyss_acc_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_dpmpyss_nac_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_dpmpyss_rnd_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_dpmpyss_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_dpmpyuu_acc_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_dpmpyuu_nac_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_dpmpyuu_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_hmmpyh_rs1 */ DoesNotAccessMemory,
		/* hexagon_M2_hmmpyl_rs1 */ DoesNotAccessMemory,
		/* hexagon_M2_maci */ DoesNotAccessMemory,
		/* hexagon_M2_macsin */ DoesNotAccessMemory,
		/* hexagon_M2_macsip */ DoesNotAccessMemory,
		/* hexagon_M2_mmachs_rs0 */ DoesNotAccessMemory,
		/* hexagon_M2_mmachs_rs1 */ DoesNotAccessMemory,
		/* hexagon_M2_mmachs_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mmachs_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mmacls_rs0 */ DoesNotAccessMemory,
		/* hexagon_M2_mmacls_rs1 */ DoesNotAccessMemory,
		/* hexagon_M2_mmacls_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mmacls_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mmacuhs_rs0 */ DoesNotAccessMemory,
		/* hexagon_M2_mmacuhs_rs1 */ DoesNotAccessMemory,
		/* hexagon_M2_mmacuhs_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mmacuhs_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mmaculs_rs0 */ DoesNotAccessMemory,
		/* hexagon_M2_mmaculs_rs1 */ DoesNotAccessMemory,
		/* hexagon_M2_mmaculs_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mmaculs_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mmpyh_rs0 */ DoesNotAccessMemory,
		/* hexagon_M2_mmpyh_rs1 */ DoesNotAccessMemory,
		/* hexagon_M2_mmpyh_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mmpyh_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mmpyl_rs0 */ DoesNotAccessMemory,
		/* hexagon_M2_mmpyl_rs1 */ DoesNotAccessMemory,
		/* hexagon_M2_mmpyl_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mmpyl_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mmpyuh_rs0 */ DoesNotAccessMemory,
		/* hexagon_M2_mmpyuh_rs1 */ DoesNotAccessMemory,
		/* hexagon_M2_mmpyuh_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mmpyuh_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mmpyul_rs0 */ DoesNotAccessMemory,
		/* hexagon_M2_mmpyul_rs1 */ DoesNotAccessMemory,
		/* hexagon_M2_mmpyul_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mmpyul_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mpy_acc_hh_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mpy_acc_hh_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mpy_acc_hl_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mpy_acc_hl_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mpy_acc_lh_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mpy_acc_lh_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mpy_acc_ll_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mpy_acc_ll_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mpy_acc_sat_hh_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mpy_acc_sat_hh_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mpy_acc_sat_hl_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mpy_acc_sat_hl_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mpy_acc_sat_lh_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mpy_acc_sat_lh_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mpy_acc_sat_ll_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mpy_acc_sat_ll_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mpy_hh_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mpy_hh_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mpy_hl_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mpy_hl_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mpy_lh_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mpy_lh_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mpy_ll_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mpy_ll_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mpy_nac_hh_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mpy_nac_hh_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mpy_nac_hl_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mpy_nac_hl_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mpy_nac_lh_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mpy_nac_lh_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mpy_nac_ll_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mpy_nac_ll_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mpy_nac_sat_hh_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mpy_nac_sat_hh_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mpy_nac_sat_hl_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mpy_nac_sat_hl_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mpy_nac_sat_lh_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mpy_nac_sat_lh_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mpy_nac_sat_ll_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mpy_nac_sat_ll_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mpy_rnd_hh_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mpy_rnd_hh_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mpy_rnd_hl_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mpy_rnd_hl_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mpy_rnd_lh_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mpy_rnd_lh_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mpy_rnd_ll_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mpy_rnd_ll_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mpy_sat_hh_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mpy_sat_hh_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mpy_sat_hl_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mpy_sat_hl_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mpy_sat_lh_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mpy_sat_lh_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mpy_sat_ll_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mpy_sat_ll_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mpy_sat_rnd_hh_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mpy_sat_rnd_hh_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mpy_sat_rnd_hl_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mpy_sat_rnd_hl_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mpy_sat_rnd_lh_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mpy_sat_rnd_lh_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mpy_sat_rnd_ll_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mpy_sat_rnd_ll_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mpy_up */ DoesNotAccessMemory,
		/* hexagon_M2_mpyd_acc_hh_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyd_acc_hh_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyd_acc_hl_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyd_acc_hl_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyd_acc_lh_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyd_acc_lh_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyd_acc_ll_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyd_acc_ll_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyd_hh_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyd_hh_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyd_hl_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyd_hl_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyd_lh_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyd_lh_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyd_ll_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyd_ll_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyd_nac_hh_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyd_nac_hh_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyd_nac_hl_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyd_nac_hl_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyd_nac_lh_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyd_nac_lh_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyd_nac_ll_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyd_nac_ll_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyd_rnd_hh_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyd_rnd_hh_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyd_rnd_hl_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyd_rnd_hl_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyd_rnd_lh_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyd_rnd_lh_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyd_rnd_ll_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyd_rnd_ll_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyi */ DoesNotAccessMemory,
		/* hexagon_M2_mpysmi */ DoesNotAccessMemory,
		/* hexagon_M2_mpyu_acc_hh_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyu_acc_hh_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyu_acc_hl_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyu_acc_hl_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyu_acc_lh_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyu_acc_lh_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyu_acc_ll_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyu_acc_ll_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyu_hh_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyu_hh_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyu_hl_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyu_hl_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyu_lh_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyu_lh_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyu_ll_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyu_ll_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyu_nac_hh_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyu_nac_hh_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyu_nac_hl_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyu_nac_hl_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyu_nac_lh_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyu_nac_lh_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyu_nac_ll_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyu_nac_ll_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyu_up */ DoesNotAccessMemory,
		/* hexagon_M2_mpyud_acc_hh_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyud_acc_hh_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyud_acc_hl_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyud_acc_hl_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyud_acc_lh_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyud_acc_lh_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyud_acc_ll_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyud_acc_ll_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyud_hh_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyud_hh_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyud_hl_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyud_hl_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyud_lh_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyud_lh_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyud_ll_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyud_ll_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyud_nac_hh_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyud_nac_hh_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyud_nac_hl_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyud_nac_hl_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyud_nac_lh_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyud_nac_lh_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyud_nac_ll_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyud_nac_ll_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_mpyui */ DoesNotAccessMemory,
		/* hexagon_M2_nacci */ DoesNotAccessMemory,
		/* hexagon_M2_naccii */ DoesNotAccessMemory,
		/* hexagon_M2_subacc */ DoesNotAccessMemory,
		/* hexagon_M2_vabsdiffh */ DoesNotAccessMemory,
		/* hexagon_M2_vabsdiffw */ DoesNotAccessMemory,
		/* hexagon_M2_vcmac_s0_sat_i */ DoesNotAccessMemory,
		/* hexagon_M2_vcmac_s0_sat_r */ DoesNotAccessMemory,
		/* hexagon_M2_vcmpy_s0_sat_i */ DoesNotAccessMemory,
		/* hexagon_M2_vcmpy_s0_sat_r */ DoesNotAccessMemory,
		/* hexagon_M2_vcmpy_s1_sat_i */ DoesNotAccessMemory,
		/* hexagon_M2_vcmpy_s1_sat_r */ DoesNotAccessMemory,
		/* hexagon_M2_vdmacs_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_vdmacs_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_vdmpyrs_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_vdmpyrs_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_vdmpys_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_vdmpys_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_vmac2 */ DoesNotAccessMemory,
		/* hexagon_M2_vmac2es */ DoesNotAccessMemory,
		/* hexagon_M2_vmac2es_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_vmac2es_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_vmac2s_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_vmac2s_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_vmpy2es_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_vmpy2es_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_vmpy2s_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_vmpy2s_s0pack */ DoesNotAccessMemory,
		/* hexagon_M2_vmpy2s_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_vmpy2s_s1pack */ DoesNotAccessMemory,
		/* hexagon_M2_vradduh */ DoesNotAccessMemory,
		/* hexagon_M2_vrcmaci_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_vrcmaci_s0c */ DoesNotAccessMemory,
		/* hexagon_M2_vrcmacr_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_vrcmacr_s0c */ DoesNotAccessMemory,
		/* hexagon_M2_vrcmpyi_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_vrcmpyi_s0c */ DoesNotAccessMemory,
		/* hexagon_M2_vrcmpyr_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_vrcmpyr_s0c */ DoesNotAccessMemory,
		/* hexagon_M2_vrcmpys_acc_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_vrcmpys_s1 */ DoesNotAccessMemory,
		/* hexagon_M2_vrcmpys_s1rp */ DoesNotAccessMemory,
		/* hexagon_M2_vrmac_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_vrmpy_s0 */ DoesNotAccessMemory,
		/* hexagon_M2_xor_xacc */ DoesNotAccessMemory,
		/* hexagon_M4_and_and */ DoesNotAccessMemory,
		/* hexagon_M4_and_andn */ DoesNotAccessMemory,
		/* hexagon_M4_and_or */ DoesNotAccessMemory,
		/* hexagon_M4_and_xor */ DoesNotAccessMemory,
		/* hexagon_M4_or_and */ DoesNotAccessMemory,
		/* hexagon_M4_or_andn */ DoesNotAccessMemory,
		/* hexagon_M4_or_or */ DoesNotAccessMemory,
		/* hexagon_M4_or_xor */ DoesNotAccessMemory,
		/* hexagon_M4_xor_and */ DoesNotAccessMemory,
		/* hexagon_M4_xor_andn */ DoesNotAccessMemory,
		/* hexagon_M4_xor_or */ DoesNotAccessMemory,
		/* hexagon_M4_xor_xacc */ DoesNotAccessMemory,
		/* hexagon_S2_addasl_rrri */ DoesNotAccessMemory,
		/* hexagon_S2_asl_i_p */ DoesNotAccessMemory,
		/* hexagon_S2_asl_i_p_acc */ DoesNotAccessMemory,
		/* hexagon_S2_asl_i_p_and */ DoesNotAccessMemory,
		/* hexagon_S2_asl_i_p_nac */ DoesNotAccessMemory,
		/* hexagon_S2_asl_i_p_or */ DoesNotAccessMemory,
		/* hexagon_S2_asl_i_p_xacc */ DoesNotAccessMemory,
		/* hexagon_S2_asl_i_r */ DoesNotAccessMemory,
		/* hexagon_S2_asl_i_r_acc */ DoesNotAccessMemory,
		/* hexagon_S2_asl_i_r_and */ DoesNotAccessMemory,
		/* hexagon_S2_asl_i_r_nac */ DoesNotAccessMemory,
		/* hexagon_S2_asl_i_r_or */ DoesNotAccessMemory,
		/* hexagon_S2_asl_i_r_sat */ DoesNotAccessMemory,
		/* hexagon_S2_asl_i_r_xacc */ DoesNotAccessMemory,
		/* hexagon_S2_asl_i_vh */ DoesNotAccessMemory,
		/* hexagon_S2_asl_i_vw */ DoesNotAccessMemory,
		/* hexagon_S2_asl_r_p */ DoesNotAccessMemory,
		/* hexagon_S2_asl_r_p_acc */ DoesNotAccessMemory,
		/* hexagon_S2_asl_r_p_and */ DoesNotAccessMemory,
		/* hexagon_S2_asl_r_p_nac */ DoesNotAccessMemory,
		/* hexagon_S2_asl_r_p_or */ DoesNotAccessMemory,
		/* hexagon_S2_asl_r_r */ DoesNotAccessMemory,
		/* hexagon_S2_asl_r_r_acc */ DoesNotAccessMemory,
		/* hexagon_S2_asl_r_r_and */ DoesNotAccessMemory,
		/* hexagon_S2_asl_r_r_nac */ DoesNotAccessMemory,
		/* hexagon_S2_asl_r_r_or */ DoesNotAccessMemory,
		/* hexagon_S2_asl_r_r_sat */ DoesNotAccessMemory,
		/* hexagon_S2_asl_r_vh */ DoesNotAccessMemory,
		/* hexagon_S2_asl_r_vw */ DoesNotAccessMemory,
		/* hexagon_S2_asr_i_p */ DoesNotAccessMemory,
		/* hexagon_S2_asr_i_p_acc */ DoesNotAccessMemory,
		/* hexagon_S2_asr_i_p_and */ DoesNotAccessMemory,
		/* hexagon_S2_asr_i_p_nac */ DoesNotAccessMemory,
		/* hexagon_S2_asr_i_p_or */ DoesNotAccessMemory,
		/* hexagon_S2_asr_i_r */ DoesNotAccessMemory,
		/* hexagon_S2_asr_i_r_acc */ DoesNotAccessMemory,
		/* hexagon_S2_asr_i_r_and */ DoesNotAccessMemory,
		/* hexagon_S2_asr_i_r_nac */ DoesNotAccessMemory,
		/* hexagon_S2_asr_i_r_or */ DoesNotAccessMemory,
		/* hexagon_S2_asr_i_r_rnd */ DoesNotAccessMemory,
		/* hexagon_S2_asr_i_r_rnd_goodsyntax */ DoesNotAccessMemory,
		/* hexagon_S2_asr_i_svw_trun */ DoesNotAccessMemory,
		/* hexagon_S2_asr_i_vh */ DoesNotAccessMemory,
		/* hexagon_S2_asr_i_vw */ DoesNotAccessMemory,
		/* hexagon_S2_asr_r_p */ DoesNotAccessMemory,
		/* hexagon_S2_asr_r_p_acc */ DoesNotAccessMemory,
		/* hexagon_S2_asr_r_p_and */ DoesNotAccessMemory,
		/* hexagon_S2_asr_r_p_nac */ DoesNotAccessMemory,
		/* hexagon_S2_asr_r_p_or */ DoesNotAccessMemory,
		/* hexagon_S2_asr_r_r */ DoesNotAccessMemory,
		/* hexagon_S2_asr_r_r_acc */ DoesNotAccessMemory,
		/* hexagon_S2_asr_r_r_and */ DoesNotAccessMemory,
		/* hexagon_S2_asr_r_r_nac */ DoesNotAccessMemory,
		/* hexagon_S2_asr_r_r_or */ DoesNotAccessMemory,
		/* hexagon_S2_asr_r_r_sat */ DoesNotAccessMemory,
		/* hexagon_S2_asr_r_svw_trun */ DoesNotAccessMemory,
		/* hexagon_S2_asr_r_vh */ DoesNotAccessMemory,
		/* hexagon_S2_asr_r_vw */ DoesNotAccessMemory,
		/* hexagon_S2_brev */ DoesNotAccessMemory,
		/* hexagon_S2_cl0 */ DoesNotAccessMemory,
		/* hexagon_S2_cl0p */ DoesNotAccessMemory,
		/* hexagon_S2_cl1 */ DoesNotAccessMemory,
		/* hexagon_S2_cl1p */ DoesNotAccessMemory,
		/* hexagon_S2_clb */ DoesNotAccessMemory,
		/* hexagon_S2_clbnorm */ DoesNotAccessMemory,
		/* hexagon_S2_clbp */ DoesNotAccessMemory,
		/* hexagon_S2_clrbit_i */ DoesNotAccessMemory,
		/* hexagon_S2_clrbit_r */ DoesNotAccessMemory,
		/* hexagon_S2_ct0 */ DoesNotAccessMemory,
		/* hexagon_S2_ct1 */ DoesNotAccessMemory,
		/* hexagon_S2_deinterleave */ DoesNotAccessMemory,
		/* hexagon_S2_extractu */ DoesNotAccessMemory,
		/* hexagon_S2_extractu_rp */ DoesNotAccessMemory,
		/* hexagon_S2_extractup */ DoesNotAccessMemory,
		/* hexagon_S2_extractup_rp */ DoesNotAccessMemory,
		/* hexagon_S2_insert */ DoesNotAccessMemory,
		/* hexagon_S2_insert_rp */ DoesNotAccessMemory,
		/* hexagon_S2_insertp */ DoesNotAccessMemory,
		/* hexagon_S2_insertp_rp */ DoesNotAccessMemory,
		/* hexagon_S2_interleave */ DoesNotAccessMemory,
		/* hexagon_S2_lfsp */ DoesNotAccessMemory,
		/* hexagon_S2_lsl_r_p */ DoesNotAccessMemory,
		/* hexagon_S2_lsl_r_p_acc */ DoesNotAccessMemory,
		/* hexagon_S2_lsl_r_p_and */ DoesNotAccessMemory,
		/* hexagon_S2_lsl_r_p_nac */ DoesNotAccessMemory,
		/* hexagon_S2_lsl_r_p_or */ DoesNotAccessMemory,
		/* hexagon_S2_lsl_r_r */ DoesNotAccessMemory,
		/* hexagon_S2_lsl_r_r_acc */ DoesNotAccessMemory,
		/* hexagon_S2_lsl_r_r_and */ DoesNotAccessMemory,
		/* hexagon_S2_lsl_r_r_nac */ DoesNotAccessMemory,
		/* hexagon_S2_lsl_r_r_or */ DoesNotAccessMemory,
		/* hexagon_S2_lsl_r_vh */ DoesNotAccessMemory,
		/* hexagon_S2_lsl_r_vw */ DoesNotAccessMemory,
		/* hexagon_S2_lsr_i_p */ DoesNotAccessMemory,
		/* hexagon_S2_lsr_i_p_acc */ DoesNotAccessMemory,
		/* hexagon_S2_lsr_i_p_and */ DoesNotAccessMemory,
		/* hexagon_S2_lsr_i_p_nac */ DoesNotAccessMemory,
		/* hexagon_S2_lsr_i_p_or */ DoesNotAccessMemory,
		/* hexagon_S2_lsr_i_p_xacc */ DoesNotAccessMemory,
		/* hexagon_S2_lsr_i_r */ DoesNotAccessMemory,
		/* hexagon_S2_lsr_i_r_acc */ DoesNotAccessMemory,
		/* hexagon_S2_lsr_i_r_and */ DoesNotAccessMemory,
		/* hexagon_S2_lsr_i_r_nac */ DoesNotAccessMemory,
		/* hexagon_S2_lsr_i_r_or */ DoesNotAccessMemory,
		/* hexagon_S2_lsr_i_r_xacc */ DoesNotAccessMemory,
		/* hexagon_S2_lsr_i_vh */ DoesNotAccessMemory,
		/* hexagon_S2_lsr_i_vw */ DoesNotAccessMemory,
		/* hexagon_S2_lsr_r_p */ DoesNotAccessMemory,
		/* hexagon_S2_lsr_r_p_acc */ DoesNotAccessMemory,
		/* hexagon_S2_lsr_r_p_and */ DoesNotAccessMemory,
		/* hexagon_S2_lsr_r_p_nac */ DoesNotAccessMemory,
		/* hexagon_S2_lsr_r_p_or */ DoesNotAccessMemory,
		/* hexagon_S2_lsr_r_r */ DoesNotAccessMemory,
		/* hexagon_S2_lsr_r_r_acc */ DoesNotAccessMemory,
		/* hexagon_S2_lsr_r_r_and */ DoesNotAccessMemory,
		/* hexagon_S2_lsr_r_r_nac */ DoesNotAccessMemory,
		/* hexagon_S2_lsr_r_r_or */ DoesNotAccessMemory,
		/* hexagon_S2_lsr_r_vh */ DoesNotAccessMemory,
		/* hexagon_S2_lsr_r_vw */ DoesNotAccessMemory,
		/* hexagon_S2_packhl */ DoesNotAccessMemory,
		/* hexagon_S2_parityp */ DoesNotAccessMemory,
		/* hexagon_S2_setbit_i */ DoesNotAccessMemory,
		/* hexagon_S2_setbit_r */ DoesNotAccessMemory,
		/* hexagon_S2_shuffeb */ DoesNotAccessMemory,
		/* hexagon_S2_shuffeh */ DoesNotAccessMemory,
		/* hexagon_S2_shuffob */ DoesNotAccessMemory,
		/* hexagon_S2_shuffoh */ DoesNotAccessMemory,
		/* hexagon_S2_svsathb */ DoesNotAccessMemory,
		/* hexagon_S2_svsathub */ DoesNotAccessMemory,
		/* hexagon_S2_tableidxb_goodsyntax */ DoesNotAccessMemory,
		/* hexagon_S2_tableidxd_goodsyntax */ DoesNotAccessMemory,
		/* hexagon_S2_tableidxh_goodsyntax */ DoesNotAccessMemory,
		/* hexagon_S2_tableidxw_goodsyntax */ DoesNotAccessMemory,
		/* hexagon_S2_togglebit_i */ DoesNotAccessMemory,
		/* hexagon_S2_togglebit_r */ DoesNotAccessMemory,
		/* hexagon_S2_tstbit_i */ DoesNotAccessMemory,
		/* hexagon_S2_tstbit_r */ DoesNotAccessMemory,
		/* hexagon_S2_valignib */ DoesNotAccessMemory,
		/* hexagon_S2_valignrb */ DoesNotAccessMemory,
		/* hexagon_S2_vcrotate */ DoesNotAccessMemory,
		/* hexagon_S2_vrndpackwh */ DoesNotAccessMemory,
		/* hexagon_S2_vrndpackwhs */ DoesNotAccessMemory,
		/* hexagon_S2_vsathb */ DoesNotAccessMemory,
		/* hexagon_S2_vsathb_nopack */ DoesNotAccessMemory,
		/* hexagon_S2_vsathub */ DoesNotAccessMemory,
		/* hexagon_S2_vsathub_nopack */ DoesNotAccessMemory,
		/* hexagon_S2_vsatwh */ DoesNotAccessMemory,
		/* hexagon_S2_vsatwh_nopack */ DoesNotAccessMemory,
		/* hexagon_S2_vsatwuh */ DoesNotAccessMemory,
		/* hexagon_S2_vsatwuh_nopack */ DoesNotAccessMemory,
		/* hexagon_S2_vsplatrb */ DoesNotAccessMemory,
		/* hexagon_S2_vsplatrh */ DoesNotAccessMemory,
		/* hexagon_S2_vspliceib */ DoesNotAccessMemory,
		/* hexagon_S2_vsplicerb */ DoesNotAccessMemory,
		/* hexagon_S2_vsxtbh */ DoesNotAccessMemory,
		/* hexagon_S2_vsxthw */ DoesNotAccessMemory,
		/* hexagon_S2_vtrunehb */ DoesNotAccessMemory,
		/* hexagon_S2_vtrunewh */ DoesNotAccessMemory,
		/* hexagon_S2_vtrunohb */ DoesNotAccessMemory,
		/* hexagon_S2_vtrunowh */ DoesNotAccessMemory,
		/* hexagon_S2_vzxtbh */ DoesNotAccessMemory,
		/* hexagon_S2_vzxthw */ DoesNotAccessMemory,
		/* hexagon_S4_addaddi */ DoesNotAccessMemory,
		/* hexagon_S4_andnp */ DoesNotAccessMemory,
		/* hexagon_S4_or_andi */ DoesNotAccessMemory,
		/* hexagon_S4_or_andix */ DoesNotAccessMemory,
		/* hexagon_S4_or_ori */ DoesNotAccessMemory,
		/* hexagon_S4_ornp */ DoesNotAccessMemory,
		/* hexagon_S4_subaddi */ DoesNotAccessMemory,
		/* hexagon_SI_to_SXTHI_asrh */ DoesNotAccessMemory,
		/* init_trampoline */ OnlyAccessesArgumentPointees,
		/* invariant_end */ OnlyAccessesArgumentPointees,
		/* invariant_start */ OnlyAccessesArgumentPointees,
		/* lifetime_end */ OnlyAccessesArgumentPointees,
		/* lifetime_start */ OnlyAccessesArgumentPointees,
		/* log */ OnlyReadsMemory,
		/* log10 */ OnlyReadsMemory,
		/* log2 */ OnlyReadsMemory,
		/* longjmp */ UnknownModRefBehavior,
		/* memcpy */ OnlyAccessesArgumentPointees,
		/* memmove */ OnlyAccessesArgumentPointees,
		/* memset */ OnlyAccessesArgumentPointees,
		/* objectsize */ DoesNotAccessMemory,
		/* pcmarker */ UnknownModRefBehavior,
		/* pow */ OnlyReadsMemory,
		/* powi */ OnlyReadsMemory,
		/* ppc_altivec_dss */ UnknownModRefBehavior,
		/* ppc_altivec_dssall */ UnknownModRefBehavior,
		/* ppc_altivec_dst */ UnknownModRefBehavior,
		/* ppc_altivec_dstst */ UnknownModRefBehavior,
		/* ppc_altivec_dststt */ UnknownModRefBehavior,
		/* ppc_altivec_dstt */ UnknownModRefBehavior,
		/* ppc_altivec_lvebx */ OnlyReadsMemory,
		/* ppc_altivec_lvehx */ OnlyReadsMemory,
		/* ppc_altivec_lvewx */ OnlyReadsMemory,
		/* ppc_altivec_lvsl */ DoesNotAccessMemory,
		/* ppc_altivec_lvsr */ DoesNotAccessMemory,
		/* ppc_altivec_lvx */ OnlyReadsMemory,
		/* ppc_altivec_lvxl */ OnlyReadsMemory,
		/* ppc_altivec_mfvscr */ OnlyReadsMemory,
		/* ppc_altivec_mtvscr */ UnknownModRefBehavior,
		/* ppc_altivec_stvebx */ UnknownModRefBehavior,
		/* ppc_altivec_stvehx */ UnknownModRefBehavior,
		/* ppc_altivec_stvewx */ UnknownModRefBehavior,
		/* ppc_altivec_stvx */ UnknownModRefBehavior,
		/* ppc_altivec_stvxl */ UnknownModRefBehavior,
		/* ppc_altivec_vaddcuw */ DoesNotAccessMemory,
		/* ppc_altivec_vaddsbs */ DoesNotAccessMemory,
		/* ppc_altivec_vaddshs */ DoesNotAccessMemory,
		/* ppc_altivec_vaddsws */ DoesNotAccessMemory,
		/* ppc_altivec_vaddubs */ DoesNotAccessMemory,
		/* ppc_altivec_vadduhs */ DoesNotAccessMemory,
		/* ppc_altivec_vadduws */ DoesNotAccessMemory,
		/* ppc_altivec_vavgsb */ DoesNotAccessMemory,
		/* ppc_altivec_vavgsh */ DoesNotAccessMemory,
		/* ppc_altivec_vavgsw */ DoesNotAccessMemory,
		/* ppc_altivec_vavgub */ DoesNotAccessMemory,
		/* ppc_altivec_vavguh */ DoesNotAccessMemory,
		/* ppc_altivec_vavguw */ DoesNotAccessMemory,
		/* ppc_altivec_vcfsx */ DoesNotAccessMemory,
		/* ppc_altivec_vcfux */ DoesNotAccessMemory,
		/* ppc_altivec_vcmpbfp */ DoesNotAccessMemory,
		/* ppc_altivec_vcmpbfp_p */ DoesNotAccessMemory,
		/* ppc_altivec_vcmpeqfp */ DoesNotAccessMemory,
		/* ppc_altivec_vcmpeqfp_p */ DoesNotAccessMemory,
		/* ppc_altivec_vcmpequb */ DoesNotAccessMemory,
		/* ppc_altivec_vcmpequb_p */ DoesNotAccessMemory,
		/* ppc_altivec_vcmpequh */ DoesNotAccessMemory,
		/* ppc_altivec_vcmpequh_p */ DoesNotAccessMemory,
		/* ppc_altivec_vcmpequw */ DoesNotAccessMemory,
		/* ppc_altivec_vcmpequw_p */ DoesNotAccessMemory,
		/* ppc_altivec_vcmpgefp */ DoesNotAccessMemory,
		/* ppc_altivec_vcmpgefp_p */ DoesNotAccessMemory,
		/* ppc_altivec_vcmpgtfp */ DoesNotAccessMemory,
		/* ppc_altivec_vcmpgtfp_p */ DoesNotAccessMemory,
		/* ppc_altivec_vcmpgtsb */ DoesNotAccessMemory,
		/* ppc_altivec_vcmpgtsb_p */ DoesNotAccessMemory,
		/* ppc_altivec_vcmpgtsh */ DoesNotAccessMemory,
		/* ppc_altivec_vcmpgtsh_p */ DoesNotAccessMemory,
		/* ppc_altivec_vcmpgtsw */ DoesNotAccessMemory,
		/* ppc_altivec_vcmpgtsw_p */ DoesNotAccessMemory,
		/* ppc_altivec_vcmpgtub */ DoesNotAccessMemory,
		/* ppc_altivec_vcmpgtub_p */ DoesNotAccessMemory,
		/* ppc_altivec_vcmpgtuh */ DoesNotAccessMemory,
		/* ppc_altivec_vcmpgtuh_p */ DoesNotAccessMemory,
		/* ppc_altivec_vcmpgtuw */ DoesNotAccessMemory,
		/* ppc_altivec_vcmpgtuw_p */ DoesNotAccessMemory,
		/* ppc_altivec_vctsxs */ DoesNotAccessMemory,
		/* ppc_altivec_vctuxs */ DoesNotAccessMemory,
		/* ppc_altivec_vexptefp */ DoesNotAccessMemory,
		/* ppc_altivec_vlogefp */ DoesNotAccessMemory,
		/* ppc_altivec_vmaddfp */ DoesNotAccessMemory,
		/* ppc_altivec_vmaxfp */ DoesNotAccessMemory,
		/* ppc_altivec_vmaxsb */ DoesNotAccessMemory,
		/* ppc_altivec_vmaxsh */ DoesNotAccessMemory,
		/* ppc_altivec_vmaxsw */ DoesNotAccessMemory,
		/* ppc_altivec_vmaxub */ DoesNotAccessMemory,
		/* ppc_altivec_vmaxuh */ DoesNotAccessMemory,
		/* ppc_altivec_vmaxuw */ DoesNotAccessMemory,
		/* ppc_altivec_vmhaddshs */ DoesNotAccessMemory,
		/* ppc_altivec_vmhraddshs */ DoesNotAccessMemory,
		/* ppc_altivec_vminfp */ DoesNotAccessMemory,
		/* ppc_altivec_vminsb */ DoesNotAccessMemory,
		/* ppc_altivec_vminsh */ DoesNotAccessMemory,
		/* ppc_altivec_vminsw */ DoesNotAccessMemory,
		/* ppc_altivec_vminub */ DoesNotAccessMemory,
		/* ppc_altivec_vminuh */ DoesNotAccessMemory,
		/* ppc_altivec_vminuw */ DoesNotAccessMemory,
		/* ppc_altivec_vmladduhm */ DoesNotAccessMemory,
		/* ppc_altivec_vmsummbm */ DoesNotAccessMemory,
		/* ppc_altivec_vmsumshm */ DoesNotAccessMemory,
		/* ppc_altivec_vmsumshs */ DoesNotAccessMemory,
		/* ppc_altivec_vmsumubm */ DoesNotAccessMemory,
		/* ppc_altivec_vmsumuhm */ DoesNotAccessMemory,
		/* ppc_altivec_vmsumuhs */ DoesNotAccessMemory,
		/* ppc_altivec_vmulesb */ DoesNotAccessMemory,
		/* ppc_altivec_vmulesh */ DoesNotAccessMemory,
		/* ppc_altivec_vmuleub */ DoesNotAccessMemory,
		/* ppc_altivec_vmuleuh */ DoesNotAccessMemory,
		/* ppc_altivec_vmulosb */ DoesNotAccessMemory,
		/* ppc_altivec_vmulosh */ DoesNotAccessMemory,
		/* ppc_altivec_vmuloub */ DoesNotAccessMemory,
		/* ppc_altivec_vmulouh */ DoesNotAccessMemory,
		/* ppc_altivec_vnmsubfp */ DoesNotAccessMemory,
		/* ppc_altivec_vperm */ DoesNotAccessMemory,
		/* ppc_altivec_vpkpx */ DoesNotAccessMemory,
		/* ppc_altivec_vpkshss */ DoesNotAccessMemory,
		/* ppc_altivec_vpkshus */ DoesNotAccessMemory,
		/* ppc_altivec_vpkswss */ DoesNotAccessMemory,
		/* ppc_altivec_vpkswus */ DoesNotAccessMemory,
		/* ppc_altivec_vpkuhus */ DoesNotAccessMemory,
		/* ppc_altivec_vpkuwus */ DoesNotAccessMemory,
		/* ppc_altivec_vrefp */ DoesNotAccessMemory,
		/* ppc_altivec_vrfim */ DoesNotAccessMemory,
		/* ppc_altivec_vrfin */ DoesNotAccessMemory,
		/* ppc_altivec_vrfip */ DoesNotAccessMemory,
		/* ppc_altivec_vrfiz */ DoesNotAccessMemory,
		/* ppc_altivec_vrlb */ DoesNotAccessMemory,
		/* ppc_altivec_vrlh */ DoesNotAccessMemory,
		/* ppc_altivec_vrlw */ DoesNotAccessMemory,
		/* ppc_altivec_vrsqrtefp */ DoesNotAccessMemory,
		/* ppc_altivec_vsel */ DoesNotAccessMemory,
		/* ppc_altivec_vsl */ DoesNotAccessMemory,
		/* ppc_altivec_vslb */ DoesNotAccessMemory,
		/* ppc_altivec_vslh */ DoesNotAccessMemory,
		/* ppc_altivec_vslo */ DoesNotAccessMemory,
		/* ppc_altivec_vslw */ DoesNotAccessMemory,
		/* ppc_altivec_vsr */ DoesNotAccessMemory,
		/* ppc_altivec_vsrab */ DoesNotAccessMemory,
		/* ppc_altivec_vsrah */ DoesNotAccessMemory,
		/* ppc_altivec_vsraw */ DoesNotAccessMemory,
		/* ppc_altivec_vsrb */ DoesNotAccessMemory,
		/* ppc_altivec_vsrh */ DoesNotAccessMemory,
		/* ppc_altivec_vsro */ DoesNotAccessMemory,
		/* ppc_altivec_vsrw */ DoesNotAccessMemory,
		/* ppc_altivec_vsubcuw */ DoesNotAccessMemory,
		/* ppc_altivec_vsubsbs */ DoesNotAccessMemory,
		/* ppc_altivec_vsubshs */ DoesNotAccessMemory,
		/* ppc_altivec_vsubsws */ DoesNotAccessMemory,
		/* ppc_altivec_vsububs */ DoesNotAccessMemory,
		/* ppc_altivec_vsubuhs */ DoesNotAccessMemory,
		/* ppc_altivec_vsubuws */ DoesNotAccessMemory,
		/* ppc_altivec_vsum2sws */ DoesNotAccessMemory,
		/* ppc_altivec_vsum4sbs */ DoesNotAccessMemory,
		/* ppc_altivec_vsum4shs */ DoesNotAccessMemory,
		/* ppc_altivec_vsum4ubs */ DoesNotAccessMemory,
		/* ppc_altivec_vsumsws */ DoesNotAccessMemory,
		/* ppc_altivec_vupkhpx */ DoesNotAccessMemory,
		/* ppc_altivec_vupkhsb */ DoesNotAccessMemory,
		/* ppc_altivec_vupkhsh */ DoesNotAccessMemory,
		/* ppc_altivec_vupklpx */ DoesNotAccessMemory,
		/* ppc_altivec_vupklsb */ DoesNotAccessMemory,
		/* ppc_altivec_vupklsh */ DoesNotAccessMemory,
		/* ppc_dcba */ UnknownModRefBehavior,
		/* ppc_dcbf */ UnknownModRefBehavior,
		/* ppc_dcbi */ UnknownModRefBehavior,
		/* ppc_dcbst */ UnknownModRefBehavior,
		/* ppc_dcbt */ UnknownModRefBehavior,
		/* ppc_dcbtst */ UnknownModRefBehavior,
		/* ppc_dcbz */ UnknownModRefBehavior,
		/* ppc_dcbzl */ UnknownModRefBehavior,
		/* ppc_sync */ UnknownModRefBehavior,
		/* prefetch */ OnlyAccessesArgumentPointees,
		/* ptr_annotation */ UnknownModRefBehavior,
		/* ptx_bar_sync */ UnknownModRefBehavior,
		/* ptx_read_clock */ DoesNotAccessMemory,
		/* ptx_read_clock64 */ DoesNotAccessMemory,
		/* ptx_read_ctaid_w */ DoesNotAccessMemory,
		/* ptx_read_ctaid_x */ DoesNotAccessMemory,
		/* ptx_read_ctaid_y */ DoesNotAccessMemory,
		/* ptx_read_ctaid_z */ DoesNotAccessMemory,
		/* ptx_read_gridid */ DoesNotAccessMemory,
		/* ptx_read_laneid */ DoesNotAccessMemory,
		/* ptx_read_lanemask_eq */ DoesNotAccessMemory,
		/* ptx_read_lanemask_ge */ DoesNotAccessMemory,
		/* ptx_read_lanemask_gt */ DoesNotAccessMemory,
		/* ptx_read_lanemask_le */ DoesNotAccessMemory,
		/* ptx_read_lanemask_lt */ DoesNotAccessMemory,
		/* ptx_read_nctaid_w */ DoesNotAccessMemory,
		/* ptx_read_nctaid_x */ DoesNotAccessMemory,
		/* ptx_read_nctaid_y */ DoesNotAccessMemory,
		/* ptx_read_nctaid_z */ DoesNotAccessMemory,
		/* ptx_read_nsmid */ DoesNotAccessMemory,
		/* ptx_read_ntid_w */ DoesNotAccessMemory,
		/* ptx_read_ntid_x */ DoesNotAccessMemory,
		/* ptx_read_ntid_y */ DoesNotAccessMemory,
		/* ptx_read_ntid_z */ DoesNotAccessMemory,
		/* ptx_read_nwarpid */ DoesNotAccessMemory,
		/* ptx_read_pm0 */ DoesNotAccessMemory,
		/* ptx_read_pm1 */ DoesNotAccessMemory,
		/* ptx_read_pm2 */ DoesNotAccessMemory,
		/* ptx_read_pm3 */ DoesNotAccessMemory,
		/* ptx_read_smid */ DoesNotAccessMemory,
		/* ptx_read_tid_w */ DoesNotAccessMemory,
		/* ptx_read_tid_x */ DoesNotAccessMemory,
		/* ptx_read_tid_y */ DoesNotAccessMemory,
		/* ptx_read_tid_z */ DoesNotAccessMemory,
		/* ptx_read_warpid */ DoesNotAccessMemory,
		/* readcyclecounter */ UnknownModRefBehavior,
		/* returnaddress */ DoesNotAccessMemory,
		/* sadd_with_overflow */ DoesNotAccessMemory,
		/* setjmp */ UnknownModRefBehavior,
		/* siglongjmp */ UnknownModRefBehavior,
		/* sigsetjmp */ UnknownModRefBehavior,
		/* sin */ OnlyReadsMemory,
		/* smul_with_overflow */ DoesNotAccessMemory,
		/* spu_si_a */ DoesNotAccessMemory,
		/* spu_si_addx */ DoesNotAccessMemory,
		/* spu_si_ah */ DoesNotAccessMemory,
		/* spu_si_ahi */ DoesNotAccessMemory,
		/* spu_si_ai */ DoesNotAccessMemory,
		/* spu_si_and */ DoesNotAccessMemory,
		/* spu_si_andbi */ DoesNotAccessMemory,
		/* spu_si_andc */ DoesNotAccessMemory,
		/* spu_si_andhi */ DoesNotAccessMemory,
		/* spu_si_andi */ DoesNotAccessMemory,
		/* spu_si_bg */ DoesNotAccessMemory,
		/* spu_si_bgx */ DoesNotAccessMemory,
		/* spu_si_ceq */ DoesNotAccessMemory,
		/* spu_si_ceqb */ DoesNotAccessMemory,
		/* spu_si_ceqbi */ DoesNotAccessMemory,
		/* spu_si_ceqh */ DoesNotAccessMemory,
		/* spu_si_ceqhi */ DoesNotAccessMemory,
		/* spu_si_ceqi */ DoesNotAccessMemory,
		/* spu_si_cg */ DoesNotAccessMemory,
		/* spu_si_cgt */ DoesNotAccessMemory,
		/* spu_si_cgtb */ DoesNotAccessMemory,
		/* spu_si_cgtbi */ DoesNotAccessMemory,
		/* spu_si_cgth */ DoesNotAccessMemory,
		/* spu_si_cgthi */ DoesNotAccessMemory,
		/* spu_si_cgti */ DoesNotAccessMemory,
		/* spu_si_cgx */ DoesNotAccessMemory,
		/* spu_si_clgt */ DoesNotAccessMemory,
		/* spu_si_clgtb */ DoesNotAccessMemory,
		/* spu_si_clgtbi */ DoesNotAccessMemory,
		/* spu_si_clgth */ DoesNotAccessMemory,
		/* spu_si_clgthi */ DoesNotAccessMemory,
		/* spu_si_clgti */ DoesNotAccessMemory,
		/* spu_si_dfa */ DoesNotAccessMemory,
		/* spu_si_dfm */ DoesNotAccessMemory,
		/* spu_si_dfma */ DoesNotAccessMemory,
		/* spu_si_dfms */ DoesNotAccessMemory,
		/* spu_si_dfnma */ DoesNotAccessMemory,
		/* spu_si_dfnms */ DoesNotAccessMemory,
		/* spu_si_dfs */ DoesNotAccessMemory,
		/* spu_si_fa */ DoesNotAccessMemory,
		/* spu_si_fceq */ DoesNotAccessMemory,
		/* spu_si_fcgt */ DoesNotAccessMemory,
		/* spu_si_fcmeq */ DoesNotAccessMemory,
		/* spu_si_fcmgt */ DoesNotAccessMemory,
		/* spu_si_fm */ DoesNotAccessMemory,
		/* spu_si_fma */ DoesNotAccessMemory,
		/* spu_si_fms */ DoesNotAccessMemory,
		/* spu_si_fnms */ DoesNotAccessMemory,
		/* spu_si_fs */ DoesNotAccessMemory,
		/* spu_si_fsmbi */ DoesNotAccessMemory,
		/* spu_si_mpy */ DoesNotAccessMemory,
		/* spu_si_mpya */ DoesNotAccessMemory,
		/* spu_si_mpyh */ DoesNotAccessMemory,
		/* spu_si_mpyhh */ DoesNotAccessMemory,
		/* spu_si_mpyhha */ DoesNotAccessMemory,
		/* spu_si_mpyhhau */ DoesNotAccessMemory,
		/* spu_si_mpyhhu */ DoesNotAccessMemory,
		/* spu_si_mpyi */ DoesNotAccessMemory,
		/* spu_si_mpys */ DoesNotAccessMemory,
		/* spu_si_mpyu */ DoesNotAccessMemory,
		/* spu_si_mpyui */ DoesNotAccessMemory,
		/* spu_si_nand */ DoesNotAccessMemory,
		/* spu_si_nor */ DoesNotAccessMemory,
		/* spu_si_or */ DoesNotAccessMemory,
		/* spu_si_orbi */ DoesNotAccessMemory,
		/* spu_si_orc */ DoesNotAccessMemory,
		/* spu_si_orhi */ DoesNotAccessMemory,
		/* spu_si_ori */ DoesNotAccessMemory,
		/* spu_si_sf */ DoesNotAccessMemory,
		/* spu_si_sfh */ DoesNotAccessMemory,
		/* spu_si_sfhi */ DoesNotAccessMemory,
		/* spu_si_sfi */ DoesNotAccessMemory,
		/* spu_si_sfx */ DoesNotAccessMemory,
		/* spu_si_shli */ DoesNotAccessMemory,
		/* spu_si_shlqbi */ DoesNotAccessMemory,
		/* spu_si_shlqbii */ DoesNotAccessMemory,
		/* spu_si_shlqby */ DoesNotAccessMemory,
		/* spu_si_shlqbyi */ DoesNotAccessMemory,
		/* spu_si_xor */ DoesNotAccessMemory,
		/* spu_si_xorbi */ DoesNotAccessMemory,
		/* spu_si_xorhi */ DoesNotAccessMemory,
		/* spu_si_xori */ DoesNotAccessMemory,
		/* sqrt */ OnlyReadsMemory,
		/* ssub_with_overflow */ DoesNotAccessMemory,
		/* stackprotector */ UnknownModRefBehavior,
		/* stackrestore */ UnknownModRefBehavior,
		/* stacksave */ UnknownModRefBehavior,
		/* trap */ UnknownModRefBehavior,
		/* uadd_with_overflow */ DoesNotAccessMemory,
		/* umul_with_overflow */ DoesNotAccessMemory,
		/* usub_with_overflow */ DoesNotAccessMemory,
		/* vacopy */ UnknownModRefBehavior,
		/* vaend */ UnknownModRefBehavior,
		/* var_annotation */ UnknownModRefBehavior,
		/* vastart */ UnknownModRefBehavior,
		/* x86_3dnow_pavgusb */ DoesNotAccessMemory,
		/* x86_3dnow_pf2id */ DoesNotAccessMemory,
		/* x86_3dnow_pfacc */ DoesNotAccessMemory,
		/* x86_3dnow_pfadd */ DoesNotAccessMemory,
		/* x86_3dnow_pfcmpeq */ DoesNotAccessMemory,
		/* x86_3dnow_pfcmpge */ DoesNotAccessMemory,
		/* x86_3dnow_pfcmpgt */ DoesNotAccessMemory,
		/* x86_3dnow_pfmax */ DoesNotAccessMemory,
		/* x86_3dnow_pfmin */ DoesNotAccessMemory,
		/* x86_3dnow_pfmul */ DoesNotAccessMemory,
		/* x86_3dnow_pfrcp */ DoesNotAccessMemory,
		/* x86_3dnow_pfrcpit1 */ DoesNotAccessMemory,
		/* x86_3dnow_pfrcpit2 */ DoesNotAccessMemory,
		/* x86_3dnow_pfrsqit1 */ DoesNotAccessMemory,
		/* x86_3dnow_pfrsqrt */ DoesNotAccessMemory,
		/* x86_3dnow_pfsub */ DoesNotAccessMemory,
		/* x86_3dnow_pfsubr */ DoesNotAccessMemory,
		/* x86_3dnow_pi2fd */ DoesNotAccessMemory,
		/* x86_3dnow_pmulhrw */ DoesNotAccessMemory,
		/* x86_3dnowa_pf2iw */ DoesNotAccessMemory,
		/* x86_3dnowa_pfnacc */ DoesNotAccessMemory,
		/* x86_3dnowa_pfpnacc */ DoesNotAccessMemory,
		/* x86_3dnowa_pi2fw */ DoesNotAccessMemory,
		/* x86_3dnowa_pswapd */ DoesNotAccessMemory,
		/* x86_aesni_aesdec */ DoesNotAccessMemory,
		/* x86_aesni_aesdeclast */ DoesNotAccessMemory,
		/* x86_aesni_aesenc */ DoesNotAccessMemory,
		/* x86_aesni_aesenclast */ DoesNotAccessMemory,
		/* x86_aesni_aesimc */ DoesNotAccessMemory,
		/* x86_aesni_aeskeygenassist */ DoesNotAccessMemory,
		/* x86_avx2_maskload_d */ OnlyReadsMemory,
		/* x86_avx2_maskload_d_256 */ OnlyReadsMemory,
		/* x86_avx2_maskload_q */ OnlyReadsMemory,
		/* x86_avx2_maskload_q_256 */ OnlyReadsMemory,
		/* x86_avx2_maskstore_d */ UnknownModRefBehavior,
		/* x86_avx2_maskstore_d_256 */ UnknownModRefBehavior,
		/* x86_avx2_maskstore_q */ UnknownModRefBehavior,
		/* x86_avx2_maskstore_q_256 */ UnknownModRefBehavior,
		/* x86_avx2_movntdqa */ OnlyReadsMemory,
		/* x86_avx2_mpsadbw */ DoesNotAccessMemory,
		/* x86_avx2_pabs_b */ DoesNotAccessMemory,
		/* x86_avx2_pabs_d */ DoesNotAccessMemory,
		/* x86_avx2_pabs_w */ DoesNotAccessMemory,
		/* x86_avx2_packssdw */ DoesNotAccessMemory,
		/* x86_avx2_packsswb */ DoesNotAccessMemory,
		/* x86_avx2_packusdw */ DoesNotAccessMemory,
		/* x86_avx2_packuswb */ DoesNotAccessMemory,
		/* x86_avx2_padds_b */ DoesNotAccessMemory,
		/* x86_avx2_padds_w */ DoesNotAccessMemory,
		/* x86_avx2_paddus_b */ DoesNotAccessMemory,
		/* x86_avx2_paddus_w */ DoesNotAccessMemory,
		/* x86_avx2_pavg_b */ DoesNotAccessMemory,
		/* x86_avx2_pavg_w */ DoesNotAccessMemory,
		/* x86_avx2_pblendd_128 */ DoesNotAccessMemory,
		/* x86_avx2_pblendd_256 */ DoesNotAccessMemory,
		/* x86_avx2_pblendvb */ DoesNotAccessMemory,
		/* x86_avx2_pblendw */ DoesNotAccessMemory,
		/* x86_avx2_pbroadcastb_128 */ DoesNotAccessMemory,
		/* x86_avx2_pbroadcastb_256 */ DoesNotAccessMemory,
		/* x86_avx2_pbroadcastd_128 */ DoesNotAccessMemory,
		/* x86_avx2_pbroadcastd_256 */ DoesNotAccessMemory,
		/* x86_avx2_pbroadcastq_128 */ DoesNotAccessMemory,
		/* x86_avx2_pbroadcastq_256 */ DoesNotAccessMemory,
		/* x86_avx2_pbroadcastw_128 */ DoesNotAccessMemory,
		/* x86_avx2_pbroadcastw_256 */ DoesNotAccessMemory,
		/* x86_avx2_permd */ DoesNotAccessMemory,
		/* x86_avx2_permps */ DoesNotAccessMemory,
		/* x86_avx2_phadd_d */ DoesNotAccessMemory,
		/* x86_avx2_phadd_sw */ DoesNotAccessMemory,
		/* x86_avx2_phadd_w */ DoesNotAccessMemory,
		/* x86_avx2_phsub_d */ DoesNotAccessMemory,
		/* x86_avx2_phsub_sw */ DoesNotAccessMemory,
		/* x86_avx2_phsub_w */ DoesNotAccessMemory,
		/* x86_avx2_pmadd_ub_sw */ DoesNotAccessMemory,
		/* x86_avx2_pmadd_wd */ DoesNotAccessMemory,
		/* x86_avx2_pmaxs_b */ DoesNotAccessMemory,
		/* x86_avx2_pmaxs_d */ DoesNotAccessMemory,
		/* x86_avx2_pmaxs_w */ DoesNotAccessMemory,
		/* x86_avx2_pmaxu_b */ DoesNotAccessMemory,
		/* x86_avx2_pmaxu_d */ DoesNotAccessMemory,
		/* x86_avx2_pmaxu_w */ DoesNotAccessMemory,
		/* x86_avx2_pmins_b */ DoesNotAccessMemory,
		/* x86_avx2_pmins_d */ DoesNotAccessMemory,
		/* x86_avx2_pmins_w */ DoesNotAccessMemory,
		/* x86_avx2_pminu_b */ DoesNotAccessMemory,
		/* x86_avx2_pminu_d */ DoesNotAccessMemory,
		/* x86_avx2_pminu_w */ DoesNotAccessMemory,
		/* x86_avx2_pmovmskb */ DoesNotAccessMemory,
		/* x86_avx2_pmovsxbd */ DoesNotAccessMemory,
		/* x86_avx2_pmovsxbq */ DoesNotAccessMemory,
		/* x86_avx2_pmovsxbw */ DoesNotAccessMemory,
		/* x86_avx2_pmovsxdq */ DoesNotAccessMemory,
		/* x86_avx2_pmovsxwd */ DoesNotAccessMemory,
		/* x86_avx2_pmovsxwq */ DoesNotAccessMemory,
		/* x86_avx2_pmovzxbd */ DoesNotAccessMemory,
		/* x86_avx2_pmovzxbq */ DoesNotAccessMemory,
		/* x86_avx2_pmovzxbw */ DoesNotAccessMemory,
		/* x86_avx2_pmovzxdq */ DoesNotAccessMemory,
		/* x86_avx2_pmovzxwd */ DoesNotAccessMemory,
		/* x86_avx2_pmovzxwq */ DoesNotAccessMemory,
		/* x86_avx2_pmul_dq */ DoesNotAccessMemory,
		/* x86_avx2_pmul_hr_sw */ DoesNotAccessMemory,
		/* x86_avx2_pmulh_w */ DoesNotAccessMemory,
		/* x86_avx2_pmulhu_w */ DoesNotAccessMemory,
		/* x86_avx2_pmulu_dq */ DoesNotAccessMemory,
		/* x86_avx2_psad_bw */ DoesNotAccessMemory,
		/* x86_avx2_pshuf_b */ DoesNotAccessMemory,
		/* x86_avx2_psign_b */ DoesNotAccessMemory,
		/* x86_avx2_psign_d */ DoesNotAccessMemory,
		/* x86_avx2_psign_w */ DoesNotAccessMemory,
		/* x86_avx2_psll_d */ DoesNotAccessMemory,
		/* x86_avx2_psll_dq */ DoesNotAccessMemory,
		/* x86_avx2_psll_dq_bs */ DoesNotAccessMemory,
		/* x86_avx2_psll_q */ DoesNotAccessMemory,
		/* x86_avx2_psll_w */ DoesNotAccessMemory,
		/* x86_avx2_pslli_d */ DoesNotAccessMemory,
		/* x86_avx2_pslli_q */ DoesNotAccessMemory,
		/* x86_avx2_pslli_w */ DoesNotAccessMemory,
		/* x86_avx2_psllv_d */ DoesNotAccessMemory,
		/* x86_avx2_psllv_d_256 */ DoesNotAccessMemory,
		/* x86_avx2_psllv_q */ DoesNotAccessMemory,
		/* x86_avx2_psllv_q_256 */ DoesNotAccessMemory,
		/* x86_avx2_psra_d */ DoesNotAccessMemory,
		/* x86_avx2_psra_w */ DoesNotAccessMemory,
		/* x86_avx2_psrai_d */ DoesNotAccessMemory,
		/* x86_avx2_psrai_w */ DoesNotAccessMemory,
		/* x86_avx2_psrav_d */ DoesNotAccessMemory,
		/* x86_avx2_psrav_d_256 */ DoesNotAccessMemory,
		/* x86_avx2_psrl_d */ DoesNotAccessMemory,
		/* x86_avx2_psrl_dq */ DoesNotAccessMemory,
		/* x86_avx2_psrl_dq_bs */ DoesNotAccessMemory,
		/* x86_avx2_psrl_q */ DoesNotAccessMemory,
		/* x86_avx2_psrl_w */ DoesNotAccessMemory,
		/* x86_avx2_psrli_d */ DoesNotAccessMemory,
		/* x86_avx2_psrli_q */ DoesNotAccessMemory,
		/* x86_avx2_psrli_w */ DoesNotAccessMemory,
		/* x86_avx2_psrlv_d */ DoesNotAccessMemory,
		/* x86_avx2_psrlv_d_256 */ DoesNotAccessMemory,
		/* x86_avx2_psrlv_q */ DoesNotAccessMemory,
		/* x86_avx2_psrlv_q_256 */ DoesNotAccessMemory,
		/* x86_avx2_psubs_b */ DoesNotAccessMemory,
		/* x86_avx2_psubs_w */ DoesNotAccessMemory,
		/* x86_avx2_psubus_b */ DoesNotAccessMemory,
		/* x86_avx2_psubus_w */ DoesNotAccessMemory,
		/* x86_avx2_vbroadcast_sd_pd_256 */ DoesNotAccessMemory,
		/* x86_avx2_vbroadcast_ss_ps */ DoesNotAccessMemory,
		/* x86_avx2_vbroadcast_ss_ps_256 */ DoesNotAccessMemory,
		/* x86_avx2_vbroadcasti128 */ OnlyReadsMemory,
		/* x86_avx2_vextracti128 */ DoesNotAccessMemory,
		/* x86_avx2_vinserti128 */ DoesNotAccessMemory,
		/* x86_avx2_vperm2i128 */ DoesNotAccessMemory,
		/* x86_avx_addsub_pd_256 */ DoesNotAccessMemory,
		/* x86_avx_addsub_ps_256 */ DoesNotAccessMemory,
		/* x86_avx_blend_pd_256 */ DoesNotAccessMemory,
		/* x86_avx_blend_ps_256 */ DoesNotAccessMemory,
		/* x86_avx_blendv_pd_256 */ DoesNotAccessMemory,
		/* x86_avx_blendv_ps_256 */ DoesNotAccessMemory,
		/* x86_avx_cmp_pd_256 */ DoesNotAccessMemory,
		/* x86_avx_cmp_ps_256 */ DoesNotAccessMemory,
		/* x86_avx_cvt_pd2_ps_256 */ DoesNotAccessMemory,
		/* x86_avx_cvt_pd2dq_256 */ DoesNotAccessMemory,
		/* x86_avx_cvt_ps2_pd_256 */ DoesNotAccessMemory,
		/* x86_avx_cvt_ps2dq_256 */ DoesNotAccessMemory,
		/* x86_avx_cvtdq2_pd_256 */ DoesNotAccessMemory,
		/* x86_avx_cvtdq2_ps_256 */ DoesNotAccessMemory,
		/* x86_avx_cvtt_pd2dq_256 */ DoesNotAccessMemory,
		/* x86_avx_cvtt_ps2dq_256 */ DoesNotAccessMemory,
		/* x86_avx_dp_ps_256 */ DoesNotAccessMemory,
		/* x86_avx_hadd_pd_256 */ DoesNotAccessMemory,
		/* x86_avx_hadd_ps_256 */ DoesNotAccessMemory,
		/* x86_avx_hsub_pd_256 */ DoesNotAccessMemory,
		/* x86_avx_hsub_ps_256 */ DoesNotAccessMemory,
		/* x86_avx_ldu_dq_256 */ OnlyReadsMemory,
		/* x86_avx_maskload_pd */ OnlyReadsMemory,
		/* x86_avx_maskload_pd_256 */ OnlyReadsMemory,
		/* x86_avx_maskload_ps */ OnlyReadsMemory,
		/* x86_avx_maskload_ps_256 */ OnlyReadsMemory,
		/* x86_avx_maskstore_pd */ UnknownModRefBehavior,
		/* x86_avx_maskstore_pd_256 */ UnknownModRefBehavior,
		/* x86_avx_maskstore_ps */ UnknownModRefBehavior,
		/* x86_avx_maskstore_ps_256 */ UnknownModRefBehavior,
		/* x86_avx_max_pd_256 */ DoesNotAccessMemory,
		/* x86_avx_max_ps_256 */ DoesNotAccessMemory,
		/* x86_avx_min_pd_256 */ DoesNotAccessMemory,
		/* x86_avx_min_ps_256 */ DoesNotAccessMemory,
		/* x86_avx_movmsk_pd_256 */ DoesNotAccessMemory,
		/* x86_avx_movmsk_ps_256 */ DoesNotAccessMemory,
		/* x86_avx_movnt_dq_256 */ UnknownModRefBehavior,
		/* x86_avx_movnt_pd_256 */ UnknownModRefBehavior,
		/* x86_avx_movnt_ps_256 */ UnknownModRefBehavior,
		/* x86_avx_ptestc_256 */ DoesNotAccessMemory,
		/* x86_avx_ptestnzc_256 */ DoesNotAccessMemory,
		/* x86_avx_ptestz_256 */ DoesNotAccessMemory,
		/* x86_avx_rcp_ps_256 */ DoesNotAccessMemory,
		/* x86_avx_round_pd_256 */ DoesNotAccessMemory,
		/* x86_avx_round_ps_256 */ DoesNotAccessMemory,
		/* x86_avx_rsqrt_ps_256 */ DoesNotAccessMemory,
		/* x86_avx_sqrt_pd_256 */ DoesNotAccessMemory,
		/* x86_avx_sqrt_ps_256 */ DoesNotAccessMemory,
		/* x86_avx_storeu_dq_256 */ UnknownModRefBehavior,
		/* x86_avx_storeu_pd_256 */ UnknownModRefBehavior,
		/* x86_avx_storeu_ps_256 */ UnknownModRefBehavior,
		/* x86_avx_vbroadcast_sd_256 */ OnlyReadsMemory,
		/* x86_avx_vbroadcast_ss */ OnlyReadsMemory,
		/* x86_avx_vbroadcast_ss_256 */ OnlyReadsMemory,
		/* x86_avx_vbroadcastf128_pd_256 */ OnlyReadsMemory,
		/* x86_avx_vbroadcastf128_ps_256 */ OnlyReadsMemory,
		/* x86_avx_vextractf128_pd_256 */ DoesNotAccessMemory,
		/* x86_avx_vextractf128_ps_256 */ DoesNotAccessMemory,
		/* x86_avx_vextractf128_si_256 */ DoesNotAccessMemory,
		/* x86_avx_vinsertf128_pd_256 */ DoesNotAccessMemory,
		/* x86_avx_vinsertf128_ps_256 */ DoesNotAccessMemory,
		/* x86_avx_vinsertf128_si_256 */ DoesNotAccessMemory,
		/* x86_avx_vperm2f128_pd_256 */ DoesNotAccessMemory,
		/* x86_avx_vperm2f128_ps_256 */ DoesNotAccessMemory,
		/* x86_avx_vperm2f128_si_256 */ DoesNotAccessMemory,
		/* x86_avx_vpermilvar_pd */ DoesNotAccessMemory,
		/* x86_avx_vpermilvar_pd_256 */ DoesNotAccessMemory,
		/* x86_avx_vpermilvar_ps */ DoesNotAccessMemory,
		/* x86_avx_vpermilvar_ps_256 */ DoesNotAccessMemory,
		/* x86_avx_vtestc_pd */ DoesNotAccessMemory,
		/* x86_avx_vtestc_pd_256 */ DoesNotAccessMemory,
		/* x86_avx_vtestc_ps */ DoesNotAccessMemory,
		/* x86_avx_vtestc_ps_256 */ DoesNotAccessMemory,
		/* x86_avx_vtestnzc_pd */ DoesNotAccessMemory,
		/* x86_avx_vtestnzc_pd_256 */ DoesNotAccessMemory,
		/* x86_avx_vtestnzc_ps */ DoesNotAccessMemory,
		/* x86_avx_vtestnzc_ps_256 */ DoesNotAccessMemory,
		/* x86_avx_vtestz_pd */ DoesNotAccessMemory,
		/* x86_avx_vtestz_pd_256 */ DoesNotAccessMemory,
		/* x86_avx_vtestz_ps */ DoesNotAccessMemory,
		/* x86_avx_vtestz_ps_256 */ DoesNotAccessMemory,
		/* x86_avx_vzeroall */ UnknownModRefBehavior,
		/* x86_avx_vzeroupper */ UnknownModRefBehavior,
		/* x86_bmi_bextr_32 */ DoesNotAccessMemory,
		/* x86_bmi_bextr_64 */ DoesNotAccessMemory,
		/* x86_bmi_bzhi_32 */ DoesNotAccessMemory,
		/* x86_bmi_bzhi_64 */ DoesNotAccessMemory,
		/* x86_bmi_pdep_32 */ DoesNotAccessMemory,
		/* x86_bmi_pdep_64 */ DoesNotAccessMemory,
		/* x86_bmi_pext_32 */ DoesNotAccessMemory,
		/* x86_bmi_pext_64 */ DoesNotAccessMemory,
		/* x86_fma4_vfmadd_pd */ DoesNotAccessMemory,
		/* x86_fma4_vfmadd_pd_256 */ DoesNotAccessMemory,
		/* x86_fma4_vfmadd_ps */ DoesNotAccessMemory,
		/* x86_fma4_vfmadd_ps_256 */ DoesNotAccessMemory,
		/* x86_fma4_vfmadd_sd */ DoesNotAccessMemory,
		/* x86_fma4_vfmadd_ss */ DoesNotAccessMemory,
		/* x86_fma4_vfmaddsub_pd */ DoesNotAccessMemory,
		/* x86_fma4_vfmaddsub_pd_256 */ DoesNotAccessMemory,
		/* x86_fma4_vfmaddsub_ps */ DoesNotAccessMemory,
		/* x86_fma4_vfmaddsub_ps_256 */ DoesNotAccessMemory,
		/* x86_fma4_vfmsub_pd */ DoesNotAccessMemory,
		/* x86_fma4_vfmsub_pd_256 */ DoesNotAccessMemory,
		/* x86_fma4_vfmsub_ps */ DoesNotAccessMemory,
		/* x86_fma4_vfmsub_ps_256 */ DoesNotAccessMemory,
		/* x86_fma4_vfmsub_sd */ DoesNotAccessMemory,
		/* x86_fma4_vfmsub_ss */ DoesNotAccessMemory,
		/* x86_fma4_vfmsubadd_pd */ DoesNotAccessMemory,
		/* x86_fma4_vfmsubadd_pd_256 */ DoesNotAccessMemory,
		/* x86_fma4_vfmsubadd_ps */ DoesNotAccessMemory,
		/* x86_fma4_vfmsubadd_ps_256 */ DoesNotAccessMemory,
		/* x86_fma4_vfnmadd_pd */ DoesNotAccessMemory,
		/* x86_fma4_vfnmadd_pd_256 */ DoesNotAccessMemory,
		/* x86_fma4_vfnmadd_ps */ DoesNotAccessMemory,
		/* x86_fma4_vfnmadd_ps_256 */ DoesNotAccessMemory,
		/* x86_fma4_vfnmadd_sd */ DoesNotAccessMemory,
		/* x86_fma4_vfnmadd_ss */ DoesNotAccessMemory,
		/* x86_fma4_vfnmsub_pd */ DoesNotAccessMemory,
		/* x86_fma4_vfnmsub_pd_256 */ DoesNotAccessMemory,
		/* x86_fma4_vfnmsub_ps */ DoesNotAccessMemory,
		/* x86_fma4_vfnmsub_ps_256 */ DoesNotAccessMemory,
		/* x86_fma4_vfnmsub_sd */ DoesNotAccessMemory,
		/* x86_fma4_vfnmsub_ss */ DoesNotAccessMemory,
		/* x86_int */ UnknownModRefBehavior,
		/* x86_mmx_emms */ UnknownModRefBehavior,
		/* x86_mmx_femms */ UnknownModRefBehavior,
		/* x86_mmx_maskmovq */ UnknownModRefBehavior,
		/* x86_mmx_movnt_dq */ UnknownModRefBehavior,
		/* x86_mmx_packssdw */ DoesNotAccessMemory,
		/* x86_mmx_packsswb */ DoesNotAccessMemory,
		/* x86_mmx_packuswb */ DoesNotAccessMemory,
		/* x86_mmx_padd_b */ DoesNotAccessMemory,
		/* x86_mmx_padd_d */ DoesNotAccessMemory,
		/* x86_mmx_padd_q */ DoesNotAccessMemory,
		/* x86_mmx_padd_w */ DoesNotAccessMemory,
		/* x86_mmx_padds_b */ DoesNotAccessMemory,
		/* x86_mmx_padds_w */ DoesNotAccessMemory,
		/* x86_mmx_paddus_b */ DoesNotAccessMemory,
		/* x86_mmx_paddus_w */ DoesNotAccessMemory,
		/* x86_mmx_palignr_b */ DoesNotAccessMemory,
		/* x86_mmx_pand */ DoesNotAccessMemory,
		/* x86_mmx_pandn */ DoesNotAccessMemory,
		/* x86_mmx_pavg_b */ DoesNotAccessMemory,
		/* x86_mmx_pavg_w */ DoesNotAccessMemory,
		/* x86_mmx_pcmpeq_b */ DoesNotAccessMemory,
		/* x86_mmx_pcmpeq_d */ DoesNotAccessMemory,
		/* x86_mmx_pcmpeq_w */ DoesNotAccessMemory,
		/* x86_mmx_pcmpgt_b */ DoesNotAccessMemory,
		/* x86_mmx_pcmpgt_d */ DoesNotAccessMemory,
		/* x86_mmx_pcmpgt_w */ DoesNotAccessMemory,
		/* x86_mmx_pextr_w */ DoesNotAccessMemory,
		/* x86_mmx_pinsr_w */ DoesNotAccessMemory,
		/* x86_mmx_pmadd_wd */ DoesNotAccessMemory,
		/* x86_mmx_pmaxs_w */ DoesNotAccessMemory,
		/* x86_mmx_pmaxu_b */ DoesNotAccessMemory,
		/* x86_mmx_pmins_w */ DoesNotAccessMemory,
		/* x86_mmx_pminu_b */ DoesNotAccessMemory,
		/* x86_mmx_pmovmskb */ DoesNotAccessMemory,
		/* x86_mmx_pmulh_w */ DoesNotAccessMemory,
		/* x86_mmx_pmulhu_w */ DoesNotAccessMemory,
		/* x86_mmx_pmull_w */ DoesNotAccessMemory,
		/* x86_mmx_pmulu_dq */ DoesNotAccessMemory,
		/* x86_mmx_por */ DoesNotAccessMemory,
		/* x86_mmx_psad_bw */ DoesNotAccessMemory,
		/* x86_mmx_psll_d */ DoesNotAccessMemory,
		/* x86_mmx_psll_q */ DoesNotAccessMemory,
		/* x86_mmx_psll_w */ DoesNotAccessMemory,
		/* x86_mmx_pslli_d */ DoesNotAccessMemory,
		/* x86_mmx_pslli_q */ DoesNotAccessMemory,
		/* x86_mmx_pslli_w */ DoesNotAccessMemory,
		/* x86_mmx_psra_d */ DoesNotAccessMemory,
		/* x86_mmx_psra_w */ DoesNotAccessMemory,
		/* x86_mmx_psrai_d */ DoesNotAccessMemory,
		/* x86_mmx_psrai_w */ DoesNotAccessMemory,
		/* x86_mmx_psrl_d */ DoesNotAccessMemory,
		/* x86_mmx_psrl_q */ DoesNotAccessMemory,
		/* x86_mmx_psrl_w */ DoesNotAccessMemory,
		/* x86_mmx_psrli_d */ DoesNotAccessMemory,
		/* x86_mmx_psrli_q */ DoesNotAccessMemory,
		/* x86_mmx_psrli_w */ DoesNotAccessMemory,
		/* x86_mmx_psub_b */ DoesNotAccessMemory,
		/* x86_mmx_psub_d */ DoesNotAccessMemory,
		/* x86_mmx_psub_q */ DoesNotAccessMemory,
		/* x86_mmx_psub_w */ DoesNotAccessMemory,
		/* x86_mmx_psubs_b */ DoesNotAccessMemory,
		/* x86_mmx_psubs_w */ DoesNotAccessMemory,
		/* x86_mmx_psubus_b */ DoesNotAccessMemory,
		/* x86_mmx_psubus_w */ DoesNotAccessMemory,
		/* x86_mmx_punpckhbw */ DoesNotAccessMemory,
		/* x86_mmx_punpckhdq */ DoesNotAccessMemory,
		/* x86_mmx_punpckhwd */ DoesNotAccessMemory,
		/* x86_mmx_punpcklbw */ DoesNotAccessMemory,
		/* x86_mmx_punpckldq */ DoesNotAccessMemory,
		/* x86_mmx_punpcklwd */ DoesNotAccessMemory,
		/* x86_mmx_pxor */ DoesNotAccessMemory,
		/* x86_rdfsbase_32 */ UnknownModRefBehavior,
		/* x86_rdfsbase_64 */ UnknownModRefBehavior,
		/* x86_rdgsbase_32 */ UnknownModRefBehavior,
		/* x86_rdgsbase_64 */ UnknownModRefBehavior,
		/* x86_sse2_add_sd */ DoesNotAccessMemory,
		/* x86_sse2_clflush */ UnknownModRefBehavior,
		/* x86_sse2_cmp_pd */ DoesNotAccessMemory,
		/* x86_sse2_cmp_sd */ DoesNotAccessMemory,
		/* x86_sse2_comieq_sd */ DoesNotAccessMemory,
		/* x86_sse2_comige_sd */ DoesNotAccessMemory,
		/* x86_sse2_comigt_sd */ DoesNotAccessMemory,
		/* x86_sse2_comile_sd */ DoesNotAccessMemory,
		/* x86_sse2_comilt_sd */ DoesNotAccessMemory,
		/* x86_sse2_comineq_sd */ DoesNotAccessMemory,
		/* x86_sse2_cvtdq2pd */ DoesNotAccessMemory,
		/* x86_sse2_cvtdq2ps */ DoesNotAccessMemory,
		/* x86_sse2_cvtpd2dq */ DoesNotAccessMemory,
		/* x86_sse2_cvtpd2ps */ DoesNotAccessMemory,
		/* x86_sse2_cvtps2dq */ DoesNotAccessMemory,
		/* x86_sse2_cvtps2pd */ DoesNotAccessMemory,
		/* x86_sse2_cvtsd2si */ DoesNotAccessMemory,
		/* x86_sse2_cvtsd2si64 */ DoesNotAccessMemory,
		/* x86_sse2_cvtsd2ss */ DoesNotAccessMemory,
		/* x86_sse2_cvtsi2sd */ DoesNotAccessMemory,
		/* x86_sse2_cvtsi642sd */ DoesNotAccessMemory,
		/* x86_sse2_cvtss2sd */ DoesNotAccessMemory,
		/* x86_sse2_cvttpd2dq */ DoesNotAccessMemory,
		/* x86_sse2_cvttps2dq */ DoesNotAccessMemory,
		/* x86_sse2_cvttsd2si */ DoesNotAccessMemory,
		/* x86_sse2_cvttsd2si64 */ DoesNotAccessMemory,
		/* x86_sse2_div_sd */ DoesNotAccessMemory,
		/* x86_sse2_lfence */ UnknownModRefBehavior,
		/* x86_sse2_maskmov_dqu */ UnknownModRefBehavior,
		/* x86_sse2_max_pd */ DoesNotAccessMemory,
		/* x86_sse2_max_sd */ DoesNotAccessMemory,
		/* x86_sse2_mfence */ UnknownModRefBehavior,
		/* x86_sse2_min_pd */ DoesNotAccessMemory,
		/* x86_sse2_min_sd */ DoesNotAccessMemory,
		/* x86_sse2_movmsk_pd */ DoesNotAccessMemory,
		/* x86_sse2_mul_sd */ DoesNotAccessMemory,
		/* x86_sse2_packssdw_128 */ DoesNotAccessMemory,
		/* x86_sse2_packsswb_128 */ DoesNotAccessMemory,
		/* x86_sse2_packuswb_128 */ DoesNotAccessMemory,
		/* x86_sse2_padds_b */ DoesNotAccessMemory,
		/* x86_sse2_padds_w */ DoesNotAccessMemory,
		/* x86_sse2_paddus_b */ DoesNotAccessMemory,
		/* x86_sse2_paddus_w */ DoesNotAccessMemory,
		/* x86_sse2_pavg_b */ DoesNotAccessMemory,
		/* x86_sse2_pavg_w */ DoesNotAccessMemory,
		/* x86_sse2_pmadd_wd */ DoesNotAccessMemory,
		/* x86_sse2_pmaxs_w */ DoesNotAccessMemory,
		/* x86_sse2_pmaxu_b */ DoesNotAccessMemory,
		/* x86_sse2_pmins_w */ DoesNotAccessMemory,
		/* x86_sse2_pminu_b */ DoesNotAccessMemory,
		/* x86_sse2_pmovmskb_128 */ DoesNotAccessMemory,
		/* x86_sse2_pmulh_w */ DoesNotAccessMemory,
		/* x86_sse2_pmulhu_w */ DoesNotAccessMemory,
		/* x86_sse2_pmulu_dq */ DoesNotAccessMemory,
		/* x86_sse2_psad_bw */ DoesNotAccessMemory,
		/* x86_sse2_psll_d */ DoesNotAccessMemory,
		/* x86_sse2_psll_dq */ DoesNotAccessMemory,
		/* x86_sse2_psll_dq_bs */ DoesNotAccessMemory,
		/* x86_sse2_psll_q */ DoesNotAccessMemory,
		/* x86_sse2_psll_w */ DoesNotAccessMemory,
		/* x86_sse2_pslli_d */ DoesNotAccessMemory,
		/* x86_sse2_pslli_q */ DoesNotAccessMemory,
		/* x86_sse2_pslli_w */ DoesNotAccessMemory,
		/* x86_sse2_psra_d */ DoesNotAccessMemory,
		/* x86_sse2_psra_w */ DoesNotAccessMemory,
		/* x86_sse2_psrai_d */ DoesNotAccessMemory,
		/* x86_sse2_psrai_w */ DoesNotAccessMemory,
		/* x86_sse2_psrl_d */ DoesNotAccessMemory,
		/* x86_sse2_psrl_dq */ DoesNotAccessMemory,
		/* x86_sse2_psrl_dq_bs */ DoesNotAccessMemory,
		/* x86_sse2_psrl_q */ DoesNotAccessMemory,
		/* x86_sse2_psrl_w */ DoesNotAccessMemory,
		/* x86_sse2_psrli_d */ DoesNotAccessMemory,
		/* x86_sse2_psrli_q */ DoesNotAccessMemory,
		/* x86_sse2_psrli_w */ DoesNotAccessMemory,
		/* x86_sse2_psubs_b */ DoesNotAccessMemory,
		/* x86_sse2_psubs_w */ DoesNotAccessMemory,
		/* x86_sse2_psubus_b */ DoesNotAccessMemory,
		/* x86_sse2_psubus_w */ DoesNotAccessMemory,
		/* x86_sse2_sqrt_pd */ DoesNotAccessMemory,
		/* x86_sse2_sqrt_sd */ DoesNotAccessMemory,
		/* x86_sse2_storel_dq */ UnknownModRefBehavior,
		/* x86_sse2_storeu_dq */ UnknownModRefBehavior,
		/* x86_sse2_storeu_pd */ UnknownModRefBehavior,
		/* x86_sse2_sub_sd */ DoesNotAccessMemory,
		/* x86_sse2_ucomieq_sd */ DoesNotAccessMemory,
		/* x86_sse2_ucomige_sd */ DoesNotAccessMemory,
		/* x86_sse2_ucomigt_sd */ DoesNotAccessMemory,
		/* x86_sse2_ucomile_sd */ DoesNotAccessMemory,
		/* x86_sse2_ucomilt_sd */ DoesNotAccessMemory,
		/* x86_sse2_ucomineq_sd */ DoesNotAccessMemory,
		/* x86_sse3_addsub_pd */ DoesNotAccessMemory,
		/* x86_sse3_addsub_ps */ DoesNotAccessMemory,
		/* x86_sse3_hadd_pd */ DoesNotAccessMemory,
		/* x86_sse3_hadd_ps */ DoesNotAccessMemory,
		/* x86_sse3_hsub_pd */ DoesNotAccessMemory,
		/* x86_sse3_hsub_ps */ DoesNotAccessMemory,
		/* x86_sse3_ldu_dq */ OnlyReadsMemory,
		/* x86_sse3_monitor */ UnknownModRefBehavior,
		/* x86_sse3_mwait */ UnknownModRefBehavior,
		/* x86_sse41_blendpd */ DoesNotAccessMemory,
		/* x86_sse41_blendps */ DoesNotAccessMemory,
		/* x86_sse41_blendvpd */ DoesNotAccessMemory,
		/* x86_sse41_blendvps */ DoesNotAccessMemory,
		/* x86_sse41_dppd */ DoesNotAccessMemory,
		/* x86_sse41_dpps */ DoesNotAccessMemory,
		/* x86_sse41_extractps */ DoesNotAccessMemory,
		/* x86_sse41_insertps */ DoesNotAccessMemory,
		/* x86_sse41_movntdqa */ OnlyReadsMemory,
		/* x86_sse41_mpsadbw */ DoesNotAccessMemory,
		/* x86_sse41_packusdw */ DoesNotAccessMemory,
		/* x86_sse41_pblendvb */ DoesNotAccessMemory,
		/* x86_sse41_pblendw */ DoesNotAccessMemory,
		/* x86_sse41_pextrb */ DoesNotAccessMemory,
		/* x86_sse41_pextrd */ DoesNotAccessMemory,
		/* x86_sse41_pextrq */ DoesNotAccessMemory,
		/* x86_sse41_phminposuw */ DoesNotAccessMemory,
		/* x86_sse41_pmaxsb */ DoesNotAccessMemory,
		/* x86_sse41_pmaxsd */ DoesNotAccessMemory,
		/* x86_sse41_pmaxud */ DoesNotAccessMemory,
		/* x86_sse41_pmaxuw */ DoesNotAccessMemory,
		/* x86_sse41_pminsb */ DoesNotAccessMemory,
		/* x86_sse41_pminsd */ DoesNotAccessMemory,
		/* x86_sse41_pminud */ DoesNotAccessMemory,
		/* x86_sse41_pminuw */ DoesNotAccessMemory,
		/* x86_sse41_pmovsxbd */ DoesNotAccessMemory,
		/* x86_sse41_pmovsxbq */ DoesNotAccessMemory,
		/* x86_sse41_pmovsxbw */ DoesNotAccessMemory,
		/* x86_sse41_pmovsxdq */ DoesNotAccessMemory,
		/* x86_sse41_pmovsxwd */ DoesNotAccessMemory,
		/* x86_sse41_pmovsxwq */ DoesNotAccessMemory,
		/* x86_sse41_pmovzxbd */ DoesNotAccessMemory,
		/* x86_sse41_pmovzxbq */ DoesNotAccessMemory,
		/* x86_sse41_pmovzxbw */ DoesNotAccessMemory,
		/* x86_sse41_pmovzxdq */ DoesNotAccessMemory,
		/* x86_sse41_pmovzxwd */ DoesNotAccessMemory,
		/* x86_sse41_pmovzxwq */ DoesNotAccessMemory,
		/* x86_sse41_pmuldq */ DoesNotAccessMemory,
		/* x86_sse41_ptestc */ DoesNotAccessMemory,
		/* x86_sse41_ptestnzc */ DoesNotAccessMemory,
		/* x86_sse41_ptestz */ DoesNotAccessMemory,
		/* x86_sse41_round_pd */ DoesNotAccessMemory,
		/* x86_sse41_round_ps */ DoesNotAccessMemory,
		/* x86_sse41_round_sd */ DoesNotAccessMemory,
		/* x86_sse41_round_ss */ DoesNotAccessMemory,
		/* x86_sse42_crc32_32_16 */ DoesNotAccessMemory,
		/* x86_sse42_crc32_32_32 */ DoesNotAccessMemory,
		/* x86_sse42_crc32_32_8 */ DoesNotAccessMemory,
		/* x86_sse42_crc32_64_64 */ DoesNotAccessMemory,
		/* x86_sse42_crc32_64_8 */ DoesNotAccessMemory,
		/* x86_sse42_pcmpestri128 */ DoesNotAccessMemory,
		/* x86_sse42_pcmpestria128 */ DoesNotAccessMemory,
		/* x86_sse42_pcmpestric128 */ DoesNotAccessMemory,
		/* x86_sse42_pcmpestrio128 */ DoesNotAccessMemory,
		/* x86_sse42_pcmpestris128 */ DoesNotAccessMemory,
		/* x86_sse42_pcmpestriz128 */ DoesNotAccessMemory,
		/* x86_sse42_pcmpestrm128 */ DoesNotAccessMemory,
		/* x86_sse42_pcmpistri128 */ DoesNotAccessMemory,
		/* x86_sse42_pcmpistria128 */ DoesNotAccessMemory,
		/* x86_sse42_pcmpistric128 */ DoesNotAccessMemory,
		/* x86_sse42_pcmpistrio128 */ DoesNotAccessMemory,
		/* x86_sse42_pcmpistris128 */ DoesNotAccessMemory,
		/* x86_sse42_pcmpistriz128 */ DoesNotAccessMemory,
		/* x86_sse42_pcmpistrm128 */ DoesNotAccessMemory,
		/* x86_sse_add_ss */ DoesNotAccessMemory,
		/* x86_sse_cmp_ps */ DoesNotAccessMemory,
		/* x86_sse_cmp_ss */ DoesNotAccessMemory,
		/* x86_sse_comieq_ss */ DoesNotAccessMemory,
		/* x86_sse_comige_ss */ DoesNotAccessMemory,
		/* x86_sse_comigt_ss */ DoesNotAccessMemory,
		/* x86_sse_comile_ss */ DoesNotAccessMemory,
		/* x86_sse_comilt_ss */ DoesNotAccessMemory,
		/* x86_sse_comineq_ss */ DoesNotAccessMemory,
		/* x86_sse_cvtpd2pi */ DoesNotAccessMemory,
		/* x86_sse_cvtpi2pd */ DoesNotAccessMemory,
		/* x86_sse_cvtpi2ps */ DoesNotAccessMemory,
		/* x86_sse_cvtps2pi */ DoesNotAccessMemory,
		/* x86_sse_cvtsi2ss */ DoesNotAccessMemory,
		/* x86_sse_cvtsi642ss */ DoesNotAccessMemory,
		/* x86_sse_cvtss2si */ DoesNotAccessMemory,
		/* x86_sse_cvtss2si64 */ DoesNotAccessMemory,
		/* x86_sse_cvttpd2pi */ DoesNotAccessMemory,
		/* x86_sse_cvttps2pi */ DoesNotAccessMemory,
		/* x86_sse_cvttss2si */ DoesNotAccessMemory,
		/* x86_sse_cvttss2si64 */ DoesNotAccessMemory,
		/* x86_sse_div_ss */ DoesNotAccessMemory,
		/* x86_sse_ldmxcsr */ UnknownModRefBehavior,
		/* x86_sse_max_ps */ DoesNotAccessMemory,
		/* x86_sse_max_ss */ DoesNotAccessMemory,
		/* x86_sse_min_ps */ DoesNotAccessMemory,
		/* x86_sse_min_ss */ DoesNotAccessMemory,
		/* x86_sse_movmsk_ps */ DoesNotAccessMemory,
		/* x86_sse_mul_ss */ DoesNotAccessMemory,
		/* x86_sse_pshuf_w */ DoesNotAccessMemory,
		/* x86_sse_rcp_ps */ DoesNotAccessMemory,
		/* x86_sse_rcp_ss */ DoesNotAccessMemory,
		/* x86_sse_rsqrt_ps */ DoesNotAccessMemory,
		/* x86_sse_rsqrt_ss */ DoesNotAccessMemory,
		/* x86_sse_sfence */ UnknownModRefBehavior,
		/* x86_sse_sqrt_ps */ DoesNotAccessMemory,
		/* x86_sse_sqrt_ss */ DoesNotAccessMemory,
		/* x86_sse_stmxcsr */ UnknownModRefBehavior,
		/* x86_sse_storeu_ps */ UnknownModRefBehavior,
		/* x86_sse_sub_ss */ DoesNotAccessMemory,
		/* x86_sse_ucomieq_ss */ DoesNotAccessMemory,
		/* x86_sse_ucomige_ss */ DoesNotAccessMemory,
		/* x86_sse_ucomigt_ss */ DoesNotAccessMemory,
		/* x86_sse_ucomile_ss */ DoesNotAccessMemory,
		/* x86_sse_ucomilt_ss */ DoesNotAccessMemory,
		/* x86_sse_ucomineq_ss */ DoesNotAccessMemory,
		/* x86_ssse3_pabs_b */ DoesNotAccessMemory,
		/* x86_ssse3_pabs_b_128 */ DoesNotAccessMemory,
		/* x86_ssse3_pabs_d */ DoesNotAccessMemory,
		/* x86_ssse3_pabs_d_128 */ DoesNotAccessMemory,
		/* x86_ssse3_pabs_w */ DoesNotAccessMemory,
		/* x86_ssse3_pabs_w_128 */ DoesNotAccessMemory,
		/* x86_ssse3_phadd_d */ DoesNotAccessMemory,
		/* x86_ssse3_phadd_d_128 */ DoesNotAccessMemory,
		/* x86_ssse3_phadd_sw */ DoesNotAccessMemory,
		/* x86_ssse3_phadd_sw_128 */ DoesNotAccessMemory,
		/* x86_ssse3_phadd_w */ DoesNotAccessMemory,
		/* x86_ssse3_phadd_w_128 */ DoesNotAccessMemory,
		/* x86_ssse3_phsub_d */ DoesNotAccessMemory,
		/* x86_ssse3_phsub_d_128 */ DoesNotAccessMemory,
		/* x86_ssse3_phsub_sw */ DoesNotAccessMemory,
		/* x86_ssse3_phsub_sw_128 */ DoesNotAccessMemory,
		/* x86_ssse3_phsub_w */ DoesNotAccessMemory,
		/* x86_ssse3_phsub_w_128 */ DoesNotAccessMemory,
		/* x86_ssse3_pmadd_ub_sw */ DoesNotAccessMemory,
		/* x86_ssse3_pmadd_ub_sw_128 */ DoesNotAccessMemory,
		/* x86_ssse3_pmul_hr_sw */ DoesNotAccessMemory,
		/* x86_ssse3_pmul_hr_sw_128 */ DoesNotAccessMemory,
		/* x86_ssse3_pshuf_b */ DoesNotAccessMemory,
		/* x86_ssse3_pshuf_b_128 */ DoesNotAccessMemory,
		/* x86_ssse3_psign_b */ DoesNotAccessMemory,
		/* x86_ssse3_psign_b_128 */ DoesNotAccessMemory,
		/* x86_ssse3_psign_d */ DoesNotAccessMemory,
		/* x86_ssse3_psign_d_128 */ DoesNotAccessMemory,
		/* x86_ssse3_psign_w */ DoesNotAccessMemory,
		/* x86_ssse3_psign_w_128 */ DoesNotAccessMemory,
		/* x86_vcvtph2ps_128 */ DoesNotAccessMemory,
		/* x86_vcvtph2ps_256 */ DoesNotAccessMemory,
		/* x86_vcvtps2ph_128 */ DoesNotAccessMemory,
		/* x86_vcvtps2ph_256 */ DoesNotAccessMemory,
		/* x86_wrfsbase_32 */ UnknownModRefBehavior,
		/* x86_wrfsbase_64 */ UnknownModRefBehavior,
		/* x86_wrgsbase_32 */ UnknownModRefBehavior,
		/* x86_wrgsbase_64 */ UnknownModRefBehavior,
		/* x86_xop_vfrcz_pd */ DoesNotAccessMemory,
		/* x86_xop_vfrcz_pd_256 */ DoesNotAccessMemory,
		/* x86_xop_vfrcz_ps */ DoesNotAccessMemory,
		/* x86_xop_vfrcz_ps_256 */ DoesNotAccessMemory,
		/* x86_xop_vfrcz_sd */ DoesNotAccessMemory,
		/* x86_xop_vfrcz_ss */ DoesNotAccessMemory,
		/* x86_xop_vpcmov */ DoesNotAccessMemory,
		/* x86_xop_vpcmov_256 */ DoesNotAccessMemory,
		/* x86_xop_vpcomeqb */ DoesNotAccessMemory,
		/* x86_xop_vpcomeqd */ DoesNotAccessMemory,
		/* x86_xop_vpcomeqq */ DoesNotAccessMemory,
		/* x86_xop_vpcomequb */ DoesNotAccessMemory,
		/* x86_xop_vpcomequd */ DoesNotAccessMemory,
		/* x86_xop_vpcomequq */ DoesNotAccessMemory,
		/* x86_xop_vpcomequw */ DoesNotAccessMemory,
		/* x86_xop_vpcomeqw */ DoesNotAccessMemory,
		/* x86_xop_vpcomfalseb */ DoesNotAccessMemory,
		/* x86_xop_vpcomfalsed */ DoesNotAccessMemory,
		/* x86_xop_vpcomfalseq */ DoesNotAccessMemory,
		/* x86_xop_vpcomfalseub */ DoesNotAccessMemory,
		/* x86_xop_vpcomfalseud */ DoesNotAccessMemory,
		/* x86_xop_vpcomfalseuq */ DoesNotAccessMemory,
		/* x86_xop_vpcomfalseuw */ DoesNotAccessMemory,
		/* x86_xop_vpcomfalsew */ DoesNotAccessMemory,
		/* x86_xop_vpcomgeb */ DoesNotAccessMemory,
		/* x86_xop_vpcomged */ DoesNotAccessMemory,
		/* x86_xop_vpcomgeq */ DoesNotAccessMemory,
		/* x86_xop_vpcomgeub */ DoesNotAccessMemory,
		/* x86_xop_vpcomgeud */ DoesNotAccessMemory,
		/* x86_xop_vpcomgeuq */ DoesNotAccessMemory,
		/* x86_xop_vpcomgeuw */ DoesNotAccessMemory,
		/* x86_xop_vpcomgew */ DoesNotAccessMemory,
		/* x86_xop_vpcomgtb */ DoesNotAccessMemory,
		/* x86_xop_vpcomgtd */ DoesNotAccessMemory,
		/* x86_xop_vpcomgtq */ DoesNotAccessMemory,
		/* x86_xop_vpcomgtub */ DoesNotAccessMemory,
		/* x86_xop_vpcomgtud */ DoesNotAccessMemory,
		/* x86_xop_vpcomgtuq */ DoesNotAccessMemory,
		/* x86_xop_vpcomgtuw */ DoesNotAccessMemory,
		/* x86_xop_vpcomgtw */ DoesNotAccessMemory,
		/* x86_xop_vpcomleb */ DoesNotAccessMemory,
		/* x86_xop_vpcomled */ DoesNotAccessMemory,
		/* x86_xop_vpcomleq */ DoesNotAccessMemory,
		/* x86_xop_vpcomleub */ DoesNotAccessMemory,
		/* x86_xop_vpcomleud */ DoesNotAccessMemory,
		/* x86_xop_vpcomleuq */ DoesNotAccessMemory,
		/* x86_xop_vpcomleuw */ DoesNotAccessMemory,
		/* x86_xop_vpcomlew */ DoesNotAccessMemory,
		/* x86_xop_vpcomltb */ DoesNotAccessMemory,
		/* x86_xop_vpcomltd */ DoesNotAccessMemory,
		/* x86_xop_vpcomltq */ DoesNotAccessMemory,
		/* x86_xop_vpcomltub */ DoesNotAccessMemory,
		/* x86_xop_vpcomltud */ DoesNotAccessMemory,
		/* x86_xop_vpcomltuq */ DoesNotAccessMemory,
		/* x86_xop_vpcomltuw */ DoesNotAccessMemory,
		/* x86_xop_vpcomltw */ DoesNotAccessMemory,
		/* x86_xop_vpcomneb */ DoesNotAccessMemory,
		/* x86_xop_vpcomned */ DoesNotAccessMemory,
		/* x86_xop_vpcomneq */ DoesNotAccessMemory,
		/* x86_xop_vpcomneub */ DoesNotAccessMemory,
		/* x86_xop_vpcomneud */ DoesNotAccessMemory,
		/* x86_xop_vpcomneuq */ DoesNotAccessMemory,
		/* x86_xop_vpcomneuw */ DoesNotAccessMemory,
		/* x86_xop_vpcomnew */ DoesNotAccessMemory,
		/* x86_xop_vpcomtrueb */ DoesNotAccessMemory,
		/* x86_xop_vpcomtrued */ DoesNotAccessMemory,
		/* x86_xop_vpcomtrueq */ DoesNotAccessMemory,
		/* x86_xop_vpcomtrueub */ DoesNotAccessMemory,
		/* x86_xop_vpcomtrueud */ DoesNotAccessMemory,
		/* x86_xop_vpcomtrueuq */ DoesNotAccessMemory,
		/* x86_xop_vpcomtrueuw */ DoesNotAccessMemory,
		/* x86_xop_vpcomtruew */ DoesNotAccessMemory,
		/* x86_xop_vpermil2pd */ DoesNotAccessMemory,
		/* x86_xop_vpermil2pd_256 */ DoesNotAccessMemory,
		/* x86_xop_vpermil2ps */ DoesNotAccessMemory,
		/* x86_xop_vpermil2ps_256 */ DoesNotAccessMemory,
		/* x86_xop_vphaddbd */ DoesNotAccessMemory,
		/* x86_xop_vphaddbq */ DoesNotAccessMemory,
		/* x86_xop_vphaddbw */ DoesNotAccessMemory,
		/* x86_xop_vphadddq */ DoesNotAccessMemory,
		/* x86_xop_vphaddubd */ DoesNotAccessMemory,
		/* x86_xop_vphaddubq */ DoesNotAccessMemory,
		/* x86_xop_vphaddubw */ DoesNotAccessMemory,
		/* x86_xop_vphaddudq */ DoesNotAccessMemory,
		/* x86_xop_vphadduwd */ DoesNotAccessMemory,
		/* x86_xop_vphadduwq */ DoesNotAccessMemory,
		/* x86_xop_vphaddwd */ DoesNotAccessMemory,
		/* x86_xop_vphaddwq */ DoesNotAccessMemory,
		/* x86_xop_vphsubbw */ DoesNotAccessMemory,
		/* x86_xop_vphsubdq */ DoesNotAccessMemory,
		/* x86_xop_vphsubwd */ DoesNotAccessMemory,
		/* x86_xop_vpmacsdd */ DoesNotAccessMemory,
		/* x86_xop_vpmacsdqh */ DoesNotAccessMemory,
		/* x86_xop_vpmacsdql */ DoesNotAccessMemory,
		/* x86_xop_vpmacssdd */ DoesNotAccessMemory,
		/* x86_xop_vpmacssdqh */ DoesNotAccessMemory,
		/* x86_xop_vpmacssdql */ DoesNotAccessMemory,
		/* x86_xop_vpmacsswd */ DoesNotAccessMemory,
		/* x86_xop_vpmacssww */ DoesNotAccessMemory,
		/* x86_xop_vpmacswd */ DoesNotAccessMemory,
		/* x86_xop_vpmacsww */ DoesNotAccessMemory,
		/* x86_xop_vpmadcsswd */ DoesNotAccessMemory,
		/* x86_xop_vpmadcswd */ DoesNotAccessMemory,
		/* x86_xop_vpperm */ DoesNotAccessMemory,
		/* x86_xop_vprotb */ DoesNotAccessMemory,
		/* x86_xop_vprotd */ DoesNotAccessMemory,
		/* x86_xop_vprotq */ DoesNotAccessMemory,
		/* x86_xop_vprotw */ DoesNotAccessMemory,
		/* x86_xop_vpshab */ DoesNotAccessMemory,
		/* x86_xop_vpshad */ DoesNotAccessMemory,
		/* x86_xop_vpshaq */ DoesNotAccessMemory,
		/* x86_xop_vpshaw */ DoesNotAccessMemory,
		/* x86_xop_vpshlb */ DoesNotAccessMemory,
		/* x86_xop_vpshld */ DoesNotAccessMemory,
		/* x86_xop_vpshlq */ DoesNotAccessMemory,
		/* x86_xop_vpshlw */ DoesNotAccessMemory,
		/* xcore_bitrev */ DoesNotAccessMemory,
		/* xcore_checkevent */ UnknownModRefBehavior,
		/* xcore_chkct */ UnknownModRefBehavior,
		/* xcore_clre */ UnknownModRefBehavior,
		/* xcore_clrsr */ UnknownModRefBehavior,
		/* xcore_crc32 */ DoesNotAccessMemory,
		/* xcore_crc8 */ DoesNotAccessMemory,
		/* xcore_eeu */ UnknownModRefBehavior,
		/* xcore_endin */ UnknownModRefBehavior,
		/* xcore_freer */ UnknownModRefBehavior,
		/* xcore_geted */ UnknownModRefBehavior,
		/* xcore_getet */ UnknownModRefBehavior,
		/* xcore_getid */ DoesNotAccessMemory,
		/* xcore_getps */ UnknownModRefBehavior,
		/* xcore_getr */ UnknownModRefBehavior,
		/* xcore_getst */ UnknownModRefBehavior,
		/* xcore_getts */ UnknownModRefBehavior,
		/* xcore_in */ UnknownModRefBehavior,
		/* xcore_inct */ UnknownModRefBehavior,
		/* xcore_initcp */ UnknownModRefBehavior,
		/* xcore_initdp */ UnknownModRefBehavior,
		/* xcore_initlr */ UnknownModRefBehavior,
		/* xcore_initpc */ UnknownModRefBehavior,
		/* xcore_initsp */ UnknownModRefBehavior,
		/* xcore_inshr */ UnknownModRefBehavior,
		/* xcore_int */ UnknownModRefBehavior,
		/* xcore_mjoin */ UnknownModRefBehavior,
		/* xcore_msync */ UnknownModRefBehavior,
		/* xcore_out */ UnknownModRefBehavior,
		/* xcore_outct */ UnknownModRefBehavior,
		/* xcore_outshr */ UnknownModRefBehavior,
		/* xcore_outt */ UnknownModRefBehavior,
		/* xcore_peek */ UnknownModRefBehavior,
		/* xcore_setc */ UnknownModRefBehavior,
		/* xcore_setclk */ UnknownModRefBehavior,
		/* xcore_setd */ UnknownModRefBehavior,
		/* xcore_setev */ UnknownModRefBehavior,
		/* xcore_setps */ UnknownModRefBehavior,
		/* xcore_setpsc */ UnknownModRefBehavior,
		/* xcore_setpt */ UnknownModRefBehavior,
		/* xcore_setrdy */ UnknownModRefBehavior,
		/* xcore_setsr */ UnknownModRefBehavior,
		/* xcore_settw */ UnknownModRefBehavior,
		/* xcore_setv */ UnknownModRefBehavior,
		/* xcore_sext */ DoesNotAccessMemory,
		/* xcore_ssync */ UnknownModRefBehavior,
		/* xcore_syncr */ UnknownModRefBehavior,
		/* xcore_testct */ UnknownModRefBehavior,
		/* xcore_testwct */ UnknownModRefBehavior,
		/* xcore_waitevent */ OnlyReadsMemory,
		/* xcore_zext */ DoesNotAccessMemory,
		};

		return static_cast<ModRefBehavior>(IntrinsicModRefBehavior[iid]);
		#endif // GET_INTRINSIC_MODREF_BEHAVIOR

		// Get the LLVM intrinsic that corresponds to a GCC builtin.
		// This is used by the C front-end. The GCC builtin name is passed
		// in as BuiltinName, and a target prefix (e.g. 'ppc') is passed
		// in as TargetPrefix. The result is assigned to 'IntrinsicID'.
		#ifdef GET_LLVM_INTRINSIC_FOR_GCC_BUILTIN
		Intrinsic::ID Intrinsic::getIntrinsicForGCCBuiltin(const char *TargetPrefix
		Str, const char *BuiltinNameStr) {
		StringRef BuiltinName(BuiltinNameStr);
		StringRef TargetPrefix(TargetPrefixStr);

		/* Target Independent Builtins */ {
		switch (BuiltinName.size()) {
		default: break;
		case 14: // 3 strings to match.
		if (BuiltinName.substr(0, 2) != "__")
		break;
		switch (BuiltinName[2]) {
		default: break;
		case 'b': // 1 string to match.
		if (BuiltinName.substr(3, 11) != "uiltin_trap")
		break;
		return Intrinsic::trap; // "__builtin_trap"
		case 'g': // 2 strings to match.
		if (BuiltinName.substr(3, 3) != "nu_")
		break;
		switch (BuiltinName[6]) {
		default: break;
		case 'f': // 1 string to match.
		if (BuiltinName.substr(7, 7) != "2h_ieee")
		break;
		return Intrinsic::convert_to_fp16; // "__gnu_f2h_ieee"
		case 'h': // 1 string to match.
		if (BuiltinName.substr(7, 7) != "2f_ieee")
		break;
		return Intrinsic::convert_from_fp16; // "__gnu_h2f_ieee"
		}
		break;
		}
	break;	break;

	case Intrinsic::ppc_altivec_vmulesb: // llvm.ppc.altivec.vmulesb	case 20: // 2 strings to match.
	case Intrinsic::ppc_altivec_vmuleub: // llvm.ppc.altivec.vmuleub	if (BuiltinName.substr(0, 10) != "__builtin_")
	case Intrinsic::ppc_altivec_vmulosb: // llvm.ppc.altivec.vmulosb	break;
	case Intrinsic::ppc_altivec_vmuloub: // llvm.ppc.altivec.vmuloub	switch (BuiltinName[10]) {
	ResultTy = VectorType::get(IntegerType::get(Context, 16), 8);	default: break;
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));	case 'f': // 1 string to match.
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));	if (BuiltinName.substr(11, 9) != "lt_rounds")
		break;
		return Intrinsic::flt_rounds; // "__builtin_flt_rounds"
		case 's': // 1 string to match.
		if (BuiltinName.substr(11, 9) != "tack_save")
		break;
		return Intrinsic::stacksave; // "__builtin_stack_save"
		}
	break;	break;

	case Intrinsic::ppc_altivec_vpkpx: // llvm.ppc.altivec.vpkpx	case 21: // 16 strings to match.
	case Intrinsic::ppc_altivec_vpkswus: // llvm.ppc.altivec.vpkswus	if (BuiltinName.substr(0, 10) != "__builtin_")
	case Intrinsic::ppc_altivec_vpkuwus: // llvm.ppc.altivec.vpkuwus	break;
	case Intrinsic::x86_sse2_packssdw_128: // llvm.x86.sse2.pac	switch (BuiltinName[10]) {
	kssdw.128	default: break;
	case Intrinsic::x86_sse41_packusdw: // llvm.x86.sse41.packusdw	case 'i': // 14 strings to match.
	ResultTy = VectorType::get(IntegerType::get(Context, 16), 8);	if (BuiltinName.substr(11, 6) != "a32_vp")
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));	break;
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));	switch (BuiltinName[17]) {
		default: break;
		case 'c': // 1 string to match.
		if (BuiltinName.substr(18, 3) != "mov")
		break;
		return Intrinsic::x86_xop_vpcmov; // "__builtin_ia32_vpcmov"
		case 'p': // 1 string to match.
		if (BuiltinName.substr(18, 3) != "erm")
		break;
		return Intrinsic::x86_xop_vpperm; // "__builtin_ia32_vpperm"
		case 'r': // 4 strings to match.
		if (BuiltinName.substr(18, 2) != "ot")
		break;
		switch (BuiltinName[20]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::x86_xop_vprotb; // "__builtin_ia32_vprotb"
		case 'd': // 1 string to match.
		return Intrinsic::x86_xop_vprotd; // "__builtin_ia32_vprotd"
		case 'q': // 1 string to match.
		return Intrinsic::x86_xop_vprotq; // "__builtin_ia32_vprotq"
		case 'w': // 1 string to match.
		return Intrinsic::x86_xop_vprotw; // "__builtin_ia32_vprotw"
		}
		break;
		case 's': // 8 strings to match.
		if (BuiltinName[18] != 'h')
		break;
		switch (BuiltinName[19]) {
		default: break;
		case 'a': // 4 strings to match.
		switch (BuiltinName[20]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::x86_xop_vpshab; // "__builtin_ia32_vpshab"
		case 'd': // 1 string to match.
		return Intrinsic::x86_xop_vpshad; // "__builtin_ia32_vpshad"
		case 'q': // 1 string to match.
		return Intrinsic::x86_xop_vpshaq; // "__builtin_ia32_vpshaq"
		case 'w': // 1 string to match.
		return Intrinsic::x86_xop_vpshaw; // "__builtin_ia32_vpshaw"
		}
		break;
		case 'l': // 4 strings to match.
		switch (BuiltinName[20]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::x86_xop_vpshlb; // "__builtin_ia32_vpshlb"
		case 'd': // 1 string to match.
		return Intrinsic::x86_xop_vpshld; // "__builtin_ia32_vpshld"
		case 'q': // 1 string to match.
		return Intrinsic::x86_xop_vpshlq; // "__builtin_ia32_vpshlq"
		case 'w': // 1 string to match.
		return Intrinsic::x86_xop_vpshlw; // "__builtin_ia32_vpshlw"
		}
		break;
		}
		break;
		}
		break;
		case 'o': // 1 string to match.
		if (BuiltinName.substr(11, 10) != "bject_size")
		break;
		return Intrinsic::objectsize; // "__builtin_object_size"
		case 'u': // 1 string to match.
		if (BuiltinName.substr(11, 10) != "nwind_init")
		break;
		return Intrinsic::eh_unwind_init; // "__builtin_unwind_init"
		}
	break;	break;

	case Intrinsic::x86_sse41_phminposuw: // llvm.x86.sse41.ph	case 22: // 4 strings to match.
	minposuw	if (BuiltinName.substr(0, 20) != "__builtin_ia32_vfrcz")
	case Intrinsic::x86_ssse3_pabs_w_128: // llvm.x86.ssse3.pa	break;
	bs.w.128	switch (BuiltinName[20]) {
	ResultTy = VectorType::get(IntegerType::get(Context, 16), 8);	default: break;
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));	case 'p': // 2 strings to match.
		switch (BuiltinName[21]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_xop_vfrcz_pd; // "__builtin_ia32_vfrczpd"
		case 's': // 1 string to match.
		return Intrinsic::x86_xop_vfrcz_ps; // "__builtin_ia32_vfrczps"
		}
		break;
		case 's': // 2 strings to match.
		switch (BuiltinName[21]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_xop_vfrcz_sd; // "__builtin_ia32_vfrczsd"
		case 's': // 1 string to match.
		return Intrinsic::x86_xop_vfrcz_ss; // "__builtin_ia32_vfrczss"
		}
		break;
		}
	break;	break;

	case Intrinsic::spu_si_ahi: // llvm.spu.si.ahi	case 23: // 37 strings to match.
	case Intrinsic::spu_si_andhi: // llvm.spu.si.andhi	if (BuiltinName.substr(0, 10) != "__builtin_")
	case Intrinsic::spu_si_ceqhi: // llvm.spu.si.ceqhi	break;
	case Intrinsic::spu_si_cgthi: // llvm.spu.si.cgthi	switch (BuiltinName[10]) {
	case Intrinsic::spu_si_clgthi: // llvm.spu.si.clgthi	default: break;
	case Intrinsic::spu_si_fsmbi: // llvm.spu.si.fsmbi	case 'i': // 36 strings to match.
	case Intrinsic::spu_si_orhi: // llvm.spu.si.orhi	if (BuiltinName.substr(11, 6) != "a32_vp")
	case Intrinsic::spu_si_sfhi: // llvm.spu.si.sfhi	break;
	case Intrinsic::spu_si_xorhi: // llvm.spu.si.xorhi	switch (BuiltinName[17]) {
	ResultTy = VectorType::get(IntegerType::get(Context, 16), 8);	default: break;
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));	case 'c': // 24 strings to match.
	ArgTys.push_back(IntegerType::get(Context, 16));	if (BuiltinName.substr(18, 2) != "om")
		break;
		switch (BuiltinName[20]) {
		default: break;
		case 'e': // 4 strings to match.
		if (BuiltinName[21] != 'q')
		break;
		switch (BuiltinName[22]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::x86_xop_vpcomeqb; // "__builtin_ia32_
		vpcomeqb"
		case 'd': // 1 string to match.
		return Intrinsic::x86_xop_vpcomeqd; // "__builtin_ia32_
		vpcomeqd"
		case 'q': // 1 string to match.
		return Intrinsic::x86_xop_vpcomeqq; // "__builtin_ia32_
		vpcomeqq"
		case 'w': // 1 string to match.
		return Intrinsic::x86_xop_vpcomeqw; // "__builtin_ia32_
		vpcomeqw"
		}
		break;
		case 'g': // 8 strings to match.
		switch (BuiltinName[21]) {
		default: break;
		case 'e': // 4 strings to match.
		switch (BuiltinName[22]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::x86_xop_vpcomgeb; // "__builtin_ia32_
		vpcomgeb"
		case 'd': // 1 string to match.
		return Intrinsic::x86_xop_vpcomged; // "__builtin_ia32_
		vpcomged"
		case 'q': // 1 string to match.
		return Intrinsic::x86_xop_vpcomgeq; // "__builtin_ia32_
		vpcomgeq"
		case 'w': // 1 string to match.
		return Intrinsic::x86_xop_vpcomgew; // "__builtin_ia32_
		vpcomgew"
		}
		break;
		case 't': // 4 strings to match.
		switch (BuiltinName[22]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::x86_xop_vpcomgtb; // "__builtin_ia32_
		vpcomgtb"
		case 'd': // 1 string to match.
		return Intrinsic::x86_xop_vpcomgtd; // "__builtin_ia32_
		vpcomgtd"
		case 'q': // 1 string to match.
		return Intrinsic::x86_xop_vpcomgtq; // "__builtin_ia32_
		vpcomgtq"
		case 'w': // 1 string to match.
		return Intrinsic::x86_xop_vpcomgtw; // "__builtin_ia32_
		vpcomgtw"
		}
		break;
		}
		break;
		case 'l': // 8 strings to match.
		switch (BuiltinName[21]) {
		default: break;
		case 'e': // 4 strings to match.
		switch (BuiltinName[22]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::x86_xop_vpcomleb; // "__builtin_ia32_
		vpcomleb"
		case 'd': // 1 string to match.
		return Intrinsic::x86_xop_vpcomled; // "__builtin_ia32_
		vpcomled"
		case 'q': // 1 string to match.
		return Intrinsic::x86_xop_vpcomleq; // "__builtin_ia32_
		vpcomleq"
		case 'w': // 1 string to match.
		return Intrinsic::x86_xop_vpcomlew; // "__builtin_ia32_
		vpcomlew"
		}
		break;
		case 't': // 4 strings to match.
		switch (BuiltinName[22]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::x86_xop_vpcomltb; // "__builtin_ia32_
		vpcomltb"
		case 'd': // 1 string to match.
		return Intrinsic::x86_xop_vpcomltd; // "__builtin_ia32_
		vpcomltd"
		case 'q': // 1 string to match.
		return Intrinsic::x86_xop_vpcomltq; // "__builtin_ia32_
		vpcomltq"
		case 'w': // 1 string to match.
		return Intrinsic::x86_xop_vpcomltw; // "__builtin_ia32_
		vpcomltw"
		}
		break;
		}
		break;
		case 'n': // 4 strings to match.
		if (BuiltinName[21] != 'e')
		break;
		switch (BuiltinName[22]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::x86_xop_vpcomneb; // "__builtin_ia32_
		vpcomneb"
		case 'd': // 1 string to match.
		return Intrinsic::x86_xop_vpcomned; // "__builtin_ia32_
		vpcomned"
		case 'q': // 1 string to match.
		return Intrinsic::x86_xop_vpcomneq; // "__builtin_ia32_
		vpcomneq"
		case 'w': // 1 string to match.
		return Intrinsic::x86_xop_vpcomnew; // "__builtin_ia32_
		vpcomnew"
		}
		break;
		}
		break;
		case 'h': // 9 strings to match.
		switch (BuiltinName[18]) {
		default: break;
		case 'a': // 6 strings to match.
		if (BuiltinName.substr(19, 2) != "dd")
		break;
		switch (BuiltinName[21]) {
		default: break;
		case 'b': // 3 strings to match.
		switch (BuiltinName[22]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_xop_vphaddbd; // "__builtin_ia32_
		vphaddbd"
		case 'q': // 1 string to match.
		return Intrinsic::x86_xop_vphaddbq; // "__builtin_ia32_
		vphaddbq"
		case 'w': // 1 string to match.
		return Intrinsic::x86_xop_vphaddbw; // "__builtin_ia32_
		vphaddbw"
		}
		break;
		case 'd': // 1 string to match.
		if (BuiltinName[22] != 'q')
		break;
		return Intrinsic::x86_xop_vphadddq; // "__builtin_ia32_
		vphadddq"
		case 'w': // 2 strings to match.
		switch (BuiltinName[22]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_xop_vphaddwd; // "__builtin_ia32_
		vphaddwd"
		case 'q': // 1 string to match.
		return Intrinsic::x86_xop_vphaddwq; // "__builtin_ia32_
		vphaddwq"
		}
		break;
		}
		break;
		case 's': // 3 strings to match.
		if (BuiltinName.substr(19, 2) != "ub")
		break;
		switch (BuiltinName[21]) {
		default: break;
		case 'b': // 1 string to match.
		if (BuiltinName[22] != 'w')
		break;
		return Intrinsic::x86_xop_vphsubbw; // "__builtin_ia32_
		vphsubbw"
		case 'd': // 1 string to match.
		if (BuiltinName[22] != 'q')
		break;
		return Intrinsic::x86_xop_vphsubdq; // "__builtin_ia32_
		vphsubdq"
		case 'w': // 1 string to match.
		if (BuiltinName[22] != 'd')
		break;
		return Intrinsic::x86_xop_vphsubwd; // "__builtin_ia32_
		vphsubwd"
		}
		break;
		}
		break;
		case 'm': // 3 strings to match.
		if (BuiltinName.substr(18, 3) != "acs")
		break;
		switch (BuiltinName[21]) {
		default: break;
		case 'd': // 1 string to match.
		if (BuiltinName[22] != 'd')
		break;
		return Intrinsic::x86_xop_vpmacsdd; // "__builtin_ia32_vpmacsdd
		"
		case 'w': // 2 strings to match.
		switch (BuiltinName[22]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_xop_vpmacswd; // "__builtin_ia32_
		vpmacswd"
		case 'w': // 1 string to match.
		return Intrinsic::x86_xop_vpmacsww; // "__builtin_ia32_
		vpmacsww"
		}
		break;
		}
		break;
		}
		break;
		case 's': // 1 string to match.
		if (BuiltinName.substr(11, 12) != "tack_restore")
		break;
		return Intrinsic::stackrestore; // "__builtin_stack_restore"
		}
	break;	break;

	case Intrinsic::spu_si_shlqbi: // llvm.spu.si.shlqbi	case 24: // 36 strings to match.
	case Intrinsic::spu_si_shlqby: // llvm.spu.si.shlqby	if (BuiltinName.substr(0, 17) != "__builtin_ia32_vp")
	case Intrinsic::x86_sse2_pslli_w: // llvm.x86.sse2.pslli.w	break;
	case Intrinsic::x86_sse2_psrai_w: // llvm.x86.sse2.psrai.w	switch (BuiltinName[17]) {
	case Intrinsic::x86_sse2_psrli_w: // llvm.x86.sse2.psrli.w	default: break;
	ResultTy = VectorType::get(IntegerType::get(Context, 16), 8);	case 'c': // 24 strings to match.
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));	if (BuiltinName.substr(18, 2) != "om")
	ArgTys.push_back(IntegerType::get(Context, 32));	break;
		switch (BuiltinName[20]) {
		default: break;
		case 'e': // 4 strings to match.
		if (BuiltinName.substr(21, 2) != "qu")
		break;
		switch (BuiltinName[23]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::x86_xop_vpcomequb; // "__builtin_ia32_vpcomequ
		b"
		case 'd': // 1 string to match.
		return Intrinsic::x86_xop_vpcomequd; // "__builtin_ia32_vpcomequ
		d"
		case 'q': // 1 string to match.
		return Intrinsic::x86_xop_vpcomequq; // "__builtin_ia32_vpcomequ
		q"
		case 'w': // 1 string to match.
		return Intrinsic::x86_xop_vpcomequw; // "__builtin_ia32_vpcomequ
		w"
		}
		break;
		case 'g': // 8 strings to match.
		switch (BuiltinName[21]) {
		default: break;
		case 'e': // 4 strings to match.
		if (BuiltinName[22] != 'u')
		break;
		switch (BuiltinName[23]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::x86_xop_vpcomgeub; // "__builtin_ia32_
		vpcomgeub"
		case 'd': // 1 string to match.
		return Intrinsic::x86_xop_vpcomgeud; // "__builtin_ia32_
		vpcomgeud"
		case 'q': // 1 string to match.
		return Intrinsic::x86_xop_vpcomgeuq; // "__builtin_ia32_
		vpcomgeuq"
		case 'w': // 1 string to match.
		return Intrinsic::x86_xop_vpcomgeuw; // "__builtin_ia32_
		vpcomgeuw"
		}
		break;
		case 't': // 4 strings to match.
		if (BuiltinName[22] != 'u')
		break;
		switch (BuiltinName[23]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::x86_xop_vpcomgtub; // "__builtin_ia32_
		vpcomgtub"
		case 'd': // 1 string to match.
		return Intrinsic::x86_xop_vpcomgtud; // "__builtin_ia32_
		vpcomgtud"
		case 'q': // 1 string to match.
		return Intrinsic::x86_xop_vpcomgtuq; // "__builtin_ia32_
		vpcomgtuq"
		case 'w': // 1 string to match.
		return Intrinsic::x86_xop_vpcomgtuw; // "__builtin_ia32_
		vpcomgtuw"
		}
		break;
		}
		break;
		case 'l': // 8 strings to match.
		switch (BuiltinName[21]) {
		default: break;
		case 'e': // 4 strings to match.
		if (BuiltinName[22] != 'u')
		break;
		switch (BuiltinName[23]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::x86_xop_vpcomleub; // "__builtin_ia32_
		vpcomleub"
		case 'd': // 1 string to match.
		return Intrinsic::x86_xop_vpcomleud; // "__builtin_ia32_
		vpcomleud"
		case 'q': // 1 string to match.
		return Intrinsic::x86_xop_vpcomleuq; // "__builtin_ia32_
		vpcomleuq"
		case 'w': // 1 string to match.
		return Intrinsic::x86_xop_vpcomleuw; // "__builtin_ia32_
		vpcomleuw"
		}
		break;
		case 't': // 4 strings to match.
		if (BuiltinName[22] != 'u')
		break;
		switch (BuiltinName[23]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::x86_xop_vpcomltub; // "__builtin_ia32_
		vpcomltub"
		case 'd': // 1 string to match.
		return Intrinsic::x86_xop_vpcomltud; // "__builtin_ia32_
		vpcomltud"
		case 'q': // 1 string to match.
		return Intrinsic::x86_xop_vpcomltuq; // "__builtin_ia32_
		vpcomltuq"
		case 'w': // 1 string to match.
		return Intrinsic::x86_xop_vpcomltuw; // "__builtin_ia32_
		vpcomltuw"
		}
		break;
		}
		break;
		case 'n': // 4 strings to match.
		if (BuiltinName.substr(21, 2) != "eu")
		break;
		switch (BuiltinName[23]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::x86_xop_vpcomneub; // "__builtin_ia32_vpcomneu
		b"
		case 'd': // 1 string to match.
		return Intrinsic::x86_xop_vpcomneud; // "__builtin_ia32_vpcomneu
		d"
		case 'q': // 1 string to match.
		return Intrinsic::x86_xop_vpcomneuq; // "__builtin_ia32_vpcomneu
		q"
		case 'w': // 1 string to match.
		return Intrinsic::x86_xop_vpcomneuw; // "__builtin_ia32_vpcomneu
		w"
		}
		break;
		}
		break;
		case 'h': // 6 strings to match.
		if (BuiltinName.substr(18, 4) != "addu")
		break;
		switch (BuiltinName[22]) {
		default: break;
		case 'b': // 3 strings to match.
		switch (BuiltinName[23]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_xop_vphaddubd; // "__builtin_ia32_vphaddub
		d"
		case 'q': // 1 string to match.
		return Intrinsic::x86_xop_vphaddubq; // "__builtin_ia32_vphaddub
		q"
		case 'w': // 1 string to match.
		return Intrinsic::x86_xop_vphaddubw; // "__builtin_ia32_vphaddub
		w"
		}
		break;
		case 'd': // 1 string to match.
		if (BuiltinName[23] != 'q')
		break;
		return Intrinsic::x86_xop_vphaddudq; // "__builtin_ia32_vphaddud
		q"
		case 'w': // 2 strings to match.
		switch (BuiltinName[23]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_xop_vphadduwd; // "__builtin_ia32_vphadduw
		d"
		case 'q': // 1 string to match.
		return Intrinsic::x86_xop_vphadduwq; // "__builtin_ia32_vphadduw
		q"
		}
		break;
		}
		break;
		case 'm': // 6 strings to match.
		if (BuiltinName[18] != 'a')
		break;
		switch (BuiltinName[19]) {
		default: break;
		case 'c': // 5 strings to match.
		if (BuiltinName[20] != 's')
		break;
		switch (BuiltinName[21]) {
		default: break;
		case 'd': // 2 strings to match.
		if (BuiltinName[22] != 'q')
		break;
		switch (BuiltinName[23]) {
		default: break;
		case 'h': // 1 string to match.
		return Intrinsic::x86_xop_vpmacsdqh; // "__builtin_ia32_
		vpmacsdqh"
		case 'l': // 1 string to match.
		return Intrinsic::x86_xop_vpmacsdql; // "__builtin_ia32_
		vpmacsdql"
		}
		break;
		case 's': // 3 strings to match.
		switch (BuiltinName[22]) {
		default: break;
		case 'd': // 1 string to match.
		if (BuiltinName[23] != 'd')
		break;
		return Intrinsic::x86_xop_vpmacssdd; // "__builtin_ia32_
		vpmacssdd"
		case 'w': // 2 strings to match.
		switch (BuiltinName[23]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_xop_vpmacsswd; // "__builtin_ia32_
		vpmacsswd"
		case 'w': // 1 string to match.
		return Intrinsic::x86_xop_vpmacssww; // "__builtin_ia32_
		vpmacssww"
		}
		break;
		}
		break;
		}
		break;
		case 'd': // 1 string to match.
		if (BuiltinName.substr(20, 4) != "cswd")
		break;
		return Intrinsic::x86_xop_vpmadcswd; // "__builtin_ia32_vpmadcsw
		d"
		}
		break;
		}
	break;	break;

	case Intrinsic::ppc_altivec_vaddshs: // llvm.ppc.altivec.vaddshs	case 25: // 13 strings to match.
	case Intrinsic::ppc_altivec_vadduhs: // llvm.ppc.altivec.vadduhs	if (BuiltinName.substr(0, 11) != "__builtin_i")
	case Intrinsic::ppc_altivec_vavgsh: // llvm.ppc.altivec.vavgsh	break;
	case Intrinsic::ppc_altivec_vavguh: // llvm.ppc.altivec.vavguh	switch (BuiltinName[11]) {
	case Intrinsic::ppc_altivec_vcmpequh: // llvm.ppc.altivec.	default: break;
	vcmpequh	case 'a': // 12 strings to match.
	case Intrinsic::ppc_altivec_vcmpgtsh: // llvm.ppc.altivec.	if (BuiltinName.substr(12, 4) != "32_v")
	vcmpgtsh	break;
	case Intrinsic::ppc_altivec_vcmpgtuh: // llvm.ppc.altivec.	switch (BuiltinName[16]) {
	vcmpgtuh	default: break;
	case Intrinsic::ppc_altivec_vmaxsh: // llvm.ppc.altivec.vmaxsh	case 'f': // 2 strings to match.
	case Intrinsic::ppc_altivec_vmaxuh: // llvm.ppc.altivec.vmaxuh	if (BuiltinName.substr(17, 4) != "rczp")
	case Intrinsic::ppc_altivec_vminsh: // llvm.ppc.altivec.vminsh	break;
	case Intrinsic::ppc_altivec_vminuh: // llvm.ppc.altivec.vminuh	switch (BuiltinName[21]) {
	case Intrinsic::ppc_altivec_vrlh: // llvm.ppc.altivec.vrlh	default: break;
	case Intrinsic::ppc_altivec_vslh: // llvm.ppc.altivec.vslh	case 'd': // 1 string to match.
	case Intrinsic::ppc_altivec_vsrah: // llvm.ppc.altivec.vsrah	if (BuiltinName.substr(22, 3) != "256")
	case Intrinsic::ppc_altivec_vsrh: // llvm.ppc.altivec.vsrh	break;
	case Intrinsic::ppc_altivec_vsubshs: // llvm.ppc.altivec.vsubshs	return Intrinsic::x86_xop_vfrcz_pd_256; // "__builtin_ia32_
	case Intrinsic::ppc_altivec_vsubuhs: // llvm.ppc.altivec.vsubuhs	vfrczpd256"
	case Intrinsic::spu_si_ah: // llvm.spu.si.ah	case 's': // 1 string to match.
	case Intrinsic::spu_si_ceqh: // llvm.spu.si.ceqh	if (BuiltinName.substr(22, 3) != "256")
	case Intrinsic::spu_si_cgth: // llvm.spu.si.cgth	break;
	case Intrinsic::spu_si_clgth: // llvm.spu.si.clgth	return Intrinsic::x86_xop_vfrcz_ps_256; // "__builtin_ia32_
	case Intrinsic::spu_si_sfh: // llvm.spu.si.sfh	vfrczps256"
	case Intrinsic::x86_sse2_padds_w: // llvm.x86.sse2.padds.w	}
	case Intrinsic::x86_sse2_paddus_w: // llvm.x86.sse2.paddus.w	break;
	case Intrinsic::x86_sse2_pavg_w: // llvm.x86.sse2.pavg.w	case 'p': // 10 strings to match.
	case Intrinsic::x86_sse2_pcmpeq_w: // llvm.x86.sse2.pcmpeq.w	switch (BuiltinName[17]) {
	case Intrinsic::x86_sse2_pcmpgt_w: // llvm.x86.sse2.pcmpgt.w	default: break;
	case Intrinsic::x86_sse2_pmaxs_w: // llvm.x86.sse2.pmaxs.w	case 'c': // 5 strings to match.
	case Intrinsic::x86_sse2_pmins_w: // llvm.x86.sse2.pmins.w	switch (BuiltinName[18]) {
	case Intrinsic::x86_sse2_pmulh_w: // llvm.x86.sse2.pmulh.w	default: break;
	case Intrinsic::x86_sse2_pmulhu_w: // llvm.x86.sse2.pmulhu.w	case 'm': // 1 string to match.
	case Intrinsic::x86_sse2_psll_w: // llvm.x86.sse2.psll.w	if (BuiltinName.substr(19, 6) != "ov_256")
	case Intrinsic::x86_sse2_psra_w: // llvm.x86.sse2.psra.w	break;
	case Intrinsic::x86_sse2_psrl_w: // llvm.x86.sse2.psrl.w	return Intrinsic::x86_xop_vpcmov_256; // "__builtin_ia32_
	case Intrinsic::x86_sse2_psubs_w: // llvm.x86.sse2.psubs.w	vpcmov_256"
	case Intrinsic::x86_sse2_psubus_w: // llvm.x86.sse2.psubus.w	case 'o': // 4 strings to match.
	case Intrinsic::x86_sse41_pmaxuw: // llvm.x86.sse41.pmaxuw	if (BuiltinName.substr(19, 5) != "mtrue")
	case Intrinsic::x86_sse41_pminuw: // llvm.x86.sse41.pminuw	break;
	case Intrinsic::x86_ssse3_phadd_w_128: // llvm.x86.ssse3.ph	switch (BuiltinName[24]) {
	add.w.128	default: break;
	case Intrinsic::x86_ssse3_phsub_sw_128: // llvm.x86.ssse3.ph	case 'b': // 1 string to match.
	sub.sw.128	return Intrinsic::x86_xop_vpcomtrueb; // "__builtin_ia32_
	case Intrinsic::x86_ssse3_phsub_w_128: // llvm.x86.ssse3.ph	vpcomtrueb"
	sub.w.128	case 'd': // 1 string to match.
	case Intrinsic::x86_ssse3_pmadd_ub_sw_128: // llvm.x86.ssse3.pm	return Intrinsic::x86_xop_vpcomtrued; // "__builtin_ia32_
	add.ub.sw.128	vpcomtrued"
	case Intrinsic::x86_ssse3_pmul_hr_sw_128: // llvm.x86.ssse3.pm	case 'q': // 1 string to match.
	ul.hr.sw.128	return Intrinsic::x86_xop_vpcomtrueq; // "__builtin_ia32_
	case Intrinsic::x86_ssse3_psign_w_128: // llvm.x86.ssse3.ps	vpcomtrueq"
	ign.w.128	case 'w': // 1 string to match.
	ResultTy = VectorType::get(IntegerType::get(Context, 16), 8);	return Intrinsic::x86_xop_vpcomtruew; // "__builtin_ia32_
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));	vpcomtruew"
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));	}
		break;
		}
		break;
		case 'e': // 2 strings to match.
		if (BuiltinName.substr(18, 6) != "rmil2p")
		break;
		switch (BuiltinName[24]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_xop_vpermil2pd; // "__builtin_ia32_
		vpermil2pd"
		case 's': // 1 string to match.
		return Intrinsic::x86_xop_vpermil2ps; // "__builtin_ia32_
		vpermil2ps"
		}
		break;
		case 'm': // 3 strings to match.
		if (BuiltinName[18] != 'a')
		break;
		switch (BuiltinName[19]) {
		default: break;
		case 'c': // 2 strings to match.
		if (BuiltinName.substr(20, 4) != "ssdq")
		break;
		switch (BuiltinName[24]) {
		default: break;
		case 'h': // 1 string to match.
		return Intrinsic::x86_xop_vpmacssdqh; // "__builtin_ia32_
		vpmacssdqh"
		case 'l': // 1 string to match.
		return Intrinsic::x86_xop_vpmacssdql; // "__builtin_ia32_
		vpmacssdql"
		}
		break;
		case 'd': // 1 string to match.
		if (BuiltinName.substr(20, 5) != "csswd")
		break;
		return Intrinsic::x86_xop_vpmadcsswd; // "__builtin_ia32_
		vpmadcsswd"
		}
		break;
		}
		break;
		}
		break;
		case 'n': // 1 string to match.
		if (BuiltinName.substr(12, 13) != "it_trampoline")
		break;
		return Intrinsic::init_trampoline; // "__builtin_init_trampoli
		ne"
		}
	break;	break;

	case Intrinsic::x86_sse41_pblendw: // llvm.x86.sse41.pblendw	case 26: // 8 strings to match.
	ResultTy = VectorType::get(IntegerType::get(Context, 16), 8);	if (BuiltinName.substr(0, 20) != "__builtin_ia32_vpcom")
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));	break;
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));	switch (BuiltinName[20]) {
	ArgTys.push_back(IntegerType::get(Context, 32));	default: break;
		case 'f': // 4 strings to match.
		if (BuiltinName.substr(21, 4) != "alse")
		break;
		switch (BuiltinName[25]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::x86_xop_vpcomfalseb; // "__builtin_ia32_vpcomfal
		seb"
		case 'd': // 1 string to match.
		return Intrinsic::x86_xop_vpcomfalsed; // "__builtin_ia32_vpcomfal
		sed"
		case 'q': // 1 string to match.
		return Intrinsic::x86_xop_vpcomfalseq; // "__builtin_ia32_vpcomfal
		seq"
		case 'w': // 1 string to match.
		return Intrinsic::x86_xop_vpcomfalsew; // "__builtin_ia32_vpcomfal
		sew"
		}
		break;
		case 't': // 4 strings to match.
		if (BuiltinName.substr(21, 4) != "rueu")
		break;
		switch (BuiltinName[25]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::x86_xop_vpcomtrueub; // "__builtin_ia32_vpcomtru
		eub"
		case 'd': // 1 string to match.
		return Intrinsic::x86_xop_vpcomtrueud; // "__builtin_ia32_vpcomtru
		eud"
		case 'q': // 1 string to match.
		return Intrinsic::x86_xop_vpcomtrueuq; // "__builtin_ia32_vpcomtru
		euq"
		case 'w': // 1 string to match.
		return Intrinsic::x86_xop_vpcomtrueuw; // "__builtin_ia32_vpcomtru
		euw"
		}
		break;
		}
	break;	break;

	case Intrinsic::ppc_altivec_vmhaddshs: // llvm.ppc.altivec.	case 27: // 5 strings to match.
	vmhaddshs	if (BuiltinName.substr(0, 10) != "__builtin_")
	case Intrinsic::ppc_altivec_vmhraddshs: // llvm.ppc.altivec.	break;
	vmhraddshs	switch (BuiltinName[10]) {
	case Intrinsic::ppc_altivec_vmladduhm: // llvm.ppc.altivec.	default: break;
	vmladduhm	case 'a': // 1 string to match.
	ResultTy = VectorType::get(IntegerType::get(Context, 16), 8);	if (BuiltinName.substr(11, 16) != "djust_trampoline")
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));	break;
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));	return Intrinsic::adjust_trampoline; // "__builtin_adjust_trampo
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));	line"
		case 'i': // 4 strings to match.
		if (BuiltinName.substr(11, 15) != "a32_vpcomfalseu")
		break;
		switch (BuiltinName[26]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::x86_xop_vpcomfalseub; // "__builtin_ia32_
		vpcomfalseub"
		case 'd': // 1 string to match.
		return Intrinsic::x86_xop_vpcomfalseud; // "__builtin_ia32_
		vpcomfalseud"
		case 'q': // 1 string to match.
		return Intrinsic::x86_xop_vpcomfalseuq; // "__builtin_ia32_
		vpcomfalseuq"
		case 'w': // 1 string to match.
		return Intrinsic::x86_xop_vpcomfalseuw; // "__builtin_ia32_
		vpcomfalseuw"
		}
		break;
		}
	break;	break;

	case Intrinsic::x86_avx_cvt_ps2dq_256: // llvm.x86.avx.cvt.	case 28: // 2 strings to match.
	ps2dq.256	if (BuiltinName.substr(0, 24) != "__builtin_ia32_vpermil2p")
	case Intrinsic::x86_avx_cvtt_ps2dq_256: // llvm.x86.avx.cvtt	break;
	.ps2dq.256	switch (BuiltinName[24]) {
	ResultTy = VectorType::get(IntegerType::get(Context, 32), 8);	default: break;
	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 8));	case 'd': // 1 string to match.
		if (BuiltinName.substr(25, 3) != "256")
		break;
		return Intrinsic::x86_xop_vpermil2pd_256; // "__builtin_ia32_
		vpermil2pd256"
		case 's': // 1 string to match.
		if (BuiltinName.substr(25, 3) != "256")
		break;
		return Intrinsic::x86_xop_vpermil2ps_256; // "__builtin_ia32_
		vpermil2ps256"
		}
	break;	break;

	case Intrinsic::x86_avx_vinsertf128_si_256: // llvm.x86.avx.vins	}
	ertf128.si.256	}
	ResultTy = VectorType::get(IntegerType::get(Context, 32), 8);	if (TargetPrefix == "arm") {
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 8));	switch (BuiltinName.size()) {
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));	default: break;
	ArgTys.push_back(IntegerType::get(Context, 8));	case 17: // 3 strings to match.
		if (BuiltinName.substr(0, 14) != "__builtin_arm_")
		break;
		switch (BuiltinName[14]) {
		default: break;
		case 'c': // 1 string to match.
		if (BuiltinName.substr(15, 2) != "dp")
		break;
		return Intrinsic::arm_cdp; // "__builtin_arm_cdp"
		case 'm': // 2 strings to match.
		switch (BuiltinName[15]) {
		default: break;
		case 'c': // 1 string to match.
		if (BuiltinName[16] != 'r')
		break;
		return Intrinsic::arm_mcr; // "__builtin_arm_mcr"
		case 'r': // 1 string to match.
		if (BuiltinName[16] != 'c')
		break;
		return Intrinsic::arm_mrc; // "__builtin_arm_mrc"
		}
		break;
		}
	break;	break;

	case Intrinsic::x86_avx_vperm2f128_si_256: // llvm.x86.avx.vper	case 18: // 8 strings to match.
	m2f128.si.256	if (BuiltinName.substr(0, 14) != "__builtin_arm_")
	ResultTy = VectorType::get(IntegerType::get(Context, 32), 8);	break;
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 8));	switch (BuiltinName[14]) {
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 8));	default: break;
	ArgTys.push_back(IntegerType::get(Context, 8));	case 'c': // 1 string to match.
		if (BuiltinName.substr(15, 3) != "dp2")
		break;
		return Intrinsic::arm_cdp2; // "__builtin_arm_cdp2"
		case 'm': // 3 strings to match.
		switch (BuiltinName[15]) {
		default: break;
		case 'c': // 2 strings to match.
		if (BuiltinName[16] != 'r')
		break;
		switch (BuiltinName[17]) {
		default: break;
		case '2': // 1 string to match.
		return Intrinsic::arm_mcr2; // "__builtin_arm_mcr2"
		case 'r': // 1 string to match.
		return Intrinsic::arm_mcrr; // "__builtin_arm_mcrr"
		}
		break;
		case 'r': // 1 string to match.
		if (BuiltinName.substr(16, 2) != "c2")
		break;
		return Intrinsic::arm_mrc2; // "__builtin_arm_mrc2"
		}
		break;
		case 'q': // 2 strings to match.
		switch (BuiltinName[15]) {
		default: break;
		case 'a': // 1 string to match.
		if (BuiltinName.substr(16, 2) != "dd")
		break;
		return Intrinsic::arm_qadd; // "__builtin_arm_qadd"
		case 's': // 1 string to match.
		if (BuiltinName.substr(16, 2) != "ub")
		break;
		return Intrinsic::arm_qsub; // "__builtin_arm_qsub"
		}
		break;
		case 's': // 1 string to match.
		if (BuiltinName.substr(15, 3) != "sat")
		break;
		return Intrinsic::arm_ssat; // "__builtin_arm_ssat"
		case 'u': // 1 string to match.
		if (BuiltinName.substr(15, 3) != "sat")
		break;
		return Intrinsic::arm_usat; // "__builtin_arm_usat"
		}
	break;	break;

	case Intrinsic::arm_neon_vtbl1: // llvm.arm.neon.vtbl1	case 19: // 1 string to match.
	ResultTy = VectorType::get(IntegerType::get(Context, 8), 8);	if (BuiltinName.substr(0, 19) != "__builtin_arm_mcrr2")
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));	break;
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));	return Intrinsic::arm_mcrr2; // "__builtin_arm_mcrr2"
		case 23: // 2 strings to match.
		if (BuiltinName.substr(0, 14) != "__builtin_arm_")
		break;
		switch (BuiltinName[14]) {
		default: break;
		case 'g': // 1 string to match.
		if (BuiltinName.substr(15, 8) != "et_fpscr")
		break;
		return Intrinsic::arm_get_fpscr; // "__builtin_arm_get_fpscr"
		case 's': // 1 string to match.
		if (BuiltinName.substr(15, 8) != "et_fpscr")
		break;
		return Intrinsic::arm_set_fpscr; // "__builtin_arm_set_fpscr"
		}
	break;	break;

	case Intrinsic::arm_neon_vtbl2: // llvm.arm.neon.vtbl2	case 24: // 1 string to match.
	case Intrinsic::arm_neon_vtbx1: // llvm.arm.neon.vtbx1	if (BuiltinName.substr(0, 24) != "__builtin_thread_pointer")
	ResultTy = VectorType::get(IntegerType::get(Context, 8), 8);	break;
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));	return Intrinsic::arm_thread_pointer; // "__builtin_thread_pointe
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));	r"
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));	}
		}
		if (TargetPrefix == "hexagon") {
		switch (BuiltinName.size()) {
		default: break;
		case 23: // 2 strings to match.
		if (BuiltinName.substr(0, 18) != "__builtin_HEXAGON.")
		break;
		switch (BuiltinName[18]) {
		default: break;
		case 'A': // 1 string to match.
		if (BuiltinName.substr(19, 4) != "2.or")
		break;
		return Intrinsic::hexagon_A2_or; // "__builtin_HEXAGON.A2.or"
		case 'C': // 1 string to match.
		if (BuiltinName.substr(19, 4) != "2.or")
		break;
		return Intrinsic::hexagon_C2_or; // "__builtin_HEXAGON.C2.or"
		}
	break;	break;

	case Intrinsic::arm_neon_vtbl3: // llvm.arm.neon.vtbl3	case 24: // 23 strings to match.
	case Intrinsic::arm_neon_vtbx2: // llvm.arm.neon.vtbx2	if (BuiltinName.substr(0, 18) != "__builtin_HEXAGON.")
	ResultTy = VectorType::get(IntegerType::get(Context, 8), 8);	break;
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));	switch (BuiltinName[18]) {
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));	default: break;
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));	case 'A': // 13 strings to match.
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));	switch (BuiltinName[19]) {
		default: break;
		case '2': // 12 strings to match.
		if (BuiltinName[20] != '.')
		break;
		switch (BuiltinName[21]) {
		default: break;
		case 'a': // 3 strings to match.
		switch (BuiltinName[22]) {
		default: break;
		case 'b': // 1 string to match.
		if (BuiltinName[23] != 's')
		break;
		return Intrinsic::hexagon_A2_abs; // "__builtin_HEXAGON.A2.ab
		s"
		case 'd': // 1 string to match.
		if (BuiltinName[23] != 'd')
		break;
		return Intrinsic::hexagon_A2_add; // "__builtin_HEXAGON.A2.ad
		d"
		case 'n': // 1 string to match.
		if (BuiltinName[23] != 'd')
		break;
		return Intrinsic::hexagon_A2_and; // "__builtin_HEXAGON.A2.an
		d"
		}
		break;
		case 'm': // 2 strings to match.
		switch (BuiltinName[22]) {
		default: break;
		case 'a': // 1 string to match.
		if (BuiltinName[23] != 'x')
		break;
		return Intrinsic::hexagon_A2_max; // "__builtin_HEXAGON.A2.ma
		x"
		case 'i': // 1 string to match.
		if (BuiltinName[23] != 'n')
		break;
		return Intrinsic::hexagon_A2_min; // "__builtin_HEXAGON.A2.mi
		n"
		}
		break;
		case 'n': // 2 strings to match.
		switch (BuiltinName[22]) {
		default: break;
		case 'e': // 1 string to match.
		if (BuiltinName[23] != 'g')
		break;
		return Intrinsic::hexagon_A2_neg; // "__builtin_HEXAGON.A2.ne
		g"
		case 'o': // 1 string to match.
		if (BuiltinName[23] != 't')
		break;
		return Intrinsic::hexagon_A2_not; // "__builtin_HEXAGON.A2.no
		t"
		}
		break;
		case 'o': // 1 string to match.
		if (BuiltinName.substr(22, 2) != "rp")
		break;
		return Intrinsic::hexagon_A2_orp; // "__builtin_HEXAGON.A2.or
		p"
		case 's': // 2 strings to match.
		switch (BuiltinName[22]) {
		default: break;
		case 'a': // 1 string to match.
		if (BuiltinName[23] != 't')
		break;
		return Intrinsic::hexagon_A2_sat; // "__builtin_HEXAGON.A2.sa
		t"
		case 'u': // 1 string to match.
		if (BuiltinName[23] != 'b')
		break;
		return Intrinsic::hexagon_A2_sub; // "__builtin_HEXAGON.A2.su
		b"
		}
		break;
		case 't': // 1 string to match.
		if (BuiltinName.substr(22, 2) != "fr")
		break;
		return Intrinsic::hexagon_A2_tfr; // "__builtin_HEXAGON.A2.tf
		r"
		case 'x': // 1 string to match.
		if (BuiltinName.substr(22, 2) != "or")
		break;
		return Intrinsic::hexagon_A2_xor; // "__builtin_HEXAGON.A2.xo
		r"
		}
		break;
		case '4': // 1 string to match.
		if (BuiltinName.substr(20, 4) != ".orn")
		break;
		return Intrinsic::hexagon_A4_orn; // "__builtin_HEXAGON.A4.or
		n"
		}
		break;
		case 'C': // 5 strings to match.
		if (BuiltinName.substr(19, 2) != "2.")
		break;
		switch (BuiltinName[21]) {
		default: break;
		case 'a': // 1 string to match.
		if (BuiltinName.substr(22, 2) != "nd")
		break;
		return Intrinsic::hexagon_C2_and; // "__builtin_HEXAGON.C2.an
		d"
		case 'm': // 1 string to match.
		if (BuiltinName.substr(22, 2) != "ux")
		break;
		return Intrinsic::hexagon_C2_mux; // "__builtin_HEXAGON.C2.mu
		x"
		case 'n': // 1 string to match.
		if (BuiltinName.substr(22, 2) != "ot")
		break;
		return Intrinsic::hexagon_C2_not; // "__builtin_HEXAGON.C2.no
		t"
		case 'o': // 1 string to match.
		if (BuiltinName.substr(22, 2) != "rn")
		break;
		return Intrinsic::hexagon_C2_orn; // "__builtin_HEXAGON.C2.or
		n"
		case 'x': // 1 string to match.
		if (BuiltinName.substr(22, 2) != "or")
		break;
		return Intrinsic::hexagon_C2_xor; // "__builtin_HEXAGON.C2.xo
		r"
		}
		break;
		case 'S': // 5 strings to match.
		if (BuiltinName.substr(19, 3) != "2.c")
		break;
		switch (BuiltinName[22]) {
		default: break;
		case 'l': // 3 strings to match.
		switch (BuiltinName[23]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_S2_cl0; // "__builtin_HEXAGON.S2.cl
		0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_S2_cl1; // "__builtin_HEXAGON.S2.cl
		1"
		case 'b': // 1 string to match.
		return Intrinsic::hexagon_S2_clb; // "__builtin_HEXAGON.S2.cl
		b"
		}
		break;
		case 't': // 2 strings to match.
		switch (BuiltinName[23]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_S2_ct0; // "__builtin_HEXAGON.S2.ct
		0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_S2_ct1; // "__builtin_HEXAGON.S2.ct
		1"
		}
		break;
		}
		break;
		}
	break;	break;

	case Intrinsic::arm_neon_vtbl4: // llvm.arm.neon.vtbl4	case 25: // 40 strings to match.
	case Intrinsic::arm_neon_vtbx3: // llvm.arm.neon.vtbx3	if (BuiltinName.substr(0, 18) != "__builtin_HEXAGON.")
	ResultTy = VectorType::get(IntegerType::get(Context, 8), 8);	break;
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));	switch (BuiltinName[18]) {
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));	default: break;
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));	case 'A': // 26 strings to match.
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));	switch (BuiltinName[19]) {
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));	default: break;
		case '2': // 24 strings to match.
		if (BuiltinName[20] != '.')
		break;
		switch (BuiltinName[21]) {
		default: break;
		case 'a': // 6 strings to match.
		switch (BuiltinName[22]) {
		default: break;
		case 'b': // 1 string to match.
		if (BuiltinName.substr(23, 2) != "sp")
		break;
		return Intrinsic::hexagon_A2_absp; // "__builtin_HEXAGON.A2.ab
		sp"
		case 'd': // 2 strings to match.
		if (BuiltinName[23] != 'd')
		break;
		switch (BuiltinName[24]) {
		default: break;
		case 'i': // 1 string to match.
		return Intrinsic::hexagon_A2_addi; // "__builtin_HEXAG
		ON.A2.addi"
		case 'p': // 1 string to match.
		return Intrinsic::hexagon_A2_addp; // "__builtin_HEXAG
		ON.A2.addp"
		}
		break;
		case 'n': // 1 string to match.
		if (BuiltinName.substr(23, 2) != "dp")
		break;
		return Intrinsic::hexagon_A2_andp; // "__builtin_HEXAGON.A2.an
		dp"
		case 's': // 2 strings to match.
		switch (BuiltinName[23]) {
		default: break;
		case 'l': // 1 string to match.
		if (BuiltinName[24] != 'h')
		break;
		return Intrinsic::hexagon_A2_aslh; // "__builtin_HEXAG
		ON.A2.aslh"
		case 'r': // 1 string to match.
		if (BuiltinName[24] != 'h')
		break;
		return Intrinsic::hexagon_A2_asrh; // "__builtin_HEXAG
		ON.A2.asrh"
		}
		break;
		}
		break;
		case 'm': // 4 strings to match.
		switch (BuiltinName[22]) {
		default: break;
		case 'a': // 2 strings to match.
		if (BuiltinName[23] != 'x')
		break;
		switch (BuiltinName[24]) {
		default: break;
		case 'p': // 1 string to match.
		return Intrinsic::hexagon_A2_maxp; // "__builtin_HEXAG
		ON.A2.maxp"
		case 'u': // 1 string to match.
		return Intrinsic::hexagon_A2_maxu; // "__builtin_HEXAG
		ON.A2.maxu"
		}
		break;
		case 'i': // 2 strings to match.
		if (BuiltinName[23] != 'n')
		break;
		switch (BuiltinName[24]) {
		default: break;
		case 'p': // 1 string to match.
		return Intrinsic::hexagon_A2_minp; // "__builtin_HEXAG
		ON.A2.minp"
		case 'u': // 1 string to match.
		return Intrinsic::hexagon_A2_minu; // "__builtin_HEXAG
		ON.A2.minu"
		}
		break;
		}
		break;
		case 'n': // 2 strings to match.
		switch (BuiltinName[22]) {
		default: break;
		case 'e': // 1 string to match.
		if (BuiltinName.substr(23, 2) != "gp")
		break;
		return Intrinsic::hexagon_A2_negp; // "__builtin_HEXAGON.A2.ne
		gp"
		case 'o': // 1 string to match.
		if (BuiltinName.substr(23, 2) != "tp")
		break;
		return Intrinsic::hexagon_A2_notp; // "__builtin_HEXAGON.A2.no
		tp"
		}
		break;
		case 'o': // 1 string to match.
		if (BuiltinName.substr(22, 3) != "rir")
		break;
		return Intrinsic::hexagon_A2_orir; // "__builtin_HEXAGON.A2.or
		ir"
		case 's': // 7 strings to match.
		switch (BuiltinName[22]) {
		default: break;
		case 'a': // 2 strings to match.
		if (BuiltinName[23] != 't')
		break;
		switch (BuiltinName[24]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::hexagon_A2_satb; // "__builtin_HEXAG
		ON.A2.satb"
		case 'h': // 1 string to match.
		return Intrinsic::hexagon_A2_sath; // "__builtin_HEXAG
		ON.A2.sath"
		}
		break;
		case 'u': // 1 string to match.
		if (BuiltinName.substr(23, 2) != "bp")
		break;
		return Intrinsic::hexagon_A2_subp; // "__builtin_HEXAGON.A2.su
		bp"
		case 'w': // 1 string to match.
		if (BuiltinName.substr(23, 2) != "iz")
		break;
		return Intrinsic::hexagon_A2_swiz; // "__builtin_HEXAGON.A2.sw
		iz"
		case 'x': // 3 strings to match.
		if (BuiltinName[23] != 't')
		break;
		switch (BuiltinName[24]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::hexagon_A2_sxtb; // "__builtin_HEXAG
		ON.A2.sxtb"
		case 'h': // 1 string to match.
		return Intrinsic::hexagon_A2_sxth; // "__builtin_HEXAG
		ON.A2.sxth"
		case 'w': // 1 string to match.
		return Intrinsic::hexagon_A2_sxtw; // "__builtin_HEXAG
		ON.A2.sxtw"
		}
		break;
		}
		break;
		case 't': // 1 string to match.
		if (BuiltinName.substr(22, 3) != "frp")
		break;
		return Intrinsic::hexagon_A2_tfrp; // "__builtin_HEXAGON.A2.tf
		rp"
		case 'x': // 1 string to match.
		if (BuiltinName.substr(22, 3) != "orp")
		break;
		return Intrinsic::hexagon_A2_xorp; // "__builtin_HEXAGON.A2.xo
		rp"
		case 'z': // 2 strings to match.
		if (BuiltinName.substr(22, 2) != "xt")
		break;
		switch (BuiltinName[24]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::hexagon_A2_zxtb; // "__builtin_HEXAGON.A2.zx
		tb"
		case 'h': // 1 string to match.
		return Intrinsic::hexagon_A2_zxth; // "__builtin_HEXAGON.A2.zx
		th"
		}
		break;
		}
		break;
		case '4': // 2 strings to match.
		if (BuiltinName[20] != '.')
		break;
		switch (BuiltinName[21]) {
		default: break;
		case 'a': // 1 string to match.
		if (BuiltinName.substr(22, 3) != "ndn")
		break;
		return Intrinsic::hexagon_A4_andn; // "__builtin_HEXAGON.A4.an
		dn"
		case 'o': // 1 string to match.
		if (BuiltinName.substr(22, 3) != "rnp")
		break;
		return Intrinsic::hexagon_A4_ornp; // "__builtin_HEXAGON.A4.or
		np"
		}
		break;
		}
		break;
		case 'C': // 5 strings to match.
		if (BuiltinName.substr(19, 2) != "2.")
		break;
		switch (BuiltinName[21]) {
		default: break;
		case 'a': // 3 strings to match.
		switch (BuiltinName[22]) {
		default: break;
		case 'l': // 1 string to match.
		if (BuiltinName.substr(23, 2) != "l8")
		break;
		return Intrinsic::hexagon_C2_all8; // "__builtin_HEXAGON.C2.al
		l8"
		case 'n': // 2 strings to match.
		switch (BuiltinName[23]) {
		default: break;
		case 'd': // 1 string to match.
		if (BuiltinName[24] != 'n')
		break;
		return Intrinsic::hexagon_C2_andn; // "__builtin_HEXAGON.C2.an
		dn"
		case 'y': // 1 string to match.
		if (BuiltinName[24] != '8')
		break;
		return Intrinsic::hexagon_C2_any8; // "__builtin_HEXAGON.C2.an
		y8"
		}
		break;
		}
		break;
		case 'm': // 1 string to match.
		if (BuiltinName.substr(22, 3) != "ask")
		break;
		return Intrinsic::hexagon_C2_mask; // "__builtin_HEXAGON.C2.ma
		sk"
		case 'v': // 1 string to match.
		if (BuiltinName.substr(22, 3) != "mux")
		break;
		return Intrinsic::hexagon_C2_vmux; // "__builtin_HEXAGON.C2.vm
		ux"
		}
		break;
		case 'M': // 3 strings to match.
		if (BuiltinName.substr(19, 2) != "2.")
		break;
		switch (BuiltinName[21]) {
		default: break;
		case 'a': // 1 string to match.
		if (BuiltinName.substr(22, 3) != "cci")
		break;
		return Intrinsic::hexagon_M2_acci; // "__builtin_HEXAGON.M2.ac
		ci"
		case 'm': // 2 strings to match.
		switch (BuiltinName[22]) {
		default: break;
		case 'a': // 1 string to match.
		if (BuiltinName.substr(23, 2) != "ci")
		break;
		return Intrinsic::hexagon_M2_maci; // "__builtin_HEXAGON.M2.ma
		ci"
		case 'p': // 1 string to match.
		if (BuiltinName.substr(23, 2) != "yi")
		break;
		return Intrinsic::hexagon_M2_mpyi; // "__builtin_HEXAGON.M2.mp
		yi"
		}
		break;
		}
		break;
		case 'S': // 6 strings to match.
		switch (BuiltinName[19]) {
		default: break;
		case '2': // 5 strings to match.
		if (BuiltinName[20] != '.')
		break;
		switch (BuiltinName[21]) {
		default: break;
		case 'b': // 1 string to match.
		if (BuiltinName.substr(22, 3) != "rev")
		break;
		return Intrinsic::hexagon_S2_brev; // "__builtin_HEXAGON.S2.br
		ev"
		case 'c': // 3 strings to match.
		if (BuiltinName[22] != 'l')
		break;
		switch (BuiltinName[23]) {
		default: break;
		case '0': // 1 string to match.
		if (BuiltinName[24] != 'p')
		break;
		return Intrinsic::hexagon_S2_cl0p; // "__builtin_HEXAGON.S2.cl
		0p"
		case '1': // 1 string to match.
		if (BuiltinName[24] != 'p')
		break;
		return Intrinsic::hexagon_S2_cl1p; // "__builtin_HEXAGON.S2.cl
		1p"
		case 'b': // 1 string to match.
		if (BuiltinName[24] != 'p')
		break;
		return Intrinsic::hexagon_S2_clbp; // "__builtin_HEXAGON.S2.cl
		bp"
		}
		break;
		case 'l': // 1 string to match.
		if (BuiltinName.substr(22, 3) != "fsp")
		break;
		return Intrinsic::hexagon_S2_lfsp; // "__builtin_HEXAGON.S2.lf
		sp"
		}
		break;
		case '4': // 1 string to match.
		if (BuiltinName.substr(20, 5) != ".ornp")
		break;
		return Intrinsic::hexagon_S4_ornp; // "__builtin_HEXAGON.S4.or
		np"
		}
		break;
		}
	break;	break;

	case Intrinsic::arm_neon_vtbx4: // llvm.arm.neon.vtbx4	case 26: // 41 strings to match.
	ResultTy = VectorType::get(IntegerType::get(Context, 8), 8);	if (BuiltinName.substr(0, 10) != "__builtin_")
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));	break;
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));	switch (BuiltinName[10]) {
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));	default: break;
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));	case 'H': // 40 strings to match.
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));	if (BuiltinName.substr(11, 7) != "EXAGON.")
	ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));	break;
		switch (BuiltinName[18]) {
		default: break;
		case 'A': // 25 strings to match.
		switch (BuiltinName[19]) {
		default: break;
		case '2': // 24 strings to match.
		if (BuiltinName[20] != '.')
		break;
		switch (BuiltinName[21]) {
		default: break;
		case 'a': // 2 strings to match.
		switch (BuiltinName[22]) {
		default: break;
		case 'd': // 1 string to match.
		if (BuiltinName.substr(23, 3) != "dsp")
		break;
		return Intrinsic::hexagon_A2_addsp; // "__builtin_HEXAG
		ON.A2.addsp"
		case 'n': // 1 string to match.
		if (BuiltinName.substr(23, 3) != "dir")
		break;
		return Intrinsic::hexagon_A2_andir; // "__builtin_HEXAG
		ON.A2.andir"
		}
		break;
		case 'm': // 2 strings to match.
		switch (BuiltinName[22]) {
		default: break;
		case 'a': // 1 string to match.
		if (BuiltinName.substr(23, 3) != "xup")
		break;
		return Intrinsic::hexagon_A2_maxup; // "__builtin_HEXAG
		ON.A2.maxup"
		case 'i': // 1 string to match.
		if (BuiltinName.substr(23, 3) != "nup")
		break;
		return Intrinsic::hexagon_A2_minup; // "__builtin_HEXAG
		ON.A2.minup"
		}
		break;
		case 's': // 3 strings to match.
		switch (BuiltinName[22]) {
		default: break;
		case 'a': // 2 strings to match.
		if (BuiltinName.substr(23, 2) != "tu")
		break;
		switch (BuiltinName[25]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::hexagon_A2_satub; // "__builtin_HEXAG
		ON.A2.satub"
		case 'h': // 1 string to match.
		return Intrinsic::hexagon_A2_satuh; // "__builtin_HEXAG
		ON.A2.satuh"
		}
		break;
		case 'u': // 1 string to match.
		if (BuiltinName.substr(23, 3) != "bri")
		break;
		return Intrinsic::hexagon_A2_subri; // "__builtin_HEXAG
		ON.A2.subri"
		}
		break;
		case 't': // 4 strings to match.
		if (BuiltinName.substr(22, 2) != "fr")
		break;
		switch (BuiltinName[24]) {
		default: break;
		case 'i': // 2 strings to match.
		switch (BuiltinName[25]) {
		default: break;
		case 'h': // 1 string to match.
		return Intrinsic::hexagon_A2_tfrih; // "__builtin_HEXAG
		ON.A2.tfrih"
		case 'l': // 1 string to match.
		return Intrinsic::hexagon_A2_tfril; // "__builtin_HEXAG
		ON.A2.tfril"
		}
		break;
		case 'p': // 1 string to match.
		if (BuiltinName[25] != 'i')
		break;
		return Intrinsic::hexagon_A2_tfrpi; // "__builtin_HEXAG
		ON.A2.tfrpi"
		case 's': // 1 string to match.
		if (BuiltinName[25] != 'i')
		break;
		return Intrinsic::hexagon_A2_tfrsi; // "__builtin_HEXAG
		ON.A2.tfrsi"
		}
		break;
		case 'v': // 13 strings to match.
		switch (BuiltinName[22]) {
		default: break;
		case 'a': // 6 strings to match.
		switch (BuiltinName[23]) {
		default: break;
		case 'b': // 2 strings to match.
		if (BuiltinName[24] != 's')
		break;
		switch (BuiltinName[25]) {
		default: break;
		case 'h': // 1 string to match.
		return Intrinsic::hexagon_A2_vabsh; // "__builtin_HEXAG
		ON.A2.vabsh"
		case 'w': // 1 string to match.
		return Intrinsic::hexagon_A2_vabsw; // "__builtin_HEXAG
		ON.A2.vabsw"
		}
		break;
		case 'd': // 2 strings to match.
		if (BuiltinName[24] != 'd')
		break;
		switch (BuiltinName[25]) {
		default: break;
		case 'h': // 1 string to match.
		return Intrinsic::hexagon_A2_vaddh; // "__builtin_HEXAG
		ON.A2.vaddh"
		case 'w': // 1 string to match.
		return Intrinsic::hexagon_A2_vaddw; // "__builtin_HEXAG
		ON.A2.vaddw"
		}
		break;
		case 'v': // 2 strings to match.
		if (BuiltinName[24] != 'g')
		break;
		switch (BuiltinName[25]) {
		default: break;
		case 'h': // 1 string to match.
		return Intrinsic::hexagon_A2_vavgh; // "__builtin_HEXAG
		ON.A2.vavgh"
		case 'w': // 1 string to match.
		return Intrinsic::hexagon_A2_vavgw; // "__builtin_HEXAG
		ON.A2.vavgw"
		}
		break;
		}
		break;
		case 'c': // 1 string to match.
		if (BuiltinName.substr(23, 3) != "onj")
		break;
		return Intrinsic::hexagon_A2_vconj; // "__builtin_HEXAG
		ON.A2.vconj"
		case 'm': // 4 strings to match.
		switch (BuiltinName[23]) {
		default: break;
		case 'a': // 2 strings to match.
		if (BuiltinName[24] != 'x')
		break;
		switch (BuiltinName[25]) {
		default: break;
		case 'h': // 1 string to match.
		return Intrinsic::hexagon_A2_vmaxh; // "__builtin_HEXAG
		ON.A2.vmaxh"
		case 'w': // 1 string to match.
		return Intrinsic::hexagon_A2_vmaxw; // "__builtin_HEXAG
		ON.A2.vmaxw"
		}
		break;
		case 'i': // 2 strings to match.
		if (BuiltinName[24] != 'n')
		break;
		switch (BuiltinName[25]) {
		default: break;
		case 'h': // 1 string to match.
		return Intrinsic::hexagon_A2_vminh; // "__builtin_HEXAG
		ON.A2.vminh"
		case 'w': // 1 string to match.
		return Intrinsic::hexagon_A2_vminw; // "__builtin_HEXAG
		ON.A2.vminw"
		}
		break;
		}
		break;
		case 's': // 2 strings to match.
		if (BuiltinName.substr(23, 2) != "ub")
		break;
		switch (BuiltinName[25]) {
		default: break;
		case 'h': // 1 string to match.
		return Intrinsic::hexagon_A2_vsubh; // "__builtin_HEXAG
		ON.A2.vsubh"
		case 'w': // 1 string to match.
		return Intrinsic::hexagon_A2_vsubw; // "__builtin_HEXAG
		ON.A2.vsubw"
		}
		break;
		}
		break;
		}
		break;
		case '4': // 1 string to match.
		if (BuiltinName.substr(20, 6) != ".andnp")
		break;
		return Intrinsic::hexagon_A4_andnp; // "__builtin_HEXAGON.A4.an
		dnp"
		}
		break;
		case 'C': // 9 strings to match.
		switch (BuiltinName[19]) {
		default: break;
		case '2': // 8 strings to match.
		if (BuiltinName[20] != '.')
		break;
		switch (BuiltinName[21]) {
		default: break;
		case 'c': // 3 strings to match.
		if (BuiltinName.substr(22, 2) != "mp")
		break;
		switch (BuiltinName[24]) {
		default: break;
		case 'e': // 1 string to match.
		if (BuiltinName[25] != 'q')
		break;
		return Intrinsic::hexagon_C2_cmpeq; // "__builtin_HEXAG
		ON.C2.cmpeq"
		case 'g': // 1 string to match.
		if (BuiltinName[25] != 't')
		break;
		return Intrinsic::hexagon_C2_cmpgt; // "__builtin_HEXAG
		ON.C2.cmpgt"
		case 'l': // 1 string to match.
		if (BuiltinName[25] != 't')
		break;
		return Intrinsic::hexagon_C2_cmplt; // "__builtin_HEXAG
		ON.C2.cmplt"
		}
		break;
		case 'm': // 3 strings to match.
		if (BuiltinName.substr(22, 2) != "ux")
		break;
		switch (BuiltinName[24]) {
		default: break;
		case 'i': // 2 strings to match.
		switch (BuiltinName[25]) {
		default: break;
		case 'i': // 1 string to match.
		return Intrinsic::hexagon_C2_muxii; // "__builtin_HEXAG
		ON.C2.muxii"
		case 'r': // 1 string to match.
		return Intrinsic::hexagon_C2_muxir; // "__builtin_HEXAG
		ON.C2.muxir"
		}
		break;
		case 'r': // 1 string to match.
		if (BuiltinName[25] != 'i')
		break;
		return Intrinsic::hexagon_C2_muxri; // "__builtin_HEXAG
		ON.C2.muxri"
		}
		break;
		case 't': // 2 strings to match.
		if (BuiltinName.substr(22, 2) != "fr")
		break;
		switch (BuiltinName[24]) {
		default: break;
		case 'p': // 1 string to match.
		if (BuiltinName[25] != 'r')
		break;
		return Intrinsic::hexagon_C2_tfrpr; // "__builtin_HEXAG
		ON.C2.tfrpr"
		case 'r': // 1 string to match.
		if (BuiltinName[25] != 'p')
		break;
		return Intrinsic::hexagon_C2_tfrrp; // "__builtin_HEXAG
		ON.C2.tfrrp"
		}
		break;
		}
		break;
		case '4': // 1 string to match.
		if (BuiltinName.substr(20, 6) != ".or_or")
		break;
		return Intrinsic::hexagon_C4_or_or; // "__builtin_HEXAGON.C4.or
		_or"
		}
		break;
		case 'M': // 5 strings to match.
		switch (BuiltinName[19]) {
		default: break;
		case '2': // 4 strings to match.
		if (BuiltinName[20] != '.')
		break;
		switch (BuiltinName[21]) {
		default: break;
		case 'a': // 1 string to match.
		if (BuiltinName.substr(22, 4) != "ccii")
		break;
		return Intrinsic::hexagon_M2_accii; // "__builtin_HEXAG
		ON.M2.accii"
		case 'm': // 1 string to match.
		if (BuiltinName.substr(22, 4) != "pyui")
		break;
		return Intrinsic::hexagon_M2_mpyui; // "__builtin_HEXAG
		ON.M2.mpyui"
		case 'n': // 1 string to match.
		if (BuiltinName.substr(22, 4) != "acci")
		break;
		return Intrinsic::hexagon_M2_nacci; // "__builtin_HEXAG
		ON.M2.nacci"
		case 'v': // 1 string to match.
		if (BuiltinName.substr(22, 4) != "mac2")
		break;
		return Intrinsic::hexagon_M2_vmac2; // "__builtin_HEXAG
		ON.M2.vmac2"
		}
		break;
		case '4': // 1 string to match.
		if (BuiltinName.substr(20, 6) != ".or_or")
		break;
		return Intrinsic::hexagon_M4_or_or; // "__builtin_HEXAGON.M4.or
		_or"
		}
		break;
		case 'S': // 1 string to match.
		if (BuiltinName.substr(19, 7) != "4.andnp")
		break;
		return Intrinsic::hexagon_S4_andnp; // "__builtin_HEXAGON.S4.an
		dnp"
		}
		break;
		case 'S': // 1 string to match.
		if (BuiltinName.substr(11, 15) != "I.to.SXTHI.asrh")
		break;
		return Intrinsic::hexagon_SI_to_SXTHI_asrh; // "__builtin_SI.to
		.SXTHI.asrh"
		}
	break;	break;

	case Intrinsic::x86_sse_cvtpd2pi: // llvm.x86.sse.cvtpd2pi	case 27: // 58 strings to match.
	case Intrinsic::x86_sse_cvttpd2pi: // llvm.x86.sse.cvttpd2pi	if (BuiltinName.substr(0, 18) != "__builtin_HEXAGON.")
	ResultTy = Type::getX86_MMXTy(Context);	break;
	ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));	switch (BuiltinName[18]) {
		default: break;
		case 'A': // 27 strings to match.
		switch (BuiltinName[19]) {
		default: break;
		case '2': // 26 strings to match.
		if (BuiltinName[20] != '.')
		break;
		switch (BuiltinName[21]) {
		default: break;
		case 'a': // 2 strings to match.
		switch (BuiltinName[22]) {
		default: break;
		case 'b': // 1 string to match.
		if (BuiltinName.substr(23, 4) != "ssat")
		break;
		return Intrinsic::hexagon_A2_abssat; // "__builtin_HEXAG
		ON.A2.abssat"
		case 'd': // 1 string to match.
		if (BuiltinName.substr(23, 4) != "dsat")
		break;
		return Intrinsic::hexagon_A2_addsat; // "__builtin_HEXAG
		ON.A2.addsat"
		}
		break;
		case 'n': // 1 string to match.
		if (BuiltinName.substr(22, 5) != "egsat")
		break;
		return Intrinsic::hexagon_A2_negsat; // "__builtin_HEXAGON.A2.ne
		gsat"
		case 's': // 4 strings to match.
		switch (BuiltinName[22]) {
		default: break;
		case 'u': // 1 string to match.
		if (BuiltinName.substr(23, 4) != "bsat")
		break;
		return Intrinsic::hexagon_A2_subsat; // "__builtin_HEXAG
		ON.A2.subsat"
		case 'v': // 3 strings to match.
		switch (BuiltinName[23]) {
		default: break;
		case 'a': // 2 strings to match.
		switch (BuiltinName[24]) {
		default: break;
		case 'd': // 1 string to match.
		if (BuiltinName.substr(25, 2) != "dh")
		break;
		return Intrinsic::hexagon_A2_svaddh; // "__builtin_HEXAG
		ON.A2.svaddh"
		case 'v': // 1 string to match.
		if (BuiltinName.substr(25, 2) != "gh")
		break;
		return Intrinsic::hexagon_A2_svavgh; // "__builtin_HEXAG
		ON.A2.svavgh"
		}
		break;
		case 's': // 1 string to match.
		if (BuiltinName.substr(24, 3) != "ubh")
		break;
		return Intrinsic::hexagon_A2_svsubh; // "__builtin_HEXAG
		ON.A2.svsubh"
		}
		break;
		}
		break;
		case 'v': // 19 strings to match.
		switch (BuiltinName[22]) {
		default: break;
		case 'a': // 8 strings to match.
		switch (BuiltinName[23]) {
		default: break;
		case 'd': // 3 strings to match.
		if (BuiltinName[24] != 'd')
		break;
		switch (BuiltinName[25]) {
		default: break;
		case 'h': // 1 string to match.
		if (BuiltinName[26] != 's')
		break;
		return Intrinsic::hexagon_A2_vaddhs; // "__builtin_HEXAG
		ON.A2.vaddhs"
		case 'u': // 1 string to match.
		if (BuiltinName[26] != 'b')
		break;
		return Intrinsic::hexagon_A2_vaddub; // "__builtin_HEXAG
		ON.A2.vaddub"
		case 'w': // 1 string to match.
		if (BuiltinName[26] != 's')
		break;
		return Intrinsic::hexagon_A2_vaddws; // "__builtin_HEXAG
		ON.A2.vaddws"
		}
		break;
		case 'v': // 5 strings to match.
		if (BuiltinName[24] != 'g')
		break;
		switch (BuiltinName[25]) {
		default: break;
		case 'h': // 1 string to match.
		if (BuiltinName[26] != 'r')
		break;
		return Intrinsic::hexagon_A2_vavghr; // "__builtin_HEXAG
		ON.A2.vavghr"
		case 'u': // 3 strings to match.
		switch (BuiltinName[26]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::hexagon_A2_vavgub; // "__builtin_HEXAG
		ON.A2.vavgub"
		case 'h': // 1 string to match.
		return Intrinsic::hexagon_A2_vavguh; // "__builtin_HEXAG
		ON.A2.vavguh"
		case 'w': // 1 string to match.
		return Intrinsic::hexagon_A2_vavguw; // "__builtin_HEXAG
		ON.A2.vavguw"
		}
		break;
		case 'w': // 1 string to match.
		if (BuiltinName[26] != 'r')
		break;
		return Intrinsic::hexagon_A2_vavgwr; // "__builtin_HEXAG
		ON.A2.vavgwr"
		}
		break;
		}
		break;
		case 'm': // 6 strings to match.
		switch (BuiltinName[23]) {
		default: break;
		case 'a': // 3 strings to match.
		if (BuiltinName.substr(24, 2) != "xu")
		break;
		switch (BuiltinName[26]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::hexagon_A2_vmaxub; // "__builtin_HEXAG
		ON.A2.vmaxub"
		case 'h': // 1 string to match.
		return Intrinsic::hexagon_A2_vmaxuh; // "__builtin_HEXAG
		ON.A2.vmaxuh"
		case 'w': // 1 string to match.
		return Intrinsic::hexagon_A2_vmaxuw; // "__builtin_HEXAG
		ON.A2.vmaxuw"
		}
		break;
		case 'i': // 3 strings to match.
		if (BuiltinName.substr(24, 2) != "nu")
		break;
		switch (BuiltinName[26]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::hexagon_A2_vminub; // "__builtin_HEXAG
		ON.A2.vminub"
		case 'h': // 1 string to match.
		return Intrinsic::hexagon_A2_vminuh; // "__builtin_HEXAG
		ON.A2.vminuh"
		case 'w': // 1 string to match.
		return Intrinsic::hexagon_A2_vminuw; // "__builtin_HEXAG
		ON.A2.vminuw"
		}
		break;
		}
		break;
		case 'n': // 2 strings to match.
		if (BuiltinName.substr(23, 3) != "avg")
		break;
		switch (BuiltinName[26]) {
		default: break;
		case 'h': // 1 string to match.
		return Intrinsic::hexagon_A2_vnavgh; // "__builtin_HEXAG
		ON.A2.vnavgh"
		case 'w': // 1 string to match.
		return Intrinsic::hexagon_A2_vnavgw; // "__builtin_HEXAG
		ON.A2.vnavgw"
		}
		break;
		case 's': // 3 strings to match.
		if (BuiltinName.substr(23, 2) != "ub")
		break;
		switch (BuiltinName[25]) {
		default: break;
		case 'h': // 1 string to match.
		if (BuiltinName[26] != 's')
		break;
		return Intrinsic::hexagon_A2_vsubhs; // "__builtin_HEXAG
		ON.A2.vsubhs"
		case 'u': // 1 string to match.
		if (BuiltinName[26] != 'b')
		break;
		return Intrinsic::hexagon_A2_vsubub; // "__builtin_HEXAG
		ON.A2.vsubub"
		case 'w': // 1 string to match.
		if (BuiltinName[26] != 's')
		break;
		return Intrinsic::hexagon_A2_vsubws; // "__builtin_HEXAG
		ON.A2.vsubws"
		}
		break;
		}
		break;
		}
		break;
		case '4': // 1 string to match.
		if (BuiltinName.substr(20, 7) != ".rcmpeq")
		break;
		return Intrinsic::hexagon_A4_rcmpeq; // "__builtin_HEXAGON.A4.rc
		mpeq"
		}
		break;
		case 'C': // 12 strings to match.
		switch (BuiltinName[19]) {
		default: break;
		case '2': // 7 strings to match.
		if (BuiltinName.substr(20, 4) != ".cmp")
		break;
		switch (BuiltinName[24]) {
		default: break;
		case 'e': // 2 strings to match.
		if (BuiltinName[25] != 'q')
		break;
		switch (BuiltinName[26]) {
		default: break;
		case 'i': // 1 string to match.
		return Intrinsic::hexagon_C2_cmpeqi; // "__builtin_HEXAG
		ON.C2.cmpeqi"
		case 'p': // 1 string to match.
		return Intrinsic::hexagon_C2_cmpeqp; // "__builtin_HEXAG
		ON.C2.cmpeqp"
		}
		break;
		case 'g': // 4 strings to match.
		switch (BuiltinName[25]) {
		default: break;
		case 'e': // 1 string to match.
		if (BuiltinName[26] != 'i')
		break;
		return Intrinsic::hexagon_C2_cmpgei; // "__builtin_HEXAG
		ON.C2.cmpgei"
		case 't': // 3 strings to match.
		switch (BuiltinName[26]) {
		default: break;
		case 'i': // 1 string to match.
		return Intrinsic::hexagon_C2_cmpgti; // "__builtin_HEXAG
		ON.C2.cmpgti"
		case 'p': // 1 string to match.
		return Intrinsic::hexagon_C2_cmpgtp; // "__builtin_HEXAG
		ON.C2.cmpgtp"
		case 'u': // 1 string to match.
		return Intrinsic::hexagon_C2_cmpgtu; // "__builtin_HEXAG
		ON.C2.cmpgtu"
		}
		break;
		}
		break;
		case 'l': // 1 string to match.
		if (BuiltinName.substr(25, 2) != "tu")
		break;
		return Intrinsic::hexagon_C2_cmpltu; // "__builtin_HEXAGON.C2.cm
		pltu"
		}
		break;
		case '4': // 5 strings to match.
		if (BuiltinName[20] != '.')
		break;
		switch (BuiltinName[21]) {
		default: break;
		case 'a': // 1 string to match.
		if (BuiltinName.substr(22, 5) != "nd_or")
		break;
		return Intrinsic::hexagon_C4_and_or; // "__builtin_HEXAGON.C4.an
		d_or"
		case 'c': // 2 strings to match.
		if (BuiltinName.substr(22, 2) != "mp")
		break;
		switch (BuiltinName[24]) {
		default: break;
		case 'l': // 1 string to match.
		if (BuiltinName.substr(25, 2) != "te")
		break;
		return Intrinsic::hexagon_C4_cmplte; // "__builtin_HEXAG
		ON.C4.cmplte"
		case 'n': // 1 string to match.
		if (BuiltinName.substr(25, 2) != "eq")
		break;
		return Intrinsic::hexagon_C4_cmpneq; // "__builtin_HEXAG
		ON.C4.cmpneq"
		}
		break;
		case 'o': // 2 strings to match.
		if (BuiltinName.substr(22, 2) != "r_")
		break;
		switch (BuiltinName[24]) {
		default: break;
		case 'a': // 1 string to match.
		if (BuiltinName.substr(25, 2) != "nd")
		break;
		return Intrinsic::hexagon_C4_or_and; // "__builtin_HEXAG
		ON.C4.or_and"
		case 'o': // 1 string to match.
		if (BuiltinName.substr(25, 2) != "rn")
		break;
		return Intrinsic::hexagon_C4_or_orn; // "__builtin_HEXAG
		ON.C4.or_orn"
		}
		break;
		}
		break;
		}
		break;
		case 'M': // 10 strings to match.
		switch (BuiltinName[19]) {
		default: break;
		case '2': // 6 strings to match.
		if (BuiltinName[20] != '.')
		break;
		switch (BuiltinName[21]) {
		default: break;
		case 'm': // 4 strings to match.
		switch (BuiltinName[22]) {
		default: break;
		case 'a': // 2 strings to match.
		if (BuiltinName.substr(23, 3) != "csi")
		break;
		switch (BuiltinName[26]) {
		default: break;
		case 'n': // 1 string to match.
		return Intrinsic::hexagon_M2_macsin; // "__builtin_HEXAG
		ON.M2.macsin"
		case 'p': // 1 string to match.
		return Intrinsic::hexagon_M2_macsip; // "__builtin_HEXAG
		ON.M2.macsip"
		}
		break;
		case 'p': // 2 strings to match.
		if (BuiltinName[23] != 'y')
		break;
		switch (BuiltinName[24]) {
		default: break;
		case '.': // 1 string to match.
		if (BuiltinName.substr(25, 2) != "up")
		break;
		return Intrinsic::hexagon_M2_mpy_up; // "__builtin_HEXAG
		ON.M2.mpy.up"
		case 's': // 1 string to match.
		if (BuiltinName.substr(25, 2) != "mi")
		break;
		return Intrinsic::hexagon_M2_mpysmi; // "__builtin_HEXAG
		ON.M2.mpysmi"
		}
		break;
		}
		break;
		case 'n': // 1 string to match.
		if (BuiltinName.substr(22, 5) != "accii")
		break;
		return Intrinsic::hexagon_M2_naccii; // "__builtin_HEXAGON.M2.na
		ccii"
		case 's': // 1 string to match.
		if (BuiltinName.substr(22, 5) != "ubacc")
		break;
		return Intrinsic::hexagon_M2_subacc; // "__builtin_HEXAGON.M2.su
		bacc"
		}
		break;
		case '4': // 4 strings to match.
		if (BuiltinName[20] != '.')
		break;
		switch (BuiltinName[21]) {
		default: break;
		case 'a': // 1 string to match.
		if (BuiltinName.substr(22, 5) != "nd_or")
		break;
		return Intrinsic::hexagon_M4_and_or; // "__builtin_HEXAGON.M4.an
		d_or"
		case 'o': // 2 strings to match.
		if (BuiltinName.substr(22, 2) != "r_")
		break;
		switch (BuiltinName[24]) {
		default: break;
		case 'a': // 1 string to match.
		if (BuiltinName.substr(25, 2) != "nd")
		break;
		return Intrinsic::hexagon_M4_or_and; // "__builtin_HEXAG
		ON.M4.or_and"
		case 'x': // 1 string to match.
		if (BuiltinName.substr(25, 2) != "or")
		break;
		return Intrinsic::hexagon_M4_or_xor; // "__builtin_HEXAG
		ON.M4.or_xor"
		}
		break;
		case 'x': // 1 string to match.
		if (BuiltinName.substr(22, 5) != "or_or")
		break;
		return Intrinsic::hexagon_M4_xor_or; // "__builtin_HEXAGON.M4.xo
		r_or"
		}
		break;
		}
		break;
		case 'S': // 9 strings to match.
		switch (BuiltinName[19]) {
		default: break;
		case '2': // 8 strings to match.
		if (BuiltinName[20] != '.')
		break;
		switch (BuiltinName[21]) {
		default: break;
		case 'i': // 1 string to match.
		if (BuiltinName.substr(22, 5) != "nsert")
		break;
		return Intrinsic::hexagon_S2_insert; // "__builtin_HEXAGON.S2.in
		sert"
		case 'p': // 1 string to match.
		if (BuiltinName.substr(22, 5) != "ackhl")
		break;
		return Intrinsic::hexagon_S2_packhl; // "__builtin_HEXAGON.S2.pa
		ckhl"
		case 'v': // 6 strings to match.
		switch (BuiltinName[22]) {
		default: break;
		case 's': // 4 strings to match.
		switch (BuiltinName[23]) {
		default: break;
		case 'a': // 2 strings to match.
		if (BuiltinName[24] != 't')
		break;
		switch (BuiltinName[25]) {
		default: break;
		case 'h': // 1 string to match.
		if (BuiltinName[26] != 'b')
		break;
		return Intrinsic::hexagon_S2_vsathb; // "__builtin_HEXAG
		ON.S2.vsathb"
		case 'w': // 1 string to match.
		if (BuiltinName[26] != 'h')
		break;
		return Intrinsic::hexagon_S2_vsatwh; // "__builtin_HEXAG
		ON.S2.vsatwh"
		}
		break;
		case 'x': // 2 strings to match.
		if (BuiltinName[24] != 't')
		break;
		switch (BuiltinName[25]) {
		default: break;
		case 'b': // 1 string to match.
		if (BuiltinName[26] != 'h')
		break;
		return Intrinsic::hexagon_S2_vsxtbh; // "__builtin_HEXAG
		ON.S2.vsxtbh"
		case 'h': // 1 string to match.
		if (BuiltinName[26] != 'w')
		break;
		return Intrinsic::hexagon_S2_vsxthw; // "__builtin_HEXAG
		ON.S2.vsxthw"
		}
		break;
		}
		break;
		case 'z': // 2 strings to match.
		if (BuiltinName.substr(23, 2) != "xt")
		break;
		switch (BuiltinName[25]) {
		default: break;
		case 'b': // 1 string to match.
		if (BuiltinName[26] != 'h')
		break;
		return Intrinsic::hexagon_S2_vzxtbh; // "__builtin_HEXAG
		ON.S2.vzxtbh"
		case 'h': // 1 string to match.
		if (BuiltinName[26] != 'w')
		break;
		return Intrinsic::hexagon_S2_vzxthw; // "__builtin_HEXAG
		ON.S2.vzxthw"
		}
		break;
		}
		break;
		}
		break;
		case '4': // 1 string to match.
		if (BuiltinName.substr(20, 7) != ".or_ori")
		break;
		return Intrinsic::hexagon_S4_or_ori; // "__builtin_HEXAGON.S4.or
		_ori"
		}
		break;
		}
	break;	break;

	case Intrinsic::x86_sse_cvtps2pi: // llvm.x86.sse.cvtps2pi	case 28: // 71 strings to match.
	case Intrinsic::x86_sse_cvttps2pi: // llvm.x86.sse.cvttps2pi	if (BuiltinName.substr(0, 18) != "__builtin_HEXAGON.")
	ResultTy = Type::getX86_MMXTy(Context);	break;
	ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));	switch (BuiltinName[18]) {
		default: break;
		case 'A': // 25 strings to match.
		switch (BuiltinName[19]) {
		default: break;
		case '2': // 23 strings to match.
		if (BuiltinName[20] != '.')
		break;
		switch (BuiltinName[21]) {
		default: break;
		case 'a': // 1 string to match.
		if (BuiltinName.substr(22, 6) != "ddpsat")
		break;
		return Intrinsic::hexagon_A2_addpsat; // "__builtin_HEXAG
		ON.A2.addpsat"
		case 's': // 4 strings to match.
		if (BuiltinName[22] != 'v')
		break;
		switch (BuiltinName[23]) {
		default: break;
		case 'a': // 2 strings to match.
		switch (BuiltinName[24]) {
		default: break;
		case 'd': // 1 string to match.
		if (BuiltinName.substr(25, 3) != "dhs")
		break;
		return Intrinsic::hexagon_A2_svaddhs; // "__builtin_HEXAG
		ON.A2.svaddhs"
		case 'v': // 1 string to match.
		if (BuiltinName.substr(25, 3) != "ghs")
		break;
		return Intrinsic::hexagon_A2_svavghs; // "__builtin_HEXAG
		ON.A2.svavghs"
		}
		break;
		case 'n': // 1 string to match.
		if (BuiltinName.substr(24, 4) != "avgh")
		break;
		return Intrinsic::hexagon_A2_svnavgh; // "__builtin_HEXAG
		ON.A2.svnavgh"
		case 's': // 1 string to match.
		if (BuiltinName.substr(24, 4) != "ubhs")
		break;
		return Intrinsic::hexagon_A2_svsubhs; // "__builtin_HEXAG
		ON.A2.svsubhs"
		}
		break;
		case 'v': // 18 strings to match.
		switch (BuiltinName[22]) {
		default: break;
		case 'a': // 7 strings to match.
		switch (BuiltinName[23]) {
		default: break;
		case 'd': // 2 strings to match.
		if (BuiltinName.substr(24, 2) != "du")
		break;
		switch (BuiltinName[26]) {
		default: break;
		case 'b': // 1 string to match.
		if (BuiltinName[27] != 's')
		break;
		return Intrinsic::hexagon_A2_vaddubs; // "__builtin_HEXAG
		ON.A2.vaddubs"
		case 'h': // 1 string to match.
		if (BuiltinName[27] != 's')
		break;
		return Intrinsic::hexagon_A2_vadduhs; // "__builtin_HEXAG
		ON.A2.vadduhs"
		}
		break;
		case 'v': // 5 strings to match.
		if (BuiltinName[24] != 'g')
		break;
		switch (BuiltinName[25]) {
		default: break;
		case 'h': // 1 string to match.
		if (BuiltinName.substr(26, 2) != "cr")
		break;
		return Intrinsic::hexagon_A2_vavghcr; // "__builtin_HEXAG
		ON.A2.vavghcr"
		case 'u': // 3 strings to match.
		switch (BuiltinName[26]) {
		default: break;
		case 'b': // 1 string to match.
		if (BuiltinName[27] != 'r')
		break;
		return Intrinsic::hexagon_A2_vavgubr; // "__built
		in_HEXAGON.A2.vavgubr"
		case 'h': // 1 string to match.
		if (BuiltinName[27] != 'r')
		break;
		return Intrinsic::hexagon_A2_vavguhr; // "__built
		in_HEXAGON.A2.vavguhr"
		case 'w': // 1 string to match.
		if (BuiltinName[27] != 'r')
		break;
		return Intrinsic::hexagon_A2_vavguwr; // "__built
		in_HEXAGON.A2.vavguwr"
		}
		break;
		case 'w': // 1 string to match.
		if (BuiltinName.substr(26, 2) != "cr")
		break;
		return Intrinsic::hexagon_A2_vavgwcr; // "__builtin_HEXAG
		ON.A2.vavgwcr"
		}
		break;
		}
		break;
		case 'c': // 5 strings to match.
		if (BuiltinName.substr(23, 2) != "mp")
		break;
		switch (BuiltinName[25]) {
		default: break;
		case 'b': // 1 string to match.
		if (BuiltinName.substr(26, 2) != "eq")
		break;
		return Intrinsic::hexagon_A2_vcmpbeq; // "__builtin_HEXAG
		ON.A2.vcmpbeq"
		case 'h': // 2 strings to match.
		switch (BuiltinName[26]) {
		default: break;
		case 'e': // 1 string to match.
		if (BuiltinName[27] != 'q')
		break;
		return Intrinsic::hexagon_A2_vcmpheq; // "__builtin_HEXAG
		ON.A2.vcmpheq"
		case 'g': // 1 string to match.
		if (BuiltinName[27] != 't')
		break;
		return Intrinsic::hexagon_A2_vcmphgt; // "__builtin_HEXAG
		ON.A2.vcmphgt"
		}
		break;
		case 'w': // 2 strings to match.
		switch (BuiltinName[26]) {
		default: break;
		case 'e': // 1 string to match.
		if (BuiltinName[27] != 'q')
		break;
		return Intrinsic::hexagon_A2_vcmpweq; // "__builtin_HEXAG
		ON.A2.vcmpweq"
		case 'g': // 1 string to match.
		if (BuiltinName[27] != 't')
		break;
		return Intrinsic::hexagon_A2_vcmpwgt; // "__builtin_HEXAG
		ON.A2.vcmpwgt"
		}
		break;
		}
		break;
		case 'n': // 2 strings to match.
		if (BuiltinName.substr(23, 3) != "avg")
		break;
		switch (BuiltinName[26]) {
		default: break;
		case 'h': // 1 string to match.
		if (BuiltinName[27] != 'r')
		break;
		return Intrinsic::hexagon_A2_vnavghr; // "__builtin_HEXAG
		ON.A2.vnavghr"
		case 'w': // 1 string to match.
		if (BuiltinName[27] != 'r')
		break;
		return Intrinsic::hexagon_A2_vnavgwr; // "__builtin_HEXAG
		ON.A2.vnavgwr"
		}
		break;
		case 'r': // 2 strings to match.
		switch (BuiltinName[23]) {
		default: break;
		case 'a': // 1 string to match.
		if (BuiltinName.substr(24, 4) != "ddub")
		break;
		return Intrinsic::hexagon_A2_vraddub; // "__builtin_HEXAG
		ON.A2.vraddub"
		case 's': // 1 string to match.
		if (BuiltinName.substr(24, 4) != "adub")
		break;
		return Intrinsic::hexagon_A2_vrsadub; // "__builtin_HEXAG
		ON.A2.vrsadub"
		}
		break;
		case 's': // 2 strings to match.
		if (BuiltinName.substr(23, 3) != "ubu")
		break;
		switch (BuiltinName[26]) {
		default: break;
		case 'b': // 1 string to match.
		if (BuiltinName[27] != 's')
		break;
		return Intrinsic::hexagon_A2_vsububs; // "__builtin_HEXAG
		ON.A2.vsububs"
		case 'h': // 1 string to match.
		if (BuiltinName[27] != 's')
		break;
		return Intrinsic::hexagon_A2_vsubuhs; // "__builtin_HEXAG
		ON.A2.vsubuhs"
		}
		break;
		}
		break;
		}
		break;
		case '4': // 2 strings to match.
		if (BuiltinName.substr(20, 5) != ".rcmp")
		break;
		switch (BuiltinName[25]) {
		default: break;
		case 'e': // 1 string to match.
		if (BuiltinName.substr(26, 2) != "qi")
		break;
		return Intrinsic::hexagon_A4_rcmpeqi; // "__builtin_HEXAG
		ON.A4.rcmpeqi"
		case 'n': // 1 string to match.
		if (BuiltinName.substr(26, 2) != "eq")
		break;
		return Intrinsic::hexagon_A4_rcmpneq; // "__builtin_HEXAG
		ON.A4.rcmpneq"
		}
		break;
		}
		break;
		case 'C': // 12 strings to match.
		switch (BuiltinName[19]) {
		default: break;
		case '2': // 6 strings to match.
		if (BuiltinName[20] != '.')
		break;
		switch (BuiltinName[21]) {
		default: break;
		case 'b': // 2 strings to match.
		if (BuiltinName.substr(22, 3) != "its")
		break;
		switch (BuiltinName[25]) {
		default: break;
		case 'c': // 1 string to match.
		if (BuiltinName.substr(26, 2) != "lr")
		break;
		return Intrinsic::hexagon_C2_bitsclr; // "__builtin_HEXAG
		ON.C2.bitsclr"
		case 's': // 1 string to match.
		if (BuiltinName.substr(26, 2) != "et")
		break;
		return Intrinsic::hexagon_C2_bitsset; // "__builtin_HEXAG
		ON.C2.bitsset"
		}
		break;
		case 'c': // 3 strings to match.
		if (BuiltinName.substr(22, 3) != "mpg")
		break;
		switch (BuiltinName[25]) {
		default: break;
		case 'e': // 1 string to match.
		if (BuiltinName.substr(26, 2) != "ui")
		break;
		return Intrinsic::hexagon_C2_cmpgeui; // "__builtin_HEXAG
		ON.C2.cmpgeui"
		case 't': // 2 strings to match.
		if (BuiltinName[26] != 'u')
		break;
		switch (BuiltinName[27]) {
		default: break;
		case 'i': // 1 string to match.
		return Intrinsic::hexagon_C2_cmpgtui; // "__builtin_HEXAG
		ON.C2.cmpgtui"
		case 'p': // 1 string to match.
		return Intrinsic::hexagon_C2_cmpgtup; // "__builtin_HEXAG
		ON.C2.cmpgtup"
		}
		break;
		}
		break;
		case 'v': // 1 string to match.
		if (BuiltinName.substr(22, 6) != "itpack")
		break;
		return Intrinsic::hexagon_C2_vitpack; // "__builtin_HEXAG
		ON.C2.vitpack"
		}
		break;
		case '4': // 6 strings to match.
		if (BuiltinName[20] != '.')
		break;
		switch (BuiltinName[21]) {
		default: break;
		case 'a': // 2 strings to match.
		if (BuiltinName.substr(22, 3) != "nd_")
		break;
		switch (BuiltinName[25]) {
		default: break;
		case 'a': // 1 string to match.
		if (BuiltinName.substr(26, 2) != "nd")
		break;
		return Intrinsic::hexagon_C4_and_and; // "__builtin_HEXAG
		ON.C4.and_and"
		case 'o': // 1 string to match.
		if (BuiltinName.substr(26, 2) != "rn")
		break;
		return Intrinsic::hexagon_C4_and_orn; // "__builtin_HEXAG
		ON.C4.and_orn"
		}
		break;
		case 'c': // 3 strings to match.
		if (BuiltinName.substr(22, 2) != "mp")
		break;
		switch (BuiltinName[24]) {
		default: break;
		case 'l': // 2 strings to match.
		if (BuiltinName.substr(25, 2) != "te")
		break;
		switch (BuiltinName[27]) {
		default: break;
		case 'i': // 1 string to match.
		return Intrinsic::hexagon_C4_cmpltei; // "__builtin_HEXAG
		ON.C4.cmpltei"
		case 'u': // 1 string to match.
		return Intrinsic::hexagon_C4_cmplteu; // "__builtin_HEXAG
		ON.C4.cmplteu"
		}
		break;
		case 'n': // 1 string to match.
		if (BuiltinName.substr(25, 3) != "eqi")
		break;
		return Intrinsic::hexagon_C4_cmpneqi; // "__builtin_HEXAG
		ON.C4.cmpneqi"
		}
		break;
		case 'o': // 1 string to match.
		if (BuiltinName.substr(22, 6) != "r_andn")
		break;
		return Intrinsic::hexagon_C4_or_andn; // "__builtin_HEXAG
		ON.C4.or_andn"
		}
		break;
		}
		break;
		case 'M': // 7 strings to match.
		switch (BuiltinName[19]) {
		default: break;
		case '2': // 3 strings to match.
		if (BuiltinName[20] != '.')
		break;
		switch (BuiltinName[21]) {
		default: break;
		case 'm': // 1 string to match.
		if (BuiltinName.substr(22, 6) != "pyu.up")
		break;
		return Intrinsic::hexagon_M2_mpyu_up; // "__builtin_HEXAG
		ON.M2.mpyu.up"
		case 'v': // 2 strings to match.
		switch (BuiltinName[22]) {
		default: break;
		case 'm': // 1 string to match.
		if (BuiltinName.substr(23, 5) != "ac2es")
		break;
		return Intrinsic::hexagon_M2_vmac2es; // "__builtin_HEXAG
		ON.M2.vmac2es"
		case 'r': // 1 string to match.
		if (BuiltinName.substr(23, 5) != "adduh")
		break;
		return Intrinsic::hexagon_M2_vradduh; // "__builtin_HEXAG
		ON.M2.vradduh"
		}
		break;
		}
		break;
		case '4': // 4 strings to match.
		if (BuiltinName[20] != '.')
		break;
		switch (BuiltinName[21]) {
		default: break;
		case 'a': // 2 strings to match.
		if (BuiltinName.substr(22, 3) != "nd_")
		break;
		switch (BuiltinName[25]) {
		default: break;
		case 'a': // 1 string to match.
		if (BuiltinName.substr(26, 2) != "nd")
		break;
		return Intrinsic::hexagon_M4_and_and; // "__builtin_HEXAG
		ON.M4.and_and"
		case 'x': // 1 string to match.
		if (BuiltinName.substr(26, 2) != "or")
		break;
		return Intrinsic::hexagon_M4_and_xor; // "__builtin_HEXAG
		ON.M4.and_xor"
		}
		break;
		case 'o': // 1 string to match.
		if (BuiltinName.substr(22, 6) != "r_andn")
		break;
		return Intrinsic::hexagon_M4_or_andn; // "__builtin_HEXAG
		ON.M4.or_andn"
		case 'x': // 1 string to match.
		if (BuiltinName.substr(22, 6) != "or_and")
		break;
		return Intrinsic::hexagon_M4_xor_and; // "__builtin_HEXAG
		ON.M4.xor_and"
		}
		break;
		}
		break;
		case 'S': // 27 strings to match.
		switch (BuiltinName[19]) {
		default: break;
		case '2': // 24 strings to match.
		if (BuiltinName[20] != '.')
		break;
		switch (BuiltinName[21]) {
		default: break;
		case 'a': // 8 strings to match.
		if (BuiltinName[22] != 's')
		break;
		switch (BuiltinName[23]) {
		default: break;
		case 'l': // 4 strings to match.
		if (BuiltinName[24] != '.')
		break;
		switch (BuiltinName[25]) {
		default: break;
		case 'i': // 2 strings to match.
		if (BuiltinName[26] != '.')
		break;
		switch (BuiltinName[27]) {
		default: break;
		case 'p': // 1 string to match.
		return Intrinsic::hexagon_S2_asl_i_p; // "__builtin_HEXAG
		ON.S2.asl.i.p"
		case 'r': // 1 string to match.
		return Intrinsic::hexagon_S2_asl_i_r; // "__builtin_HEXAG
		ON.S2.asl.i.r"
		}
		break;
		case 'r': // 2 strings to match.
		if (BuiltinName[26] != '.')
		break;
		switch (BuiltinName[27]) {
		default: break;
		case 'p': // 1 string to match.
		return Intrinsic::hexagon_S2_asl_r_p; // "__builtin_HEXAG
		ON.S2.asl.r.p"
		case 'r': // 1 string to match.
		return Intrinsic::hexagon_S2_asl_r_r; // "__builtin_HEXAG
		ON.S2.asl.r.r"
		}
		break;
		}
		break;
		case 'r': // 4 strings to match.
		if (BuiltinName[24] != '.')
		break;
		switch (BuiltinName[25]) {
		default: break;
		case 'i': // 2 strings to match.
		if (BuiltinName[26] != '.')
		break;
		switch (BuiltinName[27]) {
		default: break;
		case 'p': // 1 string to match.
		return Intrinsic::hexagon_S2_asr_i_p; // "__builtin_HEXAG
		ON.S2.asr.i.p"
		case 'r': // 1 string to match.
		return Intrinsic::hexagon_S2_asr_i_r; // "__builtin_HEXAG
		ON.S2.asr.i.r"
		}
		break;
		case 'r': // 2 strings to match.
		if (BuiltinName[26] != '.')
		break;
		switch (BuiltinName[27]) {
		default: break;
		case 'p': // 1 string to match.
		return Intrinsic::hexagon_S2_asr_r_p; // "__builtin_HEXAG
		ON.S2.asr.r.p"
		case 'r': // 1 string to match.
		return Intrinsic::hexagon_S2_asr_r_r; // "__builtin_HEXAG
		ON.S2.asr.r.r"
		}
		break;
		}
		break;
		}
		break;
		case 'c': // 1 string to match.
		if (BuiltinName.substr(22, 6) != "lbnorm")
		break;
		return Intrinsic::hexagon_S2_clbnorm; // "__builtin_HEXAG
		ON.S2.clbnorm"
		case 'i': // 1 string to match.
		if (BuiltinName.substr(22, 6) != "nsertp")
		break;
		return Intrinsic::hexagon_S2_insertp; // "__builtin_HEXAG
		ON.S2.insertp"
		case 'l': // 6 strings to match.
		if (BuiltinName[22] != 's')
		break;
		switch (BuiltinName[23]) {
		default: break;
		case 'l': // 2 strings to match.
		if (BuiltinName.substr(24, 3) != ".r.")
		break;
		switch (BuiltinName[27]) {
		default: break;
		case 'p': // 1 string to match.
		return Intrinsic::hexagon_S2_lsl_r_p; // "__builtin_HEXAG
		ON.S2.lsl.r.p"
		case 'r': // 1 string to match.
		return Intrinsic::hexagon_S2_lsl_r_r; // "__builtin_HEXAG
		ON.S2.lsl.r.r"
		}
		break;
		case 'r': // 4 strings to match.
		if (BuiltinName[24] != '.')
		break;
		switch (BuiltinName[25]) {
		default: break;
		case 'i': // 2 strings to match.
		if (BuiltinName[26] != '.')
		break;
		switch (BuiltinName[27]) {
		default: break;
		case 'p': // 1 string to match.
		return Intrinsic::hexagon_S2_lsr_i_p; // "__builtin_HEXAG
		ON.S2.lsr.i.p"
		case 'r': // 1 string to match.
		return Intrinsic::hexagon_S2_lsr_i_r; // "__builtin_HEXAG
		ON.S2.lsr.i.r"
		}
		break;
		case 'r': // 2 strings to match.
		if (BuiltinName[26] != '.')
		break;
		switch (BuiltinName[27]) {
		default: break;
		case 'p': // 1 string to match.
		return Intrinsic::hexagon_S2_lsr_r_p; // "__builtin_HEXAG
		ON.S2.lsr.r.p"
		case 'r': // 1 string to match.
		return Intrinsic::hexagon_S2_lsr_r_r; // "__builtin_HEXAG
		ON.S2.lsr.r.r"
		}
		break;
		}
		break;
		}
		break;
		case 'p': // 1 string to match.
		if (BuiltinName.substr(22, 6) != "arityp")
		break;
		return Intrinsic::hexagon_S2_parityp; // "__builtin_HEXAG
		ON.S2.parityp"
		case 's': // 5 strings to match.
		switch (BuiltinName[22]) {
		default: break;
		case 'h': // 4 strings to match.
		if (BuiltinName.substr(23, 3) != "uff")
		break;
		switch (BuiltinName[26]) {
		default: break;
		case 'e': // 2 strings to match.
		switch (BuiltinName[27]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::hexagon_S2_shuffeb; // "__builtin_HEXAG
		ON.S2.shuffeb"
		case 'h': // 1 string to match.
		return Intrinsic::hexagon_S2_shuffeh; // "__builtin_HEXAG
		ON.S2.shuffeh"
		}
		break;
		case 'o': // 2 strings to match.
		switch (BuiltinName[27]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::hexagon_S2_shuffob; // "__builtin_HEXAG
		ON.S2.shuffob"
		case 'h': // 1 string to match.
		return Intrinsic::hexagon_S2_shuffoh; // "__builtin_HEXAG
		ON.S2.shuffoh"
		}
		break;
		}
		break;
		case 'v': // 1 string to match.
		if (BuiltinName.substr(23, 5) != "sathb")
		break;
		return Intrinsic::hexagon_S2_svsathb; // "__builtin_HEXAG
		ON.S2.svsathb"
		}
		break;
		case 'v': // 2 strings to match.
		if (BuiltinName.substr(22, 3) != "sat")
		break;
		switch (BuiltinName[25]) {
		default: break;
		case 'h': // 1 string to match.
		if (BuiltinName.substr(26, 2) != "ub")
		break;
		return Intrinsic::hexagon_S2_vsathub; // "__builtin_HEXAG
		ON.S2.vsathub"
		case 'w': // 1 string to match.
		if (BuiltinName.substr(26, 2) != "uh")
		break;
		return Intrinsic::hexagon_S2_vsatwuh; // "__builtin_HEXAG
		ON.S2.vsatwuh"
		}
		break;
		}
		break;
		case '4': // 3 strings to match.
		if (BuiltinName[20] != '.')
		break;
		switch (BuiltinName[21]) {
		default: break;
		case 'a': // 1 string to match.
		if (BuiltinName.substr(22, 6) != "ddaddi")
		break;
		return Intrinsic::hexagon_S4_addaddi; // "__builtin_HEXAG
		ON.S4.addaddi"
		case 'o': // 1 string to match.
		if (BuiltinName.substr(22, 6) != "r_andi")
		break;
		return Intrinsic::hexagon_S4_or_andi; // "__builtin_HEXAG
		ON.S4.or_andi"
		case 's': // 1 string to match.
		if (BuiltinName.substr(22, 6) != "ubaddi")
		break;
		return Intrinsic::hexagon_S4_subaddi; // "__builtin_HEXAG
		ON.S4.subaddi"
		}
		break;
		}
		break;
		}
	break;	break;

	case Intrinsic::x86_3dnow_pf2id: // llvm.x86.3dnow.pf2id	case 29: // 69 strings to match.
	case Intrinsic::x86_3dnow_pfrcp: // llvm.x86.3dnow.pfrcp	if (BuiltinName.substr(0, 18) != "__builtin_HEXAGON.")
	case Intrinsic::x86_3dnow_pfrsqrt: // llvm.x86.3dnow.pfrsqrt	break;
	case Intrinsic::x86_3dnow_pi2fd: // llvm.x86.3dnow.pi2fd	switch (BuiltinName[18]) {
	case Intrinsic::x86_3dnowa_pf2iw: // llvm.x86.3dnowa.pf2iw	default: break;
	case Intrinsic::x86_3dnowa_pi2fw: // llvm.x86.3dnowa.pi2fw	case 'A': // 14 strings to match.
	case Intrinsic::x86_3dnowa_pswapd: // llvm.x86.3dnowa.pswapd	switch (BuiltinName[19]) {
	case Intrinsic::x86_ssse3_pabs_b: // llvm.x86.ssse3.pabs.b	default: break;
	case Intrinsic::x86_ssse3_pabs_d: // llvm.x86.ssse3.pabs.d	case '2': // 10 strings to match.
	case Intrinsic::x86_ssse3_pabs_w: // llvm.x86.ssse3.pabs.w	if (BuiltinName[20] != '.')
	ResultTy = Type::getX86_MMXTy(Context);	break;
	ArgTys.push_back(Type::getX86_MMXTy(Context));	switch (BuiltinName[21]) {
		default: break;
		case 'c': // 1 string to match.
		if (BuiltinName.substr(22, 7) != "ombinew")
		break;
		return Intrinsic::hexagon_A2_combinew; // "__builtin_HEXAG
		ON.A2.combinew"
		case 's': // 2 strings to match.
		if (BuiltinName[22] != 'v')
		break;
		switch (BuiltinName[23]) {
		default: break;
		case 'a': // 1 string to match.
		if (BuiltinName.substr(24, 5) != "dduhs")
		break;
		return Intrinsic::hexagon_A2_svadduhs; // "__builtin_HEXAG
		ON.A2.svadduhs"
		case 's': // 1 string to match.
		if (BuiltinName.substr(24, 5) != "ubuhs")
		break;
		return Intrinsic::hexagon_A2_svsubuhs; // "__builtin_HEXAG
		ON.A2.svsubuhs"
		}
		break;
		case 'v': // 7 strings to match.
		switch (BuiltinName[22]) {
		default: break;
		case 'a': // 2 strings to match.
		if (BuiltinName.substr(23, 2) != "bs")
		break;
		switch (BuiltinName[25]) {
		default: break;
		case 'h': // 1 string to match.
		if (BuiltinName.substr(26, 3) != "sat")
		break;
		return Intrinsic::hexagon_A2_vabshsat; // "__builtin_HEXAG
		ON.A2.vabshsat"
		case 'w': // 1 string to match.
		if (BuiltinName.substr(26, 3) != "sat")
		break;
		return Intrinsic::hexagon_A2_vabswsat; // "__builtin_HEXAG
		ON.A2.vabswsat"
		}
		break;
		case 'c': // 3 strings to match.
		if (BuiltinName.substr(23, 2) != "mp")
		break;
		switch (BuiltinName[25]) {
		default: break;
		case 'b': // 1 string to match.
		if (BuiltinName.substr(26, 3) != "gtu")
		break;
		return Intrinsic::hexagon_A2_vcmpbgtu; // "__builtin_HEXAG
		ON.A2.vcmpbgtu"
		case 'h': // 1 string to match.
		if (BuiltinName.substr(26, 3) != "gtu")
		break;
		return Intrinsic::hexagon_A2_vcmphgtu; // "__builtin_HEXAG
		ON.A2.vcmphgtu"
		case 'w': // 1 string to match.
		if (BuiltinName.substr(26, 3) != "gtu")
		break;
		return Intrinsic::hexagon_A2_vcmpwgtu; // "__builtin_HEXAG
		ON.A2.vcmpwgtu"
		}
		break;
		case 'n': // 2 strings to match.
		if (BuiltinName.substr(23, 3) != "avg")
		break;
		switch (BuiltinName[26]) {
		default: break;
		case 'h': // 1 string to match.
		if (BuiltinName.substr(27, 2) != "cr")
		break;
		return Intrinsic::hexagon_A2_vnavghcr; // "__builtin_HEXAG
		ON.A2.vnavghcr"
		case 'w': // 1 string to match.
		if (BuiltinName.substr(27, 2) != "cr")
		break;
		return Intrinsic::hexagon_A2_vnavgwcr; // "__builtin_HEXAG
		ON.A2.vnavgwcr"
		}
		break;
		}
		break;
		}
		break;
		case '4': // 4 strings to match.
		if (BuiltinName[20] != '.')
		break;
		switch (BuiltinName[21]) {
		default: break;
		case 'm': // 1 string to match.
		if (BuiltinName.substr(22, 7) != "odwrapu")
		break;
		return Intrinsic::hexagon_A4_modwrapu; // "__builtin_HEXAG
		ON.A4.modwrapu"
		case 'r': // 3 strings to match.
		switch (BuiltinName[22]) {
		default: break;
		case 'c': // 1 string to match.
		if (BuiltinName.substr(23, 6) != "mpneqi")
		break;
		return Intrinsic::hexagon_A4_rcmpneqi; // "__builtin_HEXAG
		ON.A4.rcmpneqi"
		case 'o': // 2 strings to match.
		if (BuiltinName.substr(23, 5) != "und_r")
		break;
		switch (BuiltinName[28]) {
		default: break;
		case 'i': // 1 string to match.
		return Intrinsic::hexagon_A4_round_ri; // "__builtin_HEXAG
		ON.A4.round_ri"
		case 'r': // 1 string to match.
		return Intrinsic::hexagon_A4_round_rr; // "__builtin_HEXAG
		ON.A4.round_rr"
		}
		break;
		}
		break;
		}
		break;
		}
		break;
		case 'C': // 3 strings to match.
		switch (BuiltinName[19]) {
		default: break;
		case '2': // 1 string to match.
		if (BuiltinName.substr(20, 9) != ".bitsclri")
		break;
		return Intrinsic::hexagon_C2_bitsclri; // "__builtin_HEXAGON.C2.bi
		tsclri"
		case '4': // 2 strings to match.
		if (BuiltinName[20] != '.')
		break;
		switch (BuiltinName[21]) {
		default: break;
		case 'a': // 1 string to match.
		if (BuiltinName.substr(22, 7) != "nd_andn")
		break;
		return Intrinsic::hexagon_C4_and_andn; // "__builtin_HEXAG
		ON.C4.and_andn"
		case 'c': // 1 string to match.
		if (BuiltinName.substr(22, 7) != "mplteui")
		break;
		return Intrinsic::hexagon_C4_cmplteui; // "__builtin_HEXAG
		ON.C4.cmplteui"
		}
		break;
		}
		break;
		case 'M': // 20 strings to match.
		switch (BuiltinName[19]) {
		default: break;
		case '2': // 17 strings to match.
		if (BuiltinName[20] != '.')
		break;
		switch (BuiltinName[21]) {
		default: break;
		case 'c': // 10 strings to match.
		switch (BuiltinName[22]) {
		default: break;
		case 'm': // 8 strings to match.
		switch (BuiltinName[23]) {
		default: break;
		case 'a': // 4 strings to match.
		if (BuiltinName[24] != 'c')
		break;
		switch (BuiltinName[25]) {
		default: break;
		case 'i': // 1 string to match.
		if (BuiltinName.substr(26, 3) != ".s0")
		break;
		return Intrinsic::hexagon_M2_cmaci_s0; // "__builtin_HEXAG
		ON.M2.cmaci.s0"
		case 'r': // 1 string to match.
		if (BuiltinName.substr(26, 3) != ".s0")
		break;
		return Intrinsic::hexagon_M2_cmacr_s0; // "__builtin_HEXAG
		ON.M2.cmacr.s0"
		case 's': // 2 strings to match.
		if (BuiltinName.substr(26, 2) != ".s")
		break;
		switch (BuiltinName[28]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_cmacs_s0; // "__built
		in_HEXAGON.M2.cmacs.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_cmacs_s1; // "__built
		in_HEXAGON.M2.cmacs.s1"
		}
		break;
		}
		break;
		case 'p': // 4 strings to match.
		if (BuiltinName[24] != 'y')
		break;
		switch (BuiltinName[25]) {
		default: break;
		case 'i': // 1 string to match.
		if (BuiltinName.substr(26, 3) != ".s0")
		break;
		return Intrinsic::hexagon_M2_cmpyi_s0; // "__builtin_HEXAG
		ON.M2.cmpyi.s0"
		case 'r': // 1 string to match.
		if (BuiltinName.substr(26, 3) != ".s0")
		break;
		return Intrinsic::hexagon_M2_cmpyr_s0; // "__builtin_HEXAG
		ON.M2.cmpyr.s0"
		case 's': // 2 strings to match.
		if (BuiltinName.substr(26, 2) != ".s")
		break;
		switch (BuiltinName[28]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_cmpys_s0; // "__built
		in_HEXAGON.M2.cmpys.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_cmpys_s1; // "__built
		in_HEXAGON.M2.cmpys.s1"
		}
		break;
		}
		break;
		}
		break;
		case 'n': // 2 strings to match.
		if (BuiltinName.substr(23, 5) != "acs.s")
		break;
		switch (BuiltinName[28]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_cnacs_s0; // "__builtin_HEXAG
		ON.M2.cnacs.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_cnacs_s1; // "__builtin_HEXAG
		ON.M2.cnacs.s1"
		}
		break;
		}
		break;
		case 'm': // 4 strings to match.
		if (BuiltinName.substr(22, 3) != "mpy")
		break;
		switch (BuiltinName[25]) {
		default: break;
		case 'h': // 2 strings to match.
		if (BuiltinName.substr(26, 2) != ".s")
		break;
		switch (BuiltinName[28]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mmpyh_s0; // "__builtin_HEXAG
		ON.M2.mmpyh.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mmpyh_s1; // "__builtin_HEXAG
		ON.M2.mmpyh.s1"
		}
		break;
		case 'l': // 2 strings to match.
		if (BuiltinName.substr(26, 2) != ".s")
		break;
		switch (BuiltinName[28]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mmpyl_s0; // "__builtin_HEXAG
		ON.M2.mmpyl.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mmpyl_s1; // "__builtin_HEXAG
		ON.M2.mmpyl.s1"
		}
		break;
		}
		break;
		case 'v': // 2 strings to match.
		if (BuiltinName.substr(22, 2) != "rm")
		break;
		switch (BuiltinName[24]) {
		default: break;
		case 'a': // 1 string to match.
		if (BuiltinName.substr(25, 4) != "c.s0")
		break;
		return Intrinsic::hexagon_M2_vrmac_s0; // "__builtin_HEXAG
		ON.M2.vrmac.s0"
		case 'p': // 1 string to match.
		if (BuiltinName.substr(25, 4) != "y.s0")
		break;
		return Intrinsic::hexagon_M2_vrmpy_s0; // "__builtin_HEXAG
		ON.M2.vrmpy.s0"
		}
		break;
		case 'x': // 1 string to match.
		if (BuiltinName.substr(22, 7) != "or.xacc")
		break;
		return Intrinsic::hexagon_M2_xor_xacc; // "__builtin_HEXAG
		ON.M2.xor.xacc"
		}
		break;
		case '4': // 3 strings to match.
		if (BuiltinName[20] != '.')
		break;
		switch (BuiltinName[21]) {
		default: break;
		case 'a': // 1 string to match.
		if (BuiltinName.substr(22, 7) != "nd_andn")
		break;
		return Intrinsic::hexagon_M4_and_andn; // "__builtin_HEXAG
		ON.M4.and_andn"
		case 'x': // 2 strings to match.
		if (BuiltinName.substr(22, 3) != "or_")
		break;
		switch (BuiltinName[25]) {
		default: break;
		case 'a': // 1 string to match.
		if (BuiltinName.substr(26, 3) != "ndn")
		break;
		return Intrinsic::hexagon_M4_xor_andn; // "__builtin_HEXAG
		ON.M4.xor_andn"
		case 'x': // 1 string to match.
		if (BuiltinName.substr(26, 3) != "acc")
		break;
		return Intrinsic::hexagon_M4_xor_xacc; // "__builtin_HEXAG
		ON.M4.xor_xacc"
		}
		break;
		}
		break;
		}
		break;
		case 'S': // 32 strings to match.
		switch (BuiltinName[19]) {
		default: break;
		case '2': // 31 strings to match.
		if (BuiltinName[20] != '.')
		break;
		switch (BuiltinName[21]) {
		default: break;
		case 'a': // 8 strings to match.
		if (BuiltinName[22] != 's')
		break;
		switch (BuiltinName[23]) {
		default: break;
		case 'l': // 4 strings to match.
		if (BuiltinName[24] != '.')
		break;
		switch (BuiltinName[25]) {
		default: break;
		case 'i': // 2 strings to match.
		if (BuiltinName.substr(26, 2) != ".v")
		break;
		switch (BuiltinName[28]) {
		default: break;
		case 'h': // 1 string to match.
		return Intrinsic::hexagon_S2_asl_i_vh; // "__builtin_HEXAG
		ON.S2.asl.i.vh"
		case 'w': // 1 string to match.
		return Intrinsic::hexagon_S2_asl_i_vw; // "__builtin_HEXAG
		ON.S2.asl.i.vw"
		}
		break;
		case 'r': // 2 strings to match.
		if (BuiltinName.substr(26, 2) != ".v")
		break;
		switch (BuiltinName[28]) {
		default: break;
		case 'h': // 1 string to match.
		return Intrinsic::hexagon_S2_asl_r_vh; // "__builtin_HEXAG
		ON.S2.asl.r.vh"
		case 'w': // 1 string to match.
		return Intrinsic::hexagon_S2_asl_r_vw; // "__builtin_HEXAG
		ON.S2.asl.r.vw"
		}
		break;
		}
		break;
		case 'r': // 4 strings to match.
		if (BuiltinName[24] != '.')
		break;
		switch (BuiltinName[25]) {
		default: break;
		case 'i': // 2 strings to match.
		if (BuiltinName.substr(26, 2) != ".v")
		break;
		switch (BuiltinName[28]) {
		default: break;
		case 'h': // 1 string to match.
		return Intrinsic::hexagon_S2_asr_i_vh; // "__builtin_HEXAG
		ON.S2.asr.i.vh"
		case 'w': // 1 string to match.
		return Intrinsic::hexagon_S2_asr_i_vw; // "__builtin_HEXAG
		ON.S2.asr.i.vw"
		}
		break;
		case 'r': // 2 strings to match.
		if (BuiltinName.substr(26, 2) != ".v")
		break;
		switch (BuiltinName[28]) {
		default: break;
		case 'h': // 1 string to match.
		return Intrinsic::hexagon_S2_asr_r_vh; // "__builtin_HEXAG
		ON.S2.asr.r.vh"
		case 'w': // 1 string to match.
		return Intrinsic::hexagon_S2_asr_r_vw; // "__builtin_HEXAG
		ON.S2.asr.r.vw"
		}
		break;
		}
		break;
		}
		break;
		case 'c': // 2 strings to match.
		if (BuiltinName.substr(22, 6) != "lrbit.")
		break;
		switch (BuiltinName[28]) {
		default: break;
		case 'i': // 1 string to match.
		return Intrinsic::hexagon_S2_clrbit_i; // "__builtin_HEXAG
		ON.S2.clrbit.i"
		case 'r': // 1 string to match.
		return Intrinsic::hexagon_S2_clrbit_r; // "__builtin_HEXAG
		ON.S2.clrbit.r"
		}
		break;
		case 'e': // 1 string to match.
		if (BuiltinName.substr(22, 7) != "xtractu")
		break;
		return Intrinsic::hexagon_S2_extractu; // "__builtin_HEXAG
		ON.S2.extractu"
		case 'l': // 6 strings to match.
		if (BuiltinName[22] != 's')
		break;
		switch (BuiltinName[23]) {
		default: break;
		case 'l': // 2 strings to match.
		if (BuiltinName.substr(24, 4) != ".r.v")
		break;
		switch (BuiltinName[28]) {
		default: break;
		case 'h': // 1 string to match.
		return Intrinsic::hexagon_S2_lsl_r_vh; // "__builtin_HEXAG
		ON.S2.lsl.r.vh"
		case 'w': // 1 string to match.
		return Intrinsic::hexagon_S2_lsl_r_vw; // "__builtin_HEXAG
		ON.S2.lsl.r.vw"
		}
		break;
		case 'r': // 4 strings to match.
		if (BuiltinName[24] != '.')
		break;
		switch (BuiltinName[25]) {
		default: break;
		case 'i': // 2 strings to match.
		if (BuiltinName.substr(26, 2) != ".v")
		break;
		switch (BuiltinName[28]) {
		default: break;
		case 'h': // 1 string to match.
		return Intrinsic::hexagon_S2_lsr_i_vh; // "__builtin_HEXAG
		ON.S2.lsr.i.vh"
		case 'w': // 1 string to match.
		return Intrinsic::hexagon_S2_lsr_i_vw; // "__builtin_HEXAG
		ON.S2.lsr.i.vw"
		}
		break;
		case 'r': // 2 strings to match.
		if (BuiltinName.substr(26, 2) != ".v")
		break;
		switch (BuiltinName[28]) {
		default: break;
		case 'h': // 1 string to match.
		return Intrinsic::hexagon_S2_lsr_r_vh; // "__builtin_HEXAG
		ON.S2.lsr.r.vh"
		case 'w': // 1 string to match.
		return Intrinsic::hexagon_S2_lsr_r_vw; // "__builtin_HEXAG
		ON.S2.lsr.r.vw"
		}
		break;
		}
		break;
		}
		break;
		case 's': // 3 strings to match.
		switch (BuiltinName[22]) {
		default: break;
		case 'e': // 2 strings to match.
		if (BuiltinName.substr(23, 5) != "tbit.")
		break;
		switch (BuiltinName[28]) {
		default: break;
		case 'i': // 1 string to match.
		return Intrinsic::hexagon_S2_setbit_i; // "__builtin_HEXAG
		ON.S2.setbit.i"
		case 'r': // 1 string to match.
		return Intrinsic::hexagon_S2_setbit_r; // "__builtin_HEXAG
		ON.S2.setbit.r"
		}
		break;
		case 'v': // 1 string to match.
		if (BuiltinName.substr(23, 6) != "sathub")
		break;
		return Intrinsic::hexagon_S2_svsathub; // "__builtin_HEXAG
		ON.S2.svsathub"
		}
		break;
		case 't': // 2 strings to match.
		if (BuiltinName.substr(22, 6) != "stbit.")
		break;
		switch (BuiltinName[28]) {
		default: break;
		case 'i': // 1 string to match.
		return Intrinsic::hexagon_S2_tstbit_i; // "__builtin_HEXAG
		ON.S2.tstbit.i"
		case 'r': // 1 string to match.
		return Intrinsic::hexagon_S2_tstbit_r; // "__builtin_HEXAG
		ON.S2.tstbit.r"
		}
		break;
		case 'v': // 9 strings to match.
		switch (BuiltinName[22]) {
		default: break;
		case 'a': // 2 strings to match.
		if (BuiltinName.substr(23, 4) != "lign")
		break;
		switch (BuiltinName[27]) {
		default: break;
		case 'i': // 1 string to match.
		if (BuiltinName[28] != 'b')
		break;
		return Intrinsic::hexagon_S2_valignib; // "__builtin_HEXAG
		ON.S2.valignib"
		case 'r': // 1 string to match.
		if (BuiltinName[28] != 'b')
		break;
		return Intrinsic::hexagon_S2_valignrb; // "__builtin_HEXAG
		ON.S2.valignrb"
		}
		break;
		case 'c': // 1 string to match.
		if (BuiltinName.substr(23, 6) != "rotate")
		break;
		return Intrinsic::hexagon_S2_vcrotate; // "__builtin_HEXAG
		ON.S2.vcrotate"
		case 's': // 2 strings to match.
		if (BuiltinName.substr(23, 5) != "platr")
		break;
		switch (BuiltinName[28]) {
		default: break;
		case 'b': // 1 string to match.
		return Intrinsic::hexagon_S2_vsplatrb; // "__builtin_HEXAG
		ON.S2.vsplatrb"
		case 'h': // 1 string to match.
		return Intrinsic::hexagon_S2_vsplatrh; // "__builtin_HEXAG
		ON.S2.vsplatrh"
		}
		break;
		case 't': // 4 strings to match.
		if (BuiltinName.substr(23, 3) != "run")
		break;
		switch (BuiltinName[26]) {
		default: break;
		case 'e': // 2 strings to match.
		switch (BuiltinName[27]) {
		default: break;
		case 'h': // 1 string to match.
		if (BuiltinName[28] != 'b')
		break;
		return Intrinsic::hexagon_S2_vtrunehb; // "__builtin_HEXAG
		ON.S2.vtrunehb"
		case 'w': // 1 string to match.
		if (BuiltinName[28] != 'h')
		break;
		return Intrinsic::hexagon_S2_vtrunewh; // "__builtin_HEXAG
		ON.S2.vtrunewh"
		}
		break;
		case 'o': // 2 strings to match.
		switch (BuiltinName[27]) {
		default: break;
		case 'h': // 1 string to match.
		if (BuiltinName[28] != 'b')
		break;
		return Intrinsic::hexagon_S2_vtrunohb; // "__builtin_HEXAG
		ON.S2.vtrunohb"
		case 'w': // 1 string to match.
		if (BuiltinName[28] != 'h')
		break;
		return Intrinsic::hexagon_S2_vtrunowh; // "__builtin_HEXAG
		ON.S2.vtrunowh"
		}
		break;
		}
		break;
		}
		break;
		}
		break;
		case '4': // 1 string to match.
		if (BuiltinName.substr(20, 9) != ".or_andix")
		break;
		return Intrinsic::hexagon_S4_or_andix; // "__builtin_HEXAGON.S4.or
		_andix"
		}
		break;
		}
	break;	break;

	case Intrinsic::x86_mmx_pslli_d: // llvm.x86.mmx.pslli.d	case 30: // 48 strings to match.
	case Intrinsic::x86_mmx_pslli_q: // llvm.x86.mmx.pslli.q	if (BuiltinName.substr(0, 18) != "__builtin_HEXAGON.")
	case Intrinsic::x86_mmx_pslli_w: // llvm.x86.mmx.pslli.w	break;
	case Intrinsic::x86_mmx_psrai_d: // llvm.x86.mmx.psrai.d	switch (BuiltinName[18]) {
	case Intrinsic::x86_mmx_psrai_w: // llvm.x86.mmx.psrai.w	default: break;
	case Intrinsic::x86_mmx_psrli_d: // llvm.x86.mmx.psrli.d	case 'A': // 5 strings to match.
	case Intrinsic::x86_mmx_psrli_q: // llvm.x86.mmx.psrli.q	switch (BuiltinName[19]) {
	case Intrinsic::x86_mmx_psrli_w: // llvm.x86.mmx.psrli.w	default: break;
	ResultTy = Type::getX86_MMXTy(Context);	case '2': // 1 string to match.
	ArgTys.push_back(Type::getX86_MMXTy(Context));	if (BuiltinName.substr(20, 10) != ".combineii")
	ArgTys.push_back(IntegerType::get(Context, 32));	break;
		return Intrinsic::hexagon_A2_combineii; // "__builtin_HEXAG
		ON.A2.combineii"
		case '4': // 4 strings to match.
		if (BuiltinName.substr(20, 2) != ".c")
		break;
		switch (BuiltinName[22]) {
		default: break;
		case 'o': // 2 strings to match.
		if (BuiltinName.substr(23, 5) != "mbine")
		break;
		switch (BuiltinName[28]) {
		default: break;
		case 'i': // 1 string to match.
		if (BuiltinName[29] != 'r')
		break;
		return Intrinsic::hexagon_A4_combineir; // "__builtin_HEXAG
		ON.A4.combineir"
		case 'r': // 1 string to match.
		if (BuiltinName[29] != 'i')
		break;
		return Intrinsic::hexagon_A4_combineri; // "__builtin_HEXAG
		ON.A4.combineri"
		}
		break;
		case 'r': // 2 strings to match.
		if (BuiltinName.substr(23, 6) != "ound_r")
		break;
		switch (BuiltinName[29]) {
		default: break;
		case 'i': // 1 string to match.
		return Intrinsic::hexagon_A4_cround_ri; // "__builtin_HEXAG
		ON.A4.cround_ri"
		case 'r': // 1 string to match.
		return Intrinsic::hexagon_A4_cround_rr; // "__builtin_HEXAG
		ON.A4.cround_rr"
		}
		break;
		}
		break;
		}
		break;
		case 'C': // 1 string to match.
		if (BuiltinName.substr(19, 11) != "2.pxfer.map")
		break;
		return Intrinsic::hexagon_C2_pxfer_map; // "__builtin_HEXAGON.C2.px
		fer.map"
		case 'M': // 38 strings to match.
		if (BuiltinName.substr(19, 2) != "2.")
		break;
		switch (BuiltinName[21]) {
		default: break;
		case 'c': // 8 strings to match.
		switch (BuiltinName[22]) {
		default: break;
		case 'm': // 6 strings to match.
		switch (BuiltinName[23]) {
		default: break;
		case 'a': // 2 strings to match.
		if (BuiltinName.substr(24, 5) != "csc.s")
		break;
		switch (BuiltinName[29]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_cmacsc_s0; // "__builtin_HEXAG
		ON.M2.cmacsc.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_cmacsc_s1; // "__builtin_HEXAG
		ON.M2.cmacsc.s1"
		}
		break;
		case 'p': // 4 strings to match.
		if (BuiltinName[24] != 'y')
		break;
		switch (BuiltinName[25]) {
		default: break;
		case 'r': // 2 strings to match.
		if (BuiltinName.substr(26, 3) != "s.s")
		break;
		switch (BuiltinName[29]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_cmpyrs_s0; // "__built
		in_HEXAGON.M2.cmpyrs.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_cmpyrs_s1; // "__built
		in_HEXAGON.M2.cmpyrs.s1"
		}
		break;
		case 's': // 2 strings to match.
		if (BuiltinName.substr(26, 3) != "c.s")
		break;
		switch (BuiltinName[29]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_cmpysc_s0; // "__built
		in_HEXAGON.M2.cmpysc.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_cmpysc_s1; // "__built
		in_HEXAGON.M2.cmpysc.s1"
		}
		break;
		}
		break;
		}
		break;
		case 'n': // 2 strings to match.
		if (BuiltinName.substr(23, 6) != "acsc.s")
		break;
		switch (BuiltinName[29]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_cnacsc_s0; // "__builtin_HEXAG
		ON.M2.cnacsc.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_cnacsc_s1; // "__builtin_HEXAG
		ON.M2.cnacsc.s1"
		}
		break;
		}
		break;
		case 'm': // 20 strings to match.
		switch (BuiltinName[22]) {
		default: break;
		case 'm': // 12 strings to match.
		switch (BuiltinName[23]) {
		default: break;
		case 'a': // 4 strings to match.
		if (BuiltinName[24] != 'c')
		break;
		switch (BuiltinName[25]) {
		default: break;
		case 'h': // 2 strings to match.
		if (BuiltinName.substr(26, 3) != "s.s")
		break;
		switch (BuiltinName[29]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mmachs_s0; // "__built
		in_HEXAGON.M2.mmachs.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mmachs_s1; // "__built
		in_HEXAGON.M2.mmachs.s1"
		}
		break;
		case 'l': // 2 strings to match.
		if (BuiltinName.substr(26, 3) != "s.s")
		break;
		switch (BuiltinName[29]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mmacls_s0; // "__built
		in_HEXAGON.M2.mmacls.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mmacls_s1; // "__built
		in_HEXAGON.M2.mmacls.s1"
		}
		break;
		}
		break;
		case 'p': // 8 strings to match.
		if (BuiltinName[24] != 'y')
		break;
		switch (BuiltinName[25]) {
		default: break;
		case 'h': // 2 strings to match.
		if (BuiltinName.substr(26, 3) != ".rs")
		break;
		switch (BuiltinName[29]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mmpyh_rs0; // "__built
		in_HEXAGON.M2.mmpyh.rs0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mmpyh_rs1; // "__built
		in_HEXAGON.M2.mmpyh.rs1"
		}
		break;
		case 'l': // 2 strings to match.
		if (BuiltinName.substr(26, 3) != ".rs")
		break;
		switch (BuiltinName[29]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mmpyl_rs0; // "__built
		in_HEXAGON.M2.mmpyl.rs0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mmpyl_rs1; // "__built
		in_HEXAGON.M2.mmpyl.rs1"
		}
		break;
		case 'u': // 4 strings to match.
		switch (BuiltinName[26]) {
		default: break;
		case 'h': // 2 strings to match.
		if (BuiltinName.substr(27, 2) != ".s")
		break;
		switch (BuiltinName[29]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mmpyuh_s0; // "__built
		in_HEXAGON.M2.mmpyuh.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mmpyuh_s1; // "__built
		in_HEXAGON.M2.mmpyuh.s1"
		}
		break;
		case 'l': // 2 strings to match.
		if (BuiltinName.substr(27, 2) != ".s")
		break;
		switch (BuiltinName[29]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mmpyul_s0; // "__built
		in_HEXAGON.M2.mmpyul.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mmpyul_s1; // "__built
		in_HEXAGON.M2.mmpyul.s1"
		}
		break;
		}
		break;
		}
		break;
		}
		break;
		case 'p': // 8 strings to match.
		if (BuiltinName.substr(23, 2) != "y.")
		break;
		switch (BuiltinName[25]) {
		default: break;
		case 'h': // 4 strings to match.
		switch (BuiltinName[26]) {
		default: break;
		case 'h': // 2 strings to match.
		if (BuiltinName.substr(27, 2) != ".s")
		break;
		switch (BuiltinName[29]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_hh_s0; // "__built
		in_HEXAGON.M2.mpy.hh.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_hh_s1; // "__built
		in_HEXAGON.M2.mpy.hh.s1"
		}
		break;
		case 'l': // 2 strings to match.
		if (BuiltinName.substr(27, 2) != ".s")
		break;
		switch (BuiltinName[29]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_hl_s0; // "__built
		in_HEXAGON.M2.mpy.hl.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_hl_s1; // "__built
		in_HEXAGON.M2.mpy.hl.s1"
		}
		break;
		}
		break;
		case 'l': // 4 strings to match.
		switch (BuiltinName[26]) {
		default: break;
		case 'h': // 2 strings to match.
		if (BuiltinName.substr(27, 2) != ".s")
		break;
		switch (BuiltinName[29]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_lh_s0; // "__built
		in_HEXAGON.M2.mpy.lh.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_lh_s1; // "__built
		in_HEXAGON.M2.mpy.lh.s1"
		}
		break;
		case 'l': // 2 strings to match.
		if (BuiltinName.substr(27, 2) != ".s")
		break;
		switch (BuiltinName[29]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_ll_s0; // "__built
		in_HEXAGON.M2.mpy.ll.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_ll_s1; // "__built
		in_HEXAGON.M2.mpy.ll.s1"
		}
		break;
		}
		break;
		}
		break;
		}
		break;
		case 'v': // 10 strings to match.
		switch (BuiltinName[22]) {
		default: break;
		case 'a': // 2 strings to match.
		if (BuiltinName.substr(23, 6) != "bsdiff")
		break;
		switch (BuiltinName[29]) {
		default: break;
		case 'h': // 1 string to match.
		return Intrinsic::hexagon_M2_vabsdiffh; // "__builtin_HEXAG
		ON.M2.vabsdiffh"
		case 'w': // 1 string to match.
		return Intrinsic::hexagon_M2_vabsdiffw; // "__builtin_HEXAG
		ON.M2.vabsdiffw"
		}
		break;
		case 'd': // 4 strings to match.
		if (BuiltinName[23] != 'm')
		break;
		switch (BuiltinName[24]) {
		default: break;
		case 'a': // 2 strings to match.
		if (BuiltinName.substr(25, 4) != "cs.s")
		break;
		switch (BuiltinName[29]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_vdmacs_s0; // "__builtin_HEXAG
		ON.M2.vdmacs.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_vdmacs_s1; // "__builtin_HEXAG
		ON.M2.vdmacs.s1"
		}
		break;
		case 'p': // 2 strings to match.
		if (BuiltinName.substr(25, 4) != "ys.s")
		break;
		switch (BuiltinName[29]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_vdmpys_s0; // "__builtin_HEXAG
		ON.M2.vdmpys.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_vdmpys_s1; // "__builtin_HEXAG
		ON.M2.vdmpys.s1"
		}
		break;
		}
		break;
		case 'm': // 4 strings to match.
		switch (BuiltinName[23]) {
		default: break;
		case 'a': // 2 strings to match.
		if (BuiltinName.substr(24, 5) != "c2s.s")
		break;
		switch (BuiltinName[29]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_vmac2s_s0; // "__builtin_HEXAG
		ON.M2.vmac2s.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_vmac2s_s1; // "__builtin_HEXAG
		ON.M2.vmac2s.s1"
		}
		break;
		case 'p': // 2 strings to match.
		if (BuiltinName.substr(24, 5) != "y2s.s")
		break;
		switch (BuiltinName[29]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_vmpy2s_s0; // "__builtin_HEXAG
		ON.M2.vmpy2s.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_vmpy2s_s1; // "__builtin_HEXAG
		ON.M2.vmpy2s.s1"
		}
		break;
		}
		break;
		}
		break;
		}
		break;
		case 'S': // 4 strings to match.
		if (BuiltinName.substr(19, 2) != "2.")
		break;
		switch (BuiltinName[21]) {
		default: break;
		case 'e': // 1 string to match.
		if (BuiltinName.substr(22, 8) != "xtractup")
		break;
		return Intrinsic::hexagon_S2_extractup; // "__builtin_HEXAG
		ON.S2.extractup"
		case 'i': // 1 string to match.
		if (BuiltinName.substr(22, 8) != "nsert.rp")
		break;
		return Intrinsic::hexagon_S2_insert_rp; // "__builtin_HEXAG
		ON.S2.insert.rp"
		case 'v': // 2 strings to match.
		if (BuiltinName.substr(22, 6) != "splice")
		break;
		switch (BuiltinName[28]) {
		default: break;
		case 'i': // 1 string to match.
		if (BuiltinName[29] != 'b')
		break;
		return Intrinsic::hexagon_S2_vspliceib; // "__builtin_HEXAG
		ON.S2.vspliceib"
		case 'r': // 1 string to match.
		if (BuiltinName[29] != 'b')
		break;
		return Intrinsic::hexagon_S2_vsplicerb; // "__builtin_HEXAG
		ON.S2.vsplicerb"
		}
		break;
		}
		break;
		}
	break;	break;

	case Intrinsic::x86_mmx_pinsr_w: // llvm.x86.mmx.pinsr.w	case 31: // 66 strings to match.
	ResultTy = Type::getX86_MMXTy(Context);	if (BuiltinName.substr(0, 18) != "__builtin_HEXAGON.")
	ArgTys.push_back(Type::getX86_MMXTy(Context));	break;
	ArgTys.push_back(IntegerType::get(Context, 32));	switch (BuiltinName[18]) {
	ArgTys.push_back(IntegerType::get(Context, 32));	default: break;
		case 'A': // 4 strings to match.
		if (BuiltinName.substr(19, 10) != "2.combine.")
		break;
		switch (BuiltinName[29]) {
		default: break;
		case 'h': // 2 strings to match.
		switch (BuiltinName[30]) {
		default: break;
		case 'h': // 1 string to match.
		return Intrinsic::hexagon_A2_combine_hh; // "__builtin_HEXAG
		ON.A2.combine.hh"
		case 'l': // 1 string to match.
		return Intrinsic::hexagon_A2_combine_hl; // "__builtin_HEXAG
		ON.A2.combine.hl"
		}
		break;
		case 'l': // 2 strings to match.
		switch (BuiltinName[30]) {
		default: break;
		case 'h': // 1 string to match.
		return Intrinsic::hexagon_A2_combine_lh; // "__builtin_HEXAG
		ON.A2.combine.lh"
		case 'l': // 1 string to match.
		return Intrinsic::hexagon_A2_combine_ll; // "__builtin_HEXAG
		ON.A2.combine.ll"
		}
		break;
		}
		break;
		case 'M': // 45 strings to match.
		if (BuiltinName.substr(19, 2) != "2.")
		break;
		switch (BuiltinName[21]) {
		default: break;
		case 'c': // 2 strings to match.
		if (BuiltinName.substr(22, 8) != "mpyrsc.s")
		break;
		switch (BuiltinName[30]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_cmpyrsc_s0; // "__builtin_HEXAG
		ON.M2.cmpyrsc.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_cmpyrsc_s1; // "__builtin_HEXAG
		ON.M2.cmpyrsc.s1"
		}
		break;
		case 'd': // 2 strings to match.
		if (BuiltinName.substr(22, 4) != "pmpy")
		break;
		switch (BuiltinName[26]) {
		default: break;
		case 's': // 1 string to match.
		if (BuiltinName.substr(27, 4) != "s.s0")
		break;
		return Intrinsic::hexagon_M2_dpmpyss_s0; // "__builtin_HEXAG
		ON.M2.dpmpyss.s0"
		case 'u': // 1 string to match.
		if (BuiltinName.substr(27, 4) != "u.s0")
		break;
		return Intrinsic::hexagon_M2_dpmpyuu_s0; // "__builtin_HEXAG
		ON.M2.dpmpyuu.s0"
		}
		break;
		case 'h': // 2 strings to match.
		if (BuiltinName.substr(22, 4) != "mmpy")
		break;
		switch (BuiltinName[26]) {
		default: break;
		case 'h': // 1 string to match.
		if (BuiltinName.substr(27, 4) != ".rs1")
		break;
		return Intrinsic::hexagon_M2_hmmpyh_rs1; // "__builtin_HEXAG
		ON.M2.hmmpyh.rs1"
		case 'l': // 1 string to match.
		if (BuiltinName.substr(27, 4) != ".rs1")
		break;
		return Intrinsic::hexagon_M2_hmmpyl_rs1; // "__builtin_HEXAG
		ON.M2.hmmpyl.rs1"
		}
		break;
		case 'm': // 28 strings to match.
		switch (BuiltinName[22]) {
		default: break;
		case 'm': // 12 strings to match.
		switch (BuiltinName[23]) {
		default: break;
		case 'a': // 8 strings to match.
		if (BuiltinName[24] != 'c')
		break;
		switch (BuiltinName[25]) {
		default: break;
		case 'h': // 2 strings to match.
		if (BuiltinName.substr(26, 4) != "s.rs")
		break;
		switch (BuiltinName[30]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mmachs_rs0; // "__built
		in_HEXAGON.M2.mmachs.rs0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mmachs_rs1; // "__built
		in_HEXAGON.M2.mmachs.rs1"
		}
		break;
		case 'l': // 2 strings to match.
		if (BuiltinName.substr(26, 4) != "s.rs")
		break;
		switch (BuiltinName[30]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mmacls_rs0; // "__built
		in_HEXAGON.M2.mmacls.rs0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mmacls_rs1; // "__built
		in_HEXAGON.M2.mmacls.rs1"
		}
		break;
		case 'u': // 4 strings to match.
		switch (BuiltinName[26]) {
		default: break;
		case 'h': // 2 strings to match.
		if (BuiltinName.substr(27, 3) != "s.s")
		break;
		switch (BuiltinName[30]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mmacuhs_s0; // "__built
		in_HEXAGON.M2.mmacuhs.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mmacuhs_s1; // "__built
		in_HEXAGON.M2.mmacuhs.s1"
		}
		break;
		case 'l': // 2 strings to match.
		if (BuiltinName.substr(27, 3) != "s.s")
		break;
		switch (BuiltinName[30]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mmaculs_s0; // "__built
		in_HEXAGON.M2.mmaculs.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mmaculs_s1; // "__built
		in_HEXAGON.M2.mmaculs.s1"
		}
		break;
		}
		break;
		}
		break;
		case 'p': // 4 strings to match.
		if (BuiltinName.substr(24, 2) != "yu")
		break;
		switch (BuiltinName[26]) {
		default: break;
		case 'h': // 2 strings to match.
		if (BuiltinName.substr(27, 3) != ".rs")
		break;
		switch (BuiltinName[30]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mmpyuh_rs0; // "__built
		in_HEXAGON.M2.mmpyuh.rs0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mmpyuh_rs1; // "__built
		in_HEXAGON.M2.mmpyuh.rs1"
		}
		break;
		case 'l': // 2 strings to match.
		if (BuiltinName.substr(27, 3) != ".rs")
		break;
		switch (BuiltinName[30]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mmpyul_rs0; // "__built
		in_HEXAGON.M2.mmpyul.rs0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mmpyul_rs1; // "__built
		in_HEXAGON.M2.mmpyul.rs1"
		}
		break;
		}
		break;
		}
		break;
		case 'p': // 16 strings to match.
		if (BuiltinName[23] != 'y')
		break;
		switch (BuiltinName[24]) {
		default: break;
		case 'd': // 8 strings to match.
		if (BuiltinName[25] != '.')
		break;
		switch (BuiltinName[26]) {
		default: break;
		case 'h': // 4 strings to match.
		switch (BuiltinName[27]) {
		default: break;
		case 'h': // 2 strings to match.
		if (BuiltinName.substr(28, 2) != ".s")
		break;
		switch (BuiltinName[30]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyd_hh_s0; // "__built
		in_HEXAGON.M2.mpyd.hh.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyd_hh_s1; // "__built
		in_HEXAGON.M2.mpyd.hh.s1"
		}
		break;
		case 'l': // 2 strings to match.
		if (BuiltinName.substr(28, 2) != ".s")
		break;
		switch (BuiltinName[30]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyd_hl_s0; // "__built
		in_HEXAGON.M2.mpyd.hl.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyd_hl_s1; // "__built
		in_HEXAGON.M2.mpyd.hl.s1"
		}
		break;
		}
		break;
		case 'l': // 4 strings to match.
		switch (BuiltinName[27]) {
		default: break;
		case 'h': // 2 strings to match.
		if (BuiltinName.substr(28, 2) != ".s")
		break;
		switch (BuiltinName[30]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyd_lh_s0; // "__built
		in_HEXAGON.M2.mpyd.lh.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyd_lh_s1; // "__built
		in_HEXAGON.M2.mpyd.lh.s1"
		}
		break;
		case 'l': // 2 strings to match.
		if (BuiltinName.substr(28, 2) != ".s")
		break;
		switch (BuiltinName[30]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyd_ll_s0; // "__built
		in_HEXAGON.M2.mpyd.ll.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyd_ll_s1; // "__built
		in_HEXAGON.M2.mpyd.ll.s1"
		}
		break;
		}
		break;
		}
		break;
		case 'u': // 8 strings to match.
		if (BuiltinName[25] != '.')
		break;
		switch (BuiltinName[26]) {
		default: break;
		case 'h': // 4 strings to match.
		switch (BuiltinName[27]) {
		default: break;
		case 'h': // 2 strings to match.
		if (BuiltinName.substr(28, 2) != ".s")
		break;
		switch (BuiltinName[30]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyu_hh_s0; // "__built
		in_HEXAGON.M2.mpyu.hh.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyu_hh_s1; // "__built
		in_HEXAGON.M2.mpyu.hh.s1"
		}
		break;
		case 'l': // 2 strings to match.
		if (BuiltinName.substr(28, 2) != ".s")
		break;
		switch (BuiltinName[30]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyu_hl_s0; // "__built
		in_HEXAGON.M2.mpyu.hl.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyu_hl_s1; // "__built
		in_HEXAGON.M2.mpyu.hl.s1"
		}
		break;
		}
		break;
		case 'l': // 4 strings to match.
		switch (BuiltinName[27]) {
		default: break;
		case 'h': // 2 strings to match.
		if (BuiltinName.substr(28, 2) != ".s")
		break;
		switch (BuiltinName[30]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyu_lh_s0; // "__built
		in_HEXAGON.M2.mpyu.lh.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyu_lh_s1; // "__built
		in_HEXAGON.M2.mpyu.lh.s1"
		}
		break;
		case 'l': // 2 strings to match.
		if (BuiltinName.substr(28, 2) != ".s")
		break;
		switch (BuiltinName[30]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyu_ll_s0; // "__built
		in_HEXAGON.M2.mpyu.ll.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyu_ll_s1; // "__built
		in_HEXAGON.M2.mpyu.ll.s1"
		}
		break;
		}
		break;
		}
		break;
		}
		break;
		}
		break;
		case 'v': // 11 strings to match.
		switch (BuiltinName[22]) {
		default: break;
		case 'd': // 2 strings to match.
		if (BuiltinName.substr(23, 7) != "mpyrs.s")
		break;
		switch (BuiltinName[30]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_vdmpyrs_s0; // "__builtin_HEXAG
		ON.M2.vdmpyrs.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_vdmpyrs_s1; // "__builtin_HEXAG
		ON.M2.vdmpyrs.s1"
		}
		break;
		case 'm': // 4 strings to match.
		switch (BuiltinName[23]) {
		default: break;
		case 'a': // 2 strings to match.
		if (BuiltinName.substr(24, 6) != "c2es.s")
		break;
		switch (BuiltinName[30]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_vmac2es_s0; // "__builtin_HEXAG
		ON.M2.vmac2es.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_vmac2es_s1; // "__builtin_HEXAG
		ON.M2.vmac2es.s1"
		}
		break;
		case 'p': // 2 strings to match.
		if (BuiltinName.substr(24, 6) != "y2es.s")
		break;
		switch (BuiltinName[30]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_vmpy2es_s0; // "__builtin_HEXAG
		ON.M2.vmpy2es.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_vmpy2es_s1; // "__builtin_HEXAG
		ON.M2.vmpy2es.s1"
		}
		break;
		}
		break;
		case 'r': // 5 strings to match.
		if (BuiltinName.substr(23, 2) != "cm")
		break;
		switch (BuiltinName[25]) {
		default: break;
		case 'a': // 2 strings to match.
		if (BuiltinName[26] != 'c')
		break;
		switch (BuiltinName[27]) {
		default: break;
		case 'i': // 1 string to match.
		if (BuiltinName.substr(28, 3) != ".s0")
		break;
		return Intrinsic::hexagon_M2_vrcmaci_s0; // "__builtin_HEXAG
		ON.M2.vrcmaci.s0"
		case 'r': // 1 string to match.
		if (BuiltinName.substr(28, 3) != ".s0")
		break;
		return Intrinsic::hexagon_M2_vrcmacr_s0; // "__builtin_HEXAG
		ON.M2.vrcmacr.s0"
		}
		break;
		case 'p': // 3 strings to match.
		if (BuiltinName[26] != 'y')
		break;
		switch (BuiltinName[27]) {
		default: break;
		case 'i': // 1 string to match.
		if (BuiltinName.substr(28, 3) != ".s0")
		break;
		return Intrinsic::hexagon_M2_vrcmpyi_s0; // "__builtin_HEXAG
		ON.M2.vrcmpyi.s0"
		case 'r': // 1 string to match.
		if (BuiltinName.substr(28, 3) != ".s0")
		break;
		return Intrinsic::hexagon_M2_vrcmpyr_s0; // "__builtin_HEXAG
		ON.M2.vrcmpyr.s0"
		case 's': // 1 string to match.
		if (BuiltinName.substr(28, 3) != ".s1")
		break;
		return Intrinsic::hexagon_M2_vrcmpys_s1; // "__builtin_HEXAG
		ON.M2.vrcmpys.s1"
		}
		break;
		}
		break;
		}
		break;
		}
		break;
		case 'S': // 17 strings to match.
		if (BuiltinName.substr(19, 2) != "2.")
		break;
		switch (BuiltinName[21]) {
		default: break;
		case 'a': // 8 strings to match.
		if (BuiltinName[22] != 's')
		break;
		switch (BuiltinName[23]) {
		default: break;
		case 'l': // 4 strings to match.
		if (BuiltinName[24] != '.')
		break;
		switch (BuiltinName[25]) {
		default: break;
		case 'i': // 2 strings to match.
		if (BuiltinName[26] != '.')
		break;
		switch (BuiltinName[27]) {
		default: break;
		case 'p': // 1 string to match.
		if (BuiltinName.substr(28, 3) != ".or")
		break;
		return Intrinsic::hexagon_S2_asl_i_p_or; // "__builtin_HEXAG
		ON.S2.asl.i.p.or"
		case 'r': // 1 string to match.
		if (BuiltinName.substr(28, 3) != ".or")
		break;
		return Intrinsic::hexagon_S2_asl_i_r_or; // "__builtin_HEXAG
		ON.S2.asl.i.r.or"
		}
		break;
		case 'r': // 2 strings to match.
		if (BuiltinName[26] != '.')
		break;
		switch (BuiltinName[27]) {
		default: break;
		case 'p': // 1 string to match.
		if (BuiltinName.substr(28, 3) != ".or")
		break;
		return Intrinsic::hexagon_S2_asl_r_p_or; // "__builtin_HEXAG
		ON.S2.asl.r.p.or"
		case 'r': // 1 string to match.
		if (BuiltinName.substr(28, 3) != ".or")
		break;
		return Intrinsic::hexagon_S2_asl_r_r_or; // "__builtin_HEXAG
		ON.S2.asl.r.r.or"
		}
		break;
		}
		break;
		case 'r': // 4 strings to match.
		if (BuiltinName[24] != '.')
		break;
		switch (BuiltinName[25]) {
		default: break;
		case 'i': // 2 strings to match.
		if (BuiltinName[26] != '.')
		break;
		switch (BuiltinName[27]) {
		default: break;
		case 'p': // 1 string to match.
		if (BuiltinName.substr(28, 3) != ".or")
		break;
		return Intrinsic::hexagon_S2_asr_i_p_or; // "__builtin_HEXAG
		ON.S2.asr.i.p.or"
		case 'r': // 1 string to match.
		if (BuiltinName.substr(28, 3) != ".or")
		break;
		return Intrinsic::hexagon_S2_asr_i_r_or; // "__builtin_HEXAG
		ON.S2.asr.i.r.or"
		}
		break;
		case 'r': // 2 strings to match.
		if (BuiltinName[26] != '.')
		break;
		switch (BuiltinName[27]) {
		default: break;
		case 'p': // 1 string to match.
		if (BuiltinName.substr(28, 3) != ".or")
		break;
		return Intrinsic::hexagon_S2_asr_r_p_or; // "__builtin_HEXAG
		ON.S2.asr.r.p.or"
		case 'r': // 1 string to match.
		if (BuiltinName.substr(28, 3) != ".or")
		break;
		return Intrinsic::hexagon_S2_asr_r_r_or; // "__builtin_HEXAG
		ON.S2.asr.r.r.or"
		}
		break;
		}
		break;
		}
		break;
		case 'i': // 2 strings to match.
		if (BuiltinName[22] != 'n')
		break;
		switch (BuiltinName[23]) {
		default: break;
		case 's': // 1 string to match.
		if (BuiltinName.substr(24, 7) != "ertp.rp")
		break;
		return Intrinsic::hexagon_S2_insertp_rp; // "__builtin_HEXAG
		ON.S2.insertp.rp"
		case 't': // 1 string to match.
		if (BuiltinName.substr(24, 7) != "erleave")
		break;
		return Intrinsic::hexagon_S2_interleave; // "__builtin_HEXAG
		ON.S2.interleave"
		}
		break;
		case 'l': // 6 strings to match.
		if (BuiltinName[22] != 's')
		break;
		switch (BuiltinName[23]) {
		default: break;
		case 'l': // 2 strings to match.
		if (BuiltinName.substr(24, 3) != ".r.")
		break;
		switch (BuiltinName[27]) {
		default: break;
		case 'p': // 1 string to match.
		if (BuiltinName.substr(28, 3) != ".or")
		break;
		return Intrinsic::hexagon_S2_lsl_r_p_or; // "__builtin_HEXAG
		ON.S2.lsl.r.p.or"
		case 'r': // 1 string to match.
		if (BuiltinName.substr(28, 3) != ".or")
		break;
		return Intrinsic::hexagon_S2_lsl_r_r_or; // "__builtin_HEXAG
		ON.S2.lsl.r.r.or"
		}
		break;
		case 'r': // 4 strings to match.
		if (BuiltinName[24] != '.')
		break;
		switch (BuiltinName[25]) {
		default: break;
		case 'i': // 2 strings to match.
		if (BuiltinName[26] != '.')
		break;
		switch (BuiltinName[27]) {
		default: break;
		case 'p': // 1 string to match.
		if (BuiltinName.substr(28, 3) != ".or")
		break;
		return Intrinsic::hexagon_S2_lsr_i_p_or; // "__builtin_HEXAG
		ON.S2.lsr.i.p.or"
		case 'r': // 1 string to match.
		if (BuiltinName.substr(28, 3) != ".or")
		break;
		return Intrinsic::hexagon_S2_lsr_i_r_or; // "__builtin_HEXAG
		ON.S2.lsr.i.r.or"
		}
		break;
		case 'r': // 2 strings to match.
		if (BuiltinName[26] != '.')
		break;
		switch (BuiltinName[27]) {
		default: break;
		case 'p': // 1 string to match.
		if (BuiltinName.substr(28, 3) != ".or")
		break;
		return Intrinsic::hexagon_S2_lsr_r_p_or; // "__builtin_HEXAG
		ON.S2.lsr.r.p.or"
		case 'r': // 1 string to match.
		if (BuiltinName.substr(28, 3) != ".or")
		break;
		return Intrinsic::hexagon_S2_lsr_r_r_or; // "__builtin_HEXAG
		ON.S2.lsr.r.r.or"
		}
		break;
		}
		break;
		}
		break;
		case 'v': // 1 string to match.
		if (BuiltinName.substr(22, 9) != "rndpackwh")
		break;
		return Intrinsic::hexagon_S2_vrndpackwh; // "__builtin_HEXAG
		ON.S2.vrndpackwh"
		}
		break;
		}
	break;	break;

	case Intrinsic::x86_sse_pshuf_w: // llvm.x86.sse.pshuf.w	case 32: // 84 strings to match.
	ResultTy = Type::getX86_MMXTy(Context);	if (BuiltinName.substr(0, 18) != "__builtin_HEXAGON.")
	ArgTys.push_back(Type::getX86_MMXTy(Context));	break;
	ArgTys.push_back(IntegerType::get(Context, 8));	switch (BuiltinName[18]) {
		default: break;
		case 'A': // 16 strings to match.
		if (BuiltinName.substr(19, 2) != "2.")
		break;
		switch (BuiltinName[21]) {
		default: break;
		case 'a': // 8 strings to match.
		if (BuiltinName.substr(22, 4) != "ddh.")
		break;
		switch (BuiltinName[26]) {
		default: break;
		case 'h': // 4 strings to match.
		if (BuiltinName.substr(27, 3) != "16.")
		break;
		switch (BuiltinName[30]) {
		default: break;
		case 'h': // 2 strings to match.
		switch (BuiltinName[31]) {
		default: break;
		case 'h': // 1 string to match.
		return Intrinsic::hexagon_A2_addh_h16_hh; // "__built
		in_HEXAGON.A2.addh.h16.hh"
		case 'l': // 1 string to match.
		return Intrinsic::hexagon_A2_addh_h16_hl; // "__built
		in_HEXAGON.A2.addh.h16.hl"
		}
		break;
		case 'l': // 2 strings to match.
		switch (BuiltinName[31]) {
		default: break;
		case 'h': // 1 string to match.
		return Intrinsic::hexagon_A2_addh_h16_lh; // "__built
		in_HEXAGON.A2.addh.h16.lh"
		case 'l': // 1 string to match.
		return Intrinsic::hexagon_A2_addh_h16_ll; // "__built
		in_HEXAGON.A2.addh.h16.ll"
		}
		break;
		}
		break;
		case 'l': // 4 strings to match.
		if (BuiltinName.substr(27, 3) != "16.")
		break;
		switch (BuiltinName[30]) {
		default: break;
		case 'h': // 2 strings to match.
		switch (BuiltinName[31]) {
		default: break;
		case 'h': // 1 string to match.
		return Intrinsic::hexagon_A2_addh_l16_hh; // "__built
		in_HEXAGON.A2.addh.l16.hh"
		case 'l': // 1 string to match.
		return Intrinsic::hexagon_A2_addh_l16_hl; // "__built
		in_HEXAGON.A2.addh.l16.hl"
		}
		break;
		case 'l': // 2 strings to match.
		switch (BuiltinName[31]) {
		default: break;
		case 'h': // 1 string to match.
		return Intrinsic::hexagon_A2_addh_l16_lh; // "__built
		in_HEXAGON.A2.addh.l16.lh"
		case 'l': // 1 string to match.
		return Intrinsic::hexagon_A2_addh_l16_ll; // "__built
		in_HEXAGON.A2.addh.l16.ll"
		}
		break;
		}
		break;
		}
		break;
		case 's': // 6 strings to match.
		if (BuiltinName.substr(22, 4) != "ubh.")
		break;
		switch (BuiltinName[26]) {
		default: break;
		case 'h': // 4 strings to match.
		if (BuiltinName.substr(27, 3) != "16.")
		break;
		switch (BuiltinName[30]) {
		default: break;
		case 'h': // 2 strings to match.
		switch (BuiltinName[31]) {
		default: break;
		case 'h': // 1 string to match.
		return Intrinsic::hexagon_A2_subh_h16_hh; // "__built
		in_HEXAGON.A2.subh.h16.hh"
		case 'l': // 1 string to match.
		return Intrinsic::hexagon_A2_subh_h16_hl; // "__built
		in_HEXAGON.A2.subh.h16.hl"
		}
		break;
		case 'l': // 2 strings to match.
		switch (BuiltinName[31]) {
		default: break;
		case 'h': // 1 string to match.
		return Intrinsic::hexagon_A2_subh_h16_lh; // "__built
		in_HEXAGON.A2.subh.h16.lh"
		case 'l': // 1 string to match.
		return Intrinsic::hexagon_A2_subh_h16_ll; // "__built
		in_HEXAGON.A2.subh.h16.ll"
		}
		break;
		}
		break;
		case 'l': // 2 strings to match.
		if (BuiltinName.substr(27, 3) != "16.")
		break;
		switch (BuiltinName[30]) {
		default: break;
		case 'h': // 1 string to match.
		if (BuiltinName[31] != 'l')
		break;
		return Intrinsic::hexagon_A2_subh_l16_hl; // "__builtin_HEXAG
		ON.A2.subh.l16.hl"
		case 'l': // 1 string to match.
		if (BuiltinName[31] != 'l')
		break;
		return Intrinsic::hexagon_A2_subh_l16_ll; // "__builtin_HEXAG
		ON.A2.subh.l16.ll"
		}
		break;
		}
		break;
		case 'v': // 2 strings to match.
		if (BuiltinName[22] != 'r')
		break;
		switch (BuiltinName[23]) {
		default: break;
		case 'a': // 1 string to match.
		if (BuiltinName.substr(24, 8) != "ddub.acc")
		break;
		return Intrinsic::hexagon_A2_vraddub_acc; // "__builtin_HEXAG
		ON.A2.vraddub.acc"
		case 's': // 1 string to match.
		if (BuiltinName.substr(24, 8) != "adub.acc")
		break;
		return Intrinsic::hexagon_A2_vrsadub_acc; // "__builtin_HEXAG
		ON.A2.vrsadub.acc"
		}
		break;
		}
		break;
		case 'C': // 1 string to match.
		if (BuiltinName.substr(19, 13) != "4.fastcorner9")
		break;
		return Intrinsic::hexagon_C4_fastcorner9; // "__builtin_HEXAG
		ON.C4.fastcorner9"
		case 'M': // 16 strings to match.
		if (BuiltinName.substr(19, 2) != "2.")
		break;
		switch (BuiltinName[21]) {
		default: break;
		case 'm': // 12 strings to match.
		switch (BuiltinName[22]) {
		default: break;
		case 'm': // 4 strings to match.
		if (BuiltinName.substr(23, 3) != "acu")
		break;
		switch (BuiltinName[26]) {
		default: break;
		case 'h': // 2 strings to match.
		if (BuiltinName.substr(27, 4) != "s.rs")
		break;
		switch (BuiltinName[31]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mmacuhs_rs0; // "__built
		in_HEXAGON.M2.mmacuhs.rs0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mmacuhs_rs1; // "__built
		in_HEXAGON.M2.mmacuhs.rs1"
		}
		break;
		case 'l': // 2 strings to match.
		if (BuiltinName.substr(27, 4) != "s.rs")
		break;
		switch (BuiltinName[31]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mmaculs_rs0; // "__built
		in_HEXAGON.M2.mmaculs.rs0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mmaculs_rs1; // "__built
		in_HEXAGON.M2.mmaculs.rs1"
		}
		break;
		}
		break;
		case 'p': // 8 strings to match.
		if (BuiltinName.substr(23, 4) != "yud.")
		break;
		switch (BuiltinName[27]) {
		default: break;
		case 'h': // 4 strings to match.
		switch (BuiltinName[28]) {
		default: break;
		case 'h': // 2 strings to match.
		if (BuiltinName.substr(29, 2) != ".s")
		break;
		switch (BuiltinName[31]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyud_hh_s0; // "__built
		in_HEXAGON.M2.mpyud.hh.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyud_hh_s1; // "__built
		in_HEXAGON.M2.mpyud.hh.s1"
		}
		break;
		case 'l': // 2 strings to match.
		if (BuiltinName.substr(29, 2) != ".s")
		break;
		switch (BuiltinName[31]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyud_hl_s0; // "__built
		in_HEXAGON.M2.mpyud.hl.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyud_hl_s1; // "__built
		in_HEXAGON.M2.mpyud.hl.s1"
		}
		break;
		}
		break;
		case 'l': // 4 strings to match.
		switch (BuiltinName[28]) {
		default: break;
		case 'h': // 2 strings to match.
		if (BuiltinName.substr(29, 2) != ".s")
		break;
		switch (BuiltinName[31]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyud_lh_s0; // "__built
		in_HEXAGON.M2.mpyud.lh.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyud_lh_s1; // "__built
		in_HEXAGON.M2.mpyud.lh.s1"
		}
		break;
		case 'l': // 2 strings to match.
		if (BuiltinName.substr(29, 2) != ".s")
		break;
		switch (BuiltinName[31]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyud_ll_s0; // "__built
		in_HEXAGON.M2.mpyud.ll.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyud_ll_s1; // "__built
		in_HEXAGON.M2.mpyud.ll.s1"
		}
		break;
		}
		break;
		}
		break;
		}
		break;
		case 'v': // 4 strings to match.
		if (BuiltinName.substr(22, 3) != "rcm")
		break;
		switch (BuiltinName[25]) {
		default: break;
		case 'a': // 2 strings to match.
		if (BuiltinName[26] != 'c')
		break;
		switch (BuiltinName[27]) {
		default: break;
		case 'i': // 1 string to match.
		if (BuiltinName.substr(28, 4) != ".s0c")
		break;
		return Intrinsic::hexagon_M2_vrcmaci_s0c; // "__builtin_HEXAG
		ON.M2.vrcmaci.s0c"
		case 'r': // 1 string to match.
		if (BuiltinName.substr(28, 4) != ".s0c")
		break;
		return Intrinsic::hexagon_M2_vrcmacr_s0c; // "__builtin_HEXAG
		ON.M2.vrcmacr.s0c"
		}
		break;
		case 'p': // 2 strings to match.
		if (BuiltinName[26] != 'y')
		break;
		switch (BuiltinName[27]) {
		default: break;
		case 'i': // 1 string to match.
		if (BuiltinName.substr(28, 4) != ".s0c")
		break;
		return Intrinsic::hexagon_M2_vrcmpyi_s0c; // "__builtin_HEXAG
		ON.M2.vrcmpyi.s0c"
		case 'r': // 1 string to match.
		if (BuiltinName.substr(28, 4) != ".s0c")
		break;
		return Intrinsic::hexagon_M2_vrcmpyr_s0c; // "__builtin_HEXAG
		ON.M2.vrcmpyr.s0c"
		}
		break;
		}
		break;
		}
		break;
		case 'S': // 51 strings to match.
		if (BuiltinName.substr(19, 2) != "2.")
		break;
		switch (BuiltinName[21]) {
		default: break;
		case 'a': // 29 strings to match.
		switch (BuiltinName[22]) {
		default: break;
		case 'd': // 1 string to match.
		if (BuiltinName.substr(23, 9) != "dasl.rrri")
		break;
		return Intrinsic::hexagon_S2_addasl_rrri; // "__builtin_HEXAG
		ON.S2.addasl.rrri"
		case 's': // 28 strings to match.
		switch (BuiltinName[23]) {
		default: break;
		case 'l': // 14 strings to match.
		if (BuiltinName[24] != '.')
		break;
		switch (BuiltinName[25]) {
		default: break;
		case 'i': // 7 strings to match.
		if (BuiltinName[26] != '.')
		break;
		switch (BuiltinName[27]) {
		default: break;
		case 'p': // 3 strings to match.
		if (BuiltinName[28] != '.')
		break;
		switch (BuiltinName[29]) {
		default: break;
		case 'a': // 2 strings to match.
		switch (BuiltinName[30]) {
		default: break;
		case 'c': // 1 string to match.
		if (BuiltinName[31] != 'c')
		break;
		return Intrinsic::hexagon_S2_asl_i_p_acc; // "__built
		in_HEXAGON.S2.asl.i.p.acc"
		case 'n': // 1 string to match.
		if (BuiltinName[31] != 'd')
		break;
		return Intrinsic::hexagon_S2_asl_i_p_and; // "__built
		in_HEXAGON.S2.asl.i.p.and"
		}
		break;
		case 'n': // 1 string to match.
		if (BuiltinName.substr(30, 2) != "ac")
		break;
		return Intrinsic::hexagon_S2_asl_i_p_nac; // "__built
		in_HEXAGON.S2.asl.i.p.nac"
		}
		break;
		case 'r': // 4 strings to match.
		if (BuiltinName[28] != '.')
		break;
		switch (BuiltinName[29]) {
		default: break;
		case 'a': // 2 strings to match.
		switch (BuiltinName[30]) {
		default: break;
		case 'c': // 1 string to match.
		if (BuiltinName[31] != 'c')
		break;
		return Intrinsic::hexagon_S2_asl_i_r_acc; // "__built
		in_HEXAGON.S2.asl.i.r.acc"
		case 'n': // 1 string to match.
		if (BuiltinName[31] != 'd')
		break;
		return Intrinsic::hexagon_S2_asl_i_r_and; // "__built
		in_HEXAGON.S2.asl.i.r.and"
		}
		break;
		case 'n': // 1 string to match.
		if (BuiltinName.substr(30, 2) != "ac")
		break;
		return Intrinsic::hexagon_S2_asl_i_r_nac; // "__built
		in_HEXAGON.S2.asl.i.r.nac"
		case 's': // 1 string to match.
		if (BuiltinName.substr(30, 2) != "at")
		break;
		return Intrinsic::hexagon_S2_asl_i_r_sat; // "__built
		in_HEXAGON.S2.asl.i.r.sat"
		}
		break;
		}
		break;
		case 'r': // 7 strings to match.
		if (BuiltinName[26] != '.')
		break;
		switch (BuiltinName[27]) {
		default: break;
		case 'p': // 3 strings to match.
		if (BuiltinName[28] != '.')
		break;
		switch (BuiltinName[29]) {
		default: break;
		case 'a': // 2 strings to match.
		switch (BuiltinName[30]) {
		default: break;
		case 'c': // 1 string to match.
		if (BuiltinName[31] != 'c')
		break;
		return Intrinsic::hexagon_S2_asl_r_p_acc; // "__built
		in_HEXAGON.S2.asl.r.p.acc"
		case 'n': // 1 string to match.
		if (BuiltinName[31] != 'd')
		break;
		return Intrinsic::hexagon_S2_asl_r_p_and; // "__built
		in_HEXAGON.S2.asl.r.p.and"
		}
		break;
		case 'n': // 1 string to match.
		if (BuiltinName.substr(30, 2) != "ac")
		break;
		return Intrinsic::hexagon_S2_asl_r_p_nac; // "__built
		in_HEXAGON.S2.asl.r.p.nac"
		}
		break;
		case 'r': // 4 strings to match.
		if (BuiltinName[28] != '.')
		break;
		switch (BuiltinName[29]) {
		default: break;
		case 'a': // 2 strings to match.
		switch (BuiltinName[30]) {
		default: break;
		case 'c': // 1 string to match.
		if (BuiltinName[31] != 'c')
		break;
		return Intrinsic::hexagon_S2_asl_r_r_acc; // "__built
		in_HEXAGON.S2.asl.r.r.acc"
		case 'n': // 1 string to match.
		if (BuiltinName[31] != 'd')
		break;
		return Intrinsic::hexagon_S2_asl_r_r_and; // "__built
		in_HEXAGON.S2.asl.r.r.and"
		}
		break;
		case 'n': // 1 string to match.
		if (BuiltinName.substr(30, 2) != "ac")
		break;
		return Intrinsic::hexagon_S2_asl_r_r_nac; // "__built
		in_HEXAGON.S2.asl.r.r.nac"
		case 's': // 1 string to match.
		if (BuiltinName.substr(30, 2) != "at")
		break;
		return Intrinsic::hexagon_S2_asl_r_r_sat; // "__built
		in_HEXAGON.S2.asl.r.r.sat"
		}
		break;
		}
		break;
		}
		break;
		case 'r': // 14 strings to match.
		if (BuiltinName[24] != '.')
		break;
		switch (BuiltinName[25]) {
		default: break;
		case 'i': // 7 strings to match.
		if (BuiltinName[26] != '.')
		break;
		switch (BuiltinName[27]) {
		default: break;
		case 'p': // 3 strings to match.
		if (BuiltinName[28] != '.')
		break;
		switch (BuiltinName[29]) {
		default: break;
		case 'a': // 2 strings to match.
		switch (BuiltinName[30]) {
		default: break;
		case 'c': // 1 string to match.
		if (BuiltinName[31] != 'c')
		break;
		return Intrinsic::hexagon_S2_asr_i_p_acc; // "__built
		in_HEXAGON.S2.asr.i.p.acc"
		case 'n': // 1 string to match.
		if (BuiltinName[31] != 'd')
		break;
		return Intrinsic::hexagon_S2_asr_i_p_and; // "__built
		in_HEXAGON.S2.asr.i.p.and"
		}
		break;
		case 'n': // 1 string to match.
		if (BuiltinName.substr(30, 2) != "ac")
		break;
		return Intrinsic::hexagon_S2_asr_i_p_nac; // "__built
		in_HEXAGON.S2.asr.i.p.nac"
		}
		break;
		case 'r': // 4 strings to match.
		if (BuiltinName[28] != '.')
		break;
		switch (BuiltinName[29]) {
		default: break;
		case 'a': // 2 strings to match.
		switch (BuiltinName[30]) {
		default: break;
		case 'c': // 1 string to match.
		if (BuiltinName[31] != 'c')
		break;
		return Intrinsic::hexagon_S2_asr_i_r_acc; // "__built
		in_HEXAGON.S2.asr.i.r.acc"
		case 'n': // 1 string to match.
		if (BuiltinName[31] != 'd')
		break;
		return Intrinsic::hexagon_S2_asr_i_r_and; // "__built
		in_HEXAGON.S2.asr.i.r.and"
		}
		break;
		case 'n': // 1 string to match.
		if (BuiltinName.substr(30, 2) != "ac")
		break;
		return Intrinsic::hexagon_S2_asr_i_r_nac; // "__built
		in_HEXAGON.S2.asr.i.r.nac"
		case 'r': // 1 string to match.
		if (BuiltinName.substr(30, 2) != "nd")
		break;
		return Intrinsic::hexagon_S2_asr_i_r_rnd; // "__built
		in_HEXAGON.S2.asr.i.r.rnd"
		}
		break;
		}
		break;
		case 'r': // 7 strings to match.
		if (BuiltinName[26] != '.')
		break;
		switch (BuiltinName[27]) {
		default: break;
		case 'p': // 3 strings to match.
		if (BuiltinName[28] != '.')
		break;
		switch (BuiltinName[29]) {
		default: break;
		case 'a': // 2 strings to match.
		switch (BuiltinName[30]) {
		default: break;
		case 'c': // 1 string to match.
		if (BuiltinName[31] != 'c')
		break;
		return Intrinsic::hexagon_S2_asr_r_p_acc; // "__built
		in_HEXAGON.S2.asr.r.p.acc"
		case 'n': // 1 string to match.
		if (BuiltinName[31] != 'd')
		break;
		return Intrinsic::hexagon_S2_asr_r_p_and; // "__built
		in_HEXAGON.S2.asr.r.p.and"
		}
		break;
		case 'n': // 1 string to match.
		if (BuiltinName.substr(30, 2) != "ac")
		break;
		return Intrinsic::hexagon_S2_asr_r_p_nac; // "__built
		in_HEXAGON.S2.asr.r.p.nac"
		}
		break;
		case 'r': // 4 strings to match.
		if (BuiltinName[28] != '.')
		break;
		switch (BuiltinName[29]) {
		default: break;
		case 'a': // 2 strings to match.
		switch (BuiltinName[30]) {
		default: break;
		case 'c': // 1 string to match.
		if (BuiltinName[31] != 'c')
		break;
		return Intrinsic::hexagon_S2_asr_r_r_acc; // "__built
		in_HEXAGON.S2.asr.r.r.acc"
		case 'n': // 1 string to match.
		if (BuiltinName[31] != 'd')
		break;
		return Intrinsic::hexagon_S2_asr_r_r_and; // "__built
		in_HEXAGON.S2.asr.r.r.and"
		}
		break;
		case 'n': // 1 string to match.
		if (BuiltinName.substr(30, 2) != "ac")
		break;
		return Intrinsic::hexagon_S2_asr_r_r_nac; // "__built
		in_HEXAGON.S2.asr.r.r.nac"
		case 's': // 1 string to match.
		if (BuiltinName.substr(30, 2) != "at")
		break;
		return Intrinsic::hexagon_S2_asr_r_r_sat; // "__built
		in_HEXAGON.S2.asr.r.r.sat"
		}
		break;
		}
		break;
		}
		break;
		}
		break;
		}
		break;
		case 'e': // 1 string to match.
		if (BuiltinName.substr(22, 10) != "xtractu.rp")
		break;
		return Intrinsic::hexagon_S2_extractu_rp; // "__builtin_HEXAG
		ON.S2.extractu.rp"
		case 'l': // 18 strings to match.
		if (BuiltinName[22] != 's')
		break;
		switch (BuiltinName[23]) {
		default: break;
		case 'l': // 6 strings to match.
		if (BuiltinName.substr(24, 3) != ".r.")
		break;
		switch (BuiltinName[27]) {
		default: break;
		case 'p': // 3 strings to match.
		if (BuiltinName[28] != '.')
		break;
		switch (BuiltinName[29]) {
		default: break;
		case 'a': // 2 strings to match.
		switch (BuiltinName[30]) {
		default: break;
		case 'c': // 1 string to match.
		if (BuiltinName[31] != 'c')
		break;
		return Intrinsic::hexagon_S2_lsl_r_p_acc; // "__built
		in_HEXAGON.S2.lsl.r.p.acc"
		case 'n': // 1 string to match.
		if (BuiltinName[31] != 'd')
		break;
		return Intrinsic::hexagon_S2_lsl_r_p_and; // "__built
		in_HEXAGON.S2.lsl.r.p.and"
		}
		break;
		case 'n': // 1 string to match.
		if (BuiltinName.substr(30, 2) != "ac")
		break;
		return Intrinsic::hexagon_S2_lsl_r_p_nac; // "__built
		in_HEXAGON.S2.lsl.r.p.nac"
		}
		break;
		case 'r': // 3 strings to match.
		if (BuiltinName[28] != '.')
		break;
		switch (BuiltinName[29]) {
		default: break;
		case 'a': // 2 strings to match.
		switch (BuiltinName[30]) {
		default: break;
		case 'c': // 1 string to match.
		if (BuiltinName[31] != 'c')
		break;
		return Intrinsic::hexagon_S2_lsl_r_r_acc; // "__built
		in_HEXAGON.S2.lsl.r.r.acc"
		case 'n': // 1 string to match.
		if (BuiltinName[31] != 'd')
		break;
		return Intrinsic::hexagon_S2_lsl_r_r_and; // "__built
		in_HEXAGON.S2.lsl.r.r.and"
		}
		break;
		case 'n': // 1 string to match.
		if (BuiltinName.substr(30, 2) != "ac")
		break;
		return Intrinsic::hexagon_S2_lsl_r_r_nac; // "__built
		in_HEXAGON.S2.lsl.r.r.nac"
		}
		break;
		}
		break;
		case 'r': // 12 strings to match.
		if (BuiltinName[24] != '.')
		break;
		switch (BuiltinName[25]) {
		default: break;
		case 'i': // 6 strings to match.
		if (BuiltinName[26] != '.')
		break;
		switch (BuiltinName[27]) {
		default: break;
		case 'p': // 3 strings to match.
		if (BuiltinName[28] != '.')
		break;
		switch (BuiltinName[29]) {
		default: break;
		case 'a': // 2 strings to match.
		switch (BuiltinName[30]) {
		default: break;
		case 'c': // 1 string to match.
		if (BuiltinName[31] != 'c')
		break;
		return Intrinsic::hexagon_S2_lsr_i_p_acc; // "__built
		in_HEXAGON.S2.lsr.i.p.acc"
		case 'n': // 1 string to match.
		if (BuiltinName[31] != 'd')
		break;
		return Intrinsic::hexagon_S2_lsr_i_p_and; // "__built
		in_HEXAGON.S2.lsr.i.p.and"
		}
		break;
		case 'n': // 1 string to match.
		if (BuiltinName.substr(30, 2) != "ac")
		break;
		return Intrinsic::hexagon_S2_lsr_i_p_nac; // "__built
		in_HEXAGON.S2.lsr.i.p.nac"
		}
		break;
		case 'r': // 3 strings to match.
		if (BuiltinName[28] != '.')
		break;
		switch (BuiltinName[29]) {
		default: break;
		case 'a': // 2 strings to match.
		switch (BuiltinName[30]) {
		default: break;
		case 'c': // 1 string to match.
		if (BuiltinName[31] != 'c')
		break;
		return Intrinsic::hexagon_S2_lsr_i_r_acc; // "__built
		in_HEXAGON.S2.lsr.i.r.acc"
		case 'n': // 1 string to match.
		if (BuiltinName[31] != 'd')
		break;
		return Intrinsic::hexagon_S2_lsr_i_r_and; // "__built
		in_HEXAGON.S2.lsr.i.r.and"
		}
		break;
		case 'n': // 1 string to match.
		if (BuiltinName.substr(30, 2) != "ac")
		break;
		return Intrinsic::hexagon_S2_lsr_i_r_nac; // "__built
		in_HEXAGON.S2.lsr.i.r.nac"
		}
		break;
		}
		break;
		case 'r': // 6 strings to match.
		if (BuiltinName[26] != '.')
		break;
		switch (BuiltinName[27]) {
		default: break;
		case 'p': // 3 strings to match.
		if (BuiltinName[28] != '.')
		break;
		switch (BuiltinName[29]) {
		default: break;
		case 'a': // 2 strings to match.
		switch (BuiltinName[30]) {
		default: break;
		case 'c': // 1 string to match.
		if (BuiltinName[31] != 'c')
		break;
		return Intrinsic::hexagon_S2_lsr_r_p_acc; // "__built
		in_HEXAGON.S2.lsr.r.p.acc"
		case 'n': // 1 string to match.
		if (BuiltinName[31] != 'd')
		break;
		return Intrinsic::hexagon_S2_lsr_r_p_and; // "__built
		in_HEXAGON.S2.lsr.r.p.and"
		}
		break;
		case 'n': // 1 string to match.
		if (BuiltinName.substr(30, 2) != "ac")
		break;
		return Intrinsic::hexagon_S2_lsr_r_p_nac; // "__built
		in_HEXAGON.S2.lsr.r.p.nac"
		}
		break;
		case 'r': // 3 strings to match.
		if (BuiltinName[28] != '.')
		break;
		switch (BuiltinName[29]) {
		default: break;
		case 'a': // 2 strings to match.
		switch (BuiltinName[30]) {
		default: break;
		case 'c': // 1 string to match.
		if (BuiltinName[31] != 'c')
		break;
		return Intrinsic::hexagon_S2_lsr_r_r_acc; // "__built
		in_HEXAGON.S2.lsr.r.r.acc"
		case 'n': // 1 string to match.
		if (BuiltinName[31] != 'd')
		break;
		return Intrinsic::hexagon_S2_lsr_r_r_and; // "__built
		in_HEXAGON.S2.lsr.r.r.and"
		}
		break;
		case 'n': // 1 string to match.
		if (BuiltinName.substr(30, 2) != "ac")
		break;
		return Intrinsic::hexagon_S2_lsr_r_r_nac; // "__built
		in_HEXAGON.S2.lsr.r.r.nac"
		}
		break;
		}
		break;
		}
		break;
		}
		break;
		case 't': // 2 strings to match.
		if (BuiltinName.substr(22, 9) != "ogglebit.")
		break;
		switch (BuiltinName[31]) {
		default: break;
		case 'i': // 1 string to match.
		return Intrinsic::hexagon_S2_togglebit_i; // "__builtin_HEXAG
		ON.S2.togglebit.i"
		case 'r': // 1 string to match.
		return Intrinsic::hexagon_S2_togglebit_r; // "__builtin_HEXAG
		ON.S2.togglebit.r"
		}
		break;
		case 'v': // 1 string to match.
		if (BuiltinName.substr(22, 10) != "rndpackwhs")
		break;
		return Intrinsic::hexagon_S2_vrndpackwhs; // "__builtin_HEXAG
		ON.S2.vrndpackwhs"
		}
		break;
		}
	break;	break;

	case Intrinsic::x86_3dnow_pavgusb: // llvm.x86.3dnow.pavgusb	case 33: // 9 strings to match.
	case Intrinsic::x86_3dnow_pfacc: // llvm.x86.3dnow.pfacc	if (BuiltinName.substr(0, 18) != "__builtin_HEXAGON.")
	case Intrinsic::x86_3dnow_pfadd: // llvm.x86.3dnow.pfadd	break;
	case Intrinsic::x86_3dnow_pfcmpeq: // llvm.x86.3dnow.pfcmpeq	switch (BuiltinName[18]) {
	case Intrinsic::x86_3dnow_pfcmpge: // llvm.x86.3dnow.pfcmpge	default: break;
	case Intrinsic::x86_3dnow_pfcmpgt: // llvm.x86.3dnow.pfcmpgt	case 'A': // 2 strings to match.
	case Intrinsic::x86_3dnow_pfmax: // llvm.x86.3dnow.pfmax	if (BuiltinName.substr(19, 9) != "4.round_r")
	case Intrinsic::x86_3dnow_pfmin: // llvm.x86.3dnow.pfmin	break;
	case Intrinsic::x86_3dnow_pfmul: // llvm.x86.3dnow.pfmul	switch (BuiltinName[28]) {
	case Intrinsic::x86_3dnow_pfrcpit1: // llvm.x86.3dnow.pfrcpit1	default: break;
	case Intrinsic::x86_3dnow_pfrcpit2: // llvm.x86.3dnow.pfrcpit2	case 'i': // 1 string to match.
	case Intrinsic::x86_3dnow_pfrsqit1: // llvm.x86.3dnow.pfrsqit1	if (BuiltinName.substr(29, 4) != "_sat")
	case Intrinsic::x86_3dnow_pfsub: // llvm.x86.3dnow.pfsub	break;
	case Intrinsic::x86_3dnow_pfsubr: // llvm.x86.3dnow.pfsubr	return Intrinsic::hexagon_A4_round_ri_sat; // "__builtin_HEXAG
	case Intrinsic::x86_3dnow_pmulhrw: // llvm.x86.3dnow.pmulhrw	ON.A4.round_ri_sat"
	case Intrinsic::x86_3dnowa_pfnacc: // llvm.x86.3dnowa.pfnacc	case 'r': // 1 string to match.
	case Intrinsic::x86_3dnowa_pfpnacc: // llvm.x86.3dnowa.pfpnacc	if (BuiltinName.substr(29, 4) != "_sat")
	case Intrinsic::x86_mmx_packssdw: // llvm.x86.mmx.packssdw	break;
	case Intrinsic::x86_mmx_packsswb: // llvm.x86.mmx.packsswb	return Intrinsic::hexagon_A4_round_rr_sat; // "__builtin_HEXAG
	case Intrinsic::x86_mmx_packuswb: // llvm.x86.mmx.packuswb	ON.A4.round_rr_sat"
	case Intrinsic::x86_mmx_padd_b: // llvm.x86.mmx.padd.b	}
	case Intrinsic::x86_mmx_padd_d: // llvm.x86.mmx.padd.d	break;
	case Intrinsic::x86_mmx_padd_q: // llvm.x86.mmx.padd.q	case 'M': // 1 string to match.
	case Intrinsic::x86_mmx_padd_w: // llvm.x86.mmx.padd.w	if (BuiltinName.substr(19, 14) != "2.vrcmpys.s1rp")
	case Intrinsic::x86_mmx_padds_b: // llvm.x86.mmx.padds.b	break;
	case Intrinsic::x86_mmx_padds_w: // llvm.x86.mmx.padds.w	return Intrinsic::hexagon_M2_vrcmpys_s1rp; // "__builtin_HEXAG
	case Intrinsic::x86_mmx_paddus_b: // llvm.x86.mmx.paddus.b	ON.M2.vrcmpys.s1rp"
	case Intrinsic::x86_mmx_paddus_w: // llvm.x86.mmx.paddus.w	case 'S': // 6 strings to match.
	case Intrinsic::x86_mmx_pand: // llvm.x86.mmx.pand	if (BuiltinName.substr(19, 2) != "2.")
	case Intrinsic::x86_mmx_pandn: // llvm.x86.mmx.pandn	break;
	case Intrinsic::x86_mmx_pavg_b: // llvm.x86.mmx.pavg.b	switch (BuiltinName[21]) {
	case Intrinsic::x86_mmx_pavg_w: // llvm.x86.mmx.pavg.w	default: break;
	case Intrinsic::x86_mmx_pcmpeq_b: // llvm.x86.mmx.pcmpeq.b	case 'a': // 2 strings to match.
	case Intrinsic::x86_mmx_pcmpeq_d: // llvm.x86.mmx.pcmpeq.d	if (BuiltinName.substr(22, 5) != "sl.i.")
	case Intrinsic::x86_mmx_pcmpeq_w: // llvm.x86.mmx.pcmpeq.w	break;
	case Intrinsic::x86_mmx_pcmpgt_b: // llvm.x86.mmx.pcmpgt.b	switch (BuiltinName[27]) {
	case Intrinsic::x86_mmx_pcmpgt_d: // llvm.x86.mmx.pcmpgt.d	default: break;
	case Intrinsic::x86_mmx_pcmpgt_w: // llvm.x86.mmx.pcmpgt.w	case 'p': // 1 string to match.
	case Intrinsic::x86_mmx_pmadd_wd: // llvm.x86.mmx.pmadd.wd	if (BuiltinName.substr(28, 5) != ".xacc")
	case Intrinsic::x86_mmx_pmaxs_w: // llvm.x86.mmx.pmaxs.w	break;
	case Intrinsic::x86_mmx_pmaxu_b: // llvm.x86.mmx.pmaxu.b	return Intrinsic::hexagon_S2_asl_i_p_xacc; // "__builtin_HEXAG
	case Intrinsic::x86_mmx_pmins_w: // llvm.x86.mmx.pmins.w	ON.S2.asl.i.p.xacc"
	case Intrinsic::x86_mmx_pminu_b: // llvm.x86.mmx.pminu.b	case 'r': // 1 string to match.
	case Intrinsic::x86_mmx_pmulh_w: // llvm.x86.mmx.pmulh.w	if (BuiltinName.substr(28, 5) != ".xacc")
	case Intrinsic::x86_mmx_pmulhu_w: // llvm.x86.mmx.pmulhu.w	break;
	case Intrinsic::x86_mmx_pmull_w: // llvm.x86.mmx.pmull.w	return Intrinsic::hexagon_S2_asl_i_r_xacc; // "__builtin_HEXAG
	case Intrinsic::x86_mmx_pmulu_dq: // llvm.x86.mmx.pmulu.dq	ON.S2.asl.i.r.xacc"
	case Intrinsic::x86_mmx_por: // llvm.x86.mmx.por	}
	case Intrinsic::x86_mmx_psad_bw: // llvm.x86.mmx.psad.bw	break;
	case Intrinsic::x86_mmx_psll_d: // llvm.x86.mmx.psll.d	case 'd': // 1 string to match.
	case Intrinsic::x86_mmx_psll_q: // llvm.x86.mmx.psll.q	if (BuiltinName.substr(22, 11) != "einterleave")
	case Intrinsic::x86_mmx_psll_w: // llvm.x86.mmx.psll.w	break;
	case Intrinsic::x86_mmx_psra_d: // llvm.x86.mmx.psra.d	return Intrinsic::hexagon_S2_deinterleave; // "__builtin_HEXAG
	case Intrinsic::x86_mmx_psra_w: // llvm.x86.mmx.psra.w	ON.S2.deinterleave"
	case Intrinsic::x86_mmx_psrl_d: // llvm.x86.mmx.psrl.d	case 'e': // 1 string to match.
	case Intrinsic::x86_mmx_psrl_q: // llvm.x86.mmx.psrl.q	if (BuiltinName.substr(22, 11) != "xtractup.rp")
	case Intrinsic::x86_mmx_psrl_w: // llvm.x86.mmx.psrl.w	break;
	case Intrinsic::x86_mmx_psub_b: // llvm.x86.mmx.psub.b	return Intrinsic::hexagon_S2_extractup_rp; // "__builtin_HEXAG
	case Intrinsic::x86_mmx_psub_d: // llvm.x86.mmx.psub.d	ON.S2.extractup.rp"
	case Intrinsic::x86_mmx_psub_q: // llvm.x86.mmx.psub.q	case 'l': // 2 strings to match.
	case Intrinsic::x86_mmx_psub_w: // llvm.x86.mmx.psub.w	if (BuiltinName.substr(22, 5) != "sr.i.")
	case Intrinsic::x86_mmx_psubs_b: // llvm.x86.mmx.psubs.b	break;
	case Intrinsic::x86_mmx_psubs_w: // llvm.x86.mmx.psubs.w	switch (BuiltinName[27]) {
	case Intrinsic::x86_mmx_psubus_b: // llvm.x86.mmx.psubus.b	default: break;
	case Intrinsic::x86_mmx_psubus_w: // llvm.x86.mmx.psubus.w	case 'p': // 1 string to match.
	case Intrinsic::x86_mmx_punpckhbw: // llvm.x86.mmx.punpckhbw	if (BuiltinName.substr(28, 5) != ".xacc")
	case Intrinsic::x86_mmx_punpckhdq: // llvm.x86.mmx.punpckhdq	break;
	case Intrinsic::x86_mmx_punpckhwd: // llvm.x86.mmx.punpckhwd	return Intrinsic::hexagon_S2_lsr_i_p_xacc; // "__builtin_HEXAG
	case Intrinsic::x86_mmx_punpcklbw: // llvm.x86.mmx.punpcklbw	ON.S2.lsr.i.p.xacc"
	case Intrinsic::x86_mmx_punpckldq: // llvm.x86.mmx.punpckldq	case 'r': // 1 string to match.
	case Intrinsic::x86_mmx_punpcklwd: // llvm.x86.mmx.punpcklwd	if (BuiltinName.substr(28, 5) != ".xacc")
	case Intrinsic::x86_mmx_pxor: // llvm.x86.mmx.pxor	break;
	case Intrinsic::x86_ssse3_phadd_d: // llvm.x86.ssse3.phadd.d	return Intrinsic::hexagon_S2_lsr_i_r_xacc; // "__builtin_HEXAG
	case Intrinsic::x86_ssse3_phadd_sw: // llvm.x86.ssse3.phadd.sw	ON.S2.lsr.i.r.xacc"
	case Intrinsic::x86_ssse3_phadd_w: // llvm.x86.ssse3.phadd.w	}
	case Intrinsic::x86_ssse3_phsub_d: // llvm.x86.ssse3.phsub.d	break;
	case Intrinsic::x86_ssse3_phsub_sw: // llvm.x86.ssse3.phsub.sw	}
	case Intrinsic::x86_ssse3_phsub_w: // llvm.x86.ssse3.phsub.w	break;
	case Intrinsic::x86_ssse3_pmadd_ub_sw: // llvm.x86.ssse3.pm	}
	add.ub.sw
	case Intrinsic::x86_ssse3_pmul_hr_sw: // llvm.x86.ssse3.pm
	ul.hr.sw
	case Intrinsic::x86_ssse3_pshuf_b: // llvm.x86.ssse3.pshuf.b
	case Intrinsic::x86_ssse3_psign_b: // llvm.x86.ssse3.psign.b
	case Intrinsic::x86_ssse3_psign_d: // llvm.x86.ssse3.psign.d
	case Intrinsic::x86_ssse3_psign_w: // llvm.x86.ssse3.psign.w
	ResultTy = Type::getX86_MMXTy(Context);
	ArgTys.push_back(Type::getX86_MMXTy(Context));
	ArgTys.push_back(Type::getX86_MMXTy(Context));
	break;	break;

	case Intrinsic::x86_mmx_palignr_b: // llvm.x86.mmx.palignr.b	case 34: // 36 strings to match.
	ResultTy = Type::getX86_MMXTy(Context);	if (BuiltinName.substr(0, 18) != "__builtin_HEXAGON.")
	ArgTys.push_back(Type::getX86_MMXTy(Context));	break;
	ArgTys.push_back(Type::getX86_MMXTy(Context));	switch (BuiltinName[18]) {
	ArgTys.push_back(IntegerType::get(Context, 8));	default: break;
		case 'M': // 34 strings to match.
		if (BuiltinName.substr(19, 2) != "2.")
		break;
		switch (BuiltinName[21]) {
		default: break;
		case 'm': // 32 strings to match.
		if (BuiltinName.substr(22, 3) != "py.")
		break;
		switch (BuiltinName[25]) {
		default: break;
		case 'a': // 8 strings to match.
		if (BuiltinName.substr(26, 3) != "cc.")
		break;
		switch (BuiltinName[29]) {
		default: break;
		case 'h': // 4 strings to match.
		switch (BuiltinName[30]) {
		default: break;
		case 'h': // 2 strings to match.
		if (BuiltinName.substr(31, 2) != ".s")
		break;
		switch (BuiltinName[33]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_acc_hh_s0; // "__built
		in_HEXAGON.M2.mpy.acc.hh.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_acc_hh_s1; // "__built
		in_HEXAGON.M2.mpy.acc.hh.s1"
		}
		break;
		case 'l': // 2 strings to match.
		if (BuiltinName.substr(31, 2) != ".s")
		break;
		switch (BuiltinName[33]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_acc_hl_s0; // "__built
		in_HEXAGON.M2.mpy.acc.hl.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_acc_hl_s1; // "__built
		in_HEXAGON.M2.mpy.acc.hl.s1"
		}
		break;
		}
		break;
		case 'l': // 4 strings to match.
		switch (BuiltinName[30]) {
		default: break;
		case 'h': // 2 strings to match.
		if (BuiltinName.substr(31, 2) != ".s")
		break;
		switch (BuiltinName[33]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_acc_lh_s0; // "__built
		in_HEXAGON.M2.mpy.acc.lh.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_acc_lh_s1; // "__built
		in_HEXAGON.M2.mpy.acc.lh.s1"
		}
		break;
		case 'l': // 2 strings to match.
		if (BuiltinName.substr(31, 2) != ".s")
		break;
		switch (BuiltinName[33]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_acc_ll_s0; // "__built
		in_HEXAGON.M2.mpy.acc.ll.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_acc_ll_s1; // "__built
		in_HEXAGON.M2.mpy.acc.ll.s1"
		}
		break;
		}
		break;
		}
		break;
		case 'n': // 8 strings to match.
		if (BuiltinName.substr(26, 3) != "ac.")
		break;
		switch (BuiltinName[29]) {
		default: break;
		case 'h': // 4 strings to match.
		switch (BuiltinName[30]) {
		default: break;
		case 'h': // 2 strings to match.
		if (BuiltinName.substr(31, 2) != ".s")
		break;
		switch (BuiltinName[33]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_nac_hh_s0; // "__built
		in_HEXAGON.M2.mpy.nac.hh.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_nac_hh_s1; // "__built
		in_HEXAGON.M2.mpy.nac.hh.s1"
		}
		break;
		case 'l': // 2 strings to match.
		if (BuiltinName.substr(31, 2) != ".s")
		break;
		switch (BuiltinName[33]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_nac_hl_s0; // "__built
		in_HEXAGON.M2.mpy.nac.hl.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_nac_hl_s1; // "__built
		in_HEXAGON.M2.mpy.nac.hl.s1"
		}
		break;
		}
		break;
		case 'l': // 4 strings to match.
		switch (BuiltinName[30]) {
		default: break;
		case 'h': // 2 strings to match.
		if (BuiltinName.substr(31, 2) != ".s")
		break;
		switch (BuiltinName[33]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_nac_lh_s0; // "__built
		in_HEXAGON.M2.mpy.nac.lh.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_nac_lh_s1; // "__built
		in_HEXAGON.M2.mpy.nac.lh.s1"
		}
		break;
		case 'l': // 2 strings to match.
		if (BuiltinName.substr(31, 2) != ".s")
		break;
		switch (BuiltinName[33]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_nac_ll_s0; // "__built
		in_HEXAGON.M2.mpy.nac.ll.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_nac_ll_s1; // "__built
		in_HEXAGON.M2.mpy.nac.ll.s1"
		}
		break;
		}
		break;
		}
		break;
		case 'r': // 8 strings to match.
		if (BuiltinName.substr(26, 3) != "nd.")
		break;
		switch (BuiltinName[29]) {
		default: break;
		case 'h': // 4 strings to match.
		switch (BuiltinName[30]) {
		default: break;
		case 'h': // 2 strings to match.
		if (BuiltinName.substr(31, 2) != ".s")
		break;
		switch (BuiltinName[33]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_rnd_hh_s0; // "__built
		in_HEXAGON.M2.mpy.rnd.hh.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_rnd_hh_s1; // "__built
		in_HEXAGON.M2.mpy.rnd.hh.s1"
		}
		break;
		case 'l': // 2 strings to match.
		if (BuiltinName.substr(31, 2) != ".s")
		break;
		switch (BuiltinName[33]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_rnd_hl_s0; // "__built
		in_HEXAGON.M2.mpy.rnd.hl.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_rnd_hl_s1; // "__built
		in_HEXAGON.M2.mpy.rnd.hl.s1"
		}
		break;
		}
		break;
		case 'l': // 4 strings to match.
		switch (BuiltinName[30]) {
		default: break;
		case 'h': // 2 strings to match.
		if (BuiltinName.substr(31, 2) != ".s")
		break;
		switch (BuiltinName[33]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_rnd_lh_s0; // "__built
		in_HEXAGON.M2.mpy.rnd.lh.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_rnd_lh_s1; // "__built
		in_HEXAGON.M2.mpy.rnd.lh.s1"
		}
		break;
		case 'l': // 2 strings to match.
		if (BuiltinName.substr(31, 2) != ".s")
		break;
		switch (BuiltinName[33]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_rnd_ll_s0; // "__built
		in_HEXAGON.M2.mpy.rnd.ll.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_rnd_ll_s1; // "__built
		in_HEXAGON.M2.mpy.rnd.ll.s1"
		}
		break;
		}
		break;
		}
		break;
		case 's': // 8 strings to match.
		if (BuiltinName.substr(26, 3) != "at.")
		break;
		switch (BuiltinName[29]) {
		default: break;
		case 'h': // 4 strings to match.
		switch (BuiltinName[30]) {
		default: break;
		case 'h': // 2 strings to match.
		if (BuiltinName.substr(31, 2) != ".s")
		break;
		switch (BuiltinName[33]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_sat_hh_s0; // "__built
		in_HEXAGON.M2.mpy.sat.hh.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_sat_hh_s1; // "__built
		in_HEXAGON.M2.mpy.sat.hh.s1"
		}
		break;
		case 'l': // 2 strings to match.
		if (BuiltinName.substr(31, 2) != ".s")
		break;
		switch (BuiltinName[33]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_sat_hl_s0; // "__built
		in_HEXAGON.M2.mpy.sat.hl.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_sat_hl_s1; // "__built
		in_HEXAGON.M2.mpy.sat.hl.s1"
		}
		break;
		}
		break;
		case 'l': // 4 strings to match.
		switch (BuiltinName[30]) {
		default: break;
		case 'h': // 2 strings to match.
		if (BuiltinName.substr(31, 2) != ".s")
		break;
		switch (BuiltinName[33]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_sat_lh_s0; // "__built
		in_HEXAGON.M2.mpy.sat.lh.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_sat_lh_s1; // "__built
		in_HEXAGON.M2.mpy.sat.lh.s1"
		}
		break;
		case 'l': // 2 strings to match.
		if (BuiltinName.substr(31, 2) != ".s")
		break;
		switch (BuiltinName[33]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_sat_ll_s0; // "__built
		in_HEXAGON.M2.mpy.sat.ll.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_sat_ll_s1; // "__built
		in_HEXAGON.M2.mpy.sat.ll.s1"
		}
		break;
		}
		break;
		}
		break;
		}
		break;
		case 'v': // 2 strings to match.
		if (BuiltinName.substr(22, 7) != "mpy2s.s")
		break;
		switch (BuiltinName[29]) {
		default: break;
		case '0': // 1 string to match.
		if (BuiltinName.substr(30, 4) != "pack")
		break;
		return Intrinsic::hexagon_M2_vmpy2s_s0pack; // "__builtin_HEXAG
		ON.M2.vmpy2s.s0pack"
		case '1': // 1 string to match.
		if (BuiltinName.substr(30, 4) != "pack")
		break;
		return Intrinsic::hexagon_M2_vmpy2s_s1pack; // "__builtin_HEXAG
		ON.M2.vmpy2s.s1pack"
		}
		break;
		}
		break;
		case 'S': // 2 strings to match.
		if (BuiltinName.substr(19, 6) != "2.vsat")
		break;
		switch (BuiltinName[25]) {
		default: break;
		case 'h': // 1 string to match.
		if (BuiltinName.substr(26, 8) != "b.nopack")
		break;
		return Intrinsic::hexagon_S2_vsathb_nopack; // "__builtin_HEXAG
		ON.S2.vsathb.nopack"
		case 'w': // 1 string to match.
		if (BuiltinName.substr(26, 8) != "h.nopack")
		break;
		return Intrinsic::hexagon_S2_vsatwh_nopack; // "__builtin_HEXAG
		ON.S2.vsatwh.nopack"
		}
		break;
		}
	break;	break;

	}	case 35: // 56 strings to match.
	#endif	if (BuiltinName.substr(0, 18) != "__builtin_HEXAGON.")
		break;
	// Add parameter attributes that are not common to all intrinsics.	switch (BuiltinName[18]) {
	#ifdef GET_INTRINSIC_ATTRIBUTES
	AttrListPtr Intrinsic::getAttributes(ID id) {
	AttributeWithIndex AWI[3];
	unsigned NumAttrs = 0;
	switch (id) {
	default: break;	default: break;

	case Intrinsic::alpha_umulh:	case 'M': // 52 strings to match.
	case Intrinsic::arm_get_fpscr:	if (BuiltinName.substr(19, 2) != "2.")
	case Intrinsic::arm_neon_vabds:	break;
	case Intrinsic::arm_neon_vabdu:	switch (BuiltinName[21]) {
	case Intrinsic::arm_neon_vabs:	default: break;
	case Intrinsic::arm_neon_vacged:	case 'd': // 5 strings to match.
	case Intrinsic::arm_neon_vacgeq:	if (BuiltinName.substr(22, 4) != "pmpy")
	case Intrinsic::arm_neon_vacgtd:	break;
	case Intrinsic::arm_neon_vacgtq:	switch (BuiltinName[26]) {
	case Intrinsic::arm_neon_vaddhn:	default: break;
	case Intrinsic::arm_neon_vcls:	case 's': // 3 strings to match.
	case Intrinsic::arm_neon_vclz:	if (BuiltinName.substr(27, 2) != "s.")
	case Intrinsic::arm_neon_vcnt:	break;
	case Intrinsic::arm_neon_vcvtfp2fxs:	switch (BuiltinName[29]) {
	case Intrinsic::arm_neon_vcvtfp2fxu:	default: break;
	case Intrinsic::arm_neon_vcvtfp2hf:	case 'a': // 1 string to match.
	case Intrinsic::arm_neon_vcvtfxs2fp:	if (BuiltinName.substr(30, 5) != "cc.s0")
	case Intrinsic::arm_neon_vcvtfxu2fp:	break;
	case Intrinsic::arm_neon_vcvthf2fp:	return Intrinsic::hexagon_M2_dpmpyss_acc_s0; // "__built
	case Intrinsic::arm_neon_vhadds:	in_HEXAGON.M2.dpmpyss.acc.s0"
	case Intrinsic::arm_neon_vhaddu:	case 'n': // 1 string to match.
	case Intrinsic::arm_neon_vhsubs:	if (BuiltinName.substr(30, 5) != "ac.s0")
	case Intrinsic::arm_neon_vhsubu:	break;
	case Intrinsic::arm_neon_vmaxs:	return Intrinsic::hexagon_M2_dpmpyss_nac_s0; // "__built
	case Intrinsic::arm_neon_vmaxu:	in_HEXAGON.M2.dpmpyss.nac.s0"
	case Intrinsic::arm_neon_vmins:	case 'r': // 1 string to match.
	case Intrinsic::arm_neon_vminu:	if (BuiltinName.substr(30, 5) != "nd.s0")
	case Intrinsic::arm_neon_vmullp:	break;
	case Intrinsic::arm_neon_vmulls:	return Intrinsic::hexagon_M2_dpmpyss_rnd_s0; // "__built
	case Intrinsic::arm_neon_vmullu:	in_HEXAGON.M2.dpmpyss.rnd.s0"
	case Intrinsic::arm_neon_vmulp:	}
	case Intrinsic::arm_neon_vpadals:	break;
	case Intrinsic::arm_neon_vpadalu:	case 'u': // 2 strings to match.
	case Intrinsic::arm_neon_vpadd:	if (BuiltinName.substr(27, 2) != "u.")
	case Intrinsic::arm_neon_vpaddls:	break;
	case Intrinsic::arm_neon_vpaddlu:	switch (BuiltinName[29]) {
	case Intrinsic::arm_neon_vpmaxs:	default: break;
	case Intrinsic::arm_neon_vpmaxu:	case 'a': // 1 string to match.
	case Intrinsic::arm_neon_vpmins:	if (BuiltinName.substr(30, 5) != "cc.s0")
	case Intrinsic::arm_neon_vpminu:	break;
	case Intrinsic::arm_neon_vqabs:	return Intrinsic::hexagon_M2_dpmpyuu_acc_s0; // "__built
	case Intrinsic::arm_neon_vqadds:	in_HEXAGON.M2.dpmpyuu.acc.s0"
	case Intrinsic::arm_neon_vqaddu:	case 'n': // 1 string to match.
	case Intrinsic::arm_neon_vqdmlal:	if (BuiltinName.substr(30, 5) != "ac.s0")
	case Intrinsic::arm_neon_vqdmlsl:	break;
	case Intrinsic::arm_neon_vqdmulh:	return Intrinsic::hexagon_M2_dpmpyuu_nac_s0; // "__built
	case Intrinsic::arm_neon_vqdmull:	in_HEXAGON.M2.dpmpyuu.nac.s0"
	case Intrinsic::arm_neon_vqmovns:	}
	case Intrinsic::arm_neon_vqmovnsu:	break;
	case Intrinsic::arm_neon_vqmovnu:	}
	case Intrinsic::arm_neon_vqneg:	break;
	case Intrinsic::arm_neon_vqrdmulh:	case 'm': // 40 strings to match.
	case Intrinsic::arm_neon_vqrshiftns:	if (BuiltinName.substr(22, 2) != "py")
	case Intrinsic::arm_neon_vqrshiftnsu:	break;
	case Intrinsic::arm_neon_vqrshiftnu:	switch (BuiltinName[24]) {
	case Intrinsic::arm_neon_vqrshifts:	default: break;
	case Intrinsic::arm_neon_vqrshiftu:	case 'd': // 24 strings to match.
	case Intrinsic::arm_neon_vqshiftns:	if (BuiltinName[25] != '.')
	case Intrinsic::arm_neon_vqshiftnsu:	break;
	case Intrinsic::arm_neon_vqshiftnu:	switch (BuiltinName[26]) {
	case Intrinsic::arm_neon_vqshifts:	default: break;
	case Intrinsic::arm_neon_vqshiftsu:	case 'a': // 8 strings to match.
	case Intrinsic::arm_neon_vqshiftu:	if (BuiltinName.substr(27, 3) != "cc.")
	case Intrinsic::arm_neon_vqsubs:	break;
	case Intrinsic::arm_neon_vqsubu:	switch (BuiltinName[30]) {
	case Intrinsic::arm_neon_vraddhn:	default: break;
	case Intrinsic::arm_neon_vrecpe:	case 'h': // 4 strings to match.
	case Intrinsic::arm_neon_vrecps:	switch (BuiltinName[31]) {
	case Intrinsic::arm_neon_vrhadds:	default: break;
	case Intrinsic::arm_neon_vrhaddu:	case 'h': // 2 strings to match.
	case Intrinsic::arm_neon_vrshiftn:	if (BuiltinName.substr(32, 2) != ".s")
	case Intrinsic::arm_neon_vrshifts:	break;
	case Intrinsic::arm_neon_vrshiftu:	switch (BuiltinName[34]) {
	case Intrinsic::arm_neon_vrsqrte:	default: break;
	case Intrinsic::arm_neon_vrsqrts:	case '0': // 1 string to match.
	case Intrinsic::arm_neon_vrsubhn:	return Intrinsic::hexagon_M2_mpyd_acc_hh_s0; // "__built
	case Intrinsic::arm_neon_vshiftins:	in_HEXAGON.M2.mpyd.acc.hh.s0"
	case Intrinsic::arm_neon_vshiftls:	case '1': // 1 string to match.
	case Intrinsic::arm_neon_vshiftlu:	return Intrinsic::hexagon_M2_mpyd_acc_hh_s1; // "__built
	case Intrinsic::arm_neon_vshiftn:	in_HEXAGON.M2.mpyd.acc.hh.s1"
	case Intrinsic::arm_neon_vshifts:	}
	case Intrinsic::arm_neon_vshiftu:	break;
	case Intrinsic::arm_neon_vsubhn:	case 'l': // 2 strings to match.
	case Intrinsic::arm_neon_vtbl1:	if (BuiltinName.substr(32, 2) != ".s")
	case Intrinsic::arm_neon_vtbl2:	break;
	case Intrinsic::arm_neon_vtbl3:	switch (BuiltinName[34]) {
	case Intrinsic::arm_neon_vtbl4:	default: break;
	case Intrinsic::arm_neon_vtbx1:	case '0': // 1 string to match.
	case Intrinsic::arm_neon_vtbx2:	return Intrinsic::hexagon_M2_mpyd_acc_hl_s0; // "__built
	case Intrinsic::arm_neon_vtbx3:	in_HEXAGON.M2.mpyd.acc.hl.s0"
	case Intrinsic::arm_neon_vtbx4:	case '1': // 1 string to match.
	case Intrinsic::arm_qadd:	return Intrinsic::hexagon_M2_mpyd_acc_hl_s1; // "__built
	case Intrinsic::arm_qsub:	in_HEXAGON.M2.mpyd.acc.hl.s1"
	case Intrinsic::arm_ssat:	}
	case Intrinsic::arm_thread_pointer:	break;
	case Intrinsic::arm_usat:	}
	case Intrinsic::arm_vcvtr:	break;
	case Intrinsic::arm_vcvtru:	case 'l': // 4 strings to match.
	case Intrinsic::bswap:	switch (BuiltinName[31]) {
	case Intrinsic::convert_from_fp16:	default: break;
	case Intrinsic::convert_to_fp16:	case 'h': // 2 strings to match.
	case Intrinsic::ctlz:	if (BuiltinName.substr(32, 2) != ".s")
	case Intrinsic::ctpop:	break;
	case Intrinsic::cttz:	switch (BuiltinName[34]) {
	case Intrinsic::dbg_declare:	default: break;
	case Intrinsic::dbg_value:	case '0': // 1 string to match.
	case Intrinsic::eh_sjlj_callsite:	return Intrinsic::hexagon_M2_mpyd_acc_lh_s0; // "__built
	case Intrinsic::eh_sjlj_lsda:	in_HEXAGON.M2.mpyd.acc.lh.s0"
	case Intrinsic::eh_typeid_for:	case '1': // 1 string to match.
	case Intrinsic::expect:	return Intrinsic::hexagon_M2_mpyd_acc_lh_s1; // "__built
	case Intrinsic::fma:	in_HEXAGON.M2.mpyd.acc.lh.s1"
	case Intrinsic::frameaddress:	}
	case Intrinsic::objectsize:	break;
	case Intrinsic::ppc_altivec_lvsl:	case 'l': // 2 strings to match.
	case Intrinsic::ppc_altivec_lvsr:	if (BuiltinName.substr(32, 2) != ".s")
	case Intrinsic::ppc_altivec_vaddcuw:	break;
	case Intrinsic::ppc_altivec_vaddsbs:	switch (BuiltinName[34]) {
	case Intrinsic::ppc_altivec_vaddshs:	default: break;
	case Intrinsic::ppc_altivec_vaddsws:	case '0': // 1 string to match.
	case Intrinsic::ppc_altivec_vaddubs:	return Intrinsic::hexagon_M2_mpyd_acc_ll_s0; // "__built
	case Intrinsic::ppc_altivec_vadduhs:	in_HEXAGON.M2.mpyd.acc.ll.s0"
	case Intrinsic::ppc_altivec_vadduws:	case '1': // 1 string to match.
	case Intrinsic::ppc_altivec_vavgsb:	return Intrinsic::hexagon_M2_mpyd_acc_ll_s1; // "__built
	case Intrinsic::ppc_altivec_vavgsh:	in_HEXAGON.M2.mpyd.acc.ll.s1"
	case Intrinsic::ppc_altivec_vavgsw:	}
	case Intrinsic::ppc_altivec_vavgub:	break;
	case Intrinsic::ppc_altivec_vavguh:	}
	case Intrinsic::ppc_altivec_vavguw:	break;
	case Intrinsic::ppc_altivec_vcfsx:	}
	case Intrinsic::ppc_altivec_vcfux:	break;
	case Intrinsic::ppc_altivec_vcmpbfp:	case 'n': // 8 strings to match.
	case Intrinsic::ppc_altivec_vcmpbfp_p:	if (BuiltinName.substr(27, 3) != "ac.")
	case Intrinsic::ppc_altivec_vcmpeqfp:	break;
	case Intrinsic::ppc_altivec_vcmpeqfp_p:	switch (BuiltinName[30]) {
	case Intrinsic::ppc_altivec_vcmpequb:	default: break;
	case Intrinsic::ppc_altivec_vcmpequb_p:	case 'h': // 4 strings to match.
	case Intrinsic::ppc_altivec_vcmpequh:	switch (BuiltinName[31]) {
	case Intrinsic::ppc_altivec_vcmpequh_p:	default: break;
	case Intrinsic::ppc_altivec_vcmpequw:	case 'h': // 2 strings to match.
	case Intrinsic::ppc_altivec_vcmpequw_p:	if (BuiltinName.substr(32, 2) != ".s")
	case Intrinsic::ppc_altivec_vcmpgefp:	break;
	case Intrinsic::ppc_altivec_vcmpgefp_p:	switch (BuiltinName[34]) {
	case Intrinsic::ppc_altivec_vcmpgtfp:	default: break;
	case Intrinsic::ppc_altivec_vcmpgtfp_p:	case '0': // 1 string to match.
	case Intrinsic::ppc_altivec_vcmpgtsb:	return Intrinsic::hexagon_M2_mpyd_nac_hh_s0; // "__built
	case Intrinsic::ppc_altivec_vcmpgtsb_p:	in_HEXAGON.M2.mpyd.nac.hh.s0"
	case Intrinsic::ppc_altivec_vcmpgtsh:	case '1': // 1 string to match.
	case Intrinsic::ppc_altivec_vcmpgtsh_p:	return Intrinsic::hexagon_M2_mpyd_nac_hh_s1; // "__built
	case Intrinsic::ppc_altivec_vcmpgtsw:	in_HEXAGON.M2.mpyd.nac.hh.s1"
	case Intrinsic::ppc_altivec_vcmpgtsw_p:	}
	case Intrinsic::ppc_altivec_vcmpgtub:	break;
	case Intrinsic::ppc_altivec_vcmpgtub_p:	case 'l': // 2 strings to match.
	case Intrinsic::ppc_altivec_vcmpgtuh:	if (BuiltinName.substr(32, 2) != ".s")
	case Intrinsic::ppc_altivec_vcmpgtuh_p:	break;
	case Intrinsic::ppc_altivec_vcmpgtuw:	switch (BuiltinName[34]) {
	case Intrinsic::ppc_altivec_vcmpgtuw_p:	default: break;
	case Intrinsic::ppc_altivec_vctsxs:	case '0': // 1 string to match.
	case Intrinsic::ppc_altivec_vctuxs:	return Intrinsic::hexagon_M2_mpyd_nac_hl_s0; // "__built
	case Intrinsic::ppc_altivec_vexptefp:	in_HEXAGON.M2.mpyd.nac.hl.s0"
	case Intrinsic::ppc_altivec_vlogefp:	case '1': // 1 string to match.
	case Intrinsic::ppc_altivec_vmaddfp:	return Intrinsic::hexagon_M2_mpyd_nac_hl_s1; // "__built
	case Intrinsic::ppc_altivec_vmaxfp:	in_HEXAGON.M2.mpyd.nac.hl.s1"
	case Intrinsic::ppc_altivec_vmaxsb:	}
	case Intrinsic::ppc_altivec_vmaxsh:	break;
	case Intrinsic::ppc_altivec_vmaxsw:	}
	case Intrinsic::ppc_altivec_vmaxub:	break;
	case Intrinsic::ppc_altivec_vmaxuh:	case 'l': // 4 strings to match.
	case Intrinsic::ppc_altivec_vmaxuw:	switch (BuiltinName[31]) {
	case Intrinsic::ppc_altivec_vmhaddshs:	default: break;
	case Intrinsic::ppc_altivec_vmhraddshs:	case 'h': // 2 strings to match.
	case Intrinsic::ppc_altivec_vminfp:	if (BuiltinName.substr(32, 2) != ".s")
	case Intrinsic::ppc_altivec_vminsb:	break;
	case Intrinsic::ppc_altivec_vminsh:	switch (BuiltinName[34]) {
	case Intrinsic::ppc_altivec_vminsw:	default: break;
	case Intrinsic::ppc_altivec_vminub:	case '0': // 1 string to match.
	case Intrinsic::ppc_altivec_vminuh:	return Intrinsic::hexagon_M2_mpyd_nac_lh_s0; // "__built
	case Intrinsic::ppc_altivec_vminuw:	in_HEXAGON.M2.mpyd.nac.lh.s0"
	case Intrinsic::ppc_altivec_vmladduhm:	case '1': // 1 string to match.
	case Intrinsic::ppc_altivec_vmsummbm:	return Intrinsic::hexagon_M2_mpyd_nac_lh_s1; // "__built
	case Intrinsic::ppc_altivec_vmsumshm:	in_HEXAGON.M2.mpyd.nac.lh.s1"
	case Intrinsic::ppc_altivec_vmsumshs:	}
	case Intrinsic::ppc_altivec_vmsumubm:	break;
	case Intrinsic::ppc_altivec_vmsumuhm:	case 'l': // 2 strings to match.
	case Intrinsic::ppc_altivec_vmsumuhs:	if (BuiltinName.substr(32, 2) != ".s")
	case Intrinsic::ppc_altivec_vmulesb:	break;
	case Intrinsic::ppc_altivec_vmulesh:	switch (BuiltinName[34]) {
	case Intrinsic::ppc_altivec_vmuleub:	default: break;
	case Intrinsic::ppc_altivec_vmuleuh:	case '0': // 1 string to match.
	case Intrinsic::ppc_altivec_vmulosb:	return Intrinsic::hexagon_M2_mpyd_nac_ll_s0; // "__built
	case Intrinsic::ppc_altivec_vmulosh:	in_HEXAGON.M2.mpyd.nac.ll.s0"
	case Intrinsic::ppc_altivec_vmuloub:	case '1': // 1 string to match.
	case Intrinsic::ppc_altivec_vmulouh:	return Intrinsic::hexagon_M2_mpyd_nac_ll_s1; // "__built
	case Intrinsic::ppc_altivec_vnmsubfp:	in_HEXAGON.M2.mpyd.nac.ll.s1"
	case Intrinsic::ppc_altivec_vperm:	}
	case Intrinsic::ppc_altivec_vpkpx:	break;
	case Intrinsic::ppc_altivec_vpkshss:	}
	case Intrinsic::ppc_altivec_vpkshus:	break;
	case Intrinsic::ppc_altivec_vpkswss:	}
	case Intrinsic::ppc_altivec_vpkswus:	break;
	case Intrinsic::ppc_altivec_vpkuhus:	case 'r': // 8 strings to match.
	case Intrinsic::ppc_altivec_vpkuwus:	if (BuiltinName.substr(27, 3) != "nd.")
	case Intrinsic::ppc_altivec_vrefp:	break;
	case Intrinsic::ppc_altivec_vrfim:	switch (BuiltinName[30]) {
	case Intrinsic::ppc_altivec_vrfin:	default: break;
	case Intrinsic::ppc_altivec_vrfip:	case 'h': // 4 strings to match.
	case Intrinsic::ppc_altivec_vrfiz:	switch (BuiltinName[31]) {
	case Intrinsic::ppc_altivec_vrlb:	default: break;
	case Intrinsic::ppc_altivec_vrlh:	case 'h': // 2 strings to match.
	case Intrinsic::ppc_altivec_vrlw:	if (BuiltinName.substr(32, 2) != ".s")
	case Intrinsic::ppc_altivec_vrsqrtefp:	break;
	case Intrinsic::ppc_altivec_vsel:	switch (BuiltinName[34]) {
	case Intrinsic::ppc_altivec_vsl:	default: break;
	case Intrinsic::ppc_altivec_vslb:	case '0': // 1 string to match.
	case Intrinsic::ppc_altivec_vslh:	return Intrinsic::hexagon_M2_mpyd_rnd_hh_s0; // "__built
	case Intrinsic::ppc_altivec_vslo:	in_HEXAGON.M2.mpyd.rnd.hh.s0"
	case Intrinsic::ppc_altivec_vslw:	case '1': // 1 string to match.
	case Intrinsic::ppc_altivec_vsr:	return Intrinsic::hexagon_M2_mpyd_rnd_hh_s1; // "__built
	case Intrinsic::ppc_altivec_vsrab:	in_HEXAGON.M2.mpyd.rnd.hh.s1"
	case Intrinsic::ppc_altivec_vsrah:	}
	case Intrinsic::ppc_altivec_vsraw:	break;
	case Intrinsic::ppc_altivec_vsrb:	case 'l': // 2 strings to match.
	case Intrinsic::ppc_altivec_vsrh:	if (BuiltinName.substr(32, 2) != ".s")
	case Intrinsic::ppc_altivec_vsro:	break;
	case Intrinsic::ppc_altivec_vsrw:	switch (BuiltinName[34]) {
	case Intrinsic::ppc_altivec_vsubcuw:	default: break;
	case Intrinsic::ppc_altivec_vsubsbs:	case '0': // 1 string to match.
	case Intrinsic::ppc_altivec_vsubshs:	return Intrinsic::hexagon_M2_mpyd_rnd_hl_s0; // "__built
	case Intrinsic::ppc_altivec_vsubsws:	in_HEXAGON.M2.mpyd.rnd.hl.s0"
	case Intrinsic::ppc_altivec_vsububs:	case '1': // 1 string to match.
	case Intrinsic::ppc_altivec_vsubuhs:	return Intrinsic::hexagon_M2_mpyd_rnd_hl_s1; // "__built
	case Intrinsic::ppc_altivec_vsubuws:	in_HEXAGON.M2.mpyd.rnd.hl.s1"
	case Intrinsic::ppc_altivec_vsum2sws:	}
	case Intrinsic::ppc_altivec_vsum4sbs:	break;
	case Intrinsic::ppc_altivec_vsum4shs:	}
	case Intrinsic::ppc_altivec_vsum4ubs:	break;
	case Intrinsic::ppc_altivec_vsumsws:	case 'l': // 4 strings to match.
	case Intrinsic::ppc_altivec_vupkhpx:	switch (BuiltinName[31]) {
	case Intrinsic::ppc_altivec_vupkhsb:	default: break;
	case Intrinsic::ppc_altivec_vupkhsh:	case 'h': // 2 strings to match.
	case Intrinsic::ppc_altivec_vupklpx:	if (BuiltinName.substr(32, 2) != ".s")
	case Intrinsic::ppc_altivec_vupklsb:	break;
	case Intrinsic::ppc_altivec_vupklsh:	switch (BuiltinName[34]) {
	case Intrinsic::ptx_read_clock:	default: break;
	case Intrinsic::ptx_read_clock64:	case '0': // 1 string to match.
	case Intrinsic::ptx_read_ctaid_w:	return Intrinsic::hexagon_M2_mpyd_rnd_lh_s0; // "__built
	case Intrinsic::ptx_read_ctaid_x:	in_HEXAGON.M2.mpyd.rnd.lh.s0"
	case Intrinsic::ptx_read_ctaid_y:	case '1': // 1 string to match.
	case Intrinsic::ptx_read_ctaid_z:	return Intrinsic::hexagon_M2_mpyd_rnd_lh_s1; // "__built
	case Intrinsic::ptx_read_gridid:	in_HEXAGON.M2.mpyd.rnd.lh.s1"
	case Intrinsic::ptx_read_laneid:	}
	case Intrinsic::ptx_read_lanemask_eq:	break;
	case Intrinsic::ptx_read_lanemask_ge:	case 'l': // 2 strings to match.
	case Intrinsic::ptx_read_lanemask_gt:	if (BuiltinName.substr(32, 2) != ".s")
	case Intrinsic::ptx_read_lanemask_le:	break;
	case Intrinsic::ptx_read_lanemask_lt:	switch (BuiltinName[34]) {
	case Intrinsic::ptx_read_nctaid_w:	default: break;
	case Intrinsic::ptx_read_nctaid_x:	case '0': // 1 string to match.
	case Intrinsic::ptx_read_nctaid_y:	return Intrinsic::hexagon_M2_mpyd_rnd_ll_s0; // "__built
	case Intrinsic::ptx_read_nctaid_z:	in_HEXAGON.M2.mpyd.rnd.ll.s0"
	case Intrinsic::ptx_read_nsmid:	case '1': // 1 string to match.
	case Intrinsic::ptx_read_ntid_w:	return Intrinsic::hexagon_M2_mpyd_rnd_ll_s1; // "__built
	case Intrinsic::ptx_read_ntid_x:	in_HEXAGON.M2.mpyd.rnd.ll.s1"
	case Intrinsic::ptx_read_ntid_y:	}
	case Intrinsic::ptx_read_ntid_z:	break;
	case Intrinsic::ptx_read_nwarpid:	}
	case Intrinsic::ptx_read_pm0:	break;
	case Intrinsic::ptx_read_pm1:	}
	case Intrinsic::ptx_read_pm2:	break;
	case Intrinsic::ptx_read_pm3:	}
	case Intrinsic::ptx_read_smid:	break;
	case Intrinsic::ptx_read_tid_w:	case 'u': // 16 strings to match.
	case Intrinsic::ptx_read_tid_x:	if (BuiltinName[25] != '.')
	case Intrinsic::ptx_read_tid_y:	break;
	case Intrinsic::ptx_read_tid_z:	switch (BuiltinName[26]) {
	case Intrinsic::ptx_read_warpid:	default: break;
	case Intrinsic::returnaddress:	case 'a': // 8 strings to match.
	case Intrinsic::sadd_with_overflow:	if (BuiltinName.substr(27, 3) != "cc.")
	case Intrinsic::smul_with_overflow:	break;
	case Intrinsic::spu_si_a:	switch (BuiltinName[30]) {
	case Intrinsic::spu_si_addx:	default: break;
	case Intrinsic::spu_si_ah:	case 'h': // 4 strings to match.
	case Intrinsic::spu_si_ahi:	switch (BuiltinName[31]) {
	case Intrinsic::spu_si_ai:	default: break;
	case Intrinsic::spu_si_and:	case 'h': // 2 strings to match.
	case Intrinsic::spu_si_andbi:	if (BuiltinName.substr(32, 2) != ".s")
	case Intrinsic::spu_si_andc:	break;
	case Intrinsic::spu_si_andhi:	switch (BuiltinName[34]) {
	case Intrinsic::spu_si_andi:	default: break;
	case Intrinsic::spu_si_bg:	case '0': // 1 string to match.
	case Intrinsic::spu_si_bgx:	return Intrinsic::hexagon_M2_mpyu_acc_hh_s0; // "__built
	case Intrinsic::spu_si_ceq:	in_HEXAGON.M2.mpyu.acc.hh.s0"
	case Intrinsic::spu_si_ceqb:	case '1': // 1 string to match.
	case Intrinsic::spu_si_ceqbi:	return Intrinsic::hexagon_M2_mpyu_acc_hh_s1; // "__built
	case Intrinsic::spu_si_ceqh:	in_HEXAGON.M2.mpyu.acc.hh.s1"
	case Intrinsic::spu_si_ceqhi:	}
	case Intrinsic::spu_si_ceqi:	break;
	case Intrinsic::spu_si_cg:	case 'l': // 2 strings to match.
	case Intrinsic::spu_si_cgt:	if (BuiltinName.substr(32, 2) != ".s")
	case Intrinsic::spu_si_cgtb:	break;
	case Intrinsic::spu_si_cgtbi:	switch (BuiltinName[34]) {
	case Intrinsic::spu_si_cgth:	default: break;
	case Intrinsic::spu_si_cgthi:	case '0': // 1 string to match.
	case Intrinsic::spu_si_cgti:	return Intrinsic::hexagon_M2_mpyu_acc_hl_s0; // "__built
	case Intrinsic::spu_si_cgx:	in_HEXAGON.M2.mpyu.acc.hl.s0"
	case Intrinsic::spu_si_clgt:	case '1': // 1 string to match.
	case Intrinsic::spu_si_clgtb:	return Intrinsic::hexagon_M2_mpyu_acc_hl_s1; // "__built
	case Intrinsic::spu_si_clgtbi:	in_HEXAGON.M2.mpyu.acc.hl.s1"
	case Intrinsic::spu_si_clgth:	}
	case Intrinsic::spu_si_clgthi:	break;
	case Intrinsic::spu_si_clgti:	}
	case Intrinsic::spu_si_dfa:	break;
	case Intrinsic::spu_si_dfm:	case 'l': // 4 strings to match.
	case Intrinsic::spu_si_dfma:	switch (BuiltinName[31]) {
	case Intrinsic::spu_si_dfms:	default: break;
	case Intrinsic::spu_si_dfnma:	case 'h': // 2 strings to match.
	case Intrinsic::spu_si_dfnms:	if (BuiltinName.substr(32, 2) != ".s")
	case Intrinsic::spu_si_dfs:	break;
	case Intrinsic::spu_si_fa:	switch (BuiltinName[34]) {
	case Intrinsic::spu_si_fceq:	default: break;
	case Intrinsic::spu_si_fcgt:	case '0': // 1 string to match.
	case Intrinsic::spu_si_fcmeq:	return Intrinsic::hexagon_M2_mpyu_acc_lh_s0; // "__built
	case Intrinsic::spu_si_fcmgt:	in_HEXAGON.M2.mpyu.acc.lh.s0"
	case Intrinsic::spu_si_fm:	case '1': // 1 string to match.
	case Intrinsic::spu_si_fma:	return Intrinsic::hexagon_M2_mpyu_acc_lh_s1; // "__built
	case Intrinsic::spu_si_fms:	in_HEXAGON.M2.mpyu.acc.lh.s1"
	case Intrinsic::spu_si_fnms:	}
	case Intrinsic::spu_si_fs:	break;
	case Intrinsic::spu_si_fsmbi:	case 'l': // 2 strings to match.
	case Intrinsic::spu_si_mpy:	if (BuiltinName.substr(32, 2) != ".s")
	case Intrinsic::spu_si_mpya:	break;
	case Intrinsic::spu_si_mpyh:	switch (BuiltinName[34]) {
	case Intrinsic::spu_si_mpyhh:	default: break;
	case Intrinsic::spu_si_mpyhha:	case '0': // 1 string to match.
	case Intrinsic::spu_si_mpyhhau:	return Intrinsic::hexagon_M2_mpyu_acc_ll_s0; // "__built
	case Intrinsic::spu_si_mpyhhu:	in_HEXAGON.M2.mpyu.acc.ll.s0"
	case Intrinsic::spu_si_mpyi:	case '1': // 1 string to match.
	case Intrinsic::spu_si_mpys:	return Intrinsic::hexagon_M2_mpyu_acc_ll_s1; // "__built
	case Intrinsic::spu_si_mpyu:	in_HEXAGON.M2.mpyu.acc.ll.s1"
	case Intrinsic::spu_si_mpyui:	}
	case Intrinsic::spu_si_nand:	break;
	case Intrinsic::spu_si_nor:	}
	case Intrinsic::spu_si_or:	break;
	case Intrinsic::spu_si_orbi:	}
	case Intrinsic::spu_si_orc:	break;
	case Intrinsic::spu_si_orhi:	case 'n': // 8 strings to match.
	case Intrinsic::spu_si_ori:	if (BuiltinName.substr(27, 3) != "ac.")
	case Intrinsic::spu_si_sf:	break;
	case Intrinsic::spu_si_sfh:	switch (BuiltinName[30]) {
	case Intrinsic::spu_si_sfhi:	default: break;
	case Intrinsic::spu_si_sfi:	case 'h': // 4 strings to match.
	case Intrinsic::spu_si_sfx:	switch (BuiltinName[31]) {
	case Intrinsic::spu_si_shli:	default: break;
	case Intrinsic::spu_si_shlqbi:	case 'h': // 2 strings to match.
	case Intrinsic::spu_si_shlqbii:	if (BuiltinName.substr(32, 2) != ".s")
	case Intrinsic::spu_si_shlqby:	break;
	case Intrinsic::spu_si_shlqbyi:	switch (BuiltinName[34]) {
	case Intrinsic::spu_si_xor:	default: break;
	case Intrinsic::spu_si_xorbi:	case '0': // 1 string to match.
	case Intrinsic::spu_si_xorhi:	return Intrinsic::hexagon_M2_mpyu_nac_hh_s0; // "__built
	case Intrinsic::spu_si_xori:	in_HEXAGON.M2.mpyu.nac.hh.s0"
	case Intrinsic::ssub_with_overflow:	case '1': // 1 string to match.
	case Intrinsic::uadd_with_overflow:	return Intrinsic::hexagon_M2_mpyu_nac_hh_s1; // "__built
	case Intrinsic::umul_with_overflow:	in_HEXAGON.M2.mpyu.nac.hh.s1"
	case Intrinsic::usub_with_overflow:	}
	case Intrinsic::x86_3dnow_pavgusb:	break;
	case Intrinsic::x86_3dnow_pf2id:	case 'l': // 2 strings to match.
	case Intrinsic::x86_3dnow_pfacc:	if (BuiltinName.substr(32, 2) != ".s")
	case Intrinsic::x86_3dnow_pfadd:	break;
	case Intrinsic::x86_3dnow_pfcmpeq:	switch (BuiltinName[34]) {
	case Intrinsic::x86_3dnow_pfcmpge:	default: break;
	case Intrinsic::x86_3dnow_pfcmpgt:	case '0': // 1 string to match.
	case Intrinsic::x86_3dnow_pfmax:	return Intrinsic::hexagon_M2_mpyu_nac_hl_s0; // "__built
	case Intrinsic::x86_3dnow_pfmin:	in_HEXAGON.M2.mpyu.nac.hl.s0"
	case Intrinsic::x86_3dnow_pfmul:	case '1': // 1 string to match.
	case Intrinsic::x86_3dnow_pfrcp:	return Intrinsic::hexagon_M2_mpyu_nac_hl_s1; // "__built
	case Intrinsic::x86_3dnow_pfrcpit1:	in_HEXAGON.M2.mpyu.nac.hl.s1"
	case Intrinsic::x86_3dnow_pfrcpit2:	}
	case Intrinsic::x86_3dnow_pfrsqit1:	break;
	case Intrinsic::x86_3dnow_pfrsqrt:	}
	case Intrinsic::x86_3dnow_pfsub:	break;
	case Intrinsic::x86_3dnow_pfsubr:	case 'l': // 4 strings to match.
	case Intrinsic::x86_3dnow_pi2fd:	switch (BuiltinName[31]) {
	case Intrinsic::x86_3dnow_pmulhrw:	default: break;
	case Intrinsic::x86_3dnowa_pf2iw:	case 'h': // 2 strings to match.
	case Intrinsic::x86_3dnowa_pfnacc:	if (BuiltinName.substr(32, 2) != ".s")
	case Intrinsic::x86_3dnowa_pfpnacc:	break;
	case Intrinsic::x86_3dnowa_pi2fw:	switch (BuiltinName[34]) {
	case Intrinsic::x86_3dnowa_pswapd:	default: break;
	case Intrinsic::x86_aesni_aesdec:	case '0': // 1 string to match.
	case Intrinsic::x86_aesni_aesdeclast:	return Intrinsic::hexagon_M2_mpyu_nac_lh_s0; // "__built
	case Intrinsic::x86_aesni_aesenc:	in_HEXAGON.M2.mpyu.nac.lh.s0"
	case Intrinsic::x86_aesni_aesenclast:	case '1': // 1 string to match.
	case Intrinsic::x86_aesni_aesimc:	return Intrinsic::hexagon_M2_mpyu_nac_lh_s1; // "__built
	case Intrinsic::x86_aesni_aeskeygenassist:	in_HEXAGON.M2.mpyu.nac.lh.s1"
	case Intrinsic::x86_avx_addsub_pd_256:	}
	case Intrinsic::x86_avx_addsub_ps_256:	break;
	case Intrinsic::x86_avx_blend_pd_256:	case 'l': // 2 strings to match.
	case Intrinsic::x86_avx_blend_ps_256:	if (BuiltinName.substr(32, 2) != ".s")
	case Intrinsic::x86_avx_blendv_pd_256:	break;
	case Intrinsic::x86_avx_blendv_ps_256:	switch (BuiltinName[34]) {
	case Intrinsic::x86_avx_cmp_pd_256:	default: break;
	case Intrinsic::x86_avx_cmp_ps_256:	case '0': // 1 string to match.
	case Intrinsic::x86_avx_cvt_pd2_ps_256:	return Intrinsic::hexagon_M2_mpyu_nac_ll_s0; // "__built
	case Intrinsic::x86_avx_cvt_pd2dq_256:	in_HEXAGON.M2.mpyu.nac.ll.s0"
	case Intrinsic::x86_avx_cvt_ps2_pd_256:	case '1': // 1 string to match.
	case Intrinsic::x86_avx_cvt_ps2dq_256:	return Intrinsic::hexagon_M2_mpyu_nac_ll_s1; // "__built
	case Intrinsic::x86_avx_cvtdq2_pd_256:	in_HEXAGON.M2.mpyu.nac.ll.s1"
	case Intrinsic::x86_avx_cvtdq2_ps_256:	}
	case Intrinsic::x86_avx_cvtt_pd2dq_256:	break;
	case Intrinsic::x86_avx_cvtt_ps2dq_256:	}
	case Intrinsic::x86_avx_dp_ps_256:	break;
	case Intrinsic::x86_avx_hadd_pd_256:	}
	case Intrinsic::x86_avx_hadd_ps_256:	break;
	case Intrinsic::x86_avx_hsub_pd_256:	}
	case Intrinsic::x86_avx_hsub_ps_256:	break;
	case Intrinsic::x86_avx_max_pd_256:	}
	case Intrinsic::x86_avx_max_ps_256:	break;
	case Intrinsic::x86_avx_min_pd_256:	case 'v': // 7 strings to match.
	case Intrinsic::x86_avx_min_ps_256:	switch (BuiltinName[22]) {
	case Intrinsic::x86_avx_movmsk_pd_256:	default: break;
	case Intrinsic::x86_avx_movmsk_ps_256:	case 'c': // 6 strings to match.
	case Intrinsic::x86_avx_ptestc_256:	if (BuiltinName[23] != 'm')
	case Intrinsic::x86_avx_ptestnzc_256:	break;
	case Intrinsic::x86_avx_ptestz_256:	switch (BuiltinName[24]) {
	case Intrinsic::x86_avx_rcp_ps_256:	default: break;
	case Intrinsic::x86_avx_round_pd_256:	case 'a': // 2 strings to match.
	case Intrinsic::x86_avx_round_ps_256:	if (BuiltinName.substr(25, 9) != "c.s0.sat.")
	case Intrinsic::x86_avx_rsqrt_ps_256:	break;
	case Intrinsic::x86_avx_sqrt_pd_256:	switch (BuiltinName[34]) {
	case Intrinsic::x86_avx_sqrt_ps_256:	default: break;
	case Intrinsic::x86_avx_vextractf128_pd_256:	case 'i': // 1 string to match.
	case Intrinsic::x86_avx_vextractf128_ps_256:	return Intrinsic::hexagon_M2_vcmac_s0_sat_i; // "__built
	case Intrinsic::x86_avx_vextractf128_si_256:	in_HEXAGON.M2.vcmac.s0.sat.i"
	case Intrinsic::x86_avx_vinsertf128_pd_256:	case 'r': // 1 string to match.
	case Intrinsic::x86_avx_vinsertf128_ps_256:	return Intrinsic::hexagon_M2_vcmac_s0_sat_r; // "__built
	case Intrinsic::x86_avx_vinsertf128_si_256:	in_HEXAGON.M2.vcmac.s0.sat.r"
	case Intrinsic::x86_avx_vperm2f128_pd_256:	}
	case Intrinsic::x86_avx_vperm2f128_ps_256:	break;
	case Intrinsic::x86_avx_vperm2f128_si_256:	case 'p': // 4 strings to match.
	case Intrinsic::x86_avx_vpermil_pd:	if (BuiltinName.substr(25, 3) != "y.s")
	case Intrinsic::x86_avx_vpermil_pd_256:	break;
	case Intrinsic::x86_avx_vpermil_ps:	switch (BuiltinName[28]) {
	case Intrinsic::x86_avx_vpermil_ps_256:	default: break;
	case Intrinsic::x86_avx_vpermilvar_pd:	case '0': // 2 strings to match.
	case Intrinsic::x86_avx_vpermilvar_pd_256:	if (BuiltinName.substr(29, 5) != ".sat.")
	case Intrinsic::x86_avx_vpermilvar_ps:	break;
	case Intrinsic::x86_avx_vpermilvar_ps_256:	switch (BuiltinName[34]) {
	case Intrinsic::x86_avx_vtestc_pd:	default: break;
	case Intrinsic::x86_avx_vtestc_pd_256:	case 'i': // 1 string to match.
	case Intrinsic::x86_avx_vtestc_ps:	return Intrinsic::hexagon_M2_vcmpy_s0_sat_i; // "__built
	case Intrinsic::x86_avx_vtestc_ps_256:	in_HEXAGON.M2.vcmpy.s0.sat.i"
	case Intrinsic::x86_avx_vtestnzc_pd:	case 'r': // 1 string to match.
	case Intrinsic::x86_avx_vtestnzc_pd_256:	return Intrinsic::hexagon_M2_vcmpy_s0_sat_r; // "__built
	case Intrinsic::x86_avx_vtestnzc_ps:	in_HEXAGON.M2.vcmpy.s0.sat.r"
	case Intrinsic::x86_avx_vtestnzc_ps_256:	}
	case Intrinsic::x86_avx_vtestz_pd:	break;
	case Intrinsic::x86_avx_vtestz_pd_256:	case '1': // 2 strings to match.
	case Intrinsic::x86_avx_vtestz_ps:	if (BuiltinName.substr(29, 5) != ".sat.")
	case Intrinsic::x86_avx_vtestz_ps_256:	break;
	case Intrinsic::x86_mmx_packssdw:	switch (BuiltinName[34]) {
	case Intrinsic::x86_mmx_packsswb:	default: break;
	case Intrinsic::x86_mmx_packuswb:	case 'i': // 1 string to match.
	case Intrinsic::x86_mmx_padd_b:	return Intrinsic::hexagon_M2_vcmpy_s1_sat_i; // "__built
	case Intrinsic::x86_mmx_padd_d:	in_HEXAGON.M2.vcmpy.s1.sat.i"
	case Intrinsic::x86_mmx_padd_q:	case 'r': // 1 string to match.
	case Intrinsic::x86_mmx_padd_w:	return Intrinsic::hexagon_M2_vcmpy_s1_sat_r; // "__built
	case Intrinsic::x86_mmx_padds_b:	in_HEXAGON.M2.vcmpy.s1.sat.r"
	case Intrinsic::x86_mmx_padds_w:	}
	case Intrinsic::x86_mmx_paddus_b:	break;
	case Intrinsic::x86_mmx_paddus_w:	}
	case Intrinsic::x86_mmx_palignr_b:	break;
	case Intrinsic::x86_mmx_pand:	}
	case Intrinsic::x86_mmx_pandn:	break;
	case Intrinsic::x86_mmx_pavg_b:	case 'r': // 1 string to match.
	case Intrinsic::x86_mmx_pavg_w:	if (BuiltinName.substr(23, 12) != "cmpys.acc.s1")
	case Intrinsic::x86_mmx_pcmpeq_b:	break;
	case Intrinsic::x86_mmx_pcmpeq_d:	return Intrinsic::hexagon_M2_vrcmpys_acc_s1; // "__builtin_HEXAG
	case Intrinsic::x86_mmx_pcmpeq_w:	ON.M2.vrcmpys.acc.s1"
	case Intrinsic::x86_mmx_pcmpgt_b:	}
	case Intrinsic::x86_mmx_pcmpgt_d:	break;
	case Intrinsic::x86_mmx_pcmpgt_w:	}
	case Intrinsic::x86_mmx_pextr_w:	break;
	case Intrinsic::x86_mmx_pinsr_w:	case 'S': // 4 strings to match.
	case Intrinsic::x86_mmx_pmadd_wd:	if (BuiltinName.substr(19, 2) != "2.")
	case Intrinsic::x86_mmx_pmaxs_w:	break;
	case Intrinsic::x86_mmx_pmaxu_b:	switch (BuiltinName[21]) {
	case Intrinsic::x86_mmx_pmins_w:	default: break;
	case Intrinsic::x86_mmx_pminu_b:	case 'a': // 2 strings to match.
	case Intrinsic::x86_mmx_pmovmskb:	if (BuiltinName.substr(22, 3) != "sr.")
	case Intrinsic::x86_mmx_pmulh_w:	break;
	case Intrinsic::x86_mmx_pmulhu_w:	switch (BuiltinName[25]) {
	case Intrinsic::x86_mmx_pmull_w:	default: break;
	case Intrinsic::x86_mmx_pmulu_dq:	case 'i': // 1 string to match.
	case Intrinsic::x86_mmx_por:	if (BuiltinName.substr(26, 9) != ".svw.trun")
	case Intrinsic::x86_mmx_psad_bw:	break;
	case Intrinsic::x86_mmx_psll_d:	return Intrinsic::hexagon_S2_asr_i_svw_trun; // "__builtin_HEXAG
	case Intrinsic::x86_mmx_psll_q:	ON.S2.asr.i.svw.trun"
	case Intrinsic::x86_mmx_psll_w:	case 'r': // 1 string to match.
	case Intrinsic::x86_mmx_pslli_d:	if (BuiltinName.substr(26, 9) != ".svw.trun")
	case Intrinsic::x86_mmx_pslli_q:	break;
	case Intrinsic::x86_mmx_pslli_w:	return Intrinsic::hexagon_S2_asr_r_svw_trun; // "__builtin_HEXAG
	case Intrinsic::x86_mmx_psra_d:	ON.S2.asr.r.svw.trun"
	case Intrinsic::x86_mmx_psra_w:	}
	case Intrinsic::x86_mmx_psrai_d:	break;
	case Intrinsic::x86_mmx_psrai_w:	case 'v': // 2 strings to match.
	case Intrinsic::x86_mmx_psrl_d:	if (BuiltinName.substr(22, 3) != "sat")
	case Intrinsic::x86_mmx_psrl_q:	break;
	case Intrinsic::x86_mmx_psrl_w:	switch (BuiltinName[25]) {
	case Intrinsic::x86_mmx_psrli_d:	default: break;
	case Intrinsic::x86_mmx_psrli_q:	case 'h': // 1 string to match.
	case Intrinsic::x86_mmx_psrli_w:	if (BuiltinName.substr(26, 9) != "ub.nopack")
	case Intrinsic::x86_mmx_psub_b:	break;
	case Intrinsic::x86_mmx_psub_d:	return Intrinsic::hexagon_S2_vsathub_nopack; // "__builtin_HEXAG
	case Intrinsic::x86_mmx_psub_q:	ON.S2.vsathub.nopack"
	case Intrinsic::x86_mmx_psub_w:	case 'w': // 1 string to match.
	case Intrinsic::x86_mmx_psubs_b:	if (BuiltinName.substr(26, 9) != "uh.nopack")
	case Intrinsic::x86_mmx_psubs_w:	break;
	case Intrinsic::x86_mmx_psubus_b:	return Intrinsic::hexagon_S2_vsatwuh_nopack; // "__builtin_HEXAG
	case Intrinsic::x86_mmx_psubus_w:	ON.S2.vsatwuh.nopack"
	case Intrinsic::x86_mmx_punpckhbw:	}
	case Intrinsic::x86_mmx_punpckhdq:	break;
	case Intrinsic::x86_mmx_punpckhwd:	}
	case Intrinsic::x86_mmx_punpcklbw:	break;
	case Intrinsic::x86_mmx_punpckldq:	}
	case Intrinsic::x86_mmx_punpcklwd:
	case Intrinsic::x86_mmx_pxor:
	case Intrinsic::x86_sse2_add_sd:
	case Intrinsic::x86_sse2_cmp_pd:
	case Intrinsic::x86_sse2_cmp_sd:
	case Intrinsic::x86_sse2_comieq_sd:
	case Intrinsic::x86_sse2_comige_sd:
	case Intrinsic::x86_sse2_comigt_sd:
	case Intrinsic::x86_sse2_comile_sd:
	case Intrinsic::x86_sse2_comilt_sd:
	case Intrinsic::x86_sse2_comineq_sd:
	case Intrinsic::x86_sse2_cvtdq2pd:
	case Intrinsic::x86_sse2_cvtdq2ps:
	case Intrinsic::x86_sse2_cvtpd2dq:
	case Intrinsic::x86_sse2_cvtpd2ps:
	case Intrinsic::x86_sse2_cvtps2dq:
	case Intrinsic::x86_sse2_cvtps2pd:
	case Intrinsic::x86_sse2_cvtsd2si:
	case Intrinsic::x86_sse2_cvtsd2si64:
	case Intrinsic::x86_sse2_cvtsd2ss:
	case Intrinsic::x86_sse2_cvtsi2sd:
	case Intrinsic::x86_sse2_cvtsi642sd:
	case Intrinsic::x86_sse2_cvtss2sd:
	case Intrinsic::x86_sse2_cvttpd2dq:
	case Intrinsic::x86_sse2_cvttps2dq:
	case Intrinsic::x86_sse2_cvttsd2si:
	case Intrinsic::x86_sse2_cvttsd2si64:
	case Intrinsic::x86_sse2_div_sd:
	case Intrinsic::x86_sse2_max_pd:
	case Intrinsic::x86_sse2_max_sd:
	case Intrinsic::x86_sse2_min_pd:
	case Intrinsic::x86_sse2_min_sd:
	case Intrinsic::x86_sse2_movmsk_pd:
	case Intrinsic::x86_sse2_mul_sd:
	case Intrinsic::x86_sse2_packssdw_128:
	case Intrinsic::x86_sse2_packsswb_128:
	case Intrinsic::x86_sse2_packuswb_128:
	case Intrinsic::x86_sse2_padds_b:
	case Intrinsic::x86_sse2_padds_w:
	case Intrinsic::x86_sse2_paddus_b:
	case Intrinsic::x86_sse2_paddus_w:
	case Intrinsic::x86_sse2_pavg_b:
	case Intrinsic::x86_sse2_pavg_w:
	case Intrinsic::x86_sse2_pcmpeq_b:
	case Intrinsic::x86_sse2_pcmpeq_d:
	case Intrinsic::x86_sse2_pcmpeq_w:
	case Intrinsic::x86_sse2_pcmpgt_b:
	case Intrinsic::x86_sse2_pcmpgt_d:
	case Intrinsic::x86_sse2_pcmpgt_w:
	case Intrinsic::x86_sse2_pmadd_wd:
	case Intrinsic::x86_sse2_pmaxs_w:
	case Intrinsic::x86_sse2_pmaxu_b:
	case Intrinsic::x86_sse2_pmins_w:
	case Intrinsic::x86_sse2_pminu_b:
	case Intrinsic::x86_sse2_pmovmskb_128:
	case Intrinsic::x86_sse2_pmulh_w:
	case Intrinsic::x86_sse2_pmulhu_w:
	case Intrinsic::x86_sse2_pmulu_dq:
	case Intrinsic::x86_sse2_psad_bw:
	case Intrinsic::x86_sse2_psll_d:
	case Intrinsic::x86_sse2_psll_dq:
	case Intrinsic::x86_sse2_psll_dq_bs:
	case Intrinsic::x86_sse2_psll_q:
	case Intrinsic::x86_sse2_psll_w:
	case Intrinsic::x86_sse2_pslli_d:
	case Intrinsic::x86_sse2_pslli_q:
	case Intrinsic::x86_sse2_pslli_w:
	case Intrinsic::x86_sse2_psra_d:
	case Intrinsic::x86_sse2_psra_w:
	case Intrinsic::x86_sse2_psrai_d:
	case Intrinsic::x86_sse2_psrai_w:
	case Intrinsic::x86_sse2_psrl_d:
	case Intrinsic::x86_sse2_psrl_dq:
	case Intrinsic::x86_sse2_psrl_dq_bs:
	case Intrinsic::x86_sse2_psrl_q:
	case Intrinsic::x86_sse2_psrl_w:
	case Intrinsic::x86_sse2_psrli_d:
	case Intrinsic::x86_sse2_psrli_q:
	case Intrinsic::x86_sse2_psrli_w:
	case Intrinsic::x86_sse2_psubs_b:
	case Intrinsic::x86_sse2_psubs_w:
	case Intrinsic::x86_sse2_psubus_b:
	case Intrinsic::x86_sse2_psubus_w:
	case Intrinsic::x86_sse2_sqrt_pd:
	case Intrinsic::x86_sse2_sqrt_sd:
	case Intrinsic::x86_sse2_sub_sd:
	case Intrinsic::x86_sse2_ucomieq_sd:
	case Intrinsic::x86_sse2_ucomige_sd:
	case Intrinsic::x86_sse2_ucomigt_sd:
	case Intrinsic::x86_sse2_ucomile_sd:
	case Intrinsic::x86_sse2_ucomilt_sd:
	case Intrinsic::x86_sse2_ucomineq_sd:
	case Intrinsic::x86_sse3_addsub_pd:
	case Intrinsic::x86_sse3_addsub_ps:
	case Intrinsic::x86_sse3_hadd_pd:
	case Intrinsic::x86_sse3_hadd_ps:
	case Intrinsic::x86_sse3_hsub_pd:
	case Intrinsic::x86_sse3_hsub_ps:
	case Intrinsic::x86_sse41_blendpd:
	case Intrinsic::x86_sse41_blendps:
	case Intrinsic::x86_sse41_blendvpd:
	case Intrinsic::x86_sse41_blendvps:
	case Intrinsic::x86_sse41_dppd:
	case Intrinsic::x86_sse41_dpps:
	case Intrinsic::x86_sse41_extractps:
	case Intrinsic::x86_sse41_insertps:
	case Intrinsic::x86_sse41_mpsadbw:
	case Intrinsic::x86_sse41_packusdw:
	case Intrinsic::x86_sse41_pblendvb:
	case Intrinsic::x86_sse41_pblendw:
	case Intrinsic::x86_sse41_pcmpeqq:
	case Intrinsic::x86_sse41_pextrb:
	case Intrinsic::x86_sse41_pextrd:
	case Intrinsic::x86_sse41_pextrq:
	case Intrinsic::x86_sse41_phminposuw:
	case Intrinsic::x86_sse41_pmaxsb:
	case Intrinsic::x86_sse41_pmaxsd:
	case Intrinsic::x86_sse41_pmaxud:
	case Intrinsic::x86_sse41_pmaxuw:
	case Intrinsic::x86_sse41_pminsb:
	case Intrinsic::x86_sse41_pminsd:
	case Intrinsic::x86_sse41_pminud:
	case Intrinsic::x86_sse41_pminuw:
	case Intrinsic::x86_sse41_pmovsxbd:
	case Intrinsic::x86_sse41_pmovsxbq:
	case Intrinsic::x86_sse41_pmovsxbw:
	case Intrinsic::x86_sse41_pmovsxdq:
	case Intrinsic::x86_sse41_pmovsxwd:
	case Intrinsic::x86_sse41_pmovsxwq:
	case Intrinsic::x86_sse41_pmovzxbd:
	case Intrinsic::x86_sse41_pmovzxbq:
	case Intrinsic::x86_sse41_pmovzxbw:
	case Intrinsic::x86_sse41_pmovzxdq:
	case Intrinsic::x86_sse41_pmovzxwd:
	case Intrinsic::x86_sse41_pmovzxwq:
	case Intrinsic::x86_sse41_pmuldq:
	case Intrinsic::x86_sse41_ptestc:
	case Intrinsic::x86_sse41_ptestnzc:
	case Intrinsic::x86_sse41_ptestz:
	case Intrinsic::x86_sse41_round_pd:
	case Intrinsic::x86_sse41_round_ps:
	case Intrinsic::x86_sse41_round_sd:
	case Intrinsic::x86_sse41_round_ss:
	case Intrinsic::x86_sse42_crc32_32_16:
	case Intrinsic::x86_sse42_crc32_32_32:
	case Intrinsic::x86_sse42_crc32_32_8:
	case Intrinsic::x86_sse42_crc32_64_64:
	case Intrinsic::x86_sse42_crc32_64_8:
	case Intrinsic::x86_sse42_pcmpestri128:
	case Intrinsic::x86_sse42_pcmpestria128:
	case Intrinsic::x86_sse42_pcmpestric128:
	case Intrinsic::x86_sse42_pcmpestrio128:
	case Intrinsic::x86_sse42_pcmpestris128:
	case Intrinsic::x86_sse42_pcmpestriz128:
	case Intrinsic::x86_sse42_pcmpestrm128:
	case Intrinsic::x86_sse42_pcmpgtq:
	case Intrinsic::x86_sse42_pcmpistri128:
	case Intrinsic::x86_sse42_pcmpistria128:
	case Intrinsic::x86_sse42_pcmpistric128:
	case Intrinsic::x86_sse42_pcmpistrio128:
	case Intrinsic::x86_sse42_pcmpistris128:
	case Intrinsic::x86_sse42_pcmpistriz128:
	case Intrinsic::x86_sse42_pcmpistrm128:
	case Intrinsic::x86_sse_add_ss:
	case Intrinsic::x86_sse_cmp_ps:
	case Intrinsic::x86_sse_cmp_ss:
	case Intrinsic::x86_sse_comieq_ss:
	case Intrinsic::x86_sse_comige_ss:
	case Intrinsic::x86_sse_comigt_ss:
	case Intrinsic::x86_sse_comile_ss:
	case Intrinsic::x86_sse_comilt_ss:
	case Intrinsic::x86_sse_comineq_ss:
	case Intrinsic::x86_sse_cvtpd2pi:
	case Intrinsic::x86_sse_cvtpi2pd:
	case Intrinsic::x86_sse_cvtpi2ps:
	case Intrinsic::x86_sse_cvtps2pi:
	case Intrinsic::x86_sse_cvtsi2ss:
	case Intrinsic::x86_sse_cvtsi642ss:
	case Intrinsic::x86_sse_cvtss2si:
	case Intrinsic::x86_sse_cvtss2si64:
	case Intrinsic::x86_sse_cvttpd2pi:
	case Intrinsic::x86_sse_cvttps2pi:
	case Intrinsic::x86_sse_cvttss2si:
	case Intrinsic::x86_sse_cvttss2si64:
	case Intrinsic::x86_sse_div_ss:
	case Intrinsic::x86_sse_max_ps:
	case Intrinsic::x86_sse_max_ss:
	case Intrinsic::x86_sse_min_ps:
	case Intrinsic::x86_sse_min_ss:
	case Intrinsic::x86_sse_movmsk_ps:
	case Intrinsic::x86_sse_mul_ss:
	case Intrinsic::x86_sse_pshuf_w:
	case Intrinsic::x86_sse_rcp_ps:
	case Intrinsic::x86_sse_rcp_ss:
	case Intrinsic::x86_sse_rsqrt_ps:
	case Intrinsic::x86_sse_rsqrt_ss:
	case Intrinsic::x86_sse_sqrt_ps:
	case Intrinsic::x86_sse_sqrt_ss:
	case Intrinsic::x86_sse_sub_ss:
	case Intrinsic::x86_sse_ucomieq_ss:
	case Intrinsic::x86_sse_ucomige_ss:
	case Intrinsic::x86_sse_ucomigt_ss:
	case Intrinsic::x86_sse_ucomile_ss:
	case Intrinsic::x86_sse_ucomilt_ss:
	case Intrinsic::x86_sse_ucomineq_ss:
	case Intrinsic::x86_ssse3_pabs_b:
	case Intrinsic::x86_ssse3_pabs_b_128:
	case Intrinsic::x86_ssse3_pabs_d:
	case Intrinsic::x86_ssse3_pabs_d_128:
	case Intrinsic::x86_ssse3_pabs_w:
	case Intrinsic::x86_ssse3_pabs_w_128:
	case Intrinsic::x86_ssse3_phadd_d:
	case Intrinsic::x86_ssse3_phadd_d_128:
	case Intrinsic::x86_ssse3_phadd_sw:
	case Intrinsic::x86_ssse3_phadd_sw_128:
	case Intrinsic::x86_ssse3_phadd_w:
	case Intrinsic::x86_ssse3_phadd_w_128:
	case Intrinsic::x86_ssse3_phsub_d:
	case Intrinsic::x86_ssse3_phsub_d_128:
	case Intrinsic::x86_ssse3_phsub_sw:
	case Intrinsic::x86_ssse3_phsub_sw_128:
	case Intrinsic::x86_ssse3_phsub_w:
	case Intrinsic::x86_ssse3_phsub_w_128:
	case Intrinsic::x86_ssse3_pmadd_ub_sw:
	case Intrinsic::x86_ssse3_pmadd_ub_sw_128:
	case Intrinsic::x86_ssse3_pmul_hr_sw:
	case Intrinsic::x86_ssse3_pmul_hr_sw_128:
	case Intrinsic::x86_ssse3_pshuf_b:
	case Intrinsic::x86_ssse3_pshuf_b_128:
	case Intrinsic::x86_ssse3_psign_b:
	case Intrinsic::x86_ssse3_psign_b_128:
	case Intrinsic::x86_ssse3_psign_d:
	case Intrinsic::x86_ssse3_psign_d_128:
	case Intrinsic::x86_ssse3_psign_w:
	case Intrinsic::x86_ssse3_psign_w_128:
	case Intrinsic::xcore_bitrev:
	case Intrinsic::xcore_crc32:
	case Intrinsic::xcore_crc8:
	case Intrinsic::xcore_getid:
	case Intrinsic::xcore_sext:
	case Intrinsic::xcore_zext:
	AWI[0] = AttributeWithIndex::get(~0, Attribute::NoUnwind\|Attribute::Rea
	dNone);
	NumAttrs = 1;
	break;
	case Intrinsic::adjust_trampoline:
	case Intrinsic::arm_ldrexd:
	case Intrinsic::arm_neon_vld1:
	case Intrinsic::arm_neon_vld2:
	case Intrinsic::arm_neon_vld2lane:
	case Intrinsic::arm_neon_vld3:
	case Intrinsic::arm_neon_vld3lane:
	case Intrinsic::arm_neon_vld4:
	case Intrinsic::arm_neon_vld4lane:
	case Intrinsic::cos:
	case Intrinsic::eh_exception:
	case Intrinsic::exp:
	case Intrinsic::exp2:
	case Intrinsic::gcread:
	case Intrinsic::log:
	case Intrinsic::log10:
	case Intrinsic::log2:
	case Intrinsic::pow:
	case Intrinsic::powi:
	case Intrinsic::ppc_altivec_lvebx:
	case Intrinsic::ppc_altivec_lvehx:
	case Intrinsic::ppc_altivec_lvewx:
	case Intrinsic::ppc_altivec_lvx:
	case Intrinsic::ppc_altivec_lvxl:
	case Intrinsic::ppc_altivec_mfvscr:
	case Intrinsic::sin:
	case Intrinsic::sqrt:
	case Intrinsic::x86_avx_ldu_dq_256:
	case Intrinsic::x86_avx_loadu_dq_256:
	case Intrinsic::x86_avx_loadu_pd_256:
	case Intrinsic::x86_avx_loadu_ps_256:
	case Intrinsic::x86_avx_maskload_pd:
	case Intrinsic::x86_avx_maskload_pd_256:
	case Intrinsic::x86_avx_maskload_ps:
	case Intrinsic::x86_avx_maskload_ps_256:
	case Intrinsic::x86_avx_vbroadcast_sd_256:
	case Intrinsic::x86_avx_vbroadcastf128_pd_256:
	case Intrinsic::x86_avx_vbroadcastf128_ps_256:
	case Intrinsic::x86_avx_vbroadcastss:
	case Intrinsic::x86_avx_vbroadcastss_256:
	case Intrinsic::x86_sse3_ldu_dq:
	case Intrinsic::x86_sse41_movntdqa:
	case Intrinsic::xcore_waitevent:
	AWI[0] = AttributeWithIndex::get(~0, Attribute::NoUnwind\|Attribute::Rea
	dOnly);
	NumAttrs = 1;
	break;
	case Intrinsic::annotation:
	case Intrinsic::arm_cdp:
	case Intrinsic::arm_cdp2:
	case Intrinsic::arm_mcr:
	case Intrinsic::arm_mcr2:
	case Intrinsic::arm_mcrr:
	case Intrinsic::arm_mcrr2:
	case Intrinsic::arm_mrc:
	case Intrinsic::arm_mrc2:
	case Intrinsic::arm_neon_vst1:
	case Intrinsic::arm_neon_vst2:
	case Intrinsic::arm_neon_vst2lane:
	case Intrinsic::arm_neon_vst3:
	case Intrinsic::arm_neon_vst3lane:
	case Intrinsic::arm_neon_vst4:
	case Intrinsic::arm_neon_vst4lane:
	case Intrinsic::arm_set_fpscr:
	case Intrinsic::arm_strexd:
	case Intrinsic::convertff:
	case Intrinsic::convertfsi:
	case Intrinsic::convertfui:
	case Intrinsic::convertsif:
	case Intrinsic::convertss:
	case Intrinsic::convertsu:
	case Intrinsic::convertuif:
	case Intrinsic::convertus:
	case Intrinsic::convertuu:
	case Intrinsic::eh_dwarf_cfa:
	case Intrinsic::eh_return_i32:
	case Intrinsic::eh_return_i64:
	case Intrinsic::eh_selector:
	case Intrinsic::eh_sjlj_dispatch_setup:
	case Intrinsic::eh_sjlj_functioncontext:
	case Intrinsic::eh_sjlj_longjmp:
	case Intrinsic::eh_sjlj_setjmp:
	case Intrinsic::eh_unwind_init:
	case Intrinsic::flt_rounds:
	case Intrinsic::gcroot:
	case Intrinsic::longjmp:
	case Intrinsic::pcmarker:
	case Intrinsic::ppc_altivec_dss:
	case Intrinsic::ppc_altivec_dssall:
	case Intrinsic::ppc_altivec_dst:
	case Intrinsic::ppc_altivec_dstst:
	case Intrinsic::ppc_altivec_dststt:
	case Intrinsic::ppc_altivec_dstt:
	case Intrinsic::ppc_altivec_mtvscr:
	case Intrinsic::ppc_altivec_stvebx:
	case Intrinsic::ppc_altivec_stvehx:
	case Intrinsic::ppc_altivec_stvewx:
	case Intrinsic::ppc_altivec_stvx:
	case Intrinsic::ppc_altivec_stvxl:
	case Intrinsic::ppc_dcba:
	case Intrinsic::ppc_dcbf:
	case Intrinsic::ppc_dcbi:
	case Intrinsic::ppc_dcbst:
	case Intrinsic::ppc_dcbt:
	case Intrinsic::ppc_dcbtst:
	case Intrinsic::ppc_dcbz:
	case Intrinsic::ppc_dcbzl:
	case Intrinsic::ppc_sync:
	case Intrinsic::ptr_annotation:
	case Intrinsic::ptx_bar_sync:
	case Intrinsic::readcyclecounter:
	case Intrinsic::setjmp:
	case Intrinsic::siglongjmp:
	case Intrinsic::sigsetjmp:
	case Intrinsic::stackprotector:
	case Intrinsic::stackrestore:
	case Intrinsic::stacksave:
	case Intrinsic::trap:
	case Intrinsic::vacopy:
	case Intrinsic::vaend:
	case Intrinsic::var_annotation:
	case Intrinsic::vastart:
	case Intrinsic::x86_avx_maskstore_pd:
	case Intrinsic::x86_avx_maskstore_pd_256:
	case Intrinsic::x86_avx_maskstore_ps:
	case Intrinsic::x86_avx_maskstore_ps_256:
	case Intrinsic::x86_avx_movnt_dq_256:
	case Intrinsic::x86_avx_movnt_pd_256:
	case Intrinsic::x86_avx_movnt_ps_256:
	case Intrinsic::x86_avx_storeu_dq_256:
	case Intrinsic::x86_avx_storeu_pd_256:
	case Intrinsic::x86_avx_storeu_ps_256:
	case Intrinsic::x86_avx_vzeroall:
	case Intrinsic::x86_avx_vzeroupper:
	case Intrinsic::x86_int:
	case Intrinsic::x86_mmx_emms:
	case Intrinsic::x86_mmx_femms:
	case Intrinsic::x86_mmx_maskmovq:
	case Intrinsic::x86_mmx_movnt_dq:
	case Intrinsic::x86_sse2_clflush:
	case Intrinsic::x86_sse2_lfence:
	case Intrinsic::x86_sse2_maskmov_dqu:
	case Intrinsic::x86_sse2_mfence:
	case Intrinsic::x86_sse2_storel_dq:
	case Intrinsic::x86_sse2_storeu_dq:
	case Intrinsic::x86_sse2_storeu_pd:
	case Intrinsic::x86_sse3_monitor:
	case Intrinsic::x86_sse3_mwait:
	case Intrinsic::x86_sse_ldmxcsr:
	case Intrinsic::x86_sse_sfence:
	case Intrinsic::x86_sse_stmxcsr:
	case Intrinsic::x86_sse_storeu_ps:
	case Intrinsic::xcore_checkevent:
	case Intrinsic::xcore_clre:
	case Intrinsic::xcore_clrsr:
	case Intrinsic::xcore_geted:
	case Intrinsic::xcore_getet:
	case Intrinsic::xcore_getps:
	case Intrinsic::xcore_getr:
	case Intrinsic::xcore_setps:
	case Intrinsic::xcore_setsr:
	case Intrinsic::xcore_ssync:
	AWI[0] = AttributeWithIndex::get(~0, Attribute::NoUnwind);
	NumAttrs = 1;
	break;
	case Intrinsic::init_trampoline:
	case Intrinsic::memset:
	case Intrinsic::prefetch:
	case Intrinsic::xcore_chkct:
	case Intrinsic::xcore_eeu:
	case Intrinsic::xcore_endin:
	case Intrinsic::xcore_freer:
	case Intrinsic::xcore_getst:
	case Intrinsic::xcore_getts:
	case Intrinsic::xcore_in:
	case Intrinsic::xcore_inct:
	case Intrinsic::xcore_initcp:
	case Intrinsic::xcore_initdp:
	case Intrinsic::xcore_initlr:
	case Intrinsic::xcore_initpc:
	case Intrinsic::xcore_initsp:
	case Intrinsic::xcore_inshr:
	case Intrinsic::xcore_int:
	case Intrinsic::xcore_mjoin:
	case Intrinsic::xcore_msync:
	case Intrinsic::xcore_out:
	case Intrinsic::xcore_outct:
	case Intrinsic::xcore_outshr:
	case Intrinsic::xcore_outt:
	case Intrinsic::xcore_peek:
	case Intrinsic::xcore_setc:
	case Intrinsic::xcore_setd:
	case Intrinsic::xcore_setev:
	case Intrinsic::xcore_setpsc:
	case Intrinsic::xcore_setpt:
	case Intrinsic::xcore_settw:
	case Intrinsic::xcore_setv:
	case Intrinsic::xcore_syncr:
	case Intrinsic::xcore_testct:
	case Intrinsic::xcore_testwct:
	AWI[0] = AttributeWithIndex::get(1, Attribute::NoCapture);
	AWI[1] = AttributeWithIndex::get(~0, Attribute::NoUnwind);
	NumAttrs = 2;
	break;
	case Intrinsic::memcpy:
	case Intrinsic::memmove:
	case Intrinsic::xcore_setclk:
	case Intrinsic::xcore_setrdy:
	AWI[0] = AttributeWithIndex::get(1, Attribute::NoCapture);
	AWI[1] = AttributeWithIndex::get(2, Attribute::NoCapture);
	AWI[2] = AttributeWithIndex::get(~0, Attribute::NoUnwind);
	NumAttrs = 3;
	break;
	case Intrinsic::invariant_start:
	case Intrinsic::lifetime_end:
	case Intrinsic::lifetime_start:
	AWI[0] = AttributeWithIndex::get(2, Attribute::NoCapture);
	AWI[1] = AttributeWithIndex::get(~0, Attribute::NoUnwind);
	NumAttrs = 2;
	break;
	case Intrinsic::gcwrite:
	AWI[0] = AttributeWithIndex::get(2, Attribute::NoCapture);
	AWI[1] = AttributeWithIndex::get(3, Attribute::NoCapture);
	AWI[2] = AttributeWithIndex::get(~0, Attribute::NoUnwind);
	NumAttrs = 3;
	break;
	case Intrinsic::invariant_end:
	AWI[0] = AttributeWithIndex::get(3, Attribute::NoCapture);
	AWI[1] = AttributeWithIndex::get(~0, Attribute::NoUnwind);
	NumAttrs = 2;
	break;	break;

	case Intrinsic::eh_resume:	case 36: // 31 strings to match.
	return AttrListPtr();	if (BuiltinName.substr(0, 18) != "__builtin_HEXAGON.")
	}
	return AttrListPtr::get(AWI, NumAttrs);
	}
	#endif // GET_INTRINSIC_ATTRIBUTES

	// Determine intrinsic alias analysis mod/ref behavior.
	#ifdef GET_INTRINSIC_MODREF_BEHAVIOR
	switch (iid) {
	default:
	return UnknownModRefBehavior;
	case Intrinsic::adjust_trampoline:
	return OnlyReadsArgumentPointees;
	case Intrinsic::alpha_umulh:
	return DoesNotAccessMemory;
	case Intrinsic::arm_get_fpscr:
	return DoesNotAccessMemory;
	case Intrinsic::arm_ldrexd:
	return OnlyReadsArgumentPointees;
	case Intrinsic::arm_neon_vabds:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vabdu:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vabs:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vacged:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vacgeq:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vacgtd:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vacgtq:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vaddhn:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vcls:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vclz:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vcnt:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vcvtfp2fxs:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vcvtfp2fxu:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vcvtfp2hf:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vcvtfxs2fp:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vcvtfxu2fp:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vcvthf2fp:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vhadds:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vhaddu:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vhsubs:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vhsubu:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vld1:
	return OnlyReadsArgumentPointees;
	case Intrinsic::arm_neon_vld2:
	return OnlyReadsArgumentPointees;
	case Intrinsic::arm_neon_vld2lane:
	return OnlyReadsArgumentPointees;
	case Intrinsic::arm_neon_vld3:
	return OnlyReadsArgumentPointees;
	case Intrinsic::arm_neon_vld3lane:
	return OnlyReadsArgumentPointees;
	case Intrinsic::arm_neon_vld4:
	return OnlyReadsArgumentPointees;
	case Intrinsic::arm_neon_vld4lane:
	return OnlyReadsArgumentPointees;
	case Intrinsic::arm_neon_vmaxs:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vmaxu:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vmins:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vminu:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vmullp:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vmulls:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vmullu:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vmulp:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vpadals:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vpadalu:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vpadd:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vpaddls:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vpaddlu:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vpmaxs:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vpmaxu:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vpmins:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vpminu:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vqabs:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vqadds:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vqaddu:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vqdmlal:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vqdmlsl:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vqdmulh:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vqdmull:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vqmovns:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vqmovnsu:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vqmovnu:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vqneg:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vqrdmulh:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vqrshiftns:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vqrshiftnsu:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vqrshiftnu:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vqrshifts:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vqrshiftu:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vqshiftns:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vqshiftnsu:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vqshiftnu:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vqshifts:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vqshiftsu:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vqshiftu:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vqsubs:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vqsubu:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vraddhn:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vrecpe:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vrecps:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vrhadds:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vrhaddu:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vrshiftn:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vrshifts:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vrshiftu:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vrsqrte:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vrsqrts:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vrsubhn:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vshiftins:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vshiftls:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vshiftlu:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vshiftn:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vshifts:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vshiftu:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vst1:
	return OnlyAccessesArgumentPointees;
	case Intrinsic::arm_neon_vst2:
	return OnlyAccessesArgumentPointees;
	case Intrinsic::arm_neon_vst2lane:
	return OnlyAccessesArgumentPointees;
	case Intrinsic::arm_neon_vst3:
	return OnlyAccessesArgumentPointees;
	case Intrinsic::arm_neon_vst3lane:
	return OnlyAccessesArgumentPointees;
	case Intrinsic::arm_neon_vst4:
	return OnlyAccessesArgumentPointees;
	case Intrinsic::arm_neon_vst4lane:
	return OnlyAccessesArgumentPointees;
	case Intrinsic::arm_neon_vsubhn:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vtbl1:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vtbl2:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vtbl3:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vtbl4:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vtbx1:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vtbx2:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vtbx3:
	return DoesNotAccessMemory;
	case Intrinsic::arm_neon_vtbx4:
	return DoesNotAccessMemory;
	case Intrinsic::arm_qadd:
	return DoesNotAccessMemory;
	case Intrinsic::arm_qsub:
	return DoesNotAccessMemory;
	case Intrinsic::arm_ssat:
	return DoesNotAccessMemory;
	case Intrinsic::arm_strexd:
	return OnlyAccessesArgumentPointees;
	case Intrinsic::arm_thread_pointer:
	return DoesNotAccessMemory;
	case Intrinsic::arm_usat:
	return DoesNotAccessMemory;
	case Intrinsic::arm_vcvtr:
	return DoesNotAccessMemory;
	case Intrinsic::arm_vcvtru:
	return DoesNotAccessMemory;
	case Intrinsic::bswap:
	return DoesNotAccessMemory;
	case Intrinsic::convert_from_fp16:
	return DoesNotAccessMemory;
	case Intrinsic::convert_to_fp16:
	return DoesNotAccessMemory;
	case Intrinsic::cos:
	return OnlyReadsMemory;
	case Intrinsic::ctlz:
	return DoesNotAccessMemory;
	case Intrinsic::ctpop:
	return DoesNotAccessMemory;
	case Intrinsic::cttz:
	return DoesNotAccessMemory;
	case Intrinsic::dbg_declare:
	return DoesNotAccessMemory;
	case Intrinsic::dbg_value:
	return DoesNotAccessMemory;
	case Intrinsic::eh_exception:
	return OnlyReadsMemory;
	case Intrinsic::eh_sjlj_callsite:
	return DoesNotAccessMemory;
	case Intrinsic::eh_sjlj_lsda:
	return DoesNotAccessMemory;
	case Intrinsic::eh_typeid_for:
	return DoesNotAccessMemory;
	case Intrinsic::exp:
	return OnlyReadsMemory;
	case Intrinsic::exp2:
	return OnlyReadsMemory;
	case Intrinsic::expect:
	return DoesNotAccessMemory;
	case Intrinsic::fma:
	return DoesNotAccessMemory;
	case Intrinsic::frameaddress:
	return DoesNotAccessMemory;
	case Intrinsic::gcread:
	return OnlyReadsArgumentPointees;
	case Intrinsic::gcwrite:
	return OnlyAccessesArgumentPointees;
	case Intrinsic::init_trampoline:
	return OnlyAccessesArgumentPointees;
	case Intrinsic::invariant_end:
	return OnlyAccessesArgumentPointees;
	case Intrinsic::invariant_start:
	return OnlyAccessesArgumentPointees;
	case Intrinsic::lifetime_end:
	return OnlyAccessesArgumentPointees;
	case Intrinsic::lifetime_start:
	return OnlyAccessesArgumentPointees;
	case Intrinsic::log:
	return OnlyReadsMemory;
	case Intrinsic::log10:
	return OnlyReadsMemory;
	case Intrinsic::log2:
	return OnlyReadsMemory;
	case Intrinsic::memcpy:
	return OnlyAccessesArgumentPointees;
	case Intrinsic::memmove:
	return OnlyAccessesArgumentPointees;
	case Intrinsic::memset:
	return OnlyAccessesArgumentPointees;
	case Intrinsic::objectsize:
	return DoesNotAccessMemory;
	case Intrinsic::pow:
	return OnlyReadsMemory;
	case Intrinsic::powi:
	return OnlyReadsMemory;
	case Intrinsic::ppc_altivec_lvebx:
	return OnlyReadsMemory;
	case Intrinsic::ppc_altivec_lvehx:
	return OnlyReadsMemory;
	case Intrinsic::ppc_altivec_lvewx:
	return OnlyReadsMemory;
	case Intrinsic::ppc_altivec_lvsl:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_lvsr:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_lvx:
	return OnlyReadsMemory;
	case Intrinsic::ppc_altivec_lvxl:
	return OnlyReadsMemory;
	case Intrinsic::ppc_altivec_mfvscr:
	return OnlyReadsMemory;
	case Intrinsic::ppc_altivec_vaddcuw:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vaddsbs:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vaddshs:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vaddsws:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vaddubs:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vadduhs:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vadduws:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vavgsb:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vavgsh:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vavgsw:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vavgub:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vavguh:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vavguw:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vcfsx:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vcfux:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vcmpbfp:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vcmpbfp_p:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vcmpeqfp:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vcmpeqfp_p:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vcmpequb:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vcmpequb_p:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vcmpequh:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vcmpequh_p:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vcmpequw:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vcmpequw_p:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vcmpgefp:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vcmpgefp_p:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vcmpgtfp:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vcmpgtfp_p:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vcmpgtsb:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vcmpgtsb_p:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vcmpgtsh:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vcmpgtsh_p:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vcmpgtsw:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vcmpgtsw_p:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vcmpgtub:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vcmpgtub_p:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vcmpgtuh:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vcmpgtuh_p:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vcmpgtuw:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vcmpgtuw_p:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vctsxs:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vctuxs:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vexptefp:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vlogefp:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vmaddfp:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vmaxfp:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vmaxsb:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vmaxsh:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vmaxsw:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vmaxub:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vmaxuh:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vmaxuw:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vmhaddshs:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vmhraddshs:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vminfp:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vminsb:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vminsh:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vminsw:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vminub:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vminuh:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vminuw:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vmladduhm:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vmsummbm:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vmsumshm:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vmsumshs:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vmsumubm:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vmsumuhm:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vmsumuhs:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vmulesb:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vmulesh:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vmuleub:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vmuleuh:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vmulosb:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vmulosh:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vmuloub:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vmulouh:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vnmsubfp:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vperm:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vpkpx:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vpkshss:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vpkshus:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vpkswss:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vpkswus:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vpkuhus:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vpkuwus:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vrefp:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vrfim:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vrfin:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vrfip:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vrfiz:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vrlb:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vrlh:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vrlw:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vrsqrtefp:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vsel:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vsl:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vslb:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vslh:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vslo:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vslw:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vsr:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vsrab:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vsrah:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vsraw:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vsrb:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vsrh:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vsro:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vsrw:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vsubcuw:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vsubsbs:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vsubshs:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vsubsws:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vsububs:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vsubuhs:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vsubuws:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vsum2sws:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vsum4sbs:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vsum4shs:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vsum4ubs:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vsumsws:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vupkhpx:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vupkhsb:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vupkhsh:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vupklpx:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vupklsb:
	return DoesNotAccessMemory;
	case Intrinsic::ppc_altivec_vupklsh:
	return DoesNotAccessMemory;
	case Intrinsic::prefetch:
	return OnlyAccessesArgumentPointees;
	case Intrinsic::ptx_read_clock:
	return DoesNotAccessMemory;
	case Intrinsic::ptx_read_clock64:
	return DoesNotAccessMemory;
	case Intrinsic::ptx_read_ctaid_w:
	return DoesNotAccessMemory;
	case Intrinsic::ptx_read_ctaid_x:
	return DoesNotAccessMemory;
	case Intrinsic::ptx_read_ctaid_y:
	return DoesNotAccessMemory;
	case Intrinsic::ptx_read_ctaid_z:
	return DoesNotAccessMemory;
	case Intrinsic::ptx_read_gridid:
	return DoesNotAccessMemory;
	case Intrinsic::ptx_read_laneid:
	return DoesNotAccessMemory;
	case Intrinsic::ptx_read_lanemask_eq:
	return DoesNotAccessMemory;
	case Intrinsic::ptx_read_lanemask_ge:
	return DoesNotAccessMemory;
	case Intrinsic::ptx_read_lanemask_gt:
	return DoesNotAccessMemory;
	case Intrinsic::ptx_read_lanemask_le:
	return DoesNotAccessMemory;
	case Intrinsic::ptx_read_lanemask_lt:
	return DoesNotAccessMemory;
	case Intrinsic::ptx_read_nctaid_w:
	return DoesNotAccessMemory;
	case Intrinsic::ptx_read_nctaid_x:
	return DoesNotAccessMemory;
	case Intrinsic::ptx_read_nctaid_y:
	return DoesNotAccessMemory;
	case Intrinsic::ptx_read_nctaid_z:
	return DoesNotAccessMemory;
	case Intrinsic::ptx_read_nsmid:
	return DoesNotAccessMemory;
	case Intrinsic::ptx_read_ntid_w:
	return DoesNotAccessMemory;
	case Intrinsic::ptx_read_ntid_x:
	return DoesNotAccessMemory;
	case Intrinsic::ptx_read_ntid_y:
	return DoesNotAccessMemory;
	case Intrinsic::ptx_read_ntid_z:
	return DoesNotAccessMemory;
	case Intrinsic::ptx_read_nwarpid:
	return DoesNotAccessMemory;
	case Intrinsic::ptx_read_pm0:
	return DoesNotAccessMemory;
	case Intrinsic::ptx_read_pm1:
	return DoesNotAccessMemory;
	case Intrinsic::ptx_read_pm2:
	return DoesNotAccessMemory;
	case Intrinsic::ptx_read_pm3:
	return DoesNotAccessMemory;
	case Intrinsic::ptx_read_smid:
	return DoesNotAccessMemory;
	case Intrinsic::ptx_read_tid_w:
	return DoesNotAccessMemory;
	case Intrinsic::ptx_read_tid_x:
	return DoesNotAccessMemory;
	case Intrinsic::ptx_read_tid_y:
	return DoesNotAccessMemory;
	case Intrinsic::ptx_read_tid_z:
	return DoesNotAccessMemory;
	case Intrinsic::ptx_read_warpid:
	return DoesNotAccessMemory;
	case Intrinsic::returnaddress:
	return DoesNotAccessMemory;
	case Intrinsic::sadd_with_overflow:
	return DoesNotAccessMemory;
	case Intrinsic::sin:
	return OnlyReadsMemory;
	case Intrinsic::smul_with_overflow:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_a:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_addx:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_ah:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_ahi:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_ai:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_and:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_andbi:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_andc:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_andhi:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_andi:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_bg:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_bgx:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_ceq:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_ceqb:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_ceqbi:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_ceqh:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_ceqhi:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_ceqi:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_cg:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_cgt:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_cgtb:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_cgtbi:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_cgth:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_cgthi:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_cgti:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_cgx:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_clgt:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_clgtb:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_clgtbi:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_clgth:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_clgthi:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_clgti:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_dfa:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_dfm:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_dfma:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_dfms:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_dfnma:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_dfnms:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_dfs:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_fa:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_fceq:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_fcgt:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_fcmeq:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_fcmgt:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_fm:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_fma:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_fms:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_fnms:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_fs:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_fsmbi:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_mpy:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_mpya:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_mpyh:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_mpyhh:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_mpyhha:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_mpyhhau:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_mpyhhu:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_mpyi:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_mpys:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_mpyu:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_mpyui:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_nand:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_nor:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_or:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_orbi:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_orc:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_orhi:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_ori:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_sf:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_sfh:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_sfhi:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_sfi:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_sfx:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_shli:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_shlqbi:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_shlqbii:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_shlqby:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_shlqbyi:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_xor:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_xorbi:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_xorhi:
	return DoesNotAccessMemory;
	case Intrinsic::spu_si_xori:
	return DoesNotAccessMemory;
	case Intrinsic::sqrt:
	return OnlyReadsMemory;
	case Intrinsic::ssub_with_overflow:
	return DoesNotAccessMemory;
	case Intrinsic::uadd_with_overflow:
	return DoesNotAccessMemory;
	case Intrinsic::umul_with_overflow:
	return DoesNotAccessMemory;
	case Intrinsic::usub_with_overflow:
	return DoesNotAccessMemory;
	case Intrinsic::x86_3dnow_pavgusb:
	return DoesNotAccessMemory;
	case Intrinsic::x86_3dnow_pf2id:
	return DoesNotAccessMemory;
	case Intrinsic::x86_3dnow_pfacc:
	return DoesNotAccessMemory;
	case Intrinsic::x86_3dnow_pfadd:
	return DoesNotAccessMemory;
	case Intrinsic::x86_3dnow_pfcmpeq:
	return DoesNotAccessMemory;
	case Intrinsic::x86_3dnow_pfcmpge:
	return DoesNotAccessMemory;
	case Intrinsic::x86_3dnow_pfcmpgt:
	return DoesNotAccessMemory;
	case Intrinsic::x86_3dnow_pfmax:
	return DoesNotAccessMemory;
	case Intrinsic::x86_3dnow_pfmin:
	return DoesNotAccessMemory;
	case Intrinsic::x86_3dnow_pfmul:
	return DoesNotAccessMemory;
	case Intrinsic::x86_3dnow_pfrcp:
	return DoesNotAccessMemory;
	case Intrinsic::x86_3dnow_pfrcpit1:
	return DoesNotAccessMemory;
	case Intrinsic::x86_3dnow_pfrcpit2:
	return DoesNotAccessMemory;
	case Intrinsic::x86_3dnow_pfrsqit1:
	return DoesNotAccessMemory;
	case Intrinsic::x86_3dnow_pfrsqrt:
	return DoesNotAccessMemory;
	case Intrinsic::x86_3dnow_pfsub:
	return DoesNotAccessMemory;
	case Intrinsic::x86_3dnow_pfsubr:
	return DoesNotAccessMemory;
	case Intrinsic::x86_3dnow_pi2fd:
	return DoesNotAccessMemory;
	case Intrinsic::x86_3dnow_pmulhrw:
	return DoesNotAccessMemory;
	case Intrinsic::x86_3dnowa_pf2iw:
	return DoesNotAccessMemory;
	case Intrinsic::x86_3dnowa_pfnacc:
	return DoesNotAccessMemory;
	case Intrinsic::x86_3dnowa_pfpnacc:
	return DoesNotAccessMemory;
	case Intrinsic::x86_3dnowa_pi2fw:
	return DoesNotAccessMemory;
	case Intrinsic::x86_3dnowa_pswapd:
	return DoesNotAccessMemory;
	case Intrinsic::x86_aesni_aesdec:
	return DoesNotAccessMemory;
	case Intrinsic::x86_aesni_aesdeclast:
	return DoesNotAccessMemory;
	case Intrinsic::x86_aesni_aesenc:
	return DoesNotAccessMemory;
	case Intrinsic::x86_aesni_aesenclast:
	return DoesNotAccessMemory;
	case Intrinsic::x86_aesni_aesimc:
	return DoesNotAccessMemory;
	case Intrinsic::x86_aesni_aeskeygenassist:
	return DoesNotAccessMemory;
	case Intrinsic::x86_avx_addsub_pd_256:
	return DoesNotAccessMemory;
	case Intrinsic::x86_avx_addsub_ps_256:
	return DoesNotAccessMemory;
	case Intrinsic::x86_avx_blend_pd_256:
	return DoesNotAccessMemory;
	case Intrinsic::x86_avx_blend_ps_256:
	return DoesNotAccessMemory;
	case Intrinsic::x86_avx_blendv_pd_256:
	return DoesNotAccessMemory;
	case Intrinsic::x86_avx_blendv_ps_256:
	return DoesNotAccessMemory;
	case Intrinsic::x86_avx_cmp_pd_256:
	return DoesNotAccessMemory;
	case Intrinsic::x86_avx_cmp_ps_256:
	return DoesNotAccessMemory;
	case Intrinsic::x86_avx_cvt_pd2_ps_256:
	return DoesNotAccessMemory;
	case Intrinsic::x86_avx_cvt_pd2dq_256:
	return DoesNotAccessMemory;
	case Intrinsic::x86_avx_cvt_ps2_pd_256:
	return DoesNotAccessMemory;
	case Intrinsic::x86_avx_cvt_ps2dq_256:
	return DoesNotAccessMemory;
	case Intrinsic::x86_avx_cvtdq2_pd_256:
	return DoesNotAccessMemory;
	case Intrinsic::x86_avx_cvtdq2_ps_256:
	return DoesNotAccessMemory;
	case Intrinsic::x86_avx_cvtt_pd2dq_256:
	return DoesNotAccessMemory;
	case Intrinsic::x86_avx_cvtt_ps2dq_256:
	return DoesNotAccessMemory;
	case Intrinsic::x86_avx_dp_ps_256:
	return DoesNotAccessMemory;
	case Intrinsic::x86_avx_hadd_pd_256:
	return DoesNotAccessMemory;
	case Intrinsic::x86_avx_hadd_ps_256:
	return DoesNotAccessMemory;
	case Intrinsic::x86_avx_hsub_pd_256:
	return DoesNotAccessMemory;
	case Intrinsic::x86_avx_hsub_ps_256:
	return DoesNotAccessMemory;
	case Intrinsic::x86_avx_ldu_dq_256:
	return OnlyReadsMemory;
	case Intrinsic::x86_avx_loadu_dq_256:
	return OnlyReadsMemory;
	case Intrinsic::x86_avx_loadu_pd_256:
	return OnlyReadsMemory;
	case Intrinsic::x86_avx_loadu_ps_256:
	return OnlyReadsMemory;
	case Intrinsic::x86_avx_maskload_pd:
	return OnlyReadsMemory;
	case Intrinsic::x86_avx_maskload_pd_256:
	return OnlyReadsMemory;
	case Intrinsic::x86_avx_maskload_ps:
	return OnlyReadsMemory;
	case Intrinsic::x86_avx_maskload_ps_256:
	return OnlyReadsMemory;
	case Intrinsic::x86_avx_max_pd_256:
	return DoesNotAccessMemory;
	case Intrinsic::x86_avx_max_ps_256:
	return DoesNotAccessMemory;
	case Intrinsic::x86_avx_min_pd_256:
	return DoesNotAccessMemory;
	case Intrinsic::x86_avx_min_ps_256:
	return DoesNotAccessMemory;
	case Intrinsic::x86_avx_movmsk_pd_256:
	return DoesNotAccessMemory;
	case Intrinsic::x86_avx_movmsk_ps_256:
	return DoesNotAccessMemory;
	case Intrinsic::x86_avx_ptestc_256:
	return DoesNotAccessMemory;
	case Intrinsic::x86_avx_ptestnzc_256:
	return DoesNotAccessMemory;
	case Intrinsic::x86_avx_ptestz_256:
	return DoesNotAccessMemory;
	case Intrinsic::x86_avx_rcp_ps_256:
	return DoesNotAccessMemory;
	case Intrinsic::x86_avx_round_pd_256:
	return DoesNotAccessMemory;
	case Intrinsic::x86_avx_round_ps_256:
	return DoesNotAccessMemory;
	case Intrinsic::x86_avx_rsqrt_ps_256:
	return DoesNotAccessMemory;
	case Intrinsic::x86_avx_sqrt_pd_256:
	return DoesNotAccessMemory;
	case Intrinsic::x86_avx_sqrt_ps_256:
	return DoesNotAccessMemory;
	case Intrinsic::x86_avx_vbroadcast_sd_256:
	return OnlyReadsMemory;
	case Intrinsic::x86_avx_vbroadcastf128_pd_256:
	return OnlyReadsMemory;
	case Intrinsic::x86_avx_vbroadcastf128_ps_256:
	return OnlyReadsMemory;
	case Intrinsic::x86_avx_vbroadcastss:
	return OnlyReadsMemory;
	case Intrinsic::x86_avx_vbroadcastss_256:
	return OnlyReadsMemory;
	case Intrinsic::x86_avx_vextractf128_pd_256:
	return DoesNotAccessMemory;
	case Intrinsic::x86_avx_vextractf128_ps_256:
	return DoesNotAccessMemory;
	case Intrinsic::x86_avx_vextractf128_si_256:
	return DoesNotAccessMemory;
	case Intrinsic::x86_avx_vinsertf128_pd_256:
	return DoesNotAccessMemory;
	case Intrinsic::x86_avx_vinsertf128_ps_256:
	return DoesNotAccessMemory;
	case Intrinsic::x86_avx_vinsertf128_si_256:
	return DoesNotAccessMemory;
	case Intrinsic::x86_avx_vperm2f128_pd_256:
	return DoesNotAccessMemory;
	case Intrinsic::x86_avx_vperm2f128_ps_256:
	return DoesNotAccessMemory;
	case Intrinsic::x86_avx_vperm2f128_si_256:
	return DoesNotAccessMemory;
	case Intrinsic::x86_avx_vpermil_pd:
	return DoesNotAccessMemory;
	case Intrinsic::x86_avx_vpermil_pd_256:
	return DoesNotAccessMemory;
	case Intrinsic::x86_avx_vpermil_ps:
	return DoesNotAccessMemory;
	case Intrinsic::x86_avx_vpermil_ps_256:
	return DoesNotAccessMemory;
	case Intrinsic::x86_avx_vpermilvar_pd:
	return DoesNotAccessMemory;
	case Intrinsic::x86_avx_vpermilvar_pd_256:
	return DoesNotAccessMemory;
	case Intrinsic::x86_avx_vpermilvar_ps:
	return DoesNotAccessMemory;
	case Intrinsic::x86_avx_vpermilvar_ps_256:
	return DoesNotAccessMemory;
	case Intrinsic::x86_avx_vtestc_pd:
	return DoesNotAccessMemory;
	case Intrinsic::x86_avx_vtestc_pd_256:
	return DoesNotAccessMemory;
	case Intrinsic::x86_avx_vtestc_ps:
	return DoesNotAccessMemory;
	case Intrinsic::x86_avx_vtestc_ps_256:
	return DoesNotAccessMemory;
	case Intrinsic::x86_avx_vtestnzc_pd:
	return DoesNotAccessMemory;
	case Intrinsic::x86_avx_vtestnzc_pd_256:
	return DoesNotAccessMemory;
	case Intrinsic::x86_avx_vtestnzc_ps:
	return DoesNotAccessMemory;
	case Intrinsic::x86_avx_vtestnzc_ps_256:
	return DoesNotAccessMemory;
	case Intrinsic::x86_avx_vtestz_pd:
	return DoesNotAccessMemory;
	case Intrinsic::x86_avx_vtestz_pd_256:
	return DoesNotAccessMemory;
	case Intrinsic::x86_avx_vtestz_ps:
	return DoesNotAccessMemory;
	case Intrinsic::x86_avx_vtestz_ps_256:
	return DoesNotAccessMemory;
	case Intrinsic::x86_mmx_packssdw:
	return DoesNotAccessMemory;
	case Intrinsic::x86_mmx_packsswb:
	return DoesNotAccessMemory;
	case Intrinsic::x86_mmx_packuswb:
	return DoesNotAccessMemory;
	case Intrinsic::x86_mmx_padd_b:
	return DoesNotAccessMemory;
	case Intrinsic::x86_mmx_padd_d:
	return DoesNotAccessMemory;
	case Intrinsic::x86_mmx_padd_q:
	return DoesNotAccessMemory;
	case Intrinsic::x86_mmx_padd_w:
	return DoesNotAccessMemory;
	case Intrinsic::x86_mmx_padds_b:
	return DoesNotAccessMemory;
	case Intrinsic::x86_mmx_padds_w:
	return DoesNotAccessMemory;
	case Intrinsic::x86_mmx_paddus_b:
	return DoesNotAccessMemory;
	case Intrinsic::x86_mmx_paddus_w:
	return DoesNotAccessMemory;
	case Intrinsic::x86_mmx_palignr_b:
	return DoesNotAccessMemory;
	case Intrinsic::x86_mmx_pand:
	return DoesNotAccessMemory;
	case Intrinsic::x86_mmx_pandn:
	return DoesNotAccessMemory;
	case Intrinsic::x86_mmx_pavg_b:
	return DoesNotAccessMemory;
	case Intrinsic::x86_mmx_pavg_w:
	return DoesNotAccessMemory;
	case Intrinsic::x86_mmx_pcmpeq_b:
	return DoesNotAccessMemory;
	case Intrinsic::x86_mmx_pcmpeq_d:
	return DoesNotAccessMemory;
	case Intrinsic::x86_mmx_pcmpeq_w:
	return DoesNotAccessMemory;
	case Intrinsic::x86_mmx_pcmpgt_b:
	return DoesNotAccessMemory;
	case Intrinsic::x86_mmx_pcmpgt_d:
	return DoesNotAccessMemory;
	case Intrinsic::x86_mmx_pcmpgt_w:
	return DoesNotAccessMemory;
	case Intrinsic::x86_mmx_pextr_w:
	return DoesNotAccessMemory;
	case Intrinsic::x86_mmx_pinsr_w:
	return DoesNotAccessMemory;
	case Intrinsic::x86_mmx_pmadd_wd:
	return DoesNotAccessMemory;
	case Intrinsic::x86_mmx_pmaxs_w:
	return DoesNotAccessMemory;
	case Intrinsic::x86_mmx_pmaxu_b:
	return DoesNotAccessMemory;
	case Intrinsic::x86_mmx_pmins_w:
	return DoesNotAccessMemory;
	case Intrinsic::x86_mmx_pminu_b:
	return DoesNotAccessMemory;
	case Intrinsic::x86_mmx_pmovmskb:
	return DoesNotAccessMemory;
	case Intrinsic::x86_mmx_pmulh_w:
	return DoesNotAccessMemory;
	case Intrinsic::x86_mmx_pmulhu_w:
	return DoesNotAccessMemory;
	case Intrinsic::x86_mmx_pmull_w:
	return DoesNotAccessMemory;
	case Intrinsic::x86_mmx_pmulu_dq:
	return DoesNotAccessMemory;
	case Intrinsic::x86_mmx_por:
	return DoesNotAccessMemory;
	case Intrinsic::x86_mmx_psad_bw:
	return DoesNotAccessMemory;
	case Intrinsic::x86_mmx_psll_d:
	return DoesNotAccessMemory;
	case Intrinsic::x86_mmx_psll_q:
	return DoesNotAccessMemory;
	case Intrinsic::x86_mmx_psll_w:
	return DoesNotAccessMemory;
	case Intrinsic::x86_mmx_pslli_d:
	return DoesNotAccessMemory;
	case Intrinsic::x86_mmx_pslli_q:
	return DoesNotAccessMemory;
	case Intrinsic::x86_mmx_pslli_w:
	return DoesNotAccessMemory;
	case Intrinsic::x86_mmx_psra_d:
	return DoesNotAccessMemory;
	case Intrinsic::x86_mmx_psra_w:
	return DoesNotAccessMemory;
	case Intrinsic::x86_mmx_psrai_d:
	return DoesNotAccessMemory;
	case Intrinsic::x86_mmx_psrai_w:
	return DoesNotAccessMemory;
	case Intrinsic::x86_mmx_psrl_d:
	return DoesNotAccessMemory;
	case Intrinsic::x86_mmx_psrl_q:
	return DoesNotAccessMemory;
	case Intrinsic::x86_mmx_psrl_w:
	return DoesNotAccessMemory;
	case Intrinsic::x86_mmx_psrli_d:
	return DoesNotAccessMemory;
	case Intrinsic::x86_mmx_psrli_q:
	return DoesNotAccessMemory;
	case Intrinsic::x86_mmx_psrli_w:
	return DoesNotAccessMemory;
	case Intrinsic::x86_mmx_psub_b:
	return DoesNotAccessMemory;
	case Intrinsic::x86_mmx_psub_d:
	return DoesNotAccessMemory;
	case Intrinsic::x86_mmx_psub_q:
	return DoesNotAccessMemory;
	case Intrinsic::x86_mmx_psub_w:
	return DoesNotAccessMemory;
	case Intrinsic::x86_mmx_psubs_b:
	return DoesNotAccessMemory;
	case Intrinsic::x86_mmx_psubs_w:
	return DoesNotAccessMemory;
	case Intrinsic::x86_mmx_psubus_b:
	return DoesNotAccessMemory;
	case Intrinsic::x86_mmx_psubus_w:
	return DoesNotAccessMemory;
	case Intrinsic::x86_mmx_punpckhbw:
	return DoesNotAccessMemory;
	case Intrinsic::x86_mmx_punpckhdq:
	return DoesNotAccessMemory;
	case Intrinsic::x86_mmx_punpckhwd:
	return DoesNotAccessMemory;
	case Intrinsic::x86_mmx_punpcklbw:
	return DoesNotAccessMemory;
	case Intrinsic::x86_mmx_punpckldq:
	return DoesNotAccessMemory;
	case Intrinsic::x86_mmx_punpcklwd:
	return DoesNotAccessMemory;
	case Intrinsic::x86_mmx_pxor:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_add_sd:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_cmp_pd:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_cmp_sd:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_comieq_sd:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_comige_sd:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_comigt_sd:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_comile_sd:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_comilt_sd:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_comineq_sd:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_cvtdq2pd:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_cvtdq2ps:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_cvtpd2dq:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_cvtpd2ps:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_cvtps2dq:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_cvtps2pd:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_cvtsd2si:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_cvtsd2si64:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_cvtsd2ss:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_cvtsi2sd:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_cvtsi642sd:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_cvtss2sd:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_cvttpd2dq:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_cvttps2dq:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_cvttsd2si:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_cvttsd2si64:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_div_sd:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_max_pd:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_max_sd:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_min_pd:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_min_sd:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_movmsk_pd:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_mul_sd:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_packssdw_128:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_packsswb_128:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_packuswb_128:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_padds_b:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_padds_w:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_paddus_b:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_paddus_w:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_pavg_b:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_pavg_w:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_pcmpeq_b:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_pcmpeq_d:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_pcmpeq_w:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_pcmpgt_b:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_pcmpgt_d:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_pcmpgt_w:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_pmadd_wd:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_pmaxs_w:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_pmaxu_b:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_pmins_w:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_pminu_b:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_pmovmskb_128:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_pmulh_w:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_pmulhu_w:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_pmulu_dq:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_psad_bw:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_psll_d:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_psll_dq:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_psll_dq_bs:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_psll_q:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_psll_w:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_pslli_d:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_pslli_q:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_pslli_w:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_psra_d:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_psra_w:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_psrai_d:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_psrai_w:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_psrl_d:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_psrl_dq:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_psrl_dq_bs:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_psrl_q:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_psrl_w:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_psrli_d:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_psrli_q:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_psrli_w:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_psubs_b:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_psubs_w:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_psubus_b:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_psubus_w:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_sqrt_pd:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_sqrt_sd:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_sub_sd:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_ucomieq_sd:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_ucomige_sd:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_ucomigt_sd:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_ucomile_sd:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_ucomilt_sd:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse2_ucomineq_sd:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse3_addsub_pd:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse3_addsub_ps:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse3_hadd_pd:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse3_hadd_ps:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse3_hsub_pd:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse3_hsub_ps:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse3_ldu_dq:
	return OnlyReadsMemory;
	case Intrinsic::x86_sse41_blendpd:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse41_blendps:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse41_blendvpd:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse41_blendvps:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse41_dppd:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse41_dpps:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse41_extractps:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse41_insertps:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse41_movntdqa:
	return OnlyReadsMemory;
	case Intrinsic::x86_sse41_mpsadbw:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse41_packusdw:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse41_pblendvb:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse41_pblendw:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse41_pcmpeqq:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse41_pextrb:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse41_pextrd:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse41_pextrq:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse41_phminposuw:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse41_pmaxsb:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse41_pmaxsd:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse41_pmaxud:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse41_pmaxuw:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse41_pminsb:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse41_pminsd:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse41_pminud:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse41_pminuw:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse41_pmovsxbd:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse41_pmovsxbq:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse41_pmovsxbw:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse41_pmovsxdq:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse41_pmovsxwd:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse41_pmovsxwq:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse41_pmovzxbd:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse41_pmovzxbq:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse41_pmovzxbw:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse41_pmovzxdq:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse41_pmovzxwd:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse41_pmovzxwq:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse41_pmuldq:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse41_ptestc:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse41_ptestnzc:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse41_ptestz:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse41_round_pd:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse41_round_ps:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse41_round_sd:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse41_round_ss:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse42_crc32_32_16:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse42_crc32_32_32:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse42_crc32_32_8:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse42_crc32_64_64:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse42_crc32_64_8:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse42_pcmpestri128:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse42_pcmpestria128:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse42_pcmpestric128:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse42_pcmpestrio128:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse42_pcmpestris128:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse42_pcmpestriz128:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse42_pcmpestrm128:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse42_pcmpgtq:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse42_pcmpistri128:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse42_pcmpistria128:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse42_pcmpistric128:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse42_pcmpistrio128:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse42_pcmpistris128:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse42_pcmpistriz128:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse42_pcmpistrm128:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse_add_ss:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse_cmp_ps:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse_cmp_ss:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse_comieq_ss:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse_comige_ss:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse_comigt_ss:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse_comile_ss:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse_comilt_ss:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse_comineq_ss:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse_cvtpd2pi:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse_cvtpi2pd:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse_cvtpi2ps:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse_cvtps2pi:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse_cvtsi2ss:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse_cvtsi642ss:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse_cvtss2si:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse_cvtss2si64:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse_cvttpd2pi:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse_cvttps2pi:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse_cvttss2si:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse_cvttss2si64:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse_div_ss:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse_max_ps:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse_max_ss:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse_min_ps:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse_min_ss:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse_movmsk_ps:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse_mul_ss:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse_pshuf_w:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse_rcp_ps:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse_rcp_ss:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse_rsqrt_ps:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse_rsqrt_ss:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse_sqrt_ps:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse_sqrt_ss:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse_sub_ss:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse_ucomieq_ss:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse_ucomige_ss:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse_ucomigt_ss:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse_ucomile_ss:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse_ucomilt_ss:
	return DoesNotAccessMemory;
	case Intrinsic::x86_sse_ucomineq_ss:
	return DoesNotAccessMemory;
	case Intrinsic::x86_ssse3_pabs_b:
	return DoesNotAccessMemory;
	case Intrinsic::x86_ssse3_pabs_b_128:
	return DoesNotAccessMemory;
	case Intrinsic::x86_ssse3_pabs_d:
	return DoesNotAccessMemory;
	case Intrinsic::x86_ssse3_pabs_d_128:
	return DoesNotAccessMemory;
	case Intrinsic::x86_ssse3_pabs_w:
	return DoesNotAccessMemory;
	case Intrinsic::x86_ssse3_pabs_w_128:
	return DoesNotAccessMemory;
	case Intrinsic::x86_ssse3_phadd_d:
	return DoesNotAccessMemory;
	case Intrinsic::x86_ssse3_phadd_d_128:
	return DoesNotAccessMemory;
	case Intrinsic::x86_ssse3_phadd_sw:
	return DoesNotAccessMemory;
	case Intrinsic::x86_ssse3_phadd_sw_128:
	return DoesNotAccessMemory;
	case Intrinsic::x86_ssse3_phadd_w:
	return DoesNotAccessMemory;
	case Intrinsic::x86_ssse3_phadd_w_128:
	return DoesNotAccessMemory;
	case Intrinsic::x86_ssse3_phsub_d:
	return DoesNotAccessMemory;
	case Intrinsic::x86_ssse3_phsub_d_128:
	return DoesNotAccessMemory;
	case Intrinsic::x86_ssse3_phsub_sw:
	return DoesNotAccessMemory;
	case Intrinsic::x86_ssse3_phsub_sw_128:
	return DoesNotAccessMemory;
	case Intrinsic::x86_ssse3_phsub_w:
	return DoesNotAccessMemory;
	case Intrinsic::x86_ssse3_phsub_w_128:
	return DoesNotAccessMemory;
	case Intrinsic::x86_ssse3_pmadd_ub_sw:
	return DoesNotAccessMemory;
	case Intrinsic::x86_ssse3_pmadd_ub_sw_128:
	return DoesNotAccessMemory;
	case Intrinsic::x86_ssse3_pmul_hr_sw:
	return DoesNotAccessMemory;
	case Intrinsic::x86_ssse3_pmul_hr_sw_128:
	return DoesNotAccessMemory;
	case Intrinsic::x86_ssse3_pshuf_b:
	return DoesNotAccessMemory;
	case Intrinsic::x86_ssse3_pshuf_b_128:
	return DoesNotAccessMemory;
	case Intrinsic::x86_ssse3_psign_b:
	return DoesNotAccessMemory;
	case Intrinsic::x86_ssse3_psign_b_128:
	return DoesNotAccessMemory;
	case Intrinsic::x86_ssse3_psign_d:
	return DoesNotAccessMemory;
	case Intrinsic::x86_ssse3_psign_d_128:
	return DoesNotAccessMemory;
	case Intrinsic::x86_ssse3_psign_w:
	return DoesNotAccessMemory;
	case Intrinsic::x86_ssse3_psign_w_128:
	return DoesNotAccessMemory;
	case Intrinsic::xcore_bitrev:
	return DoesNotAccessMemory;
	case Intrinsic::xcore_crc32:
	return DoesNotAccessMemory;
	case Intrinsic::xcore_crc8:
	return DoesNotAccessMemory;
	case Intrinsic::xcore_getid:
	return DoesNotAccessMemory;
	case Intrinsic::xcore_sext:
	return DoesNotAccessMemory;
	case Intrinsic::xcore_waitevent:
	return OnlyReadsMemory;
	case Intrinsic::xcore_zext:
	return DoesNotAccessMemory;
	}
	#endif // GET_INTRINSIC_MODREF_BEHAVIOR

	// Get the GCC builtin that corresponds to an LLVM intrinsic.
	#ifdef GET_GCC_BUILTIN_NAME
	switch (F->getIntrinsicID()) {
	default: BuiltinName = ""; break;
	case Intrinsic::adjust_trampoline: BuiltinName = "__builtin_adjust_trampo
	line"; break;
	case Intrinsic::alpha_umulh: BuiltinName = "__builtin_alpha_umulh"; break
	;
	case Intrinsic::arm_cdp: BuiltinName = "__builtin_arm_cdp"; break;
	case Intrinsic::arm_cdp2: BuiltinName = "__builtin_arm_cdp2"; break;
	case Intrinsic::arm_get_fpscr: BuiltinName = "__builtin_arm_get_fpscr"; b
	reak;
	case Intrinsic::arm_mcr: BuiltinName = "__builtin_arm_mcr"; break;
	case Intrinsic::arm_mcr2: BuiltinName = "__builtin_arm_mcr2"; break;
	case Intrinsic::arm_mcrr: BuiltinName = "__builtin_arm_mcrr"; break;
	case Intrinsic::arm_mcrr2: BuiltinName = "__builtin_arm_mcrr2"; break;
	case Intrinsic::arm_mrc: BuiltinName = "__builtin_arm_mrc"; break;
	case Intrinsic::arm_mrc2: BuiltinName = "__builtin_arm_mrc2"; break;
	case Intrinsic::arm_qadd: BuiltinName = "__builtin_arm_qadd"; break;
	case Intrinsic::arm_qsub: BuiltinName = "__builtin_arm_qsub"; break;
	case Intrinsic::arm_set_fpscr: BuiltinName = "__builtin_arm_set_fpscr"; b
	reak;
	case Intrinsic::arm_ssat: BuiltinName = "__builtin_arm_ssat"; break;
	case Intrinsic::arm_thread_pointer: BuiltinName = "__builtin_thread_point
	er"; break;
	case Intrinsic::arm_usat: BuiltinName = "__builtin_arm_usat"; break;
	case Intrinsic::convert_from_fp16: BuiltinName = "__gnu_h2f_ieee"; break;
	case Intrinsic::convert_to_fp16: BuiltinName = "__gnu_f2h_ieee"; break;
	case Intrinsic::eh_unwind_init: BuiltinName = "__builtin_unwind_init"; br
	eak;
	case Intrinsic::flt_rounds: BuiltinName = "__builtin_flt_rounds"; break;
	case Intrinsic::init_trampoline: BuiltinName = "__builtin_init_trampoline
	"; break;
	case Intrinsic::objectsize: BuiltinName = "__builtin_object_size"; break;
	case Intrinsic::ppc_altivec_dss: BuiltinName = "__builtin_altivec_dss"; b
	reak;
	case Intrinsic::ppc_altivec_dssall: BuiltinName = "__builtin_altivec_dssa
	ll"; break;
	case Intrinsic::ppc_altivec_dst: BuiltinName = "__builtin_altivec_dst"; b
	reak;
	case Intrinsic::ppc_altivec_dstst: BuiltinName = "__builtin_altivec_dstst
	"; break;
	case Intrinsic::ppc_altivec_dststt: BuiltinName = "__builtin_altivec_dsts
	tt"; break;
	case Intrinsic::ppc_altivec_dstt: BuiltinName = "__builtin_altivec_dstt";
	break;
	case Intrinsic::ppc_altivec_mfvscr: BuiltinName = "__builtin_altivec_mfvs
	cr"; break;
	case Intrinsic::ppc_altivec_mtvscr: BuiltinName = "__builtin_altivec_mtvs
	cr"; break;
	case Intrinsic::ppc_altivec_vaddcuw: BuiltinName = "__builtin_altivec_vad
	dcuw"; break;
	case Intrinsic::ppc_altivec_vaddsbs: BuiltinName = "__builtin_altivec_vad
	dsbs"; break;
	case Intrinsic::ppc_altivec_vaddshs: BuiltinName = "__builtin_altivec_vad
	dshs"; break;
	case Intrinsic::ppc_altivec_vaddsws: BuiltinName = "__builtin_altivec_vad
	dsws"; break;
	case Intrinsic::ppc_altivec_vaddubs: BuiltinName = "__builtin_altivec_vad
	dubs"; break;
	case Intrinsic::ppc_altivec_vadduhs: BuiltinName = "__builtin_altivec_vad
	duhs"; break;
	case Intrinsic::ppc_altivec_vadduws: BuiltinName = "__builtin_altivec_vad
	duws"; break;
	case Intrinsic::ppc_altivec_vavgsb: BuiltinName = "__builtin_altivec_vavg
	sb"; break;
	case Intrinsic::ppc_altivec_vavgsh: BuiltinName = "__builtin_altivec_vavg
	sh"; break;
	case Intrinsic::ppc_altivec_vavgsw: BuiltinName = "__builtin_altivec_vavg
	sw"; break;
	case Intrinsic::ppc_altivec_vavgub: BuiltinName = "__builtin_altivec_vavg
	ub"; break;
	case Intrinsic::ppc_altivec_vavguh: BuiltinName = "__builtin_altivec_vavg
	uh"; break;
	case Intrinsic::ppc_altivec_vavguw: BuiltinName = "__builtin_altivec_vavg
	uw"; break;
	case Intrinsic::ppc_altivec_vcfsx: BuiltinName = "__builtin_altivec_vcfsx
	"; break;
	case Intrinsic::ppc_altivec_vcfux: BuiltinName = "__builtin_altivec_vcfux
	"; break;
	case Intrinsic::ppc_altivec_vcmpbfp: BuiltinName = "__builtin_altivec_vcm
	pbfp"; break;
	case Intrinsic::ppc_altivec_vcmpbfp_p: BuiltinName = "__builtin_altivec_v
	cmpbfp_p"; break;
	case Intrinsic::ppc_altivec_vcmpeqfp: BuiltinName = "__builtin_altivec_vc
	mpeqfp"; break;
	case Intrinsic::ppc_altivec_vcmpeqfp_p: BuiltinName = "__builtin_altivec_
	vcmpeqfp_p"; break;
	case Intrinsic::ppc_altivec_vcmpequb: BuiltinName = "__builtin_altivec_vc
	mpequb"; break;
	case Intrinsic::ppc_altivec_vcmpequb_p: BuiltinName = "__builtin_altivec_
	vcmpequb_p"; break;
	case Intrinsic::ppc_altivec_vcmpequh: BuiltinName = "__builtin_altivec_vc
	mpequh"; break;
	case Intrinsic::ppc_altivec_vcmpequh_p: BuiltinName = "__builtin_altivec_
	vcmpequh_p"; break;
	case Intrinsic::ppc_altivec_vcmpequw: BuiltinName = "__builtin_altivec_vc
	mpequw"; break;
	case Intrinsic::ppc_altivec_vcmpequw_p: BuiltinName = "__builtin_altivec_
	vcmpequw_p"; break;
	case Intrinsic::ppc_altivec_vcmpgefp: BuiltinName = "__builtin_altivec_vc
	mpgefp"; break;
	case Intrinsic::ppc_altivec_vcmpgefp_p: BuiltinName = "__builtin_altivec_
	vcmpgefp_p"; break;
	case Intrinsic::ppc_altivec_vcmpgtfp: BuiltinName = "__builtin_altivec_vc
	mpgtfp"; break;
	case Intrinsic::ppc_altivec_vcmpgtfp_p: BuiltinName = "__builtin_altivec_
	vcmpgtfp_p"; break;
	case Intrinsic::ppc_altivec_vcmpgtsb: BuiltinName = "__builtin_altivec_vc
	mpgtsb"; break;
	case Intrinsic::ppc_altivec_vcmpgtsb_p: BuiltinName = "__builtin_altivec_
	vcmpgtsb_p"; break;
	case Intrinsic::ppc_altivec_vcmpgtsh: BuiltinName = "__builtin_altivec_vc
	mpgtsh"; break;
	case Intrinsic::ppc_altivec_vcmpgtsh_p: BuiltinName = "__builtin_altivec_
	vcmpgtsh_p"; break;
	case Intrinsic::ppc_altivec_vcmpgtsw: BuiltinName = "__builtin_altivec_vc
	mpgtsw"; break;
	case Intrinsic::ppc_altivec_vcmpgtsw_p: BuiltinName = "__builtin_altivec_
	vcmpgtsw_p"; break;
	case Intrinsic::ppc_altivec_vcmpgtub: BuiltinName = "__builtin_altivec_vc
	mpgtub"; break;
	case Intrinsic::ppc_altivec_vcmpgtub_p: BuiltinName = "__builtin_altivec_
	vcmpgtub_p"; break;
	case Intrinsic::ppc_altivec_vcmpgtuh: BuiltinName = "__builtin_altivec_vc
	mpgtuh"; break;
	case Intrinsic::ppc_altivec_vcmpgtuh_p: BuiltinName = "__builtin_altivec_
	vcmpgtuh_p"; break;
	case Intrinsic::ppc_altivec_vcmpgtuw: BuiltinName = "__builtin_altivec_vc
	mpgtuw"; break;
	case Intrinsic::ppc_altivec_vcmpgtuw_p: BuiltinName = "__builtin_altivec_
	vcmpgtuw_p"; break;
	case Intrinsic::ppc_altivec_vctsxs: BuiltinName = "__builtin_altivec_vcts
	xs"; break;
	case Intrinsic::ppc_altivec_vctuxs: BuiltinName = "__builtin_altivec_vctu
	xs"; break;
	case Intrinsic::ppc_altivec_vexptefp: BuiltinName = "__builtin_altivec_ve
	xptefp"; break;
	case Intrinsic::ppc_altivec_vlogefp: BuiltinName = "__builtin_altivec_vlo
	gefp"; break;
	case Intrinsic::ppc_altivec_vmaddfp: BuiltinName = "__builtin_altivec_vma
	ddfp"; break;
	case Intrinsic::ppc_altivec_vmaxfp: BuiltinName = "__builtin_altivec_vmax
	fp"; break;
	case Intrinsic::ppc_altivec_vmaxsb: BuiltinName = "__builtin_altivec_vmax
	sb"; break;
	case Intrinsic::ppc_altivec_vmaxsh: BuiltinName = "__builtin_altivec_vmax
	sh"; break;
	case Intrinsic::ppc_altivec_vmaxsw: BuiltinName = "__builtin_altivec_vmax
	sw"; break;
	case Intrinsic::ppc_altivec_vmaxub: BuiltinName = "__builtin_altivec_vmax
	ub"; break;
	case Intrinsic::ppc_altivec_vmaxuh: BuiltinName = "__builtin_altivec_vmax
	uh"; break;
	case Intrinsic::ppc_altivec_vmaxuw: BuiltinName = "__builtin_altivec_vmax
	uw"; break;
	case Intrinsic::ppc_altivec_vmhaddshs: BuiltinName = "__builtin_altivec_v
	mhaddshs"; break;
	case Intrinsic::ppc_altivec_vmhraddshs: BuiltinName = "__builtin_altivec_
	vmhraddshs"; break;
	case Intrinsic::ppc_altivec_vminfp: BuiltinName = "__builtin_altivec_vmin
	fp"; break;
	case Intrinsic::ppc_altivec_vminsb: BuiltinName = "__builtin_altivec_vmin
	sb"; break;
	case Intrinsic::ppc_altivec_vminsh: BuiltinName = "__builtin_altivec_vmin
	sh"; break;
	case Intrinsic::ppc_altivec_vminsw: BuiltinName = "__builtin_altivec_vmin
	sw"; break;
	case Intrinsic::ppc_altivec_vminub: BuiltinName = "__builtin_altivec_vmin
	ub"; break;
	case Intrinsic::ppc_altivec_vminuh: BuiltinName = "__builtin_altivec_vmin
	uh"; break;
	case Intrinsic::ppc_altivec_vminuw: BuiltinName = "__builtin_altivec_vmin
	uw"; break;
	case Intrinsic::ppc_altivec_vmladduhm: BuiltinName = "__builtin_altivec_v
	mladduhm"; break;
	case Intrinsic::ppc_altivec_vmsummbm: BuiltinName = "__builtin_altivec_vm
	summbm"; break;
	case Intrinsic::ppc_altivec_vmsumshm: BuiltinName = "__builtin_altivec_vm
	sumshm"; break;
	case Intrinsic::ppc_altivec_vmsumshs: BuiltinName = "__builtin_altivec_vm
	sumshs"; break;
	case Intrinsic::ppc_altivec_vmsumubm: BuiltinName = "__builtin_altivec_vm
	sumubm"; break;
	case Intrinsic::ppc_altivec_vmsumuhm: BuiltinName = "__builtin_altivec_vm
	sumuhm"; break;
	case Intrinsic::ppc_altivec_vmsumuhs: BuiltinName = "__builtin_altivec_vm
	sumuhs"; break;
	case Intrinsic::ppc_altivec_vmulesb: BuiltinName = "__builtin_altivec_vmu
	lesb"; break;
	case Intrinsic::ppc_altivec_vmulesh: BuiltinName = "__builtin_altivec_vmu
	lesh"; break;
	case Intrinsic::ppc_altivec_vmuleub: BuiltinName = "__builtin_altivec_vmu
	leub"; break;
	case Intrinsic::ppc_altivec_vmuleuh: BuiltinName = "__builtin_altivec_vmu
	leuh"; break;
	case Intrinsic::ppc_altivec_vmulosb: BuiltinName = "__builtin_altivec_vmu
	losb"; break;
	case Intrinsic::ppc_altivec_vmulosh: BuiltinName = "__builtin_altivec_vmu
	losh"; break;
	case Intrinsic::ppc_altivec_vmuloub: BuiltinName = "__builtin_altivec_vmu
	loub"; break;
	case Intrinsic::ppc_altivec_vmulouh: BuiltinName = "__builtin_altivec_vmu
	louh"; break;
	case Intrinsic::ppc_altivec_vnmsubfp: BuiltinName = "__builtin_altivec_vn
	msubfp"; break;
	case Intrinsic::ppc_altivec_vperm: BuiltinName = "__builtin_altivec_vperm
	_4si"; break;
	case Intrinsic::ppc_altivec_vpkpx: BuiltinName = "__builtin_altivec_vpkpx
	"; break;
	case Intrinsic::ppc_altivec_vpkshss: BuiltinName = "__builtin_altivec_vpk
	shss"; break;
	case Intrinsic::ppc_altivec_vpkshus: BuiltinName = "__builtin_altivec_vpk
	shus"; break;
	case Intrinsic::ppc_altivec_vpkswss: BuiltinName = "__builtin_altivec_vpk
	swss"; break;
	case Intrinsic::ppc_altivec_vpkswus: BuiltinName = "__builtin_altivec_vpk
	swus"; break;
	case Intrinsic::ppc_altivec_vpkuhus: BuiltinName = "__builtin_altivec_vpk
	uhus"; break;
	case Intrinsic::ppc_altivec_vpkuwus: BuiltinName = "__builtin_altivec_vpk
	uwus"; break;
	case Intrinsic::ppc_altivec_vrefp: BuiltinName = "__builtin_altivec_vrefp
	"; break;
	case Intrinsic::ppc_altivec_vrfim: BuiltinName = "__builtin_altivec_vrfim
	"; break;
	case Intrinsic::ppc_altivec_vrfin: BuiltinName = "__builtin_altivec_vrfin
	"; break;
	case Intrinsic::ppc_altivec_vrfip: BuiltinName = "__builtin_altivec_vrfip
	"; break;
	case Intrinsic::ppc_altivec_vrfiz: BuiltinName = "__builtin_altivec_vrfiz
	"; break;
	case Intrinsic::ppc_altivec_vrlb: BuiltinName = "__builtin_altivec_vrlb";
	break;
	case Intrinsic::ppc_altivec_vrlh: BuiltinName = "__builtin_altivec_vrlh";
	break;
	case Intrinsic::ppc_altivec_vrlw: BuiltinName = "__builtin_altivec_vrlw";
	break;
	case Intrinsic::ppc_altivec_vrsqrtefp: BuiltinName = "__builtin_altivec_v
	rsqrtefp"; break;
	case Intrinsic::ppc_altivec_vsel: BuiltinName = "__builtin_altivec_vsel_4
	si"; break;
	case Intrinsic::ppc_altivec_vsl: BuiltinName = "__builtin_altivec_vsl"; b
	reak;
	case Intrinsic::ppc_altivec_vslb: BuiltinName = "__builtin_altivec_vslb";
	break;
	case Intrinsic::ppc_altivec_vslh: BuiltinName = "__builtin_altivec_vslh";
	break;
	case Intrinsic::ppc_altivec_vslo: BuiltinName = "__builtin_altivec_vslo";
	break;
	case Intrinsic::ppc_altivec_vslw: BuiltinName = "__builtin_altivec_vslw";
	break;
	case Intrinsic::ppc_altivec_vsr: BuiltinName = "__builtin_altivec_vsr"; b
	reak;
	case Intrinsic::ppc_altivec_vsrab: BuiltinName = "__builtin_altivec_vsrab
	"; break;
	case Intrinsic::ppc_altivec_vsrah: BuiltinName = "__builtin_altivec_vsrah
	"; break;
	case Intrinsic::ppc_altivec_vsraw: BuiltinName = "__builtin_altivec_vsraw
	"; break;
	case Intrinsic::ppc_altivec_vsrb: BuiltinName = "__builtin_altivec_vsrb";
	break;
	case Intrinsic::ppc_altivec_vsrh: BuiltinName = "__builtin_altivec_vsrh";
	break;
	case Intrinsic::ppc_altivec_vsro: BuiltinName = "__builtin_altivec_vsro";
	break;
	case Intrinsic::ppc_altivec_vsrw: BuiltinName = "__builtin_altivec_vsrw";
	break;
	case Intrinsic::ppc_altivec_vsubcuw: BuiltinName = "__builtin_altivec_vsu
	bcuw"; break;
	case Intrinsic::ppc_altivec_vsubsbs: BuiltinName = "__builtin_altivec_vsu
	bsbs"; break;
	case Intrinsic::ppc_altivec_vsubshs: BuiltinName = "__builtin_altivec_vsu
	bshs"; break;
	case Intrinsic::ppc_altivec_vsubsws: BuiltinName = "__builtin_altivec_vsu
	bsws"; break;
	case Intrinsic::ppc_altivec_vsububs: BuiltinName = "__builtin_altivec_vsu
	bubs"; break;
	case Intrinsic::ppc_altivec_vsubuhs: BuiltinName = "__builtin_altivec_vsu
	buhs"; break;
	case Intrinsic::ppc_altivec_vsubuws: BuiltinName = "__builtin_altivec_vsu
	buws"; break;
	case Intrinsic::ppc_altivec_vsum2sws: BuiltinName = "__builtin_altivec_vs
	um2sws"; break;
	case Intrinsic::ppc_altivec_vsum4sbs: BuiltinName = "__builtin_altivec_vs
	um4sbs"; break;
	case Intrinsic::ppc_altivec_vsum4shs: BuiltinName = "__builtin_altivec_vs
	um4shs"; break;
	case Intrinsic::ppc_altivec_vsum4ubs: BuiltinName = "__builtin_altivec_vs
	um4ubs"; break;
	case Intrinsic::ppc_altivec_vsumsws: BuiltinName = "__builtin_altivec_vsu
	msws"; break;
	case Intrinsic::ppc_altivec_vupkhpx: BuiltinName = "__builtin_altivec_vup
	khpx"; break;
	case Intrinsic::ppc_altivec_vupkhsb: BuiltinName = "__builtin_altivec_vup
	khsb"; break;
	case Intrinsic::ppc_altivec_vupkhsh: BuiltinName = "__builtin_altivec_vup
	khsh"; break;
	case Intrinsic::ppc_altivec_vupklpx: BuiltinName = "__builtin_altivec_vup
	klpx"; break;
	case Intrinsic::ppc_altivec_vupklsb: BuiltinName = "__builtin_altivec_vup
	klsb"; break;
	case Intrinsic::ppc_altivec_vupklsh: BuiltinName = "__builtin_altivec_vup
	klsh"; break;
	case Intrinsic::ptx_bar_sync: BuiltinName = "__builtin_ptx_bar_sync"; bre
	ak;
	case Intrinsic::ptx_read_clock: BuiltinName = "__builtin_ptx_read_clock";
	break;
	case Intrinsic::ptx_read_clock64: BuiltinName = "__builtin_ptx_read_clock
	64"; break;
	case Intrinsic::ptx_read_ctaid_w: BuiltinName = "__builtin_ptx_read_ctaid
	_w"; break;
	case Intrinsic::ptx_read_ctaid_x: BuiltinName = "__builtin_ptx_read_ctaid
	_x"; break;
	case Intrinsic::ptx_read_ctaid_y: BuiltinName = "__builtin_ptx_read_ctaid
	_y"; break;
	case Intrinsic::ptx_read_ctaid_z: BuiltinName = "__builtin_ptx_read_ctaid
	_z"; break;
	case Intrinsic::ptx_read_gridid: BuiltinName = "__builtin_ptx_read_gridid
	"; break;
	case Intrinsic::ptx_read_laneid: BuiltinName = "__builtin_ptx_read_laneid
	"; break;
	case Intrinsic::ptx_read_lanemask_eq: BuiltinName = "__builtin_ptx_read_l
	anemask_eq"; break;
	case Intrinsic::ptx_read_lanemask_ge: BuiltinName = "__builtin_ptx_read_l
	anemask_ge"; break;
	case Intrinsic::ptx_read_lanemask_gt: BuiltinName = "__builtin_ptx_read_l
	anemask_gt"; break;
	case Intrinsic::ptx_read_lanemask_le: BuiltinName = "__builtin_ptx_read_l
	anemask_le"; break;
	case Intrinsic::ptx_read_lanemask_lt: BuiltinName = "__builtin_ptx_read_l
	anemask_lt"; break;
	case Intrinsic::ptx_read_nctaid_w: BuiltinName = "__builtin_ptx_read_ncta
	id_w"; break;
	case Intrinsic::ptx_read_nctaid_x: BuiltinName = "__builtin_ptx_read_ncta
	id_x"; break;
	case Intrinsic::ptx_read_nctaid_y: BuiltinName = "__builtin_ptx_read_ncta
	id_y"; break;
	case Intrinsic::ptx_read_nctaid_z: BuiltinName = "__builtin_ptx_read_ncta
	id_z"; break;
	case Intrinsic::ptx_read_nsmid: BuiltinName = "__builtin_ptx_read_nsmid";
	break;
	case Intrinsic::ptx_read_ntid_w: BuiltinName = "__builtin_ptx_read_ntid_w
	"; break;
	case Intrinsic::ptx_read_ntid_x: BuiltinName = "__builtin_ptx_read_ntid_x
	"; break;
	case Intrinsic::ptx_read_ntid_y: BuiltinName = "__builtin_ptx_read_ntid_y
	"; break;
	case Intrinsic::ptx_read_ntid_z: BuiltinName = "__builtin_ptx_read_ntid_z
	"; break;
	case Intrinsic::ptx_read_nwarpid: BuiltinName = "__builtin_ptx_read_nwarp
	id"; break;
	case Intrinsic::ptx_read_pm0: BuiltinName = "__builtin_ptx_read_pm0"; bre
	ak;
	case Intrinsic::ptx_read_pm1: BuiltinName = "__builtin_ptx_read_pm1"; bre
	ak;
	case Intrinsic::ptx_read_pm2: BuiltinName = "__builtin_ptx_read_pm2"; bre
	ak;
	case Intrinsic::ptx_read_pm3: BuiltinName = "__builtin_ptx_read_pm3"; bre
	ak;
	case Intrinsic::ptx_read_smid: BuiltinName = "__builtin_ptx_read_smid"; b
	reak;
	case Intrinsic::ptx_read_tid_w: BuiltinName = "__builtin_ptx_read_tid_w";
	break;
	case Intrinsic::ptx_read_tid_x: BuiltinName = "__builtin_ptx_read_tid_x";
	break;
	case Intrinsic::ptx_read_tid_y: BuiltinName = "__builtin_ptx_read_tid_y";
	break;
	case Intrinsic::ptx_read_tid_z: BuiltinName = "__builtin_ptx_read_tid_z";
	break;
	case Intrinsic::ptx_read_warpid: BuiltinName = "__builtin_ptx_read_warpid
	"; break;
	case Intrinsic::spu_si_a: BuiltinName = "__builtin_si_a"; break;
	case Intrinsic::spu_si_addx: BuiltinName = "__builtin_si_addx"; break;
	case Intrinsic::spu_si_ah: BuiltinName = "__builtin_si_ah"; break;
	case Intrinsic::spu_si_ahi: BuiltinName = "__builtin_si_ahi"; break;
	case Intrinsic::spu_si_ai: BuiltinName = "__builtin_si_ai"; break;
	case Intrinsic::spu_si_and: BuiltinName = "__builtin_si_and"; break;
	case Intrinsic::spu_si_andbi: BuiltinName = "__builtin_si_andbi"; break;
	case Intrinsic::spu_si_andc: BuiltinName = "__builtin_si_andc"; break;
	case Intrinsic::spu_si_andhi: BuiltinName = "__builtin_si_andhi"; break;
	case Intrinsic::spu_si_andi: BuiltinName = "__builtin_si_andi"; break;
	case Intrinsic::spu_si_bg: BuiltinName = "__builtin_si_bg"; break;
	case Intrinsic::spu_si_bgx: BuiltinName = "__builtin_si_bgx"; break;
	case Intrinsic::spu_si_ceq: BuiltinName = "__builtin_si_ceq"; break;
	case Intrinsic::spu_si_ceqb: BuiltinName = "__builtin_si_ceqb"; break;
	case Intrinsic::spu_si_ceqbi: BuiltinName = "__builtin_si_ceqbi"; break;
	case Intrinsic::spu_si_ceqh: BuiltinName = "__builtin_si_ceqh"; break;
	case Intrinsic::spu_si_ceqhi: BuiltinName = "__builtin_si_ceqhi"; break;
	case Intrinsic::spu_si_ceqi: BuiltinName = "__builtin_si_ceqi"; break;
	case Intrinsic::spu_si_cg: BuiltinName = "__builtin_si_cg"; break;
	case Intrinsic::spu_si_cgt: BuiltinName = "__builtin_si_cgt"; break;
	case Intrinsic::spu_si_cgtb: BuiltinName = "__builtin_si_cgtb"; break;
	case Intrinsic::spu_si_cgtbi: BuiltinName = "__builtin_si_cgtbi"; break;
	case Intrinsic::spu_si_cgth: BuiltinName = "__builtin_si_cgth"; break;
	case Intrinsic::spu_si_cgthi: BuiltinName = "__builtin_si_cgthi"; break;
	case Intrinsic::spu_si_cgti: BuiltinName = "__builtin_si_cgti"; break;
	case Intrinsic::spu_si_cgx: BuiltinName = "__builtin_si_cgx"; break;
	case Intrinsic::spu_si_clgt: BuiltinName = "__builtin_si_clgt"; break;
	case Intrinsic::spu_si_clgtb: BuiltinName = "__builtin_si_clgtb"; break;
	case Intrinsic::spu_si_clgtbi: BuiltinName = "__builtin_si_clgtbi"; break
	;
	case Intrinsic::spu_si_clgth: BuiltinName = "__builtin_si_clgth"; break;
	case Intrinsic::spu_si_clgthi: BuiltinName = "__builtin_si_clgthi"; break
	;
	case Intrinsic::spu_si_clgti: BuiltinName = "__builtin_si_clgti"; break;
	case Intrinsic::spu_si_dfa: BuiltinName = "__builtin_si_dfa"; break;
	case Intrinsic::spu_si_dfm: BuiltinName = "__builtin_si_dfm"; break;
	case Intrinsic::spu_si_dfma: BuiltinName = "__builtin_si_dfma"; break;
	case Intrinsic::spu_si_dfms: BuiltinName = "__builtin_si_dfms"; break;
	case Intrinsic::spu_si_dfnma: BuiltinName = "__builtin_si_dfnma"; break;
	case Intrinsic::spu_si_dfnms: BuiltinName = "__builtin_si_dfnms"; break;
	case Intrinsic::spu_si_dfs: BuiltinName = "__builtin_si_dfs"; break;
	case Intrinsic::spu_si_fa: BuiltinName = "__builtin_si_fa"; break;
	case Intrinsic::spu_si_fceq: BuiltinName = "__builtin_si_fceq"; break;
	case Intrinsic::spu_si_fcgt: BuiltinName = "__builtin_si_fcgt"; break;
	case Intrinsic::spu_si_fcmeq: BuiltinName = "__builtin_si_fcmeq"; break;
	case Intrinsic::spu_si_fcmgt: BuiltinName = "__builtin_si_fcmgt"; break;
	case Intrinsic::spu_si_fm: BuiltinName = "__builtin_si_fm"; break;
	case Intrinsic::spu_si_fma: BuiltinName = "__builtin_si_fma"; break;
	case Intrinsic::spu_si_fms: BuiltinName = "__builtin_si_fms"; break;
	case Intrinsic::spu_si_fnms: BuiltinName = "__builtin_si_fnms"; break;
	case Intrinsic::spu_si_fs: BuiltinName = "__builtin_si_fs"; break;
	case Intrinsic::spu_si_fsmbi: BuiltinName = "__builtin_si_fsmbi"; break;
	case Intrinsic::spu_si_mpy: BuiltinName = "__builtin_si_mpy"; break;
	case Intrinsic::spu_si_mpya: BuiltinName = "__builtin_si_mpya"; break;
	case Intrinsic::spu_si_mpyh: BuiltinName = "__builtin_si_mpyh"; break;
	case Intrinsic::spu_si_mpyhh: BuiltinName = "__builtin_si_mpyhh"; break;
	case Intrinsic::spu_si_mpyhha: BuiltinName = "__builtin_si_mpyhha"; break
	;
	case Intrinsic::spu_si_mpyhhau: BuiltinName = "__builtin_si_mpyhhau"; bre
	ak;
	case Intrinsic::spu_si_mpyhhu: BuiltinName = "__builtin_si_mpyhhu"; break
	;
	case Intrinsic::spu_si_mpyi: BuiltinName = "__builtin_si_mpyi"; break;
	case Intrinsic::spu_si_mpys: BuiltinName = "__builtin_si_mpys"; break;
	case Intrinsic::spu_si_mpyu: BuiltinName = "__builtin_si_mpyu"; break;
	case Intrinsic::spu_si_mpyui: BuiltinName = "__builtin_si_mpyui"; break;
	case Intrinsic::spu_si_nand: BuiltinName = "__builtin_si_nand"; break;
	case Intrinsic::spu_si_nor: BuiltinName = "__builtin_si_nor"; break;
	case Intrinsic::spu_si_or: BuiltinName = "__builtin_si_or"; break;
	case Intrinsic::spu_si_orbi: BuiltinName = "__builtin_si_orbi"; break;
	case Intrinsic::spu_si_orc: BuiltinName = "__builtin_si_orc"; break;
	case Intrinsic::spu_si_orhi: BuiltinName = "__builtin_si_orhi"; break;
	case Intrinsic::spu_si_ori: BuiltinName = "__builtin_si_ori"; break;
	case Intrinsic::spu_si_sf: BuiltinName = "__builtin_si_sf"; break;
	case Intrinsic::spu_si_sfh: BuiltinName = "__builtin_si_sfh"; break;
	case Intrinsic::spu_si_sfhi: BuiltinName = "__builtin_si_sfhi"; break;
	case Intrinsic::spu_si_sfi: BuiltinName = "__builtin_si_sfi"; break;
	case Intrinsic::spu_si_sfx: BuiltinName = "__builtin_si_sfx"; break;
	case Intrinsic::spu_si_shli: BuiltinName = "__builtin_si_shli"; break;
	case Intrinsic::spu_si_shlqbi: BuiltinName = "__builtin_si_shlqbi"; break
	;
	case Intrinsic::spu_si_shlqbii: BuiltinName = "__builtin_si_shlqbii"; bre
	ak;
	case Intrinsic::spu_si_shlqby: BuiltinName = "__builtin_si_shlqby"; break
	;
	case Intrinsic::spu_si_shlqbyi: BuiltinName = "__builtin_si_shlqbyi"; bre
	ak;
	case Intrinsic::spu_si_xor: BuiltinName = "__builtin_si_xor"; break;
	case Intrinsic::spu_si_xorbi: BuiltinName = "__builtin_si_xorbi"; break;
	case Intrinsic::spu_si_xorhi: BuiltinName = "__builtin_si_xorhi"; break;
	case Intrinsic::spu_si_xori: BuiltinName = "__builtin_si_xori"; break;
	case Intrinsic::stackrestore: BuiltinName = "__builtin_stack_restore"; br
	eak;
	case Intrinsic::stacksave: BuiltinName = "__builtin_stack_save"; break;
	case Intrinsic::trap: BuiltinName = "__builtin_trap"; break;
	case Intrinsic::x86_3dnow_pavgusb: BuiltinName = "__builtin_ia32_pavgusb"
	; break;
	case Intrinsic::x86_3dnow_pf2id: BuiltinName = "__builtin_ia32_pf2id"; br
	eak;
	case Intrinsic::x86_3dnow_pfacc: BuiltinName = "__builtin_ia32_pfacc"; br
	eak;
	case Intrinsic::x86_3dnow_pfadd: BuiltinName = "__builtin_ia32_pfadd"; br
	eak;
	case Intrinsic::x86_3dnow_pfcmpeq: BuiltinName = "__builtin_ia32_pfcmpeq"
	; break;
	case Intrinsic::x86_3dnow_pfcmpge: BuiltinName = "__builtin_ia32_pfcmpge"
	; break;
	case Intrinsic::x86_3dnow_pfcmpgt: BuiltinName = "__builtin_ia32_pfcmpgt"
	; break;
	case Intrinsic::x86_3dnow_pfmax: BuiltinName = "__builtin_ia32_pfmax"; br
	eak;
	case Intrinsic::x86_3dnow_pfmin: BuiltinName = "__builtin_ia32_pfmin"; br
	eak;
	case Intrinsic::x86_3dnow_pfmul: BuiltinName = "__builtin_ia32_pfmul"; br
	eak;
	case Intrinsic::x86_3dnow_pfrcp: BuiltinName = "__builtin_ia32_pfrcp"; br
	eak;
	case Intrinsic::x86_3dnow_pfrcpit1: BuiltinName = "__builtin_ia32_pfrcpit
	1"; break;
	case Intrinsic::x86_3dnow_pfrcpit2: BuiltinName = "__builtin_ia32_pfrcpit
	2"; break;
	case Intrinsic::x86_3dnow_pfrsqit1: BuiltinName = "__builtin_ia32_pfrsqit
	1"; break;
	case Intrinsic::x86_3dnow_pfrsqrt: BuiltinName = "__builtin_ia32_pfrsqrt"
	; break;
	case Intrinsic::x86_3dnow_pfsub: BuiltinName = "__builtin_ia32_pfsub"; br
	eak;
	case Intrinsic::x86_3dnow_pfsubr: BuiltinName = "__builtin_ia32_pfsubr";
	break;
	case Intrinsic::x86_3dnow_pi2fd: BuiltinName = "__builtin_ia32_pi2fd"; br
	eak;
	case Intrinsic::x86_3dnow_pmulhrw: BuiltinName = "__builtin_ia32_pmulhrw"
	; break;
	case Intrinsic::x86_3dnowa_pf2iw: BuiltinName = "__builtin_ia32_pf2iw"; b
	reak;
	case Intrinsic::x86_3dnowa_pfnacc: BuiltinName = "__builtin_ia32_pfnacc";
	break;
	case Intrinsic::x86_3dnowa_pfpnacc: BuiltinName = "__builtin_ia32_pfpnacc
	"; break;
	case Intrinsic::x86_3dnowa_pi2fw: BuiltinName = "__builtin_ia32_pi2fw"; b
	reak;
	case Intrinsic::x86_aesni_aesdec: BuiltinName = "__builtin_ia32_aesdec128
	"; break;
	case Intrinsic::x86_aesni_aesdeclast: BuiltinName = "__builtin_ia32_aesde
	clast128"; break;
	case Intrinsic::x86_aesni_aesenc: BuiltinName = "__builtin_ia32_aesenc128
	"; break;
	case Intrinsic::x86_aesni_aesenclast: BuiltinName = "__builtin_ia32_aesen
	clast128"; break;
	case Intrinsic::x86_aesni_aesimc: BuiltinName = "__builtin_ia32_aesimc128
	"; break;
	case Intrinsic::x86_aesni_aeskeygenassist: BuiltinName = "__builtin_ia32_
	aeskeygenassist128"; break;
	case Intrinsic::x86_avx_addsub_pd_256: BuiltinName = "__builtin_ia32_adds
	ubpd256"; break;
	case Intrinsic::x86_avx_addsub_ps_256: BuiltinName = "__builtin_ia32_adds
	ubps256"; break;
	case Intrinsic::x86_avx_blend_pd_256: BuiltinName = "__builtin_ia32_blend
	pd256"; break;
	case Intrinsic::x86_avx_blend_ps_256: BuiltinName = "__builtin_ia32_blend
	ps256"; break;
	case Intrinsic::x86_avx_blendv_pd_256: BuiltinName = "__builtin_ia32_blen
	dvpd256"; break;
	case Intrinsic::x86_avx_blendv_ps_256: BuiltinName = "__builtin_ia32_blen
	dvps256"; break;
	case Intrinsic::x86_avx_cmp_pd_256: BuiltinName = "__builtin_ia32_cmppd25
	6"; break;
	case Intrinsic::x86_avx_cmp_ps_256: BuiltinName = "__builtin_ia32_cmpps25
	6"; break;
	case Intrinsic::x86_avx_cvt_pd2_ps_256: BuiltinName = "__builtin_ia32_cvt
	pd2ps256"; break;
	case Intrinsic::x86_avx_cvt_pd2dq_256: BuiltinName = "__builtin_ia32_cvtp
	d2dq256"; break;
	case Intrinsic::x86_avx_cvt_ps2_pd_256: BuiltinName = "__builtin_ia32_cvt
	ps2pd256"; break;
	case Intrinsic::x86_avx_cvt_ps2dq_256: BuiltinName = "__builtin_ia32_cvtp
	s2dq256"; break;
	case Intrinsic::x86_avx_cvtdq2_pd_256: BuiltinName = "__builtin_ia32_cvtd
	q2pd256"; break;
	case Intrinsic::x86_avx_cvtdq2_ps_256: BuiltinName = "__builtin_ia32_cvtd
	q2ps256"; break;
	case Intrinsic::x86_avx_cvtt_pd2dq_256: BuiltinName = "__builtin_ia32_cvt
	tpd2dq256"; break;
	case Intrinsic::x86_avx_cvtt_ps2dq_256: BuiltinName = "__builtin_ia32_cvt
	tps2dq256"; break;
	case Intrinsic::x86_avx_dp_ps_256: BuiltinName = "__builtin_ia32_dpps256"
	; break;
	case Intrinsic::x86_avx_hadd_pd_256: BuiltinName = "__builtin_ia32_haddpd
	256"; break;
	case Intrinsic::x86_avx_hadd_ps_256: BuiltinName = "__builtin_ia32_haddps
	256"; break;
	case Intrinsic::x86_avx_hsub_pd_256: BuiltinName = "__builtin_ia32_hsubpd
	256"; break;
	case Intrinsic::x86_avx_hsub_ps_256: BuiltinName = "__builtin_ia32_hsubps
	256"; break;
	case Intrinsic::x86_avx_ldu_dq_256: BuiltinName = "__builtin_ia32_lddqu25
	6"; break;
	case Intrinsic::x86_avx_loadu_dq_256: BuiltinName = "__builtin_ia32_loadd
	qu256"; break;
	case Intrinsic::x86_avx_loadu_pd_256: BuiltinName = "__builtin_ia32_loadu
	pd256"; break;
	case Intrinsic::x86_avx_loadu_ps_256: BuiltinName = "__builtin_ia32_loadu
	ps256"; break;
	case Intrinsic::x86_avx_maskload_pd: BuiltinName = "__builtin_ia32_masklo
	adpd"; break;
	case Intrinsic::x86_avx_maskload_pd_256: BuiltinName = "__builtin_ia32_ma
	skloadpd256"; break;
	case Intrinsic::x86_avx_maskload_ps: BuiltinName = "__builtin_ia32_masklo
	adps"; break;
	case Intrinsic::x86_avx_maskload_ps_256: BuiltinName = "__builtin_ia32_ma
	skloadps256"; break;
	case Intrinsic::x86_avx_maskstore_pd: BuiltinName = "__builtin_ia32_masks
	torepd"; break;
	case Intrinsic::x86_avx_maskstore_pd_256: BuiltinName = "__builtin_ia32_m
	askstorepd256"; break;
	case Intrinsic::x86_avx_maskstore_ps: BuiltinName = "__builtin_ia32_masks
	toreps"; break;
	case Intrinsic::x86_avx_maskstore_ps_256: BuiltinName = "__builtin_ia32_m
	askstoreps256"; break;
	case Intrinsic::x86_avx_max_pd_256: BuiltinName = "__builtin_ia32_maxpd25
	6"; break;
	case Intrinsic::x86_avx_max_ps_256: BuiltinName = "__builtin_ia32_maxps25
	6"; break;
	case Intrinsic::x86_avx_min_pd_256: BuiltinName = "__builtin_ia32_minpd25
	6"; break;
	case Intrinsic::x86_avx_min_ps_256: BuiltinName = "__builtin_ia32_minps25
	6"; break;
	case Intrinsic::x86_avx_movmsk_pd_256: BuiltinName = "__builtin_ia32_movm
	skpd256"; break;
	case Intrinsic::x86_avx_movmsk_ps_256: BuiltinName = "__builtin_ia32_movm
	skps256"; break;
	case Intrinsic::x86_avx_movnt_dq_256: BuiltinName = "__builtin_ia32_movnt
	dq256"; break;
	case Intrinsic::x86_avx_movnt_pd_256: BuiltinName = "__builtin_ia32_movnt
	pd256"; break;
	case Intrinsic::x86_avx_movnt_ps_256: BuiltinName = "__builtin_ia32_movnt
	ps256"; break;
	case Intrinsic::x86_avx_ptestc_256: BuiltinName = "__builtin_ia32_ptestc2
	56"; break;
	case Intrinsic::x86_avx_ptestnzc_256: BuiltinName = "__builtin_ia32_ptest
	nzc256"; break;
	case Intrinsic::x86_avx_ptestz_256: BuiltinName = "__builtin_ia32_ptestz2
	56"; break;
	case Intrinsic::x86_avx_rcp_ps_256: BuiltinName = "__builtin_ia32_rcpps25
	6"; break;
	case Intrinsic::x86_avx_round_pd_256: BuiltinName = "__builtin_ia32_round
	pd256"; break;
	case Intrinsic::x86_avx_round_ps_256: BuiltinName = "__builtin_ia32_round
	ps256"; break;
	case Intrinsic::x86_avx_rsqrt_ps_256: BuiltinName = "__builtin_ia32_rsqrt
	ps256"; break;
	case Intrinsic::x86_avx_sqrt_pd_256: BuiltinName = "__builtin_ia32_sqrtpd
	256"; break;
	case Intrinsic::x86_avx_sqrt_ps_256: BuiltinName = "__builtin_ia32_sqrtps
	256"; break;
	case Intrinsic::x86_avx_storeu_dq_256: BuiltinName = "__builtin_ia32_stor
	edqu256"; break;
	case Intrinsic::x86_avx_storeu_pd_256: BuiltinName = "__builtin_ia32_stor
	eupd256"; break;
	case Intrinsic::x86_avx_storeu_ps_256: BuiltinName = "__builtin_ia32_stor
	eups256"; break;
	case Intrinsic::x86_avx_vbroadcast_sd_256: BuiltinName = "__builtin_ia32_
	vbroadcastsd256"; break;
	case Intrinsic::x86_avx_vbroadcastf128_pd_256: BuiltinName = "__builtin_i
	a32_vbroadcastf128_pd256"; break;
	case Intrinsic::x86_avx_vbroadcastf128_ps_256: BuiltinName = "__builtin_i
	a32_vbroadcastf128_ps256"; break;
	case Intrinsic::x86_avx_vbroadcastss: BuiltinName = "__builtin_ia32_vbroa
	dcastss"; break;
	case Intrinsic::x86_avx_vbroadcastss_256: BuiltinName = "__builtin_ia32_v
	broadcastss256"; break;
	case Intrinsic::x86_avx_vextractf128_pd_256: BuiltinName = "__builtin_ia3
	2_vextractf128_pd256"; break;
	case Intrinsic::x86_avx_vextractf128_ps_256: BuiltinName = "__builtin_ia3
	2_vextractf128_ps256"; break;
	case Intrinsic::x86_avx_vextractf128_si_256: BuiltinName = "__builtin_ia3
	2_vextractf128_si256"; break;
	case Intrinsic::x86_avx_vinsertf128_pd_256: BuiltinName = "__builtin_ia32
	_vinsertf128_pd256"; break;
	case Intrinsic::x86_avx_vinsertf128_ps_256: BuiltinName = "__builtin_ia32
	_vinsertf128_ps256"; break;
	case Intrinsic::x86_avx_vinsertf128_si_256: BuiltinName = "__builtin_ia32
	_vinsertf128_si256"; break;
	case Intrinsic::x86_avx_vperm2f128_pd_256: BuiltinName = "__builtin_ia32_
	vperm2f128_pd256"; break;
	case Intrinsic::x86_avx_vperm2f128_ps_256: BuiltinName = "__builtin_ia32_
	vperm2f128_ps256"; break;
	case Intrinsic::x86_avx_vperm2f128_si_256: BuiltinName = "__builtin_ia32_
	vperm2f128_si256"; break;
	case Intrinsic::x86_avx_vpermil_pd: BuiltinName = "__builtin_ia32_vpermil
	pd"; break;
	case Intrinsic::x86_avx_vpermil_pd_256: BuiltinName = "__builtin_ia32_vpe
	rmilpd256"; break;
	case Intrinsic::x86_avx_vpermil_ps: BuiltinName = "__builtin_ia32_vpermil
	ps"; break;
	case Intrinsic::x86_avx_vpermil_ps_256: BuiltinName = "__builtin_ia32_vpe
	rmilps256"; break;
	case Intrinsic::x86_avx_vpermilvar_pd: BuiltinName = "__builtin_ia32_vper
	milvarpd"; break;
	case Intrinsic::x86_avx_vpermilvar_pd_256: BuiltinName = "__builtin_ia32_
	vpermilvarpd256"; break;
	case Intrinsic::x86_avx_vpermilvar_ps: BuiltinName = "__builtin_ia32_vper
	milvarps"; break;
	case Intrinsic::x86_avx_vpermilvar_ps_256: BuiltinName = "__builtin_ia32_
	vpermilvarps256"; break;
	case Intrinsic::x86_avx_vtestc_pd: BuiltinName = "__builtin_ia32_vtestcpd
	"; break;
	case Intrinsic::x86_avx_vtestc_pd_256: BuiltinName = "__builtin_ia32_vtes
	tcpd256"; break;
	case Intrinsic::x86_avx_vtestc_ps: BuiltinName = "__builtin_ia32_vtestcps
	"; break;
	case Intrinsic::x86_avx_vtestc_ps_256: BuiltinName = "__builtin_ia32_vtes
	tcps256"; break;
	case Intrinsic::x86_avx_vtestnzc_pd: BuiltinName = "__builtin_ia32_vtestn
	zcpd"; break;
	case Intrinsic::x86_avx_vtestnzc_pd_256: BuiltinName = "__builtin_ia32_vt
	estnzcpd256"; break;
	case Intrinsic::x86_avx_vtestnzc_ps: BuiltinName = "__builtin_ia32_vtestn
	zcps"; break;
	case Intrinsic::x86_avx_vtestnzc_ps_256: BuiltinName = "__builtin_ia32_vt
	estnzcps256"; break;
	case Intrinsic::x86_avx_vtestz_pd: BuiltinName = "__builtin_ia32_vtestzpd
	"; break;
	case Intrinsic::x86_avx_vtestz_pd_256: BuiltinName = "__builtin_ia32_vtes
	tzpd256"; break;
	case Intrinsic::x86_avx_vtestz_ps: BuiltinName = "__builtin_ia32_vtestzps
	"; break;
	case Intrinsic::x86_avx_vtestz_ps_256: BuiltinName = "__builtin_ia32_vtes
	tzps256"; break;
	case Intrinsic::x86_avx_vzeroall: BuiltinName = "__builtin_ia32_vzeroall"
	; break;
	case Intrinsic::x86_avx_vzeroupper: BuiltinName = "__builtin_ia32_vzeroup
	per"; break;
	case Intrinsic::x86_mmx_emms: BuiltinName = "__builtin_ia32_emms"; break;
	case Intrinsic::x86_mmx_femms: BuiltinName = "__builtin_ia32_femms"; brea
	k;
	case Intrinsic::x86_mmx_maskmovq: BuiltinName = "__builtin_ia32_maskmovq"
	; break;
	case Intrinsic::x86_mmx_movnt_dq: BuiltinName = "__builtin_ia32_movntq";
	break;
	case Intrinsic::x86_mmx_packssdw: BuiltinName = "__builtin_ia32_packssdw"
	; break;
	case Intrinsic::x86_mmx_packsswb: BuiltinName = "__builtin_ia32_packsswb"
	; break;
	case Intrinsic::x86_mmx_packuswb: BuiltinName = "__builtin_ia32_packuswb"
	; break;
	case Intrinsic::x86_mmx_padd_b: BuiltinName = "__builtin_ia32_paddb"; bre
	ak;
	case Intrinsic::x86_mmx_padd_d: BuiltinName = "__builtin_ia32_paddd"; bre
	ak;
	case Intrinsic::x86_mmx_padd_q: BuiltinName = "__builtin_ia32_paddq"; bre
	ak;
	case Intrinsic::x86_mmx_padd_w: BuiltinName = "__builtin_ia32_paddw"; bre
	ak;
	case Intrinsic::x86_mmx_padds_b: BuiltinName = "__builtin_ia32_paddsb"; b
	reak;
	case Intrinsic::x86_mmx_padds_w: BuiltinName = "__builtin_ia32_paddsw"; b
	reak;
	case Intrinsic::x86_mmx_paddus_b: BuiltinName = "__builtin_ia32_paddusb";
	break;
	case Intrinsic::x86_mmx_paddus_w: BuiltinName = "__builtin_ia32_paddusw";
	break;
	case Intrinsic::x86_mmx_palignr_b: BuiltinName = "__builtin_ia32_palignr"
	; break;
	case Intrinsic::x86_mmx_pand: BuiltinName = "__builtin_ia32_pand"; break;
	case Intrinsic::x86_mmx_pandn: BuiltinName = "__builtin_ia32_pandn"; brea
	k;
	case Intrinsic::x86_mmx_pavg_b: BuiltinName = "__builtin_ia32_pavgb"; bre
	ak;
	case Intrinsic::x86_mmx_pavg_w: BuiltinName = "__builtin_ia32_pavgw"; bre
	ak;
	case Intrinsic::x86_mmx_pcmpeq_b: BuiltinName = "__builtin_ia32_pcmpeqb";
	break;
	case Intrinsic::x86_mmx_pcmpeq_d: BuiltinName = "__builtin_ia32_pcmpeqd";
	break;
	case Intrinsic::x86_mmx_pcmpeq_w: BuiltinName = "__builtin_ia32_pcmpeqw";
	break;
	case Intrinsic::x86_mmx_pcmpgt_b: BuiltinName = "__builtin_ia32_pcmpgtb";
	break;
	case Intrinsic::x86_mmx_pcmpgt_d: BuiltinName = "__builtin_ia32_pcmpgtd";
	break;
	case Intrinsic::x86_mmx_pcmpgt_w: BuiltinName = "__builtin_ia32_pcmpgtw";
	break;
	case Intrinsic::x86_mmx_pextr_w: BuiltinName = "__builtin_ia32_vec_ext_v4
	hi"; break;
	case Intrinsic::x86_mmx_pinsr_w: BuiltinName = "__builtin_ia32_vec_set_v4
	hi"; break;
	case Intrinsic::x86_mmx_pmadd_wd: BuiltinName = "__builtin_ia32_pmaddwd";
	break;
	case Intrinsic::x86_mmx_pmaxs_w: BuiltinName = "__builtin_ia32_pmaxsw"; b
	reak;
	case Intrinsic::x86_mmx_pmaxu_b: BuiltinName = "__builtin_ia32_pmaxub"; b
	reak;
	case Intrinsic::x86_mmx_pmins_w: BuiltinName = "__builtin_ia32_pminsw"; b
	reak;
	case Intrinsic::x86_mmx_pminu_b: BuiltinName = "__builtin_ia32_pminub"; b
	reak;
	case Intrinsic::x86_mmx_pmovmskb: BuiltinName = "__builtin_ia32_pmovmskb"
	; break;
	case Intrinsic::x86_mmx_pmulh_w: BuiltinName = "__builtin_ia32_pmulhw"; b
	reak;
	case Intrinsic::x86_mmx_pmulhu_w: BuiltinName = "__builtin_ia32_pmulhuw";
	break;
	case Intrinsic::x86_mmx_pmull_w: BuiltinName = "__builtin_ia32_pmullw"; b
	reak;
	case Intrinsic::x86_mmx_pmulu_dq: BuiltinName = "__builtin_ia32_pmuludq";
	break;
	case Intrinsic::x86_mmx_por: BuiltinName = "__builtin_ia32_por"; break;
	case Intrinsic::x86_mmx_psad_bw: BuiltinName = "__builtin_ia32_psadbw"; b
	reak;
	case Intrinsic::x86_mmx_psll_d: BuiltinName = "__builtin_ia32_pslld"; bre
	ak;
	case Intrinsic::x86_mmx_psll_q: BuiltinName = "__builtin_ia32_psllq"; bre
	ak;
	case Intrinsic::x86_mmx_psll_w: BuiltinName = "__builtin_ia32_psllw"; bre
	ak;
	case Intrinsic::x86_mmx_pslli_d: BuiltinName = "__builtin_ia32_pslldi"; b
	reak;
	case Intrinsic::x86_mmx_pslli_q: BuiltinName = "__builtin_ia32_psllqi"; b
	reak;
	case Intrinsic::x86_mmx_pslli_w: BuiltinName = "__builtin_ia32_psllwi"; b
	reak;
	case Intrinsic::x86_mmx_psra_d: BuiltinName = "__builtin_ia32_psrad"; bre
	ak;
	case Intrinsic::x86_mmx_psra_w: BuiltinName = "__builtin_ia32_psraw"; bre
	ak;
	case Intrinsic::x86_mmx_psrai_d: BuiltinName = "__builtin_ia32_psradi"; b
	reak;
	case Intrinsic::x86_mmx_psrai_w: BuiltinName = "__builtin_ia32_psrawi"; b
	reak;
	case Intrinsic::x86_mmx_psrl_d: BuiltinName = "__builtin_ia32_psrld"; bre
	ak;
	case Intrinsic::x86_mmx_psrl_q: BuiltinName = "__builtin_ia32_psrlq"; bre
	ak;
	case Intrinsic::x86_mmx_psrl_w: BuiltinName = "__builtin_ia32_psrlw"; bre
	ak;
	case Intrinsic::x86_mmx_psrli_d: BuiltinName = "__builtin_ia32_psrldi"; b
	reak;
	case Intrinsic::x86_mmx_psrli_q: BuiltinName = "__builtin_ia32_psrlqi"; b
	reak;
	case Intrinsic::x86_mmx_psrli_w: BuiltinName = "__builtin_ia32_psrlwi"; b
	reak;
	case Intrinsic::x86_mmx_psub_b: BuiltinName = "__builtin_ia32_psubb"; bre
	ak;
	case Intrinsic::x86_mmx_psub_d: BuiltinName = "__builtin_ia32_psubd"; bre
	ak;
	case Intrinsic::x86_mmx_psub_q: BuiltinName = "__builtin_ia32_psubq"; bre
	ak;
	case Intrinsic::x86_mmx_psub_w: BuiltinName = "__builtin_ia32_psubw"; bre
	ak;
	case Intrinsic::x86_mmx_psubs_b: BuiltinName = "__builtin_ia32_psubsb"; b
	reak;
	case Intrinsic::x86_mmx_psubs_w: BuiltinName = "__builtin_ia32_psubsw"; b
	reak;
	case Intrinsic::x86_mmx_psubus_b: BuiltinName = "__builtin_ia32_psubusb";
	break;
	case Intrinsic::x86_mmx_psubus_w: BuiltinName = "__builtin_ia32_psubusw";
	break;
	case Intrinsic::x86_mmx_punpckhbw: BuiltinName = "__builtin_ia32_punpckhb
	w"; break;
	case Intrinsic::x86_mmx_punpckhdq: BuiltinName = "__builtin_ia32_punpckhd
	q"; break;
	case Intrinsic::x86_mmx_punpckhwd: BuiltinName = "__builtin_ia32_punpckhw
	d"; break;
	case Intrinsic::x86_mmx_punpcklbw: BuiltinName = "__builtin_ia32_punpcklb
	w"; break;
	case Intrinsic::x86_mmx_punpckldq: BuiltinName = "__builtin_ia32_punpckld
	q"; break;
	case Intrinsic::x86_mmx_punpcklwd: BuiltinName = "__builtin_ia32_punpcklw
	d"; break;
	case Intrinsic::x86_mmx_pxor: BuiltinName = "__builtin_ia32_pxor"; break;
	case Intrinsic::x86_sse2_add_sd: BuiltinName = "__builtin_ia32_addsd"; br
	eak;
	case Intrinsic::x86_sse2_clflush: BuiltinName = "__builtin_ia32_clflush";
	break;
	case Intrinsic::x86_sse2_comieq_sd: BuiltinName = "__builtin_ia32_comisde
	q"; break;
	case Intrinsic::x86_sse2_comige_sd: BuiltinName = "__builtin_ia32_comisdg
	e"; break;
	case Intrinsic::x86_sse2_comigt_sd: BuiltinName = "__builtin_ia32_comisdg
	t"; break;
	case Intrinsic::x86_sse2_comile_sd: BuiltinName = "__builtin_ia32_comisdl
	e"; break;
	case Intrinsic::x86_sse2_comilt_sd: BuiltinName = "__builtin_ia32_comisdl
	t"; break;
	case Intrinsic::x86_sse2_comineq_sd: BuiltinName = "__builtin_ia32_comisd
	neq"; break;
	case Intrinsic::x86_sse2_cvtdq2pd: BuiltinName = "__builtin_ia32_cvtdq2pd
	"; break;
	case Intrinsic::x86_sse2_cvtdq2ps: BuiltinName = "__builtin_ia32_cvtdq2ps
	"; break;
	case Intrinsic::x86_sse2_cvtpd2dq: BuiltinName = "__builtin_ia32_cvtpd2dq
	"; break;
	case Intrinsic::x86_sse2_cvtpd2ps: BuiltinName = "__builtin_ia32_cvtpd2ps
	"; break;
	case Intrinsic::x86_sse2_cvtps2dq: BuiltinName = "__builtin_ia32_cvtps2dq
	"; break;
	case Intrinsic::x86_sse2_cvtps2pd: BuiltinName = "__builtin_ia32_cvtps2pd
	"; break;
	case Intrinsic::x86_sse2_cvtsd2si: BuiltinName = "__builtin_ia32_cvtsd2si
	"; break;
	case Intrinsic::x86_sse2_cvtsd2si64: BuiltinName = "__builtin_ia32_cvtsd2
	si64"; break;
	case Intrinsic::x86_sse2_cvtsd2ss: BuiltinName = "__builtin_ia32_cvtsd2ss
	"; break;
	case Intrinsic::x86_sse2_cvtsi2sd: BuiltinName = "__builtin_ia32_cvtsi2sd
	"; break;
	case Intrinsic::x86_sse2_cvtsi642sd: BuiltinName = "__builtin_ia32_cvtsi6
	42sd"; break;
	case Intrinsic::x86_sse2_cvtss2sd: BuiltinName = "__builtin_ia32_cvtss2sd
	"; break;
	case Intrinsic::x86_sse2_cvttpd2dq: BuiltinName = "__builtin_ia32_cvttpd2
	dq"; break;
	case Intrinsic::x86_sse2_cvttps2dq: BuiltinName = "__builtin_ia32_cvttps2
	dq"; break;
	case Intrinsic::x86_sse2_cvttsd2si: BuiltinName = "__builtin_ia32_cvttsd2
	si"; break;
	case Intrinsic::x86_sse2_cvttsd2si64: BuiltinName = "__builtin_ia32_cvtts
	d2si64"; break;
	case Intrinsic::x86_sse2_div_sd: BuiltinName = "__builtin_ia32_divsd"; br
	eak;
	case Intrinsic::x86_sse2_lfence: BuiltinName = "__builtin_ia32_lfence"; b
	reak;
	case Intrinsic::x86_sse2_maskmov_dqu: BuiltinName = "__builtin_ia32_maskm
	ovdqu"; break;
	case Intrinsic::x86_sse2_max_pd: BuiltinName = "__builtin_ia32_maxpd"; br
	eak;
	case Intrinsic::x86_sse2_max_sd: BuiltinName = "__builtin_ia32_maxsd"; br
	eak;
	case Intrinsic::x86_sse2_mfence: BuiltinName = "__builtin_ia32_mfence"; b
	reak;
	case Intrinsic::x86_sse2_min_pd: BuiltinName = "__builtin_ia32_minpd"; br
	eak;
	case Intrinsic::x86_sse2_min_sd: BuiltinName = "__builtin_ia32_minsd"; br
	eak;
	case Intrinsic::x86_sse2_movmsk_pd: BuiltinName = "__builtin_ia32_movmskp
	d"; break;
	case Intrinsic::x86_sse2_mul_sd: BuiltinName = "__builtin_ia32_mulsd"; br
	eak;
	case Intrinsic::x86_sse2_packssdw_128: BuiltinName = "__builtin_ia32_pack
	ssdw128"; break;
	case Intrinsic::x86_sse2_packsswb_128: BuiltinName = "__builtin_ia32_pack
	sswb128"; break;
	case Intrinsic::x86_sse2_packuswb_128: BuiltinName = "__builtin_ia32_pack
	uswb128"; break;
	case Intrinsic::x86_sse2_padds_b: BuiltinName = "__builtin_ia32_paddsb128
	"; break;
	case Intrinsic::x86_sse2_padds_w: BuiltinName = "__builtin_ia32_paddsw128
	"; break;
	case Intrinsic::x86_sse2_paddus_b: BuiltinName = "__builtin_ia32_paddusb1
	28"; break;
	case Intrinsic::x86_sse2_paddus_w: BuiltinName = "__builtin_ia32_paddusw1
	28"; break;
	case Intrinsic::x86_sse2_pavg_b: BuiltinName = "__builtin_ia32_pavgb128";
	break;
	case Intrinsic::x86_sse2_pavg_w: BuiltinName = "__builtin_ia32_pavgw128";
	break;
	case Intrinsic::x86_sse2_pcmpeq_b: BuiltinName = "__builtin_ia32_pcmpeqb1
	28"; break;
	case Intrinsic::x86_sse2_pcmpeq_d: BuiltinName = "__builtin_ia32_pcmpeqd1
	28"; break;
	case Intrinsic::x86_sse2_pcmpeq_w: BuiltinName = "__builtin_ia32_pcmpeqw1
	28"; break;
	case Intrinsic::x86_sse2_pcmpgt_b: BuiltinName = "__builtin_ia32_pcmpgtb1
	28"; break;
	case Intrinsic::x86_sse2_pcmpgt_d: BuiltinName = "__builtin_ia32_pcmpgtd1
	28"; break;
	case Intrinsic::x86_sse2_pcmpgt_w: BuiltinName = "__builtin_ia32_pcmpgtw1
	28"; break;
	case Intrinsic::x86_sse2_pmadd_wd: BuiltinName = "__builtin_ia32_pmaddwd1
	28"; break;
	case Intrinsic::x86_sse2_pmaxs_w: BuiltinName = "__builtin_ia32_pmaxsw128
	"; break;
	case Intrinsic::x86_sse2_pmaxu_b: BuiltinName = "__builtin_ia32_pmaxub128
	"; break;
	case Intrinsic::x86_sse2_pmins_w: BuiltinName = "__builtin_ia32_pminsw128
	"; break;
	case Intrinsic::x86_sse2_pminu_b: BuiltinName = "__builtin_ia32_pminub128
	"; break;
	case Intrinsic::x86_sse2_pmovmskb_128: BuiltinName = "__builtin_ia32_pmov
	mskb128"; break;
	case Intrinsic::x86_sse2_pmulh_w: BuiltinName = "__builtin_ia32_pmulhw128
	"; break;
	case Intrinsic::x86_sse2_pmulhu_w: BuiltinName = "__builtin_ia32_pmulhuw1
	28"; break;
	case Intrinsic::x86_sse2_pmulu_dq: BuiltinName = "__builtin_ia32_pmuludq1
	28"; break;
	case Intrinsic::x86_sse2_psad_bw: BuiltinName = "__builtin_ia32_psadbw128
	"; break;
	case Intrinsic::x86_sse2_psll_d: BuiltinName = "__builtin_ia32_pslld128";
	break;
	case Intrinsic::x86_sse2_psll_dq: BuiltinName = "__builtin_ia32_pslldqi12
	8"; break;
	case Intrinsic::x86_sse2_psll_dq_bs: BuiltinName = "__builtin_ia32_pslldq
	i128_byteshift"; break;
	case Intrinsic::x86_sse2_psll_q: BuiltinName = "__builtin_ia32_psllq128";
	break;
	case Intrinsic::x86_sse2_psll_w: BuiltinName = "__builtin_ia32_psllw128";
	break;
	case Intrinsic::x86_sse2_pslli_d: BuiltinName = "__builtin_ia32_pslldi128
	"; break;
	case Intrinsic::x86_sse2_pslli_q: BuiltinName = "__builtin_ia32_psllqi128
	"; break;
	case Intrinsic::x86_sse2_pslli_w: BuiltinName = "__builtin_ia32_psllwi128
	"; break;
	case Intrinsic::x86_sse2_psra_d: BuiltinName = "__builtin_ia32_psrad128";
	break;
	case Intrinsic::x86_sse2_psra_w: BuiltinName = "__builtin_ia32_psraw128";
	break;
	case Intrinsic::x86_sse2_psrai_d: BuiltinName = "__builtin_ia32_psradi128
	"; break;
	case Intrinsic::x86_sse2_psrai_w: BuiltinName = "__builtin_ia32_psrawi128
	"; break;
	case Intrinsic::x86_sse2_psrl_d: BuiltinName = "__builtin_ia32_psrld128";
	break;
	case Intrinsic::x86_sse2_psrl_dq: BuiltinName = "__builtin_ia32_psrldqi12
	8"; break;
	case Intrinsic::x86_sse2_psrl_dq_bs: BuiltinName = "__builtin_ia32_psrldq
	i128_byteshift"; break;
	case Intrinsic::x86_sse2_psrl_q: BuiltinName = "__builtin_ia32_psrlq128";
	break;
	case Intrinsic::x86_sse2_psrl_w: BuiltinName = "__builtin_ia32_psrlw128";
	break;
	case Intrinsic::x86_sse2_psrli_d: BuiltinName = "__builtin_ia32_psrldi128
	"; break;
	case Intrinsic::x86_sse2_psrli_q: BuiltinName = "__builtin_ia32_psrlqi128
	"; break;
	case Intrinsic::x86_sse2_psrli_w: BuiltinName = "__builtin_ia32_psrlwi128
	"; break;
	case Intrinsic::x86_sse2_psubs_b: BuiltinName = "__builtin_ia32_psubsb128
	"; break;
	case Intrinsic::x86_sse2_psubs_w: BuiltinName = "__builtin_ia32_psubsw128
	"; break;
	case Intrinsic::x86_sse2_psubus_b: BuiltinName = "__builtin_ia32_psubusb1
	28"; break;
	case Intrinsic::x86_sse2_psubus_w: BuiltinName = "__builtin_ia32_psubusw1
	28"; break;
	case Intrinsic::x86_sse2_sqrt_pd: BuiltinName = "__builtin_ia32_sqrtpd";
	break;
	case Intrinsic::x86_sse2_sqrt_sd: BuiltinName = "__builtin_ia32_sqrtsd";
	break;
	case Intrinsic::x86_sse2_storel_dq: BuiltinName = "__builtin_ia32_storelv
	4si"; break;
	case Intrinsic::x86_sse2_storeu_dq: BuiltinName = "__builtin_ia32_storedq
	u"; break;
	case Intrinsic::x86_sse2_storeu_pd: BuiltinName = "__builtin_ia32_storeup
	d"; break;
	case Intrinsic::x86_sse2_sub_sd: BuiltinName = "__builtin_ia32_subsd"; br
	eak;
	case Intrinsic::x86_sse2_ucomieq_sd: BuiltinName = "__builtin_ia32_ucomis
	deq"; break;
	case Intrinsic::x86_sse2_ucomige_sd: BuiltinName = "__builtin_ia32_ucomis
	dge"; break;
	case Intrinsic::x86_sse2_ucomigt_sd: BuiltinName = "__builtin_ia32_ucomis
	dgt"; break;
	case Intrinsic::x86_sse2_ucomile_sd: BuiltinName = "__builtin_ia32_ucomis
	dle"; break;
	case Intrinsic::x86_sse2_ucomilt_sd: BuiltinName = "__builtin_ia32_ucomis
	dlt"; break;
	case Intrinsic::x86_sse2_ucomineq_sd: BuiltinName = "__builtin_ia32_ucomi
	sdneq"; break;
	case Intrinsic::x86_sse3_addsub_pd: BuiltinName = "__builtin_ia32_addsubp
	d"; break;
	case Intrinsic::x86_sse3_addsub_ps: BuiltinName = "__builtin_ia32_addsubp
	s"; break;
	case Intrinsic::x86_sse3_hadd_pd: BuiltinName = "__builtin_ia32_haddpd";
	break;
	case Intrinsic::x86_sse3_hadd_ps: BuiltinName = "__builtin_ia32_haddps";
	break;
	case Intrinsic::x86_sse3_hsub_pd: BuiltinName = "__builtin_ia32_hsubpd";
	break;
	case Intrinsic::x86_sse3_hsub_ps: BuiltinName = "__builtin_ia32_hsubps";
	break;
	case Intrinsic::x86_sse3_ldu_dq: BuiltinName = "__builtin_ia32_lddqu"; br
	eak;
	case Intrinsic::x86_sse3_monitor: BuiltinName = "__builtin_ia32_monitor";
	break;
	case Intrinsic::x86_sse3_mwait: BuiltinName = "__builtin_ia32_mwait"; bre
	ak;
	case Intrinsic::x86_sse41_blendpd: BuiltinName = "__builtin_ia32_blendpd"
	; break;
	case Intrinsic::x86_sse41_blendps: BuiltinName = "__builtin_ia32_blendps"
	; break;
	case Intrinsic::x86_sse41_blendvpd: BuiltinName = "__builtin_ia32_blendvp
	d"; break;
	case Intrinsic::x86_sse41_blendvps: BuiltinName = "__builtin_ia32_blendvp
	s"; break;
	case Intrinsic::x86_sse41_dppd: BuiltinName = "__builtin_ia32_dppd"; brea
	k;
	case Intrinsic::x86_sse41_dpps: BuiltinName = "__builtin_ia32_dpps"; brea
	k;
	case Intrinsic::x86_sse41_extractps: BuiltinName = "__builtin_ia32_extrac
	tps128"; break;
	case Intrinsic::x86_sse41_insertps: BuiltinName = "__builtin_ia32_insertp
	s128"; break;
	case Intrinsic::x86_sse41_movntdqa: BuiltinName = "__builtin_ia32_movntdq
	a"; break;
	case Intrinsic::x86_sse41_mpsadbw: BuiltinName = "__builtin_ia32_mpsadbw1
	28"; break;
	case Intrinsic::x86_sse41_packusdw: BuiltinName = "__builtin_ia32_packusd
	w128"; break;
	case Intrinsic::x86_sse41_pblendvb: BuiltinName = "__builtin_ia32_pblendv
	b128"; break;
	case Intrinsic::x86_sse41_pblendw: BuiltinName = "__builtin_ia32_pblendw1
	28"; break;
	case Intrinsic::x86_sse41_pcmpeqq: BuiltinName = "__builtin_ia32_pcmpeqq"
	; break;
	case Intrinsic::x86_sse41_phminposuw: BuiltinName = "__builtin_ia32_phmin
	posuw128"; break;
	case Intrinsic::x86_sse41_pmaxsb: BuiltinName = "__builtin_ia32_pmaxsb128
	"; break;
	case Intrinsic::x86_sse41_pmaxsd: BuiltinName = "__builtin_ia32_pmaxsd128
	"; break;
	case Intrinsic::x86_sse41_pmaxud: BuiltinName = "__builtin_ia32_pmaxud128
	"; break;
	case Intrinsic::x86_sse41_pmaxuw: BuiltinName = "__builtin_ia32_pmaxuw128
	"; break;
	case Intrinsic::x86_sse41_pminsb: BuiltinName = "__builtin_ia32_pminsb128
	"; break;
	case Intrinsic::x86_sse41_pminsd: BuiltinName = "__builtin_ia32_pminsd128
	"; break;
	case Intrinsic::x86_sse41_pminud: BuiltinName = "__builtin_ia32_pminud128
	"; break;
	case Intrinsic::x86_sse41_pminuw: BuiltinName = "__builtin_ia32_pminuw128
	"; break;
	case Intrinsic::x86_sse41_pmovsxbd: BuiltinName = "__builtin_ia32_pmovsxb
	d128"; break;
	case Intrinsic::x86_sse41_pmovsxbq: BuiltinName = "__builtin_ia32_pmovsxb
	q128"; break;
	case Intrinsic::x86_sse41_pmovsxbw: BuiltinName = "__builtin_ia32_pmovsxb
	w128"; break;
	case Intrinsic::x86_sse41_pmovsxdq: BuiltinName = "__builtin_ia32_pmovsxd
	q128"; break;
	case Intrinsic::x86_sse41_pmovsxwd: BuiltinName = "__builtin_ia32_pmovsxw
	d128"; break;
	case Intrinsic::x86_sse41_pmovsxwq: BuiltinName = "__builtin_ia32_pmovsxw
	q128"; break;
	case Intrinsic::x86_sse41_pmovzxbd: BuiltinName = "__builtin_ia32_pmovzxb
	d128"; break;
	case Intrinsic::x86_sse41_pmovzxbq: BuiltinName = "__builtin_ia32_pmovzxb
	q128"; break;
	case Intrinsic::x86_sse41_pmovzxbw: BuiltinName = "__builtin_ia32_pmovzxb
	w128"; break;
	case Intrinsic::x86_sse41_pmovzxdq: BuiltinName = "__builtin_ia32_pmovzxd
	q128"; break;
	case Intrinsic::x86_sse41_pmovzxwd: BuiltinName = "__builtin_ia32_pmovzxw
	d128"; break;
	case Intrinsic::x86_sse41_pmovzxwq: BuiltinName = "__builtin_ia32_pmovzxw
	q128"; break;
	case Intrinsic::x86_sse41_pmuldq: BuiltinName = "__builtin_ia32_pmuldq128
	"; break;
	case Intrinsic::x86_sse41_ptestc: BuiltinName = "__builtin_ia32_ptestc128
	"; break;
	case Intrinsic::x86_sse41_ptestnzc: BuiltinName = "__builtin_ia32_ptestnz
	c128"; break;
	case Intrinsic::x86_sse41_ptestz: BuiltinName = "__builtin_ia32_ptestz128
	"; break;
	case Intrinsic::x86_sse41_round_pd: BuiltinName = "__builtin_ia32_roundpd
	"; break;
	case Intrinsic::x86_sse41_round_ps: BuiltinName = "__builtin_ia32_roundps
	"; break;
	case Intrinsic::x86_sse41_round_sd: BuiltinName = "__builtin_ia32_roundsd
	"; break;
	case Intrinsic::x86_sse41_round_ss: BuiltinName = "__builtin_ia32_roundss
	"; break;
	case Intrinsic::x86_sse42_crc32_32_16: BuiltinName = "__builtin_ia32_crc3
	2hi"; break;
	case Intrinsic::x86_sse42_crc32_32_32: BuiltinName = "__builtin_ia32_crc3
	2si"; break;
	case Intrinsic::x86_sse42_crc32_32_8: BuiltinName = "__builtin_ia32_crc32
	qi"; break;
	case Intrinsic::x86_sse42_crc32_64_64: BuiltinName = "__builtin_ia32_crc3
	2di"; break;
	case Intrinsic::x86_sse42_pcmpestri128: BuiltinName = "__builtin_ia32_pcm
	pestri128"; break;
	case Intrinsic::x86_sse42_pcmpestria128: BuiltinName = "__builtin_ia32_pc
	mpestria128"; break;
	case Intrinsic::x86_sse42_pcmpestric128: BuiltinName = "__builtin_ia32_pc
	mpestric128"; break;
	case Intrinsic::x86_sse42_pcmpestrio128: BuiltinName = "__builtin_ia32_pc
	mpestrio128"; break;
	case Intrinsic::x86_sse42_pcmpestris128: BuiltinName = "__builtin_ia32_pc
	mpestris128"; break;
	case Intrinsic::x86_sse42_pcmpestriz128: BuiltinName = "__builtin_ia32_pc
	mpestriz128"; break;
	case Intrinsic::x86_sse42_pcmpestrm128: BuiltinName = "__builtin_ia32_pcm
	pestrm128"; break;
	case Intrinsic::x86_sse42_pcmpgtq: BuiltinName = "__builtin_ia32_pcmpgtq"
	; break;
	case Intrinsic::x86_sse42_pcmpistri128: BuiltinName = "__builtin_ia32_pcm
	pistri128"; break;
	case Intrinsic::x86_sse42_pcmpistria128: BuiltinName = "__builtin_ia32_pc
	mpistria128"; break;
	case Intrinsic::x86_sse42_pcmpistric128: BuiltinName = "__builtin_ia32_pc
	mpistric128"; break;
	case Intrinsic::x86_sse42_pcmpistrio128: BuiltinName = "__builtin_ia32_pc
	mpistrio128"; break;
	case Intrinsic::x86_sse42_pcmpistris128: BuiltinName = "__builtin_ia32_pc
	mpistris128"; break;
	case Intrinsic::x86_sse42_pcmpistriz128: BuiltinName = "__builtin_ia32_pc
	mpistriz128"; break;
	case Intrinsic::x86_sse42_pcmpistrm128: BuiltinName = "__builtin_ia32_pcm
	pistrm128"; break;
	case Intrinsic::x86_sse_add_ss: BuiltinName = "__builtin_ia32_addss"; bre
	ak;
	case Intrinsic::x86_sse_comieq_ss: BuiltinName = "__builtin_ia32_comieq";
	break;
	case Intrinsic::x86_sse_comige_ss: BuiltinName = "__builtin_ia32_comige";
	break;
	case Intrinsic::x86_sse_comigt_ss: BuiltinName = "__builtin_ia32_comigt";
	break;
	case Intrinsic::x86_sse_comile_ss: BuiltinName = "__builtin_ia32_comile";
	break;
	case Intrinsic::x86_sse_comilt_ss: BuiltinName = "__builtin_ia32_comilt";
	break;
	case Intrinsic::x86_sse_comineq_ss: BuiltinName = "__builtin_ia32_comineq
	"; break;
	case Intrinsic::x86_sse_cvtpd2pi: BuiltinName = "__builtin_ia32_cvtpd2pi"
	; break;
	case Intrinsic::x86_sse_cvtpi2pd: BuiltinName = "__builtin_ia32_cvtpi2pd"
	; break;
	case Intrinsic::x86_sse_cvtpi2ps: BuiltinName = "__builtin_ia32_cvtpi2ps"
	; break;
	case Intrinsic::x86_sse_cvtps2pi: BuiltinName = "__builtin_ia32_cvtps2pi"
	; break;
	case Intrinsic::x86_sse_cvtsi2ss: BuiltinName = "__builtin_ia32_cvtsi2ss"
	; break;
	case Intrinsic::x86_sse_cvtsi642ss: BuiltinName = "__builtin_ia32_cvtsi64
	2ss"; break;
	case Intrinsic::x86_sse_cvtss2si: BuiltinName = "__builtin_ia32_cvtss2si"
	; break;
	case Intrinsic::x86_sse_cvtss2si64: BuiltinName = "__builtin_ia32_cvtss2s
	i64"; break;
	case Intrinsic::x86_sse_cvttpd2pi: BuiltinName = "__builtin_ia32_cvttpd2p
	i"; break;
	case Intrinsic::x86_sse_cvttps2pi: BuiltinName = "__builtin_ia32_cvttps2p
	i"; break;
	case Intrinsic::x86_sse_cvttss2si: BuiltinName = "__builtin_ia32_cvttss2s
	i"; break;
	case Intrinsic::x86_sse_cvttss2si64: BuiltinName = "__builtin_ia32_cvttss
	2si64"; break;
	case Intrinsic::x86_sse_div_ss: BuiltinName = "__builtin_ia32_divss"; bre
	ak;
	case Intrinsic::x86_sse_max_ps: BuiltinName = "__builtin_ia32_maxps"; bre
	ak;
	case Intrinsic::x86_sse_max_ss: BuiltinName = "__builtin_ia32_maxss"; bre
	ak;
	case Intrinsic::x86_sse_min_ps: BuiltinName = "__builtin_ia32_minps"; bre
	ak;
	case Intrinsic::x86_sse_min_ss: BuiltinName = "__builtin_ia32_minss"; bre
	ak;
	case Intrinsic::x86_sse_movmsk_ps: BuiltinName = "__builtin_ia32_movmskps
	"; break;
	case Intrinsic::x86_sse_mul_ss: BuiltinName = "__builtin_ia32_mulss"; bre
	ak;
	case Intrinsic::x86_sse_pshuf_w: BuiltinName = "__builtin_ia32_pshufw"; b
	reak;
	case Intrinsic::x86_sse_rcp_ps: BuiltinName = "__builtin_ia32_rcpps"; bre
	ak;
	case Intrinsic::x86_sse_rcp_ss: BuiltinName = "__builtin_ia32_rcpss"; bre
	ak;
	case Intrinsic::x86_sse_rsqrt_ps: BuiltinName = "__builtin_ia32_rsqrtps";
	break;
	case Intrinsic::x86_sse_rsqrt_ss: BuiltinName = "__builtin_ia32_rsqrtss";
	break;
	case Intrinsic::x86_sse_sfence: BuiltinName = "__builtin_ia32_sfence"; br
	eak;
	case Intrinsic::x86_sse_sqrt_ps: BuiltinName = "__builtin_ia32_sqrtps"; b
	reak;
	case Intrinsic::x86_sse_sqrt_ss: BuiltinName = "__builtin_ia32_sqrtss"; b
	reak;
	case Intrinsic::x86_sse_storeu_ps: BuiltinName = "__builtin_ia32_storeups
	"; break;
	case Intrinsic::x86_sse_sub_ss: BuiltinName = "__builtin_ia32_subss"; bre
	ak;
	case Intrinsic::x86_sse_ucomieq_ss: BuiltinName = "__builtin_ia32_ucomieq
	"; break;
	case Intrinsic::x86_sse_ucomige_ss: BuiltinName = "__builtin_ia32_ucomige
	"; break;
	case Intrinsic::x86_sse_ucomigt_ss: BuiltinName = "__builtin_ia32_ucomigt
	"; break;
	case Intrinsic::x86_sse_ucomile_ss: BuiltinName = "__builtin_ia32_ucomile
	"; break;
	case Intrinsic::x86_sse_ucomilt_ss: BuiltinName = "__builtin_ia32_ucomilt
	"; break;
	case Intrinsic::x86_sse_ucomineq_ss: BuiltinName = "__builtin_ia32_ucomin
	eq"; break;
	case Intrinsic::x86_ssse3_pabs_b: BuiltinName = "__builtin_ia32_pabsb"; b
	reak;
	case Intrinsic::x86_ssse3_pabs_b_128: BuiltinName = "__builtin_ia32_pabsb
	128"; break;
	case Intrinsic::x86_ssse3_pabs_d: BuiltinName = "__builtin_ia32_pabsd"; b
	reak;
	case Intrinsic::x86_ssse3_pabs_d_128: BuiltinName = "__builtin_ia32_pabsd
	128"; break;
	case Intrinsic::x86_ssse3_pabs_w: BuiltinName = "__builtin_ia32_pabsw"; b
	reak;
	case Intrinsic::x86_ssse3_pabs_w_128: BuiltinName = "__builtin_ia32_pabsw
	128"; break;
	case Intrinsic::x86_ssse3_phadd_d: BuiltinName = "__builtin_ia32_phaddd";
	break;
	case Intrinsic::x86_ssse3_phadd_d_128: BuiltinName = "__builtin_ia32_phad
	dd128"; break;
	case Intrinsic::x86_ssse3_phadd_sw: BuiltinName = "__builtin_ia32_phaddsw
	"; break;
	case Intrinsic::x86_ssse3_phadd_sw_128: BuiltinName = "__builtin_ia32_pha
	ddsw128"; break;
	case Intrinsic::x86_ssse3_phadd_w: BuiltinName = "__builtin_ia32_phaddw";
	break;
	case Intrinsic::x86_ssse3_phadd_w_128: BuiltinName = "__builtin_ia32_phad
	dw128"; break;
	case Intrinsic::x86_ssse3_phsub_d: BuiltinName = "__builtin_ia32_phsubd";
	break;
	case Intrinsic::x86_ssse3_phsub_d_128: BuiltinName = "__builtin_ia32_phsu
	bd128"; break;
	case Intrinsic::x86_ssse3_phsub_sw: BuiltinName = "__builtin_ia32_phsubsw
	"; break;
	case Intrinsic::x86_ssse3_phsub_sw_128: BuiltinName = "__builtin_ia32_phs
	ubsw128"; break;
	case Intrinsic::x86_ssse3_phsub_w: BuiltinName = "__builtin_ia32_phsubw";
	break;
	case Intrinsic::x86_ssse3_phsub_w_128: BuiltinName = "__builtin_ia32_phsu
	bw128"; break;
	case Intrinsic::x86_ssse3_pmadd_ub_sw: BuiltinName = "__builtin_ia32_pmad
	dubsw"; break;
	case Intrinsic::x86_ssse3_pmadd_ub_sw_128: BuiltinName = "__builtin_ia32_
	pmaddubsw128"; break;
	case Intrinsic::x86_ssse3_pmul_hr_sw: BuiltinName = "__builtin_ia32_pmulh
	rsw"; break;
	case Intrinsic::x86_ssse3_pmul_hr_sw_128: BuiltinName = "__builtin_ia32_p
	mulhrsw128"; break;
	case Intrinsic::x86_ssse3_pshuf_b: BuiltinName = "__builtin_ia32_pshufb";
	break;
	case Intrinsic::x86_ssse3_pshuf_b_128: BuiltinName = "__builtin_ia32_pshu
	fb128"; break;
	case Intrinsic::x86_ssse3_psign_b: BuiltinName = "__builtin_ia32_psignb";
	break;
	case Intrinsic::x86_ssse3_psign_b_128: BuiltinName = "__builtin_ia32_psig
	nb128"; break;
	case Intrinsic::x86_ssse3_psign_d: BuiltinName = "__builtin_ia32_psignd";
	break;
	case Intrinsic::x86_ssse3_psign_d_128: BuiltinName = "__builtin_ia32_psig
	nd128"; break;
	case Intrinsic::x86_ssse3_psign_w: BuiltinName = "__builtin_ia32_psignw";
	break;
	case Intrinsic::x86_ssse3_psign_w_128: BuiltinName = "__builtin_ia32_psig
	nw128"; break;
	}
	#endif

	// Get the LLVM intrinsic that corresponds to a GCC builtin.
	// This is used by the C front-end. The GCC builtin name is passed
	// in as BuiltinName, and a target prefix (e.g. 'ppc') is passed
	// in as TargetPrefix. The result is assigned to 'IntrinsicID'.
	#ifdef GET_LLVM_INTRINSIC_FOR_GCC_BUILTIN
	Intrinsic::ID Intrinsic::getIntrinsicForGCCBuiltin(const char *TargetPrefix
	Str, const char *BuiltinNameStr) {
	StringRef BuiltinName(BuiltinNameStr);
	StringRef TargetPrefix(TargetPrefixStr);

	/* Target Independent Builtins */ {
	switch (BuiltinName.size()) {
	default: break;
	case 14: // 3 strings to match.
	if (BuiltinName.substr(0, 2) != "__")
	break;	break;

	switch (BuiltinName[2]) {	switch (BuiltinName[18]) {
	default: break;	default: break;

	case 'b': // 1 string to match.	case 'A': // 14 strings to match.
	if (BuiltinName.substr(3, 11) != "uiltin_trap")	if (BuiltinName.substr(19, 2) != "2.")
		break;
		switch (BuiltinName[21]) {
		default: break;
		case 'a': // 8 strings to match.
		if (BuiltinName.substr(22, 4) != "ddh.")
		break;
		switch (BuiltinName[26]) {
		default: break;
		case 'h': // 4 strings to match.
		if (BuiltinName.substr(27, 7) != "16.sat.")
		break;
		switch (BuiltinName[34]) {
		default: break;
		case 'h': // 2 strings to match.
		switch (BuiltinName[35]) {
		default: break;
		case 'h': // 1 string to match.
		return Intrinsic::hexagon_A2_addh_h16_sat_hh; // "__built
		in_HEXAGON.A2.addh.h16.sat.hh"
		case 'l': // 1 string to match.
		return Intrinsic::hexagon_A2_addh_h16_sat_hl; // "__built
		in_HEXAGON.A2.addh.h16.sat.hl"
		}
		break;
		case 'l': // 2 strings to match.
		switch (BuiltinName[35]) {
		default: break;
		case 'h': // 1 string to match.
		return Intrinsic::hexagon_A2_addh_h16_sat_lh; // "__built
		in_HEXAGON.A2.addh.h16.sat.lh"
		case 'l': // 1 string to match.
		return Intrinsic::hexagon_A2_addh_h16_sat_ll; // "__built
		in_HEXAGON.A2.addh.h16.sat.ll"
		}
		break;
		}
		break;
		case 'l': // 4 strings to match.
		if (BuiltinName.substr(27, 7) != "16.sat.")
		break;
		switch (BuiltinName[34]) {
		default: break;
		case 'h': // 2 strings to match.
		switch (BuiltinName[35]) {
		default: break;
		case 'h': // 1 string to match.
		return Intrinsic::hexagon_A2_addh_l16_sat_hh; // "__built
		in_HEXAGON.A2.addh.l16.sat.hh"
		case 'l': // 1 string to match.
		return Intrinsic::hexagon_A2_addh_l16_sat_hl; // "__built
		in_HEXAGON.A2.addh.l16.sat.hl"
		}
		break;
		case 'l': // 2 strings to match.
		switch (BuiltinName[35]) {
		default: break;
		case 'h': // 1 string to match.
		return Intrinsic::hexagon_A2_addh_l16_sat_lh; // "__built
		in_HEXAGON.A2.addh.l16.sat.lh"
		case 'l': // 1 string to match.
		return Intrinsic::hexagon_A2_addh_l16_sat_ll; // "__built
		in_HEXAGON.A2.addh.l16.sat.ll"
		}
		break;
		}
		break;
		}
		break;
		case 's': // 6 strings to match.
		if (BuiltinName.substr(22, 4) != "ubh.")
		break;
		switch (BuiltinName[26]) {
		default: break;
		case 'h': // 4 strings to match.
		if (BuiltinName.substr(27, 7) != "16.sat.")
		break;
		switch (BuiltinName[34]) {
		default: break;
		case 'h': // 2 strings to match.
		switch (BuiltinName[35]) {
		default: break;
		case 'h': // 1 string to match.
		return Intrinsic::hexagon_A2_subh_h16_sat_hh; // "__built
		in_HEXAGON.A2.subh.h16.sat.hh"
		case 'l': // 1 string to match.
		return Intrinsic::hexagon_A2_subh_h16_sat_hl; // "__built
		in_HEXAGON.A2.subh.h16.sat.hl"
		}
		break;
		case 'l': // 2 strings to match.
		switch (BuiltinName[35]) {
		default: break;
		case 'h': // 1 string to match.
		return Intrinsic::hexagon_A2_subh_h16_sat_lh; // "__built
		in_HEXAGON.A2.subh.h16.sat.lh"
		case 'l': // 1 string to match.
		return Intrinsic::hexagon_A2_subh_h16_sat_ll; // "__built
		in_HEXAGON.A2.subh.h16.sat.ll"
		}
		break;
		}
		break;
		case 'l': // 2 strings to match.
		if (BuiltinName.substr(27, 7) != "16.sat.")
		break;
		switch (BuiltinName[34]) {
		default: break;
		case 'h': // 1 string to match.
		if (BuiltinName[35] != 'l')
		break;
		return Intrinsic::hexagon_A2_subh_l16_sat_hl; // "__built
		in_HEXAGON.A2.subh.l16.sat.hl"
		case 'l': // 1 string to match.
		if (BuiltinName[35] != 'l')
		break;
		return Intrinsic::hexagon_A2_subh_l16_sat_ll; // "__built
		in_HEXAGON.A2.subh.l16.sat.ll"
		}
		break;
		}
	break;	break;

	return Intrinsic::trap; // "__builtin_trap"	}
	case 'g': // 2 strings to match.	break;
	if (BuiltinName.substr(3, 3) != "nu_")	case 'C': // 1 string to match.
		if (BuiltinName.substr(19, 17) != "4.fastcorner9_not")
	break;	break;

	switch (BuiltinName[6]) {	return Intrinsic::hexagon_C4_fastcorner9_not; // "__builtin_HEXAG
		ON.C4.fastcorner9_not"
		case 'M': // 16 strings to match.
		if (BuiltinName.substr(19, 8) != "2.mpyud.")
		break;
		switch (BuiltinName[27]) {
	default: break;	default: break;

	case 'f': // 1 string to match.	case 'a': // 8 strings to match.
	if (BuiltinName.substr(7, 7) != "2h_ieee")	if (BuiltinName.substr(28, 3) != "cc.")
	break;	break;

	return Intrinsic::convert_to_fp16; // "__gnu_f2h_ieee"	switch (BuiltinName[31]) {
	case 'h': // 1 string to match.	default: break;
	if (BuiltinName.substr(7, 7) != "2f_ieee")	case 'h': // 4 strings to match.
		switch (BuiltinName[32]) {
		default: break;
		case 'h': // 2 strings to match.
		if (BuiltinName.substr(33, 2) != ".s")
		break;
		switch (BuiltinName[35]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyud_acc_hh_s0; // "__built
		in_HEXAGON.M2.mpyud.acc.hh.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyud_acc_hh_s1; // "__built
		in_HEXAGON.M2.mpyud.acc.hh.s1"
		}
		break;
		case 'l': // 2 strings to match.
		if (BuiltinName.substr(33, 2) != ".s")
		break;
		switch (BuiltinName[35]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyud_acc_hl_s0; // "__built
		in_HEXAGON.M2.mpyud.acc.hl.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyud_acc_hl_s1; // "__built
		in_HEXAGON.M2.mpyud.acc.hl.s1"
		}
		break;
		}
	break;	break;

	return Intrinsic::convert_from_fp16; // "__gnu_h2f_ieee"	case 'l': // 4 strings to match.
	}	switch (BuiltinName[32]) {
	break;	default: break;
	}	case 'h': // 2 strings to match.
	break;	if (BuiltinName.substr(33, 2) != ".s")
	case 20: // 2 strings to match.	break;
	if (BuiltinName.substr(0, 10) != "__builtin_")	switch (BuiltinName[35]) {
	break;	default: break;
	switch (BuiltinName[10]) {	case '0': // 1 string to match.
	default: break;	return Intrinsic::hexagon_M2_mpyud_acc_lh_s0; // "__built
	case 'f': // 1 string to match.	in_HEXAGON.M2.mpyud.acc.lh.s0"
	if (BuiltinName.substr(11, 9) != "lt_rounds")	case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyud_acc_lh_s1; // "__built
		in_HEXAGON.M2.mpyud.acc.lh.s1"
		}
		break;
		case 'l': // 2 strings to match.
		if (BuiltinName.substr(33, 2) != ".s")
		break;
		switch (BuiltinName[35]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyud_acc_ll_s0; // "__built
		in_HEXAGON.M2.mpyud.acc.ll.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyud_acc_ll_s1; // "__built
		in_HEXAGON.M2.mpyud.acc.ll.s1"
		}
		break;
		}
		break;
		}
	break;	break;

	return Intrinsic::flt_rounds; // "__builtin_flt_rounds"	case 'n': // 8 strings to match.
	case 's': // 1 string to match.	if (BuiltinName.substr(28, 3) != "ac.")
	if (BuiltinName.substr(11, 9) != "tack_save")	break;
		switch (BuiltinName[31]) {
		default: break;
		case 'h': // 4 strings to match.
		switch (BuiltinName[32]) {
		default: break;
		case 'h': // 2 strings to match.
		if (BuiltinName.substr(33, 2) != ".s")
		break;
		switch (BuiltinName[35]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyud_nac_hh_s0; // "__built
		in_HEXAGON.M2.mpyud.nac.hh.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyud_nac_hh_s1; // "__built
		in_HEXAGON.M2.mpyud.nac.hh.s1"
		}
		break;
		case 'l': // 2 strings to match.
		if (BuiltinName.substr(33, 2) != ".s")
		break;
		switch (BuiltinName[35]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyud_nac_hl_s0; // "__built
		in_HEXAGON.M2.mpyud.nac.hl.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyud_nac_hl_s1; // "__built
		in_HEXAGON.M2.mpyud.nac.hl.s1"
		}
		break;
		}
		break;
		case 'l': // 4 strings to match.
		switch (BuiltinName[32]) {
		default: break;
		case 'h': // 2 strings to match.
		if (BuiltinName.substr(33, 2) != ".s")
		break;
		switch (BuiltinName[35]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyud_nac_lh_s0; // "__built
		in_HEXAGON.M2.mpyud.nac.lh.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyud_nac_lh_s1; // "__built
		in_HEXAGON.M2.mpyud.nac.lh.s1"
		}
		break;
		case 'l': // 2 strings to match.
		if (BuiltinName.substr(33, 2) != ".s")
		break;
		switch (BuiltinName[35]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyud_nac_ll_s0; // "__built
		in_HEXAGON.M2.mpyud.nac.ll.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpyud_nac_ll_s1; // "__built
		in_HEXAGON.M2.mpyud.nac.ll.s1"
		}
		break;
		}
		break;
		}
	break;	break;

	return Intrinsic::stacksave; // "__builtin_stack_save"	}
	}
	break;
	case 21: // 2 strings to match.
	if (BuiltinName.substr(0, 10) != "__builtin_")
	break;	break;

	switch (BuiltinName[10]) {
	default: break;
	case 'o': // 1 string to match.
	if (BuiltinName.substr(11, 10) != "bject_size")
	break;
	return Intrinsic::objectsize; // "__builtin_object_size"
	case 'u': // 1 string to match.
	if (BuiltinName.substr(11, 10) != "nwind_init")
	break;
	return Intrinsic::eh_unwind_init; // "__builtin_unwind_init"
	}	}
	break;	break;

	case 23: // 1 string to match.	case 38: // 24 strings to match.
	if (BuiltinName.substr(0, 23) != "__builtin_stack_restore")	if (BuiltinName.substr(0, 25) != "__builtin_HEXAGON.M2.mpy.")
	break;
	return Intrinsic::stackrestore; // "__builtin_stack_restore"
	case 25: // 1 string to match.
	if (BuiltinName.substr(0, 25) != "__builtin_init_trampoline")
	break;
	return Intrinsic::init_trampoline; // "__builtin_init_trampoline"
	case 27: // 1 string to match.
	if (BuiltinName.substr(0, 27) != "__builtin_adjust_trampoline")
	break;
	return Intrinsic::adjust_trampoline; // "__builtin_adjust_trampo
	line"
	}
	}
	if (TargetPrefix == "alpha") {
	switch (BuiltinName.size()) {
	default: break;
	case 21: // 1 string to match.
	if (BuiltinName.substr(0, 21) != "__builtin_alpha_umulh")
	break;
	return Intrinsic::alpha_umulh; // "__builtin_alpha_umulh"
	}
	}
	if (TargetPrefix == "arm") {
	switch (BuiltinName.size()) {
	default: break;
	case 17: // 3 strings to match.
	if (BuiltinName.substr(0, 14) != "__builtin_arm_")
	break;	break;

	switch (BuiltinName[14]) {	switch (BuiltinName[25]) {
	default: break;	default: break;

	case 'c': // 1 string to match.	case 'a': // 8 strings to match.
	if (BuiltinName.substr(15, 2) != "dp")	if (BuiltinName.substr(26, 7) != "cc.sat.")
	break;	break;

	return Intrinsic::arm_cdp; // "__builtin_arm_cdp"	switch (BuiltinName[33]) {
	case 'm': // 2 strings to match.
	switch (BuiltinName[15]) {
	default: break;	default: break;

	case 'c': // 1 string to match.	case 'h': // 4 strings to match.
	if (BuiltinName[16] != 'r')	switch (BuiltinName[34]) {
		default: break;
		case 'h': // 2 strings to match.
		if (BuiltinName.substr(35, 2) != ".s")
		break;
		switch (BuiltinName[37]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_acc_sat_hh_s0; // "__built
		in_HEXAGON.M2.mpy.acc.sat.hh.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_acc_sat_hh_s1; // "__built
		in_HEXAGON.M2.mpy.acc.sat.hh.s1"
		}
	break;	break;

	return Intrinsic::arm_mcr; // "__builtin_arm_mcr"	case 'l': // 2 strings to match.
	case 'r': // 1 string to match.	if (BuiltinName.substr(35, 2) != ".s")
	if (BuiltinName[16] != 'c')	break;
		switch (BuiltinName[37]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_acc_sat_hl_s0; // "__built
		in_HEXAGON.M2.mpy.acc.sat.hl.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_acc_sat_hl_s1; // "__built
		in_HEXAGON.M2.mpy.acc.sat.hl.s1"
		}
	break;	break;

	return Intrinsic::arm_mrc; // "__builtin_arm_mrc"	}
		break;
		case 'l': // 4 strings to match.
		switch (BuiltinName[34]) {
		default: break;
		case 'h': // 2 strings to match.
		if (BuiltinName.substr(35, 2) != ".s")
		break;
		switch (BuiltinName[37]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_acc_sat_lh_s0; // "__built
		in_HEXAGON.M2.mpy.acc.sat.lh.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_acc_sat_lh_s1; // "__built
		in_HEXAGON.M2.mpy.acc.sat.lh.s1"
		}
		break;
		case 'l': // 2 strings to match.
		if (BuiltinName.substr(35, 2) != ".s")
		break;
		switch (BuiltinName[37]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_acc_sat_ll_s0; // "__built
		in_HEXAGON.M2.mpy.acc.sat.ll.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_acc_sat_ll_s1; // "__built
		in_HEXAGON.M2.mpy.acc.sat.ll.s1"
		}
		break;
		}
		break;
	}	}
	break;	break;

	}	case 'n': // 8 strings to match.
	break;	if (BuiltinName.substr(26, 7) != "ac.sat.")
	case 18: // 8 strings to match.
	if (BuiltinName.substr(0, 14) != "__builtin_arm_")
	break;
	switch (BuiltinName[14]) {
	default: break;
	case 'c': // 1 string to match.
	if (BuiltinName.substr(15, 3) != "dp2")
	break;	break;

	return Intrinsic::arm_cdp2; // "__builtin_arm_cdp2"	switch (BuiltinName[33]) {
	case 'm': // 3 strings to match.
	switch (BuiltinName[15]) {
	default: break;	default: break;

	case 'c': // 2 strings to match.	case 'h': // 4 strings to match.
	if (BuiltinName[16] != 'r')	switch (BuiltinName[34]) {
	break;
	switch (BuiltinName[17]) {
	default: break;	default: break;

	case '2': // 1 string to match.	case 'h': // 2 strings to match.
	return Intrinsic::arm_mcr2; // "__builtin_arm_mcr2"	if (BuiltinName.substr(35, 2) != ".s")
	case 'r': // 1 string to match.	break;
	return Intrinsic::arm_mcrr; // "__builtin_arm_mcrr"	switch (BuiltinName[37]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_nac_sat_hh_s0; // "__built
		in_HEXAGON.M2.mpy.nac.sat.hh.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_nac_sat_hh_s1; // "__built
		in_HEXAGON.M2.mpy.nac.sat.hh.s1"
		}
		break;
		case 'l': // 2 strings to match.
		if (BuiltinName.substr(35, 2) != ".s")
		break;
		switch (BuiltinName[37]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_nac_sat_hl_s0; // "__built
		in_HEXAGON.M2.mpy.nac.sat.hl.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_nac_sat_hl_s1; // "__built
		in_HEXAGON.M2.mpy.nac.sat.hl.s1"
		}
		break;
	}	}
	break;	break;

	case 'r': // 1 string to match.	case 'l': // 4 strings to match.
	if (BuiltinName.substr(16, 2) != "c2")	switch (BuiltinName[34]) {
		default: break;
		case 'h': // 2 strings to match.
		if (BuiltinName.substr(35, 2) != ".s")
		break;
		switch (BuiltinName[37]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_nac_sat_lh_s0; // "__built
		in_HEXAGON.M2.mpy.nac.sat.lh.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_nac_sat_lh_s1; // "__built
		in_HEXAGON.M2.mpy.nac.sat.lh.s1"
		}
	break;	break;

	return Intrinsic::arm_mrc2; // "__builtin_arm_mrc2"	case 'l': // 2 strings to match.
		if (BuiltinName.substr(35, 2) != ".s")
		break;
		switch (BuiltinName[37]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_nac_sat_ll_s0; // "__built
		in_HEXAGON.M2.mpy.nac.sat.ll.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_nac_sat_ll_s1; // "__built
		in_HEXAGON.M2.mpy.nac.sat.ll.s1"
		}
		break;
		}
		break;
	}	}
	break;	break;

	case 'q': // 2 strings to match.	case 's': // 8 strings to match.
	switch (BuiltinName[15]) {	if (BuiltinName.substr(26, 7) != "at.rnd.")
		break;
		switch (BuiltinName[33]) {
	default: break;	default: break;

	case 'a': // 1 string to match.	case 'h': // 4 strings to match.
	if (BuiltinName.substr(16, 2) != "dd")	switch (BuiltinName[34]) {
		default: break;
		case 'h': // 2 strings to match.
		if (BuiltinName.substr(35, 2) != ".s")
		break;
		switch (BuiltinName[37]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_sat_rnd_hh_s0; // "__built
		in_HEXAGON.M2.mpy.sat.rnd.hh.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_sat_rnd_hh_s1; // "__built
		in_HEXAGON.M2.mpy.sat.rnd.hh.s1"
		}
	break;	break;

	return Intrinsic::arm_qadd; // "__builtin_arm_qadd"	case 'l': // 2 strings to match.
	case 's': // 1 string to match.	if (BuiltinName.substr(35, 2) != ".s")
	if (BuiltinName.substr(16, 2) != "ub")	break;
		switch (BuiltinName[37]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_sat_rnd_hl_s0; // "__built
		in_HEXAGON.M2.mpy.sat.rnd.hl.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_sat_rnd_hl_s1; // "__built
		in_HEXAGON.M2.mpy.sat.rnd.hl.s1"
		}
	break;	break;

	return Intrinsic::arm_qsub; // "__builtin_arm_qsub"	}
		break;
		case 'l': // 4 strings to match.
		switch (BuiltinName[34]) {
		default: break;
		case 'h': // 2 strings to match.
		if (BuiltinName.substr(35, 2) != ".s")
		break;
		switch (BuiltinName[37]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_sat_rnd_lh_s0; // "__built
		in_HEXAGON.M2.mpy.sat.rnd.lh.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_sat_rnd_lh_s1; // "__built
		in_HEXAGON.M2.mpy.sat.rnd.lh.s1"
		}
		break;
		case 'l': // 2 strings to match.
		if (BuiltinName.substr(35, 2) != ".s")
		break;
		switch (BuiltinName[37]) {
		default: break;
		case '0': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_sat_rnd_ll_s0; // "__built
		in_HEXAGON.M2.mpy.sat.rnd.ll.s0"
		case '1': // 1 string to match.
		return Intrinsic::hexagon_M2_mpy_sat_rnd_ll_s1; // "__built
		in_HEXAGON.M2.mpy.sat.rnd.ll.s1"
		}
		break;
		}
		break;
	}	}
	break;	break;

	case 's': // 1 string to match.
	if (BuiltinName.substr(15, 3) != "sat")
	break;
	return Intrinsic::arm_ssat; // "__builtin_arm_ssat"
	case 'u': // 1 string to match.
	if (BuiltinName.substr(15, 3) != "sat")
	break;
	return Intrinsic::arm_usat; // "__builtin_arm_usat"
	}	}
	break;	break;

	case 19: // 1 string to match.	case 41: // 4 strings to match.
	if (BuiltinName.substr(0, 19) != "__builtin_arm_mcrr2")	if (BuiltinName.substr(0, 29) != "__builtin_HEXAGON.S2.tableidx")
	break;
	return Intrinsic::arm_mcrr2; // "__builtin_arm_mcrr2"
	case 23: // 2 strings to match.
	if (BuiltinName.substr(0, 14) != "__builtin_arm_")
	break;	break;

	switch (BuiltinName[14]) {	switch (BuiltinName[29]) {
	default: break;	default: break;

	case 'g': // 1 string to match.	case 'b': // 1 string to match.
	if (BuiltinName.substr(15, 8) != "et_fpscr")	if (BuiltinName.substr(30, 11) != ".goodsyntax")
	break;	break;

	return Intrinsic::arm_get_fpscr; // "__builtin_arm_get_fpscr"	return Intrinsic::hexagon_S2_tableidxb_goodsyntax; // "__built
	case 's': // 1 string to match.	in_HEXAGON.S2.tableidxb.goodsyntax"
	if (BuiltinName.substr(15, 8) != "et_fpscr")	case 'd': // 1 string to match.
		if (BuiltinName.substr(30, 11) != ".goodsyntax")
	break;	break;

	return Intrinsic::arm_set_fpscr; // "__builtin_arm_set_fpscr"	return Intrinsic::hexagon_S2_tableidxd_goodsyntax; // "__built
		in_HEXAGON.S2.tableidxd.goodsyntax"
		case 'h': // 1 string to match.
		if (BuiltinName.substr(30, 11) != ".goodsyntax")
		break;
		return Intrinsic::hexagon_S2_tableidxh_goodsyntax; // "__built
		in_HEXAGON.S2.tableidxh.goodsyntax"
		case 'w': // 1 string to match.
		if (BuiltinName.substr(30, 11) != ".goodsyntax")
		break;
		return Intrinsic::hexagon_S2_tableidxw_goodsyntax; // "__built
		in_HEXAGON.S2.tableidxw.goodsyntax"
	}	}
	break;	break;

	case 24: // 1 string to match.	case 43: // 1 string to match.
	if (BuiltinName.substr(0, 24) != "__builtin_thread_pointer")	if (BuiltinName.substr(0, 43) != "__builtin_HEXAGON.S2.asr.i.r.rnd.good
		syntax")
	break;	break;

	return Intrinsic::arm_thread_pointer; // "__builtin_thread_pointe r"	return Intrinsic::hexagon_S2_asr_i_r_rnd_goodsyntax; // "__built in_HEXAGON.S2.asr.i.r.rnd.goodsyntax"
	}	}
	}	}
	if (TargetPrefix == "ppc") {	if (TargetPrefix == "ppc") {
	switch (BuiltinName.size()) {	switch (BuiltinName.size()) {
	default: break;	default: break;
	case 21: // 4 strings to match.	case 21: // 4 strings to match.
	if (BuiltinName.substr(0, 18) != "__builtin_altivec_")	if (BuiltinName.substr(0, 18) != "__builtin_altivec_")
	break;	break;
	switch (BuiltinName[18]) {	switch (BuiltinName[18]) {
	default: break;	default: break;

	skipping to change at line 17762	skipping to change at line 34688
	break;	break;
	return Intrinsic::x86_mmx_pand; // "__builtin_ia32_pand"	return Intrinsic::x86_mmx_pand; // "__builtin_ia32_pand"
	case 'x': // 1 string to match.	case 'x': // 1 string to match.
	if (BuiltinName.substr(17, 2) != "or")	if (BuiltinName.substr(17, 2) != "or")
	break;	break;
	return Intrinsic::x86_mmx_pxor; // "__builtin_ia32_pxor"	return Intrinsic::x86_mmx_pxor; // "__builtin_ia32_pxor"
	}	}
	break;	break;
	}	}
	break;	break;

	case 20: // 54 strings to match.	case 20: // 58 strings to match.
	if (BuiltinName.substr(0, 15) != "__builtin_ia32_")	if (BuiltinName.substr(0, 15) != "__builtin_ia32_")
	break;	break;
	switch (BuiltinName[15]) {	switch (BuiltinName[15]) {
	default: break;	default: break;
	case 'a': // 2 strings to match.	case 'a': // 2 strings to match.
	if (BuiltinName.substr(16, 3) != "dds")	if (BuiltinName.substr(16, 3) != "dds")
	break;	break;
	switch (BuiltinName[19]) {	switch (BuiltinName[19]) {
	default: break;	default: break;
	case 'd': // 1 string to match.	case 'd': // 1 string to match.
	return Intrinsic::x86_sse2_add_sd; // "__builtin_ia32_addsd"	return Intrinsic::x86_sse2_add_sd; // "__builtin_ia32_addsd"
	case 's': // 1 string to match.	case 's': // 1 string to match.
	return Intrinsic::x86_sse_add_ss; // "__builtin_ia32_addss"	return Intrinsic::x86_sse_add_ss; // "__builtin_ia32_addss"
	}	}
	break;	break;

		case 'c': // 4 strings to match.
		if (BuiltinName.substr(16, 2) != "mp")
		break;
		switch (BuiltinName[18]) {
		default: break;
		case 'p': // 2 strings to match.
		switch (BuiltinName[19]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_sse2_cmp_pd; // "__builtin_ia32_cmppd"
		case 's': // 1 string to match.
		return Intrinsic::x86_sse_cmp_ps; // "__builtin_ia32_cmpps"
		}
		break;
		case 's': // 2 strings to match.
		switch (BuiltinName[19]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_sse2_cmp_sd; // "__builtin_ia32_cmpsd"
		case 's': // 1 string to match.
		return Intrinsic::x86_sse_cmp_ss; // "__builtin_ia32_cmpss"
		}
		break;
		}
		break;
	case 'd': // 2 strings to match.	case 'd': // 2 strings to match.
	if (BuiltinName.substr(16, 3) != "ivs")	if (BuiltinName.substr(16, 3) != "ivs")
	break;	break;
	switch (BuiltinName[19]) {	switch (BuiltinName[19]) {
	default: break;	default: break;
	case 'd': // 1 string to match.	case 'd': // 1 string to match.
	return Intrinsic::x86_sse2_div_sd; // "__builtin_ia32_divsd"	return Intrinsic::x86_sse2_div_sd; // "__builtin_ia32_divsd"
	case 's': // 1 string to match.	case 's': // 1 string to match.
	return Intrinsic::x86_sse_div_ss; // "__builtin_ia32_divss"	return Intrinsic::x86_sse_div_ss; // "__builtin_ia32_divss"
	}	}

	skipping to change at line 18389	skipping to change at line 35340
	case 's': // 1 string to match.	case 's': // 1 string to match.
	return Intrinsic::x86_sse_sqrt_ss; // "__builtin_ia32_sqrtss"	return Intrinsic::x86_sse_sqrt_ss; // "__builtin_ia32_sqrtss"
	}	}
	break;	break;
	}	}
	break;	break;
	}	}
	break;	break;
	}	}
	break;	break;

	case 22: // 46 strings to match.	case 22: // 50 strings to match.
	if (BuiltinName.substr(0, 15) != "__builtin_ia32_")	if (BuiltinName.substr(0, 15) != "__builtin_ia32_")
	break;	break;
	switch (BuiltinName[15]) {	switch (BuiltinName[15]) {
	default: break;	default: break;

	case 'b': // 2 strings to match.	case 'b': // 4 strings to match.
	if (BuiltinName.substr(16, 5) != "lendp")	switch (BuiltinName[16]) {
	break;
	switch (BuiltinName[21]) {
	default: break;	default: break;

	case 'd': // 1 string to match.	case 'l': // 2 strings to match.
	return Intrinsic::x86_sse41_blendpd; // "__builtin_ia32_blendpd"	if (BuiltinName.substr(17, 4) != "endp")
	case 's': // 1 string to match.	break;
	return Intrinsic::x86_sse41_blendps; // "__builtin_ia32_blendps"	switch (BuiltinName[21]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_sse41_blendpd; // "__builtin_ia32_blendpd"
		case 's': // 1 string to match.
		return Intrinsic::x86_sse41_blendps; // "__builtin_ia32_blendps"
		}
		break;
		case 'z': // 2 strings to match.
		if (BuiltinName.substr(17, 3) != "hi_")
		break;
		switch (BuiltinName[20]) {
		default: break;
		case 'd': // 1 string to match.
		if (BuiltinName[21] != 'i')
		break;
		return Intrinsic::x86_bmi_bzhi_64; // "__builtin_ia32_bzhi_di"
		case 's': // 1 string to match.
		if (BuiltinName[21] != 'i')
		break;
		return Intrinsic::x86_bmi_bzhi_32; // "__builtin_ia32_bzhi_si"
		}
		break;
	}	}
	break;	break;
	case 'c': // 6 strings to match.	case 'c': // 6 strings to match.
	switch (BuiltinName[16]) {	switch (BuiltinName[16]) {
	default: break;	default: break;
	case 'l': // 1 string to match.	case 'l': // 1 string to match.
	if (BuiltinName.substr(17, 5) != "flush")	if (BuiltinName.substr(17, 5) != "flush")
	break;	break;
	return Intrinsic::x86_sse2_clflush; // "__builtin_ia32_clflush"	return Intrinsic::x86_sse2_clflush; // "__builtin_ia32_clflush"
	case 'o': // 1 string to match.	case 'o': // 1 string to match.

	skipping to change at line 18449	skipping to change at line 35420
	}	}
	break;	break;
	case 'd': // 1 string to match.	case 'd': // 1 string to match.
	if (BuiltinName.substr(16, 6) != "pps256")	if (BuiltinName.substr(16, 6) != "pps256")
	break;	break;
	return Intrinsic::x86_avx_dp_ps_256; // "__builtin_ia32_dpps256"	return Intrinsic::x86_avx_dp_ps_256; // "__builtin_ia32_dpps256"
	case 'm': // 1 string to match.	case 'm': // 1 string to match.
	if (BuiltinName.substr(16, 6) != "onitor")	if (BuiltinName.substr(16, 6) != "onitor")
	break;	break;
	return Intrinsic::x86_sse3_monitor; // "__builtin_ia32_monitor"	return Intrinsic::x86_sse3_monitor; // "__builtin_ia32_monitor"

	case 'p': // 25 strings to match.	case 'p': // 27 strings to match.
	switch (BuiltinName[16]) {	switch (BuiltinName[16]) {
	default: break;	default: break;
	case 'a': // 4 strings to match.	case 'a': // 4 strings to match.
	switch (BuiltinName[17]) {	switch (BuiltinName[17]) {
	default: break;	default: break;
	case 'd': // 2 strings to match.	case 'd': // 2 strings to match.
	if (BuiltinName.substr(18, 3) != "dus")	if (BuiltinName.substr(18, 3) != "dus")
	break;	break;
	switch (BuiltinName[21]) {	switch (BuiltinName[21]) {
	default: break;	default: break;

	skipping to change at line 18476	skipping to change at line 35447
	case 'l': // 1 string to match.	case 'l': // 1 string to match.
	if (BuiltinName.substr(18, 4) != "ignr")	if (BuiltinName.substr(18, 4) != "ignr")
	break;	break;
	return Intrinsic::x86_mmx_palignr_b; // "__builtin_ia32_palignr"	return Intrinsic::x86_mmx_palignr_b; // "__builtin_ia32_palignr"
	case 'v': // 1 string to match.	case 'v': // 1 string to match.
	if (BuiltinName.substr(18, 4) != "gusb")	if (BuiltinName.substr(18, 4) != "gusb")
	break;	break;
	return Intrinsic::x86_3dnow_pavgusb; // "__builtin_ia32_pavgusb"	return Intrinsic::x86_3dnow_pavgusb; // "__builtin_ia32_pavgusb"
	}	}
	break;	break;

	case 'c': // 8 strings to match.	case 'c': // 6 strings to match.
	if (BuiltinName.substr(17, 2) != "mp")	if (BuiltinName.substr(17, 2) != "mp")
	break;	break;
	switch (BuiltinName[19]) {	switch (BuiltinName[19]) {
	default: break;	default: break;

	case 'e': // 4 strings to match.	case 'e': // 3 strings to match.
	if (BuiltinName[20] != 'q')	if (BuiltinName[20] != 'q')
	break;	break;
	switch (BuiltinName[21]) {	switch (BuiltinName[21]) {
	default: break;	default: break;
	case 'b': // 1 string to match.	case 'b': // 1 string to match.
	return Intrinsic::x86_mmx_pcmpeq_b; // "__builtin_ia32_ pcmpeqb"	return Intrinsic::x86_mmx_pcmpeq_b; // "__builtin_ia32_ pcmpeqb"
	case 'd': // 1 string to match.	case 'd': // 1 string to match.
	return Intrinsic::x86_mmx_pcmpeq_d; // "__builtin_ia32_ pcmpeqd"	return Intrinsic::x86_mmx_pcmpeq_d; // "__builtin_ia32_ pcmpeqd"

	case 'q': // 1 string to match.
	return Intrinsic::x86_sse41_pcmpeqq; // "__builtin_ia32_
	pcmpeqq"
	case 'w': // 1 string to match.	case 'w': // 1 string to match.
	return Intrinsic::x86_mmx_pcmpeq_w; // "__builtin_ia32_ pcmpeqw"	return Intrinsic::x86_mmx_pcmpeq_w; // "__builtin_ia32_ pcmpeqw"
	}	}
	break;	break;

	case 'g': // 4 strings to match.	case 'g': // 3 strings to match.
	if (BuiltinName[20] != 't')	if (BuiltinName[20] != 't')
	break;	break;
	switch (BuiltinName[21]) {	switch (BuiltinName[21]) {
	default: break;	default: break;
	case 'b': // 1 string to match.	case 'b': // 1 string to match.
	return Intrinsic::x86_mmx_pcmpgt_b; // "__builtin_ia32_ pcmpgtb"	return Intrinsic::x86_mmx_pcmpgt_b; // "__builtin_ia32_ pcmpgtb"
	case 'd': // 1 string to match.	case 'd': // 1 string to match.
	return Intrinsic::x86_mmx_pcmpgt_d; // "__builtin_ia32_ pcmpgtd"	return Intrinsic::x86_mmx_pcmpgt_d; // "__builtin_ia32_ pcmpgtd"

	case 'q': // 1 string to match.
	return Intrinsic::x86_sse42_pcmpgtq; // "__builtin_ia32_
	pcmpgtq"
	case 'w': // 1 string to match.	case 'w': // 1 string to match.
	return Intrinsic::x86_mmx_pcmpgt_w; // "__builtin_ia32_ pcmpgtw"	return Intrinsic::x86_mmx_pcmpgt_w; // "__builtin_ia32_ pcmpgtw"
	}	}
	break;	break;
	}	}
	break;	break;

		case 'd': // 2 strings to match.
		if (BuiltinName.substr(17, 3) != "ep_")
		break;
		switch (BuiltinName[20]) {
		default: break;
		case 'd': // 1 string to match.
		if (BuiltinName[21] != 'i')
		break;
		return Intrinsic::x86_bmi_pdep_64; // "__builtin_ia32_pdep_di"
		case 's': // 1 string to match.
		if (BuiltinName[21] != 'i')
		break;
		return Intrinsic::x86_bmi_pdep_32; // "__builtin_ia32_pdep_si"
		}
		break;
		case 'e': // 2 strings to match.
		if (BuiltinName.substr(17, 3) != "xt_")
		break;
		switch (BuiltinName[20]) {
		default: break;
		case 'd': // 1 string to match.
		if (BuiltinName[21] != 'i')
		break;
		return Intrinsic::x86_bmi_pext_64; // "__builtin_ia32_pext_di"
		case 's': // 1 string to match.
		if (BuiltinName[21] != 'i')
		break;
		return Intrinsic::x86_bmi_pext_32; // "__builtin_ia32_pext_si"
		}
		break;
	case 'f': // 5 strings to match.	case 'f': // 5 strings to match.
	switch (BuiltinName[17]) {	switch (BuiltinName[17]) {
	default: break;	default: break;
	case 'c': // 3 strings to match.	case 'c': // 3 strings to match.
	if (BuiltinName.substr(18, 2) != "mp")	if (BuiltinName.substr(18, 2) != "mp")
	break;	break;
	switch (BuiltinName[20]) {	switch (BuiltinName[20]) {
	default: break;	default: break;
	case 'e': // 1 string to match.	case 'e': // 1 string to match.
	if (BuiltinName[21] != 'q')	if (BuiltinName[21] != 'q')

	skipping to change at line 18681	skipping to change at line 35678
	case 'e': // 1 string to match.	case 'e': // 1 string to match.
	return Intrinsic::x86_sse_ucomile_ss; // "__builtin_ia32_ ucomile"	return Intrinsic::x86_sse_ucomile_ss; // "__builtin_ia32_ ucomile"
	case 't': // 1 string to match.	case 't': // 1 string to match.
	return Intrinsic::x86_sse_ucomilt_ss; // "__builtin_ia32_ ucomilt"	return Intrinsic::x86_sse_ucomilt_ss; // "__builtin_ia32_ ucomilt"
	}	}
	break;	break;
	}	}
	break;	break;
	}	}
	break;	break;

	case 23: // 67 strings to match.	case 23: // 98 strings to match.
	if (BuiltinName.substr(0, 15) != "__builtin_ia32_")	if (BuiltinName.substr(0, 15) != "__builtin_ia32_")
	break;	break;
	switch (BuiltinName[15]) {	switch (BuiltinName[15]) {
	default: break;	default: break;
	case 'a': // 2 strings to match.	case 'a': // 2 strings to match.
	if (BuiltinName.substr(16, 6) != "ddsubp")	if (BuiltinName.substr(16, 6) != "ddsubp")
	break;	break;
	switch (BuiltinName[22]) {	switch (BuiltinName[22]) {
	default: break;	default: break;
	case 'd': // 1 string to match.	case 'd': // 1 string to match.

	skipping to change at line 18939	skipping to change at line 35936
	}	}
	break;	break;
	case 'n': // 1 string to match.	case 'n': // 1 string to match.
	if (BuiltinName.substr(19, 4) != "tdqa")	if (BuiltinName.substr(19, 4) != "tdqa")
	break;	break;
	return Intrinsic::x86_sse41_movntdqa; // "__builtin_ia32_ movntdqa"	return Intrinsic::x86_sse41_movntdqa; // "__builtin_ia32_ movntdqa"
	}	}
	break;	break;
	}	}
	break;	break;

	case 'p': // 21 strings to match.	case 'p': // 44 strings to match.
	switch (BuiltinName[16]) {	switch (BuiltinName[16]) {
	default: break;	default: break;

	case 'a': // 8 strings to match.	case 'a': // 13 strings to match.
	switch (BuiltinName[17]) {	switch (BuiltinName[17]) {
	default: break;	default: break;

	case 'b': // 3 strings to match.	case 'b': // 6 strings to match.
	if (BuiltinName[18] != 's')	if (BuiltinName[18] != 's')
	break;	break;
	switch (BuiltinName[19]) {	switch (BuiltinName[19]) {
	default: break;	default: break;

	case 'b': // 1 string to match.	case 'b': // 2 strings to match.
	if (BuiltinName.substr(20, 3) != "128")	switch (BuiltinName[20]) {
	break;	default: break;
	return Intrinsic::x86_ssse3_pabs_b_128; // "__builtin_ia32_	case '1': // 1 string to match.
	pabsb128"	if (BuiltinName.substr(21, 2) != "28")
	case 'd': // 1 string to match.	break;
	if (BuiltinName.substr(20, 3) != "128")	return Intrinsic::x86_ssse3_pabs_b_128; // "__builtin_ia32_
	break;	pabsb128"
	return Intrinsic::x86_ssse3_pabs_d_128; // "__builtin_ia32_	case '2': // 1 string to match.
	pabsd128"	if (BuiltinName.substr(21, 2) != "56")
	case 'w': // 1 string to match.	break;
	if (BuiltinName.substr(20, 3) != "128")	return Intrinsic::x86_avx2_pabs_b; // "__builtin_ia32_
	break;	pabsb256"
	return Intrinsic::x86_ssse3_pabs_w_128; // "__builtin_ia32_	}
	pabsw128"	break;
		case 'd': // 2 strings to match.
		switch (BuiltinName[20]) {
		default: break;
		case '1': // 1 string to match.
		if (BuiltinName.substr(21, 2) != "28")
		break;
		return Intrinsic::x86_ssse3_pabs_d_128; // "__builtin_ia32_
		pabsd128"
		case '2': // 1 string to match.
		if (BuiltinName.substr(21, 2) != "56")
		break;
		return Intrinsic::x86_avx2_pabs_d; // "__builtin_ia32_
		pabsd256"
		}
		break;
		case 'w': // 2 strings to match.
		switch (BuiltinName[20]) {
		default: break;
		case '1': // 1 string to match.
		if (BuiltinName.substr(21, 2) != "28")
		break;
		return Intrinsic::x86_ssse3_pabs_w_128; // "__builtin_ia32_
		pabsw128"
		case '2': // 1 string to match.
		if (BuiltinName.substr(21, 2) != "56")
		break;
		return Intrinsic::x86_avx2_pabs_w; // "__builtin_ia32_
		pabsw256"
		}
		break;
	}	}
	break;	break;
	case 'c': // 3 strings to match.	case 'c': // 3 strings to match.
	if (BuiltinName[18] != 'k')	if (BuiltinName[18] != 'k')
	break;	break;
	switch (BuiltinName[19]) {	switch (BuiltinName[19]) {
	default: break;	default: break;
	case 's': // 2 strings to match.	case 's': // 2 strings to match.
	if (BuiltinName[20] != 's')	if (BuiltinName[20] != 's')
	break;	break;

	skipping to change at line 18990	skipping to change at line 36014
	break;	break;
	return Intrinsic::x86_mmx_packsswb; // "__builtin_ia32_ packsswb"	return Intrinsic::x86_mmx_packsswb; // "__builtin_ia32_ packsswb"
	}	}
	break;	break;
	case 'u': // 1 string to match.	case 'u': // 1 string to match.
	if (BuiltinName.substr(20, 3) != "swb")	if (BuiltinName.substr(20, 3) != "swb")
	break;	break;
	return Intrinsic::x86_mmx_packuswb; // "__builtin_ia32_ packuswb"	return Intrinsic::x86_mmx_packuswb; // "__builtin_ia32_ packuswb"
	}	}
	break;	break;

	case 'v': // 2 strings to match.	case 'v': // 4 strings to match.
	if (BuiltinName[18] != 'g')	if (BuiltinName[18] != 'g')
	break;	break;
	switch (BuiltinName[19]) {	switch (BuiltinName[19]) {
	default: break;	default: break;

	case 'b': // 1 string to match.	case 'b': // 2 strings to match.
	if (BuiltinName.substr(20, 3) != "128")	switch (BuiltinName[20]) {
	break;	default: break;
	return Intrinsic::x86_sse2_pavg_b; // "__builtin_ia32_pavgb128	case '1': // 1 string to match.
	"	if (BuiltinName.substr(21, 2) != "28")
	case 'w': // 1 string to match.	break;
	if (BuiltinName.substr(20, 3) != "128")	return Intrinsic::x86_sse2_pavg_b; // "__builtin_ia32_
	break;	pavgb128"
	return Intrinsic::x86_sse2_pavg_w; // "__builtin_ia32_pavgw128	case '2': // 1 string to match.
	"	if (BuiltinName.substr(21, 2) != "56")
		break;
		return Intrinsic::x86_avx2_pavg_b; // "__builtin_ia32_
		pavgb256"
		}
		break;
		case 'w': // 2 strings to match.
		switch (BuiltinName[20]) {
		default: break;
		case '1': // 1 string to match.
		if (BuiltinName.substr(21, 2) != "28")
		break;
		return Intrinsic::x86_sse2_pavg_w; // "__builtin_ia32_
		pavgw128"
		case '2': // 1 string to match.
		if (BuiltinName.substr(21, 2) != "56")
		break;
		return Intrinsic::x86_avx2_pavg_w; // "__builtin_ia32_
		pavgw256"
		}
		break;
	}	}
	break;	break;
	}	}
	break;	break;
	case 'f': // 3 strings to match.	case 'f': // 3 strings to match.
	if (BuiltinName[17] != 'r')	if (BuiltinName[17] != 'r')
	break;	break;
	switch (BuiltinName[18]) {	switch (BuiltinName[18]) {
	default: break;	default: break;
	case 'c': // 2 strings to match.	case 'c': // 2 strings to match.

	skipping to change at line 19042	skipping to change at line 36084
	case 'o': // 1 string to match.	case 'o': // 1 string to match.
	if (BuiltinName.substr(18, 5) != "vmskb")	if (BuiltinName.substr(18, 5) != "vmskb")
	break;	break;
	return Intrinsic::x86_mmx_pmovmskb; // "__builtin_ia32_pmovmskb "	return Intrinsic::x86_mmx_pmovmskb; // "__builtin_ia32_pmovmskb "
	case 'u': // 1 string to match.	case 'u': // 1 string to match.
	if (BuiltinName.substr(18, 5) != "lhrsw")	if (BuiltinName.substr(18, 5) != "lhrsw")
	break;	break;
	return Intrinsic::x86_ssse3_pmul_hr_sw; // "__builtin_ia32_ pmulhrsw"	return Intrinsic::x86_ssse3_pmul_hr_sw; // "__builtin_ia32_ pmulhrsw"
	}	}
	break;	break;

	case 's': // 8 strings to match.	case 's': // 26 strings to match.
	switch (BuiltinName[17]) {	switch (BuiltinName[17]) {
	default: break;	default: break;

	case 'l': // 3 strings to match.	case 'l': // 10 strings to match.
	if (BuiltinName[18] != 'l')	if (BuiltinName[18] != 'l')
	break;	break;
	switch (BuiltinName[19]) {	switch (BuiltinName[19]) {
	default: break;	default: break;

	case 'd': // 1 string to match.	case 'd': // 2 strings to match.
	if (BuiltinName.substr(20, 3) != "128")	switch (BuiltinName[20]) {
	break;	default: break;
	return Intrinsic::x86_sse2_psll_d; // "__builtin_ia32_pslld128	case '1': // 1 string to match.
	"	if (BuiltinName.substr(21, 2) != "28")
	case 'q': // 1 string to match.	break;
	if (BuiltinName.substr(20, 3) != "128")	return Intrinsic::x86_sse2_psll_d; // "__builtin_ia32_
	break;	pslld128"
	return Intrinsic::x86_sse2_psll_q; // "__builtin_ia32_psllq128	case '2': // 1 string to match.
	"	if (BuiltinName.substr(21, 2) != "56")
	case 'w': // 1 string to match.	break;
	if (BuiltinName.substr(20, 3) != "128")	return Intrinsic::x86_avx2_psll_d; // "__builtin_ia32_
		pslld256"
		}
		break;
		case 'q': // 2 strings to match.
		switch (BuiltinName[20]) {
		default: break;
		case '1': // 1 string to match.
		if (BuiltinName.substr(21, 2) != "28")
		break;
		return Intrinsic::x86_sse2_psll_q; // "__builtin_ia32_
		psllq128"
		case '2': // 1 string to match.
		if (BuiltinName.substr(21, 2) != "56")
		break;
		return Intrinsic::x86_avx2_psll_q; // "__builtin_ia32_
		psllq256"
		}
		break;
		case 'v': // 4 strings to match.
		switch (BuiltinName[20]) {
		default: break;
		case '2': // 1 string to match.
		if (BuiltinName.substr(21, 2) != "di")
		break;
		return Intrinsic::x86_avx2_psllv_q; // "__builtin_ia32_
		psllv2di"
		case '4': // 2 strings to match.
		switch (BuiltinName[21]) {
		default: break;
		case 'd': // 1 string to match.
		if (BuiltinName[22] != 'i')
		break;
		return Intrinsic::x86_avx2_psllv_q_256; // "__built
		in_ia32_psllv4di"
		case 's': // 1 string to match.
		if (BuiltinName[22] != 'i')
		break;
		return Intrinsic::x86_avx2_psllv_d; // "__builtin_ia32_
		psllv4si"
		}
	break;	break;

	return Intrinsic::x86_sse2_psll_w; // "__builtin_ia32_psllw128	case '8': // 1 string to match.
	"	if (BuiltinName.substr(21, 2) != "si")
		break;
		return Intrinsic::x86_avx2_psllv_d_256; // "__builtin_ia32_
		psllv8si"
		}
		break;
		case 'w': // 2 strings to match.
		switch (BuiltinName[20]) {
		default: break;
		case '1': // 1 string to match.
		if (BuiltinName.substr(21, 2) != "28")
		break;
		return Intrinsic::x86_sse2_psll_w; // "__builtin_ia32_
		psllw128"
		case '2': // 1 string to match.
		if (BuiltinName.substr(21, 2) != "56")
		break;
		return Intrinsic::x86_avx2_psll_w; // "__builtin_ia32_
		psllw256"
		}
		break;
	}	}
	break;	break;

	case 'r': // 5 strings to match.	case 'r': // 16 strings to match.
	switch (BuiltinName[18]) {	switch (BuiltinName[18]) {
	default: break;	default: break;

	case 'a': // 2 strings to match.	case 'a': // 6 strings to match.
	switch (BuiltinName[19]) {	switch (BuiltinName[19]) {
	default: break;	default: break;

	case 'd': // 1 string to match.	case 'd': // 2 strings to match.
	if (BuiltinName.substr(20, 3) != "128")	switch (BuiltinName[20]) {
	break;	default: break;
	return Intrinsic::x86_sse2_psra_d; // "__builtin_ia32_	case '1': // 1 string to match.
	psrad128"	if (BuiltinName.substr(21, 2) != "28")
	case 'w': // 1 string to match.	break;
	if (BuiltinName.substr(20, 3) != "128")	return Intrinsic::x86_sse2_psra_d; // "__builtin_ia32_
	break;	psrad128"
	return Intrinsic::x86_sse2_psra_w; // "__builtin_ia32_	case '2': // 1 string to match.
	psraw128"	if (BuiltinName.substr(21, 2) != "56")
		break;
		return Intrinsic::x86_avx2_psra_d; // "__builtin_ia32_
		psrad256"
		}
		break;
		case 'v': // 2 strings to match.
		switch (BuiltinName[20]) {
		default: break;
		case '4': // 1 string to match.
		if (BuiltinName.substr(21, 2) != "si")
		break;
		return Intrinsic::x86_avx2_psrav_d; // "__builtin_ia32_
		psrav4si"
		case '8': // 1 string to match.
		if (BuiltinName.substr(21, 2) != "si")
		break;
		return Intrinsic::x86_avx2_psrav_d_256; // "__built
		in_ia32_psrav8si"
		}
		break;
		case 'w': // 2 strings to match.
		switch (BuiltinName[20]) {
		default: break;
		case '1': // 1 string to match.
		if (BuiltinName.substr(21, 2) != "28")
		break;
		return Intrinsic::x86_sse2_psra_w; // "__builtin_ia32_
		psraw128"
		case '2': // 1 string to match.
		if (BuiltinName.substr(21, 2) != "56")
		break;
		return Intrinsic::x86_avx2_psra_w; // "__builtin_ia32_
		psraw256"
		}
		break;
	}	}
	break;	break;

	case 'l': // 3 strings to match.	case 'l': // 10 strings to match.
	switch (BuiltinName[19]) {	switch (BuiltinName[19]) {
	default: break;	default: break;

	case 'd': // 1 string to match.	case 'd': // 2 strings to match.
	if (BuiltinName.substr(20, 3) != "128")	switch (BuiltinName[20]) {
	break;	default: break;
	return Intrinsic::x86_sse2_psrl_d; // "__builtin_ia32_	case '1': // 1 string to match.
	psrld128"	if (BuiltinName.substr(21, 2) != "28")
	case 'q': // 1 string to match.	break;
	if (BuiltinName.substr(20, 3) != "128")	return Intrinsic::x86_sse2_psrl_d; // "__builtin_ia32_
	break;	psrld128"
	return Intrinsic::x86_sse2_psrl_q; // "__builtin_ia32_	case '2': // 1 string to match.
	psrlq128"	if (BuiltinName.substr(21, 2) != "56")
	case 'w': // 1 string to match.	break;
	if (BuiltinName.substr(20, 3) != "128")	return Intrinsic::x86_avx2_psrl_d; // "__builtin_ia32_
		psrld256"
		}
		break;
		case 'q': // 2 strings to match.
		switch (BuiltinName[20]) {
		default: break;
		case '1': // 1 string to match.
		if (BuiltinName.substr(21, 2) != "28")
		break;
		return Intrinsic::x86_sse2_psrl_q; // "__builtin_ia32_
		psrlq128"
		case '2': // 1 string to match.
		if (BuiltinName.substr(21, 2) != "56")
		break;
		return Intrinsic::x86_avx2_psrl_q; // "__builtin_ia32_
		psrlq256"
		}
		break;
		case 'v': // 4 strings to match.
		switch (BuiltinName[20]) {
		default: break;
		case '2': // 1 string to match.
		if (BuiltinName.substr(21, 2) != "di")
		break;
		return Intrinsic::x86_avx2_psrlv_q; // "__builtin_ia32_
		psrlv2di"
		case '4': // 2 strings to match.
		switch (BuiltinName[21]) {
		default: break;
		case 'd': // 1 string to match.
		if (BuiltinName[22] != 'i')
		break;
		return Intrinsic::x86_avx2_psrlv_q_256; // "__built
		in_ia32_psrlv4di"
		case 's': // 1 string to match.
		if (BuiltinName[22] != 'i')
		break;
		return Intrinsic::x86_avx2_psrlv_d; // "__builtin_ia32_
		psrlv4si"
		}
	break;	break;

	return Intrinsic::x86_sse2_psrl_w; // "__builtin_ia32_	case '8': // 1 string to match.
	psrlw128"	if (BuiltinName.substr(21, 2) != "si")
		break;
		return Intrinsic::x86_avx2_psrlv_d_256; // "__built
		in_ia32_psrlv8si"
		}
		break;
		case 'w': // 2 strings to match.
		switch (BuiltinName[20]) {
		default: break;
		case '1': // 1 string to match.
		if (BuiltinName.substr(21, 2) != "28")
		break;
		return Intrinsic::x86_sse2_psrl_w; // "__builtin_ia32_
		psrlw128"
		case '2': // 1 string to match.
		if (BuiltinName.substr(21, 2) != "56")
		break;
		return Intrinsic::x86_avx2_psrl_w; // "__builtin_ia32_
		psrlw256"
		}
		break;
	}	}
	break;	break;
	}	}
	break;	break;
	}	}
	break;	break;
	}	}
	break;	break;
	case 'r': // 1 string to match.	case 'r': // 1 string to match.
	if (BuiltinName.substr(16, 7) != "cpps256")	if (BuiltinName.substr(16, 7) != "cpps256")

	skipping to change at line 19133	skipping to change at line 36312
	case 's': // 1 string to match.	case 's': // 1 string to match.
	return Intrinsic::x86_sse_storeu_ps; // "__builtin_ia32_storeups "	return Intrinsic::x86_sse_storeu_ps; // "__builtin_ia32_storeups "
	}	}
	break;	break;
	}	}
	break;	break;
	case 'u': // 1 string to match.	case 'u': // 1 string to match.
	if (BuiltinName.substr(16, 7) != "comineq")	if (BuiltinName.substr(16, 7) != "comineq")
	break;	break;
	return Intrinsic::x86_sse_ucomineq_ss; // "__builtin_ia32_ucomineq "	return Intrinsic::x86_sse_ucomineq_ss; // "__builtin_ia32_ucomineq "

	case 'v': // 5 strings to match.	case 'v': // 13 strings to match.
	switch (BuiltinName[16]) {	switch (BuiltinName[16]) {
	default: break;	default: break;

		case 'f': // 8 strings to match.
		if (BuiltinName[17] != 'm')
		break;
		switch (BuiltinName[18]) {
		default: break;
		case 'a': // 4 strings to match.
		if (BuiltinName.substr(19, 2) != "dd")
		break;
		switch (BuiltinName[21]) {
		default: break;
		case 'p': // 2 strings to match.
		switch (BuiltinName[22]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_fma4_vfmadd_pd; // "__builtin_ia32_
		vfmaddpd"
		case 's': // 1 string to match.
		return Intrinsic::x86_fma4_vfmadd_ps; // "__builtin_ia32_
		vfmaddps"
		}
		break;
		case 's': // 2 strings to match.
		switch (BuiltinName[22]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_fma4_vfmadd_sd; // "__builtin_ia32_
		vfmaddsd"
		case 's': // 1 string to match.
		return Intrinsic::x86_fma4_vfmadd_ss; // "__builtin_ia32_
		vfmaddss"
		}
		break;
		}
		break;
		case 's': // 4 strings to match.
		if (BuiltinName.substr(19, 2) != "ub")
		break;
		switch (BuiltinName[21]) {
		default: break;
		case 'p': // 2 strings to match.
		switch (BuiltinName[22]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_fma4_vfmsub_pd; // "__builtin_ia32_
		vfmsubpd"
		case 's': // 1 string to match.
		return Intrinsic::x86_fma4_vfmsub_ps; // "__builtin_ia32_
		vfmsubps"
		}
		break;
		case 's': // 2 strings to match.
		switch (BuiltinName[22]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_fma4_vfmsub_sd; // "__builtin_ia32_
		vfmsubsd"
		case 's': // 1 string to match.
		return Intrinsic::x86_fma4_vfmsub_ss; // "__builtin_ia32_
		vfmsubss"
		}
		break;
		}
		break;
		}
		break;
	case 't': // 4 strings to match.	case 't': // 4 strings to match.
	if (BuiltinName.substr(17, 3) != "est")	if (BuiltinName.substr(17, 3) != "est")
	break;	break;
	switch (BuiltinName[20]) {	switch (BuiltinName[20]) {
	default: break;	default: break;
	case 'c': // 2 strings to match.	case 'c': // 2 strings to match.
	if (BuiltinName[21] != 'p')	if (BuiltinName[21] != 'p')
	break;	break;
	switch (BuiltinName[22]) {	switch (BuiltinName[22]) {
	default: break;	default: break;

	skipping to change at line 19173	skipping to change at line 36409
	}	}
	break;	break;
	case 'z': // 1 string to match.	case 'z': // 1 string to match.
	if (BuiltinName.substr(17, 6) != "eroall")	if (BuiltinName.substr(17, 6) != "eroall")
	break;	break;
	return Intrinsic::x86_avx_vzeroall; // "__builtin_ia32_vzeroall "	return Intrinsic::x86_avx_vzeroall; // "__builtin_ia32_vzeroall "
	}	}
	break;	break;
	}	}
	break;	break;

	case 24: // 69 strings to match.	case 24: // 117 strings to match.
	if (BuiltinName.substr(0, 15) != "__builtin_ia32_")	if (BuiltinName.substr(0, 15) != "__builtin_ia32_")
	break;	break;
	switch (BuiltinName[15]) {	switch (BuiltinName[15]) {
	default: break;	default: break;
	case 'a': // 3 strings to match.	case 'a': // 3 strings to match.
	if (BuiltinName.substr(16, 2) != "es")	if (BuiltinName.substr(16, 2) != "es")
	break;	break;
	switch (BuiltinName[18]) {	switch (BuiltinName[18]) {
	default: break;	default: break;
	case 'd': // 1 string to match.	case 'd': // 1 string to match.

	skipping to change at line 19197	skipping to change at line 36433
	case 'e': // 1 string to match.	case 'e': // 1 string to match.
	if (BuiltinName.substr(19, 5) != "nc128")	if (BuiltinName.substr(19, 5) != "nc128")
	break;	break;
	return Intrinsic::x86_aesni_aesenc; // "__builtin_ia32_aesenc12 8"	return Intrinsic::x86_aesni_aesenc; // "__builtin_ia32_aesenc12 8"
	case 'i': // 1 string to match.	case 'i': // 1 string to match.
	if (BuiltinName.substr(19, 5) != "mc128")	if (BuiltinName.substr(19, 5) != "mc128")
	break;	break;
	return Intrinsic::x86_aesni_aesimc; // "__builtin_ia32_aesimc12 8"	return Intrinsic::x86_aesni_aesimc; // "__builtin_ia32_aesimc12 8"
	}	}
	break;	break;

		case 'b': // 2 strings to match.
		if (BuiltinName.substr(16, 6) != "extr_u")
		break;
		switch (BuiltinName[22]) {
		default: break;
		case '3': // 1 string to match.
		if (BuiltinName[23] != '2')
		break;
		return Intrinsic::x86_bmi_bextr_32; // "__builtin_ia32_bextr_u3
		2"
		case '6': // 1 string to match.
		if (BuiltinName[23] != '4')
		break;
		return Intrinsic::x86_bmi_bextr_64; // "__builtin_ia32_bextr_u6
		4"
		}
		break;
	case 'c': // 7 strings to match.	case 'c': // 7 strings to match.
	switch (BuiltinName[16]) {	switch (BuiltinName[16]) {
	default: break;	default: break;
	case 'o': // 1 string to match.	case 'o': // 1 string to match.
	if (BuiltinName.substr(17, 7) != "misdneq")	if (BuiltinName.substr(17, 7) != "misdneq")
	break;	break;
	return Intrinsic::x86_sse2_comineq_sd; // "__builtin_ia32_comisdne q"	return Intrinsic::x86_sse2_comineq_sd; // "__builtin_ia32_comisdne q"
	case 'v': // 6 strings to match.	case 'v': // 6 strings to match.
	if (BuiltinName.substr(17, 2) != "tt")	if (BuiltinName.substr(17, 2) != "tt")
	break;	break;

	skipping to change at line 19296	skipping to change at line 36547
	break;	break;
	return Intrinsic::x86_avx_hsub_pd_256; // "__builtin_ia32_ hsubpd256"	return Intrinsic::x86_avx_hsub_pd_256; // "__builtin_ia32_ hsubpd256"
	case 's': // 1 string to match.	case 's': // 1 string to match.
	if (BuiltinName.substr(21, 3) != "256")	if (BuiltinName.substr(21, 3) != "256")
	break;	break;
	return Intrinsic::x86_avx_hsub_ps_256; // "__builtin_ia32_ hsubps256"	return Intrinsic::x86_avx_hsub_ps_256; // "__builtin_ia32_ hsubps256"
	}	}
	break;	break;
	}	}
	break;	break;

	case 'p': // 46 strings to match.	case 'm': // 2 strings to match.
		if (BuiltinName.substr(16, 7) != "askload")
		break;
		switch (BuiltinName[23]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_avx2_maskload_d; // "__builtin_ia32_maskload
		d"
		case 'q': // 1 string to match.
		return Intrinsic::x86_avx2_maskload_q; // "__builtin_ia32_maskload
		q"
		}
		break;
		case 'p': // 82 strings to match.
	switch (BuiltinName[16]) {	switch (BuiltinName[16]) {
	default: break;	default: break;

	case 'a': // 2 strings to match.	case 'a': // 4 strings to match.
	if (BuiltinName.substr(17, 3) != "dds")	if (BuiltinName.substr(17, 3) != "dds")
	break;	break;
	switch (BuiltinName[20]) {	switch (BuiltinName[20]) {
	default: break;	default: break;

	case 'b': // 1 string to match.	case 'b': // 2 strings to match.
	if (BuiltinName.substr(21, 3) != "128")	switch (BuiltinName[21]) {
	break;	default: break;
	return Intrinsic::x86_sse2_padds_b; // "__builtin_ia32_paddsb12	case '1': // 1 string to match.
	8"	if (BuiltinName.substr(22, 2) != "28")
	case 'w': // 1 string to match.	break;
	if (BuiltinName.substr(21, 3) != "128")	return Intrinsic::x86_sse2_padds_b; // "__builtin_ia32_
	break;	paddsb128"
	return Intrinsic::x86_sse2_padds_w; // "__builtin_ia32_paddsw12	case '2': // 1 string to match.
	8"	if (BuiltinName.substr(22, 2) != "56")
		break;
		return Intrinsic::x86_avx2_padds_b; // "__builtin_ia32_
		paddsb256"
		}
		break;
		case 'w': // 2 strings to match.
		switch (BuiltinName[21]) {
		default: break;
		case '1': // 1 string to match.
		if (BuiltinName.substr(22, 2) != "28")
		break;
		return Intrinsic::x86_sse2_padds_w; // "__builtin_ia32_
		paddsw128"
		case '2': // 1 string to match.
		if (BuiltinName.substr(22, 2) != "56")
		break;
		return Intrinsic::x86_avx2_padds_w; // "__builtin_ia32_
		paddsw256"
		}
		break;
	}	}
	break;	break;

	case 'h': // 4 strings to match.	case 'e': // 1 string to match.
		if (BuiltinName.substr(17, 7) != "rmti256")
		break;
		return Intrinsic::x86_avx2_vperm2i128; // "__builtin_ia32_permti25
		6"
		case 'h': // 8 strings to match.
	switch (BuiltinName[17]) {	switch (BuiltinName[17]) {
	default: break;	default: break;

	case 'a': // 2 strings to match.	case 'a': // 4 strings to match.
	if (BuiltinName.substr(18, 2) != "dd")	if (BuiltinName.substr(18, 2) != "dd")
	break;	break;
	switch (BuiltinName[20]) {	switch (BuiltinName[20]) {
	default: break;	default: break;

	case 'd': // 1 string to match.	case 'd': // 2 strings to match.
	if (BuiltinName.substr(21, 3) != "128")	switch (BuiltinName[21]) {
	break;	default: break;
	return Intrinsic::x86_ssse3_phadd_d_128; // "__builtin_ia32_	case '1': // 1 string to match.
	phaddd128"	if (BuiltinName.substr(22, 2) != "28")
	case 'w': // 1 string to match.	break;
	if (BuiltinName.substr(21, 3) != "128")	return Intrinsic::x86_ssse3_phadd_d_128; // "__builtin_ia32_
	break;	phaddd128"
	return Intrinsic::x86_ssse3_phadd_w_128; // "__builtin_ia32_	case '2': // 1 string to match.
	phaddw128"	if (BuiltinName.substr(22, 2) != "56")
		break;
		return Intrinsic::x86_avx2_phadd_d; // "__builtin_ia32_
		phaddd256"
		}
		break;
		case 'w': // 2 strings to match.
		switch (BuiltinName[21]) {
		default: break;
		case '1': // 1 string to match.
		if (BuiltinName.substr(22, 2) != "28")
		break;
		return Intrinsic::x86_ssse3_phadd_w_128; // "__builtin_ia32_
		phaddw128"
		case '2': // 1 string to match.
		if (BuiltinName.substr(22, 2) != "56")
		break;
		return Intrinsic::x86_avx2_phadd_w; // "__builtin_ia32_
		phaddw256"
		}
		break;
	}	}
	break;	break;

	case 's': // 2 strings to match.	case 's': // 4 strings to match.
	if (BuiltinName.substr(18, 2) != "ub")	if (BuiltinName.substr(18, 2) != "ub")
	break;	break;
	switch (BuiltinName[20]) {	switch (BuiltinName[20]) {
	default: break;	default: break;

	case 'd': // 1 string to match.	case 'd': // 2 strings to match.
	if (BuiltinName.substr(21, 3) != "128")	switch (BuiltinName[21]) {
	break;	default: break;
	return Intrinsic::x86_ssse3_phsub_d_128; // "__builtin_ia32_	case '1': // 1 string to match.
	phsubd128"	if (BuiltinName.substr(22, 2) != "28")
	case 'w': // 1 string to match.	break;
	if (BuiltinName.substr(21, 3) != "128")	return Intrinsic::x86_ssse3_phsub_d_128; // "__builtin_ia32_
	break;	phsubd128"
	return Intrinsic::x86_ssse3_phsub_w_128; // "__builtin_ia32_	case '2': // 1 string to match.
	phsubw128"	if (BuiltinName.substr(22, 2) != "56")
		break;
		return Intrinsic::x86_avx2_phsub_d; // "__builtin_ia32_
		phsubd256"
		}
		break;
		case 'w': // 2 strings to match.
		switch (BuiltinName[21]) {
		default: break;
		case '1': // 1 string to match.
		if (BuiltinName.substr(22, 2) != "28")
		break;
		return Intrinsic::x86_ssse3_phsub_w_128; // "__builtin_ia32_
		phsubw128"
		case '2': // 1 string to match.
		if (BuiltinName.substr(22, 2) != "56")
		break;
		return Intrinsic::x86_avx2_phsub_w; // "__builtin_ia32_
		phsubw256"
		}
		break;
	}	}
	break;	break;
	}	}
	break;	break;

	case 'm': // 15 strings to match.	case 'm': // 29 strings to match.
	switch (BuiltinName[17]) {	switch (BuiltinName[17]) {
	default: break;	default: break;

	case 'a': // 7 strings to match.	case 'a': // 13 strings to match.
	switch (BuiltinName[18]) {	switch (BuiltinName[18]) {
	default: break;	default: break;
	case 'd': // 1 string to match.	case 'd': // 1 string to match.
	if (BuiltinName.substr(19, 5) != "dubsw")	if (BuiltinName.substr(19, 5) != "dubsw")
	break;	break;
	return Intrinsic::x86_ssse3_pmadd_ub_sw; // "__builtin_ia32_ pmaddubsw"	return Intrinsic::x86_ssse3_pmadd_ub_sw; // "__builtin_ia32_ pmaddubsw"

	case 'x': // 6 strings to match.	case 'x': // 12 strings to match.
	switch (BuiltinName[19]) {	switch (BuiltinName[19]) {
	default: break;	default: break;

	case 's': // 3 strings to match.	case 's': // 6 strings to match.
	switch (BuiltinName[20]) {	switch (BuiltinName[20]) {
	default: break;	default: break;

	case 'b': // 1 string to match.	case 'b': // 2 strings to match.
	if (BuiltinName.substr(21, 3) != "128")	switch (BuiltinName[21]) {
		default: break;
		case '1': // 1 string to match.
		if (BuiltinName.substr(22, 2) != "28")
		break;
		return Intrinsic::x86_sse41_pmaxsb; // "__builtin_ia32_
		pmaxsb128"
		case '2': // 1 string to match.
		if (BuiltinName.substr(22, 2) != "56")
		break;
		return Intrinsic::x86_avx2_pmaxs_b; // "__builtin_ia32_
		pmaxsb256"
		}
		break;
		case 'd': // 2 strings to match.
		switch (BuiltinName[21]) {
		default: break;
		case '1': // 1 string to match.
		if (BuiltinName.substr(22, 2) != "28")
		break;
		return Intrinsic::x86_sse41_pmaxsd; // "__builtin_ia32_
		pmaxsd128"
		case '2': // 1 string to match.
		if (BuiltinName.substr(22, 2) != "56")
		break;
		return Intrinsic::x86_avx2_pmaxs_d; // "__builtin_ia32_
		pmaxsd256"
		}
		break;
		case 'w': // 2 strings to match.
		switch (BuiltinName[21]) {
		default: break;
		case '1': // 1 string to match.
		if (BuiltinName.substr(22, 2) != "28")
		break;
		return Intrinsic::x86_sse2_pmaxs_w; // "__builtin_ia32_
		pmaxsw128"
		case '2': // 1 string to match.
		if (BuiltinName.substr(22, 2) != "56")
		break;
		return Intrinsic::x86_avx2_pmaxs_w; // "__builtin_ia32_
		pmaxsw256"
		}
		break;
		}
		break;
		case 'u': // 6 strings to match.
		switch (BuiltinName[20]) {
		default: break;
		case 'b': // 2 strings to match.
		switch (BuiltinName[21]) {
		default: break;
		case '1': // 1 string to match.
		if (BuiltinName.substr(22, 2) != "28")
		break;
		return Intrinsic::x86_sse2_pmaxu_b; // "__builtin_ia32_
		pmaxub128"
		case '2': // 1 string to match.
		if (BuiltinName.substr(22, 2) != "56")
		break;
		return Intrinsic::x86_avx2_pmaxu_b; // "__builtin_ia32_
		pmaxub256"
		}
		break;
		case 'd': // 2 strings to match.
		switch (BuiltinName[21]) {
		default: break;
		case '1': // 1 string to match.
		if (BuiltinName.substr(22, 2) != "28")
		break;
		return Intrinsic::x86_sse41_pmaxud; // "__builtin_ia32_
		pmaxud128"
		case '2': // 1 string to match.
		if (BuiltinName.substr(22, 2) != "56")
		break;
		return Intrinsic::x86_avx2_pmaxu_d; // "__builtin_ia32_
		pmaxud256"
		}
		break;
		case 'w': // 2 strings to match.
		switch (BuiltinName[21]) {
		default: break;
		case '1': // 1 string to match.
		if (BuiltinName.substr(22, 2) != "28")
		break;
		return Intrinsic::x86_sse41_pmaxuw; // "__builtin_ia32_
		pmaxuw128"
		case '2': // 1 string to match.
		if (BuiltinName.substr(22, 2) != "56")
		break;
		return Intrinsic::x86_avx2_pmaxu_w; // "__builtin_ia32_
		pmaxuw256"
		}
		break;
		}
		break;
		}
		break;
		}
		break;
		case 'i': // 12 strings to match.
		if (BuiltinName[18] != 'n')
		break;
		switch (BuiltinName[19]) {
		default: break;
		case 's': // 6 strings to match.
		switch (BuiltinName[20]) {
		default: break;
		case 'b': // 2 strings to match.
		switch (BuiltinName[21]) {
		default: break;
		case '1': // 1 string to match.
		if (BuiltinName.substr(22, 2) != "28")
	break;	break;

	return Intrinsic::x86_sse41_pmaxsb; // "__builtin_ia32_	return Intrinsic::x86_sse41_pminsb; // "__builtin_ia32_
	pmaxsb128"	pminsb128"
	case 'd': // 1 string to match.	case '2': // 1 string to match.
	if (BuiltinName.substr(21, 3) != "128")	if (BuiltinName.substr(22, 2) != "56")
		break;
		return Intrinsic::x86_avx2_pmins_b; // "__builtin_ia32_
		pminsb256"
		}
		break;
		case 'd': // 2 strings to match.
		switch (BuiltinName[21]) {
		default: break;
		case '1': // 1 string to match.
		if (BuiltinName.substr(22, 2) != "28")
		break;
		return Intrinsic::x86_sse41_pminsd; // "__builtin_ia32_
		pminsd128"
		case '2': // 1 string to match.
		if (BuiltinName.substr(22, 2) != "56")
		break;
		return Intrinsic::x86_avx2_pmins_d; // "__builtin_ia32_
		pminsd256"
		}
		break;
		case 'w': // 2 strings to match.
		switch (BuiltinName[21]) {
		default: break;
		case '1': // 1 string to match.
		if (BuiltinName.substr(22, 2) != "28")
		break;
		return Intrinsic::x86_sse2_pmins_w; // "__builtin_ia32_
		pminsw128"
		case '2': // 1 string to match.
		if (BuiltinName.substr(22, 2) != "56")
		break;
		return Intrinsic::x86_avx2_pmins_w; // "__builtin_ia32_
		pminsw256"
		}
		break;
		}
		break;
		case 'u': // 6 strings to match.
		switch (BuiltinName[20]) {
		default: break;
		case 'b': // 2 strings to match.
		switch (BuiltinName[21]) {
		default: break;
		case '1': // 1 string to match.
		if (BuiltinName.substr(22, 2) != "28")
		break;
		return Intrinsic::x86_sse2_pminu_b; // "__builtin_ia32_
		pminub128"
		case '2': // 1 string to match.
		if (BuiltinName.substr(22, 2) != "56")
		break;
		return Intrinsic::x86_avx2_pminu_b; // "__builtin_ia32_
		pminub256"
		}
		break;
		case 'd': // 2 strings to match.
		switch (BuiltinName[21]) {
		default: break;
		case '1': // 1 string to match.
		if (BuiltinName.substr(22, 2) != "28")
	break;	break;

	return Intrinsic::x86_sse41_pmaxsd; // "__builtin_ia32_	return Intrinsic::x86_sse41_pminud; // "__builtin_ia32_
	pmaxsd128"	pminud128"
	case 'w': // 1 string to match.	case '2': // 1 string to match.
	if (BuiltinName.substr(21, 3) != "128")	if (BuiltinName.substr(22, 2) != "56")
	break;	break;

	return Intrinsic::x86_sse2_pmaxs_w; // "__builtin_ia32_ pmaxsw128"	return Intrinsic::x86_avx2_pminu_d; // "__builtin_ia32_ pminud256"
	}	}
	break;	break;

	case 'u': // 3 strings to match.	case 'w': // 2 strings to match.
	switch (BuiltinName[20]) {	switch (BuiltinName[21]) {
	default: break;	default: break;

	case 'b': // 1 string to match.	case '1': // 1 string to match.
	if (BuiltinName.substr(21, 3) != "128")	if (BuiltinName.substr(22, 2) != "28")
	break;
	return Intrinsic::x86_sse2_pmaxu_b; // "__builtin_ia32_
	pmaxub128"
	case 'd': // 1 string to match.
	if (BuiltinName.substr(21, 3) != "128")
	break;	break;

	return Intrinsic::x86_sse41_pmaxud; // "__builtin_ia32_	return Intrinsic::x86_sse41_pminuw; // "__builtin_ia32_
	pmaxud128"	pminuw128"
	case 'w': // 1 string to match.	case '2': // 1 string to match.
	if (BuiltinName.substr(21, 3) != "128")	if (BuiltinName.substr(22, 2) != "56")
	break;	break;

	return Intrinsic::x86_sse41_pmaxuw; // "__builtin_ia32_ pmaxuw128"	return Intrinsic::x86_avx2_pminu_w; // "__builtin_ia32_ pminuw256"
	}	}
	break;	break;
	}	}
	break;	break;
	}	}
	break;	break;

	case 'i': // 6 strings to match.	case 'u': // 4 strings to match.
	if (BuiltinName[18] != 'n')	if (BuiltinName[18] != 'l')
	break;	break;
	switch (BuiltinName[19]) {	switch (BuiltinName[19]) {
	default: break;	default: break;

	case 's': // 3 strings to match.	case 'd': // 2 strings to match.
	switch (BuiltinName[20]) {	if (BuiltinName[20] != 'q')
		break;
		switch (BuiltinName[21]) {
	default: break;	default: break;

	case 'b': // 1 string to match.	case '1': // 1 string to match.
	if (BuiltinName.substr(21, 3) != "128")	if (BuiltinName.substr(22, 2) != "28")
	break;
	return Intrinsic::x86_sse41_pminsb; // "__builtin_ia32_
	pminsb128"
	case 'd': // 1 string to match.
	if (BuiltinName.substr(21, 3) != "128")
	break;	break;

	return Intrinsic::x86_sse41_pminsd; // "__builtin_ia32_	return Intrinsic::x86_sse41_pmuldq; // "__builtin_ia32_
	pminsd128"	pmuldq128"
	case 'w': // 1 string to match.	case '2': // 1 string to match.
	if (BuiltinName.substr(21, 3) != "128")	if (BuiltinName.substr(22, 2) != "56")
	break;	break;

	return Intrinsic::x86_sse2_pmins_w; // "__builtin_ia32_ pminsw128"	return Intrinsic::x86_avx2_pmul_dq; // "__builtin_ia32_ pmuldq256"
	}	}
	break;	break;

	case 'u': // 3 strings to match.	case 'h': // 2 strings to match.
	switch (BuiltinName[20]) {	if (BuiltinName[20] != 'w')
		break;
		switch (BuiltinName[21]) {
	default: break;	default: break;

	case 'b': // 1 string to match.	case '1': // 1 string to match.
	if (BuiltinName.substr(21, 3) != "128")	if (BuiltinName.substr(22, 2) != "28")
	break;
	return Intrinsic::x86_sse2_pminu_b; // "__builtin_ia32_
	pminub128"
	case 'd': // 1 string to match.
	if (BuiltinName.substr(21, 3) != "128")
	break;	break;

	return Intrinsic::x86_sse41_pminud; // "__builtin_ia32_	return Intrinsic::x86_sse2_pmulh_w; // "__builtin_ia32_
	pminud128"	pmulhw128"
	case 'w': // 1 string to match.	case '2': // 1 string to match.
	if (BuiltinName.substr(21, 3) != "128")	if (BuiltinName.substr(22, 2) != "56")
	break;	break;

	return Intrinsic::x86_sse41_pminuw; // "__builtin_ia32_ pminuw128"	return Intrinsic::x86_avx2_pmulh_w; // "__builtin_ia32_ pmulhw256"
	}	}
	break;	break;
	}	}
	break;	break;

	case 'u': // 2 strings to match.	}
	if (BuiltinName[18] != 'l')	break;
		case 's': // 30 strings to match.
		switch (BuiltinName[17]) {
		default: break;
		case 'a': // 2 strings to match.
		if (BuiltinName.substr(18, 3) != "dbw")
	break;	break;

	switch (BuiltinName[19]) {	switch (BuiltinName[21]) {
	default: break;	default: break;

	case 'd': // 1 string to match.	case '1': // 1 string to match.
	if (BuiltinName.substr(20, 4) != "q128")	if (BuiltinName.substr(22, 2) != "28")
	break;	break;

	return Intrinsic::x86_sse41_pmuldq; // "__builtin_ia32_	return Intrinsic::x86_sse2_psad_bw; // "__builtin_ia32_
	pmuldq128"	psadbw128"
	case 'h': // 1 string to match.	case '2': // 1 string to match.
	if (BuiltinName.substr(20, 4) != "w128")	if (BuiltinName.substr(22, 2) != "56")
	break;	break;

	return Intrinsic::x86_sse2_pmulh_w; // "__builtin_ia32_ pmulhw128"	return Intrinsic::x86_avx2_psad_bw; // "__builtin_ia32_ psadbw256"
	}	}
	break;	break;

	}	case 'h': // 2 strings to match.
	break;	if (BuiltinName.substr(18, 3) != "ufb")
	case 's': // 15 strings to match.
	switch (BuiltinName[17]) {
	default: break;
	case 'a': // 1 string to match.
	if (BuiltinName.substr(18, 6) != "dbw128")
	break;
	return Intrinsic::x86_sse2_psad_bw; // "__builtin_ia32_psadbw12
	8"
	case 'h': // 1 string to match.
	if (BuiltinName.substr(18, 6) != "ufb128")
	break;	break;

	return Intrinsic::x86_ssse3_pshuf_b_128; // "__builtin_ia32_	switch (BuiltinName[21]) {
	pshufb128"	default: break;
	case 'i': // 3 strings to match.	case '1': // 1 string to match.
		if (BuiltinName.substr(22, 2) != "28")
		break;
		return Intrinsic::x86_ssse3_pshuf_b_128; // "__builtin_ia32_
		pshufb128"
		case '2': // 1 string to match.
		if (BuiltinName.substr(22, 2) != "56")
		break;
		return Intrinsic::x86_avx2_pshuf_b; // "__builtin_ia32_
		pshufb256"
		}
		break;
		case 'i': // 6 strings to match.
	if (BuiltinName.substr(18, 2) != "gn")	if (BuiltinName.substr(18, 2) != "gn")
	break;	break;
	switch (BuiltinName[20]) {	switch (BuiltinName[20]) {
	default: break;	default: break;

	case 'b': // 1 string to match.	case 'b': // 2 strings to match.
	if (BuiltinName.substr(21, 3) != "128")	switch (BuiltinName[21]) {
	break;	default: break;
	return Intrinsic::x86_ssse3_psign_b_128; // "__builtin_ia32_	case '1': // 1 string to match.
	psignb128"	if (BuiltinName.substr(22, 2) != "28")
	case 'd': // 1 string to match.	break;
	if (BuiltinName.substr(21, 3) != "128")	return Intrinsic::x86_ssse3_psign_b_128; // "__builtin_ia32_
	break;	psignb128"
	return Intrinsic::x86_ssse3_psign_d_128; // "__builtin_ia32_	case '2': // 1 string to match.
	psignd128"	if (BuiltinName.substr(22, 2) != "56")
	case 'w': // 1 string to match.	break;
	if (BuiltinName.substr(21, 3) != "128")	return Intrinsic::x86_avx2_psign_b; // "__builtin_ia32_
	break;	psignb256"
	return Intrinsic::x86_ssse3_psign_w_128; // "__builtin_ia32_	}
	psignw128"	break;
		case 'd': // 2 strings to match.
		switch (BuiltinName[21]) {
		default: break;
		case '1': // 1 string to match.
		if (BuiltinName.substr(22, 2) != "28")
		break;
		return Intrinsic::x86_ssse3_psign_d_128; // "__builtin_ia32_
		psignd128"
		case '2': // 1 string to match.
		if (BuiltinName.substr(22, 2) != "56")
		break;
		return Intrinsic::x86_avx2_psign_d; // "__builtin_ia32_
		psignd256"
		}
		break;
		case 'w': // 2 strings to match.
		switch (BuiltinName[21]) {
		default: break;
		case '1': // 1 string to match.
		if (BuiltinName.substr(22, 2) != "28")
		break;
		return Intrinsic::x86_ssse3_psign_w_128; // "__builtin_ia32_
		psignw128"
		case '2': // 1 string to match.
		if (BuiltinName.substr(22, 2) != "56")
		break;
		return Intrinsic::x86_avx2_psign_w; // "__builtin_ia32_
		psignw256"
		}
		break;
	}	}
	break;	break;

	case 'l': // 3 strings to match.	case 'l': // 6 strings to match.
	if (BuiltinName[18] != 'l')	if (BuiltinName[18] != 'l')
	break;	break;
	switch (BuiltinName[19]) {	switch (BuiltinName[19]) {
	default: break;	default: break;

	case 'd': // 1 string to match.	case 'd': // 2 strings to match.
	if (BuiltinName.substr(20, 4) != "i128")	if (BuiltinName[20] != 'i')
	break;	break;

	return Intrinsic::x86_sse2_pslli_d; // "__builtin_ia32_	switch (BuiltinName[21]) {
	pslldi128"	default: break;
	case 'q': // 1 string to match.	case '1': // 1 string to match.
	if (BuiltinName.substr(20, 4) != "i128")	if (BuiltinName.substr(22, 2) != "28")
		break;
		return Intrinsic::x86_sse2_pslli_d; // "__builtin_ia32_
		pslldi128"
		case '2': // 1 string to match.
		if (BuiltinName.substr(22, 2) != "56")
		break;
		return Intrinsic::x86_avx2_pslli_d; // "__builtin_ia32_
		pslldi256"
		}
		break;
		case 'q': // 2 strings to match.
		if (BuiltinName[20] != 'i')
	break;	break;

	return Intrinsic::x86_sse2_pslli_q; // "__builtin_ia32_	switch (BuiltinName[21]) {
	psllqi128"	default: break;
	case 'w': // 1 string to match.	case '1': // 1 string to match.
	if (BuiltinName.substr(20, 4) != "i128")	if (BuiltinName.substr(22, 2) != "28")
		break;
		return Intrinsic::x86_sse2_pslli_q; // "__builtin_ia32_
		psllqi128"
		case '2': // 1 string to match.
		if (BuiltinName.substr(22, 2) != "56")
		break;
		return Intrinsic::x86_avx2_pslli_q; // "__builtin_ia32_
		psllqi256"
		}
		break;
		case 'w': // 2 strings to match.
		if (BuiltinName[20] != 'i')
	break;	break;

	return Intrinsic::x86_sse2_pslli_w; // "__builtin_ia32_	switch (BuiltinName[21]) {
	psllwi128"	default: break;
		case '1': // 1 string to match.
		if (BuiltinName.substr(22, 2) != "28")
		break;
		return Intrinsic::x86_sse2_pslli_w; // "__builtin_ia32_
		psllwi128"
		case '2': // 1 string to match.
		if (BuiltinName.substr(22, 2) != "56")
		break;
		return Intrinsic::x86_avx2_pslli_w; // "__builtin_ia32_
		psllwi256"
		}
		break;
	}	}
	break;	break;

	case 'r': // 5 strings to match.	case 'r': // 10 strings to match.
	switch (BuiltinName[18]) {	switch (BuiltinName[18]) {
	default: break;	default: break;

	case 'a': // 2 strings to match.	case 'a': // 4 strings to match.
	switch (BuiltinName[19]) {	switch (BuiltinName[19]) {
	default: break;	default: break;

	case 'd': // 1 string to match.	case 'd': // 2 strings to match.
	if (BuiltinName.substr(20, 4) != "i128")	if (BuiltinName[20] != 'i')
	break;	break;

	return Intrinsic::x86_sse2_psrai_d; // "__builtin_ia32_	switch (BuiltinName[21]) {
	psradi128"	default: break;
	case 'w': // 1 string to match.	case '1': // 1 string to match.
	if (BuiltinName.substr(20, 4) != "i128")	if (BuiltinName.substr(22, 2) != "28")
		break;
		return Intrinsic::x86_sse2_psrai_d; // "__builtin_ia32_
		psradi128"
		case '2': // 1 string to match.
		if (BuiltinName.substr(22, 2) != "56")
		break;
		return Intrinsic::x86_avx2_psrai_d; // "__builtin_ia32_
		psradi256"
		}
		break;
		case 'w': // 2 strings to match.
		if (BuiltinName[20] != 'i')
	break;	break;

	return Intrinsic::x86_sse2_psrai_w; // "__builtin_ia32_	switch (BuiltinName[21]) {
	psrawi128"	default: break;
		case '1': // 1 string to match.
		if (BuiltinName.substr(22, 2) != "28")
		break;
		return Intrinsic::x86_sse2_psrai_w; // "__builtin_ia32_
		psrawi128"
		case '2': // 1 string to match.
		if (BuiltinName.substr(22, 2) != "56")
		break;
		return Intrinsic::x86_avx2_psrai_w; // "__builtin_ia32_
		psrawi256"
		}
		break;
	}	}
	break;	break;

	case 'l': // 3 strings to match.	case 'l': // 6 strings to match.
	switch (BuiltinName[19]) {	switch (BuiltinName[19]) {
	default: break;	default: break;

	case 'd': // 1 string to match.	case 'd': // 2 strings to match.
	if (BuiltinName.substr(20, 4) != "i128")	if (BuiltinName[20] != 'i')
	break;	break;

	return Intrinsic::x86_sse2_psrli_d; // "__builtin_ia32_	switch (BuiltinName[21]) {
	psrldi128"	default: break;
	case 'q': // 1 string to match.	case '1': // 1 string to match.
	if (BuiltinName.substr(20, 4) != "i128")	if (BuiltinName.substr(22, 2) != "28")
		break;
		return Intrinsic::x86_sse2_psrli_d; // "__builtin_ia32_
		psrldi128"
		case '2': // 1 string to match.
		if (BuiltinName.substr(22, 2) != "56")
		break;
		return Intrinsic::x86_avx2_psrli_d; // "__builtin_ia32_
		psrldi256"
		}
		break;
		case 'q': // 2 strings to match.
		if (BuiltinName[20] != 'i')
	break;	break;

	return Intrinsic::x86_sse2_psrli_q; // "__builtin_ia32_	switch (BuiltinName[21]) {
	psrlqi128"	default: break;
	case 'w': // 1 string to match.	case '1': // 1 string to match.
	if (BuiltinName.substr(20, 4) != "i128")	if (BuiltinName.substr(22, 2) != "28")
		break;
		return Intrinsic::x86_sse2_psrli_q; // "__builtin_ia32_
		psrlqi128"
		case '2': // 1 string to match.
		if (BuiltinName.substr(22, 2) != "56")
		break;
		return Intrinsic::x86_avx2_psrli_q; // "__builtin_ia32_
		psrlqi256"
		}
		break;
		case 'w': // 2 strings to match.
		if (BuiltinName[20] != 'i')
	break;	break;

	return Intrinsic::x86_sse2_psrli_w; // "__builtin_ia32_	switch (BuiltinName[21]) {
	psrlwi128"	default: break;
		case '1': // 1 string to match.
		if (BuiltinName.substr(22, 2) != "28")
		break;
		return Intrinsic::x86_sse2_psrli_w; // "__builtin_ia32_
		psrlwi128"
		case '2': // 1 string to match.
		if (BuiltinName.substr(22, 2) != "56")
		break;
		return Intrinsic::x86_avx2_psrli_w; // "__builtin_ia32_
		psrlwi256"
		}
		break;
	}	}
	break;	break;
	}	}
	break;	break;

	case 'u': // 2 strings to match.	case 'u': // 4 strings to match.
	if (BuiltinName.substr(18, 2) != "bs")	if (BuiltinName.substr(18, 2) != "bs")
	break;	break;
	switch (BuiltinName[20]) {	switch (BuiltinName[20]) {
	default: break;	default: break;

	case 'b': // 1 string to match.	case 'b': // 2 strings to match.
	if (BuiltinName.substr(21, 3) != "128")	switch (BuiltinName[21]) {
	break;	default: break;
	return Intrinsic::x86_sse2_psubs_b; // "__builtin_ia32_	case '1': // 1 string to match.
	psubsb128"	if (BuiltinName.substr(22, 2) != "28")
	case 'w': // 1 string to match.	break;
	if (BuiltinName.substr(21, 3) != "128")	return Intrinsic::x86_sse2_psubs_b; // "__builtin_ia32_
	break;	psubsb128"
	return Intrinsic::x86_sse2_psubs_w; // "__builtin_ia32_	case '2': // 1 string to match.
	psubsw128"	if (BuiltinName.substr(22, 2) != "56")
		break;
		return Intrinsic::x86_avx2_psubs_b; // "__builtin_ia32_
		psubsb256"
		}
		break;
		case 'w': // 2 strings to match.
		switch (BuiltinName[21]) {
		default: break;
		case '1': // 1 string to match.
		if (BuiltinName.substr(22, 2) != "28")
		break;
		return Intrinsic::x86_sse2_psubs_w; // "__builtin_ia32_
		psubsw128"
		case '2': // 1 string to match.
		if (BuiltinName.substr(22, 2) != "56")
		break;
		return Intrinsic::x86_avx2_psubs_w; // "__builtin_ia32_
		psubsw256"
		}
		break;
	}	}
	break;	break;
	}	}
	break;	break;
	case 't': // 4 strings to match.	case 't': // 4 strings to match.
	if (BuiltinName.substr(17, 3) != "est")	if (BuiltinName.substr(17, 3) != "est")
	break;	break;
	switch (BuiltinName[20]) {	switch (BuiltinName[20]) {
	default: break;	default: break;
	case 'c': // 2 strings to match.	case 'c': // 2 strings to match.

	skipping to change at line 19679	skipping to change at line 37284
	switch (BuiltinName[23]) {	switch (BuiltinName[23]) {
	default: break;	default: break;
	case 'e': // 1 string to match.	case 'e': // 1 string to match.
	return Intrinsic::x86_sse2_ucomile_sd; // "__builtin_ia32_ ucomisdle"	return Intrinsic::x86_sse2_ucomile_sd; // "__builtin_ia32_ ucomisdle"
	case 't': // 1 string to match.	case 't': // 1 string to match.
	return Intrinsic::x86_sse2_ucomilt_sd; // "__builtin_ia32_ ucomisdlt"	return Intrinsic::x86_sse2_ucomilt_sd; // "__builtin_ia32_ ucomisdlt"
	}	}
	break;	break;
	}	}
	break;	break;

	case 'v': // 2 strings to match.	case 'v': // 10 strings to match.
	if (BuiltinName.substr(16, 7) != "permilp")	switch (BuiltinName[16]) {
	break;	default: break;
	switch (BuiltinName[23]) {	case 'c': // 2 strings to match.
	default: break;	if (BuiltinName.substr(17, 3) != "vtp")
	case 'd': // 1 string to match.	break;
	return Intrinsic::x86_avx_vpermil_pd; // "__builtin_ia32_vpermilp	switch (BuiltinName[20]) {
	d"	default: break;
	case 's': // 1 string to match.	case 'h': // 1 string to match.
	return Intrinsic::x86_avx_vpermil_ps; // "__builtin_ia32_vpermilp	if (BuiltinName.substr(21, 3) != "2ps")
	s"	break;
	}	return Intrinsic::x86_vcvtph2ps_128; // "__builtin_ia32_vcvtph2p
	break;	s"
		case 's': // 1 string to match.
		if (BuiltinName.substr(21, 3) != "2ph")
		break;
		return Intrinsic::x86_vcvtps2ph_128; // "__builtin_ia32_vcvtps2p
		h"
		}
		break;
		case 'f': // 8 strings to match.
		if (BuiltinName.substr(17, 2) != "nm")
		break;
		switch (BuiltinName[19]) {
		default: break;
		case 'a': // 4 strings to match.
		if (BuiltinName.substr(20, 2) != "dd")
		break;
		switch (BuiltinName[22]) {
		default: break;
		case 'p': // 2 strings to match.
		switch (BuiltinName[23]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_fma4_vfnmadd_pd; // "__builtin_ia32_
		vfnmaddpd"
		case 's': // 1 string to match.
		return Intrinsic::x86_fma4_vfnmadd_ps; // "__builtin_ia32_
		vfnmaddps"
		}
		break;
		case 's': // 2 strings to match.
		switch (BuiltinName[23]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_fma4_vfnmadd_sd; // "__builtin_ia32_
		vfnmaddsd"
		case 's': // 1 string to match.
		return Intrinsic::x86_fma4_vfnmadd_ss; // "__builtin_ia32_
		vfnmaddss"
		}
		break;
		}
		break;
		case 's': // 4 strings to match.
		if (BuiltinName.substr(20, 2) != "ub")
		break;
		switch (BuiltinName[22]) {
		default: break;
		case 'p': // 2 strings to match.
		switch (BuiltinName[23]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_fma4_vfnmsub_pd; // "__builtin_ia32_
		vfnmsubpd"
		case 's': // 1 string to match.
		return Intrinsic::x86_fma4_vfnmsub_ps; // "__builtin_ia32_
		vfnmsubps"
		}
		break;
		case 's': // 2 strings to match.
		switch (BuiltinName[23]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_fma4_vfnmsub_sd; // "__builtin_ia32_
		vfnmsubsd"
		case 's': // 1 string to match.
		return Intrinsic::x86_fma4_vfnmsub_ss; // "__builtin_ia32_
		vfnmsubss"
		}
		break;
		}
		break;
		}
		break;
		}
		break;
	}	}
	break;	break;

	case 25: // 42 strings to match.	case 25: // 58 strings to match.
	if (BuiltinName.substr(0, 15) != "__builtin_ia32_")	if (BuiltinName.substr(0, 15) != "__builtin_ia32_")
	break;	break;
	switch (BuiltinName[15]) {	switch (BuiltinName[15]) {
	default: break;	default: break;
	case 'b': // 2 strings to match.	case 'b': // 2 strings to match.
	if (BuiltinName.substr(16, 5) != "lendp")	if (BuiltinName.substr(16, 5) != "lendp")
	break;	break;
	switch (BuiltinName[21]) {	switch (BuiltinName[21]) {
	default: break;	default: break;
	case 'd': // 1 string to match.	case 'd': // 1 string to match.

	skipping to change at line 19738	skipping to change at line 37409
	case 's': // 1 string to match.	case 's': // 1 string to match.
	return Intrinsic::x86_sse_cvtsi642ss; // "__builtin_ia32_ cvtsi642ss"	return Intrinsic::x86_sse_cvtsi642ss; // "__builtin_ia32_ cvtsi642ss"
	}	}
	break;	break;
	case 's': // 1 string to match.	case 's': // 1 string to match.
	if (BuiltinName.substr(20, 5) != "2si64")	if (BuiltinName.substr(20, 5) != "2si64")
	break;	break;
	return Intrinsic::x86_sse_cvtss2si64; // "__builtin_ia32_cvtss2si 64"	return Intrinsic::x86_sse_cvtss2si64; // "__builtin_ia32_cvtss2si 64"
	}	}
	break;	break;

	case 'l': // 3 strings to match.	case 'm': // 10 strings to match.
	if (BuiltinName.substr(16, 3) != "oad")
	break;
	switch (BuiltinName[19]) {
	default: break;
	case 'd': // 1 string to match.
	if (BuiltinName.substr(20, 5) != "qu256")
	break;
	return Intrinsic::x86_avx_loadu_dq_256; // "__builtin_ia32_
	loaddqu256"
	case 'u': // 2 strings to match.
	if (BuiltinName[20] != 'p')
	break;
	switch (BuiltinName[21]) {
	default: break;
	case 'd': // 1 string to match.
	if (BuiltinName.substr(22, 3) != "256")
	break;
	return Intrinsic::x86_avx_loadu_pd_256; // "__builtin_ia32_
	loadupd256"
	case 's': // 1 string to match.
	if (BuiltinName.substr(22, 3) != "256")
	break;
	return Intrinsic::x86_avx_loadu_ps_256; // "__builtin_ia32_
	loadups256"
	}
	break;
	}
	break;
	case 'm': // 7 strings to match.
	switch (BuiltinName[16]) {	switch (BuiltinName[16]) {
	default: break;	default: break;

	case 'a': // 3 strings to match.	case 'a': // 5 strings to match.
	if (BuiltinName.substr(17, 2) != "sk")	if (BuiltinName.substr(17, 2) != "sk")
	break;	break;
	switch (BuiltinName[19]) {	switch (BuiltinName[19]) {
	default: break;	default: break;
	case 'l': // 2 strings to match.	case 'l': // 2 strings to match.
	if (BuiltinName.substr(20, 4) != "oadp")	if (BuiltinName.substr(20, 4) != "oadp")
	break;	break;
	switch (BuiltinName[24]) {	switch (BuiltinName[24]) {
	default: break;	default: break;
	case 'd': // 1 string to match.	case 'd': // 1 string to match.
	return Intrinsic::x86_avx_maskload_pd; // "__builtin_ia32_ maskloadpd"	return Intrinsic::x86_avx_maskload_pd; // "__builtin_ia32_ maskloadpd"
	case 's': // 1 string to match.	case 's': // 1 string to match.
	return Intrinsic::x86_avx_maskload_ps; // "__builtin_ia32_ maskloadps"	return Intrinsic::x86_avx_maskload_ps; // "__builtin_ia32_ maskloadps"
	}	}
	break;	break;
	case 'm': // 1 string to match.	case 'm': // 1 string to match.
	if (BuiltinName.substr(20, 5) != "ovdqu")	if (BuiltinName.substr(20, 5) != "ovdqu")
	break;	break;
	return Intrinsic::x86_sse2_maskmov_dqu; // "__builtin_ia32_ maskmovdqu"	return Intrinsic::x86_sse2_maskmov_dqu; // "__builtin_ia32_ maskmovdqu"

		case 's': // 2 strings to match.
		if (BuiltinName.substr(20, 4) != "tore")
		break;
		switch (BuiltinName[24]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_avx2_maskstore_d; // "__builtin_ia32_
		maskstored"
		case 'q': // 1 string to match.
		return Intrinsic::x86_avx2_maskstore_q; // "__builtin_ia32_
		maskstoreq"
		}
		break;
	}	}
	break;	break;
	case 'o': // 3 strings to match.	case 'o': // 3 strings to match.
	if (BuiltinName.substr(17, 3) != "vnt")	if (BuiltinName.substr(17, 3) != "vnt")
	break;	break;
	switch (BuiltinName[20]) {	switch (BuiltinName[20]) {
	default: break;	default: break;
	case 'd': // 1 string to match.	case 'd': // 1 string to match.
	if (BuiltinName.substr(21, 4) != "q256")	if (BuiltinName.substr(21, 4) != "q256")
	break;	break;

	skipping to change at line 19813	skipping to change at line 37469
	break;	break;
	return Intrinsic::x86_avx_movnt_pd_256; // "__builtin_ia32_ movntpd256"	return Intrinsic::x86_avx_movnt_pd_256; // "__builtin_ia32_ movntpd256"
	case 's': // 1 string to match.	case 's': // 1 string to match.
	if (BuiltinName.substr(22, 3) != "256")	if (BuiltinName.substr(22, 3) != "256")
	break;	break;
	return Intrinsic::x86_avx_movnt_ps_256; // "__builtin_ia32_ movntps256"	return Intrinsic::x86_avx_movnt_ps_256; // "__builtin_ia32_ movntps256"
	}	}
	break;	break;
	}	}
	break;	break;

	case 'p': // 1 string to match.	case 'p': // 2 strings to match.
	if (BuiltinName.substr(17, 8) != "sadbw128")	if (BuiltinName.substr(17, 5) != "sadbw")
	break;	break;

	return Intrinsic::x86_sse41_mpsadbw; // "__builtin_ia32_mpsadbw1	switch (BuiltinName[22]) {
	28"	default: break;
		case '1': // 1 string to match.
		if (BuiltinName.substr(23, 2) != "28")
		break;
		return Intrinsic::x86_sse41_mpsadbw; // "__builtin_ia32_mpsadbw1
		28"
		case '2': // 1 string to match.
		if (BuiltinName.substr(23, 2) != "56")
		break;
		return Intrinsic::x86_avx2_mpsadbw; // "__builtin_ia32_mpsadbw2
		56"
		}
		break;
	}	}
	break;	break;

	case 'p': // 18 strings to match.	case 'p': // 26 strings to match.
	switch (BuiltinName[16]) {	switch (BuiltinName[16]) {
	default: break;	default: break;

	case 'a': // 2 strings to match.	case 'a': // 4 strings to match.
	if (BuiltinName.substr(17, 4) != "ddus")	if (BuiltinName.substr(17, 4) != "ddus")
	break;	break;
	switch (BuiltinName[21]) {	switch (BuiltinName[21]) {
	default: break;	default: break;

	case 'b': // 1 string to match.	case 'b': // 2 strings to match.
	if (BuiltinName.substr(22, 3) != "128")	switch (BuiltinName[22]) {
	break;	default: break;
	return Intrinsic::x86_sse2_paddus_b; // "__builtin_ia32_paddusb1	case '1': // 1 string to match.
	28"	if (BuiltinName.substr(23, 2) != "28")
	case 'w': // 1 string to match.	break;
	if (BuiltinName.substr(22, 3) != "128")	return Intrinsic::x86_sse2_paddus_b; // "__builtin_ia32_
	break;	paddusb128"
	return Intrinsic::x86_sse2_paddus_w; // "__builtin_ia32_paddusw1	case '2': // 1 string to match.
	28"	if (BuiltinName.substr(23, 2) != "56")
		break;
		return Intrinsic::x86_avx2_paddus_b; // "__builtin_ia32_
		paddusb256"
		}
		break;
		case 'w': // 2 strings to match.
		switch (BuiltinName[22]) {
		default: break;
		case '1': // 1 string to match.
		if (BuiltinName.substr(23, 2) != "28")
		break;
		return Intrinsic::x86_sse2_paddus_w; // "__builtin_ia32_
		paddusw128"
		case '2': // 1 string to match.
		if (BuiltinName.substr(23, 2) != "56")
		break;
		return Intrinsic::x86_avx2_paddus_w; // "__builtin_ia32_
		paddusw256"
		}
		break;
	}	}
	break;	break;

	case 'b': // 1 string to match.	case 'b': // 4 strings to match.
	if (BuiltinName.substr(17, 8) != "lendw128")	if (BuiltinName.substr(17, 4) != "lend")
	break;
	return Intrinsic::x86_sse41_pblendw; // "__builtin_ia32_pblendw1
	28"
	case 'c': // 6 strings to match.
	if (BuiltinName.substr(17, 2) != "mp")
	break;	break;

	switch (BuiltinName[19]) {	switch (BuiltinName[21]) {
	default: break;	default: break;

	case 'e': // 3 strings to match.	case 'd': // 2 strings to match.
	if (BuiltinName[20] != 'q')	switch (BuiltinName[22]) {
	break;
	switch (BuiltinName[21]) {
	default: break;	default: break;

	case 'b': // 1 string to match.	case '1': // 1 string to match.
	if (BuiltinName.substr(22, 3) != "128")	if (BuiltinName.substr(23, 2) != "28")
	break;
	return Intrinsic::x86_sse2_pcmpeq_b; // "__builtin_ia32_
	pcmpeqb128"
	case 'd': // 1 string to match.
	if (BuiltinName.substr(22, 3) != "128")
	break;	break;

	return Intrinsic::x86_sse2_pcmpeq_d; // "__builtin_ia32_	return Intrinsic::x86_avx2_pblendd_128; // "__builtin_ia32_
	pcmpeqd128"	pblendd128"
	case 'w': // 1 string to match.	case '2': // 1 string to match.
	if (BuiltinName.substr(22, 3) != "128")	if (BuiltinName.substr(23, 2) != "56")
	break;	break;

	return Intrinsic::x86_sse2_pcmpeq_w; // "__builtin_ia32_ pcmpeqw128"	return Intrinsic::x86_avx2_pblendd_256; // "__builtin_ia32_ pblendd256"
	}	}
	break;	break;

	case 'g': // 3 strings to match.	case 'w': // 2 strings to match.
	if (BuiltinName[20] != 't')	switch (BuiltinName[22]) {
	break;
	switch (BuiltinName[21]) {
	default: break;	default: break;

	case 'b': // 1 string to match.	case '1': // 1 string to match.
	if (BuiltinName.substr(22, 3) != "128")	if (BuiltinName.substr(23, 2) != "28")
	break;
	return Intrinsic::x86_sse2_pcmpgt_b; // "__builtin_ia32_
	pcmpgtb128"
	case 'd': // 1 string to match.
	if (BuiltinName.substr(22, 3) != "128")
	break;	break;

	return Intrinsic::x86_sse2_pcmpgt_d; // "__builtin_ia32_	return Intrinsic::x86_sse41_pblendw; // "__builtin_ia32_
	pcmpgtd128"	pblendw128"
	case 'w': // 1 string to match.	case '2': // 1 string to match.
	if (BuiltinName.substr(22, 3) != "128")	if (BuiltinName.substr(23, 2) != "56")
	break;	break;

	return Intrinsic::x86_sse2_pcmpgt_w; // "__builtin_ia32_ pcmpgtw128"	return Intrinsic::x86_avx2_pblendw; // "__builtin_ia32_ pblendw256"
	}	}
	break;	break;
	}	}
	break;	break;

	case 'h': // 2 strings to match.	case 'h': // 4 strings to match.
	switch (BuiltinName[17]) {	switch (BuiltinName[17]) {
	default: break;	default: break;

	case 'a': // 1 string to match.	case 'a': // 2 strings to match.
	if (BuiltinName.substr(18, 7) != "ddsw128")	if (BuiltinName.substr(18, 4) != "ddsw")
	break;	break;

	return Intrinsic::x86_ssse3_phadd_sw_128; // "__builtin_ia32_	switch (BuiltinName[22]) {
	phaddsw128"	default: break;
	case 's': // 1 string to match.	case '1': // 1 string to match.
	if (BuiltinName.substr(18, 7) != "ubsw128")	if (BuiltinName.substr(23, 2) != "28")
		break;
		return Intrinsic::x86_ssse3_phadd_sw_128; // "__builtin_ia32_
		phaddsw128"
		case '2': // 1 string to match.
		if (BuiltinName.substr(23, 2) != "56")
		break;
		return Intrinsic::x86_avx2_phadd_sw; // "__builtin_ia32_
		phaddsw256"
		}
		break;
		case 's': // 2 strings to match.
		if (BuiltinName.substr(18, 4) != "ubsw")
	break;	break;

	return Intrinsic::x86_ssse3_phsub_sw_128; // "__builtin_ia32_	switch (BuiltinName[22]) {
	phsubsw128"	default: break;
		case '1': // 1 string to match.
		if (BuiltinName.substr(23, 2) != "28")
		break;
		return Intrinsic::x86_ssse3_phsub_sw_128; // "__builtin_ia32_
		phsubsw128"
		case '2': // 1 string to match.
		if (BuiltinName.substr(23, 2) != "56")
		break;
		return Intrinsic::x86_avx2_phsub_sw; // "__builtin_ia32_
		phsubsw256"
		}
		break;
	}	}
	break;	break;

	case 'm': // 3 strings to match.	case 'm': // 6 strings to match.
	switch (BuiltinName[17]) {	switch (BuiltinName[17]) {
	default: break;	default: break;

	case 'a': // 1 string to match.	case 'a': // 2 strings to match.
	if (BuiltinName.substr(18, 7) != "ddwd128")	if (BuiltinName.substr(18, 4) != "ddwd")
	break;	break;

	return Intrinsic::x86_sse2_pmadd_wd; // "__builtin_ia32_pmaddwd1	switch (BuiltinName[22]) {
	28"	default: break;
	case 'u': // 2 strings to match.	case '1': // 1 string to match.
		if (BuiltinName.substr(23, 2) != "28")
		break;
		return Intrinsic::x86_sse2_pmadd_wd; // "__builtin_ia32_
		pmaddwd128"
		case '2': // 1 string to match.
		if (BuiltinName.substr(23, 2) != "56")
		break;
		return Intrinsic::x86_avx2_pmadd_wd; // "__builtin_ia32_
		pmaddwd256"
		}
		break;
		case 'u': // 4 strings to match.
	if (BuiltinName[18] != 'l')	if (BuiltinName[18] != 'l')
	break;	break;
	switch (BuiltinName[19]) {	switch (BuiltinName[19]) {
	default: break;	default: break;

	case 'h': // 1 string to match.	case 'h': // 2 strings to match.
	if (BuiltinName.substr(20, 5) != "uw128")	if (BuiltinName.substr(20, 2) != "uw")
	break;	break;

	return Intrinsic::x86_sse2_pmulhu_w; // "__builtin_ia32_	switch (BuiltinName[22]) {
	pmulhuw128"	default: break;
	case 'u': // 1 string to match.	case '1': // 1 string to match.
	if (BuiltinName.substr(20, 5) != "dq128")	if (BuiltinName.substr(23, 2) != "28")
		break;
		return Intrinsic::x86_sse2_pmulhu_w; // "__builtin_ia32_
		pmulhuw128"
		case '2': // 1 string to match.
		if (BuiltinName.substr(23, 2) != "56")
		break;
		return Intrinsic::x86_avx2_pmulhu_w; // "__builtin_ia32_
		pmulhuw256"
		}
		break;
		case 'u': // 2 strings to match.
		if (BuiltinName.substr(20, 2) != "dq")
	break;	break;

	return Intrinsic::x86_sse2_pmulu_dq; // "__builtin_ia32_	switch (BuiltinName[22]) {
	pmuludq128"	default: break;
		case '1': // 1 string to match.
		if (BuiltinName.substr(23, 2) != "28")
		break;
		return Intrinsic::x86_sse2_pmulu_dq; // "__builtin_ia32_
		pmuludq128"
		case '2': // 1 string to match.
		if (BuiltinName.substr(23, 2) != "56")
		break;
		return Intrinsic::x86_avx2_pmulu_dq; // "__builtin_ia32_
		pmuludq256"
		}
		break;
	}	}
	break;	break;
	}	}
	break;	break;

	case 's': // 4 strings to match.	case 's': // 8 strings to match.
	switch (BuiltinName[17]) {	switch (BuiltinName[17]) {
	default: break;	default: break;

	case 'l': // 1 string to match.	case 'l': // 2 strings to match.
	if (BuiltinName.substr(18, 7) != "ldqi128")	if (BuiltinName.substr(18, 4) != "ldqi")
	break;	break;

	return Intrinsic::x86_sse2_psll_dq; // "__builtin_ia32_pslldqi1	switch (BuiltinName[22]) {
	28"	default: break;
	case 'r': // 1 string to match.	case '1': // 1 string to match.
	if (BuiltinName.substr(18, 7) != "ldqi128")	if (BuiltinName.substr(23, 2) != "28")
		break;
		return Intrinsic::x86_sse2_psll_dq; // "__builtin_ia32_
		pslldqi128"
		case '2': // 1 string to match.
		if (BuiltinName.substr(23, 2) != "56")
		break;
		return Intrinsic::x86_avx2_psll_dq; // "__builtin_ia32_
		pslldqi256"
		}
		break;
		case 'r': // 2 strings to match.
		if (BuiltinName.substr(18, 4) != "ldqi")
	break;	break;

	return Intrinsic::x86_sse2_psrl_dq; // "__builtin_ia32_psrldqi1	switch (BuiltinName[22]) {
	28"	default: break;
	case 'u': // 2 strings to match.	case '1': // 1 string to match.
		if (BuiltinName.substr(23, 2) != "28")
		break;
		return Intrinsic::x86_sse2_psrl_dq; // "__builtin_ia32_
		psrldqi128"
		case '2': // 1 string to match.
		if (BuiltinName.substr(23, 2) != "56")
		break;
		return Intrinsic::x86_avx2_psrl_dq; // "__builtin_ia32_
		psrldqi256"
		}
		break;
		case 'u': // 4 strings to match.
	if (BuiltinName.substr(18, 3) != "bus")	if (BuiltinName.substr(18, 3) != "bus")
	break;	break;
	switch (BuiltinName[21]) {	switch (BuiltinName[21]) {
	default: break;	default: break;

	case 'b': // 1 string to match.	case 'b': // 2 strings to match.
	if (BuiltinName.substr(22, 3) != "128")	switch (BuiltinName[22]) {
	break;	default: break;
	return Intrinsic::x86_sse2_psubus_b; // "__builtin_ia32_	case '1': // 1 string to match.
	psubusb128"	if (BuiltinName.substr(23, 2) != "28")
	case 'w': // 1 string to match.	break;
	if (BuiltinName.substr(22, 3) != "128")	return Intrinsic::x86_sse2_psubus_b; // "__builtin_ia32_
	break;	psubusb128"
	return Intrinsic::x86_sse2_psubus_w; // "__builtin_ia32_	case '2': // 1 string to match.
	psubusw128"	if (BuiltinName.substr(23, 2) != "56")
		break;
		return Intrinsic::x86_avx2_psubus_b; // "__builtin_ia32_
		psubusb256"
		}
		break;
		case 'w': // 2 strings to match.
		switch (BuiltinName[22]) {
		default: break;
		case '1': // 1 string to match.
		if (BuiltinName.substr(23, 2) != "28")
		break;
		return Intrinsic::x86_sse2_psubus_w; // "__builtin_ia32_
		psubusw128"
		case '2': // 1 string to match.
		if (BuiltinName.substr(23, 2) != "56")
		break;
		return Intrinsic::x86_avx2_psubus_w; // "__builtin_ia32_
		psubusw256"
		}
		break;
	}	}
	break;	break;
	}	}
	break;	break;
	}	}
	break;	break;

	case 'r': // 3 strings to match.	case 'r': // 7 strings to match.
	switch (BuiltinName[16]) {	switch (BuiltinName[16]) {
	default: break;	default: break;

		case 'd': // 4 strings to match.
		switch (BuiltinName[17]) {
		default: break;
		case 'f': // 2 strings to match.
		if (BuiltinName.substr(18, 5) != "sbase")
		break;
		switch (BuiltinName[23]) {
		default: break;
		case '3': // 1 string to match.
		if (BuiltinName[24] != '2')
		break;
		return Intrinsic::x86_rdfsbase_32; // "__builtin_ia32_rdfsbase
		32"
		case '6': // 1 string to match.
		if (BuiltinName[24] != '4')
		break;
		return Intrinsic::x86_rdfsbase_64; // "__builtin_ia32_rdfsbase
		64"
		}
		break;
		case 'g': // 2 strings to match.
		if (BuiltinName.substr(18, 5) != "sbase")
		break;
		switch (BuiltinName[23]) {
		default: break;
		case '3': // 1 string to match.
		if (BuiltinName[24] != '2')
		break;
		return Intrinsic::x86_rdgsbase_32; // "__builtin_ia32_rdgsbase
		32"
		case '6': // 1 string to match.
		if (BuiltinName[24] != '4')
		break;
		return Intrinsic::x86_rdgsbase_64; // "__builtin_ia32_rdgsbase
		64"
		}
		break;
		}
		break;
	case 'o': // 2 strings to match.	case 'o': // 2 strings to match.
	if (BuiltinName.substr(17, 4) != "undp")	if (BuiltinName.substr(17, 4) != "undp")
	break;	break;
	switch (BuiltinName[21]) {	switch (BuiltinName[21]) {
	default: break;	default: break;
	case 'd': // 1 string to match.	case 'd': // 1 string to match.
	if (BuiltinName.substr(22, 3) != "256")	if (BuiltinName.substr(22, 3) != "256")
	break;	break;
	return Intrinsic::x86_avx_round_pd_256; // "__builtin_ia32_ roundpd256"	return Intrinsic::x86_avx_round_pd_256; // "__builtin_ia32_ roundpd256"
	case 's': // 1 string to match.	case 's': // 1 string to match.

	skipping to change at line 19999	skipping to change at line 37798
	if (BuiltinName.substr(17, 7) != "estnzcp")	if (BuiltinName.substr(17, 7) != "estnzcp")
	break;	break;
	switch (BuiltinName[24]) {	switch (BuiltinName[24]) {
	default: break;	default: break;
	case 'd': // 1 string to match.	case 'd': // 1 string to match.
	return Intrinsic::x86_avx_vtestnzc_pd; // "__builtin_ia32_ vtestnzcpd"	return Intrinsic::x86_avx_vtestnzc_pd; // "__builtin_ia32_ vtestnzcpd"
	case 's': // 1 string to match.	case 's': // 1 string to match.
	return Intrinsic::x86_avx_vtestnzc_ps; // "__builtin_ia32_ vtestnzcps"	return Intrinsic::x86_avx_vtestnzc_ps; // "__builtin_ia32_ vtestnzcps"
	}	}
	break;	break;

	case 'z': // 1 string to match.	case 'z': // 1 string to match.
	if (BuiltinName.substr(17, 8) != "eroupper")	if (BuiltinName.substr(17, 8) != "eroupper")
		break;
		return Intrinsic::x86_avx_vzeroupper; // "__builtin_ia32_vzeroupp
		er"
		}
		break;
		case 'w': // 4 strings to match.
		if (BuiltinName[16] != 'r')
		break;
		switch (BuiltinName[17]) {
		default: break;
		case 'f': // 2 strings to match.
		if (BuiltinName.substr(18, 5) != "sbase")
		break;
		switch (BuiltinName[23]) {
		default: break;
		case '3': // 1 string to match.
		if (BuiltinName[24] != '2')
		break;
		return Intrinsic::x86_wrfsbase_32; // "__builtin_ia32_wrfsbase
		32"
		case '6': // 1 string to match.
		if (BuiltinName[24] != '4')
		break;
		return Intrinsic::x86_wrfsbase_64; // "__builtin_ia32_wrfsbase
		64"
		}
		break;
		case 'g': // 2 strings to match.
		if (BuiltinName.substr(18, 5) != "sbase")
	break;	break;

	return Intrinsic::x86_avx_vzeroupper; // "__builtin_ia32_vzeroupp	switch (BuiltinName[23]) {
	er"	default: break;
		case '3': // 1 string to match.
		if (BuiltinName[24] != '2')
		break;
		return Intrinsic::x86_wrgsbase_32; // "__builtin_ia32_wrgsbase
		32"
		case '6': // 1 string to match.
		if (BuiltinName[24] != '4')
		break;
		return Intrinsic::x86_wrgsbase_64; // "__builtin_ia32_wrgsbase
		64"
		}
		break;
	}	}
	break;	break;
	}	}
	break;	break;

	case 26: // 45 strings to match.	case 26: // 73 strings to match.
	if (BuiltinName.substr(0, 15) != "__builtin_ia32_")	if (BuiltinName.substr(0, 15) != "__builtin_ia32_")
	break;	break;
	switch (BuiltinName[15]) {	switch (BuiltinName[15]) {
	default: break;	default: break;
	case 'a': // 2 strings to match.	case 'a': // 2 strings to match.
	if (BuiltinName.substr(16, 6) != "ddsubp")	if (BuiltinName.substr(16, 6) != "ddsubp")
	break;	break;
	switch (BuiltinName[22]) {	switch (BuiltinName[22]) {
	default: break;	default: break;
	case 'd': // 1 string to match.	case 'd': // 1 string to match.

	skipping to change at line 20118	skipping to change at line 37954
	break;	break;
	return Intrinsic::x86_sse_cvttss2si64; // "__builtin_ia32_ cvttss2si64"	return Intrinsic::x86_sse_cvttss2si64; // "__builtin_ia32_ cvttss2si64"
	}	}
	break;	break;
	}	}
	break;	break;
	case 'i': // 1 string to match.	case 'i': // 1 string to match.
	if (BuiltinName.substr(16, 10) != "nsertps128")	if (BuiltinName.substr(16, 10) != "nsertps128")
	break;	break;
	return Intrinsic::x86_sse41_insertps; // "__builtin_ia32_insertps 128"	return Intrinsic::x86_sse41_insertps; // "__builtin_ia32_insertps 128"

	case 'm': // 4 strings to match.	case 'm': // 5 strings to match.
	switch (BuiltinName[16]) {	switch (BuiltinName[16]) {
	default: break;	default: break;
	case 'a': // 2 strings to match.	case 'a': // 2 strings to match.
	if (BuiltinName.substr(17, 8) != "skstorep")	if (BuiltinName.substr(17, 8) != "skstorep")
	break;	break;
	switch (BuiltinName[25]) {	switch (BuiltinName[25]) {
	default: break;	default: break;
	case 'd': // 1 string to match.	case 'd': // 1 string to match.
	return Intrinsic::x86_avx_maskstore_pd; // "__builtin_ia32_ maskstorepd"	return Intrinsic::x86_avx_maskstore_pd; // "__builtin_ia32_ maskstorepd"
	case 's': // 1 string to match.	case 's': // 1 string to match.
	return Intrinsic::x86_avx_maskstore_ps; // "__builtin_ia32_ maskstoreps"	return Intrinsic::x86_avx_maskstore_ps; // "__builtin_ia32_ maskstoreps"
	}	}
	break;	break;

	case 'o': // 2 strings to match.	case 'o': // 3 strings to match.
	if (BuiltinName.substr(17, 5) != "vmskp")	if (BuiltinName[17] != 'v')
	break;	break;

	switch (BuiltinName[22]) {	switch (BuiltinName[18]) {
	default: break;	default: break;

	case 'd': // 1 string to match.	case 'm': // 2 strings to match.
	if (BuiltinName.substr(23, 3) != "256")	if (BuiltinName.substr(19, 3) != "skp")
	break;	break;

	return Intrinsic::x86_avx_movmsk_pd_256; // "__builtin_ia32_	switch (BuiltinName[22]) {
	movmskpd256"	default: break;
	case 's': // 1 string to match.	case 'd': // 1 string to match.
	if (BuiltinName.substr(23, 3) != "256")	if (BuiltinName.substr(23, 3) != "256")
		break;
		return Intrinsic::x86_avx_movmsk_pd_256; // "__builtin_ia32_
		movmskpd256"
		case 's': // 1 string to match.
		if (BuiltinName.substr(23, 3) != "256")
		break;
		return Intrinsic::x86_avx_movmsk_ps_256; // "__builtin_ia32_
		movmskps256"
		}
		break;
		case 'n': // 1 string to match.
		if (BuiltinName.substr(19, 7) != "tdqa256")
	break;	break;

	return Intrinsic::x86_avx_movmsk_ps_256; // "__builtin_ia32_ movmskps256"	return Intrinsic::x86_avx2_movntdqa; // "__builtin_ia32_movntdqa 256"
	}	}
	break;	break;
	}	}
	break;	break;

	case 'p': // 21 strings to match.	case 'p': // 40 strings to match.
	switch (BuiltinName[16]) {	switch (BuiltinName[16]) {
	default: break;	default: break;

	case 'a': // 4 strings to match.	case 'a': // 8 strings to match.
	if (BuiltinName.substr(17, 2) != "ck")	if (BuiltinName.substr(17, 2) != "ck")
	break;	break;
	switch (BuiltinName[19]) {	switch (BuiltinName[19]) {
	default: break;	default: break;

	case 's': // 2 strings to match.	case 's': // 4 strings to match.
	if (BuiltinName[20] != 's')	if (BuiltinName[20] != 's')
	break;	break;
	switch (BuiltinName[21]) {	switch (BuiltinName[21]) {
	default: break;	default: break;

	case 'd': // 1 string to match.	case 'd': // 2 strings to match.
	if (BuiltinName.substr(22, 4) != "w128")	if (BuiltinName[22] != 'w')
	break;	break;

	return Intrinsic::x86_sse2_packssdw_128; // "__builtin_ia32_	switch (BuiltinName[23]) {
	packssdw128"	default: break;
	case 'w': // 1 string to match.	case '1': // 1 string to match.
	if (BuiltinName.substr(22, 4) != "b128")	if (BuiltinName.substr(24, 2) != "28")
		break;
		return Intrinsic::x86_sse2_packssdw_128; // "__builtin_ia32_
		packssdw128"
		case '2': // 1 string to match.
		if (BuiltinName.substr(24, 2) != "56")
		break;
		return Intrinsic::x86_avx2_packssdw; // "__builtin_ia32_
		packssdw256"
		}
		break;
		case 'w': // 2 strings to match.
		if (BuiltinName[22] != 'b')
	break;	break;

	return Intrinsic::x86_sse2_packsswb_128; // "__builtin_ia32_	switch (BuiltinName[23]) {
	packsswb128"	default: break;
		case '1': // 1 string to match.
		if (BuiltinName.substr(24, 2) != "28")
		break;
		return Intrinsic::x86_sse2_packsswb_128; // "__builtin_ia32_
		packsswb128"
		case '2': // 1 string to match.
		if (BuiltinName.substr(24, 2) != "56")
		break;
		return Intrinsic::x86_avx2_packsswb; // "__builtin_ia32_
		packsswb256"
		}
		break;
	}	}
	break;	break;

	case 'u': // 2 strings to match.	case 'u': // 4 strings to match.
	if (BuiltinName[20] != 's')	if (BuiltinName[20] != 's')
	break;	break;
	switch (BuiltinName[21]) {	switch (BuiltinName[21]) {
	default: break;	default: break;

	case 'd': // 1 string to match.	case 'd': // 2 strings to match.
	if (BuiltinName.substr(22, 4) != "w128")	if (BuiltinName[22] != 'w')
	break;	break;

	return Intrinsic::x86_sse41_packusdw; // "__builtin_ia32_	switch (BuiltinName[23]) {
	packusdw128"	default: break;
	case 'w': // 1 string to match.	case '1': // 1 string to match.
	if (BuiltinName.substr(22, 4) != "b128")	if (BuiltinName.substr(24, 2) != "28")
		break;
		return Intrinsic::x86_sse41_packusdw; // "__builtin_ia32_
		packusdw128"
		case '2': // 1 string to match.
		if (BuiltinName.substr(24, 2) != "56")
		break;
		return Intrinsic::x86_avx2_packusdw; // "__builtin_ia32_
		packusdw256"
		}
		break;
		case 'w': // 2 strings to match.
		if (BuiltinName[22] != 'b')
	break;	break;

	return Intrinsic::x86_sse2_packuswb_128; // "__builtin_ia32_	switch (BuiltinName[23]) {
	packuswb128"	default: break;
		case '1': // 1 string to match.
		if (BuiltinName.substr(24, 2) != "28")
		break;
		return Intrinsic::x86_sse2_packuswb_128; // "__builtin_ia32_
		packuswb128"
		case '2': // 1 string to match.
		if (BuiltinName.substr(24, 2) != "56")
		break;
		return Intrinsic::x86_avx2_packuswb; // "__builtin_ia32_
		packuswb256"
		}
		break;
	}	}
	break;	break;
	}	}
	break;	break;

	case 'b': // 1 string to match.	case 'b': // 2 strings to match.
	if (BuiltinName.substr(17, 9) != "lendvb128")	if (BuiltinName.substr(17, 6) != "lendvb")
	break;	break;

	return Intrinsic::x86_sse41_pblendvb; // "__builtin_ia32_pblendvb	switch (BuiltinName[23]) {
	128"	default: break;
	case 'm': // 14 strings to match.	case '1': // 1 string to match.
		if (BuiltinName.substr(24, 2) != "28")
		break;
		return Intrinsic::x86_sse41_pblendvb; // "__builtin_ia32_
		pblendvb128"
		case '2': // 1 string to match.
		if (BuiltinName.substr(24, 2) != "56")
		break;
		return Intrinsic::x86_avx2_pblendvb; // "__builtin_ia32_pblendvb
		256"
		}
		break;
		case 'm': // 28 strings to match.
	switch (BuiltinName[17]) {	switch (BuiltinName[17]) {
	default: break;	default: break;

	case 'o': // 13 strings to match.	case 'o': // 26 strings to match.
	if (BuiltinName[18] != 'v')	if (BuiltinName[18] != 'v')
	break;	break;
	switch (BuiltinName[19]) {	switch (BuiltinName[19]) {
	default: break;	default: break;

	case 'm': // 1 string to match.	case 'm': // 2 strings to match.
	if (BuiltinName.substr(20, 6) != "skb128")	if (BuiltinName.substr(20, 3) != "skb")
	break;	break;

	return Intrinsic::x86_sse2_pmovmskb_128; // "__builtin_ia32_	switch (BuiltinName[23]) {
	pmovmskb128"	default: break;
	case 's': // 6 strings to match.	case '1': // 1 string to match.
		if (BuiltinName.substr(24, 2) != "28")
		break;
		return Intrinsic::x86_sse2_pmovmskb_128; // "__builtin_ia32_
		pmovmskb128"
		case '2': // 1 string to match.
		if (BuiltinName.substr(24, 2) != "56")
		break;
		return Intrinsic::x86_avx2_pmovmskb; // "__builtin_ia32_
		pmovmskb256"
		}
		break;
		case 's': // 12 strings to match.
	if (BuiltinName[20] != 'x')	if (BuiltinName[20] != 'x')
	break;	break;
	switch (BuiltinName[21]) {	switch (BuiltinName[21]) {
	default: break;	default: break;

	case 'b': // 3 strings to match.	case 'b': // 6 strings to match.
	switch (BuiltinName[22]) {	switch (BuiltinName[22]) {
	default: break;	default: break;

	case 'd': // 1 string to match.	case 'd': // 2 strings to match.
	if (BuiltinName.substr(23, 3) != "128")	switch (BuiltinName[23]) {
	break;	default: break;
	return Intrinsic::x86_sse41_pmovsxbd; // "__builtin_ia32_	case '1': // 1 string to match.
	pmovsxbd128"	if (BuiltinName.substr(24, 2) != "28")
	case 'q': // 1 string to match.	break;
	if (BuiltinName.substr(23, 3) != "128")	return Intrinsic::x86_sse41_pmovsxbd; // "__built
	break;	in_ia32_pmovsxbd128"
	return Intrinsic::x86_sse41_pmovsxbq; // "__builtin_ia32_	case '2': // 1 string to match.
	pmovsxbq128"	if (BuiltinName.substr(24, 2) != "56")
	case 'w': // 1 string to match.	break;
	if (BuiltinName.substr(23, 3) != "128")	return Intrinsic::x86_avx2_pmovsxbd; // "__builtin_ia32_
	break;	pmovsxbd256"
	return Intrinsic::x86_sse41_pmovsxbw; // "__builtin_ia32_	}
	pmovsxbw128"	break;
		case 'q': // 2 strings to match.
		switch (BuiltinName[23]) {
		default: break;
		case '1': // 1 string to match.
		if (BuiltinName.substr(24, 2) != "28")
		break;
		return Intrinsic::x86_sse41_pmovsxbq; // "__built
		in_ia32_pmovsxbq128"
		case '2': // 1 string to match.
		if (BuiltinName.substr(24, 2) != "56")
		break;
		return Intrinsic::x86_avx2_pmovsxbq; // "__builtin_ia32_
		pmovsxbq256"
		}
		break;
		case 'w': // 2 strings to match.
		switch (BuiltinName[23]) {
		default: break;
		case '1': // 1 string to match.
		if (BuiltinName.substr(24, 2) != "28")
		break;
		return Intrinsic::x86_sse41_pmovsxbw; // "__built
		in_ia32_pmovsxbw128"
		case '2': // 1 string to match.
		if (BuiltinName.substr(24, 2) != "56")
		break;
		return Intrinsic::x86_avx2_pmovsxbw; // "__builtin_ia32_
		pmovsxbw256"
		}
		break;
	}	}
	break;	break;

	case 'd': // 1 string to match.	case 'd': // 2 strings to match.
	if (BuiltinName.substr(22, 4) != "q128")	if (BuiltinName[22] != 'q')
	break;	break;

	return Intrinsic::x86_sse41_pmovsxdq; // "__builtin_ia32_	switch (BuiltinName[23]) {
	pmovsxdq128"
	case 'w': // 2 strings to match.
	switch (BuiltinName[22]) {
	default: break;	default: break;

	case 'd': // 1 string to match.	case '1': // 1 string to match.
	if (BuiltinName.substr(23, 3) != "128")	if (BuiltinName.substr(24, 2) != "28")
	break;	break;

	return Intrinsic::x86_sse41_pmovsxwd; // "__builtin_ia32_	return Intrinsic::x86_sse41_pmovsxdq; // "__builtin_ia32_
	pmovsxwd128"	pmovsxdq128"
	case 'q': // 1 string to match.	case '2': // 1 string to match.
	if (BuiltinName.substr(23, 3) != "128")	if (BuiltinName.substr(24, 2) != "56")
	break;	break;

	return Intrinsic::x86_sse41_pmovsxwq; // "__builtin_ia32_	return Intrinsic::x86_avx2_pmovsxdq; // "__builtin_ia32_
	pmovsxwq128"	pmovsxdq256"
		}
		break;
		case 'w': // 4 strings to match.
		switch (BuiltinName[22]) {
		default: break;
		case 'd': // 2 strings to match.
		switch (BuiltinName[23]) {
		default: break;
		case '1': // 1 string to match.
		if (BuiltinName.substr(24, 2) != "28")
		break;
		return Intrinsic::x86_sse41_pmovsxwd; // "__built
		in_ia32_pmovsxwd128"
		case '2': // 1 string to match.
		if (BuiltinName.substr(24, 2) != "56")
		break;
		return Intrinsic::x86_avx2_pmovsxwd; // "__builtin_ia32_
		pmovsxwd256"
		}
		break;
		case 'q': // 2 strings to match.
		switch (BuiltinName[23]) {
		default: break;
		case '1': // 1 string to match.
		if (BuiltinName.substr(24, 2) != "28")
		break;
		return Intrinsic::x86_sse41_pmovsxwq; // "__built
		in_ia32_pmovsxwq128"
		case '2': // 1 string to match.
		if (BuiltinName.substr(24, 2) != "56")
		break;
		return Intrinsic::x86_avx2_pmovsxwq; // "__builtin_ia32_
		pmovsxwq256"
		}
		break;
	}	}
	break;	break;
	}	}
	break;	break;

	case 'z': // 6 strings to match.	case 'z': // 12 strings to match.
	if (BuiltinName[20] != 'x')	if (BuiltinName[20] != 'x')
	break;	break;
	switch (BuiltinName[21]) {	switch (BuiltinName[21]) {
	default: break;	default: break;

	case 'b': // 3 strings to match.	case 'b': // 6 strings to match.
	switch (BuiltinName[22]) {	switch (BuiltinName[22]) {
	default: break;	default: break;

	case 'd': // 1 string to match.	case 'd': // 2 strings to match.
	if (BuiltinName.substr(23, 3) != "128")	switch (BuiltinName[23]) {
	break;	default: break;
	return Intrinsic::x86_sse41_pmovzxbd; // "__builtin_ia32_	case '1': // 1 string to match.
	pmovzxbd128"	if (BuiltinName.substr(24, 2) != "28")
	case 'q': // 1 string to match.	break;
	if (BuiltinName.substr(23, 3) != "128")	return Intrinsic::x86_sse41_pmovzxbd; // "__built
	break;	in_ia32_pmovzxbd128"
	return Intrinsic::x86_sse41_pmovzxbq; // "__builtin_ia32_	case '2': // 1 string to match.
	pmovzxbq128"	if (BuiltinName.substr(24, 2) != "56")
	case 'w': // 1 string to match.	break;
	if (BuiltinName.substr(23, 3) != "128")	return Intrinsic::x86_avx2_pmovzxbd; // "__builtin_ia32_
	break;	pmovzxbd256"
	return Intrinsic::x86_sse41_pmovzxbw; // "__builtin_ia32_	}
	pmovzxbw128"	break;
		case 'q': // 2 strings to match.
		switch (BuiltinName[23]) {
		default: break;
		case '1': // 1 string to match.
		if (BuiltinName.substr(24, 2) != "28")
		break;
		return Intrinsic::x86_sse41_pmovzxbq; // "__built
		in_ia32_pmovzxbq128"
		case '2': // 1 string to match.
		if (BuiltinName.substr(24, 2) != "56")
		break;
		return Intrinsic::x86_avx2_pmovzxbq; // "__builtin_ia32_
		pmovzxbq256"
		}
		break;
		case 'w': // 2 strings to match.
		switch (BuiltinName[23]) {
		default: break;
		case '1': // 1 string to match.
		if (BuiltinName.substr(24, 2) != "28")
		break;
		return Intrinsic::x86_sse41_pmovzxbw; // "__built
		in_ia32_pmovzxbw128"
		case '2': // 1 string to match.
		if (BuiltinName.substr(24, 2) != "56")
		break;
		return Intrinsic::x86_avx2_pmovzxbw; // "__builtin_ia32_
		pmovzxbw256"
		}
		break;
	}	}
	break;	break;

	case 'd': // 1 string to match.	case 'd': // 2 strings to match.
	if (BuiltinName.substr(22, 4) != "q128")	if (BuiltinName[22] != 'q')
	break;	break;

	return Intrinsic::x86_sse41_pmovzxdq; // "__builtin_ia32_	switch (BuiltinName[23]) {
	pmovzxdq128"
	case 'w': // 2 strings to match.
	switch (BuiltinName[22]) {
	default: break;	default: break;

	case 'd': // 1 string to match.	case '1': // 1 string to match.
	if (BuiltinName.substr(23, 3) != "128")	if (BuiltinName.substr(24, 2) != "28")
	break;	break;

	return Intrinsic::x86_sse41_pmovzxwd; // "__builtin_ia32_	return Intrinsic::x86_sse41_pmovzxdq; // "__builtin_ia32_
	pmovzxwd128"	pmovzxdq128"
	case 'q': // 1 string to match.	case '2': // 1 string to match.
	if (BuiltinName.substr(23, 3) != "128")	if (BuiltinName.substr(24, 2) != "56")
	break;	break;

	return Intrinsic::x86_sse41_pmovzxwq; // "__builtin_ia32_	return Intrinsic::x86_avx2_pmovzxdq; // "__builtin_ia32_
	pmovzxwq128"	pmovzxdq256"
		}
		break;
		case 'w': // 4 strings to match.
		switch (BuiltinName[22]) {
		default: break;
		case 'd': // 2 strings to match.
		switch (BuiltinName[23]) {
		default: break;
		case '1': // 1 string to match.
		if (BuiltinName.substr(24, 2) != "28")
		break;
		return Intrinsic::x86_sse41_pmovzxwd; // "__built
		in_ia32_pmovzxwd128"
		case '2': // 1 string to match.
		if (BuiltinName.substr(24, 2) != "56")
		break;
		return Intrinsic::x86_avx2_pmovzxwd; // "__builtin_ia32_
		pmovzxwd256"
		}
		break;
		case 'q': // 2 strings to match.
		switch (BuiltinName[23]) {
		default: break;
		case '1': // 1 string to match.
		if (BuiltinName.substr(24, 2) != "28")
		break;
		return Intrinsic::x86_sse41_pmovzxwq; // "__built
		in_ia32_pmovzxwq128"
		case '2': // 1 string to match.
		if (BuiltinName.substr(24, 2) != "56")
		break;
		return Intrinsic::x86_avx2_pmovzxwq; // "__builtin_ia32_
		pmovzxwq256"
		}
		break;
	}	}
	break;	break;
	}	}
	break;	break;
	}	}
	break;	break;

	case 'u': // 1 string to match.	case 'u': // 2 strings to match.
	if (BuiltinName.substr(18, 8) != "lhrsw128")	if (BuiltinName.substr(18, 5) != "lhrsw")
	break;	break;

	return Intrinsic::x86_ssse3_pmul_hr_sw_128; // "__builtin_ia32_	switch (BuiltinName[23]) {
	pmulhrsw128"	default: break;
		case '1': // 1 string to match.
		if (BuiltinName.substr(24, 2) != "28")
		break;
		return Intrinsic::x86_ssse3_pmul_hr_sw_128; // "__built
		in_ia32_pmulhrsw128"
		case '2': // 1 string to match.
		if (BuiltinName.substr(24, 2) != "56")
		break;
		return Intrinsic::x86_avx2_pmul_hr_sw; // "__builtin_ia32_
		pmulhrsw256"
		}
		break;
	}	}
	break;	break;
	case 't': // 2 strings to match.	case 't': // 2 strings to match.
	if (BuiltinName.substr(17, 6) != "estnzc")	if (BuiltinName.substr(17, 6) != "estnzc")
	break;	break;
	switch (BuiltinName[23]) {	switch (BuiltinName[23]) {
	default: break;	default: break;
	case '1': // 1 string to match.	case '1': // 1 string to match.
	if (BuiltinName.substr(24, 2) != "28")	if (BuiltinName.substr(24, 2) != "28")
	break;	break;

	skipping to change at line 20338	skipping to change at line 38374
	break;	break;
	return Intrinsic::x86_avx_storeu_pd_256; // "__builtin_ia32_ storeupd256"	return Intrinsic::x86_avx_storeu_pd_256; // "__builtin_ia32_ storeupd256"
	case 's': // 1 string to match.	case 's': // 1 string to match.
	if (BuiltinName.substr(23, 3) != "256")	if (BuiltinName.substr(23, 3) != "256")
	break;	break;
	return Intrinsic::x86_avx_storeu_ps_256; // "__builtin_ia32_ storeups256"	return Intrinsic::x86_avx_storeu_ps_256; // "__builtin_ia32_ storeups256"
	}	}
	break;	break;
	}	}
	break;	break;

	case 'v': // 4 strings to match.	case 'v': // 12 strings to match.
	if (BuiltinName.substr(16, 4) != "test")	switch (BuiltinName[16]) {
	break;
	switch (BuiltinName[20]) {
	default: break;	default: break;

	case 'c': // 2 strings to match.	case 'f': // 8 strings to match.
	if (BuiltinName[21] != 'p')	if (BuiltinName[17] != 'm')
	break;	break;

	switch (BuiltinName[22]) {	switch (BuiltinName[18]) {
	default: break;	default: break;

	case 'd': // 1 string to match.	case 'a': // 4 strings to match.
	if (BuiltinName.substr(23, 3) != "256")	if (BuiltinName.substr(19, 2) != "dd")
	break;	break;

	return Intrinsic::x86_avx_vtestc_pd_256; // "__builtin_ia32_	switch (BuiltinName[21]) {
	vtestcpd256"	default: break;
	case 's': // 1 string to match.	case 'p': // 2 strings to match.
	if (BuiltinName.substr(23, 3) != "256")	switch (BuiltinName[22]) {
		default: break;
		case 'd': // 1 string to match.
		if (BuiltinName.substr(23, 3) != "256")
		break;
		return Intrinsic::x86_fma4_vfmadd_pd_256; // "__built
		in_ia32_vfmaddpd256"
		case 's': // 1 string to match.
		if (BuiltinName.substr(23, 3) != "256")
		break;
		return Intrinsic::x86_fma4_vfmadd_ps_256; // "__built
		in_ia32_vfmaddps256"
		}
		break;
		case 's': // 2 strings to match.
		if (BuiltinName.substr(22, 3) != "ubp")
		break;
		switch (BuiltinName[25]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_fma4_vfmaddsub_pd; // "__builtin_ia32_
		vfmaddsubpd"
		case 's': // 1 string to match.
		return Intrinsic::x86_fma4_vfmaddsub_ps; // "__builtin_ia32_
		vfmaddsubps"
		}
		break;
		}
		break;
		case 's': // 4 strings to match.
		if (BuiltinName.substr(19, 2) != "ub")
		break;
		switch (BuiltinName[21]) {
		default: break;
		case 'a': // 2 strings to match.
		if (BuiltinName.substr(22, 3) != "ddp")
		break;
		switch (BuiltinName[25]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_fma4_vfmsubadd_pd; // "__builtin_ia32_
		vfmsubaddpd"
		case 's': // 1 string to match.
		return Intrinsic::x86_fma4_vfmsubadd_ps; // "__builtin_ia32_
		vfmsubaddps"
		}
		break;
		case 'p': // 2 strings to match.
		switch (BuiltinName[22]) {
		default: break;
		case 'd': // 1 string to match.
		if (BuiltinName.substr(23, 3) != "256")
		break;
		return Intrinsic::x86_fma4_vfmsub_pd_256; // "__built
		in_ia32_vfmsubpd256"
		case 's': // 1 string to match.
		if (BuiltinName.substr(23, 3) != "256")
		break;
		return Intrinsic::x86_fma4_vfmsub_ps_256; // "__built
		in_ia32_vfmsubps256"
		}
	break;	break;

	return Intrinsic::x86_avx_vtestc_ps_256; // "__builtin_ia32_	}
	vtestcps256"	break;
	}	}
	break;	break;

	case 'z': // 2 strings to match.	case 't': // 4 strings to match.
	if (BuiltinName[21] != 'p')	if (BuiltinName.substr(17, 3) != "est")
	break;	break;

	switch (BuiltinName[22]) {	switch (BuiltinName[20]) {
	default: break;	default: break;

	case 'd': // 1 string to match.	case 'c': // 2 strings to match.
	if (BuiltinName.substr(23, 3) != "256")	if (BuiltinName[21] != 'p')
	break;	break;

	return Intrinsic::x86_avx_vtestz_pd_256; // "__builtin_ia32_	switch (BuiltinName[22]) {
	vtestzpd256"	default: break;
	case 's': // 1 string to match.	case 'd': // 1 string to match.
	if (BuiltinName.substr(23, 3) != "256")	if (BuiltinName.substr(23, 3) != "256")
		break;
		return Intrinsic::x86_avx_vtestc_pd_256; // "__builtin_ia32_
		vtestcpd256"
		case 's': // 1 string to match.
		if (BuiltinName.substr(23, 3) != "256")
		break;
		return Intrinsic::x86_avx_vtestc_ps_256; // "__builtin_ia32_
		vtestcps256"
		}
		break;
		case 'z': // 2 strings to match.
		if (BuiltinName[21] != 'p')
	break;	break;

	return Intrinsic::x86_avx_vtestz_ps_256; // "__builtin_ia32_	switch (BuiltinName[22]) {
	vtestzps256"	default: break;
		case 'd': // 1 string to match.
		if (BuiltinName.substr(23, 3) != "256")
		break;
		return Intrinsic::x86_avx_vtestz_pd_256; // "__builtin_ia32_
		vtestzpd256"
		case 's': // 1 string to match.
		if (BuiltinName.substr(23, 3) != "256")
		break;
		return Intrinsic::x86_avx_vtestz_ps_256; // "__builtin_ia32_
		vtestzps256"
		}
		break;
	}	}
	break;	break;
	}	}
	break;	break;
	}	}
	break;	break;

	case 27: // 15 strings to match.	case 27: // 24 strings to match.
	if (BuiltinName.substr(0, 15) != "__builtin_ia32_")	if (BuiltinName.substr(0, 15) != "__builtin_ia32_")
	break;	break;
	switch (BuiltinName[15]) {	switch (BuiltinName[15]) {
	default: break;	default: break;
	case 'c': // 2 strings to match.	case 'c': // 2 strings to match.
	if (BuiltinName.substr(16, 4) != "vttp")	if (BuiltinName.substr(16, 4) != "vttp")
	break;	break;
	switch (BuiltinName[20]) {	switch (BuiltinName[20]) {
	default: break;	default: break;
	case 'd': // 1 string to match.	case 'd': // 1 string to match.

	skipping to change at line 20401	skipping to change at line 38511
	case 's': // 1 string to match.	case 's': // 1 string to match.
	if (BuiltinName.substr(21, 6) != "2dq256")	if (BuiltinName.substr(21, 6) != "2dq256")
	break;	break;
	return Intrinsic::x86_avx_cvtt_ps2dq_256; // "__builtin_ia32_ cvttps2dq256"	return Intrinsic::x86_avx_cvtt_ps2dq_256; // "__builtin_ia32_ cvttps2dq256"
	}	}
	break;	break;
	case 'e': // 1 string to match.	case 'e': // 1 string to match.
	if (BuiltinName.substr(16, 11) != "xtractps128")	if (BuiltinName.substr(16, 11) != "xtractps128")
	break;	break;
	return Intrinsic::x86_sse41_extractps; // "__builtin_ia32_extractp s128"	return Intrinsic::x86_sse41_extractps; // "__builtin_ia32_extractp s128"

	case 'p': // 5 strings to match.	case 'm': // 2 strings to match.
		if (BuiltinName.substr(16, 7) != "askload")
		break;
		switch (BuiltinName[23]) {
		default: break;
		case 'd': // 1 string to match.
		if (BuiltinName.substr(24, 3) != "256")
		break;
		return Intrinsic::x86_avx2_maskload_d_256; // "__builtin_ia32_
		maskloadd256"
		case 'q': // 1 string to match.
		if (BuiltinName.substr(24, 3) != "256")
		break;
		return Intrinsic::x86_avx2_maskload_q_256; // "__builtin_ia32_
		maskloadq256"
		}
		break;
		case 'p': // 8 strings to match.
	switch (BuiltinName[16]) {	switch (BuiltinName[16]) {
	default: break;	default: break;
	case 'c': // 4 strings to match.	case 'c': // 4 strings to match.
	if (BuiltinName.substr(17, 2) != "mp")	if (BuiltinName.substr(17, 2) != "mp")
	break;	break;
	switch (BuiltinName[19]) {	switch (BuiltinName[19]) {
	default: break;	default: break;
	case 'e': // 2 strings to match.	case 'e': // 2 strings to match.
	if (BuiltinName.substr(20, 3) != "str")	if (BuiltinName.substr(20, 3) != "str")
	break;	break;

	skipping to change at line 20441	skipping to change at line 38566
	break;	break;
	return Intrinsic::x86_sse42_pcmpistri128; // "__builtin_ia32_ pcmpistri128"	return Intrinsic::x86_sse42_pcmpistri128; // "__builtin_ia32_ pcmpistri128"
	case 'm': // 1 string to match.	case 'm': // 1 string to match.
	if (BuiltinName.substr(24, 3) != "128")	if (BuiltinName.substr(24, 3) != "128")
	break;	break;
	return Intrinsic::x86_sse42_pcmpistrm128; // "__builtin_ia32_ pcmpistrm128"	return Intrinsic::x86_sse42_pcmpistrm128; // "__builtin_ia32_ pcmpistrm128"
	}	}
	break;	break;
	}	}
	break;	break;

	case 'm': // 1 string to match.	case 'e': // 2 strings to match.
	if (BuiltinName.substr(17, 10) != "addubsw128")	if (BuiltinName.substr(17, 6) != "rmvars")
		break;
		switch (BuiltinName[23]) {
		default: break;
		case 'f': // 1 string to match.
		if (BuiltinName.substr(24, 3) != "256")
		break;
		return Intrinsic::x86_avx2_permps; // "__builtin_ia32_permvars
		f256"
		case 'i': // 1 string to match.
		if (BuiltinName.substr(24, 3) != "256")
		break;
		return Intrinsic::x86_avx2_permd; // "__builtin_ia32_permvars
		i256"
		}
		break;
		case 'm': // 2 strings to match.
		if (BuiltinName.substr(17, 7) != "addubsw")
	break;	break;

	return Intrinsic::x86_ssse3_pmadd_ub_sw_128; // "__builtin_ia32_	switch (BuiltinName[24]) {
	pmaddubsw128"	default: break;
		case '1': // 1 string to match.
		if (BuiltinName.substr(25, 2) != "28")
		break;
		return Intrinsic::x86_ssse3_pmadd_ub_sw_128; // "__builtin_ia32_
		pmaddubsw128"
		case '2': // 1 string to match.
		if (BuiltinName.substr(25, 2) != "56")
		break;
		return Intrinsic::x86_avx2_pmadd_ub_sw; // "__builtin_ia32_
		pmaddubsw256"
		}
		break;
	}	}
	break;	break;

	case 'v': // 7 strings to match.	case 'v': // 11 strings to match.
	switch (BuiltinName[16]) {	switch (BuiltinName[16]) {
	default: break;	default: break;
	case 'b': // 1 string to match.	case 'b': // 1 string to match.
	if (BuiltinName.substr(17, 10) != "roadcastss")	if (BuiltinName.substr(17, 10) != "roadcastss")
	break;	break;

	return Intrinsic::x86_avx_vbroadcastss; // "__builtin_ia32_	return Intrinsic::x86_avx_vbroadcast_ss; // "__builtin_ia32_
	vbroadcastss"	vbroadcastss"
		case 'c': // 2 strings to match.
		if (BuiltinName.substr(17, 3) != "vtp")
		break;
		switch (BuiltinName[20]) {
		default: break;
		case 'h': // 1 string to match.
		if (BuiltinName.substr(21, 6) != "2ps256")
		break;
		return Intrinsic::x86_vcvtph2ps_256; // "__builtin_ia32_vcvtph2p
		s256"
		case 's': // 1 string to match.
		if (BuiltinName.substr(21, 6) != "2ph256")
		break;
		return Intrinsic::x86_vcvtps2ph_256; // "__builtin_ia32_vcvtps2p
		h256"
		}
		break;
	case 'e': // 2 strings to match.	case 'e': // 2 strings to match.
	if (BuiltinName.substr(17, 2) != "c_")	if (BuiltinName.substr(17, 2) != "c_")
	break;	break;
	switch (BuiltinName[19]) {	switch (BuiltinName[19]) {
	default: break;	default: break;
	case 'e': // 1 string to match.	case 'e': // 1 string to match.
	if (BuiltinName.substr(20, 7) != "xt_v4hi")	if (BuiltinName.substr(20, 7) != "xt_v4hi")
	break;	break;
	return Intrinsic::x86_mmx_pextr_w; // "__builtin_ia32_vec_ext_ v4hi"	return Intrinsic::x86_mmx_pextr_w; // "__builtin_ia32_vec_ext_ v4hi"
	case 's': // 1 string to match.	case 's': // 1 string to match.
	if (BuiltinName.substr(20, 7) != "et_v4hi")	if (BuiltinName.substr(20, 7) != "et_v4hi")
	break;	break;
	return Intrinsic::x86_mmx_pinsr_w; // "__builtin_ia32_vec_set_ v4hi"	return Intrinsic::x86_mmx_pinsr_w; // "__builtin_ia32_vec_set_ v4hi"
	}	}
	break;	break;

	case 'p': // 4 strings to match.	case 'f': // 4 strings to match.
	if (BuiltinName.substr(17, 5) != "ermil")	if (BuiltinName.substr(17, 2) != "nm")
	break;	break;

	switch (BuiltinName[22]) {	switch (BuiltinName[19]) {
	default: break;	default: break;

	case 'p': // 2 strings to match.	case 'a': // 2 strings to match.
		if (BuiltinName.substr(20, 3) != "ddp")
		break;
	switch (BuiltinName[23]) {	switch (BuiltinName[23]) {
	default: break;	default: break;
	case 'd': // 1 string to match.	case 'd': // 1 string to match.
	if (BuiltinName.substr(24, 3) != "256")	if (BuiltinName.substr(24, 3) != "256")
	break;	break;

	return Intrinsic::x86_avx_vpermil_pd_256; // "__builtin_ia32_ vpermilpd256"	return Intrinsic::x86_fma4_vfnmadd_pd_256; // "__builtin_ia32_ vfnmaddpd256"
	case 's': // 1 string to match.	case 's': // 1 string to match.
	if (BuiltinName.substr(24, 3) != "256")	if (BuiltinName.substr(24, 3) != "256")
	break;	break;

	return Intrinsic::x86_avx_vpermil_ps_256; // "__builtin_ia32_ vpermilps256"	return Intrinsic::x86_fma4_vfnmadd_ps_256; // "__builtin_ia32_ vfnmaddps256"
	}	}
	break;	break;

	case 'v': // 2 strings to match.	case 's': // 2 strings to match.
	if (BuiltinName.substr(23, 3) != "arp")	if (BuiltinName.substr(20, 3) != "ubp")
	break;	break;

	switch (BuiltinName[26]) {	switch (BuiltinName[23]) {
	default: break;	default: break;
	case 'd': // 1 string to match.	case 'd': // 1 string to match.

	return Intrinsic::x86_avx_vpermilvar_pd; // "__builtin_ia32_	if (BuiltinName.substr(24, 3) != "256")
	vpermilvarpd"	break;
		return Intrinsic::x86_fma4_vfnmsub_pd_256; // "__builtin_ia32_
		vfnmsubpd256"
	case 's': // 1 string to match.	case 's': // 1 string to match.

	return Intrinsic::x86_avx_vpermilvar_ps; // "__builtin_ia32_	if (BuiltinName.substr(24, 3) != "256")
	vpermilvarps"	break;
		return Intrinsic::x86_fma4_vfnmsub_ps_256; // "__builtin_ia32_
		vfnmsubps256"
	}	}
	break;	break;
	}	}
	break;	break;

		case 'p': // 2 strings to match.
		if (BuiltinName.substr(17, 9) != "ermilvarp")
		break;
		switch (BuiltinName[26]) {
		default: break;
		case 'd': // 1 string to match.
		return Intrinsic::x86_avx_vpermilvar_pd; // "__builtin_ia32_
		vpermilvarpd"
		case 's': // 1 string to match.
		return Intrinsic::x86_avx_vpermilvar_ps; // "__builtin_ia32_
		vpermilvarps"
		}
		break;
	}	}
	break;	break;
	}	}
	break;	break;

	case 28: // 17 strings to match.	case 28: // 20 strings to match.
	if (BuiltinName.substr(0, 15) != "__builtin_ia32_")	if (BuiltinName.substr(0, 15) != "__builtin_ia32_")
	break;	break;
	switch (BuiltinName[15]) {	switch (BuiltinName[15]) {
	default: break;	default: break;
	case 'a': // 2 strings to match.	case 'a': // 2 strings to match.
	if (BuiltinName.substr(16, 2) != "es")	if (BuiltinName.substr(16, 2) != "es")
	break;	break;
	switch (BuiltinName[18]) {	switch (BuiltinName[18]) {
	default: break;	default: break;
	case 'd': // 1 string to match.	case 'd': // 1 string to match.
	if (BuiltinName.substr(19, 9) != "eclast128")	if (BuiltinName.substr(19, 9) != "eclast128")
	break;	break;
	return Intrinsic::x86_aesni_aesdeclast; // "__builtin_ia32_ aesdeclast128"	return Intrinsic::x86_aesni_aesdeclast; // "__builtin_ia32_ aesdeclast128"
	case 'e': // 1 string to match.	case 'e': // 1 string to match.
	if (BuiltinName.substr(19, 9) != "nclast128")	if (BuiltinName.substr(19, 9) != "nclast128")
	break;	break;
	return Intrinsic::x86_aesni_aesenclast; // "__builtin_ia32_ aesenclast128"	return Intrinsic::x86_aesni_aesenclast; // "__builtin_ia32_ aesenclast128"
	}	}
	break;	break;

	case 'm': // 2 strings to match.	case 'i': // 1 string to match.
	if (BuiltinName.substr(16, 8) != "askloadp")	if (BuiltinName.substr(16, 12) != "nsert128i256")
	break;	break;

	switch (BuiltinName[24]) {	return Intrinsic::x86_avx2_vinserti128; // "__builtin_ia32_insert12
		8i256"
		case 'm': // 4 strings to match.
		if (BuiltinName.substr(16, 3) != "ask")
		break;
		switch (BuiltinName[19]) {
	default: break;	default: break;

	case 'd': // 1 string to match.	case 'l': // 2 strings to match.
	if (BuiltinName.substr(25, 3) != "256")	if (BuiltinName.substr(20, 4) != "oadp")
	break;	break;

	return Intrinsic::x86_avx_maskload_pd_256; // "__builtin_ia32_	switch (BuiltinName[24]) {
	maskloadpd256"	default: break;
	case 's': // 1 string to match.	case 'd': // 1 string to match.
	if (BuiltinName.substr(25, 3) != "256")	if (BuiltinName.substr(25, 3) != "256")
		break;
		return Intrinsic::x86_avx_maskload_pd_256; // "__builtin_ia32_
		maskloadpd256"
		case 's': // 1 string to match.
		if (BuiltinName.substr(25, 3) != "256")
		break;
		return Intrinsic::x86_avx_maskload_ps_256; // "__builtin_ia32_
		maskloadps256"
		}
		break;
		case 's': // 2 strings to match.
		if (BuiltinName.substr(20, 4) != "tore")
	break;	break;

	return Intrinsic::x86_avx_maskload_ps_256; // "__builtin_ia32_	switch (BuiltinName[24]) {
	maskloadps256"	default: break;
		case 'd': // 1 string to match.
		if (BuiltinName.substr(25, 3) != "256")
		break;
		return Intrinsic::x86_avx2_maskstore_d_256; // "__builtin_ia32_
		maskstored256"
		case 'q': // 1 string to match.
		if (BuiltinName.substr(25, 3) != "256")
		break;
		return Intrinsic::x86_avx2_maskstore_q_256; // "__builtin_ia32_
		maskstoreq256"
		}
		break;
	}	}
	break;	break;
	case 'p': // 11 strings to match.	case 'p': // 11 strings to match.
	switch (BuiltinName[16]) {	switch (BuiltinName[16]) {
	default: break;	default: break;
	case 'c': // 10 strings to match.	case 'c': // 10 strings to match.
	if (BuiltinName.substr(17, 2) != "mp")	if (BuiltinName.substr(17, 2) != "mp")
	break;	break;
	switch (BuiltinName[19]) {	switch (BuiltinName[19]) {
	default: break;	default: break;

	skipping to change at line 20626	skipping to change at line 38835
	break;	break;
	return Intrinsic::x86_avx_vtestnzc_pd_256; // "__builtin_ia32_ vtestnzcpd256"	return Intrinsic::x86_avx_vtestnzc_pd_256; // "__builtin_ia32_ vtestnzcpd256"
	case 's': // 1 string to match.	case 's': // 1 string to match.
	if (BuiltinName.substr(25, 3) != "256")	if (BuiltinName.substr(25, 3) != "256")
	break;	break;
	return Intrinsic::x86_avx_vtestnzc_ps_256; // "__builtin_ia32_ vtestnzcps256"	return Intrinsic::x86_avx_vtestnzc_ps_256; // "__builtin_ia32_ vtestnzcps256"
	}	}
	break;	break;
	}	}
	break;	break;

	case 29: // 2 strings to match.	case 29: // 15 strings to match.
	if (BuiltinName.substr(0, 25) != "__builtin_ia32_maskstorep")	if (BuiltinName.substr(0, 15) != "__builtin_ia32_")
	break;	break;

	switch (BuiltinName[25]) {	switch (BuiltinName[15]) {
	default: break;	default: break;

	case 'd': // 1 string to match.	case 'e': // 1 string to match.
	if (BuiltinName.substr(26, 3) != "256")	if (BuiltinName.substr(16, 13) != "xtract128i256")
	break;	break;

	return Intrinsic::x86_avx_maskstore_pd_256; // "__builtin_ia32_	return Intrinsic::x86_avx2_vextracti128; // "__builtin_ia32_extract1
	maskstorepd256"	28i256"
	case 's': // 1 string to match.	case 'm': // 2 strings to match.
	if (BuiltinName.substr(26, 3) != "256")	if (BuiltinName.substr(16, 9) != "askstorep")
		break;
		switch (BuiltinName[25]) {
		default: break;
		case 'd': // 1 string to match.
		if (BuiltinName.substr(26, 3) != "256")
		break;
		return Intrinsic::x86_avx_maskstore_pd_256; // "__builtin_ia32_
		maskstorepd256"
		case 's': // 1 string to match.
		if (BuiltinName.substr(26, 3) != "256")
		break;
		return Intrinsic::x86_avx_maskstore_ps_256; // "__builtin_ia32_
		maskstoreps256"
		}
		break;
		case 'p': // 8 strings to match.
		if (BuiltinName.substr(16, 9) != "broadcast")
		break;
		switch (BuiltinName[25]) {
		default: break;
		case 'b': // 2 strings to match.
		switch (BuiltinName[26]) {
		default: break;
		case '1': // 1 string to match.
		if (BuiltinName.substr(27, 2) != "28")
		break;
		return Intrinsic::x86_avx2_pbroadcastb_128; // "__builtin_ia32_
		pbroadcastb128"
		case '2': // 1 string to match.
		if (BuiltinName.substr(27, 2) != "56")
		break;
		return Intrinsic::x86_avx2_pbroadcastb_256; // "__builtin_ia32_
		pbroadcastb256"
		}
		break;
		case 'd': // 2 strings to match.
		switch (BuiltinName[26]) {
		default: break;
		case '1': // 1 string to match.
		if (BuiltinName.substr(27, 2) != "28")
		break;
		return Intrinsic::x86_avx2_pbroadcastd_128; // "__builtin_ia32_
		pbroadcastd128"
		case '2': // 1 string to match.
		if (BuiltinName.substr(27, 2) != "56")
		break;
		return Intrinsic::x86_avx2_pbroadcastd_256; // "__builtin_ia32_
		pbroadcastd256"
		}
		break;
		case 'q': // 2 strings to match.
		switch (BuiltinName[26]) {
		default: break;
		case '1': // 1 string to match.
		if (BuiltinName.substr(27, 2) != "28")
		break;
		return Intrinsic::x86_avx2_pbroadcastq_128; // "__builtin_ia32_
		pbroadcastq128"
		case '2': // 1 string to match.
		if (BuiltinName.substr(27, 2) != "56")
		break;
		return Intrinsic::x86_avx2_pbroadcastq_256; // "__builtin_ia32_
		pbroadcastq256"
		}
		break;
		case 'w': // 2 strings to match.
		switch (BuiltinName[26]) {
		default: break;
		case '1': // 1 string to match.
		if (BuiltinName.substr(27, 2) != "28")
		break;
		return Intrinsic::x86_avx2_pbroadcastw_128; // "__builtin_ia32_
		pbroadcastw128"
		case '2': // 1 string to match.
		if (BuiltinName.substr(27, 2) != "56")
		break;
		return Intrinsic::x86_avx2_pbroadcastw_256; // "__builtin_ia32_
		pbroadcastw256"
		}
		break;
		}
		break;
		case 'v': // 4 strings to match.
		if (BuiltinName.substr(16, 2) != "fm")
		break;
		switch (BuiltinName[18]) {
		default: break;
		case 'a': // 2 strings to match.
		if (BuiltinName.substr(19, 6) != "ddsubp")
		break;
		switch (BuiltinName[25]) {
		default: break;
		case 'd': // 1 string to match.
		if (BuiltinName.substr(26, 3) != "256")
		break;
		return Intrinsic::x86_fma4_vfmaddsub_pd_256; // "__builtin_ia32_
		vfmaddsubpd256"
		case 's': // 1 string to match.
		if (BuiltinName.substr(26, 3) != "256")
		break;
		return Intrinsic::x86_fma4_vfmaddsub_ps_256; // "__builtin_ia32_
		vfmaddsubps256"
		}
		break;
		case 's': // 2 strings to match.
		if (BuiltinName.substr(19, 6) != "ubaddp")
		break;
		switch (BuiltinName[25]) {
		default: break;
		case 'd': // 1 string to match.
		if (BuiltinName.substr(26, 3) != "256")
		break;
		return Intrinsic::x86_fma4_vfmsubadd_pd_256; // "__builtin_ia32_
		vfmsubaddpd256"
		case 's': // 1 string to match.
		if (BuiltinName.substr(26, 3) != "256")
		break;
		return Intrinsic::x86_fma4_vfmsubadd_ps_256; // "__builtin_ia32_
		vfmsubaddps256"
		}
	break;	break;

	return Intrinsic::x86_avx_maskstore_ps_256; // "__builtin_ia32_	}
	maskstoreps256"	break;
	}	}
	break;	break;

	case 30: // 4 strings to match.	case 30: // 6 strings to match.
	if (BuiltinName.substr(0, 16) != "__builtin_ia32_v")	if (BuiltinName.substr(0, 16) != "__builtin_ia32_v")
	break;	break;
	switch (BuiltinName[16]) {	switch (BuiltinName[16]) {
	default: break;	default: break;

	case 'b': // 2 strings to match.	case 'b': // 4 strings to match.
	if (BuiltinName.substr(17, 9) != "roadcasts")	if (BuiltinName.substr(17, 9) != "roadcasts")
	break;	break;
	switch (BuiltinName[26]) {	switch (BuiltinName[26]) {
	default: break;	default: break;
	case 'd': // 1 string to match.	case 'd': // 1 string to match.
	if (BuiltinName.substr(27, 3) != "256")	if (BuiltinName.substr(27, 3) != "256")
	break;	break;
	return Intrinsic::x86_avx_vbroadcast_sd_256; // "__builtin_ia32_ vbroadcastsd256"	return Intrinsic::x86_avx_vbroadcast_sd_256; // "__builtin_ia32_ vbroadcastsd256"

	case 's': // 1 string to match.	case 'i': // 1 string to match.
	if (BuiltinName.substr(27, 3) != "256")	if (BuiltinName.substr(27, 3) != "256")
	break;	break;

	return Intrinsic::x86_avx_vbroadcastss_256; // "__builtin_ia32_	return Intrinsic::x86_avx2_vbroadcasti128; // "__builtin_ia32_
	vbroadcastss256"	vbroadcastsi256"
		case 's': // 2 strings to match.
		switch (BuiltinName[27]) {
		default: break;
		case '2': // 1 string to match.
		if (BuiltinName.substr(28, 2) != "56")
		break;
		return Intrinsic::x86_avx_vbroadcast_ss_256; // "__builtin_ia32_
		vbroadcastss256"
		case '_': // 1 string to match.
		if (BuiltinName.substr(28, 2) != "ps")
		break;
		return Intrinsic::x86_avx2_vbroadcast_ss_ps; // "__builtin_ia32_
		vbroadcastss_ps"
		}
		break;
	}	}
	break;	break;
	case 'p': // 2 strings to match.	case 'p': // 2 strings to match.
	if (BuiltinName.substr(17, 9) != "ermilvarp")	if (BuiltinName.substr(17, 9) != "ermilvarp")
	break;	break;
	switch (BuiltinName[26]) {	switch (BuiltinName[26]) {
	default: break;	default: break;
	case 'd': // 1 string to match.	case 'd': // 1 string to match.
	if (BuiltinName.substr(27, 3) != "256")	if (BuiltinName.substr(27, 3) != "256")
	break;	break;

	skipping to change at line 20726	skipping to change at line 39055
	break;	break;
	return Intrinsic::x86_avx_vinsertf128_ps_256; // "__builtin_ia32_ vinsertf128_ps256"	return Intrinsic::x86_avx_vinsertf128_ps_256; // "__builtin_ia32_ vinsertf128_ps256"
	}	}
	break;	break;
	case 's': // 1 string to match.	case 's': // 1 string to match.
	if (BuiltinName.substr(28, 4) != "i256")	if (BuiltinName.substr(28, 4) != "i256")
	break;	break;
	return Intrinsic::x86_avx_vinsertf128_si_256; // "__builtin_ia32_ vinsertf128_si256"	return Intrinsic::x86_avx_vinsertf128_si_256; // "__builtin_ia32_ vinsertf128_si256"
	}	}
	break;	break;

	case 33: // 4 strings to match.	case 33: // 6 strings to match.
	if (BuiltinName.substr(0, 15) != "__builtin_ia32_")	if (BuiltinName.substr(0, 15) != "__builtin_ia32_")
	break;	break;
	switch (BuiltinName[15]) {	switch (BuiltinName[15]) {
	default: break;	default: break;
	case 'a': // 1 string to match.	case 'a': // 1 string to match.
	if (BuiltinName.substr(16, 17) != "eskeygenassist128")	if (BuiltinName.substr(16, 17) != "eskeygenassist128")
	break;	break;
	return Intrinsic::x86_aesni_aeskeygenassist; // "__builtin_ia32_ aeskeygenassist128"	return Intrinsic::x86_aesni_aeskeygenassist; // "__builtin_ia32_ aeskeygenassist128"

	case 'v': // 3 strings to match.	case 'v': // 5 strings to match.
	if (BuiltinName.substr(16, 12) != "extractf128_")	switch (BuiltinName[16]) {
	break;
	switch (BuiltinName[28]) {
	default: break;	default: break;

	case 'p': // 2 strings to match.	case 'b': // 2 strings to match.
	switch (BuiltinName[29]) {	if (BuiltinName.substr(17, 9) != "roadcasts")
		break;
		switch (BuiltinName[26]) {
	default: break;	default: break;
	case 'd': // 1 string to match.	case 'd': // 1 string to match.

	if (BuiltinName.substr(30, 3) != "256")	if (BuiltinName.substr(27, 6) != "_pd256")
	break;	break;

	return Intrinsic::x86_avx_vextractf128_pd_256; // "__built in_ia32_vextractf128_pd256"	return Intrinsic::x86_avx2_vbroadcast_sd_pd_256; // "__built in_ia32_vbroadcastsd_pd256"
	case 's': // 1 string to match.	case 's': // 1 string to match.

	if (BuiltinName.substr(30, 3) != "256")	if (BuiltinName.substr(27, 6) != "_ps256")
	break;	break;

	return Intrinsic::x86_avx_vextractf128_ps_256; // "__built in_ia32_vextractf128_ps256"	return Intrinsic::x86_avx2_vbroadcast_ss_ps_256; // "__built in_ia32_vbroadcastss_ps256"
	}	}
	break;	break;

	case 's': // 1 string to match.	case 'e': // 3 strings to match.
	if (BuiltinName.substr(29, 4) != "i256")	if (BuiltinName.substr(17, 11) != "xtractf128_")
		break;
		switch (BuiltinName[28]) {
		default: break;
		case 'p': // 2 strings to match.
		switch (BuiltinName[29]) {
		default: break;
		case 'd': // 1 string to match.
		if (BuiltinName.substr(30, 3) != "256")
		break;
		return Intrinsic::x86_avx_vextractf128_pd_256; // "__built
		in_ia32_vextractf128_pd256"
		case 's': // 1 string to match.
		if (BuiltinName.substr(30, 3) != "256")
		break;
		return Intrinsic::x86_avx_vextractf128_ps_256; // "__built
		in_ia32_vextractf128_ps256"
		}
	break;	break;

	return Intrinsic::x86_avx_vextractf128_si_256; // "__builtin_ia32_	case 's': // 1 string to match.
	vextractf128_si256"	if (BuiltinName.substr(29, 4) != "i256")
		break;
		return Intrinsic::x86_avx_vextractf128_si_256; // "__built
		in_ia32_vextractf128_si256"
		}
		break;
	}	}
	break;	break;
	}	}
	break;	break;

	case 35: // 4 strings to match.	case 35: // 6 strings to match.
	if (BuiltinName.substr(0, 15) != "__builtin_ia32_")	if (BuiltinName.substr(0, 15) != "__builtin_ia32_")
	break;	break;
	switch (BuiltinName[15]) {	switch (BuiltinName[15]) {
	default: break;	default: break;

	case 'p': // 2 strings to match.	case 'p': // 4 strings to match.
	if (BuiltinName[16] != 's')	if (BuiltinName[16] != 's')
	break;	break;
	switch (BuiltinName[17]) {	switch (BuiltinName[17]) {
	default: break;	default: break;

	case 'l': // 1 string to match.	case 'l': // 2 strings to match.
	if (BuiltinName.substr(18, 17) != "ldqi128_byteshift")	if (BuiltinName.substr(18, 4) != "ldqi")
	break;	break;

	return Intrinsic::x86_sse2_psll_dq_bs; // "__builtin_ia32_pslldqi1	switch (BuiltinName[22]) {
	28_byteshift"	default: break;
	case 'r': // 1 string to match.	case '1': // 1 string to match.
	if (BuiltinName.substr(18, 17) != "ldqi128_byteshift")	if (BuiltinName.substr(23, 12) != "28_byteshift")
		break;
		return Intrinsic::x86_sse2_psll_dq_bs; // "__builtin_ia32_
		pslldqi128_byteshift"
		case '2': // 1 string to match.
		if (BuiltinName.substr(23, 12) != "56_byteshift")
		break;
		return Intrinsic::x86_avx2_psll_dq_bs; // "__builtin_ia32_
		pslldqi256_byteshift"
		}
		break;
		case 'r': // 2 strings to match.
		if (BuiltinName.substr(18, 4) != "ldqi")
	break;	break;

	return Intrinsic::x86_sse2_psrl_dq_bs; // "__builtin_ia32_psrldqi1	switch (BuiltinName[22]) {
	28_byteshift"	default: break;
		case '1': // 1 string to match.
		if (BuiltinName.substr(23, 12) != "28_byteshift")
		break;
		return Intrinsic::x86_sse2_psrl_dq_bs; // "__builtin_ia32_
		psrldqi128_byteshift"
		case '2': // 1 string to match.
		if (BuiltinName.substr(23, 12) != "56_byteshift")
		break;
		return Intrinsic::x86_avx2_psrl_dq_bs; // "__builtin_ia32_
		psrldqi256_byteshift"
		}
		break;
	}	}
	break;	break;
	case 'v': // 2 strings to match.	case 'v': // 2 strings to match.
	if (BuiltinName.substr(16, 15) != "broadcastf128_p")	if (BuiltinName.substr(16, 15) != "broadcastf128_p")
	break;	break;
	switch (BuiltinName[31]) {	switch (BuiltinName[31]) {
	default: break;	default: break;
	case 'd': // 1 string to match.	case 'd': // 1 string to match.
	if (BuiltinName.substr(32, 3) != "256")	if (BuiltinName.substr(32, 3) != "256")
	break;	break;

End of changes. 1373 change blocks.
	11078 lines changed or deleted	31712 lines changed or added

	IntrinsicsX86.td	IntrinsicsX86.td

	skipping to change at line 148	skipping to change at line 148
	def int_x86_sse_max_ss : GCCBuiltin<"__builtin_ia32_maxss">,	def int_x86_sse_max_ss : GCCBuiltin<"__builtin_ia32_maxss">,
	Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty,	Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty,
	llvm_v4f32_ty], [IntrNoMem]>;	llvm_v4f32_ty], [IntrNoMem]>;
	def int_x86_sse_max_ps : GCCBuiltin<"__builtin_ia32_maxps">,	def int_x86_sse_max_ps : GCCBuiltin<"__builtin_ia32_maxps">,
	Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty,	Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty,
	llvm_v4f32_ty], [IntrNoMem]>;	llvm_v4f32_ty], [IntrNoMem]>;
	}	}

	// Comparison ops	// Comparison ops
	let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".	let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".

	def int_x86_sse_cmp_ss :	def int_x86_sse_cmp_ss : GCCBuiltin<"__builtin_ia32_cmpss">,
	Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty,	Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty,
	llvm_v4f32_ty, llvm_i8_ty], [IntrNoMem]>;	llvm_v4f32_ty, llvm_i8_ty], [IntrNoMem]>;

	def int_x86_sse_cmp_ps :	def int_x86_sse_cmp_ps : GCCBuiltin<"__builtin_ia32_cmpps">,
	Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty,	Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty,
	llvm_v4f32_ty, llvm_i8_ty], [IntrNoMem]>;	llvm_v4f32_ty, llvm_i8_ty], [IntrNoMem]>;
	def int_x86_sse_comieq_ss : GCCBuiltin<"__builtin_ia32_comieq">,	def int_x86_sse_comieq_ss : GCCBuiltin<"__builtin_ia32_comieq">,
	Intrinsic<[llvm_i32_ty], [llvm_v4f32_ty,	Intrinsic<[llvm_i32_ty], [llvm_v4f32_ty,
	llvm_v4f32_ty], [IntrNoMem]>;	llvm_v4f32_ty], [IntrNoMem]>;
	def int_x86_sse_comilt_ss : GCCBuiltin<"__builtin_ia32_comilt">,	def int_x86_sse_comilt_ss : GCCBuiltin<"__builtin_ia32_comilt">,
	Intrinsic<[llvm_i32_ty], [llvm_v4f32_ty,	Intrinsic<[llvm_i32_ty], [llvm_v4f32_ty,
	llvm_v4f32_ty], [IntrNoMem]>;	llvm_v4f32_ty], [IntrNoMem]>;
	def int_x86_sse_comile_ss : GCCBuiltin<"__builtin_ia32_comile">,	def int_x86_sse_comile_ss : GCCBuiltin<"__builtin_ia32_comile">,
	Intrinsic<[llvm_i32_ty], [llvm_v4f32_ty,	Intrinsic<[llvm_i32_ty], [llvm_v4f32_ty,

	skipping to change at line 283	skipping to change at line 283
	def int_x86_sse2_max_sd : GCCBuiltin<"__builtin_ia32_maxsd">,	def int_x86_sse2_max_sd : GCCBuiltin<"__builtin_ia32_maxsd">,
	Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty,	Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty,
	llvm_v2f64_ty], [IntrNoMem]>;	llvm_v2f64_ty], [IntrNoMem]>;
	def int_x86_sse2_max_pd : GCCBuiltin<"__builtin_ia32_maxpd">,	def int_x86_sse2_max_pd : GCCBuiltin<"__builtin_ia32_maxpd">,
	Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty,	Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty,
	llvm_v2f64_ty], [IntrNoMem]>;	llvm_v2f64_ty], [IntrNoMem]>;
	}	}

	// FP comparison ops	// FP comparison ops
	let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".	let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".

	def int_x86_sse2_cmp_sd :	def int_x86_sse2_cmp_sd : GCCBuiltin<"__builtin_ia32_cmpsd">,
	Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty,	Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty,
	llvm_v2f64_ty, llvm_i8_ty], [IntrNoMem]>;	llvm_v2f64_ty, llvm_i8_ty], [IntrNoMem]>;

	def int_x86_sse2_cmp_pd :	def int_x86_sse2_cmp_pd : GCCBuiltin<"__builtin_ia32_cmppd">,
	Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty,	Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty,
	llvm_v2f64_ty, llvm_i8_ty], [IntrNoMem]>;	llvm_v2f64_ty, llvm_i8_ty], [IntrNoMem]>;
	def int_x86_sse2_comieq_sd : GCCBuiltin<"__builtin_ia32_comisdeq">,	def int_x86_sse2_comieq_sd : GCCBuiltin<"__builtin_ia32_comisdeq">,
	Intrinsic<[llvm_i32_ty], [llvm_v2f64_ty,	Intrinsic<[llvm_i32_ty], [llvm_v2f64_ty,
	llvm_v2f64_ty], [IntrNoMem]>;	llvm_v2f64_ty], [IntrNoMem]>;
	def int_x86_sse2_comilt_sd : GCCBuiltin<"__builtin_ia32_comisdlt">,	def int_x86_sse2_comilt_sd : GCCBuiltin<"__builtin_ia32_comisdlt">,
	Intrinsic<[llvm_i32_ty], [llvm_v2f64_ty,	Intrinsic<[llvm_i32_ty], [llvm_v2f64_ty,
	llvm_v2f64_ty], [IntrNoMem]>;	llvm_v2f64_ty], [IntrNoMem]>;
	def int_x86_sse2_comile_sd : GCCBuiltin<"__builtin_ia32_comisdle">,	def int_x86_sse2_comile_sd : GCCBuiltin<"__builtin_ia32_comisdle">,
	Intrinsic<[llvm_i32_ty], [llvm_v2f64_ty,	Intrinsic<[llvm_i32_ty], [llvm_v2f64_ty,

	skipping to change at line 454	skipping to change at line 454
	Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty,	Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty,
	llvm_i32_ty], [IntrNoMem]>;	llvm_i32_ty], [IntrNoMem]>;
	def int_x86_sse2_psll_dq_bs : GCCBuiltin<"__builtin_ia32_pslldqi128_bytes hift">,	def int_x86_sse2_psll_dq_bs : GCCBuiltin<"__builtin_ia32_pslldqi128_bytes hift">,
	Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty,	Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty,
	llvm_i32_ty], [IntrNoMem]>;	llvm_i32_ty], [IntrNoMem]>;
	def int_x86_sse2_psrl_dq_bs : GCCBuiltin<"__builtin_ia32_psrldqi128_bytes hift">,	def int_x86_sse2_psrl_dq_bs : GCCBuiltin<"__builtin_ia32_psrldqi128_bytes hift">,
	Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty,	Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty,
	llvm_i32_ty], [IntrNoMem]>;	llvm_i32_ty], [IntrNoMem]>;
	}	}


	// Integer comparison ops
	let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
	def int_x86_sse2_pcmpeq_b : GCCBuiltin<"__builtin_ia32_pcmpeqb128">,
	Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty,
	llvm_v16i8_ty], [IntrNoMem]>;
	def int_x86_sse2_pcmpeq_w : GCCBuiltin<"__builtin_ia32_pcmpeqw128">,
	Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty,
	llvm_v8i16_ty], [IntrNoMem]>;
	def int_x86_sse2_pcmpeq_d : GCCBuiltin<"__builtin_ia32_pcmpeqd128">,
	Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty,
	llvm_v4i32_ty], [IntrNoMem]>;
	def int_x86_sse2_pcmpgt_b : GCCBuiltin<"__builtin_ia32_pcmpgtb128">,
	Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty,
	llvm_v16i8_ty], [IntrNoMem]>;
	def int_x86_sse2_pcmpgt_w : GCCBuiltin<"__builtin_ia32_pcmpgtw128">,
	Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty,
	llvm_v8i16_ty], [IntrNoMem]>;
	def int_x86_sse2_pcmpgt_d : GCCBuiltin<"__builtin_ia32_pcmpgtd128">,
	Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty,
	llvm_v4i32_ty], [IntrNoMem]>;
	}

	// Conversion ops	// Conversion ops
	let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".	let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
	def int_x86_sse2_cvtdq2pd : GCCBuiltin<"__builtin_ia32_cvtdq2pd">,	def int_x86_sse2_cvtdq2pd : GCCBuiltin<"__builtin_ia32_cvtdq2pd">,
	Intrinsic<[llvm_v2f64_ty], [llvm_v4i32_ty], [IntrNoMem]>;	Intrinsic<[llvm_v2f64_ty], [llvm_v4i32_ty], [IntrNoMem]>;
	def int_x86_sse2_cvtdq2ps : GCCBuiltin<"__builtin_ia32_cvtdq2ps">,	def int_x86_sse2_cvtdq2ps : GCCBuiltin<"__builtin_ia32_cvtdq2ps">,
	Intrinsic<[llvm_v4f32_ty], [llvm_v4i32_ty], [IntrNoMem]>;	Intrinsic<[llvm_v4f32_ty], [llvm_v4i32_ty], [IntrNoMem]>;
	def int_x86_sse2_cvtpd2dq : GCCBuiltin<"__builtin_ia32_cvtpd2dq">,	def int_x86_sse2_cvtpd2dq : GCCBuiltin<"__builtin_ia32_cvtpd2dq">,
	Intrinsic<[llvm_v4i32_ty], [llvm_v2f64_ty], [IntrNoMem]>;	Intrinsic<[llvm_v4i32_ty], [llvm_v2f64_ty], [IntrNoMem]>;
	def int_x86_sse2_cvttpd2dq : GCCBuiltin<"__builtin_ia32_cvttpd2dq">,	def int_x86_sse2_cvttpd2dq : GCCBuiltin<"__builtin_ia32_cvttpd2dq">,
	Intrinsic<[llvm_v4i32_ty], [llvm_v2f64_ty], [IntrNoMem]>;	Intrinsic<[llvm_v4i32_ty], [llvm_v2f64_ty], [IntrNoMem]>;

	skipping to change at line 629	skipping to change at line 607
	Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,	Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,
	llvm_x86mmx_ty], [IntrNoMem]>;	llvm_x86mmx_ty], [IntrNoMem]>;
	def int_x86_ssse3_phadd_d_128 : GCCBuiltin<"__builtin_ia32_phaddd128" >,	def int_x86_ssse3_phadd_d_128 : GCCBuiltin<"__builtin_ia32_phaddd128" >,
	Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty,	Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty,
	llvm_v4i32_ty], [IntrNoMem]>;	llvm_v4i32_ty], [IntrNoMem]>;

	def int_x86_ssse3_phadd_sw : GCCBuiltin<"__builtin_ia32_phaddsw">,	def int_x86_ssse3_phadd_sw : GCCBuiltin<"__builtin_ia32_phaddsw">,
	Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,	Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,
	llvm_x86mmx_ty], [IntrNoMem]>;	llvm_x86mmx_ty], [IntrNoMem]>;
	def int_x86_ssse3_phadd_sw_128 : GCCBuiltin<"__builtin_ia32_phaddsw128 ">,	def int_x86_ssse3_phadd_sw_128 : GCCBuiltin<"__builtin_ia32_phaddsw128 ">,

	Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty,	Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty,
	llvm_v4i32_ty], [IntrNoMem]>;	llvm_v8i16_ty], [IntrNoMem]>;

	def int_x86_ssse3_phsub_w : GCCBuiltin<"__builtin_ia32_phsubw">,	def int_x86_ssse3_phsub_w : GCCBuiltin<"__builtin_ia32_phsubw">,
	Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,	Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,
	llvm_x86mmx_ty], [IntrNoMem]>;	llvm_x86mmx_ty], [IntrNoMem]>;
	def int_x86_ssse3_phsub_w_128 : GCCBuiltin<"__builtin_ia32_phsubw128" >,	def int_x86_ssse3_phsub_w_128 : GCCBuiltin<"__builtin_ia32_phsubw128" >,
	Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty,	Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty,
	llvm_v8i16_ty], [IntrNoMem]>;	llvm_v8i16_ty], [IntrNoMem]>;

	def int_x86_ssse3_phsub_d : GCCBuiltin<"__builtin_ia32_phsubd">,	def int_x86_ssse3_phsub_d : GCCBuiltin<"__builtin_ia32_phsubd">,
	Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,	Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,

	skipping to change at line 657	skipping to change at line 635
	Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,	Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,
	llvm_x86mmx_ty], [IntrNoMem]>;	llvm_x86mmx_ty], [IntrNoMem]>;
	def int_x86_ssse3_phsub_sw_128 : GCCBuiltin<"__builtin_ia32_phsubsw128 ">,	def int_x86_ssse3_phsub_sw_128 : GCCBuiltin<"__builtin_ia32_phsubsw128 ">,
	Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty,	Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty,
	llvm_v8i16_ty], [IntrNoMem]>;	llvm_v8i16_ty], [IntrNoMem]>;

	def int_x86_ssse3_pmadd_ub_sw : GCCBuiltin<"__builtin_ia32_pmaddubsw" >,	def int_x86_ssse3_pmadd_ub_sw : GCCBuiltin<"__builtin_ia32_pmaddubsw" >,
	Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,	Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,
	llvm_x86mmx_ty], [IntrNoMem]>;	llvm_x86mmx_ty], [IntrNoMem]>;
	def int_x86_ssse3_pmadd_ub_sw_128 : GCCBuiltin<"__builtin_ia32_pmaddubsw1 28">,	def int_x86_ssse3_pmadd_ub_sw_128 : GCCBuiltin<"__builtin_ia32_pmaddubsw1 28">,

	Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty,	Intrinsic<[llvm_v8i16_ty], [llvm_v16i8_ty,
	llvm_v8i16_ty], [IntrNoMem]>;	llvm_v16i8_ty], [IntrNoMem]>;
	}	}

	// Packed multiply high with round and scale	// Packed multiply high with round and scale
	let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".	let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
	def int_x86_ssse3_pmul_hr_sw : GCCBuiltin<"__builtin_ia32_pmulhrsw"> ,	def int_x86_ssse3_pmul_hr_sw : GCCBuiltin<"__builtin_ia32_pmulhrsw"> ,
	Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,	Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,
	llvm_x86mmx_ty], [IntrNoMem, Commutative]>;	llvm_x86mmx_ty], [IntrNoMem, Commutative]>;
	def int_x86_ssse3_pmul_hr_sw_128 : GCCBuiltin<"__builtin_ia32_pmulhrsw12 8">,	def int_x86_ssse3_pmul_hr_sw_128 : GCCBuiltin<"__builtin_ia32_pmulhrsw12 8">,
	Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty,	Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty,
	llvm_v8i16_ty], [IntrNoMem, Commutative]>;	llvm_v8i16_ty], [IntrNoMem, Commutative]>;

	skipping to change at line 794	skipping to change at line 772

	// Vector min element	// Vector min element
	let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".	let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
	def int_x86_sse41_phminposuw : GCCBuiltin<"__builtin_ia32_phminposuw1 28">,	def int_x86_sse41_phminposuw : GCCBuiltin<"__builtin_ia32_phminposuw1 28">,
	Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty],	Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty],
	[IntrNoMem]>;	[IntrNoMem]>;
	}	}

	// Vector compare, min, max	// Vector compare, min, max
	let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".	let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".

	def int_x86_sse41_pcmpeqq : GCCBuiltin<"__builtin_ia32_pcmpeqq">,
	Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
	[IntrNoMem, Commutative]>;
	def int_x86_sse42_pcmpgtq : GCCBuiltin<"__builtin_ia32_pcmpgtq">,
	Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
	[IntrNoMem]>;
	def int_x86_sse41_pmaxsb : GCCBuiltin<"__builtin_ia32_pmaxsb128" >,	def int_x86_sse41_pmaxsb : GCCBuiltin<"__builtin_ia32_pmaxsb128" >,
	Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty],	Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty],
	[IntrNoMem, Commutative]>;	[IntrNoMem, Commutative]>;
	def int_x86_sse41_pmaxsd : GCCBuiltin<"__builtin_ia32_pmaxsd128" >,	def int_x86_sse41_pmaxsd : GCCBuiltin<"__builtin_ia32_pmaxsd128" >,
	Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty],	Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
	[IntrNoMem, Commutative]>;	[IntrNoMem, Commutative]>;
	def int_x86_sse41_pmaxud : GCCBuiltin<"__builtin_ia32_pmaxud128" >,	def int_x86_sse41_pmaxud : GCCBuiltin<"__builtin_ia32_pmaxud128" >,
	Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty],	Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
	[IntrNoMem, Commutative]>;	[IntrNoMem, Commutative]>;
	def int_x86_sse41_pmaxuw : GCCBuiltin<"__builtin_ia32_pmaxuw128" >,	def int_x86_sse41_pmaxuw : GCCBuiltin<"__builtin_ia32_pmaxuw128" >,

	skipping to change at line 921	skipping to change at line 893
	Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty,llvm_i32 _ty],	Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty,llvm_i32 _ty],
	[IntrNoMem, Commutative]>;	[IntrNoMem, Commutative]>;
	def int_x86_sse41_dpps : GCCBuiltin<"__builtin_ia32_dpps">,	def int_x86_sse41_dpps : GCCBuiltin<"__builtin_ia32_dpps">,
	Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty,llvm_i32 _ty],	Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty,llvm_i32 _ty],
	[IntrNoMem, Commutative]>;	[IntrNoMem, Commutative]>;
	}	}

	// Vector sum of absolute differences	// Vector sum of absolute differences
	let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".	let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
	def int_x86_sse41_mpsadbw : GCCBuiltin<"__builtin_ia32_mpsadbw128 ">,	def int_x86_sse41_mpsadbw : GCCBuiltin<"__builtin_ia32_mpsadbw128 ">,

	Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty,llvm_i32 _ty],	Intrinsic<[llvm_v8i16_ty], [llvm_v16i8_ty, llvm_v16i8_ty,llvm_i32 _ty],
	[IntrNoMem, Commutative]>;	[IntrNoMem, Commutative]>;
	}	}

	// Cacheability support ops	// Cacheability support ops
	let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".	let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
	def int_x86_sse41_movntdqa : GCCBuiltin<"__builtin_ia32_movntdqa"> ,	def int_x86_sse41_movntdqa : GCCBuiltin<"__builtin_ia32_movntdqa"> ,
	Intrinsic<[llvm_v2i64_ty], [llvm_ptr_ty], [IntrReadMem]>;	Intrinsic<[llvm_v2i64_ty], [llvm_ptr_ty], [IntrReadMem]>;
	}	}

	// Test instruction with bitwise comparison.	// Test instruction with bitwise comparison.
	let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".	let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
	def int_x86_sse41_ptestz : GCCBuiltin<"__builtin_ia32_ptestz128" >,	def int_x86_sse41_ptestz : GCCBuiltin<"__builtin_ia32_ptestz128" >,

	Intrinsic<[llvm_i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty],	Intrinsic<[llvm_i32_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
	[IntrNoMem]>;	[IntrNoMem]>;
	def int_x86_sse41_ptestc : GCCBuiltin<"__builtin_ia32_ptestc128" >,	def int_x86_sse41_ptestc : GCCBuiltin<"__builtin_ia32_ptestc128" >,

	Intrinsic<[llvm_i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty],	Intrinsic<[llvm_i32_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
	[IntrNoMem]>;	[IntrNoMem]>;
	def int_x86_sse41_ptestnzc : GCCBuiltin<"__builtin_ia32_ptestnzc12 8">,	def int_x86_sse41_ptestnzc : GCCBuiltin<"__builtin_ia32_ptestnzc12 8">,

	Intrinsic<[llvm_i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty],	Intrinsic<[llvm_i32_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
	[IntrNoMem]>;	[IntrNoMem]>;
	}	}

	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	// SSE4.2	// SSE4.2

	// Miscellaneous	// Miscellaneous
	// CRC Instruction	// CRC Instruction
	let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".	let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
	def int_x86_sse42_crc32_32_8 : GCCBuiltin<"__builtin_ia32_crc32qi"> ,	def int_x86_sse42_crc32_32_8 : GCCBuiltin<"__builtin_ia32_crc32qi"> ,

	skipping to change at line 1121	skipping to change at line 1093
	Intrinsic<[llvm_v4f64_ty], [llvm_v4f64_ty,	Intrinsic<[llvm_v4f64_ty], [llvm_v4f64_ty,
	llvm_v4f64_ty, llvm_i8_ty], [IntrNoMem]>;	llvm_v4f64_ty, llvm_i8_ty], [IntrNoMem]>;
	def int_x86_avx_vperm2f128_ps_256 :	def int_x86_avx_vperm2f128_ps_256 :
	GCCBuiltin<"__builtin_ia32_vperm2f128_ps256">,	GCCBuiltin<"__builtin_ia32_vperm2f128_ps256">,
	Intrinsic<[llvm_v8f32_ty], [llvm_v8f32_ty,	Intrinsic<[llvm_v8f32_ty], [llvm_v8f32_ty,
	llvm_v8f32_ty, llvm_i8_ty], [IntrNoMem]>;	llvm_v8f32_ty, llvm_i8_ty], [IntrNoMem]>;
	def int_x86_avx_vperm2f128_si_256 :	def int_x86_avx_vperm2f128_si_256 :
	GCCBuiltin<"__builtin_ia32_vperm2f128_si256">,	GCCBuiltin<"__builtin_ia32_vperm2f128_si256">,
	Intrinsic<[llvm_v8i32_ty], [llvm_v8i32_ty,	Intrinsic<[llvm_v8i32_ty], [llvm_v8i32_ty,
	llvm_v8i32_ty, llvm_i8_ty], [IntrNoMem]>;	llvm_v8i32_ty, llvm_i8_ty], [IntrNoMem]>;


	def int_x86_avx_vpermil_pd : GCCBuiltin<"__builtin_ia32_vpermilpd">,
	Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty,
	llvm_i8_ty], [IntrNoMem]>;
	def int_x86_avx_vpermil_ps : GCCBuiltin<"__builtin_ia32_vpermilps">,
	Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty,
	llvm_i8_ty], [IntrNoMem]>;

	def int_x86_avx_vpermil_pd_256 : GCCBuiltin<"__builtin_ia32_vpermilpd256"
	>,
	Intrinsic<[llvm_v4f64_ty], [llvm_v4f64_ty,
	llvm_i8_ty], [IntrNoMem]>;
	def int_x86_avx_vpermil_ps_256 : GCCBuiltin<"__builtin_ia32_vpermilps256"
	>,
	Intrinsic<[llvm_v8f32_ty], [llvm_v8f32_ty,
	llvm_i8_ty], [IntrNoMem]>;
	}	}

	// Vector blend	// Vector blend
	let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".	let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
	def int_x86_avx_blend_pd_256 : GCCBuiltin<"__builtin_ia32_blendpd256">,	def int_x86_avx_blend_pd_256 : GCCBuiltin<"__builtin_ia32_blendpd256">,
	Intrinsic<[llvm_v4f64_ty], [llvm_v4f64_ty,	Intrinsic<[llvm_v4f64_ty], [llvm_v4f64_ty,
	llvm_v4f64_ty, llvm_i32_ty], [IntrNoMem]>;	llvm_v4f64_ty, llvm_i32_ty], [IntrNoMem]>;
	def int_x86_avx_blend_ps_256 : GCCBuiltin<"__builtin_ia32_blendps256">,	def int_x86_avx_blend_ps_256 : GCCBuiltin<"__builtin_ia32_blendps256">,
	Intrinsic<[llvm_v8f32_ty], [llvm_v8f32_ty,	Intrinsic<[llvm_v8f32_ty], [llvm_v8f32_ty,
	llvm_v8f32_ty, llvm_i32_ty], [IntrNoMem]>;	llvm_v8f32_ty, llvm_i32_ty], [IntrNoMem]>;

	skipping to change at line 1283	skipping to change at line 1241
	// Vector zero	// Vector zero
	let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".	let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
	def int_x86_avx_vzeroall : GCCBuiltin<"__builtin_ia32_vzeroall">,	def int_x86_avx_vzeroall : GCCBuiltin<"__builtin_ia32_vzeroall">,
	Intrinsic<[], [], []>;	Intrinsic<[], [], []>;
	def int_x86_avx_vzeroupper : GCCBuiltin<"__builtin_ia32_vzeroupper">,	def int_x86_avx_vzeroupper : GCCBuiltin<"__builtin_ia32_vzeroupper">,
	Intrinsic<[], [], []>;	Intrinsic<[], [], []>;
	}	}

	// Vector load with broadcast	// Vector load with broadcast
	let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".	let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".

	def int_x86_avx_vbroadcastss :	def int_x86_avx_vbroadcast_ss :
	GCCBuiltin<"__builtin_ia32_vbroadcastss">,	GCCBuiltin<"__builtin_ia32_vbroadcastss">,
	Intrinsic<[llvm_v4f32_ty], [llvm_ptr_ty], [IntrReadMem]>;	Intrinsic<[llvm_v4f32_ty], [llvm_ptr_ty], [IntrReadMem]>;
	def int_x86_avx_vbroadcast_sd_256 :	def int_x86_avx_vbroadcast_sd_256 :
	GCCBuiltin<"__builtin_ia32_vbroadcastsd256">,	GCCBuiltin<"__builtin_ia32_vbroadcastsd256">,
	Intrinsic<[llvm_v4f64_ty], [llvm_ptr_ty], [IntrReadMem]>;	Intrinsic<[llvm_v4f64_ty], [llvm_ptr_ty], [IntrReadMem]>;

	def int_x86_avx_vbroadcastss_256 :	def int_x86_avx_vbroadcast_ss_256 :
	GCCBuiltin<"__builtin_ia32_vbroadcastss256">,	GCCBuiltin<"__builtin_ia32_vbroadcastss256">,
	Intrinsic<[llvm_v8f32_ty], [llvm_ptr_ty], [IntrReadMem]>;	Intrinsic<[llvm_v8f32_ty], [llvm_ptr_ty], [IntrReadMem]>;
	def int_x86_avx_vbroadcastf128_pd_256 :	def int_x86_avx_vbroadcastf128_pd_256 :
	GCCBuiltin<"__builtin_ia32_vbroadcastf128_pd256">,	GCCBuiltin<"__builtin_ia32_vbroadcastf128_pd256">,
	Intrinsic<[llvm_v4f64_ty], [llvm_ptr_ty], [IntrReadMem]>;	Intrinsic<[llvm_v4f64_ty], [llvm_ptr_ty], [IntrReadMem]>;
	def int_x86_avx_vbroadcastf128_ps_256 :	def int_x86_avx_vbroadcastf128_ps_256 :
	GCCBuiltin<"__builtin_ia32_vbroadcastf128_ps256">,	GCCBuiltin<"__builtin_ia32_vbroadcastf128_ps256">,
	Intrinsic<[llvm_v8f32_ty], [llvm_ptr_ty], [IntrReadMem]>;	Intrinsic<[llvm_v8f32_ty], [llvm_ptr_ty], [IntrReadMem]>;
	}	}

	// SIMD load ops	// SIMD load ops
	let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".	let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".

	def int_x86_avx_loadu_pd_256 : GCCBuiltin<"__builtin_ia32_loadupd256">,
	Intrinsic<[llvm_v4f64_ty], [llvm_ptr_ty], [IntrReadMem]>;
	def int_x86_avx_loadu_ps_256 : GCCBuiltin<"__builtin_ia32_loadups256">,
	Intrinsic<[llvm_v8f32_ty], [llvm_ptr_ty], [IntrReadMem]>;
	def int_x86_avx_loadu_dq_256 : GCCBuiltin<"__builtin_ia32_loaddqu256">,
	Intrinsic<[llvm_v32i8_ty], [llvm_ptr_ty], [IntrReadMem]>;
	def int_x86_avx_ldu_dq_256 : GCCBuiltin<"__builtin_ia32_lddqu256">,	def int_x86_avx_ldu_dq_256 : GCCBuiltin<"__builtin_ia32_lddqu256">,
	Intrinsic<[llvm_v32i8_ty], [llvm_ptr_ty], [IntrReadMem]>;	Intrinsic<[llvm_v32i8_ty], [llvm_ptr_ty], [IntrReadMem]>;
	}	}

	// SIMD store ops	// SIMD store ops
	let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".	let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
	def int_x86_avx_storeu_pd_256 : GCCBuiltin<"__builtin_ia32_storeupd256">,	def int_x86_avx_storeu_pd_256 : GCCBuiltin<"__builtin_ia32_storeupd256">,
	Intrinsic<[], [llvm_ptr_ty, llvm_v4f64_ty], []>;	Intrinsic<[], [llvm_ptr_ty, llvm_v4f64_ty], []>;
	def int_x86_avx_storeu_ps_256 : GCCBuiltin<"__builtin_ia32_storeups256">,	def int_x86_avx_storeu_ps_256 : GCCBuiltin<"__builtin_ia32_storeups256">,
	Intrinsic<[], [llvm_ptr_ty, llvm_v8f32_ty], []>;	Intrinsic<[], [llvm_ptr_ty, llvm_v8f32_ty], []>;

	skipping to change at line 1363	skipping to change at line 1315
	GCCBuiltin<"__builtin_ia32_maskstorepd256">,	GCCBuiltin<"__builtin_ia32_maskstorepd256">,
	Intrinsic<[], [llvm_ptr_ty,	Intrinsic<[], [llvm_ptr_ty,
	llvm_v4f64_ty, llvm_v4f64_ty], []>;	llvm_v4f64_ty, llvm_v4f64_ty], []>;
	def int_x86_avx_maskstore_ps_256 :	def int_x86_avx_maskstore_ps_256 :
	GCCBuiltin<"__builtin_ia32_maskstoreps256">,	GCCBuiltin<"__builtin_ia32_maskstoreps256">,
	Intrinsic<[], [llvm_ptr_ty,	Intrinsic<[], [llvm_ptr_ty,
	llvm_v8f32_ty, llvm_v8f32_ty], []>;	llvm_v8f32_ty, llvm_v8f32_ty], []>;
	}	}

	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

		// AVX2

		// Integer arithmetic ops.
		let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
		def int_x86_avx2_padds_b : GCCBuiltin<"__builtin_ia32_paddsb256">,
		Intrinsic<[llvm_v32i8_ty], [llvm_v32i8_ty,
		llvm_v32i8_ty], [IntrNoMem, Commutative]>;
		def int_x86_avx2_padds_w : GCCBuiltin<"__builtin_ia32_paddsw256">,
		Intrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty,
		llvm_v16i16_ty], [IntrNoMem, Commutative]>;
		def int_x86_avx2_paddus_b : GCCBuiltin<"__builtin_ia32_paddusb256">,
		Intrinsic<[llvm_v32i8_ty], [llvm_v32i8_ty,
		llvm_v32i8_ty], [IntrNoMem, Commutative]>;
		def int_x86_avx2_paddus_w : GCCBuiltin<"__builtin_ia32_paddusw256">,
		Intrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty,
		llvm_v16i16_ty], [IntrNoMem, Commutative]>;
		def int_x86_avx2_psubs_b : GCCBuiltin<"__builtin_ia32_psubsb256">,
		Intrinsic<[llvm_v32i8_ty], [llvm_v32i8_ty,
		llvm_v32i8_ty], [IntrNoMem]>;
		def int_x86_avx2_psubs_w : GCCBuiltin<"__builtin_ia32_psubsw256">,
		Intrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty,
		llvm_v16i16_ty], [IntrNoMem]>;
		def int_x86_avx2_psubus_b : GCCBuiltin<"__builtin_ia32_psubusb256">,
		Intrinsic<[llvm_v32i8_ty], [llvm_v32i8_ty,
		llvm_v32i8_ty], [IntrNoMem]>;
		def int_x86_avx2_psubus_w : GCCBuiltin<"__builtin_ia32_psubusw256">,
		Intrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty,
		llvm_v16i16_ty], [IntrNoMem]>;
		def int_x86_avx2_pmulhu_w : GCCBuiltin<"__builtin_ia32_pmulhuw256">,
		Intrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty,
		llvm_v16i16_ty], [IntrNoMem, Commutative]>;
		def int_x86_avx2_pmulh_w : GCCBuiltin<"__builtin_ia32_pmulhw256">,
		Intrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty,
		llvm_v16i16_ty], [IntrNoMem, Commutative]>;
		def int_x86_avx2_pmulu_dq : GCCBuiltin<"__builtin_ia32_pmuludq256">,
		Intrinsic<[llvm_v4i64_ty], [llvm_v8i32_ty,
		llvm_v8i32_ty], [IntrNoMem, Commutative]>;
		def int_x86_avx2_pmul_dq : GCCBuiltin<"__builtin_ia32_pmuldq256">,
		Intrinsic<[llvm_v4i64_ty], [llvm_v8i32_ty,
		llvm_v8i32_ty], [IntrNoMem, Commutative]>;
		def int_x86_avx2_pmadd_wd : GCCBuiltin<"__builtin_ia32_pmaddwd256">,
		Intrinsic<[llvm_v8i32_ty], [llvm_v16i16_ty,
		llvm_v16i16_ty], [IntrNoMem, Commutative]>;
		def int_x86_avx2_pavg_b : GCCBuiltin<"__builtin_ia32_pavgb256">,
		Intrinsic<[llvm_v32i8_ty], [llvm_v32i8_ty,
		llvm_v32i8_ty], [IntrNoMem, Commutative]>;
		def int_x86_avx2_pavg_w : GCCBuiltin<"__builtin_ia32_pavgw256">,
		Intrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty,
		llvm_v16i16_ty], [IntrNoMem, Commutative]>;
		def int_x86_avx2_psad_bw : GCCBuiltin<"__builtin_ia32_psadbw256">,
		Intrinsic<[llvm_v4i64_ty], [llvm_v32i8_ty,
		llvm_v32i8_ty], [IntrNoMem, Commutative]>;
		}

		// Vector min, max
		let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
		def int_x86_avx2_pmaxu_b : GCCBuiltin<"__builtin_ia32_pmaxub256">,
		Intrinsic<[llvm_v32i8_ty], [llvm_v32i8_ty,
		llvm_v32i8_ty], [IntrNoMem, Commutative]>;
		def int_x86_avx2_pmaxu_w : GCCBuiltin<"__builtin_ia32_pmaxuw256">,
		Intrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty,
		llvm_v16i16_ty], [IntrNoMem, Commutative]>;
		def int_x86_avx2_pmaxu_d : GCCBuiltin<"__builtin_ia32_pmaxud256">,
		Intrinsic<[llvm_v8i32_ty], [llvm_v8i32_ty,
		llvm_v8i32_ty], [IntrNoMem, Commutative]>;
		def int_x86_avx2_pmaxs_b : GCCBuiltin<"__builtin_ia32_pmaxsb256">,
		Intrinsic<[llvm_v32i8_ty], [llvm_v32i8_ty,
		llvm_v32i8_ty], [IntrNoMem, Commutative]>;
		def int_x86_avx2_pmaxs_w : GCCBuiltin<"__builtin_ia32_pmaxsw256">,
		Intrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty,
		llvm_v16i16_ty], [IntrNoMem, Commutative]>;
		def int_x86_avx2_pmaxs_d : GCCBuiltin<"__builtin_ia32_pmaxsd256">,
		Intrinsic<[llvm_v8i32_ty], [llvm_v8i32_ty,
		llvm_v8i32_ty], [IntrNoMem, Commutative]>;
		def int_x86_avx2_pminu_b : GCCBuiltin<"__builtin_ia32_pminub256">,
		Intrinsic<[llvm_v32i8_ty], [llvm_v32i8_ty,
		llvm_v32i8_ty], [IntrNoMem, Commutative]>;
		def int_x86_avx2_pminu_w : GCCBuiltin<"__builtin_ia32_pminuw256">,
		Intrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty,
		llvm_v16i16_ty], [IntrNoMem, Commutative]>;
		def int_x86_avx2_pminu_d : GCCBuiltin<"__builtin_ia32_pminud256">,
		Intrinsic<[llvm_v8i32_ty], [llvm_v8i32_ty,
		llvm_v8i32_ty], [IntrNoMem, Commutative]>;
		def int_x86_avx2_pmins_b : GCCBuiltin<"__builtin_ia32_pminsb256">,
		Intrinsic<[llvm_v32i8_ty], [llvm_v32i8_ty,
		llvm_v32i8_ty], [IntrNoMem, Commutative]>;
		def int_x86_avx2_pmins_w : GCCBuiltin<"__builtin_ia32_pminsw256">,
		Intrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty,
		llvm_v16i16_ty], [IntrNoMem, Commutative]>;
		def int_x86_avx2_pmins_d : GCCBuiltin<"__builtin_ia32_pminsd256">,
		Intrinsic<[llvm_v8i32_ty], [llvm_v8i32_ty,
		llvm_v8i32_ty], [IntrNoMem, Commutative]>;
		}

		// Integer shift ops.
		let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
		def int_x86_avx2_psll_w : GCCBuiltin<"__builtin_ia32_psllw256">,
		Intrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty,
		llvm_v8i16_ty], [IntrNoMem]>;
		def int_x86_avx2_psll_d : GCCBuiltin<"__builtin_ia32_pslld256">,
		Intrinsic<[llvm_v8i32_ty], [llvm_v8i32_ty,
		llvm_v4i32_ty], [IntrNoMem]>;
		def int_x86_avx2_psll_q : GCCBuiltin<"__builtin_ia32_psllq256">,
		Intrinsic<[llvm_v4i64_ty], [llvm_v4i64_ty,
		llvm_v2i64_ty], [IntrNoMem]>;
		def int_x86_avx2_psrl_w : GCCBuiltin<"__builtin_ia32_psrlw256">,
		Intrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty,
		llvm_v8i16_ty], [IntrNoMem]>;
		def int_x86_avx2_psrl_d : GCCBuiltin<"__builtin_ia32_psrld256">,
		Intrinsic<[llvm_v8i32_ty], [llvm_v8i32_ty,
		llvm_v4i32_ty], [IntrNoMem]>;
		def int_x86_avx2_psrl_q : GCCBuiltin<"__builtin_ia32_psrlq256">,
		Intrinsic<[llvm_v4i64_ty], [llvm_v4i64_ty,
		llvm_v2i64_ty], [IntrNoMem]>;
		def int_x86_avx2_psra_w : GCCBuiltin<"__builtin_ia32_psraw256">,
		Intrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty,
		llvm_v8i16_ty], [IntrNoMem]>;
		def int_x86_avx2_psra_d : GCCBuiltin<"__builtin_ia32_psrad256">,
		Intrinsic<[llvm_v8i32_ty], [llvm_v8i32_ty,
		llvm_v4i32_ty], [IntrNoMem]>;

		def int_x86_avx2_pslli_w : GCCBuiltin<"__builtin_ia32_psllwi256">,
		Intrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty,
		llvm_i32_ty], [IntrNoMem]>;
		def int_x86_avx2_pslli_d : GCCBuiltin<"__builtin_ia32_pslldi256">,
		Intrinsic<[llvm_v8i32_ty], [llvm_v8i32_ty,
		llvm_i32_ty], [IntrNoMem]>;
		def int_x86_avx2_pslli_q : GCCBuiltin<"__builtin_ia32_psllqi256">,
		Intrinsic<[llvm_v4i64_ty], [llvm_v4i64_ty,
		llvm_i32_ty], [IntrNoMem]>;
		def int_x86_avx2_psrli_w : GCCBuiltin<"__builtin_ia32_psrlwi256">,
		Intrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty,
		llvm_i32_ty], [IntrNoMem]>;
		def int_x86_avx2_psrli_d : GCCBuiltin<"__builtin_ia32_psrldi256">,
		Intrinsic<[llvm_v8i32_ty], [llvm_v8i32_ty,
		llvm_i32_ty], [IntrNoMem]>;
		def int_x86_avx2_psrli_q : GCCBuiltin<"__builtin_ia32_psrlqi256">,
		Intrinsic<[llvm_v4i64_ty], [llvm_v4i64_ty,
		llvm_i32_ty], [IntrNoMem]>;
		def int_x86_avx2_psrai_w : GCCBuiltin<"__builtin_ia32_psrawi256">,
		Intrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty,
		llvm_i32_ty], [IntrNoMem]>;
		def int_x86_avx2_psrai_d : GCCBuiltin<"__builtin_ia32_psradi256">,
		Intrinsic<[llvm_v8i32_ty], [llvm_v8i32_ty,
		llvm_i32_ty], [IntrNoMem]>;

		def int_x86_avx2_psll_dq : GCCBuiltin<"__builtin_ia32_pslldqi256">,
		Intrinsic<[llvm_v4i64_ty], [llvm_v4i64_ty,
		llvm_i32_ty], [IntrNoMem]>;
		def int_x86_avx2_psrl_dq : GCCBuiltin<"__builtin_ia32_psrldqi256">,
		Intrinsic<[llvm_v4i64_ty], [llvm_v4i64_ty,
		llvm_i32_ty], [IntrNoMem]>;
		def int_x86_avx2_psll_dq_bs : GCCBuiltin<"__builtin_ia32_pslldqi256_bytes
		hift">,
		Intrinsic<[llvm_v4i64_ty], [llvm_v4i64_ty,
		llvm_i32_ty], [IntrNoMem]>;
		def int_x86_avx2_psrl_dq_bs : GCCBuiltin<"__builtin_ia32_psrldqi256_bytes
		hift">,
		Intrinsic<[llvm_v4i64_ty], [llvm_v4i64_ty,
		llvm_i32_ty], [IntrNoMem]>;
		}

		// Pack ops.
		let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
		def int_x86_avx2_packsswb : GCCBuiltin<"__builtin_ia32_packsswb256">,
		Intrinsic<[llvm_v32i8_ty], [llvm_v16i16_ty,
		llvm_v16i16_ty], [IntrNoMem]>;
		def int_x86_avx2_packssdw : GCCBuiltin<"__builtin_ia32_packssdw256">,
		Intrinsic<[llvm_v16i16_ty], [llvm_v8i32_ty,
		llvm_v8i32_ty], [IntrNoMem]>;
		def int_x86_avx2_packuswb : GCCBuiltin<"__builtin_ia32_packuswb256">,
		Intrinsic<[llvm_v32i8_ty], [llvm_v16i16_ty,
		llvm_v16i16_ty], [IntrNoMem]>;
		def int_x86_avx2_packusdw : GCCBuiltin<"__builtin_ia32_packusdw256">,
		Intrinsic<[llvm_v16i16_ty], [llvm_v8i32_ty,
		llvm_v8i32_ty], [IntrNoMem]>;
		}

		// Absolute value ops
		let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
		def int_x86_avx2_pabs_b : GCCBuiltin<"__builtin_ia32_pabsb256">,
		Intrinsic<[llvm_v32i8_ty], [llvm_v32i8_ty], [IntrNoMem]>;
		def int_x86_avx2_pabs_w : GCCBuiltin<"__builtin_ia32_pabsw256">,
		Intrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty], [IntrNoMem]>;
		def int_x86_avx2_pabs_d : GCCBuiltin<"__builtin_ia32_pabsd256">,
		Intrinsic<[llvm_v8i32_ty], [llvm_v8i32_ty], [IntrNoMem]>;
		}

		// Horizontal arithmetic ops
		let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
		def int_x86_avx2_phadd_w : GCCBuiltin<"__builtin_ia32_phaddw256">,
		Intrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty,
		llvm_v16i16_ty], [IntrNoMem]>;
		def int_x86_avx2_phadd_d : GCCBuiltin<"__builtin_ia32_phaddd256">,
		Intrinsic<[llvm_v8i32_ty], [llvm_v8i32_ty,
		llvm_v8i32_ty], [IntrNoMem]>;
		def int_x86_avx2_phadd_sw : GCCBuiltin<"__builtin_ia32_phaddsw256">,
		Intrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty,
		llvm_v16i16_ty], [IntrNoMem]>;
		def int_x86_avx2_phsub_w : GCCBuiltin<"__builtin_ia32_phsubw256">,
		Intrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty,
		llvm_v16i16_ty], [IntrNoMem]>;
		def int_x86_avx2_phsub_d : GCCBuiltin<"__builtin_ia32_phsubd256">,
		Intrinsic<[llvm_v8i32_ty], [llvm_v8i32_ty,
		llvm_v8i32_ty], [IntrNoMem]>;
		def int_x86_avx2_phsub_sw : GCCBuiltin<"__builtin_ia32_phsubsw256">,
		Intrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty,
		llvm_v16i16_ty], [IntrNoMem]>;
		def int_x86_avx2_pmadd_ub_sw : GCCBuiltin<"__builtin_ia32_pmaddubsw256">,
		Intrinsic<[llvm_v16i16_ty], [llvm_v32i8_ty,
		llvm_v32i8_ty], [IntrNoMem]>;
		}

		// Sign ops
		let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
		def int_x86_avx2_psign_b : GCCBuiltin<"__builtin_ia32_psignb256">,
		Intrinsic<[llvm_v32i8_ty], [llvm_v32i8_ty,
		llvm_v32i8_ty], [IntrNoMem]>;
		def int_x86_avx2_psign_w : GCCBuiltin<"__builtin_ia32_psignw256">,
		Intrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty,
		llvm_v16i16_ty], [IntrNoMem]>;
		def int_x86_avx2_psign_d : GCCBuiltin<"__builtin_ia32_psignd256">,
		Intrinsic<[llvm_v8i32_ty], [llvm_v8i32_ty,
		llvm_v8i32_ty], [IntrNoMem]>;
		}

		// Packed multiply high with round and scale
		let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
		def int_x86_avx2_pmul_hr_sw : GCCBuiltin<"__builtin_ia32_pmulhrsw256">,
		Intrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty,
		llvm_v16i16_ty], [IntrNoMem, Commutative]>;
		}

		// Vector sign and zero extend
		let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
		def int_x86_avx2_pmovsxbd : GCCBuiltin<"__builtin_ia32_pmovsxbd256">,
		Intrinsic<[llvm_v8i32_ty], [llvm_v16i8_ty],
		[IntrNoMem]>;
		def int_x86_avx2_pmovsxbq : GCCBuiltin<"__builtin_ia32_pmovsxbq256">,
		Intrinsic<[llvm_v4i64_ty], [llvm_v16i8_ty],
		[IntrNoMem]>;
		def int_x86_avx2_pmovsxbw : GCCBuiltin<"__builtin_ia32_pmovsxbw256">,
		Intrinsic<[llvm_v16i16_ty], [llvm_v16i8_ty],
		[IntrNoMem]>;
		def int_x86_avx2_pmovsxdq : GCCBuiltin<"__builtin_ia32_pmovsxdq256">,
		Intrinsic<[llvm_v4i64_ty], [llvm_v4i32_ty],
		[IntrNoMem]>;
		def int_x86_avx2_pmovsxwd : GCCBuiltin<"__builtin_ia32_pmovsxwd256">,
		Intrinsic<[llvm_v8i32_ty], [llvm_v8i16_ty],
		[IntrNoMem]>;
		def int_x86_avx2_pmovsxwq : GCCBuiltin<"__builtin_ia32_pmovsxwq256">,
		Intrinsic<[llvm_v4i64_ty], [llvm_v8i16_ty],
		[IntrNoMem]>;
		def int_x86_avx2_pmovzxbd : GCCBuiltin<"__builtin_ia32_pmovzxbd256">,
		Intrinsic<[llvm_v8i32_ty], [llvm_v16i8_ty],
		[IntrNoMem]>;
		def int_x86_avx2_pmovzxbq : GCCBuiltin<"__builtin_ia32_pmovzxbq256">,
		Intrinsic<[llvm_v4i64_ty], [llvm_v16i8_ty],
		[IntrNoMem]>;
		def int_x86_avx2_pmovzxbw : GCCBuiltin<"__builtin_ia32_pmovzxbw256">,
		Intrinsic<[llvm_v16i16_ty], [llvm_v16i8_ty],
		[IntrNoMem]>;
		def int_x86_avx2_pmovzxdq : GCCBuiltin<"__builtin_ia32_pmovzxdq256">,
		Intrinsic<[llvm_v4i64_ty], [llvm_v4i32_ty],
		[IntrNoMem]>;
		def int_x86_avx2_pmovzxwd : GCCBuiltin<"__builtin_ia32_pmovzxwd256">,
		Intrinsic<[llvm_v8i32_ty], [llvm_v8i16_ty],
		[IntrNoMem]>;
		def int_x86_avx2_pmovzxwq : GCCBuiltin<"__builtin_ia32_pmovzxwq256">,
		Intrinsic<[llvm_v4i64_ty], [llvm_v8i16_ty],
		[IntrNoMem]>;
		}

		// Vector blend
		let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
		def int_x86_avx2_pblendvb : GCCBuiltin<"__builtin_ia32_pblendvb256">,
		Intrinsic<[llvm_v32i8_ty], [llvm_v32i8_ty, llvm_v32i8_ty,
		llvm_v32i8_ty], [IntrNoMem]>;
		def int_x86_avx2_pblendw : GCCBuiltin<"__builtin_ia32_pblendw256">,
		Intrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty, llvm_v16i16_ty,
		llvm_i32_ty], [IntrNoMem]>;
		def int_x86_avx2_pblendd_128 : GCCBuiltin<"__builtin_ia32_pblendd128">,
		Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty,
		llvm_i32_ty], [IntrNoMem]>;
		def int_x86_avx2_pblendd_256 : GCCBuiltin<"__builtin_ia32_pblendd256">,
		Intrinsic<[llvm_v8i32_ty], [llvm_v8i32_ty, llvm_v8i32_ty,
		llvm_i32_ty], [IntrNoMem]>;
		}

		// Vector load with broadcast
		let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
		def int_x86_avx2_vbroadcast_ss_ps :
		GCCBuiltin<"__builtin_ia32_vbroadcastss_ps">,
		Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty], [IntrNoMem]>;
		def int_x86_avx2_vbroadcast_sd_pd_256 :
		GCCBuiltin<"__builtin_ia32_vbroadcastsd_pd256">,
		Intrinsic<[llvm_v4f64_ty], [llvm_v2f64_ty], [IntrNoMem]>;
		def int_x86_avx2_vbroadcast_ss_ps_256 :
		GCCBuiltin<"__builtin_ia32_vbroadcastss_ps256">,
		Intrinsic<[llvm_v8f32_ty], [llvm_v4f32_ty], [IntrNoMem]>;
		def int_x86_avx2_vbroadcasti128 :
		GCCBuiltin<"__builtin_ia32_vbroadcastsi256">,
		Intrinsic<[llvm_v4i64_ty], [llvm_ptr_ty], [IntrReadMem]>;
		def int_x86_avx2_pbroadcastb_128 :
		GCCBuiltin<"__builtin_ia32_pbroadcastb128">,
		Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty], [IntrNoMem]>;
		def int_x86_avx2_pbroadcastb_256 :
		GCCBuiltin<"__builtin_ia32_pbroadcastb256">,
		Intrinsic<[llvm_v32i8_ty], [llvm_v16i8_ty], [IntrNoMem]>;
		def int_x86_avx2_pbroadcastw_128 :
		GCCBuiltin<"__builtin_ia32_pbroadcastw128">,
		Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty], [IntrNoMem]>;
		def int_x86_avx2_pbroadcastw_256 :
		GCCBuiltin<"__builtin_ia32_pbroadcastw256">,
		Intrinsic<[llvm_v16i16_ty], [llvm_v8i16_ty], [IntrNoMem]>;
		def int_x86_avx2_pbroadcastd_128 :
		GCCBuiltin<"__builtin_ia32_pbroadcastd128">,
		Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty], [IntrNoMem]>;
		def int_x86_avx2_pbroadcastd_256 :
		GCCBuiltin<"__builtin_ia32_pbroadcastd256">,
		Intrinsic<[llvm_v8i32_ty], [llvm_v4i32_ty], [IntrNoMem]>;
		def int_x86_avx2_pbroadcastq_128 :
		GCCBuiltin<"__builtin_ia32_pbroadcastq128">,
		Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty], [IntrNoMem]>;
		def int_x86_avx2_pbroadcastq_256 :
		GCCBuiltin<"__builtin_ia32_pbroadcastq256">,
		Intrinsic<[llvm_v4i64_ty], [llvm_v2i64_ty], [IntrNoMem]>;
		}

		// Vector permutation
		let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
		def int_x86_avx2_permd : GCCBuiltin<"__builtin_ia32_permvarsi256">,
		Intrinsic<[llvm_v8i32_ty], [llvm_v8i32_ty, llvm_v8i32_ty],
		[IntrNoMem]>;
		def int_x86_avx2_permps : GCCBuiltin<"__builtin_ia32_permvarsf256">,
		Intrinsic<[llvm_v8f32_ty], [llvm_v8f32_ty, llvm_v8f32_ty],
		[IntrNoMem]>;
		def int_x86_avx2_vperm2i128 : GCCBuiltin<"__builtin_ia32_permti256">,
		Intrinsic<[llvm_v4i64_ty], [llvm_v4i64_ty,
		llvm_v4i64_ty, llvm_i8_ty], [IntrNoMem]>;
		}

		// Vector extract and insert
		let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
		def int_x86_avx2_vextracti128 : GCCBuiltin<"__builtin_ia32_extract128i256
		">,
		Intrinsic<[llvm_v2i64_ty], [llvm_v4i64_ty,
		llvm_i8_ty], [IntrNoMem]>;
		def int_x86_avx2_vinserti128 : GCCBuiltin<"__builtin_ia32_insert128i256">
		,
		Intrinsic<[llvm_v4i64_ty], [llvm_v4i64_ty,
		llvm_v2i64_ty, llvm_i8_ty], [IntrNoMem]>;
		}

		// Conditional load ops
		let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
		def int_x86_avx2_maskload_d : GCCBuiltin<"__builtin_ia32_maskloadd">,
		Intrinsic<[llvm_v4i32_ty], [llvm_ptr_ty, llvm_v4i32_ty], [IntrReadM
		em]>;
		def int_x86_avx2_maskload_q : GCCBuiltin<"__builtin_ia32_maskloadq">,
		Intrinsic<[llvm_v2i64_ty], [llvm_ptr_ty, llvm_v2i64_ty], [IntrReadM
		em]>;
		def int_x86_avx2_maskload_d_256 : GCCBuiltin<"__builtin_ia32_maskloadd256
		">,
		Intrinsic<[llvm_v8i32_ty], [llvm_ptr_ty, llvm_v8i32_ty], [IntrReadM
		em]>;
		def int_x86_avx2_maskload_q_256 : GCCBuiltin<"__builtin_ia32_maskloadq256
		">,
		Intrinsic<[llvm_v4i64_ty], [llvm_ptr_ty, llvm_v4i64_ty], [IntrReadM
		em]>;
		}

		// Conditional store ops
		let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
		def int_x86_avx2_maskstore_d : GCCBuiltin<"__builtin_ia32_maskstored">,
		Intrinsic<[], [llvm_ptr_ty, llvm_v4i32_ty, llvm_v4i32_ty], []>;
		def int_x86_avx2_maskstore_q : GCCBuiltin<"__builtin_ia32_maskstoreq">,
		Intrinsic<[], [llvm_ptr_ty, llvm_v2i64_ty, llvm_v2i64_ty], []>;
		def int_x86_avx2_maskstore_d_256 :
		GCCBuiltin<"__builtin_ia32_maskstored256">,
		Intrinsic<[], [llvm_ptr_ty, llvm_v8i32_ty, llvm_v8i32_ty], []>;
		def int_x86_avx2_maskstore_q_256 :
		GCCBuiltin<"__builtin_ia32_maskstoreq256">,
		Intrinsic<[], [llvm_ptr_ty, llvm_v4i64_ty, llvm_v4i64_ty], []>;
		}

		// Variable bit shift ops
		let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
		def int_x86_avx2_psllv_d : GCCBuiltin<"__builtin_ia32_psllv4si">,
		Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
		[IntrNoMem]>;
		def int_x86_avx2_psllv_d_256 : GCCBuiltin<"__builtin_ia32_psllv8si">,
		Intrinsic<[llvm_v8i32_ty], [llvm_v8i32_ty, llvm_v8i32_ty],
		[IntrNoMem]>;
		def int_x86_avx2_psllv_q : GCCBuiltin<"__builtin_ia32_psllv2di">,
		Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
		[IntrNoMem]>;
		def int_x86_avx2_psllv_q_256 : GCCBuiltin<"__builtin_ia32_psllv4di">,
		Intrinsic<[llvm_v4i64_ty], [llvm_v4i64_ty, llvm_v4i64_ty],
		[IntrNoMem]>;

		def int_x86_avx2_psrlv_d : GCCBuiltin<"__builtin_ia32_psrlv4si">,
		Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
		[IntrNoMem]>;
		def int_x86_avx2_psrlv_d_256 : GCCBuiltin<"__builtin_ia32_psrlv8si">,
		Intrinsic<[llvm_v8i32_ty], [llvm_v8i32_ty, llvm_v8i32_ty],
		[IntrNoMem]>;
		def int_x86_avx2_psrlv_q : GCCBuiltin<"__builtin_ia32_psrlv2di">,
		Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
		[IntrNoMem]>;
		def int_x86_avx2_psrlv_q_256 : GCCBuiltin<"__builtin_ia32_psrlv4di">,
		Intrinsic<[llvm_v4i64_ty], [llvm_v4i64_ty, llvm_v4i64_ty],
		[IntrNoMem]>;

		def int_x86_avx2_psrav_d : GCCBuiltin<"__builtin_ia32_psrav4si">,
		Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
		[IntrNoMem]>;
		def int_x86_avx2_psrav_d_256 : GCCBuiltin<"__builtin_ia32_psrav8si">,
		Intrinsic<[llvm_v8i32_ty], [llvm_v8i32_ty, llvm_v8i32_ty],
		[IntrNoMem]>;
		}

		// Misc.
		let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
		def int_x86_avx2_pmovmskb : GCCBuiltin<"__builtin_ia32_pmovmskb256">,
		Intrinsic<[llvm_i32_ty], [llvm_v32i8_ty], [IntrNoMem]>;
		def int_x86_avx2_pshuf_b : GCCBuiltin<"__builtin_ia32_pshufb256">,
		Intrinsic<[llvm_v32i8_ty], [llvm_v32i8_ty,
		llvm_v32i8_ty], [IntrNoMem]>;
		def int_x86_avx2_mpsadbw : GCCBuiltin<"__builtin_ia32_mpsadbw256">,
		Intrinsic<[llvm_v16i16_ty], [llvm_v32i8_ty, llvm_v32i8_ty,
		llvm_i32_ty], [IntrNoMem, Commutative]>;
		def int_x86_avx2_movntdqa : GCCBuiltin<"__builtin_ia32_movntdqa256">,
		Intrinsic<[llvm_v4i64_ty], [llvm_ptr_ty], [IntrReadMem]>;
		}

		//===----------------------------------------------------------------------
		===//
		// FMA4

		let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
		def int_x86_fma4_vfmadd_ss : GCCBuiltin<"__builtin_ia32_vfmaddss">,
		Intrinsic<[llvm_v4f32_ty],
		[llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty],
		[IntrNoMem]>;
		def int_x86_fma4_vfmadd_sd : GCCBuiltin<"__builtin_ia32_vfmaddsd">,
		Intrinsic<[llvm_v2f64_ty],
		[llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty],
		[IntrNoMem]>;
		def int_x86_fma4_vfmadd_ps : GCCBuiltin<"__builtin_ia32_vfmaddps">,
		Intrinsic<[llvm_v4f32_ty],
		[llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty],
		[IntrNoMem]>;
		def int_x86_fma4_vfmadd_pd : GCCBuiltin<"__builtin_ia32_vfmaddpd">,
		Intrinsic<[llvm_v2f64_ty],
		[llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty],
		[IntrNoMem]>;
		def int_x86_fma4_vfmadd_ps_256 : GCCBuiltin<"__builtin_ia32_vfmaddps256">
		,
		Intrinsic<[llvm_v8f32_ty],
		[llvm_v8f32_ty, llvm_v8f32_ty, llvm_v8f32_ty],
		[IntrNoMem]>;
		def int_x86_fma4_vfmadd_pd_256 : GCCBuiltin<"__builtin_ia32_vfmaddpd256">
		,
		Intrinsic<[llvm_v4f64_ty],
		[llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4f64_ty],
		[IntrNoMem]>;
		def int_x86_fma4_vfmsub_ss : GCCBuiltin<"__builtin_ia32_vfmsubss">,
		Intrinsic<[llvm_v4f32_ty],
		[llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty],
		[IntrNoMem]>;
		def int_x86_fma4_vfmsub_sd : GCCBuiltin<"__builtin_ia32_vfmsubsd">,
		Intrinsic<[llvm_v2f64_ty],
		[llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty],
		[IntrNoMem]>;
		def int_x86_fma4_vfmsub_ps : GCCBuiltin<"__builtin_ia32_vfmsubps">,
		Intrinsic<[llvm_v4f32_ty],
		[llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty],
		[IntrNoMem]>;
		def int_x86_fma4_vfmsub_pd : GCCBuiltin<"__builtin_ia32_vfmsubpd">,
		Intrinsic<[llvm_v2f64_ty],
		[llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty],
		[IntrNoMem]>;
		def int_x86_fma4_vfmsub_ps_256 : GCCBuiltin<"__builtin_ia32_vfmsubps256">
		,
		Intrinsic<[llvm_v8f32_ty],
		[llvm_v8f32_ty, llvm_v8f32_ty, llvm_v8f32_ty],
		[IntrNoMem]>;
		def int_x86_fma4_vfmsub_pd_256 : GCCBuiltin<"__builtin_ia32_vfmsubpd256">
		,
		Intrinsic<[llvm_v4f64_ty],
		[llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4f64_ty],
		[IntrNoMem]>;
		def int_x86_fma4_vfnmadd_ss : GCCBuiltin<"__builtin_ia32_vfnmaddss">,
		Intrinsic<[llvm_v4f32_ty],
		[llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty],
		[IntrNoMem]>;
		def int_x86_fma4_vfnmadd_sd : GCCBuiltin<"__builtin_ia32_vfnmaddsd">,
		Intrinsic<[llvm_v2f64_ty],
		[llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty],
		[IntrNoMem]>;
		def int_x86_fma4_vfnmadd_ps : GCCBuiltin<"__builtin_ia32_vfnmaddps">,
		Intrinsic<[llvm_v4f32_ty],
		[llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty],
		[IntrNoMem]>;
		def int_x86_fma4_vfnmadd_pd : GCCBuiltin<"__builtin_ia32_vfnmaddpd">,
		Intrinsic<[llvm_v2f64_ty],
		[llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty],
		[IntrNoMem]>;
		def int_x86_fma4_vfnmadd_ps_256 : GCCBuiltin<"__builtin_ia32_vfnmaddps256
		">,
		Intrinsic<[llvm_v8f32_ty],
		[llvm_v8f32_ty, llvm_v8f32_ty, llvm_v8f32_ty],
		[IntrNoMem]>;
		def int_x86_fma4_vfnmadd_pd_256 : GCCBuiltin<"__builtin_ia32_vfnmaddpd256
		">,
		Intrinsic<[llvm_v4f64_ty],
		[llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4f64_ty],
		[IntrNoMem]>;
		def int_x86_fma4_vfnmsub_ss : GCCBuiltin<"__builtin_ia32_vfnmsubss">,
		Intrinsic<[llvm_v4f32_ty],
		[llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty],
		[IntrNoMem]>;
		def int_x86_fma4_vfnmsub_sd : GCCBuiltin<"__builtin_ia32_vfnmsubsd">,
		Intrinsic<[llvm_v2f64_ty],
		[llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty],
		[IntrNoMem]>;
		def int_x86_fma4_vfnmsub_ps : GCCBuiltin<"__builtin_ia32_vfnmsubps">,
		Intrinsic<[llvm_v4f32_ty],
		[llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty],
		[IntrNoMem]>;
		def int_x86_fma4_vfnmsub_pd : GCCBuiltin<"__builtin_ia32_vfnmsubpd">,
		Intrinsic<[llvm_v2f64_ty],
		[llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty],
		[IntrNoMem]>;
		def int_x86_fma4_vfnmsub_ps_256 : GCCBuiltin<"__builtin_ia32_vfnmsubps256
		">,
		Intrinsic<[llvm_v8f32_ty],
		[llvm_v8f32_ty, llvm_v8f32_ty, llvm_v8f32_ty],
		[IntrNoMem]>;
		def int_x86_fma4_vfnmsub_pd_256 : GCCBuiltin<"__builtin_ia32_vfnmsubpd256
		">,
		Intrinsic<[llvm_v4f64_ty],
		[llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4f64_ty],
		[IntrNoMem]>;
		def int_x86_fma4_vfmaddsub_ps : GCCBuiltin<"__builtin_ia32_vfmaddsubps">,
		Intrinsic<[llvm_v4f32_ty],
		[llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty],
		[IntrNoMem]>;
		def int_x86_fma4_vfmaddsub_pd : GCCBuiltin<"__builtin_ia32_vfmaddsubpd">,
		Intrinsic<[llvm_v2f64_ty],
		[llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty],
		[IntrNoMem]>;
		def int_x86_fma4_vfmaddsub_ps_256 :
		GCCBuiltin<"__builtin_ia32_vfmaddsubps256">,
		Intrinsic<[llvm_v8f32_ty],
		[llvm_v8f32_ty, llvm_v8f32_ty, llvm_v8f32_ty],
		[IntrNoMem]>;
		def int_x86_fma4_vfmaddsub_pd_256 :
		GCCBuiltin<"__builtin_ia32_vfmaddsubpd256">,
		Intrinsic<[llvm_v4f64_ty],
		[llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4f64_ty],
		[IntrNoMem]>;
		def int_x86_fma4_vfmsubadd_ps : GCCBuiltin<"__builtin_ia32_vfmsubaddps">,
		Intrinsic<[llvm_v4f32_ty],
		[llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty],
		[IntrNoMem]>;
		def int_x86_fma4_vfmsubadd_pd : GCCBuiltin<"__builtin_ia32_vfmsubaddpd">,
		Intrinsic<[llvm_v2f64_ty],
		[llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty],
		[IntrNoMem]>;
		def int_x86_fma4_vfmsubadd_ps_256 :
		GCCBuiltin<"__builtin_ia32_vfmsubaddps256">,
		Intrinsic<[llvm_v8f32_ty],
		[llvm_v8f32_ty, llvm_v8f32_ty, llvm_v8f32_ty],
		[IntrNoMem]>;
		def int_x86_fma4_vfmsubadd_pd_256 :
		GCCBuiltin<"__builtin_ia32_vfmsubaddpd256">,
		Intrinsic<[llvm_v4f64_ty],
		[llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4f64_ty],
		[IntrNoMem]>;
		}

		//===----------------------------------------------------------------------
		===//
		// XOP

		def int_x86_xop_vpermil2pd : GCCBuiltin<"__builtin_ia32_vpermil2pd">,
		Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty,
		llvm_v2f64_ty, llvm_i8_ty],
		[IntrNoMem]>;

		def int_x86_xop_vpermil2pd_256 :
		GCCBuiltin<"__builtin_ia32_vpermil2pd256">,
		Intrinsic<[llvm_v4f64_ty], [llvm_v4f64_ty, llvm_v4f64_ty,
		llvm_v4f64_ty, llvm_i8_ty],
		[IntrNoMem]>;

		def int_x86_xop_vpermil2ps : GCCBuiltin<"__builtin_ia32_vpermil2ps">,
		Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty,
		llvm_v4f32_ty, llvm_i8_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpermil2ps_256 :
		GCCBuiltin<"__builtin_ia32_vpermil2ps256">,
		Intrinsic<[llvm_v8f32_ty], [llvm_v8f32_ty, llvm_v8f32_ty,
		llvm_v8f32_ty, llvm_i8_ty],
		[IntrNoMem]>;

		def int_x86_xop_vfrcz_pd :
		GCCBuiltin<"__builtin_ia32_vfrczpd">,
		Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty], [IntrNoMem]>;
		def int_x86_xop_vfrcz_ps :
		GCCBuiltin<"__builtin_ia32_vfrczps">,
		Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty], [IntrNoMem]>;
		def int_x86_xop_vfrcz_sd :
		GCCBuiltin<"__builtin_ia32_vfrczsd">,
		Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty],
		[IntrNoMem]>;
		def int_x86_xop_vfrcz_ss :
		GCCBuiltin<"__builtin_ia32_vfrczss">,
		Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty],
		[IntrNoMem]>;
		def int_x86_xop_vfrcz_pd_256 :
		GCCBuiltin<"__builtin_ia32_vfrczpd256">,
		Intrinsic<[llvm_v4f64_ty], [llvm_v4f64_ty], [IntrNoMem]>;
		def int_x86_xop_vfrcz_ps_256 :
		GCCBuiltin<"__builtin_ia32_vfrczps256">,
		Intrinsic<[llvm_v8f32_ty], [llvm_v8f32_ty], [IntrNoMem]>;
		def int_x86_xop_vpcmov :
		GCCBuiltin<"__builtin_ia32_vpcmov">,
		Intrinsic<[llvm_v2i64_ty],
		[llvm_v2i64_ty, llvm_v2i64_ty, llvm_v2i64_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpcmov_256 :
		GCCBuiltin<"__builtin_ia32_vpcmov_256">,
		Intrinsic<[llvm_v4i64_ty],
		[llvm_v4i64_ty, llvm_v4i64_ty, llvm_v4i64_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpcomeqb :
		GCCBuiltin<"__builtin_ia32_vpcomeqb">,
		Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpcomeqw :
		GCCBuiltin<"__builtin_ia32_vpcomeqw">,
		Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpcomeqd :
		GCCBuiltin<"__builtin_ia32_vpcomeqd">,
		Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpcomeqq :
		GCCBuiltin<"__builtin_ia32_vpcomeqq">,
		Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpcomequb :
		GCCBuiltin<"__builtin_ia32_vpcomequb">,
		Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpcomequd :
		GCCBuiltin<"__builtin_ia32_vpcomequd">,
		Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpcomequq :
		GCCBuiltin<"__builtin_ia32_vpcomequq">,
		Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpcomequw :
		GCCBuiltin<"__builtin_ia32_vpcomequw">,
		Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpcomfalseb :
		GCCBuiltin<"__builtin_ia32_vpcomfalseb">,
		Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpcomfalsed :
		GCCBuiltin<"__builtin_ia32_vpcomfalsed">,
		Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpcomfalseq :
		GCCBuiltin<"__builtin_ia32_vpcomfalseq">,
		Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpcomfalseub :
		GCCBuiltin<"__builtin_ia32_vpcomfalseub">,
		Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpcomfalseud :
		GCCBuiltin<"__builtin_ia32_vpcomfalseud">,
		Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpcomfalseuq :
		GCCBuiltin<"__builtin_ia32_vpcomfalseuq">,
		Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpcomfalseuw :
		GCCBuiltin<"__builtin_ia32_vpcomfalseuw">,
		Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpcomfalsew :
		GCCBuiltin<"__builtin_ia32_vpcomfalsew">,
		Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpcomgeb :
		GCCBuiltin<"__builtin_ia32_vpcomgeb">,
		Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpcomged :
		GCCBuiltin<"__builtin_ia32_vpcomged">,
		Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpcomgeq :
		GCCBuiltin<"__builtin_ia32_vpcomgeq">,
		Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpcomgeub :
		GCCBuiltin<"__builtin_ia32_vpcomgeub">,
		Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpcomgeud :
		GCCBuiltin<"__builtin_ia32_vpcomgeud">,
		Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpcomgeuq :
		GCCBuiltin<"__builtin_ia32_vpcomgeuq">,
		Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpcomgeuw :
		GCCBuiltin<"__builtin_ia32_vpcomgeuw">,
		Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpcomgew :
		GCCBuiltin<"__builtin_ia32_vpcomgew">,
		Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpcomgtb :
		GCCBuiltin<"__builtin_ia32_vpcomgtb">,
		Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpcomgtd :
		GCCBuiltin<"__builtin_ia32_vpcomgtd">,
		Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpcomgtq :
		GCCBuiltin<"__builtin_ia32_vpcomgtq">,
		Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpcomgtub :
		GCCBuiltin<"__builtin_ia32_vpcomgtub">,
		Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpcomgtud :
		GCCBuiltin<"__builtin_ia32_vpcomgtud">,
		Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpcomgtuq :
		GCCBuiltin<"__builtin_ia32_vpcomgtuq">,
		Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpcomgtuw :
		GCCBuiltin<"__builtin_ia32_vpcomgtuw">,
		Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpcomgtw :
		GCCBuiltin<"__builtin_ia32_vpcomgtw">,
		Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpcomleb :
		GCCBuiltin<"__builtin_ia32_vpcomleb">,
		Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpcomled :
		GCCBuiltin<"__builtin_ia32_vpcomled">,
		Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpcomleq :
		GCCBuiltin<"__builtin_ia32_vpcomleq">,
		Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpcomleub :
		GCCBuiltin<"__builtin_ia32_vpcomleub">,
		Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpcomleud :
		GCCBuiltin<"__builtin_ia32_vpcomleud">,
		Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpcomleuq :
		GCCBuiltin<"__builtin_ia32_vpcomleuq">,
		Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpcomleuw :
		GCCBuiltin<"__builtin_ia32_vpcomleuw">,
		Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpcomlew :
		GCCBuiltin<"__builtin_ia32_vpcomlew">,
		Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpcomltb :
		GCCBuiltin<"__builtin_ia32_vpcomltb">,
		Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpcomltd :
		GCCBuiltin<"__builtin_ia32_vpcomltd">,
		Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpcomltq :
		GCCBuiltin<"__builtin_ia32_vpcomltq">,
		Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpcomltub :
		GCCBuiltin<"__builtin_ia32_vpcomltub">,
		Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpcomltud :
		GCCBuiltin<"__builtin_ia32_vpcomltud">,
		Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpcomltuq :
		GCCBuiltin<"__builtin_ia32_vpcomltuq">,
		Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpcomltuw :
		GCCBuiltin<"__builtin_ia32_vpcomltuw">,
		Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpcomltw :
		GCCBuiltin<"__builtin_ia32_vpcomltw">,
		Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpcomneb :
		GCCBuiltin<"__builtin_ia32_vpcomneb">,
		Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpcomned :
		GCCBuiltin<"__builtin_ia32_vpcomned">,
		Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpcomneq :
		GCCBuiltin<"__builtin_ia32_vpcomneq">,
		Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpcomneub :
		GCCBuiltin<"__builtin_ia32_vpcomneub">,
		Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpcomneud :
		GCCBuiltin<"__builtin_ia32_vpcomneud">,
		Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpcomneuq :
		GCCBuiltin<"__builtin_ia32_vpcomneuq">,
		Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpcomneuw :
		GCCBuiltin<"__builtin_ia32_vpcomneuw">,
		Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpcomnew :
		GCCBuiltin<"__builtin_ia32_vpcomnew">,
		Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpcomtrueb :
		GCCBuiltin<"__builtin_ia32_vpcomtrueb">,
		Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpcomtrued :
		GCCBuiltin<"__builtin_ia32_vpcomtrued">,
		Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpcomtrueq :
		GCCBuiltin<"__builtin_ia32_vpcomtrueq">,
		Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpcomtrueub :
		GCCBuiltin<"__builtin_ia32_vpcomtrueub">,
		Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpcomtrueud :
		GCCBuiltin<"__builtin_ia32_vpcomtrueud">,
		Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpcomtrueuq :
		GCCBuiltin<"__builtin_ia32_vpcomtrueuq">,
		Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpcomtrueuw :
		GCCBuiltin<"__builtin_ia32_vpcomtrueuw">,
		Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpcomtruew :
		GCCBuiltin<"__builtin_ia32_vpcomtruew">,
		Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty],
		[IntrNoMem]>;
		def int_x86_xop_vphaddbd :
		GCCBuiltin<"__builtin_ia32_vphaddbd">,
		Intrinsic<[llvm_v4i32_ty], [llvm_v16i8_ty], [IntrNoMem]>;
		def int_x86_xop_vphaddbq :
		GCCBuiltin<"__builtin_ia32_vphaddbq">,
		Intrinsic<[llvm_v2i64_ty], [llvm_v16i8_ty], [IntrNoMem]>;
		def int_x86_xop_vphaddbw :
		GCCBuiltin<"__builtin_ia32_vphaddbw">,
		Intrinsic<[llvm_v8i16_ty], [llvm_v16i8_ty], [IntrNoMem]>;
		def int_x86_xop_vphadddq :
		GCCBuiltin<"__builtin_ia32_vphadddq">,
		Intrinsic<[llvm_v2i64_ty], [llvm_v4i32_ty], [IntrNoMem]>;
		def int_x86_xop_vphaddubd :
		GCCBuiltin<"__builtin_ia32_vphaddubd">,
		Intrinsic<[llvm_v4i32_ty], [llvm_v16i8_ty], [IntrNoMem]>;
		def int_x86_xop_vphaddubq :
		GCCBuiltin<"__builtin_ia32_vphaddubq">,
		Intrinsic<[llvm_v2i64_ty], [llvm_v16i8_ty], [IntrNoMem]>;
		def int_x86_xop_vphaddubw :
		GCCBuiltin<"__builtin_ia32_vphaddubw">,
		Intrinsic<[llvm_v8i16_ty], [llvm_v16i8_ty], [IntrNoMem]>;
		def int_x86_xop_vphaddudq :
		GCCBuiltin<"__builtin_ia32_vphaddudq">,
		Intrinsic<[llvm_v2i64_ty], [llvm_v4i32_ty], [IntrNoMem]>;
		def int_x86_xop_vphadduwd :
		GCCBuiltin<"__builtin_ia32_vphadduwd">,
		Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty], [IntrNoMem]>;
		def int_x86_xop_vphadduwq :
		GCCBuiltin<"__builtin_ia32_vphadduwq">,
		Intrinsic<[llvm_v2i64_ty], [llvm_v8i16_ty], [IntrNoMem]>;
		def int_x86_xop_vphaddwd :
		GCCBuiltin<"__builtin_ia32_vphaddwd">,
		Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty], [IntrNoMem]>;
		def int_x86_xop_vphaddwq :
		GCCBuiltin<"__builtin_ia32_vphaddwq">,
		Intrinsic<[llvm_v2i64_ty], [llvm_v8i16_ty], [IntrNoMem]>;
		def int_x86_xop_vphsubbw :
		GCCBuiltin<"__builtin_ia32_vphsubbw">,
		Intrinsic<[llvm_v8i16_ty], [llvm_v16i8_ty], [IntrNoMem]>;
		def int_x86_xop_vphsubdq :
		GCCBuiltin<"__builtin_ia32_vphsubdq">,
		Intrinsic<[llvm_v2i64_ty], [llvm_v4i32_ty], [IntrNoMem]>;
		def int_x86_xop_vphsubwd :
		GCCBuiltin<"__builtin_ia32_vphsubwd">,
		Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty], [IntrNoMem]>;
		def int_x86_xop_vpmacsdd :
		GCCBuiltin<"__builtin_ia32_vpmacsdd">,
		Intrinsic<[llvm_v4i32_ty],
		[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpmacsdqh :
		GCCBuiltin<"__builtin_ia32_vpmacsdqh">,
		Intrinsic<[llvm_v2i64_ty],
		[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v2i64_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpmacsdql :
		GCCBuiltin<"__builtin_ia32_vpmacsdql">,
		Intrinsic<[llvm_v2i64_ty],
		[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v2i64_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpmacssdd :
		GCCBuiltin<"__builtin_ia32_vpmacssdd">,
		Intrinsic<[llvm_v4i32_ty],
		[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpmacssdqh :
		GCCBuiltin<"__builtin_ia32_vpmacssdqh">,
		Intrinsic<[llvm_v2i64_ty],
		[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v2i64_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpmacssdql :
		GCCBuiltin<"__builtin_ia32_vpmacssdql">,
		Intrinsic<[llvm_v2i64_ty],
		[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v2i64_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpmacsswd :
		GCCBuiltin<"__builtin_ia32_vpmacsswd">,
		Intrinsic<[llvm_v4i32_ty],
		[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v4i32_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpmacssww :
		GCCBuiltin<"__builtin_ia32_vpmacssww">,
		Intrinsic<[llvm_v8i16_ty],
		[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpmacswd :
		GCCBuiltin<"__builtin_ia32_vpmacswd">,
		Intrinsic<[llvm_v4i32_ty],
		[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v4i32_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpmacsww :
		GCCBuiltin<"__builtin_ia32_vpmacsww">,
		Intrinsic<[llvm_v8i16_ty],
		[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpmadcsswd :
		GCCBuiltin<"__builtin_ia32_vpmadcsswd">,
		Intrinsic<[llvm_v4i32_ty],
		[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v4i32_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpmadcswd :
		GCCBuiltin<"__builtin_ia32_vpmadcswd">,
		Intrinsic<[llvm_v4i32_ty],
		[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v4i32_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpperm :
		GCCBuiltin<"__builtin_ia32_vpperm">,
		Intrinsic<[llvm_v16i8_ty],
		[llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty],
		[IntrNoMem]>;
		def int_x86_xop_vprotb :
		GCCBuiltin<"__builtin_ia32_vprotb">,
		Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty],
		[IntrNoMem]>;
		def int_x86_xop_vprotd :
		GCCBuiltin<"__builtin_ia32_vprotd">,
		Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
		[IntrNoMem]>;
		def int_x86_xop_vprotq :
		GCCBuiltin<"__builtin_ia32_vprotq">,
		Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
		[IntrNoMem]>;
		def int_x86_xop_vprotw :
		GCCBuiltin<"__builtin_ia32_vprotw">,
		Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpshab :
		GCCBuiltin<"__builtin_ia32_vpshab">,
		Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpshad :
		GCCBuiltin<"__builtin_ia32_vpshad">,
		Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpshaq :
		GCCBuiltin<"__builtin_ia32_vpshaq">,
		Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpshaw :
		GCCBuiltin<"__builtin_ia32_vpshaw">,
		Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpshlb :
		GCCBuiltin<"__builtin_ia32_vpshlb">,
		Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpshld :
		GCCBuiltin<"__builtin_ia32_vpshld">,
		Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpshlq :
		GCCBuiltin<"__builtin_ia32_vpshlq">,
		Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
		[IntrNoMem]>;
		def int_x86_xop_vpshlw :
		GCCBuiltin<"__builtin_ia32_vpshlw">,
		Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty],
		[IntrNoMem]>;

		//===----------------------------------------------------------------------
		===//
	// MMX	// MMX

	// Empty MMX state op.	// Empty MMX state op.
	let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".	let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
	def int_x86_mmx_emms : GCCBuiltin<"__builtin_ia32_emms">,	def int_x86_mmx_emms : GCCBuiltin<"__builtin_ia32_emms">,
	Intrinsic<[], [], []>;	Intrinsic<[], [], []>;
	def int_x86_mmx_femms : GCCBuiltin<"__builtin_ia32_femms">,	def int_x86_mmx_femms : GCCBuiltin<"__builtin_ia32_femms">,
	Intrinsic<[], [], []>;	Intrinsic<[], [], []>;
	}	}


	skipping to change at line 1589	skipping to change at line 2575
	[IntrNoMem]>;	[IntrNoMem]>;
	def int_x86_mmx_punpckldq : GCCBuiltin<"__builtin_ia32_punpckldq">,	def int_x86_mmx_punpckldq : GCCBuiltin<"__builtin_ia32_punpckldq">,
	Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty, llvm_x86mmx_ty],	Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty, llvm_x86mmx_ty],
	[IntrNoMem]>;	[IntrNoMem]>;
	}	}

	// Integer comparison ops	// Integer comparison ops
	let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".	let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
	def int_x86_mmx_pcmpeq_b : GCCBuiltin<"__builtin_ia32_pcmpeqb">,	def int_x86_mmx_pcmpeq_b : GCCBuiltin<"__builtin_ia32_pcmpeqb">,
	Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,	Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,

	llvm_x86mmx_ty], [IntrNoMem]>;	llvm_x86mmx_ty], [IntrNoMem, Commutative]>;
	def int_x86_mmx_pcmpeq_w : GCCBuiltin<"__builtin_ia32_pcmpeqw">,	def int_x86_mmx_pcmpeq_w : GCCBuiltin<"__builtin_ia32_pcmpeqw">,
	Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,	Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,

	llvm_x86mmx_ty], [IntrNoMem]>;	llvm_x86mmx_ty], [IntrNoMem, Commutative]>;
	def int_x86_mmx_pcmpeq_d : GCCBuiltin<"__builtin_ia32_pcmpeqd">,	def int_x86_mmx_pcmpeq_d : GCCBuiltin<"__builtin_ia32_pcmpeqd">,
	Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,	Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,

	llvm_x86mmx_ty], [IntrNoMem]>;	llvm_x86mmx_ty], [IntrNoMem, Commutative]>;

	def int_x86_mmx_pcmpgt_b : GCCBuiltin<"__builtin_ia32_pcmpgtb">,	def int_x86_mmx_pcmpgt_b : GCCBuiltin<"__builtin_ia32_pcmpgtb">,
	Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,	Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,
	llvm_x86mmx_ty], [IntrNoMem]>;	llvm_x86mmx_ty], [IntrNoMem]>;
	def int_x86_mmx_pcmpgt_w : GCCBuiltin<"__builtin_ia32_pcmpgtw">,	def int_x86_mmx_pcmpgt_w : GCCBuiltin<"__builtin_ia32_pcmpgtw">,
	Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,	Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,
	llvm_x86mmx_ty], [IntrNoMem]>;	llvm_x86mmx_ty], [IntrNoMem]>;
	def int_x86_mmx_pcmpgt_d : GCCBuiltin<"__builtin_ia32_pcmpgtd">,	def int_x86_mmx_pcmpgt_d : GCCBuiltin<"__builtin_ia32_pcmpgtd">,
	Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,	Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,
	llvm_x86mmx_ty], [IntrNoMem]>;	llvm_x86mmx_ty], [IntrNoMem]>;

	skipping to change at line 1631	skipping to change at line 2617
	llvm_x86mmx_ty, llvm_i8_ty], [IntrNoMem]>;	llvm_x86mmx_ty, llvm_i8_ty], [IntrNoMem]>;

	def int_x86_mmx_pextr_w : GCCBuiltin<"__builtin_ia32_vec_ext_v4hi">,	def int_x86_mmx_pextr_w : GCCBuiltin<"__builtin_ia32_vec_ext_v4hi">,
	Intrinsic<[llvm_i32_ty], [llvm_x86mmx_ty, llvm_i32_ty],	Intrinsic<[llvm_i32_ty], [llvm_x86mmx_ty, llvm_i32_ty],
	[IntrNoMem]>;	[IntrNoMem]>;

	def int_x86_mmx_pinsr_w : GCCBuiltin<"__builtin_ia32_vec_set_v4hi">,	def int_x86_mmx_pinsr_w : GCCBuiltin<"__builtin_ia32_vec_set_v4hi">,
	Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,	Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,
	llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;	llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
	}	}


		//===----------------------------------------------------------------------
		===//
		// BMI

		let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
		def int_x86_bmi_bextr_32 : GCCBuiltin<"__builtin_ia32_bextr_u32">,
		Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoM
		em]>;
		def int_x86_bmi_bextr_64 : GCCBuiltin<"__builtin_ia32_bextr_u64">,
		Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty], [IntrNoM
		em]>;
		def int_x86_bmi_bzhi_32 : GCCBuiltin<"__builtin_ia32_bzhi_si">,
		Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoM
		em]>;
		def int_x86_bmi_bzhi_64 : GCCBuiltin<"__builtin_ia32_bzhi_di">,
		Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty], [IntrNoM
		em]>;
		def int_x86_bmi_pdep_32 : GCCBuiltin<"__builtin_ia32_pdep_si">,
		Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoM
		em]>;
		def int_x86_bmi_pdep_64 : GCCBuiltin<"__builtin_ia32_pdep_di">,
		Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty], [IntrNoM
		em]>;
		def int_x86_bmi_pext_32 : GCCBuiltin<"__builtin_ia32_pext_si">,
		Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoM
		em]>;
		def int_x86_bmi_pext_64 : GCCBuiltin<"__builtin_ia32_pext_di">,
		Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty], [IntrNoM
		em]>;
		}

		//===----------------------------------------------------------------------
		===//
		// FS/GS Base

		let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
		def int_x86_rdfsbase_32 : GCCBuiltin<"__builtin_ia32_rdfsbase32">,
		Intrinsic<[llvm_i32_ty], []>;
		def int_x86_rdgsbase_32 : GCCBuiltin<"__builtin_ia32_rdgsbase32">,
		Intrinsic<[llvm_i32_ty], []>;
		def int_x86_rdfsbase_64 : GCCBuiltin<"__builtin_ia32_rdfsbase64">,
		Intrinsic<[llvm_i64_ty], []>;
		def int_x86_rdgsbase_64 : GCCBuiltin<"__builtin_ia32_rdgsbase64">,
		Intrinsic<[llvm_i64_ty], []>;
		def int_x86_wrfsbase_32 : GCCBuiltin<"__builtin_ia32_wrfsbase32">,
		Intrinsic<[], [llvm_i32_ty]>;
		def int_x86_wrgsbase_32 : GCCBuiltin<"__builtin_ia32_wrgsbase32">,
		Intrinsic<[], [llvm_i32_ty]>;
		def int_x86_wrfsbase_64 : GCCBuiltin<"__builtin_ia32_wrfsbase64">,
		Intrinsic<[], [llvm_i64_ty]>;
		def int_x86_wrgsbase_64 : GCCBuiltin<"__builtin_ia32_wrgsbase64">,
		Intrinsic<[], [llvm_i64_ty]>;
		}

		//===----------------------------------------------------------------------
		===//
		// Half float conversion

		let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
		def int_x86_vcvtph2ps_128 : GCCBuiltin<"__builtin_ia32_vcvtph2ps">,
		Intrinsic<[llvm_v4f32_ty], [llvm_v8i16_ty], [IntrNoMem]>;
		def int_x86_vcvtph2ps_256 : GCCBuiltin<"__builtin_ia32_vcvtph2ps256">,
		Intrinsic<[llvm_v8f32_ty], [llvm_v8i16_ty], [IntrNoMem]>;
		def int_x86_vcvtps2ph_128 : GCCBuiltin<"__builtin_ia32_vcvtps2ph">,
		Intrinsic<[llvm_v8i16_ty], [llvm_v4f32_ty, llvm_i32_ty],
		[IntrNoMem]>;
		def int_x86_vcvtps2ph_256 : GCCBuiltin<"__builtin_ia32_vcvtps2ph256">,
		Intrinsic<[llvm_v8i16_ty], [llvm_v8f32_ty, llvm_i32_ty],
		[IntrNoMem]>;
		}

End of changes. 21 change blocks.
	67 lines changed or deleted	1072 lines changed or added

	IntrusiveRefCntPtr.h	IntrusiveRefCntPtr.h

	skipping to change at line 49	skipping to change at line 49
	/// Objects that subclass RefCountedBase should not be allocated on	/// Objects that subclass RefCountedBase should not be allocated on
	/// the stack, as invoking "delete" (which is called when the	/// the stack, as invoking "delete" (which is called when the
	/// reference count hits 0) on such objects is an error.	/// reference count hits 0) on such objects is an error.
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	template <class Derived>	template <class Derived>
	class RefCountedBase {	class RefCountedBase {
	mutable unsigned ref_cnt;	mutable unsigned ref_cnt;

	public:	public:
	RefCountedBase() : ref_cnt(0) {}	RefCountedBase() : ref_cnt(0) {}

		RefCountedBase(const RefCountedBase &) : ref_cnt(0) {}

	void Retain() const { ++ref_cnt; }	void Retain() const { ++ref_cnt; }
	void Release() const {	void Release() const {
	assert (ref_cnt > 0 && "Reference count is already zero.");	assert (ref_cnt > 0 && "Reference count is already zero.");
	if (--ref_cnt == 0) delete static_cast<const Derived*>(this);	if (--ref_cnt == 0) delete static_cast<const Derived*>(this);
	}	}
	};	};

	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	/// RefCountedBaseVPTR - A class that has the same function as	/// RefCountedBaseVPTR - A class that has the same function as
	/// RefCountedBase, but with a virtual destructor. Should be used	/// RefCountedBase, but with a virtual destructor. Should be used
	/// instead of RefCountedBase for classes that already have virtual	/// instead of RefCountedBase for classes that already have virtual
	/// methods to enforce dynamic allocation via 'new'. Classes that	/// methods to enforce dynamic allocation via 'new'. Classes that
	/// inherit from RefCountedBaseVPTR can't be allocated on stack -	/// inherit from RefCountedBaseVPTR can't be allocated on stack -
	/// attempting to do this will produce a compile error.	/// attempting to do this will produce a compile error.
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	class RefCountedBaseVPTR {	class RefCountedBaseVPTR {
	mutable unsigned ref_cnt;	mutable unsigned ref_cnt;

		virtual void anchor();

	protected:	protected:
	RefCountedBaseVPTR() : ref_cnt(0) {}	RefCountedBaseVPTR() : ref_cnt(0) {}

		RefCountedBaseVPTR(const RefCountedBaseVPTR &) : ref_cnt(0) {}

	virtual ~RefCountedBaseVPTR() {}	virtual ~RefCountedBaseVPTR() {}

	void Retain() const { ++ref_cnt; }	void Retain() const { ++ref_cnt; }
	void Release() const {	void Release() const {
	assert (ref_cnt > 0 && "Reference count is already zero.");	assert (ref_cnt > 0 && "Reference count is already zero.");
	if (--ref_cnt == 0) delete this;	if (--ref_cnt == 0) delete this;
	}	}

	template <typename T>	template <typename T>

	friend class IntrusiveRefCntPtr;	friend struct IntrusiveRefCntPtrInfo;
		};

		template <typename T> struct IntrusiveRefCntPtrInfo {
		static void retain(T *obj) { obj->Retain(); }
		static void release(T *obj) { obj->Release(); }
	};	};

	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	/// IntrusiveRefCntPtr - A template class that implements a "smart pointer"	/// IntrusiveRefCntPtr - A template class that implements a "smart pointer"
	/// that assumes the wrapped object has a reference count associated	/// that assumes the wrapped object has a reference count associated
	/// with it that can be managed via calls to	/// with it that can be managed via calls to
	/// IntrusivePtrAddRef/IntrusivePtrRelease. The smart pointers	/// IntrusivePtrAddRef/IntrusivePtrRelease. The smart pointers
	/// manage reference counts via the RAII idiom: upon creation of	/// manage reference counts via the RAII idiom: upon creation of
	/// smart pointer the reference count of the wrapped object is	/// smart pointer the reference count of the wrapped object is
	/// incremented and upon destruction of the smart pointer the	/// incremented and upon destruction of the smart pointer the

	skipping to change at line 108	skipping to change at line 117
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	template <typename T>	template <typename T>
	class IntrusiveRefCntPtr {	class IntrusiveRefCntPtr {
	T* Obj;	T* Obj;
	typedef IntrusiveRefCntPtr this_type;	typedef IntrusiveRefCntPtr this_type;
	public:	public:
	typedef T element_type;	typedef T element_type;

	explicit IntrusiveRefCntPtr() : Obj(0) {}	explicit IntrusiveRefCntPtr() : Obj(0) {}


	explicit IntrusiveRefCntPtr(T* obj) : Obj(obj) {	IntrusiveRefCntPtr(T* obj) : Obj(obj) {
	retain();	retain();
	}	}

	IntrusiveRefCntPtr(const IntrusiveRefCntPtr& S) : Obj(S.Obj) {	IntrusiveRefCntPtr(const IntrusiveRefCntPtr& S) : Obj(S.Obj) {
	retain();	retain();
	}	}

	template <class X>	template <class X>
	IntrusiveRefCntPtr(const IntrusiveRefCntPtr<X>& S)	IntrusiveRefCntPtr(const IntrusiveRefCntPtr<X>& S)
	: Obj(S.getPtr()) {	: Obj(S.getPtr()) {

	skipping to change at line 157	skipping to change at line 166
	operator unspecified_bool_type() const {	operator unspecified_bool_type() const {
	return Obj == 0 ? 0 : &IntrusiveRefCntPtr::getPtr;	return Obj == 0 ? 0 : &IntrusiveRefCntPtr::getPtr;
	}	}

	void swap(IntrusiveRefCntPtr& other) {	void swap(IntrusiveRefCntPtr& other) {
	T* tmp = other.Obj;	T* tmp = other.Obj;
	other.Obj = Obj;	other.Obj = Obj;
	Obj = tmp;	Obj = tmp;
	}	}


		void reset() {
		release();
		Obj = 0;
		}

	void resetWithoutRelease() {	void resetWithoutRelease() {
	Obj = 0;	Obj = 0;
	}	}

	private:	private:

	void retain() { if (Obj) Obj->Retain(); }	void retain() { if (Obj) IntrusiveRefCntPtrInfo<T>::retain(Obj); }
	void release() { if (Obj) Obj->Release(); }	void release() { if (Obj) IntrusiveRefCntPtrInfo<T>::release(Obj); }

	void replace(T* S) {	void replace(T* S) {
	this_type(S).swap(*this);	this_type(S).swap(*this);
	}	}
	};	};

	template<class T, class U>	template<class T, class U>
	inline bool operator==(const IntrusiveRefCntPtr<T>& A,	inline bool operator==(const IntrusiveRefCntPtr<T>& A,
	const IntrusiveRefCntPtr<U>& B)	const IntrusiveRefCntPtr<U>& B)
	{	{

End of changes. 7 change blocks.
	4 lines changed or deleted	18 lines changed or added

	JITEventListener.h	JITEventListener.h

	skipping to change at line 18	skipping to change at line 18
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	//	//
	// This file defines the JITEventListener interface, which lets users get	// This file defines the JITEventListener interface, which lets users get
	// callbacks when significant events happen during the JIT compilation proc ess.	// callbacks when significant events happen during the JIT compilation proc ess.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_EXECUTION_ENGINE_JIT_EVENTLISTENER_H	#ifndef LLVM_EXECUTION_ENGINE_JIT_EVENTLISTENER_H
	#define LLVM_EXECUTION_ENGINE_JIT_EVENTLISTENER_H	#define LLVM_EXECUTION_ENGINE_JIT_EVENTLISTENER_H


		#include "llvm/Config/config.h"
	#include "llvm/Support/DataTypes.h"	#include "llvm/Support/DataTypes.h"
	#include "llvm/Support/DebugLoc.h"	#include "llvm/Support/DebugLoc.h"

	#include <vector>	#include <vector>

	namespace llvm {	namespace llvm {
	class Function;	class Function;
	class MachineFunction;	class MachineFunction;

		class OProfileWrapper;
		class IntelJITEventsWrapper;

	/// JITEvent_EmittedFunctionDetails - Helper struct for containing informat ion	/// JITEvent_EmittedFunctionDetails - Helper struct for containing informat ion
	/// about a generated machine code function.	/// about a generated machine code function.
	struct JITEvent_EmittedFunctionDetails {	struct JITEvent_EmittedFunctionDetails {
	struct LineStart {	struct LineStart {
	/// The address at which the current line changes.	/// The address at which the current line changes.
	uintptr_t Address;	uintptr_t Address;

	/// The new location information. These can be translated to DebugLocT uples	/// The new location information. These can be translated to DebugLocT uples
	/// using MF->getDebugLocTuple().	/// using MF->getDebugLocTuple().

	skipping to change at line 62	skipping to change at line 65
	public:	public:
	typedef JITEvent_EmittedFunctionDetails EmittedFunctionDetails;	typedef JITEvent_EmittedFunctionDetails EmittedFunctionDetails;

	public:	public:
	JITEventListener() {}	JITEventListener() {}
	virtual ~JITEventListener();	virtual ~JITEventListener();

	/// NotifyFunctionEmitted - Called after a function has been successfully	/// NotifyFunctionEmitted - Called after a function has been successfully
	/// emitted to memory. The function still has its MachineFunction attach ed,	/// emitted to memory. The function still has its MachineFunction attach ed,
	/// if you should happen to need that.	/// if you should happen to need that.

	virtual void NotifyFunctionEmitted(const Function &F,	virtual void NotifyFunctionEmitted(const Function &,
	void *Code, size_t Size,	void *, size_t,
	const EmittedFunctionDetails &Details)	const EmittedFunctionDetails &) {}
	{}

	/// NotifyFreeingMachineCode - Called from freeMachineCodeForFunction(), after	/// NotifyFreeingMachineCode - Called from freeMachineCodeForFunction(), after
	/// the global mapping is removed, but before the machine code is returne d to	/// the global mapping is removed, but before the machine code is returne d to
	/// the allocator.	/// the allocator.
	///	///
	/// OldPtr is the address of the machine code and will be the same as the Code	/// OldPtr is the address of the machine code and will be the same as the Code
	/// parameter to a previous NotifyFunctionEmitted call. The Function pas sed	/// parameter to a previous NotifyFunctionEmitted call. The Function pas sed
	/// to NotifyFunctionEmitted may have been destroyed by the time of the	/// to NotifyFunctionEmitted may have been destroyed by the time of the
	/// matching NotifyFreeingMachineCode call.	/// matching NotifyFreeingMachineCode call.

	virtual void NotifyFreeingMachineCode(void *OldPtr) {}	virtual void NotifyFreeingMachineCode(void *) {}
	};
		#if LLVM_USE_INTEL_JITEVENTS
		// Construct an IntelJITEventListener
		static JITEventListener *createIntelJITEventListener();

		// Construct an IntelJITEventListener with a test Intel JIT API implement
		ation
		static JITEventListener *createIntelJITEventListener(
		IntelJITEventsWrapper* AlternativeImp
		l);
		#else
		static JITEventListener *createIntelJITEventListener() { return 0; }

		static JITEventListener *createIntelJITEventListener(
		IntelJITEventsWrapper* AlternativeImp
		l) {
		return 0;
		}
		#endif // USE_INTEL_JITEVENTS

		#if LLVM_USE_OPROFILE
		// Construct an OProfileJITEventListener
		static JITEventListener *createOProfileJITEventListener();

		// Construct an OProfileJITEventListener with a test opagent implementati
		on
		static JITEventListener *createOProfileJITEventListener(
		OProfileWrapper* AlternativeImpl);
		#else

		static JITEventListener *createOProfileJITEventListener() { return 0; }

		static JITEventListener *createOProfileJITEventListener(
		OProfileWrapper* AlternativeImpl) {
		return 0;
		}
		#endif // USE_OPROFILE


	// This returns NULL if support isn't available.	};
	JITEventListener *createOProfileJITEventListener();

	} // end namespace llvm.	} // end namespace llvm.


	#endif	#endif // defined LLVM_EXECUTION_ENGINE_JIT_EVENTLISTENER_H

End of changes. 6 change blocks.
	8 lines changed or deleted	45 lines changed or added

	JITMemoryManager.h	JITMemoryManager.h

	skipping to change at line 50	skipping to change at line 50

	/// setMemoryExecutable - When code generation is done and we're ready to	/// setMemoryExecutable - When code generation is done and we're ready to
	/// start execution, the code pages may need permissions changed.	/// start execution, the code pages may need permissions changed.
	virtual void setMemoryExecutable() = 0;	virtual void setMemoryExecutable() = 0;

	/// setPoisonMemory - Setting this flag to true makes the memory manager	/// setPoisonMemory - Setting this flag to true makes the memory manager
	/// garbage values over freed memory. This is useful for testing and	/// garbage values over freed memory. This is useful for testing and
	/// debugging, and may be turned on by default in debug mode.	/// debugging, and may be turned on by default in debug mode.
	virtual void setPoisonMemory(bool poison) = 0;	virtual void setPoisonMemory(bool poison) = 0;


		/// getPointerToNamedFunction - This method returns the address of the
		/// specified function. As such it is only useful for resolving library
		/// symbols, not code generated symbols.
		///
		/// If AbortOnFailure is false and no function with the given name is
		/// found, this function silently returns a null pointer. Otherwise,
		/// it prints a message to stderr and aborts.
		///
		virtual void *getPointerToNamedFunction(const std::string &Name,
		bool AbortOnFailure = true) = 0;

	//===-------------------------------------------------------------------- ===//	//===-------------------------------------------------------------------- ===//
	// Global Offset Table Management	// Global Offset Table Management
	//===-------------------------------------------------------------------- ===//	//===-------------------------------------------------------------------- ===//

	/// AllocateGOT - If the current table requires a Global Offset Table, th is	/// AllocateGOT - If the current table requires a Global Offset Table, th is
	/// method is invoked to allocate it. This method is required to set Has GOT	/// method is invoked to allocate it. This method is required to set Has GOT
	/// to true.	/// to true.
	virtual void AllocateGOT() = 0;	virtual void AllocateGOT() = 0;

	/// isManagingGOT - Return true if the AllocateGOT method is called.	/// isManagingGOT - Return true if the AllocateGOT method is called.

	skipping to change at line 104	skipping to change at line 115

	/// endFunctionBody - This method is called when the JIT is done codegen' ing	/// endFunctionBody - This method is called when the JIT is done codegen' ing
	/// the specified function. At this point we know the size of the JIT	/// the specified function. At this point we know the size of the JIT
	/// compiled function. This passes in FunctionStart (which was returned by	/// compiled function. This passes in FunctionStart (which was returned by
	/// the startFunctionBody method) and FunctionEnd which is a pointer to t he	/// the startFunctionBody method) and FunctionEnd which is a pointer to t he
	/// actual end of the function. This method should mark the space alloca ted	/// actual end of the function. This method should mark the space alloca ted
	/// and remember where it is in case the client wants to deallocate it.	/// and remember where it is in case the client wants to deallocate it.
	virtual void endFunctionBody(const Function F, uint8_t FunctionStart,	virtual void endFunctionBody(const Function F, uint8_t FunctionStart,
	uint8_t *FunctionEnd) = 0;	uint8_t *FunctionEnd) = 0;


		/// allocateCodeSection - Allocate a memory block of (at least) the given
		/// size suitable for executable code. The SectionID is a unique identifi
		er
		/// assigned by the JIT and passed through to the memory manager for
		/// the instance class to use if it needs to communicate to the JIT about
		/// a given section after the fact.
		virtual uint8_t *allocateCodeSection(uintptr_t Size, unsigned Alignment,
		unsigned SectionID) = 0;

		/// allocateDataSection - Allocate a memory block of (at least) the given
		/// size suitable for data. The SectionID is a unique identifier
		/// assigned by the JIT and passed through to the memory manager for
		/// the instance class to use if it needs to communicate to the JIT about
		/// a given section after the fact.
		virtual uint8_t *allocateDataSection(uintptr_t Size, unsigned Alignment,
		unsigned SectionID) = 0;

	/// allocateSpace - Allocate a memory block of the given size. This meth od	/// allocateSpace - Allocate a memory block of the given size. This meth od
	/// cannot be called between calls to startFunctionBody and endFunctionBo dy.	/// cannot be called between calls to startFunctionBody and endFunctionBo dy.
	virtual uint8_t *allocateSpace(intptr_t Size, unsigned Alignment) = 0;	virtual uint8_t *allocateSpace(intptr_t Size, unsigned Alignment) = 0;

	/// allocateGlobal - Allocate memory for a global.	/// allocateGlobal - Allocate memory for a global.
	virtual uint8_t *allocateGlobal(uintptr_t Size, unsigned Alignment) = 0;	virtual uint8_t *allocateGlobal(uintptr_t Size, unsigned Alignment) = 0;

	/// deallocateFunctionBody - Free the specified function body. The argum ent	/// deallocateFunctionBody - Free the specified function body. The argum ent
	/// must be the return value from a call to startFunctionBody() that hasn 't	/// must be the return value from a call to startFunctionBody() that hasn 't
	/// been deallocated yet. This is never called when the JIT is currently	/// been deallocated yet. This is never called when the JIT is currently

End of changes. 2 change blocks.
	0 lines changed or deleted	28 lines changed or added

	LLVMBitCodes.h	LLVMBitCodes.h

	skipping to change at line 33	skipping to change at line 33
	namespace llvm {	namespace llvm {
	namespace bitc {	namespace bitc {
	// The only top-level block type defined is for a module.	// The only top-level block type defined is for a module.
	enum BlockIDs {	enum BlockIDs {
	// Blocks	// Blocks
	MODULE_BLOCK_ID = FIRST_APPLICATION_BLOCKID,	MODULE_BLOCK_ID = FIRST_APPLICATION_BLOCKID,

	// Module sub-block id's.	// Module sub-block id's.
	PARAMATTR_BLOCK_ID,	PARAMATTR_BLOCK_ID,


	/// TYPE_BLOCK_ID_OLD - This is the type descriptor block in LLVM 2.9 a	UNUSED_ID1,
	nd
	/// earlier, replaced with TYPE_BLOCK_ID2. FIXME: Remove in LLVM 3.1.
	TYPE_BLOCK_ID_OLD,

	CONSTANTS_BLOCK_ID,	CONSTANTS_BLOCK_ID,
	FUNCTION_BLOCK_ID,	FUNCTION_BLOCK_ID,


	/// TYPE_SYMTAB_BLOCK_ID_OLD - This type descriptor is from LLVM 2.9 an	UNUSED_ID2,
	d
	/// earlier bitcode files. FIXME: Remove in LLVM 3.1
	TYPE_SYMTAB_BLOCK_ID_OLD,

	VALUE_SYMTAB_BLOCK_ID,	VALUE_SYMTAB_BLOCK_ID,
	METADATA_BLOCK_ID,	METADATA_BLOCK_ID,
	METADATA_ATTACHMENT_ID,	METADATA_ATTACHMENT_ID,


	TYPE_BLOCK_ID_NEW	TYPE_BLOCK_ID_NEW,

		USELIST_BLOCK_ID
	};	};

	/// MODULE blocks have a number of optional fields and subblocks.	/// MODULE blocks have a number of optional fields and subblocks.
	enum ModuleCodes {	enum ModuleCodes {
	MODULE_CODE_VERSION = 1, // VERSION: [version#]	MODULE_CODE_VERSION = 1, // VERSION: [version#]
	MODULE_CODE_TRIPLE = 2, // TRIPLE: [strchr x N]	MODULE_CODE_TRIPLE = 2, // TRIPLE: [strchr x N]
	MODULE_CODE_DATALAYOUT = 3, // DATALAYOUT: [strchr x N]	MODULE_CODE_DATALAYOUT = 3, // DATALAYOUT: [strchr x N]
	MODULE_CODE_ASM = 4, // ASM: [strchr x N]	MODULE_CODE_ASM = 4, // ASM: [strchr x N]
	MODULE_CODE_SECTIONNAME = 5, // SECTIONNAME: [strchr x N]	MODULE_CODE_SECTIONNAME = 5, // SECTIONNAME: [strchr x N]
	MODULE_CODE_DEPLIB = 6, // DEPLIB: [strchr x N]	MODULE_CODE_DEPLIB = 6, // DEPLIB: [strchr x N]

	// GLOBALVAR: [pointer type, isconst, initid,	// GLOBALVAR: [pointer type, isconst, initid,
	// linkage, alignment, section, visibility, threadlocal]	// linkage, alignment, section, visibility, threadlocal]
	MODULE_CODE_GLOBALVAR = 7,	MODULE_CODE_GLOBALVAR = 7,

	// FUNCTION: [type, callingconv, isproto, linkage, paramattrs, alignme nt,	// FUNCTION: [type, callingconv, isproto, linkage, paramattrs, alignme nt,

	// section, visibility]	// section, visibility, gc, unnamed_addr]
	MODULE_CODE_FUNCTION = 8,	MODULE_CODE_FUNCTION = 8,


	// ALIAS: [alias type, aliasee val#, linkage]	// ALIAS: [alias type, aliasee val#, linkage, visibility]
	MODULE_CODE_ALIAS = 9,	MODULE_CODE_ALIAS = 9,

	/// MODULE_CODE_PURGEVALS: [numvals]	/// MODULE_CODE_PURGEVALS: [numvals]
	MODULE_CODE_PURGEVALS = 10,	MODULE_CODE_PURGEVALS = 10,

	MODULE_CODE_GCNAME = 11 // GCNAME: [strchr x N]	MODULE_CODE_GCNAME = 11 // GCNAME: [strchr x N]
	};	};

	/// PARAMATTR blocks have code for defining a parameter attribute set.	/// PARAMATTR blocks have code for defining a parameter attribute set.
	enum AttributeCodes {	enum AttributeCodes {

	skipping to change at line 94	skipping to change at line 92
	TYPE_CODE_NUMENTRY = 1, // NUMENTRY: [numentries]	TYPE_CODE_NUMENTRY = 1, // NUMENTRY: [numentries]

	// Type Codes	// Type Codes
	TYPE_CODE_VOID = 2, // VOID	TYPE_CODE_VOID = 2, // VOID
	TYPE_CODE_FLOAT = 3, // FLOAT	TYPE_CODE_FLOAT = 3, // FLOAT
	TYPE_CODE_DOUBLE = 4, // DOUBLE	TYPE_CODE_DOUBLE = 4, // DOUBLE
	TYPE_CODE_LABEL = 5, // LABEL	TYPE_CODE_LABEL = 5, // LABEL
	TYPE_CODE_OPAQUE = 6, // OPAQUE	TYPE_CODE_OPAQUE = 6, // OPAQUE
	TYPE_CODE_INTEGER = 7, // INTEGER: [width]	TYPE_CODE_INTEGER = 7, // INTEGER: [width]
	TYPE_CODE_POINTER = 8, // POINTER: [pointee type]	TYPE_CODE_POINTER = 8, // POINTER: [pointee type]

	TYPE_CODE_FUNCTION = 9, // FUNCTION: [vararg, retty, paramty x N]


	// FIXME: This is the encoding used for structs in LLVM 2.9 and earlier	TYPE_CODE_FUNCTION_OLD = 9, // FUNCTION: [vararg, attrid, retty,
	.	// paramty x N]
	// REMOVE this in LLVM 3.1
	TYPE_CODE_STRUCT_OLD = 10, // STRUCT: [ispacked, eltty x N]	TYPE_CODE_HALF = 10, // HALF

	TYPE_CODE_ARRAY = 11, // ARRAY: [numelts, eltty]	TYPE_CODE_ARRAY = 11, // ARRAY: [numelts, eltty]
	TYPE_CODE_VECTOR = 12, // VECTOR: [numelts, eltty]	TYPE_CODE_VECTOR = 12, // VECTOR: [numelts, eltty]

	// These are not with the other floating point types because they're	// These are not with the other floating point types because they're
	// a late addition, and putting them in the right place breaks	// a late addition, and putting them in the right place breaks
	// binary compatibility.	// binary compatibility.
	TYPE_CODE_X86_FP80 = 13, // X86 LONG DOUBLE	TYPE_CODE_X86_FP80 = 13, // X86 LONG DOUBLE
	TYPE_CODE_FP128 = 14, // LONG DOUBLE (112 bit mantissa)	TYPE_CODE_FP128 = 14, // LONG DOUBLE (112 bit mantissa)
	TYPE_CODE_PPC_FP128= 15, // PPC LONG DOUBLE (2 doubles)	TYPE_CODE_PPC_FP128= 15, // PPC LONG DOUBLE (2 doubles)

	TYPE_CODE_METADATA = 16, // METADATA	TYPE_CODE_METADATA = 16, // METADATA

	TYPE_CODE_X86_MMX = 17, // X86 MMX	TYPE_CODE_X86_MMX = 17, // X86 MMX

	TYPE_CODE_STRUCT_ANON = 18, // STRUCT_ANON: [ispacked, eltty x N]	TYPE_CODE_STRUCT_ANON = 18, // STRUCT_ANON: [ispacked, eltty x N]
	TYPE_CODE_STRUCT_NAME = 19, // STRUCT_NAME: [strchr x N]	TYPE_CODE_STRUCT_NAME = 19, // STRUCT_NAME: [strchr x N]

	TYPE_CODE_STRUCT_NAMED = 20 // STRUCT_NAMED: [ispacked, eltty x N]	TYPE_CODE_STRUCT_NAMED = 20,// STRUCT_NAMED: [ispacked, eltty x N]

		TYPE_CODE_FUNCTION = 21 // FUNCTION: [vararg, retty, paramty x N]
	};	};

	// The type symbol table only has one code (TST_ENTRY_CODE).	// The type symbol table only has one code (TST_ENTRY_CODE).
	enum TypeSymtabCodes {	enum TypeSymtabCodes {
	TST_CODE_ENTRY = 1 // TST_ENTRY: [typeid, namechar x N]	TST_CODE_ENTRY = 1 // TST_ENTRY: [typeid, namechar x N]
	};	};

	// The value symbol table only has one code (VST_ENTRY_CODE).	// The value symbol table only has one code (VST_ENTRY_CODE).
	enum ValueSymtabCodes {	enum ValueSymtabCodes {
	VST_CODE_ENTRY = 1, // VST_ENTRY: [valid, namechar x N]	VST_CODE_ENTRY = 1, // VST_ENTRY: [valid, namechar x N]

	skipping to change at line 165	skipping to change at line 166
	CST_CODE_CE_CAST = 11, // CE_CAST: [opcode, opty, opval]	CST_CODE_CE_CAST = 11, // CE_CAST: [opcode, opty, opval]
	CST_CODE_CE_GEP = 12, // CE_GEP: [n x operands]	CST_CODE_CE_GEP = 12, // CE_GEP: [n x operands]
	CST_CODE_CE_SELECT = 13, // CE_SELECT: [opval, opval, opval]	CST_CODE_CE_SELECT = 13, // CE_SELECT: [opval, opval, opval]
	CST_CODE_CE_EXTRACTELT = 14, // CE_EXTRACTELT: [opty, opval, opval]	CST_CODE_CE_EXTRACTELT = 14, // CE_EXTRACTELT: [opty, opval, opval]
	CST_CODE_CE_INSERTELT = 15, // CE_INSERTELT: [opval, opval, opval]	CST_CODE_CE_INSERTELT = 15, // CE_INSERTELT: [opval, opval, opval]
	CST_CODE_CE_SHUFFLEVEC = 16, // CE_SHUFFLEVEC: [opval, opval, opval]	CST_CODE_CE_SHUFFLEVEC = 16, // CE_SHUFFLEVEC: [opval, opval, opval]
	CST_CODE_CE_CMP = 17, // CE_CMP: [opty, opval, opval, pr ed]	CST_CODE_CE_CMP = 17, // CE_CMP: [opty, opval, opval, pr ed]
	CST_CODE_INLINEASM = 18, // INLINEASM: [sideeffect,asmstr,cons tstr]	CST_CODE_INLINEASM = 18, // INLINEASM: [sideeffect,asmstr,cons tstr]
	CST_CODE_CE_SHUFVEC_EX = 19, // SHUFVEC_EX: [opty, opval, opval, op val]	CST_CODE_CE_SHUFVEC_EX = 19, // SHUFVEC_EX: [opty, opval, opval, op val]
	CST_CODE_CE_INBOUNDS_GEP = 20,// INBOUNDS_GEP: [n x operands]	CST_CODE_CE_INBOUNDS_GEP = 20,// INBOUNDS_GEP: [n x operands]

	CST_CODE_BLOCKADDRESS = 21 // CST_CODE_BLOCKADDRESS [fnty, fnval, bb	CST_CODE_BLOCKADDRESS = 21, // CST_CODE_BLOCKADDRESS [fnty, fnval, bb
	#]	#]
		CST_CODE_DATA = 22 // DATA: [n x elements]
	};	};

	/// CastOpcodes - These are values used in the bitcode files to encode wh ich	/// CastOpcodes - These are values used in the bitcode files to encode wh ich
	/// cast a CST_CODE_CE_CAST or a XXX refers to. The values of these enum s	/// cast a CST_CODE_CE_CAST or a XXX refers to. The values of these enum s
	/// have no fixed relation to the LLVM IR enum values. Changing these wi ll	/// have no fixed relation to the LLVM IR enum values. Changing these wi ll
	/// break compatibility with old files.	/// break compatibility with old files.
	enum CastOpcodes {	enum CastOpcodes {
	CAST_TRUNC = 0,	CAST_TRUNC = 0,
	CAST_ZEXT = 1,	CAST_ZEXT = 1,
	CAST_SEXT = 2,	CAST_SEXT = 2,

	skipping to change at line 272	skipping to change at line 274
	FUNC_CODE_INST_SELECT = 5, // SELECT: [ty, opval, opval, opva l]	FUNC_CODE_INST_SELECT = 5, // SELECT: [ty, opval, opval, opva l]
	FUNC_CODE_INST_EXTRACTELT = 6, // EXTRACTELT: [opty, opval, opval]	FUNC_CODE_INST_EXTRACTELT = 6, // EXTRACTELT: [opty, opval, opval]
	FUNC_CODE_INST_INSERTELT = 7, // INSERTELT: [ty, opval, opval, opva l]	FUNC_CODE_INST_INSERTELT = 7, // INSERTELT: [ty, opval, opval, opva l]
	FUNC_CODE_INST_SHUFFLEVEC = 8, // SHUFFLEVEC: [ty, opval, opval, opva l]	FUNC_CODE_INST_SHUFFLEVEC = 8, // SHUFFLEVEC: [ty, opval, opval, opva l]
	FUNC_CODE_INST_CMP = 9, // CMP: [opty, opval, opval, pr ed]	FUNC_CODE_INST_CMP = 9, // CMP: [opty, opval, opval, pr ed]

	FUNC_CODE_INST_RET = 10, // RET: [opty,opval<both option al>]	FUNC_CODE_INST_RET = 10, // RET: [opty,opval<both option al>]
	FUNC_CODE_INST_BR = 11, // BR: [bb#, bb#, cond] or [bb #]	FUNC_CODE_INST_BR = 11, // BR: [bb#, bb#, cond] or [bb #]
	FUNC_CODE_INST_SWITCH = 12, // SWITCH: [opty, op0, op1, ...]	FUNC_CODE_INST_SWITCH = 12, // SWITCH: [opty, op0, op1, ...]
	FUNC_CODE_INST_INVOKE = 13, // INVOKE: [attr, fnty, op0,op1, . ..]	FUNC_CODE_INST_INVOKE = 13, // INVOKE: [attr, fnty, op0,op1, . ..]

	FUNC_CODE_INST_UNWIND = 14, // UNWIND	// 14 is unused.
	FUNC_CODE_INST_UNREACHABLE = 15, // UNREACHABLE	FUNC_CODE_INST_UNREACHABLE = 15, // UNREACHABLE

	FUNC_CODE_INST_PHI = 16, // PHI: [ty, val0,bb0, ...]	FUNC_CODE_INST_PHI = 16, // PHI: [ty, val0,bb0, ...]
	// 17 is unused.	// 17 is unused.
	// 18 is unused.	// 18 is unused.
	FUNC_CODE_INST_ALLOCA = 19, // ALLOCA: [instty, op, align]	FUNC_CODE_INST_ALLOCA = 19, // ALLOCA: [instty, op, align]
	FUNC_CODE_INST_LOAD = 20, // LOAD: [opty, op, align, vol]	FUNC_CODE_INST_LOAD = 20, // LOAD: [opty, op, align, vol]
	// 21 is unused.	// 21 is unused.
	// 22 is unused.	// 22 is unused.
	FUNC_CODE_INST_VAARG = 23, // VAARG: [valistty, valist, inst ty]	FUNC_CODE_INST_VAARG = 23, // VAARG: [valistty, valist, inst ty]

	skipping to change at line 316	skipping to change at line 318
	FUNC_CODE_INST_ATOMICRMW = 38, // ATOMICRMW: [ptrty,ptr,val, operatio n,	FUNC_CODE_INST_ATOMICRMW = 38, // ATOMICRMW: [ptrty,ptr,val, operatio n,
	// align, vol,	// align, vol,
	// ordering, synchscope]	// ordering, synchscope]
	FUNC_CODE_INST_RESUME = 39, // RESUME: [opval]	FUNC_CODE_INST_RESUME = 39, // RESUME: [opval]
	FUNC_CODE_INST_LANDINGPAD = 40, // LANDINGPAD: [ty,val,val,num,id0,val 0...]	FUNC_CODE_INST_LANDINGPAD = 40, // LANDINGPAD: [ty,val,val,num,id0,val 0...]
	FUNC_CODE_INST_LOADATOMIC = 41, // LOAD: [opty, op, align, vol,	FUNC_CODE_INST_LOADATOMIC = 41, // LOAD: [opty, op, align, vol,
	// ordering, synchscope]	// ordering, synchscope]
	FUNC_CODE_INST_STOREATOMIC = 42 // STORE: [ptrty,ptr,val, align, vol	FUNC_CODE_INST_STOREATOMIC = 42 // STORE: [ptrty,ptr,val, align, vol
	// ordering, synchscope]	// ordering, synchscope]
	};	};


		enum UseListCodes {
		USELIST_CODE_ENTRY = 1 // USELIST_CODE_ENTRY: TBD.
		};
	} // End bitc namespace	} // End bitc namespace
	} // End llvm namespace	} // End llvm namespace

	#endif	#endif

End of changes. 11 change blocks.
	20 lines changed or deleted	23 lines changed or added

	LLVMContext.h	LLVMContext.h

	skipping to change at line 22	skipping to change at line 22
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_LLVMCONTEXT_H	#ifndef LLVM_LLVMCONTEXT_H
	#define LLVM_LLVMCONTEXT_H	#define LLVM_LLVMCONTEXT_H

	namespace llvm {	namespace llvm {

	class LLVMContextImpl;	class LLVMContextImpl;
	class StringRef;	class StringRef;

		class Twine;
	class Instruction;	class Instruction;
	class Module;	class Module;
	class SMDiagnostic;	class SMDiagnostic;
	template <typename T> class SmallVectorImpl;	template <typename T> class SmallVectorImpl;

	/// This is an important class for using LLVM in a threaded context. It	/// This is an important class for using LLVM in a threaded context. It
	/// (opaquely) owns and manages the core "global" data of LLVM's core	/// (opaquely) owns and manages the core "global" data of LLVM's core
	/// infrastructure, including the type and constant uniquing tables.	/// infrastructure, including the type and constant uniquing tables.
	/// LLVMContext itself provides no locking guarantees, so you should be car eful	/// LLVMContext itself provides no locking guarantees, so you should be car eful
	/// to have one context per thread.	/// to have one context per thread.

	skipping to change at line 43	skipping to change at line 44
	public:	public:
	LLVMContextImpl *const pImpl;	LLVMContextImpl *const pImpl;
	LLVMContext();	LLVMContext();
	~LLVMContext();	~LLVMContext();

	// Pinned metadata names, which always have the same value. This is a	// Pinned metadata names, which always have the same value. This is a
	// compile-time performance optimization, not a correctness optimization.	// compile-time performance optimization, not a correctness optimization.
	enum {	enum {
	MD_dbg = 0, // "dbg"	MD_dbg = 0, // "dbg"
	MD_tbaa = 1, // "tbaa"	MD_tbaa = 1, // "tbaa"

	MD_prof = 2 // "prof"	MD_prof = 2, // "prof"
		MD_fpmath = 3, // "fpmath"
		MD_range = 4 // "range"
	};	};

	/// getMDKindID - Return a unique non-zero ID for the specified metadata kind.	/// getMDKindID - Return a unique non-zero ID for the specified metadata kind.
	/// This ID is uniqued across modules in the current LLVMContext.	/// This ID is uniqued across modules in the current LLVMContext.
	unsigned getMDKindID(StringRef Name) const;	unsigned getMDKindID(StringRef Name) const;

	/// getMDKindNames - Populate client supplied SmallVector with the name f or	/// getMDKindNames - Populate client supplied SmallVector with the name f or
	/// custom metadata IDs registered in this LLVMContext.	/// custom metadata IDs registered in this LLVMContext.
	void getMDKindNames(SmallVectorImpl<StringRef> &Result) const;	void getMDKindNames(SmallVectorImpl<StringRef> &Result) const;


	skipping to change at line 80	skipping to change at line 83

	/// getInlineAsmDiagnosticContext - Return the diagnostic context set by	/// getInlineAsmDiagnosticContext - Return the diagnostic context set by
	/// setInlineAsmDiagnosticHandler.	/// setInlineAsmDiagnosticHandler.
	void *getInlineAsmDiagnosticContext() const;	void *getInlineAsmDiagnosticContext() const;

	/// emitError - Emit an error message to the currently installed error ha ndler	/// emitError - Emit an error message to the currently installed error ha ndler
	/// with optional location information. This function returns, so code s hould	/// with optional location information. This function returns, so code s hould
	/// be prepared to drop the erroneous construct on the floor and "not cra sh".	/// be prepared to drop the erroneous construct on the floor and "not cra sh".
	/// The generated code need not be correct. The error message will be	/// The generated code need not be correct. The error message will be
	/// implicitly prefixed with "error: " and should not end with a ".".	/// implicitly prefixed with "error: " and should not end with a ".".

	void emitError(unsigned LocCookie, StringRef ErrorStr);	void emitError(unsigned LocCookie, const Twine &ErrorStr);
	void emitError(const Instruction *I, StringRef ErrorStr);	void emitError(const Instruction *I, const Twine &ErrorStr);
	void emitError(StringRef ErrorStr);	void emitError(const Twine &ErrorStr);

	private:	private:
	// DO NOT IMPLEMENT	// DO NOT IMPLEMENT
	LLVMContext(LLVMContext&);	LLVMContext(LLVMContext&);
	void operator=(LLVMContext&);	void operator=(LLVMContext&);

	/// addModule - Register a module as being instantiated in this context. If	/// addModule - Register a module as being instantiated in this context. If
	/// the context is deleted, the module will be deleted as well.	/// the context is deleted, the module will be deleted as well.
	void addModule(Module*);	void addModule(Module*);


End of changes. 3 change blocks.
	4 lines changed or deleted	7 lines changed or added

	LatencyPriorityQueue.h	LatencyPriorityQueue.h

	skipping to change at line 88	skipping to change at line 88
	bool empty() const { return Queue.empty(); }	bool empty() const { return Queue.empty(); }

	virtual void push(SUnit *U);	virtual void push(SUnit *U);

	virtual SUnit *pop();	virtual SUnit *pop();

	virtual void remove(SUnit *SU);	virtual void remove(SUnit *SU);

	virtual void dump(ScheduleDAG* DAG) const;	virtual void dump(ScheduleDAG* DAG) const;


	// ScheduledNode - As nodes are scheduled, we look to see if there are any	// scheduledNode - As nodes are scheduled, we look to see if there are any
	// successor nodes that have a single unscheduled predecessor. If so, that	// successor nodes that have a single unscheduled predecessor. If so, that
	// single predecessor has a higher priority, since scheduling it will m ake	// single predecessor has a higher priority, since scheduling it will m ake
	// the node available.	// the node available.

	void ScheduledNode(SUnit *Node);	void scheduledNode(SUnit *Node);

	private:	private:
	void AdjustPriorityOfUnscheduledPreds(SUnit *SU);	void AdjustPriorityOfUnscheduledPreds(SUnit *SU);
	SUnit getSingleUnscheduledPred(SUnit SU);	SUnit getSingleUnscheduledPred(SUnit SU);
	};	};
	}	}

	#endif	#endif

End of changes. 2 change blocks.
	2 lines changed or deleted	2 lines changed or added

	LazyValueInfo.h	LazyValueInfo.h

	skipping to change at line 23	skipping to change at line 23
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_ANALYSIS_LAZYVALUEINFO_H	#ifndef LLVM_ANALYSIS_LAZYVALUEINFO_H
	#define LLVM_ANALYSIS_LAZYVALUEINFO_H	#define LLVM_ANALYSIS_LAZYVALUEINFO_H

	#include "llvm/Pass.h"	#include "llvm/Pass.h"

	namespace llvm {	namespace llvm {
	class Constant;	class Constant;
	class TargetData;	class TargetData;

		class TargetLibraryInfo;
	class Value;	class Value;

	/// LazyValueInfo - This pass computes, caches, and vends lazy value constr aint	/// LazyValueInfo - This pass computes, caches, and vends lazy value constr aint
	/// information.	/// information.
	class LazyValueInfo : public FunctionPass {	class LazyValueInfo : public FunctionPass {
	class TargetData *TD;	class TargetData *TD;

		class TargetLibraryInfo *TLI;
	void *PImpl;	void *PImpl;
	LazyValueInfo(const LazyValueInfo&); // DO NOT IMPLEMENT.	LazyValueInfo(const LazyValueInfo&); // DO NOT IMPLEMENT.
	void operator=(const LazyValueInfo&); // DO NOT IMPLEMENT.	void operator=(const LazyValueInfo&); // DO NOT IMPLEMENT.
	public:	public:
	static char ID;	static char ID;
	LazyValueInfo() : FunctionPass(ID), PImpl(0) {	LazyValueInfo() : FunctionPass(ID), PImpl(0) {
	initializeLazyValueInfoPass(*PassRegistry::getPassRegistry());	initializeLazyValueInfoPass(*PassRegistry::getPassRegistry());
	}	}
	~LazyValueInfo() { assert(PImpl == 0 && "releaseMemory not called"); }	~LazyValueInfo() { assert(PImpl == 0 && "releaseMemory not called"); }


	skipping to change at line 69	skipping to change at line 71

	/// threadEdge - Inform the analysis cache that we have threaded an edge from	/// threadEdge - Inform the analysis cache that we have threaded an edge from
	/// PredBB to OldSucc to be from PredBB to NewSucc instead.	/// PredBB to OldSucc to be from PredBB to NewSucc instead.
	void threadEdge(BasicBlock PredBB, BasicBlock OldSucc, BasicBlock *NewS ucc);	void threadEdge(BasicBlock PredBB, BasicBlock OldSucc, BasicBlock *NewS ucc);

	/// eraseBlock - Inform the analysis cache that we have erased a block.	/// eraseBlock - Inform the analysis cache that we have erased a block.
	void eraseBlock(BasicBlock *BB);	void eraseBlock(BasicBlock *BB);

	// Implementation boilerplate.	// Implementation boilerplate.


	virtual void getAnalysisUsage(AnalysisUsage &AU) const {	virtual void getAnalysisUsage(AnalysisUsage &AU) const;
	AU.setPreservesAll();
	}
	virtual void releaseMemory();	virtual void releaseMemory();
	virtual bool runOnFunction(Function &F);	virtual bool runOnFunction(Function &F);
	};	};

	} // end namespace llvm	} // end namespace llvm

	#endif	#endif

End of changes. 3 change blocks.
	3 lines changed or deleted	3 lines changed or added

	LexicalScopes.h	LexicalScopes.h

	skipping to change at line 156	skipping to change at line 156

	/// CurrentFnLexicalScope - Top level scope for the current function.	/// CurrentFnLexicalScope - Top level scope for the current function.
	///	///
	LexicalScope *CurrentFnLexicalScope;	LexicalScope *CurrentFnLexicalScope;
	};	};

	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	/// LexicalScope - This class is used to track scope information.	/// LexicalScope - This class is used to track scope information.
	///	///
	class LexicalScope {	class LexicalScope {

		virtual void anchor();

	public:	public:
	LexicalScope(LexicalScope P, const MDNode D, const MDNode *I, bool A)	LexicalScope(LexicalScope P, const MDNode D, const MDNode *I, bool A)
	: Parent(P), Desc(D), InlinedAtLocation(I), AbstractScope(A),	: Parent(P), Desc(D), InlinedAtLocation(I), AbstractScope(A),
	LastInsn(0), FirstInsn(0), DFSIn(0), DFSOut(0), IndentLevel(0) {	LastInsn(0), FirstInsn(0), DFSIn(0), DFSOut(0), IndentLevel(0) {
	if (Parent)	if (Parent)
	Parent->addChild(this);	Parent->addChild(this);
	}	}

	virtual ~LexicalScope() {}	virtual ~LexicalScope() {}

	skipping to change at line 211	skipping to change at line 212
	assert (LastInsn && "Last insn missing!");	assert (LastInsn && "Last insn missing!");
	Ranges.push_back(InsnRange(FirstInsn, LastInsn));	Ranges.push_back(InsnRange(FirstInsn, LastInsn));
	FirstInsn = NULL;	FirstInsn = NULL;
	LastInsn = NULL;	LastInsn = NULL;
	// If Parent dominates NewScope then do not close Parent's instruction	// If Parent dominates NewScope then do not close Parent's instruction
	// range.	// range.
	if (Parent && (!NewScope \|\| !Parent->dominates(NewScope)))	if (Parent && (!NewScope \|\| !Parent->dominates(NewScope)))
	Parent->closeInsnRange(NewScope);	Parent->closeInsnRange(NewScope);
	}	}


	/// dominates - Return true if current scope dominsates given lexical sco pe.	/// dominates - Return true if current scope dominates given lexical scop e.
	bool dominates(const LexicalScope *S) const {	bool dominates(const LexicalScope *S) const {
	if (S == this)	if (S == this)
	return true;	return true;
	if (DFSIn < S->getDFSIn() && DFSOut > S->getDFSOut())	if (DFSIn < S->getDFSIn() && DFSOut > S->getDFSOut())
	return true;	return true;
	return false;	return false;
	}	}

	// Depth First Search support to walk and manipulate LexicalScope hierarc hy.	// Depth First Search support to walk and manipulate LexicalScope hierarc hy.
	unsigned getDFSOut() const { return DFSOut; }	unsigned getDFSOut() const { return DFSOut; }

End of changes. 2 change blocks.
	1 lines changed or deleted	2 lines changed or added

	LinkAllCodegenComponents.h	LinkAllCodegenComponents.h

	skipping to change at line 34	skipping to change at line 34
	namespace {	namespace {
	struct ForceCodegenLinking {	struct ForceCodegenLinking {
	ForceCodegenLinking() {	ForceCodegenLinking() {
	// We must reference the passes in such a way that compilers will not	// We must reference the passes in such a way that compilers will not
	// delete it all as dead code, even with whole program optimization,	// delete it all as dead code, even with whole program optimization,
	// yet is effectively a NO-OP. As the compiler isn't smart enough	// yet is effectively a NO-OP. As the compiler isn't smart enough
	// to know that getenv() never returns -1, this will do the job.	// to know that getenv() never returns -1, this will do the job.
	if (std::getenv("bar") != (char*) -1)	if (std::getenv("bar") != (char*) -1)
	return;	return;


	(void) llvm::createDeadMachineInstructionElimPass();

	(void) llvm::createFastRegisterAllocator();	(void) llvm::createFastRegisterAllocator();
	(void) llvm::createBasicRegisterAllocator();	(void) llvm::createBasicRegisterAllocator();

	(void) llvm::createLinearScanRegisterAllocator();
	(void) llvm::createGreedyRegisterAllocator();	(void) llvm::createGreedyRegisterAllocator();
	(void) llvm::createDefaultPBQPRegisterAllocator();	(void) llvm::createDefaultPBQPRegisterAllocator();

	llvm::linkOcamlGC();	llvm::linkOcamlGC();
	llvm::linkShadowStackGC();	llvm::linkShadowStackGC();

	(void) llvm::createBURRListDAGScheduler(NULL, llvm::CodeGenOpt::Defau lt);	(void) llvm::createBURRListDAGScheduler(NULL, llvm::CodeGenOpt::Defau lt);

	(void) llvm::createTDRRListDAGScheduler(NULL, llvm::CodeGenOpt::Defau lt);
	(void) llvm::createSourceListDAGScheduler(NULL,llvm::CodeGenOpt::Defa ult);	(void) llvm::createSourceListDAGScheduler(NULL,llvm::CodeGenOpt::Defa ult);
	(void) llvm::createHybridListDAGScheduler(NULL,llvm::CodeGenOpt::Defa ult);	(void) llvm::createHybridListDAGScheduler(NULL,llvm::CodeGenOpt::Defa ult);

	(void) llvm::createTDListDAGScheduler(NULL, llvm::CodeGenOpt::Default );
	(void) llvm::createFastDAGScheduler(NULL, llvm::CodeGenOpt::Default);	(void) llvm::createFastDAGScheduler(NULL, llvm::CodeGenOpt::Default);
	(void) llvm::createDefaultScheduler(NULL, llvm::CodeGenOpt::Default);	(void) llvm::createDefaultScheduler(NULL, llvm::CodeGenOpt::Default);

		(void) llvm::createVLIWDAGScheduler(NULL, llvm::CodeGenOpt::Default);

	}	}
	} ForceCodegenLinking; // Force link by creating a global definition.	} ForceCodegenLinking; // Force link by creating a global definition.
	}	}

	#endif	#endif

End of changes. 5 change blocks.
	5 lines changed or deleted	1 lines changed or added

	LinkTimeOptimizer.h	LinkTimeOptimizer.h

	skipping to change at line 23	skipping to change at line 23
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef __LTO_CAPI_H__	#ifndef __LTO_CAPI_H__
	#define __LTO_CAPI_H__	#define __LTO_CAPI_H__

	#ifdef __cplusplus	#ifdef __cplusplus
	extern "C" {	extern "C" {
	#endif	#endif


		/**
		* @defgroup LLVMCLinkTimeOptimizer Link Time Optimization
		* @ingroup LLVMC
		*
		* @{
		*/

	/// This provides a dummy type for pointers to the LTO object.	/// This provides a dummy type for pointers to the LTO object.
	typedef void* llvm_lto_t;	typedef void* llvm_lto_t;

	/// This provides a C-visible enumerator to manage status codes.	/// This provides a C-visible enumerator to manage status codes.
	/// This should map exactly onto the C++ enumerator LTOStatus.	/// This should map exactly onto the C++ enumerator LTOStatus.
	typedef enum llvm_lto_status {	typedef enum llvm_lto_status {
	LLVM_LTO_UNKNOWN,	LLVM_LTO_UNKNOWN,
	LLVM_LTO_OPT_SUCCESS,	LLVM_LTO_OPT_SUCCESS,
	LLVM_LTO_READ_SUCCESS,	LLVM_LTO_READ_SUCCESS,
	LLVM_LTO_READ_FAILURE,	LLVM_LTO_READ_FAILURE,

	skipping to change at line 54	skipping to change at line 61
	/// linker to use dlopen() interface to dynamically load LinkTimeOptimize r.	/// linker to use dlopen() interface to dynamically load LinkTimeOptimize r.
	/// extern "C" helps, because dlopen() interface uses name to find the sy mbol.	/// extern "C" helps, because dlopen() interface uses name to find the sy mbol.
	extern llvm_lto_t llvm_create_optimizer(void);	extern llvm_lto_t llvm_create_optimizer(void);
	extern void llvm_destroy_optimizer(llvm_lto_t lto);	extern void llvm_destroy_optimizer(llvm_lto_t lto);

	extern llvm_lto_status_t llvm_read_object_file	extern llvm_lto_status_t llvm_read_object_file
	(llvm_lto_t lto, const char* input_filename);	(llvm_lto_t lto, const char* input_filename);
	extern llvm_lto_status_t llvm_optimize_modules	extern llvm_lto_status_t llvm_optimize_modules
	(llvm_lto_t lto, const char* output_filename);	(llvm_lto_t lto, const char* output_filename);


		/**
		* @}
		*/

	#ifdef __cplusplus	#ifdef __cplusplus
	}	}
	#endif	#endif

	#endif	#endif

End of changes. 2 change blocks.
	0 lines changed or deleted	11 lines changed or added

	Linker.h	Linker.h

	skipping to change at line 18	skipping to change at line 18
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	//	//
	// This file defines the interface to the module/file/archive linker.	// This file defines the interface to the module/file/archive linker.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_LINKER_H	#ifndef LLVM_LINKER_H
	#define LLVM_LINKER_H	#define LLVM_LINKER_H

	#include <memory>	#include <memory>

		#include <string>
	#include <vector>	#include <vector>

	#include "llvm/ADT/StringRef.h"

	namespace llvm {	namespace llvm {
	namespace sys { class Path; }	namespace sys { class Path; }

	class Module;	class Module;
	class LLVMContext;	class LLVMContext;

		class StringRef;

	/// This class provides the core functionality of linking in LLVM. It retai ns a	/// This class provides the core functionality of linking in LLVM. It retai ns a
	/// Module object which is the composite of the modules and libraries linke d	/// Module object which is the composite of the modules and libraries linke d
	/// into it. The composite Module can be retrieved via the getModule() meth od.	/// into it. The composite Module can be retrieved via the getModule() meth od.
	/// In this case the Linker still retains ownership of the Module. If the	/// In this case the Linker still retains ownership of the Module. If the
	/// releaseModule() method is used, the ownership of the Module is transfer red	/// releaseModule() method is used, the ownership of the Module is transfer red
	/// to the caller and the Linker object is only suitable for destruction.	/// to the caller and the Linker object is only suitable for destruction.
	/// The Linker can link Modules from memory, bitcode files, or bitcode	/// The Linker can link Modules from memory, bitcode files, or bitcode
	/// archives. It retains a set of search paths in which to find any librar ies	/// archives. It retains a set of search paths in which to find any librar ies
	/// presented to it. By default, the linker will generate error and warning	/// presented to it. By default, the linker will generate error and warning

End of changes. 3 change blocks.
	1 lines changed or deleted	2 lines changed or added

	LiveInterval.h	LiveInterval.h

	skipping to change at line 46	skipping to change at line 46
	class raw_ostream;	class raw_ostream;

	/// VNInfo - Value Number Information.	/// VNInfo - Value Number Information.
	/// This class holds information about a machine level values, including	/// This class holds information about a machine level values, including
	/// definition and use points.	/// definition and use points.
	///	///
	class VNInfo {	class VNInfo {
	private:	private:
	enum {	enum {
	HAS_PHI_KILL = 1,	HAS_PHI_KILL = 1,

	REDEF_BY_EC = 1 << 1,	IS_PHI_DEF = 1 << 1,
	IS_PHI_DEF = 1 << 2,	IS_UNUSED = 1 << 2
	IS_UNUSED = 1 << 3
	};	};


	MachineInstr *copy;
	unsigned char flags;	unsigned char flags;

	public:	public:
	typedef BumpPtrAllocator Allocator;	typedef BumpPtrAllocator Allocator;

	/// The ID number of this value.	/// The ID number of this value.
	unsigned id;	unsigned id;


	/// The index of the defining instruction (if isDefAccurate() returns t rue).	/// The index of the defining instruction.
	SlotIndex def;	SlotIndex def;

	/// VNInfo constructor.	/// VNInfo constructor.

	VNInfo(unsigned i, SlotIndex d, MachineInstr *c)	VNInfo(unsigned i, SlotIndex d)
	: copy(c), flags(0), id(i), def(d)	: flags(0), id(i), def(d)
	{ }	{ }

	/// VNInfo construtor, copies values from orig, except for the value nu mber.	/// VNInfo construtor, copies values from orig, except for the value nu mber.
	VNInfo(unsigned i, const VNInfo &orig)	VNInfo(unsigned i, const VNInfo &orig)

	: copy(orig.copy), flags(orig.flags), id(i), def(orig.def)	: flags(orig.flags), id(i), def(orig.def)
	{ }	{ }

	/// Copy from the parameter into this VNInfo.	/// Copy from the parameter into this VNInfo.
	void copyFrom(VNInfo &src) {	void copyFrom(VNInfo &src) {
	flags = src.flags;	flags = src.flags;

	copy = src.copy;
	def = src.def;	def = src.def;
	}	}

	/// Used for copying value number info.	/// Used for copying value number info.
	unsigned getFlags() const { return flags; }	unsigned getFlags() const { return flags; }
	void setFlags(unsigned flags) { this->flags = flags; }	void setFlags(unsigned flags) { this->flags = flags; }

	/// Merge flags from another VNInfo	/// Merge flags from another VNInfo
	void mergeFlags(const VNInfo *VNI) {	void mergeFlags(const VNInfo *VNI) {
	flags = (flags \| VNI->flags) & ~IS_UNUSED;	flags = (flags \| VNI->flags) & ~IS_UNUSED;
	}	}


	/// For a register interval, if this VN was definied by a copy instr
	/// getCopy() returns a pointer to it, otherwise returns 0.
	/// For a stack interval the behaviour of this method is undefined.
	MachineInstr* getCopy() const { return copy; }
	/// For a register interval, set the copy member.
	/// This method should not be called on stack intervals as it may lead
	to
	/// undefined behavior.
	void setCopy(MachineInstr *c) { copy = c; }

	/// isDefByCopy - Return true when this value was defined by a copy-lik
	e
	/// instruction as determined by MachineInstr::isCopyLike.
	bool isDefByCopy() const { return copy != 0; }

	/// Returns true if one or more kills are PHI nodes.	/// Returns true if one or more kills are PHI nodes.
	/// Obsolete, do not use!	/// Obsolete, do not use!
	bool hasPHIKill() const { return flags & HAS_PHI_KILL; }	bool hasPHIKill() const { return flags & HAS_PHI_KILL; }
	/// Set the PHI kill flag on this value.	/// Set the PHI kill flag on this value.
	void setHasPHIKill(bool hasKill) {	void setHasPHIKill(bool hasKill) {
	if (hasKill)	if (hasKill)
	flags \|= HAS_PHI_KILL;	flags \|= HAS_PHI_KILL;
	else	else
	flags &= ~HAS_PHI_KILL;	flags &= ~HAS_PHI_KILL;
	}	}


	/// Returns true if this value is re-defined by an early clobber somewh
	ere
	/// during the live range.
	bool hasRedefByEC() const { return flags & REDEF_BY_EC; }
	/// Set the "redef by early clobber" flag on this value.
	void setHasRedefByEC(bool hasRedef) {
	if (hasRedef)
	flags \|= REDEF_BY_EC;
	else
	flags &= ~REDEF_BY_EC;
	}

	/// Returns true if this value is defined by a PHI instruction (or was,	/// Returns true if this value is defined by a PHI instruction (or was,
	/// PHI instrucions may have been eliminated).	/// PHI instrucions may have been eliminated).
	bool isPHIDef() const { return flags & IS_PHI_DEF; }	bool isPHIDef() const { return flags & IS_PHI_DEF; }
	/// Set the "phi def" flag on this value.	/// Set the "phi def" flag on this value.
	void setIsPHIDef(bool phiDef) {	void setIsPHIDef(bool phiDef) {
	if (phiDef)	if (phiDef)
	flags \|= IS_PHI_DEF;	flags \|= IS_PHI_DEF;
	else	else
	flags &= ~IS_PHI_DEF;	flags &= ~IS_PHI_DEF;
	}	}

	skipping to change at line 296	skipping to change at line 269
	return valnos[ValNo];	return valnos[ValNo];
	}	}

	/// containsValue - Returns true if VNI belongs to this interval.	/// containsValue - Returns true if VNI belongs to this interval.
	bool containsValue(const VNInfo *VNI) const {	bool containsValue(const VNInfo *VNI) const {
	return VNI && VNI->id < getNumValNums() && VNI == getValNumInfo(VNI-> id);	return VNI && VNI->id < getNumValNums() && VNI == getValNumInfo(VNI-> id);
	}	}

	/// getNextValue - Create a new value number and return it. MIIdx spec ifies	/// getNextValue - Create a new value number and return it. MIIdx spec ifies
	/// the instruction that defines the value number.	/// the instruction that defines the value number.

	VNInfo getNextValue(SlotIndex def, MachineInstr CopyMI,	VNInfo *getNextValue(SlotIndex def, VNInfo::Allocator &VNInfoAllocator)
	VNInfo::Allocator &VNInfoAllocator) {	{
	VNInfo *VNI =	VNInfo *VNI =

	new (VNInfoAllocator) VNInfo((unsigned)valnos.size(), def, CopyMI);	new (VNInfoAllocator) VNInfo((unsigned)valnos.size(), def);
	valnos.push_back(VNI);	valnos.push_back(VNI);
	return VNI;	return VNI;
	}	}

	/// Create a copy of the given value. The new value will be identical e xcept	/// Create a copy of the given value. The new value will be identical e xcept
	/// for the Value number.	/// for the Value number.
	VNInfo createValueCopy(const VNInfo orig,	VNInfo createValueCopy(const VNInfo orig,
	VNInfo::Allocator &VNInfoAllocator) {	VNInfo::Allocator &VNInfoAllocator) {
	VNInfo *VNI =	VNInfo *VNI =
	new (VNInfoAllocator) VNInfo((unsigned)valnos.size(), *orig);	new (VNInfoAllocator) VNInfo((unsigned)valnos.size(), *orig);

	skipping to change at line 383	skipping to change at line 355

	bool liveAt(SlotIndex index) const {	bool liveAt(SlotIndex index) const {
	const_iterator r = find(index);	const_iterator r = find(index);
	return r != end() && r->start <= index;	return r != end() && r->start <= index;
	}	}

	/// killedAt - Return true if a live range ends at index. Note that the kill	/// killedAt - Return true if a live range ends at index. Note that the kill
	/// point is not contained in the half-open live range. It is usually t he	/// point is not contained in the half-open live range. It is usually t he
	/// getDefIndex() slot following its last use.	/// getDefIndex() slot following its last use.
	bool killedAt(SlotIndex index) const {	bool killedAt(SlotIndex index) const {

	const_iterator r = find(index.getUseIndex());	const_iterator r = find(index.getRegSlot(true));
	return r != end() && r->end == index;	return r != end() && r->end == index;
	}	}

	/// killedInRange - Return true if the interval has kills in [Start,End ).	/// killedInRange - Return true if the interval has kills in [Start,End ).
	/// Note that the kill point is considered the end of a live range, so it is	/// Note that the kill point is considered the end of a live range, so it is
	/// not contained in the live range. If a live range ends at End, it wo n't	/// not contained in the live range. If a live range ends at End, it wo n't
	/// be counted as a kill by this method.	/// be counted as a kill by this method.
	bool killedInRange(SlotIndex Start, SlotIndex End) const;	bool killedInRange(SlotIndex Start, SlotIndex End) const;

	/// getLiveRangeContaining - Return the live range that contains the	/// getLiveRangeContaining - Return the live range that contains the

	skipping to change at line 407	skipping to change at line 379
	return I == end() ? 0 : &*I;	return I == end() ? 0 : &*I;
	}	}

	/// getLiveRangeContaining - Return the live range that contains the	/// getLiveRangeContaining - Return the live range that contains the
	/// specified index, or null if there is none.	/// specified index, or null if there is none.
	LiveRange *getLiveRangeContaining(SlotIndex Idx) {	LiveRange *getLiveRangeContaining(SlotIndex Idx) {
	iterator I = FindLiveRangeContaining(Idx);	iterator I = FindLiveRangeContaining(Idx);
	return I == end() ? 0 : &*I;	return I == end() ? 0 : &*I;
	}	}


		const LiveRange *getLiveRangeBefore(SlotIndex Idx) const {
		return getLiveRangeContaining(Idx.getPrevSlot());
		}

		LiveRange *getLiveRangeBefore(SlotIndex Idx) {
		return getLiveRangeContaining(Idx.getPrevSlot());
		}

	/// getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.	/// getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.
	VNInfo *getVNInfoAt(SlotIndex Idx) const {	VNInfo *getVNInfoAt(SlotIndex Idx) const {
	const_iterator I = FindLiveRangeContaining(Idx);	const_iterator I = FindLiveRangeContaining(Idx);
	return I == end() ? 0 : I->valno;	return I == end() ? 0 : I->valno;
	}	}

	/// getVNInfoBefore - Return the VNInfo that is live up to but not	/// getVNInfoBefore - Return the VNInfo that is live up to but not
	/// necessarilly including Idx, or NULL. Use this to find the reaching def	/// necessarilly including Idx, or NULL. Use this to find the reaching def
	/// used by an instruction at this SlotIndex position.	/// used by an instruction at this SlotIndex position.
	VNInfo *getVNInfoBefore(SlotIndex Idx) const {	VNInfo *getVNInfoBefore(SlotIndex Idx) const {

End of changes. 12 change blocks.
	40 lines changed or deleted	18 lines changed or added

	LiveIntervalAnalysis.h	LiveIntervalAnalysis.h

	skipping to change at line 66	skipping to change at line 66
	/// Special pool allocator for VNInfo's (LiveInterval val#).	/// Special pool allocator for VNInfo's (LiveInterval val#).
	///	///
	VNInfo::Allocator VNInfoAllocator;	VNInfo::Allocator VNInfoAllocator;

	typedef DenseMap<unsigned, LiveInterval*> Reg2IntervalMap;	typedef DenseMap<unsigned, LiveInterval*> Reg2IntervalMap;
	Reg2IntervalMap r2iMap_;	Reg2IntervalMap r2iMap_;

	/// allocatableRegs_ - A bit vector of allocatable registers.	/// allocatableRegs_ - A bit vector of allocatable registers.
	BitVector allocatableRegs_;	BitVector allocatableRegs_;


	/// CloneMIs - A list of clones as result of re-materialization.	/// reservedRegs_ - A bit vector of reserved registers.
	std::vector<MachineInstr*> CloneMIs;	BitVector reservedRegs_;

		/// RegMaskSlots - Sorted list of instructions with register mask opera
		nds.
		/// Always use the 'r' slot, RegMasks are normal clobbers, not early
		/// clobbers.
		SmallVector<SlotIndex, 8> RegMaskSlots;

		/// RegMaskBits - This vector is parallel to RegMaskSlots, it holds a
		/// pointer to the corresponding register mask. This pointer can be
		/// recomputed as:
		///
		/// MI = Indexes->getInstructionFromIndex(RegMaskSlot[N]);
		/// unsigned OpNum = findRegMaskOperand(MI);
		/// RegMaskBits[N] = MI->getOperand(OpNum).getRegMask();
		///
		/// This is kept in a separate vector partly because some standard
		/// libraries don't support lower_bound() with mixed objects, partly to
		/// improve locality when searching in RegMaskSlots.
		/// Also see the comment in LiveInterval::find().
		SmallVector<const uint32_t*, 8> RegMaskBits;

		/// For each basic block number, keep (begin, size) pairs indexing into
		the
		/// RegMaskSlots and RegMaskBits arrays.
		/// Note that basic block numbers may not be layout contiguous, that's
		why
		/// we can't just keep track of the first register mask in each basic
		/// block.
		SmallVector<std::pair<unsigned, unsigned>, 8> RegMaskBlocks;

	public:	public:
	static char ID; // Pass identification, replacement for typeid	static char ID; // Pass identification, replacement for typeid
	LiveIntervals() : MachineFunctionPass(ID) {	LiveIntervals() : MachineFunctionPass(ID) {
	initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());	initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
	}	}

	// Calculate the spill weight to assign to a single instruction.	// Calculate the spill weight to assign to a single instruction.
	static float getSpillWeight(bool isDef, bool isUse, unsigned loopDepth) ;	static float getSpillWeight(bool isDef, bool isUse, unsigned loopDepth) ;


	skipping to change at line 108	skipping to change at line 134
	bool hasInterval(unsigned reg) const {	bool hasInterval(unsigned reg) const {
	return r2iMap_.count(reg);	return r2iMap_.count(reg);
	}	}

	/// isAllocatable - is the physical register reg allocatable in the cur rent	/// isAllocatable - is the physical register reg allocatable in the cur rent
	/// function?	/// function?
	bool isAllocatable(unsigned reg) const {	bool isAllocatable(unsigned reg) const {
	return allocatableRegs_.test(reg);	return allocatableRegs_.test(reg);
	}	}


		/// isReserved - is the physical register reg reserved in the current
		/// function
		bool isReserved(unsigned reg) const {
		return reservedRegs_.test(reg);
		}

	/// getScaledIntervalSize - get the size of an interval in "units,"	/// getScaledIntervalSize - get the size of an interval in "units,"
	/// where every function is composed of one thousand units. This	/// where every function is composed of one thousand units. This
	/// measure scales properly with empty index slots in the function.	/// measure scales properly with empty index slots in the function.
	double getScaledIntervalSize(LiveInterval& I) {	double getScaledIntervalSize(LiveInterval& I) {
	return (1000.0 * I.getSize()) / indexes_->getIndexesLength();	return (1000.0 * I.getSize()) / indexes_->getIndexesLength();
	}	}

	/// getFuncInstructionCount - Return the number of instructions in the	/// getFuncInstructionCount - Return the number of instructions in the
	/// current function.	/// current function.
	unsigned getFuncInstructionCount() {	unsigned getFuncInstructionCount() {
	return indexes_->getFunctionSize();	return indexes_->getFunctionSize();
	}	}

	/// getApproximateInstructionCount - computes an estimate of the number	/// getApproximateInstructionCount - computes an estimate of the number
	/// of instructions in a given LiveInterval.	/// of instructions in a given LiveInterval.
	unsigned getApproximateInstructionCount(LiveInterval& I) {	unsigned getApproximateInstructionCount(LiveInterval& I) {
	double IntervalPercentage = getScaledIntervalSize(I) / 1000.0;	double IntervalPercentage = getScaledIntervalSize(I) / 1000.0;
	return (unsigned)(IntervalPercentage * indexes_->getFunctionSize());	return (unsigned)(IntervalPercentage * indexes_->getFunctionSize());
	}	}


	/// conflictsWithPhysReg - Returns true if the specified register is us
	ed or
	/// defined during the duration of the specified interval. Copies to an
	d
	/// from li.reg are allowed. This method is only able to analyze simple
	/// ranges that stay within a single basic block. Anything else is
	/// considered a conflict.
	bool conflictsWithPhysReg(const LiveInterval &li, VirtRegMap &vrm,
	unsigned reg);

	/// conflictsWithAliasRef - Similar to conflictsWithPhysRegRef except
	/// it checks for alias uses and defs.
	bool conflictsWithAliasRef(LiveInterval &li, unsigned Reg,
	SmallPtrSet<MachineInstr*,32> &JoinedCop
	ies);

	// Interval creation	// Interval creation
	LiveInterval &getOrCreateInterval(unsigned reg) {	LiveInterval &getOrCreateInterval(unsigned reg) {
	Reg2IntervalMap::iterator I = r2iMap_.find(reg);	Reg2IntervalMap::iterator I = r2iMap_.find(reg);
	if (I == r2iMap_.end())	if (I == r2iMap_.end())
	I = r2iMap_.insert(std::make_pair(reg, createInterval(reg))).first;	I = r2iMap_.insert(std::make_pair(reg, createInterval(reg))).first;
	return *I->second;	return *I->second;
	}	}

	/// dupInterval - Duplicate a live interval. The caller is responsible for	/// dupInterval - Duplicate a live interval. The caller is responsible for
	/// managing the allocated memory.	/// managing the allocated memory.

	skipping to change at line 180	skipping to change at line 199
	void removeInterval(unsigned Reg) {	void removeInterval(unsigned Reg) {
	DenseMap<unsigned, LiveInterval*>::iterator I = r2iMap_.find(Reg);	DenseMap<unsigned, LiveInterval*>::iterator I = r2iMap_.find(Reg);
	delete I->second;	delete I->second;
	r2iMap_.erase(I);	r2iMap_.erase(I);
	}	}

	SlotIndexes *getSlotIndexes() const {	SlotIndexes *getSlotIndexes() const {
	return indexes_;	return indexes_;
	}	}


	SlotIndex getZeroIndex() const {
	return indexes_->getZeroIndex();
	}

	SlotIndex getInvalidIndex() const {
	return indexes_->getInvalidIndex();
	}

	/// isNotInMIMap - returns true if the specified machine instr has been	/// isNotInMIMap - returns true if the specified machine instr has been
	/// removed or was never entered in the map.	/// removed or was never entered in the map.
	bool isNotInMIMap(const MachineInstr* Instr) const {	bool isNotInMIMap(const MachineInstr* Instr) const {
	return !indexes_->hasIndex(Instr);	return !indexes_->hasIndex(Instr);
	}	}

	/// Returns the base index of the given instruction.	/// Returns the base index of the given instruction.
	SlotIndex getInstructionIndex(const MachineInstr *instr) const {	SlotIndex getInstructionIndex(const MachineInstr *instr) const {
	return indexes_->getInstructionIndex(instr);	return indexes_->getInstructionIndex(instr);
	}	}

	skipping to change at line 219	skipping to change at line 230
	/// Return the last index in the given basic block.	/// Return the last index in the given basic block.
	SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const {	SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const {
	return indexes_->getMBBEndIdx(mbb);	return indexes_->getMBBEndIdx(mbb);
	}	}

	bool isLiveInToMBB(const LiveInterval &li,	bool isLiveInToMBB(const LiveInterval &li,
	const MachineBasicBlock *mbb) const {	const MachineBasicBlock *mbb) const {
	return li.liveAt(getMBBStartIdx(mbb));	return li.liveAt(getMBBStartIdx(mbb));
	}	}


	LiveRange* findEnteringRange(LiveInterval &li,
	const MachineBasicBlock *mbb) {
	return li.getLiveRangeContaining(getMBBStartIdx(mbb));
	}

	bool isLiveOutOfMBB(const LiveInterval &li,	bool isLiveOutOfMBB(const LiveInterval &li,
	const MachineBasicBlock *mbb) const {	const MachineBasicBlock *mbb) const {
	return li.liveAt(getMBBEndIdx(mbb).getPrevSlot());	return li.liveAt(getMBBEndIdx(mbb).getPrevSlot());
	}	}


	LiveRange* findExitingRange(LiveInterval &li,
	const MachineBasicBlock *mbb) {
	return li.getLiveRangeContaining(getMBBEndIdx(mbb).getPrevSlot());
	}

	MachineBasicBlock* getMBBFromIndex(SlotIndex index) const {	MachineBasicBlock* getMBBFromIndex(SlotIndex index) const {
	return indexes_->getMBBFromIndex(index);	return indexes_->getMBBFromIndex(index);
	}	}

	SlotIndex InsertMachineInstrInMaps(MachineInstr *MI) {	SlotIndex InsertMachineInstrInMaps(MachineInstr *MI) {
	return indexes_->insertMachineInstrInMaps(MI);	return indexes_->insertMachineInstrInMaps(MI);
	}	}

	void RemoveMachineInstrFromMaps(MachineInstr *MI) {	void RemoveMachineInstrFromMaps(MachineInstr *MI) {
	indexes_->removeMachineInstrFromMaps(MI);	indexes_->removeMachineInstrFromMaps(MI);
	}	}

	void ReplaceMachineInstrInMaps(MachineInstr MI, MachineInstr NewMI) {	void ReplaceMachineInstrInMaps(MachineInstr MI, MachineInstr NewMI) {
	indexes_->replaceMachineInstrInMaps(MI, NewMI);	indexes_->replaceMachineInstrInMaps(MI, NewMI);
	}	}


	void InsertMBBInMaps(MachineBasicBlock *MBB) {
	indexes_->insertMBBInMaps(MBB);
	}

	bool findLiveInMBBs(SlotIndex Start, SlotIndex End,	bool findLiveInMBBs(SlotIndex Start, SlotIndex End,
	SmallVectorImpl<MachineBasicBlock*> &MBBs) const {	SmallVectorImpl<MachineBasicBlock*> &MBBs) const {
	return indexes_->findLiveInMBBs(Start, End, MBBs);	return indexes_->findLiveInMBBs(Start, End, MBBs);
	}	}


	void renumber() {
	indexes_->renumberIndexes();
	}

	VNInfo::Allocator& getVNInfoAllocator() { return VNInfoAllocator; }	VNInfo::Allocator& getVNInfoAllocator() { return VNInfoAllocator; }

	virtual void getAnalysisUsage(AnalysisUsage &AU) const;	virtual void getAnalysisUsage(AnalysisUsage &AU) const;
	virtual void releaseMemory();	virtual void releaseMemory();

	/// runOnMachineFunction - pass entry point	/// runOnMachineFunction - pass entry point
	virtual bool runOnMachineFunction(MachineFunction&);	virtual bool runOnMachineFunction(MachineFunction&);

	/// print - Implement the dump method.	/// print - Implement the dump method.
	virtual void print(raw_ostream &O, const Module* = 0) const;	virtual void print(raw_ostream &O, const Module* = 0) const;


	/// addIntervalsForSpills - Create new intervals for spilled defs / use
	s of
	/// the given interval. FIXME: It also returns the weight of the spill
	slot
	/// (if any is created) by reference. This is temporary.
	std::vector<LiveInterval*>
	addIntervalsForSpills(const LiveInterval& i,
	const SmallVectorImpl<LiveInterval> SpillIs,
	const MachineLoopInfo *loopInfo, VirtRegMap& vrm)
	;

	/// spillPhysRegAroundRegDefsUses - Spill the specified physical regist
	er
	/// around all defs and uses of the specified interval. Return true if
	it
	/// was able to cut its interval.
	bool spillPhysRegAroundRegDefsUses(const LiveInterval &li,
	unsigned PhysReg, VirtRegMap &vrm);

	/// isReMaterializable - Returns true if every definition of MI of ever y	/// isReMaterializable - Returns true if every definition of MI of ever y
	/// val# of the specified interval is re-materializable. Also returns t rue	/// val# of the specified interval is re-materializable. Also returns t rue
	/// by reference if all of the defs are load instructions.	/// by reference if all of the defs are load instructions.
	bool isReMaterializable(const LiveInterval &li,	bool isReMaterializable(const LiveInterval &li,
	const SmallVectorImpl<LiveInterval> SpillIs,	const SmallVectorImpl<LiveInterval> SpillIs,
	bool &isLoad);	bool &isLoad);


	/// isReMaterializable - Returns true if the definition MI of the speci	/// intervalIsInOneMBB - If LI is confined to a single basic block, ret
	fied	urn
	/// val# of the specified interval is re-materializable.	/// a pointer to that block. If LI is live in to or out of any block,
	bool isReMaterializable(const LiveInterval &li, const VNInfo *ValNo,	/// return NULL.
	MachineInstr *MI);	MachineBasicBlock *intervalIsInOneMBB(const LiveInterval &LI) const;

	/// getRepresentativeReg - Find the largest super register of the speci
	fied
	/// physical register.
	unsigned getRepresentativeReg(unsigned Reg) const;

	/// getNumConflictsWithPhysReg - Return the number of uses and defs of
	the
	/// specified interval that conflicts with the specified physical regis
	ter.
	unsigned getNumConflictsWithPhysReg(const LiveInterval &li,
	unsigned PhysReg) const;

	/// intervalIsInOneMBB - Returns true if the specified interval is enti
	rely
	/// within a single basic block.
	bool intervalIsInOneMBB(const LiveInterval &li) const;

	/// getLastSplitPoint - Return the last possible insertion point in mbb
	for
	/// spilling and splitting code. This is the first terminator, or the c
	all
	/// instruction if li is live into a landing pad successor.
	MachineBasicBlock::iterator getLastSplitPoint(const LiveInterval &li,
	MachineBasicBlock *mbb) c
	onst;

	/// addKillFlags - Add kill flags to any instruction that kills a virtu al	/// addKillFlags - Add kill flags to any instruction that kills a virtu al
	/// register.	/// register.
	void addKillFlags();	void addKillFlags();


		/// handleMove - call this method to notify LiveIntervals that
		/// instruction 'mi' has been moved within a basic block. This will upd
		ate
		/// the live intervals for all operands of mi. Moves between basic bloc
		ks
		/// are not supported.
		void handleMove(MachineInstr* MI);

		/// moveIntoBundle - Update intervals for operands of MI so that they
		/// begin/end on the SlotIndex for BundleStart.
		///
		/// Requires MI and BundleStart to have SlotIndexes, and assumes
		/// existing liveness is accurate. BundleStart should be the first
		/// instruction in the Bundle.
		void handleMoveIntoBundle(MachineInstr* MI, MachineInstr* BundleStart);

		// Register mask functions.
		//
		// Machine instructions may use a register mask operand to indicate tha
		t a
		// large number of registers are clobbered by the instruction. This is
		// typically used for calls.
		//
		// For compile time performance reasons, these clobbers are not recorde
		d in
		// the live intervals for individual physical registers. Instead,
		// LiveIntervalAnalysis maintains a sorted list of instructions with
		// register mask operands.

		/// getRegMaskSlots - Returns a sorted array of slot indices of all
		/// instructions with register mask operands.
		ArrayRef<SlotIndex> getRegMaskSlots() const { return RegMaskSlots; }

		/// getRegMaskSlotsInBlock - Returns a sorted array of slot indices of
		all
		/// instructions with register mask operands in the basic block numbere
		d
		/// MBBNum.
		ArrayRef<SlotIndex> getRegMaskSlotsInBlock(unsigned MBBNum) const {
		std::pair<unsigned, unsigned> P = RegMaskBlocks[MBBNum];
		return getRegMaskSlots().slice(P.first, P.second);
		}

		/// getRegMaskBits() - Returns an array of register mask pointers
		/// corresponding to getRegMaskSlots().
		ArrayRef<const uint32_t*> getRegMaskBits() const { return RegMaskBits;
		}

		/// getRegMaskBitsInBlock - Returns an array of mask pointers correspon
		ding
		/// to getRegMaskSlotsInBlock(MBBNum).
		ArrayRef<const uint32_t*> getRegMaskBitsInBlock(unsigned MBBNum) const
		{
		std::pair<unsigned, unsigned> P = RegMaskBlocks[MBBNum];
		return getRegMaskBits().slice(P.first, P.second);
		}

		/// checkRegMaskInterference - Test if LI is live across any register m
		ask
		/// instructions, and compute a bit mask of physical registers that are
		not
		/// clobbered by any of them.
		///
		/// Returns false if LI doesn't cross any register mask instructions. I
		n
		/// that case, the bit vector is not filled in.
		bool checkRegMaskInterference(LiveInterval &LI,
		BitVector &UsableRegs);

	private:	private:
	/// computeIntervals - Compute live intervals.	/// computeIntervals - Compute live intervals.
	void computeIntervals();	void computeIntervals();

	/// handleRegisterDef - update intervals for a register def	/// handleRegisterDef - update intervals for a register def
	/// (calls handlePhysicalRegisterDef and	/// (calls handlePhysicalRegisterDef and
	/// handleVirtualRegisterDef)	/// handleVirtualRegisterDef)
	void handleRegisterDef(MachineBasicBlock *MBB,	void handleRegisterDef(MachineBasicBlock *MBB,
	MachineBasicBlock::iterator MI,	MachineBasicBlock::iterator MI,
	SlotIndex MIIdx,	SlotIndex MIIdx,

	skipping to change at line 354	skipping to change at line 371
	MachineBasicBlock::iterator MI,	MachineBasicBlock::iterator MI,
	SlotIndex MIIdx, MachineOperand& MO,	SlotIndex MIIdx, MachineOperand& MO,
	unsigned MOIdx,	unsigned MOIdx,
	LiveInterval& interval);	LiveInterval& interval);

	/// handlePhysicalRegisterDef - update intervals for a physical registe r	/// handlePhysicalRegisterDef - update intervals for a physical registe r
	/// def.	/// def.
	void handlePhysicalRegisterDef(MachineBasicBlock* mbb,	void handlePhysicalRegisterDef(MachineBasicBlock* mbb,
	MachineBasicBlock::iterator mi,	MachineBasicBlock::iterator mi,
	SlotIndex MIIdx, MachineOperand& MO,	SlotIndex MIIdx, MachineOperand& MO,

	LiveInterval &interval,	LiveInterval &interval);
	MachineInstr *CopyMI);

	/// handleLiveInRegister - Create interval for a livein register.	/// handleLiveInRegister - Create interval for a livein register.
	void handleLiveInRegister(MachineBasicBlock* mbb,	void handleLiveInRegister(MachineBasicBlock* mbb,
	SlotIndex MIIdx,	SlotIndex MIIdx,

	LiveInterval &interval, bool isAlias = false) ;	LiveInterval &interval);

	/// getReMatImplicitUse - If the remat definition MI has one (for now, we	/// getReMatImplicitUse - If the remat definition MI has one (for now, we
	/// only allow one) virtual register operand, then its uses are implici tly	/// only allow one) virtual register operand, then its uses are implici tly
	/// using the register. Returns the virtual register.	/// using the register. Returns the virtual register.
	unsigned getReMatImplicitUse(const LiveInterval &li,	unsigned getReMatImplicitUse(const LiveInterval &li,
	MachineInstr *MI) const;	MachineInstr *MI) const;

	/// isValNoAvailableAt - Return true if the val# of the specified inter val	/// isValNoAvailableAt - Return true if the val# of the specified inter val
	/// which reaches the given instruction also reaches the specified use	/// which reaches the given instruction also reaches the specified use
	/// index.	/// index.

	skipping to change at line 382	skipping to change at line 398
	SlotIndex UseIdx) const;	SlotIndex UseIdx) const;

	/// isReMaterializable - Returns true if the definition MI of the speci fied	/// isReMaterializable - Returns true if the definition MI of the speci fied
	/// val# of the specified interval is re-materializable. Also returns t rue	/// val# of the specified interval is re-materializable. Also returns t rue
	/// by reference if the def is a load.	/// by reference if the def is a load.
	bool isReMaterializable(const LiveInterval &li, const VNInfo *ValNo,	bool isReMaterializable(const LiveInterval &li, const VNInfo *ValNo,
	MachineInstr *MI,	MachineInstr *MI,
	const SmallVectorImpl<LiveInterval> SpillIs,	const SmallVectorImpl<LiveInterval> SpillIs,
	bool &isLoad);	bool &isLoad);


	/// tryFoldMemoryOperand - Attempts to fold either a spill / restore fr
	om
	/// slot / to reg or any rematerialized load into ith operand of specif
	ied
	/// MI. If it is successul, MI is updated with the newly created MI and
	/// returns true.
	bool tryFoldMemoryOperand(MachineInstr* &MI, VirtRegMap &vrm,
	MachineInstr *DefMI, SlotIndex InstrIdx,
	SmallVector<unsigned, 2> &Ops,
	bool isSS, int FrameIndex, unsigned Reg);

	/// canFoldMemoryOperand - Return true if the specified load / store
	/// folding is possible.
	bool canFoldMemoryOperand(MachineInstr *MI,
	SmallVector<unsigned, 2> &Ops,
	bool ReMatLoadSS) const;

	/// anyKillInMBBAfterIdx - Returns true if there is a kill of the speci
	fied
	/// VNInfo that's after the specified index but is within the basic blo
	ck.
	bool anyKillInMBBAfterIdx(const LiveInterval &li, const VNInfo *VNI,
	MachineBasicBlock *MBB,
	SlotIndex Idx) const;

	/// hasAllocatableSuperReg - Return true if the specified physical regi
	ster
	/// has any super register that's allocatable.
	bool hasAllocatableSuperReg(unsigned Reg) const;

	/// SRInfo - Spill / restore info.
	struct SRInfo {
	SlotIndex index;
	unsigned vreg;
	bool canFold;
	SRInfo(SlotIndex i, unsigned vr, bool f)
	: index(i), vreg(vr), canFold(f) {}
	};

	bool alsoFoldARestore(int Id, SlotIndex index, unsigned vr,
	BitVector &RestoreMBBs,
	DenseMap<unsigned,std::vector<SRInfo> >&RestoreId
	xes);
	void eraseRestoreInfo(int Id, SlotIndex index, unsigned vr,
	BitVector &RestoreMBBs,
	DenseMap<unsigned,std::vector<SRInfo> >&RestoreId
	xes);

	/// handleSpilledImpDefs - Remove IMPLICIT_DEF instructions which are b
	eing
	/// spilled and create empty intervals for their uses.
	void handleSpilledImpDefs(const LiveInterval &li, VirtRegMap &vrm,
	const TargetRegisterClass* rc,
	std::vector<LiveInterval*> &NewLIs);

	/// rewriteImplicitOps - Rewrite implicit use operands of MI (i.e. uses
	of
	/// interval on to-be re-materialized operands of MI) with new register
	.
	void rewriteImplicitOps(const LiveInterval &li,
	MachineInstr *MI, unsigned NewVReg, VirtRegMap &
	vrm);

	/// rewriteInstructionForSpills, rewriteInstructionsForSpills - Helper
	/// functions for addIntervalsForSpills to rewrite uses / defs for the
	given
	/// live range.
	bool rewriteInstructionForSpills(const LiveInterval &li, const VNInfo *
	VNI,
	bool TrySplit, SlotIndex index, SlotIndex end,
	MachineInstr MI, MachineInstr OrigDefMI, MachineInstr *DefMI,
	unsigned Slot, int LdSlot,
	bool isLoad, bool isLoadSS, bool DefIsReMat, bool CanDelete,
	VirtRegMap &vrm, const TargetRegisterClass* rc,
	SmallVector<int, 4> &ReMatIds, const MachineLoopInfo *loopInfo,
	unsigned &NewVReg, unsigned ImpUse, bool &HasDef, bool &HasUse,
	DenseMap<unsigned,unsigned> &MBBVRegsMap,
	std::vector<LiveInterval*> &NewLIs);
	void rewriteInstructionsForSpills(const LiveInterval &li, bool TrySplit
	,
	LiveInterval::Ranges::const_iterator &I,
	MachineInstr OrigDefMI, MachineInstr DefMI, unsigned Slot, int Ld
	Slot,
	bool isLoad, bool isLoadSS, bool DefIsReMat, bool CanDelete,
	VirtRegMap &vrm, const TargetRegisterClass* rc,
	SmallVector<int, 4> &ReMatIds, const MachineLoopInfo *loopInfo,
	BitVector &SpillMBBs,
	DenseMap<unsigned,std::vector<SRInfo> > &SpillIdxes,
	BitVector &RestoreMBBs,
	DenseMap<unsigned,std::vector<SRInfo> > &RestoreIdxes,
	DenseMap<unsigned,unsigned> &MBBVRegsMap,
	std::vector<LiveInterval*> &NewLIs);

	static LiveInterval* createInterval(unsigned Reg);	static LiveInterval* createInterval(unsigned Reg);

	void printInstrs(raw_ostream &O) const;	void printInstrs(raw_ostream &O) const;
	void dumpInstrs() const;	void dumpInstrs() const;


		class HMEditor;
	};	};
	} // End llvm namespace	} // End llvm namespace

	#endif	#endif

End of changes. 15 change blocks.
	190 lines changed or deleted	115 lines changed or added

	Loads.h	Loads.h

	skipping to change at line 23	skipping to change at line 23

	#ifndef LLVM_ANALYSIS_LOADS_H	#ifndef LLVM_ANALYSIS_LOADS_H
	#define LLVM_ANALYSIS_LOADS_H	#define LLVM_ANALYSIS_LOADS_H

	#include "llvm/BasicBlock.h"	#include "llvm/BasicBlock.h"

	namespace llvm {	namespace llvm {

	class AliasAnalysis;	class AliasAnalysis;
	class TargetData;	class TargetData;

		class MDNode;

	/// isSafeToLoadUnconditionally - Return true if we know that executing a l oad	/// isSafeToLoadUnconditionally - Return true if we know that executing a l oad
	/// from this value cannot trap. If it is not obviously safe to load from the	/// from this value cannot trap. If it is not obviously safe to load from the
	/// specified pointer, we do a quick local scan of the basic block containi ng	/// specified pointer, we do a quick local scan of the basic block containi ng
	/// ScanFrom, to determine if the address is already accessed.	/// ScanFrom, to determine if the address is already accessed.
	bool isSafeToLoadUnconditionally(Value V, Instruction ScanFrom,	bool isSafeToLoadUnconditionally(Value V, Instruction ScanFrom,
	unsigned Align, const TargetData *TD = 0);	unsigned Align, const TargetData *TD = 0);

	/// FindAvailableLoadedValue - Scan the ScanBB block backwards (starting at	/// FindAvailableLoadedValue - Scan the ScanBB block backwards (starting at
	/// the instruction before ScanFrom) checking to see if we have the value a t	/// the instruction before ScanFrom) checking to see if we have the value a t

	skipping to change at line 44	skipping to change at line 45
	/// instructions. If the value is available, return it.	/// instructions. If the value is available, return it.
	///	///
	/// If not, return the iterator for the last validated instruction that the	/// If not, return the iterator for the last validated instruction that the
	/// value would be live through. If we scanned the entire block and didn't	/// value would be live through. If we scanned the entire block and didn't
	/// find something that invalidates *Ptr or provides it, ScanFrom would be	/// find something that invalidates *Ptr or provides it, ScanFrom would be
	/// left at begin() and this returns null. ScanFrom could also be left	/// left at begin() and this returns null. ScanFrom could also be left
	///	///
	/// MaxInstsToScan specifies the maximum instructions to scan in the block.	/// MaxInstsToScan specifies the maximum instructions to scan in the block.
	/// If it is set to 0, it will scan the whole block. You can also optionall y	/// If it is set to 0, it will scan the whole block. You can also optionall y
	/// specify an alias analysis implementation, which makes this more precise .	/// specify an alias analysis implementation, which makes this more precise .

		///
		/// If TBAATag is non-null and a load or store is found, the TBAA tag from
		the
		/// load or store is recorded there. If there is no TBAA tag or if no acce
		ss
		/// is found, it is left unmodified.
	Value FindAvailableLoadedValue(Value Ptr, BasicBlock *ScanBB,	Value FindAvailableLoadedValue(Value Ptr, BasicBlock *ScanBB,
	BasicBlock::iterator &ScanFrom,	BasicBlock::iterator &ScanFrom,
	unsigned MaxInstsToScan = 6,	unsigned MaxInstsToScan = 6,

	AliasAnalysis *AA = 0);	AliasAnalysis *AA = 0,
		MDNode **TBAATag = 0);

	}	}

	#endif	#endif

End of changes. 3 change blocks.
	1 lines changed or deleted	9 lines changed or added

	LoopInfo.h	LoopInfo.h

	skipping to change at line 26	skipping to change at line 26
	// each natural loop identified, this analysis identifies natural loops	// each natural loop identified, this analysis identifies natural loops
	// contained entirely within the loop and the basic blocks the make up the loop.	// contained entirely within the loop and the basic blocks the make up the loop.
	//	//
	// It can calculate on the fly various bits of information, for example:	// It can calculate on the fly various bits of information, for example:
	//	//
	// * whether there is a preheader for the loop	// * whether there is a preheader for the loop
	// * the number of back edges to the header	// * the number of back edges to the header
	// * whether or not a particular block branches out of the loop	// * whether or not a particular block branches out of the loop
	// * the successor blocks of the loop	// * the successor blocks of the loop
	// * the loop depth	// * the loop depth

	// * the trip count
	// * etc...	// * etc...
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_ANALYSIS_LOOP_INFO_H	#ifndef LLVM_ANALYSIS_LOOP_INFO_H
	#define LLVM_ANALYSIS_LOOP_INFO_H	#define LLVM_ANALYSIS_LOOP_INFO_H

	#include "llvm/Pass.h"	#include "llvm/Pass.h"
	#include "llvm/ADT/DenseMap.h"	#include "llvm/ADT/DenseMap.h"
	#include "llvm/ADT/DenseSet.h"	#include "llvm/ADT/DenseSet.h"

	skipping to change at line 419	skipping to change at line 418
	/// the mapping in the LoopInfo class.	/// the mapping in the LoopInfo class.
	void removeBlockFromLoop(BlockT *BB) {	void removeBlockFromLoop(BlockT *BB) {
	RemoveFromVector(Blocks, BB);	RemoveFromVector(Blocks, BB);
	}	}

	/// verifyLoop - Verify loop structure	/// verifyLoop - Verify loop structure
	void verifyLoop() const {	void verifyLoop() const {
	#ifndef NDEBUG	#ifndef NDEBUG
	assert(!Blocks.empty() && "Loop header is missing");	assert(!Blocks.empty() && "Loop header is missing");


		// Setup for using a depth-first iterator to visit every block in the l
		oop.
		SmallVector<BlockT*, 8> ExitBBs;
		getExitBlocks(ExitBBs);
		llvm::SmallPtrSet<BlockT*, 8> VisitSet;
		VisitSet.insert(ExitBBs.begin(), ExitBBs.end());
		df_ext_iterator<BlockT, llvm::SmallPtrSet<BlockT, 8> >
		BI = df_ext_begin(getHeader(), VisitSet),
		BE = df_ext_end(getHeader(), VisitSet);

		// Keep track of the number of BBs visited.
		unsigned NumVisited = 0;

	// Sort the blocks vector so that we can use binary search to do quick	// Sort the blocks vector so that we can use binary search to do quick
	// lookups.	// lookups.
	SmallVector<BlockT*, 128> LoopBBs(block_begin(), block_end());	SmallVector<BlockT*, 128> LoopBBs(block_begin(), block_end());
	std::sort(LoopBBs.begin(), LoopBBs.end());	std::sort(LoopBBs.begin(), LoopBBs.end());

	// Check the individual blocks.	// Check the individual blocks.

	for (block_iterator I = block_begin(), E = block_end(); I != E; ++I) {	for ( ; BI != BE; ++BI) {
	BlockT BB = I;	BlockT BB = BI;
	bool HasInsideLoopSuccs = false;	bool HasInsideLoopSuccs = false;
	bool HasInsideLoopPreds = false;	bool HasInsideLoopPreds = false;
	SmallVector<BlockT *, 2> OutsideLoopPreds;	SmallVector<BlockT *, 2> OutsideLoopPreds;

	typedef GraphTraits<BlockT*> BlockTraits;	typedef GraphTraits<BlockT*> BlockTraits;
	for (typename BlockTraits::ChildIteratorType SI =	for (typename BlockTraits::ChildIteratorType SI =
	BlockTraits::child_begin(BB), SE = BlockTraits::child_end(BB);	BlockTraits::child_begin(BB), SE = BlockTraits::child_end(BB);
	SI != SE; ++SI)	SI != SE; ++SI)
	if (std::binary_search(LoopBBs.begin(), LoopBBs.end(), *SI)) {	if (std::binary_search(LoopBBs.begin(), LoopBBs.end(), *SI)) {
	HasInsideLoopSuccs = true;	HasInsideLoopSuccs = true;
	break;	break;
	}	}
	typedef GraphTraits<Inverse<BlockT*> > InvBlockTraits;	typedef GraphTraits<Inverse<BlockT*> > InvBlockTraits;
	for (typename InvBlockTraits::ChildIteratorType PI =	for (typename InvBlockTraits::ChildIteratorType PI =
	InvBlockTraits::child_begin(BB), PE = InvBlockTraits::child_end( BB);	InvBlockTraits::child_begin(BB), PE = InvBlockTraits::child_end( BB);
	PI != PE; ++PI) {	PI != PE; ++PI) {

	typename InvBlockTraits::NodeType N = PI;	BlockT N = PI;
	if (std::binary_search(LoopBBs.begin(), LoopBBs.end(), N))	if (std::binary_search(LoopBBs.begin(), LoopBBs.end(), N))
	HasInsideLoopPreds = true;	HasInsideLoopPreds = true;
	else	else
	OutsideLoopPreds.push_back(N);	OutsideLoopPreds.push_back(N);
	}	}

	if (BB == getHeader()) {	if (BB == getHeader()) {
	assert(!OutsideLoopPreds.empty() && "Loop is unreachable!");	assert(!OutsideLoopPreds.empty() && "Loop is unreachable!");
	} else if (!OutsideLoopPreds.empty()) {	} else if (!OutsideLoopPreds.empty()) {
	// A non-header loop shouldn't be reachable from outside the loop,	// A non-header loop shouldn't be reachable from outside the loop,

	skipping to change at line 467	skipping to change at line 478
	for (df_iterator<BlockT *> NI = df_begin(EntryBB),	for (df_iterator<BlockT *> NI = df_begin(EntryBB),
	NE = df_end(EntryBB); NI != NE; ++NI)	NE = df_end(EntryBB); NI != NE; ++NI)
	for (unsigned i = 0, e = OutsideLoopPreds.size(); i != e; ++i)	for (unsigned i = 0, e = OutsideLoopPreds.size(); i != e; ++i)
	assert(*NI != OutsideLoopPreds[i] &&	assert(*NI != OutsideLoopPreds[i] &&
	"Loop has multiple entry points!");	"Loop has multiple entry points!");
	}	}
	assert(HasInsideLoopPreds && "Loop block has no in-loop predecessors! ");	assert(HasInsideLoopPreds && "Loop block has no in-loop predecessors! ");
	assert(HasInsideLoopSuccs && "Loop block has no in-loop successors!") ;	assert(HasInsideLoopSuccs && "Loop block has no in-loop successors!") ;
	assert(BB != getHeader()->getParent()->begin() &&	assert(BB != getHeader()->getParent()->begin() &&
	"Loop contains function entry block!");	"Loop contains function entry block!");


		NumVisited++;
	}	}


		assert(NumVisited == getNumBlocks() && "Unreachable block in loop");

	// Check the subloops.	// Check the subloops.
	for (iterator I = begin(), E = end(); I != E; ++I)	for (iterator I = begin(), E = end(); I != E; ++I)
	// Each block in each subloop should be contained within this loop.	// Each block in each subloop should be contained within this loop.
	for (block_iterator BI = (I)->block_begin(), BE = (I)->block_end();	for (block_iterator BI = (I)->block_begin(), BE = (I)->block_end();
	BI != BE; ++BI) {	BI != BE; ++BI) {
	assert(std::binary_search(LoopBBs.begin(), LoopBBs.end(), *BI) &&	assert(std::binary_search(LoopBBs.begin(), LoopBBs.end(), *BI) &&
	"Loop does not contain all the blocks of a subloop!");	"Loop does not contain all the blocks of a subloop!");
	}	}

	// Check the parent loop pointer.	// Check the parent loop pointer.

	skipping to change at line 574	skipping to change at line 589
	/// getCanonicalInductionVariable - Check to see if the loop has a canoni cal	/// getCanonicalInductionVariable - Check to see if the loop has a canoni cal
	/// induction variable: an integer recurrence that starts at 0 and increm ents	/// induction variable: an integer recurrence that starts at 0 and increm ents
	/// by one each time through the loop. If so, return the phi node that	/// by one each time through the loop. If so, return the phi node that
	/// corresponds to it.	/// corresponds to it.
	///	///
	/// The IndVarSimplify pass transforms loops to have a canonical inductio n	/// The IndVarSimplify pass transforms loops to have a canonical inductio n
	/// variable.	/// variable.
	///	///
	PHINode *getCanonicalInductionVariable() const;	PHINode *getCanonicalInductionVariable() const;


	/// getTripCount - Return a loop-invariant LLVM value indicating the numb
	er of
	/// times the loop will be executed. Note that this means that the backe
	dge
	/// of the loop executes N-1 times. If the trip-count cannot be determin
	ed,
	/// this returns null.
	///
	/// The IndVarSimplify pass transforms loops to have a form that this
	/// function easily understands.
	///
	Value *getTripCount() const;

	/// getSmallConstantTripCount - Returns the trip count of this loop as a
	/// normal unsigned value, if possible. Returns 0 if the trip count is un
	known
	/// of not constant. Will also return 0 if the trip count is very large
	/// (>= 2^32)
	///
	/// The IndVarSimplify pass transforms loops to have a form that this
	/// function easily understands.
	///
	unsigned getSmallConstantTripCount() const;

	/// getSmallConstantTripMultiple - Returns the largest constant divisor o
	f the
	/// trip count of this loop as a normal unsigned value, if possible. This
	/// means that the actual trip count is always a multiple of the returned
	/// value (don't forget the trip count could very well be zero as well!).
	///
	/// Returns 1 if the trip count is unknown or not guaranteed to be the
	/// multiple of a constant (which is also the case if the trip count is s
	imply
	/// constant, use getSmallConstantTripCount for that case), Will also ret
	urn 1
	/// if the trip count is very large (>= 2^32).
	unsigned getSmallConstantTripMultiple() const;

	/// isLCSSAForm - Return true if the Loop is in LCSSA form	/// isLCSSAForm - Return true if the Loop is in LCSSA form
	bool isLCSSAForm(DominatorTree &DT) const;	bool isLCSSAForm(DominatorTree &DT) const;

	/// isLoopSimplifyForm - Return true if the Loop is in the form that	/// isLoopSimplifyForm - Return true if the Loop is in the form that
	/// the LoopSimplify form transforms loops to, which is sometimes called	/// the LoopSimplify form transforms loops to, which is sometimes called
	/// normal form.	/// normal form.
	bool isLoopSimplifyForm() const;	bool isLoopSimplifyForm() const;


		/// isSafeToClone - Return true if the loop body is safe to clone in prac
		tice.
		bool isSafeToClone() const;

	/// hasDedicatedExits - Return true if no exit block for the loop	/// hasDedicatedExits - Return true if no exit block for the loop
	/// has a predecessor that is outside the loop.	/// has a predecessor that is outside the loop.
	bool hasDedicatedExits() const;	bool hasDedicatedExits() const;

	/// getUniqueExitBlocks - Return all unique successor blocks of this loop .	/// getUniqueExitBlocks - Return all unique successor blocks of this loop .
	/// These are the blocks _outside of the current loop_ which are branched to.	/// These are the blocks _outside of the current loop_ which are branched to.
	/// This assumes that loop exits are in canonical form.	/// This assumes that loop exits are in canonical form.
	///	///
	void getUniqueExitBlocks(SmallVectorImpl<BasicBlock *> &ExitBlocks) const ;	void getUniqueExitBlocks(SmallVectorImpl<BasicBlock *> &ExitBlocks) const ;


	skipping to change at line 674	skipping to change at line 661
	///	///
	typedef typename std::vector<LoopT *>::const_iterator iterator;	typedef typename std::vector<LoopT *>::const_iterator iterator;
	iterator begin() const { return TopLevelLoops.begin(); }	iterator begin() const { return TopLevelLoops.begin(); }
	iterator end() const { return TopLevelLoops.end(); }	iterator end() const { return TopLevelLoops.end(); }
	bool empty() const { return TopLevelLoops.empty(); }	bool empty() const { return TopLevelLoops.empty(); }

	/// getLoopFor - Return the inner most loop that BB lives in. If a basic	/// getLoopFor - Return the inner most loop that BB lives in. If a basic
	/// block is in no loop (for example the entry node), null is returned.	/// block is in no loop (for example the entry node), null is returned.
	///	///
	LoopT getLoopFor(const BlockT BB) const {	LoopT getLoopFor(const BlockT BB) const {

	typename DenseMap<BlockT , LoopT >::const_iterator I=	return BBMap.lookup(const_cast<BlockT*>(BB));
	BBMap.find(const_cast<BlockT*>(BB));
	return I != BBMap.end() ? I->second : 0;
	}	}

	/// operator[] - same as getLoopFor...	/// operator[] - same as getLoopFor...
	///	///
	const LoopT operator[](const BlockT BB) const {	const LoopT operator[](const BlockT BB) const {
	return getLoopFor(BB);	return getLoopFor(BB);
	}	}

	/// getLoopDepth - Return the loop nesting level of the specified block. A	/// getLoopDepth - Return the loop nesting level of the specified block. A
	/// depth of 0 means the block is not inside any loop.	/// depth of 0 means the block is not inside any loop.

	skipping to change at line 715	skipping to change at line 700
	assert(L->getParentLoop() == 0 && "Not a top-level loop!");	assert(L->getParentLoop() == 0 && "Not a top-level loop!");
	TopLevelLoops.erase(TopLevelLoops.begin() + (I-begin()));	TopLevelLoops.erase(TopLevelLoops.begin() + (I-begin()));
	return L;	return L;
	}	}

	/// changeLoopFor - Change the top-level loop that contains BB to the	/// changeLoopFor - Change the top-level loop that contains BB to the
	/// specified loop. This should be used by transformations that restruct ure	/// specified loop. This should be used by transformations that restruct ure
	/// the loop hierarchy tree.	/// the loop hierarchy tree.
	void changeLoopFor(BlockT BB, LoopT L) {	void changeLoopFor(BlockT BB, LoopT L) {
	if (!L) {	if (!L) {

	typename DenseMap<BlockT , LoopT >::iterator I = BBMap.find(BB);	BBMap.erase(BB);
	if (I != BBMap.end())
	BBMap.erase(I);
	return;	return;
	}	}
	BBMap[BB] = L;	BBMap[BB] = L;
	}	}

	/// changeTopLevelLoop - Replace the specified loop in the top-level loop s	/// changeTopLevelLoop - Replace the specified loop in the top-level loop s
	/// list with the indicated loop.	/// list with the indicated loop.
	void changeTopLevelLoop(LoopT *OldLoop,	void changeTopLevelLoop(LoopT *OldLoop,
	LoopT *NewLoop) {	LoopT *NewLoop) {
	typename std::vector<LoopT *>::iterator I =	typename std::vector<LoopT *>::iterator I =

	skipping to change at line 774	skipping to change at line 757
	void Calculate(DominatorTreeBase<BlockT> &DT) {	void Calculate(DominatorTreeBase<BlockT> &DT) {
	BlockT *RootNode = DT.getRootNode()->getBlock();	BlockT *RootNode = DT.getRootNode()->getBlock();

	for (df_iterator<BlockT*> NI = df_begin(RootNode),	for (df_iterator<BlockT*> NI = df_begin(RootNode),
	NE = df_end(RootNode); NI != NE; ++NI)	NE = df_end(RootNode); NI != NE; ++NI)
	if (LoopT L = ConsiderForLoop(NI, DT))	if (LoopT L = ConsiderForLoop(NI, DT))
	TopLevelLoops.push_back(L);	TopLevelLoops.push_back(L);
	}	}

	LoopT ConsiderForLoop(BlockT BB, DominatorTreeBase<BlockT> &DT) {	LoopT ConsiderForLoop(BlockT BB, DominatorTreeBase<BlockT> &DT) {

	if (BBMap.find(BB) != BBMap.end()) return 0;// Haven't processed this n ode?	if (BBMap.count(BB)) return 0; // Haven't processed this node?

	std::vector<BlockT *> TodoStack;	std::vector<BlockT *> TodoStack;

	// Scan the predecessors of BB, checking to see if BB dominates any of	// Scan the predecessors of BB, checking to see if BB dominates any of
	// them. This identifies backedges which target this node...	// them. This identifies backedges which target this node...
	typedef GraphTraits<Inverse<BlockT*> > InvBlockTraits;	typedef GraphTraits<Inverse<BlockT*> > InvBlockTraits;
	for (typename InvBlockTraits::ChildIteratorType I =	for (typename InvBlockTraits::ChildIteratorType I =
	InvBlockTraits::child_begin(BB), E = InvBlockTraits::child_end(BB) ;	InvBlockTraits::child_begin(BB), E = InvBlockTraits::child_end(BB) ;
	I != E; ++I) {	I != E; ++I) {
	typename InvBlockTraits::NodeType N = I;	typename InvBlockTraits::NodeType N = I;

	if (DT.dominates(BB, N)) // If BB dominates its predecessor...	// If BB dominates its predecessor...
		if (DT.dominates(BB, N) && DT.isReachableFromEntry(N))
	TodoStack.push_back(N);	TodoStack.push_back(N);
	}	}

	if (TodoStack.empty()) return 0; // No backedges to this block...	if (TodoStack.empty()) return 0; // No backedges to this block...

	// Create a new loop to represent this basic block...	// Create a new loop to represent this basic block...
	LoopT *L = new LoopT(BB);	LoopT *L = new LoopT(BB);
	BBMap[BB] = L;	BBMap[BB] = L;


	BlockT *EntryBlock = BB->getParent()->begin();

	while (!TodoStack.empty()) { // Process all the nodes in the loop	while (!TodoStack.empty()) { // Process all the nodes in the loop
	BlockT *X = TodoStack.back();	BlockT *X = TodoStack.back();
	TodoStack.pop_back();	TodoStack.pop_back();

	if (!L->contains(X) && // As of yet unprocessed??	if (!L->contains(X) && // As of yet unprocessed??

	DT.dominates(EntryBlock, X)) { // X is reachable from entry blo ck?	DT.isReachableFromEntry(X)) {
	// Check to see if this block already belongs to a loop. If this o ccurs	// Check to see if this block already belongs to a loop. If this o ccurs
	// then we have a case where a loop that is supposed to be a child of	// then we have a case where a loop that is supposed to be a child of
	// the current loop was processed before the current loop. When th is	// the current loop was processed before the current loop. When th is
	// occurs, this child loop gets added to a part of the current loop ,	// occurs, this child loop gets added to a part of the current loop ,
	// making it a sibling to the current loop. We have to reparent th is	// making it a sibling to the current loop. We have to reparent th is
	// loop.	// loop.
	if (LoopT *SubLoop =	if (LoopT *SubLoop =
	const_cast<LoopT *>(getLoopFor(X)))	const_cast<LoopT *>(getLoopFor(X)))
	if (SubLoop->getHeader() == X && isNotAlreadyContainedIn(SubLoop, L)){	if (SubLoop->getHeader() == X && isNotAlreadyContainedIn(SubLoop, L)){
	// Remove the subloop from its current parent...	// Remove the subloop from its current parent...

End of changes. 14 change blocks.
	53 lines changed or deleted	30 lines changed or added

	MCAsmBackend.h	MCAsmBackend.h

	skipping to change at line 15	skipping to change at line 15
	// This file is distributed under the University of Illinois Open Source	// This file is distributed under the University of Illinois Open Source
	// License. See LICENSE.TXT for details.	// License. See LICENSE.TXT for details.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_MC_MCASMBACKEND_H	#ifndef LLVM_MC_MCASMBACKEND_H
	#define LLVM_MC_MCASMBACKEND_H	#define LLVM_MC_MCASMBACKEND_H

	#include "llvm/MC/MCDirectives.h"	#include "llvm/MC/MCDirectives.h"
	#include "llvm/MC/MCFixup.h"	#include "llvm/MC/MCFixup.h"

	#include "llvm/MC/MCFixupKindInfo.h"
	#include "llvm/Support/DataTypes.h"	#include "llvm/Support/DataTypes.h"

		#include "llvm/Support/ErrorHandling.h"

	namespace llvm {	namespace llvm {

		class MCAsmLayout;
		class MCAssembler;
	class MCELFObjectTargetWriter;	class MCELFObjectTargetWriter;

	class MCFixup;	struct MCFixupKindInfo;
		class MCFragment;
	class MCInst;	class MCInst;

		class MCInstFragment;
	class MCObjectWriter;	class MCObjectWriter;
	class MCSection;	class MCSection;

	template<typename T>	class MCValue;
	class SmallVectorImpl;
	class raw_ostream;	class raw_ostream;

	/// MCAsmBackend - Generic interface to target specific assembler backends.	/// MCAsmBackend - Generic interface to target specific assembler backends.
	class MCAsmBackend {	class MCAsmBackend {
	MCAsmBackend(const MCAsmBackend &); // DO NOT IMPLEMENT	MCAsmBackend(const MCAsmBackend &); // DO NOT IMPLEMENT
	void operator=(const MCAsmBackend &); // DO NOT IMPLEMENT	void operator=(const MCAsmBackend &); // DO NOT IMPLEMENT
	protected: // Can only create subclasses.	protected: // Can only create subclasses.
	MCAsmBackend();	MCAsmBackend();

	unsigned HasReliableSymbolDifference : 1;	unsigned HasReliableSymbolDifference : 1;

	skipping to change at line 47	skipping to change at line 50
	public:	public:
	virtual ~MCAsmBackend();	virtual ~MCAsmBackend();

	/// createObjectWriter - Create a new MCObjectWriter instance for use by the	/// createObjectWriter - Create a new MCObjectWriter instance for use by the
	/// assembler backend to emit the final object file.	/// assembler backend to emit the final object file.
	virtual MCObjectWriter *createObjectWriter(raw_ostream &OS) const = 0;	virtual MCObjectWriter *createObjectWriter(raw_ostream &OS) const = 0;

	/// createELFObjectTargetWriter - Create a new ELFObjectTargetWriter to e nable	/// createELFObjectTargetWriter - Create a new ELFObjectTargetWriter to e nable
	/// non-standard ELFObjectWriters.	/// non-standard ELFObjectWriters.
	virtual MCELFObjectTargetWriter *createELFObjectTargetWriter() const {	virtual MCELFObjectTargetWriter *createELFObjectTargetWriter() const {

	assert(0 && "createELFObjectTargetWriter is not supported by asm backen	llvm_unreachable("createELFObjectTargetWriter is not supported by asm "
	d");	"backend");
	return 0;
	}	}

	/// hasReliableSymbolDifference - Check whether this target implements	/// hasReliableSymbolDifference - Check whether this target implements
	/// accurate relocations for differences between symbols. If not, differe nces	/// accurate relocations for differences between symbols. If not, differe nces
	/// between symbols will always be relocatable expressions and any refere nces	/// between symbols will always be relocatable expressions and any refere nces
	/// to temporary symbols will be assumed to be in the same atom, unless t hey	/// to temporary symbols will be assumed to be in the same atom, unless t hey
	/// reside in a different section.	/// reside in a different section.
	///	///
	/// This should always be true (since it results in fewer relocations wit h no	/// This should always be true (since it results in fewer relocations wit h no
	/// loss of functionality), but is currently supported as a way to mainta in	/// loss of functionality), but is currently supported as a way to mainta in

	skipping to change at line 88	skipping to change at line 91

	/// @name Target Fixup Interfaces	/// @name Target Fixup Interfaces
	/// @{	/// @{

	/// getNumFixupKinds - Get the number of target specific fixup kinds.	/// getNumFixupKinds - Get the number of target specific fixup kinds.
	virtual unsigned getNumFixupKinds() const = 0;	virtual unsigned getNumFixupKinds() const = 0;

	/// getFixupKindInfo - Get information on a fixup kind.	/// getFixupKindInfo - Get information on a fixup kind.
	virtual const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const;	virtual const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const;


		/// processFixupValue - Target hook to adjust the literal value of a fixu
		p
		/// if necessary. IsResolved signals whether the caller believes a reloca
		tion
		/// is needed; the target can modify the value. The default does nothing.
		virtual void processFixupValue(const MCAssembler &Asm,
		const MCAsmLayout &Layout,
		const MCFixup &Fixup, const MCFragment *DF
		,
		MCValue &Target, uint64_t &Value,
		bool &IsResolved) {}

	/// @}	/// @}


	/// ApplyFixup - Apply the \arg Value for given \arg Fixup into the provi ded	/// applyFixup - Apply the \arg Value for given \arg Fixup into the provi ded
	/// data fragment, at the offset specified by the fixup and following the	/// data fragment, at the offset specified by the fixup and following the
	/// fixup kind as appropriate.	/// fixup kind as appropriate.

	virtual void ApplyFixup(const MCFixup &Fixup, char *Data, unsigned DataSi ze,	virtual void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSi ze,
	uint64_t Value) const = 0;	uint64_t Value) const = 0;

	/// @}	/// @}

	/// @name Target Relaxation Interfaces	/// @name Target Relaxation Interfaces
	/// @{	/// @{


	/// MayNeedRelaxation - Check whether the given instruction may need	/// mayNeedRelaxation - Check whether the given instruction may need
	/// relaxation.	/// relaxation.
	///	///
	/// \param Inst - The instruction to test.	/// \param Inst - The instruction to test.

	virtual bool MayNeedRelaxation(const MCInst &Inst) const = 0;	virtual bool mayNeedRelaxation(const MCInst &Inst) const = 0;

		/// fixupNeedsRelaxation - Target specific predicate for whether a given
		/// fixup requires the associated instruction to be relaxed.
		virtual bool fixupNeedsRelaxation(const MCFixup &Fixup,
		uint64_t Value,
		const MCInstFragment *DF,
		const MCAsmLayout &Layout) const = 0;

	/// RelaxInstruction - Relax the instruction in the given fragment to the next	/// RelaxInstruction - Relax the instruction in the given fragment to the next
	/// wider instruction.	/// wider instruction.
	///	///
	/// \param Inst - The instruction to relax, which may be the same as the	/// \param Inst - The instruction to relax, which may be the same as the
	/// output.	/// output.
	/// \parm Res [output] - On return, the relaxed instruction.	/// \parm Res [output] - On return, the relaxed instruction.

	virtual void RelaxInstruction(const MCInst &Inst, MCInst &Res) const = 0;	virtual void relaxInstruction(const MCInst &Inst, MCInst &Res) const = 0;

	/// @}	/// @}


	/// WriteNopData - Write an (optimal) nop sequence of Count bytes to the given	/// writeNopData - Write an (optimal) nop sequence of Count bytes to the given
	/// output. If the target cannot generate such a sequence, it should retu rn an	/// output. If the target cannot generate such a sequence, it should retu rn an
	/// error.	/// error.
	///	///
	/// \return - True on success.	/// \return - True on success.

	virtual bool WriteNopData(uint64_t Count, MCObjectWriter *OW) const = 0;	virtual bool writeNopData(uint64_t Count, MCObjectWriter *OW) const = 0;


	/// HandleAssemblerFlag - Handle any target-specific assembler flags.	/// handleAssemblerFlag - Handle any target-specific assembler flags.
	/// By default, do nothing.	/// By default, do nothing.

	virtual void HandleAssemblerFlag(MCAssemblerFlag Flag) {}	virtual void handleAssemblerFlag(MCAssemblerFlag Flag) {}
	};	};

	} // End llvm namespace	} // End llvm namespace

	#endif	#endif

End of changes. 17 change blocks.
	16 lines changed or deleted	37 lines changed or added

	MCAsmInfoCOFF.h	MCAsmInfoCOFF.h

	skipping to change at line 17	skipping to change at line 17
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_COFF_TARGET_ASM_INFO_H	#ifndef LLVM_COFF_TARGET_ASM_INFO_H
	#define LLVM_COFF_TARGET_ASM_INFO_H	#define LLVM_COFF_TARGET_ASM_INFO_H

	#include "llvm/MC/MCAsmInfo.h"	#include "llvm/MC/MCAsmInfo.h"

	namespace llvm {	namespace llvm {
	class MCAsmInfoCOFF : public MCAsmInfo {	class MCAsmInfoCOFF : public MCAsmInfo {

		virtual void anchor();
	protected:	protected:
	explicit MCAsmInfoCOFF();	explicit MCAsmInfoCOFF();

		};


		class MCAsmInfoMicrosoft : public MCAsmInfoCOFF {
		virtual void anchor();
		protected:
		explicit MCAsmInfoMicrosoft();
		};

		class MCAsmInfoGNUCOFF : public MCAsmInfoCOFF {
		virtual void anchor();
		protected:
		explicit MCAsmInfoGNUCOFF();
	};	};
	}	}

	#endif // LLVM_COFF_TARGET_ASM_INFO_H	#endif // LLVM_COFF_TARGET_ASM_INFO_H

End of changes. 3 change blocks.
	0 lines changed or deleted	12 lines changed or added

	MCAsmInfoDarwin.h	MCAsmInfoDarwin.h

	skipping to change at line 21	skipping to change at line 21
	// should take in general on Darwin-based targets	// should take in general on Darwin-based targets
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_DARWIN_TARGET_ASM_INFO_H	#ifndef LLVM_DARWIN_TARGET_ASM_INFO_H
	#define LLVM_DARWIN_TARGET_ASM_INFO_H	#define LLVM_DARWIN_TARGET_ASM_INFO_H

	#include "llvm/MC/MCAsmInfo.h"	#include "llvm/MC/MCAsmInfo.h"

	namespace llvm {	namespace llvm {

	struct MCAsmInfoDarwin : public MCAsmInfo {	class MCAsmInfoDarwin : public MCAsmInfo {
		virtual void anchor();
		public:
	explicit MCAsmInfoDarwin();	explicit MCAsmInfoDarwin();
	};	};
	}	}

	#endif // LLVM_DARWIN_TARGET_ASM_INFO_H	#endif // LLVM_DARWIN_TARGET_ASM_INFO_H

End of changes. 1 change blocks.
	1 lines changed or deleted	3 lines changed or added

	MCAsmLayout.h	MCAsmLayout.h

	skipping to change at line 13	skipping to change at line 13
	// The LLVM Compiler Infrastructure	// The LLVM Compiler Infrastructure
	//	//
	// This file is distributed under the University of Illinois Open Source	// This file is distributed under the University of Illinois Open Source
	// License. See LICENSE.TXT for details.	// License. See LICENSE.TXT for details.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_MC_MCASMLAYOUT_H	#ifndef LLVM_MC_MCASMLAYOUT_H
	#define LLVM_MC_MCASMLAYOUT_H	#define LLVM_MC_MCASMLAYOUT_H


		#include "llvm/ADT/DenseMap.h"
	#include "llvm/ADT/SmallVector.h"	#include "llvm/ADT/SmallVector.h"

	namespace llvm {	namespace llvm {
	class MCAssembler;	class MCAssembler;
	class MCFragment;	class MCFragment;
	class MCSectionData;	class MCSectionData;
	class MCSymbolData;	class MCSymbolData;

	/// Encapsulates the layout of an assembly file at a particular point in ti me.	/// Encapsulates the layout of an assembly file at a particular point in ti me.
	///	///

End of changes. 1 change blocks.
	0 lines changed or deleted	1 lines changed or added

	MCAsmLexer.h	MCAsmLexer.h

	skipping to change at line 18	skipping to change at line 18
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_MC_MCASMLEXER_H	#ifndef LLVM_MC_MCASMLEXER_H
	#define LLVM_MC_MCASMLEXER_H	#define LLVM_MC_MCASMLEXER_H

	#include "llvm/ADT/StringRef.h"	#include "llvm/ADT/StringRef.h"
	#include "llvm/Support/DataTypes.h"	#include "llvm/Support/DataTypes.h"
	#include "llvm/Support/SMLoc.h"	#include "llvm/Support/SMLoc.h"

	namespace llvm {	namespace llvm {

	class MCAsmLexer;
	class MCInst;

	/// AsmToken - Target independent representation for an assembler token.	/// AsmToken - Target independent representation for an assembler token.
	class AsmToken {	class AsmToken {
	public:	public:
	enum TokenKind {	enum TokenKind {
	// Markers	// Markers
	Eof, Error,	Eof, Error,

	// String values.	// String values.
	Identifier,	Identifier,

	skipping to change at line 56	skipping to change at line 54
	BackSlash, // '\'	BackSlash, // '\'
	LParen, RParen, LBrac, RBrac, LCurly, RCurly,	LParen, RParen, LBrac, RBrac, LCurly, RCurly,
	Star, Dot, Comma, Dollar, Equal, EqualEqual,	Star, Dot, Comma, Dollar, Equal, EqualEqual,

	Pipe, PipePipe, Caret,	Pipe, PipePipe, Caret,
	Amp, AmpAmp, Exclaim, ExclaimEqual, Percent, Hash,	Amp, AmpAmp, Exclaim, ExclaimEqual, Percent, Hash,
	Less, LessEqual, LessLess, LessGreater,	Less, LessEqual, LessLess, LessGreater,
	Greater, GreaterEqual, GreaterGreater, At	Greater, GreaterEqual, GreaterGreater, At
	};	};


		private:
	TokenKind Kind;	TokenKind Kind;

	/// A reference to the entire token contents; this is always a pointer in to	/// A reference to the entire token contents; this is always a pointer in to
	/// a memory buffer owned by the source manager.	/// a memory buffer owned by the source manager.
	StringRef Str;	StringRef Str;

	int64_t IntVal;	int64_t IntVal;

	public:	public:
	AsmToken() {}	AsmToken() {}
	AsmToken(TokenKind _Kind, StringRef _Str, int64_t _IntVal = 0)	AsmToken(TokenKind _Kind, StringRef _Str, int64_t _IntVal = 0)
	: Kind(_Kind), Str(_Str), IntVal(_IntVal) {}	: Kind(_Kind), Str(_Str), IntVal(_IntVal) {}

	TokenKind getKind() const { return Kind; }	TokenKind getKind() const { return Kind; }
	bool is(TokenKind K) const { return Kind == K; }	bool is(TokenKind K) const { return Kind == K; }
	bool isNot(TokenKind K) const { return Kind != K; }	bool isNot(TokenKind K) const { return Kind != K; }

	SMLoc getLoc() const;	SMLoc getLoc() const;

		SMLoc getEndLoc() const;

	/// getStringContents - Get the contents of a string token (without quote s).	/// getStringContents - Get the contents of a string token (without quote s).
	StringRef getStringContents() const {	StringRef getStringContents() const {
	assert(Kind == String && "This token isn't a string!");	assert(Kind == String && "This token isn't a string!");
	return Str.slice(1, Str.size() - 1);	return Str.slice(1, Str.size() - 1);
	}	}

	/// getIdentifier - Get the identifier string for the current token, whic h	/// getIdentifier - Get the identifier string for the current token, whic h
	/// should be an identifier or a string. This gets the portion of the str ing	/// should be an identifier or a string. This gets the portion of the str ing
	/// which should be used as the identifier, e.g., it does not include the	/// which should be used as the identifier, e.g., it does not include the

End of changes. 3 change blocks.
	2 lines changed or deleted	2 lines changed or added

	MCAsmParser.h	MCAsmParser.h

	skipping to change at line 14	skipping to change at line 14
	//	//
	// This file is distributed under the University of Illinois Open Source	// This file is distributed under the University of Illinois Open Source
	// License. See LICENSE.TXT for details.	// License. See LICENSE.TXT for details.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_MC_MCASMPARSER_H	#ifndef LLVM_MC_MCASMPARSER_H
	#define LLVM_MC_MCASMPARSER_H	#define LLVM_MC_MCASMPARSER_H

	#include "llvm/Support/DataTypes.h"	#include "llvm/Support/DataTypes.h"

		#include "llvm/ADT/ArrayRef.h"

	namespace llvm {	namespace llvm {
	class AsmToken;	class AsmToken;
	class MCAsmInfo;	class MCAsmInfo;
	class MCAsmLexer;	class MCAsmLexer;
	class MCAsmParserExtension;	class MCAsmParserExtension;
	class MCContext;	class MCContext;
	class MCExpr;	class MCExpr;
	class MCStreamer;	class MCStreamer;
	class MCTargetAsmParser;	class MCTargetAsmParser;
	class SMLoc;	class SMLoc;

		class SMRange;
	class SourceMgr;	class SourceMgr;
	class StringRef;	class StringRef;
	class Twine;	class Twine;

	/// MCAsmParser - Generic assembler parser interface, for use by target spe cific	/// MCAsmParser - Generic assembler parser interface, for use by target spe cific
	/// assembly parsers.	/// assembly parsers.
	class MCAsmParser {	class MCAsmParser {
	public:	public:
	typedef bool (DirectiveHandler)(MCAsmParserExtension, StringRef, SMLoc) ;	typedef bool (DirectiveHandler)(MCAsmParserExtension, StringRef, SMLoc) ;


	skipping to change at line 65	skipping to change at line 67
	virtual MCAsmLexer &getLexer() = 0;	virtual MCAsmLexer &getLexer() = 0;

	virtual MCContext &getContext() = 0;	virtual MCContext &getContext() = 0;

	/// getStreamer - Return the output streamer for the assembler.	/// getStreamer - Return the output streamer for the assembler.
	virtual MCStreamer &getStreamer() = 0;	virtual MCStreamer &getStreamer() = 0;

	MCTargetAsmParser &getTargetParser() const { return *TargetParser; }	MCTargetAsmParser &getTargetParser() const { return *TargetParser; }
	void setTargetParser(MCTargetAsmParser &P);	void setTargetParser(MCTargetAsmParser &P);


		virtual unsigned getAssemblerDialect() { return 0;}
		virtual void setAssemblerDialect(unsigned i) { }

	bool getShowParsedOperands() const { return ShowParsedOperands; }	bool getShowParsedOperands() const { return ShowParsedOperands; }
	void setShowParsedOperands(bool Value) { ShowParsedOperands = Value; }	void setShowParsedOperands(bool Value) { ShowParsedOperands = Value; }

	/// Run - Run the parser on the input source buffer.	/// Run - Run the parser on the input source buffer.
	virtual bool Run(bool NoInitialTextSection, bool NoFinalize = false) = 0;	virtual bool Run(bool NoInitialTextSection, bool NoFinalize = false) = 0;

	/// Warning - Emit a warning at the location \arg L, with the message \ar g	/// Warning - Emit a warning at the location \arg L, with the message \ar g
	/// Msg.	/// Msg.
	///	///
	/// \return The return value is true, if warnings are fatal.	/// \return The return value is true, if warnings are fatal.

	virtual bool Warning(SMLoc L, const Twine &Msg) = 0;	virtual bool Warning(SMLoc L, const Twine &Msg,
		ArrayRef<SMRange> Ranges = ArrayRef<SMRange>()) = 0;

	/// Error - Emit an error at the location \arg L, with the message \arg	/// Error - Emit an error at the location \arg L, with the message \arg
	/// Msg.	/// Msg.
	///	///
	/// \return The return value is always true, as an idiomatic convenience to	/// \return The return value is always true, as an idiomatic convenience to
	/// clients.	/// clients.

	virtual bool Error(SMLoc L, const Twine &Msg) = 0;	virtual bool Error(SMLoc L, const Twine &Msg,
		ArrayRef<SMRange> Ranges = ArrayRef<SMRange>()) = 0;

	/// Lex - Get the next AsmToken in the stream, possibly handling file	/// Lex - Get the next AsmToken in the stream, possibly handling file
	/// inclusion first.	/// inclusion first.
	virtual const AsmToken &Lex() = 0;	virtual const AsmToken &Lex() = 0;

	/// getTok - Get the current AsmToken from the stream.	/// getTok - Get the current AsmToken from the stream.
	const AsmToken &getTok();	const AsmToken &getTok();

	/// \brief Report an error at the current lexer location.	/// \brief Report an error at the current lexer location.

	bool TokError(const Twine &Msg);	bool TokError(const Twine &Msg,
		ArrayRef<SMRange> Ranges = ArrayRef<SMRange>());

	/// ParseIdentifier - Parse an identifier or string (as a quoted identifi er)	/// ParseIdentifier - Parse an identifier or string (as a quoted identifi er)
	/// and set \arg Res to the identifier contents.	/// and set \arg Res to the identifier contents.
	virtual bool ParseIdentifier(StringRef &Res) = 0;	virtual bool ParseIdentifier(StringRef &Res) = 0;

	/// \brief Parse up to the end of statement and return the contents from the	/// \brief Parse up to the end of statement and return the contents from the
	/// current token until the end of the statement; the current token on ex it	/// current token until the end of the statement; the current token on ex it
	/// will be either the EndOfStatement or EOF.	/// will be either the EndOfStatement or EOF.
	virtual StringRef ParseStringToEndOfStatement() = 0;	virtual StringRef ParseStringToEndOfStatement() = 0;


End of changes. 6 change blocks.
	3 lines changed or deleted	11 lines changed or added

	MCAssembler.h	MCAssembler.h

	skipping to change at line 28	skipping to change at line 28
	#include "llvm/ADT/ilist.h"	#include "llvm/ADT/ilist.h"
	#include "llvm/ADT/ilist_node.h"	#include "llvm/ADT/ilist_node.h"
	#include "llvm/Support/Casting.h"	#include "llvm/Support/Casting.h"
	#include "llvm/Support/DataTypes.h"	#include "llvm/Support/DataTypes.h"
	#include <vector> // FIXME: Shouldn't be needed.	#include <vector> // FIXME: Shouldn't be needed.

	namespace llvm {	namespace llvm {
	class raw_ostream;	class raw_ostream;
	class MCAsmLayout;	class MCAsmLayout;
	class MCAssembler;	class MCAssembler;

	class MCBinaryExpr;
	class MCContext;	class MCContext;
	class MCCodeEmitter;	class MCCodeEmitter;
	class MCExpr;	class MCExpr;
	class MCFragment;	class MCFragment;
	class MCObjectWriter;	class MCObjectWriter;
	class MCSection;	class MCSection;
	class MCSectionData;	class MCSectionData;
	class MCSymbol;	class MCSymbol;
	class MCSymbolData;	class MCSymbolData;
	class MCValue;	class MCValue;

	skipping to change at line 109	skipping to change at line 108

	unsigned getLayoutOrder() const { return LayoutOrder; }	unsigned getLayoutOrder() const { return LayoutOrder; }
	void setLayoutOrder(unsigned Value) { LayoutOrder = Value; }	void setLayoutOrder(unsigned Value) { LayoutOrder = Value; }

	static bool classof(const MCFragment *O) { return true; }	static bool classof(const MCFragment *O) { return true; }

	void dump();	void dump();
	};	};

	class MCDataFragment : public MCFragment {	class MCDataFragment : public MCFragment {

		virtual void anchor();
	SmallString<32> Contents;	SmallString<32> Contents;

	/// Fixups - The list of fixups in this fragment.	/// Fixups - The list of fixups in this fragment.
	std::vector<MCFixup> Fixups;	std::vector<MCFixup> Fixups;

	public:	public:
	typedef std::vector<MCFixup>::const_iterator const_fixup_iterator;	typedef std::vector<MCFixup>::const_iterator const_fixup_iterator;
	typedef std::vector<MCFixup>::iterator fixup_iterator;	typedef std::vector<MCFixup>::iterator fixup_iterator;

	public:	public:

	skipping to change at line 163	skipping to change at line 163
	}	}
	static bool classof(const MCDataFragment *) { return true; }	static bool classof(const MCDataFragment *) { return true; }
	};	};

	// FIXME: This current incarnation of MCInstFragment doesn't make much sens e, as	// FIXME: This current incarnation of MCInstFragment doesn't make much sens e, as
	// it is almost entirely a duplicate of MCDataFragment. If we decide to sti ck	// it is almost entirely a duplicate of MCDataFragment. If we decide to sti ck
	// with this approach (as opposed to making MCInstFragment a very light wei ght	// with this approach (as opposed to making MCInstFragment a very light wei ght
	// object with just the MCInst and a code size, then we should just change	// object with just the MCInst and a code size, then we should just change
	// MCDataFragment to have an optional MCInst at its end.	// MCDataFragment to have an optional MCInst at its end.
	class MCInstFragment : public MCFragment {	class MCInstFragment : public MCFragment {

		virtual void anchor();

	/// Inst - The instruction this is a fragment for.	/// Inst - The instruction this is a fragment for.
	MCInst Inst;	MCInst Inst;

	/// Code - Binary data for the currently encoded instruction.	/// Code - Binary data for the currently encoded instruction.
	SmallString<8> Code;	SmallString<8> Code;

	/// Fixups - The list of fixups in this fragment.	/// Fixups - The list of fixups in this fragment.
	SmallVector<MCFixup, 1> Fixups;	SmallVector<MCFixup, 1> Fixups;

	public:	public:

	skipping to change at line 218	skipping to change at line 220

	/// @}	/// @}

	static bool classof(const MCFragment *F) {	static bool classof(const MCFragment *F) {
	return F->getKind() == MCFragment::FT_Inst;	return F->getKind() == MCFragment::FT_Inst;
	}	}
	static bool classof(const MCInstFragment *) { return true; }	static bool classof(const MCInstFragment *) { return true; }
	};	};

	class MCAlignFragment : public MCFragment {	class MCAlignFragment : public MCFragment {

		virtual void anchor();

	/// Alignment - The alignment to ensure, in bytes.	/// Alignment - The alignment to ensure, in bytes.
	unsigned Alignment;	unsigned Alignment;

	/// Value - Value to use for filling padding bytes.	/// Value - Value to use for filling padding bytes.
	int64_t Value;	int64_t Value;

	/// ValueSize - The size of the integer (in bytes) of \arg Value.	/// ValueSize - The size of the integer (in bytes) of \arg Value.
	unsigned ValueSize;	unsigned ValueSize;

	/// MaxBytesToEmit - The maximum number of bytes to emit; if the alignmen t	/// MaxBytesToEmit - The maximum number of bytes to emit; if the alignmen t

	skipping to change at line 266	skipping to change at line 270

	/// @}	/// @}

	static bool classof(const MCFragment *F) {	static bool classof(const MCFragment *F) {
	return F->getKind() == MCFragment::FT_Align;	return F->getKind() == MCFragment::FT_Align;
	}	}
	static bool classof(const MCAlignFragment *) { return true; }	static bool classof(const MCAlignFragment *) { return true; }
	};	};

	class MCFillFragment : public MCFragment {	class MCFillFragment : public MCFragment {

		virtual void anchor();

	/// Value - Value to use for filling bytes.	/// Value - Value to use for filling bytes.
	int64_t Value;	int64_t Value;

	/// ValueSize - The size (in bytes) of \arg Value to use when filling, or 0 if	/// ValueSize - The size (in bytes) of \arg Value to use when filling, or 0 if
	/// this is a virtual fill fragment.	/// this is a virtual fill fragment.
	unsigned ValueSize;	unsigned ValueSize;

	/// Size - The number of bytes to insert.	/// Size - The number of bytes to insert.
	uint64_t Size;	uint64_t Size;


	skipping to change at line 303	skipping to change at line 309

	/// @}	/// @}

	static bool classof(const MCFragment *F) {	static bool classof(const MCFragment *F) {
	return F->getKind() == MCFragment::FT_Fill;	return F->getKind() == MCFragment::FT_Fill;
	}	}
	static bool classof(const MCFillFragment *) { return true; }	static bool classof(const MCFillFragment *) { return true; }
	};	};

	class MCOrgFragment : public MCFragment {	class MCOrgFragment : public MCFragment {

		virtual void anchor();

	/// Offset - The offset this fragment should start at.	/// Offset - The offset this fragment should start at.
	const MCExpr *Offset;	const MCExpr *Offset;

	/// Value - Value to use for filling bytes.	/// Value - Value to use for filling bytes.
	int8_t Value;	int8_t Value;

	public:	public:
	MCOrgFragment(const MCExpr &_Offset, int8_t _Value, MCSectionData *SD = 0 )	MCOrgFragment(const MCExpr &_Offset, int8_t _Value, MCSectionData *SD = 0 )
	: MCFragment(FT_Org, SD),	: MCFragment(FT_Org, SD),
	Offset(&_Offset), Value(_Value) {}	Offset(&_Offset), Value(_Value) {}

	skipping to change at line 330	skipping to change at line 338

	/// @}	/// @}

	static bool classof(const MCFragment *F) {	static bool classof(const MCFragment *F) {
	return F->getKind() == MCFragment::FT_Org;	return F->getKind() == MCFragment::FT_Org;
	}	}
	static bool classof(const MCOrgFragment *) { return true; }	static bool classof(const MCOrgFragment *) { return true; }
	};	};

	class MCLEBFragment : public MCFragment {	class MCLEBFragment : public MCFragment {

		virtual void anchor();

	/// Value - The value this fragment should contain.	/// Value - The value this fragment should contain.
	const MCExpr *Value;	const MCExpr *Value;

	/// IsSigned - True if this is a sleb128, false if uleb128.	/// IsSigned - True if this is a sleb128, false if uleb128.
	bool IsSigned;	bool IsSigned;

	SmallString<8> Contents;	SmallString<8> Contents;
	public:	public:
	MCLEBFragment(const MCExpr &Value_, bool IsSigned_, MCSectionData *SD)	MCLEBFragment(const MCExpr &Value_, bool IsSigned_, MCSectionData *SD)
	: MCFragment(FT_LEB, SD),	: MCFragment(FT_LEB, SD),

	skipping to change at line 361	skipping to change at line 371

	/// @}	/// @}

	static bool classof(const MCFragment *F) {	static bool classof(const MCFragment *F) {
	return F->getKind() == MCFragment::FT_LEB;	return F->getKind() == MCFragment::FT_LEB;
	}	}
	static bool classof(const MCLEBFragment *) { return true; }	static bool classof(const MCLEBFragment *) { return true; }
	};	};

	class MCDwarfLineAddrFragment : public MCFragment {	class MCDwarfLineAddrFragment : public MCFragment {

		virtual void anchor();

	/// LineDelta - the value of the difference between the two line numbers	/// LineDelta - the value of the difference between the two line numbers
	/// between two .loc dwarf directives.	/// between two .loc dwarf directives.
	int64_t LineDelta;	int64_t LineDelta;

	/// AddrDelta - The expression for the difference of the two symbols that	/// AddrDelta - The expression for the difference of the two symbols that
	/// make up the address delta between two .loc dwarf directives.	/// make up the address delta between two .loc dwarf directives.
	const MCExpr *AddrDelta;	const MCExpr *AddrDelta;

	SmallString<8> Contents;	SmallString<8> Contents;


	skipping to change at line 396	skipping to change at line 408

	/// @}	/// @}

	static bool classof(const MCFragment *F) {	static bool classof(const MCFragment *F) {
	return F->getKind() == MCFragment::FT_Dwarf;	return F->getKind() == MCFragment::FT_Dwarf;
	}	}
	static bool classof(const MCDwarfLineAddrFragment *) { return true; }	static bool classof(const MCDwarfLineAddrFragment *) { return true; }
	};	};

	class MCDwarfCallFrameFragment : public MCFragment {	class MCDwarfCallFrameFragment : public MCFragment {

		virtual void anchor();

	/// AddrDelta - The expression for the difference of the two symbols that	/// AddrDelta - The expression for the difference of the two symbols that
	/// make up the address delta between two .cfi_* dwarf directives.	/// make up the address delta between two .cfi_* dwarf directives.
	const MCExpr *AddrDelta;	const MCExpr *AddrDelta;

	SmallString<8> Contents;	SmallString<8> Contents;

	public:	public:
	MCDwarfCallFrameFragment(const MCExpr &_AddrDelta, MCSectionData *SD)	MCDwarfCallFrameFragment(const MCExpr &_AddrDelta, MCSectionData *SD)
	: MCFragment(FT_DwarfFrame, SD),	: MCFragment(FT_DwarfFrame, SD),
	AddrDelta(&_AddrDelta) { Contents.push_back(0); }	AddrDelta(&_AddrDelta) { Contents.push_back(0); }

	skipping to change at line 713	skipping to change at line 727
	/// \param Layout The layout to use for evaluation.	/// \param Layout The layout to use for evaluation.
	/// \param Fixup The fixup to evaluate.	/// \param Fixup The fixup to evaluate.
	/// \param DF The fragment the fixup is inside.	/// \param DF The fragment the fixup is inside.
	/// \param Target [out] On return, the relocatable expression the fixup	/// \param Target [out] On return, the relocatable expression the fixup
	/// evaluates to.	/// evaluates to.
	/// \param Value [out] On return, the value of the fixup as currently lai d	/// \param Value [out] On return, the value of the fixup as currently lai d
	/// out.	/// out.
	/// \return Whether the fixup value was fully resolved. This is true if t he	/// \return Whether the fixup value was fully resolved. This is true if t he
	/// \arg Value result is fixed, otherwise the value may change due to	/// \arg Value result is fixed, otherwise the value may change due to
	/// relocation.	/// relocation.

	bool EvaluateFixup(const MCAsmLayout &Layout,	bool evaluateFixup(const MCAsmLayout &Layout,
	const MCFixup &Fixup, const MCFragment *DF,	const MCFixup &Fixup, const MCFragment *DF,
	MCValue &Target, uint64_t &Value) const;	MCValue &Target, uint64_t &Value) const;

	/// Check whether a fixup can be satisfied, or whether it needs to be rel axed	/// Check whether a fixup can be satisfied, or whether it needs to be rel axed
	/// (increased in size, in order to hold its value correctly).	/// (increased in size, in order to hold its value correctly).

	bool FixupNeedsRelaxation(const MCFixup &Fixup, const MCFragment *DF,	bool fixupNeedsRelaxation(const MCFixup &Fixup, const MCInstFragment *DF,
	const MCAsmLayout &Layout) const;	const MCAsmLayout &Layout) const;

	/// Check whether the given fragment needs relaxation.	/// Check whether the given fragment needs relaxation.

	bool FragmentNeedsRelaxation(const MCInstFragment *IF,	bool fragmentNeedsRelaxation(const MCInstFragment *IF,
	const MCAsmLayout &Layout) const;	const MCAsmLayout &Layout) const;


	/// LayoutOnce - Perform one layout iteration and return true if any offs ets	/// layoutOnce - Perform one layout iteration and return true if any offs ets
	/// were adjusted.	/// were adjusted.

	bool LayoutOnce(MCAsmLayout &Layout);	bool layoutOnce(MCAsmLayout &Layout);


	bool LayoutSectionOnce(MCAsmLayout &Layout, MCSectionData &SD);	bool layoutSectionOnce(MCAsmLayout &Layout, MCSectionData &SD);


	bool RelaxInstruction(MCAsmLayout &Layout, MCInstFragment &IF);	bool relaxInstruction(MCAsmLayout &Layout, MCInstFragment &IF);


	bool RelaxLEB(MCAsmLayout &Layout, MCLEBFragment &IF);	bool relaxLEB(MCAsmLayout &Layout, MCLEBFragment &IF);


	bool RelaxDwarfLineAddr(MCAsmLayout &Layout, MCDwarfLineAddrFragment &DF)	bool relaxDwarfLineAddr(MCAsmLayout &Layout, MCDwarfLineAddrFragment &DF)
	;	;
	bool RelaxDwarfCallFrameFragment(MCAsmLayout &Layout,	bool relaxDwarfCallFrameFragment(MCAsmLayout &Layout,
	MCDwarfCallFrameFragment &DF);	MCDwarfCallFrameFragment &DF);


	/// FinishLayout - Finalize a layout, including fragment lowering.	/// finishLayout - Finalize a layout, including fragment lowering.
	void FinishLayout(MCAsmLayout &Layout);	void finishLayout(MCAsmLayout &Layout);


	uint64_t HandleFixup(const MCAsmLayout &Layout,	uint64_t handleFixup(const MCAsmLayout &Layout,
	MCFragment &F, const MCFixup &Fixup);	MCFragment &F, const MCFixup &Fixup);

	public:	public:
	/// Compute the effective fragment size assuming it is laid out at the gi ven	/// Compute the effective fragment size assuming it is laid out at the gi ven
	/// \arg SectionAddress and \arg FragmentOffset.	/// \arg SectionAddress and \arg FragmentOffset.

	uint64_t ComputeFragmentSize(const MCAsmLayout &Layout, const MCFragment	uint64_t computeFragmentSize(const MCAsmLayout &Layout,
	&F) const;	const MCFragment &F) const;

	/// Find the symbol which defines the atom containing the given symbol, o r	/// Find the symbol which defines the atom containing the given symbol, o r
	/// null if there is no such symbol.	/// null if there is no such symbol.
	const MCSymbolData getAtom(const MCSymbolData Symbol) const;	const MCSymbolData getAtom(const MCSymbolData Symbol) const;

	/// Check whether a particular symbol is visible to the linker and is req uired	/// Check whether a particular symbol is visible to the linker and is req uired
	/// in the symbol table, or whether it can be discarded by the assembler. This	/// in the symbol table, or whether it can be discarded by the assembler. This
	/// also effects whether the assembler treats the label as potentially	/// also effects whether the assembler treats the label as potentially
	/// defining a separate atom.	/// defining a separate atom.
	bool isSymbolLinkerVisible(const MCSymbol &SD) const;	bool isSymbolLinkerVisible(const MCSymbol &SD) const;

	/// Emit the section contents using the given object writer.	/// Emit the section contents using the given object writer.

	void WriteSectionData(const MCSectionData *Section,	void writeSectionData(const MCSectionData *Section,
	const MCAsmLayout &Layout) const;	const MCAsmLayout &Layout) const;

	/// Check whether a given symbol has been flagged with .thumb_func.	/// Check whether a given symbol has been flagged with .thumb_func.
	bool isThumbFunc(const MCSymbol *Func) const {	bool isThumbFunc(const MCSymbol *Func) const {
	return ThumbFuncs.count(Func);	return ThumbFuncs.count(Func);
	}	}

	/// Flag a function symbol as the target of a .thumb_func directive.	/// Flag a function symbol as the target of a .thumb_func directive.
	void setIsThumbFunc(const MCSymbol *Func) { ThumbFuncs.insert(Func); }	void setIsThumbFunc(const MCSymbol *Func) { ThumbFuncs.insert(Func); }


End of changes. 22 change blocks.
	18 lines changed or deleted	32 lines changed or added

	MCCodeEmitter.h	MCCodeEmitter.h

	skipping to change at line 13	skipping to change at line 13
	// The LLVM Compiler Infrastructure	// The LLVM Compiler Infrastructure
	//	//
	// This file is distributed under the University of Illinois Open Source	// This file is distributed under the University of Illinois Open Source
	// License. See LICENSE.TXT for details.	// License. See LICENSE.TXT for details.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_MC_MCCODEEMITTER_H	#ifndef LLVM_MC_MCCODEEMITTER_H
	#define LLVM_MC_MCCODEEMITTER_H	#define LLVM_MC_MCCODEEMITTER_H


	#include "llvm/MC/MCFixup.h"

	#include <cassert>

	namespace llvm {	namespace llvm {

	class MCExpr;	class MCFixup;
	class MCInst;	class MCInst;
	class raw_ostream;	class raw_ostream;
	template<typename T> class SmallVectorImpl;	template<typename T> class SmallVectorImpl;

	/// MCCodeEmitter - Generic instruction encoding interface.	/// MCCodeEmitter - Generic instruction encoding interface.
	class MCCodeEmitter {	class MCCodeEmitter {
	private:	private:
	MCCodeEmitter(const MCCodeEmitter &); // DO NOT IMPLEMENT	MCCodeEmitter(const MCCodeEmitter &); // DO NOT IMPLEMENT
	void operator=(const MCCodeEmitter &); // DO NOT IMPLEMENT	void operator=(const MCCodeEmitter &); // DO NOT IMPLEMENT
	protected: // Can only create subclasses.	protected: // Can only create subclasses.

End of changes. 2 change blocks.
	5 lines changed or deleted	1 lines changed or added

	MCCodeGenInfo.h	MCCodeGenInfo.h

	skipping to change at line 23	skipping to change at line 23
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_MC_MCCODEGENINFO_H	#ifndef LLVM_MC_MCCODEGENINFO_H
	#define LLVM_MC_MCCODEGENINFO_H	#define LLVM_MC_MCCODEGENINFO_H

	#include "llvm/Support/CodeGen.h"	#include "llvm/Support/CodeGen.h"

	namespace llvm {	namespace llvm {

	class MCCodeGenInfo {	class MCCodeGenInfo {

	/// RelocationModel - Relocation model: statcic, pic, etc.	/// RelocationModel - Relocation model: static, pic, etc.
	///	///
	Reloc::Model RelocationModel;	Reloc::Model RelocationModel;

	/// CMModel - Code model.	/// CMModel - Code model.
	///	///
	CodeModel::Model CMModel;	CodeModel::Model CMModel;


		/// OptLevel - Optimization level.
		///
		CodeGenOpt::Level OptLevel;

	public:	public:
	void InitMCCodeGenInfo(Reloc::Model RM = Reloc::Default,	void InitMCCodeGenInfo(Reloc::Model RM = Reloc::Default,

	CodeModel::Model CM = CodeModel::Default);	CodeModel::Model CM = CodeModel::Default,
		CodeGenOpt::Level OL = CodeGenOpt::Default);

	Reloc::Model getRelocationModel() const { return RelocationModel; }	Reloc::Model getRelocationModel() const { return RelocationModel; }

	CodeModel::Model getCodeModel() const { return CMModel; }	CodeModel::Model getCodeModel() const { return CMModel; }


		CodeGenOpt::Level getOptLevel() const { return OptLevel; }
	};	};
	} // namespace llvm	} // namespace llvm

	#endif	#endif

End of changes. 4 change blocks.
	2 lines changed or deleted	9 lines changed or added

	MCContext.h	MCContext.h

	skipping to change at line 18	skipping to change at line 18
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_MC_MCCONTEXT_H	#ifndef LLVM_MC_MCCONTEXT_H
	#define LLVM_MC_MCCONTEXT_H	#define LLVM_MC_MCCONTEXT_H

	#include "llvm/MC/SectionKind.h"	#include "llvm/MC/SectionKind.h"
	#include "llvm/MC/MCDwarf.h"	#include "llvm/MC/MCDwarf.h"
	#include "llvm/ADT/DenseMap.h"	#include "llvm/ADT/DenseMap.h"
	#include "llvm/ADT/StringMap.h"	#include "llvm/ADT/StringMap.h"
	#include "llvm/Support/Allocator.h"	#include "llvm/Support/Allocator.h"

		#include "llvm/Support/Compiler.h"
	#include "llvm/Support/raw_ostream.h"	#include "llvm/Support/raw_ostream.h"
	#include <vector> // FIXME: Shouldn't be needed.	#include <vector> // FIXME: Shouldn't be needed.

	namespace llvm {	namespace llvm {
	class MCAsmInfo;	class MCAsmInfo;
	class MCExpr;	class MCExpr;
	class MCSection;	class MCSection;
	class MCSymbol;	class MCSymbol;
	class MCLabel;	class MCLabel;
	class MCDwarfFile;	class MCDwarfFile;
	class MCDwarfLoc;	class MCDwarfLoc;
	class MCObjectFileInfo;	class MCObjectFileInfo;
	class MCRegisterInfo;	class MCRegisterInfo;
	class MCLineSection;	class MCLineSection;

		class SMLoc;
	class StringRef;	class StringRef;
	class Twine;	class Twine;
	class MCSectionMachO;	class MCSectionMachO;
	class MCSectionELF;	class MCSectionELF;

	/// MCContext - Context object for machine code objects. This class owns all	/// MCContext - Context object for machine code objects. This class owns all
	/// of the sections that it creates.	/// of the sections that it creates.
	///	///
	class MCContext {	class MCContext {
	MCContext(const MCContext&); // DO NOT IMPLEMENT	MCContext(const MCContext&); // DO NOT IMPLEMENT
	MCContext &operator=(const MCContext&); // DO NOT IMPLEMENT	MCContext &operator=(const MCContext&); // DO NOT IMPLEMENT
	public:	public:
	typedef StringMap<MCSymbol*, BumpPtrAllocator&> SymbolTable;	typedef StringMap<MCSymbol*, BumpPtrAllocator&> SymbolTable;
	private:	private:

		/// The SourceMgr for this object, if any.
		const SourceMgr *SrcMgr;

	/// The MCAsmInfo for this target.	/// The MCAsmInfo for this target.
	const MCAsmInfo &MAI;	const MCAsmInfo &MAI;

	/// The MCRegisterInfo for this target.	/// The MCRegisterInfo for this target.
	const MCRegisterInfo &MRI;	const MCRegisterInfo &MRI;

	/// The MCObjectFileInfo for this target.	/// The MCObjectFileInfo for this target.
	const MCObjectFileInfo *MOFI;	const MCObjectFileInfo *MOFI;


	skipping to change at line 101	skipping to change at line 105
	bool SecureLogUsed;	bool SecureLogUsed;

	/// The dwarf file and directory tables from the dwarf .file directive.	/// The dwarf file and directory tables from the dwarf .file directive.
	std::vector<MCDwarfFile *> MCDwarfFiles;	std::vector<MCDwarfFile *> MCDwarfFiles;
	std::vector<StringRef> MCDwarfDirs;	std::vector<StringRef> MCDwarfDirs;

	/// The current dwarf line information from the last dwarf .loc directi ve.	/// The current dwarf line information from the last dwarf .loc directi ve.
	MCDwarfLoc CurrentDwarfLoc;	MCDwarfLoc CurrentDwarfLoc;
	bool DwarfLocSeen;	bool DwarfLocSeen;


		/// Generate dwarf debugging info for assembly source files.
		bool GenDwarfForAssembly;

		/// The current dwarf file number when generate dwarf debugging info fo
		r
		/// assembly source files.
		unsigned GenDwarfFileNumber;

		/// The default initial text section that we generate dwarf debugging l
		ine
		/// info for when generating dwarf assembly source files.
		const MCSection *GenDwarfSection;
		/// Symbols created for the start and end of this section.
		MCSymbol GenDwarfSectionStartSym, GenDwarfSectionEndSym;

		/// The information gathered from labels that will have dwarf label
		/// entries when generating dwarf assembly source files.
		std::vector<const MCGenDwarfLabelEntry *> MCGenDwarfLabelEntries;

		/// The string to embed in the debug information for the compile unit,
		if
		/// non-empty.
		StringRef DwarfDebugFlags;

	/// Honor temporary labels, this is useful for debugging semantic	/// Honor temporary labels, this is useful for debugging semantic
	/// differences between temporary and non-temporary labels (primarily o n	/// differences between temporary and non-temporary labels (primarily o n
	/// Darwin).	/// Darwin).
	bool AllowTemporaryLabels;	bool AllowTemporaryLabels;

	/// The dwarf line information from the .loc directives for the section s	/// The dwarf line information from the .loc directives for the section s
	/// with assembled machine instructions have after seeing .loc directiv es.	/// with assembled machine instructions have after seeing .loc directiv es.
	DenseMap<const MCSection , MCLineSection > MCLineSections;	DenseMap<const MCSection , MCLineSection > MCLineSections;
	/// We need a deterministic iteration order, so we remember the order	/// We need a deterministic iteration order, so we remember the order
	/// the elements were added.	/// the elements were added.
	std::vector<const MCSection *> MCLineSectionOrder;	std::vector<const MCSection *> MCLineSectionOrder;

	void MachOUniquingMap, ELFUniquingMap, *COFFUniquingMap;	void MachOUniquingMap, ELFUniquingMap, *COFFUniquingMap;

	MCSymbol *CreateSymbol(StringRef Name);	MCSymbol *CreateSymbol(StringRef Name);

	public:	public:
	explicit MCContext(const MCAsmInfo &MAI, const MCRegisterInfo &MRI,	explicit MCContext(const MCAsmInfo &MAI, const MCRegisterInfo &MRI,

	const MCObjectFileInfo *MOFI);	const MCObjectFileInfo MOFI, const SourceMgr Mgr = 0);
	~MCContext();	~MCContext();


		const SourceMgr *getSourceManager() const { return SrcMgr; }

	const MCAsmInfo &getAsmInfo() const { return MAI; }	const MCAsmInfo &getAsmInfo() const { return MAI; }

	const MCRegisterInfo &getRegisterInfo() const { return MRI; }	const MCRegisterInfo &getRegisterInfo() const { return MRI; }

	const MCObjectFileInfo *getObjectFileInfo() const { return MOFI; }	const MCObjectFileInfo *getObjectFileInfo() const { return MOFI; }

	void setAllowTemporaryLabels(bool Value) { AllowTemporaryLabels = Value ; }	void setAllowTemporaryLabels(bool Value) { AllowTemporaryLabels = Value ; }

	/// @name Symbol Management	/// @name Symbol Management
	/// @{	/// @{

	skipping to change at line 206	skipping to change at line 233
	SectionKind Kind) {	SectionKind Kind) {
	return getCOFFSection (Section, Characteristics, 0, Kind);	return getCOFFSection (Section, Characteristics, 0, Kind);
	}	}

	/// @}	/// @}

	/// @name Dwarf Management	/// @name Dwarf Management
	/// @{	/// @{

	/// GetDwarfFile - creates an entry in the dwarf file and directory tab les.	/// GetDwarfFile - creates an entry in the dwarf file and directory tab les.

	unsigned GetDwarfFile(StringRef FileName, unsigned FileNumber);	unsigned GetDwarfFile(StringRef Directory, StringRef FileName,
		unsigned FileNumber);

	bool isValidDwarfFileNumber(unsigned FileNumber);	bool isValidDwarfFileNumber(unsigned FileNumber);

	bool hasDwarfFiles() const {	bool hasDwarfFiles() const {
	return !MCDwarfFiles.empty();	return !MCDwarfFiles.empty();
	}	}

	const std::vector<MCDwarfFile *> &getMCDwarfFiles() {	const std::vector<MCDwarfFile *> &getMCDwarfFiles() {
	return MCDwarfFiles;	return MCDwarfFiles;
	}	}

	skipping to change at line 253	skipping to change at line 281
	CurrentDwarfLoc.setFlags(Flags);	CurrentDwarfLoc.setFlags(Flags);
	CurrentDwarfLoc.setIsa(Isa);	CurrentDwarfLoc.setIsa(Isa);
	CurrentDwarfLoc.setDiscriminator(Discriminator);	CurrentDwarfLoc.setDiscriminator(Discriminator);
	DwarfLocSeen = true;	DwarfLocSeen = true;
	}	}
	void ClearDwarfLocSeen() { DwarfLocSeen = false; }	void ClearDwarfLocSeen() { DwarfLocSeen = false; }

	bool getDwarfLocSeen() { return DwarfLocSeen; }	bool getDwarfLocSeen() { return DwarfLocSeen; }
	const MCDwarfLoc &getCurrentDwarfLoc() { return CurrentDwarfLoc; }	const MCDwarfLoc &getCurrentDwarfLoc() { return CurrentDwarfLoc; }


		bool getGenDwarfForAssembly() { return GenDwarfForAssembly; }
		void setGenDwarfForAssembly(bool Value) { GenDwarfForAssembly = Value;
		}
		unsigned getGenDwarfFileNumber() { return GenDwarfFileNumber; }
		unsigned nextGenDwarfFileNumber() { return ++GenDwarfFileNumber; }
		const MCSection *getGenDwarfSection() { return GenDwarfSection; }
		void setGenDwarfSection(const MCSection *Sec) { GenDwarfSection = Sec;
		}
		MCSymbol *getGenDwarfSectionStartSym() { return GenDwarfSectionStartSym
		; }
		void setGenDwarfSectionStartSym(MCSymbol *Sym) {
		GenDwarfSectionStartSym = Sym;
		}
		MCSymbol *getGenDwarfSectionEndSym() { return GenDwarfSectionEndSym; }
		void setGenDwarfSectionEndSym(MCSymbol *Sym) {
		GenDwarfSectionEndSym = Sym;
		}
		const std::vector<const MCGenDwarfLabelEntry *>
		&getMCGenDwarfLabelEntries() const {
		return MCGenDwarfLabelEntries;
		}
		void addMCGenDwarfLabelEntry(const MCGenDwarfLabelEntry *E) {
		MCGenDwarfLabelEntries.push_back(E);
		}

		void setDwarfDebugFlags(StringRef S) { DwarfDebugFlags = S; }
		StringRef getDwarfDebugFlags() { return DwarfDebugFlags; }

	/// @}	/// @}

	char *getSecureLogFile() { return SecureLogFile; }	char *getSecureLogFile() { return SecureLogFile; }
	raw_ostream *getSecureLog() { return SecureLog; }	raw_ostream *getSecureLog() { return SecureLog; }
	bool getSecureLogUsed() { return SecureLogUsed; }	bool getSecureLogUsed() { return SecureLogUsed; }
	void setSecureLog(raw_ostream *Value) {	void setSecureLog(raw_ostream *Value) {
	SecureLog = Value;	SecureLog = Value;
	}	}
	void setSecureLogUsed(bool Value) {	void setSecureLogUsed(bool Value) {
	SecureLogUsed = Value;	SecureLogUsed = Value;
	}	}

	void *Allocate(unsigned Size, unsigned Align = 8) {	void *Allocate(unsigned Size, unsigned Align = 8) {
	return Allocator.Allocate(Size, Align);	return Allocator.Allocate(Size, Align);
	}	}
	void Deallocate(void *Ptr) {	void Deallocate(void *Ptr) {
	}	}


		// Unrecoverable error has occured. Display the best diagnostic we can
		// and bail via exit(1). For now, most MC backend errors are unrecovera
		ble.
		// FIXME: We should really do something about that.
		LLVM_ATTRIBUTE_NORETURN void FatalError(SMLoc L, const Twine &Msg);
	};	};

	} // end namespace llvm	} // end namespace llvm

	// operator new and delete aren't allowed inside namespaces.	// operator new and delete aren't allowed inside namespaces.
	// The throw specifications are mandated by the standard.	// The throw specifications are mandated by the standard.
	/// @brief Placement new for using the MCContext's allocator.	/// @brief Placement new for using the MCContext's allocator.
	///	///
	/// This placement form of operator new uses the MCContext's allocator for	/// This placement form of operator new uses the MCContext's allocator for
	/// obtaining memory. It is a non-throwing new, which means that it returns	/// obtaining memory. It is a non-throwing new, which means that it returns

End of changes. 9 change blocks.
	2 lines changed or deleted	67 lines changed or added

	MCDisassembler.h	MCDisassembler.h

	skipping to change at line 93	skipping to change at line 93
	uint64_t address,	uint64_t address,
	raw_ostream &vStream,	raw_ostream &vStream,
	raw_ostream &cStream) const = 0;	raw_ostream &cStream) const = 0;

	/// getEDInfo - Returns the enhanced instruction information correspondin g to	/// getEDInfo - Returns the enhanced instruction information correspondin g to
	/// the disassembler.	/// the disassembler.
	///	///
	/// @return - An array of instruction information, with one entry for	/// @return - An array of instruction information, with one entry for
	/// each MCInst opcode this disassembler returns.	/// each MCInst opcode this disassembler returns.
	/// NULL if there is no info for this target.	/// NULL if there is no info for this target.

	virtual EDInstInfo getEDInfo() const { return (EDInstInfo)0; }	virtual const EDInstInfo getEDInfo() const { return (EDInstInfo)0; }

	private:	private:
	//	//
	// Hooks for symbolic disassembly via the public 'C' interface.	// Hooks for symbolic disassembly via the public 'C' interface.
	//	//
	// The function to get the symbolic information for operands.	// The function to get the symbolic information for operands.
	LLVMOpInfoCallback GetOpInfo;	LLVMOpInfoCallback GetOpInfo;
	// The function to lookup a symbol name.	// The function to lookup a symbol name.
	LLVMSymbolLookupCallback SymbolLookUp;	LLVMSymbolLookupCallback SymbolLookUp;
	// The pointer to the block of symbolic information for above call back.	// The pointer to the block of symbolic information for above call back.

End of changes. 1 change blocks.
	1 lines changed or deleted	1 lines changed or added

	MCDwarf.h	MCDwarf.h

	skipping to change at line 20	skipping to change at line 20
	// This file contains the declaration of the MCDwarfFile to support the dwa rf	// This file contains the declaration of the MCDwarfFile to support the dwa rf
	// .file directive and the .loc directive.	// .file directive and the .loc directive.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_MC_MCDWARF_H	#ifndef LLVM_MC_MCDWARF_H
	#define LLVM_MC_MCDWARF_H	#define LLVM_MC_MCDWARF_H

	#include "llvm/ADT/StringRef.h"	#include "llvm/ADT/StringRef.h"
	#include "llvm/MC/MachineLocation.h"	#include "llvm/MC/MachineLocation.h"

	#include "llvm/MC/MCObjectWriter.h"
	#include "llvm/Support/raw_ostream.h"	#include "llvm/Support/raw_ostream.h"
	#include "llvm/Support/Dwarf.h"	#include "llvm/Support/Dwarf.h"
	#include <vector>	#include <vector>

	namespace llvm {	namespace llvm {
	class MCContext;	class MCContext;

	class MCExpr;	class MCObjectWriter;
	class MCSection;	class MCSection;

	class MCSectionData;
	class MCStreamer;	class MCStreamer;
	class MCSymbol;	class MCSymbol;

	class MCObjectStreamer;	class SourceMgr;
	class raw_ostream;	class SMLoc;

	/// MCDwarfFile - Instances of this class represent the name of the dwarf	/// MCDwarfFile - Instances of this class represent the name of the dwarf
	/// .file directive and its associated dwarf file number in the MC file,	/// .file directive and its associated dwarf file number in the MC file,
	/// and MCDwarfFile's are created and unique'd by the MCContext class whe re	/// and MCDwarfFile's are created and unique'd by the MCContext class whe re
	/// the file number for each is its index into the vector of DwarfFiles ( note	/// the file number for each is its index into the vector of DwarfFiles ( note
	/// index 0 is not used and not a valid dwarf file number).	/// index 0 is not used and not a valid dwarf file number).
	class MCDwarfFile {	class MCDwarfFile {
	// Name - the base name of the file without its directory path.	// Name - the base name of the file without its directory path.
	// The StringRef references memory allocated in the MCContext.	// The StringRef references memory allocated in the MCContext.
	StringRef Name;	StringRef Name;

	skipping to change at line 212	skipping to change at line 210
	const MCLineEntryCollection *getMCLineEntries() const {	const MCLineEntryCollection *getMCLineEntries() const {
	return &MCLineEntries;	return &MCLineEntries;
	}	}
	};	};

	class MCDwarfFileTable {	class MCDwarfFileTable {
	public:	public:
	//	//
	// This emits the Dwarf file and the line tables.	// This emits the Dwarf file and the line tables.
	//	//

	static void Emit(MCStreamer *MCOS);	static const MCSymbol Emit(MCStreamer MCOS);
	};	};

	class MCDwarfLineAddr {	class MCDwarfLineAddr {
	public:	public:
	/// Utility function to encode a Dwarf pair of LineDelta and AddrDeltas .	/// Utility function to encode a Dwarf pair of LineDelta and AddrDeltas .
	static void Encode(int64_t LineDelta, uint64_t AddrDelta, raw_ostream & OS);	static void Encode(int64_t LineDelta, uint64_t AddrDelta, raw_ostream & OS);

	/// Utility function to emit the encoding to a streamer.	/// Utility function to emit the encoding to a streamer.
	static void Emit(MCStreamer *MCOS,	static void Emit(MCStreamer *MCOS,
	int64_t LineDelta,uint64_t AddrDelta);	int64_t LineDelta,uint64_t AddrDelta);

	/// Utility function to write the encoding to an object writer.	/// Utility function to write the encoding to an object writer.
	static void Write(MCObjectWriter *OW,	static void Write(MCObjectWriter *OW,
	int64_t LineDelta, uint64_t AddrDelta);	int64_t LineDelta, uint64_t AddrDelta);
	};	};


		class MCGenDwarfInfo {
		public:
		//
		// When generating dwarf for assembly source files this emits the Dwarf
		// sections.
		//
		static void Emit(MCStreamer MCOS, const MCSymbol LineSectionSymbol);
		};

		// When generating dwarf for assembly source files this is the info that
		is
		// needed to be gathered for each symbol that will have a dwarf label.
		class MCGenDwarfLabelEntry {
		private:
		// Name of the symbol without a leading underbar, if any.
		StringRef Name;
		// The dwarf file number this symbol is in.
		unsigned FileNumber;
		// The line number this symbol is at.
		unsigned LineNumber;
		// The low_pc for the dwarf label is taken from this symbol.
		MCSymbol *Label;

		public:
		MCGenDwarfLabelEntry(StringRef name, unsigned fileNumber,
		unsigned lineNumber, MCSymbol *label) :
		Name(name), FileNumber(fileNumber), LineNumber(lineNumber), Label(lab
		el){}

		StringRef getName() const { return Name; }
		unsigned getFileNumber() const { return FileNumber; }
		unsigned getLineNumber() const { return LineNumber; }
		MCSymbol *getLabel() const { return Label; }

		// This is called when label is created when we are generating dwarf fo
		r
		// assembly source files.
		static void Make(MCSymbol Symbol, MCStreamer MCOS, SourceMgr &SrcMgr,
		SMLoc &Loc);
		};

	class MCCFIInstruction {	class MCCFIInstruction {
	public:	public:

	enum OpType { SameValue, Remember, Restore, Move, RelMove };	enum OpType { SameValue, RememberState, RestoreState, Move, RelMove, Es
		cape,
		Restore};
	private:	private:
	OpType Operation;	OpType Operation;
	MCSymbol *Label;	MCSymbol *Label;
	// Move to & from location.	// Move to & from location.
	MachineLocation Destination;	MachineLocation Destination;
	MachineLocation Source;	MachineLocation Source;

		std::vector<char> Values;
	public:	public:
	MCCFIInstruction(OpType Op, MCSymbol *L)	MCCFIInstruction(OpType Op, MCSymbol *L)
	: Operation(Op), Label(L) {	: Operation(Op), Label(L) {

	assert(Op == Remember \|\| Op == Restore);	assert(Op == RememberState \|\| Op == RestoreState);
	}	}
	MCCFIInstruction(OpType Op, MCSymbol *L, unsigned Register)	MCCFIInstruction(OpType Op, MCSymbol *L, unsigned Register)
	: Operation(Op), Label(L), Destination(Register) {	: Operation(Op), Label(L), Destination(Register) {

	assert(Op == SameValue);	assert(Op == SameValue \|\| Op == Restore);
	}	}
	MCCFIInstruction(MCSymbol *L, const MachineLocation &D,	MCCFIInstruction(MCSymbol *L, const MachineLocation &D,
	const MachineLocation &S)	const MachineLocation &S)
	: Operation(Move), Label(L), Destination(D), Source(S) {	: Operation(Move), Label(L), Destination(D), Source(S) {
	}	}
	MCCFIInstruction(OpType Op, MCSymbol *L, const MachineLocation &D,	MCCFIInstruction(OpType Op, MCSymbol *L, const MachineLocation &D,
	const MachineLocation &S)	const MachineLocation &S)
	: Operation(Op), Label(L), Destination(D), Source(S) {	: Operation(Op), Label(L), Destination(D), Source(S) {
	assert(Op == RelMove);	assert(Op == RelMove);
	}	}

		MCCFIInstruction(OpType Op, MCSymbol *L, StringRef Vals)
		: Operation(Op), Label(L), Values(Vals.begin(), Vals.end()) {
		assert(Op == Escape);
		}
	OpType getOperation() const { return Operation; }	OpType getOperation() const { return Operation; }
	MCSymbol *getLabel() const { return Label; }	MCSymbol *getLabel() const { return Label; }
	const MachineLocation &getDestination() const { return Destination; }	const MachineLocation &getDestination() const { return Destination; }
	const MachineLocation &getSource() const { return Source; }	const MachineLocation &getSource() const { return Source; }

		const StringRef getValues() const {
		return StringRef(&Values[0], Values.size());
		}
	};	};

	struct MCDwarfFrameInfo {	struct MCDwarfFrameInfo {
	MCDwarfFrameInfo() : Begin(0), End(0), Personality(0), Lsda(0),	MCDwarfFrameInfo() : Begin(0), End(0), Personality(0), Lsda(0),
	Function(0), Instructions(), PersonalityEncoding() ,	Function(0), Instructions(), PersonalityEncoding() ,

	LsdaEncoding(0), CompactUnwindEncoding(0) {}	LsdaEncoding(0), CompactUnwindEncoding(0),
		IsSignalFrame(false) {}
	MCSymbol *Begin;	MCSymbol *Begin;
	MCSymbol *End;	MCSymbol *End;
	const MCSymbol *Personality;	const MCSymbol *Personality;
	const MCSymbol *Lsda;	const MCSymbol *Lsda;
	const MCSymbol *Function;	const MCSymbol *Function;
	std::vector<MCCFIInstruction> Instructions;	std::vector<MCCFIInstruction> Instructions;
	unsigned PersonalityEncoding;	unsigned PersonalityEncoding;
	unsigned LsdaEncoding;	unsigned LsdaEncoding;
	uint32_t CompactUnwindEncoding;	uint32_t CompactUnwindEncoding;

		bool IsSignalFrame;
	};	};

	class MCDwarfFrameEmitter {	class MCDwarfFrameEmitter {
	public:	public:
	//	//
	// This emits the frame info section.	// This emits the frame info section.
	//	//
	static void Emit(MCStreamer &streamer, bool usingCFI,	static void Emit(MCStreamer &streamer, bool usingCFI,
	bool isEH);	bool isEH);
	static void EmitAdvanceLoc(MCStreamer &Streamer, uint64_t AddrDelta);	static void EmitAdvanceLoc(MCStreamer &Streamer, uint64_t AddrDelta);

End of changes. 14 change blocks.
	10 lines changed or deleted	61 lines changed or added

	MCELFObjectWriter.h	MCELFObjectWriter.h

	skipping to change at line 13	skipping to change at line 13
	// The LLVM Compiler Infrastructure	// The LLVM Compiler Infrastructure
	//	//
	// This file is distributed under the University of Illinois Open Source	// This file is distributed under the University of Illinois Open Source
	// License. See LICENSE.TXT for details.	// License. See LICENSE.TXT for details.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_MC_MCELFOBJECTWRITER_H	#ifndef LLVM_MC_MCELFOBJECTWRITER_H
	#define LLVM_MC_MCELFOBJECTWRITER_H	#define LLVM_MC_MCELFOBJECTWRITER_H


	#include "llvm/MC/MCObjectWriter.h"	#include "llvm/ADT/Triple.h"
	#include "llvm/Support/DataTypes.h"	#include "llvm/Support/DataTypes.h"

		#include "llvm/Support/ELF.h"
		#include <vector>

	namespace llvm {	namespace llvm {

		class MCAssembler;
		class MCFixup;
		class MCFragment;
		class MCObjectWriter;
		class MCSymbol;
		class MCValue;

		/// @name Relocation Data
		/// @{

		struct ELFRelocationEntry {
		// Make these big enough for both 32-bit and 64-bit
		uint64_t r_offset;
		int Index;
		unsigned Type;
		const MCSymbol *Symbol;
		uint64_t r_addend;
		const MCFixup *Fixup;

		ELFRelocationEntry()
		: r_offset(0), Index(0), Type(0), Symbol(0), r_addend(0), Fixup(0) {}

		ELFRelocationEntry(uint64_t RelocOffset, int Idx, unsigned RelType,
		const MCSymbol *Sym, uint64_t Addend, const MCFixup &F
		ixup)
		: r_offset(RelocOffset), Index(Idx), Type(RelType), Symbol(Sym),
		r_addend(Addend), Fixup(&Fixup) {}

		// Support lexicographic sorting.
		bool operator<(const ELFRelocationEntry &RE) const {
		return RE.r_offset < r_offset;
		}
		};

	class MCELFObjectTargetWriter {	class MCELFObjectTargetWriter {

	const Triple::OSType OSType;	const uint8_t OSABI;
	const uint16_t EMachine;	const uint16_t EMachine;
	const unsigned HasRelocationAddend : 1;	const unsigned HasRelocationAddend : 1;
	const unsigned Is64Bit : 1;	const unsigned Is64Bit : 1;


	protected:	protected:

	MCELFObjectTargetWriter(bool Is64Bit_, Triple::OSType OSType_,
		MCELFObjectTargetWriter(bool Is64Bit_, uint8_t OSABI_,
	uint16_t EMachine_, bool HasRelocationAddend_);	uint16_t EMachine_, bool HasRelocationAddend_);

	public:	public:

	virtual ~MCELFObjectTargetWriter();	static uint8_t getOSABI(Triple::OSType OSType) {
		switch (OSType) {
		case Triple::FreeBSD:
		return ELF::ELFOSABI_FREEBSD;
		case Triple::Linux:
		return ELF::ELFOSABI_LINUX;
		default:
		return ELF::ELFOSABI_NONE;
		}
		}

		virtual ~MCELFObjectTargetWriter() {}

		virtual unsigned GetRelocType(const MCValue &Target, const MCFixup &Fixup
		,
		bool IsPCRel, bool IsRelocWithSymbol,
		int64_t Addend) const = 0;
		virtual unsigned getEFlags() const;
		virtual const MCSymbol *ExplicitRelSym(const MCAssembler &Asm,
		const MCValue &Target,
		const MCFragment &F,
		const MCFixup &Fixup,
		bool IsPCRel) const;
		virtual void adjustFixupOffset(const MCFixup &Fixup,
		uint64_t &RelocOffset);

		virtual void sortRelocs(const MCAssembler &Asm,
		std::vector<ELFRelocationEntry> &Relocs);

	/// @name Accessors	/// @name Accessors
	/// @{	/// @{

	Triple::OSType getOSType() { return OSType; }	uint8_t getOSABI() { return OSABI; }
	uint16_t getEMachine() { return EMachine; }	uint16_t getEMachine() { return EMachine; }
	bool hasRelocationAddend() { return HasRelocationAddend; }	bool hasRelocationAddend() { return HasRelocationAddend; }

	bool is64Bit() { return Is64Bit; }	bool is64Bit() const { return Is64Bit; }
	/// @}	/// @}
	};	};

	/// \brief Construct a new ELF writer instance.	/// \brief Construct a new ELF writer instance.
	///	///
	/// \param MOTW - The target specific ELF writer subclass.	/// \param MOTW - The target specific ELF writer subclass.
	/// \param OS - The stream to write to.	/// \param OS - The stream to write to.
	/// \returns The constructed object writer.	/// \returns The constructed object writer.
	MCObjectWriter createELFObjectWriter(MCELFObjectTargetWriter MOTW,	MCObjectWriter createELFObjectWriter(MCELFObjectTargetWriter MOTW,
	raw_ostream &OS, bool IsLittleEndian) ;	raw_ostream &OS, bool IsLittleEndian) ;

End of changes. 9 change blocks.
	6 lines changed or deleted	71 lines changed or added

	MCExpr.h	MCExpr.h

	skipping to change at line 18	skipping to change at line 18
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_MC_MCEXPR_H	#ifndef LLVM_MC_MCEXPR_H
	#define LLVM_MC_MCEXPR_H	#define LLVM_MC_MCEXPR_H

	#include "llvm/ADT/DenseMap.h"	#include "llvm/ADT/DenseMap.h"
	#include "llvm/Support/Casting.h"	#include "llvm/Support/Casting.h"
	#include "llvm/Support/DataTypes.h"	#include "llvm/Support/DataTypes.h"

	namespace llvm {	namespace llvm {

	class MCAsmInfo;
	class MCAsmLayout;	class MCAsmLayout;
	class MCAssembler;	class MCAssembler;
	class MCContext;	class MCContext;
	class MCSection;	class MCSection;
	class MCSectionData;	class MCSectionData;
	class MCSymbol;	class MCSymbol;
	class MCValue;	class MCValue;
	class raw_ostream;	class raw_ostream;
	class StringRef;	class StringRef;
	typedef DenseMap<const MCSectionData*, uint64_t> SectionAddrMap;	typedef DenseMap<const MCSectionData*, uint64_t> SectionAddrMap;

	skipping to change at line 165	skipping to change at line 164
	VK_INDNTPOFF,	VK_INDNTPOFF,
	VK_NTPOFF,	VK_NTPOFF,
	VK_GOTNTPOFF,	VK_GOTNTPOFF,
	VK_PLT,	VK_PLT,
	VK_TLSGD,	VK_TLSGD,
	VK_TLSLD,	VK_TLSLD,
	VK_TLSLDM,	VK_TLSLDM,
	VK_TPOFF,	VK_TPOFF,
	VK_DTPOFF,	VK_DTPOFF,
	VK_TLVP, // Mach-O thread local variable relocation	VK_TLVP, // Mach-O thread local variable relocation

		VK_SECREL,
	// FIXME: We'd really like to use the generic Kinds listed above for th ese.	// FIXME: We'd really like to use the generic Kinds listed above for th ese.
	VK_ARM_PLT, // ARM-style PLT references. i.e., (PLT) instead of @PLT	VK_ARM_PLT, // ARM-style PLT references. i.e., (PLT) instead of @PLT
	VK_ARM_TLSGD, // ditto for TLSGD, GOT, GOTOFF, TPOFF and GOTTPOFF	VK_ARM_TLSGD, // ditto for TLSGD, GOT, GOTOFF, TPOFF and GOTTPOFF
	VK_ARM_GOT,	VK_ARM_GOT,
	VK_ARM_GOTOFF,	VK_ARM_GOTOFF,
	VK_ARM_TPOFF,	VK_ARM_TPOFF,
	VK_ARM_GOTTPOFF,	VK_ARM_GOTTPOFF,

		VK_ARM_TARGET1,

	VK_PPC_TOC,	VK_PPC_TOC,
	VK_PPC_DARWIN_HA16, // ha16(symbol)	VK_PPC_DARWIN_HA16, // ha16(symbol)
	VK_PPC_DARWIN_LO16, // lo16(symbol)	VK_PPC_DARWIN_LO16, // lo16(symbol)
	VK_PPC_GAS_HA16, // symbol@ha	VK_PPC_GAS_HA16, // symbol@ha

	VK_PPC_GAS_LO16 // symbol@l	VK_PPC_GAS_LO16, // symbol@l

		VK_Mips_GPREL,
		VK_Mips_GOT_CALL,
		VK_Mips_GOT16,
		VK_Mips_GOT,
		VK_Mips_ABS_HI,
		VK_Mips_ABS_LO,
		VK_Mips_TLSGD,
		VK_Mips_TLSLDM,
		VK_Mips_DTPREL_HI,
		VK_Mips_DTPREL_LO,
		VK_Mips_GOTTPREL,
		VK_Mips_TPREL_HI,
		VK_Mips_TPREL_LO,
		VK_Mips_GPOFF_HI,
		VK_Mips_GPOFF_LO,
		VK_Mips_GOT_DISP,
		VK_Mips_GOT_PAGE,
		VK_Mips_GOT_OFST
	};	};

	private:	private:
	/// The symbol being referenced.	/// The symbol being referenced.
	const MCSymbol *Symbol;	const MCSymbol *Symbol;

	/// The symbol reference modifier.	/// The symbol reference modifier.
	const VariantKind Kind;	const VariantKind Kind;

	explicit MCSymbolRefExpr(const MCSymbol *_Symbol, VariantKind _Kind)	explicit MCSymbolRefExpr(const MCSymbol *_Symbol, VariantKind _Kind)

	: MCExpr(MCExpr::SymbolRef), Symbol(_Symbol), Kind(_Kind) {}	: MCExpr(MCExpr::SymbolRef), Symbol(_Symbol), Kind(_Kind) {
		assert(Symbol);
		}

	public:	public:
	/// @name Construction	/// @name Construction
	/// @{	/// @{

	static const MCSymbolRefExpr Create(const MCSymbol Symbol, MCContext &C tx) {	static const MCSymbolRefExpr Create(const MCSymbol Symbol, MCContext &C tx) {
	return MCSymbolRefExpr::Create(Symbol, VK_None, Ctx);	return MCSymbolRefExpr::Create(Symbol, VK_None, Ctx);
	}	}

	static const MCSymbolRefExpr Create(const MCSymbol Symbol, VariantKind Kind,	static const MCSymbolRefExpr Create(const MCSymbol Symbol, VariantKind Kind,

End of changes. 5 change blocks.
	3 lines changed or deleted	25 lines changed or added

	MCFixup.h	MCFixup.h

	skipping to change at line 14	skipping to change at line 14
	//	//
	// This file is distributed under the University of Illinois Open Source	// This file is distributed under the University of Illinois Open Source
	// License. See LICENSE.TXT for details.	// License. See LICENSE.TXT for details.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_MC_MCFIXUP_H	#ifndef LLVM_MC_MCFIXUP_H
	#define LLVM_MC_MCFIXUP_H	#define LLVM_MC_MCFIXUP_H

	#include "llvm/Support/DataTypes.h"	#include "llvm/Support/DataTypes.h"

		#include "llvm/Support/ErrorHandling.h"
		#include "llvm/Support/SMLoc.h"
	#include <cassert>	#include <cassert>

	namespace llvm {	namespace llvm {
	class MCExpr;	class MCExpr;

	/// MCFixupKind - Extensible enumeration to represent the type of a fixup.	/// MCFixupKind - Extensible enumeration to represent the type of a fixup.
	enum MCFixupKind {	enum MCFixupKind {
	FK_Data_1 = 0, ///< A one-byte fixup.	FK_Data_1 = 0, ///< A one-byte fixup.
	FK_Data_2, ///< A two-byte fixup.	FK_Data_2, ///< A two-byte fixup.
	FK_Data_4, ///< A four-byte fixup.	FK_Data_4, ///< A four-byte fixup.
	FK_Data_8, ///< A eight-byte fixup.	FK_Data_8, ///< A eight-byte fixup.
	FK_PCRel_1, ///< A one-byte pc relative fixup.	FK_PCRel_1, ///< A one-byte pc relative fixup.
	FK_PCRel_2, ///< A two-byte pc relative fixup.	FK_PCRel_2, ///< A two-byte pc relative fixup.
	FK_PCRel_4, ///< A four-byte pc relative fixup.	FK_PCRel_4, ///< A four-byte pc relative fixup.
	FK_PCRel_8, ///< A eight-byte pc relative fixup.	FK_PCRel_8, ///< A eight-byte pc relative fixup.

		FK_GPRel_1, ///< A one-byte gp relative fixup.
		FK_GPRel_2, ///< A two-byte gp relative fixup.
		FK_GPRel_4, ///< A four-byte gp relative fixup.
		FK_GPRel_8, ///< A eight-byte gp relative fixup.
		FK_SecRel_1, ///< A one-byte section relative fixup.
		FK_SecRel_2, ///< A two-byte section relative fixup.
		FK_SecRel_4, ///< A four-byte section relative fixup.
		FK_SecRel_8, ///< A eight-byte section relative fixup.

	FirstTargetFixupKind = 128,	FirstTargetFixupKind = 128,

	// Limit range of target fixups, in case we want to pack more efficiently	// Limit range of target fixups, in case we want to pack more efficiently
	// later.	// later.
	MaxTargetFixupKind = (1 << 8)	MaxTargetFixupKind = (1 << 8)
	};	};

	/// MCFixup - Encode information on a single operation to perform on a byte	/// MCFixup - Encode information on a single operation to perform on a byte
	/// sequence (e.g., an encoded instruction) which requires assemble- or run -	/// sequence (e.g., an encoded instruction) which requires assemble- or run -

	skipping to change at line 64	skipping to change at line 74
	/// an instruction or an assembler directive.	/// an instruction or an assembler directive.
	const MCExpr *Value;	const MCExpr *Value;

	/// The byte index of start of the relocation inside the encoded instruct ion.	/// The byte index of start of the relocation inside the encoded instruct ion.
	uint32_t Offset;	uint32_t Offset;

	/// The target dependent kind of fixup item this is. The kind is used to	/// The target dependent kind of fixup item this is. The kind is used to
	/// determine how the operand value should be encoded into the instructio n.	/// determine how the operand value should be encoded into the instructio n.
	unsigned Kind;	unsigned Kind;


		/// The source location which gave rise to the fixup, if any.
		SMLoc Loc;
	public:	public:
	static MCFixup Create(uint32_t Offset, const MCExpr *Value,	static MCFixup Create(uint32_t Offset, const MCExpr *Value,

	MCFixupKind Kind) {	MCFixupKind Kind, SMLoc Loc = SMLoc()) {
	assert(unsigned(Kind) < MaxTargetFixupKind && "Kind out of range!");	assert(unsigned(Kind) < MaxTargetFixupKind && "Kind out of range!");
	MCFixup FI;	MCFixup FI;
	FI.Value = Value;	FI.Value = Value;
	FI.Offset = Offset;	FI.Offset = Offset;
	FI.Kind = unsigned(Kind);	FI.Kind = unsigned(Kind);

		FI.Loc = Loc;
	return FI;	return FI;
	}	}

	MCFixupKind getKind() const { return MCFixupKind(Kind); }	MCFixupKind getKind() const { return MCFixupKind(Kind); }

	uint32_t getOffset() const { return Offset; }	uint32_t getOffset() const { return Offset; }
	void setOffset(uint32_t Value) { Offset = Value; }	void setOffset(uint32_t Value) { Offset = Value; }

	const MCExpr *getValue() const { return Value; }	const MCExpr *getValue() const { return Value; }

	/// getKindForSize - Return the generic fixup kind for a value with the g iven	/// getKindForSize - Return the generic fixup kind for a value with the g iven
	/// size. It is an error to pass an unsupported size.	/// size. It is an error to pass an unsupported size.
	static MCFixupKind getKindForSize(unsigned Size, bool isPCRel) {	static MCFixupKind getKindForSize(unsigned Size, bool isPCRel) {
	switch (Size) {	switch (Size) {

	default: assert(0 && "Invalid generic fixup size!");	default: llvm_unreachable("Invalid generic fixup size!");
	case 1: return isPCRel ? FK_PCRel_1 : FK_Data_1;	case 1: return isPCRel ? FK_PCRel_1 : FK_Data_1;
	case 2: return isPCRel ? FK_PCRel_2 : FK_Data_2;	case 2: return isPCRel ? FK_PCRel_2 : FK_Data_2;
	case 4: return isPCRel ? FK_PCRel_4 : FK_Data_4;	case 4: return isPCRel ? FK_PCRel_4 : FK_Data_4;
	case 8: return isPCRel ? FK_PCRel_8 : FK_Data_8;	case 8: return isPCRel ? FK_PCRel_8 : FK_Data_8;
	}	}
	}	}


		SMLoc getLoc() const { return Loc; }
	};	};

	} // End llvm namespace	} // End llvm namespace

	#endif	#endif

End of changes. 7 change blocks.
	2 lines changed or deleted	17 lines changed or added

	MCInst.h	MCInst.h

	skipping to change at line 22	skipping to change at line 22
	// instructions.	// instructions.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_MC_MCINST_H	#ifndef LLVM_MC_MCINST_H
	#define LLVM_MC_MCINST_H	#define LLVM_MC_MCINST_H

	#include "llvm/ADT/SmallVector.h"	#include "llvm/ADT/SmallVector.h"
	#include "llvm/ADT/StringRef.h"	#include "llvm/ADT/StringRef.h"
	#include "llvm/Support/DataTypes.h"	#include "llvm/Support/DataTypes.h"

		#include "llvm/Support/SMLoc.h"

	namespace llvm {	namespace llvm {
	class raw_ostream;	class raw_ostream;
	class MCAsmInfo;	class MCAsmInfo;
	class MCInstPrinter;	class MCInstPrinter;
	class MCExpr;	class MCExpr;

		class MCInst;

	/// MCOperand - Instances of this class represent operands of the MCInst cl ass.	/// MCOperand - Instances of this class represent operands of the MCInst cl ass.
	/// This is a simple discriminated union.	/// This is a simple discriminated union.
	class MCOperand {	class MCOperand {
	enum MachineOperandType {	enum MachineOperandType {
	kInvalid, ///< Uninitialized.	kInvalid, ///< Uninitialized.
	kRegister, ///< Register operand.	kRegister, ///< Register operand.
	kImmediate, ///< Immediate operand.	kImmediate, ///< Immediate operand.
	kFPImmediate, ///< Floating-point immediate operand.	kFPImmediate, ///< Floating-point immediate operand.

	kExpr ///< Relocatable immediate operand.	kExpr, ///< Relocatable immediate operand.
		kInst ///< Sub-instruction operand.
	};	};
	unsigned char Kind;	unsigned char Kind;

	union {	union {
	unsigned RegVal;	unsigned RegVal;
	int64_t ImmVal;	int64_t ImmVal;
	double FPImmVal;	double FPImmVal;
	const MCExpr *ExprVal;	const MCExpr *ExprVal;

		const MCInst *InstVal;
	};	};
	public:	public:

	MCOperand() : Kind(kInvalid), FPImmVal(0.0) {}	MCOperand() : Kind(kInvalid), FPImmVal(0.0) {}

	bool isValid() const { return Kind != kInvalid; }	bool isValid() const { return Kind != kInvalid; }
	bool isReg() const { return Kind == kRegister; }	bool isReg() const { return Kind == kRegister; }
	bool isImm() const { return Kind == kImmediate; }	bool isImm() const { return Kind == kImmediate; }
	bool isFPImm() const { return Kind == kFPImmediate; }	bool isFPImm() const { return Kind == kFPImmediate; }
	bool isExpr() const { return Kind == kExpr; }	bool isExpr() const { return Kind == kExpr; }

		bool isInst() const { return Kind == kInst; }

	/// getReg - Returns the register number.	/// getReg - Returns the register number.
	unsigned getReg() const {	unsigned getReg() const {
	assert(isReg() && "This is not a register operand!");	assert(isReg() && "This is not a register operand!");
	return RegVal;	return RegVal;
	}	}

	/// setReg - Set the register number.	/// setReg - Set the register number.
	void setReg(unsigned Reg) {	void setReg(unsigned Reg) {
	assert(isReg() && "This is not a register operand!");	assert(isReg() && "This is not a register operand!");

	skipping to change at line 97	skipping to change at line 102

	const MCExpr *getExpr() const {	const MCExpr *getExpr() const {
	assert(isExpr() && "This is not an expression");	assert(isExpr() && "This is not an expression");
	return ExprVal;	return ExprVal;
	}	}
	void setExpr(const MCExpr *Val) {	void setExpr(const MCExpr *Val) {
	assert(isExpr() && "This is not an expression");	assert(isExpr() && "This is not an expression");
	ExprVal = Val;	ExprVal = Val;
	}	}


		const MCInst *getInst() const {
		assert(isInst() && "This is not a sub-instruction");
		return InstVal;
		}
		void setInst(const MCInst *Val) {
		assert(isInst() && "This is not a sub-instruction");
		InstVal = Val;
		}

	static MCOperand CreateReg(unsigned Reg) {	static MCOperand CreateReg(unsigned Reg) {
	MCOperand Op;	MCOperand Op;
	Op.Kind = kRegister;	Op.Kind = kRegister;
	Op.RegVal = Reg;	Op.RegVal = Reg;
	return Op;	return Op;
	}	}
	static MCOperand CreateImm(int64_t Val) {	static MCOperand CreateImm(int64_t Val) {
	MCOperand Op;	MCOperand Op;
	Op.Kind = kImmediate;	Op.Kind = kImmediate;
	Op.ImmVal = Val;	Op.ImmVal = Val;

	skipping to change at line 121	skipping to change at line 135
	Op.Kind = kFPImmediate;	Op.Kind = kFPImmediate;
	Op.FPImmVal = Val;	Op.FPImmVal = Val;
	return Op;	return Op;
	}	}
	static MCOperand CreateExpr(const MCExpr *Val) {	static MCOperand CreateExpr(const MCExpr *Val) {
	MCOperand Op;	MCOperand Op;
	Op.Kind = kExpr;	Op.Kind = kExpr;
	Op.ExprVal = Val;	Op.ExprVal = Val;
	return Op;	return Op;
	}	}

		static MCOperand CreateInst(const MCInst *Val) {
		MCOperand Op;
		Op.Kind = kInst;
		Op.InstVal = Val;
		return Op;
		}

	void print(raw_ostream &OS, const MCAsmInfo *MAI) const;	void print(raw_ostream &OS, const MCAsmInfo *MAI) const;
	void dump() const;	void dump() const;
	};	};


		template <> struct isPodLike<MCOperand> { static const bool value = true; }
		;

	/// MCInst - Instances of this class represent a single low-level machine	/// MCInst - Instances of this class represent a single low-level machine
	/// instruction.	/// instruction.
	class MCInst {	class MCInst {
	unsigned Opcode;	unsigned Opcode;

		SMLoc Loc;
	SmallVector<MCOperand, 8> Operands;	SmallVector<MCOperand, 8> Operands;
	public:	public:
	MCInst() : Opcode(0) {}	MCInst() : Opcode(0) {}

	void setOpcode(unsigned Op) { Opcode = Op; }	void setOpcode(unsigned Op) { Opcode = Op; }


	unsigned getOpcode() const { return Opcode; }	unsigned getOpcode() const { return Opcode; }


		void setLoc(SMLoc loc) { Loc = loc; }
		SMLoc getLoc() const { return Loc; }

	const MCOperand &getOperand(unsigned i) const { return Operands[i]; }	const MCOperand &getOperand(unsigned i) const { return Operands[i]; }
	MCOperand &getOperand(unsigned i) { return Operands[i]; }	MCOperand &getOperand(unsigned i) { return Operands[i]; }
	unsigned getNumOperands() const { return Operands.size(); }	unsigned getNumOperands() const { return Operands.size(); }

	void addOperand(const MCOperand &Op) {	void addOperand(const MCOperand &Op) {
	Operands.push_back(Op);	Operands.push_back(Op);
	}	}

	void clear() { Operands.clear(); }	void clear() { Operands.clear(); }
	size_t size() { return Operands.size(); }	size_t size() { return Operands.size(); }

End of changes. 11 change blocks.
	2 lines changed or deleted	28 lines changed or added

	MCInstPrinter.h	MCInstPrinter.h

	skipping to change at line 17	skipping to change at line 17
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_MC_MCINSTPRINTER_H	#ifndef LLVM_MC_MCINSTPRINTER_H
	#define LLVM_MC_MCINSTPRINTER_H	#define LLVM_MC_MCINSTPRINTER_H

	namespace llvm {	namespace llvm {
	class MCInst;	class MCInst;
	class raw_ostream;	class raw_ostream;
	class MCAsmInfo;	class MCAsmInfo;

		class MCInstrInfo;
		class MCRegisterInfo;
	class StringRef;	class StringRef;

	/// MCInstPrinter - This is an instance of a target assembly language print er	/// MCInstPrinter - This is an instance of a target assembly language print er
	/// that converts an MCInst to valid target assembly syntax.	/// that converts an MCInst to valid target assembly syntax.
	class MCInstPrinter {	class MCInstPrinter {
	protected:	protected:
	/// CommentStream - a stream that comments can be emitted to if desired.	/// CommentStream - a stream that comments can be emitted to if desired.
	/// Each comment must end with a newline. This will be null if verbose	/// Each comment must end with a newline. This will be null if verbose
	/// assembly emission is disable.	/// assembly emission is disable.
	raw_ostream *CommentStream;	raw_ostream *CommentStream;
	const MCAsmInfo &MAI;	const MCAsmInfo &MAI;

		const MCInstrInfo &MII;
		const MCRegisterInfo &MRI;

	/// The current set of available features.	/// The current set of available features.
	unsigned AvailableFeatures;	unsigned AvailableFeatures;

	/// Utility function for printing annotations.	/// Utility function for printing annotations.
	void printAnnotation(raw_ostream &OS, StringRef Annot);	void printAnnotation(raw_ostream &OS, StringRef Annot);
	public:	public:

	MCInstPrinter(const MCAsmInfo &mai)	MCInstPrinter(const MCAsmInfo &mai, const MCInstrInfo &mii,
	: CommentStream(0), MAI(mai), AvailableFeatures(0) {}	const MCRegisterInfo &mri)
		: CommentStream(0), MAI(mai), MII(mii), MRI(mri), AvailableFeatures(0)
		{}

	virtual ~MCInstPrinter();	virtual ~MCInstPrinter();

	/// setCommentStream - Specify a stream to emit comments to.	/// setCommentStream - Specify a stream to emit comments to.
	void setCommentStream(raw_ostream &OS) { CommentStream = &OS; }	void setCommentStream(raw_ostream &OS) { CommentStream = &OS; }

	/// printInst - Print the specified MCInst to the specified raw_ostream.	/// printInst - Print the specified MCInst to the specified raw_ostream.
	///	///
	virtual void printInst(const MCInst *MI, raw_ostream &OS,	virtual void printInst(const MCInst *MI, raw_ostream &OS,
	StringRef Annot) = 0;	StringRef Annot) = 0;

	/// getOpcodeName - Return the name of the specified opcode enum (e.g.	/// getOpcodeName - Return the name of the specified opcode enum (e.g.
	/// "MOV32ri") or empty if we can't resolve it.	/// "MOV32ri") or empty if we can't resolve it.

	virtual StringRef getOpcodeName(unsigned Opcode) const;	StringRef getOpcodeName(unsigned Opcode) const;

	/// printRegName - Print the assembler register name.	/// printRegName - Print the assembler register name.
	virtual void printRegName(raw_ostream &OS, unsigned RegNo) const;	virtual void printRegName(raw_ostream &OS, unsigned RegNo) const;

	unsigned getAvailableFeatures() const { return AvailableFeatures; }	unsigned getAvailableFeatures() const { return AvailableFeatures; }
	void setAvailableFeatures(unsigned Value) { AvailableFeatures = Value; }	void setAvailableFeatures(unsigned Value) { AvailableFeatures = Value; }
	};	};

	} // namespace llvm	} // namespace llvm


End of changes. 4 change blocks.
	3 lines changed or deleted	9 lines changed or added

	MCInstrAnalysis.h	MCInstrAnalysis.h

	skipping to change at line 36	skipping to change at line 36
	public:	public:
	MCInstrAnalysis(const MCInstrInfo *Info) : Info(Info) {}	MCInstrAnalysis(const MCInstrInfo *Info) : Info(Info) {}

	virtual ~MCInstrAnalysis() {}	virtual ~MCInstrAnalysis() {}

	virtual bool isBranch(const MCInst &Inst) const {	virtual bool isBranch(const MCInst &Inst) const {
	return Info->get(Inst.getOpcode()).isBranch();	return Info->get(Inst.getOpcode()).isBranch();
	}	}

	virtual bool isConditionalBranch(const MCInst &Inst) const {	virtual bool isConditionalBranch(const MCInst &Inst) const {

	return Info->get(Inst.getOpcode()).isBranch();	return Info->get(Inst.getOpcode()).isConditionalBranch();
	}	}

	virtual bool isUnconditionalBranch(const MCInst &Inst) const {	virtual bool isUnconditionalBranch(const MCInst &Inst) const {
	return Info->get(Inst.getOpcode()).isUnconditionalBranch();	return Info->get(Inst.getOpcode()).isUnconditionalBranch();
	}	}

	virtual bool isIndirectBranch(const MCInst &Inst) const {	virtual bool isIndirectBranch(const MCInst &Inst) const {
	return Info->get(Inst.getOpcode()).isIndirectBranch();	return Info->get(Inst.getOpcode()).isIndirectBranch();
	}	}


End of changes. 1 change blocks.
	1 lines changed or deleted	1 lines changed or added

	MCInstrDesc.h	MCInstrDesc.h

	skipping to change at line 61	skipping to change at line 61

	/// MCOperandInfo - This holds information about one operand of a machine	/// MCOperandInfo - This holds information about one operand of a machine
	/// instruction, indicating the register class for register operands, etc.	/// instruction, indicating the register class for register operands, etc.
	///	///
	class MCOperandInfo {	class MCOperandInfo {
	public:	public:
	/// RegClass - This specifies the register class enumeration of the opera nd	/// RegClass - This specifies the register class enumeration of the opera nd
	/// if the operand is a register. If isLookupPtrRegClass is set, then th is is	/// if the operand is a register. If isLookupPtrRegClass is set, then th is is
	/// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to	/// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to
	/// get a dynamic register class.	/// get a dynamic register class.

	short RegClass;	int16_t RegClass;

	/// Flags - These are flags from the MCOI::OperandFlags enum.	/// Flags - These are flags from the MCOI::OperandFlags enum.

	unsigned short Flags;	uint8_t Flags;

		/// OperandType - Information about the type of the operand.
		uint8_t OperandType;

	/// Lower 16 bits are used to specify which constraints are set. The high er 16	/// Lower 16 bits are used to specify which constraints are set. The high er 16
	/// bits are used to specify the value of constraints (4 bits each).	/// bits are used to specify the value of constraints (4 bits each).

	unsigned Constraints;	uint32_t Constraints;

	/// OperandType - Information about the type of the operand.
	MCOI::OperandType OperandType;
	/// Currently no other information.	/// Currently no other information.

	/// isLookupPtrRegClass - Set if this operand is a pointer value and it	/// isLookupPtrRegClass - Set if this operand is a pointer value and it
	/// requires a callback to look up its register class.	/// requires a callback to look up its register class.
	bool isLookupPtrRegClass() const {return Flags&(1 <<MCOI::LookupPtrRegCla ss);}	bool isLookupPtrRegClass() const {return Flags&(1 <<MCOI::LookupPtrRegCla ss);}

	/// isPredicate - Set if this is one of the operands that made up of	/// isPredicate - Set if this is one of the operands that made up of
	/// the predicate operand that controls an isPredicable() instruction.	/// the predicate operand that controls an isPredicable() instruction.
	bool isPredicate() const { return Flags & (1 << MCOI::Predicate); }	bool isPredicate() const { return Flags & (1 << MCOI::Predicate); }


	skipping to change at line 139	skipping to change at line 139
	/// register use and many other things. There is one instance of this stru ct	/// register use and many other things. There is one instance of this stru ct
	/// for each target instruction class, and the MachineInstr class points to	/// for each target instruction class, and the MachineInstr class points to
	/// this struct directly to describe itself.	/// this struct directly to describe itself.
	class MCInstrDesc {	class MCInstrDesc {
	public:	public:
	unsigned short Opcode; // The opcode number	unsigned short Opcode; // The opcode number
	unsigned short NumOperands; // Num of args (may be more if variable_op s)	unsigned short NumOperands; // Num of args (may be more if variable_op s)
	unsigned short NumDefs; // Num of args that are definitions	unsigned short NumDefs; // Num of args that are definitions
	unsigned short SchedClass; // enum identifying instr sched class	unsigned short SchedClass; // enum identifying instr sched class
	unsigned short Size; // Number of bytes in encoding.	unsigned short Size; // Number of bytes in encoding.

	const char * Name; // Name of the instruction record in td fi le
	unsigned Flags; // Flags identifying machine instr class	unsigned Flags; // Flags identifying machine instr class
	uint64_t TSFlags; // Target Specific Flag values	uint64_t TSFlags; // Target Specific Flag values

	const unsigned *ImplicitUses; // Registers implicitly read by this instr	const uint16_t *ImplicitUses; // Registers implicitly read by this instr
	const unsigned *ImplicitDefs; // Registers implicitly defined by this in	const uint16_t *ImplicitDefs; // Registers implicitly defined by this in
	str	str
	const MCOperandInfo *OpInfo; // 'NumOperands' entries about operands	const MCOperandInfo *OpInfo; // 'NumOperands' entries about operands

	/// getOperandConstraint - Returns the value of the specific constraint i f	/// getOperandConstraint - Returns the value of the specific constraint i f
	/// it is set. Returns -1 if it is not set.	/// it is set. Returns -1 if it is not set.
	int getOperandConstraint(unsigned OpNum,	int getOperandConstraint(unsigned OpNum,
	MCOI::OperandConstraint Constraint) const {	MCOI::OperandConstraint Constraint) const {
	if (OpNum < NumOperands &&	if (OpNum < NumOperands &&
	(OpInfo[OpNum].Constraints & (1 << Constraint))) {	(OpInfo[OpNum].Constraints & (1 << Constraint))) {
	unsigned Pos = 16 + Constraint * 4;	unsigned Pos = 16 + Constraint * 4;
	return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;	return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
	}	}
	return -1;	return -1;
	}	}

	/// getOpcode - Return the opcode number for this descriptor.	/// getOpcode - Return the opcode number for this descriptor.
	unsigned getOpcode() const {	unsigned getOpcode() const {
	return Opcode;	return Opcode;
	}	}


	/// getName - Return the name of the record in the .td file for this
	/// instruction, for example "ADD8ri".
	const char *getName() const {
	return Name;
	}

	/// getNumOperands - Return the number of declared MachineOperands for th is	/// getNumOperands - Return the number of declared MachineOperands for th is
	/// MachineInstruction. Note that variadic (isVariadic() returns true)	/// MachineInstruction. Note that variadic (isVariadic() returns true)
	/// instructions may have additional operands at the end of the list, and note	/// instructions may have additional operands at the end of the list, and note
	/// that the machine instruction may include implicit register def/uses a s	/// that the machine instruction may include implicit register def/uses a s
	/// well.	/// well.
	unsigned getNumOperands() const {	unsigned getNumOperands() const {
	return NumOperands;	return NumOperands;
	}	}

	/// getNumDefs - Return the number of MachineOperands that are register	/// getNumDefs - Return the number of MachineOperands that are register
	/// definitions. Register definitions always occur at the start of the	/// definitions. Register definitions always occur at the start of the
	/// machine operand list. This is the number of "outs" in the .td file,	/// machine operand list. This is the number of "outs" in the .td file,
	/// and does not include implicit defs.	/// and does not include implicit defs.
	unsigned getNumDefs() const {	unsigned getNumDefs() const {
	return NumDefs;	return NumDefs;
	}	}


		/// getFlags - Return flags of this instruction.
		///
		unsigned getFlags() const { return Flags; }

	/// isVariadic - Return true if this instruction can have a variable numb er of	/// isVariadic - Return true if this instruction can have a variable numb er of
	/// operands. In this case, the variable operands will be after the norm al	/// operands. In this case, the variable operands will be after the norm al
	/// operands but before the implicit definitions and uses (if any are	/// operands but before the implicit definitions and uses (if any are
	/// present).	/// present).
	bool isVariadic() const {	bool isVariadic() const {
	return Flags & (1 << MCID::Variadic);	return Flags & (1 << MCID::Variadic);
	}	}

	/// hasOptionalDef - Set if this instruction has an optional definition, e.g.	/// hasOptionalDef - Set if this instruction has an optional definition, e.g.
	/// ARM instructions which can set condition code if 's' bit is set.	/// ARM instructions which can set condition code if 's' bit is set.
	bool hasOptionalDef() const {	bool hasOptionalDef() const {
	return Flags & (1 << MCID::HasOptionalDef);	return Flags & (1 << MCID::HasOptionalDef);
	}	}


	/// getImplicitUses - Return a list of registers that are potentially
	/// read by any instance of this machine instruction. For example, on X8
	6,
	/// the "adc" instruction adds two register operands and adds the carry b
	it in
	/// from the flags register. In this case, the instruction is marked as
	/// implicitly reading the flags. Likewise, the variable shift instructi
	on on
	/// X86 is marked as implicitly reading the 'CL' register, which it alway
	s
	/// does.
	///
	/// This method returns null if the instruction has no implicit uses.
	const unsigned *getImplicitUses() const {
	return ImplicitUses;
	}

	/// getNumImplicitUses - Return the number of implicit uses this instruct
	ion
	/// has.
	unsigned getNumImplicitUses() const {
	if (ImplicitUses == 0) return 0;
	unsigned i = 0;
	for (; ImplicitUses[i]; ++i) /empty/;
	return i;
	}

	/// getImplicitDefs - Return a list of registers that are potentially
	/// written by any instance of this machine instruction. For example, on
	X86,
	/// many instructions implicitly set the flags register. In this case, t
	hey
	/// are marked as setting the FLAGS. Likewise, many instructions always
	/// deposit their result in a physical register. For example, the X86 di
	vide
	/// instruction always deposits the quotient and remainder in the EAX/EDX
	/// registers. For that instruction, this will return a list containing
	the
	/// EAX/EDX/EFLAGS registers.
	///
	/// This method returns null if the instruction has no implicit defs.
	const unsigned *getImplicitDefs() const {
	return ImplicitDefs;
	}

	/// getNumImplicitDefs - Return the number of implicit defs this instruct
	ion
	/// has.
	unsigned getNumImplicitDefs() const {
	if (ImplicitDefs == 0) return 0;
	unsigned i = 0;
	for (; ImplicitDefs[i]; ++i) /empty/;
	return i;
	}

	/// hasImplicitUseOfPhysReg - Return true if this instruction implicitly
	/// uses the specified physical register.
	bool hasImplicitUseOfPhysReg(unsigned Reg) const {
	if (const unsigned *ImpUses = ImplicitUses)
	for (; *ImpUses; ++ImpUses)
	if (*ImpUses == Reg) return true;
	return false;
	}

	/// hasImplicitDefOfPhysReg - Return true if this instruction implicitly
	/// defines the specified physical register.
	bool hasImplicitDefOfPhysReg(unsigned Reg) const {
	if (const unsigned *ImpDefs = ImplicitDefs)
	for (; *ImpDefs; ++ImpDefs)
	if (*ImpDefs == Reg) return true;
	return false;
	}

	/// getSchedClass - Return the scheduling class for this instruction. Th
	e
	/// scheduling class is an index into the InstrItineraryData table. This
	/// returns zero if there is no known scheduling information for the
	/// instruction.
	///
	unsigned getSchedClass() const {
	return SchedClass;
	}

	/// getSize - Return the number of bytes in the encoding of this instruct
	ion,
	/// or zero if the encoding size cannot be known from the opcode.
	unsigned getSize() const {
	return Size;
	}

	/// isPseudo - Return true if this is a pseudo instruction that doesn't	/// isPseudo - Return true if this is a pseudo instruction that doesn't
	/// correspond to a real machine instruction.	/// correspond to a real machine instruction.
	///	///
	bool isPseudo() const {	bool isPseudo() const {
	return Flags & (1 << MCID::Pseudo);	return Flags & (1 << MCID::Pseudo);
	}	}

	bool isReturn() const {	bool isReturn() const {
	return Flags & (1 << MCID::Return);	return Flags & (1 << MCID::Return);
	}	}

	skipping to change at line 300	skipping to change at line 219
	return Flags & (1 << MCID::Call);	return Flags & (1 << MCID::Call);
	}	}

	/// isBarrier - Returns true if the specified instruction stops control f low	/// isBarrier - Returns true if the specified instruction stops control f low
	/// from executing the instruction immediately following it. Examples in clude	/// from executing the instruction immediately following it. Examples in clude
	/// unconditional branches and return instructions.	/// unconditional branches and return instructions.
	bool isBarrier() const {	bool isBarrier() const {
	return Flags & (1 << MCID::Barrier);	return Flags & (1 << MCID::Barrier);
	}	}


	/// findFirstPredOperandIdx() - Find the index of the first operand in th
	e
	/// operand list that is used to represent the predicate. It returns -1 i
	f
	/// none is found.
	int findFirstPredOperandIdx() const {
	if (isPredicable()) {
	for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
	if (OpInfo[i].isPredicate())
	return i;
	}
	return -1;
	}

	/// isTerminator - Returns true if this instruction part of the terminato r for	/// isTerminator - Returns true if this instruction part of the terminato r for
	/// a basic block. Typically this is things like return and branch	/// a basic block. Typically this is things like return and branch
	/// instructions.	/// instructions.
	///	///
	/// Various passes use this to insert code into the bottom of a basic blo ck,	/// Various passes use this to insert code into the bottom of a basic blo ck,
	/// but before control flow occurs.	/// but before control flow occurs.
	bool isTerminator() const {	bool isTerminator() const {
	return Flags & (1 << MCID::Terminator);	return Flags & (1 << MCID::Terminator);
	}	}


	skipping to change at line 531	skipping to change at line 438

	/// hasExtraDefRegAllocReq - Returns true if this instruction def operand s	/// hasExtraDefRegAllocReq - Returns true if this instruction def operand s
	/// have special register allocation requirements that are not captured b y the	/// have special register allocation requirements that are not captured b y the
	/// operand register classes. e.g. ARM::LDRD's two def registers must be an	/// operand register classes. e.g. ARM::LDRD's two def registers must be an
	/// even / odd pair, ARM::LDM registers have to be in ascending order.	/// even / odd pair, ARM::LDM registers have to be in ascending order.
	/// Post-register allocation passes should not attempt to change allocati ons	/// Post-register allocation passes should not attempt to change allocati ons
	/// for definitions of instructions with this flag.	/// for definitions of instructions with this flag.
	bool hasExtraDefRegAllocReq() const {	bool hasExtraDefRegAllocReq() const {
	return Flags & (1 << MCID::ExtraDefRegAllocReq);	return Flags & (1 << MCID::ExtraDefRegAllocReq);
	}	}


		/// getImplicitUses - Return a list of registers that are potentially
		/// read by any instance of this machine instruction. For example, on X8
		6,
		/// the "adc" instruction adds two register operands and adds the carry b
		it in
		/// from the flags register. In this case, the instruction is marked as
		/// implicitly reading the flags. Likewise, the variable shift instructi
		on on
		/// X86 is marked as implicitly reading the 'CL' register, which it alway
		s
		/// does.
		///
		/// This method returns null if the instruction has no implicit uses.
		const uint16_t *getImplicitUses() const {
		return ImplicitUses;
		}

		/// getNumImplicitUses - Return the number of implicit uses this instruct
		ion
		/// has.
		unsigned getNumImplicitUses() const {
		if (ImplicitUses == 0) return 0;
		unsigned i = 0;
		for (; ImplicitUses[i]; ++i) /empty/;
		return i;
		}

		/// getImplicitDefs - Return a list of registers that are potentially
		/// written by any instance of this machine instruction. For example, on
		X86,
		/// many instructions implicitly set the flags register. In this case, t
		hey
		/// are marked as setting the FLAGS. Likewise, many instructions always
		/// deposit their result in a physical register. For example, the X86 di
		vide
		/// instruction always deposits the quotient and remainder in the EAX/EDX
		/// registers. For that instruction, this will return a list containing
		the
		/// EAX/EDX/EFLAGS registers.
		///
		/// This method returns null if the instruction has no implicit defs.
		const uint16_t *getImplicitDefs() const {
		return ImplicitDefs;
		}

		/// getNumImplicitDefs - Return the number of implicit defs this instruct
		ion
		/// has.
		unsigned getNumImplicitDefs() const {
		if (ImplicitDefs == 0) return 0;
		unsigned i = 0;
		for (; ImplicitDefs[i]; ++i) /empty/;
		return i;
		}

		/// hasImplicitUseOfPhysReg - Return true if this instruction implicitly
		/// uses the specified physical register.
		bool hasImplicitUseOfPhysReg(unsigned Reg) const {
		if (const uint16_t *ImpUses = ImplicitUses)
		for (; *ImpUses; ++ImpUses)
		if (*ImpUses == Reg) return true;
		return false;
		}

		/// hasImplicitDefOfPhysReg - Return true if this instruction implicitly
		/// defines the specified physical register.
		bool hasImplicitDefOfPhysReg(unsigned Reg) const {
		if (const uint16_t *ImpDefs = ImplicitDefs)
		for (; *ImpDefs; ++ImpDefs)
		if (*ImpDefs == Reg) return true;
		return false;
		}

		/// getSchedClass - Return the scheduling class for this instruction. Th
		e
		/// scheduling class is an index into the InstrItineraryData table. This
		/// returns zero if there is no known scheduling information for the
		/// instruction.
		///
		unsigned getSchedClass() const {
		return SchedClass;
		}

		/// getSize - Return the number of bytes in the encoding of this instruct
		ion,
		/// or zero if the encoding size cannot be known from the opcode.
		unsigned getSize() const {
		return Size;
		}

		/// findFirstPredOperandIdx() - Find the index of the first operand in th
		e
		/// operand list that is used to represent the predicate. It returns -1 i
		f
		/// none is found.
		int findFirstPredOperandIdx() const {
		if (isPredicable()) {
		for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
		if (OpInfo[i].isPredicate())
		return i;
		}
		return -1;
		}
	};	};

	} // end namespace llvm	} // end namespace llvm

	#endif	#endif

End of changes. 10 change blocks.
	120 lines changed or deleted	117 lines changed or added

	MCInstrInfo.h	MCInstrInfo.h

	skipping to change at line 27	skipping to change at line 27
	#include "llvm/MC/MCInstrDesc.h"	#include "llvm/MC/MCInstrDesc.h"
	#include <cassert>	#include <cassert>

	namespace llvm {	namespace llvm {

	//------------------------------------------------------------------------- --	//------------------------------------------------------------------------- --
	///	///
	/// MCInstrInfo - Interface to description of machine instruction set	/// MCInstrInfo - Interface to description of machine instruction set
	///	///
	class MCInstrInfo {	class MCInstrInfo {

	const MCInstrDesc *Desc; // Raw array to allow static init'n	const MCInstrDesc *Desc; // Raw array to allow static init'n
	unsigned NumOpcodes; // Number of entries in the desc array	const unsigned *InstrNameIndices; // Array for name indices in InstrNameD
		ata
		const char *InstrNameData; // Instruction name string pool
		unsigned NumOpcodes; // Number of entries in the desc array

	public:	public:
	/// InitMCInstrInfo - Initialize MCInstrInfo, called by TableGen	/// InitMCInstrInfo - Initialize MCInstrInfo, called by TableGen
	/// auto-generated routines. DO NOT USE.	/// auto-generated routines. DO NOT USE.

	void InitMCInstrInfo(const MCInstrDesc *D, unsigned NO) {	void InitMCInstrInfo(const MCInstrDesc D, const unsigned NI, const char
		*ND,
		unsigned NO) {
	Desc = D;	Desc = D;

		InstrNameIndices = NI;
		InstrNameData = ND;
	NumOpcodes = NO;	NumOpcodes = NO;
	}	}

	unsigned getNumOpcodes() const { return NumOpcodes; }	unsigned getNumOpcodes() const { return NumOpcodes; }

	/// get - Return the machine instruction descriptor that corresponds to t he	/// get - Return the machine instruction descriptor that corresponds to t he
	/// specified instruction opcode.	/// specified instruction opcode.
	///	///
	const MCInstrDesc &get(unsigned Opcode) const {	const MCInstrDesc &get(unsigned Opcode) const {
	assert(Opcode < NumOpcodes && "Invalid opcode!");	assert(Opcode < NumOpcodes && "Invalid opcode!");
	return Desc[Opcode];	return Desc[Opcode];
	}	}


		/// getName - Returns the name for the instructions with the given opcode
		.
		const char *getName(unsigned Opcode) const {
		assert(Opcode < NumOpcodes && "Invalid opcode!");
		return &InstrNameData[InstrNameIndices[Opcode]];
		}
	};	};

	} // End llvm namespace	} // End llvm namespace

	#endif	#endif

End of changes. 4 change blocks.
	3 lines changed or deleted	17 lines changed or added

	MCObjectFileInfo.h	MCObjectFileInfo.h

	skipping to change at line 17	skipping to change at line 17
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	//	//
	// This file describes common object file formats.	// This file describes common object file formats.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_MC_MCBJECTFILEINFO_H	#ifndef LLVM_MC_MCBJECTFILEINFO_H
	#define LLVM_MC_MCBJECTFILEINFO_H	#define LLVM_MC_MCBJECTFILEINFO_H


	#include "llvm/MC/MCCodeGenInfo.h"	#include "llvm/Support/CodeGen.h"
	#include "llvm/ADT/StringRef.h"
	#include "llvm/MC/SectionKind.h"

	namespace llvm {	namespace llvm {

	class MCContext;	class MCContext;
	class MCSection;	class MCSection;
	class Triple;	class StringRef;
		class Triple;

	class MCObjectFileInfo {	class MCObjectFileInfo {
	protected:	protected:
	/// CommDirectiveSupportsAlignment - True if .comm supports alignment. T his	/// CommDirectiveSupportsAlignment - True if .comm supports alignment. T his
	/// is a hack for as long as we support 10.4 Tiger, whose assembler doesn 't	/// is a hack for as long as we support 10.4 Tiger, whose assembler doesn 't
	/// support alignment on comm.	/// support alignment on comm.
	bool CommDirectiveSupportsAlignment;	bool CommDirectiveSupportsAlignment;

	/// SupportsWeakEmptyEHFrame - True if target object file supports a	/// SupportsWeakEmptyEHFrame - True if target object file supports a
	/// weak_definition of constant 0 for an omitted EH frame.	/// weak_definition of constant 0 for an omitted EH frame.

	skipping to change at line 50	skipping to change at line 49
	/// non-.globl label. This defaults to true.	/// non-.globl label. This defaults to true.
	bool IsFunctionEHFrameSymbolPrivate;	bool IsFunctionEHFrameSymbolPrivate;

	/// PersonalityEncoding, LSDAEncoding, FDEEncoding, TTypeEncoding - Some	/// PersonalityEncoding, LSDAEncoding, FDEEncoding, TTypeEncoding - Some
	/// encoding values for EH.	/// encoding values for EH.
	unsigned PersonalityEncoding;	unsigned PersonalityEncoding;
	unsigned LSDAEncoding;	unsigned LSDAEncoding;
	unsigned FDEEncoding;	unsigned FDEEncoding;
	unsigned FDECFIEncoding;	unsigned FDECFIEncoding;
	unsigned TTypeEncoding;	unsigned TTypeEncoding;

		// Section flags for eh_frame
		unsigned EHSectionType;
		unsigned EHSectionFlags;

	/// TextSection - Section directive for standard text.	/// TextSection - Section directive for standard text.
	///	///
	const MCSection *TextSection;	const MCSection *TextSection;

	/// DataSection - Section directive for standard data.	/// DataSection - Section directive for standard data.
	///	///
	const MCSection *DataSection;	const MCSection *DataSection;

	/// BSSSection - Section that is default initialized to zero.	/// BSSSection - Section that is default initialized to zero.

	skipping to change at line 85	skipping to change at line 87

	/// LSDASection - If exception handling is supported by the target, this is	/// LSDASection - If exception handling is supported by the target, this is
	/// the section the Language Specific Data Area information is emitted to .	/// the section the Language Specific Data Area information is emitted to .
	const MCSection *LSDASection;	const MCSection *LSDASection;

	/// CompactUnwindSection - If exception handling is supported by the targ et	/// CompactUnwindSection - If exception handling is supported by the targ et
	/// and the target can support a compact representation of the CIE and FD E,	/// and the target can support a compact representation of the CIE and FD E,
	/// this is the section to emit them into.	/// this is the section to emit them into.
	const MCSection *CompactUnwindSection;	const MCSection *CompactUnwindSection;


		/// DwarfAccelNamesSection, DwarfAccelObjCSection
		/// If we use the DWARF accelerated hash tables then we want toe emit the
		se
		/// sections.
		const MCSection *DwarfAccelNamesSection;
		const MCSection *DwarfAccelObjCSection;
		const MCSection *DwarfAccelNamespaceSection;
		const MCSection *DwarfAccelTypesSection;

	// Dwarf sections for debug info. If a target supports debug info, these must	// Dwarf sections for debug info. If a target supports debug info, these must
	// be set.	// be set.
	const MCSection *DwarfAbbrevSection;	const MCSection *DwarfAbbrevSection;
	const MCSection *DwarfInfoSection;	const MCSection *DwarfInfoSection;
	const MCSection *DwarfLineSection;	const MCSection *DwarfLineSection;
	const MCSection *DwarfFrameSection;	const MCSection *DwarfFrameSection;

	const MCSection *DwarfPubNamesSection;
	const MCSection *DwarfPubTypesSection;	const MCSection *DwarfPubTypesSection;
	const MCSection *DwarfDebugInlineSection;	const MCSection *DwarfDebugInlineSection;
	const MCSection *DwarfStrSection;	const MCSection *DwarfStrSection;
	const MCSection *DwarfLocSection;	const MCSection *DwarfLocSection;
	const MCSection *DwarfARangesSection;	const MCSection *DwarfARangesSection;
	const MCSection *DwarfRangesSection;	const MCSection *DwarfRangesSection;
	const MCSection *DwarfMacroInfoSection;	const MCSection *DwarfMacroInfoSection;

	// Extra TLS Variable Data section. If the target needs to put additiona l	// Extra TLS Variable Data section. If the target needs to put additiona l
	// information for a TLS variable, it'll go here.	// information for a TLS variable, it'll go here.
	const MCSection *TLSExtraDataSection;	const MCSection *TLSExtraDataSection;

	/// TLSDataSection - Section directive for Thread Local data.	/// TLSDataSection - Section directive for Thread Local data.

	/// ELF and MachO only.	/// ELF, MachO and COFF.
	const MCSection *TLSDataSection; // Defaults to ".tdata".	const MCSection *TLSDataSection; // Defaults to ".tdata".

	/// TLSBSSSection - Section directive for Thread Local uninitialized data .	/// TLSBSSSection - Section directive for Thread Local uninitialized data .
	/// Null if this target doesn't support a BSS section.	/// Null if this target doesn't support a BSS section.
	/// ELF and MachO only.	/// ELF and MachO only.
	const MCSection *TLSBSSSection; // Defaults to ".tbss".	const MCSection *TLSBSSSection; // Defaults to ".tbss".

	/// EHFrameSection - EH frame section. It is initialized on demand so it	/// EHFrameSection - EH frame section. It is initialized on demand so it
	/// can be overwritten (with uniquing).	/// can be overwritten (with uniquing).
	const MCSection *EHFrameSection;	const MCSection *EHFrameSection;

	skipping to change at line 183	skipping to change at line 192
	unsigned getPersonalityEncoding() const { return PersonalityEncoding; }	unsigned getPersonalityEncoding() const { return PersonalityEncoding; }
	unsigned getLSDAEncoding() const { return LSDAEncoding; }	unsigned getLSDAEncoding() const { return LSDAEncoding; }
	unsigned getFDEEncoding(bool CFI) const {	unsigned getFDEEncoding(bool CFI) const {
	return CFI ? FDECFIEncoding : FDEEncoding;	return CFI ? FDECFIEncoding : FDEEncoding;
	}	}
	unsigned getTTypeEncoding() const { return TTypeEncoding; }	unsigned getTTypeEncoding() const { return TTypeEncoding; }

	const MCSection *getTextSection() const { return TextSection; }	const MCSection *getTextSection() const { return TextSection; }
	const MCSection *getDataSection() const { return DataSection; }	const MCSection *getDataSection() const { return DataSection; }
	const MCSection *getBSSSection() const { return BSSSection; }	const MCSection *getBSSSection() const { return BSSSection; }

	const MCSection *getStaticCtorSection() const { return StaticCtorSection;
	}
	const MCSection *getStaticDtorSection() const { return StaticDtorSection;
	}
	const MCSection *getLSDASection() const { return LSDASection; }	const MCSection *getLSDASection() const { return LSDASection; }
	const MCSection *getCompactUnwindSection() const{	const MCSection *getCompactUnwindSection() const{
	return CompactUnwindSection;	return CompactUnwindSection;
	}	}

		const MCSection *getDwarfAccelNamesSection() const {
		return DwarfAccelNamesSection;
		}
		const MCSection *getDwarfAccelObjCSection() const {
		return DwarfAccelObjCSection;
		}
		const MCSection *getDwarfAccelNamespaceSection() const {
		return DwarfAccelNamespaceSection;
		}
		const MCSection *getDwarfAccelTypesSection() const {
		return DwarfAccelTypesSection;
		}
	const MCSection *getDwarfAbbrevSection() const { return DwarfAbbrevSectio n; }	const MCSection *getDwarfAbbrevSection() const { return DwarfAbbrevSectio n; }
	const MCSection *getDwarfInfoSection() const { return DwarfInfoSection; }	const MCSection *getDwarfInfoSection() const { return DwarfInfoSection; }
	const MCSection *getDwarfLineSection() const { return DwarfLineSection; }	const MCSection *getDwarfLineSection() const { return DwarfLineSection; }
	const MCSection *getDwarfFrameSection() const { return DwarfFrameSection; }	const MCSection *getDwarfFrameSection() const { return DwarfFrameSection; }

	const MCSection *getDwarfPubNamesSection() const{return DwarfPubNamesSect ion;}
	const MCSection *getDwarfPubTypesSection() const{return DwarfPubTypesSect ion;}	const MCSection *getDwarfPubTypesSection() const{return DwarfPubTypesSect ion;}
	const MCSection *getDwarfDebugInlineSection() const {	const MCSection *getDwarfDebugInlineSection() const {
	return DwarfDebugInlineSection;	return DwarfDebugInlineSection;
	}	}
	const MCSection *getDwarfStrSection() const { return DwarfStrSection; }	const MCSection *getDwarfStrSection() const { return DwarfStrSection; }
	const MCSection *getDwarfLocSection() const { return DwarfLocSection; }	const MCSection *getDwarfLocSection() const { return DwarfLocSection; }
	const MCSection *getDwarfARangesSection() const { return DwarfARangesSect ion;}	const MCSection *getDwarfARangesSection() const { return DwarfARangesSect ion;}
	const MCSection *getDwarfRangesSection() const { return DwarfRangesSectio n; }	const MCSection *getDwarfRangesSection() const { return DwarfRangesSectio n; }
	const MCSection *getDwarfMacroInfoSection() const {	const MCSection *getDwarfMacroInfoSection() const {
	return DwarfMacroInfoSection;	return DwarfMacroInfoSection;

End of changes. 9 change blocks.
	13 lines changed or deleted	30 lines changed or added

	MCObjectStreamer.h	MCObjectStreamer.h

	skipping to change at line 37	skipping to change at line 37
	/// This class provides an implementation of the MCStreamer interface which is	/// This class provides an implementation of the MCStreamer interface which is
	/// suitable for use with the assembler backend. Specific object file forma ts	/// suitable for use with the assembler backend. Specific object file forma ts
	/// are expected to subclass this interface to implement directives specifi c	/// are expected to subclass this interface to implement directives specifi c
	/// to that file format or custom semantics expected by the object writer	/// to that file format or custom semantics expected by the object writer
	/// implementation.	/// implementation.
	class MCObjectStreamer : public MCStreamer {	class MCObjectStreamer : public MCStreamer {
	MCAssembler *Assembler;	MCAssembler *Assembler;
	MCSectionData *CurSectionData;	MCSectionData *CurSectionData;

	virtual void EmitInstToData(const MCInst &Inst) = 0;	virtual void EmitInstToData(const MCInst &Inst) = 0;

		virtual void EmitCFIStartProcImpl(MCDwarfFrameInfo &Frame);
		virtual void EmitCFIEndProcImpl(MCDwarfFrameInfo &Frame);

	protected:	protected:
	MCObjectStreamer(MCContext &Context, MCAsmBackend &TAB,	MCObjectStreamer(MCContext &Context, MCAsmBackend &TAB,
	raw_ostream &_OS, MCCodeEmitter *_Emitter);	raw_ostream &_OS, MCCodeEmitter *_Emitter);
	MCObjectStreamer(MCContext &Context, MCAsmBackend &TAB,	MCObjectStreamer(MCContext &Context, MCAsmBackend &TAB,
	raw_ostream &_OS, MCCodeEmitter *_Emitter,	raw_ostream &_OS, MCCodeEmitter *_Emitter,
	MCAssembler *_Assembler);	MCAssembler *_Assembler);
	~MCObjectStreamer();	~MCObjectStreamer();

	MCSectionData *getCurrentSectionData() const {	MCSectionData *getCurrentSectionData() const {

	skipping to change at line 73	skipping to change at line 75

	virtual void EmitLabel(MCSymbol *Symbol);	virtual void EmitLabel(MCSymbol *Symbol);
	virtual void EmitValueImpl(const MCExpr *Value, unsigned Size,	virtual void EmitValueImpl(const MCExpr *Value, unsigned Size,
	unsigned AddrSpace);	unsigned AddrSpace);
	virtual void EmitULEB128Value(const MCExpr *Value);	virtual void EmitULEB128Value(const MCExpr *Value);
	virtual void EmitSLEB128Value(const MCExpr *Value);	virtual void EmitSLEB128Value(const MCExpr *Value);
	virtual void EmitWeakReference(MCSymbol Alias, const MCSymbol Symbol);	virtual void EmitWeakReference(MCSymbol Alias, const MCSymbol Symbol);
	virtual void ChangeSection(const MCSection *Section);	virtual void ChangeSection(const MCSection *Section);
	virtual void EmitInstruction(const MCInst &Inst);	virtual void EmitInstruction(const MCInst &Inst);
	virtual void EmitInstToFragment(const MCInst &Inst);	virtual void EmitInstToFragment(const MCInst &Inst);

	virtual void EmitValueToOffset(const MCExpr *Offset, unsigned char Value) ;	virtual bool EmitValueToOffset(const MCExpr *Offset, unsigned char Value) ;
	virtual void EmitDwarfAdvanceLineAddr(int64_t LineDelta,	virtual void EmitDwarfAdvanceLineAddr(int64_t LineDelta,
	const MCSymbol *LastLabel,	const MCSymbol *LastLabel,
	const MCSymbol *Label,	const MCSymbol *Label,
	unsigned PointerSize);	unsigned PointerSize);
	virtual void EmitDwarfAdvanceFrameAddr(const MCSymbol *LastLabel,	virtual void EmitDwarfAdvanceFrameAddr(const MCSymbol *LastLabel,
	const MCSymbol *Label);	const MCSymbol *Label);

	virtual void Finish();	virtual void EmitGPRel32Value(const MCExpr *Value);
		virtual void FinishImpl();

	/// @}	/// @}
	};	};

	} // end namespace llvm	} // end namespace llvm

	#endif	#endif

End of changes. 3 change blocks.
	2 lines changed or deleted	5 lines changed or added

	MCObjectWriter.h	MCObjectWriter.h

	skipping to change at line 13	skipping to change at line 13
	// The LLVM Compiler Infrastructure	// The LLVM Compiler Infrastructure
	//	//
	// This file is distributed under the University of Illinois Open Source	// This file is distributed under the University of Illinois Open Source
	// License. See LICENSE.TXT for details.	// License. See LICENSE.TXT for details.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_MC_MCOBJECTWRITER_H	#ifndef LLVM_MC_MCOBJECTWRITER_H
	#define LLVM_MC_MCOBJECTWRITER_H	#define LLVM_MC_MCOBJECTWRITER_H


	#include "llvm/ADT/Triple.h"
	#include "llvm/Support/raw_ostream.h"	#include "llvm/Support/raw_ostream.h"
	#include "llvm/Support/DataTypes.h"	#include "llvm/Support/DataTypes.h"
	#include <cassert>	#include <cassert>

	namespace llvm {	namespace llvm {
	class MCAsmLayout;	class MCAsmLayout;
	class MCAssembler;	class MCAssembler;
	class MCFixup;	class MCFixup;
	class MCFragment;	class MCFragment;

	class MCSymbol;
	class MCSymbolData;	class MCSymbolData;
	class MCSymbolRefExpr;	class MCSymbolRefExpr;
	class MCValue;	class MCValue;

	class raw_ostream;

	/// MCObjectWriter - Defines the object file and target independent interfa ces	/// MCObjectWriter - Defines the object file and target independent interfa ces
	/// used by the assembler backend to write native file format object files.	/// used by the assembler backend to write native file format object files.
	///	///
	/// The object writer contains a few callbacks used by the assembler to all ow	/// The object writer contains a few callbacks used by the assembler to all ow
	/// the object writer to modify the assembler data structures at appropriat e	/// the object writer to modify the assembler data structures at appropriat e
	/// points. Once assembly is complete, the object writer is given the	/// points. Once assembly is complete, the object writer is given the
	/// MCAssembler instance, which contains all the symbol and section data wh ich	/// MCAssembler instance, which contains all the symbol and section data wh ich
	/// should be emitted as part of WriteObject().	/// should be emitted as part of WriteObject().
	///	///

	skipping to change at line 190	skipping to change at line 187
	OS << Str;	OS << Str;
	if (ZeroFillSize)	if (ZeroFillSize)
	WriteZeros(ZeroFillSize - Str.size());	WriteZeros(ZeroFillSize - Str.size());
	}	}

	/// @}	/// @}

	/// Utility function to encode a SLEB128 value.	/// Utility function to encode a SLEB128 value.
	static void EncodeSLEB128(int64_t Value, raw_ostream &OS);	static void EncodeSLEB128(int64_t Value, raw_ostream &OS);
	/// Utility function to encode a ULEB128 value.	/// Utility function to encode a ULEB128 value.

	static void EncodeULEB128(uint64_t Value, raw_ostream &OS);	static void EncodeULEB128(uint64_t Value, raw_ostream &OS,
		unsigned Padding = 0);
	};	};


	MCObjectWriter *createWinCOFFObjectWriter(raw_ostream &OS, bool is64Bit);

	} // End llvm namespace	} // End llvm namespace

	#endif	#endif

End of changes. 5 change blocks.
	6 lines changed or deleted	2 lines changed or added

	MCRegisterInfo.h	MCRegisterInfo.h

	skipping to change at line 20	skipping to change at line 20
	// This file describes an abstract interface used to get information about a	// This file describes an abstract interface used to get information about a
	// target machines register file. This information is used for a variety o f	// target machines register file. This information is used for a variety o f
	// purposed, especially register allocation.	// purposed, especially register allocation.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_MC_MCREGISTERINFO_H	#ifndef LLVM_MC_MCREGISTERINFO_H
	#define LLVM_MC_MCREGISTERINFO_H	#define LLVM_MC_MCREGISTERINFO_H

	#include "llvm/ADT/DenseMap.h"	#include "llvm/ADT/DenseMap.h"

		#include "llvm/Support/ErrorHandling.h"
	#include <cassert>	#include <cassert>

	namespace llvm {	namespace llvm {

	/// MCRegisterClass - Base class of TargetRegisterClass.	/// MCRegisterClass - Base class of TargetRegisterClass.
	class MCRegisterClass {	class MCRegisterClass {
	public:	public:

	typedef const unsigned* iterator;	typedef const uint16_t* iterator;
	typedef const unsigned* const_iterator;	typedef const uint16_t* const_iterator;
	private:
	unsigned ID;
	const char *Name;	const char *Name;

	const unsigned RegSize, Alignment; // Size & Alignment of register in byt	const iterator RegsBegin;
	es	const uint8_t *const RegSet;
	const int CopyCost;	const uint16_t RegsSize;
		const uint16_t RegSetSize;
		const uint16_t ID;
		const uint16_t RegSize, Alignment; // Size & Alignment of register in byt
		es
		const int8_t CopyCost;
	const bool Allocatable;	const bool Allocatable;

	const iterator RegsBegin, RegsEnd;
	const unsigned char *const RegSet;
	const unsigned RegSetSize;
	public:
	MCRegisterClass(unsigned id, const char *name,
	unsigned RS, unsigned Al, int CC, bool Allocable,
	iterator RB, iterator RE, const unsigned char *Bits,
	unsigned NumBytes)
	: ID(id), Name(name), RegSize(RS), Alignment(Al), CopyCost(CC),
	Allocatable(Allocable), RegsBegin(RB), RegsEnd(RE), RegSet(Bits),
	RegSetSize(NumBytes) {
	for (iterator i = RegsBegin; i != RegsEnd; ++i)
	assert(contains(*i) && "Bit field corrupted.");
	}

	/// getID() - Return the register class ID number.	/// getID() - Return the register class ID number.
	///	///
	unsigned getID() const { return ID; }	unsigned getID() const { return ID; }

	/// getName() - Return the register class name for debugging.	/// getName() - Return the register class name for debugging.
	///	///
	const char *getName() const { return Name; }	const char *getName() const { return Name; }

	/// begin/end - Return all of the registers in this class.	/// begin/end - Return all of the registers in this class.
	///	///
	iterator begin() const { return RegsBegin; }	iterator begin() const { return RegsBegin; }

	iterator end() const { return RegsEnd; }	iterator end() const { return RegsBegin + RegsSize; }

	/// getNumRegs - Return the number of registers in this class.	/// getNumRegs - Return the number of registers in this class.
	///	///

	unsigned getNumRegs() const { return (unsigned)(RegsEnd-RegsBegin); }	unsigned getNumRegs() const { return RegsSize; }

	/// getRegister - Return the specified register in the class.	/// getRegister - Return the specified register in the class.
	///	///
	unsigned getRegister(unsigned i) const {	unsigned getRegister(unsigned i) const {
	assert(i < getNumRegs() && "Register number out of range!");	assert(i < getNumRegs() && "Register number out of range!");
	return RegsBegin[i];	return RegsBegin[i];
	}	}

	/// contains - Return true if the specified register is included in this	/// contains - Return true if the specified register is included in this
	/// register class. This does not include virtual registers.	/// register class. This does not include virtual registers.

	skipping to change at line 118	skipping to change at line 109
	/// a particular register. The Overlaps field contains a pointer to a zero	/// a particular register. The Overlaps field contains a pointer to a zero
	/// terminated array of registers that this register aliases, starting with	/// terminated array of registers that this register aliases, starting with
	/// itself. This is needed for architectures like X86 which have AL alias A X	/// itself. This is needed for architectures like X86 which have AL alias A X
	/// alias EAX. The SubRegs field is a zero terminated array of registers th at	/// alias EAX. The SubRegs field is a zero terminated array of registers th at
	/// are sub-registers of the specific register, e.g. AL, AH are sub-registe rs of	/// are sub-registers of the specific register, e.g. AL, AH are sub-registe rs of
	/// AX. The SuperRegs field is a zero terminated array of registers that ar e	/// AX. The SuperRegs field is a zero terminated array of registers that ar e
	/// super-registers of the specific register, e.g. RAX, EAX, are super-regi sters	/// super-registers of the specific register, e.g. RAX, EAX, are super-regi sters
	/// of AX.	/// of AX.
	///	///
	struct MCRegisterDesc {	struct MCRegisterDesc {

	const char *Name; // Printable name for the reg (for debuggin	const char *Name; // Printable name for the reg (for debugging)
	g)	uint32_t Overlaps; // Overlapping registers, described above
	const unsigned *Overlaps; // Overlapping registers, described above	uint32_t SubRegs; // Sub-register set, described above
	const unsigned *SubRegs; // Sub-register set, described above	uint32_t SuperRegs; // Super-register set, described above
	const unsigned *SuperRegs; // Super-register set, described above
	};	};

	/// MCRegisterInfo base class - We assume that the target defines a static	/// MCRegisterInfo base class - We assume that the target defines a static
	/// array of MCRegisterDesc objects that represent all of the machine	/// array of MCRegisterDesc objects that represent all of the machine
	/// registers that the target has. As such, we simply have to track a poin ter	/// registers that the target has. As such, we simply have to track a poin ter
	/// to this array so that we can turn register number into a register	/// to this array so that we can turn register number into a register
	/// descriptor.	/// descriptor.
	///	///
	/// Note this class is designed to be a base class of TargetRegisterInfo, w hich	/// Note this class is designed to be a base class of TargetRegisterInfo, w hich
	/// is the interface used by codegen. However, specific targets should nev er	/// is the interface used by codegen. However, specific targets should nev er
	/// specialize this class. MCRegisterInfo should only contain getters to ac cess	/// specialize this class. MCRegisterInfo should only contain getters to ac cess
	/// TableGen generated physical register data. It must not be extended with	/// TableGen generated physical register data. It must not be extended with
	/// virtual methods.	/// virtual methods.
	///	///
	class MCRegisterInfo {	class MCRegisterInfo {
	public:	public:
	typedef const MCRegisterClass *regclass_iterator;	typedef const MCRegisterClass *regclass_iterator;


		/// DwarfLLVMRegPair - Emitted by tablegen so Dwarf<->LLVM reg mappings c
		an be
		/// performed with a binary search.
		struct DwarfLLVMRegPair {
		unsigned FromReg;
		unsigned ToReg;

		bool operator<(DwarfLLVMRegPair RHS) const { return FromReg < RHS.FromR
		eg; }
		};
	private:	private:
	const MCRegisterDesc *Desc; // Pointer to the descriptor array	const MCRegisterDesc *Desc; // Pointer to the descriptor array
	unsigned NumRegs; // Number of entries in the a rray	unsigned NumRegs; // Number of entries in the a rray
	unsigned RAReg; // Return address register	unsigned RAReg; // Return address register
	const MCRegisterClass *Classes; // Pointer to the regclass ar ray	const MCRegisterClass *Classes; // Pointer to the regclass ar ray
	unsigned NumClasses; // Number of entries in the a rray	unsigned NumClasses; // Number of entries in the a rray

	DenseMap<unsigned, int> L2DwarfRegs; // LLVM to Dwarf regs mapping	const uint16_t *RegLists; // Pointer to the reglists ar
	DenseMap<unsigned, int> EHL2DwarfRegs; // LLVM to Dwarf regs mapping	ray
	EH	const uint16_t *SubRegIndices; // Pointer to the subreg look
	DenseMap<unsigned, unsigned> Dwarf2LRegs; // Dwarf to LLVM regs mapping	up
	DenseMap<unsigned, unsigned> EHDwarf2LRegs; // Dwarf to LLVM regs mapping	// array.
	EH	unsigned NumSubRegIndices; // Number of subreg indices.

		unsigned L2DwarfRegsSize;
		unsigned EHL2DwarfRegsSize;
		unsigned Dwarf2LRegsSize;
		unsigned EHDwarf2LRegsSize;
		const DwarfLLVMRegPair *L2DwarfRegs; // LLVM to Dwarf regs mapping
		const DwarfLLVMRegPair *EHL2DwarfRegs; // LLVM to Dwarf regs mapping
		EH
		const DwarfLLVMRegPair *Dwarf2LRegs; // Dwarf to LLVM regs mapping
		const DwarfLLVMRegPair *EHDwarf2LRegs; // Dwarf to LLVM regs mapping
		EH
	DenseMap<unsigned, int> L2SEHRegs; // LLVM to SEH regs mapping	DenseMap<unsigned, int> L2SEHRegs; // LLVM to SEH regs mapping

	public:	public:
	/// InitMCRegisterInfo - Initialize MCRegisterInfo, called by TableGen	/// InitMCRegisterInfo - Initialize MCRegisterInfo, called by TableGen
	/// auto-generated routines. DO NOT USE.	/// auto-generated routines. DO NOT USE.
	void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA ,	void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA ,

	const MCRegisterClass *C, unsigned NC) {	const MCRegisterClass *C, unsigned NC,
		const uint16_t *RL,
		const uint16_t *SubIndices,
		unsigned NumIndices) {
	Desc = D;	Desc = D;
	NumRegs = NR;	NumRegs = NR;
	RAReg = RA;	RAReg = RA;
	Classes = C;	Classes = C;

		RegLists = RL;
	NumClasses = NC;	NumClasses = NC;

		SubRegIndices = SubIndices;
		NumSubRegIndices = NumIndices;
	}	}


	/// mapLLVMRegToDwarfReg - Used to initialize LLVM register to Dwarf	/// mapLLVMRegsToDwarfRegs - Used to initialize LLVM register to Dwarf
	/// register number mapping. Called by TableGen auto-generated routines.	/// register number mapping. Called by TableGen auto-generated routines.
	/// DO NOT USE.	/// DO NOT USE.

	void mapLLVMRegToDwarfReg(unsigned LLVMReg, int DwarfReg, bool isEH) {	void mapLLVMRegsToDwarfRegs(const DwarfLLVMRegPair *Map, unsigned Size,
	if (isEH)	bool isEH) {
	EHL2DwarfRegs[LLVMReg] = DwarfReg;	if (isEH) {
	else	EHL2DwarfRegs = Map;
	L2DwarfRegs[LLVMReg] = DwarfReg;	EHL2DwarfRegsSize = Size;
		} else {
		L2DwarfRegs = Map;
		L2DwarfRegsSize = Size;
		}
	}	}


	/// mapDwarfRegToLLVMReg - Used to initialize Dwarf register to LLVM	/// mapDwarfRegsToLLVMRegs - Used to initialize Dwarf register to LLVM
	/// register number mapping. Called by TableGen auto-generated routines.	/// register number mapping. Called by TableGen auto-generated routines.
	/// DO NOT USE.	/// DO NOT USE.

	void mapDwarfRegToLLVMReg(unsigned DwarfReg, unsigned LLVMReg, bool isEH)	void mapDwarfRegsToLLVMRegs(const DwarfLLVMRegPair *Map, unsigned Size,
	{	bool isEH) {
	if (isEH)	if (isEH) {
	EHDwarf2LRegs[DwarfReg] = LLVMReg;	EHDwarf2LRegs = Map;
	else	EHDwarf2LRegsSize = Size;
	Dwarf2LRegs[DwarfReg] = LLVMReg;	} else {
		Dwarf2LRegs = Map;
		Dwarf2LRegsSize = Size;
		}
	}	}

	/// mapLLVMRegToSEHReg - Used to initialize LLVM register to SEH register	/// mapLLVMRegToSEHReg - Used to initialize LLVM register to SEH register
	/// number mapping. By default the SEH register number is just the same	/// number mapping. By default the SEH register number is just the same
	/// as the LLVM register number.	/// as the LLVM register number.
	/// FIXME: TableGen these numbers. Currently this requires target specifi c	/// FIXME: TableGen these numbers. Currently this requires target specifi c
	/// initialization code.	/// initialization code.
	void mapLLVMRegToSEHReg(unsigned LLVMReg, int SEHReg) {	void mapLLVMRegToSEHReg(unsigned LLVMReg, int SEHReg) {
	L2SEHRegs[LLVMReg] = SEHReg;	L2SEHRegs[LLVMReg] = SEHReg;
	}	}

	skipping to change at line 215	skipping to change at line 238
	/// pointer to this object.	/// pointer to this object.
	///	///
	const MCRegisterDesc &get(unsigned RegNo) const {	const MCRegisterDesc &get(unsigned RegNo) const {
	return operator[](RegNo);	return operator[](RegNo);
	}	}

	/// getAliasSet - Return the set of registers aliased by the specified	/// getAliasSet - Return the set of registers aliased by the specified
	/// register, or a null list of there are none. The list returned is zer o	/// register, or a null list of there are none. The list returned is zer o
	/// terminated.	/// terminated.
	///	///

	const unsigned *getAliasSet(unsigned RegNo) const {	const uint16_t *getAliasSet(unsigned RegNo) const {
	// The Overlaps set always begins with Reg itself.	// The Overlaps set always begins with Reg itself.

	return get(RegNo).Overlaps + 1;	return RegLists + get(RegNo).Overlaps + 1;
	}	}

	/// getOverlaps - Return a list of registers that overlap Reg, including	/// getOverlaps - Return a list of registers that overlap Reg, including
	/// itself. This is the same as the alias set except Reg is included in t he	/// itself. This is the same as the alias set except Reg is included in t he
	/// list.	/// list.
	/// These are exactly the registers in { x \| regsOverlap(x, Reg) }.	/// These are exactly the registers in { x \| regsOverlap(x, Reg) }.
	///	///

	const unsigned *getOverlaps(unsigned RegNo) const {	const uint16_t *getOverlaps(unsigned RegNo) const {
	return get(RegNo).Overlaps;	return RegLists + get(RegNo).Overlaps;
	}	}

	/// getSubRegisters - Return the list of registers that are sub-registers of	/// getSubRegisters - Return the list of registers that are sub-registers of
	/// the specified register, or a null list of there are none. The list	/// the specified register, or a null list of there are none. The list
	/// returned is zero terminated and sorted according to super-sub registe r	/// returned is zero terminated and sorted according to super-sub registe r
	/// relations. e.g. X86::RAX's sub-register list is EAX, AX, AL, AH.	/// relations. e.g. X86::RAX's sub-register list is EAX, AX, AL, AH.
	///	///

	const unsigned *getSubRegisters(unsigned RegNo) const {	const uint16_t *getSubRegisters(unsigned RegNo) const {
	return get(RegNo).SubRegs;	return RegLists + get(RegNo).SubRegs;
		}

		/// getSubReg - Returns the physical register number of sub-register "Ind
		ex"
		/// for physical register RegNo. Return zero if the sub-register does not
		/// exist.
		unsigned getSubReg(unsigned Reg, unsigned Idx) const {
		return (SubRegIndices + (Reg - 1) NumSubRegIndices + Idx - 1);
		}

		/// getMatchingSuperReg - Return a super-register of the specified regist
		er
		/// Reg so its sub-register of index SubIdx is Reg.
		unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
		const MCRegisterClass *RC) const {
		for (const uint16_t SRs = getSuperRegisters(Reg); unsigned SR = SRs;+
		+SRs)
		if (Reg == getSubReg(SR, SubIdx) && RC->contains(SR))
		return SR;
		return 0;
		}

		/// getSubRegIndex - For a given register pair, return the sub-register i
		ndex
		/// if the second register is a sub-register of the first. Return zero
		/// otherwise.
		unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const {
		for (unsigned I = 1; I <= NumSubRegIndices; ++I)
		if (getSubReg(RegNo, I) == SubRegNo)
		return I;
		return 0;
	}	}

	/// getSuperRegisters - Return the list of registers that are super-regis ters	/// getSuperRegisters - Return the list of registers that are super-regis ters
	/// of the specified register, or a null list of there are none. The list	/// of the specified register, or a null list of there are none. The list
	/// returned is zero terminated and sorted according to super-sub registe r	/// returned is zero terminated and sorted according to super-sub registe r
	/// relations. e.g. X86::AL's super-register list is AX, EAX, RAX.	/// relations. e.g. X86::AL's super-register list is AX, EAX, RAX.
	///	///

	const unsigned *getSuperRegisters(unsigned RegNo) const {	const uint16_t *getSuperRegisters(unsigned RegNo) const {
	return get(RegNo).SuperRegs;	return RegLists + get(RegNo).SuperRegs;
	}	}

	/// getName - Return the human-readable symbolic target-specific name for the	/// getName - Return the human-readable symbolic target-specific name for the
	/// specified physical register.	/// specified physical register.
	const char *getName(unsigned RegNo) const {	const char *getName(unsigned RegNo) const {
	return get(RegNo).Name;	return get(RegNo).Name;
	}	}

	/// getNumRegs - Return the number of registers this target has (useful f or	/// getNumRegs - Return the number of registers this target has (useful f or
	/// sizing arrays holding per register information)	/// sizing arrays holding per register information)
	unsigned getNumRegs() const {	unsigned getNumRegs() const {
	return NumRegs;	return NumRegs;
	}	}

	/// getDwarfRegNum - Map a target register to an equivalent dwarf registe r	/// getDwarfRegNum - Map a target register to an equivalent dwarf registe r
	/// number. Returns -1 if there is no equivalent value. The second	/// number. Returns -1 if there is no equivalent value. The second
	/// parameter allows targets to use different numberings for EH info and	/// parameter allows targets to use different numberings for EH info and
	/// debugging info.	/// debugging info.
	int getDwarfRegNum(unsigned RegNum, bool isEH) const {	int getDwarfRegNum(unsigned RegNum, bool isEH) const {

	const DenseMap<unsigned, int> &M = isEH ? EHL2DwarfRegs : L2DwarfRegs;	const DwarfLLVMRegPair *M = isEH ? EHL2DwarfRegs : L2DwarfRegs;
	const DenseMap<unsigned, int>::const_iterator I = M.find(RegNum);	unsigned Size = isEH ? EHL2DwarfRegsSize : L2DwarfRegsSize;
	if (I == M.end()) return -1;
	return I->second;	DwarfLLVMRegPair Key = { RegNum, 0 };
		const DwarfLLVMRegPair *I = std::lower_bound(M, M+Size, Key);
		if (I == M+Size \|\| I->FromReg != RegNum)
		return -1;
		return I->ToReg;
	}	}

	/// getLLVMRegNum - Map a dwarf register back to a target register.	/// getLLVMRegNum - Map a dwarf register back to a target register.
	///	///
	int getLLVMRegNum(unsigned RegNum, bool isEH) const {	int getLLVMRegNum(unsigned RegNum, bool isEH) const {

	const DenseMap<unsigned, unsigned> &M = isEH ? EHDwarf2LRegs : Dwarf2LR	const DwarfLLVMRegPair *M = isEH ? EHDwarf2LRegs : Dwarf2LRegs;
	egs;	unsigned Size = isEH ? EHDwarf2LRegsSize : Dwarf2LRegsSize;
	const DenseMap<unsigned, unsigned>::const_iterator I = M.find(RegNum);
	if (I == M.end()) {	DwarfLLVMRegPair Key = { RegNum, 0 };
	assert(0 && "Invalid RegNum");	const DwarfLLVMRegPair *I = std::lower_bound(M, M+Size, Key);
	return -1;	assert(I != M+Size && I->FromReg == RegNum && "Invalid RegNum");
	}	return I->ToReg;
	return I->second;
	}	}

	/// getSEHRegNum - Map a target register to an equivalent SEH register	/// getSEHRegNum - Map a target register to an equivalent SEH register
	/// number. Returns LLVM register number if there is no equivalent value .	/// number. Returns LLVM register number if there is no equivalent value .
	int getSEHRegNum(unsigned RegNum) const {	int getSEHRegNum(unsigned RegNum) const {
	const DenseMap<unsigned, int>::const_iterator I = L2SEHRegs.find(RegNum );	const DenseMap<unsigned, int>::const_iterator I = L2SEHRegs.find(RegNum );
	if (I == L2SEHRegs.end()) return (int)RegNum;	if (I == L2SEHRegs.end()) return (int)RegNum;
	return I->second;	return I->second;
	}	}


End of changes. 23 change blocks.
	68 lines changed or deleted	127 lines changed or added

	MCSection.h	MCSection.h

	skipping to change at line 17	skipping to change at line 17
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	//	//
	// This file declares the MCSection class.	// This file declares the MCSection class.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_MC_MCSECTION_H	#ifndef LLVM_MC_MCSECTION_H
	#define LLVM_MC_MCSECTION_H	#define LLVM_MC_MCSECTION_H


	#include "llvm/ADT/StringRef.h"
	#include "llvm/MC/SectionKind.h"	#include "llvm/MC/SectionKind.h"
	#include "llvm/Support/Casting.h"	#include "llvm/Support/Casting.h"

	namespace llvm {	namespace llvm {

	class MCContext;
	class MCAsmInfo;	class MCAsmInfo;
	class raw_ostream;	class raw_ostream;

	/// MCSection - Instances of this class represent a uniqued identifier fo r a	/// MCSection - Instances of this class represent a uniqued identifier fo r a
	/// section in the current translation unit. The MCContext class uniques and	/// section in the current translation unit. The MCContext class uniques and
	/// creates these.	/// creates these.
	class MCSection {	class MCSection {
	public:	public:
	enum SectionVariant {	enum SectionVariant {
	SV_COFF = 0,	SV_COFF = 0,

End of changes. 2 change blocks.
	2 lines changed or deleted	0 lines changed or added

	MCSectionELF.h	MCSectionELF.h

	skipping to change at line 19	skipping to change at line 19
	//	//
	// This file declares the MCSectionELF class.	// This file declares the MCSectionELF class.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_MC_MCSECTIONELF_H	#ifndef LLVM_MC_MCSECTIONELF_H
	#define LLVM_MC_MCSECTIONELF_H	#define LLVM_MC_MCSECTIONELF_H

	#include "llvm/MC/MCSection.h"	#include "llvm/MC/MCSection.h"
	#include "llvm/Support/ELF.h"	#include "llvm/Support/ELF.h"

		#include "llvm/ADT/StringRef.h"

	namespace llvm {	namespace llvm {

	class MCSymbol;	class MCSymbol;

	/// MCSectionELF - This represents a section on linux, lots of unix variant s	/// MCSectionELF - This represents a section on linux, lots of unix variant s
	/// and some bare metal systems.	/// and some bare metal systems.
	class MCSectionELF : public MCSection {	class MCSectionELF : public MCSection {
	/// SectionName - This is the name of the section. The referenced memory is	/// SectionName - This is the name of the section. The referenced memory is
	/// owned by TargetLoweringObjectFileELF's ELFUniqueMap.	/// owned by TargetLoweringObjectFileELF's ELFUniqueMap.

End of changes. 1 change blocks.
	0 lines changed or deleted	1 lines changed or added

	MCStreamer.h	MCStreamer.h

	skipping to change at line 26	skipping to change at line 26

	#include "llvm/Support/DataTypes.h"	#include "llvm/Support/DataTypes.h"
	#include "llvm/MC/MCDirectives.h"	#include "llvm/MC/MCDirectives.h"
	#include "llvm/MC/MCDwarf.h"	#include "llvm/MC/MCDwarf.h"
	#include "llvm/MC/MCWin64EH.h"	#include "llvm/MC/MCWin64EH.h"
	#include "llvm/ADT/ArrayRef.h"	#include "llvm/ADT/ArrayRef.h"
	#include "llvm/ADT/SmallVector.h"	#include "llvm/ADT/SmallVector.h"

	namespace llvm {	namespace llvm {
	class MCAsmBackend;	class MCAsmBackend;

	class MCAsmInfo;
	class MCCodeEmitter;	class MCCodeEmitter;
	class MCContext;	class MCContext;
	class MCExpr;	class MCExpr;
	class MCInst;	class MCInst;
	class MCInstPrinter;	class MCInstPrinter;
	class MCSection;	class MCSection;
	class MCSymbol;	class MCSymbol;
	class StringRef;	class StringRef;

	class TargetLoweringObjectFile;
	class Twine;	class Twine;
	class raw_ostream;	class raw_ostream;
	class formatted_raw_ostream;	class formatted_raw_ostream;

	/// MCStreamer - Streaming machine code generation interface. This inter face	/// MCStreamer - Streaming machine code generation interface. This inter face
	/// is intended to provide a programatic interface that is very similar t o the	/// is intended to provide a programatic interface that is very similar t o the
	/// level that an assembler .s file provides. It has callbacks to emit b ytes,	/// level that an assembler .s file provides. It has callbacks to emit b ytes,
	/// handle directives, etc. The implementation of this interface retains	/// handle directives, etc. The implementation of this interface retains
	/// state to know what the current section is etc.	/// state to know what the current section is etc.
	///	///

	skipping to change at line 96	skipping to change at line 94
	};	};
	DataType RegionIndicator;	DataType RegionIndicator;

	MCStreamer(MCContext &Ctx);	MCStreamer(MCContext &Ctx);

	const MCExpr BuildSymbolDiff(MCContext &Context, const MCSymbol A,	const MCExpr BuildSymbolDiff(MCContext &Context, const MCSymbol A,
	const MCSymbol *B);	const MCSymbol *B);

	const MCExpr ForceExpAbs(const MCExpr Expr);	const MCExpr ForceExpAbs(const MCExpr Expr);


		void RecordProcStart(MCDwarfFrameInfo &Frame);
		virtual void EmitCFIStartProcImpl(MCDwarfFrameInfo &Frame);
		void RecordProcEnd(MCDwarfFrameInfo &Frame);
		virtual void EmitCFIEndProcImpl(MCDwarfFrameInfo &CurFrame);
	void EmitFrames(bool usingCFI);	void EmitFrames(bool usingCFI);

	MCWin64EHUnwindInfo *getCurrentW64UnwindInfo(){return CurrentW64UnwindI nfo;}	MCWin64EHUnwindInfo *getCurrentW64UnwindInfo(){return CurrentW64UnwindI nfo;}
	void EmitW64Tables();	void EmitW64Tables();

	public:	public:
	virtual ~MCStreamer();	virtual ~MCStreamer();

	MCContext &getContext() const { return Context; }	MCContext &getContext() const { return Context; }


	skipping to change at line 335	skipping to change at line 337
	virtual void EmitCOFFSymbolStorageClass(int StorageClass) = 0;	virtual void EmitCOFFSymbolStorageClass(int StorageClass) = 0;

	/// EmitCOFFSymbolType - Emit the type of the symbol.	/// EmitCOFFSymbolType - Emit the type of the symbol.
	///	///
	/// @param Type - A COFF type identifier (see COFF::SymbolType in X86CO FF.h)	/// @param Type - A COFF type identifier (see COFF::SymbolType in X86CO FF.h)
	virtual void EmitCOFFSymbolType(int Type) = 0;	virtual void EmitCOFFSymbolType(int Type) = 0;

	/// EndCOFFSymbolDef - Marks the end of the symbol definition.	/// EndCOFFSymbolDef - Marks the end of the symbol definition.
	virtual void EndCOFFSymbolDef() = 0;	virtual void EndCOFFSymbolDef() = 0;


		/// EmitCOFFSecRel32 - Emits a COFF section relative relocation.
		///
		/// @param Symbol - Symbol the section relative realocation should poin
		t to.
		virtual void EmitCOFFSecRel32(MCSymbol const *Symbol);

	/// EmitELFSize - Emit an ELF .size directive.	/// EmitELFSize - Emit an ELF .size directive.
	///	///
	/// This corresponds to an assembler statement such as:	/// This corresponds to an assembler statement such as:
	/// .size symbol, expression	/// .size symbol, expression
	///	///
	virtual void EmitELFSize(MCSymbol Symbol, const MCExpr Value) = 0;	virtual void EmitELFSize(MCSymbol Symbol, const MCExpr Value) = 0;

	/// EmitCommonSymbol - Emit a common symbol.	/// EmitCommonSymbol - Emit a common symbol.
	///	///
	/// @param Symbol - The common symbol to emit.	/// @param Symbol - The common symbol to emit.

	skipping to change at line 421	skipping to change at line 428
	/// .long foo	/// .long foo
	void EmitAbsValue(const MCExpr *Value, unsigned Size,	void EmitAbsValue(const MCExpr *Value, unsigned Size,
	unsigned AddrSpace = 0);	unsigned AddrSpace = 0);

	virtual void EmitULEB128Value(const MCExpr *Value) = 0;	virtual void EmitULEB128Value(const MCExpr *Value) = 0;

	virtual void EmitSLEB128Value(const MCExpr *Value) = 0;	virtual void EmitSLEB128Value(const MCExpr *Value) = 0;

	/// EmitULEB128Value - Special case of EmitULEB128Value that avoids the	/// EmitULEB128Value - Special case of EmitULEB128Value that avoids the
	/// client having to pass in a MCExpr for constant integers.	/// client having to pass in a MCExpr for constant integers.

	void EmitULEB128IntValue(uint64_t Value, unsigned AddrSpace = 0);	void EmitULEB128IntValue(uint64_t Value, unsigned AddrSpace = 0,
		unsigned Padding = 0);

	/// EmitSLEB128Value - Special case of EmitSLEB128Value that avoids the	/// EmitSLEB128Value - Special case of EmitSLEB128Value that avoids the
	/// client having to pass in a MCExpr for constant integers.	/// client having to pass in a MCExpr for constant integers.
	void EmitSLEB128IntValue(int64_t Value, unsigned AddrSpace = 0);	void EmitSLEB128IntValue(int64_t Value, unsigned AddrSpace = 0);

	/// EmitSymbolValue - Special case of EmitValue that avoids the client	/// EmitSymbolValue - Special case of EmitValue that avoids the client
	/// having to pass in a MCExpr for MCSymbols.	/// having to pass in a MCExpr for MCSymbols.
	void EmitSymbolValue(const MCSymbol *Sym, unsigned Size,	void EmitSymbolValue(const MCSymbol *Sym, unsigned Size,
	unsigned AddrSpace = 0);	unsigned AddrSpace = 0);


		/// EmitGPRel64Value - Emit the expression @p Value into the output as
		a
		/// gprel64 (64-bit GP relative) value.
		///
		/// This is used to implement assembler directives such as .gpdword on
		/// targets that support them.
		virtual void EmitGPRel64Value(const MCExpr *Value);

	/// EmitGPRel32Value - Emit the expression @p Value into the output as a	/// EmitGPRel32Value - Emit the expression @p Value into the output as a
	/// gprel32 (32-bit GP relative) value.	/// gprel32 (32-bit GP relative) value.
	///	///
	/// This is used to implement assembler directives such as .gprel32 on	/// This is used to implement assembler directives such as .gprel32 on
	/// targets that support them.	/// targets that support them.
	virtual void EmitGPRel32Value(const MCExpr *Value);	virtual void EmitGPRel32Value(const MCExpr *Value);

	/// EmitFill - Emit NumBytes bytes worth of the value specified by	/// EmitFill - Emit NumBytes bytes worth of the value specified by
	/// FillValue. This implements directives such as '.space'.	/// FillValue. This implements directives such as '.space'.
	virtual void EmitFill(uint64_t NumBytes, uint8_t FillValue,	virtual void EmitFill(uint64_t NumBytes, uint8_t FillValue,

	skipping to change at line 493	skipping to change at line 508
	unsigned MaxBytesToEmit = 0) = 0;	unsigned MaxBytesToEmit = 0) = 0;

	/// EmitValueToOffset - Emit some number of copies of @p Value until th e	/// EmitValueToOffset - Emit some number of copies of @p Value until th e
	/// byte offset @p Offset is reached.	/// byte offset @p Offset is reached.
	///	///
	/// This is used to implement assembler directives such as .org.	/// This is used to implement assembler directives such as .org.
	///	///
	/// @param Offset - The offset to reach. This may be an expression, but the	/// @param Offset - The offset to reach. This may be an expression, but the
	/// expression must be associated with the current section.	/// expression must be associated with the current section.
	/// @param Value - The value to use when filling bytes.	/// @param Value - The value to use when filling bytes.

	virtual void EmitValueToOffset(const MCExpr *Offset,	/// @return false on success, true if the offset was invalid.
		virtual bool EmitValueToOffset(const MCExpr *Offset,
	unsigned char Value = 0) = 0;	unsigned char Value = 0) = 0;

	/// @}	/// @}

	/// EmitFileDirective - Switch to a new logical file. This is used to	/// EmitFileDirective - Switch to a new logical file. This is used to
	/// implement the '.file "foo.c"' assembler directive.	/// implement the '.file "foo.c"' assembler directive.
	virtual void EmitFileDirective(StringRef Filename) = 0;	virtual void EmitFileDirective(StringRef Filename) = 0;

	/// EmitDwarfFileDirective - Associate a filename with a specified logi cal	/// EmitDwarfFileDirective - Associate a filename with a specified logi cal
	/// file number. This implements the DWARF2 '.file 4 "foo.c"' assemble r	/// file number. This implements the DWARF2 '.file 4 "foo.c"' assemble r
	/// directive.	/// directive.

	virtual bool EmitDwarfFileDirective(unsigned FileNo,StringRef Filename)	virtual bool EmitDwarfFileDirective(unsigned FileNo, StringRef Director
	;	y,
		StringRef Filename);

	/// EmitDwarfLocDirective - This implements the DWARF2	/// EmitDwarfLocDirective - This implements the DWARF2
	// '.loc fileno lineno ...' assembler directive.	// '.loc fileno lineno ...' assembler directive.
	virtual void EmitDwarfLocDirective(unsigned FileNo, unsigned Line,	virtual void EmitDwarfLocDirective(unsigned FileNo, unsigned Line,
	unsigned Column, unsigned Flags,	unsigned Column, unsigned Flags,
	unsigned Isa,	unsigned Isa,
	unsigned Discriminator,	unsigned Discriminator,
	StringRef FileName);	StringRef FileName);

	virtual void EmitDwarfAdvanceLineAddr(int64_t LineDelta,	virtual void EmitDwarfAdvanceLineAddr(int64_t LineDelta,

	skipping to change at line 529	skipping to change at line 546

	virtual void EmitDwarfAdvanceFrameAddr(const MCSymbol *LastLabel,	virtual void EmitDwarfAdvanceFrameAddr(const MCSymbol *LastLabel,
	const MCSymbol *Label) {	const MCSymbol *Label) {
	}	}

	void EmitDwarfSetLineAddr(int64_t LineDelta, const MCSymbol *Label,	void EmitDwarfSetLineAddr(int64_t LineDelta, const MCSymbol *Label,
	int PointerSize);	int PointerSize);

	virtual void EmitCompactUnwindEncoding(uint32_t CompactUnwindEncoding);	virtual void EmitCompactUnwindEncoding(uint32_t CompactUnwindEncoding);
	virtual void EmitCFISections(bool EH, bool Debug);	virtual void EmitCFISections(bool EH, bool Debug);

	virtual void EmitCFIStartProc();	void EmitCFIStartProc();
	virtual void EmitCFIEndProc();	void EmitCFIEndProc();
	virtual void EmitCFIDefCfa(int64_t Register, int64_t Offset);	virtual void EmitCFIDefCfa(int64_t Register, int64_t Offset);
	virtual void EmitCFIDefCfaOffset(int64_t Offset);	virtual void EmitCFIDefCfaOffset(int64_t Offset);
	virtual void EmitCFIDefCfaRegister(int64_t Register);	virtual void EmitCFIDefCfaRegister(int64_t Register);
	virtual void EmitCFIOffset(int64_t Register, int64_t Offset);	virtual void EmitCFIOffset(int64_t Register, int64_t Offset);
	virtual void EmitCFIPersonality(const MCSymbol *Sym, unsigned Encoding) ;	virtual void EmitCFIPersonality(const MCSymbol *Sym, unsigned Encoding) ;
	virtual void EmitCFILsda(const MCSymbol *Sym, unsigned Encoding);	virtual void EmitCFILsda(const MCSymbol *Sym, unsigned Encoding);
	virtual void EmitCFIRememberState();	virtual void EmitCFIRememberState();
	virtual void EmitCFIRestoreState();	virtual void EmitCFIRestoreState();
	virtual void EmitCFISameValue(int64_t Register);	virtual void EmitCFISameValue(int64_t Register);

		virtual void EmitCFIRestore(int64_t Register);
	virtual void EmitCFIRelOffset(int64_t Register, int64_t Offset);	virtual void EmitCFIRelOffset(int64_t Register, int64_t Offset);
	virtual void EmitCFIAdjustCfaOffset(int64_t Adjustment);	virtual void EmitCFIAdjustCfaOffset(int64_t Adjustment);

		virtual void EmitCFIEscape(StringRef Values);
		virtual void EmitCFISignalFrame();

	virtual void EmitWin64EHStartProc(const MCSymbol *Symbol);	virtual void EmitWin64EHStartProc(const MCSymbol *Symbol);
	virtual void EmitWin64EHEndProc();	virtual void EmitWin64EHEndProc();
	virtual void EmitWin64EHStartChained();	virtual void EmitWin64EHStartChained();
	virtual void EmitWin64EHEndChained();	virtual void EmitWin64EHEndChained();
	virtual void EmitWin64EHHandler(const MCSymbol *Sym, bool Unwind,	virtual void EmitWin64EHHandler(const MCSymbol *Sym, bool Unwind,
	bool Except);	bool Except);
	virtual void EmitWin64EHHandlerData();	virtual void EmitWin64EHHandlerData();
	virtual void EmitWin64EHPushReg(unsigned Register);	virtual void EmitWin64EHPushReg(unsigned Register);
	virtual void EmitWin64EHSetFrame(unsigned Register, unsigned Offset);	virtual void EmitWin64EHSetFrame(unsigned Register, unsigned Offset);

	skipping to change at line 581	skipping to change at line 601
	virtual void EmitFnStart();	virtual void EmitFnStart();
	virtual void EmitFnEnd();	virtual void EmitFnEnd();
	virtual void EmitCantUnwind();	virtual void EmitCantUnwind();
	virtual void EmitPersonality(const MCSymbol *Personality);	virtual void EmitPersonality(const MCSymbol *Personality);
	virtual void EmitHandlerData();	virtual void EmitHandlerData();
	virtual void EmitSetFP(unsigned FpReg, unsigned SpReg, int64_t Offset = 0);	virtual void EmitSetFP(unsigned FpReg, unsigned SpReg, int64_t Offset = 0);
	virtual void EmitPad(int64_t Offset);	virtual void EmitPad(int64_t Offset);
	virtual void EmitRegSave(const SmallVectorImpl<unsigned> &RegList,	virtual void EmitRegSave(const SmallVectorImpl<unsigned> &RegList,
	bool isVector);	bool isVector);


		/// FinishImpl - Streamer specific finalization.
		virtual void FinishImpl() = 0;
	/// Finish - Finish emission of machine code.	/// Finish - Finish emission of machine code.

	virtual void Finish() = 0;	void Finish();
	};	};

	/// createNullStreamer - Create a dummy machine code streamer, which does	/// createNullStreamer - Create a dummy machine code streamer, which does
	/// nothing. This is useful for timing the assembler front end.	/// nothing. This is useful for timing the assembler front end.
	MCStreamer *createNullStreamer(MCContext &Ctx);	MCStreamer *createNullStreamer(MCContext &Ctx);

	/// createAsmStreamer - Create a machine code streamer which will print o ut	/// createAsmStreamer - Create a machine code streamer which will print o ut
	/// assembly for the native target, suitable for compiling with a native	/// assembly for the native target, suitable for compiling with a native
	/// assembler.	/// assembler.
	///	///

	skipping to change at line 613	skipping to change at line 635
	///	///
	/// \param ShowInst - Whether to show the MCInst representation inline wi th	/// \param ShowInst - Whether to show the MCInst representation inline wi th
	/// the assembly.	/// the assembly.
	///	///
	/// \param DecodeLSDA - If true, emit comments that translates the LSDA i nto a	/// \param DecodeLSDA - If true, emit comments that translates the LSDA i nto a
	/// human readable format. Only usable with CFI.	/// human readable format. Only usable with CFI.
	MCStreamer *createAsmStreamer(MCContext &Ctx, formatted_raw_ostream &OS,	MCStreamer *createAsmStreamer(MCContext &Ctx, formatted_raw_ostream &OS,
	bool isVerboseAsm,	bool isVerboseAsm,
	bool useLoc,	bool useLoc,
	bool useCFI,	bool useCFI,

		bool useDwarfDirectory,
	MCInstPrinter *InstPrint = 0,	MCInstPrinter *InstPrint = 0,
	MCCodeEmitter *CE = 0,	MCCodeEmitter *CE = 0,
	MCAsmBackend *TAB = 0,	MCAsmBackend *TAB = 0,
	bool ShowInst = false);	bool ShowInst = false);

	/// createMachOStreamer - Create a machine code streamer which will gener ate	/// createMachOStreamer - Create a machine code streamer which will gener ate
	/// Mach-O format object files.	/// Mach-O format object files.
	///	///
	/// Takes ownership of \arg TAB and \arg CE.	/// Takes ownership of \arg TAB and \arg CE.
	MCStreamer *createMachOStreamer(MCContext &Ctx, MCAsmBackend &TAB,	MCStreamer *createMachOStreamer(MCContext &Ctx, MCAsmBackend &TAB,

	skipping to change at line 638	skipping to change at line 661
	///	///
	/// Takes ownership of \arg TAB and \arg CE.	/// Takes ownership of \arg TAB and \arg CE.
	MCStreamer *createWinCOFFStreamer(MCContext &Ctx,	MCStreamer *createWinCOFFStreamer(MCContext &Ctx,
	MCAsmBackend &TAB,	MCAsmBackend &TAB,
	MCCodeEmitter &CE, raw_ostream &OS,	MCCodeEmitter &CE, raw_ostream &OS,
	bool RelaxAll = false);	bool RelaxAll = false);

	/// createELFStreamer - Create a machine code streamer which will generat e	/// createELFStreamer - Create a machine code streamer which will generat e
	/// ELF format object files.	/// ELF format object files.
	MCStreamer *createELFStreamer(MCContext &Ctx, MCAsmBackend &TAB,	MCStreamer *createELFStreamer(MCContext &Ctx, MCAsmBackend &TAB,

	raw_ostream &OS, MCCodeEmitter *CE,	raw_ostream &OS, MCCodeEmitter *CE,
	bool RelaxAll, bool NoExecStack);	bool RelaxAll, bool NoExecStack);

	/// createLoggingStreamer - Create a machine code streamer which just log
	s the
	/// API calls and then dispatches to another streamer.
	///
	/// The new streamer takes ownership of the \arg Child.
	MCStreamer createLoggingStreamer(MCStreamer Child, raw_ostream &OS);

	/// createPureStreamer - Create a machine code streamer which will genera te	/// createPureStreamer - Create a machine code streamer which will genera te
	/// "pure" MC object files, for use with MC-JIT and testing tools.	/// "pure" MC object files, for use with MC-JIT and testing tools.
	///	///
	/// Takes ownership of \arg TAB and \arg CE.	/// Takes ownership of \arg TAB and \arg CE.
	MCStreamer *createPureStreamer(MCContext &Ctx, MCAsmBackend &TAB,	MCStreamer *createPureStreamer(MCContext &Ctx, MCAsmBackend &TAB,
	raw_ostream &OS, MCCodeEmitter *CE);	raw_ostream &OS, MCCodeEmitter *CE);

	} // end namespace llvm	} // end namespace llvm


End of changes. 15 change blocks.
	18 lines changed or deleted	36 lines changed or added

	MachO.h	MachO.h

	skipping to change at line 21	skipping to change at line 21
	// class to the generic ObjectFile wrapper.	// class to the generic ObjectFile wrapper.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_OBJECT_MACHO_H	#ifndef LLVM_OBJECT_MACHO_H
	#define LLVM_OBJECT_MACHO_H	#define LLVM_OBJECT_MACHO_H

	#include "llvm/Object/ObjectFile.h"	#include "llvm/Object/ObjectFile.h"
	#include "llvm/Object/MachOObject.h"	#include "llvm/Object/MachOObject.h"
	#include "llvm/Support/MachO.h"	#include "llvm/Support/MachO.h"

		#include "llvm/Support/raw_ostream.h"
	#include "llvm/ADT/SmallVector.h"	#include "llvm/ADT/SmallVector.h"

	namespace llvm {	namespace llvm {
	namespace object {	namespace object {

	typedef MachOObject::LoadCommandInfo LoadCommandInfo;	typedef MachOObject::LoadCommandInfo LoadCommandInfo;

	class MachOObjectFile : public ObjectFile {	class MachOObjectFile : public ObjectFile {
	public:	public:
	MachOObjectFile(MemoryBuffer Object, MachOObject MOO, error_code &ec);	MachOObjectFile(MemoryBuffer Object, MachOObject MOO, error_code &ec);

	virtual symbol_iterator begin_symbols() const;	virtual symbol_iterator begin_symbols() const;
	virtual symbol_iterator end_symbols() const;	virtual symbol_iterator end_symbols() const;

		virtual symbol_iterator begin_dynamic_symbols() const;
		virtual symbol_iterator end_dynamic_symbols() const;
		virtual library_iterator begin_libraries_needed() const;
		virtual library_iterator end_libraries_needed() const;
	virtual section_iterator begin_sections() const;	virtual section_iterator begin_sections() const;
	virtual section_iterator end_sections() const;	virtual section_iterator end_sections() const;

	virtual uint8_t getBytesInAddress() const;	virtual uint8_t getBytesInAddress() const;
	virtual StringRef getFileFormatName() const;	virtual StringRef getFileFormatName() const;
	virtual unsigned getArch() const;	virtual unsigned getArch() const;

		virtual StringRef getLoadName() const;

		MachOObject *getObject() { return MachOObj; }

		static inline bool classof(const Binary *v) {
		return v->isMachO();
		}
		static inline bool classof(const MachOObjectFile *v) { return true; }

	protected:	protected:
	virtual error_code getSymbolNext(DataRefImpl Symb, SymbolRef &Res) const;	virtual error_code getSymbolNext(DataRefImpl Symb, SymbolRef &Res) const;
	virtual error_code getSymbolName(DataRefImpl Symb, StringRef &Res) const;	virtual error_code getSymbolName(DataRefImpl Symb, StringRef &Res) const;

	virtual error_code getSymbolOffset(DataRefImpl Symb, uint64_t &Res) const ;	virtual error_code getSymbolFileOffset(DataRefImpl Symb, uint64_t &Res) c onst;
	virtual error_code getSymbolAddress(DataRefImpl Symb, uint64_t &Res) cons t;	virtual error_code getSymbolAddress(DataRefImpl Symb, uint64_t &Res) cons t;
	virtual error_code getSymbolSize(DataRefImpl Symb, uint64_t &Res) const;	virtual error_code getSymbolSize(DataRefImpl Symb, uint64_t &Res) const;
	virtual error_code getSymbolNMTypeChar(DataRefImpl Symb, char &Res) const ;	virtual error_code getSymbolNMTypeChar(DataRefImpl Symb, char &Res) const ;

	virtual error_code isSymbolInternal(DataRefImpl Symb, bool &Res) const;	virtual error_code getSymbolFlags(DataRefImpl Symb, uint32_t &Res) const;
	virtual error_code isSymbolGlobal(DataRefImpl Symb, bool &Res) const;	virtual error_code getSymbolType(DataRefImpl Symb, SymbolRef::Type &Res)
	virtual error_code getSymbolType(DataRefImpl Symb, SymbolRef::SymbolType	const;
	&Res) const;	virtual error_code getSymbolSection(DataRefImpl Symb,
		section_iterator &Res) const;

	virtual error_code getSectionNext(DataRefImpl Sec, SectionRef &Res) const ;	virtual error_code getSectionNext(DataRefImpl Sec, SectionRef &Res) const ;
	virtual error_code getSectionName(DataRefImpl Sec, StringRef &Res) const;	virtual error_code getSectionName(DataRefImpl Sec, StringRef &Res) const;
	virtual error_code getSectionAddress(DataRefImpl Sec, uint64_t &Res) cons t;	virtual error_code getSectionAddress(DataRefImpl Sec, uint64_t &Res) cons t;
	virtual error_code getSectionSize(DataRefImpl Sec, uint64_t &Res) const;	virtual error_code getSectionSize(DataRefImpl Sec, uint64_t &Res) const;
	virtual error_code getSectionContents(DataRefImpl Sec, StringRef &Res) co nst;	virtual error_code getSectionContents(DataRefImpl Sec, StringRef &Res) co nst;
	virtual error_code getSectionAlignment(DataRefImpl Sec, uint64_t &Res) co nst;	virtual error_code getSectionAlignment(DataRefImpl Sec, uint64_t &Res) co nst;
	virtual error_code isSectionText(DataRefImpl Sec, bool &Res) const;	virtual error_code isSectionText(DataRefImpl Sec, bool &Res) const;
	virtual error_code isSectionData(DataRefImpl Sec, bool &Res) const;	virtual error_code isSectionData(DataRefImpl Sec, bool &Res) const;
	virtual error_code isSectionBSS(DataRefImpl Sec, bool &Res) const;	virtual error_code isSectionBSS(DataRefImpl Sec, bool &Res) const;

		virtual error_code isSectionRequiredForExecution(DataRefImpl Sec,
		bool &Res) const;
		virtual error_code isSectionVirtual(DataRefImpl Sec, bool &Res) const;
		virtual error_code isSectionZeroInit(DataRefImpl Sec, bool &Res) const;
	virtual error_code sectionContainsSymbol(DataRefImpl DRI, DataRefImpl S,	virtual error_code sectionContainsSymbol(DataRefImpl DRI, DataRefImpl S,
	bool &Result) const;	bool &Result) const;
	virtual relocation_iterator getSectionRelBegin(DataRefImpl Sec) const;	virtual relocation_iterator getSectionRelBegin(DataRefImpl Sec) const;
	virtual relocation_iterator getSectionRelEnd(DataRefImpl Sec) const;	virtual relocation_iterator getSectionRelEnd(DataRefImpl Sec) const;

	virtual error_code getRelocationNext(DataRefImpl Rel,	virtual error_code getRelocationNext(DataRefImpl Rel,
	RelocationRef &Res) const;	RelocationRef &Res) const;
	virtual error_code getRelocationAddress(DataRefImpl Rel,	virtual error_code getRelocationAddress(DataRefImpl Rel,
	uint64_t &Res) const;	uint64_t &Res) const;

		virtual error_code getRelocationOffset(DataRefImpl Rel,
		uint64_t &Res) const;
	virtual error_code getRelocationSymbol(DataRefImpl Rel,	virtual error_code getRelocationSymbol(DataRefImpl Rel,
	SymbolRef &Res) const;	SymbolRef &Res) const;
	virtual error_code getRelocationType(DataRefImpl Rel,	virtual error_code getRelocationType(DataRefImpl Rel,

	uint32_t &Res) const;	uint64_t &Res) const;
	virtual error_code getRelocationTypeName(DataRefImpl Rel,	virtual error_code getRelocationTypeName(DataRefImpl Rel,
	SmallVectorImpl<char> &Result) c onst;	SmallVectorImpl<char> &Result) c onst;
	virtual error_code getRelocationAdditionalInfo(DataRefImpl Rel,	virtual error_code getRelocationAdditionalInfo(DataRefImpl Rel,
	int64_t &Res) const;	int64_t &Res) const;
	virtual error_code getRelocationValueString(DataRefImpl Rel,	virtual error_code getRelocationValueString(DataRefImpl Rel,
	SmallVectorImpl<char> &Result) c onst;	SmallVectorImpl<char> &Result) c onst;

		virtual error_code getRelocationHidden(DataRefImpl Rel, bool &Result) con
		st;

		virtual error_code getLibraryNext(DataRefImpl LibData, LibraryRef &Res) c
		onst;
		virtual error_code getLibraryPath(DataRefImpl LibData, StringRef &Res) co
		nst;

	private:	private:
	MachOObject *MachOObj;	MachOObject *MachOObj;
	mutable uint32_t RegisteredStringTable;	mutable uint32_t RegisteredStringTable;
	typedef SmallVector<DataRefImpl, 1> SectionList;	typedef SmallVector<DataRefImpl, 1> SectionList;
	SectionList Sections;	SectionList Sections;

	void moveToNextSection(DataRefImpl &DRI) const;	void moveToNextSection(DataRefImpl &DRI) const;
	void getSymbolTableEntry(DataRefImpl DRI,	void getSymbolTableEntry(DataRefImpl DRI,
	InMemoryStruct<macho::SymbolTableEntry> &Res) co nst;	InMemoryStruct<macho::SymbolTableEntry> &Res) co nst;
	void getSymbol64TableEntry(DataRefImpl DRI,	void getSymbol64TableEntry(DataRefImpl DRI,
	InMemoryStruct<macho::Symbol64TableEntry> &Res) c onst;	InMemoryStruct<macho::Symbol64TableEntry> &Res) c onst;
	void moveToNextSymbol(DataRefImpl &DRI) const;	void moveToNextSymbol(DataRefImpl &DRI) const;
	void getSection(DataRefImpl DRI, InMemoryStruct<macho::Section> &Res) con st;	void getSection(DataRefImpl DRI, InMemoryStruct<macho::Section> &Res) con st;
	void getSection64(DataRefImpl DRI,	void getSection64(DataRefImpl DRI,
	InMemoryStruct<macho::Section64> &Res) const;	InMemoryStruct<macho::Section64> &Res) const;
	void getRelocation(DataRefImpl Rel,	void getRelocation(DataRefImpl Rel,
	InMemoryStruct<macho::RelocationEntry> &Res) const;	InMemoryStruct<macho::RelocationEntry> &Res) const;
	std::size_t getSectionIndex(DataRefImpl Sec) const;	std::size_t getSectionIndex(DataRefImpl Sec) const;


		void printRelocationTargetName(InMemoryStruct<macho::RelocationEntry>& RE
		,
		raw_string_ostream &fmt) const;
	};	};

	}	}
	}	}

	#endif	#endif

End of changes. 10 change blocks.
	6 lines changed or deleted	37 lines changed or added

	MachineBasicBlock.h	MachineBasicBlock.h

	skipping to change at line 79	skipping to change at line 79
	/// Predecessors/Successors - Keep track of the predecessor / successor	/// Predecessors/Successors - Keep track of the predecessor / successor
	/// basicblocks.	/// basicblocks.
	std::vector<MachineBasicBlock *> Predecessors;	std::vector<MachineBasicBlock *> Predecessors;
	std::vector<MachineBasicBlock *> Successors;	std::vector<MachineBasicBlock *> Successors;

	/// Weights - Keep track of the weights to the successors. This vector	/// Weights - Keep track of the weights to the successors. This vector
	/// has the same order as Successors, or it is empty if we don't use it	/// has the same order as Successors, or it is empty if we don't use it
	/// (disable optimization).	/// (disable optimization).
	std::vector<uint32_t> Weights;	std::vector<uint32_t> Weights;
	typedef std::vector<uint32_t>::iterator weight_iterator;	typedef std::vector<uint32_t>::iterator weight_iterator;

		typedef std::vector<uint32_t>::const_iterator const_weight_iterator;

	/// LiveIns - Keep track of the physical registers that are livein of	/// LiveIns - Keep track of the physical registers that are livein of
	/// the basicblock.	/// the basicblock.
	std::vector<unsigned> LiveIns;	std::vector<unsigned> LiveIns;

	/// Alignment - Alignment of the basic block. Zero if the basic block doe s	/// Alignment - Alignment of the basic block. Zero if the basic block doe s
	/// not need to be aligned.	/// not need to be aligned.

		/// The alignment is specified as log2(bytes).
	unsigned Alignment;	unsigned Alignment;

	/// IsLandingPad - Indicate that this basic block is entered via an	/// IsLandingPad - Indicate that this basic block is entered via an
	/// exception handler.	/// exception handler.
	bool IsLandingPad;	bool IsLandingPad;

	/// AddressTaken - Indicate that this basic block is potentially the	/// AddressTaken - Indicate that this basic block is potentially the
	/// target of an indirect branch.	/// target of an indirect branch.
	bool AddressTaken;	bool AddressTaken;


	skipping to change at line 117	skipping to change at line 119
	/// getBasicBlock - Return the LLVM basic block that this instance	/// getBasicBlock - Return the LLVM basic block that this instance
	/// corresponded to originally. Note that this may be NULL if this instan ce	/// corresponded to originally. Note that this may be NULL if this instan ce
	/// does not correspond directly to an LLVM basic block.	/// does not correspond directly to an LLVM basic block.
	///	///
	const BasicBlock *getBasicBlock() const { return BB; }	const BasicBlock *getBasicBlock() const { return BB; }

	/// getName - Return the name of the corresponding LLVM basic block, or	/// getName - Return the name of the corresponding LLVM basic block, or
	/// "(null)".	/// "(null)".
	StringRef getName() const;	StringRef getName() const;


		/// getFullName - Return a formatted string to identify this block and it
		s
		/// parent function.
		std::string getFullName() const;

	/// hasAddressTaken - Test whether this block is potentially the target	/// hasAddressTaken - Test whether this block is potentially the target
	/// of an indirect branch.	/// of an indirect branch.
	bool hasAddressTaken() const { return AddressTaken; }	bool hasAddressTaken() const { return AddressTaken; }

	/// setHasAddressTaken - Set this block to reflect that it potentially	/// setHasAddressTaken - Set this block to reflect that it potentially
	/// is the target of an indirect branch.	/// is the target of an indirect branch.
	void setHasAddressTaken() { AddressTaken = true; }	void setHasAddressTaken() { AddressTaken = true; }

	/// getParent - Return the MachineFunction containing this basic block.	/// getParent - Return the MachineFunction containing this basic block.
	///	///
	const MachineFunction *getParent() const { return xParent; }	const MachineFunction *getParent() const { return xParent; }
	MachineFunction *getParent() { return xParent; }	MachineFunction *getParent() { return xParent; }


	typedef Instructions::iterator iterator;	/// bundle_iterator - MachineBasicBlock iterator that automatically skips
	typedef Instructions::const_iterator const_iterator;	over
	typedef std::reverse_iterator<const_iterator> const_reverse_iterator;	/// MIs that are inside bundles (i.e. walk top level MIs only).
	typedef std::reverse_iterator<iterator> reverse_iterator;	template<typename Ty, typename IterTy>
		class bundle_iterator
		: public std::iterator<std::bidirectional_iterator_tag, Ty, ptrdiff_t>
		{
		IterTy MII;

		public:
		bundle_iterator(IterTy mii) : MII(mii) {
		assert(!MII->isInsideBundle() &&
		"It's not legal to initialize bundle_iterator with a bundled M
		I");
		}

		bundle_iterator(Ty &mi) : MII(mi) {
		assert(!mi.isInsideBundle() &&
		"It's not legal to initialize bundle_iterator with a bundled M
		I");
		}
		bundle_iterator(Ty *mi) : MII(mi) {
		assert((!mi \|\| !mi->isInsideBundle()) &&
		"It's not legal to initialize bundle_iterator with a bundled M
		I");
		}
		bundle_iterator(const bundle_iterator &I) : MII(I.MII) {}
		bundle_iterator() : MII(0) {}

		Ty &operator() const { return MII; }
		Ty operator->() const { return &operator(); }

		operator Ty*() const { return MII; }

		bool operator==(const bundle_iterator &x) const {
		return MII == x.MII;
		}
		bool operator!=(const bundle_iterator &x) const {
		return !operator==(x);
		}

		// Increment and decrement operators...
		bundle_iterator &operator--() { // predecrement - Back up
		do {
		--MII;
		} while (MII->isInsideBundle());
		return *this;
		}
		bundle_iterator &operator++() { // preincrement - Advance
		do {
		++MII;
		} while (MII->isInsideBundle());
		return *this;
		}
		bundle_iterator operator--(int) { // postdecrement operators...
		bundle_iterator tmp = *this;
		do {
		--MII;
		} while (MII->isInsideBundle());
		return tmp;
		}
		bundle_iterator operator++(int) { // postincrement operators...
		bundle_iterator tmp = *this;
		do {
		++MII;
		} while (MII->isInsideBundle());
		return tmp;
		}

		IterTy getInstrIterator() const {
		return MII;
		}
		};

		typedef Instructions::iterator instr_iter
		ator;
		typedef Instructions::const_iterator const_instr_iter
		ator;
		typedef std::reverse_iterator<instr_iterator> reverse_instr_iter
		ator;
		typedef
		std::reverse_iterator<const_instr_iterator> const_reverse_instr_iter
		ator;

		typedef
		bundle_iterator<MachineInstr,instr_iterator> iter
		ator;
		typedef
		bundle_iterator<const MachineInstr,const_instr_iterator> const_iter
		ator;
		typedef std::reverse_iterator<const_iterator> const_reverse_iter
		ator;
		typedef std::reverse_iterator<iterator> reverse_iter
		ator;

	unsigned size() const { return (unsigned)Insts.size(); }	unsigned size() const { return (unsigned)Insts.size(); }
	bool empty() const { return Insts.empty(); }	bool empty() const { return Insts.empty(); }

	MachineInstr& front() { return Insts.front(); }	MachineInstr& front() { return Insts.front(); }
	MachineInstr& back() { return Insts.back(); }	MachineInstr& back() { return Insts.back(); }
	const MachineInstr& front() const { return Insts.front(); }	const MachineInstr& front() const { return Insts.front(); }
	const MachineInstr& back() const { return Insts.back(); }	const MachineInstr& back() const { return Insts.back(); }


		instr_iterator instr_begin() { return Insts.begin();
		}
		const_instr_iterator instr_begin() const { return Insts.begin();
		}
		instr_iterator instr_end() { return Insts.end();
		}
		const_instr_iterator instr_end() const { return Insts.end();
		}
		reverse_instr_iterator instr_rbegin() { return Insts.rbegin()
		; }
		const_reverse_instr_iterator instr_rbegin() const { return Insts.rbegin()
		; }
		reverse_instr_iterator instr_rend () { return Insts.rend();
		}
		const_reverse_instr_iterator instr_rend () const { return Insts.rend();
		}

	iterator begin() { return Insts.begin(); }	iterator begin() { return Insts.begin(); }
	const_iterator begin() const { return Insts.begin(); }	const_iterator begin() const { return Insts.begin(); }

	iterator end() { return Insts.end(); }	iterator end() {
	const_iterator end() const { return Insts.end(); }	instr_iterator II = instr_end();
	reverse_iterator rbegin() { return Insts.rbegin(); }	if (II != instr_begin()) {
	const_reverse_iterator rbegin() const { return Insts.rbegin(); }	while (II->isInsideBundle())
		--II;
		}
		return II;
		}
		const_iterator end() const {
		const_instr_iterator II = instr_end();
		if (II != instr_begin()) {
		while (II->isInsideBundle())
		--II;
		}
		return II;
		}
		reverse_iterator rbegin() {
		reverse_instr_iterator II = instr_rbegin();
		if (II != instr_rend()) {
		while (II->isInsideBundle())
		++II;
		}
		return II;
		}
		const_reverse_iterator rbegin() const {
		const_reverse_instr_iterator II = instr_rbegin();
		if (II != instr_rend()) {
		while (II->isInsideBundle())
		++II;
		}
		return II;
		}
	reverse_iterator rend () { return Insts.rend(); }	reverse_iterator rend () { return Insts.rend(); }
	const_reverse_iterator rend () const { return Insts.rend(); }	const_reverse_iterator rend () const { return Insts.rend(); }

	// Machine-CFG iterators	// Machine-CFG iterators
	typedef std::vector<MachineBasicBlock *>::iterator pred_iterator;	typedef std::vector<MachineBasicBlock *>::iterator pred_iterator;
	typedef std::vector<MachineBasicBlock *>::const_iterator const_pred_itera tor;	typedef std::vector<MachineBasicBlock *>::const_iterator const_pred_itera tor;
	typedef std::vector<MachineBasicBlock *>::iterator succ_iterator;	typedef std::vector<MachineBasicBlock *>::iterator succ_iterator;
	typedef std::vector<MachineBasicBlock *>::const_iterator const_succ_itera tor;	typedef std::vector<MachineBasicBlock *>::const_iterator const_succ_itera tor;
	typedef std::vector<MachineBasicBlock *>::reverse_iterator	typedef std::vector<MachineBasicBlock *>::reverse_iterator
	pred_reverse_itera tor;	pred_reverse_itera tor;

	skipping to change at line 221	skipping to change at line 341
	bool isLiveIn(unsigned Reg) const;	bool isLiveIn(unsigned Reg) const;

	// Iteration support for live in sets. These sets are kept in sorted	// Iteration support for live in sets. These sets are kept in sorted
	// order by their register number.	// order by their register number.
	typedef std::vector<unsigned>::const_iterator livein_iterator;	typedef std::vector<unsigned>::const_iterator livein_iterator;
	livein_iterator livein_begin() const { return LiveIns.begin(); }	livein_iterator livein_begin() const { return LiveIns.begin(); }
	livein_iterator livein_end() const { return LiveIns.end(); }	livein_iterator livein_end() const { return LiveIns.end(); }
	bool livein_empty() const { return LiveIns.empty(); }	bool livein_empty() const { return LiveIns.empty(); }

	/// getAlignment - Return alignment of the basic block.	/// getAlignment - Return alignment of the basic block.

		/// The alignment is specified as log2(bytes).
	///	///
	unsigned getAlignment() const { return Alignment; }	unsigned getAlignment() const { return Alignment; }

	/// setAlignment - Set alignment of the basic block.	/// setAlignment - Set alignment of the basic block.

		/// The alignment is specified as log2(bytes).
	///	///
	void setAlignment(unsigned Align) { Alignment = Align; }	void setAlignment(unsigned Align) { Alignment = Align; }

	/// isLandingPad - Returns true if the block is a landing pad. That is	/// isLandingPad - Returns true if the block is a landing pad. That is
	/// this basic block is entered via an exception handler.	/// this basic block is entered via an exception handler.
	bool isLandingPad() const { return IsLandingPad; }	bool isLandingPad() const { return IsLandingPad; }

	/// setIsLandingPad - Indicates the block is a landing pad. That is	/// setIsLandingPad - Indicates the block is a landing pad. That is
	/// this basic block is entered via an exception handler.	/// this basic block is entered via an exception handler.
	void setIsLandingPad(bool V = true) { IsLandingPad = V; }	void setIsLandingPad(bool V = true) { IsLandingPad = V; }

	skipping to change at line 321	skipping to change at line 443

	/// SkipPHIsAndLabels - Return the first instruction in MBB after I that is	/// SkipPHIsAndLabels - Return the first instruction in MBB after I that is
	/// not a PHI or a label. This is the correct point to insert copies at t he	/// not a PHI or a label. This is the correct point to insert copies at t he
	/// beginning of a basic block.	/// beginning of a basic block.
	iterator SkipPHIsAndLabels(iterator I);	iterator SkipPHIsAndLabels(iterator I);

	/// getFirstTerminator - returns an iterator to the first terminator	/// getFirstTerminator - returns an iterator to the first terminator
	/// instruction of this basic block. If a terminator does not exist,	/// instruction of this basic block. If a terminator does not exist,
	/// it returns end()	/// it returns end()
	iterator getFirstTerminator();	iterator getFirstTerminator();

		const_iterator getFirstTerminator() const;


	const_iterator getFirstTerminator() const {	/// getFirstInstrTerminator - Same getFirstTerminator but it ignores bund
	return const_cast<MachineBasicBlock*>(this)->getFirstTerminator();	les
	}	/// and return an instr_iterator instead.
		instr_iterator getFirstInstrTerminator();

	/// getLastNonDebugInstr - returns an iterator to the last non-debug	/// getLastNonDebugInstr - returns an iterator to the last non-debug
	/// instruction in the basic block, or end()	/// instruction in the basic block, or end()
	iterator getLastNonDebugInstr();	iterator getLastNonDebugInstr();

		const_iterator getLastNonDebugInstr() const;
	const_iterator getLastNonDebugInstr() const {
	return const_cast<MachineBasicBlock*>(this)->getLastNonDebugInstr();
	}

	/// SplitCriticalEdge - Split the critical edge from this block to the	/// SplitCriticalEdge - Split the critical edge from this block to the
	/// given successor block, and return the newly created block, or null	/// given successor block, and return the newly created block, or null
	/// if splitting is not possible.	/// if splitting is not possible.
	///	///
	/// This function updates LiveVariables, MachineDominatorTree, and	/// This function updates LiveVariables, MachineDominatorTree, and
	/// MachineLoopInfo, as applicable.	/// MachineLoopInfo, as applicable.
	MachineBasicBlock SplitCriticalEdge(MachineBasicBlock Succ, Pass *P);	MachineBasicBlock SplitCriticalEdge(MachineBasicBlock Succ, Pass *P);

	void pop_front() { Insts.pop_front(); }	void pop_front() { Insts.pop_front(); }
	void pop_back() { Insts.pop_back(); }	void pop_back() { Insts.pop_back(); }
	void push_back(MachineInstr *MI) { Insts.push_back(MI); }	void push_back(MachineInstr *MI) { Insts.push_back(MI); }


	template<typename IT>	template<typename IT>

	void insert(iterator I, IT S, IT E) { Insts.insert(I, S, E); }	void insert(instr_iterator I, IT S, IT E) {
	iterator insert(iterator I, MachineInstr *M) { return Insts.insert(I, M);	Insts.insert(I, S, E);
	}	}
	iterator insertAfter(iterator I, MachineInstr *M) {	instr_iterator insert(instr_iterator I, MachineInstr *M) {
		return Insts.insert(I, M);
		}
		instr_iterator insertAfter(instr_iterator I, MachineInstr *M) {
	return Insts.insertAfter(I, M);	return Insts.insertAfter(I, M);
	}	}


	// erase - Remove the specified element or range from the instruction lis	template<typename IT>
	t.	void insert(iterator I, IT S, IT E) {
	// These functions delete any instructions removed.	Insts.insert(I.getInstrIterator(), S, E);
	//	}
	iterator erase(iterator I) { return Insts.erase(I); }	iterator insert(iterator I, MachineInstr *M) {
	iterator erase(iterator I, iterator E) { return Insts.erase(I, E); }	return Insts.insert(I.getInstrIterator(), M);
	MachineInstr remove(MachineInstr I) { return Insts.remove(I); }	}
	void clear() { Insts.clear(); }	iterator insertAfter(iterator I, MachineInstr *M) {
		return Insts.insertAfter(I.getInstrIterator(), M);
		}

		/// erase - Remove the specified element or range from the instruction li
		st.
		/// These functions delete any instructions removed.
		///
		instr_iterator erase(instr_iterator I) {
		return Insts.erase(I);
		}
		instr_iterator erase(instr_iterator I, instr_iterator E) {
		return Insts.erase(I, E);
		}
		instr_iterator erase_instr(MachineInstr *I) {
		instr_iterator MII(I);
		return erase(MII);
		}

		iterator erase(iterator I);
		iterator erase(iterator I, iterator E) {
		return Insts.erase(I.getInstrIterator(), E.getInstrIterator());
		}
		iterator erase(MachineInstr *I) {
		iterator MII(I);
		return erase(MII);
		}

		/// remove - Remove the instruction from the instruction list. This funct
		ion
		/// does not delete the instruction. WARNING: Note, if the specified
		/// instruction is a bundle this function will remove all the bundled
		/// instructions as well. It is up to the caller to keep a list of the
		/// bundled instructions and re-insert them if desired. This function is
		/// not recommended for manipulating instructions with bundles. Use
		/// splice instead.
		MachineInstr remove(MachineInstr I);
		void clear() {
		Insts.clear();
		}

	/// splice - Take an instruction from MBB 'Other' at the position From,	/// splice - Take an instruction from MBB 'Other' at the position From,
	/// and insert it into this MBB right before 'where'.	/// and insert it into this MBB right before 'where'.

	void splice(iterator where, MachineBasicBlock *Other, iterator From) {	void splice(instr_iterator where, MachineBasicBlock *Other,
		instr_iterator From) {
	Insts.splice(where, Other->Insts, From);	Insts.splice(where, Other->Insts, From);
	}	}

		void splice(iterator where, MachineBasicBlock *Other, iterator From);

	/// splice - Take a block of instructions from MBB 'Other' in the range [ From,	/// splice - Take a block of instructions from MBB 'Other' in the range [ From,
	/// To), and insert them into this MBB right before 'where'.	/// To), and insert them into this MBB right before 'where'.

		void splice(instr_iterator where, MachineBasicBlock *Other, instr_iterato
		r From,
		instr_iterator To) {
		Insts.splice(where, Other->Insts, From, To);
		}
	void splice(iterator where, MachineBasicBlock *Other, iterator From,	void splice(iterator where, MachineBasicBlock *Other, iterator From,
	iterator To) {	iterator To) {

	Insts.splice(where, Other->Insts, From, To);	Insts.splice(where.getInstrIterator(), Other->Insts,
		From.getInstrIterator(), To.getInstrIterator());
	}	}

	/// removeFromParent - This method unlinks 'this' from the containing	/// removeFromParent - This method unlinks 'this' from the containing
	/// function, and returns it, but does not delete it.	/// function, and returns it, but does not delete it.
	MachineBasicBlock *removeFromParent();	MachineBasicBlock *removeFromParent();

	/// eraseFromParent - This method unlinks 'this' from the containing	/// eraseFromParent - This method unlinks 'this' from the containing
	/// function and deletes it.	/// function and deletes it.
	void eraseFromParent();	void eraseFromParent();


	skipping to change at line 397	skipping to change at line 567
	/// DestA and DestB, remove any other MBB successors from the CFG. DestA and	/// DestA and DestB, remove any other MBB successors from the CFG. DestA and
	/// DestB can be null. Besides DestA and DestB, retain other edges leadin g	/// DestB can be null. Besides DestA and DestB, retain other edges leadin g
	/// to LandingPads (currently there can be only one; we don't check or re quire	/// to LandingPads (currently there can be only one; we don't check or re quire
	/// that here). Note it is possible that DestA and/or DestB are LandingPa ds.	/// that here). Note it is possible that DestA and/or DestB are LandingPa ds.
	bool CorrectExtraCFGEdges(MachineBasicBlock *DestA,	bool CorrectExtraCFGEdges(MachineBasicBlock *DestA,
	MachineBasicBlock *DestB,	MachineBasicBlock *DestB,
	bool isCond);	bool isCond);

	/// findDebugLoc - find the next valid DebugLoc starting at MBBI, skippin g	/// findDebugLoc - find the next valid DebugLoc starting at MBBI, skippin g
	/// any DBG_VALUE instructions. Return UnknownLoc if there is none.	/// any DBG_VALUE instructions. Return UnknownLoc if there is none.

	DebugLoc findDebugLoc(MachineBasicBlock::iterator &MBBI);	DebugLoc findDebugLoc(instr_iterator MBBI);
		DebugLoc findDebugLoc(iterator MBBI) {
		return findDebugLoc(MBBI.getInstrIterator());
		}

	// Debugging methods.	// Debugging methods.
	void dump() const;	void dump() const;
	void print(raw_ostream &OS, SlotIndexes* = 0) const;	void print(raw_ostream &OS, SlotIndexes* = 0) const;

	/// getNumber - MachineBasicBlocks are uniquely numbered at the function	/// getNumber - MachineBasicBlocks are uniquely numbered at the function
	/// level, unless they're not in a MachineFunction yet, in which case thi s	/// level, unless they're not in a MachineFunction yet, in which case thi s
	/// will return -1.	/// will return -1.
	///	///
	int getNumber() const { return Number; }	int getNumber() const { return Number; }
	void setNumber(int N) { Number = N; }	void setNumber(int N) { Number = N; }

	/// getSymbol - Return the MCSymbol for this basic block.	/// getSymbol - Return the MCSymbol for this basic block.
	///	///
	MCSymbol *getSymbol() const;	MCSymbol *getSymbol() const;

	private:	private:
	/// getWeightIterator - Return weight iterator corresponding to the I	/// getWeightIterator - Return weight iterator corresponding to the I
	/// successor iterator.	/// successor iterator.
	weight_iterator getWeightIterator(succ_iterator I);	weight_iterator getWeightIterator(succ_iterator I);

		const_weight_iterator getWeightIterator(const_succ_iterator I) const;

	friend class MachineBranchProbabilityInfo;	friend class MachineBranchProbabilityInfo;

	/// getSuccWeight - Return weight of the edge from this block to MBB. Thi s	/// getSuccWeight - Return weight of the edge from this block to MBB. Thi s
	/// method should NOT be called directly, but by using getEdgeWeight meth od	/// method should NOT be called directly, but by using getEdgeWeight meth od
	/// from MachineBranchProbabilityInfo class.	/// from MachineBranchProbabilityInfo class.

	uint32_t getSuccWeight(MachineBasicBlock *succ);	uint32_t getSuccWeight(const MachineBasicBlock *succ) const;

	// Methods used to maintain doubly linked list of blocks...	// Methods used to maintain doubly linked list of blocks...
	friend struct ilist_traits<MachineBasicBlock>;	friend struct ilist_traits<MachineBasicBlock>;

	// Machine-CFG mutators	// Machine-CFG mutators

	/// addPredecessor - Remove pred as a predecessor of this MachineBasicBlo ck.	/// addPredecessor - Remove pred as a predecessor of this MachineBasicBlo ck.
	/// Don't do this unless you know what you're doing, because it doesn't	/// Don't do this unless you know what you're doing, because it doesn't
	/// update pred's successors list. Use pred->addSuccessor instead.	/// update pred's successors list. Use pred->addSuccessor instead.
	///	///

End of changes. 21 change blocks.
	31 lines changed or deleted	229 lines changed or added

	MachineBlockFrequencyInfo.h	MachineBlockFrequencyInfo.h

	skipping to change at line 23	skipping to change at line 23

	#ifndef LLVM_CODEGEN_MACHINEBLOCKFREQUENCYINFO_H	#ifndef LLVM_CODEGEN_MACHINEBLOCKFREQUENCYINFO_H
	#define LLVM_CODEGEN_MACHINEBLOCKFREQUENCYINFO_H	#define LLVM_CODEGEN_MACHINEBLOCKFREQUENCYINFO_H

	#include "llvm/CodeGen/MachineFunctionPass.h"	#include "llvm/CodeGen/MachineFunctionPass.h"
	#include "llvm/Support/BlockFrequency.h"	#include "llvm/Support/BlockFrequency.h"
	#include <climits>	#include <climits>

	namespace llvm {	namespace llvm {


		class MachineBasicBlock;
	class MachineBranchProbabilityInfo;	class MachineBranchProbabilityInfo;
	template<class BlockT, class FunctionT, class BranchProbInfoT>	template<class BlockT, class FunctionT, class BranchProbInfoT>
	class BlockFrequencyImpl;	class BlockFrequencyImpl;

	/// MachineBlockFrequencyInfo pass uses BlockFrequencyImpl implementation t o estimate	/// MachineBlockFrequencyInfo pass uses BlockFrequencyImpl implementation t o estimate
	/// machine basic block frequencies.	/// machine basic block frequencies.
	class MachineBlockFrequencyInfo : public MachineFunctionPass {	class MachineBlockFrequencyInfo : public MachineFunctionPass {


	BlockFrequencyImpl<MachineBasicBlock, MachineFunction, MachineBranchProba	BlockFrequencyImpl<MachineBasicBlock, MachineFunction,
	bilityInfo> *MBFI;	MachineBranchProbabilityInfo> *MBFI;

	public:	public:
	static char ID;	static char ID;

	MachineBlockFrequencyInfo();	MachineBlockFrequencyInfo();

	~MachineBlockFrequencyInfo();	~MachineBlockFrequencyInfo();

	void getAnalysisUsage(AnalysisUsage &AU) const;	void getAnalysisUsage(AnalysisUsage &AU) const;

	bool runOnMachineFunction(MachineFunction &F);	bool runOnMachineFunction(MachineFunction &F);

	/// getblockFreq - Return block frequency. Return 0 if we don't have the	/// getblockFreq - Return block frequency. Return 0 if we don't have the
	/// information. Please note that initial frequency is equal to 1024. It means	/// information. Please note that initial frequency is equal to 1024. It means
	/// that we should not rely on the value itself, but only on the comparis on to	/// that we should not rely on the value itself, but only on the comparis on to
	/// the other block frequencies. We do this to avoid using of floating po ints.	/// the other block frequencies. We do this to avoid using of floating po ints.
	///	///

	BlockFrequency getBlockFreq(MachineBasicBlock *MBB) const;	BlockFrequency getBlockFreq(const MachineBasicBlock *MBB) const;
	};	};

	}	}

	#endif	#endif

End of changes. 3 change blocks.
	3 lines changed or deleted	4 lines changed or added

	MachineBranchProbabilityInfo.h	MachineBranchProbabilityInfo.h

	skipping to change at line 28	skipping to change at line 28
	#include "llvm/Pass.h"	#include "llvm/Pass.h"
	#include "llvm/Support/BranchProbability.h"	#include "llvm/Support/BranchProbability.h"
	#include <climits>	#include <climits>

	namespace llvm {	namespace llvm {

	class raw_ostream;	class raw_ostream;
	class MachineBasicBlock;	class MachineBasicBlock;

	class MachineBranchProbabilityInfo : public ImmutablePass {	class MachineBranchProbabilityInfo : public ImmutablePass {

		virtual void anchor();

	// Default weight value. Used when we don't have information about the ed ge.	// Default weight value. Used when we don't have information about the ed ge.
	// TODO: DEFAULT_WEIGHT makes sense during static predication, when none of	// TODO: DEFAULT_WEIGHT makes sense during static predication, when none of
	// the successors have a weight yet. But it doesn't make sense when provi ding	// the successors have a weight yet. But it doesn't make sense when provi ding
	// weight to an edge that may have siblings with non-zero weights. This c an	// weight to an edge that may have siblings with non-zero weights. This c an
	// be handled various ways, but it's probably fine for an edge with unkno wn	// be handled various ways, but it's probably fine for an edge with unkno wn
	// weight to just "inherit" the non-zero weight of an adjacent successor.	// weight to just "inherit" the non-zero weight of an adjacent successor.
	static const uint32_t DEFAULT_WEIGHT = 16;	static const uint32_t DEFAULT_WEIGHT = 16;


	// Get sum of the block successors' weights.
	uint32_t getSumForBlock(MachineBasicBlock *MBB) const;

	public:	public:
	static char ID;	static char ID;

	MachineBranchProbabilityInfo() : ImmutablePass(ID) {	MachineBranchProbabilityInfo() : ImmutablePass(ID) {
	PassRegistry &Registry = *PassRegistry::getPassRegistry();	PassRegistry &Registry = *PassRegistry::getPassRegistry();
	initializeMachineBranchProbabilityInfoPass(Registry);	initializeMachineBranchProbabilityInfoPass(Registry);
	}	}

	void getAnalysisUsage(AnalysisUsage &AU) const {	void getAnalysisUsage(AnalysisUsage &AU) const {
	AU.setPreservesAll();	AU.setPreservesAll();
	}	}

	// Return edge weight. If we don't have any informations about it - retur n	// Return edge weight. If we don't have any informations about it - retur n
	// DEFAULT_WEIGHT.	// DEFAULT_WEIGHT.

	uint32_t getEdgeWeight(MachineBasicBlock Src, MachineBasicBlock Dst) co	uint32_t getEdgeWeight(const MachineBasicBlock *Src,
	nst;	const MachineBasicBlock *Dst) const;

		// Get sum of the block successors' weights, potentially scaling them to
		fit
		// within 32-bits. If scaling is required, sets Scale based on the necess
		ary
		// adjustment. Any edge weights used with the sum should be divided by Sc
		ale.
		uint32_t getSumForBlock(const MachineBasicBlock *MBB, uint32_t &Scale) co
		nst;

	// A 'Hot' edge is an edge which probability is >= 80%.	// A 'Hot' edge is an edge which probability is >= 80%.
	bool isEdgeHot(MachineBasicBlock Src, MachineBasicBlock Dst) const;	bool isEdgeHot(MachineBasicBlock Src, MachineBasicBlock Dst) const;

	// Return a hot successor for the block BB or null if there isn't one.	// Return a hot successor for the block BB or null if there isn't one.

		// NB: This routine's complexity is linear on the number of successors.
	MachineBasicBlock getHotSucc(MachineBasicBlock MBB) const;	MachineBasicBlock getHotSucc(MachineBasicBlock MBB) const;

	// Return a probability as a fraction between 0 (0% probability) and	// Return a probability as a fraction between 0 (0% probability) and
	// 1 (100% probability), however the value is never equal to 0, and can b e 1	// 1 (100% probability), however the value is never equal to 0, and can b e 1
	// only iff SRC block has only one successor.	// only iff SRC block has only one successor.

		// NB: This routine's complexity is linear on the number of successors of
		// Src. Querying sequentially for each successor's probability is a quadr
		atic
		// query pattern.
	BranchProbability getEdgeProbability(MachineBasicBlock *Src,	BranchProbability getEdgeProbability(MachineBasicBlock *Src,
	MachineBasicBlock *Dst) const;	MachineBasicBlock *Dst) const;

	// Print value between 0 (0% probability) and 1 (100% probability),	// Print value between 0 (0% probability) and 1 (100% probability),
	// however the value is never equal to 0, and can be 1 only iff SRC block	// however the value is never equal to 0, and can be 1 only iff SRC block
	// has only one successor.	// has only one successor.
	raw_ostream &printEdgeProbability(raw_ostream &OS, MachineBasicBlock *Src ,	raw_ostream &printEdgeProbability(raw_ostream &OS, MachineBasicBlock *Src ,
	MachineBasicBlock *Dst) const;	MachineBasicBlock *Dst) const;
	};	};


End of changes. 5 change blocks.
	5 lines changed or deleted	17 lines changed or added

	MachineCodeEmitter.h	MachineCodeEmitter.h

	skipping to change at line 23	skipping to change at line 23
	// machine code will be written (memory or disk, f.e.).	// machine code will be written (memory or disk, f.e.).
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_CODEGEN_MACHINECODEEMITTER_H	#ifndef LLVM_CODEGEN_MACHINECODEEMITTER_H
	#define LLVM_CODEGEN_MACHINECODEEMITTER_H	#define LLVM_CODEGEN_MACHINECODEEMITTER_H

	#include "llvm/Support/DataTypes.h"	#include "llvm/Support/DataTypes.h"
	#include "llvm/Support/DebugLoc.h"	#include "llvm/Support/DebugLoc.h"


		#include <string>

	namespace llvm {	namespace llvm {

	class MachineBasicBlock;	class MachineBasicBlock;
	class MachineConstantPool;	class MachineConstantPool;
	class MachineJumpTableInfo;	class MachineJumpTableInfo;
	class MachineFunction;	class MachineFunction;
	class MachineModuleInfo;	class MachineModuleInfo;
	class MachineRelocation;	class MachineRelocation;
	class Value;	class Value;
	class GlobalValue;	class GlobalValue;

	skipping to change at line 52	skipping to change at line 54
	/// we emit it. As such, we preallocate a certain amount of memory, and se t the	/// we emit it. As such, we preallocate a certain amount of memory, and se t the
	/// BufferBegin/BufferEnd pointers to the start and end of the buffer. As we	/// BufferBegin/BufferEnd pointers to the start and end of the buffer. As we
	/// emit machine instructions, we advance the CurBufferPtr to indicate the	/// emit machine instructions, we advance the CurBufferPtr to indicate the
	/// location of the next byte to emit. In the case of a buffer overflow (w e	/// location of the next byte to emit. In the case of a buffer overflow (w e
	/// need to emit more machine code than we have allocated space for), the	/// need to emit more machine code than we have allocated space for), the
	/// CurBufferPtr will saturate to BufferEnd and ignore stores. Once the en tire	/// CurBufferPtr will saturate to BufferEnd and ignore stores. Once the en tire
	/// function has been emitted, the overflow condition is checked, and if it has	/// function has been emitted, the overflow condition is checked, and if it has
	/// occurred, more memory is allocated, and we reemit the code into it.	/// occurred, more memory is allocated, and we reemit the code into it.
	///	///
	class MachineCodeEmitter {	class MachineCodeEmitter {

		virtual void anchor();
	protected:	protected:
	/// BufferBegin/BufferEnd - Pointers to the start and end of the memory	/// BufferBegin/BufferEnd - Pointers to the start and end of the memory
	/// allocated for this code buffer.	/// allocated for this code buffer.
	uint8_t BufferBegin, BufferEnd;	uint8_t BufferBegin, BufferEnd;
	/// CurBufferPtr - Pointer to the next byte of memory to fill when emitti ng	/// CurBufferPtr - Pointer to the next byte of memory to fill when emitti ng
	/// code. This is guaranteed to be in the range [BufferBegin,BufferEnd]. If	/// code. This is guaranteed to be in the range [BufferBegin,BufferEnd]. If
	/// this pointer is at BufferEnd, it will never move due to code emission , and	/// this pointer is at BufferEnd, it will never move due to code emission , and
	/// all code emission requests will be ignored (this is the buffer overfl ow	/// all code emission requests will be ignored (this is the buffer overfl ow
	/// condition).	/// condition).
	uint8_t *CurBufferPtr;	uint8_t *CurBufferPtr;

End of changes. 2 change blocks.
	0 lines changed or deleted	3 lines changed or added

	MachineConstantPool.h	MachineConstantPool.h

	skipping to change at line 37	skipping to change at line 37
	class FoldingSetNodeID;	class FoldingSetNodeID;
	class TargetData;	class TargetData;
	class TargetMachine;	class TargetMachine;
	class Type;	class Type;
	class MachineConstantPool;	class MachineConstantPool;
	class raw_ostream;	class raw_ostream;

	/// Abstract base class for all machine specific constantpool value subclas ses.	/// Abstract base class for all machine specific constantpool value subclas ses.
	///	///
	class MachineConstantPoolValue {	class MachineConstantPoolValue {

		virtual void anchor();
	Type *Ty;	Type *Ty;

	public:	public:
	explicit MachineConstantPoolValue(Type *ty) : Ty(ty) {}	explicit MachineConstantPoolValue(Type *ty) : Ty(ty) {}
	virtual ~MachineConstantPoolValue() {}	virtual ~MachineConstantPoolValue() {}

	/// getType - get type of this MachineConstantPoolValue.	/// getType - get type of this MachineConstantPoolValue.
	///	///
	Type *getType() const { return Ty; }	Type *getType() const { return Ty; }


End of changes. 1 change blocks.
	0 lines changed or deleted	1 lines changed or added

	MachineDominators.h	MachineDominators.h

	skipping to change at line 87	skipping to change at line 87
	}	}

	// dominates - Return true if A dominates B. This performs the	// dominates - Return true if A dominates B. This performs the
	// special checks necessary if A and B are in the same basic block.	// special checks necessary if A and B are in the same basic block.
	bool dominates(MachineInstr A, MachineInstr B) const {	bool dominates(MachineInstr A, MachineInstr B) const {
	MachineBasicBlock BBA = A->getParent(), BBB = B->getParent();	MachineBasicBlock BBA = A->getParent(), BBB = B->getParent();
	if (BBA != BBB) return DT->dominates(BBA, BBB);	if (BBA != BBB) return DT->dominates(BBA, BBB);

	// Loop through the basic block until we find A or B.	// Loop through the basic block until we find A or B.
	MachineBasicBlock::iterator I = BBA->begin();	MachineBasicBlock::iterator I = BBA->begin();

	for (; &I != A && &I != B; ++I) /empty/;	for (; &I != A && &I != B; ++I)
		/empty/ ;

	//if(!DT.IsPostDominators) {	//if(!DT.IsPostDominators) {
	// A dominates B if it is found first in the basic block.	// A dominates B if it is found first in the basic block.
	return &*I == A;	return &*I == A;
	//} else {	//} else {
	// // A post-dominates B if B is found first in the basic block.	// // A post-dominates B if B is found first in the basic block.
	// return &*I == B;	// return &*I == B;
	//}	//}
	}	}


End of changes. 1 change blocks.
	1 lines changed or deleted	2 lines changed or added

	MachineFunction.h	MachineFunction.h

	skipping to change at line 123	skipping to change at line 123
	BasicBlockListType BasicBlocks;	BasicBlockListType BasicBlocks;

	/// FunctionNumber - This provides a unique ID for each function emitted in	/// FunctionNumber - This provides a unique ID for each function emitted in
	/// this translation unit.	/// this translation unit.
	///	///
	unsigned FunctionNumber;	unsigned FunctionNumber;

	/// Alignment - The alignment of the function.	/// Alignment - The alignment of the function.
	unsigned Alignment;	unsigned Alignment;


	/// CallsSetJmp - True if the function calls setjmp or sigsetjmp. This is	/// ExposesReturnsTwice - True if the function calls setjmp or related
	used	/// functions with attribute "returns twice", but doesn't have
	/// to limit optimizations which cannot reason about the control flow of	/// the attribute itself.
	/// setjmp.	/// This is used to limit optimizations which cannot reason
	bool CallsSetJmp;	/// about the control flow of such functions.
		bool ExposesReturnsTwice;

	MachineFunction(const MachineFunction &); // DO NOT IMPLEMENT	MachineFunction(const MachineFunction &); // DO NOT IMPLEMENT
	void operator=(const MachineFunction&); // DO NOT IMPLEMENT	void operator=(const MachineFunction&); // DO NOT IMPLEMENT
	public:	public:
	MachineFunction(const Function *Fn, const TargetMachine &TM,	MachineFunction(const Function *Fn, const TargetMachine &TM,
	unsigned FunctionNum, MachineModuleInfo &MMI,	unsigned FunctionNum, MachineModuleInfo &MMI,
	GCModuleInfo* GMI);	GCModuleInfo* GMI);
	~MachineFunction();	~MachineFunction();

	MachineModuleInfo &getMMI() const { return MMI; }	MachineModuleInfo &getMMI() const { return MMI; }

	skipping to change at line 189	skipping to change at line 191
	const MachineConstantPool *getConstantPool() const { return ConstantPool; }	const MachineConstantPool *getConstantPool() const { return ConstantPool; }

	/// getAlignment - Return the alignment (log2, not bytes) of the function .	/// getAlignment - Return the alignment (log2, not bytes) of the function .
	///	///
	unsigned getAlignment() const { return Alignment; }	unsigned getAlignment() const { return Alignment; }

	/// setAlignment - Set the alignment (log2, not bytes) of the function.	/// setAlignment - Set the alignment (log2, not bytes) of the function.
	///	///
	void setAlignment(unsigned A) { Alignment = A; }	void setAlignment(unsigned A) { Alignment = A; }


	/// EnsureAlignment - Make sure the function is at least 'A' bits aligned .	/// EnsureAlignment - Make sure the function is at least 1 << A bytes ali gned.
	void EnsureAlignment(unsigned A) {	void EnsureAlignment(unsigned A) {
	if (Alignment < A) Alignment = A;	if (Alignment < A) Alignment = A;
	}	}


	/// callsSetJmp - Returns true if the function calls setjmp or sigsetjmp.	/// exposesReturnsTwice - Returns true if the function calls setjmp or
	bool callsSetJmp() const {	/// any other similar functions with attribute "returns twice" without
	return CallsSetJmp;	/// having the attribute itself.
		bool exposesReturnsTwice() const {
		return ExposesReturnsTwice;
	}	}


	/// setCallsSetJmp - Set a flag that indicates if there's a call to setjm	/// setCallsSetJmp - Set a flag that indicates if there's a call to
	p or	/// a "returns twice" function.
	/// sigsetjmp.	void setExposesReturnsTwice(bool B) {
	void setCallsSetJmp(bool B) {	ExposesReturnsTwice = B;
	CallsSetJmp = B;
	}	}

	/// getInfo - Keep track of various per-function pieces of information fo r	/// getInfo - Keep track of various per-function pieces of information fo r
	/// backends that would like to do so.	/// backends that would like to do so.
	///	///
	template<typename Ty>	template<typename Ty>
	Ty *getInfo() {	Ty *getInfo() {
	if (!MFInfo) {	if (!MFInfo) {
	// This should be just `new (Allocator.Allocate<Ty>()) Ty(*this)', but	// This should be just `new (Allocator.Allocate<Ty>()) Ty(*this)', but
	// that apparently breaks GCC 3.3.	// that apparently breaks GCC 3.3.

	skipping to change at line 378	skipping to change at line 382
	/// DeleteMachineBasicBlock - Delete the given MachineBasicBlock.	/// DeleteMachineBasicBlock - Delete the given MachineBasicBlock.
	///	///
	void DeleteMachineBasicBlock(MachineBasicBlock *MBB);	void DeleteMachineBasicBlock(MachineBasicBlock *MBB);

	/// getMachineMemOperand - Allocate a new MachineMemOperand.	/// getMachineMemOperand - Allocate a new MachineMemOperand.
	/// MachineMemOperands are owned by the MachineFunction and need not be	/// MachineMemOperands are owned by the MachineFunction and need not be
	/// explicitly deallocated.	/// explicitly deallocated.
	MachineMemOperand *getMachineMemOperand(MachinePointerInfo PtrInfo,	MachineMemOperand *getMachineMemOperand(MachinePointerInfo PtrInfo,
	unsigned f, uint64_t s,	unsigned f, uint64_t s,
	unsigned base_alignment,	unsigned base_alignment,

	const MDNode *TBAAInfo = 0);	const MDNode *TBAAInfo = 0,
		const MDNode *Ranges = 0);

	/// getMachineMemOperand - Allocate a new MachineMemOperand by copying	/// getMachineMemOperand - Allocate a new MachineMemOperand by copying
	/// an existing one, adjusting by an offset and using the given size.	/// an existing one, adjusting by an offset and using the given size.
	/// MachineMemOperands are owned by the MachineFunction and need not be	/// MachineMemOperands are owned by the MachineFunction and need not be
	/// explicitly deallocated.	/// explicitly deallocated.
	MachineMemOperand getMachineMemOperand(const MachineMemOperand MMO,	MachineMemOperand getMachineMemOperand(const MachineMemOperand MMO,
	int64_t Offset, uint64_t Size);	int64_t Offset, uint64_t Size);

	/// allocateMemRefsArray - Allocate an array to hold MachineMemOperand	/// allocateMemRefsArray - Allocate an array to hold MachineMemOperand
	/// pointers. This array is owned by the MachineFunction.	/// pointers. This array is owned by the MachineFunction.

	skipping to change at line 439	skipping to change at line 444
	template <> struct GraphTraits<MachineFunction*> :	template <> struct GraphTraits<MachineFunction*> :
	public GraphTraits<MachineBasicBlock*> {	public GraphTraits<MachineBasicBlock*> {
	static NodeType getEntryNode(MachineFunction F) {	static NodeType getEntryNode(MachineFunction F) {
	return &F->front();	return &F->front();
	}	}

	// nodes_iterator/begin/end - Allow iteration over all nodes in the graph	// nodes_iterator/begin/end - Allow iteration over all nodes in the graph
	typedef MachineFunction::iterator nodes_iterator;	typedef MachineFunction::iterator nodes_iterator;
	static nodes_iterator nodes_begin(MachineFunction *F) { return F->begin() ; }	static nodes_iterator nodes_begin(MachineFunction *F) { return F->begin() ; }
	static nodes_iterator nodes_end (MachineFunction *F) { return F->end(); }	static nodes_iterator nodes_end (MachineFunction *F) { return F->end(); }

		static unsigned size (MachineFunction *F) { return F->size(); }
	};	};
	template <> struct GraphTraits<const MachineFunction*> :	template <> struct GraphTraits<const MachineFunction*> :
	public GraphTraits<const MachineBasicBlock*> {	public GraphTraits<const MachineBasicBlock*> {
	static NodeType getEntryNode(const MachineFunction F) {	static NodeType getEntryNode(const MachineFunction F) {
	return &F->front();	return &F->front();
	}	}

	// nodes_iterator/begin/end - Allow iteration over all nodes in the graph	// nodes_iterator/begin/end - Allow iteration over all nodes in the graph
	typedef MachineFunction::const_iterator nodes_iterator;	typedef MachineFunction::const_iterator nodes_iterator;
	static nodes_iterator nodes_begin(const MachineFunction *F) {	static nodes_iterator nodes_begin(const MachineFunction *F) {
	return F->begin();	return F->begin();
	}	}
	static nodes_iterator nodes_end (const MachineFunction *F) {	static nodes_iterator nodes_end (const MachineFunction *F) {
	return F->end();	return F->end();
	}	}

		static unsigned size (const MachineFunction *F) {
		return F->size();
		}
	};	};

	// Provide specializations of GraphTraits to be able to treat a function as a	// Provide specializations of GraphTraits to be able to treat a function as a
	// graph of basic blocks... and to walk it in inverse order. Inverse order for	// graph of basic blocks... and to walk it in inverse order. Inverse order for
	// a function is considered to be when traversing the predecessor edges of a BB	// a function is considered to be when traversing the predecessor edges of a BB
	// instead of the successor edges.	// instead of the successor edges.
	//	//
	template <> struct GraphTraits<Inverse<MachineFunction*> > :	template <> struct GraphTraits<Inverse<MachineFunction*> > :
	public GraphTraits<Inverse<MachineBasicBlock*> > {	public GraphTraits<Inverse<MachineBasicBlock*> > {
	static NodeType getEntryNode(Inverse<MachineFunction> G) {	static NodeType getEntryNode(Inverse<MachineFunction> G) {

End of changes. 7 change blocks.
	15 lines changed or deleted	22 lines changed or added

	MachineFunctionAnalysis.h	MachineFunctionAnalysis.h

	skipping to change at line 29	skipping to change at line 29

	namespace llvm {	namespace llvm {

	class MachineFunction;	class MachineFunction;

	/// MachineFunctionAnalysis - This class is a Pass that manages a	/// MachineFunctionAnalysis - This class is a Pass that manages a
	/// MachineFunction object.	/// MachineFunction object.
	struct MachineFunctionAnalysis : public FunctionPass {	struct MachineFunctionAnalysis : public FunctionPass {
	private:	private:
	const TargetMachine &TM;	const TargetMachine &TM;

	CodeGenOpt::Level OptLevel;
	MachineFunction *MF;	MachineFunction *MF;
	unsigned NextFnNum;	unsigned NextFnNum;
	public:	public:
	static char ID;	static char ID;

	explicit MachineFunctionAnalysis(const TargetMachine &tm,	explicit MachineFunctionAnalysis(const TargetMachine &tm);
	CodeGenOpt::Level OL = CodeGenOpt::Defau
	lt);
	~MachineFunctionAnalysis();	~MachineFunctionAnalysis();

	MachineFunction &getMF() const { return *MF; }	MachineFunction &getMF() const { return *MF; }

	CodeGenOpt::Level getOptLevel() const { return OptLevel; }

	virtual const char* getPassName() const {	virtual const char* getPassName() const {
	return "Machine Function Analysis";	return "Machine Function Analysis";
	}	}

	private:	private:
	virtual bool doInitialization(Module &M);	virtual bool doInitialization(Module &M);
	virtual bool runOnFunction(Function &F);	virtual bool runOnFunction(Function &F);
	virtual void releaseMemory();	virtual void releaseMemory();
	virtual void getAnalysisUsage(AnalysisUsage &AU) const;	virtual void getAnalysisUsage(AnalysisUsage &AU) const;

End of changes. 3 change blocks.
	5 lines changed or deleted	1 lines changed or added

	MachineInstr.h	MachineInstr.h

	skipping to change at line 22	skipping to change at line 22
	// the back end.	// the back end.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_CODEGEN_MACHINEINSTR_H	#ifndef LLVM_CODEGEN_MACHINEINSTR_H
	#define LLVM_CODEGEN_MACHINEINSTR_H	#define LLVM_CODEGEN_MACHINEINSTR_H

	#include "llvm/CodeGen/MachineOperand.h"	#include "llvm/CodeGen/MachineOperand.h"
	#include "llvm/MC/MCInstrDesc.h"	#include "llvm/MC/MCInstrDesc.h"
	#include "llvm/Target/TargetOpcodes.h"	#include "llvm/Target/TargetOpcodes.h"

		#include "llvm/ADT/ArrayRef.h"
	#include "llvm/ADT/ilist.h"	#include "llvm/ADT/ilist.h"
	#include "llvm/ADT/ilist_node.h"	#include "llvm/ADT/ilist_node.h"
	#include "llvm/ADT/STLExtras.h"	#include "llvm/ADT/STLExtras.h"
	#include "llvm/ADT/StringRef.h"	#include "llvm/ADT/StringRef.h"
	#include "llvm/ADT/DenseMapInfo.h"	#include "llvm/ADT/DenseMapInfo.h"
	#include "llvm/Support/DebugLoc.h"	#include "llvm/Support/DebugLoc.h"
	#include <vector>	#include <vector>

	namespace llvm {	namespace llvm {


	skipping to change at line 56	skipping to change at line 57

	/// Flags to specify different kinds of comments to output in	/// Flags to specify different kinds of comments to output in
	/// assembly code. These flags carry semantic information not	/// assembly code. These flags carry semantic information not
	/// otherwise easily derivable from the IR text.	/// otherwise easily derivable from the IR text.
	///	///
	enum CommentFlag {	enum CommentFlag {
	ReloadReuse = 0x1	ReloadReuse = 0x1
	};	};

	enum MIFlag {	enum MIFlag {

	NoFlags = 0,	NoFlags = 0,
	FrameSetup = 1 << 0 // Instruction is used as a part of	FrameSetup = 1 << 0, // Instruction is used as a part of
	// function frame setup code.	// function frame setup code.

		InsideBundle = 1 << 1 // Instruction is inside a bundle (
		not
		// the first MI in a bundle)
	};	};
	private:	private:
	const MCInstrDesc *MCID; // Instruction descriptor.	const MCInstrDesc *MCID; // Instruction descriptor.

	uint8_t Flags; // Various bits of additional	uint8_t Flags; // Various bits of additional
	// information about machine	// information about machine
	// instruction.	// instruction.

	uint8_t AsmPrinterFlags; // Various bits of information used by	uint8_t AsmPrinterFlags; // Various bits of information used by
	// the AsmPrinter to emit helpful	// the AsmPrinter to emit helpful
	// comments. This is not semanti c	// comments. This is not semanti c
	// information. Do not use this fo r	// information. Do not use this fo r
	// anything other than to convey co mment	// anything other than to convey co mment
	// information to AsmPrinter.	// information to AsmPrinter.


		uint16_t NumMemRefs; // information on memory references
		mmo_iterator MemRefs;

	std::vector<MachineOperand> Operands; // the operands	std::vector<MachineOperand> Operands; // the operands

	mmo_iterator MemRefs; // information on memory references
	mmo_iterator MemRefsEnd;
	MachineBasicBlock *Parent; // Pointer to the owning basic bloc k.	MachineBasicBlock *Parent; // Pointer to the owning basic bloc k.
	DebugLoc debugLoc; // Source line information.	DebugLoc debugLoc; // Source line information.

	MachineInstr(const MachineInstr&); // DO NOT IMPLEMENT	MachineInstr(const MachineInstr&); // DO NOT IMPLEMENT
	void operator=(const MachineInstr&); // DO NOT IMPLEMENT	void operator=(const MachineInstr&); // DO NOT IMPLEMENT

	// Intrusive list support	// Intrusive list support
	friend struct ilist_traits<MachineInstr>;	friend struct ilist_traits<MachineInstr>;
	friend struct ilist_traits<MachineBasicBlock>;	friend struct ilist_traits<MachineBasicBlock>;
	void setParent(MachineBasicBlock *P) { Parent = P; }	void setParent(MachineBasicBlock *P) { Parent = P; }

	skipping to change at line 151	skipping to change at line 155
	bool getAsmPrinterFlag(CommentFlag Flag) const {	bool getAsmPrinterFlag(CommentFlag Flag) const {
	return AsmPrinterFlags & Flag;	return AsmPrinterFlags & Flag;
	}	}

	/// setAsmPrinterFlag - Set a flag for the AsmPrinter.	/// setAsmPrinterFlag - Set a flag for the AsmPrinter.
	///	///
	void setAsmPrinterFlag(CommentFlag Flag) {	void setAsmPrinterFlag(CommentFlag Flag) {
	AsmPrinterFlags \|= (uint8_t)Flag;	AsmPrinterFlags \|= (uint8_t)Flag;
	}	}


		/// clearAsmPrinterFlag - clear specific AsmPrinter flags
		///
		void clearAsmPrinterFlag(CommentFlag Flag) {
		AsmPrinterFlags &= ~Flag;
		}

	/// getFlags - Return the MI flags bitvector.	/// getFlags - Return the MI flags bitvector.
	uint8_t getFlags() const {	uint8_t getFlags() const {
	return Flags;	return Flags;
	}	}

	/// getFlag - Return whether an MI flag is set.	/// getFlag - Return whether an MI flag is set.
	bool getFlag(MIFlag Flag) const {	bool getFlag(MIFlag Flag) const {
	return Flags & Flag;	return Flags & Flag;
	}	}

	/// setFlag - Set a MI flag.	/// setFlag - Set a MI flag.
	void setFlag(MIFlag Flag) {	void setFlag(MIFlag Flag) {
	Flags \|= (uint8_t)Flag;	Flags \|= (uint8_t)Flag;
	}	}

	void setFlags(unsigned flags) {	void setFlags(unsigned flags) {
	Flags = flags;	Flags = flags;
	}	}


	/// clearAsmPrinterFlag - clear specific AsmPrinter flags	/// clearFlag - Clear a MI flag.
	///	void clearFlag(MIFlag Flag) {
	void clearAsmPrinterFlag(CommentFlag Flag) {	Flags &= ~((uint8_t)Flag);
	AsmPrinterFlags &= ~Flag;	}
	}
		/// isInsideBundle - Return true if MI is in a bundle (but not the first
		MI
		/// in a bundle).
		///
		/// A bundle looks like this before it's finalized:
		/// ----------------
		/// \| MI \|
		/// ----------------
		/// \|
		/// ----------------
		/// \| MI * \|
		/// ----------------
		/// \|
		/// ----------------
		/// \| MI * \|
		/// ----------------
		/// In this case, the first MI starts a bundle but is not inside a bundle
		, the
		/// next 2 MIs are considered "inside" the bundle.
		///
		/// After a bundle is finalized, it looks like this:
		/// ----------------
		/// \| Bundle \|
		/// ----------------
		/// \|
		/// ----------------
		/// \| MI * \|
		/// ----------------
		/// \|
		/// ----------------
		/// \| MI * \|
		/// ----------------
		/// \|
		/// ----------------
		/// \| MI * \|
		/// ----------------
		/// The first instruction has the special opcode "BUNDLE". It's not "insi
		de"
		/// a bundle, but the next three MIs are.
		bool isInsideBundle() const {
		return getFlag(InsideBundle);
		}

		/// setIsInsideBundle - Set InsideBundle bit.
		///
		void setIsInsideBundle(bool Val = true) {
		if (Val)
		setFlag(InsideBundle);
		else
		clearFlag(InsideBundle);
		}

		/// isBundled - Return true if this instruction part of a bundle. This is
		true
		/// if either itself or its following instruction is marked "InsideBundle
		".
		bool isBundled() const;

	/// getDebugLoc - Returns the debug location id of this MachineInstr.	/// getDebugLoc - Returns the debug location id of this MachineInstr.
	///	///
	DebugLoc getDebugLoc() const { return debugLoc; }	DebugLoc getDebugLoc() const { return debugLoc; }

	/// emitError - Emit an error referring to the source location of this	/// emitError - Emit an error referring to the source location of this
	/// instruction. This should only be used for inline assembly that is som ehow	/// instruction. This should only be used for inline assembly that is som ehow
	/// impossible to compile. Other errors should have been handled much	/// impossible to compile. Other errors should have been handled much
	/// earlier.	/// earlier.
	///	///

	skipping to change at line 226	skipping to change at line 288
	typedef std::vector<MachineOperand>::const_iterator const_mop_iterator;	typedef std::vector<MachineOperand>::const_iterator const_mop_iterator;

	mop_iterator operands_begin() { return Operands.begin(); }	mop_iterator operands_begin() { return Operands.begin(); }
	mop_iterator operands_end() { return Operands.end(); }	mop_iterator operands_end() { return Operands.end(); }

	const_mop_iterator operands_begin() const { return Operands.begin(); }	const_mop_iterator operands_begin() const { return Operands.begin(); }
	const_mop_iterator operands_end() const { return Operands.end(); }	const_mop_iterator operands_end() const { return Operands.end(); }

	/// Access to memory operands of the instruction	/// Access to memory operands of the instruction
	mmo_iterator memoperands_begin() const { return MemRefs; }	mmo_iterator memoperands_begin() const { return MemRefs; }

	mmo_iterator memoperands_end() const { return MemRefsEnd; }	mmo_iterator memoperands_end() const { return MemRefs + NumMemRefs; }
	bool memoperands_empty() const { return MemRefsEnd == MemRefs; }	bool memoperands_empty() const { return NumMemRefs == 0; }

	/// hasOneMemOperand - Return true if this instruction has exactly one	/// hasOneMemOperand - Return true if this instruction has exactly one
	/// MachineMemOperand.	/// MachineMemOperand.
	bool hasOneMemOperand() const {	bool hasOneMemOperand() const {

	return MemRefsEnd - MemRefs == 1;	return NumMemRefs == 1;
		}

		/// API for querying MachineInstr properties. They are the same as MCInst
		rDesc
		/// queries but they are bundle aware.

		enum QueryType {
		IgnoreBundle, // Ignore bundles
		AnyInBundle, // Return true if any instruction in bundle has proper
		ty
		AllInBundle // Return true if all instructions in bundle have prop
		erty
		};

		/// hasProperty - Return true if the instruction (or in the case of a bun
		dle,
		/// the instructions inside the bundle) has the specified property.
		/// The first argument is the property being queried.
		/// The second argument indicates whether the query should look inside
		/// instruction bundles.
		bool hasProperty(unsigned MCFlag, QueryType Type = AnyInBundle) const {
		// Inline the fast path.
		if (Type == IgnoreBundle \|\| !isBundle())
		return getDesc().getFlags() & (1 << MCFlag);

		// If we have a bundle, take the slow path.
		return hasPropertyInBundle(1 << MCFlag, Type);
		}

		/// isVariadic - Return true if this instruction can have a variable numb
		er of
		/// operands. In this case, the variable operands will be after the norm
		al
		/// operands but before the implicit definitions and uses (if any are
		/// present).
		bool isVariadic(QueryType Type = IgnoreBundle) const {
		return hasProperty(MCID::Variadic, Type);
		}

		/// hasOptionalDef - Set if this instruction has an optional definition,
		e.g.
		/// ARM instructions which can set condition code if 's' bit is set.
		bool hasOptionalDef(QueryType Type = IgnoreBundle) const {
		return hasProperty(MCID::HasOptionalDef, Type);
		}

		/// isPseudo - Return true if this is a pseudo instruction that doesn't
		/// correspond to a real machine instruction.
		///
		bool isPseudo(QueryType Type = IgnoreBundle) const {
		return hasProperty(MCID::Pseudo, Type);
		}

		bool isReturn(QueryType Type = AnyInBundle) const {
		return hasProperty(MCID::Return, Type);
		}

		bool isCall(QueryType Type = AnyInBundle) const {
		return hasProperty(MCID::Call, Type);
		}

		/// isBarrier - Returns true if the specified instruction stops control f
		low
		/// from executing the instruction immediately following it. Examples in
		clude
		/// unconditional branches and return instructions.
		bool isBarrier(QueryType Type = AnyInBundle) const {
		return hasProperty(MCID::Barrier, Type);
		}

		/// isTerminator - Returns true if this instruction part of the terminato
		r for
		/// a basic block. Typically this is things like return and branch
		/// instructions.
		///
		/// Various passes use this to insert code into the bottom of a basic blo
		ck,
		/// but before control flow occurs.
		bool isTerminator(QueryType Type = AnyInBundle) const {
		return hasProperty(MCID::Terminator, Type);
		}

		/// isBranch - Returns true if this is a conditional, unconditional, or
		/// indirect branch. Predicates below can be used to discriminate betwee
		n
		/// these cases, and the TargetInstrInfo::AnalyzeBranch method can be use
		d to
		/// get more information.
		bool isBranch(QueryType Type = AnyInBundle) const {
		return hasProperty(MCID::Branch, Type);
		}

		/// isIndirectBranch - Return true if this is an indirect branch, such as
		a
		/// branch through a register.
		bool isIndirectBranch(QueryType Type = AnyInBundle) const {
		return hasProperty(MCID::IndirectBranch, Type);
		}

		/// isConditionalBranch - Return true if this is a branch which may fall
		/// through to the next instruction or may transfer control flow to some
		other
		/// block. The TargetInstrInfo::AnalyzeBranch method can be used to get
		more
		/// information about this branch.
		bool isConditionalBranch(QueryType Type = AnyInBundle) const {
		return isBranch(Type) & !isBarrier(Type) & !isIndirectBranch(Type);
		}

		/// isUnconditionalBranch - Return true if this is a branch which always
		/// transfers control flow to some other block. The
		/// TargetInstrInfo::AnalyzeBranch method can be used to get more informa
		tion
		/// about this branch.
		bool isUnconditionalBranch(QueryType Type = AnyInBundle) const {
		return isBranch(Type) & isBarrier(Type) & !isIndirectBranch(Type);
		}

		// isPredicable - Return true if this instruction has a predicate operand
		that
		// controls execution. It may be set to 'always', or may be set to other
		/// values. There are various methods in TargetInstrInfo that can be us
		ed to
		/// control and modify the predicate in this instruction.
		bool isPredicable(QueryType Type = AllInBundle) const {
		// If it's a bundle than all bundled instructions must be predicable fo
		r this
		// to return true.
		return hasProperty(MCID::Predicable, Type);
		}

		/// isCompare - Return true if this instruction is a comparison.
		bool isCompare(QueryType Type = IgnoreBundle) const {
		return hasProperty(MCID::Compare, Type);
		}

		/// isMoveImmediate - Return true if this instruction is a move immediate
		/// (including conditional moves) instruction.
		bool isMoveImmediate(QueryType Type = IgnoreBundle) const {
		return hasProperty(MCID::MoveImm, Type);
		}

		/// isBitcast - Return true if this instruction is a bitcast instruction.
		///
		bool isBitcast(QueryType Type = IgnoreBundle) const {
		return hasProperty(MCID::Bitcast, Type);
		}

		/// isNotDuplicable - Return true if this instruction cannot be safely
		/// duplicated. For example, if the instruction has a unique labels atta
		ched
		/// to it, duplicating it would cause multiple definition errors.
		bool isNotDuplicable(QueryType Type = AnyInBundle) const {
		return hasProperty(MCID::NotDuplicable, Type);
		}

		/// hasDelaySlot - Returns true if the specified instruction has a delay
		slot
		/// which must be filled by the code generator.
		bool hasDelaySlot(QueryType Type = AnyInBundle) const {
		return hasProperty(MCID::DelaySlot, Type);
		}

		/// canFoldAsLoad - Return true for instructions that can be folded as
		/// memory operands in other instructions. The most common use for this
		/// is instructions that are simple loads from memory that don't modify
		/// the loaded value in any way, but it can also be used for instructions
		/// that can be expressed as constant-pool loads, such as V_SETALLONES
		/// on x86, to allow them to be folded when it is beneficial.
		/// This should only be set on instructions that return a value in their
		/// only virtual register definition.
		bool canFoldAsLoad(QueryType Type = IgnoreBundle) const {
		return hasProperty(MCID::FoldableAsLoad, Type);
		}

		//===--------------------------------------------------------------------
		===//
		// Side Effect Analysis
		//===--------------------------------------------------------------------
		===//

		/// mayLoad - Return true if this instruction could possibly read memory.
		/// Instructions with this flag set are not necessarily simple load
		/// instructions, they may load a value and modify it, for example.
		bool mayLoad(QueryType Type = AnyInBundle) const {
		return hasProperty(MCID::MayLoad, Type);
		}

		/// mayStore - Return true if this instruction could possibly modify memo
		ry.
		/// Instructions with this flag set are not necessarily simple store
		/// instructions, they may store a modified value based on their operands
		, or
		/// may not actually modify anything, for example.
		bool mayStore(QueryType Type = AnyInBundle) const {
		return hasProperty(MCID::MayStore, Type);
		}

		//===--------------------------------------------------------------------
		===//
		// Flags that indicate whether an instruction can be modified by a method
		.
		//===--------------------------------------------------------------------
		===//

		/// isCommutable - Return true if this may be a 2- or 3-address
		/// instruction (of the form "X = op Y, Z, ..."), which produces the same
		/// result if Y and Z are exchanged. If this flag is set, then the
		/// TargetInstrInfo::commuteInstruction method may be used to hack on the
		/// instruction.
		///
		/// Note that this flag may be set on instructions that are only commutab
		le
		/// sometimes. In these cases, the call to commuteInstruction will fail.
		/// Also note that some instructions require non-trivial modification to
		/// commute them.
		bool isCommutable(QueryType Type = IgnoreBundle) const {
		return hasProperty(MCID::Commutable, Type);
		}

		/// isConvertibleTo3Addr - Return true if this is a 2-address instruction
		/// which can be changed into a 3-address instruction if needed. Doing t
		his
		/// transformation can be profitable in the register allocator, because i
		t
		/// means that the instruction can use a 2-address form if possible, but
		/// degrade into a less efficient form if the source and dest register ca
		nnot
		/// be assigned to the same register. For example, this allows the x86
		/// backend to turn a "shl reg, 3" instruction into an LEA instruction, w
		hich
		/// is the same speed as the shift but has bigger code size.
		///
		/// If this returns true, then the target must implement the
		/// TargetInstrInfo::convertToThreeAddress method for this instruction, w
		hich
		/// is allowed to fail if the transformation isn't valid for this specifi
		c
		/// instruction (e.g. shl reg, 4 on x86).
		///
		bool isConvertibleTo3Addr(QueryType Type = IgnoreBundle) const {
		return hasProperty(MCID::ConvertibleTo3Addr, Type);
		}

		/// usesCustomInsertionHook - Return true if this instruction requires
		/// custom insertion support when the DAG scheduler is inserting it into
		a
		/// machine basic block. If this is true for the instruction, it basical
		ly
		/// means that it is a pseudo instruction used at SelectionDAG time that
		is
		/// expanded out into magic code by the target when MachineInstrs are for
		med.
		///
		/// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock meth
		od
		/// is used to insert this into the MachineBasicBlock.
		bool usesCustomInsertionHook(QueryType Type = IgnoreBundle) const {
		return hasProperty(MCID::UsesCustomInserter, Type);
		}

		/// hasPostISelHook - Return true if this instruction requires *adjustmen
		t*
		/// after instruction selection by calling a target hook. For example, th
		is
		/// can be used to fill in ARM 's' optional operand depending on whether
		/// the conditional flag register is used.
		bool hasPostISelHook(QueryType Type = IgnoreBundle) const {
		return hasProperty(MCID::HasPostISelHook, Type);
		}

		/// isRematerializable - Returns true if this instruction is a candidate
		for
		/// remat. This flag is deprecated, please don't use it anymore. If thi
		s
		/// flag is set, the isReallyTriviallyReMaterializable() method is called
		to
		/// verify the instruction is really rematable.
		bool isRematerializable(QueryType Type = AllInBundle) const {
		// It's only possible to re-mat a bundle if all bundled instructions ar
		e
		// re-materializable.
		return hasProperty(MCID::Rematerializable, Type);
		}

		/// isAsCheapAsAMove - Returns true if this instruction has the same cost
		(or
		/// less) than a move instruction. This is useful during certain types of
		/// optimizations (e.g., remat during two-address conversion or machine l
		icm)
		/// where we would like to remat or hoist the instruction, but not if it
		costs
		/// more than moving the instruction into the appropriate register. Note,
		we
		/// are not marking copies from and to the same register class with this
		flag.
		bool isAsCheapAsAMove(QueryType Type = AllInBundle) const {
		// Only returns true for a bundle if all bundled instructions are cheap
		.
		// FIXME: This probably requires a target hook.
		return hasProperty(MCID::CheapAsAMove, Type);
		}

		/// hasExtraSrcRegAllocReq - Returns true if this instruction source oper
		ands
		/// have special register allocation requirements that are not captured b
		y the
		/// operand register classes. e.g. ARM::STRD's two source registers must
		be an
		/// even / odd pair, ARM::STM registers have to be in ascending order.
		/// Post-register allocation passes should not attempt to change allocati
		ons
		/// for sources of instructions with this flag.
		bool hasExtraSrcRegAllocReq(QueryType Type = AnyInBundle) const {
		return hasProperty(MCID::ExtraSrcRegAllocReq, Type);
		}

		/// hasExtraDefRegAllocReq - Returns true if this instruction def operand
		s
		/// have special register allocation requirements that are not captured b
		y the
		/// operand register classes. e.g. ARM::LDRD's two def registers must be
		an
		/// even / odd pair, ARM::LDM registers have to be in ascending order.
		/// Post-register allocation passes should not attempt to change allocati
		ons
		/// for definitions of instructions with this flag.
		bool hasExtraDefRegAllocReq(QueryType Type = AnyInBundle) const {
		return hasProperty(MCID::ExtraDefRegAllocReq, Type);
	}	}

	enum MICheckType {	enum MICheckType {
	CheckDefs, // Check all operands for equality	CheckDefs, // Check all operands for equality
	CheckKillDead, // Check all operands including kill / dead markers	CheckKillDead, // Check all operands including kill / dead markers
	IgnoreDefs, // Ignore all definitions	IgnoreDefs, // Ignore all definitions
	IgnoreVRegDefs // Ignore virtual register definitions	IgnoreVRegDefs // Ignore virtual register definitions
	};	};

	/// isIdenticalTo - Return true if this instruction is identical to (same	/// isIdenticalTo - Return true if this instruction is identical to (same

	skipping to change at line 284	skipping to change at line 614
	bool isStackAligningInlineAsm() const;	bool isStackAligningInlineAsm() const;
	bool isInsertSubreg() const {	bool isInsertSubreg() const {
	return getOpcode() == TargetOpcode::INSERT_SUBREG;	return getOpcode() == TargetOpcode::INSERT_SUBREG;
	}	}
	bool isSubregToReg() const {	bool isSubregToReg() const {
	return getOpcode() == TargetOpcode::SUBREG_TO_REG;	return getOpcode() == TargetOpcode::SUBREG_TO_REG;
	}	}
	bool isRegSequence() const {	bool isRegSequence() const {
	return getOpcode() == TargetOpcode::REG_SEQUENCE;	return getOpcode() == TargetOpcode::REG_SEQUENCE;
	}	}

		bool isBundle() const {
		return getOpcode() == TargetOpcode::BUNDLE;
		}
	bool isCopy() const {	bool isCopy() const {
	return getOpcode() == TargetOpcode::COPY;	return getOpcode() == TargetOpcode::COPY;
	}	}
	bool isFullCopy() const {	bool isFullCopy() const {
	return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubR eg();	return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubR eg();
	}	}

	/// isCopyLike - Return true if the instruction behaves like a copy.	/// isCopyLike - Return true if the instruction behaves like a copy.
	/// This does not include native copy instructions.	/// This does not include native copy instructions.
	bool isCopyLike() const {	bool isCopyLike() const {
	return isCopy() \|\| isSubregToReg();	return isCopy() \|\| isSubregToReg();
	}	}

	/// isIdentityCopy - Return true is the instruction is an identity copy.	/// isIdentityCopy - Return true is the instruction is an identity copy.
	bool isIdentityCopy() const {	bool isIdentityCopy() const {
	return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() &&	return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() &&
	getOperand(0).getSubReg() == getOperand(1).getSubReg();	getOperand(0).getSubReg() == getOperand(1).getSubReg();
	}	}


		/// getBundleSize - Return the number of instructions inside the MI bundl
		e.
		unsigned getBundleSize() const;

	/// readsRegister - Return true if the MachineInstr reads the specified	/// readsRegister - Return true if the MachineInstr reads the specified
	/// register. If TargetRegisterInfo is passed, then it also checks if the re	/// register. If TargetRegisterInfo is passed, then it also checks if the re
	/// is a read of a super-register.	/// is a read of a super-register.
	/// This does not count partial redefines of virtual registers as reads:	/// This does not count partial redefines of virtual registers as reads:
	/// %reg1024:6 = OP.	/// %reg1024:6 = OP.
	bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) co nst {	bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) co nst {
	return findRegisterUseOperandIdx(Reg, false, TRI) != -1;	return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
	}	}

	/// readsVirtualRegister - Return true if the MachineInstr reads the spec ified	/// readsVirtualRegister - Return true if the MachineInstr reads the spec ified

	skipping to change at line 375	skipping to change at line 711
	const TargetRegisterInfo *TRI = NU LL) {	const TargetRegisterInfo *TRI = NU LL) {
	int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);	int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
	return (Idx == -1) ? NULL : &getOperand(Idx);	return (Idx == -1) ? NULL : &getOperand(Idx);
	}	}

	/// findRegisterDefOperandIdx() - Returns the operand index that is a def of	/// findRegisterDefOperandIdx() - Returns the operand index that is a def of
	/// the specified register or -1 if it is not found. If isDead is true, d efs	/// the specified register or -1 if it is not found. If isDead is true, d efs
	/// that are not dead are skipped. If Overlap is true, then it also looks for	/// that are not dead are skipped. If Overlap is true, then it also looks for
	/// defs that merely overlap the specified register. If TargetRegisterInf o is	/// defs that merely overlap the specified register. If TargetRegisterInf o is
	/// non-null, then it also checks if there is a def of a super-register.	/// non-null, then it also checks if there is a def of a super-register.

		/// This may also return a register mask operand when Overlap is true.
	int findRegisterDefOperandIdx(unsigned Reg,	int findRegisterDefOperandIdx(unsigned Reg,
	bool isDead = false, bool Overlap = false,	bool isDead = false, bool Overlap = false,
	const TargetRegisterInfo *TRI = NULL) const ;	const TargetRegisterInfo *TRI = NULL) const ;

	/// findRegisterDefOperand - Wrapper for findRegisterDefOperandIdx, it re turns	/// findRegisterDefOperand - Wrapper for findRegisterDefOperandIdx, it re turns
	/// a pointer to the MachineOperand rather than an index.	/// a pointer to the MachineOperand rather than an index.
	MachineOperand *findRegisterDefOperand(unsigned Reg, bool isDead = false,	MachineOperand *findRegisterDefOperand(unsigned Reg, bool isDead = false,
	const TargetRegisterInfo *TRI = NU LL) {	const TargetRegisterInfo *TRI = NU LL) {
	int Idx = findRegisterDefOperandIdx(Reg, isDead, false, TRI);	int Idx = findRegisterDefOperandIdx(Reg, isDead, false, TRI);
	return (Idx == -1) ? NULL : &getOperand(Idx);	return (Idx == -1) ? NULL : &getOperand(Idx);

	skipping to change at line 419	skipping to change at line 756
	/// determined.	/// determined.
	///	///
	const TargetRegisterClass*	const TargetRegisterClass*
	getRegClassConstraint(unsigned OpIdx,	getRegClassConstraint(unsigned OpIdx,
	const TargetInstrInfo *TII,	const TargetInstrInfo *TII,
	const TargetRegisterInfo *TRI) const;	const TargetRegisterInfo *TRI) const;

	/// isRegTiedToUseOperand - Given the index of a register def operand,	/// isRegTiedToUseOperand - Given the index of a register def operand,
	/// check if the register def is tied to a source operand, due to either	/// check if the register def is tied to a source operand, due to either
	/// two-address elimination or inline assembly constraints. Returns the	/// two-address elimination or inline assembly constraints. Returns the

	/// first tied use operand index by reference is UseOpIdx is not null.	/// first tied use operand index by reference if UseOpIdx is not null.
	bool isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx = 0) con st;	bool isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx = 0) con st;

	/// isRegTiedToDefOperand - Return true if the use operand of the specifi ed	/// isRegTiedToDefOperand - Return true if the use operand of the specifi ed
	/// index is tied to an def operand. It also returns the def operand inde x by	/// index is tied to an def operand. It also returns the def operand inde x by
	/// reference if DefOpIdx is not null.	/// reference if DefOpIdx is not null.
	bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx = 0) con st;	bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx = 0) con st;

	/// clearKillInfo - Clears kill flags on all operands.	/// clearKillInfo - Clears kill flags on all operands.
	///	///
	void clearKillInfo();	void clearKillInfo();

	skipping to change at line 451	skipping to change at line 788
	const TargetRegisterInfo &RegInfo);	const TargetRegisterInfo &RegInfo);

	/// addRegisterKilled - We have determined MI kills a register. Look for the	/// addRegisterKilled - We have determined MI kills a register. Look for the
	/// operand that uses it and mark it as IsKill. If AddIfNotFound is true,	/// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
	/// add a implicit operand if it's not found. Returns true if the operand	/// add a implicit operand if it's not found. Returns true if the operand
	/// exists / is added.	/// exists / is added.
	bool addRegisterKilled(unsigned IncomingReg,	bool addRegisterKilled(unsigned IncomingReg,
	const TargetRegisterInfo *RegInfo,	const TargetRegisterInfo *RegInfo,
	bool AddIfNotFound = false);	bool AddIfNotFound = false);


		/// clearRegisterKills - Clear all kill flags affecting Reg. If RegInfo
		is
		/// provided, this includes super-register kills.
		void clearRegisterKills(unsigned Reg, const TargetRegisterInfo *RegInfo);

	/// addRegisterDead - We have determined MI defined a register without a use.	/// addRegisterDead - We have determined MI defined a register without a use.
	/// Look for the operand that defines it and mark it as IsDead. If	/// Look for the operand that defines it and mark it as IsDead. If
	/// AddIfNotFound is true, add a implicit operand if it's not found. Retu rns	/// AddIfNotFound is true, add a implicit operand if it's not found. Retu rns
	/// true if the operand exists / is added.	/// true if the operand exists / is added.
	bool addRegisterDead(unsigned IncomingReg, const TargetRegisterInfo *RegI nfo,	bool addRegisterDead(unsigned IncomingReg, const TargetRegisterInfo *RegI nfo,
	bool AddIfNotFound = false);	bool AddIfNotFound = false);

	/// addRegisterDefined - We have determined MI defines a register. Make s ure	/// addRegisterDefined - We have determined MI defines a register. Make s ure
	/// there is an operand defining Reg.	/// there is an operand defining Reg.
	void addRegisterDefined(unsigned IncomingReg,	void addRegisterDefined(unsigned IncomingReg,
	const TargetRegisterInfo *RegInfo = 0);	const TargetRegisterInfo *RegInfo = 0);

	/// setPhysRegsDeadExcept - Mark every physreg used by this instruction a s	/// setPhysRegsDeadExcept - Mark every physreg used by this instruction a s
	/// dead except those in the UsedRegs list.	/// dead except those in the UsedRegs list.

	void setPhysRegsDeadExcept(const SmallVectorImpl<unsigned> &UsedRegs,	///
		/// On instructions with register mask operands, also add implicit-def
		/// operands for all registers in UsedRegs.
		void setPhysRegsDeadExcept(ArrayRef<unsigned> UsedRegs,
	const TargetRegisterInfo &TRI);	const TargetRegisterInfo &TRI);

	/// isSafeToMove - Return true if it is safe to move this instruction. If	/// isSafeToMove - Return true if it is safe to move this instruction. If
	/// SawStore is set to true, it means that there is a store (or call) bet ween	/// SawStore is set to true, it means that there is a store (or call) bet ween
	/// the instruction's location and its intended destination.	/// the instruction's location and its intended destination.
	bool isSafeToMove(const TargetInstrInfo TII, AliasAnalysis AA,	bool isSafeToMove(const TargetInstrInfo TII, AliasAnalysis AA,
	bool &SawStore) const;	bool &SawStore) const;

	/// isSafeToReMat - Return true if it's safe to rematerialize the specifi ed	/// isSafeToReMat - Return true if it's safe to rematerialize the specifi ed
	/// instruction which defined the specified register instead of copying i t.	/// instruction which defined the specified register instead of copying i t.

	skipping to change at line 553	skipping to change at line 897

	/// addMemOperand - Add a MachineMemOperand to the machine instruction.	/// addMemOperand - Add a MachineMemOperand to the machine instruction.
	/// This function should be used only occasionally. The setMemRefs functi on	/// This function should be used only occasionally. The setMemRefs functi on
	/// is the primary method for setting up a MachineInstr's MemRefs list.	/// is the primary method for setting up a MachineInstr's MemRefs list.
	void addMemOperand(MachineFunction &MF, MachineMemOperand *MO);	void addMemOperand(MachineFunction &MF, MachineMemOperand *MO);

	/// setMemRefs - Assign this MachineInstr's memory reference descriptor	/// setMemRefs - Assign this MachineInstr's memory reference descriptor
	/// list. This does not transfer ownership.	/// list. This does not transfer ownership.
	void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd) {	void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd) {
	MemRefs = NewMemRefs;	MemRefs = NewMemRefs;

	MemRefsEnd = NewMemRefsEnd;	NumMemRefs = NewMemRefsEnd - NewMemRefs;
	}	}

	private:	private:
	/// getRegInfo - If this instruction is embedded into a MachineFunction,	/// getRegInfo - If this instruction is embedded into a MachineFunction,
	/// return the MachineRegisterInfo object for the current function, other wise	/// return the MachineRegisterInfo object for the current function, other wise
	/// return null.	/// return null.
	MachineRegisterInfo *getRegInfo();	MachineRegisterInfo *getRegInfo();

	/// addImplicitDefUseOperands - Add all implicit def and use operands to	/// addImplicitDefUseOperands - Add all implicit def and use operands to
	/// this instruction.	/// this instruction.

	skipping to change at line 575	skipping to change at line 919

	/// RemoveRegOperandsFromUseLists - Unlink all of the register operands i n	/// RemoveRegOperandsFromUseLists - Unlink all of the register operands i n
	/// this instruction from their respective use lists. This requires that the	/// this instruction from their respective use lists. This requires that the
	/// operands already be on their use lists.	/// operands already be on their use lists.
	void RemoveRegOperandsFromUseLists();	void RemoveRegOperandsFromUseLists();

	/// AddRegOperandsToUseLists - Add all of the register operands in	/// AddRegOperandsToUseLists - Add all of the register operands in
	/// this instruction from their respective use lists. This requires that the	/// this instruction from their respective use lists. This requires that the
	/// operands not be on their use lists yet.	/// operands not be on their use lists yet.
	void AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo);	void AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo);


		/// hasPropertyInBundle - Slow path for hasProperty when we're dealing wi
		th a
		/// bundle.
		bool hasPropertyInBundle(unsigned Mask, QueryType Type) const;
	};	};

	/// MachineInstrExpressionTrait - Special DenseMapInfo traits to compare	/// MachineInstrExpressionTrait - Special DenseMapInfo traits to compare
	/// MachineInstr* by value of the instruction rather than by pointer valu e.	/// MachineInstr* by value of the instruction rather than by pointer valu e.
	/// The hashing and equality testing functions ignore definitions so this i s	/// The hashing and equality testing functions ignore definitions so this i s
	/// useful for CSE, etc.	/// useful for CSE, etc.
	struct MachineInstrExpressionTrait : DenseMapInfo<MachineInstr*> {	struct MachineInstrExpressionTrait : DenseMapInfo<MachineInstr*> {
	static inline MachineInstr *getEmptyKey() {	static inline MachineInstr *getEmptyKey() {
	return 0;	return 0;
	}	}

End of changes. 17 change blocks.
	15 lines changed or deleted	433 lines changed or added

	MachineInstrBuilder.h	MachineInstrBuilder.h

	skipping to change at line 37	skipping to change at line 37

	namespace RegState {	namespace RegState {
	enum {	enum {
	Define = 0x2,	Define = 0x2,
	Implicit = 0x4,	Implicit = 0x4,
	Kill = 0x8,	Kill = 0x8,
	Dead = 0x10,	Dead = 0x10,
	Undef = 0x20,	Undef = 0x20,
	EarlyClobber = 0x40,	EarlyClobber = 0x40,
	Debug = 0x80,	Debug = 0x80,

		DefineNoRead = Define \| Undef,
	ImplicitDefine = Implicit \| Define,	ImplicitDefine = Implicit \| Define,
	ImplicitKill = Implicit \| Kill	ImplicitKill = Implicit \| Kill
	};	};
	}	}

	class MachineInstrBuilder {	class MachineInstrBuilder {
	MachineInstr *MI;	MachineInstr *MI;
	public:	public:
	MachineInstrBuilder() : MI(0) {}	MachineInstrBuilder() : MI(0) {}
	explicit MachineInstrBuilder(MachineInstr *mi) : MI(mi) {}	explicit MachineInstrBuilder(MachineInstr *mi) : MI(mi) {}

	skipping to change at line 127	skipping to change at line 128
	MI->addOperand(MachineOperand::CreateGA(GV, Offset, TargetFlags));	MI->addOperand(MachineOperand::CreateGA(GV, Offset, TargetFlags));
	return *this;	return *this;
	}	}

	const MachineInstrBuilder &addExternalSymbol(const char *FnName,	const MachineInstrBuilder &addExternalSymbol(const char *FnName,
	unsigned char TargetFlags = 0) co nst {	unsigned char TargetFlags = 0) co nst {
	MI->addOperand(MachineOperand::CreateES(FnName, TargetFlags));	MI->addOperand(MachineOperand::CreateES(FnName, TargetFlags));
	return *this;	return *this;
	}	}


		const MachineInstrBuilder &addRegMask(const uint32_t *Mask) const {
		MI->addOperand(MachineOperand::CreateRegMask(Mask));
		return *this;
		}

	const MachineInstrBuilder &addMemOperand(MachineMemOperand *MMO) const {	const MachineInstrBuilder &addMemOperand(MachineMemOperand *MMO) const {
	MI->addMemOperand(*MI->getParent()->getParent(), MMO);	MI->addMemOperand(*MI->getParent()->getParent(), MMO);
	return *this;	return *this;
	}	}

	const MachineInstrBuilder &setMemRefs(MachineInstr::mmo_iterator b,	const MachineInstrBuilder &setMemRefs(MachineInstr::mmo_iterator b,
	MachineInstr::mmo_iterator e) const {	MachineInstr::mmo_iterator e) const {
	MI->setMemRefs(b, e);	MI->setMemRefs(b, e);
	return *this;	return *this;
	}	}

	skipping to change at line 211	skipping to change at line 217
	inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,	inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
	MachineBasicBlock::iterator I,	MachineBasicBlock::iterator I,
	DebugLoc DL,	DebugLoc DL,
	const MCInstrDesc &MCID,	const MCInstrDesc &MCID,
	unsigned DestReg) {	unsigned DestReg) {
	MachineInstr *MI = BB.getParent()->CreateMachineInstr(MCID, DL);	MachineInstr *MI = BB.getParent()->CreateMachineInstr(MCID, DL);
	BB.insert(I, MI);	BB.insert(I, MI);
	return MachineInstrBuilder(MI).addReg(DestReg, RegState::Define);	return MachineInstrBuilder(MI).addReg(DestReg, RegState::Define);
	}	}


		inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
		MachineBasicBlock::instr_iterator I,
		DebugLoc DL,
		const MCInstrDesc &MCID,
		unsigned DestReg) {
		MachineInstr *MI = BB.getParent()->CreateMachineInstr(MCID, DL);
		BB.insert(I, MI);
		return MachineInstrBuilder(MI).addReg(DestReg, RegState::Define);
		}

		inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
		MachineInstr *I,
		DebugLoc DL,
		const MCInstrDesc &MCID,
		unsigned DestReg) {
		if (I->isInsideBundle()) {
		MachineBasicBlock::instr_iterator MII = I;
		return BuildMI(BB, MII, DL, MCID, DestReg);
		}

		MachineBasicBlock::iterator MII = I;
		return BuildMI(BB, MII, DL, MCID, DestReg);
		}

	/// BuildMI - This version of the builder inserts the newly-built	/// BuildMI - This version of the builder inserts the newly-built
	/// instruction before the given position in the given MachineBasicBlock, a nd	/// instruction before the given position in the given MachineBasicBlock, a nd
	/// does NOT take a destination register.	/// does NOT take a destination register.
	///	///
	inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,	inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
	MachineBasicBlock::iterator I,	MachineBasicBlock::iterator I,
	DebugLoc DL,	DebugLoc DL,
	const MCInstrDesc &MCID) {	const MCInstrDesc &MCID) {
	MachineInstr *MI = BB.getParent()->CreateMachineInstr(MCID, DL);	MachineInstr *MI = BB.getParent()->CreateMachineInstr(MCID, DL);
	BB.insert(I, MI);	BB.insert(I, MI);
	return MachineInstrBuilder(MI);	return MachineInstrBuilder(MI);
	}	}


		inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
		MachineBasicBlock::instr_iterator I,
		DebugLoc DL,
		const MCInstrDesc &MCID) {
		MachineInstr *MI = BB.getParent()->CreateMachineInstr(MCID, DL);
		BB.insert(I, MI);
		return MachineInstrBuilder(MI);
		}

		inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
		MachineInstr *I,
		DebugLoc DL,
		const MCInstrDesc &MCID) {
		if (I->isInsideBundle()) {
		MachineBasicBlock::instr_iterator MII = I;
		return BuildMI(BB, MII, DL, MCID);
		}

		MachineBasicBlock::iterator MII = I;
		return BuildMI(BB, MII, DL, MCID);
		}

	/// BuildMI - This version of the builder inserts the newly-built	/// BuildMI - This version of the builder inserts the newly-built
	/// instruction at the end of the given MachineBasicBlock, and does NOT tak e a	/// instruction at the end of the given MachineBasicBlock, and does NOT tak e a
	/// destination register.	/// destination register.
	///	///
	inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB,	inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB,
	DebugLoc DL,	DebugLoc DL,
	const MCInstrDesc &MCID) {	const MCInstrDesc &MCID) {
	return BuildMI(*BB, BB->end(), DL, MCID);	return BuildMI(*BB, BB->end(), DL, MCID);
	}	}


End of changes. 4 change blocks.
	0 lines changed or deleted	52 lines changed or added

	MachineJumpTableInfo.h	MachineJumpTableInfo.h

	skipping to change at line 51	skipping to change at line 51

	class MachineJumpTableInfo {	class MachineJumpTableInfo {
	public:	public:
	/// JTEntryKind - This enum indicates how each entry of the jump table is	/// JTEntryKind - This enum indicates how each entry of the jump table is
	/// represented and emitted.	/// represented and emitted.
	enum JTEntryKind {	enum JTEntryKind {
	/// EK_BlockAddress - Each entry is a plain address of block, e.g.:	/// EK_BlockAddress - Each entry is a plain address of block, e.g.:
	/// .word LBB123	/// .word LBB123
	EK_BlockAddress,	EK_BlockAddress,


		/// EK_GPRel64BlockAddress - Each entry is an address of block, encoded
		/// with a relocation as gp-relative, e.g.:
		/// .gpdword LBB123
		EK_GPRel64BlockAddress,

	/// EK_GPRel32BlockAddress - Each entry is an address of block, encoded	/// EK_GPRel32BlockAddress - Each entry is an address of block, encoded
	/// with a relocation as gp-relative, e.g.:	/// with a relocation as gp-relative, e.g.:
	/// .gprel32 LBB123	/// .gprel32 LBB123
	EK_GPRel32BlockAddress,	EK_GPRel32BlockAddress,

	/// EK_LabelDifference32 - Each entry is the address of the block minus	/// EK_LabelDifference32 - Each entry is the address of the block minus
	/// the address of the jump table. This is used for PIC jump tables wh ere	/// the address of the jump table. This is used for PIC jump tables wh ere
	/// gprel32 is not supported. e.g.:	/// gprel32 is not supported. e.g.:
	/// .word LBB123 - LJTI1_2	/// .word LBB123 - LJTI1_2
	/// If the .set directive is supported, this is emitted as:	/// If the .set directive is supported, this is emitted as:

End of changes. 1 change blocks.
	0 lines changed or deleted	5 lines changed or added

	MachineMemOperand.h	MachineMemOperand.h

	skipping to change at line 25	skipping to change at line 25

	#ifndef LLVM_CODEGEN_MACHINEMEMOPERAND_H	#ifndef LLVM_CODEGEN_MACHINEMEMOPERAND_H
	#define LLVM_CODEGEN_MACHINEMEMOPERAND_H	#define LLVM_CODEGEN_MACHINEMEMOPERAND_H

	#include "llvm/Support/DataTypes.h"	#include "llvm/Support/DataTypes.h"

	namespace llvm {	namespace llvm {

	class Value;	class Value;
	class FoldingSetNodeID;	class FoldingSetNodeID;

		class MDNode;
	class raw_ostream;	class raw_ostream;

	/// MachinePointerInfo - This class contains a discriminated union of	/// MachinePointerInfo - This class contains a discriminated union of
	/// information about pointers in memory operands, relating them back to LL VM IR	/// information about pointers in memory operands, relating them back to LL VM IR
	/// or to virtual locations (such as frame indices) that are exposed during	/// or to virtual locations (such as frame indices) that are exposed during
	/// codegen.	/// codegen.
	struct MachinePointerInfo {	struct MachinePointerInfo {
	/// V - This is the IR pointer value for the access, or it is null if unk nown.	/// V - This is the IR pointer value for the access, or it is null if unk nown.
	/// If this is null, then the access is to a pointer in the default addre ss	/// If this is null, then the access is to a pointer in the default addre ss
	/// space.	/// space.

	skipping to change at line 85	skipping to change at line 86
	/// Value of the reference along with a byte size and offset. This allows i t	/// Value of the reference along with a byte size and offset. This allows i t
	/// to describe lowered loads and stores. Also, the special PseudoSourceVal ue	/// to describe lowered loads and stores. Also, the special PseudoSourceVal ue
	/// objects can be used to represent loads and stores to memory locations	/// objects can be used to represent loads and stores to memory locations
	/// that aren't explicit in the regular LLVM IR.	/// that aren't explicit in the regular LLVM IR.
	///	///
	class MachineMemOperand {	class MachineMemOperand {
	MachinePointerInfo PtrInfo;	MachinePointerInfo PtrInfo;
	uint64_t Size;	uint64_t Size;
	unsigned Flags;	unsigned Flags;
	const MDNode *TBAAInfo;	const MDNode *TBAAInfo;

		const MDNode *Ranges;

	public:	public:
	/// Flags values. These may be or'd together.	/// Flags values. These may be or'd together.
	enum MemOperandFlags {	enum MemOperandFlags {
	/// The memory access reads data.	/// The memory access reads data.
	MOLoad = 1,	MOLoad = 1,
	/// The memory access writes data.	/// The memory access writes data.
	MOStore = 2,	MOStore = 2,
	/// The memory access is volatile.	/// The memory access is volatile.
	MOVolatile = 4,	MOVolatile = 4,
	/// The memory access is non-temporal.	/// The memory access is non-temporal.
	MONonTemporal = 8,	MONonTemporal = 8,

		/// The memory access is invariant.
		MOInvariant = 16,
	// This is the number of bits we need to represent flags.	// This is the number of bits we need to represent flags.

	MOMaxBits = 4	MOMaxBits = 5
	};	};

	/// MachineMemOperand - Construct an MachineMemOperand object with the	/// MachineMemOperand - Construct an MachineMemOperand object with the
	/// specified PtrInfo, flags, size, and base alignment.	/// specified PtrInfo, flags, size, and base alignment.
	MachineMemOperand(MachinePointerInfo PtrInfo, unsigned flags, uint64_t s,	MachineMemOperand(MachinePointerInfo PtrInfo, unsigned flags, uint64_t s,

	unsigned base_alignment, const MDNode *TBAAInfo = 0);	unsigned base_alignment, const MDNode *TBAAInfo = 0,
		const MDNode *Ranges = 0);

	const MachinePointerInfo &getPointerInfo() const { return PtrInfo; }	const MachinePointerInfo &getPointerInfo() const { return PtrInfo; }

	/// getValue - Return the base address of the memory access. This may eit her	/// getValue - Return the base address of the memory access. This may eit her
	/// be a normal LLVM IR Value, or one of the special values used in CodeG en.	/// be a normal LLVM IR Value, or one of the special values used in CodeG en.
	/// Special values are those obtained via	/// Special values are those obtained via
	/// PseudoSourceValue::getFixedStack(int), PseudoSourceValue::getStack, a nd	/// PseudoSourceValue::getFixedStack(int), PseudoSourceValue::getStack, a nd
	/// other PseudoSourceValue member functions which return objects which s tand	/// other PseudoSourceValue member functions which return objects which s tand
	/// for frame/stack pointer relative references and other special referen ces	/// for frame/stack pointer relative references and other special referen ces
	/// which are not representable in the high-level IR.	/// which are not representable in the high-level IR.

	skipping to change at line 139	skipping to change at line 144
	/// actual memory reference.	/// actual memory reference.
	uint64_t getAlignment() const;	uint64_t getAlignment() const;

	/// getBaseAlignment - Return the minimum known alignment in bytes of the	/// getBaseAlignment - Return the minimum known alignment in bytes of the
	/// base address, without the offset.	/// base address, without the offset.
	uint64_t getBaseAlignment() const { return (1u << (Flags >> MOMaxBits)) > > 1; }	uint64_t getBaseAlignment() const { return (1u << (Flags >> MOMaxBits)) > > 1; }

	/// getTBAAInfo - Return the TBAA tag for the memory reference.	/// getTBAAInfo - Return the TBAA tag for the memory reference.
	const MDNode *getTBAAInfo() const { return TBAAInfo; }	const MDNode *getTBAAInfo() const { return TBAAInfo; }


		/// getRanges - Return the range tag for the memory reference.
		const MDNode *getRanges() const { return Ranges; }

	bool isLoad() const { return Flags & MOLoad; }	bool isLoad() const { return Flags & MOLoad; }
	bool isStore() const { return Flags & MOStore; }	bool isStore() const { return Flags & MOStore; }
	bool isVolatile() const { return Flags & MOVolatile; }	bool isVolatile() const { return Flags & MOVolatile; }
	bool isNonTemporal() const { return Flags & MONonTemporal; }	bool isNonTemporal() const { return Flags & MONonTemporal; }

		bool isInvariant() const { return Flags & MOInvariant; }

	/// refineAlignment - Update this MachineMemOperand to reflect the alignm ent	/// refineAlignment - Update this MachineMemOperand to reflect the alignm ent
	/// of MMO, if it has a greater alignment. This must only be used when th e	/// of MMO, if it has a greater alignment. This must only be used when th e
	/// new alignment applies to all users of this MachineMemOperand.	/// new alignment applies to all users of this MachineMemOperand.
	void refineAlignment(const MachineMemOperand *MMO);	void refineAlignment(const MachineMemOperand *MMO);

	/// setValue - Change the SourceValue for this MachineMemOperand. This	/// setValue - Change the SourceValue for this MachineMemOperand. This
	/// should only be used when an object is being relocated and all referen ces	/// should only be used when an object is being relocated and all referen ces
	/// to it are being updated.	/// to it are being updated.
	void setValue(const Value *NewSV) { PtrInfo.V = NewSV; }	void setValue(const Value *NewSV) { PtrInfo.V = NewSV; }

End of changes. 7 change blocks.
	2 lines changed or deleted	11 lines changed or added

	MachineModuleInfo.h	MachineModuleInfo.h

	skipping to change at line 164	skipping to change at line 164
	/// the specified basic block's address of label.	/// the specified basic block's address of label.
	MMIAddrLabelMap *AddrLabelSymbols;	MMIAddrLabelMap *AddrLabelSymbols;

	bool CallsEHReturn;	bool CallsEHReturn;
	bool CallsUnwindInit;	bool CallsUnwindInit;

	/// DbgInfoAvailable - True if debugging information is available	/// DbgInfoAvailable - True if debugging information is available
	/// in this module.	/// in this module.
	bool DbgInfoAvailable;	bool DbgInfoAvailable;


	/// CallsExternalVAFunctionWithFloatingPointArguments - True if this modu	/// UsesVAFloatArgument - True if this module calls VarArg function with
	le	/// floating-point arguments. This is used to emit an undefined referenc
	/// calls VarArg function with floating point arguments. This is used to	e
	emit	/// to _fltused on Windows targets.
	/// an undefined reference to fltused on Windows targets.	bool UsesVAFloatArgument;
	bool CallsExternalVAFunctionWithFloatingPointArguments;

	public:	public:
	static char ID; // Pass identification, replacement for typeid	static char ID; // Pass identification, replacement for typeid

	typedef std::pair<unsigned, DebugLoc> UnsignedDebugLocPair;	typedef std::pair<unsigned, DebugLoc> UnsignedDebugLocPair;
	typedef SmallVector<std::pair<TrackingVH<MDNode>, UnsignedDebugLocPair>, 4>	typedef SmallVector<std::pair<TrackingVH<MDNode>, UnsignedDebugLocPair>, 4>
	VariableDbgInfoMapTy;	VariableDbgInfoMapTy;
	VariableDbgInfoMapTy VariableDbgInfo;	VariableDbgInfoMapTy VariableDbgInfo;

	MachineModuleInfo(); // DUMMY CONSTRUCTOR, DO NOT CALL.	MachineModuleInfo(); // DUMMY CONSTRUCTOR, DO NOT CALL.

	skipping to change at line 226	skipping to change at line 226
	///	///
	bool hasDebugInfo() const { return DbgInfoAvailable; }	bool hasDebugInfo() const { return DbgInfoAvailable; }
	void setDebugInfoAvailability(bool avail) { DbgInfoAvailable = avail; }	void setDebugInfoAvailability(bool avail) { DbgInfoAvailable = avail; }

	bool callsEHReturn() const { return CallsEHReturn; }	bool callsEHReturn() const { return CallsEHReturn; }
	void setCallsEHReturn(bool b) { CallsEHReturn = b; }	void setCallsEHReturn(bool b) { CallsEHReturn = b; }

	bool callsUnwindInit() const { return CallsUnwindInit; }	bool callsUnwindInit() const { return CallsUnwindInit; }
	void setCallsUnwindInit(bool b) { CallsUnwindInit = b; }	void setCallsUnwindInit(bool b) { CallsUnwindInit = b; }


	bool callsExternalVAFunctionWithFloatingPointArguments() const {	bool usesVAFloatArgument() const {
	return CallsExternalVAFunctionWithFloatingPointArguments;	return UsesVAFloatArgument;
	}	}


	void setCallsExternalVAFunctionWithFloatingPointArguments(bool b) {	void setUsesVAFloatArgument(bool b) {
	CallsExternalVAFunctionWithFloatingPointArguments = b;	UsesVAFloatArgument = b;
	}	}

	/// getFrameMoves - Returns a reference to a list of moves done in the cu rrent	/// getFrameMoves - Returns a reference to a list of moves done in the cu rrent
	/// function's prologue. Used to construct frame maps for debug and exce ption	/// function's prologue. Used to construct frame maps for debug and exce ption
	/// handling comsumers.	/// handling comsumers.
	std::vector<MachineMove> &getFrameMoves() { return FrameMoves; }	std::vector<MachineMove> &getFrameMoves() { return FrameMoves; }

	/// getCompactUnwindEncoding - Returns the compact unwind encoding for a	/// getCompactUnwindEncoding - Returns the compact unwind encoding for a
	/// function if the target supports the encoding. This encoding replaces a	/// function if the target supports the encoding. This encoding replaces a
	/// function's CIE and FDE.	/// function's CIE and FDE.

End of changes. 3 change blocks.
	10 lines changed or deleted	9 lines changed or added

	MachineOperand.h	MachineOperand.h

	skipping to change at line 51	skipping to change at line 51
	MO_Immediate, ///< Immediate operand	MO_Immediate, ///< Immediate operand
	MO_CImmediate, ///< Immediate >64bit operand	MO_CImmediate, ///< Immediate >64bit operand
	MO_FPImmediate, ///< Floating-point immediate operand	MO_FPImmediate, ///< Floating-point immediate operand
	MO_MachineBasicBlock, ///< MachineBasicBlock reference	MO_MachineBasicBlock, ///< MachineBasicBlock reference
	MO_FrameIndex, ///< Abstract Stack Frame Index	MO_FrameIndex, ///< Abstract Stack Frame Index
	MO_ConstantPoolIndex, ///< Address of indexed Constant in Constant Pool	MO_ConstantPoolIndex, ///< Address of indexed Constant in Constant Pool
	MO_JumpTableIndex, ///< Address of indexed Jump Table for switc h	MO_JumpTableIndex, ///< Address of indexed Jump Table for switc h
	MO_ExternalSymbol, ///< Name of external global symbol	MO_ExternalSymbol, ///< Name of external global symbol
	MO_GlobalAddress, ///< Address of a global value	MO_GlobalAddress, ///< Address of a global value
	MO_BlockAddress, ///< Address of a basic block	MO_BlockAddress, ///< Address of a basic block

		MO_RegisterMask, ///< Mask of preserved registers.
	MO_Metadata, ///< Metadata reference (for debug info)	MO_Metadata, ///< Metadata reference (for debug info)
	MO_MCSymbol ///< MCSymbol reference (for debug/eh info)	MO_MCSymbol ///< MCSymbol reference (for debug/eh info)
	};	};

	private:	private:
	/// OpKind - Specify what kind of operand this is. This discriminates th e	/// OpKind - Specify what kind of operand this is. This discriminates th e
	/// union.	/// union.
	unsigned char OpKind; // MachineOperandType	unsigned char OpKind; // MachineOperandType

	/// SubReg - Subregister number, only valid for MO_Register. A value of 0	/// SubReg - Subregister number, only valid for MO_Register. A value of 0

	skipping to change at line 105	skipping to change at line 106
	/// the same register. In that case, the instruction may depend on those	/// the same register. In that case, the instruction may depend on those
	/// operands reading the same dont-care value. For example:	/// operands reading the same dont-care value. For example:
	///	///
	/// %vreg1<def> = XOR %vreg2<undef>, %vreg2<undef>	/// %vreg1<def> = XOR %vreg2<undef>, %vreg2<undef>
	///	///
	/// Any register can be used for %vreg2, and its value doesn't matter, bu t	/// Any register can be used for %vreg2, and its value doesn't matter, bu t
	/// the two operands must be the same register.	/// the two operands must be the same register.
	///	///
	bool IsUndef : 1;	bool IsUndef : 1;


		/// IsInternalRead - True if this operand reads a value that was defined
		/// inside the same instruction or bundle. This flag can be set on both
		use
		/// and def operands. On a sub-register def operand, it refers to the pa
		rt
		/// of the register that isn't written. On a full-register def operand,
		it
		/// is a noop.
		///
		/// When this flag is set, the instruction bundle must contain at least o
		ne
		/// other def of the register. If multiple instructions in the bundle de
		fine
		/// the register, the meaning is target-defined.
		bool IsInternalRead : 1;

	/// IsEarlyClobber - True if this MO_Register 'def' operand is written to	/// IsEarlyClobber - True if this MO_Register 'def' operand is written to
	/// by the MachineInstr before all input registers are read. This is use d to	/// by the MachineInstr before all input registers are read. This is use d to
	/// model the GCC inline asm '&' constraint modifier.	/// model the GCC inline asm '&' constraint modifier.
	bool IsEarlyClobber : 1;	bool IsEarlyClobber : 1;

	/// IsDebug - True if this MO_Register 'use' operand is in a debug pseudo ,	/// IsDebug - True if this MO_Register 'use' operand is in a debug pseudo ,
	/// not a real instruction. Such uses should be ignored during codegen.	/// not a real instruction. Such uses should be ignored during codegen.
	bool IsDebug : 1;	bool IsDebug : 1;

	/// SmallContents - This really should be part of the Contents union, but	/// SmallContents - This really should be part of the Contents union, but

	skipping to change at line 133	skipping to change at line 145
	/// ParentMI - This is the instruction that this operand is embedded into .	/// ParentMI - This is the instruction that this operand is embedded into .
	/// This is valid for all operand types, when the operand is in an instr.	/// This is valid for all operand types, when the operand is in an instr.
	MachineInstr *ParentMI;	MachineInstr *ParentMI;

	/// Contents union - This contains the payload for the various operand ty pes.	/// Contents union - This contains the payload for the various operand ty pes.
	union {	union {
	MachineBasicBlock *MBB; // For MO_MachineBasicBlock.	MachineBasicBlock *MBB; // For MO_MachineBasicBlock.
	const ConstantFP *CFP; // For MO_FPImmediate.	const ConstantFP *CFP; // For MO_FPImmediate.
	const ConstantInt *CI; // For MO_CImmediate. Integers > 64bit.	const ConstantInt *CI; // For MO_CImmediate. Integers > 64bit.
	int64_t ImmVal; // For MO_Immediate.	int64_t ImmVal; // For MO_Immediate.

		const uint32_t *RegMask; // For MO_RegisterMask.
	const MDNode *MD; // For MO_Metadata.	const MDNode *MD; // For MO_Metadata.
	MCSymbol *Sym; // For MO_MCSymbol	MCSymbol *Sym; // For MO_MCSymbol

	struct { // For MO_Register.	struct { // For MO_Register.
	// Register number is in SmallContents.RegNo.	// Register number is in SmallContents.RegNo.
	MachineOperand **Prev; // Access list for register.	MachineOperand **Prev; // Access list for register.
	MachineOperand *Next;	MachineOperand *Next;
	} Reg;	} Reg;

	/// OffsetedInfo - This struct contains the offset and an object identi fier.	/// OffsetedInfo - This struct contains the offset and an object identi fier.

	skipping to change at line 211	skipping to change at line 224
	/// isCPI - Tests if this is a MO_ConstantPoolIndex operand.	/// isCPI - Tests if this is a MO_ConstantPoolIndex operand.
	bool isCPI() const { return OpKind == MO_ConstantPoolIndex; }	bool isCPI() const { return OpKind == MO_ConstantPoolIndex; }
	/// isJTI - Tests if this is a MO_JumpTableIndex operand.	/// isJTI - Tests if this is a MO_JumpTableIndex operand.
	bool isJTI() const { return OpKind == MO_JumpTableIndex; }	bool isJTI() const { return OpKind == MO_JumpTableIndex; }
	/// isGlobal - Tests if this is a MO_GlobalAddress operand.	/// isGlobal - Tests if this is a MO_GlobalAddress operand.
	bool isGlobal() const { return OpKind == MO_GlobalAddress; }	bool isGlobal() const { return OpKind == MO_GlobalAddress; }
	/// isSymbol - Tests if this is a MO_ExternalSymbol operand.	/// isSymbol - Tests if this is a MO_ExternalSymbol operand.
	bool isSymbol() const { return OpKind == MO_ExternalSymbol; }	bool isSymbol() const { return OpKind == MO_ExternalSymbol; }
	/// isBlockAddress - Tests if this is a MO_BlockAddress operand.	/// isBlockAddress - Tests if this is a MO_BlockAddress operand.
	bool isBlockAddress() const { return OpKind == MO_BlockAddress; }	bool isBlockAddress() const { return OpKind == MO_BlockAddress; }

		/// isRegMask - Tests if this is a MO_RegisterMask operand.
		bool isRegMask() const { return OpKind == MO_RegisterMask; }
	/// isMetadata - Tests if this is a MO_Metadata operand.	/// isMetadata - Tests if this is a MO_Metadata operand.
	bool isMetadata() const { return OpKind == MO_Metadata; }	bool isMetadata() const { return OpKind == MO_Metadata; }
	bool isMCSymbol() const { return OpKind == MO_MCSymbol; }	bool isMCSymbol() const { return OpKind == MO_MCSymbol; }

	//===-------------------------------------------------------------------- ===//	//===-------------------------------------------------------------------- ===//
	// Accessors for Register Operands	// Accessors for Register Operands
	//===-------------------------------------------------------------------- ===//	//===-------------------------------------------------------------------- ===//

	/// getReg - Returns the register number.	/// getReg - Returns the register number.
	unsigned getReg() const {	unsigned getReg() const {

	skipping to change at line 260	skipping to change at line 275
	bool isKill() const {	bool isKill() const {
	assert(isReg() && "Wrong MachineOperand accessor");	assert(isReg() && "Wrong MachineOperand accessor");
	return IsKill;	return IsKill;
	}	}

	bool isUndef() const {	bool isUndef() const {
	assert(isReg() && "Wrong MachineOperand accessor");	assert(isReg() && "Wrong MachineOperand accessor");
	return IsUndef;	return IsUndef;
	}	}


		bool isInternalRead() const {
		assert(isReg() && "Wrong MachineOperand accessor");
		return IsInternalRead;
		}

	bool isEarlyClobber() const {	bool isEarlyClobber() const {
	assert(isReg() && "Wrong MachineOperand accessor");	assert(isReg() && "Wrong MachineOperand accessor");
	return IsEarlyClobber;	return IsEarlyClobber;
	}	}

	bool isDebug() const {	bool isDebug() const {
	assert(isReg() && "Wrong MachineOperand accessor");	assert(isReg() && "Wrong MachineOperand accessor");
	return IsDebug;	return IsDebug;
	}	}

	/// readsReg - Returns true if this operand reads the previous value of i ts	/// readsReg - Returns true if this operand reads the previous value of i ts
	/// register. A use operand with the <undef> flag set doesn't read its	/// register. A use operand with the <undef> flag set doesn't read its
	/// register. A sub-register def implicitly reads the other parts of the	/// register. A sub-register def implicitly reads the other parts of the
	/// register being redefined unless the <undef> flag is set.	/// register being redefined unless the <undef> flag is set.

		///
		/// This refers to reading the register value from before the current
		/// instruction or bundle. Internal bundle reads are not included.
	bool readsReg() const {	bool readsReg() const {
	assert(isReg() && "Wrong MachineOperand accessor");	assert(isReg() && "Wrong MachineOperand accessor");

	return !isUndef() && (isUse() \|\| getSubReg());	return !isUndef() && !isInternalRead() && (isUse() \|\| getSubReg());
	}	}

	/// getNextOperandForReg - Return the next MachineOperand in the function that	/// getNextOperandForReg - Return the next MachineOperand in the function that
	/// uses or defines this register.	/// uses or defines this register.
	MachineOperand *getNextOperandForReg() const {	MachineOperand *getNextOperandForReg() const {
	assert(isReg() && "This is not a register operand!");	assert(isReg() && "This is not a register operand!");
	return Contents.Reg.Next;	return Contents.Reg.Next;
	}	}

	//===-------------------------------------------------------------------- ===//	//===-------------------------------------------------------------------- ===//

	skipping to change at line 345	skipping to change at line 368
	void setIsDead(bool Val = true) {	void setIsDead(bool Val = true) {
	assert(isReg() && IsDef && "Wrong MachineOperand accessor");	assert(isReg() && IsDef && "Wrong MachineOperand accessor");
	IsDead = Val;	IsDead = Val;
	}	}

	void setIsUndef(bool Val = true) {	void setIsUndef(bool Val = true) {
	assert(isReg() && "Wrong MachineOperand accessor");	assert(isReg() && "Wrong MachineOperand accessor");
	IsUndef = Val;	IsUndef = Val;
	}	}


		void setIsInternalRead(bool Val = true) {
		assert(isReg() && "Wrong MachineOperand accessor");
		IsInternalRead = Val;
		}

	void setIsEarlyClobber(bool Val = true) {	void setIsEarlyClobber(bool Val = true) {
	assert(isReg() && IsDef && "Wrong MachineOperand accessor");	assert(isReg() && IsDef && "Wrong MachineOperand accessor");
	IsEarlyClobber = Val;	IsEarlyClobber = Val;
	}	}

	void setIsDebug(bool Val = true) {	void setIsDebug(bool Val = true) {
	assert(isReg() && IsDef && "Wrong MachineOperand accessor");	assert(isReg() && IsDef && "Wrong MachineOperand accessor");
	IsDebug = Val;	IsDebug = Val;
	}	}


	skipping to change at line 414	skipping to change at line 442
	"Wrong MachineOperand accessor");	"Wrong MachineOperand accessor");
	return (int64_t(Contents.OffsetedInfo.OffsetHi) << 32) \|	return (int64_t(Contents.OffsetedInfo.OffsetHi) << 32) \|
	SmallContents.OffsetLo;	SmallContents.OffsetLo;
	}	}

	const char *getSymbolName() const {	const char *getSymbolName() const {
	assert(isSymbol() && "Wrong MachineOperand accessor");	assert(isSymbol() && "Wrong MachineOperand accessor");
	return Contents.OffsetedInfo.Val.SymbolName;	return Contents.OffsetedInfo.Val.SymbolName;
	}	}


		/// clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
		/// It is sometimes necessary to detach the register mask pointer from it
		s
		/// machine operand. This static method can be used for such detached bit
		/// mask pointers.
		static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg) {
		// See TargetRegisterInfo.h.
		assert(PhysReg < (1u << 30) && "Not a physical register");
		return !(RegMask[PhysReg / 32] & (1u << PhysReg % 32));
		}

		/// clobbersPhysReg - Returns true if this RegMask operand clobbers PhysR
		eg.
		bool clobbersPhysReg(unsigned PhysReg) const {
		return clobbersPhysReg(getRegMask(), PhysReg);
		}

		/// getRegMask - Returns a bit mask of registers preserved by this RegMas
		k
		/// operand.
		const uint32_t *getRegMask() const {
		assert(isRegMask() && "Wrong MachineOperand accessor");
		return Contents.RegMask;
		}

	const MDNode *getMetadata() const {	const MDNode *getMetadata() const {
	assert(isMetadata() && "Wrong MachineOperand accessor");	assert(isMetadata() && "Wrong MachineOperand accessor");
	return Contents.MD;	return Contents.MD;
	}	}

	//===-------------------------------------------------------------------- ===//	//===-------------------------------------------------------------------- ===//
	// Mutators for various operand types.	// Mutators for various operand types.
	//===-------------------------------------------------------------------- ===//	//===-------------------------------------------------------------------- ===//

	void setImm(int64_t immVal) {	void setImm(int64_t immVal) {

	skipping to change at line 500	skipping to change at line 550
	bool isUndef = false,	bool isUndef = false,
	bool isEarlyClobber = false,	bool isEarlyClobber = false,
	unsigned SubReg = 0,	unsigned SubReg = 0,
	bool isDebug = false) {	bool isDebug = false) {
	MachineOperand Op(MachineOperand::MO_Register);	MachineOperand Op(MachineOperand::MO_Register);
	Op.IsDef = isDef;	Op.IsDef = isDef;
	Op.IsImp = isImp;	Op.IsImp = isImp;
	Op.IsKill = isKill;	Op.IsKill = isKill;
	Op.IsDead = isDead;	Op.IsDead = isDead;
	Op.IsUndef = isUndef;	Op.IsUndef = isUndef;

		Op.IsInternalRead = false;
	Op.IsEarlyClobber = isEarlyClobber;	Op.IsEarlyClobber = isEarlyClobber;
	Op.IsDebug = isDebug;	Op.IsDebug = isDebug;
	Op.SmallContents.RegNo = Reg;	Op.SmallContents.RegNo = Reg;
	Op.Contents.Reg.Prev = 0;	Op.Contents.Reg.Prev = 0;
	Op.Contents.Reg.Next = 0;	Op.Contents.Reg.Next = 0;
	Op.SubReg = SubReg;	Op.SubReg = SubReg;
	return Op;	return Op;
	}	}
	static MachineOperand CreateMBB(MachineBasicBlock *MBB,	static MachineOperand CreateMBB(MachineBasicBlock *MBB,
	unsigned char TargetFlags = 0) {	unsigned char TargetFlags = 0) {

	skipping to change at line 559	skipping to change at line 610
	return Op;	return Op;
	}	}
	static MachineOperand CreateBA(const BlockAddress *BA,	static MachineOperand CreateBA(const BlockAddress *BA,
	unsigned char TargetFlags = 0) {	unsigned char TargetFlags = 0) {
	MachineOperand Op(MachineOperand::MO_BlockAddress);	MachineOperand Op(MachineOperand::MO_BlockAddress);
	Op.Contents.OffsetedInfo.Val.BA = BA;	Op.Contents.OffsetedInfo.Val.BA = BA;
	Op.setOffset(0); // Offset is always 0.	Op.setOffset(0); // Offset is always 0.
	Op.setTargetFlags(TargetFlags);	Op.setTargetFlags(TargetFlags);
	return Op;	return Op;
	}	}

		/// CreateRegMask - Creates a register mask operand referencing Mask. Th
		e
		/// operand does not take ownership of the memory referenced by Mask, it
		must
		/// remain valid for the lifetime of the operand.
		///
		/// A RegMask operand represents a set of non-clobbered physical register
		s on
		/// an instruction that clobbers many registers, typically a call. The b
		it
		/// mask has a bit set for each physreg that is preserved by this
		/// instruction, as described in the documentation for
		/// TargetRegisterInfo::getCallPreservedMask().
		///
		/// Any physreg with a 0 bit in the mask is clobbered by the instruction.
		///
		static MachineOperand CreateRegMask(const uint32_t *Mask) {
		assert(Mask && "Missing register mask");
		MachineOperand Op(MachineOperand::MO_RegisterMask);
		Op.Contents.RegMask = Mask;
		return Op;
		}
	static MachineOperand CreateMetadata(const MDNode *Meta) {	static MachineOperand CreateMetadata(const MDNode *Meta) {
	MachineOperand Op(MachineOperand::MO_Metadata);	MachineOperand Op(MachineOperand::MO_Metadata);
	Op.Contents.MD = Meta;	Op.Contents.MD = Meta;
	return Op;	return Op;
	}	}

	static MachineOperand CreateMCSymbol(MCSymbol *Sym) {	static MachineOperand CreateMCSymbol(MCSymbol *Sym) {
	MachineOperand Op(MachineOperand::MO_MCSymbol);	MachineOperand Op(MachineOperand::MO_MCSymbol);
	Op.Contents.Sym = Sym;	Op.Contents.Sym = Sym;
	return Op;	return Op;

End of changes. 11 change blocks.
	1 lines changed or deleted	82 lines changed or added

	MachineRegisterInfo.h	MachineRegisterInfo.h

	skipping to change at line 18	skipping to change at line 18
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	//	//
	// This file defines the MachineRegisterInfo class.	// This file defines the MachineRegisterInfo class.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H	#ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H
	#define LLVM_CODEGEN_MACHINEREGISTERINFO_H	#define LLVM_CODEGEN_MACHINEREGISTERINFO_H

	#include "llvm/Target/TargetRegisterInfo.h"	#include "llvm/Target/TargetRegisterInfo.h"

		#include "llvm/CodeGen/MachineInstrBundle.h"
	#include "llvm/ADT/BitVector.h"	#include "llvm/ADT/BitVector.h"
	#include "llvm/ADT/IndexedMap.h"	#include "llvm/ADT/IndexedMap.h"
	#include <vector>	#include <vector>

	namespace llvm {	namespace llvm {

	/// MachineRegisterInfo - Keep track of information for virtual and physica l	/// MachineRegisterInfo - Keep track of information for virtual and physica l
	/// registers, including vreg register classes, use/def chains for register s,	/// registers, including vreg register classes, use/def chains for register s,
	/// etc.	/// etc.
	class MachineRegisterInfo {	class MachineRegisterInfo {
	const TargetRegisterInfo *const TRI;	const TargetRegisterInfo *const TRI;

	/// IsSSA - True when the machine function is in SSA form and virtual	/// IsSSA - True when the machine function is in SSA form and virtual
	/// registers have a single def.	/// registers have a single def.
	bool IsSSA;	bool IsSSA;


		/// TracksLiveness - True while register liveness is being tracked accura
		tely.
		/// Basic block live-in lists, kill flags, and implicit defs may not be
		/// accurate when after this flag is cleared.
		bool TracksLiveness;

	/// VRegInfo - Information we keep for each virtual register.	/// VRegInfo - Information we keep for each virtual register.
	///	///
	/// Each element in this list contains the register class of the vreg and the	/// Each element in this list contains the register class of the vreg and the
	/// start of the use/def list for the register.	/// start of the use/def list for the register.
	IndexedMap<std::pair<const TargetRegisterClass, MachineOperand>,	IndexedMap<std::pair<const TargetRegisterClass, MachineOperand>,
	VirtReg2IndexFunctor> VRegInfo;	VirtReg2IndexFunctor> VRegInfo;

	/// RegAllocHints - This vector records register allocation hints for vir tual	/// RegAllocHints - This vector records register allocation hints for vir tual
	/// registers. For each virtual register, it keeps a register and hint ty pe	/// registers. For each virtual register, it keeps a register and hint ty pe
	/// pair making up the allocation hint. Hint type is target specific exce pt	/// pair making up the allocation hint. Hint type is target specific exce pt

	skipping to change at line 59	skipping to change at line 65

	/// PhysRegUseDefLists - This is an array of the head of the use/def list for	/// PhysRegUseDefLists - This is an array of the head of the use/def list for
	/// physical registers.	/// physical registers.
	MachineOperand **PhysRegUseDefLists;	MachineOperand **PhysRegUseDefLists;

	/// UsedPhysRegs - This is a bit vector that is computed and set by the	/// UsedPhysRegs - This is a bit vector that is computed and set by the
	/// register allocator, and must be kept up to date by passes that run af ter	/// register allocator, and must be kept up to date by passes that run af ter
	/// register allocation (though most don't modify this). This is used	/// register allocation (though most don't modify this). This is used
	/// so that the code generator knows which callee save registers to save and	/// so that the code generator knows which callee save registers to save and
	/// for other target specific uses.	/// for other target specific uses.

		/// This vector only has bits set for registers explicitly used, not thei
		r
		/// aliases.
	BitVector UsedPhysRegs;	BitVector UsedPhysRegs;


		/// UsedPhysRegMask - Additional used physregs, but including aliases.
		BitVector UsedPhysRegMask;

		/// ReservedRegs - This is a bit vector of reserved registers. The targe
		t
		/// may change its mind about which registers should be reserved. This
		/// vector is the frozen set of reserved registers when register allocati
		on
		/// started.
		BitVector ReservedRegs;

		/// AllocatableRegs - From TRI->getAllocatableSet.
		mutable BitVector AllocatableRegs;

	/// LiveIns/LiveOuts - Keep track of the physical registers that are	/// LiveIns/LiveOuts - Keep track of the physical registers that are
	/// livein/liveout of the function. Live in values are typically argumen ts in	/// livein/liveout of the function. Live in values are typically argumen ts in
	/// registers, live out values are typically return values in registers.	/// registers, live out values are typically return values in registers.
	/// LiveIn values are allowed to have virtual registers associated with t hem,	/// LiveIn values are allowed to have virtual registers associated with t hem,
	/// stored in the second element.	/// stored in the second element.
	std::vector<std::pair<unsigned, unsigned> > LiveIns;	std::vector<std::pair<unsigned, unsigned> > LiveIns;
	std::vector<unsigned> LiveOuts;	std::vector<unsigned> LiveOuts;

	MachineRegisterInfo(const MachineRegisterInfo&); // DO NOT IMPLEMENT	MachineRegisterInfo(const MachineRegisterInfo&); // DO NOT IMPLEMENT
	void operator=(const MachineRegisterInfo&); // DO NOT IMPLEMENT	void operator=(const MachineRegisterInfo&); // DO NOT IMPLEMENT

	skipping to change at line 91	skipping to change at line 111
	// register has a single defining instruction.	// register has a single defining instruction.
	//	//
	// The TwoAddressInstructionPass and PHIElimination passes take the machi ne	// The TwoAddressInstructionPass and PHIElimination passes take the machi ne
	// function out of SSA form when they introduce multiple defs per virtual	// function out of SSA form when they introduce multiple defs per virtual
	// register.	// register.
	bool isSSA() const { return IsSSA; }	bool isSSA() const { return IsSSA; }

	// leaveSSA - Indicates that the machine function is no longer in SSA for m.	// leaveSSA - Indicates that the machine function is no longer in SSA for m.
	void leaveSSA() { IsSSA = false; }	void leaveSSA() { IsSSA = false; }


		/// tracksLiveness - Returns true when tracking register liveness accurat
		ely.
		///
		/// While this flag is true, register liveness information in basic block
		/// live-in lists and machine instruction operands is accurate. This mean
		s it
		/// can be used to change the code in ways that affect the values in
		/// registers, for example by the register scavenger.
		///
		/// When this flag is false, liveness is no longer reliable.
		bool tracksLiveness() const { return TracksLiveness; }

		/// invalidateLiveness - Indicates that register liveness is no longer be
		ing
		/// tracked accurately.
		///
		/// This should be called by late passes that invalidate the liveness
		/// information.
		void invalidateLiveness() { TracksLiveness = false; }

	//===-------------------------------------------------------------------- ===//	//===-------------------------------------------------------------------- ===//
	// Register Info	// Register Info
	//===-------------------------------------------------------------------- ===//	//===-------------------------------------------------------------------- ===//

	/// reg_begin/reg_end - Provide iteration support to walk over all defini tions	/// reg_begin/reg_end - Provide iteration support to walk over all defini tions
	/// and uses of a register within the MachineFunction that corresponds to this	/// and uses of a register within the MachineFunction that corresponds to this
	/// MachineRegisterInfo object.	/// MachineRegisterInfo object.
	template<bool Uses, bool Defs, bool SkipDebug>	template<bool Uses, bool Defs, bool SkipDebug>
	class defusechain_iterator;	class defusechain_iterator;


	skipping to change at line 174	skipping to change at line 211
	return use_nodbg_begin(RegNo) == use_nodbg_end();	return use_nodbg_begin(RegNo) == use_nodbg_end();
	}	}

	/// hasOneNonDBGUse - Return true if there is exactly one non-Debug	/// hasOneNonDBGUse - Return true if there is exactly one non-Debug
	/// instruction using the specified register.	/// instruction using the specified register.
	bool hasOneNonDBGUse(unsigned RegNo) const;	bool hasOneNonDBGUse(unsigned RegNo) const;

	/// replaceRegWith - Replace all instances of FromReg with ToReg in the	/// replaceRegWith - Replace all instances of FromReg with ToReg in the
	/// machine function. This is like llvm-level X->replaceAllUsesWith(Y),	/// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
	/// except that it also changes any definitions of the register as well.	/// except that it also changes any definitions of the register as well.

		///
		/// Note that it is usually necessary to first constrain ToReg's register
		/// class to match the FromReg constraints using:
		///
		/// constrainRegClass(ToReg, getRegClass(FromReg))
		///
		/// That function will return NULL if the virtual registers have incompat
		ible
		/// constraints.
	void replaceRegWith(unsigned FromReg, unsigned ToReg);	void replaceRegWith(unsigned FromReg, unsigned ToReg);

	/// getRegUseDefListHead - Return the head pointer for the register use/d ef	/// getRegUseDefListHead - Return the head pointer for the register use/d ef
	/// list for the specified virtual or physical register.	/// list for the specified virtual or physical register.
	MachineOperand *&getRegUseDefListHead(unsigned RegNo) {	MachineOperand *&getRegUseDefListHead(unsigned RegNo) {
	if (TargetRegisterInfo::isVirtualRegister(RegNo))	if (TargetRegisterInfo::isVirtualRegister(RegNo))
	return VRegInfo[RegNo].second;	return VRegInfo[RegNo].second;
	return PhysRegUseDefLists[RegNo];	return PhysRegUseDefLists[RegNo];
	}	}


	skipping to change at line 205	skipping to change at line 250
	/// clearKillFlags - Iterate over all the uses of the given register and	/// clearKillFlags - Iterate over all the uses of the given register and
	/// clear the kill flag from the MachineOperand. This function is used by	/// clear the kill flag from the MachineOperand. This function is used by
	/// optimization passes which extend register lifetimes and need only	/// optimization passes which extend register lifetimes and need only
	/// preserve conservative kill flag information.	/// preserve conservative kill flag information.
	void clearKillFlags(unsigned Reg) const;	void clearKillFlags(unsigned Reg) const;

	#ifndef NDEBUG	#ifndef NDEBUG
	void dumpUses(unsigned RegNo) const;	void dumpUses(unsigned RegNo) const;
	#endif	#endif


		/// isConstantPhysReg - Returns true if PhysReg is unallocatable and cons
		tant
		/// throughout the function. It is safe to move instructions that read s
		uch
		/// a physreg.
		bool isConstantPhysReg(unsigned PhysReg, const MachineFunction &MF) const
		;

	//===-------------------------------------------------------------------- ===//	//===-------------------------------------------------------------------- ===//
	// Virtual Register Info	// Virtual Register Info
	//===-------------------------------------------------------------------- ===//	//===-------------------------------------------------------------------- ===//

	/// getRegClass - Return the register class of the specified virtual regi ster.	/// getRegClass - Return the register class of the specified virtual regi ster.
	///	///
	const TargetRegisterClass *getRegClass(unsigned Reg) const {	const TargetRegisterClass *getRegClass(unsigned Reg) const {
	return VRegInfo[Reg].first;	return VRegInfo[Reg].first;
	}	}


	skipping to change at line 249	skipping to change at line 299

	/// createVirtualRegister - Create and return a new virtual register in t he	/// createVirtualRegister - Create and return a new virtual register in t he
	/// function with the specified register class.	/// function with the specified register class.
	///	///
	unsigned createVirtualRegister(const TargetRegisterClass *RegClass);	unsigned createVirtualRegister(const TargetRegisterClass *RegClass);

	/// getNumVirtRegs - Return the number of virtual registers created.	/// getNumVirtRegs - Return the number of virtual registers created.
	///	///
	unsigned getNumVirtRegs() const { return VRegInfo.size(); }	unsigned getNumVirtRegs() const { return VRegInfo.size(); }


		/// clearVirtRegs - Remove all virtual registers (after physreg assignmen
		t).
		void clearVirtRegs();

	/// setRegAllocationHint - Specify a register allocation hint for the	/// setRegAllocationHint - Specify a register allocation hint for the
	/// specified virtual register.	/// specified virtual register.
	void setRegAllocationHint(unsigned Reg, unsigned Type, unsigned PrefReg) {	void setRegAllocationHint(unsigned Reg, unsigned Type, unsigned PrefReg) {
	RegAllocHints[Reg].first = Type;	RegAllocHints[Reg].first = Type;
	RegAllocHints[Reg].second = PrefReg;	RegAllocHints[Reg].second = PrefReg;
	}	}

	/// getRegAllocationHint - Return the register allocation hint for the	/// getRegAllocationHint - Return the register allocation hint for the
	/// specified virtual register.	/// specified virtual register.
	std::pair<unsigned, unsigned>	std::pair<unsigned, unsigned>

	skipping to change at line 276	skipping to change at line 329
	std::pair<unsigned, unsigned> Hint = getRegAllocationHint(Reg);	std::pair<unsigned, unsigned> Hint = getRegAllocationHint(Reg);
	return Hint.first ? 0 : Hint.second;	return Hint.first ? 0 : Hint.second;
	}	}

	//===-------------------------------------------------------------------- ===//	//===-------------------------------------------------------------------- ===//
	// Physical Register Use Info	// Physical Register Use Info
	//===-------------------------------------------------------------------- ===//	//===-------------------------------------------------------------------- ===//

	/// isPhysRegUsed - Return true if the specified register is used in this	/// isPhysRegUsed - Return true if the specified register is used in this
	/// function. This only works after register allocation.	/// function. This only works after register allocation.

	bool isPhysRegUsed(unsigned Reg) const { return UsedPhysRegs[Reg]; }	bool isPhysRegUsed(unsigned Reg) const {
		return UsedPhysRegs.test(Reg) \|\| UsedPhysRegMask.test(Reg);
		}

		/// isPhysRegOrOverlapUsed - Return true if Reg or any overlapping regist
		er
		/// is used in this function.
		bool isPhysRegOrOverlapUsed(unsigned Reg) const {
		if (UsedPhysRegMask.test(Reg))
		return true;
		for (const uint16_t AI = TRI->getOverlaps(Reg); AI; ++AI)
		if (UsedPhysRegs.test(*AI))
		return true;
		return false;
		}

	/// setPhysRegUsed - Mark the specified register used in this function.	/// setPhysRegUsed - Mark the specified register used in this function.
	/// This should only be called during and after register allocation.	/// This should only be called during and after register allocation.

	void setPhysRegUsed(unsigned Reg) { UsedPhysRegs[Reg] = true; }	void setPhysRegUsed(unsigned Reg) { UsedPhysRegs.set(Reg); }

	/// addPhysRegsUsed - Mark the specified registers used in this function.	/// addPhysRegsUsed - Mark the specified registers used in this function.
	/// This should only be called during and after register allocation.	/// This should only be called during and after register allocation.
	void addPhysRegsUsed(const BitVector &Regs) { UsedPhysRegs \|= Regs; }	void addPhysRegsUsed(const BitVector &Regs) { UsedPhysRegs \|= Regs; }


		/// addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as use
		d.
		/// This corresponds to the bit mask attached to register mask operands.
		void addPhysRegsUsedFromRegMask(const uint32_t *RegMask) {
		UsedPhysRegMask.setBitsNotInMask(RegMask);
		}

	/// setPhysRegUnused - Mark the specified register unused in this functio n.	/// setPhysRegUnused - Mark the specified register unused in this functio n.
	/// This should only be called during and after register allocation.	/// This should only be called during and after register allocation.

	void setPhysRegUnused(unsigned Reg) { UsedPhysRegs[Reg] = false; }	void setPhysRegUnused(unsigned Reg) {
		UsedPhysRegs.reset(Reg);
		UsedPhysRegMask.reset(Reg);
		}


	/// closePhysRegsUsed - Expand UsedPhysRegs to its transitive closure ove	//===--------------------------------------------------------------------
	r	===//
	/// subregisters. That means that if R is used, so are all subregisters.	// Reserved Register Info
	void closePhysRegsUsed(const TargetRegisterInfo&);	//===--------------------------------------------------------------------
		===//
		//
		// The set of reserved registers must be invariant during register
		// allocation. For example, the target cannot suddenly decide it needs a
		// frame pointer when the register allocator has already used the frame
		// pointer register for something else.
		//
		// These methods can be used by target hooks like hasFP() to avoid changi
		ng
		// the reserved register set during register allocation.

		/// freezeReservedRegs - Called by the register allocator to freeze the s
		et
		/// of reserved registers before allocation begins.
		void freezeReservedRegs(const MachineFunction&);

		/// reservedRegsFrozen - Returns true after freezeReservedRegs() was call
		ed
		/// to ensure the set of reserved registers stays constant.
		bool reservedRegsFrozen() const {
		return !ReservedRegs.empty();
		}

		/// canReserveReg - Returns true if PhysReg can be used as a reserved
		/// register. Any register can be reserved before freezeReservedRegs() i
		s
		/// called.
		bool canReserveReg(unsigned PhysReg) const {
		return !reservedRegsFrozen() \|\| ReservedRegs.test(PhysReg);
		}

	//===-------------------------------------------------------------------- ===//	//===-------------------------------------------------------------------- ===//
	// LiveIn/LiveOut Management	// LiveIn/LiveOut Management
	//===-------------------------------------------------------------------- ===//	//===-------------------------------------------------------------------- ===//

	/// addLiveIn/Out - Add the specified register as a live in/out. Note th at it	/// addLiveIn/Out - Add the specified register as a live in/out. Note th at it
	/// is an error to add the same register to the same set more than once.	/// is an error to add the same register to the same set more than once.
	void addLiveIn(unsigned Reg, unsigned vreg = 0) {	void addLiveIn(unsigned Reg, unsigned vreg = 0) {
	LiveIns.push_back(std::make_pair(Reg, vreg));	LiveIns.push_back(std::make_pair(Reg, vreg));
	}	}

	skipping to change at line 406	skipping to change at line 506
	/// Return the skipped instruction that is no longer pointed to, or NUL L if	/// Return the skipped instruction that is no longer pointed to, or NUL L if
	/// already pointing to end().	/// already pointing to end().
	MachineInstr *skipInstruction() {	MachineInstr *skipInstruction() {
	if (!Op) return 0;	if (!Op) return 0;
	MachineInstr *MI = Op->getParent();	MachineInstr *MI = Op->getParent();
	do ++*this;	do ++*this;
	while (Op && Op->getParent() == MI);	while (Op && Op->getParent() == MI);
	return MI;	return MI;
	}	}


		MachineInstr *skipBundle() {
		if (!Op) return 0;
		MachineInstr *MI = getBundleStart(Op->getParent());
		do ++*this;
		while (Op && getBundleStart(Op->getParent()) == MI);
		return MI;
		}

	MachineOperand &getOperand() const {	MachineOperand &getOperand() const {
	assert(Op && "Cannot dereference end iterator!");	assert(Op && "Cannot dereference end iterator!");
	return *Op;	return *Op;
	}	}

	/// getOperandNo - Return the operand # of this MachineOperand in its	/// getOperandNo - Return the operand # of this MachineOperand in its
	/// MachineInstr.	/// MachineInstr.
	unsigned getOperandNo() const {	unsigned getOperandNo() const {
	assert(Op && "Cannot dereference end iterator!");	assert(Op && "Cannot dereference end iterator!");
	return Op - &Op->getParent()->getOperand(0);	return Op - &Op->getParent()->getOperand(0);

End of changes. 14 change blocks.
	7 lines changed or deleted	134 lines changed or added

	ManagedStatic.h	ManagedStatic.h

	skipping to change at line 19	skipping to change at line 19
	//	//
	// This file defines the ManagedStatic class and the llvm_shutdown() functi on.	// This file defines the ManagedStatic class and the llvm_shutdown() functi on.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_SUPPORT_MANAGED_STATIC_H	#ifndef LLVM_SUPPORT_MANAGED_STATIC_H
	#define LLVM_SUPPORT_MANAGED_STATIC_H	#define LLVM_SUPPORT_MANAGED_STATIC_H

	#include "llvm/Support/Atomic.h"	#include "llvm/Support/Atomic.h"
	#include "llvm/Support/Threading.h"	#include "llvm/Support/Threading.h"

		#include "llvm/Support/Valgrind.h"

	namespace llvm {	namespace llvm {

	/// object_creator - Helper method for ManagedStatic.	/// object_creator - Helper method for ManagedStatic.
	template<class C>	template<class C>
	void* object_creator() {	void* object_creator() {
	return new C();	return new C();
	}	}

	/// object_deleter - Helper method for ManagedStatic.	/// object_deleter - Helper method for ManagedStatic.

	skipping to change at line 68	skipping to change at line 69
	///	///
	template<class C>	template<class C>
	class ManagedStatic : public ManagedStaticBase {	class ManagedStatic : public ManagedStaticBase {
	public:	public:

	// Accessors.	// Accessors.
	C &operator*() {	C &operator*() {
	void* tmp = Ptr;	void* tmp = Ptr;
	if (llvm_is_multithreaded()) sys::MemoryFence();	if (llvm_is_multithreaded()) sys::MemoryFence();
	if (!tmp) RegisterManagedStatic(object_creator<C>, object_deleter<C>::c all);	if (!tmp) RegisterManagedStatic(object_creator<C>, object_deleter<C>::c all);

		TsanHappensAfter(this);

	return static_cast<C>(Ptr);	return static_cast<C>(Ptr);
	}	}
	C *operator->() {	C *operator->() {
	void* tmp = Ptr;	void* tmp = Ptr;
	if (llvm_is_multithreaded()) sys::MemoryFence();	if (llvm_is_multithreaded()) sys::MemoryFence();
	if (!tmp) RegisterManagedStatic(object_creator<C>, object_deleter<C>::c all);	if (!tmp) RegisterManagedStatic(object_creator<C>, object_deleter<C>::c all);

		TsanHappensAfter(this);

	return static_cast<C*>(Ptr);	return static_cast<C*>(Ptr);
	}	}
	const C &operator*() const {	const C &operator*() const {
	void* tmp = Ptr;	void* tmp = Ptr;
	if (llvm_is_multithreaded()) sys::MemoryFence();	if (llvm_is_multithreaded()) sys::MemoryFence();
	if (!tmp) RegisterManagedStatic(object_creator<C>, object_deleter<C>::c all);	if (!tmp) RegisterManagedStatic(object_creator<C>, object_deleter<C>::c all);

		TsanHappensAfter(this);

	return static_cast<C>(Ptr);	return static_cast<C>(Ptr);
	}	}
	const C *operator->() const {	const C *operator->() const {
	void* tmp = Ptr;	void* tmp = Ptr;
	if (llvm_is_multithreaded()) sys::MemoryFence();	if (llvm_is_multithreaded()) sys::MemoryFence();
	if (!tmp) RegisterManagedStatic(object_creator<C>, object_deleter<C>::c all);	if (!tmp) RegisterManagedStatic(object_creator<C>, object_deleter<C>::c all);

		TsanHappensAfter(this);

	return static_cast<C*>(Ptr);	return static_cast<C*>(Ptr);
	}	}
	};	};

	/// llvm_shutdown - Deallocate and destroy all ManagedStatic variables.	/// llvm_shutdown - Deallocate and destroy all ManagedStatic variables.
	void llvm_shutdown();	void llvm_shutdown();

	/// llvm_shutdown_obj - This is a simple helper class that calls	/// llvm_shutdown_obj - This is a simple helper class that calls
	/// llvm_shutdown() when it is destroyed.	/// llvm_shutdown() when it is destroyed.

End of changes. 5 change blocks.
	0 lines changed or deleted	5 lines changed or added

	Mangler.h	Mangler.h

	skipping to change at line 20	skipping to change at line 20
	// Unified name mangler for various backends.	// Unified name mangler for various backends.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_SUPPORT_MANGLER_H	#ifndef LLVM_SUPPORT_MANGLER_H
	#define LLVM_SUPPORT_MANGLER_H	#define LLVM_SUPPORT_MANGLER_H

	#include "llvm/ADT/DenseMap.h"	#include "llvm/ADT/DenseMap.h"

	namespace llvm {	namespace llvm {

	class StringRef;
	class Twine;	class Twine;

	class Value;
	class GlobalValue;	class GlobalValue;
	template <typename T> class SmallVectorImpl;	template <typename T> class SmallVectorImpl;
	class MCContext;	class MCContext;
	class MCSymbol;	class MCSymbol;
	class TargetData;	class TargetData;

	class Mangler {	class Mangler {
	public:	public:
	enum ManglerPrefixTy {	enum ManglerPrefixTy {
	Default, ///< Emit default string before each symbol.	Default, ///< Emit default string before each symbol.

End of changes. 2 change blocks.
	2 lines changed or deleted	0 lines changed or added

	MathExtras.h	MathExtras.h

	skipping to change at line 54	skipping to change at line 54
	}	}
	template<>	template<>
	inline bool isInt<16>(int64_t x) {	inline bool isInt<16>(int64_t x) {
	return static_cast<int16_t>(x) == x;	return static_cast<int16_t>(x) == x;
	}	}
	template<>	template<>
	inline bool isInt<32>(int64_t x) {	inline bool isInt<32>(int64_t x) {
	return static_cast<int32_t>(x) == x;	return static_cast<int32_t>(x) == x;
	}	}


		/// isShiftedInt<N,S> - Checks if a signed integer is an N bit number shift
		ed
		/// left by S.
		template<unsigned N, unsigned S>
		inline bool isShiftedInt(int64_t x) {
		return isInt<N+S>(x) && (x % (1<<S) == 0);
		}

	/// isUInt - Checks if an unsigned integer fits into the given bit width.	/// isUInt - Checks if an unsigned integer fits into the given bit width.
	template<unsigned N>	template<unsigned N>
	inline bool isUInt(uint64_t x) {	inline bool isUInt(uint64_t x) {
	return N >= 64 \|\| x < (UINT64_C(1)<<N);	return N >= 64 \|\| x < (UINT64_C(1)<<N);
	}	}
	// Template specializations to get better code for common cases.	// Template specializations to get better code for common cases.
	template<>	template<>
	inline bool isUInt<8>(uint64_t x) {	inline bool isUInt<8>(uint64_t x) {
	return static_cast<uint8_t>(x) == x;	return static_cast<uint8_t>(x) == x;
	}	}
	template<>	template<>
	inline bool isUInt<16>(uint64_t x) {	inline bool isUInt<16>(uint64_t x) {
	return static_cast<uint16_t>(x) == x;	return static_cast<uint16_t>(x) == x;
	}	}
	template<>	template<>
	inline bool isUInt<32>(uint64_t x) {	inline bool isUInt<32>(uint64_t x) {
	return static_cast<uint32_t>(x) == x;	return static_cast<uint32_t>(x) == x;
	}	}


		/// isShiftedUInt<N,S> - Checks if a unsigned integer is an N bit number sh
		ifted
		/// left by S.
		template<unsigned N, unsigned S>
		inline bool isShiftedUInt(uint64_t x) {
		return isUInt<N+S>(x) && (x % (1<<S) == 0);
		}

	/// isUIntN - Checks if an unsigned integer fits into the given (dynamic)	/// isUIntN - Checks if an unsigned integer fits into the given (dynamic)
	/// bit width.	/// bit width.
	inline bool isUIntN(unsigned N, uint64_t x) {	inline bool isUIntN(unsigned N, uint64_t x) {
	return x == (x & (~0ULL >> (64 - N)));	return x == (x & (~0ULL >> (64 - N)));
	}	}

	/// isIntN - Checks if an signed integer fits into the given (dynamic)	/// isIntN - Checks if an signed integer fits into the given (dynamic)
	/// bit width.	/// bit width.
	inline bool isIntN(unsigned N, int64_t x) {	inline bool isIntN(unsigned N, int64_t x) {
	return N >= 64 \|\| (-(INT64_C(1)<<(N-1)) <= x && x < (INT64_C(1)<<(N-1)));	return N >= 64 \|\| (-(INT64_C(1)<<(N-1)) <= x && x < (INT64_C(1)<<(N-1)));

End of changes. 2 change blocks.
	0 lines changed or deleted	16 lines changed or added

	MemoryDependenceAnalysis.h	MemoryDependenceAnalysis.h

	skipping to change at line 326	skipping to change at line 326
	typedef DenseMap<Instruction*,	typedef DenseMap<Instruction*,
	SmallPtrSet<Instruction*, 4> > ReverseDepMapType;	SmallPtrSet<Instruction*, 4> > ReverseDepMapType;
	ReverseDepMapType ReverseLocalDeps;	ReverseDepMapType ReverseLocalDeps;

	// A reverse mapping from dependencies to the non-local dependees.	// A reverse mapping from dependencies to the non-local dependees.
	ReverseDepMapType ReverseNonLocalDeps;	ReverseDepMapType ReverseNonLocalDeps;

	/// Current AA implementation, just a cache.	/// Current AA implementation, just a cache.
	AliasAnalysis *AA;	AliasAnalysis *AA;
	TargetData *TD;	TargetData *TD;

		DominatorTree *DT;
	OwningPtr<PredIteratorCache> PredCache;	OwningPtr<PredIteratorCache> PredCache;
	public:	public:
	MemoryDependenceAnalysis();	MemoryDependenceAnalysis();
	~MemoryDependenceAnalysis();	~MemoryDependenceAnalysis();
	static char ID;	static char ID;

	/// Pass Implementation stuff. This doesn't do any analysis eagerly.	/// Pass Implementation stuff. This doesn't do any analysis eagerly.
	bool runOnFunction(Function &);	bool runOnFunction(Function &);

	/// Clean up memory in between runs	/// Clean up memory in between runs

	skipping to change at line 430	skipping to change at line 431
	SmallVectorImpl<NonLocalDepResult> &Re sult,	SmallVectorImpl<NonLocalDepResult> &Re sult,
	DenseMap<BasicBlock, Value> &Visited ,	DenseMap<BasicBlock, Value> &Visited ,
	bool SkipFirstBlock = false);	bool SkipFirstBlock = false);
	MemDepResult GetNonLocalInfoForBlock(const AliasAnalysis::Location &Loc ,	MemDepResult GetNonLocalInfoForBlock(const AliasAnalysis::Location &Loc ,
	bool isLoad, BasicBlock *BB,	bool isLoad, BasicBlock *BB,
	NonLocalDepInfo *Cache,	NonLocalDepInfo *Cache,
	unsigned NumSortedEntries);	unsigned NumSortedEntries);

	void RemoveCachedNonLocalPointerDependencies(ValueIsLoadPair P);	void RemoveCachedNonLocalPointerDependencies(ValueIsLoadPair P);


		AliasAnalysis::ModRefResult
		getModRefInfo(const Instruction *Inst, const AliasAnalysis::Location &L
		oc);

	/// verifyRemoved - Verify that the specified instruction does not occu r	/// verifyRemoved - Verify that the specified instruction does not occu r
	/// in our internal data structures.	/// in our internal data structures.
	void verifyRemoved(Instruction *Inst) const;	void verifyRemoved(Instruction *Inst) const;

	};	};

	} // End llvm namespace	} // End llvm namespace

	#endif	#endif

End of changes. 2 change blocks.
	0 lines changed or deleted	5 lines changed or added

	Metadata.h	Metadata.h

	skipping to change at line 38	skipping to change at line 38
	class Module;	class Module;
	template <typename T> class SmallVectorImpl;	template <typename T> class SmallVectorImpl;
	template<typename ValueSubClass, typename ItemParentClass>	template<typename ValueSubClass, typename ItemParentClass>
	class SymbolTableListTraits;	class SymbolTableListTraits;

	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	/// MDString - a single uniqued string.	/// MDString - a single uniqued string.
	/// These are used to efficiently contain a byte sequence for metadata.	/// These are used to efficiently contain a byte sequence for metadata.
	/// MDString is always unnamed.	/// MDString is always unnamed.
	class MDString : public Value {	class MDString : public Value {

		virtual void anchor();
	MDString(const MDString &); // DO NOT IMPLEMENT	MDString(const MDString &); // DO NOT IMPLEMENT


	StringRef Str;	explicit MDString(LLVMContext &C);
	explicit MDString(LLVMContext &C, StringRef S);

	public:	public:
	static MDString *get(LLVMContext &Context, StringRef Str);	static MDString *get(LLVMContext &Context, StringRef Str);
	static MDString get(LLVMContext &Context, const char Str) {	static MDString get(LLVMContext &Context, const char Str) {
	return get(Context, Str ? StringRef(Str) : StringRef());	return get(Context, Str ? StringRef(Str) : StringRef());
	}	}


	StringRef getString() const { return Str; }	StringRef getString() const { return getName(); }


	unsigned getLength() const { return (unsigned)Str.size(); }	unsigned getLength() const { return (unsigned)getName().size(); }

	typedef StringRef::iterator iterator;	typedef StringRef::iterator iterator;

	/// begin() - Pointer to the first byte of the string.	/// begin() - Pointer to the first byte of the string.

	///	iterator begin() const { return getName().begin(); }
	iterator begin() const { return Str.begin(); }

	/// end() - Pointer to one byte past the end of the string.	/// end() - Pointer to one byte past the end of the string.

	///	iterator end() const { return getName().end(); }
	iterator end() const { return Str.end(); }

	/// Methods for support type inquiry through isa, cast, and dyn_cast:	/// Methods for support type inquiry through isa, cast, and dyn_cast:
	static inline bool classof(const MDString *) { return true; }	static inline bool classof(const MDString *) { return true; }
	static bool classof(const Value *V) {	static bool classof(const Value *V) {
	return V->getValueID() == MDStringVal;	return V->getValueID() == MDStringVal;
	}	}
	};	};

	class MDNodeOperand;	class MDNodeOperand;

	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	/// MDNode - a tuple of other values.	/// MDNode - a tuple of other values.
	class MDNode : public Value, public FoldingSetNode {	class MDNode : public Value, public FoldingSetNode {
	MDNode(const MDNode &); // DO NOT IMPLEMENT	MDNode(const MDNode &); // DO NOT IMPLEMENT
	void operator=(const MDNode &); // DO NOT IMPLEMENT	void operator=(const MDNode &); // DO NOT IMPLEMENT
	friend class MDNodeOperand;	friend class MDNodeOperand;
	friend class LLVMContextImpl;	friend class LLVMContextImpl;

		friend struct FoldingSetTrait<MDNode>;

		/// Hash - If the MDNode is uniqued cache the hash to speed up lookup.
		unsigned Hash;

	/// NumOperands - This many 'MDNodeOperand' items are co-allocated onto t he	/// NumOperands - This many 'MDNodeOperand' items are co-allocated onto t he
	/// end of this MDNode.	/// end of this MDNode.
	unsigned NumOperands;	unsigned NumOperands;

	// Subclass data enums.	// Subclass data enums.
	enum {	enum {
	/// FunctionLocalBit - This bit is set if this MDNode is function local .	/// FunctionLocalBit - This bit is set if this MDNode is function local .
	/// This is true when it (potentially transitively) contains a referenc e to	/// This is true when it (potentially transitively) contains a referenc e to
	/// something in a function, like an argument, basicblock, or instructi on.	/// something in a function, like an argument, basicblock, or instructi on.

	skipping to change at line 136	skipping to change at line 137

	/// getTemporary - Return a temporary MDNode, for use in constructing	/// getTemporary - Return a temporary MDNode, for use in constructing
	/// cyclic MDNode structures. A temporary MDNode is not uniqued,	/// cyclic MDNode structures. A temporary MDNode is not uniqued,
	/// may be RAUW'd, and must be manually deleted with deleteTemporary.	/// may be RAUW'd, and must be manually deleted with deleteTemporary.
	static MDNode getTemporary(LLVMContext &Context, ArrayRef<Value> Vals);	static MDNode getTemporary(LLVMContext &Context, ArrayRef<Value> Vals);

	/// deleteTemporary - Deallocate a node created by getTemporary. The	/// deleteTemporary - Deallocate a node created by getTemporary. The
	/// node must not have any users.	/// node must not have any users.
	static void deleteTemporary(MDNode *N);	static void deleteTemporary(MDNode *N);


		/// replaceOperandWith - Replace a specific operand.
		void replaceOperandWith(unsigned i, Value *NewVal);

	/// getOperand - Return specified operand.	/// getOperand - Return specified operand.
	Value *getOperand(unsigned i) const;	Value *getOperand(unsigned i) const;

	/// getNumOperands - Return number of MDNode operands.	/// getNumOperands - Return number of MDNode operands.
	unsigned getNumOperands() const { return NumOperands; }	unsigned getNumOperands() const { return NumOperands; }

	/// isFunctionLocal - Return whether MDNode is local to a function.	/// isFunctionLocal - Return whether MDNode is local to a function.
	bool isFunctionLocal() const {	bool isFunctionLocal() const {
	return (getSubclassDataFromValue() & FunctionLocalBit) != 0;	return (getSubclassDataFromValue() & FunctionLocalBit) != 0;
	}	}

	skipping to change at line 226	skipping to change at line 230
	unsigned getNumOperands() const;	unsigned getNumOperands() const;

	/// addOperand - Add metadata operand.	/// addOperand - Add metadata operand.
	void addOperand(MDNode *M);	void addOperand(MDNode *M);

	/// getName - Return a constant reference to this named metadata's name.	/// getName - Return a constant reference to this named metadata's name.
	StringRef getName() const;	StringRef getName() const;

	/// print - Implement operator<< on NamedMDNode.	/// print - Implement operator<< on NamedMDNode.
	void print(raw_ostream &ROS, AssemblyAnnotationWriter *AAW = 0) const;	void print(raw_ostream &ROS, AssemblyAnnotationWriter *AAW = 0) const;


		/// dump() - Allow printing of NamedMDNodes from the debugger.
		void dump() const;
	};	};

	} // end llvm namespace	} // end llvm namespace

	#endif	#endif

End of changes. 9 change blocks.
	9 lines changed or deleted	16 lines changed or added

	Module.h	Module.h

	skipping to change at line 33	skipping to change at line 33
	#include "llvm/Support/DataTypes.h"	#include "llvm/Support/DataTypes.h"
	#include <vector>	#include <vector>

	namespace llvm {	namespace llvm {

	class FunctionType;	class FunctionType;
	class GVMaterializer;	class GVMaterializer;
	class LLVMContext;	class LLVMContext;
	class StructType;	class StructType;
	template<typename T> struct DenseMapInfo;	template<typename T> struct DenseMapInfo;

	template<typename KeyT, typename ValueT,	template<typename KeyT, typename ValueT, typename KeyInfoT> class DenseMap;
	typename KeyInfoT, typename ValueInfoT> class DenseMap;

	template<> struct ilist_traits<Function>	template<> struct ilist_traits<Function>
	: public SymbolTableListTraits<Function, Module> {	: public SymbolTableListTraits<Function, Module> {

	// createSentinel is used to get hold of the node that marks the end of t he	// createSentinel is used to get hold of the node that marks the end of t he
	// list... (same trick used here as in ilist_traits<Instruction>)	// list... (same trick used here as in ilist_traits<Instruction>)
	Function *createSentinel() const {	Function *createSentinel() const {
	return static_cast<Function*>(&Sentinel);	return static_cast<Function*>(&Sentinel);
	}	}
	static void destroySentinel(Function*) {}	static void destroySentinel(Function*) {}

	skipping to change at line 157	skipping to change at line 156
	typedef NamedMDListType::const_iterator const_named_metadata_iterator;	typedef NamedMDListType::const_iterator const_named_metadata_iterator;
	/// The Library list iterator.	/// The Library list iterator.
	typedef LibraryListType::const_iterator lib_iterator;	typedef LibraryListType::const_iterator lib_iterator;

	/// An enumeration for describing the endianess of the target machine.	/// An enumeration for describing the endianess of the target machine.
	enum Endianness { AnyEndianness, LittleEndian, BigEndian };	enum Endianness { AnyEndianness, LittleEndian, BigEndian };

	/// An enumeration for describing the size of a pointer on the target mac hine.	/// An enumeration for describing the size of a pointer on the target mac hine.
	enum PointerSize { AnyPointerSize, Pointer32, Pointer64 };	enum PointerSize { AnyPointerSize, Pointer32, Pointer64 };


		/// An enumeration for the supported behaviors of module flags. The follo
		wing
		/// module flags behavior values are supported:
		///
		/// Value Behavior
		/// ----- --------
		/// 1 Error
		/// Emits an error if two values disagree.
		///
		/// 2 Warning
		/// Emits a warning if two values disagree.
		///
		/// 3 Require
		/// Emits an error when the specified value is not pres
		ent
		/// or doesn't have the specified value. It is an error
		for
		/// two (or more) llvm.module.flags with the same ID to
		have
		/// the Require behavior but different values. There ma
		y be
		/// multiple Require flags per ID.
		///
		/// 4 Override
		/// Uses the specified value if the two values disagree
		. It
		/// is an error for two (or more) llvm.module.flags wit
		h the
		/// same ID to have the Override behavior but different
		/// values.
		enum ModFlagBehavior { Error = 1, Warning = 2, Require = 3, Override = 4
		};

		struct ModuleFlagEntry {
		ModFlagBehavior Behavior;
		MDString *Key;
		Value *Val;
		ModuleFlagEntry(ModFlagBehavior B, MDString K, Value V)
		: Behavior(B), Key(K), Val(V) {}
		};

	/// @}	/// @}
	/// @name Member Variables	/// @name Member Variables
	/// @{	/// @{
	private:	private:
	LLVMContext &Context; ///< The LLVMContext from which types and	LLVMContext &Context; ///< The LLVMContext from which types and
	///< constants are allocated.	///< constants are allocated.
	GlobalListType GlobalList; ///< The Global Variables in the module	GlobalListType GlobalList; ///< The Global Variables in the module
	FunctionListType FunctionList; ///< The Functions in the module	FunctionListType FunctionList; ///< The Functions in the module
	AliasListType AliasList; ///< The Aliases in the module	AliasListType AliasList; ///< The Aliases in the module
	LibraryListType LibraryList; ///< The Libraries needed by the module	LibraryListType LibraryList; ///< The Libraries needed by the module

	skipping to change at line 268	skipping to change at line 300
	GlobalValue *getNamedValue(StringRef Name) const;	GlobalValue *getNamedValue(StringRef Name) const;

	/// getMDKindID - Return a unique non-zero ID for the specified metadata kind.	/// getMDKindID - Return a unique non-zero ID for the specified metadata kind.
	/// This ID is uniqued across modules in the current LLVMContext.	/// This ID is uniqued across modules in the current LLVMContext.
	unsigned getMDKindID(StringRef Name) const;	unsigned getMDKindID(StringRef Name) const;

	/// getMDKindNames - Populate client supplied SmallVector with the name f or	/// getMDKindNames - Populate client supplied SmallVector with the name f or
	/// custom metadata IDs registered in this LLVMContext.	/// custom metadata IDs registered in this LLVMContext.
	void getMDKindNames(SmallVectorImpl<StringRef> &Result) const;	void getMDKindNames(SmallVectorImpl<StringRef> &Result) const;


	typedef DenseMap<StructType, unsigned, DenseMapInfo<StructType>,	typedef DenseMap<StructType, unsigned, DenseMapInfo<StructType> >
	DenseMapInfo<unsigned> > NumeredTypesMapTy;	NumeredTypesMapTy;

	/// findUsedStructTypes - Walk the entire module and find all of the	/// findUsedStructTypes - Walk the entire module and find all of the
	/// struct types that are in use, returning them in a vector.	/// struct types that are in use, returning them in a vector.
	void findUsedStructTypes(std::vector<StructType*> &StructTypes) const;	void findUsedStructTypes(std::vector<StructType*> &StructTypes) const;

	/// getTypeByName - Return the type with the specified name, or null if t here	/// getTypeByName - Return the type with the specified name, or null if t here
	/// is none by that name.	/// is none by that name.
	StructType *getTypeByName(StringRef Name) const;	StructType *getTypeByName(StringRef Name) const;

	/// @}	/// @}

	skipping to change at line 375	skipping to change at line 407
	/// getOrInsertNamedMetadata - Return the named MDNode in the module	/// getOrInsertNamedMetadata - Return the named MDNode in the module
	/// with the specified name. This method returns a new NamedMDNode if a	/// with the specified name. This method returns a new NamedMDNode if a
	/// NamedMDNode with the specified name is not found.	/// NamedMDNode with the specified name is not found.
	NamedMDNode *getOrInsertNamedMetadata(StringRef Name);	NamedMDNode *getOrInsertNamedMetadata(StringRef Name);

	/// eraseNamedMetadata - Remove the given NamedMDNode from this module	/// eraseNamedMetadata - Remove the given NamedMDNode from this module
	/// and delete it.	/// and delete it.
	void eraseNamedMetadata(NamedMDNode *NMD);	void eraseNamedMetadata(NamedMDNode *NMD);

	/// @}	/// @}

		/// @name Module Flags Accessors
		/// @{

		/// getModuleFlagsMetadata - Returns the module flags in the provided vec
		tor.
		void getModuleFlagsMetadata(SmallVectorImpl<ModuleFlagEntry> &Flags) cons
		t;

		/// getModuleFlagsMetadata - Returns the NamedMDNode in the module that
		/// represents module-level flags. This method returns null if there are
		no
		/// module-level flags.
		NamedMDNode *getModuleFlagsMetadata() const;

		/// getOrInsertModuleFlagsMetadata - Returns the NamedMDNode in the modul
		e
		/// that represents module-level flags. If module-level flags aren't foun
		d,
		/// it creates the named metadata that contains them.
		NamedMDNode *getOrInsertModuleFlagsMetadata();

		/// addModuleFlag - Add a module-level flag to the module-level flags
		/// metadata. It will create the module-level flags named metadata if it
		/// doesn't already exist.
		void addModuleFlag(ModFlagBehavior Behavior, StringRef Key, Value *Val);
		void addModuleFlag(ModFlagBehavior Behavior, StringRef Key, uint32_t Val)
		;
		void addModuleFlag(MDNode *Node);

		/// @}
	/// @name Materialization	/// @name Materialization
	/// @{	/// @{

	/// setMaterializer - Sets the GVMaterializer to GVM. This module must n ot	/// setMaterializer - Sets the GVMaterializer to GVM. This module must n ot
	/// yet have a Materializer. To reset the materializer for a module that	/// yet have a Materializer. To reset the materializer for a module that
	/// already has one, call MaterializeAllPermanently first. Destroying th is	/// already has one, call MaterializeAllPermanently first. Destroying th is
	/// module will destroy its materializer without materializing any more	/// module will destroy its materializer without materializing any more
	/// GlobalValues. Without destroying the Module, there is no way to deta ch or	/// GlobalValues. Without destroying the Module, there is no way to deta ch or
	/// destroy a materializer without materializing all the GVs it controls, to	/// destroy a materializer without materializing all the GVs it controls, to
	/// avoid leaving orphan unmaterialized GVs.	/// avoid leaving orphan unmaterialized GVs.

End of changes. 4 change blocks.
	4 lines changed or deleted	74 lines changed or added

	Object.h	Object.h

	skipping to change at line 31	skipping to change at line 31

	#include "llvm-c/Core.h"	#include "llvm-c/Core.h"
	#include "llvm/Config/llvm-config.h"	#include "llvm/Config/llvm-config.h"

	#ifdef __cplusplus	#ifdef __cplusplus
	#include "llvm/Object/ObjectFile.h"	#include "llvm/Object/ObjectFile.h"

	extern "C" {	extern "C" {
	#endif	#endif


	typedef struct LLVMOpaqueObjectFile *LLVMObjectFileRef;	/**
		* @defgroup LLVMCObject Object file reading and writing
		* @ingroup LLVMC
		*
		* @{
		*/


		// Opaque type wrappers
		typedef struct LLVMOpaqueObjectFile *LLVMObjectFileRef;
	typedef struct LLVMOpaqueSectionIterator *LLVMSectionIteratorRef;	typedef struct LLVMOpaqueSectionIterator *LLVMSectionIteratorRef;

		typedef struct LLVMOpaqueSymbolIterator *LLVMSymbolIteratorRef;
		typedef struct LLVMOpaqueRelocationIterator *LLVMRelocationIteratorRef;


		// ObjectFile creation
	LLVMObjectFileRef LLVMCreateObjectFile(LLVMMemoryBufferRef MemBuf);	LLVMObjectFileRef LLVMCreateObjectFile(LLVMMemoryBufferRef MemBuf);
	void LLVMDisposeObjectFile(LLVMObjectFileRef ObjectFile);	void LLVMDisposeObjectFile(LLVMObjectFileRef ObjectFile);


		// ObjectFile Section iterators
	LLVMSectionIteratorRef LLVMGetSections(LLVMObjectFileRef ObjectFile);	LLVMSectionIteratorRef LLVMGetSections(LLVMObjectFileRef ObjectFile);
	void LLVMDisposeSectionIterator(LLVMSectionIteratorRef SI);	void LLVMDisposeSectionIterator(LLVMSectionIteratorRef SI);
	LLVMBool LLVMIsSectionIteratorAtEnd(LLVMObjectFileRef ObjectFile,	LLVMBool LLVMIsSectionIteratorAtEnd(LLVMObjectFileRef ObjectFile,
	LLVMSectionIteratorRef SI);	LLVMSectionIteratorRef SI);
	void LLVMMoveToNextSection(LLVMSectionIteratorRef SI);	void LLVMMoveToNextSection(LLVMSectionIteratorRef SI);

		void LLVMMoveToContainingSection(LLVMSectionIteratorRef Sect,
		LLVMSymbolIteratorRef Sym);

		// ObjectFile Symbol iterators
		LLVMSymbolIteratorRef LLVMGetSymbols(LLVMObjectFileRef ObjectFile);
		void LLVMDisposeSymbolIterator(LLVMSymbolIteratorRef SI);
		LLVMBool LLVMIsSymbolIteratorAtEnd(LLVMObjectFileRef ObjectFile,
		LLVMSymbolIteratorRef SI);
		void LLVMMoveToNextSymbol(LLVMSymbolIteratorRef SI);

		// SectionRef accessors
	const char *LLVMGetSectionName(LLVMSectionIteratorRef SI);	const char *LLVMGetSectionName(LLVMSectionIteratorRef SI);
	uint64_t LLVMGetSectionSize(LLVMSectionIteratorRef SI);	uint64_t LLVMGetSectionSize(LLVMSectionIteratorRef SI);
	const char *LLVMGetSectionContents(LLVMSectionIteratorRef SI);	const char *LLVMGetSectionContents(LLVMSectionIteratorRef SI);

		uint64_t LLVMGetSectionAddress(LLVMSectionIteratorRef SI);
		LLVMBool LLVMGetSectionContainsSymbol(LLVMSectionIteratorRef SI,
		LLVMSymbolIteratorRef Sym);

		// Section Relocation iterators
		LLVMRelocationIteratorRef LLVMGetRelocations(LLVMSectionIteratorRef Section
		);
		void LLVMDisposeRelocationIterator(LLVMRelocationIteratorRef RI);
		LLVMBool LLVMIsRelocationIteratorAtEnd(LLVMSectionIteratorRef Section,
		LLVMRelocationIteratorRef RI);
		void LLVMMoveToNextRelocation(LLVMRelocationIteratorRef RI);

		// SymbolRef accessors
		const char *LLVMGetSymbolName(LLVMSymbolIteratorRef SI);
		uint64_t LLVMGetSymbolAddress(LLVMSymbolIteratorRef SI);
		uint64_t LLVMGetSymbolFileOffset(LLVMSymbolIteratorRef SI);
		uint64_t LLVMGetSymbolSize(LLVMSymbolIteratorRef SI);

		// RelocationRef accessors
		uint64_t LLVMGetRelocationAddress(LLVMRelocationIteratorRef RI);
		uint64_t LLVMGetRelocationOffset(LLVMRelocationIteratorRef RI);
		LLVMSymbolIteratorRef LLVMGetRelocationSymbol(LLVMRelocationIteratorRef RI)
		;
		uint64_t LLVMGetRelocationType(LLVMRelocationIteratorRef RI);
		// NOTE: Caller takes ownership of returned string of the two
		// following functions.
		const char *LLVMGetRelocationTypeName(LLVMRelocationIteratorRef RI);
		const char *LLVMGetRelocationValueString(LLVMRelocationIteratorRef RI);

		/**
		* @}
		*/

	#ifdef __cplusplus	#ifdef __cplusplus
	}	}

	namespace llvm {	namespace llvm {
	namespace object {	namespace object {
	inline ObjectFile *unwrap(LLVMObjectFileRef OF) {	inline ObjectFile *unwrap(LLVMObjectFileRef OF) {
	return reinterpret_cast<ObjectFile*>(OF);	return reinterpret_cast<ObjectFile*>(OF);
	}	}


	skipping to change at line 69	skipping to change at line 121

	inline section_iterator *unwrap(LLVMSectionIteratorRef SI) {	inline section_iterator *unwrap(LLVMSectionIteratorRef SI) {
	return reinterpret_cast<section_iterator*>(SI);	return reinterpret_cast<section_iterator*>(SI);
	}	}

	inline LLVMSectionIteratorRef	inline LLVMSectionIteratorRef
	wrap(const section_iterator *SI) {	wrap(const section_iterator *SI) {
	return reinterpret_cast<LLVMSectionIteratorRef>	return reinterpret_cast<LLVMSectionIteratorRef>
	(const_cast<section_iterator*>(SI));	(const_cast<section_iterator*>(SI));
	}	}


		inline symbol_iterator *unwrap(LLVMSymbolIteratorRef SI) {
		return reinterpret_cast<symbol_iterator*>(SI);
		}

		inline LLVMSymbolIteratorRef
		wrap(const symbol_iterator *SI) {
		return reinterpret_cast<LLVMSymbolIteratorRef>
		(const_cast<symbol_iterator*>(SI));
		}

		inline relocation_iterator *unwrap(LLVMRelocationIteratorRef SI) {
		return reinterpret_cast<relocation_iterator*>(SI);
		}

		inline LLVMRelocationIteratorRef
		wrap(const relocation_iterator *SI) {
		return reinterpret_cast<LLVMRelocationIteratorRef>
		(const_cast<relocation_iterator*>(SI));
		}

	}	}
	}	}

	#endif /* defined(__cplusplus) */	#endif /* defined(__cplusplus) */

	#endif	#endif

End of changes. 8 change blocks.
	1 lines changed or deleted	76 lines changed or added

	ObjectFile.h	ObjectFile.h

	skipping to change at line 23	skipping to change at line 23

	#ifndef LLVM_OBJECT_OBJECT_FILE_H	#ifndef LLVM_OBJECT_OBJECT_FILE_H
	#define LLVM_OBJECT_OBJECT_FILE_H	#define LLVM_OBJECT_OBJECT_FILE_H

	#include "llvm/Object/Binary.h"	#include "llvm/Object/Binary.h"
	#include "llvm/ADT/StringRef.h"	#include "llvm/ADT/StringRef.h"
	#include "llvm/Support/DataTypes.h"	#include "llvm/Support/DataTypes.h"
	#include "llvm/Support/ErrorHandling.h"	#include "llvm/Support/ErrorHandling.h"
	#include "llvm/Support/MemoryBuffer.h"	#include "llvm/Support/MemoryBuffer.h"
	#include <cstring>	#include <cstring>

		#include <vector>

	namespace llvm {	namespace llvm {
	namespace object {	namespace object {

	class ObjectFile;	class ObjectFile;

	union DataRefImpl {	union DataRefImpl {
	struct {	struct {
	// ELF needs this for relocations. This entire union should probably be a	// ELF needs this for relocations. This entire union should probably be a
	// char[max(8, sizeof(uintptr_t))] and require the impl to cast.	// char[max(8, sizeof(uintptr_t))] and require the impl to cast.
	uint16_t a, b;	uint16_t a, b;
	uint32_t c;	uint32_t c;
	} w;	} w;
	struct {	struct {
	uint32_t a, b;	uint32_t a, b;
	} d;	} d;
	uintptr_t p;	uintptr_t p;

		DataRefImpl() {
		std::memset(this, 0, sizeof(DataRefImpl));
		}
	};	};

	template<class content_type>	template<class content_type>
	class content_iterator {	class content_iterator {
	content_type Current;	content_type Current;
	public:	public:
	content_iterator(content_type symb)	content_iterator(content_type symb)
	: Current(symb) {}	: Current(symb) {}

	const content_type* operator->() const {	const content_type* operator->() const {

	skipping to change at line 81	skipping to change at line 85
	return *this;	return *this;
	}	}
	};	};

	static bool operator ==(const DataRefImpl &a, const DataRefImpl &b) {	static bool operator ==(const DataRefImpl &a, const DataRefImpl &b) {
	// Check bitwise identical. This is the only legal way to compare a union w/o	// Check bitwise identical. This is the only legal way to compare a union w/o
	// knowing which member is in use.	// knowing which member is in use.
	return std::memcmp(&a, &b, sizeof(DataRefImpl)) == 0;	return std::memcmp(&a, &b, sizeof(DataRefImpl)) == 0;
	}	}


	/// SymbolRef - This is a value type class that represents a single symbol	static bool operator <(const DataRefImpl &a, const DataRefImpl &b) {
	in	// Check bitwise identical. This is the only legal way to compare a union
	/// the list of symbols in the object file.	w/o
	class SymbolRef {	// knowing which member is in use.
	friend class SectionRef;	return std::memcmp(&a, &b, sizeof(DataRefImpl)) < 0;
	DataRefImpl SymbolPimpl;	}
	const ObjectFile *OwningObject;

	public:
	SymbolRef() : OwningObject(NULL) {
	std::memset(&SymbolPimpl, 0, sizeof(SymbolPimpl));
	}

	enum SymbolType {
	ST_Function,
	ST_Data,
	ST_External, // Defined in another object file
	ST_Other
	};

	SymbolRef(DataRefImpl SymbolP, const ObjectFile *Owner);

	bool operator==(const SymbolRef &Other) const;

	error_code getNext(SymbolRef &Result) const;

	error_code getName(StringRef &Result) const;
	error_code getAddress(uint64_t &Result) const;
	error_code getOffset(uint64_t &Result) const;
	error_code getSize(uint64_t &Result) const;
	error_code getSymbolType(SymbolRef::SymbolType &Result) const;

	/// Returns the ascii char that should be displayed in a symbol table dum
	p via
	/// nm for this symbol.
	error_code getNMTypeChar(char &Result) const;

	/// Returns true for symbols that are internal to the object file format
	such
	/// as section symbols.
	error_code isInternal(bool &Result) const;

	/// Returns true for symbols that can be used in another objects,
	/// such as library functions
	error_code isGlobal(bool &Result) const;


	DataRefImpl getRawDataRefImpl() const;	class SymbolRef;
	};
	typedef content_iterator<SymbolRef> symbol_iterator;

	/// RelocationRef - This is a value type class that represents a single	/// RelocationRef - This is a value type class that represents a single
	/// relocation in the list of relocations in the object file.	/// relocation in the list of relocations in the object file.
	class RelocationRef {	class RelocationRef {
	DataRefImpl RelocationPimpl;	DataRefImpl RelocationPimpl;
	const ObjectFile *OwningObject;	const ObjectFile *OwningObject;

	public:	public:

	RelocationRef() : OwningObject(NULL) {	RelocationRef() : OwningObject(NULL) { }
	std::memset(&RelocationPimpl, 0, sizeof(RelocationPimpl));
	}

	RelocationRef(DataRefImpl RelocationP, const ObjectFile *Owner);	RelocationRef(DataRefImpl RelocationP, const ObjectFile *Owner);

	bool operator==(const RelocationRef &Other) const;	bool operator==(const RelocationRef &Other) const;

	error_code getNext(RelocationRef &Result) const;	error_code getNext(RelocationRef &Result) const;

	error_code getAddress(uint64_t &Result) const;	error_code getAddress(uint64_t &Result) const;

		error_code getOffset(uint64_t &Result) const;
	error_code getSymbol(SymbolRef &Result) const;	error_code getSymbol(SymbolRef &Result) const;

	error_code getType(uint32_t &Result) const;	error_code getType(uint64_t &Result) const;

		/// @brief Indicates whether this relocation should hidden when listing
		/// relocations, usually because it is the trailing part of a multipart
		/// relocation that will be printed as part of the leading relocation.
		error_code getHidden(bool &Result) const;

	/// @brief Get a string that represents the type of this relocation.	/// @brief Get a string that represents the type of this relocation.
	///	///
	/// This is for display purposes only.	/// This is for display purposes only.
	error_code getTypeName(SmallVectorImpl<char> &Result) const;	error_code getTypeName(SmallVectorImpl<char> &Result) const;
	error_code getAdditionalInfo(int64_t &Result) const;	error_code getAdditionalInfo(int64_t &Result) const;

	/// @brief Get a string that represents the calculation of the value of t his	/// @brief Get a string that represents the calculation of the value of t his
	/// relocation.	/// relocation.
	///	///

	skipping to change at line 171	skipping to change at line 140
	typedef content_iterator<RelocationRef> relocation_iterator;	typedef content_iterator<RelocationRef> relocation_iterator;

	/// SectionRef - This is a value type class that represents a single sectio n in	/// SectionRef - This is a value type class that represents a single sectio n in
	/// the list of sections in the object file.	/// the list of sections in the object file.
	class SectionRef {	class SectionRef {
	friend class SymbolRef;	friend class SymbolRef;
	DataRefImpl SectionPimpl;	DataRefImpl SectionPimpl;
	const ObjectFile *OwningObject;	const ObjectFile *OwningObject;

	public:	public:

	SectionRef() : OwningObject(NULL) {	SectionRef() : OwningObject(NULL) { }
	std::memset(&SectionPimpl, 0, sizeof(SectionPimpl));
	}

	SectionRef(DataRefImpl SectionP, const ObjectFile *Owner);	SectionRef(DataRefImpl SectionP, const ObjectFile *Owner);

	bool operator==(const SectionRef &Other) const;	bool operator==(const SectionRef &Other) const;

		bool operator <(const SectionRef &Other) const;

	error_code getNext(SectionRef &Result) const;	error_code getNext(SectionRef &Result) const;

	error_code getName(StringRef &Result) const;	error_code getName(StringRef &Result) const;
	error_code getAddress(uint64_t &Result) const;	error_code getAddress(uint64_t &Result) const;
	error_code getSize(uint64_t &Result) const;	error_code getSize(uint64_t &Result) const;
	error_code getContents(StringRef &Result) const;	error_code getContents(StringRef &Result) const;

	/// @brief Get the alignment of this section as the actual value (not log 2).	/// @brief Get the alignment of this section as the actual value (not log 2).
	error_code getAlignment(uint64_t &Result) const;	error_code getAlignment(uint64_t &Result) const;

	// FIXME: Move to the normalization layer when it's created.	// FIXME: Move to the normalization layer when it's created.
	error_code isText(bool &Result) const;	error_code isText(bool &Result) const;
	error_code isData(bool &Result) const;	error_code isData(bool &Result) const;
	error_code isBSS(bool &Result) const;	error_code isBSS(bool &Result) const;

		error_code isRequiredForExecution(bool &Result) const;
		error_code isVirtual(bool &Result) const;
		error_code isZeroInit(bool &Result) const;

	error_code containsSymbol(SymbolRef S, bool &Result) const;	error_code containsSymbol(SymbolRef S, bool &Result) const;

	relocation_iterator begin_relocations() const;	relocation_iterator begin_relocations() const;
	relocation_iterator end_relocations() const;	relocation_iterator end_relocations() const;


		DataRefImpl getRawDataRefImpl() const;
	};	};
	typedef content_iterator<SectionRef> section_iterator;	typedef content_iterator<SectionRef> section_iterator;


		/// SymbolRef - This is a value type class that represents a single symbol
		in
		/// the list of symbols in the object file.
		class SymbolRef {
		friend class SectionRef;
		DataRefImpl SymbolPimpl;
		const ObjectFile *OwningObject;

		public:
		SymbolRef() : OwningObject(NULL) { }

		enum Type {
		ST_Unknown, // Type not specified
		ST_Data,
		ST_Debug,
		ST_File,
		ST_Function,
		ST_Other
		};

		enum Flags {
		SF_None = 0,
		SF_Undefined = 1U << 0, // Symbol is defined in another object f
		ile
		SF_Global = 1U << 1, // Global symbol
		SF_Weak = 1U << 2, // Weak symbol
		SF_Absolute = 1U << 3, // Absolute symbol
		SF_ThreadLocal = 1U << 4, // Thread local symbol
		SF_Common = 1U << 5, // Symbol has common linkage
		SF_FormatSpecific = 1U << 31 // Specific to the object file format
		// (e.g. section symbols)
		};

		SymbolRef(DataRefImpl SymbolP, const ObjectFile *Owner);

		bool operator==(const SymbolRef &Other) const;
		bool operator <(const SymbolRef &Other) const;

		error_code getNext(SymbolRef &Result) const;

		error_code getName(StringRef &Result) const;
		error_code getAddress(uint64_t &Result) const;
		error_code getFileOffset(uint64_t &Result) const;
		error_code getSize(uint64_t &Result) const;
		error_code getType(SymbolRef::Type &Result) const;

		/// Returns the ascii char that should be displayed in a symbol table dum
		p via
		/// nm for this symbol.
		error_code getNMTypeChar(char &Result) const;

		/// Get symbol flags (bitwise OR of SymbolRef::Flags)
		error_code getFlags(uint32_t &Result) const;

		/// @brief Return true for common symbols such as uninitialized globals
		error_code isCommon(bool &Result) const;

		/// @brief Get section this symbol is defined in reference to. Result is
		/// end_sections() if it is undefined or is an absolute symbol.
		error_code getSection(section_iterator &Result) const;

		DataRefImpl getRawDataRefImpl() const;
		};
		typedef content_iterator<SymbolRef> symbol_iterator;

		/// LibraryRef - This is a value type class that represents a single librar
		y in
		/// the list of libraries needed by a shared or dynamic object.
		class LibraryRef {
		friend class SectionRef;
		DataRefImpl LibraryPimpl;
		const ObjectFile *OwningObject;

		public:
		LibraryRef() : OwningObject(NULL) { }

		LibraryRef(DataRefImpl LibraryP, const ObjectFile *Owner);

		bool operator==(const LibraryRef &Other) const;
		bool operator <(const LibraryRef &Other) const;

		error_code getNext(LibraryRef &Result) const;

		// Get the path to this library, as stored in the object file.
		error_code getPath(StringRef &Result) const;

		DataRefImpl getRawDataRefImpl() const;
		};
		typedef content_iterator<LibraryRef> library_iterator;

	const uint64_t UnknownAddressOrSize = ~0ULL;	const uint64_t UnknownAddressOrSize = ~0ULL;

	/// ObjectFile - This class is the base class for all object file types.	/// ObjectFile - This class is the base class for all object file types.
	/// Concrete instances of this object are created by createObjectFile, whic h	/// Concrete instances of this object are created by createObjectFile, whic h
	/// figure out which type to create.	/// figure out which type to create.
	class ObjectFile : public Binary {	class ObjectFile : public Binary {

	private:	virtual void anchor();
	ObjectFile(); // = delete	ObjectFile(); // = delete
	ObjectFile(const ObjectFile &other); // = delete	ObjectFile(const ObjectFile &other); // = delete

	protected:	protected:
	ObjectFile(unsigned int Type, MemoryBuffer *source, error_code &ec);	ObjectFile(unsigned int Type, MemoryBuffer *source, error_code &ec);

	const uint8_t *base() const {	const uint8_t *base() const {
	return reinterpret_cast<const uint8_t *>(Data->getBufferStart());	return reinterpret_cast<const uint8_t *>(Data->getBufferStart());
	}	}


	skipping to change at line 230	skipping to change at line 289
	// entry in the memory mapped object file. SymbolPimpl cannot contain any	// entry in the memory mapped object file. SymbolPimpl cannot contain any
	// virtual functions because then it could not point into the memory mapp ed	// virtual functions because then it could not point into the memory mapp ed
	// file.	// file.
	//	//
	// Implementations assume that the DataRefImpl is valid and has not been	// Implementations assume that the DataRefImpl is valid and has not been
	// modified externally. It's UB otherwise.	// modified externally. It's UB otherwise.
	friend class SymbolRef;	friend class SymbolRef;
	virtual error_code getSymbolNext(DataRefImpl Symb, SymbolRef &Res) const = 0;	virtual error_code getSymbolNext(DataRefImpl Symb, SymbolRef &Res) const = 0;
	virtual error_code getSymbolName(DataRefImpl Symb, StringRef &Res) const = 0;	virtual error_code getSymbolName(DataRefImpl Symb, StringRef &Res) const = 0;
	virtual error_code getSymbolAddress(DataRefImpl Symb, uint64_t &Res) cons t =0;	virtual error_code getSymbolAddress(DataRefImpl Symb, uint64_t &Res) cons t =0;

	virtual error_code getSymbolOffset(DataRefImpl Symb, uint64_t &Res) const =0;	virtual error_code getSymbolFileOffset(DataRefImpl Symb, uint64_t &Res) c onst =0;
	virtual error_code getSymbolSize(DataRefImpl Symb, uint64_t &Res) const = 0;	virtual error_code getSymbolSize(DataRefImpl Symb, uint64_t &Res) const = 0;

		virtual error_code getSymbolType(DataRefImpl Symb,
		SymbolRef::Type &Res) const = 0;
	virtual error_code getSymbolNMTypeChar(DataRefImpl Symb, char &Res) const = 0;	virtual error_code getSymbolNMTypeChar(DataRefImpl Symb, char &Res) const = 0;

	virtual error_code isSymbolInternal(DataRefImpl Symb, bool &Res) const =	virtual error_code getSymbolFlags(DataRefImpl Symb,
	0;	uint32_t &Res) const = 0;
	virtual error_code isSymbolGlobal(DataRefImpl Symb, bool &Res) const = 0;	virtual error_code getSymbolSection(DataRefImpl Symb,
	virtual error_code getSymbolType(DataRefImpl Symb, SymbolRef::SymbolType	section_iterator &Res) const = 0;
	&Res) const = 0;

	// Same as above for SectionRef.	// Same as above for SectionRef.
	friend class SectionRef;	friend class SectionRef;
	virtual error_code getSectionNext(DataRefImpl Sec, SectionRef &Res) const = 0;	virtual error_code getSectionNext(DataRefImpl Sec, SectionRef &Res) const = 0;
	virtual error_code getSectionName(DataRefImpl Sec, StringRef &Res) const = 0;	virtual error_code getSectionName(DataRefImpl Sec, StringRef &Res) const = 0;
	virtual error_code getSectionAddress(DataRefImpl Sec, uint64_t &Res) cons t =0;	virtual error_code getSectionAddress(DataRefImpl Sec, uint64_t &Res) cons t =0;
	virtual error_code getSectionSize(DataRefImpl Sec, uint64_t &Res) const = 0;	virtual error_code getSectionSize(DataRefImpl Sec, uint64_t &Res) const = 0;
	virtual error_code getSectionContents(DataRefImpl Sec, StringRef &Res)con st=0;	virtual error_code getSectionContents(DataRefImpl Sec, StringRef &Res)con st=0;
	virtual error_code getSectionAlignment(DataRefImpl Sec, uint64_t &Res)con st=0;	virtual error_code getSectionAlignment(DataRefImpl Sec, uint64_t &Res)con st=0;
	virtual error_code isSectionText(DataRefImpl Sec, bool &Res) const = 0;	virtual error_code isSectionText(DataRefImpl Sec, bool &Res) const = 0;
	virtual error_code isSectionData(DataRefImpl Sec, bool &Res) const = 0;	virtual error_code isSectionData(DataRefImpl Sec, bool &Res) const = 0;
	virtual error_code isSectionBSS(DataRefImpl Sec, bool &Res) const = 0;	virtual error_code isSectionBSS(DataRefImpl Sec, bool &Res) const = 0;

		virtual error_code isSectionRequiredForExecution(DataRefImpl Sec,
		bool &Res) const = 0;
		// A section is 'virtual' if its contents aren't present in the object im
		age.
		virtual error_code isSectionVirtual(DataRefImpl Sec, bool &Res) const = 0
		;
		virtual error_code isSectionZeroInit(DataRefImpl Sec, bool &Res) const =
		0;
	virtual error_code sectionContainsSymbol(DataRefImpl Sec, DataRefImpl Sym b,	virtual error_code sectionContainsSymbol(DataRefImpl Sec, DataRefImpl Sym b,
	bool &Result) const = 0;	bool &Result) const = 0;
	virtual relocation_iterator getSectionRelBegin(DataRefImpl Sec) const = 0 ;	virtual relocation_iterator getSectionRelBegin(DataRefImpl Sec) const = 0 ;
	virtual relocation_iterator getSectionRelEnd(DataRefImpl Sec) const = 0;	virtual relocation_iterator getSectionRelEnd(DataRefImpl Sec) const = 0;

	// Same as above for RelocationRef.	// Same as above for RelocationRef.
	friend class RelocationRef;	friend class RelocationRef;
	virtual error_code getRelocationNext(DataRefImpl Rel,	virtual error_code getRelocationNext(DataRefImpl Rel,
	RelocationRef &Res) const = 0;	RelocationRef &Res) const = 0;
	virtual error_code getRelocationAddress(DataRefImpl Rel,	virtual error_code getRelocationAddress(DataRefImpl Rel,
	uint64_t &Res) const =0;	uint64_t &Res) const =0;

		virtual error_code getRelocationOffset(DataRefImpl Rel,
		uint64_t &Res) const =0;
	virtual error_code getRelocationSymbol(DataRefImpl Rel,	virtual error_code getRelocationSymbol(DataRefImpl Rel,
	SymbolRef &Res) const = 0;	SymbolRef &Res) const = 0;
	virtual error_code getRelocationType(DataRefImpl Rel,	virtual error_code getRelocationType(DataRefImpl Rel,

	uint32_t &Res) const = 0;	uint64_t &Res) const = 0;
	virtual error_code getRelocationTypeName(DataRefImpl Rel,	virtual error_code getRelocationTypeName(DataRefImpl Rel,
	SmallVectorImpl<char> &Result) const = 0;	SmallVectorImpl<char> &Result) const = 0;
	virtual error_code getRelocationAdditionalInfo(DataRefImpl Rel,	virtual error_code getRelocationAdditionalInfo(DataRefImpl Rel,
	int64_t &Res) const = 0;	int64_t &Res) const = 0;
	virtual error_code getRelocationValueString(DataRefImpl Rel,	virtual error_code getRelocationValueString(DataRefImpl Rel,
	SmallVectorImpl<char> &Result) const = 0;	SmallVectorImpl<char> &Result) const = 0;

		virtual error_code getRelocationHidden(DataRefImpl Rel, bool &Result) con
		st {
		Result = false;
		return object_error::success;
		}

		// Same for LibraryRef
		friend class LibraryRef;
		virtual error_code getLibraryNext(DataRefImpl Lib, LibraryRef &Res) const
		= 0;
		virtual error_code getLibraryPath(DataRefImpl Lib, StringRef &Res) const
		= 0;

	public:	public:

	virtual symbol_iterator begin_symbols() const = 0;	virtual symbol_iterator begin_symbols() const = 0;
	virtual symbol_iterator end_symbols() const = 0;	virtual symbol_iterator end_symbols() const = 0;


		virtual symbol_iterator begin_dynamic_symbols() const = 0;
		virtual symbol_iterator end_dynamic_symbols() const = 0;

	virtual section_iterator begin_sections() const = 0;	virtual section_iterator begin_sections() const = 0;
	virtual section_iterator end_sections() const = 0;	virtual section_iterator end_sections() const = 0;


		virtual library_iterator begin_libraries_needed() const = 0;
		virtual library_iterator end_libraries_needed() const = 0;

	/// @brief The number of bytes used to represent an address in this objec t	/// @brief The number of bytes used to represent an address in this objec t
	/// file format.	/// file format.
	virtual uint8_t getBytesInAddress() const = 0;	virtual uint8_t getBytesInAddress() const = 0;

	virtual StringRef getFileFormatName() const = 0;	virtual StringRef getFileFormatName() const = 0;
	virtual /* Triple::ArchType */ unsigned getArch() const = 0;	virtual /* Triple::ArchType */ unsigned getArch() const = 0;


		/// For shared objects, returns the name which this object should be
		/// loaded from at runtime. This corresponds to DT_SONAME on ELF and
		/// LC_ID_DYLIB (install name) on MachO.
		virtual StringRef getLoadName() const = 0;

	/// @returns Pointer to ObjectFile subclass to handle this type of object .	/// @returns Pointer to ObjectFile subclass to handle this type of object .
	/// @param ObjectPath The path to the object file. ObjectPath.isObject mu st	/// @param ObjectPath The path to the object file. ObjectPath.isObject mu st
	/// return true.	/// return true.
	/// @brief Create ObjectFile from path.	/// @brief Create ObjectFile from path.
	static ObjectFile *createObjectFile(StringRef ObjectPath);	static ObjectFile *createObjectFile(StringRef ObjectPath);
	static ObjectFile createObjectFile(MemoryBuffer Object);	static ObjectFile createObjectFile(MemoryBuffer Object);

	static inline bool classof(const Binary *v) {	static inline bool classof(const Binary *v) {

	return v->getType() >= isObject &&	return v->isObject();
	v->getType() < lastObject;
	}	}
	static inline bool classof(const ObjectFile *v) { return true; }	static inline bool classof(const ObjectFile *v) { return true; }

	public:	public:
	static ObjectFile createCOFFObjectFile(MemoryBuffer Object);	static ObjectFile createCOFFObjectFile(MemoryBuffer Object);
	static ObjectFile createELFObjectFile(MemoryBuffer Object);	static ObjectFile createELFObjectFile(MemoryBuffer Object);
	static ObjectFile createMachOObjectFile(MemoryBuffer Object);	static ObjectFile createMachOObjectFile(MemoryBuffer Object);
	};	};

	// Inline function definitions.	// Inline function definitions.
	inline SymbolRef::SymbolRef(DataRefImpl SymbolP, const ObjectFile *Owner)	inline SymbolRef::SymbolRef(DataRefImpl SymbolP, const ObjectFile *Owner)
	: SymbolPimpl(SymbolP)	: SymbolPimpl(SymbolP)
	, OwningObject(Owner) {}	, OwningObject(Owner) {}

	inline bool SymbolRef::operator==(const SymbolRef &Other) const {	inline bool SymbolRef::operator==(const SymbolRef &Other) const {
	return SymbolPimpl == Other.SymbolPimpl;	return SymbolPimpl == Other.SymbolPimpl;
	}	}


		inline bool SymbolRef::operator <(const SymbolRef &Other) const {
		return SymbolPimpl < Other.SymbolPimpl;
		}

	inline error_code SymbolRef::getNext(SymbolRef &Result) const {	inline error_code SymbolRef::getNext(SymbolRef &Result) const {
	return OwningObject->getSymbolNext(SymbolPimpl, Result);	return OwningObject->getSymbolNext(SymbolPimpl, Result);
	}	}

	inline error_code SymbolRef::getName(StringRef &Result) const {	inline error_code SymbolRef::getName(StringRef &Result) const {
	return OwningObject->getSymbolName(SymbolPimpl, Result);	return OwningObject->getSymbolName(SymbolPimpl, Result);
	}	}

	inline error_code SymbolRef::getAddress(uint64_t &Result) const {	inline error_code SymbolRef::getAddress(uint64_t &Result) const {
	return OwningObject->getSymbolAddress(SymbolPimpl, Result);	return OwningObject->getSymbolAddress(SymbolPimpl, Result);
	}	}


	inline error_code SymbolRef::getOffset(uint64_t &Result) const {	inline error_code SymbolRef::getFileOffset(uint64_t &Result) const {
	return OwningObject->getSymbolOffset(SymbolPimpl, Result);	return OwningObject->getSymbolFileOffset(SymbolPimpl, Result);
	}	}

	inline error_code SymbolRef::getSize(uint64_t &Result) const {	inline error_code SymbolRef::getSize(uint64_t &Result) const {
	return OwningObject->getSymbolSize(SymbolPimpl, Result);	return OwningObject->getSymbolSize(SymbolPimpl, Result);
	}	}

	inline error_code SymbolRef::getNMTypeChar(char &Result) const {	inline error_code SymbolRef::getNMTypeChar(char &Result) const {
	return OwningObject->getSymbolNMTypeChar(SymbolPimpl, Result);	return OwningObject->getSymbolNMTypeChar(SymbolPimpl, Result);
	}	}


	inline error_code SymbolRef::isInternal(bool &Result) const {	inline error_code SymbolRef::getFlags(uint32_t &Result) const {
	return OwningObject->isSymbolInternal(SymbolPimpl, Result);	return OwningObject->getSymbolFlags(SymbolPimpl, Result);
	}	}


	inline error_code SymbolRef::isGlobal(bool &Result) const {	inline error_code SymbolRef::getSection(section_iterator &Result) const {
	return OwningObject->isSymbolGlobal(SymbolPimpl, Result);	return OwningObject->getSymbolSection(SymbolPimpl, Result);
	}	}


	inline error_code SymbolRef::getSymbolType(SymbolRef::SymbolType &Result) c onst {	inline error_code SymbolRef::getType(SymbolRef::Type &Result) const {
	return OwningObject->getSymbolType(SymbolPimpl, Result);	return OwningObject->getSymbolType(SymbolPimpl, Result);
	}	}

	inline DataRefImpl SymbolRef::getRawDataRefImpl() const {	inline DataRefImpl SymbolRef::getRawDataRefImpl() const {
	return SymbolPimpl;	return SymbolPimpl;
	}	}

	/// SectionRef	/// SectionRef
	inline SectionRef::SectionRef(DataRefImpl SectionP,	inline SectionRef::SectionRef(DataRefImpl SectionP,
	const ObjectFile *Owner)	const ObjectFile *Owner)
	: SectionPimpl(SectionP)	: SectionPimpl(SectionP)
	, OwningObject(Owner) {}	, OwningObject(Owner) {}

	inline bool SectionRef::operator==(const SectionRef &Other) const {	inline bool SectionRef::operator==(const SectionRef &Other) const {
	return SectionPimpl == Other.SectionPimpl;	return SectionPimpl == Other.SectionPimpl;
	}	}


		inline bool SectionRef::operator <(const SectionRef &Other) const {
		return SectionPimpl < Other.SectionPimpl;
		}

	inline error_code SectionRef::getNext(SectionRef &Result) const {	inline error_code SectionRef::getNext(SectionRef &Result) const {
	return OwningObject->getSectionNext(SectionPimpl, Result);	return OwningObject->getSectionNext(SectionPimpl, Result);
	}	}

	inline error_code SectionRef::getName(StringRef &Result) const {	inline error_code SectionRef::getName(StringRef &Result) const {
	return OwningObject->getSectionName(SectionPimpl, Result);	return OwningObject->getSectionName(SectionPimpl, Result);
	}	}

	inline error_code SectionRef::getAddress(uint64_t &Result) const {	inline error_code SectionRef::getAddress(uint64_t &Result) const {
	return OwningObject->getSectionAddress(SectionPimpl, Result);	return OwningObject->getSectionAddress(SectionPimpl, Result);

	skipping to change at line 399	skipping to change at line 495
	}	}

	inline error_code SectionRef::isData(bool &Result) const {	inline error_code SectionRef::isData(bool &Result) const {
	return OwningObject->isSectionData(SectionPimpl, Result);	return OwningObject->isSectionData(SectionPimpl, Result);
	}	}

	inline error_code SectionRef::isBSS(bool &Result) const {	inline error_code SectionRef::isBSS(bool &Result) const {
	return OwningObject->isSectionBSS(SectionPimpl, Result);	return OwningObject->isSectionBSS(SectionPimpl, Result);
	}	}


		inline error_code SectionRef::isRequiredForExecution(bool &Result) const {
		return OwningObject->isSectionRequiredForExecution(SectionPimpl, Result);
		}

		inline error_code SectionRef::isVirtual(bool &Result) const {
		return OwningObject->isSectionVirtual(SectionPimpl, Result);
		}

		inline error_code SectionRef::isZeroInit(bool &Result) const {
		return OwningObject->isSectionZeroInit(SectionPimpl, Result);
		}

	inline error_code SectionRef::containsSymbol(SymbolRef S, bool &Result) con st {	inline error_code SectionRef::containsSymbol(SymbolRef S, bool &Result) con st {
	return OwningObject->sectionContainsSymbol(SectionPimpl, S.SymbolPimpl,	return OwningObject->sectionContainsSymbol(SectionPimpl, S.SymbolPimpl,
	Result);	Result);
	}	}

	inline relocation_iterator SectionRef::begin_relocations() const {	inline relocation_iterator SectionRef::begin_relocations() const {
	return OwningObject->getSectionRelBegin(SectionPimpl);	return OwningObject->getSectionRelBegin(SectionPimpl);
	}	}

	inline relocation_iterator SectionRef::end_relocations() const {	inline relocation_iterator SectionRef::end_relocations() const {
	return OwningObject->getSectionRelEnd(SectionPimpl);	return OwningObject->getSectionRelEnd(SectionPimpl);
	}	}


		inline DataRefImpl SectionRef::getRawDataRefImpl() const {
		return SectionPimpl;
		}

	/// RelocationRef	/// RelocationRef
	inline RelocationRef::RelocationRef(DataRefImpl RelocationP,	inline RelocationRef::RelocationRef(DataRefImpl RelocationP,
	const ObjectFile *Owner)	const ObjectFile *Owner)
	: RelocationPimpl(RelocationP)	: RelocationPimpl(RelocationP)
	, OwningObject(Owner) {}	, OwningObject(Owner) {}

	inline bool RelocationRef::operator==(const RelocationRef &Other) const {	inline bool RelocationRef::operator==(const RelocationRef &Other) const {
	return RelocationPimpl == Other.RelocationPimpl;	return RelocationPimpl == Other.RelocationPimpl;
	}	}

	inline error_code RelocationRef::getNext(RelocationRef &Result) const {	inline error_code RelocationRef::getNext(RelocationRef &Result) const {
	return OwningObject->getRelocationNext(RelocationPimpl, Result);	return OwningObject->getRelocationNext(RelocationPimpl, Result);
	}	}

	inline error_code RelocationRef::getAddress(uint64_t &Result) const {	inline error_code RelocationRef::getAddress(uint64_t &Result) const {
	return OwningObject->getRelocationAddress(RelocationPimpl, Result);	return OwningObject->getRelocationAddress(RelocationPimpl, Result);
	}	}


		inline error_code RelocationRef::getOffset(uint64_t &Result) const {
		return OwningObject->getRelocationOffset(RelocationPimpl, Result);
		}

	inline error_code RelocationRef::getSymbol(SymbolRef &Result) const {	inline error_code RelocationRef::getSymbol(SymbolRef &Result) const {
	return OwningObject->getRelocationSymbol(RelocationPimpl, Result);	return OwningObject->getRelocationSymbol(RelocationPimpl, Result);
	}	}


	inline error_code RelocationRef::getType(uint32_t &Result) const {	inline error_code RelocationRef::getType(uint64_t &Result) const {
	return OwningObject->getRelocationType(RelocationPimpl, Result);	return OwningObject->getRelocationType(RelocationPimpl, Result);
	}	}

	inline error_code RelocationRef::getTypeName(SmallVectorImpl<char> &Result)	inline error_code RelocationRef::getTypeName(SmallVectorImpl<char> &Result)
	const {	const {
	return OwningObject->getRelocationTypeName(RelocationPimpl, Result);	return OwningObject->getRelocationTypeName(RelocationPimpl, Result);
	}	}

	inline error_code RelocationRef::getAdditionalInfo(int64_t &Result) const {	inline error_code RelocationRef::getAdditionalInfo(int64_t &Result) const {
	return OwningObject->getRelocationAdditionalInfo(RelocationPimpl, Result) ;	return OwningObject->getRelocationAdditionalInfo(RelocationPimpl, Result) ;
	}	}

	inline error_code RelocationRef::getValueString(SmallVectorImpl<char> &Resu lt)	inline error_code RelocationRef::getValueString(SmallVectorImpl<char> &Resu lt)
	const {	const {
	return OwningObject->getRelocationValueString(RelocationPimpl, Result);	return OwningObject->getRelocationValueString(RelocationPimpl, Result);
	}	}


		inline error_code RelocationRef::getHidden(bool &Result) const {
		return OwningObject->getRelocationHidden(RelocationPimpl, Result);
		}
		// Inline function definitions.
		inline LibraryRef::LibraryRef(DataRefImpl LibraryP, const ObjectFile *Owner
		)
		: LibraryPimpl(LibraryP)
		, OwningObject(Owner) {}

		inline bool LibraryRef::operator==(const LibraryRef &Other) const {
		return LibraryPimpl == Other.LibraryPimpl;
		}

		inline bool LibraryRef::operator <(const LibraryRef &Other) const {
		return LibraryPimpl < Other.LibraryPimpl;
		}

		inline error_code LibraryRef::getNext(LibraryRef &Result) const {
		return OwningObject->getLibraryNext(LibraryPimpl, Result);
		}

		inline error_code LibraryRef::getPath(StringRef &Result) const {
		return OwningObject->getLibraryPath(LibraryPimpl, Result);
		}

	} // end namespace object	} // end namespace object
	} // end namespace llvm	} // end namespace llvm

	#endif	#endif

End of changes. 35 change blocks.
	73 lines changed or deleted	220 lines changed or added

	Operator.h	Operator.h

	skipping to change at line 18	skipping to change at line 18
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	//	//
	// This file defines various classes for working with Instructions and	// This file defines various classes for working with Instructions and
	// ConstantExprs.	// ConstantExprs.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_OPERATOR_H	#ifndef LLVM_OPERATOR_H
	#define LLVM_OPERATOR_H	#define LLVM_OPERATOR_H


	#include "llvm/Instruction.h"
	#include "llvm/Constants.h"	#include "llvm/Constants.h"

		#include "llvm/Instruction.h"
		#include "llvm/Type.h"

	namespace llvm {	namespace llvm {

	class GetElementPtrInst;	class GetElementPtrInst;
	class BinaryOperator;	class BinaryOperator;
	class ConstantExpr;	class ConstantExpr;

	/// Operator - This is a utility class that provides an abstraction for the	/// Operator - This is a utility class that provides an abstraction for the
	/// common functionality between Instructions and ConstantExprs.	/// common functionality between Instructions and ConstantExprs.
	///	///

	skipping to change at line 132	skipping to change at line 133
	};	};

	/// PossiblyExactOperator - A udiv or sdiv instruction, which can be marked as	/// PossiblyExactOperator - A udiv or sdiv instruction, which can be marked as
	/// "exact", indicating that no bits are destroyed.	/// "exact", indicating that no bits are destroyed.
	class PossiblyExactOperator : public Operator {	class PossiblyExactOperator : public Operator {
	public:	public:
	enum {	enum {
	IsExact = (1 << 0)	IsExact = (1 << 0)
	};	};


		private:
		~PossiblyExactOperator(); // do not implement

	friend class BinaryOperator;	friend class BinaryOperator;
	friend class ConstantExpr;	friend class ConstantExpr;
	void setIsExact(bool B) {	void setIsExact(bool B) {
	SubclassOptionalData = (SubclassOptionalData & ~IsExact) \| (B * IsExact );	SubclassOptionalData = (SubclassOptionalData & ~IsExact) \| (B * IsExact );
	}	}


	private:
	~PossiblyExactOperator(); // do not implement
	public:	public:
	/// isExact - Test whether this division is known to be exact, with	/// isExact - Test whether this division is known to be exact, with
	/// zero remainder.	/// zero remainder.
	bool isExact() const {	bool isExact() const {
	return SubclassOptionalData & IsExact;	return SubclassOptionalData & IsExact;
	}	}

	static bool isPossiblyExactOpcode(unsigned OpC) {	static bool isPossiblyExactOpcode(unsigned OpC) {
	return OpC == Instruction::SDiv \|\|	return OpC == Instruction::SDiv \|\|
	OpC == Instruction::UDiv \|\|	OpC == Instruction::UDiv \|\|

	skipping to change at line 165	skipping to change at line 167
	}	}
	static inline bool classof(const Instruction *I) {	static inline bool classof(const Instruction *I) {
	return isPossiblyExactOpcode(I->getOpcode());	return isPossiblyExactOpcode(I->getOpcode());
	}	}
	static inline bool classof(const Value *V) {	static inline bool classof(const Value *V) {
	return (isa<Instruction>(V) && classof(cast<Instruction>(V))) \|\|	return (isa<Instruction>(V) && classof(cast<Instruction>(V))) \|\|
	(isa<ConstantExpr>(V) && classof(cast<ConstantExpr>(V)));	(isa<ConstantExpr>(V) && classof(cast<ConstantExpr>(V)));
	}	}
	};	};


		/// FPMathOperator - Utility class for floating point operations which can
		have
		/// information about relaxed accuracy requirements attached to them.
		class FPMathOperator : public Operator {
		private:
		~FPMathOperator(); // do not implement

		public:

		/// \brief Get the maximum error permitted by this operation in ULPs. An
		/// accuracy of 0.0 means that the operation should be performed with the
		/// default precision.
		float getFPAccuracy() const;

		static inline bool classof(const FPMathOperator *) { return true; }
		static inline bool classof(const Instruction *I) {
		return I->getType()->isFPOrFPVectorTy();
		}
		static inline bool classof(const Value *V) {
		return isa<Instruction>(V) && classof(cast<Instruction>(V));
		}
		};

	/// ConcreteOperator - A helper template for defining operators for individ ual	/// ConcreteOperator - A helper template for defining operators for individ ual
	/// opcodes.	/// opcodes.
	template<typename SuperClass, unsigned Opc>	template<typename SuperClass, unsigned Opc>
	class ConcreteOperator : public SuperClass {	class ConcreteOperator : public SuperClass {
	~ConcreteOperator(); // DO NOT IMPLEMENT	~ConcreteOperator(); // DO NOT IMPLEMENT
	public:	public:
	static inline bool classof(const ConcreteOperator<SuperClass, Opc> *) {	static inline bool classof(const ConcreteOperator<SuperClass, Opc> *) {
	return true;	return true;
	}	}
	static inline bool classof(const Instruction *I) {	static inline bool classof(const Instruction *I) {

	skipping to change at line 259	skipping to change at line 283
	}	}
	const Value *getPointerOperand() const {	const Value *getPointerOperand() const {
	return getOperand(0);	return getOperand(0);
	}	}
	static unsigned getPointerOperandIndex() {	static unsigned getPointerOperandIndex() {
	return 0U; // get index for modifying correct oper and	return 0U; // get index for modifying correct oper and
	}	}

	/// getPointerOperandType - Method to return the pointer operand as a	/// getPointerOperandType - Method to return the pointer operand as a
	/// PointerType.	/// PointerType.

	PointerType *getPointerOperandType() const {	Type *getPointerOperandType() const {
	return reinterpret_cast<PointerType*>(getPointerOperand()->getType());	return getPointerOperand()->getType();
	}	}

	unsigned getNumIndices() const { // Note: always non-negative	unsigned getNumIndices() const { // Note: always non-negative
	return getNumOperands() - 1;	return getNumOperands() - 1;
	}	}

	bool hasIndices() const {	bool hasIndices() const {
	return getNumOperands() > 1;	return getNumOperands() > 1;
	}	}


End of changes. 6 change blocks.
	5 lines changed or deleted	30 lines changed or added

	PHITransAddr.h	PHITransAddr.h

	skipping to change at line 23	skipping to change at line 23

	#ifndef LLVM_ANALYSIS_PHITRANSADDR_H	#ifndef LLVM_ANALYSIS_PHITRANSADDR_H
	#define LLVM_ANALYSIS_PHITRANSADDR_H	#define LLVM_ANALYSIS_PHITRANSADDR_H

	#include "llvm/Instruction.h"	#include "llvm/Instruction.h"
	#include "llvm/ADT/SmallVector.h"	#include "llvm/ADT/SmallVector.h"

	namespace llvm {	namespace llvm {
	class DominatorTree;	class DominatorTree;
	class TargetData;	class TargetData;

		class TargetLibraryInfo;

	/// PHITransAddr - An address value which tracks and handles phi translatio n.	/// PHITransAddr - An address value which tracks and handles phi translatio n.
	/// As we walk "up" the CFG through predecessors, we need to ensure that th e	/// As we walk "up" the CFG through predecessors, we need to ensure that th e
	/// address we're tracking is kept up to date. For example, if we're analy zing	/// address we're tracking is kept up to date. For example, if we're analy zing
	/// an address of "&A[i]" and walk through the definition of 'i' which is a PHI	/// an address of "&A[i]" and walk through the definition of 'i' which is a PHI
	/// node, we must phi translate i to get "&A[j]" or else we will analyze an	/// node, we must phi translate i to get "&A[j]" or else we will analyze an
	/// incorrect pointer in the predecessor block.	/// incorrect pointer in the predecessor block.
	///	///
	/// This is designed to be a relatively small object that lives on the stac k and	/// This is designed to be a relatively small object that lives on the stac k and
	/// is copyable.	/// is copyable.
	///	///
	class PHITransAddr {	class PHITransAddr {
	/// Addr - The actual address we're analyzing.	/// Addr - The actual address we're analyzing.
	Value *Addr;	Value *Addr;

	/// TD - The target data we are playing with if known, otherwise null.	/// TD - The target data we are playing with if known, otherwise null.
	const TargetData *TD;	const TargetData *TD;


		/// TLI - The target library info if known, otherwise null.
		const TargetLibraryInfo *TLI;

	/// InstInputs - The inputs for our symbolic address.	/// InstInputs - The inputs for our symbolic address.
	SmallVector<Instruction*, 4> InstInputs;	SmallVector<Instruction*, 4> InstInputs;
	public:	public:

	PHITransAddr(Value addr, const TargetData td) : Addr(addr), TD(td) {	PHITransAddr(Value addr, const TargetData td) : Addr(addr), TD(td), TLI (0) {
	// If the address is an instruction, the whole thing is considered an i nput.	// If the address is an instruction, the whole thing is considered an i nput.
	if (Instruction *I = dyn_cast<Instruction>(Addr))	if (Instruction *I = dyn_cast<Instruction>(Addr))
	InstInputs.push_back(I);	InstInputs.push_back(I);
	}	}

	Value *getAddr() const { return Addr; }	Value *getAddr() const { return Addr; }

	/// NeedsPHITranslationFromBlock - Return true if moving from the specifi ed	/// NeedsPHITranslationFromBlock - Return true if moving from the specifi ed
	/// BasicBlock to its predecessors requires PHI translation.	/// BasicBlock to its predecessors requires PHI translation.
	bool NeedsPHITranslationFromBlock(BasicBlock *BB) const {	bool NeedsPHITranslationFromBlock(BasicBlock *BB) const {

End of changes. 3 change blocks.
	1 lines changed or deleted	5 lines changed or added

	Parser.h	Parser.h

	skipping to change at line 24	skipping to change at line 24
	#ifndef LLVM_ASSEMBLY_PARSER_H	#ifndef LLVM_ASSEMBLY_PARSER_H
	#define LLVM_ASSEMBLY_PARSER_H	#define LLVM_ASSEMBLY_PARSER_H

	#include <string>	#include <string>

	namespace llvm {	namespace llvm {

	class Module;	class Module;
	class MemoryBuffer;	class MemoryBuffer;
	class SMDiagnostic;	class SMDiagnostic;

	class raw_ostream;
	class LLVMContext;	class LLVMContext;

	/// This function is the main interface to the LLVM Assembly Parser. It par ses	/// This function is the main interface to the LLVM Assembly Parser. It par ses
	/// an ASCII file that (presumably) contains LLVM Assembly code. It returns a	/// an ASCII file that (presumably) contains LLVM Assembly code. It returns a
	/// Module (intermediate representation) with the corresponding features. N ote	/// Module (intermediate representation) with the corresponding features. N ote
	/// that this does not verify that the generated Module is valid, so you sh ould	/// that this does not verify that the generated Module is valid, so you sh ould
	/// run the verifier after parsing the file to check that it is okay.	/// run the verifier after parsing the file to check that it is okay.
	/// @brief Parse LLVM Assembly from a file	/// @brief Parse LLVM Assembly from a file
	Module *ParseAssemblyFile(	Module *ParseAssemblyFile(
	const std::string &Filename, ///< The name of the file to parse	const std::string &Filename, ///< The name of the file to parse

End of changes. 1 change blocks.
	1 lines changed or deleted	0 lines changed or added

	PassAnalysisSupport.h	PassAnalysisSupport.h

	skipping to change at line 22	skipping to change at line 22
	//	//
	// NO .CPP FILES SHOULD INCLUDE THIS FILE DIRECTLY	// NO .CPP FILES SHOULD INCLUDE THIS FILE DIRECTLY
	//	//
	// Instead, #include Pass.h	// Instead, #include Pass.h
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_PASS_ANALYSIS_SUPPORT_H	#ifndef LLVM_PASS_ANALYSIS_SUPPORT_H
	#define LLVM_PASS_ANALYSIS_SUPPORT_H	#define LLVM_PASS_ANALYSIS_SUPPORT_H


		#include "llvm/Pass.h"
	#include "llvm/ADT/SmallVector.h"	#include "llvm/ADT/SmallVector.h"
	#include "llvm/ADT/StringRef.h"	#include "llvm/ADT/StringRef.h"
	#include <vector>	#include <vector>

	namespace llvm {	namespace llvm {

	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	// AnalysisUsage - Represent the analysis usage information of a pass. Thi s	// AnalysisUsage - Represent the analysis usage information of a pass. Thi s
	// tracks analyses that the pass REQUIRES (must be available when the pass	// tracks analyses that the pass REQUIRES (must be available when the pass
	// runs), REQUIRES TRANSITIVE (must be available throughout the lifetime of the	// runs), REQUIRES TRANSITIVE (must be available throughout the lifetime of the

End of changes. 1 change blocks.
	0 lines changed or deleted	1 lines changed or added

	PassManager.h	PassManager.h

	skipping to change at line 62	skipping to change at line 62
	/// the Pass to the PassManager. When the PassManager is destroyed, the pass	/// the Pass to the PassManager. When the PassManager is destroyed, the pass
	/// will be destroyed as well, so there is no need to delete the pass. T his	/// will be destroyed as well, so there is no need to delete the pass. T his
	/// implies that all passes MUST be allocated with 'new'.	/// implies that all passes MUST be allocated with 'new'.
	void add(Pass *P);	void add(Pass *P);

	/// run - Execute all of the passes scheduled for execution. Keep track of	/// run - Execute all of the passes scheduled for execution. Keep track of
	/// whether any of the passes modifies the module, and if so, return true .	/// whether any of the passes modifies the module, and if so, return true .
	bool run(Module &M);	bool run(Module &M);

	private:	private:

	/// addImpl - Add a pass to the queue of passes to run, without
	/// checking whether to add a printer pass.
	void addImpl(Pass *P);

	/// PassManagerImpl_New is the actual class. PassManager is just the	/// PassManagerImpl_New is the actual class. PassManager is just the
	/// wraper to publish simple pass manager interface	/// wraper to publish simple pass manager interface
	PassManagerImpl *PM;	PassManagerImpl *PM;
	};	};

	/// FunctionPassManager manages FunctionPasses and BasicBlockPassManagers.	/// FunctionPassManager manages FunctionPasses and BasicBlockPassManagers.
	class FunctionPassManager : public PassManagerBase {	class FunctionPassManager : public PassManagerBase {
	public:	public:
	/// FunctionPassManager ctor - This initializes the pass manager. It nee ds,	/// FunctionPassManager ctor - This initializes the pass manager. It nee ds,
	/// but does not take ownership of, the specified Module.	/// but does not take ownership of, the specified Module.
	explicit FunctionPassManager(Module *M);	explicit FunctionPassManager(Module *M);
	~FunctionPassManager();	~FunctionPassManager();

	/// add - Add a pass to the queue of passes to run. This passes	/// add - Add a pass to the queue of passes to run. This passes
	/// ownership of the Pass to the PassManager. When the	/// ownership of the Pass to the PassManager. When the
	/// PassManager_X is destroyed, the pass will be destroyed as well, so	/// PassManager_X is destroyed, the pass will be destroyed as well, so

	/// there is no need to delete the pass. (TODO delete passes.)	/// there is no need to delete the pass.
	/// This implies that all passes MUST be allocated with 'new'.	/// This implies that all passes MUST be allocated with 'new'.
	void add(Pass *P);	void add(Pass *P);

	/// run - Execute all of the passes scheduled for execution. Keep	/// run - Execute all of the passes scheduled for execution. Keep
	/// track of whether any of the passes modifies the function, and if	/// track of whether any of the passes modifies the function, and if
	/// so, return true.	/// so, return true.
	///	///
	bool run(Function &F);	bool run(Function &F);

	/// doInitialization - Run all of the initializers for the function passe s.	/// doInitialization - Run all of the initializers for the function passe s.
	///	///
	bool doInitialization();	bool doInitialization();

	/// doFinalization - Run all of the finalizers for the function passes.	/// doFinalization - Run all of the finalizers for the function passes.
	///	///
	bool doFinalization();	bool doFinalization();

	private:	private:

	/// addImpl - Add a pass to the queue of passes to run, without
	/// checking whether to add a printer pass.
	void addImpl(Pass *P);

	FunctionPassManagerImpl *FPM;	FunctionPassManagerImpl *FPM;
	Module *M;	Module *M;
	};	};

	} // End llvm namespace	} // End llvm namespace

	#endif	#endif

End of changes. 3 change blocks.
	9 lines changed or deleted	1 lines changed or added

	PassManagerBuilder.h	PassManagerBuilder.h

	skipping to change at line 26	skipping to change at line 26

	#include "llvm-c/Core.h"	#include "llvm-c/Core.h"

	typedef struct LLVMOpaquePassManagerBuilder *LLVMPassManagerBuilderRef;	typedef struct LLVMOpaquePassManagerBuilder *LLVMPassManagerBuilderRef;

	#ifdef __cplusplus	#ifdef __cplusplus
	#include "llvm/Transforms/IPO/PassManagerBuilder.h"	#include "llvm/Transforms/IPO/PassManagerBuilder.h"
	extern "C" {	extern "C" {
	#endif	#endif


		/**
		* @defgroup LLVMCTransformsPassManagerBuilder Pass manager builder
		* @ingroup LLVMCTransforms
		*
		* @{
		*/

	/** See llvm::PassManagerBuilder. */	/** See llvm::PassManagerBuilder. */
	LLVMPassManagerBuilderRef LLVMPassManagerBuilderCreate(void);	LLVMPassManagerBuilderRef LLVMPassManagerBuilderCreate(void);
	void LLVMPassManagerBuilderDispose(LLVMPassManagerBuilderRef PMB);	void LLVMPassManagerBuilderDispose(LLVMPassManagerBuilderRef PMB);

	/** See llvm::PassManagerBuilder::OptLevel. */	/** See llvm::PassManagerBuilder::OptLevel. */
	void	void
	LLVMPassManagerBuilderSetOptLevel(LLVMPassManagerBuilderRef PMB,	LLVMPassManagerBuilderSetOptLevel(LLVMPassManagerBuilderRef PMB,
	unsigned OptLevel);	unsigned OptLevel);

	/** See llvm::PassManagerBuilder::SizeLevel. */	/** See llvm::PassManagerBuilder::SizeLevel. */

	skipping to change at line 76	skipping to change at line 83
	void	void
	LLVMPassManagerBuilderPopulateModulePassManager(LLVMPassManagerBuilderRef P MB,	LLVMPassManagerBuilderPopulateModulePassManager(LLVMPassManagerBuilderRef P MB,
	LLVMPassManagerRef PM);	LLVMPassManagerRef PM);

	/** See llvm::PassManagerBuilder::populateLTOPassManager. */	/** See llvm::PassManagerBuilder::populateLTOPassManager. */
	void LLVMPassManagerBuilderPopulateLTOPassManager(LLVMPassManagerBuilderRef PMB,	void LLVMPassManagerBuilderPopulateLTOPassManager(LLVMPassManagerBuilderRef PMB,
	LLVMPassManagerRef PM,	LLVMPassManagerRef PM,
	bool Internalize,	bool Internalize,
	bool RunInliner);	bool RunInliner);


		/**
		* @}
		*/

	#ifdef __cplusplus	#ifdef __cplusplus
	}	}

	namespace llvm {	namespace llvm {
	inline PassManagerBuilder *unwrap(LLVMPassManagerBuilderRef P) {	inline PassManagerBuilder *unwrap(LLVMPassManagerBuilderRef P) {
	return reinterpret_cast<PassManagerBuilder*>(P);	return reinterpret_cast<PassManagerBuilder*>(P);
	}	}

	inline LLVMPassManagerBuilderRef wrap(PassManagerBuilder *P) {	inline LLVMPassManagerBuilderRef wrap(PassManagerBuilder *P) {
	return reinterpret_cast<LLVMPassManagerBuilderRef>(P);	return reinterpret_cast<LLVMPassManagerBuilderRef>(P);

End of changes. 2 change blocks.
	0 lines changed or deleted	11 lines changed or added

	PassManagers.h	PassManagers.h

	skipping to change at line 85	skipping to change at line 85
	// [o] class MPPassManager : public Pass, public PMDataManager;	// [o] class MPPassManager : public Pass, public PMDataManager;
	//	//
	// MPPassManager manages ModulePasses and FPPassManagers	// MPPassManager manages ModulePasses and FPPassManagers
	//	//
	// [o] class PassManager;	// [o] class PassManager;
	//	//
	// This is a external interface used by various tools to manages passes. It	// This is a external interface used by various tools to manages passes. It
	// relies on PassManagerImpl to do all the tasks.	// relies on PassManagerImpl to do all the tasks.
	//	//
	// [o] class PassManagerImpl : public Pass, public PMDataManager,	// [o] class PassManagerImpl : public Pass, public PMDataManager,

	// public PMDTopLevelManager	// public PMTopLevelManager
	//	//
	// PassManagerImpl is a top level pass manager responsible for managing	// PassManagerImpl is a top level pass manager responsible for managing
	// MPPassManagers.	// MPPassManagers.
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#include "llvm/Support/PrettyStackTrace.h"	#include "llvm/Support/PrettyStackTrace.h"

	namespace llvm {	namespace llvm {
	class Module;	class Module;
	class Pass;	class Pass;

	skipping to change at line 175	skipping to change at line 175
	protected:	protected:
	explicit PMTopLevelManager(PMDataManager *PMDM);	explicit PMTopLevelManager(PMDataManager *PMDM);

	virtual unsigned getNumContainedManagers() const {	virtual unsigned getNumContainedManagers() const {
	return (unsigned)PassManagers.size();	return (unsigned)PassManagers.size();
	}	}

	void initializeAllAnalysisInfo();	void initializeAllAnalysisInfo();

	private:	private:

	/// This is implemented by top level pass manager and used by	virtual PMDataManager *getAsPMDataManager() = 0;
	/// schedulePass() to add analysis info passes that are not available.	virtual PassManagerType getTopLevelPassManagerType() = 0;
	virtual void addTopLevelPass(Pass *P) = 0;

	public:	public:
	/// Schedule pass P for execution. Make sure that passes required by	/// Schedule pass P for execution. Make sure that passes required by
	/// P are run before P is run. Update analysis info maintained by	/// P are run before P is run. Update analysis info maintained by
	/// the manager. Remove dead passes. This is a recursive function.	/// the manager. Remove dead passes. This is a recursive function.
	void schedulePass(Pass *P);	void schedulePass(Pass *P);

	/// Set pass P as the last user of the given analysis passes.	/// Set pass P as the last user of the given analysis passes.
	void setLastUser(const SmallVectorImpl<Pass > &AnalysisPasses, Pass P);	void setLastUser(const SmallVectorImpl<Pass > &AnalysisPasses, Pass P);


End of changes. 2 change blocks.
	4 lines changed or deleted	3 lines changed or added

	PassSupport.h	PassSupport.h

	skipping to change at line 28	skipping to change at line 28
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_PASS_SUPPORT_H	#ifndef LLVM_PASS_SUPPORT_H
	#define LLVM_PASS_SUPPORT_H	#define LLVM_PASS_SUPPORT_H

	#include "Pass.h"	#include "Pass.h"
	#include "llvm/PassRegistry.h"	#include "llvm/PassRegistry.h"
	#include "llvm/InitializePasses.h"	#include "llvm/InitializePasses.h"
	#include "llvm/Support/Atomic.h"	#include "llvm/Support/Atomic.h"

		#include "llvm/Support/Valgrind.h"
	#include <vector>	#include <vector>

	namespace llvm {	namespace llvm {

	//===---------------------------------------------------------------------- -----	//===---------------------------------------------------------------------- -----
	/// PassInfo class - An instance of this class exists for every pass known by	/// PassInfo class - An instance of this class exists for every pass known by
	/// the system, and can be obtained from a live Pass by calling its	/// the system, and can be obtained from a live Pass by calling its
	/// getPassInfo() method. These objects are set up by the RegisterPass<>	/// getPassInfo() method. These objects are set up by the RegisterPass<>
	/// template, defined below.	/// template, defined below.
	///	///

	skipping to change at line 138	skipping to change at line 139
	void operator=(const PassInfo &); // do not implement	void operator=(const PassInfo &); // do not implement
	PassInfo(const PassInfo &); // do not implement	PassInfo(const PassInfo &); // do not implement
	};	};

	#define CALL_ONCE_INITIALIZATION(function) \	#define CALL_ONCE_INITIALIZATION(function) \
	static volatile sys::cas_flag initialized = 0; \	static volatile sys::cas_flag initialized = 0; \
	sys::cas_flag old_val = sys::CompareAndSwap(&initialized, 1, 0); \	sys::cas_flag old_val = sys::CompareAndSwap(&initialized, 1, 0); \
	if (old_val == 0) { \	if (old_val == 0) { \
	function(Registry); \	function(Registry); \
	sys::MemoryFence(); \	sys::MemoryFence(); \

		TsanIgnoreWritesBegin(); \
		TsanHappensBefore(&initialized); \
	initialized = 2; \	initialized = 2; \

		TsanIgnoreWritesEnd(); \
	} else { \	} else { \
	sys::cas_flag tmp = initialized; \	sys::cas_flag tmp = initialized; \
	sys::MemoryFence(); \	sys::MemoryFence(); \
	while (tmp != 2) { \	while (tmp != 2) { \
	tmp = initialized; \	tmp = initialized; \
	sys::MemoryFence(); \	sys::MemoryFence(); \
	} \	} \

	}	} \
		TsanHappensAfter(&initialized);

	#define INITIALIZE_PASS(passName, arg, name, cfg, analysis) \	#define INITIALIZE_PASS(passName, arg, name, cfg, analysis) \
	static void* initialize##passName##PassOnce(PassRegistry &Registry) { \	static void* initialize##passName##PassOnce(PassRegistry &Registry) { \
	PassInfo *PI = new PassInfo(name, arg, & passName ::ID, \	PassInfo *PI = new PassInfo(name, arg, & passName ::ID, \
	PassInfo::NormalCtor_t(callDefaultCtor< passName >), cfg, analysis); \	PassInfo::NormalCtor_t(callDefaultCtor< passName >), cfg, analysis); \
	Registry.registerPass(*PI, true); \	Registry.registerPass(*PI, true); \
	return PI; \	return PI; \
	} \	} \
	void llvm::initialize##passName##Pass(PassRegistry &Registry) { \	void llvm::initialize##passName##Pass(PassRegistry &Registry) { \
	CALL_ONCE_INITIALIZATION(initialize##passName##PassOnce) \	CALL_ONCE_INITIALIZATION(initialize##passName##PassOnce) \

End of changes. 4 change blocks.
	1 lines changed or deleted	6 lines changed or added

	Passes.h	Passes.h

	skipping to change at line 18	skipping to change at line 18
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	//	//
	// This file defines interfaces to access the target independent code gener ation	// This file defines interfaces to access the target independent code gener ation
	// passes provided by the LLVM backend.	// passes provided by the LLVM backend.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_CODEGEN_PASSES_H	#ifndef LLVM_CODEGEN_PASSES_H
	#define LLVM_CODEGEN_PASSES_H	#define LLVM_CODEGEN_PASSES_H


		#include "llvm/Pass.h"
	#include "llvm/Target/TargetMachine.h"	#include "llvm/Target/TargetMachine.h"
	#include <string>	#include <string>

	namespace llvm {	namespace llvm {

	class FunctionPass;	class FunctionPass;
	class MachineFunctionPass;	class MachineFunctionPass;
	class PassInfo;	class PassInfo;
	class TargetLowering;	class TargetLowering;
	class TargetRegisterClass;	class TargetRegisterClass;
	class raw_ostream;	class raw_ostream;

		}


		namespace llvm {

		extern char &NoPassID; // Allow targets to choose not to run a pass.

		class PassConfigImpl;

		/// Target-Independent Code Generator Pass Configuration Options.
		///
		/// This is an ImmutablePass solely for the purpose of exposing CodeGen opt
		ions
		/// to the internals of other CodeGen passes.
		class TargetPassConfig : public ImmutablePass {
		public:
		/// Pseudo Pass IDs. These are defined within TargetPassConfig because th
		ey
		/// are unregistered pass IDs. They are only useful for use with
		/// TargetPassConfig APIs to identify multiple occurrences of the same pa
		ss.
		///

		/// EarlyTailDuplicate - A clone of the TailDuplicate pass that runs earl
		y
		/// during codegen, on SSA form.
		static char EarlyTailDuplicateID;

		/// PostRAMachineLICM - A clone of the LICM pass that runs during late ma
		chine
		/// optimization after regalloc.
		static char PostRAMachineLICMID;

		protected:
		TargetMachine *TM;
		PassManagerBase *PM;
		PassConfigImpl *Impl; // Internal data structures
		bool Initialized; // Flagged after all passes are configured.

		// Target Pass Options
		// Targets provide a default setting, user flags override.
		//
		bool DisableVerify;

		/// Default setting for -enable-tail-merge on this target.
		bool EnableTailMerge;

		public:
		TargetPassConfig(TargetMachine *tm, PassManagerBase &pm);
		// Dummy constructor.
		TargetPassConfig();

		virtual ~TargetPassConfig();

		static char ID;

		/// Get the right type of TargetMachine for this target.
		template<typename TMC> TMC &getTM() const {
		return static_cast<TMC>(TM);
		}

		const TargetLowering *getTargetLowering() const {
		return TM->getTargetLowering();
		}

		//
		void setInitialized() { Initialized = true; }

		CodeGenOpt::Level getOptLevel() const { return TM->getOptLevel(); }

		void setDisableVerify(bool Disable) { setOpt(DisableVerify, Disable); }

		bool getEnableTailMerge() const { return EnableTailMerge; }
		void setEnableTailMerge(bool Enable) { setOpt(EnableTailMerge, Enable); }

		/// Allow the target to override a specific pass without overriding the p
		ass
		/// pipeline. When passes are added to the standard pipeline at the
		/// point where StadardID is expected, add TargetID in its place.
		void substitutePass(char &StandardID, char &TargetID);

		/// Allow the target to enable a specific standard pass by default.
		void enablePass(char &ID) { substitutePass(ID, ID); }

		/// Allow the target to disable a specific standard pass by default.
		void disablePass(char &ID) { substitutePass(ID, NoPassID); }

		/// Return the pass ssubtituted for StandardID by the target.
		/// If no substitution exists, return StandardID.
		AnalysisID getPassSubstitution(AnalysisID StandardID) const;

		/// Return true if the optimized regalloc pipeline is enabled.
		bool getOptimizeRegAlloc() const;

		/// Add common target configurable passes that perform LLVM IR to IR
		/// transforms following machine independent optimization.
		virtual void addIRPasses();

		/// Add common passes that perform LLVM IR to IR transforms in preparatio
		n for
		/// instruction selection.
		virtual void addISelPrepare();

		/// addInstSelector - This method should install an instruction selector
		pass,
		/// which converts from LLVM code to machine instructions.
		virtual bool addInstSelector() {
		return true;
		}

		/// Add the complete, standard set of LLVM CodeGen passes.
		/// Fully developed targets will not generally override this.
		virtual void addMachinePasses();

		protected:
		// Helper to verify the analysis is really immutable.
		void setOpt(bool &Opt, bool Val);

		/// Methods with trivial inline returns are convenient points in the comm
		on
		/// codegen pass pipeline where targets may insert passes. Methods with
		/// out-of-line standard implementations are major CodeGen stages called
		by
		/// addMachinePasses. Some targets may override major stages when inserti
		ng
		/// passes is insufficient, but maintaining overriden stages is more work
		.
		///

		/// addPreISelPasses - This method should add any "last minute" LLVM->LLV
		M
		/// passes (which are run just before instruction selector).
		virtual bool addPreISel() {
		return true;
		}

		/// addMachineSSAOptimization - Add standard passes that optimize machine
		/// instructions in SSA form.
		virtual void addMachineSSAOptimization();

		/// addPreRegAlloc - This method may be implemented by targets that want
		to
		/// run passes immediately before register allocation. This should return
		/// true if -print-machineinstrs should print after these passes.
		virtual bool addPreRegAlloc() {
		return false;
		}

		/// createTargetRegisterAllocator - Create the register allocator pass fo
		r
		/// this target at the current optimization level.
		virtual FunctionPass *createTargetRegisterAllocator(bool Optimized);

		/// addFastRegAlloc - Add the minimum set of target-independent passes th
		at
		/// are required for fast register allocation.
		virtual void addFastRegAlloc(FunctionPass *RegAllocPass);

		/// addOptimizedRegAlloc - Add passes related to register allocation.
		/// LLVMTargetMachine provides standard regalloc passes for most targets.
		virtual void addOptimizedRegAlloc(FunctionPass *RegAllocPass);

		/// addFinalizeRegAlloc - This method may be implemented by targets that
		want
		/// to run passes within the regalloc pipeline, immediately after the reg
		ister
		/// allocation pass itself. These passes run as soon as virtual regisiter
		s
		/// have been rewritten to physical registers but before and other postRA
		/// optimization happens. Targets that have marked instructions for bundl
		ing
		/// must have finalized those bundles by the time these passes have run,
		/// because subsequent passes are not guaranteed to be bundle-aware.
		virtual bool addFinalizeRegAlloc() {
		return false;
		}

		/// addPostRegAlloc - This method may be implemented by targets that want
		to
		/// run passes after register allocation pass pipeline but before
		/// prolog-epilog insertion. This should return true if -print-machinein
		strs
		/// should print after these passes.
		virtual bool addPostRegAlloc() {
		return false;
		}

		/// Add passes that optimize machine instructions after register allocati
		on.
		virtual void addMachineLateOptimization();

		/// addPreSched2 - This method may be implemented by targets that want to
		/// run passes after prolog-epilog insertion and before the second instru
		ction
		/// scheduling pass. This should return true if -print-machineinstrs sho
		uld
		/// print after these passes.
		virtual bool addPreSched2() {
		return false;
		}

		/// Add standard basic block placement passes.
		virtual void addBlockPlacement();

		/// addPreEmitPass - This pass may be implemented by targets that want to
		run
		/// passes immediately before machine code is emitted. This should retur
		n
		/// true if -print-machineinstrs should print out the code after the pass
		es.
		virtual bool addPreEmitPass() {
		return false;
		}

		/// Utilities for targets to add passes to the pass manager.
		///

		/// Add a CodeGen pass at this point in the pipeline after checking overr
		ides.
		/// Return the pass that was added, or NoPassID.
		AnalysisID addPass(char &ID);

		/// addMachinePasses helper to create the target-selected or overriden
		/// regalloc pass.
		FunctionPass *createRegAllocPass(bool Optimized);

		/// printAndVerify - Add a pass to dump then verify the machine function,
		if
		/// those steps are enabled.
		///
		void printAndVerify(const char *Banner) const;
		};
		} // namespace llvm

		/// List of target independent CodeGen pass IDs.
		namespace llvm {
	/// createUnreachableBlockEliminationPass - The LLVM code generator does not	/// createUnreachableBlockEliminationPass - The LLVM code generator does not
	/// work well with unreachable basic blocks (what live ranges make sense for a	/// work well with unreachable basic blocks (what live ranges make sense for a
	/// block that cannot be reached?). As such, a code generator should eit her	/// block that cannot be reached?). As such, a code generator should eit her
	/// not instruction select unreachable blocks, or run this pass as its	/// not instruction select unreachable blocks, or run this pass as its
	/// last LLVM modifying pass to clean up blocks that are not reachable fr om	/// last LLVM modifying pass to clean up blocks that are not reachable fr om
	/// the entry block.	/// the entry block.
	FunctionPass *createUnreachableBlockEliminationPass();	FunctionPass *createUnreachableBlockEliminationPass();

	/// MachineFunctionPrinter pass - This pass prints out the machine functi on to	/// MachineFunctionPrinter pass - This pass prints out the machine functi on to
	/// the given stream as a debugging tool.	/// the given stream as a debugging tool.
	MachineFunctionPass *	MachineFunctionPass *
	createMachineFunctionPrinterPass(raw_ostream &OS,	createMachineFunctionPrinterPass(raw_ostream &OS,
	const std::string &Banner ="");	const std::string &Banner ="");


	/// MachineLoopInfo pass - This pass is a loop analysis pass.	/// MachineLoopInfo - This pass is a loop analysis pass.
	///
	extern char &MachineLoopInfoID;	extern char &MachineLoopInfoID;


	/// MachineLoopRanges pass - This pass is an on-demand loop coverage	/// MachineLoopRanges - This pass is an on-demand loop coverage analysis.
	/// analysis pass.
	///
	extern char &MachineLoopRangesID;	extern char &MachineLoopRangesID;


	/// MachineDominators pass - This pass is a machine dominators analysis p	/// MachineDominators - This pass is a machine dominators analysis pass.
	ass.
	///
	extern char &MachineDominatorsID;	extern char &MachineDominatorsID;

	/// EdgeBundles analysis - Bundle machine CFG edges.	/// EdgeBundles analysis - Bundle machine CFG edges.

	///
	extern char &EdgeBundlesID;	extern char &EdgeBundlesID;


	/// PHIElimination pass - This pass eliminates machine instruction PHI no	/// LiveVariables pass - This pass computes the set of blocks in which ea
	des	ch
		/// variable is life and sets machine operand kill flags.
		extern char &LiveVariablesID;

		/// PHIElimination - This pass eliminates machine instruction PHI nodes
	/// by inserting copy instructions. This destroys SSA information, but i s the	/// by inserting copy instructions. This destroys SSA information, but i s the
	/// desired input for some register allocators. This pass is "required" by	/// desired input for some register allocators. This pass is "required" by
	/// these register allocator like this: AU.addRequiredID(PHIEliminationID );	/// these register allocator like this: AU.addRequiredID(PHIEliminationID );

	///
	extern char &PHIEliminationID;	extern char &PHIEliminationID;


	/// StrongPHIElimination pass - This pass eliminates machine instruction PHI	/// StrongPHIElimination - This pass eliminates machine instruction PHI
	/// nodes by inserting copy instructions. This destroys SSA information, but	/// nodes by inserting copy instructions. This destroys SSA information, but
	/// is the desired input for some register allocators. This pass is	/// is the desired input for some register allocators. This pass is
	/// "required" by these register allocator like this:	/// "required" by these register allocator like this:
	/// AU.addRequiredID(PHIEliminationID);	/// AU.addRequiredID(PHIEliminationID);
	/// This pass is still in development	/// This pass is still in development
	extern char &StrongPHIEliminationID;	extern char &StrongPHIEliminationID;

	/// LiveStacks pass. An analysis keeping track of the liveness of stack s lots.	/// LiveStacks pass. An analysis keeping track of the liveness of stack s lots.
	extern char &LiveStacksID;	extern char &LiveStacksID;


	/// TwoAddressInstruction pass - This pass reduces two-address instructio ns to	/// TwoAddressInstruction - This pass reduces two-address instructions to
	/// use two operands. This destroys SSA information but it is desired by	/// use two operands. This destroys SSA information but it is desired by
	/// register allocators.	/// register allocators.
	extern char &TwoAddressInstructionPassID;	extern char &TwoAddressInstructionPassID;


	/// RegisteCoalescer pass - This pass merges live ranges to eliminate cop	/// ProcessImpicitDefs pass - This pass removes IMPLICIT_DEFs.
	ies.	extern char &ProcessImplicitDefsID;
	extern char &RegisterCoalescerPassID;
		/// RegisterCoalescer - This pass merges live ranges to eliminate copies.
		extern char &RegisterCoalescerID;

		/// MachineScheduler - This pass schedules machine instructions.
		extern char &MachineSchedulerID;

	/// SpillPlacement analysis. Suggest optimal placement of spill code betw een	/// SpillPlacement analysis. Suggest optimal placement of spill code betw een
	/// basic blocks.	/// basic blocks.

	///
	extern char &SpillPlacementID;	extern char &SpillPlacementID;


	/// UnreachableMachineBlockElimination pass - This pass removes unreachab le	/// UnreachableMachineBlockElimination - This pass removes unreachable
	/// machine basic blocks.	/// machine basic blocks.
	extern char &UnreachableMachineBlockElimID;	extern char &UnreachableMachineBlockElimID;


	/// DeadMachineInstructionElim pass - This pass removes dead machine	/// DeadMachineInstructionElim - This pass removes dead machine instructi
	/// instructions.	ons.
	///	extern char &DeadMachineInstructionElimID;
	FunctionPass *createDeadMachineInstructionElimPass();

	/// Creates a register allocator as the user specified on the command lin
	e, or
	/// picks one that matches OptLevel.
	///
	FunctionPass *createRegisterAllocator(CodeGenOpt::Level OptLevel);

	/// FastRegisterAllocation Pass - This pass register allocates as fast as	/// FastRegisterAllocation Pass - This pass register allocates as fast as
	/// possible. It is best suited for debug code where live ranges are shor t.	/// possible. It is best suited for debug code where live ranges are shor t.
	///	///
	FunctionPass *createFastRegisterAllocator();	FunctionPass *createFastRegisterAllocator();

	/// BasicRegisterAllocation Pass - This pass implements a degenerate glob al	/// BasicRegisterAllocation Pass - This pass implements a degenerate glob al
	/// register allocator using the basic regalloc framework.	/// register allocator using the basic regalloc framework.
	///	///
	FunctionPass *createBasicRegisterAllocator();	FunctionPass *createBasicRegisterAllocator();

	/// Greedy register allocation pass - This pass implements a global regis ter	/// Greedy register allocation pass - This pass implements a global regis ter
	/// allocator for optimized builds.	/// allocator for optimized builds.
	///	///
	FunctionPass *createGreedyRegisterAllocator();	FunctionPass *createGreedyRegisterAllocator();


	/// LinearScanRegisterAllocation Pass - This pass implements the linear s
	can
	/// register allocation algorithm, a global register allocator.
	///
	FunctionPass *createLinearScanRegisterAllocator();

	/// PBQPRegisterAllocation Pass - This pass implements the Partitioned Bo olean	/// PBQPRegisterAllocation Pass - This pass implements the Partitioned Bo olean
	/// Quadratic Prograaming (PBQP) based register allocator.	/// Quadratic Prograaming (PBQP) based register allocator.
	///	///
	FunctionPass *createDefaultPBQPRegisterAllocator();	FunctionPass *createDefaultPBQPRegisterAllocator();


	/// PrologEpilogCodeInserter Pass - This pass inserts prolog and epilog c ode,	/// PrologEpilogCodeInserter - This pass inserts prolog and epilog code,
	/// and eliminates abstract frame references.	/// and eliminates abstract frame references.

	///	extern char &PrologEpilogCodeInserterID;
	FunctionPass *createPrologEpilogCodeInserter();


	/// ExpandPostRAPseudos Pass - This pass expands pseudo instructions afte r	/// ExpandPostRAPseudos - This pass expands pseudo instructions after
	/// register allocation.	/// register allocation.

	///	extern char &ExpandPostRAPseudosID;
	FunctionPass *createExpandPostRAPseudosPass();

	/// createPostRAScheduler - This pass performs post register allocation	/// createPostRAScheduler - This pass performs post register allocation
	/// scheduling.	/// scheduling.

	FunctionPass *createPostRAScheduler(CodeGenOpt::Level OptLevel);	extern char &PostRASchedulerID;


	/// BranchFolding Pass - This pass performs machine code CFG based	/// BranchFolding - This pass performs machine code CFG based
	/// optimizations to delete branches to branches, eliminate branches to	/// optimizations to delete branches to branches, eliminate branches to
	/// successor blocks (creating fall throughs), and eliminating branches o ver	/// successor blocks (creating fall throughs), and eliminating branches o ver
	/// branches.	/// branches.

	FunctionPass *createBranchFoldingPass(bool DefaultEnableTailMerge);	extern char &BranchFolderPassID;


	/// TailDuplicate Pass - Duplicate blocks with unconditional branches	/// TailDuplicate - Duplicate blocks with unconditional branches
	/// into tails of their predecessors.	/// into tails of their predecessors.

	FunctionPass *createTailDuplicatePass(bool PreRegAlloc = false);	extern char &TailDuplicateID;

		/// IfConverter - This pass performs machine code if conversion.
		extern char &IfConverterID;


	/// IfConverter Pass - This pass performs machine code if conversion.	/// MachineBlockPlacement - This pass places basic blocks based on branch
	FunctionPass *createIfConverterPass();	/// probabilities.
		extern char &MachineBlockPlacementID;


	/// Code Placement Pass - This pass optimize code placement and aligns lo	/// MachineBlockPlacementStats - This pass collects statistics about the
	op	/// basic block placement using branch probabilities and block frequency
		/// information.
		extern char &MachineBlockPlacementStatsID;

		/// Code Placement - This pass optimize code placement and aligns loop
	/// headers to target specific alignment boundary.	/// headers to target specific alignment boundary.

	FunctionPass *createCodePlacementOptPass();	extern char &CodePlacementOptID;


	/// IntrinsicLowering Pass - Performs target-independent LLVM IR	/// GCLowering Pass - Performs target-independent LLVM IR transformations
	/// transformations for highly portable strategies.	for
		/// highly portable strategies.
		///
	FunctionPass *createGCLoweringPass();	FunctionPass *createGCLoweringPass();


	/// MachineCodeAnalysis Pass - Target-independent pass to mark safe point	/// GCMachineCodeAnalysis - Target-independent pass to mark safe points
	s in	/// in machine code. Must be added very late during code generation, just
	/// machine code. Must be added very late during code generation, just pr	/// prior to output, and importantly after all CFG transformations (such
	ior	as
	/// to output, and importantly after all CFG transformations (such as bra	/// branch folding).
	nch	extern char &GCMachineCodeAnalysisID;
	/// folding).
	FunctionPass *createGCMachineCodeAnalysisPass();

	/// Deleter Pass - Releases GC metadata.	/// Deleter Pass - Releases GC metadata.
	///	///
	FunctionPass *createGCInfoDeleter();	FunctionPass *createGCInfoDeleter();

	/// Creates a pass to print GC metadata.	/// Creates a pass to print GC metadata.
	///	///
	FunctionPass *createGCInfoPrinter(raw_ostream &OS);	FunctionPass *createGCInfoPrinter(raw_ostream &OS);


	/// createMachineCSEPass - This pass performs global CSE on machine	/// MachineCSE - This pass performs global CSE on machine instructions.
	/// instructions.	extern char &MachineCSEID;
	FunctionPass *createMachineCSEPass();


	/// createMachineLICMPass - This pass performs LICM on machine instructio	/// MachineLICM - This pass performs LICM on machine instructions.
	ns.	extern char &MachineLICMID;
	///
	FunctionPass *createMachineLICMPass(bool PreRegAlloc = true);	/// MachineSinking - This pass performs sinking on machine instructions.
		extern char &MachineSinkingID;


	/// createMachineSinkingPass - This pass performs sinking on machine	/// MachineCopyPropagation - This pass performs copy propagation on
	/// instructions.	/// machine instructions.
	FunctionPass *createMachineSinkingPass();	extern char &MachineCopyPropagationID;


	/// createPeepholeOptimizerPass - This pass performs peephole optimizatio ns -	/// PeepholeOptimizer - This pass performs peephole optimizations -
	/// like extension and comparison eliminations.	/// like extension and comparison eliminations.

	FunctionPass *createPeepholeOptimizerPass();	extern char &PeepholeOptimizerID;


	/// createOptimizePHIsPass - This pass optimizes machine instruction PHIs	/// OptimizePHIs - This pass optimizes machine instruction PHIs
	/// to take advantage of opportunities created during DAG legalization.	/// to take advantage of opportunities created during DAG legalization.

	FunctionPass *createOptimizePHIsPass();	extern char &OptimizePHIsID;


	/// createStackSlotColoringPass - This pass performs stack slot coloring.	/// StackSlotColoring - This pass performs stack slot coloring.
	FunctionPass *createStackSlotColoringPass(bool);	extern char &StackSlotColoringID;

	/// createStackProtectorPass - This pass adds stack protectors to functio ns.	/// createStackProtectorPass - This pass adds stack protectors to functio ns.

		///
	FunctionPass createStackProtectorPass(const TargetLowering tli);	FunctionPass createStackProtectorPass(const TargetLowering tli);

	/// createMachineVerifierPass - This pass verifies cenerated machine code	/// createMachineVerifierPass - This pass verifies cenerated machine code
	/// instructions for correctness.	/// instructions for correctness.

		///
	FunctionPass createMachineVerifierPass(const char Banner = 0);	FunctionPass createMachineVerifierPass(const char Banner = 0);

	/// createDwarfEHPass - This pass mulches exception handling code into a form	/// createDwarfEHPass - This pass mulches exception handling code into a form
	/// adapted to code generation. Required if using dwarf exception handli ng.	/// adapted to code generation. Required if using dwarf exception handli ng.
	FunctionPass createDwarfEHPass(const TargetMachine tm);	FunctionPass createDwarfEHPass(const TargetMachine tm);


	/// createSjLjEHPass - This pass adapts exception handling code to use	/// createSjLjEHPreparePass - This pass adapts exception handling code to use
	/// the GCC-style builtin setjmp/longjmp (sjlj) to handling EH control fl ow.	/// the GCC-style builtin setjmp/longjmp (sjlj) to handling EH control fl ow.

	FunctionPass createSjLjEHPass(const TargetLowering tli);	///
		FunctionPass createSjLjEHPreparePass(const TargetLowering tli);


	/// createLocalStackSlotAllocationPass - This pass assigns local frame	/// LocalStackSlotAllocation - This pass assigns local frame indices to s
	/// indices to stack slots relative to one another and allocates	tack
	/// base registers to access them when it is estimated by the target to	/// slots relative to one another and allocates base registers to access
	/// be out of range of normal frame pointer or stack pointer index	them
	/// addressing.	/// when it is estimated by the target to be out of range of normal frame
	FunctionPass *createLocalStackSlotAllocationPass();	/// pointer or stack pointer index addressing.
		extern char &LocalStackSlotAllocationID;


	/// createExpandISelPseudosPass - This pass expands pseudo-instructions.	/// ExpandISelPseudos - This pass expands pseudo-instructions.
	///	extern char &ExpandISelPseudosID;
	FunctionPass *createExpandISelPseudosPass();

	/// createExecutionDependencyFixPass - This pass fixes execution time	/// createExecutionDependencyFixPass - This pass fixes execution time
	/// problems with dependent instructions, such as switching execution	/// problems with dependent instructions, such as switching execution
	/// domains to match.	/// domains to match.
	///	///
	/// The pass will examine instructions using and defining registers in RC .	/// The pass will examine instructions using and defining registers in RC .
	///	///
	FunctionPass createExecutionDependencyFixPass(const TargetRegisterClass RC);	FunctionPass createExecutionDependencyFixPass(const TargetRegisterClass RC);


		/// UnpackMachineBundles - This pass unpack machine instruction bundles.
		extern char &UnpackMachineBundlesID;

		/// FinalizeMachineBundles - This pass finalize machine instruction
		/// bundles (created earlier, e.g. during pre-RA scheduling).
		extern char &FinalizeMachineBundlesID;

	} // End llvm namespace	} // End llvm namespace

	#endif	#endif

End of changes. 45 change blocks.
	88 lines changed or deleted	327 lines changed or added

	PathV1.h	PathV1.h

	skipping to change at line 134	skipping to change at line 134
	/// @see GetSystemLibraryPaths	/// @see GetSystemLibraryPaths
	/// @brief Construct a list of directories in which bitcode could be	/// @brief Construct a list of directories in which bitcode could be
	/// found.	/// found.
	static void GetBitcodeLibraryPaths(std::vector<sys::Path>& Paths);	static void GetBitcodeLibraryPaths(std::vector<sys::Path>& Paths);

	/// Find the path to a library using its short name. Use the system	/// Find the path to a library using its short name. Use the system
	/// dependent library paths to locate the library.	/// dependent library paths to locate the library.
	/// @brief Find a library.	/// @brief Find a library.
	static Path FindLibrary(std::string& short_name);	static Path FindLibrary(std::string& short_name);


	/// Construct a path to the default LLVM configuration directory. The
	/// implementation must ensure that this is a well-known (same on man
	y
	/// systems) directory in which llvm configuration files exist. For
	/// example, on Unix, the /etc/llvm directory has been selected.
	/// @brief Construct a path to the default LLVM configuration directo
	ry
	static Path GetLLVMDefaultConfigDir();

	/// Construct a path to the LLVM installed configuration directory. T
	he
	/// implementation must ensure that this refers to the "etc" director
	y of
	/// the LLVM installation. This is the location where configuration f
	iles
	/// will be located for a particular installation of LLVM on a machin
	e.
	/// @brief Construct a path to the LLVM installed configuration direc
	tory
	static Path GetLLVMConfigDir();

	/// Construct a path to the current user's home directory. The	/// Construct a path to the current user's home directory. The
	/// implementation must use an operating system specific mechanism fo r	/// implementation must use an operating system specific mechanism fo r
	/// determining the user's home directory. For example, the environme nt	/// determining the user's home directory. For example, the environme nt
	/// variable "HOME" could be used on Unix. If a given operating syste m	/// variable "HOME" could be used on Unix. If a given operating syste m
	/// does not have the concept of a user's home directory, this static	/// does not have the concept of a user's home directory, this static
	/// constructor must provide the same result as GetRootDirectory.	/// constructor must provide the same result as GetRootDirectory.
	/// @brief Construct a path to the current user's "home" directory	/// @brief Construct a path to the current user's "home" directory
	static Path GetUserHomeDirectory();	static Path GetUserHomeDirectory();

	/// Construct a path to the current directory for the current process .	/// Construct a path to the current directory for the current process .

End of changes. 1 change blocks.
	21 lines changed or deleted	0 lines changed or added

	PatternMatch.h	PatternMatch.h

	skipping to change at line 34	skipping to change at line 34
	// This is primarily useful to things like the instruction combiner, but ca n	// This is primarily useful to things like the instruction combiner, but ca n
	// also be useful for static analysis tools or code generators.	// also be useful for static analysis tools or code generators.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_SUPPORT_PATTERNMATCH_H	#ifndef LLVM_SUPPORT_PATTERNMATCH_H
	#define LLVM_SUPPORT_PATTERNMATCH_H	#define LLVM_SUPPORT_PATTERNMATCH_H

	#include "llvm/Constants.h"	#include "llvm/Constants.h"
	#include "llvm/Instructions.h"	#include "llvm/Instructions.h"

		#include "llvm/Operator.h"

	namespace llvm {	namespace llvm {
	namespace PatternMatch {	namespace PatternMatch {

	template<typename Val, typename Pattern>	template<typename Val, typename Pattern>
	bool match(Val *V, const Pattern &P) {	bool match(Val *V, const Pattern &P) {
	return const_cast<Pattern&>(P).match(V);	return const_cast<Pattern&>(P).match(V);
	}	}

	template<typename SubPattern_t>	template<typename SubPattern_t>

	skipping to change at line 97	skipping to change at line 98

	struct apint_match {	struct apint_match {
	const APInt *&Res;	const APInt *&Res;
	apint_match(const APInt *&R) : Res(R) {}	apint_match(const APInt *&R) : Res(R) {}
	template<typename ITy>	template<typename ITy>
	bool match(ITy *V) {	bool match(ITy *V) {
	if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {	if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
	Res = &CI->getValue();	Res = &CI->getValue();
	return true;	return true;
	}	}

		// FIXME: Remove this.
	if (ConstantVector *CV = dyn_cast<ConstantVector>(V))	if (ConstantVector *CV = dyn_cast<ConstantVector>(V))
	if (ConstantInt *CI =	if (ConstantInt *CI =
	dyn_cast_or_null<ConstantInt>(CV->getSplatValue())) {	dyn_cast_or_null<ConstantInt>(CV->getSplatValue())) {
	Res = &CI->getValue();	Res = &CI->getValue();
	return true;	return true;
	}	}

		if (ConstantDataVector *CV = dyn_cast<ConstantDataVector>(V))
		if (ConstantInt *CI =
		dyn_cast_or_null<ConstantInt>(CV->getSplatValue())) {
		Res = &CI->getValue();
		return true;
		}
	return false;	return false;
	}	}
	};	};

	/// m_APInt - Match a ConstantInt or splatted ConstantVector, binding the	/// m_APInt - Match a ConstantInt or splatted ConstantVector, binding the
	/// specified pointer to the contained APInt.	/// specified pointer to the contained APInt.
	inline apint_match m_APInt(const APInt *&Res) { return Res; }	inline apint_match m_APInt(const APInt *&Res) { return Res; }

	template<int64_t Val>	template<int64_t Val>
	struct constantint_match {	struct constantint_match {

	skipping to change at line 142	skipping to change at line 150
	}	}

	/// cst_pred_ty - This helper class is used to match scalar and vector cons tants	/// cst_pred_ty - This helper class is used to match scalar and vector cons tants
	/// that satisfy a specified predicate.	/// that satisfy a specified predicate.
	template<typename Predicate>	template<typename Predicate>
	struct cst_pred_ty : public Predicate {	struct cst_pred_ty : public Predicate {
	template<typename ITy>	template<typename ITy>
	bool match(ITy *V) {	bool match(ITy *V) {
	if (const ConstantInt *CI = dyn_cast<ConstantInt>(V))	if (const ConstantInt *CI = dyn_cast<ConstantInt>(V))
	return this->isValue(CI->getValue());	return this->isValue(CI->getValue());

		// FIXME: Remove this.
	if (const ConstantVector *CV = dyn_cast<ConstantVector>(V))	if (const ConstantVector *CV = dyn_cast<ConstantVector>(V))
	if (ConstantInt *CI = dyn_cast_or_null<ConstantInt>(CV->getSplatValue ()))	if (ConstantInt *CI = dyn_cast_or_null<ConstantInt>(CV->getSplatValue ()))
	return this->isValue(CI->getValue());	return this->isValue(CI->getValue());

		if (const ConstantDataVector *CV = dyn_cast<ConstantDataVector>(V))
		if (ConstantInt *CI = dyn_cast_or_null<ConstantInt>(CV->getSplatValue
		()))
		return this->isValue(CI->getValue());
	return false;	return false;
	}	}
	};	};

	/// api_pred_ty - This helper class is used to match scalar and vector cons tants	/// api_pred_ty - This helper class is used to match scalar and vector cons tants
	/// that satisfy a specified predicate, and bind them to an APInt.	/// that satisfy a specified predicate, and bind them to an APInt.
	template<typename Predicate>	template<typename Predicate>
	struct api_pred_ty : public Predicate {	struct api_pred_ty : public Predicate {
	const APInt *&Res;	const APInt *&Res;
	api_pred_ty(const APInt *&R) : Res(R) {}	api_pred_ty(const APInt *&R) : Res(R) {}
	template<typename ITy>	template<typename ITy>
	bool match(ITy *V) {	bool match(ITy *V) {
	if (const ConstantInt *CI = dyn_cast<ConstantInt>(V))	if (const ConstantInt *CI = dyn_cast<ConstantInt>(V))
	if (this->isValue(CI->getValue())) {	if (this->isValue(CI->getValue())) {
	Res = &CI->getValue();	Res = &CI->getValue();
	return true;	return true;
	}	}


		// FIXME: remove.
	if (const ConstantVector *CV = dyn_cast<ConstantVector>(V))	if (const ConstantVector *CV = dyn_cast<ConstantVector>(V))
	if (ConstantInt *CI = dyn_cast_or_null<ConstantInt>(CV->getSplatValue ()))	if (ConstantInt *CI = dyn_cast_or_null<ConstantInt>(CV->getSplatValue ()))
	if (this->isValue(CI->getValue())) {	if (this->isValue(CI->getValue())) {
	Res = &CI->getValue();	Res = &CI->getValue();
	return true;	return true;
	}	}


		if (const ConstantDataVector *CV = dyn_cast<ConstantDataVector>(V))
		if (ConstantInt *CI = dyn_cast_or_null<ConstantInt>(CV->getSplatValue
		()))
		if (this->isValue(CI->getValue())) {
		Res = &CI->getValue();
		return true;
		}

	return false;	return false;
	}	}
	};	};

	struct is_one {	struct is_one {
	bool isValue(const APInt &C) { return C == 1; }	bool isValue(const APInt &C) { return C == 1; }
	};	};

	/// m_One() - Match an integer 1 or a vector with all elements equal to 1.	/// m_One() - Match an integer 1 or a vector with all elements equal to 1.
	inline cst_pred_ty<is_one> m_One() { return cst_pred_ty<is_one>(); }	inline cst_pred_ty<is_one> m_One() { return cst_pred_ty<is_one>(); }

	skipping to change at line 439	skipping to change at line 461
	}	}

	/// m_IDiv - Matches UDiv and SDiv.	/// m_IDiv - Matches UDiv and SDiv.
	template<typename LHS, typename RHS>	template<typename LHS, typename RHS>
	inline BinOp2_match<LHS, RHS, Instruction::SDiv, Instruction::UDiv>	inline BinOp2_match<LHS, RHS, Instruction::SDiv, Instruction::UDiv>
	m_IDiv(const LHS &L, const RHS &R) {	m_IDiv(const LHS &L, const RHS &R) {
	return BinOp2_match<LHS, RHS, Instruction::SDiv, Instruction::UDiv>(L, R) ;	return BinOp2_match<LHS, RHS, Instruction::SDiv, Instruction::UDiv>(L, R) ;
	}	}

	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

		// Class that matches exact binary ops.
		//
		template<typename SubPattern_t>
		struct Exact_match {
		SubPattern_t SubPattern;

		Exact_match(const SubPattern_t &SP) : SubPattern(SP) {}

		template<typename OpTy>
		bool match(OpTy *V) {
		if (PossiblyExactOperator *PEO = dyn_cast<PossiblyExactOperator>(V))
		return PEO->isExact() && SubPattern.match(V);
		return false;
		}
		};

		template<typename T>
		inline Exact_match<T> m_Exact(const T &SubPattern) { return SubPattern; }

		//===----------------------------------------------------------------------
		===//
	// Matchers for CmpInst classes	// Matchers for CmpInst classes
	//	//

	template<typename LHS_t, typename RHS_t, typename Class, typename Predicate Ty>	template<typename LHS_t, typename RHS_t, typename Class, typename Predicate Ty>
	struct CmpClass_match {	struct CmpClass_match {
	PredicateTy &Predicate;	PredicateTy &Predicate;
	LHS_t L;	LHS_t L;
	RHS_t R;	RHS_t R;

	CmpClass_match(PredicateTy &Pred, const LHS_t &LHS, const RHS_t &RHS)	CmpClass_match(PredicateTy &Pred, const LHS_t &LHS, const RHS_t &RHS)

	skipping to change at line 526	skipping to change at line 568
	//	//

	template<typename Op_t, unsigned Opcode>	template<typename Op_t, unsigned Opcode>
	struct CastClass_match {	struct CastClass_match {
	Op_t Op;	Op_t Op;

	CastClass_match(const Op_t &OpMatch) : Op(OpMatch) {}	CastClass_match(const Op_t &OpMatch) : Op(OpMatch) {}

	template<typename OpTy>	template<typename OpTy>
	bool match(OpTy *V) {	bool match(OpTy *V) {

	if (CastInst *I = dyn_cast<CastInst>(V))	if (Operator *O = dyn_cast<Operator>(V))
	return I->getOpcode() == Opcode && Op.match(I->getOperand(0));	return O->getOpcode() == Opcode && Op.match(O->getOperand(0));
	if (ConstantExpr *CE = dyn_cast<ConstantExpr>(V))
	return CE->getOpcode() == Opcode && Op.match(CE->getOperand(0));
	return false;	return false;
	}	}
	};	};

	/// m_BitCast	/// m_BitCast
	template<typename OpTy>	template<typename OpTy>
	inline CastClass_match<OpTy, Instruction::BitCast>	inline CastClass_match<OpTy, Instruction::BitCast>
	m_BitCast(const OpTy &Op) {	m_BitCast(const OpTy &Op) {
	return CastClass_match<OpTy, Instruction::BitCast>(Op);	return CastClass_match<OpTy, Instruction::BitCast>(Op);
	}	}

	skipping to change at line 581	skipping to change at line 621
	//	//

	template<typename LHS_t>	template<typename LHS_t>
	struct not_match {	struct not_match {
	LHS_t L;	LHS_t L;

	not_match(const LHS_t &LHS) : L(LHS) {}	not_match(const LHS_t &LHS) : L(LHS) {}

	template<typename OpTy>	template<typename OpTy>
	bool match(OpTy *V) {	bool match(OpTy *V) {

	if (Instruction *I = dyn_cast<Instruction>(V))	if (Operator *O = dyn_cast<Operator>(V))
	if (I->getOpcode() == Instruction::Xor)	if (O->getOpcode() == Instruction::Xor)
	return matchIfNot(I->getOperand(0), I->getOperand(1));	return matchIfNot(O->getOperand(0), O->getOperand(1));
	if (ConstantExpr *CE = dyn_cast<ConstantExpr>(V))
	if (CE->getOpcode() == Instruction::Xor)
	return matchIfNot(CE->getOperand(0), CE->getOperand(1));
	return false;	return false;
	}	}
	private:	private:
	bool matchIfNot(Value LHS, Value RHS) {	bool matchIfNot(Value LHS, Value RHS) {

	if (ConstantInt *CI = dyn_cast<ConstantInt>(RHS))	return (isa<ConstantInt>(RHS) \|\| isa<ConstantDataVector>(RHS) \|\|
	return CI->isAllOnesValue() && L.match(LHS);	// FIXME: Remove CV.
	if (ConstantVector *CV = dyn_cast<ConstantVector>(RHS))	isa<ConstantVector>(RHS)) &&
	return CV->isAllOnesValue() && L.match(LHS);	cast<Constant>(RHS)->isAllOnesValue() &&
	return false;	L.match(LHS);
	}	}
	};	};

	template<typename LHS>	template<typename LHS>
	inline not_match<LHS> m_Not(const LHS &L) { return L; }	inline not_match<LHS> m_Not(const LHS &L) { return L; }

	template<typename LHS_t>	template<typename LHS_t>
	struct neg_match {	struct neg_match {
	LHS_t L;	LHS_t L;

	neg_match(const LHS_t &LHS) : L(LHS) {}	neg_match(const LHS_t &LHS) : L(LHS) {}

	template<typename OpTy>	template<typename OpTy>
	bool match(OpTy *V) {	bool match(OpTy *V) {

	if (Instruction *I = dyn_cast<Instruction>(V))	if (Operator *O = dyn_cast<Operator>(V))
	if (I->getOpcode() == Instruction::Sub)	if (O->getOpcode() == Instruction::Sub)
	return matchIfNeg(I->getOperand(0), I->getOperand(1));	return matchIfNeg(O->getOperand(0), O->getOperand(1));
	if (ConstantExpr *CE = dyn_cast<ConstantExpr>(V))
	if (CE->getOpcode() == Instruction::Sub)
	return matchIfNeg(CE->getOperand(0), CE->getOperand(1));
	return false;	return false;
	}	}
	private:	private:
	bool matchIfNeg(Value LHS, Value RHS) {	bool matchIfNeg(Value LHS, Value RHS) {

	if (ConstantInt *C = dyn_cast<ConstantInt>(LHS))	return ((isa<ConstantInt>(LHS) && cast<ConstantInt>(LHS)->isZero()) \|\|
	return C->isZero() && L.match(RHS);	isa<ConstantAggregateZero>(LHS)) &&
	return false;	L.match(RHS);
	}	}
	};	};

	/// m_Neg - Match an integer negate.	/// m_Neg - Match an integer negate.
	template<typename LHS>	template<typename LHS>
	inline neg_match<LHS> m_Neg(const LHS &L) { return L; }	inline neg_match<LHS> m_Neg(const LHS &L) { return L; }

	template<typename LHS_t>	template<typename LHS_t>
	struct fneg_match {	struct fneg_match {
	LHS_t L;	LHS_t L;

	fneg_match(const LHS_t &LHS) : L(LHS) {}	fneg_match(const LHS_t &LHS) : L(LHS) {}

	template<typename OpTy>	template<typename OpTy>
	bool match(OpTy *V) {	bool match(OpTy *V) {

	if (Instruction *I = dyn_cast<Instruction>(V))	if (Operator *O = dyn_cast<Operator>(V))
	if (I->getOpcode() == Instruction::FSub)	if (O->getOpcode() == Instruction::FSub)
	return matchIfFNeg(I->getOperand(0), I->getOperand(1));	return matchIfFNeg(O->getOperand(0), O->getOperand(1));
	if (ConstantExpr *CE = dyn_cast<ConstantExpr>(V))
	if (CE->getOpcode() == Instruction::FSub)
	return matchIfFNeg(CE->getOperand(0), CE->getOperand(1));
	return false;	return false;
	}	}
	private:	private:
	bool matchIfFNeg(Value LHS, Value RHS) {	bool matchIfFNeg(Value LHS, Value RHS) {
	if (ConstantFP *C = dyn_cast<ConstantFP>(LHS))	if (ConstantFP *C = dyn_cast<ConstantFP>(LHS))
	return C->isNegativeZeroValue() && L.match(RHS);	return C->isNegativeZeroValue() && L.match(RHS);
	return false;	return false;
	}	}
	};	};


End of changes. 14 change blocks.
	30 lines changed or deleted	64 lines changed or added

	PointerUnion.h	PointerUnion.h

	skipping to change at line 145	skipping to change at line 145
	}	}

	/// dyn_cast<T>() - If the current value is of the specified pointer ty pe,	/// dyn_cast<T>() - If the current value is of the specified pointer ty pe,
	/// return it, otherwise return null.	/// return it, otherwise return null.
	template<typename T>	template<typename T>
	T dyn_cast() const {	T dyn_cast() const {
	if (is<T>()) return get<T>();	if (is<T>()) return get<T>();
	return T();	return T();
	}	}


	/// \brief If the union is set to the first pointer type we can get an	/// \brief If the union is set to the first pointer type get an address
	/// address pointing to it.	/// pointing to it.
	template <typename T>	PT1 const *getAddrOfPtr1() const {
	PT1 const *getAddrOf() const {	return const_cast<PointerUnion *>(this)->getAddrOfPtr1();
		}

		/// \brief If the union is set to the first pointer type get an address
		/// pointing to it.
		PT1 *getAddrOfPtr1() {
	assert(is<PT1>() && "Val is not the first pointer");	assert(is<PT1>() && "Val is not the first pointer");
	assert(get<PT1>() == Val.getPointer() &&	assert(get<PT1>() == Val.getPointer() &&
	"Can't get the address because PointerLikeTypeTraits changes the p tr");	"Can't get the address because PointerLikeTypeTraits changes the p tr");

	T const *can_only_get_address_of_first_pointer_type	return (PT1 *)Val.getAddrOfPointer();
	= reinterpret_cast<PT1 const *>(Val.getAddrOfPointe
	r());
	return can_only_get_address_of_first_pointer_type;
	}	}

	/// Assignment operators - Allow assigning into this union from either	/// Assignment operators - Allow assigning into this union from either
	/// pointer type, setting the discriminator to remember what it came fr om.	/// pointer type, setting the discriminator to remember what it came fr om.
	const PointerUnion &operator=(const PT1 &RHS) {	const PointerUnion &operator=(const PT1 &RHS) {
	Val.setPointer(	Val.setPointer(
	const_cast<void *>(PointerLikeTypeTraits<PT1>::getAsVoidPointer(RH S)));	const_cast<void *>(PointerLikeTypeTraits<PT1>::getAsVoidPointer(RH S)));
	Val.setInt(0);	Val.setInt(0);
	return *this;	return *this;
	}	}

	skipping to change at line 265	skipping to change at line 268
	operator bool() const { return !isNull(); }	operator bool() const { return !isNull(); }

	/// is<T>() return true if the Union currently holds the type matching T.	/// is<T>() return true if the Union currently holds the type matching T.
	template<typename T>	template<typename T>
	int is() const {	int is() const {
	// If T is PT1/PT2 choose IsInnerUnion otherwise choose IsPT3.	// If T is PT1/PT2 choose IsInnerUnion otherwise choose IsPT3.
	typedef typename	typedef typename
	::llvm::PointerUnionTypeSelector<PT1, T, IsInnerUnion,	::llvm::PointerUnionTypeSelector<PT1, T, IsInnerUnion,
	::llvm::PointerUnionTypeSelector<PT2, T, IsInnerUnion, IsPT3 >	::llvm::PointerUnionTypeSelector<PT2, T, IsInnerUnion, IsPT3 >
	>::Retur n Ty;	>::Retur n Ty;

	return Ty(Val).is<T>();	return Ty(Val).template is<T>();
	}	}

	/// get<T>() - Return the value of the specified pointer type. If the	/// get<T>() - Return the value of the specified pointer type. If the
	/// specified pointer type is incorrect, assert.	/// specified pointer type is incorrect, assert.
	template<typename T>	template<typename T>
	T get() const {	T get() const {
	assert(is<T>() && "Invalid accessor called");	assert(is<T>() && "Invalid accessor called");
	// If T is PT1/PT2 choose IsInnerUnion otherwise choose IsPT3.	// If T is PT1/PT2 choose IsInnerUnion otherwise choose IsPT3.
	typedef typename	typedef typename
	::llvm::PointerUnionTypeSelector<PT1, T, IsInnerUnion,	::llvm::PointerUnionTypeSelector<PT1, T, IsInnerUnion,
	::llvm::PointerUnionTypeSelector<PT2, T, IsInnerUnion, IsPT3 >	::llvm::PointerUnionTypeSelector<PT2, T, IsInnerUnion, IsPT3 >
	>::Retur n Ty;	>::Retur n Ty;

	return Ty(Val).get<T>();	return Ty(Val).template get<T>();
	}	}

	/// dyn_cast<T>() - If the current value is of the specified pointer ty pe,	/// dyn_cast<T>() - If the current value is of the specified pointer ty pe,
	/// return it, otherwise return null.	/// return it, otherwise return null.
	template<typename T>	template<typename T>
	T dyn_cast() const {	T dyn_cast() const {
	if (is<T>()) return get<T>();	if (is<T>()) return get<T>();
	return T();	return T();
	}	}


End of changes. 4 change blocks.
	10 lines changed or deleted	12 lines changed or added

	Process.h	Process.h

	skipping to change at line 139	skipping to change at line 139
	/// This function returns the colorcode escape sequences.	/// This function returns the colorcode escape sequences.
	/// If ColorNeedsFlush() is true then this function will change the c olors	/// If ColorNeedsFlush() is true then this function will change the c olors
	/// and return an empty escape sequence. In that case it is the	/// and return an empty escape sequence. In that case it is the
	/// responsibility of the client to flush the output stream prior to	/// responsibility of the client to flush the output stream prior to
	/// calling this function.	/// calling this function.
	static const char *OutputColor(char c, bool bold, bool bg);	static const char *OutputColor(char c, bool bold, bool bg);

	/// Same as OutputColor, but only enables the bold attribute.	/// Same as OutputColor, but only enables the bold attribute.
	static const char *OutputBold(bool bg);	static const char *OutputBold(bool bg);


		/// This function returns the escape sequence to reverse forground an
		d
		/// background colors.
		static const char *OutputReverse();

	/// Resets the terminals colors, or returns an escape sequence to do so.	/// Resets the terminals colors, or returns an escape sequence to do so.
	static const char *ResetColor();	static const char *ResetColor();


	/// Change the program working directory to that given by \arg Path.
	static void SetWorkingDirectory(std::string Path);
	/// @}	/// @}
	};	};
	}	}
	}	}

	#endif	#endif

End of changes. 2 change blocks.
	3 lines changed or deleted	5 lines changed or added

	ProfileInfo.h	ProfileInfo.h

	skipping to change at line 25	skipping to change at line 25
	// Note that to be useful, all profile-based optimizations should preserve	// Note that to be useful, all profile-based optimizations should preserve
	// ProfileInfo, which requires that they notify it when changes to the CFG are	// ProfileInfo, which requires that they notify it when changes to the CFG are
	// made. (This is not implemented yet.)	// made. (This is not implemented yet.)
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_ANALYSIS_PROFILEINFO_H	#ifndef LLVM_ANALYSIS_PROFILEINFO_H
	#define LLVM_ANALYSIS_PROFILEINFO_H	#define LLVM_ANALYSIS_PROFILEINFO_H

	#include "llvm/Support/Debug.h"	#include "llvm/Support/Debug.h"

		#include "llvm/Support/ErrorHandling.h"
	#include "llvm/Support/Format.h"	#include "llvm/Support/Format.h"
	#include "llvm/Support/raw_ostream.h"	#include "llvm/Support/raw_ostream.h"
	#include <cassert>	#include <cassert>
	#include <string>	#include <string>
	#include <map>	#include <map>
	#include <set>	#include <set>

	namespace llvm {	namespace llvm {
	class Pass;	class Pass;
	class raw_ostream;	class raw_ostream;

	skipping to change at line 88	skipping to change at line 89
	static char ID; // Class identification, replacement for typeinfo	static char ID; // Class identification, replacement for typeinfo
	ProfileInfoT();	ProfileInfoT();
	~ProfileInfoT(); // We want to be subclassed	~ProfileInfoT(); // We want to be subclassed

	// MissingValue - The value that is returned for execution counts in ca se	// MissingValue - The value that is returned for execution counts in ca se
	// no value is available.	// no value is available.
	static const double MissingValue;	static const double MissingValue;

	// getFunction() - Returns the Function for an Edge, checking for valid ity.	// getFunction() - Returns the Function for an Edge, checking for valid ity.
	static const FType* getFunction(Edge e) {	static const FType* getFunction(Edge e) {

	if (e.first) {	if (e.first)
	return e.first->getParent();	return e.first->getParent();

	} else if (e.second) {	if (e.second)
	return e.second->getParent();	return e.second->getParent();

	}	llvm_unreachable("Invalid ProfileInfo::Edge");
	assert(0 && "Invalid ProfileInfo::Edge");
	return (const FType*)0;
	}	}

	// getEdge() - Creates an Edge from two BasicBlocks.	// getEdge() - Creates an Edge from two BasicBlocks.
	static Edge getEdge(const BType Src, const BType Dest) {	static Edge getEdge(const BType Src, const BType Dest) {
	return std::make_pair(Src, Dest);	return std::make_pair(Src, Dest);
	}	}

	//===------------------------------------------------------------------ ===//	//===------------------------------------------------------------------ ===//
	/// Profile Information Queries	/// Profile Information Queries
	///	///

End of changes. 4 change blocks.
	5 lines changed or deleted	4 lines changed or added

	Program.h	Program.h

	skipping to change at line 20	skipping to change at line 20
	// This file declares the llvm::sys::Program class.	// This file declares the llvm::sys::Program class.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_SYSTEM_PROGRAM_H	#ifndef LLVM_SYSTEM_PROGRAM_H
	#define LLVM_SYSTEM_PROGRAM_H	#define LLVM_SYSTEM_PROGRAM_H

	#include "llvm/Support/Path.h"	#include "llvm/Support/Path.h"

	namespace llvm {	namespace llvm {

		class error_code;
	namespace sys {	namespace sys {

	// TODO: Add operations to communicate with the process, redirect its I/O ,	// TODO: Add operations to communicate with the process, redirect its I/O ,
	// etc.	// etc.

	/// This class provides an abstraction for programs that are executable b y the	/// This class provides an abstraction for programs that are executable b y the
	/// operating system. It provides a platform generic way to find executab le	/// operating system. It provides a platform generic way to find executab le
	/// programs from the path and to execute them in various ways. The sys:: Path	/// programs from the path and to execute them in various ways. The sys:: Path
	/// class is used to specify the location of the Program.	/// class is used to specify the location of the Program.
	/// @since 1.4	/// @since 1.4

	skipping to change at line 125	skipping to change at line 126

	/// This static constructor (factory) will attempt to locate a program in	/// This static constructor (factory) will attempt to locate a program in
	/// the operating system's file system using some pre-determined set of	/// the operating system's file system using some pre-determined set of
	/// locations to search (e.g. the PATH on Unix). Paths with slashes are	/// locations to search (e.g. the PATH on Unix). Paths with slashes are
	/// returned unmodified.	/// returned unmodified.
	/// @returns A Path object initialized to the path of the program or a	/// @returns A Path object initialized to the path of the program or a
	/// Path object that is empty (invalid) if the program could not be fou nd.	/// Path object that is empty (invalid) if the program could not be fou nd.
	/// @brief Construct a Program by finding it by name.	/// @brief Construct a Program by finding it by name.
	static Path FindProgramByName(const std::string& name);	static Path FindProgramByName(const std::string& name);


	// These methods change the specified standard stream (stdin,	// These methods change the specified standard stream (stdin, stdout, o
	// stdout, or stderr) to binary mode. They return true if an error	r
	// occurred	// stderr) to binary mode. They return errc::success if the specified s
	static bool ChangeStdinToBinary();	tream
	static bool ChangeStdoutToBinary();	// was changed. Otherwise a platform dependent error is returned.
	static bool ChangeStderrToBinary();	static error_code ChangeStdinToBinary();
		static error_code ChangeStdoutToBinary();
		static error_code ChangeStderrToBinary();

	/// A convenience function equivalent to Program prg; prg.Execute(..);	/// A convenience function equivalent to Program prg; prg.Execute(..);
	/// prg.Wait(..);	/// prg.Wait(..);
	/// @see Execute, Wait	/// @see Execute, Wait
	static int ExecuteAndWait(const Path& path,	static int ExecuteAndWait(const Path& path,
	const char** args,	const char** args,
	const char ** env = 0,	const char ** env = 0,
	const sys::Path** redirects = 0,	const sys::Path** redirects = 0,
	unsigned secondsToWait = 0,	unsigned secondsToWait = 0,
	unsigned memoryLimit = 0,	unsigned memoryLimit = 0,

End of changes. 2 change blocks.
	6 lines changed or deleted	9 lines changed or added

	ReaderWriter.h	ReaderWriter.h

	skipping to change at line 20	skipping to change at line 20
	// This header defines interfaces to read and write LLVM bitcode files/stre ams.	// This header defines interfaces to read and write LLVM bitcode files/stre ams.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_BITCODE_H	#ifndef LLVM_BITCODE_H
	#define LLVM_BITCODE_H	#define LLVM_BITCODE_H

	#include <string>	#include <string>

	namespace llvm {	namespace llvm {

	class Module;
	class MemoryBuffer;
	class ModulePass;
	class BitstreamWriter;	class BitstreamWriter;

		class MemoryBuffer;
		class DataStreamer;
	class LLVMContext;	class LLVMContext;

		class Module;
		class ModulePass;
	class raw_ostream;	class raw_ostream;

	/// getLazyBitcodeModule - Read the header of the specified bitcode buffe r	/// getLazyBitcodeModule - Read the header of the specified bitcode buffe r
	/// and prepare for lazy deserialization of function bodies. If successf ul,	/// and prepare for lazy deserialization of function bodies. If successf ul,
	/// this takes ownership of 'buffer' and returns a non-null pointer. On	/// this takes ownership of 'buffer' and returns a non-null pointer. On
	/// error, this returns null, does not take ownership of Buffer, and fi lls	/// error, this returns null, does not take ownership of Buffer, and fi lls
	/// in *ErrMsg with an error description if ErrMsg is non-null.	/// in *ErrMsg with an error description if ErrMsg is non-null.
	Module getLazyBitcodeModule(MemoryBuffer Buffer,	Module getLazyBitcodeModule(MemoryBuffer Buffer,

	LLVMContext& Context,	LLVMContext &Context,
	std::string *ErrMsg = 0);	std::string *ErrMsg = 0);


		/// getStreamedBitcodeModule - Read the header of the specified stream
		/// and prepare for lazy deserialization and streaming of function bodies
		.
		/// On error, this returns null, and fills in *ErrMsg with an error
		/// description if ErrMsg is non-null.
		Module *getStreamedBitcodeModule(const std::string &name,
		DataStreamer *streamer,
		LLVMContext &Context,
		std::string *ErrMsg = 0);

	/// getBitcodeTargetTriple - Read the header of the specified bitcode	/// getBitcodeTargetTriple - Read the header of the specified bitcode
	/// buffer and extract just the triple information. If successful,	/// buffer and extract just the triple information. If successful,
	/// this returns a string and does not take ownership	/// this returns a string and does not take ownership
	/// of 'buffer'. On error, this returns "", and fills in *ErrMsg	/// of 'buffer'. On error, this returns "", and fills in *ErrMsg
	/// if ErrMsg is non-null.	/// if ErrMsg is non-null.
	std::string getBitcodeTargetTriple(MemoryBuffer *Buffer,	std::string getBitcodeTargetTriple(MemoryBuffer *Buffer,

	LLVMContext& Context,	LLVMContext &Context,
	std::string *ErrMsg = 0);	std::string *ErrMsg = 0);

	/// ParseBitcodeFile - Read the specified bitcode file, returning the mod ule.	/// ParseBitcodeFile - Read the specified bitcode file, returning the mod ule.
	/// If an error occurs, this returns null and fills in *ErrMsg if it is	/// If an error occurs, this returns null and fills in *ErrMsg if it is
	/// non-null. This method never takes ownership of Buffer.	/// non-null. This method never takes ownership of Buffer.

	Module ParseBitcodeFile(MemoryBuffer Buffer, LLVMContext& Context,	Module ParseBitcodeFile(MemoryBuffer Buffer, LLVMContext &Context,
	std::string *ErrMsg = 0);	std::string *ErrMsg = 0);

	/// WriteBitcodeToFile - Write the specified module to the specified	/// WriteBitcodeToFile - Write the specified module to the specified
	/// raw output stream. For streams where it matters, the given stream	/// raw output stream. For streams where it matters, the given stream
	/// should be in "binary" mode.	/// should be in "binary" mode.
	void WriteBitcodeToFile(const Module *M, raw_ostream &Out);	void WriteBitcodeToFile(const Module *M, raw_ostream &Out);


	/// WriteBitcodeToStream - Write the specified module to the specified
	/// raw output stream.
	void WriteBitcodeToStream(const Module *M, BitstreamWriter &Stream);

	/// createBitcodeWriterPass - Create and return a pass that writes the mo dule	/// createBitcodeWriterPass - Create and return a pass that writes the mo dule
	/// to the specified ostream.	/// to the specified ostream.
	ModulePass *createBitcodeWriterPass(raw_ostream &Str);	ModulePass *createBitcodeWriterPass(raw_ostream &Str);

	/// isBitcodeWrapper - Return true if the given bytes are the magic bytes	/// isBitcodeWrapper - Return true if the given bytes are the magic bytes
	/// for an LLVM IR bitcode wrapper.	/// for an LLVM IR bitcode wrapper.
	///	///
	static inline bool isBitcodeWrapper(const unsigned char *BufPtr,	static inline bool isBitcodeWrapper(const unsigned char *BufPtr,
	const unsigned char *BufEnd) {	const unsigned char *BufEnd) {
	// See if you can find the hidden message in the magic bytes :-).	// See if you can find the hidden message in the magic bytes :-).

	skipping to change at line 115	skipping to change at line 121
	/// uint32_t Magic; // 0x0B17C0DE	/// uint32_t Magic; // 0x0B17C0DE
	/// uint32_t Version; // Version, currently always 0.	/// uint32_t Version; // Version, currently always 0.
	/// uint32_t BitcodeOffset; // Offset to traditional bitcode file.	/// uint32_t BitcodeOffset; // Offset to traditional bitcode file.
	/// uint32_t BitcodeSize; // Size of traditional bitcode file.	/// uint32_t BitcodeSize; // Size of traditional bitcode file.
	/// ... potentially other gunk ...	/// ... potentially other gunk ...
	/// };	/// };
	///	///
	/// This function is called when we find a file with a matching magic num ber.	/// This function is called when we find a file with a matching magic num ber.
	/// In this case, skip down to the subsection of the file that is actuall y a	/// In this case, skip down to the subsection of the file that is actuall y a
	/// BC file.	/// BC file.

	static inline bool SkipBitcodeWrapperHeader(unsigned char *&BufPtr,	/// If 'VerifyBufferSize' is true, check that the buffer is large enough
	unsigned char *&BufEnd) {	to
		/// contain the whole bitcode file.
		static inline bool SkipBitcodeWrapperHeader(const unsigned char *&BufPtr,
		const unsigned char *&BufEnd,
		bool VerifyBufferSize) {
	enum {	enum {
	KnownHeaderSize = 4*4, // Size of header we read.	KnownHeaderSize = 4*4, // Size of header we read.
	OffsetField = 2*4, // Offset in bytes to Offset field.	OffsetField = 2*4, // Offset in bytes to Offset field.
	SizeField = 3*4 // Offset in bytes to Size field.	SizeField = 3*4 // Offset in bytes to Size field.
	};	};

	// Must contain the header!	// Must contain the header!
	if (BufEnd-BufPtr < KnownHeaderSize) return true;	if (BufEnd-BufPtr < KnownHeaderSize) return true;

	unsigned Offset = ( BufPtr[OffsetField ] \|	unsigned Offset = ( BufPtr[OffsetField ] \|
	(BufPtr[OffsetField+1] << 8) \|	(BufPtr[OffsetField+1] << 8) \|
	(BufPtr[OffsetField+2] << 16) \|	(BufPtr[OffsetField+2] << 16) \|
	(BufPtr[OffsetField+3] << 24));	(BufPtr[OffsetField+3] << 24));
	unsigned Size = ( BufPtr[SizeField ] \|	unsigned Size = ( BufPtr[SizeField ] \|
	(BufPtr[SizeField +1] << 8) \|	(BufPtr[SizeField +1] << 8) \|
	(BufPtr[SizeField +2] << 16) \|	(BufPtr[SizeField +2] << 16) \|
	(BufPtr[SizeField +3] << 24));	(BufPtr[SizeField +3] << 24));

	// Verify that Offset+Size fits in the file.	// Verify that Offset+Size fits in the file.

	if (Offset+Size > unsigned(BufEnd-BufPtr))	if (VerifyBufferSize && Offset+Size > unsigned(BufEnd-BufPtr))
	return true;	return true;
	BufPtr += Offset;	BufPtr += Offset;
	BufEnd = BufPtr+Size;	BufEnd = BufPtr+Size;
	return false;	return false;
	}	}
	} // End llvm namespace	} // End llvm namespace

	#endif	#endif

End of changes. 10 change blocks.
	13 lines changed or deleted	24 lines changed or added

	Record.h	Record.h

	skipping to change at line 23	skipping to change at line 23
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_TABLEGEN_RECORD_H	#ifndef LLVM_TABLEGEN_RECORD_H
	#define LLVM_TABLEGEN_RECORD_H	#define LLVM_TABLEGEN_RECORD_H

	#include "llvm/ADT/ArrayRef.h"	#include "llvm/ADT/ArrayRef.h"
	#include "llvm/ADT/FoldingSet.h"	#include "llvm/ADT/FoldingSet.h"
	#include "llvm/Support/Allocator.h"	#include "llvm/Support/Allocator.h"
	#include "llvm/Support/SourceMgr.h"	#include "llvm/Support/SourceMgr.h"
	#include "llvm/Support/DataTypes.h"	#include "llvm/Support/DataTypes.h"

		#include "llvm/Support/ErrorHandling.h"
	#include "llvm/Support/raw_ostream.h"	#include "llvm/Support/raw_ostream.h"
	#include <map>	#include <map>

	namespace llvm {	namespace llvm {
	class raw_ostream;	class raw_ostream;

	// RecTy subclasses.	// RecTy subclasses.
	class BitRecTy;	class BitRecTy;
	class BitsRecTy;	class BitsRecTy;
	class IntRecTy;	class IntRecTy;
	class StringRecTy;	class StringRecTy;
	class ListRecTy;	class ListRecTy;

	class CodeRecTy;
	class DagRecTy;	class DagRecTy;
	class RecordRecTy;	class RecordRecTy;

	// Init subclasses.	// Init subclasses.
	class Init;	class Init;
	class UnsetInit;	class UnsetInit;
	class BitInit;	class BitInit;
	class BitsInit;	class BitsInit;
	class IntInit;	class IntInit;
	class StringInit;	class StringInit;

	class CodeInit;
	class ListInit;	class ListInit;
	class UnOpInit;	class UnOpInit;
	class BinOpInit;	class BinOpInit;
	class TernOpInit;	class TernOpInit;
	class DefInit;	class DefInit;
	class DagInit;	class DagInit;
	class TypedInit;	class TypedInit;
	class VarInit;	class VarInit;
	class FieldInit;	class FieldInit;
	class VarBitInit;	class VarBitInit;

	skipping to change at line 71	skipping to change at line 70
	class RecordVal;	class RecordVal;
	struct MultiClass;	struct MultiClass;
	class RecordKeeper;	class RecordKeeper;

	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	// Type Classes	// Type Classes
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	class RecTy {	class RecTy {
	ListRecTy *ListTy;	ListRecTy *ListTy;

		virtual void anchor();
	public:	public:
	RecTy() : ListTy(0) {}	RecTy() : ListTy(0) {}
	virtual ~RecTy() {}	virtual ~RecTy() {}

	virtual std::string getAsString() const = 0;	virtual std::string getAsString() const = 0;
	void print(raw_ostream &OS) const { OS << getAsString(); }	void print(raw_ostream &OS) const { OS << getAsString(); }
	void dump() const;	void dump() const;

	/// typeIsConvertibleTo - Return true if all values of 'this' type can be	/// typeIsConvertibleTo - Return true if all values of 'this' type can be
	/// converted to the specified type.	/// converted to the specified type.

	skipping to change at line 102	skipping to change at line 102
	virtual Init convertValue( ListInit LI) { return 0; }	virtual Init convertValue( ListInit LI) { return 0; }
	virtual Init convertValue( UnOpInit UI) {	virtual Init convertValue( UnOpInit UI) {
	return convertValue((TypedInit*)UI);	return convertValue((TypedInit*)UI);
	}	}
	virtual Init convertValue( BinOpInit UI) {	virtual Init convertValue( BinOpInit UI) {
	return convertValue((TypedInit*)UI);	return convertValue((TypedInit*)UI);
	}	}
	virtual Init convertValue( TernOpInit UI) {	virtual Init convertValue( TernOpInit UI) {
	return convertValue((TypedInit*)UI);	return convertValue((TypedInit*)UI);
	}	}

	virtual Init convertValue( CodeInit CI) { return 0; }
	virtual Init convertValue(VarBitInit VB) { return 0; }	virtual Init convertValue(VarBitInit VB) { return 0; }
	virtual Init convertValue( DefInit DI) { return 0; }	virtual Init convertValue( DefInit DI) { return 0; }
	virtual Init convertValue( DagInit DI) { return 0; }	virtual Init convertValue( DagInit DI) { return 0; }
	virtual Init convertValue( TypedInit TI) { return 0; }	virtual Init convertValue( TypedInit TI) { return 0; }
	virtual Init convertValue( VarInit VI) {	virtual Init convertValue( VarInit VI) {
	return convertValue((TypedInit*)VI);	return convertValue((TypedInit*)VI);
	}	}
	virtual Init convertValue( FieldInit FI) {	virtual Init convertValue( FieldInit FI) {
	return convertValue((TypedInit*)FI);	return convertValue((TypedInit*)FI);
	}	}

	public: // These methods should only be called by subclasses of RecTy.	public: // These methods should only be called by subclasses of RecTy.
	// baseClassOf - These virtual methods should be overloaded to return tru e iff	// baseClassOf - These virtual methods should be overloaded to return tru e iff
	// all values of type 'RHS' can be converted to the 'this' type.	// all values of type 'RHS' can be converted to the 'this' type.
	virtual bool baseClassOf(const BitRecTy *RHS) const { return false; }	virtual bool baseClassOf(const BitRecTy *RHS) const { return false; }
	virtual bool baseClassOf(const BitsRecTy *RHS) const { return false; }	virtual bool baseClassOf(const BitsRecTy *RHS) const { return false; }
	virtual bool baseClassOf(const IntRecTy *RHS) const { return false; }	virtual bool baseClassOf(const IntRecTy *RHS) const { return false; }
	virtual bool baseClassOf(const StringRecTy *RHS) const { return false; }	virtual bool baseClassOf(const StringRecTy *RHS) const { return false; }
	virtual bool baseClassOf(const ListRecTy *RHS) const { return false; }	virtual bool baseClassOf(const ListRecTy *RHS) const { return false; }

	virtual bool baseClassOf(const CodeRecTy *RHS) const { return false; }
	virtual bool baseClassOf(const DagRecTy *RHS) const { return false; }	virtual bool baseClassOf(const DagRecTy *RHS) const { return false; }
	virtual bool baseClassOf(const RecordRecTy *RHS) const { return false; }	virtual bool baseClassOf(const RecordRecTy *RHS) const { return false; }
	};	};

	inline raw_ostream &operator<<(raw_ostream &OS, const RecTy &Ty) {	inline raw_ostream &operator<<(raw_ostream &OS, const RecTy &Ty) {
	Ty.print(OS);	Ty.print(OS);
	return OS;	return OS;
	}	}

	/// BitRecTy - 'bit' - Represent a single bit	/// BitRecTy - 'bit' - Represent a single bit

	skipping to change at line 146	skipping to change at line 144
	BitRecTy() {}	BitRecTy() {}
	public:	public:
	static BitRecTy *get() { return &Shared; }	static BitRecTy *get() { return &Shared; }

	virtual Init convertValue( UnsetInit UI) { return (Init*)UI; }	virtual Init convertValue( UnsetInit UI) { return (Init*)UI; }
	virtual Init convertValue( BitInit BI) { return (Init*)BI; }	virtual Init convertValue( BitInit BI) { return (Init*)BI; }
	virtual Init convertValue( BitsInit BI);	virtual Init convertValue( BitsInit BI);
	virtual Init convertValue( IntInit II);	virtual Init convertValue( IntInit II);
	virtual Init convertValue(StringInit SI) { return 0; }	virtual Init convertValue(StringInit SI) { return 0; }
	virtual Init convertValue( ListInit LI) { return 0; }	virtual Init convertValue( ListInit LI) { return 0; }

	virtual Init convertValue( CodeInit CI) { return 0; }
	virtual Init convertValue(VarBitInit VB) { return (Init*)VB; }	virtual Init convertValue(VarBitInit VB) { return (Init*)VB; }
	virtual Init convertValue( DefInit DI) { return 0; }	virtual Init convertValue( DefInit DI) { return 0; }
	virtual Init convertValue( DagInit DI) { return 0; }	virtual Init convertValue( DagInit DI) { return 0; }
	virtual Init convertValue( UnOpInit UI) { return RecTy::convertValue(UI );}	virtual Init convertValue( UnOpInit UI) { return RecTy::convertValue(UI );}
	virtual Init convertValue( BinOpInit UI) { return RecTy::convertValue(U I);}	virtual Init convertValue( BinOpInit UI) { return RecTy::convertValue(U I);}
	virtual Init convertValue( TernOpInit UI) { return RecTy::convertValue( UI);}	virtual Init convertValue( TernOpInit UI) { return RecTy::convertValue( UI);}
	virtual Init convertValue( TypedInit TI);	virtual Init convertValue( TypedInit TI);
	virtual Init convertValue( VarInit VI) { return RecTy::convertValue(V I);}	virtual Init convertValue( VarInit VI) { return RecTy::convertValue(V I);}
	virtual Init convertValue( FieldInit FI) { return RecTy::convertValue(F I);}	virtual Init convertValue( FieldInit FI) { return RecTy::convertValue(F I);}

	std::string getAsString() const { return "bit"; }	std::string getAsString() const { return "bit"; }

	bool typeIsConvertibleTo(const RecTy *RHS) const {	bool typeIsConvertibleTo(const RecTy *RHS) const {
	return RHS->baseClassOf(this);	return RHS->baseClassOf(this);
	}	}
	virtual bool baseClassOf(const BitRecTy *RHS) const { return true; }	virtual bool baseClassOf(const BitRecTy *RHS) const { return true; }
	virtual bool baseClassOf(const BitsRecTy *RHS) const;	virtual bool baseClassOf(const BitsRecTy *RHS) const;
	virtual bool baseClassOf(const IntRecTy *RHS) const { return true; }	virtual bool baseClassOf(const IntRecTy *RHS) const { return true; }
	virtual bool baseClassOf(const StringRecTy *RHS) const { return false; }	virtual bool baseClassOf(const StringRecTy *RHS) const { return false; }
	virtual bool baseClassOf(const ListRecTy *RHS) const { return false; }	virtual bool baseClassOf(const ListRecTy *RHS) const { return false; }

	virtual bool baseClassOf(const CodeRecTy *RHS) const { return false; }
	virtual bool baseClassOf(const DagRecTy *RHS) const { return false; }	virtual bool baseClassOf(const DagRecTy *RHS) const { return false; }
	virtual bool baseClassOf(const RecordRecTy *RHS) const { return false; }	virtual bool baseClassOf(const RecordRecTy *RHS) const { return false; }

	};	};

	// BitsRecTy - 'bits<n>' - Represent a fixed number of bits	// BitsRecTy - 'bits<n>' - Represent a fixed number of bits
	/// BitsRecTy - 'bits<n>' - Represent a fixed number of bits	/// BitsRecTy - 'bits<n>' - Represent a fixed number of bits
	///	///
	class BitsRecTy : public RecTy {	class BitsRecTy : public RecTy {
	unsigned Size;	unsigned Size;

	skipping to change at line 190	skipping to change at line 186
	static BitsRecTy *get(unsigned Sz);	static BitsRecTy *get(unsigned Sz);

	unsigned getNumBits() const { return Size; }	unsigned getNumBits() const { return Size; }

	virtual Init convertValue( UnsetInit UI);	virtual Init convertValue( UnsetInit UI);
	virtual Init convertValue( BitInit UI);	virtual Init convertValue( BitInit UI);
	virtual Init convertValue( BitsInit BI);	virtual Init convertValue( BitsInit BI);
	virtual Init convertValue( IntInit II);	virtual Init convertValue( IntInit II);
	virtual Init convertValue(StringInit SI) { return 0; }	virtual Init convertValue(StringInit SI) { return 0; }
	virtual Init convertValue( ListInit LI) { return 0; }	virtual Init convertValue( ListInit LI) { return 0; }

	virtual Init convertValue( CodeInit CI) { return 0; }
	virtual Init convertValue(VarBitInit VB) { return 0; }	virtual Init convertValue(VarBitInit VB) { return 0; }
	virtual Init convertValue( DefInit DI) { return 0; }	virtual Init convertValue( DefInit DI) { return 0; }
	virtual Init convertValue( DagInit DI) { return 0; }	virtual Init convertValue( DagInit DI) { return 0; }
	virtual Init convertValue( UnOpInit UI) { return RecTy::convertValue(UI );}	virtual Init convertValue( UnOpInit UI) { return RecTy::convertValue(UI );}
	virtual Init convertValue( BinOpInit UI) { return RecTy::convertValue(U I);}	virtual Init convertValue( BinOpInit UI) { return RecTy::convertValue(U I);}
	virtual Init convertValue( TernOpInit UI) { return RecTy::convertValue( UI);}	virtual Init convertValue( TernOpInit UI) { return RecTy::convertValue( UI);}
	virtual Init convertValue( TypedInit TI);	virtual Init convertValue( TypedInit TI);
	virtual Init convertValue( VarInit VI) { return RecTy::convertValue(V I);}	virtual Init convertValue( VarInit VI) { return RecTy::convertValue(V I);}
	virtual Init convertValue( FieldInit FI) { return RecTy::convertValue(F I);}	virtual Init convertValue( FieldInit FI) { return RecTy::convertValue(F I);}


	skipping to change at line 213	skipping to change at line 208
	bool typeIsConvertibleTo(const RecTy *RHS) const {	bool typeIsConvertibleTo(const RecTy *RHS) const {
	return RHS->baseClassOf(this);	return RHS->baseClassOf(this);
	}	}
	virtual bool baseClassOf(const BitRecTy *RHS) const { return Size == 1 ; }	virtual bool baseClassOf(const BitRecTy *RHS) const { return Size == 1 ; }
	virtual bool baseClassOf(const BitsRecTy *RHS) const {	virtual bool baseClassOf(const BitsRecTy *RHS) const {
	return RHS->Size == Size;	return RHS->Size == Size;
	}	}
	virtual bool baseClassOf(const IntRecTy *RHS) const { return true; }	virtual bool baseClassOf(const IntRecTy *RHS) const { return true; }
	virtual bool baseClassOf(const StringRecTy *RHS) const { return false; }	virtual bool baseClassOf(const StringRecTy *RHS) const { return false; }
	virtual bool baseClassOf(const ListRecTy *RHS) const { return false; }	virtual bool baseClassOf(const ListRecTy *RHS) const { return false; }

	virtual bool baseClassOf(const CodeRecTy *RHS) const { return false; }
	virtual bool baseClassOf(const DagRecTy *RHS) const { return false; }	virtual bool baseClassOf(const DagRecTy *RHS) const { return false; }
	virtual bool baseClassOf(const RecordRecTy *RHS) const { return false; }	virtual bool baseClassOf(const RecordRecTy *RHS) const { return false; }

	};	};

	/// IntRecTy - 'int' - Represent an integer value of no particular size	/// IntRecTy - 'int' - Represent an integer value of no particular size
	///	///
	class IntRecTy : public RecTy {	class IntRecTy : public RecTy {
	static IntRecTy Shared;	static IntRecTy Shared;
	IntRecTy() {}	IntRecTy() {}
	public:	public:
	static IntRecTy *get() { return &Shared; }	static IntRecTy *get() { return &Shared; }

	virtual Init convertValue( UnsetInit UI) { return (Init*)UI; }	virtual Init convertValue( UnsetInit UI) { return (Init*)UI; }
	virtual Init convertValue( BitInit BI);	virtual Init convertValue( BitInit BI);
	virtual Init convertValue( BitsInit BI);	virtual Init convertValue( BitsInit BI);
	virtual Init convertValue( IntInit II) { return (Init*)II; }	virtual Init convertValue( IntInit II) { return (Init*)II; }
	virtual Init convertValue(StringInit SI) { return 0; }	virtual Init convertValue(StringInit SI) { return 0; }
	virtual Init convertValue( ListInit LI) { return 0; }	virtual Init convertValue( ListInit LI) { return 0; }

	virtual Init convertValue( CodeInit CI) { return 0; }
	virtual Init convertValue(VarBitInit VB) { return 0; }	virtual Init convertValue(VarBitInit VB) { return 0; }
	virtual Init convertValue( DefInit DI) { return 0; }	virtual Init convertValue( DefInit DI) { return 0; }
	virtual Init convertValue( DagInit DI) { return 0; }	virtual Init convertValue( DagInit DI) { return 0; }
	virtual Init convertValue( UnOpInit UI) { return RecTy::convertValue(UI );}	virtual Init convertValue( UnOpInit UI) { return RecTy::convertValue(UI );}
	virtual Init convertValue( BinOpInit UI) { return RecTy::convertValue(U I);}	virtual Init convertValue( BinOpInit UI) { return RecTy::convertValue(U I);}
	virtual Init convertValue( TernOpInit UI) { return RecTy::convertValue( UI);}	virtual Init convertValue( TernOpInit UI) { return RecTy::convertValue( UI);}
	virtual Init convertValue( TypedInit TI);	virtual Init convertValue( TypedInit TI);
	virtual Init convertValue( VarInit VI) { return RecTy::convertValue(V I);}	virtual Init convertValue( VarInit VI) { return RecTy::convertValue(V I);}
	virtual Init convertValue( FieldInit FI) { return RecTy::convertValue(F I);}	virtual Init convertValue( FieldInit FI) { return RecTy::convertValue(F I);}


	skipping to change at line 255	skipping to change at line 248

	bool typeIsConvertibleTo(const RecTy *RHS) const {	bool typeIsConvertibleTo(const RecTy *RHS) const {
	return RHS->baseClassOf(this);	return RHS->baseClassOf(this);
	}	}

	virtual bool baseClassOf(const BitRecTy *RHS) const { return true; }	virtual bool baseClassOf(const BitRecTy *RHS) const { return true; }
	virtual bool baseClassOf(const BitsRecTy *RHS) const { return true; }	virtual bool baseClassOf(const BitsRecTy *RHS) const { return true; }
	virtual bool baseClassOf(const IntRecTy *RHS) const { return true; }	virtual bool baseClassOf(const IntRecTy *RHS) const { return true; }
	virtual bool baseClassOf(const StringRecTy *RHS) const { return false; }	virtual bool baseClassOf(const StringRecTy *RHS) const { return false; }
	virtual bool baseClassOf(const ListRecTy *RHS) const { return false; }	virtual bool baseClassOf(const ListRecTy *RHS) const { return false; }

	virtual bool baseClassOf(const CodeRecTy *RHS) const { return false; }
	virtual bool baseClassOf(const DagRecTy *RHS) const { return false; }	virtual bool baseClassOf(const DagRecTy *RHS) const { return false; }
	virtual bool baseClassOf(const RecordRecTy *RHS) const { return false; }	virtual bool baseClassOf(const RecordRecTy *RHS) const { return false; }

	};	};

	/// StringRecTy - 'string' - Represent an string value	/// StringRecTy - 'string' - Represent an string value
	///	///
	class StringRecTy : public RecTy {	class StringRecTy : public RecTy {
	static StringRecTy Shared;	static StringRecTy Shared;
	StringRecTy() {}	StringRecTy() {}

	skipping to change at line 279	skipping to change at line 271
	virtual Init convertValue( UnsetInit UI) { return (Init*)UI; }	virtual Init convertValue( UnsetInit UI) { return (Init*)UI; }
	virtual Init convertValue( BitInit BI) { return 0; }	virtual Init convertValue( BitInit BI) { return 0; }
	virtual Init convertValue( BitsInit BI) { return 0; }	virtual Init convertValue( BitsInit BI) { return 0; }
	virtual Init convertValue( IntInit II) { return 0; }	virtual Init convertValue( IntInit II) { return 0; }
	virtual Init convertValue(StringInit SI) { return (Init*)SI; }	virtual Init convertValue(StringInit SI) { return (Init*)SI; }
	virtual Init convertValue( ListInit LI) { return 0; }	virtual Init convertValue( ListInit LI) { return 0; }
	virtual Init convertValue( UnOpInit BO);	virtual Init convertValue( UnOpInit BO);
	virtual Init convertValue( BinOpInit BO);	virtual Init convertValue( BinOpInit BO);
	virtual Init convertValue( TernOpInit BO) { return RecTy::convertValue( BO);}	virtual Init convertValue( TernOpInit BO) { return RecTy::convertValue( BO);}


	virtual Init convertValue( CodeInit CI) { return 0; }
	virtual Init convertValue(VarBitInit VB) { return 0; }	virtual Init convertValue(VarBitInit VB) { return 0; }
	virtual Init convertValue( DefInit DI) { return 0; }	virtual Init convertValue( DefInit DI) { return 0; }
	virtual Init convertValue( DagInit DI) { return 0; }	virtual Init convertValue( DagInit DI) { return 0; }
	virtual Init convertValue( TypedInit TI);	virtual Init convertValue( TypedInit TI);
	virtual Init convertValue( VarInit VI) { return RecTy::convertValue(V I);}	virtual Init convertValue( VarInit VI) { return RecTy::convertValue(V I);}
	virtual Init convertValue( FieldInit FI) { return RecTy::convertValue(F I);}	virtual Init convertValue( FieldInit FI) { return RecTy::convertValue(F I);}

	std::string getAsString() const { return "string"; }	std::string getAsString() const { return "string"; }

	bool typeIsConvertibleTo(const RecTy *RHS) const {	bool typeIsConvertibleTo(const RecTy *RHS) const {
	return RHS->baseClassOf(this);	return RHS->baseClassOf(this);
	}	}

	virtual bool baseClassOf(const BitRecTy *RHS) const { return false; }	virtual bool baseClassOf(const BitRecTy *RHS) const { return false; }
	virtual bool baseClassOf(const BitsRecTy *RHS) const { return false; }	virtual bool baseClassOf(const BitsRecTy *RHS) const { return false; }
	virtual bool baseClassOf(const IntRecTy *RHS) const { return false; }	virtual bool baseClassOf(const IntRecTy *RHS) const { return false; }
	virtual bool baseClassOf(const StringRecTy *RHS) const { return true; }	virtual bool baseClassOf(const StringRecTy *RHS) const { return true; }
	virtual bool baseClassOf(const ListRecTy *RHS) const { return false; }	virtual bool baseClassOf(const ListRecTy *RHS) const { return false; }

	virtual bool baseClassOf(const CodeRecTy *RHS) const { return false; }
	virtual bool baseClassOf(const DagRecTy *RHS) const { return false; }	virtual bool baseClassOf(const DagRecTy *RHS) const { return false; }
	virtual bool baseClassOf(const RecordRecTy *RHS) const { return false; }	virtual bool baseClassOf(const RecordRecTy *RHS) const { return false; }
	};	};

	// ListRecTy - 'list<Ty>' - Represent a list of values, all of which must b e of	// ListRecTy - 'list<Ty>' - Represent a list of values, all of which must b e of
	// the specified type.	// the specified type.
	/// ListRecTy - 'list<Ty>' - Represent a list of values, all of which must	/// ListRecTy - 'list<Ty>' - Represent a list of values, all of which must
	/// be of the specified type.	/// be of the specified type.
	///	///
	class ListRecTy : public RecTy {	class ListRecTy : public RecTy {

	skipping to change at line 322	skipping to change at line 312
	public:	public:
	static ListRecTy get(RecTy T) { return T->getListTy(); }	static ListRecTy get(RecTy T) { return T->getListTy(); }
	RecTy *getElementType() const { return Ty; }	RecTy *getElementType() const { return Ty; }

	virtual Init convertValue( UnsetInit UI) { return (Init*)UI; }	virtual Init convertValue( UnsetInit UI) { return (Init*)UI; }
	virtual Init convertValue( BitInit BI) { return 0; }	virtual Init convertValue( BitInit BI) { return 0; }
	virtual Init convertValue( BitsInit BI) { return 0; }	virtual Init convertValue( BitsInit BI) { return 0; }
	virtual Init convertValue( IntInit II) { return 0; }	virtual Init convertValue( IntInit II) { return 0; }
	virtual Init convertValue(StringInit SI) { return 0; }	virtual Init convertValue(StringInit SI) { return 0; }
	virtual Init convertValue( ListInit LI);	virtual Init convertValue( ListInit LI);

	virtual Init convertValue( CodeInit CI) { return 0; }
	virtual Init convertValue(VarBitInit VB) { return 0; }	virtual Init convertValue(VarBitInit VB) { return 0; }
	virtual Init convertValue( DefInit DI) { return 0; }	virtual Init convertValue( DefInit DI) { return 0; }
	virtual Init convertValue( DagInit DI) { return 0; }	virtual Init convertValue( DagInit DI) { return 0; }
	virtual Init convertValue( UnOpInit UI) { return RecTy::convertValue(UI );}	virtual Init convertValue( UnOpInit UI) { return RecTy::convertValue(UI );}
	virtual Init convertValue( BinOpInit UI) { return RecTy::convertValue(U I);}	virtual Init convertValue( BinOpInit UI) { return RecTy::convertValue(U I);}
	virtual Init convertValue( TernOpInit UI) { return RecTy::convertValue( UI);}	virtual Init convertValue( TernOpInit UI) { return RecTy::convertValue( UI);}
	virtual Init convertValue( TypedInit TI);	virtual Init convertValue( TypedInit TI);
	virtual Init convertValue( VarInit VI) { return RecTy::convertValue(V I);}	virtual Init convertValue( VarInit VI) { return RecTy::convertValue(V I);}
	virtual Init convertValue( FieldInit FI) { return RecTy::convertValue(F I);}	virtual Init convertValue( FieldInit FI) { return RecTy::convertValue(F I);}


	skipping to change at line 346	skipping to change at line 335
	return RHS->baseClassOf(this);	return RHS->baseClassOf(this);
	}	}

	virtual bool baseClassOf(const BitRecTy *RHS) const { return false; }	virtual bool baseClassOf(const BitRecTy *RHS) const { return false; }
	virtual bool baseClassOf(const BitsRecTy *RHS) const { return false; }	virtual bool baseClassOf(const BitsRecTy *RHS) const { return false; }
	virtual bool baseClassOf(const IntRecTy *RHS) const { return false; }	virtual bool baseClassOf(const IntRecTy *RHS) const { return false; }
	virtual bool baseClassOf(const StringRecTy *RHS) const { return false; }	virtual bool baseClassOf(const StringRecTy *RHS) const { return false; }
	virtual bool baseClassOf(const ListRecTy *RHS) const {	virtual bool baseClassOf(const ListRecTy *RHS) const {
	return RHS->getElementType()->typeIsConvertibleTo(Ty);	return RHS->getElementType()->typeIsConvertibleTo(Ty);
	}	}

	virtual bool baseClassOf(const CodeRecTy *RHS) const { return false; }
	virtual bool baseClassOf(const DagRecTy *RHS) const { return false; }
	virtual bool baseClassOf(const RecordRecTy *RHS) const { return false; }
	};

	/// CodeRecTy - 'code' - Represent an code fragment, function or method.
	///
	class CodeRecTy : public RecTy {
	static CodeRecTy Shared;
	CodeRecTy() {}
	public:
	static CodeRecTy *get() { return &Shared; }

	virtual Init convertValue( UnsetInit UI) { return (Init*)UI; }
	virtual Init convertValue( BitInit BI) { return 0; }
	virtual Init convertValue( BitsInit BI) { return 0; }
	virtual Init convertValue( IntInit II) { return 0; }
	virtual Init convertValue(StringInit SI) { return 0; }
	virtual Init convertValue( ListInit LI) { return 0; }
	virtual Init convertValue( CodeInit CI) { return (Init*)CI; }
	virtual Init convertValue(VarBitInit VB) { return 0; }
	virtual Init convertValue( DefInit DI) { return 0; }
	virtual Init convertValue( DagInit DI) { return 0; }
	virtual Init convertValue( UnOpInit UI) { return RecTy::convertValue(UI
	);}
	virtual Init convertValue( BinOpInit UI) { return RecTy::convertValue(U
	I);}
	virtual Init convertValue( TernOpInit UI) { return RecTy::convertValue(
	UI);}
	virtual Init convertValue( TypedInit TI);
	virtual Init convertValue( VarInit VI) { return RecTy::convertValue(V
	I);}
	virtual Init convertValue( FieldInit FI) { return RecTy::convertValue(F
	I);}

	std::string getAsString() const { return "code"; }

	bool typeIsConvertibleTo(const RecTy *RHS) const {
	return RHS->baseClassOf(this);
	}
	virtual bool baseClassOf(const BitRecTy *RHS) const { return false; }
	virtual bool baseClassOf(const BitsRecTy *RHS) const { return false; }
	virtual bool baseClassOf(const IntRecTy *RHS) const { return false; }
	virtual bool baseClassOf(const StringRecTy *RHS) const { return false; }
	virtual bool baseClassOf(const ListRecTy *RHS) const { return false; }
	virtual bool baseClassOf(const CodeRecTy *RHS) const { return true; }
	virtual bool baseClassOf(const DagRecTy *RHS) const { return false; }	virtual bool baseClassOf(const DagRecTy *RHS) const { return false; }
	virtual bool baseClassOf(const RecordRecTy *RHS) const { return false; }	virtual bool baseClassOf(const RecordRecTy *RHS) const { return false; }
	};	};

	/// DagRecTy - 'dag' - Represent a dag fragment	/// DagRecTy - 'dag' - Represent a dag fragment
	///	///
	class DagRecTy : public RecTy {	class DagRecTy : public RecTy {
	static DagRecTy Shared;	static DagRecTy Shared;
	DagRecTy() {}	DagRecTy() {}
	public:	public:
	static DagRecTy *get() { return &Shared; }	static DagRecTy *get() { return &Shared; }

	virtual Init convertValue( UnsetInit UI) { return (Init*)UI; }	virtual Init convertValue( UnsetInit UI) { return (Init*)UI; }
	virtual Init convertValue( BitInit BI) { return 0; }	virtual Init convertValue( BitInit BI) { return 0; }
	virtual Init convertValue( BitsInit BI) { return 0; }	virtual Init convertValue( BitsInit BI) { return 0; }
	virtual Init convertValue( IntInit II) { return 0; }	virtual Init convertValue( IntInit II) { return 0; }
	virtual Init convertValue(StringInit SI) { return 0; }	virtual Init convertValue(StringInit SI) { return 0; }
	virtual Init convertValue( ListInit LI) { return 0; }	virtual Init convertValue( ListInit LI) { return 0; }

	virtual Init convertValue( CodeInit CI) { return 0; }
	virtual Init convertValue(VarBitInit VB) { return 0; }	virtual Init convertValue(VarBitInit VB) { return 0; }
	virtual Init convertValue( DefInit DI) { return 0; }	virtual Init convertValue( DefInit DI) { return 0; }
	virtual Init convertValue( UnOpInit BO);	virtual Init convertValue( UnOpInit BO);
	virtual Init convertValue( BinOpInit BO);	virtual Init convertValue( BinOpInit BO);
	virtual Init convertValue( TernOpInit BO) { return RecTy::convertValue( BO);}	virtual Init convertValue( TernOpInit BO) { return RecTy::convertValue( BO);}
	virtual Init convertValue( DagInit CI) { return (Init*)CI; }	virtual Init convertValue( DagInit CI) { return (Init*)CI; }
	virtual Init convertValue( TypedInit TI);	virtual Init convertValue( TypedInit TI);
	virtual Init convertValue( VarInit VI) { return RecTy::convertValue(V I);}	virtual Init convertValue( VarInit VI) { return RecTy::convertValue(V I);}
	virtual Init convertValue( FieldInit FI) { return RecTy::convertValue(F I);}	virtual Init convertValue( FieldInit FI) { return RecTy::convertValue(F I);}


	skipping to change at line 427	skipping to change at line 374

	bool typeIsConvertibleTo(const RecTy *RHS) const {	bool typeIsConvertibleTo(const RecTy *RHS) const {
	return RHS->baseClassOf(this);	return RHS->baseClassOf(this);
	}	}

	virtual bool baseClassOf(const BitRecTy *RHS) const { return false; }	virtual bool baseClassOf(const BitRecTy *RHS) const { return false; }
	virtual bool baseClassOf(const BitsRecTy *RHS) const { return false; }	virtual bool baseClassOf(const BitsRecTy *RHS) const { return false; }
	virtual bool baseClassOf(const IntRecTy *RHS) const { return false; }	virtual bool baseClassOf(const IntRecTy *RHS) const { return false; }
	virtual bool baseClassOf(const StringRecTy *RHS) const { return false; }	virtual bool baseClassOf(const StringRecTy *RHS) const { return false; }
	virtual bool baseClassOf(const ListRecTy *RHS) const { return false; }	virtual bool baseClassOf(const ListRecTy *RHS) const { return false; }

	virtual bool baseClassOf(const CodeRecTy *RHS) const { return false; }
	virtual bool baseClassOf(const DagRecTy *RHS) const { return true; }	virtual bool baseClassOf(const DagRecTy *RHS) const { return true; }
	virtual bool baseClassOf(const RecordRecTy *RHS) const { return false; }	virtual bool baseClassOf(const RecordRecTy *RHS) const { return false; }
	};	};

	/// RecordRecTy - '[classname]' - Represent an instance of a class, such as :	/// RecordRecTy - '[classname]' - Represent an instance of a class, such as :
	/// (R32 X = EAX).	/// (R32 X = EAX).
	///	///
	class RecordRecTy : public RecTy {	class RecordRecTy : public RecTy {
	Record *Rec;	Record *Rec;
	explicit RecordRecTy(Record *R) : Rec(R) {}	explicit RecordRecTy(Record *R) : Rec(R) {}

	skipping to change at line 450	skipping to change at line 396
	static RecordRecTy get(Record R);	static RecordRecTy get(Record R);

	Record *getRecord() const { return Rec; }	Record *getRecord() const { return Rec; }

	virtual Init convertValue( UnsetInit UI) { return (Init*)UI; }	virtual Init convertValue( UnsetInit UI) { return (Init*)UI; }
	virtual Init convertValue( BitInit BI) { return 0; }	virtual Init convertValue( BitInit BI) { return 0; }
	virtual Init convertValue( BitsInit BI) { return 0; }	virtual Init convertValue( BitsInit BI) { return 0; }
	virtual Init convertValue( IntInit II) { return 0; }	virtual Init convertValue( IntInit II) { return 0; }
	virtual Init convertValue(StringInit SI) { return 0; }	virtual Init convertValue(StringInit SI) { return 0; }
	virtual Init convertValue( ListInit LI) { return 0; }	virtual Init convertValue( ListInit LI) { return 0; }

	virtual Init convertValue( CodeInit CI) { return 0; }
	virtual Init convertValue(VarBitInit VB) { return 0; }	virtual Init convertValue(VarBitInit VB) { return 0; }
	virtual Init convertValue( UnOpInit UI) { return RecTy::convertValue(UI );}	virtual Init convertValue( UnOpInit UI) { return RecTy::convertValue(UI );}
	virtual Init convertValue( BinOpInit UI) { return RecTy::convertValue(U I);}	virtual Init convertValue( BinOpInit UI) { return RecTy::convertValue(U I);}
	virtual Init convertValue( TernOpInit UI) { return RecTy::convertValue( UI);}	virtual Init convertValue( TernOpInit UI) { return RecTy::convertValue( UI);}
	virtual Init convertValue( DefInit DI);	virtual Init convertValue( DefInit DI);
	virtual Init convertValue( DagInit DI) { return 0; }	virtual Init convertValue( DagInit DI) { return 0; }
	virtual Init convertValue( TypedInit VI);	virtual Init convertValue( TypedInit VI);
	virtual Init convertValue( VarInit VI) { return RecTy::convertValue(V I);}	virtual Init convertValue( VarInit VI) { return RecTy::convertValue(V I);}
	virtual Init convertValue( FieldInit FI) { return RecTy::convertValue(F I);}	virtual Init convertValue( FieldInit FI) { return RecTy::convertValue(F I);}

	std::string getAsString() const;	std::string getAsString() const;

	bool typeIsConvertibleTo(const RecTy *RHS) const {	bool typeIsConvertibleTo(const RecTy *RHS) const {
	return RHS->baseClassOf(this);	return RHS->baseClassOf(this);
	}	}
	virtual bool baseClassOf(const BitRecTy *RHS) const { return false; }	virtual bool baseClassOf(const BitRecTy *RHS) const { return false; }
	virtual bool baseClassOf(const BitsRecTy *RHS) const { return false; }	virtual bool baseClassOf(const BitsRecTy *RHS) const { return false; }
	virtual bool baseClassOf(const IntRecTy *RHS) const { return false; }	virtual bool baseClassOf(const IntRecTy *RHS) const { return false; }
	virtual bool baseClassOf(const StringRecTy *RHS) const { return false; }	virtual bool baseClassOf(const StringRecTy *RHS) const { return false; }
	virtual bool baseClassOf(const ListRecTy *RHS) const { return false; }	virtual bool baseClassOf(const ListRecTy *RHS) const { return false; }

	virtual bool baseClassOf(const CodeRecTy *RHS) const { return false; }
	virtual bool baseClassOf(const DagRecTy *RHS) const { return false; }	virtual bool baseClassOf(const DagRecTy *RHS) const { return false; }
	virtual bool baseClassOf(const RecordRecTy *RHS) const;	virtual bool baseClassOf(const RecordRecTy *RHS) const;
	};	};

	/// resolveTypes - Find a common type that T1 and T2 convert to.	/// resolveTypes - Find a common type that T1 and T2 convert to.
	/// Return 0 if no such type exists.	/// Return 0 if no such type exists.
	///	///
	RecTy resolveTypes(RecTy T1, RecTy *T2);	RecTy resolveTypes(RecTy T1, RecTy *T2);

	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	// Initializer Classes	// Initializer Classes
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	class Init {	class Init {
	Init(const Init &); // Do not define.	Init(const Init &); // Do not define.
	Init &operator=(const Init &); // Do not define.	Init &operator=(const Init &); // Do not define.

		virtual void anchor();

	protected:	protected:
	Init(void) {}	Init(void) {}

	public:	public:
	virtual ~Init() {}	virtual ~Init() {}

	/// isComplete - This virtual method should be overridden by values that may	/// isComplete - This virtual method should be overridden by values that may
	/// not be completely specified yet.	/// not be completely specified yet.
	virtual bool isComplete() const { return true; }	virtual bool isComplete() const { return true; }

	skipping to change at line 615	skipping to change at line 560
	virtual Init resolveListElementReference(Record &R, const RecordVal RV,	virtual Init resolveListElementReference(Record &R, const RecordVal RV,
	unsigned Elt) const = 0;	unsigned Elt) const = 0;
	};	};

	/// UnsetInit - ? - Represents an uninitialized value	/// UnsetInit - ? - Represents an uninitialized value
	///	///
	class UnsetInit : public Init {	class UnsetInit : public Init {
	UnsetInit() : Init() {}	UnsetInit() : Init() {}
	UnsetInit(const UnsetInit &); // Do not define.	UnsetInit(const UnsetInit &); // Do not define.
	UnsetInit &operator=(const UnsetInit &Other); // Do not define.	UnsetInit &operator=(const UnsetInit &Other); // Do not define.

		virtual void anchor();

	public:	public:
	static UnsetInit *get();	static UnsetInit *get();

	virtual Init convertInitializerTo(RecTy Ty) const {	virtual Init convertInitializerTo(RecTy Ty) const {
	return Ty->convertValue(const_cast<UnsetInit *>(this));	return Ty->convertValue(const_cast<UnsetInit *>(this));
	}	}

	virtual bool isComplete() const { return false; }	virtual bool isComplete() const { return false; }
	virtual std::string getAsString() const { return "?"; }	virtual std::string getAsString() const { return "?"; }
	};	};

	/// BitInit - true/false - Represent a concrete initializer for a bit.	/// BitInit - true/false - Represent a concrete initializer for a bit.
	///	///
	class BitInit : public Init {	class BitInit : public Init {
	bool Value;	bool Value;

	explicit BitInit(bool V) : Value(V) {}	explicit BitInit(bool V) : Value(V) {}
	BitInit(const BitInit &Other); // Do not define.	BitInit(const BitInit &Other); // Do not define.
	BitInit &operator=(BitInit &Other); // Do not define.	BitInit &operator=(BitInit &Other); // Do not define.

		virtual void anchor();

	public:	public:
	static BitInit *get(bool V);	static BitInit *get(bool V);

	bool getValue() const { return Value; }	bool getValue() const { return Value; }

	virtual Init convertInitializerTo(RecTy Ty) const {	virtual Init convertInitializerTo(RecTy Ty) const {
	return Ty->convertValue(const_cast<BitInit *>(this));	return Ty->convertValue(const_cast<BitInit *>(this));
	}	}


	skipping to change at line 721	skipping to change at line 668
	convertInitializerBitRange(const std::vector<unsigned> &Bits) const;	convertInitializerBitRange(const std::vector<unsigned> &Bits) const;

	virtual std::string getAsString() const;	virtual std::string getAsString() const;

	/// resolveBitReference - This method is used to implement	/// resolveBitReference - This method is used to implement
	/// VarBitInit::resolveReferences. If the bit is able to be resolved, we	/// VarBitInit::resolveReferences. If the bit is able to be resolved, we
	/// simply return the resolved value, otherwise we return null.	/// simply return the resolved value, otherwise we return null.
	///	///
	virtual Init resolveBitReference(Record &R, const RecordVal RV,	virtual Init resolveBitReference(Record &R, const RecordVal RV,
	unsigned Bit) const {	unsigned Bit) const {

	assert(0 && "Illegal bit reference off int");	llvm_unreachable("Illegal bit reference off int");
	return 0;
	}	}

	/// resolveListElementReference - This method is used to implement	/// resolveListElementReference - This method is used to implement
	/// VarListElementInit::resolveReferences. If the list element is resolv able	/// VarListElementInit::resolveReferences. If the list element is resolv able
	/// now, we return the resolved value, otherwise we return null.	/// now, we return the resolved value, otherwise we return null.
	virtual Init resolveListElementReference(Record &R, const RecordVal RV,	virtual Init resolveListElementReference(Record &R, const RecordVal RV,
	unsigned Elt) const {	unsigned Elt) const {

	assert(0 && "Illegal element reference off int");	llvm_unreachable("Illegal element reference off int");
	return 0;
	}	}
	};	};

	/// StringInit - "foo" - Represent an initialization by a string value.	/// StringInit - "foo" - Represent an initialization by a string value.
	///	///
	class StringInit : public TypedInit {	class StringInit : public TypedInit {
	std::string Value;	std::string Value;

	explicit StringInit(const std::string &V)	explicit StringInit(const std::string &V)
	: TypedInit(StringRecTy::get()), Value(V) {}	: TypedInit(StringRecTy::get()), Value(V) {}

	StringInit(const StringInit &Other); // Do not define.	StringInit(const StringInit &Other); // Do not define.
	StringInit &operator=(const StringInit &Other); // Do not define.	StringInit &operator=(const StringInit &Other); // Do not define.

		virtual void anchor();

	public:	public:

	static StringInit *get(const std::string &V);	static StringInit *get(StringRef);

	const std::string &getValue() const { return Value; }	const std::string &getValue() const { return Value; }

	virtual Init convertInitializerTo(RecTy Ty) const {	virtual Init convertInitializerTo(RecTy Ty) const {
	return Ty->convertValue(const_cast<StringInit *>(this));	return Ty->convertValue(const_cast<StringInit *>(this));
	}	}

	virtual std::string getAsString() const { return "\"" + Value + "\""; }	virtual std::string getAsString() const { return "\"" + Value + "\""; }
	virtual std::string getAsUnquotedString() const { return Value; }	virtual std::string getAsUnquotedString() const { return Value; }

	/// resolveBitReference - This method is used to implement	/// resolveBitReference - This method is used to implement
	/// VarBitInit::resolveReferences. If the bit is able to be resolved, we	/// VarBitInit::resolveReferences. If the bit is able to be resolved, we
	/// simply return the resolved value, otherwise we return null.	/// simply return the resolved value, otherwise we return null.
	///	///
	virtual Init resolveBitReference(Record &R, const RecordVal RV,	virtual Init resolveBitReference(Record &R, const RecordVal RV,
	unsigned Bit) const {	unsigned Bit) const {

	assert(0 && "Illegal bit reference off string");	llvm_unreachable("Illegal bit reference off string");
	return 0;
	}	}

	/// resolveListElementReference - This method is used to implement	/// resolveListElementReference - This method is used to implement
	/// VarListElementInit::resolveReferences. If the list element is resolv able	/// VarListElementInit::resolveReferences. If the list element is resolv able
	/// now, we return the resolved value, otherwise we return null.	/// now, we return the resolved value, otherwise we return null.
	virtual Init resolveListElementReference(Record &R, const RecordVal RV,	virtual Init resolveListElementReference(Record &R, const RecordVal RV,
	unsigned Elt) const {	unsigned Elt) const {

	assert(0 && "Illegal element reference off string");	llvm_unreachable("Illegal element reference off string");
	return 0;
	}
	};

	/// CodeInit - "[{...}]" - Represent a code fragment.
	///
	class CodeInit : public Init {
	std::string Value;

	explicit CodeInit(const std::string &V) : Value(V) {}

	CodeInit(const CodeInit &Other); // Do not define.
	CodeInit &operator=(const CodeInit &Other); // Do not define.

	public:
	static CodeInit *get(const std::string &V);

	const std::string &getValue() const { return Value; }

	virtual Init convertInitializerTo(RecTy Ty) const {
	return Ty->convertValue(const_cast<CodeInit *>(this));
	}	}


	virtual std::string getAsString() const { return "[{" + Value + "}]"; }
	};	};

	/// ListInit - [AL, AH, CL] - Represent a list of defs	/// ListInit - [AL, AH, CL] - Represent a list of defs
	///	///
	class ListInit : public TypedInit, public FoldingSetNode {	class ListInit : public TypedInit, public FoldingSetNode {
	std::vector<Init*> Values;	std::vector<Init*> Values;
	public:	public:
	typedef std::vector<Init*>::const_iterator const_iterator;	typedef std::vector<Init*>::const_iterator const_iterator;

	private:	private:

	skipping to change at line 856	skipping to change at line 778

	inline size_t size () const { return Values.size(); }	inline size_t size () const { return Values.size(); }
	inline bool empty() const { return Values.empty(); }	inline bool empty() const { return Values.empty(); }

	/// resolveBitReference - This method is used to implement	/// resolveBitReference - This method is used to implement
	/// VarBitInit::resolveReferences. If the bit is able to be resolved, we	/// VarBitInit::resolveReferences. If the bit is able to be resolved, we
	/// simply return the resolved value, otherwise we return null.	/// simply return the resolved value, otherwise we return null.
	///	///
	virtual Init resolveBitReference(Record &R, const RecordVal RV,	virtual Init resolveBitReference(Record &R, const RecordVal RV,
	unsigned Bit) const {	unsigned Bit) const {

	assert(0 && "Illegal bit reference off list");	llvm_unreachable("Illegal bit reference off list");
	return 0;
	}	}

	/// resolveListElementReference - This method is used to implement	/// resolveListElementReference - This method is used to implement
	/// VarListElementInit::resolveReferences. If the list element is resolv able	/// VarListElementInit::resolveReferences. If the list element is resolv able
	/// now, we return the resolved value, otherwise we return null.	/// now, we return the resolved value, otherwise we return null.
	virtual Init resolveListElementReference(Record &R, const RecordVal RV,	virtual Init resolveListElementReference(Record &R, const RecordVal RV,
	unsigned Elt) const;	unsigned Elt) const;
	};	};

	/// OpInit - Base class for operators	/// OpInit - Base class for operators

	skipping to change at line 1050	skipping to change at line 971
	virtual bool isComplete() const { return false; }	virtual bool isComplete() const { return false; }

	virtual Init resolveReferences(Record &R, const RecordVal RV) const;	virtual Init resolveReferences(Record &R, const RecordVal RV) const;

	virtual std::string getAsString() const;	virtual std::string getAsString() const;
	};	};

	/// VarInit - 'Opcode' - Represent a reference to an entire variable object .	/// VarInit - 'Opcode' - Represent a reference to an entire variable object .
	///	///
	class VarInit : public TypedInit {	class VarInit : public TypedInit {

	std::string VarName;	Init *VarName;

	explicit VarInit(const std::string &VN, RecTy *T)	explicit VarInit(const std::string &VN, RecTy *T)

		: TypedInit(T), VarName(StringInit::get(VN)) {}
		explicit VarInit(Init VN, RecTy T)
	: TypedInit(T), VarName(VN) {}	: TypedInit(T), VarName(VN) {}

	VarInit(const VarInit &Other); // Do not define.	VarInit(const VarInit &Other); // Do not define.
	VarInit &operator=(const VarInit &Other); // Do not define.	VarInit &operator=(const VarInit &Other); // Do not define.

	public:	public:
	static VarInit get(const std::string &VN, RecTy T);	static VarInit get(const std::string &VN, RecTy T);
	static VarInit get(Init VN, RecTy *T);	static VarInit get(Init VN, RecTy *T);

	virtual Init convertInitializerTo(RecTy Ty) const {	virtual Init convertInitializerTo(RecTy Ty) const {
	return Ty->convertValue(const_cast<VarInit *>(this));	return Ty->convertValue(const_cast<VarInit *>(this));
	}	}


	const std::string &getName() const { return VarName; }	const std::string &getName() const;
		Init *getNameInit() const { return VarName; }
		std::string getNameInitAsString() const {
		return getNameInit()->getAsUnquotedString();
		}

	virtual Init resolveBitReference(Record &R, const RecordVal RV,	virtual Init resolveBitReference(Record &R, const RecordVal RV,
	unsigned Bit) const;	unsigned Bit) const;
	virtual Init resolveListElementReference(Record &R, const RecordVal RV,	virtual Init resolveListElementReference(Record &R, const RecordVal RV,
	unsigned Elt) const;	unsigned Elt) const;

	virtual RecTy *getFieldType(const std::string &FieldName) const;	virtual RecTy *getFieldType(const std::string &FieldName) const;
	virtual Init getFieldInit(Record &R, const RecordVal RV,	virtual Init getFieldInit(Record &R, const RecordVal RV,
	const std::string &FieldName) const;	const std::string &FieldName) const;

	/// resolveReferences - This method is used by classes that refer to othe r	/// resolveReferences - This method is used by classes that refer to othe r
	/// variables which may not be defined at the time they expression is for med.	/// variables which may not be defined at the time they expression is for med.
	/// If a value is set for the variable later, this method will be called on	/// If a value is set for the variable later, this method will be called on
	/// users of the value to allow the value to propagate out.	/// users of the value to allow the value to propagate out.
	///	///
	virtual Init resolveReferences(Record &R, const RecordVal RV) const;	virtual Init resolveReferences(Record &R, const RecordVal RV) const;


	virtual std::string getAsString() const { return VarName; }	virtual std::string getAsString() const { return getName(); }
	};	};

	/// VarBitInit - Opcode{0} - Represent access to one bit of a variable or f ield.	/// VarBitInit - Opcode{0} - Represent access to one bit of a variable or f ield.
	///	///
	class VarBitInit : public Init {	class VarBitInit : public Init {
	TypedInit *TI;	TypedInit *TI;
	unsigned Bit;	unsigned Bit;

	VarBitInit(TypedInit *T, unsigned B) : TI(T), Bit(B) {	VarBitInit(TypedInit *T, unsigned B) : TI(T), Bit(B) {
	assert(T->getType() && dynamic_cast<BitsRecTy*>(T->getType()) &&	assert(T->getType() && dynamic_cast<BitsRecTy*>(T->getType()) &&

	skipping to change at line 1192	skipping to change at line 1119
	const std::string &FieldName) const;	const std::string &FieldName) const;

	virtual std::string getAsString() const;	virtual std::string getAsString() const;

	/// resolveBitReference - This method is used to implement	/// resolveBitReference - This method is used to implement
	/// VarBitInit::resolveReferences. If the bit is able to be resolved, we	/// VarBitInit::resolveReferences. If the bit is able to be resolved, we
	/// simply return the resolved value, otherwise we return null.	/// simply return the resolved value, otherwise we return null.
	///	///
	virtual Init resolveBitReference(Record &R, const RecordVal RV,	virtual Init resolveBitReference(Record &R, const RecordVal RV,
	unsigned Bit) const {	unsigned Bit) const {

	assert(0 && "Illegal bit reference off def");	llvm_unreachable("Illegal bit reference off def");
	return 0;
	}	}

	/// resolveListElementReference - This method is used to implement	/// resolveListElementReference - This method is used to implement
	/// VarListElementInit::resolveReferences. If the list element is resolv able	/// VarListElementInit::resolveReferences. If the list element is resolv able
	/// now, we return the resolved value, otherwise we return null.	/// now, we return the resolved value, otherwise we return null.
	virtual Init resolveListElementReference(Record &R, const RecordVal RV,	virtual Init resolveListElementReference(Record &R, const RecordVal RV,
	unsigned Elt) const {	unsigned Elt) const {

	assert(0 && "Illegal element reference off def");	llvm_unreachable("Illegal element reference off def");
	return 0;
	}	}
	};	};

	/// FieldInit - X.Y - Represent a reference to a subfield of a variable	/// FieldInit - X.Y - Represent a reference to a subfield of a variable
	///	///
	class FieldInit : public TypedInit {	class FieldInit : public TypedInit {
	Init *Rec; // Record we are referring to	Init *Rec; // Record we are referring to
	std::string FieldName; // Field we are accessing	std::string FieldName; // Field we are accessing

	FieldInit(Init *R, const std::string &FN)	FieldInit(Init *R, const std::string &FN)

	skipping to change at line 1310	skipping to change at line 1235
	inline bool arg_empty() const { return Args.empty(); }	inline bool arg_empty() const { return Args.empty(); }

	inline const_name_iterator name_begin() const { return ArgNames.begin(); }	inline const_name_iterator name_begin() const { return ArgNames.begin(); }
	inline const_name_iterator name_end () const { return ArgNames.end(); }	inline const_name_iterator name_end () const { return ArgNames.end(); }

	inline size_t name_size () const { return ArgNames.size(); }	inline size_t name_size () const { return ArgNames.size(); }
	inline bool name_empty() const { return ArgNames.empty(); }	inline bool name_empty() const { return ArgNames.empty(); }

	virtual Init resolveBitReference(Record &R, const RecordVal RV,	virtual Init resolveBitReference(Record &R, const RecordVal RV,
	unsigned Bit) const {	unsigned Bit) const {

	assert(0 && "Illegal bit reference off dag");	llvm_unreachable("Illegal bit reference off dag");
	return 0;
	}	}

	virtual Init resolveListElementReference(Record &R, const RecordVal RV,	virtual Init resolveListElementReference(Record &R, const RecordVal RV,
	unsigned Elt) const {	unsigned Elt) const {

	assert(0 && "Illegal element reference off dag");	llvm_unreachable("Illegal element reference off dag");
	return 0;
	}	}
	};	};

	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	// High-Level Classes	// High-Level Classes
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	class RecordVal {	class RecordVal {
	Init *Name;	Init *Name;
	RecTy *Ty;	RecTy *Ty;
	unsigned Prefix;	unsigned Prefix;
	Init *Value;	Init *Value;
	public:	public:
	RecordVal(Init N, RecTy T, unsigned P);	RecordVal(Init N, RecTy T, unsigned P);
	RecordVal(const std::string &N, RecTy *T, unsigned P);	RecordVal(const std::string &N, RecTy *T, unsigned P);

	const std::string &getName() const;	const std::string &getName() const;

		const Init *getNameInit() const { return Name; }
		std::string getNameInitAsString() const {
		return getNameInit()->getAsUnquotedString();
		}

	unsigned getPrefix() const { return Prefix; }	unsigned getPrefix() const { return Prefix; }
	RecTy *getType() const { return Ty; }	RecTy *getType() const { return Ty; }
	Init *getValue() const { return Value; }	Init *getValue() const { return Value; }

	bool setValue(Init *V) {	bool setValue(Init *V) {
	if (V) {	if (V) {
	Value = V->convertInitializerTo(Ty);	Value = V->convertInitializerTo(Ty);
	return Value == 0;	return Value == 0;
	}	}

	skipping to change at line 1365	skipping to change at line 1292
	return OS;	return OS;
	}	}

	class Record {	class Record {
	static unsigned LastID;	static unsigned LastID;

	// Unique record ID.	// Unique record ID.
	unsigned ID;	unsigned ID;
	Init *Name;	Init *Name;
	SMLoc Loc;	SMLoc Loc;

	std::vector<std::string> TemplateArgs;	std::vector<Init *> TemplateArgs;
	std::vector<RecordVal> Values;	std::vector<RecordVal> Values;
	std::vector<Record*> SuperClasses;	std::vector<Record*> SuperClasses;

	// Tracks Record instances. Not owned by Record.	// Tracks Record instances. Not owned by Record.
	RecordKeeper &TrackedRecords;	RecordKeeper &TrackedRecords;

	DefInit *TheInit;	DefInit *TheInit;


		void init();
	void checkName();	void checkName();

	public:	public:

	// Constructs a record.	// Constructs a record.
	explicit Record(const std::string &N, SMLoc loc, RecordKeeper &records) :	explicit Record(const std::string &N, SMLoc loc, RecordKeeper &records) :

	ID(LastID++), Name(StringInit::get(N)), Loc(loc), TrackedRecords(record	ID(LastID++), Name(StringInit::get(N)), Loc(loc), TrackedRecords(record
	s), TheInit(0) {}	s),
		TheInit(0) {
		init();
		}
		explicit Record(Init *N, SMLoc loc, RecordKeeper &records) :
		ID(LastID++), Name(N), Loc(loc), TrackedRecords(records), TheInit(0) {
		init();
		}
	~Record() {}	~Record() {}

	static unsigned getNewUID() { return LastID++; }	static unsigned getNewUID() { return LastID++; }

	unsigned getID() const { return ID; }	unsigned getID() const { return ID; }

	const std::string &getName() const;	const std::string &getName() const;

		Init *getNameInit() const {
		return Name;
		}
		const std::string getNameInitAsString() const {
		return getNameInit()->getAsUnquotedString();
		}

	void setName(Init *Name); // Also updates RecordKeeper.	void setName(Init *Name); // Also updates RecordKeeper.
	void setName(const std::string &Name); // Also updates RecordKeeper.	void setName(const std::string &Name); // Also updates RecordKeeper.

	SMLoc getLoc() const { return Loc; }	SMLoc getLoc() const { return Loc; }

	/// get the corresponding DefInit.	/// get the corresponding DefInit.
	DefInit *getDefInit();	DefInit *getDefInit();


	const std::vector<std::string> &getTemplateArgs() const {	const std::vector<Init *> &getTemplateArgs() const {
	return TemplateArgs;	return TemplateArgs;
	}	}
	const std::vector<RecordVal> &getValues() const { return Values; }	const std::vector<RecordVal> &getValues() const { return Values; }
	const std::vector<Record*> &getSuperClasses() const { return SuperClass es; }	const std::vector<Record*> &getSuperClasses() const { return SuperClass es; }


	bool isTemplateArg(StringRef Name) const {	bool isTemplateArg(Init *Name) const {
	for (unsigned i = 0, e = TemplateArgs.size(); i != e; ++i)	for (unsigned i = 0, e = TemplateArgs.size(); i != e; ++i)
	if (TemplateArgs[i] == Name) return true;	if (TemplateArgs[i] == Name) return true;
	return false;	return false;
	}	}

		bool isTemplateArg(StringRef Name) const {
		return isTemplateArg(StringInit::get(Name.str()));
		}


	const RecordVal *getValue(StringRef Name) const {	const RecordVal getValue(const Init Name) const {
	for (unsigned i = 0, e = Values.size(); i != e; ++i)	for (unsigned i = 0, e = Values.size(); i != e; ++i)

	if (Values[i].getName() == Name) return &Values[i];	if (Values[i].getNameInit() == Name) return &Values[i];
	return 0;	return 0;
	}	}

	RecordVal *getValue(StringRef Name) {	const RecordVal *getValue(StringRef Name) const {
		return getValue(StringInit::get(Name));
		}
		RecordVal getValue(const Init Name) {
	for (unsigned i = 0, e = Values.size(); i != e; ++i)	for (unsigned i = 0, e = Values.size(); i != e; ++i)

	if (Values[i].getName() == Name) return &Values[i];	if (Values[i].getNameInit() == Name) return &Values[i];
	return 0;	return 0;
	}	}

		RecordVal *getValue(StringRef Name) {
		return getValue(StringInit::get(Name));
		}


	void addTemplateArg(StringRef Name) {	void addTemplateArg(Init *Name) {
	assert(!isTemplateArg(Name) && "Template arg already defined!");	assert(!isTemplateArg(Name) && "Template arg already defined!");
	TemplateArgs.push_back(Name);	TemplateArgs.push_back(Name);
	}	}

		void addTemplateArg(StringRef Name) {
		addTemplateArg(StringInit::get(Name.str()));
		}

	void addValue(const RecordVal &RV) {	void addValue(const RecordVal &RV) {

	assert(getValue(RV.getName()) == 0 && "Value already added!");	assert(getValue(RV.getNameInit()) == 0 && "Value already added!");
	Values.push_back(RV);	Values.push_back(RV);

		if (Values.size() > 1)
		// Keep NAME at the end of the list. It makes record dumps a
		// bit prettier and allows TableGen tests to be written more
		// naturally. Tests can use CHECK-NEXT to look for Record
		// fields they expect to see after a def. They can't do that if
		// NAME is the first Record field.
		std::swap(Values[Values.size() - 2], Values[Values.size() - 1]);
	}	}


	void removeValue(StringRef Name) {	void removeValue(Init *Name) {
	for (unsigned i = 0, e = Values.size(); i != e; ++i)	for (unsigned i = 0, e = Values.size(); i != e; ++i)

	if (Values[i].getName() == Name) {	if (Values[i].getNameInit() == Name) {
	Values.erase(Values.begin()+i);	Values.erase(Values.begin()+i);
	return;	return;
	}	}

	assert(0 && "Cannot remove an entry that does not exist!");	llvm_unreachable("Cannot remove an entry that does not exist!");
		}

		void removeValue(StringRef Name) {
		removeValue(StringInit::get(Name.str()));
	}	}

	bool isSubClassOf(const Record *R) const {	bool isSubClassOf(const Record *R) const {
	for (unsigned i = 0, e = SuperClasses.size(); i != e; ++i)	for (unsigned i = 0, e = SuperClasses.size(); i != e; ++i)
	if (SuperClasses[i] == R)	if (SuperClasses[i] == R)
	return true;	return true;
	return false;	return false;
	}	}

	bool isSubClassOf(StringRef Name) const {	bool isSubClassOf(StringRef Name) const {
	for (unsigned i = 0, e = SuperClasses.size(); i != e; ++i)	for (unsigned i = 0, e = SuperClasses.size(); i != e; ++i)

	if (SuperClasses[i]->getName() == Name)	if (SuperClasses[i]->getNameInitAsString() == Name)
	return true;	return true;
	return false;	return false;
	}	}

	void addSuperClass(Record *R) {	void addSuperClass(Record *R) {
	assert(!isSubClassOf(R) && "Already subclassing record!");	assert(!isSubClassOf(R) && "Already subclassing record!");
	SuperClasses.push_back(R);	SuperClasses.push_back(R);
	}	}

	/// resolveReferences - If there are any field references that refer to f ields	/// resolveReferences - If there are any field references that refer to f ields

	skipping to change at line 1541	skipping to change at line 1506
	/// value as an int64_t, throwing an exception if the field does not exis t or	/// value as an int64_t, throwing an exception if the field does not exis t or
	/// if the value is not the right type.	/// if the value is not the right type.
	///	///
	int64_t getValueAsInt(StringRef FieldName) const;	int64_t getValueAsInt(StringRef FieldName) const;

	/// getValueAsDag - This method looks up the specified field and returns its	/// getValueAsDag - This method looks up the specified field and returns its
	/// value as an Dag, throwing an exception if the field does not exist or if	/// value as an Dag, throwing an exception if the field does not exist or if
	/// the value is not the right type.	/// the value is not the right type.
	///	///
	DagInit *getValueAsDag(StringRef FieldName) const;	DagInit *getValueAsDag(StringRef FieldName) const;


	/// getValueAsCode - This method looks up the specified field and returns
	/// its value as the string data in a CodeInit, throwing an exception if
	the
	/// field does not exist or if the value is not a code object.
	///
	std::string getValueAsCode(StringRef FieldName) const;
	};	};

	raw_ostream &operator<<(raw_ostream &OS, const Record &R);	raw_ostream &operator<<(raw_ostream &OS, const Record &R);

	struct MultiClass {	struct MultiClass {
	Record Rec; // Placeholder for template args and Name.	Record Rec; // Placeholder for template args and Name.
	typedef std::vector<Record*> RecordVector;	typedef std::vector<Record*> RecordVector;
	RecordVector DefPrototypes;	RecordVector DefPrototypes;

	void dump() const;	void dump() const;

	MultiClass(const std::string &Name, SMLoc Loc, RecordKeeper &Records) :	MultiClass(const std::string &Name, SMLoc Loc, RecordKeeper &Records) :
	Rec(Name, Loc, Records) {}	Rec(Name, Loc, Records) {}
	};	};

	class RecordKeeper {	class RecordKeeper {
	std::map<std::string, Record*> Classes, Defs;	std::map<std::string, Record*> Classes, Defs;


	public:	public:
	~RecordKeeper() {	~RecordKeeper() {
	for (std::map<std::string, Record*>::iterator I = Classes.begin(),	for (std::map<std::string, Record*>::iterator I = Classes.begin(),
	E = Classes.end(); I != E; ++I)	E = Classes.end(); I != E; ++I)
	delete I->second;	delete I->second;
	for (std::map<std::string, Record*>::iterator I = Defs.begin(),	for (std::map<std::string, Record*>::iterator I = Defs.begin(),
	E = Defs.end(); I != E; ++I)	E = Defs.end(); I != E; ++I)
	delete I->second;	delete I->second;
	}	}


	skipping to change at line 1586	skipping to change at line 1546

	Record *getClass(const std::string &Name) const {	Record *getClass(const std::string &Name) const {
	std::map<std::string, Record*>::const_iterator I = Classes.find(Name);	std::map<std::string, Record*>::const_iterator I = Classes.find(Name);
	return I == Classes.end() ? 0 : I->second;	return I == Classes.end() ? 0 : I->second;
	}	}
	Record *getDef(const std::string &Name) const {	Record *getDef(const std::string &Name) const {
	std::map<std::string, Record*>::const_iterator I = Defs.find(Name);	std::map<std::string, Record*>::const_iterator I = Defs.find(Name);
	return I == Defs.end() ? 0 : I->second;	return I == Defs.end() ? 0 : I->second;
	}	}
	void addClass(Record *R) {	void addClass(Record *R) {

	assert(getClass(R->getName()) == 0 && "Class already exists!");	assert(getClass(R->getNameInitAsString()) == 0 && "Class already exists
	Classes.insert(std::make_pair(R->getName(), R));	!");
		Classes.insert(std::make_pair(R->getNameInitAsString(), R));
	}	}
	void addDef(Record *R) {	void addDef(Record *R) {

	assert(getDef(R->getName()) == 0 && "Def already exists!");	assert(getDef(R->getNameInitAsString()) == 0 && "Def already exists!");
	Defs.insert(std::make_pair(R->getName(), R));	Defs.insert(std::make_pair(R->getNameInitAsString(), R));
	}	}

	/// removeClass - Remove, but do not delete, the specified record.	/// removeClass - Remove, but do not delete, the specified record.
	///	///
	void removeClass(const std::string &Name) {	void removeClass(const std::string &Name) {
	assert(Classes.count(Name) && "Class does not exist!");	assert(Classes.count(Name) && "Class does not exist!");
	Classes.erase(Name);	Classes.erase(Name);
	}	}
	/// removeDef - Remove, but do not delete, the specified record.	/// removeDef - Remove, but do not delete, the specified record.
	///	///

	skipping to change at line 1638	skipping to change at line 1598
	/// name field.	/// name field.
	///	///
	struct LessRecordFieldName {	struct LessRecordFieldName {
	bool operator()(const Record Rec1, const Record Rec2) const {	bool operator()(const Record Rec1, const Record Rec2) const {
	return Rec1->getValueAsString("Name") < Rec2->getValueAsString("Name");	return Rec1->getValueAsString("Name") < Rec2->getValueAsString("Name");
	}	}
	};	};

	raw_ostream &operator<<(raw_ostream &OS, const RecordKeeper &RK);	raw_ostream &operator<<(raw_ostream &OS, const RecordKeeper &RK);


		/// QualifyName - Return an Init with a qualifier prefix referring
		/// to CurRec's name.
		Init QualifyName(Record &CurRec, MultiClass CurMultiClass,
		Init *Name, const std::string &Scoper);

		/// QualifyName - Return an Init with a qualifier prefix referring
		/// to CurRec's name.
		Init QualifyName(Record &CurRec, MultiClass CurMultiClass,
		const std::string &Name, const std::string &Scoper);

	} // End llvm namespace	} // End llvm namespace

	#endif	#endif

End of changes. 65 change blocks.
	133 lines changed or deleted	98 lines changed or added

	Recycler.h	Recycler.h

	skipping to change at line 20	skipping to change at line 20
	// This file defines the Recycler class template. See the doxygen comment for	// This file defines the Recycler class template. See the doxygen comment for
	// Recycler for more details.	// Recycler for more details.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_SUPPORT_RECYCLER_H	#ifndef LLVM_SUPPORT_RECYCLER_H
	#define LLVM_SUPPORT_RECYCLER_H	#define LLVM_SUPPORT_RECYCLER_H

	#include "llvm/ADT/ilist.h"	#include "llvm/ADT/ilist.h"
	#include "llvm/Support/AlignOf.h"	#include "llvm/Support/AlignOf.h"

		#include "llvm/Support/ErrorHandling.h"
	#include <cassert>	#include <cassert>

	namespace llvm {	namespace llvm {

	/// PrintRecyclingAllocatorStats - Helper for RecyclingAllocator for	/// PrintRecyclingAllocatorStats - Helper for RecyclingAllocator for
	/// printing statistics.	/// printing statistics.
	///	///
	void PrintRecyclerStats(size_t Size, size_t Align, size_t FreeListSize);	void PrintRecyclerStats(size_t Size, size_t Align, size_t FreeListSize);

	/// RecyclerStruct - Implementation detail for Recycler. This is a	/// RecyclerStruct - Implementation detail for Recycler. This is a

	skipping to change at line 55	skipping to change at line 56
	RecyclerStruct *createSentinel() const {	RecyclerStruct *createSentinel() const {
	return &Sentinel;	return &Sentinel;
	}	}
	static void destroySentinel(RecyclerStruct *) {}	static void destroySentinel(RecyclerStruct *) {}

	RecyclerStruct *provideInitialHead() const { return createSentinel(); }	RecyclerStruct *provideInitialHead() const { return createSentinel(); }
	RecyclerStruct ensureHead(RecyclerStruct) const { return createSentinel (); }	RecyclerStruct ensureHead(RecyclerStruct) const { return createSentinel (); }
	static void noteHead(RecyclerStruct, RecyclerStruct) {}	static void noteHead(RecyclerStruct, RecyclerStruct) {}

	static void deleteNode(RecyclerStruct *) {	static void deleteNode(RecyclerStruct *) {

	assert(0 && "Recycler's ilist_traits shouldn't see a deleteNode call!") ;	llvm_unreachable("Recycler's ilist_traits shouldn't see a deleteNode ca ll!");
	}	}
	};	};

	/// Recycler - This class manages a linked-list of deallocated nodes	/// Recycler - This class manages a linked-list of deallocated nodes
	/// and facilitates reusing deallocated memory in place of allocating	/// and facilitates reusing deallocated memory in place of allocating
	/// new memory.	/// new memory.
	///	///
	template<class T, size_t Size = sizeof(T), size_t Align = AlignOf<T>::Align ment>	template<class T, size_t Size = sizeof(T), size_t Align = AlignOf<T>::Align ment>
	class Recycler {	class Recycler {
	/// FreeList - Doubly-linked list of nodes that have deleted contents and	/// FreeList - Doubly-linked list of nodes that have deleted contents and

End of changes. 2 change blocks.
	1 lines changed or deleted	2 lines changed or added

	RegionInfo.h	RegionInfo.h

	skipping to change at line 684	skipping to change at line 684
	void clearNodeCache() {	void clearNodeCache() {
	if (TopLevelRegion)	if (TopLevelRegion)
	TopLevelRegion->clearNodeCache();	TopLevelRegion->clearNodeCache();
	}	}
	};	};

	inline raw_ostream &operator<<(raw_ostream &OS, const RegionNode &Node) {	inline raw_ostream &operator<<(raw_ostream &OS, const RegionNode &Node) {
	if (Node.isSubRegion())	if (Node.isSubRegion())
	return OS << Node.getNodeAs<Region>()->getNameStr();	return OS << Node.getNodeAs<Region>()->getNameStr();
	else	else

	return OS << Node.getNodeAs<BasicBlock>()->getNameStr();	return OS << Node.getNodeAs<BasicBlock>()->getName();
	}	}
	} // End llvm namespace	} // End llvm namespace
	#endif	#endif

End of changes. 1 change blocks.
	1 lines changed or deleted	1 lines changed or added

	RegisterScavenging.h	RegisterScavenging.h

	skipping to change at line 71	skipping to change at line 71

	/// ReservedRegs - A bitvector of reserved registers.	/// ReservedRegs - A bitvector of reserved registers.
	///	///
	BitVector ReservedRegs;	BitVector ReservedRegs;

	/// RegsAvailable - The current state of all the physical registers immed iately	/// RegsAvailable - The current state of all the physical registers immed iately
	/// before MBBI. One bit per physical register. If bit is set that means it's	/// before MBBI. One bit per physical register. If bit is set that means it's
	/// available, unset means the register is currently being used.	/// available, unset means the register is currently being used.
	BitVector RegsAvailable;	BitVector RegsAvailable;


		// These BitVectors are only used internally to forward(). They are membe
		rs
		// to avoid frequent reallocations.
		BitVector KillRegs, DefRegs;

	public:	public:
	RegScavenger()	RegScavenger()
	: MBB(NULL), NumPhysRegs(0), Tracking(false),	: MBB(NULL), NumPhysRegs(0), Tracking(false),
	ScavengingFrameIndex(-1), ScavengedReg(0), ScavengedRC(NULL) {}	ScavengingFrameIndex(-1), ScavengedReg(0), ScavengedRC(NULL) {}

	/// enterBasicBlock - Start tracking liveness from the begin of the speci fic	/// enterBasicBlock - Start tracking liveness from the begin of the speci fic
	/// basic block.	/// basic block.
	void enterBasicBlock(MachineBasicBlock *mbb);	void enterBasicBlock(MachineBasicBlock *mbb);

	/// initRegState - allow resetting register state info for multiple	/// initRegState - allow resetting register state info for multiple

	skipping to change at line 133	skipping to change at line 137

	/// setUsed - Tell the scavenger a register is used.	/// setUsed - Tell the scavenger a register is used.
	///	///
	void setUsed(unsigned Reg);	void setUsed(unsigned Reg);
	private:	private:
	/// isReserved - Returns true if a register is reserved. It is never "unu sed".	/// isReserved - Returns true if a register is reserved. It is never "unu sed".
	bool isReserved(unsigned Reg) const { return ReservedRegs.test(Reg); }	bool isReserved(unsigned Reg) const { return ReservedRegs.test(Reg); }

	/// isUsed / isUnused - Test if a register is currently being used.	/// isUsed / isUnused - Test if a register is currently being used.
	///	///

	bool isUsed(unsigned Reg) const { return !RegsAvailable.test(Reg); }	bool isUsed(unsigned Reg) const {
	bool isUnused(unsigned Reg) const { return RegsAvailable.test(Reg); }	return !RegsAvailable.test(Reg) \|\| ReservedRegs.test(Reg);
		}

	/// isAliasUsed - Is Reg or an alias currently in use?	/// isAliasUsed - Is Reg or an alias currently in use?
	bool isAliasUsed(unsigned Reg) const;	bool isAliasUsed(unsigned Reg) const;

	/// setUsed / setUnused - Mark the state of one or a number of registers.	/// setUsed / setUnused - Mark the state of one or a number of registers.
	///	///
	void setUsed(BitVector &Regs) {	void setUsed(BitVector &Regs) {

	RegsAvailable &= ~Regs;	RegsAvailable.reset(Regs);
	}	}
	void setUnused(BitVector &Regs) {	void setUnused(BitVector &Regs) {
	RegsAvailable \|= Regs;	RegsAvailable \|= Regs;
	}	}

	/// Add Reg and all its sub-registers to BV.	/// Add Reg and all its sub-registers to BV.
	void addRegWithSubRegs(BitVector &BV, unsigned Reg);	void addRegWithSubRegs(BitVector &BV, unsigned Reg);


	/// Add Reg and its aliases to BV.
	void addRegWithAliases(BitVector &BV, unsigned Reg);

	/// findSurvivorReg - Return the candidate register that is unused for th e	/// findSurvivorReg - Return the candidate register that is unused for th e
	/// longest after StartMI. UseMI is set to the instruction where the sear ch	/// longest after StartMI. UseMI is set to the instruction where the sear ch
	/// stopped.	/// stopped.
	///	///
	/// No more than InstrLimit instructions are inspected.	/// No more than InstrLimit instructions are inspected.
	unsigned findSurvivorReg(MachineBasicBlock::iterator StartMI,	unsigned findSurvivorReg(MachineBasicBlock::iterator StartMI,
	BitVector &Candidates,	BitVector &Candidates,
	unsigned InstrLimit,	unsigned InstrLimit,
	MachineBasicBlock::iterator &UseMI);	MachineBasicBlock::iterator &UseMI);


End of changes. 4 change blocks.
	6 lines changed or deleted	9 lines changed or added

	RuntimeDyld.h	RuntimeDyld.h

	skipping to change at line 38	skipping to change at line 38
	// representations in LLVM IR.	// representations in LLVM IR.
	// FIXME: As the RuntimeDyld fills out, additional routines will be needed	// FIXME: As the RuntimeDyld fills out, additional routines will be needed
	// for the varying types of objects to be allocated.	// for the varying types of objects to be allocated.
	class RTDyldMemoryManager {	class RTDyldMemoryManager {
	RTDyldMemoryManager(const RTDyldMemoryManager&); // DO NOT IMPLEMENT	RTDyldMemoryManager(const RTDyldMemoryManager&); // DO NOT IMPLEMENT
	void operator=(const RTDyldMemoryManager&); // DO NOT IMPLEMENT	void operator=(const RTDyldMemoryManager&); // DO NOT IMPLEMENT
	public:	public:
	RTDyldMemoryManager() {}	RTDyldMemoryManager() {}
	virtual ~RTDyldMemoryManager();	virtual ~RTDyldMemoryManager();


	// Allocate ActualSize bytes, or more, for the named function. Return	/// allocateCodeSection - Allocate a memory block of (at least) the given
	// a pointer to the allocated memory and update Size to reflect how much	/// size suitable for executable code.
	// memory was acutally allocated.	virtual uint8_t *allocateCodeSection(uintptr_t Size, unsigned Alignment,
	virtual uint8_t startFunctionBody(const char Name, uintptr_t &Size) = 0	unsigned SectionID) = 0;
	;
		/// allocateDataSection - Allocate a memory block of (at least) the given
	// Mark the end of the function, including how much of the allocated	/// size suitable for data.
	// memory was actually used.	virtual uint8_t *allocateDataSection(uintptr_t Size, unsigned Alignment,
	virtual void endFunctionBody(const char Name, uint8_t FunctionStart,	unsigned SectionID) = 0;
	uint8_t *FunctionEnd) = 0;
		virtual void *getPointerToNamedFunction(const std::string &Name,
		bool AbortOnFailure = true) = 0;
	};	};

	class RuntimeDyld {	class RuntimeDyld {
	RuntimeDyld(const RuntimeDyld &); // DO NOT IMPLEMENT	RuntimeDyld(const RuntimeDyld &); // DO NOT IMPLEMENT
	void operator=(const RuntimeDyld &); // DO NOT IMPLEMENT	void operator=(const RuntimeDyld &); // DO NOT IMPLEMENT

	// RuntimeDyldImpl is the actual class. RuntimeDyld is just the public	// RuntimeDyldImpl is the actual class. RuntimeDyld is just the public
	// interface.	// interface.
	RuntimeDyldImpl *Dyld;	RuntimeDyldImpl *Dyld;
	RTDyldMemoryManager *MM;	RTDyldMemoryManager *MM;

		protected:
		// Change the address associated with a section when resolving relocation
		s.
		// Any relocations already associated with the symbol will be re-resolved
		.
		void reassignSectionAddress(unsigned SectionID, uint64_t Addr);
	public:	public:
	RuntimeDyld(RTDyldMemoryManager*);	RuntimeDyld(RTDyldMemoryManager*);
	~RuntimeDyld();	~RuntimeDyld();

	bool loadObject(MemoryBuffer *InputBuffer);	bool loadObject(MemoryBuffer *InputBuffer);
	// Get the address of our local copy of the symbol. This may or may not	// Get the address of our local copy of the symbol. This may or may not
	// be the address used for relocation (clients can copy the data around	// be the address used for relocation (clients can copy the data around
	// and resolve relocatons based on where they put it).	// and resolve relocatons based on where they put it).
	void *getSymbolAddress(StringRef Name);	void *getSymbolAddress(StringRef Name);
	// Resolve the relocations for all symbols we currently know about.	// Resolve the relocations for all symbols we currently know about.
	void resolveRelocations();	void resolveRelocations();

	// Change the address associated with a symbol when resolving relocations
	.	/// mapSectionAddress - map a section to its target address space value.
	// Any relocations already associated with the symbol will be re-resolved	/// Map the address of a JIT section as returned from the memory manager
	.	/// to the address in the target process as the running code will see it.
	void reassignSymbolAddress(StringRef Name, uint8_t *Addr);	/// This is the address which will be used for relocation resolution.
		void mapSectionAddress(void *LocalAddress, uint64_t TargetAddress);

	StringRef getErrorString();	StringRef getErrorString();
	};	};

	} // end namespace llvm	} // end namespace llvm

	#endif	#endif

End of changes. 3 change blocks.
	15 lines changed or deleted	25 lines changed or added

	SMLoc.h	SMLoc.h

	skipping to change at line 18	skipping to change at line 18
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	//	//
	// This file declares the SMLoc class. This class encapsulates a location in	// This file declares the SMLoc class. This class encapsulates a location in
	// source code for use in diagnostics.	// source code for use in diagnostics.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef SUPPORT_SMLOC_H	#ifndef SUPPORT_SMLOC_H
	#define SUPPORT_SMLOC_H	#define SUPPORT_SMLOC_H


		#include <cassert>

	namespace llvm {	namespace llvm {


	// SMLoc - Represents a location in source code.	/// SMLoc - Represents a location in source code.
	class SMLoc {	class SMLoc {
	const char *Ptr;	const char *Ptr;
	public:	public:
	SMLoc() : Ptr(0) {}	SMLoc() : Ptr(0) {}
	SMLoc(const SMLoc &RHS) : Ptr(RHS.Ptr) {}	SMLoc(const SMLoc &RHS) : Ptr(RHS.Ptr) {}

	bool isValid() const { return Ptr != 0; }	bool isValid() const { return Ptr != 0; }

	bool operator==(const SMLoc &RHS) const { return RHS.Ptr == Ptr; }	bool operator==(const SMLoc &RHS) const { return RHS.Ptr == Ptr; }
	bool operator!=(const SMLoc &RHS) const { return RHS.Ptr != Ptr; }	bool operator!=(const SMLoc &RHS) const { return RHS.Ptr != Ptr; }

	const char *getPointer() const { return Ptr; }	const char *getPointer() const { return Ptr; }

	static SMLoc getFromPointer(const char *Ptr) {	static SMLoc getFromPointer(const char *Ptr) {
	SMLoc L;	SMLoc L;
	L.Ptr = Ptr;	L.Ptr = Ptr;
	return L;	return L;
	}	}
	};	};


	}	/// SMRange - Represents a range in source code. Note that unlike standard
		STL
		/// ranges, the locations specified are considered to be inclusive. For
		/// example, [X,X] does include X, it isn't an empty range.
		class SMRange {
		public:
		SMLoc Start, End;

		SMRange() {}
		SMRange(SMLoc Start, SMLoc End) : Start(Start), End(End) {
		assert(Start.isValid() == End.isValid() &&
		"Start and end should either both be valid or both be invalid!")
		;
		}

		bool isValid() const { return Start.isValid(); }
		};

		} // end namespace llvm

	#endif	#endif

End of changes. 3 change blocks.
	2 lines changed or deleted	22 lines changed or added

	SSAUpdater.h	SSAUpdater.h

	skipping to change at line 17	skipping to change at line 17
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	//	//
	// This file declares the SSAUpdater class.	// This file declares the SSAUpdater class.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_TRANSFORMS_UTILS_SSAUPDATER_H	#ifndef LLVM_TRANSFORMS_UTILS_SSAUPDATER_H
	#define LLVM_TRANSFORMS_UTILS_SSAUPDATER_H	#define LLVM_TRANSFORMS_UTILS_SSAUPDATER_H


		#include "llvm/ADT/StringRef.h"

	namespace llvm {	namespace llvm {

	class Value;
	class BasicBlock;	class BasicBlock;

	class Use;	class Instruction;
	class PHINode;	class LoadInst;
	template<typename T> class SmallVectorImpl;	template<typename T> class SmallVectorImpl;
	template<typename T> class SSAUpdaterTraits;	template<typename T> class SSAUpdaterTraits;

	class DbgDeclareInst;	class PHINode;
	class DIBuilder;	class Type;
	class BumpPtrAllocator;	class Use;
		class Value;

	/// SSAUpdater - This class updates SSA form for a set of values defined in	/// SSAUpdater - This class updates SSA form for a set of values defined in
	/// multiple blocks. This is used when code duplication or another unstruc tured	/// multiple blocks. This is used when code duplication or another unstruc tured
	/// transformation wants to rewrite a set of uses of one value with uses of a	/// transformation wants to rewrite a set of uses of one value with uses of a
	/// set of values.	/// set of values.
	class SSAUpdater {	class SSAUpdater {
	friend class SSAUpdaterTraits<SSAUpdater>;	friend class SSAUpdaterTraits<SSAUpdater>;

	private:	private:
	/// AvailableVals - This keeps track of which value to use on a per-block	/// AvailableVals - This keeps track of which value to use on a per-block

	skipping to change at line 139	skipping to change at line 141

	/// run - This does the promotion. Insts is a list of loads and stores t o	/// run - This does the promotion. Insts is a list of loads and stores t o
	/// promote, and Name is the basename for the PHIs to insert. After this is	/// promote, and Name is the basename for the PHIs to insert. After this is
	/// complete, the loads and stores are removed from the code.	/// complete, the loads and stores are removed from the code.
	void run(const SmallVectorImpl<Instruction*> &Insts) const;	void run(const SmallVectorImpl<Instruction*> &Insts) const;

	/// Return true if the specified instruction is in the Inst list (which w as	/// Return true if the specified instruction is in the Inst list (which w as
	/// passed into the run method). Clients should implement this with a mo re	/// passed into the run method). Clients should implement this with a mo re
	/// efficient version if possible.	/// efficient version if possible.
	virtual bool isInstInList(Instruction *I,	virtual bool isInstInList(Instruction *I,

	const SmallVectorImpl<Instruction*> &Insts) con	const SmallVectorImpl<Instruction*> &Insts) con
	st {	st;
	for (unsigned i = 0, e = Insts.size(); i != e; ++i)
	if (Insts[i] == I)
	return true;
	return false;
	}

	/// doExtraRewritesBeforeFinalDeletion - This hook is invoked after all t he	/// doExtraRewritesBeforeFinalDeletion - This hook is invoked after all t he
	/// stores are found and inserted as available values, but	/// stores are found and inserted as available values, but
	virtual void doExtraRewritesBeforeFinalDeletion() const {	virtual void doExtraRewritesBeforeFinalDeletion() const {
	}	}

	/// replaceLoadWithValue - Clients can choose to implement this to get	/// replaceLoadWithValue - Clients can choose to implement this to get
	/// notified right before a load is RAUW'd another value.	/// notified right before a load is RAUW'd another value.
	virtual void replaceLoadWithValue(LoadInst LI, Value V) const {	virtual void replaceLoadWithValue(LoadInst LI, Value V) const {
	}	}

End of changes. 5 change blocks.
	13 lines changed or deleted	10 lines changed or added

	SSAUpdaterImpl.h	SSAUpdaterImpl.h

	skipping to change at line 18	skipping to change at line 18
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	//	//
	// This file provides a template that implements the core algorithm for the	// This file provides a template that implements the core algorithm for the
	// SSAUpdater and MachineSSAUpdater.	// SSAUpdater and MachineSSAUpdater.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_TRANSFORMS_UTILS_SSAUPDATERIMPL_H	#ifndef LLVM_TRANSFORMS_UTILS_SSAUPDATERIMPL_H
	#define LLVM_TRANSFORMS_UTILS_SSAUPDATERIMPL_H	#define LLVM_TRANSFORMS_UTILS_SSAUPDATERIMPL_H


		#include "llvm/ADT/DenseMap.h"
		#include "llvm/ADT/SmallVector.h"
		#include "llvm/Support/Allocator.h"
		#include "llvm/Support/Debug.h"
		#include "llvm/Support/ValueHandle.h"

	namespace llvm {	namespace llvm {


		class CastInst;
		class PHINode;
	template<typename T> class SSAUpdaterTraits;	template<typename T> class SSAUpdaterTraits;

	template<typename UpdaterT>	template<typename UpdaterT>
	class SSAUpdaterImpl {	class SSAUpdaterImpl {
	private:	private:
	UpdaterT *Updater;	UpdaterT *Updater;

	typedef SSAUpdaterTraits<UpdaterT> Traits;	typedef SSAUpdaterTraits<UpdaterT> Traits;
	typedef typename Traits::BlkT BlkT;	typedef typename Traits::BlkT BlkT;
	typedef typename Traits::ValT ValT;	typedef typename Traits::ValT ValT;

	skipping to change at line 375	skipping to change at line 383

	/// FindExistingPHI - Look through the PHI nodes in a block to see if any of	/// FindExistingPHI - Look through the PHI nodes in a block to see if any of
	/// them match what is needed.	/// them match what is needed.
	void FindExistingPHI(BlkT BB, BlockListTy BlockList) {	void FindExistingPHI(BlkT BB, BlockListTy BlockList) {
	for (typename BlkT::iterator BBI = BB->begin(), BBE = BB->end();	for (typename BlkT::iterator BBI = BB->begin(), BBE = BB->end();
	BBI != BBE; ++BBI) {	BBI != BBE; ++BBI) {
	PhiT *SomePHI = Traits::InstrIsPHI(BBI);	PhiT *SomePHI = Traits::InstrIsPHI(BBI);
	if (!SomePHI)	if (!SomePHI)
	break;	break;
	if (CheckIfPHIMatches(SomePHI)) {	if (CheckIfPHIMatches(SomePHI)) {

	RecordMatchingPHI(SomePHI);	RecordMatchingPHIs(BlockList);
	break;	break;
	}	}
	// Match failed: clear all the PHITag values.	// Match failed: clear all the PHITag values.
	for (typename BlockListTy::iterator I = BlockList->begin(),	for (typename BlockListTy::iterator I = BlockList->begin(),
	E = BlockList->end(); I != E; ++I)	E = BlockList->end(); I != E; ++I)
	(*I)->PHITag = 0;	(*I)->PHITag = 0;
	}	}
	}	}

	/// CheckIfPHIMatches - Check if a PHI node matches the placement and val ues	/// CheckIfPHIMatches - Check if a PHI node matches the placement and val ues

	skipping to change at line 432	skipping to change at line 440
	return false;	return false;
	}	}
	PredInfo->PHITag = IncomingPHIVal;	PredInfo->PHITag = IncomingPHIVal;

	WorkList.push_back(IncomingPHIVal);	WorkList.push_back(IncomingPHIVal);
	}	}
	}	}
	return true;	return true;
	}	}


	/// RecordMatchingPHI - For a PHI node that matches, record it and its in	/// RecordMatchingPHIs - For each PHI node that matches, record it in bot
	put	h
	/// PHIs in both the BBMap and the AvailableVals mapping.	/// the BBMap and the AvailableVals mapping.
	void RecordMatchingPHI(PhiT *PHI) {	void RecordMatchingPHIs(BlockListTy *BlockList) {
	SmallVector<PhiT*, 20> WorkList;	for (typename BlockListTy::iterator I = BlockList->begin(),
	WorkList.push_back(PHI);	E = BlockList->end(); I != E; ++I)
		if (PhiT PHI = (I)->PHITag) {
	// Record this PHI.	BlkT *BB = PHI->getParent();
	BlkT *BB = PHI->getParent();	ValT PHIVal = Traits::GetPHIValue(PHI);
	ValT PHIVal = Traits::GetPHIValue(PHI);	(*AvailableVals)[BB] = PHIVal;
	(*AvailableVals)[BB] = PHIVal;	BBMap[BB]->AvailableVal = PHIVal;
	BBMap[BB]->AvailableVal = PHIVal;

	while (!WorkList.empty()) {
	PHI = WorkList.pop_back_val();

	// Iterate through the PHI's incoming values.
	for (typename Traits::PHI_iterator I = Traits::PHI_begin(PHI),
	E = Traits::PHI_end(PHI); I != E; ++I) {
	ValT IncomingVal = I.getIncomingValue();
	PhiT *IncomingPHI = Traits::ValueIsPHI(IncomingVal, Updater);
	if (!IncomingPHI) continue;
	BB = IncomingPHI->getParent();
	BBInfo *Info = BBMap[BB];
	if (!Info \|\| Info->AvailableVal)
	continue;

	// Record the PHI and add it to the worklist.
	(*AvailableVals)[BB] = IncomingVal;
	Info->AvailableVal = IncomingVal;
	WorkList.push_back(IncomingPHI);
	}	}

	}
	}	}
	};	};

	} // End llvm namespace	} // End llvm namespace

	#endif	#endif

End of changes. 5 change blocks.
	33 lines changed or deleted	20 lines changed or added

	ScalarEvolution.h	ScalarEvolution.h

	skipping to change at line 44	skipping to change at line 44
	#include <map>	#include <map>

	namespace llvm {	namespace llvm {
	class APInt;	class APInt;
	class Constant;	class Constant;
	class ConstantInt;	class ConstantInt;
	class DominatorTree;	class DominatorTree;
	class Type;	class Type;
	class ScalarEvolution;	class ScalarEvolution;
	class TargetData;	class TargetData;

		class TargetLibraryInfo;
	class LLVMContext;	class LLVMContext;
	class Loop;	class Loop;
	class LoopInfo;	class LoopInfo;
	class Operator;	class Operator;
	class SCEVUnknown;	class SCEVUnknown;
	class SCEV;	class SCEV;
	template<> struct FoldingSetTrait<SCEV>;	template<> struct FoldingSetTrait<SCEV>;

	/// SCEV - This class represents an analyzed expression in the program. These	/// SCEV - This class represents an analyzed expression in the program. These
	/// are opaque objects that the client is not allowed to do much with	/// are opaque objects that the client is not allowed to do much with

	skipping to change at line 121	skipping to change at line 122

	/// isOne - Return true if the expression is a constant one.	/// isOne - Return true if the expression is a constant one.
	///	///
	bool isOne() const;	bool isOne() const;

	/// isAllOnesValue - Return true if the expression is a constant	/// isAllOnesValue - Return true if the expression is a constant
	/// all-ones value.	/// all-ones value.
	///	///
	bool isAllOnesValue() const;	bool isAllOnesValue() const;


		/// isNonConstantNegative - Return true if the specified scev is negate
		d,
		/// but not a constant.
		bool isNonConstantNegative() const;

	/// print - Print out the internal representation of this scalar to the	/// print - Print out the internal representation of this scalar to the
	/// specified stream. This should really only be used for debugging	/// specified stream. This should really only be used for debugging
	/// purposes.	/// purposes.
	void print(raw_ostream &OS) const;	void print(raw_ostream &OS) const;

	/// dump - This method is used for debugging.	/// dump - This method is used for debugging.
	///	///
	void dump() const;	void dump() const;
	};	};

	// Specialize FoldingSetTrait for SCEV to avoid needing to compute	// Specialize FoldingSetTrait for SCEV to avoid needing to compute
	// temporary FoldingSetNodeID values.	// temporary FoldingSetNodeID values.
	template<> struct FoldingSetTrait<SCEV> : DefaultFoldingSetTrait<SCEV> {	template<> struct FoldingSetTrait<SCEV> : DefaultFoldingSetTrait<SCEV> {
	static void Profile(const SCEV &X, FoldingSetNodeID& ID) {	static void Profile(const SCEV &X, FoldingSetNodeID& ID) {
	ID = X.FastID;	ID = X.FastID;
	}	}
	static bool Equals(const SCEV &X, const FoldingSetNodeID &ID,	static bool Equals(const SCEV &X, const FoldingSetNodeID &ID,

	FoldingSetNodeID &TempID) {	unsigned IDHash, FoldingSetNodeID &TempID) {
	return ID == X.FastID;	return ID == X.FastID;
	}	}
	static unsigned ComputeHash(const SCEV &X, FoldingSetNodeID &TempID) {	static unsigned ComputeHash(const SCEV &X, FoldingSetNodeID &TempID) {
	return X.FastID.ComputeHash();	return X.FastID.ComputeHash();
	}	}
	};	};

	inline raw_ostream &operator<<(raw_ostream &OS, const SCEV &S) {	inline raw_ostream &operator<<(raw_ostream &OS, const SCEV &S) {
	S.print(OS);	S.print(OS);
	return OS;	return OS;

	skipping to change at line 227	skipping to change at line 232
	Function *F;	Function *F;

	/// LI - The loop information for the function we are currently analyzi ng.	/// LI - The loop information for the function we are currently analyzi ng.
	///	///
	LoopInfo *LI;	LoopInfo *LI;

	/// TD - The target data information for the target we are targeting.	/// TD - The target data information for the target we are targeting.
	///	///
	TargetData *TD;	TargetData *TD;


		/// TLI - The target library information for the target we are targetin
		g.
		///
		TargetLibraryInfo *TLI;

	/// DT - The dominator tree.	/// DT - The dominator tree.
	///	///
	DominatorTree *DT;	DominatorTree *DT;

	/// CouldNotCompute - This SCEV is used to represent unknown trip	/// CouldNotCompute - This SCEV is used to represent unknown trip
	/// counts and things.	/// counts and things.
	SCEVCouldNotCompute CouldNotCompute;	SCEVCouldNotCompute CouldNotCompute;

	/// ValueExprMapType - The typedef for ValueExprMap.	/// ValueExprMapType - The typedef for ValueExprMap.
	///	///

	skipping to change at line 724	skipping to change at line 733
	bool isLoopEntryGuardedByCond(const Loop *L, ICmpInst::Predicate Pred,	bool isLoopEntryGuardedByCond(const Loop *L, ICmpInst::Predicate Pred,
	const SCEV LHS, const SCEV RHS);	const SCEV LHS, const SCEV RHS);

	/// isLoopBackedgeGuardedByCond - Test whether the backedge of the loop is	/// isLoopBackedgeGuardedByCond - Test whether the backedge of the loop is
	/// protected by a conditional between LHS and RHS. This is used to	/// protected by a conditional between LHS and RHS. This is used to
	/// to eliminate casts.	/// to eliminate casts.
	bool isLoopBackedgeGuardedByCond(const Loop *L, ICmpInst::Predicate Pre d,	bool isLoopBackedgeGuardedByCond(const Loop *L, ICmpInst::Predicate Pre d,
	const SCEV LHS, const SCEV RHS);	const SCEV LHS, const SCEV RHS);

	/// getSmallConstantTripCount - Returns the maximum trip count of this loop	/// getSmallConstantTripCount - Returns the maximum trip count of this loop

	/// as a normal unsigned value, if possible. Returns 0 if the trip coun	/// as a normal unsigned value. Returns 0 if the trip count is unknown
	t is	or
	/// unknown or not constant.	/// not constant. This "trip count" assumes that control exits via
	unsigned getSmallConstantTripCount(Loop L, BasicBlock ExitBlock);	/// ExitingBlock. More precisely, it is the number of times that contro
		l may
		/// reach ExitingBlock before taking the branch. For loops with multipl
		e
		/// exits, it may not be the number times that the loop header executes
		if
		/// the loop exits prematurely via another branch.
		unsigned getSmallConstantTripCount(Loop L, BasicBlock ExitingBlock);

	/// getSmallConstantTripMultiple - Returns the largest constant divisor of	/// getSmallConstantTripMultiple - Returns the largest constant divisor of
	/// the trip count of this loop as a normal unsigned value, if	/// the trip count of this loop as a normal unsigned value, if
	/// possible. This means that the actual trip count is always a multipl e of	/// possible. This means that the actual trip count is always a multipl e of
	/// the returned value (don't forget the trip count could very well be zero	/// the returned value (don't forget the trip count could very well be zero

	/// as well!).	/// as well!). As explained in the comments for getSmallConstantTripCou
	unsigned getSmallConstantTripMultiple(Loop L, BasicBlock ExitBlock);	nt,
		/// this assumes that control exits the loop via ExitingBlock.
		unsigned getSmallConstantTripMultiple(Loop L, BasicBlock ExitingBlock
		);

	// getExitCount - Get the expression for the number of loop iterations for	// getExitCount - Get the expression for the number of loop iterations for
	// which this loop is guaranteed not to exit via ExitingBlock. Otherwis e	// which this loop is guaranteed not to exit via ExitingBlock. Otherwis e
	// return SCEVCouldNotCompute.	// return SCEVCouldNotCompute.
	const SCEV getExitCount(Loop L, BasicBlock *ExitingBlock);	const SCEV getExitCount(Loop L, BasicBlock *ExitingBlock);

	/// getBackedgeTakenCount - If the specified loop has a predictable	/// getBackedgeTakenCount - If the specified loop has a predictable
	/// backedge-taken count, return it, otherwise return a SCEVCouldNotCom pute	/// backedge-taken count, return it, otherwise return a SCEVCouldNotCom pute
	/// object. The backedge-taken count is the number of times the loop he ader	/// object. The backedge-taken count is the number of times the loop he ader
	/// will be branched to from within the loop. This is one less than the	/// will be branched to from within the loop. This is one less than the

End of changes. 6 change blocks.
	7 lines changed or deleted	28 lines changed or added

	ScalarEvolutionExpander.h	ScalarEvolutionExpander.h

	skipping to change at line 25	skipping to change at line 25
	#define LLVM_ANALYSIS_SCALAREVOLUTION_EXPANDER_H	#define LLVM_ANALYSIS_SCALAREVOLUTION_EXPANDER_H

	#include "llvm/Analysis/ScalarEvolutionExpressions.h"	#include "llvm/Analysis/ScalarEvolutionExpressions.h"
	#include "llvm/Analysis/ScalarEvolutionNormalization.h"	#include "llvm/Analysis/ScalarEvolutionNormalization.h"
	#include "llvm/Support/IRBuilder.h"	#include "llvm/Support/IRBuilder.h"
	#include "llvm/Support/TargetFolder.h"	#include "llvm/Support/TargetFolder.h"
	#include "llvm/Support/ValueHandle.h"	#include "llvm/Support/ValueHandle.h"
	#include <set>	#include <set>

	namespace llvm {	namespace llvm {

		class TargetLowering;

	/// SCEVExpander - This class uses information about analyze scalars to	/// SCEVExpander - This class uses information about analyze scalars to
	/// rewrite expressions in canonical form.	/// rewrite expressions in canonical form.
	///	///
	/// Clients should create an instance of this class when rewriting is nee ded,	/// Clients should create an instance of this class when rewriting is nee ded,
	/// and destroy it when finished to allow the release of the associated	/// and destroy it when finished to allow the release of the associated
	/// memory.	/// memory.
	class SCEVExpander : public SCEVVisitor<SCEVExpander, Value*> {	class SCEVExpander : public SCEVVisitor<SCEVExpander, Value*> {
	ScalarEvolution &SE;	ScalarEvolution &SE;

	// New instructions receive a name to identifies them with the current pass.	// New instructions receive a name to identifies them with the current pass.

	skipping to change at line 61	skipping to change at line 63

	/// IVIncInsertPos - When this is non-null, addrecs expanded in the	/// IVIncInsertPos - When this is non-null, addrecs expanded in the
	/// loop it indicates should be inserted with increments at	/// loop it indicates should be inserted with increments at
	/// IVIncInsertPos.	/// IVIncInsertPos.
	const Loop *IVIncInsertLoop;	const Loop *IVIncInsertLoop;

	/// IVIncInsertPos - When expanding addrecs in the IVIncInsertLoop loop ,	/// IVIncInsertPos - When expanding addrecs in the IVIncInsertLoop loop ,
	/// insert the IV increment at this position.	/// insert the IV increment at this position.
	Instruction *IVIncInsertPos;	Instruction *IVIncInsertPos;


		/// Phis that complete an IV chain. Reuse
		std::set<AssertingVH<PHINode> > ChainedPhis;

	/// CanonicalMode - When true, expressions are expanded in "canonical"	/// CanonicalMode - When true, expressions are expanded in "canonical"
	/// form. In particular, addrecs are expanded as arithmetic based on	/// form. In particular, addrecs are expanded as arithmetic based on
	/// a canonical induction variable. When false, expression are expanded	/// a canonical induction variable. When false, expression are expanded
	/// in a more literal form.	/// in a more literal form.
	bool CanonicalMode;	bool CanonicalMode;

	/// When invoked from LSR, the expander is in "strength reduction" mode . The	/// When invoked from LSR, the expander is in "strength reduction" mode . The
	/// only difference is that phi's are only reused if they are already i n	/// only difference is that phi's are only reused if they are already i n
	/// "expanded" form.	/// "expanded" form.
	bool LSRMode;	bool LSRMode;

	skipping to change at line 103	skipping to change at line 108
	void setDebugType(const char* s) { DebugType = s; }	void setDebugType(const char* s) { DebugType = s; }
	#endif	#endif

	/// clear - Erase the contents of the InsertedExpressions map so that u sers	/// clear - Erase the contents of the InsertedExpressions map so that u sers
	/// trying to expand the same expression into multiple BasicBlocks or	/// trying to expand the same expression into multiple BasicBlocks or
	/// different places within the same BasicBlock can do so.	/// different places within the same BasicBlock can do so.
	void clear() {	void clear() {
	InsertedExpressions.clear();	InsertedExpressions.clear();
	InsertedValues.clear();	InsertedValues.clear();
	InsertedPostIncValues.clear();	InsertedPostIncValues.clear();

		ChainedPhis.clear();
	}	}

	/// getOrInsertCanonicalInductionVariable - This method returns the	/// getOrInsertCanonicalInductionVariable - This method returns the
	/// canonical induction variable of the specified type for the specifie d	/// canonical induction variable of the specified type for the specifie d
	/// loop (inserting one if there is none). A canonical induction varia ble	/// loop (inserting one if there is none). A canonical induction varia ble
	/// starts at zero and steps by one on each iteration.	/// starts at zero and steps by one on each iteration.
	PHINode getOrInsertCanonicalInductionVariable(const Loop L, Type *Ty) ;	PHINode getOrInsertCanonicalInductionVariable(const Loop L, Type *Ty) ;


	/// hoistStep - Utility for hoisting an IV increment.	/// getIVIncOperand - Return the induction variable increment's IV oper
	static bool hoistStep(Instruction IncV, Instruction InsertPos,	and.
	const DominatorTree *DT);	Instruction getIVIncOperand(Instruction IncV, Instruction *InsertPos,
		bool allowScale);

		/// hoistIVInc - Utility for hoisting an IV increment.
		bool hoistIVInc(Instruction IncV, Instruction InsertPos);

	/// replaceCongruentIVs - replace congruent phis with their most canoni cal	/// replaceCongruentIVs - replace congruent phis with their most canoni cal
	/// representative. Return the number of phis eliminated.	/// representative. Return the number of phis eliminated.
	unsigned replaceCongruentIVs(Loop L, const DominatorTree DT,	unsigned replaceCongruentIVs(Loop L, const DominatorTree DT,

	SmallVectorImpl<WeakVH> &DeadInsts);	SmallVectorImpl<WeakVH> &DeadInsts,
		const TargetLowering *TLI = NULL);

	/// expandCodeFor - Insert code to directly compute the specified SCEV	/// expandCodeFor - Insert code to directly compute the specified SCEV
	/// expression into the program. The inserted code is inserted into th e	/// expression into the program. The inserted code is inserted into th e
	/// specified block.	/// specified block.
	Value expandCodeFor(const SCEV SH, Type Ty, Instruction I);	Value expandCodeFor(const SCEV SH, Type Ty, Instruction I);

	/// setIVIncInsertPos - Set the current IV increment loop and position.	/// setIVIncInsertPos - Set the current IV increment loop and position.
	void setIVIncInsertPos(const Loop L, Instruction Pos) {	void setIVIncInsertPos(const Loop L, Instruction Pos) {
	assert(!CanonicalMode &&	assert(!CanonicalMode &&
	"IV increment positions are not supported in CanonicalMode");	"IV increment positions are not supported in CanonicalMode");

	skipping to change at line 164	skipping to change at line 174
	void disableCanonicalMode() { CanonicalMode = false; }	void disableCanonicalMode() { CanonicalMode = false; }

	void enableLSRMode() { LSRMode = true; }	void enableLSRMode() { LSRMode = true; }

	/// clearInsertPoint - Clear the current insertion point. This is usefu l	/// clearInsertPoint - Clear the current insertion point. This is usefu l
	/// if the instruction that had been serving as the insertion point may	/// if the instruction that had been serving as the insertion point may
	/// have been deleted.	/// have been deleted.
	void clearInsertPoint() {	void clearInsertPoint() {
	Builder.ClearInsertionPoint();	Builder.ClearInsertionPoint();
	}	}


		/// isInsertedInstruction - Return true if the specified instruction wa
		s
		/// inserted by the code rewriter. If so, the client should not modify
		the
		/// instruction.
		bool isInsertedInstruction(Instruction *I) const {
		return InsertedValues.count(I) \|\| InsertedPostIncValues.count(I);
		}

		void setChainedPhi(PHINode *PN) { ChainedPhis.insert(PN); }

	private:	private:
	LLVMContext &getContext() const { return SE.getContext(); }	LLVMContext &getContext() const { return SE.getContext(); }

	/// InsertBinop - Insert the specified binary operator, doing a small a mount	/// InsertBinop - Insert the specified binary operator, doing a small a mount
	/// of work to avoid inserting an obviously redundant operation.	/// of work to avoid inserting an obviously redundant operation.
	Value InsertBinop(Instruction::BinaryOps Opcode, Value LHS, Value *RH S);	Value InsertBinop(Instruction::BinaryOps Opcode, Value LHS, Value *RH S);

	/// ReuseOrCreateCast - Arange for there to be a cast of V to Ty at IP,	/// ReuseOrCreateCast - Arange for there to be a cast of V to Ty at IP,
	/// reusing an existing cast if a suitable one exists, moving an existi ng	/// reusing an existing cast if a suitable one exists, moving an existi ng
	/// cast if a suitable one exists but isn't in the right place, or	/// cast if a suitable one exists but isn't in the right place, or

	skipping to change at line 198	skipping to change at line 218
	PointerType PTy, Type Ty, Value *V);	PointerType PTy, Type Ty, Value *V);

	Value expand(const SCEV S);	Value expand(const SCEV S);

	/// expandCodeFor - Insert code to directly compute the specified SCEV	/// expandCodeFor - Insert code to directly compute the specified SCEV
	/// expression into the program. The inserted code is inserted into th e	/// expression into the program. The inserted code is inserted into th e
	/// SCEVExpander's current insertion point. If a type is specified, the	/// SCEVExpander's current insertion point. If a type is specified, the
	/// result will be expanded to have that type, with a cast if necessary .	/// result will be expanded to have that type, with a cast if necessary .
	Value expandCodeFor(const SCEV SH, Type *Ty = 0);	Value expandCodeFor(const SCEV SH, Type *Ty = 0);


	/// isInsertedInstruction - Return true if the specified instruction wa
	s
	/// inserted by the code rewriter. If so, the client should not modify
	the
	/// instruction.
	bool isInsertedInstruction(Instruction *I) const {
	return InsertedValues.count(I) \|\| InsertedPostIncValues.count(I);
	}

	/// getRelevantLoop - Determine the most "relevant" loop for the given SCEV.	/// getRelevantLoop - Determine the most "relevant" loop for the given SCEV.
	const Loop getRelevantLoop(const SCEV );	const Loop getRelevantLoop(const SCEV );

	Value visitConstant(const SCEVConstant S) {	Value visitConstant(const SCEVConstant S) {
	return S->getValue();	return S->getValue();
	}	}

	Value visitTruncateExpr(const SCEVTruncateExpr S);	Value visitTruncateExpr(const SCEVTruncateExpr S);

	Value visitZeroExtendExpr(const SCEVZeroExtendExpr S);	Value visitZeroExtendExpr(const SCEVZeroExtendExpr S);

	skipping to change at line 247	skipping to change at line 260

	bool isNormalAddRecExprPHI(PHINode PN, Instruction IncV, const Loop * L);	bool isNormalAddRecExprPHI(PHINode PN, Instruction IncV, const Loop * L);

	bool isExpandedAddRecExprPHI(PHINode PN, Instruction IncV, const Loop *L);	bool isExpandedAddRecExprPHI(PHINode PN, Instruction IncV, const Loop *L);

	Value expandAddRecExprLiterally(const SCEVAddRecExpr );	Value expandAddRecExprLiterally(const SCEVAddRecExpr );
	PHINode getAddRecExprPHILiterally(const SCEVAddRecExpr Normalized,	PHINode getAddRecExprPHILiterally(const SCEVAddRecExpr Normalized,
	const Loop *L,	const Loop *L,
	Type *ExpandTy,	Type *ExpandTy,
	Type *IntTy);	Type *IntTy);

		Value expandIVInc(PHINode PN, Value StepV, const Loop L,
		Type ExpandTy, Type IntTy, bool useSubtract);
	};	};
	}	}

	#endif	#endif

End of changes. 8 change blocks.
	13 lines changed or deleted	29 lines changed or added

	ScalarEvolutionExpressions.h	ScalarEvolutionExpressions.h

	skipping to change at line 488	skipping to change at line 488
	return ((SC)this)->visitUnknown((const SCEVUnknown)S);	return ((SC)this)->visitUnknown((const SCEVUnknown)S);
	case scCouldNotCompute:	case scCouldNotCompute:
	return ((SC)this)->visitCouldNotCompute((const SCEVCouldNotCompute )S);	return ((SC)this)->visitCouldNotCompute((const SCEVCouldNotCompute )S);
	default:	default:
	llvm_unreachable("Unknown SCEV type!");	llvm_unreachable("Unknown SCEV type!");
	}	}
	}	}

	RetVal visitCouldNotCompute(const SCEVCouldNotCompute *S) {	RetVal visitCouldNotCompute(const SCEVCouldNotCompute *S) {
	llvm_unreachable("Invalid use of SCEVCouldNotCompute!");	llvm_unreachable("Invalid use of SCEVCouldNotCompute!");

	return RetVal();
	}	}
	};	};
	}	}

	#endif	#endif

End of changes. 1 change blocks.
	1 lines changed or deleted	0 lines changed or added

	ScheduleDAG.h	ScheduleDAG.h
	//===------- llvm/CodeGen/ScheduleDAG.h - Common Base Class------- C++ -- ===//	//===------- llvm/CodeGen/ScheduleDAG.h - Common Base Class------- C++ -- ===//
	//	//
	// The LLVM Compiler Infrastructure	// The LLVM Compiler Infrastructure
	//	//
	// This file is distributed under the University of Illinois Open Source	// This file is distributed under the University of Illinois Open Source
	// License. See LICENSE.TXT for details.	// License. See LICENSE.TXT for details.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	//	//
	// This file implements the ScheduleDAG class, which is used as the common	// This file implements the ScheduleDAG class, which is used as the common

	// base class for instruction schedulers.	// base class for instruction schedulers. This encapsulates the scheduling
		DAG,
		// which is shared between SelectionDAG and MachineInstr scheduling.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_CODEGEN_SCHEDULEDAG_H	#ifndef LLVM_CODEGEN_SCHEDULEDAG_H
	#define LLVM_CODEGEN_SCHEDULEDAG_H	#define LLVM_CODEGEN_SCHEDULEDAG_H

	#include "llvm/CodeGen/MachineBasicBlock.h"	#include "llvm/CodeGen/MachineBasicBlock.h"

	#include "llvm/Target/TargetMachine.h"	#include "llvm/Target/TargetLowering.h"
	#include "llvm/ADT/DenseMap.h"	#include "llvm/ADT/DenseMap.h"
	#include "llvm/ADT/BitVector.h"	#include "llvm/ADT/BitVector.h"
	#include "llvm/ADT/GraphTraits.h"	#include "llvm/ADT/GraphTraits.h"
	#include "llvm/ADT/SmallVector.h"	#include "llvm/ADT/SmallVector.h"
	#include "llvm/ADT/PointerIntPair.h"	#include "llvm/ADT/PointerIntPair.h"

	namespace llvm {	namespace llvm {
	class AliasAnalysis;	class AliasAnalysis;
	class SUnit;	class SUnit;
	class MachineConstantPool;	class MachineConstantPool;

	skipping to change at line 132	skipping to change at line 133
	case Data:	case Data:
	case Anti:	case Anti:
	case Output:	case Output:
	return Contents.Reg == Other.Contents.Reg;	return Contents.Reg == Other.Contents.Reg;
	case Order:	case Order:
	return Contents.Order.isNormalMemory ==	return Contents.Order.isNormalMemory ==
	Other.Contents.Order.isNormalMemory &&	Other.Contents.Order.isNormalMemory &&
	Contents.Order.isMustAlias == Other.Contents.Order.isMustAli as &&	Contents.Order.isMustAlias == Other.Contents.Order.isMustAli as &&
	Contents.Order.isArtificial == Other.Contents.Order.isArtifi cial;	Contents.Order.isArtificial == Other.Contents.Order.isArtifi cial;
	}	}

	assert(0 && "Invalid dependency kind!");	llvm_unreachable("Invalid dependency kind!");
	return false;
	}	}

	bool operator!=(const SDep &Other) const {	bool operator!=(const SDep &Other) const {
	return !operator==(Other);	return !operator==(Other);
	}	}

	/// getLatency - Return the latency value for this edge, which roughly	/// getLatency - Return the latency value for this edge, which roughly
	/// means the minimum number of cycles that must elapse between the	/// means the minimum number of cycles that must elapse between the
	/// predecessor and the successor, given that they have this edge	/// predecessor and the successor, given that they have this edge
	/// between them.	/// between them.

	skipping to change at line 235	skipping to change at line 235
	struct isPodLike<SDep> { static const bool value = true; };	struct isPodLike<SDep> { static const bool value = true; };

	/// SUnit - Scheduling unit. This is a node in the scheduling DAG.	/// SUnit - Scheduling unit. This is a node in the scheduling DAG.
	class SUnit {	class SUnit {
	private:	private:
	SDNode *Node; // Representative node.	SDNode *Node; // Representative node.
	MachineInstr *Instr; // Alternatively, a MachineInstr.	MachineInstr *Instr; // Alternatively, a MachineInstr.
	public:	public:
	SUnit *OrigNode; // If not this, the node from which	SUnit *OrigNode; // If not this, the node from which
	// this node was cloned.	// this node was cloned.

		// (SD scheduling only)

	// Preds/Succs - The SUnits before/after us in the graph.	// Preds/Succs - The SUnits before/after us in the graph.
	SmallVector<SDep, 4> Preds; // All sunit predecessors.	SmallVector<SDep, 4> Preds; // All sunit predecessors.
	SmallVector<SDep, 4> Succs; // All sunit successors.	SmallVector<SDep, 4> Succs; // All sunit successors.

	typedef SmallVector<SDep, 4>::iterator pred_iterator;	typedef SmallVector<SDep, 4>::iterator pred_iterator;
	typedef SmallVector<SDep, 4>::iterator succ_iterator;	typedef SmallVector<SDep, 4>::iterator succ_iterator;
	typedef SmallVector<SDep, 4>::const_iterator const_pred_iterator;	typedef SmallVector<SDep, 4>::const_iterator const_pred_iterator;
	typedef SmallVector<SDep, 4>::const_iterator const_succ_iterator;	typedef SmallVector<SDep, 4>::const_iterator const_succ_iterator;


	skipping to change at line 412	skipping to change at line 413
	}	}

	/// isSucc - Test if node N is a successor of this node.	/// isSucc - Test if node N is a successor of this node.
	bool isSucc(SUnit *N) {	bool isSucc(SUnit *N) {
	for (unsigned i = 0, e = (unsigned)Succs.size(); i != e; ++i)	for (unsigned i = 0, e = (unsigned)Succs.size(); i != e; ++i)
	if (Succs[i].getSUnit() == N)	if (Succs[i].getSUnit() == N)
	return true;	return true;
	return false;	return false;
	}	}


		bool isTopReady() const {
		return NumPredsLeft == 0;
		}
		bool isBottomReady() const {
		return NumSuccsLeft == 0;
		}

	void dump(const ScheduleDAG *G) const;	void dump(const ScheduleDAG *G) const;
	void dumpAll(const ScheduleDAG *G) const;	void dumpAll(const ScheduleDAG *G) const;
	void print(raw_ostream &O, const ScheduleDAG *G) const;	void print(raw_ostream &O, const ScheduleDAG *G) const;

	private:	private:
	void ComputeDepth();	void ComputeDepth();
	void ComputeHeight();	void ComputeHeight();
	};	};

	//===-------------------------------------------------------------------- ===//	//===-------------------------------------------------------------------- ===//
	/// SchedulingPriorityQueue - This interface is used to plug different	/// SchedulingPriorityQueue - This interface is used to plug different
	/// priorities computation algorithms into the list scheduler. It impleme nts	/// priorities computation algorithms into the list scheduler. It impleme nts
	/// the interface of a standard priority queue, where nodes are inserted in	/// the interface of a standard priority queue, where nodes are inserted in
	/// arbitrary order and returned in priority order. The computation of t he	/// arbitrary order and returned in priority order. The computation of t he
	/// priority and the representation of the queue are totally up to the	/// priority and the representation of the queue are totally up to the
	/// implementation to decide.	/// implementation to decide.
	///	///
	class SchedulingPriorityQueue {	class SchedulingPriorityQueue {

		virtual void anchor();
	unsigned CurCycle;	unsigned CurCycle;
	bool HasReadyFilter;	bool HasReadyFilter;
	public:	public:
	SchedulingPriorityQueue(bool rf = false):	SchedulingPriorityQueue(bool rf = false):
	CurCycle(0), HasReadyFilter(rf) {}	CurCycle(0), HasReadyFilter(rf) {}
	virtual ~SchedulingPriorityQueue() {}	virtual ~SchedulingPriorityQueue() {}

	virtual bool isBottomUp() const = 0;	virtual bool isBottomUp() const = 0;

	virtual void initNodes(std::vector<SUnit> &SUnits) = 0;	virtual void initNodes(std::vector<SUnit> &SUnits) = 0;

	skipping to change at line 468	skipping to change at line 477
	E = Nodes.end(); I != E; ++I)	E = Nodes.end(); I != E; ++I)
	push(*I);	push(*I);
	}	}

	virtual SUnit *pop() = 0;	virtual SUnit *pop() = 0;

	virtual void remove(SUnit *SU) = 0;	virtual void remove(SUnit *SU) = 0;

	virtual void dump(ScheduleDAG *) const {}	virtual void dump(ScheduleDAG *) const {}


	/// ScheduledNode - As each node is scheduled, this method is invoked. This	/// scheduledNode - As each node is scheduled, this method is invoked. This
	/// allows the priority function to adjust the priority of related	/// allows the priority function to adjust the priority of related
	/// unscheduled nodes, for example.	/// unscheduled nodes, for example.
	///	///

	virtual void ScheduledNode(SUnit *) {}	virtual void scheduledNode(SUnit *) {}


	virtual void UnscheduledNode(SUnit *) {}	virtual void unscheduledNode(SUnit *) {}

	void setCurCycle(unsigned Cycle) {	void setCurCycle(unsigned Cycle) {
	CurCycle = Cycle;	CurCycle = Cycle;
	}	}

	unsigned getCurCycle() const {	unsigned getCurCycle() const {
	return CurCycle;	return CurCycle;
	}	}
	};	};

	class ScheduleDAG {	class ScheduleDAG {
	public:	public:

	MachineBasicBlock *BB; // The block in which to insert instruc
	tions
	MachineBasicBlock::iterator InsertPos;// The position to insert instruc
	tions
	const TargetMachine &TM; // Target processor	const TargetMachine &TM; // Target processor
	const TargetInstrInfo *TII; // Target instruction information	const TargetInstrInfo *TII; // Target instruction information
	const TargetRegisterInfo *TRI; // Target processor register info	const TargetRegisterInfo *TRI; // Target processor register info
	MachineFunction &MF; // Machine function	MachineFunction &MF; // Machine function
	MachineRegisterInfo &MRI; // Virtual/real register map	MachineRegisterInfo &MRI; // Virtual/real register map

	std::vector<SUnit> Sequence; // The schedule. Null SUnit's
	// represent noop instructions.
	std::vector<SUnit> SUnits; // The scheduling units.	std::vector<SUnit> SUnits; // The scheduling units.
	SUnit EntrySU; // Special node for the region en try.	SUnit EntrySU; // Special node for the region en try.
	SUnit ExitSU; // Special node for the region ex it.	SUnit ExitSU; // Special node for the region ex it.

	#ifdef NDEBUG	#ifdef NDEBUG
	static const bool StressSched = false;	static const bool StressSched = false;
	#else	#else
	bool StressSched;	bool StressSched;
	#endif	#endif

	explicit ScheduleDAG(MachineFunction &mf);	explicit ScheduleDAG(MachineFunction &mf);

	virtual ~ScheduleDAG();	virtual ~ScheduleDAG();


		/// clearDAG - clear the DAG state (between regions).
		void clearDAG();

	/// getInstrDesc - Return the MCInstrDesc of this SUnit.	/// getInstrDesc - Return the MCInstrDesc of this SUnit.
	/// Return NULL for SDNodes without a machine opcode.	/// Return NULL for SDNodes without a machine opcode.
	const MCInstrDesc getInstrDesc(const SUnit SU) const {	const MCInstrDesc getInstrDesc(const SUnit SU) const {
	if (SU->isInstr()) return &SU->getInstr()->getDesc();	if (SU->isInstr()) return &SU->getInstr()->getDesc();
	return getNodeDesc(SU->getNode());	return getNodeDesc(SU->getNode());
	}	}

	/// viewGraph - Pop up a GraphViz/gv window with the ScheduleDAG render ed	/// viewGraph - Pop up a GraphViz/gv window with the ScheduleDAG render ed
	/// using 'dot'.	/// using 'dot'.
	///	///

		void viewGraph(const Twine &Name, const Twine &Title);
	void viewGraph();	void viewGraph();


	/// EmitSchedule - Insert MachineInstrs into the MachineBasicBlock
	/// according to the order specified in Sequence.
	///
	virtual MachineBasicBlock *EmitSchedule() = 0;

	void dumpSchedule() const;

	virtual void dumpNode(const SUnit *SU) const = 0;	virtual void dumpNode(const SUnit *SU) const = 0;

	/// getGraphNodeLabel - Return a label for an SUnit node in a visualiza tion	/// getGraphNodeLabel - Return a label for an SUnit node in a visualiza tion
	/// of the ScheduleDAG.	/// of the ScheduleDAG.
	virtual std::string getGraphNodeLabel(const SUnit *SU) const = 0;	virtual std::string getGraphNodeLabel(const SUnit *SU) const = 0;


		/// getDAGLabel - Return a label for the region of code covered by the
		DAG.
		virtual std::string getDAGName() const = 0;

	/// addCustomGraphFeatures - Add custom features for a visualization of	/// addCustomGraphFeatures - Add custom features for a visualization of
	/// the ScheduleDAG.	/// the ScheduleDAG.
	virtual void addCustomGraphFeatures(GraphWriter<ScheduleDAG*> &) const {}	virtual void addCustomGraphFeatures(GraphWriter<ScheduleDAG*> &) const {}

	#ifndef NDEBUG	#ifndef NDEBUG

	/// VerifySchedule - Verify that all SUnits were scheduled and that	/// VerifyScheduledDAG - Verify that all SUnits were scheduled and that
	/// their state is consistent.	/// their state is consistent. Return the number of scheduled SUnits.
	void VerifySchedule(bool isBottomUp);	unsigned VerifyScheduledDAG(bool isBottomUp);
	#endif	#endif

	protected:	protected:

	/// Run - perform scheduling.
	///
	void Run(MachineBasicBlock *bb, MachineBasicBlock::iterator insertPos);

	/// BuildSchedGraph - Build SUnits and set up their Preds and Succs
	/// to form the scheduling dependency graph.
	///
	virtual void BuildSchedGraph(AliasAnalysis *AA) = 0;

	/// ComputeLatency - Compute node latency.	/// ComputeLatency - Compute node latency.
	///	///

	virtual void ComputeLatency(SUnit *SU) = 0;	virtual void computeLatency(SUnit *SU) = 0;

	/// ComputeOperandLatency - Override dependence edge latency using	/// ComputeOperandLatency - Override dependence edge latency using
	/// operand use/def information	/// operand use/def information
	///	///

	virtual void ComputeOperandLatency(SUnit , SUnit ,	virtual void computeOperandLatency(SUnit , SUnit ,
	SDep&) const { }	SDep&) const { }


	/// Schedule - Order nodes according to selected style, filling
	/// in the Sequence member.
	///
	virtual void Schedule() = 0;

	/// ForceUnitLatencies - Return true if all scheduling edges should be given	/// ForceUnitLatencies - Return true if all scheduling edges should be given
	/// a latency value of one. The default is to return false; schedulers may	/// a latency value of one. The default is to return false; schedulers may
	/// override this as needed.	/// override this as needed.

	virtual bool ForceUnitLatencies() const { return false; }	virtual bool forceUnitLatencies() const { return false; }

	/// EmitNoop - Emit a noop instruction.
	///
	void EmitNoop();

	void EmitPhysRegCopy(SUnit SU, DenseMap<SUnit, unsigned> &VRBaseMap);

	private:	private:
	// Return the MCInstrDesc of this SDNode or NULL.	// Return the MCInstrDesc of this SDNode or NULL.
	const MCInstrDesc getNodeDesc(const SDNode Node) const;	const MCInstrDesc getNodeDesc(const SDNode Node) const;
	};	};

	class SUnitIterator : public std::iterator<std::forward_iterator_tag,	class SUnitIterator : public std::iterator<std::forward_iterator_tag,
	SUnit, ptrdiff_t> {	SUnit, ptrdiff_t> {
	SUnit *Node;	SUnit *Node;
	unsigned Operand;	unsigned Operand;

End of changes. 21 change blocks.
	46 lines changed or deleted	31 lines changed or added

	SchedulerRegistry.h	SchedulerRegistry.h

	skipping to change at line 70	skipping to change at line 70
	static void setListener(MachinePassRegistryListener *L) {	static void setListener(MachinePassRegistryListener *L) {
	Registry.setListener(L);	Registry.setListener(L);
	}	}
	};	};

	/// createBURRListDAGScheduler - This creates a bottom up register usage	/// createBURRListDAGScheduler - This creates a bottom up register usage
	/// reduction list scheduler.	/// reduction list scheduler.
	ScheduleDAGSDNodes createBURRListDAGScheduler(SelectionDAGISel IS,	ScheduleDAGSDNodes createBURRListDAGScheduler(SelectionDAGISel IS,
	CodeGenOpt::Level OptLevel);	CodeGenOpt::Level OptLevel);


	/// createTDRRListDAGScheduler - This creates a top down register usage
	/// reduction list scheduler.
	ScheduleDAGSDNodes createTDRRListDAGScheduler(SelectionDAGISel IS,
	CodeGenOpt::Level OptLevel);

	/// createBURRListDAGScheduler - This creates a bottom up list scheduler th at	/// createBURRListDAGScheduler - This creates a bottom up list scheduler th at
	/// schedules nodes in source code order when possible.	/// schedules nodes in source code order when possible.
	ScheduleDAGSDNodes createSourceListDAGScheduler(SelectionDAGISel IS,	ScheduleDAGSDNodes createSourceListDAGScheduler(SelectionDAGISel IS,
	CodeGenOpt::Level OptLevel );	CodeGenOpt::Level OptLevel );

	/// createHybridListDAGScheduler - This creates a bottom up register pressu re	/// createHybridListDAGScheduler - This creates a bottom up register pressu re
	/// aware list scheduler that make use of latency information to avoid stal ls	/// aware list scheduler that make use of latency information to avoid stal ls
	/// for long latency instructions in low register pressure mode. In high	/// for long latency instructions in low register pressure mode. In high
	/// register pressure mode it schedules to reduce register pressure.	/// register pressure mode it schedules to reduce register pressure.
	ScheduleDAGSDNodes createHybridListDAGScheduler(SelectionDAGISel IS,	ScheduleDAGSDNodes createHybridListDAGScheduler(SelectionDAGISel IS,
	CodeGenOpt::Level);	CodeGenOpt::Level);

	/// createILPListDAGScheduler - This creates a bottom up register pressure	/// createILPListDAGScheduler - This creates a bottom up register pressure
	/// aware list scheduler that tries to increase instruction level paralleli sm	/// aware list scheduler that tries to increase instruction level paralleli sm
	/// in low register pressure mode. In high register pressure mode it schedu les	/// in low register pressure mode. In high register pressure mode it schedu les
	/// to reduce register pressure.	/// to reduce register pressure.
	ScheduleDAGSDNodes createILPListDAGScheduler(SelectionDAGISel IS,	ScheduleDAGSDNodes createILPListDAGScheduler(SelectionDAGISel IS,
	CodeGenOpt::Level);	CodeGenOpt::Level);

	/// createTDListDAGScheduler - This creates a top-down list scheduler with
	/// a hazard recognizer.
	ScheduleDAGSDNodes createTDListDAGScheduler(SelectionDAGISel IS,
	CodeGenOpt::Level OptLevel);

	/// createFastDAGScheduler - This creates a "fast" scheduler.	/// createFastDAGScheduler - This creates a "fast" scheduler.
	///	///
	ScheduleDAGSDNodes createFastDAGScheduler(SelectionDAGISel IS,	ScheduleDAGSDNodes createFastDAGScheduler(SelectionDAGISel IS,
	CodeGenOpt::Level OptLevel);	CodeGenOpt::Level OptLevel);


		/// createVLIWDAGScheduler - Scheduler for VLIW targets. This creates top d
		own
		/// DFA driven list scheduler with clustering heuristic to control
		/// register pressure.
		ScheduleDAGSDNodes createVLIWDAGScheduler(SelectionDAGISel IS,
		CodeGenOpt::Level OptLevel);
	/// createDefaultScheduler - This creates an instruction scheduler appropri ate	/// createDefaultScheduler - This creates an instruction scheduler appropri ate
	/// for the target.	/// for the target.
	ScheduleDAGSDNodes createDefaultScheduler(SelectionDAGISel IS,	ScheduleDAGSDNodes createDefaultScheduler(SelectionDAGISel IS,
	CodeGenOpt::Level OptLevel);	CodeGenOpt::Level OptLevel);

	} // end namespace llvm	} // end namespace llvm

	#endif	#endif

End of changes. 3 change blocks.
	9 lines changed or deleted	6 lines changed or added

	SelectionDAGISel.h	SelectionDAGISel.h

	skipping to change at line 32	skipping to change at line 32

	namespace llvm {	namespace llvm {
	class FastISel;	class FastISel;
	class SelectionDAGBuilder;	class SelectionDAGBuilder;
	class SDValue;	class SDValue;
	class MachineRegisterInfo;	class MachineRegisterInfo;
	class MachineBasicBlock;	class MachineBasicBlock;
	class MachineFunction;	class MachineFunction;
	class MachineInstr;	class MachineInstr;
	class TargetLowering;	class TargetLowering;

		class TargetLibraryInfo;
	class TargetInstrInfo;	class TargetInstrInfo;
	class FunctionLoweringInfo;	class FunctionLoweringInfo;
	class ScheduleHazardRecognizer;	class ScheduleHazardRecognizer;
	class GCFunctionInfo;	class GCFunctionInfo;
	class ScheduleDAGSDNodes;	class ScheduleDAGSDNodes;
	class LoadInst;	class LoadInst;

	/// SelectionDAGISel - This is the common base class used for SelectionDAG- based	/// SelectionDAGISel - This is the common base class used for SelectionDAG- based
	/// pattern-matching instruction selectors.	/// pattern-matching instruction selectors.
	class SelectionDAGISel : public MachineFunctionPass {	class SelectionDAGISel : public MachineFunctionPass {
	public:	public:
	const TargetMachine &TM;	const TargetMachine &TM;
	const TargetLowering &TLI;	const TargetLowering &TLI;

		const TargetLibraryInfo *LibInfo;
	FunctionLoweringInfo *FuncInfo;	FunctionLoweringInfo *FuncInfo;
	MachineFunction *MF;	MachineFunction *MF;
	MachineRegisterInfo *RegInfo;	MachineRegisterInfo *RegInfo;
	SelectionDAG *CurDAG;	SelectionDAG *CurDAG;
	SelectionDAGBuilder *SDB;	SelectionDAGBuilder *SDB;
	AliasAnalysis *AA;	AliasAnalysis *AA;
	GCFunctionInfo *GFI;	GCFunctionInfo *GFI;
	CodeGenOpt::Level OptLevel;	CodeGenOpt::Level OptLevel;
	static char ID;	static char ID;


	skipping to change at line 95	skipping to change at line 97
	std::vector<SDValue> &OutOps) {	std::vector<SDValue> &OutOps) {
	return true;	return true;
	}	}

	/// IsProfitableToFold - Returns true if it's profitable to fold the spec ific	/// IsProfitableToFold - Returns true if it's profitable to fold the spec ific
	/// operand node N of U during instruction selection that starts at Root.	/// operand node N of U during instruction selection that starts at Root.
	virtual bool IsProfitableToFold(SDValue N, SDNode U, SDNode Root) const ;	virtual bool IsProfitableToFold(SDValue N, SDNode U, SDNode Root) const ;

	/// IsLegalToFold - Returns true if the specific operand node N of	/// IsLegalToFold - Returns true if the specific operand node N of
	/// U can be folded during instruction selection that starts at Root.	/// U can be folded during instruction selection that starts at Root.

	/// FIXME: This is a static member function because the MSP430/SystemZ/X8 6	/// FIXME: This is a static member function because the MSP430/X86
	/// targets, which uses it during isel. This could become a proper membe r.	/// targets, which uses it during isel. This could become a proper membe r.
	static bool IsLegalToFold(SDValue N, SDNode U, SDNode Root,	static bool IsLegalToFold(SDValue N, SDNode U, SDNode Root,
	CodeGenOpt::Level OptLevel,	CodeGenOpt::Level OptLevel,
	bool IgnoreChains = false);	bool IgnoreChains = false);

	// Opcodes used by the DAG state machine:	// Opcodes used by the DAG state machine:
	enum BuiltinOpcodes {	enum BuiltinOpcodes {
	OPC_Scope,	OPC_Scope,
	OPC_RecordNode,	OPC_RecordNode,
	OPC_RecordChild0, OPC_RecordChild1, OPC_RecordChild2, OPC_RecordChild3,	OPC_RecordChild0, OPC_RecordChild1, OPC_RecordChild2, OPC_RecordChild3,

	skipping to change at line 180	skipping to change at line 182
	unsigned DAGSize;	unsigned DAGSize;

	/// ISelPosition - Node iterator marking the current position of	/// ISelPosition - Node iterator marking the current position of
	/// instruction selection as it procedes through the topologically-sorted	/// instruction selection as it procedes through the topologically-sorted
	/// node list.	/// node list.
	SelectionDAG::allnodes_iterator ISelPosition;	SelectionDAG::allnodes_iterator ISelPosition;

	/// ISelUpdater - helper class to handle updates of the	/// ISelUpdater - helper class to handle updates of the
	/// instruction selection graph.	/// instruction selection graph.
	class ISelUpdater : public SelectionDAG::DAGUpdateListener {	class ISelUpdater : public SelectionDAG::DAGUpdateListener {

		virtual void anchor();
	SelectionDAG::allnodes_iterator &ISelPosition;	SelectionDAG::allnodes_iterator &ISelPosition;
	public:	public:
	explicit ISelUpdater(SelectionDAG::allnodes_iterator &isp)	explicit ISelUpdater(SelectionDAG::allnodes_iterator &isp)
	: ISelPosition(isp) {}	: ISelPosition(isp) {}

	/// NodeDeleted - Handle nodes deleted from the graph. If the	/// NodeDeleted - Handle nodes deleted from the graph. If the
	/// node being deleted is the current ISelPosition node, update	/// node being deleted is the current ISelPosition node, update
	/// ISelPosition.	/// ISelPosition.
	///	///
	virtual void NodeDeleted(SDNode N, SDNode E) {	virtual void NodeDeleted(SDNode N, SDNode E) {

	skipping to change at line 235	skipping to change at line 238
	bool CheckAndMask(SDValue LHS, ConstantSDNode *RHS,	bool CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
	int64_t DesiredMaskS) const;	int64_t DesiredMaskS) const;
	bool CheckOrMask(SDValue LHS, ConstantSDNode *RHS,	bool CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
	int64_t DesiredMaskS) const;	int64_t DesiredMaskS) const;

	/// CheckPatternPredicate - This function is generated by tblgen in the	/// CheckPatternPredicate - This function is generated by tblgen in the
	/// target. It runs the specified pattern predicate and returns true if it	/// target. It runs the specified pattern predicate and returns true if it
	/// succeeds or false if it fails. The number is a private implementatio n	/// succeeds or false if it fails. The number is a private implementatio n
	/// detail to the code tblgen produces.	/// detail to the code tblgen produces.
	virtual bool CheckPatternPredicate(unsigned PredNo) const {	virtual bool CheckPatternPredicate(unsigned PredNo) const {

	assert(0 && "Tblgen should generate the implementation of this!");	llvm_unreachable("Tblgen should generate the implementation of this!");
	return 0;
	}	}

	/// CheckNodePredicate - This function is generated by tblgen in the targ et.	/// CheckNodePredicate - This function is generated by tblgen in the targ et.
	/// It runs node predicate number PredNo and returns true if it succeeds or	/// It runs node predicate number PredNo and returns true if it succeeds or
	/// false if it fails. The number is a private implementation	/// false if it fails. The number is a private implementation
	/// detail to the code tblgen produces.	/// detail to the code tblgen produces.
	virtual bool CheckNodePredicate(SDNode *N, unsigned PredNo) const {	virtual bool CheckNodePredicate(SDNode *N, unsigned PredNo) const {

	assert(0 && "Tblgen should generate the implementation of this!");	llvm_unreachable("Tblgen should generate the implementation of this!");
	return 0;
	}	}

	virtual bool CheckComplexPattern(SDNode Root, SDNode Parent, SDValue N,	virtual bool CheckComplexPattern(SDNode Root, SDNode Parent, SDValue N,
	unsigned PatternNo,	unsigned PatternNo,
	SmallVectorImpl<std::pair<SDValue, SDNode*> > &Resu lt) {	SmallVectorImpl<std::pair<SDValue, SDNode*> > &Resu lt) {

	assert(0 && "Tblgen should generate the implementation of this!");	llvm_unreachable("Tblgen should generate the implementation of this!");
	return false;
	}	}

	virtual SDValue RunSDNodeXForm(SDValue V, unsigned XFormNo) {	virtual SDValue RunSDNodeXForm(SDValue V, unsigned XFormNo) {

	assert(0 && "Tblgen should generate this!");	llvm_unreachable("Tblgen should generate this!");
	return SDValue();
	}	}

	SDNode SelectCodeCommon(SDNode NodeToMatch,	SDNode SelectCodeCommon(SDNode NodeToMatch,
	const unsigned char *MatcherTable,	const unsigned char *MatcherTable,
	unsigned TableSize);	unsigned TableSize);

	private:	private:

	// Calls to these functions are generated by tblgen.	// Calls to these functions are generated by tblgen.
	SDNode Select_INLINEASM(SDNode N);	SDNode Select_INLINEASM(SDNode N);

End of changes. 8 change blocks.
	9 lines changed or deleted	8 lines changed or added

	SelectionDAGNodes.h	SelectionDAGNodes.h

	skipping to change at line 911	skipping to change at line 911
	/// encoding of the volatile flag, as well as bits used by subclasses. Th is	/// encoding of the volatile flag, as well as bits used by subclasses. Th is
	/// function should only be used to compute a FoldingSetNodeID value.	/// function should only be used to compute a FoldingSetNodeID value.
	unsigned getRawSubclassData() const {	unsigned getRawSubclassData() const {
	return SubclassData;	return SubclassData;
	}	}

	// We access subclass data here so that we can check consistency	// We access subclass data here so that we can check consistency
	// with MachineMemOperand information.	// with MachineMemOperand information.
	bool isVolatile() const { return (SubclassData >> 5) & 1; }	bool isVolatile() const { return (SubclassData >> 5) & 1; }
	bool isNonTemporal() const { return (SubclassData >> 6) & 1; }	bool isNonTemporal() const { return (SubclassData >> 6) & 1; }

		bool isInvariant() const { return (SubclassData >> 7) & 1; }

	AtomicOrdering getOrdering() const {	AtomicOrdering getOrdering() const {

	return AtomicOrdering((SubclassData >> 7) & 15);	return AtomicOrdering((SubclassData >> 8) & 15);
	}	}
	SynchronizationScope getSynchScope() const {	SynchronizationScope getSynchScope() const {

	return SynchronizationScope((SubclassData >> 11) & 1);	return SynchronizationScope((SubclassData >> 12) & 1);
	}	}

	/// Returns the SrcValue and offset that describes the location of the ac cess	/// Returns the SrcValue and offset that describes the location of the ac cess
	const Value *getSrcValue() const { return MMO->getValue(); }	const Value *getSrcValue() const { return MMO->getValue(); }
	int64_t getSrcValueOffset() const { return MMO->getOffset(); }	int64_t getSrcValueOffset() const { return MMO->getOffset(); }

	/// Returns the TBAAInfo that describes the dereference.	/// Returns the TBAAInfo that describes the dereference.
	const MDNode *getTBAAInfo() const { return MMO->getTBAAInfo(); }	const MDNode *getTBAAInfo() const { return MMO->getTBAAInfo(); }


		/// Returns the Ranges that describes the dereference.
		const MDNode *getRanges() const { return MMO->getRanges(); }

	/// getMemoryVT - Return the type of the in-memory value.	/// getMemoryVT - Return the type of the in-memory value.
	EVT getMemoryVT() const { return MemoryVT; }	EVT getMemoryVT() const { return MemoryVT; }

	/// getMemOperand - Return a MachineMemOperand object describing the memo ry	/// getMemOperand - Return a MachineMemOperand object describing the memo ry
	/// reference performed by operation.	/// reference performed by operation.
	MachineMemOperand *getMemOperand() const { return MMO; }	MachineMemOperand *getMemOperand() const { return MMO; }

	const MachinePointerInfo &getPointerInfo() const {	const MachinePointerInfo &getPointerInfo() const {
	return MMO->getPointerInfo();	return MMO->getPointerInfo();
	}	}

	skipping to change at line 987	skipping to change at line 991
	///	///
	class AtomicSDNode : public MemSDNode {	class AtomicSDNode : public MemSDNode {
	SDUse Ops[4];	SDUse Ops[4];

	void InitAtomic(AtomicOrdering Ordering, SynchronizationScope SynchScope) {	void InitAtomic(AtomicOrdering Ordering, SynchronizationScope SynchScope) {
	// This must match encodeMemSDNodeFlags() in SelectionDAG.cpp.	// This must match encodeMemSDNodeFlags() in SelectionDAG.cpp.
	assert((Ordering & 15) == Ordering &&	assert((Ordering & 15) == Ordering &&
	"Ordering may not require more than 4 bits!");	"Ordering may not require more than 4 bits!");
	assert((SynchScope & 1) == SynchScope &&	assert((SynchScope & 1) == SynchScope &&
	"SynchScope may not require more than 1 bit!");	"SynchScope may not require more than 1 bit!");

	SubclassData \|= Ordering << 7;	SubclassData \|= Ordering << 8;
	SubclassData \|= SynchScope << 11;	SubclassData \|= SynchScope << 12;
	assert(getOrdering() == Ordering && "Ordering encoding error!");	assert(getOrdering() == Ordering && "Ordering encoding error!");
	assert(getSynchScope() == SynchScope && "Synch-scope encoding error!");	assert(getSynchScope() == SynchScope && "Synch-scope encoding error!");

	assert((readMem() \|\| getOrdering() <= Monotonic) &&	assert((readMem() \|\| getOrdering() <= Monotonic) &&
	"Acquire/Release MachineMemOperand must be a load!");	"Acquire/Release MachineMemOperand must be a load!");
	assert((writeMem() \|\| getOrdering() <= Monotonic) &&	assert((writeMem() \|\| getOrdering() <= Monotonic) &&
	"Acquire/Release MachineMemOperand must be a store!");	"Acquire/Release MachineMemOperand must be a store!");
	}	}

	public:	public:

	skipping to change at line 1107	skipping to change at line 1111
	const int *Mask;	const int *Mask;
	protected:	protected:
	friend class SelectionDAG;	friend class SelectionDAG;
	ShuffleVectorSDNode(EVT VT, DebugLoc dl, SDValue N1, SDValue N2,	ShuffleVectorSDNode(EVT VT, DebugLoc dl, SDValue N1, SDValue N2,
	const int *M)	const int *M)
	: SDNode(ISD::VECTOR_SHUFFLE, dl, getSDVTList(VT)), Mask(M) {	: SDNode(ISD::VECTOR_SHUFFLE, dl, getSDVTList(VT)), Mask(M) {
	InitOperands(Ops, N1, N2);	InitOperands(Ops, N1, N2);
	}	}
	public:	public:


	void getMask(SmallVectorImpl<int> &M) const {	ArrayRef<int> getMask() const {
	EVT VT = getValueType(0);	EVT VT = getValueType(0);

	M.clear();	return makeArrayRef(Mask, VT.getVectorNumElements());
	for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
	M.push_back(Mask[i]);
	}	}
	int getMaskElt(unsigned Idx) const {	int getMaskElt(unsigned Idx) const {
	assert(Idx < getValueType(0).getVectorNumElements() && "Idx out of rang e!");	assert(Idx < getValueType(0).getVectorNumElements() && "Idx out of rang e!");
	return Mask[Idx];	return Mask[Idx];
	}	}

	bool isSplat() const { return isSplatMask(Mask, getValueType(0)); }	bool isSplat() const { return isSplatMask(Mask, getValueType(0)); }
	int getSplatIndex() const {	int getSplatIndex() const {
	assert(isSplat() && "Cannot get splat index for non-splat!");	assert(isSplat() && "Cannot get splat index for non-splat!");
	EVT VT = getValueType(0);	EVT VT = getValueType(0);

	skipping to change at line 1426	skipping to change at line 1428
	public:	public:

	unsigned getReg() const { return Reg; }	unsigned getReg() const { return Reg; }

	static bool classof(const RegisterSDNode *) { return true; }	static bool classof(const RegisterSDNode *) { return true; }
	static bool classof(const SDNode *N) {	static bool classof(const SDNode *N) {
	return N->getOpcode() == ISD::Register;	return N->getOpcode() == ISD::Register;
	}	}
	};	};


		class RegisterMaskSDNode : public SDNode {
		// The memory for RegMask is not owned by the node.
		const uint32_t *RegMask;
		friend class SelectionDAG;
		RegisterMaskSDNode(const uint32_t *mask)
		: SDNode(ISD::RegisterMask, DebugLoc(), getSDVTList(MVT::Untyped)),
		RegMask(mask) {}
		public:

		const uint32_t *getRegMask() const { return RegMask; }

		static bool classof(const RegisterMaskSDNode *) { return true; }
		static bool classof(const SDNode *N) {
		return N->getOpcode() == ISD::RegisterMask;
		}
		};

	class BlockAddressSDNode : public SDNode {	class BlockAddressSDNode : public SDNode {
	const BlockAddress *BA;	const BlockAddress *BA;
	unsigned char TargetFlags;	unsigned char TargetFlags;
	friend class SelectionDAG;	friend class SelectionDAG;
	BlockAddressSDNode(unsigned NodeTy, EVT VT, const BlockAddress *ba,	BlockAddressSDNode(unsigned NodeTy, EVT VT, const BlockAddress *ba,
	unsigned char Flags)	unsigned char Flags)
	: SDNode(NodeTy, DebugLoc(), getSDVTList(VT)),	: SDNode(NodeTy, DebugLoc(), getSDVTList(VT)),
	BA(ba), TargetFlags(Flags) {	BA(ba), TargetFlags(Flags) {
	}	}
	public:	public:

	skipping to change at line 1676	skipping to change at line 1695
	mmo_iterator MemRefsEnd;	mmo_iterator MemRefsEnd;

	public:	public:
	mmo_iterator memoperands_begin() const { return MemRefs; }	mmo_iterator memoperands_begin() const { return MemRefs; }
	mmo_iterator memoperands_end() const { return MemRefsEnd; }	mmo_iterator memoperands_end() const { return MemRefsEnd; }
	bool memoperands_empty() const { return MemRefsEnd == MemRefs; }	bool memoperands_empty() const { return MemRefsEnd == MemRefs; }

	/// setMemRefs - Assign this MachineSDNodes's memory reference descriptor	/// setMemRefs - Assign this MachineSDNodes's memory reference descriptor
	/// list. This does not transfer ownership.	/// list. This does not transfer ownership.
	void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd) {	void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd) {

		for (mmo_iterator MMI = NewMemRefs, MME = NewMemRefsEnd; MMI != MME; ++
		MMI)
		assert(*MMI && "Null mem ref detected!");
	MemRefs = NewMemRefs;	MemRefs = NewMemRefs;
	MemRefsEnd = NewMemRefsEnd;	MemRefsEnd = NewMemRefsEnd;
	}	}

	static bool classof(const MachineSDNode *) { return true; }	static bool classof(const MachineSDNode *) { return true; }
	static bool classof(const SDNode *N) {	static bool classof(const SDNode *N) {
	return N->isMachineOpcode();	return N->isMachineOpcode();
	}	}
	};	};


End of changes. 9 change blocks.
	8 lines changed or deleted	30 lines changed or added

	SetVector.h	SetVector.h

	skipping to change at line 147	skipping to change at line 147
	vector_.clear();	vector_.clear();
	}	}

	/// @brief Remove the last element of the SetVector.	/// @brief Remove the last element of the SetVector.
	void pop_back() {	void pop_back() {
	assert(!empty() && "Cannot remove an element from an empty SetVector!") ;	assert(!empty() && "Cannot remove an element from an empty SetVector!") ;
	set_.erase(back());	set_.erase(back());
	vector_.pop_back();	vector_.pop_back();
	}	}


		T pop_back_val() {
		T Ret = back();
		pop_back();
		return Ret;
		}

	bool operator==(const SetVector &that) const {	bool operator==(const SetVector &that) const {
	return vector_ == that.vector_;	return vector_ == that.vector_;
	}	}

	bool operator!=(const SetVector &that) const {	bool operator!=(const SetVector &that) const {
	return vector_ != that.vector_;	return vector_ != that.vector_;
	}	}

	private:	private:
	set_type set_; ///< The set.	set_type set_; ///< The set.

End of changes. 1 change blocks.
	0 lines changed or deleted	6 lines changed or added

	SimplifyIndVar.h	SimplifyIndVar.h

	skipping to change at line 20	skipping to change at line 20
	// This file defines in interface for induction variable simplification. It does	// This file defines in interface for induction variable simplification. It does
	// not define any actual pass or policy, but provides a single function to	// not define any actual pass or policy, but provides a single function to
	// simplify a loop's induction variables based on ScalarEvolution.	// simplify a loop's induction variables based on ScalarEvolution.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_TRANSFORMS_UTILS_SIMPLIFYINDVAR_H	#ifndef LLVM_TRANSFORMS_UTILS_SIMPLIFYINDVAR_H
	#define LLVM_TRANSFORMS_UTILS_SIMPLIFYINDVAR_H	#define LLVM_TRANSFORMS_UTILS_SIMPLIFYINDVAR_H

	#include "llvm/Support/CommandLine.h"	#include "llvm/Support/CommandLine.h"

		#include "llvm/Support/ValueHandle.h"

	namespace llvm {	namespace llvm {

	extern cl::opt<bool> DisableIVRewrite;	extern cl::opt<bool> DisableIVRewrite;


		class CastInst;
		class IVUsers;
	class Loop;	class Loop;

	class LoopInfo;
	class DominatorTree;
	class ScalarEvolution;
	class LPPassManager;	class LPPassManager;

	class IVUsers;	class PHINode;
		class ScalarEvolution;

	/// Interface for visiting interesting IV users that are recognized but not	/// Interface for visiting interesting IV users that are recognized but not
	/// simplified by this utility.	/// simplified by this utility.
	class IVVisitor {	class IVVisitor {

		virtual void anchor();
	public:	public:
	virtual ~IVVisitor() {}	virtual ~IVVisitor() {}
	virtual void visitCast(CastInst *Cast) = 0;	virtual void visitCast(CastInst *Cast) = 0;
	};	};

	/// simplifyUsersOfIV - Simplify instructions that use this induction varia ble	/// simplifyUsersOfIV - Simplify instructions that use this induction varia ble
	/// by using ScalarEvolution to analyze the IV's recurrence.	/// by using ScalarEvolution to analyze the IV's recurrence.
	bool simplifyUsersOfIV(PHINode CurrIV, ScalarEvolution SE, LPPassManager *LPM,	bool simplifyUsersOfIV(PHINode CurrIV, ScalarEvolution SE, LPPassManager *LPM,
	SmallVectorImpl<WeakVH> &Dead, IVVisitor *V = NULL);	SmallVectorImpl<WeakVH> &Dead, IVVisitor *V = NULL);

	/// SimplifyLoopIVs - Simplify users of induction variables within this	/// SimplifyLoopIVs - Simplify users of induction variables within this
	/// loop. This does not actually change or add IVs.	/// loop. This does not actually change or add IVs.
	bool simplifyLoopIVs(Loop L, ScalarEvolution SE, LPPassManager *LPM,	bool simplifyLoopIVs(Loop L, ScalarEvolution SE, LPPassManager *LPM,
	SmallVectorImpl<WeakVH> &Dead);	SmallVectorImpl<WeakVH> &Dead);


	/// simplifyIVUsers - Simplify instructions recorded by the IVUsers pass.
	/// This is a legacy implementation to reproduce the behavior of the
	/// IndVarSimplify pass prior to DisableIVRewrite.
	bool simplifyIVUsers(IVUsers IU, ScalarEvolution SE, LPPassManager *LPM,
	SmallVectorImpl<WeakVH> &Dead);

	} // namespace llvm	} // namespace llvm

	#endif	#endif

End of changes. 6 change blocks.
	10 lines changed or deleted	6 lines changed or added

	SlotIndexes.h	SlotIndexes.h

	skipping to change at line 22	skipping to change at line 22
	// be live.	// be live.
	//	//
	// SlotIndex is mostly a proxy for entries of the SlotIndexList, a class wh ich	// SlotIndex is mostly a proxy for entries of the SlotIndexList, a class wh ich
	// is held is LiveIntervals and provides the real numbering. This allows	// is held is LiveIntervals and provides the real numbering. This allows
	// LiveIntervals to perform largely transparent renumbering.	// LiveIntervals to perform largely transparent renumbering.
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_CODEGEN_SLOTINDEXES_H	#ifndef LLVM_CODEGEN_SLOTINDEXES_H
	#define LLVM_CODEGEN_SLOTINDEXES_H	#define LLVM_CODEGEN_SLOTINDEXES_H


	#include "llvm/CodeGen/MachineBasicBlock.h"	#include "llvm/CodeGen/MachineInstrBundle.h"
	#include "llvm/CodeGen/MachineFunction.h"	#include "llvm/CodeGen/MachineFunction.h"
	#include "llvm/CodeGen/MachineFunctionPass.h"	#include "llvm/CodeGen/MachineFunctionPass.h"
	#include "llvm/ADT/PointerIntPair.h"	#include "llvm/ADT/PointerIntPair.h"

		#include "llvm/ADT/ilist.h"
	#include "llvm/ADT/SmallVector.h"	#include "llvm/ADT/SmallVector.h"
	#include "llvm/ADT/DenseMap.h"	#include "llvm/ADT/DenseMap.h"
	#include "llvm/Support/Allocator.h"	#include "llvm/Support/Allocator.h"

	namespace llvm {	namespace llvm {

	/// This class represents an entry in the slot index list held in the	/// This class represents an entry in the slot index list held in the
	/// SlotIndexes pass. It should not be used directly. See the	/// SlotIndexes pass. It should not be used directly. See the
	/// SlotIndex & SlotIndexes classes for the public interface to this	/// SlotIndex & SlotIndexes classes for the public interface to this
	/// information.	/// information.

	class IndexListEntry {	class IndexListEntry : public ilist_node<IndexListEntry> {
	IndexListEntry next, prev;
	MachineInstr *mi;	MachineInstr *mi;
	unsigned index;	unsigned index;

	public:	public:

	IndexListEntry(MachineInstr *mi, unsigned index) : mi(mi), index(index) {}	IndexListEntry(MachineInstr *mi, unsigned index) : mi(mi), index(index) {}

	MachineInstr* getInstr() const { return mi; }	MachineInstr* getInstr() const { return mi; }
	void setInstr(MachineInstr *mi) {	void setInstr(MachineInstr *mi) {
	this->mi = mi;	this->mi = mi;
	}	}

	unsigned getIndex() const { return index; }	unsigned getIndex() const { return index; }
	void setIndex(unsigned index) {	void setIndex(unsigned index) {
	this->index = index;	this->index = index;
	}	}


	IndexListEntry* getNext() { return next; }
	const IndexListEntry* getNext() const { return next; }
	void setNext(IndexListEntry *next) {
	this->next = next;
	}

	IndexListEntry* getPrev() { return prev; }
	const IndexListEntry* getPrev() const { return prev; }
	void setPrev(IndexListEntry *prev) {
	this->prev = prev;
	}
	};	};


	// Specialize PointerLikeTypeTraits for IndexListEntry.
	template <>	template <>

	class PointerLikeTypeTraits<IndexListEntry*> {	struct ilist_traits<IndexListEntry> : public ilist_default_traits<IndexLi
		stEntry> {
		private:
		mutable ilist_half_node<IndexListEntry> Sentinel;
	public:	public:

	static inline void* getAsVoidPointer(IndexListEntry *p) {	IndexListEntry *createSentinel() const {
	return p;	return static_cast<IndexListEntry*>(&Sentinel);
	}	}

	static inline IndexListEntry* getFromVoidPointer(void *p) {	void destroySentinel(IndexListEntry *) const {}
	return static_cast<IndexListEntry*>(p);
	}	IndexListEntry *provideInitialHead() const { return createSentinel(); }
	enum { NumLowBitsAvailable = 3 };	IndexListEntry ensureHead(IndexListEntry) const { return createSentin
		el(); }
		static void noteHead(IndexListEntry, IndexListEntry) {}
		void deleteNode(IndexListEntry *N) {}

		private:
		void createNode(const IndexListEntry &);
	};	};

	/// SlotIndex - An opaque wrapper around machine indexes.	/// SlotIndex - An opaque wrapper around machine indexes.
	class SlotIndex {	class SlotIndex {
	friend class SlotIndexes;	friend class SlotIndexes;
	friend struct DenseMapInfo<SlotIndex>;	friend struct DenseMapInfo<SlotIndex>;


	enum Slot { LOAD, USE, DEF, STORE, NUM };	enum Slot {
		/// Basic block boundary. Used for live ranges entering and leaving
		a
		/// block without being live in the layout neighbor. Also used as th
		e
		/// def slot of PHI-defs.
		Slot_Block,

		/// Early-clobber register use/def slot. A live range defined at
		/// Slot_EarlyCLobber interferes with normal live ranges killed at
		/// Slot_Register. Also used as the kill slot for live ranges tied t
		o an
		/// early-clobber def.
		Slot_EarlyClobber,

		/// Normal register use/def slot. Normal instructions kill and defin
		e
		/// register live ranges at this slot.
		Slot_Register,

		/// Dead def kill point. Kill slot for a live range that is defined
		by
		/// the same instruction (Slot_Register or Slot_EarlyClobber), but is
		n't
		/// used anywhere.
		Slot_Dead,

		Slot_Count
		};

	PointerIntPair<IndexListEntry*, 2, unsigned> lie;	PointerIntPair<IndexListEntry*, 2, unsigned> lie;

	SlotIndex(IndexListEntry *entry, unsigned slot)	SlotIndex(IndexListEntry *entry, unsigned slot)
	: lie(entry, slot) {}	: lie(entry, slot) {}


	IndexListEntry& entry() const {	IndexListEntry* listEntry() const {
	assert(isValid() && "Attempt to compare reserved index.");	assert(isValid() && "Attempt to compare reserved index.");

	return *lie.getPointer();	return lie.getPointer();
	}	}

	int getIndex() const {	int getIndex() const {

	return entry().getIndex() \| getSlot();	return listEntry()->getIndex() \| getSlot();
	}	}

	/// Returns the slot for this SlotIndex.	/// Returns the slot for this SlotIndex.
	Slot getSlot() const {	Slot getSlot() const {
	return static_cast<Slot>(lie.getInt());	return static_cast<Slot>(lie.getInt());
	}	}

	static inline unsigned getHashValue(const SlotIndex &v) {	static inline unsigned getHashValue(const SlotIndex &v) {
	void *ptrVal = v.lie.getOpaqueValue();	void *ptrVal = v.lie.getOpaqueValue();
	return (unsigned((intptr_t)ptrVal)) ^ (unsigned((intptr_t)ptrVal) >> 9);	return (unsigned((intptr_t)ptrVal)) ^ (unsigned((intptr_t)ptrVal) >> 9);
	}	}

	public:	public:
	enum {	enum {
	/// The default distance between instructions as returned by distance ().	/// The default distance between instructions as returned by distance ().
	/// This may vary as instructions are inserted and removed.	/// This may vary as instructions are inserted and removed.

	InstrDist = 4*NUM	InstrDist = 4 * Slot_Count
	};	};

	static inline SlotIndex getEmptyKey() {	static inline SlotIndex getEmptyKey() {
	return SlotIndex(0, 1);	return SlotIndex(0, 1);
	}	}

	static inline SlotIndex getTombstoneKey() {	static inline SlotIndex getTombstoneKey() {
	return SlotIndex(0, 2);	return SlotIndex(0, 2);
	}	}

	/// Construct an invalid index.	/// Construct an invalid index.
	SlotIndex() : lie(0, 0) {}	SlotIndex() : lie(0, 0) {}

	// Construct a new slot index from the given one, and set the slot.	// Construct a new slot index from the given one, and set the slot.

	SlotIndex(const SlotIndex &li, Slot s)	SlotIndex(const SlotIndex &li, Slot s) : lie(li.listEntry(), unsigned(s
	: lie(&li.entry(), unsigned(s)) {	)) {
	assert(lie.getPointer() != 0 &&	assert(lie.getPointer() != 0 &&
	"Attempt to construct index with 0 pointer.");	"Attempt to construct index with 0 pointer.");
	}	}

	/// Returns true if this is a valid index. Invalid indicies do	/// Returns true if this is a valid index. Invalid indicies do
	/// not point into an index table, and cannot be compared.	/// not point into an index table, and cannot be compared.
	bool isValid() const {	bool isValid() const {
	return lie.getPointer();	return lie.getPointer();
	}	}


	skipping to change at line 189	skipping to change at line 205
	/// is greater than, or equal to, the second.	/// is greater than, or equal to, the second.
	bool operator>=(SlotIndex other) const {	bool operator>=(SlotIndex other) const {
	return getIndex() >= other.getIndex();	return getIndex() >= other.getIndex();
	}	}

	/// isSameInstr - Return true if A and B refer to the same instruction.	/// isSameInstr - Return true if A and B refer to the same instruction.
	static bool isSameInstr(SlotIndex A, SlotIndex B) {	static bool isSameInstr(SlotIndex A, SlotIndex B) {
	return A.lie.getPointer() == B.lie.getPointer();	return A.lie.getPointer() == B.lie.getPointer();
	}	}


		/// isEarlierInstr - Return true if A refers to an instruction earlier
		than
		/// B. This is equivalent to A < B && !isSameInstr(A, B).
		static bool isEarlierInstr(SlotIndex A, SlotIndex B) {
		return A.listEntry()->getIndex() < B.listEntry()->getIndex();
		}

	/// Return the distance from this index to the given one.	/// Return the distance from this index to the given one.
	int distance(SlotIndex other) const {	int distance(SlotIndex other) const {
	return other.getIndex() - getIndex();	return other.getIndex() - getIndex();
	}	}


	/// isLoad - Return true if this is a LOAD slot.	/// isBlock - Returns true if this is a block boundary slot.
	bool isLoad() const {	bool isBlock() const { return getSlot() == Slot_Block; }
	return getSlot() == LOAD;
	}


	/// isDef - Return true if this is a DEF slot.	/// isEarlyClobber - Returns true if this is an early-clobber slot.
	bool isDef() const {	bool isEarlyClobber() const { return getSlot() == Slot_EarlyClobber; }
	return getSlot() == DEF;
	}


	/// isUse - Return true if this is a USE slot.	/// isRegister - Returns true if this is a normal register use/def slot
	bool isUse() const {	.
	return getSlot() == USE;	/// Note that early-clobber slots may also be used for uses and defs.
	}	bool isRegister() const { return getSlot() == Slot_Register; }


	/// isStore - Return true if this is a STORE slot.	/// isDead - Returns true if this is a dead def kill slot.
	bool isStore() const {	bool isDead() const { return getSlot() == Slot_Dead; }
	return getSlot() == STORE;
	}

	/// Returns the base index for associated with this index. The base ind ex	/// Returns the base index for associated with this index. The base ind ex

	/// is the one associated with the LOAD slot for the instruction pointe	/// is the one associated with the Slot_Block slot for the instruction
	d to	/// pointed to by this index.
	/// by this index.
	SlotIndex getBaseIndex() const {	SlotIndex getBaseIndex() const {

	return getLoadIndex();	return SlotIndex(listEntry(), Slot_Block);
	}	}

	/// Returns the boundary index for associated with this index. The boun dary	/// Returns the boundary index for associated with this index. The boun dary

	/// index is the one associated with the LOAD slot for the instruction	/// index is the one associated with the Slot_Block slot for the instru ction
	/// pointed to by this index.	/// pointed to by this index.
	SlotIndex getBoundaryIndex() const {	SlotIndex getBoundaryIndex() const {

	return getStoreIndex();	return SlotIndex(listEntry(), Slot_Dead);
	}	}


	/// Returns the index of the LOAD slot for the instruction pointed to b	/// Returns the register use/def slot in the current instruction for a
	y	/// normal or early-clobber def.
	/// this index.	SlotIndex getRegSlot(bool EC = false) const {
	SlotIndex getLoadIndex() const {	return SlotIndex(listEntry(), EC ? Slot_EarlyClobber : Slot_Register)
	return SlotIndex(&entry(), SlotIndex::LOAD);	;
	}	}


	/// Returns the index of the USE slot for the instruction pointed to by	/// Returns the dead def kill slot for the current instruction.
	/// this index.	SlotIndex getDeadSlot() const {
	SlotIndex getUseIndex() const {	return SlotIndex(listEntry(), Slot_Dead);
	return SlotIndex(&entry(), SlotIndex::USE);
	}

	/// Returns the index of the DEF slot for the instruction pointed to by
	/// this index.
	SlotIndex getDefIndex() const {
	return SlotIndex(&entry(), SlotIndex::DEF);
	}

	/// Returns the index of the STORE slot for the instruction pointed to
	by
	/// this index.
	SlotIndex getStoreIndex() const {
	return SlotIndex(&entry(), SlotIndex::STORE);
	}	}

	/// Returns the next slot in the index list. This could be either the	/// Returns the next slot in the index list. This could be either the
	/// next slot for the instruction pointed to by this index or, if this	/// next slot for the instruction pointed to by this index or, if this
	/// index is a STORE, the first slot for the next instruction.	/// index is a STORE, the first slot for the next instruction.
	/// WARNING: This method is considerably more expensive than the method s	/// WARNING: This method is considerably more expensive than the method s
	/// that return specific slots (getUseIndex(), etc). If you can - pleas e	/// that return specific slots (getUseIndex(), etc). If you can - pleas e
	/// use one of those methods.	/// use one of those methods.
	SlotIndex getNextSlot() const {	SlotIndex getNextSlot() const {
	Slot s = getSlot();	Slot s = getSlot();

	if (s == SlotIndex::STORE) {	if (s == Slot_Dead) {
	return SlotIndex(entry().getNext(), SlotIndex::LOAD);	return SlotIndex(listEntry()->getNextNode(), Slot_Block);
	}	}

	return SlotIndex(&entry(), s + 1);	return SlotIndex(listEntry(), s + 1);
	}	}

	/// Returns the next index. This is the index corresponding to the this	/// Returns the next index. This is the index corresponding to the this
	/// index's slot, but for the next instruction.	/// index's slot, but for the next instruction.
	SlotIndex getNextIndex() const {	SlotIndex getNextIndex() const {

	return SlotIndex(entry().getNext(), getSlot());	return SlotIndex(listEntry()->getNextNode(), getSlot());
	}	}

	/// Returns the previous slot in the index list. This could be either t he	/// Returns the previous slot in the index list. This could be either t he
	/// previous slot for the instruction pointed to by this index or, if t his	/// previous slot for the instruction pointed to by this index or, if t his

	/// index is a LOAD, the last slot for the previous instruction.	/// index is a Slot_Block, the last slot for the previous instruction.
	/// WARNING: This method is considerably more expensive than the method s	/// WARNING: This method is considerably more expensive than the method s
	/// that return specific slots (getUseIndex(), etc). If you can - pleas e	/// that return specific slots (getUseIndex(), etc). If you can - pleas e
	/// use one of those methods.	/// use one of those methods.
	SlotIndex getPrevSlot() const {	SlotIndex getPrevSlot() const {
	Slot s = getSlot();	Slot s = getSlot();

	if (s == SlotIndex::LOAD) {	if (s == Slot_Block) {
	return SlotIndex(entry().getPrev(), SlotIndex::STORE);	return SlotIndex(listEntry()->getPrevNode(), Slot_Dead);
	}	}

	return SlotIndex(&entry(), s - 1);	return SlotIndex(listEntry(), s - 1);
	}	}

	/// Returns the previous index. This is the index corresponding to this	/// Returns the previous index. This is the index corresponding to this
	/// index's slot, but for the previous instruction.	/// index's slot, but for the previous instruction.
	SlotIndex getPrevIndex() const {	SlotIndex getPrevIndex() const {

	return SlotIndex(entry().getPrev(), getSlot());	return SlotIndex(listEntry()->getPrevNode(), getSlot());
	}	}

	};	};

	/// DenseMapInfo specialization for SlotIndex.	/// DenseMapInfo specialization for SlotIndex.
	template <>	template <>
	struct DenseMapInfo<SlotIndex> {	struct DenseMapInfo<SlotIndex> {
	static inline SlotIndex getEmptyKey() {	static inline SlotIndex getEmptyKey() {
	return SlotIndex::getEmptyKey();	return SlotIndex::getEmptyKey();
	}	}

	skipping to change at line 340	skipping to change at line 342
	return LHS.first < RHS.first;	return LHS.first < RHS.first;
	}	}
	};	};

	/// SlotIndexes pass.	/// SlotIndexes pass.
	///	///
	/// This pass assigns indexes to each instruction.	/// This pass assigns indexes to each instruction.
	class SlotIndexes : public MachineFunctionPass {	class SlotIndexes : public MachineFunctionPass {
	private:	private:


		typedef ilist<IndexListEntry> IndexList;
		IndexList indexList;

	MachineFunction *mf;	MachineFunction *mf;

	IndexListEntry *indexListHead;
	unsigned functionSize;	unsigned functionSize;

	typedef DenseMap<const MachineInstr*, SlotIndex> Mi2IndexMap;	typedef DenseMap<const MachineInstr*, SlotIndex> Mi2IndexMap;
	Mi2IndexMap mi2iMap;	Mi2IndexMap mi2iMap;

	/// MBBRanges - Map MBB number to (start, stop) indexes.	/// MBBRanges - Map MBB number to (start, stop) indexes.
	SmallVector<std::pair<SlotIndex, SlotIndex>, 8> MBBRanges;	SmallVector<std::pair<SlotIndex, SlotIndex>, 8> MBBRanges;

	/// Idx2MBBMap - Sorted list of pairs of index of first instruction	/// Idx2MBBMap - Sorted list of pairs of index of first instruction
	/// and MBB id.	/// and MBB id.

	skipping to change at line 368	skipping to change at line 372
	IndexListEntry *entry =	IndexListEntry *entry =
	static_cast<IndexListEntry*>(	static_cast<IndexListEntry*>(
	ileAllocator.Allocate(sizeof(IndexListEntry),	ileAllocator.Allocate(sizeof(IndexListEntry),
	alignOf<IndexListEntry>()));	alignOf<IndexListEntry>()));

	new (entry) IndexListEntry(mi, index);	new (entry) IndexListEntry(mi, index);

	return entry;	return entry;
	}	}


	void initList() {	/// Renumber locally after inserting curItr.
	assert(indexListHead == 0 && "Zero entry non-null at initialisation."	void renumberIndexes(IndexList::iterator curItr);
	);
	indexListHead = createEntry(0, ~0U);
	indexListHead->setNext(0);
	indexListHead->setPrev(indexListHead);
	}

	void clearList() {
	indexListHead = 0;
	ileAllocator.Reset();
	}

	IndexListEntry* getTail() {
	assert(indexListHead != 0 && "Call to getTail on uninitialized list."
	);
	return indexListHead->getPrev();
	}

	const IndexListEntry* getTail() const {
	assert(indexListHead != 0 && "Call to getTail on uninitialized list."
	);
	return indexListHead->getPrev();
	}

	// Returns true if the index list is empty.
	bool empty() const { return (indexListHead == getTail()); }

	IndexListEntry* front() {
	assert(!empty() && "front() called on empty index list.");
	return indexListHead;
	}

	const IndexListEntry* front() const {
	assert(!empty() && "front() called on empty index list.");
	return indexListHead;
	}

	IndexListEntry* back() {
	assert(!empty() && "back() called on empty index list.");
	return getTail()->getPrev();
	}

	const IndexListEntry* back() const {
	assert(!empty() && "back() called on empty index list.");
	return getTail()->getPrev();
	}

	/// Insert a new entry before itr.
	void insert(IndexListEntry itr, IndexListEntry val) {
	assert(itr != 0 && "itr should not be null.");
	IndexListEntry *prev = itr->getPrev();
	val->setNext(itr);
	val->setPrev(prev);

	if (itr != indexListHead) {
	prev->setNext(val);
	}
	else {
	indexListHead = val;
	}
	itr->setPrev(val);
	}

	/// Push a new entry on to the end of the list.
	void push_back(IndexListEntry *val) {
	insert(getTail(), val);
	}

	/// Renumber locally after inserting newEntry.
	void renumberIndexes(IndexListEntry *newEntry);

	public:	public:
	static char ID;	static char ID;


	SlotIndexes() : MachineFunctionPass(ID), indexListHead(0) {	SlotIndexes() : MachineFunctionPass(ID) {
	initializeSlotIndexesPass(*PassRegistry::getPassRegistry());	initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
	}	}

	virtual void getAnalysisUsage(AnalysisUsage &au) const;	virtual void getAnalysisUsage(AnalysisUsage &au) const;
	virtual void releaseMemory();	virtual void releaseMemory();

	virtual bool runOnMachineFunction(MachineFunction &fn);	virtual bool runOnMachineFunction(MachineFunction &fn);

	/// Dump the indexes.	/// Dump the indexes.
	void dump() const;	void dump() const;

	/// Renumber the index list, providing space for new instructions.	/// Renumber the index list, providing space for new instructions.
	void renumberIndexes();	void renumberIndexes();

	/// Returns the zero index for this analysis.	/// Returns the zero index for this analysis.
	SlotIndex getZeroIndex() {	SlotIndex getZeroIndex() {

	assert(front()->getIndex() == 0 && "First index is not 0?");	assert(indexList.front().getIndex() == 0 && "First index is not 0?");
	return SlotIndex(front(), 0);	return SlotIndex(&indexList.front(), 0);
	}	}

	/// Returns the base index of the last slot in this analysis.	/// Returns the base index of the last slot in this analysis.
	SlotIndex getLastIndex() {	SlotIndex getLastIndex() {

	return SlotIndex(back(), 0);	return SlotIndex(&indexList.back(), 0);
	}

	/// Returns the invalid index marker for this analysis.
	SlotIndex getInvalidIndex() {
	return getZeroIndex();
	}	}

	/// Returns the distance between the highest and lowest indexes allocat ed	/// Returns the distance between the highest and lowest indexes allocat ed
	/// so far.	/// so far.
	unsigned getIndexesLength() const {	unsigned getIndexesLength() const {

	assert(front()->getIndex() == 0 &&	assert(indexList.front().getIndex() == 0 &&
	"Initial index isn't zero?");	"Initial index isn't zero?");

		return indexList.back().getIndex();
	return back()->getIndex();
	}	}

	/// Returns the number of instructions in the function.	/// Returns the number of instructions in the function.
	unsigned getFunctionSize() const {	unsigned getFunctionSize() const {
	return functionSize;	return functionSize;
	}	}

	/// Returns true if the given machine instr is mapped to an index,	/// Returns true if the given machine instr is mapped to an index,
	/// otherwise returns false.	/// otherwise returns false.
	bool hasIndex(const MachineInstr *instr) const {	bool hasIndex(const MachineInstr *instr) const {

	return (mi2iMap.find(instr) != mi2iMap.end());	return mi2iMap.count(instr);
	}	}

	/// Returns the base index for the given instruction.	/// Returns the base index for the given instruction.

	SlotIndex getInstructionIndex(const MachineInstr *instr) const {	SlotIndex getInstructionIndex(const MachineInstr *MI) const {
	Mi2IndexMap::const_iterator itr = mi2iMap.find(instr);	// Instructions inside a bundle have the same number as the bundle it
		self.
		Mi2IndexMap::const_iterator itr = mi2iMap.find(getBundleStart(MI));
	assert(itr != mi2iMap.end() && "Instruction not found in maps.");	assert(itr != mi2iMap.end() && "Instruction not found in maps.");
	return itr->second;	return itr->second;
	}	}

	/// Returns the instruction for the given index, or null if the given	/// Returns the instruction for the given index, or null if the given
	/// index has no instruction associated with it.	/// index has no instruction associated with it.
	MachineInstr* getInstructionFromIndex(SlotIndex index) const {	MachineInstr* getInstructionFromIndex(SlotIndex index) const {

	return index.isValid() ? index.entry().getInstr() : 0;	return index.isValid() ? index.listEntry()->getInstr() : 0;
	}	}

	/// Returns the next non-null index.	/// Returns the next non-null index.
	SlotIndex getNextNonNullIndex(SlotIndex index) {	SlotIndex getNextNonNullIndex(SlotIndex index) {

	SlotIndex nextNonNull = index.getNextIndex();	IndexList::iterator itr(index.listEntry());
		++itr;
	while (&nextNonNull.entry() != getTail() &&	while (itr != indexList.end() && itr->getInstr() == 0) { ++itr; }
	getInstructionFromIndex(nextNonNull) == 0) {	return SlotIndex(itr, index.getSlot());
	nextNonNull = nextNonNull.getNextIndex();
	}

	return nextNonNull;
	}	}

	/// getIndexBefore - Returns the index of the last indexed instruction	/// getIndexBefore - Returns the index of the last indexed instruction
	/// before MI, or the the start index of its basic block.	/// before MI, or the the start index of its basic block.
	/// MI is not required to have an index.	/// MI is not required to have an index.
	SlotIndex getIndexBefore(const MachineInstr *MI) const {	SlotIndex getIndexBefore(const MachineInstr *MI) const {
	const MachineBasicBlock *MBB = MI->getParent();	const MachineBasicBlock *MBB = MI->getParent();
	assert(MBB && "MI must be inserted inna basic block");	assert(MBB && "MI must be inserted inna basic block");
	MachineBasicBlock::const_iterator I = MI, B = MBB->begin();	MachineBasicBlock::const_iterator I = MI, B = MBB->begin();
	for (;;) {	for (;;) {

	skipping to change at line 647	skipping to change at line 576

	return 0;	return 0;
	}	}

	/// Insert the given machine instruction into the mapping. Returns the	/// Insert the given machine instruction into the mapping. Returns the
	/// assigned index.	/// assigned index.
	/// If Late is set and there are null indexes between mi's neighboring	/// If Late is set and there are null indexes between mi's neighboring
	/// instructions, create the new index after the null indexes instead o f	/// instructions, create the new index after the null indexes instead o f
	/// before them.	/// before them.
	SlotIndex insertMachineInstrInMaps(MachineInstr *mi, bool Late = false) {	SlotIndex insertMachineInstrInMaps(MachineInstr *mi, bool Late = false) {

		assert(!mi->isInsideBundle() &&
		"Instructions inside bundles should use bundle start's slot.")
		;
	assert(mi2iMap.find(mi) == mi2iMap.end() && "Instr already indexed.") ;	assert(mi2iMap.find(mi) == mi2iMap.end() && "Instr already indexed.") ;
	// Numbering DBG_VALUE instructions could cause code generation to be	// Numbering DBG_VALUE instructions could cause code generation to be
	// affected by debug information.	// affected by debug information.
	assert(!mi->isDebugValue() && "Cannot number DBG_VALUE instructions." );	assert(!mi->isDebugValue() && "Cannot number DBG_VALUE instructions." );

	assert(mi->getParent() != 0 && "Instr must be added to function.");	assert(mi->getParent() != 0 && "Instr must be added to function.");

	// Get the entries where mi should be inserted.	// Get the entries where mi should be inserted.

	IndexListEntry prevEntry, nextEntry;	IndexList::iterator prevItr, nextItr;
	if (Late) {	if (Late) {
	// Insert mi's index immediately before the following instruction.	// Insert mi's index immediately before the following instruction.

	nextEntry = &getIndexAfter(mi).entry();	nextItr = getIndexAfter(mi).listEntry();
	prevEntry = nextEntry->getPrev();	prevItr = prior(nextItr);
	} else {	} else {
	// Insert mi's index immediately after the preceeding instruction.	// Insert mi's index immediately after the preceeding instruction.

	prevEntry = &getIndexBefore(mi).entry();	prevItr = getIndexBefore(mi).listEntry();
	nextEntry = prevEntry->getNext();	nextItr = llvm::next(prevItr);
	}	}

	// Get a number for the new instr, or 0 if there's no room currently.	// Get a number for the new instr, or 0 if there's no room currently.
	// In the latter case we'll force a renumber later.	// In the latter case we'll force a renumber later.

	unsigned dist = ((nextEntry->getIndex() - prevEntry->getIndex())/2) &	unsigned dist = ((nextItr->getIndex() - prevItr->getIndex())/2) & ~3u
	~3u;	;
	unsigned newNumber = prevEntry->getIndex() + dist;	unsigned newNumber = prevItr->getIndex() + dist;

	// Insert a new list entry for mi.	// Insert a new list entry for mi.

	IndexListEntry *newEntry = createEntry(mi, newNumber);	IndexList::iterator newItr =
	insert(nextEntry, newEntry);	indexList.insert(nextItr, createEntry(mi, newNumber));

	// Renumber locally if we need to.	// Renumber locally if we need to.
	if (dist == 0)	if (dist == 0)

	renumberIndexes(newEntry);	renumberIndexes(newItr);


	SlotIndex newIndex(newEntry, SlotIndex::LOAD);	SlotIndex newIndex(&*newItr, SlotIndex::Slot_Block);
	mi2iMap.insert(std::make_pair(mi, newIndex));	mi2iMap.insert(std::make_pair(mi, newIndex));
	return newIndex;	return newIndex;
	}	}

	/// Remove the given machine instruction from the mapping.	/// Remove the given machine instruction from the mapping.
	void removeMachineInstrFromMaps(MachineInstr *mi) {	void removeMachineInstrFromMaps(MachineInstr *mi) {
	// remove index -> MachineInstr and	// remove index -> MachineInstr and
	// MachineInstr -> index mappings	// MachineInstr -> index mappings
	Mi2IndexMap::iterator mi2iItr = mi2iMap.find(mi);	Mi2IndexMap::iterator mi2iItr = mi2iMap.find(mi);
	if (mi2iItr != mi2iMap.end()) {	if (mi2iItr != mi2iMap.end()) {

	IndexListEntry *miEntry(&mi2iItr->second.entry());	IndexListEntry *miEntry(mi2iItr->second.listEntry());
	assert(miEntry->getInstr() == mi && "Instruction indexes broken.");	assert(miEntry->getInstr() == mi && "Instruction indexes broken.");
	// FIXME: Eventually we want to actually delete these indexes.	// FIXME: Eventually we want to actually delete these indexes.
	miEntry->setInstr(0);	miEntry->setInstr(0);
	mi2iMap.erase(mi2iItr);	mi2iMap.erase(mi2iItr);
	}	}
	}	}

	/// ReplaceMachineInstrInMaps - Replacing a machine instr with a new on e in	/// ReplaceMachineInstrInMaps - Replacing a machine instr with a new on e in
	/// maps used by register allocator.	/// maps used by register allocator.
	void replaceMachineInstrInMaps(MachineInstr mi, MachineInstr newMI) {	void replaceMachineInstrInMaps(MachineInstr mi, MachineInstr newMI) {
	Mi2IndexMap::iterator mi2iItr = mi2iMap.find(mi);	Mi2IndexMap::iterator mi2iItr = mi2iMap.find(mi);
	if (mi2iItr == mi2iMap.end())	if (mi2iItr == mi2iMap.end())
	return;	return;
	SlotIndex replaceBaseIndex = mi2iItr->second;	SlotIndex replaceBaseIndex = mi2iItr->second;

	IndexListEntry *miEntry(&replaceBaseIndex.entry());	IndexListEntry *miEntry(replaceBaseIndex.listEntry());
	assert(miEntry->getInstr() == mi &&	assert(miEntry->getInstr() == mi &&
	"Mismatched instruction in index tables.");	"Mismatched instruction in index tables.");
	miEntry->setInstr(newMI);	miEntry->setInstr(newMI);
	mi2iMap.erase(mi2iItr);	mi2iMap.erase(mi2iItr);
	mi2iMap.insert(std::make_pair(newMI, replaceBaseIndex));	mi2iMap.insert(std::make_pair(newMI, replaceBaseIndex));
	}	}

	/// Add the given MachineBasicBlock into the maps.	/// Add the given MachineBasicBlock into the maps.
	void insertMBBInMaps(MachineBasicBlock *mbb) {	void insertMBBInMaps(MachineBasicBlock *mbb) {
	MachineFunction::iterator nextMBB =	MachineFunction::iterator nextMBB =
	llvm::next(MachineFunction::iterator(mbb));	llvm::next(MachineFunction::iterator(mbb));
	IndexListEntry *startEntry = createEntry(0, 0);	IndexListEntry *startEntry = createEntry(0, 0);
	IndexListEntry *stopEntry = createEntry(0, 0);	IndexListEntry *stopEntry = createEntry(0, 0);
	IndexListEntry *nextEntry = 0;	IndexListEntry *nextEntry = 0;

	if (nextMBB == mbb->getParent()->end()) {	if (nextMBB == mbb->getParent()->end()) {

	nextEntry = getTail();	nextEntry = indexList.end();
	} else {	} else {

	nextEntry = &getMBBStartIdx(nextMBB).entry();	nextEntry = getMBBStartIdx(nextMBB).listEntry();
	}	}


	insert(nextEntry, startEntry);	indexList.insert(nextEntry, startEntry);
	insert(nextEntry, stopEntry);	indexList.insert(nextEntry, stopEntry);


	SlotIndex startIdx(startEntry, SlotIndex::LOAD);	SlotIndex startIdx(startEntry, SlotIndex::Slot_Block);
	SlotIndex endIdx(nextEntry, SlotIndex::LOAD);	SlotIndex endIdx(nextEntry, SlotIndex::Slot_Block);

	assert(unsigned(mbb->getNumber()) == MBBRanges.size() &&	assert(unsigned(mbb->getNumber()) == MBBRanges.size() &&
	"Blocks must be added in order");	"Blocks must be added in order");
	MBBRanges.push_back(std::make_pair(startIdx, endIdx));	MBBRanges.push_back(std::make_pair(startIdx, endIdx));

	idx2MBBMap.push_back(IdxMBBPair(startIdx, mbb));	idx2MBBMap.push_back(IdxMBBPair(startIdx, mbb));

	renumberIndexes();	renumberIndexes();
	std::sort(idx2MBBMap.begin(), idx2MBBMap.end(), Idx2MBBCompare());	std::sort(idx2MBBMap.begin(), idx2MBBMap.end(), Idx2MBBCompare());
	}	}

	skipping to change at line 761	skipping to change at line 692
	static inline bool stopLess(const SlotIndex &b, const SlotIndex &x) {	static inline bool stopLess(const SlotIndex &b, const SlotIndex &x) {
	return b <= x;	return b <= x;
	}	}
	static inline bool adjacent(const SlotIndex &a, const SlotIndex &b) {	static inline bool adjacent(const SlotIndex &a, const SlotIndex &b) {
	return a == b;	return a == b;
	}	}
	};	};

	}	}


	#endif // LLVM_CODEGEN_LIVEINDEX_H	#endif // LLVM_CODEGEN_SLOTINDEXES_H

End of changes. 59 change blocks.
	198 lines changed or deleted	137 lines changed or added

	SmallBitVector.h	SmallBitVector.h

	skipping to change at line 178	skipping to change at line 178
	}	}

	/// count - Returns the number of bits which are set.	/// count - Returns the number of bits which are set.
	unsigned count() const {	unsigned count() const {
	if (isSmall()) {	if (isSmall()) {
	uintptr_t Bits = getSmallBits();	uintptr_t Bits = getSmallBits();
	if (sizeof(uintptr_t) * CHAR_BIT == 32)	if (sizeof(uintptr_t) * CHAR_BIT == 32)
	return CountPopulation_32(Bits);	return CountPopulation_32(Bits);
	if (sizeof(uintptr_t) * CHAR_BIT == 64)	if (sizeof(uintptr_t) * CHAR_BIT == 64)
	return CountPopulation_64(Bits);	return CountPopulation_64(Bits);

	assert(0 && "Unsupported!");	llvm_unreachable("Unsupported!");
	}	}
	return getPointer()->count();	return getPointer()->count();
	}	}

	/// any - Returns true if any bit is set.	/// any - Returns true if any bit is set.
	bool any() const {	bool any() const {
	if (isSmall())	if (isSmall())
	return getSmallBits() != 0;	return getSmallBits() != 0;
	return getPointer()->any();	return getPointer()->any();
	}	}

	skipping to change at line 215	skipping to change at line 215
	/// of the bits are set.	/// of the bits are set.
	int find_first() const {	int find_first() const {
	if (isSmall()) {	if (isSmall()) {
	uintptr_t Bits = getSmallBits();	uintptr_t Bits = getSmallBits();
	if (Bits == 0)	if (Bits == 0)
	return -1;	return -1;
	if (sizeof(uintptr_t) * CHAR_BIT == 32)	if (sizeof(uintptr_t) * CHAR_BIT == 32)
	return CountTrailingZeros_32(Bits);	return CountTrailingZeros_32(Bits);
	if (sizeof(uintptr_t) * CHAR_BIT == 64)	if (sizeof(uintptr_t) * CHAR_BIT == 64)
	return CountTrailingZeros_64(Bits);	return CountTrailingZeros_64(Bits);

	assert(0 && "Unsupported!");	llvm_unreachable("Unsupported!");
	}	}
	return getPointer()->find_first();	return getPointer()->find_first();
	}	}

	/// find_next - Returns the index of the next set bit following the	/// find_next - Returns the index of the next set bit following the
	/// "Prev" bit. Returns -1 if the next set bit is not found.	/// "Prev" bit. Returns -1 if the next set bit is not found.
	int find_next(unsigned Prev) const {	int find_next(unsigned Prev) const {
	if (isSmall()) {	if (isSmall()) {
	uintptr_t Bits = getSmallBits();	uintptr_t Bits = getSmallBits();
	// Mask off previous bits.	// Mask off previous bits.
	Bits &= ~uintptr_t(0) << (Prev + 1);	Bits &= ~uintptr_t(0) << (Prev + 1);
	if (Bits == 0 \|\| Prev + 1 >= getSmallSize())	if (Bits == 0 \|\| Prev + 1 >= getSmallSize())
	return -1;	return -1;
	if (sizeof(uintptr_t) * CHAR_BIT == 32)	if (sizeof(uintptr_t) * CHAR_BIT == 32)
	return CountTrailingZeros_32(Bits);	return CountTrailingZeros_32(Bits);
	if (sizeof(uintptr_t) * CHAR_BIT == 64)	if (sizeof(uintptr_t) * CHAR_BIT == 64)
	return CountTrailingZeros_64(Bits);	return CountTrailingZeros_64(Bits);

	assert(0 && "Unsupported!");	llvm_unreachable("Unsupported!");
	}	}
	return getPointer()->find_next(Prev);	return getPointer()->find_next(Prev);
	}	}

	/// clear - Clear all bits.	/// clear - Clear all bits.
	void clear() {	void clear() {
	if (!isSmall())	if (!isSmall())
	delete getPointer();	delete getPointer();
	switchToSmall(0, 0);	switchToSmall(0, 0);
	}	}

End of changes. 3 change blocks.
	3 lines changed or deleted	3 lines changed or added

	SmallPtrSet.h	SmallPtrSet.h

	skipping to change at line 129	skipping to change at line 129
	return false;	return false;
	}	}

	// Big set case.	// Big set case.
	return *FindBucketFor(Ptr) == Ptr;	return *FindBucketFor(Ptr) == Ptr;
	}	}

	private:	private:
	bool isSmall() const { return CurArray == SmallArray; }	bool isSmall() const { return CurArray == SmallArray; }


	unsigned Hash(const void *Ptr) const {
	return static_cast<unsigned>(((uintptr_t)Ptr >> 4) & (CurArraySize-1));
	}
	const void * const FindBucketFor(const void Ptr) const;	const void * const FindBucketFor(const void Ptr) const;
	void shrink_and_clear();	void shrink_and_clear();

	/// Grow - Allocate a larger backing store for the buckets and move it ov er.	/// Grow - Allocate a larger backing store for the buckets and move it ov er.
	void Grow(unsigned NewSize);	void Grow(unsigned NewSize);

	void operator=(const SmallPtrSetImpl &RHS); // DO NOT IMPLEMENT.	void operator=(const SmallPtrSetImpl &RHS); // DO NOT IMPLEMENT.
	protected:	protected:

		/// swap - Swaps the elements of two sets.
		/// Note: This method assumes that both sets have the same small size.
		void swap(SmallPtrSetImpl &RHS);

	void CopyFrom(const SmallPtrSetImpl &RHS);	void CopyFrom(const SmallPtrSetImpl &RHS);
	};	};

	/// SmallPtrSetIteratorImpl - This is the common base class shared between all	/// SmallPtrSetIteratorImpl - This is the common base class shared between all
	/// instances of SmallPtrSetIterator.	/// instances of SmallPtrSetIterator.
	class SmallPtrSetIteratorImpl {	class SmallPtrSetIteratorImpl {
	protected:	protected:
	const void const Bucket;	const void const Bucket;
	public:	public:
	explicit SmallPtrSetIteratorImpl(const void const BP) : Bucket(BP) {	explicit SmallPtrSetIteratorImpl(const void const BP) : Bucket(BP) {

	skipping to change at line 289	skipping to change at line 290
	}	}

	// Allow assignment from any smallptrset with the same element type even if it	// Allow assignment from any smallptrset with the same element type even if it
	// doesn't have the same smallsize.	// doesn't have the same smallsize.
	const SmallPtrSet<PtrType, SmallSize>&	const SmallPtrSet<PtrType, SmallSize>&
	operator=(const SmallPtrSet<PtrType, SmallSize> &RHS) {	operator=(const SmallPtrSet<PtrType, SmallSize> &RHS) {
	CopyFrom(RHS);	CopyFrom(RHS);
	return *this;	return *this;
	}	}


		/// swap - Swaps the elements of two sets.
		void swap(SmallPtrSet<PtrType, SmallSize> &RHS) {
		SmallPtrSetImpl::swap(RHS);
		}
	};	};

	}	}


		namespace std {
		/// Implement std::swap in terms of SmallPtrSet swap.
		template<class T, unsigned N>
		inline void swap(llvm::SmallPtrSet<T, N> &LHS, llvm::SmallPtrSet<T, N> &R
		HS) {
		LHS.swap(RHS);
		}
		}

	#endif	#endif

End of changes. 4 change blocks.
	3 lines changed or deleted	17 lines changed or added

	SmallSet.h	SmallSet.h

	skipping to change at line 30	skipping to change at line 30

	namespace llvm {	namespace llvm {

	/// SmallSet - This maintains a set of unique values, optimizing for the ca se	/// SmallSet - This maintains a set of unique values, optimizing for the ca se
	/// when the set is small (less than N). In this case, the set can be	/// when the set is small (less than N). In this case, the set can be
	/// maintained with no mallocs. If the set gets large, we expand to using an	/// maintained with no mallocs. If the set gets large, we expand to using an
	/// std::set to maintain reasonable lookup times.	/// std::set to maintain reasonable lookup times.
	///	///
	/// Note that this set does not provide a way to iterate over members in th e	/// Note that this set does not provide a way to iterate over members in th e
	/// set.	/// set.

	template <typename T, unsigned N>	template <typename T, unsigned N, typename C = std::less<T> >
	class SmallSet {	class SmallSet {
	/// Use a SmallVector to hold the elements here (even though it will neve r	/// Use a SmallVector to hold the elements here (even though it will neve r
	/// reach its 'large' stage) to avoid calling the default ctors of elemen ts	/// reach its 'large' stage) to avoid calling the default ctors of elemen ts
	/// we will never use.	/// we will never use.
	SmallVector<T, N> Vector;	SmallVector<T, N> Vector;

	std::set<T> Set;	std::set<T, C> Set;
	typedef typename SmallVector<T, N>::const_iterator VIterator;	typedef typename SmallVector<T, N>::const_iterator VIterator;
	typedef typename SmallVector<T, N>::iterator mutable_iterator;	typedef typename SmallVector<T, N>::iterator mutable_iterator;
	public:	public:
	SmallSet() {}	SmallSet() {}

	bool empty() const { return Vector.empty() && Set.empty(); }	bool empty() const { return Vector.empty() && Set.empty(); }
	unsigned size() const {	unsigned size() const {
	return isSmall() ? Vector.size() : Set.size();	return isSmall() ? Vector.size() : Set.size();
	}	}


End of changes. 2 change blocks.
	2 lines changed or deleted	2 lines changed or added

	SmallString.h	SmallString.h

	skipping to change at line 27	skipping to change at line 27
	#include "llvm/ADT/SmallVector.h"	#include "llvm/ADT/SmallVector.h"
	#include "llvm/ADT/StringRef.h"	#include "llvm/ADT/StringRef.h"

	namespace llvm {	namespace llvm {

	/// SmallString - A SmallString is just a SmallVector with methods and acce ssors	/// SmallString - A SmallString is just a SmallVector with methods and acce ssors
	/// that make it work better as a string (e.g. operator+ etc).	/// that make it work better as a string (e.g. operator+ etc).
	template<unsigned InternalLen>	template<unsigned InternalLen>
	class SmallString : public SmallVector<char, InternalLen> {	class SmallString : public SmallVector<char, InternalLen> {
	public:	public:

	// Default ctor - Initialize to empty.	/// Default ctor - Initialize to empty.
	SmallString() {}	SmallString() {}


	// Initialize from a StringRef.	/// Initialize from a StringRef.
	SmallString(StringRef S) : SmallVector<char, InternalLen>(S.begin(), S.en d()) {}	SmallString(StringRef S) : SmallVector<char, InternalLen>(S.begin(), S.en d()) {}


	// Initialize with a range.	/// Initialize with a range.
	template<typename ItTy>	template<typename ItTy>
	SmallString(ItTy S, ItTy E) : SmallVector<char, InternalLen>(S, E) {}	SmallString(ItTy S, ItTy E) : SmallVector<char, InternalLen>(S, E) {}


	// Copy ctor.	/// Copy ctor.
	SmallString(const SmallString &RHS) : SmallVector<char, InternalLen>(RHS) {}	SmallString(const SmallString &RHS) : SmallVector<char, InternalLen>(RHS) {}


		// Note that in order to add new overloads for append & assign, we have t
		o
		// duplicate the inherited versions so as not to inadvertently hide them.

		/// @}
		/// @name String Assignment
		/// @{

		/// Assign from a repeated element
		void assign(unsigned NumElts, char Elt) {
		this->SmallVectorImpl<char>::assign(NumElts, Elt);
		}

		/// Assign from an iterator pair
		template<typename in_iter>
		void assign(in_iter S, in_iter E) {
		this->clear();
		SmallVectorImpl<char>::append(S, E);
		}

		/// Assign from a StringRef
		void assign(StringRef RHS) {
		this->clear();
		SmallVectorImpl<char>::append(RHS.begin(), RHS.end());
		}

		/// Assign from a SmallVector
		void assign(const SmallVectorImpl<char> &RHS) {
		this->clear();
		SmallVectorImpl<char>::append(RHS.begin(), RHS.end());
		}

		/// @}
		/// @name String Concatenation
		/// @{

		/// Append from an iterator pair
		template<typename in_iter>
		void append(in_iter S, in_iter E) {
		SmallVectorImpl<char>::append(S, E);
		}

		/// Append from a StringRef
		void append(StringRef RHS) {
		SmallVectorImpl<char>::append(RHS.begin(), RHS.end());
		}

		/// Append from a SmallVector
		void append(const SmallVectorImpl<char> &RHS) {
		SmallVectorImpl<char>::append(RHS.begin(), RHS.end());
		}

		/// @}
		/// @name String Comparison
		/// @{

		/// equals - Check for string equality, this is more efficient than
		/// compare() when the relative ordering of inequal strings isn't needed.
		bool equals(StringRef RHS) const {
		return str().equals(RHS);
		}

		/// equals_lower - Check for string equality, ignoring case.
		bool equals_lower(StringRef RHS) const {
		return str().equals_lower(RHS);
		}

		/// compare - Compare two strings; the result is -1, 0, or 1 if this stri
		ng
		/// is lexicographically less than, equal to, or greater than the \arg RH
		S.
		int compare(StringRef RHS) const {
		return str().compare(RHS);
		}

		/// compare_lower - Compare two strings, ignoring case.
		int compare_lower(StringRef RHS) const {
		return str().compare_lower(RHS);
		}

		/// compare_numeric - Compare two strings, treating sequences of digits a
		s
		/// numbers.
		int compare_numeric(StringRef RHS) const {
		return str().compare_numeric(RHS);
		}

		/// @}
		/// @name String Predicates
		/// @{

		/// startswith - Check if this string starts with the given \arg Prefix.
		bool startswith(StringRef Prefix) const {
		return str().startswith(Prefix);
		}

		/// endswith - Check if this string ends with the given \arg Suffix.
		bool endswith(StringRef Suffix) const {
		return str().endswith(Suffix);
		}

		/// @}
		/// @name String Searching
		/// @{

		/// find - Search for the first character \arg C in the string.
		///
		/// \return - The index of the first occurrence of \arg C, or npos if not
		/// found.
		size_t find(char C, size_t From = 0) const {
		return str().find(C, From);
		}

		/// find - Search for the first string \arg Str in the string.
		///
		/// \return - The index of the first occurrence of \arg Str, or npos if n
		ot
		/// found.
		size_t find(StringRef Str, size_t From = 0) const {
		return str().find(Str, From);
		}

		/// rfind - Search for the last character \arg C in the string.
		///
		/// \return - The index of the last occurrence of \arg C, or npos if not
		/// found.
		size_t rfind(char C, size_t From = StringRef::npos) const {
		return str().rfind(C, From);
		}

		/// rfind - Search for the last string \arg Str in the string.
		///
		/// \return - The index of the last occurrence of \arg Str, or npos if no
		t
		/// found.
		size_t rfind(StringRef Str) const {
		return str().rfind(Str);
		}

		/// find_first_of - Find the first character in the string that is \arg C
		,
		/// or npos if not found. Same as find.
		size_t find_first_of(char C, size_t From = 0) const {
		return str().find_first_of(C, From);
		}

		/// find_first_of - Find the first character in the string that is in \ar
		g
		/// Chars, or npos if not found.
		///
		/// Note: O(size() + Chars.size())
		size_t find_first_of(StringRef Chars, size_t From = 0) const {
		return str().find_first_of(Chars, From);
		}

		/// find_first_not_of - Find the first character in the string that is no
		t
		/// \arg C or npos if not found.
		size_t find_first_not_of(char C, size_t From = 0) const {
		return str().find_first_not_of(C, From);
		}

		/// find_first_not_of - Find the first character in the string that is no
		t
		/// in the string \arg Chars, or npos if not found.
		///
		/// Note: O(size() + Chars.size())
		size_t find_first_not_of(StringRef Chars, size_t From = 0) const {
		return str().find_first_not_of(Chars, From);
		}

		/// find_last_of - Find the last character in the string that is \arg C,
		or
		/// npos if not found.
		size_t find_last_of(char C, size_t From = StringRef::npos) const {
		return str().find_last_of(C, From);
		}

		/// find_last_of - Find the last character in the string that is in \arg
		C,
		/// or npos if not found.
		///
		/// Note: O(size() + Chars.size())
		size_t find_last_of(
		StringRef Chars, size_t From = StringRef::npos) const {
		return str().find_last_of(Chars, From);
		}

		/// @}
		/// @name Helpful Algorithms
		/// @{

		/// count - Return the number of occurrences of \arg C in the string.
		size_t count(char C) const {
		return str().count(C);
		}

		/// count - Return the number of non-overlapped occurrences of \arg Str i
		n
		/// the string.
		size_t count(StringRef Str) const {
		return str().count(Str);
		}

		/// @}
		/// @name Substring Operations
		/// @{

		/// substr - Return a reference to the substring from [Start, Start + N).
		///
		/// \param Start - The index of the starting character in the substring;
		if
		/// the index is npos or greater than the length of the string then the
		/// empty substring will be returned.
		///
		/// \param N - The number of characters to included in the substring. If
		N
		/// exceeds the number of characters remaining in the string, the string
		/// suffix (starting with \arg Start) will be returned.
		StringRef substr(size_t Start, size_t N = StringRef::npos) const {
		return str().substr(Start, N);
		}

		/// slice - Return a reference to the substring from [Start, End).
		///
		/// \param Start - The index of the starting character in the substring;
		if
		/// the index is npos or greater than the length of the string then the
		/// empty substring will be returned.
		///
		/// \param End - The index following the last character to include in the
		/// substring. If this is npos, or less than \arg Start, or exceeds the
		/// number of characters remaining in the string, the string suffix
		/// (starting with \arg Start) will be returned.
		StringRef slice(size_t Start, size_t End) const {
		return str().slice(Start, End);
		}

	// Extra methods.	// Extra methods.


		/// Explicit conversion to StringRef
	StringRef str() const { return StringRef(this->begin(), this->size()); }	StringRef str() const { return StringRef(this->begin(), this->size()); }

	// TODO: Make this const, if it's safe...	// TODO: Make this const, if it's safe...
	const char* c_str() {	const char* c_str() {
	this->push_back(0);	this->push_back(0);
	this->pop_back();	this->pop_back();
	return this->data();	return this->data();
	}	}


	// Implicit conversion to StringRef.	/// Implicit conversion to StringRef.
	operator StringRef() const { return str(); }	operator StringRef() const { return str(); }

	// Extra operators.	// Extra operators.
	const SmallString &operator=(StringRef RHS) {	const SmallString &operator=(StringRef RHS) {
	this->clear();	this->clear();
	return *this += RHS;	return *this += RHS;
	}	}

	SmallString &operator+=(StringRef RHS) {	SmallString &operator+=(StringRef RHS) {
	this->append(RHS.begin(), RHS.end());	this->append(RHS.begin(), RHS.end());

End of changes. 7 change blocks.
	5 lines changed or deleted	245 lines changed or added

	SmallVector.h	SmallVector.h

	skipping to change at line 26	skipping to change at line 26

	#include "llvm/Support/type_traits.h"	#include "llvm/Support/type_traits.h"
	#include <algorithm>	#include <algorithm>
	#include <cassert>	#include <cassert>
	#include <cstddef>	#include <cstddef>
	#include <cstdlib>	#include <cstdlib>
	#include <cstring>	#include <cstring>
	#include <iterator>	#include <iterator>
	#include <memory>	#include <memory>


	#ifdef _MSC_VER
	namespace std {
	#if _MSC_VER <= 1310
	// Work around flawed VC++ implementation of std::uninitialized_copy. De
	fine
	// additional overloads so that elements with pointer types are recognize
	d as
	// scalars and not objects, causing bizarre type conversion errors.
	template<class T1, class T2>
	inline _Scalar_ptr_iterator_tag _Ptr_cat(T1 , T2 ) {
	_Scalar_ptr_iterator_tag _Cat;
	return _Cat;
	}

	template<class T1, class T2>
	inline _Scalar_ptr_iterator_tag _Ptr_cat(T1* const , T2 *) {
	_Scalar_ptr_iterator_tag _Cat;
	return _Cat;
	}
	#else
	// FIXME: It is not clear if the problem is fixed in VS 2005. What is clea
	r
	// is that the above hack won't work if it wasn't fixed.
	#endif
	}
	#endif

	namespace llvm {	namespace llvm {

	/// SmallVectorBase - This is all the non-templated stuff common to all	/// SmallVectorBase - This is all the non-templated stuff common to all
	/// SmallVectors.	/// SmallVectors.
	class SmallVectorBase {	class SmallVectorBase {
	protected:	protected:
	void BeginX, EndX, *CapacityX;	void BeginX, EndX, *CapacityX;

	// Allocate raw space for N elements of type T. If T has a ctor or dtor, we	// Allocate raw space for N elements of type T. If T has a ctor or dtor, we
	// don't want it to be automatically run, so we need to represent the spa ce as	// don't want it to be automatically run, so we need to represent the spa ce as

	skipping to change at line 102	skipping to change at line 78
	size_t capacity_in_bytes() const {	size_t capacity_in_bytes() const {
	return size_t((char)CapacityX - (char)BeginX);	return size_t((char)CapacityX - (char)BeginX);
	}	}

	bool empty() const { return BeginX == EndX; }	bool empty() const { return BeginX == EndX; }
	};	};

	template <typename T>	template <typename T>
	class SmallVectorTemplateCommon : public SmallVectorBase {	class SmallVectorTemplateCommon : public SmallVectorBase {
	protected:	protected:

	void setEnd(T *P) { this->EndX = P; }
	public:
	SmallVectorTemplateCommon(size_t Size) : SmallVectorBase(Size) {}	SmallVectorTemplateCommon(size_t Size) : SmallVectorBase(Size) {}


		void setEnd(T *P) { this->EndX = P; }
		public:
	typedef size_t size_type;	typedef size_t size_type;
	typedef ptrdiff_t difference_type;	typedef ptrdiff_t difference_type;
	typedef T value_type;	typedef T value_type;
	typedef T *iterator;	typedef T *iterator;
	typedef const T *const_iterator;	typedef const T *const_iterator;

	typedef std::reverse_iterator<const_iterator> const_reverse_iterator;	typedef std::reverse_iterator<const_iterator> const_reverse_iterator;
	typedef std::reverse_iterator<iterator> reverse_iterator;	typedef std::reverse_iterator<iterator> reverse_iterator;

	typedef T &reference;	typedef T &reference;

	skipping to change at line 176	skipping to change at line 152
	}	}
	const_reference back() const {	const_reference back() const {
	return end()[-1];	return end()[-1];
	}	}
	};	};

	/// SmallVectorTemplateBase<isPodLike = false> - This is where we put metho d	/// SmallVectorTemplateBase<isPodLike = false> - This is where we put metho d
	/// implementations that are designed to work with non-POD-like T's.	/// implementations that are designed to work with non-POD-like T's.
	template <typename T, bool isPodLike>	template <typename T, bool isPodLike>
	class SmallVectorTemplateBase : public SmallVectorTemplateCommon<T> {	class SmallVectorTemplateBase : public SmallVectorTemplateCommon<T> {

	public:	protected:
	SmallVectorTemplateBase(size_t Size) : SmallVectorTemplateCommon<T>(Size) {}	SmallVectorTemplateBase(size_t Size) : SmallVectorTemplateCommon<T>(Size) {}

	static void destroy_range(T S, T E) {	static void destroy_range(T S, T E) {
	while (S != E) {	while (S != E) {
	--E;	--E;
	E->~T();	E->~T();
	}	}
	}	}

	/// uninitialized_copy - Copy the range [I, E) onto the uninitialized mem ory	/// uninitialized_copy - Copy the range [I, E) onto the uninitialized mem ory
	/// starting with "Dest", constructing elements into it as needed.	/// starting with "Dest", constructing elements into it as needed.
	template<typename It1, typename It2>	template<typename It1, typename It2>
	static void uninitialized_copy(It1 I, It1 E, It2 Dest) {	static void uninitialized_copy(It1 I, It1 E, It2 Dest) {
	std::uninitialized_copy(I, E, Dest);	std::uninitialized_copy(I, E, Dest);
	}	}

	/// grow - double the size of the allocated memory, guaranteeing space fo r at	/// grow - double the size of the allocated memory, guaranteeing space fo r at
	/// least one more element or MinSize if specified.	/// least one more element or MinSize if specified.
	void grow(size_t MinSize = 0);	void grow(size_t MinSize = 0);


		public:
		void push_back(const T &Elt) {
		if (this->EndX < this->CapacityX) {
		Retry:
		new (this->end()) T(Elt);
		this->setEnd(this->end()+1);
		return;
		}
		this->grow();
		goto Retry;
		}

		void pop_back() {
		this->setEnd(this->end()-1);
		this->end()->~T();
		}
	};	};

	// Define this out-of-line to dissuade the C++ compiler from inlining it.	// Define this out-of-line to dissuade the C++ compiler from inlining it.
	template <typename T, bool isPodLike>	template <typename T, bool isPodLike>
	void SmallVectorTemplateBase<T, isPodLike>::grow(size_t MinSize) {	void SmallVectorTemplateBase<T, isPodLike>::grow(size_t MinSize) {
	size_t CurCapacity = this->capacity();	size_t CurCapacity = this->capacity();
	size_t CurSize = this->size();	size_t CurSize = this->size();
	size_t NewCapacity = 2*CurCapacity + 1; // Always grow, even from zero.	size_t NewCapacity = 2*CurCapacity + 1; // Always grow, even from zero.
	if (NewCapacity < MinSize)	if (NewCapacity < MinSize)
	NewCapacity = MinSize;	NewCapacity = MinSize;

	skipping to change at line 227	skipping to change at line 220

	this->setEnd(NewElts+CurSize);	this->setEnd(NewElts+CurSize);
	this->BeginX = NewElts;	this->BeginX = NewElts;
	this->CapacityX = this->begin()+NewCapacity;	this->CapacityX = this->begin()+NewCapacity;
	}	}

	/// SmallVectorTemplateBase<isPodLike = true> - This is where we put method	/// SmallVectorTemplateBase<isPodLike = true> - This is where we put method
	/// implementations that are designed to work with POD-like T's.	/// implementations that are designed to work with POD-like T's.
	template <typename T>	template <typename T>
	class SmallVectorTemplateBase<T, true> : public SmallVectorTemplateCommon<T > {	class SmallVectorTemplateBase<T, true> : public SmallVectorTemplateCommon<T > {

	public:	protected:
	SmallVectorTemplateBase(size_t Size) : SmallVectorTemplateCommon<T>(Size) {}	SmallVectorTemplateBase(size_t Size) : SmallVectorTemplateCommon<T>(Size) {}

	// No need to do a destroy loop for POD's.	// No need to do a destroy loop for POD's.
	static void destroy_range(T , T ) {}	static void destroy_range(T , T ) {}

	/// uninitialized_copy - Copy the range [I, E) onto the uninitialized mem ory	/// uninitialized_copy - Copy the range [I, E) onto the uninitialized mem ory
	/// starting with "Dest", constructing elements into it as needed.	/// starting with "Dest", constructing elements into it as needed.
	template<typename It1, typename It2>	template<typename It1, typename It2>
	static void uninitialized_copy(It1 I, It1 E, It2 Dest) {	static void uninitialized_copy(It1 I, It1 E, It2 Dest) {
	// Arbitrary iterator types; just use the basic implementation.	// Arbitrary iterator types; just use the basic implementation.

	skipping to change at line 256	skipping to change at line 249
	// iterators): std::uninitialized_copy optimizes to memmove, but we can	// iterators): std::uninitialized_copy optimizes to memmove, but we can
	// use memcpy here.	// use memcpy here.
	memcpy(Dest, I, (E-I)*sizeof(T));	memcpy(Dest, I, (E-I)*sizeof(T));
	}	}

	/// grow - double the size of the allocated memory, guaranteeing space fo r at	/// grow - double the size of the allocated memory, guaranteeing space fo r at
	/// least one more element or MinSize if specified.	/// least one more element or MinSize if specified.
	void grow(size_t MinSize = 0) {	void grow(size_t MinSize = 0) {
	this->grow_pod(MinSize*sizeof(T), sizeof(T));	this->grow_pod(MinSize*sizeof(T), sizeof(T));
	}	}

		public:
		void push_back(const T &Elt) {
		if (this->EndX < this->CapacityX) {
		Retry:
		*this->end() = Elt;
		this->setEnd(this->end()+1);
		return;
		}
		this->grow();
		goto Retry;
		}

		void pop_back() {
		this->setEnd(this->end()-1);
		}
	};	};

	/// SmallVectorImpl - This class consists of common code factored out of th e	/// SmallVectorImpl - This class consists of common code factored out of th e
	/// SmallVector class to reduce code duplication based on the SmallVector ' N'	/// SmallVector class to reduce code duplication based on the SmallVector ' N'
	/// template parameter.	/// template parameter.
	template <typename T>	template <typename T>
	class SmallVectorImpl : public SmallVectorTemplateBase<T, isPodLike<T>::val ue> {	class SmallVectorImpl : public SmallVectorTemplateBase<T, isPodLike<T>::val ue> {
	typedef SmallVectorTemplateBase<T, isPodLike<T>::value > SuperClass;	typedef SmallVectorTemplateBase<T, isPodLike<T>::value > SuperClass;

	SmallVectorImpl(const SmallVectorImpl&); // DISABLED.	SmallVectorImpl(const SmallVectorImpl&); // DISABLED.
	public:	public:
	typedef typename SuperClass::iterator iterator;	typedef typename SuperClass::iterator iterator;
	typedef typename SuperClass::size_type size_type;	typedef typename SuperClass::size_type size_type;


		protected:
	// Default ctor - Initialize to empty.	// Default ctor - Initialize to empty.
	explicit SmallVectorImpl(unsigned N)	explicit SmallVectorImpl(unsigned N)
	: SmallVectorTemplateBase<T, isPodLike<T>::value>(N*sizeof(T)) {	: SmallVectorTemplateBase<T, isPodLike<T>::value>(N*sizeof(T)) {
	}	}


		public:
	~SmallVectorImpl() {	~SmallVectorImpl() {
	// Destroy the constructed elements in the vector.	// Destroy the constructed elements in the vector.
	this->destroy_range(this->begin(), this->end());	this->destroy_range(this->begin(), this->end());

	// If this wasn't grown from the inline copy, deallocate the old space.	// If this wasn't grown from the inline copy, deallocate the old space.
	if (!this->isSmall())	if (!this->isSmall())
	free(this->begin());	free(this->begin());
	}	}

	void clear() {	void clear() {

	skipping to change at line 296	skipping to change at line 306
	this->EndX = this->BeginX;	this->EndX = this->BeginX;
	}	}

	void resize(unsigned N) {	void resize(unsigned N) {
	if (N < this->size()) {	if (N < this->size()) {
	this->destroy_range(this->begin()+N, this->end());	this->destroy_range(this->begin()+N, this->end());
	this->setEnd(this->begin()+N);	this->setEnd(this->begin()+N);
	} else if (N > this->size()) {	} else if (N > this->size()) {
	if (this->capacity() < N)	if (this->capacity() < N)
	this->grow(N);	this->grow(N);

	this->construct_range(this->end(), this->begin()+N, T());	std::uninitialized_fill(this->end(), this->begin()+N, T());
	this->setEnd(this->begin()+N);	this->setEnd(this->begin()+N);
	}	}
	}	}

	void resize(unsigned N, const T &NV) {	void resize(unsigned N, const T &NV) {
	if (N < this->size()) {	if (N < this->size()) {
	this->destroy_range(this->begin()+N, this->end());	this->destroy_range(this->begin()+N, this->end());
	this->setEnd(this->begin()+N);	this->setEnd(this->begin()+N);
	} else if (N > this->size()) {	} else if (N > this->size()) {
	if (this->capacity() < N)	if (this->capacity() < N)
	this->grow(N);	this->grow(N);

	construct_range(this->end(), this->begin()+N, NV);	std::uninitialized_fill(this->end(), this->begin()+N, NV);
	this->setEnd(this->begin()+N);	this->setEnd(this->begin()+N);
	}	}
	}	}

	void reserve(unsigned N) {	void reserve(unsigned N) {
	if (this->capacity() < N)	if (this->capacity() < N)
	this->grow(N);	this->grow(N);
	}	}


	void push_back(const T &Elt) {
	if (this->EndX < this->CapacityX) {
	Retry:
	new (this->end()) T(Elt);
	this->setEnd(this->end()+1);
	return;
	}
	this->grow();
	goto Retry;
	}

	void pop_back() {
	this->setEnd(this->end()-1);
	this->end()->~T();
	}

	T pop_back_val() {	T pop_back_val() {
	T Result = this->back();	T Result = this->back();

	pop_back();	this->pop_back();
	return Result;	return Result;
	}	}

	void swap(SmallVectorImpl &RHS);	void swap(SmallVectorImpl &RHS);

	/// append - Add the specified range to the end of the SmallVector.	/// append - Add the specified range to the end of the SmallVector.
	///	///
	template<typename in_iter>	template<typename in_iter>
	void append(in_iter in_start, in_iter in_end) {	void append(in_iter in_start, in_iter in_end) {
	size_type NumInputs = std::distance(in_start, in_end);	size_type NumInputs = std::distance(in_start, in_end);

	skipping to change at line 375	skipping to change at line 369
	// Copy the new elements over.	// Copy the new elements over.
	std::uninitialized_fill_n(this->end(), NumInputs, Elt);	std::uninitialized_fill_n(this->end(), NumInputs, Elt);
	this->setEnd(this->end() + NumInputs);	this->setEnd(this->end() + NumInputs);
	}	}

	void assign(unsigned NumElts, const T &Elt) {	void assign(unsigned NumElts, const T &Elt) {
	clear();	clear();
	if (this->capacity() < NumElts)	if (this->capacity() < NumElts)
	this->grow(NumElts);	this->grow(NumElts);
	this->setEnd(this->begin()+NumElts);	this->setEnd(this->begin()+NumElts);

	construct_range(this->begin(), this->end(), Elt);	std::uninitialized_fill(this->begin(), this->end(), Elt);
	}	}

	iterator erase(iterator I) {	iterator erase(iterator I) {
	iterator N = I;	iterator N = I;
	// Shift all elts down one.	// Shift all elts down one.
	std::copy(I+1, this->end(), I);	std::copy(I+1, this->end(), I);
	// Drop the last elt.	// Drop the last elt.

	pop_back();	this->pop_back();
	return(N);	return(N);
	}	}

	iterator erase(iterator S, iterator E) {	iterator erase(iterator S, iterator E) {
	iterator N = S;	iterator N = S;
	// Shift all elts down.	// Shift all elts down.
	iterator I = std::copy(E, this->end(), S);	iterator I = std::copy(E, this->end(), S);
	// Drop the last elts.	// Drop the last elts.
	this->destroy_range(I, this->end());	this->destroy_range(I, this->end());
	this->setEnd(I);	this->setEnd(I);
	return(N);	return(N);
	}	}

	iterator insert(iterator I, const T &Elt) {	iterator insert(iterator I, const T &Elt) {
	if (I == this->end()) { // Important special case for empty vector.	if (I == this->end()) { // Important special case for empty vector.

	push_back(Elt);	this->push_back(Elt);
	return this->end()-1;	return this->end()-1;
	}	}

	if (this->EndX < this->CapacityX) {	if (this->EndX < this->CapacityX) {
	Retry:	Retry:
	new (this->end()) T(this->back());	new (this->end()) T(this->back());
	this->setEnd(this->end()+1);	this->setEnd(this->end()+1);
	// Push everything else over.	// Push everything else over.
	std::copy_backward(I, this->end()-1, this->end());	std::copy_backward(I, this->end()-1, this->end());


	skipping to change at line 553	skipping to change at line 547
	/// This does not construct or destroy any elements in the vector.	/// This does not construct or destroy any elements in the vector.
	///	///
	/// Clients can use this in conjunction with capacity() to write past the end	/// Clients can use this in conjunction with capacity() to write past the end
	/// of the buffer when they know that more elements are available, and on ly	/// of the buffer when they know that more elements are available, and on ly
	/// update the size later. This avoids the cost of value initializing ele ments	/// update the size later. This avoids the cost of value initializing ele ments
	/// which will only be overwritten.	/// which will only be overwritten.
	void set_size(unsigned N) {	void set_size(unsigned N) {
	assert(N <= this->capacity());	assert(N <= this->capacity());
	this->setEnd(this->begin() + N);	this->setEnd(this->begin() + N);
	}	}


	private:
	static void construct_range(T S, T E, const T &Elt) {
	for (; S != E; ++S)
	new (S) T(Elt);
	}
	};	};

	template <typename T>	template <typename T>
	void SmallVectorImpl<T>::swap(SmallVectorImpl<T> &RHS) {	void SmallVectorImpl<T>::swap(SmallVectorImpl<T> &RHS) {
	if (this == &RHS) return;	if (this == &RHS) return;

	// We can only avoid copying elements if neither vector is small.	// We can only avoid copying elements if neither vector is small.
	if (!this->isSmall() && !RHS.isSmall()) {	if (!this->isSmall() && !RHS.isSmall()) {
	std::swap(this->BeginX, RHS.BeginX);	std::swap(this->BeginX, RHS.BeginX);
	std::swap(this->EndX, RHS.EndX);	std::swap(this->EndX, RHS.EndX);

	skipping to change at line 683	skipping to change at line 671
	NumTsAvailable = (NumInlineEltsElts+1)*static_cast<unsigned int>(sizeof (U))/	NumTsAvailable = (NumInlineEltsElts+1)*static_cast<unsigned int>(sizeof (U))/
	static_cast<unsigned int>(sizeof(T))	static_cast<unsigned int>(sizeof(T))
	};	};
	U InlineElts[NumInlineEltsElts];	U InlineElts[NumInlineEltsElts];
	public:	public:
	SmallVector() : SmallVectorImpl<T>(NumTsAvailable) {	SmallVector() : SmallVectorImpl<T>(NumTsAvailable) {
	}	}

	explicit SmallVector(unsigned Size, const T &Value = T())	explicit SmallVector(unsigned Size, const T &Value = T())
	: SmallVectorImpl<T>(NumTsAvailable) {	: SmallVectorImpl<T>(NumTsAvailable) {

	this->reserve(Size);	this->assign(Size, Value);
	while (Size--)
	this->push_back(Value);
	}	}

	template<typename ItTy>	template<typename ItTy>
	SmallVector(ItTy S, ItTy E) : SmallVectorImpl<T>(NumTsAvailable) {	SmallVector(ItTy S, ItTy E) : SmallVectorImpl<T>(NumTsAvailable) {
	this->append(S, E);	this->append(S, E);
	}	}

	SmallVector(const SmallVector &RHS) : SmallVectorImpl<T>(NumTsAvailable) {	SmallVector(const SmallVector &RHS) : SmallVectorImpl<T>(NumTsAvailable) {
	if (!RHS.empty())	if (!RHS.empty())
	SmallVectorImpl<T>::operator=(RHS);	SmallVectorImpl<T>::operator=(RHS);

	skipping to change at line 715	skipping to change at line 701
	/// Specialize SmallVector at N=0. This specialization guarantees	/// Specialize SmallVector at N=0. This specialization guarantees
	/// that it can be instantiated at an incomplete T if none of its	/// that it can be instantiated at an incomplete T if none of its
	/// members are required.	/// members are required.
	template <typename T>	template <typename T>
	class SmallVector<T,0> : public SmallVectorImpl<T> {	class SmallVector<T,0> : public SmallVectorImpl<T> {
	public:	public:
	SmallVector() : SmallVectorImpl<T>(0) {}	SmallVector() : SmallVectorImpl<T>(0) {}

	explicit SmallVector(unsigned Size, const T &Value = T())	explicit SmallVector(unsigned Size, const T &Value = T())
	: SmallVectorImpl<T>(0) {	: SmallVectorImpl<T>(0) {

	this->reserve(Size);	this->assign(Size, Value);
	while (Size--)
	this->push_back(Value);
	}	}

	template<typename ItTy>	template<typename ItTy>
	SmallVector(ItTy S, ItTy E) : SmallVectorImpl<T>(0) {	SmallVector(ItTy S, ItTy E) : SmallVectorImpl<T>(0) {
	this->append(S, E);	this->append(S, E);
	}	}

	SmallVector(const SmallVector &RHS) : SmallVectorImpl<T>(0) {	SmallVector(const SmallVector &RHS) : SmallVectorImpl<T>(0) {
	SmallVectorImpl<T>::operator=(RHS);	SmallVectorImpl<T>::operator=(RHS);
	}	}

End of changes. 19 change blocks.
	65 lines changed or deleted	46 lines changed or added

	SourceMgr.h	SourceMgr.h

	skipping to change at line 20	skipping to change at line 20
	// This file declares the SMDiagnostic and SourceMgr classes. This	// This file declares the SMDiagnostic and SourceMgr classes. This
	// provides a simple substrate for diagnostics, #include handling, and othe r low	// provides a simple substrate for diagnostics, #include handling, and othe r low
	// level things for simple parsers.	// level things for simple parsers.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef SUPPORT_SOURCEMGR_H	#ifndef SUPPORT_SOURCEMGR_H
	#define SUPPORT_SOURCEMGR_H	#define SUPPORT_SOURCEMGR_H

	#include "llvm/Support/SMLoc.h"	#include "llvm/Support/SMLoc.h"

		#include "llvm/ADT/ArrayRef.h"
	#include <string>	#include <string>

	#include <vector>
	#include <cassert>

	namespace llvm {	namespace llvm {
	class MemoryBuffer;	class MemoryBuffer;
	class SourceMgr;	class SourceMgr;
	class SMDiagnostic;	class SMDiagnostic;
	class Twine;	class Twine;
	class raw_ostream;	class raw_ostream;

	/// SourceMgr - This owns the files read by a parser, handles include stack s,	/// SourceMgr - This owns the files read by a parser, handles include stack s,
	/// and handles diagnostic wrangling.	/// and handles diagnostic wrangling.
	class SourceMgr {	class SourceMgr {
	public:	public:

		enum DiagKind {
		DK_Error,
		DK_Warning,
		DK_Note
		};

	/// DiagHandlerTy - Clients that want to handle their own diagnostics in a	/// DiagHandlerTy - Clients that want to handle their own diagnostics in a
	/// custom way can register a function pointer+context as a diagnostic	/// custom way can register a function pointer+context as a diagnostic
	/// handler. It gets called each time PrintMessage is invoked.	/// handler. It gets called each time PrintMessage is invoked.

	typedef void (DiagHandlerTy)(const SMDiagnostic&, void Context);	typedef void (DiagHandlerTy)(const SMDiagnostic &, void Context);
	private:	private:
	struct SrcBuffer {	struct SrcBuffer {
	/// Buffer - The memory buffer for the file.	/// Buffer - The memory buffer for the file.
	MemoryBuffer *Buffer;	MemoryBuffer *Buffer;

	/// IncludeLoc - This is the location of the parent include, or null if at	/// IncludeLoc - This is the location of the parent include, or null if at
	/// the top level.	/// the top level.
	SMLoc IncludeLoc;	SMLoc IncludeLoc;
	};	};


	skipping to change at line 127	skipping to change at line 131
	/// specified location, returning -1 if not found.	/// specified location, returning -1 if not found.
	int FindBufferContainingLoc(SMLoc Loc) const;	int FindBufferContainingLoc(SMLoc Loc) const;

	/// FindLineNumber - Find the line number for the specified location in t he	/// FindLineNumber - Find the line number for the specified location in t he
	/// specified file. This is not a fast method.	/// specified file. This is not a fast method.
	unsigned FindLineNumber(SMLoc Loc, int BufferID = -1) const;	unsigned FindLineNumber(SMLoc Loc, int BufferID = -1) const;

	/// PrintMessage - Emit a message about the specified location with the	/// PrintMessage - Emit a message about the specified location with the
	/// specified string.	/// specified string.
	///	///

	/// @param Type - If non-null, the kind of message (e.g., "error") which	/// @param ShowColors - Display colored messages if output is a terminal
	is	and
	/// prefixed to the message.	/// the default error handler is used.
	/// @param ShowLine - Should the diagnostic show the source line.	void PrintMessage(SMLoc Loc, DiagKind Kind, const Twine &Msg,
	void PrintMessage(SMLoc Loc, const Twine &Msg, const char *Type,	ArrayRef<SMRange> Ranges = ArrayRef<SMRange>(),
	bool ShowLine = true) const;	bool ShowColors = true) const;

	/// GetMessage - Return an SMDiagnostic at the specified location with th e	/// GetMessage - Return an SMDiagnostic at the specified location with th e
	/// specified string.	/// specified string.
	///	///
	/// @param Type - If non-null, the kind of message (e.g., "error") which is	/// @param Type - If non-null, the kind of message (e.g., "error") which is
	/// prefixed to the message.	/// prefixed to the message.

	/// @param ShowLine - Should the diagnostic show the source line.	SMDiagnostic GetMessage(SMLoc Loc, DiagKind Kind, const Twine &Msg,
	SMDiagnostic GetMessage(SMLoc Loc,	ArrayRef<SMRange> Ranges = ArrayRef<SMRange>()) c
	const Twine &Msg, const char *Type,	onst;
	bool ShowLine = true) const;

	/// PrintIncludeStack - Prints the names of included files and the line o f the	/// PrintIncludeStack - Prints the names of included files and the line o f the
	/// file they were included from. A diagnostic handler can use this befo re	/// file they were included from. A diagnostic handler can use this befo re
	/// printing its custom formatted message.	/// printing its custom formatted message.
	///	///
	/// @param IncludeLoc - The line of the include.	/// @param IncludeLoc - The line of the include.
	/// @param OS the raw_ostream to print on.	/// @param OS the raw_ostream to print on.
	void PrintIncludeStack(SMLoc IncludeLoc, raw_ostream &OS) const;	void PrintIncludeStack(SMLoc IncludeLoc, raw_ostream &OS) const;
	};	};

	/// SMDiagnostic - Instances of this class encapsulate one diagnostic repor t,	/// SMDiagnostic - Instances of this class encapsulate one diagnostic repor t,
	/// allowing printing to a raw_ostream as a caret diagnostic.	/// allowing printing to a raw_ostream as a caret diagnostic.
	class SMDiagnostic {	class SMDiagnostic {
	const SourceMgr *SM;	const SourceMgr *SM;
	SMLoc Loc;	SMLoc Loc;
	std::string Filename;	std::string Filename;
	int LineNo, ColumnNo;	int LineNo, ColumnNo;

		SourceMgr::DiagKind Kind;
	std::string Message, LineContents;	std::string Message, LineContents;

	unsigned ShowLine : 1;	std::vector<std::pair<unsigned, unsigned> > Ranges;

	public:	public:
	// Null diagnostic.	// Null diagnostic.

	SMDiagnostic() : SM(0), LineNo(0), ColumnNo(0), ShowLine(0) {}	SMDiagnostic()
		: SM(0), LineNo(0), ColumnNo(0), Kind(SourceMgr::DK_Error) {}
	// Diagnostic with no location (e.g. file not found, command line arg err or).	// Diagnostic with no location (e.g. file not found, command line arg err or).

	SMDiagnostic(const std::string &filename, const std::string &Msg)	SMDiagnostic(const std::string &filename, SourceMgr::DiagKind Kind,
	: SM(0), Filename(filename), LineNo(-1), ColumnNo(-1),	const std::string &Msg)
	Message(Msg), ShowLine(false) {}	: SM(0), Filename(filename), LineNo(-1), ColumnNo(-1), Kind(Kind),
		Message(Msg) {}

	// Diagnostic with a location.	// Diagnostic with a location.
	SMDiagnostic(const SourceMgr &sm, SMLoc L, const std::string &FN,	SMDiagnostic(const SourceMgr &sm, SMLoc L, const std::string &FN,

	int Line, int Col,	int Line, int Col, SourceMgr::DiagKind Kind,
	const std::string &Msg, const std::string &LineStr,	const std::string &Msg, const std::string &LineStr,

	bool showline = true)	ArrayRef<std::pair<unsigned,unsigned> > Ranges);
	: SM(&sm), Loc(L), Filename(FN), LineNo(Line), ColumnNo(Col), Message(M
	sg),
	LineContents(LineStr), ShowLine(showline) {}

	const SourceMgr *getSourceMgr() const { return SM; }	const SourceMgr *getSourceMgr() const { return SM; }
	SMLoc getLoc() const { return Loc; }	SMLoc getLoc() const { return Loc; }
	const std::string &getFilename() const { return Filename; }	const std::string &getFilename() const { return Filename; }
	int getLineNo() const { return LineNo; }	int getLineNo() const { return LineNo; }
	int getColumnNo() const { return ColumnNo; }	int getColumnNo() const { return ColumnNo; }

		SourceMgr::DiagKind getKind() const { return Kind; }
	const std::string &getMessage() const { return Message; }	const std::string &getMessage() const { return Message; }
	const std::string &getLineContents() const { return LineContents; }	const std::string &getLineContents() const { return LineContents; }

	bool getShowLine() const { return ShowLine; }	const std::vector<std::pair<unsigned, unsigned> > &getRanges() const {
		return Ranges;
	void Print(const char *ProgName, raw_ostream &S) const;	}
		void print(const char *ProgName, raw_ostream &S, bool ShowColors = true)
		const;
	};	};

	} // end llvm namespace	} // end llvm namespace

	#endif	#endif

End of changes. 14 change blocks.
	27 lines changed or deleted	33 lines changed or added

	SparseBitVector.h	SparseBitVector.h

	skipping to change at line 21	skipping to change at line 21
	// SparseBitVector for more details on the algorithm used.	// SparseBitVector for more details on the algorithm used.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_ADT_SPARSEBITVECTOR_H	#ifndef LLVM_ADT_SPARSEBITVECTOR_H
	#define LLVM_ADT_SPARSEBITVECTOR_H	#define LLVM_ADT_SPARSEBITVECTOR_H

	#include "llvm/ADT/ilist.h"	#include "llvm/ADT/ilist.h"
	#include "llvm/ADT/ilist_node.h"	#include "llvm/ADT/ilist_node.h"
	#include "llvm/Support/DataTypes.h"	#include "llvm/Support/DataTypes.h"

		#include "llvm/Support/ErrorHandling.h"
	#include "llvm/Support/MathExtras.h"	#include "llvm/Support/MathExtras.h"
	#include "llvm/Support/raw_ostream.h"	#include "llvm/Support/raw_ostream.h"
	#include <cassert>	#include <cassert>
	#include <climits>	#include <climits>

	#include <cstring>

	namespace llvm {	namespace llvm {

	/// SparseBitVector is an implementation of a bitvector that is sparse by o nly	/// SparseBitVector is an implementation of a bitvector that is sparse by o nly
	/// storing the elements that have non-zero bits set. In order to make thi s	/// storing the elements that have non-zero bits set. In order to make thi s
	/// fast for the most common cases, SparseBitVector is implemented as a lin ked	/// fast for the most common cases, SparseBitVector is implemented as a lin ked
	/// list of SparseBitVectorElements. We maintain a pointer to the last	/// list of SparseBitVectorElements. We maintain a pointer to the last
	/// SparseBitVectorElement accessed (in the form of a list iterator), in or der	/// SparseBitVectorElement accessed (in the form of a list iterator), in or der
	/// to make multiple in-order test/set constant time after the first one is	/// to make multiple in-order test/set constant time after the first one is
	/// executed. Note that using vectors to store SparseBitVectorElement's do es	/// executed. Note that using vectors to store SparseBitVectorElement's do es

	skipping to change at line 130	skipping to change at line 130
	}	}

	unsigned count() const {	unsigned count() const {
	unsigned NumBits = 0;	unsigned NumBits = 0;
	for (unsigned i = 0; i < BITWORDS_PER_ELEMENT; ++i)	for (unsigned i = 0; i < BITWORDS_PER_ELEMENT; ++i)
	if (sizeof(BitWord) == 4)	if (sizeof(BitWord) == 4)
	NumBits += CountPopulation_32(Bits[i]);	NumBits += CountPopulation_32(Bits[i]);
	else if (sizeof(BitWord) == 8)	else if (sizeof(BitWord) == 8)
	NumBits += CountPopulation_64(Bits[i]);	NumBits += CountPopulation_64(Bits[i]);
	else	else

	assert(0 && "Unsupported!");	llvm_unreachable("Unsupported!");
	return NumBits;	return NumBits;
	}	}

	/// find_first - Returns the index of the first set bit.	/// find_first - Returns the index of the first set bit.
	int find_first() const {	int find_first() const {
	for (unsigned i = 0; i < BITWORDS_PER_ELEMENT; ++i)	for (unsigned i = 0; i < BITWORDS_PER_ELEMENT; ++i)
	if (Bits[i] != 0) {	if (Bits[i] != 0) {
	if (sizeof(BitWord) == 4)	if (sizeof(BitWord) == 4)
	return i * BITWORD_SIZE + CountTrailingZeros_32(Bits[i]);	return i * BITWORD_SIZE + CountTrailingZeros_32(Bits[i]);

	else if (sizeof(BitWord) == 8)	if (sizeof(BitWord) == 8)
	return i * BITWORD_SIZE + CountTrailingZeros_64(Bits[i]);	return i * BITWORD_SIZE + CountTrailingZeros_64(Bits[i]);

	else	llvm_unreachable("Unsupported!");
	assert(0 && "Unsupported!");
	}	}

	assert(0 && "Illegal empty element");	llvm_unreachable("Illegal empty element");
	return 0; // Not reached
	}	}

	/// find_next - Returns the index of the next set bit starting from the	/// find_next - Returns the index of the next set bit starting from the
	/// "Curr" bit. Returns -1 if the next set bit is not found.	/// "Curr" bit. Returns -1 if the next set bit is not found.
	int find_next(unsigned Curr) const {	int find_next(unsigned Curr) const {
	if (Curr >= BITS_PER_ELEMENT)	if (Curr >= BITS_PER_ELEMENT)
	return -1;	return -1;

	unsigned WordPos = Curr / BITWORD_SIZE;	unsigned WordPos = Curr / BITWORD_SIZE;
	unsigned BitPos = Curr % BITWORD_SIZE;	unsigned BitPos = Curr % BITWORD_SIZE;
	BitWord Copy = Bits[WordPos];	BitWord Copy = Bits[WordPos];
	assert (WordPos <= BITWORDS_PER_ELEMENT	assert (WordPos <= BITWORDS_PER_ELEMENT
	&& "Word Position outside of element");	&& "Word Position outside of element");

	// Mask off previous bits.	// Mask off previous bits.
	Copy &= ~0L << BitPos;	Copy &= ~0L << BitPos;

	if (Copy != 0) {	if (Copy != 0) {
	if (sizeof(BitWord) == 4)	if (sizeof(BitWord) == 4)
	return WordPos * BITWORD_SIZE + CountTrailingZeros_32(Copy);	return WordPos * BITWORD_SIZE + CountTrailingZeros_32(Copy);

	else if (sizeof(BitWord) == 8)	if (sizeof(BitWord) == 8)
	return WordPos * BITWORD_SIZE + CountTrailingZeros_64(Copy);	return WordPos * BITWORD_SIZE + CountTrailingZeros_64(Copy);

	else	llvm_unreachable("Unsupported!");
	assert(0 && "Unsupported!");
	}	}

	// Check subsequent words.	// Check subsequent words.
	for (unsigned i = WordPos+1; i < BITWORDS_PER_ELEMENT; ++i)	for (unsigned i = WordPos+1; i < BITWORDS_PER_ELEMENT; ++i)
	if (Bits[i] != 0) {	if (Bits[i] != 0) {
	if (sizeof(BitWord) == 4)	if (sizeof(BitWord) == 4)
	return i * BITWORD_SIZE + CountTrailingZeros_32(Bits[i]);	return i * BITWORD_SIZE + CountTrailingZeros_32(Bits[i]);

	else if (sizeof(BitWord) == 8)	if (sizeof(BitWord) == 8)
	return i * BITWORD_SIZE + CountTrailingZeros_64(Bits[i]);	return i * BITWORD_SIZE + CountTrailingZeros_64(Bits[i]);

	else	llvm_unreachable("Unsupported!");
	assert(0 && "Unsupported!");
	}	}
	return -1;	return -1;
	}	}

	// Union this element with RHS and return true if this one changed.	// Union this element with RHS and return true if this one changed.
	bool unionWith(const SparseBitVectorElement &RHS) {	bool unionWith(const SparseBitVectorElement &RHS) {
	bool changed = false;	bool changed = false;
	for (unsigned i = 0; i < BITWORDS_PER_ELEMENT; ++i) {	for (unsigned i = 0; i < BITWORDS_PER_ELEMENT; ++i) {
	BitWord old = changed ? 0 : Bits[i];	BitWord old = changed ? 0 : Bits[i];


	skipping to change at line 266	skipping to change at line 262
	bool allzero = true;	bool allzero = true;

	BecameZero = false;	BecameZero = false;
	for (unsigned i = 0; i < BITWORDS_PER_ELEMENT; ++i) {	for (unsigned i = 0; i < BITWORDS_PER_ELEMENT; ++i) {
	Bits[i] = RHS1.Bits[i] & ~RHS2.Bits[i];	Bits[i] = RHS1.Bits[i] & ~RHS2.Bits[i];
	if (Bits[i] != 0)	if (Bits[i] != 0)
	allzero = false;	allzero = false;
	}	}
	BecameZero = allzero;	BecameZero = allzero;
	}	}


	// Get a hash value for this element;
	uint64_t getHashValue() const {
	uint64_t HashVal = 0;
	for (unsigned i = 0; i < BITWORDS_PER_ELEMENT; ++i) {
	HashVal ^= Bits[i];
	}
	return HashVal;
	}
	};	};

	template <unsigned ElementSize = 128>	template <unsigned ElementSize = 128>
	class SparseBitVector {	class SparseBitVector {
	typedef ilist<SparseBitVectorElement<ElementSize> > ElementList;	typedef ilist<SparseBitVectorElement<ElementSize> > ElementList;
	typedef typename ElementList::iterator ElementListIter;	typedef typename ElementList::iterator ElementListIter;
	typedef typename ElementList::const_iterator ElementListConstIter;	typedef typename ElementList::const_iterator ElementListConstIter;
	enum {	enum {
	BITWORD_SIZE = SparseBitVectorElement<ElementSize>::BITWORD_SIZE	BITWORD_SIZE = SparseBitVectorElement<ElementSize>::BITWORD_SIZE
	};	};

	skipping to change at line 813	skipping to change at line 800

	return BitCount;	return BitCount;
	}	}
	iterator begin() const {	iterator begin() const {
	return iterator(this);	return iterator(this);
	}	}

	iterator end() const {	iterator end() const {
	return iterator(this, true);	return iterator(this, true);
	}	}


	// Get a hash value for this bitmap.
	uint64_t getHashValue() const {
	uint64_t HashVal = 0;
	for (ElementListConstIter Iter = Elements.begin();
	Iter != Elements.end();
	++Iter) {
	HashVal ^= Iter->index();
	HashVal ^= Iter->getHashValue();
	}
	return HashVal;
	}
	};	};

	// Convenience functions to allow Or and And without dereferencing in the u ser	// Convenience functions to allow Or and And without dereferencing in the u ser
	// code.	// code.

	template <unsigned ElementSize>	template <unsigned ElementSize>
	inline bool operator \|=(SparseBitVector<ElementSize> &LHS,	inline bool operator \|=(SparseBitVector<ElementSize> &LHS,
	const SparseBitVector<ElementSize> *RHS) {	const SparseBitVector<ElementSize> *RHS) {
	return LHS \|= *RHS;	return LHS \|= *RHS;
	}	}

End of changes. 12 change blocks.
	34 lines changed or deleted	9 lines changed or added

	Statistic.h	Statistic.h

	skipping to change at line 30	skipping to change at line 30
	// Later, in the code: ++NumInstsKilled;	// Later, in the code: ++NumInstsKilled;
	//	//
	// NOTE: Statistics must be declared as global variables.	// NOTE: Statistics must be declared as global variables.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_ADT_STATISTIC_H	#ifndef LLVM_ADT_STATISTIC_H
	#define LLVM_ADT_STATISTIC_H	#define LLVM_ADT_STATISTIC_H

	#include "llvm/Support/Atomic.h"	#include "llvm/Support/Atomic.h"

		#include "llvm/Support/Valgrind.h"

	namespace llvm {	namespace llvm {
	class raw_ostream;	class raw_ostream;

	class Statistic {	class Statistic {
	public:	public:
	const char *Name;	const char *Name;
	const char *Desc;	const char *Desc;
	volatile llvm::sys::cas_flag Value;	volatile llvm::sys::cas_flag Value;
	bool Initialized;	bool Initialized;

	skipping to change at line 113	skipping to change at line 114
	const Statistic &operator/=(const unsigned &V) {	const Statistic &operator/=(const unsigned &V) {
	sys::AtomicDiv(&Value, V);	sys::AtomicDiv(&Value, V);
	return init();	return init();
	}	}

	protected:	protected:
	Statistic &init() {	Statistic &init() {
	bool tmp = Initialized;	bool tmp = Initialized;
	sys::MemoryFence();	sys::MemoryFence();
	if (!tmp) RegisterStatistic();	if (!tmp) RegisterStatistic();

		TsanHappensAfter(this);
	return *this;	return *this;
	}	}
	void RegisterStatistic();	void RegisterStatistic();
	};	};

	// STATISTIC - A macro to make definition of statistics really simple. Thi s	// STATISTIC - A macro to make definition of statistics really simple. Thi s
	// automatically passes the DEBUG_TYPE of the file into the statistic.	// automatically passes the DEBUG_TYPE of the file into the statistic.
	#define STATISTIC(VARNAME, DESC) \	#define STATISTIC(VARNAME, DESC) \
	static llvm::Statistic VARNAME = { DEBUG_TYPE, DESC, 0, 0 }	static llvm::Statistic VARNAME = { DEBUG_TYPE, DESC, 0, 0 }


End of changes. 2 change blocks.
	0 lines changed or deleted	2 lines changed or added

	StringExtras.h	StringExtras.h

	skipping to change at line 18	skipping to change at line 18
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	//	//
	// This file contains some functions that are useful when dealing with stri ngs.	// This file contains some functions that are useful when dealing with stri ngs.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_ADT_STRINGEXTRAS_H	#ifndef LLVM_ADT_STRINGEXTRAS_H
	#define LLVM_ADT_STRINGEXTRAS_H	#define LLVM_ADT_STRINGEXTRAS_H

	#include "llvm/Support/DataTypes.h"	#include "llvm/Support/DataTypes.h"

	#include "llvm/ADT/APFloat.h"
	#include "llvm/ADT/DenseMapInfo.h"
	#include "llvm/ADT/StringRef.h"	#include "llvm/ADT/StringRef.h"

	#include <cctype>
	#include <cstdio>
	#include <string>

	namespace llvm {	namespace llvm {
	template<typename T> class SmallVectorImpl;	template<typename T> class SmallVectorImpl;

	/// hexdigit - Return the hexadecimal character for the	/// hexdigit - Return the hexadecimal character for the
	/// given number \arg X (which should be less than 16).	/// given number \arg X (which should be less than 16).
	static inline char hexdigit(unsigned X, bool LowerCase = false) {	static inline char hexdigit(unsigned X, bool LowerCase = false) {
	const char HexChar = LowerCase ? 'a' : 'A';	const char HexChar = LowerCase ? 'a' : 'A';
	return X < 10 ? '0' + X : HexChar + X - 10;	return X < 10 ? '0' + X : HexChar + X - 10;
	}	}

	skipping to change at line 103	skipping to change at line 98
	return std::string(BufPtr, Buffer+21);	return std::string(BufPtr, Buffer+21);
	}	}

	static inline std::string itostr(int64_t X) {	static inline std::string itostr(int64_t X) {
	if (X < 0)	if (X < 0)
	return utostr(static_cast<uint64_t>(-X), true);	return utostr(static_cast<uint64_t>(-X), true);
	else	else
	return utostr(static_cast<uint64_t>(X));	return utostr(static_cast<uint64_t>(X));
	}	}


	static inline std::string ftostr(double V) {
	char Buffer[200];
	sprintf(Buffer, "%20.6e", V);
	char *B = Buffer;
	while (*B == ' ') ++B;
	return B;
	}

	static inline std::string ftostr(const APFloat& V) {
	if (&V.getSemantics() == &APFloat::IEEEdouble)
	return ftostr(V.convertToDouble());
	else if (&V.getSemantics() == &APFloat::IEEEsingle)
	return ftostr((double)V.convertToFloat());
	return "<unknown format in ftostr>"; // error
	}

	static inline std::string LowercaseString(const std::string &S) {
	std::string result(S);
	for (unsigned i = 0; i < S.length(); ++i)
	if (isupper(result[i]))
	result[i] = char(tolower(result[i]));
	return result;
	}

	static inline std::string UppercaseString(const std::string &S) {
	std::string result(S);
	for (unsigned i = 0; i < S.length(); ++i)
	if (islower(result[i]))
	result[i] = char(toupper(result[i]));
	return result;
	}

	/// StrInStrNoCase - Portable version of strcasestr. Locates the first	/// StrInStrNoCase - Portable version of strcasestr. Locates the first
	/// occurrence of string 's1' in string 's2', ignoring case. Returns	/// occurrence of string 's1' in string 's2', ignoring case. Returns
	/// the offset of s2 in s1 or npos if s2 cannot be found.	/// the offset of s2 in s1 or npos if s2 cannot be found.
	StringRef::size_type StrInStrNoCase(StringRef s1, StringRef s2);	StringRef::size_type StrInStrNoCase(StringRef s1, StringRef s2);

	/// getToken - This function extracts one token from source, ignoring any	/// getToken - This function extracts one token from source, ignoring any
	/// leading characters that appear in the Delimiters string, and ending the	/// leading characters that appear in the Delimiters string, and ending the
	/// token at any of the characters that appear in the Delimiters string. I f	/// token at any of the characters that appear in the Delimiters string. I f
	/// there are no tokens in the source string, an empty string is returned.	/// there are no tokens in the source string, an empty string is returned.
	/// The function returns a pair containing the extracted token and the	/// The function returns a pair containing the extracted token and the

End of changes. 3 change blocks.
	37 lines changed or deleted	0 lines changed or added

	StringMap.h	StringMap.h

	skipping to change at line 53	skipping to change at line 53
	unsigned StrLen;	unsigned StrLen;
	public:	public:
	explicit StringMapEntryBase(unsigned Len) : StrLen(Len) {}	explicit StringMapEntryBase(unsigned Len) : StrLen(Len) {}

	unsigned getKeyLength() const { return StrLen; }	unsigned getKeyLength() const { return StrLen; }
	};	};

	/// StringMapImpl - This is the base class of StringMap that is shared amon g	/// StringMapImpl - This is the base class of StringMap that is shared amon g
	/// all of its instantiations.	/// all of its instantiations.
	class StringMapImpl {	class StringMapImpl {

	public:
	/// ItemBucket - The hash table consists of an array of these. If Item i
	s
	/// non-null, this is an extant entry, otherwise, it is a hole.
	struct ItemBucket {
	/// FullHashValue - This remembers the full hash value of the key for
	/// easy scanning.
	unsigned FullHashValue;

	/// Item - This is a pointer to the actual item object.
	StringMapEntryBase *Item;
	};

	protected:	protected:

	ItemBucket *TheTable;	// Array of NumBuckets pointers to entries, null pointers are holes.
		// TheTable[NumBuckets] contains a sentinel value for easy iteration. Fol
		lwed
		// by an array of the actual hash values as unsigned integers.
		StringMapEntryBase **TheTable;
	unsigned NumBuckets;	unsigned NumBuckets;
	unsigned NumItems;	unsigned NumItems;
	unsigned NumTombstones;	unsigned NumTombstones;
	unsigned ItemSize;	unsigned ItemSize;
	protected:	protected:
	explicit StringMapImpl(unsigned itemSize) : ItemSize(itemSize) {	explicit StringMapImpl(unsigned itemSize) : ItemSize(itemSize) {
	// Initialize the map with zero buckets to allocation.	// Initialize the map with zero buckets to allocation.
	TheTable = 0;	TheTable = 0;
	NumBuckets = 0;	NumBuckets = 0;
	NumItems = 0;	NumItems = 0;

	skipping to change at line 237	skipping to change at line 228
	}	}
	};	};

	/// StringMap - This is an unconventional map that is specialized for handl ing	/// StringMap - This is an unconventional map that is specialized for handl ing
	/// keys that are "strings", which are basically ranges of bytes. This does some	/// keys that are "strings", which are basically ranges of bytes. This does some
	/// funky memory allocation and hashing things to make it extremely efficie nt,	/// funky memory allocation and hashing things to make it extremely efficie nt,
	/// storing the string data after the value in the map.	/// storing the string data after the value in the map.
	template<typename ValueTy, typename AllocatorTy = MallocAllocator>	template<typename ValueTy, typename AllocatorTy = MallocAllocator>
	class StringMap : public StringMapImpl {	class StringMap : public StringMapImpl {
	AllocatorTy Allocator;	AllocatorTy Allocator;

	typedef StringMapEntry<ValueTy> MapEntryTy;
	public:	public:

		typedef StringMapEntry<ValueTy> MapEntryTy;

	StringMap() : StringMapImpl(static_cast<unsigned>(sizeof(MapEntryTy))) {}	StringMap() : StringMapImpl(static_cast<unsigned>(sizeof(MapEntryTy))) {}
	explicit StringMap(unsigned InitialSize)	explicit StringMap(unsigned InitialSize)
	: StringMapImpl(InitialSize, static_cast<unsigned>(sizeof(MapEntryTy))) {}	: StringMapImpl(InitialSize, static_cast<unsigned>(sizeof(MapEntryTy))) {}

	explicit StringMap(AllocatorTy A)	explicit StringMap(AllocatorTy A)
	: StringMapImpl(static_cast<unsigned>(sizeof(MapEntryTy))), Allocator(A ) {}	: StringMapImpl(static_cast<unsigned>(sizeof(MapEntryTy))), Allocator(A ) {}


	explicit StringMap(const StringMap &RHS)	StringMap(const StringMap &RHS)
	: StringMapImpl(static_cast<unsigned>(sizeof(MapEntryTy))) {	: StringMapImpl(static_cast<unsigned>(sizeof(MapEntryTy))) {
	assert(RHS.empty() &&	assert(RHS.empty() &&
	"Copy ctor from non-empty stringmap not implemented yet!");	"Copy ctor from non-empty stringmap not implemented yet!");
	(void)RHS;	(void)RHS;
	}	}
	void operator=(const StringMap &RHS) {	void operator=(const StringMap &RHS) {
	assert(RHS.empty() &&	assert(RHS.empty() &&
	"assignment from non-empty stringmap not implemented yet!");	"assignment from non-empty stringmap not implemented yet!");
	(void)RHS;	(void)RHS;
	clear();	clear();

	skipping to change at line 288	skipping to change at line 280
	const_iterator begin() const {	const_iterator begin() const {
	return const_iterator(TheTable, NumBuckets == 0);	return const_iterator(TheTable, NumBuckets == 0);
	}	}
	const_iterator end() const {	const_iterator end() const {
	return const_iterator(TheTable+NumBuckets, true);	return const_iterator(TheTable+NumBuckets, true);
	}	}

	iterator find(StringRef Key) {	iterator find(StringRef Key) {
	int Bucket = FindKey(Key);	int Bucket = FindKey(Key);
	if (Bucket == -1) return end();	if (Bucket == -1) return end();

	return iterator(TheTable+Bucket);	return iterator(TheTable+Bucket, true);
	}	}

	const_iterator find(StringRef Key) const {	const_iterator find(StringRef Key) const {
	int Bucket = FindKey(Key);	int Bucket = FindKey(Key);
	if (Bucket == -1) return end();	if (Bucket == -1) return end();

	return const_iterator(TheTable+Bucket);	return const_iterator(TheTable+Bucket, true);
	}	}

	/// lookup - Return the entry for the specified key, or a default	/// lookup - Return the entry for the specified key, or a default
	/// constructed value if no such entry exists.	/// constructed value if no such entry exists.
	ValueTy lookup(StringRef Key) const {	ValueTy lookup(StringRef Key) const {
	const_iterator it = find(Key);	const_iterator it = find(Key);
	if (it != end())	if (it != end())
	return it->second;	return it->second;
	return ValueTy();	return ValueTy();
	}	}

	skipping to change at line 319	skipping to change at line 311

	size_type count(StringRef Key) const {	size_type count(StringRef Key) const {
	return find(Key) == end() ? 0 : 1;	return find(Key) == end() ? 0 : 1;
	}	}

	/// insert - Insert the specified key/value pair into the map. If the ke y	/// insert - Insert the specified key/value pair into the map. If the ke y
	/// already exists in the map, return false and ignore the request, other wise	/// already exists in the map, return false and ignore the request, other wise
	/// insert it and return true.	/// insert it and return true.
	bool insert(MapEntryTy *KeyValue) {	bool insert(MapEntryTy *KeyValue) {
	unsigned BucketNo = LookupBucketFor(KeyValue->getKey());	unsigned BucketNo = LookupBucketFor(KeyValue->getKey());

	ItemBucket &Bucket = TheTable[BucketNo];	StringMapEntryBase *&Bucket = TheTable[BucketNo];
	if (Bucket.Item && Bucket.Item != getTombstoneVal())	if (Bucket && Bucket != getTombstoneVal())
	return false; // Already exists in map.	return false; // Already exists in map.


	if (Bucket.Item == getTombstoneVal())	if (Bucket == getTombstoneVal())
	--NumTombstones;	--NumTombstones;

	Bucket.Item = KeyValue;	Bucket = KeyValue;
	++NumItems;	++NumItems;
	assert(NumItems + NumTombstones <= NumBuckets);	assert(NumItems + NumTombstones <= NumBuckets);

	RehashTable();	RehashTable();
	return true;	return true;
	}	}

	// clear - Empties out the StringMap	// clear - Empties out the StringMap
	void clear() {	void clear() {
	if (empty()) return;	if (empty()) return;

	// Zap all values, resetting the keys back to non-present (not tombston e),	// Zap all values, resetting the keys back to non-present (not tombston e),
	// which is safe because we're removing all elements.	// which is safe because we're removing all elements.

	for (ItemBucket I = TheTable, E = TheTable+NumBuckets; I != E; ++I) {	for (unsigned I = 0, E = NumBuckets; I != E; ++I) {
	if (I->Item && I->Item != getTombstoneVal()) {	StringMapEntryBase *&Bucket = TheTable[I];
	static_cast<MapEntryTy*>(I->Item)->Destroy(Allocator);	if (Bucket && Bucket != getTombstoneVal()) {
	I->Item = 0;	static_cast<MapEntryTy*>(Bucket)->Destroy(Allocator);
		Bucket = 0;
	}	}
	}	}

	NumItems = 0;	NumItems = 0;
	NumTombstones = 0;	NumTombstones = 0;
	}	}

	/// GetOrCreateValue - Look up the specified key in the table. If a valu e	/// GetOrCreateValue - Look up the specified key in the table. If a valu e
	/// exists, return it. Otherwise, default construct a value, insert it, and	/// exists, return it. Otherwise, default construct a value, insert it, and
	/// return.	/// return.
	template <typename InitTy>	template <typename InitTy>
	MapEntryTy &GetOrCreateValue(StringRef Key, InitTy Val) {	MapEntryTy &GetOrCreateValue(StringRef Key, InitTy Val) {
	unsigned BucketNo = LookupBucketFor(Key);	unsigned BucketNo = LookupBucketFor(Key);

	ItemBucket &Bucket = TheTable[BucketNo];	StringMapEntryBase *&Bucket = TheTable[BucketNo];
	if (Bucket.Item && Bucket.Item != getTombstoneVal())	if (Bucket && Bucket != getTombstoneVal())
	return static_cast<MapEntryTy>(Bucket.Item);	return static_cast<MapEntryTy>(Bucket);

	MapEntryTy *NewItem =	MapEntryTy *NewItem =
	MapEntryTy::Create(Key.begin(), Key.end(), Allocator, Val);	MapEntryTy::Create(Key.begin(), Key.end(), Allocator, Val);


	if (Bucket.Item == getTombstoneVal())	if (Bucket == getTombstoneVal())
	--NumTombstones;	--NumTombstones;
	++NumItems;	++NumItems;
	assert(NumItems + NumTombstones <= NumBuckets);	assert(NumItems + NumTombstones <= NumBuckets);

	// Fill in the bucket for the hash table. The FullHashValue was alread y	// Fill in the bucket for the hash table. The FullHashValue was alread y
	// filled in by LookupBucketFor.	// filled in by LookupBucketFor.

	Bucket.Item = NewItem;	Bucket = NewItem;

	RehashTable();	RehashTable();
	return *NewItem;	return *NewItem;
	}	}

	MapEntryTy &GetOrCreateValue(StringRef Key) {	MapEntryTy &GetOrCreateValue(StringRef Key) {
	return GetOrCreateValue(Key, ValueTy());	return GetOrCreateValue(Key, ValueTy());
	}	}

	/// remove - Remove the specified key/value pair from the map, but do not	/// remove - Remove the specified key/value pair from the map, but do not

	skipping to change at line 408	skipping to change at line 401

	~StringMap() {	~StringMap() {
	clear();	clear();
	free(TheTable);	free(TheTable);
	}	}
	};	};

	template<typename ValueTy>	template<typename ValueTy>
	class StringMapConstIterator {	class StringMapConstIterator {
	protected:	protected:

	StringMapImpl::ItemBucket *Ptr;	StringMapEntryBase **Ptr;
	public:	public:
	typedef StringMapEntry<ValueTy> value_type;	typedef StringMapEntry<ValueTy> value_type;


	explicit StringMapConstIterator(StringMapImpl::ItemBucket *Bucket,	explicit StringMapConstIterator(StringMapEntryBase **Bucket,
	bool NoAdvance = false)	bool NoAdvance = false)
	: Ptr(Bucket) {	: Ptr(Bucket) {
	if (!NoAdvance) AdvancePastEmptyBuckets();	if (!NoAdvance) AdvancePastEmptyBuckets();
	}	}

	const value_type &operator*() const {	const value_type &operator*() const {

	return static_cast<StringMapEntry<ValueTy>>(Ptr->Item);	return static_cast<StringMapEntry<ValueTy>>(*Ptr);
	}	}
	const value_type *operator->() const {	const value_type *operator->() const {

	return static_cast<StringMapEntry<ValueTy>*>(Ptr->Item);	return static_cast<StringMapEntry<ValueTy>>(Ptr);
	}	}

	bool operator==(const StringMapConstIterator &RHS) const {	bool operator==(const StringMapConstIterator &RHS) const {
	return Ptr == RHS.Ptr;	return Ptr == RHS.Ptr;
	}	}
	bool operator!=(const StringMapConstIterator &RHS) const {	bool operator!=(const StringMapConstIterator &RHS) const {
	return Ptr != RHS.Ptr;	return Ptr != RHS.Ptr;
	}	}

	inline StringMapConstIterator& operator++() { // Preincrement	inline StringMapConstIterator& operator++() { // Preincrement
	++Ptr;	++Ptr;
	AdvancePastEmptyBuckets();	AdvancePastEmptyBuckets();
	return *this;	return *this;
	}	}
	StringMapConstIterator operator++(int) { // Postincrement	StringMapConstIterator operator++(int) { // Postincrement
	StringMapConstIterator tmp = this; ++this; return tmp;	StringMapConstIterator tmp = this; ++this; return tmp;
	}	}

	private:	private:
	void AdvancePastEmptyBuckets() {	void AdvancePastEmptyBuckets() {

	while (Ptr->Item == 0 \|\| Ptr->Item == StringMapImpl::getTombstoneVal())	while (Ptr == 0 \|\| Ptr == StringMapImpl::getTombstoneVal())
	++Ptr;	++Ptr;
	}	}
	};	};

	template<typename ValueTy>	template<typename ValueTy>
	class StringMapIterator : public StringMapConstIterator<ValueTy> {	class StringMapIterator : public StringMapConstIterator<ValueTy> {
	public:	public:

	explicit StringMapIterator(StringMapImpl::ItemBucket *Bucket,	explicit StringMapIterator(StringMapEntryBase **Bucket,
	bool NoAdvance = false)	bool NoAdvance = false)
	: StringMapConstIterator<ValueTy>(Bucket, NoAdvance) {	: StringMapConstIterator<ValueTy>(Bucket, NoAdvance) {
	}	}
	StringMapEntry<ValueTy> &operator*() const {	StringMapEntry<ValueTy> &operator*() const {

	return static_cast<StringMapEntry<ValueTy>>(this->Ptr->Item);	return static_cast<StringMapEntry<ValueTy>>(*this->Ptr);
	}	}
	StringMapEntry<ValueTy> *operator->() const {	StringMapEntry<ValueTy> *operator->() const {

	return static_cast<StringMapEntry<ValueTy>*>(this->Ptr->Item);	return static_cast<StringMapEntry<ValueTy>>(this->Ptr);
	}	}
	};	};

	}	}

	#endif	#endif

End of changes. 22 change blocks.
	39 lines changed or deleted	32 lines changed or added

	StringRef.h	StringRef.h

	skipping to change at line 13	skipping to change at line 13
	// The LLVM Compiler Infrastructure	// The LLVM Compiler Infrastructure
	//	//
	// This file is distributed under the University of Illinois Open Source	// This file is distributed under the University of Illinois Open Source
	// License. See LICENSE.TXT for details.	// License. See LICENSE.TXT for details.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_ADT_STRINGREF_H	#ifndef LLVM_ADT_STRINGREF_H
	#define LLVM_ADT_STRINGREF_H	#define LLVM_ADT_STRINGREF_H


		#include "llvm/Support/type_traits.h"

	#include <cassert>	#include <cassert>
	#include <cstring>	#include <cstring>

	#include <utility>	#include <limits>
	#include <string>	#include <string>

		#include <utility>

	namespace llvm {	namespace llvm {
	template<typename T>	template<typename T>
	class SmallVectorImpl;	class SmallVectorImpl;
	class APInt;	class APInt;

		class hash_code;
		class StringRef;

		/// Helper functions for StringRef::getAsInteger.
		bool getAsUnsignedInteger(StringRef Str, unsigned Radix,
		unsigned long long &Result);

		bool getAsSignedInteger(StringRef Str, unsigned Radix, long long &Result)
		;

	/// StringRef - Represent a constant reference to a string, i.e. a charac ter	/// StringRef - Represent a constant reference to a string, i.e. a charac ter
	/// array and a length, which need not be null terminated.	/// array and a length, which need not be null terminated.
	///	///
	/// This class does not own the string data, it is expected to be used in	/// This class does not own the string data, it is expected to be used in
	/// situations where the character data resides in some other buffer, who se	/// situations where the character data resides in some other buffer, who se
	/// lifetime extends past that of the StringRef. For this reason, it is n ot in	/// lifetime extends past that of the StringRef. For this reason, it is n ot in
	/// general safe to store a StringRef.	/// general safe to store a StringRef.
	class StringRef {	class StringRef {
	public:	public:

	skipping to change at line 307	skipping to change at line 318
	/// count - Return the number of non-overlapped occurrences of \arg Str in	/// count - Return the number of non-overlapped occurrences of \arg Str in
	/// the string.	/// the string.
	size_t count(StringRef Str) const;	size_t count(StringRef Str) const;

	/// getAsInteger - Parse the current string as an integer of the specif ied	/// getAsInteger - Parse the current string as an integer of the specif ied
	/// radix. If Radix is specified as zero, this does radix autosensing using	/// radix. If Radix is specified as zero, this does radix autosensing using
	/// extended C rules: 0 is octal, 0x is hex, 0b is binary.	/// extended C rules: 0 is octal, 0x is hex, 0b is binary.
	///	///
	/// If the string is invalid or if only a subset of the string is valid ,	/// If the string is invalid or if only a subset of the string is valid ,
	/// this returns true to signify the error. The string is considered	/// this returns true to signify the error. The string is considered

	/// erroneous if empty.	/// erroneous if empty or if it overflows T.
	///	///

	bool getAsInteger(unsigned Radix, long long &Result) const;	template <typename T>
	bool getAsInteger(unsigned Radix, unsigned long long &Result) const;	typename enable_if_c<std::numeric_limits<T>::is_signed, bool>::type
	bool getAsInteger(unsigned Radix, int &Result) const;	getAsInteger(unsigned Radix, T &Result) const {
	bool getAsInteger(unsigned Radix, unsigned &Result) const;	long long LLVal;
		if (getAsSignedInteger(*this, Radix, LLVal) \|\|
	// TODO: Provide overloads for int/unsigned that check for overflow.	static_cast<T>(LLVal) != LLVal)
		return true;
		Result = LLVal;
		return false;
		}

		template <typename T>
		typename enable_if_c<!std::numeric_limits<T>::is_signed, bool>::type
		getAsInteger(unsigned Radix, T &Result) const {
		unsigned long long ULLVal;
		if (getAsUnsignedInteger(*this, Radix, ULLVal) \|\|
		static_cast<T>(ULLVal) != ULLVal)
		return true;
		Result = ULLVal;
		return false;
		}

	/// getAsInteger - Parse the current string as an integer of the	/// getAsInteger - Parse the current string as an integer of the
	/// specified radix, or of an autosensed radix if the radix given	/// specified radix, or of an autosensed radix if the radix given
	/// is 0. The current value in Result is discarded, and the	/// is 0. The current value in Result is discarded, and the
	/// storage is changed to be wide enough to store the parsed	/// storage is changed to be wide enough to store the parsed
	/// integer.	/// integer.
	///	///
	/// Returns true if the string does not solely consist of a valid	/// Returns true if the string does not solely consist of a valid
	/// non-empty number in the appropriate base.	/// non-empty number in the appropriate base.
	///	///
	/// APInt::fromString is superficially similar but assumes the	/// APInt::fromString is superficially similar but assumes the
	/// string is well-formed in the given radix.	/// string is well-formed in the given radix.
	bool getAsInteger(unsigned Radix, APInt &Result) const;	bool getAsInteger(unsigned Radix, APInt &Result) const;

	/// @}	/// @}

		/// @name String Operations
		/// @{

		// lower - Convert the given ASCII string to lowercase.
		std::string lower() const;

		/// upper - Convert the given ASCII string to uppercase.
		std::string upper() const;

		/// @}
	/// @name Substring Operations	/// @name Substring Operations
	/// @{	/// @{

	/// substr - Return a reference to the substring from [Start, Start + N ).	/// substr - Return a reference to the substring from [Start, Start + N ).
	///	///
	/// \param Start - The index of the starting character in the substring ; if	/// \param Start - The index of the starting character in the substring ; if
	/// the index is npos or greater than the length of the string then the	/// the index is npos or greater than the length of the string then the
	/// empty substring will be returned.	/// empty substring will be returned.
	///	///
	/// \param N - The number of characters to included in the substring. I f N	/// \param N - The number of characters to included in the substring. I f N
	/// exceeds the number of characters remaining in the string, the strin g	/// exceeds the number of characters remaining in the string, the strin g
	/// suffix (starting with \arg Start) will be returned.	/// suffix (starting with \arg Start) will be returned.
	StringRef substr(size_t Start, size_t N = npos) const {	StringRef substr(size_t Start, size_t N = npos) const {
	Start = min(Start, Length);	Start = min(Start, Length);
	return StringRef(Data + Start, min(N, Length - Start));	return StringRef(Data + Start, min(N, Length - Start));
	}	}


		/// drop_front - Return a StringRef equal to 'this' but with the first
		/// elements dropped.
		StringRef drop_front(unsigned N = 1) const {
		assert(size() >= N && "Dropping more elements than exist");
		return substr(N);
		}

		/// drop_back - Return a StringRef equal to 'this' but with the last
		/// elements dropped.
		StringRef drop_back(unsigned N = 1) const {
		assert(size() >= N && "Dropping more elements than exist");
		return substr(0, size()-N);
		}

	/// slice - Return a reference to the substring from [Start, End).	/// slice - Return a reference to the substring from [Start, End).
	///	///
	/// \param Start - The index of the starting character in the substring ; if	/// \param Start - The index of the starting character in the substring ; if
	/// the index is npos or greater than the length of the string then the	/// the index is npos or greater than the length of the string then the
	/// empty substring will be returned.	/// empty substring will be returned.
	///	///
	/// \param End - The index following the last character to include in t he	/// \param End - The index following the last character to include in t he
	/// substring. If this is npos, or less than \arg Start, or exceeds the	/// substring. If this is npos, or less than \arg Start, or exceeds the
	/// number of characters remaining in the string, the string suffix	/// number of characters remaining in the string, the string suffix
	/// (starting with \arg Start) will be returned.	/// (starting with \arg Start) will be returned.

	skipping to change at line 469	skipping to change at line 519
	inline bool operator>=(StringRef LHS, StringRef RHS) {	inline bool operator>=(StringRef LHS, StringRef RHS) {
	return LHS.compare(RHS) != -1;	return LHS.compare(RHS) != -1;
	}	}

	inline std::string &operator+=(std::string &buffer, llvm::StringRef strin g) {	inline std::string &operator+=(std::string &buffer, llvm::StringRef strin g) {
	return buffer.append(string.data(), string.size());	return buffer.append(string.data(), string.size());
	}	}

	/// @}	/// @}


		/// \brief Compute a hash_code for a StringRef.
		hash_code hash_value(StringRef S);

	// StringRefs can be treated like a POD type.	// StringRefs can be treated like a POD type.
	template <typename T> struct isPodLike;	template <typename T> struct isPodLike;
	template <> struct isPodLike<StringRef> { static const bool value = true; };	template <> struct isPodLike<StringRef> { static const bool value = true; };

	}	}

	#endif	#endif

End of changes. 9 change blocks.
	8 lines changed or deleted	62 lines changed or added

	TableGenAction.h	TableGenAction.h

	skipping to change at line 24	skipping to change at line 24

	#ifndef LLVM_TABLEGEN_TABLEGENACTION_H	#ifndef LLVM_TABLEGEN_TABLEGENACTION_H
	#define LLVM_TABLEGEN_TABLEGENACTION_H	#define LLVM_TABLEGEN_TABLEGENACTION_H

	namespace llvm {	namespace llvm {

	class raw_ostream;	class raw_ostream;
	class RecordKeeper;	class RecordKeeper;

	class TableGenAction {	class TableGenAction {

		virtual void anchor();
	public:	public:
	virtual ~TableGenAction() {}	virtual ~TableGenAction() {}

	/// Perform the action using Records, and write output to OS.	/// Perform the action using Records, and write output to OS.
	/// @returns true on error, false otherwise	/// @returns true on error, false otherwise
	virtual bool operator()(raw_ostream &OS, RecordKeeper &Records) = 0;	virtual bool operator()(raw_ostream &OS, RecordKeeper &Records) = 0;
	};	};

	}	}


End of changes. 1 change blocks.
	0 lines changed or deleted	1 lines changed or added

	TableGenBackend.h	TableGenBackend.h

	skipping to change at line 19	skipping to change at line 19
	//	//
	// The TableGenBackend class is provided as a common interface for all Tabl eGen	// The TableGenBackend class is provided as a common interface for all Tabl eGen
	// backends. It provides useful services and an standardized interface.	// backends. It provides useful services and an standardized interface.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_TABLEGEN_TABLEGENBACKEND_H	#ifndef LLVM_TABLEGEN_TABLEGENBACKEND_H
	#define LLVM_TABLEGEN_TABLEGENBACKEND_H	#define LLVM_TABLEGEN_TABLEGENBACKEND_H

	#include "llvm/Support/raw_ostream.h"	#include "llvm/Support/raw_ostream.h"

	#include <string>

	namespace llvm {	namespace llvm {

	class Record;	class Record;
	class RecordKeeper;	class RecordKeeper;

	struct TableGenBackend {	struct TableGenBackend {

		virtual void anchor();
	virtual ~TableGenBackend() {}	virtual ~TableGenBackend() {}

	// run - All TableGen backends should implement the run method, which sho uld	// run - All TableGen backends should implement the run method, which sho uld
	// be the main entry point.	// be the main entry point.
	virtual void run(raw_ostream &OS) = 0;	virtual void run(raw_ostream &OS) = 0;

	public: // Useful helper routines...	public: // Useful helper routines...
	/// EmitSourceFileHeader - Output a LLVM style file header to the specifi ed	/// EmitSourceFileHeader - Output a LLVM style file header to the specifi ed
	/// ostream.	/// ostream.

	void EmitSourceFileHeader(const std::string &Desc, raw_ostream &OS) const ;	void EmitSourceFileHeader(StringRef Desc, raw_ostream &OS) const;

	};	};

	} // End llvm namespace	} // End llvm namespace

	#endif	#endif

End of changes. 3 change blocks.
	2 lines changed or deleted	2 lines changed or added

	Target.h	Target.h

	skipping to change at line 29	skipping to change at line 29
	#ifndef LLVM_C_TARGET_H	#ifndef LLVM_C_TARGET_H
	#define LLVM_C_TARGET_H	#define LLVM_C_TARGET_H

	#include "llvm-c/Core.h"	#include "llvm-c/Core.h"
	#include "llvm/Config/llvm-config.h"	#include "llvm/Config/llvm-config.h"

	#ifdef __cplusplus	#ifdef __cplusplus
	extern "C" {	extern "C" {
	#endif	#endif


		/**
		* @defgroup LLVMCTarget Target information
		* @ingroup LLVMC
		*
		* @{
		*/

	enum LLVMByteOrdering { LLVMBigEndian, LLVMLittleEndian };	enum LLVMByteOrdering { LLVMBigEndian, LLVMLittleEndian };

	typedef struct LLVMOpaqueTargetData *LLVMTargetDataRef;	typedef struct LLVMOpaqueTargetData *LLVMTargetDataRef;
	typedef struct LLVMOpaqueTargetLibraryInfotData *LLVMTargetLibraryInfoRef;	typedef struct LLVMOpaqueTargetLibraryInfotData *LLVMTargetLibraryInfoRef;
	typedef struct LLVMStructLayout *LLVMStructLayoutRef;	typedef struct LLVMStructLayout *LLVMStructLayoutRef;

	/* Declare all of the target-initialization functions that are available. * /	/* Declare all of the target-initialization functions that are available. * /
	#define LLVM_TARGET(TargetName) \	#define LLVM_TARGET(TargetName) \
	void LLVMInitialize##TargetName##TargetInfo(void);	void LLVMInitialize##TargetName##TargetInfo(void);
	#include "llvm/Config/Targets.def"	#include "llvm/Config/Targets.def"

	skipping to change at line 50	skipping to change at line 57

	#define LLVM_TARGET(TargetName) void LLVMInitialize##TargetName##Target(voi d);	#define LLVM_TARGET(TargetName) void LLVMInitialize##TargetName##Target(voi d);
	#include "llvm/Config/Targets.def"	#include "llvm/Config/Targets.def"
	#undef LLVM_TARGET /* Explicit undef to make SWIG happier */	#undef LLVM_TARGET /* Explicit undef to make SWIG happier */

	#define LLVM_TARGET(TargetName) \	#define LLVM_TARGET(TargetName) \
	void LLVMInitialize##TargetName##TargetMC(void);	void LLVMInitialize##TargetName##TargetMC(void);
	#include "llvm/Config/Targets.def"	#include "llvm/Config/Targets.def"
	#undef LLVM_TARGET /* Explicit undef to make SWIG happier */	#undef LLVM_TARGET /* Explicit undef to make SWIG happier */


		/* Declare all of the available assembly printer initialization functions.
		*/
		#define LLVM_ASM_PRINTER(TargetName) \
		void LLVMInitialize##TargetName##AsmPrinter();
		#include "llvm/Config/AsmPrinters.def"
		#undef LLVM_ASM_PRINTER /* Explicit undef to make SWIG happier */

		/* Declare all of the available assembly parser initialization functions. *
		/
		#define LLVM_ASM_PARSER(TargetName) \
		void LLVMInitialize##TargetName##AsmParser();
		#include "llvm/Config/AsmParsers.def"
		#undef LLVM_ASM_PARSER /* Explicit undef to make SWIG happier */

		/* Declare all of the available disassembler initialization functions. */
		#define LLVM_DISASSEMBLER(TargetName) \
		void LLVMInitialize##TargetName##Disassembler();
		#include "llvm/Config/Disassemblers.def"
		#undef LLVM_DISASSEMBLER /* Explicit undef to make SWIG happier */

	/** LLVMInitializeAllTargetInfos - The main program should call this functi on if	/** LLVMInitializeAllTargetInfos - The main program should call this functi on if
	it wants access to all available targets that LLVM is configured to	it wants access to all available targets that LLVM is configured to
	support. */	support. */
	static inline void LLVMInitializeAllTargetInfos(void) {	static inline void LLVMInitializeAllTargetInfos(void) {
	#define LLVM_TARGET(TargetName) LLVMInitialize##TargetName##TargetInfo();	#define LLVM_TARGET(TargetName) LLVMInitialize##TargetName##TargetInfo();
	#include "llvm/Config/Targets.def"	#include "llvm/Config/Targets.def"
	#undef LLVM_TARGET /* Explicit undef to make SWIG happier */	#undef LLVM_TARGET /* Explicit undef to make SWIG happier */
	}	}

	/** LLVMInitializeAllTargets - The main program should call this function i f it	/** LLVMInitializeAllTargets - The main program should call this function i f it
	wants to link in all available targets that LLVM is configured to	wants to link in all available targets that LLVM is configured to
	support. */	support. */
	static inline void LLVMInitializeAllTargets(void) {	static inline void LLVMInitializeAllTargets(void) {
	#define LLVM_TARGET(TargetName) LLVMInitialize##TargetName##Target();	#define LLVM_TARGET(TargetName) LLVMInitialize##TargetName##Target();
	#include "llvm/Config/Targets.def"	#include "llvm/Config/Targets.def"
	#undef LLVM_TARGET /* Explicit undef to make SWIG happier */	#undef LLVM_TARGET /* Explicit undef to make SWIG happier */
	}	}


		/** LLVMInitializeAllTargetMCs - The main program should call this function
		if
		it wants access to all available target MC that LLVM is configured to
		support. */
		static inline void LLVMInitializeAllTargetMCs(void) {
		#define LLVM_TARGET(TargetName) LLVMInitialize##TargetName##TargetMC();
		#include "llvm/Config/Targets.def"
		#undef LLVM_TARGET /* Explicit undef to make SWIG happier */
		}

		/** LLVMInitializeAllAsmPrinters - The main program should call this functi
		on if
		it wants all asm printers that LLVM is configured to support, to make t
		hem
		available via the TargetRegistry. */
		static inline void LLVMInitializeAllAsmPrinters() {
		#define LLVM_ASM_PRINTER(TargetName) LLVMInitialize##TargetName##AsmPrinter
		();
		#include "llvm/Config/AsmPrinters.def"
		#undef LLVM_ASM_PRINTER /* Explicit undef to make SWIG happier */
		}

		/** LLVMInitializeAllAsmParsers - The main program should call this functio
		n if
		it wants all asm parsers that LLVM is configured to support, to make th
		em
		available via the TargetRegistry. */
		static inline void LLVMInitializeAllAsmParsers() {
		#define LLVM_ASM_PARSER(TargetName) LLVMInitialize##TargetName##AsmParser()
		;
		#include "llvm/Config/AsmParsers.def"
		#undef LLVM_ASM_PARSER /* Explicit undef to make SWIG happier */
		}

		/** LLVMInitializeAllDisassemblers - The main program should call this func
		tion
		if it wants all disassemblers that LLVM is configured to support, to ma
		ke
		them available via the TargetRegistry. */
		static inline void LLVMInitializeAllDisassemblers() {
		#define LLVM_DISASSEMBLER(TargetName) \
		LLVMInitialize##TargetName##Disassembler();
		#include "llvm/Config/Disassemblers.def"
		#undef LLVM_DISASSEMBLER /* Explicit undef to make SWIG happier */
		}

	/** LLVMInitializeNativeTarget - The main program should call this function to	/** LLVMInitializeNativeTarget - The main program should call this function to
	initialize the native target corresponding to the host. This is useful	initialize the native target corresponding to the host. This is useful
	for JIT applications to ensure that the target gets linked in correctly . */	for JIT applications to ensure that the target gets linked in correctly . */
	static inline LLVMBool LLVMInitializeNativeTarget(void) {	static inline LLVMBool LLVMInitializeNativeTarget(void) {
	/* If we have a native target, initialize it to ensure it is linked in. * /	/* If we have a native target, initialize it to ensure it is linked in. * /
	#ifdef LLVM_NATIVE_TARGET	#ifdef LLVM_NATIVE_TARGET
	LLVM_NATIVE_TARGETINFO();	LLVM_NATIVE_TARGETINFO();
	LLVM_NATIVE_TARGET();	LLVM_NATIVE_TARGET();
	LLVM_NATIVE_TARGETMC();	LLVM_NATIVE_TARGETMC();
	return 0;	return 0;

	skipping to change at line 160	skipping to change at line 222

	/** Computes the byte offset of the indexed struct element for a target.	/** Computes the byte offset of the indexed struct element for a target.
	See the method llvm::StructLayout::getElementContainingOffset. */	See the method llvm::StructLayout::getElementContainingOffset. */
	unsigned long long LLVMOffsetOfElement(LLVMTargetDataRef, LLVMTypeRef Struc tTy,	unsigned long long LLVMOffsetOfElement(LLVMTargetDataRef, LLVMTypeRef Struc tTy,
	unsigned Element);	unsigned Element);

	/** Deallocates a TargetData.	/** Deallocates a TargetData.
	See the destructor llvm::TargetData::~TargetData. */	See the destructor llvm::TargetData::~TargetData. */
	void LLVMDisposeTargetData(LLVMTargetDataRef);	void LLVMDisposeTargetData(LLVMTargetDataRef);


		/**
		* @}
		*/

	#ifdef __cplusplus	#ifdef __cplusplus
	}	}

	namespace llvm {	namespace llvm {
	class TargetData;	class TargetData;
	class TargetLibraryInfo;	class TargetLibraryInfo;

	inline TargetData *unwrap(LLVMTargetDataRef P) {	inline TargetData *unwrap(LLVMTargetDataRef P) {
	return reinterpret_cast<TargetData*>(P);	return reinterpret_cast<TargetData*>(P);
	}	}

End of changes. 4 change blocks.
	0 lines changed or deleted	77 lines changed or added

	Target.td	Target.td

	skipping to change at line 25	skipping to change at line 25
	// Include all information about LLVM intrinsics.	// Include all information about LLVM intrinsics.
	include "llvm/Intrinsics.td"	include "llvm/Intrinsics.td"

	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	// Register file description - These classes are used to fill in the target	// Register file description - These classes are used to fill in the target
	// description classes.	// description classes.

	class RegisterClass; // Forward def	class RegisterClass; // Forward def

	// SubRegIndex - Use instances of SubRegIndex to identify subregisters.	// SubRegIndex - Use instances of SubRegIndex to identify subregisters.

	class SubRegIndex {	class SubRegIndex<list<SubRegIndex> comps = []> {
	string Namespace = "";	string Namespace = "";


		// ComposedOf - A list of two SubRegIndex instances, [A, B].
		// This indicates that this SubRegIndex is the result of composing A and
		B.
		list<SubRegIndex> ComposedOf = comps;
	}	}

	// RegAltNameIndex - The alternate name set to use for register operands of	// RegAltNameIndex - The alternate name set to use for register operands of
	// this register class when printing.	// this register class when printing.
	class RegAltNameIndex {	class RegAltNameIndex {
	string Namespace = "";	string Namespace = "";
	}	}
	def NoRegAltName : RegAltNameIndex;	def NoRegAltName : RegAltNameIndex;

	// Register - You should define one instance of this class for each registe r	// Register - You should define one instance of this class for each registe r

	skipping to change at line 89	skipping to change at line 93
	// -1 indicates that the gcc number is undefined and -2 that register num ber	// -1 indicates that the gcc number is undefined and -2 that register num ber
	// is invalid for this mode/flavour.	// is invalid for this mode/flavour.
	list<int> DwarfNumbers = [];	list<int> DwarfNumbers = [];

	// CostPerUse - Additional cost of instructions using this register compa red	// CostPerUse - Additional cost of instructions using this register compa red
	// to other registers in its class. The register allocator will try to	// to other registers in its class. The register allocator will try to
	// minimize the number of instructions using a register with a CostPerUse .	// minimize the number of instructions using a register with a CostPerUse .
	// This is used by the x86-64 and ARM Thumb targets where some registers	// This is used by the x86-64 and ARM Thumb targets where some registers
	// require larger instruction encodings.	// require larger instruction encodings.
	int CostPerUse = 0;	int CostPerUse = 0;


		// CoveredBySubRegs - When this bit is set, the value of this register is
		// completely determined by the value of its sub-registers. For example,
		the
		// x86 register AX is covered by its sub-registers AL and AH, but EAX is
		not
		// covered by its sub-register AX.
		bit CoveredBySubRegs = 0;
	}	}

	// RegisterWithSubRegs - This can be used to define instances of Register w hich	// RegisterWithSubRegs - This can be used to define instances of Register w hich
	// need to specify sub-registers.	// need to specify sub-registers.
	// List "subregs" specifies which registers are sub-registers to this one. This	// List "subregs" specifies which registers are sub-registers to this one. This
	// is used to populate the SubRegs and AliasSet fields of TargetRegisterDes c.	// is used to populate the SubRegs and AliasSet fields of TargetRegisterDes c.
	// This allows the code generator to be careful not to put two values with	// This allows the code generator to be careful not to put two values with
	// overlapping live ranges into registers which alias.	// overlapping live ranges into registers which alias.
	class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> {	class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> {
	let SubRegs = subregs;	let SubRegs = subregs;

	skipping to change at line 197	skipping to change at line 207
	// (shl GPR, 4) - Remove the first N elements.	// (shl GPR, 4) - Remove the first N elements.
	//	//
	// (trunc GPR, 4) - Truncate after the first N elements.	// (trunc GPR, 4) - Truncate after the first N elements.
	//	//
	// (rotl GPR, 1) - Rotate N places to the left.	// (rotl GPR, 1) - Rotate N places to the left.
	//	//
	// (rotr GPR, 1) - Rotate N places to the right.	// (rotr GPR, 1) - Rotate N places to the right.
	//	//
	// (decimate GPR, 2) - Pick every N'th element, starting with the first.	// (decimate GPR, 2) - Pick every N'th element, starting with the first.
	//	//

		// (interleave A, B, ...) - Interleave the elements from each argument list
		.
		//
	// All of these operators work on ordered sets, not lists. That means	// All of these operators work on ordered sets, not lists. That means
	// duplicates are removed from sub-expressions.	// duplicates are removed from sub-expressions.

	// Set operators. The rest is defined in TargetSelectionDAG.td.	// Set operators. The rest is defined in TargetSelectionDAG.td.
	def sequence;	def sequence;
	def decimate;	def decimate;

		def interleave;

	// RegisterTuples - Automatically generate super-registers by forming tuple s of	// RegisterTuples - Automatically generate super-registers by forming tuple s of
	// sub-registers. This is useful for modeling register sequence constraints	// sub-registers. This is useful for modeling register sequence constraints
	// with pseudo-registers that are larger than the architectural registers.	// with pseudo-registers that are larger than the architectural registers.
	//	//
	// The sub-register lists are zipped together:	// The sub-register lists are zipped together:
	//	//
	// def EvenOdd : RegisterTuples<[sube, subo], [(add R0, R2), (add R1, R3) ]>;	// def EvenOdd : RegisterTuples<[sube, subo], [(add R0, R2), (add R1, R3) ]>;
	//	//
	// Generates the same registers as:	// Generates the same registers as:

	skipping to change at line 358	skipping to change at line 371
	bit neverHasSideEffects = 0;	bit neverHasSideEffects = 0;

	// Is this instruction a "real" instruction (with a distinct machine	// Is this instruction a "real" instruction (with a distinct machine
	// encoding), or is it a pseudo instruction used for codegen modeling	// encoding), or is it a pseudo instruction used for codegen modeling
	// purposes.	// purposes.
	// FIXME: For now this is distinct from isPseudo, above, as code-gen-only	// FIXME: For now this is distinct from isPseudo, above, as code-gen-only
	// instructions can (and often do) still have encoding information	// instructions can (and often do) still have encoding information
	// associated with them. Once we've migrated all of them over to true	// associated with them. Once we've migrated all of them over to true
	// pseudo-instructions that are lowered to real instructions prior to	// pseudo-instructions that are lowered to real instructions prior to
	// the printer/emitter, we can remove this attribute and just use isPseud o.	// the printer/emitter, we can remove this attribute and just use isPseud o.

		//
		// The intended use is:
		// isPseudo: Does not have encoding information and should be expanded,
		// at the latest, during lowering to MCInst.
		//
		// isCodeGenOnly: Does have encoding information and can go through to th
		e
		// CodeEmitter unchanged, but duplicates a canonical instruction
		// definition's encoding and should be ignored when constructing the
		// assembler match tables.
	bit isCodeGenOnly = 0;	bit isCodeGenOnly = 0;

	// Is this instruction a pseudo instruction for use by the assembler pars er.	// Is this instruction a pseudo instruction for use by the assembler pars er.
	bit isAsmParserOnly = 0;	bit isAsmParserOnly = 0;

	InstrItinClass Itinerary = NoItinerary;// Execution steps used for schedu ling.	InstrItinClass Itinerary = NoItinerary;// Execution steps used for schedu ling.

	string Constraints = ""; // OperandConstraint, e.g. $src = $dst.	string Constraints = ""; // OperandConstraint, e.g. $src = $dst.

	/// DisableEncoding - List of operand names (e.g. "$op1,$op2") that shoul d not	/// DisableEncoding - List of operand names (e.g. "$op1,$op2") that shoul d not

	skipping to change at line 416	skipping to change at line 438
	/// "!ModeThumb" is translated to "(Bits & ModeThumb) == 0".	/// "!ModeThumb" is translated to "(Bits & ModeThumb) == 0".
	/// It can also list multiple features separated by ",".	/// It can also list multiple features separated by ",".
	/// e.g. "ModeThumb,FeatureThumb2" is translated to	/// e.g. "ModeThumb,FeatureThumb2" is translated to
	/// "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0".	/// "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0".
	string AssemblerCondString = "";	string AssemblerCondString = "";
	}	}

	/// NoHonorSignDependentRounding - This predicate is true if support for	/// NoHonorSignDependentRounding - This predicate is true if support for
	/// sign-dependent-rounding is not enabled.	/// sign-dependent-rounding is not enabled.
	def NoHonorSignDependentRounding	def NoHonorSignDependentRounding

	: Predicate<"!HonorSignDependentRoundingFPMath()">;	: Predicate<"!TM.Options.HonorSignDependentRoundingFPMath()">;

	class Requires<list<Predicate> preds> {	class Requires<list<Predicate> preds> {
	list<Predicate> Predicates = preds;	list<Predicate> Predicates = preds;
	}	}

	/// ops definition - This is just a simple marker used to identify the oper and	/// ops definition - This is just a simple marker used to identify the oper and
	/// list for an instruction. outs and ins are identical both syntactically and	/// list for an instruction. outs and ins are identical both syntactically and
	/// semanticallyr; they are used to define def operands and use operands to	/// semanticallyr; they are used to define def operands and use operands to
	/// improve readibility. This should be used like this:	/// improve readibility. This should be used like this:
	/// (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar.	/// (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar.

	skipping to change at line 678	skipping to change at line 700
	let neverHasSideEffects = 1;	let neverHasSideEffects = 1;
	let isAsCheapAsAMove = 1;	let isAsCheapAsAMove = 1;
	}	}
	def COPY : Instruction {	def COPY : Instruction {
	let OutOperandList = (outs unknown:$dst);	let OutOperandList = (outs unknown:$dst);
	let InOperandList = (ins unknown:$src);	let InOperandList = (ins unknown:$src);
	let AsmString = "";	let AsmString = "";
	let neverHasSideEffects = 1;	let neverHasSideEffects = 1;
	let isAsCheapAsAMove = 1;	let isAsCheapAsAMove = 1;
	}	}

		def BUNDLE : Instruction {
		let OutOperandList = (outs);
		let InOperandList = (ins variable_ops);
		let AsmString = "BUNDLE";
		}
	}	}

	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	// AsmParser - This class can be implemented by targets that wish to implem ent	// AsmParser - This class can be implemented by targets that wish to implem ent
	// .s file parsing.	// .s file parsing.
	//	//
	// Subtargets can have multiple different assembly parsers (e.g. AT&T vs In tel	// Subtargets can have multiple different assembly parsers (e.g. AT&T vs In tel
	// syntax on X86 for example).	// syntax on X86 for example).
	//	//
	class AsmParser {	class AsmParser {
	// AsmParserClassName - This specifies the suffix to use for the asmparse r	// AsmParserClassName - This specifies the suffix to use for the asmparse r
	// class. Generated AsmParser classes are always prefixed with the targe t	// class. Generated AsmParser classes are always prefixed with the targe t
	// name.	// name.
	string AsmParserClassName = "AsmParser";	string AsmParserClassName = "AsmParser";

	// AsmParserInstCleanup - If non-empty, this is the name of a custom memb er	// AsmParserInstCleanup - If non-empty, this is the name of a custom memb er
	// function of the AsmParser class to call on every matched instruction.	// function of the AsmParser class to call on every matched instruction.
	// This can be used to perform target specific instruction post-processin g.	// This can be used to perform target specific instruction post-processin g.
	string AsmParserInstCleanup = "";	string AsmParserInstCleanup = "";

		}
		def DefaultAsmParser : AsmParser;


		//===----------------------------------------------------------------------
		===//
		// AsmParserVariant - Subtargets can have multiple different assembly parse
		rs
		// (e.g. AT&T vs Intel syntax on X86 for example). This class can be
		// implemented by targets to describe such variants.
		//
		class AsmParserVariant {
	// Variant - AsmParsers can be of multiple different variants. Variants are	// Variant - AsmParsers can be of multiple different variants. Variants are
	// used to support targets that need to parser multiple formats for the	// used to support targets that need to parser multiple formats for the
	// assembly language.	// assembly language.
	int Variant = 0;	int Variant = 0;

	// CommentDelimiter - If given, the delimiter string used to recognize	// CommentDelimiter - If given, the delimiter string used to recognize
	// comments which are hard coded in the .td assembler strings for individ ual	// comments which are hard coded in the .td assembler strings for individ ual
	// instructions.	// instructions.
	string CommentDelimiter = "";	string CommentDelimiter = "";

	// RegisterPrefix - If given, the token prefix which indicates a register	// RegisterPrefix - If given, the token prefix which indicates a register
	// token. This is used by the matcher to automatically recognize hard cod ed	// token. This is used by the matcher to automatically recognize hard cod ed
	// register tokens as constrained registers, instead of tokens, for the	// register tokens as constrained registers, instead of tokens, for the
	// purposes of matching.	// purposes of matching.
	string RegisterPrefix = "";	string RegisterPrefix = "";
	}	}

	def DefaultAsmParser : AsmParser;	def DefaultAsmParserVariant : AsmParserVariant;

	/// AssemblerPredicate - This is a Predicate that can be used when the asse mbler	/// AssemblerPredicate - This is a Predicate that can be used when the asse mbler
	/// matches instructions and aliases.	/// matches instructions and aliases.
	class AssemblerPredicate<string cond> {	class AssemblerPredicate<string cond> {
	bit AssemblerMatcherPredicate = 1;	bit AssemblerMatcherPredicate = 1;
	string AssemblerCondString = cond;	string AssemblerCondString = cond;
	}	}


		/// TokenAlias - This class allows targets to define assembler token
		/// operand aliases. That is, a token literal operand which is equivalent
		/// to another, canonical, token literal. For example, ARM allows:
		/// vmov.u32 s4, #0 -> vmov.i32, #0
		/// 'u32' is a more specific designator for the 32-bit integer type specifi
		er
		/// and is legal for any instruction which accepts 'i32' as a datatype suff
		ix.
		/// def : TokenAlias<".u32", ".i32">;
		///
		/// This works by marking the match class of 'From' as a subclass of the
		/// match class of 'To'.
		class TokenAlias<string From, string To> {
		string FromToken = From;
		string ToToken = To;
		}

	/// MnemonicAlias - This class allows targets to define assembler mnemonic	/// MnemonicAlias - This class allows targets to define assembler mnemonic
	/// aliases. This should be used when all forms of one mnemonic are accept ed	/// aliases. This should be used when all forms of one mnemonic are accept ed
	/// with a different mnemonic. For example, X86 allows:	/// with a different mnemonic. For example, X86 allows:
	/// sal %al, 1 -> shl %al, 1	/// sal %al, 1 -> shl %al, 1
	/// sal %ax, %cl -> shl %ax, %cl	/// sal %ax, %cl -> shl %ax, %cl
	/// sal %eax, %cl -> shl %eax, %cl	/// sal %eax, %cl -> shl %eax, %cl
	/// etc. Though "sal" is accepted with many forms, all of them are directl y	/// etc. Though "sal" is accepted with many forms, all of them are directl y
	/// translated to a shl, so it can be handled with (in the case of X86, it	/// translated to a shl, so it can be handled with (in the case of X86, it
	/// actually has one for each suffix as well):	/// actually has one for each suffix as well):
	/// def : MnemonicAlias<"sal", "shl">;	/// def : MnemonicAlias<"sal", "shl">;

	skipping to change at line 808	skipping to change at line 858
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	// Target - This class contains the "global" target information	// Target - This class contains the "global" target information
	//	//
	class Target {	class Target {
	// InstructionSet - Instruction set description for this target.	// InstructionSet - Instruction set description for this target.
	InstrInfo InstructionSet;	InstrInfo InstructionSet;

	// AssemblyParsers - The AsmParser instances available for this target.	// AssemblyParsers - The AsmParser instances available for this target.
	list<AsmParser> AssemblyParsers = [DefaultAsmParser];	list<AsmParser> AssemblyParsers = [DefaultAsmParser];


		/// AssemblyParserVariants - The AsmParserVariant instances available for
		/// this target.
		list<AsmParserVariant> AssemblyParserVariants = [DefaultAsmParserVariant]
		;

	// AssemblyWriters - The AsmWriter instances available for this target.	// AssemblyWriters - The AsmWriter instances available for this target.
	list<AsmWriter> AssemblyWriters = [DefaultAsmWriter];	list<AsmWriter> AssemblyWriters = [DefaultAsmWriter];
	}	}

	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	// SubtargetFeature - A characteristic of the chip set.	// SubtargetFeature - A characteristic of the chip set.
	//	//
	class SubtargetFeature<string n, string a, string v, string d,	class SubtargetFeature<string n, string a, string v, string d,
	list<SubtargetFeature> i = []> {	list<SubtargetFeature> i = []> {
	// Name - Feature name. Used by command line (-mattr=) to determine the	// Name - Feature name. Used by command line (-mattr=) to determine the

End of changes. 13 change blocks.
	3 lines changed or deleted	67 lines changed or added

	TargetCallingConv.h	TargetCallingConv.h

	skipping to change at line 17	skipping to change at line 17
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	//	//
	// This file defines types for working with calling-convention information.	// This file defines types for working with calling-convention information.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_TARGET_TARGETCALLINGCONV_H	#ifndef LLVM_TARGET_TARGETCALLINGCONV_H
	#define LLVM_TARGET_TARGETCALLINGCONV_H	#define LLVM_TARGET_TARGETCALLINGCONV_H


		#include "llvm/Support/DataTypes.h"
		#include "llvm/Support/MathExtras.h"
		#include <string>

	namespace llvm {	namespace llvm {

	namespace ISD {	namespace ISD {
	struct ArgFlagsTy {	struct ArgFlagsTy {
	private:	private:
	static const uint64_t NoFlagSet = 0ULL;	static const uint64_t NoFlagSet = 0ULL;
	static const uint64_t ZExt = 1ULL<<0; ///< Zero extended	static const uint64_t ZExt = 1ULL<<0; ///< Zero extended
	static const uint64_t ZExtOffs = 0;	static const uint64_t ZExtOffs = 0;
	static const uint64_t SExt = 1ULL<<1; ///< Sign extended	static const uint64_t SExt = 1ULL<<1; ///< Sign extended
	static const uint64_t SExtOffs = 1;	static const uint64_t SExtOffs = 1;

End of changes. 1 change blocks.
	0 lines changed or deleted	4 lines changed or added

	TargetCallingConv.td	TargetCallingConv.td

	skipping to change at line 136	skipping to change at line 136
	/// is successful if the specified CC matches.	/// is successful if the specified CC matches.
	class CCDelegateTo<CallingConv cc> : CCAction {	class CCDelegateTo<CallingConv cc> : CCAction {
	CallingConv CC = cc;	CallingConv CC = cc;
	}	}

	/// CallingConv - An instance of this is used to define each calling conven tion	/// CallingConv - An instance of this is used to define each calling conven tion
	/// that the target supports.	/// that the target supports.
	class CallingConv<list<CCAction> actions> {	class CallingConv<list<CCAction> actions> {
	list<CCAction> Actions = actions;	list<CCAction> Actions = actions;
	}	}


		/// CalleeSavedRegs - A list of callee saved registers for a given calling
		/// convention. The order of registers is used by PrologEpilogInsertion wh
		en
		/// allocation stack slots for saved registers.
		///
		/// For each CalleeSavedRegs def, TableGen will emit a FOO_SaveList array f
		or
		/// returning from getCalleeSavedRegs(), and a FOO_RegMask bit mask suitabl
		e for
		/// returning from getCallPreservedMask().
		class CalleeSavedRegs<dag saves> {
		dag SaveList = saves;
		}

End of changes. 1 change blocks.
	0 lines changed or deleted	0 lines changed or added

	TargetData.h	TargetData.h

	skipping to change at line 115	skipping to change at line 115
	unsigned getAlignment(Type *Ty, bool abi_or_pref) const;	unsigned getAlignment(Type *Ty, bool abi_or_pref) const;

	/// Valid alignment predicate.	/// Valid alignment predicate.
	///	///
	/// Predicate that tests a TargetAlignElem reference returned by get() ag ainst	/// Predicate that tests a TargetAlignElem reference returned by get() ag ainst
	/// InvalidAlignmentElem.	/// InvalidAlignmentElem.
	bool validAlignment(const TargetAlignElem &align) const {	bool validAlignment(const TargetAlignElem &align) const {
	return &align != &InvalidAlignmentElem;	return &align != &InvalidAlignmentElem;
	}	}


		/// Initialise a TargetData object with default values, ensure that the
		/// target data pass is registered.
		void init();

	public:	public:
	/// Default ctor.	/// Default ctor.
	///	///
	/// @note This has to exist, because this is a pass, but it should never be	/// @note This has to exist, because this is a pass, but it should never be
	/// used.	/// used.
	TargetData();	TargetData();

	/// Constructs a TargetData from a specification string. See init().	/// Constructs a TargetData from a specification string. See init().
	explicit TargetData(StringRef TargetDescription)	explicit TargetData(StringRef TargetDescription)
	: ImmutablePass(ID) {	: ImmutablePass(ID) {

	init(TargetDescription);	std::string errMsg = parseSpecifier(TargetDescription, this);
		assert(errMsg == "" && "Invalid target data layout string.");
		(void)errMsg;
	}	}


		/// Parses a target data specification string. Returns an error message
		/// if the string is malformed, or the empty string on success. Optionall
		y
		/// initialises a TargetData object if passed a non-null pointer.
		static std::string parseSpecifier(StringRef TargetDescription, TargetData
		* td = 0);

	/// Initialize target data from properties stored in the module.	/// Initialize target data from properties stored in the module.
	explicit TargetData(const Module *M);	explicit TargetData(const Module *M);

	TargetData(const TargetData &TD) :	TargetData(const TargetData &TD) :
	ImmutablePass(ID),	ImmutablePass(ID),
	LittleEndian(TD.isLittleEndian()),	LittleEndian(TD.isLittleEndian()),
	PointerMemSize(TD.PointerMemSize),	PointerMemSize(TD.PointerMemSize),
	PointerABIAlign(TD.PointerABIAlign),	PointerABIAlign(TD.PointerABIAlign),
	PointerPrefAlign(TD.PointerPrefAlign),	PointerPrefAlign(TD.PointerPrefAlign),
	LegalIntWidths(TD.LegalIntWidths),	LegalIntWidths(TD.LegalIntWidths),
	Alignments(TD.Alignments),	Alignments(TD.Alignments),
	LayoutMap(0)	LayoutMap(0)
	{ }	{ }

	~TargetData(); // Not virtual, do not subclass this class	~TargetData(); // Not virtual, do not subclass this class


	//! Parse a target data layout string and initialize TargetData alignment
	s.
	void init(StringRef TargetDescription);

	/// Target endianness...	/// Target endianness...
	bool isLittleEndian() const { return LittleEndian; }	bool isLittleEndian() const { return LittleEndian; }
	bool isBigEndian() const { return !LittleEndian; }	bool isBigEndian() const { return !LittleEndian; }

	/// getStringRepresentation - Return the string representation of the	/// getStringRepresentation - Return the string representation of the
	/// TargetData. This representation is in the same format accepted by th e	/// TargetData. This representation is in the same format accepted by th e
	/// string constructor above.	/// string constructor above.
	std::string getStringRepresentation() const;	std::string getStringRepresentation() const;

	/// isLegalInteger - This function returns true if the specified type is	/// isLegalInteger - This function returns true if the specified type is

End of changes. 4 change blocks.
	5 lines changed or deleted	14 lines changed or added

	TargetELFWriterInfo.h	TargetELFWriterInfo.h

	skipping to change at line 18	skipping to change at line 18
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	//	//
	// This file defines the TargetELFWriterInfo class.	// This file defines the TargetELFWriterInfo class.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_TARGET_TARGETELFWRITERINFO_H	#ifndef LLVM_TARGET_TARGETELFWRITERINFO_H
	#define LLVM_TARGET_TARGETELFWRITERINFO_H	#define LLVM_TARGET_TARGETELFWRITERINFO_H

	namespace llvm {	namespace llvm {

	class Function;
	class TargetData;
	class TargetMachine;

	//===-------------------------------------------------------------------- ===//	//===-------------------------------------------------------------------- ===//
	// TargetELFWriterInfo	// TargetELFWriterInfo
	//===-------------------------------------------------------------------- ===//	//===-------------------------------------------------------------------- ===//

	class TargetELFWriterInfo {	class TargetELFWriterInfo {
	protected:	protected:
	// EMachine - This field is the target specific value to emit as the	// EMachine - This field is the target specific value to emit as the
	// e_machine member of the ELF header.	// e_machine member of the ELF header.
	unsigned short EMachine;	unsigned short EMachine;

End of changes. 1 change blocks.
	3 lines changed or deleted	0 lines changed or added

	TargetFrameLowering.h	TargetFrameLowering.h

	skipping to change at line 18	skipping to change at line 18
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	//	//
	// Interface to describe the layout of a stack frame on the target machine.	// Interface to describe the layout of a stack frame on the target machine.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_TARGET_TARGETFRAMELOWERING_H	#ifndef LLVM_TARGET_TARGETFRAMELOWERING_H
	#define LLVM_TARGET_TARGETFRAMELOWERING_H	#define LLVM_TARGET_TARGETFRAMELOWERING_H

	#include "llvm/CodeGen/MachineBasicBlock.h"	#include "llvm/CodeGen/MachineBasicBlock.h"

	#include "llvm/MC/MCDwarf.h"
	#include "llvm/ADT/ArrayRef.h"

	#include <utility>	#include <utility>
	#include <vector>	#include <vector>

	namespace llvm {	namespace llvm {
	class CalleeSavedInfo;	class CalleeSavedInfo;
	class MachineFunction;	class MachineFunction;

	class MachineBasicBlock;
	class MachineMove;
	class RegScavenger;	class RegScavenger;

	/// Information about stack frame layout on the target. It holds the direc tion	/// Information about stack frame layout on the target. It holds the direc tion
	/// of stack growth, the known stack alignment on entry to each function, a nd	/// of stack growth, the known stack alignment on entry to each function, a nd
	/// the offset to the locals area.	/// the offset to the locals area.
	///	///
	/// The offset to the local area is the offset from the stack pointer on	/// The offset to the local area is the offset from the stack pointer on
	/// function entry to the first location where function data (local variabl es,	/// function entry to the first location where function data (local variabl es,
	/// spill locations) can be stored.	/// spill locations) can be stored.
	class TargetFrameLowering {	class TargetFrameLowering {

End of changes. 2 change blocks.
	4 lines changed or deleted	0 lines changed or added

	TargetInstrInfo.h	TargetInstrInfo.h

	skipping to change at line 18	skipping to change at line 18
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	//	//
	// This file describes the target machine instruction set to the code gener ator.	// This file describes the target machine instruction set to the code gener ator.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_TARGET_TARGETINSTRINFO_H	#ifndef LLVM_TARGET_TARGETINSTRINFO_H
	#define LLVM_TARGET_TARGETINSTRINFO_H	#define LLVM_TARGET_TARGETINSTRINFO_H

	#include "llvm/MC/MCInstrInfo.h"	#include "llvm/MC/MCInstrInfo.h"

		#include "llvm/CodeGen/DFAPacketizer.h"
	#include "llvm/CodeGen/MachineFunction.h"	#include "llvm/CodeGen/MachineFunction.h"

	namespace llvm {	namespace llvm {

	class InstrItineraryData;	class InstrItineraryData;
	class LiveVariables;	class LiveVariables;
	class MCAsmInfo;	class MCAsmInfo;
	class MachineMemOperand;	class MachineMemOperand;
	class MachineRegisterInfo;	class MachineRegisterInfo;
	class MDNode;	class MDNode;

	skipping to change at line 280	skipping to change at line 281
	MachineBasicBlock *&FBB,	MachineBasicBlock *&FBB,
	SmallVectorImpl<MachineOperand> &Cond,	SmallVectorImpl<MachineOperand> &Cond,
	bool AllowModify = false) const {	bool AllowModify = false) const {
	return true;	return true;
	}	}

	/// RemoveBranch - Remove the branching code at the end of the specific M BB.	/// RemoveBranch - Remove the branching code at the end of the specific M BB.
	/// This is only invoked in cases where AnalyzeBranch returns success. It	/// This is only invoked in cases where AnalyzeBranch returns success. It
	/// returns the number of instructions that were removed.	/// returns the number of instructions that were removed.
	virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const {	virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const {

	assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!");	llvm_unreachable("Target didn't implement TargetInstrInfo::RemoveBranch
	return 0;	!");
	}	}

	/// InsertBranch - Insert branch code into the end of the specified	/// InsertBranch - Insert branch code into the end of the specified
	/// MachineBasicBlock. The operands to this method are the same as those	/// MachineBasicBlock. The operands to this method are the same as those
	/// returned by AnalyzeBranch. This is only invoked in cases where	/// returned by AnalyzeBranch. This is only invoked in cases where
	/// AnalyzeBranch returns success. It returns the number of instructions	/// AnalyzeBranch returns success. It returns the number of instructions
	/// inserted.	/// inserted.
	///	///
	/// It is also invoked by tail merging to add unconditional branches in	/// It is also invoked by tail merging to add unconditional branches in
	/// cases where AnalyzeBranch doesn't apply because there was no original	/// cases where AnalyzeBranch doesn't apply because there was no original
	/// branch to analyze. At least this much must be implemented, else tail	/// branch to analyze. At least this much must be implemented, else tail
	/// merging needs to be disabled.	/// merging needs to be disabled.
	virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock * TBB,	virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock * TBB,
	MachineBasicBlock *FBB,	MachineBasicBlock *FBB,
	const SmallVectorImpl<MachineOperand> &Cond ,	const SmallVectorImpl<MachineOperand> &Cond ,
	DebugLoc DL) const {	DebugLoc DL) const {

	assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!");	llvm_unreachable("Target didn't implement TargetInstrInfo::InsertBranch
	return 0;	!");
	}	}

	/// ReplaceTailWithBranchTo - Delete the instruction OldInst and everythi ng	/// ReplaceTailWithBranchTo - Delete the instruction OldInst and everythi ng
	/// after it, replacing it with an unconditional branch to NewDest. This is	/// after it, replacing it with an unconditional branch to NewDest. This is
	/// used by the tail merging pass.	/// used by the tail merging pass.
	virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,	virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
	MachineBasicBlock *NewDest) const = 0;	MachineBasicBlock *NewDest) const = 0;

	/// isLegalToSplitMBBAt - Return true if it's legal to split the given ba sic	/// isLegalToSplitMBBAt - Return true if it's legal to split the given ba sic
	/// block at the specified instruction (i.e. instruction would be the sta rt	/// block at the specified instruction (i.e. instruction would be the sta rt

	skipping to change at line 355	skipping to change at line 354
	/// instruction latencies in the specified MBB to enable if-conversion.	/// instruction latencies in the specified MBB to enable if-conversion.
	/// The probability of the instructions being executed is given by	/// The probability of the instructions being executed is given by
	/// Probability, and Confidence is a measure of our confidence that it	/// Probability, and Confidence is a measure of our confidence that it
	/// will be properly predicted.	/// will be properly predicted.
	virtual bool	virtual bool
	isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,	isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
	const BranchProbability &Probability) const {	const BranchProbability &Probability) const {
	return false;	return false;
	}	}


		/// isProfitableToUnpredicate - Return true if it's profitable to unpredi
		cate
		/// one side of a 'diamond', i.e. two sides of if-else predicated on mutu
		ally
		/// exclusive predicates.
		/// e.g.
		/// subeq r0, r1, #1
		/// addne r0, r1, #1
		/// =>
		/// sub r0, r1, #1
		/// addne r0, r1, #1
		///
		/// This may be profitable is conditional instructions are always execute
		d.
		virtual bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
		MachineBasicBlock &FMBB) const {
		return false;
		}

	/// copyPhysReg - Emit instructions to copy a pair of physical registers.	/// copyPhysReg - Emit instructions to copy a pair of physical registers.
	virtual void copyPhysReg(MachineBasicBlock &MBB,	virtual void copyPhysReg(MachineBasicBlock &MBB,
	MachineBasicBlock::iterator MI, DebugLoc DL,	MachineBasicBlock::iterator MI, DebugLoc DL,
	unsigned DestReg, unsigned SrcReg,	unsigned DestReg, unsigned SrcReg,
	bool KillSrc) const {	bool KillSrc) const {

	assert(0 && "Target didn't implement TargetInstrInfo::copyPhysReg!");	llvm_unreachable("Target didn't implement TargetInstrInfo::copyPhysReg! ");
	}	}

	/// storeRegToStackSlot - Store the specified register of the given regis ter	/// storeRegToStackSlot - Store the specified register of the given regis ter
	/// class to the specified stack frame index. The store instruction is to be	/// class to the specified stack frame index. The store instruction is to be
	/// added to the given machine basic block before the specified machine	/// added to the given machine basic block before the specified machine
	/// instruction. If isKill is true, the register operand is the last use and	/// instruction. If isKill is true, the register operand is the last use and
	/// must be marked kill.	/// must be marked kill.
	virtual void storeRegToStackSlot(MachineBasicBlock &MBB,	virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
	MachineBasicBlock::iterator MI,	MachineBasicBlock::iterator MI,
	unsigned SrcReg, bool isKill, int FrameI ndex,	unsigned SrcReg, bool isKill, int FrameI ndex,
	const TargetRegisterClass *RC,	const TargetRegisterClass *RC,
	const TargetRegisterInfo *TRI) const {	const TargetRegisterInfo *TRI) const {

	assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot	llvm_unreachable("Target didn't implement "
	!");	"TargetInstrInfo::storeRegToStackSlot!");
	}	}

	/// loadRegFromStackSlot - Load the specified register of the given regis ter	/// loadRegFromStackSlot - Load the specified register of the given regis ter
	/// class from the specified stack frame index. The load instruction is t o be	/// class from the specified stack frame index. The load instruction is t o be
	/// added to the given machine basic block before the specified machine	/// added to the given machine basic block before the specified machine
	/// instruction.	/// instruction.
	virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,	virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
	MachineBasicBlock::iterator MI,	MachineBasicBlock::iterator MI,
	unsigned DestReg, int FrameIndex,	unsigned DestReg, int FrameIndex,
	const TargetRegisterClass *RC,	const TargetRegisterClass *RC,
	const TargetRegisterInfo *TRI) const {	const TargetRegisterInfo *TRI) const {

	assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlo	llvm_unreachable("Target didn't implement "
	t!");	"TargetInstrInfo::loadRegFromStackSlot!");
	}	}

	/// expandPostRAPseudo - This function is called for all pseudo instructi ons	/// expandPostRAPseudo - This function is called for all pseudo instructi ons
	/// that remain after register allocation. Many pseudo instructions are	/// that remain after register allocation. Many pseudo instructions are
	/// created to help register allocation. This is the place to convert the m	/// created to help register allocation. This is the place to convert the m
	/// into real instructions. The target can edit MI in place, or it can in sert	/// into real instructions. The target can edit MI in place, or it can in sert
	/// new instructions and erase MI. The function should return true if	/// new instructions and erase MI. The function should return true if
	/// anything was changed.	/// anything was changed.
	virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const {	virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
	return false;	return false;

	skipping to change at line 535	skipping to change at line 552
	}	}

	/// isPredicated - Returns true if the instruction is already predicated.	/// isPredicated - Returns true if the instruction is already predicated.
	///	///
	virtual bool isPredicated(const MachineInstr *MI) const {	virtual bool isPredicated(const MachineInstr *MI) const {
	return false;	return false;
	}	}

	/// isUnpredicatedTerminator - Returns true if the instruction is a	/// isUnpredicatedTerminator - Returns true if the instruction is a
	/// terminator instruction that has not been predicated.	/// terminator instruction that has not been predicated.

	virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const;	virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const = 0;

	/// PredicateInstruction - Convert the instruction into a predicated	/// PredicateInstruction - Convert the instruction into a predicated
	/// instruction. It returns true if the operation was successful.	/// instruction. It returns true if the operation was successful.
	virtual	virtual
	bool PredicateInstruction(MachineInstr *MI,	bool PredicateInstruction(MachineInstr *MI,
	const SmallVectorImpl<MachineOperand> &Pred) const = 0;	const SmallVectorImpl<MachineOperand> &Pred) const = 0;

	/// SubsumesPredicate - Returns true if the first specified predicate	/// SubsumesPredicate - Returns true if the first specified predicate
	/// subsumes the second, e.g. GE subsumes GT.	/// subsumes the second, e.g. GE subsumes GT.
	virtual	virtual

	skipping to change at line 646	skipping to change at line 663
	/// pair of def and use.	/// pair of def and use.
	/// In most cases, the static scheduling itinerary was enough to determin e the	/// In most cases, the static scheduling itinerary was enough to determin e the
	/// operand latency. But it may not be possible for instructions with var iable	/// operand latency. But it may not be possible for instructions with var iable
	/// number of defs / uses.	/// number of defs / uses.
	virtual int getOperandLatency(const InstrItineraryData *ItinData,	virtual int getOperandLatency(const InstrItineraryData *ItinData,
	const MachineInstr *DefMI, unsigned DefIdx,	const MachineInstr *DefMI, unsigned DefIdx,
	const MachineInstr *UseMI, unsigned UseIdx) c onst;	const MachineInstr *UseMI, unsigned UseIdx) c onst;

	virtual int getOperandLatency(const InstrItineraryData *ItinData,	virtual int getOperandLatency(const InstrItineraryData *ItinData,
	SDNode *DefNode, unsigned DefIdx,	SDNode *DefNode, unsigned DefIdx,

	SDNode *UseNode, unsigned UseIdx) const;	SDNode *UseNode, unsigned UseIdx) const = 0
		;

		/// getOutputLatency - Compute and return the output dependency latency o
		f a
		/// a given pair of defs which both target the same register. This is usu
		ally
		/// one.
		virtual unsigned getOutputLatency(const InstrItineraryData *ItinData,
		const MachineInstr *DefMI, unsigned Def
		Idx,
		const MachineInstr *DepMI) const {
		return 1;
		}

	/// getInstrLatency - Compute the instruction latency of a given instruct ion.	/// getInstrLatency - Compute the instruction latency of a given instruct ion.
	/// If the instruction has higher cost when predicated, it's returned via	/// If the instruction has higher cost when predicated, it's returned via
	/// PredCost.	/// PredCost.
	virtual int getInstrLatency(const InstrItineraryData *ItinData,	virtual int getInstrLatency(const InstrItineraryData *ItinData,
	const MachineInstr *MI,	const MachineInstr *MI,
	unsigned *PredCost = 0) const;	unsigned *PredCost = 0) const;

	virtual int getInstrLatency(const InstrItineraryData *ItinData,	virtual int getInstrLatency(const InstrItineraryData *ItinData,

	SDNode *Node) const;	SDNode *Node) const = 0;

	/// isHighLatencyDef - Return true if this opcode has high latency to its	/// isHighLatencyDef - Return true if this opcode has high latency to its
	/// result.	/// result.
	virtual bool isHighLatencyDef(int opc) const { return false; }	virtual bool isHighLatencyDef(int opc) const { return false; }

	/// hasHighOperandLatency - Compute operand latency between a def of 'Reg '	/// hasHighOperandLatency - Compute operand latency between a def of 'Reg '
	/// and an use in the current loop, return true if the target considered	/// and an use in the current loop, return true if the target considered
	/// it 'high'. This is used by optimization passes such as machine LICM t o	/// it 'high'. This is used by optimization passes such as machine LICM t o
	/// determine whether it makes sense to hoist an instruction out even in	/// determine whether it makes sense to hoist an instruction out even in
	/// high register pressure situation.	/// high register pressure situation.

	skipping to change at line 718	skipping to change at line 744
	return std::make_pair(0, 0);	return std::make_pair(0, 0);
	}	}

	/// setExecutionDomain - Change the opcode of MI to execute in Domain.	/// setExecutionDomain - Change the opcode of MI to execute in Domain.
	///	///
	/// The bit (1 << Domain) must be set in the mask returned from	/// The bit (1 << Domain) must be set in the mask returned from
	/// getExecutionDomain(MI).	/// getExecutionDomain(MI).
	///	///
	virtual void setExecutionDomain(MachineInstr *MI, unsigned Domain) const {}	virtual void setExecutionDomain(MachineInstr *MI, unsigned Domain) const {}


		/// getPartialRegUpdateClearance - Returns the preferred minimum clearanc
		e
		/// before an instruction with an unwanted partial register update.
		///
		/// Some instructions only write part of a register, and implicitly need
		to
		/// read the other parts of the register. This may cause unwanted stalls
		/// preventing otherwise unrelated instructions from executing in paralle
		l in
		/// an out-of-order CPU.
		///
		/// For example, the x86 instruction cvtsi2ss writes its result to bits
		/// [31:0] of the destination xmm register. Bits [127:32] are unaffected,
		so
		/// the instruction needs to wait for the old value of the register to be
		come
		/// available:
		///
		/// addps %xmm1, %xmm0
		/// movaps %xmm0, (%rax)
		/// cvtsi2ss %rbx, %xmm0
		///
		/// In the code above, the cvtsi2ss instruction needs to wait for the add
		ps
		/// instruction before it can issue, even though the high bits of %xmm0
		/// probably aren't needed.
		///
		/// This hook returns the preferred clearance before MI, measured in
		/// instructions. Other defs of MI's operand OpNum are avoided in the la
		st N
		/// instructions before MI. It should only return a positive value for
		/// unwanted dependencies. If the old bits of the defined register have
		/// useful values, or if MI is determined to otherwise read the dependenc
		y,
		/// the hook should return 0.
		///
		/// The unwanted dependency may be handled by:
		///
		/// 1. Allocating the same register for an MI def and use. That makes th
		e
		/// unwanted dependency identical to a required dependency.
		///
		/// 2. Allocating a register for the def that has no defs in the previous
		N
		/// instructions.
		///
		/// 3. Calling breakPartialRegDependency() with the same arguments. This
		/// allows the target to insert a dependency breaking instruction.
		///
		virtual unsigned
		getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,
		const TargetRegisterInfo *TRI) const {
		// The default implementation returns 0 for no partial register depende
		ncy.
		return 0;
		}

		/// breakPartialRegDependency - Insert a dependency-breaking instruction
		/// before MI to eliminate an unwanted dependency on OpNum.
		///
		/// If it wasn't possible to avoid a def in the last N instructions befor
		e MI
		/// (see getPartialRegUpdateClearance), this hook will be called to break
		the
		/// unwanted dependency.
		///
		/// On x86, an xorps instruction can be used as a dependency breaker:
		///
		/// addps %xmm1, %xmm0
		/// movaps %xmm0, (%rax)
		/// xorps %xmm0, %xmm0
		/// cvtsi2ss %rbx, %xmm0
		///
		/// An <imp-kill> operand should be added to MI if an instruction was
		/// inserted. This ties the instructions together in the post-ra schedul
		er.
		///
		virtual void
		breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum,
		const TargetRegisterInfo *TRI) const {}

		/// Create machine specific model for scheduling.
		virtual DFAPacketizer*
		CreateTargetScheduleState(const TargetMachine, const ScheduleDAG) con
		st {
		return NULL;
		}

	private:	private:
	int CallFrameSetupOpcode, CallFrameDestroyOpcode;	int CallFrameSetupOpcode, CallFrameDestroyOpcode;
	};	};

	/// TargetInstrInfoImpl - This is the default implementation of	/// TargetInstrInfoImpl - This is the default implementation of
	/// TargetInstrInfo, which just provides a couple of default implementation s	/// TargetInstrInfo, which just provides a couple of default implementation s
	/// for various methods. This separated out because it is implemented in	/// for various methods. This separated out because it is implemented in
	/// libcodegen, not in libtarget.	/// libcodegen, not in libtarget.
	class TargetInstrInfoImpl : public TargetInstrInfo {	class TargetInstrInfoImpl : public TargetInstrInfo {
	protected:	protected:

	skipping to change at line 746	skipping to change at line 845
	virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,	virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
	unsigned &SrcOpIdx2) const;	unsigned &SrcOpIdx2) const;
	virtual bool canFoldMemoryOperand(const MachineInstr *MI,	virtual bool canFoldMemoryOperand(const MachineInstr *MI,
	const SmallVectorImpl<unsigned> &Ops) c onst;	const SmallVectorImpl<unsigned> &Ops) c onst;
	virtual bool hasLoadFromStackSlot(const MachineInstr *MI,	virtual bool hasLoadFromStackSlot(const MachineInstr *MI,
	const MachineMemOperand *&MMO,	const MachineMemOperand *&MMO,
	int &FrameIndex) const;	int &FrameIndex) const;
	virtual bool hasStoreToStackSlot(const MachineInstr *MI,	virtual bool hasStoreToStackSlot(const MachineInstr *MI,
	const MachineMemOperand *&MMO,	const MachineMemOperand *&MMO,
	int &FrameIndex) const;	int &FrameIndex) const;

		virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const;
	virtual bool PredicateInstruction(MachineInstr *MI,	virtual bool PredicateInstruction(MachineInstr *MI,
	const SmallVectorImpl<MachineOperand> &Pred) co nst;	const SmallVectorImpl<MachineOperand> &Pred) co nst;
	virtual void reMaterialize(MachineBasicBlock &MBB,	virtual void reMaterialize(MachineBasicBlock &MBB,
	MachineBasicBlock::iterator MI,	MachineBasicBlock::iterator MI,
	unsigned DestReg, unsigned SubReg,	unsigned DestReg, unsigned SubReg,
	const MachineInstr *Orig,	const MachineInstr *Orig,
	const TargetRegisterInfo &TRI) const;	const TargetRegisterInfo &TRI) const;
	virtual MachineInstr duplicate(MachineInstr Orig,	virtual MachineInstr duplicate(MachineInstr Orig,
	MachineFunction &MF) const;	MachineFunction &MF) const;
	virtual bool produceSameValue(const MachineInstr *MI0,	virtual bool produceSameValue(const MachineInstr *MI0,
	const MachineInstr *MI1,	const MachineInstr *MI1,
	const MachineRegisterInfo *MRI) const;	const MachineRegisterInfo *MRI) const;
	virtual bool isSchedulingBoundary(const MachineInstr *MI,	virtual bool isSchedulingBoundary(const MachineInstr *MI,
	const MachineBasicBlock *MBB,	const MachineBasicBlock *MBB,
	const MachineFunction &MF) const;	const MachineFunction &MF) const;

		using TargetInstrInfo::getOperandLatency;
		virtual int getOperandLatency(const InstrItineraryData *ItinData,
		SDNode *DefNode, unsigned DefIdx,
		SDNode *UseNode, unsigned UseIdx) const;
		using TargetInstrInfo::getInstrLatency;
		virtual int getInstrLatency(const InstrItineraryData *ItinData,
		SDNode *Node) const;

	bool usePreRAHazardRecognizer() const;	bool usePreRAHazardRecognizer() const;

	virtual ScheduleHazardRecognizer *	virtual ScheduleHazardRecognizer *
	CreateTargetHazardRecognizer(const TargetMachine, const ScheduleDAG) co nst;	CreateTargetHazardRecognizer(const TargetMachine, const ScheduleDAG) co nst;

	virtual ScheduleHazardRecognizer *	virtual ScheduleHazardRecognizer *
	CreateTargetPostRAHazardRecognizer(const InstrItineraryData*,	CreateTargetPostRAHazardRecognizer(const InstrItineraryData*,
	const ScheduleDAG*) const;	const ScheduleDAG*) const;
	};	};

End of changes. 13 change blocks.
	12 lines changed or deleted	141 lines changed or added

	TargetLibraryInfo.h	TargetLibraryInfo.h

	skipping to change at line 14	skipping to change at line 14
	//	//
	// This file is distributed under the University of Illinois Open Source	// This file is distributed under the University of Illinois Open Source
	// License. See LICENSE.TXT for details.	// License. See LICENSE.TXT for details.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_TARGET_TARGETLIBRARYINFO_H	#ifndef LLVM_TARGET_TARGETLIBRARYINFO_H
	#define LLVM_TARGET_TARGETLIBRARYINFO_H	#define LLVM_TARGET_TARGETLIBRARYINFO_H

	#include "llvm/Pass.h"	#include "llvm/Pass.h"

		#include "llvm/ADT/DenseMap.h"

	namespace llvm {	namespace llvm {
	class Triple;	class Triple;

	namespace LibFunc {	namespace LibFunc {
	enum Func {	enum Func {

	/// void memset(void b, int c, size_t len);	/// double acos(double x);
	memset,	acos,
		/// long double acosl(long double x);
	// void memcpy(void s1, const void *s2, size_t n);	acosl,
		/// float acosf(float x);
		acosf,
		/// double asin(double x);
		asin,
		/// long double asinl(long double x);
		asinl,
		/// float asinf(float x);
		asinf,
		/// double atan(double x);
		atan,
		/// long double atanl(long double x);
		atanl,
		/// float atanf(float x);
		atanf,
		/// double atan2(double y, double x);
		atan2,
		/// long double atan2l(long double y, long double x);
		atan2l,
		/// float atan2f(float y, float x);
		atan2f,
		/// double ceil(double x);
		ceil,
		/// long double ceill(long double x);
		ceill,
		/// float ceilf(float x);
		ceilf,
		/// double copysign(double x, double y);
		copysign,
		/// float copysignf(float x, float y);
		copysignf,
		/// long double copysignl(long double x, long double y);
		copysignl,
		/// double cos(double x);
		cos,
		/// long double cosl(long double x);
		cosl,
		/// float cosf(float x);
		cosf,
		/// double cosh(double x);
		cosh,
		/// long double coshl(long double x);
		coshl,
		/// float coshf(float x);
		coshf,
		/// double exp(double x);
		exp,
		/// long double expl(long double x);
		expl,
		/// float expf(float x);
		expf,
		/// double exp2(double x);
		exp2,
		/// long double exp2l(long double x);
		exp2l,
		/// float exp2f(float x);
		exp2f,
		/// double expm1(double x);
		expm1,
		/// long double expm1l(long double x);
		expm1l,
		/// float expm1f(float x);
		expm1f,
		/// double fabs(double x);
		fabs,
		/// long double fabsl(long double x);
		fabsl,
		/// float fabsf(float x);
		fabsf,
		/// double floor(double x);
		floor,
		/// long double floorl(long double x);
		floorl,
		/// float floorf(float x);
		floorf,
		/// int fiprintf(FILE stream, const char format, ...);
		fiprintf,
		/// double fmod(double x, double y);
		fmod,
		/// long double fmodl(long double x, long double y);
		fmodl,
		/// float fmodf(float x, float y);
		fmodf,
		/// int fputs(const char s, FILE stream);
		fputs,
		/// size_t fwrite(const void *ptr, size_t size, size_t nitems,
		/// FILE *stream);
		fwrite,
		/// int iprintf(const char *format, ...);
		iprintf,
		/// double log(double x);
		log,
		/// long double logl(long double x);
		logl,
		/// float logf(float x);
		logf,
		/// double log2(double x);
		log2,
		/// double long double log2l(long double x);
		log2l,
		/// float log2f(float x);
		log2f,
		/// double log10(double x);
		log10,
		/// long double log10l(long double x);
		log10l,
		/// float log10f(float x);
		log10f,
		/// double log1p(double x);
		log1p,
		/// long double log1pl(long double x);
		log1pl,
		/// float log1pf(float x);
		log1pf,
		/// void memcpy(void s1, const void *s2, size_t n);
	memcpy,	memcpy,

		/// void memmove(void s1, const void *s2, size_t n);
	// void memmove(void s1, const void *s2, size_t n);
	memmove,	memmove,

		/// void memset(void b, int c, size_t len);
		memset,
	/// void memset_pattern16(void b, const void pattern16, size_t len) ;	/// void memset_pattern16(void b, const void pattern16, size_t len) ;
	memset_pattern16,	memset_pattern16,

		/// double nearbyint(double x);
	/// int iprintf(const char *format, ...);	nearbyint,
	iprintf,	/// float nearbyintf(float x);
		nearbyintf,
		/// long double nearbyintl(long double x);
		nearbyintl,
		/// double pow(double x, double y);
		pow,
		/// float powf(float x, float y);
		powf,
		/// long double powl(long double x, long double y);
		powl,
		/// double rint(double x);
		rint,
		/// float rintf(float x);
		rintf,
		/// long double rintl(long double x);
		rintl,
		/// double round(double x);
		round,
		/// float roundf(float x);
		roundf,
		/// long double roundl(long double x);
		roundl,
		/// double sin(double x);
		sin,
		/// long double sinl(long double x);
		sinl,
		/// float sinf(float x);
		sinf,
		/// double sinh(double x);
		sinh,
		/// long double sinhl(long double x);
		sinhl,
		/// float sinhf(float x);
		sinhf,
	/// int siprintf(char str, const char format, ...);	/// int siprintf(char str, const char format, ...);
	siprintf,	siprintf,

		/// double sqrt(double x);
	/// int fiprintf(FILE stream, const char format, ...);	sqrt,
	fiprintf,	/// long double sqrtl(long double x);
		sqrtl,
		/// float sqrtf(float x);
		sqrtf,
		/// double tan(double x);
		tan,
		/// long double tanl(long double x);
		tanl,
		/// float tanf(float x);
		tanf,
		/// double tanh(double x);
		tanh,
		/// long double tanhl(long double x);
		tanhl,
		/// float tanhf(float x);
		tanhf,
		/// double trunc(double x);
		trunc,
		/// float truncf(float x);
		truncf,
		/// long double truncl(long double x);
		truncl,
		/// int __cxa_atexit(void (f)(void ), void p, void d);
		cxa_atexit,
		/// void __cxa_guard_abort(guard_t *guard);
		/// guard_t is int64_t in Itanium ABI or int32_t on ARM eabi.
		cxa_guard_abort,
		/// int __cxa_guard_acquire(guard_t *guard);
		cxa_guard_acquire,
		/// void __cxa_guard_release(guard_t *guard);
		cxa_guard_release,

	NumLibFuncs	NumLibFuncs
	};	};
	}	}

	/// TargetLibraryInfo - This immutable pass captures information about what	/// TargetLibraryInfo - This immutable pass captures information about what
	/// library functions are available for the current target, and allows a	/// library functions are available for the current target, and allows a
	/// frontend to disable optimizations through -fno-builtin etc.	/// frontend to disable optimizations through -fno-builtin etc.
	class TargetLibraryInfo : public ImmutablePass {	class TargetLibraryInfo : public ImmutablePass {

	unsigned char AvailableArray[(LibFunc::NumLibFuncs+7)/8];	virtual void anchor();
		unsigned char AvailableArray[(LibFunc::NumLibFuncs+3)/4];
		llvm::DenseMap<unsigned, std::string> CustomNames;
		static const char* StandardNames[LibFunc::NumLibFuncs];

		enum AvailabilityState {
		StandardName = 3, // (memset to all ones)
		CustomName = 1,
		Unavailable = 0 // (memset to all zeros)
		};
		void setState(LibFunc::Func F, AvailabilityState State) {
		AvailableArray[F/4] &= ~(3 << 2*(F&3));
		AvailableArray[F/4] \|= State << 2*(F&3);
		}
		AvailabilityState getState(LibFunc::Func F) const {
		return static_cast<AvailabilityState>((AvailableArray[F/4] >> 2*(F&3))
		& 3);
		}

	public:	public:
	static char ID;	static char ID;
	TargetLibraryInfo();	TargetLibraryInfo();
	TargetLibraryInfo(const Triple &T);	TargetLibraryInfo(const Triple &T);
	explicit TargetLibraryInfo(const TargetLibraryInfo &TLI);	explicit TargetLibraryInfo(const TargetLibraryInfo &TLI);

	/// has - This function is used by optimizations that want to match on or form	/// has - This function is used by optimizations that want to match on or form
	/// a given library function.	/// a given library function.
	bool has(LibFunc::Func F) const {	bool has(LibFunc::Func F) const {

	return (AvailableArray[F/8] & (1 << (F&7))) != 0;	return getState(F) != Unavailable;
		}

		StringRef getName(LibFunc::Func F) const {
		AvailabilityState State = getState(F);
		if (State == Unavailable)
		return StringRef();
		if (State == StandardName)
		return StandardNames[F];
		assert(State == CustomName);
		return CustomNames.find(F)->second;
	}	}

	/// setUnavailable - this can be used by whatever sets up TargetLibraryIn fo to	/// setUnavailable - this can be used by whatever sets up TargetLibraryIn fo to
	/// ban use of specific library functions.	/// ban use of specific library functions.
	void setUnavailable(LibFunc::Func F) {	void setUnavailable(LibFunc::Func F) {

	AvailableArray[F/8] &= ~(1 << (F&7));	setState(F, Unavailable);
	}	}

	void setAvailable(LibFunc::Func F) {	void setAvailable(LibFunc::Func F) {

	AvailableArray[F/8] \|= 1 << (F&7);	setState(F, StandardName);
		}

		void setAvailableWithName(LibFunc::Func F, StringRef Name) {
		if (StandardNames[F] != Name) {
		setState(F, CustomName);
		CustomNames[F] = Name;
		assert(CustomNames.find(F) != CustomNames.end());
		} else {
		setState(F, StandardName);
		}
	}	}

	/// disableAllFunctions - This disables all builtins, which is used for	/// disableAllFunctions - This disables all builtins, which is used for
	/// options like -fno-builtin.	/// options like -fno-builtin.
	void disableAllFunctions();	void disableAllFunctions();
	};	};

	} // end namespace llvm	} // end namespace llvm

	#endif	#endif

End of changes. 10 change blocks.
	18 lines changed or deleted	233 lines changed or added

	TargetLowering.h	TargetLowering.h

	skipping to change at line 28	skipping to change at line 28
	// immediates.	// immediates.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_TARGET_TARGETLOWERING_H	#ifndef LLVM_TARGET_TARGETLOWERING_H
	#define LLVM_TARGET_TARGETLOWERING_H	#define LLVM_TARGET_TARGETLOWERING_H

	#include "llvm/CallingConv.h"	#include "llvm/CallingConv.h"
	#include "llvm/InlineAsm.h"	#include "llvm/InlineAsm.h"
	#include "llvm/Attributes.h"	#include "llvm/Attributes.h"

	#include "llvm/ADT/SmallPtrSet.h"
	#include "llvm/CodeGen/SelectionDAGNodes.h"	#include "llvm/CodeGen/SelectionDAGNodes.h"
	#include "llvm/CodeGen/RuntimeLibcalls.h"	#include "llvm/CodeGen/RuntimeLibcalls.h"
	#include "llvm/Support/DebugLoc.h"	#include "llvm/Support/DebugLoc.h"
	#include "llvm/Target/TargetCallingConv.h"	#include "llvm/Target/TargetCallingConv.h"
	#include "llvm/Target/TargetMachine.h"	#include "llvm/Target/TargetMachine.h"
	#include <climits>	#include <climits>
	#include <map>	#include <map>
	#include <vector>	#include <vector>

	namespace llvm {	namespace llvm {

	class AllocaInst;
	class APFloat;
	class CallInst;	class CallInst;
	class CCState;	class CCState;

	class Function;
	class FastISel;	class FastISel;
	class FunctionLoweringInfo;	class FunctionLoweringInfo;
	class ImmutableCallSite;	class ImmutableCallSite;

		class IntrinsicInst;
	class MachineBasicBlock;	class MachineBasicBlock;
	class MachineFunction;	class MachineFunction;

	class MachineFrameInfo;
	class MachineInstr;	class MachineInstr;
	class MachineJumpTableInfo;	class MachineJumpTableInfo;
	class MCContext;	class MCContext;
	class MCExpr;	class MCExpr;

	class SDNode;
	class SDValue;
	class SelectionDAG;
	template<typename T> class SmallVectorImpl;	template<typename T> class SmallVectorImpl;
	class TargetData;	class TargetData;

	class TargetMachine;
	class TargetRegisterClass;	class TargetRegisterClass;
	class TargetLoweringObjectFile;	class TargetLoweringObjectFile;
	class Value;	class Value;


	// FIXME: should this be here?	namespace Sched {
	namespace TLSModel {	enum Preference {
	enum Model {	None, // No preference
	GeneralDynamic,	Source, // Follow source order.
	LocalDynamic,	RegPressure, // Scheduling for lowest register pressure.
	InitialExec,	Hybrid, // Scheduling for both latency and register pressur
	LocalExec	e.
		ILP, // Scheduling for ILP in low register pressure mode
		.
		VLIW // Scheduling for VLIW targets.
	};	};
	}	}

	TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc);

	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	/// TargetLowering - This class defines information used to lower LLVM code to	/// TargetLowering - This class defines information used to lower LLVM code to
	/// legal SelectionDAG operators that the target instruction selector can a ccept	/// legal SelectionDAG operators that the target instruction selector can a ccept
	/// natively.	/// natively.
	///	///
	/// This class also defines callbacks that targets must implement to lower	/// This class also defines callbacks that targets must implement to lower
	/// target-specific constructs to SelectionDAG operators.	/// target-specific constructs to SelectionDAG operators.
	///	///
	class TargetLowering {	class TargetLowering {

	skipping to change at line 96	skipping to change at line 88
	public:	public:
	/// LegalizeAction - This enum indicates whether operations are valid for a	/// LegalizeAction - This enum indicates whether operations are valid for a
	/// target, and if not, what action should be used to make them valid.	/// target, and if not, what action should be used to make them valid.
	enum LegalizeAction {	enum LegalizeAction {
	Legal, // The target natively supports this operation.	Legal, // The target natively supports this operation.
	Promote, // This operation should be executed in a larger type.	Promote, // This operation should be executed in a larger type.
	Expand, // Try to expand this to other ops, otherwise use a libcall .	Expand, // Try to expand this to other ops, otherwise use a libcall .
	Custom // Use the LowerOperation hook to implement custom lowering .	Custom // Use the LowerOperation hook to implement custom lowering .
	};	};


	/// LegalizeAction - This enum indicates whether a types are legal for a	/// LegalizeTypeAction - This enum indicates whether a types are legal fo r a
	/// target, and if not, what action should be used to make them valid.	/// target, and if not, what action should be used to make them valid.
	enum LegalizeTypeAction {	enum LegalizeTypeAction {
	TypeLegal, // The target natively supports this type.	TypeLegal, // The target natively supports this type.
	TypePromoteInteger, // Replace this integer with a larger one.	TypePromoteInteger, // Replace this integer with a larger one.
	TypeExpandInteger, // Split this integer into two of half the size.	TypeExpandInteger, // Split this integer into two of half the size.
	TypeSoftenFloat, // Convert this float to a same size integer type.	TypeSoftenFloat, // Convert this float to a same size integer type.
	TypeExpandFloat, // Split this float into two of half the size.	TypeExpandFloat, // Split this float into two of half the size.
	TypeScalarizeVector, // Replace this one-element vector with its elemen t.	TypeScalarizeVector, // Replace this one-element vector with its elemen t.
	TypeSplitVector, // Split this vector into two of half the size.	TypeSplitVector, // Split this vector into two of half the size.
	TypeWidenVector // This vector should be widened into a larger vec tor.	TypeWidenVector // This vector should be widened into a larger vec tor.
	};	};

	enum BooleanContent { // How the target represents true/false values.	enum BooleanContent { // How the target represents true/false values.
	UndefinedBooleanContent, // Only bit 0 counts, the rest can hold gar bage.	UndefinedBooleanContent, // Only bit 0 counts, the rest can hold gar bage.
	ZeroOrOneBooleanContent, // All bits zero except for bit 0.	ZeroOrOneBooleanContent, // All bits zero except for bit 0.
	ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.	ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
	};	};

	static ISD::NodeType getExtendForContent(BooleanContent Content) {	static ISD::NodeType getExtendForContent(BooleanContent Content) {
	switch (Content) {	switch (Content) {

	default:
	assert(false && "Unknown BooleanContent!");
	case UndefinedBooleanContent:	case UndefinedBooleanContent:
	// Extend by adding rubbish bits.	// Extend by adding rubbish bits.
	return ISD::ANY_EXTEND;	return ISD::ANY_EXTEND;
	case ZeroOrOneBooleanContent:	case ZeroOrOneBooleanContent:
	// Extend by adding zero bits.	// Extend by adding zero bits.
	return ISD::ZERO_EXTEND;	return ISD::ZERO_EXTEND;
	case ZeroOrNegativeOneBooleanContent:	case ZeroOrNegativeOneBooleanContent:
	// Extend by copying the sign bit.	// Extend by copying the sign bit.
	return ISD::SIGN_EXTEND;	return ISD::SIGN_EXTEND;
	}	}

		llvm_unreachable("Invalid content kind");
	}	}

	/// NOTE: The constructor takes ownership of TLOF.	/// NOTE: The constructor takes ownership of TLOF.
	explicit TargetLowering(const TargetMachine &TM,	explicit TargetLowering(const TargetMachine &TM,
	const TargetLoweringObjectFile *TLOF);	const TargetLoweringObjectFile *TLOF);
	virtual ~TargetLowering();	virtual ~TargetLowering();

	const TargetMachine &getTargetMachine() const { return TM; }	const TargetMachine &getTargetMachine() const { return TM; }
	const TargetData *getTargetData() const { return TD; }	const TargetData *getTargetData() const { return TD; }
	const TargetLoweringObjectFile &getObjFileLowering() const { return TLOF; }	const TargetLoweringObjectFile &getObjFileLowering() const { return TLOF; }

	skipping to change at line 201	skipping to change at line 192

	/// getSchedulingPreference - Some scheduler, e.g. hybrid, can switch to	/// getSchedulingPreference - Some scheduler, e.g. hybrid, can switch to
	/// different scheduling heuristics for different nodes. This function re turns	/// different scheduling heuristics for different nodes. This function re turns
	/// the preference (or none) for the given node.	/// the preference (or none) for the given node.
	virtual Sched::Preference getSchedulingPreference(SDNode *) const {	virtual Sched::Preference getSchedulingPreference(SDNode *) const {
	return Sched::None;	return Sched::None;
	}	}

	/// getRegClassFor - Return the register class that should be used for th e	/// getRegClassFor - Return the register class that should be used for th e
	/// specified value type.	/// specified value type.

	virtual TargetRegisterClass *getRegClassFor(EVT VT) const {	virtual const TargetRegisterClass *getRegClassFor(EVT VT) const {
	assert(VT.isSimple() && "getRegClassFor called on illegal type!");	assert(VT.isSimple() && "getRegClassFor called on illegal type!");

	TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy];	const TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy ];
	assert(RC && "This value type is not natively supported!");	assert(RC && "This value type is not natively supported!");
	return RC;	return RC;
	}	}

	/// getRepRegClassFor - Return the 'representative' register class for th e	/// getRepRegClassFor - Return the 'representative' register class for th e
	/// specified value type. The 'representative' register class is the larg est	/// specified value type. The 'representative' register class is the larg est
	/// legal super-reg register class for the register class of the value ty pe.	/// legal super-reg register class for the register class of the value ty pe.
	/// For example, on i386 the rep register class for i8, i16, and i32 are GR32;	/// For example, on i386 the rep register class for i8, i16, and i32 are GR32;
	/// while the rep register class is GR64 on x86_64.	/// while the rep register class is GR64 on x86_64.
	virtual const TargetRegisterClass *getRepRegClassFor(EVT VT) const {	virtual const TargetRegisterClass *getRepRegClassFor(EVT VT) const {

	skipping to change at line 294	skipping to change at line 285
	EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {	EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
	assert(!VT.isVector());	assert(!VT.isVector());
	while (true) {	while (true) {
	switch (getTypeAction(Context, VT)) {	switch (getTypeAction(Context, VT)) {
	case TypeLegal:	case TypeLegal:
	return VT;	return VT;
	case TypeExpandInteger:	case TypeExpandInteger:
	VT = getTypeToTransformTo(Context, VT);	VT = getTypeToTransformTo(Context, VT);
	break;	break;
	default:	default:

	assert(false && "Type is not legal nor is it to be expanded!");	llvm_unreachable("Type is not legal nor is it to be expanded!");
	return VT;
	}	}
	}	}

	return VT;
	}	}

	/// getVectorTypeBreakdown - Vector types are broken down into some numbe r of	/// getVectorTypeBreakdown - Vector types are broken down into some numbe r of
	/// legal first class types. For example, EVT::v8f32 maps to 2 EVT::v4f3 2	/// legal first class types. For example, EVT::v8f32 maps to 2 EVT::v4f3 2
	/// with Altivec or SSE1, or 8 promoted EVT::f64 values with the X86 FP s tack.	/// with Altivec or SSE1, or 8 promoted EVT::f64 values with the X86 FP s tack.
	/// Similarly, EVT::v2i64 turns into 4 EVT::i32 values with both PPC and X86.	/// Similarly, EVT::v2i64 turns into 4 EVT::i32 values with both PPC and X86.
	///	///
	/// This method returns the number of registers needed, and the VT for ea ch	/// This method returns the number of registers needed, and the VT for ea ch
	/// register. It also returns the VT and quantity of the intermediate va lues	/// register. It also returns the VT and quantity of the intermediate va lues
	/// before they are promoted/expanded.	/// before they are promoted/expanded.

	skipping to change at line 521	skipping to change at line 510
	} while (!isTypeLegal(NVT) \|\|	} while (!isTypeLegal(NVT) \|\|
	getOperationAction(Op, NVT) == Promote);	getOperationAction(Op, NVT) == Promote);
	return NVT;	return NVT;
	}	}

	/// getValueType - Return the EVT corresponding to this LLVM type.	/// getValueType - Return the EVT corresponding to this LLVM type.
	/// This is fixed by the LLVM operations except for the pointer size. If	/// This is fixed by the LLVM operations except for the pointer size. If
	/// AllowUnknown is true, this will return MVT::Other for types with no E VT	/// AllowUnknown is true, this will return MVT::Other for types with no E VT
	/// counterpart (e.g. structs), otherwise it will assert.	/// counterpart (e.g. structs), otherwise it will assert.
	EVT getValueType(Type *Ty, bool AllowUnknown = false) const {	EVT getValueType(Type *Ty, bool AllowUnknown = false) const {

	EVT VT = EVT::getEVT(Ty, AllowUnknown);	// Lower scalar pointers to native pointer types.
	return VT == MVT::iPTR ? PointerTy : VT;	if (Ty->isPointerTy()) return PointerTy;

		if (Ty->isVectorTy()) {
		VectorType *VTy = cast<VectorType>(Ty);
		Type *Elm = VTy->getElementType();
		// Lower vectors of pointers to native pointer types.
		if (Elm->isPointerTy())
		Elm = EVT(PointerTy).getTypeForEVT(Ty->getContext());
		return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(Elm, false),
		VTy->getNumElements());
		}
		return EVT::getEVT(Ty, AllowUnknown);
	}	}

	/// getByValTypeAlignment - Return the desired alignment for ByVal aggreg ate	/// getByValTypeAlignment - Return the desired alignment for ByVal aggreg ate
	/// function arguments in the caller parameter area. This is the actual	/// function arguments in the caller parameter area. This is the actual
	/// alignment, not its logarithm.	/// alignment, not its logarithm.
	virtual unsigned getByValTypeAlignment(Type *Ty) const;	virtual unsigned getByValTypeAlignment(Type *Ty) const;

	/// getRegisterType - Return the type of registers that this ValueType wi ll	/// getRegisterType - Return the type of registers that this ValueType wi ll
	/// eventually require.	/// eventually require.
	EVT getRegisterType(MVT VT) const {	EVT getRegisterType(MVT VT) const {

	skipping to change at line 555	skipping to change at line 555
	if (VT.isVector()) {	if (VT.isVector()) {
	EVT VT1, RegisterVT;	EVT VT1, RegisterVT;
	unsigned NumIntermediates;	unsigned NumIntermediates;
	(void)getVectorTypeBreakdown(Context, VT, VT1,	(void)getVectorTypeBreakdown(Context, VT, VT1,
	NumIntermediates, RegisterVT);	NumIntermediates, RegisterVT);
	return RegisterVT;	return RegisterVT;
	}	}
	if (VT.isInteger()) {	if (VT.isInteger()) {
	return getRegisterType(Context, getTypeToTransformTo(Context, VT));	return getRegisterType(Context, getTypeToTransformTo(Context, VT));
	}	}

	assert(0 && "Unsupported extended type!");	llvm_unreachable("Unsupported extended type!");
	return EVT(MVT::Other); // Not reached
	}	}

	/// getNumRegisters - Return the number of registers that this ValueType will	/// getNumRegisters - Return the number of registers that this ValueType will
	/// eventually require. This is one for any types promoted to live in la rger	/// eventually require. This is one for any types promoted to live in la rger
	/// registers, but may be more than one for types (like i64) that are spl it	/// registers, but may be more than one for types (like i64) that are spl it
	/// into pieces. For types like i140, which are first promoted then expa nded,	/// into pieces. For types like i140, which are first promoted then expa nded,
	/// it is the number of registers needed to hold all the bits of the orig inal	/// it is the number of registers needed to hold all the bits of the orig inal
	/// type. For an i140 on a 32 bit machine this means 5 registers.	/// type. For an i140 on a 32 bit machine this means 5 registers.
	unsigned getNumRegisters(LLVMContext &Context, EVT VT) const {	unsigned getNumRegisters(LLVMContext &Context, EVT VT) const {
	if (VT.isSimple()) {	if (VT.isSimple()) {

	skipping to change at line 581	skipping to change at line 580
	if (VT.isVector()) {	if (VT.isVector()) {
	EVT VT1, VT2;	EVT VT1, VT2;
	unsigned NumIntermediates;	unsigned NumIntermediates;
	return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2 );	return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2 );
	}	}
	if (VT.isInteger()) {	if (VT.isInteger()) {
	unsigned BitWidth = VT.getSizeInBits();	unsigned BitWidth = VT.getSizeInBits();
	unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();	unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
	return (BitWidth + RegWidth - 1) / RegWidth;	return (BitWidth + RegWidth - 1) / RegWidth;
	}	}

	assert(0 && "Unsupported extended type!");	llvm_unreachable("Unsupported extended type!");
	return 0; // Not reached
	}	}

	/// ShouldShrinkFPConstant - If true, then instruction selection should	/// ShouldShrinkFPConstant - If true, then instruction selection should
	/// seek to shrink the FP constant of the specified type to a smaller typ e	/// seek to shrink the FP constant of the specified type to a smaller typ e
	/// in order to save space and / or reduce runtime.	/// in order to save space and / or reduce runtime.
	virtual bool ShouldShrinkFPConstant(EVT) const { return true; }	virtual bool ShouldShrinkFPConstant(EVT) const { return true; }

	/// hasTargetDAGCombine - If true, the target has custom DAG combine	/// hasTargetDAGCombine - If true, the target has custom DAG combine
	/// transformations that it can perform for the specified node.	/// transformations that it can perform for the specified node.
	bool hasTargetDAGCombine(ISD::NodeType NT) const {	bool hasTargetDAGCombine(ISD::NodeType NT) const {

	skipping to change at line 647	skipping to change at line 645
	bool shouldOptimizeCodePlacement() const {	bool shouldOptimizeCodePlacement() const {
	return benefitFromCodePlacementOpt;	return benefitFromCodePlacementOpt;
	}	}

	/// getOptimalMemOpType - Returns the target specific optimal type for lo ad	/// getOptimalMemOpType - Returns the target specific optimal type for lo ad
	/// and store operations as a result of memset, memcpy, and memmove	/// and store operations as a result of memset, memcpy, and memmove
	/// lowering. If DstAlign is zero that means it's safe to destination	/// lowering. If DstAlign is zero that means it's safe to destination
	/// alignment can satisfy any constraint. Similarly if SrcAlign is zero i t	/// alignment can satisfy any constraint. Similarly if SrcAlign is zero i t
	/// means there isn't a need to check it against alignment requirement,	/// means there isn't a need to check it against alignment requirement,
	/// probably because the source does not need to be loaded. If	/// probably because the source does not need to be loaded. If

	/// 'NonScalarIntSafe' is true, that means it's safe to return a	/// 'IsZeroVal' is true, that means it's safe to return a
	/// non-scalar-integer type, e.g. empty string source, constant, or loade d	/// non-scalar-integer type, e.g. empty string source, constant, or loade d
	/// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is	/// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
	/// constant so it does not need to be loaded.	/// constant so it does not need to be loaded.
	/// It returns EVT::Other if the type should be determined using generic	/// It returns EVT::Other if the type should be determined using generic
	/// target-independent logic.	/// target-independent logic.
	virtual EVT getOptimalMemOpType(uint64_t /Size/,	virtual EVT getOptimalMemOpType(uint64_t /Size/,
	unsigned /DstAlign/, unsigned /SrcAlig n/,	unsigned /DstAlign/, unsigned /SrcAlig n/,

	bool /NonScalarIntSafe/,	bool /IsZeroVal/,
	bool /MemcpyStrSrc/,	bool /MemcpyStrSrc/,
	MachineFunction &/MF/) const {	MachineFunction &/MF/) const {
	return MVT::Other;	return MVT::Other;
	}	}

	/// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp	/// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp
	/// to implement llvm.setjmp.	/// to implement llvm.setjmp.
	bool usesUnderscoreSetJmp() const {	bool usesUnderscoreSetJmp() const {
	return UseUnderscoreSetJmp;	return UseUnderscoreSetJmp;
	}	}

	skipping to change at line 680	skipping to change at line 678
	return UseUnderscoreLongJmp;	return UseUnderscoreLongJmp;
	}	}

	/// getStackPointerRegisterToSaveRestore - If a physical register, this	/// getStackPointerRegisterToSaveRestore - If a physical register, this
	/// specifies the register that llvm.savestack/llvm.restorestack should s ave	/// specifies the register that llvm.savestack/llvm.restorestack should s ave
	/// and restore.	/// and restore.
	unsigned getStackPointerRegisterToSaveRestore() const {	unsigned getStackPointerRegisterToSaveRestore() const {
	return StackPointerRegisterToSaveRestore;	return StackPointerRegisterToSaveRestore;
	}	}


	/// getExceptionAddressRegister - If a physical register, this returns	/// getExceptionPointerRegister - If a physical register, this returns
	/// the register that receives the exception address on entry to a landin g	/// the register that receives the exception address on entry to a landin g
	/// pad.	/// pad.

	unsigned getExceptionAddressRegister() const {	unsigned getExceptionPointerRegister() const {
	return ExceptionPointerRegister;	return ExceptionPointerRegister;
	}	}

	/// getExceptionSelectorRegister - If a physical register, this returns	/// getExceptionSelectorRegister - If a physical register, this returns
	/// the register that receives the exception typeid on entry to a landing	/// the register that receives the exception typeid on entry to a landing
	/// pad.	/// pad.
	unsigned getExceptionSelectorRegister() const {	unsigned getExceptionSelectorRegister() const {
	return ExceptionSelectorRegister;	return ExceptionSelectorRegister;
	}	}


	skipping to change at line 773	skipping to change at line 771

	/// getJumpTableEncoding - Return the entry encoding for a jump table in the	/// getJumpTableEncoding - Return the entry encoding for a jump table in the
	/// current function. The returned value is a member of the	/// current function. The returned value is a member of the
	/// MachineJumpTableInfo::JTEntryKind enum.	/// MachineJumpTableInfo::JTEntryKind enum.
	virtual unsigned getJumpTableEncoding() const;	virtual unsigned getJumpTableEncoding() const;

	virtual const MCExpr *	virtual const MCExpr *
	LowerCustomJumpTableEntry(const MachineJumpTableInfo * /MJTI/,	LowerCustomJumpTableEntry(const MachineJumpTableInfo * /MJTI/,
	const MachineBasicBlock * /MBB/, unsigned /u id/,	const MachineBasicBlock * /MBB/, unsigned /u id/,
	MCContext &/Ctx/) const {	MCContext &/Ctx/) const {

	assert(0 && "Need to implement this hook if target has custom JTIs");	llvm_unreachable("Need to implement this hook if target has custom JTIs
	return 0;	");
	}	}

	/// getPICJumpTableRelocaBase - Returns relocation base for the given PIC	/// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
	/// jumptable.	/// jumptable.
	virtual SDValue getPICJumpTableRelocBase(SDValue Table,	virtual SDValue getPICJumpTableRelocBase(SDValue Table,
	SelectionDAG &DAG) const;	SelectionDAG &DAG) const;

	/// getPICJumpTableRelocBaseExpr - This returns the relocation base for t he	/// getPICJumpTableRelocBaseExpr - This returns the relocation base for t he
	/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an	/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
	/// MCExpr.	/// MCExpr.

	skipping to change at line 866	skipping to change at line 863
	/// The KnownZero/One bits may only be accurate for those bits in the	/// The KnownZero/One bits may only be accurate for those bits in the
	/// DemandedMask.	/// DemandedMask.
	bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,	bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
	APInt &KnownZero, APInt &KnownOne,	APInt &KnownZero, APInt &KnownOne,
	TargetLoweringOpt &TLO, unsigned Depth = 0) con st;	TargetLoweringOpt &TLO, unsigned Depth = 0) con st;

	/// computeMaskedBitsForTargetNode - Determine which of the bits specifie d in	/// computeMaskedBitsForTargetNode - Determine which of the bits specifie d in
	/// Mask are known to be either zero or one and return them in the	/// Mask are known to be either zero or one and return them in the
	/// KnownZero/KnownOne bitsets.	/// KnownZero/KnownOne bitsets.
	virtual void computeMaskedBitsForTargetNode(const SDValue Op,	virtual void computeMaskedBitsForTargetNode(const SDValue Op,

	const APInt &Mask,
	APInt &KnownZero,	APInt &KnownZero,
	APInt &KnownOne,	APInt &KnownOne,
	const SelectionDAG &DAG,	const SelectionDAG &DAG,
	unsigned Depth = 0) const;	unsigned Depth = 0) const;

	/// ComputeNumSignBitsForTargetNode - This method can be implemented by	/// ComputeNumSignBitsForTargetNode - This method can be implemented by
	/// targets that want to expose additional information about sign bits to the	/// targets that want to expose additional information about sign bits to the
	/// DAG Combiner.	/// DAG Combiner.
	virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,	virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
	unsigned Depth = 0) cons t;	unsigned Depth = 0) cons t;

	skipping to change at line 1036	skipping to change at line 1032
	void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; }	void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; }

	/// setPow2DivIsCheap - Tells the code generator that it shouldn't genera te	/// setPow2DivIsCheap - Tells the code generator that it shouldn't genera te
	/// srl/add/sra for a signed divide by power of two, and let the target h andle	/// srl/add/sra for a signed divide by power of two, and let the target h andle
	/// it.	/// it.
	void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; }	void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; }

	/// addRegisterClass - Add the specified register class as an available	/// addRegisterClass - Add the specified register class as an available
	/// regclass for the specified value type. This indicates the selector c an	/// regclass for the specified value type. This indicates the selector c an
	/// handle values of that class natively.	/// handle values of that class natively.

	void addRegisterClass(EVT VT, TargetRegisterClass *RC) {	void addRegisterClass(EVT VT, const TargetRegisterClass *RC) {
	assert((unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassFor VT));	assert((unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassFor VT));
	AvailableRegClasses.push_back(std::make_pair(VT, RC));	AvailableRegClasses.push_back(std::make_pair(VT, RC));
	RegClassForVT[VT.getSimpleVT().SimpleTy] = RC;	RegClassForVT[VT.getSimpleVT().SimpleTy] = RC;
	}	}

	/// findRepresentativeClass - Return the largest legal super-reg register class	/// findRepresentativeClass - Return the largest legal super-reg register class
	/// of the register class for the specified type and its associated "cost ".	/// of the register class for the specified type and its associated "cost ".
	virtual std::pair<const TargetRegisterClass*, uint8_t>	virtual std::pair<const TargetRegisterClass*, uint8_t>
	findRepresentativeClass(EVT VT) const;	findRepresentativeClass(EVT VT) const;


	skipping to change at line 1142	skipping to change at line 1138
	void setJumpBufSize(unsigned Size) {	void setJumpBufSize(unsigned Size) {
	JumpBufSize = Size;	JumpBufSize = Size;
	}	}

	/// setJumpBufAlignment - Set the target's required jmp_buf buffer	/// setJumpBufAlignment - Set the target's required jmp_buf buffer
	/// alignment (in bytes); default is 0	/// alignment (in bytes); default is 0
	void setJumpBufAlignment(unsigned Align) {	void setJumpBufAlignment(unsigned Align) {
	JumpBufAlignment = Align;	JumpBufAlignment = Align;
	}	}


	/// setMinFunctionAlignment - Set the target's minimum function alignment	/// setMinFunctionAlignment - Set the target's minimum function alignment
	.	(in
		/// log2(bytes))
	void setMinFunctionAlignment(unsigned Align) {	void setMinFunctionAlignment(unsigned Align) {
	MinFunctionAlignment = Align;	MinFunctionAlignment = Align;
	}	}

	/// setPrefFunctionAlignment - Set the target's preferred function alignm ent.	/// setPrefFunctionAlignment - Set the target's preferred function alignm ent.
	/// This should be set if there is a performance benefit to	/// This should be set if there is a performance benefit to

	/// higher-than-minimum alignment	/// higher-than-minimum alignment (in log2(bytes))
	void setPrefFunctionAlignment(unsigned Align) {	void setPrefFunctionAlignment(unsigned Align) {
	PrefFunctionAlignment = Align;	PrefFunctionAlignment = Align;
	}	}

	/// setPrefLoopAlignment - Set the target's preferred loop alignment. Def ault	/// setPrefLoopAlignment - Set the target's preferred loop alignment. Def ault
	/// alignment is zero, it means the target does not care about loop align ment.	/// alignment is zero, it means the target does not care about loop align ment.

		/// The alignment is specified in log2(bytes).
	void setPrefLoopAlignment(unsigned Align) {	void setPrefLoopAlignment(unsigned Align) {
	PrefLoopAlignment = Align;	PrefLoopAlignment = Align;
	}	}

	/// setMinStackArgumentAlignment - Set the minimum stack alignment of an	/// setMinStackArgumentAlignment - Set the minimum stack alignment of an

	/// argument.	/// argument (in log2(bytes)).
	void setMinStackArgumentAlignment(unsigned Align) {	void setMinStackArgumentAlignment(unsigned Align) {
	MinStackArgumentAlignment = Align;	MinStackArgumentAlignment = Align;
	}	}

	/// setShouldFoldAtomicFences - Set if the target's implementation of the	/// setShouldFoldAtomicFences - Set if the target's implementation of the
	/// atomic operation intrinsics includes locking. Default is false.	/// atomic operation intrinsics includes locking. Default is false.
	void setShouldFoldAtomicFences(bool fold) {	void setShouldFoldAtomicFences(bool fold) {
	ShouldFoldAtomicFences = fold;	ShouldFoldAtomicFences = fold;
	}	}


	skipping to change at line 1197	skipping to change at line 1195
	/// specified DAG. The implementation should fill in the InVals array	/// specified DAG. The implementation should fill in the InVals array
	/// with legal-type argument values, and return the resulting token	/// with legal-type argument values, and return the resulting token
	/// chain value.	/// chain value.
	///	///
	virtual SDValue	virtual SDValue
	LowerFormalArguments(SDValue /Chain/, CallingConv::ID /CallConv/,	LowerFormalArguments(SDValue /Chain/, CallingConv::ID /CallConv/,
	bool /isVarArg/,	bool /isVarArg/,
	const SmallVectorImpl<ISD::InputArg> &/Ins/,	const SmallVectorImpl<ISD::InputArg> &/Ins/,
	DebugLoc /dl/, SelectionDAG &/DAG/,	DebugLoc /dl/, SelectionDAG &/DAG/,
	SmallVectorImpl<SDValue> &/InVals/) const {	SmallVectorImpl<SDValue> &/InVals/) const {

	assert(0 && "Not Implemented");	llvm_unreachable("Not Implemented");
	return SDValue(); // this is here to silence compiler errors
	}	}

	/// LowerCallTo - This function lowers an abstract call to a function int o an	/// LowerCallTo - This function lowers an abstract call to a function int o an
	/// actual call. This returns a pair of operands. The first element is the	/// actual call. This returns a pair of operands. The first element is the
	/// return value for the function (if RetTy is not VoidTy). The second	/// return value for the function (if RetTy is not VoidTy). The second
	/// element is the outgoing token chain. It calls LowerCall to do the act ual	/// element is the outgoing token chain. It calls LowerCall to do the act ual
	/// lowering.	/// lowering.
	struct ArgListEntry {	struct ArgListEntry {
	SDValue Node;	SDValue Node;
	Type* Ty;	Type* Ty;

	skipping to change at line 1225	skipping to change at line 1222
	uint16_t Alignment;	uint16_t Alignment;

	ArgListEntry() : isSExt(false), isZExt(false), isInReg(false),	ArgListEntry() : isSExt(false), isZExt(false), isInReg(false),
	isSRet(false), isNest(false), isByVal(false), Alignment(0) { }	isSRet(false), isNest(false), isByVal(false), Alignment(0) { }
	};	};
	typedef std::vector<ArgListEntry> ArgListTy;	typedef std::vector<ArgListEntry> ArgListTy;
	std::pair<SDValue, SDValue>	std::pair<SDValue, SDValue>
	LowerCallTo(SDValue Chain, Type *RetTy, bool RetSExt, bool RetZExt,	LowerCallTo(SDValue Chain, Type *RetTy, bool RetSExt, bool RetZExt,
	bool isVarArg, bool isInreg, unsigned NumFixedArgs,	bool isVarArg, bool isInreg, unsigned NumFixedArgs,
	CallingConv::ID CallConv, bool isTailCall,	CallingConv::ID CallConv, bool isTailCall,

	bool isReturnValueUsed, SDValue Callee, ArgListTy &Args,	bool doesNotRet, bool isReturnValueUsed,
		SDValue Callee, ArgListTy &Args,
	SelectionDAG &DAG, DebugLoc dl) const;	SelectionDAG &DAG, DebugLoc dl) const;

	/// LowerCall - This hook must be implemented to lower calls into the	/// LowerCall - This hook must be implemented to lower calls into the
	/// the specified DAG. The outgoing arguments to the call are described	/// the specified DAG. The outgoing arguments to the call are described
	/// by the Outs array, and the values to be returned by the call are	/// by the Outs array, and the values to be returned by the call are
	/// described by the Ins array. The implementation should fill in the	/// described by the Ins array. The implementation should fill in the
	/// InVals array with legal-type return values from the call, and return	/// InVals array with legal-type return values from the call, and return
	/// the resulting token chain value.	/// the resulting token chain value.
	virtual SDValue	virtual SDValue
	LowerCall(SDValue /Chain/, SDValue /Callee/,	LowerCall(SDValue /Chain/, SDValue /Callee/,
	CallingConv::ID /CallConv/, bool /isVarArg/,	CallingConv::ID /CallConv/, bool /isVarArg/,

	bool &/isTailCall/,	bool /doesNotRet/, bool &/isTailCall/,
	const SmallVectorImpl<ISD::OutputArg> &/Outs/,	const SmallVectorImpl<ISD::OutputArg> &/Outs/,
	const SmallVectorImpl<SDValue> &/OutVals/,	const SmallVectorImpl<SDValue> &/OutVals/,
	const SmallVectorImpl<ISD::InputArg> &/Ins/,	const SmallVectorImpl<ISD::InputArg> &/Ins/,
	DebugLoc /dl/, SelectionDAG &/DAG/,	DebugLoc /dl/, SelectionDAG &/DAG/,
	SmallVectorImpl<SDValue> &/InVals/) const {	SmallVectorImpl<SDValue> &/InVals/) const {

	assert(0 && "Not Implemented");	llvm_unreachable("Not Implemented");
	return SDValue(); // this is here to silence compiler errors
	}	}

	/// HandleByVal - Target-specific cleanup for formal ByVal parameters.	/// HandleByVal - Target-specific cleanup for formal ByVal parameters.
	virtual void HandleByVal(CCState *, unsigned &) const {}	virtual void HandleByVal(CCState *, unsigned &) const {}

	/// CanLowerReturn - This hook should be implemented to check whether the	/// CanLowerReturn - This hook should be implemented to check whether the
	/// return values described by the Outs array can fit into the return	/// return values described by the Outs array can fit into the return
	/// registers. If false is returned, an sret-demotion is performed.	/// registers. If false is returned, an sret-demotion is performed.
	///	///
	virtual bool CanLowerReturn(CallingConv::ID /CallConv/,	virtual bool CanLowerReturn(CallingConv::ID /CallConv/,

	skipping to change at line 1274	skipping to change at line 1271
	/// return values, described by the Outs array, into the specified	/// return values, described by the Outs array, into the specified
	/// DAG. The implementation should return the resulting token chain	/// DAG. The implementation should return the resulting token chain
	/// value.	/// value.
	///	///
	virtual SDValue	virtual SDValue
	LowerReturn(SDValue /Chain/, CallingConv::ID /CallConv/,	LowerReturn(SDValue /Chain/, CallingConv::ID /CallConv/,
	bool /isVarArg/,	bool /isVarArg/,
	const SmallVectorImpl<ISD::OutputArg> &/Outs/,	const SmallVectorImpl<ISD::OutputArg> &/Outs/,
	const SmallVectorImpl<SDValue> &/OutVals/,	const SmallVectorImpl<SDValue> &/OutVals/,
	DebugLoc /dl/, SelectionDAG &/DAG/) const {	DebugLoc /dl/, SelectionDAG &/DAG/) const {

	assert(0 && "Not Implemented");	llvm_unreachable("Not Implemented");
	return SDValue(); // this is here to silence compiler errors
	}	}

	/// isUsedByReturnOnly - Return true if result of the specified node is u sed	/// isUsedByReturnOnly - Return true if result of the specified node is u sed

	/// by a return node only. This is used to determine whether it is possib	/// by a return node only. It also compute and return the input chain for
	le	the
		/// tail call.
		/// This is used to determine whether it is possible
	/// to codegen a libcall as tail call at legalization time.	/// to codegen a libcall as tail call at legalization time.

	virtual bool isUsedByReturnOnly(SDNode *) const {	virtual bool isUsedByReturnOnly(SDNode *, SDValue &Chain) const {
	return false;	return false;
	}	}

	/// mayBeEmittedAsTailCall - Return true if the target may be able emit t he	/// mayBeEmittedAsTailCall - Return true if the target may be able emit t he
	/// call instruction as a tail call. This is used by optimization passes to	/// call instruction as a tail call. This is used by optimization passes to
	/// determine if it's profitable to duplicate return instructions to enab le	/// determine if it's profitable to duplicate return instructions to enab le
	/// tailcall optimization.	/// tailcall optimization.
	virtual bool mayBeEmittedAsTailCall(CallInst *) const {	virtual bool mayBeEmittedAsTailCall(CallInst *) const {
	return false;	return false;
	}	}

	skipping to change at line 1340	skipping to change at line 1338
	/// lowering for that result type. The target places new result values f or	/// lowering for that result type. The target places new result values f or
	/// the node in Results (their number and types must exactly match those of	/// the node in Results (their number and types must exactly match those of
	/// the original return values of the node), or leaves Results empty, whi ch	/// the original return values of the node), or leaves Results empty, whi ch
	/// indicates that the node is not to be custom lowered after all.	/// indicates that the node is not to be custom lowered after all.
	///	///
	/// If the target has no operations that require custom lowering, it need not	/// If the target has no operations that require custom lowering, it need not
	/// implement this. The default implementation aborts.	/// implement this. The default implementation aborts.
	virtual void ReplaceNodeResults(SDNode * /N/,	virtual void ReplaceNodeResults(SDNode * /N/,
	SmallVectorImpl<SDValue> &/Results/,	SmallVectorImpl<SDValue> &/Results/,
	SelectionDAG &/DAG/) const {	SelectionDAG &/DAG/) const {

	assert(0 && "ReplaceNodeResults not implemented for this target!");	llvm_unreachable("ReplaceNodeResults not implemented for this target!") ;
	}	}

	/// getTargetNodeName() - This method returns the name of a target specif ic	/// getTargetNodeName() - This method returns the name of a target specif ic
	/// DAG node.	/// DAG node.
	virtual const char *getTargetNodeName(unsigned Opcode) const;	virtual const char *getTargetNodeName(unsigned Opcode) const;

	/// createFastISel - This method returns a target specific FastISel objec t,	/// createFastISel - This method returns a target specific FastISel objec t,
	/// or null if the target does not support "fast" ISel.	/// or null if the target does not support "fast" ISel.
	virtual FastISel *createFastISel(FunctionLoweringInfo &) const {	virtual FastISel *createFastISel(FunctionLoweringInfo &) const {
	return 0;	return 0;

	skipping to change at line 1532	skipping to change at line 1530
	/// no scale.	/// no scale.
	///	///
	struct AddrMode {	struct AddrMode {
	GlobalValue *BaseGV;	GlobalValue *BaseGV;
	int64_t BaseOffs;	int64_t BaseOffs;
	bool HasBaseReg;	bool HasBaseReg;
	int64_t Scale;	int64_t Scale;
	AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {}	AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {}
	};	};


		/// GetAddrModeArguments - CodeGenPrepare sinks address calculations into
		the
		/// same BB as Load/Store instructions reading the address. This allows
		as
		/// much computation as possible to be done in the address mode for that
		/// operand. This hook lets targets also pass back when this should be d
		one
		/// on intrinsics which load/store.
		virtual bool GetAddrModeArguments(IntrinsicInst *I,
		SmallVectorImpl<Value*> &Ops,
		Type *&AccessTy) const {
		return false;
		}

	/// isLegalAddressingMode - Return true if the addressing mode represente d by	/// isLegalAddressingMode - Return true if the addressing mode represente d by
	/// AM is legal for this target, for a load/store of the specified type.	/// AM is legal for this target, for a load/store of the specified type.
	/// The type may be VoidTy, in which case only return true if the address ing	/// The type may be VoidTy, in which case only return true if the address ing
	/// mode is legal for a load/store of any legal type.	/// mode is legal for a load/store of any legal type.
	/// TODO: Handle pre/postinc as well.	/// TODO: Handle pre/postinc as well.
	virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;	virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;

	/// isLegalICmpImmediate - Return true if the specified immediate is lega l	/// isLegalICmpImmediate - Return true if the specified immediate is lega l
	/// icmp immediate, that is the target has icmp instructions which can co mpare	/// icmp immediate, that is the target has icmp instructions which can co mpare
	/// a register against the immediate without having to materialize the	/// a register against the immediate without having to materialize the

	skipping to change at line 1582	skipping to change at line 1591
	/// all instructions that define 32-bit values implicit zero-extend the	/// all instructions that define 32-bit values implicit zero-extend the
	/// result out to 64 bits.	/// result out to 64 bits.
	virtual bool isZExtFree(Type * /Ty1/, Type * /Ty2/) const {	virtual bool isZExtFree(Type * /Ty1/, Type * /Ty2/) const {
	return false;	return false;
	}	}

	virtual bool isZExtFree(EVT /VT1/, EVT /VT2/) const {	virtual bool isZExtFree(EVT /VT1/, EVT /VT2/) const {
	return false;	return false;
	}	}


		/// isFNegFree - Return true if an fneg operation is free to the point wh
		ere
		/// it is never worthwhile to replace it with a bitwise operation.
		virtual bool isFNegFree(EVT) const {
		return false;
		}

		/// isFAbsFree - Return true if an fneg operation is free to the point wh
		ere
		/// it is never worthwhile to replace it with a bitwise operation.
		virtual bool isFAbsFree(EVT) const {
		return false;
		}

	/// isNarrowingProfitable - Return true if it's profitable to narrow	/// isNarrowingProfitable - Return true if it's profitable to narrow
	/// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow	/// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
	/// from i32 to i8 but not from i32 to i16.	/// from i32 to i8 but not from i32 to i16.
	virtual bool isNarrowingProfitable(EVT /VT1/, EVT /VT2/) const {	virtual bool isNarrowingProfitable(EVT /VT1/, EVT /VT2/) const {
	return false;	return false;
	}	}

	//===-------------------------------------------------------------------- ===//	//===-------------------------------------------------------------------- ===//
	// Div utility functions	// Div utility functions
	//	//
	SDValue BuildExactSDIV(SDValue Op1, SDValue Op2, DebugLoc dl,	SDValue BuildExactSDIV(SDValue Op1, SDValue Op2, DebugLoc dl,
	SelectionDAG &DAG) const;	SelectionDAG &DAG) const;

	SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG,	SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
	std::vector<SDNode> Created) const;	std::vector<SDNode> Created) const;

	SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG,	SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
	std::vector<SDNode> Created) const;	std::vector<SDNode> Created) const;

	//===-------------------------------------------------------------------- ===//	//===-------------------------------------------------------------------- ===//
	// Runtime Library hooks	// Runtime Library hooks
	//	//

	/// setLibcallName - Rename the default libcall routine name for the spec ified	/// setLibcallName - Rename the default libcall routine name for the spec ified
	/// libcall.	/// libcall.
	void setLibcallName(RTLIB::Libcall Call, const char *Name) {	void setLibcallName(RTLIB::Libcall Call, const char *Name) {
	LibcallRoutineNames[Call] = Name;	LibcallRoutineNames[Call] = Name;

	skipping to change at line 1753	skipping to change at line 1774
	/// pad.	/// pad.
	unsigned ExceptionPointerRegister;	unsigned ExceptionPointerRegister;

	/// ExceptionSelectorRegister - If set to a physical register, this speci fies	/// ExceptionSelectorRegister - If set to a physical register, this speci fies
	/// the register that receives the exception typeid on entry to a landing	/// the register that receives the exception typeid on entry to a landing
	/// pad.	/// pad.
	unsigned ExceptionSelectorRegister;	unsigned ExceptionSelectorRegister;

	/// RegClassForVT - This indicates the default register class to use for	/// RegClassForVT - This indicates the default register class to use for
	/// each ValueType the target supports natively.	/// each ValueType the target supports natively.

	TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];	const TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
	unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];	unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
	EVT RegisterTypeForVT[MVT::LAST_VALUETYPE];	EVT RegisterTypeForVT[MVT::LAST_VALUETYPE];

	/// RepRegClassForVT - This indicates the "representative" register class to	/// RepRegClassForVT - This indicates the "representative" register class to
	/// use for each ValueType the target supports natively. This information is	/// use for each ValueType the target supports natively. This information is
	/// used by the scheduler to track register pressure. By default, the	/// used by the scheduler to track register pressure. By default, the
	/// representative register class is the largest legal super-reg register	/// representative register class is the largest legal super-reg register
	/// class of the register class of the specified type. e.g. On x86, i8, i 16,	/// class of the register class of the specified type. e.g. On x86, i8, i 16,
	/// and i32's representative class would be GR32.	/// and i32's representative class would be GR32.
	const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE];	const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE];

	skipping to change at line 1925	skipping to change at line 1946

	// Widen odd vectors to next power of two.	// Widen odd vectors to next power of two.
	if (!VT.isPow2VectorType()) {	if (!VT.isPow2VectorType()) {
	EVT NVT = VT.getPow2VectorType(Context);	EVT NVT = VT.getPow2VectorType(Context);
	return LegalizeKind(TypeWidenVector, NVT);	return LegalizeKind(TypeWidenVector, NVT);
	}	}

	// Vectors with illegal element types are expanded.	// Vectors with illegal element types are expanded.
	EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorNumElements() / 2);	EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorNumElements() / 2);
	return LegalizeKind(TypeSplitVector, NVT);	return LegalizeKind(TypeSplitVector, NVT);


	assert(false && "Unable to handle this kind of vector type");
	return LegalizeKind(TypeLegal, VT);
	}	}


	std::vector<std::pair<EVT, TargetRegisterClass*> > AvailableRegClasses;	std::vector<std::pair<EVT, const TargetRegisterClass*> > AvailableRegClas ses;

	/// TargetDAGCombineArray - Targets can specify ISD nodes that they would	/// TargetDAGCombineArray - Targets can specify ISD nodes that they would
	/// like PerformDAGCombine callbacks for by calling setTargetDAGCombine() ,	/// like PerformDAGCombine callbacks for by calling setTargetDAGCombine() ,
	/// which sets a bit in this array.	/// which sets a bit in this array.
	unsigned char	unsigned char
	TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];	TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];

	/// PromoteToType - For operations that must be promoted to a specific ty pe,	/// PromoteToType - For operations that must be promoted to a specific ty pe,
	/// this holds the destination type. This map should be sparse, so don't hold	/// this holds the destination type. This map should be sparse, so don't hold
	/// it as an array.	/// it as an array.

End of changes. 45 change blocks.
	62 lines changed or deleted	88 lines changed or added

	TargetLoweringObjectFile.h	TargetLoweringObjectFile.h

	skipping to change at line 18	skipping to change at line 18
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	//	//
	// This file implements classes used to handle lowerings specific to common	// This file implements classes used to handle lowerings specific to common
	// object file formats.	// object file formats.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_TARGET_TARGETLOWERINGOBJECTFILE_H	#ifndef LLVM_TARGET_TARGETLOWERINGOBJECTFILE_H
	#define LLVM_TARGET_TARGETLOWERINGOBJECTFILE_H	#define LLVM_TARGET_TARGETLOWERINGOBJECTFILE_H


	#include "llvm/ADT/StringRef.h"	#include "llvm/Module.h"
	#include "llvm/MC/MCObjectFileInfo.h"	#include "llvm/MC/MCObjectFileInfo.h"
	#include "llvm/MC/SectionKind.h"	#include "llvm/MC/SectionKind.h"

		#include "llvm/ADT/ArrayRef.h"

	namespace llvm {	namespace llvm {
	class MachineModuleInfo;	class MachineModuleInfo;
	class Mangler;	class Mangler;

	class MCAsmInfo;
	class MCContext;	class MCContext;
	class MCExpr;	class MCExpr;
	class MCSection;	class MCSection;

	class MCSectionMachO;
	class MCSymbol;	class MCSymbol;
	class MCStreamer;	class MCStreamer;
	class GlobalValue;	class GlobalValue;
	class TargetMachine;	class TargetMachine;

	class TargetLoweringObjectFile : public MCObjectFileInfo {	class TargetLoweringObjectFile : public MCObjectFileInfo {
	MCContext *Ctx;	MCContext *Ctx;

	TargetLoweringObjectFile(const TargetLoweringObjectFile&); // DO NOT IMPL EMENT	TargetLoweringObjectFile(const TargetLoweringObjectFile&); // DO NOT IMPL EMENT
	void operator=(const TargetLoweringObjectFile&); // DO NOT IMPL EMENT	void operator=(const TargetLoweringObjectFile&); // DO NOT IMPL EMENT

	skipping to change at line 57	skipping to change at line 56

	/// Initialize - this method must be called before any actual lowering is	/// Initialize - this method must be called before any actual lowering is
	/// done. This specifies the current context for codegen, and gives the	/// done. This specifies the current context for codegen, and gives the
	/// lowering implementations a chance to set up their default sections.	/// lowering implementations a chance to set up their default sections.
	virtual void Initialize(MCContext &ctx, const TargetMachine &TM);	virtual void Initialize(MCContext &ctx, const TargetMachine &TM);

	virtual void emitPersonalityValue(MCStreamer &Streamer,	virtual void emitPersonalityValue(MCStreamer &Streamer,
	const TargetMachine &TM,	const TargetMachine &TM,
	const MCSymbol *Sym) const;	const MCSymbol *Sym) const;


		/// emitModuleFlags - Emit the module flags that the platform cares about
		.
		virtual void emitModuleFlags(MCStreamer &,
		ArrayRef<Module::ModuleFlagEntry>,
		Mangler *, const TargetMachine &) const {
		}

	/// shouldEmitUsedDirectiveFor - This hook allows targets to selectively	/// shouldEmitUsedDirectiveFor - This hook allows targets to selectively
	/// decide not to emit the UsedDirective for some symbols in llvm.used.	/// decide not to emit the UsedDirective for some symbols in llvm.used.
	/// FIXME: REMOVE this (rdar://7071300)	/// FIXME: REMOVE this (rdar://7071300)
	virtual bool shouldEmitUsedDirectiveFor(const GlobalValue *GV,	virtual bool shouldEmitUsedDirectiveFor(const GlobalValue *GV,
	Mangler *) const {	Mangler *) const {
	return GV != 0;	return GV != 0;
	}	}

	/// getSectionForConstant - Given a constant with the SectionKind, return a	/// getSectionForConstant - Given a constant with the SectionKind, return a
	/// section that it should be placed in.	/// section that it should be placed in.

	skipping to change at line 123	skipping to change at line 128
	// getCFIPersonalitySymbol - The symbol that gets passed to .cfi_personal ity.	// getCFIPersonalitySymbol - The symbol that gets passed to .cfi_personal ity.
	virtual MCSymbol *	virtual MCSymbol *
	getCFIPersonalitySymbol(const GlobalValue GV, Mangler Mang,	getCFIPersonalitySymbol(const GlobalValue GV, Mangler Mang,
	MachineModuleInfo *MMI) const;	MachineModuleInfo *MMI) const;

	///	///
	const MCExpr *	const MCExpr *
	getExprForDwarfReference(const MCSymbol *Sym, unsigned Encoding,	getExprForDwarfReference(const MCSymbol *Sym, unsigned Encoding,
	MCStreamer &Streamer) const;	MCStreamer &Streamer) const;


		virtual const MCSection *
		getStaticCtorSection(unsigned Priority = 65535) const {
		(void)Priority;
		return StaticCtorSection;
		}
		virtual const MCSection *
		getStaticDtorSection(unsigned Priority = 65535) const {
		(void)Priority;
		return StaticDtorSection;
		}

	protected:	protected:
	virtual const MCSection *	virtual const MCSection *
	SelectSectionForGlobal(const GlobalValue *GV, SectionKind Kind,	SelectSectionForGlobal(const GlobalValue *GV, SectionKind Kind,
	Mangler *Mang, const TargetMachine &TM) const;	Mangler *Mang, const TargetMachine &TM) const;
	};	};

	} // end namespace llvm	} // end namespace llvm

	#endif	#endif

End of changes. 6 change blocks.
	3 lines changed or deleted	20 lines changed or added

	TargetLoweringObjectFileImpl.h	TargetLoweringObjectFileImpl.h

	skipping to change at line 18	skipping to change at line 18
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	//	//
	// This file implements classes used to handle lowerings specific to common	// This file implements classes used to handle lowerings specific to common
	// object file formats.	// object file formats.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_CODEGEN_TARGETLOWERINGOBJECTFILEIMPL_H	#ifndef LLVM_CODEGEN_TARGETLOWERINGOBJECTFILEIMPL_H
	#define LLVM_CODEGEN_TARGETLOWERINGOBJECTFILEIMPL_H	#define LLVM_CODEGEN_TARGETLOWERINGOBJECTFILEIMPL_H


	#include "llvm/ADT/StringRef.h"
	#include "llvm/MC/SectionKind.h"	#include "llvm/MC/SectionKind.h"
	#include "llvm/Target/TargetLoweringObjectFile.h"	#include "llvm/Target/TargetLoweringObjectFile.h"

		#include "llvm/ADT/StringRef.h"

	namespace llvm {	namespace llvm {
	class MachineModuleInfo;	class MachineModuleInfo;
	class Mangler;	class Mangler;
	class MCAsmInfo;	class MCAsmInfo;
	class MCExpr;	class MCExpr;
	class MCSection;	class MCSection;
	class MCSectionMachO;	class MCSectionMachO;
	class MCSymbol;	class MCSymbol;
	class MCContext;	class MCContext;

	skipping to change at line 66	skipping to change at line 66
	///	///
	virtual const MCExpr *	virtual const MCExpr *
	getExprForDwarfGlobalReference(const GlobalValue GV, Mangler Mang,	getExprForDwarfGlobalReference(const GlobalValue GV, Mangler Mang,
	MachineModuleInfo *MMI, unsigned Encoding,	MachineModuleInfo *MMI, unsigned Encoding,
	MCStreamer &Streamer) const;	MCStreamer &Streamer) const;

	// getCFIPersonalitySymbol - The symbol that gets passed to .cfi_personal ity.	// getCFIPersonalitySymbol - The symbol that gets passed to .cfi_personal ity.
	virtual MCSymbol *	virtual MCSymbol *
	getCFIPersonalitySymbol(const GlobalValue GV, Mangler Mang,	getCFIPersonalitySymbol(const GlobalValue GV, Mangler Mang,
	MachineModuleInfo *MMI) const;	MachineModuleInfo *MMI) const;


		virtual const MCSection *
		getStaticCtorSection(unsigned Priority = 65535) const;
		virtual const MCSection *
		getStaticDtorSection(unsigned Priority = 65535) const;
	};	};

	class TargetLoweringObjectFileMachO : public TargetLoweringObjectFile {	class TargetLoweringObjectFileMachO : public TargetLoweringObjectFile {
	public:	public:
	virtual ~TargetLoweringObjectFileMachO() {}	virtual ~TargetLoweringObjectFileMachO() {}


		/// emitModuleFlags - Emit the module flags that specify the garbage
		/// collection information.
		virtual void emitModuleFlags(MCStreamer &Streamer,
		ArrayRef<Module::ModuleFlagEntry> ModuleFlag
		s,
		Mangler *Mang, const TargetMachine &TM) cons
		t;

	virtual const MCSection *	virtual const MCSection *
	SelectSectionForGlobal(const GlobalValue *GV, SectionKind Kind,	SelectSectionForGlobal(const GlobalValue *GV, SectionKind Kind,
	Mangler *Mang, const TargetMachine &TM) const;	Mangler *Mang, const TargetMachine &TM) const;

	virtual const MCSection *	virtual const MCSection *
	getExplicitSectionGlobal(const GlobalValue *GV, SectionKind Kind,	getExplicitSectionGlobal(const GlobalValue *GV, SectionKind Kind,
	Mangler *Mang, const TargetMachine &TM) const;	Mangler *Mang, const TargetMachine &TM) const;

	virtual const MCSection *getSectionForConstant(SectionKind Kind) const;	virtual const MCSection *getSectionForConstant(SectionKind Kind) const;


End of changes. 4 change blocks.
	1 lines changed or deleted	14 lines changed or added

	TargetMachine.h	TargetMachine.h

	//===-- llvm/Target/TargetMachine.h - Target Information --------- C++ --	/*===-- llvm-c/TargetMachine.h - Target Machine Library C Interface - C++ -
	===//	-=\
	//	\|*
	// The LLVM Compiler Infrastructure	*\|
	//	\|* The LLVM Compiler Infrastructure
	// This file is distributed under the University of Illinois Open Source	*\|
	// License. See LICENSE.TXT for details.	\|*
	//	*\|
	//===----------------------------------------------------------------------	\|* This file is distributed under the University of Illinois Open Source
	===//	*\|
	//	\|* License. See LICENSE.TXT for details.
	// This file defines the TargetMachine and LLVMTargetMachine classes.	*\|
	//	\|*
	//===----------------------------------------------------------------------	*\|
	===//	\|*===----------------------------------------------------------------------
		===*\|
	#ifndef LLVM_TARGET_TARGETMACHINE_H	\|*
	#define LLVM_TARGET_TARGETMACHINE_H	*\|
		\|* This header declares the C interface to the Target and TargetMachine
	#include "llvm/MC/MCCodeGenInfo.h"	*\|
	#include "llvm/ADT/StringRef.h"	\|* classes, which can be used to generate assembly or object files.
	#include <cassert>	*\|
	#include <string>	\|*
		*\|
		\|* Many exotic languages can interoperate with C code but have a harder tim
		e *\|
		\|* with C++ due to name mangling. So in addition to C, this interface enabl
		es *\|
		\|* tools written in such languages.
		*\|
		\|*
		*\|
		\*===----------------------------------------------------------------------
		===*/


	namespace llvm {	#ifndef LLVM_C_TARGETMACHINE_H
		#define LLVM_C_TARGETMACHINE_H
	class InstrItineraryData;
	class JITCodeEmitter;
	class MCAsmInfo;
	class MCCodeGenInfo;
	class MCContext;
	class Pass;
	class PassManager;
	class PassManagerBase;
	class Target;
	class TargetData;
	class TargetELFWriterInfo;
	class TargetFrameLowering;
	class TargetInstrInfo;
	class TargetIntrinsicInfo;
	class TargetJITInfo;
	class TargetLowering;
	class TargetRegisterInfo;
	class TargetSelectionDAGInfo;
	class TargetSubtargetInfo;
	class formatted_raw_ostream;
	class raw_ostream;

	// Code generation optimization level.
	namespace CodeGenOpt {
	enum Level {
	None, // -O0
	Less, // -O1
	Default, // -O2, -Os
	Aggressive // -O3
	};
	}


	namespace Sched {	#include "llvm-c/Core.h"
	enum Preference {
	None, // No preference
	Latency, // Scheduling for shortest total latency.
	RegPressure, // Scheduling for lowest register pressure.
	Hybrid, // Scheduling for both latency and register pressure.
	ILP // Scheduling for ILP in low register pressure mode.
	};
	}


	//===----------------------------------------------------------------------	#ifdef __cplusplus
	===//	extern "C" {
	///	#endif
	/// TargetMachine - Primary interface to the complete machine description f	typedef struct LLVMTargetMachine *LLVMTargetMachineRef;
	or	typedef struct LLVMTarget *LLVMTargetRef;
	/// the target machine. All target-specific information should be accessib
	le
	/// through this interface.
	///
	class TargetMachine {
	TargetMachine(const TargetMachine &); // DO NOT IMPLEMENT
	void operator=(const TargetMachine &); // DO NOT IMPLEMENT
	protected: // Can only create subclasses.
	TargetMachine(const Target &T, StringRef TargetTriple,
	StringRef CPU, StringRef FS);

	/// getSubtargetImpl - virtual method implemented by subclasses that retu
	rns
	/// a reference to that target's TargetSubtargetInfo-derived member varia
	ble.
	virtual const TargetSubtargetInfo *getSubtargetImpl() const { return 0; }

	/// TheTarget - The Target that this machine was created for.
	const Target &TheTarget;

	/// TargetTriple, TargetCPU, TargetFS - Triple string, CPU name, and targ
	et
	/// feature strings the TargetMachine instance is created with.
	std::string TargetTriple;
	std::string TargetCPU;
	std::string TargetFS;

	/// CodeGenInfo - Low level target information such as relocation model.
	const MCCodeGenInfo *CodeGenInfo;

	/// AsmInfo - Contains target specific asm information.
	///
	const MCAsmInfo *AsmInfo;

	unsigned MCRelaxAll : 1;
	unsigned MCNoExecStack : 1;
	unsigned MCSaveTempLabels : 1;
	unsigned MCUseLoc : 1;
	unsigned MCUseCFI : 1;

	public:
	virtual ~TargetMachine();

	const Target &getTarget() const { return TheTarget; }

	const StringRef getTargetTriple() const { return TargetTriple; }
	const StringRef getTargetCPU() const { return TargetCPU; }
	const StringRef getTargetFeatureString() const { return TargetFS; }

	// Interfaces to the major aspects of target machine information:
	// -- Instruction opcode and operand information
	// -- Pipelines and scheduling information
	// -- Stack frame information
	// -- Selection DAG lowering information
	//
	virtual const TargetInstrInfo *getInstrInfo() const { return 0; }
	virtual const TargetFrameLowering *getFrameLowering() const { return 0; }
	virtual const TargetLowering *getTargetLowering() const { return 0; }
	virtual const TargetSelectionDAGInfo *getSelectionDAGInfo() const{ return
	0; }
	virtual const TargetData *getTargetData() const { return 0; }

	/// getMCAsmInfo - Return target specific asm information.
	///
	const MCAsmInfo *getMCAsmInfo() const { return AsmInfo; }

	/// getSubtarget - This method returns a pointer to the specified type of
	/// TargetSubtargetInfo. In debug builds, it verifies that the object be
	ing
	/// returned is of the correct type.
	template<typename STC> const STC &getSubtarget() const {
	return static_cast<const STC>(getSubtargetImpl());
	}

	/// getRegisterInfo - If register information is available, return it. I
	f
	/// not, return null. This is kept separate from RegInfo until RegInfo h
	as
	/// details of graph coloring register allocation removed from it.
	///
	virtual const TargetRegisterInfo *getRegisterInfo() const { return 0; }

	/// getIntrinsicInfo - If intrinsic information is available, return it.
	If
	/// not, return null.
	///
	virtual const TargetIntrinsicInfo *getIntrinsicInfo() const { return 0; }

	/// getJITInfo - If this target supports a JIT, return information for it
	,
	/// otherwise return null.
	///
	virtual TargetJITInfo *getJITInfo() { return 0; }

	/// getInstrItineraryData - Returns instruction itinerary data for the ta
	rget
	/// or specific subtarget.
	///
	virtual const InstrItineraryData *getInstrItineraryData() const {
	return 0;
	}

	/// getELFWriterInfo - If this target supports an ELF writer, return
	/// information for it, otherwise return null.
	///
	virtual const TargetELFWriterInfo *getELFWriterInfo() const { return 0; }

	/// hasMCRelaxAll - Check whether all machine code instructions should be
	/// relaxed.
	bool hasMCRelaxAll() const { return MCRelaxAll; }

	/// setMCRelaxAll - Set whether all machine code instructions should be
	/// relaxed.
	void setMCRelaxAll(bool Value) { MCRelaxAll = Value; }

	/// hasMCSaveTempLabels - Check whether temporary labels will be preserve
	d
	/// (i.e., not treated as temporary).
	bool hasMCSaveTempLabels() const { return MCSaveTempLabels; }

	/// setMCSaveTempLabels - Set whether temporary labels will be preserved
	/// (i.e., not treated as temporary).
	void setMCSaveTempLabels(bool Value) { MCSaveTempLabels = Value; }

	/// hasMCNoExecStack - Check whether an executable stack is not needed.
	bool hasMCNoExecStack() const { return MCNoExecStack; }

	/// setMCNoExecStack - Set whether an executabel stack is not needed.
	void setMCNoExecStack(bool Value) { MCNoExecStack = Value; }

	/// hasMCUseLoc - Check whether we should use dwarf's .loc directive.
	bool hasMCUseLoc() const { return MCUseLoc; }

	/// setMCUseLoc - Set whether all we should use dwarf's .loc directive.
	void setMCUseLoc(bool Value) { MCUseLoc = Value; }

	/// hasMCUseCFI - Check whether we should use dwarf's .cfi_* directives.
	bool hasMCUseCFI() const { return MCUseCFI; }

	/// setMCUseCFI - Set whether all we should use dwarf's .cfi_* directives
	.
	void setMCUseCFI(bool Value) { MCUseCFI = Value; }

	/// getRelocationModel - Returns the code generation relocation model. Th
	e
	/// choices are static, PIC, and dynamic-no-pic, and target default.
	Reloc::Model getRelocationModel() const;

	/// getCodeModel - Returns the code model. The choices are small, kernel,
	/// medium, large, and target default.
	CodeModel::Model getCodeModel() const;

	/// getAsmVerbosityDefault - Returns the default value of asm verbosity.
	///
	static bool getAsmVerbosityDefault();

	/// setAsmVerbosityDefault - Set the default value of asm verbosity. Defa
	ult
	/// is false.
	static void setAsmVerbosityDefault(bool);

	/// getDataSections - Return true if data objects should be emitted into
	their
	/// own section, corresponds to -fdata-sections.
	static bool getDataSections();

	/// getFunctionSections - Return true if functions should be emitted into
	/// their own section, corresponding to -ffunction-sections.
	static bool getFunctionSections();

	/// setDataSections - Set if the data are emit into separate sections.
	static void setDataSections(bool);

	/// setFunctionSections - Set if the functions are emit into separate
	/// sections.
	static void setFunctionSections(bool);

	/// CodeGenFileType - These enums are meant to be passed into
	/// addPassesToEmitFile to indicate what type of file to emit, and return
	ed by
	/// it to indicate what type of file could actually be made.
	enum CodeGenFileType {
	CGFT_AssemblyFile,
	CGFT_ObjectFile,
	CGFT_Null // Do not emit any output.
	};

	/// getEnableTailMergeDefault - the default setting for -enable-tail-merg
	e
	/// on this target. User flag overrides.
	virtual bool getEnableTailMergeDefault() const { return true; }

	/// addPassesToEmitFile - Add passes to the specified pass manager to get
	the
	/// specified file emitted. Typically this will involve several steps of
	code
	/// generation. This method should return true if emission of this file
	type
	/// is not supported, or false on success.
	virtual bool addPassesToEmitFile(PassManagerBase &,
	formatted_raw_ostream &,
	CodeGenFileType,
	CodeGenOpt::Level,
	bool = true) {
	return true;
	}

	/// addPassesToEmitMachineCode - Add passes to the specified pass manager
	to
	/// get machine code emitted. This uses a JITCodeEmitter object to handl
	e
	/// actually outputting the machine code and resolving things like the ad
	dress
	/// of functions. This method returns true if machine code emission is
	/// not supported.
	///
	virtual bool addPassesToEmitMachineCode(PassManagerBase &,
	JITCodeEmitter &,
	CodeGenOpt::Level,
	bool = true) {
	return true;
	}

	/// addPassesToEmitMC - Add passes to the specified pass manager to get
	/// machine code emitted with the MCJIT. This method returns true if mach
	ine
	/// code is not supported. It fills the MCContext Ctx pointer which can b
	e
	/// used to build custom MCStreamer.
	///
	virtual bool addPassesToEmitMC(PassManagerBase &,
	MCContext *&,
	raw_ostream &,
	CodeGenOpt::Level,
	bool = true) {
	return true;
	}
	};


	/// LLVMTargetMachine - This class describes a target machine that is	typedef enum {
	/// implemented with the LLVM target-independent code generator.	LLVMCodeGenLevelNone,
	///	LLVMCodeGenLevelLess,
	class LLVMTargetMachine : public TargetMachine {	LLVMCodeGenLevelDefault,
	protected: // Can only create subclasses.	LLVMCodeGenLevelAggressive
	LLVMTargetMachine(const Target &T, StringRef TargetTriple,	} LLVMCodeGenOptLevel;
	StringRef CPU, StringRef FS,
	Reloc::Model RM, CodeModel::Model CM);	typedef enum {
		LLVMRelocDefault,
	private:	LLVMRelocStatic,
	/// addCommonCodeGenPasses - Add standard LLVM codegen passes used for	LLVMRelocPIC,
	/// both emitting to assembly files or machine code output.	LLVMRelocDynamicNoPic
	///	} LLVMRelocMode;
	bool addCommonCodeGenPasses(PassManagerBase &, CodeGenOpt::Level,
	bool DisableVerify, MCContext *&OutCtx);	typedef enum {
		LLVMCodeModelDefault,
	public:	LLVMCodeModelJITDefault,
	/// addPassesToEmitFile - Add passes to the specified pass manager to get	LLVMCodeModelSmall,
	the	LLVMCodeModelKernel,
	/// specified file emitted. Typically this will involve several steps of	LLVMCodeModelMedium,
	code	LLVMCodeModelLarge
	/// generation. If OptLevel is None, the code generator should emit code	} LLVMCodeModel;
	as
	/// fast as possible, though the generated code may be less efficient.	typedef enum {
	virtual bool addPassesToEmitFile(PassManagerBase &PM,	LLVMAssemblyFile,
	formatted_raw_ostream &Out,	LLVMObjectFile
	CodeGenFileType FileType,	} LLVMCodeGenFileType;
	CodeGenOpt::Level,
	bool DisableVerify = true);	/** Returns the first llvm::Target in the registered targets list. */
		LLVMTargetRef LLVMGetFirstTarget();
	/// addPassesToEmitMachineCode - Add passes to the specified pass manager	/** Returns the next llvm::Target given a previous one (or null if there's
	to	none) */
	/// get machine code emitted. This uses a JITCodeEmitter object to handl	LLVMTargetRef LLVMGetNextTarget(LLVMTargetRef T);
	e
	/// actually outputting the machine code and resolving things like the ad	/*===-- Target ------------------------------------------------------------
	dress	===*/
	/// of functions. This method returns true if machine code emission is	/** Returns the name of a target. See llvm::Target::getName */
	/// not supported.	const char *LLVMGetTargetName(LLVMTargetRef T);
	///
	virtual bool addPassesToEmitMachineCode(PassManagerBase &PM,	/** Returns the description of a target. See llvm::Target::getDescription
	JITCodeEmitter &MCE,	*/
	CodeGenOpt::Level,	const char *LLVMGetTargetDescription(LLVMTargetRef T);
	bool DisableVerify = true);
		/** Returns if the target has a JIT */
	/// addPassesToEmitMC - Add passes to the specified pass manager to get	LLVMBool LLVMTargetHasJIT(LLVMTargetRef T);
	/// machine code emitted with the MCJIT. This method returns true if mach
	ine	/** Returns if the target has a TargetMachine associated */
	/// code is not supported. It fills the MCContext Ctx pointer which can b	LLVMBool LLVMTargetHasTargetMachine(LLVMTargetRef T);
	e
	/// used to build custom MCStreamer.	/** Returns if the target as an ASM backend (required for emitting output)
	///	*/
	virtual bool addPassesToEmitMC(PassManagerBase &PM,	LLVMBool LLVMTargetHasAsmBackend(LLVMTargetRef T);
	MCContext *&Ctx,
	raw_ostream &OS,	/*===-- Target Machine ----------------------------------------------------
	CodeGenOpt::Level OptLevel,	===*/
	bool DisableVerify = true);	/** Creates a new llvm::TargetMachine. See llvm::Target::createTargetMachin
		e */
	/// Target-Independent Code Generator Pass Configuration Options.	LLVMTargetMachineRef LLVMCreateTargetMachine(LLVMTargetRef T, char *Triple,
		char CPU, char Features, LLVMCodeGenOptLevel Level, LLVMRelocMode Reloc
	/// addPreISelPasses - This method should add any "last minute" LLVM->LLV	,
	M	LLVMCodeModel CodeModel);
	/// passes (which are run just before instruction selector).
	virtual bool addPreISel(PassManagerBase &, CodeGenOpt::Level) {	/** Dispose the LLVMTargetMachineRef instance generated by
	return true;	LLVMCreateTargetMachine. */
	}	void LLVMDisposeTargetMachine(LLVMTargetMachineRef T);

		/** Returns the Target used in a TargetMachine */
		LLVMTargetRef LLVMGetTargetMachineTarget(LLVMTargetMachineRef T);

		/** Returns the triple used creating this target machine. See
		llvm::TargetMachine::getTriple. The result needs to be disposed with
		LLVMDisposeMessage. */
		char *LLVMGetTargetMachineTriple(LLVMTargetMachineRef T);

		/** Returns the cpu used creating this target machine. See
		llvm::TargetMachine::getCPU. The result needs to be disposed with
		LLVMDisposeMessage. */
		char *LLVMGetTargetMachineCPU(LLVMTargetMachineRef T);

		/** Returns the feature string used creating this target machine. See
		llvm::TargetMachine::getFeatureString. The result needs to be disposed wi
		th
		LLVMDisposeMessage. */
		char *LLVMGetTargetMachineFeatureString(LLVMTargetMachineRef T);

		/** Returns the llvm::TargetData used for this llvm:TargetMachine. */
		LLVMTargetDataRef LLVMGetTargetMachineData(LLVMTargetMachineRef T);

		/** Emits an asm or object file for the given module to the filename. This
		wraps several c++ only classes (among them a file stream). Returns any
		error in ErrorMessage. Use LLVMDisposeMessage to dispose the message. */
		LLVMBool LLVMTargetMachineEmitToFile(LLVMTargetMachineRef T, LLVMModuleRef
		M,
		char Filename, LLVMCodeGenFileType codegen, char *ErrorMessage);


	/// addInstSelector - This method should install an instruction selector	#ifdef __cplusplus
	pass,	}
	/// which converts from LLVM code to machine instructions.
	virtual bool addInstSelector(PassManagerBase &, CodeGenOpt::Level) {
	return true;
	}


	/// addPreRegAlloc - This method may be implemented by targets that want	namespace llvm {
	to	class TargetMachine;
	/// run passes immediately before register allocation. This should return	class Target;
	/// true if -print-machineinstrs should print after these passes.
	virtual bool addPreRegAlloc(PassManagerBase &, CodeGenOpt::Level) {
	return false;
	}


	/// addPostRegAlloc - This method may be implemented by targets that want	inline TargetMachine *unwrap(LLVMTargetMachineRef P) {
	/// to run passes after register allocation but before prolog-epilog	return reinterpret_cast<TargetMachine*>(P);
	/// insertion. This should return true if -print-machineinstrs should pr
	int
	/// after these passes.
	virtual bool addPostRegAlloc(PassManagerBase &, CodeGenOpt::Level) {
	return false;
	}	}

		inline Target *unwrap(LLVMTargetRef P) {
	/// addPreSched2 - This method may be implemented by targets that want to	return reinterpret_cast<Target*>(P);
	/// run passes after prolog-epilog insertion and before the second instru
	ction
	/// scheduling pass. This should return true if -print-machineinstrs sho
	uld
	/// print after these passes.
	virtual bool addPreSched2(PassManagerBase &, CodeGenOpt::Level) {
	return false;
	}	}

		inline LLVMTargetMachineRef wrap(const TargetMachine *P) {
	/// addPreEmitPass - This pass may be implemented by targets that want to	return reinterpret_cast<LLVMTargetMachineRef>(
	run	const_cast<TargetMachine*>(P));
	/// passes immediately before machine code is emitted. This should retur
	n
	/// true if -print-machineinstrs should print out the code after the pass
	es.
	virtual bool addPreEmitPass(PassManagerBase &, CodeGenOpt::Level) {
	return false;
	}	}

		inline LLVMTargetRef wrap(const Target * P) {
	/// addCodeEmitter - This pass should be overridden by the target to add	return reinterpret_cast<LLVMTargetRef>(const_cast<Target*>(P));
	a
	/// code emitter, if supported. If this is not supported, 'true' should
	be
	/// returned.
	virtual bool addCodeEmitter(PassManagerBase &, CodeGenOpt::Level,
	JITCodeEmitter &) {
	return true;
	}	}

		}
	/// getEnableTailMergeDefault - the default setting for -enable-tail-merg	#endif
	e
	/// on this target. User flag overrides.
	virtual bool getEnableTailMergeDefault() const { return true; }
	};

	} // End llvm namespace

	#endif	#endif

End of changes. 12 change blocks.
	428 lines changed or deleted	152 lines changed or added

	TargetOpcodes.h	TargetOpcodes.h

	skipping to change at line 85	skipping to change at line 85
	// the REG_SEQUENCE, while each subsequent pair names a vreg + subreg i ndex	// the REG_SEQUENCE, while each subsequent pair names a vreg + subreg i ndex
	// pair. Once it has been lowered to a MachineInstr, the regclass oper and	// pair. Once it has been lowered to a MachineInstr, the regclass oper and
	// is no longer present.	// is no longer present.
	/// e.g. v1027 = REG_SEQUENCE v1024, 3, v1025, 4, v1026, 5	/// e.g. v1027 = REG_SEQUENCE v1024, 3, v1025, 4, v1026, 5
	/// After register coalescing references of v1024 should be replace wit h	/// After register coalescing references of v1024 should be replace wit h
	/// v1027:3, v1025 with v1027:4, etc.	/// v1027:3, v1025 with v1027:4, etc.
	REG_SEQUENCE = 12,	REG_SEQUENCE = 12,

	/// COPY - Target-independent register copy. This instruction can also be	/// COPY - Target-independent register copy. This instruction can also be
	/// used to copy between subregisters of virtual registers.	/// used to copy between subregisters of virtual registers.

	COPY = 13	COPY = 13,

		/// BUNDLE - This instruction represents an instruction bundle. Instruc
		tions
		/// which immediately follow a BUNDLE instruction which are marked with
		/// 'InsideBundle' flag are inside the bundle.
		BUNDLE
	};	};
	} // end namespace TargetOpcode	} // end namespace TargetOpcode
	} // end namespace llvm	} // end namespace llvm

	#endif	#endif

End of changes. 1 change blocks.
	1 lines changed or deleted	7 lines changed or added

	TargetOptions.h	TargetOptions.h

	skipping to change at line 18	skipping to change at line 18
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	//	//
	// This file defines command line option flags that are shared across vario us	// This file defines command line option flags that are shared across vario us
	// targets.	// targets.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_TARGET_TARGETOPTIONS_H	#ifndef LLVM_TARGET_TARGETOPTIONS_H
	#define LLVM_TARGET_TARGETOPTIONS_H	#define LLVM_TARGET_TARGETOPTIONS_H


		#include <string>

	namespace llvm {	namespace llvm {
	class MachineFunction;	class MachineFunction;

		class StringRef;

	// Possible float ABI settings. Used with FloatABIType in TargetOptions.h .	// Possible float ABI settings. Used with FloatABIType in TargetOptions.h .
	namespace FloatABI {	namespace FloatABI {
	enum ABIType {	enum ABIType {

	Default, // Target-specific (either soft of hard depending on triple, etc).	Default, // Target-specific (either soft or hard depending on triple, etc).
	Soft, // Soft float.	Soft, // Soft float.
	Hard // Hard float.	Hard // Hard float.
	};	};
	}	}


	/// PrintMachineCode - This flag is enabled when the -print-machineinstrs	class TargetOptions {
	/// option is specified on the command line, and should enable debugging	public:
	/// output from the code generator.	TargetOptions()
	extern bool PrintMachineCode;	: PrintMachineCode(false), NoFramePointerElim(false),
		NoFramePointerElimNonLeaf(false), LessPreciseFPMADOption(false),
	/// NoFramePointerElim - This flag is enabled when the -disable-fp-elim i	NoExcessFPPrecision(false), UnsafeFPMath(false), NoInfsFPMath(fal
	s	se),
	/// specified on the command line. If the target supports the frame poin	NoNaNsFPMath(false), HonorSignDependentRoundingFPMathOption(false
	ter	),
	/// elimination optimization, this option should disable it.	UseSoftFloat(false), NoZerosInBSS(false), JITExceptionHandling(fa
	extern bool NoFramePointerElim;	lse),
		JITEmitDebugInfo(false), JITEmitDebugInfoToDisk(false),
	/// NoFramePointerElimNonLeaf - This flag is enabled when the	GuaranteedTailCallOpt(false), DisableTailCalls(false),
	/// -disable-non-leaf-fp-elim is specified on the command line. If the ta	StackAlignmentOverride(0), RealignStack(true),
	rget	DisableJumpTables(false), EnableFastISel(false),
	/// supports the frame pointer elimination optimization, this option shou	PositionIndependentExecutable(false), EnableSegmentedStacks(false
	ld	),
	/// disable it for non-leaf functions.	TrapFuncName(""), FloatABIType(FloatABI::Default)
	extern bool NoFramePointerElimNonLeaf;	{}

	/// DisableFramePointerElim - This returns true if frame pointer eliminat	/// PrintMachineCode - This flag is enabled when the -print-machineinst
	ion	rs
	/// optimization should be disabled for the given machine function.	/// option is specified on the command line, and should enable debuggin
	extern bool DisableFramePointerElim(const MachineFunction &MF);	g
		/// output from the code generator.
	/// LessPreciseFPMAD - This flag is enabled when the	unsigned PrintMachineCode : 1;
	/// -enable-fp-mad is specified on the command line. When this flag is o
	ff	/// NoFramePointerElim - This flag is enabled when the -disable-fp-elim
	/// (the default), the code generator is not allowed to generate mad	is
	/// (multiply add) if the result is "less precise" than doing those opera	/// specified on the command line. If the target supports the frame po
	tions	inter
	/// individually.	/// elimination optimization, this option should disable it.
	extern bool LessPreciseFPMADOption;	unsigned NoFramePointerElim : 1;
	extern bool LessPreciseFPMAD();
		/// NoFramePointerElimNonLeaf - This flag is enabled when the
	/// NoExcessFPPrecision - This flag is enabled when the	/// -disable-non-leaf-fp-elim is specified on the command line. If the
	/// -disable-excess-fp-precision flag is specified on the command line.	/// target supports the frame pointer elimination optimization, this op
	When	tion
	/// this flag is off (the default), the code generator is allowed to prod	/// should disable it for non-leaf functions.
	uce	unsigned NoFramePointerElimNonLeaf : 1;
	/// results that are "more precise" than IEEE allows. This includes use
	of	/// DisableFramePointerElim - This returns true if frame pointer elimin
	/// FMA-like operations and use of the X86 FP registers without rounding	ation
	all	/// optimization should be disabled for the given machine function.
	/// over the place.	bool DisableFramePointerElim(const MachineFunction &MF) const;
	extern bool NoExcessFPPrecision;
		/// LessPreciseFPMAD - This flag is enabled when the
	/// UnsafeFPMath - This flag is enabled when the	/// -enable-fp-mad is specified on the command line. When this flag is
	/// -enable-unsafe-fp-math flag is specified on the command line. When	off
	/// this flag is off (the default), the code generator is not allowed to	/// (the default), the code generator is not allowed to generate mad
	/// produce results that are "less precise" than IEEE allows. This inclu	/// (multiply add) if the result is "less precise" than doing those
	des	/// operations individually.
	/// use of X86 instructions like FSIN and FCOS instead of libcalls.	unsigned LessPreciseFPMADOption : 1;
	/// UnsafeFPMath implies LessPreciseFPMAD.	bool LessPreciseFPMAD() const;
	extern bool UnsafeFPMath;
		/// NoExcessFPPrecision - This flag is enabled when the
	/// NoInfsFPMath - This flag is enabled when the	/// -disable-excess-fp-precision flag is specified on the command line.
	/// -enable-no-infs-fp-math flag is specified on the command line. When	/// When this flag is off (the default), the code generator is allowed
	/// this flag is off (the default), the code generator is not allowed to	to
	/// assume the FP arithmetic arguments and results are never +-Infs.	/// produce results that are "more precise" than IEEE allows. This inc
	extern bool NoInfsFPMath;	ludes
		/// use of FMA-like operations and use of the X86 FP registers without
	/// NoNaNsFPMath - This flag is enabled when the	/// rounding all over the place.
	/// -enable-no-nans-fp-math flag is specified on the command line. When	unsigned NoExcessFPPrecision : 1;
	/// this flag is off (the default), the code generator is not allowed to
	/// assume the FP arithmetic arguments and results are never NaNs.	/// UnsafeFPMath - This flag is enabled when the
	extern bool NoNaNsFPMath;	/// -enable-unsafe-fp-math flag is specified on the command line. When
		/// this flag is off (the default), the code generator is not allowed t
	/// HonorSignDependentRoundingFPMath - This returns true when the	o
	/// -enable-sign-dependent-rounding-fp-math is specified. If this return	/// produce results that are "less precise" than IEEE allows. This inc
	s	ludes
	/// false (the default), the code generator is allowed to assume that the	/// use of X86 instructions like FSIN and FCOS instead of libcalls.
	/// rounding behavior is the default (round-to-zero for all floating poin	/// UnsafeFPMath implies LessPreciseFPMAD.
	t to	unsigned UnsafeFPMath : 1;
	/// integer conversions, and round-to-nearest for all other arithmetic
	/// truncations). If this is enabled (set to true), the code generator m	/// NoInfsFPMath - This flag is enabled when the
	ust	/// -enable-no-infs-fp-math flag is specified on the command line. When
	/// assume that the rounding mode may dynamically change.	/// this flag is off (the default), the code generator is not allowed t
	extern bool HonorSignDependentRoundingFPMathOption;	o
	extern bool HonorSignDependentRoundingFPMath();	/// assume the FP arithmetic arguments and results are never +-Infs.
		unsigned NoInfsFPMath : 1;
	/// UseSoftFloat - This flag is enabled when the -soft-float flag is spec
	ified	/// NoNaNsFPMath - This flag is enabled when the
	/// on the command line. When this flag is on, the code generator will	/// -enable-no-nans-fp-math flag is specified on the command line. When
	/// generate libcalls to the software floating point library instead of	/// this flag is off (the default), the code generator is not allowed t
	/// target FP instructions.	o
	extern bool UseSoftFloat;	/// assume the FP arithmetic arguments and results are never NaNs.
		unsigned NoNaNsFPMath : 1;
	/// FloatABIType - This setting is set by -float-abi=xxx option is specfi
	ed	/// HonorSignDependentRoundingFPMath - This returns true when the
	/// on the command line. This setting may either be Default, Soft, or Har	/// -enable-sign-dependent-rounding-fp-math is specified. If this retu
	d.	rns
	/// Default selects the target's default behavior. Soft selects the ABI f	/// false (the default), the code generator is allowed to assume that t
	or	he
	/// UseSoftFloat, but does not inidcate that FP hardware may not be used.	/// rounding behavior is the default (round-to-zero for all floating po
	/// Such a combination is unfortunately popular (e.g. arm-apple-darwin).	int
	/// Hard presumes that the normal FP ABI is used.	/// to integer conversions, and round-to-nearest for all other arithmet
	extern FloatABI::ABIType FloatABIType;	ic
		/// truncations). If this is enabled (set to true), the code generator
	/// NoZerosInBSS - By default some codegens place zero-initialized data t	must
	o	/// assume that the rounding mode may dynamically change.
	/// .bss section. This flag disables such behaviour (necessary, e.g. for	unsigned HonorSignDependentRoundingFPMathOption : 1;
	/// crt*.o compiling).	bool HonorSignDependentRoundingFPMath() const;
	extern bool NoZerosInBSS;
		/// UseSoftFloat - This flag is enabled when the -soft-float flag is
	/// JITExceptionHandling - This flag indicates that the JIT should emit	/// specified on the command line. When this flag is on, the code gene
	/// exception handling information.	rator
	extern bool JITExceptionHandling;	/// will generate libcalls to the software floating point library inste
		ad of
	/// JITEmitDebugInfo - This flag indicates that the JIT should try to emi	/// target FP instructions.
	t	unsigned UseSoftFloat : 1;
	/// debug information and notify a debugger about it.
	extern bool JITEmitDebugInfo;	/// NoZerosInBSS - By default some codegens place zero-initialized data
		to
	/// JITEmitDebugInfoToDisk - This flag indicates that the JIT should writ	/// .bss section. This flag disables such behaviour (necessary, e.g. fo
	e	r
	/// the object files generated by the JITEmitDebugInfo flag to disk. Thi	/// crt*.o compiling).
	s	unsigned NoZerosInBSS : 1;
	/// flag is hidden and is only for debugging the debug info.
	extern bool JITEmitDebugInfoToDisk;	/// JITExceptionHandling - This flag indicates that the JIT should emit
		/// exception handling information.
	/// GuaranteedTailCallOpt - This flag is enabled when -tailcallopt is	unsigned JITExceptionHandling : 1;
	/// specified on the commandline. When the flag is on, participating targ
	ets	/// JITEmitDebugInfo - This flag indicates that the JIT should try to e
	/// will perform tail call optimization on all calls which use the fastcc	mit
	/// calling convention and which satisfy certain target-independent	/// debug information and notify a debugger about it.
	/// criteria (being at the end of a function, having the same return type	unsigned JITEmitDebugInfo : 1;
	/// as their parent function, etc.), using an alternate ABI if necessary.
	extern bool GuaranteedTailCallOpt;	/// JITEmitDebugInfoToDisk - This flag indicates that the JIT should wr
		ite
	/// StackAlignmentOverride - Override default stack alignment for target.	/// the object files generated by the JITEmitDebugInfo flag to disk. T
	extern unsigned StackAlignmentOverride;	his
		/// flag is hidden and is only for debugging the debug info.
	/// RealignStack - This flag indicates whether the stack should be	unsigned JITEmitDebugInfoToDisk : 1;
	/// automatically realigned, if needed.
	extern bool RealignStack;	/// GuaranteedTailCallOpt - This flag is enabled when -tailcallopt is
		/// specified on the commandline. When the flag is on, participating ta
	/// DisableJumpTables - This flag indicates jump tables should not be	rgets
	/// generated.	/// will perform tail call optimization on all calls which use the fast
	extern bool DisableJumpTables;	cc
		/// calling convention and which satisfy certain target-independent
	/// EnableFastISel - This flag enables fast-path instruction selection	/// criteria (being at the end of a function, having the same return ty
	/// which trades away generated code quality in favor of reducing	pe
	/// compile time.	/// as their parent function, etc.), using an alternate ABI if necessar
	extern bool EnableFastISel;	y.
		unsigned GuaranteedTailCallOpt : 1;
	/// StrongPHIElim - This flag enables more aggressive PHI elimination
	/// wth earlier copy coalescing.	/// DisableTailCalls - This flag controls whether we will use tail call
	extern bool StrongPHIElim;	s.
		/// Disabling them may be useful to maintain a correct call stack.
	/// getTrapFunctionName - If this returns a non-empty string, this means	unsigned DisableTailCalls : 1;
	isel
	/// should lower Intrinsic::trap to a call to the specified function name	/// StackAlignmentOverride - Override default stack alignment for targe
	/// instead of an ISD::TRAP node.	t.
	extern StringRef getTrapFunctionName();	unsigned StackAlignmentOverride;

	extern bool EnableSegmentedStacks;	/// RealignStack - This flag indicates whether the stack should be
		/// automatically realigned, if needed.
		unsigned RealignStack : 1;

		/// DisableJumpTables - This flag indicates jump tables should not be
		/// generated.
		unsigned DisableJumpTables : 1;

		/// EnableFastISel - This flag enables fast-path instruction selection
		/// which trades away generated code quality in favor of reducing
		/// compile time.
		unsigned EnableFastISel : 1;

		/// PositionIndependentExecutable - This flag indicates whether the cod
		e
		/// will eventually be linked into a single executable, despite the PIC
		/// relocation model being in use. It's value is undefined (and irrelev
		ant)
		/// if the relocation model is anything other than PIC.
		unsigned PositionIndependentExecutable : 1;

		unsigned EnableSegmentedStacks : 1;

		/// getTrapFunctionName - If this returns a non-empty string, this mean
		s
		/// isel should lower Intrinsic::trap to a call to the specified functi
		on
		/// name instead of an ISD::TRAP node.
		std::string TrapFuncName;
		StringRef getTrapFunctionName() const;

		/// FloatABIType - This setting is set by -float-abi=xxx option is spec
		fied
		/// on the command line. This setting may either be Default, Soft, or H
		ard.
		/// Default selects the target's default behavior. Soft selects the ABI
		for
		/// UseSoftFloat, but does not indicate that FP hardware may not be use
		d.
		/// Such a combination is unfortunately popular (e.g. arm-apple-darwin)
		.
		/// Hard presumes that the normal FP ABI is used.
		FloatABI::ABIType FloatABIType;
		};
	} // End llvm namespace	} // End llvm namespace

	#endif	#endif

End of changes. 4 change blocks.
	159 lines changed or deleted	204 lines changed or added

	TargetRegisterInfo.h	TargetRegisterInfo.h

	skipping to change at line 23	skipping to change at line 23
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_TARGET_TARGETREGISTERINFO_H	#ifndef LLVM_TARGET_TARGETREGISTERINFO_H
	#define LLVM_TARGET_TARGETREGISTERINFO_H	#define LLVM_TARGET_TARGETREGISTERINFO_H

	#include "llvm/MC/MCRegisterInfo.h"	#include "llvm/MC/MCRegisterInfo.h"
	#include "llvm/CodeGen/MachineBasicBlock.h"	#include "llvm/CodeGen/MachineBasicBlock.h"
	#include "llvm/CodeGen/ValueTypes.h"	#include "llvm/CodeGen/ValueTypes.h"
	#include "llvm/ADT/ArrayRef.h"	#include "llvm/ADT/ArrayRef.h"

		#include "llvm/CallingConv.h"
	#include <cassert>	#include <cassert>
	#include <functional>	#include <functional>

	namespace llvm {	namespace llvm {

	class BitVector;	class BitVector;
	class MachineFunction;	class MachineFunction;
	class RegScavenger;	class RegScavenger;
	template<class T> class SmallVectorImpl;	template<class T> class SmallVectorImpl;
	class raw_ostream;	class raw_ostream;

	class TargetRegisterClass {	class TargetRegisterClass {
	public:	public:

	typedef const unsigned* iterator;	typedef const uint16_t* iterator;
	typedef const unsigned* const_iterator;	typedef const uint16_t* const_iterator;
	typedef const EVT* vt_iterator;	typedef const MVT::SimpleValueType* vt_iterator;
	typedef const TargetRegisterClass* const * sc_iterator;	typedef const TargetRegisterClass* const * sc_iterator;

	private:
		// Instance variables filled by tablegen, do not use!
	const MCRegisterClass *MC;	const MCRegisterClass *MC;
	const vt_iterator VTs;	const vt_iterator VTs;
	const unsigned *SubClassMask;	const unsigned *SubClassMask;
	const sc_iterator SuperClasses;	const sc_iterator SuperClasses;
	const sc_iterator SuperRegClasses;	const sc_iterator SuperRegClasses;

	public:	ArrayRef<uint16_t> (*OrderFunc)(const MachineFunction&);
	TargetRegisterClass(const MCRegisterClass MC, const EVT vts,
	const unsigned *subcm,
	const TargetRegisterClass * const *supcs,
	const TargetRegisterClass * const *superregcs)
	: MC(MC), VTs(vts), SubClassMask(subcm), SuperClasses(supcs),
	SuperRegClasses(superregcs) {}

	virtual ~TargetRegisterClass() {} // Allow subclasses

	/// getID() - Return the register class ID number.	/// getID() - Return the register class ID number.
	///	///
	unsigned getID() const { return MC->getID(); }	unsigned getID() const { return MC->getID(); }

	/// getName() - Return the register class name for debugging.	/// getName() - Return the register class name for debugging.
	///	///
	const char *getName() const { return MC->getName(); }	const char *getName() const { return MC->getName(); }

	/// begin/end - Return all of the registers in this class.	/// begin/end - Return all of the registers in this class.

	skipping to change at line 111	skipping to change at line 105
	int getCopyCost() const { return MC->getCopyCost(); }	int getCopyCost() const { return MC->getCopyCost(); }

	/// isAllocatable - Return true if this register class may be used to cre ate	/// isAllocatable - Return true if this register class may be used to cre ate
	/// virtual registers.	/// virtual registers.
	bool isAllocatable() const { return MC->isAllocatable(); }	bool isAllocatable() const { return MC->isAllocatable(); }

	/// hasType - return true if this TargetRegisterClass has the ValueType v t.	/// hasType - return true if this TargetRegisterClass has the ValueType v t.
	///	///
	bool hasType(EVT vt) const {	bool hasType(EVT vt) const {
	for(int i = 0; VTs[i] != MVT::Other; ++i)	for(int i = 0; VTs[i] != MVT::Other; ++i)

	if (VTs[i] == vt)	if (EVT(VTs[i]) == vt)
	return true;	return true;
	return false;	return false;
	}	}

	/// vt_begin / vt_end - Loop over all of the value types that can be	/// vt_begin / vt_end - Loop over all of the value types that can be
	/// represented by values in this register class.	/// represented by values in this register class.
	vt_iterator vt_begin() const {	vt_iterator vt_begin() const {
	return VTs;	return VTs;
	}	}


	skipping to change at line 168	skipping to change at line 162

	/// hasSuperClassEq - Returns true if RC is a super-class of or equal to this	/// hasSuperClassEq - Returns true if RC is a super-class of or equal to this
	/// class.	/// class.
	bool hasSuperClassEq(const TargetRegisterClass *RC) const {	bool hasSuperClassEq(const TargetRegisterClass *RC) const {
	return RC->hasSubClassEq(this);	return RC->hasSubClassEq(this);
	}	}

	/// getSubClassMask - Returns a bit vector of subclasses, including this one.	/// getSubClassMask - Returns a bit vector of subclasses, including this one.
	/// The vector is indexed by class IDs, see hasSubClassEq() above for how to	/// The vector is indexed by class IDs, see hasSubClassEq() above for how to
	/// use it.	/// use it.

	const unsigned *getSubClassMask() const {	const uint32_t *getSubClassMask() const {
	return SubClassMask;	return SubClassMask;
	}	}

	/// getSuperClasses - Returns a NULL terminated list of super-classes. T he	/// getSuperClasses - Returns a NULL terminated list of super-classes. T he
	/// classes are ordered by ID which is also a topological ordering from l arge	/// classes are ordered by ID which is also a topological ordering from l arge
	/// to small classes. The list does NOT include the current class.	/// to small classes. The list does NOT include the current class.
	sc_iterator getSuperClasses() const {	sc_iterator getSuperClasses() const {
	return SuperClasses;	return SuperClasses;
	}	}


	skipping to change at line 199	skipping to change at line 193
	/// callee-saved registers only after all the volatiles are used. The	/// callee-saved registers only after all the volatiles are used. The
	/// RegisterClassInfo class provides filtered allocation orders with	/// RegisterClassInfo class provides filtered allocation orders with
	/// callee-saved registers moved to the end.	/// callee-saved registers moved to the end.
	///	///
	/// The MachineFunction argument can be used to tune the allocatable	/// The MachineFunction argument can be used to tune the allocatable
	/// registers based on the characteristics of the function, subtarget, or	/// registers based on the characteristics of the function, subtarget, or
	/// other criteria.	/// other criteria.
	///	///
	/// By default, this method returns all registers in the class.	/// By default, this method returns all registers in the class.
	///	///

	virtual	ArrayRef<uint16_t> getRawAllocationOrder(const MachineFunction &MF) const
	ArrayRef<unsigned> getRawAllocationOrder(const MachineFunction &MF) const	{
	{	return OrderFunc ? OrderFunc(MF) : makeArrayRef(begin(), getNumRegs());
	return makeArrayRef(begin(), getNumRegs());
	}	}
	};	};

	/// TargetRegisterInfoDesc - Extra information, not in MCRegisterDesc, abou t	/// TargetRegisterInfoDesc - Extra information, not in MCRegisterDesc, abou t
	/// registers. These are used by codegen, not by MC.	/// registers. These are used by codegen, not by MC.
	struct TargetRegisterInfoDesc {	struct TargetRegisterInfoDesc {
	unsigned CostPerUse; // Extra cost of instructions using registe r.	unsigned CostPerUse; // Extra cost of instructions using registe r.
	bool inAllocatableClass; // Register belongs to an allocatable regcl ass.	bool inAllocatableClass; // Register belongs to an allocatable regcl ass.
	};	};


		/// Each TargetRegisterClass has a per register weight, and weight
		/// limit which must be less than the limits of its pressure sets.
		struct RegClassWeight {
		unsigned RegWeight;
		unsigned WeightLimit;
		};

	/// TargetRegisterInfo base class - We assume that the target defines a sta tic	/// TargetRegisterInfo base class - We assume that the target defines a sta tic
	/// array of TargetRegisterDesc objects that represent all of the machine	/// array of TargetRegisterDesc objects that represent all of the machine
	/// registers that the target has. As such, we simply have to track a poin ter	/// registers that the target has. As such, we simply have to track a poin ter
	/// to this array so that we can turn register number into a register	/// to this array so that we can turn register number into a register
	/// descriptor.	/// descriptor.
	///	///
	class TargetRegisterInfo : public MCRegisterInfo {	class TargetRegisterInfo : public MCRegisterInfo {
	public:	public:
	typedef const TargetRegisterClass * const * regclass_iterator;	typedef const TargetRegisterClass * const * regclass_iterator;
	private:	private:

	skipping to change at line 335	skipping to change at line 335
	assert(SubIdx && "This is not a subregister index");	assert(SubIdx && "This is not a subregister index");
	return SubRegIndexNames[SubIdx-1];	return SubRegIndexNames[SubIdx-1];
	}	}

	/// regsOverlap - Returns true if the two registers are equal or alias ea ch	/// regsOverlap - Returns true if the two registers are equal or alias ea ch
	/// other. The registers may be virtual register.	/// other. The registers may be virtual register.
	bool regsOverlap(unsigned regA, unsigned regB) const {	bool regsOverlap(unsigned regA, unsigned regB) const {
	if (regA == regB) return true;	if (regA == regB) return true;
	if (isVirtualRegister(regA) \|\| isVirtualRegister(regB))	if (isVirtualRegister(regA) \|\| isVirtualRegister(regB))
	return false;	return false;

	for (const unsigned regList = getOverlaps(regA)+1; regList; ++regList ) {	for (const uint16_t regList = getOverlaps(regA)+1; regList; ++regList ) {
	if (*regList == regB) return true;	if (*regList == regB) return true;
	}	}
	return false;	return false;
	}	}

	/// isSubRegister - Returns true if regB is a sub-register of regA.	/// isSubRegister - Returns true if regB is a sub-register of regA.
	///	///
	bool isSubRegister(unsigned regA, unsigned regB) const {	bool isSubRegister(unsigned regA, unsigned regB) const {
	return isSuperRegister(regB, regA);	return isSuperRegister(regB, regA);
	}	}

	/// isSuperRegister - Returns true if regB is a super-register of regA.	/// isSuperRegister - Returns true if regB is a super-register of regA.
	///	///
	bool isSuperRegister(unsigned regA, unsigned regB) const {	bool isSuperRegister(unsigned regA, unsigned regB) const {

	for (const unsigned regList = getSuperRegisters(regA); regList;++regL ist){	for (const uint16_t regList = getSuperRegisters(regA); regList;++regL ist){
	if (*regList == regB) return true;	if (*regList == regB) return true;
	}	}
	return false;	return false;
	}	}

	/// getCalleeSavedRegs - Return a null-terminated list of all of the	/// getCalleeSavedRegs - Return a null-terminated list of all of the
	/// callee saved registers on this target. The register should be in the	/// callee saved registers on this target. The register should be in the
	/// order of desired callee-save stack frame offset. The first register i s	/// order of desired callee-save stack frame offset. The first register i s

	/// closed to the incoming stack pointer if stack grows down, and vice ve	/// closest to the incoming stack pointer if stack grows down, and vice v
	rsa.	ersa.
	virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF = 0)	///
		virtual const uint16_t* getCalleeSavedRegs(const MachineFunction *MF = 0)
	const = 0;	const = 0;


		/// getCallPreservedMask - Return a mask of call-preserved registers for
		the
		/// given calling convention on the current sub-target. The mask should
		/// include all call-preserved aliases. This is used by the register
		/// allocator to determine which registers can be live across a call.
		///
		/// The mask is an array containing (TRI::getNumRegs()+31)/32 entries.
		/// A set bit indicates that all bits of the corresponding register are
		/// preserved across the function call. The bit mask is expected to be
		/// sub-register complete, i.e. if A is preserved, so are all its
		/// sub-registers.
		///
		/// Bits are numbered from the LSB, so the bit for physical register Reg
		can
		/// be found as (Mask[Reg / 32] >> Reg % 32) & 1.
		///
		/// A NULL pointer means that no register mask will be used, and call
		/// instructions should use implicit-def operands to indicate call clobbe
		red
		/// registers.
		///
		virtual const uint32_t *getCallPreservedMask(CallingConv::ID) const {
		// The default mask clobbers everything. All targets should override.
		return 0;
		}

	/// getReservedRegs - Returns a bitset indexed by physical register numbe r	/// getReservedRegs - Returns a bitset indexed by physical register numbe r
	/// indicating if a register is a special register that has particular us es	/// indicating if a register is a special register that has particular us es
	/// and should be considered unavailable at all times, e.g. SP, RA. This is	/// and should be considered unavailable at all times, e.g. SP, RA. This is
	/// used by register scavenger to determine what registers are free.	/// used by register scavenger to determine what registers are free.
	virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;	virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;


	/// getSubReg - Returns the physical register number of sub-register "Ind
	ex"
	/// for physical register RegNo. Return zero if the sub-register does not
	/// exist.
	virtual unsigned getSubReg(unsigned RegNo, unsigned Index) const = 0;

	/// getSubRegIndex - For a given register pair, return the sub-register i
	ndex
	/// if the second register is a sub-register of the first. Return zero
	/// otherwise.
	virtual unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const
	= 0;

	/// getMatchingSuperReg - Return a super-register of the specified regist er	/// getMatchingSuperReg - Return a super-register of the specified regist er
	/// Reg so its sub-register of index SubIdx is Reg.	/// Reg so its sub-register of index SubIdx is Reg.
	unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,	unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
	const TargetRegisterClass *RC) const {	const TargetRegisterClass *RC) const {

	for (const unsigned SRs = getSuperRegisters(Reg); unsigned SR = SRs;+	return MCRegisterInfo::getMatchingSuperReg(Reg, SubIdx, RC->MC);
	+SRs)
	if (Reg == getSubReg(SR, SubIdx) && RC->contains(SR))
	return SR;
	return 0;
	}	}

	/// canCombineSubRegIndices - Given a register class and a list of	/// canCombineSubRegIndices - Given a register class and a list of
	/// subregister indices, return true if it's possible to combine the	/// subregister indices, return true if it's possible to combine the
	/// subregister indices into one that corresponds to a larger	/// subregister indices into one that corresponds to a larger
	/// subregister. Return the new subregister index by reference. Note the	/// subregister. Return the new subregister index by reference. Note the
	/// new index may be zero if the given subregisters can be combined to	/// new index may be zero if the given subregisters can be combined to
	/// form the whole register.	/// form the whole register.
	virtual bool canCombineSubRegIndices(const TargetRegisterClass *RC,	virtual bool canCombineSubRegIndices(const TargetRegisterClass *RC,
	SmallVectorImpl<unsigned> &SubIndice s,	SmallVectorImpl<unsigned> &SubIndice s,
	unsigned &NewSubIdx) const {	unsigned &NewSubIdx) const {
	return 0;	return 0;
	}	}

	/// getMatchingSuperRegClass - Return a subclass of the specified registe r	/// getMatchingSuperRegClass - Return a subclass of the specified registe r
	/// class A so that each register in it has a sub-register of the	/// class A so that each register in it has a sub-register of the
	/// specified sub-register index which is in the specified register class B.	/// specified sub-register index which is in the specified register class B.

		///
		/// TableGen will synthesize missing A sub-classes.
	virtual const TargetRegisterClass *	virtual const TargetRegisterClass *
	getMatchingSuperRegClass(const TargetRegisterClass *A,	getMatchingSuperRegClass(const TargetRegisterClass *A,

	const TargetRegisterClass *B, unsigned Idx) cons	const TargetRegisterClass *B, unsigned Idx) cons
	t {	t =0;
	return 0;
	}

	/// getSubClassWithSubReg - Returns the largest legal sub-class of RC tha t	/// getSubClassWithSubReg - Returns the largest legal sub-class of RC tha t
	/// supports the sub-register index Idx.	/// supports the sub-register index Idx.
	/// If no such sub-class exists, return NULL.	/// If no such sub-class exists, return NULL.
	/// If all registers in RC already have an Idx sub-register, return RC.	/// If all registers in RC already have an Idx sub-register, return RC.
	///	///
	/// TableGen generates a version of this function that is good enough in most	/// TableGen generates a version of this function that is good enough in most
	/// cases. Targets can override if they have constraints that TableGen	/// cases. Targets can override if they have constraints that TableGen
	/// doesn't understand. For example, the x86 sub_8bit sub-register index is	/// doesn't understand. For example, the x86 sub_8bit sub-register index is
	/// supported by the full GR32 register class in 64-bit mode, but only by the	/// supported by the full GR32 register class in 64-bit mode, but only by the
	/// GR32_ABCD regiister class in 32-bit mode.	/// GR32_ABCD regiister class in 32-bit mode.
	///	///

		/// TableGen will synthesize missing RC sub-classes.
	virtual const TargetRegisterClass *	virtual const TargetRegisterClass *
	getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const =0;	getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const =0;

	/// composeSubRegIndices - Return the subregister index you get from comp osing	/// composeSubRegIndices - Return the subregister index you get from comp osing
	/// two subregister indices.	/// two subregister indices.
	///	///
	/// If R:a:b is the same register as R:c, then composeSubRegIndices(a, b)	/// If R:a:b is the same register as R:c, then composeSubRegIndices(a, b)
	/// returns c. Note that composeSubRegIndices does not tell you about ill egal	/// returns c. Note that composeSubRegIndices does not tell you about ill egal
	/// compositions. If R does not have a subreg a, or R:a does not have a s ubreg	/// compositions. If R does not have a subreg a, or R:a does not have a s ubreg
	/// b, composeSubRegIndices doesn't tell you.	/// b, composeSubRegIndices doesn't tell you.

	skipping to change at line 471	skipping to change at line 483
	/// getCommonSubClass - find the largest common subclass of A and B. Retu rn	/// getCommonSubClass - find the largest common subclass of A and B. Retu rn
	/// NULL if there is no common subclass.	/// NULL if there is no common subclass.
	const TargetRegisterClass *	const TargetRegisterClass *
	getCommonSubClass(const TargetRegisterClass *A,	getCommonSubClass(const TargetRegisterClass *A,
	const TargetRegisterClass *B) const;	const TargetRegisterClass *B) const;

	/// getPointerRegClass - Returns a TargetRegisterClass used for pointer	/// getPointerRegClass - Returns a TargetRegisterClass used for pointer
	/// values. If a target supports multiple different pointer register cla sses,	/// values. If a target supports multiple different pointer register cla sses,
	/// kind specifies which one is indicated.	/// kind specifies which one is indicated.
	virtual const TargetRegisterClass *getPointerRegClass(unsigned Kind=0) co nst {	virtual const TargetRegisterClass *getPointerRegClass(unsigned Kind=0) co nst {

	assert(0 && "Target didn't implement getPointerRegClass!");	llvm_unreachable("Target didn't implement getPointerRegClass!");
	return 0; // Must return a value in order to compile with VS 2005
	}	}

	/// getCrossCopyRegClass - Returns a legal register class to copy a regis ter	/// getCrossCopyRegClass - Returns a legal register class to copy a regis ter
	/// in the specified class to or from. If it is possible to copy the regi ster	/// in the specified class to or from. If it is possible to copy the regi ster
	/// directly without using a cross register class copy, return the specif ied	/// directly without using a cross register class copy, return the specif ied
	/// RC. Returns NULL if it is not possible to copy between a two register s of	/// RC. Returns NULL if it is not possible to copy between a two register s of
	/// the specified class.	/// the specified class.
	virtual const TargetRegisterClass *	virtual const TargetRegisterClass *
	getCrossCopyRegClass(const TargetRegisterClass *RC) const {	getCrossCopyRegClass(const TargetRegisterClass *RC) const {
	return RC;	return RC;

	skipping to change at line 499	skipping to change at line 510
	virtual const TargetRegisterClass*	virtual const TargetRegisterClass*
	getLargestLegalSuperClass(const TargetRegisterClass *RC) const {	getLargestLegalSuperClass(const TargetRegisterClass *RC) const {
	/// The default implementation is very conservative and doesn't allow t he	/// The default implementation is very conservative and doesn't allow t he
	/// register allocator to inflate register classes.	/// register allocator to inflate register classes.
	return RC;	return RC;
	}	}

	/// getRegPressureLimit - Return the register pressure "high water mark" for	/// getRegPressureLimit - Return the register pressure "high water mark" for
	/// the specific register class. The scheduler is in high register pressu re	/// the specific register class. The scheduler is in high register pressu re
	/// mode (for the specific register class) if it goes over the limit.	/// mode (for the specific register class) if it goes over the limit.

		///
		/// Note: this is the old register pressure model that relies on a manual
		ly
		/// specified representative register class per value type.
	virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC,	virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC,
	MachineFunction &MF) const {	MachineFunction &MF) const {
	return 0;	return 0;
	}	}


		/// Get the weight in units of pressure for this register class.
		virtual const RegClassWeight &getRegClassWeight(
		const TargetRegisterClass *RC) const = 0;

		/// Get the number of dimensions of register pressure.
		virtual unsigned getNumRegPressureSets() const = 0;

		/// Get the register unit pressure limit for this dimension.
		/// This limit must be adjusted dynamically for reserved registers.
		virtual unsigned getRegPressureSetLimit(unsigned Idx) const = 0;

		/// Get the dimensions of register pressure impacted by this register cla
		ss.
		/// Returns a -1 terminated array of pressure set IDs.
		virtual const int *getRegClassPressureSets(
		const TargetRegisterClass *RC) const = 0;

	/// getRawAllocationOrder - Returns the register allocation order for a	/// getRawAllocationOrder - Returns the register allocation order for a
	/// specified register class with a target-dependent hint. The returned l ist	/// specified register class with a target-dependent hint. The returned l ist
	/// may contain reserved registers that cannot be allocated.	/// may contain reserved registers that cannot be allocated.
	///	///
	/// Register allocators need only call this function to resolve	/// Register allocators need only call this function to resolve
	/// target-dependent hints, but it should work without hinting as well.	/// target-dependent hints, but it should work without hinting as well.

	virtual ArrayRef<unsigned>	virtual ArrayRef<uint16_t>
	getRawAllocationOrder(const TargetRegisterClass *RC,	getRawAllocationOrder(const TargetRegisterClass *RC,
	unsigned HintType, unsigned HintReg,	unsigned HintType, unsigned HintReg,
	const MachineFunction &MF) const {	const MachineFunction &MF) const {
	return RC->getRawAllocationOrder(MF);	return RC->getRawAllocationOrder(MF);
	}	}

	/// ResolveRegAllocHint - Resolves the specified register allocation hint	/// ResolveRegAllocHint - Resolves the specified register allocation hint
	/// to a physical register. Returns the physical register if it is succes sful.	/// to a physical register. Returns the physical register if it is succes sful.
	virtual unsigned ResolveRegAllocHint(unsigned Type, unsigned Reg,	virtual unsigned ResolveRegAllocHint(unsigned Type, unsigned Reg,
	const MachineFunction &MF) const {	const MachineFunction &MF) const {

	skipping to change at line 609	skipping to change at line 639
	/// references it should create new base registers for.	/// references it should create new base registers for.
	virtual bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {	virtual bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
	return false;	return false;
	}	}

	/// materializeFrameBaseRegister - Insert defining instruction(s) for	/// materializeFrameBaseRegister - Insert defining instruction(s) for
	/// BaseReg to be a pointer to FrameIdx before insertion point I.	/// BaseReg to be a pointer to FrameIdx before insertion point I.
	virtual void materializeFrameBaseRegister(MachineBasicBlock *MBB,	virtual void materializeFrameBaseRegister(MachineBasicBlock *MBB,
	unsigned BaseReg, int FrameIdx,	unsigned BaseReg, int FrameIdx,
	int64_t Offset) const {	int64_t Offset) const {

	assert(0 && "materializeFrameBaseRegister does not exist on this target	llvm_unreachable("materializeFrameBaseRegister does not exist on this "
	");	"target");
	}	}

	/// resolveFrameIndex - Resolve a frame index operand of an instruction	/// resolveFrameIndex - Resolve a frame index operand of an instruction
	/// to reference the indicated base register plus offset instead.	/// to reference the indicated base register plus offset instead.
	virtual void resolveFrameIndex(MachineBasicBlock::iterator I,	virtual void resolveFrameIndex(MachineBasicBlock::iterator I,
	unsigned BaseReg, int64_t Offset) const {	unsigned BaseReg, int64_t Offset) const {

	assert(0 && "resolveFrameIndex does not exist on this target");	llvm_unreachable("resolveFrameIndex does not exist on this target");
	}	}

	/// isFrameOffsetLegal - Determine whether a given offset immediate is	/// isFrameOffsetLegal - Determine whether a given offset immediate is
	/// encodable to resolve a frame index.	/// encodable to resolve a frame index.
	virtual bool isFrameOffsetLegal(const MachineInstr *MI,	virtual bool isFrameOffsetLegal(const MachineInstr *MI,
	int64_t Offset) const {	int64_t Offset) const {

	assert(0 && "isFrameOffsetLegal does not exist on this target");	llvm_unreachable("isFrameOffsetLegal does not exist on this target");
	return false; // Must return a value in order to compile with VS 2005
	}	}

	/// eliminateCallFramePseudoInstr - This method is called during prolog/e pilog	/// eliminateCallFramePseudoInstr - This method is called during prolog/e pilog
	/// code insertion to eliminate call frame setup and destroy pseudo	/// code insertion to eliminate call frame setup and destroy pseudo
	/// instructions (but only if the Target is using them). It is responsib le	/// instructions (but only if the Target is using them). It is responsib le
	/// for eliminating these instructions, replacing them with concrete	/// for eliminating these instructions, replacing them with concrete
	/// instructions. This method need only be implemented if using call fra me	/// instructions. This method need only be implemented if using call fra me
	/// setup/destroy pseudo instructions.	/// setup/destroy pseudo instructions.
	///	///
	virtual void	virtual void
	eliminateCallFramePseudoInstr(MachineFunction &MF,	eliminateCallFramePseudoInstr(MachineFunction &MF,
	MachineBasicBlock &MBB,	MachineBasicBlock &MBB,
	MachineBasicBlock::iterator MI) const {	MachineBasicBlock::iterator MI) const {

	assert(0 && "Call Frame Pseudo Instructions do not exist on this target	llvm_unreachable("Call Frame Pseudo Instructions do not exist on this "
	!");	"target!");
	}	}

	/// saveScavengerRegister - Spill the register so it can be used by the	/// saveScavengerRegister - Spill the register so it can be used by the
	/// register scavenger. Return true if the register was spilled, false	/// register scavenger. Return true if the register was spilled, false
	/// otherwise. If this function does not spill the register, the scavenge r	/// otherwise. If this function does not spill the register, the scavenge r
	/// will instead spill it to the emergency spill slot.	/// will instead spill it to the emergency spill slot.
	///	///
	virtual bool saveScavengerRegister(MachineBasicBlock &MBB,	virtual bool saveScavengerRegister(MachineBasicBlock &MBB,
	MachineBasicBlock::iterator I,	MachineBasicBlock::iterator I,
	MachineBasicBlock::iterator &UseMI,	MachineBasicBlock::iterator &UseMI,

End of changes. 25 change blocks.
	56 lines changed or deleted	86 lines changed or added

	TargetRegistry.h	TargetRegistry.h

	skipping to change at line 47	skipping to change at line 47
	class MCDisassembler;	class MCDisassembler;
	class MCInstrAnalysis;	class MCInstrAnalysis;
	class MCInstPrinter;	class MCInstPrinter;
	class MCInstrInfo;	class MCInstrInfo;
	class MCRegisterInfo;	class MCRegisterInfo;
	class MCStreamer;	class MCStreamer;
	class MCSubtargetInfo;	class MCSubtargetInfo;
	class MCTargetAsmLexer;	class MCTargetAsmLexer;
	class MCTargetAsmParser;	class MCTargetAsmParser;
	class TargetMachine;	class TargetMachine;

		class TargetOptions;
	class raw_ostream;	class raw_ostream;
	class formatted_raw_ostream;	class formatted_raw_ostream;

	MCStreamer *createAsmStreamer(MCContext &Ctx, formatted_raw_ostream &OS,	MCStreamer *createAsmStreamer(MCContext &Ctx, formatted_raw_ostream &OS,
	bool isVerboseAsm,	bool isVerboseAsm,
	bool useLoc, bool useCFI,	bool useLoc, bool useCFI,

		bool useDwarfDirectory,
	MCInstPrinter *InstPrint,	MCInstPrinter *InstPrint,
	MCCodeEmitter *CE,	MCCodeEmitter *CE,
	MCAsmBackend *TAB,	MCAsmBackend *TAB,
	bool ShowInst);	bool ShowInst);

	/// Target - Wrapper for Target specific information.	/// Target - Wrapper for Target specific information.
	///	///
	/// For registration purposes, this is a POD type so that targets can be	/// For registration purposes, this is a POD type so that targets can be
	/// registered without the use of static constructors.	/// registered without the use of static constructors.
	///	///

	skipping to change at line 76	skipping to change at line 78
	class Target {	class Target {
	public:	public:
	friend struct TargetRegistry;	friend struct TargetRegistry;

	typedef unsigned (*TripleMatchQualityFnTy)(const std::string &TT);	typedef unsigned (*TripleMatchQualityFnTy)(const std::string &TT);

	typedef MCAsmInfo (MCAsmInfoCtorFnTy)(const Target &T,	typedef MCAsmInfo (MCAsmInfoCtorFnTy)(const Target &T,
	StringRef TT);	StringRef TT);
	typedef MCCodeGenInfo (MCCodeGenInfoCtorFnTy)(StringRef TT,	typedef MCCodeGenInfo (MCCodeGenInfoCtorFnTy)(StringRef TT,
	Reloc::Model RM,	Reloc::Model RM,

	CodeModel::Model CM);	CodeModel::Model CM,
		CodeGenOpt::Level OL);
	typedef MCInstrInfo (MCInstrInfoCtorFnTy)(void);	typedef MCInstrInfo (MCInstrInfoCtorFnTy)(void);
	typedef MCInstrAnalysis (MCInstrAnalysisCtorFnTy)(const MCInstrInfo*I nfo);	typedef MCInstrAnalysis (MCInstrAnalysisCtorFnTy)(const MCInstrInfo*I nfo);
	typedef MCRegisterInfo (MCRegInfoCtorFnTy)(StringRef TT);	typedef MCRegisterInfo (MCRegInfoCtorFnTy)(StringRef TT);
	typedef MCSubtargetInfo (MCSubtargetInfoCtorFnTy)(StringRef TT,	typedef MCSubtargetInfo (MCSubtargetInfoCtorFnTy)(StringRef TT,
	StringRef CPU,	StringRef CPU,
	StringRef Features) ;	StringRef Features) ;
	typedef TargetMachine (TargetMachineCtorTy)(const Target &T,	typedef TargetMachine (TargetMachineCtorTy)(const Target &T,
	StringRef TT,	StringRef TT,
	StringRef CPU,	StringRef CPU,
	StringRef Features,	StringRef Features,

		const TargetOptions &Opti ons,
	Reloc::Model RM,	Reloc::Model RM,

	CodeModel::Model CM);	CodeModel::Model CM,
		CodeGenOpt::Level OL);
	typedef AsmPrinter (AsmPrinterCtorTy)(TargetMachine &TM,	typedef AsmPrinter (AsmPrinterCtorTy)(TargetMachine &TM,
	MCStreamer &Streamer);	MCStreamer &Streamer);
	typedef MCAsmBackend (MCAsmBackendCtorTy)(const Target &T, StringRef TT);	typedef MCAsmBackend (MCAsmBackendCtorTy)(const Target &T, StringRef TT);
	typedef MCTargetAsmLexer (MCAsmLexerCtorTy)(const Target &T,	typedef MCTargetAsmLexer (MCAsmLexerCtorTy)(const Target &T,
	const MCRegisterInfo &MRI ,	const MCRegisterInfo &MRI ,
	const MCAsmInfo &MAI);	const MCAsmInfo &MAI);
	typedef MCTargetAsmParser (MCAsmParserCtorTy)(MCSubtargetInfo &STI,	typedef MCTargetAsmParser (MCAsmParserCtorTy)(MCSubtargetInfo &STI,
	MCAsmParser &P);	MCAsmParser &P);
	typedef MCDisassembler (MCDisassemblerCtorTy)(const Target &T,	typedef MCDisassembler (MCDisassemblerCtorTy)(const Target &T,
	const MCSubtargetInfo & STI);	const MCSubtargetInfo & STI);
	typedef MCInstPrinter (MCInstPrinterCtorTy)(const Target &T,	typedef MCInstPrinter (MCInstPrinterCtorTy)(const Target &T,
	unsigned SyntaxVariant,	unsigned SyntaxVariant,
	const MCAsmInfo &MAI,	const MCAsmInfo &MAI,

		const MCInstrInfo &MII,
		const MCRegisterInfo &MRI
		,
	const MCSubtargetInfo &ST I);	const MCSubtargetInfo &ST I);
	typedef MCCodeEmitter (MCCodeEmitterCtorTy)(const MCInstrInfo &II,	typedef MCCodeEmitter (MCCodeEmitterCtorTy)(const MCInstrInfo &II,
	const MCSubtargetInfo &ST I,	const MCSubtargetInfo &ST I,
	MCContext &Ctx);	MCContext &Ctx);
	typedef MCStreamer (MCObjectStreamerCtorTy)(const Target &T,	typedef MCStreamer (MCObjectStreamerCtorTy)(const Target &T,
	StringRef TT,	StringRef TT,
	MCContext &Ctx,	MCContext &Ctx,
	MCAsmBackend &TAB,	MCAsmBackend &TAB,
	raw_ostream &_OS,	raw_ostream &_OS,
	MCCodeEmitter *_Emitter,	MCCodeEmitter *_Emitter,
	bool RelaxAll,	bool RelaxAll,
	bool NoExecStack);	bool NoExecStack);
	typedef MCStreamer (AsmStreamerCtorTy)(MCContext &Ctx,	typedef MCStreamer (AsmStreamerCtorTy)(MCContext &Ctx,
	formatted_raw_ostream &OS,	formatted_raw_ostream &OS,
	bool isVerboseAsm,	bool isVerboseAsm,
	bool useLoc,	bool useLoc,
	bool useCFI,	bool useCFI,

		bool useDwarfDirectory,
	MCInstPrinter *InstPrint,	MCInstPrinter *InstPrint,
	MCCodeEmitter *CE,	MCCodeEmitter *CE,
	MCAsmBackend *TAB,	MCAsmBackend *TAB,
	bool ShowInst);	bool ShowInst);

	private:	private:
	/// Next - The next registered target in the linked list, maintained by the	/// Next - The next registered target in the linked list, maintained by the
	/// TargetRegistry.	/// TargetRegistry.
	Target *Next;	Target *Next;


	skipping to change at line 146	skipping to change at line 154
	/// ShortDesc - A short description of the target.	/// ShortDesc - A short description of the target.
	const char *ShortDesc;	const char *ShortDesc;

	/// HasJIT - Whether this target supports the JIT.	/// HasJIT - Whether this target supports the JIT.
	bool HasJIT;	bool HasJIT;

	/// MCAsmInfoCtorFn - Constructor function for this target's MCAsmInfo, if	/// MCAsmInfoCtorFn - Constructor function for this target's MCAsmInfo, if
	/// registered.	/// registered.
	MCAsmInfoCtorFnTy MCAsmInfoCtorFn;	MCAsmInfoCtorFnTy MCAsmInfoCtorFn;


	/// MCCodeGenInfoCtorFn - Constructor function for this target's MCCode	/// MCCodeGenInfoCtorFn - Constructor function for this target's
	GenInfo,	/// MCCodeGenInfo, if registered.
	/// if registered.
	MCCodeGenInfoCtorFnTy MCCodeGenInfoCtorFn;	MCCodeGenInfoCtorFnTy MCCodeGenInfoCtorFn;

	/// MCInstrInfoCtorFn - Constructor function for this target's MCInstrI nfo,	/// MCInstrInfoCtorFn - Constructor function for this target's MCInstrI nfo,
	/// if registered.	/// if registered.
	MCInstrInfoCtorFnTy MCInstrInfoCtorFn;	MCInstrInfoCtorFnTy MCInstrInfoCtorFn;

	/// MCInstrAnalysisCtorFn - Constructor function for this target's	/// MCInstrAnalysisCtorFn - Constructor function for this target's
	/// MCInstrAnalysis, if registered.	/// MCInstrAnalysis, if registered.
	MCInstrAnalysisCtorFnTy MCInstrAnalysisCtorFn;	MCInstrAnalysisCtorFnTy MCInstrAnalysisCtorFn;


	skipping to change at line 278	skipping to change at line 286
	/// host if that does not exist.	/// host if that does not exist.
	MCAsmInfo *createMCAsmInfo(StringRef Triple) const {	MCAsmInfo *createMCAsmInfo(StringRef Triple) const {
	if (!MCAsmInfoCtorFn)	if (!MCAsmInfoCtorFn)
	return 0;	return 0;
	return MCAsmInfoCtorFn(*this, Triple);	return MCAsmInfoCtorFn(*this, Triple);
	}	}

	/// createMCCodeGenInfo - Create a MCCodeGenInfo implementation.	/// createMCCodeGenInfo - Create a MCCodeGenInfo implementation.
	///	///
	MCCodeGenInfo *createMCCodeGenInfo(StringRef Triple, Reloc::Model RM,	MCCodeGenInfo *createMCCodeGenInfo(StringRef Triple, Reloc::Model RM,

	CodeModel::Model CM) const {	CodeModel::Model CM,
		CodeGenOpt::Level OL) const {
	if (!MCCodeGenInfoCtorFn)	if (!MCCodeGenInfoCtorFn)
	return 0;	return 0;

	return MCCodeGenInfoCtorFn(Triple, RM, CM);	return MCCodeGenInfoCtorFn(Triple, RM, CM, OL);
	}	}

	/// createMCInstrInfo - Create a MCInstrInfo implementation.	/// createMCInstrInfo - Create a MCInstrInfo implementation.
	///	///
	MCInstrInfo *createMCInstrInfo() const {	MCInstrInfo *createMCInstrInfo() const {
	if (!MCInstrInfoCtorFn)	if (!MCInstrInfoCtorFn)
	return 0;	return 0;
	return MCInstrInfoCtorFn();	return MCInstrInfoCtorFn();
	}	}


	skipping to change at line 332	skipping to change at line 341
	}	}

	/// createTargetMachine - Create a target specific machine implementati on	/// createTargetMachine - Create a target specific machine implementati on
	/// for the specified \arg Triple.	/// for the specified \arg Triple.
	///	///
	/// \arg Triple - This argument is used to determine the target machine	/// \arg Triple - This argument is used to determine the target machine
	/// feature set; it should always be provided. Generally this should be	/// feature set; it should always be provided. Generally this should be
	/// either the target triple from the module, or the target triple of t he	/// either the target triple from the module, or the target triple of t he
	/// host if that does not exist.	/// host if that does not exist.
	TargetMachine *createTargetMachine(StringRef Triple, StringRef CPU,	TargetMachine *createTargetMachine(StringRef Triple, StringRef CPU,

	StringRef Features,	StringRef Features, const TargetOptions &Optio
	Reloc::Model RM = Reloc::Default,	ns,
	CodeModel::Model CM = CodeModel::Default) co	Reloc::Model RM = Reloc::Default,
	nst {	CodeModel::Model CM = CodeModel::Default,
		CodeGenOpt::Level OL = CodeGenOpt::Default) co
		nst {
	if (!TargetMachineCtorFn)	if (!TargetMachineCtorFn)
	return 0;	return 0;

	return TargetMachineCtorFn(*this, Triple, CPU, Features, RM, CM);	return TargetMachineCtorFn(*this, Triple, CPU, Features, Options,
		RM, CM, OL);
	}	}

	/// createMCAsmBackend - Create a target specific assembly parser.	/// createMCAsmBackend - Create a target specific assembly parser.
	///	///
	/// \arg Triple - The target triple string.	/// \arg Triple - The target triple string.
	/// \arg Backend - The target independent assembler object.	/// \arg Backend - The target independent assembler object.
	MCAsmBackend *createMCAsmBackend(StringRef Triple) const {	MCAsmBackend *createMCAsmBackend(StringRef Triple) const {
	if (!MCAsmBackendCtorFn)	if (!MCAsmBackendCtorFn)
	return 0;	return 0;
	return MCAsmBackendCtorFn(*this, Triple);	return MCAsmBackendCtorFn(*this, Triple);

	skipping to change at line 386	skipping to change at line 397
	}	}

	MCDisassembler *createMCDisassembler(const MCSubtargetInfo &STI) const {	MCDisassembler *createMCDisassembler(const MCSubtargetInfo &STI) const {
	if (!MCDisassemblerCtorFn)	if (!MCDisassemblerCtorFn)
	return 0;	return 0;
	return MCDisassemblerCtorFn(*this, STI);	return MCDisassemblerCtorFn(*this, STI);
	}	}

	MCInstPrinter *createMCInstPrinter(unsigned SyntaxVariant,	MCInstPrinter *createMCInstPrinter(unsigned SyntaxVariant,
	const MCAsmInfo &MAI,	const MCAsmInfo &MAI,

		const MCInstrInfo &MII,
		const MCRegisterInfo &MRI,
	const MCSubtargetInfo &STI) const {	const MCSubtargetInfo &STI) const {
	if (!MCInstPrinterCtorFn)	if (!MCInstPrinterCtorFn)
	return 0;	return 0;

	return MCInstPrinterCtorFn(*this, SyntaxVariant, MAI, STI);	return MCInstPrinterCtorFn(*this, SyntaxVariant, MAI, MII, MRI, STI);
	}	}

	/// createMCCodeEmitter - Create a target specific code emitter.	/// createMCCodeEmitter - Create a target specific code emitter.
	MCCodeEmitter *createMCCodeEmitter(const MCInstrInfo &II,	MCCodeEmitter *createMCCodeEmitter(const MCInstrInfo &II,
	const MCSubtargetInfo &STI,	const MCSubtargetInfo &STI,
	MCContext &Ctx) const {	MCContext &Ctx) const {
	if (!MCCodeEmitterCtorFn)	if (!MCCodeEmitterCtorFn)
	return 0;	return 0;
	return MCCodeEmitterCtorFn(II, STI, Ctx);	return MCCodeEmitterCtorFn(II, STI, Ctx);
	}	}

	skipping to change at line 428	skipping to change at line 441
	return MCObjectStreamerCtorFn(*this, TT, Ctx, TAB, _OS, _Emitter,	return MCObjectStreamerCtorFn(*this, TT, Ctx, TAB, _OS, _Emitter,
	RelaxAll, NoExecStack);	RelaxAll, NoExecStack);
	}	}

	/// createAsmStreamer - Create a target specific MCStreamer.	/// createAsmStreamer - Create a target specific MCStreamer.
	MCStreamer *createAsmStreamer(MCContext &Ctx,	MCStreamer *createAsmStreamer(MCContext &Ctx,
	formatted_raw_ostream &OS,	formatted_raw_ostream &OS,
	bool isVerboseAsm,	bool isVerboseAsm,
	bool useLoc,	bool useLoc,
	bool useCFI,	bool useCFI,

		bool useDwarfDirectory,
	MCInstPrinter *InstPrint,	MCInstPrinter *InstPrint,
	MCCodeEmitter *CE,	MCCodeEmitter *CE,
	MCAsmBackend *TAB,	MCAsmBackend *TAB,
	bool ShowInst) const {	bool ShowInst) const {
	// AsmStreamerCtorFn is default to llvm::createAsmStreamer	// AsmStreamerCtorFn is default to llvm::createAsmStreamer
	return AsmStreamerCtorFn(Ctx, OS, isVerboseAsm, useLoc, useCFI,	return AsmStreamerCtorFn(Ctx, OS, isVerboseAsm, useLoc, useCFI,

	InstPrint, CE, TAB, ShowInst);	useDwarfDirectory, InstPrint, CE, TAB, ShowI nst);
	}	}

	/// @}	/// @}
	};	};

	/// TargetRegistry - Generic interface to target specific features.	/// TargetRegistry - Generic interface to target specific features.
	struct TargetRegistry {	struct TargetRegistry {
	class iterator {	class iterator {
	const Target *Current;	const Target *Current;
	explicit iterator(Target *T) : Current(T) {}	explicit iterator(Target *T) : Current(T) {}

	skipping to change at line 777	skipping to change at line 791

	/// RegisterTarget - Helper template for registering a target, for use in the	/// RegisterTarget - Helper template for registering a target, for use in the
	/// target's initialization function. Usage:	/// target's initialization function. Usage:
	///	///
	///	///
	/// Target TheFooTarget; // The global target instance.	/// Target TheFooTarget; // The global target instance.
	///	///
	/// extern "C" void LLVMInitializeFooTargetInfo() {	/// extern "C" void LLVMInitializeFooTargetInfo() {
	/// RegisterTarget<Triple::foo> X(TheFooTarget, "foo", "Foo description ");	/// RegisterTarget<Triple::foo> X(TheFooTarget, "foo", "Foo description ");
	/// }	/// }

	template<Triple::ArchType TargetArchType = Triple::InvalidArch,	template<Triple::ArchType TargetArchType = Triple::UnknownArch,
	bool HasJIT = false>	bool HasJIT = false>
	struct RegisterTarget {	struct RegisterTarget {
	RegisterTarget(Target &T, const char Name, const char Desc) {	RegisterTarget(Target &T, const char Name, const char Desc) {
	TargetRegistry::RegisterTarget(T, Name, Desc,	TargetRegistry::RegisterTarget(T, Name, Desc,
	&getTripleMatchQuality,	&getTripleMatchQuality,
	HasJIT);	HasJIT);
	}	}

	static unsigned getTripleMatchQuality(const std::string &TT) {	static unsigned getTripleMatchQuality(const std::string &TT) {
	if (Triple(TT).getArch() == TargetArchType)	if (Triple(TT).getArch() == TargetArchType)

	skipping to change at line 841	skipping to change at line 855
	/// extern "C" void LLVMInitializeFooTarget() {	/// extern "C" void LLVMInitializeFooTarget() {
	/// extern Target TheFooTarget;	/// extern Target TheFooTarget;
	/// RegisterMCCodeGenInfo<FooMCCodeGenInfo> X(TheFooTarget);	/// RegisterMCCodeGenInfo<FooMCCodeGenInfo> X(TheFooTarget);
	/// }	/// }
	template<class MCCodeGenInfoImpl>	template<class MCCodeGenInfoImpl>
	struct RegisterMCCodeGenInfo {	struct RegisterMCCodeGenInfo {
	RegisterMCCodeGenInfo(Target &T) {	RegisterMCCodeGenInfo(Target &T) {
	TargetRegistry::RegisterMCCodeGenInfo(T, &Allocator);	TargetRegistry::RegisterMCCodeGenInfo(T, &Allocator);
	}	}
	private:	private:

	static MCCodeGenInfo *Allocator(StringRef TT,	static MCCodeGenInfo *Allocator(StringRef TT, Reloc::Model RM,
	Reloc::Model RM, CodeModel::Model CM) {	CodeModel::Model CM, CodeGenOpt::Level
		OL) {
	return new MCCodeGenInfoImpl();	return new MCCodeGenInfoImpl();
	}	}
	};	};

	/// RegisterMCCodeGenInfoFn - Helper template for registering a target co degen	/// RegisterMCCodeGenInfoFn - Helper template for registering a target co degen
	/// info implementation. This invokes the specified function to do the	/// info implementation. This invokes the specified function to do the
	/// construction. Usage:	/// construction. Usage:
	///	///
	/// extern "C" void LLVMInitializeFooTarget() {	/// extern "C" void LLVMInitializeFooTarget() {
	/// extern Target TheFooTarget;	/// extern Target TheFooTarget;

	skipping to change at line 1011	skipping to change at line 1025
	/// }	/// }
	template<class TargetMachineImpl>	template<class TargetMachineImpl>
	struct RegisterTargetMachine {	struct RegisterTargetMachine {
	RegisterTargetMachine(Target &T) {	RegisterTargetMachine(Target &T) {
	TargetRegistry::RegisterTargetMachine(T, &Allocator);	TargetRegistry::RegisterTargetMachine(T, &Allocator);
	}	}

	private:	private:
	static TargetMachine *Allocator(const Target &T, StringRef TT,	static TargetMachine *Allocator(const Target &T, StringRef TT,
	StringRef CPU, StringRef FS,	StringRef CPU, StringRef FS,

		const TargetOptions &Options,
	Reloc::Model RM,	Reloc::Model RM,

	CodeModel::Model CM) {	CodeModel::Model CM,
	return new TargetMachineImpl(T, TT, CPU, FS, RM, CM);	CodeGenOpt::Level OL) {
		return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL);
	}	}
	};	};

	/// RegisterMCAsmBackend - Helper template for registering a target speci fic	/// RegisterMCAsmBackend - Helper template for registering a target speci fic
	/// assembler backend. Usage:	/// assembler backend. Usage:
	///	///
	/// extern "C" void LLVMInitializeFooMCAsmBackend() {	/// extern "C" void LLVMInitializeFooMCAsmBackend() {
	/// extern Target TheFooTarget;	/// extern Target TheFooTarget;
	/// RegisterMCAsmBackend<FooAsmLexer> X(TheFooTarget);	/// RegisterMCAsmBackend<FooAsmLexer> X(TheFooTarget);
	/// }	/// }

End of changes. 20 change blocks.
	19 lines changed or deleted	37 lines changed or added

	TargetSelect.h	TargetSelect.h

	skipping to change at line 152	skipping to change at line 152
	inline bool InitializeNativeTargetAsmParser() {	inline bool InitializeNativeTargetAsmParser() {
	// If we have a native target, initialize the corresponding asm parser.	// If we have a native target, initialize the corresponding asm parser.
	#ifdef LLVM_NATIVE_ASMPARSER	#ifdef LLVM_NATIVE_ASMPARSER
	LLVM_NATIVE_ASMPARSER();	LLVM_NATIVE_ASMPARSER();
	return false;	return false;
	#else	#else
	return true;	return true;
	#endif	#endif
	}	}


		/// InitializeNativeTargetDisassembler - The main program should call
		/// this function to initialize the native target disassembler.
		inline bool InitializeNativeTargetDisassembler() {
		// If we have a native target, initialize the corresponding disassembler.
		#ifdef LLVM_NATIVE_DISASSEMBLER
		LLVM_NATIVE_DISASSEMBLER();
		return false;
		#else
		return true;
		#endif
		}

	}	}

	#endif	#endif

End of changes. 1 change blocks.
	0 lines changed or deleted	12 lines changed or added

	TargetSelectionDAG.td	TargetSelectionDAG.td

	skipping to change at line 355	skipping to change at line 355
	def subc : SDNode<"ISD::SUBC" , SDTIntBinOp,	def subc : SDNode<"ISD::SUBC" , SDTIntBinOp,
	[SDNPOutGlue]>;	[SDNPOutGlue]>;
	def sube : SDNode<"ISD::SUBE" , SDTIntBinOp,	def sube : SDNode<"ISD::SUBE" , SDTIntBinOp,
	[SDNPOutGlue, SDNPInGlue]>;	[SDNPOutGlue, SDNPInGlue]>;

	def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>;	def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>;
	def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>;	def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>;
	def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>;	def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>;
	def cttz : SDNode<"ISD::CTTZ" , SDTIntUnaryOp>;	def cttz : SDNode<"ISD::CTTZ" , SDTIntUnaryOp>;
	def ctpop : SDNode<"ISD::CTPOP" , SDTIntUnaryOp>;	def ctpop : SDNode<"ISD::CTPOP" , SDTIntUnaryOp>;

		def ctlz_zero_undef : SDNode<"ISD::CTLZ_ZERO_UNDEF", SDTIntUnaryOp>;
		def cttz_zero_undef : SDNode<"ISD::CTTZ_ZERO_UNDEF", SDTIntUnaryOp>;
	def sext : SDNode<"ISD::SIGN_EXTEND", SDTIntExtendOp>;	def sext : SDNode<"ISD::SIGN_EXTEND", SDTIntExtendOp>;
	def zext : SDNode<"ISD::ZERO_EXTEND", SDTIntExtendOp>;	def zext : SDNode<"ISD::ZERO_EXTEND", SDTIntExtendOp>;
	def anyext : SDNode<"ISD::ANY_EXTEND" , SDTIntExtendOp>;	def anyext : SDNode<"ISD::ANY_EXTEND" , SDTIntExtendOp>;
	def trunc : SDNode<"ISD::TRUNCATE" , SDTIntTruncOp>;	def trunc : SDNode<"ISD::TRUNCATE" , SDTIntTruncOp>;
	def bitconvert : SDNode<"ISD::BITCAST" , SDTUnaryOp>;	def bitconvert : SDNode<"ISD::BITCAST" , SDTUnaryOp>;
	def extractelt : SDNode<"ISD::EXTRACT_VECTOR_ELT", SDTVecExtract>;	def extractelt : SDNode<"ISD::EXTRACT_VECTOR_ELT", SDTVecExtract>;
	def insertelt : SDNode<"ISD::INSERT_VECTOR_ELT", SDTVecInsert>;	def insertelt : SDNode<"ISD::INSERT_VECTOR_ELT", SDTVecInsert>;

	def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>;	def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>;
	def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>;	def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>;

	skipping to change at line 651	skipping to change at line 653
	def zextloadi8 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{	def zextloadi8 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
	return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;	return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
	}]>;	}]>;
	def zextloadi16 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{	def zextloadi16 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
	return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;	return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
	}]>;	}]>;
	def zextloadi32 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{	def zextloadi32 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
	return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;	return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
	}]>;	}]>;


		def extloadvi1 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
		return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i1;
		}]>;
		def extloadvi8 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
		return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
		}]>;
		def extloadvi16 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
		return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
		}]>;
		def extloadvi32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
		return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;
		}]>;
		def extloadvf32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
		return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::f32;
		}]>;
		def extloadvf64 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
		return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::f64;
		}]>;

		def sextloadvi1 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
		return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i1;
		}]>;
		def sextloadvi8 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
		return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
		}]>;
		def sextloadvi16 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
		return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
		}]>;
		def sextloadvi32 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
		return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;
		}]>;

		def zextloadvi1 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
		return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i1;
		}]>;
		def zextloadvi8 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
		return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
		}]>;
		def zextloadvi16 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
		return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
		}]>;
		def zextloadvi32 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
		return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;
		}]>;

	// store fragments.	// store fragments.
	def unindexedstore : PatFrag<(ops node:$val, node:$ptr),	def unindexedstore : PatFrag<(ops node:$val, node:$ptr),
	(st node:$val, node:$ptr), [{	(st node:$val, node:$ptr), [{
	return cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;	return cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
	}]>;	}]>;
	def store : PatFrag<(ops node:$val, node:$ptr),	def store : PatFrag<(ops node:$val, node:$ptr),
	(unindexedstore node:$val, node:$ptr), [{	(unindexedstore node:$val, node:$ptr), [{
	return !cast<StoreSDNode>(N)->isTruncatingStore();	return !cast<StoreSDNode>(N)->isTruncatingStore();
	}]>;	}]>;


End of changes. 2 change blocks.
	0 lines changed or deleted	47 lines changed or added

	Targets.def	Targets.def

	skipping to change at line 26	skipping to change at line 26
	\|* The set of targets supported by LLVM is generated at configuration *\|	\|* The set of targets supported by LLVM is generated at configuration *\|
	\|* time, at which point this header is generated. Do not modify this *\|	\|* time, at which point this header is generated. Do not modify this *\|
	\|* header directly. *\|	\|* header directly. *\|
	\|* *\|	\|* *\|
	\===---------------------------------------------------------------------- ===/	\===---------------------------------------------------------------------- ===/

	#ifndef LLVM_TARGET	#ifndef LLVM_TARGET
	# error Please define the macro LLVM_TARGET(TargetName)	# error Please define the macro LLVM_TARGET(TargetName)
	#endif	#endif


	LLVM_TARGET(PTX) LLVM_TARGET(MBlaze) LLVM_TARGET(CppBackend) LLVM_TARGET(CB ackend) LLVM_TARGET(Blackfin) LLVM_TARGET(SystemZ) LLVM_TARGET(MSP430) LLVM _TARGET(XCore) LLVM_TARGET(CellSPU) LLVM_TARGET(Mips) LLVM_TARGET(ARM) LLVM _TARGET(Alpha) LLVM_TARGET(PowerPC) LLVM_TARGET(Sparc) LLVM_TARGET(X86)	LLVM_TARGET(Hexagon) LLVM_TARGET(PTX) LLVM_TARGET(MBlaze) LLVM_TARGET(CppBa ckend) LLVM_TARGET(MSP430) LLVM_TARGET(XCore) LLVM_TARGET(CellSPU) LLVM_TAR GET(Mips) LLVM_TARGET(ARM) LLVM_TARGET(PowerPC) LLVM_TARGET(Sparc) LLVM_TAR GET(X86)

	#undef LLVM_TARGET	#undef LLVM_TARGET

End of changes. 1 change blocks.
	1 lines changed or deleted	1 lines changed or added

	TinyPtrVector.h	TinyPtrVector.h

	skipping to change at line 40	skipping to change at line 40
	TinyPtrVector() {}	TinyPtrVector() {}
	TinyPtrVector(const TinyPtrVector &RHS) : Val(RHS.Val) {	TinyPtrVector(const TinyPtrVector &RHS) : Val(RHS.Val) {
	if (VecTy V = Val.template dyn_cast<VecTy>())	if (VecTy V = Val.template dyn_cast<VecTy>())
	Val = new VecTy(*V);	Val = new VecTy(*V);
	}	}
	~TinyPtrVector() {	~TinyPtrVector() {
	if (VecTy V = Val.template dyn_cast<VecTy>())	if (VecTy V = Val.template dyn_cast<VecTy>())
	delete V;	delete V;
	}	}


		// implicit conversion operator to ArrayRef.
		operator ArrayRef<EltTy>() const {
		if (Val.isNull())
		return ArrayRef<EltTy>();
		if (Val.template is<EltTy>())
		return *Val.getAddrOfPtr1();
		return Val.template get<VecTy>();
		}

	bool empty() const {	bool empty() const {
	// This vector can be empty if it contains no element, or if it	// This vector can be empty if it contains no element, or if it
	// contains a pointer to an empty vector.	// contains a pointer to an empty vector.
	if (Val.isNull()) return true;	if (Val.isNull()) return true;
	if (VecTy Vec = Val.template dyn_cast<VecTy>())	if (VecTy Vec = Val.template dyn_cast<VecTy>())
	return Vec->empty();	return Vec->empty();
	return false;	return false;
	}	}

	unsigned size() const {	unsigned size() const {
	if (empty())	if (empty())
	return 0;	return 0;
	if (Val.template is<EltTy>())	if (Val.template is<EltTy>())
	return 1;	return 1;
	return Val.template get<VecTy*>()->size();	return Val.template get<VecTy*>()->size();
	}	}


	typedef const EltTy *iterator;	typedef const EltTy *const_iterator;
	iterator begin() const {	typedef EltTy *iterator;

		iterator begin() {
	if (empty())	if (empty())
	return 0;	return 0;

	if (Val.template is<EltTy>())	if (Val.template is<EltTy>())

	return Val.template getAddrOf<EltTy>();	return Val.getAddrOfPtr1();

	return Val.template get<VecTy *>()->begin();	return Val.template get<VecTy *>()->begin();

	}	}

	iterator end() const {	iterator end() {
	if (empty())	if (empty())
	return 0;	return 0;

	if (Val.template is<EltTy>())	if (Val.template is<EltTy>())
	return begin() + 1;	return begin() + 1;

	return Val.template get<VecTy *>()->end();	return Val.template get<VecTy *>()->end();
	}	}


		const_iterator begin() const {
		return (const_iterator)const_cast<TinyPtrVector*>(this)->begin();
		}

		const_iterator end() const {
		return (const_iterator)const_cast<TinyPtrVector*>(this)->end();
		}

	EltTy operator[](unsigned i) const {	EltTy operator[](unsigned i) const {
	assert(!Val.isNull() && "can't index into an empty vector");	assert(!Val.isNull() && "can't index into an empty vector");
	if (EltTy V = Val.template dyn_cast<EltTy>()) {	if (EltTy V = Val.template dyn_cast<EltTy>()) {
	assert(i == 0 && "tinyvector index out of range");	assert(i == 0 && "tinyvector index out of range");
	return V;	return V;
	}	}

	assert(i < Val.template get<VecTy*>()->size() &&	assert(i < Val.template get<VecTy*>()->size() &&
	"tinyvector index out of range");	"tinyvector index out of range");
	return (Val.template get<VecTy>())[i];	return (Val.template get<VecTy>())[i];

	skipping to change at line 127	skipping to change at line 146
	// If we have a single value, convert to empty.	// If we have a single value, convert to empty.
	if (Val.template is<EltTy>()) {	if (Val.template is<EltTy>()) {
	Val = (EltTy)0;	Val = (EltTy)0;
	} else if (VecTy Vec = Val.template dyn_cast<VecTy>()) {	} else if (VecTy Vec = Val.template dyn_cast<VecTy>()) {
	// If we have a vector form, just clear it.	// If we have a vector form, just clear it.
	Vec->clear();	Vec->clear();
	}	}
	// Otherwise, we're already empty.	// Otherwise, we're already empty.
	}	}


		iterator erase(iterator I) {
		// If we have a single value, convert to empty.
		if (Val.template is<EltTy>()) {
		if (I == begin())
		Val = (EltTy)0;
		} else if (VecTy Vec = Val.template dyn_cast<VecTy>()) {
		// multiple items in a vector; just do the erase, there is no
		// benefit to collapsing back to a pointer
		return Vec->erase(I);
		}

		return 0;
		}

	private:	private:
	void operator=(const TinyPtrVector&); // NOT IMPLEMENTED YET.	void operator=(const TinyPtrVector&); // NOT IMPLEMENTED YET.
	};	};
	} // end namespace llvm	} // end namespace llvm

	#endif	#endif

End of changes. 6 change blocks.
	4 lines changed or deleted	37 lines changed or added

	Trie.h	Trie.h

	skipping to change at line 223	skipping to change at line 223
	typename Node::QueryResult r = nNode->query(s1);	typename Node::QueryResult r = nNode->query(s1);

	switch (r) {	switch (r) {
	case Node::Same:	case Node::Same:
	case Node::StringIsPrefix:	case Node::StringIsPrefix:
	// Currently we don't allow to have two strings in the trie one	// Currently we don't allow to have two strings in the trie one
	// being a prefix of another. This should be fixed.	// being a prefix of another. This should be fixed.
	assert(0 && "FIXME!");	assert(0 && "FIXME!");
	return false;	return false;
	case Node::DontMatch:	case Node::DontMatch:

	assert(0 && "Impossible!");	llvm_unreachable("Impossible!");
	return false;
	case Node::LabelIsPrefix:	case Node::LabelIsPrefix:
	s1 = s1.substr(nNode->label().length());	s1 = s1.substr(nNode->label().length());
	cNode = nNode;	cNode = nNode;
	break;	break;
	default:	default:
	nNode = splitEdge(cNode, Id, r);	nNode = splitEdge(cNode, Id, r);
	tNode = addNode(data, s1.substr(r));	tNode = addNode(data, s1.substr(r));
	nNode->addEdge(tNode);	nNode->addEdge(tNode);
	}	}
	} else {	} else {

	skipping to change at line 261	skipping to change at line 260
	if (Node* nNode = cNode->getEdge(Id)) {	if (Node* nNode = cNode->getEdge(Id)) {
	typename Node::QueryResult r = nNode->query(s1);	typename Node::QueryResult r = nNode->query(s1);

	switch (r) {	switch (r) {
	case Node::Same:	case Node::Same:
	tNode = nNode;	tNode = nNode;
	break;	break;
	case Node::StringIsPrefix:	case Node::StringIsPrefix:
	return Empty;	return Empty;
	case Node::DontMatch:	case Node::DontMatch:

	assert(0 && "Impossible!");	llvm_unreachable("Impossible!");
	return Empty;
	case Node::LabelIsPrefix:	case Node::LabelIsPrefix:
	s1 = s1.substr(nNode->label().length());	s1 = s1.substr(nNode->label().length());
	cNode = nNode;	cNode = nNode;
	break;	break;
	default:	default:
	return Empty;	return Empty;
	}	}
	} else	} else
	return Empty;	return Empty;
	}	}

End of changes. 2 change blocks.
	4 lines changed or deleted	2 lines changed or added

	Triple.h	Triple.h

	skipping to change at line 46	skipping to change at line 46
	/// Clients that need to handle the non-canonical triples that users often	/// Clients that need to handle the non-canonical triples that users often
	/// specify should use the normalize method.	/// specify should use the normalize method.
	///	///
	/// See autoconf/config.guess for a glimpse into what triples look like in	/// See autoconf/config.guess for a glimpse into what triples look like in
	/// practice.	/// practice.
	class Triple {	class Triple {
	public:	public:
	enum ArchType {	enum ArchType {
	UnknownArch,	UnknownArch,


	alpha, // Alpha: alpha
	arm, // ARM; arm, armv.*, xscale	arm, // ARM; arm, armv.*, xscale

	bfin, // Blackfin: bfin
	cellspu, // CellSPU: spu, cellspu	cellspu, // CellSPU: spu, cellspu

		hexagon, // Hexagon: hexagon
	mips, // MIPS: mips, mipsallegrex	mips, // MIPS: mips, mipsallegrex

	mipsel, // MIPSEL: mipsel, mipsallegrexel, psp	mipsel, // MIPSEL: mipsel, mipsallegrexel
	mips64, // MIPS64: mips64	mips64, // MIPS64: mips64
	mips64el,// MIPS64EL: mips64el	mips64el,// MIPS64EL: mips64el
	msp430, // MSP430: msp430	msp430, // MSP430: msp430
	ppc, // PPC: powerpc	ppc, // PPC: powerpc
	ppc64, // PPC64: powerpc64, ppu	ppc64, // PPC64: powerpc64, ppu

		r600, // R600: AMD GPUs HD2XXX - HD6XXX
	sparc, // Sparc: sparc	sparc, // Sparc: sparc
	sparcv9, // Sparcv9: Sparcv9	sparcv9, // Sparcv9: Sparcv9

	systemz, // SystemZ: s390x
	tce, // TCE (http://tce.cs.tut.fi/): tce	tce, // TCE (http://tce.cs.tut.fi/): tce
	thumb, // Thumb: thumb, thumbv.*	thumb, // Thumb: thumb, thumbv.*
	x86, // X86: i[3-9]86	x86, // X86: i[3-9]86
	x86_64, // X86-64: amd64, x86_64	x86_64, // X86-64: amd64, x86_64
	xcore, // XCore: xcore	xcore, // XCore: xcore
	mblaze, // MBlaze: mblaze	mblaze, // MBlaze: mblaze
	ptx32, // PTX: ptx (32-bit)	ptx32, // PTX: ptx (32-bit)
	ptx64, // PTX: ptx (64-bit)	ptx64, // PTX: ptx (64-bit)
	le32, // le32: generic little-endian 32-bit CPU (PNaCl / Emscripten)	le32, // le32: generic little-endian 32-bit CPU (PNaCl / Emscripten)

	amdil, // amdil: amd IL	amdil // amdil: amd IL

	InvalidArch
	};	};
	enum VendorType {	enum VendorType {
	UnknownVendor,	UnknownVendor,

	Apple,	Apple,
	PC,	PC,

	SCEI	SCEI,
		BGP,
		BGQ
	};	};
	enum OSType {	enum OSType {
	UnknownOS,	UnknownOS,

	AuroraUX,	AuroraUX,
	Cygwin,	Cygwin,
	Darwin,	Darwin,
	DragonFly,	DragonFly,
	FreeBSD,	FreeBSD,
	IOS,	IOS,
	KFreeBSD,	KFreeBSD,
	Linux,	Linux,
	Lv2, // PS3	Lv2, // PS3
	MacOSX,	MacOSX,
	MinGW32, // i86-pc-mingw32, -w64-mingw32	MinGW32, // i86-pc-mingw32, -w64-mingw32
	NetBSD,	NetBSD,
	OpenBSD,	OpenBSD,

	Psp,
	Solaris,	Solaris,
	Win32,	Win32,
	Haiku,	Haiku,
	Minix,	Minix,
	RTEMS,	RTEMS,

	NativeClient	NativeClient,
		CNK // BG/P Compute-Node Kernel
	};	};
	enum EnvironmentType {	enum EnvironmentType {
	UnknownEnvironment,	UnknownEnvironment,

	GNU,	GNU,
	GNUEABI,	GNUEABI,

		GNUEABIHF,
	EABI,	EABI,

	MachO	MachO,
		ANDROIDEABI
	};	};

	private:	private:
	std::string Data;	std::string Data;


	/// The parsed arch type (or InvalidArch if uninitialized).	/// The parsed arch type.
	mutable ArchType Arch;	ArchType Arch;

	/// The parsed vendor type.	/// The parsed vendor type.

	mutable VendorType Vendor;	VendorType Vendor;

	/// The parsed OS type.	/// The parsed OS type.

	mutable OSType OS;	OSType OS;

	/// The parsed Environment type.	/// The parsed Environment type.

	mutable EnvironmentType Environment;	EnvironmentType Environment;

	bool isInitialized() const { return Arch != InvalidArch; }
	static ArchType ParseArch(StringRef ArchName);
	static VendorType ParseVendor(StringRef VendorName);
	static OSType ParseOS(StringRef OSName);
	static EnvironmentType ParseEnvironment(StringRef EnvironmentName);
	void Parse() const;

	public:	public:
	/// @name Constructors	/// @name Constructors
	/// @{	/// @{


	Triple() : Data(), Arch(InvalidArch) {}	/// \brief Default constructor is the same as an empty string and leaves
	explicit Triple(const Twine &Str) : Data(Str.str()), Arch(InvalidArch) {}	all
	Triple(const Twine &ArchStr, const Twine &VendorStr, const Twine &OSStr)	/// triple fields unknown.
	: Data((ArchStr + Twine('-') + VendorStr + Twine('-') + OSStr).str()),	Triple() : Data(), Arch(), Vendor(), OS(), Environment() {}
	Arch(InvalidArch) {
	}


		explicit Triple(const Twine &Str);
		Triple(const Twine &ArchStr, const Twine &VendorStr, const Twine &OSStr);
	Triple(const Twine &ArchStr, const Twine &VendorStr, const Twine &OSStr,	Triple(const Twine &ArchStr, const Twine &VendorStr, const Twine &OSStr,

	const Twine &EnvironmentStr)	const Twine &EnvironmentStr);
	: Data((ArchStr + Twine('-') + VendorStr + Twine('-') + OSStr + Twine('
	-') +
	EnvironmentStr).str()), Arch(InvalidArch) {
	}

	/// @}	/// @}
	/// @name Normalization	/// @name Normalization
	/// @{	/// @{

	/// normalize - Turn an arbitrary machine specification into the canonica l	/// normalize - Turn an arbitrary machine specification into the canonica l
	/// triple form (or something sensible that the Triple class understands if	/// triple form (or something sensible that the Triple class understands if
	/// nothing better can reasonably be done). In particular, it handles th e	/// nothing better can reasonably be done). In particular, it handles th e
	/// common case in which otherwise valid components are in the wrong orde r.	/// common case in which otherwise valid components are in the wrong orde r.
	static std::string normalize(StringRef Str);	static std::string normalize(StringRef Str);

	/// @}	/// @}
	/// @name Typed Component Access	/// @name Typed Component Access
	/// @{	/// @{

	/// getArch - Get the parsed architecture type of this triple.	/// getArch - Get the parsed architecture type of this triple.

	ArchType getArch() const {	ArchType getArch() const { return Arch; }
	if (!isInitialized()) Parse();
	return Arch;
	}

	/// getVendor - Get the parsed vendor type of this triple.	/// getVendor - Get the parsed vendor type of this triple.

	VendorType getVendor() const {	VendorType getVendor() const { return Vendor; }
	if (!isInitialized()) Parse();
	return Vendor;
	}

	/// getOS - Get the parsed operating system type of this triple.	/// getOS - Get the parsed operating system type of this triple.

	OSType getOS() const {	OSType getOS() const { return OS; }
	if (!isInitialized()) Parse();
	return OS;
	}

	/// hasEnvironment - Does this triple have the optional environment	/// hasEnvironment - Does this triple have the optional environment
	/// (fourth) component?	/// (fourth) component?
	bool hasEnvironment() const {	bool hasEnvironment() const {
	return getEnvironmentName() != "";	return getEnvironmentName() != "";
	}	}

	/// getEnvironment - Get the parsed environment type of this triple.	/// getEnvironment - Get the parsed environment type of this triple.

	EnvironmentType getEnvironment() const {	EnvironmentType getEnvironment() const { return Environment; }
	if (!isInitialized()) Parse();
	return Environment;	/// getOSVersion - Parse the version number from the OS name component of
		the
		/// triple, if present.
		///
		/// For example, "fooos1.2.3" would return (1, 2, 3).
		///
		/// If an entry is not defined, it will be returned as 0.
		void getOSVersion(unsigned &Major, unsigned &Minor, unsigned &Micro) cons
		t;

		/// getOSMajorVersion - Return just the major version number, this is
		/// specialized because it is a common query.
		unsigned getOSMajorVersion() const {
		unsigned Maj, Min, Micro;
		getOSVersion(Maj, Min, Micro);
		return Maj;
	}	}


		/// getMacOSXVersion - Parse the version number as with getOSVersion and
		then
		/// translate generic "darwin" versions to the corresponding OS X version
		s.
		/// This may also be called with IOS triples but the OS X version number
		is
		/// just set to a constant 10.4.0 in that case. Returns true if successf
		ul.
		bool getMacOSXVersion(unsigned &Major, unsigned &Minor,
		unsigned &Micro) const;

	/// @}	/// @}
	/// @name Direct Component Access	/// @name Direct Component Access
	/// @{	/// @{

	const std::string &str() const { return Data; }	const std::string &str() const { return Data; }

	const std::string &getTriple() const { return Data; }	const std::string &getTriple() const { return Data; }

	/// getArchName - Get the architecture (first) component of the	/// getArchName - Get the architecture (first) component of the
	/// triple.	/// triple.

	skipping to change at line 224	skipping to change at line 225

	/// getEnvironmentName - Get the optional environment (fourth)	/// getEnvironmentName - Get the optional environment (fourth)
	/// component of the triple, or "" if empty.	/// component of the triple, or "" if empty.
	StringRef getEnvironmentName() const;	StringRef getEnvironmentName() const;

	/// getOSAndEnvironmentName - Get the operating system and optional	/// getOSAndEnvironmentName - Get the operating system and optional
	/// environment components as a single string (separated by a '-'	/// environment components as a single string (separated by a '-'
	/// if the environment component is present).	/// if the environment component is present).
	StringRef getOSAndEnvironmentName() const;	StringRef getOSAndEnvironmentName() const;


	/// getOSVersion - Parse the version number from the OS name component of	/// @}
	the	/// @name Convenience Predicates
	/// triple, if present.	/// @{

		/// \brief Test whether the architecture is 64-bit
	///	///

	/// For example, "fooos1.2.3" would return (1, 2, 3).	/// Note that this tests for 64-bit pointer width, and nothing else. Note
		/// that we intentionally expose only three predicates, 64-bit, 32-bit, a
		nd
		/// 16-bit. The inner details of pointer width for particular architectur
		es
		/// is not summed up in the triple, and so only a coarse grained predicat
		e
		/// system is provided.
		bool isArch64Bit() const;

		/// \brief Test whether the architecture is 32-bit
	///	///

	/// If an entry is not defined, it will be returned as 0.	/// Note that this tests for 32-bit pointer width, and nothing else.
	void getOSVersion(unsigned &Major, unsigned &Minor, unsigned &Micro) cons	bool isArch32Bit() const;
	t;


	/// getOSMajorVersion - Return just the major version number, this is	/// \brief Test whether the architecture is 16-bit
	/// specialized because it is a common query.	///
	unsigned getOSMajorVersion() const {	/// Note that this tests for 16-bit pointer width, and nothing else.
	unsigned Maj, Min, Micro;	bool isArch16Bit() const;
	getOSVersion(Maj, Min, Micro);
	return Maj;
	}

	/// isOSVersionLT - Helper function for doing comparisons against version	/// isOSVersionLT - Helper function for doing comparisons against version
	/// numbers included in the target triple.	/// numbers included in the target triple.
	bool isOSVersionLT(unsigned Major, unsigned Minor = 0,	bool isOSVersionLT(unsigned Major, unsigned Minor = 0,
	unsigned Micro = 0) const {	unsigned Micro = 0) const {
	unsigned LHS[3];	unsigned LHS[3];
	getOSVersion(LHS[0], LHS[1], LHS[2]);	getOSVersion(LHS[0], LHS[1], LHS[2]);

	if (LHS[0] != Major)	if (LHS[0] != Major)
	return LHS[0] < Major;	return LHS[0] < Major;
	if (LHS[1] != Minor)	if (LHS[1] != Minor)
	return LHS[1] < Minor;	return LHS[1] < Minor;
	if (LHS[2] != Micro)	if (LHS[2] != Micro)
	return LHS[1] < Micro;	return LHS[1] < Micro;

	return false;	return false;
	}	}


		/// isMacOSXVersionLT - Comparison function for checking OS X version
		/// compatibility, which handles supporting skewed version numbering sche
		mes
		/// used by the "darwin" triples.
		unsigned isMacOSXVersionLT(unsigned Major, unsigned Minor = 0,
		unsigned Micro = 0) const {
		assert(isMacOSX() && "Not an OS X triple!");

		// If this is OS X, expect a sane version number.
		if (getOS() == Triple::MacOSX)
		return isOSVersionLT(Major, Minor, Micro);

		// Otherwise, compare to the "Darwin" number.
		assert(Major == 10 && "Unexpected major version");
		return isOSVersionLT(Minor + 4, Micro, 0);
		}

	/// isMacOSX - Is this a Mac OS X triple. For legacy reasons, we support both	/// isMacOSX - Is this a Mac OS X triple. For legacy reasons, we support both
	/// "darwin" and "osx" as OS X triples.	/// "darwin" and "osx" as OS X triples.
	bool isMacOSX() const {	bool isMacOSX() const {
	return getOS() == Triple::Darwin \|\| getOS() == Triple::MacOSX;	return getOS() == Triple::Darwin \|\| getOS() == Triple::MacOSX;
	}	}

	/// isOSDarwin - Is this a "Darwin" OS (OS X or iOS).	/// isOSDarwin - Is this a "Darwin" OS (OS X or iOS).
	bool isOSDarwin() const {	bool isOSDarwin() const {
	return isMacOSX() \|\| getOS() == Triple::IOS;	return isMacOSX() \|\| getOS() == Triple::IOS;
	}	}


		/// \brief Tests for either Cygwin or MinGW OS
		bool isOSCygMing() const {
		return getOS() == Triple::Cygwin \|\| getOS() == Triple::MinGW32;
		}

	/// isOSWindows - Is this a "Windows" OS.	/// isOSWindows - Is this a "Windows" OS.
	bool isOSWindows() const {	bool isOSWindows() const {

	return getOS() == Triple::Win32 \|\| getOS() == Triple::Cygwin \|\|	return getOS() == Triple::Win32 \|\| isOSCygMing();
	getOS() == Triple::MinGW32;
	}	}


	/// isMacOSXVersionLT - Comparison function for checking OS X version	/// \brief Tests whether the OS uses the ELF binary format.
	/// compatibility, which handles supporting skewed version numbering sche	bool isOSBinFormatELF() const {
	mes	return !isOSDarwin() && !isOSWindows();
	/// used by the "darwin" triples.	}
	unsigned isMacOSXVersionLT(unsigned Major, unsigned Minor = 0,
	unsigned Micro = 0) const {
	assert(isMacOSX() && "Not an OS X triple!");


	// If this is OS X, expect a sane version number.	/// \brief Tests whether the OS uses the COFF binary format.
	if (getOS() == Triple::MacOSX)	bool isOSBinFormatCOFF() const {
	return isOSVersionLT(Major, Minor, Micro);	return isOSWindows();
		}


	// Otherwise, compare to the "Darwin" number.	/// \brief Tests whether the environment is MachO.
	assert(Major == 10 && "Unexpected major version");	// FIXME: Should this be an OSBinFormat predicate?
	return isOSVersionLT(Minor + 4, Micro, 0);	bool isEnvironmentMachO() const {
		return getEnvironment() == Triple::MachO \|\| isOSDarwin();
	}	}

	/// @}	/// @}
	/// @name Mutators	/// @name Mutators
	/// @{	/// @{

	/// setArch - Set the architecture (first) component of the triple	/// setArch - Set the architecture (first) component of the triple
	/// to a known type.	/// to a known type.
	void setArch(ArchType Kind);	void setArch(ArchType Kind);


	skipping to change at line 338	skipping to change at line 366

	/// setOSAndEnvironmentName - Set the operating system and optional	/// setOSAndEnvironmentName - Set the operating system and optional
	/// environment components with a single string.	/// environment components with a single string.
	void setOSAndEnvironmentName(StringRef Str);	void setOSAndEnvironmentName(StringRef Str);

	/// getArchNameForAssembler - Get an architecture name that is understood by	/// getArchNameForAssembler - Get an architecture name that is understood by
	/// the target assembler.	/// the target assembler.
	const char *getArchNameForAssembler();	const char *getArchNameForAssembler();

	/// @}	/// @}

		/// @name Helpers to build variants of a particular triple.
		/// @{

		/// \brief Form a triple with a 32-bit variant of the current architectur
		e.
		///
		/// This can be used to move across "families" of architectures where use
		ful.
		///
		/// \returns A new triple with a 32-bit architecture or an unknown
		/// architecture if no such variant can be found.
		llvm::Triple get32BitArchVariant() const;

		/// \brief Form a triple with a 64-bit variant of the current architectur
		e.
		///
		/// This can be used to move across "families" of architectures where use
		ful.
		///
		/// \returns A new triple with a 64-bit architecture or an unknown
		/// architecture if no such variant can be found.
		llvm::Triple get64BitArchVariant() const;

		/// @}
	/// @name Static helpers for IDs.	/// @name Static helpers for IDs.
	/// @{	/// @{

	/// getArchTypeName - Get the canonical name for the \arg Kind	/// getArchTypeName - Get the canonical name for the \arg Kind
	/// architecture.	/// architecture.
	static const char *getArchTypeName(ArchType Kind);	static const char *getArchTypeName(ArchType Kind);

	/// getArchTypePrefix - Get the "prefix" canonical name for the \arg Kind	/// getArchTypePrefix - Get the "prefix" canonical name for the \arg Kind
	/// architecture. This is the prefix used by the architecture specific	/// architecture. This is the prefix used by the architecture specific
	/// builtins, and is suitable for passing to \see	/// builtins, and is suitable for passing to \see

End of changes. 35 change blocks.
	78 lines changed or deleted	137 lines changed or added

	Twine.h	Twine.h

	skipping to change at line 15	skipping to change at line 15
	// This file is distributed under the University of Illinois Open Source	// This file is distributed under the University of Illinois Open Source
	// License. See LICENSE.TXT for details.	// License. See LICENSE.TXT for details.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_ADT_TWINE_H	#ifndef LLVM_ADT_TWINE_H
	#define LLVM_ADT_TWINE_H	#define LLVM_ADT_TWINE_H

	#include "llvm/ADT/StringRef.h"	#include "llvm/ADT/StringRef.h"
	#include "llvm/Support/DataTypes.h"	#include "llvm/Support/DataTypes.h"

		#include "llvm/Support/ErrorHandling.h"
	#include <cassert>	#include <cassert>
	#include <string>	#include <string>

	namespace llvm {	namespace llvm {
	template <typename T>	template <typename T>
	class SmallVectorImpl;	class SmallVectorImpl;
	class StringRef;	class StringRef;
	class raw_ostream;	class raw_ostream;

	/// Twine - A lightweight data structure for efficiently representing the	/// Twine - A lightweight data structure for efficiently representing the

	skipping to change at line 428	skipping to change at line 429

	/// toVector - Write the concatenated string into the given SmallString or	/// toVector - Write the concatenated string into the given SmallString or
	/// SmallVector.	/// SmallVector.
	void toVector(SmallVectorImpl<char> &Out) const;	void toVector(SmallVectorImpl<char> &Out) const;

	/// getSingleStringRef - This returns the twine as a single StringRef. This	/// getSingleStringRef - This returns the twine as a single StringRef. This
	/// method is only valid if isSingleStringRef() is true.	/// method is only valid if isSingleStringRef() is true.
	StringRef getSingleStringRef() const {	StringRef getSingleStringRef() const {
	assert(isSingleStringRef() &&"This cannot be had as a single stringre f!");	assert(isSingleStringRef() &&"This cannot be had as a single stringre f!");
	switch (getLHSKind()) {	switch (getLHSKind()) {

	default: assert(0 && "Out of sync with isSingleStringRef");	default: llvm_unreachable("Out of sync with isSingleStringRef");
	case EmptyKind: return StringRef();	case EmptyKind: return StringRef();
	case CStringKind: return StringRef(LHS.cString);	case CStringKind: return StringRef(LHS.cString);
	case StdStringKind: return StringRef(*LHS.stdString);	case StdStringKind: return StringRef(*LHS.stdString);
	case StringRefKind: return *LHS.stringRef;	case StringRefKind: return *LHS.stringRef;
	}	}
	}	}

	/// toStringRef - This returns the twine as a single StringRef if it ca n be	/// toStringRef - This returns the twine as a single StringRef if it ca n be
	/// represented as such. Otherwise the twine is written into the given	/// represented as such. Otherwise the twine is written into the given
	/// SmallVector and a StringRef to the SmallVector's data is returned.	/// SmallVector and a StringRef to the SmallVector's data is returned.

End of changes. 2 change blocks.
	1 lines changed or deleted	2 lines changed or added

	Type.h	Type.h

	skipping to change at line 19	skipping to change at line 19
	//	//
	// This file contains the declaration of the Type class. For more "Type"	// This file contains the declaration of the Type class. For more "Type"
	// stuff, look in DerivedTypes.h.	// stuff, look in DerivedTypes.h.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_TYPE_H	#ifndef LLVM_TYPE_H
	#define LLVM_TYPE_H	#define LLVM_TYPE_H

	#include "llvm/Support/Casting.h"	#include "llvm/Support/Casting.h"

		#include "llvm/Support/DataTypes.h"

	namespace llvm {	namespace llvm {

	class PointerType;	class PointerType;
	class IntegerType;	class IntegerType;
	class raw_ostream;	class raw_ostream;
	class Module;	class Module;
	class LLVMContext;	class LLVMContext;
	class LLVMContextImpl;	class LLVMContextImpl;

		class StringRef;
	template<class GraphType> struct GraphTraits;	template<class GraphType> struct GraphTraits;

	/// The instances of the Type class are immutable: once they are created,	/// The instances of the Type class are immutable: once they are created,
	/// they are never changed. Also note that only one instance of a particul ar	/// they are never changed. Also note that only one instance of a particul ar
	/// type is ever created. Thus seeing if two types are equal is a matter o f	/// type is ever created. Thus seeing if two types are equal is a matter o f
	/// doing a trivial pointer comparison. To enforce that no two equal instan ces	/// doing a trivial pointer comparison. To enforce that no two equal instan ces
	/// are created, Type instances can only be created via static factory meth ods	/// are created, Type instances can only be created via static factory meth ods
	/// in class Type and in derived classes. Once allocated, Types are never	/// in class Type and in derived classes. Once allocated, Types are never
	/// free'd.	/// free'd.
	///	///

	skipping to change at line 50	skipping to change at line 52
	//===-------------------------------------------------------------------- ===//	//===-------------------------------------------------------------------- ===//
	/// Definitions of all of the base types for the Type system. Based on t his	/// Definitions of all of the base types for the Type system. Based on t his
	/// value, you can cast to a class defined in DerivedTypes.h.	/// value, you can cast to a class defined in DerivedTypes.h.
	/// Note: If you add an element to this, you need to add an element to th e	/// Note: If you add an element to this, you need to add an element to th e
	/// Type::getPrimitiveType function, or else things will break!	/// Type::getPrimitiveType function, or else things will break!
	/// Also update LLVMTypeKind and LLVMGetTypeKind () in the C binding.	/// Also update LLVMTypeKind and LLVMGetTypeKind () in the C binding.
	///	///
	enum TypeID {	enum TypeID {
	// PrimitiveTypes - make sure LastPrimitiveTyID stays up to date.	// PrimitiveTypes - make sure LastPrimitiveTyID stays up to date.
	VoidTyID = 0, ///< 0: type with no size	VoidTyID = 0, ///< 0: type with no size

	FloatTyID, ///< 1: 32-bit floating point type	HalfTyID, ///< 1: 16-bit floating point type
	DoubleTyID, ///< 2: 64-bit floating point type	FloatTyID, ///< 2: 32-bit floating point type
	X86_FP80TyID, ///< 3: 80-bit floating point type (X87)	DoubleTyID, ///< 3: 64-bit floating point type
	FP128TyID, ///< 4: 128-bit floating point type (112-bit mantissa	X86_FP80TyID, ///< 4: 80-bit floating point type (X87)
	)	FP128TyID, ///< 5: 128-bit floating point type (112-bit mantissa
	PPC_FP128TyID, ///< 5: 128-bit floating point type (two 64-bits, Pow	)
	erPC)	PPC_FP128TyID, ///< 6: 128-bit floating point type (two 64-bits, Pow
	LabelTyID, ///< 6: Labels	erPC)
	MetadataTyID, ///< 7: Metadata	LabelTyID, ///< 7: Labels
	X86_MMXTyID, ///< 8: MMX vectors (64 bits, X86 specific)	MetadataTyID, ///< 8: Metadata
		X86_MMXTyID, ///< 9: MMX vectors (64 bits, X86 specific)

	// Derived types... see DerivedTypes.h file.	// Derived types... see DerivedTypes.h file.
	// Make sure FirstDerivedTyID stays up to date!	// Make sure FirstDerivedTyID stays up to date!

	IntegerTyID, ///< 9: Arbitrary bit width integers	IntegerTyID, ///< 10: Arbitrary bit width integers
	FunctionTyID, ///< 10: Functions	FunctionTyID, ///< 11: Functions
	StructTyID, ///< 11: Structures	StructTyID, ///< 12: Structures
	ArrayTyID, ///< 12: Arrays	ArrayTyID, ///< 13: Arrays
	PointerTyID, ///< 13: Pointers	PointerTyID, ///< 14: Pointers
	VectorTyID, ///< 14: SIMD 'packed' format, or other vector type	VectorTyID, ///< 15: SIMD 'packed' format, or other vector type

	NumTypeIDs, // Must remain as last defined ID	NumTypeIDs, // Must remain as last defined ID
	LastPrimitiveTyID = X86_MMXTyID,	LastPrimitiveTyID = X86_MMXTyID,
	FirstDerivedTyID = IntegerTyID	FirstDerivedTyID = IntegerTyID
	};	};

	private:	private:
	/// Context - This refers to the LLVMContext in which this type was uniqu ed.	/// Context - This refers to the LLVMContext in which this type was uniqu ed.
	LLVMContext &Context;	LLVMContext &Context;


	TypeID ID : 8; // The current base type of this type.	// Due to Ubuntu GCC bug 910363:
	unsigned SubclassData : 24; // Space for subclasses to store data	// https://bugs.launchpad.net/ubuntu/+source/gcc-4.5/+bug/910363
		// Bitpack ID and SubclassData manually.
		// Note: TypeID : low 8 bit; SubclassData : high 24 bit.
		uint32_t IDAndSubclassData;

	protected:	protected:
	friend class LLVMContextImpl;	friend class LLVMContextImpl;
	explicit Type(LLVMContext &C, TypeID tid)	explicit Type(LLVMContext &C, TypeID tid)

	: Context(C), ID(tid), SubclassData(0),	: Context(C), IDAndSubclassData(0),
	NumContainedTys(0), ContainedTys(0) {}	NumContainedTys(0), ContainedTys(0) {
		setTypeID(tid);
		}
	~Type() {}	~Type() {}


	unsigned getSubclassData() const { return SubclassData; }	void setTypeID(TypeID ID) {
		IDAndSubclassData = (ID & 0xFF) \| (IDAndSubclassData & 0xFFFFFF00);
		assert(getTypeID() == ID && "TypeID data too large for field");
		}

		unsigned getSubclassData() const { return IDAndSubclassData >> 8; }

	void setSubclassData(unsigned val) {	void setSubclassData(unsigned val) {

	SubclassData = val;	IDAndSubclassData = (IDAndSubclassData & 0xFF) \| (val << 8);
	// Ensure we don't have any accidental truncation.	// Ensure we don't have any accidental truncation.

	assert(SubclassData == val && "Subclass data too large for field");	assert(getSubclassData() == val && "Subclass data too large for field") ;
	}	}

	/// NumContainedTys - Keeps track of how many Type*'s there are in the	/// NumContainedTys - Keeps track of how many Type*'s there are in the
	/// ContainedTys list.	/// ContainedTys list.
	unsigned NumContainedTys;	unsigned NumContainedTys;

	/// ContainedTys - A pointer to the array of Types contained by this Type .	/// ContainedTys - A pointer to the array of Types contained by this Type .
	/// For example, this includes the arguments of a function type, the elem ents	/// For example, this includes the arguments of a function type, the elem ents
	/// of a structure, the pointee of a pointer, the element type of an arra y,	/// of a structure, the pointee of a pointer, the element type of an arra y,
	/// etc. This pointer may be 0 for types that don't contain other types	/// etc. This pointer may be 0 for types that don't contain other types

	skipping to change at line 119	skipping to change at line 133
	/// getContext - Return the LLVMContext in which this type was uniqued.	/// getContext - Return the LLVMContext in which this type was uniqued.
	LLVMContext &getContext() const { return Context; }	LLVMContext &getContext() const { return Context; }

	//===-------------------------------------------------------------------- ===//	//===-------------------------------------------------------------------- ===//
	// Accessors for working with types.	// Accessors for working with types.
	//	//

	/// getTypeID - Return the type id for the type. This will return one	/// getTypeID - Return the type id for the type. This will return one
	/// of the TypeID enum elements defined above.	/// of the TypeID enum elements defined above.
	///	///

	TypeID getTypeID() const { return ID; }	TypeID getTypeID() const { return (TypeID)(IDAndSubclassData & 0xFF); }

	/// isVoidTy - Return true if this is 'void'.	/// isVoidTy - Return true if this is 'void'.

	bool isVoidTy() const { return ID == VoidTyID; }	bool isVoidTy() const { return getTypeID() == VoidTyID; }

		/// isHalfTy - Return true if this is 'half', a 16-bit IEEE fp type.
		bool isHalfTy() const { return getTypeID() == HalfTyID; }

	/// isFloatTy - Return true if this is 'float', a 32-bit IEEE fp type.	/// isFloatTy - Return true if this is 'float', a 32-bit IEEE fp type.

	bool isFloatTy() const { return ID == FloatTyID; }	bool isFloatTy() const { return getTypeID() == FloatTyID; }

	/// isDoubleTy - Return true if this is 'double', a 64-bit IEEE fp type.	/// isDoubleTy - Return true if this is 'double', a 64-bit IEEE fp type.

	bool isDoubleTy() const { return ID == DoubleTyID; }	bool isDoubleTy() const { return getTypeID() == DoubleTyID; }

	/// isX86_FP80Ty - Return true if this is x86 long double.	/// isX86_FP80Ty - Return true if this is x86 long double.

	bool isX86_FP80Ty() const { return ID == X86_FP80TyID; }	bool isX86_FP80Ty() const { return getTypeID() == X86_FP80TyID; }

	/// isFP128Ty - Return true if this is 'fp128'.	/// isFP128Ty - Return true if this is 'fp128'.

	bool isFP128Ty() const { return ID == FP128TyID; }	bool isFP128Ty() const { return getTypeID() == FP128TyID; }

	/// isPPC_FP128Ty - Return true if this is powerpc long double.	/// isPPC_FP128Ty - Return true if this is powerpc long double.

	bool isPPC_FP128Ty() const { return ID == PPC_FP128TyID; }	bool isPPC_FP128Ty() const { return getTypeID() == PPC_FP128TyID; }

	/// isFloatingPointTy - Return true if this is one of the five floating p oint	/// isFloatingPointTy - Return true if this is one of the five floating p oint
	/// types	/// types
	bool isFloatingPointTy() const {	bool isFloatingPointTy() const {

	return ID == FloatTyID \|\| ID == DoubleTyID \|\|	return getTypeID() == HalfTyID \|\| getTypeID() == FloatTyID \|\|
	ID == X86_FP80TyID \|\| ID == FP128TyID \|\| ID == PPC_FP128TyID;	getTypeID() == DoubleTyID \|\|
		getTypeID() == X86_FP80TyID \|\| getTypeID() == FP128TyID \|\|
		getTypeID() == PPC_FP128TyID;
	}	}

	/// isX86_MMXTy - Return true if this is X86 MMX.	/// isX86_MMXTy - Return true if this is X86 MMX.

	bool isX86_MMXTy() const { return ID == X86_MMXTyID; }	bool isX86_MMXTy() const { return getTypeID() == X86_MMXTyID; }

	/// isFPOrFPVectorTy - Return true if this is a FP type or a vector of FP .	/// isFPOrFPVectorTy - Return true if this is a FP type or a vector of FP .
	///	///
	bool isFPOrFPVectorTy() const;	bool isFPOrFPVectorTy() const;

	/// isLabelTy - Return true if this is 'label'.	/// isLabelTy - Return true if this is 'label'.

	bool isLabelTy() const { return ID == LabelTyID; }	bool isLabelTy() const { return getTypeID() == LabelTyID; }

	/// isMetadataTy - Return true if this is 'metadata'.	/// isMetadataTy - Return true if this is 'metadata'.

	bool isMetadataTy() const { return ID == MetadataTyID; }	bool isMetadataTy() const { return getTypeID() == MetadataTyID; }

	/// isIntegerTy - True if this is an instance of IntegerType.	/// isIntegerTy - True if this is an instance of IntegerType.
	///	///

	bool isIntegerTy() const { return ID == IntegerTyID; }	bool isIntegerTy() const { return getTypeID() == IntegerTyID; }

	/// isIntegerTy - Return true if this is an IntegerType of the given widt h.	/// isIntegerTy - Return true if this is an IntegerType of the given widt h.
	bool isIntegerTy(unsigned Bitwidth) const;	bool isIntegerTy(unsigned Bitwidth) const;

	/// isIntOrIntVectorTy - Return true if this is an integer type or a vect or of	/// isIntOrIntVectorTy - Return true if this is an integer type or a vect or of
	/// integer types.	/// integer types.
	///	///
	bool isIntOrIntVectorTy() const;	bool isIntOrIntVectorTy() const;

	/// isFunctionTy - True if this is an instance of FunctionType.	/// isFunctionTy - True if this is an instance of FunctionType.
	///	///

	bool isFunctionTy() const { return ID == FunctionTyID; }	bool isFunctionTy() const { return getTypeID() == FunctionTyID; }

	/// isStructTy - True if this is an instance of StructType.	/// isStructTy - True if this is an instance of StructType.
	///	///

	bool isStructTy() const { return ID == StructTyID; }	bool isStructTy() const { return getTypeID() == StructTyID; }

	/// isArrayTy - True if this is an instance of ArrayType.	/// isArrayTy - True if this is an instance of ArrayType.
	///	///

	bool isArrayTy() const { return ID == ArrayTyID; }	bool isArrayTy() const { return getTypeID() == ArrayTyID; }

	/// isPointerTy - True if this is an instance of PointerType.	/// isPointerTy - True if this is an instance of PointerType.
	///	///

	bool isPointerTy() const { return ID == PointerTyID; }	bool isPointerTy() const { return getTypeID() == PointerTyID; }

	/// isVectorTy - True if this is an instance of VectorType.	/// isVectorTy - True if this is an instance of VectorType.
	///	///

	bool isVectorTy() const { return ID == VectorTyID; }	bool isVectorTy() const { return getTypeID() == VectorTyID; }

	/// canLosslesslyBitCastTo - Return true if this type could be converted	/// canLosslesslyBitCastTo - Return true if this type could be converted
	/// with a lossless BitCast to type 'Ty'. For example, i8* to i32*. BitCa sts	/// with a lossless BitCast to type 'Ty'. For example, i8* to i32*. BitCa sts
	/// are valid for types of the same size only where no re-interpretation of	/// are valid for types of the same size only where no re-interpretation of
	/// the bits is done.	/// the bits is done.
	/// @brief Determine if this type could be losslessly bitcast to Ty	/// @brief Determine if this type could be losslessly bitcast to Ty
	bool canLosslesslyBitCastTo(Type *Ty) const;	bool canLosslesslyBitCastTo(Type *Ty) const;

	/// isEmptyTy - Return true if this type is empty, that is, it has no	/// isEmptyTy - Return true if this type is empty, that is, it has no
	/// elements or all its elements are empty.	/// elements or all its elements are empty.
	bool isEmptyTy() const;	bool isEmptyTy() const;

	/// Here are some useful little methods to query what type derived types are	/// Here are some useful little methods to query what type derived types are
	/// Note that all other types can just compare to see if this == Type::xx xTy;	/// Note that all other types can just compare to see if this == Type::xx xTy;
	///	///

	bool isPrimitiveType() const { return ID <= LastPrimitiveTyID; }	bool isPrimitiveType() const { return getTypeID() <= LastPrimitiveTyID; }
	bool isDerivedType() const { return ID >= FirstDerivedTyID; }	bool isDerivedType() const { return getTypeID() >= FirstDerivedTyID; }

	/// isFirstClassType - Return true if the type is "first class", meaning it	/// isFirstClassType - Return true if the type is "first class", meaning it
	/// is a valid type for a Value.	/// is a valid type for a Value.
	///	///
	bool isFirstClassType() const {	bool isFirstClassType() const {

	return ID != FunctionTyID && ID != VoidTyID;	return getTypeID() != FunctionTyID && getTypeID() != VoidTyID;
	}	}

	/// isSingleValueType - Return true if the type is a valid type for a	/// isSingleValueType - Return true if the type is a valid type for a
	/// register in codegen. This includes all first-class types except stru ct	/// register in codegen. This includes all first-class types except stru ct
	/// and array types.	/// and array types.
	///	///
	bool isSingleValueType() const {	bool isSingleValueType() const {

	return (ID != VoidTyID && isPrimitiveType()) \|\|	return (getTypeID() != VoidTyID && isPrimitiveType()) \|\|
	ID == IntegerTyID \|\| ID == PointerTyID \|\| ID == VectorTyID;	getTypeID() == IntegerTyID \|\| getTypeID() == PointerTyID \|\|
		getTypeID() == VectorTyID;
	}	}

	/// isAggregateType - Return true if the type is an aggregate type. This	/// isAggregateType - Return true if the type is an aggregate type. This
	/// means it is valid as the first operand of an insertvalue or	/// means it is valid as the first operand of an insertvalue or
	/// extractvalue instruction. This includes struct and array types, but	/// extractvalue instruction. This includes struct and array types, but
	/// does not include vector types.	/// does not include vector types.
	///	///
	bool isAggregateType() const {	bool isAggregateType() const {

	return ID == StructTyID \|\| ID == ArrayTyID;	return getTypeID() == StructTyID \|\| getTypeID() == ArrayTyID;
	}	}

	/// isSized - Return true if it makes sense to take the size of this type . To	/// isSized - Return true if it makes sense to take the size of this type . To
	/// get the actual size for a particular target, it is reasonable to use the	/// get the actual size for a particular target, it is reasonable to use the
	/// TargetData subsystem to do this.	/// TargetData subsystem to do this.
	///	///
	bool isSized() const {	bool isSized() const {
	// If it's a primitive, it is always sized.	// If it's a primitive, it is always sized.

	if (ID == IntegerTyID \|\| isFloatingPointTy() \|\| ID == PointerTyID \|\|	if (getTypeID() == IntegerTyID \|\| isFloatingPointTy() \|\|
	ID == X86_MMXTyID)	getTypeID() == PointerTyID \|\|
		getTypeID() == X86_MMXTyID)
	return true;	return true;
	// If it is not something that can have a size (e.g. a function or labe l),	// If it is not something that can have a size (e.g. a function or labe l),
	// it doesn't have a size.	// it doesn't have a size.

	if (ID != StructTyID && ID != ArrayTyID && ID != VectorTyID)	if (getTypeID() != StructTyID && getTypeID() != ArrayTyID &&
		getTypeID() != VectorTyID)
	return false;	return false;
	// Otherwise we have to try harder to decide.	// Otherwise we have to try harder to decide.
	return isSizedDerivedType();	return isSizedDerivedType();
	}	}

	/// getPrimitiveSizeInBits - Return the basic size of this type if it is a	/// getPrimitiveSizeInBits - Return the basic size of this type if it is a
	/// primitive type. These are fixed by LLVM and are not target dependent .	/// primitive type. These are fixed by LLVM and are not target dependent .
	/// This will return zero if the type does not have a size or is not a	/// This will return zero if the type does not have a size or is not a
	/// primitive type.	/// primitive type.
	///	///

	skipping to change at line 297	skipping to change at line 319
	Type *getContainedType(unsigned i) const {	Type *getContainedType(unsigned i) const {
	assert(i < NumContainedTys && "Index out of range!");	assert(i < NumContainedTys && "Index out of range!");
	return ContainedTys[i];	return ContainedTys[i];
	}	}

	/// getNumContainedTypes - Return the number of types in the derived type .	/// getNumContainedTypes - Return the number of types in the derived type .
	///	///
	unsigned getNumContainedTypes() const { return NumContainedTys; }	unsigned getNumContainedTypes() const { return NumContainedTys; }

	//===-------------------------------------------------------------------- ===//	//===-------------------------------------------------------------------- ===//

		// Helper methods corresponding to subclass methods. This forces a cast
		to
		// the specified subclass and calls its accessor. "getVectorNumElements"
		(for
		// example) is shorthand for cast<VectorType>(Ty)->getNumElements(). Thi
		s is
		// only intended to cover the core methods that are frequently used, help
		er
		// methods should not be added here.

		unsigned getIntegerBitWidth() const;

		Type *getFunctionParamType(unsigned i) const;
		unsigned getFunctionNumParams() const;
		bool isFunctionVarArg() const;

		StringRef getStructName() const;
		unsigned getStructNumElements() const;
		Type *getStructElementType(unsigned N) const;

		Type *getSequentialElementType() const;

		uint64_t getArrayNumElements() const;
		Type *getArrayElementType() const { return getSequentialElementType(); }

		unsigned getVectorNumElements() const;
		Type *getVectorElementType() const { return getSequentialElementType(); }

		unsigned getPointerAddressSpace() const;
		Type *getPointerElementType() const { return getSequentialElementType();
		}

		//===--------------------------------------------------------------------
		===//
	// Static members exported by the Type class itself. Useful for getting	// Static members exported by the Type class itself. Useful for getting
	// instances of Type.	// instances of Type.
	//	//

	/// getPrimitiveType - Return a type based on an identifier.	/// getPrimitiveType - Return a type based on an identifier.
	static Type *getPrimitiveType(LLVMContext &C, TypeID IDNumber);	static Type *getPrimitiveType(LLVMContext &C, TypeID IDNumber);

	//===-------------------------------------------------------------------- ===//	//===-------------------------------------------------------------------- ===//
	// These are the builtin types that are always available.	// These are the builtin types that are always available.
	//	//
	static Type *getVoidTy(LLVMContext &C);	static Type *getVoidTy(LLVMContext &C);
	static Type *getLabelTy(LLVMContext &C);	static Type *getLabelTy(LLVMContext &C);

		static Type *getHalfTy(LLVMContext &C);
	static Type *getFloatTy(LLVMContext &C);	static Type *getFloatTy(LLVMContext &C);
	static Type *getDoubleTy(LLVMContext &C);	static Type *getDoubleTy(LLVMContext &C);
	static Type *getMetadataTy(LLVMContext &C);	static Type *getMetadataTy(LLVMContext &C);
	static Type *getX86_FP80Ty(LLVMContext &C);	static Type *getX86_FP80Ty(LLVMContext &C);
	static Type *getFP128Ty(LLVMContext &C);	static Type *getFP128Ty(LLVMContext &C);
	static Type *getPPC_FP128Ty(LLVMContext &C);	static Type *getPPC_FP128Ty(LLVMContext &C);
	static Type *getX86_MMXTy(LLVMContext &C);	static Type *getX86_MMXTy(LLVMContext &C);
	static IntegerType *getIntNTy(LLVMContext &C, unsigned N);	static IntegerType *getIntNTy(LLVMContext &C, unsigned N);
	static IntegerType *getInt1Ty(LLVMContext &C);	static IntegerType *getInt1Ty(LLVMContext &C);
	static IntegerType *getInt8Ty(LLVMContext &C);	static IntegerType *getInt8Ty(LLVMContext &C);
	static IntegerType *getInt16Ty(LLVMContext &C);	static IntegerType *getInt16Ty(LLVMContext &C);
	static IntegerType *getInt32Ty(LLVMContext &C);	static IntegerType *getInt32Ty(LLVMContext &C);
	static IntegerType *getInt64Ty(LLVMContext &C);	static IntegerType *getInt64Ty(LLVMContext &C);

	//===-------------------------------------------------------------------- ===//	//===-------------------------------------------------------------------- ===//
	// Convenience methods for getting pointer types with one of the above bu iltin	// Convenience methods for getting pointer types with one of the above bu iltin
	// types as pointee.	// types as pointee.
	//	//

		static PointerType *getHalfPtrTy(LLVMContext &C, unsigned AS = 0);
	static PointerType *getFloatPtrTy(LLVMContext &C, unsigned AS = 0);	static PointerType *getFloatPtrTy(LLVMContext &C, unsigned AS = 0);
	static PointerType *getDoublePtrTy(LLVMContext &C, unsigned AS = 0);	static PointerType *getDoublePtrTy(LLVMContext &C, unsigned AS = 0);
	static PointerType *getX86_FP80PtrTy(LLVMContext &C, unsigned AS = 0);	static PointerType *getX86_FP80PtrTy(LLVMContext &C, unsigned AS = 0);
	static PointerType *getFP128PtrTy(LLVMContext &C, unsigned AS = 0);	static PointerType *getFP128PtrTy(LLVMContext &C, unsigned AS = 0);
	static PointerType *getPPC_FP128PtrTy(LLVMContext &C, unsigned AS = 0);	static PointerType *getPPC_FP128PtrTy(LLVMContext &C, unsigned AS = 0);
	static PointerType *getX86_MMXPtrTy(LLVMContext &C, unsigned AS = 0);	static PointerType *getX86_MMXPtrTy(LLVMContext &C, unsigned AS = 0);
	static PointerType *getIntNPtrTy(LLVMContext &C, unsigned N, unsigned AS = 0);	static PointerType *getIntNPtrTy(LLVMContext &C, unsigned N, unsigned AS = 0);
	static PointerType *getInt1PtrTy(LLVMContext &C, unsigned AS = 0);	static PointerType *getInt1PtrTy(LLVMContext &C, unsigned AS = 0);
	static PointerType *getInt8PtrTy(LLVMContext &C, unsigned AS = 0);	static PointerType *getInt8PtrTy(LLVMContext &C, unsigned AS = 0);
	static PointerType *getInt16PtrTy(LLVMContext &C, unsigned AS = 0);	static PointerType *getInt16PtrTy(LLVMContext &C, unsigned AS = 0);

End of changes. 35 change blocks.
	50 lines changed or deleted	108 lines changed or added

	UnrollLoop.h	UnrollLoop.h

	skipping to change at line 25	skipping to change at line 25

	#ifndef LLVM_TRANSFORMS_UTILS_UNROLLLOOP_H	#ifndef LLVM_TRANSFORMS_UTILS_UNROLLLOOP_H
	#define LLVM_TRANSFORMS_UTILS_UNROLLLOOP_H	#define LLVM_TRANSFORMS_UTILS_UNROLLLOOP_H

	namespace llvm {	namespace llvm {

	class Loop;	class Loop;
	class LoopInfo;	class LoopInfo;
	class LPPassManager;	class LPPassManager;


	bool UnrollLoop(Loop *L, unsigned Count, unsigned TripCount,	bool UnrollLoop(Loop *L, unsigned Count, unsigned TripCount, bool AllowRunt ime,
	unsigned TripMultiple, LoopInfo* LI, LPPassManager* LPM);	unsigned TripMultiple, LoopInfo* LI, LPPassManager* LPM);


		bool UnrollRuntimeLoopProlog(Loop L, unsigned Count, LoopInfo LI,
		LPPassManager* LPM);

	}	}

	#endif	#endif

End of changes. 2 change blocks.
	1 lines changed or deleted	4 lines changed or added

	User.h	User.h

	skipping to change at line 22	skipping to change at line 22
	// to it.	// to it.
	//	//
	// * Instructions are the largest class of User's.	// * Instructions are the largest class of User's.
	// * Constants may be users of other constants (think arrays and stuff)	// * Constants may be users of other constants (think arrays and stuff)
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_USER_H	#ifndef LLVM_USER_H
	#define LLVM_USER_H	#define LLVM_USER_H


		#include "llvm/Support/ErrorHandling.h"
	#include "llvm/Value.h"	#include "llvm/Value.h"

	namespace llvm {	namespace llvm {

	/// OperandTraits - Compile-time customization of	/// OperandTraits - Compile-time customization of
	/// operand-related allocators and accessors	/// operand-related allocators and accessors
	/// for use of the User class	/// for use of the User class
	template <class>	template <class>
	struct OperandTraits;	struct OperandTraits;

	class User : public Value {	class User : public Value {
	User(const User &); // Do not implement	User(const User &); // Do not implement
	void *operator new(size_t); // Do not implement	void *operator new(size_t); // Do not implement
	template <unsigned>	template <unsigned>
	friend struct HungoffOperandTraits;	friend struct HungoffOperandTraits;

		virtual void anchor();
	protected:	protected:
	/// OperandList - This is a pointer to the array of Uses for this User.	/// OperandList - This is a pointer to the array of Uses for this User.
	/// For nodes of fixed arity (e.g. a binary operator) this array will liv e	/// For nodes of fixed arity (e.g. a binary operator) this array will liv e
	/// prefixed to some derived class instance. For nodes of resizable vari able	/// prefixed to some derived class instance. For nodes of resizable vari able
	/// arity (e.g. PHINodes, SwitchInst etc.), this memory will be dynamical ly	/// arity (e.g. PHINodes, SwitchInst etc.), this memory will be dynamical ly
	/// allocated and should be destroyed by the classes' virtual dtor.	/// allocated and should be destroyed by the classes' virtual dtor.
	Use *OperandList;	Use *OperandList;

	/// NumOperands - The number of values used by this User.	/// NumOperands - The number of values used by this User.
	///	///

	skipping to change at line 67	skipping to change at line 69
	NumOperands = 0;	NumOperands = 0;
	}	}
	public:	public:
	~User() {	~User() {
	Use::zap(OperandList, OperandList + NumOperands);	Use::zap(OperandList, OperandList + NumOperands);
	}	}
	/// operator delete - free memory allocated for User and Use objects	/// operator delete - free memory allocated for User and Use objects
	void operator delete(void *Usr);	void operator delete(void *Usr);
	/// placement delete - required by std, but never called.	/// placement delete - required by std, but never called.
	void operator delete(void*, unsigned) {	void operator delete(void*, unsigned) {

	assert(0 && "Constructor throws?");	llvm_unreachable("Constructor throws?");
	}	}
	/// placement delete - required by std, but never called.	/// placement delete - required by std, but never called.
	void operator delete(void*, unsigned, bool) {	void operator delete(void*, unsigned, bool) {

	assert(0 && "Constructor throws?");	llvm_unreachable("Constructor throws?");
	}	}
	protected:	protected:
	template <int Idx, typename U> static Use &OpFrom(const U *that) {	template <int Idx, typename U> static Use &OpFrom(const U *that) {
	return Idx < 0	return Idx < 0
	? OperandTraits<U>::op_end(const_cast<U*>(that))[Idx]	? OperandTraits<U>::op_end(const_cast<U*>(that))[Idx]
	: OperandTraits<U>::op_begin(const_cast<U*>(that))[Idx];	: OperandTraits<U>::op_begin(const_cast<U*>(that))[Idx];
	}	}
	template <int Idx> Use &Op() {	template <int Idx> Use &Op() {
	return OpFrom<Idx>(this);	return OpFrom<Idx>(this);
	}	}

End of changes. 4 change blocks.
	2 lines changed or deleted	4 lines changed or added

	Valgrind.h	Valgrind.h

	skipping to change at line 19	skipping to change at line 19
	//	//
	// Methods for communicating with a valgrind instance this program is runni ng	// Methods for communicating with a valgrind instance this program is runni ng
	// under. These are all no-ops unless LLVM was configured on a system with the	// under. These are all no-ops unless LLVM was configured on a system with the
	// valgrind headers installed and valgrind is controlling this process.	// valgrind headers installed and valgrind is controlling this process.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_SYSTEM_VALGRIND_H	#ifndef LLVM_SYSTEM_VALGRIND_H
	#define LLVM_SYSTEM_VALGRIND_H	#define LLVM_SYSTEM_VALGRIND_H


		#include "llvm/Support/Compiler.h"
		#include "llvm/Config/llvm-config.h"
	#include <stddef.h>	#include <stddef.h>


		#if LLVM_ENABLE_THREADS != 0 && !defined(NDEBUG)
		// tsan (Thread Sanitizer) is a valgrind-based tool that detects these exac
		t
		// functions by name.
		extern "C" {
		LLVM_ATTRIBUTE_WEAK void AnnotateHappensAfter(const char *file, int line,
		const volatile void *cv);
		LLVM_ATTRIBUTE_WEAK void AnnotateHappensBefore(const char *file, int line,
		const volatile void *cv);
		LLVM_ATTRIBUTE_WEAK void AnnotateIgnoreWritesBegin(const char *file, int li
		ne);
		LLVM_ATTRIBUTE_WEAK void AnnotateIgnoreWritesEnd(const char *file, int line
		);
		}
		#endif

	namespace llvm {	namespace llvm {
	namespace sys {	namespace sys {
	// True if Valgrind is controlling this process.	// True if Valgrind is controlling this process.
	bool RunningOnValgrind();	bool RunningOnValgrind();

	// Discard valgrind's translation of code in the range [Addr .. Addr + Le n).	// Discard valgrind's translation of code in the range [Addr .. Addr + Le n).
	// Otherwise valgrind may continue to execute the old version of the code .	// Otherwise valgrind may continue to execute the old version of the code .
	void ValgrindDiscardTranslations(const void *Addr, size_t Len);	void ValgrindDiscardTranslations(const void *Addr, size_t Len);


		#if LLVM_ENABLE_THREADS != 0 && !defined(NDEBUG)
		// Thread Sanitizer is a valgrind tool that finds races in code.
		// See http://code.google.com/p/data-race-test/wiki/DynamicAnnotations .

		// This marker is used to define a happens-before arc. The race detector
		will
		// infer an arc from the begin to the end when they share the same pointe
		r
		// argument.
		#define TsanHappensBefore(cv) \
		AnnotateHappensBefore(__FILE__, __LINE__, cv)

		// This marker defines the destination of a happens-before arc.
		#define TsanHappensAfter(cv) \
		AnnotateHappensAfter(__FILE__, __LINE__, cv)

		// Ignore any races on writes between here and the next TsanIgnoreWritesE
		nd.
		#define TsanIgnoreWritesBegin() \
		AnnotateIgnoreWritesBegin(__FILE__, __LINE__)

		// Resume checking for racy writes.
		#define TsanIgnoreWritesEnd() \
		AnnotateIgnoreWritesEnd(__FILE__, __LINE__)
		#else
		#define TsanHappensBefore(cv)
		#define TsanHappensAfter(cv)
		#define TsanIgnoreWritesBegin()
		#define TsanIgnoreWritesEnd()
		#endif
	}	}
	}	}

	#endif	#endif

End of changes. 3 change blocks.
	0 lines changed or deleted	49 lines changed or added

	Value.h	Value.h

	skipping to change at line 18	skipping to change at line 18
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	//	//
	// This file declares the Value class.	// This file declares the Value class.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_VALUE_H	#ifndef LLVM_VALUE_H
	#define LLVM_VALUE_H	#define LLVM_VALUE_H

	#include "llvm/Use.h"	#include "llvm/Use.h"

	#include "llvm/ADT/StringRef.h"
	#include "llvm/Support/Casting.h"	#include "llvm/Support/Casting.h"

	#include <string>

	namespace llvm {	namespace llvm {

	class Constant;	class Constant;
	class Argument;	class Argument;
	class Instruction;	class Instruction;
	class BasicBlock;	class BasicBlock;
	class GlobalValue;	class GlobalValue;
	class Function;	class Function;
	class GlobalVariable;	class GlobalVariable;
	class GlobalAlias;	class GlobalAlias;
	class InlineAsm;	class InlineAsm;
	class ValueSymbolTable;	class ValueSymbolTable;
	template<typename ValueTy> class StringMapEntry;	template<typename ValueTy> class StringMapEntry;

	template <typename ValueTy = Value>
	class AssertingVH;
	typedef StringMapEntry<Value*> ValueName;	typedef StringMapEntry<Value*> ValueName;
	class raw_ostream;	class raw_ostream;
	class AssemblyAnnotationWriter;	class AssemblyAnnotationWriter;
	class ValueHandleBase;	class ValueHandleBase;
	class LLVMContext;	class LLVMContext;
	class Twine;	class Twine;
	class MDNode;	class MDNode;
	class Type;	class Type;

		class StringRef;

	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	// Value Class	// Value Class
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	/// This is a very important LLVM class. It is the base class of all values	/// This is a very important LLVM class. It is the base class of all values
	/// computed by a program that may be used as operands to other values. Val ue is	/// computed by a program that may be used as operands to other values. Val ue is
	/// the super class of other important classes such as Instruction and Func tion.	/// the super class of other important classes such as Instruction and Func tion.
	/// All Values have a Type. Type is not a subclass of Value. Some values ca n	/// All Values have a Type. Type is not a subclass of Value. Some values ca n
	/// have a name and they belong to some Module. Setting the name on the Va lue	/// have a name and they belong to some Module. Setting the name on the Va lue

	skipping to change at line 113	skipping to change at line 110
	///	///
	void print(raw_ostream &O, AssemblyAnnotationWriter *AAW = 0) const;	void print(raw_ostream &O, AssemblyAnnotationWriter *AAW = 0) const;

	/// All values are typed, get the type of this value.	/// All values are typed, get the type of this value.
	///	///
	Type *getType() const { return VTy; }	Type *getType() const { return VTy; }

	/// All values hold a context through their type.	/// All values hold a context through their type.
	LLVMContext &getContext() const;	LLVMContext &getContext() const;


	// All values can potentially be named...	// All values can potentially be named.
	bool hasName() const { return Name != 0; }	bool hasName() const { return Name != 0 && SubclassID != MDStringVal; }
	ValueName *getValueName() const { return Name; }	ValueName *getValueName() const { return Name; }

		void setValueName(ValueName *VN) { Name = VN; }

	/// getName() - Return a constant reference to the value's name. This is cheap	/// getName() - Return a constant reference to the value's name. This is cheap
	/// and guaranteed to return the same reference as long as the value is n ot	/// and guaranteed to return the same reference as long as the value is n ot
	/// modified.	/// modified.

	///
	/// This is currently guaranteed to return a StringRef for which data() p
	oints
	/// to a valid null terminated string. The use of StringRef.data() is
	/// deprecated here, however, and clients should not rely on it. If such
	/// behavior is needed, clients should use expensive getNameStr(), or swi
	tch
	/// to an interface that does not depend on null termination.
	StringRef getName() const;	StringRef getName() const;


	/// getNameStr() - Return the name of the specified value, *constructing
	a
	/// string* to hold it. This is guaranteed to construct a string and is
	very
	/// expensive, clients should use getName() unless necessary.
	std::string getNameStr() const;

	/// setName() - Change the name of the value, choosing a new unique name if	/// setName() - Change the name of the value, choosing a new unique name if
	/// the provided name is taken.	/// the provided name is taken.
	///	///
	/// \arg Name - The new name; or "" if the value's name should be removed .	/// \arg Name - The new name; or "" if the value's name should be removed .
	void setName(const Twine &Name);	void setName(const Twine &Name);

	/// takeName - transfer the name from V to this value, setting V's name t o	/// takeName - transfer the name from V to this value, setting V's name t o
	/// empty. It is an error to call V->takeName(V).	/// empty. It is an error to call V->takeName(V).
	void takeName(Value *V);	void takeName(Value *V);


	skipping to change at line 207	skipping to change at line 194
	enum ValueTy {	enum ValueTy {
	ArgumentVal, // This is an instance of Argument	ArgumentVal, // This is an instance of Argument
	BasicBlockVal, // This is an instance of BasicBlock	BasicBlockVal, // This is an instance of BasicBlock
	FunctionVal, // This is an instance of Function	FunctionVal, // This is an instance of Function
	GlobalAliasVal, // This is an instance of GlobalAlias	GlobalAliasVal, // This is an instance of GlobalAlias
	GlobalVariableVal, // This is an instance of GlobalVariable	GlobalVariableVal, // This is an instance of GlobalVariable
	UndefValueVal, // This is an instance of UndefValue	UndefValueVal, // This is an instance of UndefValue
	BlockAddressVal, // This is an instance of BlockAddress	BlockAddressVal, // This is an instance of BlockAddress
	ConstantExprVal, // This is an instance of ConstantExpr	ConstantExprVal, // This is an instance of ConstantExpr
	ConstantAggregateZeroVal, // This is an instance of ConstantAggregateZe ro	ConstantAggregateZeroVal, // This is an instance of ConstantAggregateZe ro

		ConstantDataArrayVal, // This is an instance of ConstantDataArray
		ConstantDataVectorVal, // This is an instance of ConstantDataVector
	ConstantIntVal, // This is an instance of ConstantInt	ConstantIntVal, // This is an instance of ConstantInt
	ConstantFPVal, // This is an instance of ConstantFP	ConstantFPVal, // This is an instance of ConstantFP
	ConstantArrayVal, // This is an instance of ConstantArray	ConstantArrayVal, // This is an instance of ConstantArray
	ConstantStructVal, // This is an instance of ConstantStruct	ConstantStructVal, // This is an instance of ConstantStruct
	ConstantVectorVal, // This is an instance of ConstantVector	ConstantVectorVal, // This is an instance of ConstantVector
	ConstantPointerNullVal, // This is an instance of ConstantPointerNull	ConstantPointerNullVal, // This is an instance of ConstantPointerNull
	MDNodeVal, // This is an instance of MDNode	MDNodeVal, // This is an instance of MDNode
	MDStringVal, // This is an instance of MDString	MDStringVal, // This is an instance of MDString
	InlineAsmVal, // This is an instance of InlineAsm	InlineAsmVal, // This is an instance of InlineAsm
	PseudoSourceValueVal, // This is an instance of PseudoSourceValue	PseudoSourceValueVal, // This is an instance of PseudoSourceValue

	skipping to change at line 275	skipping to change at line 264

	/// hasValueHandle - Return true if there is a value handle associated wi th	/// hasValueHandle - Return true if there is a value handle associated wi th
	/// this value.	/// this value.
	bool hasValueHandle() const { return HasValueHandle; }	bool hasValueHandle() const { return HasValueHandle; }

	// Methods for support type inquiry through isa, cast, and dyn_cast:	// Methods for support type inquiry through isa, cast, and dyn_cast:
	static inline bool classof(const Value *) {	static inline bool classof(const Value *) {
	return true; // Values are always values.	return true; // Values are always values.
	}	}


	/// stripPointerCasts - This method strips off any unneeded pointer	/// stripPointerCasts - This method strips off any unneeded pointer casts
	/// casts from the specified value, returning the original uncasted value	and
	.	/// all-zero GEPs from the specified value, returning the original uncast
	/// Note that the returned value has pointer type if the specified value	ed
	does.	/// value. If this is called on a non-pointer value, it returns 'this'.
	Value *stripPointerCasts();	Value *stripPointerCasts();
	const Value *stripPointerCasts() const {	const Value *stripPointerCasts() const {
	return const_cast<Value*>(this)->stripPointerCasts();	return const_cast<Value*>(this)->stripPointerCasts();
	}	}


		/// stripInBoundsConstantOffsets - This method strips off unneeded pointe
		r casts and
		/// all-constant GEPs from the specified value, returning the original
		/// pointer value. If this is called on a non-pointer value, it returns
		/// 'this'.
		Value *stripInBoundsConstantOffsets();
		const Value *stripInBoundsConstantOffsets() const {
		return const_cast<Value*>(this)->stripInBoundsConstantOffsets();
		}

		/// stripInBoundsOffsets - This method strips off unneeded pointer casts
		and
		/// any in-bounds Offsets from the specified value, returning the origina
		l
		/// pointer value. If this is called on a non-pointer value, it returns
		/// 'this'.
		Value *stripInBoundsOffsets();
		const Value *stripInBoundsOffsets() const {
		return const_cast<Value*>(this)->stripInBoundsOffsets();
		}

	/// isDereferenceablePointer - Test if this value is always a pointer to	/// isDereferenceablePointer - Test if this value is always a pointer to
	/// allocated and suitably aligned memory for a simple load or store.	/// allocated and suitably aligned memory for a simple load or store.
	bool isDereferenceablePointer() const;	bool isDereferenceablePointer() const;

	/// DoPHITranslation - If this value is a PHI node with CurBB as its pare nt,	/// DoPHITranslation - If this value is a PHI node with CurBB as its pare nt,
	/// return the value in the PHI node corresponding to PredBB. If not, re turn	/// return the value in the PHI node corresponding to PredBB. If not, re turn
	/// ourself. This is useful if you want to know the value something has in a	/// ourself. This is useful if you want to know the value something has in a
	/// predecessor block.	/// predecessor block.
	Value DoPHITranslation(const BasicBlock CurBB, const BasicBlock *PredBB );	Value DoPHITranslation(const BasicBlock CurBB, const BasicBlock *PredBB );


End of changes. 11 change blocks.
	26 lines changed or deleted	32 lines changed or added

	ValueHandle.h	ValueHandle.h

	skipping to change at line 52	skipping to change at line 52
	protected:	protected:
	/// HandleBaseKind - This indicates what sub class the handle actually is .	/// HandleBaseKind - This indicates what sub class the handle actually is .
	/// This is to avoid having a vtable for the light-weight handle pointers . The	/// This is to avoid having a vtable for the light-weight handle pointers . The
	/// fully general Callback version does have a vtable.	/// fully general Callback version does have a vtable.
	enum HandleBaseKind {	enum HandleBaseKind {
	Assert,	Assert,
	Callback,	Callback,
	Tracking,	Tracking,
	Weak	Weak
	};	};

	private:


		private:
	PointerIntPair<ValueHandleBase**, 2, HandleBaseKind> PrevPair;	PointerIntPair<ValueHandleBase**, 2, HandleBaseKind> PrevPair;
	ValueHandleBase *Next;	ValueHandleBase *Next;

	Value *VP;
		// A subclass may want to store some information along with the value
		// pointer. Allow them to do this by making the value pointer a pointer-i
		nt
		// pair. The 'setValPtrInt' and 'getValPtrInt' methods below give them th
		is
		// access.
		PointerIntPair<Value*, 2> VP;

	explicit ValueHandleBase(const ValueHandleBase&); // DO NOT IMPLEMENT.	explicit ValueHandleBase(const ValueHandleBase&); // DO NOT IMPLEMENT.
	public:	public:
	explicit ValueHandleBase(HandleBaseKind Kind)	explicit ValueHandleBase(HandleBaseKind Kind)

	: PrevPair(0, Kind), Next(0), VP(0) {}	: PrevPair(0, Kind), Next(0), VP(0, 0) {}
	ValueHandleBase(HandleBaseKind Kind, Value *V)	ValueHandleBase(HandleBaseKind Kind, Value *V)

	: PrevPair(0, Kind), Next(0), VP(V) {	: PrevPair(0, Kind), Next(0), VP(V, 0) {
	if (isValid(VP))	if (isValid(VP.getPointer()))
	AddToUseList();	AddToUseList();
	}	}
	ValueHandleBase(HandleBaseKind Kind, const ValueHandleBase &RHS)	ValueHandleBase(HandleBaseKind Kind, const ValueHandleBase &RHS)
	: PrevPair(0, Kind), Next(0), VP(RHS.VP) {	: PrevPair(0, Kind), Next(0), VP(RHS.VP) {

	if (isValid(VP))	if (isValid(VP.getPointer()))
	AddToExistingUseList(RHS.getPrevPtr());	AddToExistingUseList(RHS.getPrevPtr());
	}	}
	~ValueHandleBase() {	~ValueHandleBase() {

	if (isValid(VP))	if (isValid(VP.getPointer()))
	RemoveFromUseList();	RemoveFromUseList();
	}	}

	Value operator=(Value RHS) {	Value operator=(Value RHS) {

	if (VP == RHS) return RHS;	if (VP.getPointer() == RHS) return RHS;
	if (isValid(VP)) RemoveFromUseList();	if (isValid(VP.getPointer())) RemoveFromUseList();
	VP = RHS;	VP.setPointer(RHS);
	if (isValid(VP)) AddToUseList();	if (isValid(VP.getPointer())) AddToUseList();
	return RHS;	return RHS;
	}	}

	Value *operator=(const ValueHandleBase &RHS) {	Value *operator=(const ValueHandleBase &RHS) {

	if (VP == RHS.VP) return RHS.VP;	if (VP.getPointer() == RHS.VP.getPointer()) return RHS.VP.getPointer();
	if (isValid(VP)) RemoveFromUseList();	if (isValid(VP.getPointer())) RemoveFromUseList();
	VP = RHS.VP;	VP.setPointer(RHS.VP.getPointer());
	if (isValid(VP)) AddToExistingUseList(RHS.getPrevPtr());	if (isValid(VP.getPointer())) AddToExistingUseList(RHS.getPrevPtr());
	return VP;	return VP.getPointer();
	}	}

	Value *operator->() const { return getValPtr(); }	Value *operator->() const { return getValPtr(); }
	Value &operator() const { return getValPtr(); }	Value &operator() const { return getValPtr(); }

	protected:	protected:

	Value *getValPtr() const { return VP; }	Value *getValPtr() const { return VP.getPointer(); }

		void setValPtrInt(unsigned K) { VP.setInt(K); }
		unsigned getValPtrInt() const { return VP.getInt(); }

	static bool isValid(Value *V) {	static bool isValid(Value *V) {
	return V &&	return V &&
	V != DenseMapInfo<Value *>::getEmptyKey() &&	V != DenseMapInfo<Value *>::getEmptyKey() &&
	V != DenseMapInfo<Value *>::getTombstoneKey();	V != DenseMapInfo<Value *>::getTombstoneKey();
	}	}

	private:	private:
	// Callbacks made from Value.	// Callbacks made from Value.
	static void ValueIsDeleted(Value *V);	static void ValueIsDeleted(Value *V);
	static void ValueIsRAUWd(Value Old, Value New);	static void ValueIsRAUWd(Value Old, Value New);

End of changes. 10 change blocks.
	17 lines changed or deleted	28 lines changed or added

	ValueMap.h	ValueMap.h

	skipping to change at line 38	skipping to change at line 38

	#include "llvm/ADT/DenseMap.h"	#include "llvm/ADT/DenseMap.h"
	#include "llvm/Support/ValueHandle.h"	#include "llvm/Support/ValueHandle.h"
	#include "llvm/Support/type_traits.h"	#include "llvm/Support/type_traits.h"
	#include "llvm/Support/Mutex.h"	#include "llvm/Support/Mutex.h"

	#include <iterator>	#include <iterator>

	namespace llvm {	namespace llvm {


	template<typename KeyT, typename ValueT, typename Config, typename ValueInf oT>	template<typename KeyT, typename ValueT, typename Config>
	class ValueMapCallbackVH;	class ValueMapCallbackVH;

	template<typename DenseMapT, typename KeyT>	template<typename DenseMapT, typename KeyT>
	class ValueMapIterator;	class ValueMapIterator;
	template<typename DenseMapT, typename KeyT>	template<typename DenseMapT, typename KeyT>
	class ValueMapConstIterator;	class ValueMapConstIterator;

	/// This class defines the default behavior for configurable aspects of	/// This class defines the default behavior for configurable aspects of
	/// ValueMap<>. User Configs should inherit from this class to be as compa tible	/// ValueMap<>. User Configs should inherit from this class to be as compa tible
	/// as possible with future versions of ValueMap.	/// as possible with future versions of ValueMap.

	skipping to change at line 75	skipping to change at line 75

	/// Returns a mutex that should be acquired around any changes to the map .	/// Returns a mutex that should be acquired around any changes to the map .
	/// This is only acquired from the CallbackVH (and held around calls to o nRAUW	/// This is only acquired from the CallbackVH (and held around calls to o nRAUW
	/// and onDelete) and not inside other ValueMap methods. NULL means that no	/// and onDelete) and not inside other ValueMap methods. NULL means that no
	/// mutex is necessary.	/// mutex is necessary.
	template<typename ExtraDataT>	template<typename ExtraDataT>
	static sys::Mutex getMutex(const ExtraDataT &/Data*/) { return NULL; }	static sys::Mutex getMutex(const ExtraDataT &/Data*/) { return NULL; }
	};	};

	/// See the file comment.	/// See the file comment.

	template<typename KeyT, typename ValueT, typename Config = ValueMapConfig<K	template<typename KeyT, typename ValueT, typename Config =ValueMapConfig<Ke
	eyT>,	yT> >
	typename ValueInfoT = DenseMapInfo<ValueT> >
	class ValueMap {	class ValueMap {

	friend class ValueMapCallbackVH<KeyT, ValueT, Config, ValueInfoT>;	friend class ValueMapCallbackVH<KeyT, ValueT, Config>;
	typedef ValueMapCallbackVH<KeyT, ValueT, Config, ValueInfoT> ValueMapCVH;	typedef ValueMapCallbackVH<KeyT, ValueT, Config> ValueMapCVH;
	typedef DenseMap<ValueMapCVH, ValueT, DenseMapInfo<ValueMapCVH>,	typedef DenseMap<ValueMapCVH, ValueT, DenseMapInfo<ValueMapCVH> > MapT;
	ValueInfoT> MapT;
	typedef typename Config::ExtraData ExtraData;	typedef typename Config::ExtraData ExtraData;
	MapT Map;	MapT Map;
	ExtraData Data;	ExtraData Data;
	ValueMap(const ValueMap&); // DO NOT IMPLEMENT	ValueMap(const ValueMap&); // DO NOT IMPLEMENT
	ValueMap& operator=(const ValueMap&); // DO NOT IMPLEMENT	ValueMap& operator=(const ValueMap&); // DO NOT IMPLEMENT
	public:	public:
	typedef KeyT key_type;	typedef KeyT key_type;
	typedef ValueT mapped_type;	typedef ValueT mapped_type;
	typedef std::pair<KeyT, ValueT> value_type;	typedef std::pair<KeyT, ValueT> value_type;


	skipping to change at line 192	skipping to change at line 190
	// The only way the resulting CallbackVH could try to modify *this (mak ing	// The only way the resulting CallbackVH could try to modify *this (mak ing
	// the const_cast incorrect) is if it gets inserted into the map. But then	// the const_cast incorrect) is if it gets inserted into the map. But then
	// this function must have been called from a non-const method, making the	// this function must have been called from a non-const method, making the
	// const_cast ok.	// const_cast ok.
	return ValueMapCVH(key, const_cast<ValueMap*>(this));	return ValueMapCVH(key, const_cast<ValueMap*>(this));
	}	}
	};	};

	// This CallbackVH updates its ValueMap when the contained Value changes,	// This CallbackVH updates its ValueMap when the contained Value changes,
	// according to the user's preferences expressed through the Config object.	// according to the user's preferences expressed through the Config object.

	template<typename KeyT, typename ValueT, typename Config, typename ValueInf oT>	template<typename KeyT, typename ValueT, typename Config>
	class ValueMapCallbackVH : public CallbackVH {	class ValueMapCallbackVH : public CallbackVH {

	friend class ValueMap<KeyT, ValueT, Config, ValueInfoT>;	friend class ValueMap<KeyT, ValueT, Config>;
	friend struct DenseMapInfo<ValueMapCallbackVH>;	friend struct DenseMapInfo<ValueMapCallbackVH>;

	typedef ValueMap<KeyT, ValueT, Config, ValueInfoT> ValueMapT;	typedef ValueMap<KeyT, ValueT, Config> ValueMapT;
	typedef typename llvm::remove_pointer<KeyT>::type KeySansPointerT;	typedef typename llvm::remove_pointer<KeyT>::type KeySansPointerT;

	ValueMapT *Map;	ValueMapT *Map;

	ValueMapCallbackVH(KeyT Key, ValueMapT *Map)	ValueMapCallbackVH(KeyT Key, ValueMapT *Map)
	: CallbackVH(const_cast<Value>(static_cast<const Value>(Key))),	: CallbackVH(const_cast<Value>(static_cast<const Value>(Key))),
	Map(Map) {}	Map(Map) {}

	public:	public:
	KeyT Unwrap() const { return cast_or_null<KeySansPointerT>(getValPtr()); }	KeyT Unwrap() const { return cast_or_null<KeySansPointerT>(getValPtr()); }

	skipping to change at line 246	skipping to change at line 244
	ValueT Target(I->second);	ValueT Target(I->second);
	Copy.Map->Map.erase(I); // Definitely destroys *this.	Copy.Map->Map.erase(I); // Definitely destroys *this.
	Copy.Map->insert(std::make_pair(typed_new_key, Target));	Copy.Map->insert(std::make_pair(typed_new_key, Target));
	}	}
	}	}
	if (M)	if (M)
	M->release();	M->release();
	}	}
	};	};


	template<typename KeyT, typename ValueT, typename Config, typename ValueInf	template<typename KeyT, typename ValueT, typename Config>
	oT>	struct DenseMapInfo<ValueMapCallbackVH<KeyT, ValueT, Config> > {
	struct DenseMapInfo<ValueMapCallbackVH<KeyT, ValueT, Config, ValueInfoT> >	typedef ValueMapCallbackVH<KeyT, ValueT, Config> VH;
	{
	typedef ValueMapCallbackVH<KeyT, ValueT, Config, ValueInfoT> VH;
	typedef DenseMapInfo<KeyT> PointerInfo;	typedef DenseMapInfo<KeyT> PointerInfo;

	static inline VH getEmptyKey() {	static inline VH getEmptyKey() {
	return VH(PointerInfo::getEmptyKey(), NULL);	return VH(PointerInfo::getEmptyKey(), NULL);
	}	}
	static inline VH getTombstoneKey() {	static inline VH getTombstoneKey() {
	return VH(PointerInfo::getTombstoneKey(), NULL);	return VH(PointerInfo::getTombstoneKey(), NULL);
	}	}
	static unsigned getHashValue(const VH &Val) {	static unsigned getHashValue(const VH &Val) {
	return PointerInfo::getHashValue(Val.Unwrap());	return PointerInfo::getHashValue(Val.Unwrap());

End of changes. 7 change blocks.
	16 lines changed or deleted	12 lines changed or added

	ValueMapper.h	ValueMapper.h

	skipping to change at line 23	skipping to change at line 23
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_TRANSFORMS_UTILS_VALUEMAPPER_H	#ifndef LLVM_TRANSFORMS_UTILS_VALUEMAPPER_H
	#define LLVM_TRANSFORMS_UTILS_VALUEMAPPER_H	#define LLVM_TRANSFORMS_UTILS_VALUEMAPPER_H

	#include "llvm/ADT/ValueMap.h"	#include "llvm/ADT/ValueMap.h"

	namespace llvm {	namespace llvm {
	class Value;	class Value;
	class Instruction;	class Instruction;

	typedef ValueMap<const Value *, TrackingVH<Value> > ValueToValueMapTy;	typedef ValueMap<const Value *, WeakVH> ValueToValueMapTy;

	/// ValueMapTypeRemapper - This is a class that can be implemented by cli ents	/// ValueMapTypeRemapper - This is a class that can be implemented by cli ents
	/// to remap types when cloning constants and instructions.	/// to remap types when cloning constants and instructions.
	class ValueMapTypeRemapper {	class ValueMapTypeRemapper {
	virtual void Anchor(); // Out of line method.	virtual void Anchor(); // Out of line method.
	public:	public:
	virtual ~ValueMapTypeRemapper() {}	virtual ~ValueMapTypeRemapper() {}

	/// remapType - The client should implement this method if they want to	/// remapType - The client should implement this method if they want to
	/// remap types while mapping values.	/// remap types while mapping values.

End of changes. 1 change blocks.
	1 lines changed or deleted	1 lines changed or added

	ValueTracking.h	ValueTracking.h

	skipping to change at line 20	skipping to change at line 20
	// This file contains routines that help analyze properties that chains of	// This file contains routines that help analyze properties that chains of
	// computations have.	// computations have.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_ANALYSIS_VALUETRACKING_H	#ifndef LLVM_ANALYSIS_VALUETRACKING_H
	#define LLVM_ANALYSIS_VALUETRACKING_H	#define LLVM_ANALYSIS_VALUETRACKING_H

	#include "llvm/ADT/ArrayRef.h"	#include "llvm/ADT/ArrayRef.h"
	#include "llvm/Support/DataTypes.h"	#include "llvm/Support/DataTypes.h"

	#include <string>

	namespace llvm {	namespace llvm {

	template <typename T> class SmallVectorImpl;
	class Value;	class Value;
	class Instruction;	class Instruction;
	class APInt;	class APInt;
	class TargetData;	class TargetData;

		class StringRef;
		class MDNode;

	/// ComputeMaskedBits - Determine which of the bits specified in Mask are	/// ComputeMaskedBits - Determine which of the bits specified in Mask are
	/// known to be either zero or one and return them in the KnownZero/Known One	/// known to be either zero or one and return them in the KnownZero/Known One
	/// bit sets. This code only analyzes bits in Mask, in order to short-ci rcuit	/// bit sets. This code only analyzes bits in Mask, in order to short-ci rcuit
	/// processing.	/// processing.
	///	///
	/// This function is defined on values with integer type, values with poi nter	/// This function is defined on values with integer type, values with poi nter
	/// type (but only if TD is non-null), and vectors of integers. In the c ase	/// type (but only if TD is non-null), and vectors of integers. In the c ase
	/// where V is a vector, the mask, known zero, and known one values are t he	/// where V is a vector, the mask, known zero, and known one values are t he
	/// same width as the vector element, and the bit is set only if it is tr ue	/// same width as the vector element, and the bit is set only if it is tr ue
	/// for all of the elements in the vector.	/// for all of the elements in the vector.

	void ComputeMaskedBits(Value *V, const APInt &Mask, APInt &KnownZero,	void ComputeMaskedBits(Value *V, APInt &KnownZero, APInt &KnownOne,
	APInt &KnownOne, const TargetData *TD = 0,	const TargetData *TD = 0, unsigned Depth = 0);
	unsigned Depth = 0);	void computeMaskedBitsLoad(const MDNode &Ranges, APInt &KnownZero);

	/// ComputeSignBit - Determine whether the sign bit is known to be zero o r	/// ComputeSignBit - Determine whether the sign bit is known to be zero o r
	/// one. Convenience wrapper around ComputeMaskedBits.	/// one. Convenience wrapper around ComputeMaskedBits.
	void ComputeSignBit(Value *V, bool &KnownZero, bool &KnownOne,	void ComputeSignBit(Value *V, bool &KnownZero, bool &KnownOne,
	const TargetData *TD = 0, unsigned Depth = 0);	const TargetData *TD = 0, unsigned Depth = 0);

	/// isPowerOfTwo - Return true if the given value is known to have exactl y one	/// isPowerOfTwo - Return true if the given value is known to have exactl y one
	/// bit set when defined. For vectors return true if every element is kno wn to	/// bit set when defined. For vectors return true if every element is kno wn to
	/// be a power of two when defined. Supports values with integer or poin ter	/// be a power of two when defined. Supports values with integer or poin ter

	/// type and vectors of integers.	/// type and vectors of integers. If 'OrZero' is set then returns true i
	bool isPowerOfTwo(Value V, const TargetData TD = 0, unsigned Depth = 0)	f the
	;	/// given value is either a power of two or zero.
		bool isPowerOfTwo(Value V, const TargetData TD = 0, bool OrZero = false
		,
		unsigned Depth = 0);

	/// isKnownNonZero - Return true if the given value is known to be non-ze ro	/// isKnownNonZero - Return true if the given value is known to be non-ze ro
	/// when defined. For vectors return true if every element is known to b e	/// when defined. For vectors return true if every element is known to b e
	/// non-zero when defined. Supports values with integer or pointer type and	/// non-zero when defined. Supports values with integer or pointer type and
	/// vectors of integers.	/// vectors of integers.
	bool isKnownNonZero(Value V, const TargetData TD = 0, unsigned Depth = 0);	bool isKnownNonZero(Value V, const TargetData TD = 0, unsigned Depth = 0);

	/// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. W e use	/// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. W e use
	/// this predicate to simplify operations downstream. Mask is known to b e	/// this predicate to simplify operations downstream. Mask is known to b e
	/// zero for bits that V cannot have.	/// zero for bits that V cannot have.

	skipping to change at line 125	skipping to change at line 127
	/// it can be expressed as a base pointer plus a constant offset. Return the	/// it can be expressed as a base pointer plus a constant offset. Return the
	/// base and offset to the caller.	/// base and offset to the caller.
	Value GetPointerBaseWithConstantOffset(Value Ptr, int64_t &Offset,	Value GetPointerBaseWithConstantOffset(Value Ptr, int64_t &Offset,
	const TargetData &TD);	const TargetData &TD);
	static inline const Value *	static inline const Value *
	GetPointerBaseWithConstantOffset(const Value *Ptr, int64_t &Offset,	GetPointerBaseWithConstantOffset(const Value *Ptr, int64_t &Offset,
	const TargetData &TD) {	const TargetData &TD) {
	return GetPointerBaseWithConstantOffset(const_cast<Value*>(Ptr), Offset ,TD);	return GetPointerBaseWithConstantOffset(const_cast<Value*>(Ptr), Offset ,TD);
	}	}


	/// GetConstantStringInfo - This function computes the length of a	/// getConstantStringInfo - This function computes the length of a
	/// null-terminated C string pointed to by V. If successful, it returns true	/// null-terminated C string pointed to by V. If successful, it returns true

	/// and returns the string in Str. If unsuccessful, it returns false. I	/// and returns the string in Str. If unsuccessful, it returns false. T
	f	his
	/// StopAtNul is set to true (the default), the returned string is trunca	/// does not include the trailing nul character by default. If TrimAtNul
	ted	is
	/// by a nul character in the global. If StopAtNul is false, the nul	/// set to false, then this returns any trailing nul characters as well a
	/// character is included in the result string.	s any
	bool GetConstantStringInfo(const Value *V, std::string &Str,	/// other characters that come after it.
	uint64_t Offset = 0,	bool getConstantStringInfo(const Value *V, StringRef &Str,
	bool StopAtNul = true);	uint64_t Offset = 0, bool TrimAtNul = true);

	/// GetStringLength - If we can compute the length of the string pointed to by	/// GetStringLength - If we can compute the length of the string pointed to by
	/// the specified pointer, return 'len+1'. If we can't, return 0.	/// the specified pointer, return 'len+1'. If we can't, return 0.
	uint64_t GetStringLength(Value *V);	uint64_t GetStringLength(Value *V);

	/// GetUnderlyingObject - This method strips off any GEP address adjustme nts	/// GetUnderlyingObject - This method strips off any GEP address adjustme nts
	/// and pointer casts from the specified value, returning the original ob ject	/// and pointer casts from the specified value, returning the original ob ject
	/// being addressed. Note that the returned value has pointer type if th e	/// being addressed. Note that the returned value has pointer type if th e
	/// specified value does. If the MaxLookup value is non-zero, it limits the	/// specified value does. If the MaxLookup value is non-zero, it limits the
	/// number of instructions to be stripped off.	/// number of instructions to be stripped off.

	skipping to change at line 156	skipping to change at line 157
	static inline const Value *	static inline const Value *
	GetUnderlyingObject(const Value V, const TargetData TD = 0,	GetUnderlyingObject(const Value V, const TargetData TD = 0,
	unsigned MaxLookup = 6) {	unsigned MaxLookup = 6) {
	return GetUnderlyingObject(const_cast<Value *>(V), TD, MaxLookup);	return GetUnderlyingObject(const_cast<Value *>(V), TD, MaxLookup);
	}	}

	/// onlyUsedByLifetimeMarkers - Return true if the only users of this poi nter	/// onlyUsedByLifetimeMarkers - Return true if the only users of this poi nter
	/// are lifetime markers.	/// are lifetime markers.
	bool onlyUsedByLifetimeMarkers(const Value *V);	bool onlyUsedByLifetimeMarkers(const Value *V);


		/// isSafeToSpeculativelyExecute - Return true if the instruction does no
		t
		/// have any effects besides calculating the result and does not have
		/// undefined behavior.
		///
		/// This method never returns true for an instruction that returns true f
		or
		/// mayHaveSideEffects; however, this method also does some other checks
		in
		/// addition. It checks for undefined behavior, like dividing by zero or
		/// loading from an invalid pointer (but not for undefined results, like
		a
		/// shift with a shift amount larger than the width of the result). It ch
		ecks
		/// for malloc and alloca because speculatively executing them might caus
		e a
		/// memory leak. It also returns false for instructions related to contro
		l
		/// flow, specifically terminators and PHI nodes.
		///
		/// This method only looks at the instruction itself and its operands, so
		if
		/// this method returns true, it is safe to move the instruction as long
		as
		/// the correct dominance relationships for the operands and users hold.
		/// However, this method can return true for instructions that read memor
		y;
		/// for such instructions, moving them may change the resulting value.
		bool isSafeToSpeculativelyExecute(const Value *V,
		const TargetData *TD = 0);

	} // end namespace llvm	} // end namespace llvm

	#endif	#endif

End of changes. 8 change blocks.
	18 lines changed or deleted	52 lines changed or added

	ValueTypes.h	ValueTypes.h

	skipping to change at line 19	skipping to change at line 19
	//	//
	// This file defines the set of low-level target independent types which va rious	// This file defines the set of low-level target independent types which va rious
	// values in the code generator are. This allows the target specific behav ior	// values in the code generator are. This allows the target specific behav ior
	// of instructions to be described to target independent passes.	// of instructions to be described to target independent passes.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_CODEGEN_VALUETYPES_H	#ifndef LLVM_CODEGEN_VALUETYPES_H
	#define LLVM_CODEGEN_VALUETYPES_H	#define LLVM_CODEGEN_VALUETYPES_H


	#include <cassert>
	#include <string>
	#include "llvm/Support/DataTypes.h"	#include "llvm/Support/DataTypes.h"

		#include "llvm/Support/ErrorHandling.h"
	#include "llvm/Support/MathExtras.h"	#include "llvm/Support/MathExtras.h"

		#include <cassert>
		#include <string>

	namespace llvm {	namespace llvm {
	class Type;	class Type;
	class LLVMContext;	class LLVMContext;
	struct EVT;	struct EVT;

	/// MVT - Machine Value Type. Every type that is supported natively by s ome	/// MVT - Machine Value Type. Every type that is supported natively by s ome
	/// processor targeted by LLVM occurs here. This means that any legal va lue	/// processor targeted by LLVM occurs here. This means that any legal va lue
	/// type can be represented by a MVT.	/// type can be represented by a MVT.
	class MVT {	class MVT {

	skipping to change at line 48	skipping to change at line 49
	i1 = 1, // This is a 1 bit integer value	i1 = 1, // This is a 1 bit integer value
	i8 = 2, // This is an 8 bit integer value	i8 = 2, // This is an 8 bit integer value
	i16 = 3, // This is a 16 bit integer value	i16 = 3, // This is a 16 bit integer value
	i32 = 4, // This is a 32 bit integer value	i32 = 4, // This is a 32 bit integer value
	i64 = 5, // This is a 64 bit integer value	i64 = 5, // This is a 64 bit integer value
	i128 = 6, // This is a 128 bit integer value	i128 = 6, // This is a 128 bit integer value

	FIRST_INTEGER_VALUETYPE = i1,	FIRST_INTEGER_VALUETYPE = i1,
	LAST_INTEGER_VALUETYPE = i128,	LAST_INTEGER_VALUETYPE = i128,


	f32 = 7, // This is a 32 bit floating point value	f16 = 7, // This is a 16 bit floating point value
	f64 = 8, // This is a 64 bit floating point value	f32 = 8, // This is a 32 bit floating point value
	f80 = 9, // This is a 80 bit floating point value	f64 = 9, // This is a 64 bit floating point value
	f128 = 10, // This is a 128 bit floating point value	f80 = 10, // This is a 80 bit floating point value
	ppcf128 = 11, // This is a PPC 128-bit floating point value	f128 = 11, // This is a 128 bit floating point value
		ppcf128 = 12, // This is a PPC 128-bit floating point value
	v2i8 = 12, // 2 x i8
	v4i8 = 13, // 4 x i8	FIRST_FP_VALUETYPE = f16,
	v8i8 = 14, // 8 x i8	LAST_FP_VALUETYPE = ppcf128,
	v16i8 = 15, // 16 x i8
	v32i8 = 16, // 32 x i8	v2i8 = 13, // 2 x i8
	v2i16 = 17, // 2 x i16	v4i8 = 14, // 4 x i8
	v4i16 = 18, // 4 x i16	v8i8 = 15, // 8 x i8
	v8i16 = 19, // 8 x i16	v16i8 = 16, // 16 x i8
	v16i16 = 20, // 16 x i16	v32i8 = 17, // 32 x i8
	v2i32 = 21, // 2 x i32	v2i16 = 18, // 2 x i16
	v4i32 = 22, // 4 x i32	v4i16 = 19, // 4 x i16
	v8i32 = 23, // 8 x i32	v8i16 = 20, // 8 x i16
	v1i64 = 24, // 1 x i64	v16i16 = 21, // 16 x i16
	v2i64 = 25, // 2 x i64	v2i32 = 22, // 2 x i32
	v4i64 = 26, // 4 x i64	v4i32 = 23, // 4 x i32
	v8i64 = 27, // 8 x i64	v8i32 = 24, // 8 x i32
		v1i64 = 25, // 1 x i64
	v2f32 = 28, // 2 x f32	v2i64 = 26, // 2 x i64
	v4f32 = 29, // 4 x f32	v4i64 = 27, // 4 x i64
	v8f32 = 30, // 8 x f32	v8i64 = 28, // 8 x i64
	v2f64 = 31, // 2 x f64
	v4f64 = 32, // 4 x f64	v2f16 = 29, // 2 x f16
		v2f32 = 30, // 2 x f32
		v4f32 = 31, // 4 x f32
		v8f32 = 32, // 8 x f32
		v2f64 = 33, // 2 x f64
		v4f64 = 34, // 4 x f64

	FIRST_VECTOR_VALUETYPE = v2i8,	FIRST_VECTOR_VALUETYPE = v2i8,
	LAST_VECTOR_VALUETYPE = v4f64,	LAST_VECTOR_VALUETYPE = v4f64,

		FIRST_FP_VECTOR_VALUETYPE = v2f16,
		LAST_FP_VECTOR_VALUETYPE = v4f64,


	x86mmx = 33, // This is an X86 MMX value	x86mmx = 35, // This is an X86 MMX value


	Glue = 34, // This glues nodes together during pre-RA sc hed	Glue = 36, // This glues nodes together during pre-RA sc hed


	isVoid = 35, // This has no value	isVoid = 37, // This has no value


	untyped = 36, // This value takes a register, but has	Untyped = 38, // This value takes a register, but has
	// unspecified type. The register class	// unspecified type. The register class
	// will be determined by the opcode.	// will be determined by the opcode.


	LAST_VALUETYPE = 37, // This always remains at the end of the list .	LAST_VALUETYPE = 39, // This always remains at the end of the list .

	// This is the current maximum for LAST_VALUETYPE.	// This is the current maximum for LAST_VALUETYPE.
	// MVT::MAX_ALLOWED_VALUETYPE is used for asserts and to size bit vec tors	// MVT::MAX_ALLOWED_VALUETYPE is used for asserts and to size bit vec tors
	// This value must be a multiple of 32.	// This value must be a multiple of 32.
	MAX_ALLOWED_VALUETYPE = 64,	MAX_ALLOWED_VALUETYPE = 64,

	// Metadata - This is MDNode or MDString.	// Metadata - This is MDNode or MDString.
	Metadata = 250,	Metadata = 250,

	// iPTRAny - An int value the size of the pointer of the current	// iPTRAny - An int value the size of the pointer of the current

	skipping to change at line 146	skipping to change at line 154

	bool operator>(const MVT& S) const { return SimpleTy > S.SimpleTy; }	bool operator>(const MVT& S) const { return SimpleTy > S.SimpleTy; }
	bool operator<(const MVT& S) const { return SimpleTy < S.SimpleTy; }	bool operator<(const MVT& S) const { return SimpleTy < S.SimpleTy; }
	bool operator==(const MVT& S) const { return SimpleTy == S.SimpleTy; }	bool operator==(const MVT& S) const { return SimpleTy == S.SimpleTy; }
	bool operator!=(const MVT& S) const { return SimpleTy != S.SimpleTy; }	bool operator!=(const MVT& S) const { return SimpleTy != S.SimpleTy; }
	bool operator>=(const MVT& S) const { return SimpleTy >= S.SimpleTy; }	bool operator>=(const MVT& S) const { return SimpleTy >= S.SimpleTy; }
	bool operator<=(const MVT& S) const { return SimpleTy <= S.SimpleTy; }	bool operator<=(const MVT& S) const { return SimpleTy <= S.SimpleTy; }

	/// isFloatingPoint - Return true if this is a FP, or a vector FP type.	/// isFloatingPoint - Return true if this is a FP, or a vector FP type.
	bool isFloatingPoint() const {	bool isFloatingPoint() const {

	return ((SimpleTy >= MVT::f32 && SimpleTy <= MVT::ppcf128) \|\|	return ((SimpleTy >= MVT::FIRST_FP_VALUETYPE &&
	(SimpleTy >= MVT::v2f32 && SimpleTy <= MVT::v4f64));	SimpleTy <= MVT::LAST_FP_VALUETYPE) \|\|
		(SimpleTy >= MVT::FIRST_FP_VECTOR_VALUETYPE &&
		SimpleTy <= MVT::LAST_FP_VECTOR_VALUETYPE));
	}	}

	/// isInteger - Return true if this is an integer, or a vector integer type.	/// isInteger - Return true if this is an integer, or a vector integer type.
	bool isInteger() const {	bool isInteger() const {
	return ((SimpleTy >= MVT::FIRST_INTEGER_VALUETYPE &&	return ((SimpleTy >= MVT::FIRST_INTEGER_VALUETYPE &&
	SimpleTy <= MVT::LAST_INTEGER_VALUETYPE) \|\|	SimpleTy <= MVT::LAST_INTEGER_VALUETYPE) \|\|
	(SimpleTy >= MVT::v2i8 && SimpleTy <= MVT::v8i64));	(SimpleTy >= MVT::v2i8 && SimpleTy <= MVT::v8i64));
	}	}

	/// isVector - Return true if this is a vector value type.	/// isVector - Return true if this is a vector value type.

	skipping to change at line 206	skipping to change at line 216
	case v4i16:	case v4i16:
	case v8i16:	case v8i16:
	case v16i16: return i16;	case v16i16: return i16;
	case v2i32:	case v2i32:
	case v4i32:	case v4i32:
	case v8i32: return i32;	case v8i32: return i32;
	case v1i64:	case v1i64:
	case v2i64:	case v2i64:
	case v4i64:	case v4i64:
	case v8i64: return i64;	case v8i64: return i64;

		case v2f16: return f16;
	case v2f32:	case v2f32:
	case v4f32:	case v4f32:
	case v8f32: return f32;	case v8f32: return f32;
	case v2f64:	case v2f64:
	case v4f64: return f64;	case v4f64: return f64;
	}	}
	}	}

	unsigned getVectorNumElements() const {	unsigned getVectorNumElements() const {
	switch (SimpleTy) {	switch (SimpleTy) {

	skipping to change at line 236	skipping to change at line 247
	case v4i8:	case v4i8:
	case v4i16:	case v4i16:
	case v4i32:	case v4i32:
	case v4i64:	case v4i64:
	case v4f32:	case v4f32:
	case v4f64: return 4;	case v4f64: return 4;
	case v2i8:	case v2i8:
	case v2i16:	case v2i16:
	case v2i32:	case v2i32:
	case v2i64:	case v2i64:

		case v2f16:
	case v2f32:	case v2f32:
	case v2f64: return 2;	case v2f64: return 2;
	case v1i64: return 1;	case v1i64: return 1;
	}	}
	}	}

	unsigned getSizeInBits() const {	unsigned getSizeInBits() const {
	switch (SimpleTy) {	switch (SimpleTy) {
	case iPTR:	case iPTR:

	assert(0 && "Value type size is target-dependent. Ask TLI.");	llvm_unreachable("Value type size is target-dependent. Ask TLI.");
	case iPTRAny:	case iPTRAny:
	case iAny:	case iAny:
	case fAny:	case fAny:

	assert(0 && "Value type is overloaded.");	llvm_unreachable("Value type is overloaded.");
	default:	default:

	assert(0 && "getSizeInBits called on extended MVT.");	llvm_unreachable("getSizeInBits called on extended MVT.");
	case i1 : return 1;	case i1 : return 1;
	case i8 : return 8;	case i8 : return 8;
	case i16 :	case i16 :

		case f16:
	case v2i8: return 16;	case v2i8: return 16;
	case f32 :	case f32 :
	case i32 :	case i32 :
	case v4i8:	case v4i8:

	case v2i16: return 32;	case v2i16:
		case v2f16: return 32;
	case x86mmx:	case x86mmx:
	case f64 :	case f64 :
	case i64 :	case i64 :
	case v8i8:	case v8i8:
	case v4i16:	case v4i16:
	case v2i32:	case v2i32:
	case v1i64:	case v1i64:
	case v2f32: return 64;	case v2f32: return 64;
	case f80 : return 80;	case f80 : return 80;
	case f128:	case f128:

	skipping to change at line 303	skipping to change at line 317

	/// getStoreSizeInBits - Return the number of bits overwritten by a sto re	/// getStoreSizeInBits - Return the number of bits overwritten by a sto re
	/// of the specified value type.	/// of the specified value type.
	unsigned getStoreSizeInBits() const {	unsigned getStoreSizeInBits() const {
	return getStoreSize() * 8;	return getStoreSize() * 8;
	}	}

	static MVT getFloatingPointVT(unsigned BitWidth) {	static MVT getFloatingPointVT(unsigned BitWidth) {
	switch (BitWidth) {	switch (BitWidth) {
	default:	default:

	assert(false && "Bad bit width!");	llvm_unreachable("Bad bit width!");
		case 16:
		return MVT::f16;
	case 32:	case 32:
	return MVT::f32;	return MVT::f32;
	case 64:	case 64:
	return MVT::f64;	return MVT::f64;
	case 80:	case 80:
	return MVT::f80;	return MVT::f80;
	case 128:	case 128:
	return MVT::f128;	return MVT::f128;
	}	}
	}	}

	skipping to change at line 362	skipping to change at line 378
	if (NumElements == 2) return MVT::v2i32;	if (NumElements == 2) return MVT::v2i32;
	if (NumElements == 4) return MVT::v4i32;	if (NumElements == 4) return MVT::v4i32;
	if (NumElements == 8) return MVT::v8i32;	if (NumElements == 8) return MVT::v8i32;
	break;	break;
	case MVT::i64:	case MVT::i64:
	if (NumElements == 1) return MVT::v1i64;	if (NumElements == 1) return MVT::v1i64;
	if (NumElements == 2) return MVT::v2i64;	if (NumElements == 2) return MVT::v2i64;
	if (NumElements == 4) return MVT::v4i64;	if (NumElements == 4) return MVT::v4i64;
	if (NumElements == 8) return MVT::v8i64;	if (NumElements == 8) return MVT::v8i64;
	break;	break;

		case MVT::f16:
		if (NumElements == 2) return MVT::v2f16;
		break;
	case MVT::f32:	case MVT::f32:
	if (NumElements == 2) return MVT::v2f32;	if (NumElements == 2) return MVT::v2f32;
	if (NumElements == 4) return MVT::v4f32;	if (NumElements == 4) return MVT::v4f32;
	if (NumElements == 8) return MVT::v8f32;	if (NumElements == 8) return MVT::v8f32;
	break;	break;
	case MVT::f64:	case MVT::f64:
	if (NumElements == 2) return MVT::v2f64;	if (NumElements == 2) return MVT::v2f64;
	if (NumElements == 4) return MVT::v4f64;	if (NumElements == 4) return MVT::v4f64;
	break;	break;
	}	}

	skipping to change at line 426	skipping to change at line 445

	/// getVectorVT - Returns the EVT that represents a vector NumElements in	/// getVectorVT - Returns the EVT that represents a vector NumElements in
	/// length, where each element is of type VT.	/// length, where each element is of type VT.
	static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElemen ts) {	static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElemen ts) {
	MVT M = MVT::getVectorVT(VT.V, NumElements);	MVT M = MVT::getVectorVT(VT.V, NumElements);
	if (M.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE)	if (M.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE)
	return M;	return M;
	return getExtendedVectorVT(Context, VT, NumElements);	return getExtendedVectorVT(Context, VT, NumElements);
	}	}


	/// getIntVectorWithNumElements - Return any integer vector type that h
	as
	/// the specified number of elements.
	static EVT getIntVectorWithNumElements(LLVMContext &C, unsigned NumElts
	) {
	switch (NumElts) {
	default: return getVectorVT(C, MVT::i8, NumElts);
	case 1: return MVT::v1i64;
	case 2: return MVT::v2i32;
	case 4: return MVT::v4i16;
	case 8: return MVT::v8i8;
	case 16: return MVT::v16i8;
	}
	return MVT::INVALID_SIMPLE_VALUE_TYPE;
	}

	/// changeVectorElementTypeToInteger - Return a vector with the same nu mber	/// changeVectorElementTypeToInteger - Return a vector with the same nu mber
	/// of elements as this vector, but with the element type converted to an	/// of elements as this vector, but with the element type converted to an
	/// integer type with the same bitwidth.	/// integer type with the same bitwidth.
	EVT changeVectorElementTypeToInteger() const {	EVT changeVectorElementTypeToInteger() const {
	if (!isSimple())	if (!isSimple())
	return changeExtendedVectorElementTypeToInteger();	return changeExtendedVectorElementTypeToInteger();
	MVT EltTy = getSimpleVT().getVectorElementType();	MVT EltTy = getSimpleVT().getVectorElementType();
	unsigned BitWidth = EltTy.getSizeInBits();	unsigned BitWidth = EltTy.getSizeInBits();
	MVT IntTy = MVT::getIntegerVT(BitWidth);	MVT IntTy = MVT::getIntegerVT(BitWidth);
	MVT VecTy = MVT::getVectorVT(IntTy, getVectorNumElements());	MVT VecTy = MVT::getVectorVT(IntTy, getVectorNumElements());

End of changes. 21 change blocks.
	58 lines changed or deleted	61 lines changed or added

	ValueTypes.td	ValueTypes.td

	skipping to change at line 29	skipping to change at line 29
	int Value = value;	int Value = value;
	}	}

	def OtherVT: ValueType<0 , 0>; // "Other" value	def OtherVT: ValueType<0 , 0>; // "Other" value
	def i1 : ValueType<1 , 1>; // One bit boolean value	def i1 : ValueType<1 , 1>; // One bit boolean value
	def i8 : ValueType<8 , 2>; // 8-bit integer value	def i8 : ValueType<8 , 2>; // 8-bit integer value
	def i16 : ValueType<16 , 3>; // 16-bit integer value	def i16 : ValueType<16 , 3>; // 16-bit integer value
	def i32 : ValueType<32 , 4>; // 32-bit integer value	def i32 : ValueType<32 , 4>; // 32-bit integer value
	def i64 : ValueType<64 , 5>; // 64-bit integer value	def i64 : ValueType<64 , 5>; // 64-bit integer value
	def i128 : ValueType<128, 6>; // 128-bit integer value	def i128 : ValueType<128, 6>; // 128-bit integer value

	def f32 : ValueType<32 , 7>; // 32-bit floating point value	def f16 : ValueType<16 , 7>; // 32-bit floating point value
	def f64 : ValueType<64 , 8>; // 64-bit floating point value	def f32 : ValueType<32 , 8>; // 32-bit floating point value
	def f80 : ValueType<80 , 9>; // 80-bit floating point value	def f64 : ValueType<64 , 9>; // 64-bit floating point value
	def f128 : ValueType<128, 10>; // 128-bit floating point value	def f80 : ValueType<80 , 10>; // 80-bit floating point value
	def ppcf128: ValueType<128, 11>; // PPC 128-bit floating point value	def f128 : ValueType<128, 11>; // 128-bit floating point value
		def ppcf128: ValueType<128, 12>; // PPC 128-bit floating point value
	def v2i8 : ValueType<16 , 12>; // 2 x i8 vector value
	def v4i8 : ValueType<32 , 13>; // 4 x i8 vector value	def v2i8 : ValueType<16 , 13>; // 2 x i8 vector value
	def v8i8 : ValueType<64 , 14>; // 8 x i8 vector value	def v4i8 : ValueType<32 , 14>; // 4 x i8 vector value
	def v16i8 : ValueType<128, 15>; // 16 x i8 vector value	def v8i8 : ValueType<64 , 15>; // 8 x i8 vector value
	def v32i8 : ValueType<256, 16>; // 32 x i8 vector value	def v16i8 : ValueType<128, 16>; // 16 x i8 vector value
	def v2i16 : ValueType<32 , 17>; // 2 x i16 vector value	def v32i8 : ValueType<256, 17>; // 32 x i8 vector value
	def v4i16 : ValueType<64 , 18>; // 4 x i16 vector value	def v2i16 : ValueType<32 , 18>; // 2 x i16 vector value
	def v8i16 : ValueType<128, 19>; // 8 x i16 vector value	def v4i16 : ValueType<64 , 19>; // 4 x i16 vector value
	def v16i16 : ValueType<256, 20>; // 16 x i16 vector value	def v8i16 : ValueType<128, 20>; // 8 x i16 vector value
	def v2i32 : ValueType<64 , 21>; // 2 x i32 vector value	def v16i16 : ValueType<256, 21>; // 16 x i16 vector value
	def v4i32 : ValueType<128, 22>; // 4 x i32 vector value	def v2i32 : ValueType<64 , 22>; // 2 x i32 vector value
	def v8i32 : ValueType<256, 23>; // 8 x i32 vector value	def v4i32 : ValueType<128, 23>; // 4 x i32 vector value
	def v1i64 : ValueType<64 , 24>; // 1 x i64 vector value	def v8i32 : ValueType<256, 24>; // 8 x i32 vector value
	def v2i64 : ValueType<128, 25>; // 2 x i64 vector value	def v1i64 : ValueType<64 , 25>; // 1 x i64 vector value
	def v4i64 : ValueType<256, 26>; // 4 x i64 vector value	def v2i64 : ValueType<128, 26>; // 2 x i64 vector value
	def v8i64 : ValueType<512, 27>; // 8 x i64 vector value	def v4i64 : ValueType<256, 27>; // 4 x i64 vector value
		def v8i64 : ValueType<512, 28>; // 8 x i64 vector value
	def v2f32 : ValueType<64 , 28>; // 2 x f32 vector value
	def v4f32 : ValueType<128, 29>; // 4 x f32 vector value	def v2f16 : ValueType<32 , 29>; // 2 x f16 vector value
	def v8f32 : ValueType<256, 30>; // 8 x f32 vector value	def v2f32 : ValueType<64 , 30>; // 2 x f32 vector value
	def v2f64 : ValueType<128, 31>; // 2 x f64 vector value	def v4f32 : ValueType<128, 31>; // 4 x f32 vector value
	def v4f64 : ValueType<256, 32>; // 4 x f64 vector value	def v8f32 : ValueType<256, 32>; // 8 x f32 vector value
		def v2f64 : ValueType<128, 33>; // 2 x f64 vector value
	def x86mmx : ValueType<64 , 33>; // X86 MMX value	def v4f64 : ValueType<256, 34>; // 4 x f64 vector value
	def FlagVT : ValueType<0 , 34>; // Pre-RA sched glue
	def isVoid : ValueType<0 , 35>; // Produces no value	def x86mmx : ValueType<64 , 35>; // X86 MMX value
	def untyped: ValueType<8 , 36>; // Produces an untyped value	def FlagVT : ValueType<0 , 36>; // Pre-RA sched glue
		def isVoid : ValueType<0 , 37>; // Produces no value
		def untyped: ValueType<8 , 38>; // Produces an untyped value

	def MetadataVT: ValueType<0, 250>; // Metadata	def MetadataVT: ValueType<0, 250>; // Metadata

	// Pseudo valuetype mapped to the current pointer size to any address space .	// Pseudo valuetype mapped to the current pointer size to any address space .
	// Should only be used in TableGen.	// Should only be used in TableGen.
	def iPTRAny : ValueType<0, 251>;	def iPTRAny : ValueType<0, 251>;

	// Pseudo valuetype to represent "vector of any size"	// Pseudo valuetype to represent "vector of any size"
	def vAny : ValueType<0 , 252>;	def vAny : ValueType<0 , 252>;


End of changes. 1 change blocks.
	33 lines changed or deleted	35 lines changed or added

	Writer.h	Writer.h

	skipping to change at line 22	skipping to change at line 22
	// can print LLVM code at a variety of granularities, including Modules,	// can print LLVM code at a variety of granularities, including Modules,
	// BasicBlocks, and Instructions. This makes it useful for debugging.	// BasicBlocks, and Instructions. This makes it useful for debugging.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_ASSEMBLY_WRITER_H	#ifndef LLVM_ASSEMBLY_WRITER_H
	#define LLVM_ASSEMBLY_WRITER_H	#define LLVM_ASSEMBLY_WRITER_H

	namespace llvm {	namespace llvm {


	class Type;
	class Module;	class Module;
	class Value;	class Value;
	class raw_ostream;	class raw_ostream;

	// WriteAsOperand - Write the name of the specified value out to the specif ied	// WriteAsOperand - Write the name of the specified value out to the specif ied
	// ostream. This can be useful when you just want to print int %reg126, no t the	// ostream. This can be useful when you just want to print int %reg126, no t the
	// whole instruction that generated it. If you specify a Module for contex t,	// whole instruction that generated it. If you specify a Module for contex t,
	// then even constants get pretty-printed; for example, the type of a null	// then even constants get pretty-printed; for example, the type of a null
	// pointer is printed symbolically.	// pointer is printed symbolically.
	//	//

End of changes. 1 change blocks.
	1 lines changed or deleted	0 lines changed or added

	config.h	config.h

	skipping to change at line 13	skipping to change at line 13

	#ifndef CONFIG_H	#ifndef CONFIG_H
	#define CONFIG_H	#define CONFIG_H

	/* Bug report URL. */	/* Bug report URL. */
	#define BUG_REPORT_URL "http://llvm.org/bugs/"	#define BUG_REPORT_URL "http://llvm.org/bugs/"

	/* Relative directory for resource files */	/* Relative directory for resource files */
	#define CLANG_RESOURCE_DIR ""	#define CLANG_RESOURCE_DIR ""


	/* 32 bit multilib directory. */
	#define CXX_INCLUDE_32BIT_DIR ""

	/* 64 bit multilib directory. */
	#define CXX_INCLUDE_64BIT_DIR ""

	/* Arch the libstdc++ headers. */
	#define CXX_INCLUDE_ARCH ""

	/* Directory with the libstdc++ headers. */
	#define CXX_INCLUDE_ROOT ""

	/* Directories clang will search for headers */	/* Directories clang will search for headers */
	#define C_INCLUDE_DIRS ""	#define C_INCLUDE_DIRS ""


	/* Define if CBE is enabled for printf %a output */	/* Default <path> to all compiler invocations for --sysroot=<path>. */
	#define ENABLE_CBE_PRINTF_A 1	#define DEFAULT_SYSROOT ""

	/* Define if position independent code is enabled */	/* Define if position independent code is enabled */
	#define ENABLE_PIC 1	#define ENABLE_PIC 1


	/* Define if threads enabled */
	#define ENABLE_THREADS 1

	/* Define if timestamp information (e.g., __DATE___) is allowed */	/* Define if timestamp information (e.g., __DATE___) is allowed */
	#define ENABLE_TIMESTAMPS 1	#define ENABLE_TIMESTAMPS 1


		/* Directory where gcc is installed. */
		#define GCC_INSTALL_PREFIX ""

	/* Define to 1 if you have the `argz_append' function. */	/* Define to 1 if you have the `argz_append' function. */
	#define HAVE_ARGZ_APPEND 1	#define HAVE_ARGZ_APPEND 1

	/* Define to 1 if you have the `argz_create_sep' function. */	/* Define to 1 if you have the `argz_create_sep' function. */
	#define HAVE_ARGZ_CREATE_SEP 1	#define HAVE_ARGZ_CREATE_SEP 1

	/* Define to 1 if you have the <argz.h> header file. */	/* Define to 1 if you have the <argz.h> header file. */
	#define HAVE_ARGZ_H 1	#define HAVE_ARGZ_H 1

	/* Define to 1 if you have the `argz_insert' function. */	/* Define to 1 if you have the `argz_insert' function. */

	skipping to change at line 299	skipping to change at line 287

	/* Define to 1 if you have the `opendir' function. */	/* Define to 1 if you have the `opendir' function. */
	#define HAVE_OPENDIR 1	#define HAVE_OPENDIR 1

	/* Define to 1 if you have the `posix_spawn' function. */	/* Define to 1 if you have the `posix_spawn' function. */
	#define HAVE_POSIX_SPAWN 1	#define HAVE_POSIX_SPAWN 1

	/* Define to 1 if you have the `powf' function. */	/* Define to 1 if you have the `powf' function. */
	#define HAVE_POWF 1	#define HAVE_POWF 1


		/* Define to 1 if you have the `pread' function. */
		#define HAVE_PREAD 1

	/* Define if libtool can extract symbol lists from object files. */	/* Define if libtool can extract symbol lists from object files. */
	#define HAVE_PRELOADED_SYMBOLS 1	#define HAVE_PRELOADED_SYMBOLS 1

	/* Define to have the %a format string */	/* Define to have the %a format string */
	#define HAVE_PRINTF_A 1	#define HAVE_PRINTF_A 1

	/* Have pthread_getspecific */	/* Have pthread_getspecific */
	#define HAVE_PTHREAD_GETSPECIFIC 1	#define HAVE_PTHREAD_GETSPECIFIC 1

	/* Define to 1 if you have the <pthread.h> header file. */	/* Define to 1 if you have the <pthread.h> header file. */

	skipping to change at line 375	skipping to change at line 366
	/* Define to 1 if you have the <stdint.h> header file. */	/* Define to 1 if you have the <stdint.h> header file. */
	#define HAVE_STDINT_H 1	#define HAVE_STDINT_H 1

	/* Define to 1 if you have the <stdio.h> header file. */	/* Define to 1 if you have the <stdio.h> header file. */
	#define HAVE_STDIO_H 1	#define HAVE_STDIO_H 1

	/* Define to 1 if you have the <stdlib.h> header file. */	/* Define to 1 if you have the <stdlib.h> header file. */
	#define HAVE_STDLIB_H 1	#define HAVE_STDLIB_H 1

	/* Set to 1 if the std::isinf function is found in <cmath> */	/* Set to 1 if the std::isinf function is found in <cmath> */

	/* #undef HAVE_STD_ISINF_IN_CMATH */	#define HAVE_STD_ISINF_IN_CMATH 1

	/* Set to 1 if the std::isnan function is found in <cmath> */	/* Set to 1 if the std::isnan function is found in <cmath> */
	#define HAVE_STD_ISNAN_IN_CMATH 1	#define HAVE_STD_ISNAN_IN_CMATH 1

	/* Define to 1 if you have the `strchr' function. */	/* Define to 1 if you have the `strchr' function. */
	#define HAVE_STRCHR 1	#define HAVE_STRCHR 1

	/* Define to 1 if you have the `strcmp' function. */	/* Define to 1 if you have the `strcmp' function. */
	#define HAVE_STRCMP 1	#define HAVE_STRCMP 1


	skipping to change at line 539	skipping to change at line 530
	/* Have host's __umoddi3 */	/* Have host's __umoddi3 */
	/* #undef HAVE___UMODDI3 */	/* #undef HAVE___UMODDI3 */

	/* Have host's ___chkstk */	/* Have host's ___chkstk */
	/* #undef HAVE____CHKSTK */	/* #undef HAVE____CHKSTK */

	/* Linker version detected at compile time. */	/* Linker version detected at compile time. */
	#define HOST_LINK_VERSION "2.21.52.0.2.20110610"	#define HOST_LINK_VERSION "2.21.52.0.2.20110610"

	/* Installation directory for binary executables */	/* Installation directory for binary executables */

	#define LLVM_BINDIR "/home/ut/testing/llvm/3.0/bin"	#define LLVM_BINDIR "/home/ut/testing/llvm/3.1/bin"

	/* Time at which LLVM was configured */	/* Time at which LLVM was configured */

	#define LLVM_CONFIGTIME "Wed Jan 9 17:39:20 MSK 2013"	#define LLVM_CONFIGTIME "Wed Jan 9 15:19:52 MSK 2013"

	/* Installation directory for data files */	/* Installation directory for data files */

	#define LLVM_DATADIR "/home/ut/testing/llvm/3.0/share/llvm"	#define LLVM_DATADIR "/home/ut/testing/llvm/3.1/share/llvm"

		/* Target triple LLVM will generate code for by default */
		#define LLVM_DEFAULT_TARGET_TRIPLE "i686-pc-linux-gnu"

	/* Installation directory for documentation */	/* Installation directory for documentation */

	#define LLVM_DOCSDIR "/home/ut/testing/llvm/3.0/share/doc/llvm"	#define LLVM_DOCSDIR "/home/ut/testing/llvm/3.1/share/doc/llvm"

		/* Define if threads enabled */
		#define LLVM_ENABLE_THREADS 1

	/* Installation directory for config files */	/* Installation directory for config files */

	#define LLVM_ETCDIR "/home/ut/testing/llvm/3.0/etc/llvm"	#define LLVM_ETCDIR "/home/ut/testing/llvm/3.1/etc/llvm"

	/* Has gcc/MSVC atomic intrinsics */	/* Has gcc/MSVC atomic intrinsics */
	#define LLVM_HAS_ATOMICS 1	#define LLVM_HAS_ATOMICS 1


	/* Host triple we were built on */
	#define LLVM_HOSTTRIPLE "i686-pc-linux-gnu"

	/* Installation directory for include files */	/* Installation directory for include files */

	#define LLVM_INCLUDEDIR "/home/ut/testing/llvm/3.0/include"	#define LLVM_INCLUDEDIR "/home/ut/testing/llvm/3.1/include"

	/* Installation directory for .info files */	/* Installation directory for .info files */

	#define LLVM_INFODIR "/home/ut/testing/llvm/3.0/info"	#define LLVM_INFODIR "/home/ut/testing/llvm/3.1/info"

	/* Installation directory for libraries */	/* Installation directory for libraries */

	#define LLVM_LIBDIR "/home/ut/testing/llvm/3.0/lib"	#define LLVM_LIBDIR "/home/ut/testing/llvm/3.1/lib"

	/* Installation directory for man pages */	/* Installation directory for man pages */

	#define LLVM_MANDIR "/home/ut/testing/llvm/3.0/man"	#define LLVM_MANDIR "/home/ut/testing/llvm/3.1/man"

	/* LLVM architecture name for the native architecture, if available */	/* LLVM architecture name for the native architecture, if available */
	#define LLVM_NATIVE_ARCH X86	#define LLVM_NATIVE_ARCH X86

	/* LLVM name for the native AsmParser init function, if available */	/* LLVM name for the native AsmParser init function, if available */
	#define LLVM_NATIVE_ASMPARSER LLVMInitializeX86AsmParser	#define LLVM_NATIVE_ASMPARSER LLVMInitializeX86AsmParser

	/* LLVM name for the native AsmPrinter init function, if available */	/* LLVM name for the native AsmPrinter init function, if available */
	#define LLVM_NATIVE_ASMPRINTER LLVMInitializeX86AsmPrinter	#define LLVM_NATIVE_ASMPRINTER LLVMInitializeX86AsmPrinter


		/* LLVM name for the native Disassembler init function, if available */
		#define LLVM_NATIVE_DISASSEMBLER LLVMInitializeX86Disassembler

	/* LLVM name for the native Target init function, if available */	/* LLVM name for the native Target init function, if available */
	#define LLVM_NATIVE_TARGET LLVMInitializeX86Target	#define LLVM_NATIVE_TARGET LLVMInitializeX86Target

	/* LLVM name for the native TargetInfo init function, if available */	/* LLVM name for the native TargetInfo init function, if available */
	#define LLVM_NATIVE_TARGETINFO LLVMInitializeX86TargetInfo	#define LLVM_NATIVE_TARGETINFO LLVMInitializeX86TargetInfo

	/* LLVM name for the native target MC init function, if available */	/* LLVM name for the native target MC init function, if available */
	#define LLVM_NATIVE_TARGETMC LLVMInitializeX86TargetMC	#define LLVM_NATIVE_TARGETMC LLVMInitializeX86TargetMC

	/* Define if this is Unixish platform */	/* Define if this is Unixish platform */

	skipping to change at line 623	skipping to change at line 620
	/* Define to path to neato program if found or 'echo neato' otherwise */	/* Define to path to neato program if found or 'echo neato' otherwise */
	#define LLVM_PATH_NEATO "/usr/bin/neato"	#define LLVM_PATH_NEATO "/usr/bin/neato"

	/* Define to path to twopi program if found or 'echo twopi' otherwise */	/* Define to path to twopi program if found or 'echo twopi' otherwise */
	#define LLVM_PATH_TWOPI "/usr/bin/twopi"	#define LLVM_PATH_TWOPI "/usr/bin/twopi"

	/* Define to path to xdot.py program if found or 'echo xdot.py' otherwise * /	/* Define to path to xdot.py program if found or 'echo xdot.py' otherwise * /
	/* #undef LLVM_PATH_XDOT_PY */	/* #undef LLVM_PATH_XDOT_PY */

	/* Installation prefix directory */	/* Installation prefix directory */

	#define LLVM_PREFIX "/home/ut/testing/llvm/3.0"	#define LLVM_PREFIX "/home/ut/testing/llvm/3.1"

		/* Define if we have the Intel JIT API runtime support library */
		#define LLVM_USE_INTEL_JITEVENTS 0

		/* Define if we have the oprofile JIT-support library */
		#define LLVM_USE_OPROFILE 0

		/* Major version of the LLVM API */
		#define LLVM_VERSION_MAJOR 3

		/* Minor version of the LLVM API */
		#define LLVM_VERSION_MINOR 1

	/* Define if the OS needs help to load dependent libraries for dlopen(). */	/* Define if the OS needs help to load dependent libraries for dlopen(). */
	/* #undef LTDL_DLOPEN_DEPLIBS */	/* #undef LTDL_DLOPEN_DEPLIBS */

	/* Define to the sub-directory in which libtool stores uninstalled librarie s.	/* Define to the sub-directory in which libtool stores uninstalled librarie s.
	*/	*/
	#define LTDL_OBJDIR ".libs/"	#define LTDL_OBJDIR ".libs/"

	/* Define to the name of the environment variable that determines the dynam ic	/* Define to the name of the environment variable that determines the dynam ic
	library search path. */	library search path. */

	skipping to change at line 650	skipping to change at line 659
	#define LTDL_SYSSEARCHPATH "/lib:/usr/lib:/usr/lib/atlas-sse:/usr/lib/atlas -sse3:/usr/lib/atlas:/usr/lib/paraview-mpi"	#define LTDL_SYSSEARCHPATH "/lib:/usr/lib:/usr/lib/atlas-sse:/usr/lib/atlas -sse3:/usr/lib/atlas:/usr/lib/paraview-mpi"

	/* Define if /dev/zero should be used when mapping RWX memory, or undefine if	/* Define if /dev/zero should be used when mapping RWX memory, or undefine if
	its not necessary */	its not necessary */
	/* #undef NEED_DEV_ZERO_FOR_MMAP */	/* #undef NEED_DEV_ZERO_FOR_MMAP */

	/* Define if dlsym() requires a leading underscore in symbol names. */	/* Define if dlsym() requires a leading underscore in symbol names. */
	/* #undef NEED_USCORE */	/* #undef NEED_USCORE */

	/* Define to the address where bug reports for this package should be sent. */	/* Define to the address where bug reports for this package should be sent. */

	#define PACKAGE_BUGREPORT "llvmbugs@cs.uiuc.edu"	#define PACKAGE_BUGREPORT "http://llvm.org/bugs/"

	/* Define to the full name of this package. */	/* Define to the full name of this package. */

	#define PACKAGE_NAME "llvm"	#define PACKAGE_NAME "LLVM"

	/* Define to the full name and version of this package. */	/* Define to the full name and version of this package. */

	#define PACKAGE_STRING "llvm 3.0"	#define PACKAGE_STRING "LLVM 3.1"

	/* Define to the one symbol short name of this package. */	/* Define to the one symbol short name of this package. */

	#define PACKAGE_TARNAME "-llvm-"	#define PACKAGE_TARNAME "llvm"

	/* Define to the version of this package. */	/* Define to the version of this package. */

	#define PACKAGE_VERSION "3.0"	#define PACKAGE_VERSION "3.1"

	/* Define as the return type of signal handlers (`int' or `void'). */	/* Define as the return type of signal handlers (`int' or `void'). */
	#define RETSIGTYPE void	#define RETSIGTYPE void

	/* Define to 1 if the `S_IS' macros in <sys/stat.h> do not work properly. /	/* Define to 1 if the `S_IS' macros in <sys/stat.h> do not work properly. /
	/* #undef STAT_MACROS_BROKEN */	/* #undef STAT_MACROS_BROKEN */

	/* Define to 1 if you have the ANSI C header files. */	/* Define to 1 if you have the ANSI C header files. */
	#define STDC_HEADERS 1	#define STDC_HEADERS 1

	/* Define to 1 if you can safely include both <sys/time.h> and <time.h>. */	/* Define to 1 if you can safely include both <sys/time.h> and <time.h>. */
	#define TIME_WITH_SYS_TIME 1	#define TIME_WITH_SYS_TIME 1

	/* Define to 1 if your <sys/time.h> declares `struct tm'. */	/* Define to 1 if your <sys/time.h> declares `struct tm'. */
	/* #undef TM_IN_SYS_TIME */	/* #undef TM_IN_SYS_TIME */


	/* Define if we have the oprofile JIT-support library */
	#define USE_OPROFILE 0

	/* Define if use udis86 library */	/* Define if use udis86 library */
	#define USE_UDIS86 0	#define USE_UDIS86 0

	/* Type of 1st arg on ELM Callback */	/* Type of 1st arg on ELM Callback */
	/* #undef WIN32_ELMCB_PCSTR */	/* #undef WIN32_ELMCB_PCSTR */

	/* Define to empty if `const' does not conform to ANSI C. */	/* Define to empty if `const' does not conform to ANSI C. */
	/* #undef const */	/* #undef const */

	/* Define to a type to use for `error_t' if it is not otherwise available. */	/* Define to a type to use for `error_t' if it is not otherwise available. */

End of changes. 24 change blocks.
	39 lines changed or deleted	45 lines changed or added

	ilist.h	ilist.h

	skipping to change at line 647	skipping to change at line 647

	// Main implementation here - Insert for a node passed by value...	// Main implementation here - Insert for a node passed by value...
	iterator insert(iterator where, const NodeTy &val) {	iterator insert(iterator where, const NodeTy &val) {
	return insert(where, this->createNode(val));	return insert(where, this->createNode(val));
	}	}

	// Front and back inserters...	// Front and back inserters...
	void push_front(const NodeTy &val) { insert(this->begin(), val); }	void push_front(const NodeTy &val) { insert(this->begin(), val); }
	void push_back(const NodeTy &val) { insert(this->end(), val); }	void push_back(const NodeTy &val) { insert(this->end(), val); }


	// Special forms of insert...
	template<class InIt> void insert(iterator where, InIt first, InIt last) {
	for (; first != last; ++first) insert(where, *first);
	}
	void insert(iterator where, size_type count, const NodeTy &val) {	void insert(iterator where, size_type count, const NodeTy &val) {
	for (; count != 0; --count) insert(where, val);	for (; count != 0; --count) insert(where, val);
	}	}

	// Assign special forms...	// Assign special forms...
	void assign(size_type count, const NodeTy &val) {	void assign(size_type count, const NodeTy &val) {
	iterator I = this->begin();	iterator I = this->begin();
	for (; I != this->end() && count != 0; ++I, --count)	for (; I != this->end() && count != 0; ++I, --count)
	*I = val;	*I = val;
	if (count != 0)	if (count != 0)

End of changes. 1 change blocks.
	4 lines changed or deleted	0 lines changed or added

	lto.h	lto.h

	skipping to change at line 23	skipping to change at line 23
	\|* *\|	\|* *\|
	\===---------------------------------------------------------------------- ===/	\===---------------------------------------------------------------------- ===/

	#ifndef LTO_H	#ifndef LTO_H
	#define LTO_H 1	#define LTO_H 1

	#include <stdbool.h>	#include <stdbool.h>
	#include <stddef.h>	#include <stddef.h>
	#include <unistd.h>	#include <unistd.h>


		/**
		* @defgroup LLVMCLTO LTO
		* @ingroup LLVMC
		*
		* @{
		*/

	#define LTO_API_VERSION 4	#define LTO_API_VERSION 4

	typedef enum {	typedef enum {
	LTO_SYMBOL_ALIGNMENT_MASK = 0x0000001F, /* log2 of alignme nt */	LTO_SYMBOL_ALIGNMENT_MASK = 0x0000001F, /* log2 of alignme nt */
	LTO_SYMBOL_PERMISSIONS_MASK = 0x000000E0,	LTO_SYMBOL_PERMISSIONS_MASK = 0x000000E0,
	LTO_SYMBOL_PERMISSIONS_CODE = 0x000000A0,	LTO_SYMBOL_PERMISSIONS_CODE = 0x000000A0,
	LTO_SYMBOL_PERMISSIONS_DATA = 0x000000C0,	LTO_SYMBOL_PERMISSIONS_DATA = 0x000000C0,
	LTO_SYMBOL_PERMISSIONS_RODATA = 0x00000080,	LTO_SYMBOL_PERMISSIONS_RODATA = 0x00000080,
	LTO_SYMBOL_DEFINITION_MASK = 0x00000700,	LTO_SYMBOL_DEFINITION_MASK = 0x00000700,
	LTO_SYMBOL_DEFINITION_REGULAR = 0x00000100,	LTO_SYMBOL_DEFINITION_REGULAR = 0x00000100,

	skipping to change at line 264	skipping to change at line 271
	* The name of the file is written to name. Returns true on error.	* The name of the file is written to name. Returns true on error.
	*/	*/
	extern bool	extern bool
	lto_codegen_compile_to_file(lto_code_gen_t cg, const char** name);	lto_codegen_compile_to_file(lto_code_gen_t cg, const char** name);

	/**	/**
	* Sets options to help debug codegen bugs.	* Sets options to help debug codegen bugs.
	*/	*/
	extern void	extern void
	lto_codegen_debug_options(lto_code_gen_t cg, const char *);	lto_codegen_debug_options(lto_code_gen_t cg, const char *);


	#ifdef __cplusplus	#ifdef __cplusplus
	}	}
	#endif	#endif


		/**
		* @}
		*/

	#endif	#endif

End of changes. 3 change blocks.
	0 lines changed or deleted	12 lines changed or added

	system_error.h	system_error.h

	skipping to change at line 473	skipping to change at line 473
	# ifndef EOVERFLOW	# ifndef EOVERFLOW
	# define EOVERFLOW 132	# define EOVERFLOW 132
	# endif	# endif
	# ifndef EPROTOTYPE	# ifndef EPROTOTYPE
	# define EPROTOTYPE 136	# define EPROTOTYPE 136
	# endif	# endif
	#endif	#endif

	namespace llvm {	namespace llvm {


	template <class T, T v>
	struct integral_constant {
	typedef T value_type;
	static const value_type value = v;
	typedef integral_constant<T,v> type;
	operator value_type() { return value; }
	};

	typedef integral_constant<bool, true> true_type;
	typedef integral_constant<bool, false> false_type;

	// is_error_code_enum	// is_error_code_enum

	template <class Tp> struct is_error_code_enum : public false_type {};	template <class Tp> struct is_error_code_enum : public false_type {};

	// is_error_condition_enum	// is_error_condition_enum

	template <class Tp> struct is_error_condition_enum : public false_type {};	template <class Tp> struct is_error_condition_enum : public false_type {};

	// Some error codes are not present on all platforms, so we provide equival ents	// Some error codes are not present on all platforms, so we provide equival ents
	// for them:	// for them:

	skipping to change at line 741	skipping to change at line 730
	}	}

	// error_code	// error_code

	class error_code {	class error_code {
	int _val_;	int _val_;
	const error_category* _cat_;	const error_category* _cat_;
	public:	public:
	error_code() : _val_(0), _cat_(&system_category()) {}	error_code() : _val_(0), _cat_(&system_category()) {}


		static error_code success() {
		return error_code();
		}

	error_code(int _val, const error_category& _cat)	error_code(int _val, const error_category& _cat)
	: _val_(_val), _cat_(&_cat) {}	: _val_(_val), _cat_(&_cat) {}

	template <class E>	template <class E>
	error_code(E _e, typename enable_if_c<	error_code(E _e, typename enable_if_c<
	is_error_code_enum<E>::value	is_error_code_enum<E>::value
	>::type* = 0) {	>::type* = 0) {
	*this = make_error_code(_e);	*this = make_error_code(_e);
	}	}


End of changes. 2 change blocks.
	11 lines changed or deleted	4 lines changed or added

	type_traits.h	type_traits.h

	skipping to change at line 20	skipping to change at line 20
	// This file provides a template class that determines if a type is a class or	// This file provides a template class that determines if a type is a class or
	// not. The basic mechanism, based on using the pointer to member function of	// not. The basic mechanism, based on using the pointer to member function of
	// a zero argument to a function was "boosted" from the boost type_traits	// a zero argument to a function was "boosted" from the boost type_traits
	// library. See http://www.boost.org/ for all the gory details.	// library. See http://www.boost.org/ for all the gory details.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_SUPPORT_TYPE_TRAITS_H	#ifndef LLVM_SUPPORT_TYPE_TRAITS_H
	#define LLVM_SUPPORT_TYPE_TRAITS_H	#define LLVM_SUPPORT_TYPE_TRAITS_H


		#include "llvm/Support/DataTypes.h"
		#include <cstddef>
	#include <utility>	#include <utility>

	// This is actually the conforming implementation which works with abstract	// This is actually the conforming implementation which works with abstract
	// classes. However, enough compilers have trouble with it that most will use	// classes. However, enough compilers have trouble with it that most will use
	// the one in boost/type_traits/object_traits.hpp. This implementation actu ally	// the one in boost/type_traits/object_traits.hpp. This implementation actu ally
	// works with VC7.0, but other interactions seem to fail when we use it.	// works with VC7.0, but other interactions seem to fail when we use it.

	namespace llvm {	namespace llvm {

	namespace dont_use	namespace dont_use

	skipping to change at line 66	skipping to change at line 68
	template <typename T>	template <typename T>
	struct isPodLike {	struct isPodLike {
	// If we don't know anything else, we can (at least) assume that all non- class	// If we don't know anything else, we can (at least) assume that all non- class
	// types are PODs.	// types are PODs.
	static const bool value = !is_class<T>::value;	static const bool value = !is_class<T>::value;
	};	};

	// std::pair's are pod-like if their elements are.	// std::pair's are pod-like if their elements are.
	template<typename T, typename U>	template<typename T, typename U>
	struct isPodLike<std::pair<T, U> > {	struct isPodLike<std::pair<T, U> > {

	static const bool value = isPodLike<T>::value & isPodLike<U>::value;	static const bool value = isPodLike<T>::value && isPodLike<U>::value;
	};	};


		template <class T, T v>
		struct integral_constant {
		typedef T value_type;
		static const value_type value = v;
		typedef integral_constant<T,v> type;
		operator value_type() { return value; }
		};

		typedef integral_constant<bool, true> true_type;
		typedef integral_constant<bool, false> false_type;

	/// \brief Metafunction that determines whether the two given types are	/// \brief Metafunction that determines whether the two given types are
	/// equivalent.	/// equivalent.

	template<typename T, typename U>	template<typename T, typename U> struct is_same : public false_type {
	struct is_same {	};
	static const bool value = false;	template<typename T> struct is_same<T, T> : public true_type {}
	};	;

		/// \brief Metafunction that removes const qualification from a type.
		template <typename T> struct remove_const { typedef T type; };
		template <typename T> struct remove_const<const T> { typedef T type; };

		/// \brief Metafunction that removes volatile qualification from a type.
		template <typename T> struct remove_volatile { typedef T type;
		};
		template <typename T> struct remove_volatile<volatile T> { typedef T type;
		};

		/// \brief Metafunction that removes both const and volatile qualification
		from
		/// a type.
		template <typename T> struct remove_cv {
		typedef typename remove_const<typename remove_volatile<T>::type>::type ty
		pe;
		};

		/// \brief Helper to implement is_integral metafunction.
		template <typename T> struct is_integral_impl : false_type {};
		template <> struct is_integral_impl< bool> : true_type {};
		template <> struct is_integral_impl< char> : true_type {};
		template <> struct is_integral_impl< signed char> : true_type {};
		template <> struct is_integral_impl<unsigned char> : true_type {};
		template <> struct is_integral_impl< wchar_t> : true_type {};
		template <> struct is_integral_impl< short> : true_type {};
		template <> struct is_integral_impl<unsigned short> : true_type {};
		template <> struct is_integral_impl< int> : true_type {};
		template <> struct is_integral_impl<unsigned int> : true_type {};
		template <> struct is_integral_impl< long> : true_type {};
		template <> struct is_integral_impl<unsigned long> : true_type {};
		template <> struct is_integral_impl< long long> : true_type {};
		template <> struct is_integral_impl<unsigned long long> : true_type {};

		/// \brief Metafunction that determines whether the given type is an integr
		al
		/// type.
		template <typename T>
		struct is_integral : is_integral_impl<T> {};


	template<typename T>	/// \brief Metafunction to remove reference from a type.
	struct is_same<T, T> {	template <typename T> struct remove_reference { typedef T type; };
	static const bool value = true;	template <typename T> struct remove_reference<T&> { typedef T type; };

		/// \brief Metafunction that determines whether the given type is a pointer
		/// type.
		template <typename T> struct is_pointer : false_type {};
		template <typename T> struct is_pointer<T*> : true_type {};
		template <typename T> struct is_pointer<T* const> : true_type {};
		template <typename T> struct is_pointer<T* volatile> : true_type {};
		template <typename T> struct is_pointer<T* const volatile> : true_type {};

		/// \brief Metafunction that determines whether the given type is either an
		/// integral type or an enumeration type.
		///
		/// Note that this accepts potentially more integral types than we whitelis
		t
		/// above for is_integral because it is based on merely being convertible
		/// implicitly to an integral type.
		template <typename T> class is_integral_or_enum {
		// Provide an overload which can be called with anything implicitly
		// convertible to an unsigned long long. This should catch integer types
		and
		// enumeration types at least. We blacklist classes with conversion opera
		tors
		// below.
		static double check_int_convertible(unsigned long long);
		static char check_int_convertible(...);

		typedef typename remove_reference<T>::type UnderlyingT;
		static UnderlyingT &nonce_instance;

		public:
		enum {
		value = (!is_class<UnderlyingT>::value && !is_pointer<UnderlyingT>::val
		ue &&
		!is_same<UnderlyingT, float>::value &&
		!is_same<UnderlyingT, double>::value &&
		sizeof(char) != sizeof(check_int_convertible(nonce_instance)))
		};
	};	};

	// enable_if_c - Enable/disable a template based on a metafunction	// enable_if_c - Enable/disable a template based on a metafunction
	template<bool Cond, typename T = void>	template<bool Cond, typename T = void>
	struct enable_if_c {	struct enable_if_c {
	typedef T type;	typedef T type;
	};	};

	template<typename T> struct enable_if_c<false, T> { };	template<typename T> struct enable_if_c<false, T> { };


End of changes. 5 change blocks.
	8 lines changed or deleted	98 lines changed or added

This html diff was produced by rfcdiff 1.41. The latest version is available from http://tools.ietf.org/tools/rfcdiff/

	AliasAnalysis.h	AliasAnalysis.h

	skipping to change at line 330	skipping to change at line 330

	/// onlyAccessesArgPointees - Return true if functions with the specified	/// onlyAccessesArgPointees - Return true if functions with the specified
	/// behavior are known to read and write at most from objects pointed to by	/// behavior are known to read and write at most from objects pointed to by
	/// their pointer-typed arguments (with arbitrary offsets).	/// their pointer-typed arguments (with arbitrary offsets).
	///	///
	static bool onlyAccessesArgPointees(ModRefBehavior MRB) {	static bool onlyAccessesArgPointees(ModRefBehavior MRB) {
	return !(MRB & Anywhere & ~ArgumentPointees);	return !(MRB & Anywhere & ~ArgumentPointees);
	}	}

	/// doesAccessArgPointees - Return true if functions with the specified	/// doesAccessArgPointees - Return true if functions with the specified

	/// behavior are known to potentially read or write from objects pointed	/// behavior are known to potentially read or write from objects pointed
	/// to be their pointer-typed arguments (with arbitrary offsets).	/// to be their pointer-typed arguments (with arbitrary offsets).
	///	///
	static bool doesAccessArgPointees(ModRefBehavior MRB) {	static bool doesAccessArgPointees(ModRefBehavior MRB) {
	return (MRB & ModRef) && (MRB & ArgumentPointees);	return (MRB & ModRef) && (MRB & ArgumentPointees);
	}	}

	/// getModRefInfo - Return information about whether or not an instructio n may	/// getModRefInfo - Return information about whether or not an instructio n may
	/// read or write the specified memory location. An instruction	/// read or write the specified memory location. An instruction
	/// that doesn't read or write memory may be trivially LICM'd for example .	/// that doesn't read or write memory may be trivially LICM'd for example .
	ModRefResult getModRefInfo(const Instruction *I,	ModRefResult getModRefInfo(const Instruction *I,

	skipping to change at line 571	skipping to change at line 571

	/// isIdentifiedObject - Return true if this pointer refers to a distinct a nd	/// isIdentifiedObject - Return true if this pointer refers to a distinct a nd
	/// identifiable object. This returns true for:	/// identifiable object. This returns true for:
	/// Global Variables and Functions (but not Global Aliases)	/// Global Variables and Functions (but not Global Aliases)
	/// Allocas and Mallocs	/// Allocas and Mallocs
	/// ByVal and NoAlias Arguments	/// ByVal and NoAlias Arguments
	/// NoAlias returns	/// NoAlias returns
	///	///
	bool isIdentifiedObject(const Value *V);	bool isIdentifiedObject(const Value *V);


		/// isKnownNonNull - Return true if this pointer couldn't possibly be null
		by
		/// its definition. This returns true for allocas, non-extern-weak globals
		and
		/// byval arguments.
		bool isKnownNonNull(const Value *V);

	} // End llvm namespace	} // End llvm namespace

	#endif	#endif

End of changes. 2 change blocks.
	1 lines changed or deleted	8 lines changed or added

	AliasSetTracker.h	AliasSetTracker.h

	skipping to change at line 267	skipping to change at line 267
	void removeUnknownInst(Instruction *I) {	void removeUnknownInst(Instruction *I) {
	for (size_t i = 0, e = UnknownInsts.size(); i != e; ++i)	for (size_t i = 0, e = UnknownInsts.size(); i != e; ++i)
	if (UnknownInsts[i] == I) {	if (UnknownInsts[i] == I) {
	UnknownInsts[i] = UnknownInsts.back();	UnknownInsts[i] = UnknownInsts.back();
	UnknownInsts.pop_back();	UnknownInsts.pop_back();
	--i; --e; // Revisit the moved entry.	--i; --e; // Revisit the moved entry.
	}	}
	}	}
	void setVolatile() { Volatile = true; }	void setVolatile() { Volatile = true; }


		public:
	/// aliasesPointer - Return true if the specified pointer "may" (or must)	/// aliasesPointer - Return true if the specified pointer "may" (or must)
	/// alias one of the members in the set.	/// alias one of the members in the set.
	///	///
	bool aliasesPointer(const Value Ptr, uint64_t Size, const MDNode TBAAIn fo,	bool aliasesPointer(const Value Ptr, uint64_t Size, const MDNode TBAAIn fo,
	AliasAnalysis &AA) const;	AliasAnalysis &AA) const;
	bool aliasesUnknownInst(Instruction *Inst, AliasAnalysis &AA) const;	bool aliasesUnknownInst(Instruction *Inst, AliasAnalysis &AA) const;
	};	};

	inline raw_ostream& operator<<(raw_ostream &OS, const AliasSet &AS) {	inline raw_ostream& operator<<(raw_ostream &OS, const AliasSet &AS) {
	AS.print(OS);	AS.print(OS);

End of changes. 1 change blocks.
	0 lines changed or deleted	1 lines changed or added

	BasicBlock.h	BasicBlock.h

	skipping to change at line 113	skipping to change at line 113
	Function Parent = 0,BasicBlock InsertBefore = 0) {	Function Parent = 0,BasicBlock InsertBefore = 0) {
	return new BasicBlock(Context, Name, Parent, InsertBefore);	return new BasicBlock(Context, Name, Parent, InsertBefore);
	}	}
	~BasicBlock();	~BasicBlock();

	/// getParent - Return the enclosing method, or null if none	/// getParent - Return the enclosing method, or null if none
	///	///
	const Function *getParent() const { return Parent; }	const Function *getParent() const { return Parent; }
	Function *getParent() { return Parent; }	Function *getParent() { return Parent; }


	/// use_back - Specialize the methods defined in Value, as we know that a
	n
	/// BasicBlock can only be used by Users (specifically terminators
	/// and BlockAddress's).
	User use_back() { return cast<User>(use_begin());}
	const User use_back() const { return cast<User>(use_begin());}

	/// getTerminator() - If this is a well formed basic block, then this ret urns	/// getTerminator() - If this is a well formed basic block, then this ret urns
	/// a pointer to the terminator instruction. If it is not, then you get a	/// a pointer to the terminator instruction. If it is not, then you get a
	/// null pointer back.	/// null pointer back.
	///	///
	TerminatorInst *getTerminator();	TerminatorInst *getTerminator();
	const TerminatorInst *getTerminator() const;	const TerminatorInst *getTerminator() const;

	/// Returns a pointer to the first instructon in this block that is not a	/// Returns a pointer to the first instructon in this block that is not a
	/// PHINode instruction. When adding instruction to the beginning of the	/// PHINode instruction. When adding instruction to the beginning of the
	/// basic block, they should be added before the returned value, not befo re	/// basic block, they should be added before the returned value, not befo re

	skipping to change at line 276	skipping to change at line 270
	/// to refer to basic block New instead of to us.	/// to refer to basic block New instead of to us.
	void replaceSuccessorsPhiUsesWith(BasicBlock *New);	void replaceSuccessorsPhiUsesWith(BasicBlock *New);

	/// isLandingPad - Return true if this basic block is a landing pad. I.e. ,	/// isLandingPad - Return true if this basic block is a landing pad. I.e. ,
	/// it's the destination of the 'unwind' edge of an invoke instruction.	/// it's the destination of the 'unwind' edge of an invoke instruction.
	bool isLandingPad() const;	bool isLandingPad() const;

	/// getLandingPadInst() - Return the landingpad instruction associated wi th	/// getLandingPadInst() - Return the landingpad instruction associated wi th
	/// the landing pad.	/// the landing pad.
	LandingPadInst *getLandingPadInst();	LandingPadInst *getLandingPadInst();

		const LandingPadInst *getLandingPadInst() const;

	private:	private:
	/// AdjustBlockAddressRefCount - BasicBlock stores the number of BlockAdd ress	/// AdjustBlockAddressRefCount - BasicBlock stores the number of BlockAdd ress
	/// objects using it. This is almost always 0, sometimes one, possibly b ut	/// objects using it. This is almost always 0, sometimes one, possibly b ut
	/// almost never 2, and inconceivably 3 or more.	/// almost never 2, and inconceivably 3 or more.
	void AdjustBlockAddressRefCount(int Amt) {	void AdjustBlockAddressRefCount(int Amt) {
	setValueSubclassData(getSubclassDataFromValue()+Amt);	setValueSubclassData(getSubclassDataFromValue()+Amt);
	assert((int)(signed char)getSubclassDataFromValue() >= 0 &&	assert((int)(signed char)getSubclassDataFromValue() >= 0 &&
	"Refcount wrap-around");	"Refcount wrap-around");
	}	}

End of changes. 2 change blocks.
	7 lines changed or deleted	1 lines changed or added

	BasicBlockUtils.h	BasicBlockUtils.h

	skipping to change at line 111	skipping to change at line 111
	/// dest go to one block instead of each going to a different block, but is n't	/// dest go to one block instead of each going to a different block, but is n't
	/// the standard definition of a "critical edge".	/// the standard definition of a "critical edge".
	///	///
	/// It is invalid to call this function on a critical edge that starts at a n	/// It is invalid to call this function on a critical edge that starts at a n
	/// IndirectBrInst. Splitting these edges will almost always create an inv alid	/// IndirectBrInst. Splitting these edges will almost always create an inv alid
	/// program because the address of the new block won't be the one that is j umped	/// program because the address of the new block won't be the one that is j umped
	/// to.	/// to.
	///	///
	BasicBlock SplitCriticalEdge(TerminatorInst TI, unsigned SuccNum,	BasicBlock SplitCriticalEdge(TerminatorInst TI, unsigned SuccNum,
	Pass *P = 0, bool MergeIdenticalEdges = false ,	Pass *P = 0, bool MergeIdenticalEdges = false ,

	bool DontDeleteUselessPHIs = false);	bool DontDeleteUselessPHIs = false,
		bool SplitLandingPads = false);

	inline BasicBlock SplitCriticalEdge(BasicBlock BB, succ_iterator SI,	inline BasicBlock SplitCriticalEdge(BasicBlock BB, succ_iterator SI,
	Pass *P = 0) {	Pass *P = 0) {
	return SplitCriticalEdge(BB->getTerminator(), SI.getSuccessorIndex(), P);	return SplitCriticalEdge(BB->getTerminator(), SI.getSuccessorIndex(), P);
	}	}

	/// SplitCriticalEdge - If the edge from *PI to BB is not critical, return	/// SplitCriticalEdge - If the edge from *PI to BB is not critical, return
	/// false. Otherwise, split all edges between the two blocks and return tr ue.	/// false. Otherwise, split all edges between the two blocks and return tr ue.
	/// This updates all of the same analyses as the other SplitCriticalEdge	/// This updates all of the same analyses as the other SplitCriticalEdge
	/// function. If P is specified, it updates the analyses	/// function. If P is specified, it updates the analyses

	skipping to change at line 174	skipping to change at line 175
	/// be predecessors of the new block. The new predecessors are indicated b y the	/// be predecessors of the new block. The new predecessors are indicated b y the
	/// Preds array, which has NumPreds elements in it. The new block is given a	/// Preds array, which has NumPreds elements in it. The new block is given a
	/// suffix of 'Suffix'. This function returns the new block.	/// suffix of 'Suffix'. This function returns the new block.
	///	///
	/// This currently updates the LLVM IR, AliasAnalysis, DominatorTree,	/// This currently updates the LLVM IR, AliasAnalysis, DominatorTree,
	/// DominanceFrontier, LoopInfo, and LCCSA but no other analyses.	/// DominanceFrontier, LoopInfo, and LCCSA but no other analyses.
	/// In particular, it does not preserve LoopSimplify (because it's	/// In particular, it does not preserve LoopSimplify (because it's
	/// complicated to handle the case where one of the edges being split	/// complicated to handle the case where one of the edges being split
	/// is an exit of a loop with other exits).	/// is an exit of a loop with other exits).
	///	///

	BasicBlock SplitBlockPredecessors(BasicBlock BB, BasicBlock const Preds	BasicBlock SplitBlockPredecessors(BasicBlock BB, ArrayRef<BasicBlock*> Pr
	,	eds,
	unsigned NumPreds, const char *Suffix,	const char Suffix, Pass P = 0);
	Pass *P = 0);

	/// SplitLandingPadPredecessors - This method transforms the landing pad,	/// SplitLandingPadPredecessors - This method transforms the landing pad,
	/// OrigBB, by introducing two new basic blocks into the function. One of t hose	/// OrigBB, by introducing two new basic blocks into the function. One of t hose
	/// new basic blocks gets the predecessors listed in Preds. The other basic	/// new basic blocks gets the predecessors listed in Preds. The other basic
	/// block gets the remaining predecessors of OrigBB. The landingpad instruc tion	/// block gets the remaining predecessors of OrigBB. The landingpad instruc tion
	/// OrigBB is clone into both of the new basic blocks. The new blocks are g iven	/// OrigBB is clone into both of the new basic blocks. The new blocks are g iven
	/// the suffixes 'Suffix1' and 'Suffix2', and are returned in the NewBBs ve ctor.	/// the suffixes 'Suffix1' and 'Suffix2', and are returned in the NewBBs ve ctor.
	///	///
	/// This currently updates the LLVM IR, AliasAnalysis, DominatorTree,	/// This currently updates the LLVM IR, AliasAnalysis, DominatorTree,
	/// DominanceFrontier, LoopInfo, and LCCSA but no other analyses. In partic ular,	/// DominanceFrontier, LoopInfo, and LCCSA but no other analyses. In partic ular,

End of changes. 2 change blocks.
	5 lines changed or deleted	5 lines changed or added

	CFG.h	CFG.h

	skipping to change at line 74	skipping to change at line 74

	inline Self operator++(int) { // Postincrement	inline Self operator++(int) { // Postincrement
	Self tmp = this; ++this; return tmp;	Self tmp = this; ++this; return tmp;
	}	}

	/// getOperandNo - Return the operand number in the predecessor's	/// getOperandNo - Return the operand number in the predecessor's
	/// terminator of the successor.	/// terminator of the successor.
	unsigned getOperandNo() const {	unsigned getOperandNo() const {
	return It.getOperandNo();	return It.getOperandNo();
	}	}


		/// getUse - Return the operand Use in the predecessor's terminator
		/// of the successor.
		Use &getUse() const {
		return It.getUse();
		}
	};	};

	typedef PredIterator<BasicBlock, Value::use_iterator> pred_iterator;	typedef PredIterator<BasicBlock, Value::use_iterator> pred_iterator;
	typedef PredIterator<const BasicBlock,	typedef PredIterator<const BasicBlock,
	Value::const_use_iterator> const_pred_iterator;	Value::const_use_iterator> const_pred_iterator;

	inline pred_iterator pred_begin(BasicBlock *BB) { return pred_iterator(BB); }	inline pred_iterator pred_begin(BasicBlock *BB) { return pred_iterator(BB); }
	inline const_pred_iterator pred_begin(const BasicBlock *BB) {	inline const_pred_iterator pred_begin(const BasicBlock *BB) {
	return const_pred_iterator(BB);	return const_pred_iterator(BB);
	}	}

	skipping to change at line 311	skipping to change at line 317
	// graph of basic blocks... these are the same as the basic block iterators ,	// graph of basic blocks... these are the same as the basic block iterators ,
	// except that the root node is implicitly the first node of the function.	// except that the root node is implicitly the first node of the function.
	//	//
	template <> struct GraphTraits<Function> : public GraphTraits<BasicBlock> {	template <> struct GraphTraits<Function> : public GraphTraits<BasicBlock> {
	static NodeType getEntryNode(Function F) { return &F->getEntryBlock(); }	static NodeType getEntryNode(Function F) { return &F->getEntryBlock(); }

	// nodes_iterator/begin/end - Allow iteration over all nodes in the graph	// nodes_iterator/begin/end - Allow iteration over all nodes in the graph
	typedef Function::iterator nodes_iterator;	typedef Function::iterator nodes_iterator;
	static nodes_iterator nodes_begin(Function *F) { return F->begin(); }	static nodes_iterator nodes_begin(Function *F) { return F->begin(); }
	static nodes_iterator nodes_end (Function *F) { return F->end(); }	static nodes_iterator nodes_end (Function *F) { return F->end(); }

		static unsigned size (Function *F) { return F->size(); }
	};	};
	template <> struct GraphTraits<const Function*> :	template <> struct GraphTraits<const Function*> :
	public GraphTraits<const BasicBlock*> {	public GraphTraits<const BasicBlock*> {
	static NodeType getEntryNode(const Function F) {return &F->getEntryBloc k();}	static NodeType getEntryNode(const Function F) {return &F->getEntryBloc k();}

	// nodes_iterator/begin/end - Allow iteration over all nodes in the graph	// nodes_iterator/begin/end - Allow iteration over all nodes in the graph
	typedef Function::const_iterator nodes_iterator;	typedef Function::const_iterator nodes_iterator;
	static nodes_iterator nodes_begin(const Function *F) { return F->begin(); }	static nodes_iterator nodes_begin(const Function *F) { return F->begin(); }
	static nodes_iterator nodes_end (const Function *F) { return F->end(); }	static nodes_iterator nodes_end (const Function *F) { return F->end(); }

		static unsigned size (const Function *F) { return F->size(); }
	};	};

	// Provide specializations of GraphTraits to be able to treat a function as a	// Provide specializations of GraphTraits to be able to treat a function as a
	// graph of basic blocks... and to walk it in inverse order. Inverse order for	// graph of basic blocks... and to walk it in inverse order. Inverse order for
	// a function is considered to be when traversing the predecessor edges of a BB	// a function is considered to be when traversing the predecessor edges of a BB
	// instead of the successor edges.	// instead of the successor edges.
	//	//
	template <> struct GraphTraits<Inverse<Function*> > :	template <> struct GraphTraits<Inverse<Function*> > :
	public GraphTraits<Inverse<BasicBlock*> > {	public GraphTraits<Inverse<BasicBlock*> > {
	static NodeType getEntryNode(Inverse<Function> G) {	static NodeType getEntryNode(Inverse<Function> G) {

End of changes. 3 change blocks.
	0 lines changed or deleted	8 lines changed or added

	Constant.h	Constant.h

	skipping to change at line 44	skipping to change at line 44
	///	///
	/// Note that Constants are immutable (once created they never change)	/// Note that Constants are immutable (once created they never change)
	/// and are fully shared by structural equivalence. This means that two	/// and are fully shared by structural equivalence. This means that two
	/// structurally equivalent constants will always have the same address.	/// structurally equivalent constants will always have the same address.
	/// Constants are created on demand as needed and never deleted: thus clien ts	/// Constants are created on demand as needed and never deleted: thus clien ts
	/// don't have to worry about the lifetime of the objects.	/// don't have to worry about the lifetime of the objects.
	/// @brief LLVM Constant Representation	/// @brief LLVM Constant Representation
	class Constant : public User {	class Constant : public User {
	void operator=(const Constant &); // Do not implement	void operator=(const Constant &); // Do not implement
	Constant(const Constant &); // Do not implement	Constant(const Constant &); // Do not implement

		virtual void anchor();

	protected:	protected:
	Constant(Type ty, ValueTy vty, Use Ops, unsigned NumOps)	Constant(Type ty, ValueTy vty, Use Ops, unsigned NumOps)
	: User(ty, vty, Ops, NumOps) {}	: User(ty, vty, Ops, NumOps) {}

	void destroyConstantImpl();	void destroyConstantImpl();
	public:	public:
	/// isNullValue - Return true if this is the value that would be returned by	/// isNullValue - Return true if this is the value that would be returned by
	/// getNullValue.	/// getNullValue.
	bool isNullValue() const;	bool isNullValue() const;

	skipping to change at line 93	skipping to change at line 94
	/// relocation applied to it (because it holds a simple constant like	/// relocation applied to it (because it holds a simple constant like
	/// '4').	/// '4').
	/// LocalRelocation: This entry has relocations, but the entries are	/// LocalRelocation: This entry has relocations, but the entries are
	/// guaranteed to be resolvable by the static linker, so the dynamic	/// guaranteed to be resolvable by the static linker, so the dynamic
	/// linker will never see them.	/// linker will never see them.
	/// GlobalRelocations: This entry may have arbitrary relocations.	/// GlobalRelocations: This entry may have arbitrary relocations.
	///	///
	/// FIXME: This really should not be in VMCore.	/// FIXME: This really should not be in VMCore.
	PossibleRelocationsTy getRelocationInfo() const;	PossibleRelocationsTy getRelocationInfo() const;


	/// getVectorElements - This method, which is only valid on constant of v	/// getAggregateElement - For aggregates (struct/array/vector) return the
	ector	/// constant that corresponds to the specified element if possible, or nu
	/// type, returns the elements of the vector in the specified smallvector	ll if
	.	/// not. This can return null if the element index is a ConstantExpr, or
	/// This handles breaking down a vector undef into undef elements, etc.	if
	For	/// 'this' is a constant expr.
	/// constant exprs and other cases we can't handle, we return an empty ve	Constant *getAggregateElement(unsigned Elt) const;
	ctor.	Constant getAggregateElement(Constant Elt) const;
	void getVectorElements(SmallVectorImpl<Constant*> &Elts) const;

	/// destroyConstant - Called if some element of this constant is no longe r	/// destroyConstant - Called if some element of this constant is no longe r
	/// valid. At this point only other constants may be on the use_list for this	/// valid. At this point only other constants may be on the use_list for this
	/// constant. Any constants on our Use list must also be destroy'd. The	/// constant. Any constants on our Use list must also be destroy'd. The
	/// implementation must be sure to remove the constant from the list of	/// implementation must be sure to remove the constant from the list of
	/// available cached constants. Implementations should call	/// available cached constants. Implementations should call
	/// destroyConstantImpl as the last thing they do, to destroy all users a nd	/// destroyConstantImpl as the last thing they do, to destroy all users a nd
	/// delete this.	/// delete this.

	virtual void destroyConstant() { assert(0 && "Not reached!"); }	virtual void destroyConstant() { llvm_unreachable("Not reached!"); }

	//// Methods for support type inquiry through isa, cast, and dyn_cast:	//// Methods for support type inquiry through isa, cast, and dyn_cast:
	static inline bool classof(const Constant *) { return true; }	static inline bool classof(const Constant *) { return true; }
	static inline bool classof(const GlobalValue *) { return true; }	static inline bool classof(const GlobalValue *) { return true; }
	static inline bool classof(const Value *V) {	static inline bool classof(const Value *V) {
	return V->getValueID() >= ConstantFirstVal &&	return V->getValueID() >= ConstantFirstVal &&
	V->getValueID() <= ConstantLastVal;	V->getValueID() <= ConstantLastVal;
	}	}

	/// replaceUsesOfWithOnConstant - This method is a special form of	/// replaceUsesOfWithOnConstant - This method is a special form of

	skipping to change at line 132	skipping to change at line 134
	/// 'this' is deleted. In general, you should not call this method, inst ead,	/// 'this' is deleted. In general, you should not call this method, inst ead,
	/// use Value::replaceAllUsesWith, which automatically dispatches to this	/// use Value::replaceAllUsesWith, which automatically dispatches to this
	/// method as needed.	/// method as needed.
	///	///
	virtual void replaceUsesOfWithOnConstant(Value , Value , Use *) {	virtual void replaceUsesOfWithOnConstant(Value , Value , Use *) {
	// Provide a default implementation for constants (like integers) that	// Provide a default implementation for constants (like integers) that
	// cannot use any other values. This cannot be called at runtime, but needs	// cannot use any other values. This cannot be called at runtime, but needs
	// to be here to avoid link errors.	// to be here to avoid link errors.
	assert(getNumOperands() == 0 && "replaceUsesOfWithOnConstant must be "	assert(getNumOperands() == 0 && "replaceUsesOfWithOnConstant must be "
	"implemented for all constants that have operands!");	"implemented for all constants that have operands!");

	assert(0 && "Constants that do not have operands cannot be using 'From'	llvm_unreachable("Constants that do not have operands cannot be using "
	!");	"'From'!");
	}	}

	static Constant getNullValue(Type Ty);	static Constant getNullValue(Type Ty);

	/// @returns the value for an integer constant of the given type that has all	/// @returns the value for an integer constant of the given type that has all
	/// its bits set to true.	/// its bits set to true.
	/// @brief Get the all ones value	/// @brief Get the all ones value
	static Constant getAllOnesValue(Type Ty);	static Constant getAllOnesValue(Type Ty);

	/// getIntegerValue - Return the value for an integer or pointer constant ,	/// getIntegerValue - Return the value for an integer or pointer constant ,

End of changes. 4 change blocks.
	12 lines changed or deleted	12 lines changed or added

	DenseMapInfo.h	DenseMapInfo.h

	skipping to change at line 62	skipping to change at line 62
	static inline char getEmptyKey() { return ~0; }	static inline char getEmptyKey() { return ~0; }
	static inline char getTombstoneKey() { return ~0 - 1; }	static inline char getTombstoneKey() { return ~0 - 1; }
	static unsigned getHashValue(const char& Val) { return Val * 37U; }	static unsigned getHashValue(const char& Val) { return Val * 37U; }
	static bool isEqual(const char &LHS, const char &RHS) {	static bool isEqual(const char &LHS, const char &RHS) {
	return LHS == RHS;	return LHS == RHS;
	}	}
	};	};

	// Provide DenseMapInfo for unsigned ints.	// Provide DenseMapInfo for unsigned ints.
	template<> struct DenseMapInfo<unsigned> {	template<> struct DenseMapInfo<unsigned> {

	static inline unsigned getEmptyKey() { return ~0; }	static inline unsigned getEmptyKey() { return ~0U; }
	static inline unsigned getTombstoneKey() { return ~0U - 1; }	static inline unsigned getTombstoneKey() { return ~0U - 1; }
	static unsigned getHashValue(const unsigned& Val) { return Val * 37U; }	static unsigned getHashValue(const unsigned& Val) { return Val * 37U; }
	static bool isEqual(const unsigned& LHS, const unsigned& RHS) {	static bool isEqual(const unsigned& LHS, const unsigned& RHS) {
	return LHS == RHS;	return LHS == RHS;
	}	}
	};	};

	// Provide DenseMapInfo for unsigned longs.	// Provide DenseMapInfo for unsigned longs.
	template<> struct DenseMapInfo<unsigned long> {	template<> struct DenseMapInfo<unsigned long> {
	static inline unsigned long getEmptyKey() { return ~0UL; }	static inline unsigned long getEmptyKey() { return ~0UL; }

End of changes. 1 change blocks.
	1 lines changed or deleted	1 lines changed or added

	DerivedTypes.h	DerivedTypes.h

	skipping to change at line 195	skipping to change at line 195
	///	///
	class StructType : public CompositeType {	class StructType : public CompositeType {
	StructType(const StructType &); // Do not implement	StructType(const StructType &); // Do not implement
	const StructType &operator=(const StructType &); // Do not implement	const StructType &operator=(const StructType &); // Do not implement
	StructType(LLVMContext &C)	StructType(LLVMContext &C)
	: CompositeType(C, StructTyID), SymbolTableEntry(0) {}	: CompositeType(C, StructTyID), SymbolTableEntry(0) {}
	enum {	enum {
	// This is the contents of the SubClassData field.	// This is the contents of the SubClassData field.
	SCDB_HasBody = 1,	SCDB_HasBody = 1,
	SCDB_Packed = 2,	SCDB_Packed = 2,

	SCDB_IsLiteral = 4	SCDB_IsLiteral = 4,
		SCDB_IsSized = 8
	};	};

	/// SymbolTableEntry - For a named struct that actually has a name, this is a	/// SymbolTableEntry - For a named struct that actually has a name, this is a
	/// pointer to the symbol table entry (maintained by LLVMContext) for the	/// pointer to the symbol table entry (maintained by LLVMContext) for the
	/// struct. This is null if the type is an literal struct or if it is	/// struct. This is null if the type is an literal struct or if it is
	/// a identified type that has an empty name.	/// a identified type that has an empty name.
	///	///
	void *SymbolTableEntry;	void *SymbolTableEntry;
	public:	public:
	~StructType() {	~StructType() {

	skipping to change at line 249	skipping to change at line 250
	bool isPacked() const { return (getSubclassData() & SCDB_Packed) != 0; }	bool isPacked() const { return (getSubclassData() & SCDB_Packed) != 0; }

	/// isLiteral - Return true if this type is uniqued by structural	/// isLiteral - Return true if this type is uniqued by structural
	/// equivalence, false if it is a struct definition.	/// equivalence, false if it is a struct definition.
	bool isLiteral() const { return (getSubclassData() & SCDB_IsLiteral) != 0 ; }	bool isLiteral() const { return (getSubclassData() & SCDB_IsLiteral) != 0 ; }

	/// isOpaque - Return true if this is a type with an identity that has no body	/// isOpaque - Return true if this is a type with an identity that has no body
	/// specified yet. These prints as 'opaque' in .ll files.	/// specified yet. These prints as 'opaque' in .ll files.
	bool isOpaque() const { return (getSubclassData() & SCDB_HasBody) == 0; }	bool isOpaque() const { return (getSubclassData() & SCDB_HasBody) == 0; }


		/// isSized - Return true if this is a sized type.
		bool isSized() const;

	/// hasName - Return true if this is a named struct that has a non-empty name.	/// hasName - Return true if this is a named struct that has a non-empty name.
	bool hasName() const { return SymbolTableEntry != 0; }	bool hasName() const { return SymbolTableEntry != 0; }

	/// getName - Return the name for this struct type if it has an identity.	/// getName - Return the name for this struct type if it has an identity.
	/// This may return an empty string for an unnamed struct type. Do not c all	/// This may return an empty string for an unnamed struct type. Do not c all
	/// this on an literal type.	/// this on an literal type.
	StringRef getName() const;	StringRef getName() const;

	/// setName - Change the name of this type to the specified name, or to a name	/// setName - Change the name of this type to the specified name, or to a name
	/// with a suffix if there is a collision. Do not call this on an litera l	/// with a suffix if there is a collision. Do not call this on an litera l

	skipping to change at line 372	skipping to change at line 376
	/// VectorType.	/// VectorType.
	///	///
	static VectorType get(Type ElementType, unsigned NumElements);	static VectorType get(Type ElementType, unsigned NumElements);

	/// VectorType::getInteger - This static method gets a VectorType with th e	/// VectorType::getInteger - This static method gets a VectorType with th e
	/// same number of elements as the input type, and the element type is an	/// same number of elements as the input type, and the element type is an
	/// integer type of the same width as the input element type.	/// integer type of the same width as the input element type.
	///	///
	static VectorType getInteger(VectorType VTy) {	static VectorType getInteger(VectorType VTy) {
	unsigned EltBits = VTy->getElementType()->getPrimitiveSizeInBits();	unsigned EltBits = VTy->getElementType()->getPrimitiveSizeInBits();

		assert(EltBits && "Element size must be of a non-zero size");
	Type *EltTy = IntegerType::get(VTy->getContext(), EltBits);	Type *EltTy = IntegerType::get(VTy->getContext(), EltBits);
	return VectorType::get(EltTy, VTy->getNumElements());	return VectorType::get(EltTy, VTy->getNumElements());
	}	}

	/// VectorType::getExtendedElementVectorType - This static method is like	/// VectorType::getExtendedElementVectorType - This static method is like
	/// getInteger except that the element types are twice as wide as the	/// getInteger except that the element types are twice as wide as the
	/// elements in the input type.	/// elements in the input type.
	///	///
	static VectorType getExtendedElementVectorType(VectorType VTy) {	static VectorType getExtendedElementVectorType(VectorType VTy) {
	unsigned EltBits = VTy->getElementType()->getPrimitiveSizeInBits();	unsigned EltBits = VTy->getElementType()->getPrimitiveSizeInBits();

	skipping to change at line 406	skipping to change at line 411
	}	}

	/// isValidElementType - Return true if the specified type is valid as a	/// isValidElementType - Return true if the specified type is valid as a
	/// element type.	/// element type.
	static bool isValidElementType(Type *ElemTy);	static bool isValidElementType(Type *ElemTy);

	/// @brief Return the number of elements in the Vector type.	/// @brief Return the number of elements in the Vector type.
	unsigned getNumElements() const { return NumElements; }	unsigned getNumElements() const { return NumElements; }

	/// @brief Return the number of bits in the Vector type.	/// @brief Return the number of bits in the Vector type.

		/// Returns zero when the vector is a vector of pointers.
	unsigned getBitWidth() const {	unsigned getBitWidth() const {
	return NumElements * getElementType()->getPrimitiveSizeInBits();	return NumElements * getElementType()->getPrimitiveSizeInBits();
	}	}

	// Methods for support type inquiry through isa, cast, and dyn_cast.	// Methods for support type inquiry through isa, cast, and dyn_cast.
	static inline bool classof(const VectorType *) { return true; }	static inline bool classof(const VectorType *) { return true; }
	static inline bool classof(const Type *T) {	static inline bool classof(const Type *T) {
	return T->getTypeID() == VectorTyID;	return T->getTypeID() == VectorTyID;
	}	}
	};	};

End of changes. 4 change blocks.
	1 lines changed or deleted	7 lines changed or added

	Disassemblers.def	Disassemblers.def

	skipping to change at line 12	skipping to change at line 12
	//	//
	// The LLVM Compiler Infrastructure	// The LLVM Compiler Infrastructure
	//	//
	// This file is distributed under the University of Illinois Open Source	// This file is distributed under the University of Illinois Open Source
	// License. See LICENSE.TXT for details.	// License. See LICENSE.TXT for details.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	//	//
	// This file enumerates all of the assembly-language parsers	// This file enumerates all of the assembly-language parsers
	// supported by this build of LLVM. Clients of this file should define	// supported by this build of LLVM. Clients of this file should define

	// the LLVM_ASM_PARSER macro to be a function-like macro with a	// the LLVM_DISASSEMBLER macro to be a function-like macro with a
	// single parameter (the name of the target whose assembly can be	// single parameter (the name of the target whose assembly can be
	// generated); including this file will then enumerate all of the	// generated); including this file will then enumerate all of the
	// targets with assembly parsers.	// targets with assembly parsers.
	//	//
	// The set of targets supported by LLVM is generated at configuration	// The set of targets supported by LLVM is generated at configuration
	// time, at which point this header is generated. Do not modify this	// time, at which point this header is generated. Do not modify this
	// header directly.	// header directly.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_DISASSEMBLER	#ifndef LLVM_DISASSEMBLER
	# error Please define the macro LLVM_DISASSEMBLER(TargetName)	# error Please define the macro LLVM_DISASSEMBLER(TargetName)
	#endif	#endif


	LLVM_DISASSEMBLER(MBlaze) LLVM_DISASSEMBLER(ARM) LLVM_DISASSEMBLER(X86)	LLVM_DISASSEMBLER(MBlaze) LLVM_DISASSEMBLER(Mips) LLVM_DISASSEMBLER(ARM) LL VM_DISASSEMBLER(X86)

	#undef LLVM_DISASSEMBLER	#undef LLVM_DISASSEMBLER

End of changes. 2 change blocks.
	2 lines changed or deleted	2 lines changed or added

	DominatorInternals.h	DominatorInternals.h

	skipping to change at line 174	skipping to change at line 174
	}	}

	// Step #1: Number blocks in depth-first order and initialize variables u sed	// Step #1: Number blocks in depth-first order and initialize variables u sed
	// in later stages of the algorithm.	// in later stages of the algorithm.
	for (unsigned i = 0, e = static_cast<unsigned>(DT.Roots.size());	for (unsigned i = 0, e = static_cast<unsigned>(DT.Roots.size());
	i != e; ++i)	i != e; ++i)
	N = DFSPass<GraphT>(DT, DT.Roots[i], N);	N = DFSPass<GraphT>(DT, DT.Roots[i], N);

	// it might be that some blocks did not get a DFS number (e.g., blocks of	// it might be that some blocks did not get a DFS number (e.g., blocks of
	// infinite loops). In these cases an artificial exit node is required.	// infinite loops). In these cases an artificial exit node is required.

	MultipleRoots \|= (DT.isPostDominator() && N != F.size());	MultipleRoots \|= (DT.isPostDominator() && N != GraphTraits<FuncT*>::size( &F));

	// When naively implemented, the Lengauer-Tarjan algorithm requires a sep arate	// When naively implemented, the Lengauer-Tarjan algorithm requires a sep arate
	// bucket for each vertex. However, this is unnecessary, because each ver tex	// bucket for each vertex. However, this is unnecessary, because each ver tex
	// is only placed into a single bucket (that of its semidominator), and e ach	// is only placed into a single bucket (that of its semidominator), and e ach
	// vertex's bucket is processed before it is added to any bucket itself.	// vertex's bucket is processed before it is added to any bucket itself.
	//	//
	// Instead of using a bucket per vertex, we use a single array Buckets th at	// Instead of using a bucket per vertex, we use a single array Buckets th at
	// has two purposes. Before the vertex V with preorder number i is proces sed,	// has two purposes. Before the vertex V with preorder number i is proces sed,
	// Buckets[i] stores the index of the first element in V's bucket. After V's	// Buckets[i] stores the index of the first element in V's bucket. After V's
	// bucket is processed, Buckets[i] stores the index of the next element i n the	// bucket is processed, Buckets[i] stores the index of the next element i n the

End of changes. 1 change blocks.
	1 lines changed or deleted	1 lines changed or added

	DynamicLibrary.h	DynamicLibrary.h

	skipping to change at line 20	skipping to change at line 20
	// This file declares the sys::DynamicLibrary class.	// This file declares the sys::DynamicLibrary class.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_SYSTEM_DYNAMIC_LIBRARY_H	#ifndef LLVM_SYSTEM_DYNAMIC_LIBRARY_H
	#define LLVM_SYSTEM_DYNAMIC_LIBRARY_H	#define LLVM_SYSTEM_DYNAMIC_LIBRARY_H

	#include <string>	#include <string>

	namespace llvm {	namespace llvm {


		class StringRef;

	namespace sys {	namespace sys {

	/// This class provides a portable interface to dynamic libraries which a lso	/// This class provides a portable interface to dynamic libraries which a lso
	/// might be known as shared libraries, shared objects, dynamic shared	/// might be known as shared libraries, shared objects, dynamic shared
	/// objects, or dynamic link libraries. Regardless of the terminology or the	/// objects, or dynamic link libraries. Regardless of the terminology or the
	/// operating system interface, this class provides a portable interface that	/// operating system interface, this class provides a portable interface that
	/// allows dynamic libraries to be loaded and searched for externally	/// allows dynamic libraries to be loaded and searched for externally
	/// defined symbols. This is typically used to provide "plug-in" support.	/// defined symbols. This is typically used to provide "plug-in" support.
	/// It also allows for symbols to be defined which don't live in any libr ary,	/// It also allows for symbols to be defined which don't live in any libr ary,
	/// but rather the main program itself, useful on Windows where the main	/// but rather the main program itself, useful on Windows where the main

End of changes. 1 change blocks.
	0 lines changed or deleted	3 lines changed or added

	FoldingSet.h	FoldingSet.h

	skipping to change at line 196	skipping to change at line 196
	///	///
	void GrowHashTable();	void GrowHashTable();

	protected:	protected:

	/// GetNodeProfile - Instantiations of the FoldingSet template implement	/// GetNodeProfile - Instantiations of the FoldingSet template implement
	/// this function to gather data bits for the given node.	/// this function to gather data bits for the given node.
	virtual void GetNodeProfile(Node *N, FoldingSetNodeID &ID) const = 0;	virtual void GetNodeProfile(Node *N, FoldingSetNodeID &ID) const = 0;
	/// NodeEquals - Instantiations of the FoldingSet template implement	/// NodeEquals - Instantiations of the FoldingSet template implement
	/// this function to compare the given node with the given ID.	/// this function to compare the given node with the given ID.

	virtual bool NodeEquals(Node *N, const FoldingSetNodeID &ID,	virtual bool NodeEquals(Node *N, const FoldingSetNodeID &ID, unsigned IDH ash,
	FoldingSetNodeID &TempID) const=0;	FoldingSetNodeID &TempID) const=0;

	/// NodeEquals - Instantiations of the FoldingSet template implement	/// ComputeNodeHash - Instantiations of the FoldingSet template implement
	/// this function to compute a hash value for the given node.	/// this function to compute a hash value for the given node.

	virtual unsigned ComputeNodeHash(Node *N,	virtual unsigned ComputeNodeHash(Node *N, FoldingSetNodeID &TempID) const
	FoldingSetNodeID &TempID) const = 0;	= 0;
	};	};

	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	template<typename T> struct FoldingSetTrait;	template<typename T> struct FoldingSetTrait;

	/// DefaultFoldingSetTrait - This class provides default implementations	/// DefaultFoldingSetTrait - This class provides default implementations
	/// for FoldingSetTrait implementations.	/// for FoldingSetTrait implementations.
	///	///
	template<typename T> struct DefaultFoldingSetTrait {	template<typename T> struct DefaultFoldingSetTrait {

	skipping to change at line 223	skipping to change at line 222
	X.Profile(ID);	X.Profile(ID);
	}	}
	static void Profile(T &X, FoldingSetNodeID &ID) {	static void Profile(T &X, FoldingSetNodeID &ID) {
	X.Profile(ID);	X.Profile(ID);
	}	}

	// Equals - Test if the profile for X would match ID, using TempID	// Equals - Test if the profile for X would match ID, using TempID
	// to compute a temporary ID if necessary. The default implementation	// to compute a temporary ID if necessary. The default implementation
	// just calls Profile and does a regular comparison. Implementations	// just calls Profile and does a regular comparison. Implementations
	// can override this to provide more efficient implementations.	// can override this to provide more efficient implementations.

	static inline bool Equals(T &X, const FoldingSetNodeID &ID,	static inline bool Equals(T &X, const FoldingSetNodeID &ID, unsigned IDHa sh,
	FoldingSetNodeID &TempID);	FoldingSetNodeID &TempID);

	// ComputeHash - Compute a hash value for X, using TempID to	// ComputeHash - Compute a hash value for X, using TempID to
	// compute a temporary ID if necessary. The default implementation	// compute a temporary ID if necessary. The default implementation
	// just calls Profile and does a regular hash computation.	// just calls Profile and does a regular hash computation.
	// Implementations can override this to provide more efficient	// Implementations can override this to provide more efficient
	// implementations.	// implementations.
	static inline unsigned ComputeHash(T &X, FoldingSetNodeID &TempID);	static inline unsigned ComputeHash(T &X, FoldingSetNodeID &TempID);
	};	};


	skipping to change at line 252	skipping to change at line 251

	template<typename T, typename Ctx> struct ContextualFoldingSetTrait;	template<typename T, typename Ctx> struct ContextualFoldingSetTrait;

	/// DefaultContextualFoldingSetTrait - Like DefaultFoldingSetTrait, but	/// DefaultContextualFoldingSetTrait - Like DefaultFoldingSetTrait, but
	/// for ContextualFoldingSets.	/// for ContextualFoldingSets.
	template<typename T, typename Ctx>	template<typename T, typename Ctx>
	struct DefaultContextualFoldingSetTrait {	struct DefaultContextualFoldingSetTrait {
	static void Profile(T &X, FoldingSetNodeID &ID, Ctx Context) {	static void Profile(T &X, FoldingSetNodeID &ID, Ctx Context) {
	X.Profile(ID, Context);	X.Profile(ID, Context);
	}	}

	static inline bool Equals(T &X, const FoldingSetNodeID &ID,	static inline bool Equals(T &X, const FoldingSetNodeID &ID, unsigned IDHa sh,
	FoldingSetNodeID &TempID, Ctx Context);	FoldingSetNodeID &TempID, Ctx Context);
	static inline unsigned ComputeHash(T &X, FoldingSetNodeID &TempID,	static inline unsigned ComputeHash(T &X, FoldingSetNodeID &TempID,
	Ctx Context);	Ctx Context);
	};	};

	/// ContextualFoldingSetTrait - Like FoldingSetTrait, but for	/// ContextualFoldingSetTrait - Like FoldingSetTrait, but for
	/// ContextualFoldingSets.	/// ContextualFoldingSets.
	template<typename T, typename Ctx> struct ContextualFoldingSetTrait	template<typename T, typename Ctx> struct ContextualFoldingSetTrait
	: public DefaultContextualFoldingSetTrait<T, Ctx> {};	: public DefaultContextualFoldingSetTrait<T, Ctx> {};


	skipping to change at line 347	skipping to change at line 346
	// Convenience type to hide the implementation of the folding set.	// Convenience type to hide the implementation of the folding set.
	typedef FoldingSetImpl::Node FoldingSetNode;	typedef FoldingSetImpl::Node FoldingSetNode;
	template<class T> class FoldingSetIterator;	template<class T> class FoldingSetIterator;
	template<class T> class FoldingSetBucketIterator;	template<class T> class FoldingSetBucketIterator;

	// Definitions of FoldingSetTrait and ContextualFoldingSetTrait functions, which	// Definitions of FoldingSetTrait and ContextualFoldingSetTrait functions, which
	// require the definition of FoldingSetNodeID.	// require the definition of FoldingSetNodeID.
	template<typename T>	template<typename T>
	inline bool	inline bool
	DefaultFoldingSetTrait<T>::Equals(T &X, const FoldingSetNodeID &ID,	DefaultFoldingSetTrait<T>::Equals(T &X, const FoldingSetNodeID &ID,

	FoldingSetNodeID &TempID) {	unsigned IDHash, FoldingSetNodeID &TempID ) {
	FoldingSetTrait<T>::Profile(X, TempID);	FoldingSetTrait<T>::Profile(X, TempID);
	return TempID == ID;	return TempID == ID;
	}	}
	template<typename T>	template<typename T>
	inline unsigned	inline unsigned
	DefaultFoldingSetTrait<T>::ComputeHash(T &X, FoldingSetNodeID &TempID) {	DefaultFoldingSetTrait<T>::ComputeHash(T &X, FoldingSetNodeID &TempID) {
	FoldingSetTrait<T>::Profile(X, TempID);	FoldingSetTrait<T>::Profile(X, TempID);
	return TempID.ComputeHash();	return TempID.ComputeHash();
	}	}
	template<typename T, typename Ctx>	template<typename T, typename Ctx>
	inline bool	inline bool
	DefaultContextualFoldingSetTrait<T, Ctx>::Equals(T &X,	DefaultContextualFoldingSetTrait<T, Ctx>::Equals(T &X,
	const FoldingSetNodeID &ID ,	const FoldingSetNodeID &ID ,

		unsigned IDHash,
	FoldingSetNodeID &TempID,	FoldingSetNodeID &TempID,
	Ctx Context) {	Ctx Context) {
	ContextualFoldingSetTrait<T, Ctx>::Profile(X, TempID, Context);	ContextualFoldingSetTrait<T, Ctx>::Profile(X, TempID, Context);
	return TempID == ID;	return TempID == ID;
	}	}
	template<typename T, typename Ctx>	template<typename T, typename Ctx>
	inline unsigned	inline unsigned
	DefaultContextualFoldingSetTrait<T, Ctx>::ComputeHash(T &X,	DefaultContextualFoldingSetTrait<T, Ctx>::ComputeHash(T &X,
	FoldingSetNodeID &Tem pID,	FoldingSetNodeID &Tem pID,
	Ctx Context) {	Ctx Context) {

	skipping to change at line 390	skipping to change at line 390
	template<class T> class FoldingSet : public FoldingSetImpl {	template<class T> class FoldingSet : public FoldingSetImpl {
	private:	private:
	/// GetNodeProfile - Each instantiatation of the FoldingSet needs to prov ide a	/// GetNodeProfile - Each instantiatation of the FoldingSet needs to prov ide a
	/// way to convert nodes into a unique specifier.	/// way to convert nodes into a unique specifier.
	virtual void GetNodeProfile(Node *N, FoldingSetNodeID &ID) const {	virtual void GetNodeProfile(Node *N, FoldingSetNodeID &ID) const {
	T TN = static_cast<T >(N);	T TN = static_cast<T >(N);
	FoldingSetTrait<T>::Profile(*TN, ID);	FoldingSetTrait<T>::Profile(*TN, ID);
	}	}
	/// NodeEquals - Instantiations may optionally provide a way to compare a	/// NodeEquals - Instantiations may optionally provide a way to compare a
	/// node with a specified ID.	/// node with a specified ID.

	virtual bool NodeEquals(Node *N, const FoldingSetNodeID &ID,	virtual bool NodeEquals(Node *N, const FoldingSetNodeID &ID, unsigned IDH ash,
	FoldingSetNodeID &TempID) const {	FoldingSetNodeID &TempID) const {
	T TN = static_cast<T >(N);	T TN = static_cast<T >(N);

	return FoldingSetTrait<T>::Equals(*TN, ID, TempID);	return FoldingSetTrait<T>::Equals(*TN, ID, IDHash, TempID);
	}	}

	/// NodeEquals - Instantiations may optionally provide a way to compute a	/// ComputeNodeHash - Instantiations may optionally provide a way to comp ute a
	/// hash value directly from a node.	/// hash value directly from a node.

	virtual unsigned ComputeNodeHash(Node *N,	virtual unsigned ComputeNodeHash(Node *N, FoldingSetNodeID &TempID) const
	FoldingSetNodeID &TempID) const {	{
	T TN = static_cast<T >(N);	T TN = static_cast<T >(N);
	return FoldingSetTrait<T>::ComputeHash(*TN, TempID);	return FoldingSetTrait<T>::ComputeHash(*TN, TempID);
	}	}

	public:	public:
	explicit FoldingSet(unsigned Log2InitSize = 6)	explicit FoldingSet(unsigned Log2InitSize = 6)
	: FoldingSetImpl(Log2InitSize)	: FoldingSetImpl(Log2InitSize)
	{}	{}

	typedef FoldingSetIterator<T> iterator;	typedef FoldingSetIterator<T> iterator;

	skipping to change at line 468	skipping to change at line 467
	Ctx Context;	Ctx Context;

	/// GetNodeProfile - Each instantiatation of the FoldingSet needs to prov ide a	/// GetNodeProfile - Each instantiatation of the FoldingSet needs to prov ide a
	/// way to convert nodes into a unique specifier.	/// way to convert nodes into a unique specifier.
	virtual void GetNodeProfile(FoldingSetImpl::Node *N,	virtual void GetNodeProfile(FoldingSetImpl::Node *N,
	FoldingSetNodeID &ID) const {	FoldingSetNodeID &ID) const {
	T TN = static_cast<T >(N);	T TN = static_cast<T >(N);
	ContextualFoldingSetTrait<T, Ctx>::Profile(*TN, ID, Context);	ContextualFoldingSetTrait<T, Ctx>::Profile(*TN, ID, Context);
	}	}
	virtual bool NodeEquals(FoldingSetImpl::Node *N,	virtual bool NodeEquals(FoldingSetImpl::Node *N,

	const FoldingSetNodeID &ID,	const FoldingSetNodeID &ID, unsigned IDHash,
	FoldingSetNodeID &TempID) const {	FoldingSetNodeID &TempID) const {
	T TN = static_cast<T >(N);	T TN = static_cast<T >(N);

	return ContextualFoldingSetTrait<T, Ctx>::Equals(*TN, ID, TempID, Conte	return ContextualFoldingSetTrait<T, Ctx>::Equals(*TN, ID, IDHash, TempI
	xt);	D,
		Context);
	}	}
	virtual unsigned ComputeNodeHash(FoldingSetImpl::Node *N,	virtual unsigned ComputeNodeHash(FoldingSetImpl::Node *N,
	FoldingSetNodeID &TempID) const {	FoldingSetNodeID &TempID) const {
	T TN = static_cast<T >(N);	T TN = static_cast<T >(N);
	return ContextualFoldingSetTrait<T, Ctx>::ComputeHash(*TN, TempID, Cont ext);	return ContextualFoldingSetTrait<T, Ctx>::ComputeHash(*TN, TempID, Cont ext);
	}	}

	public:	public:
	explicit ContextualFoldingSet(Ctx Context, unsigned Log2InitSize = 6)	explicit ContextualFoldingSet(Ctx Context, unsigned Log2InitSize = 6)
	: FoldingSetImpl(Log2InitSize), Context(Context)	: FoldingSetImpl(Log2InitSize), Context(Context)

End of changes. 13 change blocks.
	15 lines changed or deleted	17 lines changed or added

	Function.h	Function.h

	skipping to change at line 149	skipping to change at line 149
	/// arguments.	/// arguments.
	bool isVarArg() const;	bool isVarArg() const;

	/// getIntrinsicID - This method returns the ID number of the specified	/// getIntrinsicID - This method returns the ID number of the specified
	/// function, or Intrinsic::not_intrinsic if the function is not an	/// function, or Intrinsic::not_intrinsic if the function is not an
	/// instrinsic, or if the pointer is null. This value is always defined to be	/// instrinsic, or if the pointer is null. This value is always defined to be
	/// zero to allow easy checking for whether a function is intrinsic or no t.	/// zero to allow easy checking for whether a function is intrinsic or no t.
	/// The particular intrinsic functions which correspond to this value are	/// The particular intrinsic functions which correspond to this value are
	/// defined in llvm/Intrinsics.h.	/// defined in llvm/Intrinsics.h.
	///	///

	unsigned getIntrinsicID() const LLVM_ATTRIBUTE_READONLY;	unsigned getIntrinsicID() const LLVM_READONLY;
	bool isIntrinsic() const { return getIntrinsicID() != 0; }	bool isIntrinsic() const { return getIntrinsicID() != 0; }

	/// getCallingConv()/setCallingConv(CC) - These method get and set the	/// getCallingConv()/setCallingConv(CC) - These method get and set the
	/// calling convention of this function. The enum values for the known	/// calling convention of this function. The enum values for the known
	/// calling conventions are defined in CallingConv.h.	/// calling conventions are defined in CallingConv.h.
	CallingConv::ID getCallingConv() const {	CallingConv::ID getCallingConv() const {
	return static_cast<CallingConv::ID>(getSubclassDataFromValue() >> 1);	return static_cast<CallingConv::ID>(getSubclassDataFromValue() >> 1);
	}	}
	void setCallingConv(CallingConv::ID CC) {	void setCallingConv(CallingConv::ID CC) {
	setValueSubclassData((getSubclassDataFromValue() & 1) \|	setValueSubclassData((getSubclassDataFromValue() & 1) \|

	skipping to change at line 426	skipping to change at line 426
	/// including any contained basic blocks.	/// including any contained basic blocks.
	///	///
	void dropAllReferences();	void dropAllReferences();

	/// hasAddressTaken - returns true if there are any uses of this function	/// hasAddressTaken - returns true if there are any uses of this function
	/// other than direct calls or invokes to it. Optionally passes back the	/// other than direct calls or invokes to it. Optionally passes back the
	/// offending user for diagnostic purposes.	/// offending user for diagnostic purposes.
	///	///
	bool hasAddressTaken(const User** = 0) const;	bool hasAddressTaken(const User** = 0) const;


		/// isDefTriviallyDead - Return true if it is trivially safe to remove
		/// this function definition from the module (because it isn't externally
		/// visible, does not have its address taken, and has no callers). To ma
		ke
		/// this more accurate, call removeDeadConstantUsers first.
		bool isDefTriviallyDead() const;

	/// callsFunctionThatReturnsTwice - Return true if the function has a cal l to	/// callsFunctionThatReturnsTwice - Return true if the function has a cal l to
	/// setjmp or other function that gcc recognizes as "returning twice".	/// setjmp or other function that gcc recognizes as "returning twice".
	bool callsFunctionThatReturnsTwice() const;	bool callsFunctionThatReturnsTwice() const;

	private:	private:
	// Shadow Value::setValueSubclassData with a private forwarding method so that	// Shadow Value::setValueSubclassData with a private forwarding method so that
	// subclasses cannot accidentally use it.	// subclasses cannot accidentally use it.
	void setValueSubclassData(unsigned short D) {	void setValueSubclassData(unsigned short D) {
	Value::setValueSubclassData(D);	Value::setValueSubclassData(D);
	}	}

End of changes. 2 change blocks.
	1 lines changed or deleted	8 lines changed or added

	GCStrategy.h	GCStrategy.h

	skipping to change at line 40	skipping to change at line 40
	//	//
	// This information can used to emit the metadata tables which are required by	// This information can used to emit the metadata tables which are required by
	// the target garbage collector runtime.	// the target garbage collector runtime.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_CODEGEN_GCSTRATEGY_H	#ifndef LLVM_CODEGEN_GCSTRATEGY_H
	#define LLVM_CODEGEN_GCSTRATEGY_H	#define LLVM_CODEGEN_GCSTRATEGY_H

	#include "llvm/CodeGen/GCMetadata.h"	#include "llvm/CodeGen/GCMetadata.h"

		#include "llvm/CodeGen/MachineFunction.h"
	#include "llvm/Support/Registry.h"	#include "llvm/Support/Registry.h"
	#include <string>	#include <string>

	namespace llvm {	namespace llvm {

	class GCStrategy;	class GCStrategy;

	/// The GC strategy registry uses all the defaults from Registry.	/// The GC strategy registry uses all the defaults from Registry.
	///	///
	typedef Registry<GCStrategy> GCRegistry;	typedef Registry<GCStrategy> GCRegistry;

	skipping to change at line 71	skipping to change at line 72
	const Module *M;	const Module *M;
	std::string Name;	std::string Name;

	list_type Functions;	list_type Functions;

	protected:	protected:
	unsigned NeededSafePoints; //< Bitmask of required safe points.	unsigned NeededSafePoints; //< Bitmask of required safe points.
	bool CustomReadBarriers; //< Default is to insert loads.	bool CustomReadBarriers; //< Default is to insert loads.
	bool CustomWriteBarriers; //< Default is to insert stores.	bool CustomWriteBarriers; //< Default is to insert stores.
	bool CustomRoots; //< Default is to pass through to backend.	bool CustomRoots; //< Default is to pass through to backend.

		bool CustomSafePoints; //< Default is to use NeededSafePoints
		// to find safe points.
	bool InitRoots; //< If set, roots are nulled during lowering .	bool InitRoots; //< If set, roots are nulled during lowering .
	bool UsesMetadata; //< If set, backend must emit metadata table s.	bool UsesMetadata; //< If set, backend must emit metadata table s.

	public:	public:
	GCStrategy();	GCStrategy();

	virtual ~GCStrategy();	virtual ~GCStrategy();

	/// getName - The name of the GC strategy, for debugging.	/// getName - The name of the GC strategy, for debugging.
	///	///
	const std::string &getName() const { return Name; }	const std::string &getName() const { return Name; }

	/// getModule - The module within which the GC strategy is operating.	/// getModule - The module within which the GC strategy is operating.
	///	///
	const Module &getModule() const { return *M; }	const Module &getModule() const { return *M; }

	/// needsSafePoitns - True if safe points of any kind are required. By	/// needsSafePoitns - True if safe points of any kind are required. By
	// default, none are recorded.	// default, none are recorded.

	bool needsSafePoints() const { return NeededSafePoints != 0; }	bool needsSafePoints() const {
		return CustomSafePoints \|\| NeededSafePoints != 0;
		}

	/// needsSafePoint(Kind) - True if the given kind of safe point is	/// needsSafePoint(Kind) - True if the given kind of safe point is
	// required. By default, none are recorded.	// required. By default, none are recorded.
	bool needsSafePoint(GC::PointKind Kind) const {	bool needsSafePoint(GC::PointKind Kind) const {
	return (NeededSafePoints & 1 << Kind) != 0;	return (NeededSafePoints & 1 << Kind) != 0;
	}	}

	/// customWriteBarrier - By default, write barriers are replaced with s imple	/// customWriteBarrier - By default, write barriers are replaced with s imple
	/// store instructions. If true, then	/// store instructions. If true, then
	/// performCustomLowering must instead lower them.	/// performCustomLowering must instead lower them.

	skipping to change at line 112	skipping to change at line 117
	/// customReadBarrier - By default, read barriers are replaced with sim ple	/// customReadBarrier - By default, read barriers are replaced with sim ple
	/// load instructions. If true, then	/// load instructions. If true, then
	/// performCustomLowering must instead lower them.	/// performCustomLowering must instead lower them.
	bool customReadBarrier() const { return CustomReadBarriers; }	bool customReadBarrier() const { return CustomReadBarriers; }

	/// customRoots - By default, roots are left for the code generator so it	/// customRoots - By default, roots are left for the code generator so it
	/// can generate a stack map. If true, then	/// can generate a stack map. If true, then
	// performCustomLowering must delete them.	// performCustomLowering must delete them.
	bool customRoots() const { return CustomRoots; }	bool customRoots() const { return CustomRoots; }


		/// customSafePoints - By default, the GC analysis will find safe
		/// points according to NeededSafePoints. If true,
		/// then findCustomSafePoints must create them.
		bool customSafePoints() const { return CustomSafePoints; }

	/// initializeRoots - If set, gcroot intrinsics should initialize their	/// initializeRoots - If set, gcroot intrinsics should initialize their
	// allocas to null before the first use. This is	// allocas to null before the first use. This is
	// necessary for most GCs and is enabled by default.	// necessary for most GCs and is enabled by default.
	bool initializeRoots() const { return InitRoots; }	bool initializeRoots() const { return InitRoots; }

	/// usesMetadata - If set, appropriate metadata tables must be emitted by	/// usesMetadata - If set, appropriate metadata tables must be emitted by
	/// the back-end (assembler, JIT, or otherwise).	/// the back-end (assembler, JIT, or otherwise).
	bool usesMetadata() const { return UsesMetadata; }	bool usesMetadata() const { return UsesMetadata; }

	/// begin/end - Iterators for function metadata.	/// begin/end - Iterators for function metadata.

	skipping to change at line 137	skipping to change at line 147
	///	///
	GCFunctionInfo *insertFunctionInfo(const Function &F);	GCFunctionInfo *insertFunctionInfo(const Function &F);

	/// initializeCustomLowering/performCustomLowering - If any of the acti ons	/// initializeCustomLowering/performCustomLowering - If any of the acti ons
	/// are set to custom, performCustomLowering must be overriden to trans form	/// are set to custom, performCustomLowering must be overriden to trans form
	/// the corresponding actions to LLVM IR. initializeCustomLowering is	/// the corresponding actions to LLVM IR. initializeCustomLowering is
	/// optional to override. These are the only GCStrategy methods through	/// optional to override. These are the only GCStrategy methods through
	/// which the LLVM IR can be modified.	/// which the LLVM IR can be modified.
	virtual bool initializeCustomLowering(Module &F);	virtual bool initializeCustomLowering(Module &F);
	virtual bool performCustomLowering(Function &F);	virtual bool performCustomLowering(Function &F);

		virtual bool findCustomSafePoints(GCFunctionInfo& FI, MachineFunction& MF);
	};	};

	}	}

	#endif	#endif

End of changes. 5 change blocks.
	1 lines changed or deleted	12 lines changed or added

	GlobalValue.h	GlobalValue.h

	skipping to change at line 62	skipping to change at line 62
	/// @brief An enumeration for the kinds of visibility of global values.	/// @brief An enumeration for the kinds of visibility of global values.
	enum VisibilityTypes {	enum VisibilityTypes {
	DefaultVisibility = 0, ///< The GV is visible	DefaultVisibility = 0, ///< The GV is visible
	HiddenVisibility, ///< The GV is hidden	HiddenVisibility, ///< The GV is hidden
	ProtectedVisibility ///< The GV is protected	ProtectedVisibility ///< The GV is protected
	};	};

	protected:	protected:
	GlobalValue(Type ty, ValueTy vty, Use Ops, unsigned NumOps,	GlobalValue(Type ty, ValueTy vty, Use Ops, unsigned NumOps,
	LinkageTypes linkage, const Twine &Name)	LinkageTypes linkage, const Twine &Name)

	: Constant(ty, vty, Ops, NumOps), Parent(0),	: Constant(ty, vty, Ops, NumOps), Linkage(linkage),
	Linkage(linkage), Visibility(DefaultVisibility), Alignment(0),	Visibility(DefaultVisibility), Alignment(0), UnnamedAddr(0), Parent(0
	UnnamedAddr(0) {	) {
	setName(Name);	setName(Name);
	}	}


	Module *Parent;
	// Note: VC++ treats enums as signed, so an extra bit is required to prev ent	// Note: VC++ treats enums as signed, so an extra bit is required to prev ent
	// Linkage and Visibility from turning into negative values.	// Linkage and Visibility from turning into negative values.
	LinkageTypes Linkage : 5; // The linkage of this global	LinkageTypes Linkage : 5; // The linkage of this global
	unsigned Visibility : 2; // The visibility style of this global	unsigned Visibility : 2; // The visibility style of this global
	unsigned Alignment : 16; // Alignment of this symbol, must be power of two	unsigned Alignment : 16; // Alignment of this symbol, must be power of two
	unsigned UnnamedAddr : 1; // This value's address is not significant	unsigned UnnamedAddr : 1; // This value's address is not significant

		Module *Parent; // The containing module.
	std::string Section; // Section to emit this into, empty mean defa ult	std::string Section; // Section to emit this into, empty mean defa ult
	public:	public:
	~GlobalValue() {	~GlobalValue() {
	removeDeadConstantUsers(); // remove any dead constants using this.	removeDeadConstantUsers(); // remove any dead constants using this.
	}	}

	unsigned getAlignment() const {	unsigned getAlignment() const {
	return (1u << Alignment) >> 1;	return (1u << Alignment) >> 1;
	}	}
	void setAlignment(unsigned Align);	void setAlignment(unsigned Align);

End of changes. 3 change blocks.
	4 lines changed or deleted	4 lines changed or added

	GraphTraits.h	GraphTraits.h

	skipping to change at line 45	skipping to change at line 45

	// static ChildIteratorType child_begin(NodeType *)	// static ChildIteratorType child_begin(NodeType *)
	// static ChildIteratorType child_end (NodeType *)	// static ChildIteratorType child_end (NodeType *)
	// Return iterators that point to the beginning and ending of the chil d	// Return iterators that point to the beginning and ending of the chil d
	// node list for the specified node.	// node list for the specified node.
	//	//

	// typedef ...iterator nodes_iterator;	// typedef ...iterator nodes_iterator;
	// static nodes_iterator nodes_begin(GraphType *G)	// static nodes_iterator nodes_begin(GraphType *G)
	// static nodes_iterator nodes_end (GraphType *G)	// static nodes_iterator nodes_end (GraphType *G)

	//
	// nodes_iterator/begin/end - Allow iteration over all nodes in the gr aph	// nodes_iterator/begin/end - Allow iteration over all nodes in the gr aph


		// static unsigned size (GraphType *G)
		// Return total number of nodes in the graph
		//

	// If anyone tries to use this class without having an appropriate	// If anyone tries to use this class without having an appropriate
	// specialization, make an error. If you get this error, it's because yo u	// specialization, make an error. If you get this error, it's because yo u
	// need to include the appropriate specialization of GraphTraits<> for yo ur	// need to include the appropriate specialization of GraphTraits<> for yo ur
	// graph, or you need to define it for a new graph type. Either that or	// graph, or you need to define it for a new graph type. Either that or
	// your argument to XXX_begin(...) is unknown or needs to have the proper .h	// your argument to XXX_begin(...) is unknown or needs to have the proper .h
	// file #include'd.	// file #include'd.
	//	//
	typedef typename GraphType::UnknownGraphTypeError NodeType;	typedef typename GraphType::UnknownGraphTypeError NodeType;
	};	};


End of changes. 2 change blocks.
	1 lines changed or deleted	4 lines changed or added

	HeuristicBase.h	HeuristicBase.h

	skipping to change at line 160	skipping to change at line 160
	if (optimalList.empty())	if (optimalList.empty())
	return false;	return false;

	Graph::NodeItr nItr = optimalList.front();	Graph::NodeItr nItr = optimalList.front();
	optimalList.pop_front();	optimalList.pop_front();

	switch (s.getSolverDegree(nItr)) {	switch (s.getSolverDegree(nItr)) {
	case 0: s.applyR0(nItr); break;	case 0: s.applyR0(nItr); break;
	case 1: s.applyR1(nItr); break;	case 1: s.applyR1(nItr); break;
	case 2: s.applyR2(nItr); break;	case 2: s.applyR2(nItr); break;

	default: assert(false &&	default: llvm_unreachable(
	"Optimal reductions of degree > 2 nodes is invalid. ");	"Optimal reductions of degree > 2 nodes is invalid. ");
	}	}

	return true;	return true;
	}	}

	/// \brief Perform the PBQP reduction process.	/// \brief Perform the PBQP reduction process.
	///	///
	/// Reduces the problem to the empty graph by repeated application of t he	/// Reduces the problem to the empty graph by repeated application of t he
	/// reduction rules R0, R1, R2 and RN.	/// reduction rules R0, R1, R2 and RN.

	skipping to change at line 189	skipping to change at line 189
	} else {	} else {
	finished = true;	finished = true;
	}	}
	}	}
	}	}
	}	}

	/// \brief Add a node to the heuristic reduce list.	/// \brief Add a node to the heuristic reduce list.
	/// @param nItr Node iterator to add to the heuristic reduce list.	/// @param nItr Node iterator to add to the heuristic reduce list.
	void addToHeuristicList(Graph::NodeItr nItr) {	void addToHeuristicList(Graph::NodeItr nItr) {

	assert(false && "Must be implemented in derived class.");	llvm_unreachable("Must be implemented in derived class.");
	}	}

	/// \brief Heuristically reduce one of the nodes in the heuristic	/// \brief Heuristically reduce one of the nodes in the heuristic
	/// reduce list.	/// reduce list.
	/// @return True if a reduction takes place, false if the heuristic red uce	/// @return True if a reduction takes place, false if the heuristic red uce
	/// list is empty.	/// list is empty.
	void heuristicReduce() {	void heuristicReduce() {

	assert(false && "Must be implemented in derived class.");	llvm_unreachable("Must be implemented in derived class.");
	}	}

	/// \brief Prepare a change in the costs on the given edge.	/// \brief Prepare a change in the costs on the given edge.
	/// @param eItr Edge iterator.	/// @param eItr Edge iterator.
	void preUpdateEdgeCosts(Graph::EdgeItr eItr) {	void preUpdateEdgeCosts(Graph::EdgeItr eItr) {

	assert(false && "Must be implemented in derived class.");	llvm_unreachable("Must be implemented in derived class.");
	}	}

	/// \brief Handle the change in the costs on the given edge.	/// \brief Handle the change in the costs on the given edge.
	/// @param eItr Edge iterator.	/// @param eItr Edge iterator.
	void postUpdateEdgeCostts(Graph::EdgeItr eItr) {	void postUpdateEdgeCostts(Graph::EdgeItr eItr) {

	assert(false && "Must be implemented in derived class.");	llvm_unreachable("Must be implemented in derived class.");
	}	}

	/// \brief Handle the addition of a new edge into the PBQP graph.	/// \brief Handle the addition of a new edge into the PBQP graph.
	/// @param eItr Edge iterator for the added edge.	/// @param eItr Edge iterator for the added edge.
	void handleAddEdge(Graph::EdgeItr eItr) {	void handleAddEdge(Graph::EdgeItr eItr) {

	assert(false && "Must be implemented in derived class.");	llvm_unreachable("Must be implemented in derived class.");
	}	}

	/// \brief Handle disconnection of an edge from a node.	/// \brief Handle disconnection of an edge from a node.
	/// @param eItr Edge iterator for edge being disconnected.	/// @param eItr Edge iterator for edge being disconnected.
	/// @param nItr Node iterator for the node being disconnected from.	/// @param nItr Node iterator for the node being disconnected from.
	///	///
	/// Edges are frequently removed due to the removal of a node. This	/// Edges are frequently removed due to the removal of a node. This
	/// method allows for the effect to be computed only for the remaining	/// method allows for the effect to be computed only for the remaining
	/// node in the graph.	/// node in the graph.
	void handleRemoveEdge(Graph::EdgeItr eItr, Graph::NodeItr nItr) {	void handleRemoveEdge(Graph::EdgeItr eItr, Graph::NodeItr nItr) {

	assert(false && "Must be implemented in derived class.");	llvm_unreachable("Must be implemented in derived class.");
	}	}

	/// \brief Clean up any structures used by HeuristicBase.	/// \brief Clean up any structures used by HeuristicBase.
	///	///
	/// At present this just performs a sanity check: that the optimal redu ce	/// At present this just performs a sanity check: that the optimal redu ce
	/// list is empty now that reduction has completed.	/// list is empty now that reduction has completed.
	///	///
	/// If your derived class has more complex structures which need tearin g	/// If your derived class has more complex structures which need tearin g
	/// down you should over-ride this method but include a call back to th is	/// down you should over-ride this method but include a call back to th is
	/// implementation.	/// implementation.

End of changes. 7 change blocks.
	7 lines changed or deleted	7 lines changed or added

	IPO.h	IPO.h

	skipping to change at line 94	skipping to change at line 94
	///	///
	/// The -inline-threshold command line option takes precedence over the	/// The -inline-threshold command line option takes precedence over the
	/// threshold given here.	/// threshold given here.
	Pass *createFunctionInliningPass();	Pass *createFunctionInliningPass();
	Pass *createFunctionInliningPass(int Threshold);	Pass *createFunctionInliningPass(int Threshold);

	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	/// createAlwaysInlinerPass - Return a new pass object that inlines only	/// createAlwaysInlinerPass - Return a new pass object that inlines only
	/// functions that are marked as "always_inline".	/// functions that are marked as "always_inline".
	Pass *createAlwaysInlinerPass();	Pass *createAlwaysInlinerPass();

		Pass *createAlwaysInlinerPass(bool InsertLifetime);

	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	/// createPruneEHPass - Return a new pass object which transforms invoke	/// createPruneEHPass - Return a new pass object which transforms invoke
	/// instructions into calls, if the callee can _not_ unwind the stack.	/// instructions into calls, if the callee can _not_ unwind the stack.
	///	///
	Pass *createPruneEHPass();	Pass *createPruneEHPass();

	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	/// createInternalizePass - This pass loops over all of the functions in th e	/// createInternalizePass - This pass loops over all of the functions in th e
	/// input module, internalizing all globals (functions and variables) not p art	/// input module, internalizing all globals (functions and variables) not p art

End of changes. 1 change blocks.
	0 lines changed or deleted	1 lines changed or added

	IRBuilder.h	IRBuilder.h

	skipping to change at line 20	skipping to change at line 20
	// This file defines the IRBuilder class, which is used as a convenient way	// This file defines the IRBuilder class, which is used as a convenient way
	// to create LLVM instructions with a consistent and simplified interface.	// to create LLVM instructions with a consistent and simplified interface.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_SUPPORT_IRBUILDER_H	#ifndef LLVM_SUPPORT_IRBUILDER_H
	#define LLVM_SUPPORT_IRBUILDER_H	#define LLVM_SUPPORT_IRBUILDER_H

	#include "llvm/Instructions.h"	#include "llvm/Instructions.h"
	#include "llvm/BasicBlock.h"	#include "llvm/BasicBlock.h"

		#include "llvm/LLVMContext.h"
	#include "llvm/ADT/ArrayRef.h"	#include "llvm/ADT/ArrayRef.h"
	#include "llvm/ADT/StringRef.h"	#include "llvm/ADT/StringRef.h"
	#include "llvm/ADT/Twine.h"	#include "llvm/ADT/Twine.h"
	#include "llvm/Support/ConstantFolder.h"	#include "llvm/Support/ConstantFolder.h"

	namespace llvm {	namespace llvm {
	class MDNode;	class MDNode;

	/// IRBuilderDefaultInserter - This provides the default implementation of the	/// IRBuilderDefaultInserter - This provides the default implementation of the
	/// IRBuilder 'InsertHelper' method that is called whenever an instruction is	/// IRBuilder 'InsertHelper' method that is called whenever an instruction is

	skipping to change at line 334	skipping to change at line 335
	/// The first template argument handles whether or not to preserve names in the	/// The first template argument handles whether or not to preserve names in the
	/// final instruction output. This defaults to on. The second template arg ument	/// final instruction output. This defaults to on. The second template arg ument
	/// specifies a class to use for creating constants. This defaults to crea ting	/// specifies a class to use for creating constants. This defaults to crea ting
	/// minimally folded constants. The fourth template argument allows client s to	/// minimally folded constants. The fourth template argument allows client s to
	/// specify custom insertion hooks that are called on every newly created	/// specify custom insertion hooks that are called on every newly created
	/// insertion.	/// insertion.
	template<bool preserveNames = true, typename T = ConstantFolder,	template<bool preserveNames = true, typename T = ConstantFolder,
	typename Inserter = IRBuilderDefaultInserter<preserveNames> >	typename Inserter = IRBuilderDefaultInserter<preserveNames> >
	class IRBuilder : public IRBuilderBase, public Inserter {	class IRBuilder : public IRBuilderBase, public Inserter {
	T Folder;	T Folder;

		MDNode *DefaultFPMathTag;
	public:	public:

	IRBuilder(LLVMContext &C, const T &F, const Inserter &I = Inserter())	IRBuilder(LLVMContext &C, const T &F, const Inserter &I = Inserter(),
	: IRBuilderBase(C), Inserter(I), Folder(F) {	MDNode *FPMathTag = 0)
		: IRBuilderBase(C), Inserter(I), Folder(F), DefaultFPMathTag(FPMathTag)
		{
	}	}


	explicit IRBuilder(LLVMContext &C) : IRBuilderBase(C), Folder() {	explicit IRBuilder(LLVMContext &C, MDNode *FPMathTag = 0) : IRBuilderBase
		(C),
		Folder(), DefaultFPMathTag(FPMathTag) {
	}	}


	explicit IRBuilder(BasicBlock *TheBB, const T &F)	explicit IRBuilder(BasicBlock TheBB, const T &F, MDNode FPMathTag = 0)
	: IRBuilderBase(TheBB->getContext()), Folder(F) {	: IRBuilderBase(TheBB->getContext()), Folder(F),
		DefaultFPMathTag(FPMathTag) {
	SetInsertPoint(TheBB);	SetInsertPoint(TheBB);
	}	}


	explicit IRBuilder(BasicBlock *TheBB)	explicit IRBuilder(BasicBlock TheBB, MDNode FPMathTag = 0)
	: IRBuilderBase(TheBB->getContext()), Folder() {	: IRBuilderBase(TheBB->getContext()), Folder(),
		DefaultFPMathTag(FPMathTag) {
	SetInsertPoint(TheBB);	SetInsertPoint(TheBB);
	}	}


	explicit IRBuilder(Instruction *IP)	explicit IRBuilder(Instruction IP, MDNode FPMathTag = 0)
	: IRBuilderBase(IP->getContext()), Folder() {	: IRBuilderBase(IP->getContext()), Folder(), DefaultFPMathTag(FPMathTag
		) {
	SetInsertPoint(IP);	SetInsertPoint(IP);
	SetCurrentDebugLocation(IP->getDebugLoc());	SetCurrentDebugLocation(IP->getDebugLoc());
	}	}


	explicit IRBuilder(Use &U)	explicit IRBuilder(Use &U, MDNode *FPMathTag = 0)
	: IRBuilderBase(U->getContext()), Folder() {	: IRBuilderBase(U->getContext()), Folder(), DefaultFPMathTag(FPMathTag)
		{
	SetInsertPoint(U);	SetInsertPoint(U);
	SetCurrentDebugLocation(cast<Instruction>(U.getUser())->getDebugLoc());	SetCurrentDebugLocation(cast<Instruction>(U.getUser())->getDebugLoc());
	}	}


	IRBuilder(BasicBlock *TheBB, BasicBlock::iterator IP, const T& F)	IRBuilder(BasicBlock *TheBB, BasicBlock::iterator IP, const T& F,
	: IRBuilderBase(TheBB->getContext()), Folder(F) {	MDNode *FPMathTag = 0)
		: IRBuilderBase(TheBB->getContext()), Folder(F),
		DefaultFPMathTag(FPMathTag) {
	SetInsertPoint(TheBB, IP);	SetInsertPoint(TheBB, IP);
	}	}


	IRBuilder(BasicBlock *TheBB, BasicBlock::iterator IP)	IRBuilder(BasicBlock TheBB, BasicBlock::iterator IP, MDNode FPMathTag =
	: IRBuilderBase(TheBB->getContext()), Folder() {	0)
		: IRBuilderBase(TheBB->getContext()), Folder(),
		DefaultFPMathTag(FPMathTag) {
	SetInsertPoint(TheBB, IP);	SetInsertPoint(TheBB, IP);
	}	}

	/// getFolder - Get the constant folder being used.	/// getFolder - Get the constant folder being used.
	const T &getFolder() { return Folder; }	const T &getFolder() { return Folder; }


		/// getDefaultFPMathTag - Get the floating point math metadata being used
		.
		MDNode *getDefaultFPMathTag() const { return DefaultFPMathTag; }

		/// SetDefaultFPMathTag - Set the floating point math metadata to be used
		.
		void SetDefaultFPMathTag(MDNode *FPMathTag) { DefaultFPMathTag = FPMathTa
		g; }

	/// isNamePreserving - Return true if this builder is configured to actua lly	/// isNamePreserving - Return true if this builder is configured to actua lly
	/// add the requested names to IR created through it.	/// add the requested names to IR created through it.
	bool isNamePreserving() const { return preserveNames; }	bool isNamePreserving() const { return preserveNames; }

	/// Insert - Insert and return the specified instruction.	/// Insert - Insert and return the specified instruction.
	template<typename InstTy>	template<typename InstTy>
	InstTy Insert(InstTy I, const Twine &Name = "") const {	InstTy Insert(InstTy I, const Twine &Name = "") const {
	this->InsertHelper(I, Name, BB, InsertPt);	this->InsertHelper(I, Name, BB, InsertPt);
	if (!getCurrentDebugLocation().isUnknown())	if (!getCurrentDebugLocation().isUnknown())
	this->SetInstDebugLocation(I);	this->SetInstDebugLocation(I);

	skipping to change at line 499	skipping to change at line 514
	private:	private:
	BinaryOperator *CreateInsertNUWNSWBinOp(BinaryOperator::BinaryOps Opc,	BinaryOperator *CreateInsertNUWNSWBinOp(BinaryOperator::BinaryOps Opc,
	Value LHS, Value RHS,	Value LHS, Value RHS,
	const Twine &Name,	const Twine &Name,
	bool HasNUW, bool HasNSW) {	bool HasNUW, bool HasNSW) {
	BinaryOperator *BO = Insert(BinaryOperator::Create(Opc, LHS, RHS), Name );	BinaryOperator *BO = Insert(BinaryOperator::Create(Opc, LHS, RHS), Name );
	if (HasNUW) BO->setHasNoUnsignedWrap();	if (HasNUW) BO->setHasNoUnsignedWrap();
	if (HasNSW) BO->setHasNoSignedWrap();	if (HasNSW) BO->setHasNoSignedWrap();
	return BO;	return BO;
	}	}


		Instruction AddFPMathTag(Instruction I, MDNode *FPMathTag) const {
		if (!FPMathTag)
		FPMathTag = DefaultFPMathTag;
		if (FPMathTag)
		I->setMetadata(LLVMContext::MD_fpmath, FPMathTag);
		return I;
		}
	public:	public:
	Value CreateAdd(Value LHS, Value *RHS, const Twine &Name = "",	Value CreateAdd(Value LHS, Value *RHS, const Twine &Name = "",
	bool HasNUW = false, bool HasNSW = false) {	bool HasNUW = false, bool HasNSW = false) {
	if (Constant *LC = dyn_cast<Constant>(LHS))	if (Constant *LC = dyn_cast<Constant>(LHS))
	if (Constant *RC = dyn_cast<Constant>(RHS))	if (Constant *RC = dyn_cast<Constant>(RHS))
	return Insert(Folder.CreateAdd(LC, RC, HasNUW, HasNSW), Name);	return Insert(Folder.CreateAdd(LC, RC, HasNUW, HasNSW), Name);
	return CreateInsertNUWNSWBinOp(Instruction::Add, LHS, RHS, Name,	return CreateInsertNUWNSWBinOp(Instruction::Add, LHS, RHS, Name,
	HasNUW, HasNSW);	HasNUW, HasNSW);
	}	}
	Value CreateNSWAdd(Value LHS, Value *RHS, const Twine &Name = "") {	Value CreateNSWAdd(Value LHS, Value *RHS, const Twine &Name = "") {
	return CreateAdd(LHS, RHS, Name, false, true);	return CreateAdd(LHS, RHS, Name, false, true);
	}	}
	Value CreateNUWAdd(Value LHS, Value *RHS, const Twine &Name = "") {	Value CreateNUWAdd(Value LHS, Value *RHS, const Twine &Name = "") {
	return CreateAdd(LHS, RHS, Name, true, false);	return CreateAdd(LHS, RHS, Name, true, false);
	}	}

	Value CreateFAdd(Value LHS, Value *RHS, const Twine &Name = "") {	Value CreateFAdd(Value LHS, Value *RHS, const Twine &Name = "",
		MDNode *FPMathTag = 0) {
	if (Constant *LC = dyn_cast<Constant>(LHS))	if (Constant *LC = dyn_cast<Constant>(LHS))
	if (Constant *RC = dyn_cast<Constant>(RHS))	if (Constant *RC = dyn_cast<Constant>(RHS))
	return Insert(Folder.CreateFAdd(LC, RC), Name);	return Insert(Folder.CreateFAdd(LC, RC), Name);

	return Insert(BinaryOperator::CreateFAdd(LHS, RHS), Name);	return Insert(AddFPMathTag(BinaryOperator::CreateFAdd(LHS, RHS),
		FPMathTag), Name);
	}	}
	Value CreateSub(Value LHS, Value *RHS, const Twine &Name = "",	Value CreateSub(Value LHS, Value *RHS, const Twine &Name = "",
	bool HasNUW = false, bool HasNSW = false) {	bool HasNUW = false, bool HasNSW = false) {
	if (Constant *LC = dyn_cast<Constant>(LHS))	if (Constant *LC = dyn_cast<Constant>(LHS))
	if (Constant *RC = dyn_cast<Constant>(RHS))	if (Constant *RC = dyn_cast<Constant>(RHS))
	return Insert(Folder.CreateSub(LC, RC), Name);	return Insert(Folder.CreateSub(LC, RC), Name);
	return CreateInsertNUWNSWBinOp(Instruction::Sub, LHS, RHS, Name,	return CreateInsertNUWNSWBinOp(Instruction::Sub, LHS, RHS, Name,
	HasNUW, HasNSW);	HasNUW, HasNSW);
	}	}
	Value CreateNSWSub(Value LHS, Value *RHS, const Twine &Name = "") {	Value CreateNSWSub(Value LHS, Value *RHS, const Twine &Name = "") {
	return CreateSub(LHS, RHS, Name, false, true);	return CreateSub(LHS, RHS, Name, false, true);
	}	}
	Value CreateNUWSub(Value LHS, Value *RHS, const Twine &Name = "") {	Value CreateNUWSub(Value LHS, Value *RHS, const Twine &Name = "") {
	return CreateSub(LHS, RHS, Name, true, false);	return CreateSub(LHS, RHS, Name, true, false);
	}	}

	Value CreateFSub(Value LHS, Value *RHS, const Twine &Name = "") {	Value CreateFSub(Value LHS, Value *RHS, const Twine &Name = "",
		MDNode *FPMathTag = 0) {
	if (Constant *LC = dyn_cast<Constant>(LHS))	if (Constant *LC = dyn_cast<Constant>(LHS))
	if (Constant *RC = dyn_cast<Constant>(RHS))	if (Constant *RC = dyn_cast<Constant>(RHS))
	return Insert(Folder.CreateFSub(LC, RC), Name);	return Insert(Folder.CreateFSub(LC, RC), Name);

	return Insert(BinaryOperator::CreateFSub(LHS, RHS), Name);	return Insert(AddFPMathTag(BinaryOperator::CreateFSub(LHS, RHS),
		FPMathTag), Name);
	}	}
	Value CreateMul(Value LHS, Value *RHS, const Twine &Name = "",	Value CreateMul(Value LHS, Value *RHS, const Twine &Name = "",
	bool HasNUW = false, bool HasNSW = false) {	bool HasNUW = false, bool HasNSW = false) {
	if (Constant *LC = dyn_cast<Constant>(LHS))	if (Constant *LC = dyn_cast<Constant>(LHS))
	if (Constant *RC = dyn_cast<Constant>(RHS))	if (Constant *RC = dyn_cast<Constant>(RHS))
	return Insert(Folder.CreateMul(LC, RC), Name);	return Insert(Folder.CreateMul(LC, RC), Name);
	return CreateInsertNUWNSWBinOp(Instruction::Mul, LHS, RHS, Name,	return CreateInsertNUWNSWBinOp(Instruction::Mul, LHS, RHS, Name,
	HasNUW, HasNSW);	HasNUW, HasNSW);
	}	}
	Value CreateNSWMul(Value LHS, Value *RHS, const Twine &Name = "") {	Value CreateNSWMul(Value LHS, Value *RHS, const Twine &Name = "") {
	return CreateMul(LHS, RHS, Name, false, true);	return CreateMul(LHS, RHS, Name, false, true);
	}	}
	Value CreateNUWMul(Value LHS, Value *RHS, const Twine &Name = "") {	Value CreateNUWMul(Value LHS, Value *RHS, const Twine &Name = "") {
	return CreateMul(LHS, RHS, Name, true, false);	return CreateMul(LHS, RHS, Name, true, false);
	}	}

	Value CreateFMul(Value LHS, Value *RHS, const Twine &Name = "") {	Value CreateFMul(Value LHS, Value *RHS, const Twine &Name = "",
		MDNode *FPMathTag = 0) {
	if (Constant *LC = dyn_cast<Constant>(LHS))	if (Constant *LC = dyn_cast<Constant>(LHS))
	if (Constant *RC = dyn_cast<Constant>(RHS))	if (Constant *RC = dyn_cast<Constant>(RHS))
	return Insert(Folder.CreateFMul(LC, RC), Name);	return Insert(Folder.CreateFMul(LC, RC), Name);

	return Insert(BinaryOperator::CreateFMul(LHS, RHS), Name);	return Insert(AddFPMathTag(BinaryOperator::CreateFMul(LHS, RHS),
		FPMathTag), Name);
	}	}
	Value CreateUDiv(Value LHS, Value *RHS, const Twine &Name = "",	Value CreateUDiv(Value LHS, Value *RHS, const Twine &Name = "",
	bool isExact = false) {	bool isExact = false) {
	if (Constant *LC = dyn_cast<Constant>(LHS))	if (Constant *LC = dyn_cast<Constant>(LHS))
	if (Constant *RC = dyn_cast<Constant>(RHS))	if (Constant *RC = dyn_cast<Constant>(RHS))
	return Insert(Folder.CreateUDiv(LC, RC, isExact), Name);	return Insert(Folder.CreateUDiv(LC, RC, isExact), Name);
	if (!isExact)	if (!isExact)
	return Insert(BinaryOperator::CreateUDiv(LHS, RHS), Name);	return Insert(BinaryOperator::CreateUDiv(LHS, RHS), Name);
	return Insert(BinaryOperator::CreateExactUDiv(LHS, RHS), Name);	return Insert(BinaryOperator::CreateExactUDiv(LHS, RHS), Name);
	}	}

	skipping to change at line 584	skipping to change at line 613
	if (Constant *LC = dyn_cast<Constant>(LHS))	if (Constant *LC = dyn_cast<Constant>(LHS))
	if (Constant *RC = dyn_cast<Constant>(RHS))	if (Constant *RC = dyn_cast<Constant>(RHS))
	return Insert(Folder.CreateSDiv(LC, RC, isExact), Name);	return Insert(Folder.CreateSDiv(LC, RC, isExact), Name);
	if (!isExact)	if (!isExact)
	return Insert(BinaryOperator::CreateSDiv(LHS, RHS), Name);	return Insert(BinaryOperator::CreateSDiv(LHS, RHS), Name);
	return Insert(BinaryOperator::CreateExactSDiv(LHS, RHS), Name);	return Insert(BinaryOperator::CreateExactSDiv(LHS, RHS), Name);
	}	}
	Value CreateExactSDiv(Value LHS, Value *RHS, const Twine &Name = "") {	Value CreateExactSDiv(Value LHS, Value *RHS, const Twine &Name = "") {
	return CreateSDiv(LHS, RHS, Name, true);	return CreateSDiv(LHS, RHS, Name, true);
	}	}

	Value CreateFDiv(Value LHS, Value *RHS, const Twine &Name = "") {	Value CreateFDiv(Value LHS, Value *RHS, const Twine &Name = "",
		MDNode *FPMathTag = 0) {
	if (Constant *LC = dyn_cast<Constant>(LHS))	if (Constant *LC = dyn_cast<Constant>(LHS))
	if (Constant *RC = dyn_cast<Constant>(RHS))	if (Constant *RC = dyn_cast<Constant>(RHS))
	return Insert(Folder.CreateFDiv(LC, RC), Name);	return Insert(Folder.CreateFDiv(LC, RC), Name);

	return Insert(BinaryOperator::CreateFDiv(LHS, RHS), Name);	return Insert(AddFPMathTag(BinaryOperator::CreateFDiv(LHS, RHS),
		FPMathTag), Name);
	}	}
	Value CreateURem(Value LHS, Value *RHS, const Twine &Name = "") {	Value CreateURem(Value LHS, Value *RHS, const Twine &Name = "") {
	if (Constant *LC = dyn_cast<Constant>(LHS))	if (Constant *LC = dyn_cast<Constant>(LHS))
	if (Constant *RC = dyn_cast<Constant>(RHS))	if (Constant *RC = dyn_cast<Constant>(RHS))
	return Insert(Folder.CreateURem(LC, RC), Name);	return Insert(Folder.CreateURem(LC, RC), Name);
	return Insert(BinaryOperator::CreateURem(LHS, RHS), Name);	return Insert(BinaryOperator::CreateURem(LHS, RHS), Name);
	}	}
	Value CreateSRem(Value LHS, Value *RHS, const Twine &Name = "") {	Value CreateSRem(Value LHS, Value *RHS, const Twine &Name = "") {
	if (Constant *LC = dyn_cast<Constant>(LHS))	if (Constant *LC = dyn_cast<Constant>(LHS))
	if (Constant *RC = dyn_cast<Constant>(RHS))	if (Constant *RC = dyn_cast<Constant>(RHS))
	return Insert(Folder.CreateSRem(LC, RC), Name);	return Insert(Folder.CreateSRem(LC, RC), Name);
	return Insert(BinaryOperator::CreateSRem(LHS, RHS), Name);	return Insert(BinaryOperator::CreateSRem(LHS, RHS), Name);
	}	}

	Value CreateFRem(Value LHS, Value *RHS, const Twine &Name = "") {	Value CreateFRem(Value LHS, Value *RHS, const Twine &Name = "",
		MDNode *FPMathTag = 0) {
	if (Constant *LC = dyn_cast<Constant>(LHS))	if (Constant *LC = dyn_cast<Constant>(LHS))
	if (Constant *RC = dyn_cast<Constant>(RHS))	if (Constant *RC = dyn_cast<Constant>(RHS))
	return Insert(Folder.CreateFRem(LC, RC), Name);	return Insert(Folder.CreateFRem(LC, RC), Name);

	return Insert(BinaryOperator::CreateFRem(LHS, RHS), Name);	return Insert(AddFPMathTag(BinaryOperator::CreateFRem(LHS, RHS),
		FPMathTag), Name);
	}	}

	Value CreateShl(Value LHS, Value *RHS, const Twine &Name = "",	Value CreateShl(Value LHS, Value *RHS, const Twine &Name = "",
	bool HasNUW = false, bool HasNSW = false) {	bool HasNUW = false, bool HasNSW = false) {
	if (Constant *LC = dyn_cast<Constant>(LHS))	if (Constant *LC = dyn_cast<Constant>(LHS))
	if (Constant *RC = dyn_cast<Constant>(RHS))	if (Constant *RC = dyn_cast<Constant>(RHS))
	return Insert(Folder.CreateShl(LC, RC, HasNUW, HasNSW), Name);	return Insert(Folder.CreateShl(LC, RC, HasNUW, HasNSW), Name);
	return CreateInsertNUWNSWBinOp(Instruction::Shl, LHS, RHS, Name,	return CreateInsertNUWNSWBinOp(Instruction::Shl, LHS, RHS, Name,
	HasNUW, HasNSW);	HasNUW, HasNSW);
	}	}

	skipping to change at line 732	skipping to change at line 765
	if (HasNUW) BO->setHasNoUnsignedWrap();	if (HasNUW) BO->setHasNoUnsignedWrap();
	if (HasNSW) BO->setHasNoSignedWrap();	if (HasNSW) BO->setHasNoSignedWrap();
	return BO;	return BO;
	}	}
	Value CreateNSWNeg(Value V, const Twine &Name = "") {	Value CreateNSWNeg(Value V, const Twine &Name = "") {
	return CreateNeg(V, Name, false, true);	return CreateNeg(V, Name, false, true);
	}	}
	Value CreateNUWNeg(Value V, const Twine &Name = "") {	Value CreateNUWNeg(Value V, const Twine &Name = "") {
	return CreateNeg(V, Name, true, false);	return CreateNeg(V, Name, true, false);
	}	}

	Value CreateFNeg(Value V, const Twine &Name = "") {	Value CreateFNeg(Value V, const Twine &Name = "", MDNode *FPMathTag = 0 ) {
	if (Constant *VC = dyn_cast<Constant>(V))	if (Constant *VC = dyn_cast<Constant>(V))
	return Insert(Folder.CreateFNeg(VC), Name);	return Insert(Folder.CreateFNeg(VC), Name);

	return Insert(BinaryOperator::CreateFNeg(V), Name);	return Insert(AddFPMathTag(BinaryOperator::CreateFNeg(V), FPMathTag), N ame);
	}	}
	Value CreateNot(Value V, const Twine &Name = "") {	Value CreateNot(Value V, const Twine &Name = "") {
	if (Constant *VC = dyn_cast<Constant>(V))	if (Constant *VC = dyn_cast<Constant>(V))
	return Insert(Folder.CreateNot(VC), Name);	return Insert(Folder.CreateNot(VC), Name);
	return Insert(BinaryOperator::CreateNot(V), Name);	return Insert(BinaryOperator::CreateNot(V), Name);
	}	}

	//===-------------------------------------------------------------------- ===//	//===-------------------------------------------------------------------- ===//
	// Instruction creation methods: Memory Instructions	// Instruction creation methods: Memory Instructions
	//===-------------------------------------------------------------------- ===//	//===-------------------------------------------------------------------- ===//

End of changes. 24 change blocks.
	27 lines changed or deleted	68 lines changed or added

	InitializePasses.h	InitializePasses.h

	skipping to change at line 34	skipping to change at line 34
	void initializeCore(PassRegistry&);	void initializeCore(PassRegistry&);

	/// initializeTransformUtils - Initialize all passes linked into the	/// initializeTransformUtils - Initialize all passes linked into the
	/// TransformUtils library.	/// TransformUtils library.
	void initializeTransformUtils(PassRegistry&);	void initializeTransformUtils(PassRegistry&);

	/// initializeScalarOpts - Initialize all passes linked into the	/// initializeScalarOpts - Initialize all passes linked into the
	/// ScalarOpts library.	/// ScalarOpts library.
	void initializeScalarOpts(PassRegistry&);	void initializeScalarOpts(PassRegistry&);


		/// initializeVectorization - Initialize all passes linked into the
		/// Vectorize library.
		void initializeVectorization(PassRegistry&);

	/// initializeInstCombine - Initialize all passes linked into the	/// initializeInstCombine - Initialize all passes linked into the
	/// ScalarOpts library.	/// ScalarOpts library.
	void initializeInstCombine(PassRegistry&);	void initializeInstCombine(PassRegistry&);

	/// initializeIPO - Initialize all passes linked into the IPO library.	/// initializeIPO - Initialize all passes linked into the IPO library.
	void initializeIPO(PassRegistry&);	void initializeIPO(PassRegistry&);

	/// initializeInstrumentation - Initialize all passes linked into the	/// initializeInstrumentation - Initialize all passes linked into the
	/// Instrumentation library.	/// Instrumentation library.
	void initializeInstrumentation(PassRegistry&);	void initializeInstrumentation(PassRegistry&);

	skipping to change at line 70	skipping to change at line 74
	void initializeAliasAnalysisCounterPass(PassRegistry&);	void initializeAliasAnalysisCounterPass(PassRegistry&);
	void initializeAliasDebuggerPass(PassRegistry&);	void initializeAliasDebuggerPass(PassRegistry&);
	void initializeAliasSetPrinterPass(PassRegistry&);	void initializeAliasSetPrinterPass(PassRegistry&);
	void initializeAlwaysInlinerPass(PassRegistry&);	void initializeAlwaysInlinerPass(PassRegistry&);
	void initializeArgPromotionPass(PassRegistry&);	void initializeArgPromotionPass(PassRegistry&);
	void initializeBasicAliasAnalysisPass(PassRegistry&);	void initializeBasicAliasAnalysisPass(PassRegistry&);
	void initializeBasicCallGraphPass(PassRegistry&);	void initializeBasicCallGraphPass(PassRegistry&);
	void initializeBlockExtractorPassPass(PassRegistry&);	void initializeBlockExtractorPassPass(PassRegistry&);
	void initializeBlockFrequencyInfoPass(PassRegistry&);	void initializeBlockFrequencyInfoPass(PassRegistry&);
	void initializeBlockPlacementPass(PassRegistry&);	void initializeBlockPlacementPass(PassRegistry&);

		void initializeBranchFolderPassPass(PassRegistry&);
	void initializeBranchProbabilityInfoPass(PassRegistry&);	void initializeBranchProbabilityInfoPass(PassRegistry&);
	void initializeBreakCriticalEdgesPass(PassRegistry&);	void initializeBreakCriticalEdgesPass(PassRegistry&);
	void initializeCFGOnlyPrinterPass(PassRegistry&);	void initializeCFGOnlyPrinterPass(PassRegistry&);
	void initializeCFGOnlyViewerPass(PassRegistry&);	void initializeCFGOnlyViewerPass(PassRegistry&);
	void initializeCFGPrinterPass(PassRegistry&);	void initializeCFGPrinterPass(PassRegistry&);
	void initializeCFGSimplifyPassPass(PassRegistry&);	void initializeCFGSimplifyPassPass(PassRegistry&);
	void initializeCFGViewerPass(PassRegistry&);	void initializeCFGViewerPass(PassRegistry&);
	void initializeCalculateSpillWeightsPass(PassRegistry&);	void initializeCalculateSpillWeightsPass(PassRegistry&);
	void initializeCallGraphAnalysisGroup(PassRegistry&);	void initializeCallGraphAnalysisGroup(PassRegistry&);
	void initializeCodeGenPreparePass(PassRegistry&);	void initializeCodeGenPreparePass(PassRegistry&);

		void initializeCodePlacementOptPass(PassRegistry&);
	void initializeConstantMergePass(PassRegistry&);	void initializeConstantMergePass(PassRegistry&);
	void initializeConstantPropagationPass(PassRegistry&);	void initializeConstantPropagationPass(PassRegistry&);

		void initializeMachineCopyPropagationPass(PassRegistry&);
	void initializeCorrelatedValuePropagationPass(PassRegistry&);	void initializeCorrelatedValuePropagationPass(PassRegistry&);
	void initializeDAEPass(PassRegistry&);	void initializeDAEPass(PassRegistry&);
	void initializeDAHPass(PassRegistry&);	void initializeDAHPass(PassRegistry&);
	void initializeDCEPass(PassRegistry&);	void initializeDCEPass(PassRegistry&);
	void initializeDSEPass(PassRegistry&);	void initializeDSEPass(PassRegistry&);
	void initializeDeadInstEliminationPass(PassRegistry&);	void initializeDeadInstEliminationPass(PassRegistry&);
	void initializeDeadMachineInstructionElimPass(PassRegistry&);	void initializeDeadMachineInstructionElimPass(PassRegistry&);
	void initializeDomOnlyPrinterPass(PassRegistry&);	void initializeDomOnlyPrinterPass(PassRegistry&);
	void initializeDomOnlyViewerPass(PassRegistry&);	void initializeDomOnlyViewerPass(PassRegistry&);
	void initializeDomPrinterPass(PassRegistry&);	void initializeDomPrinterPass(PassRegistry&);
	void initializeDomViewerPass(PassRegistry&);	void initializeDomViewerPass(PassRegistry&);
	void initializeDominanceFrontierPass(PassRegistry&);	void initializeDominanceFrontierPass(PassRegistry&);
	void initializeDominatorTreePass(PassRegistry&);	void initializeDominatorTreePass(PassRegistry&);
	void initializeEdgeBundlesPass(PassRegistry&);	void initializeEdgeBundlesPass(PassRegistry&);
	void initializeEdgeProfilerPass(PassRegistry&);	void initializeEdgeProfilerPass(PassRegistry&);

		void initializeExpandPostRAPass(PassRegistry&);
	void initializePathProfilerPass(PassRegistry&);	void initializePathProfilerPass(PassRegistry&);
	void initializeGCOVProfilerPass(PassRegistry&);	void initializeGCOVProfilerPass(PassRegistry&);

		void initializeAddressSanitizerPass(PassRegistry&);
		void initializeThreadSanitizerPass(PassRegistry&);
	void initializeEarlyCSEPass(PassRegistry&);	void initializeEarlyCSEPass(PassRegistry&);
	void initializeExpandISelPseudosPass(PassRegistry&);	void initializeExpandISelPseudosPass(PassRegistry&);
	void initializeFindUsedTypesPass(PassRegistry&);	void initializeFindUsedTypesPass(PassRegistry&);
	void initializeFunctionAttrsPass(PassRegistry&);	void initializeFunctionAttrsPass(PassRegistry&);

		void initializeGCInfoDeleterPass(PassRegistry&);
		void initializeGCMachineCodeAnalysisPass(PassRegistry&);
	void initializeGCModuleInfoPass(PassRegistry&);	void initializeGCModuleInfoPass(PassRegistry&);
	void initializeGVNPass(PassRegistry&);	void initializeGVNPass(PassRegistry&);
	void initializeGlobalDCEPass(PassRegistry&);	void initializeGlobalDCEPass(PassRegistry&);
	void initializeGlobalOptPass(PassRegistry&);	void initializeGlobalOptPass(PassRegistry&);
	void initializeGlobalsModRefPass(PassRegistry&);	void initializeGlobalsModRefPass(PassRegistry&);
	void initializeIPCPPass(PassRegistry&);	void initializeIPCPPass(PassRegistry&);
	void initializeIPSCCPPass(PassRegistry&);	void initializeIPSCCPPass(PassRegistry&);
	void initializeIVUsersPass(PassRegistry&);	void initializeIVUsersPass(PassRegistry&);
	void initializeIfConverterPass(PassRegistry&);	void initializeIfConverterPass(PassRegistry&);
	void initializeIndVarSimplifyPass(PassRegistry&);	void initializeIndVarSimplifyPass(PassRegistry&);

	skipping to change at line 130	skipping to change at line 142
	void initializeLICMPass(PassRegistry&);	void initializeLICMPass(PassRegistry&);
	void initializeLazyValueInfoPass(PassRegistry&);	void initializeLazyValueInfoPass(PassRegistry&);
	void initializeLibCallAliasAnalysisPass(PassRegistry&);	void initializeLibCallAliasAnalysisPass(PassRegistry&);
	void initializeLintPass(PassRegistry&);	void initializeLintPass(PassRegistry&);
	void initializeLiveDebugVariablesPass(PassRegistry&);	void initializeLiveDebugVariablesPass(PassRegistry&);
	void initializeLiveIntervalsPass(PassRegistry&);	void initializeLiveIntervalsPass(PassRegistry&);
	void initializeLiveStacksPass(PassRegistry&);	void initializeLiveStacksPass(PassRegistry&);
	void initializeLiveVariablesPass(PassRegistry&);	void initializeLiveVariablesPass(PassRegistry&);
	void initializeLoaderPassPass(PassRegistry&);	void initializeLoaderPassPass(PassRegistry&);
	void initializePathProfileLoaderPassPass(PassRegistry&);	void initializePathProfileLoaderPassPass(PassRegistry&);

		void initializeLocalStackSlotPassPass(PassRegistry&);
	void initializeLoopDeletionPass(PassRegistry&);	void initializeLoopDeletionPass(PassRegistry&);
	void initializeLoopDependenceAnalysisPass(PassRegistry&);	void initializeLoopDependenceAnalysisPass(PassRegistry&);
	void initializeLoopExtractorPass(PassRegistry&);	void initializeLoopExtractorPass(PassRegistry&);
	void initializeLoopInfoPass(PassRegistry&);	void initializeLoopInfoPass(PassRegistry&);
	void initializeLoopInstSimplifyPass(PassRegistry&);	void initializeLoopInstSimplifyPass(PassRegistry&);
	void initializeLoopRotatePass(PassRegistry&);	void initializeLoopRotatePass(PassRegistry&);
	void initializeLoopSimplifyPass(PassRegistry&);	void initializeLoopSimplifyPass(PassRegistry&);

	void initializeLoopSplitterPass(PassRegistry&);
	void initializeLoopStrengthReducePass(PassRegistry&);	void initializeLoopStrengthReducePass(PassRegistry&);

		void initializeGlobalMergePass(PassRegistry&);
	void initializeLoopUnrollPass(PassRegistry&);	void initializeLoopUnrollPass(PassRegistry&);
	void initializeLoopUnswitchPass(PassRegistry&);	void initializeLoopUnswitchPass(PassRegistry&);
	void initializeLoopIdiomRecognizePass(PassRegistry&);	void initializeLoopIdiomRecognizePass(PassRegistry&);
	void initializeLowerAtomicPass(PassRegistry&);	void initializeLowerAtomicPass(PassRegistry&);
	void initializeLowerExpectIntrinsicPass(PassRegistry&);	void initializeLowerExpectIntrinsicPass(PassRegistry&);
	void initializeLowerIntrinsicsPass(PassRegistry&);	void initializeLowerIntrinsicsPass(PassRegistry&);
	void initializeLowerInvokePass(PassRegistry&);	void initializeLowerInvokePass(PassRegistry&);
	void initializeLowerSwitchPass(PassRegistry&);	void initializeLowerSwitchPass(PassRegistry&);
	void initializeMachineBlockFrequencyInfoPass(PassRegistry&);	void initializeMachineBlockFrequencyInfoPass(PassRegistry&);

		void initializeMachineBlockPlacementPass(PassRegistry&);
		void initializeMachineBlockPlacementStatsPass(PassRegistry&);
	void initializeMachineBranchProbabilityInfoPass(PassRegistry&);	void initializeMachineBranchProbabilityInfoPass(PassRegistry&);
	void initializeMachineCSEPass(PassRegistry&);	void initializeMachineCSEPass(PassRegistry&);
	void initializeMachineDominatorTreePass(PassRegistry&);	void initializeMachineDominatorTreePass(PassRegistry&);
	void initializeMachineLICMPass(PassRegistry&);	void initializeMachineLICMPass(PassRegistry&);
	void initializeMachineLoopInfoPass(PassRegistry&);	void initializeMachineLoopInfoPass(PassRegistry&);
	void initializeMachineLoopRangesPass(PassRegistry&);	void initializeMachineLoopRangesPass(PassRegistry&);
	void initializeMachineModuleInfoPass(PassRegistry&);	void initializeMachineModuleInfoPass(PassRegistry&);

		void initializeMachineSchedulerPass(PassRegistry&);
	void initializeMachineSinkingPass(PassRegistry&);	void initializeMachineSinkingPass(PassRegistry&);
	void initializeMachineVerifierPassPass(PassRegistry&);	void initializeMachineVerifierPassPass(PassRegistry&);
	void initializeMemCpyOptPass(PassRegistry&);	void initializeMemCpyOptPass(PassRegistry&);
	void initializeMemDepPrinterPass(PassRegistry&);	void initializeMemDepPrinterPass(PassRegistry&);
	void initializeMemoryDependenceAnalysisPass(PassRegistry&);	void initializeMemoryDependenceAnalysisPass(PassRegistry&);
	void initializeMergeFunctionsPass(PassRegistry&);	void initializeMergeFunctionsPass(PassRegistry&);
	void initializeModuleDebugInfoPrinterPass(PassRegistry&);	void initializeModuleDebugInfoPrinterPass(PassRegistry&);
	void initializeNoAAPass(PassRegistry&);	void initializeNoAAPass(PassRegistry&);
	void initializeNoProfileInfoPass(PassRegistry&);	void initializeNoProfileInfoPass(PassRegistry&);
	void initializeNoPathProfileInfoPass(PassRegistry&);	void initializeNoPathProfileInfoPass(PassRegistry&);
	void initializeObjCARCAliasAnalysisPass(PassRegistry&);	void initializeObjCARCAliasAnalysisPass(PassRegistry&);

		void initializeObjCARCAPElimPass(PassRegistry&);
	void initializeObjCARCExpandPass(PassRegistry&);	void initializeObjCARCExpandPass(PassRegistry&);
	void initializeObjCARCContractPass(PassRegistry&);	void initializeObjCARCContractPass(PassRegistry&);
	void initializeObjCARCOptPass(PassRegistry&);	void initializeObjCARCOptPass(PassRegistry&);
	void initializeOptimalEdgeProfilerPass(PassRegistry&);	void initializeOptimalEdgeProfilerPass(PassRegistry&);
	void initializeOptimizePHIsPass(PassRegistry&);	void initializeOptimizePHIsPass(PassRegistry&);
	void initializePEIPass(PassRegistry&);	void initializePEIPass(PassRegistry&);
	void initializePHIEliminationPass(PassRegistry&);	void initializePHIEliminationPass(PassRegistry&);
	void initializePartialInlinerPass(PassRegistry&);	void initializePartialInlinerPass(PassRegistry&);
	void initializePeepholeOptimizerPass(PassRegistry&);	void initializePeepholeOptimizerPass(PassRegistry&);
	void initializePostDomOnlyPrinterPass(PassRegistry&);	void initializePostDomOnlyPrinterPass(PassRegistry&);
	void initializePostDomOnlyViewerPass(PassRegistry&);	void initializePostDomOnlyViewerPass(PassRegistry&);
	void initializePostDomPrinterPass(PassRegistry&);	void initializePostDomPrinterPass(PassRegistry&);
	void initializePostDomViewerPass(PassRegistry&);	void initializePostDomViewerPass(PassRegistry&);
	void initializePostDominatorTreePass(PassRegistry&);	void initializePostDominatorTreePass(PassRegistry&);

		void initializePostRASchedulerPass(PassRegistry&);
	void initializePreVerifierPass(PassRegistry&);	void initializePreVerifierPass(PassRegistry&);
	void initializePrintDbgInfoPass(PassRegistry&);	void initializePrintDbgInfoPass(PassRegistry&);
	void initializePrintFunctionPassPass(PassRegistry&);	void initializePrintFunctionPassPass(PassRegistry&);
	void initializePrintModulePassPass(PassRegistry&);	void initializePrintModulePassPass(PassRegistry&);
	void initializeProcessImplicitDefsPass(PassRegistry&);	void initializeProcessImplicitDefsPass(PassRegistry&);
	void initializeProfileEstimatorPassPass(PassRegistry&);	void initializeProfileEstimatorPassPass(PassRegistry&);
	void initializeProfileInfoAnalysisGroup(PassRegistry&);	void initializeProfileInfoAnalysisGroup(PassRegistry&);
	void initializePathProfileInfoAnalysisGroup(PassRegistry&);	void initializePathProfileInfoAnalysisGroup(PassRegistry&);
	void initializePathProfileVerifierPass(PassRegistry&);	void initializePathProfileVerifierPass(PassRegistry&);
	void initializeProfileVerifierPassPass(PassRegistry&);	void initializeProfileVerifierPassPass(PassRegistry&);
	void initializePromotePassPass(PassRegistry&);	void initializePromotePassPass(PassRegistry&);
	void initializePruneEHPass(PassRegistry&);	void initializePruneEHPass(PassRegistry&);

	void initializeRALinScanPass(PassRegistry&);
	void initializeReassociatePass(PassRegistry&);	void initializeReassociatePass(PassRegistry&);
	void initializeRegToMemPass(PassRegistry&);	void initializeRegToMemPass(PassRegistry&);
	void initializeRegionInfoPass(PassRegistry&);	void initializeRegionInfoPass(PassRegistry&);
	void initializeRegionOnlyPrinterPass(PassRegistry&);	void initializeRegionOnlyPrinterPass(PassRegistry&);
	void initializeRegionOnlyViewerPass(PassRegistry&);	void initializeRegionOnlyViewerPass(PassRegistry&);
	void initializeRegionPrinterPass(PassRegistry&);	void initializeRegionPrinterPass(PassRegistry&);
	void initializeRegionViewerPass(PassRegistry&);	void initializeRegionViewerPass(PassRegistry&);
	void initializeRenderMachineFunctionPass(PassRegistry&);	void initializeRenderMachineFunctionPass(PassRegistry&);
	void initializeSCCPPass(PassRegistry&);	void initializeSCCPPass(PassRegistry&);
	void initializeSROA_DTPass(PassRegistry&);	void initializeSROA_DTPass(PassRegistry&);

	skipping to change at line 222	skipping to change at line 239
	void initializeSpillPlacementPass(PassRegistry&);	void initializeSpillPlacementPass(PassRegistry&);
	void initializeStackProtectorPass(PassRegistry&);	void initializeStackProtectorPass(PassRegistry&);
	void initializeStackSlotColoringPass(PassRegistry&);	void initializeStackSlotColoringPass(PassRegistry&);
	void initializeStripDeadDebugInfoPass(PassRegistry&);	void initializeStripDeadDebugInfoPass(PassRegistry&);
	void initializeStripDeadPrototypesPassPass(PassRegistry&);	void initializeStripDeadPrototypesPassPass(PassRegistry&);
	void initializeStripDebugDeclarePass(PassRegistry&);	void initializeStripDebugDeclarePass(PassRegistry&);
	void initializeStripNonDebugSymbolsPass(PassRegistry&);	void initializeStripNonDebugSymbolsPass(PassRegistry&);
	void initializeStripSymbolsPass(PassRegistry&);	void initializeStripSymbolsPass(PassRegistry&);
	void initializeStrongPHIEliminationPass(PassRegistry&);	void initializeStrongPHIEliminationPass(PassRegistry&);
	void initializeTailCallElimPass(PassRegistry&);	void initializeTailCallElimPass(PassRegistry&);

		void initializeTailDuplicatePassPass(PassRegistry&);
		void initializeTargetPassConfigPass(PassRegistry&);
	void initializeTargetDataPass(PassRegistry&);	void initializeTargetDataPass(PassRegistry&);
	void initializeTargetLibraryInfoPass(PassRegistry&);	void initializeTargetLibraryInfoPass(PassRegistry&);
	void initializeTwoAddressInstructionPassPass(PassRegistry&);	void initializeTwoAddressInstructionPassPass(PassRegistry&);
	void initializeTypeBasedAliasAnalysisPass(PassRegistry&);	void initializeTypeBasedAliasAnalysisPass(PassRegistry&);
	void initializeUnifyFunctionExitNodesPass(PassRegistry&);	void initializeUnifyFunctionExitNodesPass(PassRegistry&);
	void initializeUnreachableBlockElimPass(PassRegistry&);	void initializeUnreachableBlockElimPass(PassRegistry&);
	void initializeUnreachableMachineBlockElimPass(PassRegistry&);	void initializeUnreachableMachineBlockElimPass(PassRegistry&);
	void initializeVerifierPass(PassRegistry&);	void initializeVerifierPass(PassRegistry&);
	void initializeVirtRegMapPass(PassRegistry&);	void initializeVirtRegMapPass(PassRegistry&);
	void initializeInstSimplifierPass(PassRegistry&);	void initializeInstSimplifierPass(PassRegistry&);

		void initializeUnpackMachineBundlesPass(PassRegistry&);
		void initializeFinalizeMachineBundlesPass(PassRegistry&);
		void initializeBBVectorizePass(PassRegistry&);
	}	}

	#endif	#endif

End of changes. 17 change blocks.
	3 lines changed or deleted	24 lines changed or added

	InstrTypes.h	InstrTypes.h

	skipping to change at line 390	skipping to change at line 390
	// CastInst Class	// CastInst Class
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	/// CastInst - This is the base class for all instructions that perform dat a	/// CastInst - This is the base class for all instructions that perform dat a
	/// casts. It is simply provided so that instruction category testing	/// casts. It is simply provided so that instruction category testing
	/// can be performed with code like:	/// can be performed with code like:
	///	///
	/// if (isa<CastInst>(Instr)) { ... }	/// if (isa<CastInst>(Instr)) { ... }
	/// @brief Base class of casting instructions.	/// @brief Base class of casting instructions.
	class CastInst : public UnaryInstruction {	class CastInst : public UnaryInstruction {

		virtual void anchor();
	protected:	protected:
	/// @brief Constructor with insert-before-instruction semantics for subcl asses	/// @brief Constructor with insert-before-instruction semantics for subcl asses
	CastInst(Type Ty, unsigned iType, Value S,	CastInst(Type Ty, unsigned iType, Value S,
	const Twine &NameStr = "", Instruction *InsertBefore = 0)	const Twine &NameStr = "", Instruction *InsertBefore = 0)
	: UnaryInstruction(Ty, iType, S, InsertBefore) {	: UnaryInstruction(Ty, iType, S, InsertBefore) {
	setName(NameStr);	setName(NameStr);
	}	}
	/// @brief Constructor with insert-at-end-of-block semantics for subclass es	/// @brief Constructor with insert-at-end-of-block semantics for subclass es
	CastInst(Type Ty, unsigned iType, Value S,	CastInst(Type Ty, unsigned iType, Value S,
	const Twine &NameStr, BasicBlock *InsertAtEnd)	const Twine &NameStr, BasicBlock *InsertAtEnd)

End of changes. 1 change blocks.
	0 lines changed or deleted	1 lines changed or added

	Intrinsics.td	Intrinsics.td

	skipping to change at line 285	skipping to change at line 285
	def int_expect : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>,	def int_expect : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>,
	LLVMMatchType<0>], [IntrNoMem ]>;	LLVMMatchType<0>], [IntrNoMem ]>;

	//===-------------------- Bit Manipulation Intrinsics --------------------- ===//	//===-------------------- Bit Manipulation Intrinsics --------------------- ===//
	//	//

	// None of these intrinsics accesses memory at all.	// None of these intrinsics accesses memory at all.
	let Properties = [IntrNoMem] in {	let Properties = [IntrNoMem] in {
	def int_bswap: Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>]>;	def int_bswap: Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>]>;
	def int_ctpop: Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>]>;	def int_ctpop: Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>]>;

	def int_ctlz : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>]>;	def int_ctlz : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, llvm_i1_ty]
	def int_cttz : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>]>;	>;
		def int_cttz : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, llvm_i1_ty]
		>;
	}	}

	//===------------------------ Debugger Intrinsics ------------------------- ===//	//===------------------------ Debugger Intrinsics ------------------------- ===//
	//	//

	// None of these intrinsics accesses memory at all...but that doesn't mean the	// None of these intrinsics accesses memory at all...but that doesn't mean the
	// optimizers can change them aggressively. Special handling needed in a f ew	// optimizers can change them aggressively. Special handling needed in a f ew
	// places.	// places.
	let Properties = [IntrNoMem] in {	let Properties = [IntrNoMem] in {
	def int_dbg_declare : Intrinsic<[],	def int_dbg_declare : Intrinsic<[],
	[llvm_metadata_ty, llvm_metadata_ty] >;	[llvm_metadata_ty, llvm_metadata_ty] >;
	def int_dbg_value : Intrinsic<[],	def int_dbg_value : Intrinsic<[],
	[llvm_metadata_ty, llvm_i64_ty,	[llvm_metadata_ty, llvm_i64_ty,
	llvm_metadata_ty]>;	llvm_metadata_ty]>;
	}	}

	//===------------------ Exception Handling Intrinsics---------------------- ===//	//===------------------ Exception Handling Intrinsics---------------------- ===//
	//	//

	def int_eh_exception : Intrinsic<[llvm_ptr_ty], [], [IntrReadMem]>;
	def int_eh_selector : Intrinsic<[llvm_i32_ty],
	[llvm_ptr_ty, llvm_ptr_ty, llvm_vararg_ty]
	>;
	def int_eh_resume : Intrinsic<[], [llvm_ptr_ty, llvm_i32_ty], [Throws]>;

	// The result of eh.typeid.for depends on the enclosing function, but insid e a	// The result of eh.typeid.for depends on the enclosing function, but insid e a
	// given function it is 'const' and may be CSE'd etc.	// given function it is 'const' and may be CSE'd etc.
	def int_eh_typeid_for : Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrNoMem] >;	def int_eh_typeid_for : Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrNoMem] >;

	def int_eh_return_i32 : Intrinsic<[], [llvm_i32_ty, llvm_ptr_ty]>;	def int_eh_return_i32 : Intrinsic<[], [llvm_i32_ty, llvm_ptr_ty]>;
	def int_eh_return_i64 : Intrinsic<[], [llvm_i64_ty, llvm_ptr_ty]>;	def int_eh_return_i64 : Intrinsic<[], [llvm_i64_ty, llvm_ptr_ty]>;

	def int_eh_unwind_init: Intrinsic<[]>,	def int_eh_unwind_init: Intrinsic<[]>,
	GCCBuiltin<"__builtin_unwind_init">;	GCCBuiltin<"__builtin_unwind_init">;

	def int_eh_dwarf_cfa : Intrinsic<[llvm_ptr_ty], [llvm_i32_ty]>;	def int_eh_dwarf_cfa : Intrinsic<[llvm_ptr_ty], [llvm_i32_ty]>;

	let Properties = [IntrNoMem] in {	let Properties = [IntrNoMem] in {
	def int_eh_sjlj_lsda : Intrinsic<[llvm_ptr_ty]>;	def int_eh_sjlj_lsda : Intrinsic<[llvm_ptr_ty]>;
	def int_eh_sjlj_callsite : Intrinsic<[], [llvm_i32_ty]>;	def int_eh_sjlj_callsite : Intrinsic<[], [llvm_i32_ty]>;
	}	}
	def int_eh_sjlj_functioncontext : Intrinsic<[], [llvm_ptr_ty]>;	def int_eh_sjlj_functioncontext : Intrinsic<[], [llvm_ptr_ty]>;

	def int_eh_sjlj_dispatch_setup : Intrinsic<[], [llvm_i32_ty]>;
	def int_eh_sjlj_setjmp : Intrinsic<[llvm_i32_ty], [llvm_ptr_ty]>;	def int_eh_sjlj_setjmp : Intrinsic<[llvm_i32_ty], [llvm_ptr_ty]>;
	def int_eh_sjlj_longjmp : Intrinsic<[], [llvm_ptr_ty]>;	def int_eh_sjlj_longjmp : Intrinsic<[], [llvm_ptr_ty]>;

	//===---------------- Generic Variable Attribute Intrinsics---------------- ===//	//===---------------- Generic Variable Attribute Intrinsics---------------- ===//
	//	//
	def int_var_annotation : Intrinsic<[],	def int_var_annotation : Intrinsic<[],
	[llvm_ptr_ty, llvm_ptr_ty,	[llvm_ptr_ty, llvm_ptr_ty,
	llvm_ptr_ty, llvm_i32_ty],	llvm_ptr_ty, llvm_i32_ty],
	[], "llvm.var.annotation">;	[], "llvm.var.annotation">;
	def int_ptr_annotation : Intrinsic<[LLVMAnyPointerType<llvm_anyint_ty>],	def int_ptr_annotation : Intrinsic<[LLVMAnyPointerType<llvm_anyint_ty>],

	skipping to change at line 444	skipping to change at line 439
	[llvm_anyint_ty, llvm_i32_ty, llvm_i32_ty]>;	[llvm_anyint_ty, llvm_i32_ty, llvm_i32_ty]>;

	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	// Target-specific intrinsics	// Target-specific intrinsics
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	include "llvm/IntrinsicsPowerPC.td"	include "llvm/IntrinsicsPowerPC.td"
	include "llvm/IntrinsicsX86.td"	include "llvm/IntrinsicsX86.td"
	include "llvm/IntrinsicsARM.td"	include "llvm/IntrinsicsARM.td"
	include "llvm/IntrinsicsCellSPU.td"	include "llvm/IntrinsicsCellSPU.td"

	include "llvm/IntrinsicsAlpha.td"
	include "llvm/IntrinsicsXCore.td"	include "llvm/IntrinsicsXCore.td"
	include "llvm/IntrinsicsPTX.td"	include "llvm/IntrinsicsPTX.td"

		include "llvm/IntrinsicsHexagon.td"

End of changes. 5 change blocks.
	9 lines changed or deleted	4 lines changed or added

	LinkAllPasses.h	LinkAllPasses.h

	skipping to change at line 34	skipping to change at line 34
	#include "llvm/Analysis/RegionPass.h"	#include "llvm/Analysis/RegionPass.h"
	#include "llvm/Analysis/RegionPrinter.h"	#include "llvm/Analysis/RegionPrinter.h"
	#include "llvm/Analysis/ScalarEvolution.h"	#include "llvm/Analysis/ScalarEvolution.h"
	#include "llvm/Analysis/Lint.h"	#include "llvm/Analysis/Lint.h"
	#include "llvm/Assembly/PrintModulePass.h"	#include "llvm/Assembly/PrintModulePass.h"
	#include "llvm/CodeGen/Passes.h"	#include "llvm/CodeGen/Passes.h"
	#include "llvm/Function.h"	#include "llvm/Function.h"
	#include "llvm/Transforms/Instrumentation.h"	#include "llvm/Transforms/Instrumentation.h"
	#include "llvm/Transforms/IPO.h"	#include "llvm/Transforms/IPO.h"
	#include "llvm/Transforms/Scalar.h"	#include "llvm/Transforms/Scalar.h"

		#include "llvm/Transforms/Vectorize.h"
	#include "llvm/Transforms/Utils/UnifyFunctionExitNodes.h"	#include "llvm/Transforms/Utils/UnifyFunctionExitNodes.h"
	#include <cstdlib>	#include <cstdlib>

	namespace {	namespace {
	struct ForcePassLinking {	struct ForcePassLinking {
	ForcePassLinking() {	ForcePassLinking() {
	// We must reference the passes in such a way that compilers will not	// We must reference the passes in such a way that compilers will not
	// delete it all as dead code, even with whole program optimization,	// delete it all as dead code, even with whole program optimization,
	// yet is effectively a NO-OP. As the compiler isn't smart enough	// yet is effectively a NO-OP. As the compiler isn't smart enough
	// to know that getenv() never returns -1, this will do the job.	// to know that getenv() never returns -1, this will do the job.

	skipping to change at line 72	skipping to change at line 73
	(void) llvm::createDeadCodeEliminationPass();	(void) llvm::createDeadCodeEliminationPass();
	(void) llvm::createDeadInstEliminationPass();	(void) llvm::createDeadInstEliminationPass();
	(void) llvm::createDeadStoreEliminationPass();	(void) llvm::createDeadStoreEliminationPass();
	(void) llvm::createDomOnlyPrinterPass();	(void) llvm::createDomOnlyPrinterPass();
	(void) llvm::createDomPrinterPass();	(void) llvm::createDomPrinterPass();
	(void) llvm::createDomOnlyViewerPass();	(void) llvm::createDomOnlyViewerPass();
	(void) llvm::createDomViewerPass();	(void) llvm::createDomViewerPass();
	(void) llvm::createEdgeProfilerPass();	(void) llvm::createEdgeProfilerPass();
	(void) llvm::createOptimalEdgeProfilerPass();	(void) llvm::createOptimalEdgeProfilerPass();
	(void) llvm::createPathProfilerPass();	(void) llvm::createPathProfilerPass();

	(void) llvm::createGCOVProfilerPass(true, true, false);	(void) llvm::createGCOVProfilerPass();
	(void) llvm::createFunctionInliningPass();	(void) llvm::createFunctionInliningPass();
	(void) llvm::createAlwaysInlinerPass();	(void) llvm::createAlwaysInlinerPass();
	(void) llvm::createGlobalDCEPass();	(void) llvm::createGlobalDCEPass();
	(void) llvm::createGlobalOptimizerPass();	(void) llvm::createGlobalOptimizerPass();
	(void) llvm::createGlobalsModRefPass();	(void) llvm::createGlobalsModRefPass();
	(void) llvm::createIPConstantPropagationPass();	(void) llvm::createIPConstantPropagationPass();
	(void) llvm::createIPSCCPPass();	(void) llvm::createIPSCCPPass();
	(void) llvm::createIndVarSimplifyPass();	(void) llvm::createIndVarSimplifyPass();
	(void) llvm::createInstructionCombiningPass();	(void) llvm::createInstructionCombiningPass();
	(void) llvm::createInternalizePass(false);	(void) llvm::createInternalizePass(false);

	skipping to change at line 100	skipping to change at line 101
	(void) llvm::createLoopUnrollPass();	(void) llvm::createLoopUnrollPass();
	(void) llvm::createLoopUnswitchPass();	(void) llvm::createLoopUnswitchPass();
	(void) llvm::createLoopIdiomPass();	(void) llvm::createLoopIdiomPass();
	(void) llvm::createLoopRotatePass();	(void) llvm::createLoopRotatePass();
	(void) llvm::createLowerExpectIntrinsicPass();	(void) llvm::createLowerExpectIntrinsicPass();
	(void) llvm::createLowerInvokePass();	(void) llvm::createLowerInvokePass();
	(void) llvm::createLowerSwitchPass();	(void) llvm::createLowerSwitchPass();
	(void) llvm::createNoAAPass();	(void) llvm::createNoAAPass();
	(void) llvm::createNoProfileInfoPass();	(void) llvm::createNoProfileInfoPass();
	(void) llvm::createObjCARCAliasAnalysisPass();	(void) llvm::createObjCARCAliasAnalysisPass();

		(void) llvm::createObjCARCAPElimPass();
	(void) llvm::createObjCARCExpandPass();	(void) llvm::createObjCARCExpandPass();
	(void) llvm::createObjCARCContractPass();	(void) llvm::createObjCARCContractPass();
	(void) llvm::createObjCARCOptPass();	(void) llvm::createObjCARCOptPass();
	(void) llvm::createProfileEstimatorPass();	(void) llvm::createProfileEstimatorPass();
	(void) llvm::createProfileVerifierPass();	(void) llvm::createProfileVerifierPass();
	(void) llvm::createPathProfileVerifierPass();	(void) llvm::createPathProfileVerifierPass();
	(void) llvm::createProfileLoaderPass();	(void) llvm::createProfileLoaderPass();
	(void) llvm::createPathProfileLoaderPass();	(void) llvm::createPathProfileLoaderPass();
	(void) llvm::createPromoteMemoryToRegisterPass();	(void) llvm::createPromoteMemoryToRegisterPass();
	(void) llvm::createDemoteRegisterToMemoryPass();	(void) llvm::createDemoteRegisterToMemoryPass();

	skipping to change at line 153	skipping to change at line 155
	(void) llvm::createPrintFunctionPass("", 0);	(void) llvm::createPrintFunctionPass("", 0);
	(void) llvm::createDbgInfoPrinterPass();	(void) llvm::createDbgInfoPrinterPass();
	(void) llvm::createModuleDebugInfoPrinterPass();	(void) llvm::createModuleDebugInfoPrinterPass();
	(void) llvm::createPartialInliningPass();	(void) llvm::createPartialInliningPass();
	(void) llvm::createLintPass();	(void) llvm::createLintPass();
	(void) llvm::createSinkingPass();	(void) llvm::createSinkingPass();
	(void) llvm::createLowerAtomicPass();	(void) llvm::createLowerAtomicPass();
	(void) llvm::createCorrelatedValuePropagationPass();	(void) llvm::createCorrelatedValuePropagationPass();
	(void) llvm::createMemDepPrinter();	(void) llvm::createMemDepPrinter();
	(void) llvm::createInstructionSimplifierPass();	(void) llvm::createInstructionSimplifierPass();

		(void) llvm::createBBVectorizePass();

	(void)new llvm::IntervalPartition();	(void)new llvm::IntervalPartition();
	(void)new llvm::FindUsedTypes();	(void)new llvm::FindUsedTypes();
	(void)new llvm::ScalarEvolution();	(void)new llvm::ScalarEvolution();
	((llvm::Function*)0)->viewCFGOnly();	((llvm::Function*)0)->viewCFGOnly();
	llvm::RGPassManager RGM;	llvm::RGPassManager RGM;
	((llvm::RegionPass)0)->runOnRegion((llvm::Region)0, RGM);	((llvm::RegionPass)0)->runOnRegion((llvm::Region)0, RGM);
	llvm::AliasSetTracker X((llvm::AliasAnalysis)0);	llvm::AliasSetTracker X((llvm::AliasAnalysis)0);
	X.add((llvm::Value*)0, 0, 0); // for -print-alias-sets	X.add((llvm::Value*)0, 0, 0); // for -print-alias-sets
	}	}

End of changes. 4 change blocks.
	1 lines changed or deleted	4 lines changed or added

	LiveVariables.h	LiveVariables.h

	skipping to change at line 88	skipping to change at line 88
	/// not live across any blocks) and Kills is empty (phi nodes are not	/// not live across any blocks) and Kills is empty (phi nodes are not
	/// included). This is sensical because the value must be live to the end of	/// included). This is sensical because the value must be live to the end of
	/// the block, but is not live in any successor blocks.	/// the block, but is not live in any successor blocks.
	struct VarInfo {	struct VarInfo {
	/// AliveBlocks - Set of blocks in which this value is alive completely	/// AliveBlocks - Set of blocks in which this value is alive completely
	/// through. This is a bit set which uses the basic block number as an	/// through. This is a bit set which uses the basic block number as an
	/// index.	/// index.
	///	///
	SparseBitVector<> AliveBlocks;	SparseBitVector<> AliveBlocks;


	/// NumUses - Number of uses of this register across the entire functio
	n.
	///
	unsigned NumUses;

	/// Kills - List of MachineInstruction's which are the last use of this	/// Kills - List of MachineInstruction's which are the last use of this
	/// virtual register (kill it) in their basic block.	/// virtual register (kill it) in their basic block.
	///	///
	std::vector<MachineInstr*> Kills;	std::vector<MachineInstr*> Kills;


	VarInfo() : NumUses(0) {}

	/// removeKill - Delete a kill corresponding to the specified	/// removeKill - Delete a kill corresponding to the specified
	/// machine instruction. Returns true if there was a kill	/// machine instruction. Returns true if there was a kill
	/// corresponding to this instruction, false otherwise.	/// corresponding to this instruction, false otherwise.
	bool removeKill(MachineInstr *MI) {	bool removeKill(MachineInstr *MI) {
	std::vector<MachineInstr*>::iterator	std::vector<MachineInstr*>::iterator
	I = std::find(Kills.begin(), Kills.end(), MI);	I = std::find(Kills.begin(), Kills.end(), MI);
	if (I == Kills.end())	if (I == Kills.end())
	return false;	return false;
	Kills.erase(I);	Kills.erase(I);
	return true;	return true;

	skipping to change at line 169	skipping to change at line 163

	// DistanceMap - Keep track the distance of a MI from the start of the	// DistanceMap - Keep track the distance of a MI from the start of the
	// current basic block.	// current basic block.
	DenseMap<MachineInstr*, unsigned> DistanceMap;	DenseMap<MachineInstr*, unsigned> DistanceMap;

	/// HandlePhysRegKill - Add kills of Reg and its sub-registers to the	/// HandlePhysRegKill - Add kills of Reg and its sub-registers to the
	/// uses. Pay special attention to the sub-register uses which may come b elow	/// uses. Pay special attention to the sub-register uses which may come b elow
	/// the last use of the whole register.	/// the last use of the whole register.
	bool HandlePhysRegKill(unsigned Reg, MachineInstr *MI);	bool HandlePhysRegKill(unsigned Reg, MachineInstr *MI);


		/// HandleRegMask - Call HandlePhysRegKill for all registers clobbered by
		Mask.
		void HandleRegMask(const MachineOperand&);

	void HandlePhysRegUse(unsigned Reg, MachineInstr *MI);	void HandlePhysRegUse(unsigned Reg, MachineInstr *MI);
	void HandlePhysRegDef(unsigned Reg, MachineInstr *MI,	void HandlePhysRegDef(unsigned Reg, MachineInstr *MI,
	SmallVector<unsigned, 4> &Defs);	SmallVector<unsigned, 4> &Defs);
	void UpdatePhysRegDefs(MachineInstr *MI, SmallVector<unsigned, 4> &Defs);	void UpdatePhysRegDefs(MachineInstr *MI, SmallVector<unsigned, 4> &Defs);

	/// FindLastRefOrPartRef - Return the last reference or partial reference of	/// FindLastRefOrPartRef - Return the last reference or partial reference of
	/// the specified register.	/// the specified register.
	MachineInstr *FindLastRefOrPartRef(unsigned Reg);	MachineInstr *FindLastRefOrPartRef(unsigned Reg);

	/// FindLastPartialDef - Return the last partial def of the specified	/// FindLastPartialDef - Return the last partial def of the specified

End of changes. 3 change blocks.
	7 lines changed or deleted	4 lines changed or added

	MachineFrameInfo.h	MachineFrameInfo.h

	skipping to change at line 467	skipping to change at line 467
	assert(unsigned(ObjectIdx+NumFixedObjects) < Objects.size() &&	assert(unsigned(ObjectIdx+NumFixedObjects) < Objects.size() &&
	"Invalid Object Idx!");	"Invalid Object Idx!");
	return Objects[ObjectIdx+NumFixedObjects].isImmutable;	return Objects[ObjectIdx+NumFixedObjects].isImmutable;
	}	}

	/// isSpillSlotObjectIndex - Returns true if the specified index correspo nds	/// isSpillSlotObjectIndex - Returns true if the specified index correspo nds
	/// to a spill slot..	/// to a spill slot..
	bool isSpillSlotObjectIndex(int ObjectIdx) const {	bool isSpillSlotObjectIndex(int ObjectIdx) const {
	assert(unsigned(ObjectIdx+NumFixedObjects) < Objects.size() &&	assert(unsigned(ObjectIdx+NumFixedObjects) < Objects.size() &&
	"Invalid Object Idx!");	"Invalid Object Idx!");

	return Objects[ObjectIdx+NumFixedObjects].isSpillSlot;;	return Objects[ObjectIdx+NumFixedObjects].isSpillSlot;
	}	}

	/// isDeadObjectIndex - Returns true if the specified index corresponds t o	/// isDeadObjectIndex - Returns true if the specified index corresponds t o
	/// a dead object.	/// a dead object.
	bool isDeadObjectIndex(int ObjectIdx) const {	bool isDeadObjectIndex(int ObjectIdx) const {
	assert(unsigned(ObjectIdx+NumFixedObjects) < Objects.size() &&	assert(unsigned(ObjectIdx+NumFixedObjects) < Objects.size() &&
	"Invalid Object Idx!");	"Invalid Object Idx!");
	return Objects[ObjectIdx+NumFixedObjects].Size == ~0ULL;	return Objects[ObjectIdx+NumFixedObjects].Size == ~0ULL;
	}	}


End of changes. 1 change blocks.
	1 lines changed or deleted	1 lines changed or added

	MachinePassRegistry.h	MachinePassRegistry.h

	skipping to change at line 35	skipping to change at line 35

	typedef void (MachinePassCtor)();	typedef void (MachinePassCtor)();

	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	///	///
	/// MachinePassRegistryListener - Listener to adds and removals of nodes in	/// MachinePassRegistryListener - Listener to adds and removals of nodes in
	/// registration list.	/// registration list.
	///	///
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	class MachinePassRegistryListener {	class MachinePassRegistryListener {

		virtual void anchor();
	public:	public:
	MachinePassRegistryListener() {}	MachinePassRegistryListener() {}
	virtual ~MachinePassRegistryListener() {}	virtual ~MachinePassRegistryListener() {}
	virtual void NotifyAdd(const char N, MachinePassCtor C, const char D) = 0;	virtual void NotifyAdd(const char N, MachinePassCtor C, const char D) = 0;
	virtual void NotifyRemove(const char *N) = 0;	virtual void NotifyRemove(const char *N) = 0;
	};	};

	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//
	///	///
	/// MachinePassRegistryNode - Machine pass node stored in registration list .	/// MachinePassRegistryNode - Machine pass node stored in registration list .

End of changes. 1 change blocks.
	0 lines changed or deleted	1 lines changed or added

	Pass.h	Pass.h

	skipping to change at line 89	skipping to change at line 89
	/// constrained passes described below.	/// constrained passes described below.
	///	///
	class Pass {	class Pass {
	AnalysisResolver *Resolver; // Used to resolve analysis	AnalysisResolver *Resolver; // Used to resolve analysis
	const void *PassID;	const void *PassID;
	PassKind Kind;	PassKind Kind;
	void operator=(const Pass&); // DO NOT IMPLEMENT	void operator=(const Pass&); // DO NOT IMPLEMENT
	Pass(const Pass &); // DO NOT IMPLEMENT	Pass(const Pass &); // DO NOT IMPLEMENT

	public:	public:

	explicit Pass(PassKind K, char &pid);	explicit Pass(PassKind K, char &pid) : Resolver(0), PassID(&pid), Kind(K) { }
	virtual ~Pass();	virtual ~Pass();

	PassKind getPassKind() const { return Kind; }	PassKind getPassKind() const { return Kind; }

	/// getPassName - Return a nice clean name for a pass. This usually	/// getPassName - Return a nice clean name for a pass. This usually
	/// implemented in terms of the name that is registered by one of the	/// implemented in terms of the name that is registered by one of the
	/// Registration templates, but can be overloaded directly.	/// Registration templates, but can be overloaded directly.
	///	///
	virtual const char *getPassName() const;	virtual const char *getPassName() const;

	/// getPassID - Return the PassID number that corresponds to this pass.	/// getPassID - Return the PassID number that corresponds to this pass.

	virtual AnalysisID getPassID() const {	AnalysisID getPassID() const {
	return PassID;	return PassID;
	}	}

	/// print - Print out the internal state of the pass. This is called by	/// print - Print out the internal state of the pass. This is called by
	/// Analyze to print out the contents of an analysis. Otherwise it is no t	/// Analyze to print out the contents of an analysis. Otherwise it is no t
	/// necessary to implement this method. Beware that the module pointer M AY be	/// necessary to implement this method. Beware that the module pointer M AY be
	/// null. This automatically forwards to a virtual function that does no t	/// null. This automatically forwards to a virtual function that does no t
	/// provide the Module* in case the analysis doesn't need it it can just be	/// provide the Module* in case the analysis doesn't need it it can just be
	/// ignored.	/// ignored.
	///	///

	skipping to change at line 177	skipping to change at line 177
	virtual void dumpPassStructure(unsigned Offset = 0);	virtual void dumpPassStructure(unsigned Offset = 0);

	// lookupPassInfo - Return the pass info object for the specified pass cl ass,	// lookupPassInfo - Return the pass info object for the specified pass cl ass,
	// or null if it is not known.	// or null if it is not known.
	static const PassInfo lookupPassInfo(const void TI);	static const PassInfo lookupPassInfo(const void TI);

	// lookupPassInfo - Return the pass info object for the pass with the giv en	// lookupPassInfo - Return the pass info object for the pass with the giv en
	// argument string, or null if it is not known.	// argument string, or null if it is not known.
	static const PassInfo *lookupPassInfo(StringRef Arg);	static const PassInfo *lookupPassInfo(StringRef Arg);


		// createPass - Create a object for the specified pass class,
		// or null if it is not known.
		static Pass *createPass(AnalysisID ID);

	/// getAnalysisIfAvailable<AnalysisType>() - Subclasses use this function to	/// getAnalysisIfAvailable<AnalysisType>() - Subclasses use this function to
	/// get analysis information that might be around, for example to update it.	/// get analysis information that might be around, for example to update it.
	/// This is different than getAnalysis in that it can fail (if the analys is	/// This is different than getAnalysis in that it can fail (if the analys is
	/// results haven't been computed), so should only be used if you can han dle	/// results haven't been computed), so should only be used if you can han dle
	/// the case when the analysis is not available. This method is often us ed by	/// the case when the analysis is not available. This method is often us ed by
	/// transformation APIs to update analysis results for a pass automatical ly as	/// transformation APIs to update analysis results for a pass automatical ly as
	/// the transform is performed.	/// the transform is performed.
	///	///
	template<typename AnalysisType> AnalysisType *	template<typename AnalysisType> AnalysisType *
	getAnalysisIfAvailable() const; // Defined in PassAnalysisSupport.h	getAnalysisIfAvailable() const; // Defined in PassAnalysisSupport.h

End of changes. 3 change blocks.
	2 lines changed or deleted	6 lines changed or added

	PointerIntPair.h	PointerIntPair.h

	skipping to change at line 95	skipping to change at line 95
	void setInt(IntType Int) {	void setInt(IntType Int) {
	intptr_t IntVal = Int;	intptr_t IntVal = Int;
	assert(IntVal < (1 << IntBits) && "Integer too large for field");	assert(IntVal < (1 << IntBits) && "Integer too large for field");

	// Preserve all bits other than the ones we are updating.	// Preserve all bits other than the ones we are updating.
	Value &= ~ShiftedIntMask; // Remove integer field.	Value &= ~ShiftedIntMask; // Remove integer field.
	Value \|= IntVal << IntShift; // Set new integer.	Value \|= IntVal << IntShift; // Set new integer.
	}	}

	PointerTy const *getAddrOfPointer() const {	PointerTy const *getAddrOfPointer() const {

		return const_cast<PointerIntPair *>(this)->getAddrOfPointer();
		}

		PointerTy *getAddrOfPointer() {
	assert(Value == reinterpret_cast<intptr_t>(getPointer()) &&	assert(Value == reinterpret_cast<intptr_t>(getPointer()) &&
	"Can only return the address if IntBits is cleared and "	"Can only return the address if IntBits is cleared and "
	"PtrTraits doesn't change the pointer");	"PtrTraits doesn't change the pointer");

	return reinterpret_cast<PointerTy const *>(&Value);	return reinterpret_cast<PointerTy *>(&Value);
	}	}

	void getOpaqueValue() const { return reinterpret_cast<void>(Value); }	void getOpaqueValue() const { return reinterpret_cast<void>(Value); }
	void setFromOpaqueValue(void *Val) { Value = reinterpret_cast<intptr_t>(V al);}	void setFromOpaqueValue(void *Val) { Value = reinterpret_cast<intptr_t>(V al);}

	static PointerIntPair getFromOpaqueValue(void *V) {	static PointerIntPair getFromOpaqueValue(void *V) {
	PointerIntPair P; P.setFromOpaqueValue(V); return P;	PointerIntPair P; P.setFromOpaqueValue(V); return P;
	}	}

	bool operator==(const PointerIntPair &RHS) const {return Value == RHS.Val ue;}	bool operator==(const PointerIntPair &RHS) const {return Value == RHS.Val ue;}

End of changes. 2 change blocks.
	1 lines changed or deleted	5 lines changed or added

	SelectionDAG.h	SelectionDAG.h

	skipping to change at line 54	skipping to change at line 54
	SDNode *createSentinel() const {	SDNode *createSentinel() const {
	return static_cast<SDNode*>(&Sentinel);	return static_cast<SDNode*>(&Sentinel);
	}	}
	static void destroySentinel(SDNode *) {}	static void destroySentinel(SDNode *) {}

	SDNode *provideInitialHead() const { return createSentinel(); }	SDNode *provideInitialHead() const { return createSentinel(); }
	SDNode ensureHead(SDNode) const { return createSentinel(); }	SDNode ensureHead(SDNode) const { return createSentinel(); }
	static void noteHead(SDNode, SDNode) {}	static void noteHead(SDNode, SDNode) {}

	static void deleteNode(SDNode *) {	static void deleteNode(SDNode *) {

	assert(0 && "ilist_traits<SDNode> shouldn't see a deleteNode call!");	llvm_unreachable("ilist_traits<SDNode> shouldn't see a deleteNode call! ");
	}	}
	private:	private:
	static void createNode(const SDNode &);	static void createNode(const SDNode &);
	};	};

	/// SDDbgInfo - Keeps track of dbg_value information through SDISel. We do	/// SDDbgInfo - Keeps track of dbg_value information through SDISel. We do
	/// not build SDNodes for these so as not to perturb the generated code;	/// not build SDNodes for these so as not to perturb the generated code;
	/// instead the info is kept off to the side in this structure. Each SDNode may	/// instead the info is kept off to the side in this structure. Each SDNode may
	/// have one or more associated dbg_value entries. This information is kept in	/// have one or more associated dbg_value entries. This information is kept in
	/// DbgValMap.	/// DbgValMap.

	skipping to change at line 115	skipping to change at line 115
	}	}

	typedef SmallVector<SDDbgValue*,32>::iterator DbgIterator;	typedef SmallVector<SDDbgValue*,32>::iterator DbgIterator;
	DbgIterator DbgBegin() { return DbgValues.begin(); }	DbgIterator DbgBegin() { return DbgValues.begin(); }
	DbgIterator DbgEnd() { return DbgValues.end(); }	DbgIterator DbgEnd() { return DbgValues.end(); }
	DbgIterator ByvalParmDbgBegin() { return ByvalParmDbgValues.begin(); }	DbgIterator ByvalParmDbgBegin() { return ByvalParmDbgValues.begin(); }
	DbgIterator ByvalParmDbgEnd() { return ByvalParmDbgValues.end(); }	DbgIterator ByvalParmDbgEnd() { return ByvalParmDbgValues.end(); }
	};	};

	enum CombineLevel {	enum CombineLevel {

	Unrestricted, // Combine may create illegal operations and illegal type	BeforeLegalizeTypes,
	s.	AfterLegalizeTypes,
	NoIllegalTypes, // Combine may create illegal operations but no illegal t	AfterLegalizeVectorOps,
	ypes.	AfterLegalizeDAG
	NoIllegalOperations // Combine may only create legal operations and types
	.
	};	};

	class SelectionDAG;	class SelectionDAG;
	void checkForCycles(const SDNode *N);	void checkForCycles(const SDNode *N);
	void checkForCycles(const SelectionDAG *DAG);	void checkForCycles(const SelectionDAG *DAG);

	/// SelectionDAG class - This is used to represent a portion of an LLVM fun ction	/// SelectionDAG class - This is used to represent a portion of an LLVM fun ction
	/// in a low-level Data Dependence DAG representation suitable for instruct ion	/// in a low-level Data Dependence DAG representation suitable for instruct ion
	/// selection. This DAG is constructed as the first step of instruction	/// selection. This DAG is constructed as the first step of instruction
	/// selection in order to allow implementation of machine specific optimiza tions	/// selection in order to allow implementation of machine specific optimiza tions

	skipping to change at line 141	skipping to change at line 142
	/// representation, which has some similarities to the GCC RTL representati on,	/// representation, which has some similarities to the GCC RTL representati on,
	/// but is significantly more simple, powerful, and is a graph form instead of a	/// but is significantly more simple, powerful, and is a graph form instead of a
	/// linear form.	/// linear form.
	///	///
	class SelectionDAG {	class SelectionDAG {
	const TargetMachine &TM;	const TargetMachine &TM;
	const TargetLowering &TLI;	const TargetLowering &TLI;
	const TargetSelectionDAGInfo &TSI;	const TargetSelectionDAGInfo &TSI;
	MachineFunction *MF;	MachineFunction *MF;
	LLVMContext *Context;	LLVMContext *Context;

		CodeGenOpt::Level OptLevel;

	/// EntryNode - The starting token.	/// EntryNode - The starting token.
	SDNode EntryNode;	SDNode EntryNode;

	/// Root - The root of the entire DAG.	/// Root - The root of the entire DAG.
	SDValue Root;	SDValue Root;

	/// AllNodes - A linked list of nodes in the current DAG.	/// AllNodes - A linked list of nodes in the current DAG.
	ilist<SDNode> AllNodes;	ilist<SDNode> AllNodes;


	skipping to change at line 189	skipping to change at line 191
	/// Return whether we had to truncate the search.	/// Return whether we had to truncate the search.
	///	///
	bool setSubgraphColorHelper(SDNode N, const char Color,	bool setSubgraphColorHelper(SDNode N, const char Color,
	DenseSet<SDNode *> &visited,	DenseSet<SDNode *> &visited,
	int level, bool &printed);	int level, bool &printed);

	void operator=(const SelectionDAG&); // Do not implement.	void operator=(const SelectionDAG&); // Do not implement.
	SelectionDAG(const SelectionDAG&); // Do not implement.	SelectionDAG(const SelectionDAG&); // Do not implement.

	public:	public:

	explicit SelectionDAG(const TargetMachine &TM);	explicit SelectionDAG(const TargetMachine &TM, llvm::CodeGenOpt::Level);
	~SelectionDAG();	~SelectionDAG();

	/// init - Prepare this SelectionDAG to process code in the given	/// init - Prepare this SelectionDAG to process code in the given
	/// MachineFunction.	/// MachineFunction.
	///	///
	void init(MachineFunction &mf);	void init(MachineFunction &mf);

	/// clear - Clear state and free memory necessary to make this	/// clear - Clear state and free memory necessary to make this
	/// SelectionDAG ready to process a new block.	/// SelectionDAG ready to process a new block.
	///	///

	skipping to change at line 395	skipping to change at line 397
	// When generating a branch to a BB, we don't in general know enough	// When generating a branch to a BB, we don't in general know enough
	// to provide debug info for the BB at that time, so keep this one around .	// to provide debug info for the BB at that time, so keep this one around .
	SDValue getBasicBlock(MachineBasicBlock *MBB);	SDValue getBasicBlock(MachineBasicBlock *MBB);
	SDValue getBasicBlock(MachineBasicBlock *MBB, DebugLoc dl);	SDValue getBasicBlock(MachineBasicBlock *MBB, DebugLoc dl);
	SDValue getExternalSymbol(const char *Sym, EVT VT);	SDValue getExternalSymbol(const char *Sym, EVT VT);
	SDValue getExternalSymbol(const char *Sym, DebugLoc dl, EVT VT);	SDValue getExternalSymbol(const char *Sym, DebugLoc dl, EVT VT);
	SDValue getTargetExternalSymbol(const char *Sym, EVT VT,	SDValue getTargetExternalSymbol(const char *Sym, EVT VT,
	unsigned char TargetFlags = 0);	unsigned char TargetFlags = 0);
	SDValue getValueType(EVT);	SDValue getValueType(EVT);
	SDValue getRegister(unsigned Reg, EVT VT);	SDValue getRegister(unsigned Reg, EVT VT);

		SDValue getRegisterMask(const uint32_t *RegMask);
	SDValue getEHLabel(DebugLoc dl, SDValue Root, MCSymbol *Label);	SDValue getEHLabel(DebugLoc dl, SDValue Root, MCSymbol *Label);
	SDValue getBlockAddress(const BlockAddress *BA, EVT VT,	SDValue getBlockAddress(const BlockAddress *BA, EVT VT,
	bool isTarget = false, unsigned char TargetFlags = 0);	bool isTarget = false, unsigned char TargetFlags = 0);

	SDValue getCopyToReg(SDValue Chain, DebugLoc dl, unsigned Reg, SDValue N) {	SDValue getCopyToReg(SDValue Chain, DebugLoc dl, unsigned Reg, SDValue N) {
	return getNode(ISD::CopyToReg, dl, MVT::Other, Chain,	return getNode(ISD::CopyToReg, dl, MVT::Other, Chain,
	getRegister(Reg, N.getValueType()), N);	getRegister(Reg, N.getValueType()), N);
	}	}

	// This version of the getCopyToReg method takes an extra operand, which	// This version of the getCopyToReg method takes an extra operand, which

	skipping to change at line 653	skipping to change at line 656
	EVT MemVT, MachineMemOperand *MMO);	EVT MemVT, MachineMemOperand *MMO);

	/// getMergeValues - Create a MERGE_VALUES node from the given operands.	/// getMergeValues - Create a MERGE_VALUES node from the given operands.
	SDValue getMergeValues(const SDValue *Ops, unsigned NumOps, DebugLoc dl);	SDValue getMergeValues(const SDValue *Ops, unsigned NumOps, DebugLoc dl);

	/// getLoad - Loads are not normal binary operators: their result type is not	/// getLoad - Loads are not normal binary operators: their result type is not
	/// determined by their operands, and they produce a value AND a token ch ain.	/// determined by their operands, and they produce a value AND a token ch ain.
	///	///
	SDValue getLoad(EVT VT, DebugLoc dl, SDValue Chain, SDValue Ptr,	SDValue getLoad(EVT VT, DebugLoc dl, SDValue Chain, SDValue Ptr,
	MachinePointerInfo PtrInfo, bool isVolatile,	MachinePointerInfo PtrInfo, bool isVolatile,

	bool isNonTemporal, unsigned Alignment,	bool isNonTemporal, bool isInvariant, unsigned Alignment,
	const MDNode *TBAAInfo = 0);	const MDNode TBAAInfo = 0, const MDNode Ranges = 0);
	SDValue getExtLoad(ISD::LoadExtType ExtType, DebugLoc dl, EVT VT,	SDValue getExtLoad(ISD::LoadExtType ExtType, DebugLoc dl, EVT VT,
	SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo ,	SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo ,
	EVT MemVT, bool isVolatile,	EVT MemVT, bool isVolatile,
	bool isNonTemporal, unsigned Alignment,	bool isNonTemporal, unsigned Alignment,
	const MDNode *TBAAInfo = 0);	const MDNode *TBAAInfo = 0);
	SDValue getIndexedLoad(SDValue OrigLoad, DebugLoc dl, SDValue Base,	SDValue getIndexedLoad(SDValue OrigLoad, DebugLoc dl, SDValue Base,
	SDValue Offset, ISD::MemIndexedMode AM);	SDValue Offset, ISD::MemIndexedMode AM);
	SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,	SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
	EVT VT, DebugLoc dl,	EVT VT, DebugLoc dl,
	SDValue Chain, SDValue Ptr, SDValue Offset,	SDValue Chain, SDValue Ptr, SDValue Offset,
	MachinePointerInfo PtrInfo, EVT MemVT,	MachinePointerInfo PtrInfo, EVT MemVT,

	bool isVolatile, bool isNonTemporal, unsigned Alignment,	bool isVolatile, bool isNonTemporal, bool isInvariant,
	const MDNode *TBAAInfo = 0);	unsigned Alignment, const MDNode *TBAAInfo = 0,
		const MDNode *Ranges = 0);
	SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,	SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
	EVT VT, DebugLoc dl,	EVT VT, DebugLoc dl,
	SDValue Chain, SDValue Ptr, SDValue Offset,	SDValue Chain, SDValue Ptr, SDValue Offset,
	EVT MemVT, MachineMemOperand *MMO);	EVT MemVT, MachineMemOperand *MMO);

	/// getStore - Helper function to build ISD::STORE nodes.	/// getStore - Helper function to build ISD::STORE nodes.
	///	///
	SDValue getStore(SDValue Chain, DebugLoc dl, SDValue Val, SDValue Ptr,	SDValue getStore(SDValue Chain, DebugLoc dl, SDValue Val, SDValue Ptr,
	MachinePointerInfo PtrInfo, bool isVolatile,	MachinePointerInfo PtrInfo, bool isVolatile,
	bool isNonTemporal, unsigned Alignment,	bool isNonTemporal, unsigned Alignment,

	skipping to change at line 979	skipping to change at line 983
	/// use this predicate to simplify operations downstream. Op and Mask ar e	/// use this predicate to simplify operations downstream. Op and Mask ar e
	/// known to be the same type.	/// known to be the same type.
	bool MaskedValueIsZero(SDValue Op, const APInt &Mask, unsigned Depth = 0)	bool MaskedValueIsZero(SDValue Op, const APInt &Mask, unsigned Depth = 0)
	const;	const;

	/// ComputeMaskedBits - Determine which of the bits specified in Mask are	/// ComputeMaskedBits - Determine which of the bits specified in Mask are
	/// known to be either zero or one and return them in the KnownZero/Known One	/// known to be either zero or one and return them in the KnownZero/Known One
	/// bitsets. This code only analyzes bits in Mask, in order to short-cir cuit	/// bitsets. This code only analyzes bits in Mask, in order to short-cir cuit
	/// processing. Targets can implement the computeMaskedBitsForTargetNode	/// processing. Targets can implement the computeMaskedBitsForTargetNode
	/// method in the TargetLowering class to allow target nodes to be unders tood.	/// method in the TargetLowering class to allow target nodes to be unders tood.

	void ComputeMaskedBits(SDValue Op, const APInt &Mask, APInt &KnownZero,	void ComputeMaskedBits(SDValue Op, APInt &KnownZero, APInt &KnownOne,
	APInt &KnownOne, unsigned Depth = 0) const;	unsigned Depth = 0) const;

	/// ComputeNumSignBits - Return the number of times the sign bit of the	/// ComputeNumSignBits - Return the number of times the sign bit of the
	/// register is replicated into the other bits. We know that at least 1 bit	/// register is replicated into the other bits. We know that at least 1 bit
	/// is always equal to the sign bit (itself), but other cases can give us	/// is always equal to the sign bit (itself), but other cases can give us
	/// information. For example, immediately after an "SRA X, 2", we know t hat	/// information. For example, immediately after an "SRA X, 2", we know t hat
	/// the top 3 bits are all equal to each other, so we return 3. Targets can	/// the top 3 bits are all equal to each other, so we return 3. Targets can
	/// implement the ComputeNumSignBitsForTarget method in the TargetLowerin g	/// implement the ComputeNumSignBitsForTarget method in the TargetLowerin g
	/// class to allow target nodes to be understood.	/// class to allow target nodes to be understood.
	unsigned ComputeNumSignBits(SDValue Op, unsigned Depth = 0) const;	unsigned ComputeNumSignBits(SDValue Op, unsigned Depth = 0) const;


	skipping to change at line 1036	skipping to change at line 1040
	unsigned InferPtrAlignment(SDValue Ptr) const;	unsigned InferPtrAlignment(SDValue Ptr) const;

	private:	private:
	bool RemoveNodeFromCSEMaps(SDNode *N);	bool RemoveNodeFromCSEMaps(SDNode *N);
	void AddModifiedNodeToCSEMaps(SDNode N, DAGUpdateListener UpdateListene r);	void AddModifiedNodeToCSEMaps(SDNode N, DAGUpdateListener UpdateListene r);
	SDNode FindModifiedNodeSlot(SDNode N, SDValue Op, void *&InsertPos);	SDNode FindModifiedNodeSlot(SDNode N, SDValue Op, void *&InsertPos);
	SDNode FindModifiedNodeSlot(SDNode N, SDValue Op1, SDValue Op2,	SDNode FindModifiedNodeSlot(SDNode N, SDValue Op1, SDValue Op2,
	void *&InsertPos);	void *&InsertPos);
	SDNode FindModifiedNodeSlot(SDNode N, const SDValue *Ops, unsigned NumO ps,	SDNode FindModifiedNodeSlot(SDNode N, const SDValue *Ops, unsigned NumO ps,
	void *&InsertPos);	void *&InsertPos);

		SDNode UpdadeDebugLocOnMergedSDNode(SDNode N, DebugLoc loc);

	void DeleteNodeNotInCSEMaps(SDNode *N);	void DeleteNodeNotInCSEMaps(SDNode *N);
	void DeallocateNode(SDNode *N);	void DeallocateNode(SDNode *N);

	unsigned getEVTAlignment(EVT MemoryVT) const;	unsigned getEVTAlignment(EVT MemoryVT) const;

	void allnodes_clear();	void allnodes_clear();

	/// VTList - List of non-single value types.	/// VTList - List of non-single value types.
	std::vector<SDVTList> VTList;	std::vector<SDVTList> VTList;

End of changes. 9 change blocks.
	14 lines changed or deleted	16 lines changed or added

	TargetJITInfo.h	TargetJITInfo.h

	skipping to change at line 20	skipping to change at line 20
	// This file exposes an abstract interface used by the Just-In-Time code	// This file exposes an abstract interface used by the Just-In-Time code
	// generator to perform target-specific activities, such as emitting stubs. If	// generator to perform target-specific activities, such as emitting stubs. If
	// a TargetMachine supports JIT code generation, it should provide one of t hese	// a TargetMachine supports JIT code generation, it should provide one of t hese
	// objects through the getJITInfo() method.	// objects through the getJITInfo() method.
	//	//
	//===---------------------------------------------------------------------- ===//	//===---------------------------------------------------------------------- ===//

	#ifndef LLVM_TARGET_TARGETJITINFO_H	#ifndef LLVM_TARGET_TARGETJITINFO_H
	#define LLVM_TARGET_TARGETJITINFO_H	#define LLVM_TARGET_TARGETJITINFO_H


	#include <cassert>
	#include "llvm/Support/ErrorHandling.h"	#include "llvm/Support/ErrorHandling.h"
	#include "llvm/Support/DataTypes.h"	#include "llvm/Support/DataTypes.h"

		#include <cassert>

	namespace llvm {	namespace llvm {
	class Function;	class Function;
	class GlobalValue;	class GlobalValue;
	class JITCodeEmitter;	class JITCodeEmitter;
	class MachineRelocation;	class MachineRelocation;

	/// TargetJITInfo - Target specific information required by the Just-In-T ime	/// TargetJITInfo - Target specific information required by the Just-In-T ime
	/// code generator.	/// code generator.
	class TargetJITInfo {	class TargetJITInfo {

		virtual void anchor();
	public:	public:
	virtual ~TargetJITInfo() {}	virtual ~TargetJITInfo() {}

	/// replaceMachineCodeForFunction - Make it so that calling the functio n	/// replaceMachineCodeForFunction - Make it so that calling the functio n
	/// whose machine code is at OLD turns into a call to NEW, perhaps by	/// whose machine code is at OLD turns into a call to NEW, perhaps by
	/// overwriting OLD with a branch to NEW. This is used for self-modify ing	/// overwriting OLD with a branch to NEW. This is used for self-modify ing
	/// code.	/// code.
	///	///
	virtual void replaceMachineCodeForFunction(void Old, void New) = 0;	virtual void replaceMachineCodeForFunction(void Old, void New) = 0;

	/// emitGlobalValueIndirectSym - Use the specified JITCodeEmitter objec t	/// emitGlobalValueIndirectSym - Use the specified JITCodeEmitter objec t
	/// to emit an indirect symbol which contains the address of the specif ied	/// to emit an indirect symbol which contains the address of the specif ied
	/// ptr.	/// ptr.
	virtual void emitGlobalValueIndirectSym(const GlobalValue GV, void *p tr,	virtual void emitGlobalValueIndirectSym(const GlobalValue GV, void *p tr,
	JITCodeEmitter &JCE) {	JITCodeEmitter &JCE) {

	assert(0 && "This target doesn't implement emitGlobalValueIndirectSym	llvm_unreachable("This target doesn't implement "
	!");	"emitGlobalValueIndirectSym!");
	return 0;
	}	}

	/// Records the required size and alignment for a call stub in bytes.	/// Records the required size and alignment for a call stub in bytes.
	struct StubLayout {	struct StubLayout {
	size_t Size;	size_t Size;
	size_t Alignment;	size_t Alignment;
	};	};
	/// Returns the maximum size and alignment for a call stub on this targ et.	/// Returns the maximum size and alignment for a call stub on this targ et.
	virtual StubLayout getStubLayout() {	virtual StubLayout getStubLayout() {
	llvm_unreachable("This target doesn't implement getStubLayout!");	llvm_unreachable("This target doesn't implement getStubLayout!");

	StubLayout Result = {0, 0};
	return Result;
	}	}

	/// emitFunctionStub - Use the specified JITCodeEmitter object to emit a	/// emitFunctionStub - Use the specified JITCodeEmitter object to emit a
	/// small native function that simply calls the function at the specifi ed	/// small native function that simply calls the function at the specifi ed
	/// address. The JITCodeEmitter must already have storage allocated fo r the	/// address. The JITCodeEmitter must already have storage allocated fo r the
	/// stub. Return the address of the resultant function, which may have been	/// stub. Return the address of the resultant function, which may have been
	/// aligned from the address the JCE was set up to emit at.	/// aligned from the address the JCE was set up to emit at.
	virtual void emitFunctionStub(const Function F, void *Target,	virtual void emitFunctionStub(const Function F, void *Target,
	JITCodeEmitter &JCE) {	JITCodeEmitter &JCE) {

	assert(0 && "This target doesn't implement emitFunctionStub!");	llvm_unreachable("This target doesn't implement emitFunctionStub!");
	return 0;
	}	}

	/// getPICJumpTableEntry - Returns the value of the jumptable entry for the	/// getPICJumpTableEntry - Returns the value of the jumptable entry for the
	/// specific basic block.	/// specific basic block.
	virtual uintptr_t getPICJumpTableEntry(uintptr_t BB, uintptr_t JTBase) {	virtual uintptr_t getPICJumpTableEntry(uintptr_t BB, uintptr_t JTBase) {

	assert(0 && "This target doesn't implement getPICJumpTableEntry!");	llvm_unreachable("This target doesn't implement getPICJumpTableEntry!
	return 0;	");
	}	}

	/// LazyResolverFn - This typedef is used to represent the function tha t	/// LazyResolverFn - This typedef is used to represent the function tha t
	/// unresolved call points should invoke. This is a target specific	/// unresolved call points should invoke. This is a target specific
	/// function that knows how to walk the stack and find out which stub t he	/// function that knows how to walk the stack and find out which stub t he
	/// call is coming from.	/// call is coming from.
	typedef void (*LazyResolverFn)();	typedef void (*LazyResolverFn)();

	/// JITCompilerFn - This typedef is used to represent the JIT function that	/// JITCompilerFn - This typedef is used to represent the JIT function that
	/// lazily compiles the function corresponding to a stub. The JIT keep s	/// lazily compiles the function corresponding to a stub. The JIT keep s
	/// track of the mapping between stubs and LLVM Functions, the target	/// track of the mapping between stubs and LLVM Functions, the target
	/// provides the ability to figure out the address of a stub that is ca lled	/// provides the ability to figure out the address of a stub that is ca lled
	/// by the LazyResolverFn.	/// by the LazyResolverFn.
	typedef void* (JITCompilerFn)(void );	typedef void* (JITCompilerFn)(void );

	/// getLazyResolverFunction - This method is used to initialize the JIT ,	/// getLazyResolverFunction - This method is used to initialize the JIT ,
	/// giving the target the function that should be used to compile a	/// giving the target the function that should be used to compile a
	/// function, and giving the JIT the target function used to do the laz y	/// function, and giving the JIT the target function used to do the laz y
	/// resolving.	/// resolving.
	virtual LazyResolverFn getLazyResolverFunction(JITCompilerFn) {	virtual LazyResolverFn getLazyResolverFunction(JITCompilerFn) {

	assert(0 && "Not implemented for this target!");	llvm_unreachable("Not implemented for this target!");
	return 0;
	}	}

	/// relocate - Before the JIT can run a block of code that has been emi tted,	/// relocate - Before the JIT can run a block of code that has been emi tted,
	/// it must rewrite the code to contain the actual addresses of any	/// it must rewrite the code to contain the actual addresses of any
	/// referenced global symbols.	/// referenced global symbols.
	virtual void relocate(void Function, MachineRelocation MR,	virtual void relocate(void Function, MachineRelocation MR,
	unsigned NumRelocs, unsigned char* GOTBase) {	unsigned NumRelocs, unsigned char* GOTBase) {
	assert(NumRelocs == 0 && "This target does not have relocations!");	assert(NumRelocs == 0 && "This target does not have relocations!");
	}	}

	/// allocateThreadLocalMemory - Each target has its own way of	/// allocateThreadLocalMemory - Each target has its own way of
	/// handling thread local variables. This method returns a value only	/// handling thread local variables. This method returns a value only
	/// meaningful to the target.	/// meaningful to the target.
	virtual char* allocateThreadLocalMemory(size_t size) {	virtual char* allocateThreadLocalMemory(size_t size) {

	assert(0 && "This target does not implement thread local storage!");	llvm_unreachable("This target does not implement thread local storage
	return 0;	!");
	}	}

	/// needsGOT - Allows a target to specify that it would like the	/// needsGOT - Allows a target to specify that it would like the
	/// JIT to manage a GOT for it.	/// JIT to manage a GOT for it.
	bool needsGOT() const { return useGOT; }	bool needsGOT() const { return useGOT; }

	/// hasCustomConstantPool - Allows a target to specify that constant	/// hasCustomConstantPool - Allows a target to specify that constant
	/// pool address resolution is handled by the target.	/// pool address resolution is handled by the target.
	virtual bool hasCustomConstantPool() const { return false; }	virtual bool hasCustomConstantPool() const { return false; }


End of changes. 9 change blocks.
	14 lines changed or deleted	10 lines changed or added