APFloat.h   APFloat.h 
skipping to change at line 277 skipping to change at line 277
/* Arithmetic. */ /* Arithmetic. */
opStatus add(const APFloat &, roundingMode); opStatus add(const APFloat &, roundingMode);
opStatus subtract(const APFloat &, roundingMode); opStatus subtract(const APFloat &, roundingMode);
opStatus multiply(const APFloat &, roundingMode); opStatus multiply(const APFloat &, roundingMode);
opStatus divide(const APFloat &, roundingMode); opStatus divide(const APFloat &, roundingMode);
/* IEEE remainder. */ /* IEEE remainder. */
opStatus remainder(const APFloat &); opStatus remainder(const APFloat &);
/* C fmod, or llvm frem. */ /* C fmod, or llvm frem. */
opStatus mod(const APFloat &, roundingMode); opStatus mod(const APFloat &, roundingMode);
opStatus fusedMultiplyAdd(const APFloat &, const APFloat &, roundingMod e); opStatus fusedMultiplyAdd(const APFloat &, const APFloat &, roundingMod e);
opStatus roundToIntegral(roundingMode);
/* Sign operations. */ /* Sign operations. */
void changeSign(); void changeSign();
void clearSign(); void clearSign();
void copySign(const APFloat &); void copySign(const APFloat &);
/* Conversions. */ /* Conversions. */
opStatus convert(const fltSemantics &, roundingMode, bool *); opStatus convert(const fltSemantics &, roundingMode, bool *);
opStatus convertToInteger(integerPart *, unsigned int, bool, opStatus convertToInteger(integerPart *, unsigned int, bool,
roundingMode, bool *) const; roundingMode, bool *) const;
skipping to change at line 457 skipping to change at line 458
/* The exponent - a signed number. */ /* The exponent - a signed number. */
exponent_t exponent; exponent_t exponent;
/* What kind of floating point number this is. */ /* What kind of floating point number this is. */
/* Only 2 bits are required, but VisualStudio incorrectly sign extends /* Only 2 bits are required, but VisualStudio incorrectly sign extends
it. Using the extra bit keeps it from failing under VisualStudio */ it. Using the extra bit keeps it from failing under VisualStudio */
fltCategory category: 3; fltCategory category: 3;
/* The sign bit of this number. */ /* The sign bit of this number. */
unsigned int sign: 1; unsigned int sign: 1;
/* For PPCDoubleDouble, we have a second exponent and sign (the second
significand is appended to the first one, although it would be wrong
to
regard these as a single number for arithmetic purposes). These fie
lds
are not meaningful for any other type. */
exponent_t exponent2 : 11;
unsigned int sign2: 1;
}; };
// See friend declaration above. This additional declaration is required
in
// order to compile LLVM with IBM xlC compiler.
hash_code hash_value(const APFloat &Arg);
} /* namespace llvm */ } /* namespace llvm */
#endif /* LLVM_FLOAT_H */ #endif /* LLVM_FLOAT_H */
 End of changes. 3 change blocks. 
9 lines changed or deleted 6 lines changed or added


 APInt.h   APInt.h 
skipping to change at line 19 skipping to change at line 19
// //
// This file implements a class to represent arbitrary precision integral // This file implements a class to represent arbitrary precision integral
// constant values and operations on them. // constant values and operations on them.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_APINT_H #ifndef LLVM_APINT_H
#define LLVM_APINT_H #define LLVM_APINT_H
#include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/ArrayRef.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/MathExtras.h" #include "llvm/Support/MathExtras.h"
#include <cassert> #include <cassert>
#include <climits> #include <climits>
#include <cstring> #include <cstring>
#include <string> #include <string>
namespace llvm { namespace llvm {
class Deserializer; class Deserializer;
class FoldingSetNodeID; class FoldingSetNodeID;
class Serializer; class Serializer;
skipping to change at line 253 skipping to change at line 254
APInt(unsigned numBits, ArrayRef<uint64_t> bigVal); APInt(unsigned numBits, ArrayRef<uint64_t> bigVal);
/// Equivalent to APInt(numBits, ArrayRef<uint64_t>(bigVal, numWords)), b ut /// Equivalent to APInt(numBits, ArrayRef<uint64_t>(bigVal, numWords)), b ut
/// deprecated because this constructor is prone to ambiguity with the /// deprecated because this constructor is prone to ambiguity with the
/// APInt(unsigned, uint64_t, bool) constructor. /// APInt(unsigned, uint64_t, bool) constructor.
/// ///
/// If this overload is ever deleted, care should be taken to prevent cal ls /// If this overload is ever deleted, care should be taken to prevent cal ls
/// from being incorrectly captured by the APInt(unsigned, uint64_t, bool ) /// from being incorrectly captured by the APInt(unsigned, uint64_t, bool )
/// constructor. /// constructor.
APInt(unsigned numBits, unsigned numWords, const uint64_t bigVal[]); APInt(unsigned numBits, unsigned numWords, const uint64_t bigVal[]);
/// This constructor interprets the string \arg str in the given radix. T he /// This constructor interprets the string \p str in the given radix. The
/// interpretation stops when the first character that is not suitable fo r the /// interpretation stops when the first character that is not suitable fo r the
/// radix is encountered, or the end of the string. Acceptable radix valu es /// radix is encountered, or the end of the string. Acceptable radix valu es
/// are 2, 8, 10, 16, and 36. It is an error for the value implied by the /// are 2, 8, 10, 16, and 36. It is an error for the value implied by the
/// string to require more bits than numBits. /// string to require more bits than numBits.
/// ///
/// @param numBits the bit width of the constructed APInt /// @param numBits the bit width of the constructed APInt
/// @param str the string to be interpreted /// @param str the string to be interpreted
/// @param radix the radix to use for the conversion /// @param radix the radix to use for the conversion
/// @brief Construct an APInt from a string representation. /// @brief Construct an APInt from a string representation.
APInt(unsigned numBits, StringRef str, uint8_t radix); APInt(unsigned numBits, StringRef str, uint8_t radix);
skipping to change at line 276 skipping to change at line 277
/// @brief Copy Constructor. /// @brief Copy Constructor.
APInt(const APInt& that) APInt(const APInt& that)
: BitWidth(that.BitWidth), VAL(0) { : BitWidth(that.BitWidth), VAL(0) {
assert(BitWidth && "bitwidth too small"); assert(BitWidth && "bitwidth too small");
if (isSingleWord()) if (isSingleWord())
VAL = that.VAL; VAL = that.VAL;
else else
initSlowCase(that); initSlowCase(that);
} }
#if LLVM_USE_RVALUE_REFERENCES
/// @brief Move Constructor.
APInt(APInt&& that) : BitWidth(that.BitWidth), VAL(that.VAL) {
that.BitWidth = 0;
}
#endif
/// @brief Destructor. /// @brief Destructor.
~APInt() { ~APInt() {
if (!isSingleWord()) if (!isSingleWord())
delete [] pVal; delete [] pVal;
} }
/// Default constructor that creates an uninitialized APInt. This is use ful /// Default constructor that creates an uninitialized APInt. This is use ful
/// for object deserialization (pair this with the static method Read). /// for object deserialization (pair this with the static method Read).
explicit APInt() : BitWidth(1) {} explicit APInt() : BitWidth(1) {}
skipping to change at line 352 skipping to change at line 360
/// This checks to see if the value of this APInt is the minimum signed /// This checks to see if the value of this APInt is the minimum signed
/// value for the APInt's bit width. /// value for the APInt's bit width.
/// @brief Determine if this is the smallest signed value. /// @brief Determine if this is the smallest signed value.
bool isMinSignedValue() const { bool isMinSignedValue() const {
return BitWidth == 1 ? VAL == 1 : isNegative() && isPowerOf2(); return BitWidth == 1 ? VAL == 1 : isNegative() && isPowerOf2();
} }
/// @brief Check if this APInt has an N-bits unsigned integer value. /// @brief Check if this APInt has an N-bits unsigned integer value.
bool isIntN(unsigned N) const { bool isIntN(unsigned N) const {
assert(N && "N == 0 ???"); assert(N && "N == 0 ???");
if (N >= getBitWidth()) return getActiveBits() <= N;
return true;
if (isSingleWord())
return isUIntN(N, VAL);
return APInt(N, makeArrayRef(pVal, getNumWords())).zext(getBitWidth())
== (*this);
} }
/// @brief Check if this APInt has an N-bits signed integer value. /// @brief Check if this APInt has an N-bits signed integer value.
bool isSignedIntN(unsigned N) const { bool isSignedIntN(unsigned N) const {
assert(N && "N == 0 ???"); assert(N && "N == 0 ???");
return getMinSignedBits() <= N; return getMinSignedBits() <= N;
} }
/// @returns true if the argument APInt value is a power of two > 0. /// @returns true if the argument APInt value is a power of two > 0.
bool isPowerOf2() const { bool isPowerOf2() const {
skipping to change at line 506 skipping to change at line 508
if (loBitsSet == 0) if (loBitsSet == 0)
return APInt(numBits, 0); return APInt(numBits, 0);
if (loBitsSet == APINT_BITS_PER_WORD) if (loBitsSet == APINT_BITS_PER_WORD)
return APInt(numBits, -1ULL); return APInt(numBits, -1ULL);
// For small values, return quickly. // For small values, return quickly.
if (loBitsSet <= APINT_BITS_PER_WORD) if (loBitsSet <= APINT_BITS_PER_WORD)
return APInt(numBits, -1ULL >> (APINT_BITS_PER_WORD - loBitsSet)); return APInt(numBits, -1ULL >> (APINT_BITS_PER_WORD - loBitsSet));
return getAllOnesValue(numBits).lshr(numBits - loBitsSet); return getAllOnesValue(numBits).lshr(numBits - loBitsSet);
} }
/// \brief Determine if two APInts have the same value, after zero-extend
ing
/// one of them (if needed!) to ensure that the bit-widths match.
static bool isSameValue(const APInt &I1, const APInt &I2) {
if (I1.getBitWidth() == I2.getBitWidth())
return I1 == I2;
if (I1.getBitWidth() > I2.getBitWidth())
return I1 == I2.zext(I1.getBitWidth());
return I1.zext(I2.getBitWidth()) == I2;
}
/// \brief Overload to compute a hash_code for an APInt value. /// \brief Overload to compute a hash_code for an APInt value.
friend hash_code hash_value(const APInt &Arg); friend hash_code hash_value(const APInt &Arg);
/// This function returns a pointer to the internal storage of the APInt. /// This function returns a pointer to the internal storage of the APInt.
/// This is useful for writing out the APInt in binary form without any /// This is useful for writing out the APInt in binary form without any
/// conversions. /// conversions.
const uint64_t* getRawData() const { const uint64_t* getRawData() const {
if (isSingleWord()) if (isSingleWord())
return &VAL; return &VAL;
return &pVal[0]; return &pVal[0];
skipping to change at line 590 skipping to change at line 604
// If the bitwidths are the same, we can avoid mucking with memory // If the bitwidths are the same, we can avoid mucking with memory
if (isSingleWord() && RHS.isSingleWord()) { if (isSingleWord() && RHS.isSingleWord()) {
VAL = RHS.VAL; VAL = RHS.VAL;
BitWidth = RHS.BitWidth; BitWidth = RHS.BitWidth;
return clearUnusedBits(); return clearUnusedBits();
} }
return AssignSlowCase(RHS); return AssignSlowCase(RHS);
} }
#if LLVM_USE_RVALUE_REFERENCES
/// @brief Move assignment operator.
APInt& operator=(APInt&& that) {
if (!isSingleWord())
delete [] pVal;
BitWidth = that.BitWidth;
VAL = that.VAL;
that.BitWidth = 0;
return *this;
}
#endif
/// The RHS value is assigned to *this. If the significant bits in RHS ex ceed /// The RHS value is assigned to *this. If the significant bits in RHS ex ceed
/// the bit width, the excess bits are truncated. If the bit width is lar ger /// the bit width, the excess bits are truncated. If the bit width is lar ger
/// than 64, the value is zero filled in the unspecified high order bits. /// than 64, the value is zero filled in the unspecified high order bits.
/// @returns *this after assignment of RHS value. /// @returns *this after assignment of RHS value.
/// @brief Assignment operator. /// @brief Assignment operator.
APInt& operator=(uint64_t RHS); APInt& operator=(uint64_t RHS);
/// Performs a bitwise AND operation on this APInt and RHS. The result is /// Performs a bitwise AND operation on this APInt and RHS. The result is
/// assigned to *this. /// assigned to *this.
/// @returns *this after ANDing with RHS. /// @returns *this after ANDing with RHS.
skipping to change at line 734 skipping to change at line 763
/// Logical right-shift this APInt by shiftAmt. /// Logical right-shift this APInt by shiftAmt.
/// @brief Logical right-shift function. /// @brief Logical right-shift function.
APInt lshr(unsigned shiftAmt) const; APInt lshr(unsigned shiftAmt) const;
/// Left-shift this APInt by shiftAmt. /// Left-shift this APInt by shiftAmt.
/// @brief Left-shift function. /// @brief Left-shift function.
APInt shl(unsigned shiftAmt) const { APInt shl(unsigned shiftAmt) const {
assert(shiftAmt <= BitWidth && "Invalid shift amount"); assert(shiftAmt <= BitWidth && "Invalid shift amount");
if (isSingleWord()) { if (isSingleWord()) {
if (shiftAmt == BitWidth) if (shiftAmt >= BitWidth)
return APInt(BitWidth, 0); // avoid undefined shift results return APInt(BitWidth, 0); // avoid undefined shift results
return APInt(BitWidth, VAL << shiftAmt); return APInt(BitWidth, VAL << shiftAmt);
} }
return shlSlowCase(shiftAmt); return shlSlowCase(shiftAmt);
} }
/// @brief Rotate left by rotateAmt. /// @brief Rotate left by rotateAmt.
APInt rotl(unsigned rotateAmt) const; APInt rotl(unsigned rotateAmt) const;
/// @brief Rotate right by rotateAmt. /// @brief Rotate right by rotateAmt.
skipping to change at line 820 skipping to change at line 849
/// udivrem(X, Y, X, Y), for example. /// udivrem(X, Y, X, Y), for example.
/// @brief Dual division/remainder interface. /// @brief Dual division/remainder interface.
static void udivrem(const APInt &LHS, const APInt &RHS, static void udivrem(const APInt &LHS, const APInt &RHS,
APInt &Quotient, APInt &Remainder); APInt &Quotient, APInt &Remainder);
static void sdivrem(const APInt &LHS, const APInt &RHS, static void sdivrem(const APInt &LHS, const APInt &RHS,
APInt &Quotient, APInt &Remainder) { APInt &Quotient, APInt &Remainder) {
if (LHS.isNegative()) { if (LHS.isNegative()) {
if (RHS.isNegative()) if (RHS.isNegative())
APInt::udivrem(-LHS, -RHS, Quotient, Remainder); APInt::udivrem(-LHS, -RHS, Quotient, Remainder);
else else {
APInt::udivrem(-LHS, RHS, Quotient, Remainder); APInt::udivrem(-LHS, RHS, Quotient, Remainder);
Quotient = -Quotient; Quotient = -Quotient;
}
Remainder = -Remainder; Remainder = -Remainder;
} else if (RHS.isNegative()) { } else if (RHS.isNegative()) {
APInt::udivrem(LHS, -RHS, Quotient, Remainder); APInt::udivrem(LHS, -RHS, Quotient, Remainder);
Quotient = -Quotient; Quotient = -Quotient;
} else { } else {
APInt::udivrem(LHS, RHS, Quotient, Remainder); APInt::udivrem(LHS, RHS, Quotient, Remainder);
} }
} }
// Operations that return overflow indicators. // Operations that return overflow indicators.
skipping to change at line 1086 skipping to change at line 1116
/// @} /// @}
/// @name Bit Manipulation Operators /// @name Bit Manipulation Operators
/// @{ /// @{
/// @brief Set every bit to 1. /// @brief Set every bit to 1.
void setAllBits() { void setAllBits() {
if (isSingleWord()) if (isSingleWord())
VAL = -1ULL; VAL = -1ULL;
else { else {
// Set all the bits in all the words. // Set all the bits in all the words.
for (unsigned i = 0; i < getNumWords(); ++i) for (unsigned i = 0; i < getNumWords(); ++i)
pVal[i] = -1ULL; pVal[i] = -1ULL;
} }
// Clear the unused ones // Clear the unused ones
clearUnusedBits(); clearUnusedBits();
} }
/// Set the given bit to 1 whose position is given as "bitPosition". /// Set the given bit to 1 whose position is given as "bitPosition".
/// @brief Set a given bit to 1. /// @brief Set a given bit to 1.
void setBit(unsigned bitPosition); void setBit(unsigned bitPosition);
/// @brief Set every bit to 0. /// @brief Set every bit to 0.
skipping to change at line 1200 skipping to change at line 1230
/// @brief Get sign extended value /// @brief Get sign extended value
int64_t getSExtValue() const { int64_t getSExtValue() const {
if (isSingleWord()) if (isSingleWord())
return int64_t(VAL << (APINT_BITS_PER_WORD - BitWidth)) >> return int64_t(VAL << (APINT_BITS_PER_WORD - BitWidth)) >>
(APINT_BITS_PER_WORD - BitWidth); (APINT_BITS_PER_WORD - BitWidth);
assert(getMinSignedBits() <= 64 && "Too many bits for int64_t"); assert(getMinSignedBits() <= 64 && "Too many bits for int64_t");
return int64_t(pVal[0]); return int64_t(pVal[0]);
} }
/// This method determines how many bits are required to hold the APInt /// This method determines how many bits are required to hold the APInt
/// equivalent of the string given by \arg str. /// equivalent of the string given by \p str.
/// @brief Get bits required for string value. /// @brief Get bits required for string value.
static unsigned getBitsNeeded(StringRef str, uint8_t radix); static unsigned getBitsNeeded(StringRef str, uint8_t radix);
/// countLeadingZeros - This function is an APInt version of the /// countLeadingZeros - This function is an APInt version of the
/// countLeadingZeros_{32,64} functions in MathExtras.h. It counts the nu mber /// countLeadingZeros_{32,64} functions in MathExtras.h. It counts the nu mber
/// of zeros from the most significant bit to the first one bit. /// of zeros from the most significant bit to the first one bit.
/// @returns BitWidth if the value is zero. /// @returns BitWidth if the value is zero, otherwise
/// @returns the number of zeros from the most significant bit to the fir /// returns the number of zeros from the most significant bit to the firs
st t
/// one bits. /// one bits.
unsigned countLeadingZeros() const { unsigned countLeadingZeros() const {
if (isSingleWord()) { if (isSingleWord()) {
unsigned unusedBits = APINT_BITS_PER_WORD - BitWidth; unsigned unusedBits = APINT_BITS_PER_WORD - BitWidth;
return CountLeadingZeros_64(VAL) - unusedBits; return CountLeadingZeros_64(VAL) - unusedBits;
} }
return countLeadingZerosSlowCase(); return countLeadingZerosSlowCase();
} }
/// countLeadingOnes - This function is an APInt version of the /// countLeadingOnes - This function is an APInt version of the
/// countLeadingOnes_{32,64} functions in MathExtras.h. It counts the num ber /// countLeadingOnes_{32,64} functions in MathExtras.h. It counts the num ber
/// of ones from the most significant bit to the first zero bit. /// of ones from the most significant bit to the first zero bit.
/// @returns 0 if the high order bit is not set /// @returns 0 if the high order bit is not set, otherwise
/// @returns the number of 1 bits from the most significant to the least /// returns the number of 1 bits from the most significant to the least
/// @brief Count the number of leading one bits. /// @brief Count the number of leading one bits.
unsigned countLeadingOnes() const; unsigned countLeadingOnes() const;
/// Computes the number of leading bits of this APInt that are equal to i ts /// Computes the number of leading bits of this APInt that are equal to i ts
/// sign bit. /// sign bit.
unsigned getNumSignBits() const { unsigned getNumSignBits() const {
return isNegative() ? countLeadingOnes() : countLeadingZeros(); return isNegative() ? countLeadingOnes() : countLeadingZeros();
} }
/// countTrailingZeros - This function is an APInt version of the /// countTrailingZeros - This function is an APInt version of the
/// countTrailingZeros_{32,64} functions in MathExtras.h. It counts /// countTrailingZeros_{32,64} functions in MathExtras.h. It counts
/// the number of zeros from the least significant bit to the first set b it. /// the number of zeros from the least significant bit to the first set b it.
/// @returns BitWidth if the value is zero. /// @returns BitWidth if the value is zero, otherwise
/// @returns the number of zeros from the least significant bit to the fi /// returns the number of zeros from the least significant bit to the fir
rst st
/// one bit. /// one bit.
/// @brief Count the number of trailing zero bits. /// @brief Count the number of trailing zero bits.
unsigned countTrailingZeros() const; unsigned countTrailingZeros() const;
/// countTrailingOnes - This function is an APInt version of the /// countTrailingOnes - This function is an APInt version of the
/// countTrailingOnes_{32,64} functions in MathExtras.h. It counts /// countTrailingOnes_{32,64} functions in MathExtras.h. It counts
/// the number of ones from the least significant bit to the first zero b it. /// the number of ones from the least significant bit to the first zero b it.
/// @returns BitWidth if the value is all ones. /// @returns BitWidth if the value is all ones, otherwise
/// @returns the number of ones from the least significant bit to the fir /// returns the number of ones from the least significant bit to the firs
st t
/// zero bit. /// zero bit.
/// @brief Count the number of trailing one bits. /// @brief Count the number of trailing one bits.
unsigned countTrailingOnes() const { unsigned countTrailingOnes() const {
if (isSingleWord()) if (isSingleWord())
return CountTrailingOnes_64(VAL); return CountTrailingOnes_64(VAL);
return countTrailingOnesSlowCase(); return countTrailingOnesSlowCase();
} }
/// countPopulation - This function is an APInt version of the /// countPopulation - This function is an APInt version of the
/// countPopulation_{32,64} functions in MathExtras.h. It counts the numb er /// countPopulation_{32,64} functions in MathExtras.h. It counts the numb er
/// of 1 bits in the APInt value. /// of 1 bits in the APInt value.
/// @returns 0 if the value is zero. /// @returns 0 if the value is zero, otherwise returns the number of set
/// @returns the number of set bits. /// bits.
/// @brief Count the number of bits set. /// @brief Count the number of bits set.
unsigned countPopulation() const { unsigned countPopulation() const {
if (isSingleWord()) if (isSingleWord())
return CountPopulation_64(VAL); return CountPopulation_64(VAL);
return countPopulationSlowCase(); return countPopulationSlowCase();
} }
/// @} /// @}
/// @name Conversion Functions /// @name Conversion Functions
/// @{ /// @{
skipping to change at line 1748 skipping to change at line 1778
} }
/// Performs a bitwise complement operation on APInt. /// Performs a bitwise complement operation on APInt.
/// @brief Bitwise complement function. /// @brief Bitwise complement function.
inline APInt Not(const APInt& APIVal) { inline APInt Not(const APInt& APIVal) {
return ~APIVal; return ~APIVal;
} }
} // End of APIntOps namespace } // End of APIntOps namespace
// See friend declaration above. This additional declaration is required
in
// order to compile LLVM with IBM xlC compiler.
hash_code hash_value(const APInt &Arg);
} // End of llvm namespace } // End of llvm namespace
#endif #endif
 End of changes. 17 change blocks. 
26 lines changed or deleted 61 lines changed or added


 APSInt.h   APSInt.h 
skipping to change at line 138 skipping to change at line 138
return IsUnsigned ? ugt(RHS) : sgt(RHS); return IsUnsigned ? ugt(RHS) : sgt(RHS);
} }
inline bool operator<=(const APSInt& RHS) const { inline bool operator<=(const APSInt& RHS) const {
assert(IsUnsigned == RHS.IsUnsigned && "Signedness mismatch!"); assert(IsUnsigned == RHS.IsUnsigned && "Signedness mismatch!");
return IsUnsigned ? ule(RHS) : sle(RHS); return IsUnsigned ? ule(RHS) : sle(RHS);
} }
inline bool operator>=(const APSInt& RHS) const { inline bool operator>=(const APSInt& RHS) const {
assert(IsUnsigned == RHS.IsUnsigned && "Signedness mismatch!"); assert(IsUnsigned == RHS.IsUnsigned && "Signedness mismatch!");
return IsUnsigned ? uge(RHS) : sge(RHS); return IsUnsigned ? uge(RHS) : sge(RHS);
} }
inline bool operator==(const APSInt& RHS) const {
assert(IsUnsigned == RHS.IsUnsigned && "Signedness mismatch!");
return eq(RHS);
}
inline bool operator==(int64_t RHS) const {
return isSameValue(*this, APSInt(APInt(64, RHS), true));
}
inline bool operator!=(const APSInt& RHS) const {
return !((*this) == RHS);
}
inline bool operator!=(int64_t RHS) const {
return !((*this) == RHS);
}
// The remaining operators just wrap the logic of APInt, but retain the // The remaining operators just wrap the logic of APInt, but retain the
// signedness information. // signedness information.
APSInt operator<<(unsigned Bits) const { APSInt operator<<(unsigned Bits) const {
return APSInt(static_cast<const APInt&>(*this) << Bits, IsUnsigned); return APSInt(static_cast<const APInt&>(*this) << Bits, IsUnsigned);
} }
APSInt& operator<<=(unsigned Amt) { APSInt& operator<<=(unsigned Amt) {
*this = *this << Amt; *this = *this << Amt;
return *this; return *this;
skipping to change at line 252 skipping to change at line 265
: APInt::getSignedMaxValue(numBits), Unsigned); : APInt::getSignedMaxValue(numBits), Unsigned);
} }
/// getMinValue - Return the APSInt representing the minimum integer valu e /// getMinValue - Return the APSInt representing the minimum integer valu e
/// with the given bit width and signedness. /// with the given bit width and signedness.
static APSInt getMinValue(uint32_t numBits, bool Unsigned) { static APSInt getMinValue(uint32_t numBits, bool Unsigned) {
return APSInt(Unsigned ? APInt::getMinValue(numBits) return APSInt(Unsigned ? APInt::getMinValue(numBits)
: APInt::getSignedMinValue(numBits), Unsigned); : APInt::getSignedMinValue(numBits), Unsigned);
} }
/// \brief Determine if two APSInts have the same value, zero- or
/// sign-extending as needed.
static bool isSameValue(const APSInt &I1, const APSInt &I2) {
if (I1.getBitWidth() == I2.getBitWidth() && I1.isSigned() == I2.isSigne
d())
return I1 == I2;
// Check for a bit-width mismatch.
if (I1.getBitWidth() > I2.getBitWidth())
return isSameValue(I1, I2.extend(I1.getBitWidth()));
else if (I2.getBitWidth() > I1.getBitWidth())
return isSameValue(I1.extend(I2.getBitWidth()), I2);
// We have a signedness mismatch. Turn the signed value into an unsigne
d
// value.
if (I1.isSigned()) {
if (I1.isNegative())
return false;
return APSInt(I1, true) == I2;
}
if (I2.isNegative())
return false;
return I1 == APSInt(I2, true);
}
/// Profile - Used to insert APSInt objects, or objects that contain APSI nt /// Profile - Used to insert APSInt objects, or objects that contain APSI nt
/// objects, into FoldingSets. /// objects, into FoldingSets.
void Profile(FoldingSetNodeID& ID) const; void Profile(FoldingSetNodeID& ID) const;
}; };
inline bool operator==(int64_t V1, const APSInt& V2) {
return V2 == V1;
}
inline bool operator!=(int64_t V1, const APSInt& V2) {
return V2 != V1;
}
inline raw_ostream &operator<<(raw_ostream &OS, const APSInt &I) { inline raw_ostream &operator<<(raw_ostream &OS, const APSInt &I) {
I.print(OS, I.isSigned()); I.print(OS, I.isSigned());
return OS; return OS;
} }
} // end namespace llvm } // end namespace llvm
#endif #endif
 End of changes. 3 change blocks. 
0 lines changed or deleted 49 lines changed or added


 AddrModeMatcher.h   AddrModeMatcher.h 
skipping to change at line 22 skipping to change at line 22
// specified by TLI for an access to "V" with an access type of AccessTy. This // specified by TLI for an access to "V" with an access type of AccessTy. This
// returns the addressing mode that is actually matched by value, but also // returns the addressing mode that is actually matched by value, but also
// returns the list of instructions involved in that addressing computation in // returns the list of instructions involved in that addressing computation in
// AddrModeInsts. // AddrModeInsts.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_TRANSFORMS_UTILS_ADDRMODEMATCHER_H #ifndef LLVM_TRANSFORMS_UTILS_ADDRMODEMATCHER_H
#define LLVM_TRANSFORMS_UTILS_ADDRMODEMATCHER_H #define LLVM_TRANSFORMS_UTILS_ADDRMODEMATCHER_H
#include "llvm/AddressingMode.h"
#include "llvm/ADT/SmallVector.h" #include "llvm/ADT/SmallVector.h"
#include "llvm/Target/TargetLowering.h" #include "llvm/Target/TargetLowering.h"
namespace llvm { namespace llvm {
class GlobalValue; class GlobalValue;
class Instruction; class Instruction;
class Value; class Value;
class Type; class Type;
class User; class User;
class raw_ostream; class raw_ostream;
/// ExtAddrMode - This is an extended version of TargetLowering::AddrMode /// ExtAddrMode - This is an extended version of TargetLowering::AddrMode
/// which holds actual Value*'s for register values. /// which holds actual Value*'s for register values.
struct ExtAddrMode : public TargetLowering::AddrMode { struct ExtAddrMode : public AddrMode {
Value *BaseReg; Value *BaseReg;
Value *ScaledReg; Value *ScaledReg;
ExtAddrMode() : BaseReg(0), ScaledReg(0) {} ExtAddrMode() : BaseReg(0), ScaledReg(0) {}
void print(raw_ostream &OS) const; void print(raw_ostream &OS) const;
void dump() const; void dump() const;
bool operator==(const ExtAddrMode& O) const { bool operator==(const ExtAddrMode& O) const {
return (BaseReg == O.BaseReg) && (ScaledReg == O.ScaledReg) && return (BaseReg == O.BaseReg) && (ScaledReg == O.ScaledReg) &&
(BaseGV == O.BaseGV) && (BaseOffs == O.BaseOffs) && (BaseGV == O.BaseGV) && (BaseOffs == O.BaseOffs) &&
(HasBaseReg == O.HasBaseReg) && (Scale == O.Scale); (HasBaseReg == O.HasBaseReg) && (Scale == O.Scale);
 End of changes. 2 change blocks. 
1 lines changed or deleted 2 lines changed or added


 AliasAnalysis.h   AliasAnalysis.h 
skipping to change at line 48 skipping to change at line 48
#define LLVM_ANALYSIS_ALIAS_ANALYSIS_H #define LLVM_ANALYSIS_ALIAS_ANALYSIS_H
#include "llvm/Support/CallSite.h" #include "llvm/Support/CallSite.h"
#include "llvm/ADT/DenseMap.h" #include "llvm/ADT/DenseMap.h"
namespace llvm { namespace llvm {
class LoadInst; class LoadInst;
class StoreInst; class StoreInst;
class VAArgInst; class VAArgInst;
class TargetData; class DataLayout;
class TargetLibraryInfo;
class Pass; class Pass;
class AnalysisUsage; class AnalysisUsage;
class MemTransferInst; class MemTransferInst;
class MemIntrinsic; class MemIntrinsic;
class DominatorTree;
class AliasAnalysis { class AliasAnalysis {
protected: protected:
const TargetData *TD; const DataLayout *TD;
const TargetLibraryInfo *TLI;
private: private:
AliasAnalysis *AA; // Previous Alias Analysis to chain to. AliasAnalysis *AA; // Previous Alias Analysis to chain to.
protected: protected:
/// InitializeAliasAnalysis - Subclasses must call this method to initial ize /// InitializeAliasAnalysis - Subclasses must call this method to initial ize
/// the AliasAnalysis interface before any other methods are called. Thi s is /// the AliasAnalysis interface before any other methods are called. Thi s is
/// typically called by the run* methods of these subclasses. This may b e /// typically called by the run* methods of these subclasses. This may b e
/// called multiple times. /// called multiple times.
/// ///
void InitializeAliasAnalysis(Pass *P); void InitializeAliasAnalysis(Pass *P);
/// getAnalysisUsage - All alias analysis implementations should invoke t his /// getAnalysisUsage - All alias analysis implementations should invoke t his
/// directly (using AliasAnalysis::getAnalysisUsage(AU)). /// directly (using AliasAnalysis::getAnalysisUsage(AU)).
virtual void getAnalysisUsage(AnalysisUsage &AU) const; virtual void getAnalysisUsage(AnalysisUsage &AU) const;
public: public:
static char ID; // Class identification, replacement for typeinfo static char ID; // Class identification, replacement for typeinfo
AliasAnalysis() : TD(0), AA(0) {} AliasAnalysis() : TD(0), TLI(0), AA(0) {}
virtual ~AliasAnalysis(); // We want to be subclassed virtual ~AliasAnalysis(); // We want to be subclassed
/// UnknownSize - This is a special value which can be used with the /// UnknownSize - This is a special value which can be used with the
/// size arguments in alias queries to indicate that the caller does not /// size arguments in alias queries to indicate that the caller does not
/// know the sizes of the potential memory references. /// know the sizes of the potential memory references.
static uint64_t const UnknownSize = ~UINT64_C(0); static uint64_t const UnknownSize = ~UINT64_C(0);
/// getTargetData - Return a pointer to the current TargetData object, or /// getDataLayout - Return a pointer to the current DataLayout object, or
/// null if no TargetData object is available. /// null if no DataLayout object is available.
/// ///
const TargetData *getTargetData() const { return TD; } const DataLayout *getDataLayout() const { return TD; }
/// getTypeStoreSize - Return the TargetData store size for the given typ /// getTargetLibraryInfo - Return a pointer to the current TargetLibraryI
e, nfo
/// object, or null if no TargetLibraryInfo object is available.
///
const TargetLibraryInfo *getTargetLibraryInfo() const { return TLI; }
/// getTypeStoreSize - Return the DataLayout store size for the given typ
e,
/// if known, or a conservative value otherwise. /// if known, or a conservative value otherwise.
/// ///
uint64_t getTypeStoreSize(Type *Ty); uint64_t getTypeStoreSize(Type *Ty);
//===-------------------------------------------------------------------- ===// //===-------------------------------------------------------------------- ===//
/// Alias Queries... /// Alias Queries...
/// ///
/// Location - A description of a memory location. /// Location - A description of a memory location.
struct Location { struct Location {
skipping to change at line 189 skipping to change at line 197
bool isNoAlias(const Location &LocA, const Location &LocB) { bool isNoAlias(const Location &LocA, const Location &LocB) {
return alias(LocA, LocB) == NoAlias; return alias(LocA, LocB) == NoAlias;
} }
/// isNoAlias - A convenience wrapper. /// isNoAlias - A convenience wrapper.
bool isNoAlias(const Value *V1, uint64_t V1Size, bool isNoAlias(const Value *V1, uint64_t V1Size,
const Value *V2, uint64_t V2Size) { const Value *V2, uint64_t V2Size) {
return isNoAlias(Location(V1, V1Size), Location(V2, V2Size)); return isNoAlias(Location(V1, V1Size), Location(V2, V2Size));
} }
/// isNoAlias - A convenience wrapper.
bool isNoAlias(const Value *V1, const Value *V2) {
return isNoAlias(Location(V1), Location(V2));
}
/// isMustAlias - A convenience wrapper. /// isMustAlias - A convenience wrapper.
bool isMustAlias(const Location &LocA, const Location &LocB) { bool isMustAlias(const Location &LocA, const Location &LocB) {
return alias(LocA, LocB) == MustAlias; return alias(LocA, LocB) == MustAlias;
} }
/// isMustAlias - A convenience wrapper. /// isMustAlias - A convenience wrapper.
bool isMustAlias(const Value *V1, const Value *V2) { bool isMustAlias(const Value *V1, const Value *V2) {
return alias(V1, 1, V2, 1) == MustAlias; return alias(V1, 1, V2, 1) == MustAlias;
} }
skipping to change at line 465 skipping to change at line 478
return getModRefInfo(I, Location(P, Size)); return getModRefInfo(I, Location(P, Size));
} }
/// getModRefInfo - Return information about whether two call sites may r efer /// getModRefInfo - Return information about whether two call sites may r efer
/// to the same set of memory locations. See /// to the same set of memory locations. See
/// http://llvm.org/docs/AliasAnalysis.html#ModRefInfo /// http://llvm.org/docs/AliasAnalysis.html#ModRefInfo
/// for details. /// for details.
virtual ModRefResult getModRefInfo(ImmutableCallSite CS1, virtual ModRefResult getModRefInfo(ImmutableCallSite CS1,
ImmutableCallSite CS2); ImmutableCallSite CS2);
/// callCapturesBefore - Return information about whether a particular ca
ll
/// site modifies or reads the specified memory location.
ModRefResult callCapturesBefore(const Instruction *I,
const AliasAnalysis::Location &MemLoc,
DominatorTree *DT);
/// callCapturesBefore - A convenience wrapper.
ModRefResult callCapturesBefore(const Instruction *I, const Value *P,
uint64_t Size, DominatorTree *DT) {
return callCapturesBefore(I, Location(P, Size), DT);
}
//===-------------------------------------------------------------------- ===// //===-------------------------------------------------------------------- ===//
/// Higher level methods for querying mod/ref information. /// Higher level methods for querying mod/ref information.
/// ///
/// canBasicBlockModify - Return true if it is possible for execution of the /// canBasicBlockModify - Return true if it is possible for execution of the
/// specified basic block to modify the value pointed to by Ptr. /// specified basic block to modify the value pointed to by Ptr.
bool canBasicBlockModify(const BasicBlock &BB, const Location &Loc); bool canBasicBlockModify(const BasicBlock &BB, const Location &Loc);
/// canBasicBlockModify - A convenience wrapper. /// canBasicBlockModify - A convenience wrapper.
bool canBasicBlockModify(const BasicBlock &BB, const Value *P, uint64_t S ize){ bool canBasicBlockModify(const BasicBlock &BB, const Value *P, uint64_t S ize){
 End of changes. 9 change blocks. 
8 lines changed or deleted 35 lines changed or added


 AliasSetTracker.h   AliasSetTracker.h 
skipping to change at line 112 skipping to change at line 112
if (AS->PtrListEnd == &NextInList) { if (AS->PtrListEnd == &NextInList) {
AS->PtrListEnd = PrevInList; AS->PtrListEnd = PrevInList;
assert(*AS->PtrListEnd == 0 && "List not terminated right!"); assert(*AS->PtrListEnd == 0 && "List not terminated right!");
} }
delete this; delete this;
} }
}; };
PointerRec *PtrList, **PtrListEnd; // Doubly linked list of nodes. PointerRec *PtrList, **PtrListEnd; // Doubly linked list of nodes.
AliasSet *Forward; // Forwarding pointer. AliasSet *Forward; // Forwarding pointer.
AliasSet *Next, *Prev; // Doubly linked list of AliasSets.
// All instructions without a specific address in this alias set. // All instructions without a specific address in this alias set.
std::vector<AssertingVH<Instruction> > UnknownInsts; std::vector<AssertingVH<Instruction> > UnknownInsts;
// RefCount - Number of nodes pointing to this AliasSet plus the number o f // RefCount - Number of nodes pointing to this AliasSet plus the number o f
// AliasSets forwarding to it. // AliasSets forwarding to it.
unsigned RefCount : 28; unsigned RefCount : 28;
/// AccessType - Keep track of whether this alias set merely refers to th e /// AccessType - Keep track of whether this alias set merely refers to th e
/// locations of memory, whether it modifies the memory, or whether it do es /// locations of memory, whether it modifies the memory, or whether it do es
skipping to change at line 229 skipping to change at line 228
}; };
private: private:
// Can only be created by AliasSetTracker. Also, ilist creates one // Can only be created by AliasSetTracker. Also, ilist creates one
// to serve as a sentinel. // to serve as a sentinel.
friend struct ilist_sentinel_traits<AliasSet>; friend struct ilist_sentinel_traits<AliasSet>;
AliasSet() : PtrList(0), PtrListEnd(&PtrList), Forward(0), RefCount(0), AliasSet() : PtrList(0), PtrListEnd(&PtrList), Forward(0), RefCount(0),
AccessTy(NoModRef), AliasTy(MustAlias), Volatile(false) { AccessTy(NoModRef), AliasTy(MustAlias), Volatile(false) {
} }
AliasSet(const AliasSet &AS); // do not implement AliasSet(const AliasSet &AS) LLVM_DELETED_FUNCTION;
void operator=(const AliasSet &AS); // do not implement void operator=(const AliasSet &AS) LLVM_DELETED_FUNCTION;
PointerRec *getSomePointer() const { PointerRec *getSomePointer() const {
return PtrList; return PtrList;
} }
/// getForwardedTarget - Return the real alias set this represents. If t his /// getForwardedTarget - Return the real alias set this represents. If t his
/// has been merged with another set and is forwarding, return the ultima te /// has been merged with another set and is forwarding, return the ultima te
/// destination set. This also implements the union-find collapsing as w ell. /// destination set. This also implements the union-find collapsing as w ell.
AliasSet *getForwardedTarget(AliasSetTracker &AST) { AliasSet *getForwardedTarget(AliasSetTracker &AST) {
if (!Forward) return this; if (!Forward) return this;
 End of changes. 2 change blocks. 
3 lines changed or deleted 2 lines changed or added


 AlignOf.h   AlignOf.h 
skipping to change at line 18 skipping to change at line 18
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// //
// This file defines the AlignOf function that computes alignments for // This file defines the AlignOf function that computes alignments for
// arbitrary types. // arbitrary types.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_SUPPORT_ALIGNOF_H #ifndef LLVM_SUPPORT_ALIGNOF_H
#define LLVM_SUPPORT_ALIGNOF_H #define LLVM_SUPPORT_ALIGNOF_H
#include "llvm/Support/Compiler.h"
#include <cstddef>
namespace llvm { namespace llvm {
template <typename T> template <typename T>
struct AlignmentCalcImpl { struct AlignmentCalcImpl {
char x; char x;
T t; T t;
private: private:
AlignmentCalcImpl() {} // Never instantiate. AlignmentCalcImpl() {} // Never instantiate.
}; };
skipping to change at line 57 skipping to change at line 60
enum { Alignment_LessEqual_8Bytes = Alignment <= 8 ? 1 : 0 }; enum { Alignment_LessEqual_8Bytes = Alignment <= 8 ? 1 : 0 };
enum { Alignment_LessEqual_16Bytes = Alignment <= 16 ? 1 : 0 }; enum { Alignment_LessEqual_16Bytes = Alignment <= 16 ? 1 : 0 };
}; };
/// alignOf - A templated function that returns the minimum alignment of /// alignOf - A templated function that returns the minimum alignment of
/// of a type. This provides no extra functionality beyond the AlignOf /// of a type. This provides no extra functionality beyond the AlignOf
/// class besides some cosmetic cleanliness. Example usage: /// class besides some cosmetic cleanliness. Example usage:
/// alignOf<int>() returns the alignment of an int. /// alignOf<int>() returns the alignment of an int.
template <typename T> template <typename T>
static inline unsigned alignOf() { return AlignOf<T>::Alignment; } inline unsigned alignOf() { return AlignOf<T>::Alignment; }
/// \brief Helper for building an aligned character array type.
///
/// This template is used to explicitly build up a collection of aligned
/// character types. We have to build these up using a macro and explicit
/// specialization to cope with old versions of MSVC and GCC where only an
/// integer literal can be used to specify an alignment constraint. Once bu
ilt
/// up here, we can then begin to indirect between these using normal C++
/// template parameters.
template <size_t Alignment> struct AlignedCharArrayImpl;
// MSVC requires special handling here.
#ifndef _MSC_VER
#if __has_feature(cxx_alignas)
#define LLVM_ALIGNEDCHARARRAY_TEMPLATE_ALIGNMENT(x) \
template <> struct AlignedCharArrayImpl<x> { \
char alignas(x) aligned; \
}
#elif defined(__GNUC__) || defined(__IBM_ATTRIBUTES)
#define LLVM_ALIGNEDCHARARRAY_TEMPLATE_ALIGNMENT(x) \
template <> struct AlignedCharArrayImpl<x> { \
char aligned __attribute__((aligned(x))); \
}
#else
# error No supported align as directive.
#endif
LLVM_ALIGNEDCHARARRAY_TEMPLATE_ALIGNMENT(1);
LLVM_ALIGNEDCHARARRAY_TEMPLATE_ALIGNMENT(2);
LLVM_ALIGNEDCHARARRAY_TEMPLATE_ALIGNMENT(4);
LLVM_ALIGNEDCHARARRAY_TEMPLATE_ALIGNMENT(8);
LLVM_ALIGNEDCHARARRAY_TEMPLATE_ALIGNMENT(16);
LLVM_ALIGNEDCHARARRAY_TEMPLATE_ALIGNMENT(32);
LLVM_ALIGNEDCHARARRAY_TEMPLATE_ALIGNMENT(64);
LLVM_ALIGNEDCHARARRAY_TEMPLATE_ALIGNMENT(128);
LLVM_ALIGNEDCHARARRAY_TEMPLATE_ALIGNMENT(512);
LLVM_ALIGNEDCHARARRAY_TEMPLATE_ALIGNMENT(1024);
LLVM_ALIGNEDCHARARRAY_TEMPLATE_ALIGNMENT(2048);
LLVM_ALIGNEDCHARARRAY_TEMPLATE_ALIGNMENT(4096);
LLVM_ALIGNEDCHARARRAY_TEMPLATE_ALIGNMENT(8192);
#undef LLVM_ALIGNEDCHARARRAY_TEMPLATE_ALIGNMENT
#else // _MSC_VER
// We provide special variations of this template for the most common
// alignments because __declspec(align(...)) doesn't actually work when it
is
// a member of a by-value function argument in MSVC, even if the alignment
// request is something reasonably like 8-byte or 16-byte.
template <> struct AlignedCharArrayImpl<1> { char aligned; };
template <> struct AlignedCharArrayImpl<2> { short aligned; };
template <> struct AlignedCharArrayImpl<4> { int aligned; };
template <> struct AlignedCharArrayImpl<8> { double aligned; };
#define LLVM_ALIGNEDCHARARRAY_TEMPLATE_ALIGNMENT(x) \
template <> struct AlignedCharArrayImpl<x> { \
__declspec(align(x)) char aligned; \
}
LLVM_ALIGNEDCHARARRAY_TEMPLATE_ALIGNMENT(16);
LLVM_ALIGNEDCHARARRAY_TEMPLATE_ALIGNMENT(32);
LLVM_ALIGNEDCHARARRAY_TEMPLATE_ALIGNMENT(64);
LLVM_ALIGNEDCHARARRAY_TEMPLATE_ALIGNMENT(128);
LLVM_ALIGNEDCHARARRAY_TEMPLATE_ALIGNMENT(512);
LLVM_ALIGNEDCHARARRAY_TEMPLATE_ALIGNMENT(1024);
LLVM_ALIGNEDCHARARRAY_TEMPLATE_ALIGNMENT(2048);
LLVM_ALIGNEDCHARARRAY_TEMPLATE_ALIGNMENT(4096);
LLVM_ALIGNEDCHARARRAY_TEMPLATE_ALIGNMENT(8192);
// Any larger and MSVC complains.
#undef LLVM_ALIGNEDCHARARRAY_TEMPLATE_ALIGNMENT
#endif // _MSC_VER
/// \brief This union template exposes a suitably aligned and sized charact
er
/// array member which can hold elements of any of up to four types.
///
/// These types may be arrays, structs, or any other types. The goal is to
/// produce a union type containing a character array which, when used, for
ms
/// storage suitable to placement new any of these types over. Support for
more
/// than four types can be added at the cost of more boiler plate.
template <typename T1,
typename T2 = char, typename T3 = char, typename T4 = char>
union AlignedCharArrayUnion {
private:
class AlignerImpl {
T1 t1; T2 t2; T3 t3; T4 t4;
AlignerImpl(); // Never defined or instantiated.
};
union SizerImpl {
char arr1[sizeof(T1)], arr2[sizeof(T2)], arr3[sizeof(T3)], arr4[sizeof(
T4)];
};
public:
/// \brief The character array buffer for use by clients.
///
/// No other member of this union should be referenced. The exist purely
to
/// constrain the layout of this character array.
char buffer[sizeof(SizerImpl)];
private:
// Tests seem to indicate that both Clang and GCC will properly register
the
// alignment of a struct containing an aligned member, and this alignment
// should carry over to the character array in the union.
llvm::AlignedCharArrayImpl<AlignOf<AlignerImpl>::Alignment> nonce_member;
};
} // end namespace llvm } // end namespace llvm
#endif #endif
 End of changes. 2 change blocks. 
1 lines changed or deleted 118 lines changed or added


 Allocator.h   Allocator.h 
skipping to change at line 82 skipping to change at line 82
/// is an adapter class for MallocAllocator that just forwards the method /// is an adapter class for MallocAllocator that just forwards the method
/// calls and translates the arguments. /// calls and translates the arguments.
class MallocSlabAllocator : public SlabAllocator { class MallocSlabAllocator : public SlabAllocator {
/// Allocator - The underlying allocator that we forward to. /// Allocator - The underlying allocator that we forward to.
/// ///
MallocAllocator Allocator; MallocAllocator Allocator;
public: public:
MallocSlabAllocator() : Allocator() { } MallocSlabAllocator() : Allocator() { }
virtual ~MallocSlabAllocator(); virtual ~MallocSlabAllocator();
virtual MemSlab *Allocate(size_t Size); virtual MemSlab *Allocate(size_t Size) LLVM_OVERRIDE;
virtual void Deallocate(MemSlab *Slab); virtual void Deallocate(MemSlab *Slab) LLVM_OVERRIDE;
}; };
/// BumpPtrAllocator - This allocator is useful for containers that need /// BumpPtrAllocator - This allocator is useful for containers that need
/// very simple memory allocation strategies. In particular, this just kee ps /// very simple memory allocation strategies. In particular, this just kee ps
/// allocating memory, and never deletes it until the entire block is dead. This /// allocating memory, and never deletes it until the entire block is dead. This
/// makes allocation speedy, but must only be used when the trade-off is ok . /// makes allocation speedy, but must only be used when the trade-off is ok .
class BumpPtrAllocator { class BumpPtrAllocator {
BumpPtrAllocator(const BumpPtrAllocator &); // do not implement BumpPtrAllocator(const BumpPtrAllocator &) LLVM_DELETED_FUNCTION;
void operator=(const BumpPtrAllocator &); // do not implement void operator=(const BumpPtrAllocator &) LLVM_DELETED_FUNCTION;
/// SlabSize - Allocate data into slabs of this size unless we get an /// SlabSize - Allocate data into slabs of this size unless we get an
/// allocation above SizeThreshold. /// allocation above SizeThreshold.
size_t SlabSize; size_t SlabSize;
/// SizeThreshold - For any allocation larger than this threshold, we sho uld /// SizeThreshold - For any allocation larger than this threshold, we sho uld
/// allocate a separate slab. /// allocate a separate slab.
size_t SizeThreshold; size_t SizeThreshold;
/// Allocator - The underlying allocator we use to get slabs of memory. This /// Allocator - The underlying allocator we use to get slabs of memory. This
 End of changes. 2 change blocks. 
4 lines changed or deleted 4 lines changed or added


 Archive.h   Archive.h 
skipping to change at line 132 skipping to change at line 132
Archive(MemoryBuffer *source, error_code &ec); Archive(MemoryBuffer *source, error_code &ec);
child_iterator begin_children(bool skip_internal = true) const; child_iterator begin_children(bool skip_internal = true) const;
child_iterator end_children() const; child_iterator end_children() const;
symbol_iterator begin_symbols() const; symbol_iterator begin_symbols() const;
symbol_iterator end_symbols() const; symbol_iterator end_symbols() const;
// Cast methods. // Cast methods.
static inline bool classof(Archive const *v) { return true; }
static inline bool classof(Binary const *v) { static inline bool classof(Binary const *v) {
return v->isArchive(); return v->isArchive();
} }
private: private:
child_iterator SymbolTable; child_iterator SymbolTable;
child_iterator StringTable; child_iterator StringTable;
}; };
} }
 End of changes. 1 change blocks. 
1 lines changed or deleted 0 lines changed or added


 Argument.h   Argument.h 
skipping to change at line 71 skipping to change at line 71
bool hasNestAttr() const; bool hasNestAttr() const;
/// hasNoAliasAttr - Return true if this argument has the noalias attribu te on /// hasNoAliasAttr - Return true if this argument has the noalias attribu te on
/// it in its containing function. /// it in its containing function.
bool hasNoAliasAttr() const; bool hasNoAliasAttr() const;
/// hasNoCaptureAttr - Return true if this argument has the nocapture /// hasNoCaptureAttr - Return true if this argument has the nocapture
/// attribute on it in its containing function. /// attribute on it in its containing function.
bool hasNoCaptureAttr() const; bool hasNoCaptureAttr() const;
/// hasSRetAttr - Return true if this argument has the sret attribute on /// hasStructRetAttr - Return true if this argument has the sret attribut
it in e on
/// its containing function. /// it in its containing function.
bool hasStructRetAttr() const; bool hasStructRetAttr() const;
/// addAttr - Add a Attribute to an argument /// addAttr - Add a Attribute to an argument
void addAttr(Attributes); void addAttr(Attributes);
/// removeAttr - Remove a Attribute from an argument /// removeAttr - Remove a Attribute from an argument
void removeAttr(Attributes); void removeAttr(Attributes);
/// classof - Methods for support type inquiry through isa, cast, and /// classof - Methods for support type inquiry through isa, cast, and
/// dyn_cast: /// dyn_cast:
/// ///
static inline bool classof(const Argument *) { return true; }
static inline bool classof(const Value *V) { static inline bool classof(const Value *V) {
return V->getValueID() == ArgumentVal; return V->getValueID() == ArgumentVal;
} }
}; };
} // End llvm namespace } // End llvm namespace
#endif #endif
 End of changes. 2 change blocks. 
4 lines changed or deleted 3 lines changed or added


 ArrayRef.h   ArrayRef.h 
skipping to change at line 62 skipping to change at line 62
: Data(&OneElt), Length(1) {} : Data(&OneElt), Length(1) {}
/// Construct an ArrayRef from a pointer and length. /// Construct an ArrayRef from a pointer and length.
/*implicit*/ ArrayRef(const T *data, size_t length) /*implicit*/ ArrayRef(const T *data, size_t length)
: Data(data), Length(length) {} : Data(data), Length(length) {}
/// Construct an ArrayRef from a range. /// Construct an ArrayRef from a range.
ArrayRef(const T *begin, const T *end) ArrayRef(const T *begin, const T *end)
: Data(begin), Length(end - begin) {} : Data(begin), Length(end - begin) {}
/// Construct an ArrayRef from a SmallVector. /// Construct an ArrayRef from a SmallVector. This is templated in orde
/*implicit*/ ArrayRef(const SmallVectorImpl<T> &Vec) r to
: Data(Vec.data()), Length(Vec.size()) {} /// avoid instantiating SmallVectorTemplateCommon<T> whenever we
/// copy-construct an ArrayRef.
template<typename U>
/*implicit*/ ArrayRef(const SmallVectorTemplateCommon<T, U> &Vec)
: Data(Vec.data()), Length(Vec.size()) {
}
/// Construct an ArrayRef from a std::vector. /// Construct an ArrayRef from a std::vector.
/*implicit*/ ArrayRef(const std::vector<T> &Vec) template<typename A>
/*implicit*/ ArrayRef(const std::vector<T, A> &Vec)
: Data(Vec.empty() ? (T*)0 : &Vec[0]), Length(Vec.size()) {} : Data(Vec.empty() ? (T*)0 : &Vec[0]), Length(Vec.size()) {}
/// Construct an ArrayRef from a C array. /// Construct an ArrayRef from a C array.
template <size_t N> template <size_t N>
/*implicit*/ ArrayRef(const T (&Arr)[N]) /*implicit*/ ArrayRef(const T (&Arr)[N])
: Data(Arr), Length(N) {} : Data(Arr), Length(N) {}
/// @} /// @}
/// @name Simple Operations /// @name Simple Operations
/// @{ /// @{
 End of changes. 2 change blocks. 
4 lines changed or deleted 10 lines changed or added


 AsmLexer.h   AsmLexer.h 
skipping to change at line 34 skipping to change at line 34
class MCAsmInfo; class MCAsmInfo;
/// AsmLexer - Lexer class for assembly files. /// AsmLexer - Lexer class for assembly files.
class AsmLexer : public MCAsmLexer { class AsmLexer : public MCAsmLexer {
const MCAsmInfo &MAI; const MCAsmInfo &MAI;
const char *CurPtr; const char *CurPtr;
const MemoryBuffer *CurBuf; const MemoryBuffer *CurBuf;
bool isAtStartOfLine; bool isAtStartOfLine;
void operator=(const AsmLexer&); // DO NOT IMPLEMENT void operator=(const AsmLexer&) LLVM_DELETED_FUNCTION;
AsmLexer(const AsmLexer&); // DO NOT IMPLEMENT AsmLexer(const AsmLexer&) LLVM_DELETED_FUNCTION;
protected: protected:
/// LexToken - Read the next token and return its code. /// LexToken - Read the next token and return its code.
virtual AsmToken LexToken(); virtual AsmToken LexToken();
public: public:
AsmLexer(const MCAsmInfo &MAI); AsmLexer(const MCAsmInfo &MAI);
~AsmLexer(); ~AsmLexer();
void setBuffer(const MemoryBuffer *buf, const char *ptr = NULL); void setBuffer(const MemoryBuffer *buf, const char *ptr = NULL);
 End of changes. 1 change blocks. 
2 lines changed or deleted 2 lines changed or added


 AsmParsers.def   AsmParsers.def 
//===- llvm/Config/AsmParsers.def - LLVM Assembly Parsers -------*- C++ -*- /*===- llvm/Config/AsmParsers.def - LLVM Assembly Parsers -------*- C++ -*-
===// ===*\
// |*
// The LLVM Compiler Infrastructure *|
// |* The LLVM Compiler Infrastructure
// This file is distributed under the University of Illinois Open Source *|
// License. See LICENSE.TXT for details. |*
// *|
//===---------------------------------------------------------------------- |* This file is distributed under the University of Illinois Open Source
===// *|
// |* License. See LICENSE.TXT for details.
// This file enumerates all of the assembly-language parsers *|
// supported by this build of LLVM. Clients of this file should define |*
// the LLVM_ASM_PARSER macro to be a function-like macro with a *|
// single parameter (the name of the target whose assembly can be |*===----------------------------------------------------------------------
// generated); including this file will then enumerate all of the ===*|
// targets with assembly parsers. |*
// *|
// The set of targets supported by LLVM is generated at configuration |* This file enumerates all of the assembly-language parsers
// time, at which point this header is generated. Do not modify this *|
// header directly. |* supported by this build of LLVM. Clients of this file should define
// *|
//===---------------------------------------------------------------------- |* the LLVM_ASM_PARSER macro to be a function-like macro with a
===// *|
|* single parameter (the name of the target whose assembly can be
*|
|* generated); including this file will then enumerate all of the
*|
|* targets with assembly parsers.
*|
|*
*|
|* The set of targets supported by LLVM is generated at configuration
*|
|* time, at which point this header is generated. Do not modify this
*|
|* header directly.
*|
|*
*|
\*===----------------------------------------------------------------------
===*/
#ifndef LLVM_ASM_PARSER #ifndef LLVM_ASM_PARSER
# error Please define the macro LLVM_ASM_PARSER(TargetName) # error Please define the macro LLVM_ASM_PARSER(TargetName)
#endif #endif
LLVM_ASM_PARSER(MBlaze) LLVM_ASM_PARSER(Mips) LLVM_ASM_PARSER(ARM) LLVM_ASM _PARSER(X86) LLVM_ASM_PARSER(MBlaze) LLVM_ASM_PARSER(Mips) LLVM_ASM_PARSER(ARM) LLVM_ASM _PARSER(X86)
#undef LLVM_ASM_PARSER #undef LLVM_ASM_PARSER
 End of changes. 1 change blocks. 
24 lines changed or deleted 42 lines changed or added


 AsmPrinter.h   AsmPrinter.h 
skipping to change at line 20 skipping to change at line 20
// This file contains a class to be used as the base class for target speci fic // This file contains a class to be used as the base class for target speci fic
// asm writers. This class primarily handles common functionality used by // asm writers. This class primarily handles common functionality used by
// all asm writers. // all asm writers.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_CODEGEN_ASMPRINTER_H #ifndef LLVM_CODEGEN_ASMPRINTER_H
#define LLVM_CODEGEN_ASMPRINTER_H #define LLVM_CODEGEN_ASMPRINTER_H
#include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/InlineAsm.h"
#include "llvm/Support/DataTypes.h" #include "llvm/Support/DataTypes.h"
#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/ErrorHandling.h"
namespace llvm { namespace llvm {
class BlockAddress; class BlockAddress;
class GCStrategy; class GCStrategy;
class Constant; class Constant;
class GCMetadataPrinter; class GCMetadataPrinter;
class GlobalValue; class GlobalValue;
class GlobalVariable; class GlobalVariable;
skipping to change at line 50 skipping to change at line 51
class MCAsmInfo; class MCAsmInfo;
class MCContext; class MCContext;
class MCSection; class MCSection;
class MCStreamer; class MCStreamer;
class MCSymbol; class MCSymbol;
class MDNode; class MDNode;
class DwarfDebug; class DwarfDebug;
class DwarfException; class DwarfException;
class Mangler; class Mangler;
class TargetLoweringObjectFile; class TargetLoweringObjectFile;
class TargetData; class DataLayout;
class TargetMachine; class TargetMachine;
/// AsmPrinter - This class is intended to be used as a driving class for all /// AsmPrinter - This class is intended to be used as a driving class for all
/// asm writers. /// asm writers.
class AsmPrinter : public MachineFunctionPass { class AsmPrinter : public MachineFunctionPass {
public: public:
/// Target machine description. /// Target machine description.
/// ///
TargetMachine &TM; TargetMachine &TM;
skipping to change at line 133 skipping to change at line 134
/// ///
bool isVerbose() const { return VerboseAsm; } bool isVerbose() const { return VerboseAsm; }
/// getFunctionNumber - Return a unique ID for the current function. /// getFunctionNumber - Return a unique ID for the current function.
/// ///
unsigned getFunctionNumber() const; unsigned getFunctionNumber() const;
/// getObjFileLowering - Return information about object file lowering. /// getObjFileLowering - Return information about object file lowering.
const TargetLoweringObjectFile &getObjFileLowering() const; const TargetLoweringObjectFile &getObjFileLowering() const;
/// getTargetData - Return information about data layout. /// getDataLayout - Return information about data layout.
const TargetData &getTargetData() const; const DataLayout &getDataLayout() const;
/// getCurrentSection() - Return the current section we are emitting to . /// getCurrentSection() - Return the current section we are emitting to .
const MCSection *getCurrentSection() const; const MCSection *getCurrentSection() const;
//===------------------------------------------------------------------ ===// //===------------------------------------------------------------------ ===//
// MachineFunctionPass Implementation. // MachineFunctionPass Implementation.
//===------------------------------------------------------------------ ===// //===------------------------------------------------------------------ ===//
/// getAnalysisUsage - Record analysis usage. /// getAnalysisUsage - Record analysis usage.
/// ///
skipping to change at line 354 skipping to change at line 355
/// specify the labels. This implicitly uses .set if it is available. /// specify the labels. This implicitly uses .set if it is available.
void EmitLabelOffsetDifference(const MCSymbol *Hi, uint64_t Offset, void EmitLabelOffsetDifference(const MCSymbol *Hi, uint64_t Offset,
const MCSymbol *Lo, unsigned Size) const ; const MCSymbol *Lo, unsigned Size) const ;
/// EmitLabelPlusOffset - Emit something like ".long Label+Offset" /// EmitLabelPlusOffset - Emit something like ".long Label+Offset"
/// where the size in bytes of the directive is specified by Size and L abel /// where the size in bytes of the directive is specified by Size and L abel
/// specifies the label. This implicitly uses .set if it is available. /// specifies the label. This implicitly uses .set if it is available.
void EmitLabelPlusOffset(const MCSymbol *Label, uint64_t Offset, void EmitLabelPlusOffset(const MCSymbol *Label, uint64_t Offset,
unsigned Size) const; unsigned Size) const;
/// EmitLabelReference - Emit something like ".long Label"
/// where the size in bytes of the directive is specified by Size and L
abel
/// specifies the label.
void EmitLabelReference(const MCSymbol *Label, unsigned Size) const {
EmitLabelPlusOffset(Label, 0, Size);
}
//===------------------------------------------------------------------ ===// //===------------------------------------------------------------------ ===//
// Dwarf Emission Helper Routines // Dwarf Emission Helper Routines
//===------------------------------------------------------------------ ===// //===------------------------------------------------------------------ ===//
/// EmitSLEB128 - emit the specified signed leb128 value. /// EmitSLEB128 - emit the specified signed leb128 value.
void EmitSLEB128(int Value, const char *Desc = 0) const; void EmitSLEB128(int Value, const char *Desc = 0) const;
/// EmitULEB128 - emit the specified unsigned leb128 value. /// EmitULEB128 - emit the specified unsigned leb128 value.
void EmitULEB128(unsigned Value, const char *Desc = 0, void EmitULEB128(unsigned Value, const char *Desc = 0,
unsigned PadTo = 0) const; unsigned PadTo = 0) const;
skipping to change at line 453 skipping to change at line 461
private: private:
/// Private state for PrintSpecial() /// Private state for PrintSpecial()
// Assign a unique ID to this machine instruction. // Assign a unique ID to this machine instruction.
mutable const MachineInstr *LastMI; mutable const MachineInstr *LastMI;
mutable unsigned LastFn; mutable unsigned LastFn;
mutable unsigned Counter; mutable unsigned Counter;
mutable unsigned SetCounter; mutable unsigned SetCounter;
/// EmitInlineAsm - Emit a blob of inline asm to the output streamer. /// EmitInlineAsm - Emit a blob of inline asm to the output streamer.
void EmitInlineAsm(StringRef Str, const MDNode *LocMDNode = 0) const; void EmitInlineAsm(StringRef Str, const MDNode *LocMDNode = 0,
InlineAsm::AsmDialect AsmDialect = InlineAsm::AD_ATT) c
onst;
/// EmitInlineAsm - This method formats and emits the specified machine /// EmitInlineAsm - This method formats and emits the specified machine
/// instruction that is an inline asm. /// instruction that is an inline asm.
void EmitInlineAsm(const MachineInstr *MI) const; void EmitInlineAsm(const MachineInstr *MI) const;
//===------------------------------------------------------------------ ===// //===------------------------------------------------------------------ ===//
// Internal Implementation Details // Internal Implementation Details
//===------------------------------------------------------------------ ===// //===------------------------------------------------------------------ ===//
/// EmitVisibility - This emits visibility information about symbol, if /// EmitVisibility - This emits visibility information about symbol, if
 End of changes. 5 change blocks. 
4 lines changed or deleted 15 lines changed or added


 AsmPrinters.def   AsmPrinters.def 
//===- llvm/Config/AsmPrinters.def - LLVM Assembly Printers -----*- C++ -*- /*===- llvm/Config/AsmPrinters.def - LLVM Assembly Printers -----*- C++ -*-
===// ===*\
// |*
// The LLVM Compiler Infrastructure *|
// |* The LLVM Compiler Infrastructure
// This file is distributed under the University of Illinois Open Source *|
// License. See LICENSE.TXT for details. |*
// *|
//===---------------------------------------------------------------------- |* This file is distributed under the University of Illinois Open Source
===// *|
// |* License. See LICENSE.TXT for details.
// This file enumerates all of the assembly-language printers *|
// supported by this build of LLVM. Clients of this file should define |*
// the LLVM_ASM_PRINTER macro to be a function-like macro with a *|
// single parameter (the name of the target whose assembly can be |*===----------------------------------------------------------------------
// generated); including this file will then enumerate all of the ===*|
// targets with assembly printers. |*
// *|
// The set of targets supported by LLVM is generated at configuration |* This file enumerates all of the assembly-language printers
// time, at which point this header is generated. Do not modify this *|
// header directly. |* supported by this build of LLVM. Clients of this file should define
// *|
//===---------------------------------------------------------------------- |* the LLVM_ASM_PRINTER macro to be a function-like macro with a
===// *|
|* single parameter (the name of the target whose assembly can be
*|
|* generated); including this file will then enumerate all of the
*|
|* targets with assembly printers.
*|
|*
*|
|* The set of targets supported by LLVM is generated at configuration
*|
|* time, at which point this header is generated. Do not modify this
*|
|* header directly.
*|
|*
*|
\*===----------------------------------------------------------------------
===*/
#ifndef LLVM_ASM_PRINTER #ifndef LLVM_ASM_PRINTER
# error Please define the macro LLVM_ASM_PRINTER(TargetName) # error Please define the macro LLVM_ASM_PRINTER(TargetName)
#endif #endif
LLVM_ASM_PRINTER(Hexagon) LLVM_ASM_PRINTER(PTX) LLVM_ASM_PRINTER(MBlaze) LL VM_ASM_PRINTER(MSP430) LLVM_ASM_PRINTER(XCore) LLVM_ASM_PRINTER(CellSPU) LL VM_ASM_PRINTER(Mips) LLVM_ASM_PRINTER(ARM) LLVM_ASM_PRINTER(PowerPC) LLVM_A SM_PRINTER(Sparc) LLVM_ASM_PRINTER(X86) LLVM_ASM_PRINTER(Hexagon) LLVM_ASM_PRINTER(NVPTX) LLVM_ASM_PRINTER(MBlaze) LLVM_ASM_PRINTER(MSP430) LLVM_ASM_PRINTER(XCore) LLVM_ASM_PRINTER(CellSPU) LLVM_ASM_PRINTER(Mips) LLVM_ASM_PRINTER(ARM) LLVM_ASM_PRINTER(PowerPC) LLVM _ASM_PRINTER(Sparc) LLVM_ASM_PRINTER(X86)
#undef LLVM_ASM_PRINTER #undef LLVM_ASM_PRINTER
 End of changes. 2 change blocks. 
25 lines changed or deleted 43 lines changed or added


 Attributes.h   Attributes.h 
skipping to change at line 19 skipping to change at line 19
// //
// This file contains the simple types necessary to represent the // This file contains the simple types necessary to represent the
// attributes associated with functions and their calls. // attributes associated with functions and their calls.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_ATTRIBUTES_H #ifndef LLVM_ATTRIBUTES_H
#define LLVM_ATTRIBUTES_H #define LLVM_ATTRIBUTES_H
#include "llvm/Support/MathExtras.h" #include "llvm/Support/MathExtras.h"
#include "llvm/ADT/ArrayRef.h"
#include <cassert> #include <cassert>
#include <string> #include <string>
namespace llvm { namespace llvm {
class Type;
namespace Attribute { class AttrBuilder;
/// We use this proxy POD type to allow constructing Attributes constants class AttributesImpl;
/// using initializer lists. Do not use this class directly. class LLVMContext;
struct AttrConst { class Type;
uint64_t v;
AttrConst operator | (const AttrConst Attrs) const {
AttrConst Res = {v | Attrs.v};
return Res;
}
AttrConst operator ~ () const {
AttrConst Res = {~v};
return Res;
}
};
} // namespace Attribute
/// Attributes - A bitset of attributes. /// Attributes - A bitset of attributes.
class Attributes { class Attributes {
public: public:
Attributes() : Bits(0) { } /// Function parameters and results can have attributes to indicate how t
explicit Attributes(uint64_t Val) : Bits(Val) { } hey
/*implicit*/ Attributes(Attribute::AttrConst Val) : Bits(Val.v) { } /// should be treated by optimizations and code generation. This enumerat
Attributes(const Attributes &Attrs) : Bits(Attrs.Bits) { } ion
// This is a "safe bool() operator". /// lists the attributes that can be associated with parameters, function
operator const void *() const { return Bits ? this : 0; } /// results or the function itself.
bool isEmptyOrSingleton() const { return (Bits & (Bits - 1)) == 0; } ///
Attributes &operator = (const Attributes &Attrs) { /// Note that uwtable is about the ABI or the user mandating an entry in
Bits = Attrs.Bits; the
return *this; /// unwind table. The nounwind attribute is about an exception passing by
} the
bool operator == (const Attributes &Attrs) const { /// function.
return Bits == Attrs.Bits; ///
} /// In a theoretical system that uses tables for profiling and sjlj for
bool operator != (const Attributes &Attrs) const { /// exceptions, they would be fully independent. In a normal system that
return Bits != Attrs.Bits; uses
} /// tables for both, the semantics are:
Attributes operator | (const Attributes &Attrs) const { ///
return Attributes(Bits | Attrs.Bits); /// nil = Needs an entry because an exception might pass b
} y.
Attributes operator & (const Attributes &Attrs) const { /// nounwind = No need for an entry
return Attributes(Bits & Attrs.Bits); /// uwtable = Needs an entry because the ABI says so and becau
} se
Attributes operator ^ (const Attributes &Attrs) const { /// an exception might pass by.
return Attributes(Bits ^ Attrs.Bits); /// uwtable + nounwind = Needs an entry because the ABI says so.
}
Attributes &operator |= (const Attributes &Attrs) { enum AttrVal {
Bits |= Attrs.Bits; // IR-Level Attributes
return *this; None, ///< No attributes have been set
} AddressSafety, ///< Address safety checking is on.
Attributes &operator &= (const Attributes &Attrs) { Alignment, ///< Alignment of parameter (5 bits)
Bits &= Attrs.Bits; ///< stored as log2 of alignment with +1 bias
///< 0 means unaligned different from align 1
AlwaysInline, ///< inline=always
ByVal, ///< Pass structure by value
InlineHint, ///< Source said inlining was desirable
InReg, ///< Force argument to be passed in register
MinSize, ///< Function must be optimized for size first
Naked, ///< Naked function
Nest, ///< Nested function static chain
NoAlias, ///< Considered to not alias after call
NoCapture, ///< Function creates no aliases of pointer
NoImplicitFloat, ///< Disable implicit floating point insts
NoInline, ///< inline=never
NonLazyBind, ///< Function is called early and/or
///< often, so lazy binding isn't worthwhile
NoRedZone, ///< Disable redzone
NoReturn, ///< Mark the function as not returning
NoUnwind, ///< Function doesn't unwind stack
OptimizeForSize, ///< opt_size
ReadNone, ///< Function does not access memory
ReadOnly, ///< Function only reads from memory
ReturnsTwice, ///< Function can return twice
SExt, ///< Sign extended before/after call
StackAlignment, ///< Alignment of stack for function (3 bits)
///< stored as log2 of alignment with +1 bias 0
///< means unaligned (different from
///< alignstack={1))
StackProtect, ///< Stack protection.
StackProtectReq, ///< Stack protection required.
StructRet, ///< Hidden pointer to structure to return
UWTable, ///< Function must be in a unwind table
ZExt ///< Zero extended before/after call
};
private:
AttributesImpl *Attrs;
Attributes(AttributesImpl *A) : Attrs(A) {}
public:
Attributes() : Attrs(0) {}
Attributes(const Attributes &A) : Attrs(A.Attrs) {}
Attributes &operator=(const Attributes &A) {
Attrs = A.Attrs;
return *this; return *this;
} }
Attributes operator ~ () const { return Attributes(~Bits); }
uint64_t Raw() const { return Bits; } /// get - Return a uniquified Attributes object. This takes the uniquifie
private: d
// Currently, we need less than 64 bits. /// value from the Builder and wraps it in the Attributes class.
uint64_t Bits; static Attributes get(LLVMContext &Context, ArrayRef<AttrVal> Vals);
static Attributes get(LLVMContext &Context, AttrBuilder &B);
/// @brief Return true if the attribute is present.
bool hasAttribute(AttrVal Val) const;
/// @brief Return true if attributes exist
bool hasAttributes() const;
/// @brief Return true if the attributes are a non-null intersection.
bool hasAttributes(const Attributes &A) const;
/// @brief Returns the alignment field of an attribute as a byte alignmen
t
/// value.
unsigned getAlignment() const;
/// @brief Returns the stack alignment field of an attribute as a byte
/// alignment value.
unsigned getStackAlignment() const;
/// @brief Parameter attributes that do not apply to vararg call argument
s.
bool hasIncompatibleWithVarArgsAttrs() const {
return hasAttribute(Attributes::StructRet);
}
/// @brief Attributes that only apply to function parameters.
bool hasParameterOnlyAttrs() const {
return hasAttribute(Attributes::ByVal) ||
hasAttribute(Attributes::Nest) ||
hasAttribute(Attributes::StructRet) ||
hasAttribute(Attributes::NoCapture);
}
/// @brief Attributes that may be applied to the function itself. These
cannot
/// be used on return values or function parameters.
bool hasFunctionOnlyAttrs() const {
return hasAttribute(Attributes::NoReturn) ||
hasAttribute(Attributes::NoUnwind) ||
hasAttribute(Attributes::ReadNone) ||
hasAttribute(Attributes::ReadOnly) ||
hasAttribute(Attributes::NoInline) ||
hasAttribute(Attributes::AlwaysInline) ||
hasAttribute(Attributes::OptimizeForSize) ||
hasAttribute(Attributes::StackProtect) ||
hasAttribute(Attributes::StackProtectReq) ||
hasAttribute(Attributes::NoRedZone) ||
hasAttribute(Attributes::NoImplicitFloat) ||
hasAttribute(Attributes::Naked) ||
hasAttribute(Attributes::InlineHint) ||
hasAttribute(Attributes::StackAlignment) ||
hasAttribute(Attributes::UWTable) ||
hasAttribute(Attributes::NonLazyBind) ||
hasAttribute(Attributes::ReturnsTwice) ||
hasAttribute(Attributes::AddressSafety) ||
hasAttribute(Attributes::MinSize);
}
bool operator==(const Attributes &A) const {
return Attrs == A.Attrs;
}
bool operator!=(const Attributes &A) const {
return Attrs != A.Attrs;
}
uint64_t Raw() const;
/// @brief Which attributes cannot be applied to a type.
static Attributes typeIncompatible(Type *Ty);
/// encodeLLVMAttributesForBitcode - This returns an integer containing a
n
/// encoding of all the LLVM attributes found in the given attribute bits
et.
/// Any change to this encoding is a breaking change to bitcode compatibi
lity.
static uint64_t encodeLLVMAttributesForBitcode(Attributes Attrs);
/// decodeLLVMAttributesForBitcode - This returns an attribute bitset
/// containing the LLVM attributes that have been decoded from the given
/// integer. This function must stay in sync with
/// 'encodeLLVMAttributesForBitcode'.
static Attributes decodeLLVMAttributesForBitcode(LLVMContext &C,
uint64_t EncodedAttrs);
/// getAsString - The set of Attributes set in Attributes is converted to
a
/// string of equivalent mnemonics. This is, presumably, for writing out
the
/// mnemonics for the assembly writer.
/// @brief Convert attribute bits to text
std::string getAsString() const;
}; };
namespace Attribute { //===----------------------------------------------------------------------
===//
/// AttrBuilder - This class is used in conjunction with the Attributes::ge
t
/// method to create an Attributes object. The object itself is uniquified.
The
/// Builder's value, however, is not. So this can be used as a quick way to
test
/// for equality, presence of attributes, etc.
class AttrBuilder {
uint64_t Bits;
public:
AttrBuilder() : Bits(0) {}
explicit AttrBuilder(uint64_t B) : Bits(B) {}
AttrBuilder(const Attributes &A) : Bits(A.Raw()) {}
AttrBuilder(const AttrBuilder &B) : Bits(B.Bits) {}
void clear() { Bits = 0; }
/// addAttribute - Add an attribute to the builder.
AttrBuilder &addAttribute(Attributes::AttrVal Val);
/// removeAttribute - Remove an attribute from the builder.
AttrBuilder &removeAttribute(Attributes::AttrVal Val);
/// addAttribute - Add the attributes from A to the builder.
AttrBuilder &addAttributes(const Attributes &A);
/// removeAttribute - Remove the attributes from A from the builder.
AttrBuilder &removeAttributes(const Attributes &A);
/// hasAttribute - Return true if the builder has the specified attribute
.
bool hasAttribute(Attributes::AttrVal A) const;
/// hasAttributes - Return true if the builder has IR-level attributes.
bool hasAttributes() const;
/// hasAttributes - Return true if the builder has any attribute that's i
n the
/// specified attribute.
bool hasAttributes(const Attributes &A) const;
/// hasAlignmentAttr - Return true if the builder has an alignment attrib
ute.
bool hasAlignmentAttr() const;
/// getAlignment - Retrieve the alignment attribute, if it exists.
uint64_t getAlignment() const;
/// getStackAlignment - Retrieve the stack alignment attribute, if it exi
sts.
uint64_t getStackAlignment() const;
/// addAlignmentAttr - This turns an int alignment (which must be a power
of
/// 2) into the form used internally in Attributes.
AttrBuilder &addAlignmentAttr(unsigned Align);
/// addStackAlignmentAttr - This turns an int stack alignment (which must
be a
/// power of 2) into the form used internally in Attributes.
AttrBuilder &addStackAlignmentAttr(unsigned Align);
/// addRawValue - Add the raw value to the internal representation.
/// N.B. This should be used ONLY for decoding LLVM bitcode!
AttrBuilder &addRawValue(uint64_t Val);
/// @brief Remove attributes that are used on functions only.
void removeFunctionOnlyAttrs() {
removeAttribute(Attributes::NoReturn)
.removeAttribute(Attributes::NoUnwind)
.removeAttribute(Attributes::ReadNone)
.removeAttribute(Attributes::ReadOnly)
.removeAttribute(Attributes::NoInline)
.removeAttribute(Attributes::AlwaysInline)
.removeAttribute(Attributes::OptimizeForSize)
.removeAttribute(Attributes::StackProtect)
.removeAttribute(Attributes::StackProtectReq)
.removeAttribute(Attributes::NoRedZone)
.removeAttribute(Attributes::NoImplicitFloat)
.removeAttribute(Attributes::Naked)
.removeAttribute(Attributes::InlineHint)
.removeAttribute(Attributes::StackAlignment)
.removeAttribute(Attributes::UWTable)
.removeAttribute(Attributes::NonLazyBind)
.removeAttribute(Attributes::ReturnsTwice)
.removeAttribute(Attributes::AddressSafety)
.removeAttribute(Attributes::MinSize);
}
uint64_t Raw() const { return Bits; }
/// Function parameters and results can have attributes to indicate how the bool operator==(const AttrBuilder &B) {
y return Bits == B.Bits;
/// should be treated by optimizations and code generation. This enumeratio }
n bool operator!=(const AttrBuilder &B) {
/// lists the attributes that can be associated with parameters, function return Bits != B.Bits;
/// results or the function itself. }
/// @brief Function attributes.
// We declare AttrConst objects that will be used throughout the code
// and also raw uint64_t objects with _i suffix to be used below for other
// constant declarations. This is done to avoid static CTORs and at the sam
e
// time to keep type-safety of Attributes.
#define DECLARE_LLVM_ATTRIBUTE(name, value) \
const uint64_t name##_i = value; \
const AttrConst name = {value};
DECLARE_LLVM_ATTRIBUTE(None,0) ///< No attributes have been set
DECLARE_LLVM_ATTRIBUTE(ZExt,1<<0) ///< Zero extended before/after call
DECLARE_LLVM_ATTRIBUTE(SExt,1<<1) ///< Sign extended before/after call
DECLARE_LLVM_ATTRIBUTE(NoReturn,1<<2) ///< Mark the function as not returni
ng
DECLARE_LLVM_ATTRIBUTE(InReg,1<<3) ///< Force argument to be passed in regi
ster
DECLARE_LLVM_ATTRIBUTE(StructRet,1<<4) ///< Hidden pointer to structure to
return
DECLARE_LLVM_ATTRIBUTE(NoUnwind,1<<5) ///< Function doesn't unwind stack
DECLARE_LLVM_ATTRIBUTE(NoAlias,1<<6) ///< Considered to not alias after cal
l
DECLARE_LLVM_ATTRIBUTE(ByVal,1<<7) ///< Pass structure by value
DECLARE_LLVM_ATTRIBUTE(Nest,1<<8) ///< Nested function static chain
DECLARE_LLVM_ATTRIBUTE(ReadNone,1<<9) ///< Function does not access memory
DECLARE_LLVM_ATTRIBUTE(ReadOnly,1<<10) ///< Function only reads from memory
DECLARE_LLVM_ATTRIBUTE(NoInline,1<<11) ///< inline=never
DECLARE_LLVM_ATTRIBUTE(AlwaysInline,1<<12) ///< inline=always
DECLARE_LLVM_ATTRIBUTE(OptimizeForSize,1<<13) ///< opt_size
DECLARE_LLVM_ATTRIBUTE(StackProtect,1<<14) ///< Stack protection.
DECLARE_LLVM_ATTRIBUTE(StackProtectReq,1<<15) ///< Stack protection require
d.
DECLARE_LLVM_ATTRIBUTE(Alignment,31<<16) ///< Alignment of parameter (5 bit
s)
// stored as log2 of alignment with +1
bias
// 0 means unaligned different from al
ign 1
DECLARE_LLVM_ATTRIBUTE(NoCapture,1<<21) ///< Function creates no aliases of
pointer
DECLARE_LLVM_ATTRIBUTE(NoRedZone,1<<22) /// disable redzone
DECLARE_LLVM_ATTRIBUTE(NoImplicitFloat,1<<23) /// disable implicit floating
point
/// instructions.
DECLARE_LLVM_ATTRIBUTE(Naked,1<<24) ///< Naked function
DECLARE_LLVM_ATTRIBUTE(InlineHint,1<<25) ///< source said inlining was
///desirable
DECLARE_LLVM_ATTRIBUTE(StackAlignment,7<<26) ///< Alignment of stack for
///function (3 bits) stored as l
og2
///of alignment with +1 bias
///0 means unaligned (different
from
///alignstack= {1))
DECLARE_LLVM_ATTRIBUTE(ReturnsTwice,1<<29) ///< Function can return twice
DECLARE_LLVM_ATTRIBUTE(UWTable,1<<30) ///< Function must be in a unwind
///table
DECLARE_LLVM_ATTRIBUTE(NonLazyBind,1U<<31) ///< Function is called early an
d/or
/// often, so lazy binding isn'
t
/// worthwhile.
DECLARE_LLVM_ATTRIBUTE(AddressSafety,1ULL<<32) ///< Address safety checking
is on.
#undef DECLARE_LLVM_ATTRIBUTE
/// Note that uwtable is about the ABI or the user mandating an entry in th
e
/// unwind table. The nounwind attribute is about an exception passing by t
he
/// function.
/// In a theoretical system that uses tables for profiling and sjlj for
/// exceptions, they would be fully independent. In a normal system that
/// uses tables for both, the semantics are:
/// nil = Needs an entry because an exception might pass by.
/// nounwind = No need for an entry
/// uwtable = Needs an entry because the ABI says so and because
/// an exception might pass by.
/// uwtable + nounwind = Needs an entry because the ABI says so.
/// @brief Attributes that only apply to function parameters.
const AttrConst ParameterOnly = {ByVal_i | Nest_i |
StructRet_i | NoCapture_i};
/// @brief Attributes that may be applied to the function itself. These ca
nnot
/// be used on return values or function parameters.
const AttrConst FunctionOnly = {NoReturn_i | NoUnwind_i | ReadNone_i |
ReadOnly_i | NoInline_i | AlwaysInline_i | OptimizeForSize_i |
StackProtect_i | StackProtectReq_i | NoRedZone_i | NoImplicitFloat_i |
Naked_i | InlineHint_i | StackAlignment_i |
UWTable_i | NonLazyBind_i | ReturnsTwice_i | AddressSafety_i};
/// @brief Parameter attributes that do not apply to vararg call arguments.
const AttrConst VarArgsIncompatible = {StructRet_i};
/// @brief Attributes that are mutually incompatible.
const AttrConst MutuallyIncompatible[4] = {
{ByVal_i | InReg_i | Nest_i | StructRet_i},
{ZExt_i | SExt_i},
{ReadNone_i | ReadOnly_i},
{NoInline_i | AlwaysInline_i}
}; };
/// @brief Which attributes cannot be applied to a type. //===----------------------------------------------------------------------
Attributes typeIncompatible(Type *Ty); ===//
// AttributeWithIndex
/// This turns an int alignment (a power of 2, normally) into the //===----------------------------------------------------------------------
/// form used internally in Attributes. ===//
inline Attributes constructAlignmentFromInt(unsigned i) {
// Default alignment, allow the target to define how to align it.
if (i == 0)
return None;
assert(isPowerOf2_32(i) && "Alignment must be a power of two.");
assert(i <= 0x40000000 && "Alignment too large.");
return Attributes((Log2_32(i)+1) << 16);
}
/// This returns the alignment field of an attribute as a byte alignment va
lue.
inline unsigned getAlignmentFromAttrs(Attributes A) {
Attributes Align = A & Attribute::Alignment;
if (!Align)
return 0;
return 1U << ((Align.Raw() >> 16) - 1);
}
/// This turns an int stack alignment (which must be a power of 2) into
/// the form used internally in Attributes.
inline Attributes constructStackAlignmentFromInt(unsigned i) {
// Default alignment, allow the target to define how to align it.
if (i == 0)
return None;
assert(isPowerOf2_32(i) && "Alignment must be a power of two.");
assert(i <= 0x100 && "Alignment too large.");
return Attributes((Log2_32(i)+1) << 26);
}
/// This returns the stack alignment field of an attribute as a byte alignm
ent
/// value.
inline unsigned getStackAlignmentFromAttrs(Attributes A) {
Attributes StackAlign = A & Attribute::StackAlignment;
if (!StackAlign)
return 0;
return 1U << ((StackAlign.Raw() >> 26) - 1);
}
/// The set of Attributes set in Attributes is converted to a
/// string of equivalent mnemonics. This is, presumably, for writing out
/// the mnemonics for the assembly writer.
/// @brief Convert attribute bits to text
std::string getAsString(Attributes Attrs);
} // end namespace Attribute
/// This is just a pair of values to associate a set of attributes /// AttributeWithIndex - This is just a pair of values to associate a set o
/// with an index. f
/// attributes with an index.
struct AttributeWithIndex { struct AttributeWithIndex {
Attributes Attrs; ///< The attributes that are set, or'd together. Attributes Attrs; ///< The attributes that are set, or'd together.
unsigned Index; ///< Index of the parameter for which the attributes appl unsigned Index; ///< Index of the parameter for which the attributes a
y. pply.
///< Index 0 is used for return value attributes. ///< Index 0 is used for return value attributes.
///< Index ~0U is used for function attributes. ///< Index ~0U is used for function attributes.
static AttributeWithIndex get(LLVMContext &C, unsigned Idx,
ArrayRef<Attributes::AttrVal> Attrs) {
return get(Idx, Attributes::get(C, Attrs));
}
static AttributeWithIndex get(unsigned Idx, Attributes Attrs) { static AttributeWithIndex get(unsigned Idx, Attributes Attrs) {
AttributeWithIndex P; AttributeWithIndex P;
P.Index = Idx; P.Index = Idx;
P.Attrs = Attrs; P.Attrs = Attrs;
return P; return P;
} }
}; };
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// AttrListPtr Smart Pointer // AttrListPtr Smart Pointer
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
class AttributeListImpl; class AttributeListImpl;
/// AttrListPtr - This class manages the ref count for the opaque /// AttrListPtr - This class manages the ref count for the opaque
/// AttributeListImpl object and provides accessors for it. /// AttributeListImpl object and provides accessors for it.
class AttrListPtr { class AttrListPtr {
/// AttrList - The attributes that we are managing. This can be null public:
/// to represent the empty attributes list. enum AttrIndex {
ReturnIndex = 0U,
FunctionIndex = ~0U
};
private:
/// @brief The attributes that we are managing. This can be null to repr
esent
/// the empty attributes list.
AttributeListImpl *AttrList; AttributeListImpl *AttrList;
/// @brief The attributes for the specified index are returned. Attribut
es
/// for the result are denoted with Idx = 0.
Attributes getAttributes(unsigned Idx) const;
explicit AttrListPtr(AttributeListImpl *LI) : AttrList(LI) {}
public: public:
AttrListPtr() : AttrList(0) {} AttrListPtr() : AttrList(0) {}
AttrListPtr(const AttrListPtr &P); AttrListPtr(const AttrListPtr &P) : AttrList(P.AttrList) {}
const AttrListPtr &operator=(const AttrListPtr &RHS); const AttrListPtr &operator=(const AttrListPtr &RHS);
~AttrListPtr();
//===-------------------------------------------------------------------- ===// //===-------------------------------------------------------------------- ===//
// Attribute List Construction and Mutation // Attribute List Construction and Mutation
//===-------------------------------------------------------------------- ===// //===-------------------------------------------------------------------- ===//
/// get - Return a Attributes list with the specified parameter in it. /// get - Return a Attributes list with the specified parameters in it.
static AttrListPtr get(const AttributeWithIndex *Attr, unsigned NumAttrs) static AttrListPtr get(LLVMContext &C, ArrayRef<AttributeWithIndex> Attrs
; );
/// get - Return a Attribute list with the parameters specified by the
/// consecutive random access iterator range.
template <typename Iter>
static AttrListPtr get(const Iter &I, const Iter &E) {
if (I == E) return AttrListPtr(); // Empty list.
return get(&*I, static_cast<unsigned>(E-I));
}
/// addAttr - Add the specified attribute at the specified index to this /// addAttr - Add the specified attribute at the specified index to this
/// attribute list. Since attribute lists are immutable, this /// attribute list. Since attribute lists are immutable, this
/// returns the new list. /// returns the new list.
AttrListPtr addAttr(unsigned Idx, Attributes Attrs) const; AttrListPtr addAttr(LLVMContext &C, unsigned Idx, Attributes Attrs) const ;
/// removeAttr - Remove the specified attribute at the specified index fr om /// removeAttr - Remove the specified attribute at the specified index fr om
/// this attribute list. Since attribute lists are immutable, this /// this attribute list. Since attribute lists are immutable, this
/// returns the new list. /// returns the new list.
AttrListPtr removeAttr(unsigned Idx, Attributes Attrs) const; AttrListPtr removeAttr(LLVMContext &C, unsigned Idx, Attributes Attrs) co nst;
//===-------------------------------------------------------------------- ===// //===-------------------------------------------------------------------- ===//
// Attribute List Accessors // Attribute List Accessors
//===-------------------------------------------------------------------- ===// //===-------------------------------------------------------------------- ===//
/// getParamAttributes - The attributes for the specified index are /// getParamAttributes - The attributes for the specified index are
/// returned. /// returned.
Attributes getParamAttributes(unsigned Idx) const { Attributes getParamAttributes(unsigned Idx) const {
assert (Idx && Idx != ~0U && "Invalid parameter index!");
return getAttributes(Idx); return getAttributes(Idx);
} }
/// getRetAttributes - The attributes for the ret value are /// getRetAttributes - The attributes for the ret value are
/// returned. /// returned.
Attributes getRetAttributes() const { Attributes getRetAttributes() const {
return getAttributes(0); return getAttributes(ReturnIndex);
} }
/// getFnAttributes - The function attributes are returned. /// getFnAttributes - The function attributes are returned.
Attributes getFnAttributes() const { Attributes getFnAttributes() const {
return getAttributes(~0U); return getAttributes(FunctionIndex);
} }
/// paramHasAttr - Return true if the specified parameter index has the /// paramHasAttr - Return true if the specified parameter index has the
/// specified attribute set. /// specified attribute set.
bool paramHasAttr(unsigned Idx, Attributes Attr) const { bool paramHasAttr(unsigned Idx, Attributes Attr) const {
return getAttributes(Idx) & Attr; return getAttributes(Idx).hasAttributes(Attr);
} }
/// getParamAlignment - Return the alignment for the specified function /// getParamAlignment - Return the alignment for the specified function
/// parameter. /// parameter.
unsigned getParamAlignment(unsigned Idx) const { unsigned getParamAlignment(unsigned Idx) const {
return Attribute::getAlignmentFromAttrs(getAttributes(Idx)); return getAttributes(Idx).getAlignment();
} }
/// hasAttrSomewhere - Return true if the specified attribute is set for at /// hasAttrSomewhere - Return true if the specified attribute is set for at
/// least one parameter or for the return value. /// least one parameter or for the return value.
bool hasAttrSomewhere(Attributes Attr) const; bool hasAttrSomewhere(Attributes::AttrVal Attr) const;
unsigned getNumAttrs() const;
Attributes &getAttributesAtIndex(unsigned i) const;
/// operator==/!= - Provide equality predicates. /// operator==/!= - Provide equality predicates.
bool operator==(const AttrListPtr &RHS) const bool operator==(const AttrListPtr &RHS) const
{ return AttrList == RHS.AttrList; } { return AttrList == RHS.AttrList; }
bool operator!=(const AttrListPtr &RHS) const bool operator!=(const AttrListPtr &RHS) const
{ return AttrList != RHS.AttrList; } { return AttrList != RHS.AttrList; }
void dump() const;
//===-------------------------------------------------------------------- ===// //===-------------------------------------------------------------------- ===//
// Attribute List Introspection // Attribute List Introspection
//===-------------------------------------------------------------------- ===// //===-------------------------------------------------------------------- ===//
/// getRawPointer - Return a raw pointer that uniquely identifies this /// getRawPointer - Return a raw pointer that uniquely identifies this
/// attribute list. /// attribute list.
void *getRawPointer() const { void *getRawPointer() const {
return AttrList; return AttrList;
} }
skipping to change at line 364 skipping to change at line 426
/// getNumSlots - Return the number of slots used in this attribute list. /// getNumSlots - Return the number of slots used in this attribute list.
/// This is the number of arguments that have an attribute set on them /// This is the number of arguments that have an attribute set on them
/// (including the function itself). /// (including the function itself).
unsigned getNumSlots() const; unsigned getNumSlots() const;
/// getSlot - Return the AttributeWithIndex at the specified slot. This /// getSlot - Return the AttributeWithIndex at the specified slot. This
/// holds a index number plus a set of attributes. /// holds a index number plus a set of attributes.
const AttributeWithIndex &getSlot(unsigned Slot) const; const AttributeWithIndex &getSlot(unsigned Slot) const;
private: void dump() const;
explicit AttrListPtr(AttributeListImpl *L);
/// getAttributes - The attributes for the specified index are
/// returned. Attributes for the result are denoted with Idx = 0.
Attributes getAttributes(unsigned Idx) const;
}; };
} // End llvm namespace } // End llvm namespace
#endif #endif
 End of changes. 25 change blocks. 
259 lines changed or deleted 323 lines changed or added


 BasicBlock.h   BasicBlock.h 
skipping to change at line 82 skipping to change at line 82
friend class BlockAddress; friend class BlockAddress;
public: public:
typedef iplist<Instruction> InstListType; typedef iplist<Instruction> InstListType;
private: private:
InstListType InstList; InstListType InstList;
Function *Parent; Function *Parent;
void setParent(Function *parent); void setParent(Function *parent);
friend class SymbolTableListTraits<BasicBlock, Function>; friend class SymbolTableListTraits<BasicBlock, Function>;
BasicBlock(const BasicBlock &); // Do not implement BasicBlock(const BasicBlock &) LLVM_DELETED_FUNCTION;
void operator=(const BasicBlock &); // Do not implement void operator=(const BasicBlock &) LLVM_DELETED_FUNCTION;
/// BasicBlock ctor - If the function parameter is specified, the basic b lock /// BasicBlock ctor - If the function parameter is specified, the basic b lock
/// is automatically inserted at either the end of the function (if /// is automatically inserted at either the end of the function (if
/// InsertBefore is null), or before the specified basic block. /// InsertBefore is null), or before the specified basic block.
/// ///
explicit BasicBlock(LLVMContext &C, const Twine &Name = "", explicit BasicBlock(LLVMContext &C, const Twine &Name = "",
Function *Parent = 0, BasicBlock *InsertBefore = 0); Function *Parent = 0, BasicBlock *InsertBefore = 0);
public: public:
/// getContext - Get the context in which this basic block lives. /// getContext - Get the context in which this basic block lives.
LLVMContext &getContext() const; LLVMContext &getContext() const;
skipping to change at line 215 skipping to change at line 215
/// getSublistAccess() - returns pointer to member of instruction list /// getSublistAccess() - returns pointer to member of instruction list
static iplist<Instruction> BasicBlock::*getSublistAccess(Instruction*) { static iplist<Instruction> BasicBlock::*getSublistAccess(Instruction*) {
return &BasicBlock::InstList; return &BasicBlock::InstList;
} }
/// getValueSymbolTable() - returns pointer to symbol table (if any) /// getValueSymbolTable() - returns pointer to symbol table (if any)
ValueSymbolTable *getValueSymbolTable(); ValueSymbolTable *getValueSymbolTable();
/// Methods for support type inquiry through isa, cast, and dyn_cast: /// Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const BasicBlock *) { return true; }
static inline bool classof(const Value *V) { static inline bool classof(const Value *V) {
return V->getValueID() == Value::BasicBlockVal; return V->getValueID() == Value::BasicBlockVal;
} }
/// dropAllReferences() - This function causes all the subinstructions to "let /// dropAllReferences() - This function causes all the subinstructions to "let
/// go" of all references that they are maintaining. This allows one to /// go" of all references that they are maintaining. This allows one to
/// 'delete' a whole class at a time, even though there may be circular /// 'delete' a whole class at a time, even though there may be circular
/// references... first all references are dropped, and all use counts go to /// references... first all references are dropped, and all use counts go to
/// zero. Then everything is delete'd for real. Note that no operations are /// zero. Then everything is delete'd for real. Note that no operations are
/// valid on an object that has "dropped all references", except operator /// valid on an object that has "dropped all references", except operator
 End of changes. 2 change blocks. 
3 lines changed or deleted 2 lines changed or added


 BasicBlockUtils.h   BasicBlockUtils.h 
skipping to change at line 28 skipping to change at line 28
// FIXME: Move to this file: BasicBlock::removePredecessor, BB::splitBasicB lock // FIXME: Move to this file: BasicBlock::removePredecessor, BB::splitBasicB lock
#include "llvm/BasicBlock.h" #include "llvm/BasicBlock.h"
#include "llvm/Support/CFG.h" #include "llvm/Support/CFG.h"
#include "llvm/Support/DebugLoc.h" #include "llvm/Support/DebugLoc.h"
namespace llvm { namespace llvm {
class AliasAnalysis; class AliasAnalysis;
class Instruction; class Instruction;
class MDNode;
class Pass; class Pass;
class ReturnInst; class ReturnInst;
class TargetLibraryInfo;
class TerminatorInst;
/// DeleteDeadBlock - Delete the specified block, which must have no /// DeleteDeadBlock - Delete the specified block, which must have no
/// predecessors. /// predecessors.
void DeleteDeadBlock(BasicBlock *BB); void DeleteDeadBlock(BasicBlock *BB);
/// FoldSingleEntryPHINodes - We know that BB has one predecessor. If ther e are /// FoldSingleEntryPHINodes - We know that BB has one predecessor. If ther e are
/// any single-entry PHI nodes in it, fold them away. This handles the cas e /// any single-entry PHI nodes in it, fold them away. This handles the cas e
/// when all entries to the PHI nodes in a block are guaranteed equal, such as /// when all entries to the PHI nodes in a block are guaranteed equal, such as
/// when the block has exactly one predecessor. /// when the block has exactly one predecessor.
void FoldSingleEntryPHINodes(BasicBlock *BB, Pass *P = 0); void FoldSingleEntryPHINodes(BasicBlock *BB, Pass *P = 0);
/// DeleteDeadPHIs - Examine each PHI in the given block and delete it if i t /// DeleteDeadPHIs - Examine each PHI in the given block and delete it if i t
/// is dead. Also recursively delete any operands that become dead as /// is dead. Also recursively delete any operands that become dead as
/// a result. This includes tracing the def-use list from the PHI to see if /// a result. This includes tracing the def-use list from the PHI to see if
/// it is ultimately unused or if it reaches an unused cycle. Return true /// it is ultimately unused or if it reaches an unused cycle. Return true
/// if any PHIs were deleted. /// if any PHIs were deleted.
bool DeleteDeadPHIs(BasicBlock *BB); bool DeleteDeadPHIs(BasicBlock *BB, const TargetLibraryInfo *TLI = 0);
/// MergeBlockIntoPredecessor - Attempts to merge a block into its predeces sor, /// MergeBlockIntoPredecessor - Attempts to merge a block into its predeces sor,
/// if possible. The return value indicates success or failure. /// if possible. The return value indicates success or failure.
bool MergeBlockIntoPredecessor(BasicBlock *BB, Pass *P = 0); bool MergeBlockIntoPredecessor(BasicBlock *BB, Pass *P = 0);
// ReplaceInstWithValue - Replace all uses of an instruction (specified by BI) // ReplaceInstWithValue - Replace all uses of an instruction (specified by BI)
// with a value, then remove and delete the original instruction. // with a value, then remove and delete the original instruction.
// //
void ReplaceInstWithValue(BasicBlock::InstListType &BIL, void ReplaceInstWithValue(BasicBlock::InstListType &BIL,
BasicBlock::iterator &BI, Value *V); BasicBlock::iterator &BI, Value *V);
skipping to change at line 203 skipping to change at line 206
Pass *P, SmallVectorImpl<BasicBlock*> &New BBs); Pass *P, SmallVectorImpl<BasicBlock*> &New BBs);
/// FoldReturnIntoUncondBranch - This method duplicates the specified retur n /// FoldReturnIntoUncondBranch - This method duplicates the specified retur n
/// instruction into a predecessor which ends in an unconditional branch. I f /// instruction into a predecessor which ends in an unconditional branch. I f
/// the return instruction returns a value defined by a PHI, propagate the /// the return instruction returns a value defined by a PHI, propagate the
/// right value into the return. It returns the new return instruction in t he /// right value into the return. It returns the new return instruction in t he
/// predecessor. /// predecessor.
ReturnInst *FoldReturnIntoUncondBranch(ReturnInst *RI, BasicBlock *BB, ReturnInst *FoldReturnIntoUncondBranch(ReturnInst *RI, BasicBlock *BB,
BasicBlock *Pred); BasicBlock *Pred);
/// GetFirstDebugLocInBasicBlock - Return first valid DebugLoc entry in a /// SplitBlockAndInsertIfThen - Split the containing block at the
/// given basic block. /// specified instruction - everything before and including Cmp stays
DebugLoc GetFirstDebugLocInBasicBlock(const BasicBlock *BB); /// in the old basic block, and everything after Cmp is moved to a
/// new block. The two blocks are connected by a conditional branch
/// (with value of Cmp being the condition).
/// Before:
/// Head
/// Cmp
/// Tail
/// After:
/// Head
/// Cmp
/// if (Cmp)
/// ThenBlock
/// Tail
///
/// If Unreachable is true, then ThenBlock ends with
/// UnreachableInst, otherwise it branches to Tail.
/// Returns the NewBasicBlock's terminator.
TerminatorInst *SplitBlockAndInsertIfThen(Instruction *Cmp,
bool Unreachable, MDNode *BranchWeights = 0);
} // End llvm namespace } // End llvm namespace
#endif #endif
 End of changes. 4 change blocks. 
4 lines changed or deleted 26 lines changed or added


 Binary.h   Binary.h 
skipping to change at line 29 skipping to change at line 29
namespace llvm { namespace llvm {
class MemoryBuffer; class MemoryBuffer;
class StringRef; class StringRef;
namespace object { namespace object {
class Binary { class Binary {
private: private:
Binary(); // = delete Binary() LLVM_DELETED_FUNCTION;
Binary(const Binary &other); // = delete Binary(const Binary &other) LLVM_DELETED_FUNCTION;
unsigned int TypeID; unsigned int TypeID;
protected: protected:
MemoryBuffer *Data; MemoryBuffer *Data;
Binary(unsigned int Type, MemoryBuffer *Source); Binary(unsigned int Type, MemoryBuffer *Source);
enum { enum {
ID_Archive, ID_Archive,
skipping to change at line 67 skipping to change at line 67
} }
public: public:
virtual ~Binary(); virtual ~Binary();
StringRef getData() const; StringRef getData() const;
StringRef getFileName() const; StringRef getFileName() const;
// Cast methods. // Cast methods.
unsigned int getType() const { return TypeID; } unsigned int getType() const { return TypeID; }
static inline bool classof(const Binary *v) { return true; }
// Convenience methods // Convenience methods
bool isObject() const { bool isObject() const {
return TypeID > ID_StartObjects && TypeID < ID_EndObjects; return TypeID > ID_StartObjects && TypeID < ID_EndObjects;
} }
bool isArchive() const { bool isArchive() const {
return TypeID == ID_Archive; return TypeID == ID_Archive;
} }
skipping to change at line 93 skipping to change at line 92
return TypeID == ID_MachO; return TypeID == ID_MachO;
} }
bool isCOFF() const { bool isCOFF() const {
return TypeID == ID_COFF; return TypeID == ID_COFF;
} }
}; };
/// @brief Create a Binary from Source, autodetecting the file type. /// @brief Create a Binary from Source, autodetecting the file type.
/// ///
/// @param Source The data to create the Binary from. Ownership is transfer ed /// @param Source The data to create the Binary from. Ownership is transfer red
/// to Result if successful. If an error is returned, Source is dest royed /// to Result if successful. If an error is returned, Source is dest royed
/// by createBinary before returning. /// by createBinary before returning.
/// @param Result A pointer to the resulting Binary if no error occured. /// @param Result A pointer to the resulting Binary if no error occured.
error_code createBinary(MemoryBuffer *Source, OwningPtr<Binary> &Result); error_code createBinary(MemoryBuffer *Source, OwningPtr<Binary> &Result);
error_code createBinary(StringRef Path, OwningPtr<Binary> &Result); error_code createBinary(StringRef Path, OwningPtr<Binary> &Result);
} }
} }
 End of changes. 3 change blocks. 
4 lines changed or deleted 3 lines changed or added


 BitVector.h   BitVector.h 
skipping to change at line 17 skipping to change at line 17
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// //
// This file implements the BitVector class. // This file implements the BitVector class.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_ADT_BITVECTOR_H #ifndef LLVM_ADT_BITVECTOR_H
#define LLVM_ADT_BITVECTOR_H #define LLVM_ADT_BITVECTOR_H
#include "llvm/Support/Compiler.h"
#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h" #include "llvm/Support/MathExtras.h"
#include <algorithm> #include <algorithm>
#include <cassert> #include <cassert>
#include <climits> #include <climits>
#include <cstdlib> #include <cstdlib>
namespace llvm { namespace llvm {
class BitVector { class BitVector {
skipping to change at line 99 skipping to change at line 100
Bits = 0; Bits = 0;
Capacity = 0; Capacity = 0;
return; return;
} }
Capacity = NumBitWords(RHS.size()); Capacity = NumBitWords(RHS.size());
Bits = (BitWord *)std::malloc(Capacity * sizeof(BitWord)); Bits = (BitWord *)std::malloc(Capacity * sizeof(BitWord));
std::memcpy(Bits, RHS.Bits, Capacity * sizeof(BitWord)); std::memcpy(Bits, RHS.Bits, Capacity * sizeof(BitWord));
} }
#if LLVM_USE_RVALUE_REFERENCES
BitVector(BitVector &&RHS)
: Bits(RHS.Bits), Size(RHS.Size), Capacity(RHS.Capacity) {
RHS.Bits = 0;
}
#endif
~BitVector() { ~BitVector() {
std::free(Bits); std::free(Bits);
} }
/// empty - Tests whether there are no bits in this bitvector. /// empty - Tests whether there are no bits in this bitvector.
bool empty() const { return Size == 0; } bool empty() const { return Size == 0; }
/// size - Returns the number of bits in this bitvector. /// size - Returns the number of bits in this bitvector.
unsigned size() const { return Size; } unsigned size() const { return Size; }
skipping to change at line 166 skipping to change at line 174
/// "Prev" bit. Returns -1 if the next set bit is not found. /// "Prev" bit. Returns -1 if the next set bit is not found.
int find_next(unsigned Prev) const { int find_next(unsigned Prev) const {
++Prev; ++Prev;
if (Prev >= Size) if (Prev >= Size)
return -1; return -1;
unsigned WordPos = Prev / BITWORD_SIZE; unsigned WordPos = Prev / BITWORD_SIZE;
unsigned BitPos = Prev % BITWORD_SIZE; unsigned BitPos = Prev % BITWORD_SIZE;
BitWord Copy = Bits[WordPos]; BitWord Copy = Bits[WordPos];
// Mask off previous bits. // Mask off previous bits.
Copy &= ~0L << BitPos; Copy &= ~0UL << BitPos;
if (Copy != 0) { if (Copy != 0) {
if (sizeof(BitWord) == 4) if (sizeof(BitWord) == 4)
return WordPos * BITWORD_SIZE + CountTrailingZeros_32((uint32_t)Cop y); return WordPos * BITWORD_SIZE + CountTrailingZeros_32((uint32_t)Cop y);
if (sizeof(BitWord) == 8) if (sizeof(BitWord) == 8)
return WordPos * BITWORD_SIZE + CountTrailingZeros_64(Copy); return WordPos * BITWORD_SIZE + CountTrailingZeros_64(Copy);
llvm_unreachable("Unsupported!"); llvm_unreachable("Unsupported!");
} }
// Check subsequent words. // Check subsequent words.
skipping to change at line 231 skipping to change at line 239
init_words(Bits, Capacity, true); init_words(Bits, Capacity, true);
clear_unused_bits(); clear_unused_bits();
return *this; return *this;
} }
BitVector &set(unsigned Idx) { BitVector &set(unsigned Idx) {
Bits[Idx / BITWORD_SIZE] |= 1L << (Idx % BITWORD_SIZE); Bits[Idx / BITWORD_SIZE] |= 1L << (Idx % BITWORD_SIZE);
return *this; return *this;
} }
/// set - Efficiently set a range of bits in [I, E)
BitVector &set(unsigned I, unsigned E) {
assert(I <= E && "Attempted to set backwards range!");
assert(E <= size() && "Attempted to set out-of-bounds range!");
if (I == E) return *this;
if (I / BITWORD_SIZE == E / BITWORD_SIZE) {
BitWord EMask = 1UL << (E % BITWORD_SIZE);
BitWord IMask = 1UL << (I % BITWORD_SIZE);
BitWord Mask = EMask - IMask;
Bits[I / BITWORD_SIZE] |= Mask;
return *this;
}
BitWord PrefixMask = ~0UL << (I % BITWORD_SIZE);
Bits[I / BITWORD_SIZE] |= PrefixMask;
I = RoundUpToAlignment(I, BITWORD_SIZE);
for (; I + BITWORD_SIZE <= E; I += BITWORD_SIZE)
Bits[I / BITWORD_SIZE] = ~0UL;
BitWord PostfixMask = (1UL << (E % BITWORD_SIZE)) - 1;
Bits[I / BITWORD_SIZE] |= PostfixMask;
return *this;
}
BitVector &reset() { BitVector &reset() {
init_words(Bits, Capacity, false); init_words(Bits, Capacity, false);
return *this; return *this;
} }
BitVector &reset(unsigned Idx) { BitVector &reset(unsigned Idx) {
Bits[Idx / BITWORD_SIZE] &= ~(1L << (Idx % BITWORD_SIZE)); Bits[Idx / BITWORD_SIZE] &= ~(1L << (Idx % BITWORD_SIZE));
return *this; return *this;
} }
/// reset - Efficiently reset a range of bits in [I, E)
BitVector &reset(unsigned I, unsigned E) {
assert(I <= E && "Attempted to reset backwards range!");
assert(E <= size() && "Attempted to reset out-of-bounds range!");
if (I == E) return *this;
if (I / BITWORD_SIZE == E / BITWORD_SIZE) {
BitWord EMask = 1UL << (E % BITWORD_SIZE);
BitWord IMask = 1UL << (I % BITWORD_SIZE);
BitWord Mask = EMask - IMask;
Bits[I / BITWORD_SIZE] &= ~Mask;
return *this;
}
BitWord PrefixMask = ~0UL << (I % BITWORD_SIZE);
Bits[I / BITWORD_SIZE] &= ~PrefixMask;
I = RoundUpToAlignment(I, BITWORD_SIZE);
for (; I + BITWORD_SIZE <= E; I += BITWORD_SIZE)
Bits[I / BITWORD_SIZE] = 0UL;
BitWord PostfixMask = (1UL << (E % BITWORD_SIZE)) - 1;
Bits[I / BITWORD_SIZE] &= ~PostfixMask;
return *this;
}
BitVector &flip() { BitVector &flip() {
for (unsigned i = 0; i < NumBitWords(size()); ++i) for (unsigned i = 0; i < NumBitWords(size()); ++i)
Bits[i] = ~Bits[i]; Bits[i] = ~Bits[i];
clear_unused_bits(); clear_unused_bits();
return *this; return *this;
} }
BitVector &flip(unsigned Idx) { BitVector &flip(unsigned Idx) {
Bits[Idx / BITWORD_SIZE] ^= 1L << (Idx % BITWORD_SIZE); Bits[Idx / BITWORD_SIZE] ^= 1L << (Idx % BITWORD_SIZE);
return *this; return *this;
} }
// No argument flip.
BitVector operator~() const {
return BitVector(*this).flip();
}
// Indexing. // Indexing.
reference operator[](unsigned Idx) { reference operator[](unsigned Idx) {
assert (Idx < Size && "Out-of-bounds Bit access."); assert (Idx < Size && "Out-of-bounds Bit access.");
return reference(*this, Idx); return reference(*this, Idx);
} }
bool operator[](unsigned Idx) const { bool operator[](unsigned Idx) const {
assert (Idx < Size && "Out-of-bounds Bit access."); assert (Idx < Size && "Out-of-bounds Bit access.");
BitWord Mask = 1L << (Idx % BITWORD_SIZE); BitWord Mask = 1L << (Idx % BITWORD_SIZE);
return (Bits[Idx / BITWORD_SIZE] & Mask) != 0; return (Bits[Idx / BITWORD_SIZE] & Mask) != 0;
} }
bool test(unsigned Idx) const { bool test(unsigned Idx) const {
return (*this)[Idx]; return (*this)[Idx];
} }
/// Test if any common bits are set.
bool anyCommon(const BitVector &RHS) const {
unsigned ThisWords = NumBitWords(size());
unsigned RHSWords = NumBitWords(RHS.size());
for (unsigned i = 0, e = std::min(ThisWords, RHSWords); i != e; ++i)
if (Bits[i] & RHS.Bits[i])
return true;
return false;
}
// Comparison operators. // Comparison operators.
bool operator==(const BitVector &RHS) const { bool operator==(const BitVector &RHS) const {
unsigned ThisWords = NumBitWords(size()); unsigned ThisWords = NumBitWords(size());
unsigned RHSWords = NumBitWords(RHS.size()); unsigned RHSWords = NumBitWords(RHS.size());
unsigned i; unsigned i;
for (i = 0; i != std::min(ThisWords, RHSWords); ++i) for (i = 0; i != std::min(ThisWords, RHSWords); ++i)
if (Bits[i] != RHS.Bits[i]) if (Bits[i] != RHS.Bits[i])
return false; return false;
// Verify that any extra words are all zeros. // Verify that any extra words are all zeros.
skipping to change at line 300 skipping to change at line 369
if (RHS.Bits[i]) if (RHS.Bits[i])
return false; return false;
} }
return true; return true;
} }
bool operator!=(const BitVector &RHS) const { bool operator!=(const BitVector &RHS) const {
return !(*this == RHS); return !(*this == RHS);
} }
// Intersection, union, disjoint union. /// Intersection, union, disjoint union.
BitVector &operator&=(const BitVector &RHS) { BitVector &operator&=(const BitVector &RHS) {
unsigned ThisWords = NumBitWords(size()); unsigned ThisWords = NumBitWords(size());
unsigned RHSWords = NumBitWords(RHS.size()); unsigned RHSWords = NumBitWords(RHS.size());
unsigned i; unsigned i;
for (i = 0; i != std::min(ThisWords, RHSWords); ++i) for (i = 0; i != std::min(ThisWords, RHSWords); ++i)
Bits[i] &= RHS.Bits[i]; Bits[i] &= RHS.Bits[i];
// Any bits that are just in this bitvector become zero, because they a ren't // Any bits that are just in this bitvector become zero, because they a ren't
// in the RHS bit vector. Any words only in RHS are ignored because th ey // in the RHS bit vector. Any words only in RHS are ignored because th ey
// are already zero in the LHS. // are already zero in the LHS.
for (; i != ThisWords; ++i) for (; i != ThisWords; ++i)
Bits[i] = 0; Bits[i] = 0;
return *this; return *this;
} }
// reset - Reset bits that are set in RHS. Same as *this &= ~RHS. /// reset - Reset bits that are set in RHS. Same as *this &= ~RHS.
BitVector &reset(const BitVector &RHS) { BitVector &reset(const BitVector &RHS) {
unsigned ThisWords = NumBitWords(size()); unsigned ThisWords = NumBitWords(size());
unsigned RHSWords = NumBitWords(RHS.size()); unsigned RHSWords = NumBitWords(RHS.size());
unsigned i; unsigned i;
for (i = 0; i != std::min(ThisWords, RHSWords); ++i) for (i = 0; i != std::min(ThisWords, RHSWords); ++i)
Bits[i] &= ~RHS.Bits[i]; Bits[i] &= ~RHS.Bits[i];
return *this; return *this;
} }
/// test - Check if (This - RHS) is zero.
/// This is the same as reset(RHS) and any().
bool test(const BitVector &RHS) const {
unsigned ThisWords = NumBitWords(size());
unsigned RHSWords = NumBitWords(RHS.size());
unsigned i;
for (i = 0; i != std::min(ThisWords, RHSWords); ++i)
if ((Bits[i] & ~RHS.Bits[i]) != 0)
return true;
for (; i != ThisWords ; ++i)
if (Bits[i] != 0)
return true;
return false;
}
BitVector &operator|=(const BitVector &RHS) { BitVector &operator|=(const BitVector &RHS) {
if (size() < RHS.size()) if (size() < RHS.size())
resize(RHS.size()); resize(RHS.size());
for (size_t i = 0, e = NumBitWords(RHS.size()); i != e; ++i) for (size_t i = 0, e = NumBitWords(RHS.size()); i != e; ++i)
Bits[i] |= RHS.Bits[i]; Bits[i] |= RHS.Bits[i];
return *this; return *this;
} }
BitVector &operator^=(const BitVector &RHS) { BitVector &operator^=(const BitVector &RHS) {
if (size() < RHS.size()) if (size() < RHS.size())
skipping to change at line 368 skipping to change at line 454
BitWord *NewBits = (BitWord *)std::malloc(Capacity * sizeof(BitWord)); BitWord *NewBits = (BitWord *)std::malloc(Capacity * sizeof(BitWord));
std::memcpy(NewBits, RHS.Bits, Capacity * sizeof(BitWord)); std::memcpy(NewBits, RHS.Bits, Capacity * sizeof(BitWord));
// Destroy the old bits. // Destroy the old bits.
std::free(Bits); std::free(Bits);
Bits = NewBits; Bits = NewBits;
return *this; return *this;
} }
#if LLVM_USE_RVALUE_REFERENCES
const BitVector &operator=(BitVector &&RHS) {
if (this == &RHS) return *this;
std::free(Bits);
Bits = RHS.Bits;
Size = RHS.Size;
Capacity = RHS.Capacity;
RHS.Bits = 0;
return *this;
}
#endif
void swap(BitVector &RHS) { void swap(BitVector &RHS) {
std::swap(Bits, RHS.Bits); std::swap(Bits, RHS.Bits);
std::swap(Size, RHS.Size); std::swap(Size, RHS.Size);
std::swap(Capacity, RHS.Capacity); std::swap(Capacity, RHS.Capacity);
} }
//===-------------------------------------------------------------------- ===// //===-------------------------------------------------------------------- ===//
// Portable bit mask operations. // Portable bit mask operations.
//===-------------------------------------------------------------------- ===// //===-------------------------------------------------------------------- ===//
// //
skipping to change at line 425 skipping to change at line 526
// Set the unused bits in the high words. // Set the unused bits in the high words.
void set_unused_bits(bool t = true) { void set_unused_bits(bool t = true) {
// Set high words first. // Set high words first.
unsigned UsedWords = NumBitWords(Size); unsigned UsedWords = NumBitWords(Size);
if (Capacity > UsedWords) if (Capacity > UsedWords)
init_words(&Bits[UsedWords], (Capacity-UsedWords), t); init_words(&Bits[UsedWords], (Capacity-UsedWords), t);
// Then set any stray high bits of the last used word. // Then set any stray high bits of the last used word.
unsigned ExtraBits = Size % BITWORD_SIZE; unsigned ExtraBits = Size % BITWORD_SIZE;
if (ExtraBits) { if (ExtraBits) {
Bits[UsedWords-1] &= ~(~0L << ExtraBits); BitWord ExtraBitMask = ~0UL << ExtraBits;
Bits[UsedWords-1] |= (0 - (BitWord)t) << ExtraBits; if (t)
Bits[UsedWords-1] |= ExtraBitMask;
else
Bits[UsedWords-1] &= ~ExtraBitMask;
} }
} }
// Clear the unused bits in the high words. // Clear the unused bits in the high words.
void clear_unused_bits() { void clear_unused_bits() {
set_unused_bits(false); set_unused_bits(false);
} }
void grow(unsigned NewSize) { void grow(unsigned NewSize) {
Capacity = std::max(NumBitWords(NewSize), Capacity * 2); Capacity = std::max(NumBitWords(NewSize), Capacity * 2);
skipping to change at line 474 skipping to change at line 578
uint32_t M = *Mask++; uint32_t M = *Mask++;
if (InvertMask) M = ~M; if (InvertMask) M = ~M;
if (AddBits) Bits[i] |= BitWord(M) << b; if (AddBits) Bits[i] |= BitWord(M) << b;
else Bits[i] &= ~(BitWord(M) << b); else Bits[i] &= ~(BitWord(M) << b);
} }
if (AddBits) if (AddBits)
clear_unused_bits(); clear_unused_bits();
} }
}; };
inline BitVector operator&(const BitVector &LHS, const BitVector &RHS) {
BitVector Result(LHS);
Result &= RHS;
return Result;
}
inline BitVector operator|(const BitVector &LHS, const BitVector &RHS) {
BitVector Result(LHS);
Result |= RHS;
return Result;
}
inline BitVector operator^(const BitVector &LHS, const BitVector &RHS) {
BitVector Result(LHS);
Result ^= RHS;
return Result;
}
} // End llvm namespace } // End llvm namespace
namespace std { namespace std {
/// Implement std::swap in terms of BitVector swap. /// Implement std::swap in terms of BitVector swap.
inline void inline void
swap(llvm::BitVector &LHS, llvm::BitVector &RHS) { swap(llvm::BitVector &LHS, llvm::BitVector &RHS) {
LHS.swap(RHS); LHS.swap(RHS);
} }
} }
 End of changes. 13 change blocks. 
28 lines changed or deleted 114 lines changed or added


 BitstreamReader.h   BitstreamReader.h 
skipping to change at line 51 skipping to change at line 51
private: private:
OwningPtr<StreamableMemoryObject> BitcodeBytes; OwningPtr<StreamableMemoryObject> BitcodeBytes;
std::vector<BlockInfo> BlockInfoRecords; std::vector<BlockInfo> BlockInfoRecords;
/// IgnoreBlockInfoNames - This is set to true if we don't care about the /// IgnoreBlockInfoNames - This is set to true if we don't care about the
/// block/record name information in the BlockInfo block. Only llvm-bcana lyzer /// block/record name information in the BlockInfo block. Only llvm-bcana lyzer
/// uses this. /// uses this.
bool IgnoreBlockInfoNames; bool IgnoreBlockInfoNames;
BitstreamReader(const BitstreamReader&); // DO NOT IMPLEMENT BitstreamReader(const BitstreamReader&) LLVM_DELETED_FUNCTION;
void operator=(const BitstreamReader&); // DO NOT IMPLEMENT void operator=(const BitstreamReader&) LLVM_DELETED_FUNCTION;
public: public:
BitstreamReader() : IgnoreBlockInfoNames(true) { BitstreamReader() : IgnoreBlockInfoNames(true) {
} }
BitstreamReader(const unsigned char *Start, const unsigned char *End) { BitstreamReader(const unsigned char *Start, const unsigned char *End) {
IgnoreBlockInfoNames = true; IgnoreBlockInfoNames = true;
init(Start, End); init(Start, End);
} }
BitstreamReader(StreamableMemoryObject *bytes) { BitstreamReader(StreamableMemoryObject *bytes) {
skipping to change at line 409 skipping to change at line 409
// bogus. // bogus.
size_t SkipTo = NextChar + NumWords*4; size_t SkipTo = NextChar + NumWords*4;
if (AtEndOfStream() || !canSkipToPos(SkipTo)) if (AtEndOfStream() || !canSkipToPos(SkipTo))
return true; return true;
NextChar = SkipTo; NextChar = SkipTo;
return false; return false;
} }
/// EnterSubBlock - Having read the ENTER_SUBBLOCK abbrevid, enter /// EnterSubBlock - Having read the ENTER_SUBBLOCK abbrevid, enter
/// the block, and return true if the block is valid. /// the block, and return true if the block has an error.
bool EnterSubBlock(unsigned BlockID, unsigned *NumWordsP = 0) { bool EnterSubBlock(unsigned BlockID, unsigned *NumWordsP = 0) {
// Save the current block's state on BlockScope. // Save the current block's state on BlockScope.
BlockScope.push_back(Block(CurCodeSize)); BlockScope.push_back(Block(CurCodeSize));
BlockScope.back().PrevAbbrevs.swap(CurAbbrevs); BlockScope.back().PrevAbbrevs.swap(CurAbbrevs);
// Add the abbrevs specific to this block to the CurAbbrevs list. // Add the abbrevs specific to this block to the CurAbbrevs list.
if (const BitstreamReader::BlockInfo *Info = if (const BitstreamReader::BlockInfo *Info =
BitStream->getBlockInfo(BlockID)) { BitStream->getBlockInfo(BlockID)) {
for (unsigned i = 0, e = static_cast<unsigned>(Info->Abbrevs.size()); for (unsigned i = 0, e = static_cast<unsigned>(Info->Abbrevs.size());
i != e; ++i) { i != e; ++i) {
 End of changes. 2 change blocks. 
3 lines changed or deleted 3 lines changed or added


 BitstreamWriter.h   BitstreamWriter.h 
skipping to change at line 158 skipping to change at line 158
void FlushToWord() { void FlushToWord() {
if (CurBit) { if (CurBit) {
WriteWord(CurValue); WriteWord(CurValue);
CurBit = 0; CurBit = 0;
CurValue = 0; CurValue = 0;
} }
} }
void EmitVBR(uint32_t Val, unsigned NumBits) { void EmitVBR(uint32_t Val, unsigned NumBits) {
assert(NumBits <= 32 && "Too many bits to emit!");
uint32_t Threshold = 1U << (NumBits-1); uint32_t Threshold = 1U << (NumBits-1);
// Emit the bits with VBR encoding, NumBits-1 bits at a time. // Emit the bits with VBR encoding, NumBits-1 bits at a time.
while (Val >= Threshold) { while (Val >= Threshold) {
Emit((Val & ((1 << (NumBits-1))-1)) | (1 << (NumBits-1)), NumBits); Emit((Val & ((1 << (NumBits-1))-1)) | (1 << (NumBits-1)), NumBits);
Val >>= NumBits-1; Val >>= NumBits-1;
} }
Emit(Val, NumBits); Emit(Val, NumBits);
} }
void EmitVBR64(uint64_t Val, unsigned NumBits) { void EmitVBR64(uint64_t Val, unsigned NumBits) {
assert(NumBits <= 32 && "Too many bits to emit!");
if ((uint32_t)Val == Val) if ((uint32_t)Val == Val)
return EmitVBR((uint32_t)Val, NumBits); return EmitVBR((uint32_t)Val, NumBits);
uint64_t Threshold = 1U << (NumBits-1); uint32_t Threshold = 1U << (NumBits-1);
// Emit the bits with VBR encoding, NumBits-1 bits at a time. // Emit the bits with VBR encoding, NumBits-1 bits at a time.
while (Val >= Threshold) { while (Val >= Threshold) {
Emit(((uint32_t)Val & ((1 << (NumBits-1))-1)) | Emit(((uint32_t)Val & ((1 << (NumBits-1))-1)) |
(1 << (NumBits-1)), NumBits); (1 << (NumBits-1)), NumBits);
Val >>= NumBits-1; Val >>= NumBits-1;
} }
Emit((uint32_t)Val, NumBits); Emit((uint32_t)Val, NumBits);
} }
 End of changes. 3 change blocks. 
1 lines changed or deleted 3 lines changed or added


 BlockFrequencyImpl.h   BlockFrequencyImpl.h 
skipping to change at line 218 skipping to change at line 218
if (!isLoopHead) if (!isLoopHead)
return; return;
assert(EntryFreq >= CycleProb[BB]); assert(EntryFreq >= CycleProb[BB]);
uint32_t CProb = CycleProb[BB]; uint32_t CProb = CycleProb[BB];
uint32_t Numerator = EntryFreq - CProb ? EntryFreq - CProb : 1; uint32_t Numerator = EntryFreq - CProb ? EntryFreq - CProb : 1;
divBlockFreq(BB, BranchProbability(Numerator, EntryFreq)); divBlockFreq(BB, BranchProbability(Numerator, EntryFreq));
} }
/// doLoop - Propagate block frequency down throught the loop. /// doLoop - Propagate block frequency down through the loop.
void doLoop(BlockT *Head, BlockT *Tail) { void doLoop(BlockT *Head, BlockT *Tail) {
DEBUG(dbgs() << "doLoop(" << getBlockName(Head) << ", " DEBUG(dbgs() << "doLoop(" << getBlockName(Head) << ", "
<< getBlockName(Tail) << ")\n"); << getBlockName(Tail) << ")\n");
SmallPtrSet<BlockT *, 8> BlocksInLoop; SmallPtrSet<BlockT *, 8> BlocksInLoop;
for (rpot_iterator I = rpot_at(Head), E = rpot_at(Tail); ; ++I) { for (rpot_iterator I = rpot_at(Head), E = rpot_at(Tail); ; ++I) {
BlockT *BB = *I; BlockT *BB = *I;
doBlock(BB, Head, BlocksInLoop); doBlock(BB, Head, BlocksInLoop);
 End of changes. 1 change blocks. 
1 lines changed or deleted 1 lines changed or added


 BranchProbabilityInfo.h   BranchProbabilityInfo.h 
skipping to change at line 31 skipping to change at line 31
#include "llvm/Support/BranchProbability.h" #include "llvm/Support/BranchProbability.h"
namespace llvm { namespace llvm {
class LoopInfo; class LoopInfo;
class raw_ostream; class raw_ostream;
/// \brief Analysis pass providing branch probability information. /// \brief Analysis pass providing branch probability information.
/// ///
/// This is a function analysis pass which provides information on the rela tive /// This is a function analysis pass which provides information on the rela tive
/// probabilities of each "edge" in the function's CFG where such an edge i s /// probabilities of each "edge" in the function's CFG where such an edge i s
/// defined by a pair of basic blocks. The probability for a given block an /// defined by a pair (PredBlock and an index in the successors). The
d /// probability of an edge from one block is always relative to the
/// a successor block are always relative to the probabilities of the other /// probabilities of other edges from the block. The probabilites of all ed
/// successor blocks. Another way of looking at it is that the probabilitie ges
s /// from a block sum to exactly one (100%).
/// for a given block B and each of its successors should sum to exactly /// We use a pair (PredBlock and an index in the successors) to uniquely
/// one (100%). /// identify an edge, since we can have multiple edges from Src to Dst.
/// As an example, we can have a switch which jumps to Dst with value 0 and
/// value 10.
class BranchProbabilityInfo : public FunctionPass { class BranchProbabilityInfo : public FunctionPass {
public: public:
static char ID; static char ID;
BranchProbabilityInfo() : FunctionPass(ID) { BranchProbabilityInfo() : FunctionPass(ID) {
initializeBranchProbabilityInfoPass(*PassRegistry::getPassRegistry()); initializeBranchProbabilityInfoPass(*PassRegistry::getPassRegistry());
} }
void getAnalysisUsage(AnalysisUsage &AU) const; void getAnalysisUsage(AnalysisUsage &AU) const;
bool runOnFunction(Function &F); bool runOnFunction(Function &F);
void print(raw_ostream &OS, const Module *M = 0) const; void print(raw_ostream &OS, const Module *M = 0) const;
/// \brief Get an edge's probability, relative to other out-edges of the Src. /// \brief Get an edge's probability, relative to other out-edges of the Src.
/// ///
/// This routine provides access to the fractional probability between ze ro /// This routine provides access to the fractional probability between ze ro
/// (0%) and one (100%) of this edge executing, relative to other edges /// (0%) and one (100%) of this edge executing, relative to other edges
/// leaving the 'Src' block. The returned probability is never zero, and can /// leaving the 'Src' block. The returned probability is never zero, and can
/// only be one if the source block has only one successor. /// only be one if the source block has only one successor.
BranchProbability getEdgeProbability(const BasicBlock *Src, BranchProbability getEdgeProbability(const BasicBlock *Src,
unsigned IndexInSuccessors) const;
/// \brief Get the probability of going from Src to Dst.
///
/// It returns the sum of all probabilities for edges from Src to Dst.
BranchProbability getEdgeProbability(const BasicBlock *Src,
const BasicBlock *Dst) const; const BasicBlock *Dst) const;
/// \brief Test if an edge is hot relative to other out-edges of the Src. /// \brief Test if an edge is hot relative to other out-edges of the Src.
/// ///
/// Check whether this edge out of the source block is 'hot'. We define h ot /// Check whether this edge out of the source block is 'hot'. We define h ot
/// as having a relative probability >= 80%. /// as having a relative probability >= 80%.
bool isEdgeHot(const BasicBlock *Src, const BasicBlock *Dst) const; bool isEdgeHot(const BasicBlock *Src, const BasicBlock *Dst) const;
/// \brief Retrieve the hot successor of a block if one exists. /// \brief Retrieve the hot successor of a block if one exists.
/// ///
skipping to change at line 77 skipping to change at line 86
BasicBlock *getHotSucc(BasicBlock *BB) const; BasicBlock *getHotSucc(BasicBlock *BB) const;
/// \brief Print an edge's probability. /// \brief Print an edge's probability.
/// ///
/// Retrieves an edge's probability similarly to \see getEdgeProbability, but /// Retrieves an edge's probability similarly to \see getEdgeProbability, but
/// then prints that probability to the provided stream. That stream is t hen /// then prints that probability to the provided stream. That stream is t hen
/// returned. /// returned.
raw_ostream &printEdgeProbability(raw_ostream &OS, const BasicBlock *Src, raw_ostream &printEdgeProbability(raw_ostream &OS, const BasicBlock *Src,
const BasicBlock *Dst) const; const BasicBlock *Dst) const;
/// \brief Get the raw edge weight calculated for the block pair. /// \brief Get the raw edge weight calculated for the edge.
/// ///
/// This returns the raw edge weight. It is guaranteed to fall between 1 and /// This returns the raw edge weight. It is guaranteed to fall between 1 and
/// UINT32_MAX. Note that the raw edge weight is not meaningful in isolat ion. /// UINT32_MAX. Note that the raw edge weight is not meaningful in isolat ion.
/// This interface should be very carefully, and primarily by routines th at /// This interface should be very carefully, and primarily by routines th at
/// are updating the analysis by later calling setEdgeWeight. /// are updating the analysis by later calling setEdgeWeight.
uint32_t getEdgeWeight(const BasicBlock *Src,
unsigned IndexInSuccessors) const;
/// \brief Get the raw edge weight calculated for the block pair.
///
/// This returns the sum of all raw edge weights from Src to Dst.
/// It is guaranteed to fall between 1 and UINT32_MAX.
uint32_t getEdgeWeight(const BasicBlock *Src, const BasicBlock *Dst) cons t; uint32_t getEdgeWeight(const BasicBlock *Src, const BasicBlock *Dst) cons t;
/// \brief Set the raw edge weight for the block pair. /// \brief Set the raw edge weight for a given edge.
/// ///
/// This allows a pass to explicitly set the edge weight for a block. It can /// This allows a pass to explicitly set the edge weight for an edge. It can
/// be used when updating the CFG to update and preserve the branch /// be used when updating the CFG to update and preserve the branch
/// probability information. Read the implementation of how these edge /// probability information. Read the implementation of how these edge
/// weights are calculated carefully before using! /// weights are calculated carefully before using!
void setEdgeWeight(const BasicBlock *Src, const BasicBlock *Dst, void setEdgeWeight(const BasicBlock *Src, unsigned IndexInSuccessors,
uint32_t Weight); uint32_t Weight);
private: private:
typedef std::pair<const BasicBlock *, const BasicBlock *> Edge; // Since we allow duplicate edges from one basic block to another, we use
// a pair (PredBlock and an index in the successors) to specify an edge.
typedef std::pair<const BasicBlock *, unsigned> Edge;
// Default weight value. Used when we don't have information about the ed ge. // Default weight value. Used when we don't have information about the ed ge.
// TODO: DEFAULT_WEIGHT makes sense during static predication, when none of // TODO: DEFAULT_WEIGHT makes sense during static predication, when none of
// the successors have a weight yet. But it doesn't make sense when provi ding // the successors have a weight yet. But it doesn't make sense when provi ding
// weight to an edge that may have siblings with non-zero weights. This c an // weight to an edge that may have siblings with non-zero weights. This c an
// be handled various ways, but it's probably fine for an edge with unkno wn // be handled various ways, but it's probably fine for an edge with unkno wn
// weight to just "inherit" the non-zero weight of an adjacent successor. // weight to just "inherit" the non-zero weight of an adjacent successor.
static const uint32_t DEFAULT_WEIGHT = 16; static const uint32_t DEFAULT_WEIGHT = 16;
DenseMap<Edge, uint32_t> Weights; DenseMap<Edge, uint32_t> Weights;
skipping to change at line 125 skipping to change at line 143
/// \brief Get sum of the block successors' weights. /// \brief Get sum of the block successors' weights.
uint32_t getSumForBlock(const BasicBlock *BB) const; uint32_t getSumForBlock(const BasicBlock *BB) const;
bool calcUnreachableHeuristics(BasicBlock *BB); bool calcUnreachableHeuristics(BasicBlock *BB);
bool calcMetadataWeights(BasicBlock *BB); bool calcMetadataWeights(BasicBlock *BB);
bool calcPointerHeuristics(BasicBlock *BB); bool calcPointerHeuristics(BasicBlock *BB);
bool calcLoopBranchHeuristics(BasicBlock *BB); bool calcLoopBranchHeuristics(BasicBlock *BB);
bool calcZeroHeuristics(BasicBlock *BB); bool calcZeroHeuristics(BasicBlock *BB);
bool calcFloatingPointHeuristics(BasicBlock *BB); bool calcFloatingPointHeuristics(BasicBlock *BB);
bool calcInvokeHeuristics(BasicBlock *BB);
}; };
} }
#endif #endif
 End of changes. 9 change blocks. 
12 lines changed or deleted 30 lines changed or added


 BuildLibCalls.h   BuildLibCalls.h 
skipping to change at line 18 skipping to change at line 18
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// //
// This file exposes an interface to build some C language libcalls for // This file exposes an interface to build some C language libcalls for
// optimization passes that need to call the various functions. // optimization passes that need to call the various functions.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef TRANSFORMS_UTILS_BUILDLIBCALLS_H #ifndef TRANSFORMS_UTILS_BUILDLIBCALLS_H
#define TRANSFORMS_UTILS_BUILDLIBCALLS_H #define TRANSFORMS_UTILS_BUILDLIBCALLS_H
#include "llvm/Support/IRBuilder.h" #include "llvm/IRBuilder.h"
namespace llvm { namespace llvm {
class Value; class Value;
class TargetData; class DataLayout;
class TargetLibraryInfo; class TargetLibraryInfo;
/// CastToCStr - Return V if it is an i8*, otherwise cast it to i8*. /// CastToCStr - Return V if it is an i8*, otherwise cast it to i8*.
Value *CastToCStr(Value *V, IRBuilder<> &B); Value *CastToCStr(Value *V, IRBuilder<> &B);
/// EmitStrLen - Emit a call to the strlen function to the builder, for t he /// EmitStrLen - Emit a call to the strlen function to the builder, for t he
/// specified pointer. Ptr is required to be some pointer type, and the /// specified pointer. Ptr is required to be some pointer type, and the
/// return value has 'intptr_t' type. /// return value has 'intptr_t' type.
Value *EmitStrLen(Value *Ptr, IRBuilder<> &B, const TargetData *TD); Value *EmitStrLen(Value *Ptr, IRBuilder<> &B, const DataLayout *TD,
const TargetLibraryInfo *TLI);
/// EmitStrNLen - Emit a call to the strnlen function to the builder, for
the
/// specified pointer. Ptr is required to be some pointer type, MaxLen m
ust
/// be of size_t type, and the return value has 'intptr_t' type.
Value *EmitStrNLen(Value *Ptr, Value *MaxLen, IRBuilder<> &B,
const DataLayout *TD, const TargetLibraryInfo *TLI);
/// EmitStrChr - Emit a call to the strchr function to the builder, for t he /// EmitStrChr - Emit a call to the strchr function to the builder, for t he
/// specified pointer and character. Ptr is required to be some pointer type, /// specified pointer and character. Ptr is required to be some pointer type,
/// and the return value has 'i8*' type. /// and the return value has 'i8*' type.
Value *EmitStrChr(Value *Ptr, char C, IRBuilder<> &B, const TargetData *T Value *EmitStrChr(Value *Ptr, char C, IRBuilder<> &B, const DataLayout *T
D); D,
const TargetLibraryInfo *TLI);
/// EmitStrNCmp - Emit a call to the strncmp function to the builder. /// EmitStrNCmp - Emit a call to the strncmp function to the builder.
Value *EmitStrNCmp(Value *Ptr1, Value *Ptr2, Value *Len, IRBuilder<> &B, Value *EmitStrNCmp(Value *Ptr1, Value *Ptr2, Value *Len, IRBuilder<> &B,
const TargetData *TD); const DataLayout *TD, const TargetLibraryInfo *TLI);
/// EmitStrCpy - Emit a call to the strcpy function to the builder, for t he /// EmitStrCpy - Emit a call to the strcpy function to the builder, for t he
/// specified pointer arguments. /// specified pointer arguments.
Value *EmitStrCpy(Value *Dst, Value *Src, IRBuilder<> &B, Value *EmitStrCpy(Value *Dst, Value *Src, IRBuilder<> &B,
const TargetData *TD, StringRef Name = "strcpy"); const DataLayout *TD, const TargetLibraryInfo *TLI,
StringRef Name = "strcpy");
/// EmitStrNCpy - Emit a call to the strncpy function to the builder, for the /// EmitStrNCpy - Emit a call to the strncpy function to the builder, for the
/// specified pointer arguments and length. /// specified pointer arguments and length.
Value *EmitStrNCpy(Value *Dst, Value *Src, Value *Len, IRBuilder<> &B, Value *EmitStrNCpy(Value *Dst, Value *Src, Value *Len, IRBuilder<> &B,
const TargetData *TD, StringRef Name = "strncpy"); const DataLayout *TD, const TargetLibraryInfo *TLI,
StringRef Name = "strncpy");
/// EmitMemCpyChk - Emit a call to the __memcpy_chk function to the build er. /// EmitMemCpyChk - Emit a call to the __memcpy_chk function to the build er.
/// This expects that the Len and ObjSize have type 'intptr_t' and Dst/Sr c /// This expects that the Len and ObjSize have type 'intptr_t' and Dst/Sr c
/// are pointers. /// are pointers.
Value *EmitMemCpyChk(Value *Dst, Value *Src, Value *Len, Value *ObjSize, Value *EmitMemCpyChk(Value *Dst, Value *Src, Value *Len, Value *ObjSize,
IRBuilder<> &B, const TargetData *TD); IRBuilder<> &B, const DataLayout *TD,
const TargetLibraryInfo *TLI);
/// EmitMemChr - Emit a call to the memchr function. This assumes that P tr is /// EmitMemChr - Emit a call to the memchr function. This assumes that P tr is
/// a pointer, Val is an i32 value, and Len is an 'intptr_t' value. /// a pointer, Val is an i32 value, and Len is an 'intptr_t' value.
Value *EmitMemChr(Value *Ptr, Value *Val, Value *Len, IRBuilder<> &B, Value *EmitMemChr(Value *Ptr, Value *Val, Value *Len, IRBuilder<> &B,
const TargetData *TD); const DataLayout *TD, const TargetLibraryInfo *TLI);
/// EmitMemCmp - Emit a call to the memcmp function. /// EmitMemCmp - Emit a call to the memcmp function.
Value *EmitMemCmp(Value *Ptr1, Value *Ptr2, Value *Len, IRBuilder<> &B, Value *EmitMemCmp(Value *Ptr1, Value *Ptr2, Value *Len, IRBuilder<> &B,
const TargetData *TD); const DataLayout *TD, const TargetLibraryInfo *TLI);
/// EmitUnaryFloatFnCall - Emit a call to the unary function named 'Name' /// EmitUnaryFloatFnCall - Emit a call to the unary function named 'Name'
/// (e.g. 'floor'). This function is known to take a single of type mat ching /// (e.g. 'floor'). This function is known to take a single of type mat ching
/// 'Op' and returns one value with the same type. If 'Op' is a long dou ble, /// 'Op' and returns one value with the same type. If 'Op' is a long dou ble,
/// 'l' is added as the suffix of name, if 'Op' is a float, we add a 'f' /// 'l' is added as the suffix of name, if 'Op' is a float, we add a 'f'
/// suffix. /// suffix.
Value *EmitUnaryFloatFnCall(Value *Op, StringRef Name, IRBuilder<> &B, Value *EmitUnaryFloatFnCall(Value *Op, StringRef Name, IRBuilder<> &B,
const AttrListPtr &Attrs); const AttrListPtr &Attrs);
/// EmitPutChar - Emit a call to the putchar function. This assumes that Char /// EmitPutChar - Emit a call to the putchar function. This assumes that Char
/// is an integer. /// is an integer.
Value *EmitPutChar(Value *Char, IRBuilder<> &B, const TargetData *TD); Value *EmitPutChar(Value *Char, IRBuilder<> &B, const DataLayout *TD,
const TargetLibraryInfo *TLI);
/// EmitPutS - Emit a call to the puts function. This assumes that Str i s /// EmitPutS - Emit a call to the puts function. This assumes that Str i s
/// some pointer. /// some pointer.
void EmitPutS(Value *Str, IRBuilder<> &B, const TargetData *TD); Value *EmitPutS(Value *Str, IRBuilder<> &B, const DataLayout *TD,
const TargetLibraryInfo *TLI);
/// EmitFPutC - Emit a call to the fputc function. This assumes that Cha r is /// EmitFPutC - Emit a call to the fputc function. This assumes that Cha r is
/// an i32, and File is a pointer to FILE. /// an i32, and File is a pointer to FILE.
void EmitFPutC(Value *Char, Value *File, IRBuilder<> &B, Value *EmitFPutC(Value *Char, Value *File, IRBuilder<> &B,
const TargetData *TD); const DataLayout *TD, const TargetLibraryInfo *TLI);
/// EmitFPutS - Emit a call to the puts function. Str is required to be a /// EmitFPutS - Emit a call to the puts function. Str is required to be a
/// pointer and File is a pointer to FILE. /// pointer and File is a pointer to FILE.
void EmitFPutS(Value *Str, Value *File, IRBuilder<> &B, const TargetData Value *EmitFPutS(Value *Str, Value *File, IRBuilder<> &B, const DataLayou
*TD, t *TD,
const TargetLibraryInfo *TLI); const TargetLibraryInfo *TLI);
/// EmitFWrite - Emit a call to the fwrite function. This assumes that P tr is /// EmitFWrite - Emit a call to the fwrite function. This assumes that P tr is
/// a pointer, Size is an 'intptr_t', and File is a pointer to FILE. /// a pointer, Size is an 'intptr_t', and File is a pointer to FILE.
void EmitFWrite(Value *Ptr, Value *Size, Value *File, IRBuilder<> &B, Value *EmitFWrite(Value *Ptr, Value *Size, Value *File, IRBuilder<> &B,
const TargetData *TD, const TargetLibraryInfo *TLI); const DataLayout *TD, const TargetLibraryInfo *TLI);
/// SimplifyFortifiedLibCalls - Helper class for folding checked library /// SimplifyFortifiedLibCalls - Helper class for folding checked library
/// calls (e.g. __strcpy_chk) into their unchecked counterparts. /// calls (e.g. __strcpy_chk) into their unchecked counterparts.
class SimplifyFortifiedLibCalls { class SimplifyFortifiedLibCalls {
protected: protected:
CallInst *CI; CallInst *CI;
virtual void replaceCall(Value *With) = 0; virtual void replaceCall(Value *With) = 0;
virtual bool isFoldable(unsigned SizeCIOp, unsigned SizeArgOp, virtual bool isFoldable(unsigned SizeCIOp, unsigned SizeArgOp,
bool isString) const = 0; bool isString) const = 0;
public: public:
virtual ~SimplifyFortifiedLibCalls(); virtual ~SimplifyFortifiedLibCalls();
bool fold(CallInst *CI, const TargetData *TD); bool fold(CallInst *CI, const DataLayout *TD, const TargetLibraryInfo * TLI);
}; };
} }
#endif #endif
 End of changes. 16 change blocks. 
21 lines changed or deleted 36 lines changed or added


 COFF.h   COFF.h 
skipping to change at line 119 skipping to change at line 119
virtual error_code getSymbolNext(DataRefImpl Symb, SymbolRef &Res) const; virtual error_code getSymbolNext(DataRefImpl Symb, SymbolRef &Res) const;
virtual error_code getSymbolName(DataRefImpl Symb, StringRef &Res) const; virtual error_code getSymbolName(DataRefImpl Symb, StringRef &Res) const;
virtual error_code getSymbolFileOffset(DataRefImpl Symb, uint64_t &Res) c onst; virtual error_code getSymbolFileOffset(DataRefImpl Symb, uint64_t &Res) c onst;
virtual error_code getSymbolAddress(DataRefImpl Symb, uint64_t &Res) cons t; virtual error_code getSymbolAddress(DataRefImpl Symb, uint64_t &Res) cons t;
virtual error_code getSymbolSize(DataRefImpl Symb, uint64_t &Res) const; virtual error_code getSymbolSize(DataRefImpl Symb, uint64_t &Res) const;
virtual error_code getSymbolNMTypeChar(DataRefImpl Symb, char &Res) const ; virtual error_code getSymbolNMTypeChar(DataRefImpl Symb, char &Res) const ;
virtual error_code getSymbolFlags(DataRefImpl Symb, uint32_t &Res) const; virtual error_code getSymbolFlags(DataRefImpl Symb, uint32_t &Res) const;
virtual error_code getSymbolType(DataRefImpl Symb, SymbolRef::Type &Res) const; virtual error_code getSymbolType(DataRefImpl Symb, SymbolRef::Type &Res) const;
virtual error_code getSymbolSection(DataRefImpl Symb, virtual error_code getSymbolSection(DataRefImpl Symb,
section_iterator &Res) const; section_iterator &Res) const;
virtual error_code getSymbolValue(DataRefImpl Symb, uint64_t &Val) const;
virtual error_code getSectionNext(DataRefImpl Sec, SectionRef &Res) const ; virtual error_code getSectionNext(DataRefImpl Sec, SectionRef &Res) const ;
virtual error_code getSectionName(DataRefImpl Sec, StringRef &Res) const; virtual error_code getSectionName(DataRefImpl Sec, StringRef &Res) const;
virtual error_code getSectionAddress(DataRefImpl Sec, uint64_t &Res) cons t; virtual error_code getSectionAddress(DataRefImpl Sec, uint64_t &Res) cons t;
virtual error_code getSectionSize(DataRefImpl Sec, uint64_t &Res) const; virtual error_code getSectionSize(DataRefImpl Sec, uint64_t &Res) const;
virtual error_code getSectionContents(DataRefImpl Sec, StringRef &Res) co nst; virtual error_code getSectionContents(DataRefImpl Sec, StringRef &Res) co nst;
virtual error_code getSectionAlignment(DataRefImpl Sec, uint64_t &Res) co nst; virtual error_code getSectionAlignment(DataRefImpl Sec, uint64_t &Res) co nst;
virtual error_code isSectionText(DataRefImpl Sec, bool &Res) const; virtual error_code isSectionText(DataRefImpl Sec, bool &Res) const;
virtual error_code isSectionData(DataRefImpl Sec, bool &Res) const; virtual error_code isSectionData(DataRefImpl Sec, bool &Res) const;
virtual error_code isSectionBSS(DataRefImpl Sec, bool &Res) const; virtual error_code isSectionBSS(DataRefImpl Sec, bool &Res) const;
virtual error_code isSectionVirtual(DataRefImpl Sec, bool &Res) const; virtual error_code isSectionVirtual(DataRefImpl Sec, bool &Res) const;
virtual error_code isSectionZeroInit(DataRefImpl Sec, bool &Res) const; virtual error_code isSectionZeroInit(DataRefImpl Sec, bool &Res) const;
virtual error_code isSectionReadOnlyData(DataRefImpl Sec, bool &Res) cons t;
virtual error_code isSectionRequiredForExecution(DataRefImpl Sec, virtual error_code isSectionRequiredForExecution(DataRefImpl Sec,
bool &Res) const; bool &Res) const;
virtual error_code sectionContainsSymbol(DataRefImpl Sec, DataRefImpl Sym b, virtual error_code sectionContainsSymbol(DataRefImpl Sec, DataRefImpl Sym b,
bool &Result) const; bool &Result) const;
virtual relocation_iterator getSectionRelBegin(DataRefImpl Sec) const; virtual relocation_iterator getSectionRelBegin(DataRefImpl Sec) const;
virtual relocation_iterator getSectionRelEnd(DataRefImpl Sec) const; virtual relocation_iterator getSectionRelEnd(DataRefImpl Sec) const;
virtual error_code getRelocationNext(DataRefImpl Rel, virtual error_code getRelocationNext(DataRefImpl Rel,
RelocationRef &Res) const; RelocationRef &Res) const;
virtual error_code getRelocationAddress(DataRefImpl Rel, virtual error_code getRelocationAddress(DataRefImpl Rel,
skipping to change at line 171 skipping to change at line 173
COFFObjectFile(MemoryBuffer *Object, error_code &ec); COFFObjectFile(MemoryBuffer *Object, error_code &ec);
virtual symbol_iterator begin_symbols() const; virtual symbol_iterator begin_symbols() const;
virtual symbol_iterator end_symbols() const; virtual symbol_iterator end_symbols() const;
virtual symbol_iterator begin_dynamic_symbols() const; virtual symbol_iterator begin_dynamic_symbols() const;
virtual symbol_iterator end_dynamic_symbols() const; virtual symbol_iterator end_dynamic_symbols() const;
virtual library_iterator begin_libraries_needed() const; virtual library_iterator begin_libraries_needed() const;
virtual library_iterator end_libraries_needed() const; virtual library_iterator end_libraries_needed() const;
virtual section_iterator begin_sections() const; virtual section_iterator begin_sections() const;
virtual section_iterator end_sections() const; virtual section_iterator end_sections() const;
const coff_section *getCOFFSection(section_iterator &It) const;
const coff_symbol *getCOFFSymbol(symbol_iterator &It) const;
const coff_relocation *getCOFFRelocation(relocation_iterator &It) const;
virtual uint8_t getBytesInAddress() const; virtual uint8_t getBytesInAddress() const;
virtual StringRef getFileFormatName() const; virtual StringRef getFileFormatName() const;
virtual unsigned getArch() const; virtual unsigned getArch() const;
virtual StringRef getLoadName() const; virtual StringRef getLoadName() const;
error_code getHeader(const coff_file_header *&Res) const; error_code getHeader(const coff_file_header *&Res) const;
error_code getSection(int32_t index, const coff_section *&Res) const; error_code getSection(int32_t index, const coff_section *&Res) const;
error_code getSymbol(uint32_t index, const coff_symbol *&Res) const; error_code getSymbol(uint32_t index, const coff_symbol *&Res) const;
template <typename T> template <typename T>
error_code getAuxSymbol(uint32_t index, const T *&Res) const { error_code getAuxSymbol(uint32_t index, const T *&Res) const {
const coff_symbol *s; const coff_symbol *s;
error_code ec = getSymbol(index, s); error_code ec = getSymbol(index, s);
Res = reinterpret_cast<const T*>(s); Res = reinterpret_cast<const T*>(s);
return ec; return ec;
} }
error_code getSymbolName(const coff_symbol *symbol, StringRef &Res) const ; error_code getSymbolName(const coff_symbol *symbol, StringRef &Res) const ;
ArrayRef<uint8_t> getSymbolAuxData(const coff_symbol *symbol) const;
error_code getSectionName(const coff_section *Sec, StringRef &Res) const; error_code getSectionName(const coff_section *Sec, StringRef &Res) const;
error_code getSectionContents(const coff_section *Sec, error_code getSectionContents(const coff_section *Sec,
ArrayRef<uint8_t> &Res) const; ArrayRef<uint8_t> &Res) const;
static inline bool classof(const Binary *v) { static inline bool classof(const Binary *v) {
return v->isCOFF(); return v->isCOFF();
} }
static inline bool classof(const COFFObjectFile *v) { return true; }
}; };
} }
} }
#endif #endif
 End of changes. 5 change blocks. 
1 lines changed or deleted 8 lines changed or added


 CallGraph.h   CallGraph.h 
skipping to change at line 188 skipping to change at line 188
// and the callgraph node being called. // and the callgraph node being called.
public: public:
typedef std::pair<WeakVH, CallGraphNode*> CallRecord; typedef std::pair<WeakVH, CallGraphNode*> CallRecord;
private: private:
std::vector<CallRecord> CalledFunctions; std::vector<CallRecord> CalledFunctions;
/// NumReferences - This is the number of times that this CallGraphNode o ccurs /// NumReferences - This is the number of times that this CallGraphNode o ccurs
/// in the CalledFunctions array of this or other CallGraphNodes. /// in the CalledFunctions array of this or other CallGraphNodes.
unsigned NumReferences; unsigned NumReferences;
CallGraphNode(const CallGraphNode &); // DO NOT IMPLEMENT CallGraphNode(const CallGraphNode &) LLVM_DELETED_FUNCTION;
void operator=(const CallGraphNode &); // DO NOT IMPLEMENT void operator=(const CallGraphNode &) LLVM_DELETED_FUNCTION;
void DropRef() { --NumReferences; } void DropRef() { --NumReferences; }
void AddRef() { ++NumReferences; } void AddRef() { ++NumReferences; }
public: public:
typedef std::vector<CallRecord> CalledFunctionsVector; typedef std::vector<CallRecord> CalledFunctionsVector;
// CallGraphNode ctor - Create a node for the specified function. // CallGraphNode ctor - Create a node for the specified function.
inline CallGraphNode(Function *f) : F(f), NumReferences(0) {} inline CallGraphNode(Function *f) : F(f), NumReferences(0) {}
~CallGraphNode() { ~CallGraphNode() {
assert(NumReferences == 0 && "Node deleted while references remain"); assert(NumReferences == 0 && "Node deleted while references remain");
 End of changes. 1 change blocks. 
2 lines changed or deleted 2 lines changed or added


 CallSite.h   CallSite.h 
skipping to change at line 84 skipping to change at line 84
bool isCall() const { return I.getInt(); } bool isCall() const { return I.getInt(); }
/// isInvoke - true if a InvokeInst is enclosed. /// isInvoke - true if a InvokeInst is enclosed.
/// ///
bool isInvoke() const { return getInstruction() && !I.getInt(); } bool isInvoke() const { return getInstruction() && !I.getInt(); }
InstrTy *getInstruction() const { return I.getPointer(); } InstrTy *getInstruction() const { return I.getPointer(); }
InstrTy *operator->() const { return I.getPointer(); } InstrTy *operator->() const { return I.getPointer(); }
operator bool() const { return I.getPointer(); } operator bool() const { return I.getPointer(); }
/// getCalledValue - Return the pointer to function that is being called. .. /// getCalledValue - Return the pointer to function that is being called.
/// ///
ValTy *getCalledValue() const { ValTy *getCalledValue() const {
assert(getInstruction() && "Not a call or invoke instruction!"); assert(getInstruction() && "Not a call or invoke instruction!");
return *getCallee(); return *getCallee();
} }
/// getCalledFunction - Return the function being called if this is a dir ect /// getCalledFunction - Return the function being called if this is a dir ect
/// call, otherwise return null (if it's an indirect call). /// call, otherwise return null (if it's an indirect call).
/// ///
FunTy *getCalledFunction() const { FunTy *getCalledFunction() const {
return dyn_cast<FunTy>(getCalledValue()); return dyn_cast<FunTy>(getCalledValue());
} }
/// setCalledFunction - Set the callee to the specified value... /// setCalledFunction - Set the callee to the specified value.
/// ///
void setCalledFunction(Value *V) { void setCalledFunction(Value *V) {
assert(getInstruction() && "Not a call or invoke instruction!"); assert(getInstruction() && "Not a call or invoke instruction!");
*getCallee() = V; *getCallee() = V;
} }
/// isCallee - Determine whether the passed iterator points to the /// isCallee - Determine whether the passed iterator points to the
/// callee operand's Use. /// callee operand's Use.
/// ///
bool isCallee(value_use_iterator<UserTy> UI) const { bool isCallee(value_use_iterator<UserTy> UI) const {
skipping to change at line 133 skipping to change at line 133
/// Given a value use iterator, returns the argument that corresponds to it. /// Given a value use iterator, returns the argument that corresponds to it.
/// Iterator must actually correspond to an argument. /// Iterator must actually correspond to an argument.
unsigned getArgumentNo(value_use_iterator<UserTy> I) const { unsigned getArgumentNo(value_use_iterator<UserTy> I) const {
assert(getInstruction() && "Not a call or invoke instruction!"); assert(getInstruction() && "Not a call or invoke instruction!");
assert(arg_begin() <= &I.getUse() && &I.getUse() < arg_end() assert(arg_begin() <= &I.getUse() && &I.getUse() < arg_end()
&& "Argument # out of range!"); && "Argument # out of range!");
return &I.getUse() - arg_begin(); return &I.getUse() - arg_begin();
} }
/// arg_iterator - The type of iterator to use when looping over actual /// arg_iterator - The type of iterator to use when looping over actual
/// arguments at this call site... /// arguments at this call site.
typedef IterTy arg_iterator; typedef IterTy arg_iterator;
/// arg_begin/arg_end - Return iterators corresponding to the actual argu ment /// arg_begin/arg_end - Return iterators corresponding to the actual argu ment
/// list for a call site. /// list for a call site.
IterTy arg_begin() const { IterTy arg_begin() const {
assert(getInstruction() && "Not a call or invoke instruction!"); assert(getInstruction() && "Not a call or invoke instruction!");
// Skip non-arguments // Skip non-arguments
return (*this)->op_begin(); return (*this)->op_begin();
} }
skipping to change at line 187 skipping to change at line 187
/// getAttributes/setAttributes - get or set the parameter attributes of /// getAttributes/setAttributes - get or set the parameter attributes of
/// the call. /// the call.
const AttrListPtr &getAttributes() const { const AttrListPtr &getAttributes() const {
CALLSITE_DELEGATE_GETTER(getAttributes()); CALLSITE_DELEGATE_GETTER(getAttributes());
} }
void setAttributes(const AttrListPtr &PAL) { void setAttributes(const AttrListPtr &PAL) {
CALLSITE_DELEGATE_SETTER(setAttributes(PAL)); CALLSITE_DELEGATE_SETTER(setAttributes(PAL));
} }
/// paramHasAttr - whether the call or the callee has the given attribute /// \brief Return true if this function has the given attribute.
. bool hasFnAttr(Attributes::AttrVal A) const {
bool paramHasAttr(uint16_t i, Attributes attr) const { CALLSITE_DELEGATE_GETTER(hasFnAttr(A));
CALLSITE_DELEGATE_GETTER(paramHasAttr(i, attr)); }
/// \brief Return true if the call or the callee has the given attribute.
bool paramHasAttr(unsigned i, Attributes::AttrVal A) const {
CALLSITE_DELEGATE_GETTER(paramHasAttr(i, A));
} }
/// @brief Extract the alignment for a call or parameter (0=unknown). /// @brief Extract the alignment for a call or parameter (0=unknown).
uint16_t getParamAlignment(uint16_t i) const { uint16_t getParamAlignment(uint16_t i) const {
CALLSITE_DELEGATE_GETTER(getParamAlignment(i)); CALLSITE_DELEGATE_GETTER(getParamAlignment(i));
} }
/// @brief Return true if the call should not be inlined. /// @brief Return true if the call should not be inlined.
bool isNoInline() const { bool isNoInline() const {
CALLSITE_DELEGATE_GETTER(isNoInline()); CALLSITE_DELEGATE_GETTER(isNoInline());
} }
void setIsNoInline(bool Value = true) { void setIsNoInline(bool Value = true) {
CALLSITE_DELEGATE_SETTER(setIsNoInline(Value)); CALLSITE_DELEGATE_SETTER(setIsNoInline(Value));
} }
/// @brief Determine if the call does not access memory. /// @brief Determine if the call does not access memory.
bool doesNotAccessMemory() const { bool doesNotAccessMemory() const {
CALLSITE_DELEGATE_GETTER(doesNotAccessMemory()); CALLSITE_DELEGATE_GETTER(doesNotAccessMemory());
} }
void setDoesNotAccessMemory(bool doesNotAccessMemory = true) { void setDoesNotAccessMemory() {
CALLSITE_DELEGATE_SETTER(setDoesNotAccessMemory(doesNotAccessMemory)); CALLSITE_DELEGATE_SETTER(setDoesNotAccessMemory());
} }
/// @brief Determine if the call does not access or only reads memory. /// @brief Determine if the call does not access or only reads memory.
bool onlyReadsMemory() const { bool onlyReadsMemory() const {
CALLSITE_DELEGATE_GETTER(onlyReadsMemory()); CALLSITE_DELEGATE_GETTER(onlyReadsMemory());
} }
void setOnlyReadsMemory(bool onlyReadsMemory = true) { void setOnlyReadsMemory() {
CALLSITE_DELEGATE_SETTER(setOnlyReadsMemory(onlyReadsMemory)); CALLSITE_DELEGATE_SETTER(setOnlyReadsMemory());
} }
/// @brief Determine if the call cannot return. /// @brief Determine if the call cannot return.
bool doesNotReturn() const { bool doesNotReturn() const {
CALLSITE_DELEGATE_GETTER(doesNotReturn()); CALLSITE_DELEGATE_GETTER(doesNotReturn());
} }
void setDoesNotReturn(bool doesNotReturn = true) { void setDoesNotReturn() {
CALLSITE_DELEGATE_SETTER(setDoesNotReturn(doesNotReturn)); CALLSITE_DELEGATE_SETTER(setDoesNotReturn());
} }
/// @brief Determine if the call cannot unwind. /// @brief Determine if the call cannot unwind.
bool doesNotThrow() const { bool doesNotThrow() const {
CALLSITE_DELEGATE_GETTER(doesNotThrow()); CALLSITE_DELEGATE_GETTER(doesNotThrow());
} }
void setDoesNotThrow(bool doesNotThrow = true) { void setDoesNotThrow() {
CALLSITE_DELEGATE_SETTER(setDoesNotThrow(doesNotThrow)); CALLSITE_DELEGATE_SETTER(setDoesNotThrow());
} }
#undef CALLSITE_DELEGATE_GETTER #undef CALLSITE_DELEGATE_GETTER
#undef CALLSITE_DELEGATE_SETTER #undef CALLSITE_DELEGATE_SETTER
/// @brief Determine whether this argument is not captured. /// @brief Determine whether this argument is not captured.
bool doesNotCapture(unsigned ArgNo) const { bool doesNotCapture(unsigned ArgNo) const {
return paramHasAttr(ArgNo + 1, Attribute::NoCapture); return paramHasAttr(ArgNo + 1, Attributes::NoCapture);
} }
/// @brief Determine whether this argument is passed by value. /// @brief Determine whether this argument is passed by value.
bool isByValArgument(unsigned ArgNo) const { bool isByValArgument(unsigned ArgNo) const {
return paramHasAttr(ArgNo + 1, Attribute::ByVal); return paramHasAttr(ArgNo + 1, Attributes::ByVal);
} }
/// hasArgument - Returns true if this CallSite passes the given Value* a s an /// hasArgument - Returns true if this CallSite passes the given Value* a s an
/// argument to the called function. /// argument to the called function.
bool hasArgument(const Value *Arg) const { bool hasArgument(const Value *Arg) const {
for (arg_iterator AI = this->arg_begin(), E = this->arg_end(); AI != E; for (arg_iterator AI = this->arg_begin(), E = this->arg_end(); AI != E;
++AI) ++AI)
if (AI->get() == Arg) if (AI->get() == Arg)
return true; return true;
return false; return false;
 End of changes. 10 change blocks. 
17 lines changed or deleted 21 lines changed or added


 CallingConv.h   CallingConv.h 
skipping to change at line 97 skipping to change at line 97
/// PTX_Device - Call to a PTX device function. /// PTX_Device - Call to a PTX device function.
/// Passes all arguments in register or parameter space. /// Passes all arguments in register or parameter space.
PTX_Device = 72, PTX_Device = 72,
/// MBLAZE_INTR - Calling convention used for MBlaze interrupt routines . /// MBLAZE_INTR - Calling convention used for MBlaze interrupt routines .
MBLAZE_INTR = 73, MBLAZE_INTR = 73,
/// MBLAZE_INTR - Calling convention used for MBlaze interrupt support /// MBLAZE_INTR - Calling convention used for MBlaze interrupt support
/// routines (i.e. GCC's save_volatiles attribute). /// routines (i.e. GCC's save_volatiles attribute).
MBLAZE_SVOL = 74 MBLAZE_SVOL = 74,
/// SPIR_FUNC - Calling convention for SPIR non-kernel device functions
.
/// No lowering or expansion of arguments.
/// Structures are passed as a pointer to a struct with the byval attri
bute.
/// Functions can only call SPIR_FUNC and SPIR_KERNEL functions.
/// Functions can only have zero or one return values.
/// Variable arguments are not allowed, except for printf.
/// How arguments/return values are lowered are not specified.
/// Functions are only visible to the devices.
SPIR_FUNC = 75,
/// SPIR_KERNEL - Calling convention for SPIR kernel functions.
/// Inherits the restrictions of SPIR_FUNC, except
/// Cannot have non-void return values.
/// Cannot have variable arguments.
/// Can also be called by the host.
/// Is externally visible.
SPIR_KERNEL = 76,
/// Intel_OCL_BI - Calling conventions for Intel OpenCL built-ins
Intel_OCL_BI = 77
}; };
} // End CallingConv namespace } // End CallingConv namespace
} // End llvm namespace } // End llvm namespace
#endif #endif
 End of changes. 1 change blocks. 
1 lines changed or deleted 25 lines changed or added


 CallingConvLower.h   CallingConvLower.h 
skipping to change at line 20 skipping to change at line 20
// This file declares the CCState and CCValAssign classes, used for lowerin g // This file declares the CCState and CCValAssign classes, used for lowerin g
// and implementing calling conventions. // and implementing calling conventions.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_CODEGEN_CALLINGCONVLOWER_H #ifndef LLVM_CODEGEN_CALLINGCONVLOWER_H
#define LLVM_CODEGEN_CALLINGCONVLOWER_H #define LLVM_CODEGEN_CALLINGCONVLOWER_H
#include "llvm/ADT/SmallVector.h" #include "llvm/ADT/SmallVector.h"
#include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/ValueTypes.h" #include "llvm/CodeGen/ValueTypes.h"
#include "llvm/Target/TargetCallingConv.h" #include "llvm/Target/TargetCallingConv.h"
#include "llvm/CallingConv.h" #include "llvm/CallingConv.h"
namespace llvm { namespace llvm {
class TargetRegisterInfo; class TargetRegisterInfo;
class TargetMachine; class TargetMachine;
class CCState; class CCState;
/// CCValAssign - Represent assignment of one arg/retval to a location. /// CCValAssign - Represent assignment of one arg/retval to a location.
skipping to change at line 291 skipping to change at line 292
return Reg; return Reg;
} }
/// AllocateStack - Allocate a chunk of stack space with the specified si ze /// AllocateStack - Allocate a chunk of stack space with the specified si ze
/// and alignment. /// and alignment.
unsigned AllocateStack(unsigned Size, unsigned Align) { unsigned AllocateStack(unsigned Size, unsigned Align) {
assert(Align && ((Align-1) & Align) == 0); // Align is power of 2. assert(Align && ((Align-1) & Align) == 0); // Align is power of 2.
StackOffset = ((StackOffset + Align-1) & ~(Align-1)); StackOffset = ((StackOffset + Align-1) & ~(Align-1));
unsigned Result = StackOffset; unsigned Result = StackOffset;
StackOffset += Size; StackOffset += Size;
MF.getFrameInfo()->ensureMaxAlignment(Align);
return Result; return Result;
} }
/// Version of AllocateStack with extra register to be shadowed. /// Version of AllocateStack with extra register to be shadowed.
unsigned AllocateStack(unsigned Size, unsigned Align, unsigned ShadowReg) { unsigned AllocateStack(unsigned Size, unsigned Align, unsigned ShadowReg) {
MarkAllocated(ShadowReg); MarkAllocated(ShadowReg);
return AllocateStack(Size, Align); return AllocateStack(Size, Align);
} }
// HandleByVal - Allocate a stack slot large enough to pass an argument b y // HandleByVal - Allocate a stack slot large enough to pass an argument b y
 End of changes. 2 change blocks. 
0 lines changed or deleted 2 lines changed or added


 CaptureTracking.h   CaptureTracking.h 
skipping to change at line 49 skipping to change at line 49
/// tooManyUses - The depth of traversal has breached a limit. There ma y be /// tooManyUses - The depth of traversal has breached a limit. There ma y be
/// capturing instructions that will not be passed into captured(). /// capturing instructions that will not be passed into captured().
virtual void tooManyUses() = 0; virtual void tooManyUses() = 0;
/// shouldExplore - This is the use of a value derived from the pointer . /// shouldExplore - This is the use of a value derived from the pointer .
/// To prune the search (ie., assume that none of its users could possi bly /// To prune the search (ie., assume that none of its users could possi bly
/// capture) return false. To search it, return true. /// capture) return false. To search it, return true.
/// ///
/// U->getUser() is always an Instruction. /// U->getUser() is always an Instruction.
virtual bool shouldExplore(Use *U) = 0; virtual bool shouldExplore(Use *U);
/// captured - Information about the pointer was captured by the user o f /// captured - Information about the pointer was captured by the user o f
/// use U. Return true to stop the traversal or false to continue looki ng /// use U. Return true to stop the traversal or false to continue looki ng
/// for more capturing instructions. /// for more capturing instructions.
virtual bool captured(Use *U) = 0; virtual bool captured(Use *U) = 0;
}; };
/// PointerMayBeCaptured - Visit the value and the values derived from it and /// PointerMayBeCaptured - Visit the value and the values derived from it and
/// find values which appear to be capturing the pointer value. This feed s /// find values which appear to be capturing the pointer value. This feed s
/// results into and is controlled by the CaptureTracker object. /// results into and is controlled by the CaptureTracker object.
 End of changes. 1 change blocks. 
1 lines changed or deleted 1 lines changed or added


 Casting.h   Casting.h 
skipping to change at line 18 skipping to change at line 18
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// //
// This file defines the isa<X>(), cast<X>(), dyn_cast<X>(), cast_or_null<X >(), // This file defines the isa<X>(), cast<X>(), dyn_cast<X>(), cast_or_null<X >(),
// and dyn_cast_or_null<X>() templates. // and dyn_cast_or_null<X>() templates.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_SUPPORT_CASTING_H #ifndef LLVM_SUPPORT_CASTING_H
#define LLVM_SUPPORT_CASTING_H #define LLVM_SUPPORT_CASTING_H
#include "llvm/Support/type_traits.h"
#include <cassert> #include <cassert>
namespace llvm { namespace llvm {
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// isa<x> Support Templates // isa<x> Support Templates
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// Define a template that can be specialized by smart pointers to reflect t he // Define a template that can be specialized by smart pointers to reflect t he
// fact that they are automatically dereferenced, and are not involved with the // fact that they are automatically dereferenced, and are not involved with the
skipping to change at line 47 skipping to change at line 48
template<typename From> struct simplify_type<const From> { template<typename From> struct simplify_type<const From> {
typedef const From SimpleType; typedef const From SimpleType;
static SimpleType &getSimplifiedValue(const From &Val) { static SimpleType &getSimplifiedValue(const From &Val) {
return simplify_type<From>::getSimplifiedValue(static_cast<From&>(Val)) ; return simplify_type<From>::getSimplifiedValue(static_cast<From&>(Val)) ;
} }
}; };
// The core of the implementation of isa<X> is here; To and From should be // The core of the implementation of isa<X> is here; To and From should be
// the names of classes. This template can be specialized to customize the // the names of classes. This template can be specialized to customize the
// implementation of isa<> without rewriting it from scratch. // implementation of isa<> without rewriting it from scratch.
template <typename To, typename From> template <typename To, typename From, typename Enabler = void>
struct isa_impl { struct isa_impl {
static inline bool doit(const From &Val) { static inline bool doit(const From &Val) {
return To::classof(&Val); return To::classof(&Val);
} }
}; };
/// \brief Always allow upcasts, and perform no dynamic check for them.
template <typename To, typename From>
struct isa_impl<To, From,
typename llvm::enable_if_c<
llvm::is_base_of<To, From>::value
>::type
> {
static inline bool doit(const From &) { return true; }
};
template <typename To, typename From> struct isa_impl_cl { template <typename To, typename From> struct isa_impl_cl {
static inline bool doit(const From &Val) { static inline bool doit(const From &Val) {
return isa_impl<To, From>::doit(Val); return isa_impl<To, From>::doit(Val);
} }
}; };
template <typename To, typename From> struct isa_impl_cl<To, const From> { template <typename To, typename From> struct isa_impl_cl<To, const From> {
static inline bool doit(const From &Val) { static inline bool doit(const From &Val) {
return isa_impl<To, From>::doit(Val); return isa_impl<To, From>::doit(Val);
} }
}; };
template <typename To, typename From> struct isa_impl_cl<To, From*> { template <typename To, typename From> struct isa_impl_cl<To, From*> {
static inline bool doit(const From *Val) { static inline bool doit(const From *Val) {
assert(Val && "isa<> used on a null pointer");
return isa_impl<To, From>::doit(*Val); return isa_impl<To, From>::doit(*Val);
} }
}; };
template <typename To, typename From> struct isa_impl_cl<To, const From*> { template <typename To, typename From> struct isa_impl_cl<To, const From*> {
static inline bool doit(const From *Val) { static inline bool doit(const From *Val) {
assert(Val && "isa<> used on a null pointer");
return isa_impl<To, From>::doit(*Val); return isa_impl<To, From>::doit(*Val);
} }
}; };
template <typename To, typename From> struct isa_impl_cl<To, const From*con st> { template <typename To, typename From> struct isa_impl_cl<To, const From*con st> {
static inline bool doit(const From *Val) { static inline bool doit(const From *Val) {
assert(Val && "isa<> used on a null pointer");
return isa_impl<To, From>::doit(*Val); return isa_impl<To, From>::doit(*Val);
} }
}; };
template<typename To, typename From, typename SimpleFrom> template<typename To, typename From, typename SimpleFrom>
struct isa_impl_wrap { struct isa_impl_wrap {
// When From != SimplifiedType, we can simplify the type some more by usi ng // When From != SimplifiedType, we can simplify the type some more by usi ng
// the simplify_type template. // the simplify_type template.
static bool doit(const From &Val) { static bool doit(const From &Val) {
return isa_impl_wrap<To, SimpleFrom, return isa_impl_wrap<To, SimpleFrom,
 End of changes. 6 change blocks. 
1 lines changed or deleted 15 lines changed or added


 Cloning.h   Cloning.h 
skipping to change at line 42 skipping to change at line 42
class Pass; class Pass;
class LPPassManager; class LPPassManager;
class BasicBlock; class BasicBlock;
class Value; class Value;
class CallInst; class CallInst;
class InvokeInst; class InvokeInst;
class ReturnInst; class ReturnInst;
class CallSite; class CallSite;
class Trace; class Trace;
class CallGraph; class CallGraph;
class TargetData; class DataLayout;
class Loop; class Loop;
class LoopInfo; class LoopInfo;
class AllocaInst; class AllocaInst;
/// CloneModule - Return an exact copy of the specified module /// CloneModule - Return an exact copy of the specified module
/// ///
Module *CloneModule(const Module *M); Module *CloneModule(const Module *M);
Module *CloneModule(const Module *M, ValueToValueMapTy &VMap); Module *CloneModule(const Module *M, ValueToValueMapTy &VMap);
/// ClonedCodeInfo - This struct can be used to capture information about c ode /// ClonedCodeInfo - This struct can be used to capture information about c ode
skipping to change at line 118 skipping to change at line 118
/// information about the cloned code if non-null. /// information about the cloned code if non-null.
/// ///
/// If ModuleLevelChanges is false, VMap contains no non-identity GlobalVal ue /// If ModuleLevelChanges is false, VMap contains no non-identity GlobalVal ue
/// mappings. /// mappings.
/// ///
Function *CloneFunction(const Function *F, Function *CloneFunction(const Function *F,
ValueToValueMapTy &VMap, ValueToValueMapTy &VMap,
bool ModuleLevelChanges, bool ModuleLevelChanges,
ClonedCodeInfo *CodeInfo = 0); ClonedCodeInfo *CodeInfo = 0);
/// CloneFunction - Version of the function that doesn't need the VMap.
///
inline Function *CloneFunction(const Function *F, ClonedCodeInfo *CodeInfo
= 0){
ValueToValueMapTy VMap;
return CloneFunction(F, VMap, CodeInfo);
}
/// Clone OldFunc into NewFunc, transforming the old arguments into referen ces /// Clone OldFunc into NewFunc, transforming the old arguments into referen ces
/// to VMap values. Note that if NewFunc already has basic blocks, the one s /// to VMap values. Note that if NewFunc already has basic blocks, the one s
/// cloned into it will be added to the end of the function. This function /// cloned into it will be added to the end of the function. This function
/// fills in a list of return instructions, and can optionally remap types /// fills in a list of return instructions, and can optionally remap types
/// and/or append the specified suffix to all values cloned. /// and/or append the specified suffix to all values cloned.
/// ///
/// If ModuleLevelChanges is false, VMap contains no non-identity GlobalVal ue /// If ModuleLevelChanges is false, VMap contains no non-identity GlobalVal ue
/// mappings. /// mappings.
/// ///
void CloneFunctionInto(Function *NewFunc, const Function *OldFunc, void CloneFunctionInto(Function *NewFunc, const Function *OldFunc,
skipping to change at line 159 skipping to change at line 152
/// ///
/// If ModuleLevelChanges is false, VMap contains no non-identity GlobalVal ue /// If ModuleLevelChanges is false, VMap contains no non-identity GlobalVal ue
/// mappings. /// mappings.
/// ///
void CloneAndPruneFunctionInto(Function *NewFunc, const Function *OldFunc, void CloneAndPruneFunctionInto(Function *NewFunc, const Function *OldFunc,
ValueToValueMapTy &VMap, ValueToValueMapTy &VMap,
bool ModuleLevelChanges, bool ModuleLevelChanges,
SmallVectorImpl<ReturnInst*> &Returns, SmallVectorImpl<ReturnInst*> &Returns,
const char *NameSuffix = "", const char *NameSuffix = "",
ClonedCodeInfo *CodeInfo = 0, ClonedCodeInfo *CodeInfo = 0,
const TargetData *TD = 0, const DataLayout *TD = 0,
Instruction *TheCall = 0); Instruction *TheCall = 0);
/// InlineFunctionInfo - This class captures the data input to the /// InlineFunctionInfo - This class captures the data input to the
/// InlineFunction call, and records the auxiliary results produced by it. /// InlineFunction call, and records the auxiliary results produced by it.
class InlineFunctionInfo { class InlineFunctionInfo {
public: public:
explicit InlineFunctionInfo(CallGraph *cg = 0, const TargetData *td = 0) explicit InlineFunctionInfo(CallGraph *cg = 0, const DataLayout *td = 0)
: CG(cg), TD(td) {} : CG(cg), TD(td) {}
/// CG - If non-null, InlineFunction will update the callgraph to reflect the /// CG - If non-null, InlineFunction will update the callgraph to reflect the
/// changes it makes. /// changes it makes.
CallGraph *CG; CallGraph *CG;
const TargetData *TD; const DataLayout *TD;
/// StaticAllocas - InlineFunction fills this in with all static allocas that /// StaticAllocas - InlineFunction fills this in with all static allocas that
/// get copied into the caller. /// get copied into the caller.
SmallVector<AllocaInst*, 4> StaticAllocas; SmallVector<AllocaInst*, 4> StaticAllocas;
/// InlinedCalls - InlineFunction fills this in with callsites that were /// InlinedCalls - InlineFunction fills this in with callsites that were
/// inlined from the callee. This is only filled in if CG is non-null. /// inlined from the callee. This is only filled in if CG is non-null.
SmallVector<WeakVH, 8> InlinedCalls; SmallVector<WeakVH, 8> InlinedCalls;
void reset() { void reset() {
 End of changes. 5 change blocks. 
12 lines changed or deleted 4 lines changed or added


 CodeMetrics.h   CodeMetrics.h 
skipping to change at line 19 skipping to change at line 19
// //
// This file implements various weight measurements for code, helping // This file implements various weight measurements for code, helping
// the Inliner and other passes decide whether to duplicate its contents. // the Inliner and other passes decide whether to duplicate its contents.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_ANALYSIS_CODEMETRICS_H #ifndef LLVM_ANALYSIS_CODEMETRICS_H
#define LLVM_ANALYSIS_CODEMETRICS_H #define LLVM_ANALYSIS_CODEMETRICS_H
#include "llvm/ADT/DenseMap.h" #include "llvm/ADT/DenseMap.h"
#include "llvm/Support/CallSite.h"
namespace llvm { namespace llvm {
class BasicBlock; class BasicBlock;
class Function; class Function;
class Instruction; class Instruction;
class TargetData; class DataLayout;
class Value; class Value;
/// \brief Check whether an instruction is likely to be "free" when lower ed. /// \brief Check whether an instruction is likely to be "free" when lower ed.
bool isInstructionFree(const Instruction *I, const TargetData *TD = 0); bool isInstructionFree(const Instruction *I, const DataLayout *TD = 0);
/// \brief Check whether a call will lower to something small. /// \brief Check whether a call will lower to something small.
/// ///
/// This tests checks whether calls to this function will lower to someth ing /// This tests checks whether this callsite will lower to something
/// significantly cheaper than a traditional call, often a single /// significantly cheaper than a traditional call, often a single
/// instruction. /// instruction. Note that if isInstructionFree(CS.getInstruction()) woul
bool callIsSmall(const Function *F); d
/// return true, so will this function.
bool callIsSmall(ImmutableCallSite CS);
/// \brief Utility to calculate the size and a few similar metrics for a set /// \brief Utility to calculate the size and a few similar metrics for a set
/// of basic blocks. /// of basic blocks.
struct CodeMetrics { struct CodeMetrics {
/// \brief True if this function contains a call to setjmp or other fun ctions /// \brief True if this function contains a call to setjmp or other fun ctions
/// with attribute "returns twice" without having the attribute itself. /// with attribute "returns twice" without having the attribute itself.
bool exposesReturnsTwice; bool exposesReturnsTwice;
/// \brief True if this function calls itself. /// \brief True if this function calls itself.
bool isRecursive; bool isRecursive;
skipping to change at line 86 skipping to change at line 88
/// \brief How many 'ret' instructions the blocks contain. /// \brief How many 'ret' instructions the blocks contain.
unsigned NumRets; unsigned NumRets;
CodeMetrics() : exposesReturnsTwice(false), isRecursive(false), CodeMetrics() : exposesReturnsTwice(false), isRecursive(false),
containsIndirectBr(false), usesDynamicAlloca(false), containsIndirectBr(false), usesDynamicAlloca(false),
NumInsts(0), NumBlocks(0), NumCalls(0), NumInsts(0), NumBlocks(0), NumCalls(0),
NumInlineCandidates(0), NumVectorInsts(0), NumInlineCandidates(0), NumVectorInsts(0),
NumRets(0) {} NumRets(0) {}
/// \brief Add information about a block to the current state. /// \brief Add information about a block to the current state.
void analyzeBasicBlock(const BasicBlock *BB, const TargetData *TD = 0); void analyzeBasicBlock(const BasicBlock *BB, const DataLayout *TD = 0);
/// \brief Add information about a function to the current state. /// \brief Add information about a function to the current state.
void analyzeFunction(Function *F, const TargetData *TD = 0); void analyzeFunction(Function *F, const DataLayout *TD = 0);
}; };
} }
#endif #endif
 End of changes. 7 change blocks. 
7 lines changed or deleted 10 lines changed or added


 CommandLine.h   CommandLine.h 
skipping to change at line 44 skipping to change at line 44
/// cl Namespace - This namespace contains all of the command line option /// cl Namespace - This namespace contains all of the command line option
/// processing machinery. It is intentionally a short name to make qualifi ed /// processing machinery. It is intentionally a short name to make qualifi ed
/// usage concise. /// usage concise.
namespace cl { namespace cl {
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// ParseCommandLineOptions - Command line option processing entry point. // ParseCommandLineOptions - Command line option processing entry point.
// //
void ParseCommandLineOptions(int argc, const char * const *argv, void ParseCommandLineOptions(int argc, const char * const *argv,
const char *Overview = 0, const char *Overview = 0);
bool ReadResponseFiles = false);
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// ParseEnvironmentOptions - Environment variable option processing alterna te // ParseEnvironmentOptions - Environment variable option processing alterna te
// entry point. // entry point.
// //
void ParseEnvironmentOptions(const char *progName, const char *envvar, void ParseEnvironmentOptions(const char *progName, const char *envvar,
const char *Overview = 0, const char *Overview = 0);
bool ReadResponseFiles = false);
///===--------------------------------------------------------------------- ===// ///===--------------------------------------------------------------------- ===//
/// SetVersionPrinter - Override the default (LLVM specific) version printe r /// SetVersionPrinter - Override the default (LLVM specific) version printe r
/// used to print out the version when --version is giv en /// used to print out the version when --version is giv en
/// on the command line. This allows other systems usin g the /// on the command line. This allows other systems usin g the
/// CommandLine utilities to print their own version st ring. /// CommandLine utilities to print their own version st ring.
void SetVersionPrinter(void (*func)()); void SetVersionPrinter(void (*func)());
///===--------------------------------------------------------------------- ===// ///===--------------------------------------------------------------------- ===//
/// AddExtraVersionPrinter - Add an extra printer to use in addition to the /// AddExtraVersionPrinter - Add an extra printer to use in addition to the
skipping to change at line 217 skipping to change at line 215
void setValueStr(const char *S) { ValueStr = S; } void setValueStr(const char *S) { ValueStr = S; }
void setNumOccurrencesFlag(enum NumOccurrencesFlag Val) { void setNumOccurrencesFlag(enum NumOccurrencesFlag Val) {
Occurrences = Val; Occurrences = Val;
} }
void setValueExpectedFlag(enum ValueExpected Val) { Value = Val; } void setValueExpectedFlag(enum ValueExpected Val) { Value = Val; }
void setHiddenFlag(enum OptionHidden Val) { HiddenFlag = Val; } void setHiddenFlag(enum OptionHidden Val) { HiddenFlag = Val; }
void setFormattingFlag(enum FormattingFlags V) { Formatting = V; } void setFormattingFlag(enum FormattingFlags V) { Formatting = V; }
void setMiscFlag(enum MiscFlags M) { Misc |= M; } void setMiscFlag(enum MiscFlags M) { Misc |= M; }
void setPosition(unsigned pos) { Position = pos; } void setPosition(unsigned pos) { Position = pos; }
protected: protected:
explicit Option(enum NumOccurrencesFlag Occurrences, explicit Option(enum NumOccurrencesFlag OccurrencesFlag,
enum OptionHidden Hidden) enum OptionHidden Hidden)
: NumOccurrences(0), Occurrences(Occurrences), HiddenFlag(Hidden), : NumOccurrences(0), Occurrences(OccurrencesFlag), Value(0),
Formatting(NormalFormatting), Position(0), HiddenFlag(Hidden), Formatting(NormalFormatting), Misc(0),
AdditionalVals(0), NextRegistered(0), Position(0), AdditionalVals(0), NextRegistered(0),
ArgStr(""), HelpStr(""), ValueStr("") { ArgStr(""), HelpStr(""), ValueStr("") {
} }
inline void setNumAdditionalVals(unsigned n) { AdditionalVals = n; } inline void setNumAdditionalVals(unsigned n) { AdditionalVals = n; }
public: public:
// addArgument - Register this argument with the commandline system. // addArgument - Register this argument with the commandline system.
// //
void addArgument(); void addArgument();
Option *getNextRegisteredOption() const { return NextRegistered; } Option *getNextRegisteredOption() const { return NextRegistered; }
skipping to change at line 1498 skipping to change at line 1496
} }
virtual void getExtraOptionNames(SmallVectorImpl<const char*> &OptionName s) { virtual void getExtraOptionNames(SmallVectorImpl<const char*> &OptionName s) {
return Parser.getExtraOptionNames(OptionNames); return Parser.getExtraOptionNames(OptionNames);
} }
virtual bool handleOccurrence(unsigned pos, StringRef ArgName, StringRef Arg){ virtual bool handleOccurrence(unsigned pos, StringRef ArgName, StringRef Arg){
typename ParserClass::parser_data_type Val = typename ParserClass::parser_data_type Val =
typename ParserClass::parser_data_type(); typename ParserClass::parser_data_type();
if (Parser.parse(*this, ArgName, Arg, Val)) if (Parser.parse(*this, ArgName, Arg, Val))
return true; // Parse Error! return true; // Parse Error!
addValue(Val); this->addValue(Val);
setPosition(pos); setPosition(pos);
Positions.push_back(pos); Positions.push_back(pos);
return false; return false;
} }
// Forward printing stuff to the parser... // Forward printing stuff to the parser...
virtual size_t getOptionWidth() const {return Parser.getOptionWidth(*this );} virtual size_t getOptionWidth() const {return Parser.getOptionWidth(*this );}
virtual void printOptionInfo(size_t GlobalWidth) const { virtual void printOptionInfo(size_t GlobalWidth) const {
Parser.printOptionInfo(*this, GlobalWidth); Parser.printOptionInfo(*this, GlobalWidth);
} }
skipping to change at line 1597 skipping to change at line 1595
} }
}; };
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// Aliased command line option (alias this name to a preexisting name) // Aliased command line option (alias this name to a preexisting name)
// //
class alias : public Option { class alias : public Option {
Option *AliasFor; Option *AliasFor;
virtual bool handleOccurrence(unsigned pos, StringRef /*ArgName*/, virtual bool handleOccurrence(unsigned pos, StringRef /*ArgName*/,
StringRef Arg) { StringRef Arg) LLVM_OVERRIDE {
return AliasFor->handleOccurrence(pos, AliasFor->ArgStr, Arg); return AliasFor->handleOccurrence(pos, AliasFor->ArgStr, Arg);
} }
// Handle printing stuff... // Handle printing stuff...
virtual size_t getOptionWidth() const; virtual size_t getOptionWidth() const LLVM_OVERRIDE;
virtual void printOptionInfo(size_t GlobalWidth) const; virtual void printOptionInfo(size_t GlobalWidth) const LLVM_OVERRIDE;
// Aliases do not need to print their values. // Aliases do not need to print their values.
virtual void printOptionValue(size_t /*GlobalWidth*/, bool /*Force*/) con virtual void printOptionValue(size_t /*GlobalWidth*/,
st {} bool /*Force*/) const LLVM_OVERRIDE {}
void done() { void done() {
if (!hasArgStr()) if (!hasArgStr())
error("cl::alias must have argument name specified!"); error("cl::alias must have argument name specified!");
if (AliasFor == 0) if (AliasFor == 0)
error("cl::alias must have an cl::aliasopt(option) specified!"); error("cl::alias must have an cl::aliasopt(option) specified!");
addArgument(); addArgument();
} }
public: public:
void setAliasFor(Option &O) { void setAliasFor(Option &O) {
 End of changes. 8 change blocks. 
14 lines changed or deleted 12 lines changed or added


 Compiler.h   Compiler.h 
skipping to change at line 22 skipping to change at line 22
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_SUPPORT_COMPILER_H #ifndef LLVM_SUPPORT_COMPILER_H
#define LLVM_SUPPORT_COMPILER_H #define LLVM_SUPPORT_COMPILER_H
#ifndef __has_feature #ifndef __has_feature
# define __has_feature(x) 0 # define __has_feature(x) 0
#endif #endif
/// LLVM_HAS_RVALUE_REFERENCES - Does the compiler provide r-value referenc
es?
/// This implies that <utility> provides the one-argument std::move; it
/// does not imply the existence of any other C++ library features.
#if (__has_feature(cxx_rvalue_references) \
|| defined(__GXX_EXPERIMENTAL_CXX0X__) \
|| (defined(_MSC_VER) && _MSC_VER >= 1600))
#define LLVM_USE_RVALUE_REFERENCES 1
#else
#define LLVM_USE_RVALUE_REFERENCES 0
#endif
/// llvm_move - Expands to ::std::move if the compiler supports
/// r-value references; otherwise, expands to the argument.
#if LLVM_USE_RVALUE_REFERENCES
#define llvm_move(value) (::std::move(value))
#else
#define llvm_move(value) (value)
#endif
/// LLVM_DELETED_FUNCTION - Expands to = delete if the compiler supports it
.
/// Use to mark functions as uncallable. Member functions with this should
/// be declared private so that some behavior is kept in C++03 mode.
///
/// class DontCopy {
/// private:
/// DontCopy(const DontCopy&) LLVM_DELETED_FUNCTION;
/// DontCopy &operator =(const DontCopy&) LLVM_DELETED_FUNCTION;
/// public:
/// ...
/// };
#if (__has_feature(cxx_deleted_functions) \
|| defined(__GXX_EXPERIMENTAL_CXX0X__))
// No version of MSVC currently supports this.
#define LLVM_DELETED_FUNCTION = delete
#else
#define LLVM_DELETED_FUNCTION
#endif
/// LLVM_FINAL - Expands to 'final' if the compiler supports it.
/// Use to mark classes or virtual methods as final.
#if (__has_feature(cxx_override_control))
#define LLVM_FINAL final
#else
#define LLVM_FINAL
#endif
/// LLVM_OVERRIDE - Expands to 'override' if the compiler supports it.
/// Use to mark virtual methods as overriding a base class method.
#if (__has_feature(cxx_override_control))
#define LLVM_OVERRIDE override
#else
#define LLVM_OVERRIDE
#endif
/// LLVM_LIBRARY_VISIBILITY - If a class marked with this attribute is link ed /// LLVM_LIBRARY_VISIBILITY - If a class marked with this attribute is link ed
/// into a shared library, then the class should be private to the library and /// into a shared library, then the class should be private to the library and
/// not accessible from outside it. Can also be used to mark variables and /// not accessible from outside it. Can also be used to mark variables and
/// functions, making them private to any shared library they are linked in to. /// functions, making them private to any shared library they are linked in to.
#if (__GNUC__ >= 4) && !defined(__MINGW32__) && !defined(__CYGWIN__) #if (__GNUC__ >= 4) && !defined(__MINGW32__) && !defined(__CYGWIN__)
#define LLVM_LIBRARY_VISIBILITY __attribute__ ((visibility("hidden"))) #define LLVM_LIBRARY_VISIBILITY __attribute__ ((visibility("hidden")))
#else #else
#define LLVM_LIBRARY_VISIBILITY #define LLVM_LIBRARY_VISIBILITY
#endif #endif
skipping to change at line 71 skipping to change at line 125
#define LLVM_READNONE #define LLVM_READNONE
#endif #endif
#ifdef __GNUC__ // aka 'PURE' but following LLVM Conventions. #ifdef __GNUC__ // aka 'PURE' but following LLVM Conventions.
#define LLVM_READONLY __attribute__((__pure__)) #define LLVM_READONLY __attribute__((__pure__))
#else #else
#define LLVM_READONLY #define LLVM_READONLY
#endif #endif
#if (__GNUC__ >= 4) #if (__GNUC__ >= 4)
#define BUILTIN_EXPECT(EXPR, VALUE) __builtin_expect((EXPR), (VALUE)) #define LLVM_LIKELY(EXPR) __builtin_expect((bool)(EXPR), true)
#define LLVM_UNLIKELY(EXPR) __builtin_expect((bool)(EXPR), false)
#else #else
#define BUILTIN_EXPECT(EXPR, VALUE) (EXPR) #define LLVM_LIKELY(EXPR) (EXPR)
#define LLVM_UNLIKELY(EXPR) (EXPR)
#endif #endif
// C++ doesn't support 'extern template' of template specializations. GCC does, // C++ doesn't support 'extern template' of template specializations. GCC does,
// but requires __extension__ before it. In the header, use this: // but requires __extension__ before it. In the header, use this:
// EXTERN_TEMPLATE_INSTANTIATION(class foo<bar>); // EXTERN_TEMPLATE_INSTANTIATION(class foo<bar>);
// in the .cpp file, use this: // in the .cpp file, use this:
// TEMPLATE_INSTANTIATION(class foo<bar>); // TEMPLATE_INSTANTIATION(class foo<bar>);
#ifdef __GNUC__ #ifdef __GNUC__
#define EXTERN_TEMPLATE_INSTANTIATION(X) __extension__ extern template X #define EXTERN_TEMPLATE_INSTANTIATION(X) __extension__ extern template X
#define TEMPLATE_INSTANTIATION(X) template X #define TEMPLATE_INSTANTIATION(X) template X
skipping to change at line 104 skipping to change at line 160
#define LLVM_ATTRIBUTE_NOINLINE __declspec(noinline) #define LLVM_ATTRIBUTE_NOINLINE __declspec(noinline)
#else #else
#define LLVM_ATTRIBUTE_NOINLINE #define LLVM_ATTRIBUTE_NOINLINE
#endif #endif
// LLVM_ATTRIBUTE_ALWAYS_INLINE - On compilers where we have a directive to do // LLVM_ATTRIBUTE_ALWAYS_INLINE - On compilers where we have a directive to do
// so, mark a method "always inline" because it is performance sensitive. G CC // so, mark a method "always inline" because it is performance sensitive. G CC
// 3.4 supported this but is buggy in various cases and produces unimplemen ted // 3.4 supported this but is buggy in various cases and produces unimplemen ted
// errors, just use it in GCC 4.0 and later. // errors, just use it in GCC 4.0 and later.
#if __GNUC__ > 3 #if __GNUC__ > 3
#define LLVM_ATTRIBUTE_ALWAYS_INLINE __attribute__((always_inline)) #define LLVM_ATTRIBUTE_ALWAYS_INLINE inline __attribute__((always_inline))
#elif defined(_MSC_VER) #elif defined(_MSC_VER)
#define LLVM_ATTRIBUTE_ALWAYS_INLINE __forceinline #define LLVM_ATTRIBUTE_ALWAYS_INLINE __forceinline
#else #else
#define LLVM_ATTRIBUTE_ALWAYS_INLINE #define LLVM_ATTRIBUTE_ALWAYS_INLINE
#endif #endif
#ifdef __GNUC__ #ifdef __GNUC__
#define LLVM_ATTRIBUTE_NORETURN __attribute__((noreturn)) #define LLVM_ATTRIBUTE_NORETURN __attribute__((noreturn))
#elif defined(_MSC_VER) #elif defined(_MSC_VER)
#define LLVM_ATTRIBUTE_NORETURN __declspec(noreturn) #define LLVM_ATTRIBUTE_NORETURN __declspec(noreturn)
skipping to change at line 150 skipping to change at line 206
#endif #endif
// LLVM_BUILTIN_UNREACHABLE - On compilers which support it, expands // LLVM_BUILTIN_UNREACHABLE - On compilers which support it, expands
// to an expression which states that it is undefined behavior for the // to an expression which states that it is undefined behavior for the
// compiler to reach this point. Otherwise is not defined. // compiler to reach this point. Otherwise is not defined.
#if defined(__clang__) || (__GNUC__ > 4) \ #if defined(__clang__) || (__GNUC__ > 4) \
|| (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
# define LLVM_BUILTIN_UNREACHABLE __builtin_unreachable() # define LLVM_BUILTIN_UNREACHABLE __builtin_unreachable()
#endif #endif
// LLVM_BUILTIN_TRAP - On compilers which support it, expands to an express
ion
// which causes the program to exit abnormally.
#if defined(__clang__) || (__GNUC__ > 4) \
|| (__GNUC__ == 4 && __GNUC_MINOR__ >= 3)
# define LLVM_BUILTIN_TRAP __builtin_trap()
#else
# define LLVM_BUILTIN_TRAP *(volatile int*)0x11 = 0
#endif
#endif #endif
 End of changes. 5 change blocks. 
3 lines changed or deleted 71 lines changed or added


 Constant.h   Constant.h 
skipping to change at line 42 skipping to change at line 42
/// or expression based (computations yielding a constant value composed of /// or expression based (computations yielding a constant value composed of
/// only certain operators and other constant values). /// only certain operators and other constant values).
/// ///
/// Note that Constants are immutable (once created they never change) /// Note that Constants are immutable (once created they never change)
/// and are fully shared by structural equivalence. This means that two /// and are fully shared by structural equivalence. This means that two
/// structurally equivalent constants will always have the same address. /// structurally equivalent constants will always have the same address.
/// Constants are created on demand as needed and never deleted: thus clien ts /// Constants are created on demand as needed and never deleted: thus clien ts
/// don't have to worry about the lifetime of the objects. /// don't have to worry about the lifetime of the objects.
/// @brief LLVM Constant Representation /// @brief LLVM Constant Representation
class Constant : public User { class Constant : public User {
void operator=(const Constant &); // Do not implement void operator=(const Constant &) LLVM_DELETED_FUNCTION;
Constant(const Constant &); // Do not implement Constant(const Constant &) LLVM_DELETED_FUNCTION;
virtual void anchor(); virtual void anchor();
protected: protected:
Constant(Type *ty, ValueTy vty, Use *Ops, unsigned NumOps) Constant(Type *ty, ValueTy vty, Use *Ops, unsigned NumOps)
: User(ty, vty, Ops, NumOps) {} : User(ty, vty, Ops, NumOps) {}
void destroyConstantImpl(); void destroyConstantImpl();
public: public:
/// isNullValue - Return true if this is the value that would be returned by /// isNullValue - Return true if this is the value that would be returned by
/// getNullValue. /// getNullValue.
skipping to change at line 68 skipping to change at line 68
bool isAllOnesValue() const; bool isAllOnesValue() const;
/// isNegativeZeroValue - Return true if the value is what would be retur ned /// isNegativeZeroValue - Return true if the value is what would be retur ned
/// by getZeroValueForNegation. /// by getZeroValueForNegation.
bool isNegativeZeroValue() const; bool isNegativeZeroValue() const;
/// canTrap - Return true if evaluation of this constant could trap. Thi s is /// canTrap - Return true if evaluation of this constant could trap. Thi s is
/// true for things like constant expressions that could divide by zero. /// true for things like constant expressions that could divide by zero.
bool canTrap() const; bool canTrap() const;
/// isThreadDependent - Return true if the value can vary between threads
.
bool isThreadDependent() const;
/// isConstantUsed - Return true if the constant has users other than con stant /// isConstantUsed - Return true if the constant has users other than con stant
/// exprs and other dangling things. /// exprs and other dangling things.
bool isConstantUsed() const; bool isConstantUsed() const;
enum PossibleRelocationsTy { enum PossibleRelocationsTy {
NoRelocation = 0, NoRelocation = 0,
LocalRelocation = 1, LocalRelocation = 1,
GlobalRelocations = 2 GlobalRelocations = 2
}; };
skipping to change at line 111 skipping to change at line 114
/// destroyConstant - Called if some element of this constant is no longe r /// destroyConstant - Called if some element of this constant is no longe r
/// valid. At this point only other constants may be on the use_list for this /// valid. At this point only other constants may be on the use_list for this
/// constant. Any constants on our Use list must also be destroy'd. The /// constant. Any constants on our Use list must also be destroy'd. The
/// implementation must be sure to remove the constant from the list of /// implementation must be sure to remove the constant from the list of
/// available cached constants. Implementations should call /// available cached constants. Implementations should call
/// destroyConstantImpl as the last thing they do, to destroy all users a nd /// destroyConstantImpl as the last thing they do, to destroy all users a nd
/// delete this. /// delete this.
virtual void destroyConstant() { llvm_unreachable("Not reached!"); } virtual void destroyConstant() { llvm_unreachable("Not reached!"); }
//// Methods for support type inquiry through isa, cast, and dyn_cast: //// Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const Constant *) { return true; }
static inline bool classof(const GlobalValue *) { return true; }
static inline bool classof(const Value *V) { static inline bool classof(const Value *V) {
return V->getValueID() >= ConstantFirstVal && return V->getValueID() >= ConstantFirstVal &&
V->getValueID() <= ConstantLastVal; V->getValueID() <= ConstantLastVal;
} }
/// replaceUsesOfWithOnConstant - This method is a special form of /// replaceUsesOfWithOnConstant - This method is a special form of
/// User::replaceUsesOfWith (which does not work on constants) that does work /// User::replaceUsesOfWith (which does not work on constants) that does work
/// on constants. Basically this method goes through the trouble of buil ding /// on constants. Basically this method goes through the trouble of buil ding
/// a new constant that is equivalent to the current one, with all uses o f /// a new constant that is equivalent to the current one, with all uses o f
/// From replaced with uses of To. After this construction is completed, all /// From replaced with uses of To. After this construction is completed, all
skipping to change at line 140 skipping to change at line 141
// cannot use any other values. This cannot be called at runtime, but needs // cannot use any other values. This cannot be called at runtime, but needs
// to be here to avoid link errors. // to be here to avoid link errors.
assert(getNumOperands() == 0 && "replaceUsesOfWithOnConstant must be " assert(getNumOperands() == 0 && "replaceUsesOfWithOnConstant must be "
"implemented for all constants that have operands!"); "implemented for all constants that have operands!");
llvm_unreachable("Constants that do not have operands cannot be using " llvm_unreachable("Constants that do not have operands cannot be using "
"'From'!"); "'From'!");
} }
static Constant *getNullValue(Type* Ty); static Constant *getNullValue(Type* Ty);
/// @returns the value for an integer constant of the given type that has /// @returns the value for an integer or vector of integer constant of th
all e
/// its bits set to true. /// given type that has all its bits set to true.
/// @brief Get the all ones value /// @brief Get the all ones value
static Constant *getAllOnesValue(Type* Ty); static Constant *getAllOnesValue(Type* Ty);
/// getIntegerValue - Return the value for an integer or pointer constant , /// getIntegerValue - Return the value for an integer or pointer constant ,
/// or a vector thereof, with the given scalar value. /// or a vector thereof, with the given scalar value.
static Constant *getIntegerValue(Type* Ty, const APInt &V); static Constant *getIntegerValue(Type* Ty, const APInt &V);
/// removeDeadConstantUsers - If there are any dead constant users dangli ng /// removeDeadConstantUsers - If there are any dead constant users dangli ng
/// off of this constant, remove them. This method is useful for clients /// off of this constant, remove them. This method is useful for clients
/// that want to check to see if a global is unused, but don't want to de al /// that want to check to see if a global is unused, but don't want to de al
 End of changes. 4 change blocks. 
7 lines changed or deleted 9 lines changed or added


 ConstantFolding.h   ConstantFolding.h 
skipping to change at line 15 skipping to change at line 15
// This file is distributed under the University of Illinois Open Source // This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details. // License. See LICENSE.TXT for details.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// //
// This file declares routines for folding instructions into constants when all // This file declares routines for folding instructions into constants when all
// operands are constants, for example "sub i32 1, 0" -> "1". // operands are constants, for example "sub i32 1, 0" -> "1".
// //
// Also, to supplement the basic VMCore ConstantExpr simplifications, // Also, to supplement the basic VMCore ConstantExpr simplifications,
// this file declares some additional folding routines that can make use of // this file declares some additional folding routines that can make use of
// TargetData information. These functions cannot go in VMCore due to libra ry // DataLayout information. These functions cannot go in VMCore due to libra ry
// dependency issues. // dependency issues.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_ANALYSIS_CONSTANTFOLDING_H #ifndef LLVM_ANALYSIS_CONSTANTFOLDING_H
#define LLVM_ANALYSIS_CONSTANTFOLDING_H #define LLVM_ANALYSIS_CONSTANTFOLDING_H
namespace llvm { namespace llvm {
class Constant; class Constant;
class ConstantExpr; class ConstantExpr;
class Instruction; class Instruction;
class TargetData; class DataLayout;
class TargetLibraryInfo; class TargetLibraryInfo;
class Function; class Function;
class Type; class Type;
template<typename T> template<typename T>
class ArrayRef; class ArrayRef;
/// ConstantFoldInstruction - Try to constant fold the specified instructio n. /// ConstantFoldInstruction - Try to constant fold the specified instructio n.
/// If successful, the constant result is returned, if not, null is returne d. /// If successful, the constant result is returned, if not, null is returne d.
/// Note that this fails if not all of the operands are constant. Otherwis e, /// Note that this fails if not all of the operands are constant. Otherwis e,
/// this function can only fail when attempting to fold instructions like l oads /// this function can only fail when attempting to fold instructions like l oads
/// and stores, which have no constant expression form. /// and stores, which have no constant expression form.
Constant *ConstantFoldInstruction(Instruction *I, const TargetData *TD = 0, Constant *ConstantFoldInstruction(Instruction *I, const DataLayout *TD = 0,
const TargetLibraryInfo *TLI = 0); const TargetLibraryInfo *TLI = 0);
/// ConstantFoldConstantExpression - Attempt to fold the constant expressio n /// ConstantFoldConstantExpression - Attempt to fold the constant expressio n
/// using the specified TargetData. If successful, the constant result is /// using the specified DataLayout. If successful, the constant result is
/// result is returned, if not, null is returned. /// result is returned, if not, null is returned.
Constant *ConstantFoldConstantExpression(const ConstantExpr *CE, Constant *ConstantFoldConstantExpression(const ConstantExpr *CE,
const TargetData *TD = 0, const DataLayout *TD = 0,
const TargetLibraryInfo *TLI = 0); const TargetLibraryInfo *TLI = 0);
/// ConstantFoldInstOperands - Attempt to constant fold an instruction with the /// ConstantFoldInstOperands - Attempt to constant fold an instruction with the
/// specified operands. If successful, the constant result is returned, if not, /// specified operands. If successful, the constant result is returned, if not,
/// null is returned. Note that this function can fail when attempting to /// null is returned. Note that this function can fail when attempting to
/// fold instructions like loads and stores, which have no constant express ion /// fold instructions like loads and stores, which have no constant express ion
/// form. /// form.
/// ///
Constant *ConstantFoldInstOperands(unsigned Opcode, Type *DestTy, Constant *ConstantFoldInstOperands(unsigned Opcode, Type *DestTy,
ArrayRef<Constant *> Ops, ArrayRef<Constant *> Ops,
const TargetData *TD = 0, const DataLayout *TD = 0,
const TargetLibraryInfo *TLI = 0); const TargetLibraryInfo *TLI = 0);
/// ConstantFoldCompareInstOperands - Attempt to constant fold a compare /// ConstantFoldCompareInstOperands - Attempt to constant fold a compare
/// instruction (icmp/fcmp) with the specified operands. If it fails, it /// instruction (icmp/fcmp) with the specified operands. If it fails, it
/// returns a constant expression of the specified operands. /// returns a constant expression of the specified operands.
/// ///
Constant *ConstantFoldCompareInstOperands(unsigned Predicate, Constant *ConstantFoldCompareInstOperands(unsigned Predicate,
Constant *LHS, Constant *RHS, Constant *LHS, Constant *RHS,
const TargetData *TD = 0, const DataLayout *TD = 0,
const TargetLibraryInfo *TLI = 0) ; const TargetLibraryInfo *TLI = 0) ;
/// ConstantFoldInsertValueInstruction - Attempt to constant fold an insert value /// ConstantFoldInsertValueInstruction - Attempt to constant fold an insert value
/// instruction with the specified operands and indices. The constant resu lt is /// instruction with the specified operands and indices. The constant resu lt is
/// returned if successful; if not, null is returned. /// returned if successful; if not, null is returned.
Constant *ConstantFoldInsertValueInstruction(Constant *Agg, Constant *Val, Constant *ConstantFoldInsertValueInstruction(Constant *Agg, Constant *Val,
ArrayRef<unsigned> Idxs); ArrayRef<unsigned> Idxs);
/// ConstantFoldLoadFromConstPtr - Return the value that a load from C woul d /// ConstantFoldLoadFromConstPtr - Return the value that a load from C woul d
/// produce if it is constant and determinable. If this is not determinabl e, /// produce if it is constant and determinable. If this is not determinabl e,
/// return null. /// return null.
Constant *ConstantFoldLoadFromConstPtr(Constant *C, const TargetData *TD = 0); Constant *ConstantFoldLoadFromConstPtr(Constant *C, const DataLayout *TD = 0);
/// ConstantFoldLoadThroughGEPConstantExpr - Given a constant and a /// ConstantFoldLoadThroughGEPConstantExpr - Given a constant and a
/// getelementptr constantexpr, return the constant value being addressed b y the /// getelementptr constantexpr, return the constant value being addressed b y the
/// constant expression, or null if something is funny and we can't decide. /// constant expression, or null if something is funny and we can't decide.
Constant *ConstantFoldLoadThroughGEPConstantExpr(Constant *C, ConstantExpr *CE); Constant *ConstantFoldLoadThroughGEPConstantExpr(Constant *C, ConstantExpr *CE);
/// ConstantFoldLoadThroughGEPIndices - Given a constant and getelementptr /// ConstantFoldLoadThroughGEPIndices - Given a constant and getelementptr
/// indices (with an *implied* zero pointer index that is not in the list), /// indices (with an *implied* zero pointer index that is not in the list),
/// return the constant value being addressed by a virtual load, or null if /// return the constant value being addressed by a virtual load, or null if
/// something is funny and we can't decide. /// something is funny and we can't decide.
 End of changes. 8 change blocks. 
8 lines changed or deleted 8 lines changed or added


 ConstantRange.h   ConstantRange.h 
skipping to change at line 158 skipping to change at line 158
return Lower == CR.Lower && Upper == CR.Upper; return Lower == CR.Lower && Upper == CR.Upper;
} }
bool operator!=(const ConstantRange &CR) const { bool operator!=(const ConstantRange &CR) const {
return !operator==(CR); return !operator==(CR);
} }
/// subtract - Subtract the specified constant from the endpoints of this /// subtract - Subtract the specified constant from the endpoints of this
/// constant range. /// constant range.
ConstantRange subtract(const APInt &CI) const; ConstantRange subtract(const APInt &CI) const;
/// \brief Subtract the specified range from this range (aka relative
/// complement of the sets).
ConstantRange difference(const ConstantRange &CR) const;
/// intersectWith - Return the range that results from the intersection o f /// intersectWith - Return the range that results from the intersection o f
/// this range with another range. The resultant range is guaranteed to /// this range with another range. The resultant range is guaranteed to
/// include all elements contained in both input ranges, and to have the /// include all elements contained in both input ranges, and to have the
/// smallest possible set size that does so. Because there may be two /// smallest possible set size that does so. Because there may be two
/// intersections with the same set size, A.intersectWith(B) might not /// intersections with the same set size, A.intersectWith(B) might not
/// be equal to B.intersectWith(A). /// be equal to B.intersectWith(A).
/// ///
ConstantRange intersectWith(const ConstantRange &CR) const; ConstantRange intersectWith(const ConstantRange &CR) const;
/// unionWith - Return the range that results from the union of this rang e /// unionWith - Return the range that results from the union of this rang e
 End of changes. 1 change blocks. 
0 lines changed or deleted 4 lines changed or added


 Constants.h   Constants.h 
skipping to change at line 52 skipping to change at line 52
struct ConstantArrayCreator; struct ConstantArrayCreator;
template<class ConstantClass, class TypeClass> template<class ConstantClass, class TypeClass>
struct ConvertConstantType; struct ConvertConstantType;
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
/// This is the shared class of boolean and integer constants. This class /// This is the shared class of boolean and integer constants. This class
/// represents both boolean and integral constants. /// represents both boolean and integral constants.
/// @brief Class for constant integers. /// @brief Class for constant integers.
class ConstantInt : public Constant { class ConstantInt : public Constant {
virtual void anchor(); virtual void anchor();
void *operator new(size_t, unsigned); // DO NOT IMPLEMENT void *operator new(size_t, unsigned) LLVM_DELETED_FUNCTION;
ConstantInt(const ConstantInt &); // DO NOT IMPLEMENT ConstantInt(const ConstantInt &) LLVM_DELETED_FUNCTION;
ConstantInt(IntegerType *Ty, const APInt& V); ConstantInt(IntegerType *Ty, const APInt& V);
APInt Val; APInt Val;
protected: protected:
// allocate space for exactly zero operands // allocate space for exactly zero operands
void *operator new(size_t s) { void *operator new(size_t s) {
return User::operator new(s, 0); return User::operator new(s, 0);
} }
public: public:
static ConstantInt *getTrue(LLVMContext &Context); static ConstantInt *getTrue(LLVMContext &Context);
static ConstantInt *getFalse(LLVMContext &Context); static ConstantInt *getFalse(LLVMContext &Context);
skipping to change at line 224 skipping to change at line 224
/// getLimitedValue - If the value is smaller than the specified limit, /// getLimitedValue - If the value is smaller than the specified limit,
/// return it, otherwise return the limit value. This causes the value /// return it, otherwise return the limit value. This causes the value
/// to saturate to the limit. /// to saturate to the limit.
/// @returns the min of the value of the constant and the specified value /// @returns the min of the value of the constant and the specified value
/// @brief Get the constant's value with a saturation limit /// @brief Get the constant's value with a saturation limit
uint64_t getLimitedValue(uint64_t Limit = ~0ULL) const { uint64_t getLimitedValue(uint64_t Limit = ~0ULL) const {
return Val.getLimitedValue(Limit); return Val.getLimitedValue(Limit);
} }
/// @brief Methods to support type inquiry through isa, cast, and dyn_cas t. /// @brief Methods to support type inquiry through isa, cast, and dyn_cas t.
static inline bool classof(const ConstantInt *) { return true; }
static bool classof(const Value *V) { static bool classof(const Value *V) {
return V->getValueID() == ConstantIntVal; return V->getValueID() == ConstantIntVal;
} }
}; };
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
/// ConstantFP - Floating Point Values [float, double] /// ConstantFP - Floating Point Values [float, double]
/// ///
class ConstantFP : public Constant { class ConstantFP : public Constant {
APFloat Val; APFloat Val;
virtual void anchor(); virtual void anchor();
void *operator new(size_t, unsigned);// DO NOT IMPLEMENT void *operator new(size_t, unsigned) LLVM_DELETED_FUNCTION;
ConstantFP(const ConstantFP &); // DO NOT IMPLEMENT ConstantFP(const ConstantFP &) LLVM_DELETED_FUNCTION;
friend class LLVMContextImpl; friend class LLVMContextImpl;
protected: protected:
ConstantFP(Type *Ty, const APFloat& V); ConstantFP(Type *Ty, const APFloat& V);
protected: protected:
// allocate space for exactly zero operands // allocate space for exactly zero operands
void *operator new(size_t s) { void *operator new(size_t s) {
return User::operator new(s, 0); return User::operator new(s, 0);
} }
public: public:
/// Floating point negation must be implemented with f(x) = -0.0 - x. Thi s /// Floating point negation must be implemented with f(x) = -0.0 - x. Thi s
skipping to change at line 285 skipping to change at line 284
/// isExactlyValue - We don't rely on operator== working on double values , as /// isExactlyValue - We don't rely on operator== working on double values , as
/// it returns true for things that are clearly not equal, like -0.0 and 0.0. /// it returns true for things that are clearly not equal, like -0.0 and 0.0.
/// As such, this method can be used to do an exact bit-for-bit compariso n of /// As such, this method can be used to do an exact bit-for-bit compariso n of
/// two floating point values. The version with a double operand is reta ined /// two floating point values. The version with a double operand is reta ined
/// because it's so convenient to write isExactlyValue(2.0), but please u se /// because it's so convenient to write isExactlyValue(2.0), but please u se
/// it only for simple constants. /// it only for simple constants.
bool isExactlyValue(const APFloat &V) const; bool isExactlyValue(const APFloat &V) const;
bool isExactlyValue(double V) const { bool isExactlyValue(double V) const {
bool ignored; bool ignored;
// convert is not supported on this type
if (&Val.getSemantics() == &APFloat::PPCDoubleDouble)
return false;
APFloat FV(V); APFloat FV(V);
FV.convert(Val.getSemantics(), APFloat::rmNearestTiesToEven, &ignored); FV.convert(Val.getSemantics(), APFloat::rmNearestTiesToEven, &ignored);
return isExactlyValue(FV); return isExactlyValue(FV);
} }
/// Methods for support type inquiry through isa, cast, and dyn_cast: /// Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const ConstantFP *) { return true; }
static bool classof(const Value *V) { static bool classof(const Value *V) {
return V->getValueID() == ConstantFPVal; return V->getValueID() == ConstantFPVal;
} }
}; };
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
/// ConstantAggregateZero - All zero aggregate value /// ConstantAggregateZero - All zero aggregate value
/// ///
class ConstantAggregateZero : public Constant { class ConstantAggregateZero : public Constant {
void *operator new(size_t, unsigned); // DO NOT IMPL void *operator new(size_t, unsigned) LLVM_DELETED_FUNCTION;
EMENT ConstantAggregateZero(const ConstantAggregateZero &) LLVM_DELETED_FUNCTIO
ConstantAggregateZero(const ConstantAggregateZero &); // DO NOT IMPL N;
EMENT
protected: protected:
explicit ConstantAggregateZero(Type *ty) explicit ConstantAggregateZero(Type *ty)
: Constant(ty, ConstantAggregateZeroVal, 0, 0) {} : Constant(ty, ConstantAggregateZeroVal, 0, 0) {}
protected: protected:
// allocate space for exactly zero operands // allocate space for exactly zero operands
void *operator new(size_t s) { void *operator new(size_t s) {
return User::operator new(s, 0); return User::operator new(s, 0);
} }
public: public:
static ConstantAggregateZero *get(Type *Ty); static ConstantAggregateZero *get(Type *Ty);
skipping to change at line 336 skipping to change at line 331
/// getElementValue - Return a zero of the right value for the specified GEP /// getElementValue - Return a zero of the right value for the specified GEP
/// index. /// index.
Constant *getElementValue(Constant *C) const; Constant *getElementValue(Constant *C) const;
/// getElementValue - Return a zero of the right value for the specified GEP /// getElementValue - Return a zero of the right value for the specified GEP
/// index. /// index.
Constant *getElementValue(unsigned Idx) const; Constant *getElementValue(unsigned Idx) const;
/// Methods for support type inquiry through isa, cast, and dyn_cast: /// Methods for support type inquiry through isa, cast, and dyn_cast:
/// ///
static bool classof(const ConstantAggregateZero *) { return true; }
static bool classof(const Value *V) { static bool classof(const Value *V) {
return V->getValueID() == ConstantAggregateZeroVal; return V->getValueID() == ConstantAggregateZeroVal;
} }
}; };
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
/// ConstantArray - Constant Array Declarations /// ConstantArray - Constant Array Declarations
/// ///
class ConstantArray : public Constant { class ConstantArray : public Constant {
friend struct ConstantArrayCreator<ConstantArray, ArrayType>; friend struct ConstantArrayCreator<ConstantArray, ArrayType>;
ConstantArray(const ConstantArray &); // DO NOT IMPLEMENT ConstantArray(const ConstantArray &) LLVM_DELETED_FUNCTION;
protected: protected:
ConstantArray(ArrayType *T, ArrayRef<Constant *> Val); ConstantArray(ArrayType *T, ArrayRef<Constant *> Val);
public: public:
// ConstantArray accessors // ConstantArray accessors
static Constant *get(ArrayType *T, ArrayRef<Constant*> V); static Constant *get(ArrayType *T, ArrayRef<Constant*> V);
/// Transparently provide more efficient getOperand methods. /// Transparently provide more efficient getOperand methods.
DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Constant); DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Constant);
/// getType - Specialize the getType() method to always return an ArrayTy pe, /// getType - Specialize the getType() method to always return an ArrayTy pe,
/// which reduces the amount of casting needed in parts of the compiler. /// which reduces the amount of casting needed in parts of the compiler.
/// ///
inline ArrayType *getType() const { inline ArrayType *getType() const {
return reinterpret_cast<ArrayType*>(Value::getType()); return reinterpret_cast<ArrayType*>(Value::getType());
} }
virtual void destroyConstant(); virtual void destroyConstant();
virtual void replaceUsesOfWithOnConstant(Value *From, Value *To, Use *U); virtual void replaceUsesOfWithOnConstant(Value *From, Value *To, Use *U);
/// Methods for support type inquiry through isa, cast, and dyn_cast: /// Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const ConstantArray *) { return true; }
static bool classof(const Value *V) { static bool classof(const Value *V) {
return V->getValueID() == ConstantArrayVal; return V->getValueID() == ConstantArrayVal;
} }
}; };
template <> template <>
struct OperandTraits<ConstantArray> : struct OperandTraits<ConstantArray> :
public VariadicOperandTraits<ConstantArray> { public VariadicOperandTraits<ConstantArray> {
}; };
DEFINE_TRANSPARENT_OPERAND_ACCESSORS(ConstantArray, Constant) DEFINE_TRANSPARENT_OPERAND_ACCESSORS(ConstantArray, Constant)
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// ConstantStruct - Constant Struct Declarations // ConstantStruct - Constant Struct Declarations
// //
class ConstantStruct : public Constant { class ConstantStruct : public Constant {
friend struct ConstantArrayCreator<ConstantStruct, StructType>; friend struct ConstantArrayCreator<ConstantStruct, StructType>;
ConstantStruct(const ConstantStruct &); // DO NOT IMPLEMENT ConstantStruct(const ConstantStruct &) LLVM_DELETED_FUNCTION;
protected: protected:
ConstantStruct(StructType *T, ArrayRef<Constant *> Val); ConstantStruct(StructType *T, ArrayRef<Constant *> Val);
public: public:
// ConstantStruct accessors // ConstantStruct accessors
static Constant *get(StructType *T, ArrayRef<Constant*> V); static Constant *get(StructType *T, ArrayRef<Constant*> V);
static Constant *get(StructType *T, ...) END_WITH_NULL; static Constant *get(StructType *T, ...) END_WITH_NULL;
/// getAnon - Return an anonymous struct that has the specified /// getAnon - Return an anonymous struct that has the specified
/// elements. If the struct is possibly empty, then you must specify a /// elements. If the struct is possibly empty, then you must specify a
/// context. /// context.
skipping to change at line 427 skipping to change at line 420
/// getType() specialization - Reduce amount of casting... /// getType() specialization - Reduce amount of casting...
/// ///
inline StructType *getType() const { inline StructType *getType() const {
return reinterpret_cast<StructType*>(Value::getType()); return reinterpret_cast<StructType*>(Value::getType());
} }
virtual void destroyConstant(); virtual void destroyConstant();
virtual void replaceUsesOfWithOnConstant(Value *From, Value *To, Use *U); virtual void replaceUsesOfWithOnConstant(Value *From, Value *To, Use *U);
/// Methods for support type inquiry through isa, cast, and dyn_cast: /// Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const ConstantStruct *) { return true; }
static bool classof(const Value *V) { static bool classof(const Value *V) {
return V->getValueID() == ConstantStructVal; return V->getValueID() == ConstantStructVal;
} }
}; };
template <> template <>
struct OperandTraits<ConstantStruct> : struct OperandTraits<ConstantStruct> :
public VariadicOperandTraits<ConstantStruct> { public VariadicOperandTraits<ConstantStruct> {
}; };
DEFINE_TRANSPARENT_OPERAND_ACCESSORS(ConstantStruct, Constant) DEFINE_TRANSPARENT_OPERAND_ACCESSORS(ConstantStruct, Constant)
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
/// ConstantVector - Constant Vector Declarations /// ConstantVector - Constant Vector Declarations
/// ///
class ConstantVector : public Constant { class ConstantVector : public Constant {
friend struct ConstantArrayCreator<ConstantVector, VectorType>; friend struct ConstantArrayCreator<ConstantVector, VectorType>;
ConstantVector(const ConstantVector &); // DO NOT IMPLEMENT ConstantVector(const ConstantVector &) LLVM_DELETED_FUNCTION;
protected: protected:
ConstantVector(VectorType *T, ArrayRef<Constant *> Val); ConstantVector(VectorType *T, ArrayRef<Constant *> Val);
public: public:
// ConstantVector accessors // ConstantVector accessors
static Constant *get(ArrayRef<Constant*> V); static Constant *get(ArrayRef<Constant*> V);
/// getSplat - Return a ConstantVector with the specified constant in eac h /// getSplat - Return a ConstantVector with the specified constant in eac h
/// element. /// element.
static Constant *getSplat(unsigned NumElts, Constant *Elt); static Constant *getSplat(unsigned NumElts, Constant *Elt);
skipping to change at line 474 skipping to change at line 466
} }
/// getSplatValue - If this is a splat constant, meaning that all of the /// getSplatValue - If this is a splat constant, meaning that all of the
/// elements have the same value, return that value. Otherwise return NUL L. /// elements have the same value, return that value. Otherwise return NUL L.
Constant *getSplatValue() const; Constant *getSplatValue() const;
virtual void destroyConstant(); virtual void destroyConstant();
virtual void replaceUsesOfWithOnConstant(Value *From, Value *To, Use *U); virtual void replaceUsesOfWithOnConstant(Value *From, Value *To, Use *U);
/// Methods for support type inquiry through isa, cast, and dyn_cast: /// Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const ConstantVector *) { return true; }
static bool classof(const Value *V) { static bool classof(const Value *V) {
return V->getValueID() == ConstantVectorVal; return V->getValueID() == ConstantVectorVal;
} }
}; };
template <> template <>
struct OperandTraits<ConstantVector> : struct OperandTraits<ConstantVector> :
public VariadicOperandTraits<ConstantVector> { public VariadicOperandTraits<ConstantVector> {
}; };
DEFINE_TRANSPARENT_OPERAND_ACCESSORS(ConstantVector, Constant) DEFINE_TRANSPARENT_OPERAND_ACCESSORS(ConstantVector, Constant)
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
/// ConstantPointerNull - a constant pointer value that points to null /// ConstantPointerNull - a constant pointer value that points to null
/// ///
class ConstantPointerNull : public Constant { class ConstantPointerNull : public Constant {
void *operator new(size_t, unsigned); // DO NOT IMPLEMEN void *operator new(size_t, unsigned) LLVM_DELETED_FUNCTION;
T ConstantPointerNull(const ConstantPointerNull &) LLVM_DELETED_FUNCTION;
ConstantPointerNull(const ConstantPointerNull &); // DO NOT IMPLEMEN
T
protected: protected:
explicit ConstantPointerNull(PointerType *T) explicit ConstantPointerNull(PointerType *T)
: Constant(reinterpret_cast<Type*>(T), : Constant(reinterpret_cast<Type*>(T),
Value::ConstantPointerNullVal, 0, 0) {} Value::ConstantPointerNullVal, 0, 0) {}
protected: protected:
// allocate space for exactly zero operands // allocate space for exactly zero operands
void *operator new(size_t s) { void *operator new(size_t s) {
return User::operator new(s, 0); return User::operator new(s, 0);
} }
skipping to change at line 517 skipping to change at line 508
virtual void destroyConstant(); virtual void destroyConstant();
/// getType - Specialize the getType() method to always return an Pointer Type, /// getType - Specialize the getType() method to always return an Pointer Type,
/// which reduces the amount of casting needed in parts of the compiler. /// which reduces the amount of casting needed in parts of the compiler.
/// ///
inline PointerType *getType() const { inline PointerType *getType() const {
return reinterpret_cast<PointerType*>(Value::getType()); return reinterpret_cast<PointerType*>(Value::getType());
} }
/// Methods for support type inquiry through isa, cast, and dyn_cast: /// Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const ConstantPointerNull *) { return true; }
static bool classof(const Value *V) { static bool classof(const Value *V) {
return V->getValueID() == ConstantPointerNullVal; return V->getValueID() == ConstantPointerNullVal;
} }
}; };
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
/// ConstantDataSequential - A vector or array constant whose element type is a /// ConstantDataSequential - A vector or array constant whose element type is a
/// simple 1/2/4/8-byte integer or float/double, and whose elements are jus t /// simple 1/2/4/8-byte integer or float/double, and whose elements are jus t
/// simple data values (i.e. ConstantInt/ConstantFP). This Constant node h as no /// simple data values (i.e. ConstantInt/ConstantFP). This Constant node h as no
/// operands because it stores all of the elements of the constant as dense ly /// operands because it stores all of the elements of the constant as dense ly
skipping to change at line 543 skipping to change at line 533
friend class LLVMContextImpl; friend class LLVMContextImpl;
/// DataElements - A pointer to the bytes underlying this constant (which is /// DataElements - A pointer to the bytes underlying this constant (which is
/// owned by the uniquing StringMap). /// owned by the uniquing StringMap).
const char *DataElements; const char *DataElements;
/// Next - This forms a link list of ConstantDataSequential nodes that ha ve /// Next - This forms a link list of ConstantDataSequential nodes that ha ve
/// the same value but different type. For example, 0,0,0,1 could be a 4 /// the same value but different type. For example, 0,0,0,1 could be a 4
/// element array of i8, or a 1-element array of i32. They'll both end u p in /// element array of i8, or a 1-element array of i32. They'll both end u p in
/// the same StringMap bucket, linked up. /// the same StringMap bucket, linked up.
ConstantDataSequential *Next; ConstantDataSequential *Next;
void *operator new(size_t, unsigned); // DO NOT IMPL void *operator new(size_t, unsigned) LLVM_DELETED_FUNCTION;
EMENT ConstantDataSequential(const ConstantDataSequential &) LLVM_DELETED_FUNCT
ConstantDataSequential(const ConstantDataSequential &); // DO NOT IMPL ION;
EMENT
protected: protected:
explicit ConstantDataSequential(Type *ty, ValueTy VT, const char *Data) explicit ConstantDataSequential(Type *ty, ValueTy VT, const char *Data)
: Constant(ty, VT, 0, 0), DataElements(Data), Next(0) {} : Constant(ty, VT, 0, 0), DataElements(Data), Next(0) {}
~ConstantDataSequential() { delete Next; } ~ConstantDataSequential() { delete Next; }
static Constant *getImpl(StringRef Bytes, Type *Ty); static Constant *getImpl(StringRef Bytes, Type *Ty);
protected: protected:
// allocate space for exactly zero operands. // allocate space for exactly zero operands.
void *operator new(size_t s) { void *operator new(size_t s) {
skipping to change at line 638 skipping to change at line 628
/// getRawDataValues - Return the raw, underlying, bytes of this data. N ote /// getRawDataValues - Return the raw, underlying, bytes of this data. N ote
/// that this is an extremely tricky thing to work with, as it exposes th e /// that this is an extremely tricky thing to work with, as it exposes th e
/// host endianness of the data elements. /// host endianness of the data elements.
StringRef getRawDataValues() const; StringRef getRawDataValues() const;
virtual void destroyConstant(); virtual void destroyConstant();
/// Methods for support type inquiry through isa, cast, and dyn_cast: /// Methods for support type inquiry through isa, cast, and dyn_cast:
/// ///
static bool classof(const ConstantDataSequential *) { return true; }
static bool classof(const Value *V) { static bool classof(const Value *V) {
return V->getValueID() == ConstantDataArrayVal || return V->getValueID() == ConstantDataArrayVal ||
V->getValueID() == ConstantDataVectorVal; V->getValueID() == ConstantDataVectorVal;
} }
private: private:
const char *getElementPointer(unsigned Elt) const; const char *getElementPointer(unsigned Elt) const;
}; };
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
/// ConstantDataArray - An array constant whose element type is a simple /// ConstantDataArray - An array constant whose element type is a simple
/// 1/2/4/8-byte integer or float/double, and whose elements are just simpl e /// 1/2/4/8-byte integer or float/double, and whose elements are just simpl e
/// data values (i.e. ConstantInt/ConstantFP). This Constant node has no /// data values (i.e. ConstantInt/ConstantFP). This Constant node has no
/// operands because it stores all of the elements of the constant as dense ly /// operands because it stores all of the elements of the constant as dense ly
/// packed data, instead of as Value*'s. /// packed data, instead of as Value*'s.
class ConstantDataArray : public ConstantDataSequential { class ConstantDataArray : public ConstantDataSequential {
void *operator new(size_t, unsigned); // DO NOT IMPLEMENT void *operator new(size_t, unsigned) LLVM_DELETED_FUNCTION;
ConstantDataArray(const ConstantDataArray &); // DO NOT IMPLEMENT ConstantDataArray(const ConstantDataArray &) LLVM_DELETED_FUNCTION;
virtual void anchor(); virtual void anchor();
friend class ConstantDataSequential; friend class ConstantDataSequential;
explicit ConstantDataArray(Type *ty, const char *Data) explicit ConstantDataArray(Type *ty, const char *Data)
: ConstantDataSequential(ty, ConstantDataArrayVal, Data) {} : ConstantDataSequential(ty, ConstantDataArrayVal, Data) {}
protected: protected:
// allocate space for exactly zero operands. // allocate space for exactly zero operands.
void *operator new(size_t s) { void *operator new(size_t s) {
return User::operator new(s, 0); return User::operator new(s, 0);
} }
public: public:
skipping to change at line 694 skipping to change at line 683
/// getType - Specialize the getType() method to always return an ArrayTy pe, /// getType - Specialize the getType() method to always return an ArrayTy pe,
/// which reduces the amount of casting needed in parts of the compiler. /// which reduces the amount of casting needed in parts of the compiler.
/// ///
inline ArrayType *getType() const { inline ArrayType *getType() const {
return reinterpret_cast<ArrayType*>(Value::getType()); return reinterpret_cast<ArrayType*>(Value::getType());
} }
/// Methods for support type inquiry through isa, cast, and dyn_cast: /// Methods for support type inquiry through isa, cast, and dyn_cast:
/// ///
static bool classof(const ConstantDataArray *) { return true; }
static bool classof(const Value *V) { static bool classof(const Value *V) {
return V->getValueID() == ConstantDataArrayVal; return V->getValueID() == ConstantDataArrayVal;
} }
}; };
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
/// ConstantDataVector - A vector constant whose element type is a simple /// ConstantDataVector - A vector constant whose element type is a simple
/// 1/2/4/8-byte integer or float/double, and whose elements are just simpl e /// 1/2/4/8-byte integer or float/double, and whose elements are just simpl e
/// data values (i.e. ConstantInt/ConstantFP). This Constant node has no /// data values (i.e. ConstantInt/ConstantFP). This Constant node has no
/// operands because it stores all of the elements of the constant as dense ly /// operands because it stores all of the elements of the constant as dense ly
/// packed data, instead of as Value*'s. /// packed data, instead of as Value*'s.
class ConstantDataVector : public ConstantDataSequential { class ConstantDataVector : public ConstantDataSequential {
void *operator new(size_t, unsigned); // DO NOT IMPLEMENT void *operator new(size_t, unsigned) LLVM_DELETED_FUNCTION;
ConstantDataVector(const ConstantDataVector &); // DO NOT IMPLEMENT ConstantDataVector(const ConstantDataVector &) LLVM_DELETED_FUNCTION;
virtual void anchor(); virtual void anchor();
friend class ConstantDataSequential; friend class ConstantDataSequential;
explicit ConstantDataVector(Type *ty, const char *Data) explicit ConstantDataVector(Type *ty, const char *Data)
: ConstantDataSequential(ty, ConstantDataVectorVal, Data) {} : ConstantDataSequential(ty, ConstantDataVectorVal, Data) {}
protected: protected:
// allocate space for exactly zero operands. // allocate space for exactly zero operands.
void *operator new(size_t s) { void *operator new(size_t s) {
return User::operator new(s, 0); return User::operator new(s, 0);
} }
public: public:
skipping to change at line 748 skipping to change at line 736
/// getType - Specialize the getType() method to always return a VectorTy pe, /// getType - Specialize the getType() method to always return a VectorTy pe,
/// which reduces the amount of casting needed in parts of the compiler. /// which reduces the amount of casting needed in parts of the compiler.
/// ///
inline VectorType *getType() const { inline VectorType *getType() const {
return reinterpret_cast<VectorType*>(Value::getType()); return reinterpret_cast<VectorType*>(Value::getType());
} }
/// Methods for support type inquiry through isa, cast, and dyn_cast: /// Methods for support type inquiry through isa, cast, and dyn_cast:
/// ///
static bool classof(const ConstantDataVector *) { return true; }
static bool classof(const Value *V) { static bool classof(const Value *V) {
return V->getValueID() == ConstantDataVectorVal; return V->getValueID() == ConstantDataVectorVal;
} }
}; };
/// BlockAddress - The address of a basic block. /// BlockAddress - The address of a basic block.
/// ///
class BlockAddress : public Constant { class BlockAddress : public Constant {
void *operator new(size_t, unsigned); // DO NOT IMPLEMEN T void *operator new(size_t, unsigned) LLVM_DELETED_FUNCTION;
void *operator new(size_t s) { return User::operator new(s, 2); } void *operator new(size_t s) { return User::operator new(s, 2); }
BlockAddress(Function *F, BasicBlock *BB); BlockAddress(Function *F, BasicBlock *BB);
public: public:
/// get - Return a BlockAddress for the specified function and basic bloc k. /// get - Return a BlockAddress for the specified function and basic bloc k.
static BlockAddress *get(Function *F, BasicBlock *BB); static BlockAddress *get(Function *F, BasicBlock *BB);
/// get - Return a BlockAddress for the specified basic block. The basic /// get - Return a BlockAddress for the specified basic block. The basic
/// block must be embedded into a function. /// block must be embedded into a function.
static BlockAddress *get(BasicBlock *BB); static BlockAddress *get(BasicBlock *BB);
/// Transparently provide more efficient getOperand methods. /// Transparently provide more efficient getOperand methods.
DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value); DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value);
Function *getFunction() const { return (Function*)Op<0>().get(); } Function *getFunction() const { return (Function*)Op<0>().get(); }
BasicBlock *getBasicBlock() const { return (BasicBlock*)Op<1>().get(); } BasicBlock *getBasicBlock() const { return (BasicBlock*)Op<1>().get(); }
virtual void destroyConstant(); virtual void destroyConstant();
virtual void replaceUsesOfWithOnConstant(Value *From, Value *To, Use *U); virtual void replaceUsesOfWithOnConstant(Value *From, Value *To, Use *U);
/// Methods for support type inquiry through isa, cast, and dyn_cast: /// Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const BlockAddress *) { return true; }
static inline bool classof(const Value *V) { static inline bool classof(const Value *V) {
return V->getValueID() == BlockAddressVal; return V->getValueID() == BlockAddressVal;
} }
}; };
template <> template <>
struct OperandTraits<BlockAddress> : struct OperandTraits<BlockAddress> :
public FixedNumOperandTraits<BlockAddress, 2> { public FixedNumOperandTraits<BlockAddress, 2> {
}; };
skipping to change at line 913 skipping to change at line 899
static Constant *getExactUDiv(Constant *C1, Constant *C2) { static Constant *getExactUDiv(Constant *C1, Constant *C2) {
return getUDiv(C1, C2, true); return getUDiv(C1, C2, true);
} }
static Constant *getExactAShr(Constant *C1, Constant *C2) { static Constant *getExactAShr(Constant *C1, Constant *C2) {
return getAShr(C1, C2, true); return getAShr(C1, C2, true);
} }
static Constant *getExactLShr(Constant *C1, Constant *C2) { static Constant *getExactLShr(Constant *C1, Constant *C2) {
return getLShr(C1, C2, true); return getLShr(C1, C2, true);
} }
/// getBinOpIdentity - Return the identity for the given binary operation
,
/// i.e. a constant C such that X op C = X and C op X = X for every X. I
t
/// returns null if the operator doesn't have an identity.
static Constant *getBinOpIdentity(unsigned Opcode, Type *Ty);
/// getBinOpAbsorber - Return the absorbing element for the given binary
/// operation, i.e. a constant C such that X op C = C and C op X = C for
/// every X. For example, this returns zero for integer multiplication.
/// It returns null if the operator doesn't have an absorbing element.
static Constant *getBinOpAbsorber(unsigned Opcode, Type *Ty);
/// Transparently provide more efficient getOperand methods. /// Transparently provide more efficient getOperand methods.
DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Constant); DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Constant);
// @brief Convenience function for getting one of the casting operations // @brief Convenience function for getting one of the casting operations
// using a CastOps opcode. // using a CastOps opcode.
static Constant *getCast( static Constant *getCast(
unsigned ops, ///< The opcode for the conversion unsigned ops, ///< The opcode for the conversion
Constant *C, ///< The constant to be converted Constant *C, ///< The constant to be converted
Type *Ty ///< The type to which the constant is converted Type *Ty ///< The type to which the constant is converted
); );
skipping to change at line 1079 skipping to change at line 1076
/// getWithOperands - This returns the current constant expression with t he /// getWithOperands - This returns the current constant expression with t he
/// operands replaced with the specified values and with the specified re sult /// operands replaced with the specified values and with the specified re sult
/// type. The specified array must have the same number of operands as o ur /// type. The specified array must have the same number of operands as o ur
/// current one. /// current one.
Constant *getWithOperands(ArrayRef<Constant*> Ops, Type *Ty) const; Constant *getWithOperands(ArrayRef<Constant*> Ops, Type *Ty) const;
virtual void destroyConstant(); virtual void destroyConstant();
virtual void replaceUsesOfWithOnConstant(Value *From, Value *To, Use *U); virtual void replaceUsesOfWithOnConstant(Value *From, Value *To, Use *U);
/// Methods for support type inquiry through isa, cast, and dyn_cast: /// Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const ConstantExpr *) { return true; }
static inline bool classof(const Value *V) { static inline bool classof(const Value *V) {
return V->getValueID() == ConstantExprVal; return V->getValueID() == ConstantExprVal;
} }
private: private:
// Shadow Value::setValueSubclassData with a private forwarding method so that // Shadow Value::setValueSubclassData with a private forwarding method so that
// subclasses cannot accidentally use it. // subclasses cannot accidentally use it.
void setValueSubclassData(unsigned short D) { void setValueSubclassData(unsigned short D) {
Value::setValueSubclassData(D); Value::setValueSubclassData(D);
} }
skipping to change at line 1110 skipping to change at line 1106
/// UndefValue - 'undef' values are things that do not have specified conte nts. /// UndefValue - 'undef' values are things that do not have specified conte nts.
/// These are used for a variety of purposes, including global variable /// These are used for a variety of purposes, including global variable
/// initializers and operands to instructions. 'undef' values can occur wi th /// initializers and operands to instructions. 'undef' values can occur wi th
/// any first-class type. /// any first-class type.
/// ///
/// Undef values aren't exactly constants; if they have multiple uses, they /// Undef values aren't exactly constants; if they have multiple uses, they
/// can appear to have different bit patterns at each use. See /// can appear to have different bit patterns at each use. See
/// LangRef.html#undefvalues for details. /// LangRef.html#undefvalues for details.
/// ///
class UndefValue : public Constant { class UndefValue : public Constant {
void *operator new(size_t, unsigned); // DO NOT IMPLEMENT void *operator new(size_t, unsigned) LLVM_DELETED_FUNCTION;
UndefValue(const UndefValue &); // DO NOT IMPLEMENT UndefValue(const UndefValue &) LLVM_DELETED_FUNCTION;
protected: protected:
explicit UndefValue(Type *T) : Constant(T, UndefValueVal, 0, 0) {} explicit UndefValue(Type *T) : Constant(T, UndefValueVal, 0, 0) {}
protected: protected:
// allocate space for exactly zero operands // allocate space for exactly zero operands
void *operator new(size_t s) { void *operator new(size_t s) {
return User::operator new(s, 0); return User::operator new(s, 0);
} }
public: public:
/// get() - Static factory methods - Return an 'undef' object of the spec ified /// get() - Static factory methods - Return an 'undef' object of the spec ified
/// type. /// type.
skipping to change at line 1144 skipping to change at line 1140
/// index. /// index.
UndefValue *getElementValue(Constant *C) const; UndefValue *getElementValue(Constant *C) const;
/// getElementValue - Return an undef of the right value for the specifie d GEP /// getElementValue - Return an undef of the right value for the specifie d GEP
/// index. /// index.
UndefValue *getElementValue(unsigned Idx) const; UndefValue *getElementValue(unsigned Idx) const;
virtual void destroyConstant(); virtual void destroyConstant();
/// Methods for support type inquiry through isa, cast, and dyn_cast: /// Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const UndefValue *) { return true; }
static bool classof(const Value *V) { static bool classof(const Value *V) {
return V->getValueID() == UndefValueVal; return V->getValueID() == UndefValueVal;
} }
}; };
} // End llvm namespace } // End llvm namespace
#endif #endif
 End of changes. 27 change blocks. 
42 lines changed or deleted 35 lines changed or added


 Core.h   Core.h 
skipping to change at line 24 skipping to change at line 24
#ifndef LLVM_C_CORE_H #ifndef LLVM_C_CORE_H
#define LLVM_C_CORE_H #define LLVM_C_CORE_H
#include "llvm/Support/DataTypes.h" #include "llvm/Support/DataTypes.h"
#ifdef __cplusplus #ifdef __cplusplus
/* Need these includes to support the LLVM 'cast' template for the C++ 'wra p' /* Need these includes to support the LLVM 'cast' template for the C++ 'wra p'
and 'unwrap' conversion functions. */ and 'unwrap' conversion functions. */
#include "llvm/IRBuilder.h"
#include "llvm/Module.h" #include "llvm/Module.h"
#include "llvm/PassRegistry.h" #include "llvm/PassRegistry.h"
#include "llvm/Support/IRBuilder.h"
extern "C" { extern "C" {
#endif #endif
/** /**
* @defgroup LLVMC LLVM-C: C interface to LLVM * @defgroup LLVMC LLVM-C: C interface to LLVM
* *
* This module exposes parts of the LLVM library as a C API. * This module exposes parts of the LLVM library as a C API.
* *
* @{ * @{
skipping to change at line 56 skipping to change at line 56
* This modules provide an interface to libLLVMCore, which implements * This modules provide an interface to libLLVMCore, which implements
* the LLVM intermediate representation as well as other related types * the LLVM intermediate representation as well as other related types
* and utilities. * and utilities.
* *
* LLVM uses a polymorphic type hierarchy which C cannot represent, therefo re * LLVM uses a polymorphic type hierarchy which C cannot represent, therefo re
* parameters must be passed as base types. Despite the declared types, mos t * parameters must be passed as base types. Despite the declared types, mos t
* of the functions provided operate only on branches of the type hierarchy . * of the functions provided operate only on branches of the type hierarchy .
* The declared parameter names are descriptive and specify which type is * The declared parameter names are descriptive and specify which type is
* required. Additionally, each type hierarchy is documented along with the * required. Additionally, each type hierarchy is documented along with the
* functions that operate upon it. For more detail, refer to LLVM's C++ cod e. * functions that operate upon it. For more detail, refer to LLVM's C++ cod e.
* If in doubt, refer to Core.cpp, which performs paramter downcasts in the * If in doubt, refer to Core.cpp, which performs parameter downcasts in th e
* form unwrap<RequiredType>(Param). * form unwrap<RequiredType>(Param).
* *
* Many exotic languages can interoperate with C code but have a harder tim e * Many exotic languages can interoperate with C code but have a harder tim e
* with C++ due to name mangling. So in addition to C, this interface enabl es * with C++ due to name mangling. So in addition to C, this interface enabl es
* tools written in such languages. * tools written in such languages.
* *
* When included into a C++ source file, also declares 'wrap' and 'unwrap' * When included into a C++ source file, also declares 'wrap' and 'unwrap'
* helpers to perform opaque reference<-->pointer conversions. These helper s * helpers to perform opaque reference<-->pointer conversions. These helper s
* are shorter and more tightly typed than writing the casts by hand when * are shorter and more tightly typed than writing the casts by hand when
* authoring bindings. In assert builds, they will do runtime type checking . * authoring bindings. In assert builds, they will do runtime type checking .
skipping to change at line 109 skipping to change at line 109
typedef struct LLVMOpaqueType *LLVMTypeRef; typedef struct LLVMOpaqueType *LLVMTypeRef;
/** /**
* Represents an individual value in LLVM IR. * Represents an individual value in LLVM IR.
* *
* This models llvm::Value. * This models llvm::Value.
*/ */
typedef struct LLVMOpaqueValue *LLVMValueRef; typedef struct LLVMOpaqueValue *LLVMValueRef;
/** /**
* Represents a basic block of instruction in LLVM IR. * Represents a basic block of instructions in LLVM IR.
* *
* This models llvm::BasicBlock. * This models llvm::BasicBlock.
*/ */
typedef struct LLVMOpaqueBasicBlock *LLVMBasicBlockRef; typedef struct LLVMOpaqueBasicBlock *LLVMBasicBlockRef;
/** /**
* Represents an LLVM basic block builder. * Represents an LLVM basic block builder.
* *
* This models llvm::IRBuilder. * This models llvm::IRBuilder.
*/ */
skipping to change at line 176 skipping to change at line 176
LLVMNoCaptureAttribute = 1<<21, LLVMNoCaptureAttribute = 1<<21,
LLVMNoRedZoneAttribute = 1<<22, LLVMNoRedZoneAttribute = 1<<22,
LLVMNoImplicitFloatAttribute = 1<<23, LLVMNoImplicitFloatAttribute = 1<<23,
LLVMNakedAttribute = 1<<24, LLVMNakedAttribute = 1<<24,
LLVMInlineHintAttribute = 1<<25, LLVMInlineHintAttribute = 1<<25,
LLVMStackAlignment = 7<<26, LLVMStackAlignment = 7<<26,
LLVMReturnsTwice = 1 << 29, LLVMReturnsTwice = 1 << 29,
LLVMUWTable = 1 << 30, LLVMUWTable = 1 << 30,
LLVMNonLazyBind = 1 << 31 LLVMNonLazyBind = 1 << 31
// FIXME: This attribute is currently not included in the C API as /* FIXME: This attribute is currently not included in the C API as
// a temporary measure until the API/ABI impact to the C API is underst a temporary measure until the API/ABI impact to the C API is underst
ood ood
// and the path forward agreed upon. and the path forward agreed upon.
//LLVMAddressSafety = 1ULL << 32 LLVMAddressSafety = 1ULL << 32
*/
} LLVMAttribute; } LLVMAttribute;
typedef enum { typedef enum {
/* Terminator Instructions */ /* Terminator Instructions */
LLVMRet = 1, LLVMRet = 1,
LLVMBr = 2, LLVMBr = 2,
LLVMSwitch = 3, LLVMSwitch = 3,
LLVMIndirectBr = 4, LLVMIndirectBr = 4,
LLVMInvoke = 5, LLVMInvoke = 5,
/* removed 6 due to API changes */ /* removed 6 due to API changes */
skipping to change at line 285 skipping to change at line 286
LLVMMetadataTypeKind, /**< Metadata */ LLVMMetadataTypeKind, /**< Metadata */
LLVMX86_MMXTypeKind /**< X86 MMX */ LLVMX86_MMXTypeKind /**< X86 MMX */
} LLVMTypeKind; } LLVMTypeKind;
typedef enum { typedef enum {
LLVMExternalLinkage, /**< Externally visible function */ LLVMExternalLinkage, /**< Externally visible function */
LLVMAvailableExternallyLinkage, LLVMAvailableExternallyLinkage,
LLVMLinkOnceAnyLinkage, /**< Keep one copy of function when linking (inli ne)*/ LLVMLinkOnceAnyLinkage, /**< Keep one copy of function when linking (inli ne)*/
LLVMLinkOnceODRLinkage, /**< Same, but only replaced by something LLVMLinkOnceODRLinkage, /**< Same, but only replaced by something
equivalent. */ equivalent. */
LLVMLinkOnceODRAutoHideLinkage, /**< Like LinkOnceODR, but possibly hidde n. */
LLVMWeakAnyLinkage, /**< Keep one copy of function when linking (weak ) */ LLVMWeakAnyLinkage, /**< Keep one copy of function when linking (weak ) */
LLVMWeakODRLinkage, /**< Same, but only replaced by something LLVMWeakODRLinkage, /**< Same, but only replaced by something
equivalent. */ equivalent. */
LLVMAppendingLinkage, /**< Special purpose, only applies to global arra ys */ LLVMAppendingLinkage, /**< Special purpose, only applies to global arra ys */
LLVMInternalLinkage, /**< Rename collisions when linking (static LLVMInternalLinkage, /**< Rename collisions when linking (static
functions) */ functions) */
LLVMPrivateLinkage, /**< Like Internal, but omit from symbol table */ LLVMPrivateLinkage, /**< Like Internal, but omit from symbol table */
LLVMDLLImportLinkage, /**< Function to be imported from DLL */ LLVMDLLImportLinkage, /**< Function to be imported from DLL */
LLVMDLLExportLinkage, /**< Function to be accessible from DLL */ LLVMDLLExportLinkage, /**< Function to be accessible from DLL */
LLVMExternalWeakLinkage,/**< ExternalWeak linkage description */ LLVMExternalWeakLinkage,/**< ExternalWeak linkage description */
LLVMGhostLinkage, /**< Obsolete */ LLVMGhostLinkage, /**< Obsolete */
LLVMCommonLinkage, /**< Tentative definitions */ LLVMCommonLinkage, /**< Tentative definitions */
LLVMLinkerPrivateLinkage, /**< Like Private, but linker removes. */ LLVMLinkerPrivateLinkage, /**< Like Private, but linker removes. */
LLVMLinkerPrivateWeakLinkage, /**< Like LinkerPrivate, but is weak. */ LLVMLinkerPrivateWeakLinkage /**< Like LinkerPrivate, but is weak. */
LLVMLinkerPrivateWeakDefAutoLinkage /**< Like LinkerPrivateWeak, but poss
ibly
hidden. */
} LLVMLinkage; } LLVMLinkage;
typedef enum { typedef enum {
LLVMDefaultVisibility, /**< The GV is visible */ LLVMDefaultVisibility, /**< The GV is visible */
LLVMHiddenVisibility, /**< The GV is hidden */ LLVMHiddenVisibility, /**< The GV is hidden */
LLVMProtectedVisibility /**< The GV is protected */ LLVMProtectedVisibility /**< The GV is protected */
} LLVMVisibility; } LLVMVisibility;
typedef enum { typedef enum {
LLVMCCallConv = 0, LLVMCCallConv = 0,
skipping to change at line 479 skipping to change at line 479
void LLVMSetTarget(LLVMModuleRef M, const char *Triple); void LLVMSetTarget(LLVMModuleRef M, const char *Triple);
/** /**
* Dump a representation of a module to stderr. * Dump a representation of a module to stderr.
* *
* @see Module::dump() * @see Module::dump()
*/ */
void LLVMDumpModule(LLVMModuleRef M); void LLVMDumpModule(LLVMModuleRef M);
/** /**
* Print a representation of a module to a file. The ErrorMessage needs to
be
* disposed with LLVMDisposeMessage. Returns 0 on success, 1 otherwise.
*
* @see Module::print()
*/
LLVMBool LLVMPrintModuleToFile(LLVMModuleRef M, const char *Filename,
char **ErrorMessage);
/**
* Set inline assembly for a module. * Set inline assembly for a module.
* *
* @see Module::setModuleInlineAsm() * @see Module::setModuleInlineAsm()
*/ */
void LLVMSetModuleInlineAsm(LLVMModuleRef M, const char *Asm); void LLVMSetModuleInlineAsm(LLVMModuleRef M, const char *Asm);
/** /**
* Obtain the context to which this module is associated. * Obtain the context to which this module is associated.
* *
* @see Module::getContext() * @see Module::getContext()
skipping to change at line 977 skipping to change at line 986
*/ */
/** /**
* @defgroup LLVMCCoreValues Values * @defgroup LLVMCCoreValues Values
* *
* The bulk of LLVM's object model consists of values, which comprise a ver y * The bulk of LLVM's object model consists of values, which comprise a ver y
* rich type hierarchy. * rich type hierarchy.
* *
* LLVMValueRef essentially represents llvm::Value. There is a rich * LLVMValueRef essentially represents llvm::Value. There is a rich
* hierarchy of classes within this type. Depending on the instance * hierarchy of classes within this type. Depending on the instance
* obtain, not all APIs are available. * obtained, not all APIs are available.
* *
* Callers can determine the type of a LLVMValueRef by calling the * Callers can determine the type of a LLVMValueRef by calling the
* LLVMIsA* family of functions (e.g. LLVMIsAArgument()). These * LLVMIsA* family of functions (e.g. LLVMIsAArgument()). These
* functions are defined by a macro, so it isn't obvious which are * functions are defined by a macro, so it isn't obvious which are
* available by looking at the Doxygen source code. Instead, look at the * available by looking at the Doxygen source code. Instead, look at the
* source definition of LLVM_FOR_EACH_VALUE_SUBCLASS and note the list * source definition of LLVM_FOR_EACH_VALUE_SUBCLASS and note the list
* of value names given. These value names also correspond to classes in * of value names given. These value names also correspond to classes in
* the llvm::Value hierarchy. * the llvm::Value hierarchy.
* *
* @{ * @{
skipping to change at line 1153 skipping to change at line 1162
* llvm::User and llvm::Value. * llvm::User and llvm::Value.
* *
* @{ * @{
*/ */
/** /**
* Obtain the first use of a value. * Obtain the first use of a value.
* *
* Uses are obtained in an iterator fashion. First, call this function * Uses are obtained in an iterator fashion. First, call this function
* to obtain a reference to the first use. Then, call LLVMGetNextUse() * to obtain a reference to the first use. Then, call LLVMGetNextUse()
* on that instance and all subsequently obtained instances untl * on that instance and all subsequently obtained instances until
* LLVMGetNextUse() returns NULL. * LLVMGetNextUse() returns NULL.
* *
* @see llvm::Value::use_begin() * @see llvm::Value::use_begin()
*/ */
LLVMUseRef LLVMGetFirstUse(LLVMValueRef Val); LLVMUseRef LLVMGetFirstUse(LLVMValueRef Val);
/** /**
* Obtain the next use of a value. * Obtain the next use of a value.
* *
* This effectively advances the iterator. It returns NULL if you are on * This effectively advances the iterator. It returns NULL if you are on
skipping to change at line 1794 skipping to change at line 1803
/** /**
* Get an attribute from a function argument. * Get an attribute from a function argument.
*/ */
LLVMAttribute LLVMGetAttribute(LLVMValueRef Arg); LLVMAttribute LLVMGetAttribute(LLVMValueRef Arg);
/** /**
* Set the alignment for a function parameter. * Set the alignment for a function parameter.
* *
* @see llvm::Argument::addAttr() * @see llvm::Argument::addAttr()
* @see llvm::Attribute::constructAlignmentFromInt() * @see llvm::AttrBuilder::addAlignmentAttr()
*/ */
void LLVMSetParamAlignment(LLVMValueRef Arg, unsigned align); void LLVMSetParamAlignment(LLVMValueRef Arg, unsigned align);
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
skipping to change at line 1860 skipping to change at line 1869
/** /**
* Obtain the underlying string from a MDString value. * Obtain the underlying string from a MDString value.
* *
* @param V Instance to obtain string from. * @param V Instance to obtain string from.
* @param Len Memory address which will hold length of returned string. * @param Len Memory address which will hold length of returned string.
* @return String data in MDString. * @return String data in MDString.
*/ */
const char *LLVMGetMDString(LLVMValueRef V, unsigned* Len); const char *LLVMGetMDString(LLVMValueRef V, unsigned* Len);
/** /**
* Obtain the number of operands from an MDNode value.
*
* @param V MDNode to get number of operands from.
* @return Number of operands of the MDNode.
*/
unsigned LLVMGetMDNodeNumOperands(LLVMValueRef V);
/**
* Obtain the given MDNode's operands.
*
* The passed LLVMValueRef pointer should point to enough memory to hold al
l of
* the operands of the given MDNode (see LLVMGetMDNodeNumOperands) as
* LLVMValueRefs. This memory will be populated with the LLVMValueRefs of t
he
* MDNode's operands.
*
* @param V MDNode to get the operands from.
* @param Dest Destination array for operands.
*/
void LLVMGetMDNodeOperands(LLVMValueRef V, LLVMValueRef *Dest);
/**
* @} * @}
*/ */
/** /**
* @defgroup LLVMCCoreValueBasicBlock Basic Block * @defgroup LLVMCCoreValueBasicBlock Basic Block
* *
* A basic block represents a single entry single exit section of code. * A basic block represents a single entry single exit section of code.
* Basic blocks contain a list of instructions which form the body of * Basic blocks contain a list of instructions which form the body of
* the block. * the block.
* *
skipping to change at line 2106 skipping to change at line 2136
* Obtain the instruction that occurs after the one specified. * Obtain the instruction that occurs after the one specified.
* *
* The next instruction will be from the same basic block. * The next instruction will be from the same basic block.
* *
* If this is the last instruction in a basic block, NULL will be * If this is the last instruction in a basic block, NULL will be
* returned. * returned.
*/ */
LLVMValueRef LLVMGetNextInstruction(LLVMValueRef Inst); LLVMValueRef LLVMGetNextInstruction(LLVMValueRef Inst);
/** /**
* Obtain the instruction that occured before this one. * Obtain the instruction that occurred before this one.
* *
* If the instruction is the first instruction in a basic block, NULL * If the instruction is the first instruction in a basic block, NULL
* will be returned. * will be returned.
*/ */
LLVMValueRef LLVMGetPreviousInstruction(LLVMValueRef Inst); LLVMValueRef LLVMGetPreviousInstruction(LLVMValueRef Inst);
/** /**
* Remove and delete an instruction. * Remove and delete an instruction.
* *
* The instruction specified is removed from its containing building * The instruction specified is removed from its containing building
skipping to change at line 2678 skipping to change at line 2708
} }
/* Specialized opaque value conversions. /* Specialized opaque value conversions.
*/ */
inline Value **unwrap(LLVMValueRef *Vals) { inline Value **unwrap(LLVMValueRef *Vals) {
return reinterpret_cast<Value**>(Vals); return reinterpret_cast<Value**>(Vals);
} }
template<typename T> template<typename T>
inline T **unwrap(LLVMValueRef *Vals, unsigned Length) { inline T **unwrap(LLVMValueRef *Vals, unsigned Length) {
#if DEBUG #ifdef DEBUG
for (LLVMValueRef *I = Vals, *E = Vals + Length; I != E; ++I) for (LLVMValueRef *I = Vals, *E = Vals + Length; I != E; ++I)
cast<T>(*I); cast<T>(*I);
#endif #endif
(void)Length; (void)Length;
return reinterpret_cast<T**>(Vals); return reinterpret_cast<T**>(Vals);
} }
inline LLVMValueRef *wrap(const Value **Vals) { inline LLVMValueRef *wrap(const Value **Vals) {
return reinterpret_cast<LLVMValueRef*>(const_cast<Value**>(Vals)); return reinterpret_cast<LLVMValueRef*>(const_cast<Value**>(Vals));
} }
 End of changes. 14 change blocks. 
17 lines changed or deleted 49 lines changed or added


 DAGDeltaAlgorithm.h   DAGDeltaAlgorithm.h 
skipping to change at line 51 skipping to change at line 51
typedef unsigned change_ty; typedef unsigned change_ty;
typedef std::pair<change_ty, change_ty> edge_ty; typedef std::pair<change_ty, change_ty> edge_ty;
// FIXME: Use a decent data structure. // FIXME: Use a decent data structure.
typedef std::set<change_ty> changeset_ty; typedef std::set<change_ty> changeset_ty;
typedef std::vector<changeset_ty> changesetlist_ty; typedef std::vector<changeset_ty> changesetlist_ty;
public: public:
virtual ~DAGDeltaAlgorithm() {} virtual ~DAGDeltaAlgorithm() {}
/// Run - Minimize the DAG formed by the \arg Changes vertices and the \a /// Run - Minimize the DAG formed by the \p Changes vertices and the
rg /// \p Dependencies edges by executing \see ExecuteOneTest() on subsets o
/// Dependencies edges by executing \see ExecuteOneTest() on subsets of f
/// changes and returning the smallest set which still satisfies the test /// changes and returning the smallest set which still satisfies the test
/// predicate and the input \arg Dependencies. /// predicate and the input \p Dependencies.
/// ///
/// \param Changes The list of changes. /// \param Changes The list of changes.
/// ///
/// \param Dependencies The list of dependencies amongst changes. For eac h /// \param Dependencies The list of dependencies amongst changes. For eac h
/// (x,y) in \arg Dependencies, both x and y must be in \arg Changes. The /// (x,y) in \p Dependencies, both x and y must be in \p Changes. The
/// minimization algorithm guarantees that for each tested changed set S, /// minimization algorithm guarantees that for each tested changed set S,
x /// \f$ x \in S \f$ implies \f$ y \in S \f$. It is an error to have cycli
/// \in S implies y \in S. It is an error to have cyclic dependencies. c
/// dependencies.
changeset_ty Run(const changeset_ty &Changes, changeset_ty Run(const changeset_ty &Changes,
const std::vector<edge_ty> &Dependencies); const std::vector<edge_ty> &Dependencies);
/// UpdatedSearchState - Callback used when the search state changes. /// UpdatedSearchState - Callback used when the search state changes.
virtual void UpdatedSearchState(const changeset_ty &Changes, virtual void UpdatedSearchState(const changeset_ty &Changes,
const changesetlist_ty &Sets, const changesetlist_ty &Sets,
const changeset_ty &Required) {} const changeset_ty &Required) {}
/// ExecuteOneTest - Execute a single test predicate on the change set \a rg S. /// ExecuteOneTest - Execute a single test predicate on the change set \p S.
virtual bool ExecuteOneTest(const changeset_ty &S) = 0; virtual bool ExecuteOneTest(const changeset_ty &S) = 0;
}; };
} // end namespace llvm } // end namespace llvm
#endif #endif
 End of changes. 4 change blocks. 
9 lines changed or deleted 10 lines changed or added


 DFAPacketizer.h   DFAPacketizer.h 
skipping to change at line 31 skipping to change at line 31
// transition exists from the corresponding state. Invalid transitions // transition exists from the corresponding state. Invalid transitions
// indicate that the instruction cannot be added to the current packet. // indicate that the instruction cannot be added to the current packet.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_CODEGEN_DFAPACKETIZER_H #ifndef LLVM_CODEGEN_DFAPACKETIZER_H
#define LLVM_CODEGEN_DFAPACKETIZER_H #define LLVM_CODEGEN_DFAPACKETIZER_H
#include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/ADT/DenseMap.h" #include "llvm/ADT/DenseMap.h"
#include <map>
namespace llvm { namespace llvm {
class MCInstrDesc; class MCInstrDesc;
class MachineInstr; class MachineInstr;
class MachineLoopInfo; class MachineLoopInfo;
class MachineDominatorTree; class MachineDominatorTree;
class InstrItineraryData; class InstrItineraryData;
class ScheduleDAGInstrs; class DefaultVLIWScheduler;
class SUnit; class SUnit;
class DFAPacketizer { class DFAPacketizer {
private: private:
typedef std::pair<unsigned, unsigned> UnsignPair; typedef std::pair<unsigned, unsigned> UnsignPair;
const InstrItineraryData *InstrItins; const InstrItineraryData *InstrItins;
int CurrentState; int CurrentState;
const int (*DFAStateInputTable)[2]; const int (*DFAStateInputTable)[2];
const unsigned *DFAStateEntryTable; const unsigned *DFAStateEntryTable;
skipping to change at line 80 skipping to change at line 81
// change the current state to reflect that change. // change the current state to reflect that change.
void reserveResources(const llvm::MCInstrDesc *MID); void reserveResources(const llvm::MCInstrDesc *MID);
// canReserveResources - Check if the resources occupied by a machine // canReserveResources - Check if the resources occupied by a machine
// instruction are available in the current state. // instruction are available in the current state.
bool canReserveResources(llvm::MachineInstr *MI); bool canReserveResources(llvm::MachineInstr *MI);
// reserveResources - Reserve the resources occupied by a machine // reserveResources - Reserve the resources occupied by a machine
// instruction and change the current state to reflect that change. // instruction and change the current state to reflect that change.
void reserveResources(llvm::MachineInstr *MI); void reserveResources(llvm::MachineInstr *MI);
const InstrItineraryData *getInstrItins() const { return InstrItins; }
}; };
// VLIWPacketizerList - Implements a simple VLIW packetizer using DFA. The // VLIWPacketizerList - Implements a simple VLIW packetizer using DFA. The
// packetizer works on machine basic blocks. For each instruction I in BB, the // packetizer works on machine basic blocks. For each instruction I in BB, the
// packetizer consults the DFA to see if machine resources are available to // packetizer consults the DFA to see if machine resources are available to
// execute I. If so, the packetizer checks if I depends on any instruction J in // execute I. If so, the packetizer checks if I depends on any instruction J in
// the current packet. If no dependency is found, I is added to current pac ket // the current packet. If no dependency is found, I is added to current pac ket
// and machine resource is marked as taken. If any dependency is found, a t arget // and machine resource is marked as taken. If any dependency is found, a t arget
// API call is made to prune the dependence. // API call is made to prune the dependence.
class VLIWPacketizerList { class VLIWPacketizerList {
protected:
const TargetMachine &TM; const TargetMachine &TM;
const MachineFunction &MF; const MachineFunction &MF;
const TargetInstrInfo *TII; const TargetInstrInfo *TII;
// Encapsulate data types not exposed to the target interface. // The VLIW Scheduler.
ScheduleDAGInstrs *SchedulerImpl; DefaultVLIWScheduler *VLIWScheduler;
protected:
// Vector of instructions assigned to the current packet. // Vector of instructions assigned to the current packet.
std::vector<MachineInstr*> CurrentPacketMIs; std::vector<MachineInstr*> CurrentPacketMIs;
// DFA resource tracker. // DFA resource tracker.
DFAPacketizer *ResourceTracker; DFAPacketizer *ResourceTracker;
// Scheduling units.
std::vector<SUnit> SUnits; // Generate MI -> SU map.
std::map<MachineInstr*, SUnit*> MIToSUnit;
public: public:
VLIWPacketizerList( VLIWPacketizerList(
MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT, MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT,
bool IsPostRA); bool IsPostRA);
virtual ~VLIWPacketizerList(); virtual ~VLIWPacketizerList();
// PacketizeMIs - Implement this API in the backend to bundle instruction s. // PacketizeMIs - Implement this API in the backend to bundle instruction s.
void PacketizeMIs(MachineBasicBlock *MBB, void PacketizeMIs(MachineBasicBlock *MBB,
MachineBasicBlock::iterator BeginItr, MachineBasicBlock::iterator BeginItr,
MachineBasicBlock::iterator EndItr); MachineBasicBlock::iterator EndItr);
// getResourceTracker - return ResourceTracker // getResourceTracker - return ResourceTracker
DFAPacketizer *getResourceTracker() {return ResourceTracker;} DFAPacketizer *getResourceTracker() {return ResourceTracker;}
// addToPacket - Add MI to the current packet. // addToPacket - Add MI to the current packet.
void addToPacket(MachineInstr *MI); virtual MachineBasicBlock::iterator addToPacket(MachineInstr *MI) {
MachineBasicBlock::iterator MII = MI;
CurrentPacketMIs.push_back(MI);
ResourceTracker->reserveResources(MI);
return MII;
}
// endPacket - End the current packet. // endPacket - End the current packet.
void endPacket(MachineBasicBlock *MBB, MachineInstr *I); void endPacket(MachineBasicBlock *MBB, MachineInstr *MI);
// initPacketizerState - perform initialization before packetizing
// an instruction. This function is supposed to be overrided by
// the target dependent packetizer.
virtual void initPacketizerState(void) { return; }
// ignorePseudoInstruction - Ignore bundling of pseudo instructions. // ignorePseudoInstruction - Ignore bundling of pseudo instructions.
bool ignorePseudoInstruction(MachineInstr *I, MachineBasicBlock *MBB); virtual bool ignorePseudoInstruction(MachineInstr *I,
MachineBasicBlock *MBB) {
return false;
}
// isSoloInstruction - return true if instruction I must end previous // isSoloInstruction - return true if instruction MI can not be packetize
// packet. d
bool isSoloInstruction(MachineInstr *I); // with any other instruction, which means that MI itself is a packet.
virtual bool isSoloInstruction(MachineInstr *MI) {
return true;
}
// isLegalToPacketizeTogether - Is it legal to packetize SUI and SUJ // isLegalToPacketizeTogether - Is it legal to packetize SUI and SUJ
// together. // together.
virtual bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) { virtual bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) {
return false; return false;
} }
// isLegalToPruneDependencies - Is it legal to prune dependece between SU I // isLegalToPruneDependencies - Is it legal to prune dependece between SU I
// and SUJ. // and SUJ.
virtual bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) { virtual bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) {
return false; return false;
} }
}; };
} }
#endif #endif
 End of changes. 12 change blocks. 
12 lines changed or deleted 33 lines changed or added


 DIBuilder.h   DIBuilder.h 
//===--- llvm/Analysis/DIBuilder.h - Debug Information Builder --*- C++ -*- ===// //===--- llvm/DIBuilder.h - Debug Information Builder -----------*- C++ -*- ===//
// //
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
// //
// This file is distributed under the University of Illinois Open Source // This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details. // License. See LICENSE.TXT for details.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// //
// This file defines a DIBuilder that is useful for creating debugging // This file defines a DIBuilder that is useful for creating debugging
// information entries in LLVM IR form. // information entries in LLVM IR form.
skipping to change at line 66 skipping to change at line 66
MDNode *TempGVs; MDNode *TempGVs;
Function *DeclareFn; // llvm.dbg.declare Function *DeclareFn; // llvm.dbg.declare
Function *ValueFn; // llvm.dbg.value Function *ValueFn; // llvm.dbg.value
SmallVector<Value *, 4> AllEnumTypes; SmallVector<Value *, 4> AllEnumTypes;
SmallVector<Value *, 4> AllRetainTypes; SmallVector<Value *, 4> AllRetainTypes;
SmallVector<Value *, 4> AllSubprograms; SmallVector<Value *, 4> AllSubprograms;
SmallVector<Value *, 4> AllGVs; SmallVector<Value *, 4> AllGVs;
DIBuilder(const DIBuilder &); // DO NOT IMPLEMENT DIBuilder(const DIBuilder &) LLVM_DELETED_FUNCTION;
void operator=(const DIBuilder &); // DO NOT IMPLEMENT void operator=(const DIBuilder &) LLVM_DELETED_FUNCTION;
public: public:
explicit DIBuilder(Module &M); explicit DIBuilder(Module &M);
const MDNode *getCU() { return TheCU; } const MDNode *getCU() { return TheCU; }
enum ComplexAddrKind { OpPlus=1, OpDeref }; enum ComplexAddrKind { OpPlus=1, OpDeref };
/// finalize - Construct any deferred debug info descriptors. /// finalize - Construct any deferred debug info descriptors.
void finalize(); void finalize();
/// createCompileUnit - A CompileUnit provides an anchor for all debugg ing /// createCompileUnit - A CompileUnit provides an anchor for all debugg ing
skipping to change at line 130 skipping to change at line 130
/// createPointerType - Create debugging information entry for a pointe r. /// createPointerType - Create debugging information entry for a pointe r.
/// @param PointeeTy Type pointed by this pointer. /// @param PointeeTy Type pointed by this pointer.
/// @param SizeInBits Size. /// @param SizeInBits Size.
/// @param AlignInBits Alignment. (optional) /// @param AlignInBits Alignment. (optional)
/// @param Name Pointer type name. (optional) /// @param Name Pointer type name. (optional)
DIType createPointerType(DIType PointeeTy, uint64_t SizeInBits, DIType createPointerType(DIType PointeeTy, uint64_t SizeInBits,
uint64_t AlignInBits = 0, uint64_t AlignInBits = 0,
StringRef Name = StringRef()); StringRef Name = StringRef());
/// createReferenceType - Create debugging information entry for a c++ /// createReferenceType - Create debugging information entry for a c++
/// style reference. /// style reference or rvalue reference type.
DIType createReferenceType(DIType RTy); DIType createReferenceType(unsigned Tag, DIType RTy);
/// createTypedef - Create debugging information entry for a typedef. /// createTypedef - Create debugging information entry for a typedef.
/// @param Ty Original type. /// @param Ty Original type.
/// @param Name Typedef name. /// @param Name Typedef name.
/// @param File File where this type is defined. /// @param File File where this type is defined.
/// @param LineNo Line number. /// @param LineNo Line number.
/// @param Context The surrounding context for the typedef. /// @param Context The surrounding context for the typedef.
DIType createTypedef(DIType Ty, StringRef Name, DIFile File, DIType createTypedef(DIType Ty, StringRef Name, DIFile File,
unsigned LineNo, DIDescriptor Context); unsigned LineNo, DIDescriptor Context);
skipping to change at line 180 skipping to change at line 180
/// createObjCIVar - Create debugging information entry for Objective-C /// createObjCIVar - Create debugging information entry for Objective-C
/// instance variable. /// instance variable.
/// @param Name Member name. /// @param Name Member name.
/// @param File File where this member is defined. /// @param File File where this member is defined.
/// @param LineNo Line number. /// @param LineNo Line number.
/// @param SizeInBits Member size. /// @param SizeInBits Member size.
/// @param AlignInBits Member alignment. /// @param AlignInBits Member alignment.
/// @param OffsetInBits Member offset. /// @param OffsetInBits Member offset.
/// @param Flags Flags to encode member attribute, e.g. private /// @param Flags Flags to encode member attribute, e.g. private
/// @param Ty Parent type. /// @param Ty Parent type.
/// @param PropertyName Name of the Objective C property assoicated wit h /// @param PropertyName Name of the Objective C property associated wit h
/// this ivar. /// this ivar.
/// @param GetterName Name of the Objective C property getter selecto /// @param PropertyGetterName Name of the Objective C property getter
r. /// selector.
/// @param SetterName Name of the Objective C property setter selecto /// @param PropertySetterName Name of the Objective C property setter
r. /// selector.
/// @param PropertyAttributes Objective C property attributes. /// @param PropertyAttributes Objective C property attributes.
DIType createObjCIVar(StringRef Name, DIFile File, DIType createObjCIVar(StringRef Name, DIFile File,
unsigned LineNo, uint64_t SizeInBits, unsigned LineNo, uint64_t SizeInBits,
uint64_t AlignInBits, uint64_t OffsetInBits, uint64_t AlignInBits, uint64_t OffsetInBits,
unsigned Flags, DIType Ty, unsigned Flags, DIType Ty,
StringRef PropertyName = StringRef(), StringRef PropertyName = StringRef(),
StringRef PropertyGetterName = StringRef(), StringRef PropertyGetterName = StringRef(),
StringRef PropertySetterName = StringRef(), StringRef PropertySetterName = StringRef(),
unsigned PropertyAttributes = 0); unsigned PropertyAttributes = 0);
/// createObjCIVar - Create debugging information entry for Objective-C /// createObjCIVar - Create debugging information entry for Objective-C
/// instance variable. /// instance variable.
/// @param Name Member name. /// @param Name Member name.
/// @param File File where this member is defined. /// @param File File where this member is defined.
/// @param LineNo Line number. /// @param LineNo Line number.
/// @param SizeInBits Member size. /// @param SizeInBits Member size.
/// @param AlignInBits Member alignment. /// @param AlignInBits Member alignment.
/// @param OffsetInBits Member offset. /// @param OffsetInBits Member offset.
/// @param Flags Flags to encode member attribute, e.g. private /// @param Flags Flags to encode member attribute, e.g. private
/// @param Ty Parent type. /// @param Ty Parent type.
/// @param Property Property associated with this ivar. /// @param PropertyNode Property associated with this ivar.
DIType createObjCIVar(StringRef Name, DIFile File, DIType createObjCIVar(StringRef Name, DIFile File,
unsigned LineNo, uint64_t SizeInBits, unsigned LineNo, uint64_t SizeInBits,
uint64_t AlignInBits, uint64_t OffsetInBits, uint64_t AlignInBits, uint64_t OffsetInBits,
unsigned Flags, DIType Ty, unsigned Flags, DIType Ty,
MDNode *PropertyNode); MDNode *PropertyNode);
/// createObjCProperty - Create debugging information entry for Objecti ve-C /// createObjCProperty - Create debugging information entry for Objecti ve-C
/// property. /// property.
/// @param Name Property name. /// @param Name Property name.
/// @param File File where this property is defined. /// @param File File where this property is defined.
/// @param LineNumber Line number. /// @param LineNumber Line number.
/// @param GetterName Name of the Objective C property getter selecto r. /// @param GetterName Name of the Objective C property getter selecto r.
/// @param SetterName Name of the Objective C property setter selecto r. /// @param SetterName Name of the Objective C property setter selecto r.
/// @param PropertyAttributes Objective C property attributes. /// @param PropertyAttributes Objective C property attributes.
/// @param Ty Type. /// @param Ty Type.
DIObjCProperty createObjCProperty(StringRef Name, DIObjCProperty createObjCProperty(StringRef Name,
DIFile File, unsigned LineNumber, DIFile File, unsigned LineNumber,
StringRef GetterName, StringRef GetterName,
StringRef SetterName, StringRef SetterName,
unsigned PropertyAttributes, unsigned PropertyAttributes,
DIType Ty); DIType Ty);
/// createClassType - Create debugging information entry for a class. /// createClassType - Create debugging information entry for a class.
/// @param Scope Scope in which this class is defined. /// @param Scope Scope in which this class is defined.
/// @param Name class name. /// @param Name class name.
/// @param File File where this member is defined. /// @param File File where this member is defined.
/// @param LineNo Line number. /// @param LineNumber Line number.
/// @param SizeInBits Member size. /// @param SizeInBits Member size.
/// @param AlignInBits Member alignment. /// @param AlignInBits Member alignment.
/// @param OffsetInBits Member offset. /// @param OffsetInBits Member offset.
/// @param Flags Flags to encode member attribute, e.g. private /// @param Flags Flags to encode member attribute, e.g. private
/// @param Elements class members. /// @param Elements class members.
/// @param VTableHolder Debug info of the base class that contains vtab le /// @param VTableHolder Debug info of the base class that contains vtab le
/// for this type. This is used in /// for this type. This is used in
/// DW_AT_containing_type. See DWARF documentation /// DW_AT_containing_type. See DWARF documentation
/// for more info. /// for more info.
/// @param TemplateParms Template type parameters. /// @param TemplateParms Template type parameters.
skipping to change at line 253 skipping to change at line 255
unsigned LineNumber, uint64_t SizeInBits, unsigned LineNumber, uint64_t SizeInBits,
uint64_t AlignInBits, uint64_t OffsetInBits, uint64_t AlignInBits, uint64_t OffsetInBits,
unsigned Flags, DIType DerivedFrom, unsigned Flags, DIType DerivedFrom,
DIArray Elements, MDNode *VTableHolder = 0, DIArray Elements, MDNode *VTableHolder = 0,
MDNode *TemplateParms = 0); MDNode *TemplateParms = 0);
/// createStructType - Create debugging information entry for a struct. /// createStructType - Create debugging information entry for a struct.
/// @param Scope Scope in which this struct is defined. /// @param Scope Scope in which this struct is defined.
/// @param Name Struct name. /// @param Name Struct name.
/// @param File File where this member is defined. /// @param File File where this member is defined.
/// @param LineNo Line number. /// @param LineNumber Line number.
/// @param SizeInBits Member size. /// @param SizeInBits Member size.
/// @param AlignInBits Member alignment. /// @param AlignInBits Member alignment.
/// @param Flags Flags to encode member attribute, e.g. private /// @param Flags Flags to encode member attribute, e.g. private
/// @param Elements Struct elements. /// @param Elements Struct elements.
/// @param RunTimeLang Optional parameter, Objective-C runtime version . /// @param RunTimeLang Optional parameter, Objective-C runtime version .
DIType createStructType(DIDescriptor Scope, StringRef Name, DIFile File , DIType createStructType(DIDescriptor Scope, StringRef Name, DIFile File ,
unsigned LineNumber, uint64_t SizeInBits, unsigned LineNumber, uint64_t SizeInBits,
uint64_t AlignInBits, unsigned Flags, uint64_t AlignInBits, unsigned Flags,
DIArray Elements, unsigned RunTimeLang = 0); DIArray Elements, unsigned RunTimeLang = 0);
/// createUnionType - Create debugging information entry for an union. /// createUnionType - Create debugging information entry for an union.
/// @param Scope Scope in which this union is defined. /// @param Scope Scope in which this union is defined.
/// @param Name Union name. /// @param Name Union name.
/// @param File File where this member is defined. /// @param File File where this member is defined.
/// @param LineNo Line number. /// @param LineNumber Line number.
/// @param SizeInBits Member size. /// @param SizeInBits Member size.
/// @param AlignInBits Member alignment. /// @param AlignInBits Member alignment.
/// @param Flags Flags to encode member attribute, e.g. private /// @param Flags Flags to encode member attribute, e.g. private
/// @param Elements Union elements. /// @param Elements Union elements.
/// @param RunTimeLang Optional parameter, Objective-C runtime version . /// @param RunTimeLang Optional parameter, Objective-C runtime version .
DIType createUnionType(DIDescriptor Scope, StringRef Name, DIFile File, DIType createUnionType(DIDescriptor Scope, StringRef Name, DIFile File,
unsigned LineNumber, uint64_t SizeInBits, unsigned LineNumber, uint64_t SizeInBits,
uint64_t AlignInBits, unsigned Flags, uint64_t AlignInBits, unsigned Flags,
DIArray Elements, unsigned RunTimeLang = 0); DIArray Elements, unsigned RunTimeLang = 0);
skipping to change at line 328 skipping to change at line 330
/// @param Ty Element type. /// @param Ty Element type.
/// @param Subscripts Subscripts. /// @param Subscripts Subscripts.
DIType createVectorType(uint64_t Size, uint64_t AlignInBits, DIType createVectorType(uint64_t Size, uint64_t AlignInBits,
DIType Ty, DIArray Subscripts); DIType Ty, DIArray Subscripts);
/// createEnumerationType - Create debugging information entry for an /// createEnumerationType - Create debugging information entry for an
/// enumeration. /// enumeration.
/// @param Scope Scope in which this enumeration is defined. /// @param Scope Scope in which this enumeration is defined.
/// @param Name Union name. /// @param Name Union name.
/// @param File File where this member is defined. /// @param File File where this member is defined.
/// @param LineNo Line number. /// @param LineNumber Line number.
/// @param SizeInBits Member size. /// @param SizeInBits Member size.
/// @param AlignInBits Member alignment. /// @param AlignInBits Member alignment.
/// @param Elements Enumeration elements. /// @param Elements Enumeration elements.
DIType createEnumerationType(DIDescriptor Scope, StringRef Name, DIType createEnumerationType(DIDescriptor Scope, StringRef Name,
DIFile File, unsigned LineNumber, DIFile File, unsigned LineNumber,
uint64_t SizeInBits, uint64_t SizeInBits, uint64_t AlignInBits,
uint64_t AlignInBits, DIArray Elements); DIArray Elements, DIType ClassType);
/// createSubroutineType - Create subroutine type. /// createSubroutineType - Create subroutine type.
/// @param File File in which this subroutine is defined. /// @param File File in which this subroutine is defined.
/// @param ParamterTypes An array of subroutine parameter types. This /// @param ParameterTypes An array of subroutine parameter types. This
/// includes return type at 0th index. /// includes return type at 0th index.
DIType createSubroutineType(DIFile File, DIArray ParameterTypes); DIType createSubroutineType(DIFile File, DIArray ParameterTypes);
/// createArtificialType - Create a new DIType with "artificial" flag s et. /// createArtificialType - Create a new DIType with "artificial" flag s et.
DIType createArtificialType(DIType Ty); DIType createArtificialType(DIType Ty);
/// createObjectPointerType - Create a new DIType with the "object poin
ter"
/// flag set.
DIType createObjectPointerType(DIType Ty);
/// createTemporaryType - Create a temporary forward-declared type. /// createTemporaryType - Create a temporary forward-declared type.
DIType createTemporaryType(); DIType createTemporaryType();
DIType createTemporaryType(DIFile F); DIType createTemporaryType(DIFile F);
/// createForwardDecl - Create a temporary forward-declared type. /// createForwardDecl - Create a temporary forward-declared type.
DIType createForwardDecl(unsigned Tag, StringRef Name, DIFile F, DIType createForwardDecl(unsigned Tag, StringRef Name, DIDescriptor Sco
unsigned Line, unsigned RuntimeLang = 0); pe,
DIFile F, unsigned Line, unsigned RuntimeLang
= 0,
uint64_t SizeInBits = 0, uint64_t AlignInBits
= 0);
/// retainType - Retain DIType in a module even if it is not referenced /// retainType - Retain DIType in a module even if it is not referenced
/// through debug info anchors. /// through debug info anchors.
void retainType(DIType T); void retainType(DIType T);
/// createUnspecifiedParameter - Create unspeicified type descriptor /// createUnspecifiedParameter - Create unspeicified type descriptor
/// for a subroutine type. /// for a subroutine type.
DIDescriptor createUnspecifiedParameter(); DIDescriptor createUnspecifiedParameter();
/// getOrCreateArray - Get a DIArray, create one if required. /// getOrCreateArray - Get a DIArray, create one if required.
skipping to change at line 383 skipping to change at line 390
/// @param Ty Variable Type. /// @param Ty Variable Type.
/// @param isLocalToUnit Boolean flag indicate whether this variable is /// @param isLocalToUnit Boolean flag indicate whether this variable is
/// externally visible or not. /// externally visible or not.
/// @param Val llvm::Value of the variable. /// @param Val llvm::Value of the variable.
DIGlobalVariable DIGlobalVariable
createGlobalVariable(StringRef Name, DIFile File, unsigned LineNo, createGlobalVariable(StringRef Name, DIFile File, unsigned LineNo,
DIType Ty, bool isLocalToUnit, llvm::Value *Val); DIType Ty, bool isLocalToUnit, llvm::Value *Val);
/// createStaticVariable - Create a new descriptor for the specified /// createStaticVariable - Create a new descriptor for the specified
/// variable. /// variable.
/// @param Conext Variable scope. /// @param Context Variable scope.
/// @param Name Name of the variable. /// @param Name Name of the variable.
/// @param LinakgeName Mangled name of the variable. /// @param LinkageName Mangled name of the variable.
/// @param File File where this variable is defined. /// @param File File where this variable is defined.
/// @param LineNo Line number. /// @param LineNo Line number.
/// @param Ty Variable Type. /// @param Ty Variable Type.
/// @param isLocalToUnit Boolean flag indicate whether this variable is /// @param isLocalToUnit Boolean flag indicate whether this variable is
/// externally visible or not. /// externally visible or not.
/// @param Val llvm::Value of the variable. /// @param Val llvm::Value of the variable.
DIGlobalVariable DIGlobalVariable
createStaticVariable(DIDescriptor Context, StringRef Name, createStaticVariable(DIDescriptor Context, StringRef Name,
StringRef LinkageName, DIFile File, unsigned LineN o, StringRef LinkageName, DIFile File, unsigned LineN o,
DIType Ty, bool isLocalToUnit, llvm::Value *Val); DIType Ty, bool isLocalToUnit, llvm::Value *Val);
skipping to change at line 424 skipping to change at line 431
DIType Ty, bool AlwaysPreserve = false, DIType Ty, bool AlwaysPreserve = false,
unsigned Flags = 0, unsigned Flags = 0,
unsigned ArgNo = 0); unsigned ArgNo = 0);
/// createComplexVariable - Create a new descriptor for the specified /// createComplexVariable - Create a new descriptor for the specified
/// variable which has a complex address expression for its address. /// variable which has a complex address expression for its address.
/// @param Tag Dwarf TAG. Usually DW_TAG_auto_variable or /// @param Tag Dwarf TAG. Usually DW_TAG_auto_variable or
/// DW_TAG_arg_variable. /// DW_TAG_arg_variable.
/// @param Scope Variable scope. /// @param Scope Variable scope.
/// @param Name Variable name. /// @param Name Variable name.
/// @param File File where this variable is defined. /// @param F File where this variable is defined.
/// @param LineNo Line number. /// @param LineNo Line number.
/// @param Ty Variable Type /// @param Ty Variable Type
/// @param Addr An array of complex address operations. /// @param Addr An array of complex address operations.
/// @param ArgNo If this variable is an arugment then this argume nt's /// @param ArgNo If this variable is an arugment then this argume nt's
/// number. 1 indicates 1st argument. /// number. 1 indicates 1st argument.
DIVariable createComplexVariable(unsigned Tag, DIDescriptor Scope, DIVariable createComplexVariable(unsigned Tag, DIDescriptor Scope,
StringRef Name, DIFile F, unsigned Lin eNo, StringRef Name, DIFile F, unsigned Lin eNo,
DIType Ty, ArrayRef<Value *> Addr, DIType Ty, ArrayRef<Value *> Addr,
unsigned ArgNo = 0); unsigned ArgNo = 0);
 End of changes. 18 change blocks. 
30 lines changed or deleted 39 lines changed or added


 DIContext.h   DIContext.h 
skipping to change at line 18 skipping to change at line 18
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// //
// This file defines DIContext, an abstract data structure that holds // This file defines DIContext, an abstract data structure that holds
// debug information data. // debug information data.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_DEBUGINFO_DICONTEXT_H #ifndef LLVM_DEBUGINFO_DICONTEXT_H
#define LLVM_DEBUGINFO_DICONTEXT_H #define LLVM_DEBUGINFO_DICONTEXT_H
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/SmallString.h"
#include "llvm/ADT/StringRef.h" #include "llvm/ADT/StringRef.h"
#include "llvm/Support/DataTypes.h" #include "llvm/Support/DataTypes.h"
#include <cstring>
namespace llvm { namespace llvm {
class raw_ostream; class raw_ostream;
/// DILineInfo - a format-neutral container for source line information. /// DILineInfo - a format-neutral container for source line information.
class DILineInfo { class DILineInfo {
const char *FileName; SmallString<16> FileName;
SmallString<16> FunctionName;
uint32_t Line; uint32_t Line;
uint32_t Column; uint32_t Column;
public: public:
DILineInfo() : FileName("<invalid>"), Line(0), Column(0) {} DILineInfo()
DILineInfo(const char *fileName, uint32_t line, uint32_t column) : FileName("<invalid>"), FunctionName("<invalid>"),
: FileName(fileName), Line(line), Column(column) {} Line(0), Column(0) {}
DILineInfo(const SmallString<16> &fileName,
const SmallString<16> &functionName,
uint32_t line, uint32_t column)
: FileName(fileName), FunctionName(functionName),
Line(line), Column(column) {}
const char *getFileName() const { return FileName; } const char *getFileName() { return FileName.c_str(); }
const char *getFunctionName() { return FunctionName.c_str(); }
uint32_t getLine() const { return Line; } uint32_t getLine() const { return Line; }
uint32_t getColumn() const { return Column; } uint32_t getColumn() const { return Column; }
bool operator==(const DILineInfo &RHS) const { bool operator==(const DILineInfo &RHS) const {
return Line == RHS.Line && Column == RHS.Column && return Line == RHS.Line && Column == RHS.Column &&
std::strcmp(FileName, RHS.FileName) == 0; FileName.equals(RHS.FileName) &&
FunctionName.equals(RHS.FunctionName);
} }
bool operator!=(const DILineInfo &RHS) const { bool operator!=(const DILineInfo &RHS) const {
return !(*this == RHS); return !(*this == RHS);
} }
}; };
/// DIInliningInfo - a format-neutral container for inlined code descriptio
n.
class DIInliningInfo {
SmallVector<DILineInfo, 4> Frames;
public:
DIInliningInfo() {}
DILineInfo getFrame(unsigned Index) const {
assert(Index < Frames.size());
return Frames[Index];
}
uint32_t getNumberOfFrames() const {
return Frames.size();
}
void addFrame(const DILineInfo &Frame) {
Frames.push_back(Frame);
}
};
/// DILineInfoSpecifier - controls which fields of DILineInfo container
/// should be filled with data.
class DILineInfoSpecifier {
const uint32_t Flags; // Or'ed flags that set the info we want to fetch.
public:
enum Specification {
FileLineInfo = 1 << 0,
AbsoluteFilePath = 1 << 1,
FunctionName = 1 << 2
};
// Use file/line info by default.
DILineInfoSpecifier(uint32_t flags = FileLineInfo) : Flags(flags) {}
bool needs(Specification spec) const {
return (Flags & spec) > 0;
}
};
// In place of applying the relocations to the data we've read from disk we
use
// a separate mapping table to the side and checking that at locations in t
he
// dwarf where we expect relocated values. This adds a bit of complexity to
the
// dwarf parsing/extraction at the benefit of not allocating memory for the
// entire size of the debug info sections.
typedef DenseMap<uint64_t, std::pair<uint8_t, int64_t> > RelocAddrMap;
class DIContext { class DIContext {
public: public:
virtual ~DIContext(); virtual ~DIContext();
/// getDWARFContext - get a context for binary DWARF data. /// getDWARFContext - get a context for binary DWARF data.
static DIContext *getDWARFContext(bool isLittleEndian, static DIContext *getDWARFContext(bool isLittleEndian,
StringRef infoSection, StringRef infoSection,
StringRef abbrevSection, StringRef abbrevSection,
StringRef aRangeSection = StringRef(), StringRef aRangeSection = StringRef(),
StringRef lineSection = StringRef(), StringRef lineSection = StringRef(),
StringRef stringSection = StringRef()); StringRef stringSection = StringRef(),
StringRef rangeSection = StringRef(),
const RelocAddrMap &Map = RelocAddrMap(
));
virtual void dump(raw_ostream &OS) = 0; virtual void dump(raw_ostream &OS) = 0;
virtual DILineInfo getLineInfoForAddress(uint64_t address) = 0; virtual DILineInfo getLineInfoForAddress(uint64_t Address,
DILineInfoSpecifier Specifier = DILineInfoSpecifier()) = 0;
virtual DIInliningInfo getInliningInfoForAddress(uint64_t Address,
DILineInfoSpecifier Specifier = DILineInfoSpecifier()) = 0;
}; };
} }
#endif #endif
 End of changes. 9 change blocks. 
9 lines changed or deleted 70 lines changed or added


 DataExtractor.h   DataExtractor.h 
skipping to change at line 13 skipping to change at line 13
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
// //
// This file is distributed under the University of Illinois Open Source // This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details. // License. See LICENSE.TXT for details.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_SUPPORT_DATAEXTRACTOR_H #ifndef LLVM_SUPPORT_DATAEXTRACTOR_H
#define LLVM_SUPPORT_DATAEXTRACTOR_H #define LLVM_SUPPORT_DATAEXTRACTOR_H
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/StringRef.h" #include "llvm/ADT/StringRef.h"
#include "llvm/Support/DataTypes.h" #include "llvm/Support/DataTypes.h"
namespace llvm { namespace llvm {
class DataExtractor { class DataExtractor {
StringRef Data; StringRef Data;
uint8_t IsLittleEndian; uint8_t IsLittleEndian;
uint8_t PointerSize; uint8_t PointerSize;
public: public:
/// Construct with a buffer that is owned by the caller. /// Construct with a buffer that is owned by the caller.
skipping to change at line 102 skipping to change at line 103
/// bits wide. Any \a byte_size values less than 1 or greater than /// bits wide. Any \a byte_size values less than 1 or greater than
/// 8 will result in nothing being extracted, and zero being returned. /// 8 will result in nothing being extracted, and zero being returned.
/// ///
/// @param[in,out] offset_ptr /// @param[in,out] offset_ptr
/// A pointer to an offset within the data that will be advanced /// A pointer to an offset within the data that will be advanced
/// by the appropriate number of bytes if the value is extracted /// by the appropriate number of bytes if the value is extracted
/// correctly. If the offset is out of bounds or there are not /// correctly. If the offset is out of bounds or there are not
/// enough bytes to extract this value, the offset will be left /// enough bytes to extract this value, the offset will be left
/// unmodified. /// unmodified.
/// ///
/// @param[in] byte_size /// @param[in] size
/// The size in byte of the integer to extract. /// The size in bytes of the integer to extract.
/// ///
/// @return /// @return
/// The sign extended signed integer value that was extracted, /// The sign extended signed integer value that was extracted,
/// or zero on failure. /// or zero on failure.
int64_t getSigned(uint32_t *offset_ptr, uint32_t size) const; int64_t getSigned(uint32_t *offset_ptr, uint32_t size) const;
//------------------------------------------------------------------ //------------------------------------------------------------------
/// Extract an pointer from \a *offset_ptr. /// Extract an pointer from \a *offset_ptr.
/// ///
/// Extract a single pointer from the data and update the offset /// Extract a single pointer from the data and update the offset
 End of changes. 2 change blocks. 
2 lines changed or deleted 3 lines changed or added


 DataTypes.h   DataTypes.h 
skipping to change at line 83 skipping to change at line 83
/* Handle incorrect definition of uint64_t as u_int64_t */ /* Handle incorrect definition of uint64_t as u_int64_t */
#ifndef HAVE_UINT64_T #ifndef HAVE_UINT64_T
#ifdef HAVE_U_INT64_T #ifdef HAVE_U_INT64_T
typedef u_int64_t uint64_t; typedef u_int64_t uint64_t;
#else #else
# error "Don't have a definition for uint64_t on this platform" # error "Don't have a definition for uint64_t on this platform"
#endif #endif
#endif #endif
#ifdef _OpenBSD_
#define INT8_MAX 127
#define INT8_MIN -128
#define UINT8_MAX 255
#define INT16_MAX 32767
#define INT16_MIN -32768
#define UINT16_MAX 65535
#define INT32_MAX 2147483647
#define INT32_MIN -2147483648
#define UINT32_MAX 4294967295U
#endif
#else /* _MSC_VER */ #else /* _MSC_VER */
/* Visual C++ doesn't provide standard integer headers, but it does provide /* Visual C++ doesn't provide standard integer headers, but it does provide
built-in data types. */ built-in data types. */
#include <stdlib.h> #include <stdlib.h>
#include <stddef.h> #include <stddef.h>
#include <sys/types.h> #include <sys/types.h>
#ifdef __cplusplus #ifdef __cplusplus
#include <cmath> #include <cmath>
#else #else
#include <math.h> #include <math.h>
 End of changes. 1 change blocks. 
12 lines changed or deleted 0 lines changed or added


 Debug.h   Debug.h 
skipping to change at line 22 skipping to change at line 22
// command line options to enable it. // command line options to enable it.
// //
// In particular, just wrap your code with the DEBUG() macro, and it will b e // In particular, just wrap your code with the DEBUG() macro, and it will b e
// enabled automatically if you specify '-debug' on the command-line. // enabled automatically if you specify '-debug' on the command-line.
// Alternatively, you can also use the SET_DEBUG_TYPE("foo") macro to speci fy // Alternatively, you can also use the SET_DEBUG_TYPE("foo") macro to speci fy
// that your debug code belongs to class "foo". Then, on the command line, you // that your debug code belongs to class "foo". Then, on the command line, you
// can specify '-debug-only=foo' to enable JUST the debug information for t he // can specify '-debug-only=foo' to enable JUST the debug information for t he
// foo class. // foo class.
// //
// When compiling without assertions, the -debug-* options and all code in // When compiling without assertions, the -debug-* options and all code in
// DEBUG() statements disappears, so it does not effect the runtime of the code. // DEBUG() statements disappears, so it does not affect the runtime of the code.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_SUPPORT_DEBUG_H #ifndef LLVM_SUPPORT_DEBUG_H
#define LLVM_SUPPORT_DEBUG_H #define LLVM_SUPPORT_DEBUG_H
namespace llvm { namespace llvm {
class raw_ostream; class raw_ostream;
skipping to change at line 52 skipping to change at line 52
/// the DEBUG macro below. /// the DEBUG macro below.
/// ///
extern bool DebugFlag; extern bool DebugFlag;
/// isCurrentDebugType - Return true if the specified string is the debug t ype /// isCurrentDebugType - Return true if the specified string is the debug t ype
/// specified on the command line, or if none was specified on the command line /// specified on the command line, or if none was specified on the command line
/// with the -debug-only=X option. /// with the -debug-only=X option.
/// ///
bool isCurrentDebugType(const char *Type); bool isCurrentDebugType(const char *Type);
/// SetCurrentDebugType - Set the current debug type, as if the -debug-only =X /// setCurrentDebugType - Set the current debug type, as if the -debug-only =X
/// option were specified. Note that DebugFlag also needs to be set to tru e for /// option were specified. Note that DebugFlag also needs to be set to tru e for
/// debug output to be produced. /// debug output to be produced.
/// ///
void SetCurrentDebugType(const char *Type); void setCurrentDebugType(const char *Type);
/// DEBUG_WITH_TYPE macro - This macro should be used by passes to emit deb ug /// DEBUG_WITH_TYPE macro - This macro should be used by passes to emit deb ug
/// information. In the '-debug' option is specified on the commandline, a nd if /// information. In the '-debug' option is specified on the commandline, a nd if
/// this is a debug build, then the code specified as the option to the mac ro /// this is a debug build, then the code specified as the option to the mac ro
/// will be executed. Otherwise it will not be. Example: /// will be executed. Otherwise it will not be. Example:
/// ///
/// DEBUG_WITH_TYPE("bitset", dbgs() << "Bitset contains: " << Bitset << "\ n"); /// DEBUG_WITH_TYPE("bitset", dbgs() << "Bitset contains: " << Bitset << "\ n");
/// ///
/// This will emit the debug information if -debug is present, and -debug-o nly /// This will emit the debug information if -debug is present, and -debug-o nly
/// is not specified, or is specified as "bitset". /// is not specified, or is specified as "bitset".
#define DEBUG_WITH_TYPE(TYPE, X) \ #define DEBUG_WITH_TYPE(TYPE, X) \
do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType(TYPE)) { X; } \ do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType(TYPE)) { X; } \
} while (0) } while (0)
#else #else
#define isCurrentDebugType(X) (false) #define isCurrentDebugType(X) (false)
#define SetCurrentDebugType(X) #define setCurrentDebugType(X)
#define DEBUG_WITH_TYPE(TYPE, X) do { } while (0) #define DEBUG_WITH_TYPE(TYPE, X) do { } while (0)
#endif #endif
/// EnableDebugBuffering - This defaults to false. If true, the debug /// EnableDebugBuffering - This defaults to false. If true, the debug
/// stream will install signal handlers to dump any buffered debug /// stream will install signal handlers to dump any buffered debug
/// output. It allows clients to selectively allow the debug stream /// output. It allows clients to selectively allow the debug stream
/// to install signal handlers if they are certain there will be no /// to install signal handlers if they are certain there will be no
/// conflict. /// conflict.
/// ///
extern bool EnableDebugBuffering; extern bool EnableDebugBuffering;
 End of changes. 4 change blocks. 
4 lines changed or deleted 4 lines changed or added


 DebugInfo.h   DebugInfo.h 
skipping to change at line 49 skipping to change at line 49
class DIFile; class DIFile;
class DISubprogram; class DISubprogram;
class DILexicalBlock; class DILexicalBlock;
class DILexicalBlockFile; class DILexicalBlockFile;
class DIVariable; class DIVariable;
class DIType; class DIType;
class DIObjCProperty; class DIObjCProperty;
/// DIDescriptor - A thin wraper around MDNode to access encoded debug in fo. /// DIDescriptor - A thin wraper around MDNode to access encoded debug in fo.
/// This should not be stored in a container, because underly MDNode may /// This should not be stored in a container, because the underlying MDNo
/// change in certain situations. de
/// may change in certain situations.
class DIDescriptor { class DIDescriptor {
public: public:
enum { enum {
FlagPrivate = 1 << 0, FlagPrivate = 1 << 0,
FlagProtected = 1 << 1, FlagProtected = 1 << 1,
FlagFwdDecl = 1 << 2, FlagFwdDecl = 1 << 2,
FlagAppleBlock = 1 << 3, FlagAppleBlock = 1 << 3,
FlagBlockByrefStruct = 1 << 4, FlagBlockByrefStruct = 1 << 4,
FlagVirtual = 1 << 5, FlagVirtual = 1 << 5,
FlagArtificial = 1 << 6, FlagArtificial = 1 << 6,
FlagExplicit = 1 << 7, FlagExplicit = 1 << 7,
FlagPrototyped = 1 << 8, FlagPrototyped = 1 << 8,
FlagObjcClassComplete = 1 << 9 FlagObjcClassComplete = 1 << 9,
FlagObjectPointer = 1 << 10
}; };
protected: protected:
const MDNode *DbgNode; const MDNode *DbgNode;
StringRef getStringField(unsigned Elt) const; StringRef getStringField(unsigned Elt) const;
unsigned getUnsignedField(unsigned Elt) const { unsigned getUnsignedField(unsigned Elt) const {
return (unsigned)getUInt64Field(Elt); return (unsigned)getUInt64Field(Elt);
} }
uint64_t getUInt64Field(unsigned Elt) const; uint64_t getUInt64Field(unsigned Elt) const;
DIDescriptor getDescriptorField(unsigned Elt) const; DIDescriptor getDescriptorField(unsigned Elt) const;
template <typename DescTy> template <typename DescTy>
DescTy getFieldAs(unsigned Elt) const { DescTy getFieldAs(unsigned Elt) const {
return DescTy(getDescriptorField(Elt)); return DescTy(getDescriptorField(Elt));
} }
GlobalVariable *getGlobalVariableField(unsigned Elt) const; GlobalVariable *getGlobalVariableField(unsigned Elt) const;
Constant *getConstantField(unsigned Elt) const; Constant *getConstantField(unsigned Elt) const;
Function *getFunctionField(unsigned Elt) const; Function *getFunctionField(unsigned Elt) const;
void replaceFunctionField(unsigned Elt, Function *F);
public: public:
explicit DIDescriptor() : DbgNode(0) {} explicit DIDescriptor() : DbgNode(0) {}
explicit DIDescriptor(const MDNode *N) : DbgNode(N) {} explicit DIDescriptor(const MDNode *N) : DbgNode(N) {}
explicit DIDescriptor(const DIFile F); explicit DIDescriptor(const DIFile F);
explicit DIDescriptor(const DISubprogram F); explicit DIDescriptor(const DISubprogram F);
explicit DIDescriptor(const DILexicalBlockFile F); explicit DIDescriptor(const DILexicalBlockFile F);
explicit DIDescriptor(const DILexicalBlock F); explicit DIDescriptor(const DILexicalBlock F);
explicit DIDescriptor(const DIVariable F); explicit DIDescriptor(const DIVariable F);
explicit DIDescriptor(const DIType F); explicit DIDescriptor(const DIType F);
skipping to change at line 107 skipping to change at line 109
MDNode *operator ->() const { return const_cast<MDNode*>(DbgNode); } MDNode *operator ->() const { return const_cast<MDNode*>(DbgNode); }
unsigned getVersion() const { unsigned getVersion() const {
return getUnsignedField(0) & LLVMDebugVersionMask; return getUnsignedField(0) & LLVMDebugVersionMask;
} }
unsigned getTag() const { unsigned getTag() const {
return getUnsignedField(0) & ~LLVMDebugVersionMask; return getUnsignedField(0) & ~LLVMDebugVersionMask;
} }
/// print - print descriptor.
void print(raw_ostream &OS) const;
/// dump - print descriptor to dbgs() with a newline.
void dump() const;
bool isDerivedType() const; bool isDerivedType() const;
bool isCompositeType() const; bool isCompositeType() const;
bool isBasicType() const; bool isBasicType() const;
bool isVariable() const; bool isVariable() const;
bool isSubprogram() const; bool isSubprogram() const;
bool isGlobalVariable() const; bool isGlobalVariable() const;
bool isScope() const; bool isScope() const;
bool isFile() const; bool isFile() const;
bool isCompileUnit() const; bool isCompileUnit() const;
bool isNameSpace() const; bool isNameSpace() const;
bool isLexicalBlockFile() const; bool isLexicalBlockFile() const;
bool isLexicalBlock() const; bool isLexicalBlock() const;
bool isSubrange() const; bool isSubrange() const;
bool isEnumerator() const; bool isEnumerator() const;
bool isType() const; bool isType() const;
bool isGlobal() const; bool isGlobal() const;
bool isUnspecifiedParameter() const; bool isUnspecifiedParameter() const;
bool isTemplateTypeParameter() const; bool isTemplateTypeParameter() const;
bool isTemplateValueParameter() const; bool isTemplateValueParameter() const;
bool isObjCProperty() const; bool isObjCProperty() const;
/// print - print descriptor.
void print(raw_ostream &OS) const;
/// dump - print descriptor to dbgs() with a newline.
void dump() const;
}; };
/// DISubrange - This is used to represent ranges, for array bounds. /// DISubrange - This is used to represent ranges, for array bounds.
class DISubrange : public DIDescriptor { class DISubrange : public DIDescriptor {
friend class DIDescriptor;
void printInternal(raw_ostream &OS) const;
public: public:
explicit DISubrange(const MDNode *N = 0) : DIDescriptor(N) {} explicit DISubrange(const MDNode *N = 0) : DIDescriptor(N) {}
uint64_t getLo() const { return getUInt64Field(1); } uint64_t getLo() const { return getUInt64Field(1); }
uint64_t getHi() const { return getUInt64Field(2); } uint64_t getHi() const { return getUInt64Field(2); }
}; };
/// DIArray - This descriptor holds an array of descriptors. /// DIArray - This descriptor holds an array of descriptors.
class DIArray : public DIDescriptor { class DIArray : public DIDescriptor {
public: public:
skipping to change at line 158 skipping to change at line 162
: DIDescriptor(N) {} : DIDescriptor(N) {}
unsigned getNumElements() const; unsigned getNumElements() const;
DIDescriptor getElement(unsigned Idx) const { DIDescriptor getElement(unsigned Idx) const {
return getDescriptorField(Idx); return getDescriptorField(Idx);
} }
}; };
/// DIScope - A base class for various scopes. /// DIScope - A base class for various scopes.
class DIScope : public DIDescriptor { class DIScope : public DIDescriptor {
virtual void anchor(); protected:
friend class DIDescriptor;
void printInternal(raw_ostream &OS) const;
public: public:
explicit DIScope(const MDNode *N = 0) : DIDescriptor (N) {} explicit DIScope(const MDNode *N = 0) : DIDescriptor (N) {}
virtual ~DIScope() {}
StringRef getFilename() const; StringRef getFilename() const;
StringRef getDirectory() const; StringRef getDirectory() const;
}; };
/// DICompileUnit - A wrapper for a compile unit. /// DICompileUnit - A wrapper for a compile unit.
class DICompileUnit : public DIScope { class DICompileUnit : public DIScope {
virtual void anchor(); friend class DIDescriptor;
void printInternal(raw_ostream &OS) const;
public: public:
explicit DICompileUnit(const MDNode *N = 0) : DIScope(N) {} explicit DICompileUnit(const MDNode *N = 0) : DIScope(N) {}
unsigned getLanguage() const { return getUnsignedField(2); } unsigned getLanguage() const { return getUnsignedField(2); }
StringRef getFilename() const { return getStringField(3); } StringRef getFilename() const { return getStringField(3); }
StringRef getDirectory() const { return getStringField(4); } StringRef getDirectory() const { return getStringField(4); }
StringRef getProducer() const { return getStringField(5); } StringRef getProducer() const { return getStringField(5); }
/// isMain - Each input file is encoded as a separate compile unit in L LVM /// isMain - Each input file is encoded as a separate compile unit in L LVM
/// debugging information output. However, many target specific tool ch ains /// debugging information output. However, many target specific tool ch ains
skipping to change at line 199 skipping to change at line 205
StringRef getFlags() const { return getStringField(8); } StringRef getFlags() const { return getStringField(8); }
unsigned getRunTimeVersion() const { return getUnsignedField(9); } unsigned getRunTimeVersion() const { return getUnsignedField(9); }
DIArray getEnumTypes() const; DIArray getEnumTypes() const;
DIArray getRetainedTypes() const; DIArray getRetainedTypes() const;
DIArray getSubprograms() const; DIArray getSubprograms() const;
DIArray getGlobalVariables() const; DIArray getGlobalVariables() const;
/// Verify - Verify that a compile unit is well formed. /// Verify - Verify that a compile unit is well formed.
bool Verify() const; bool Verify() const;
/// print - print compile unit.
void print(raw_ostream &OS) const;
/// dump - print compile unit to dbgs() with a newline.
void dump() const;
}; };
/// DIFile - This is a wrapper for a file. /// DIFile - This is a wrapper for a file.
class DIFile : public DIScope { class DIFile : public DIScope {
virtual void anchor(); friend class DIDescriptor;
void printInternal(raw_ostream &OS) const {} // FIXME: Output something
?
public: public:
explicit DIFile(const MDNode *N = 0) : DIScope(N) { explicit DIFile(const MDNode *N = 0) : DIScope(N) {
if (DbgNode && !isFile()) if (DbgNode && !isFile())
DbgNode = 0; DbgNode = 0;
} }
StringRef getFilename() const { return getStringField(1); } StringRef getFilename() const { return getStringField(1); }
StringRef getDirectory() const { return getStringField(2); } StringRef getDirectory() const { return getStringField(2); }
DICompileUnit getCompileUnit() const{ DICompileUnit getCompileUnit() const{
assert (getVersion() <= LLVMDebugVersion10 && "Invalid CompileUnit!" ); assert (getVersion() <= LLVMDebugVersion10 && "Invalid CompileUnit!" );
return getFieldAs<DICompileUnit>(3); return getFieldAs<DICompileUnit>(3);
} }
}; };
/// DIEnumerator - A wrapper for an enumerator (e.g. X and Y in 'enum {X, Y}'). /// DIEnumerator - A wrapper for an enumerator (e.g. X and Y in 'enum {X, Y}').
/// FIXME: it seems strange that this doesn't have either a reference to the /// FIXME: it seems strange that this doesn't have either a reference to the
/// type/precision or a file/line pair for location info. /// type/precision or a file/line pair for location info.
class DIEnumerator : public DIDescriptor { class DIEnumerator : public DIDescriptor {
friend class DIDescriptor;
void printInternal(raw_ostream &OS) const;
public: public:
explicit DIEnumerator(const MDNode *N = 0) : DIDescriptor(N) {} explicit DIEnumerator(const MDNode *N = 0) : DIDescriptor(N) {}
StringRef getName() const { return getStringField(1); } StringRef getName() const { return getStringField(1); }
uint64_t getEnumValue() const { return getUInt64Field(2); } uint64_t getEnumValue() const { return getUInt64Field(2); }
}; };
/// DIType - This is a wrapper for a type. /// DIType - This is a wrapper for a type.
/// FIXME: Types should be factored much better so that CV qualifiers and /// FIXME: Types should be factored much better so that CV qualifiers and
/// others do not require a huge and empty descriptor full of zeros. /// others do not require a huge and empty descriptor full of zeros.
class DIType : public DIScope { class DIType : public DIScope {
virtual void anchor();
protected: protected:
friend class DIDescriptor;
void printInternal(raw_ostream &OS) const;
// This ctor is used when the Tag has already been validated by a deriv ed // This ctor is used when the Tag has already been validated by a deriv ed
// ctor. // ctor.
DIType(const MDNode *N, bool, bool) : DIScope(N) {} DIType(const MDNode *N, bool, bool) : DIScope(N) {}
public: public:
/// Verify - Verify that a type descriptor is well formed. /// Verify - Verify that a type descriptor is well formed.
bool Verify() const; bool Verify() const;
explicit DIType(const MDNode *N); explicit DIType(const MDNode *N);
explicit DIType() {} explicit DIType() {}
virtual ~DIType() {}
DIScope getContext() const { return getFieldAs<DIScope>(1); } DIScope getContext() const { return getFieldAs<DIScope>(1); }
StringRef getName() const { return getStringField(2); } StringRef getName() const { return getStringField(2); }
DICompileUnit getCompileUnit() const{ DICompileUnit getCompileUnit() const{
assert (getVersion() <= LLVMDebugVersion10 && "Invalid getCompileUnit !"); assert (getVersion() <= LLVMDebugVersion10 && "Invalid getCompileUnit !");
if (getVersion() == llvm::LLVMDebugVersion7) if (getVersion() == llvm::LLVMDebugVersion7)
return getFieldAs<DICompileUnit>(3); return getFieldAs<DICompileUnit>(3);
return getFieldAs<DIFile>(3).getCompileUnit(); return getFieldAs<DIFile>(3).getCompileUnit();
} }
skipping to change at line 291 skipping to change at line 292
} }
bool isBlockByrefStruct() const { bool isBlockByrefStruct() const {
return (getFlags() & FlagBlockByrefStruct) != 0; return (getFlags() & FlagBlockByrefStruct) != 0;
} }
bool isVirtual() const { bool isVirtual() const {
return (getFlags() & FlagVirtual) != 0; return (getFlags() & FlagVirtual) != 0;
} }
bool isArtificial() const { bool isArtificial() const {
return (getFlags() & FlagArtificial) != 0; return (getFlags() & FlagArtificial) != 0;
} }
bool isObjectPointer() const {
return (getFlags() & FlagObjectPointer) != 0;
}
bool isObjcClassComplete() const { bool isObjcClassComplete() const {
return (getFlags() & FlagObjcClassComplete) != 0; return (getFlags() & FlagObjcClassComplete) != 0;
} }
bool isValid() const { bool isValid() const {
return DbgNode && (isBasicType() || isDerivedType() || isCompositeTyp e()); return DbgNode && (isBasicType() || isDerivedType() || isCompositeTyp e());
} }
StringRef getDirectory() const { StringRef getDirectory() const {
if (getVersion() == llvm::LLVMDebugVersion7) if (getVersion() == llvm::LLVMDebugVersion7)
return getCompileUnit().getDirectory(); return getCompileUnit().getDirectory();
skipping to change at line 317 skipping to change at line 321
return getFieldAs<DIFile>(3).getFilename(); return getFieldAs<DIFile>(3).getFilename();
} }
/// isUnsignedDIType - Return true if type encoding is unsigned. /// isUnsignedDIType - Return true if type encoding is unsigned.
bool isUnsignedDIType(); bool isUnsignedDIType();
/// replaceAllUsesWith - Replace all uses of debug info referenced by /// replaceAllUsesWith - Replace all uses of debug info referenced by
/// this descriptor. /// this descriptor.
void replaceAllUsesWith(DIDescriptor &D); void replaceAllUsesWith(DIDescriptor &D);
void replaceAllUsesWith(MDNode *D); void replaceAllUsesWith(MDNode *D);
/// print - print type.
void print(raw_ostream &OS) const;
/// dump - print type to dbgs() with a newline.
void dump() const;
}; };
/// DIBasicType - A basic type, like 'int' or 'float'. /// DIBasicType - A basic type, like 'int' or 'float'.
class DIBasicType : public DIType { class DIBasicType : public DIType {
virtual void anchor();
public: public:
explicit DIBasicType(const MDNode *N = 0) : DIType(N) {} explicit DIBasicType(const MDNode *N = 0) : DIType(N) {}
unsigned getEncoding() const { return getUnsignedField(9); } unsigned getEncoding() const { return getUnsignedField(9); }
/// Verify - Verify that a basic type descriptor is well formed. /// Verify - Verify that a basic type descriptor is well formed.
bool Verify() const; bool Verify() const;
/// print - print basic type.
void print(raw_ostream &OS) const;
/// dump - print basic type to dbgs() with a newline.
void dump() const;
}; };
/// DIDerivedType - A simple derived type, like a const qualified type, /// DIDerivedType - A simple derived type, like a const qualified type,
/// a typedef, a pointer or reference, etc. /// a typedef, a pointer or reference, etc.
class DIDerivedType : public DIType { class DIDerivedType : public DIType {
virtual void anchor(); friend class DIDescriptor;
void printInternal(raw_ostream &OS) const;
protected: protected:
explicit DIDerivedType(const MDNode *N, bool, bool) explicit DIDerivedType(const MDNode *N, bool, bool)
: DIType(N, true, true) {} : DIType(N, true, true) {}
public: public:
explicit DIDerivedType(const MDNode *N = 0) explicit DIDerivedType(const MDNode *N = 0)
: DIType(N, true, true) {} : DIType(N, true, true) {}
DIType getTypeDerivedFrom() const { return getFieldAs<DIType>(9); } DIType getTypeDerivedFrom() const { return getFieldAs<DIType>(9); }
/// getOriginalTypeSize - If this type is derived from a base type then /// getOriginalTypeSize - If this type is derived from a base type then
skipping to change at line 404 skipping to change at line 396
assert (getVersion() <= LLVMDebugVersion11 && "Invalid Request"); assert (getVersion() <= LLVMDebugVersion11 && "Invalid Request");
return (getUnsignedField(13) & dwarf::DW_APPLE_PROPERTY_copy) != 0; return (getUnsignedField(13) & dwarf::DW_APPLE_PROPERTY_copy) != 0;
} }
bool isNonAtomicObjCProperty() { bool isNonAtomicObjCProperty() {
assert (getVersion() <= LLVMDebugVersion11 && "Invalid Request"); assert (getVersion() <= LLVMDebugVersion11 && "Invalid Request");
return (getUnsignedField(13) & dwarf::DW_APPLE_PROPERTY_nonatomic) != 0; return (getUnsignedField(13) & dwarf::DW_APPLE_PROPERTY_nonatomic) != 0;
} }
/// Verify - Verify that a derived type descriptor is well formed. /// Verify - Verify that a derived type descriptor is well formed.
bool Verify() const; bool Verify() const;
/// print - print derived type.
void print(raw_ostream &OS) const;
/// dump - print derived type to dbgs() with a newline.
void dump() const;
}; };
/// DICompositeType - This descriptor holds a type that can refer to mult iple /// DICompositeType - This descriptor holds a type that can refer to mult iple
/// other types, like a function or struct. /// other types, like a function or struct.
/// FIXME: Why is this a DIDerivedType?? /// FIXME: Why is this a DIDerivedType??
class DICompositeType : public DIDerivedType { class DICompositeType : public DIDerivedType {
virtual void anchor(); friend class DIDescriptor;
void printInternal(raw_ostream &OS) const;
public: public:
explicit DICompositeType(const MDNode *N = 0) explicit DICompositeType(const MDNode *N = 0)
: DIDerivedType(N, true, true) { : DIDerivedType(N, true, true) {
if (N && !isCompositeType()) if (N && !isCompositeType())
DbgNode = 0; DbgNode = 0;
} }
DIArray getTypeArray() const { return getFieldAs<DIArray>(10); } DIArray getTypeArray() const { return getFieldAs<DIArray>(10); }
unsigned getRunTimeLang() const { return getUnsignedField(11); } unsigned getRunTimeLang() const { return getUnsignedField(11); }
DICompositeType getContainingType() const { DICompositeType getContainingType() const {
return getFieldAs<DICompositeType>(12); return getFieldAs<DICompositeType>(12);
} }
DIArray getTemplateParams() const { return getFieldAs<DIArray>(13); } DIArray getTemplateParams() const { return getFieldAs<DIArray>(13); }
/// Verify - Verify that a composite type descriptor is well formed. /// Verify - Verify that a composite type descriptor is well formed.
bool Verify() const; bool Verify() const;
/// print - print composite type.
void print(raw_ostream &OS) const;
/// dump - print composite type to dbgs() with a newline.
void dump() const;
}; };
/// DITemplateTypeParameter - This is a wrapper for template type paramet er. /// DITemplateTypeParameter - This is a wrapper for template type paramet er.
class DITemplateTypeParameter : public DIDescriptor { class DITemplateTypeParameter : public DIDescriptor {
public: public:
explicit DITemplateTypeParameter(const MDNode *N = 0) : DIDescriptor(N) {} explicit DITemplateTypeParameter(const MDNode *N = 0) : DIDescriptor(N) {}
DIScope getContext() const { return getFieldAs<DIScope>(1); } DIScope getContext() const { return getFieldAs<DIScope>(1); }
StringRef getName() const { return getStringField(2); } StringRef getName() const { return getStringField(2); }
DIType getType() const { return getFieldAs<DIType>(3); } DIType getType() const { return getFieldAs<DIType>(3); }
skipping to change at line 480 skipping to change at line 461
} }
StringRef getDirectory() const { StringRef getDirectory() const {
return getFieldAs<DIFile>(5).getDirectory(); return getFieldAs<DIFile>(5).getDirectory();
} }
unsigned getLineNumber() const { return getUnsignedField(6); } unsigned getLineNumber() const { return getUnsignedField(6); }
unsigned getColumnNumber() const { return getUnsignedField(7); } unsigned getColumnNumber() const { return getUnsignedField(7); }
}; };
/// DISubprogram - This is a wrapper for a subprogram (e.g. a function). /// DISubprogram - This is a wrapper for a subprogram (e.g. a function).
class DISubprogram : public DIScope { class DISubprogram : public DIScope {
virtual void anchor(); friend class DIDescriptor;
void printInternal(raw_ostream &OS) const;
public: public:
explicit DISubprogram(const MDNode *N = 0) : DIScope(N) {} explicit DISubprogram(const MDNode *N = 0) : DIScope(N) {}
DIScope getContext() const { return getFieldAs<DIScope>(2); } DIScope getContext() const { return getFieldAs<DIScope>(2); }
StringRef getName() const { return getStringField(3); } StringRef getName() const { return getStringField(3); }
StringRef getDisplayName() const { return getStringField(4); } StringRef getDisplayName() const { return getStringField(4); }
StringRef getLinkageName() const { return getStringField(5); } StringRef getLinkageName() const { return getStringField(5); }
DICompileUnit getCompileUnit() const{ DICompileUnit getCompileUnit() const{
assert (getVersion() <= LLVMDebugVersion10 && "Invalid getCompileUnit !"); assert (getVersion() <= LLVMDebugVersion10 && "Invalid getCompileUnit !");
if (getVersion() == llvm::LLVMDebugVersion7) if (getVersion() == llvm::LLVMDebugVersion7)
skipping to change at line 579 skipping to change at line 561
} }
/// getScopeLineNumber - Get the beginning of the scope of the /// getScopeLineNumber - Get the beginning of the scope of the
/// function, not necessarily where the name of the program /// function, not necessarily where the name of the program
/// starts. /// starts.
unsigned getScopeLineNumber() const { return getUnsignedField(20); } unsigned getScopeLineNumber() const { return getUnsignedField(20); }
/// Verify - Verify that a subprogram descriptor is well formed. /// Verify - Verify that a subprogram descriptor is well formed.
bool Verify() const; bool Verify() const;
/// print - print subprogram.
void print(raw_ostream &OS) const;
/// dump - print subprogram to dbgs() with a newline.
void dump() const;
/// describes - Return true if this subprogram provides debugging /// describes - Return true if this subprogram provides debugging
/// information for the function F. /// information for the function F.
bool describes(const Function *F); bool describes(const Function *F);
Function *getFunction() const { return getFunctionField(16); } Function *getFunction() const { return getFunctionField(16); }
void replaceFunction(Function *F) { replaceFunctionField(16, F); }
DIArray getTemplateParams() const { return getFieldAs<DIArray>(17); } DIArray getTemplateParams() const { return getFieldAs<DIArray>(17); }
DISubprogram getFunctionDeclaration() const { DISubprogram getFunctionDeclaration() const {
return getFieldAs<DISubprogram>(18); return getFieldAs<DISubprogram>(18);
} }
MDNode *getVariablesNodes() const; MDNode *getVariablesNodes() const;
DIArray getVariables() const; DIArray getVariables() const;
}; };
/// DIGlobalVariable - This is a wrapper for a global variable. /// DIGlobalVariable - This is a wrapper for a global variable.
class DIGlobalVariable : public DIDescriptor { class DIGlobalVariable : public DIDescriptor {
friend class DIDescriptor;
void printInternal(raw_ostream &OS) const;
public: public:
explicit DIGlobalVariable(const MDNode *N = 0) : DIDescriptor(N) {} explicit DIGlobalVariable(const MDNode *N = 0) : DIDescriptor(N) {}
DIScope getContext() const { return getFieldAs<DIScope>(2); } DIScope getContext() const { return getFieldAs<DIScope>(2); }
StringRef getName() const { return getStringField(3); } StringRef getName() const { return getStringField(3); }
StringRef getDisplayName() const { return getStringField(4); } StringRef getDisplayName() const { return getStringField(4); }
StringRef getLinkageName() const { return getStringField(5); } StringRef getLinkageName() const { return getStringField(5); }
DICompileUnit getCompileUnit() const{ DICompileUnit getCompileUnit() const{
assert (getVersion() <= LLVMDebugVersion10 && "Invalid getCompileUnit !"); assert (getVersion() <= LLVMDebugVersion10 && "Invalid getCompileUnit !");
if (getVersion() == llvm::LLVMDebugVersion7) if (getVersion() == llvm::LLVMDebugVersion7)
skipping to change at line 637 skipping to change at line 616
unsigned getLineNumber() const { return getUnsignedField(7); } unsigned getLineNumber() const { return getUnsignedField(7); }
DIType getType() const { return getFieldAs<DIType>(8); } DIType getType() const { return getFieldAs<DIType>(8); }
unsigned isLocalToUnit() const { return getUnsignedField(9); } unsigned isLocalToUnit() const { return getUnsignedField(9); }
unsigned isDefinition() const { return getUnsignedField(10); } unsigned isDefinition() const { return getUnsignedField(10); }
GlobalVariable *getGlobal() const { return getGlobalVariableField(11); } GlobalVariable *getGlobal() const { return getGlobalVariableField(11); }
Constant *getConstant() const { return getConstantField(11); } Constant *getConstant() const { return getConstantField(11); }
/// Verify - Verify that a global variable descriptor is well formed. /// Verify - Verify that a global variable descriptor is well formed.
bool Verify() const; bool Verify() const;
/// print - print global variable.
void print(raw_ostream &OS) const;
/// dump - print global variable to dbgs() with a newline.
void dump() const;
}; };
/// DIVariable - This is a wrapper for a variable (e.g. parameter, local, /// DIVariable - This is a wrapper for a variable (e.g. parameter, local,
/// global etc). /// global etc).
class DIVariable : public DIDescriptor { class DIVariable : public DIDescriptor {
friend class DIDescriptor;
void printInternal(raw_ostream &OS) const;
public: public:
explicit DIVariable(const MDNode *N = 0) explicit DIVariable(const MDNode *N = 0)
: DIDescriptor(N) {} : DIDescriptor(N) {}
DIScope getContext() const { return getFieldAs<DIScope>(1); } DIScope getContext() const { return getFieldAs<DIScope>(1); }
StringRef getName() const { return getStringField(2); } StringRef getName() const { return getStringField(2); }
DICompileUnit getCompileUnit() const { DICompileUnit getCompileUnit() const {
assert (getVersion() <= LLVMDebugVersion10 && "Invalid getCompileUnit !"); assert (getVersion() <= LLVMDebugVersion10 && "Invalid getCompileUnit !");
if (getVersion() == llvm::LLVMDebugVersion7) if (getVersion() == llvm::LLVMDebugVersion7)
return getFieldAs<DICompileUnit>(3); return getFieldAs<DICompileUnit>(3);
skipping to change at line 678 skipping to change at line 653
} }
DIType getType() const { return getFieldAs<DIType>(5); } DIType getType() const { return getFieldAs<DIType>(5); }
/// isArtificial - Return true if this variable is marked as "artificia l". /// isArtificial - Return true if this variable is marked as "artificia l".
bool isArtificial() const { bool isArtificial() const {
if (getVersion() <= llvm::LLVMDebugVersion8) if (getVersion() <= llvm::LLVMDebugVersion8)
return false; return false;
return (getUnsignedField(6) & FlagArtificial) != 0; return (getUnsignedField(6) & FlagArtificial) != 0;
} }
bool isObjectPointer() const {
return (getUnsignedField(6) & FlagObjectPointer) != 0;
}
/// getInlinedAt - If this variable is inlined then return inline locat ion. /// getInlinedAt - If this variable is inlined then return inline locat ion.
MDNode *getInlinedAt() const; MDNode *getInlinedAt() const;
/// Verify - Verify that a variable descriptor is well formed. /// Verify - Verify that a variable descriptor is well formed.
bool Verify() const; bool Verify() const;
/// HasComplexAddr - Return true if the variable has a complex address. /// HasComplexAddr - Return true if the variable has a complex address.
bool hasComplexAddress() const { bool hasComplexAddress() const {
return getNumAddrElements() > 0; return getNumAddrElements() > 0;
} }
skipping to change at line 709 skipping to change at line 688
/// isBlockByrefVariable - Return true if the variable was declared as /// isBlockByrefVariable - Return true if the variable was declared as
/// a "__block" variable (Apple Blocks). /// a "__block" variable (Apple Blocks).
bool isBlockByrefVariable() const { bool isBlockByrefVariable() const {
return getType().isBlockByrefStruct(); return getType().isBlockByrefStruct();
} }
/// isInlinedFnArgument - Return trule if this variable provides debugg ing /// isInlinedFnArgument - Return trule if this variable provides debugg ing
/// information for an inlined function arguments. /// information for an inlined function arguments.
bool isInlinedFnArgument(const Function *CurFn); bool isInlinedFnArgument(const Function *CurFn);
/// print - print variable.
void print(raw_ostream &OS) const;
void printExtendedName(raw_ostream &OS) const; void printExtendedName(raw_ostream &OS) const;
/// dump - print variable to dbgs() with a newline.
void dump() const;
}; };
/// DILexicalBlock - This is a wrapper for a lexical block. /// DILexicalBlock - This is a wrapper for a lexical block.
class DILexicalBlock : public DIScope { class DILexicalBlock : public DIScope {
virtual void anchor();
public: public:
explicit DILexicalBlock(const MDNode *N = 0) : DIScope(N) {} explicit DILexicalBlock(const MDNode *N = 0) : DIScope(N) {}
DIScope getContext() const { return getFieldAs<DIScope>(1); } DIScope getContext() const { return getFieldAs<DIScope>(1); }
unsigned getLineNumber() const { return getUnsignedField(2); } unsigned getLineNumber() const { return getUnsignedField(2); }
unsigned getColumnNumber() const { return getUnsignedField(3); } unsigned getColumnNumber() const { return getUnsignedField(3); }
StringRef getDirectory() const { StringRef getDirectory() const {
StringRef dir = getFieldAs<DIFile>(4).getDirectory(); StringRef dir = getFieldAs<DIFile>(4).getDirectory();
return !dir.empty() ? dir : getContext().getDirectory(); return !dir.empty() ? dir : getContext().getDirectory();
} }
StringRef getFilename() const { StringRef getFilename() const {
StringRef filename = getFieldAs<DIFile>(4).getFilename(); StringRef filename = getFieldAs<DIFile>(4).getFilename();
return !filename.empty() ? filename : getContext().getFilename(); return !filename.empty() ? filename : getContext().getFilename();
} }
}; };
/// DILexicalBlockFile - This is a wrapper for a lexical block with /// DILexicalBlockFile - This is a wrapper for a lexical block with
/// a filename change. /// a filename change.
class DILexicalBlockFile : public DIScope { class DILexicalBlockFile : public DIScope {
virtual void anchor();
public: public:
explicit DILexicalBlockFile(const MDNode *N = 0) : DIScope(N) {} explicit DILexicalBlockFile(const MDNode *N = 0) : DIScope(N) {}
DIScope getContext() const { return getScope().getContext(); } DIScope getContext() const { return getScope().getContext(); }
unsigned getLineNumber() const { return getScope().getLineNumber(); } unsigned getLineNumber() const { return getScope().getLineNumber(); }
unsigned getColumnNumber() const { return getScope().getColumnNumber(); } unsigned getColumnNumber() const { return getScope().getColumnNumber(); }
StringRef getDirectory() const { StringRef getDirectory() const {
StringRef dir = getFieldAs<DIFile>(2).getDirectory(); StringRef dir = getFieldAs<DIFile>(2).getDirectory();
return !dir.empty() ? dir : getContext().getDirectory(); return !dir.empty() ? dir : getContext().getDirectory();
} }
StringRef getFilename() const { StringRef getFilename() const {
StringRef filename = getFieldAs<DIFile>(2).getFilename(); StringRef filename = getFieldAs<DIFile>(2).getFilename();
assert(!filename.empty() && "Why'd you create this then?"); assert(!filename.empty() && "Why'd you create this then?");
return filename; return filename;
} }
DILexicalBlock getScope() const { return getFieldAs<DILexicalBlock>(1); } DILexicalBlock getScope() const { return getFieldAs<DILexicalBlock>(1); }
}; };
/// DINameSpace - A wrapper for a C++ style name space. /// DINameSpace - A wrapper for a C++ style name space.
class DINameSpace : public DIScope { class DINameSpace : public DIScope {
virtual void anchor();
public: public:
explicit DINameSpace(const MDNode *N = 0) : DIScope(N) {} explicit DINameSpace(const MDNode *N = 0) : DIScope(N) {}
DIScope getContext() const { return getFieldAs<DIScope>(1); } DIScope getContext() const { return getFieldAs<DIScope>(1); }
StringRef getName() const { return getStringField(2); } StringRef getName() const { return getStringField(2); }
StringRef getDirectory() const { StringRef getDirectory() const {
return getFieldAs<DIFile>(3).getDirectory(); return getFieldAs<DIFile>(3).getDirectory();
} }
StringRef getFilename() const { StringRef getFilename() const {
return getFieldAs<DIFile>(3).getFilename(); return getFieldAs<DIFile>(3).getFilename();
} }
skipping to change at line 797 skipping to change at line 767
unsigned getLineNumber() const { return getUnsignedField(0); } unsigned getLineNumber() const { return getUnsignedField(0); }
unsigned getColumnNumber() const { return getUnsignedField(1); } unsigned getColumnNumber() const { return getUnsignedField(1); }
DIScope getScope() const { return getFieldAs<DIScope>(2); } DIScope getScope() const { return getFieldAs<DIScope>(2); }
DILocation getOrigLocation() const { return getFieldAs<DILocation>(3); } DILocation getOrigLocation() const { return getFieldAs<DILocation>(3); }
StringRef getFilename() const { return getScope().getFilename(); } StringRef getFilename() const { return getScope().getFilename(); }
StringRef getDirectory() const { return getScope().getDirectory(); } StringRef getDirectory() const { return getScope().getDirectory(); }
bool Verify() const; bool Verify() const;
}; };
class DIObjCProperty : public DIDescriptor { class DIObjCProperty : public DIDescriptor {
friend class DIDescriptor;
void printInternal(raw_ostream &OS) const;
public: public:
explicit DIObjCProperty(const MDNode *N) : DIDescriptor(N) { } explicit DIObjCProperty(const MDNode *N) : DIDescriptor(N) { }
StringRef getObjCPropertyName() const { return getStringField(1); } StringRef getObjCPropertyName() const { return getStringField(1); }
DIFile getFile() const { return getFieldAs<DIFile>(2); } DIFile getFile() const { return getFieldAs<DIFile>(2); }
unsigned getLineNumber() const { return getUnsignedField(3); } unsigned getLineNumber() const { return getUnsignedField(3); }
StringRef getObjCPropertyGetterName() const { StringRef getObjCPropertyGetterName() const {
return getStringField(4); return getStringField(4);
} }
skipping to change at line 833 skipping to change at line 805
return (getUnsignedField(6) & dwarf::DW_APPLE_PROPERTY_copy) != 0; return (getUnsignedField(6) & dwarf::DW_APPLE_PROPERTY_copy) != 0;
} }
bool isNonAtomicObjCProperty() { bool isNonAtomicObjCProperty() {
return (getUnsignedField(6) & dwarf::DW_APPLE_PROPERTY_nonatomic) != 0; return (getUnsignedField(6) & dwarf::DW_APPLE_PROPERTY_nonatomic) != 0;
} }
DIType getType() const { return getFieldAs<DIType>(7); } DIType getType() const { return getFieldAs<DIType>(7); }
/// Verify - Verify that a derived type descriptor is well formed. /// Verify - Verify that a derived type descriptor is well formed.
bool Verify() const; bool Verify() const;
/// print - print derived type.
void print(raw_ostream &OS) const;
/// dump - print derived type to dbgs() with a newline.
void dump() const;
}; };
/// getDISubprogram - Find subprogram that is enclosing this scope. /// getDISubprogram - Find subprogram that is enclosing this scope.
DISubprogram getDISubprogram(const MDNode *Scope); DISubprogram getDISubprogram(const MDNode *Scope);
/// getDICompositeType - Find underlying composite type. /// getDICompositeType - Find underlying composite type.
DICompositeType getDICompositeType(DIType T); DICompositeType getDICompositeType(DIType T);
/// isSubprogramContext - Return true if Context is either a subprogram /// isSubprogramContext - Return true if Context is either a subprogram
/// or another context nested inside a subprogram. /// or another context nested inside a subprogram.
 End of changes. 39 change blocks. 
78 lines changed or deleted 46 lines changed or added


 DebugLoc.h   DebugLoc.h 
skipping to change at line 18 skipping to change at line 18
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// //
// This file defines a number of light weight data structures used // This file defines a number of light weight data structures used
// to describe and track debug location information. // to describe and track debug location information.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_SUPPORT_DEBUGLOC_H #ifndef LLVM_SUPPORT_DEBUGLOC_H
#define LLVM_SUPPORT_DEBUGLOC_H #define LLVM_SUPPORT_DEBUGLOC_H
#include "llvm/ADT/DenseMapInfo.h"
namespace llvm { namespace llvm {
template <typename T> struct DenseMapInfo;
class MDNode; class MDNode;
class LLVMContext; class LLVMContext;
/// DebugLoc - Debug location id. This is carried by Instruction, SDNode , /// DebugLoc - Debug location id. This is carried by Instruction, SDNode ,
/// and MachineInstr to compactly encode file/line/scope information for an /// and MachineInstr to compactly encode file/line/scope information for an
/// operation. /// operation.
class DebugLoc { class DebugLoc {
friend struct DenseMapInfo<DebugLoc>; friend struct DenseMapInfo<DebugLoc>;
/// getEmptyKey() - A private constructor that returns an unknown that is /// getEmptyKey() - A private constructor that returns an unknown that is
skipping to change at line 105 skipping to change at line 104
bool operator==(const DebugLoc &DL) const { bool operator==(const DebugLoc &DL) const {
return LineCol == DL.LineCol && ScopeIdx == DL.ScopeIdx; return LineCol == DL.LineCol && ScopeIdx == DL.ScopeIdx;
} }
bool operator!=(const DebugLoc &DL) const { return !(*this == DL); } bool operator!=(const DebugLoc &DL) const { return !(*this == DL); }
void dump(const LLVMContext &Ctx) const; void dump(const LLVMContext &Ctx) const;
}; };
template <> template <>
struct DenseMapInfo<DebugLoc> { struct DenseMapInfo<DebugLoc> {
static DebugLoc getEmptyKey(); static DebugLoc getEmptyKey() { return DebugLoc::getEmptyKey(); }
static DebugLoc getTombstoneKey(); static DebugLoc getTombstoneKey() { return DebugLoc::getTombstoneKey();
}
static unsigned getHashValue(const DebugLoc &Key); static unsigned getHashValue(const DebugLoc &Key);
static bool isEqual(const DebugLoc &LHS, const DebugLoc &RHS); static bool isEqual(DebugLoc LHS, DebugLoc RHS) { return LHS == RHS; }
}; };
} // end namespace llvm } // end namespace llvm
#endif /* LLVM_DEBUGLOC_H */ #endif /* LLVM_DEBUGLOC_H */
 End of changes. 4 change blocks. 
5 lines changed or deleted 5 lines changed or added


 DefaultPasses.h   DefaultPasses.h 
skipping to change at line 17 skipping to change at line 17
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// This file defines the infrastructure for registering the standard pass l ist. // This file defines the infrastructure for registering the standard pass l ist.
// This defines sets of standard optimizations that plugins can modify and // This defines sets of standard optimizations that plugins can modify and
// front ends can use. // front ends can use.
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_DEFAULT_PASS_SUPPORT_H #ifndef LLVM_DEFAULT_PASS_SUPPORT_H
#define LLVM_DEFAULT_PASS_SUPPORT_H #define LLVM_DEFAULT_PASS_SUPPORT_H
#include <llvm/PassSupport.h> #include "llvm/PassSupport.h"
namespace llvm { namespace llvm {
class PassManagerBase; class PassManagerBase;
/// Unique identifiers for the default standard passes. The addresses of /// Unique identifiers for the default standard passes. The addresses of
/// these symbols are used to uniquely identify passes from the default lis t. /// these symbols are used to uniquely identify passes from the default lis t.
namespace DefaultStandardPasses { namespace DefaultStandardPasses {
extern unsigned char AggressiveDCEID; extern unsigned char AggressiveDCEID;
extern unsigned char ArgumentPromotionID; extern unsigned char ArgumentPromotionID;
 End of changes. 1 change blocks. 
1 lines changed or deleted 1 lines changed or added


 DeltaAlgorithm.h   DeltaAlgorithm.h 
skipping to change at line 48 skipping to change at line 48
typedef unsigned change_ty; typedef unsigned change_ty;
// FIXME: Use a decent data structure. // FIXME: Use a decent data structure.
typedef std::set<change_ty> changeset_ty; typedef std::set<change_ty> changeset_ty;
typedef std::vector<changeset_ty> changesetlist_ty; typedef std::vector<changeset_ty> changesetlist_ty;
private: private:
/// Cache of failed test results. Successful test results are never cache d /// Cache of failed test results. Successful test results are never cache d
/// since we always reduce following a success. /// since we always reduce following a success.
std::set<changeset_ty> FailedTestsCache; std::set<changeset_ty> FailedTestsCache;
/// GetTestResult - Get the test result for the \arg Changes from the /// GetTestResult - Get the test result for the \p Changes from the
/// cache, executing the test if necessary. /// cache, executing the test if necessary.
/// ///
/// \param Changes - The change set to test. /// \param Changes - The change set to test.
/// \return - The test result. /// \return - The test result.
bool GetTestResult(const changeset_ty &Changes); bool GetTestResult(const changeset_ty &Changes);
/// Split - Partition a set of changes \arg S into one or two subsets. /// Split - Partition a set of changes \p S into one or two subsets.
void Split(const changeset_ty &S, changesetlist_ty &Res); void Split(const changeset_ty &S, changesetlist_ty &Res);
/// Delta - Minimize a set of \arg Changes which has been partioned into /// Delta - Minimize a set of \p Changes which has been partioned into
/// smaller sets, by attempting to remove individual subsets. /// smaller sets, by attempting to remove individual subsets.
changeset_ty Delta(const changeset_ty &Changes, changeset_ty Delta(const changeset_ty &Changes,
const changesetlist_ty &Sets); const changesetlist_ty &Sets);
/// Search - Search for a subset (or subsets) in \arg Sets which can be /// Search - Search for a subset (or subsets) in \p Sets which can be
/// removed from \arg Changes while still satisfying the predicate. /// removed from \p Changes while still satisfying the predicate.
/// ///
/// \param Res - On success, a subset of Changes which satisfies the /// \param Res - On success, a subset of Changes which satisfies the
/// predicate. /// predicate.
/// \return - True on success. /// \return - True on success.
bool Search(const changeset_ty &Changes, const changesetlist_ty &Sets, bool Search(const changeset_ty &Changes, const changesetlist_ty &Sets,
changeset_ty &Res); changeset_ty &Res);
protected: protected:
/// UpdatedSearchState - Callback used when the search state changes. /// UpdatedSearchState - Callback used when the search state changes.
virtual void UpdatedSearchState(const changeset_ty &Changes, virtual void UpdatedSearchState(const changeset_ty &Changes,
const changesetlist_ty &Sets) {} const changesetlist_ty &Sets) {}
/// ExecuteOneTest - Execute a single test predicate on the change set \a rg S. /// ExecuteOneTest - Execute a single test predicate on the change set \p S.
virtual bool ExecuteOneTest(const changeset_ty &S) = 0; virtual bool ExecuteOneTest(const changeset_ty &S) = 0;
public: public:
virtual ~DeltaAlgorithm(); virtual ~DeltaAlgorithm();
/// Run - Minimize the set \arg Changes by executing \see ExecuteOneTest( ) on /// Run - Minimize the set \p Changes by executing \see ExecuteOneTest() on
/// subsets of changes and returning the smallest set which still satisfi es /// subsets of changes and returning the smallest set which still satisfi es
/// the test predicate. /// the test predicate.
changeset_ty Run(const changeset_ty &Changes); changeset_ty Run(const changeset_ty &Changes);
}; };
} // end namespace llvm } // end namespace llvm
#endif #endif
 End of changes. 6 change blocks. 
7 lines changed or deleted 7 lines changed or added


 DenseMap.h   DenseMap.h 
skipping to change at line 17 skipping to change at line 17
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// //
// This file defines the DenseMap class. // This file defines the DenseMap class.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_ADT_DENSEMAP_H #ifndef LLVM_ADT_DENSEMAP_H
#define LLVM_ADT_DENSEMAP_H #define LLVM_ADT_DENSEMAP_H
#include "llvm/Support/Compiler.h"
#include "llvm/Support/AlignOf.h"
#include "llvm/Support/MathExtras.h" #include "llvm/Support/MathExtras.h"
#include "llvm/Support/PointerLikeTypeTraits.h" #include "llvm/Support/PointerLikeTypeTraits.h"
#include "llvm/Support/type_traits.h" #include "llvm/Support/type_traits.h"
#include "llvm/ADT/DenseMapInfo.h" #include "llvm/ADT/DenseMapInfo.h"
#include <algorithm> #include <algorithm>
#include <iterator> #include <iterator>
#include <new> #include <new>
#include <utility> #include <utility>
#include <cassert> #include <cassert>
#include <climits>
#include <cstddef> #include <cstddef>
#include <cstring> #include <cstring>
namespace llvm { namespace llvm {
template<typename KeyT, typename ValueT, template<typename KeyT, typename ValueT,
typename KeyInfoT = DenseMapInfo<KeyT>, typename KeyInfoT = DenseMapInfo<KeyT>,
bool IsConst = false> bool IsConst = false>
class DenseMapIterator; class DenseMapIterator;
template<typename KeyT, typename ValueT, template<typename DerivedT,
typename KeyInfoT = DenseMapInfo<KeyT> > typename KeyT, typename ValueT, typename KeyInfoT>
class DenseMap { class DenseMapBase {
protected:
typedef std::pair<KeyT, ValueT> BucketT; typedef std::pair<KeyT, ValueT> BucketT;
unsigned NumBuckets;
BucketT *Buckets;
unsigned NumEntries;
unsigned NumTombstones;
public: public:
typedef KeyT key_type; typedef KeyT key_type;
typedef ValueT mapped_type; typedef ValueT mapped_type;
typedef BucketT value_type; typedef BucketT value_type;
DenseMap(const DenseMap &other) {
NumBuckets = 0;
CopyFrom(other);
}
explicit DenseMap(unsigned NumInitBuckets = 0) {
init(NumInitBuckets);
}
template<typename InputIt>
DenseMap(const InputIt &I, const InputIt &E) {
init(NextPowerOf2(std::distance(I, E)));
insert(I, E);
}
~DenseMap() {
const KeyT EmptyKey = getEmptyKey(), TombstoneKey = getTombstoneKey();
for (BucketT *P = Buckets, *E = Buckets+NumBuckets; P != E; ++P) {
if (!KeyInfoT::isEqual(P->first, EmptyKey) &&
!KeyInfoT::isEqual(P->first, TombstoneKey))
P->second.~ValueT();
P->first.~KeyT();
}
#ifndef NDEBUG
if (NumBuckets)
memset((void*)Buckets, 0x5a, sizeof(BucketT)*NumBuckets);
#endif
operator delete(Buckets);
}
typedef DenseMapIterator<KeyT, ValueT, KeyInfoT> iterator; typedef DenseMapIterator<KeyT, ValueT, KeyInfoT> iterator;
typedef DenseMapIterator<KeyT, ValueT, typedef DenseMapIterator<KeyT, ValueT,
KeyInfoT, true> const_iterator; KeyInfoT, true> const_iterator;
inline iterator begin() { inline iterator begin() {
// When the map is empty, avoid the overhead of AdvancePastEmptyBuckets (). // When the map is empty, avoid the overhead of AdvancePastEmptyBuckets ().
return empty() ? end() : iterator(Buckets, Buckets+NumBuckets); return empty() ? end() : iterator(getBuckets(), getBucketsEnd());
} }
inline iterator end() { inline iterator end() {
return iterator(Buckets+NumBuckets, Buckets+NumBuckets, true); return iterator(getBucketsEnd(), getBucketsEnd(), true);
} }
inline const_iterator begin() const { inline const_iterator begin() const {
return empty() ? end() : const_iterator(Buckets, Buckets+NumBuckets); return empty() ? end() : const_iterator(getBuckets(), getBucketsEnd());
} }
inline const_iterator end() const { inline const_iterator end() const {
return const_iterator(Buckets+NumBuckets, Buckets+NumBuckets, true); return const_iterator(getBucketsEnd(), getBucketsEnd(), true);
} }
bool empty() const { return NumEntries == 0; } bool empty() const { return getNumEntries() == 0; }
unsigned size() const { return NumEntries; } unsigned size() const { return getNumEntries(); }
/// Grow the densemap so that it has at least Size buckets. Does not shri nk /// Grow the densemap so that it has at least Size buckets. Does not shri nk
void resize(size_t Size) { void resize(size_t Size) {
if (Size > NumBuckets) if (Size > getNumBuckets())
grow(Size); grow(Size);
} }
void clear() { void clear() {
if (NumEntries == 0 && NumTombstones == 0) return; if (getNumEntries() == 0 && getNumTombstones() == 0) return;
// If the capacity of the array is huge, and the # elements used is sma ll, // If the capacity of the array is huge, and the # elements used is sma ll,
// shrink the array. // shrink the array.
if (NumEntries * 4 < NumBuckets && NumBuckets > 64) { if (getNumEntries() * 4 < getNumBuckets() && getNumBuckets() > 64) {
shrink_and_clear(); shrink_and_clear();
return; return;
} }
const KeyT EmptyKey = getEmptyKey(), TombstoneKey = getTombstoneKey(); const KeyT EmptyKey = getEmptyKey(), TombstoneKey = getTombstoneKey();
for (BucketT *P = Buckets, *E = Buckets+NumBuckets; P != E; ++P) { for (BucketT *P = getBuckets(), *E = getBucketsEnd(); P != E; ++P) {
if (!KeyInfoT::isEqual(P->first, EmptyKey)) { if (!KeyInfoT::isEqual(P->first, EmptyKey)) {
if (!KeyInfoT::isEqual(P->first, TombstoneKey)) { if (!KeyInfoT::isEqual(P->first, TombstoneKey)) {
P->second.~ValueT(); P->second.~ValueT();
--NumEntries; decrementNumEntries();
} }
P->first = EmptyKey; P->first = EmptyKey;
} }
} }
assert(NumEntries == 0 && "Node count imbalance!"); assert(getNumEntries() == 0 && "Node count imbalance!");
NumTombstones = 0; setNumTombstones(0);
} }
/// count - Return true if the specified key is in the map. /// count - Return true if the specified key is in the map.
bool count(const KeyT &Val) const { bool count(const KeyT &Val) const {
BucketT *TheBucket; const BucketT *TheBucket;
return LookupBucketFor(Val, TheBucket); return LookupBucketFor(Val, TheBucket);
} }
iterator find(const KeyT &Val) { iterator find(const KeyT &Val) {
BucketT *TheBucket; BucketT *TheBucket;
if (LookupBucketFor(Val, TheBucket)) if (LookupBucketFor(Val, TheBucket))
return iterator(TheBucket, Buckets+NumBuckets, true); return iterator(TheBucket, getBucketsEnd(), true);
return end(); return end();
} }
const_iterator find(const KeyT &Val) const { const_iterator find(const KeyT &Val) const {
BucketT *TheBucket; const BucketT *TheBucket;
if (LookupBucketFor(Val, TheBucket)) if (LookupBucketFor(Val, TheBucket))
return const_iterator(TheBucket, Buckets+NumBuckets, true); return const_iterator(TheBucket, getBucketsEnd(), true);
return end(); return end();
} }
/// Alternate version of find() which allows a different, and possibly /// Alternate version of find() which allows a different, and possibly
/// less expensive, key type. /// less expensive, key type.
/// The DenseMapInfo is responsible for supplying methods /// The DenseMapInfo is responsible for supplying methods
/// getHashValue(LookupKeyT) and isEqual(LookupKeyT, KeyT) for each key /// getHashValue(LookupKeyT) and isEqual(LookupKeyT, KeyT) for each key
/// type used. /// type used.
template<class LookupKeyT> template<class LookupKeyT>
iterator find_as(const LookupKeyT &Val) { iterator find_as(const LookupKeyT &Val) {
BucketT *TheBucket; BucketT *TheBucket;
if (LookupBucketFor(Val, TheBucket)) if (LookupBucketFor(Val, TheBucket))
return iterator(TheBucket, Buckets+NumBuckets, true); return iterator(TheBucket, getBucketsEnd(), true);
return end(); return end();
} }
template<class LookupKeyT> template<class LookupKeyT>
const_iterator find_as(const LookupKeyT &Val) const { const_iterator find_as(const LookupKeyT &Val) const {
BucketT *TheBucket; const BucketT *TheBucket;
if (LookupBucketFor(Val, TheBucket)) if (LookupBucketFor(Val, TheBucket))
return const_iterator(TheBucket, Buckets+NumBuckets, true); return const_iterator(TheBucket, getBucketsEnd(), true);
return end(); return end();
} }
/// lookup - Return the entry for the specified key, or a default /// lookup - Return the entry for the specified key, or a default
/// constructed value if no such entry exists. /// constructed value if no such entry exists.
ValueT lookup(const KeyT &Val) const { ValueT lookup(const KeyT &Val) const {
BucketT *TheBucket; const BucketT *TheBucket;
if (LookupBucketFor(Val, TheBucket)) if (LookupBucketFor(Val, TheBucket))
return TheBucket->second; return TheBucket->second;
return ValueT(); return ValueT();
} }
// Inserts key,value pair into the map if the key isn't already in the ma p. // Inserts key,value pair into the map if the key isn't already in the ma p.
// If the key is already in the map, it returns false and doesn't update the // If the key is already in the map, it returns false and doesn't update the
// value. // value.
std::pair<iterator, bool> insert(const std::pair<KeyT, ValueT> &KV) { std::pair<iterator, bool> insert(const std::pair<KeyT, ValueT> &KV) {
BucketT *TheBucket; BucketT *TheBucket;
if (LookupBucketFor(KV.first, TheBucket)) if (LookupBucketFor(KV.first, TheBucket))
return std::make_pair(iterator(TheBucket, Buckets+NumBuckets, true), return std::make_pair(iterator(TheBucket, getBucketsEnd(), true),
false); // Already in map. false); // Already in map.
// Otherwise, insert the new element. // Otherwise, insert the new element.
TheBucket = InsertIntoBucket(KV.first, KV.second, TheBucket); TheBucket = InsertIntoBucket(KV.first, KV.second, TheBucket);
return std::make_pair(iterator(TheBucket, Buckets+NumBuckets, true), tr ue); return std::make_pair(iterator(TheBucket, getBucketsEnd(), true), true) ;
} }
/// insert - Range insertion of pairs. /// insert - Range insertion of pairs.
template<typename InputIt> template<typename InputIt>
void insert(InputIt I, InputIt E) { void insert(InputIt I, InputIt E) {
for (; I != E; ++I) for (; I != E; ++I)
insert(*I); insert(*I);
} }
bool erase(const KeyT &Val) { bool erase(const KeyT &Val) {
BucketT *TheBucket; BucketT *TheBucket;
if (!LookupBucketFor(Val, TheBucket)) if (!LookupBucketFor(Val, TheBucket))
return false; // not in map. return false; // not in map.
TheBucket->second.~ValueT(); TheBucket->second.~ValueT();
TheBucket->first = getTombstoneKey(); TheBucket->first = getTombstoneKey();
--NumEntries; decrementNumEntries();
++NumTombstones; incrementNumTombstones();
return true; return true;
} }
void erase(iterator I) { void erase(iterator I) {
BucketT *TheBucket = &*I; BucketT *TheBucket = &*I;
TheBucket->second.~ValueT(); TheBucket->second.~ValueT();
TheBucket->first = getTombstoneKey(); TheBucket->first = getTombstoneKey();
--NumEntries; decrementNumEntries();
++NumTombstones; incrementNumTombstones();
}
void swap(DenseMap& RHS) {
std::swap(NumBuckets, RHS.NumBuckets);
std::swap(Buckets, RHS.Buckets);
std::swap(NumEntries, RHS.NumEntries);
std::swap(NumTombstones, RHS.NumTombstones);
} }
value_type& FindAndConstruct(const KeyT &Key) { value_type& FindAndConstruct(const KeyT &Key) {
BucketT *TheBucket; BucketT *TheBucket;
if (LookupBucketFor(Key, TheBucket)) if (LookupBucketFor(Key, TheBucket))
return *TheBucket; return *TheBucket;
return *InsertIntoBucket(Key, ValueT(), TheBucket); return *InsertIntoBucket(Key, ValueT(), TheBucket);
} }
ValueT &operator[](const KeyT &Key) { ValueT &operator[](const KeyT &Key) {
return FindAndConstruct(Key).second; return FindAndConstruct(Key).second;
} }
DenseMap& operator=(const DenseMap& other) { #if LLVM_USE_RVALUE_REFERENCES
CopyFrom(other); value_type& FindAndConstruct(KeyT &&Key) {
return *this; BucketT *TheBucket;
if (LookupBucketFor(Key, TheBucket))
return *TheBucket;
return *InsertIntoBucket(Key, ValueT(), TheBucket);
} }
ValueT &operator[](KeyT &&Key) {
return FindAndConstruct(Key).second;
}
#endif
/// isPointerIntoBucketsArray - Return true if the specified pointer poin ts /// isPointerIntoBucketsArray - Return true if the specified pointer poin ts
/// somewhere into the DenseMap's array of buckets (i.e. either to a key or /// somewhere into the DenseMap's array of buckets (i.e. either to a key or
/// value in the DenseMap). /// value in the DenseMap).
bool isPointerIntoBucketsArray(const void *Ptr) const { bool isPointerIntoBucketsArray(const void *Ptr) const {
return Ptr >= Buckets && Ptr < Buckets+NumBuckets; return Ptr >= getBuckets() && Ptr < getBucketsEnd();
} }
/// getPointerIntoBucketsArray() - Return an opaque pointer into the buck ets /// getPointerIntoBucketsArray() - Return an opaque pointer into the buck ets
/// array. In conjunction with the previous method, this can be used to /// array. In conjunction with the previous method, this can be used to
/// determine whether an insertion caused the DenseMap to reallocate. /// determine whether an insertion caused the DenseMap to reallocate.
const void *getPointerIntoBucketsArray() const { return Buckets; } const void *getPointerIntoBucketsArray() const { return getBuckets(); }
private: protected:
void CopyFrom(const DenseMap& other) { DenseMapBase() {}
if (NumBuckets != 0 &&
(!isPodLike<KeyT>::value || !isPodLike<ValueT>::value)) { void destroyAll() {
const KeyT EmptyKey = getEmptyKey(), TombstoneKey = getTombstoneKey() if (getNumBuckets() == 0) // Nothing to do.
; return;
for (BucketT *P = Buckets, *E = Buckets+NumBuckets; P != E; ++P) {
if (!KeyInfoT::isEqual(P->first, EmptyKey) &&
!KeyInfoT::isEqual(P->first, TombstoneKey))
P->second.~ValueT();
P->first.~KeyT();
}
}
NumEntries = other.NumEntries; const KeyT EmptyKey = getEmptyKey(), TombstoneKey = getTombstoneKey();
NumTombstones = other.NumTombstones; for (BucketT *P = getBuckets(), *E = getBucketsEnd(); P != E; ++P) {
if (!KeyInfoT::isEqual(P->first, EmptyKey) &&
!KeyInfoT::isEqual(P->first, TombstoneKey))
P->second.~ValueT();
P->first.~KeyT();
}
if (NumBuckets) {
#ifndef NDEBUG #ifndef NDEBUG
memset((void*)Buckets, 0x5a, sizeof(BucketT)*NumBuckets); memset((void*)getBuckets(), 0x5a, sizeof(BucketT)*getNumBuckets());
#endif #endif
operator delete(Buckets); }
}
NumBuckets = other.NumBuckets; void initEmpty() {
setNumEntries(0);
setNumTombstones(0);
if (NumBuckets == 0) { assert((getNumBuckets() & (getNumBuckets()-1)) == 0 &&
Buckets = 0; "# initial buckets must be a power of two!");
return; const KeyT EmptyKey = getEmptyKey();
for (BucketT *B = getBuckets(), *E = getBucketsEnd(); B != E; ++B)
new (&B->first) KeyT(EmptyKey);
}
void moveFromOldBuckets(BucketT *OldBucketsBegin, BucketT *OldBucketsEnd)
{
initEmpty();
// Insert all the old elements.
const KeyT EmptyKey = getEmptyKey();
const KeyT TombstoneKey = getTombstoneKey();
for (BucketT *B = OldBucketsBegin, *E = OldBucketsEnd; B != E; ++B) {
if (!KeyInfoT::isEqual(B->first, EmptyKey) &&
!KeyInfoT::isEqual(B->first, TombstoneKey)) {
// Insert the key/value into the new table.
BucketT *DestBucket;
bool FoundVal = LookupBucketFor(B->first, DestBucket);
(void)FoundVal; // silence warning.
assert(!FoundVal && "Key already in new map?");
DestBucket->first = llvm_move(B->first);
new (&DestBucket->second) ValueT(llvm_move(B->second));
incrementNumEntries();
// Free the value.
B->second.~ValueT();
}
B->first.~KeyT();
} }
Buckets = static_cast<BucketT*>(operator new(sizeof(BucketT) * NumBucke #ifndef NDEBUG
ts)); if (OldBucketsBegin != OldBucketsEnd)
memset((void*)OldBucketsBegin, 0x5a,
sizeof(BucketT) * (OldBucketsEnd - OldBucketsBegin));
#endif
}
template <typename OtherBaseT>
void copyFrom(const DenseMapBase<OtherBaseT, KeyT, ValueT, KeyInfoT>& oth
er) {
assert(getNumBuckets() == other.getNumBuckets());
setNumEntries(other.getNumEntries());
setNumTombstones(other.getNumTombstones());
if (isPodLike<KeyT>::value && isPodLike<ValueT>::value) if (isPodLike<KeyT>::value && isPodLike<ValueT>::value)
memcpy(Buckets, other.Buckets, NumBuckets * sizeof(BucketT)); memcpy(getBuckets(), other.getBuckets(),
getNumBuckets() * sizeof(BucketT));
else else
for (size_t i = 0; i < NumBuckets; ++i) { for (size_t i = 0; i < getNumBuckets(); ++i) {
new (&Buckets[i].first) KeyT(other.Buckets[i].first); new (&getBuckets()[i].first) KeyT(other.getBuckets()[i].first);
if (!KeyInfoT::isEqual(Buckets[i].first, getEmptyKey()) && if (!KeyInfoT::isEqual(getBuckets()[i].first, getEmptyKey()) &&
!KeyInfoT::isEqual(Buckets[i].first, getTombstoneKey())) !KeyInfoT::isEqual(getBuckets()[i].first, getTombstoneKey()))
new (&Buckets[i].second) ValueT(other.Buckets[i].second); new (&getBuckets()[i].second) ValueT(other.getBuckets()[i].second
);
} }
} }
void swap(DenseMapBase& RHS) {
std::swap(getNumEntries(), RHS.getNumEntries());
std::swap(getNumTombstones(), RHS.getNumTombstones());
}
static unsigned getHashValue(const KeyT &Val) {
return KeyInfoT::getHashValue(Val);
}
template<typename LookupKeyT>
static unsigned getHashValue(const LookupKeyT &Val) {
return KeyInfoT::getHashValue(Val);
}
static const KeyT getEmptyKey() {
return KeyInfoT::getEmptyKey();
}
static const KeyT getTombstoneKey() {
return KeyInfoT::getTombstoneKey();
}
private:
unsigned getNumEntries() const {
return static_cast<const DerivedT *>(this)->getNumEntries();
}
void setNumEntries(unsigned Num) {
static_cast<DerivedT *>(this)->setNumEntries(Num);
}
void incrementNumEntries() {
setNumEntries(getNumEntries() + 1);
}
void decrementNumEntries() {
setNumEntries(getNumEntries() - 1);
}
unsigned getNumTombstones() const {
return static_cast<const DerivedT *>(this)->getNumTombstones();
}
void setNumTombstones(unsigned Num) {
static_cast<DerivedT *>(this)->setNumTombstones(Num);
}
void incrementNumTombstones() {
setNumTombstones(getNumTombstones() + 1);
}
void decrementNumTombstones() {
setNumTombstones(getNumTombstones() - 1);
}
const BucketT *getBuckets() const {
return static_cast<const DerivedT *>(this)->getBuckets();
}
BucketT *getBuckets() {
return static_cast<DerivedT *>(this)->getBuckets();
}
unsigned getNumBuckets() const {
return static_cast<const DerivedT *>(this)->getNumBuckets();
}
BucketT *getBucketsEnd() {
return getBuckets() + getNumBuckets();
}
const BucketT *getBucketsEnd() const {
return getBuckets() + getNumBuckets();
}
void grow(unsigned AtLeast) {
static_cast<DerivedT *>(this)->grow(AtLeast);
}
void shrink_and_clear() {
static_cast<DerivedT *>(this)->shrink_and_clear();
}
BucketT *InsertIntoBucket(const KeyT &Key, const ValueT &Value, BucketT *InsertIntoBucket(const KeyT &Key, const ValueT &Value,
BucketT *TheBucket) { BucketT *TheBucket) {
TheBucket = InsertIntoBucketImpl(Key, TheBucket);
TheBucket->first = Key;
new (&TheBucket->second) ValueT(Value);
return TheBucket;
}
#if LLVM_USE_RVALUE_REFERENCES
BucketT *InsertIntoBucket(const KeyT &Key, ValueT &&Value,
BucketT *TheBucket) {
TheBucket = InsertIntoBucketImpl(Key, TheBucket);
TheBucket->first = Key;
new (&TheBucket->second) ValueT(std::move(Value));
return TheBucket;
}
BucketT *InsertIntoBucket(KeyT &&Key, ValueT &&Value, BucketT *TheBucket)
{
TheBucket = InsertIntoBucketImpl(Key, TheBucket);
TheBucket->first = std::move(Key);
new (&TheBucket->second) ValueT(std::move(Value));
return TheBucket;
}
#endif
BucketT *InsertIntoBucketImpl(const KeyT &Key, BucketT *TheBucket) {
// If the load of the hash table is more than 3/4, or if fewer than 1/8 of // If the load of the hash table is more than 3/4, or if fewer than 1/8 of
// the buckets are empty (meaning that many are filled with tombstones) , // the buckets are empty (meaning that many are filled with tombstones) ,
// grow the table. // grow the table.
// //
// The later case is tricky. For example, if we had one empty bucket w ith // The later case is tricky. For example, if we had one empty bucket w ith
// tons of tombstones, failing lookups (e.g. for insertion) would have to // tons of tombstones, failing lookups (e.g. for insertion) would have to
// probe almost the entire table until it found the empty bucket. If t he // probe almost the entire table until it found the empty bucket. If t he
// table completely filled with tombstones, no lookup would ever succee d, // table completely filled with tombstones, no lookup would ever succee d,
// causing infinite loops in lookup. // causing infinite loops in lookup.
++NumEntries; unsigned NewNumEntries = getNumEntries() + 1;
if (NumEntries*4 >= NumBuckets*3) { unsigned NumBuckets = getNumBuckets();
if (NewNumEntries*4 >= NumBuckets*3) {
this->grow(NumBuckets * 2); this->grow(NumBuckets * 2);
LookupBucketFor(Key, TheBucket); LookupBucketFor(Key, TheBucket);
NumBuckets = getNumBuckets();
} }
if (NumBuckets-(NumEntries+NumTombstones) < NumBuckets/8) { if (NumBuckets-(NewNumEntries+getNumTombstones()) <= NumBuckets/8) {
this->grow(NumBuckets); this->grow(NumBuckets * 2);
LookupBucketFor(Key, TheBucket); LookupBucketFor(Key, TheBucket);
} }
assert(TheBucket);
// Only update the state after we've grown our bucket space appropriate
ly
// so that when growing buckets we have self-consistent entry count.
incrementNumEntries();
// If we are writing over a tombstone, remember this. // If we are writing over a tombstone, remember this.
if (!KeyInfoT::isEqual(TheBucket->first, getEmptyKey())) if (!KeyInfoT::isEqual(TheBucket->first, getEmptyKey()))
--NumTombstones; decrementNumTombstones();
TheBucket->first = Key;
new (&TheBucket->second) ValueT(Value);
return TheBucket; return TheBucket;
} }
static unsigned getHashValue(const KeyT &Val) {
return KeyInfoT::getHashValue(Val);
}
template<typename LookupKeyT>
static unsigned getHashValue(const LookupKeyT &Val) {
return KeyInfoT::getHashValue(Val);
}
static const KeyT getEmptyKey() {
return KeyInfoT::getEmptyKey();
}
static const KeyT getTombstoneKey() {
return KeyInfoT::getTombstoneKey();
}
/// LookupBucketFor - Lookup the appropriate bucket for Val, returning it in /// LookupBucketFor - Lookup the appropriate bucket for Val, returning it in
/// FoundBucket. If the bucket contains the key and a value, this return s /// FoundBucket. If the bucket contains the key and a value, this return s
/// true, otherwise it returns a bucket with an empty marker or tombstone and /// true, otherwise it returns a bucket with an empty marker or tombstone and
/// returns false. /// returns false.
template<typename LookupKeyT> template<typename LookupKeyT>
bool LookupBucketFor(const LookupKeyT &Val, BucketT *&FoundBucket) const bool LookupBucketFor(const LookupKeyT &Val,
{ const BucketT *&FoundBucket) const {
unsigned BucketNo = getHashValue(Val); const BucketT *BucketsPtr = getBuckets();
unsigned ProbeAmt = 1; const unsigned NumBuckets = getNumBuckets();
BucketT *BucketsPtr = Buckets;
if (NumBuckets == 0) { if (NumBuckets == 0) {
FoundBucket = 0; FoundBucket = 0;
return false; return false;
} }
// FoundTombstone - Keep track of whether we find a tombstone while pro bing. // FoundTombstone - Keep track of whether we find a tombstone while pro bing.
BucketT *FoundTombstone = 0; const BucketT *FoundTombstone = 0;
const KeyT EmptyKey = getEmptyKey(); const KeyT EmptyKey = getEmptyKey();
const KeyT TombstoneKey = getTombstoneKey(); const KeyT TombstoneKey = getTombstoneKey();
assert(!KeyInfoT::isEqual(Val, EmptyKey) && assert(!KeyInfoT::isEqual(Val, EmptyKey) &&
!KeyInfoT::isEqual(Val, TombstoneKey) && !KeyInfoT::isEqual(Val, TombstoneKey) &&
"Empty/Tombstone value shouldn't be inserted into map!"); "Empty/Tombstone value shouldn't be inserted into map!");
unsigned BucketNo = getHashValue(Val) & (NumBuckets-1);
unsigned ProbeAmt = 1;
while (1) { while (1) {
BucketT *ThisBucket = BucketsPtr + (BucketNo & (NumBuckets-1)); const BucketT *ThisBucket = BucketsPtr + BucketNo;
// Found Val's bucket? If so, return it. // Found Val's bucket? If so, return it.
if (KeyInfoT::isEqual(Val, ThisBucket->first)) { if (KeyInfoT::isEqual(Val, ThisBucket->first)) {
FoundBucket = ThisBucket; FoundBucket = ThisBucket;
return true; return true;
} }
// If we found an empty bucket, the key doesn't exist in the set. // If we found an empty bucket, the key doesn't exist in the set.
// Insert it and return the default value. // Insert it and return the default value.
if (KeyInfoT::isEqual(ThisBucket->first, EmptyKey)) { if (KeyInfoT::isEqual(ThisBucket->first, EmptyKey)) {
// If we've already seen a tombstone while probing, fill it in inst ead // If we've already seen a tombstone while probing, fill it in inst ead
skipping to change at line 390 skipping to change at line 488
} }
// If this is a tombstone, remember it. If Val ends up not in the ma p, we // If this is a tombstone, remember it. If Val ends up not in the ma p, we
// prefer to return it than something that would require more probing . // prefer to return it than something that would require more probing .
if (KeyInfoT::isEqual(ThisBucket->first, TombstoneKey) && !FoundTombs tone) if (KeyInfoT::isEqual(ThisBucket->first, TombstoneKey) && !FoundTombs tone)
FoundTombstone = ThisBucket; // Remember the first tombstone found . FoundTombstone = ThisBucket; // Remember the first tombstone found .
// Otherwise, it's a hash collision or a tombstone, continue quadrati c // Otherwise, it's a hash collision or a tombstone, continue quadrati c
// probing. // probing.
BucketNo += ProbeAmt++; BucketNo += ProbeAmt++;
BucketNo &= (NumBuckets-1);
} }
} }
void init(unsigned InitBuckets) { template <typename LookupKeyT>
NumEntries = 0; bool LookupBucketFor(const LookupKeyT &Val, BucketT *&FoundBucket) {
NumTombstones = 0; const BucketT *ConstFoundBucket;
NumBuckets = InitBuckets; bool Result = const_cast<const DenseMapBase *>(this)
->LookupBucketFor(Val, ConstFoundBucket);
FoundBucket = const_cast<BucketT *>(ConstFoundBucket);
return Result;
}
if (InitBuckets == 0) { public:
Buckets = 0; /// Return the approximate size (in bytes) of the actual map.
return; /// This is just the raw memory used by DenseMap.
/// If entries are pointers to objects, the size of the referenced object
s
/// are not included.
size_t getMemorySize() const {
return getNumBuckets() * sizeof(BucketT);
}
};
template<typename KeyT, typename ValueT,
typename KeyInfoT = DenseMapInfo<KeyT> >
class DenseMap
: public DenseMapBase<DenseMap<KeyT, ValueT, KeyInfoT>,
KeyT, ValueT, KeyInfoT> {
// Lift some types from the dependent base class into this class for
// simplicity of referring to them.
typedef DenseMapBase<DenseMap, KeyT, ValueT, KeyInfoT> BaseT;
typedef typename BaseT::BucketT BucketT;
friend class DenseMapBase<DenseMap, KeyT, ValueT, KeyInfoT>;
BucketT *Buckets;
unsigned NumEntries;
unsigned NumTombstones;
unsigned NumBuckets;
public:
explicit DenseMap(unsigned NumInitBuckets = 0) {
init(NumInitBuckets);
}
DenseMap(const DenseMap &other) {
init(0);
copyFrom(other);
}
#if LLVM_USE_RVALUE_REFERENCES
DenseMap(DenseMap &&other) {
init(0);
swap(other);
}
#endif
template<typename InputIt>
DenseMap(const InputIt &I, const InputIt &E) {
init(NextPowerOf2(std::distance(I, E)));
this->insert(I, E);
}
~DenseMap() {
this->destroyAll();
operator delete(Buckets);
}
void swap(DenseMap& RHS) {
std::swap(Buckets, RHS.Buckets);
std::swap(NumEntries, RHS.NumEntries);
std::swap(NumTombstones, RHS.NumTombstones);
std::swap(NumBuckets, RHS.NumBuckets);
}
DenseMap& operator=(const DenseMap& other) {
copyFrom(other);
return *this;
}
#if LLVM_USE_RVALUE_REFERENCES
DenseMap& operator=(DenseMap &&other) {
this->destroyAll();
operator delete(Buckets);
init(0);
swap(other);
return *this;
}
#endif
void copyFrom(const DenseMap& other) {
this->destroyAll();
operator delete(Buckets);
if (allocateBuckets(other.NumBuckets)) {
this->BaseT::copyFrom(other);
} else {
NumEntries = 0;
NumTombstones = 0;
} }
}
assert(InitBuckets && (InitBuckets & (InitBuckets-1)) == 0 && void init(unsigned InitBuckets) {
"# initial buckets must be a power of two!"); if (allocateBuckets(InitBuckets)) {
Buckets = static_cast<BucketT*>(operator new(sizeof(BucketT)*InitBucket this->BaseT::initEmpty();
s)); } else {
// Initialize all the keys to EmptyKey. NumEntries = 0;
const KeyT EmptyKey = getEmptyKey(); NumTombstones = 0;
for (unsigned i = 0; i != InitBuckets; ++i) }
new (&Buckets[i].first) KeyT(EmptyKey);
} }
void grow(unsigned AtLeast) { void grow(unsigned AtLeast) {
unsigned OldNumBuckets = NumBuckets; unsigned OldNumBuckets = NumBuckets;
BucketT *OldBuckets = Buckets; BucketT *OldBuckets = Buckets;
if (NumBuckets < 64) allocateBuckets(std::max<unsigned>(64, NextPowerOf2(AtLeast-1)));
NumBuckets = 64; assert(Buckets);
if (!OldBuckets) {
this->BaseT::initEmpty();
return;
}
// Double the number of buckets. this->moveFromOldBuckets(OldBuckets, OldBuckets+OldNumBuckets);
while (NumBuckets < AtLeast)
NumBuckets <<= 1;
NumTombstones = 0;
Buckets = static_cast<BucketT*>(operator new(sizeof(BucketT)*NumBuckets
));
// Initialize all the keys to EmptyKey. // Free the old table.
const KeyT EmptyKey = getEmptyKey(); operator delete(OldBuckets);
for (unsigned i = 0, e = NumBuckets; i != e; ++i) }
new (&Buckets[i].first) KeyT(EmptyKey);
// Insert all the old elements. void shrink_and_clear() {
const KeyT TombstoneKey = getTombstoneKey(); unsigned OldNumEntries = NumEntries;
for (BucketT *B = OldBuckets, *E = OldBuckets+OldNumBuckets; B != E; ++ this->destroyAll();
B) {
if (!KeyInfoT::isEqual(B->first, EmptyKey) &&
!KeyInfoT::isEqual(B->first, TombstoneKey)) {
// Insert the key/value into the new table.
BucketT *DestBucket;
bool FoundVal = LookupBucketFor(B->first, DestBucket);
(void)FoundVal; // silence warning.
assert(!FoundVal && "Key already in new map?");
DestBucket->first = B->first;
new (&DestBucket->second) ValueT(B->second);
// Free the value. // Reduce the number of buckets.
B->second.~ValueT(); unsigned NewNumBuckets = 0;
} if (OldNumEntries)
B->first.~KeyT(); NewNumBuckets = std::max(64, 1 << (Log2_32_Ceil(OldNumEntries) + 1));
if (NewNumBuckets == NumBuckets) {
this->BaseT::initEmpty();
return;
} }
#ifndef NDEBUG operator delete(Buckets);
if (OldNumBuckets) init(NewNumBuckets);
memset((void*)OldBuckets, 0x5a, sizeof(BucketT)*OldNumBuckets); }
private:
unsigned getNumEntries() const {
return NumEntries;
}
void setNumEntries(unsigned Num) {
NumEntries = Num;
}
unsigned getNumTombstones() const {
return NumTombstones;
}
void setNumTombstones(unsigned Num) {
NumTombstones = Num;
}
BucketT *getBuckets() const {
return Buckets;
}
unsigned getNumBuckets() const {
return NumBuckets;
}
bool allocateBuckets(unsigned Num) {
NumBuckets = Num;
if (NumBuckets == 0) {
Buckets = 0;
return false;
}
Buckets = static_cast<BucketT*>(operator new(sizeof(BucketT) * NumBucke
ts));
return true;
}
};
template<typename KeyT, typename ValueT,
unsigned InlineBuckets = 4,
typename KeyInfoT = DenseMapInfo<KeyT> >
class SmallDenseMap
: public DenseMapBase<SmallDenseMap<KeyT, ValueT, InlineBuckets, KeyInf
oT>,
KeyT, ValueT, KeyInfoT> {
// Lift some types from the dependent base class into this class for
// simplicity of referring to them.
typedef DenseMapBase<SmallDenseMap, KeyT, ValueT, KeyInfoT> BaseT;
typedef typename BaseT::BucketT BucketT;
friend class DenseMapBase<SmallDenseMap, KeyT, ValueT, KeyInfoT>;
unsigned Small : 1;
unsigned NumEntries : 31;
unsigned NumTombstones;
struct LargeRep {
BucketT *Buckets;
unsigned NumBuckets;
};
/// A "union" of an inline bucket array and the struct representing
/// a large bucket. This union will be discriminated by the 'Small' bit.
AlignedCharArrayUnion<BucketT[InlineBuckets], LargeRep> storage;
public:
explicit SmallDenseMap(unsigned NumInitBuckets = 0) {
init(NumInitBuckets);
}
SmallDenseMap(const SmallDenseMap &other) {
init(0);
copyFrom(other);
}
#if LLVM_USE_RVALUE_REFERENCES
SmallDenseMap(SmallDenseMap &&other) {
init(0);
swap(other);
}
#endif #endif
// Free the old table.
operator delete(OldBuckets); template<typename InputIt>
SmallDenseMap(const InputIt &I, const InputIt &E) {
init(NextPowerOf2(std::distance(I, E)));
this->insert(I, E);
} }
void shrink_and_clear() { ~SmallDenseMap() {
unsigned OldNumBuckets = NumBuckets; this->destroyAll();
BucketT *OldBuckets = Buckets; deallocateBuckets();
}
// Reduce the number of buckets. void swap(SmallDenseMap& RHS) {
NumBuckets = NumEntries > 32 ? 1 << (Log2_32_Ceil(NumEntries) + 1) unsigned TmpNumEntries = RHS.NumEntries;
: 64; RHS.NumEntries = NumEntries;
NumTombstones = 0; NumEntries = TmpNumEntries;
Buckets = static_cast<BucketT*>(operator new(sizeof(BucketT)*NumBuckets std::swap(NumTombstones, RHS.NumTombstones);
));
// Initialize all the keys to EmptyKey. const KeyT EmptyKey = this->getEmptyKey();
const KeyT EmptyKey = getEmptyKey(); const KeyT TombstoneKey = this->getTombstoneKey();
for (unsigned i = 0, e = NumBuckets; i != e; ++i) if (Small && RHS.Small) {
new (&Buckets[i].first) KeyT(EmptyKey); // If we're swapping inline bucket arrays, we have to cope with some
of
// the tricky bits of DenseMap's storage system: the buckets are not
// fully initialized. Thus we swap every key, but we may have
// a one-directional move of the value.
for (unsigned i = 0, e = InlineBuckets; i != e; ++i) {
BucketT *LHSB = &getInlineBuckets()[i],
*RHSB = &RHS.getInlineBuckets()[i];
bool hasLHSValue = (!KeyInfoT::isEqual(LHSB->first, EmptyKey) &&
!KeyInfoT::isEqual(LHSB->first, TombstoneKey));
bool hasRHSValue = (!KeyInfoT::isEqual(RHSB->first, EmptyKey) &&
!KeyInfoT::isEqual(RHSB->first, TombstoneKey));
if (hasLHSValue && hasRHSValue) {
// Swap together if we can...
std::swap(*LHSB, *RHSB);
continue;
}
// Swap separately and handle any assymetry.
std::swap(LHSB->first, RHSB->first);
if (hasLHSValue) {
new (&RHSB->second) ValueT(llvm_move(LHSB->second));
LHSB->second.~ValueT();
} else if (hasRHSValue) {
new (&LHSB->second) ValueT(llvm_move(RHSB->second));
RHSB->second.~ValueT();
}
}
return;
}
if (!Small && !RHS.Small) {
std::swap(getLargeRep()->Buckets, RHS.getLargeRep()->Buckets);
std::swap(getLargeRep()->NumBuckets, RHS.getLargeRep()->NumBuckets);
return;
}
// Free the old buckets. SmallDenseMap &SmallSide = Small ? *this : RHS;
const KeyT TombstoneKey = getTombstoneKey(); SmallDenseMap &LargeSide = Small ? RHS : *this;
for (BucketT *B = OldBuckets, *E = OldBuckets+OldNumBuckets; B != E; ++
B) { // First stash the large side's rep and move the small side across.
if (!KeyInfoT::isEqual(B->first, EmptyKey) && LargeRep TmpRep = llvm_move(*LargeSide.getLargeRep());
!KeyInfoT::isEqual(B->first, TombstoneKey)) { LargeSide.getLargeRep()->~LargeRep();
// Free the value. LargeSide.Small = true;
B->second.~ValueT(); // This is similar to the standard move-from-old-buckets, but the bucke
t
// count hasn't actually rotated in this case. So we have to carefully
// move construct the keys and values into their new locations, but the
re
// is no need to re-hash things.
for (unsigned i = 0, e = InlineBuckets; i != e; ++i) {
BucketT *NewB = &LargeSide.getInlineBuckets()[i],
*OldB = &SmallSide.getInlineBuckets()[i];
new (&NewB->first) KeyT(llvm_move(OldB->first));
OldB->first.~KeyT();
if (!KeyInfoT::isEqual(NewB->first, EmptyKey) &&
!KeyInfoT::isEqual(NewB->first, TombstoneKey)) {
new (&NewB->second) ValueT(llvm_move(OldB->second));
OldB->second.~ValueT();
} }
B->first.~KeyT();
} }
#ifndef NDEBUG // The hard part of moving the small buckets across is done, just move
memset((void*)OldBuckets, 0x5a, sizeof(BucketT)*OldNumBuckets); // the TmpRep into its new home.
SmallSide.Small = false;
new (SmallSide.getLargeRep()) LargeRep(llvm_move(TmpRep));
}
SmallDenseMap& operator=(const SmallDenseMap& other) {
copyFrom(other);
return *this;
}
#if LLVM_USE_RVALUE_REFERENCES
SmallDenseMap& operator=(SmallDenseMap &&other) {
this->destroyAll();
deallocateBuckets();
init(0);
swap(other);
return *this;
}
#endif #endif
void copyFrom(const SmallDenseMap& other) {
this->destroyAll();
deallocateBuckets();
Small = true;
if (other.getNumBuckets() > InlineBuckets) {
Small = false;
allocateBuckets(other.getNumBuckets());
}
this->BaseT::copyFrom(other);
}
void init(unsigned InitBuckets) {
Small = true;
if (InitBuckets > InlineBuckets) {
Small = false;
new (getLargeRep()) LargeRep(allocateBuckets(InitBuckets));
}
this->BaseT::initEmpty();
}
void grow(unsigned AtLeast) {
if (AtLeast >= InlineBuckets)
AtLeast = std::max<unsigned>(64, NextPowerOf2(AtLeast-1));
if (Small) {
if (AtLeast < InlineBuckets)
return; // Nothing to do.
// First move the inline buckets into a temporary storage.
AlignedCharArrayUnion<BucketT[InlineBuckets]> TmpStorage;
BucketT *TmpBegin = reinterpret_cast<BucketT *>(TmpStorage.buffer);
BucketT *TmpEnd = TmpBegin;
// Loop over the buckets, moving non-empty, non-tombstones into the
// temporary storage. Have the loop move the TmpEnd forward as it goe
s.
const KeyT EmptyKey = this->getEmptyKey();
const KeyT TombstoneKey = this->getTombstoneKey();
for (BucketT *P = getBuckets(), *E = P + InlineBuckets; P != E; ++P)
{
if (!KeyInfoT::isEqual(P->first, EmptyKey) &&
!KeyInfoT::isEqual(P->first, TombstoneKey)) {
assert(size_t(TmpEnd - TmpBegin) < InlineBuckets &&
"Too many inline buckets!");
new (&TmpEnd->first) KeyT(llvm_move(P->first));
new (&TmpEnd->second) ValueT(llvm_move(P->second));
++TmpEnd;
P->second.~ValueT();
}
P->first.~KeyT();
}
// Now make this map use the large rep, and move all the entries back
// into it.
Small = false;
new (getLargeRep()) LargeRep(allocateBuckets(AtLeast));
this->moveFromOldBuckets(TmpBegin, TmpEnd);
return;
}
LargeRep OldRep = llvm_move(*getLargeRep());
getLargeRep()->~LargeRep();
if (AtLeast <= InlineBuckets) {
Small = true;
} else {
new (getLargeRep()) LargeRep(allocateBuckets(AtLeast));
}
this->moveFromOldBuckets(OldRep.Buckets, OldRep.Buckets+OldRep.NumBucke
ts);
// Free the old table. // Free the old table.
operator delete(OldBuckets); operator delete(OldRep.Buckets);
}
void shrink_and_clear() {
unsigned OldSize = this->size();
this->destroyAll();
NumEntries = 0; // Reduce the number of buckets.
unsigned NewNumBuckets = 0;
if (OldSize) {
NewNumBuckets = 1 << (Log2_32_Ceil(OldSize) + 1);
if (NewNumBuckets > InlineBuckets && NewNumBuckets < 64u)
NewNumBuckets = 64;
}
if ((Small && NewNumBuckets <= InlineBuckets) ||
(!Small && NewNumBuckets == getLargeRep()->NumBuckets)) {
this->BaseT::initEmpty();
return;
}
deallocateBuckets();
init(NewNumBuckets);
} }
public: private:
/// Return the approximate size (in bytes) of the actual map. unsigned getNumEntries() const {
/// This is just the raw memory used by DenseMap. return NumEntries;
/// If entries are pointers to objects, the size of the referenced object }
s void setNumEntries(unsigned Num) {
/// are not included. assert(Num < INT_MAX && "Cannot support more than INT_MAX entries");
size_t getMemorySize() const { NumEntries = Num;
return NumBuckets * sizeof(BucketT); }
unsigned getNumTombstones() const {
return NumTombstones;
}
void setNumTombstones(unsigned Num) {
NumTombstones = Num;
}
const BucketT *getInlineBuckets() const {
assert(Small);
// Note that this cast does not violate aliasing rules as we assert tha
t
// the memory's dynamic type is the small, inline bucket buffer, and th
e
// 'storage.buffer' static type is 'char *'.
return reinterpret_cast<const BucketT *>(storage.buffer);
}
BucketT *getInlineBuckets() {
return const_cast<BucketT *>(
const_cast<const SmallDenseMap *>(this)->getInlineBuckets());
}
const LargeRep *getLargeRep() const {
assert(!Small);
// Note, same rule about aliasing as with getInlineBuckets.
return reinterpret_cast<const LargeRep *>(storage.buffer);
}
LargeRep *getLargeRep() {
return const_cast<LargeRep *>(
const_cast<const SmallDenseMap *>(this)->getLargeRep());
}
const BucketT *getBuckets() const {
return Small ? getInlineBuckets() : getLargeRep()->Buckets;
}
BucketT *getBuckets() {
return const_cast<BucketT *>(
const_cast<const SmallDenseMap *>(this)->getBuckets());
}
unsigned getNumBuckets() const {
return Small ? InlineBuckets : getLargeRep()->NumBuckets;
}
void deallocateBuckets() {
if (Small)
return;
operator delete(getLargeRep()->Buckets);
getLargeRep()->~LargeRep();
}
LargeRep allocateBuckets(unsigned Num) {
assert(Num > InlineBuckets && "Must allocate more buckets than are inli
ne");
LargeRep Rep = {
static_cast<BucketT*>(operator new(sizeof(BucketT) * Num)), Num
};
return Rep;
} }
}; };
template<typename KeyT, typename ValueT, template<typename KeyT, typename ValueT,
typename KeyInfoT, bool IsConst> typename KeyInfoT, bool IsConst>
class DenseMapIterator { class DenseMapIterator {
typedef std::pair<KeyT, ValueT> Bucket; typedef std::pair<KeyT, ValueT> Bucket;
typedef DenseMapIterator<KeyT, ValueT, typedef DenseMapIterator<KeyT, ValueT,
KeyInfoT, true> ConstIterator; KeyInfoT, true> ConstIterator;
friend class DenseMapIterator<KeyT, ValueT, KeyInfoT, true>; friend class DenseMapIterator<KeyT, ValueT, KeyInfoT, true>;
 End of changes. 78 change blocks. 
218 lines changed or deleted 688 lines changed or added


 DenseMapInfo.h   DenseMapInfo.h 
skipping to change at line 34 skipping to change at line 34
//static inline T getEmptyKey(); //static inline T getEmptyKey();
//static inline T getTombstoneKey(); //static inline T getTombstoneKey();
//static unsigned getHashValue(const T &Val); //static unsigned getHashValue(const T &Val);
//static bool isEqual(const T &LHS, const T &RHS); //static bool isEqual(const T &LHS, const T &RHS);
}; };
// Provide DenseMapInfo for all pointers. // Provide DenseMapInfo for all pointers.
template<typename T> template<typename T>
struct DenseMapInfo<T*> { struct DenseMapInfo<T*> {
static inline T* getEmptyKey() { static inline T* getEmptyKey() {
intptr_t Val = -1; uintptr_t Val = static_cast<uintptr_t>(-1);
Val <<= PointerLikeTypeTraits<T*>::NumLowBitsAvailable; Val <<= PointerLikeTypeTraits<T*>::NumLowBitsAvailable;
return reinterpret_cast<T*>(Val); return reinterpret_cast<T*>(Val);
} }
static inline T* getTombstoneKey() { static inline T* getTombstoneKey() {
intptr_t Val = -2; uintptr_t Val = static_cast<uintptr_t>(-2);
Val <<= PointerLikeTypeTraits<T*>::NumLowBitsAvailable; Val <<= PointerLikeTypeTraits<T*>::NumLowBitsAvailable;
return reinterpret_cast<T*>(Val); return reinterpret_cast<T*>(Val);
} }
static unsigned getHashValue(const T *PtrVal) { static unsigned getHashValue(const T *PtrVal) {
return (unsigned((uintptr_t)PtrVal) >> 4) ^ return (unsigned((uintptr_t)PtrVal) >> 4) ^
(unsigned((uintptr_t)PtrVal) >> 9); (unsigned((uintptr_t)PtrVal) >> 9);
} }
static bool isEqual(const T *LHS, const T *RHS) { return LHS == RHS; } static bool isEqual(const T *LHS, const T *RHS) { return LHS == RHS; }
}; };
skipping to change at line 108 skipping to change at line 108
static inline int getTombstoneKey() { return -0x7fffffff - 1; } static inline int getTombstoneKey() { return -0x7fffffff - 1; }
static unsigned getHashValue(const int& Val) { return (unsigned)(Val * 37 U); } static unsigned getHashValue(const int& Val) { return (unsigned)(Val * 37 U); }
static bool isEqual(const int& LHS, const int& RHS) { static bool isEqual(const int& LHS, const int& RHS) {
return LHS == RHS; return LHS == RHS;
} }
}; };
// Provide DenseMapInfo for longs. // Provide DenseMapInfo for longs.
template<> struct DenseMapInfo<long> { template<> struct DenseMapInfo<long> {
static inline long getEmptyKey() { static inline long getEmptyKey() {
return (1UL << (sizeof(long) * 8 - 1)) - 1L; return (1UL << (sizeof(long) * 8 - 1)) - 1UL;
} }
static inline long getTombstoneKey() { return getEmptyKey() - 1L; } static inline long getTombstoneKey() { return getEmptyKey() - 1L; }
static unsigned getHashValue(const long& Val) { static unsigned getHashValue(const long& Val) {
return (unsigned)(Val * 37UL); return (unsigned)(Val * 37UL);
} }
static bool isEqual(const long& LHS, const long& RHS) { static bool isEqual(const long& LHS, const long& RHS) {
return LHS == RHS; return LHS == RHS;
} }
}; };
 End of changes. 3 change blocks. 
3 lines changed or deleted 3 lines changed or added


 DepthFirstIterator.h   DepthFirstIterator.h 
skipping to change at line 189 skipping to change at line 189
// nodes that a depth first iteration did not find: ie unreachable nodes. // nodes that a depth first iteration did not find: ie unreachable nodes.
// //
inline bool nodeVisited(NodeType *Node) const { inline bool nodeVisited(NodeType *Node) const {
return this->Visited.count(Node) != 0; return this->Visited.count(Node) != 0;
} }
/// getPathLength - Return the length of the path from the entry node to the /// getPathLength - Return the length of the path from the entry node to the
/// current node, counting both nodes. /// current node, counting both nodes.
unsigned getPathLength() const { return VisitStack.size(); } unsigned getPathLength() const { return VisitStack.size(); }
/// getPath - Return the n'th node in the path from the the entry node to the /// getPath - Return the n'th node in the path from the entry node to the
/// current node. /// current node.
NodeType *getPath(unsigned n) const { NodeType *getPath(unsigned n) const {
return VisitStack[n].first.getPointer(); return VisitStack[n].first.getPointer();
} }
}; };
// Provide global constructors that automatically figure out correct types. .. // Provide global constructors that automatically figure out correct types. ..
// //
template <class T> template <class T>
df_iterator<T> df_begin(const T& G) { df_iterator<T> df_begin(const T& G) {
 End of changes. 1 change blocks. 
1 lines changed or deleted 1 lines changed or added


 DerivedTypes.h   DerivedTypes.h 
skipping to change at line 23 skipping to change at line 23
// //
// The implementations of these classes live in the Type.cpp file. // The implementations of these classes live in the Type.cpp file.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_DERIVED_TYPES_H #ifndef LLVM_DERIVED_TYPES_H
#define LLVM_DERIVED_TYPES_H #define LLVM_DERIVED_TYPES_H
#include "llvm/Type.h" #include "llvm/Type.h"
#include "llvm/Support/DataTypes.h" #include "llvm/Support/DataTypes.h"
#include "llvm/Support/Compiler.h"
namespace llvm { namespace llvm {
class Value; class Value;
class APInt; class APInt;
class LLVMContext; class LLVMContext;
template<typename T> class ArrayRef; template<typename T> class ArrayRef;
class StringRef; class StringRef;
/// Class to represent integer types. Note that this class is also used to /// Class to represent integer types. Note that this class is also used to
skipping to change at line 87 skipping to change at line 88
/// @brief Get a bit mask for this type. /// @brief Get a bit mask for this type.
APInt getMask() const; APInt getMask() const;
/// This method determines if the width of this IntegerType is a power-of -2 /// This method determines if the width of this IntegerType is a power-of -2
/// in terms of 8 bit bytes. /// in terms of 8 bit bytes.
/// @returns true if this is a power-of-2 byte width. /// @returns true if this is a power-of-2 byte width.
/// @brief Is this a power-of-2 byte-width IntegerType ? /// @brief Is this a power-of-2 byte-width IntegerType ?
bool isPowerOf2ByteWidth() const; bool isPowerOf2ByteWidth() const;
// Methods for support type inquiry through isa, cast, and dyn_cast. // Methods for support type inquiry through isa, cast, and dyn_cast.
static inline bool classof(const IntegerType *) { return true; }
static inline bool classof(const Type *T) { static inline bool classof(const Type *T) {
return T->getTypeID() == IntegerTyID; return T->getTypeID() == IntegerTyID;
} }
}; };
/// FunctionType - Class to represent function types /// FunctionType - Class to represent function types
/// ///
class FunctionType : public Type { class FunctionType : public Type {
FunctionType(const FunctionType &); // Do not implement FunctionType(const FunctionType &) LLVM_DELETED_FUNCTION;
const FunctionType &operator=(const FunctionType &); // Do not implement const FunctionType &operator=(const FunctionType &) LLVM_DELETED_FUNCTION
;
FunctionType(Type *Result, ArrayRef<Type*> Params, bool IsVarArgs); FunctionType(Type *Result, ArrayRef<Type*> Params, bool IsVarArgs);
public: public:
/// FunctionType::get - This static method is the primary way of construc ting /// FunctionType::get - This static method is the primary way of construc ting
/// a FunctionType. /// a FunctionType.
/// ///
static FunctionType *get(Type *Result, static FunctionType *get(Type *Result,
ArrayRef<Type*> Params, bool isVarArg); ArrayRef<Type*> Params, bool isVarArg);
/// FunctionType::get - Create a FunctionType taking no parameters. /// FunctionType::get - Create a FunctionType taking no parameters.
skipping to change at line 135 skipping to change at line 135
// Parameter type accessors. // Parameter type accessors.
Type *getParamType(unsigned i) const { return ContainedTys[i+1]; } Type *getParamType(unsigned i) const { return ContainedTys[i+1]; }
/// getNumParams - Return the number of fixed parameters this function ty pe /// getNumParams - Return the number of fixed parameters this function ty pe
/// requires. This does not consider varargs. /// requires. This does not consider varargs.
/// ///
unsigned getNumParams() const { return NumContainedTys - 1; } unsigned getNumParams() const { return NumContainedTys - 1; }
// Methods for support type inquiry through isa, cast, and dyn_cast. // Methods for support type inquiry through isa, cast, and dyn_cast.
static inline bool classof(const FunctionType *) { return true; }
static inline bool classof(const Type *T) { static inline bool classof(const Type *T) {
return T->getTypeID() == FunctionTyID; return T->getTypeID() == FunctionTyID;
} }
}; };
/// CompositeType - Common super class of ArrayType, StructType, PointerTyp e /// CompositeType - Common super class of ArrayType, StructType, PointerTyp e
/// and VectorType. /// and VectorType.
class CompositeType : public Type { class CompositeType : public Type {
protected: protected:
explicit CompositeType(LLVMContext &C, TypeID tid) : Type(C, tid) { } explicit CompositeType(LLVMContext &C, TypeID tid) : Type(C, tid) { }
skipping to change at line 157 skipping to change at line 156
/// getTypeAtIndex - Given an index value into the type, return the type of /// getTypeAtIndex - Given an index value into the type, return the type of
/// the element. /// the element.
/// ///
Type *getTypeAtIndex(const Value *V); Type *getTypeAtIndex(const Value *V);
Type *getTypeAtIndex(unsigned Idx); Type *getTypeAtIndex(unsigned Idx);
bool indexValid(const Value *V) const; bool indexValid(const Value *V) const;
bool indexValid(unsigned Idx) const; bool indexValid(unsigned Idx) const;
// Methods for support type inquiry through isa, cast, and dyn_cast. // Methods for support type inquiry through isa, cast, and dyn_cast.
static inline bool classof(const CompositeType *) { return true; }
static inline bool classof(const Type *T) { static inline bool classof(const Type *T) {
return T->getTypeID() == ArrayTyID || return T->getTypeID() == ArrayTyID ||
T->getTypeID() == StructTyID || T->getTypeID() == StructTyID ||
T->getTypeID() == PointerTyID || T->getTypeID() == PointerTyID ||
T->getTypeID() == VectorTyID; T->getTypeID() == VectorTyID;
} }
}; };
/// StructType - Class to represent struct types. There are two different kinds /// StructType - Class to represent struct types. There are two different kinds
/// of struct types: Literal structs and Identified structs. /// of struct types: Literal structs and Identified structs.
skipping to change at line 183 skipping to change at line 181
/// Identified structs (e.g. %foo or %42) may optionally have a name and ar e not /// Identified structs (e.g. %foo or %42) may optionally have a name and ar e not
/// uniqued. The names for identified structs are managed at the LLVMConte xt /// uniqued. The names for identified structs are managed at the LLVMConte xt
/// level, so there can only be a single identified struct with a given nam e in /// level, so there can only be a single identified struct with a given nam e in
/// a particular LLVMContext. Identified structs may also optionally be op aque /// a particular LLVMContext. Identified structs may also optionally be op aque
/// (have no body specified). You get one of these by using one of the /// (have no body specified). You get one of these by using one of the
/// StructType::create() forms. /// StructType::create() forms.
/// ///
/// Independent of what kind of struct you have, the body of a struct type are /// Independent of what kind of struct you have, the body of a struct type are
/// laid out in memory consequtively with the elements directly one after t he /// laid out in memory consequtively with the elements directly one after t he
/// other (if the struct is packed) or (if not packed) with padding between the /// other (if the struct is packed) or (if not packed) with padding between the
/// elements as defined by TargetData (which is required to match what the code /// elements as defined by DataLayout (which is required to match what the code
/// generator for a target expects). /// generator for a target expects).
/// ///
class StructType : public CompositeType { class StructType : public CompositeType {
StructType(const StructType &); // Do not implement StructType(const StructType &) LLVM_DELETED_FUNCTION;
const StructType &operator=(const StructType &); // Do not implement const StructType &operator=(const StructType &) LLVM_DELETED_FUNCTION;
StructType(LLVMContext &C) StructType(LLVMContext &C)
: CompositeType(C, StructTyID), SymbolTableEntry(0) {} : CompositeType(C, StructTyID), SymbolTableEntry(0) {}
enum { enum {
// This is the contents of the SubClassData field. // This is the contents of the SubClassData field.
SCDB_HasBody = 1, SCDB_HasBody = 1,
SCDB_Packed = 2, SCDB_Packed = 2,
SCDB_IsLiteral = 4, SCDB_IsLiteral = 4,
SCDB_IsSized = 8 SCDB_IsSized = 8
}; };
skipping to change at line 291 skipping to change at line 289
bool isLayoutIdentical(StructType *Other) const; bool isLayoutIdentical(StructType *Other) const;
// Random access to the elements // Random access to the elements
unsigned getNumElements() const { return NumContainedTys; } unsigned getNumElements() const { return NumContainedTys; }
Type *getElementType(unsigned N) const { Type *getElementType(unsigned N) const {
assert(N < NumContainedTys && "Element number out of range!"); assert(N < NumContainedTys && "Element number out of range!");
return ContainedTys[N]; return ContainedTys[N];
} }
// Methods for support type inquiry through isa, cast, and dyn_cast. // Methods for support type inquiry through isa, cast, and dyn_cast.
static inline bool classof(const StructType *) { return true; }
static inline bool classof(const Type *T) { static inline bool classof(const Type *T) {
return T->getTypeID() == StructTyID; return T->getTypeID() == StructTyID;
} }
}; };
/// SequentialType - This is the superclass of the array, pointer and vecto r /// SequentialType - This is the superclass of the array, pointer and vecto r
/// type classes. All of these represent "arrays" in memory. The array ty pe /// type classes. All of these represent "arrays" in memory. The array ty pe
/// represents a specifically sized array, pointer types are unsized/unknow n /// represents a specifically sized array, pointer types are unsized/unknow n
/// size arrays, vector types represent specifically sized arrays that /// size arrays, vector types represent specifically sized arrays that
/// allow for use of SIMD instructions. SequentialType holds the common /// allow for use of SIMD instructions. SequentialType holds the common
/// features of all, which stem from the fact that all three lay their /// features of all, which stem from the fact that all three lay their
/// components out in memory identically. /// components out in memory identically.
/// ///
class SequentialType : public CompositeType { class SequentialType : public CompositeType {
Type *ContainedType; ///< Storage for the single contained type. Type *ContainedType; ///< Storage for the single contained type.
SequentialType(const SequentialType &); // Do not implem SequentialType(const SequentialType &) LLVM_DELETED_FUNCTION;
ent! const SequentialType &operator=(const SequentialType &) LLVM_DELETED_FUNC
const SequentialType &operator=(const SequentialType &); // Do not implem TION;
ent!
protected: protected:
SequentialType(TypeID TID, Type *ElType) SequentialType(TypeID TID, Type *ElType)
: CompositeType(ElType->getContext(), TID), ContainedType(ElType) { : CompositeType(ElType->getContext(), TID), ContainedType(ElType) {
ContainedTys = &ContainedType; ContainedTys = &ContainedType;
NumContainedTys = 1; NumContainedTys = 1;
} }
public: public:
Type *getElementType() const { return ContainedTys[0]; } Type *getElementType() const { return ContainedTys[0]; }
// Methods for support type inquiry through isa, cast, and dyn_cast. // Methods for support type inquiry through isa, cast, and dyn_cast.
static inline bool classof(const SequentialType *) { return true; }
static inline bool classof(const Type *T) { static inline bool classof(const Type *T) {
return T->getTypeID() == ArrayTyID || return T->getTypeID() == ArrayTyID ||
T->getTypeID() == PointerTyID || T->getTypeID() == PointerTyID ||
T->getTypeID() == VectorTyID; T->getTypeID() == VectorTyID;
} }
}; };
/// ArrayType - Class to represent array types. /// ArrayType - Class to represent array types.
/// ///
class ArrayType : public SequentialType { class ArrayType : public SequentialType {
uint64_t NumElements; uint64_t NumElements;
ArrayType(const ArrayType &); // Do not implement ArrayType(const ArrayType &) LLVM_DELETED_FUNCTION;
const ArrayType &operator=(const ArrayType &); // Do not implement const ArrayType &operator=(const ArrayType &) LLVM_DELETED_FUNCTION;
ArrayType(Type *ElType, uint64_t NumEl); ArrayType(Type *ElType, uint64_t NumEl);
public: public:
/// ArrayType::get - This static method is the primary way to construct a n /// ArrayType::get - This static method is the primary way to construct a n
/// ArrayType /// ArrayType
/// ///
static ArrayType *get(Type *ElementType, uint64_t NumElements); static ArrayType *get(Type *ElementType, uint64_t NumElements);
/// isValidElementType - Return true if the specified type is valid as a /// isValidElementType - Return true if the specified type is valid as a
/// element type. /// element type.
static bool isValidElementType(Type *ElemTy); static bool isValidElementType(Type *ElemTy);
uint64_t getNumElements() const { return NumElements; } uint64_t getNumElements() const { return NumElements; }
// Methods for support type inquiry through isa, cast, and dyn_cast. // Methods for support type inquiry through isa, cast, and dyn_cast.
static inline bool classof(const ArrayType *) { return true; }
static inline bool classof(const Type *T) { static inline bool classof(const Type *T) {
return T->getTypeID() == ArrayTyID; return T->getTypeID() == ArrayTyID;
} }
}; };
/// VectorType - Class to represent vector types. /// VectorType - Class to represent vector types.
/// ///
class VectorType : public SequentialType { class VectorType : public SequentialType {
unsigned NumElements; unsigned NumElements;
VectorType(const VectorType &); // Do not implement VectorType(const VectorType &) LLVM_DELETED_FUNCTION;
const VectorType &operator=(const VectorType &); // Do not implement const VectorType &operator=(const VectorType &) LLVM_DELETED_FUNCTION;
VectorType(Type *ElType, unsigned NumEl); VectorType(Type *ElType, unsigned NumEl);
public: public:
/// VectorType::get - This static method is the primary way to construct an /// VectorType::get - This static method is the primary way to construct an
/// VectorType. /// VectorType.
/// ///
static VectorType *get(Type *ElementType, unsigned NumElements); static VectorType *get(Type *ElementType, unsigned NumElements);
/// VectorType::getInteger - This static method gets a VectorType with th e /// VectorType::getInteger - This static method gets a VectorType with th e
/// same number of elements as the input type, and the element type is an /// same number of elements as the input type, and the element type is an
/// integer type of the same width as the input element type. /// integer type of the same width as the input element type.
skipping to change at line 417 skipping to change at line 412
/// @brief Return the number of elements in the Vector type. /// @brief Return the number of elements in the Vector type.
unsigned getNumElements() const { return NumElements; } unsigned getNumElements() const { return NumElements; }
/// @brief Return the number of bits in the Vector type. /// @brief Return the number of bits in the Vector type.
/// Returns zero when the vector is a vector of pointers. /// Returns zero when the vector is a vector of pointers.
unsigned getBitWidth() const { unsigned getBitWidth() const {
return NumElements * getElementType()->getPrimitiveSizeInBits(); return NumElements * getElementType()->getPrimitiveSizeInBits();
} }
// Methods for support type inquiry through isa, cast, and dyn_cast. // Methods for support type inquiry through isa, cast, and dyn_cast.
static inline bool classof(const VectorType *) { return true; }
static inline bool classof(const Type *T) { static inline bool classof(const Type *T) {
return T->getTypeID() == VectorTyID; return T->getTypeID() == VectorTyID;
} }
}; };
/// PointerType - Class to represent pointers. /// PointerType - Class to represent pointers.
/// ///
class PointerType : public SequentialType { class PointerType : public SequentialType {
PointerType(const PointerType &); // Do not implement PointerType(const PointerType &) LLVM_DELETED_FUNCTION;
const PointerType &operator=(const PointerType &); // Do not implement const PointerType &operator=(const PointerType &) LLVM_DELETED_FUNCTION;
explicit PointerType(Type *ElType, unsigned AddrSpace); explicit PointerType(Type *ElType, unsigned AddrSpace);
public: public:
/// PointerType::get - This constructs a pointer to an object of the spec ified /// PointerType::get - This constructs a pointer to an object of the spec ified
/// type in a numbered address space. /// type in a numbered address space.
static PointerType *get(Type *ElementType, unsigned AddressSpace); static PointerType *get(Type *ElementType, unsigned AddressSpace);
/// PointerType::getUnqual - This constructs a pointer to an object of th e /// PointerType::getUnqual - This constructs a pointer to an object of th e
/// specified type in the generic address space (address space zero). /// specified type in the generic address space (address space zero).
static PointerType *getUnqual(Type *ElementType) { static PointerType *getUnqual(Type *ElementType) {
return PointerType::get(ElementType, 0); return PointerType::get(ElementType, 0);
} }
/// isValidElementType - Return true if the specified type is valid as a /// isValidElementType - Return true if the specified type is valid as a
/// element type. /// element type.
static bool isValidElementType(Type *ElemTy); static bool isValidElementType(Type *ElemTy);
/// @brief Return the address space of the Pointer type. /// @brief Return the address space of the Pointer type.
inline unsigned getAddressSpace() const { return getSubclassData(); } inline unsigned getAddressSpace() const { return getSubclassData(); }
// Implement support type inquiry through isa, cast, and dyn_cast. // Implement support type inquiry through isa, cast, and dyn_cast.
static inline bool classof(const PointerType *) { return true; }
static inline bool classof(const Type *T) { static inline bool classof(const Type *T) {
return T->getTypeID() == PointerTyID; return T->getTypeID() == PointerTyID;
} }
}; };
} // End llvm namespace } // End llvm namespace
#endif #endif
 End of changes. 16 change blocks. 
23 lines changed or deleted 16 lines changed or added


 Disassembler.h   Disassembler.h 
skipping to change at line 112 skipping to change at line 112
* It is passed the block information is saved when the disassembler contex t is * It is passed the block information is saved when the disassembler contex t is
* created and the ReferenceValue to look up as a symbol. If no symbol is found * created and the ReferenceValue to look up as a symbol. If no symbol is found
* for the ReferenceValue NULL is returned. The ReferenceType of the * for the ReferenceValue NULL is returned. The ReferenceType of the
* instruction is passed indirectly as is the PC of the instruction in * instruction is passed indirectly as is the PC of the instruction in
* ReferencePC. If the output reference can be determined its type is retu rned * ReferencePC. If the output reference can be determined its type is retu rned
* indirectly in ReferenceType along with ReferenceName if any, or that is set * indirectly in ReferenceType along with ReferenceName if any, or that is set
* to NULL. * to NULL.
*/ */
typedef const char *(*LLVMSymbolLookupCallback)(void *DisInfo, typedef const char *(*LLVMSymbolLookupCallback)(void *DisInfo,
uint64_t ReferenceValue, uint64_t ReferenceValue,
uint64_t *ReferenceType, uint64_t *ReferenceType,
uint64_t ReferencePC, uint64_t ReferencePC,
const char **ReferenceName); const char **ReferenceName)
;
/** /**
* The reference types on input and output. * The reference types on input and output.
*/ */
/* No input reference type or no output reference type. */ /* No input reference type or no output reference type. */
#define LLVMDisassembler_ReferenceType_InOut_None 0 #define LLVMDisassembler_ReferenceType_InOut_None 0
/* The input reference is from a branch instruction. */ /* The input reference is from a branch instruction. */
#define LLVMDisassembler_ReferenceType_In_Branch 1 #define LLVMDisassembler_ReferenceType_In_Branch 1
/* The input reference is from a PC relative load instruction. */ /* The input reference is from a PC relative load instruction. */
#define LLVMDisassembler_ReferenceType_In_PCrel_Load 2 #define LLVMDisassembler_ReferenceType_In_PCrel_Load 2
skipping to change at line 149 skipping to change at line 149
* by passing a block of information in the DisInfo parameter and specifyin g the * by passing a block of information in the DisInfo parameter and specifyin g the
* TagType and callback functions as described above. These can all be pas sed * TagType and callback functions as described above. These can all be pas sed
* as NULL. If successful, this returns a disassembler context. If not, i t * as NULL. If successful, this returns a disassembler context. If not, i t
* returns NULL. * returns NULL.
*/ */
LLVMDisasmContextRef LLVMCreateDisasm(const char *TripleName, void *DisInfo , LLVMDisasmContextRef LLVMCreateDisasm(const char *TripleName, void *DisInfo ,
int TagType, LLVMOpInfoCallback GetOp Info, int TagType, LLVMOpInfoCallback GetOp Info,
LLVMSymbolLookupCallback SymbolLookUp ); LLVMSymbolLookupCallback SymbolLookUp );
/** /**
* Set the disassembler's options. Returns 1 if it can set the Options and
0
* otherwise.
*/
int LLVMSetDisasmOptions(LLVMDisasmContextRef DC, uint64_t Options);
/* The option to produce marked up assembly. */
#define LLVMDisassembler_Option_UseMarkup 1
/**
* Dispose of a disassembler context. * Dispose of a disassembler context.
*/ */
void LLVMDisasmDispose(LLVMDisasmContextRef DC); void LLVMDisasmDispose(LLVMDisasmContextRef DC);
/** /**
* Disassemble a single instruction using the disassembler context specifie d in * Disassemble a single instruction using the disassembler context specifie d in
* the parameter DC. The bytes of the instruction are specified in the * the parameter DC. The bytes of the instruction are specified in the
* parameter Bytes, and contains at least BytesSize number of bytes. The * parameter Bytes, and contains at least BytesSize number of bytes. The
* instruction is at the address specified by the PC parameter. If a valid * instruction is at the address specified by the PC parameter. If a valid
* instruction can be disassembled, its string is returned indirectly in * instruction can be disassembled, its string is returned indirectly in
 End of changes. 2 change blocks. 
3 lines changed or deleted 14 lines changed or added


 Disassemblers.def   Disassemblers.def 
//===- llvm/Config/Disassemblers.def - LLVM Assembly Parsers ----*- C++ -*- /*===- llvm/Config/Disassemblers.def - LLVM Assembly Parsers ----*- C++ -*-
===// ===*\
// |*
// The LLVM Compiler Infrastructure *|
// |* The LLVM Compiler Infrastructure
// This file is distributed under the University of Illinois Open Source *|
// License. See LICENSE.TXT for details. |*
// *|
//===---------------------------------------------------------------------- |* This file is distributed under the University of Illinois Open Source
===// *|
// |* License. See LICENSE.TXT for details.
// This file enumerates all of the assembly-language parsers *|
// supported by this build of LLVM. Clients of this file should define |*
// the LLVM_DISASSEMBLER macro to be a function-like macro with a *|
// single parameter (the name of the target whose assembly can be |*===----------------------------------------------------------------------
// generated); including this file will then enumerate all of the ===*|
// targets with assembly parsers. |*
// *|
// The set of targets supported by LLVM is generated at configuration |* This file enumerates all of the assembly-language parsers
// time, at which point this header is generated. Do not modify this *|
// header directly. |* supported by this build of LLVM. Clients of this file should define
// *|
//===---------------------------------------------------------------------- |* the LLVM_DISASSEMBLER macro to be a function-like macro with a
===// *|
|* single parameter (the name of the target whose assembly can be
*|
|* generated); including this file will then enumerate all of the
*|
|* targets with assembly parsers.
*|
|*
*|
|* The set of targets supported by LLVM is generated at configuration
*|
|* time, at which point this header is generated. Do not modify this
*|
|* header directly.
*|
|*
*|
\*===----------------------------------------------------------------------
===*/
#ifndef LLVM_DISASSEMBLER #ifndef LLVM_DISASSEMBLER
# error Please define the macro LLVM_DISASSEMBLER(TargetName) # error Please define the macro LLVM_DISASSEMBLER(TargetName)
#endif #endif
LLVM_DISASSEMBLER(MBlaze) LLVM_DISASSEMBLER(Mips) LLVM_DISASSEMBLER(ARM) LL VM_DISASSEMBLER(X86) LLVM_DISASSEMBLER(MBlaze) LLVM_DISASSEMBLER(Mips) LLVM_DISASSEMBLER(ARM) LL VM_DISASSEMBLER(X86)
#undef LLVM_DISASSEMBLER #undef LLVM_DISASSEMBLER
 End of changes. 1 change blocks. 
24 lines changed or deleted 42 lines changed or added


 Dominators.h   Dominators.h 
skipping to change at line 154 skipping to change at line 154
bool DominatedBy(const DomTreeNodeBase<NodeT> *other) const { bool DominatedBy(const DomTreeNodeBase<NodeT> *other) const {
return this->DFSNumIn >= other->DFSNumIn && return this->DFSNumIn >= other->DFSNumIn &&
this->DFSNumOut <= other->DFSNumOut; this->DFSNumOut <= other->DFSNumOut;
} }
}; };
EXTERN_TEMPLATE_INSTANTIATION(class DomTreeNodeBase<BasicBlock>); EXTERN_TEMPLATE_INSTANTIATION(class DomTreeNodeBase<BasicBlock>);
EXTERN_TEMPLATE_INSTANTIATION(class DomTreeNodeBase<MachineBasicBlock>); EXTERN_TEMPLATE_INSTANTIATION(class DomTreeNodeBase<MachineBasicBlock>);
template<class NodeT> template<class NodeT>
static raw_ostream &operator<<(raw_ostream &o, inline raw_ostream &operator<<(raw_ostream &o,
const DomTreeNodeBase<NodeT> *Node) { const DomTreeNodeBase<NodeT> *Node) {
if (Node->getBlock()) if (Node->getBlock())
WriteAsOperand(o, Node->getBlock(), false); WriteAsOperand(o, Node->getBlock(), false);
else else
o << " <<exit node>>"; o << " <<exit node>>";
o << " {" << Node->getDFSNumIn() << "," << Node->getDFSNumOut() << "}"; o << " {" << Node->getDFSNumIn() << "," << Node->getDFSNumOut() << "}";
return o << "\n"; return o << "\n";
} }
template<class NodeT> template<class NodeT>
static void PrintDomTree(const DomTreeNodeBase<NodeT> *N, raw_ostream &o, inline void PrintDomTree(const DomTreeNodeBase<NodeT> *N, raw_ostream &o,
unsigned Lev) { unsigned Lev) {
o.indent(2*Lev) << "[" << Lev << "] " << N; o.indent(2*Lev) << "[" << Lev << "] " << N;
for (typename DomTreeNodeBase<NodeT>::const_iterator I = N->begin(), for (typename DomTreeNodeBase<NodeT>::const_iterator I = N->begin(),
E = N->end(); I != E; ++I) E = N->end(); I != E; ++I)
PrintDomTree<NodeT>(*I, o, Lev+1); PrintDomTree<NodeT>(*I, o, Lev+1);
} }
typedef DomTreeNodeBase<BasicBlock> DomTreeNode; typedef DomTreeNodeBase<BasicBlock> DomTreeNode;
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
skipping to change at line 348 skipping to change at line 348
/// getRootNode - This returns the entry node for the CFG of the function . If /// getRootNode - This returns the entry node for the CFG of the function . If
/// this tree represents the post-dominance relations for a function, how ever, /// this tree represents the post-dominance relations for a function, how ever,
/// this root may be a node with the block == NULL. This is the case whe n /// this root may be a node with the block == NULL. This is the case whe n
/// there are multiple exit nodes from a particular function. Consumers of /// there are multiple exit nodes from a particular function. Consumers of
/// post-dominance information must be capable of dealing with this /// post-dominance information must be capable of dealing with this
/// possibility. /// possibility.
/// ///
DomTreeNodeBase<NodeT> *getRootNode() { return RootNode; } DomTreeNodeBase<NodeT> *getRootNode() { return RootNode; }
const DomTreeNodeBase<NodeT> *getRootNode() const { return RootNode; } const DomTreeNodeBase<NodeT> *getRootNode() const { return RootNode; }
/// properlyDominates - Returns true iff this dominates N and this != N. /// properlyDominates - Returns true iff A dominates B and A != B.
/// Note that this is not a constant time operation! /// Note that this is not a constant time operation!
/// ///
bool properlyDominates(const DomTreeNodeBase<NodeT> *A, bool properlyDominates(const DomTreeNodeBase<NodeT> *A,
const DomTreeNodeBase<NodeT> *B) { const DomTreeNodeBase<NodeT> *B) {
if (A == 0 || B == 0) if (A == 0 || B == 0)
return false; return false;
if (A == B) if (A == B)
return false; return false;
return dominates(A, B); return dominates(A, B);
} }
skipping to change at line 707 skipping to change at line 707
// Cast away the const qualifiers here. This is ok since // Cast away the const qualifiers here. This is ok since
// this function doesn't actually return the values returned // this function doesn't actually return the values returned
// from getNode. // from getNode.
return dominates(getNode(const_cast<NodeT *>(A)), return dominates(getNode(const_cast<NodeT *>(A)),
getNode(const_cast<NodeT *>(B))); getNode(const_cast<NodeT *>(B)));
} }
EXTERN_TEMPLATE_INSTANTIATION(class DominatorTreeBase<BasicBlock>); EXTERN_TEMPLATE_INSTANTIATION(class DominatorTreeBase<BasicBlock>);
class BasicBlockEdge {
const BasicBlock *Start;
const BasicBlock *End;
public:
BasicBlockEdge(const BasicBlock *Start_, const BasicBlock *End_) :
Start(Start_), End(End_) { }
const BasicBlock *getStart() const {
return Start;
}
const BasicBlock *getEnd() const {
return End;
}
bool isSingleEdge() const;
};
//===------------------------------------- //===-------------------------------------
/// DominatorTree Class - Concrete subclass of DominatorTreeBase that is us ed to /// DominatorTree Class - Concrete subclass of DominatorTreeBase that is us ed to
/// compute a normal dominator tree. /// compute a normal dominator tree.
/// ///
class DominatorTree : public FunctionPass { class DominatorTree : public FunctionPass {
public: public:
static char ID; // Pass ID, replacement for typeid static char ID; // Pass ID, replacement for typeid
DominatorTreeBase<BasicBlock>* DT; DominatorTreeBase<BasicBlock>* DT;
DominatorTree() : FunctionPass(ID) { DominatorTree() : FunctionPass(ID) {
skipping to change at line 780 skipping to change at line 795
inline bool dominates(const BasicBlock* A, const BasicBlock* B) const { inline bool dominates(const BasicBlock* A, const BasicBlock* B) const {
return DT->dominates(A, B); return DT->dominates(A, B);
} }
// dominates - Return true if Def dominates a use in User. This performs // dominates - Return true if Def dominates a use in User. This performs
// the special checks necessary if Def and User are in the same basic blo ck. // the special checks necessary if Def and User are in the same basic blo ck.
// Note that Def doesn't dominate a use in Def itself! // Note that Def doesn't dominate a use in Def itself!
bool dominates(const Instruction *Def, const Use &U) const; bool dominates(const Instruction *Def, const Use &U) const;
bool dominates(const Instruction *Def, const Instruction *User) const; bool dominates(const Instruction *Def, const Instruction *User) const;
bool dominates(const Instruction *Def, const BasicBlock *BB) const; bool dominates(const Instruction *Def, const BasicBlock *BB) const;
bool dominates(const BasicBlockEdge &BBE, const Use &U) const;
bool dominates(const BasicBlockEdge &BBE, const BasicBlock *BB) const;
bool properlyDominates(const DomTreeNode *A, const DomTreeNode *B) const { bool properlyDominates(const DomTreeNode *A, const DomTreeNode *B) const {
return DT->properlyDominates(A, B); return DT->properlyDominates(A, B);
} }
bool properlyDominates(const BasicBlock *A, const BasicBlock *B) const { bool properlyDominates(const BasicBlock *A, const BasicBlock *B) const {
return DT->properlyDominates(A, B); return DT->properlyDominates(A, B);
} }
/// findNearestCommonDominator - Find nearest common dominator basic bloc k /// findNearestCommonDominator - Find nearest common dominator basic bloc k
 End of changes. 5 change blocks. 
3 lines changed or deleted 20 lines changed or added


 ELF.h   ELF.h 
skipping to change at line 220 skipping to change at line 220
Elf_Word vd_hash; // Hash of name Elf_Word vd_hash; // Hash of name
Elf_Word vd_aux; // Offset to the first Verdaux entry (in bytes) Elf_Word vd_aux; // Offset to the first Verdaux entry (in bytes)
Elf_Word vd_next; // Offset to the next Verdef entry (in bytes) Elf_Word vd_next; // Offset to the next Verdef entry (in bytes)
/// Get the first Verdaux entry for this Verdef. /// Get the first Verdaux entry for this Verdef.
const Elf_Verdaux *getAux() const { const Elf_Verdaux *getAux() const {
return reinterpret_cast<const Elf_Verdaux*>((const char*)this + vd_aux) ; return reinterpret_cast<const Elf_Verdaux*>((const char*)this + vd_aux) ;
} }
}; };
/// Elf_Verdaux: This is the structure of auxilary data in the SHT_GNU_verd ef /// Elf_Verdaux: This is the structure of auxiliary data in the SHT_GNU_ver def
/// section (.gnu.version_d). This structure is identical for ELF32 and ELF 64. /// section (.gnu.version_d). This structure is identical for ELF32 and ELF 64.
template<support::endianness target_endianness, bool is64Bits> template<support::endianness target_endianness, bool is64Bits>
struct Elf_Verdaux_Impl { struct Elf_Verdaux_Impl {
LLVM_ELF_IMPORT_TYPES(target_endianness, is64Bits) LLVM_ELF_IMPORT_TYPES(target_endianness, is64Bits)
Elf_Word vda_name; // Version name (offset in string table) Elf_Word vda_name; // Version name (offset in string table)
Elf_Word vda_next; // Offset to next Verdaux entry (in bytes) Elf_Word vda_next; // Offset to next Verdaux entry (in bytes)
}; };
/// Elf_Verneed: This is the structure of entries in the SHT_GNU_verneed /// Elf_Verneed: This is the structure of entries in the SHT_GNU_verneed
/// section (.gnu.version_r). This structure is identical for ELF32 and ELF 64. /// section (.gnu.version_r). This structure is identical for ELF32 and ELF 64.
skipping to change at line 391 skipping to change at line 391
uint32_t getSymbol() const { return (r_info >> 8); } uint32_t getSymbol() const { return (r_info >> 8); }
unsigned char getType() const { return (unsigned char) (r_info & 0x0ff); } unsigned char getType() const { return (unsigned char) (r_info & 0x0ff); }
void setSymbol(uint32_t s) { setSymbolAndType(s, getType()); } void setSymbol(uint32_t s) { setSymbolAndType(s, getType()); }
void setType(unsigned char t) { setSymbolAndType(getSymbol(), t); } void setType(unsigned char t) { setSymbolAndType(getSymbol(), t); }
void setSymbolAndType(uint32_t s, unsigned char t) { void setSymbolAndType(uint32_t s, unsigned char t) {
r_info = (s << 8) + t; r_info = (s << 8) + t;
} }
}; };
template<support::endianness target_endianness, bool is64Bits> template<support::endianness target_endianness, bool is64Bits>
struct Elf_Ehdr_Impl {
LLVM_ELF_IMPORT_TYPES(target_endianness, is64Bits)
unsigned char e_ident[ELF::EI_NIDENT]; // ELF Identification bytes
Elf_Half e_type; // Type of file (see ET_*)
Elf_Half e_machine; // Required architecture for this file (see EM_*)
Elf_Word e_version; // Must be equal to 1
Elf_Addr e_entry; // Address to jump to in order to start program
Elf_Off e_phoff; // Program header table's file offset, in bytes
Elf_Off e_shoff; // Section header table's file offset, in bytes
Elf_Word e_flags; // Processor-specific flags
Elf_Half e_ehsize; // Size of ELF header, in bytes
Elf_Half e_phentsize;// Size of an entry in the program header table
Elf_Half e_phnum; // Number of entries in the program header table
Elf_Half e_shentsize;// Size of an entry in the section header table
Elf_Half e_shnum; // Number of entries in the section header table
Elf_Half e_shstrndx; // Section header table index of section name
// string table
bool checkMagic() const {
return (memcmp(e_ident, ELF::ElfMagic, strlen(ELF::ElfMagic))) == 0;
}
unsigned char getFileClass() const { return e_ident[ELF::EI_CLASS]; }
unsigned char getDataEncoding() const { return e_ident[ELF::EI_DATA]; }
};
template<support::endianness target_endianness, bool is64Bits>
struct Elf_Phdr;
template<support::endianness target_endianness>
struct Elf_Phdr<target_endianness, false> {
LLVM_ELF_IMPORT_TYPES(target_endianness, false)
Elf_Word p_type; // Type of segment
Elf_Off p_offset; // FileOffset where segment is located, in bytes
Elf_Addr p_vaddr; // Virtual Address of beginning of segment
Elf_Addr p_paddr; // Physical address of beginning of segment (OS-specif
ic)
Elf_Word p_filesz; // Num. of bytes in file image of segment (may be zero
)
Elf_Word p_memsz; // Num. of bytes in mem image of segment (may be zero)
Elf_Word p_flags; // Segment flags
Elf_Word p_align; // Segment alignment constraint
};
template<support::endianness target_endianness>
struct Elf_Phdr<target_endianness, true> {
LLVM_ELF_IMPORT_TYPES(target_endianness, true)
Elf_Word p_type; // Type of segment
Elf_Word p_flags; // Segment flags
Elf_Off p_offset; // FileOffset where segment is located, in bytes
Elf_Addr p_vaddr; // Virtual Address of beginning of segment
Elf_Addr p_paddr; // Physical address of beginning of segment (OS-specif
ic)
Elf_Word p_filesz; // Num. of bytes in file image of segment (may be zero
)
Elf_Word p_memsz; // Num. of bytes in mem image of segment (may be zero)
Elf_Word p_align; // Segment alignment constraint
};
template<support::endianness target_endianness, bool is64Bits>
class ELFObjectFile : public ObjectFile { class ELFObjectFile : public ObjectFile {
LLVM_ELF_IMPORT_TYPES(target_endianness, is64Bits) LLVM_ELF_IMPORT_TYPES(target_endianness, is64Bits)
typedef Elf_Ehdr_Impl<target_endianness, is64Bits> Elf_Ehdr;
typedef Elf_Shdr_Impl<target_endianness, is64Bits> Elf_Shdr; typedef Elf_Shdr_Impl<target_endianness, is64Bits> Elf_Shdr;
typedef Elf_Sym_Impl<target_endianness, is64Bits> Elf_Sym; typedef Elf_Sym_Impl<target_endianness, is64Bits> Elf_Sym;
typedef Elf_Dyn_Impl<target_endianness, is64Bits> Elf_Dyn; typedef Elf_Dyn_Impl<target_endianness, is64Bits> Elf_Dyn;
typedef Elf_Rel_Impl<target_endianness, is64Bits, false> Elf_Rel; typedef Elf_Rel_Impl<target_endianness, is64Bits, false> Elf_Rel;
typedef Elf_Rel_Impl<target_endianness, is64Bits, true> Elf_Rela; typedef Elf_Rel_Impl<target_endianness, is64Bits, true> Elf_Rela;
typedef Elf_Verdef_Impl<target_endianness, is64Bits> Elf_Verdef; typedef Elf_Verdef_Impl<target_endianness, is64Bits> Elf_Verdef;
typedef Elf_Verdaux_Impl<target_endianness, is64Bits> Elf_Verdaux; typedef Elf_Verdaux_Impl<target_endianness, is64Bits> Elf_Verdaux;
typedef Elf_Verneed_Impl<target_endianness, is64Bits> Elf_Verneed; typedef Elf_Verneed_Impl<target_endianness, is64Bits> Elf_Verneed;
typedef Elf_Vernaux_Impl<target_endianness, is64Bits> Elf_Vernaux; typedef Elf_Vernaux_Impl<target_endianness, is64Bits> Elf_Vernaux;
typedef Elf_Versym_Impl<target_endianness, is64Bits> Elf_Versym; typedef Elf_Versym_Impl<target_endianness, is64Bits> Elf_Versym;
typedef DynRefImpl<target_endianness, is64Bits> DynRef; typedef DynRefImpl<target_endianness, is64Bits> DynRef;
typedef content_iterator<DynRef> dyn_iterator; typedef content_iterator<DynRef> dyn_iterator;
protected: protected:
struct Elf_Ehdr {
unsigned char e_ident[ELF::EI_NIDENT]; // ELF Identification bytes
Elf_Half e_type; // Type of file (see ET_*)
Elf_Half e_machine; // Required architecture for this file (see EM_*)
Elf_Word e_version; // Must be equal to 1
Elf_Addr e_entry; // Address to jump to in order to start program
Elf_Off e_phoff; // Program header table's file offset, in bytes
Elf_Off e_shoff; // Section header table's file offset, in bytes
Elf_Word e_flags; // Processor-specific flags
Elf_Half e_ehsize; // Size of ELF header, in bytes
Elf_Half e_phentsize;// Size of an entry in the program header table
Elf_Half e_phnum; // Number of entries in the program header table
Elf_Half e_shentsize;// Size of an entry in the section header table
Elf_Half e_shnum; // Number of entries in the section header table
Elf_Half e_shstrndx; // Section header table index of section name
// string table
bool checkMagic() const {
return (memcmp(e_ident, ELF::ElfMagic, strlen(ELF::ElfMagic))) == 0;
}
unsigned char getFileClass() const { return e_ident[ELF::EI_CLASS]; }
unsigned char getDataEncoding() const { return e_ident[ELF::EI_DATA]; }
};
// This flag is used for classof, to distinguish ELFObjectFile from // This flag is used for classof, to distinguish ELFObjectFile from
// its subclass. If more subclasses will be created, this flag will // its subclass. If more subclasses will be created, this flag will
// have to become an enum. // have to become an enum.
bool isDyldELFObject; bool isDyldELFObject;
private: private:
typedef SmallVector<const Elf_Shdr*, 1> Sections_t; typedef SmallVector<const Elf_Shdr*, 1> Sections_t;
typedef DenseMap<unsigned, unsigned> IndexMap_t; typedef DenseMap<unsigned, unsigned> IndexMap_t;
typedef DenseMap<const Elf_Shdr*, SmallVector<uint32_t, 1> > RelocMap_t; typedef DenseMap<const Elf_Shdr*, SmallVector<uint32_t, 1> > RelocMap_t;
skipping to change at line 461 skipping to change at line 494
const Elf_Shdr *dot_dynamic_sec; // .dynamic const Elf_Shdr *dot_dynamic_sec; // .dynamic
const Elf_Shdr *dot_gnu_version_sec; // .gnu.version const Elf_Shdr *dot_gnu_version_sec; // .gnu.version
const Elf_Shdr *dot_gnu_version_r_sec; // .gnu.version_r const Elf_Shdr *dot_gnu_version_r_sec; // .gnu.version_r
const Elf_Shdr *dot_gnu_version_d_sec; // .gnu.version_d const Elf_Shdr *dot_gnu_version_d_sec; // .gnu.version_d
// Pointer to SONAME entry in dynamic string table // Pointer to SONAME entry in dynamic string table
// This is set the first time getLoadName is called. // This is set the first time getLoadName is called.
mutable const char *dt_soname; mutable const char *dt_soname;
public:
/// \brief Iterate over relocations in a .rel or .rela section.
template<class RelocT>
class ELFRelocationIterator {
public:
typedef void difference_type;
typedef const RelocT value_type;
typedef std::forward_iterator_tag iterator_category;
typedef value_type &reference;
typedef value_type *pointer;
/// \brief Default construct iterator.
ELFRelocationIterator() : Section(0), Current(0) {}
ELFRelocationIterator(const Elf_Shdr *Sec, const char *Start)
: Section(Sec)
, Current(Start) {}
reference operator *() {
assert(Current && "Attempted to dereference an invalid iterator!");
return *reinterpret_cast<const RelocT*>(Current);
}
pointer operator ->() {
assert(Current && "Attempted to dereference an invalid iterator!");
return reinterpret_cast<const RelocT*>(Current);
}
bool operator ==(const ELFRelocationIterator &Other) {
return Section == Other.Section && Current == Other.Current;
}
bool operator !=(const ELFRelocationIterator &Other) {
return !(*this == Other);
}
ELFRelocationIterator &operator ++(int) {
assert(Current && "Attempted to increment an invalid iterator!");
Current += Section->sh_entsize;
return *this;
}
ELFRelocationIterator operator ++() {
ELFRelocationIterator Tmp = *this;
++*this;
return Tmp;
}
private:
const Elf_Shdr *Section;
const char *Current;
};
private:
// Records for each version index the corresponding Verdef or Vernaux ent ry. // Records for each version index the corresponding Verdef or Vernaux ent ry.
// This is filled the first time LoadVersionMap() is called. // This is filled the first time LoadVersionMap() is called.
class VersionMapEntry : public PointerIntPair<const void*, 1> { class VersionMapEntry : public PointerIntPair<const void*, 1> {
public: public:
// If the integer is 0, this is an Elf_Verdef*. // If the integer is 0, this is an Elf_Verdef*.
// If the integer is 1, this is an Elf_Vernaux*. // If the integer is 1, this is an Elf_Vernaux*.
VersionMapEntry() : PointerIntPair<const void*, 1>(NULL, 0) { } VersionMapEntry() : PointerIntPair<const void*, 1>(NULL, 0) { }
VersionMapEntry(const Elf_Verdef *verdef) VersionMapEntry(const Elf_Verdef *verdef)
: PointerIntPair<const void*, 1>(verdef, 0) { } : PointerIntPair<const void*, 1>(verdef, 0) { }
VersionMapEntry(const Elf_Vernaux *vernaux) VersionMapEntry(const Elf_Vernaux *vernaux)
skipping to change at line 507 skipping to change at line 593
template<typename T> template<typename T>
const T *getEntry(uint16_t Section, uint32_t Entry) const; const T *getEntry(uint16_t Section, uint32_t Entry) const;
template<typename T> template<typename T>
const T *getEntry(const Elf_Shdr *Section, uint32_t Entry) const; const T *getEntry(const Elf_Shdr *Section, uint32_t Entry) const;
const Elf_Shdr *getSection(DataRefImpl index) const; const Elf_Shdr *getSection(DataRefImpl index) const;
const Elf_Shdr *getSection(uint32_t index) const; const Elf_Shdr *getSection(uint32_t index) const;
const Elf_Rel *getRel(DataRefImpl Rel) const; const Elf_Rel *getRel(DataRefImpl Rel) const;
const Elf_Rela *getRela(DataRefImpl Rela) const; const Elf_Rela *getRela(DataRefImpl Rela) const;
const char *getString(uint32_t section, uint32_t offset) const; const char *getString(uint32_t section, uint32_t offset) const;
const char *getString(const Elf_Shdr *section, uint32_t offset) const ; const char *getString(const Elf_Shdr *section, uint32_t offset) const ;
error_code getSymbolName(const Elf_Shdr *section,
const Elf_Sym *Symb,
StringRef &Res) const;
error_code getSymbolVersion(const Elf_Shdr *section, error_code getSymbolVersion(const Elf_Shdr *section,
const Elf_Sym *Symb, const Elf_Sym *Symb,
StringRef &Version, StringRef &Version,
bool &IsDefault) const; bool &IsDefault) const;
void VerifyStrTab(const Elf_Shdr *sh) const; void VerifyStrTab(const Elf_Shdr *sh) const;
protected: protected:
const Elf_Sym *getSymbol(DataRefImpl Symb) const; // FIXME: Should be pr ivate? const Elf_Sym *getSymbol(DataRefImpl Symb) const; // FIXME: Should be pr ivate?
void validateSymbol(DataRefImpl Symb) const; void validateSymbol(DataRefImpl Symb) const;
public: public:
error_code getSymbolName(const Elf_Shdr *section,
const Elf_Sym *Symb,
StringRef &Res) const;
error_code getSectionName(const Elf_Shdr *section,
StringRef &Res) const;
const Elf_Dyn *getDyn(DataRefImpl DynData) const; const Elf_Dyn *getDyn(DataRefImpl DynData) const;
error_code getSymbolVersion(SymbolRef Symb, StringRef &Version, error_code getSymbolVersion(SymbolRef Symb, StringRef &Version,
bool &IsDefault) const; bool &IsDefault) const;
protected: protected:
virtual error_code getSymbolNext(DataRefImpl Symb, SymbolRef &Res) const; virtual error_code getSymbolNext(DataRefImpl Symb, SymbolRef &Res) const;
virtual error_code getSymbolName(DataRefImpl Symb, StringRef &Res) const; virtual error_code getSymbolName(DataRefImpl Symb, StringRef &Res) const;
virtual error_code getSymbolFileOffset(DataRefImpl Symb, uint64_t &Res) c onst; virtual error_code getSymbolFileOffset(DataRefImpl Symb, uint64_t &Res) c onst;
virtual error_code getSymbolAddress(DataRefImpl Symb, uint64_t &Res) cons t; virtual error_code getSymbolAddress(DataRefImpl Symb, uint64_t &Res) cons t;
virtual error_code getSymbolSize(DataRefImpl Symb, uint64_t &Res) const; virtual error_code getSymbolSize(DataRefImpl Symb, uint64_t &Res) const;
virtual error_code getSymbolNMTypeChar(DataRefImpl Symb, char &Res) const ; virtual error_code getSymbolNMTypeChar(DataRefImpl Symb, char &Res) const ;
virtual error_code getSymbolFlags(DataRefImpl Symb, uint32_t &Res) const; virtual error_code getSymbolFlags(DataRefImpl Symb, uint32_t &Res) const;
virtual error_code getSymbolType(DataRefImpl Symb, SymbolRef::Type &Res) const; virtual error_code getSymbolType(DataRefImpl Symb, SymbolRef::Type &Res) const;
virtual error_code getSymbolSection(DataRefImpl Symb, virtual error_code getSymbolSection(DataRefImpl Symb,
section_iterator &Res) const; section_iterator &Res) const;
virtual error_code getSymbolValue(DataRefImpl Symb, uint64_t &Val) const;
friend class DynRefImpl<target_endianness, is64Bits>; friend class DynRefImpl<target_endianness, is64Bits>;
virtual error_code getDynNext(DataRefImpl DynData, DynRef &Result) const; virtual error_code getDynNext(DataRefImpl DynData, DynRef &Result) const;
virtual error_code getLibraryNext(DataRefImpl Data, LibraryRef &Result) c onst; virtual error_code getLibraryNext(DataRefImpl Data, LibraryRef &Result) c onst;
virtual error_code getLibraryPath(DataRefImpl Data, StringRef &Res) const ; virtual error_code getLibraryPath(DataRefImpl Data, StringRef &Res) const ;
virtual error_code getSectionNext(DataRefImpl Sec, SectionRef &Res) const ; virtual error_code getSectionNext(DataRefImpl Sec, SectionRef &Res) const ;
virtual error_code getSectionName(DataRefImpl Sec, StringRef &Res) const; virtual error_code getSectionName(DataRefImpl Sec, StringRef &Res) const;
virtual error_code getSectionAddress(DataRefImpl Sec, uint64_t &Res) cons t; virtual error_code getSectionAddress(DataRefImpl Sec, uint64_t &Res) cons t;
virtual error_code getSectionSize(DataRefImpl Sec, uint64_t &Res) const; virtual error_code getSectionSize(DataRefImpl Sec, uint64_t &Res) const;
virtual error_code getSectionContents(DataRefImpl Sec, StringRef &Res) co nst; virtual error_code getSectionContents(DataRefImpl Sec, StringRef &Res) co nst;
virtual error_code getSectionAlignment(DataRefImpl Sec, uint64_t &Res) co nst; virtual error_code getSectionAlignment(DataRefImpl Sec, uint64_t &Res) co nst;
virtual error_code isSectionText(DataRefImpl Sec, bool &Res) const; virtual error_code isSectionText(DataRefImpl Sec, bool &Res) const;
virtual error_code isSectionData(DataRefImpl Sec, bool &Res) const; virtual error_code isSectionData(DataRefImpl Sec, bool &Res) const;
virtual error_code isSectionBSS(DataRefImpl Sec, bool &Res) const; virtual error_code isSectionBSS(DataRefImpl Sec, bool &Res) const;
virtual error_code isSectionRequiredForExecution(DataRefImpl Sec, virtual error_code isSectionRequiredForExecution(DataRefImpl Sec,
bool &Res) const; bool &Res) const;
virtual error_code isSectionVirtual(DataRefImpl Sec, bool &Res) const; virtual error_code isSectionVirtual(DataRefImpl Sec, bool &Res) const;
virtual error_code isSectionZeroInit(DataRefImpl Sec, bool &Res) const; virtual error_code isSectionZeroInit(DataRefImpl Sec, bool &Res) const;
virtual error_code isSectionReadOnlyData(DataRefImpl Sec, bool &Res) cons t;
virtual error_code sectionContainsSymbol(DataRefImpl Sec, DataRefImpl Sym b, virtual error_code sectionContainsSymbol(DataRefImpl Sec, DataRefImpl Sym b,
bool &Result) const; bool &Result) const;
virtual relocation_iterator getSectionRelBegin(DataRefImpl Sec) const; virtual relocation_iterator getSectionRelBegin(DataRefImpl Sec) const;
virtual relocation_iterator getSectionRelEnd(DataRefImpl Sec) const; virtual relocation_iterator getSectionRelEnd(DataRefImpl Sec) const;
virtual error_code getRelocationNext(DataRefImpl Rel, virtual error_code getRelocationNext(DataRefImpl Rel,
RelocationRef &Res) const; RelocationRef &Res) const;
virtual error_code getRelocationAddress(DataRefImpl Rel, virtual error_code getRelocationAddress(DataRefImpl Rel,
uint64_t &Res) const; uint64_t &Res) const;
virtual error_code getRelocationOffset(DataRefImpl Rel, virtual error_code getRelocationOffset(DataRefImpl Rel,
skipping to change at line 594 skipping to change at line 684
virtual section_iterator begin_sections() const; virtual section_iterator begin_sections() const;
virtual section_iterator end_sections() const; virtual section_iterator end_sections() const;
virtual library_iterator begin_libraries_needed() const; virtual library_iterator begin_libraries_needed() const;
virtual library_iterator end_libraries_needed() const; virtual library_iterator end_libraries_needed() const;
virtual dyn_iterator begin_dynamic_table() const; virtual dyn_iterator begin_dynamic_table() const;
virtual dyn_iterator end_dynamic_table() const; virtual dyn_iterator end_dynamic_table() const;
typedef ELFRelocationIterator<Elf_Rela> Elf_Rela_Iter;
typedef ELFRelocationIterator<Elf_Rel> Elf_Rel_Iter;
virtual Elf_Rela_Iter beginELFRela(const Elf_Shdr *sec) const {
return Elf_Rela_Iter(sec, (const char *)(base() + sec->sh_offset));
}
virtual Elf_Rela_Iter endELFRela(const Elf_Shdr *sec) const {
return Elf_Rela_Iter(sec, (const char *)
(base() + sec->sh_offset + sec->sh_size));
}
virtual Elf_Rel_Iter beginELFRel(const Elf_Shdr *sec) const {
return Elf_Rel_Iter(sec, (const char *)(base() + sec->sh_offset));
}
virtual Elf_Rel_Iter endELFRel(const Elf_Shdr *sec) const {
return Elf_Rel_Iter(sec, (const char *)
(base() + sec->sh_offset + sec->sh_size));
}
virtual uint8_t getBytesInAddress() const; virtual uint8_t getBytesInAddress() const;
virtual StringRef getFileFormatName() const; virtual StringRef getFileFormatName() const;
virtual StringRef getObjectType() const { return "ELF"; } virtual StringRef getObjectType() const { return "ELF"; }
virtual unsigned getArch() const; virtual unsigned getArch() const;
virtual StringRef getLoadName() const; virtual StringRef getLoadName() const;
virtual error_code getSectionContents(const Elf_Shdr *sec,
StringRef &Res) const;
uint64_t getNumSections() const; uint64_t getNumSections() const;
uint64_t getStringTableIndex() const; uint64_t getStringTableIndex() const;
ELF::Elf64_Word getSymbolTableIndex(const Elf_Sym *symb) const; ELF::Elf64_Word getSymbolTableIndex(const Elf_Sym *symb) const;
const Elf_Shdr *getSection(const Elf_Sym *symb) const; const Elf_Shdr *getSection(const Elf_Sym *symb) const;
const Elf_Shdr *getElfSection(section_iterator &It) const;
const Elf_Sym *getElfSymbol(symbol_iterator &It) const;
const Elf_Sym *getElfSymbol(uint32_t index) const;
// Methods for type inquiry through isa, cast, and dyn_cast // Methods for type inquiry through isa, cast, and dyn_cast
bool isDyldType() const { return isDyldELFObject; } bool isDyldType() const { return isDyldELFObject; }
static inline bool classof(const Binary *v) { static inline bool classof(const Binary *v) {
return v->getType() == getELFType(target_endianness == support::little, return v->getType() == getELFType(target_endianness == support::little,
is64Bits); is64Bits);
} }
static inline bool classof(const ELFObjectFile *v) { return true; }
}; };
// Iterate through the version definitions, and place each Elf_Verdef // Iterate through the version definitions, and place each Elf_Verdef
// in the VersionMap according to its index. // in the VersionMap according to its index.
template<support::endianness target_endianness, bool is64Bits> template<support::endianness target_endianness, bool is64Bits>
void ELFObjectFile<target_endianness, is64Bits>:: void ELFObjectFile<target_endianness, is64Bits>::
LoadVersionDefs(const Elf_Shdr *sec) const { LoadVersionDefs(const Elf_Shdr *sec) const {
unsigned vd_size = sec->sh_size; // Size of section in bytes unsigned vd_size = sec->sh_size; // Size of section in bytes
unsigned vd_count = sec->sh_info; // Number of Verdef entries unsigned vd_count = sec->sh_info; // Number of Verdef entries
const char *sec_start = (const char*)base() + sec->sh_offset; const char *sec_start = (const char*)base() + sec->sh_offset;
skipping to change at line 785 skipping to change at line 900
ELFObjectFile<target_endianness, is64Bits> ELFObjectFile<target_endianness, is64Bits>
::getSection(const Elf_Sym *symb) const { ::getSection(const Elf_Sym *symb) const {
if (symb->st_shndx == ELF::SHN_XINDEX) if (symb->st_shndx == ELF::SHN_XINDEX)
return getSection(ExtendedSymbolTable.lookup(symb)); return getSection(ExtendedSymbolTable.lookup(symb));
if (symb->st_shndx >= ELF::SHN_LORESERVE) if (symb->st_shndx >= ELF::SHN_LORESERVE)
return 0; return 0;
return getSection(symb->st_shndx); return getSection(symb->st_shndx);
} }
template<support::endianness target_endianness, bool is64Bits> template<support::endianness target_endianness, bool is64Bits>
const typename ELFObjectFile<target_endianness, is64Bits>::Elf_Shdr *
ELFObjectFile<target_endianness, is64Bits>
::getElfSection(section_iterator &It) const {
llvm::object::DataRefImpl ShdrRef = It->getRawDataRefImpl();
return reinterpret_cast<const Elf_Shdr *>(ShdrRef.p);
}
template<support::endianness target_endianness, bool is64Bits>
const typename ELFObjectFile<target_endianness, is64Bits>::Elf_Sym *
ELFObjectFile<target_endianness, is64Bits>
::getElfSymbol(symbol_iterator &It) const {
return getSymbol(It->getRawDataRefImpl());
}
template<support::endianness target_endianness, bool is64Bits>
const typename ELFObjectFile<target_endianness, is64Bits>::Elf_Sym *
ELFObjectFile<target_endianness, is64Bits>
::getElfSymbol(uint32_t index) const {
DataRefImpl SymbolData;
SymbolData.d.a = index;
SymbolData.d.b = 1;
return getSymbol(SymbolData);
}
template<support::endianness target_endianness, bool is64Bits>
error_code ELFObjectFile<target_endianness, is64Bits> error_code ELFObjectFile<target_endianness, is64Bits>
::getSymbolFileOffset(DataRefImpl Symb, ::getSymbolFileOffset(DataRefImpl Symb,
uint64_t &Result) const { uint64_t &Result) const {
validateSymbol(Symb); validateSymbol(Symb);
const Elf_Sym *symb = getSymbol(Symb); const Elf_Sym *symb = getSymbol(Symb);
const Elf_Shdr *Section; const Elf_Shdr *Section;
switch (getSymbolTableIndex(symb)) { switch (getSymbolTableIndex(symb)) {
case ELF::SHN_COMMON: case ELF::SHN_COMMON:
// Unintialized symbols have no offset in the object file // Unintialized symbols have no offset in the object file
case ELF::SHN_UNDEF: case ELF::SHN_UNDEF:
skipping to change at line 844 skipping to change at line 984
default: Section = getSection(symb); default: Section = getSection(symb);
} }
switch (symb->getType()) { switch (symb->getType()) {
case ELF::STT_SECTION: case ELF::STT_SECTION:
Result = Section ? Section->sh_addr : UnknownAddressOrSize; Result = Section ? Section->sh_addr : UnknownAddressOrSize;
return object_error::success; return object_error::success;
case ELF::STT_FUNC: case ELF::STT_FUNC:
case ELF::STT_OBJECT: case ELF::STT_OBJECT:
case ELF::STT_NOTYPE: case ELF::STT_NOTYPE:
Result = symb->st_value + (Section ? Section->sh_addr : 0); bool IsRelocatable;
switch(Header->e_type) {
case ELF::ET_EXEC:
case ELF::ET_DYN:
IsRelocatable = false;
break;
default:
IsRelocatable = true;
}
Result = symb->st_value;
if (IsRelocatable && Section != 0)
Result += Section->sh_addr;
return object_error::success; return object_error::success;
default: default:
Result = UnknownAddressOrSize; Result = UnknownAddressOrSize;
return object_error::success; return object_error::success;
} }
} }
template<support::endianness target_endianness, bool is64Bits> template<support::endianness target_endianness, bool is64Bits>
error_code ELFObjectFile<target_endianness, is64Bits> error_code ELFObjectFile<target_endianness, is64Bits>
::getSymbolSize(DataRefImpl Symb, ::getSymbolSize(DataRefImpl Symb,
skipping to change at line 1015 skipping to change at line 1166
else { else {
DataRefImpl Sec; DataRefImpl Sec;
Sec.p = reinterpret_cast<intptr_t>(sec); Sec.p = reinterpret_cast<intptr_t>(sec);
Res = section_iterator(SectionRef(Sec, this)); Res = section_iterator(SectionRef(Sec, this));
} }
return object_error::success; return object_error::success;
} }
template<support::endianness target_endianness, bool is64Bits> template<support::endianness target_endianness, bool is64Bits>
error_code ELFObjectFile<target_endianness, is64Bits> error_code ELFObjectFile<target_endianness, is64Bits>
::getSymbolValue(DataRefImpl Symb,
uint64_t &Val) const {
validateSymbol(Symb);
const Elf_Sym *symb = getSymbol(Symb);
Val = symb->st_value;
return object_error::success;
}
template<support::endianness target_endianness, bool is64Bits>
error_code ELFObjectFile<target_endianness, is64Bits>
::getSectionNext(DataRefImpl Sec, SectionRef &Resul t) const { ::getSectionNext(DataRefImpl Sec, SectionRef &Resul t) const {
const uint8_t *sec = reinterpret_cast<const uint8_t *>(Sec.p); const uint8_t *sec = reinterpret_cast<const uint8_t *>(Sec.p);
sec += Header->e_shentsize; sec += Header->e_shentsize;
Sec.p = reinterpret_cast<intptr_t>(sec); Sec.p = reinterpret_cast<intptr_t>(sec);
Result = SectionRef(Sec, this); Result = SectionRef(Sec, this);
return object_error::success; return object_error::success;
} }
template<support::endianness target_endianness, bool is64Bits> template<support::endianness target_endianness, bool is64Bits>
error_code ELFObjectFile<target_endianness, is64Bits> error_code ELFObjectFile<target_endianness, is64Bits>
skipping to change at line 1062 skipping to change at line 1223
::getSectionContents(DataRefImpl Sec, ::getSectionContents(DataRefImpl Sec,
StringRef &Result) const { StringRef &Result) const {
const Elf_Shdr *sec = reinterpret_cast<const Elf_Shdr *>(Sec.p); const Elf_Shdr *sec = reinterpret_cast<const Elf_Shdr *>(Sec.p);
const char *start = (const char*)base() + sec->sh_offset; const char *start = (const char*)base() + sec->sh_offset;
Result = StringRef(start, sec->sh_size); Result = StringRef(start, sec->sh_size);
return object_error::success; return object_error::success;
} }
template<support::endianness target_endianness, bool is64Bits> template<support::endianness target_endianness, bool is64Bits>
error_code ELFObjectFile<target_endianness, is64Bits> error_code ELFObjectFile<target_endianness, is64Bits>
::getSectionContents(const Elf_Shdr *Sec,
StringRef &Result) const {
const char *start = (const char*)base() + Sec->sh_offset;
Result = StringRef(start, Sec->sh_size);
return object_error::success;
}
template<support::endianness target_endianness, bool is64Bits>
error_code ELFObjectFile<target_endianness, is64Bits>
::getSectionAlignment(DataRefImpl Sec, ::getSectionAlignment(DataRefImpl Sec,
uint64_t &Result) const { uint64_t &Result) const {
const Elf_Shdr *sec = reinterpret_cast<const Elf_Shdr *>(Sec.p); const Elf_Shdr *sec = reinterpret_cast<const Elf_Shdr *>(Sec.p);
Result = sec->sh_addralign; Result = sec->sh_addralign;
return object_error::success; return object_error::success;
} }
template<support::endianness target_endianness, bool is64Bits> template<support::endianness target_endianness, bool is64Bits>
error_code ELFObjectFile<target_endianness, is64Bits> error_code ELFObjectFile<target_endianness, is64Bits>
::isSectionText(DataRefImpl Sec, ::isSectionText(DataRefImpl Sec,
skipping to change at line 1132 skipping to change at line 1302
bool &Result) const { bool &Result) const {
const Elf_Shdr *sec = reinterpret_cast<const Elf_Shdr *>(Sec.p); const Elf_Shdr *sec = reinterpret_cast<const Elf_Shdr *>(Sec.p);
if (sec->sh_type == ELF::SHT_NOBITS) if (sec->sh_type == ELF::SHT_NOBITS)
Result = true; Result = true;
else else
Result = false; Result = false;
return object_error::success; return object_error::success;
} }
template<support::endianness target_endianness, bool is64Bits> template<support::endianness target_endianness, bool is64Bits>
error_code ELFObjectFile<target_endianness, is64Bits>::isSectionZeroInit(Da error_code ELFObjectFile<target_endianness, is64Bits>
taRefImpl Sec, ::isSectionZeroInit(DataRefImpl Sec,
bool &Result) const { bool &Result) const {
const Elf_Shdr *sec = reinterpret_cast<const Elf_Shdr *>(Sec.p); const Elf_Shdr *sec = reinterpret_cast<const Elf_Shdr *>(Sec.p);
// For ELF, all zero-init sections are virtual (that is, they occupy no s pace // For ELF, all zero-init sections are virtual (that is, they occupy no s pace
// in the object image) and vice versa. // in the object image) and vice versa.
if (sec->sh_flags & ELF::SHT_NOBITS) if (sec->sh_flags & ELF::SHT_NOBITS)
Result = true; Result = true;
else else
Result = false; Result = false;
return object_error::success; return object_error::success;
} }
template<support::endianness target_endianness, bool is64Bits> template<support::endianness target_endianness, bool is64Bits>
error_code ELFObjectFile<target_endianness, is64Bits> error_code ELFObjectFile<target_endianness, is64Bits>
::isSectionReadOnlyData(DataRefImpl Sec,
bool &Result) const {
const Elf_Shdr *sec = reinterpret_cast<const Elf_Shdr *>(Sec.p);
if (sec->sh_flags & ELF::SHF_WRITE || sec->sh_flags & ELF::SHF_EXECINSTR)
Result = false;
else
Result = true;
return object_error::success;
}
template<support::endianness target_endianness, bool is64Bits>
error_code ELFObjectFile<target_endianness, is64Bits>
::sectionContainsSymbol(DataRefImpl Sec, ::sectionContainsSymbol(DataRefImpl Sec,
DataRefImpl Symb, DataRefImpl Symb,
bool &Result) const { bool &Result) const {
// FIXME: Unimplemented. // FIXME: Unimplemented.
Result = false; Result = false;
return object_error::success; return object_error::success;
} }
template<support::endianness target_endianness, bool is64Bits> template<support::endianness target_endianness, bool is64Bits>
relocation_iterator ELFObjectFile<target_endianness, is64Bits> relocation_iterator ELFObjectFile<target_endianness, is64Bits>
skipping to change at line 1416 skipping to change at line 1599
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_TLS_DTPOFF32); LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_TLS_DTPOFF32);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_TLS_TPOFF32); LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_TLS_TPOFF32);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_TLS_GOTDESC); LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_TLS_GOTDESC);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_TLS_DESC_CALL); LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_TLS_DESC_CALL);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_TLS_DESC); LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_TLS_DESC);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_IRELATIVE); LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_IRELATIVE);
default: default:
res = "Unknown"; res = "Unknown";
} }
break; break;
case ELF::EM_ARM:
switch (type) {
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_NONE);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_PC24);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_ABS32);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_REL32);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_LDR_PC_G0);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_ABS16);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_ABS12);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_THM_ABS5);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_ABS8);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_SBREL32);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_THM_CALL);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_THM_PC8);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_BREL_ADJ);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_TLS_DESC);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_THM_SWI8);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_XPC25);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_THM_XPC22);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_TLS_DTPMOD32);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_TLS_DTPOFF32);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_TLS_TPOFF32);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_COPY);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_GLOB_DAT);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_JUMP_SLOT);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_RELATIVE);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_GOTOFF32);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_BASE_PREL);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_GOT_BREL);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_PLT32);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_CALL);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_JUMP24);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_THM_JUMP24);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_BASE_ABS);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_ALU_PCREL_7_0);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_ALU_PCREL_15_8);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_ALU_PCREL_23_15);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_LDR_SBREL_11_0_NC);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_ALU_SBREL_19_12_NC);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_ALU_SBREL_27_20_CK);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_TARGET1);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_SBREL31);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_V4BX);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_TARGET2);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_PREL31);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_MOVW_ABS_NC);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_MOVT_ABS);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_MOVW_PREL_NC);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_MOVT_PREL);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_THM_MOVW_ABS_NC);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_THM_MOVT_ABS);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_THM_MOVW_PREL_NC);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_THM_MOVT_PREL);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_THM_JUMP19);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_THM_JUMP6);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_THM_ALU_PREL_11_0);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_THM_PC12);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_ABS32_NOI);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_REL32_NOI);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_ALU_PC_G0_NC);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_ALU_PC_G0);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_ALU_PC_G1_NC);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_ALU_PC_G1);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_ALU_PC_G2);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_LDR_PC_G1);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_LDR_PC_G2);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_LDRS_PC_G0);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_LDRS_PC_G1);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_LDRS_PC_G2);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_LDC_PC_G0);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_LDC_PC_G1);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_LDC_PC_G2);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_ALU_SB_G0_NC);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_ALU_SB_G0);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_ALU_SB_G1_NC);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_ALU_SB_G1);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_ALU_SB_G2);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_LDR_SB_G0);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_LDR_SB_G1);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_LDR_SB_G2);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_LDRS_SB_G0);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_LDRS_SB_G1);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_LDRS_SB_G2);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_LDC_SB_G0);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_LDC_SB_G1);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_LDC_SB_G2);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_MOVW_BREL_NC);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_MOVT_BREL);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_MOVW_BREL);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_THM_MOVW_BREL_NC);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_THM_MOVT_BREL);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_THM_MOVW_BREL);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_TLS_GOTDESC);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_TLS_CALL);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_TLS_DESCSEQ);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_THM_TLS_CALL);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_PLT32_ABS);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_GOT_ABS);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_GOT_PREL);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_GOT_BREL12);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_GOTOFF12);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_GOTRELAX);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_GNU_VTENTRY);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_GNU_VTINHERIT);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_THM_JUMP11);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_THM_JUMP8);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_TLS_GD32);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_TLS_LDM32);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_TLS_LDO32);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_TLS_IE32);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_TLS_LE32);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_TLS_LDO12);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_TLS_LE12);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_TLS_IE12GP);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_PRIVATE_0);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_PRIVATE_1);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_PRIVATE_2);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_PRIVATE_3);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_PRIVATE_4);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_PRIVATE_5);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_PRIVATE_6);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_PRIVATE_7);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_PRIVATE_8);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_PRIVATE_9);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_PRIVATE_10);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_PRIVATE_11);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_PRIVATE_12);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_PRIVATE_13);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_PRIVATE_14);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_PRIVATE_15);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_ME_TOO);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_THM_TLS_DESCSEQ16);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_THM_TLS_DESCSEQ32);
default:
res = "Unknown";
}
break;
case ELF::EM_HEXAGON:
switch (type) {
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_NONE);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_B22_PCREL);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_B15_PCREL);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_B7_PCREL);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_LO16);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_HI16);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_32);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_16);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_8);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_GPREL16_0);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_GPREL16_1);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_GPREL16_2);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_GPREL16_3);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_HL16);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_B13_PCREL);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_B9_PCREL);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_B32_PCREL_X);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_32_6_X);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_B22_PCREL_X);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_B15_PCREL_X);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_B13_PCREL_X);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_B9_PCREL_X);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_B7_PCREL_X);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_16_X);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_12_X);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_11_X);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_10_X);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_9_X);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_8_X);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_7_X);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_6_X);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_32_PCREL);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_COPY);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_GLOB_DAT);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_JMP_SLOT);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_RELATIVE);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_PLT_B22_PCREL);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_GOTREL_LO16);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_GOTREL_HI16);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_GOTREL_32);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_GOT_LO16);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_GOT_HI16);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_GOT_32);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_GOT_16);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_DTPMOD_32);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_DTPREL_LO16);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_DTPREL_HI16);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_DTPREL_32);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_DTPREL_16);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_GD_PLT_B22_PCREL);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_GD_GOT_LO16);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_GD_GOT_HI16);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_GD_GOT_32);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_GD_GOT_16);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_IE_LO16);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_IE_HI16);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_IE_32);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_IE_GOT_LO16);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_IE_GOT_HI16);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_IE_GOT_32);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_IE_GOT_16);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_TPREL_LO16);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_TPREL_HI16);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_TPREL_32);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_TPREL_16);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_6_PCREL_X);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_GOTREL_32_6_X);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_GOTREL_16_X);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_GOTREL_11_X);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_GOT_32_6_X);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_GOT_16_X);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_GOT_11_X);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_DTPREL_32_6_X);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_DTPREL_16_X);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_DTPREL_11_X);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_GD_GOT_32_6_X);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_GD_GOT_16_X);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_GD_GOT_11_X);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_IE_32_6_X);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_IE_16_X);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_IE_GOT_32_6_X);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_IE_GOT_16_X);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_IE_GOT_11_X);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_TPREL_32_6_X);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_TPREL_16_X);
LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_TPREL_11_X);
default:
res = "Unknown";
}
break;
default: default:
res = "Unknown"; res = "Unknown";
} }
Result.append(res.begin(), res.end()); Result.append(res.begin(), res.end());
return object_error::success; return object_error::success;
} }
#undef LLVM_ELF_SWITCH_RELOC_TYPE_NAME #undef LLVM_ELF_SWITCH_RELOC_TYPE_NAME
template<support::endianness target_endianness, bool is64Bits> template<support::endianness target_endianness, bool is64Bits>
skipping to change at line 1454 skipping to change at line 1866
template<support::endianness target_endianness, bool is64Bits> template<support::endianness target_endianness, bool is64Bits>
error_code ELFObjectFile<target_endianness, is64Bits> error_code ELFObjectFile<target_endianness, is64Bits>
::getRelocationValueString(DataRefImpl Rel, ::getRelocationValueString(DataRefImpl Rel,
SmallVectorImpl<char> &Result) co nst { SmallVectorImpl<char> &Result) co nst {
const Elf_Shdr *sec = getSection(Rel.w.b); const Elf_Shdr *sec = getSection(Rel.w.b);
uint8_t type; uint8_t type;
StringRef res; StringRef res;
int64_t addend = 0; int64_t addend = 0;
uint16_t symbol_index = 0; uint16_t symbol_index = 0;
switch (sec->sh_type) { switch (sec->sh_type) {
default : default:
return object_error::parse_failed; return object_error::parse_failed;
case ELF::SHT_REL : { case ELF::SHT_REL: {
type = getRel(Rel)->getType(); type = getRel(Rel)->getType();
symbol_index = getRel(Rel)->getSymbol(); symbol_index = getRel(Rel)->getSymbol();
// TODO: Read implicit addend from section data. // TODO: Read implicit addend from section data.
break; break;
} }
case ELF::SHT_RELA : { case ELF::SHT_RELA: {
type = getRela(Rel)->getType(); type = getRela(Rel)->getType();
symbol_index = getRela(Rel)->getSymbol(); symbol_index = getRela(Rel)->getSymbol();
addend = getRela(Rel)->r_addend; addend = getRela(Rel)->r_addend;
break; break;
} }
} }
const Elf_Sym *symb = getEntry<Elf_Sym>(sec->sh_link, symbol_index); const Elf_Sym *symb = getEntry<Elf_Sym>(sec->sh_link, symbol_index);
StringRef symname; StringRef symname;
if (error_code ec = getSymbolName(getSection(sec->sh_link), symb, symname )) if (error_code ec = getSymbolName(getSection(sec->sh_link), symb, symname ))
return ec; return ec;
switch (Header->e_machine) { switch (Header->e_machine) {
case ELF::EM_X86_64: case ELF::EM_X86_64:
switch (type) { switch (type) {
case ELF::R_X86_64_32S: case ELF::R_X86_64_PC8:
res = symname; case ELF::R_X86_64_PC16:
break;
case ELF::R_X86_64_PC32: { case ELF::R_X86_64_PC32: {
std::string fmtbuf; std::string fmtbuf;
raw_string_ostream fmt(fmtbuf); raw_string_ostream fmt(fmtbuf);
fmt << symname << (addend < 0 ? "" : "+") << addend << "-P"; fmt << symname << (addend < 0 ? "" : "+") << addend << "-P";
fmt.flush(); fmt.flush();
Result.append(fmtbuf.begin(), fmtbuf.end()); Result.append(fmtbuf.begin(), fmtbuf.end());
} }
break; break;
case ELF::R_X86_64_8:
case ELF::R_X86_64_16:
case ELF::R_X86_64_32:
case ELF::R_X86_64_32S:
case ELF::R_X86_64_64: {
std::string fmtbuf;
raw_string_ostream fmt(fmtbuf);
fmt << symname << (addend < 0 ? "" : "+") << addend;
fmt.flush();
Result.append(fmtbuf.begin(), fmtbuf.end());
}
break;
default: default:
res = "Unknown"; res = "Unknown";
} }
break; break;
case ELF::EM_ARM:
case ELF::EM_HEXAGON:
res = symname;
break;
default: default:
res = "Unknown"; res = "Unknown";
} }
if (Result.empty()) if (Result.empty())
Result.append(res.begin(), res.end()); Result.append(res.begin(), res.end());
return object_error::success; return object_error::success;
} }
// Verify that the last byte in the string table in a null. // Verify that the last byte in the string table in a null.
template<support::endianness target_endianness, bool is64Bits> template<support::endianness target_endianness, bool is64Bits>
skipping to change at line 1890 skipping to change at line 2317
::getFileFormatName() const { ::getFileFormatName() const {
switch(Header->e_ident[ELF::EI_CLASS]) { switch(Header->e_ident[ELF::EI_CLASS]) {
case ELF::ELFCLASS32: case ELF::ELFCLASS32:
switch(Header->e_machine) { switch(Header->e_machine) {
case ELF::EM_386: case ELF::EM_386:
return "ELF32-i386"; return "ELF32-i386";
case ELF::EM_X86_64: case ELF::EM_X86_64:
return "ELF32-x86-64"; return "ELF32-x86-64";
case ELF::EM_ARM: case ELF::EM_ARM:
return "ELF32-arm"; return "ELF32-arm";
case ELF::EM_HEXAGON:
return "ELF32-hexagon";
default: default:
return "ELF32-unknown"; return "ELF32-unknown";
} }
case ELF::ELFCLASS64: case ELF::ELFCLASS64:
switch(Header->e_machine) { switch(Header->e_machine) {
case ELF::EM_386: case ELF::EM_386:
return "ELF64-i386"; return "ELF64-i386";
case ELF::EM_X86_64: case ELF::EM_X86_64:
return "ELF64-x86-64"; return "ELF64-x86-64";
case ELF::EM_PPC64:
return "ELF64-ppc64";
default: default:
return "ELF64-unknown"; return "ELF64-unknown";
} }
default: default:
// FIXME: Proper error handling. // FIXME: Proper error handling.
report_fatal_error("Invalid ELFCLASS!"); report_fatal_error("Invalid ELFCLASS!");
} }
} }
template<support::endianness target_endianness, bool is64Bits> template<support::endianness target_endianness, bool is64Bits>
unsigned ELFObjectFile<target_endianness, is64Bits>::getArch() const { unsigned ELFObjectFile<target_endianness, is64Bits>::getArch() const {
switch(Header->e_machine) { switch(Header->e_machine) {
case ELF::EM_386: case ELF::EM_386:
return Triple::x86; return Triple::x86;
case ELF::EM_X86_64: case ELF::EM_X86_64:
return Triple::x86_64; return Triple::x86_64;
case ELF::EM_ARM: case ELF::EM_ARM:
return Triple::arm; return Triple::arm;
case ELF::EM_HEXAGON:
return Triple::hexagon;
case ELF::EM_MIPS:
return (target_endianness == support::little) ?
Triple::mipsel : Triple::mips;
case ELF::EM_PPC64:
return Triple::ppc64;
default: default:
return Triple::UnknownArch; return Triple::UnknownArch;
} }
} }
template<support::endianness target_endianness, bool is64Bits> template<support::endianness target_endianness, bool is64Bits>
uint64_t ELFObjectFile<target_endianness, is64Bits>::getNumSections() const { uint64_t ELFObjectFile<target_endianness, is64Bits>::getNumSections() const {
assert(Header && "Header not initialized!"); assert(Header && "Header not initialized!");
if (Header->e_shnum == ELF::SHN_UNDEF) { if (Header->e_shnum == ELF::SHN_UNDEF) {
assert(SectionHeaderTable && "SectionHeaderTable not initialized!"); assert(SectionHeaderTable && "SectionHeaderTable not initialized!");
skipping to change at line 2055 skipping to change at line 2493
Result = getString(dot_dynstr_sec, symb->st_name); Result = getString(dot_dynstr_sec, symb->st_name);
} else { } else {
// Use the default symbol table name section. // Use the default symbol table name section.
Result = getString(dot_strtab_sec, symb->st_name); Result = getString(dot_strtab_sec, symb->st_name);
} }
return object_error::success; return object_error::success;
} }
template<support::endianness target_endianness, bool is64Bits> template<support::endianness target_endianness, bool is64Bits>
error_code ELFObjectFile<target_endianness, is64Bits> error_code ELFObjectFile<target_endianness, is64Bits>
::getSectionName(const Elf_Shdr *section,
StringRef &Result) const {
Result = StringRef(getString(dot_shstrtab_sec, section->sh_name));
return object_error::success;
}
template<support::endianness target_endianness, bool is64Bits>
error_code ELFObjectFile<target_endianness, is64Bits>
::getSymbolVersion(const Elf_Shdr *section, ::getSymbolVersion(const Elf_Shdr *section,
const Elf_Sym *symb, const Elf_Sym *symb,
StringRef &Version, StringRef &Version,
bool &IsDefault) const { bool &IsDefault) const {
// Handle non-dynamic symbols. // Handle non-dynamic symbols.
if (section != SymbolTableSections[0]) { if (section != SymbolTableSections[0]) {
// Non-dynamic symbols can have versions in their names // Non-dynamic symbols can have versions in their names
// A name of the form 'foo@V1' indicates version 'V1', non-default. // A name of the form 'foo@V1' indicates version 'V1', non-default.
// A name of the form 'foo@@V2' indicates version 'V2', default version . // A name of the form 'foo@@V2' indicates version 'V2', default version .
StringRef Name; StringRef Name;
 End of changes. 30 change blocks. 
36 lines changed or deleted 485 lines changed or added


 EdgeBundles.h   EdgeBundles.h 
skipping to change at line 49 skipping to change at line 49
EdgeBundles() : MachineFunctionPass(ID) {} EdgeBundles() : MachineFunctionPass(ID) {}
/// getBundle - Return the ingoing (Out = false) or outgoing (Out = true) /// getBundle - Return the ingoing (Out = false) or outgoing (Out = true)
/// bundle number for basic block #N /// bundle number for basic block #N
unsigned getBundle(unsigned N, bool Out) const { return EC[2 * N + Out]; } unsigned getBundle(unsigned N, bool Out) const { return EC[2 * N + Out]; }
/// getNumBundles - Return the total number of bundles in the CFG. /// getNumBundles - Return the total number of bundles in the CFG.
unsigned getNumBundles() const { return EC.getNumClasses(); } unsigned getNumBundles() const { return EC.getNumClasses(); }
/// getBlocks - Return an array of blocks that are connected to Bundle. /// getBlocks - Return an array of blocks that are connected to Bundle.
ArrayRef<unsigned> getBlocks(unsigned Bundle) { return Blocks[Bundle]; } ArrayRef<unsigned> getBlocks(unsigned Bundle) const { return Blocks[Bundl e]; }
/// getMachineFunction - Return the last machine function computed. /// getMachineFunction - Return the last machine function computed.
const MachineFunction *getMachineFunction() const { return MF; } const MachineFunction *getMachineFunction() const { return MF; }
/// view - Visualize the annotated bipartite CFG with Graphviz. /// view - Visualize the annotated bipartite CFG with Graphviz.
void view() const; void view() const;
private: private:
virtual bool runOnMachineFunction(MachineFunction&); virtual bool runOnMachineFunction(MachineFunction&);
virtual void getAnalysisUsage(AnalysisUsage&) const; virtual void getAnalysisUsage(AnalysisUsage&) const;
 End of changes. 1 change blocks. 
1 lines changed or deleted 1 lines changed or added


 Endian.h   Endian.h 
skipping to change at line 52 skipping to change at line 52
struct alignment_access_helper<value_type, unaligned> struct alignment_access_helper<value_type, unaligned>
{ {
value_type val; value_type val;
}; };
#pragma pack(pop) #pragma pack(pop)
} // end namespace detail } // end namespace detail
namespace endian { namespace endian {
template<typename value_type, alignment align> template<typename value_type, alignment align>
static value_type read_le(const void *memory) { inline value_type read_le(const void *memory) {
value_type t = value_type t =
reinterpret_cast<const detail::alignment_access_helper reinterpret_cast<const detail::alignment_access_helper
<value_type, align> *>(memory)->val; <value_type, align> *>(memory)->val;
if (sys::isBigEndianHost()) if (sys::isBigEndianHost())
return sys::SwapByteOrder(t); return sys::SwapByteOrder(t);
return t; return t;
} }
template<typename value_type, alignment align> template<typename value_type, alignment align>
static void write_le(void *memory, value_type value) { inline void write_le(void *memory, value_type value) {
if (sys::isBigEndianHost()) if (sys::isBigEndianHost())
value = sys::SwapByteOrder(value); value = sys::SwapByteOrder(value);
reinterpret_cast<detail::alignment_access_helper<value_type, align> *> reinterpret_cast<detail::alignment_access_helper<value_type, align> *>
(memory)->val = value; (memory)->val = value;
} }
template<typename value_type, alignment align> template<typename value_type, alignment align>
static value_type read_be(const void *memory) { inline value_type read_be(const void *memory) {
value_type t = value_type t =
reinterpret_cast<const detail::alignment_access_helper reinterpret_cast<const detail::alignment_access_helper
<value_type, align> *>(memory)->val; <value_type, align> *>(memory)->val;
if (sys::isLittleEndianHost()) if (sys::isLittleEndianHost())
return sys::SwapByteOrder(t); return sys::SwapByteOrder(t);
return t; return t;
} }
template<typename value_type, alignment align> template<typename value_type, alignment align>
static void write_be(void *memory, value_type value) { inline void write_be(void *memory, value_type value) {
if (sys::isLittleEndianHost()) if (sys::isLittleEndianHost())
value = sys::SwapByteOrder(value); value = sys::SwapByteOrder(value);
reinterpret_cast<detail::alignment_access_helper<value_type, align> *> reinterpret_cast<detail::alignment_access_helper<value_type, align> *>
(memory)->val = value; (memory)->val = value;
} }
} }
namespace detail { namespace detail {
template<typename value_type, template<typename value_type,
 End of changes. 4 change blocks. 
4 lines changed or deleted 4 lines changed or added


 EquivalenceClasses.h   EquivalenceClasses.h 
skipping to change at line 36 skipping to change at line 36
/// own, union two classes, and find the class for a given element. In /// own, union two classes, and find the class for a given element. In
/// addition to these modification methods, it is possible to iterate over all /// addition to these modification methods, it is possible to iterate over all
/// of the equivalence classes and all of the elements in a class. /// of the equivalence classes and all of the elements in a class.
/// ///
/// This implementation is an efficient implementation that only stores one copy /// This implementation is an efficient implementation that only stores one copy
/// of the element being indexed per entry in the set, and allows any arbit rary /// of the element being indexed per entry in the set, and allows any arbit rary
/// type to be indexed (as long as it can be ordered with operator<). /// type to be indexed (as long as it can be ordered with operator<).
/// ///
/// Here is a simple example using integers: /// Here is a simple example using integers:
/// ///
/// \code
/// EquivalenceClasses<int> EC; /// EquivalenceClasses<int> EC;
/// EC.unionSets(1, 2); // insert 1, 2 into the same set /// EC.unionSets(1, 2); // insert 1, 2 into the same set
/// EC.insert(4); EC.insert(5); // insert 4, 5 into own sets /// EC.insert(4); EC.insert(5); // insert 4, 5 into own sets
/// EC.unionSets(5, 1); // merge the set for 1 with 5's set . /// EC.unionSets(5, 1); // merge the set for 1 with 5's set .
/// ///
/// for (EquivalenceClasses<int>::iterator I = EC.begin(), E = EC.end(); /// for (EquivalenceClasses<int>::iterator I = EC.begin(), E = EC.end();
/// I != E; ++I) { // Iterate over all of the equivalence s ets. /// I != E; ++I) { // Iterate over all of the equivalence s ets.
/// if (!I->isLeader()) continue; // Ignore non-leader sets. /// if (!I->isLeader()) continue; // Ignore non-leader sets.
/// for (EquivalenceClasses<int>::member_iterator MI = EC.member_begin(I ); /// for (EquivalenceClasses<int>::member_iterator MI = EC.member_begin(I );
/// MI != EC.member_end(); ++MI) // Loop over members in this set . /// MI != EC.member_end(); ++MI) // Loop over members in this set .
/// cerr << *MI << " "; // Print member. /// cerr << *MI << " "; // Print member.
/// cerr << "\n"; // Finish set. /// cerr << "\n"; // Finish set.
/// } /// }
/// \endcode
/// ///
/// This example prints: /// This example prints:
/// 4 /// 4
/// 5 1 2 /// 5 1 2
/// ///
template <class ElemTy> template <class ElemTy>
class EquivalenceClasses { class EquivalenceClasses {
/// ECValue - The EquivalenceClasses data structure is just a set of thes e. /// ECValue - The EquivalenceClasses data structure is just a set of thes e.
/// Each of these represents a relation for a value. First it stores the /// Each of these represents a relation for a value. First it stores the
/// value itself, which provides the ordering that the set queries. Next , it /// value itself, which provides the ordering that the set queries. Next , it
 End of changes. 2 change blocks. 
0 lines changed or deleted 2 lines changed or added


 FastISel.h   FastISel.h 
skipping to change at line 35 skipping to change at line 35
class ConstantFP; class ConstantFP;
class FunctionLoweringInfo; class FunctionLoweringInfo;
class Instruction; class Instruction;
class LoadInst; class LoadInst;
class MachineBasicBlock; class MachineBasicBlock;
class MachineConstantPool; class MachineConstantPool;
class MachineFunction; class MachineFunction;
class MachineInstr; class MachineInstr;
class MachineFrameInfo; class MachineFrameInfo;
class MachineRegisterInfo; class MachineRegisterInfo;
class TargetData; class DataLayout;
class TargetInstrInfo; class TargetInstrInfo;
class TargetLibraryInfo;
class TargetLowering; class TargetLowering;
class TargetMachine; class TargetMachine;
class TargetRegisterClass; class TargetRegisterClass;
class TargetRegisterInfo; class TargetRegisterInfo;
class User; class User;
class Value; class Value;
/// FastISel - This is a fast-path instruction selection class that /// FastISel - This is a fast-path instruction selection class that
/// generates poor code and doesn't support illegal types or non-trivial /// generates poor code and doesn't support illegal types or non-trivial
/// lowering, but runs quickly. /// lowering, but runs quickly.
class FastISel { class FastISel {
protected: protected:
DenseMap<const Value *, unsigned> LocalValueMap; DenseMap<const Value *, unsigned> LocalValueMap;
FunctionLoweringInfo &FuncInfo; FunctionLoweringInfo &FuncInfo;
MachineRegisterInfo &MRI; MachineRegisterInfo &MRI;
MachineFrameInfo &MFI; MachineFrameInfo &MFI;
MachineConstantPool &MCP; MachineConstantPool &MCP;
DebugLoc DL; DebugLoc DL;
const TargetMachine &TM; const TargetMachine &TM;
const TargetData &TD; const DataLayout &TD;
const TargetInstrInfo &TII; const TargetInstrInfo &TII;
const TargetLowering &TLI; const TargetLowering &TLI;
const TargetRegisterInfo &TRI; const TargetRegisterInfo &TRI;
const TargetLibraryInfo *LibInfo;
/// The position of the last instruction for materializing constants /// The position of the last instruction for materializing constants
/// for use in the current block. It resets to EmitStartPt when it /// for use in the current block. It resets to EmitStartPt when it
/// makes sense (for example, it's usually profitable to avoid function /// makes sense (for example, it's usually profitable to avoid function
/// calls between the definition and the use) /// calls between the definition and the use)
MachineInstr *LastLocalValue; MachineInstr *LastLocalValue;
/// The top most instruction in the current block that is allowed for /// The top most instruction in the current block that is allowed for
/// emitting local variables. LastLocalValue resets to EmitStartPt when /// emitting local variables. LastLocalValue resets to EmitStartPt when
/// it makes sense (for example, on function calls) /// it makes sense (for example, on function calls)
skipping to change at line 147 skipping to change at line 149
/// enterLocalValueArea - Prepare InsertPt to begin inserting instruction s /// enterLocalValueArea - Prepare InsertPt to begin inserting instruction s
/// into the local value area and return the old insert position. /// into the local value area and return the old insert position.
SavePoint enterLocalValueArea(); SavePoint enterLocalValueArea();
/// leaveLocalValueArea - Reset InsertPt to the given old insert position . /// leaveLocalValueArea - Reset InsertPt to the given old insert position .
void leaveLocalValueArea(SavePoint Old); void leaveLocalValueArea(SavePoint Old);
virtual ~FastISel(); virtual ~FastISel();
protected: protected:
explicit FastISel(FunctionLoweringInfo &funcInfo); explicit FastISel(FunctionLoweringInfo &funcInfo,
const TargetLibraryInfo *libInfo);
/// TargetSelectInstruction - This method is called by target-independent /// TargetSelectInstruction - This method is called by target-independent
/// code when the normal FastISel process fails to select an instruction. /// code when the normal FastISel process fails to select an instruction.
/// This gives targets a chance to emit code for anything that doesn't /// This gives targets a chance to emit code for anything that doesn't
/// fit into FastISel's framework. It returns true if it was successful. /// fit into FastISel's framework. It returns true if it was successful.
/// ///
virtual bool virtual bool
TargetSelectInstruction(const Instruction *I) = 0; TargetSelectInstruction(const Instruction *I) = 0;
/// FastEmit_r - This method is called by target-independent code /// FastEmit_r - This method is called by target-independent code
skipping to change at line 302 skipping to change at line 305
/// FastEmitInst_rri - Emit a MachineInstr with two register operands, /// FastEmitInst_rri - Emit a MachineInstr with two register operands,
/// an immediate, and a result register in the given register class. /// an immediate, and a result register in the given register class.
/// ///
unsigned FastEmitInst_rri(unsigned MachineInstOpcode, unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
const TargetRegisterClass *RC, const TargetRegisterClass *RC,
unsigned Op0, bool Op0IsKill, unsigned Op0, bool Op0IsKill,
unsigned Op1, bool Op1IsKill, unsigned Op1, bool Op1IsKill,
uint64_t Imm); uint64_t Imm);
/// FastEmitInst_rrii - Emit a MachineInstr with two register operands,
/// two immediates operands, and a result register in the given register
/// class.
unsigned FastEmitInst_rrii(unsigned MachineInstOpcode,
const TargetRegisterClass *RC,
unsigned Op0, bool Op0IsKill,
unsigned Op1, bool Op1IsKill,
uint64_t Imm1, uint64_t Imm2);
/// FastEmitInst_i - Emit a MachineInstr with a single immediate /// FastEmitInst_i - Emit a MachineInstr with a single immediate
/// operand, and a result register in the given register class. /// operand, and a result register in the given register class.
unsigned FastEmitInst_i(unsigned MachineInstrOpcode, unsigned FastEmitInst_i(unsigned MachineInstrOpcode,
const TargetRegisterClass *RC, const TargetRegisterClass *RC,
uint64_t Imm); uint64_t Imm);
/// FastEmitInst_ii - Emit a MachineInstr with a two immediate operands. /// FastEmitInst_ii - Emit a MachineInstr with a two immediate operands.
unsigned FastEmitInst_ii(unsigned MachineInstrOpcode, unsigned FastEmitInst_ii(unsigned MachineInstrOpcode,
const TargetRegisterClass *RC, const TargetRegisterClass *RC,
uint64_t Imm1, uint64_t Imm2); uint64_t Imm1, uint64_t Imm2);
 End of changes. 6 change blocks. 
3 lines changed or deleted 15 lines changed or added


 FileSystem.h   FileSystem.h 
skipping to change at line 31 skipping to change at line 31
// errors occur, the correct error_code will be used ]. All functions may // errors occur, the correct error_code will be used ]. All functions may
// return errc::not_enough_memory if there is not enough memory to complete the // return errc::not_enough_memory if there is not enough memory to complete the
// operation. // operation.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_SUPPORT_FILE_SYSTEM_H #ifndef LLVM_SUPPORT_FILE_SYSTEM_H
#define LLVM_SUPPORT_FILE_SYSTEM_H #define LLVM_SUPPORT_FILE_SYSTEM_H
#include "llvm/ADT/IntrusiveRefCntPtr.h" #include "llvm/ADT/IntrusiveRefCntPtr.h"
#include "llvm/ADT/OwningPtr.h"
#include "llvm/ADT/SmallString.h" #include "llvm/ADT/SmallString.h"
#include "llvm/ADT/Twine.h" #include "llvm/ADT/Twine.h"
#include "llvm/Support/DataTypes.h" #include "llvm/Support/DataTypes.h"
#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/system_error.h" #include "llvm/Support/system_error.h"
#include <ctime> #include <ctime>
#include <iterator> #include <iterator>
#include <stack> #include <stack>
#include <string> #include <string>
#include <vector> #include <vector>
#if HAVE_SYS_STAT_H #ifdef HAVE_SYS_STAT_H
#include <sys/stat.h> #include <sys/stat.h>
#endif #endif
namespace llvm { namespace llvm {
namespace sys { namespace sys {
namespace fs { namespace fs {
/// file_type - An "enum class" enumeration for the file system's view of t he /// file_type - An "enum class" enumeration for the file system's view of t he
/// type. /// type.
struct file_type { struct file_type {
skipping to change at line 97 skipping to change at line 98
int v_; int v_;
}; };
/// space_info - Self explanatory. /// space_info - Self explanatory.
struct space_info { struct space_info {
uint64_t capacity; uint64_t capacity;
uint64_t free; uint64_t free;
uint64_t available; uint64_t available;
}; };
enum perms {
no_perms = 0,
owner_read = 0400,
owner_write = 0200,
owner_exe = 0100,
owner_all = owner_read | owner_write | owner_exe,
group_read = 040,
group_write = 020,
group_exe = 010,
group_all = group_read | group_write | group_exe,
others_read = 04,
others_write = 02,
others_exe = 01,
others_all = others_read | others_write | others_exe,
all_all = owner_all | group_all | others_all,
set_uid_on_exe = 04000,
set_gid_on_exe = 02000,
sticky_bit = 01000,
perms_mask = all_all | set_uid_on_exe | set_gid_on_exe | sticky_bit,
perms_not_known = 0xFFFF,
add_perms = 0x1000,
remove_perms = 0x2000,
symlink_perms = 0x4000
};
// Helper functions so that you can use & and | to manipulate perms bits:
inline perms operator|(perms l , perms r) {
return static_cast<perms>(
static_cast<unsigned short>(l) | static_cast<unsigned short>(r
));
}
inline perms operator&(perms l , perms r) {
return static_cast<perms>(
static_cast<unsigned short>(l) & static_cast<unsigned short>(r
));
}
inline perms &operator|=(perms &l, perms r) {
l = l | r;
return l;
}
inline perms &operator&=(perms &l, perms r) {
l = l & r;
return l;
}
inline perms operator~(perms x) {
return static_cast<perms>(~static_cast<unsigned short>(x));
}
/// file_status - Represents the result of a call to stat and friends. It h as /// file_status - Represents the result of a call to stat and friends. It h as
/// a platform specific member to store the result. /// a platform specific member to store the result.
class file_status class file_status
{ {
#if defined(LLVM_ON_UNIX) #if defined(LLVM_ON_UNIX)
dev_t st_dev; dev_t fs_st_dev;
ino_t st_ino; ino_t fs_st_ino;
#elif defined (LLVM_ON_WIN32) #elif defined (LLVM_ON_WIN32)
uint32_t LastWriteTimeHigh; uint32_t LastWriteTimeHigh;
uint32_t LastWriteTimeLow; uint32_t LastWriteTimeLow;
uint32_t VolumeSerialNumber; uint32_t VolumeSerialNumber;
uint32_t FileSizeHigh; uint32_t FileSizeHigh;
uint32_t FileSizeLow; uint32_t FileSizeLow;
uint32_t FileIndexHigh; uint32_t FileIndexHigh;
uint32_t FileIndexLow; uint32_t FileIndexLow;
#endif #endif
friend bool equivalent(file_status A, file_status B); friend bool equivalent(file_status A, file_status B);
friend error_code status(const Twine &path, file_status &result); friend error_code status(const Twine &path, file_status &result);
file_type Type; file_type Type;
perms Perms;
public: public:
explicit file_status(file_type v=file_type::status_error) explicit file_status(file_type v=file_type::status_error,
: Type(v) {} perms prms=perms_not_known)
: Type(v), Perms(prms) {}
// getters
file_type type() const { return Type; } file_type type() const { return Type; }
perms permissions() const { return Perms; }
// setters
void type(file_type v) { Type = v; } void type(file_type v) { Type = v; }
void permissions(perms p) { Perms = p; }
}; };
/// file_magic - An "enum class" enumeration of file types based on magic ( the first /// file_magic - An "enum class" enumeration of file types based on magic ( the first
/// N bytes of the file). /// N bytes of the file).
struct file_magic { struct file_magic {
enum _ { enum _ {
unknown = 0, ///< Unrecognized file unknown = 0, ///< Unrecognized file
bitcode, ///< Bitcode file bitcode, ///< Bitcode file
archive, ///< ar style archive file archive, ///< ar style archive file
elf_relocatable, ///< ELF Relocatable object file elf_relocatable, ///< ELF Relocatable object file
skipping to change at line 226 skipping to change at line 280
/// ///
/// @param to The path to symbolically link to. /// @param to The path to symbolically link to.
/// @param from The path to symbolically link from. This is created. /// @param from The path to symbolically link from. This is created.
/// @returns errc::success if exists(to) && exists(from) && is_symlink(from ), /// @returns errc::success if exists(to) && exists(from) && is_symlink(from ),
/// otherwise a platform specific error_code. /// otherwise a platform specific error_code.
error_code create_symlink(const Twine &to, const Twine &from); error_code create_symlink(const Twine &to, const Twine &from);
/// @brief Get the current path. /// @brief Get the current path.
/// ///
/// @param result Holds the current path on return. /// @param result Holds the current path on return.
/// @results errc::success if the current path has been stored in result, /// @returns errc::success if the current path has been stored in result,
/// otherwise a platform specific error_code. /// otherwise a platform specific error_code.
error_code current_path(SmallVectorImpl<char> &result); error_code current_path(SmallVectorImpl<char> &result);
/// @brief Remove path. Equivalent to POSIX remove(). /// @brief Remove path. Equivalent to POSIX remove().
/// ///
/// @param path Input path. /// @param path Input path.
/// @param existed Set to true if \a path existed, false if it did not. /// @param existed Set to true if \a path existed, false if it did not.
/// undefined otherwise. /// undefined otherwise.
/// @results errc::success if path has been removed and existed has been /// @returns errc::success if path has been removed and existed has been
/// successfully set, otherwise a platform specific error_code. /// successfully set, otherwise a platform specific error_code.
error_code remove(const Twine &path, bool &existed); error_code remove(const Twine &path, bool &existed);
/// @brief Recursively remove all files below \a path, then \a path. Files are /// @brief Recursively remove all files below \a path, then \a path. Files are
/// removed as if by POSIX remove(). /// removed as if by POSIX remove().
/// ///
/// @param path Input path. /// @param path Input path.
/// @param num_removed Number of files removed. /// @param num_removed Number of files removed.
/// @results errc::success if path has been removed and num_removed has bee n /// @returns errc::success if path has been removed and num_removed has bee n
/// successfully set, otherwise a platform specific error_code. /// successfully set, otherwise a platform specific error_code.
error_code remove_all(const Twine &path, uint32_t &num_removed); error_code remove_all(const Twine &path, uint32_t &num_removed);
/// @brief Rename \a from to \a to. Files are renamed as if by POSIX rename (). /// @brief Rename \a from to \a to. Files are renamed as if by POSIX rename ().
/// ///
/// @param from The path to rename from. /// @param from The path to rename from.
/// @param to The path to rename to. This is created. /// @param to The path to rename to. This is created.
error_code rename(const Twine &from, const Twine &to); error_code rename(const Twine &from, const Twine &to);
/// @brief Resize path to size. File is resized as if by POSIX truncate(). /// @brief Resize path to size. File is resized as if by POSIX truncate().
skipping to change at line 269 skipping to change at line 323
/// platform specific error_code. /// platform specific error_code.
error_code resize_file(const Twine &path, uint64_t size); error_code resize_file(const Twine &path, uint64_t size);
/// @} /// @}
/// @name Physical Observers /// @name Physical Observers
/// @{ /// @{
/// @brief Does file exist? /// @brief Does file exist?
/// ///
/// @param status A file_status previously returned from stat. /// @param status A file_status previously returned from stat.
/// @results True if the file represented by status exists, false if it doe s /// @returns True if the file represented by status exists, false if it doe s
/// not. /// not.
bool exists(file_status status); bool exists(file_status status);
/// @brief Does file exist? /// @brief Does file exist?
/// ///
/// @param path Input path. /// @param path Input path.
/// @param result Set to true if the file represented by status exists, fal se if /// @param result Set to true if the file represented by status exists, fal se if
/// it does not. Undefined otherwise. /// it does not. Undefined otherwise.
/// @results errc::success if result has been successfully set, otherwise a /// @returns errc::success if result has been successfully set, otherwise a
/// platform specific error_code. /// platform specific error_code.
error_code exists(const Twine &path, bool &result); error_code exists(const Twine &path, bool &result);
/// @brief Simpler version of exists for clients that don't need to /// @brief Simpler version of exists for clients that don't need to
/// differentiate between an error and false. /// differentiate between an error and false.
inline bool exists(const Twine &path) { inline bool exists(const Twine &path) {
bool result; bool result;
return !exists(path, result) && result; return !exists(path, result) && result;
} }
/// @brief Do file_status's represent the same thing? /// @brief Do file_status's represent the same thing?
/// ///
/// @param A Input file_status. /// @param A Input file_status.
/// @param B Input file_status. /// @param B Input file_status.
/// ///
/// assert(status_known(A) || status_known(B)); /// assert(status_known(A) || status_known(B));
/// ///
/// @results True if A and B both represent the same file system entity, fa lse /// @returns True if A and B both represent the same file system entity, fa lse
/// otherwise. /// otherwise.
bool equivalent(file_status A, file_status B); bool equivalent(file_status A, file_status B);
/// @brief Do paths represent the same thing? /// @brief Do paths represent the same thing?
/// ///
/// assert(status_known(A) || status_known(B)); /// assert(status_known(A) || status_known(B));
/// ///
/// @param A Input path A. /// @param A Input path A.
/// @param B Input path B. /// @param B Input path B.
/// @param result Set to true if stat(A) and stat(B) have the same device a nd /// @param result Set to true if stat(A) and stat(B) have the same device a nd
/// inode (or equivalent). /// inode (or equivalent).
/// @results errc::success if result has been successfully set, otherwise a /// @returns errc::success if result has been successfully set, otherwise a
/// platform specific error_code. /// platform specific error_code.
error_code equivalent(const Twine &A, const Twine &B, bool &result); error_code equivalent(const Twine &A, const Twine &B, bool &result);
/// @brief Simpler version of equivalent for clients that don't need to
/// differentiate between an error and false.
inline bool equivalent(const Twine &A, const Twine &B) {
bool result;
return !equivalent(A, B, result) && result;
}
/// @brief Get file size. /// @brief Get file size.
/// ///
/// @param path Input path. /// @param path Input path.
/// @param result Set to the size of the file in \a path. /// @param result Set to the size of the file in \a path.
/// @returns errc::success if result has been successfully set, otherwise a /// @returns errc::success if result has been successfully set, otherwise a
/// platform specific error_code. /// platform specific error_code.
error_code file_size(const Twine &path, uint64_t &result); error_code file_size(const Twine &path, uint64_t &result);
/// @brief Does status represent a directory? /// @brief Does status represent a directory?
/// ///
/// @param status A file_status previously returned from status. /// @param status A file_status previously returned from status.
/// @results status.type() == file_type::directory_file. /// @returns status.type() == file_type::directory_file.
bool is_directory(file_status status); bool is_directory(file_status status);
/// @brief Is path a directory? /// @brief Is path a directory?
/// ///
/// @param path Input path. /// @param path Input path.
/// @param result Set to true if \a path is a directory, false if it is not . /// @param result Set to true if \a path is a directory, false if it is not .
/// Undefined otherwise. /// Undefined otherwise.
/// @results errc::success if result has been successfully set, otherwise a /// @returns errc::success if result has been successfully set, otherwise a
/// platform specific error_code. /// platform specific error_code.
error_code is_directory(const Twine &path, bool &result); error_code is_directory(const Twine &path, bool &result);
/// @brief Does status represent a regular file? /// @brief Does status represent a regular file?
/// ///
/// @param status A file_status previously returned from status. /// @param status A file_status previously returned from status.
/// @results status_known(status) && status.type() == file_type::regular_fi le. /// @returns status_known(status) && status.type() == file_type::regular_fi le.
bool is_regular_file(file_status status); bool is_regular_file(file_status status);
/// @brief Is path a regular file? /// @brief Is path a regular file?
/// ///
/// @param path Input path. /// @param path Input path.
/// @param result Set to true if \a path is a regular file, false if it is not. /// @param result Set to true if \a path is a regular file, false if it is not.
/// Undefined otherwise. /// Undefined otherwise.
/// @results errc::success if result has been successfully set, otherwise a /// @returns errc::success if result has been successfully set, otherwise a
/// platform specific error_code. /// platform specific error_code.
error_code is_regular_file(const Twine &path, bool &result); error_code is_regular_file(const Twine &path, bool &result);
/// @brief Does this status represent something that exists but is not a /// @brief Does this status represent something that exists but is not a
/// directory, regular file, or symlink? /// directory, regular file, or symlink?
/// ///
/// @param status A file_status previously returned from status. /// @param status A file_status previously returned from status.
/// @results exists(s) && !is_regular_file(s) && !is_directory(s) && /// @returns exists(s) && !is_regular_file(s) && !is_directory(s) &&
/// !is_symlink(s) /// !is_symlink(s)
bool is_other(file_status status); bool is_other(file_status status);
/// @brief Is path something that exists but is not a directory, /// @brief Is path something that exists but is not a directory,
/// regular file, or symlink? /// regular file, or symlink?
/// ///
/// @param path Input path. /// @param path Input path.
/// @param result Set to true if \a path exists, but is not a directory, re gular /// @param result Set to true if \a path exists, but is not a directory, re gular
/// file, or a symlink, false if it does not. Undefined other wise. /// file, or a symlink, false if it does not. Undefined other wise.
/// @results errc::success if result has been successfully set, otherwise a /// @returns errc::success if result has been successfully set, otherwise a
/// platform specific error_code. /// platform specific error_code.
error_code is_other(const Twine &path, bool &result); error_code is_other(const Twine &path, bool &result);
/// @brief Does status represent a symlink? /// @brief Does status represent a symlink?
/// ///
/// @param status A file_status previously returned from stat. /// @param status A file_status previously returned from stat.
/// @param result status.type() == symlink_file. /// @returns status.type() == symlink_file.
bool is_symlink(file_status status); bool is_symlink(file_status status);
/// @brief Is path a symlink? /// @brief Is path a symlink?
/// ///
/// @param path Input path. /// @param path Input path.
/// @param result Set to true if \a path is a symlink, false if it is not. /// @param result Set to true if \a path is a symlink, false if it is not.
/// Undefined otherwise. /// Undefined otherwise.
/// @results errc::success if result has been successfully set, otherwise a /// @returns errc::success if result has been successfully set, otherwise a
/// platform specific error_code. /// platform specific error_code.
error_code is_symlink(const Twine &path, bool &result); error_code is_symlink(const Twine &path, bool &result);
/// @brief Get file status as if by POSIX stat(). /// @brief Get file status as if by POSIX stat().
/// ///
/// @param path Input path. /// @param path Input path.
/// @param result Set to the file status. /// @param result Set to the file status.
/// @results errc::success if result has been successfully set, otherwise a /// @returns errc::success if result has been successfully set, otherwise a
/// platform specific error_code. /// platform specific error_code.
error_code status(const Twine &path, file_status &result); error_code status(const Twine &path, file_status &result);
/// @brief Is status available? /// @brief Modifies permission bits on a file
/// ///
/// @param path Input path. /// @param path Input path.
/// @results True if status() != status_error. /// @returns errc::success if permissions have been changed, otherwise a
/// platform specific error_code.
error_code permissions(const Twine &path, perms prms);
/// @brief Is status available?
///
/// @param s Input file status.
/// @returns True if status() != status_error.
bool status_known(file_status s); bool status_known(file_status s);
/// @brief Is status available? /// @brief Is status available?
/// ///
/// @param path Input path. /// @param path Input path.
/// @param result Set to true if status() != status_error. /// @param result Set to true if status() != status_error.
/// @results errc::success if result has been successfully set, otherwise a /// @returns errc::success if result has been successfully set, otherwise a
/// platform specific error_code. /// platform specific error_code.
error_code status_known(const Twine &path, bool &result); error_code status_known(const Twine &path, bool &result);
/// @brief Generate a unique path and open it as a file. /// @brief Generate a unique path and open it as a file.
/// ///
/// Generates a unique path suitable for a temporary file and then opens it as a /// Generates a unique path suitable for a temporary file and then opens it as a
/// file. The name is based on \a model with '%' replaced by a random char in /// file. The name is based on \a model with '%' replaced by a random char in
/// [0-9a-f]. If \a model is not an absolute path, a suitable temporary /// [0-9a-f]. If \a model is not an absolute path, a suitable temporary
/// directory will be prepended. /// directory will be prepended.
/// ///
/// This is an atomic operation. Either the file is created and opened, or the /// This is an atomic operation. Either the file is created and opened, or the
/// file system is left untouched. /// file system is left untouched.
/// ///
/// clang-%%-%%-%%-%%-%%.s => /tmp/clang-a0-b1-c2-d3-e4.s /// clang-%%-%%-%%-%%-%%.s => /tmp/clang-a0-b1-c2-d3-e4.s
/// ///
/// @param model Name to base unique path off of. /// @param model Name to base unique path off of.
/// @param result_fs Set to the opened file's file descriptor. /// @param result_fd Set to the opened file's file descriptor.
/// @param result_path Set to the opened file's absolute path. /// @param result_path Set to the opened file's absolute path.
/// @param makeAbsolute If true and @model is not an absolute path, a temp /// @param makeAbsolute If true and \a model is not an absolute path, a tem p
/// directory will be prepended. /// directory will be prepended.
/// @results errc::success if result_{fd,path} have been successfully set, /// @returns errc::success if result_{fd,path} have been successfully set,
/// otherwise a platform specific error_code. /// otherwise a platform specific error_code.
error_code unique_file(const Twine &model, int &result_fd, error_code unique_file(const Twine &model, int &result_fd,
SmallVectorImpl<char> &result_path, SmallVectorImpl<char> &result_path,
bool makeAbsolute = true); bool makeAbsolute = true, unsigned mode = 0600);
/// @brief Canonicalize path. /// @brief Canonicalize path.
/// ///
/// Sets result to the file system's idea of what path is. The result is al ways /// Sets result to the file system's idea of what path is. The result is al ways
/// absolute and has the same capitalization as the file system. /// absolute and has the same capitalization as the file system.
/// ///
/// @param path Input path. /// @param path Input path.
/// @param result Set to the canonicalized version of \a path. /// @param result Set to the canonicalized version of \a path.
/// @results errc::success if result has been successfully set, otherwise a /// @returns errc::success if result has been successfully set, otherwise a
/// platform specific error_code. /// platform specific error_code.
error_code canonicalize(const Twine &path, SmallVectorImpl<char> &result); error_code canonicalize(const Twine &path, SmallVectorImpl<char> &result);
/// @brief Are \a path's first bytes \a magic? /// @brief Are \a path's first bytes \a magic?
/// ///
/// @param path Input path. /// @param path Input path.
/// @param magic Byte sequence to compare \a path's first len(magic) bytes to. /// @param magic Byte sequence to compare \a path's first len(magic) bytes to.
/// @results errc::success if result has been successfully set, otherwise a /// @returns errc::success if result has been successfully set, otherwise a
/// platform specific error_code. /// platform specific error_code.
error_code has_magic(const Twine &path, const Twine &magic, bool &result); error_code has_magic(const Twine &path, const Twine &magic, bool &result);
/// @brief Get \a path's first \a len bytes. /// @brief Get \a path's first \a len bytes.
/// ///
/// @param path Input path. /// @param path Input path.
/// @param len Number of magic bytes to get. /// @param len Number of magic bytes to get.
/// @param result Set to the first \a len bytes in the file pointed to by /// @param result Set to the first \a len bytes in the file pointed to by
/// \a path. Or the entire file if file_size(path) < len, in which /// \a path. Or the entire file if file_size(path) < len, in which
/// case result.size() returns the size of the file. /// case result.size() returns the size of the file.
/// @results errc::success if result has been successfully set, /// @returns errc::success if result has been successfully set,
/// errc::value_too_large if len is larger then the file pointed t o by /// errc::value_too_large if len is larger then the file pointed t o by
/// \a path, otherwise a platform specific error_code. /// \a path, otherwise a platform specific error_code.
error_code get_magic(const Twine &path, uint32_t len, error_code get_magic(const Twine &path, uint32_t len,
SmallVectorImpl<char> &result); SmallVectorImpl<char> &result);
/// @brief Identify the type of a binary file based on how magical it is. /// @brief Identify the type of a binary file based on how magical it is.
file_magic identify_magic(StringRef magic); file_magic identify_magic(StringRef magic);
/// @brief Get and identify \a path's type based on its content. /// @brief Get and identify \a path's type based on its content.
/// ///
/// @param path Input path. /// @param path Input path.
/// @param result Set to the type of file, or LLVMFileType::Unknown_FileTyp e. /// @param result Set to the type of file, or LLVMFileType::Unknown_FileTyp e.
/// @results errc::success if result has been successfully set, otherwise a /// @returns errc::success if result has been successfully set, otherwise a
/// platform specific error_code. /// platform specific error_code.
error_code identify_magic(const Twine &path, file_magic &result); error_code identify_magic(const Twine &path, file_magic &result);
/// @brief Get library paths the system linker uses. /// @brief Get library paths the system linker uses.
/// ///
/// @param result Set to the list of system library paths. /// @param result Set to the list of system library paths.
/// @results errc::success if result has been successfully set, otherwise a /// @returns errc::success if result has been successfully set, otherwise a
/// platform specific error_code. /// platform specific error_code.
error_code GetSystemLibraryPaths(SmallVectorImpl<std::string> &result); error_code GetSystemLibraryPaths(SmallVectorImpl<std::string> &result);
/// @brief Get bitcode library paths the system linker uses /// @brief Get bitcode library paths the system linker uses
/// + LLVM_LIB_SEARCH_PATH + LLVM_LIBDIR. /// + LLVM_LIB_SEARCH_PATH + LLVM_LIBDIR.
/// ///
/// @param result Set to the list of bitcode library paths. /// @param result Set to the list of bitcode library paths.
/// @results errc::success if result has been successfully set, otherwise a /// @returns errc::success if result has been successfully set, otherwise a
/// platform specific error_code. /// platform specific error_code.
error_code GetBitcodeLibraryPaths(SmallVectorImpl<std::string> &result); error_code GetBitcodeLibraryPaths(SmallVectorImpl<std::string> &result);
/// @brief Find a library. /// @brief Find a library.
/// ///
/// Find the path to a library using its short name. Use the system /// Find the path to a library using its short name. Use the system
/// dependent library paths to locate the library. /// dependent library paths to locate the library.
/// ///
/// c => /usr/lib/libc.so /// c => /usr/lib/libc.so
/// ///
/// @param short_name Library name one would give to the system linker. /// @param short_name Library name one would give to the system linker.
/// @param result Set to the absolute path \a short_name represents. /// @param result Set to the absolute path \a short_name represents.
/// @results errc::success if result has been successfully set, otherwise a /// @returns errc::success if result has been successfully set, otherwise a
/// platform specific error_code. /// platform specific error_code.
error_code FindLibrary(const Twine &short_name, SmallVectorImpl<char> &resu lt); error_code FindLibrary(const Twine &short_name, SmallVectorImpl<char> &resu lt);
/// @brief Get absolute path of main executable. /// @brief Get absolute path of main executable.
/// ///
/// @param argv0 The program name as it was spelled on the command line. /// @param argv0 The program name as it was spelled on the command line.
/// @param MainAddr Address of some symbol in the executable (not in a libr ary). /// @param MainAddr Address of some symbol in the executable (not in a libr ary).
/// @param result Set to the absolute path of the current executable. /// @param result Set to the absolute path of the current executable.
/// @results errc::success if result has been successfully set, otherwise a /// @returns errc::success if result has been successfully set, otherwise a
/// platform specific error_code. /// platform specific error_code.
error_code GetMainExecutable(const char *argv0, void *MainAddr, error_code GetMainExecutable(const char *argv0, void *MainAddr,
SmallVectorImpl<char> &result); SmallVectorImpl<char> &result);
/// This class represents a memory mapped file. It is based on
/// boost::iostreams::mapped_file.
class mapped_file_region {
mapped_file_region() LLVM_DELETED_FUNCTION;
mapped_file_region(mapped_file_region&) LLVM_DELETED_FUNCTION;
mapped_file_region &operator =(mapped_file_region&) LLVM_DELETED_FUNCTION
;
public:
enum mapmode {
readonly, ///< May only access map via const_data as read only.
readwrite, ///< May access map via data and modify it. Written to path.
priv ///< May modify via data, but changes are lost on destruction.
};
private:
/// Platform specific mapping state.
mapmode Mode;
uint64_t Size;
void *Mapping;
#ifdef LLVM_ON_WIN32
int FileDescriptor;
void *FileHandle;
void *FileMappingHandle;
#endif
error_code init(int FD, uint64_t Offset);
public:
typedef char char_type;
#if LLVM_USE_RVALUE_REFERENCES
mapped_file_region(mapped_file_region&&);
mapped_file_region &operator =(mapped_file_region&&);
#endif
/// Construct a mapped_file_region at \a path starting at \a offset of le
ngth
/// \a length and with access \a mode.
///
/// \param path Path to the file to map. If it does not exist it will be
/// created.
/// \param mode How to map the memory.
/// \param length Number of bytes to map in starting at \a offset. If the
file
/// is shorter than this, it will be extended. If \a length
is
/// 0, the entire file will be mapped.
/// \param offset Byte offset from the beginning of the file where the ma
p
/// should begin. Must be a multiple of
/// mapped_file_region::alignment().
/// \param ec This is set to errc::success if the map was constructed
/// sucessfully. Otherwise it is set to a platform dependent er
ror.
mapped_file_region(const Twine &path,
mapmode mode,
uint64_t length,
uint64_t offset,
error_code &ec);
/// \param fd An open file descriptor to map. mapped_file_region takes
/// ownership. It must have been opended in the correct mode.
mapped_file_region(int fd,
mapmode mode,
uint64_t length,
uint64_t offset,
error_code &ec);
~mapped_file_region();
mapmode flags() const;
uint64_t size() const;
char *data() const;
/// Get a const view of the data. Modifying this memory has undefined
/// behaivor.
const char *const_data() const;
/// \returns The minimum alignment offset must be.
static int alignment();
};
/// @brief Memory maps the contents of a file
///
/// @param path Path to file to map.
/// @param file_offset Byte offset in file where mapping should begin.
/// @param size Byte length of range of the file to map.
/// @param map_writable If true, the file will be mapped in r/w such
/// that changes to the mapped buffer will be flushed back
/// to the file. If false, the file will be mapped read-only
/// and the buffer will be read-only.
/// @param result Set to the start address of the mapped buffer.
/// @returns errc::success if result has been successfully set, otherwise a
/// platform specific error_code.
error_code map_file_pages(const Twine &path, off_t file_offset, size_t size
,
bool map_writable, void *&result);
/// @brief Memory unmaps the contents of a file
///
/// @param base Pointer to the start of the buffer.
/// @param size Byte length of the range to unmmap.
/// @returns errc::success if result has been successfully set, otherwise a
/// platform specific error_code.
error_code unmap_file_pages(void *base, size_t size);
/// @} /// @}
/// @name Iterators /// @name Iterators
/// @{ /// @{
/// directory_entry - A single entry in a directory. Caches the status eith er /// directory_entry - A single entry in a directory. Caches the status eith er
/// from the result of the iteration syscall, or the first time status is /// from the result of the iteration syscall, or the first time status is
/// called. /// called.
class directory_entry { class directory_entry {
std::string Path; std::string Path;
mutable file_status Status; mutable file_status Status;
 End of changes. 42 change blocks. 
37 lines changed or deleted 214 lines changed or added


 FoldingSet.h   FoldingSet.h 
skipping to change at line 281 skipping to change at line 281
public: public:
FoldingSetNodeIDRef() : Data(0), Size(0) {} FoldingSetNodeIDRef() : Data(0), Size(0) {}
FoldingSetNodeIDRef(const unsigned *D, size_t S) : Data(D), Size(S) {} FoldingSetNodeIDRef(const unsigned *D, size_t S) : Data(D), Size(S) {}
/// ComputeHash - Compute a strong hash value for this FoldingSetNodeIDRe f, /// ComputeHash - Compute a strong hash value for this FoldingSetNodeIDRe f,
/// used to lookup the node in the FoldingSetImpl. /// used to lookup the node in the FoldingSetImpl.
unsigned ComputeHash() const; unsigned ComputeHash() const;
bool operator==(FoldingSetNodeIDRef) const; bool operator==(FoldingSetNodeIDRef) const;
/// Used to compare the "ordering" of two nodes as defined by the
/// profiled bits and their ordering defined by memcmp().
bool operator<(FoldingSetNodeIDRef) const;
const unsigned *getData() const { return Data; } const unsigned *getData() const { return Data; }
size_t getSize() const { return Size; } size_t getSize() const { return Size; }
}; };
//===--------------------------------------------------------------------== =// //===--------------------------------------------------------------------== =//
/// FoldingSetNodeID - This class is used to gather all the unique data bit s of /// FoldingSetNodeID - This class is used to gather all the unique data bit s of
/// a node. When all the bits are gathered this class is used to produce a /// a node. When all the bits are gathered this class is used to produce a
/// hash value for the node. /// hash value for the node.
/// ///
class FoldingSetNodeID { class FoldingSetNodeID {
skipping to change at line 330 skipping to change at line 334
/// ComputeHash - Compute a strong hash value for this FoldingSetNodeID, used /// ComputeHash - Compute a strong hash value for this FoldingSetNodeID, used
/// to lookup the node in the FoldingSetImpl. /// to lookup the node in the FoldingSetImpl.
unsigned ComputeHash() const; unsigned ComputeHash() const;
/// operator== - Used to compare two nodes to each other. /// operator== - Used to compare two nodes to each other.
/// ///
bool operator==(const FoldingSetNodeID &RHS) const; bool operator==(const FoldingSetNodeID &RHS) const;
bool operator==(const FoldingSetNodeIDRef RHS) const; bool operator==(const FoldingSetNodeIDRef RHS) const;
/// Used to compare the "ordering" of two nodes as defined by the
/// profiled bits and their ordering defined by memcmp().
bool operator<(const FoldingSetNodeID &RHS) const;
bool operator<(const FoldingSetNodeIDRef RHS) const;
/// Intern - Copy this node's data to a memory region allocated from the /// Intern - Copy this node's data to a memory region allocated from the
/// given allocator and return a FoldingSetNodeIDRef describing the /// given allocator and return a FoldingSetNodeIDRef describing the
/// interned data. /// interned data.
FoldingSetNodeIDRef Intern(BumpPtrAllocator &Allocator) const; FoldingSetNodeIDRef Intern(BumpPtrAllocator &Allocator) const;
}; };
// Convenience type to hide the implementation of the folding set. // Convenience type to hide the implementation of the folding set.
typedef FoldingSetImpl::Node FoldingSetNode; typedef FoldingSetImpl::Node FoldingSetNode;
template<class T> class FoldingSetIterator; template<class T> class FoldingSetIterator;
template<class T> class FoldingSetBucketIterator; template<class T> class FoldingSetBucketIterator;
skipping to change at line 520 skipping to change at line 529
/// FindNodeOrInsertPos - Look up the node specified by ID. If it /// FindNodeOrInsertPos - Look up the node specified by ID. If it
/// exists, return it. If not, return the insertion token that will /// exists, return it. If not, return the insertion token that will
/// make insertion faster. /// make insertion faster.
T *FindNodeOrInsertPos(const FoldingSetNodeID &ID, void *&InsertPos) { T *FindNodeOrInsertPos(const FoldingSetNodeID &ID, void *&InsertPos) {
return static_cast<T *>(FoldingSetImpl::FindNodeOrInsertPos(ID, InsertP os)); return static_cast<T *>(FoldingSetImpl::FindNodeOrInsertPos(ID, InsertP os));
} }
}; };
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
/// FoldingSetVectorIterator - This implements an iterator for
/// FoldingSetVector. It is only necessary because FoldingSetIterator provi
des
/// a value_type of T, while the vector in FoldingSetVector exposes
/// a value_type of T*. Fortunately, FoldingSetIterator doesn't expose very
/// much besides operator* and operator->, so we just wrap the inner vector
/// iterator and perform the extra dereference.
template <class T, class VectorIteratorT>
class FoldingSetVectorIterator {
// Provide a typedef to workaround the lack of correct injected class nam
e
// support in older GCCs.
typedef FoldingSetVectorIterator<T, VectorIteratorT> SelfT;
VectorIteratorT Iterator;
public:
FoldingSetVectorIterator(VectorIteratorT I) : Iterator(I) {}
bool operator==(const SelfT &RHS) const {
return Iterator == RHS.Iterator;
}
bool operator!=(const SelfT &RHS) const {
return Iterator != RHS.Iterator;
}
T &operator*() const { return **Iterator; }
T *operator->() const { return *Iterator; }
inline SelfT &operator++() {
++Iterator;
return *this;
}
SelfT operator++(int) {
SelfT tmp = *this;
++*this;
return tmp;
}
};
//===----------------------------------------------------------------------
===//
/// FoldingSetVector - This template class combines a FoldingSet and a vect
or
/// to provide the interface of FoldingSet but with deterministic iteration
/// order based on the insertion order. T must be a subclass of FoldingSetN
ode
/// and implement a Profile function.
template <class T, class VectorT = SmallVector<T*, 8> >
class FoldingSetVector {
FoldingSet<T> Set;
VectorT Vector;
public:
explicit FoldingSetVector(unsigned Log2InitSize = 6)
: Set(Log2InitSize) {
}
typedef FoldingSetVectorIterator<T, typename VectorT::iterator> iterator;
iterator begin() { return Vector.begin(); }
iterator end() { return Vector.end(); }
typedef FoldingSetVectorIterator<const T, typename VectorT::const_iterato
r>
const_iterator;
const_iterator begin() const { return Vector.begin(); }
const_iterator end() const { return Vector.end(); }
/// clear - Remove all nodes from the folding set.
void clear() { Set.clear(); Vector.clear(); }
/// FindNodeOrInsertPos - Look up the node specified by ID. If it exists
,
/// return it. If not, return the insertion token that will make inserti
on
/// faster.
T *FindNodeOrInsertPos(const FoldingSetNodeID &ID, void *&InsertPos) {
return Set.FindNodeOrInsertPos(ID, InsertPos);
}
/// GetOrInsertNode - If there is an existing simple Node exactly
/// equal to the specified node, return it. Otherwise, insert 'N' and
/// return it instead.
T *GetOrInsertNode(T *N) {
T *Result = Set.GetOrInsertNode(N);
if (Result == N) Vector.push_back(N);
return Result;
}
/// InsertNode - Insert the specified node into the folding set, knowing
that
/// it is not already in the folding set. InsertPos must be obtained fro
m
/// FindNodeOrInsertPos.
void InsertNode(T *N, void *InsertPos) {
Set.InsertNode(N, InsertPos);
Vector.push_back(N);
}
/// InsertNode - Insert the specified node into the folding set, knowing
that
/// it is not already in the folding set.
void InsertNode(T *N) {
Set.InsertNode(N);
Vector.push_back(N);
}
/// size - Returns the number of nodes in the folding set.
unsigned size() const { return Set.size(); }
/// empty - Returns true if there are no nodes in the folding set.
bool empty() const { return Set.empty(); }
};
//===----------------------------------------------------------------------
===//
/// FoldingSetIteratorImpl - This is the common iterator support shared by all /// FoldingSetIteratorImpl - This is the common iterator support shared by all
/// folding sets, which knows how to walk the folding set hash table. /// folding sets, which knows how to walk the folding set hash table.
class FoldingSetIteratorImpl { class FoldingSetIteratorImpl {
protected: protected:
FoldingSetNode *NodePtr; FoldingSetNode *NodePtr;
FoldingSetIteratorImpl(void **Bucket); FoldingSetIteratorImpl(void **Bucket);
void advance(); void advance();
public: public:
bool operator==(const FoldingSetIteratorImpl &RHS) const { bool operator==(const FoldingSetIteratorImpl &RHS) const {
 End of changes. 3 change blocks. 
0 lines changed or deleted 126 lines changed or added


 Format.h   Format.h 
skipping to change at line 173 skipping to change at line 173
const T3 &val3, const T4 &val4, const T5 &val5) const T3 &val3, const T4 &val4, const T5 &val5)
: format_object_base(fmt), Val1(val1), Val2(val2), Val3(val3), Val4(val 4), : format_object_base(fmt), Val1(val1), Val2(val2), Val3(val3), Val4(val 4),
Val5(val5) { Val5(val5) {
} }
virtual int snprint(char *Buffer, unsigned BufferSize) const { virtual int snprint(char *Buffer, unsigned BufferSize) const {
return snprintf(Buffer, BufferSize, Fmt, Val1, Val2, Val3, Val4, Val5); return snprintf(Buffer, BufferSize, Fmt, Val1, Val2, Val3, Val4, Val5);
} }
}; };
/// format - This is a helper function that is used to produce formatted ou /// This is a helper function that is used to produce formatted output.
tput. ///
/// This is typically used like: OS << format("%0.4f", myfloat) << '\n'; /// This is typically used like:
/// \code
/// OS << format("%0.4f", myfloat) << '\n';
/// \endcode
template <typename T> template <typename T>
inline format_object1<T> format(const char *Fmt, const T &Val) { inline format_object1<T> format(const char *Fmt, const T &Val) {
return format_object1<T>(Fmt, Val); return format_object1<T>(Fmt, Val);
} }
/// format - This is a helper function that is used to produce formatted ou /// This is a helper function that is used to produce formatted output.
tput. ///
/// This is typically used like: OS << format("%0.4f", myfloat) << '\n'; /// This is typically used like:
/// \code
/// OS << format("%0.4f", myfloat) << '\n';
/// \endcode
template <typename T1, typename T2> template <typename T1, typename T2>
inline format_object2<T1, T2> format(const char *Fmt, const T1 &Val1, inline format_object2<T1, T2> format(const char *Fmt, const T1 &Val1,
const T2 &Val2) { const T2 &Val2) {
return format_object2<T1, T2>(Fmt, Val1, Val2); return format_object2<T1, T2>(Fmt, Val1, Val2);
} }
/// format - This is a helper function that is used to produce formatted ou /// This is a helper function that is used to produce formatted output.
tput. ///
/// This is typically used like: OS << format("%0.4f", myfloat) << '\n'; /// This is typically used like:
/// \code
/// OS << format("%0.4f", myfloat) << '\n';
/// \endcode
template <typename T1, typename T2, typename T3> template <typename T1, typename T2, typename T3>
inline format_object3<T1, T2, T3> format(const char *Fmt, const T1 &Val1, inline format_object3<T1, T2, T3> format(const char *Fmt, const T1 &Val1,
const T2 &Val2, const T3 &Val3) { const T2 &Val2, const T3 &Val3) {
return format_object3<T1, T2, T3>(Fmt, Val1, Val2, Val3); return format_object3<T1, T2, T3>(Fmt, Val1, Val2, Val3);
} }
/// format - This is a helper function that is used to produce formatted ou /// This is a helper function that is used to produce formatted output.
tput. ///
/// This is typically used like: OS << format("%0.4f", myfloat) << '\n'; /// This is typically used like:
/// \code
/// OS << format("%0.4f", myfloat) << '\n';
/// \endcode
template <typename T1, typename T2, typename T3, typename T4> template <typename T1, typename T2, typename T3, typename T4>
inline format_object4<T1, T2, T3, T4> format(const char *Fmt, const T1 &Val 1, inline format_object4<T1, T2, T3, T4> format(const char *Fmt, const T1 &Val 1,
const T2 &Val2, const T3 &Val3 , const T2 &Val2, const T3 &Val3 ,
const T4 &Val4) { const T4 &Val4) {
return format_object4<T1, T2, T3, T4>(Fmt, Val1, Val2, Val3, Val4); return format_object4<T1, T2, T3, T4>(Fmt, Val1, Val2, Val3, Val4);
} }
/// format - This is a helper function that is used to produce formatted ou /// This is a helper function that is used to produce formatted output.
tput. ///
/// This is typically used like: OS << format("%0.4f", myfloat) << '\n'; /// This is typically used like:
/// \code
/// OS << format("%0.4f", myfloat) << '\n';
/// \endcode
template <typename T1, typename T2, typename T3, typename T4, typename T5> template <typename T1, typename T2, typename T3, typename T4, typename T5>
inline format_object5<T1, T2, T3, T4, T5> format(const char *Fmt,const T1 & Val1, inline format_object5<T1, T2, T3, T4, T5> format(const char *Fmt,const T1 & Val1,
const T2 &Val2, const T3 &Val3 , const T2 &Val2, const T3 &Val3 ,
const T4 &Val4, const T5 &Val5 ) { const T4 &Val4, const T5 &Val5 ) {
return format_object5<T1, T2, T3, T4, T5>(Fmt, Val1, Val2, Val3, Val4, Va l5); return format_object5<T1, T2, T3, T4, T5>(Fmt, Val1, Val2, Val3, Val4, Va l5);
} }
} // end namespace llvm } // end namespace llvm
#endif #endif
 End of changes. 5 change blocks. 
15 lines changed or deleted 30 lines changed or added


 FormattedStream.h   FormattedStream.h 
skipping to change at line 58 skipping to change at line 58
/// been flushed and the portion of the buffer that's been /// been flushed and the portion of the buffer that's been
/// scanned. The column scheme is zero-based. /// scanned. The column scheme is zero-based.
/// ///
unsigned ColumnScanned; unsigned ColumnScanned;
/// Scanned - This points to one past the last character in the /// Scanned - This points to one past the last character in the
/// buffer we've scanned. /// buffer we've scanned.
/// ///
const char *Scanned; const char *Scanned;
virtual void write_impl(const char *Ptr, size_t Size); virtual void write_impl(const char *Ptr, size_t Size) LLVM_OVERRIDE;
/// current_pos - Return the current position within the stream, /// current_pos - Return the current position within the stream,
/// not counting the bytes currently in the buffer. /// not counting the bytes currently in the buffer.
virtual uint64_t current_pos() const { virtual uint64_t current_pos() const LLVM_OVERRIDE {
// This has the same effect as calling TheStream.current_pos(), // Our current position in the stream is all the contents which have
// but that interface is private. been
return TheStream->tell() - TheStream->GetNumBytesInBuffer(); // written to the underlying stream (*not* the current position of th
e
// underlying stream).
return TheStream->tell();
} }
/// ComputeColumn - Examine the given output buffer and figure out whic h /// ComputeColumn - Examine the given output buffer and figure out whic h
/// column we end up in after output. /// column we end up in after output.
/// ///
void ComputeColumn(const char *Ptr, size_t size); void ComputeColumn(const char *Ptr, size_t size);
public: public:
/// formatted_raw_ostream - Open the specified file for /// formatted_raw_ostream - Open the specified file for
/// writing. If an error occurs, information about the error is /// writing. If an error occurs, information about the error is
 End of changes. 2 change blocks. 
5 lines changed or deleted 8 lines changed or added


 Function.h   Function.h 
skipping to change at line 113 skipping to change at line 113
/// hasn't been set up yet. /// hasn't been set up yet.
bool hasLazyArguments() const { bool hasLazyArguments() const {
return getSubclassDataFromValue() & 1; return getSubclassDataFromValue() & 1;
} }
void CheckLazyArguments() const { void CheckLazyArguments() const {
if (hasLazyArguments()) if (hasLazyArguments())
BuildLazyArguments(); BuildLazyArguments();
} }
void BuildLazyArguments() const; void BuildLazyArguments() const;
Function(const Function&); // DO NOT IMPLEMENT Function(const Function&) LLVM_DELETED_FUNCTION;
void operator=(const Function&); // DO NOT IMPLEMENT void operator=(const Function&) LLVM_DELETED_FUNCTION;
/// Function ctor - If the (optional) Module argument is specified, the /// Function ctor - If the (optional) Module argument is specified, the
/// function is automatically inserted into the end of the function list for /// function is automatically inserted into the end of the function list for
/// the module. /// the module.
/// ///
Function(FunctionType *Ty, LinkageTypes Linkage, Function(FunctionType *Ty, LinkageTypes Linkage,
const Twine &N = "", Module *M = 0); const Twine &N = "", Module *M = 0);
public: public:
static Function *Create(FunctionType *Ty, LinkageTypes Linkage, static Function *Create(FunctionType *Ty, LinkageTypes Linkage,
skipping to change at line 171 skipping to change at line 171
} }
/// getAttributes - Return the attribute list for this Function. /// getAttributes - Return the attribute list for this Function.
/// ///
const AttrListPtr &getAttributes() const { return AttributeList; } const AttrListPtr &getAttributes() const { return AttributeList; }
/// setAttributes - Set the attribute list for this Function. /// setAttributes - Set the attribute list for this Function.
/// ///
void setAttributes(const AttrListPtr &attrs) { AttributeList = attrs; } void setAttributes(const AttrListPtr &attrs) { AttributeList = attrs; }
/// hasFnAttr - Return true if this function has the given attribute. /// getFnAttributes - Return the function attributes for querying.
bool hasFnAttr(Attributes N) const { ///
// Function Attributes are stored at ~0 index Attributes getFnAttributes() const {
return AttributeList.paramHasAttr(~0U, N); return AttributeList.getFnAttributes();
} }
/// addFnAttr - Add function attributes to this function. /// addFnAttr - Add function attributes to this function.
/// ///
void addFnAttr(Attributes N) { void addFnAttr(Attributes::AttrVal N) {
// Function Attributes are stored at ~0 index // Function Attributes are stored at ~0 index
addAttribute(~0U, N); addAttribute(AttrListPtr::FunctionIndex, Attributes::get(getContext(), N));
} }
/// removeFnAttr - Remove function attributes from this function. /// removeFnAttr - Remove function attributes from this function.
/// ///
void removeFnAttr(Attributes N) { void removeFnAttr(Attributes N) {
// Function Attributes are stored at ~0 index // Function Attributes are stored at ~0 index
removeAttribute(~0U, N); removeAttribute(~0U, N);
} }
/// hasGC/getGC/setGC/clearGC - The name of the garbage collection algori thm /// hasGC/getGC/setGC/clearGC - The name of the garbage collection algori thm
/// to use during code generation. /// to use during code generation.
bool hasGC() const; bool hasGC() const;
const char *getGC() const; const char *getGC() const;
void setGC(const char *Str); void setGC(const char *Str);
void clearGC(); void clearGC();
/// @brief Determine whether the function has the given attribute. /// getRetAttributes - Return the return attributes for querying.
bool paramHasAttr(unsigned i, Attributes attr) const { Attributes getRetAttributes() const {
return AttributeList.paramHasAttr(i, attr); return AttributeList.getRetAttributes();
}
/// getParamAttributes - Return the parameter attributes for querying.
Attributes getParamAttributes(unsigned Idx) const {
return AttributeList.getParamAttributes(Idx);
} }
/// addAttribute - adds the attribute to the list of attributes. /// addAttribute - adds the attribute to the list of attributes.
void addAttribute(unsigned i, Attributes attr); void addAttribute(unsigned i, Attributes attr);
/// removeAttribute - removes the attribute from the list of attributes. /// removeAttribute - removes the attribute from the list of attributes.
void removeAttribute(unsigned i, Attributes attr); void removeAttribute(unsigned i, Attributes attr);
/// @brief Extract the alignment for a call or parameter (0=unknown). /// @brief Extract the alignment for a call or parameter (0=unknown).
unsigned getParamAlignment(unsigned i) const { unsigned getParamAlignment(unsigned i) const {
return AttributeList.getParamAlignment(i); return AttributeList.getParamAlignment(i);
} }
/// @brief Determine if the function does not access memory. /// @brief Determine if the function does not access memory.
bool doesNotAccessMemory() const { bool doesNotAccessMemory() const {
return hasFnAttr(Attribute::ReadNone); return getFnAttributes().hasAttribute(Attributes::ReadNone);
} }
void setDoesNotAccessMemory(bool DoesNotAccessMemory = true) { void setDoesNotAccessMemory() {
if (DoesNotAccessMemory) addFnAttr(Attribute::ReadNone); addFnAttr(Attributes::ReadNone);
else removeFnAttr(Attribute::ReadNone);
} }
/// @brief Determine if the function does not access or only reads memory . /// @brief Determine if the function does not access or only reads memory .
bool onlyReadsMemory() const { bool onlyReadsMemory() const {
return doesNotAccessMemory() || hasFnAttr(Attribute::ReadOnly); return doesNotAccessMemory() ||
getFnAttributes().hasAttribute(Attributes::ReadOnly);
} }
void setOnlyReadsMemory(bool OnlyReadsMemory = true) { void setOnlyReadsMemory() {
if (OnlyReadsMemory) addFnAttr(Attribute::ReadOnly); addFnAttr(Attributes::ReadOnly);
else removeFnAttr(Attribute::ReadOnly | Attribute::ReadNone);
} }
/// @brief Determine if the function cannot return. /// @brief Determine if the function cannot return.
bool doesNotReturn() const { bool doesNotReturn() const {
return hasFnAttr(Attribute::NoReturn); return getFnAttributes().hasAttribute(Attributes::NoReturn);
} }
void setDoesNotReturn(bool DoesNotReturn = true) { void setDoesNotReturn() {
if (DoesNotReturn) addFnAttr(Attribute::NoReturn); addFnAttr(Attributes::NoReturn);
else removeFnAttr(Attribute::NoReturn);
} }
/// @brief Determine if the function cannot unwind. /// @brief Determine if the function cannot unwind.
bool doesNotThrow() const { bool doesNotThrow() const {
return hasFnAttr(Attribute::NoUnwind); return getFnAttributes().hasAttribute(Attributes::NoUnwind);
} }
void setDoesNotThrow(bool DoesNotThrow = true) { void setDoesNotThrow() {
if (DoesNotThrow) addFnAttr(Attribute::NoUnwind); addFnAttr(Attributes::NoUnwind);
else removeFnAttr(Attribute::NoUnwind);
} }
/// @brief True if the ABI mandates (or the user requested) that this /// @brief True if the ABI mandates (or the user requested) that this
/// function be in a unwind table. /// function be in a unwind table.
bool hasUWTable() const { bool hasUWTable() const {
return hasFnAttr(Attribute::UWTable); return getFnAttributes().hasAttribute(Attributes::UWTable);
} }
void setHasUWTable(bool HasUWTable = true) { void setHasUWTable() {
if (HasUWTable) addFnAttr(Attributes::UWTable);
addFnAttr(Attribute::UWTable);
else
removeFnAttr(Attribute::UWTable);
} }
/// @brief True if this function needs an unwind table. /// @brief True if this function needs an unwind table.
bool needsUnwindTableEntry() const { bool needsUnwindTableEntry() const {
return hasUWTable() || !doesNotThrow(); return hasUWTable() || !doesNotThrow();
} }
/// @brief Determine if the function returns a structure through first /// @brief Determine if the function returns a structure through first
/// pointer argument. /// pointer argument.
bool hasStructRetAttr() const { bool hasStructRetAttr() const {
return paramHasAttr(1, Attribute::StructRet); return getParamAttributes(1).hasAttribute(Attributes::StructRet);
} }
/// @brief Determine if the parameter does not alias other parameters. /// @brief Determine if the parameter does not alias other parameters.
/// @param n The parameter to check. 1 is the first parameter, 0 is the r eturn /// @param n The parameter to check. 1 is the first parameter, 0 is the r eturn
bool doesNotAlias(unsigned n) const { bool doesNotAlias(unsigned n) const {
return paramHasAttr(n, Attribute::NoAlias); return getParamAttributes(n).hasAttribute(Attributes::NoAlias);
} }
void setDoesNotAlias(unsigned n, bool DoesNotAlias = true) { void setDoesNotAlias(unsigned n) {
if (DoesNotAlias) addAttribute(n, Attribute::NoAlias); addAttribute(n, Attributes::get(getContext(), Attributes::NoAlias));
else removeAttribute(n, Attribute::NoAlias);
} }
/// @brief Determine if the parameter can be captured. /// @brief Determine if the parameter can be captured.
/// @param n The parameter to check. 1 is the first parameter, 0 is the r eturn /// @param n The parameter to check. 1 is the first parameter, 0 is the r eturn
bool doesNotCapture(unsigned n) const { bool doesNotCapture(unsigned n) const {
return paramHasAttr(n, Attribute::NoCapture); return getParamAttributes(n).hasAttribute(Attributes::NoCapture);
} }
void setDoesNotCapture(unsigned n, bool DoesNotCapture = true) { void setDoesNotCapture(unsigned n) {
if (DoesNotCapture) addAttribute(n, Attribute::NoCapture); addAttribute(n, Attributes::get(getContext(), Attributes::NoCapture));
else removeAttribute(n, Attribute::NoCapture);
} }
/// copyAttributesFrom - copy all additional attributes (those not needed to /// copyAttributesFrom - copy all additional attributes (those not needed to
/// create a Function) from the Function Src to this one. /// create a Function) from the Function Src to this one.
void copyAttributesFrom(const GlobalValue *Src); void copyAttributesFrom(const GlobalValue *Src);
/// deleteBody - This method deletes the body of the function, and conver ts /// deleteBody - This method deletes the body of the function, and conver ts
/// the linkage to external. /// the linkage to external.
/// ///
void deleteBody() { void deleteBody() {
skipping to change at line 401 skipping to change at line 398
void viewCFG() const; void viewCFG() const;
/// viewCFGOnly - This function is meant for use from the debugger. It w orks /// viewCFGOnly - This function is meant for use from the debugger. It w orks
/// just like viewCFG, but it does not include the contents of basic bloc ks /// just like viewCFG, but it does not include the contents of basic bloc ks
/// into the nodes, just the label. If you are only interested in the CF G /// into the nodes, just the label. If you are only interested in the CF G
/// this can make the graph smaller. /// this can make the graph smaller.
/// ///
void viewCFGOnly() const; void viewCFGOnly() const;
/// Methods for support type inquiry through isa, cast, and dyn_cast: /// Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const Function *) { return true; }
static inline bool classof(const Value *V) { static inline bool classof(const Value *V) {
return V->getValueID() == Value::FunctionVal; return V->getValueID() == Value::FunctionVal;
} }
/// dropAllReferences() - This method causes all the subinstructions to " let /// dropAllReferences() - This method causes all the subinstructions to " let
/// go" of all references that they are maintaining. This allows one to /// go" of all references that they are maintaining. This allows one to
/// 'delete' a whole module at a time, even though there may be circular /// 'delete' a whole module at a time, even though there may be circular
/// references... first all references are dropped, and all use counts go to /// references... first all references are dropped, and all use counts go to
/// zero. Then everything is deleted for real. Note that no operations are /// zero. Then everything is deleted for real. Note that no operations are
/// valid on an object that has "dropped all references", except operator /// valid on an object that has "dropped all references", except operator
/// delete. /// delete.
/// ///
/// Since no other object in the module can have references into the body of a /// Since no other object in the module can have references into the body of a
/// function, dropping all references deletes the entire body of the func tion, /// function, dropping all references deletes the entire body of the func tion,
/// including any contained basic blocks. /// including any contained basic blocks.
/// ///
void dropAllReferences(); void dropAllReferences();
/// hasAddressTaken - returns true if there are any uses of this function /// hasAddressTaken - returns true if there are any uses of this function
/// other than direct calls or invokes to it. Optionally passes back the /// other than direct calls or invokes to it, or blockaddress expressions
/// offending user for diagnostic purposes. .
/// Optionally passes back an offending user for diagnostic purposes.
/// ///
bool hasAddressTaken(const User** = 0) const; bool hasAddressTaken(const User** = 0) const;
/// isDefTriviallyDead - Return true if it is trivially safe to remove /// isDefTriviallyDead - Return true if it is trivially safe to remove
/// this function definition from the module (because it isn't externally /// this function definition from the module (because it isn't externally
/// visible, does not have its address taken, and has no callers). To ma ke /// visible, does not have its address taken, and has no callers). To ma ke
/// this more accurate, call removeDeadConstantUsers first. /// this more accurate, call removeDeadConstantUsers first.
bool isDefTriviallyDead() const; bool isDefTriviallyDead() const;
/// callsFunctionThatReturnsTwice - Return true if the function has a cal l to /// callsFunctionThatReturnsTwice - Return true if the function has a cal l to
 End of changes. 22 change blocks. 
45 lines changed or deleted 42 lines changed or added


 GCMetadata.h   GCMetadata.h 
skipping to change at line 51 skipping to change at line 51
namespace llvm { namespace llvm {
class AsmPrinter; class AsmPrinter;
class GCStrategy; class GCStrategy;
class Constant; class Constant;
class MCSymbol; class MCSymbol;
namespace GC { namespace GC {
/// PointKind - The type of a collector-safe point. /// PointKind - The type of a collector-safe point.
/// ///
enum PointKind { enum PointKind {
Loop, //< Instr is a loop (backwards branch). Loop, ///< Instr is a loop (backwards branch).
Return, //< Instr is a return instruction. Return, ///< Instr is a return instruction.
PreCall, //< Instr is a call instruction. PreCall, ///< Instr is a call instruction.
PostCall //< Instr is the return address of a call. PostCall ///< Instr is the return address of a call.
}; };
} }
/// GCPoint - Metadata for a collector-safe point in machine code. /// GCPoint - Metadata for a collector-safe point in machine code.
/// ///
struct GCPoint { struct GCPoint {
GC::PointKind Kind; //< The kind of the safe point. GC::PointKind Kind; ///< The kind of the safe point.
MCSymbol *Label; //< A label. MCSymbol *Label; ///< A label.
DebugLoc Loc; DebugLoc Loc;
GCPoint(GC::PointKind K, MCSymbol *L, DebugLoc DL) GCPoint(GC::PointKind K, MCSymbol *L, DebugLoc DL)
: Kind(K), Label(L), Loc(DL) {} : Kind(K), Label(L), Loc(DL) {}
}; };
/// GCRoot - Metadata for a pointer to an object managed by the garbage /// GCRoot - Metadata for a pointer to an object managed by the garbage
/// collector. /// collector.
struct GCRoot { struct GCRoot {
int Num; //< Usually a frame index. int Num; ///< Usually a frame index.
int StackOffset; //< Offset from the stack pointer. int StackOffset; ///< Offset from the stack pointer.
const Constant *Metadata;//< Metadata straight from the call to llvm.gc const Constant *Metadata; ///< Metadata straight from the call
root. ///< to llvm.gcroot.
GCRoot(int N, const Constant *MD) : Num(N), StackOffset(-1), Metadata(M D) {} GCRoot(int N, const Constant *MD) : Num(N), StackOffset(-1), Metadata(M D) {}
}; };
/// GCFunctionInfo - Garbage collection metadata for a single function. /// GCFunctionInfo - Garbage collection metadata for a single function.
/// ///
class GCFunctionInfo { class GCFunctionInfo {
public: public:
typedef std::vector<GCPoint>::iterator iterator; typedef std::vector<GCPoint>::iterator iterator;
typedef std::vector<GCRoot>::iterator roots_iterator; typedef std::vector<GCRoot>::iterator roots_iterator;
skipping to change at line 123 skipping to change at line 124
/// ///
GCStrategy &getStrategy() { return S; } GCStrategy &getStrategy() { return S; }
/// addStackRoot - Registers a root that lives on the stack. Num is the /// addStackRoot - Registers a root that lives on the stack. Num is the
/// stack object ID for the alloca (if the code generato r is /// stack object ID for the alloca (if the code generato r is
// using MachineFrameInfo). // using MachineFrameInfo).
void addStackRoot(int Num, const Constant *Metadata) { void addStackRoot(int Num, const Constant *Metadata) {
Roots.push_back(GCRoot(Num, Metadata)); Roots.push_back(GCRoot(Num, Metadata));
} }
/// removeStackRoot - Removes a root.
roots_iterator removeStackRoot(roots_iterator position) {
return Roots.erase(position);
}
/// addSafePoint - Notes the existence of a safe point. Num is the ID o f the /// addSafePoint - Notes the existence of a safe point. Num is the ID o f the
/// label just prior to the safe point (if the code generator is using /// label just prior to the safe point (if the code generator is using
/// MachineModuleInfo). /// MachineModuleInfo).
void addSafePoint(GC::PointKind Kind, MCSymbol *Label, DebugLoc DL) { void addSafePoint(GC::PointKind Kind, MCSymbol *Label, DebugLoc DL) {
SafePoints.push_back(GCPoint(Kind, Label, DL)); SafePoints.push_back(GCPoint(Kind, Label, DL));
} }
/// getFrameSize/setFrameSize - Records the function's frame size. /// getFrameSize/setFrameSize - Records the function's frame size.
/// ///
uint64_t getFrameSize() const { return FrameSize; } uint64_t getFrameSize() const { return FrameSize; }
 End of changes. 4 change blocks. 
10 lines changed or deleted 15 lines changed or added


 GCMetadataPrinter.h   GCMetadataPrinter.h 
skipping to change at line 51 skipping to change at line 51
private: private:
GCStrategy *S; GCStrategy *S;
friend class AsmPrinter; friend class AsmPrinter;
protected: protected:
// May only be subclassed. // May only be subclassed.
GCMetadataPrinter(); GCMetadataPrinter();
// Do not implement. private:
GCMetadataPrinter(const GCMetadataPrinter &); GCMetadataPrinter(const GCMetadataPrinter &) LLVM_DELETED_FUNCTION;
GCMetadataPrinter &operator=(const GCMetadataPrinter &); GCMetadataPrinter &
operator=(const GCMetadataPrinter &) LLVM_DELETED_FUNCTION;
public: public:
GCStrategy &getStrategy() { return *S; } GCStrategy &getStrategy() { return *S; }
const Module &getModule() const { return S->getModule(); } const Module &getModule() const { return S->getModule(); }
/// begin/end - Iterate over the collected function metadata. /// begin/end - Iterate over the collected function metadata.
iterator begin() { return S->begin(); } iterator begin() { return S->begin(); }
iterator end() { return S->end(); } iterator end() { return S->end(); }
/// beginAssembly/finishAssembly - Emit module metadata as assembly cod e. /// beginAssembly/finishAssembly - Emit module metadata as assembly cod e.
 End of changes. 1 change blocks. 
3 lines changed or deleted 4 lines changed or added


 GCOV.h   GCOV.h 
skipping to change at line 30 skipping to change at line 30
#include "llvm/Support/MemoryBuffer.h" #include "llvm/Support/MemoryBuffer.h"
#include "llvm/Support/raw_ostream.h" #include "llvm/Support/raw_ostream.h"
namespace llvm { namespace llvm {
class GCOVFunction; class GCOVFunction;
class GCOVBlock; class GCOVBlock;
class GCOVLines; class GCOVLines;
class FileInfo; class FileInfo;
enum GCOVFormat { namespace GCOV {
InvalidGCOV, enum GCOVFormat {
GCNO_402, InvalidGCOV,
GCNO_404, GCNO_402,
GCDA_402, GCNO_404,
GCDA_404 GCDA_402,
}; GCDA_404
};
} // end GCOV namespace
/// GCOVBuffer - A wrapper around MemoryBuffer to provide GCOV specific /// GCOVBuffer - A wrapper around MemoryBuffer to provide GCOV specific
/// read operations. /// read operations.
class GCOVBuffer { class GCOVBuffer {
public: public:
GCOVBuffer(MemoryBuffer *B) : Buffer(B), Cursor(0) {} GCOVBuffer(MemoryBuffer *B) : Buffer(B), Cursor(0) {}
/// readGCOVFormat - Read GCOV signature at the beginning of buffer. /// readGCOVFormat - Read GCOV signature at the beginning of buffer.
enum GCOVFormat readGCOVFormat() { GCOV::GCOVFormat readGCOVFormat() {
StringRef Magic = Buffer->getBuffer().slice(0, 12); StringRef Magic = Buffer->getBuffer().slice(0, 12);
Cursor = 12; Cursor = 12;
if (Magic == "oncg*404MVLL") if (Magic == "oncg*404MVLL")
return GCNO_404; return GCOV::GCNO_404;
else if (Magic == "oncg*204MVLL") else if (Magic == "oncg*204MVLL")
return GCNO_402; return GCOV::GCNO_402;
else if (Magic == "adcg*404MVLL") else if (Magic == "adcg*404MVLL")
return GCDA_404; return GCOV::GCDA_404;
else if (Magic == "adcg*204MVLL") else if (Magic == "adcg*204MVLL")
return GCDA_402; return GCOV::GCDA_402;
Cursor = 0; Cursor = 0;
return InvalidGCOV; return GCOV::InvalidGCOV;
} }
/// readFunctionTag - If cursor points to a function tag then increment t he /// readFunctionTag - If cursor points to a function tag then increment t he
/// cursor and return true otherwise return false. /// cursor and return true otherwise return false.
bool readFunctionTag() { bool readFunctionTag() {
StringRef Tag = Buffer->getBuffer().slice(Cursor, Cursor+4); StringRef Tag = Buffer->getBuffer().slice(Cursor, Cursor+4);
if (Tag.empty() || if (Tag.empty() ||
Tag[0] != '\0' || Tag[1] != '\0' || Tag[0] != '\0' || Tag[1] != '\0' ||
Tag[2] != '\0' || Tag[3] != '\1') { Tag[2] != '\0' || Tag[3] != '\1') {
return false; return false;
} }
Cursor += 4; Cursor += 4;
return true; return true;
} }
/// readBlockTag - If cursor points to a block tag then increment the /// readBlockTag - If cursor points to a block tag then increment the
/// cursor and return true otherwise return false. /// cursor and return true otherwise return false.
bool readBlockTag() { bool readBlockTag() {
StringRef Tag = Buffer->getBuffer().slice(Cursor, Cursor+4); StringRef Tag = Buffer->getBuffer().slice(Cursor, Cursor+4);
if (Tag.empty() || if (Tag.empty() ||
Tag[0] != '\0' || Tag[1] != '\0' || Tag[0] != '\0' || Tag[1] != '\0' ||
Tag[2] != '\x41' || Tag[3] != '\x01') { Tag[2] != '\x41' || Tag[3] != '\x01') {
return false; return false;
} }
Cursor += 4; Cursor += 4;
return true; return true;
} }
/// readEdgeTag - If cursor points to an edge tag then increment the /// readEdgeTag - If cursor points to an edge tag then increment the
/// cursor and return true otherwise return false. /// cursor and return true otherwise return false.
bool readEdgeTag() { bool readEdgeTag() {
StringRef Tag = Buffer->getBuffer().slice(Cursor, Cursor+4); StringRef Tag = Buffer->getBuffer().slice(Cursor, Cursor+4);
if (Tag.empty() || if (Tag.empty() ||
Tag[0] != '\0' || Tag[1] != '\0' || Tag[0] != '\0' || Tag[1] != '\0' ||
Tag[2] != '\x43' || Tag[3] != '\x01') { Tag[2] != '\x43' || Tag[3] != '\x01') {
return false; return false;
} }
Cursor += 4; Cursor += 4;
return true; return true;
} }
/// readLineTag - If cursor points to a line tag then increment the /// readLineTag - If cursor points to a line tag then increment the
/// cursor and return true otherwise return false. /// cursor and return true otherwise return false.
bool readLineTag() { bool readLineTag() {
StringRef Tag = Buffer->getBuffer().slice(Cursor, Cursor+4); StringRef Tag = Buffer->getBuffer().slice(Cursor, Cursor+4);
if (Tag.empty() || if (Tag.empty() ||
Tag[0] != '\0' || Tag[1] != '\0' || Tag[0] != '\0' || Tag[1] != '\0' ||
Tag[2] != '\x45' || Tag[3] != '\x01') { Tag[2] != '\x45' || Tag[3] != '\x01') {
return false; return false;
} }
Cursor += 4; Cursor += 4;
return true; return true;
} }
/// readArcTag - If cursor points to an gcda arc tag then increment the /// readArcTag - If cursor points to an gcda arc tag then increment the
/// cursor and return true otherwise return false. /// cursor and return true otherwise return false.
bool readArcTag() { bool readArcTag() {
StringRef Tag = Buffer->getBuffer().slice(Cursor, Cursor+4); StringRef Tag = Buffer->getBuffer().slice(Cursor, Cursor+4);
if (Tag.empty() || if (Tag.empty() ||
Tag[0] != '\0' || Tag[1] != '\0' || Tag[0] != '\0' || Tag[1] != '\0' ||
Tag[2] != '\xa1' || Tag[3] != '\1') { Tag[2] != '\xa1' || Tag[3] != '\1') {
return false; return false;
} }
Cursor += 4; Cursor += 4;
return true; return true;
} }
uint32_t readInt() { uint32_t readInt() {
uint32_t Result; uint32_t Result;
StringRef Str = Buffer->getBuffer().slice(Cursor, Cursor+4); StringRef Str = Buffer->getBuffer().slice(Cursor, Cursor+4);
assert (Str.empty() == false && "Unexpected memory buffer end!"); assert (Str.empty() == false && "Unexpected memory buffer end!");
Cursor += 4; Cursor += 4;
Result = *(uint32_t *)(Str.data()); Result = *(const uint32_t *)(Str.data());
return Result; return Result;
} }
uint64_t readInt64() { uint64_t readInt64() {
uint64_t Lo = readInt(); uint64_t Lo = readInt();
uint64_t Hi = readInt(); uint64_t Hi = readInt();
uint64_t Result = Lo | (Hi << 32); uint64_t Result = Lo | (Hi << 32);
return Result; return Result;
} }
skipping to change at line 173 skipping to change at line 175
void collectLineCounts(FileInfo &FI); void collectLineCounts(FileInfo &FI);
private: private:
SmallVector<GCOVFunction *, 16> Functions; SmallVector<GCOVFunction *, 16> Functions;
}; };
/// GCOVFunction - Collects function information. /// GCOVFunction - Collects function information.
class GCOVFunction { class GCOVFunction {
public: public:
GCOVFunction() : Ident(0), LineNumber(0) {} GCOVFunction() : Ident(0), LineNumber(0) {}
~GCOVFunction(); ~GCOVFunction();
bool read(GCOVBuffer &Buffer, GCOVFormat Format); bool read(GCOVBuffer &Buffer, GCOV::GCOVFormat Format);
void dump(); void dump();
void collectLineCounts(FileInfo &FI); void collectLineCounts(FileInfo &FI);
private: private:
uint32_t Ident; uint32_t Ident;
uint32_t LineNumber; uint32_t LineNumber;
StringRef Name; StringRef Name;
StringRef Filename; StringRef Filename;
SmallVector<GCOVBlock *, 16> Blocks; SmallVector<GCOVBlock *, 16> Blocks;
}; };
 End of changes. 14 change blocks. 
25 lines changed or deleted 27 lines changed or added


 GCStrategy.h   GCStrategy.h 
skipping to change at line 68 skipping to change at line 68
typedef list_type::iterator iterator; typedef list_type::iterator iterator;
private: private:
friend class GCModuleInfo; friend class GCModuleInfo;
const Module *M; const Module *M;
std::string Name; std::string Name;
list_type Functions; list_type Functions;
protected: protected:
unsigned NeededSafePoints; //< Bitmask of required safe points. unsigned NeededSafePoints; ///< Bitmask of required safe points.
bool CustomReadBarriers; //< Default is to insert loads. bool CustomReadBarriers; ///< Default is to insert loads.
bool CustomWriteBarriers; //< Default is to insert stores. bool CustomWriteBarriers; ///< Default is to insert stores.
bool CustomRoots; //< Default is to pass through to backend. bool CustomRoots; ///< Default is to pass through to backend.
bool CustomSafePoints; //< Default is to use NeededSafePoints bool CustomSafePoints; ///< Default is to use NeededSafePoints
// to find safe points. ///< to find safe points.
bool InitRoots; //< If set, roots are nulled during lowering bool InitRoots; ///< If set, roots are nulled during lowerin
. g.
bool UsesMetadata; //< If set, backend must emit metadata table bool UsesMetadata; ///< If set, backend must emit metadata tabl
s. es.
public: public:
GCStrategy(); GCStrategy();
virtual ~GCStrategy(); virtual ~GCStrategy();
/// getName - The name of the GC strategy, for debugging. /// getName - The name of the GC strategy, for debugging.
/// ///
const std::string &getName() const { return Name; } const std::string &getName() const { return Name; }
 End of changes. 1 change blocks. 
10 lines changed or deleted 10 lines changed or added


 GlobalAlias.h   GlobalAlias.h 
skipping to change at line 31 skipping to change at line 31
#include "llvm/ADT/Twine.h" #include "llvm/ADT/Twine.h"
namespace llvm { namespace llvm {
class Module; class Module;
template<typename ValueSubClass, typename ItemParentClass> template<typename ValueSubClass, typename ItemParentClass>
class SymbolTableListTraits; class SymbolTableListTraits;
class GlobalAlias : public GlobalValue, public ilist_node<GlobalAlias> { class GlobalAlias : public GlobalValue, public ilist_node<GlobalAlias> {
friend class SymbolTableListTraits<GlobalAlias, Module>; friend class SymbolTableListTraits<GlobalAlias, Module>;
void operator=(const GlobalAlias &); // Do not implement void operator=(const GlobalAlias &) LLVM_DELETED_FUNCTION;
GlobalAlias(const GlobalAlias &); // Do not implement GlobalAlias(const GlobalAlias &) LLVM_DELETED_FUNCTION;
void setParent(Module *parent); void setParent(Module *parent);
public: public:
// allocate space for exactly one operand // allocate space for exactly one operand
void *operator new(size_t s) { void *operator new(size_t s) {
return User::operator new(s, 1); return User::operator new(s, 1);
} }
/// GlobalAlias ctor - If a parent module is specified, the alias is /// GlobalAlias ctor - If a parent module is specified, the alias is
/// automatically inserted into the end of the specified module's alias l ist. /// automatically inserted into the end of the specified module's alias l ist.
skipping to change at line 79 skipping to change at line 79
const GlobalValue *getAliasedGlobal() const; const GlobalValue *getAliasedGlobal() const;
/// resolveAliasedGlobal() - This method tries to ultimately resolve the alias /// resolveAliasedGlobal() - This method tries to ultimately resolve the alias
/// by going through the aliasing chain and trying to find the very last /// by going through the aliasing chain and trying to find the very last
/// global. Returns NULL if a cycle was found. If stopOnWeak is false, th en /// global. Returns NULL if a cycle was found. If stopOnWeak is false, th en
/// the whole chain aliasing chain is traversed, otherwise - only strong /// the whole chain aliasing chain is traversed, otherwise - only strong
/// aliases. /// aliases.
const GlobalValue *resolveAliasedGlobal(bool stopOnWeak = true) const; const GlobalValue *resolveAliasedGlobal(bool stopOnWeak = true) const;
// Methods for support type inquiry through isa, cast, and dyn_cast: // Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const GlobalAlias *) { return true; }
static inline bool classof(const Value *V) { static inline bool classof(const Value *V) {
return V->getValueID() == Value::GlobalAliasVal; return V->getValueID() == Value::GlobalAliasVal;
} }
}; };
template <> template <>
struct OperandTraits<GlobalAlias> : struct OperandTraits<GlobalAlias> :
public FixedNumOperandTraits<GlobalAlias, 1> { public FixedNumOperandTraits<GlobalAlias, 1> {
}; };
 End of changes. 2 change blocks. 
3 lines changed or deleted 2 lines changed or added


 GlobalValue.h   GlobalValue.h 
skipping to change at line 29 skipping to change at line 29
#define LLVM_GLOBALVALUE_H #define LLVM_GLOBALVALUE_H
#include "llvm/Constant.h" #include "llvm/Constant.h"
namespace llvm { namespace llvm {
class PointerType; class PointerType;
class Module; class Module;
class GlobalValue : public Constant { class GlobalValue : public Constant {
GlobalValue(const GlobalValue &); // do not implement GlobalValue(const GlobalValue &) LLVM_DELETED_FUNCTION;
public: public:
/// @brief An enumeration for the kinds of linkage for global values. /// @brief An enumeration for the kinds of linkage for global values.
enum LinkageTypes { enum LinkageTypes {
ExternalLinkage = 0,///< Externally visible function ExternalLinkage = 0,///< Externally visible function
AvailableExternallyLinkage, ///< Available for inspection, not emission . AvailableExternallyLinkage, ///< Available for inspection, not emission .
LinkOnceAnyLinkage, ///< Keep one copy of function when linking (inline ) LinkOnceAnyLinkage, ///< Keep one copy of function when linking (inline )
LinkOnceODRLinkage, ///< Same, but only replaced by something equivalen t. LinkOnceODRLinkage, ///< Same, but only replaced by something equivalen t.
LinkOnceODRAutoHideLinkage, ///< Like LinkOnceODRLinkage but addr not t aken.
WeakAnyLinkage, ///< Keep one copy of named function when linking ( weak) WeakAnyLinkage, ///< Keep one copy of named function when linking ( weak)
WeakODRLinkage, ///< Same, but only replaced by something equivalen t. WeakODRLinkage, ///< Same, but only replaced by something equivalen t.
AppendingLinkage, ///< Special purpose, only applies to global arrays AppendingLinkage, ///< Special purpose, only applies to global arrays
InternalLinkage, ///< Rename collisions when linking (static functio ns). InternalLinkage, ///< Rename collisions when linking (static functio ns).
PrivateLinkage, ///< Like Internal, but omit from symbol table. PrivateLinkage, ///< Like Internal, but omit from symbol table.
LinkerPrivateLinkage, ///< Like Private, but linker removes. LinkerPrivateLinkage, ///< Like Private, but linker removes.
LinkerPrivateWeakLinkage, ///< Like LinkerPrivate, but weak. LinkerPrivateWeakLinkage, ///< Like LinkerPrivate, but weak.
LinkerPrivateWeakDefAutoLinkage, ///< Like LinkerPrivateWeak, but possi
bly
/// hidden.
DLLImportLinkage, ///< Function to be imported from DLL DLLImportLinkage, ///< Function to be imported from DLL
DLLExportLinkage, ///< Function to be accessible from DLL. DLLExportLinkage, ///< Function to be accessible from DLL.
ExternalWeakLinkage,///< ExternalWeak linkage description. ExternalWeakLinkage,///< ExternalWeak linkage description.
CommonLinkage ///< Tentative definitions. CommonLinkage ///< Tentative definitions.
}; };
/// @brief An enumeration for the kinds of visibility of global values. /// @brief An enumeration for the kinds of visibility of global values.
enum VisibilityTypes { enum VisibilityTypes {
DefaultVisibility = 0, ///< The GV is visible DefaultVisibility = 0, ///< The GV is visible
HiddenVisibility, ///< The GV is hidden HiddenVisibility, ///< The GV is hidden
skipping to change at line 126 skipping to change at line 125
return ODR ? WeakODRLinkage : WeakAnyLinkage; return ODR ? WeakODRLinkage : WeakAnyLinkage;
} }
static bool isExternalLinkage(LinkageTypes Linkage) { static bool isExternalLinkage(LinkageTypes Linkage) {
return Linkage == ExternalLinkage; return Linkage == ExternalLinkage;
} }
static bool isAvailableExternallyLinkage(LinkageTypes Linkage) { static bool isAvailableExternallyLinkage(LinkageTypes Linkage) {
return Linkage == AvailableExternallyLinkage; return Linkage == AvailableExternallyLinkage;
} }
static bool isLinkOnceLinkage(LinkageTypes Linkage) { static bool isLinkOnceLinkage(LinkageTypes Linkage) {
return Linkage == LinkOnceAnyLinkage || Linkage == LinkOnceODRLinkage; return Linkage == LinkOnceAnyLinkage ||
Linkage == LinkOnceODRLinkage ||
Linkage == LinkOnceODRAutoHideLinkage;
}
static bool isLinkOnceODRAutoHideLinkage(LinkageTypes Linkage) {
return Linkage == LinkOnceODRAutoHideLinkage;
} }
static bool isWeakLinkage(LinkageTypes Linkage) { static bool isWeakLinkage(LinkageTypes Linkage) {
return Linkage == WeakAnyLinkage || Linkage == WeakODRLinkage; return Linkage == WeakAnyLinkage || Linkage == WeakODRLinkage;
} }
static bool isAppendingLinkage(LinkageTypes Linkage) { static bool isAppendingLinkage(LinkageTypes Linkage) {
return Linkage == AppendingLinkage; return Linkage == AppendingLinkage;
} }
static bool isInternalLinkage(LinkageTypes Linkage) { static bool isInternalLinkage(LinkageTypes Linkage) {
return Linkage == InternalLinkage; return Linkage == InternalLinkage;
} }
static bool isPrivateLinkage(LinkageTypes Linkage) { static bool isPrivateLinkage(LinkageTypes Linkage) {
return Linkage == PrivateLinkage; return Linkage == PrivateLinkage;
} }
static bool isLinkerPrivateLinkage(LinkageTypes Linkage) { static bool isLinkerPrivateLinkage(LinkageTypes Linkage) {
return Linkage == LinkerPrivateLinkage; return Linkage == LinkerPrivateLinkage;
} }
static bool isLinkerPrivateWeakLinkage(LinkageTypes Linkage) { static bool isLinkerPrivateWeakLinkage(LinkageTypes Linkage) {
return Linkage == LinkerPrivateWeakLinkage; return Linkage == LinkerPrivateWeakLinkage;
} }
static bool isLinkerPrivateWeakDefAutoLinkage(LinkageTypes Linkage) {
return Linkage == LinkerPrivateWeakDefAutoLinkage;
}
static bool isLocalLinkage(LinkageTypes Linkage) { static bool isLocalLinkage(LinkageTypes Linkage) {
return isInternalLinkage(Linkage) || isPrivateLinkage(Linkage) || return isInternalLinkage(Linkage) || isPrivateLinkage(Linkage) ||
isLinkerPrivateLinkage(Linkage) || isLinkerPrivateWeakLinkage(Linkage isLinkerPrivateLinkage(Linkage) || isLinkerPrivateWeakLinkage(Linkage
) || );
isLinkerPrivateWeakDefAutoLinkage(Linkage);
} }
static bool isDLLImportLinkage(LinkageTypes Linkage) { static bool isDLLImportLinkage(LinkageTypes Linkage) {
return Linkage == DLLImportLinkage; return Linkage == DLLImportLinkage;
} }
static bool isDLLExportLinkage(LinkageTypes Linkage) { static bool isDLLExportLinkage(LinkageTypes Linkage) {
return Linkage == DLLExportLinkage; return Linkage == DLLExportLinkage;
} }
static bool isExternalWeakLinkage(LinkageTypes Linkage) { static bool isExternalWeakLinkage(LinkageTypes Linkage) {
return Linkage == ExternalWeakLinkage; return Linkage == ExternalWeakLinkage;
} }
static bool isCommonLinkage(LinkageTypes Linkage) { static bool isCommonLinkage(LinkageTypes Linkage) {
return Linkage == CommonLinkage; return Linkage == CommonLinkage;
} }
/// isDiscardableIfUnused - Whether the definition of this global may be
/// discarded if it is not used in its compilation unit.
static bool isDiscardableIfUnused(LinkageTypes Linkage) {
return isLinkOnceLinkage(Linkage) || isLocalLinkage(Linkage);
}
/// mayBeOverridden - Whether the definition of this global may be replac ed /// mayBeOverridden - Whether the definition of this global may be replac ed
/// by something non-equivalent at link time. For example, if a function has /// by something non-equivalent at link time. For example, if a function has
/// weak linkage then the code defining it may be replaced by different c ode. /// weak linkage then the code defining it may be replaced by different c ode.
static bool mayBeOverridden(LinkageTypes Linkage) { static bool mayBeOverridden(LinkageTypes Linkage) {
return Linkage == WeakAnyLinkage || return Linkage == WeakAnyLinkage ||
Linkage == LinkOnceAnyLinkage || Linkage == LinkOnceAnyLinkage ||
Linkage == CommonLinkage || Linkage == CommonLinkage ||
Linkage == ExternalWeakLinkage || Linkage == ExternalWeakLinkage ||
Linkage == LinkerPrivateWeakLinkage || Linkage == LinkerPrivateWeakLinkage;
Linkage == LinkerPrivateWeakDefAutoLinkage;
} }
/// isWeakForLinker - Whether the definition of this global may be replac ed at /// isWeakForLinker - Whether the definition of this global may be replac ed at
/// link time. NB: Using this method outside of the code generators is a lmost /// link time. NB: Using this method outside of the code generators is a lmost
/// always a mistake: when working at the IR level use mayBeOverridden in stead /// always a mistake: when working at the IR level use mayBeOverridden in stead
/// as it knows about ODR semantics. /// as it knows about ODR semantics.
static bool isWeakForLinker(LinkageTypes Linkage) { static bool isWeakForLinker(LinkageTypes Linkage) {
return Linkage == AvailableExternallyLinkage || return Linkage == AvailableExternallyLinkage ||
Linkage == WeakAnyLinkage || Linkage == WeakAnyLinkage ||
Linkage == WeakODRLinkage || Linkage == WeakODRLinkage ||
Linkage == LinkOnceAnyLinkage || Linkage == LinkOnceAnyLinkage ||
Linkage == LinkOnceODRLinkage || Linkage == LinkOnceODRLinkage ||
Linkage == LinkOnceODRAutoHideLinkage ||
Linkage == CommonLinkage || Linkage == CommonLinkage ||
Linkage == ExternalWeakLinkage || Linkage == ExternalWeakLinkage ||
Linkage == LinkerPrivateWeakLinkage || Linkage == LinkerPrivateWeakLinkage;
Linkage == LinkerPrivateWeakDefAutoLinkage;
} }
bool hasExternalLinkage() const { return isExternalLinkage(Linkage); } bool hasExternalLinkage() const { return isExternalLinkage(Linkage); }
bool hasAvailableExternallyLinkage() const { bool hasAvailableExternallyLinkage() const {
return isAvailableExternallyLinkage(Linkage); return isAvailableExternallyLinkage(Linkage);
} }
bool hasLinkOnceLinkage() const { bool hasLinkOnceLinkage() const {
return isLinkOnceLinkage(Linkage); return isLinkOnceLinkage(Linkage);
} }
bool hasLinkOnceODRAutoHideLinkage() const {
return isLinkOnceODRAutoHideLinkage(Linkage);
}
bool hasWeakLinkage() const { bool hasWeakLinkage() const {
return isWeakLinkage(Linkage); return isWeakLinkage(Linkage);
} }
bool hasAppendingLinkage() const { return isAppendingLinkage(Linkage); } bool hasAppendingLinkage() const { return isAppendingLinkage(Linkage); }
bool hasInternalLinkage() const { return isInternalLinkage(Linkage); } bool hasInternalLinkage() const { return isInternalLinkage(Linkage); }
bool hasPrivateLinkage() const { return isPrivateLinkage(Linkage); } bool hasPrivateLinkage() const { return isPrivateLinkage(Linkage); }
bool hasLinkerPrivateLinkage() const { return isLinkerPrivateLinkage(Link age); } bool hasLinkerPrivateLinkage() const { return isLinkerPrivateLinkage(Link age); }
bool hasLinkerPrivateWeakLinkage() const { bool hasLinkerPrivateWeakLinkage() const {
return isLinkerPrivateWeakLinkage(Linkage); return isLinkerPrivateWeakLinkage(Linkage);
} }
bool hasLinkerPrivateWeakDefAutoLinkage() const {
return isLinkerPrivateWeakDefAutoLinkage(Linkage);
}
bool hasLocalLinkage() const { return isLocalLinkage(Linkage); } bool hasLocalLinkage() const { return isLocalLinkage(Linkage); }
bool hasDLLImportLinkage() const { return isDLLImportLinkage(Linkage); } bool hasDLLImportLinkage() const { return isDLLImportLinkage(Linkage); }
bool hasDLLExportLinkage() const { return isDLLExportLinkage(Linkage); } bool hasDLLExportLinkage() const { return isDLLExportLinkage(Linkage); }
bool hasExternalWeakLinkage() const { return isExternalWeakLinkage(Linkag e); } bool hasExternalWeakLinkage() const { return isExternalWeakLinkage(Linkag e); }
bool hasCommonLinkage() const { return isCommonLinkage(Linkage); } bool hasCommonLinkage() const { return isCommonLinkage(Linkage); }
void setLinkage(LinkageTypes LT) { Linkage = LT; } void setLinkage(LinkageTypes LT) { Linkage = LT; }
LinkageTypes getLinkage() const { return Linkage; } LinkageTypes getLinkage() const { return Linkage; }
bool isDiscardableIfUnused() const {
return isDiscardableIfUnused(Linkage);
}
bool mayBeOverridden() const { return mayBeOverridden(Linkage); } bool mayBeOverridden() const { return mayBeOverridden(Linkage); }
bool isWeakForLinker() const { return isWeakForLinker(Linkage); } bool isWeakForLinker() const { return isWeakForLinker(Linkage); }
/// copyAttributesFrom - copy all additional attributes (those not needed to /// copyAttributesFrom - copy all additional attributes (those not needed to
/// create a GlobalValue) from the GlobalValue Src to this one. /// create a GlobalValue) from the GlobalValue Src to this one.
virtual void copyAttributesFrom(const GlobalValue *Src); virtual void copyAttributesFrom(const GlobalValue *Src);
/// @name Materialization /// @name Materialization
/// Materialization is used to construct functions only as they're needed. This /// Materialization is used to construct functions only as they're needed. This
skipping to change at line 281 skipping to change at line 290
/// eraseFromParent - This method unlinks 'this' from the containing modu le /// eraseFromParent - This method unlinks 'this' from the containing modu le
/// and deletes it. /// and deletes it.
virtual void eraseFromParent() = 0; virtual void eraseFromParent() = 0;
/// getParent - Get the module that this global value is contained inside /// getParent - Get the module that this global value is contained inside
/// of... /// of...
inline Module *getParent() { return Parent; } inline Module *getParent() { return Parent; }
inline const Module *getParent() const { return Parent; } inline const Module *getParent() const { return Parent; }
// Methods for support type inquiry through isa, cast, and dyn_cast: // Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const GlobalValue *) { return true; }
static inline bool classof(const Value *V) { static inline bool classof(const Value *V) {
return V->getValueID() == Value::FunctionVal || return V->getValueID() == Value::FunctionVal ||
V->getValueID() == Value::GlobalVariableVal || V->getValueID() == Value::GlobalVariableVal ||
V->getValueID() == Value::GlobalAliasVal; V->getValueID() == Value::GlobalAliasVal;
} }
}; };
} // End llvm namespace } // End llvm namespace
#endif #endif
 End of changes. 14 change blocks. 
19 lines changed or deleted 26 lines changed or added


 GlobalVariable.h   GlobalVariable.h 
skipping to change at line 37 skipping to change at line 37
namespace llvm { namespace llvm {
class Module; class Module;
class Constant; class Constant;
template<typename ValueSubClass, typename ItemParentClass> template<typename ValueSubClass, typename ItemParentClass>
class SymbolTableListTraits; class SymbolTableListTraits;
class GlobalVariable : public GlobalValue, public ilist_node<GlobalVariable > { class GlobalVariable : public GlobalValue, public ilist_node<GlobalVariable > {
friend class SymbolTableListTraits<GlobalVariable, Module>; friend class SymbolTableListTraits<GlobalVariable, Module>;
void *operator new(size_t, unsigned); // Do not implement void *operator new(size_t, unsigned) LLVM_DELETED_FUNCTION;
void operator=(const GlobalVariable &); // Do not implement void operator=(const GlobalVariable &) LLVM_DELETED_FUNCTION;
GlobalVariable(const GlobalVariable &); // Do not implement GlobalVariable(const GlobalVariable &) LLVM_DELETED_FUNCTION;
void setParent(Module *parent); void setParent(Module *parent);
bool isConstantGlobal : 1; // Is this a global constant? bool isConstantGlobal : 1; // Is this a global constant?
bool isThreadLocalSymbol : 1; // Is this symbol "Thread Local"? unsigned threadLocalMode : 3; // Is this symbol "Thread Local",
// if so, what is the desired model?
public: public:
// allocate space for exactly one operand // allocate space for exactly one operand
void *operator new(size_t s) { void *operator new(size_t s) {
return User::operator new(s, 1); return User::operator new(s, 1);
} }
enum ThreadLocalMode {
NotThreadLocal = 0,
GeneralDynamicTLSModel,
LocalDynamicTLSModel,
InitialExecTLSModel,
LocalExecTLSModel
};
/// GlobalVariable ctor - If a parent module is specified, the global is /// GlobalVariable ctor - If a parent module is specified, the global is
/// automatically inserted into the end of the specified modules global l ist. /// automatically inserted into the end of the specified modules global l ist.
GlobalVariable(Type *Ty, bool isConstant, LinkageTypes Linkage, GlobalVariable(Type *Ty, bool isConstant, LinkageTypes Linkage,
Constant *Initializer = 0, const Twine &Name = "", Constant *Initializer = 0, const Twine &Name = "",
bool ThreadLocal = false, unsigned AddressSpace = 0); ThreadLocalMode = NotThreadLocal, unsigned AddressSpace = 0);
/// GlobalVariable ctor - This creates a global and inserts it before the /// GlobalVariable ctor - This creates a global and inserts it before the
/// specified other global. /// specified other global.
GlobalVariable(Module &M, Type *Ty, bool isConstant, GlobalVariable(Module &M, Type *Ty, bool isConstant,
LinkageTypes Linkage, Constant *Initializer, LinkageTypes Linkage, Constant *Initializer,
const Twine &Name, const Twine &Name = "",
GlobalVariable *InsertBefore = 0, bool ThreadLocal = false GlobalVariable *InsertBefore = 0,
, ThreadLocalMode = NotThreadLocal,
unsigned AddressSpace = 0); unsigned AddressSpace = 0);
~GlobalVariable() { ~GlobalVariable() {
NumOperands = 1; // FIXME: needed by operator delete NumOperands = 1; // FIXME: needed by operator delete
} }
/// Provide fast operand accessors /// Provide fast operand accessors
DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value); DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value);
/// hasInitializer - Unless a global variable isExternal(), it has an /// hasInitializer - Unless a global variable isExternal(), it has an
skipping to change at line 138 skipping to change at line 149
void setInitializer(Constant *InitVal); void setInitializer(Constant *InitVal);
/// If the value is a global constant, its value is immutable throughout the /// If the value is a global constant, its value is immutable throughout the
/// runtime execution of the program. Assigning a value into the constan t /// runtime execution of the program. Assigning a value into the constan t
/// leads to undefined behavior. /// leads to undefined behavior.
/// ///
bool isConstant() const { return isConstantGlobal; } bool isConstant() const { return isConstantGlobal; }
void setConstant(bool Val) { isConstantGlobal = Val; } void setConstant(bool Val) { isConstantGlobal = Val; }
/// If the value is "Thread Local", its value isn't shared by the threads . /// If the value is "Thread Local", its value isn't shared by the threads .
bool isThreadLocal() const { return isThreadLocalSymbol; } bool isThreadLocal() const { return threadLocalMode != NotThreadLocal; }
void setThreadLocal(bool Val) { isThreadLocalSymbol = Val; } void setThreadLocal(bool Val) {
threadLocalMode = Val ? GeneralDynamicTLSModel : NotThreadLocal;
}
void setThreadLocalMode(ThreadLocalMode Val) { threadLocalMode = Val; }
ThreadLocalMode getThreadLocalMode() const {
return static_cast<ThreadLocalMode>(threadLocalMode);
}
/// copyAttributesFrom - copy all additional attributes (those not needed to /// copyAttributesFrom - copy all additional attributes (those not needed to
/// create a GlobalVariable) from the GlobalVariable Src to this one. /// create a GlobalVariable) from the GlobalVariable Src to this one.
void copyAttributesFrom(const GlobalValue *Src); void copyAttributesFrom(const GlobalValue *Src);
/// removeFromParent - This method unlinks 'this' from the containing mod ule, /// removeFromParent - This method unlinks 'this' from the containing mod ule,
/// but does not delete it. /// but does not delete it.
/// ///
virtual void removeFromParent(); virtual void removeFromParent();
/// eraseFromParent - This method unlinks 'this' from the containing modu le /// eraseFromParent - This method unlinks 'this' from the containing modu le
/// and deletes it. /// and deletes it.
/// ///
virtual void eraseFromParent(); virtual void eraseFromParent();
/// Override Constant's implementation of this method so we can /// Override Constant's implementation of this method so we can
/// replace constant initializers. /// replace constant initializers.
virtual void replaceUsesOfWithOnConstant(Value *From, Value *To, Use *U); virtual void replaceUsesOfWithOnConstant(Value *From, Value *To, Use *U);
// Methods for support type inquiry through isa, cast, and dyn_cast: // Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const GlobalVariable *) { return true; }
static inline bool classof(const Value *V) { static inline bool classof(const Value *V) {
return V->getValueID() == Value::GlobalVariableVal; return V->getValueID() == Value::GlobalVariableVal;
} }
}; };
template <> template <>
struct OperandTraits<GlobalVariable> : struct OperandTraits<GlobalVariable> :
public OptionalOperandTraits<GlobalVariable> { public OptionalOperandTraits<GlobalVariable> {
}; };
 End of changes. 7 change blocks. 
11 lines changed or deleted 26 lines changed or added


 Graph.h   Graph.h 
skipping to change at line 21 skipping to change at line 21
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_CODEGEN_PBQP_GRAPH_H #ifndef LLVM_CODEGEN_PBQP_GRAPH_H
#define LLVM_CODEGEN_PBQP_GRAPH_H #define LLVM_CODEGEN_PBQP_GRAPH_H
#include "Math.h" #include "Math.h"
#include <list> #include <list>
#include <map> #include <map>
#include <llvm/ADT/ilist.h>
namespace PBQP { namespace PBQP {
/// PBQP Graph class. /// PBQP Graph class.
/// Instances of this class describe PBQP problems. /// Instances of this class describe PBQP problems.
class Graph { class Graph {
private: private:
// ----- TYPEDEFS ----- // ----- TYPEDEFS -----
class NodeEntry; class NodeEntry;
class EdgeEntry; class EdgeEntry;
typedef std::list<NodeEntry> NodeList; typedef llvm::ilist<NodeEntry> NodeList;
typedef std::list<EdgeEntry> EdgeList; typedef llvm::ilist<EdgeEntry> EdgeList;
public: public:
typedef NodeList::iterator NodeItr; typedef NodeEntry* NodeItr;
typedef NodeList::const_iterator ConstNodeItr; typedef const NodeEntry* ConstNodeItr;
typedef EdgeList::iterator EdgeItr; typedef EdgeEntry* EdgeItr;
typedef EdgeList::const_iterator ConstEdgeItr; typedef const EdgeEntry* ConstEdgeItr;
private: private:
typedef std::list<EdgeItr> AdjEdgeList; typedef std::list<EdgeItr> AdjEdgeList;
public: public:
typedef AdjEdgeList::iterator AdjEdgeItr; typedef AdjEdgeList::iterator AdjEdgeItr;
private: private:
class NodeEntry { class NodeEntry : public llvm::ilist_node<NodeEntry> {
friend struct llvm::ilist_sentinel_traits<NodeEntry>;
private: private:
Vector costs; Vector costs;
AdjEdgeList adjEdges; AdjEdgeList adjEdges;
unsigned degree; unsigned degree;
void *data; void *data;
NodeEntry() : costs(0, 0) {}
public: public:
NodeEntry(const Vector &costs) : costs(costs), degree(0) {} NodeEntry(const Vector &costs) : costs(costs), degree(0) {}
Vector& getCosts() { return costs; } Vector& getCosts() { return costs; }
const Vector& getCosts() const { return costs; } const Vector& getCosts() const { return costs; }
unsigned getDegree() const { return degree; } unsigned getDegree() const { return degree; }
AdjEdgeItr edgesBegin() { return adjEdges.begin(); } AdjEdgeItr edgesBegin() { return adjEdges.begin(); }
AdjEdgeItr edgesEnd() { return adjEdges.end(); } AdjEdgeItr edgesEnd() { return adjEdges.end(); }
AdjEdgeItr addEdge(EdgeItr e) { AdjEdgeItr addEdge(EdgeItr e) {
++degree; ++degree;
return adjEdges.insert(adjEdges.end(), e); return adjEdges.insert(adjEdges.end(), e);
} }
void removeEdge(AdjEdgeItr ae) { void removeEdge(AdjEdgeItr ae) {
--degree; --degree;
adjEdges.erase(ae); adjEdges.erase(ae);
} }
void setData(void *data) { this->data = data; } void setData(void *data) { this->data = data; }
void* getData() { return data; } void* getData() { return data; }
}; };
class EdgeEntry { class EdgeEntry : public llvm::ilist_node<EdgeEntry> {
friend struct llvm::ilist_sentinel_traits<EdgeEntry>;
private: private:
NodeItr node1, node2; NodeItr node1, node2;
Matrix costs; Matrix costs;
AdjEdgeItr node1AEItr, node2AEItr; AdjEdgeItr node1AEItr, node2AEItr;
void *data; void *data;
EdgeEntry() : costs(0, 0, 0) {}
public: public:
EdgeEntry(NodeItr node1, NodeItr node2, const Matrix &costs) EdgeEntry(NodeItr node1, NodeItr node2, const Matrix &costs)
: node1(node1), node2(node2), costs(costs) {} : node1(node1), node2(node2), costs(costs) {}
NodeItr getNode1() const { return node1; } NodeItr getNode1() const { return node1; }
NodeItr getNode2() const { return node2; } NodeItr getNode2() const { return node2; }
Matrix& getCosts() { return costs; } Matrix& getCosts() { return costs; }
const Matrix& getCosts() const { return costs; } const Matrix& getCosts() const { return costs; }
void setNode1AEItr(AdjEdgeItr ae) { node1AEItr = ae; } void setNode1AEItr(AdjEdgeItr ae) { node1AEItr = ae; }
AdjEdgeItr getNode1AEItr() { return node1AEItr; } AdjEdgeItr getNode1AEItr() { return node1AEItr; }
void setNode2AEItr(AdjEdgeItr ae) { node2AEItr = ae; } void setNode2AEItr(AdjEdgeItr ae) { node2AEItr = ae; }
 End of changes. 8 change blocks. 
8 lines changed or deleted 13 lines changed or added


 GraphWriter.h   GraphWriter.h 
skipping to change at line 175 skipping to change at line 175
O << "\tNode" << static_cast<const void*>(Node) << " [shape=record,"; O << "\tNode" << static_cast<const void*>(Node) << " [shape=record,";
if (!NodeAttributes.empty()) O << NodeAttributes << ","; if (!NodeAttributes.empty()) O << NodeAttributes << ",";
O << "label=\"{"; O << "label=\"{";
if (!DTraits.renderGraphFromBottomUp()) { if (!DTraits.renderGraphFromBottomUp()) {
O << DOT::EscapeString(DTraits.getNodeLabel(Node, G)); O << DOT::EscapeString(DTraits.getNodeLabel(Node, G));
// If we should include the address of the node in the label, do so n ow. // If we should include the address of the node in the label, do so n ow.
if (DTraits.hasNodeAddressLabel(Node, G)) if (DTraits.hasNodeAddressLabel(Node, G))
O << "|" << (void*)Node; O << "|" << static_cast<const void*>(Node);
} }
std::string edgeSourceLabels; std::string edgeSourceLabels;
raw_string_ostream EdgeSourceLabels(edgeSourceLabels); raw_string_ostream EdgeSourceLabels(edgeSourceLabels);
bool hasEdgeSourceLabels = getEdgeSourceLabels(EdgeSourceLabels, Node); bool hasEdgeSourceLabels = getEdgeSourceLabels(EdgeSourceLabels, Node);
if (hasEdgeSourceLabels) { if (hasEdgeSourceLabels) {
if (!DTraits.renderGraphFromBottomUp()) O << "|"; if (!DTraits.renderGraphFromBottomUp()) O << "|";
O << "{" << EdgeSourceLabels.str() << "}"; O << "{" << EdgeSourceLabels.str() << "}";
if (DTraits.renderGraphFromBottomUp()) O << "|"; if (DTraits.renderGraphFromBottomUp()) O << "|";
} }
if (DTraits.renderGraphFromBottomUp()) { if (DTraits.renderGraphFromBottomUp()) {
O << DOT::EscapeString(DTraits.getNodeLabel(Node, G)); O << DOT::EscapeString(DTraits.getNodeLabel(Node, G));
// If we should include the address of the node in the label, do so n ow. // If we should include the address of the node in the label, do so n ow.
if (DTraits.hasNodeAddressLabel(Node, G)) if (DTraits.hasNodeAddressLabel(Node, G))
O << "|" << (void*)Node; O << "|" << static_cast<const void*>(Node);
} }
if (DTraits.hasEdgeDestLabels()) { if (DTraits.hasEdgeDestLabels()) {
O << "|{"; O << "|{";
unsigned i = 0, e = DTraits.numEdgeDestLabels(Node); unsigned i = 0, e = DTraits.numEdgeDestLabels(Node);
for (; i != e && i != 64; ++i) { for (; i != e && i != 64; ++i) {
if (i) O << "|"; if (i) O << "|";
O << "<d" << i << ">" O << "<d" << i << ">"
<< DOT::EscapeString(DTraits.getEdgeDestLabel(Node, i)); << DOT::EscapeString(DTraits.getEdgeDestLabel(Node, i));
 End of changes. 2 change blocks. 
2 lines changed or deleted 2 lines changed or added


 Hashing.h   Hashing.h 
skipping to change at line 79 skipping to change at line 79
/// This object represents the result of hashing some entity. It is intende d to /// This object represents the result of hashing some entity. It is intende d to
/// be used to implement hashtables or other hashing-based data structures. /// be used to implement hashtables or other hashing-based data structures.
/// While it wraps and exposes a numeric value, this value should not be /// While it wraps and exposes a numeric value, this value should not be
/// trusted to be stable or predictable across processes or executions. /// trusted to be stable or predictable across processes or executions.
/// ///
/// In order to obtain the hash_code for an object 'x': /// In order to obtain the hash_code for an object 'x':
/// \code /// \code
/// using llvm::hash_value; /// using llvm::hash_value;
/// llvm::hash_code code = hash_value(x); /// llvm::hash_code code = hash_value(x);
/// \endcode /// \endcode
///
/// Also note that there are two numerical values which are reserved, and t
he
/// implementation ensures will never be produced for real hash_codes. Thes
e
/// can be used as sentinels within hashing data structures.
class hash_code { class hash_code {
size_t value; size_t value;
public: public:
/// \brief Default construct a hash_code. /// \brief Default construct a hash_code.
/// Note that this leaves the value uninitialized. /// Note that this leaves the value uninitialized.
hash_code() {} hash_code() {}
/// \brief Form a hash code directly from a numerical value. /// \brief Form a hash code directly from a numerical value.
hash_code(size_t value) : value(value) {} hash_code(size_t value) : value(value) {}
skipping to change at line 412 skipping to change at line 408
return true; return true;
} }
/// \brief Implement the combining of integral values into a hash_code. /// \brief Implement the combining of integral values into a hash_code.
/// ///
/// This overload is selected when the value type of the iterator is /// This overload is selected when the value type of the iterator is
/// integral. Rather than computing a hash_code for each object and then /// integral. Rather than computing a hash_code for each object and then
/// combining them, this (as an optimization) directly combines the integer s. /// combining them, this (as an optimization) directly combines the integer s.
template <typename InputIteratorT> template <typename InputIteratorT>
hash_code hash_combine_range_impl(InputIteratorT first, InputIteratorT last ) { hash_code hash_combine_range_impl(InputIteratorT first, InputIteratorT last ) {
typedef typename std::iterator_traits<InputIteratorT>::value_type ValueT;
const size_t seed = get_execution_seed(); const size_t seed = get_execution_seed();
char buffer[64], *buffer_ptr = buffer; char buffer[64], *buffer_ptr = buffer;
char *const buffer_end = buffer_ptr + array_lengthof(buffer); char *const buffer_end = buffer_ptr + array_lengthof(buffer);
while (first != last && store_and_advance(buffer_ptr, buffer_end, while (first != last && store_and_advance(buffer_ptr, buffer_end,
get_hashable_data(*first))) get_hashable_data(*first)))
++first; ++first;
if (first == last) if (first == last)
return hash_short(buffer, buffer_ptr - buffer, seed); return hash_short(buffer, buffer_ptr - buffer, seed);
assert(buffer_ptr == buffer_end); assert(buffer_ptr == buffer_end);
skipping to change at line 710 skipping to change at line 705
return helper.combine(0, helper.buffer, helper.buffer + 64, arg1, arg2); return helper.combine(0, helper.buffer, helper.buffer + 64, arg1, arg2);
} }
template <typename T1> template <typename T1>
hash_code hash_combine(const T1 &arg1) { hash_code hash_combine(const T1 &arg1) {
::llvm::hashing::detail::hash_combine_recursive_helper helper; ::llvm::hashing::detail::hash_combine_recursive_helper helper;
return helper.combine(0, helper.buffer, helper.buffer + 64, arg1); return helper.combine(0, helper.buffer, helper.buffer + 64, arg1);
} }
#endif #endif
// Implementation details for implementatinos of hash_value overloads provi ded // Implementation details for implementations of hash_value overloads provi ded
// here. // here.
namespace hashing { namespace hashing {
namespace detail { namespace detail {
/// \brief Helper to hash the value of a single integer. /// \brief Helper to hash the value of a single integer.
/// ///
/// Overloads for smaller integer types are not provided to ensure consiste nt /// Overloads for smaller integer types are not provided to ensure consiste nt
/// behavior in the presence of integral promotions. Essentially, /// behavior in the presence of integral promotions. Essentially,
/// "hash_value('4')" and "hash_value('0' + 4)" should be the same. /// "hash_value('4')" and "hash_value('0' + 4)" should be the same.
inline hash_code hash_integer_value(uint64_t value) { inline hash_code hash_integer_value(uint64_t value) {
 End of changes. 3 change blocks. 
8 lines changed or deleted 1 lines changed or added


 HeuristicBase.h   HeuristicBase.h 
skipping to change at line 116 skipping to change at line 116
/// should be <i>at least</i> as strong as this. I.e. Nodes of degree 3 or /// should be <i>at least</i> as strong as this. I.e. Nodes of degree 3 or
/// higher should not be selected under any circumstances. /// higher should not be selected under any circumstances.
bool shouldOptimallyReduce(Graph::NodeItr nItr) { bool shouldOptimallyReduce(Graph::NodeItr nItr) {
if (g.getNodeDegree(nItr) < 3) if (g.getNodeDegree(nItr) < 3)
return true; return true;
// else // else
return false; return false;
} }
/// \brief Add the given node to the list of nodes to be optimally redu ced. /// \brief Add the given node to the list of nodes to be optimally redu ced.
/// @return nItr Node iterator to be added. /// @param nItr Node iterator to be added.
/// ///
/// You probably don't want to over-ride this, except perhaps to record /// You probably don't want to over-ride this, except perhaps to record
/// statistics before calling this implementation. HeuristicBase relies on /// statistics before calling this implementation. HeuristicBase relies on
/// its behaviour. /// its behaviour.
void addToOptimalReduceList(Graph::NodeItr nItr) { void addToOptimalReduceList(Graph::NodeItr nItr) {
optimalList.push_back(nItr); optimalList.push_back(nItr);
} }
/// \brief Initialise the heuristic. /// \brief Initialise the heuristic.
/// ///
skipping to change at line 196 skipping to change at line 196
/// \brief Add a node to the heuristic reduce list. /// \brief Add a node to the heuristic reduce list.
/// @param nItr Node iterator to add to the heuristic reduce list. /// @param nItr Node iterator to add to the heuristic reduce list.
void addToHeuristicList(Graph::NodeItr nItr) { void addToHeuristicList(Graph::NodeItr nItr) {
llvm_unreachable("Must be implemented in derived class."); llvm_unreachable("Must be implemented in derived class.");
} }
/// \brief Heuristically reduce one of the nodes in the heuristic /// \brief Heuristically reduce one of the nodes in the heuristic
/// reduce list. /// reduce list.
/// @return True if a reduction takes place, false if the heuristic red uce /// @return True if a reduction takes place, false if the heuristic red uce
/// list is empty. /// list is empty.
void heuristicReduce() { bool heuristicReduce() {
llvm_unreachable("Must be implemented in derived class."); llvm_unreachable("Must be implemented in derived class.");
return false;
} }
/// \brief Prepare a change in the costs on the given edge. /// \brief Prepare a change in the costs on the given edge.
/// @param eItr Edge iterator. /// @param eItr Edge iterator.
void preUpdateEdgeCosts(Graph::EdgeItr eItr) { void preUpdateEdgeCosts(Graph::EdgeItr eItr) {
llvm_unreachable("Must be implemented in derived class."); llvm_unreachable("Must be implemented in derived class.");
} }
/// \brief Handle the change in the costs on the given edge. /// \brief Handle the change in the costs on the given edge.
/// @param eItr Edge iterator. /// @param eItr Edge iterator.
 End of changes. 3 change blocks. 
2 lines changed or deleted 3 lines changed or added


 IPO.h   IPO.h 
skipping to change at line 104 skipping to change at line 104
Pass *createAlwaysInlinerPass(bool InsertLifetime); Pass *createAlwaysInlinerPass(bool InsertLifetime);
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
/// createPruneEHPass - Return a new pass object which transforms invoke /// createPruneEHPass - Return a new pass object which transforms invoke
/// instructions into calls, if the callee can _not_ unwind the stack. /// instructions into calls, if the callee can _not_ unwind the stack.
/// ///
Pass *createPruneEHPass(); Pass *createPruneEHPass();
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
/// createInternalizePass - This pass loops over all of the functions in th e /// createInternalizePass - This pass loops over all of the functions in th e
/// input module, internalizing all globals (functions and variables) not p
art
/// of the api. If a list of symbols is specified with the
/// -internalize-public-api-* command line options, those symbols are not
/// internalized and all others are. Otherwise if AllButMain is set and th
e
/// main function is found, all other globals are marked as internal. If no
api
/// is supplied and AllButMain is not set, or no main function is found, no
thing
/// is internalized.
///
ModulePass *createInternalizePass(bool AllButMain);
/// createInternalizePass - This pass loops over all of the functions in th
e
/// input module, internalizing all globals (functions and variables) not i n the /// input module, internalizing all globals (functions and variables) not i n the
/// given exportList. /// given exportList.
/// ///
/// Note that commandline options that are used with the above function are not /// Note that commandline options that are used with the above function are not
/// used now! Also, when exportList is empty, nothing is internalized. /// used now!
ModulePass *createInternalizePass(const std::vector<const char *> &exportLi st); ModulePass *createInternalizePass(const std::vector<const char *> &exportLi st);
/// createInternalizePass - Same as above, but with an empty exportList.
ModulePass *createInternalizePass();
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
/// createDeadArgEliminationPass - This pass removes arguments from functio ns /// createDeadArgEliminationPass - This pass removes arguments from functio ns
/// which are not used by the body of the function. /// which are not used by the body of the function.
/// ///
ModulePass *createDeadArgEliminationPass(); ModulePass *createDeadArgEliminationPass();
/// DeadArgHacking pass - Same as DAE, but delete arguments of external /// DeadArgHacking pass - Same as DAE, but delete arguments of external
/// functions as well. This is definitely not safe, and should only be use d by /// functions as well. This is definitely not safe, and should only be use d by
/// bugpoint. /// bugpoint.
skipping to change at line 193 skipping to change at line 184
/// createMergeFunctionsPass - This pass discovers identical functions and /// createMergeFunctionsPass - This pass discovers identical functions and
/// collapses them. /// collapses them.
/// ///
ModulePass *createMergeFunctionsPass(); ModulePass *createMergeFunctionsPass();
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
/// createPartialInliningPass - This pass inlines parts of functions. /// createPartialInliningPass - This pass inlines parts of functions.
/// ///
ModulePass *createPartialInliningPass(); ModulePass *createPartialInliningPass();
//===----------------------------------------------------------------------
===//
// createMetaRenamerPass - Rename everything with metasyntatic names.
//
ModulePass *createMetaRenamerPass();
//===----------------------------------------------------------------------
===//
/// createBarrierNoopPass - This pass is purely a module pass barrier in a
pass
/// manager.
ModulePass *createBarrierNoopPass();
} // End llvm namespace } // End llvm namespace
#endif #endif
 End of changes. 4 change blocks. 
17 lines changed or deleted 16 lines changed or added


 IRBuilder.h   IRBuilder.h 
//===---- llvm/Support/IRBuilder.h - Builder for LLVM Instrs ----*- C++ -*- ===// //===---- llvm/IRBuilder.h - Builder for LLVM Instructions ------*- C++ -*- ===//
// //
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
// //
// This file is distributed under the University of Illinois Open Source // This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details. // License. See LICENSE.TXT for details.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// //
// This file defines the IRBuilder class, which is used as a convenient way // This file defines the IRBuilder class, which is used as a convenient way
// to create LLVM instructions with a consistent and simplified interface. // to create LLVM instructions with a consistent and simplified interface.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_SUPPORT_IRBUILDER_H #ifndef LLVM_IRBUILDER_H
#define LLVM_SUPPORT_IRBUILDER_H #define LLVM_IRBUILDER_H
#include "llvm/Instructions.h" #include "llvm/Instructions.h"
#include "llvm/BasicBlock.h" #include "llvm/BasicBlock.h"
#include "llvm/DataLayout.h"
#include "llvm/LLVMContext.h" #include "llvm/LLVMContext.h"
#include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/StringRef.h" #include "llvm/ADT/StringRef.h"
#include "llvm/ADT/Twine.h" #include "llvm/ADT/Twine.h"
#include "llvm/Support/ConstantFolder.h" #include "llvm/Support/ConstantFolder.h"
namespace llvm { namespace llvm {
class MDNode; class MDNode;
/// IRBuilderDefaultInserter - This provides the default implementation of the /// IRBuilderDefaultInserter - This provides the default implementation of the
skipping to change at line 269 skipping to change at line 270
/// getVoidTy - Fetch the type representing void. /// getVoidTy - Fetch the type representing void.
Type *getVoidTy() { Type *getVoidTy() {
return Type::getVoidTy(Context); return Type::getVoidTy(Context);
} }
PointerType *getInt8PtrTy(unsigned AddrSpace = 0) { PointerType *getInt8PtrTy(unsigned AddrSpace = 0) {
return Type::getInt8PtrTy(Context, AddrSpace); return Type::getInt8PtrTy(Context, AddrSpace);
} }
IntegerType* getIntPtrTy(DataLayout *DL, unsigned AddrSpace = 0) {
return DL->getIntPtrType(Context, AddrSpace);
}
//===-------------------------------------------------------------------- ===// //===-------------------------------------------------------------------- ===//
// Intrinsic creation methods // Intrinsic creation methods
//===-------------------------------------------------------------------- ===// //===-------------------------------------------------------------------- ===//
/// CreateMemSet - Create and insert a memset to the specified pointer an d the /// CreateMemSet - Create and insert a memset to the specified pointer an d the
/// specified value. If the pointer isn't an i8*, it will be converted. If a /// specified value. If the pointer isn't an i8*, it will be converted. If a
/// TBAA tag is specified, it will be added to the instruction. /// TBAA tag is specified, it will be added to the instruction.
CallInst *CreateMemSet(Value *Ptr, Value *Val, uint64_t Size, unsigned Al ign, CallInst *CreateMemSet(Value *Ptr, Value *Val, uint64_t Size, unsigned Al ign,
bool isVolatile = false, MDNode *TBAATag = 0) { bool isVolatile = false, MDNode *TBAATag = 0) {
return CreateMemSet(Ptr, Val, getInt64(Size), Align, isVolatile, TBAATa g); return CreateMemSet(Ptr, Val, getInt64(Size), Align, isVolatile, TBAATa g);
} }
CallInst *CreateMemSet(Value *Ptr, Value *Val, Value *Size, unsigned Alig n, CallInst *CreateMemSet(Value *Ptr, Value *Val, Value *Size, unsigned Alig n,
bool isVolatile = false, MDNode *TBAATag = 0); bool isVolatile = false, MDNode *TBAATag = 0);
/// CreateMemCpy - Create and insert a memcpy between the specified point ers. /// CreateMemCpy - Create and insert a memcpy between the specified point ers.
/// If the pointers aren't i8*, they will be converted. If a TBAA tag is /// If the pointers aren't i8*, they will be converted. If a TBAA tag is
/// specified, it will be added to the instruction. /// specified, it will be added to the instruction.
CallInst *CreateMemCpy(Value *Dst, Value *Src, uint64_t Size, unsigned Al ign, CallInst *CreateMemCpy(Value *Dst, Value *Src, uint64_t Size, unsigned Al ign,
bool isVolatile = false, MDNode *TBAATag = 0) { bool isVolatile = false, MDNode *TBAATag = 0,
return CreateMemCpy(Dst, Src, getInt64(Size), Align, isVolatile, TBAATa MDNode *TBAAStructTag = 0) {
g); return CreateMemCpy(Dst, Src, getInt64(Size), Align, isVolatile, TBAATa
g,
TBAAStructTag);
} }
CallInst *CreateMemCpy(Value *Dst, Value *Src, Value *Size, unsigned Alig n, CallInst *CreateMemCpy(Value *Dst, Value *Src, Value *Size, unsigned Alig n,
bool isVolatile = false, MDNode *TBAATag = 0); bool isVolatile = false, MDNode *TBAATag = 0,
MDNode *TBAAStructTag = 0);
/// CreateMemMove - Create and insert a memmove between the specified /// CreateMemMove - Create and insert a memmove between the specified
/// pointers. If the pointers aren't i8*, they will be converted. If a TBAA /// pointers. If the pointers aren't i8*, they will be converted. If a TBAA
/// tag is specified, it will be added to the instruction. /// tag is specified, it will be added to the instruction.
CallInst *CreateMemMove(Value *Dst, Value *Src, uint64_t Size, unsigned A lign, CallInst *CreateMemMove(Value *Dst, Value *Src, uint64_t Size, unsigned A lign,
bool isVolatile = false, MDNode *TBAATag = 0) { bool isVolatile = false, MDNode *TBAATag = 0) {
return CreateMemMove(Dst, Src, getInt64(Size), Align, isVolatile, TBAAT ag); return CreateMemMove(Dst, Src, getInt64(Size), Align, isVolatile, TBAAT ag);
} }
CallInst *CreateMemMove(Value *Dst, Value *Src, Value *Size, unsigned Ali gn, CallInst *CreateMemMove(Value *Dst, Value *Src, Value *Size, unsigned Ali gn,
skipping to change at line 414 skipping to change at line 422
/// Insert - No-op overload to handle constants. /// Insert - No-op overload to handle constants.
Constant *Insert(Constant *C, const Twine& = "") const { Constant *Insert(Constant *C, const Twine& = "") const {
return C; return C;
} }
//===-------------------------------------------------------------------- ===// //===-------------------------------------------------------------------- ===//
// Instruction creation methods: Terminators // Instruction creation methods: Terminators
//===-------------------------------------------------------------------- ===// //===-------------------------------------------------------------------- ===//
private:
/// \brief Helper to add branch weight metadata onto an instruction.
/// \returns The annotated instruction.
template <typename InstTy>
InstTy *addBranchWeights(InstTy *I, MDNode *Weights) {
if (Weights)
I->setMetadata(LLVMContext::MD_prof, Weights);
return I;
}
public:
/// CreateRetVoid - Create a 'ret void' instruction. /// CreateRetVoid - Create a 'ret void' instruction.
ReturnInst *CreateRetVoid() { ReturnInst *CreateRetVoid() {
return Insert(ReturnInst::Create(Context)); return Insert(ReturnInst::Create(Context));
} }
/// @verbatim /// @verbatim
/// CreateRet - Create a 'ret <val>' instruction. /// CreateRet - Create a 'ret <val>' instruction.
/// @endverbatim /// @endverbatim
ReturnInst *CreateRet(Value *V) { ReturnInst *CreateRet(Value *V) {
return Insert(ReturnInst::Create(Context, V)); return Insert(ReturnInst::Create(Context, V));
skipping to change at line 447 skipping to change at line 466
return Insert(ReturnInst::Create(Context, V)); return Insert(ReturnInst::Create(Context, V));
} }
/// CreateBr - Create an unconditional 'br label X' instruction. /// CreateBr - Create an unconditional 'br label X' instruction.
BranchInst *CreateBr(BasicBlock *Dest) { BranchInst *CreateBr(BasicBlock *Dest) {
return Insert(BranchInst::Create(Dest)); return Insert(BranchInst::Create(Dest));
} }
/// CreateCondBr - Create a conditional 'br Cond, TrueDest, FalseDest' /// CreateCondBr - Create a conditional 'br Cond, TrueDest, FalseDest'
/// instruction. /// instruction.
BranchInst *CreateCondBr(Value *Cond, BasicBlock *True, BasicBlock *False BranchInst *CreateCondBr(Value *Cond, BasicBlock *True, BasicBlock *False
) { ,
return Insert(BranchInst::Create(True, False, Cond)); MDNode *BranchWeights = 0) {
return Insert(addBranchWeights(BranchInst::Create(True, False, Cond),
BranchWeights));
} }
/// CreateSwitch - Create a switch instruction with the specified value, /// CreateSwitch - Create a switch instruction with the specified value,
/// default dest, and with a hint for the number of cases that will be ad ded /// default dest, and with a hint for the number of cases that will be ad ded
/// (for efficient allocation). /// (for efficient allocation).
SwitchInst *CreateSwitch(Value *V, BasicBlock *Dest, unsigned NumCases = SwitchInst *CreateSwitch(Value *V, BasicBlock *Dest, unsigned NumCases =
10) { 10,
return Insert(SwitchInst::Create(V, Dest, NumCases)); MDNode *BranchWeights = 0) {
return Insert(addBranchWeights(SwitchInst::Create(V, Dest, NumCases),
BranchWeights));
} }
/// CreateIndirectBr - Create an indirect branch instruction with the /// CreateIndirectBr - Create an indirect branch instruction with the
/// specified address operand, with an optional hint for the number of /// specified address operand, with an optional hint for the number of
/// destinations that will be added (for efficient allocation). /// destinations that will be added (for efficient allocation).
IndirectBrInst *CreateIndirectBr(Value *Addr, unsigned NumDests = 10) { IndirectBrInst *CreateIndirectBr(Value *Addr, unsigned NumDests = 10) {
return Insert(IndirectBrInst::Create(Addr, NumDests)); return Insert(IndirectBrInst::Create(Addr, NumDests));
} }
InvokeInst *CreateInvoke(Value *Callee, BasicBlock *NormalDest, InvokeInst *CreateInvoke(Value *Callee, BasicBlock *NormalDest,
skipping to change at line 798 skipping to change at line 821
} }
LoadInst *CreateLoad(Value *Ptr, const Twine &Name = "") { LoadInst *CreateLoad(Value *Ptr, const Twine &Name = "") {
return Insert(new LoadInst(Ptr), Name); return Insert(new LoadInst(Ptr), Name);
} }
LoadInst *CreateLoad(Value *Ptr, bool isVolatile, const Twine &Name = "") { LoadInst *CreateLoad(Value *Ptr, bool isVolatile, const Twine &Name = "") {
return Insert(new LoadInst(Ptr, 0, isVolatile), Name); return Insert(new LoadInst(Ptr, 0, isVolatile), Name);
} }
StoreInst *CreateStore(Value *Val, Value *Ptr, bool isVolatile = false) { StoreInst *CreateStore(Value *Val, Value *Ptr, bool isVolatile = false) {
return Insert(new StoreInst(Val, Ptr, isVolatile)); return Insert(new StoreInst(Val, Ptr, isVolatile));
} }
// Provided to resolve 'CreateAlignedLoad(Ptr, Align, "...")' correctly,
// instead of converting the string to 'bool' for the isVolatile paramete
r.
LoadInst *CreateAlignedLoad(Value *Ptr, unsigned Align, const char *Name)
{
LoadInst *LI = CreateLoad(Ptr, Name);
LI->setAlignment(Align);
return LI;
}
LoadInst *CreateAlignedLoad(Value *Ptr, unsigned Align,
const Twine &Name = "") {
LoadInst *LI = CreateLoad(Ptr, Name);
LI->setAlignment(Align);
return LI;
}
LoadInst *CreateAlignedLoad(Value *Ptr, unsigned Align, bool isVolatile,
const Twine &Name = "") {
LoadInst *LI = CreateLoad(Ptr, isVolatile, Name);
LI->setAlignment(Align);
return LI;
}
StoreInst *CreateAlignedStore(Value *Val, Value *Ptr, unsigned Align,
bool isVolatile = false) {
StoreInst *SI = CreateStore(Val, Ptr, isVolatile);
SI->setAlignment(Align);
return SI;
}
FenceInst *CreateFence(AtomicOrdering Ordering, FenceInst *CreateFence(AtomicOrdering Ordering,
SynchronizationScope SynchScope = CrossThread) { SynchronizationScope SynchScope = CrossThread) {
return Insert(new FenceInst(Context, Ordering, SynchScope)); return Insert(new FenceInst(Context, Ordering, SynchScope));
} }
AtomicCmpXchgInst *CreateAtomicCmpXchg(Value *Ptr, Value *Cmp, Value *New , AtomicCmpXchgInst *CreateAtomicCmpXchg(Value *Ptr, Value *Cmp, Value *New ,
AtomicOrdering Ordering, AtomicOrdering Ordering,
SynchronizationScope SynchScope = CrossThrea d) { SynchronizationScope SynchScope = CrossThrea d) {
return Insert(new AtomicCmpXchgInst(Ptr, Cmp, New, Ordering, SynchScope )); return Insert(new AtomicCmpXchgInst(Ptr, Cmp, New, Ordering, SynchScope ));
} }
AtomicRMWInst *CreateAtomicRMW(AtomicRMWInst::BinOp Op, Value *Ptr, Value *Val, AtomicRMWInst *CreateAtomicRMW(AtomicRMWInst::BinOp Op, Value *Ptr, Value *Val,
skipping to change at line 958 skipping to change at line 1006
Value *CreateTrunc(Value *V, Type *DestTy, const Twine &Name = "") { Value *CreateTrunc(Value *V, Type *DestTy, const Twine &Name = "") {
return CreateCast(Instruction::Trunc, V, DestTy, Name); return CreateCast(Instruction::Trunc, V, DestTy, Name);
} }
Value *CreateZExt(Value *V, Type *DestTy, const Twine &Name = "") { Value *CreateZExt(Value *V, Type *DestTy, const Twine &Name = "") {
return CreateCast(Instruction::ZExt, V, DestTy, Name); return CreateCast(Instruction::ZExt, V, DestTy, Name);
} }
Value *CreateSExt(Value *V, Type *DestTy, const Twine &Name = "") { Value *CreateSExt(Value *V, Type *DestTy, const Twine &Name = "") {
return CreateCast(Instruction::SExt, V, DestTy, Name); return CreateCast(Instruction::SExt, V, DestTy, Name);
} }
/// CreateZExtOrTrunc - Create a ZExt or Trunc from the integer value V t
o
/// DestTy. Return the value untouched if the type of V is already DestTy
.
Value *CreateZExtOrTrunc(Value *V, IntegerType *DestTy,
const Twine &Name = "") {
assert(isa<IntegerType>(V->getType()) && "Can only zero extend integers
!");
IntegerType *IntTy = cast<IntegerType>(V->getType());
if (IntTy->getBitWidth() < DestTy->getBitWidth())
return CreateZExt(V, DestTy, Name);
if (IntTy->getBitWidth() > DestTy->getBitWidth())
return CreateTrunc(V, DestTy, Name);
return V;
}
/// CreateSExtOrTrunc - Create a SExt or Trunc from the integer value V t
o
/// DestTy. Return the value untouched if the type of V is already DestTy
.
Value *CreateSExtOrTrunc(Value *V, IntegerType *DestTy,
const Twine &Name = "") {
assert(isa<IntegerType>(V->getType()) && "Can only sign extend integers
!");
IntegerType *IntTy = cast<IntegerType>(V->getType());
if (IntTy->getBitWidth() < DestTy->getBitWidth())
return CreateSExt(V, DestTy, Name);
if (IntTy->getBitWidth() > DestTy->getBitWidth())
return CreateTrunc(V, DestTy, Name);
return V;
}
Value *CreateFPToUI(Value *V, Type *DestTy, const Twine &Name = ""){ Value *CreateFPToUI(Value *V, Type *DestTy, const Twine &Name = ""){
return CreateCast(Instruction::FPToUI, V, DestTy, Name); return CreateCast(Instruction::FPToUI, V, DestTy, Name);
} }
Value *CreateFPToSI(Value *V, Type *DestTy, const Twine &Name = ""){ Value *CreateFPToSI(Value *V, Type *DestTy, const Twine &Name = ""){
return CreateCast(Instruction::FPToSI, V, DestTy, Name); return CreateCast(Instruction::FPToSI, V, DestTy, Name);
} }
Value *CreateUIToFP(Value *V, Type *DestTy, const Twine &Name = ""){ Value *CreateUIToFP(Value *V, Type *DestTy, const Twine &Name = ""){
return CreateCast(Instruction::UIToFP, V, DestTy, Name); return CreateCast(Instruction::UIToFP, V, DestTy, Name);
} }
Value *CreateSIToFP(Value *V, Type *DestTy, const Twine &Name = ""){ Value *CreateSIToFP(Value *V, Type *DestTy, const Twine &Name = ""){
skipping to change at line 1040 skipping to change at line 1112
const Twine &Name = "") { const Twine &Name = "") {
if (V->getType() == DestTy) if (V->getType() == DestTy)
return V; return V;
if (Constant *VC = dyn_cast<Constant>(V)) if (Constant *VC = dyn_cast<Constant>(V))
return Insert(Folder.CreateIntCast(VC, DestTy, isSigned), Name); return Insert(Folder.CreateIntCast(VC, DestTy, isSigned), Name);
return Insert(CastInst::CreateIntegerCast(V, DestTy, isSigned), Name); return Insert(CastInst::CreateIntegerCast(V, DestTy, isSigned), Name);
} }
private: private:
// Provided to resolve 'CreateIntCast(Ptr, Ptr, "...")', giving a compile time // Provided to resolve 'CreateIntCast(Ptr, Ptr, "...")', giving a compile time
// error, instead of converting the string to bool for the isSigned param eter. // error, instead of converting the string to bool for the isSigned param eter.
Value *CreateIntCast(Value *, Type *, const char *); // DO NOT IMPLEMENT Value *CreateIntCast(Value *, Type *, const char *) LLVM_DELETED_FUNCTION ;
public: public:
Value *CreateFPCast(Value *V, Type *DestTy, const Twine &Name = "") { Value *CreateFPCast(Value *V, Type *DestTy, const Twine &Name = "") {
if (V->getType() == DestTy) if (V->getType() == DestTy)
return V; return V;
if (Constant *VC = dyn_cast<Constant>(V)) if (Constant *VC = dyn_cast<Constant>(V))
return Insert(Folder.CreateFPCast(VC, DestTy), Name); return Insert(Folder.CreateFPCast(VC, DestTy), Name);
return Insert(CastInst::CreateFPCast(V, DestTy), Name); return Insert(CastInst::CreateFPCast(V, DestTy), Name);
} }
//===-------------------------------------------------------------------- ===// //===-------------------------------------------------------------------- ===//
skipping to change at line 1249 skipping to change at line 1321
LandingPadInst *CreateLandingPad(Type *Ty, Value *PersFn, unsigned NumCla uses, LandingPadInst *CreateLandingPad(Type *Ty, Value *PersFn, unsigned NumCla uses,
const Twine &Name = "") { const Twine &Name = "") {
return Insert(LandingPadInst::Create(Ty, PersFn, NumClauses, Name)); return Insert(LandingPadInst::Create(Ty, PersFn, NumClauses, Name));
} }
//===-------------------------------------------------------------------- ===// //===-------------------------------------------------------------------- ===//
// Utility creation methods // Utility creation methods
//===-------------------------------------------------------------------- ===// //===-------------------------------------------------------------------- ===//
/// CreateIsNull - Return an i1 value testing if \arg Arg is null. /// CreateIsNull - Return an i1 value testing if \p Arg is null.
Value *CreateIsNull(Value *Arg, const Twine &Name = "") { Value *CreateIsNull(Value *Arg, const Twine &Name = "") {
return CreateICmpEQ(Arg, Constant::getNullValue(Arg->getType()), return CreateICmpEQ(Arg, Constant::getNullValue(Arg->getType()),
Name); Name);
} }
/// CreateIsNotNull - Return an i1 value testing if \arg Arg is not null. /// CreateIsNotNull - Return an i1 value testing if \p Arg is not null.
Value *CreateIsNotNull(Value *Arg, const Twine &Name = "") { Value *CreateIsNotNull(Value *Arg, const Twine &Name = "") {
return CreateICmpNE(Arg, Constant::getNullValue(Arg->getType()), return CreateICmpNE(Arg, Constant::getNullValue(Arg->getType()),
Name); Name);
} }
/// CreatePtrDiff - Return the i64 difference between two pointer values, /// CreatePtrDiff - Return the i64 difference between two pointer values,
/// dividing out the size of the pointed-to objects. This is intended to /// dividing out the size of the pointed-to objects. This is intended to
/// implement C-style pointer subtraction. As such, the pointers must be /// implement C-style pointer subtraction. As such, the pointers must be
/// appropriately aligned for their element types and pointing into the /// appropriately aligned for their element types and pointing into the
/// same object. /// same object.
 End of changes. 14 change blocks. 
16 lines changed or deleted 96 lines changed or added


 ISDOpcodes.h   ISDOpcodes.h 
skipping to change at line 40 skipping to change at line 40
/// Targets should aim to use target-independent operators to model their /// Targets should aim to use target-independent operators to model their
/// instruction sets as much as possible, and only use target-dependent /// instruction sets as much as possible, and only use target-dependent
/// operators when they have special requirements. /// operators when they have special requirements.
/// ///
/// Finally, during and after selection proper, SNodes may use special /// Finally, during and after selection proper, SNodes may use special
/// operator codes that correspond directly with MachineInstr opcodes. Th ese /// operator codes that correspond directly with MachineInstr opcodes. Th ese
/// are used to represent selected instructions. See the isMachineOpcode( ) /// are used to represent selected instructions. See the isMachineOpcode( )
/// and getMachineOpcode() member functions of SDNode. /// and getMachineOpcode() member functions of SDNode.
/// ///
enum NodeType { enum NodeType {
// DELETED_NODE - This is an illegal value that is used to catch /// DELETED_NODE - This is an illegal value that is used to catch
// errors. This opcode is not a legal opcode for any node. /// errors. This opcode is not a legal opcode for any node.
DELETED_NODE, DELETED_NODE,
// EntryToken - This is the marker used to indicate the start of the re gion. /// EntryToken - This is the marker used to indicate the start of a reg ion.
EntryToken, EntryToken,
// TokenFactor - This node takes multiple tokens as input and produces /// TokenFactor - This node takes multiple tokens as input and produces
a a
// single token result. This is used to represent the fact that the op /// single token result. This is used to represent the fact that the op
erand erand
// operators are independent of each other. /// operators are independent of each other.
TokenFactor, TokenFactor,
// AssertSext, AssertZext - These nodes record if a register contains a /// AssertSext, AssertZext - These nodes record if a register contains
// value that has already been zero or sign extended from a narrower ty a
pe. /// value that has already been zero or sign extended from a narrower t
// These nodes take two operands. The first is the node that has alrea ype.
dy /// These nodes take two operands. The first is the node that has alre
// been extended, and the second is a value type node indicating the wi ady
dth /// been extended, and the second is a value type node indicating the w
// of the extension idth
/// of the extension
AssertSext, AssertZext, AssertSext, AssertZext,
// Various leaf nodes. /// Various leaf nodes.
BasicBlock, VALUETYPE, CONDCODE, Register, RegisterMask, BasicBlock, VALUETYPE, CONDCODE, Register, RegisterMask,
Constant, ConstantFP, Constant, ConstantFP,
GlobalAddress, GlobalTLSAddress, FrameIndex, GlobalAddress, GlobalTLSAddress, FrameIndex,
JumpTable, ConstantPool, ExternalSymbol, BlockAddress, JumpTable, ConstantPool, ExternalSymbol, BlockAddress,
// The address of the GOT /// The address of the GOT
GLOBAL_OFFSET_TABLE, GLOBAL_OFFSET_TABLE,
// FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and /// FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and
// llvm.returnaddress on the DAG. These nodes take one operand, the in /// llvm.returnaddress on the DAG. These nodes take one operand, the i
dex ndex
// of the frame or return address to return. An index of zero correspo /// of the frame or return address to return. An index of zero corresp
nds onds
// to the current function's frame or return address, an index of one t /// to the current function's frame or return address, an index of one
o the to
// parent's frame or return address, and so on. /// the parent's frame or return address, and so on.
FRAMEADDR, RETURNADDR, FRAMEADDR, RETURNADDR,
// FRAME_TO_ARGS_OFFSET - This node represents offset from frame pointe /// FRAME_TO_ARGS_OFFSET - This node represents offset from frame point
r to er to
// first (possible) on-stack argument. This is needed for correct stack /// first (possible) on-stack argument. This is needed for correct stac
// adjustment during unwind. k
/// adjustment during unwind.
FRAME_TO_ARGS_OFFSET, FRAME_TO_ARGS_OFFSET,
// RESULT, OUTCHAIN = EXCEPTIONADDR(INCHAIN) - This node represents the /// RESULT, OUTCHAIN = EXCEPTIONADDR(INCHAIN) - This node represents th
// address of the exception block on entry to an landing pad block. e
/// address of the exception block on entry to an landing pad block.
EXCEPTIONADDR, EXCEPTIONADDR,
// RESULT, OUTCHAIN = LSDAADDR(INCHAIN) - This node represents the /// RESULT, OUTCHAIN = LSDAADDR(INCHAIN) - This node represents the
// address of the Language Specific Data Area for the enclosing functio /// address of the Language Specific Data Area for the enclosing functi
n. on.
LSDAADDR, LSDAADDR,
// RESULT, OUTCHAIN = EHSELECTION(INCHAIN, EXCEPTION) - This node repre /// RESULT, OUTCHAIN = EHSELECTION(INCHAIN, EXCEPTION) - This node
sents /// represents the selection index of the exception thrown.
// the selection index of the exception thrown.
EHSELECTION, EHSELECTION,
// OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represent /// OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represen
s ts
// 'eh_return' gcc dwarf builtin, which is used to return from /// 'eh_return' gcc dwarf builtin, which is used to return from
// exception. The general meaning is: adjust stack by OFFSET and pass /// exception. The general meaning is: adjust stack by OFFSET and pass
// execution to HANDLER. Many platform-related details also :) /// execution to HANDLER. Many platform-related details also :)
EH_RETURN, EH_RETURN,
// RESULT, OUTCHAIN = EH_SJLJ_SETJMP(INCHAIN, buffer) /// RESULT, OUTCHAIN = EH_SJLJ_SETJMP(INCHAIN, buffer)
// This corresponds to the eh.sjlj.setjmp intrinsic. /// This corresponds to the eh.sjlj.setjmp intrinsic.
// It takes an input chain and a pointer to the jump buffer as inputs /// It takes an input chain and a pointer to the jump buffer as inputs
// and returns an outchain. /// and returns an outchain.
EH_SJLJ_SETJMP, EH_SJLJ_SETJMP,
// OUTCHAIN = EH_SJLJ_LONGJMP(INCHAIN, buffer) /// OUTCHAIN = EH_SJLJ_LONGJMP(INCHAIN, buffer)
// This corresponds to the eh.sjlj.longjmp intrinsic. /// This corresponds to the eh.sjlj.longjmp intrinsic.
// It takes an input chain and a pointer to the jump buffer as inputs /// It takes an input chain and a pointer to the jump buffer as inputs
// and returns an outchain. /// and returns an outchain.
EH_SJLJ_LONGJMP, EH_SJLJ_LONGJMP,
// TargetConstant* - Like Constant*, but the DAG does not do any foldin /// TargetConstant* - Like Constant*, but the DAG does not do any foldi
g, ng,
// simplification, or lowering of the constant. They are used for const /// simplification, or lowering of the constant. They are used for cons
ants tants
// which are known to fit in the immediate fields of their users, or fo /// which are known to fit in the immediate fields of their users, or f
r or
// carrying magic numbers which are not values which need to be materia /// carrying magic numbers which are not values which need to be
lized /// materialized in registers.
// in registers.
TargetConstant, TargetConstant,
TargetConstantFP, TargetConstantFP,
// TargetGlobalAddress - Like GlobalAddress, but the DAG does no foldin /// TargetGlobalAddress - Like GlobalAddress, but the DAG does no foldi
g or ng or
// anything else with this node, and this is valid in the target-specif /// anything else with this node, and this is valid in the target-speci
ic fic
// dag, turning into a GlobalAddress operand. /// dag, turning into a GlobalAddress operand.
TargetGlobalAddress, TargetGlobalAddress,
TargetGlobalTLSAddress, TargetGlobalTLSAddress,
TargetFrameIndex, TargetFrameIndex,
TargetJumpTable, TargetJumpTable,
TargetConstantPool, TargetConstantPool,
TargetExternalSymbol, TargetExternalSymbol,
TargetBlockAddress, TargetBlockAddress,
/// TargetIndex - Like a constant pool entry, but with completely
/// target-dependent semantics. Holds target flags, a 32-bit index, and
a
/// 64-bit index. Targets can use this however they like.
TargetIndex,
/// RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) /// RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...)
/// This node represents a target intrinsic function with no side effec ts. /// This node represents a target intrinsic function with no side effec ts.
/// The first operand is the ID number of the intrinsic from the /// The first operand is the ID number of the intrinsic from the
/// llvm::Intrinsic namespace. The operands to the intrinsic follow. The /// llvm::Intrinsic namespace. The operands to the intrinsic follow. The
/// node returns the result of the intrinsic. /// node returns the result of the intrinsic.
INTRINSIC_WO_CHAIN, INTRINSIC_WO_CHAIN,
/// RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ... ) /// RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ... )
/// This node represents a target intrinsic function with side effects that /// This node represents a target intrinsic function with side effects that
/// returns a result. The first operand is a chain pointer. The secon d is /// returns a result. The first operand is a chain pointer. The secon d is
skipping to change at line 151 skipping to change at line 156
/// of the intrinsic and an output chain. /// of the intrinsic and an output chain.
INTRINSIC_W_CHAIN, INTRINSIC_W_CHAIN,
/// OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) /// OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...)
/// This node represents a target intrinsic function with side effects that /// This node represents a target intrinsic function with side effects that
/// does not return a result. The first operand is a chain pointer. T he /// does not return a result. The first operand is a chain pointer. T he
/// second is the ID number of the intrinsic from the llvm::Intrinsic /// second is the ID number of the intrinsic from the llvm::Intrinsic
/// namespace. The operands to the intrinsic follow. /// namespace. The operands to the intrinsic follow.
INTRINSIC_VOID, INTRINSIC_VOID,
// CopyToReg - This node has three operands: a chain, a register number /// CopyToReg - This node has three operands: a chain, a register numbe
to r to
// set to this value, and a value. /// set to this value, and a value.
CopyToReg, CopyToReg,
// CopyFromReg - This node indicates that the input value is a virtual /// CopyFromReg - This node indicates that the input value is a virtual
or or
// physical register that is defined outside of the scope of this /// physical register that is defined outside of the scope of this
// SelectionDAG. The register is available from the RegisterSDNode obj /// SelectionDAG. The register is available from the RegisterSDNode ob
ect. ject.
CopyFromReg, CopyFromReg,
// UNDEF - An undefined node /// UNDEF - An undefined node.
UNDEF, UNDEF,
// EXTRACT_ELEMENT - This is used to get the lower or upper (determined /// EXTRACT_ELEMENT - This is used to get the lower or upper (determine
by d by
// a Constant, which is required to be operand #1) half of the integer /// a Constant, which is required to be operand #1) half of the integer
or or
// float value specified as operand #0. This is only for use before /// float value specified as operand #0. This is only for use before
// legalization, for values that will be broken into multiple registers /// legalization, for values that will be broken into multiple register
. s.
EXTRACT_ELEMENT, EXTRACT_ELEMENT,
// BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways. /// BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
Given /// Given two values of the same integer value type, this produces a va
// two values of the same integer value type, this produces a value twi lue
ce as /// twice as big. Like EXTRACT_ELEMENT, this can only be used before
// big. Like EXTRACT_ELEMENT, this can only be used before legalizatio /// legalization.
n.
BUILD_PAIR, BUILD_PAIR,
// MERGE_VALUES - This node takes multiple discrete operands and return /// MERGE_VALUES - This node takes multiple discrete operands and retur
s ns
// them all as its individual results. This nodes has exactly the same /// them all as its individual results. This nodes has exactly the sam
// number of inputs and outputs. This node is useful for some pieces of e
the /// number of inputs and outputs. This node is useful for some pieces o
// code generator that want to think about a single node with multiple f the
// results, not multiple nodes. /// code generator that want to think about a single node with multiple
/// results, not multiple nodes.
MERGE_VALUES, MERGE_VALUES,
// Simple integer binary arithmetic operators. /// Simple integer binary arithmetic operators.
ADD, SUB, MUL, SDIV, UDIV, SREM, UREM, ADD, SUB, MUL, SDIV, UDIV, SREM, UREM,
// SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing /// SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing
// a signed/unsigned value of type i[2*N], and return the full value as /// a signed/unsigned value of type i[2*N], and return the full value a
// two results, each of type iN. s
/// two results, each of type iN.
SMUL_LOHI, UMUL_LOHI, SMUL_LOHI, UMUL_LOHI,
// SDIVREM/UDIVREM - Divide two integers and produce both a quotient an /// SDIVREM/UDIVREM - Divide two integers and produce both a quotient a
d nd
// remainder result. /// remainder result.
SDIVREM, UDIVREM, SDIVREM, UDIVREM,
// CARRY_FALSE - This node is used when folding other nodes, /// CARRY_FALSE - This node is used when folding other nodes,
// like ADDC/SUBC, which indicate the carry result is always false. /// like ADDC/SUBC, which indicate the carry result is always false.
CARRY_FALSE, CARRY_FALSE,
// Carry-setting nodes for multiple precision addition and subtraction. /// Carry-setting nodes for multiple precision addition and subtraction
// These nodes take two operands of the same value type, and produce tw .
o /// These nodes take two operands of the same value type, and produce t
// results. The first result is the normal add or sub result, the seco wo
nd /// results. The first result is the normal add or sub result, the sec
// result is the carry flag result. ond
/// result is the carry flag result.
ADDC, SUBC, ADDC, SUBC,
// Carry-using nodes for multiple precision addition and subtraction. /// Carry-using nodes for multiple precision addition and subtraction.
These These
// nodes take three operands: The first two are the normal lhs and rhs /// nodes take three operands: The first two are the normal lhs and rhs
to to
// the add or sub, and the third is the input carry flag. These nodes /// the add or sub, and the third is the input carry flag. These nodes
// produce two results; the normal result of the add or sub, and the ou /// produce two results; the normal result of the add or sub, and the o
tput utput
// carry flag. These nodes both read and write a carry flag to allow t /// carry flag. These nodes both read and write a carry flag to allow
hem them
// to them to be chained together for add and sub of arbitrarily large /// to them to be chained together for add and sub of arbitrarily large
// values. /// values.
ADDE, SUBE, ADDE, SUBE,
// RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for additio /// RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for additi
n. on.
// These nodes take two operands: the normal LHS and RHS to the add. Th /// These nodes take two operands: the normal LHS and RHS to the add. T
ey hey
// produce two results: the normal result of the add, and a boolean tha /// produce two results: the normal result of the add, and a boolean th
t at
// indicates if an overflow occurred (*not* a flag, because it may be s /// indicates if an overflow occurred (*not* a flag, because it may be
tored store
// to memory, etc.). If the type of the boolean is not i1 then the hig /// to memory, etc.). If the type of the boolean is not i1 then the hi
h gh
// bits conform to getBooleanContents. /// bits conform to getBooleanContents.
// These nodes are generated from the llvm.[su]add.with.overflow intrin /// These nodes are generated from llvm.[su]add.with.overflow intrinsic
sics. s.
SADDO, UADDO, SADDO, UADDO,
// Same for subtraction /// Same for subtraction.
SSUBO, USUBO, SSUBO, USUBO,
// Same for multiplication /// Same for multiplication.
SMULO, UMULO, SMULO, UMULO,
// Simple binary floating point operators. /// Simple binary floating point operators.
FADD, FSUB, FMUL, FMA, FDIV, FREM, FADD, FSUB, FMUL, FMA, FDIV, FREM,
// FCOPYSIGN(X, Y) - Return the value of X with the sign of Y. NOTE: T /// FCOPYSIGN(X, Y) - Return the value of X with the sign of Y. NOTE:
his This
// DAG node does not require that X and Y have the same type, just that /// DAG node does not require that X and Y have the same type, just tha
they t the
// are both floating point. X and the result must have the same type. /// are both floating point. X and the result must have the same type.
// FCOPYSIGN(f32, f64) is allowed. /// FCOPYSIGN(f32, f64) is allowed.
FCOPYSIGN, FCOPYSIGN,
// INT = FGETSIGN(FP) - Return the sign bit of the specified floating p /// INT = FGETSIGN(FP) - Return the sign bit of the specified floating
oint point
// value as an integer 0/1 value. /// value as an integer 0/1 value.
FGETSIGN, FGETSIGN,
/// BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the /// BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the
/// specified, possibly variable, elements. The number of elements is /// specified, possibly variable, elements. The number of elements is
/// required to be a power of two. The types of the operands must all be /// required to be a power of two. The types of the operands must all be
/// the same and must match the vector element type, except that intege r /// the same and must match the vector element type, except that intege r
/// types are allowed to be larger than the element type, in which case /// types are allowed to be larger than the element type, in which case
/// the operands are implicitly truncated. /// the operands are implicitly truncated.
BUILD_VECTOR, BUILD_VECTOR,
skipping to change at line 295 skipping to change at line 301
VECTOR_SHUFFLE, VECTOR_SHUFFLE,
/// SCALAR_TO_VECTOR(VAL) - This represents the operation of loading a /// SCALAR_TO_VECTOR(VAL) - This represents the operation of loading a
/// scalar value into element 0 of the resultant vector type. The top /// scalar value into element 0 of the resultant vector type. The top
/// elements 1 to N-1 of the N-element vector are undefined. The type /// elements 1 to N-1 of the N-element vector are undefined. The type
/// of the operand must match the vector element type, except when they /// of the operand must match the vector element type, except when they
/// are integer types. In this case the operand is allowed to be wider /// are integer types. In this case the operand is allowed to be wider
/// than the vector element type, and is implicitly truncated to it. /// than the vector element type, and is implicitly truncated to it.
SCALAR_TO_VECTOR, SCALAR_TO_VECTOR,
// MULHU/MULHS - Multiply high - Multiply two integers of type iN, prod /// MULHU/MULHS - Multiply high - Multiply two integers of type iN,
ucing /// producing an unsigned/signed value of type i[2*N], then return the
// an unsigned/signed value of type i[2*N], then return the top part. top
/// part.
MULHU, MULHS, MULHU, MULHS,
/// Bitwise operators - logical and, logical or, logical xor. /// Bitwise operators - logical and, logical or, logical xor.
AND, OR, XOR, AND, OR, XOR,
/// Shift and rotation operations. After legalization, the type of the /// Shift and rotation operations. After legalization, the type of the
/// shift amount is known to be TLI.getShiftAmountTy(). Before legaliz ation /// shift amount is known to be TLI.getShiftAmountTy(). Before legaliz ation
/// the shift amount can be any type, but care must be taken to ensure it is /// the shift amount can be any type, but care must be taken to ensure it is
/// large enough. TLI.getShiftAmountTy() is i8 on some targets, but be fore /// large enough. TLI.getShiftAmountTy() is i8 on some targets, but be fore
/// legalization, types like i1024 can occur and i8 doesn't have enough bits /// legalization, types like i1024 can occur and i8 doesn't have enough bits
/// to represent the shift amount. By convention, DAGCombine and /// to represent the shift amount. By convention, DAGCombine and
/// SelectionDAGBuilder forces these shift amounts to i32 for simplicit y. /// SelectionDAGBuilder forces these shift amounts to i32 for simplicit y.
///
SHL, SRA, SRL, ROTL, ROTR, SHL, SRA, SRL, ROTL, ROTR,
/// Byte Swap and Counting operators. /// Byte Swap and Counting operators.
BSWAP, CTTZ, CTLZ, CTPOP, BSWAP, CTTZ, CTLZ, CTPOP,
/// Bit counting operators with an undefined result for zero inputs. /// Bit counting operators with an undefined result for zero inputs.
CTTZ_ZERO_UNDEF, CTLZ_ZERO_UNDEF, CTTZ_ZERO_UNDEF, CTLZ_ZERO_UNDEF,
// Select(COND, TRUEVAL, FALSEVAL). If the type of the boolean COND is /// Select(COND, TRUEVAL, FALSEVAL). If the type of the boolean COND i
not s not
// i1 then the high bits must conform to getBooleanContents. /// i1 then the high bits must conform to getBooleanContents.
SELECT, SELECT,
// Select with a vector condition (op #0) and two vector operands (ops /// Select with a vector condition (op #0) and two vector operands (ops
#1 #1
// and #2), returning a vector result. All vectors have the same lengt /// and #2), returning a vector result. All vectors have the same leng
h. th.
// Much like the scalar select and setcc, each bit in the condition sel /// Much like the scalar select and setcc, each bit in the condition se
ects lects
// whether the corresponding result element is taken from op #1 or op # /// whether the corresponding result element is taken from op #1 or op
2. #2.
// At first, the VSELECT condition is of vXi1 type. Later, targets may /// At first, the VSELECT condition is of vXi1 type. Later, targets may
change /// change the condition type in order to match the VSELECT node using
// the condition type in order to match the VSELECT node using a a patt a
ern. /// pattern. The condition follows the BooleanContent format of the tar
// The condition follows the BooleanContent format of the target. get.
VSELECT, VSELECT,
// Select with condition operator - This selects between a true value a /// Select with condition operator - This selects between a true value
nd and
// a false value (ops #2 and #3) based on the boolean result of compari /// a false value (ops #2 and #3) based on the boolean result of compar
ng ing
// the lhs and rhs (ops #0 and #1) of a conditional expression with the /// the lhs and rhs (ops #0 and #1) of a conditional expression with th
// condition code in op #4, a CondCodeSDNode. e
/// condition code in op #4, a CondCodeSDNode.
SELECT_CC, SELECT_CC,
// SetCC operator - This evaluates to a true value iff the condition is /// SetCC operator - This evaluates to a true value iff the condition i
// true. If the result value type is not i1 then the high bits conform s
// to getBooleanContents. The operands to this are the left and right /// true. If the result value type is not i1 then the high bits confor
// operands to compare (ops #0, and #1) and the condition code to compa m
re /// to getBooleanContents. The operands to this are the left and right
// them with (op #2) as a CondCodeSDNode. If the operands are vector ty /// operands to compare (ops #0, and #1) and the condition code to comp
pes are
// then the result type must also be a vector type. /// them with (op #2) as a CondCodeSDNode. If the operands are vector t
ypes
/// then the result type must also be a vector type.
SETCC, SETCC,
// SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expande /// SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expand
d ed
// integer shift operations, just like ADD/SUB_PARTS. The operation /// integer shift operations, just like ADD/SUB_PARTS. The operation
// ordering is: /// ordering is:
// [Lo,Hi] = op [LoLHS,HiLHS], Amt /// [Lo,Hi] = op [LoLHS,HiLHS], Amt
SHL_PARTS, SRA_PARTS, SRL_PARTS, SHL_PARTS, SRA_PARTS, SRL_PARTS,
// Conversion operators. These are all single input single output /// Conversion operators. These are all single input single output
// operations. For all of these, the result type must be strictly /// operations. For all of these, the result type must be strictly
// wider or narrower (depending on the operation) than the source /// wider or narrower (depending on the operation) than the source
// type. /// type.
// SIGN_EXTEND - Used for integer types, replicating the sign bit /// SIGN_EXTEND - Used for integer types, replicating the sign bit
// into new bits. /// into new bits.
SIGN_EXTEND, SIGN_EXTEND,
// ZERO_EXTEND - Used for integer types, zeroing the new bits. /// ZERO_EXTEND - Used for integer types, zeroing the new bits.
ZERO_EXTEND, ZERO_EXTEND,
// ANY_EXTEND - Used for integer types. The high bits are undefined. /// ANY_EXTEND - Used for integer types. The high bits are undefined.
ANY_EXTEND, ANY_EXTEND,
// TRUNCATE - Completely drop the high bits. /// TRUNCATE - Completely drop the high bits.
TRUNCATE, TRUNCATE,
// [SU]INT_TO_FP - These operators convert integers (whose interpreted /// [SU]INT_TO_FP - These operators convert integers (whose interpreted
sign sign
// depends on the first letter) to floating point. /// depends on the first letter) to floating point.
SINT_TO_FP, SINT_TO_FP,
UINT_TO_FP, UINT_TO_FP,
// SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair /// SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pai
to r to
// sign extend a small value in a large integer register (e.g. sign /// sign extend a small value in a large integer register (e.g. sign
// extending the low 8 bits of a 32-bit register to fill the top 24 bit /// extending the low 8 bits of a 32-bit register to fill the top 24 bi
s ts
// with the 7th bit). The size of the smaller type is indicated by the /// with the 7th bit). The size of the smaller type is indicated by th
1th e 1th
// operand, a ValueType node. /// operand, a ValueType node.
SIGN_EXTEND_INREG, SIGN_EXTEND_INREG,
/// FP_TO_[US]INT - Convert a floating point value to a signed or unsig ned /// FP_TO_[US]INT - Convert a floating point value to a signed or unsig ned
/// integer. /// integer.
FP_TO_SINT, FP_TO_SINT,
FP_TO_UINT, FP_TO_UINT,
/// X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type /// X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type
/// down to the precision of the destination VT. TRUNC is a flag, whic h is /// down to the precision of the destination VT. TRUNC is a flag, whic h is
/// always an integer that is zero or one. If TRUNC is 0, this is a /// always an integer that is zero or one. If TRUNC is 0, this is a
/// normal rounding, if it is 1, this FP_ROUND is known to not change t he /// normal rounding, if it is 1, this FP_ROUND is known to not change t he
/// value of Y. /// value of Y.
/// ///
/// The TRUNC = 1 case is used in cases where we know that the value wi ll /// The TRUNC = 1 case is used in cases where we know that the value wi ll
/// not be modified by the node, because Y is not using any of the extr a /// not be modified by the node, because Y is not using any of the extr a
/// precision of source type. This allows certain transformations like /// precision of source type. This allows certain transformations like
/// FP_EXTEND(FP_ROUND(X,1)) -> X which are not safe for /// FP_EXTEND(FP_ROUND(X,1)) -> X which are not safe for
/// FP_EXTEND(FP_ROUND(X,0)) because the extra bits aren't removed. /// FP_EXTEND(FP_ROUND(X,0)) because the extra bits aren't removed.
FP_ROUND, FP_ROUND,
// FLT_ROUNDS_ - Returns current rounding mode: /// FLT_ROUNDS_ - Returns current rounding mode:
// -1 Undefined /// -1 Undefined
// 0 Round to 0 /// 0 Round to 0
// 1 Round to nearest /// 1 Round to nearest
// 2 Round to +inf /// 2 Round to +inf
// 3 Round to -inf /// 3 Round to -inf
FLT_ROUNDS_, FLT_ROUNDS_,
/// X = FP_ROUND_INREG(Y, VT) - This operator takes an FP register, and /// X = FP_ROUND_INREG(Y, VT) - This operator takes an FP register, and
/// rounds it to a floating point value. It then promotes it and retur ns it /// rounds it to a floating point value. It then promotes it and retur ns it
/// in a register of the same size. This operation effectively just /// in a register of the same size. This operation effectively just
/// discards excess precision. The type to round down to is specified by /// discards excess precision. The type to round down to is specified by
/// the VT operand, a VTSDNode. /// the VT operand, a VTSDNode.
FP_ROUND_INREG, FP_ROUND_INREG,
/// X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type. /// X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
FP_EXTEND, FP_EXTEND,
// BITCAST - This operator converts between integer, vector and FP /// BITCAST - This operator converts between integer, vector and FP
// values, as if the value was stored to memory with one type and loade /// values, as if the value was stored to memory with one type and load
d ed
// from the same address with the other type (or equivalently for vecto /// from the same address with the other type (or equivalently for vect
r or
// format conversions, etc). The source and result are required to hav /// format conversions, etc). The source and result are required to ha
e ve
// the same bit size (e.g. f32 <-> i32). This can also be used for /// the same bit size (e.g. f32 <-> i32). This can also be used for
// int-to-int or fp-to-fp conversions, but that is a noop, deleted by /// int-to-int or fp-to-fp conversions, but that is a noop, deleted by
// getNode(). /// getNode().
BITCAST, BITCAST,
// CONVERT_RNDSAT - This operator is used to support various conversion /// CONVERT_RNDSAT - This operator is used to support various conversio
s ns
// between various types (float, signed, unsigned and vectors of those /// between various types (float, signed, unsigned and vectors of those
// types) with rounding and saturation. NOTE: Avoid using this operator /// types) with rounding and saturation. NOTE: Avoid using this operato
as r as
// most target don't support it and the operator might be removed in th /// most target don't support it and the operator might be removed in t
e he
// future. It takes the following arguments: /// future. It takes the following arguments:
// 0) value /// 0) value
// 1) dest type (type to convert to) /// 1) dest type (type to convert to)
// 2) src type (type to convert from) /// 2) src type (type to convert from)
// 3) rounding imm /// 3) rounding imm
// 4) saturation imm /// 4) saturation imm
// 5) ISD::CvtCode indicating the type of conversion to do /// 5) ISD::CvtCode indicating the type of conversion to do
CONVERT_RNDSAT, CONVERT_RNDSAT,
// FP16_TO_FP32, FP32_TO_FP16 - These operators are used to perform /// FP16_TO_FP32, FP32_TO_FP16 - These operators are used to perform
// promotions and truncation for half-precision (16 bit) floating /// promotions and truncation for half-precision (16 bit) floating
// numbers. We need special nodes since FP16 is a storage-only type wit /// numbers. We need special nodes since FP16 is a storage-only type wi
h th
// special semantics of operations. /// special semantics of operations.
FP16_TO_FP32, FP32_TO_FP16, FP16_TO_FP32, FP32_TO_FP16,
// FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, /// FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW,
// FLOG, FLOG2, FLOG10, FEXP, FEXP2, /// FLOG, FLOG2, FLOG10, FEXP, FEXP2,
// FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR - Perform various unary flo /// FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR - Perform various unary
ating /// floating point operations. These are inspired by libm.
// point operations. These are inspired by libm.
FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW,
FLOG, FLOG2, FLOG10, FEXP, FEXP2, FLOG, FLOG2, FLOG10, FEXP, FEXP2,
FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR, FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR,
// LOAD and STORE have token chains as their first operand, then the sa /// LOAD and STORE have token chains as their first operand, then the s
me ame
// operands as an LLVM load/store instruction, then an offset node that /// operands as an LLVM load/store instruction, then an offset node tha
// is added / subtracted from the base pointer to form the address (for t
// indexed memory ops). /// is added / subtracted from the base pointer to form the address (fo
r
/// indexed memory ops).
LOAD, STORE, LOAD, STORE,
// DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack alig /// DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack ali
ned gned
// to a specified boundary. This node always has two return values: a /// to a specified boundary. This node always has two return values: a
new new
// stack pointer value and a chain. The first operand is the token chai /// stack pointer value and a chain. The first operand is the token cha
n, in,
// the second is the number of bytes to allocate, and the third is the /// the second is the number of bytes to allocate, and the third is the
// alignment boundary. The size is guaranteed to be a multiple of the /// alignment boundary. The size is guaranteed to be a multiple of the
stack /// stack alignment, and the alignment is guaranteed to be bigger than
// alignment, and the alignment is guaranteed to be bigger than the sta the
ck /// stack alignment (if required) or 0 to get standard stack alignment.
// alignment (if required) or 0 to get standard stack alignment.
DYNAMIC_STACKALLOC, DYNAMIC_STACKALLOC,
// Control flow instructions. These all have token chains. /// Control flow instructions. These all have token chains.
// BR - Unconditional branch. The first operand is the chain /// BR - Unconditional branch. The first operand is the chain
// operand, the second is the MBB to branch to. /// operand, the second is the MBB to branch to.
BR, BR,
// BRIND - Indirect branch. The first operand is the chain, the second /// BRIND - Indirect branch. The first operand is the chain, the secon
// is the value to branch to, which must be of the same type as the tar d
get's /// is the value to branch to, which must be of the same type as the
// pointer type. /// target's pointer type.
BRIND, BRIND,
// BR_JT - Jumptable branch. The first operand is the chain, the second /// BR_JT - Jumptable branch. The first operand is the chain, the secon
// is the jumptable index, the last one is the jumptable entry index. d
/// is the jumptable index, the last one is the jumptable entry index.
BR_JT, BR_JT,
// BRCOND - Conditional branch. The first operand is the chain, the /// BRCOND - Conditional branch. The first operand is the chain, the
// second is the condition, the third is the block to branch to if the /// second is the condition, the third is the block to branch to if the
// condition is true. If the type of the condition is not i1, then the /// condition is true. If the type of the condition is not i1, then th
// high bits must conform to getBooleanContents. e
/// high bits must conform to getBooleanContents.
BRCOND, BRCOND,
// BR_CC - Conditional branch. The behavior is like that of SELECT_CC, /// BR_CC - Conditional branch. The behavior is like that of SELECT_CC
in , in
// that the condition is represented as condition code, and two nodes t /// that the condition is represented as condition code, and two nodes
o to
// compare, rather than as a combined SetCC node. The operands in orde /// compare, rather than as a combined SetCC node. The operands in ord
r are er
// chain, cc, lhs, rhs, block to branch to if condition is true. /// are chain, cc, lhs, rhs, block to branch to if condition is true.
BR_CC, BR_CC,
// INLINEASM - Represents an inline asm block. This node always has tw /// INLINEASM - Represents an inline asm block. This node always has t
o wo
// return values: a chain and a flag result. The inputs are as follows /// return values: a chain and a flag result. The inputs are as follow
: s:
// Operand #0 : Input chain. /// Operand #0 : Input chain.
// Operand #1 : a ExternalSymbolSDNode with a pointer to the asm st /// Operand #1 : a ExternalSymbolSDNode with a pointer to the asm st
ring. ring.
// Operand #2 : a MDNodeSDNode with the !srcloc metadata. /// Operand #2 : a MDNodeSDNode with the !srcloc metadata.
// Operand #3 : HasSideEffect, IsAlignStack bits. /// Operand #3 : HasSideEffect, IsAlignStack bits.
// After this, it is followed by a list of operands with this format: /// After this, it is followed by a list of operands with this format
// ConstantSDNode: Flags that encode whether it is a mem or not, th :
e /// ConstantSDNode: Flags that encode whether it is a mem or not, t
// of operands that follow, etc. See InlineAsm.h. he
// ... however many operands ... /// of operands that follow, etc. See InlineAsm.h.
// Operand #last: Optional, an incoming flag. /// ... however many operands ...
// /// Operand #last: Optional, an incoming flag.
// The variable width operands are required to represent target address ///
ing /// The variable width operands are required to represent target addres
// modes as a single "operand", even though they may have multiple sing
// SDOperands. /// modes as a single "operand", even though they may have multiple
/// SDOperands.
INLINEASM, INLINEASM,
// EH_LABEL - Represents a label in mid basic block used to track /// EH_LABEL - Represents a label in mid basic block used to track
// locations needed for debug and exception handling tables. These nod /// locations needed for debug and exception handling tables. These no
es des
// take a chain as input and return a chain. /// take a chain as input and return a chain.
EH_LABEL, EH_LABEL,
// STACKSAVE - STACKSAVE has one operand, an input chain. It produces /// STACKSAVE - STACKSAVE has one operand, an input chain. It produces
a a
// value, the same type as the pointer type for the system, and an outp /// value, the same type as the pointer type for the system, and an out
ut put
// chain. /// chain.
STACKSAVE, STACKSAVE,
// STACKRESTORE has two operands, an input chain and a pointer to resto /// STACKRESTORE has two operands, an input chain and a pointer to rest
re to ore
// it returns an output chain. /// to it returns an output chain.
STACKRESTORE, STACKRESTORE,
// CALLSEQ_START/CALLSEQ_END - These operators mark the beginning and e /// CALLSEQ_START/CALLSEQ_END - These operators mark the beginning and
nd of end
// a call sequence, and carry arbitrary information that target might w /// of a call sequence, and carry arbitrary information that target mig
ant ht
// to know. The first operand is a chain, the rest are specified by th /// want to know. The first operand is a chain, the rest are specified
e by
// target and not touched by the DAG optimizers. /// the target and not touched by the DAG optimizers.
// CALLSEQ_START..CALLSEQ_END pairs may not be nested. /// CALLSEQ_START..CALLSEQ_END pairs may not be nested.
CALLSEQ_START, // Beginning of a call sequence CALLSEQ_START, // Beginning of a call sequence
CALLSEQ_END, // End of a call sequence CALLSEQ_END, // End of a call sequence
// VAARG - VAARG has four operands: an input chain, a pointer, a SRCVAL /// VAARG - VAARG has four operands: an input chain, a pointer, a SRCVA
UE, LUE,
// and the alignment. It returns a pair of values: the vaarg value and /// and the alignment. It returns a pair of values: the vaarg value and
a a
// new chain. /// new chain.
VAARG, VAARG,
// VACOPY - VACOPY has five operands: an input chain, a destination poi /// VACOPY - VACOPY has 5 operands: an input chain, a destination point
nter, er,
// a source pointer, a SRCVALUE for the destination, and a SRCVALUE for /// a source pointer, a SRCVALUE for the destination, and a SRCVALUE fo
the r the
// source. /// source.
VACOPY, VACOPY,
// VAEND, VASTART - VAEND and VASTART have three operands: an input cha /// VAEND, VASTART - VAEND and VASTART have three operands: an input ch
in, a ain,
// pointer, and a SRCVALUE. /// pointer, and a SRCVALUE.
VAEND, VASTART, VAEND, VASTART,
// SRCVALUE - This is a node type that holds a Value* that is used to /// SRCVALUE - This is a node type that holds a Value* that is used to
// make reference to a value in the LLVM IR. /// make reference to a value in the LLVM IR.
SRCVALUE, SRCVALUE,
// MDNODE_SDNODE - This is a node that holdes an MDNode*, which is used /// MDNODE_SDNODE - This is a node that holdes an MDNode*, which is use
to d to
// reference metadata in the IR. /// reference metadata in the IR.
MDNODE_SDNODE, MDNODE_SDNODE,
// PCMARKER - This corresponds to the pcmarker intrinsic. /// PCMARKER - This corresponds to the pcmarker intrinsic.
PCMARKER, PCMARKER,
// READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsi /// READCYCLECOUNTER - This corresponds to the readcyclecounter intrins
c. ic.
// The only operand is a chain and a value and a chain are produced. T /// The only operand is a chain and a value and a chain are produced.
he The
// value is the contents of the architecture specific cycle counter lik /// value is the contents of the architecture specific cycle counter li
e ke
// register (or other high accuracy low latency clock source) /// register (or other high accuracy low latency clock source)
READCYCLECOUNTER, READCYCLECOUNTER,
// HANDLENODE node - Used as a handle for various purposes. /// HANDLENODE node - Used as a handle for various purposes.
HANDLENODE, HANDLENODE,
// INIT_TRAMPOLINE - This corresponds to the init_trampoline intrinsic. /// INIT_TRAMPOLINE - This corresponds to the init_trampoline intrinsic
It . It
// takes as input a token chain, the pointer to the trampoline, the poi /// takes as input a token chain, the pointer to the trampoline, the po
nter inter
// to the nested function, the pointer to pass for the 'nest' parameter /// to the nested function, the pointer to pass for the 'nest' paramete
, a r, a
// SRCVALUE for the trampoline and another for the nested function (all /// SRCVALUE for the trampoline and another for the nested function
owing /// (allowing targets to access the original Function*).
// targets to access the original Function*). It produces a token chai /// It produces a token chain as output.
n as
// output.
INIT_TRAMPOLINE, INIT_TRAMPOLINE,
// ADJUST_TRAMPOLINE - This corresponds to the adjust_trampoline intrin /// ADJUST_TRAMPOLINE - This corresponds to the adjust_trampoline intri
sic. nsic.
// It takes a pointer to the trampoline and produces a (possibly) new /// It takes a pointer to the trampoline and produces a (possibly) new
// pointer to the same trampoline with platform-specific adjustments /// pointer to the same trampoline with platform-specific adjustments
// applied. The pointer it returns points to an executable block of co /// applied. The pointer it returns points to an executable block of c
de. ode.
ADJUST_TRAMPOLINE, ADJUST_TRAMPOLINE,
// TRAP - Trapping instruction /// TRAP - Trapping instruction
TRAP, TRAP,
// PREFETCH - This corresponds to a prefetch intrinsic. It takes chains /// DEBUGTRAP - Trap intended to get the attention of a debugger.
are DEBUGTRAP,
// their first operand. The other operands are the address to prefetch,
// read / write specifier, locality specifier and instruction / data ca /// PREFETCH - This corresponds to a prefetch intrinsic. The first oper
che and
// specifier. /// is the chain. The other operands are the address to prefetch,
/// read / write specifier, locality specifier and instruction / data c
ache
/// specifier.
PREFETCH, PREFETCH,
// OUTCHAIN = MEMBARRIER(INCHAIN, load-load, load-store, store-load, /// OUTCHAIN = MEMBARRIER(INCHAIN, load-load, load-store, store-load,
// store-store, device) /// store-store, device)
// This corresponds to the memory.barrier intrinsic. /// This corresponds to the memory.barrier intrinsic.
// it takes an input chain, 4 operands to specify the type of barrier, /// it takes an input chain, 4 operands to specify the type of barrier,
an an
// operand specifying if the barrier applies to device and uncached mem /// operand specifying if the barrier applies to device and uncached me
ory mory
// and produces an output chain. /// and produces an output chain.
MEMBARRIER, MEMBARRIER,
// OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) /// OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope)
// This corresponds to the fence instruction. It takes an input chain, /// This corresponds to the fence instruction. It takes an input chain,
and and
// two integer constants: an AtomicOrdering and a SynchronizationScope. /// two integer constants: an AtomicOrdering and a SynchronizationScope
.
ATOMIC_FENCE, ATOMIC_FENCE,
// Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr) /// Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr)
// This corresponds to "load atomic" instruction. /// This corresponds to "load atomic" instruction.
ATOMIC_LOAD, ATOMIC_LOAD,
// OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr, val) /// OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr, val)
// This corresponds to "store atomic" instruction. /// This corresponds to "store atomic" instruction.
ATOMIC_STORE, ATOMIC_STORE,
// Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) /// Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap)
// This corresponds to the cmpxchg instruction. /// This corresponds to the cmpxchg instruction.
ATOMIC_CMP_SWAP, ATOMIC_CMP_SWAP,
// Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) /// Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt)
// Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amt) /// Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amt)
// These correspond to the atomicrmw instruction. /// These correspond to the atomicrmw instruction.
ATOMIC_SWAP, ATOMIC_SWAP,
ATOMIC_LOAD_ADD, ATOMIC_LOAD_ADD,
ATOMIC_LOAD_SUB, ATOMIC_LOAD_SUB,
ATOMIC_LOAD_AND, ATOMIC_LOAD_AND,
ATOMIC_LOAD_OR, ATOMIC_LOAD_OR,
ATOMIC_LOAD_XOR, ATOMIC_LOAD_XOR,
ATOMIC_LOAD_NAND, ATOMIC_LOAD_NAND,
ATOMIC_LOAD_MIN, ATOMIC_LOAD_MIN,
ATOMIC_LOAD_MAX, ATOMIC_LOAD_MAX,
ATOMIC_LOAD_UMIN, ATOMIC_LOAD_UMIN,
ATOMIC_LOAD_UMAX, ATOMIC_LOAD_UMAX,
/// This corresponds to the llvm.lifetime.* intrinsics. The first opera
nd
/// is the chain and the second operand is the alloca pointer.
LIFETIME_START, LIFETIME_END,
/// BUILTIN_OP_END - This must be the last enum value in this list. /// BUILTIN_OP_END - This must be the last enum value in this list.
/// The target-specific pre-isel opcode values start here. /// The target-specific pre-isel opcode values start here.
BUILTIN_OP_END BUILTIN_OP_END
}; };
/// FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations /// FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations
/// which do not reference a specific memory location should be less than /// which do not reference a specific memory location should be less than
/// this value. Those that do must not be less than this value, and can /// this value. Those that do must not be less than this value, and can
/// be used with SelectionDAG::getMemIntrinsicNode. /// be used with SelectionDAG::getMemIntrinsicNode.
static const int FIRST_TARGET_MEMORY_OPCODE = BUILTIN_OP_END+150; static const int FIRST_TARGET_MEMORY_OPCODE = BUILTIN_OP_END+150;
skipping to change at line 793 skipping to change at line 806
/// getSetCCAndOperation - Return the result of a logical AND between /// getSetCCAndOperation - Return the result of a logical AND between
/// different comparisons of identical values: ((X op1 Y) & (X op2 Y)). This /// different comparisons of identical values: ((X op1 Y) & (X op2 Y)). This
/// function returns SETCC_INVALID if it is not possible to represent the /// function returns SETCC_INVALID if it is not possible to represent the
/// resultant comparison. /// resultant comparison.
CondCode getSetCCAndOperation(CondCode Op1, CondCode Op2, bool isInteger) ; CondCode getSetCCAndOperation(CondCode Op1, CondCode Op2, bool isInteger) ;
//===-------------------------------------------------------------------- ===// //===-------------------------------------------------------------------- ===//
/// CvtCode enum - This enum defines the various converts CONVERT_RNDSAT /// CvtCode enum - This enum defines the various converts CONVERT_RNDSAT
/// supports. /// supports.
enum CvtCode { enum CvtCode {
CVT_FF, // Float from Float CVT_FF, /// Float from Float
CVT_FS, // Float from Signed CVT_FS, /// Float from Signed
CVT_FU, // Float from Unsigned CVT_FU, /// Float from Unsigned
CVT_SF, // Signed from Float CVT_SF, /// Signed from Float
CVT_UF, // Unsigned from Float CVT_UF, /// Unsigned from Float
CVT_SS, // Signed from Signed CVT_SS, /// Signed from Signed
CVT_SU, // Signed from Unsigned CVT_SU, /// Signed from Unsigned
CVT_US, // Unsigned from Signed CVT_US, /// Unsigned from Signed
CVT_UU, // Unsigned from Unsigned CVT_UU, /// Unsigned from Unsigned
CVT_INVALID // Marker - Invalid opcode CVT_INVALID /// Marker - Invalid opcode
}; };
} // end llvm::ISD namespace } // end llvm::ISD namespace
} // end llvm namespace } // end llvm namespace
#endif #endif
 End of changes. 87 change blocks. 
403 lines changed or deleted 425 lines changed or added


 IVUsers.h   IVUsers.h 
skipping to change at line 31 skipping to change at line 31
namespace llvm { namespace llvm {
class DominatorTree; class DominatorTree;
class Instruction; class Instruction;
class Value; class Value;
class IVUsers; class IVUsers;
class ScalarEvolution; class ScalarEvolution;
class SCEV; class SCEV;
class IVUsers; class IVUsers;
class TargetData; class DataLayout;
/// IVStrideUse - Keep track of one use of a strided induction variable. /// IVStrideUse - Keep track of one use of a strided induction variable.
/// The Expr member keeps track of the expression, User is the actual user /// The Expr member keeps track of the expression, User is the actual user
/// instruction of the operand, and 'OperandValToReplace' is the operand of /// instruction of the operand, and 'OperandValToReplace' is the operand of
/// the User that is the use. /// the User that is the use.
class IVStrideUse : public CallbackVH, public ilist_node<IVStrideUse> { class IVStrideUse : public CallbackVH, public ilist_node<IVStrideUse> {
friend class IVUsers; friend class IVUsers;
public: public:
IVStrideUse(IVUsers *P, Instruction* U, Value *O) IVStrideUse(IVUsers *P, Instruction* U, Value *O)
: CallbackVH(U), Parent(P), OperandValToReplace(O) { : CallbackVH(U), Parent(P), OperandValToReplace(O) {
skipping to change at line 126 skipping to change at line 126
private: private:
mutable ilist_node<IVStrideUse> Sentinel; mutable ilist_node<IVStrideUse> Sentinel;
}; };
class IVUsers : public LoopPass { class IVUsers : public LoopPass {
friend class IVStrideUse; friend class IVStrideUse;
Loop *L; Loop *L;
LoopInfo *LI; LoopInfo *LI;
DominatorTree *DT; DominatorTree *DT;
ScalarEvolution *SE; ScalarEvolution *SE;
TargetData *TD; DataLayout *TD;
SmallPtrSet<Instruction*,16> Processed; SmallPtrSet<Instruction*,16> Processed;
/// IVUses - A list of all tracked IV uses of induction variable expressi ons /// IVUses - A list of all tracked IV uses of induction variable expressi ons
/// we are interested in. /// we are interested in.
ilist<IVStrideUse> IVUses; ilist<IVStrideUse> IVUses;
virtual void getAnalysisUsage(AnalysisUsage &AU) const; virtual void getAnalysisUsage(AnalysisUsage &AU) const;
virtual bool runOnLoop(Loop *L, LPPassManager &LPM); virtual bool runOnLoop(Loop *L, LPPassManager &LPM);
 End of changes. 2 change blocks. 
2 lines changed or deleted 2 lines changed or added


 ImmutableList.h   ImmutableList.h 
skipping to change at line 36 skipping to change at line 36
template <typename T> template <typename T>
class ImmutableListImpl : public FoldingSetNode { class ImmutableListImpl : public FoldingSetNode {
T Head; T Head;
const ImmutableListImpl* Tail; const ImmutableListImpl* Tail;
ImmutableListImpl(const T& head, const ImmutableListImpl* tail = 0) ImmutableListImpl(const T& head, const ImmutableListImpl* tail = 0)
: Head(head), Tail(tail) {} : Head(head), Tail(tail) {}
friend class ImmutableListFactory<T>; friend class ImmutableListFactory<T>;
// Do not implement. void operator=(const ImmutableListImpl&) LLVM_DELETED_FUNCTION;
void operator=(const ImmutableListImpl&); ImmutableListImpl(const ImmutableListImpl&) LLVM_DELETED_FUNCTION;
ImmutableListImpl(const ImmutableListImpl&);
public: public:
const T& getHead() const { return Head; } const T& getHead() const { return Head; }
const ImmutableListImpl* getTail() const { return Tail; } const ImmutableListImpl* getTail() const { return Tail; }
static inline void Profile(FoldingSetNodeID& ID, const T& H, static inline void Profile(FoldingSetNodeID& ID, const T& H,
const ImmutableListImpl* L){ const ImmutableListImpl* L){
ID.AddPointer(L); ID.AddPointer(L);
ID.Add(H); ID.Add(H);
} }
 End of changes. 1 change blocks. 
3 lines changed or deleted 2 lines changed or added


 ImmutableMap.h   ImmutableMap.h 
skipping to change at line 124 skipping to change at line 124
ImmutableMap remove(ImmutableMap Old, key_type_ref K) { ImmutableMap remove(ImmutableMap Old, key_type_ref K) {
TreeTy *T = F.remove(Old.Root,K); TreeTy *T = F.remove(Old.Root,K);
return ImmutableMap(Canonicalize ? F.getCanonicalTree(T): T); return ImmutableMap(Canonicalize ? F.getCanonicalTree(T): T);
} }
typename TreeTy::Factory *getTreeFactory() const { typename TreeTy::Factory *getTreeFactory() const {
return const_cast<typename TreeTy::Factory *>(&F); return const_cast<typename TreeTy::Factory *>(&F);
} }
private: private:
Factory(const Factory& RHS); // DO NOT IMPLEMENT Factory(const Factory& RHS) LLVM_DELETED_FUNCTION;
void operator=(const Factory& RHS); // DO NOT IMPLEMENT void operator=(const Factory& RHS) LLVM_DELETED_FUNCTION;
}; };
bool contains(key_type_ref K) const { bool contains(key_type_ref K) const {
return Root ? Root->contains(K) : false; return Root ? Root->contains(K) : false;
} }
bool operator==(const ImmutableMap &RHS) const { bool operator==(const ImmutableMap &RHS) const {
return Root && RHS.Root ? Root->isEqual(*RHS.Root) : Root == RHS.Root; return Root && RHS.Root ? Root->isEqual(*RHS.Root) : Root == RHS.Root;
} }
 End of changes. 1 change blocks. 
2 lines changed or deleted 2 lines changed or added


 ImmutableSet.h   ImmutableSet.h 
skipping to change at line 25 skipping to change at line 25
#define LLVM_ADT_IMSET_H #define LLVM_ADT_IMSET_H
#include "llvm/Support/Allocator.h" #include "llvm/Support/Allocator.h"
#include "llvm/ADT/DenseMap.h" #include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/FoldingSet.h" #include "llvm/ADT/FoldingSet.h"
#include "llvm/Support/DataTypes.h" #include "llvm/Support/DataTypes.h"
#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/ErrorHandling.h"
#include <cassert> #include <cassert>
#include <functional> #include <functional>
#include <vector> #include <vector>
#include <stdio.h>
namespace llvm { namespace llvm {
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// Immutable AVL-Tree Definition. // Immutable AVL-Tree Definition.
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
template <typename ImutInfo> class ImutAVLFactory; template <typename ImutInfo> class ImutAVLFactory;
template <typename ImutInfo> class ImutIntervalAVLFactory; template <typename ImutInfo> class ImutIntervalAVLFactory;
template <typename ImutInfo> class ImutAVLTreeInOrderIterator; template <typename ImutInfo> class ImutAVLTreeInOrderIterator;
skipping to change at line 93 skipping to change at line 92
T = T->getRight(); T = T->getRight();
} }
return NULL; return NULL;
} }
/// getMaxElement - Find the subtree associated with the highest ranged /// getMaxElement - Find the subtree associated with the highest ranged
/// key value. /// key value.
ImutAVLTree* getMaxElement() { ImutAVLTree* getMaxElement() {
ImutAVLTree *T = this; ImutAVLTree *T = this;
ImutAVLTree *Right = T->getRight(); ImutAVLTree *Right = T->getRight();
while (Right) { T = right; right = T->getRight(); } while (Right) { T = Right; Right = T->getRight(); }
return T; return T;
} }
/// size - Returns the number of nodes in the tree, which includes /// size - Returns the number of nodes in the tree, which includes
/// both leaves and non-leaf nodes. /// both leaves and non-leaf nodes.
unsigned size() const { unsigned size() const {
unsigned n = 1; unsigned n = 1;
if (const ImutAVLTree* L = getLeft()) if (const ImutAVLTree* L = getLeft())
n += L->size(); n += L->size();
if (const ImutAVLTree* R = getRight()) if (const ImutAVLTree* R = getRight())
skipping to change at line 433 skipping to change at line 432
//===--------------------------------------------------===// //===--------------------------------------------------===//
bool isEmpty(TreeTy* T) const { return !T; } bool isEmpty(TreeTy* T) const { return !T; }
unsigned getHeight(TreeTy* T) const { return T ? T->getHeight() : 0; } unsigned getHeight(TreeTy* T) const { return T ? T->getHeight() : 0; }
TreeTy* getLeft(TreeTy* T) const { return T->getLeft(); } TreeTy* getLeft(TreeTy* T) const { return T->getLeft(); }
TreeTy* getRight(TreeTy* T) const { return T->getRight(); } TreeTy* getRight(TreeTy* T) const { return T->getRight(); }
value_type_ref getValue(TreeTy* T) const { return T->value; } value_type_ref getValue(TreeTy* T) const { return T->value; }
// Make sure the index is not the Tombstone or Entry key of the DenseMap. // Make sure the index is not the Tombstone or Entry key of the DenseMap.
static inline unsigned maskCacheIndex(unsigned I) { static inline unsigned maskCacheIndex(unsigned I) {
return (I & ~0x02); return (I & ~0x02);
} }
unsigned incrementHeight(TreeTy* L, TreeTy* R) const { unsigned incrementHeight(TreeTy* L, TreeTy* R) const {
unsigned hl = getHeight(L); unsigned hl = getHeight(L);
unsigned hr = getHeight(R); unsigned hr = getHeight(R);
return (hl > hr ? hl : hr) + 1; return (hl > hr ? hl : hr) + 1;
} }
static bool compareTreeWithSection(TreeTy* T, static bool compareTreeWithSection(TreeTy* T,
typename TreeTy::iterator& TI, typename TreeTy::iterator& TI,
skipping to change at line 471 skipping to change at line 470
//===--------------------------------------------------===// //===--------------------------------------------------===//
TreeTy* createNode(TreeTy* L, value_type_ref V, TreeTy* R) { TreeTy* createNode(TreeTy* L, value_type_ref V, TreeTy* R) {
BumpPtrAllocator& A = getAllocator(); BumpPtrAllocator& A = getAllocator();
TreeTy* T; TreeTy* T;
if (!freeNodes.empty()) { if (!freeNodes.empty()) {
T = freeNodes.back(); T = freeNodes.back();
freeNodes.pop_back(); freeNodes.pop_back();
assert(T != L); assert(T != L);
assert(T != R); assert(T != R);
} } else {
else {
T = (TreeTy*) A.Allocate<TreeTy>(); T = (TreeTy*) A.Allocate<TreeTy>();
} }
new (T) TreeTy(this, L, R, V, incrementHeight(L,R)); new (T) TreeTy(this, L, R, V, incrementHeight(L,R));
createdNodes.push_back(T); createdNodes.push_back(T);
return T; return T;
} }
TreeTy* createNode(TreeTy* newLeft, TreeTy* oldTree, TreeTy* newRight) { TreeTy* createNode(TreeTy* newLeft, TreeTy* oldTree, TreeTy* newRight) {
return createNode(newLeft, getValue(oldTree), newRight); return createNode(newLeft, getValue(oldTree), newRight);
} }
skipping to change at line 515 skipping to change at line 513
if (getHeight(LL) >= getHeight(LR)) if (getHeight(LL) >= getHeight(LR))
return createNode(LL, L, createNode(LR,V,R)); return createNode(LL, L, createNode(LR,V,R));
assert(!isEmpty(LR) && "LR cannot be empty because it has a height >= 1"); assert(!isEmpty(LR) && "LR cannot be empty because it has a height >= 1");
TreeTy *LRL = getLeft(LR); TreeTy *LRL = getLeft(LR);
TreeTy *LRR = getRight(LR); TreeTy *LRR = getRight(LR);
return createNode(createNode(LL,L,LRL), LR, createNode(LRR,V,R)); return createNode(createNode(LL,L,LRL), LR, createNode(LRR,V,R));
} }
else if (hr > hl + 2) {
if (hr > hl + 2) {
assert(!isEmpty(R) && "Right tree cannot be empty to have a height >= 2"); assert(!isEmpty(R) && "Right tree cannot be empty to have a height >= 2");
TreeTy *RL = getLeft(R); TreeTy *RL = getLeft(R);
TreeTy *RR = getRight(R); TreeTy *RR = getRight(R);
if (getHeight(RR) >= getHeight(RL)) if (getHeight(RR) >= getHeight(RL))
return createNode(createNode(L,V,RL), R, RR); return createNode(createNode(L,V,RL), R, RR);
assert(!isEmpty(RL) && "RL cannot be empty because it has a height >= 1"); assert(!isEmpty(RL) && "RL cannot be empty because it has a height >= 1");
TreeTy *RLL = getLeft(RL); TreeTy *RLL = getLeft(RL);
TreeTy *RLR = getRight(RL); TreeTy *RLR = getRight(RL);
return createNode(createNode(L,V,RLL), RL, createNode(RLR,R,RR)); return createNode(createNode(L,V,RLL), RL, createNode(RLR,R,RR));
} }
else
return createNode(L,V,R); return createNode(L,V,R);
} }
/// add_internal - Creates a new tree that includes the specified /// add_internal - Creates a new tree that includes the specified
/// data and the data from the original tree. If the original tree /// data and the data from the original tree. If the original tree
/// already contained the data item, the original tree is returned. /// already contained the data item, the original tree is returned.
TreeTy* add_internal(value_type_ref V, TreeTy* T) { TreeTy* add_internal(value_type_ref V, TreeTy* T) {
if (isEmpty(T)) if (isEmpty(T))
return createNode(T, V, T); return createNode(T, V, T);
assert(!T->isMutable()); assert(!T->isMutable());
skipping to change at line 669 skipping to change at line 668
inline ImutAVLTreeGenericIterator() {} inline ImutAVLTreeGenericIterator() {}
inline ImutAVLTreeGenericIterator(const TreeTy* Root) { inline ImutAVLTreeGenericIterator(const TreeTy* Root) {
if (Root) stack.push_back(reinterpret_cast<uintptr_t>(Root)); if (Root) stack.push_back(reinterpret_cast<uintptr_t>(Root));
} }
TreeTy* operator*() const { TreeTy* operator*() const {
assert(!stack.empty()); assert(!stack.empty());
return reinterpret_cast<TreeTy*>(stack.back() & ~Flags); return reinterpret_cast<TreeTy*>(stack.back() & ~Flags);
} }
uintptr_t getVisitState() { uintptr_t getVisitState() const {
assert(!stack.empty()); assert(!stack.empty());
return stack.back() & Flags; return stack.back() & Flags;
} }
bool atEnd() const { return stack.empty(); } bool atEnd() const { return stack.empty(); }
bool atBeginning() const { bool atBeginning() const {
return stack.size() == 1 && getVisitState() == VisitedNone; return stack.size() == 1 && getVisitState() == VisitedNone;
} }
skipping to change at line 1008 skipping to change at line 1007
return ImmutableSet(Canonicalize ? F.getCanonicalTree(NewT) : NewT); return ImmutableSet(Canonicalize ? F.getCanonicalTree(NewT) : NewT);
} }
BumpPtrAllocator& getAllocator() { return F.getAllocator(); } BumpPtrAllocator& getAllocator() { return F.getAllocator(); }
typename TreeTy::Factory *getTreeFactory() const { typename TreeTy::Factory *getTreeFactory() const {
return const_cast<typename TreeTy::Factory *>(&F); return const_cast<typename TreeTy::Factory *>(&F);
} }
private: private:
Factory(const Factory& RHS); // DO NOT IMPLEMENT Factory(const Factory& RHS) LLVM_DELETED_FUNCTION;
void operator=(const Factory& RHS); // DO NOT IMPLEMENT void operator=(const Factory& RHS) LLVM_DELETED_FUNCTION;
}; };
friend class Factory; friend class Factory;
/// Returns true if the set contains the specified value. /// Returns true if the set contains the specified value.
bool contains(value_type_ref V) const { bool contains(value_type_ref V) const {
return Root ? Root->contains(V) : false; return Root ? Root->contains(V) : false;
} }
bool operator==(const ImmutableSet &RHS) const { bool operator==(const ImmutableSet &RHS) const {
 End of changes. 8 change blocks. 
11 lines changed or deleted 10 lines changed or added


 IndexedMap.h   IndexedMap.h 
skipping to change at line 23 skipping to change at line 23
// can be provided to be used as a "does not exist" indicator in the // can be provided to be used as a "does not exist" indicator in the
// map. A member function grow() is provided that given the value of // map. A member function grow() is provided that given the value of
// the maximally indexed key (the argument of the functor) makes sure // the maximally indexed key (the argument of the functor) makes sure
// the map has enough space for it. // the map has enough space for it.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_ADT_INDEXEDMAP_H #ifndef LLVM_ADT_INDEXEDMAP_H
#define LLVM_ADT_INDEXEDMAP_H #define LLVM_ADT_INDEXEDMAP_H
#include "llvm/ADT/STLExtras.h"
#include <cassert> #include <cassert>
#include <functional> #include <functional>
#include <vector> #include <vector>
namespace llvm { namespace llvm {
struct IdentityFunctor : public std::unary_function<unsigned, unsigned> { template <typename T, typename ToIndexT = llvm::identity<unsigned> >
unsigned operator()(unsigned Index) const {
return Index;
}
};
template <typename T, typename ToIndexT = IdentityFunctor>
class IndexedMap { class IndexedMap {
typedef typename ToIndexT::argument_type IndexT; typedef typename ToIndexT::argument_type IndexT;
typedef std::vector<T> StorageT; typedef std::vector<T> StorageT;
StorageT storage_; StorageT storage_;
T nullVal_; T nullVal_;
ToIndexT toIndex_; ToIndexT toIndex_;
public: public:
IndexedMap() : nullVal_(T()) { } IndexedMap() : nullVal_(T()) { }
 End of changes. 2 change blocks. 
7 lines changed or deleted 2 lines changed or added


 InitializePasses.h   InitializePasses.h 
skipping to change at line 69 skipping to change at line 69
void initializeTarget(PassRegistry&); void initializeTarget(PassRegistry&);
void initializeAAEvalPass(PassRegistry&); void initializeAAEvalPass(PassRegistry&);
void initializeADCEPass(PassRegistry&); void initializeADCEPass(PassRegistry&);
void initializeAliasAnalysisAnalysisGroup(PassRegistry&); void initializeAliasAnalysisAnalysisGroup(PassRegistry&);
void initializeAliasAnalysisCounterPass(PassRegistry&); void initializeAliasAnalysisCounterPass(PassRegistry&);
void initializeAliasDebuggerPass(PassRegistry&); void initializeAliasDebuggerPass(PassRegistry&);
void initializeAliasSetPrinterPass(PassRegistry&); void initializeAliasSetPrinterPass(PassRegistry&);
void initializeAlwaysInlinerPass(PassRegistry&); void initializeAlwaysInlinerPass(PassRegistry&);
void initializeArgPromotionPass(PassRegistry&); void initializeArgPromotionPass(PassRegistry&);
void initializeBarrierNoopPass(PassRegistry&);
void initializeBasicAliasAnalysisPass(PassRegistry&); void initializeBasicAliasAnalysisPass(PassRegistry&);
void initializeBasicCallGraphPass(PassRegistry&); void initializeBasicCallGraphPass(PassRegistry&);
void initializeBlockExtractorPassPass(PassRegistry&); void initializeBlockExtractorPassPass(PassRegistry&);
void initializeBlockFrequencyInfoPass(PassRegistry&); void initializeBlockFrequencyInfoPass(PassRegistry&);
void initializeBlockPlacementPass(PassRegistry&); void initializeBlockPlacementPass(PassRegistry&);
void initializeBoundsCheckingPass(PassRegistry&);
void initializeBranchFolderPassPass(PassRegistry&); void initializeBranchFolderPassPass(PassRegistry&);
void initializeBranchProbabilityInfoPass(PassRegistry&); void initializeBranchProbabilityInfoPass(PassRegistry&);
void initializeBreakCriticalEdgesPass(PassRegistry&); void initializeBreakCriticalEdgesPass(PassRegistry&);
void initializeCFGOnlyPrinterPass(PassRegistry&); void initializeCFGOnlyPrinterPass(PassRegistry&);
void initializeCFGOnlyViewerPass(PassRegistry&); void initializeCFGOnlyViewerPass(PassRegistry&);
void initializeCFGPrinterPass(PassRegistry&); void initializeCFGPrinterPass(PassRegistry&);
void initializeCFGSimplifyPassPass(PassRegistry&); void initializeCFGSimplifyPassPass(PassRegistry&);
void initializeCFGViewerPass(PassRegistry&); void initializeCFGViewerPass(PassRegistry&);
void initializeCalculateSpillWeightsPass(PassRegistry&); void initializeCalculateSpillWeightsPass(PassRegistry&);
void initializeCallGraphAnalysisGroup(PassRegistry&); void initializeCallGraphAnalysisGroup(PassRegistry&);
void initializeCodeGenPreparePass(PassRegistry&); void initializeCodeGenPreparePass(PassRegistry&);
void initializeCodePlacementOptPass(PassRegistry&); void initializeCodePlacementOptPass(PassRegistry&);
void initializeConstantMergePass(PassRegistry&); void initializeConstantMergePass(PassRegistry&);
void initializeConstantPropagationPass(PassRegistry&); void initializeConstantPropagationPass(PassRegistry&);
void initializeMachineCopyPropagationPass(PassRegistry&); void initializeMachineCopyPropagationPass(PassRegistry&);
void initializeCostModelAnalysisPass(PassRegistry&);
void initializeCorrelatedValuePropagationPass(PassRegistry&); void initializeCorrelatedValuePropagationPass(PassRegistry&);
void initializeDAEPass(PassRegistry&); void initializeDAEPass(PassRegistry&);
void initializeDAHPass(PassRegistry&); void initializeDAHPass(PassRegistry&);
void initializeDCEPass(PassRegistry&); void initializeDCEPass(PassRegistry&);
void initializeDSEPass(PassRegistry&); void initializeDSEPass(PassRegistry&);
void initializeDeadInstEliminationPass(PassRegistry&); void initializeDeadInstEliminationPass(PassRegistry&);
void initializeDeadMachineInstructionElimPass(PassRegistry&); void initializeDeadMachineInstructionElimPass(PassRegistry&);
void initializeDependenceAnalysisPass(PassRegistry&);
void initializeDomOnlyPrinterPass(PassRegistry&); void initializeDomOnlyPrinterPass(PassRegistry&);
void initializeDomOnlyViewerPass(PassRegistry&); void initializeDomOnlyViewerPass(PassRegistry&);
void initializeDomPrinterPass(PassRegistry&); void initializeDomPrinterPass(PassRegistry&);
void initializeDomViewerPass(PassRegistry&); void initializeDomViewerPass(PassRegistry&);
void initializeDominanceFrontierPass(PassRegistry&); void initializeDominanceFrontierPass(PassRegistry&);
void initializeDominatorTreePass(PassRegistry&); void initializeDominatorTreePass(PassRegistry&);
void initializeEarlyIfConverterPass(PassRegistry&);
void initializeEdgeBundlesPass(PassRegistry&); void initializeEdgeBundlesPass(PassRegistry&);
void initializeEdgeProfilerPass(PassRegistry&); void initializeEdgeProfilerPass(PassRegistry&);
void initializeExpandPostRAPass(PassRegistry&); void initializeExpandPostRAPass(PassRegistry&);
void initializePathProfilerPass(PassRegistry&); void initializePathProfilerPass(PassRegistry&);
void initializeGCOVProfilerPass(PassRegistry&); void initializeGCOVProfilerPass(PassRegistry&);
void initializeAddressSanitizerPass(PassRegistry&); void initializeAddressSanitizerPass(PassRegistry&);
void initializeThreadSanitizerPass(PassRegistry&); void initializeThreadSanitizerPass(PassRegistry&);
void initializeEarlyCSEPass(PassRegistry&); void initializeEarlyCSEPass(PassRegistry&);
void initializeExpandISelPseudosPass(PassRegistry&); void initializeExpandISelPseudosPass(PassRegistry&);
void initializeFindUsedTypesPass(PassRegistry&); void initializeFindUsedTypesPass(PassRegistry&);
skipping to change at line 138 skipping to change at line 143
void initializeInternalizePassPass(PassRegistry&); void initializeInternalizePassPass(PassRegistry&);
void initializeIntervalPartitionPass(PassRegistry&); void initializeIntervalPartitionPass(PassRegistry&);
void initializeJumpThreadingPass(PassRegistry&); void initializeJumpThreadingPass(PassRegistry&);
void initializeLCSSAPass(PassRegistry&); void initializeLCSSAPass(PassRegistry&);
void initializeLICMPass(PassRegistry&); void initializeLICMPass(PassRegistry&);
void initializeLazyValueInfoPass(PassRegistry&); void initializeLazyValueInfoPass(PassRegistry&);
void initializeLibCallAliasAnalysisPass(PassRegistry&); void initializeLibCallAliasAnalysisPass(PassRegistry&);
void initializeLintPass(PassRegistry&); void initializeLintPass(PassRegistry&);
void initializeLiveDebugVariablesPass(PassRegistry&); void initializeLiveDebugVariablesPass(PassRegistry&);
void initializeLiveIntervalsPass(PassRegistry&); void initializeLiveIntervalsPass(PassRegistry&);
void initializeLiveRegMatrixPass(PassRegistry&);
void initializeLiveStacksPass(PassRegistry&); void initializeLiveStacksPass(PassRegistry&);
void initializeLiveVariablesPass(PassRegistry&); void initializeLiveVariablesPass(PassRegistry&);
void initializeLoaderPassPass(PassRegistry&); void initializeLoaderPassPass(PassRegistry&);
void initializeProfileMetadataLoaderPassPass(PassRegistry&);
void initializePathProfileLoaderPassPass(PassRegistry&); void initializePathProfileLoaderPassPass(PassRegistry&);
void initializeLocalStackSlotPassPass(PassRegistry&); void initializeLocalStackSlotPassPass(PassRegistry&);
void initializeLoopDeletionPass(PassRegistry&); void initializeLoopDeletionPass(PassRegistry&);
void initializeLoopDependenceAnalysisPass(PassRegistry&);
void initializeLoopExtractorPass(PassRegistry&); void initializeLoopExtractorPass(PassRegistry&);
void initializeLoopInfoPass(PassRegistry&); void initializeLoopInfoPass(PassRegistry&);
void initializeLoopInstSimplifyPass(PassRegistry&); void initializeLoopInstSimplifyPass(PassRegistry&);
void initializeLoopRotatePass(PassRegistry&); void initializeLoopRotatePass(PassRegistry&);
void initializeLoopSimplifyPass(PassRegistry&); void initializeLoopSimplifyPass(PassRegistry&);
void initializeLoopStrengthReducePass(PassRegistry&); void initializeLoopStrengthReducePass(PassRegistry&);
void initializeGlobalMergePass(PassRegistry&); void initializeGlobalMergePass(PassRegistry&);
void initializeLoopUnrollPass(PassRegistry&); void initializeLoopUnrollPass(PassRegistry&);
void initializeLoopUnswitchPass(PassRegistry&); void initializeLoopUnswitchPass(PassRegistry&);
void initializeLoopIdiomRecognizePass(PassRegistry&); void initializeLoopIdiomRecognizePass(PassRegistry&);
skipping to change at line 166 skipping to change at line 172
void initializeLowerExpectIntrinsicPass(PassRegistry&); void initializeLowerExpectIntrinsicPass(PassRegistry&);
void initializeLowerIntrinsicsPass(PassRegistry&); void initializeLowerIntrinsicsPass(PassRegistry&);
void initializeLowerInvokePass(PassRegistry&); void initializeLowerInvokePass(PassRegistry&);
void initializeLowerSwitchPass(PassRegistry&); void initializeLowerSwitchPass(PassRegistry&);
void initializeMachineBlockFrequencyInfoPass(PassRegistry&); void initializeMachineBlockFrequencyInfoPass(PassRegistry&);
void initializeMachineBlockPlacementPass(PassRegistry&); void initializeMachineBlockPlacementPass(PassRegistry&);
void initializeMachineBlockPlacementStatsPass(PassRegistry&); void initializeMachineBlockPlacementStatsPass(PassRegistry&);
void initializeMachineBranchProbabilityInfoPass(PassRegistry&); void initializeMachineBranchProbabilityInfoPass(PassRegistry&);
void initializeMachineCSEPass(PassRegistry&); void initializeMachineCSEPass(PassRegistry&);
void initializeMachineDominatorTreePass(PassRegistry&); void initializeMachineDominatorTreePass(PassRegistry&);
void initializeMachinePostDominatorTreePass(PassRegistry&);
void initializeMachineLICMPass(PassRegistry&); void initializeMachineLICMPass(PassRegistry&);
void initializeMachineLoopInfoPass(PassRegistry&); void initializeMachineLoopInfoPass(PassRegistry&);
void initializeMachineLoopRangesPass(PassRegistry&); void initializeMachineLoopRangesPass(PassRegistry&);
void initializeMachineModuleInfoPass(PassRegistry&); void initializeMachineModuleInfoPass(PassRegistry&);
void initializeMachineSchedulerPass(PassRegistry&); void initializeMachineSchedulerPass(PassRegistry&);
void initializeMachineSinkingPass(PassRegistry&); void initializeMachineSinkingPass(PassRegistry&);
void initializeMachineTraceMetricsPass(PassRegistry&);
void initializeMachineVerifierPassPass(PassRegistry&); void initializeMachineVerifierPassPass(PassRegistry&);
void initializeMemCpyOptPass(PassRegistry&); void initializeMemCpyOptPass(PassRegistry&);
void initializeMemDepPrinterPass(PassRegistry&); void initializeMemDepPrinterPass(PassRegistry&);
void initializeMemoryDependenceAnalysisPass(PassRegistry&); void initializeMemoryDependenceAnalysisPass(PassRegistry&);
void initializeMetaRenamerPass(PassRegistry&);
void initializeMergeFunctionsPass(PassRegistry&); void initializeMergeFunctionsPass(PassRegistry&);
void initializeModuleDebugInfoPrinterPass(PassRegistry&); void initializeModuleDebugInfoPrinterPass(PassRegistry&);
void initializeNoAAPass(PassRegistry&); void initializeNoAAPass(PassRegistry&);
void initializeNoProfileInfoPass(PassRegistry&); void initializeNoProfileInfoPass(PassRegistry&);
void initializeNoPathProfileInfoPass(PassRegistry&); void initializeNoPathProfileInfoPass(PassRegistry&);
void initializeObjCARCAliasAnalysisPass(PassRegistry&); void initializeObjCARCAliasAnalysisPass(PassRegistry&);
void initializeObjCARCAPElimPass(PassRegistry&); void initializeObjCARCAPElimPass(PassRegistry&);
void initializeObjCARCExpandPass(PassRegistry&); void initializeObjCARCExpandPass(PassRegistry&);
void initializeObjCARCContractPass(PassRegistry&); void initializeObjCARCContractPass(PassRegistry&);
void initializeObjCARCOptPass(PassRegistry&); void initializeObjCARCOptPass(PassRegistry&);
skipping to change at line 217 skipping to change at line 226
void initializeProfileVerifierPassPass(PassRegistry&); void initializeProfileVerifierPassPass(PassRegistry&);
void initializePromotePassPass(PassRegistry&); void initializePromotePassPass(PassRegistry&);
void initializePruneEHPass(PassRegistry&); void initializePruneEHPass(PassRegistry&);
void initializeReassociatePass(PassRegistry&); void initializeReassociatePass(PassRegistry&);
void initializeRegToMemPass(PassRegistry&); void initializeRegToMemPass(PassRegistry&);
void initializeRegionInfoPass(PassRegistry&); void initializeRegionInfoPass(PassRegistry&);
void initializeRegionOnlyPrinterPass(PassRegistry&); void initializeRegionOnlyPrinterPass(PassRegistry&);
void initializeRegionOnlyViewerPass(PassRegistry&); void initializeRegionOnlyViewerPass(PassRegistry&);
void initializeRegionPrinterPass(PassRegistry&); void initializeRegionPrinterPass(PassRegistry&);
void initializeRegionViewerPass(PassRegistry&); void initializeRegionViewerPass(PassRegistry&);
void initializeRenderMachineFunctionPass(PassRegistry&);
void initializeSCCPPass(PassRegistry&); void initializeSCCPPass(PassRegistry&);
void initializeSROAPass(PassRegistry&);
void initializeSROA_DTPass(PassRegistry&); void initializeSROA_DTPass(PassRegistry&);
void initializeSROA_SSAUpPass(PassRegistry&); void initializeSROA_SSAUpPass(PassRegistry&);
void initializeScalarEvolutionAliasAnalysisPass(PassRegistry&); void initializeScalarEvolutionAliasAnalysisPass(PassRegistry&);
void initializeScalarEvolutionPass(PassRegistry&); void initializeScalarEvolutionPass(PassRegistry&);
void initializeSimpleInlinerPass(PassRegistry&); void initializeSimpleInlinerPass(PassRegistry&);
void initializeRegisterCoalescerPass(PassRegistry&); void initializeRegisterCoalescerPass(PassRegistry&);
void initializeSimplifyLibCallsPass(PassRegistry&); void initializeSimplifyLibCallsPass(PassRegistry&);
void initializeSingleLoopExtractorPass(PassRegistry&); void initializeSingleLoopExtractorPass(PassRegistry&);
void initializeSinkingPass(PassRegistry&); void initializeSinkingPass(PassRegistry&);
void initializeSlotIndexesPass(PassRegistry&); void initializeSlotIndexesPass(PassRegistry&);
void initializeSpillPlacementPass(PassRegistry&); void initializeSpillPlacementPass(PassRegistry&);
void initializeStackProtectorPass(PassRegistry&); void initializeStackProtectorPass(PassRegistry&);
void initializeStackColoringPass(PassRegistry&);
void initializeStackSlotColoringPass(PassRegistry&); void initializeStackSlotColoringPass(PassRegistry&);
void initializeStripDeadDebugInfoPass(PassRegistry&); void initializeStripDeadDebugInfoPass(PassRegistry&);
void initializeStripDeadPrototypesPassPass(PassRegistry&); void initializeStripDeadPrototypesPassPass(PassRegistry&);
void initializeStripDebugDeclarePass(PassRegistry&); void initializeStripDebugDeclarePass(PassRegistry&);
void initializeStripNonDebugSymbolsPass(PassRegistry&); void initializeStripNonDebugSymbolsPass(PassRegistry&);
void initializeStripSymbolsPass(PassRegistry&); void initializeStripSymbolsPass(PassRegistry&);
void initializeStrongPHIEliminationPass(PassRegistry&); void initializeStrongPHIEliminationPass(PassRegistry&);
void initializeTailCallElimPass(PassRegistry&); void initializeTailCallElimPass(PassRegistry&);
void initializeTailDuplicatePassPass(PassRegistry&); void initializeTailDuplicatePassPass(PassRegistry&);
void initializeTargetPassConfigPass(PassRegistry&); void initializeTargetPassConfigPass(PassRegistry&);
void initializeTargetDataPass(PassRegistry&); void initializeDataLayoutPass(PassRegistry&);
void initializeTargetTransformInfoPass(PassRegistry&);
void initializeTargetLibraryInfoPass(PassRegistry&); void initializeTargetLibraryInfoPass(PassRegistry&);
void initializeTwoAddressInstructionPassPass(PassRegistry&); void initializeTwoAddressInstructionPassPass(PassRegistry&);
void initializeTypeBasedAliasAnalysisPass(PassRegistry&); void initializeTypeBasedAliasAnalysisPass(PassRegistry&);
void initializeUnifyFunctionExitNodesPass(PassRegistry&); void initializeUnifyFunctionExitNodesPass(PassRegistry&);
void initializeUnreachableBlockElimPass(PassRegistry&); void initializeUnreachableBlockElimPass(PassRegistry&);
void initializeUnreachableMachineBlockElimPass(PassRegistry&); void initializeUnreachableMachineBlockElimPass(PassRegistry&);
void initializeVerifierPass(PassRegistry&); void initializeVerifierPass(PassRegistry&);
void initializeVirtRegMapPass(PassRegistry&); void initializeVirtRegMapPass(PassRegistry&);
void initializeVirtRegRewriterPass(PassRegistry&);
void initializeInstSimplifierPass(PassRegistry&); void initializeInstSimplifierPass(PassRegistry&);
void initializeUnpackMachineBundlesPass(PassRegistry&); void initializeUnpackMachineBundlesPass(PassRegistry&);
void initializeFinalizeMachineBundlesPass(PassRegistry&); void initializeFinalizeMachineBundlesPass(PassRegistry&);
void initializeLoopVectorizePass(PassRegistry&);
void initializeBBVectorizePass(PassRegistry&); void initializeBBVectorizePass(PassRegistry&);
void initializeMachineFunctionPrinterPassPass(PassRegistry&);
} }
#endif #endif
 End of changes. 18 change blocks. 
3 lines changed or deleted 17 lines changed or added


 InlineAsm.h   InlineAsm.h 
skipping to change at line 36 skipping to change at line 36
class FunctionType; class FunctionType;
class Module; class Module;
struct InlineAsmKeyType; struct InlineAsmKeyType;
template<class ValType, class ValRefType, class TypeClass, class ConstantCl ass, template<class ValType, class ValRefType, class TypeClass, class ConstantCl ass,
bool HasLargeKey> bool HasLargeKey>
class ConstantUniqueMap; class ConstantUniqueMap;
template<class ConstantClass, class TypeClass, class ValType> template<class ConstantClass, class TypeClass, class ValType>
struct ConstantCreator; struct ConstantCreator;
class InlineAsm : public Value { class InlineAsm : public Value {
public:
enum AsmDialect {
AD_ATT,
AD_Intel
};
private:
friend struct ConstantCreator<InlineAsm, PointerType, InlineAsmKeyType>; friend struct ConstantCreator<InlineAsm, PointerType, InlineAsmKeyType>;
friend class ConstantUniqueMap<InlineAsmKeyType, const InlineAsmKeyType&, friend class ConstantUniqueMap<InlineAsmKeyType, const InlineAsmKeyType&,
PointerType, InlineAsm, false>; PointerType, InlineAsm, false>;
InlineAsm(const InlineAsm &); // do not implement InlineAsm(const InlineAsm &) LLVM_DELETED_FUNCTION;
void operator=(const InlineAsm&); // do not implement void operator=(const InlineAsm&) LLVM_DELETED_FUNCTION;
std::string AsmString, Constraints; std::string AsmString, Constraints;
bool HasSideEffects; bool HasSideEffects;
bool IsAlignStack; bool IsAlignStack;
AsmDialect Dialect;
InlineAsm(PointerType *Ty, const std::string &AsmString, InlineAsm(PointerType *Ty, const std::string &AsmString,
const std::string &Constraints, bool hasSideEffects, const std::string &Constraints, bool hasSideEffects,
bool isAlignStack); bool isAlignStack, AsmDialect asmDialect);
virtual ~InlineAsm(); virtual ~InlineAsm();
/// When the ConstantUniqueMap merges two types and makes two InlineAsms /// When the ConstantUniqueMap merges two types and makes two InlineAsms
/// identical, it destroys one of them with this method. /// identical, it destroys one of them with this method.
void destroyConstant(); void destroyConstant();
public: public:
/// InlineAsm::get - Return the specified uniqued inline asm string. /// InlineAsm::get - Return the specified uniqued inline asm string.
/// ///
static InlineAsm *get(FunctionType *Ty, StringRef AsmString, static InlineAsm *get(FunctionType *Ty, StringRef AsmString,
StringRef Constraints, bool hasSideEffects, StringRef Constraints, bool hasSideEffects,
bool isAlignStack = false); bool isAlignStack = false,
AsmDialect asmDialect = AD_ATT);
bool hasSideEffects() const { return HasSideEffects; } bool hasSideEffects() const { return HasSideEffects; }
bool isAlignStack() const { return IsAlignStack; } bool isAlignStack() const { return IsAlignStack; }
AsmDialect getDialect() const { return Dialect; }
/// getType - InlineAsm's are always pointers. /// getType - InlineAsm's are always pointers.
/// ///
PointerType *getType() const { PointerType *getType() const {
return reinterpret_cast<PointerType*>(Value::getType()); return reinterpret_cast<PointerType*>(Value::getType());
} }
/// getFunctionType - InlineAsm's are always pointers to functions. /// getFunctionType - InlineAsm's are always pointers to functions.
/// ///
FunctionType *getFunctionType() const; FunctionType *getFunctionType() const;
skipping to change at line 182 skipping to change at line 192
/// the constraint string itself isn't empty, there was an error parsing. /// the constraint string itself isn't empty, there was an error parsing.
static ConstraintInfoVector ParseConstraints(StringRef ConstraintString); static ConstraintInfoVector ParseConstraints(StringRef ConstraintString);
/// ParseConstraints - Parse the constraints of this inlineasm object, /// ParseConstraints - Parse the constraints of this inlineasm object,
/// returning them the same way that ParseConstraints(str) does. /// returning them the same way that ParseConstraints(str) does.
ConstraintInfoVector ParseConstraints() const { ConstraintInfoVector ParseConstraints() const {
return ParseConstraints(Constraints); return ParseConstraints(Constraints);
} }
// Methods for support type inquiry through isa, cast, and dyn_cast: // Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const InlineAsm *) { return true; }
static inline bool classof(const Value *V) { static inline bool classof(const Value *V) {
return V->getValueID() == Value::InlineAsmVal; return V->getValueID() == Value::InlineAsmVal;
} }
// These are helper methods for dealing with flags in the INLINEASM SDNod e // These are helper methods for dealing with flags in the INLINEASM SDNod e
// in the backend. // in the backend.
enum { enum {
// Fixed operands on an INLINEASM SDNode. // Fixed operands on an INLINEASM SDNode.
Op_InputChain = 0, Op_InputChain = 0,
Op_AsmString = 1, Op_AsmString = 1,
Op_MDNode = 2, Op_MDNode = 2,
Op_ExtraInfo = 3, // HasSideEffects, IsAlignStack Op_ExtraInfo = 3, // HasSideEffects, IsAlignStack, AsmDialect.
Op_FirstOperand = 4, Op_FirstOperand = 4,
// Fixed operands on an INLINEASM MachineInstr. // Fixed operands on an INLINEASM MachineInstr.
MIOp_AsmString = 0, MIOp_AsmString = 0,
MIOp_ExtraInfo = 1, // HasSideEffects, IsAlignStack MIOp_ExtraInfo = 1, // HasSideEffects, IsAlignStack, AsmDialect.
MIOp_FirstOperand = 2, MIOp_FirstOperand = 2,
// Interpretation of the MIOp_ExtraInfo bit field. // Interpretation of the MIOp_ExtraInfo bit field.
Extra_HasSideEffects = 1, Extra_HasSideEffects = 1,
Extra_IsAlignStack = 2, Extra_IsAlignStack = 2,
Extra_AsmDialect = 4,
Extra_MayLoad = 8,
Extra_MayStore = 16,
// Inline asm operands map to multiple SDNode / MachineInstr operands. // Inline asm operands map to multiple SDNode / MachineInstr operands.
// The first operand is an immediate describing the asm operand, the lo w // The first operand is an immediate describing the asm operand, the lo w
// bits is the kind: // bits is the kind:
Kind_RegUse = 1, // Input register, "r". Kind_RegUse = 1, // Input register, "r".
Kind_RegDef = 2, // Output register, "=r". Kind_RegDef = 2, // Output register, "=r".
Kind_RegDefEarlyClobber = 3, // Early-clobber output register, "=&r". Kind_RegDefEarlyClobber = 3, // Early-clobber output register, "=&r".
Kind_Clobber = 4, // Clobbered register, "~r". Kind_Clobber = 4, // Clobbered register, "~r".
Kind_Imm = 5, // Immediate. Kind_Imm = 5, // Immediate.
Kind_Mem = 6, // Memory operand, "m". Kind_Mem = 6, // Memory operand, "m".
 End of changes. 10 change blocks. 
7 lines changed or deleted 19 lines changed or added


 InlineCost.h   InlineCost.h 
skipping to change at line 29 skipping to change at line 29
#include "llvm/ADT/SmallPtrSet.h" #include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/ValueMap.h" #include "llvm/ADT/ValueMap.h"
#include "llvm/Analysis/CodeMetrics.h" #include "llvm/Analysis/CodeMetrics.h"
#include <cassert> #include <cassert>
#include <climits> #include <climits>
#include <vector> #include <vector>
namespace llvm { namespace llvm {
class CallSite; class CallSite;
class TargetData; class DataLayout;
namespace InlineConstants { namespace InlineConstants {
// Various magic constants used to adjust heuristics. // Various magic constants used to adjust heuristics.
const int InstrCost = 5; const int InstrCost = 5;
const int IndirectCallThreshold = 100; const int IndirectCallThreshold = 100;
const int CallPenalty = 25; const int CallPenalty = 25;
const int LastCallToStaticBonus = -15000; const int LastCallToStaticBonus = -15000;
const int ColdccPenalty = 2000; const int ColdccPenalty = 2000;
const int NoreturnPenalty = 10000; const int NoreturnPenalty = 10000;
/// Do not inline functions which allocate this many bytes on the stack
/// when the caller is recursive.
const unsigned TotalAllocaSizeRecursiveCaller = 1024;
} }
/// \brief Represents the cost of inlining a function. /// \brief Represents the cost of inlining a function.
/// ///
/// This supports special values for functions which should "always" or /// This supports special values for functions which should "always" or
/// "never" be inlined. Otherwise, the cost represents a unitless amount; /// "never" be inlined. Otherwise, the cost represents a unitless amount;
/// smaller values increase the likelihood of the function being inlined. /// smaller values increase the likelihood of the function being inlined.
/// ///
/// Objects of this type also provide the adjusted threshold for inlining /// Objects of this type also provide the adjusted threshold for inlining
/// based on the information available for a particular callsite. They ca n be /// based on the information available for a particular callsite. They ca n be
skipping to change at line 104 skipping to change at line 107
} }
/// \brief Get the cost delta from the threshold for inlining. /// \brief Get the cost delta from the threshold for inlining.
/// Only valid if the cost is of the variable kind. Returns a negative /// Only valid if the cost is of the variable kind. Returns a negative
/// value if the cost is too high to inline. /// value if the cost is too high to inline.
int getCostDelta() const { return Threshold - getCost(); } int getCostDelta() const { return Threshold - getCost(); }
}; };
/// InlineCostAnalyzer - Cost analyzer used by inliner. /// InlineCostAnalyzer - Cost analyzer used by inliner.
class InlineCostAnalyzer { class InlineCostAnalyzer {
// TargetData if available, or null. // DataLayout if available, or null.
const TargetData *TD; const DataLayout *TD;
public: public:
InlineCostAnalyzer(): TD(0) {} InlineCostAnalyzer(): TD(0) {}
void setTargetData(const TargetData *TData) { TD = TData; } void setDataLayout(const DataLayout *TData) { TD = TData; }
/// \brief Get an InlineCost object representing the cost of inlining t his /// \brief Get an InlineCost object representing the cost of inlining t his
/// callsite. /// callsite.
/// ///
/// Note that threshold is passed into this function. Only costs below the /// Note that threshold is passed into this function. Only costs below the
/// threshold are computed with any accuracy. The threshold can be used to /// threshold are computed with any accuracy. The threshold can be used to
/// bound the computation necessary to determine whether the cost is /// bound the computation necessary to determine whether the cost is
/// sufficiently low to warrant inlining. /// sufficiently low to warrant inlining.
InlineCost getInlineCost(CallSite CS, int Threshold); InlineCost getInlineCost(CallSite CS, int Threshold);
/// getCalledFunction - The heuristic used to determine if we should in line /// getCalledFunction - The heuristic used to determine if we should in line
/// the function call or not. The callee is explicitly specified, to a llow /// the function call or not. The callee is explicitly specified, to a llow
/// you to calculate the cost of inlining a function via a pointer. Th is /// you to calculate the cost of inlining a function via a pointer. Th is
/// behaves exactly as the version with no explicit callee parameter in all /// behaves exactly as the version with no explicit callee parameter in all
/// other respects. /// other respects.
// //
// Note: This is used by out-of-tree passes, please do not remove with out // Note: This is used by out-of-tree passes, please do not remove with out
// adding a replacement API. // adding a replacement API.
InlineCost getInlineCost(CallSite CS, Function *Callee, int Threshold); InlineCost getInlineCost(CallSite CS, Function *Callee, int Threshold);
}; };
/// callIsSmall - If a call is likely to lower to a single target instruc
tion,
/// or is otherwise deemed small return true.
bool callIsSmall(const Function *Callee);
} }
#endif #endif
 End of changes. 5 change blocks. 
9 lines changed or deleted 7 lines changed or added


 InlinerPass.h   InlinerPass.h 
skipping to change at line 24 skipping to change at line 24
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_TRANSFORMS_IPO_INLINERPASS_H #ifndef LLVM_TRANSFORMS_IPO_INLINERPASS_H
#define LLVM_TRANSFORMS_IPO_INLINERPASS_H #define LLVM_TRANSFORMS_IPO_INLINERPASS_H
#include "llvm/CallGraphSCCPass.h" #include "llvm/CallGraphSCCPass.h"
namespace llvm { namespace llvm {
class CallSite; class CallSite;
class TargetData; class DataLayout;
class InlineCost; class InlineCost;
template<class PtrType, unsigned SmallSize> template<class PtrType, unsigned SmallSize>
class SmallPtrSet; class SmallPtrSet;
/// Inliner - This class contains all of the helper code which is used to /// Inliner - This class contains all of the helper code which is used to
/// perform the inlining operations that do not depend on the policy. /// perform the inlining operations that do not depend on the policy.
/// ///
struct Inliner : public CallGraphSCCPass { struct Inliner : public CallGraphSCCPass {
explicit Inliner(char &ID); explicit Inliner(char &ID);
explicit Inliner(char &ID, int Threshold, bool InsertLifetime); explicit Inliner(char &ID, int Threshold, bool InsertLifetime);
 End of changes. 1 change blocks. 
1 lines changed or deleted 1 lines changed or added


 InstVisitor.h   InstVisitor.h 
skipping to change at line 15 skipping to change at line 15
// This file is distributed under the University of Illinois Open Source // This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details. // License. See LICENSE.TXT for details.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_SUPPORT_INSTVISITOR_H #ifndef LLVM_SUPPORT_INSTVISITOR_H
#define LLVM_SUPPORT_INSTVISITOR_H #define LLVM_SUPPORT_INSTVISITOR_H
#include "llvm/Function.h" #include "llvm/Function.h"
#include "llvm/Instructions.h" #include "llvm/Instructions.h"
#include "llvm/Intrinsics.h"
#include "llvm/IntrinsicInst.h"
#include "llvm/Module.h" #include "llvm/Module.h"
#include "llvm/Support/CallSite.h" #include "llvm/Support/CallSite.h"
#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/ErrorHandling.h"
namespace llvm { namespace llvm {
// We operate on opaque instruction classes, so forward declare all instruc tion // We operate on opaque instruction classes, so forward declare all instruc tion
// types now... // types now...
// //
#define HANDLE_INST(NUM, OPCODE, CLASS) class CLASS; #define HANDLE_INST(NUM, OPCODE, CLASS) class CLASS;
skipping to change at line 146 skipping to change at line 148
// //
void visitModule (Module &M) {} void visitModule (Module &M) {}
void visitFunction (Function &F) {} void visitFunction (Function &F) {}
void visitBasicBlock(BasicBlock &BB) {} void visitBasicBlock(BasicBlock &BB) {}
// Define instruction specific visitor functions that can be overridden t o // Define instruction specific visitor functions that can be overridden t o
// handle SPECIFIC instructions. These functions automatically define // handle SPECIFIC instructions. These functions automatically define
// visitMul to proxy to visitBinaryOperator for instance in case the user does // visitMul to proxy to visitBinaryOperator for instance in case the user does
// not need this generality. // not need this generality.
// //
// The one problem case we have to handle here though is that the PHINode // These functions can also implement fan-out, when a single opcode and
// class and opcode name are the exact same. Because of this, we cannot // instruction have multiple more specific Instruction subclasses. The Ca
// define visitPHINode (the inst version) to forward to visitPHINode (the ll
// generic version) without multiply defined symbols and recursion. To h // instruction currently supports this. We implement that by redirecting
andle that
// this, we do not autoexpand "Other" instructions, we do it manually. // instruction to a special delegation helper.
//
#define HANDLE_INST(NUM, OPCODE, CLASS) \ #define HANDLE_INST(NUM, OPCODE, CLASS) \
RetTy visit##OPCODE(CLASS &I) { DELEGATE(CLASS); } RetTy visit##OPCODE(CLASS &I) { \
if (NUM == Instruction::Call) \
return delegateCallInst(I); \
else \
DELEGATE(CLASS); \
}
#include "llvm/Instruction.def" #include "llvm/Instruction.def"
// Specific Instruction type classes... note that all of the casts are // Specific Instruction type classes... note that all of the casts are
// necessary because we use the instruction classes as opaque types... // necessary because we use the instruction classes as opaque types...
// //
RetTy visitReturnInst(ReturnInst &I) { DELEGATE(TerminatorInst );} RetTy visitReturnInst(ReturnInst &I) { DELEGATE(TerminatorInst );}
RetTy visitBranchInst(BranchInst &I) { DELEGATE(TerminatorInst );} RetTy visitBranchInst(BranchInst &I) { DELEGATE(TerminatorInst );}
RetTy visitSwitchInst(SwitchInst &I) { DELEGATE(TerminatorInst );} RetTy visitSwitchInst(SwitchInst &I) { DELEGATE(TerminatorInst );}
RetTy visitIndirectBrInst(IndirectBrInst &I) { DELEGATE(TerminatorInst );} RetTy visitIndirectBrInst(IndirectBrInst &I) { DELEGATE(TerminatorInst );}
RetTy visitResumeInst(ResumeInst &I) { DELEGATE(TerminatorInst );} RetTy visitResumeInst(ResumeInst &I) { DELEGATE(TerminatorInst );}
skipping to change at line 196 skipping to change at line 201
RetTy visitBitCastInst(BitCastInst &I) { DELEGATE(CastInst);} RetTy visitBitCastInst(BitCastInst &I) { DELEGATE(CastInst);}
RetTy visitSelectInst(SelectInst &I) { DELEGATE(Instruction);} RetTy visitSelectInst(SelectInst &I) { DELEGATE(Instruction);}
RetTy visitVAArgInst(VAArgInst &I) { DELEGATE(UnaryInstructi on);} RetTy visitVAArgInst(VAArgInst &I) { DELEGATE(UnaryInstructi on);}
RetTy visitExtractElementInst(ExtractElementInst &I) { DELEGATE(Instructi on);} RetTy visitExtractElementInst(ExtractElementInst &I) { DELEGATE(Instructi on);}
RetTy visitInsertElementInst(InsertElementInst &I) { DELEGATE(Instruction );} RetTy visitInsertElementInst(InsertElementInst &I) { DELEGATE(Instruction );}
RetTy visitShuffleVectorInst(ShuffleVectorInst &I) { DELEGATE(Instruction );} RetTy visitShuffleVectorInst(ShuffleVectorInst &I) { DELEGATE(Instruction );}
RetTy visitExtractValueInst(ExtractValueInst &I){ DELEGATE(UnaryInstructi on);} RetTy visitExtractValueInst(ExtractValueInst &I){ DELEGATE(UnaryInstructi on);}
RetTy visitInsertValueInst(InsertValueInst &I) { DELEGATE(Instruction); } RetTy visitInsertValueInst(InsertValueInst &I) { DELEGATE(Instruction); }
RetTy visitLandingPadInst(LandingPadInst &I) { DELEGATE(Instruction); } RetTy visitLandingPadInst(LandingPadInst &I) { DELEGATE(Instruction); }
// Handle the special instrinsic instruction classes.
RetTy visitDbgDeclareInst(DbgDeclareInst &I) { DELEGATE(DbgInfoIntrins
ic);}
RetTy visitDbgValueInst(DbgValueInst &I) { DELEGATE(DbgInfoIntrins
ic);}
RetTy visitDbgInfoIntrinsic(DbgInfoIntrinsic &I) { DELEGATE(IntrinsicInst
); }
RetTy visitMemSetInst(MemSetInst &I) { DELEGATE(MemIntrinsic);
}
RetTy visitMemCpyInst(MemCpyInst &I) { DELEGATE(MemTransferIns
t); }
RetTy visitMemMoveInst(MemMoveInst &I) { DELEGATE(MemTransferIns
t); }
RetTy visitMemTransferInst(MemTransferInst &I) { DELEGATE(MemIntrinsic);
}
RetTy visitMemIntrinsic(MemIntrinsic &I) { DELEGATE(IntrinsicInst)
; }
RetTy visitVAStartInst(VAStartInst &I) { DELEGATE(IntrinsicInst)
; }
RetTy visitVAEndInst(VAEndInst &I) { DELEGATE(IntrinsicInst)
; }
RetTy visitVACopyInst(VACopyInst &I) { DELEGATE(IntrinsicInst)
; }
RetTy visitIntrinsicInst(IntrinsicInst &I) { DELEGATE(CallInst); }
// Call and Invoke are slightly different as they delegate first through // Call and Invoke are slightly different as they delegate first through
// a generic CallSite visitor. // a generic CallSite visitor.
RetTy visitCallInst(CallInst &I) { RetTy visitCallInst(CallInst &I) {
return static_cast<SubClass*>(this)->visitCallSite(&I); return static_cast<SubClass*>(this)->visitCallSite(&I);
} }
RetTy visitInvokeInst(InvokeInst &I) { RetTy visitInvokeInst(InvokeInst &I) {
return static_cast<SubClass*>(this)->visitCallSite(&I); return static_cast<SubClass*>(this)->visitCallSite(&I);
} }
// Next level propagators: If the user does not overload a specific // Next level propagators: If the user does not overload a specific
skipping to change at line 235 skipping to change at line 254
DELEGATE(TerminatorInst); DELEGATE(TerminatorInst);
} }
// If the user wants a 'default' case, they can choose to override this // If the user wants a 'default' case, they can choose to override this
// function. If this function is not overloaded in the user's subclass, then // function. If this function is not overloaded in the user's subclass, then
// this instruction just gets ignored. // this instruction just gets ignored.
// //
// Note that you MUST override this function if your return type is not v oid. // Note that you MUST override this function if your return type is not v oid.
// //
void visitInstruction(Instruction &I) {} // Ignore unhandled instruction s void visitInstruction(Instruction &I) {} // Ignore unhandled instruction s
private:
// Special helper function to delegate to CallInst subclass visitors.
RetTy delegateCallInst(CallInst &I) {
if (const Function *F = I.getCalledFunction()) {
switch ((Intrinsic::ID)F->getIntrinsicID()) {
default: DELEGATE(IntrinsicInst);
case Intrinsic::dbg_declare: DELEGATE(DbgDeclareInst);
case Intrinsic::dbg_value: DELEGATE(DbgValueInst);
case Intrinsic::memcpy: DELEGATE(MemCpyInst);
case Intrinsic::memmove: DELEGATE(MemMoveInst);
case Intrinsic::memset: DELEGATE(MemSetInst);
case Intrinsic::vastart: DELEGATE(VAStartInst);
case Intrinsic::vaend: DELEGATE(VAEndInst);
case Intrinsic::vacopy: DELEGATE(VACopyInst);
case Intrinsic::not_intrinsic: break;
}
}
DELEGATE(CallInst);
}
// An overload that will never actually be called, it is used only from d
ead
// code in the dispatching from opcodes to instruction subclasses.
RetTy delegateCallInst(Instruction &I) {
llvm_unreachable("delegateCallInst called for non-CallInst");
}
}; };
#undef DELEGATE #undef DELEGATE
} // End llvm namespace } // End llvm namespace
#endif #endif
 End of changes. 5 change blocks. 
8 lines changed or deleted 66 lines changed or added


 InstrTypes.h   InstrTypes.h 
skipping to change at line 76 skipping to change at line 76
return getSuccessorV(idx); return getSuccessorV(idx);
} }
/// setSuccessor - Update the specified successor to point at the provide d /// setSuccessor - Update the specified successor to point at the provide d
/// block. /// block.
void setSuccessor(unsigned idx, BasicBlock *B) { void setSuccessor(unsigned idx, BasicBlock *B) {
setSuccessorV(idx, B); setSuccessorV(idx, B);
} }
// Methods for support type inquiry through isa, cast, and dyn_cast: // Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const TerminatorInst *) { return true; }
static inline bool classof(const Instruction *I) { static inline bool classof(const Instruction *I) {
return I->isTerminator(); return I->isTerminator();
} }
static inline bool classof(const Value *V) { static inline bool classof(const Value *V) {
return isa<Instruction>(V) && classof(cast<Instruction>(V)); return isa<Instruction>(V) && classof(cast<Instruction>(V));
} }
}; };
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// UnaryInstruction Class // UnaryInstruction Class
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
class UnaryInstruction : public Instruction { class UnaryInstruction : public Instruction {
void *operator new(size_t, unsigned); // Do not implement void *operator new(size_t, unsigned) LLVM_DELETED_FUNCTION;
protected: protected:
UnaryInstruction(Type *Ty, unsigned iType, Value *V, UnaryInstruction(Type *Ty, unsigned iType, Value *V,
Instruction *IB = 0) Instruction *IB = 0)
: Instruction(Ty, iType, &Op<0>(), 1, IB) { : Instruction(Ty, iType, &Op<0>(), 1, IB) {
Op<0>() = V; Op<0>() = V;
} }
UnaryInstruction(Type *Ty, unsigned iType, Value *V, BasicBlock *IAE) UnaryInstruction(Type *Ty, unsigned iType, Value *V, BasicBlock *IAE)
: Instruction(Ty, iType, &Op<0>(), 1, IAE) { : Instruction(Ty, iType, &Op<0>(), 1, IAE) {
Op<0>() = V; Op<0>() = V;
skipping to change at line 115 skipping to change at line 114
return User::operator new(s, 1); return User::operator new(s, 1);
} }
// Out of line virtual method, so the vtable, etc has a home. // Out of line virtual method, so the vtable, etc has a home.
~UnaryInstruction(); ~UnaryInstruction();
/// Transparently provide more efficient getOperand methods. /// Transparently provide more efficient getOperand methods.
DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value); DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value);
// Methods for support type inquiry through isa, cast, and dyn_cast: // Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const UnaryInstruction *) { return true; }
static inline bool classof(const Instruction *I) { static inline bool classof(const Instruction *I) {
return I->getOpcode() == Instruction::Alloca || return I->getOpcode() == Instruction::Alloca ||
I->getOpcode() == Instruction::Load || I->getOpcode() == Instruction::Load ||
I->getOpcode() == Instruction::VAArg || I->getOpcode() == Instruction::VAArg ||
I->getOpcode() == Instruction::ExtractValue || I->getOpcode() == Instruction::ExtractValue ||
(I->getOpcode() >= CastOpsBegin && I->getOpcode() < CastOpsEnd); (I->getOpcode() >= CastOpsBegin && I->getOpcode() < CastOpsEnd);
} }
static inline bool classof(const Value *V) { static inline bool classof(const Value *V) {
return isa<Instruction>(V) && classof(cast<Instruction>(V)); return isa<Instruction>(V) && classof(cast<Instruction>(V));
} }
skipping to change at line 140 skipping to change at line 138
public FixedNumOperandTraits<UnaryInstruction, 1> { public FixedNumOperandTraits<UnaryInstruction, 1> {
}; };
DEFINE_TRANSPARENT_OPERAND_ACCESSORS(UnaryInstruction, Value) DEFINE_TRANSPARENT_OPERAND_ACCESSORS(UnaryInstruction, Value)
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// BinaryOperator Class // BinaryOperator Class
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
class BinaryOperator : public Instruction { class BinaryOperator : public Instruction {
void *operator new(size_t, unsigned); // Do not implement void *operator new(size_t, unsigned) LLVM_DELETED_FUNCTION;
protected: protected:
void init(BinaryOps iType); void init(BinaryOps iType);
BinaryOperator(BinaryOps iType, Value *S1, Value *S2, Type *Ty, BinaryOperator(BinaryOps iType, Value *S1, Value *S2, Type *Ty,
const Twine &Name, Instruction *InsertBefore); const Twine &Name, Instruction *InsertBefore);
BinaryOperator(BinaryOps iType, Value *S1, Value *S2, Type *Ty, BinaryOperator(BinaryOps iType, Value *S1, Value *S2, Type *Ty,
const Twine &Name, BasicBlock *InsertAtEnd); const Twine &Name, BasicBlock *InsertAtEnd);
virtual BinaryOperator *clone_impl() const; virtual BinaryOperator *clone_impl() const LLVM_OVERRIDE;
public: public:
// allocate space for exactly two operands // allocate space for exactly two operands
void *operator new(size_t s) { void *operator new(size_t s) {
return User::operator new(s, 2); return User::operator new(s, 2);
} }
/// Transparently provide more efficient getOperand methods. /// Transparently provide more efficient getOperand methods.
DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value); DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value);
/// Create() - Construct a binary instruction, given the opcode and the t wo /// Create() - Construct a binary instruction, given the opcode and the t wo
skipping to change at line 363 skipping to change at line 361
/// hasNoUnsignedWrap - Determine whether the no unsigned wrap flag is se t. /// hasNoUnsignedWrap - Determine whether the no unsigned wrap flag is se t.
bool hasNoUnsignedWrap() const; bool hasNoUnsignedWrap() const;
/// hasNoSignedWrap - Determine whether the no signed wrap flag is set. /// hasNoSignedWrap - Determine whether the no signed wrap flag is set.
bool hasNoSignedWrap() const; bool hasNoSignedWrap() const;
/// isExact - Determine whether the exact flag is set. /// isExact - Determine whether the exact flag is set.
bool isExact() const; bool isExact() const;
// Methods for support type inquiry through isa, cast, and dyn_cast: // Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const BinaryOperator *) { return true; }
static inline bool classof(const Instruction *I) { static inline bool classof(const Instruction *I) {
return I->isBinaryOp(); return I->isBinaryOp();
} }
static inline bool classof(const Value *V) { static inline bool classof(const Value *V) {
return isa<Instruction>(V) && classof(cast<Instruction>(V)); return isa<Instruction>(V) && classof(cast<Instruction>(V));
} }
}; };
template <> template <>
struct OperandTraits<BinaryOperator> : struct OperandTraits<BinaryOperator> :
skipping to change at line 390 skipping to change at line 387
// CastInst Class // CastInst Class
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
/// CastInst - This is the base class for all instructions that perform dat a /// CastInst - This is the base class for all instructions that perform dat a
/// casts. It is simply provided so that instruction category testing /// casts. It is simply provided so that instruction category testing
/// can be performed with code like: /// can be performed with code like:
/// ///
/// if (isa<CastInst>(Instr)) { ... } /// if (isa<CastInst>(Instr)) { ... }
/// @brief Base class of casting instructions. /// @brief Base class of casting instructions.
class CastInst : public UnaryInstruction { class CastInst : public UnaryInstruction {
virtual void anchor(); virtual void anchor() LLVM_OVERRIDE;
protected: protected:
/// @brief Constructor with insert-before-instruction semantics for subcl asses /// @brief Constructor with insert-before-instruction semantics for subcl asses
CastInst(Type *Ty, unsigned iType, Value *S, CastInst(Type *Ty, unsigned iType, Value *S,
const Twine &NameStr = "", Instruction *InsertBefore = 0) const Twine &NameStr = "", Instruction *InsertBefore = 0)
: UnaryInstruction(Ty, iType, S, InsertBefore) { : UnaryInstruction(Ty, iType, S, InsertBefore) {
setName(NameStr); setName(NameStr);
} }
/// @brief Constructor with insert-at-end-of-block semantics for subclass es /// @brief Constructor with insert-at-end-of-block semantics for subclass es
CastInst(Type *Ty, unsigned iType, Value *S, CastInst(Type *Ty, unsigned iType, Value *S,
const Twine &NameStr, BasicBlock *InsertAtEnd) const Twine &NameStr, BasicBlock *InsertAtEnd)
skipping to change at line 565 skipping to change at line 562
/// long->double, or int->ptr. /// long->double, or int->ptr.
/// @returns true iff the cast is lossless. /// @returns true iff the cast is lossless.
/// @brief Determine if this is a lossless cast. /// @brief Determine if this is a lossless cast.
bool isLosslessCast() const; bool isLosslessCast() const;
/// A no-op cast is one that can be effected without changing any bits. /// A no-op cast is one that can be effected without changing any bits.
/// It implies that the source and destination types are the same size. T he /// It implies that the source and destination types are the same size. T he
/// IntPtrTy argument is used to make accurate determinations for casts /// IntPtrTy argument is used to make accurate determinations for casts
/// involving Integer and Pointer types. They are no-op casts if the inte ger /// involving Integer and Pointer types. They are no-op casts if the inte ger
/// is the same size as the pointer. However, pointer size varies with /// is the same size as the pointer. However, pointer size varies with
/// platform. Generally, the result of TargetData::getIntPtrType() should be /// platform. Generally, the result of DataLayout::getIntPtrType() should be
/// passed in. If that's not available, use Type::Int64Ty, which will mak e /// passed in. If that's not available, use Type::Int64Ty, which will mak e
/// the isNoopCast call conservative. /// the isNoopCast call conservative.
/// @brief Determine if the described cast is a no-op cast. /// @brief Determine if the described cast is a no-op cast.
static bool isNoopCast( static bool isNoopCast(
Instruction::CastOps Opcode, ///< Opcode of cast Instruction::CastOps Opcode, ///< Opcode of cast
Type *SrcTy, ///< SrcTy of cast Type *SrcTy, ///< SrcTy of cast
Type *DstTy, ///< DstTy of cast Type *DstTy, ///< DstTy of cast
Type *IntPtrTy ///< Integer type corresponding to Ptr types, or null Type *IntPtrTy ///< Integer type corresponding to Ptr types, or null
); );
/// @brief Determine if this cast is a no-op cast. /// @brief Determine if this cast is a no-op cast.
bool isNoopCast( bool isNoopCast(
Type *IntPtrTy ///< Integer type corresponding to pointer Type *IntPtrTy ///< Integer type corresponding to pointer
) const; ) const;
/// Determine how a pair of casts can be eliminated, if they can be at al l. /// Determine how a pair of casts can be eliminated, if they can be at al l.
/// This is a helper function for both CastInst and ConstantExpr. /// This is a helper function for both CastInst and ConstantExpr.
/// @returns 0 if the CastInst pair can't be eliminated /// @returns 0 if the CastInst pair can't be eliminated, otherwise
/// @returns Instruction::CastOps value for a cast that can replace /// returns Instruction::CastOps value for a cast that can replace
/// the pair, casting SrcTy to DstTy. /// the pair, casting SrcTy to DstTy.
/// @brief Determine if a cast pair is eliminable /// @brief Determine if a cast pair is eliminable
static unsigned isEliminableCastPair( static unsigned isEliminableCastPair(
Instruction::CastOps firstOpcode, ///< Opcode of first cast Instruction::CastOps firstOpcode, ///< Opcode of first cast
Instruction::CastOps secondOpcode, ///< Opcode of second cast Instruction::CastOps secondOpcode, ///< Opcode of second cast
Type *SrcTy, ///< SrcTy of 1st cast Type *SrcTy, ///< SrcTy of 1st cast
Type *MidTy, ///< DstTy of 1st cast & SrcTy of 2nd cast Type *MidTy, ///< DstTy of 1st cast & SrcTy of 2nd cast
Type *DstTy, ///< DstTy of 2nd cast Type *DstTy, ///< DstTy of 2nd cast
Type *IntPtrTy ///< Integer type corresponding to Ptr types, or null Type *SrcIntPtrTy, ///< Integer type corresponding to Ptr SrcTy, or nul
l
Type *MidIntPtrTy, ///< Integer type corresponding to Ptr MidTy, or nul
l
Type *DstIntPtrTy ///< Integer type corresponding to Ptr DstTy, or nul
l
); );
/// @brief Return the opcode of this CastInst /// @brief Return the opcode of this CastInst
Instruction::CastOps getOpcode() const { Instruction::CastOps getOpcode() const {
return Instruction::CastOps(Instruction::getOpcode()); return Instruction::CastOps(Instruction::getOpcode());
} }
/// @brief Return the source type, as a convenience /// @brief Return the source type, as a convenience
Type* getSrcTy() const { return getOperand(0)->getType(); } Type* getSrcTy() const { return getOperand(0)->getType(); }
/// @brief Return the destination type, as a convenience /// @brief Return the destination type, as a convenience
Type* getDestTy() const { return getType(); } Type* getDestTy() const { return getType(); }
/// This method can be used to determine if a cast from S to DstTy using /// This method can be used to determine if a cast from S to DstTy using
/// Opcode op is valid or not. /// Opcode op is valid or not.
/// @returns true iff the proposed cast is valid. /// @returns true iff the proposed cast is valid.
/// @brief Determine if a cast is valid without creating one. /// @brief Determine if a cast is valid without creating one.
static bool castIsValid(Instruction::CastOps op, Value *S, Type *DstTy); static bool castIsValid(Instruction::CastOps op, Value *S, Type *DstTy);
/// @brief Methods for support type inquiry through isa, cast, and dyn_ca st: /// @brief Methods for support type inquiry through isa, cast, and dyn_ca st:
static inline bool classof(const CastInst *) { return true; }
static inline bool classof(const Instruction *I) { static inline bool classof(const Instruction *I) {
return I->isCast(); return I->isCast();
} }
static inline bool classof(const Value *V) { static inline bool classof(const Value *V) {
return isa<Instruction>(V) && classof(cast<Instruction>(V)); return isa<Instruction>(V) && classof(cast<Instruction>(V));
} }
}; };
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// CmpInst Class // CmpInst Class
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
/// This class is the base class for the comparison instructions. /// This class is the base class for the comparison instructions.
/// @brief Abstract base class of comparison instructions. /// @brief Abstract base class of comparison instructions.
class CmpInst : public Instruction { class CmpInst : public Instruction {
void *operator new(size_t, unsigned); // DO NOT IMPLEMENT void *operator new(size_t, unsigned) LLVM_DELETED_FUNCTION;
CmpInst(); // do not implement CmpInst() LLVM_DELETED_FUNCTION;
protected: protected:
CmpInst(Type *ty, Instruction::OtherOps op, unsigned short pred, CmpInst(Type *ty, Instruction::OtherOps op, unsigned short pred,
Value *LHS, Value *RHS, const Twine &Name = "", Value *LHS, Value *RHS, const Twine &Name = "",
Instruction *InsertBefore = 0); Instruction *InsertBefore = 0);
CmpInst(Type *ty, Instruction::OtherOps op, unsigned short pred, CmpInst(Type *ty, Instruction::OtherOps op, unsigned short pred,
Value *LHS, Value *RHS, const Twine &Name, Value *LHS, Value *RHS, const Twine &Name,
BasicBlock *InsertAtEnd); BasicBlock *InsertAtEnd);
virtual void Anchor() const; // Out of line virtual method. virtual void anchor() LLVM_OVERRIDE; // Out of line virtual method.
public: public:
/// This enumeration lists the possible predicates for CmpInst subclasses . /// This enumeration lists the possible predicates for CmpInst subclasses .
/// Values in the range 0-31 are reserved for FCmpInst, while values in t he /// Values in the range 0-31 are reserved for FCmpInst, while values in t he
/// range 32-64 are reserved for ICmpInst. This is necessary to ensure th e /// range 32-64 are reserved for ICmpInst. This is necessary to ensure th e
/// predicate values are not overlapping between the classes. /// predicate values are not overlapping between the classes.
enum Predicate { enum Predicate {
// Opcode U L G E Intuitive operation // Opcode U L G E Intuitive operation
FCMP_FALSE = 0, ///< 0 0 0 0 Always false (always folded) FCMP_FALSE = 0, ///< 0 0 0 0 Always false (always folded)
FCMP_OEQ = 1, ///< 0 0 0 1 True if ordered and equal FCMP_OEQ = 1, ///< 0 0 0 1 True if ordered and equal
FCMP_OGT = 2, ///< 0 0 1 0 True if ordered and greater than FCMP_OGT = 2, ///< 0 0 1 0 True if ordered and greater than
skipping to change at line 817 skipping to change at line 815
/// @brief Determine if the predicate is an unordered operation. /// @brief Determine if the predicate is an unordered operation.
static bool isUnordered(unsigned short predicate); static bool isUnordered(unsigned short predicate);
/// Determine if the predicate is true when comparing a value with itself . /// Determine if the predicate is true when comparing a value with itself .
static bool isTrueWhenEqual(unsigned short predicate); static bool isTrueWhenEqual(unsigned short predicate);
/// Determine if the predicate is false when comparing a value with itsel f. /// Determine if the predicate is false when comparing a value with itsel f.
static bool isFalseWhenEqual(unsigned short predicate); static bool isFalseWhenEqual(unsigned short predicate);
/// @brief Methods for support type inquiry through isa, cast, and dyn_ca st: /// @brief Methods for support type inquiry through isa, cast, and dyn_ca st:
static inline bool classof(const CmpInst *) { return true; }
static inline bool classof(const Instruction *I) { static inline bool classof(const Instruction *I) {
return I->getOpcode() == Instruction::ICmp || return I->getOpcode() == Instruction::ICmp ||
I->getOpcode() == Instruction::FCmp; I->getOpcode() == Instruction::FCmp;
} }
static inline bool classof(const Value *V) { static inline bool classof(const Value *V) {
return isa<Instruction>(V) && classof(cast<Instruction>(V)); return isa<Instruction>(V) && classof(cast<Instruction>(V));
} }
/// @brief Create a result type for fcmp/icmp /// @brief Create a result type for fcmp/icmp
static Type* makeCmpResultType(Type* opnd_type) { static Type* makeCmpResultType(Type* opnd_type) {
 End of changes. 14 change blocks. 
16 lines changed or deleted 16 lines changed or added


 Instruction.h   Instruction.h 
skipping to change at line 31 skipping to change at line 31
namespace llvm { namespace llvm {
class LLVMContext; class LLVMContext;
class MDNode; class MDNode;
template<typename ValueSubClass, typename ItemParentClass> template<typename ValueSubClass, typename ItemParentClass>
class SymbolTableListTraits; class SymbolTableListTraits;
class Instruction : public User, public ilist_node<Instruction> { class Instruction : public User, public ilist_node<Instruction> {
void operator=(const Instruction &); // Do not implement void operator=(const Instruction &) LLVM_DELETED_FUNCTION;
Instruction(const Instruction &); // Do not implement Instruction(const Instruction &) LLVM_DELETED_FUNCTION;
BasicBlock *Parent; BasicBlock *Parent;
DebugLoc DbgLoc; // 'dbg' Metadata cache. DebugLoc DbgLoc; // 'dbg' Metadata cache.
enum { enum {
/// HasMetadataBit - This is a bit stored in the SubClassData field whi ch /// HasMetadataBit - This is a bit stored in the SubClassData field whi ch
/// indicates whether this instruction has metadata attached to it or n ot. /// indicates whether this instruction has metadata attached to it or n ot.
HasMetadataBit = 1 << 15 HasMetadataBit = 1 << 15
}; };
public: public:
skipping to change at line 217 skipping to change at line 217
/// isCommutative - Return true if the instruction is commutative: /// isCommutative - Return true if the instruction is commutative:
/// ///
/// Commutative operators satisfy: (x op y) === (y op x) /// Commutative operators satisfy: (x op y) === (y op x)
/// ///
/// In LLVM, these are the associative operators, plus SetEQ and SetNE, w hen /// In LLVM, these are the associative operators, plus SetEQ and SetNE, w hen
/// applied to any type. /// applied to any type.
/// ///
bool isCommutative() const { return isCommutative(getOpcode()); } bool isCommutative() const { return isCommutative(getOpcode()); }
static bool isCommutative(unsigned op); static bool isCommutative(unsigned op);
/// isIdempotent - Return true if the instruction is idempotent:
///
/// Idempotent operators satisfy: x op x === x
///
/// In LLVM, the And and Or operators are idempotent.
///
bool isIdempotent() const { return isIdempotent(getOpcode()); }
static bool isIdempotent(unsigned op);
/// isNilpotent - Return true if the instruction is nilpotent:
///
/// Nilpotent operators satisfy: x op x === Id,
///
/// where Id is the identity for the operator, i.e. a constant such tha
t
/// x op Id === x and Id op x === x for all x.
///
/// In LLVM, the Xor operator is nilpotent.
///
bool isNilpotent() const { return isNilpotent(getOpcode()); }
static bool isNilpotent(unsigned op);
/// mayWriteToMemory - Return true if this instruction may modify memory. /// mayWriteToMemory - Return true if this instruction may modify memory.
/// ///
bool mayWriteToMemory() const; bool mayWriteToMemory() const;
/// mayReadFromMemory - Return true if this instruction may read memory. /// mayReadFromMemory - Return true if this instruction may read memory.
/// ///
bool mayReadFromMemory() const; bool mayReadFromMemory() const;
/// mayReadOrWriteMemory - Return true if this instruction may read or /// mayReadOrWriteMemory - Return true if this instruction may read or
/// write memory. /// write memory.
skipping to change at line 263 skipping to change at line 284
/// isIdenticalTo - Return true if the specified instruction is exactly /// isIdenticalTo - Return true if the specified instruction is exactly
/// identical to the current one. This means that all operands match and any /// identical to the current one. This means that all operands match and any
/// extra information (e.g. load is volatile) agree. /// extra information (e.g. load is volatile) agree.
bool isIdenticalTo(const Instruction *I) const; bool isIdenticalTo(const Instruction *I) const;
/// isIdenticalToWhenDefined - This is like isIdenticalTo, except that it /// isIdenticalToWhenDefined - This is like isIdenticalTo, except that it
/// ignores the SubclassOptionalData flags, which specify conditions /// ignores the SubclassOptionalData flags, which specify conditions
/// under which the instruction's result is undefined. /// under which the instruction's result is undefined.
bool isIdenticalToWhenDefined(const Instruction *I) const; bool isIdenticalToWhenDefined(const Instruction *I) const;
/// When checking for operation equivalence (using isSameOperationAs) it
is
/// sometimes useful to ignore certain attributes.
enum OperationEquivalenceFlags {
/// Check for equivalence ignoring load/store alignment.
CompareIgnoringAlignment = 1<<0,
/// Check for equivalence treating a type and a vector of that type
/// as equivalent.
CompareUsingScalarTypes = 1<<1
};
/// This function determines if the specified instruction executes the sa me /// This function determines if the specified instruction executes the sa me
/// operation as the current one. This means that the opcodes, type, oper and /// operation as the current one. This means that the opcodes, type, oper and
/// types and any other factors affecting the operation must be the same. This /// types and any other factors affecting the operation must be the same. This
/// is similar to isIdenticalTo except the operands themselves don't have to /// is similar to isIdenticalTo except the operands themselves don't have to
/// be identical. /// be identical.
/// @returns true if the specified instruction is the same operation as /// @returns true if the specified instruction is the same operation as
/// the current one. /// the current one.
/// @brief Determine if one instruction is the same operation as another. /// @brief Determine if one instruction is the same operation as another.
bool isSameOperationAs(const Instruction *I) const; bool isSameOperationAs(const Instruction *I, unsigned flags = 0) const;
/// isUsedOutsideOfBlock - Return true if there are any uses of this /// isUsedOutsideOfBlock - Return true if there are any uses of this
/// instruction in blocks other than the specified block. Note that PHI nodes /// instruction in blocks other than the specified block. Note that PHI nodes
/// are considered to evaluate their operands in the corresponding predec essor /// are considered to evaluate their operands in the corresponding predec essor
/// block. /// block.
bool isUsedOutsideOfBlock(const BasicBlock *BB) const; bool isUsedOutsideOfBlock(const BasicBlock *BB) const;
/// Methods for support type inquiry through isa, cast, and dyn_cast: /// Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const Instruction *) { return true; }
static inline bool classof(const Value *V) { static inline bool classof(const Value *V) {
return V->getValueID() >= Value::InstructionVal; return V->getValueID() >= Value::InstructionVal;
} }
//---------------------------------------------------------------------- //----------------------------------------------------------------------
// Exported enumerations. // Exported enumerations.
// //
enum TermOps { // These terminate basic blocks enum TermOps { // These terminate basic blocks
#define FIRST_TERM_INST(N) TermOpsBegin = N, #define FIRST_TERM_INST(N) TermOpsBegin = N,
#define HANDLE_TERM_INST(N, OPC, CLASS) OPC = N, #define HANDLE_TERM_INST(N, OPC, CLASS) OPC = N,
 End of changes. 5 change blocks. 
4 lines changed or deleted 36 lines changed or added


 InstructionSimplify.h   InstructionSimplify.h 
skipping to change at line 27 skipping to change at line 27
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_ANALYSIS_INSTRUCTIONSIMPLIFY_H #ifndef LLVM_ANALYSIS_INSTRUCTIONSIMPLIFY_H
#define LLVM_ANALYSIS_INSTRUCTIONSIMPLIFY_H #define LLVM_ANALYSIS_INSTRUCTIONSIMPLIFY_H
namespace llvm { namespace llvm {
template<typename T> template<typename T>
class ArrayRef; class ArrayRef;
class DominatorTree; class DominatorTree;
class Instruction; class Instruction;
class TargetData; class DataLayout;
class TargetLibraryInfo; class TargetLibraryInfo;
class Type; class Type;
class Value; class Value;
/// SimplifyAddInst - Given operands for an Add, see if we can /// SimplifyAddInst - Given operands for an Add, see if we can
/// fold the result. If not, this returns null. /// fold the result. If not, this returns null.
Value *SimplifyAddInst(Value *LHS, Value *RHS, bool isNSW, bool isNUW, Value *SimplifyAddInst(Value *LHS, Value *RHS, bool isNSW, bool isNUW,
const TargetData *TD = 0, const DataLayout *TD = 0,
const TargetLibraryInfo *TLI = 0, const TargetLibraryInfo *TLI = 0,
const DominatorTree *DT = 0); const DominatorTree *DT = 0);
/// SimplifySubInst - Given operands for a Sub, see if we can /// SimplifySubInst - Given operands for a Sub, see if we can
/// fold the result. If not, this returns null. /// fold the result. If not, this returns null.
Value *SimplifySubInst(Value *LHS, Value *RHS, bool isNSW, bool isNUW, Value *SimplifySubInst(Value *LHS, Value *RHS, bool isNSW, bool isNUW,
const TargetData *TD = 0, const DataLayout *TD = 0,
const TargetLibraryInfo *TLI = 0, const TargetLibraryInfo *TLI = 0,
const DominatorTree *DT = 0); const DominatorTree *DT = 0);
/// SimplifyMulInst - Given operands for a Mul, see if we can /// SimplifyMulInst - Given operands for a Mul, see if we can
/// fold the result. If not, this returns null. /// fold the result. If not, this returns null.
Value *SimplifyMulInst(Value *LHS, Value *RHS, const TargetData *TD = 0, Value *SimplifyMulInst(Value *LHS, Value *RHS, const DataLayout *TD = 0,
const TargetLibraryInfo *TLI = 0, const TargetLibraryInfo *TLI = 0,
const DominatorTree *DT = 0); const DominatorTree *DT = 0);
/// SimplifySDivInst - Given operands for an SDiv, see if we can /// SimplifySDivInst - Given operands for an SDiv, see if we can
/// fold the result. If not, this returns null. /// fold the result. If not, this returns null.
Value *SimplifySDivInst(Value *LHS, Value *RHS, const TargetData *TD = 0, Value *SimplifySDivInst(Value *LHS, Value *RHS, const DataLayout *TD = 0,
const TargetLibraryInfo *TLI = 0, const TargetLibraryInfo *TLI = 0,
const DominatorTree *DT = 0); const DominatorTree *DT = 0);
/// SimplifyUDivInst - Given operands for a UDiv, see if we can /// SimplifyUDivInst - Given operands for a UDiv, see if we can
/// fold the result. If not, this returns null. /// fold the result. If not, this returns null.
Value *SimplifyUDivInst(Value *LHS, Value *RHS, const TargetData *TD = 0, Value *SimplifyUDivInst(Value *LHS, Value *RHS, const DataLayout *TD = 0,
const TargetLibraryInfo *TLI = 0, const TargetLibraryInfo *TLI = 0,
const DominatorTree *DT = 0); const DominatorTree *DT = 0);
/// SimplifyFDivInst - Given operands for an FDiv, see if we can /// SimplifyFDivInst - Given operands for an FDiv, see if we can
/// fold the result. If not, this returns null. /// fold the result. If not, this returns null.
Value *SimplifyFDivInst(Value *LHS, Value *RHS, const TargetData *TD = 0, Value *SimplifyFDivInst(Value *LHS, Value *RHS, const DataLayout *TD = 0,
const TargetLibraryInfo *TLI = 0, const TargetLibraryInfo *TLI = 0,
const DominatorTree *DT = 0); const DominatorTree *DT = 0);
/// SimplifySRemInst - Given operands for an SRem, see if we can /// SimplifySRemInst - Given operands for an SRem, see if we can
/// fold the result. If not, this returns null. /// fold the result. If not, this returns null.
Value *SimplifySRemInst(Value *LHS, Value *RHS, const TargetData *TD = 0, Value *SimplifySRemInst(Value *LHS, Value *RHS, const DataLayout *TD = 0,
const TargetLibraryInfo *TLI = 0, const TargetLibraryInfo *TLI = 0,
const DominatorTree *DT = 0); const DominatorTree *DT = 0);
/// SimplifyURemInst - Given operands for a URem, see if we can /// SimplifyURemInst - Given operands for a URem, see if we can
/// fold the result. If not, this returns null. /// fold the result. If not, this returns null.
Value *SimplifyURemInst(Value *LHS, Value *RHS, const TargetData *TD = 0, Value *SimplifyURemInst(Value *LHS, Value *RHS, const DataLayout *TD = 0,
const TargetLibraryInfo *TLI = 0, const TargetLibraryInfo *TLI = 0,
const DominatorTree *DT = 0); const DominatorTree *DT = 0);
/// SimplifyFRemInst - Given operands for an FRem, see if we can /// SimplifyFRemInst - Given operands for an FRem, see if we can
/// fold the result. If not, this returns null. /// fold the result. If not, this returns null.
Value *SimplifyFRemInst(Value *LHS, Value *RHS, const TargetData *TD = 0, Value *SimplifyFRemInst(Value *LHS, Value *RHS, const DataLayout *TD = 0,
const TargetLibraryInfo *TLI = 0, const TargetLibraryInfo *TLI = 0,
const DominatorTree *DT = 0); const DominatorTree *DT = 0);
/// SimplifyShlInst - Given operands for a Shl, see if we can /// SimplifyShlInst - Given operands for a Shl, see if we can
/// fold the result. If not, this returns null. /// fold the result. If not, this returns null.
Value *SimplifyShlInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW, Value *SimplifyShlInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW,
const TargetData *TD = 0, const DataLayout *TD = 0,
const TargetLibraryInfo *TLI = 0, const TargetLibraryInfo *TLI = 0,
const DominatorTree *DT = 0); const DominatorTree *DT = 0);
/// SimplifyLShrInst - Given operands for a LShr, see if we can /// SimplifyLShrInst - Given operands for a LShr, see if we can
/// fold the result. If not, this returns null. /// fold the result. If not, this returns null.
Value *SimplifyLShrInst(Value *Op0, Value *Op1, bool isExact, Value *SimplifyLShrInst(Value *Op0, Value *Op1, bool isExact,
const TargetData *TD = 0, const DataLayout *TD = 0,
const TargetLibraryInfo *TLI = 0, const TargetLibraryInfo *TLI = 0,
const DominatorTree *DT = 0); const DominatorTree *DT = 0);
/// SimplifyAShrInst - Given operands for a AShr, see if we can /// SimplifyAShrInst - Given operands for a AShr, see if we can
/// fold the result. If not, this returns null. /// fold the result. If not, this returns null.
Value *SimplifyAShrInst(Value *Op0, Value *Op1, bool isExact, Value *SimplifyAShrInst(Value *Op0, Value *Op1, bool isExact,
const TargetData *TD = 0, const DataLayout *TD = 0,
const TargetLibraryInfo *TLI = 0, const TargetLibraryInfo *TLI = 0,
const DominatorTree *DT = 0); const DominatorTree *DT = 0);
/// SimplifyAndInst - Given operands for an And, see if we can /// SimplifyAndInst - Given operands for an And, see if we can
/// fold the result. If not, this returns null. /// fold the result. If not, this returns null.
Value *SimplifyAndInst(Value *LHS, Value *RHS, const TargetData *TD = 0, Value *SimplifyAndInst(Value *LHS, Value *RHS, const DataLayout *TD = 0,
const TargetLibraryInfo *TLI = 0, const TargetLibraryInfo *TLI = 0,
const DominatorTree *DT = 0); const DominatorTree *DT = 0);
/// SimplifyOrInst - Given operands for an Or, see if we can /// SimplifyOrInst - Given operands for an Or, see if we can
/// fold the result. If not, this returns null. /// fold the result. If not, this returns null.
Value *SimplifyOrInst(Value *LHS, Value *RHS, const TargetData *TD = 0, Value *SimplifyOrInst(Value *LHS, Value *RHS, const DataLayout *TD = 0,
const TargetLibraryInfo *TLI = 0, const TargetLibraryInfo *TLI = 0,
const DominatorTree *DT = 0); const DominatorTree *DT = 0);
/// SimplifyXorInst - Given operands for a Xor, see if we can /// SimplifyXorInst - Given operands for a Xor, see if we can
/// fold the result. If not, this returns null. /// fold the result. If not, this returns null.
Value *SimplifyXorInst(Value *LHS, Value *RHS, const TargetData *TD = 0, Value *SimplifyXorInst(Value *LHS, Value *RHS, const DataLayout *TD = 0,
const TargetLibraryInfo *TLI = 0, const TargetLibraryInfo *TLI = 0,
const DominatorTree *DT = 0); const DominatorTree *DT = 0);
/// SimplifyICmpInst - Given operands for an ICmpInst, see if we can /// SimplifyICmpInst - Given operands for an ICmpInst, see if we can
/// fold the result. If not, this returns null. /// fold the result. If not, this returns null.
Value *SimplifyICmpInst(unsigned Predicate, Value *LHS, Value *RHS, Value *SimplifyICmpInst(unsigned Predicate, Value *LHS, Value *RHS,
const TargetData *TD = 0, const DataLayout *TD = 0,
const TargetLibraryInfo *TLI = 0, const TargetLibraryInfo *TLI = 0,
const DominatorTree *DT = 0); const DominatorTree *DT = 0);
/// SimplifyFCmpInst - Given operands for an FCmpInst, see if we can /// SimplifyFCmpInst - Given operands for an FCmpInst, see if we can
/// fold the result. If not, this returns null. /// fold the result. If not, this returns null.
Value *SimplifyFCmpInst(unsigned Predicate, Value *LHS, Value *RHS, Value *SimplifyFCmpInst(unsigned Predicate, Value *LHS, Value *RHS,
const TargetData *TD = 0, const DataLayout *TD = 0,
const TargetLibraryInfo *TLI = 0, const TargetLibraryInfo *TLI = 0,
const DominatorTree *DT = 0); const DominatorTree *DT = 0);
/// SimplifySelectInst - Given operands for a SelectInst, see if we can f old /// SimplifySelectInst - Given operands for a SelectInst, see if we can f old
/// the result. If not, this returns null. /// the result. If not, this returns null.
Value *SimplifySelectInst(Value *Cond, Value *TrueVal, Value *FalseVal, Value *SimplifySelectInst(Value *Cond, Value *TrueVal, Value *FalseVal,
const TargetData *TD = 0, const DataLayout *TD = 0,
const TargetLibraryInfo *TLI = 0, const TargetLibraryInfo *TLI = 0,
const DominatorTree *DT = 0); const DominatorTree *DT = 0);
/// SimplifyGEPInst - Given operands for an GetElementPtrInst, see if we can /// SimplifyGEPInst - Given operands for an GetElementPtrInst, see if we can
/// fold the result. If not, this returns null. /// fold the result. If not, this returns null.
Value *SimplifyGEPInst(ArrayRef<Value *> Ops, const TargetData *TD = 0, Value *SimplifyGEPInst(ArrayRef<Value *> Ops, const DataLayout *TD = 0,
const TargetLibraryInfo *TLI = 0, const TargetLibraryInfo *TLI = 0,
const DominatorTree *DT = 0); const DominatorTree *DT = 0);
/// SimplifyInsertValueInst - Given operands for an InsertValueInst, see if we /// SimplifyInsertValueInst - Given operands for an InsertValueInst, see if we
/// can fold the result. If not, this returns null. /// can fold the result. If not, this returns null.
Value *SimplifyInsertValueInst(Value *Agg, Value *Val, Value *SimplifyInsertValueInst(Value *Agg, Value *Val,
ArrayRef<unsigned> Idxs, ArrayRef<unsigned> Idxs,
const TargetData *TD = 0, const DataLayout *TD = 0,
const TargetLibraryInfo *TLI = 0, const TargetLibraryInfo *TLI = 0,
const DominatorTree *DT = 0); const DominatorTree *DT = 0);
/// SimplifyTruncInst - Given operands for an TruncInst, see if we can fo ld /// SimplifyTruncInst - Given operands for an TruncInst, see if we can fo ld
/// the result. If not, this returns null. /// the result. If not, this returns null.
Value *SimplifyTruncInst(Value *Op, Type *Ty, const TargetData *TD = 0, Value *SimplifyTruncInst(Value *Op, Type *Ty, const DataLayout *TD = 0,
const TargetLibraryInfo *TLI = 0, const TargetLibraryInfo *TLI = 0,
const DominatorTree *DT = 0); const DominatorTree *DT = 0);
//=== Helper functions for higher up the class hierarchy. //=== Helper functions for higher up the class hierarchy.
/// SimplifyCmpInst - Given operands for a CmpInst, see if we can /// SimplifyCmpInst - Given operands for a CmpInst, see if we can
/// fold the result. If not, this returns null. /// fold the result. If not, this returns null.
Value *SimplifyCmpInst(unsigned Predicate, Value *LHS, Value *RHS, Value *SimplifyCmpInst(unsigned Predicate, Value *LHS, Value *RHS,
const TargetData *TD = 0, const DataLayout *TD = 0,
const TargetLibraryInfo *TLI = 0, const TargetLibraryInfo *TLI = 0,
const DominatorTree *DT = 0); const DominatorTree *DT = 0);
/// SimplifyBinOp - Given operands for a BinaryOperator, see if we can /// SimplifyBinOp - Given operands for a BinaryOperator, see if we can
/// fold the result. If not, this returns null. /// fold the result. If not, this returns null.
Value *SimplifyBinOp(unsigned Opcode, Value *LHS, Value *RHS, Value *SimplifyBinOp(unsigned Opcode, Value *LHS, Value *RHS,
const TargetData *TD = 0, const DataLayout *TD = 0,
const TargetLibraryInfo *TLI = 0, const TargetLibraryInfo *TLI = 0,
const DominatorTree *DT = 0); const DominatorTree *DT = 0);
/// SimplifyInstruction - See if we can compute a simplified version of t his /// SimplifyInstruction - See if we can compute a simplified version of t his
/// instruction. If not, this returns null. /// instruction. If not, this returns null.
Value *SimplifyInstruction(Instruction *I, const TargetData *TD = 0, Value *SimplifyInstruction(Instruction *I, const DataLayout *TD = 0,
const TargetLibraryInfo *TLI = 0, const TargetLibraryInfo *TLI = 0,
const DominatorTree *DT = 0); const DominatorTree *DT = 0);
/// \brief Replace all uses of 'I' with 'SimpleV' and simplify the uses /// \brief Replace all uses of 'I' with 'SimpleV' and simplify the uses
/// recursively. /// recursively.
/// ///
/// This first performs a normal RAUW of I with SimpleV. It then recursiv ely /// This first performs a normal RAUW of I with SimpleV. It then recursiv ely
/// attempts to simplify those users updated by the operation. The 'I' /// attempts to simplify those users updated by the operation. The 'I'
/// instruction must not be equal to the simplified value 'SimpleV'. /// instruction must not be equal to the simplified value 'SimpleV'.
/// ///
/// The function returns true if any simplifications were performed. /// The function returns true if any simplifications were performed.
bool replaceAndRecursivelySimplify(Instruction *I, Value *SimpleV, bool replaceAndRecursivelySimplify(Instruction *I, Value *SimpleV,
const TargetData *TD = 0, const DataLayout *TD = 0,
const TargetLibraryInfo *TLI = 0, const TargetLibraryInfo *TLI = 0,
const DominatorTree *DT = 0); const DominatorTree *DT = 0);
/// \brief Recursively attempt to simplify an instruction. /// \brief Recursively attempt to simplify an instruction.
/// ///
/// This routine uses SimplifyInstruction to simplify 'I', and if success ful /// This routine uses SimplifyInstruction to simplify 'I', and if success ful
/// replaces uses of 'I' with the simplified value. It then recurses on e ach /// replaces uses of 'I' with the simplified value. It then recurses on e ach
/// of the users impacted. It returns true if any simplifications were /// of the users impacted. It returns true if any simplifications were
/// performed. /// performed.
bool recursivelySimplifyInstruction(Instruction *I, bool recursivelySimplifyInstruction(Instruction *I,
const TargetData *TD = 0, const DataLayout *TD = 0,
const TargetLibraryInfo *TLI = 0, const TargetLibraryInfo *TLI = 0,
const DominatorTree *DT = 0); const DominatorTree *DT = 0);
} // end namespace llvm } // end namespace llvm
#endif #endif
 End of changes. 27 change blocks. 
27 lines changed or deleted 27 lines changed or added


 Instructions.h   Instructions.h 
skipping to change at line 23 skipping to change at line 23
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_INSTRUCTIONS_H #ifndef LLVM_INSTRUCTIONS_H
#define LLVM_INSTRUCTIONS_H #define LLVM_INSTRUCTIONS_H
#include "llvm/InstrTypes.h" #include "llvm/InstrTypes.h"
#include "llvm/DerivedTypes.h" #include "llvm/DerivedTypes.h"
#include "llvm/Attributes.h" #include "llvm/Attributes.h"
#include "llvm/CallingConv.h" #include "llvm/CallingConv.h"
#include "llvm/Support/IntegersSubset.h"
#include "llvm/Support/IntegersSubsetMapping.h"
#include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/SmallVector.h" #include "llvm/ADT/SmallVector.h"
#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/ErrorHandling.h"
#include <iterator> #include <iterator>
namespace llvm { namespace llvm {
class ConstantInt; class ConstantInt;
class ConstantRange; class ConstantRange;
class APInt; class APInt;
skipping to change at line 113 skipping to change at line 115
return (1u << getSubclassDataFromInstruction()) >> 1; return (1u << getSubclassDataFromInstruction()) >> 1;
} }
void setAlignment(unsigned Align); void setAlignment(unsigned Align);
/// isStaticAlloca - Return true if this alloca is in the entry block of the /// isStaticAlloca - Return true if this alloca is in the entry block of the
/// function and is a constant size. If so, the code generator will fold it /// function and is a constant size. If so, the code generator will fold it
/// into the prolog/epilog code, so it is basically free. /// into the prolog/epilog code, so it is basically free.
bool isStaticAlloca() const; bool isStaticAlloca() const;
// Methods for support type inquiry through isa, cast, and dyn_cast: // Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const AllocaInst *) { return true; }
static inline bool classof(const Instruction *I) { static inline bool classof(const Instruction *I) {
return (I->getOpcode() == Instruction::Alloca); return (I->getOpcode() == Instruction::Alloca);
} }
static inline bool classof(const Value *V) { static inline bool classof(const Value *V) {
return isa<Instruction>(V) && classof(cast<Instruction>(V)); return isa<Instruction>(V) && classof(cast<Instruction>(V));
} }
private: private:
// Shadow Instruction::setInstructionSubclassData with a private forwardi ng // Shadow Instruction::setInstructionSubclassData with a private forwardi ng
// method so that subclasses cannot accidentally use it. // method so that subclasses cannot accidentally use it.
void setInstructionSubclassData(unsigned short D) { void setInstructionSubclassData(unsigned short D) {
skipping to change at line 226 skipping to change at line 227
bool isSimple() const { return !isAtomic() && !isVolatile(); } bool isSimple() const { return !isAtomic() && !isVolatile(); }
bool isUnordered() const { bool isUnordered() const {
return getOrdering() <= Unordered && !isVolatile(); return getOrdering() <= Unordered && !isVolatile();
} }
Value *getPointerOperand() { return getOperand(0); } Value *getPointerOperand() { return getOperand(0); }
const Value *getPointerOperand() const { return getOperand(0); } const Value *getPointerOperand() const { return getOperand(0); }
static unsigned getPointerOperandIndex() { return 0U; } static unsigned getPointerOperandIndex() { return 0U; }
/// \brief Returns the address space of the pointer operand.
unsigned getPointerAddressSpace() const { unsigned getPointerAddressSpace() const {
return cast<PointerType>(getPointerOperand()->getType())->getAddressSpa ce(); return getPointerOperand()->getType()->getPointerAddressSpace();
} }
// Methods for support type inquiry through isa, cast, and dyn_cast: // Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const LoadInst *) { return true; }
static inline bool classof(const Instruction *I) { static inline bool classof(const Instruction *I) {
return I->getOpcode() == Instruction::Load; return I->getOpcode() == Instruction::Load;
} }
static inline bool classof(const Value *V) { static inline bool classof(const Value *V) {
return isa<Instruction>(V) && classof(cast<Instruction>(V)); return isa<Instruction>(V) && classof(cast<Instruction>(V));
} }
private: private:
// Shadow Instruction::setInstructionSubclassData with a private forwardi ng // Shadow Instruction::setInstructionSubclassData with a private forwardi ng
// method so that subclasses cannot accidentally use it. // method so that subclasses cannot accidentally use it.
void setInstructionSubclassData(unsigned short D) { void setInstructionSubclassData(unsigned short D) {
skipping to change at line 253 skipping to change at line 254
} }
}; };
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// StoreInst Class // StoreInst Class
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
/// StoreInst - an instruction for storing to memory /// StoreInst - an instruction for storing to memory
/// ///
class StoreInst : public Instruction { class StoreInst : public Instruction {
void *operator new(size_t, unsigned); // DO NOT IMPLEMENT void *operator new(size_t, unsigned) LLVM_DELETED_FUNCTION;
void AssertOK(); void AssertOK();
protected: protected:
virtual StoreInst *clone_impl() const; virtual StoreInst *clone_impl() const;
public: public:
// allocate space for exactly two operands // allocate space for exactly two operands
void *operator new(size_t s) { void *operator new(size_t s) {
return User::operator new(s, 2); return User::operator new(s, 2);
} }
StoreInst(Value *Val, Value *Ptr, Instruction *InsertBefore); StoreInst(Value *Val, Value *Ptr, Instruction *InsertBefore);
StoreInst(Value *Val, Value *Ptr, BasicBlock *InsertAtEnd); StoreInst(Value *Val, Value *Ptr, BasicBlock *InsertAtEnd);
skipping to change at line 346 skipping to change at line 347
return getOrdering() <= Unordered && !isVolatile(); return getOrdering() <= Unordered && !isVolatile();
} }
Value *getValueOperand() { return getOperand(0); } Value *getValueOperand() { return getOperand(0); }
const Value *getValueOperand() const { return getOperand(0); } const Value *getValueOperand() const { return getOperand(0); }
Value *getPointerOperand() { return getOperand(1); } Value *getPointerOperand() { return getOperand(1); }
const Value *getPointerOperand() const { return getOperand(1); } const Value *getPointerOperand() const { return getOperand(1); }
static unsigned getPointerOperandIndex() { return 1U; } static unsigned getPointerOperandIndex() { return 1U; }
/// \brief Returns the address space of the pointer operand.
unsigned getPointerAddressSpace() const { unsigned getPointerAddressSpace() const {
return cast<PointerType>(getPointerOperand()->getType())->getAddressSpa ce(); return getPointerOperand()->getType()->getPointerAddressSpace();
} }
// Methods for support type inquiry through isa, cast, and dyn_cast: // Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const StoreInst *) { return true; }
static inline bool classof(const Instruction *I) { static inline bool classof(const Instruction *I) {
return I->getOpcode() == Instruction::Store; return I->getOpcode() == Instruction::Store;
} }
static inline bool classof(const Value *V) { static inline bool classof(const Value *V) {
return isa<Instruction>(V) && classof(cast<Instruction>(V)); return isa<Instruction>(V) && classof(cast<Instruction>(V));
} }
private: private:
// Shadow Instruction::setInstructionSubclassData with a private forwardi ng // Shadow Instruction::setInstructionSubclassData with a private forwardi ng
// method so that subclasses cannot accidentally use it. // method so that subclasses cannot accidentally use it.
void setInstructionSubclassData(unsigned short D) { void setInstructionSubclassData(unsigned short D) {
skipping to change at line 379 skipping to change at line 380
DEFINE_TRANSPARENT_OPERAND_ACCESSORS(StoreInst, Value) DEFINE_TRANSPARENT_OPERAND_ACCESSORS(StoreInst, Value)
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// FenceInst Class // FenceInst Class
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
/// FenceInst - an instruction for ordering other memory operations /// FenceInst - an instruction for ordering other memory operations
/// ///
class FenceInst : public Instruction { class FenceInst : public Instruction {
void *operator new(size_t, unsigned); // DO NOT IMPLEMENT void *operator new(size_t, unsigned) LLVM_DELETED_FUNCTION;
void Init(AtomicOrdering Ordering, SynchronizationScope SynchScope); void Init(AtomicOrdering Ordering, SynchronizationScope SynchScope);
protected: protected:
virtual FenceInst *clone_impl() const; virtual FenceInst *clone_impl() const;
public: public:
// allocate space for exactly zero operands // allocate space for exactly zero operands
void *operator new(size_t s) { void *operator new(size_t s) {
return User::operator new(s, 0); return User::operator new(s, 0);
} }
// Ordering may only be Acquire, Release, AcquireRelease, or // Ordering may only be Acquire, Release, AcquireRelease, or
skipping to change at line 423 skipping to change at line 424
/// Specify whether this fence orders other operations with respect to al l /// Specify whether this fence orders other operations with respect to al l
/// concurrently executing threads, or only with respect to signal handle rs /// concurrently executing threads, or only with respect to signal handle rs
/// executing in the same thread. /// executing in the same thread.
void setSynchScope(SynchronizationScope xthread) { void setSynchScope(SynchronizationScope xthread) {
setInstructionSubclassData((getSubclassDataFromInstruction() & ~1) | setInstructionSubclassData((getSubclassDataFromInstruction() & ~1) |
xthread); xthread);
} }
// Methods for support type inquiry through isa, cast, and dyn_cast: // Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const FenceInst *) { return true; }
static inline bool classof(const Instruction *I) { static inline bool classof(const Instruction *I) {
return I->getOpcode() == Instruction::Fence; return I->getOpcode() == Instruction::Fence;
} }
static inline bool classof(const Value *V) { static inline bool classof(const Value *V) {
return isa<Instruction>(V) && classof(cast<Instruction>(V)); return isa<Instruction>(V) && classof(cast<Instruction>(V));
} }
private: private:
// Shadow Instruction::setInstructionSubclassData with a private forwardi ng // Shadow Instruction::setInstructionSubclassData with a private forwardi ng
// method so that subclasses cannot accidentally use it. // method so that subclasses cannot accidentally use it.
void setInstructionSubclassData(unsigned short D) { void setInstructionSubclassData(unsigned short D) {
skipping to change at line 447 skipping to change at line 447
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// AtomicCmpXchgInst Class // AtomicCmpXchgInst Class
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
/// AtomicCmpXchgInst - an instruction that atomically checks whether a /// AtomicCmpXchgInst - an instruction that atomically checks whether a
/// specified value is in a memory location, and, if it is, stores a new va lue /// specified value is in a memory location, and, if it is, stores a new va lue
/// there. Returns the value that was loaded. /// there. Returns the value that was loaded.
/// ///
class AtomicCmpXchgInst : public Instruction { class AtomicCmpXchgInst : public Instruction {
void *operator new(size_t, unsigned); // DO NOT IMPLEMENT void *operator new(size_t, unsigned) LLVM_DELETED_FUNCTION;
void Init(Value *Ptr, Value *Cmp, Value *NewVal, void Init(Value *Ptr, Value *Cmp, Value *NewVal,
AtomicOrdering Ordering, SynchronizationScope SynchScope); AtomicOrdering Ordering, SynchronizationScope SynchScope);
protected: protected:
virtual AtomicCmpXchgInst *clone_impl() const; virtual AtomicCmpXchgInst *clone_impl() const;
public: public:
// allocate space for exactly three operands // allocate space for exactly three operands
void *operator new(size_t s) { void *operator new(size_t s) {
return User::operator new(s, 3); return User::operator new(s, 3);
} }
AtomicCmpXchgInst(Value *Ptr, Value *Cmp, Value *NewVal, AtomicCmpXchgInst(Value *Ptr, Value *Cmp, Value *NewVal,
skipping to change at line 518 skipping to change at line 518
Value *getPointerOperand() { return getOperand(0); } Value *getPointerOperand() { return getOperand(0); }
const Value *getPointerOperand() const { return getOperand(0); } const Value *getPointerOperand() const { return getOperand(0); }
static unsigned getPointerOperandIndex() { return 0U; } static unsigned getPointerOperandIndex() { return 0U; }
Value *getCompareOperand() { return getOperand(1); } Value *getCompareOperand() { return getOperand(1); }
const Value *getCompareOperand() const { return getOperand(1); } const Value *getCompareOperand() const { return getOperand(1); }
Value *getNewValOperand() { return getOperand(2); } Value *getNewValOperand() { return getOperand(2); }
const Value *getNewValOperand() const { return getOperand(2); } const Value *getNewValOperand() const { return getOperand(2); }
/// \brief Returns the address space of the pointer operand.
unsigned getPointerAddressSpace() const { unsigned getPointerAddressSpace() const {
return cast<PointerType>(getPointerOperand()->getType())->getAddressSpa ce(); return getPointerOperand()->getType()->getPointerAddressSpace();
} }
// Methods for support type inquiry through isa, cast, and dyn_cast: // Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const AtomicCmpXchgInst *) { return true; }
static inline bool classof(const Instruction *I) { static inline bool classof(const Instruction *I) {
return I->getOpcode() == Instruction::AtomicCmpXchg; return I->getOpcode() == Instruction::AtomicCmpXchg;
} }
static inline bool classof(const Value *V) { static inline bool classof(const Value *V) {
return isa<Instruction>(V) && classof(cast<Instruction>(V)); return isa<Instruction>(V) && classof(cast<Instruction>(V));
} }
private: private:
// Shadow Instruction::setInstructionSubclassData with a private forwardi ng // Shadow Instruction::setInstructionSubclassData with a private forwardi ng
// method so that subclasses cannot accidentally use it. // method so that subclasses cannot accidentally use it.
void setInstructionSubclassData(unsigned short D) { void setInstructionSubclassData(unsigned short D) {
skipping to change at line 554 skipping to change at line 554
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// AtomicRMWInst Class // AtomicRMWInst Class
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
/// AtomicRMWInst - an instruction that atomically reads a memory location, /// AtomicRMWInst - an instruction that atomically reads a memory location,
/// combines it with another value, and then stores the result back. Retur ns /// combines it with another value, and then stores the result back. Retur ns
/// the old value. /// the old value.
/// ///
class AtomicRMWInst : public Instruction { class AtomicRMWInst : public Instruction {
void *operator new(size_t, unsigned); // DO NOT IMPLEMENT void *operator new(size_t, unsigned) LLVM_DELETED_FUNCTION;
protected: protected:
virtual AtomicRMWInst *clone_impl() const; virtual AtomicRMWInst *clone_impl() const;
public: public:
/// This enumeration lists the possible modifications atomicrmw can make. In /// This enumeration lists the possible modifications atomicrmw can make. In
/// the descriptions, 'p' is the pointer to the instruction's memory loca tion, /// the descriptions, 'p' is the pointer to the instruction's memory loca tion,
/// 'old' is the initial value of *p, and 'v' is the other value passed t o the /// 'old' is the initial value of *p, and 'v' is the other value passed t o the
/// instruction. These instructions always return 'old'. /// instruction. These instructions always return 'old'.
enum BinOp { enum BinOp {
/// *p = v /// *p = v
Xchg, Xchg,
skipping to change at line 662 skipping to change at line 662
return SynchronizationScope((getSubclassDataFromInstruction() & 2) >> 1 ); return SynchronizationScope((getSubclassDataFromInstruction() & 2) >> 1 );
} }
Value *getPointerOperand() { return getOperand(0); } Value *getPointerOperand() { return getOperand(0); }
const Value *getPointerOperand() const { return getOperand(0); } const Value *getPointerOperand() const { return getOperand(0); }
static unsigned getPointerOperandIndex() { return 0U; } static unsigned getPointerOperandIndex() { return 0U; }
Value *getValOperand() { return getOperand(1); } Value *getValOperand() { return getOperand(1); }
const Value *getValOperand() const { return getOperand(1); } const Value *getValOperand() const { return getOperand(1); }
/// \brief Returns the address space of the pointer operand.
unsigned getPointerAddressSpace() const { unsigned getPointerAddressSpace() const {
return cast<PointerType>(getPointerOperand()->getType())->getAddressSpa ce(); return getPointerOperand()->getType()->getPointerAddressSpace();
} }
// Methods for support type inquiry through isa, cast, and dyn_cast: // Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const AtomicRMWInst *) { return true; }
static inline bool classof(const Instruction *I) { static inline bool classof(const Instruction *I) {
return I->getOpcode() == Instruction::AtomicRMW; return I->getOpcode() == Instruction::AtomicRMW;
} }
static inline bool classof(const Value *V) { static inline bool classof(const Value *V) {
return isa<Instruction>(V) && classof(cast<Instruction>(V)); return isa<Instruction>(V) && classof(cast<Instruction>(V));
} }
private: private:
void Init(BinOp Operation, Value *Ptr, Value *Val, void Init(BinOp Operation, Value *Ptr, Value *Val,
AtomicOrdering Ordering, SynchronizationScope SynchScope); AtomicOrdering Ordering, SynchronizationScope SynchScope);
// Shadow Instruction::setInstructionSubclassData with a private forwardi ng // Shadow Instruction::setInstructionSubclassData with a private forwardi ng
skipping to change at line 698 skipping to change at line 698
DEFINE_TRANSPARENT_OPERAND_ACCESSORS(AtomicRMWInst, Value) DEFINE_TRANSPARENT_OPERAND_ACCESSORS(AtomicRMWInst, Value)
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// GetElementPtrInst Class // GetElementPtrInst Class
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// checkGEPType - Simple wrapper function to give a better assertion failur e // checkGEPType - Simple wrapper function to give a better assertion failur e
// message on bad indexes for a gep instruction. // message on bad indexes for a gep instruction.
// //
static inline Type *checkGEPType(Type *Ty) { inline Type *checkGEPType(Type *Ty) {
assert(Ty && "Invalid GetElementPtrInst indices for type!"); assert(Ty && "Invalid GetElementPtrInst indices for type!");
return Ty; return Ty;
} }
/// GetElementPtrInst - an instruction for type-safe pointer arithmetic to /// GetElementPtrInst - an instruction for type-safe pointer arithmetic to
/// access elements of arrays and structs /// access elements of arrays and structs
/// ///
class GetElementPtrInst : public Instruction { class GetElementPtrInst : public Instruction {
GetElementPtrInst(const GetElementPtrInst &GEPI); GetElementPtrInst(const GetElementPtrInst &GEPI);
void init(Value *Ptr, ArrayRef<Value *> IdxList, const Twine &NameStr); void init(Value *Ptr, ArrayRef<Value *> IdxList, const Twine &NameStr);
skipping to change at line 765 skipping to change at line 765
} }
/// Transparently provide more efficient getOperand methods. /// Transparently provide more efficient getOperand methods.
DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value); DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value);
// getType - Overload to return most specific pointer type... // getType - Overload to return most specific pointer type...
PointerType *getType() const { PointerType *getType() const {
return reinterpret_cast<PointerType*>(Instruction::getType()); return reinterpret_cast<PointerType*>(Instruction::getType());
} }
/// \brief Returns the address space of this instruction's pointer type.
unsigned getAddressSpace() const {
// Note that this is always the same as the pointer operand's address s
pace
// and that is cheaper to compute, so cheat here.
return getPointerAddressSpace();
}
/// getIndexedType - Returns the type of the element that would be loaded with /// getIndexedType - Returns the type of the element that would be loaded with
/// a load instruction with the specified parameters. /// a load instruction with the specified parameters.
/// ///
/// Null is returned if the indices are invalid for the specified /// Null is returned if the indices are invalid for the specified
/// pointer type. /// pointer type.
/// ///
static Type *getIndexedType(Type *Ptr, ArrayRef<Value *> IdxList); static Type *getIndexedType(Type *Ptr, ArrayRef<Value *> IdxList);
static Type *getIndexedType(Type *Ptr, ArrayRef<Constant *> IdxList); static Type *getIndexedType(Type *Ptr, ArrayRef<Constant *> IdxList);
static Type *getIndexedType(Type *Ptr, ArrayRef<uint64_t> IdxList); static Type *getIndexedType(Type *Ptr, ArrayRef<uint64_t> IdxList);
/// getIndexedType - Returns the address space used by the GEP pointer.
///
static unsigned getAddressSpace(Value *Ptr);
inline op_iterator idx_begin() { return op_begin()+1; } inline op_iterator idx_begin() { return op_begin()+1; }
inline const_op_iterator idx_begin() const { return op_begin()+1; } inline const_op_iterator idx_begin() const { return op_begin()+1; }
inline op_iterator idx_end() { return op_end(); } inline op_iterator idx_end() { return op_end(); }
inline const_op_iterator idx_end() const { return op_end(); } inline const_op_iterator idx_end() const { return op_end(); }
Value *getPointerOperand() { Value *getPointerOperand() {
return getOperand(0); return getOperand(0);
} }
const Value *getPointerOperand() const { const Value *getPointerOperand() const {
return getOperand(0); return getOperand(0);
} }
static unsigned getPointerOperandIndex() { static unsigned getPointerOperandIndex() {
return 0U; // get index for modifying correct operand. return 0U; // get index for modifying correct operand.
} }
unsigned getPointerAddressSpace() const {
return cast<PointerType>(getType())->getAddressSpace();
}
/// getPointerOperandType - Method to return the pointer operand as a /// getPointerOperandType - Method to return the pointer operand as a
/// PointerType. /// PointerType.
Type *getPointerOperandType() const { Type *getPointerOperandType() const {
return getPointerOperand()->getType(); return getPointerOperand()->getType();
} }
/// \brief Returns the address space of the pointer operand.
unsigned getPointerAddressSpace() const {
return getPointerOperandType()->getPointerAddressSpace();
}
/// GetGEPReturnType - Returns the pointer type returned by the GEP /// GetGEPReturnType - Returns the pointer type returned by the GEP
/// instruction, which may be a vector of pointers. /// instruction, which may be a vector of pointers.
static Type *getGEPReturnType(Value *Ptr, ArrayRef<Value *> IdxList) { static Type *getGEPReturnType(Value *Ptr, ArrayRef<Value *> IdxList) {
Type *PtrTy = PointerType::get(checkGEPType( Type *PtrTy = PointerType::get(checkGEPType(
getIndexedType(Ptr->getType(), IdxList)) , getIndexedType(Ptr->getType(), IdxList)) ,
getAddressSpace(Ptr)); Ptr->getType()->getPointerAddressSpace() );
// Vector GEP // Vector GEP
if (Ptr->getType()->isVectorTy()) { if (Ptr->getType()->isVectorTy()) {
unsigned NumElem = cast<VectorType>(Ptr->getType())->getNumElements() ; unsigned NumElem = cast<VectorType>(Ptr->getType())->getNumElements() ;
return VectorType::get(PtrTy, NumElem); return VectorType::get(PtrTy, NumElem);
} }
// Scalar GEP // Scalar GEP
return PtrTy; return PtrTy;
} }
skipping to change at line 846 skipping to change at line 850
bool hasAllConstantIndices() const; bool hasAllConstantIndices() const;
/// setIsInBounds - Set or clear the inbounds flag on this GEP instructio n. /// setIsInBounds - Set or clear the inbounds flag on this GEP instructio n.
/// See LangRef.html for the meaning of inbounds on a getelementptr. /// See LangRef.html for the meaning of inbounds on a getelementptr.
void setIsInBounds(bool b = true); void setIsInBounds(bool b = true);
/// isInBounds - Determine whether the GEP has the inbounds flag. /// isInBounds - Determine whether the GEP has the inbounds flag.
bool isInBounds() const; bool isInBounds() const;
// Methods for support type inquiry through isa, cast, and dyn_cast: // Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const GetElementPtrInst *) { return true; }
static inline bool classof(const Instruction *I) { static inline bool classof(const Instruction *I) {
return (I->getOpcode() == Instruction::GetElementPtr); return (I->getOpcode() == Instruction::GetElementPtr);
} }
static inline bool classof(const Value *V) { static inline bool classof(const Value *V) {
return isa<Instruction>(V) && classof(cast<Instruction>(V)); return isa<Instruction>(V) && classof(cast<Instruction>(V));
} }
}; };
template <> template <>
struct OperandTraits<GetElementPtrInst> : struct OperandTraits<GetElementPtrInst> :
skipping to change at line 892 skipping to change at line 895
DEFINE_TRANSPARENT_OPERAND_ACCESSORS(GetElementPtrInst, Value) DEFINE_TRANSPARENT_OPERAND_ACCESSORS(GetElementPtrInst, Value)
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// ICmpInst Class // ICmpInst Class
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
/// This instruction compares its operands according to the predicate given /// This instruction compares its operands according to the predicate given
/// to the constructor. It only operates on integers or pointers. The opera nds /// to the constructor. It only operates on integers or pointers. The opera nds
/// must be identical types. /// must be identical types.
/// @brief Represent an integer comparison operator. /// \brief Represent an integer comparison operator.
class ICmpInst: public CmpInst { class ICmpInst: public CmpInst {
protected: protected:
/// @brief Clone an identical ICmpInst /// \brief Clone an identical ICmpInst
virtual ICmpInst *clone_impl() const; virtual ICmpInst *clone_impl() const;
public: public:
/// @brief Constructor with insert-before-instruction semantics. /// \brief Constructor with insert-before-instruction semantics.
ICmpInst( ICmpInst(
Instruction *InsertBefore, ///< Where to insert Instruction *InsertBefore, ///< Where to insert
Predicate pred, ///< The predicate to use for the comparison Predicate pred, ///< The predicate to use for the comparison
Value *LHS, ///< The left-hand-side of the expression Value *LHS, ///< The left-hand-side of the expression
Value *RHS, ///< The right-hand-side of the expression Value *RHS, ///< The right-hand-side of the expression
const Twine &NameStr = "" ///< Name of the instruction const Twine &NameStr = "" ///< Name of the instruction
) : CmpInst(makeCmpResultType(LHS->getType()), ) : CmpInst(makeCmpResultType(LHS->getType()),
Instruction::ICmp, pred, LHS, RHS, NameStr, Instruction::ICmp, pred, LHS, RHS, NameStr,
InsertBefore) { InsertBefore) {
assert(pred >= CmpInst::FIRST_ICMP_PREDICATE && assert(pred >= CmpInst::FIRST_ICMP_PREDICATE &&
pred <= CmpInst::LAST_ICMP_PREDICATE && pred <= CmpInst::LAST_ICMP_PREDICATE &&
"Invalid ICmp predicate value"); "Invalid ICmp predicate value");
assert(getOperand(0)->getType() == getOperand(1)->getType() && assert(getOperand(0)->getType() == getOperand(1)->getType() &&
"Both operands to ICmp instruction are not of the same type!"); "Both operands to ICmp instruction are not of the same type!");
// Check that the operands are the right type // Check that the operands are the right type
assert((getOperand(0)->getType()->isIntOrIntVectorTy() || assert((getOperand(0)->getType()->isIntOrIntVectorTy() ||
getOperand(0)->getType()->getScalarType()->isPointerTy()) && getOperand(0)->getType()->getScalarType()->isPointerTy()) &&
"Invalid operand types for ICmp instruction"); "Invalid operand types for ICmp instruction");
} }
/// @brief Constructor with insert-at-end semantics. /// \brief Constructor with insert-at-end semantics.
ICmpInst( ICmpInst(
BasicBlock &InsertAtEnd, ///< Block to insert into. BasicBlock &InsertAtEnd, ///< Block to insert into.
Predicate pred, ///< The predicate to use for the comparison Predicate pred, ///< The predicate to use for the comparison
Value *LHS, ///< The left-hand-side of the expression Value *LHS, ///< The left-hand-side of the expression
Value *RHS, ///< The right-hand-side of the expression Value *RHS, ///< The right-hand-side of the expression
const Twine &NameStr = "" ///< Name of the instruction const Twine &NameStr = "" ///< Name of the instruction
) : CmpInst(makeCmpResultType(LHS->getType()), ) : CmpInst(makeCmpResultType(LHS->getType()),
Instruction::ICmp, pred, LHS, RHS, NameStr, Instruction::ICmp, pred, LHS, RHS, NameStr,
&InsertAtEnd) { &InsertAtEnd) {
assert(pred >= CmpInst::FIRST_ICMP_PREDICATE && assert(pred >= CmpInst::FIRST_ICMP_PREDICATE &&
pred <= CmpInst::LAST_ICMP_PREDICATE && pred <= CmpInst::LAST_ICMP_PREDICATE &&
"Invalid ICmp predicate value"); "Invalid ICmp predicate value");
assert(getOperand(0)->getType() == getOperand(1)->getType() && assert(getOperand(0)->getType() == getOperand(1)->getType() &&
"Both operands to ICmp instruction are not of the same type!"); "Both operands to ICmp instruction are not of the same type!");
// Check that the operands are the right type // Check that the operands are the right type
assert((getOperand(0)->getType()->isIntOrIntVectorTy() || assert((getOperand(0)->getType()->isIntOrIntVectorTy() ||
getOperand(0)->getType()->isPointerTy()) && getOperand(0)->getType()->isPointerTy()) &&
"Invalid operand types for ICmp instruction"); "Invalid operand types for ICmp instruction");
} }
/// @brief Constructor with no-insertion semantics /// \brief Constructor with no-insertion semantics
ICmpInst( ICmpInst(
Predicate pred, ///< The predicate to use for the comparison Predicate pred, ///< The predicate to use for the comparison
Value *LHS, ///< The left-hand-side of the expression Value *LHS, ///< The left-hand-side of the expression
Value *RHS, ///< The right-hand-side of the expression Value *RHS, ///< The right-hand-side of the expression
const Twine &NameStr = "" ///< Name of the instruction const Twine &NameStr = "" ///< Name of the instruction
) : CmpInst(makeCmpResultType(LHS->getType()), ) : CmpInst(makeCmpResultType(LHS->getType()),
Instruction::ICmp, pred, LHS, RHS, NameStr) { Instruction::ICmp, pred, LHS, RHS, NameStr) {
assert(pred >= CmpInst::FIRST_ICMP_PREDICATE && assert(pred >= CmpInst::FIRST_ICMP_PREDICATE &&
pred <= CmpInst::LAST_ICMP_PREDICATE && pred <= CmpInst::LAST_ICMP_PREDICATE &&
"Invalid ICmp predicate value"); "Invalid ICmp predicate value");
skipping to change at line 962 skipping to change at line 965
"Both operands to ICmp instruction are not of the same type!"); "Both operands to ICmp instruction are not of the same type!");
// Check that the operands are the right type // Check that the operands are the right type
assert((getOperand(0)->getType()->isIntOrIntVectorTy() || assert((getOperand(0)->getType()->isIntOrIntVectorTy() ||
getOperand(0)->getType()->getScalarType()->isPointerTy()) && getOperand(0)->getType()->getScalarType()->isPointerTy()) &&
"Invalid operand types for ICmp instruction"); "Invalid operand types for ICmp instruction");
} }
/// For example, EQ->EQ, SLE->SLE, UGT->SGT, etc. /// For example, EQ->EQ, SLE->SLE, UGT->SGT, etc.
/// @returns the predicate that would be the result if the operand were /// @returns the predicate that would be the result if the operand were
/// regarded as signed. /// regarded as signed.
/// @brief Return the signed version of the predicate /// \brief Return the signed version of the predicate
Predicate getSignedPredicate() const { Predicate getSignedPredicate() const {
return getSignedPredicate(getPredicate()); return getSignedPredicate(getPredicate());
} }
/// This is a static version that you can use without an instruction. /// This is a static version that you can use without an instruction.
/// @brief Return the signed version of the predicate. /// \brief Return the signed version of the predicate.
static Predicate getSignedPredicate(Predicate pred); static Predicate getSignedPredicate(Predicate pred);
/// For example, EQ->EQ, SLE->ULE, UGT->UGT, etc. /// For example, EQ->EQ, SLE->ULE, UGT->UGT, etc.
/// @returns the predicate that would be the result if the operand were /// @returns the predicate that would be the result if the operand were
/// regarded as unsigned. /// regarded as unsigned.
/// @brief Return the unsigned version of the predicate /// \brief Return the unsigned version of the predicate
Predicate getUnsignedPredicate() const { Predicate getUnsignedPredicate() const {
return getUnsignedPredicate(getPredicate()); return getUnsignedPredicate(getPredicate());
} }
/// This is a static version that you can use without an instruction. /// This is a static version that you can use without an instruction.
/// @brief Return the unsigned version of the predicate. /// \brief Return the unsigned version of the predicate.
static Predicate getUnsignedPredicate(Predicate pred); static Predicate getUnsignedPredicate(Predicate pred);
/// isEquality - Return true if this predicate is either EQ or NE. This also /// isEquality - Return true if this predicate is either EQ or NE. This also
/// tests for commutativity. /// tests for commutativity.
static bool isEquality(Predicate P) { static bool isEquality(Predicate P) {
return P == ICMP_EQ || P == ICMP_NE; return P == ICMP_EQ || P == ICMP_NE;
} }
/// isEquality - Return true if this predicate is either EQ or NE. This also /// isEquality - Return true if this predicate is either EQ or NE. This also
/// tests for commutativity. /// tests for commutativity.
bool isEquality() const { bool isEquality() const {
return isEquality(getPredicate()); return isEquality(getPredicate());
} }
/// @returns true if the predicate of this ICmpInst is commutative /// @returns true if the predicate of this ICmpInst is commutative
/// @brief Determine if this relation is commutative. /// \brief Determine if this relation is commutative.
bool isCommutative() const { return isEquality(); } bool isCommutative() const { return isEquality(); }
/// isRelational - Return true if the predicate is relational (not EQ or NE). /// isRelational - Return true if the predicate is relational (not EQ or NE).
/// ///
bool isRelational() const { bool isRelational() const {
return !isEquality(); return !isEquality();
} }
/// isRelational - Return true if the predicate is relational (not EQ or NE). /// isRelational - Return true if the predicate is relational (not EQ or NE).
/// ///
static bool isRelational(Predicate P) { static bool isRelational(Predicate P) {
return !isEquality(P); return !isEquality(P);
} }
/// Initialize a set of values that all satisfy the predicate with C. /// Initialize a set of values that all satisfy the predicate with C.
/// @brief Make a ConstantRange for a relation with a constant value. /// \brief Make a ConstantRange for a relation with a constant value.
static ConstantRange makeConstantRange(Predicate pred, const APInt &C); static ConstantRange makeConstantRange(Predicate pred, const APInt &C);
/// Exchange the two operands to this instruction in such a way that it d oes /// Exchange the two operands to this instruction in such a way that it d oes
/// not modify the semantics of the instruction. The predicate value may be /// not modify the semantics of the instruction. The predicate value may be
/// changed to retain the same result if the predicate is order dependent /// changed to retain the same result if the predicate is order dependent
/// (e.g. ult). /// (e.g. ult).
/// @brief Swap operands and adjust predicate. /// \brief Swap operands and adjust predicate.
void swapOperands() { void swapOperands() {
setPredicate(getSwappedPredicate()); setPredicate(getSwappedPredicate());
Op<0>().swap(Op<1>()); Op<0>().swap(Op<1>());
} }
// Methods for support type inquiry through isa, cast, and dyn_cast: // Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const ICmpInst *) { return true; }
static inline bool classof(const Instruction *I) { static inline bool classof(const Instruction *I) {
return I->getOpcode() == Instruction::ICmp; return I->getOpcode() == Instruction::ICmp;
} }
static inline bool classof(const Value *V) { static inline bool classof(const Value *V) {
return isa<Instruction>(V) && classof(cast<Instruction>(V)); return isa<Instruction>(V) && classof(cast<Instruction>(V));
} }
}; };
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// FCmpInst Class // FCmpInst Class
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
/// This instruction compares its operands according to the predicate given /// This instruction compares its operands according to the predicate given
/// to the constructor. It only operates on floating point values or packed /// to the constructor. It only operates on floating point values or packed
/// vectors of floating point values. The operands must be identical types. /// vectors of floating point values. The operands must be identical types.
/// @brief Represents a floating point comparison operator. /// \brief Represents a floating point comparison operator.
class FCmpInst: public CmpInst { class FCmpInst: public CmpInst {
protected: protected:
/// @brief Clone an identical FCmpInst /// \brief Clone an identical FCmpInst
virtual FCmpInst *clone_impl() const; virtual FCmpInst *clone_impl() const;
public: public:
/// @brief Constructor with insert-before-instruction semantics. /// \brief Constructor with insert-before-instruction semantics.
FCmpInst( FCmpInst(
Instruction *InsertBefore, ///< Where to insert Instruction *InsertBefore, ///< Where to insert
Predicate pred, ///< The predicate to use for the comparison Predicate pred, ///< The predicate to use for the comparison
Value *LHS, ///< The left-hand-side of the expression Value *LHS, ///< The left-hand-side of the expression
Value *RHS, ///< The right-hand-side of the expression Value *RHS, ///< The right-hand-side of the expression
const Twine &NameStr = "" ///< Name of the instruction const Twine &NameStr = "" ///< Name of the instruction
) : CmpInst(makeCmpResultType(LHS->getType()), ) : CmpInst(makeCmpResultType(LHS->getType()),
Instruction::FCmp, pred, LHS, RHS, NameStr, Instruction::FCmp, pred, LHS, RHS, NameStr,
InsertBefore) { InsertBefore) {
assert(pred <= FCmpInst::LAST_FCMP_PREDICATE && assert(pred <= FCmpInst::LAST_FCMP_PREDICATE &&
"Invalid FCmp predicate value"); "Invalid FCmp predicate value");
assert(getOperand(0)->getType() == getOperand(1)->getType() && assert(getOperand(0)->getType() == getOperand(1)->getType() &&
"Both operands to FCmp instruction are not of the same type!"); "Both operands to FCmp instruction are not of the same type!");
// Check that the operands are the right type // Check that the operands are the right type
assert(getOperand(0)->getType()->isFPOrFPVectorTy() && assert(getOperand(0)->getType()->isFPOrFPVectorTy() &&
"Invalid operand types for FCmp instruction"); "Invalid operand types for FCmp instruction");
} }
/// @brief Constructor with insert-at-end semantics. /// \brief Constructor with insert-at-end semantics.
FCmpInst( FCmpInst(
BasicBlock &InsertAtEnd, ///< Block to insert into. BasicBlock &InsertAtEnd, ///< Block to insert into.
Predicate pred, ///< The predicate to use for the comparison Predicate pred, ///< The predicate to use for the comparison
Value *LHS, ///< The left-hand-side of the expression Value *LHS, ///< The left-hand-side of the expression
Value *RHS, ///< The right-hand-side of the expression Value *RHS, ///< The right-hand-side of the expression
const Twine &NameStr = "" ///< Name of the instruction const Twine &NameStr = "" ///< Name of the instruction
) : CmpInst(makeCmpResultType(LHS->getType()), ) : CmpInst(makeCmpResultType(LHS->getType()),
Instruction::FCmp, pred, LHS, RHS, NameStr, Instruction::FCmp, pred, LHS, RHS, NameStr,
&InsertAtEnd) { &InsertAtEnd) {
assert(pred <= FCmpInst::LAST_FCMP_PREDICATE && assert(pred <= FCmpInst::LAST_FCMP_PREDICATE &&
"Invalid FCmp predicate value"); "Invalid FCmp predicate value");
assert(getOperand(0)->getType() == getOperand(1)->getType() && assert(getOperand(0)->getType() == getOperand(1)->getType() &&
"Both operands to FCmp instruction are not of the same type!"); "Both operands to FCmp instruction are not of the same type!");
// Check that the operands are the right type // Check that the operands are the right type
assert(getOperand(0)->getType()->isFPOrFPVectorTy() && assert(getOperand(0)->getType()->isFPOrFPVectorTy() &&
"Invalid operand types for FCmp instruction"); "Invalid operand types for FCmp instruction");
} }
/// @brief Constructor with no-insertion semantics /// \brief Constructor with no-insertion semantics
FCmpInst( FCmpInst(
Predicate pred, ///< The predicate to use for the comparison Predicate pred, ///< The predicate to use for the comparison
Value *LHS, ///< The left-hand-side of the expression Value *LHS, ///< The left-hand-side of the expression
Value *RHS, ///< The right-hand-side of the expression Value *RHS, ///< The right-hand-side of the expression
const Twine &NameStr = "" ///< Name of the instruction const Twine &NameStr = "" ///< Name of the instruction
) : CmpInst(makeCmpResultType(LHS->getType()), ) : CmpInst(makeCmpResultType(LHS->getType()),
Instruction::FCmp, pred, LHS, RHS, NameStr) { Instruction::FCmp, pred, LHS, RHS, NameStr) {
assert(pred <= FCmpInst::LAST_FCMP_PREDICATE && assert(pred <= FCmpInst::LAST_FCMP_PREDICATE &&
"Invalid FCmp predicate value"); "Invalid FCmp predicate value");
assert(getOperand(0)->getType() == getOperand(1)->getType() && assert(getOperand(0)->getType() == getOperand(1)->getType() &&
"Both operands to FCmp instruction are not of the same type!"); "Both operands to FCmp instruction are not of the same type!");
// Check that the operands are the right type // Check that the operands are the right type
assert(getOperand(0)->getType()->isFPOrFPVectorTy() && assert(getOperand(0)->getType()->isFPOrFPVectorTy() &&
"Invalid operand types for FCmp instruction"); "Invalid operand types for FCmp instruction");
} }
/// @returns true if the predicate of this instruction is EQ or NE. /// @returns true if the predicate of this instruction is EQ or NE.
/// @brief Determine if this is an equality predicate. /// \brief Determine if this is an equality predicate.
bool isEquality() const { bool isEquality() const {
return getPredicate() == FCMP_OEQ || getPredicate() == FCMP_ONE || return getPredicate() == FCMP_OEQ || getPredicate() == FCMP_ONE ||
getPredicate() == FCMP_UEQ || getPredicate() == FCMP_UNE; getPredicate() == FCMP_UEQ || getPredicate() == FCMP_UNE;
} }
/// @returns true if the predicate of this instruction is commutative. /// @returns true if the predicate of this instruction is commutative.
/// @brief Determine if this is a commutative predicate. /// \brief Determine if this is a commutative predicate.
bool isCommutative() const { bool isCommutative() const {
return isEquality() || return isEquality() ||
getPredicate() == FCMP_FALSE || getPredicate() == FCMP_FALSE ||
getPredicate() == FCMP_TRUE || getPredicate() == FCMP_TRUE ||
getPredicate() == FCMP_ORD || getPredicate() == FCMP_ORD ||
getPredicate() == FCMP_UNO; getPredicate() == FCMP_UNO;
} }
/// @returns true if the predicate is relational (not EQ or NE). /// @returns true if the predicate is relational (not EQ or NE).
/// @brief Determine if this a relational predicate. /// \brief Determine if this a relational predicate.
bool isRelational() const { return !isEquality(); } bool isRelational() const { return !isEquality(); }
/// Exchange the two operands to this instruction in such a way that it d oes /// Exchange the two operands to this instruction in such a way that it d oes
/// not modify the semantics of the instruction. The predicate value may be /// not modify the semantics of the instruction. The predicate value may be
/// changed to retain the same result if the predicate is order dependent /// changed to retain the same result if the predicate is order dependent
/// (e.g. ult). /// (e.g. ult).
/// @brief Swap operands and adjust predicate. /// \brief Swap operands and adjust predicate.
void swapOperands() { void swapOperands() {
setPredicate(getSwappedPredicate()); setPredicate(getSwappedPredicate());
Op<0>().swap(Op<1>()); Op<0>().swap(Op<1>());
} }
/// @brief Methods for support type inquiry through isa, cast, and dyn_ca /// \brief Methods for support type inquiry through isa, cast, and dyn_ca
st: st:
static inline bool classof(const FCmpInst *) { return true; }
static inline bool classof(const Instruction *I) { static inline bool classof(const Instruction *I) {
return I->getOpcode() == Instruction::FCmp; return I->getOpcode() == Instruction::FCmp;
} }
static inline bool classof(const Value *V) { static inline bool classof(const Value *V) {
return isa<Instruction>(V) && classof(cast<Instruction>(V)); return isa<Instruction>(V) && classof(cast<Instruction>(V));
} }
}; };
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
/// CallInst - This class represents a function call, abstracting a target /// CallInst - This class represents a function call, abstracting a target
skipping to change at line 1158 skipping to change at line 1159
/// field to indicate whether or not this is a tail call. The rest of the bits /// field to indicate whether or not this is a tail call. The rest of the bits
/// hold the calling convention of the call. /// hold the calling convention of the call.
/// ///
class CallInst : public Instruction { class CallInst : public Instruction {
AttrListPtr AttributeList; ///< parameter attributes for call AttrListPtr AttributeList; ///< parameter attributes for call
CallInst(const CallInst &CI); CallInst(const CallInst &CI);
void init(Value *Func, ArrayRef<Value *> Args, const Twine &NameStr); void init(Value *Func, ArrayRef<Value *> Args, const Twine &NameStr);
void init(Value *Func, const Twine &NameStr); void init(Value *Func, const Twine &NameStr);
/// Construct a CallInst given a range of arguments. /// Construct a CallInst given a range of arguments.
/// @brief Construct a CallInst from a range of arguments /// \brief Construct a CallInst from a range of arguments
inline CallInst(Value *Func, ArrayRef<Value *> Args, inline CallInst(Value *Func, ArrayRef<Value *> Args,
const Twine &NameStr, Instruction *InsertBefore); const Twine &NameStr, Instruction *InsertBefore);
/// Construct a CallInst given a range of arguments. /// Construct a CallInst given a range of arguments.
/// @brief Construct a CallInst from a range of arguments /// \brief Construct a CallInst from a range of arguments
inline CallInst(Value *Func, ArrayRef<Value *> Args, inline CallInst(Value *Func, ArrayRef<Value *> Args,
const Twine &NameStr, BasicBlock *InsertAtEnd); const Twine &NameStr, BasicBlock *InsertAtEnd);
CallInst(Value *F, Value *Actual, const Twine &NameStr, CallInst(Value *F, Value *Actual, const Twine &NameStr,
Instruction *InsertBefore); Instruction *InsertBefore);
CallInst(Value *F, Value *Actual, const Twine &NameStr, CallInst(Value *F, Value *Actual, const Twine &NameStr,
BasicBlock *InsertAtEnd); BasicBlock *InsertAtEnd);
explicit CallInst(Value *F, const Twine &NameStr, explicit CallInst(Value *F, const Twine &NameStr,
Instruction *InsertBefore); Instruction *InsertBefore);
CallInst(Value *F, const Twine &NameStr, BasicBlock *InsertAtEnd); CallInst(Value *F, const Twine &NameStr, BasicBlock *InsertAtEnd);
skipping to change at line 1262 skipping to change at line 1263
/// setAttributes - Set the parameter attributes for this call. /// setAttributes - Set the parameter attributes for this call.
/// ///
void setAttributes(const AttrListPtr &Attrs) { AttributeList = Attrs; } void setAttributes(const AttrListPtr &Attrs) { AttributeList = Attrs; }
/// addAttribute - adds the attribute to the list of attributes. /// addAttribute - adds the attribute to the list of attributes.
void addAttribute(unsigned i, Attributes attr); void addAttribute(unsigned i, Attributes attr);
/// removeAttribute - removes the attribute from the list of attributes. /// removeAttribute - removes the attribute from the list of attributes.
void removeAttribute(unsigned i, Attributes attr); void removeAttribute(unsigned i, Attributes attr);
/// @brief Determine whether the call or the callee has the given attribu /// \brief Determine whether this call has the given attribute.
te. bool hasFnAttr(Attributes::AttrVal A) const;
bool paramHasAttr(unsigned i, Attributes attr) const;
/// @brief Extract the alignment for a call or parameter (0=unknown). /// \brief Determine whether the call or the callee has the given attribu
tes.
bool paramHasAttr(unsigned i, Attributes::AttrVal A) const;
/// \brief Extract the alignment for a call or parameter (0=unknown).
unsigned getParamAlignment(unsigned i) const { unsigned getParamAlignment(unsigned i) const {
return AttributeList.getParamAlignment(i); return AttributeList.getParamAlignment(i);
} }
/// @brief Return true if the call should not be inlined. /// \brief Return true if the call should not be inlined.
bool isNoInline() const { return paramHasAttr(~0, Attribute::NoInline); } bool isNoInline() const { return hasFnAttr(Attributes::NoInline); }
void setIsNoInline(bool Value = true) { void setIsNoInline() {
if (Value) addAttribute(~0, Attribute::NoInline); addAttribute(AttrListPtr::FunctionIndex,
else removeAttribute(~0, Attribute::NoInline); Attributes::get(getContext(), Attributes::NoInline));
} }
/// @brief Return true if the call can return twice /// \brief Return true if the call can return twice
bool canReturnTwice() const { bool canReturnTwice() const {
return paramHasAttr(~0, Attribute::ReturnsTwice); return hasFnAttr(Attributes::ReturnsTwice);
} }
void setCanReturnTwice(bool Value = true) { void setCanReturnTwice() {
if (Value) addAttribute(~0, Attribute::ReturnsTwice); addAttribute(AttrListPtr::FunctionIndex,
else removeAttribute(~0, Attribute::ReturnsTwice); Attributes::get(getContext(), Attributes::ReturnsTwice));
} }
/// @brief Determine if the call does not access memory. /// \brief Determine if the call does not access memory.
bool doesNotAccessMemory() const { bool doesNotAccessMemory() const {
return paramHasAttr(~0, Attribute::ReadNone); return hasFnAttr(Attributes::ReadNone);
} }
void setDoesNotAccessMemory(bool NotAccessMemory = true) { void setDoesNotAccessMemory() {
if (NotAccessMemory) addAttribute(~0, Attribute::ReadNone); addAttribute(AttrListPtr::FunctionIndex,
else removeAttribute(~0, Attribute::ReadNone); Attributes::get(getContext(), Attributes::ReadNone));
} }
/// @brief Determine if the call does not access or only reads memory. /// \brief Determine if the call does not access or only reads memory.
bool onlyReadsMemory() const { bool onlyReadsMemory() const {
return doesNotAccessMemory() || paramHasAttr(~0, Attribute::ReadOnly); return doesNotAccessMemory() || hasFnAttr(Attributes::ReadOnly);
} }
void setOnlyReadsMemory(bool OnlyReadsMemory = true) { void setOnlyReadsMemory() {
if (OnlyReadsMemory) addAttribute(~0, Attribute::ReadOnly); addAttribute(AttrListPtr::FunctionIndex,
else removeAttribute(~0, Attribute::ReadOnly | Attribute::ReadNone); Attributes::get(getContext(), Attributes::ReadOnly));
} }
/// @brief Determine if the call cannot return. /// \brief Determine if the call cannot return.
bool doesNotReturn() const { return paramHasAttr(~0, Attribute::NoReturn) bool doesNotReturn() const { return hasFnAttr(Attributes::NoReturn); }
; } void setDoesNotReturn() {
void setDoesNotReturn(bool DoesNotReturn = true) { addAttribute(AttrListPtr::FunctionIndex,
if (DoesNotReturn) addAttribute(~0, Attribute::NoReturn); Attributes::get(getContext(), Attributes::NoReturn));
else removeAttribute(~0, Attribute::NoReturn);
} }
/// @brief Determine if the call cannot unwind. /// \brief Determine if the call cannot unwind.
bool doesNotThrow() const { return paramHasAttr(~0, Attribute::NoUnwind); bool doesNotThrow() const { return hasFnAttr(Attributes::NoUnwind); }
} void setDoesNotThrow() {
void setDoesNotThrow(bool DoesNotThrow = true) { addAttribute(AttrListPtr::FunctionIndex,
if (DoesNotThrow) addAttribute(~0, Attribute::NoUnwind); Attributes::get(getContext(), Attributes::NoUnwind));
else removeAttribute(~0, Attribute::NoUnwind);
} }
/// @brief Determine if the call returns a structure through first /// \brief Determine if the call returns a structure through first
/// pointer argument. /// pointer argument.
bool hasStructRetAttr() const { bool hasStructRetAttr() const {
// Be friendly and also check the callee. // Be friendly and also check the callee.
return paramHasAttr(1, Attribute::StructRet); return paramHasAttr(1, Attributes::StructRet);
} }
/// @brief Determine if any call argument is an aggregate passed by value . /// \brief Determine if any call argument is an aggregate passed by value .
bool hasByValArgument() const { bool hasByValArgument() const {
return AttributeList.hasAttrSomewhere(Attribute::ByVal); for (unsigned I = 0, E = AttributeList.getNumAttrs(); I != E; ++I)
if (AttributeList.getAttributesAtIndex(I).hasAttribute(Attributes::By
Val))
return true;
return false;
} }
/// getCalledFunction - Return the function called, or null if this is an /// getCalledFunction - Return the function called, or null if this is an
/// indirect function invocation. /// indirect function invocation.
/// ///
Function *getCalledFunction() const { Function *getCalledFunction() const {
return dyn_cast<Function>(Op<-1>()); return dyn_cast<Function>(Op<-1>());
} }
/// getCalledValue - Get a pointer to the function that is invoked by thi s /// getCalledValue - Get a pointer to the function that is invoked by thi s
skipping to change at line 1353 skipping to change at line 1360
void setCalledFunction(Value* Fn) { void setCalledFunction(Value* Fn) {
Op<-1>() = Fn; Op<-1>() = Fn;
} }
/// isInlineAsm - Check if this call is an inline asm statement. /// isInlineAsm - Check if this call is an inline asm statement.
bool isInlineAsm() const { bool isInlineAsm() const {
return isa<InlineAsm>(Op<-1>()); return isa<InlineAsm>(Op<-1>());
} }
// Methods for support type inquiry through isa, cast, and dyn_cast: // Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const CallInst *) { return true; }
static inline bool classof(const Instruction *I) { static inline bool classof(const Instruction *I) {
return I->getOpcode() == Instruction::Call; return I->getOpcode() == Instruction::Call;
} }
static inline bool classof(const Value *V) { static inline bool classof(const Value *V) {
return isa<Instruction>(V) && classof(cast<Instruction>(V)); return isa<Instruction>(V) && classof(cast<Instruction>(V));
} }
private: private:
// Shadow Instruction::setInstructionSubclassData with a private forwardi ng // Shadow Instruction::setInstructionSubclassData with a private forwardi ng
// method so that subclasses cannot accidentally use it. // method so that subclasses cannot accidentally use it.
void setInstructionSubclassData(unsigned short D) { void setInstructionSubclassData(unsigned short D) {
skipping to change at line 1458 skipping to change at line 1464
static const char *areInvalidOperands(Value *Cond, Value *True, Value *Fa lse); static const char *areInvalidOperands(Value *Cond, Value *True, Value *Fa lse);
/// Transparently provide more efficient getOperand methods. /// Transparently provide more efficient getOperand methods.
DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value); DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value);
OtherOps getOpcode() const { OtherOps getOpcode() const {
return static_cast<OtherOps>(Instruction::getOpcode()); return static_cast<OtherOps>(Instruction::getOpcode());
} }
// Methods for support type inquiry through isa, cast, and dyn_cast: // Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const SelectInst *) { return true; }
static inline bool classof(const Instruction *I) { static inline bool classof(const Instruction *I) {
return I->getOpcode() == Instruction::Select; return I->getOpcode() == Instruction::Select;
} }
static inline bool classof(const Value *V) { static inline bool classof(const Value *V) {
return isa<Instruction>(V) && classof(cast<Instruction>(V)); return isa<Instruction>(V) && classof(cast<Instruction>(V));
} }
}; };
template <> template <>
struct OperandTraits<SelectInst> : public FixedNumOperandTraits<SelectInst, 3> { struct OperandTraits<SelectInst> : public FixedNumOperandTraits<SelectInst, 3> {
skipping to change at line 1501 skipping to change at line 1506
BasicBlock *InsertAtEnd) BasicBlock *InsertAtEnd)
: UnaryInstruction(Ty, VAArg, List, InsertAtEnd) { : UnaryInstruction(Ty, VAArg, List, InsertAtEnd) {
setName(NameStr); setName(NameStr);
} }
Value *getPointerOperand() { return getOperand(0); } Value *getPointerOperand() { return getOperand(0); }
const Value *getPointerOperand() const { return getOperand(0); } const Value *getPointerOperand() const { return getOperand(0); }
static unsigned getPointerOperandIndex() { return 0U; } static unsigned getPointerOperandIndex() { return 0U; }
// Methods for support type inquiry through isa, cast, and dyn_cast: // Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const VAArgInst *) { return true; }
static inline bool classof(const Instruction *I) { static inline bool classof(const Instruction *I) {
return I->getOpcode() == VAArg; return I->getOpcode() == VAArg;
} }
static inline bool classof(const Value *V) { static inline bool classof(const Value *V) {
return isa<Instruction>(V) && classof(cast<Instruction>(V)); return isa<Instruction>(V) && classof(cast<Instruction>(V));
} }
}; };
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// ExtractElementInst Class // ExtractElementInst Class
skipping to change at line 1554 skipping to change at line 1558
const Value *getIndexOperand() const { return Op<1>(); } const Value *getIndexOperand() const { return Op<1>(); }
VectorType *getVectorOperandType() const { VectorType *getVectorOperandType() const {
return reinterpret_cast<VectorType*>(getVectorOperand()->getType()); return reinterpret_cast<VectorType*>(getVectorOperand()->getType());
} }
/// Transparently provide more efficient getOperand methods. /// Transparently provide more efficient getOperand methods.
DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value); DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value);
// Methods for support type inquiry through isa, cast, and dyn_cast: // Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const ExtractElementInst *) { return true; }
static inline bool classof(const Instruction *I) { static inline bool classof(const Instruction *I) {
return I->getOpcode() == Instruction::ExtractElement; return I->getOpcode() == Instruction::ExtractElement;
} }
static inline bool classof(const Value *V) { static inline bool classof(const Value *V) {
return isa<Instruction>(V) && classof(cast<Instruction>(V)); return isa<Instruction>(V) && classof(cast<Instruction>(V));
} }
}; };
template <> template <>
struct OperandTraits<ExtractElementInst> : struct OperandTraits<ExtractElementInst> :
skipping to change at line 1613 skipping to change at line 1616
/// getType - Overload to return most specific vector type. /// getType - Overload to return most specific vector type.
/// ///
VectorType *getType() const { VectorType *getType() const {
return reinterpret_cast<VectorType*>(Instruction::getType()); return reinterpret_cast<VectorType*>(Instruction::getType());
} }
/// Transparently provide more efficient getOperand methods. /// Transparently provide more efficient getOperand methods.
DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value); DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value);
// Methods for support type inquiry through isa, cast, and dyn_cast: // Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const InsertElementInst *) { return true; }
static inline bool classof(const Instruction *I) { static inline bool classof(const Instruction *I) {
return I->getOpcode() == Instruction::InsertElement; return I->getOpcode() == Instruction::InsertElement;
} }
static inline bool classof(const Value *V) { static inline bool classof(const Value *V) {
return isa<Instruction>(V) && classof(cast<Instruction>(V)); return isa<Instruction>(V) && classof(cast<Instruction>(V));
} }
}; };
template <> template <>
struct OperandTraits<InsertElementInst> : struct OperandTraits<InsertElementInst> :
skipping to change at line 1693 skipping to change at line 1695
return getShuffleMask(getMask(), Result); return getShuffleMask(getMask(), Result);
} }
SmallVector<int, 16> getShuffleMask() const { SmallVector<int, 16> getShuffleMask() const {
SmallVector<int, 16> Mask; SmallVector<int, 16> Mask;
getShuffleMask(Mask); getShuffleMask(Mask);
return Mask; return Mask;
} }
// Methods for support type inquiry through isa, cast, and dyn_cast: // Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const ShuffleVectorInst *) { return true; }
static inline bool classof(const Instruction *I) { static inline bool classof(const Instruction *I) {
return I->getOpcode() == Instruction::ShuffleVector; return I->getOpcode() == Instruction::ShuffleVector;
} }
static inline bool classof(const Value *V) { static inline bool classof(const Value *V) {
return isa<Instruction>(V) && classof(cast<Instruction>(V)); return isa<Instruction>(V) && classof(cast<Instruction>(V));
} }
}; };
template <> template <>
struct OperandTraits<ShuffleVectorInst> : struct OperandTraits<ShuffleVectorInst> :
skipping to change at line 1789 skipping to change at line 1790
unsigned getNumIndices() const { unsigned getNumIndices() const {
return (unsigned)Indices.size(); return (unsigned)Indices.size();
} }
bool hasIndices() const { bool hasIndices() const {
return true; return true;
} }
// Methods for support type inquiry through isa, cast, and dyn_cast: // Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const ExtractValueInst *) { return true; }
static inline bool classof(const Instruction *I) { static inline bool classof(const Instruction *I) {
return I->getOpcode() == Instruction::ExtractValue; return I->getOpcode() == Instruction::ExtractValue;
} }
static inline bool classof(const Value *V) { static inline bool classof(const Value *V) {
return isa<Instruction>(V) && classof(cast<Instruction>(V)); return isa<Instruction>(V) && classof(cast<Instruction>(V));
} }
}; };
ExtractValueInst::ExtractValueInst(Value *Agg, ExtractValueInst::ExtractValueInst(Value *Agg,
ArrayRef<unsigned> Idxs, ArrayRef<unsigned> Idxs,
skipping to change at line 1825 skipping to change at line 1825
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// InsertValueInst Class // InsertValueInst Class
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
/// InsertValueInst - This instruction inserts a struct field of array elem ent /// InsertValueInst - This instruction inserts a struct field of array elem ent
/// value into an aggregate value. /// value into an aggregate value.
/// ///
class InsertValueInst : public Instruction { class InsertValueInst : public Instruction {
SmallVector<unsigned, 4> Indices; SmallVector<unsigned, 4> Indices;
void *operator new(size_t, unsigned); // Do not implement void *operator new(size_t, unsigned) LLVM_DELETED_FUNCTION;
InsertValueInst(const InsertValueInst &IVI); InsertValueInst(const InsertValueInst &IVI);
void init(Value *Agg, Value *Val, ArrayRef<unsigned> Idxs, void init(Value *Agg, Value *Val, ArrayRef<unsigned> Idxs,
const Twine &NameStr); const Twine &NameStr);
/// Constructors - Create a insertvalue instruction with a base aggregate /// Constructors - Create a insertvalue instruction with a base aggregate
/// value, a value to insert, and a list of indices. The first ctor can /// value, a value to insert, and a list of indices. The first ctor can
/// optionally insert before an existing instruction, the second appends /// optionally insert before an existing instruction, the second appends
/// the new instruction to the specified BasicBlock. /// the new instruction to the specified BasicBlock.
inline InsertValueInst(Value *Agg, Value *Val, inline InsertValueInst(Value *Agg, Value *Val,
ArrayRef<unsigned> Idxs, ArrayRef<unsigned> Idxs,
skipping to change at line 1910 skipping to change at line 1910
unsigned getNumIndices() const { unsigned getNumIndices() const {
return (unsigned)Indices.size(); return (unsigned)Indices.size();
} }
bool hasIndices() const { bool hasIndices() const {
return true; return true;
} }
// Methods for support type inquiry through isa, cast, and dyn_cast: // Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const InsertValueInst *) { return true; }
static inline bool classof(const Instruction *I) { static inline bool classof(const Instruction *I) {
return I->getOpcode() == Instruction::InsertValue; return I->getOpcode() == Instruction::InsertValue;
} }
static inline bool classof(const Value *V) { static inline bool classof(const Value *V) {
return isa<Instruction>(V) && classof(cast<Instruction>(V)); return isa<Instruction>(V) && classof(cast<Instruction>(V));
} }
}; };
template <> template <>
struct OperandTraits<InsertValueInst> : struct OperandTraits<InsertValueInst> :
skipping to change at line 1956 skipping to change at line 1955
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// PHINode Class // PHINode Class
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// PHINode - The PHINode class is used to represent the magical mystical PH I // PHINode - The PHINode class is used to represent the magical mystical PH I
// node, that can not exist in nature, but can be synthesized in a computer // node, that can not exist in nature, but can be synthesized in a computer
// scientist's overactive imagination. // scientist's overactive imagination.
// //
class PHINode : public Instruction { class PHINode : public Instruction {
void *operator new(size_t, unsigned); // DO NOT IMPLEMENT void *operator new(size_t, unsigned) LLVM_DELETED_FUNCTION;
/// ReservedSpace - The number of operands actually allocated. NumOperan ds is /// ReservedSpace - The number of operands actually allocated. NumOperan ds is
/// the number actually in use. /// the number actually in use.
unsigned ReservedSpace; unsigned ReservedSpace;
PHINode(const PHINode &PN); PHINode(const PHINode &PN);
// allocate space for exactly zero operands // allocate space for exactly zero operands
void *operator new(size_t s) { void *operator new(size_t s) {
return User::operator new(s, 0); return User::operator new(s, 0);
} }
explicit PHINode(Type *Ty, unsigned NumReservedValues, explicit PHINode(Type *Ty, unsigned NumReservedValues,
const Twine &NameStr = "", Instruction *InsertBefore = 0 ) const Twine &NameStr = "", Instruction *InsertBefore = 0 )
skipping to change at line 2127 skipping to change at line 2126
int Idx = getBasicBlockIndex(BB); int Idx = getBasicBlockIndex(BB);
assert(Idx >= 0 && "Invalid basic block argument!"); assert(Idx >= 0 && "Invalid basic block argument!");
return getIncomingValue(Idx); return getIncomingValue(Idx);
} }
/// hasConstantValue - If the specified PHI node always merges together t he /// hasConstantValue - If the specified PHI node always merges together t he
/// same value, return the value, otherwise return null. /// same value, return the value, otherwise return null.
Value *hasConstantValue() const; Value *hasConstantValue() const;
/// Methods for support type inquiry through isa, cast, and dyn_cast: /// Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const PHINode *) { return true; }
static inline bool classof(const Instruction *I) { static inline bool classof(const Instruction *I) {
return I->getOpcode() == Instruction::PHI; return I->getOpcode() == Instruction::PHI;
} }
static inline bool classof(const Value *V) { static inline bool classof(const Value *V) {
return isa<Instruction>(V) && classof(cast<Instruction>(V)); return isa<Instruction>(V) && classof(cast<Instruction>(V));
} }
private: private:
void growOperands(); void growOperands();
}; };
skipping to change at line 2164 skipping to change at line 2162
/// cleanup. /// cleanup.
/// ///
class LandingPadInst : public Instruction { class LandingPadInst : public Instruction {
/// ReservedSpace - The number of operands actually allocated. NumOperan ds is /// ReservedSpace - The number of operands actually allocated. NumOperan ds is
/// the number actually in use. /// the number actually in use.
unsigned ReservedSpace; unsigned ReservedSpace;
LandingPadInst(const LandingPadInst &LP); LandingPadInst(const LandingPadInst &LP);
public: public:
enum ClauseType { Catch, Filter }; enum ClauseType { Catch, Filter };
private: private:
void *operator new(size_t, unsigned); // DO NOT IMPLEMENT void *operator new(size_t, unsigned) LLVM_DELETED_FUNCTION;
// Allocate space for exactly zero operands. // Allocate space for exactly zero operands.
void *operator new(size_t s) { void *operator new(size_t s) {
return User::operator new(s, 0); return User::operator new(s, 0);
} }
void growOperands(unsigned Size); void growOperands(unsigned Size);
void init(Value *PersFn, unsigned NumReservedValues, const Twine &NameStr ); void init(Value *PersFn, unsigned NumReservedValues, const Twine &NameStr );
explicit LandingPadInst(Type *RetTy, Value *PersonalityFn, explicit LandingPadInst(Type *RetTy, Value *PersonalityFn,
unsigned NumReservedValues, const Twine &NameStr, unsigned NumReservedValues, const Twine &NameStr,
Instruction *InsertBefore); Instruction *InsertBefore);
skipping to change at line 2230 skipping to change at line 2228
} }
/// isFilter - Return 'true' if the clause and index Idx is a filter clau se. /// isFilter - Return 'true' if the clause and index Idx is a filter clau se.
bool isFilter(unsigned Idx) const { bool isFilter(unsigned Idx) const {
return isa<ArrayType>(OperandList[Idx + 1]->getType()); return isa<ArrayType>(OperandList[Idx + 1]->getType());
} }
/// getNumClauses - Get the number of clauses for this landing pad. /// getNumClauses - Get the number of clauses for this landing pad.
unsigned getNumClauses() const { return getNumOperands() - 1; } unsigned getNumClauses() const { return getNumOperands() - 1; }
/// reserveClauses - Grow the size of the operand list to accomodate the new /// reserveClauses - Grow the size of the operand list to accommodate the new
/// number of clauses. /// number of clauses.
void reserveClauses(unsigned Size) { growOperands(Size); } void reserveClauses(unsigned Size) { growOperands(Size); }
// Methods for support type inquiry through isa, cast, and dyn_cast: // Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const LandingPadInst *) { return true; }
static inline bool classof(const Instruction *I) { static inline bool classof(const Instruction *I) {
return I->getOpcode() == Instruction::LandingPad; return I->getOpcode() == Instruction::LandingPad;
} }
static inline bool classof(const Value *V) { static inline bool classof(const Value *V) {
return isa<Instruction>(V) && classof(cast<Instruction>(V)); return isa<Instruction>(V) && classof(cast<Instruction>(V));
} }
}; };
template <> template <>
struct OperandTraits<LandingPadInst> : public HungoffOperandTraits<2> { struct OperandTraits<LandingPadInst> : public HungoffOperandTraits<2> {
skipping to change at line 2304 skipping to change at line 2301
DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value); DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value);
/// Convenience accessor. Returns null if there is no return value. /// Convenience accessor. Returns null if there is no return value.
Value *getReturnValue() const { Value *getReturnValue() const {
return getNumOperands() != 0 ? getOperand(0) : 0; return getNumOperands() != 0 ? getOperand(0) : 0;
} }
unsigned getNumSuccessors() const { return 0; } unsigned getNumSuccessors() const { return 0; }
// Methods for support type inquiry through isa, cast, and dyn_cast: // Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const ReturnInst *) { return true; }
static inline bool classof(const Instruction *I) { static inline bool classof(const Instruction *I) {
return (I->getOpcode() == Instruction::Ret); return (I->getOpcode() == Instruction::Ret);
} }
static inline bool classof(const Value *V) { static inline bool classof(const Value *V) {
return isa<Instruction>(V) && classof(cast<Instruction>(V)); return isa<Instruction>(V) && classof(cast<Instruction>(V));
} }
private: private:
virtual BasicBlock *getSuccessorV(unsigned idx) const; virtual BasicBlock *getSuccessorV(unsigned idx) const;
virtual unsigned getNumSuccessorsV() const; virtual unsigned getNumSuccessorsV() const;
virtual void setSuccessorV(unsigned idx, BasicBlock *B); virtual void setSuccessorV(unsigned idx, BasicBlock *B);
skipping to change at line 2404 skipping to change at line 2400
} }
/// \brief Swap the successors of this branch instruction. /// \brief Swap the successors of this branch instruction.
/// ///
/// Swaps the successors of the branch instruction. This also swaps any /// Swaps the successors of the branch instruction. This also swaps any
/// branch weight metadata associated with the instruction so that it /// branch weight metadata associated with the instruction so that it
/// continues to map correctly to each operand. /// continues to map correctly to each operand.
void swapSuccessors(); void swapSuccessors();
// Methods for support type inquiry through isa, cast, and dyn_cast: // Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const BranchInst *) { return true; }
static inline bool classof(const Instruction *I) { static inline bool classof(const Instruction *I) {
return (I->getOpcode() == Instruction::Br); return (I->getOpcode() == Instruction::Br);
} }
static inline bool classof(const Value *V) { static inline bool classof(const Value *V) {
return isa<Instruction>(V) && classof(cast<Instruction>(V)); return isa<Instruction>(V) && classof(cast<Instruction>(V));
} }
private: private:
virtual BasicBlock *getSuccessorV(unsigned idx) const; virtual BasicBlock *getSuccessorV(unsigned idx) const;
virtual unsigned getNumSuccessorsV() const; virtual unsigned getNumSuccessorsV() const;
virtual void setSuccessorV(unsigned idx, BasicBlock *B); virtual void setSuccessorV(unsigned idx, BasicBlock *B);
skipping to change at line 2431 skipping to change at line 2426
DEFINE_TRANSPARENT_OPERAND_ACCESSORS(BranchInst, Value) DEFINE_TRANSPARENT_OPERAND_ACCESSORS(BranchInst, Value)
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// SwitchInst Class // SwitchInst Class
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
//===---------------------------------------------------------------------- ----- //===---------------------------------------------------------------------- -----
/// SwitchInst - Multiway switch /// SwitchInst - Multiway switch
/// ///
class SwitchInst : public TerminatorInst { class SwitchInst : public TerminatorInst {
void *operator new(size_t, unsigned); // DO NOT IMPLEMENT void *operator new(size_t, unsigned) LLVM_DELETED_FUNCTION;
unsigned ReservedSpace; unsigned ReservedSpace;
// Operands format:
// Operand[0] = Value to switch on // Operand[0] = Value to switch on
// Operand[1] = Default basic block destination // Operand[1] = Default basic block destination
// Operand[2n ] = Value to match // Operand[2n ] = Value to match
// Operand[2n+1] = BasicBlock to go to on match // Operand[2n+1] = BasicBlock to go to on match
// Store case values separately from operands list. We needn't User-Use
// concept here, since it is just a case value, it will always constant,
// and case value couldn't reused with another instructions/values.
// Additionally:
// It allows us to use custom type for case values that is not inherited
// from Value. Since case value is a complex type that implements
// the subset of integers, we needn't extract sub-constants within
// slow getAggregateElement method.
// For case values we will use std::list to by two reasons:
// 1. It allows to add/remove cases without whole collection reallocation
.
// 2. In most of cases we needn't random access.
// Currently case values are also stored in Operands List, but it will mo
ved
// out in future commits.
typedef std::list<IntegersSubset> Subsets;
typedef Subsets::iterator SubsetsIt;
typedef Subsets::const_iterator SubsetsConstIt;
Subsets TheSubsets;
SwitchInst(const SwitchInst &SI); SwitchInst(const SwitchInst &SI);
void init(Value *Value, BasicBlock *Default, unsigned NumReserved); void init(Value *Value, BasicBlock *Default, unsigned NumReserved);
void growOperands(); void growOperands();
// allocate space for exactly zero operands // allocate space for exactly zero operands
void *operator new(size_t s) { void *operator new(size_t s) {
return User::operator new(s, 0); return User::operator new(s, 0);
} }
/// SwitchInst ctor - Create a new switch instruction, specifying a value to /// SwitchInst ctor - Create a new switch instruction, specifying a value to
/// switch on and a default destination. The number of additional cases can /// switch on and a default destination. The number of additional cases can
/// be specified here to make memory allocation more efficient. This /// be specified here to make memory allocation more efficient. This
skipping to change at line 2461 skipping to change at line 2477
/// SwitchInst ctor - Create a new switch instruction, specifying a value to /// SwitchInst ctor - Create a new switch instruction, specifying a value to
/// switch on and a default destination. The number of additional cases can /// switch on and a default destination. The number of additional cases can
/// be specified here to make memory allocation more efficient. This /// be specified here to make memory allocation more efficient. This
/// constructor also autoinserts at the end of the specified BasicBlock. /// constructor also autoinserts at the end of the specified BasicBlock.
SwitchInst(Value *Value, BasicBlock *Default, unsigned NumCases, SwitchInst(Value *Value, BasicBlock *Default, unsigned NumCases,
BasicBlock *InsertAtEnd); BasicBlock *InsertAtEnd);
protected: protected:
virtual SwitchInst *clone_impl() const; virtual SwitchInst *clone_impl() const;
public: public:
// FIXME: Currently there are a lot of unclean template parameters,
// we need to make refactoring in future.
// All these parameters are used to implement both iterator and const_ite
rator
// without code duplication.
// SwitchInstTy may be "const SwitchInst" or "SwitchInst"
// ConstantIntTy may be "const ConstantInt" or "ConstantInt"
// SubsetsItTy may be SubsetsConstIt or SubsetsIt
// BasicBlockTy may be "const BasicBlock" or "BasicBlock"
template <class SwitchInstTy, class ConstantIntTy,
class SubsetsItTy, class BasicBlockTy>
class CaseIteratorT;
typedef CaseIteratorT<const SwitchInst, const ConstantInt,
SubsetsConstIt, const BasicBlock> ConstCaseIt;
class CaseIt;
// -2 // -2
static const unsigned DefaultPseudoIndex = static_cast<unsigned>(~0L-1); static const unsigned DefaultPseudoIndex = static_cast<unsigned>(~0L-1);
template <class SwitchInstTy, class ConstantIntTy, class BasicBlockTy>
class CaseIteratorT {
protected:
SwitchInstTy *SI;
unsigned Index;
public:
typedef CaseIteratorT<SwitchInstTy, ConstantIntTy, BasicBlockTy> Self;
/// Initializes case iterator for given SwitchInst and for given
/// case number.
CaseIteratorT(SwitchInstTy *SI, unsigned CaseNum) {
this->SI = SI;
Index = CaseNum;
}
/// Initializes case iterator for given SwitchInst and for given
/// TerminatorInst's successor index.
static Self fromSuccessorIndex(SwitchInstTy *SI, unsigned SuccessorInde
x) {
assert(SuccessorIndex < SI->getNumSuccessors() &&
"Successor index # out of range!");
return SuccessorIndex != 0 ?
Self(SI, SuccessorIndex - 1) :
Self(SI, DefaultPseudoIndex);
}
/// Resolves case value for current case.
ConstantIntTy *getCaseValue() {
assert(Index < SI->getNumCases() && "Index out the number of cases.")
;
return reinterpret_cast<ConstantIntTy*>(SI->getOperand(2 + Index*2));
}
/// Resolves successor for current case.
BasicBlockTy *getCaseSuccessor() {
assert((Index < SI->getNumCases() ||
Index == DefaultPseudoIndex) &&
"Index out the number of cases.");
return SI->getSuccessor(getSuccessorIndex());
}
/// Returns number of current case.
unsigned getCaseIndex() const { return Index; }
/// Returns TerminatorInst's successor index for current case successor
.
unsigned getSuccessorIndex() const {
assert((Index == DefaultPseudoIndex || Index < SI->getNumCases()) &&
"Index out the number of cases.");
return Index != DefaultPseudoIndex ? Index + 1 : 0;
}
Self operator++() {
// Check index correctness after increment.
// Note: Index == getNumCases() means end().
assert(Index+1 <= SI->getNumCases() && "Index out the number of cases
.");
++Index;
return *this;
}
Self operator++(int) {
Self tmp = *this;
++(*this);
return tmp;
}
Self operator--() {
// Check index correctness after decrement.
// Note: Index == getNumCases() means end().
// Also allow "-1" iterator here. That will became valid after ++.
assert((Index == 0 || Index-1 <= SI->getNumCases()) &&
"Index out the number of cases.");
--Index;
return *this;
}
Self operator--(int) {
Self tmp = *this;
--(*this);
return tmp;
}
bool operator==(const Self& RHS) const {
assert(RHS.SI == SI && "Incompatible operators.");
return RHS.Index == Index;
}
bool operator!=(const Self& RHS) const {
assert(RHS.SI == SI && "Incompatible operators.");
return RHS.Index != Index;
}
};
typedef CaseIteratorT<const SwitchInst, const ConstantInt, const BasicBlo
ck>
ConstCaseIt;
class CaseIt : public CaseIteratorT<SwitchInst, ConstantInt, BasicBlock>
{
typedef CaseIteratorT<SwitchInst, ConstantInt, BasicBlock> ParentTy;
public:
CaseIt(const ParentTy& Src) : ParentTy(Src) {}
CaseIt(SwitchInst *SI, unsigned CaseNum) : ParentTy(SI, CaseNum) {}
/// Sets the new value for current case.
void setValue(ConstantInt *V) {
assert(Index < SI->getNumCases() && "Index out the number of cases.")
;
SI->setOperand(2 + Index*2, reinterpret_cast<Value*>(V));
}
/// Sets the new successor for current case.
void setSuccessor(BasicBlock *S) {
SI->setSuccessor(getSuccessorIndex(), S);
}
};
static SwitchInst *Create(Value *Value, BasicBlock *Default, static SwitchInst *Create(Value *Value, BasicBlock *Default,
unsigned NumCases, Instruction *InsertBefore = 0) { unsigned NumCases, Instruction *InsertBefore = 0) {
return new SwitchInst(Value, Default, NumCases, InsertBefore); return new SwitchInst(Value, Default, NumCases, InsertBefore);
} }
static SwitchInst *Create(Value *Value, BasicBlock *Default, static SwitchInst *Create(Value *Value, BasicBlock *Default,
unsigned NumCases, BasicBlock *InsertAtEnd) { unsigned NumCases, BasicBlock *InsertAtEnd) {
return new SwitchInst(Value, Default, NumCases, InsertAtEnd); return new SwitchInst(Value, Default, NumCases, InsertAtEnd);
} }
~SwitchInst(); ~SwitchInst();
skipping to change at line 2611 skipping to change at line 2531
/// getNumCases - return the number of 'cases' in this switch instruction , /// getNumCases - return the number of 'cases' in this switch instruction ,
/// except the default case /// except the default case
unsigned getNumCases() const { unsigned getNumCases() const {
return getNumOperands()/2 - 1; return getNumOperands()/2 - 1;
} }
/// Returns a read/write iterator that points to the first /// Returns a read/write iterator that points to the first
/// case in SwitchInst. /// case in SwitchInst.
CaseIt case_begin() { CaseIt case_begin() {
return CaseIt(this, 0); return CaseIt(this, 0, TheSubsets.begin());
} }
/// Returns a read-only iterator that points to the first /// Returns a read-only iterator that points to the first
/// case in the SwitchInst. /// case in the SwitchInst.
ConstCaseIt case_begin() const { ConstCaseIt case_begin() const {
return ConstCaseIt(this, 0); return ConstCaseIt(this, 0, TheSubsets.begin());
} }
/// Returns a read/write iterator that points one past the last /// Returns a read/write iterator that points one past the last
/// in the SwitchInst. /// in the SwitchInst.
CaseIt case_end() { CaseIt case_end() {
return CaseIt(this, getNumCases()); return CaseIt(this, getNumCases(), TheSubsets.end());
} }
/// Returns a read-only iterator that points one past the last /// Returns a read-only iterator that points one past the last
/// in the SwitchInst. /// in the SwitchInst.
ConstCaseIt case_end() const { ConstCaseIt case_end() const {
return ConstCaseIt(this, getNumCases()); return ConstCaseIt(this, getNumCases(), TheSubsets.end());
} }
/// Returns an iterator that points to the default case. /// Returns an iterator that points to the default case.
/// Note: this iterator allows to resolve successor only. Attempt /// Note: this iterator allows to resolve successor only. Attempt
/// to resolve case value causes an assertion. /// to resolve case value causes an assertion.
/// Also note, that increment and decrement also causes an assertion and /// Also note, that increment and decrement also causes an assertion and
/// makes iterator invalid. /// makes iterator invalid.
CaseIt case_default() { CaseIt case_default() {
return CaseIt(this, DefaultPseudoIndex); return CaseIt(this, DefaultPseudoIndex, TheSubsets.end());
} }
ConstCaseIt case_default() const { ConstCaseIt case_default() const {
return ConstCaseIt(this, DefaultPseudoIndex); return ConstCaseIt(this, DefaultPseudoIndex, TheSubsets.end());
} }
/// findCaseValue - Search all of the case values for the specified const ant. /// findCaseValue - Search all of the case values for the specified const ant.
/// If it is explicitly handled, return the case iterator of it, otherwis e /// If it is explicitly handled, return the case iterator of it, otherwis e
/// return default case iterator to indicate /// return default case iterator to indicate
/// that it is handled by the default handler. /// that it is handled by the default handler.
CaseIt findCaseValue(const ConstantInt *C) { CaseIt findCaseValue(const ConstantInt *C) {
for (CaseIt i = case_begin(), e = case_end(); i != e; ++i) for (CaseIt i = case_begin(), e = case_end(); i != e; ++i)
if (i.getCaseValue() == C) if (i.getCaseValueEx().isSatisfies(IntItem::fromConstantInt(C)))
return i; return i;
return case_default(); return case_default();
} }
ConstCaseIt findCaseValue(const ConstantInt *C) const { ConstCaseIt findCaseValue(const ConstantInt *C) const {
for (ConstCaseIt i = case_begin(), e = case_end(); i != e; ++i) for (ConstCaseIt i = case_begin(), e = case_end(); i != e; ++i)
if (i.getCaseValue() == C) if (i.getCaseValueEx().isSatisfies(IntItem::fromConstantInt(C)))
return i; return i;
return case_default(); return case_default();
} }
/// findCaseDest - Finds the unique case value for a given successor. Ret urns /// findCaseDest - Finds the unique case value for a given successor. Ret urns
/// null if the successor is not found, not unique, or is the default cas e. /// null if the successor is not found, not unique, or is the default cas e.
ConstantInt *findCaseDest(BasicBlock *BB) { ConstantInt *findCaseDest(BasicBlock *BB) {
if (BB == getDefaultDest()) return NULL; if (BB == getDefaultDest()) return NULL;
ConstantInt *CI = NULL; ConstantInt *CI = NULL;
for (CaseIt i = case_begin(), e = case_end(); i != e; ++i) { for (CaseIt i = case_begin(), e = case_end(); i != e; ++i) {
if (i.getCaseSuccessor() == BB) { if (i.getCaseSuccessor() == BB) {
if (CI) return NULL; // Multiple cases lead to BB. if (CI) return NULL; // Multiple cases lead to BB.
else CI = i.getCaseValue(); else CI = i.getCaseValue();
} }
} }
return CI; return CI;
} }
/// addCase - Add an entry to the switch instruction... /// addCase - Add an entry to the switch instruction...
/// @deprecated
/// Note: /// Note:
/// This action invalidates case_end(). Old case_end() iterator will /// This action invalidates case_end(). Old case_end() iterator will
/// point to the added case. /// point to the added case.
void addCase(ConstantInt *OnVal, BasicBlock *Dest); void addCase(ConstantInt *OnVal, BasicBlock *Dest);
/// addCase - Add an entry to the switch instruction.
/// Note:
/// This action invalidates case_end(). Old case_end() iterator will
/// point to the added case.
void addCase(IntegersSubset& OnVal, BasicBlock *Dest);
/// removeCase - This method removes the specified case and its successor /// removeCase - This method removes the specified case and its successor
/// from the switch instruction. Note that this operation may reorder the /// from the switch instruction. Note that this operation may reorder the
/// remaining cases at index idx and above. /// remaining cases at index idx and above.
/// Note: /// Note:
/// This action invalidates iterators for all cases following the one rem oved, /// This action invalidates iterators for all cases following the one rem oved,
/// including the case_end() iterator. /// including the case_end() iterator.
void removeCase(CaseIt i); void removeCase(CaseIt& i);
unsigned getNumSuccessors() const { return getNumOperands()/2; } unsigned getNumSuccessors() const { return getNumOperands()/2; }
BasicBlock *getSuccessor(unsigned idx) const { BasicBlock *getSuccessor(unsigned idx) const {
assert(idx < getNumSuccessors() &&"Successor idx out of range for switc h!"); assert(idx < getNumSuccessors() &&"Successor idx out of range for switc h!");
return cast<BasicBlock>(getOperand(idx*2+1)); return cast<BasicBlock>(getOperand(idx*2+1));
} }
void setSuccessor(unsigned idx, BasicBlock *NewSucc) { void setSuccessor(unsigned idx, BasicBlock *NewSucc) {
assert(idx < getNumSuccessors() && "Successor # out of range for switch !"); assert(idx < getNumSuccessors() && "Successor # out of range for switch !");
setOperand(idx*2+1, (Value*)NewSucc); setOperand(idx*2+1, (Value*)NewSucc);
} }
uint16_t hash() const {
uint32_t NumberOfCases = (uint32_t)getNumCases();
uint16_t Hash = (0xFFFF & NumberOfCases) ^ (NumberOfCases >> 16);
for (ConstCaseIt i = case_begin(), e = case_end();
i != e; ++i) {
uint32_t NumItems = (uint32_t)i.getCaseValueEx().getNumItems();
Hash = (Hash << 1) ^ (0xFFFF & NumItems) ^ (NumItems >> 16);
}
return Hash;
}
// Case iterators definition.
template <class SwitchInstTy, class ConstantIntTy,
class SubsetsItTy, class BasicBlockTy>
class CaseIteratorT {
protected:
SwitchInstTy *SI;
unsigned long Index;
SubsetsItTy SubsetIt;
/// Initializes case iterator for given SwitchInst and for given
/// case number.
friend class SwitchInst;
CaseIteratorT(SwitchInstTy *SI, unsigned SuccessorIndex,
SubsetsItTy CaseValueIt) {
this->SI = SI;
Index = SuccessorIndex;
this->SubsetIt = CaseValueIt;
}
public:
typedef typename SubsetsItTy::reference IntegersSubsetRef;
typedef CaseIteratorT<SwitchInstTy, ConstantIntTy,
SubsetsItTy, BasicBlockTy> Self;
CaseIteratorT(SwitchInstTy *SI, unsigned CaseNum) {
this->SI = SI;
Index = CaseNum;
SubsetIt = SI->TheSubsets.begin();
std::advance(SubsetIt, CaseNum);
}
/// Initializes case iterator for given SwitchInst and for given
/// TerminatorInst's successor index.
static Self fromSuccessorIndex(SwitchInstTy *SI, unsigned SuccessorInde
x) {
assert(SuccessorIndex < SI->getNumSuccessors() &&
"Successor index # out of range!");
return SuccessorIndex != 0 ?
Self(SI, SuccessorIndex - 1) :
Self(SI, DefaultPseudoIndex);
}
/// Resolves case value for current case.
/// @deprecated
ConstantIntTy *getCaseValue() {
assert(Index < SI->getNumCases() && "Index out the number of cases.")
;
IntegersSubsetRef CaseRanges = *SubsetIt;
// FIXME: Currently we work with ConstantInt based cases.
// So return CaseValue as ConstantInt.
return CaseRanges.getSingleNumber(0).toConstantInt();
}
/// Resolves case value for current case.
IntegersSubsetRef getCaseValueEx() {
assert(Index < SI->getNumCases() && "Index out the number of cases.")
;
return *SubsetIt;
}
/// Resolves successor for current case.
BasicBlockTy *getCaseSuccessor() {
assert((Index < SI->getNumCases() ||
Index == DefaultPseudoIndex) &&
"Index out the number of cases.");
return SI->getSuccessor(getSuccessorIndex());
}
/// Returns number of current case.
unsigned getCaseIndex() const { return Index; }
/// Returns TerminatorInst's successor index for current case successor
.
unsigned getSuccessorIndex() const {
assert((Index == DefaultPseudoIndex || Index < SI->getNumCases()) &&
"Index out the number of cases.");
return Index != DefaultPseudoIndex ? Index + 1 : 0;
}
Self operator++() {
// Check index correctness after increment.
// Note: Index == getNumCases() means end().
assert(Index+1 <= SI->getNumCases() && "Index out the number of cases
.");
++Index;
if (Index == 0)
SubsetIt = SI->TheSubsets.begin();
else
++SubsetIt;
return *this;
}
Self operator++(int) {
Self tmp = *this;
++(*this);
return tmp;
}
Self operator--() {
// Check index correctness after decrement.
// Note: Index == getNumCases() means end().
// Also allow "-1" iterator here. That will became valid after ++.
unsigned NumCases = SI->getNumCases();
assert((Index == 0 || Index-1 <= NumCases) &&
"Index out the number of cases.");
--Index;
if (Index == NumCases) {
SubsetIt = SI->TheSubsets.end();
return *this;
}
if (Index != -1UL)
--SubsetIt;
return *this;
}
Self operator--(int) {
Self tmp = *this;
--(*this);
return tmp;
}
bool operator==(const Self& RHS) const {
assert(RHS.SI == SI && "Incompatible operators.");
return RHS.Index == Index;
}
bool operator!=(const Self& RHS) const {
assert(RHS.SI == SI && "Incompatible operators.");
return RHS.Index != Index;
}
};
class CaseIt : public CaseIteratorT<SwitchInst, ConstantInt,
SubsetsIt, BasicBlock> {
typedef CaseIteratorT<SwitchInst, ConstantInt, SubsetsIt, BasicBlock>
ParentTy;
protected:
friend class SwitchInst;
CaseIt(SwitchInst *SI, unsigned CaseNum, SubsetsIt SubsetIt) :
ParentTy(SI, CaseNum, SubsetIt) {}
void updateCaseValueOperand(IntegersSubset& V) {
SI->setOperand(2 + Index*2, reinterpret_cast<Value*>((Constant*)V));
}
public:
CaseIt(SwitchInst *SI, unsigned CaseNum) : ParentTy(SI, CaseNum) {}
CaseIt(const ParentTy& Src) : ParentTy(Src) {}
/// Sets the new value for current case.
/// @deprecated.
void setValue(ConstantInt *V) {
assert(Index < SI->getNumCases() && "Index out the number of cases.")
;
IntegersSubsetToBB Mapping;
// FIXME: Currently we work with ConstantInt based cases.
// So inititalize IntItem container directly from ConstantInt.
Mapping.add(IntItem::fromConstantInt(V));
*SubsetIt = Mapping.getCase();
updateCaseValueOperand(*SubsetIt);
}
/// Sets the new value for current case.
void setValueEx(IntegersSubset& V) {
assert(Index < SI->getNumCases() && "Index out the number of cases.")
;
*SubsetIt = V;
updateCaseValueOperand(*SubsetIt);
}
/// Sets the new successor for current case.
void setSuccessor(BasicBlock *S) {
SI->setSuccessor(getSuccessorIndex(), S);
}
};
// Methods for support type inquiry through isa, cast, and dyn_cast: // Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const SwitchInst *) { return true; }
static inline bool classof(const Instruction *I) { static inline bool classof(const Instruction *I) {
return I->getOpcode() == Instruction::Switch; return I->getOpcode() == Instruction::Switch;
} }
static inline bool classof(const Value *V) { static inline bool classof(const Value *V) {
return isa<Instruction>(V) && classof(cast<Instruction>(V)); return isa<Instruction>(V) && classof(cast<Instruction>(V));
} }
private: private:
virtual BasicBlock *getSuccessorV(unsigned idx) const; virtual BasicBlock *getSuccessorV(unsigned idx) const;
virtual unsigned getNumSuccessorsV() const; virtual unsigned getNumSuccessorsV() const;
virtual void setSuccessorV(unsigned idx, BasicBlock *B); virtual void setSuccessorV(unsigned idx, BasicBlock *B);
skipping to change at line 2725 skipping to change at line 2835
DEFINE_TRANSPARENT_OPERAND_ACCESSORS(SwitchInst, Value) DEFINE_TRANSPARENT_OPERAND_ACCESSORS(SwitchInst, Value)
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// IndirectBrInst Class // IndirectBrInst Class
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
//===---------------------------------------------------------------------- ----- //===---------------------------------------------------------------------- -----
/// IndirectBrInst - Indirect Branch Instruction. /// IndirectBrInst - Indirect Branch Instruction.
/// ///
class IndirectBrInst : public TerminatorInst { class IndirectBrInst : public TerminatorInst {
void *operator new(size_t, unsigned); // DO NOT IMPLEMENT void *operator new(size_t, unsigned) LLVM_DELETED_FUNCTION;
unsigned ReservedSpace; unsigned ReservedSpace;
// Operand[0] = Value to switch on // Operand[0] = Value to switch on
// Operand[1] = Default basic block destination // Operand[1] = Default basic block destination
// Operand[2n ] = Value to match // Operand[2n ] = Value to match
// Operand[2n+1] = BasicBlock to go to on match // Operand[2n+1] = BasicBlock to go to on match
IndirectBrInst(const IndirectBrInst &IBI); IndirectBrInst(const IndirectBrInst &IBI);
void init(Value *Address, unsigned NumDests); void init(Value *Address, unsigned NumDests);
void growOperands(); void growOperands();
// allocate space for exactly zero operands // allocate space for exactly zero operands
void *operator new(size_t s) { void *operator new(size_t s) {
skipping to change at line 2795 skipping to change at line 2905
unsigned getNumSuccessors() const { return getNumOperands()-1; } unsigned getNumSuccessors() const { return getNumOperands()-1; }
BasicBlock *getSuccessor(unsigned i) const { BasicBlock *getSuccessor(unsigned i) const {
return cast<BasicBlock>(getOperand(i+1)); return cast<BasicBlock>(getOperand(i+1));
} }
void setSuccessor(unsigned i, BasicBlock *NewSucc) { void setSuccessor(unsigned i, BasicBlock *NewSucc) {
setOperand(i+1, (Value*)NewSucc); setOperand(i+1, (Value*)NewSucc);
} }
// Methods for support type inquiry through isa, cast, and dyn_cast: // Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const IndirectBrInst *) { return true; }
static inline bool classof(const Instruction *I) { static inline bool classof(const Instruction *I) {
return I->getOpcode() == Instruction::IndirectBr; return I->getOpcode() == Instruction::IndirectBr;
} }
static inline bool classof(const Value *V) { static inline bool classof(const Value *V) {
return isa<Instruction>(V) && classof(cast<Instruction>(V)); return isa<Instruction>(V) && classof(cast<Instruction>(V));
} }
private: private:
virtual BasicBlock *getSuccessorV(unsigned idx) const; virtual BasicBlock *getSuccessorV(unsigned idx) const;
virtual unsigned getNumSuccessorsV() const; virtual unsigned getNumSuccessorsV() const;
virtual void setSuccessorV(unsigned idx, BasicBlock *B); virtual void setSuccessorV(unsigned idx, BasicBlock *B);
skipping to change at line 2829 skipping to change at line 2938
/// calling convention of the call. /// calling convention of the call.
/// ///
class InvokeInst : public TerminatorInst { class InvokeInst : public TerminatorInst {
AttrListPtr AttributeList; AttrListPtr AttributeList;
InvokeInst(const InvokeInst &BI); InvokeInst(const InvokeInst &BI);
void init(Value *Func, BasicBlock *IfNormal, BasicBlock *IfException, void init(Value *Func, BasicBlock *IfNormal, BasicBlock *IfException,
ArrayRef<Value *> Args, const Twine &NameStr); ArrayRef<Value *> Args, const Twine &NameStr);
/// Construct an InvokeInst given a range of arguments. /// Construct an InvokeInst given a range of arguments.
/// ///
/// @brief Construct an InvokeInst from a range of arguments /// \brief Construct an InvokeInst from a range of arguments
inline InvokeInst(Value *Func, BasicBlock *IfNormal, BasicBlock *IfExcept ion, inline InvokeInst(Value *Func, BasicBlock *IfNormal, BasicBlock *IfExcept ion,
ArrayRef<Value *> Args, unsigned Values, ArrayRef<Value *> Args, unsigned Values,
const Twine &NameStr, Instruction *InsertBefore); const Twine &NameStr, Instruction *InsertBefore);
/// Construct an InvokeInst given a range of arguments. /// Construct an InvokeInst given a range of arguments.
/// ///
/// @brief Construct an InvokeInst from a range of arguments /// \brief Construct an InvokeInst from a range of arguments
inline InvokeInst(Value *Func, BasicBlock *IfNormal, BasicBlock *IfExcept ion, inline InvokeInst(Value *Func, BasicBlock *IfNormal, BasicBlock *IfExcept ion,
ArrayRef<Value *> Args, unsigned Values, ArrayRef<Value *> Args, unsigned Values,
const Twine &NameStr, BasicBlock *InsertAtEnd); const Twine &NameStr, BasicBlock *InsertAtEnd);
protected: protected:
virtual InvokeInst *clone_impl() const; virtual InvokeInst *clone_impl() const;
public: public:
static InvokeInst *Create(Value *Func, static InvokeInst *Create(Value *Func,
BasicBlock *IfNormal, BasicBlock *IfException, BasicBlock *IfNormal, BasicBlock *IfException,
ArrayRef<Value *> Args, const Twine &NameStr = "", ArrayRef<Value *> Args, const Twine &NameStr = "",
Instruction *InsertBefore = 0) { Instruction *InsertBefore = 0) {
skipping to change at line 2895 skipping to change at line 3004
/// setAttributes - Set the parameter attributes for this invoke. /// setAttributes - Set the parameter attributes for this invoke.
/// ///
void setAttributes(const AttrListPtr &Attrs) { AttributeList = Attrs; } void setAttributes(const AttrListPtr &Attrs) { AttributeList = Attrs; }
/// addAttribute - adds the attribute to the list of attributes. /// addAttribute - adds the attribute to the list of attributes.
void addAttribute(unsigned i, Attributes attr); void addAttribute(unsigned i, Attributes attr);
/// removeAttribute - removes the attribute from the list of attributes. /// removeAttribute - removes the attribute from the list of attributes.
void removeAttribute(unsigned i, Attributes attr); void removeAttribute(unsigned i, Attributes attr);
/// @brief Determine whether the call or the callee has the given attribu /// \brief Determine whether this call has the NoAlias attribute.
te. bool hasFnAttr(Attributes::AttrVal A) const;
bool paramHasAttr(unsigned i, Attributes attr) const;
/// \brief Determine whether the call or the callee has the given attribu
tes.
bool paramHasAttr(unsigned i, Attributes::AttrVal A) const;
/// @brief Extract the alignment for a call or parameter (0=unknown). /// \brief Extract the alignment for a call or parameter (0=unknown).
unsigned getParamAlignment(unsigned i) const { unsigned getParamAlignment(unsigned i) const {
return AttributeList.getParamAlignment(i); return AttributeList.getParamAlignment(i);
} }
/// @brief Return true if the call should not be inlined. /// \brief Return true if the call should not be inlined.
bool isNoInline() const { return paramHasAttr(~0, Attribute::NoInline); } bool isNoInline() const { return hasFnAttr(Attributes::NoInline); }
void setIsNoInline(bool Value = true) { void setIsNoInline() {
if (Value) addAttribute(~0, Attribute::NoInline); addAttribute(AttrListPtr::FunctionIndex,
else removeAttribute(~0, Attribute::NoInline); Attributes::get(getContext(), Attributes::NoInline));
} }
/// @brief Determine if the call does not access memory. /// \brief Determine if the call does not access memory.
bool doesNotAccessMemory() const { bool doesNotAccessMemory() const {
return paramHasAttr(~0, Attribute::ReadNone); return hasFnAttr(Attributes::ReadNone);
} }
void setDoesNotAccessMemory(bool NotAccessMemory = true) { void setDoesNotAccessMemory() {
if (NotAccessMemory) addAttribute(~0, Attribute::ReadNone); addAttribute(AttrListPtr::FunctionIndex,
else removeAttribute(~0, Attribute::ReadNone); Attributes::get(getContext(), Attributes::ReadNone));
} }
/// @brief Determine if the call does not access or only reads memory. /// \brief Determine if the call does not access or only reads memory.
bool onlyReadsMemory() const { bool onlyReadsMemory() const {
return doesNotAccessMemory() || paramHasAttr(~0, Attribute::ReadOnly); return doesNotAccessMemory() || hasFnAttr(Attributes::ReadOnly);
} }
void setOnlyReadsMemory(bool OnlyReadsMemory = true) { void setOnlyReadsMemory() {
if (OnlyReadsMemory) addAttribute(~0, Attribute::ReadOnly); addAttribute(AttrListPtr::FunctionIndex,
else removeAttribute(~0, Attribute::ReadOnly | Attribute::ReadNone); Attributes::get(getContext(), Attributes::ReadOnly));
} }
/// @brief Determine if the call cannot return. /// \brief Determine if the call cannot return.
bool doesNotReturn() const { return paramHasAttr(~0, Attribute::NoReturn) bool doesNotReturn() const { return hasFnAttr(Attributes::NoReturn); }
; } void setDoesNotReturn() {
void setDoesNotReturn(bool DoesNotReturn = true) { addAttribute(AttrListPtr::FunctionIndex,
if (DoesNotReturn) addAttribute(~0, Attribute::NoReturn); Attributes::get(getContext(), Attributes::NoReturn));
else removeAttribute(~0, Attribute::NoReturn);
} }
/// @brief Determine if the call cannot unwind. /// \brief Determine if the call cannot unwind.
bool doesNotThrow() const { return paramHasAttr(~0, Attribute::NoUnwind); bool doesNotThrow() const { return hasFnAttr(Attributes::NoUnwind); }
} void setDoesNotThrow() {
void setDoesNotThrow(bool DoesNotThrow = true) { addAttribute(AttrListPtr::FunctionIndex,
if (DoesNotThrow) addAttribute(~0, Attribute::NoUnwind); Attributes::get(getContext(), Attributes::NoUnwind));
else removeAttribute(~0, Attribute::NoUnwind);
} }
/// @brief Determine if the call returns a structure through first /// \brief Determine if the call returns a structure through first
/// pointer argument. /// pointer argument.
bool hasStructRetAttr() const { bool hasStructRetAttr() const {
// Be friendly and also check the callee. // Be friendly and also check the callee.
return paramHasAttr(1, Attribute::StructRet); return paramHasAttr(1, Attributes::StructRet);
} }
/// @brief Determine if any call argument is an aggregate passed by value . /// \brief Determine if any call argument is an aggregate passed by value .
bool hasByValArgument() const { bool hasByValArgument() const {
return AttributeList.hasAttrSomewhere(Attribute::ByVal); for (unsigned I = 0, E = AttributeList.getNumAttrs(); I != E; ++I)
if (AttributeList.getAttributesAtIndex(I).hasAttribute(Attributes::By
Val))
return true;
return false;
} }
/// getCalledFunction - Return the function called, or null if this is an /// getCalledFunction - Return the function called, or null if this is an
/// indirect function invocation. /// indirect function invocation.
/// ///
Function *getCalledFunction() const { Function *getCalledFunction() const {
return dyn_cast<Function>(Op<-3>()); return dyn_cast<Function>(Op<-3>());
} }
/// getCalledValue - Get a pointer to the function that is invoked by thi s /// getCalledValue - Get a pointer to the function that is invoked by thi s
skipping to change at line 3002 skipping to change at line 3117
} }
void setSuccessor(unsigned idx, BasicBlock *NewSucc) { void setSuccessor(unsigned idx, BasicBlock *NewSucc) {
assert(idx < 2 && "Successor # out of range for invoke!"); assert(idx < 2 && "Successor # out of range for invoke!");
*(&Op<-2>() + idx) = reinterpret_cast<Value*>(NewSucc); *(&Op<-2>() + idx) = reinterpret_cast<Value*>(NewSucc);
} }
unsigned getNumSuccessors() const { return 2; } unsigned getNumSuccessors() const { return 2; }
// Methods for support type inquiry through isa, cast, and dyn_cast: // Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const InvokeInst *) { return true; }
static inline bool classof(const Instruction *I) { static inline bool classof(const Instruction *I) {
return (I->getOpcode() == Instruction::Invoke); return (I->getOpcode() == Instruction::Invoke);
} }
static inline bool classof(const Value *V) { static inline bool classof(const Value *V) {
return isa<Instruction>(V) && classof(cast<Instruction>(V)); return isa<Instruction>(V) && classof(cast<Instruction>(V));
} }
private: private:
virtual BasicBlock *getSuccessorV(unsigned idx) const; virtual BasicBlock *getSuccessorV(unsigned idx) const;
virtual unsigned getNumSuccessorsV() const; virtual unsigned getNumSuccessorsV() const;
skipping to change at line 3082 skipping to change at line 3196
/// Provide fast operand accessors /// Provide fast operand accessors
DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value); DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value);
/// Convenience accessor. /// Convenience accessor.
Value *getValue() const { return Op<0>(); } Value *getValue() const { return Op<0>(); }
unsigned getNumSuccessors() const { return 0; } unsigned getNumSuccessors() const { return 0; }
// Methods for support type inquiry through isa, cast, and dyn_cast: // Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const ResumeInst *) { return true; }
static inline bool classof(const Instruction *I) { static inline bool classof(const Instruction *I) {
return I->getOpcode() == Instruction::Resume; return I->getOpcode() == Instruction::Resume;
} }
static inline bool classof(const Value *V) { static inline bool classof(const Value *V) {
return isa<Instruction>(V) && classof(cast<Instruction>(V)); return isa<Instruction>(V) && classof(cast<Instruction>(V));
} }
private: private:
virtual BasicBlock *getSuccessorV(unsigned idx) const; virtual BasicBlock *getSuccessorV(unsigned idx) const;
virtual unsigned getNumSuccessorsV() const; virtual unsigned getNumSuccessorsV() const;
virtual void setSuccessorV(unsigned idx, BasicBlock *B); virtual void setSuccessorV(unsigned idx, BasicBlock *B);
skipping to change at line 3112 skipping to change at line 3225
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// UnreachableInst Class // UnreachableInst Class
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
//===---------------------------------------------------------------------- ----- //===---------------------------------------------------------------------- -----
/// UnreachableInst - This function has undefined behavior. In particular, the /// UnreachableInst - This function has undefined behavior. In particular, the
/// presence of this instruction indicates some higher level knowledge that the /// presence of this instruction indicates some higher level knowledge that the
/// end of the block cannot be reached. /// end of the block cannot be reached.
/// ///
class UnreachableInst : public TerminatorInst { class UnreachableInst : public TerminatorInst {
void *operator new(size_t, unsigned); // DO NOT IMPLEMENT void *operator new(size_t, unsigned) LLVM_DELETED_FUNCTION;
protected: protected:
virtual UnreachableInst *clone_impl() const; virtual UnreachableInst *clone_impl() const;
public: public:
// allocate space for exactly zero operands // allocate space for exactly zero operands
void *operator new(size_t s) { void *operator new(size_t s) {
return User::operator new(s, 0); return User::operator new(s, 0);
} }
explicit UnreachableInst(LLVMContext &C, Instruction *InsertBefore = 0); explicit UnreachableInst(LLVMContext &C, Instruction *InsertBefore = 0);
explicit UnreachableInst(LLVMContext &C, BasicBlock *InsertAtEnd); explicit UnreachableInst(LLVMContext &C, BasicBlock *InsertAtEnd);
unsigned getNumSuccessors() const { return 0; } unsigned getNumSuccessors() const { return 0; }
// Methods for support type inquiry through isa, cast, and dyn_cast: // Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const UnreachableInst *) { return true; }
static inline bool classof(const Instruction *I) { static inline bool classof(const Instruction *I) {
return I->getOpcode() == Instruction::Unreachable; return I->getOpcode() == Instruction::Unreachable;
} }
static inline bool classof(const Value *V) { static inline bool classof(const Value *V) {
return isa<Instruction>(V) && classof(cast<Instruction>(V)); return isa<Instruction>(V) && classof(cast<Instruction>(V));
} }
private: private:
virtual BasicBlock *getSuccessorV(unsigned idx) const; virtual BasicBlock *getSuccessorV(unsigned idx) const;
virtual unsigned getNumSuccessorsV() const; virtual unsigned getNumSuccessorsV() const;
virtual void setSuccessorV(unsigned idx, BasicBlock *B); virtual void setSuccessorV(unsigned idx, BasicBlock *B);
}; };
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// TruncInst Class // TruncInst Class
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
/// @brief This class represents a truncation of integer types. /// \brief This class represents a truncation of integer types.
class TruncInst : public CastInst { class TruncInst : public CastInst {
protected: protected:
/// @brief Clone an identical TruncInst /// \brief Clone an identical TruncInst
virtual TruncInst *clone_impl() const; virtual TruncInst *clone_impl() const;
public: public:
/// @brief Constructor with insert-before-instruction semantics /// \brief Constructor with insert-before-instruction semantics
TruncInst( TruncInst(
Value *S, ///< The value to be truncated Value *S, ///< The value to be truncated
Type *Ty, ///< The (smaller) type to truncate to Type *Ty, ///< The (smaller) type to truncate to
const Twine &NameStr = "", ///< A name for the new instruction const Twine &NameStr = "", ///< A name for the new instruction
Instruction *InsertBefore = 0 ///< Where to insert the new instruction Instruction *InsertBefore = 0 ///< Where to insert the new instruction
); );
/// @brief Constructor with insert-at-end-of-block semantics /// \brief Constructor with insert-at-end-of-block semantics
TruncInst( TruncInst(
Value *S, ///< The value to be truncated Value *S, ///< The value to be truncated
Type *Ty, ///< The (smaller) type to truncate to Type *Ty, ///< The (smaller) type to truncate to
const Twine &NameStr, ///< A name for the new instruction const Twine &NameStr, ///< A name for the new instruction
BasicBlock *InsertAtEnd ///< The block to insert the instruction into BasicBlock *InsertAtEnd ///< The block to insert the instruction into
); );
/// @brief Methods for support type inquiry through isa, cast, and dyn_ca /// \brief Methods for support type inquiry through isa, cast, and dyn_ca
st: st:
static inline bool classof(const TruncInst *) { return true; }
static inline bool classof(const Instruction *I) { static inline bool classof(const Instruction *I) {
return I->getOpcode() == Trunc; return I->getOpcode() == Trunc;
} }
static inline bool classof(const Value *V) { static inline bool classof(const Value *V) {
return isa<Instruction>(V) && classof(cast<Instruction>(V)); return isa<Instruction>(V) && classof(cast<Instruction>(V));
} }
}; };
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// ZExtInst Class // ZExtInst Class
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
/// @brief This class represents zero extension of integer types. /// \brief This class represents zero extension of integer types.
class ZExtInst : public CastInst { class ZExtInst : public CastInst {
protected: protected:
/// @brief Clone an identical ZExtInst /// \brief Clone an identical ZExtInst
virtual ZExtInst *clone_impl() const; virtual ZExtInst *clone_impl() const;
public: public:
/// @brief Constructor with insert-before-instruction semantics /// \brief Constructor with insert-before-instruction semantics
ZExtInst( ZExtInst(
Value *S, ///< The value to be zero extended Value *S, ///< The value to be zero extended
Type *Ty, ///< The type to zero extend to Type *Ty, ///< The type to zero extend to
const Twine &NameStr = "", ///< A name for the new instruction const Twine &NameStr = "", ///< A name for the new instruction
Instruction *InsertBefore = 0 ///< Where to insert the new instruction Instruction *InsertBefore = 0 ///< Where to insert the new instruction
); );
/// @brief Constructor with insert-at-end semantics. /// \brief Constructor with insert-at-end semantics.
ZExtInst( ZExtInst(
Value *S, ///< The value to be zero extended Value *S, ///< The value to be zero extended
Type *Ty, ///< The type to zero extend to Type *Ty, ///< The type to zero extend to
const Twine &NameStr, ///< A name for the new instruction const Twine &NameStr, ///< A name for the new instruction
BasicBlock *InsertAtEnd ///< The block to insert the instruction into BasicBlock *InsertAtEnd ///< The block to insert the instruction into
); );
/// @brief Methods for support type inquiry through isa, cast, and dyn_ca /// \brief Methods for support type inquiry through isa, cast, and dyn_ca
st: st:
static inline bool classof(const ZExtInst *) { return true; }
static inline bool classof(const Instruction *I) { static inline bool classof(const Instruction *I) {
return I->getOpcode() == ZExt; return I->getOpcode() == ZExt;
} }
static inline bool classof(const Value *V) { static inline bool classof(const Value *V) {
return isa<Instruction>(V) && classof(cast<Instruction>(V)); return isa<Instruction>(V) && classof(cast<Instruction>(V));
} }
}; };
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// SExtInst Class // SExtInst Class
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
/// @brief This class represents a sign extension of integer types. /// \brief This class represents a sign extension of integer types.
class SExtInst : public CastInst { class SExtInst : public CastInst {
protected: protected:
/// @brief Clone an identical SExtInst /// \brief Clone an identical SExtInst
virtual SExtInst *clone_impl() const; virtual SExtInst *clone_impl() const;
public: public:
/// @brief Constructor with insert-before-instruction semantics /// \brief Constructor with insert-before-instruction semantics
SExtInst( SExtInst(
Value *S, ///< The value to be sign extended Value *S, ///< The value to be sign extended
Type *Ty, ///< The type to sign extend to Type *Ty, ///< The type to sign extend to
const Twine &NameStr = "", ///< A name for the new instruction const Twine &NameStr = "", ///< A name for the new instruction
Instruction *InsertBefore = 0 ///< Where to insert the new instruction Instruction *InsertBefore = 0 ///< Where to insert the new instruction
); );
/// @brief Constructor with insert-at-end-of-block semantics /// \brief Constructor with insert-at-end-of-block semantics
SExtInst( SExtInst(
Value *S, ///< The value to be sign extended Value *S, ///< The value to be sign extended
Type *Ty, ///< The type to sign extend to Type *Ty, ///< The type to sign extend to
const Twine &NameStr, ///< A name for the new instruction const Twine &NameStr, ///< A name for the new instruction
BasicBlock *InsertAtEnd ///< The block to insert the instruction into BasicBlock *InsertAtEnd ///< The block to insert the instruction into
); );
/// @brief Methods for support type inquiry through isa, cast, and dyn_ca /// \brief Methods for support type inquiry through isa, cast, and dyn_ca
st: st:
static inline bool classof(const SExtInst *) { return true; }
static inline bool classof(const Instruction *I) { static inline bool classof(const Instruction *I) {
return I->getOpcode() == SExt; return I->getOpcode() == SExt;
} }
static inline bool classof(const Value *V) { static inline bool classof(const Value *V) {
return isa<Instruction>(V) && classof(cast<Instruction>(V)); return isa<Instruction>(V) && classof(cast<Instruction>(V));
} }
}; };
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// FPTruncInst Class // FPTruncInst Class
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
/// @brief This class represents a truncation of floating point types. /// \brief This class represents a truncation of floating point types.
class FPTruncInst : public CastInst { class FPTruncInst : public CastInst {
protected: protected:
/// @brief Clone an identical FPTruncInst /// \brief Clone an identical FPTruncInst
virtual FPTruncInst *clone_impl() const; virtual FPTruncInst *clone_impl() const;
public: public:
/// @brief Constructor with insert-before-instruction semantics /// \brief Constructor with insert-before-instruction semantics
FPTruncInst( FPTruncInst(
Value *S, ///< The value to be truncated Value *S, ///< The value to be truncated
Type *Ty, ///< The type to truncate to Type *Ty, ///< The type to truncate to
const Twine &NameStr = "", ///< A name for the new instruction const Twine &NameStr = "", ///< A name for the new instruction
Instruction *InsertBefore = 0 ///< Where to insert the new instruction Instruction *InsertBefore = 0 ///< Where to insert the new instruction
); );
/// @brief Constructor with insert-before-instruction semantics /// \brief Constructor with insert-before-instruction semantics
FPTruncInst( FPTruncInst(
Value *S, ///< The value to be truncated Value *S, ///< The value to be truncated
Type *Ty, ///< The type to truncate to Type *Ty, ///< The type to truncate to
const Twine &NameStr, ///< A name for the new instruction const Twine &NameStr, ///< A name for the new instruction
BasicBlock *InsertAtEnd ///< The block to insert the instruction into BasicBlock *InsertAtEnd ///< The block to insert the instruction into
); );
/// @brief Methods for support type inquiry through isa, cast, and dyn_ca /// \brief Methods for support type inquiry through isa, cast, and dyn_ca
st: st:
static inline bool classof(const FPTruncInst *) { return true; }
static inline bool classof(const Instruction *I) { static inline bool classof(const Instruction *I) {
return I->getOpcode() == FPTrunc; return I->getOpcode() == FPTrunc;
} }
static inline bool classof(const Value *V) { static inline bool classof(const Value *V) {
return isa<Instruction>(V) && classof(cast<Instruction>(V)); return isa<Instruction>(V) && classof(cast<Instruction>(V));
} }
}; };
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// FPExtInst Class // FPExtInst Class
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
/// @brief This class represents an extension of floating point types. /// \brief This class represents an extension of floating point types.
class FPExtInst : public CastInst { class FPExtInst : public CastInst {
protected: protected:
/// @brief Clone an identical FPExtInst /// \brief Clone an identical FPExtInst
virtual FPExtInst *clone_impl() const; virtual FPExtInst *clone_impl() const;
public: public:
/// @brief Constructor with insert-before-instruction semantics /// \brief Constructor with insert-before-instruction semantics
FPExtInst( FPExtInst(
Value *S, ///< The value to be extended Value *S, ///< The value to be extended
Type *Ty, ///< The type to extend to Type *Ty, ///< The type to extend to
const Twine &NameStr = "", ///< A name for the new instruction const Twine &NameStr = "", ///< A name for the new instruction
Instruction *InsertBefore = 0 ///< Where to insert the new instruction Instruction *InsertBefore = 0 ///< Where to insert the new instruction
); );
/// @brief Constructor with insert-at-end-of-block semantics /// \brief Constructor with insert-at-end-of-block semantics
FPExtInst( FPExtInst(
Value *S, ///< The value to be extended Value *S, ///< The value to be extended
Type *Ty, ///< The type to extend to Type *Ty, ///< The type to extend to
const Twine &NameStr, ///< A name for the new instruction const Twine &NameStr, ///< A name for the new instruction
BasicBlock *InsertAtEnd ///< The block to insert the instruction into BasicBlock *InsertAtEnd ///< The block to insert the instruction into
); );
/// @brief Methods for support type inquiry through isa, cast, and dyn_ca /// \brief Methods for support type inquiry through isa, cast, and dyn_ca
st: st:
static inline bool classof(const FPExtInst *) { return true; }
static inline bool classof(const Instruction *I) { static inline bool classof(const Instruction *I) {
return I->getOpcode() == FPExt; return I->getOpcode() == FPExt;
} }
static inline bool classof(const Value *V) { static inline bool classof(const Value *V) {
return isa<Instruction>(V) && classof(cast<Instruction>(V)); return isa<Instruction>(V) && classof(cast<Instruction>(V));
} }
}; };
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// UIToFPInst Class // UIToFPInst Class
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
/// @brief This class represents a cast unsigned integer to floating point. /// \brief This class represents a cast unsigned integer to floating point.
class UIToFPInst : public CastInst { class UIToFPInst : public CastInst {
protected: protected:
/// @brief Clone an identical UIToFPInst /// \brief Clone an identical UIToFPInst
virtual UIToFPInst *clone_impl() const; virtual UIToFPInst *clone_impl() const;
public: public:
/// @brief Constructor with insert-before-instruction semantics /// \brief Constructor with insert-before-instruction semantics
UIToFPInst( UIToFPInst(
Value *S, ///< The value to be converted Value *S, ///< The value to be converted
Type *Ty, ///< The type to convert to Type *Ty, ///< The type to convert to
const Twine &NameStr = "", ///< A name for the new instruction const Twine &NameStr = "", ///< A name for the new instruction
Instruction *InsertBefore = 0 ///< Where to insert the new instruction Instruction *InsertBefore = 0 ///< Where to insert the new instruction
); );
/// @brief Constructor with insert-at-end-of-block semantics /// \brief Constructor with insert-at-end-of-block semantics
UIToFPInst( UIToFPInst(
Value *S, ///< The value to be converted Value *S, ///< The value to be converted
Type *Ty, ///< The type to convert to Type *Ty, ///< The type to convert to
const Twine &NameStr, ///< A name for the new instruction const Twine &NameStr, ///< A name for the new instruction
BasicBlock *InsertAtEnd ///< The block to insert the instruction into BasicBlock *InsertAtEnd ///< The block to insert the instruction into
); );
/// @brief Methods for support type inquiry through isa, cast, and dyn_ca /// \brief Methods for support type inquiry through isa, cast, and dyn_ca
st: st:
static inline bool classof(const UIToFPInst *) { return true; }
static inline bool classof(const Instruction *I) { static inline bool classof(const Instruction *I) {
return I->getOpcode() == UIToFP; return I->getOpcode() == UIToFP;
} }
static inline bool classof(const Value *V) { static inline bool classof(const Value *V) {
return isa<Instruction>(V) && classof(cast<Instruction>(V)); return isa<Instruction>(V) && classof(cast<Instruction>(V));
} }
}; };
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// SIToFPInst Class // SIToFPInst Class
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
/// @brief This class represents a cast from signed integer to floating poi nt. /// \brief This class represents a cast from signed integer to floating poi nt.
class SIToFPInst : public CastInst { class SIToFPInst : public CastInst {
protected: protected:
/// @brief Clone an identical SIToFPInst /// \brief Clone an identical SIToFPInst
virtual SIToFPInst *clone_impl() const; virtual SIToFPInst *clone_impl() const;
public: public:
/// @brief Constructor with insert-before-instruction semantics /// \brief Constructor with insert-before-instruction semantics
SIToFPInst( SIToFPInst(
Value *S, ///< The value to be converted Value *S, ///< The value to be converted
Type *Ty, ///< The type to convert to Type *Ty, ///< The type to convert to
const Twine &NameStr = "", ///< A name for the new instruction const Twine &NameStr = "", ///< A name for the new instruction
Instruction *InsertBefore = 0 ///< Where to insert the new instruction Instruction *InsertBefore = 0 ///< Where to insert the new instruction
); );
/// @brief Constructor with insert-at-end-of-block semantics /// \brief Constructor with insert-at-end-of-block semantics
SIToFPInst( SIToFPInst(
Value *S, ///< The value to be converted Value *S, ///< The value to be converted
Type *Ty, ///< The type to convert to Type *Ty, ///< The type to convert to
const Twine &NameStr, ///< A name for the new instruction const Twine &NameStr, ///< A name for the new instruction
BasicBlock *InsertAtEnd ///< The block to insert the instruction into BasicBlock *InsertAtEnd ///< The block to insert the instruction into
); );
/// @brief Methods for support type inquiry through isa, cast, and dyn_ca /// \brief Methods for support type inquiry through isa, cast, and dyn_ca
st: st:
static inline bool classof(const SIToFPInst *) { return true; }
static inline bool classof(const Instruction *I) { static inline bool classof(const Instruction *I) {
return I->getOpcode() == SIToFP; return I->getOpcode() == SIToFP;
} }
static inline bool classof(const Value *V) { static inline bool classof(const Value *V) {
return isa<Instruction>(V) && classof(cast<Instruction>(V)); return isa<Instruction>(V) && classof(cast<Instruction>(V));
} }
}; };
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// FPToUIInst Class // FPToUIInst Class
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
/// @brief This class represents a cast from floating point to unsigned int eger /// \brief This class represents a cast from floating point to unsigned int eger
class FPToUIInst : public CastInst { class FPToUIInst : public CastInst {
protected: protected:
/// @brief Clone an identical FPToUIInst /// \brief Clone an identical FPToUIInst
virtual FPToUIInst *clone_impl() const; virtual FPToUIInst *clone_impl() const;
public: public:
/// @brief Constructor with insert-before-instruction semantics /// \brief Constructor with insert-before-instruction semantics
FPToUIInst( FPToUIInst(
Value *S, ///< The value to be converted Value *S, ///< The value to be converted
Type *Ty, ///< The type to convert to Type *Ty, ///< The type to convert to
const Twine &NameStr = "", ///< A name for the new instruction const Twine &NameStr = "", ///< A name for the new instruction
Instruction *InsertBefore = 0 ///< Where to insert the new instruction Instruction *InsertBefore = 0 ///< Where to insert the new instruction
); );
/// @brief Constructor with insert-at-end-of-block semantics /// \brief Constructor with insert-at-end-of-block semantics
FPToUIInst( FPToUIInst(
Value *S, ///< The value to be converted Value *S, ///< The value to be converted
Type *Ty, ///< The type to convert to Type *Ty, ///< The type to convert to
const Twine &NameStr, ///< A name for the new instruction const Twine &NameStr, ///< A name for the new instruction
BasicBlock *InsertAtEnd ///< Where to insert the new instruction BasicBlock *InsertAtEnd ///< Where to insert the new instruction
); );
/// @brief Methods for support type inquiry through isa, cast, and dyn_ca /// \brief Methods for support type inquiry through isa, cast, and dyn_ca
st: st:
static inline bool classof(const FPToUIInst *) { return true; }
static inline bool classof(const Instruction *I) { static inline bool classof(const Instruction *I) {
return I->getOpcode() == FPToUI; return I->getOpcode() == FPToUI;
} }
static inline bool classof(const Value *V) { static inline bool classof(const Value *V) {
return isa<Instruction>(V) && classof(cast<Instruction>(V)); return isa<Instruction>(V) && classof(cast<Instruction>(V));
} }
}; };
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// FPToSIInst Class // FPToSIInst Class
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
/// @brief This class represents a cast from floating point to signed integ er. /// \brief This class represents a cast from floating point to signed integ er.
class FPToSIInst : public CastInst { class FPToSIInst : public CastInst {
protected: protected:
/// @brief Clone an identical FPToSIInst /// \brief Clone an identical FPToSIInst
virtual FPToSIInst *clone_impl() const; virtual FPToSIInst *clone_impl() const;
public: public:
/// @brief Constructor with insert-before-instruction semantics /// \brief Constructor with insert-before-instruction semantics
FPToSIInst( FPToSIInst(
Value *S, ///< The value to be converted Value *S, ///< The value to be converted
Type *Ty, ///< The type to convert to Type *Ty, ///< The type to convert to
const Twine &NameStr = "", ///< A name for the new instruction const Twine &NameStr = "", ///< A name for the new instruction
Instruction *InsertBefore = 0 ///< Where to insert the new instruction Instruction *InsertBefore = 0 ///< Where to insert the new instruction
); );
/// @brief Constructor with insert-at-end-of-block semantics /// \brief Constructor with insert-at-end-of-block semantics
FPToSIInst( FPToSIInst(
Value *S, ///< The value to be converted Value *S, ///< The value to be converted
Type *Ty, ///< The type to convert to Type *Ty, ///< The type to convert to
const Twine &NameStr, ///< A name for the new instruction const Twine &NameStr, ///< A name for the new instruction
BasicBlock *InsertAtEnd ///< The block to insert the instruction into BasicBlock *InsertAtEnd ///< The block to insert the instruction into
); );
/// @brief Methods for support type inquiry through isa, cast, and dyn_ca /// \brief Methods for support type inquiry through isa, cast, and dyn_ca
st: st:
static inline bool classof(const FPToSIInst *) { return true; }
static inline bool classof(const Instruction *I) { static inline bool classof(const Instruction *I) {
return I->getOpcode() == FPToSI; return I->getOpcode() == FPToSI;
} }
static inline bool classof(const Value *V) { static inline bool classof(const Value *V) {
return isa<Instruction>(V) && classof(cast<Instruction>(V)); return isa<Instruction>(V) && classof(cast<Instruction>(V));
} }
}; };
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// IntToPtrInst Class // IntToPtrInst Class
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
/// @brief This class represents a cast from an integer to a pointer. /// \brief This class represents a cast from an integer to a pointer.
class IntToPtrInst : public CastInst { class IntToPtrInst : public CastInst {
public: public:
/// @brief Constructor with insert-before-instruction semantics /// \brief Constructor with insert-before-instruction semantics
IntToPtrInst( IntToPtrInst(
Value *S, ///< The value to be converted Value *S, ///< The value to be converted
Type *Ty, ///< The type to convert to Type *Ty, ///< The type to convert to
const Twine &NameStr = "", ///< A name for the new instruction const Twine &NameStr = "", ///< A name for the new instruction
Instruction *InsertBefore = 0 ///< Where to insert the new instruction Instruction *InsertBefore = 0 ///< Where to insert the new instruction
); );
/// @brief Constructor with insert-at-end-of-block semantics /// \brief Constructor with insert-at-end-of-block semantics
IntToPtrInst( IntToPtrInst(
Value *S, ///< The value to be converted Value *S, ///< The value to be converted
Type *Ty, ///< The type to convert to Type *Ty, ///< The type to convert to
const Twine &NameStr, ///< A name for the new instruction const Twine &NameStr, ///< A name for the new instruction
BasicBlock *InsertAtEnd ///< The block to insert the instruction into BasicBlock *InsertAtEnd ///< The block to insert the instruction into
); );
/// @brief Clone an identical IntToPtrInst /// \brief Clone an identical IntToPtrInst
virtual IntToPtrInst *clone_impl() const; virtual IntToPtrInst *clone_impl() const;
/// \brief Returns the address space of this instruction's pointer type.
unsigned getAddressSpace() const {
return getType()->getPointerAddressSpace();
}
// Methods for support type inquiry through isa, cast, and dyn_cast: // Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const IntToPtrInst *) { return true; }
static inline bool classof(const Instruction *I) { static inline bool classof(const Instruction *I) {
return I->getOpcode() == IntToPtr; return I->getOpcode() == IntToPtr;
} }
static inline bool classof(const Value *V) { static inline bool classof(const Value *V) {
return isa<Instruction>(V) && classof(cast<Instruction>(V)); return isa<Instruction>(V) && classof(cast<Instruction>(V));
} }
}; };
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// PtrToIntInst Class // PtrToIntInst Class
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
/// @brief This class represents a cast from a pointer to an integer /// \brief This class represents a cast from a pointer to an integer
class PtrToIntInst : public CastInst { class PtrToIntInst : public CastInst {
protected: protected:
/// @brief Clone an identical PtrToIntInst /// \brief Clone an identical PtrToIntInst
virtual PtrToIntInst *clone_impl() const; virtual PtrToIntInst *clone_impl() const;
public: public:
/// @brief Constructor with insert-before-instruction semantics /// \brief Constructor with insert-before-instruction semantics
PtrToIntInst( PtrToIntInst(
Value *S, ///< The value to be converted Value *S, ///< The value to be converted
Type *Ty, ///< The type to convert to Type *Ty, ///< The type to convert to
const Twine &NameStr = "", ///< A name for the new instruction const Twine &NameStr = "", ///< A name for the new instruction
Instruction *InsertBefore = 0 ///< Where to insert the new instruction Instruction *InsertBefore = 0 ///< Where to insert the new instruction
); );
/// @brief Constructor with insert-at-end-of-block semantics /// \brief Constructor with insert-at-end-of-block semantics
PtrToIntInst( PtrToIntInst(
Value *S, ///< The value to be converted Value *S, ///< The value to be converted
Type *Ty, ///< The type to convert to Type *Ty, ///< The type to convert to
const Twine &NameStr, ///< A name for the new instruction const Twine &NameStr, ///< A name for the new instruction
BasicBlock *InsertAtEnd ///< The block to insert the instruction into BasicBlock *InsertAtEnd ///< The block to insert the instruction into
); );
/// \brief Gets the pointer operand.
Value *getPointerOperand() { return getOperand(0); }
/// \brief Gets the pointer operand.
const Value *getPointerOperand() const { return getOperand(0); }
/// \brief Gets the operand index of the pointer operand.
static unsigned getPointerOperandIndex() { return 0U; }
/// \brief Returns the address space of the pointer operand.
unsigned getPointerAddressSpace() const {
return getPointerOperand()->getType()->getPointerAddressSpace();
}
// Methods for support type inquiry through isa, cast, and dyn_cast: // Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const PtrToIntInst *) { return true; }
static inline bool classof(const Instruction *I) { static inline bool classof(const Instruction *I) {
return I->getOpcode() == PtrToInt; return I->getOpcode() == PtrToInt;
} }
static inline bool classof(const Value *V) { static inline bool classof(const Value *V) {
return isa<Instruction>(V) && classof(cast<Instruction>(V)); return isa<Instruction>(V) && classof(cast<Instruction>(V));
} }
}; };
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// BitCastInst Class // BitCastInst Class
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
/// @brief This class represents a no-op cast from one type to another. /// \brief This class represents a no-op cast from one type to another.
class BitCastInst : public CastInst { class BitCastInst : public CastInst {
protected: protected:
/// @brief Clone an identical BitCastInst /// \brief Clone an identical BitCastInst
virtual BitCastInst *clone_impl() const; virtual BitCastInst *clone_impl() const;
public: public:
/// @brief Constructor with insert-before-instruction semantics /// \brief Constructor with insert-before-instruction semantics
BitCastInst( BitCastInst(
Value *S, ///< The value to be casted Value *S, ///< The value to be casted
Type *Ty, ///< The type to casted to Type *Ty, ///< The type to casted to
const Twine &NameStr = "", ///< A name for the new instruction const Twine &NameStr = "", ///< A name for the new instruction
Instruction *InsertBefore = 0 ///< Where to insert the new instruction Instruction *InsertBefore = 0 ///< Where to insert the new instruction
); );
/// @brief Constructor with insert-at-end-of-block semantics /// \brief Constructor with insert-at-end-of-block semantics
BitCastInst( BitCastInst(
Value *S, ///< The value to be casted Value *S, ///< The value to be casted
Type *Ty, ///< The type to casted to Type *Ty, ///< The type to casted to
const Twine &NameStr, ///< A name for the new instruction const Twine &NameStr, ///< A name for the new instruction
BasicBlock *InsertAtEnd ///< The block to insert the instruction into BasicBlock *InsertAtEnd ///< The block to insert the instruction into
); );
// Methods for support type inquiry through isa, cast, and dyn_cast: // Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const BitCastInst *) { return true; }
static inline bool classof(const Instruction *I) { static inline bool classof(const Instruction *I) {
return I->getOpcode() == BitCast; return I->getOpcode() == BitCast;
} }
static inline bool classof(const Value *V) { static inline bool classof(const Value *V) {
return isa<Instruction>(V) && classof(cast<Instruction>(V)); return isa<Instruction>(V) && classof(cast<Instruction>(V));
} }
}; };
} // End llvm namespace } // End llvm namespace
 End of changes. 188 change blocks. 
359 lines changed or deleted 478 lines changed or added


 Instrumentation.h   Instrumentation.h 
skipping to change at line 37 skipping to change at line 37
// Insert path profiling instrumentation // Insert path profiling instrumentation
ModulePass *createPathProfilerPass(); ModulePass *createPathProfilerPass();
// Insert GCOV profiling instrumentation // Insert GCOV profiling instrumentation
ModulePass *createGCOVProfilerPass(bool EmitNotes = true, bool EmitData = t rue, ModulePass *createGCOVProfilerPass(bool EmitNotes = true, bool EmitData = t rue,
bool Use402Format = false, bool Use402Format = false,
bool UseExtraChecksum = false); bool UseExtraChecksum = false);
// Insert AddressSanitizer (address sanity checking) instrumentation // Insert AddressSanitizer (address sanity checking) instrumentation
ModulePass *createAddressSanitizerPass(); FunctionPass *createAddressSanitizerPass();
// Insert ThreadSanitizer (race detection) instrumentation // Insert ThreadSanitizer (race detection) instrumentation
FunctionPass *createThreadSanitizerPass(); FunctionPass *createThreadSanitizerPass();
// BoundsChecking - This pass instruments the code to perform run-time boun
ds
// checking on loads, stores, and other memory intrinsics.
// Penalty is the maximum run-time that is acceptable for the user.
//
FunctionPass *createBoundsCheckingPass(unsigned Penalty = 5);
} // End llvm namespace } // End llvm namespace
#endif #endif
 End of changes. 2 change blocks. 
1 lines changed or deleted 8 lines changed or added


 Interpreter.h   Interpreter.h 
skipping to change at line 26 skipping to change at line 26
#define EXECUTION_ENGINE_INTERPRETER_H #define EXECUTION_ENGINE_INTERPRETER_H
#include "llvm/ExecutionEngine/ExecutionEngine.h" #include "llvm/ExecutionEngine/ExecutionEngine.h"
#include <cstdlib> #include <cstdlib>
extern "C" void LLVMLinkInInterpreter(); extern "C" void LLVMLinkInInterpreter();
namespace { namespace {
struct ForceInterpreterLinking { struct ForceInterpreterLinking {
ForceInterpreterLinking() { ForceInterpreterLinking() {
// We must reference the passes in such a way that compilers will not // We must reference the interpreter in such a way that compilers wil l not
// delete it all as dead code, even with whole program optimization, // delete it all as dead code, even with whole program optimization,
// yet is effectively a NO-OP. As the compiler isn't smart enough // yet is effectively a NO-OP. As the compiler isn't smart enough
// to know that getenv() never returns -1, this will do the job. // to know that getenv() never returns -1, this will do the job.
if (std::getenv("bar") != (char*) -1) if (std::getenv("bar") != (char*) -1)
return; return;
LLVMLinkInInterpreter(); LLVMLinkInInterpreter();
} }
} ForceInterpreterLinking; } ForceInterpreterLinking;
} }
 End of changes. 1 change blocks. 
1 lines changed or deleted 1 lines changed or added


 IntervalPartition.h   IntervalPartition.h 
skipping to change at line 36 skipping to change at line 36
#include "llvm/Analysis/Interval.h" #include "llvm/Analysis/Interval.h"
#include "llvm/Pass.h" #include "llvm/Pass.h"
#include <map> #include <map>
namespace llvm { namespace llvm {
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// //
// IntervalPartition - This class builds and holds an "interval partition" for // IntervalPartition - This class builds and holds an "interval partition" for
// a function. This partition divides the control flow graph into a set of // a function. This partition divides the control flow graph into a set of
// maximal intervals, as defined with the properties above. Intuitively, a // maximal intervals, as defined with the properties above. Intuitively, a
// BasicBlock is a (possibly nonexistent) loop with a "tail" of non looping n
// interval is a (possibly nonexistent) loop with a "tail" of non looping
// nodes following it. // nodes following it.
// //
class IntervalPartition : public FunctionPass { class IntervalPartition : public FunctionPass {
typedef std::map<BasicBlock*, Interval*> IntervalMapTy; typedef std::map<BasicBlock*, Interval*> IntervalMapTy;
IntervalMapTy IntervalMap; IntervalMapTy IntervalMap;
typedef std::vector<Interval*> IntervalListTy; typedef std::vector<Interval*> IntervalListTy;
Interval *RootInterval; Interval *RootInterval;
std::vector<Interval*> Intervals; std::vector<Interval*> Intervals;
 End of changes. 1 change blocks. 
2 lines changed or deleted 3 lines changed or added


 IntrinsicInst.h   IntrinsicInst.h 
skipping to change at line 37 skipping to change at line 37
#include "llvm/Constants.h" #include "llvm/Constants.h"
#include "llvm/Function.h" #include "llvm/Function.h"
#include "llvm/Instructions.h" #include "llvm/Instructions.h"
#include "llvm/Intrinsics.h" #include "llvm/Intrinsics.h"
namespace llvm { namespace llvm {
/// IntrinsicInst - A useful wrapper class for inspecting calls to intrin sic /// IntrinsicInst - A useful wrapper class for inspecting calls to intrin sic
/// functions. This allows the standard isa/dyncast/cast functionality t o /// functions. This allows the standard isa/dyncast/cast functionality t o
/// work with calls to intrinsic functions. /// work with calls to intrinsic functions.
class IntrinsicInst : public CallInst { class IntrinsicInst : public CallInst {
IntrinsicInst(); // DO NOT IMPLEMENT IntrinsicInst() LLVM_DELETED_FUNCTION;
IntrinsicInst(const IntrinsicInst&); // DO NOT IMPLEMENT IntrinsicInst(const IntrinsicInst&) LLVM_DELETED_FUNCTION;
void operator=(const IntrinsicInst&); // DO NOT IMPLEMENT void operator=(const IntrinsicInst&) LLVM_DELETED_FUNCTION;
public: public:
/// getIntrinsicID - Return the intrinsic ID of this intrinsic. /// getIntrinsicID - Return the intrinsic ID of this intrinsic.
/// ///
Intrinsic::ID getIntrinsicID() const { Intrinsic::ID getIntrinsicID() const {
return (Intrinsic::ID)getCalledFunction()->getIntrinsicID(); return (Intrinsic::ID)getCalledFunction()->getIntrinsicID();
} }
// Methods for support type inquiry through isa, cast, and dyn_cast: // Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const IntrinsicInst *) { return true; }
static inline bool classof(const CallInst *I) { static inline bool classof(const CallInst *I) {
if (const Function *CF = I->getCalledFunction()) if (const Function *CF = I->getCalledFunction())
return CF->getIntrinsicID() != 0; return CF->getIntrinsicID() != 0;
return false; return false;
} }
static inline bool classof(const Value *V) { static inline bool classof(const Value *V) {
return isa<CallInst>(V) && classof(cast<CallInst>(V)); return isa<CallInst>(V) && classof(cast<CallInst>(V));
} }
}; };
/// DbgInfoIntrinsic - This is the common base class for debug info intri nsics /// DbgInfoIntrinsic - This is the common base class for debug info intri nsics
/// ///
class DbgInfoIntrinsic : public IntrinsicInst { class DbgInfoIntrinsic : public IntrinsicInst {
public: public:
// Methods for support type inquiry through isa, cast, and dyn_cast: // Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const DbgInfoIntrinsic *) { return true; }
static inline bool classof(const IntrinsicInst *I) { static inline bool classof(const IntrinsicInst *I) {
switch (I->getIntrinsicID()) { switch (I->getIntrinsicID()) {
case Intrinsic::dbg_declare: case Intrinsic::dbg_declare:
case Intrinsic::dbg_value: case Intrinsic::dbg_value:
return true; return true;
default: return false; default: return false;
} }
} }
static inline bool classof(const Value *V) { static inline bool classof(const Value *V) {
return isa<IntrinsicInst>(V) && classof(cast<IntrinsicInst>(V)); return isa<IntrinsicInst>(V) && classof(cast<IntrinsicInst>(V));
skipping to change at line 89 skipping to change at line 87
}; };
/// DbgDeclareInst - This represents the llvm.dbg.declare instruction. /// DbgDeclareInst - This represents the llvm.dbg.declare instruction.
/// ///
class DbgDeclareInst : public DbgInfoIntrinsic { class DbgDeclareInst : public DbgInfoIntrinsic {
public: public:
Value *getAddress() const; Value *getAddress() const;
MDNode *getVariable() const { return cast<MDNode>(getArgOperand(1)); } MDNode *getVariable() const { return cast<MDNode>(getArgOperand(1)); }
// Methods for support type inquiry through isa, cast, and dyn_cast: // Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const DbgDeclareInst *) { return true; }
static inline bool classof(const IntrinsicInst *I) { static inline bool classof(const IntrinsicInst *I) {
return I->getIntrinsicID() == Intrinsic::dbg_declare; return I->getIntrinsicID() == Intrinsic::dbg_declare;
} }
static inline bool classof(const Value *V) { static inline bool classof(const Value *V) {
return isa<IntrinsicInst>(V) && classof(cast<IntrinsicInst>(V)); return isa<IntrinsicInst>(V) && classof(cast<IntrinsicInst>(V));
} }
}; };
/// DbgValueInst - This represents the llvm.dbg.value instruction. /// DbgValueInst - This represents the llvm.dbg.value instruction.
/// ///
skipping to change at line 111 skipping to change at line 108
public: public:
const Value *getValue() const; const Value *getValue() const;
Value *getValue(); Value *getValue();
uint64_t getOffset() const { uint64_t getOffset() const {
return cast<ConstantInt>( return cast<ConstantInt>(
const_cast<Value*>(getArgOperand(1)))->getZExtVal ue(); const_cast<Value*>(getArgOperand(1)))->getZExtVal ue();
} }
MDNode *getVariable() const { return cast<MDNode>(getArgOperand(2)); } MDNode *getVariable() const { return cast<MDNode>(getArgOperand(2)); }
// Methods for support type inquiry through isa, cast, and dyn_cast: // Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const DbgValueInst *) { return true; }
static inline bool classof(const IntrinsicInst *I) { static inline bool classof(const IntrinsicInst *I) {
return I->getIntrinsicID() == Intrinsic::dbg_value; return I->getIntrinsicID() == Intrinsic::dbg_value;
} }
static inline bool classof(const Value *V) { static inline bool classof(const Value *V) {
return isa<IntrinsicInst>(V) && classof(cast<IntrinsicInst>(V)); return isa<IntrinsicInst>(V) && classof(cast<IntrinsicInst>(V));
} }
}; };
/// MemIntrinsic - This is the common base class for memset/memcpy/memmov e. /// MemIntrinsic - This is the common base class for memset/memcpy/memmov e.
/// ///
skipping to change at line 178 skipping to change at line 174
void setVolatile(Constant* V) { void setVolatile(Constant* V) {
setArgOperand(4, V); setArgOperand(4, V);
} }
Type *getAlignmentType() const { Type *getAlignmentType() const {
return getArgOperand(3)->getType(); return getArgOperand(3)->getType();
} }
// Methods for support type inquiry through isa, cast, and dyn_cast: // Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const MemIntrinsic *) { return true; }
static inline bool classof(const IntrinsicInst *I) { static inline bool classof(const IntrinsicInst *I) {
switch (I->getIntrinsicID()) { switch (I->getIntrinsicID()) {
case Intrinsic::memcpy: case Intrinsic::memcpy:
case Intrinsic::memmove: case Intrinsic::memmove:
case Intrinsic::memset: case Intrinsic::memset:
return true; return true;
default: return false; default: return false;
} }
} }
static inline bool classof(const Value *V) { static inline bool classof(const Value *V) {
skipping to change at line 208 skipping to change at line 203
/// ///
Value *getValue() const { return const_cast<Value*>(getArgOperand(1)); } Value *getValue() const { return const_cast<Value*>(getArgOperand(1)); }
void setValue(Value *Val) { void setValue(Value *Val) {
assert(getValue()->getType() == Val->getType() && assert(getValue()->getType() == Val->getType() &&
"setValue called with value of wrong type!"); "setValue called with value of wrong type!");
setArgOperand(1, Val); setArgOperand(1, Val);
} }
// Methods for support type inquiry through isa, cast, and dyn_cast: // Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const MemSetInst *) { return true; }
static inline bool classof(const IntrinsicInst *I) { static inline bool classof(const IntrinsicInst *I) {
return I->getIntrinsicID() == Intrinsic::memset; return I->getIntrinsicID() == Intrinsic::memset;
} }
static inline bool classof(const Value *V) { static inline bool classof(const Value *V) {
return isa<IntrinsicInst>(V) && classof(cast<IntrinsicInst>(V)); return isa<IntrinsicInst>(V) && classof(cast<IntrinsicInst>(V));
} }
}; };
/// MemTransferInst - This class wraps the llvm.memcpy/memmove intrinsics . /// MemTransferInst - This class wraps the llvm.memcpy/memmove intrinsics .
/// ///
skipping to change at line 241 skipping to change at line 235
return cast<PointerType>(getRawSource()->getType())->getAddressSpace( ); return cast<PointerType>(getRawSource()->getType())->getAddressSpace( );
} }
void setSource(Value *Ptr) { void setSource(Value *Ptr) {
assert(getRawSource()->getType() == Ptr->getType() && assert(getRawSource()->getType() == Ptr->getType() &&
"setSource called with pointer of wrong type!"); "setSource called with pointer of wrong type!");
setArgOperand(1, Ptr); setArgOperand(1, Ptr);
} }
// Methods for support type inquiry through isa, cast, and dyn_cast: // Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const MemTransferInst *) { return true; }
static inline bool classof(const IntrinsicInst *I) { static inline bool classof(const IntrinsicInst *I) {
return I->getIntrinsicID() == Intrinsic::memcpy || return I->getIntrinsicID() == Intrinsic::memcpy ||
I->getIntrinsicID() == Intrinsic::memmove; I->getIntrinsicID() == Intrinsic::memmove;
} }
static inline bool classof(const Value *V) { static inline bool classof(const Value *V) {
return isa<IntrinsicInst>(V) && classof(cast<IntrinsicInst>(V)); return isa<IntrinsicInst>(V) && classof(cast<IntrinsicInst>(V));
} }
}; };
/// MemCpyInst - This class wraps the llvm.memcpy intrinsic. /// MemCpyInst - This class wraps the llvm.memcpy intrinsic.
/// ///
class MemCpyInst : public MemTransferInst { class MemCpyInst : public MemTransferInst {
public: public:
// Methods for support type inquiry through isa, cast, and dyn_cast: // Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const MemCpyInst *) { return true; }
static inline bool classof(const IntrinsicInst *I) { static inline bool classof(const IntrinsicInst *I) {
return I->getIntrinsicID() == Intrinsic::memcpy; return I->getIntrinsicID() == Intrinsic::memcpy;
} }
static inline bool classof(const Value *V) { static inline bool classof(const Value *V) {
return isa<IntrinsicInst>(V) && classof(cast<IntrinsicInst>(V)); return isa<IntrinsicInst>(V) && classof(cast<IntrinsicInst>(V));
} }
}; };
/// MemMoveInst - This class wraps the llvm.memmove intrinsic. /// MemMoveInst - This class wraps the llvm.memmove intrinsic.
/// ///
class MemMoveInst : public MemTransferInst { class MemMoveInst : public MemTransferInst {
public: public:
// Methods for support type inquiry through isa, cast, and dyn_cast: // Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const MemMoveInst *) { return true; }
static inline bool classof(const IntrinsicInst *I) { static inline bool classof(const IntrinsicInst *I) {
return I->getIntrinsicID() == Intrinsic::memmove; return I->getIntrinsicID() == Intrinsic::memmove;
} }
static inline bool classof(const Value *V) { static inline bool classof(const Value *V) {
return isa<IntrinsicInst>(V) && classof(cast<IntrinsicInst>(V)); return isa<IntrinsicInst>(V) && classof(cast<IntrinsicInst>(V));
} }
}; };
/// VAStartInst - This represents the llvm.va_start intrinsic.
///
class VAStartInst : public IntrinsicInst {
public:
static inline bool classof(const IntrinsicInst *I) {
return I->getIntrinsicID() == Intrinsic::vastart;
}
static inline bool classof(const Value *V) {
return isa<IntrinsicInst>(V) && classof(cast<IntrinsicInst>(V));
}
Value *getArgList() const { return const_cast<Value*>(getArgOperand(0))
; }
};
/// VAEndInst - This represents the llvm.va_end intrinsic.
///
class VAEndInst : public IntrinsicInst {
public:
static inline bool classof(const IntrinsicInst *I) {
return I->getIntrinsicID() == Intrinsic::vaend;
}
static inline bool classof(const Value *V) {
return isa<IntrinsicInst>(V) && classof(cast<IntrinsicInst>(V));
}
Value *getArgList() const { return const_cast<Value*>(getArgOperand(0))
; }
};
/// VACopyInst - This represents the llvm.va_copy intrinsic.
///
class VACopyInst : public IntrinsicInst {
public:
static inline bool classof(const IntrinsicInst *I) {
return I->getIntrinsicID() == Intrinsic::vacopy;
}
static inline bool classof(const Value *V) {
return isa<IntrinsicInst>(V) && classof(cast<IntrinsicInst>(V));
}
Value *getDest() const { return const_cast<Value*>(getArgOperand(0)); }
Value *getSrc() const { return const_cast<Value*>(getArgOperand(1)); }
};
} }
#endif #endif
 End of changes. 11 change blocks. 
12 lines changed or deleted 48 lines changed or added


 IntrinsicLowering.h   IntrinsicLowering.h 
skipping to change at line 24 skipping to change at line 24
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_CODEGEN_INTRINSICLOWERING_H #ifndef LLVM_CODEGEN_INTRINSICLOWERING_H
#define LLVM_CODEGEN_INTRINSICLOWERING_H #define LLVM_CODEGEN_INTRINSICLOWERING_H
#include "llvm/Intrinsics.h" #include "llvm/Intrinsics.h"
namespace llvm { namespace llvm {
class CallInst; class CallInst;
class Module; class Module;
class TargetData; class DataLayout;
class IntrinsicLowering { class IntrinsicLowering {
const TargetData& TD; const DataLayout& TD;
bool Warned; bool Warned;
public: public:
explicit IntrinsicLowering(const TargetData &td) : explicit IntrinsicLowering(const DataLayout &td) :
TD(td), Warned(false) {} TD(td), Warned(false) {}
/// AddPrototypes - This method, if called, causes all of the prototype s /// AddPrototypes - This method, if called, causes all of the prototype s
/// that might be needed by an intrinsic lowering implementation to be /// that might be needed by an intrinsic lowering implementation to be
/// inserted into the module specified. /// inserted into the module specified.
void AddPrototypes(Module &M); void AddPrototypes(Module &M);
/// LowerIntrinsicCall - This method replaces a call with the LLVM func tion /// LowerIntrinsicCall - This method replaces a call with the LLVM func tion
/// which should be used to implement the specified intrinsic function call. /// which should be used to implement the specified intrinsic function call.
/// If an intrinsic function must be implemented by the code generator /// If an intrinsic function must be implemented by the code generator
 End of changes. 3 change blocks. 
3 lines changed or deleted 3 lines changed or added


 Intrinsics.gen   Intrinsics.gen 
//===- TableGen'erated file -------------------------------------*- C++ -*- /*===- TableGen'erated file -------------------------------------*- C++ -*-
===// ===*\
// |*
// Intrinsic Function Source Fragment *|
// |* Intrinsic Function Source Fragment
// Automatically generated file, do not edit! *|
// |*
//===---------------------------------------------------------------------- *|
===// |* Automatically generated file, do not edit!
*|
|*
*|
\*===----------------------------------------------------------------------
===*/
// VisualStudio defines setjmp as _setjmp // VisualStudio defines setjmp as _setjmp
#if defined(_MSC_VER) && defined(setjmp) && \ #if defined(_MSC_VER) && defined(setjmp) && \
!defined(setjmp_undefined_for_msvc) !defined(setjmp_undefined_for_msvc)
# pragma push_macro("setjmp") # pragma push_macro("setjmp")
# undef setjmp # undef setjmp
# define setjmp_undefined_for_msvc # define setjmp_undefined_for_msvc
#endif #endif
// Enum values for Intrinsics.h // Enum values for Intrinsics.h
skipping to change at line 39 skipping to change at line 39
arm_mrc, // llvm.arm.mrc arm_mrc, // llvm.arm.mrc
arm_mrc2, // llvm.arm.mrc2 arm_mrc2, // llvm.arm.mrc2
arm_neon_vabds, // llvm.arm.neon.vabds arm_neon_vabds, // llvm.arm.neon.vabds
arm_neon_vabdu, // llvm.arm.neon.vabdu arm_neon_vabdu, // llvm.arm.neon.vabdu
arm_neon_vabs, // llvm.arm.neon.vabs arm_neon_vabs, // llvm.arm.neon.vabs
arm_neon_vacged, // llvm.arm.neon.vacged arm_neon_vacged, // llvm.arm.neon.vacged
arm_neon_vacgeq, // llvm.arm.neon.vacgeq arm_neon_vacgeq, // llvm.arm.neon.vacgeq
arm_neon_vacgtd, // llvm.arm.neon.vacgtd arm_neon_vacgtd, // llvm.arm.neon.vacgtd
arm_neon_vacgtq, // llvm.arm.neon.vacgtq arm_neon_vacgtq, // llvm.arm.neon.vacgtq
arm_neon_vaddhn, // llvm.arm.neon.vaddhn arm_neon_vaddhn, // llvm.arm.neon.vaddhn
arm_neon_vbsl, // llvm.arm.neon.vbsl
arm_neon_vcls, // llvm.arm.neon.vcls arm_neon_vcls, // llvm.arm.neon.vcls
arm_neon_vclz, // llvm.arm.neon.vclz arm_neon_vclz, // llvm.arm.neon.vclz
arm_neon_vcnt, // llvm.arm.neon.vcnt arm_neon_vcnt, // llvm.arm.neon.vcnt
arm_neon_vcvtfp2fxs, // llvm.arm.neon.vcvtfp2fxs arm_neon_vcvtfp2fxs, // llvm.arm.neon.vcvtfp2fxs
arm_neon_vcvtfp2fxu, // llvm.arm.neon.vcvtfp2fxu arm_neon_vcvtfp2fxu, // llvm.arm.neon.vcvtfp2fxu
arm_neon_vcvtfp2hf, // llvm.arm.neon.vcvtfp2hf arm_neon_vcvtfp2hf, // llvm.arm.neon.vcvtfp2hf
arm_neon_vcvtfxs2fp, // llvm.arm.neon.vcvtfxs2fp arm_neon_vcvtfxs2fp, // llvm.arm.neon.vcvtfxs2fp
arm_neon_vcvtfxu2fp, // llvm.arm.neon.vcvtfxu2fp arm_neon_vcvtfxu2fp, // llvm.arm.neon.vcvtfxu2fp
arm_neon_vcvthf2fp, // llvm.arm.neon.vcvthf2fp arm_neon_vcvthf2fp, // llvm.arm.neon.vcvthf2fp
arm_neon_vhadds, // llvm.arm.neon.vhadds arm_neon_vhadds, // llvm.arm.neon.vhadds
skipping to change at line 159 skipping to change at line 160
convertsif, // llvm.convertsif convertsif, // llvm.convertsif
convertss, // llvm.convertss convertss, // llvm.convertss
convertsu, // llvm.convertsu convertsu, // llvm.convertsu
convertuif, // llvm.convertuif convertuif, // llvm.convertuif
convertus, // llvm.convertus convertus, // llvm.convertus
convertuu, // llvm.convertuu convertuu, // llvm.convertuu
cos, // llvm.cos cos, // llvm.cos
ctlz, // llvm.ctlz ctlz, // llvm.ctlz
ctpop, // llvm.ctpop ctpop, // llvm.ctpop
cttz, // llvm.cttz cttz, // llvm.cttz
cuda_syncthreads, // llvm.cuda.syncthreads
dbg_declare, // llvm.dbg.declare dbg_declare, // llvm.dbg.declare
dbg_value, // llvm.dbg.value dbg_value, // llvm.dbg.value
debugtrap, // llvm.debugtrap
donothing, // llvm.donothing
eh_dwarf_cfa, // llvm.eh.dwarf.cfa eh_dwarf_cfa, // llvm.eh.dwarf.cfa
eh_return_i32, // llvm.eh.return.i32 eh_return_i32, // llvm.eh.return.i32
eh_return_i64, // llvm.eh.return.i64 eh_return_i64, // llvm.eh.return.i64
eh_sjlj_callsite, // llvm.eh.sjlj.callsite eh_sjlj_callsite, // llvm.eh.sjlj.callsite
eh_sjlj_functioncontext, // llvm.eh.sjlj.functionconte xt eh_sjlj_functioncontext, // llvm.eh.sjlj.functionconte xt
eh_sjlj_longjmp, // llvm.eh.sjlj.longjmp eh_sjlj_longjmp, // llvm.eh.sjlj.longjmp
eh_sjlj_lsda, // llvm.eh.sjlj.lsda eh_sjlj_lsda, // llvm.eh.sjlj.lsda
eh_sjlj_setjmp, // llvm.eh.sjlj.setjmp eh_sjlj_setjmp, // llvm.eh.sjlj.setjmp
eh_typeid_for, // llvm.eh.typeid.for eh_typeid_for, // llvm.eh.typeid.for
eh_unwind_init, // llvm.eh.unwind.init eh_unwind_init, // llvm.eh.unwind.init
exp, // llvm.exp exp, // llvm.exp
exp2, // llvm.exp2 exp2, // llvm.exp2
expect, // llvm.expect expect, // llvm.expect
fabs, // llvm.fabs
floor, // llvm.floor
flt_rounds, // llvm.flt.rounds flt_rounds, // llvm.flt.rounds
fma, // llvm.fma fma, // llvm.fma
fmuladd, // llvm.fmuladd
frameaddress, // llvm.frameaddress frameaddress, // llvm.frameaddress
gcread, // llvm.gcread gcread, // llvm.gcread
gcroot, // llvm.gcroot gcroot, // llvm.gcroot
gcwrite, // llvm.gcwrite gcwrite, // llvm.gcwrite
hexagon_A2_abs, // llvm.hexagon.A2.abs hexagon_A2_abs, // llvm.hexagon.A2.abs
hexagon_A2_absp, // llvm.hexagon.A2.absp hexagon_A2_absp, // llvm.hexagon.A2.absp
hexagon_A2_abssat, // llvm.hexagon.A2.abssat hexagon_A2_abssat, // llvm.hexagon.A2.abssat
hexagon_A2_add, // llvm.hexagon.A2.add hexagon_A2_add, // llvm.hexagon.A2.add
hexagon_A2_addh_h16_hh, // llvm.hexagon.A2.addh.h16.h h hexagon_A2_addh_h16_hh, // llvm.hexagon.A2.addh.h16.h h
hexagon_A2_addh_h16_hl, // llvm.hexagon.A2.addh.h16.h l hexagon_A2_addh_h16_hl, // llvm.hexagon.A2.addh.h16.h l
hexagon_A2_addh_h16_lh, // llvm.hexagon.A2.addh.h16.l h hexagon_A2_addh_h16_lh, // llvm.hexagon.A2.addh.h16.l h
hexagon_A2_addh_h16_ll, // llvm.hexagon.A2.addh.h16.l l hexagon_A2_addh_h16_ll, // llvm.hexagon.A2.addh.h16.l l
hexagon_A2_addh_h16_sat_hh, // llvm.hexagon.A2.addh.h16.s at.hh hexagon_A2_addh_h16_sat_hh, // llvm.hexagon.A2.addh.h16.s at.hh
hexagon_A2_addh_h16_sat_hl, // llvm.hexagon.A2.addh.h16.s at.hl hexagon_A2_addh_h16_sat_hl, // llvm.hexagon.A2.addh.h16.s at.hl
hexagon_A2_addh_h16_sat_lh, // llvm.hexagon.A2.addh.h16.s at.lh hexagon_A2_addh_h16_sat_lh, // llvm.hexagon.A2.addh.h16.s at.lh
hexagon_A2_addh_h16_sat_ll, // llvm.hexagon.A2.addh.h16.s at.ll hexagon_A2_addh_h16_sat_ll, // llvm.hexagon.A2.addh.h16.s at.ll
hexagon_A2_addh_l16_hh, // llvm.hexagon.A2.addh.l16.h h
hexagon_A2_addh_l16_hl, // llvm.hexagon.A2.addh.l16.h l hexagon_A2_addh_l16_hl, // llvm.hexagon.A2.addh.l16.h l
hexagon_A2_addh_l16_lh, // llvm.hexagon.A2.addh.l16.l h
hexagon_A2_addh_l16_ll, // llvm.hexagon.A2.addh.l16.l l hexagon_A2_addh_l16_ll, // llvm.hexagon.A2.addh.l16.l l
hexagon_A2_addh_l16_sat_hh, // llvm.hexagon.A2.addh.l16.s at.hh
hexagon_A2_addh_l16_sat_hl, // llvm.hexagon.A2.addh.l16.s at.hl hexagon_A2_addh_l16_sat_hl, // llvm.hexagon.A2.addh.l16.s at.hl
hexagon_A2_addh_l16_sat_lh, // llvm.hexagon.A2.addh.l16.s at.lh
hexagon_A2_addh_l16_sat_ll, // llvm.hexagon.A2.addh.l16.s at.ll hexagon_A2_addh_l16_sat_ll, // llvm.hexagon.A2.addh.l16.s at.ll
hexagon_A2_addi, // llvm.hexagon.A2.addi hexagon_A2_addi, // llvm.hexagon.A2.addi
hexagon_A2_addp, // llvm.hexagon.A2.addp hexagon_A2_addp, // llvm.hexagon.A2.addp
hexagon_A2_addpsat, // llvm.hexagon.A2.addpsat hexagon_A2_addpsat, // llvm.hexagon.A2.addpsat
hexagon_A2_addsat, // llvm.hexagon.A2.addsat hexagon_A2_addsat, // llvm.hexagon.A2.addsat
hexagon_A2_addsp, // llvm.hexagon.A2.addsp hexagon_A2_addsp, // llvm.hexagon.A2.addsp
hexagon_A2_and, // llvm.hexagon.A2.and hexagon_A2_and, // llvm.hexagon.A2.and
hexagon_A2_andir, // llvm.hexagon.A2.andir hexagon_A2_andir, // llvm.hexagon.A2.andir
hexagon_A2_andp, // llvm.hexagon.A2.andp hexagon_A2_andp, // llvm.hexagon.A2.andp
hexagon_A2_aslh, // llvm.hexagon.A2.aslh hexagon_A2_aslh, // llvm.hexagon.A2.aslh
skipping to change at line 232 skipping to change at line 235
hexagon_A2_minu, // llvm.hexagon.A2.minu hexagon_A2_minu, // llvm.hexagon.A2.minu
hexagon_A2_minup, // llvm.hexagon.A2.minup hexagon_A2_minup, // llvm.hexagon.A2.minup
hexagon_A2_neg, // llvm.hexagon.A2.neg hexagon_A2_neg, // llvm.hexagon.A2.neg
hexagon_A2_negp, // llvm.hexagon.A2.negp hexagon_A2_negp, // llvm.hexagon.A2.negp
hexagon_A2_negsat, // llvm.hexagon.A2.negsat hexagon_A2_negsat, // llvm.hexagon.A2.negsat
hexagon_A2_not, // llvm.hexagon.A2.not hexagon_A2_not, // llvm.hexagon.A2.not
hexagon_A2_notp, // llvm.hexagon.A2.notp hexagon_A2_notp, // llvm.hexagon.A2.notp
hexagon_A2_or, // llvm.hexagon.A2.or hexagon_A2_or, // llvm.hexagon.A2.or
hexagon_A2_orir, // llvm.hexagon.A2.orir hexagon_A2_orir, // llvm.hexagon.A2.orir
hexagon_A2_orp, // llvm.hexagon.A2.orp hexagon_A2_orp, // llvm.hexagon.A2.orp
hexagon_A2_roundsat, // llvm.hexagon.A2.roundsat
hexagon_A2_sat, // llvm.hexagon.A2.sat hexagon_A2_sat, // llvm.hexagon.A2.sat
hexagon_A2_satb, // llvm.hexagon.A2.satb hexagon_A2_satb, // llvm.hexagon.A2.satb
hexagon_A2_sath, // llvm.hexagon.A2.sath hexagon_A2_sath, // llvm.hexagon.A2.sath
hexagon_A2_satub, // llvm.hexagon.A2.satub hexagon_A2_satub, // llvm.hexagon.A2.satub
hexagon_A2_satuh, // llvm.hexagon.A2.satuh hexagon_A2_satuh, // llvm.hexagon.A2.satuh
hexagon_A2_sub, // llvm.hexagon.A2.sub hexagon_A2_sub, // llvm.hexagon.A2.sub
hexagon_A2_subh_h16_hh, // llvm.hexagon.A2.subh.h16.h h hexagon_A2_subh_h16_hh, // llvm.hexagon.A2.subh.h16.h h
hexagon_A2_subh_h16_hl, // llvm.hexagon.A2.subh.h16.h l hexagon_A2_subh_h16_hl, // llvm.hexagon.A2.subh.h16.h l
hexagon_A2_subh_h16_lh, // llvm.hexagon.A2.subh.h16.l h hexagon_A2_subh_h16_lh, // llvm.hexagon.A2.subh.h16.l h
hexagon_A2_subh_h16_ll, // llvm.hexagon.A2.subh.h16.l l hexagon_A2_subh_h16_ll, // llvm.hexagon.A2.subh.h16.l l
skipping to change at line 276 skipping to change at line 280
hexagon_A2_tfr, // llvm.hexagon.A2.tfr hexagon_A2_tfr, // llvm.hexagon.A2.tfr
hexagon_A2_tfrih, // llvm.hexagon.A2.tfrih hexagon_A2_tfrih, // llvm.hexagon.A2.tfrih
hexagon_A2_tfril, // llvm.hexagon.A2.tfril hexagon_A2_tfril, // llvm.hexagon.A2.tfril
hexagon_A2_tfrp, // llvm.hexagon.A2.tfrp hexagon_A2_tfrp, // llvm.hexagon.A2.tfrp
hexagon_A2_tfrpi, // llvm.hexagon.A2.tfrpi hexagon_A2_tfrpi, // llvm.hexagon.A2.tfrpi
hexagon_A2_tfrsi, // llvm.hexagon.A2.tfrsi hexagon_A2_tfrsi, // llvm.hexagon.A2.tfrsi
hexagon_A2_vabsh, // llvm.hexagon.A2.vabsh hexagon_A2_vabsh, // llvm.hexagon.A2.vabsh
hexagon_A2_vabshsat, // llvm.hexagon.A2.vabshsat hexagon_A2_vabshsat, // llvm.hexagon.A2.vabshsat
hexagon_A2_vabsw, // llvm.hexagon.A2.vabsw hexagon_A2_vabsw, // llvm.hexagon.A2.vabsw
hexagon_A2_vabswsat, // llvm.hexagon.A2.vabswsat hexagon_A2_vabswsat, // llvm.hexagon.A2.vabswsat
hexagon_A2_vaddb_map, // llvm.hexagon.A2.vaddb.map
hexagon_A2_vaddh, // llvm.hexagon.A2.vaddh hexagon_A2_vaddh, // llvm.hexagon.A2.vaddh
hexagon_A2_vaddhs, // llvm.hexagon.A2.vaddhs hexagon_A2_vaddhs, // llvm.hexagon.A2.vaddhs
hexagon_A2_vaddub, // llvm.hexagon.A2.vaddub hexagon_A2_vaddub, // llvm.hexagon.A2.vaddub
hexagon_A2_vaddubs, // llvm.hexagon.A2.vaddubs hexagon_A2_vaddubs, // llvm.hexagon.A2.vaddubs
hexagon_A2_vadduhs, // llvm.hexagon.A2.vadduhs hexagon_A2_vadduhs, // llvm.hexagon.A2.vadduhs
hexagon_A2_vaddw, // llvm.hexagon.A2.vaddw hexagon_A2_vaddw, // llvm.hexagon.A2.vaddw
hexagon_A2_vaddws, // llvm.hexagon.A2.vaddws hexagon_A2_vaddws, // llvm.hexagon.A2.vaddws
hexagon_A2_vavgh, // llvm.hexagon.A2.vavgh hexagon_A2_vavgh, // llvm.hexagon.A2.vavgh
hexagon_A2_vavghcr, // llvm.hexagon.A2.vavghcr hexagon_A2_vavghcr, // llvm.hexagon.A2.vavghcr
hexagon_A2_vavghr, // llvm.hexagon.A2.vavghr hexagon_A2_vavghr, // llvm.hexagon.A2.vavghr
skipping to change at line 304 skipping to change at line 309
hexagon_A2_vavgwr, // llvm.hexagon.A2.vavgwr hexagon_A2_vavgwr, // llvm.hexagon.A2.vavgwr
hexagon_A2_vcmpbeq, // llvm.hexagon.A2.vcmpbeq hexagon_A2_vcmpbeq, // llvm.hexagon.A2.vcmpbeq
hexagon_A2_vcmpbgtu, // llvm.hexagon.A2.vcmpbgtu hexagon_A2_vcmpbgtu, // llvm.hexagon.A2.vcmpbgtu
hexagon_A2_vcmpheq, // llvm.hexagon.A2.vcmpheq hexagon_A2_vcmpheq, // llvm.hexagon.A2.vcmpheq
hexagon_A2_vcmphgt, // llvm.hexagon.A2.vcmphgt hexagon_A2_vcmphgt, // llvm.hexagon.A2.vcmphgt
hexagon_A2_vcmphgtu, // llvm.hexagon.A2.vcmphgtu hexagon_A2_vcmphgtu, // llvm.hexagon.A2.vcmphgtu
hexagon_A2_vcmpweq, // llvm.hexagon.A2.vcmpweq hexagon_A2_vcmpweq, // llvm.hexagon.A2.vcmpweq
hexagon_A2_vcmpwgt, // llvm.hexagon.A2.vcmpwgt hexagon_A2_vcmpwgt, // llvm.hexagon.A2.vcmpwgt
hexagon_A2_vcmpwgtu, // llvm.hexagon.A2.vcmpwgtu hexagon_A2_vcmpwgtu, // llvm.hexagon.A2.vcmpwgtu
hexagon_A2_vconj, // llvm.hexagon.A2.vconj hexagon_A2_vconj, // llvm.hexagon.A2.vconj
hexagon_A2_vmaxb, // llvm.hexagon.A2.vmaxb
hexagon_A2_vmaxh, // llvm.hexagon.A2.vmaxh hexagon_A2_vmaxh, // llvm.hexagon.A2.vmaxh
hexagon_A2_vmaxub, // llvm.hexagon.A2.vmaxub hexagon_A2_vmaxub, // llvm.hexagon.A2.vmaxub
hexagon_A2_vmaxuh, // llvm.hexagon.A2.vmaxuh hexagon_A2_vmaxuh, // llvm.hexagon.A2.vmaxuh
hexagon_A2_vmaxuw, // llvm.hexagon.A2.vmaxuw hexagon_A2_vmaxuw, // llvm.hexagon.A2.vmaxuw
hexagon_A2_vmaxw, // llvm.hexagon.A2.vmaxw hexagon_A2_vmaxw, // llvm.hexagon.A2.vmaxw
hexagon_A2_vminb, // llvm.hexagon.A2.vminb
hexagon_A2_vminh, // llvm.hexagon.A2.vminh hexagon_A2_vminh, // llvm.hexagon.A2.vminh
hexagon_A2_vminub, // llvm.hexagon.A2.vminub hexagon_A2_vminub, // llvm.hexagon.A2.vminub
hexagon_A2_vminuh, // llvm.hexagon.A2.vminuh hexagon_A2_vminuh, // llvm.hexagon.A2.vminuh
hexagon_A2_vminuw, // llvm.hexagon.A2.vminuw hexagon_A2_vminuw, // llvm.hexagon.A2.vminuw
hexagon_A2_vminw, // llvm.hexagon.A2.vminw hexagon_A2_vminw, // llvm.hexagon.A2.vminw
hexagon_A2_vnavgh, // llvm.hexagon.A2.vnavgh hexagon_A2_vnavgh, // llvm.hexagon.A2.vnavgh
hexagon_A2_vnavghcr, // llvm.hexagon.A2.vnavghcr hexagon_A2_vnavghcr, // llvm.hexagon.A2.vnavghcr
hexagon_A2_vnavghr, // llvm.hexagon.A2.vnavghr hexagon_A2_vnavghr, // llvm.hexagon.A2.vnavghr
hexagon_A2_vnavgw, // llvm.hexagon.A2.vnavgw hexagon_A2_vnavgw, // llvm.hexagon.A2.vnavgw
hexagon_A2_vnavgwcr, // llvm.hexagon.A2.vnavgwcr hexagon_A2_vnavgwcr, // llvm.hexagon.A2.vnavgwcr
hexagon_A2_vnavgwr, // llvm.hexagon.A2.vnavgwr hexagon_A2_vnavgwr, // llvm.hexagon.A2.vnavgwr
hexagon_A2_vraddub, // llvm.hexagon.A2.vraddub hexagon_A2_vraddub, // llvm.hexagon.A2.vraddub
hexagon_A2_vraddub_acc, // llvm.hexagon.A2.vraddub.ac c hexagon_A2_vraddub_acc, // llvm.hexagon.A2.vraddub.ac c
hexagon_A2_vrsadub, // llvm.hexagon.A2.vrsadub hexagon_A2_vrsadub, // llvm.hexagon.A2.vrsadub
hexagon_A2_vrsadub_acc, // llvm.hexagon.A2.vrsadub.ac c hexagon_A2_vrsadub_acc, // llvm.hexagon.A2.vrsadub.ac c
hexagon_A2_vsubb_map, // llvm.hexagon.A2.vsubb.map
hexagon_A2_vsubh, // llvm.hexagon.A2.vsubh hexagon_A2_vsubh, // llvm.hexagon.A2.vsubh
hexagon_A2_vsubhs, // llvm.hexagon.A2.vsubhs hexagon_A2_vsubhs, // llvm.hexagon.A2.vsubhs
hexagon_A2_vsubub, // llvm.hexagon.A2.vsubub hexagon_A2_vsubub, // llvm.hexagon.A2.vsubub
hexagon_A2_vsububs, // llvm.hexagon.A2.vsububs hexagon_A2_vsububs, // llvm.hexagon.A2.vsububs
hexagon_A2_vsubuhs, // llvm.hexagon.A2.vsubuhs hexagon_A2_vsubuhs, // llvm.hexagon.A2.vsubuhs
hexagon_A2_vsubw, // llvm.hexagon.A2.vsubw hexagon_A2_vsubw, // llvm.hexagon.A2.vsubw
hexagon_A2_vsubws, // llvm.hexagon.A2.vsubws hexagon_A2_vsubws, // llvm.hexagon.A2.vsubws
hexagon_A2_xor, // llvm.hexagon.A2.xor hexagon_A2_xor, // llvm.hexagon.A2.xor
hexagon_A2_xorp, // llvm.hexagon.A2.xorp hexagon_A2_xorp, // llvm.hexagon.A2.xorp
hexagon_A2_zxtb, // llvm.hexagon.A2.zxtb hexagon_A2_zxtb, // llvm.hexagon.A2.zxtb
hexagon_A2_zxth, // llvm.hexagon.A2.zxth hexagon_A2_zxth, // llvm.hexagon.A2.zxth
hexagon_A4_andn, // llvm.hexagon.A4.andn hexagon_A4_andn, // llvm.hexagon.A4.andn
hexagon_A4_andnp, // llvm.hexagon.A4.andnp hexagon_A4_andnp, // llvm.hexagon.A4.andnp
hexagon_A4_bitsplit, // llvm.hexagon.A4.bitsplit
hexagon_A4_bitspliti, // llvm.hexagon.A4.bitspliti
hexagon_A4_boundscheck, // llvm.hexagon.A4.boundschec
k
hexagon_A4_cmpbeq, // llvm.hexagon.A4.cmpbeq
hexagon_A4_cmpbeqi, // llvm.hexagon.A4.cmpbeqi
hexagon_A4_cmpbgt, // llvm.hexagon.A4.cmpbgt
hexagon_A4_cmpbgti, // llvm.hexagon.A4.cmpbgti
hexagon_A4_cmpbgtu, // llvm.hexagon.A4.cmpbgtu
hexagon_A4_cmpbgtui, // llvm.hexagon.A4.cmpbgtui
hexagon_A4_cmpheq, // llvm.hexagon.A4.cmpheq
hexagon_A4_cmpheqi, // llvm.hexagon.A4.cmpheqi
hexagon_A4_cmphgt, // llvm.hexagon.A4.cmphgt
hexagon_A4_cmphgti, // llvm.hexagon.A4.cmphgti
hexagon_A4_cmphgtu, // llvm.hexagon.A4.cmphgtu
hexagon_A4_cmphgtui, // llvm.hexagon.A4.cmphgtui
hexagon_A4_combineir, // llvm.hexagon.A4.combineir hexagon_A4_combineir, // llvm.hexagon.A4.combineir
hexagon_A4_combineri, // llvm.hexagon.A4.combineri hexagon_A4_combineri, // llvm.hexagon.A4.combineri
hexagon_A4_cround_ri, // llvm.hexagon.A4.cround.ri hexagon_A4_cround_ri, // llvm.hexagon.A4.cround.ri
hexagon_A4_cround_rr, // llvm.hexagon.A4.cround.rr hexagon_A4_cround_rr, // llvm.hexagon.A4.cround.rr
hexagon_A4_modwrapu, // llvm.hexagon.A4.modwrapu hexagon_A4_modwrapu, // llvm.hexagon.A4.modwrapu
hexagon_A4_orn, // llvm.hexagon.A4.orn hexagon_A4_orn, // llvm.hexagon.A4.orn
hexagon_A4_ornp, // llvm.hexagon.A4.ornp hexagon_A4_ornp, // llvm.hexagon.A4.ornp
hexagon_A4_rcmpeq, // llvm.hexagon.A4.rcmpeq hexagon_A4_rcmpeq, // llvm.hexagon.A4.rcmpeq
hexagon_A4_rcmpeqi, // llvm.hexagon.A4.rcmpeqi hexagon_A4_rcmpeqi, // llvm.hexagon.A4.rcmpeqi
hexagon_A4_rcmpneq, // llvm.hexagon.A4.rcmpneq hexagon_A4_rcmpneq, // llvm.hexagon.A4.rcmpneq
hexagon_A4_rcmpneqi, // llvm.hexagon.A4.rcmpneqi hexagon_A4_rcmpneqi, // llvm.hexagon.A4.rcmpneqi
hexagon_A4_round_ri, // llvm.hexagon.A4.round.ri hexagon_A4_round_ri, // llvm.hexagon.A4.round.ri
hexagon_A4_round_ri_sat, // llvm.hexagon.A4.round.ri.s at hexagon_A4_round_ri_sat, // llvm.hexagon.A4.round.ri.s at
hexagon_A4_round_rr, // llvm.hexagon.A4.round.rr hexagon_A4_round_rr, // llvm.hexagon.A4.round.rr
hexagon_A4_round_rr_sat, // llvm.hexagon.A4.round.rr.s at hexagon_A4_round_rr_sat, // llvm.hexagon.A4.round.rr.s at
hexagon_A4_tlbmatch, // llvm.hexagon.A4.tlbmatch
hexagon_A4_vcmpbeq_any, // llvm.hexagon.A4.vcmpbeq.an
y
hexagon_A4_vcmpbeqi, // llvm.hexagon.A4.vcmpbeqi
hexagon_A4_vcmpbgt, // llvm.hexagon.A4.vcmpbgt
hexagon_A4_vcmpbgti, // llvm.hexagon.A4.vcmpbgti
hexagon_A4_vcmpbgtui, // llvm.hexagon.A4.vcmpbgtui
hexagon_A4_vcmpheqi, // llvm.hexagon.A4.vcmpheqi
hexagon_A4_vcmphgti, // llvm.hexagon.A4.vcmphgti
hexagon_A4_vcmphgtui, // llvm.hexagon.A4.vcmphgtui
hexagon_A4_vcmpweqi, // llvm.hexagon.A4.vcmpweqi
hexagon_A4_vcmpwgti, // llvm.hexagon.A4.vcmpwgti
hexagon_A4_vcmpwgtui, // llvm.hexagon.A4.vcmpwgtui
hexagon_A4_vrmaxh, // llvm.hexagon.A4.vrmaxh
hexagon_A4_vrmaxuh, // llvm.hexagon.A4.vrmaxuh
hexagon_A4_vrmaxuw, // llvm.hexagon.A4.vrmaxuw
hexagon_A4_vrmaxw, // llvm.hexagon.A4.vrmaxw
hexagon_A4_vrminh, // llvm.hexagon.A4.vrminh
hexagon_A4_vrminuh, // llvm.hexagon.A4.vrminuh
hexagon_A4_vrminuw, // llvm.hexagon.A4.vrminuw
hexagon_A4_vrminw, // llvm.hexagon.A4.vrminw
hexagon_A5_vaddhubs, // llvm.hexagon.A5.vaddhubs
hexagon_C2_all8, // llvm.hexagon.C2.all8 hexagon_C2_all8, // llvm.hexagon.C2.all8
hexagon_C2_and, // llvm.hexagon.C2.and hexagon_C2_and, // llvm.hexagon.C2.and
hexagon_C2_andn, // llvm.hexagon.C2.andn hexagon_C2_andn, // llvm.hexagon.C2.andn
hexagon_C2_any8, // llvm.hexagon.C2.any8 hexagon_C2_any8, // llvm.hexagon.C2.any8
hexagon_C2_bitsclr, // llvm.hexagon.C2.bitsclr hexagon_C2_bitsclr, // llvm.hexagon.C2.bitsclr
hexagon_C2_bitsclri, // llvm.hexagon.C2.bitsclri hexagon_C2_bitsclri, // llvm.hexagon.C2.bitsclri
hexagon_C2_bitsset, // llvm.hexagon.C2.bitsset hexagon_C2_bitsset, // llvm.hexagon.C2.bitsset
hexagon_C2_cmpeq, // llvm.hexagon.C2.cmpeq hexagon_C2_cmpeq, // llvm.hexagon.C2.cmpeq
hexagon_C2_cmpeqi, // llvm.hexagon.C2.cmpeqi hexagon_C2_cmpeqi, // llvm.hexagon.C2.cmpeqi
hexagon_C2_cmpeqp, // llvm.hexagon.C2.cmpeqp hexagon_C2_cmpeqp, // llvm.hexagon.C2.cmpeqp
skipping to change at line 398 skipping to change at line 442
hexagon_C4_and_or, // llvm.hexagon.C4.and.or hexagon_C4_and_or, // llvm.hexagon.C4.and.or
hexagon_C4_and_orn, // llvm.hexagon.C4.and.orn hexagon_C4_and_orn, // llvm.hexagon.C4.and.orn
hexagon_C4_cmplte, // llvm.hexagon.C4.cmplte hexagon_C4_cmplte, // llvm.hexagon.C4.cmplte
hexagon_C4_cmpltei, // llvm.hexagon.C4.cmpltei hexagon_C4_cmpltei, // llvm.hexagon.C4.cmpltei
hexagon_C4_cmplteu, // llvm.hexagon.C4.cmplteu hexagon_C4_cmplteu, // llvm.hexagon.C4.cmplteu
hexagon_C4_cmplteui, // llvm.hexagon.C4.cmplteui hexagon_C4_cmplteui, // llvm.hexagon.C4.cmplteui
hexagon_C4_cmpneq, // llvm.hexagon.C4.cmpneq hexagon_C4_cmpneq, // llvm.hexagon.C4.cmpneq
hexagon_C4_cmpneqi, // llvm.hexagon.C4.cmpneqi hexagon_C4_cmpneqi, // llvm.hexagon.C4.cmpneqi
hexagon_C4_fastcorner9, // llvm.hexagon.C4.fastcorner 9 hexagon_C4_fastcorner9, // llvm.hexagon.C4.fastcorner 9
hexagon_C4_fastcorner9_not, // llvm.hexagon.C4.fastcorner 9.not hexagon_C4_fastcorner9_not, // llvm.hexagon.C4.fastcorner 9.not
hexagon_C4_nbitsclr, // llvm.hexagon.C4.nbitsclr
hexagon_C4_nbitsclri, // llvm.hexagon.C4.nbitsclri
hexagon_C4_nbitsset, // llvm.hexagon.C4.nbitsset
hexagon_C4_or_and, // llvm.hexagon.C4.or.and hexagon_C4_or_and, // llvm.hexagon.C4.or.and
hexagon_C4_or_andn, // llvm.hexagon.C4.or.andn hexagon_C4_or_andn, // llvm.hexagon.C4.or.andn
hexagon_C4_or_or, // llvm.hexagon.C4.or.or hexagon_C4_or_or, // llvm.hexagon.C4.or.or
hexagon_C4_or_orn, // llvm.hexagon.C4.or.orn hexagon_C4_or_orn, // llvm.hexagon.C4.or.orn
hexagon_F2_conv_d2df, // llvm.hexagon.F2.conv.d2df
hexagon_F2_conv_d2sf, // llvm.hexagon.F2.conv.d2sf
hexagon_F2_conv_df2d, // llvm.hexagon.F2.conv.df2d
hexagon_F2_conv_df2d_chop, // llvm.hexagon.F2.conv.df2d.
chop
hexagon_F2_conv_df2sf, // llvm.hexagon.F2.conv.df2sf
hexagon_F2_conv_df2ud, // llvm.hexagon.F2.conv.df2ud
hexagon_F2_conv_df2ud_chop, // llvm.hexagon.F2.conv.df2ud
.chop
hexagon_F2_conv_df2uw, // llvm.hexagon.F2.conv.df2uw
hexagon_F2_conv_df2uw_chop, // llvm.hexagon.F2.conv.df2uw
.chop
hexagon_F2_conv_df2w, // llvm.hexagon.F2.conv.df2w
hexagon_F2_conv_df2w_chop, // llvm.hexagon.F2.conv.df2w.
chop
hexagon_F2_conv_sf2d, // llvm.hexagon.F2.conv.sf2d
hexagon_F2_conv_sf2d_chop, // llvm.hexagon.F2.conv.sf2d.
chop
hexagon_F2_conv_sf2df, // llvm.hexagon.F2.conv.sf2df
hexagon_F2_conv_sf2ud, // llvm.hexagon.F2.conv.sf2ud
hexagon_F2_conv_sf2ud_chop, // llvm.hexagon.F2.conv.sf2ud
.chop
hexagon_F2_conv_sf2uw, // llvm.hexagon.F2.conv.sf2uw
hexagon_F2_conv_sf2uw_chop, // llvm.hexagon.F2.conv.sf2uw
.chop
hexagon_F2_conv_sf2w, // llvm.hexagon.F2.conv.sf2w
hexagon_F2_conv_sf2w_chop, // llvm.hexagon.F2.conv.sf2w.
chop
hexagon_F2_conv_ud2df, // llvm.hexagon.F2.conv.ud2df
hexagon_F2_conv_ud2sf, // llvm.hexagon.F2.conv.ud2sf
hexagon_F2_conv_uw2df, // llvm.hexagon.F2.conv.uw2df
hexagon_F2_conv_uw2sf, // llvm.hexagon.F2.conv.uw2sf
hexagon_F2_conv_w2df, // llvm.hexagon.F2.conv.w2df
hexagon_F2_conv_w2sf, // llvm.hexagon.F2.conv.w2sf
hexagon_F2_dfadd, // llvm.hexagon.F2.dfadd
hexagon_F2_dfclass, // llvm.hexagon.F2.dfclass
hexagon_F2_dfcmpeq, // llvm.hexagon.F2.dfcmpeq
hexagon_F2_dfcmpge, // llvm.hexagon.F2.dfcmpge
hexagon_F2_dfcmpgt, // llvm.hexagon.F2.dfcmpgt
hexagon_F2_dfcmpuo, // llvm.hexagon.F2.dfcmpuo
hexagon_F2_dffixupd, // llvm.hexagon.F2.dffixupd
hexagon_F2_dffixupn, // llvm.hexagon.F2.dffixupn
hexagon_F2_dffixupr, // llvm.hexagon.F2.dffixupr
hexagon_F2_dffma, // llvm.hexagon.F2.dffma
hexagon_F2_dffma_lib, // llvm.hexagon.F2.dffma.lib
hexagon_F2_dffma_sc, // llvm.hexagon.F2.dffma.sc
hexagon_F2_dffms, // llvm.hexagon.F2.dffms
hexagon_F2_dffms_lib, // llvm.hexagon.F2.dffms.lib
hexagon_F2_dfimm_n, // llvm.hexagon.F2.dfimm.n
hexagon_F2_dfimm_p, // llvm.hexagon.F2.dfimm.p
hexagon_F2_dfmax, // llvm.hexagon.F2.dfmax
hexagon_F2_dfmin, // llvm.hexagon.F2.dfmin
hexagon_F2_dfmpy, // llvm.hexagon.F2.dfmpy
hexagon_F2_dfsub, // llvm.hexagon.F2.dfsub
hexagon_F2_sfadd, // llvm.hexagon.F2.sfadd
hexagon_F2_sfclass, // llvm.hexagon.F2.sfclass
hexagon_F2_sfcmpeq, // llvm.hexagon.F2.sfcmpeq
hexagon_F2_sfcmpge, // llvm.hexagon.F2.sfcmpge
hexagon_F2_sfcmpgt, // llvm.hexagon.F2.sfcmpgt
hexagon_F2_sfcmpuo, // llvm.hexagon.F2.sfcmpuo
hexagon_F2_sffixupd, // llvm.hexagon.F2.sffixupd
hexagon_F2_sffixupn, // llvm.hexagon.F2.sffixupn
hexagon_F2_sffixupr, // llvm.hexagon.F2.sffixupr
hexagon_F2_sffma, // llvm.hexagon.F2.sffma
hexagon_F2_sffma_lib, // llvm.hexagon.F2.sffma.lib
hexagon_F2_sffma_sc, // llvm.hexagon.F2.sffma.sc
hexagon_F2_sffms, // llvm.hexagon.F2.sffms
hexagon_F2_sffms_lib, // llvm.hexagon.F2.sffms.lib
hexagon_F2_sfimm_n, // llvm.hexagon.F2.sfimm.n
hexagon_F2_sfimm_p, // llvm.hexagon.F2.sfimm.p
hexagon_F2_sfmax, // llvm.hexagon.F2.sfmax
hexagon_F2_sfmin, // llvm.hexagon.F2.sfmin
hexagon_F2_sfmpy, // llvm.hexagon.F2.sfmpy
hexagon_F2_sfsub, // llvm.hexagon.F2.sfsub
hexagon_M2_acci, // llvm.hexagon.M2.acci hexagon_M2_acci, // llvm.hexagon.M2.acci
hexagon_M2_accii, // llvm.hexagon.M2.accii hexagon_M2_accii, // llvm.hexagon.M2.accii
hexagon_M2_cmaci_s0, // llvm.hexagon.M2.cmaci.s0 hexagon_M2_cmaci_s0, // llvm.hexagon.M2.cmaci.s0
hexagon_M2_cmacr_s0, // llvm.hexagon.M2.cmacr.s0 hexagon_M2_cmacr_s0, // llvm.hexagon.M2.cmacr.s0
hexagon_M2_cmacs_s0, // llvm.hexagon.M2.cmacs.s0 hexagon_M2_cmacs_s0, // llvm.hexagon.M2.cmacs.s0
hexagon_M2_cmacs_s1, // llvm.hexagon.M2.cmacs.s1 hexagon_M2_cmacs_s1, // llvm.hexagon.M2.cmacs.s1
hexagon_M2_cmacsc_s0, // llvm.hexagon.M2.cmacsc.s0 hexagon_M2_cmacsc_s0, // llvm.hexagon.M2.cmacsc.s0
hexagon_M2_cmacsc_s1, // llvm.hexagon.M2.cmacsc.s1 hexagon_M2_cmacsc_s1, // llvm.hexagon.M2.cmacsc.s1
hexagon_M2_cmpyi_s0, // llvm.hexagon.M2.cmpyi.s0 hexagon_M2_cmpyi_s0, // llvm.hexagon.M2.cmpyi.s0
hexagon_M2_cmpyr_s0, // llvm.hexagon.M2.cmpyr.s0 hexagon_M2_cmpyr_s0, // llvm.hexagon.M2.cmpyr.s0
skipping to change at line 432 skipping to change at line 545
hexagon_M2_cnacsc_s0, // llvm.hexagon.M2.cnacsc.s0 hexagon_M2_cnacsc_s0, // llvm.hexagon.M2.cnacsc.s0
hexagon_M2_cnacsc_s1, // llvm.hexagon.M2.cnacsc.s1 hexagon_M2_cnacsc_s1, // llvm.hexagon.M2.cnacsc.s1
hexagon_M2_dpmpyss_acc_s0, // llvm.hexagon.M2.dpmpyss.ac c.s0 hexagon_M2_dpmpyss_acc_s0, // llvm.hexagon.M2.dpmpyss.ac c.s0
hexagon_M2_dpmpyss_nac_s0, // llvm.hexagon.M2.dpmpyss.na c.s0 hexagon_M2_dpmpyss_nac_s0, // llvm.hexagon.M2.dpmpyss.na c.s0
hexagon_M2_dpmpyss_rnd_s0, // llvm.hexagon.M2.dpmpyss.rn d.s0 hexagon_M2_dpmpyss_rnd_s0, // llvm.hexagon.M2.dpmpyss.rn d.s0
hexagon_M2_dpmpyss_s0, // llvm.hexagon.M2.dpmpyss.s0 hexagon_M2_dpmpyss_s0, // llvm.hexagon.M2.dpmpyss.s0
hexagon_M2_dpmpyuu_acc_s0, // llvm.hexagon.M2.dpmpyuu.ac c.s0 hexagon_M2_dpmpyuu_acc_s0, // llvm.hexagon.M2.dpmpyuu.ac c.s0
hexagon_M2_dpmpyuu_nac_s0, // llvm.hexagon.M2.dpmpyuu.na c.s0 hexagon_M2_dpmpyuu_nac_s0, // llvm.hexagon.M2.dpmpyuu.na c.s0
hexagon_M2_dpmpyuu_s0, // llvm.hexagon.M2.dpmpyuu.s0 hexagon_M2_dpmpyuu_s0, // llvm.hexagon.M2.dpmpyuu.s0
hexagon_M2_hmmpyh_rs1, // llvm.hexagon.M2.hmmpyh.rs1 hexagon_M2_hmmpyh_rs1, // llvm.hexagon.M2.hmmpyh.rs1
hexagon_M2_hmmpyh_s1, // llvm.hexagon.M2.hmmpyh.s1
hexagon_M2_hmmpyl_rs1, // llvm.hexagon.M2.hmmpyl.rs1 hexagon_M2_hmmpyl_rs1, // llvm.hexagon.M2.hmmpyl.rs1
hexagon_M2_hmmpyl_s1, // llvm.hexagon.M2.hmmpyl.s1
hexagon_M2_maci, // llvm.hexagon.M2.maci hexagon_M2_maci, // llvm.hexagon.M2.maci
hexagon_M2_macsin, // llvm.hexagon.M2.macsin hexagon_M2_macsin, // llvm.hexagon.M2.macsin
hexagon_M2_macsip, // llvm.hexagon.M2.macsip hexagon_M2_macsip, // llvm.hexagon.M2.macsip
hexagon_M2_mmachs_rs0, // llvm.hexagon.M2.mmachs.rs0 hexagon_M2_mmachs_rs0, // llvm.hexagon.M2.mmachs.rs0
hexagon_M2_mmachs_rs1, // llvm.hexagon.M2.mmachs.rs1 hexagon_M2_mmachs_rs1, // llvm.hexagon.M2.mmachs.rs1
hexagon_M2_mmachs_s0, // llvm.hexagon.M2.mmachs.s0 hexagon_M2_mmachs_s0, // llvm.hexagon.M2.mmachs.s0
hexagon_M2_mmachs_s1, // llvm.hexagon.M2.mmachs.s1 hexagon_M2_mmachs_s1, // llvm.hexagon.M2.mmachs.s1
hexagon_M2_mmacls_rs0, // llvm.hexagon.M2.mmacls.rs0 hexagon_M2_mmacls_rs0, // llvm.hexagon.M2.mmacls.rs0
hexagon_M2_mmacls_rs1, // llvm.hexagon.M2.mmacls.rs1 hexagon_M2_mmacls_rs1, // llvm.hexagon.M2.mmacls.rs1
hexagon_M2_mmacls_s0, // llvm.hexagon.M2.mmacls.s0 hexagon_M2_mmacls_s0, // llvm.hexagon.M2.mmacls.s0
skipping to change at line 533 skipping to change at line 648
hexagon_M2_mpy_sat_ll_s1, // llvm.hexagon.M2.mpy.sat.ll .s1 hexagon_M2_mpy_sat_ll_s1, // llvm.hexagon.M2.mpy.sat.ll .s1
hexagon_M2_mpy_sat_rnd_hh_s0, // llvm.hexagon.M2.mpy.sat.rn d.hh.s0 hexagon_M2_mpy_sat_rnd_hh_s0, // llvm.hexagon.M2.mpy.sat.rn d.hh.s0
hexagon_M2_mpy_sat_rnd_hh_s1, // llvm.hexagon.M2.mpy.sat.rn d.hh.s1 hexagon_M2_mpy_sat_rnd_hh_s1, // llvm.hexagon.M2.mpy.sat.rn d.hh.s1
hexagon_M2_mpy_sat_rnd_hl_s0, // llvm.hexagon.M2.mpy.sat.rn d.hl.s0 hexagon_M2_mpy_sat_rnd_hl_s0, // llvm.hexagon.M2.mpy.sat.rn d.hl.s0
hexagon_M2_mpy_sat_rnd_hl_s1, // llvm.hexagon.M2.mpy.sat.rn d.hl.s1 hexagon_M2_mpy_sat_rnd_hl_s1, // llvm.hexagon.M2.mpy.sat.rn d.hl.s1
hexagon_M2_mpy_sat_rnd_lh_s0, // llvm.hexagon.M2.mpy.sat.rn d.lh.s0 hexagon_M2_mpy_sat_rnd_lh_s0, // llvm.hexagon.M2.mpy.sat.rn d.lh.s0
hexagon_M2_mpy_sat_rnd_lh_s1, // llvm.hexagon.M2.mpy.sat.rn d.lh.s1 hexagon_M2_mpy_sat_rnd_lh_s1, // llvm.hexagon.M2.mpy.sat.rn d.lh.s1
hexagon_M2_mpy_sat_rnd_ll_s0, // llvm.hexagon.M2.mpy.sat.rn d.ll.s0 hexagon_M2_mpy_sat_rnd_ll_s0, // llvm.hexagon.M2.mpy.sat.rn d.ll.s0
hexagon_M2_mpy_sat_rnd_ll_s1, // llvm.hexagon.M2.mpy.sat.rn d.ll.s1 hexagon_M2_mpy_sat_rnd_ll_s1, // llvm.hexagon.M2.mpy.sat.rn d.ll.s1
hexagon_M2_mpy_up, // llvm.hexagon.M2.mpy.up hexagon_M2_mpy_up, // llvm.hexagon.M2.mpy.up
hexagon_M2_mpy_up_s1, // llvm.hexagon.M2.mpy.up.s1
hexagon_M2_mpy_up_s1_sat, // llvm.hexagon.M2.mpy.up.s1.
sat
hexagon_M2_mpyd_acc_hh_s0, // llvm.hexagon.M2.mpyd.acc.h h.s0 hexagon_M2_mpyd_acc_hh_s0, // llvm.hexagon.M2.mpyd.acc.h h.s0
hexagon_M2_mpyd_acc_hh_s1, // llvm.hexagon.M2.mpyd.acc.h h.s1 hexagon_M2_mpyd_acc_hh_s1, // llvm.hexagon.M2.mpyd.acc.h h.s1
hexagon_M2_mpyd_acc_hl_s0, // llvm.hexagon.M2.mpyd.acc.h l.s0 hexagon_M2_mpyd_acc_hl_s0, // llvm.hexagon.M2.mpyd.acc.h l.s0
hexagon_M2_mpyd_acc_hl_s1, // llvm.hexagon.M2.mpyd.acc.h l.s1 hexagon_M2_mpyd_acc_hl_s1, // llvm.hexagon.M2.mpyd.acc.h l.s1
hexagon_M2_mpyd_acc_lh_s0, // llvm.hexagon.M2.mpyd.acc.l h.s0 hexagon_M2_mpyd_acc_lh_s0, // llvm.hexagon.M2.mpyd.acc.l h.s0
hexagon_M2_mpyd_acc_lh_s1, // llvm.hexagon.M2.mpyd.acc.l h.s1 hexagon_M2_mpyd_acc_lh_s1, // llvm.hexagon.M2.mpyd.acc.l h.s1
hexagon_M2_mpyd_acc_ll_s0, // llvm.hexagon.M2.mpyd.acc.l l.s0 hexagon_M2_mpyd_acc_ll_s0, // llvm.hexagon.M2.mpyd.acc.l l.s0
hexagon_M2_mpyd_acc_ll_s1, // llvm.hexagon.M2.mpyd.acc.l l.s1 hexagon_M2_mpyd_acc_ll_s1, // llvm.hexagon.M2.mpyd.acc.l l.s1
hexagon_M2_mpyd_hh_s0, // llvm.hexagon.M2.mpyd.hh.s0 hexagon_M2_mpyd_hh_s0, // llvm.hexagon.M2.mpyd.hh.s0
hexagon_M2_mpyd_hh_s1, // llvm.hexagon.M2.mpyd.hh.s1 hexagon_M2_mpyd_hh_s1, // llvm.hexagon.M2.mpyd.hh.s1
skipping to change at line 567 skipping to change at line 684
hexagon_M2_mpyd_rnd_hh_s0, // llvm.hexagon.M2.mpyd.rnd.h h.s0 hexagon_M2_mpyd_rnd_hh_s0, // llvm.hexagon.M2.mpyd.rnd.h h.s0
hexagon_M2_mpyd_rnd_hh_s1, // llvm.hexagon.M2.mpyd.rnd.h h.s1 hexagon_M2_mpyd_rnd_hh_s1, // llvm.hexagon.M2.mpyd.rnd.h h.s1
hexagon_M2_mpyd_rnd_hl_s0, // llvm.hexagon.M2.mpyd.rnd.h l.s0 hexagon_M2_mpyd_rnd_hl_s0, // llvm.hexagon.M2.mpyd.rnd.h l.s0
hexagon_M2_mpyd_rnd_hl_s1, // llvm.hexagon.M2.mpyd.rnd.h l.s1 hexagon_M2_mpyd_rnd_hl_s1, // llvm.hexagon.M2.mpyd.rnd.h l.s1
hexagon_M2_mpyd_rnd_lh_s0, // llvm.hexagon.M2.mpyd.rnd.l h.s0 hexagon_M2_mpyd_rnd_lh_s0, // llvm.hexagon.M2.mpyd.rnd.l h.s0
hexagon_M2_mpyd_rnd_lh_s1, // llvm.hexagon.M2.mpyd.rnd.l h.s1 hexagon_M2_mpyd_rnd_lh_s1, // llvm.hexagon.M2.mpyd.rnd.l h.s1
hexagon_M2_mpyd_rnd_ll_s0, // llvm.hexagon.M2.mpyd.rnd.l l.s0 hexagon_M2_mpyd_rnd_ll_s0, // llvm.hexagon.M2.mpyd.rnd.l l.s0
hexagon_M2_mpyd_rnd_ll_s1, // llvm.hexagon.M2.mpyd.rnd.l l.s1 hexagon_M2_mpyd_rnd_ll_s1, // llvm.hexagon.M2.mpyd.rnd.l l.s1
hexagon_M2_mpyi, // llvm.hexagon.M2.mpyi hexagon_M2_mpyi, // llvm.hexagon.M2.mpyi
hexagon_M2_mpysmi, // llvm.hexagon.M2.mpysmi hexagon_M2_mpysmi, // llvm.hexagon.M2.mpysmi
hexagon_M2_mpysu_up, // llvm.hexagon.M2.mpysu.up
hexagon_M2_mpyu_acc_hh_s0, // llvm.hexagon.M2.mpyu.acc.h h.s0 hexagon_M2_mpyu_acc_hh_s0, // llvm.hexagon.M2.mpyu.acc.h h.s0
hexagon_M2_mpyu_acc_hh_s1, // llvm.hexagon.M2.mpyu.acc.h h.s1 hexagon_M2_mpyu_acc_hh_s1, // llvm.hexagon.M2.mpyu.acc.h h.s1
hexagon_M2_mpyu_acc_hl_s0, // llvm.hexagon.M2.mpyu.acc.h l.s0 hexagon_M2_mpyu_acc_hl_s0, // llvm.hexagon.M2.mpyu.acc.h l.s0
hexagon_M2_mpyu_acc_hl_s1, // llvm.hexagon.M2.mpyu.acc.h l.s1 hexagon_M2_mpyu_acc_hl_s1, // llvm.hexagon.M2.mpyu.acc.h l.s1
hexagon_M2_mpyu_acc_lh_s0, // llvm.hexagon.M2.mpyu.acc.l h.s0 hexagon_M2_mpyu_acc_lh_s0, // llvm.hexagon.M2.mpyu.acc.l h.s0
hexagon_M2_mpyu_acc_lh_s1, // llvm.hexagon.M2.mpyu.acc.l h.s1 hexagon_M2_mpyu_acc_lh_s1, // llvm.hexagon.M2.mpyu.acc.l h.s1
hexagon_M2_mpyu_acc_ll_s0, // llvm.hexagon.M2.mpyu.acc.l l.s0 hexagon_M2_mpyu_acc_ll_s0, // llvm.hexagon.M2.mpyu.acc.l l.s0
hexagon_M2_mpyu_acc_ll_s1, // llvm.hexagon.M2.mpyu.acc.l l.s1 hexagon_M2_mpyu_acc_ll_s1, // llvm.hexagon.M2.mpyu.acc.l l.s1
hexagon_M2_mpyu_hh_s0, // llvm.hexagon.M2.mpyu.hh.s0 hexagon_M2_mpyu_hh_s0, // llvm.hexagon.M2.mpyu.hh.s0
hexagon_M2_mpyu_hh_s1, // llvm.hexagon.M2.mpyu.hh.s1 hexagon_M2_mpyu_hh_s1, // llvm.hexagon.M2.mpyu.hh.s1
skipping to change at line 640 skipping to change at line 758
hexagon_M2_vdmpyrs_s0, // llvm.hexagon.M2.vdmpyrs.s0 hexagon_M2_vdmpyrs_s0, // llvm.hexagon.M2.vdmpyrs.s0
hexagon_M2_vdmpyrs_s1, // llvm.hexagon.M2.vdmpyrs.s1 hexagon_M2_vdmpyrs_s1, // llvm.hexagon.M2.vdmpyrs.s1
hexagon_M2_vdmpys_s0, // llvm.hexagon.M2.vdmpys.s0 hexagon_M2_vdmpys_s0, // llvm.hexagon.M2.vdmpys.s0
hexagon_M2_vdmpys_s1, // llvm.hexagon.M2.vdmpys.s1 hexagon_M2_vdmpys_s1, // llvm.hexagon.M2.vdmpys.s1
hexagon_M2_vmac2, // llvm.hexagon.M2.vmac2 hexagon_M2_vmac2, // llvm.hexagon.M2.vmac2
hexagon_M2_vmac2es, // llvm.hexagon.M2.vmac2es hexagon_M2_vmac2es, // llvm.hexagon.M2.vmac2es
hexagon_M2_vmac2es_s0, // llvm.hexagon.M2.vmac2es.s0 hexagon_M2_vmac2es_s0, // llvm.hexagon.M2.vmac2es.s0
hexagon_M2_vmac2es_s1, // llvm.hexagon.M2.vmac2es.s1 hexagon_M2_vmac2es_s1, // llvm.hexagon.M2.vmac2es.s1
hexagon_M2_vmac2s_s0, // llvm.hexagon.M2.vmac2s.s0 hexagon_M2_vmac2s_s0, // llvm.hexagon.M2.vmac2s.s0
hexagon_M2_vmac2s_s1, // llvm.hexagon.M2.vmac2s.s1 hexagon_M2_vmac2s_s1, // llvm.hexagon.M2.vmac2s.s1
hexagon_M2_vmac2su_s0, // llvm.hexagon.M2.vmac2su.s0
hexagon_M2_vmac2su_s1, // llvm.hexagon.M2.vmac2su.s1
hexagon_M2_vmpy2es_s0, // llvm.hexagon.M2.vmpy2es.s0 hexagon_M2_vmpy2es_s0, // llvm.hexagon.M2.vmpy2es.s0
hexagon_M2_vmpy2es_s1, // llvm.hexagon.M2.vmpy2es.s1 hexagon_M2_vmpy2es_s1, // llvm.hexagon.M2.vmpy2es.s1
hexagon_M2_vmpy2s_s0, // llvm.hexagon.M2.vmpy2s.s0 hexagon_M2_vmpy2s_s0, // llvm.hexagon.M2.vmpy2s.s0
hexagon_M2_vmpy2s_s0pack, // llvm.hexagon.M2.vmpy2s.s0p ack hexagon_M2_vmpy2s_s0pack, // llvm.hexagon.M2.vmpy2s.s0p ack
hexagon_M2_vmpy2s_s1, // llvm.hexagon.M2.vmpy2s.s1 hexagon_M2_vmpy2s_s1, // llvm.hexagon.M2.vmpy2s.s1
hexagon_M2_vmpy2s_s1pack, // llvm.hexagon.M2.vmpy2s.s1p ack hexagon_M2_vmpy2s_s1pack, // llvm.hexagon.M2.vmpy2s.s1p ack
hexagon_M2_vmpy2su_s0, // llvm.hexagon.M2.vmpy2su.s0
hexagon_M2_vmpy2su_s1, // llvm.hexagon.M2.vmpy2su.s1
hexagon_M2_vraddh, // llvm.hexagon.M2.vraddh
hexagon_M2_vradduh, // llvm.hexagon.M2.vradduh hexagon_M2_vradduh, // llvm.hexagon.M2.vradduh
hexagon_M2_vrcmaci_s0, // llvm.hexagon.M2.vrcmaci.s0 hexagon_M2_vrcmaci_s0, // llvm.hexagon.M2.vrcmaci.s0
hexagon_M2_vrcmaci_s0c, // llvm.hexagon.M2.vrcmaci.s0 c hexagon_M2_vrcmaci_s0c, // llvm.hexagon.M2.vrcmaci.s0 c
hexagon_M2_vrcmacr_s0, // llvm.hexagon.M2.vrcmacr.s0 hexagon_M2_vrcmacr_s0, // llvm.hexagon.M2.vrcmacr.s0
hexagon_M2_vrcmacr_s0c, // llvm.hexagon.M2.vrcmacr.s0 c hexagon_M2_vrcmacr_s0c, // llvm.hexagon.M2.vrcmacr.s0 c
hexagon_M2_vrcmpyi_s0, // llvm.hexagon.M2.vrcmpyi.s0 hexagon_M2_vrcmpyi_s0, // llvm.hexagon.M2.vrcmpyi.s0
hexagon_M2_vrcmpyi_s0c, // llvm.hexagon.M2.vrcmpyi.s0 c hexagon_M2_vrcmpyi_s0c, // llvm.hexagon.M2.vrcmpyi.s0 c
hexagon_M2_vrcmpyr_s0, // llvm.hexagon.M2.vrcmpyr.s0 hexagon_M2_vrcmpyr_s0, // llvm.hexagon.M2.vrcmpyr.s0
hexagon_M2_vrcmpyr_s0c, // llvm.hexagon.M2.vrcmpyr.s0 c hexagon_M2_vrcmpyr_s0c, // llvm.hexagon.M2.vrcmpyr.s0 c
hexagon_M2_vrcmpys_acc_s1, // llvm.hexagon.M2.vrcmpys.ac c.s1 hexagon_M2_vrcmpys_acc_s1, // llvm.hexagon.M2.vrcmpys.ac c.s1
hexagon_M2_vrcmpys_s1, // llvm.hexagon.M2.vrcmpys.s1 hexagon_M2_vrcmpys_s1, // llvm.hexagon.M2.vrcmpys.s1
hexagon_M2_vrcmpys_s1rp, // llvm.hexagon.M2.vrcmpys.s1 rp hexagon_M2_vrcmpys_s1rp, // llvm.hexagon.M2.vrcmpys.s1 rp
hexagon_M2_vrmac_s0, // llvm.hexagon.M2.vrmac.s0 hexagon_M2_vrmac_s0, // llvm.hexagon.M2.vrmac.s0
hexagon_M2_vrmpy_s0, // llvm.hexagon.M2.vrmpy.s0 hexagon_M2_vrmpy_s0, // llvm.hexagon.M2.vrmpy.s0
hexagon_M2_xor_xacc, // llvm.hexagon.M2.xor.xacc hexagon_M2_xor_xacc, // llvm.hexagon.M2.xor.xacc
hexagon_M4_and_and, // llvm.hexagon.M4.and.and hexagon_M4_and_and, // llvm.hexagon.M4.and.and
hexagon_M4_and_andn, // llvm.hexagon.M4.and.andn hexagon_M4_and_andn, // llvm.hexagon.M4.and.andn
hexagon_M4_and_or, // llvm.hexagon.M4.and.or hexagon_M4_and_or, // llvm.hexagon.M4.and.or
hexagon_M4_and_xor, // llvm.hexagon.M4.and.xor hexagon_M4_and_xor, // llvm.hexagon.M4.and.xor
hexagon_M4_cmpyi_wh, // llvm.hexagon.M4.cmpyi.wh
hexagon_M4_cmpyi_whc, // llvm.hexagon.M4.cmpyi.whc
hexagon_M4_cmpyr_wh, // llvm.hexagon.M4.cmpyr.wh
hexagon_M4_cmpyr_whc, // llvm.hexagon.M4.cmpyr.whc
hexagon_M4_mac_up_s1_sat, // llvm.hexagon.M4.mac.up.s1.
sat
hexagon_M4_mpyri_addi, // llvm.hexagon.M4.mpyri.addi
hexagon_M4_mpyri_addr, // llvm.hexagon.M4.mpyri.addr
hexagon_M4_mpyri_addr_u2, // llvm.hexagon.M4.mpyri.addr
.u2
hexagon_M4_mpyrr_addi, // llvm.hexagon.M4.mpyrr.addi
hexagon_M4_mpyrr_addr, // llvm.hexagon.M4.mpyrr.addr
hexagon_M4_nac_up_s1_sat, // llvm.hexagon.M4.nac.up.s1.
sat
hexagon_M4_or_and, // llvm.hexagon.M4.or.and hexagon_M4_or_and, // llvm.hexagon.M4.or.and
hexagon_M4_or_andn, // llvm.hexagon.M4.or.andn hexagon_M4_or_andn, // llvm.hexagon.M4.or.andn
hexagon_M4_or_or, // llvm.hexagon.M4.or.or hexagon_M4_or_or, // llvm.hexagon.M4.or.or
hexagon_M4_or_xor, // llvm.hexagon.M4.or.xor hexagon_M4_or_xor, // llvm.hexagon.M4.or.xor
hexagon_M4_pmpyw, // llvm.hexagon.M4.pmpyw
hexagon_M4_pmpyw_acc, // llvm.hexagon.M4.pmpyw.acc
hexagon_M4_vpmpyh, // llvm.hexagon.M4.vpmpyh
hexagon_M4_vpmpyh_acc, // llvm.hexagon.M4.vpmpyh.acc
hexagon_M4_vrmpyeh_acc_s0, // llvm.hexagon.M4.vrmpyeh.ac
c.s0
hexagon_M4_vrmpyeh_acc_s1, // llvm.hexagon.M4.vrmpyeh.ac
c.s1
hexagon_M4_vrmpyeh_s0, // llvm.hexagon.M4.vrmpyeh.s0
hexagon_M4_vrmpyeh_s1, // llvm.hexagon.M4.vrmpyeh.s1
hexagon_M4_vrmpyoh_acc_s0, // llvm.hexagon.M4.vrmpyoh.ac
c.s0
hexagon_M4_vrmpyoh_acc_s1, // llvm.hexagon.M4.vrmpyoh.ac
c.s1
hexagon_M4_vrmpyoh_s0, // llvm.hexagon.M4.vrmpyoh.s0
hexagon_M4_vrmpyoh_s1, // llvm.hexagon.M4.vrmpyoh.s1
hexagon_M4_xor_and, // llvm.hexagon.M4.xor.and hexagon_M4_xor_and, // llvm.hexagon.M4.xor.and
hexagon_M4_xor_andn, // llvm.hexagon.M4.xor.andn hexagon_M4_xor_andn, // llvm.hexagon.M4.xor.andn
hexagon_M4_xor_or, // llvm.hexagon.M4.xor.or hexagon_M4_xor_or, // llvm.hexagon.M4.xor.or
hexagon_M4_xor_xacc, // llvm.hexagon.M4.xor.xacc hexagon_M4_xor_xacc, // llvm.hexagon.M4.xor.xacc
hexagon_M5_vdmacbsu, // llvm.hexagon.M5.vdmacbsu
hexagon_M5_vdmpybsu, // llvm.hexagon.M5.vdmpybsu
hexagon_M5_vmacbsu, // llvm.hexagon.M5.vmacbsu
hexagon_M5_vmacbuu, // llvm.hexagon.M5.vmacbuu
hexagon_M5_vmpybsu, // llvm.hexagon.M5.vmpybsu
hexagon_M5_vmpybuu, // llvm.hexagon.M5.vmpybuu
hexagon_M5_vrmacbsu, // llvm.hexagon.M5.vrmacbsu
hexagon_M5_vrmacbuu, // llvm.hexagon.M5.vrmacbuu
hexagon_M5_vrmpybsu, // llvm.hexagon.M5.vrmpybsu
hexagon_M5_vrmpybuu, // llvm.hexagon.M5.vrmpybuu
hexagon_S2_addasl_rrri, // llvm.hexagon.S2.addasl.rrr i hexagon_S2_addasl_rrri, // llvm.hexagon.S2.addasl.rrr i
hexagon_S2_asl_i_p, // llvm.hexagon.S2.asl.i.p hexagon_S2_asl_i_p, // llvm.hexagon.S2.asl.i.p
hexagon_S2_asl_i_p_acc, // llvm.hexagon.S2.asl.i.p.ac c hexagon_S2_asl_i_p_acc, // llvm.hexagon.S2.asl.i.p.ac c
hexagon_S2_asl_i_p_and, // llvm.hexagon.S2.asl.i.p.an d hexagon_S2_asl_i_p_and, // llvm.hexagon.S2.asl.i.p.an d
hexagon_S2_asl_i_p_nac, // llvm.hexagon.S2.asl.i.p.na c hexagon_S2_asl_i_p_nac, // llvm.hexagon.S2.asl.i.p.na c
hexagon_S2_asl_i_p_or, // llvm.hexagon.S2.asl.i.p.or hexagon_S2_asl_i_p_or, // llvm.hexagon.S2.asl.i.p.or
hexagon_S2_asl_i_p_xacc, // llvm.hexagon.S2.asl.i.p.xa cc hexagon_S2_asl_i_p_xacc, // llvm.hexagon.S2.asl.i.p.xa cc
hexagon_S2_asl_i_r, // llvm.hexagon.S2.asl.i.r hexagon_S2_asl_i_r, // llvm.hexagon.S2.asl.i.r
hexagon_S2_asl_i_r_acc, // llvm.hexagon.S2.asl.i.r.ac c hexagon_S2_asl_i_r_acc, // llvm.hexagon.S2.asl.i.r.ac c
hexagon_S2_asl_i_r_and, // llvm.hexagon.S2.asl.i.r.an d hexagon_S2_asl_i_r_and, // llvm.hexagon.S2.asl.i.r.an d
skipping to change at line 694 skipping to change at line 850
hexagon_S2_asl_i_r_or, // llvm.hexagon.S2.asl.i.r.or hexagon_S2_asl_i_r_or, // llvm.hexagon.S2.asl.i.r.or
hexagon_S2_asl_i_r_sat, // llvm.hexagon.S2.asl.i.r.sa t hexagon_S2_asl_i_r_sat, // llvm.hexagon.S2.asl.i.r.sa t
hexagon_S2_asl_i_r_xacc, // llvm.hexagon.S2.asl.i.r.xa cc hexagon_S2_asl_i_r_xacc, // llvm.hexagon.S2.asl.i.r.xa cc
hexagon_S2_asl_i_vh, // llvm.hexagon.S2.asl.i.vh hexagon_S2_asl_i_vh, // llvm.hexagon.S2.asl.i.vh
hexagon_S2_asl_i_vw, // llvm.hexagon.S2.asl.i.vw hexagon_S2_asl_i_vw, // llvm.hexagon.S2.asl.i.vw
hexagon_S2_asl_r_p, // llvm.hexagon.S2.asl.r.p hexagon_S2_asl_r_p, // llvm.hexagon.S2.asl.r.p
hexagon_S2_asl_r_p_acc, // llvm.hexagon.S2.asl.r.p.ac c hexagon_S2_asl_r_p_acc, // llvm.hexagon.S2.asl.r.p.ac c
hexagon_S2_asl_r_p_and, // llvm.hexagon.S2.asl.r.p.an d hexagon_S2_asl_r_p_and, // llvm.hexagon.S2.asl.r.p.an d
hexagon_S2_asl_r_p_nac, // llvm.hexagon.S2.asl.r.p.na c hexagon_S2_asl_r_p_nac, // llvm.hexagon.S2.asl.r.p.na c
hexagon_S2_asl_r_p_or, // llvm.hexagon.S2.asl.r.p.or hexagon_S2_asl_r_p_or, // llvm.hexagon.S2.asl.r.p.or
hexagon_S2_asl_r_p_xor, // llvm.hexagon.S2.asl.r.p.xo r
hexagon_S2_asl_r_r, // llvm.hexagon.S2.asl.r.r hexagon_S2_asl_r_r, // llvm.hexagon.S2.asl.r.r
hexagon_S2_asl_r_r_acc, // llvm.hexagon.S2.asl.r.r.ac c hexagon_S2_asl_r_r_acc, // llvm.hexagon.S2.asl.r.r.ac c
hexagon_S2_asl_r_r_and, // llvm.hexagon.S2.asl.r.r.an d hexagon_S2_asl_r_r_and, // llvm.hexagon.S2.asl.r.r.an d
hexagon_S2_asl_r_r_nac, // llvm.hexagon.S2.asl.r.r.na c hexagon_S2_asl_r_r_nac, // llvm.hexagon.S2.asl.r.r.na c
hexagon_S2_asl_r_r_or, // llvm.hexagon.S2.asl.r.r.or hexagon_S2_asl_r_r_or, // llvm.hexagon.S2.asl.r.r.or
hexagon_S2_asl_r_r_sat, // llvm.hexagon.S2.asl.r.r.sa t hexagon_S2_asl_r_r_sat, // llvm.hexagon.S2.asl.r.r.sa t
hexagon_S2_asl_r_vh, // llvm.hexagon.S2.asl.r.vh hexagon_S2_asl_r_vh, // llvm.hexagon.S2.asl.r.vh
hexagon_S2_asl_r_vw, // llvm.hexagon.S2.asl.r.vw hexagon_S2_asl_r_vw, // llvm.hexagon.S2.asl.r.vw
hexagon_S2_asr_i_p, // llvm.hexagon.S2.asr.i.p hexagon_S2_asr_i_p, // llvm.hexagon.S2.asr.i.p
hexagon_S2_asr_i_p_acc, // llvm.hexagon.S2.asr.i.p.ac c hexagon_S2_asr_i_p_acc, // llvm.hexagon.S2.asr.i.p.ac c
hexagon_S2_asr_i_p_and, // llvm.hexagon.S2.asr.i.p.an d hexagon_S2_asr_i_p_and, // llvm.hexagon.S2.asr.i.p.an d
hexagon_S2_asr_i_p_nac, // llvm.hexagon.S2.asr.i.p.na c hexagon_S2_asr_i_p_nac, // llvm.hexagon.S2.asr.i.p.na c
hexagon_S2_asr_i_p_or, // llvm.hexagon.S2.asr.i.p.or hexagon_S2_asr_i_p_or, // llvm.hexagon.S2.asr.i.p.or
hexagon_S2_asr_i_p_rnd, // llvm.hexagon.S2.asr.i.p.rn
d
hexagon_S2_asr_i_p_rnd_goodsyntax, // llvm.hexagon.S2.asr.i.p.rn
d.goodsyntax
hexagon_S2_asr_i_r, // llvm.hexagon.S2.asr.i.r hexagon_S2_asr_i_r, // llvm.hexagon.S2.asr.i.r
hexagon_S2_asr_i_r_acc, // llvm.hexagon.S2.asr.i.r.ac c hexagon_S2_asr_i_r_acc, // llvm.hexagon.S2.asr.i.r.ac c
hexagon_S2_asr_i_r_and, // llvm.hexagon.S2.asr.i.r.an d hexagon_S2_asr_i_r_and, // llvm.hexagon.S2.asr.i.r.an d
hexagon_S2_asr_i_r_nac, // llvm.hexagon.S2.asr.i.r.na c hexagon_S2_asr_i_r_nac, // llvm.hexagon.S2.asr.i.r.na c
hexagon_S2_asr_i_r_or, // llvm.hexagon.S2.asr.i.r.or hexagon_S2_asr_i_r_or, // llvm.hexagon.S2.asr.i.r.or
hexagon_S2_asr_i_r_rnd, // llvm.hexagon.S2.asr.i.r.rn d hexagon_S2_asr_i_r_rnd, // llvm.hexagon.S2.asr.i.r.rn d
hexagon_S2_asr_i_r_rnd_goodsyntax, // llvm.hexagon.S2.asr.i.r.rn d.goodsyntax hexagon_S2_asr_i_r_rnd_goodsyntax, // llvm.hexagon.S2.asr.i.r.rn d.goodsyntax
hexagon_S2_asr_i_svw_trun, // llvm.hexagon.S2.asr.i.svw. trun hexagon_S2_asr_i_svw_trun, // llvm.hexagon.S2.asr.i.svw. trun
hexagon_S2_asr_i_vh, // llvm.hexagon.S2.asr.i.vh hexagon_S2_asr_i_vh, // llvm.hexagon.S2.asr.i.vh
hexagon_S2_asr_i_vw, // llvm.hexagon.S2.asr.i.vw hexagon_S2_asr_i_vw, // llvm.hexagon.S2.asr.i.vw
hexagon_S2_asr_r_p, // llvm.hexagon.S2.asr.r.p hexagon_S2_asr_r_p, // llvm.hexagon.S2.asr.r.p
hexagon_S2_asr_r_p_acc, // llvm.hexagon.S2.asr.r.p.ac c hexagon_S2_asr_r_p_acc, // llvm.hexagon.S2.asr.r.p.ac c
hexagon_S2_asr_r_p_and, // llvm.hexagon.S2.asr.r.p.an d hexagon_S2_asr_r_p_and, // llvm.hexagon.S2.asr.r.p.an d
hexagon_S2_asr_r_p_nac, // llvm.hexagon.S2.asr.r.p.na c hexagon_S2_asr_r_p_nac, // llvm.hexagon.S2.asr.r.p.na c
hexagon_S2_asr_r_p_or, // llvm.hexagon.S2.asr.r.p.or hexagon_S2_asr_r_p_or, // llvm.hexagon.S2.asr.r.p.or
hexagon_S2_asr_r_p_xor, // llvm.hexagon.S2.asr.r.p.xo r
hexagon_S2_asr_r_r, // llvm.hexagon.S2.asr.r.r hexagon_S2_asr_r_r, // llvm.hexagon.S2.asr.r.r
hexagon_S2_asr_r_r_acc, // llvm.hexagon.S2.asr.r.r.ac c hexagon_S2_asr_r_r_acc, // llvm.hexagon.S2.asr.r.r.ac c
hexagon_S2_asr_r_r_and, // llvm.hexagon.S2.asr.r.r.an d hexagon_S2_asr_r_r_and, // llvm.hexagon.S2.asr.r.r.an d
hexagon_S2_asr_r_r_nac, // llvm.hexagon.S2.asr.r.r.na c hexagon_S2_asr_r_r_nac, // llvm.hexagon.S2.asr.r.r.na c
hexagon_S2_asr_r_r_or, // llvm.hexagon.S2.asr.r.r.or hexagon_S2_asr_r_r_or, // llvm.hexagon.S2.asr.r.r.or
hexagon_S2_asr_r_r_sat, // llvm.hexagon.S2.asr.r.r.sa t hexagon_S2_asr_r_r_sat, // llvm.hexagon.S2.asr.r.r.sa t
hexagon_S2_asr_r_svw_trun, // llvm.hexagon.S2.asr.r.svw. trun hexagon_S2_asr_r_svw_trun, // llvm.hexagon.S2.asr.r.svw. trun
hexagon_S2_asr_r_vh, // llvm.hexagon.S2.asr.r.vh hexagon_S2_asr_r_vh, // llvm.hexagon.S2.asr.r.vh
hexagon_S2_asr_r_vw, // llvm.hexagon.S2.asr.r.vw hexagon_S2_asr_r_vw, // llvm.hexagon.S2.asr.r.vw
hexagon_S2_brev, // llvm.hexagon.S2.brev hexagon_S2_brev, // llvm.hexagon.S2.brev
hexagon_S2_brevp, // llvm.hexagon.S2.brevp
hexagon_S2_cl0, // llvm.hexagon.S2.cl0 hexagon_S2_cl0, // llvm.hexagon.S2.cl0
hexagon_S2_cl0p, // llvm.hexagon.S2.cl0p hexagon_S2_cl0p, // llvm.hexagon.S2.cl0p
hexagon_S2_cl1, // llvm.hexagon.S2.cl1 hexagon_S2_cl1, // llvm.hexagon.S2.cl1
hexagon_S2_cl1p, // llvm.hexagon.S2.cl1p hexagon_S2_cl1p, // llvm.hexagon.S2.cl1p
hexagon_S2_clb, // llvm.hexagon.S2.clb hexagon_S2_clb, // llvm.hexagon.S2.clb
hexagon_S2_clbnorm, // llvm.hexagon.S2.clbnorm hexagon_S2_clbnorm, // llvm.hexagon.S2.clbnorm
hexagon_S2_clbp, // llvm.hexagon.S2.clbp hexagon_S2_clbp, // llvm.hexagon.S2.clbp
hexagon_S2_clrbit_i, // llvm.hexagon.S2.clrbit.i hexagon_S2_clrbit_i, // llvm.hexagon.S2.clrbit.i
hexagon_S2_clrbit_r, // llvm.hexagon.S2.clrbit.r hexagon_S2_clrbit_r, // llvm.hexagon.S2.clrbit.r
hexagon_S2_ct0, // llvm.hexagon.S2.ct0 hexagon_S2_ct0, // llvm.hexagon.S2.ct0
hexagon_S2_ct0p, // llvm.hexagon.S2.ct0p
hexagon_S2_ct1, // llvm.hexagon.S2.ct1 hexagon_S2_ct1, // llvm.hexagon.S2.ct1
hexagon_S2_ct1p, // llvm.hexagon.S2.ct1p
hexagon_S2_deinterleave, // llvm.hexagon.S2.deinterlea ve hexagon_S2_deinterleave, // llvm.hexagon.S2.deinterlea ve
hexagon_S2_extractu, // llvm.hexagon.S2.extractu hexagon_S2_extractu, // llvm.hexagon.S2.extractu
hexagon_S2_extractu_rp, // llvm.hexagon.S2.extractu.r p hexagon_S2_extractu_rp, // llvm.hexagon.S2.extractu.r p
hexagon_S2_extractup, // llvm.hexagon.S2.extractup hexagon_S2_extractup, // llvm.hexagon.S2.extractup
hexagon_S2_extractup_rp, // llvm.hexagon.S2.extractup. rp hexagon_S2_extractup_rp, // llvm.hexagon.S2.extractup. rp
hexagon_S2_insert, // llvm.hexagon.S2.insert hexagon_S2_insert, // llvm.hexagon.S2.insert
hexagon_S2_insert_rp, // llvm.hexagon.S2.insert.rp hexagon_S2_insert_rp, // llvm.hexagon.S2.insert.rp
hexagon_S2_insertp, // llvm.hexagon.S2.insertp hexagon_S2_insertp, // llvm.hexagon.S2.insertp
hexagon_S2_insertp_rp, // llvm.hexagon.S2.insertp.rp hexagon_S2_insertp_rp, // llvm.hexagon.S2.insertp.rp
hexagon_S2_interleave, // llvm.hexagon.S2.interleave hexagon_S2_interleave, // llvm.hexagon.S2.interleave
hexagon_S2_lfsp, // llvm.hexagon.S2.lfsp hexagon_S2_lfsp, // llvm.hexagon.S2.lfsp
hexagon_S2_lsl_r_p, // llvm.hexagon.S2.lsl.r.p hexagon_S2_lsl_r_p, // llvm.hexagon.S2.lsl.r.p
hexagon_S2_lsl_r_p_acc, // llvm.hexagon.S2.lsl.r.p.ac c hexagon_S2_lsl_r_p_acc, // llvm.hexagon.S2.lsl.r.p.ac c
hexagon_S2_lsl_r_p_and, // llvm.hexagon.S2.lsl.r.p.an d hexagon_S2_lsl_r_p_and, // llvm.hexagon.S2.lsl.r.p.an d
hexagon_S2_lsl_r_p_nac, // llvm.hexagon.S2.lsl.r.p.na c hexagon_S2_lsl_r_p_nac, // llvm.hexagon.S2.lsl.r.p.na c
hexagon_S2_lsl_r_p_or, // llvm.hexagon.S2.lsl.r.p.or hexagon_S2_lsl_r_p_or, // llvm.hexagon.S2.lsl.r.p.or
hexagon_S2_lsl_r_p_xor, // llvm.hexagon.S2.lsl.r.p.xo r
hexagon_S2_lsl_r_r, // llvm.hexagon.S2.lsl.r.r hexagon_S2_lsl_r_r, // llvm.hexagon.S2.lsl.r.r
hexagon_S2_lsl_r_r_acc, // llvm.hexagon.S2.lsl.r.r.ac c hexagon_S2_lsl_r_r_acc, // llvm.hexagon.S2.lsl.r.r.ac c
hexagon_S2_lsl_r_r_and, // llvm.hexagon.S2.lsl.r.r.an d hexagon_S2_lsl_r_r_and, // llvm.hexagon.S2.lsl.r.r.an d
hexagon_S2_lsl_r_r_nac, // llvm.hexagon.S2.lsl.r.r.na c hexagon_S2_lsl_r_r_nac, // llvm.hexagon.S2.lsl.r.r.na c
hexagon_S2_lsl_r_r_or, // llvm.hexagon.S2.lsl.r.r.or hexagon_S2_lsl_r_r_or, // llvm.hexagon.S2.lsl.r.r.or
hexagon_S2_lsl_r_vh, // llvm.hexagon.S2.lsl.r.vh hexagon_S2_lsl_r_vh, // llvm.hexagon.S2.lsl.r.vh
hexagon_S2_lsl_r_vw, // llvm.hexagon.S2.lsl.r.vw hexagon_S2_lsl_r_vw, // llvm.hexagon.S2.lsl.r.vw
hexagon_S2_lsr_i_p, // llvm.hexagon.S2.lsr.i.p hexagon_S2_lsr_i_p, // llvm.hexagon.S2.lsr.i.p
hexagon_S2_lsr_i_p_acc, // llvm.hexagon.S2.lsr.i.p.ac c hexagon_S2_lsr_i_p_acc, // llvm.hexagon.S2.lsr.i.p.ac c
hexagon_S2_lsr_i_p_and, // llvm.hexagon.S2.lsr.i.p.an d hexagon_S2_lsr_i_p_and, // llvm.hexagon.S2.lsr.i.p.an d
skipping to change at line 785 skipping to change at line 949
hexagon_S2_lsr_i_r_nac, // llvm.hexagon.S2.lsr.i.r.na c hexagon_S2_lsr_i_r_nac, // llvm.hexagon.S2.lsr.i.r.na c
hexagon_S2_lsr_i_r_or, // llvm.hexagon.S2.lsr.i.r.or hexagon_S2_lsr_i_r_or, // llvm.hexagon.S2.lsr.i.r.or
hexagon_S2_lsr_i_r_xacc, // llvm.hexagon.S2.lsr.i.r.xa cc hexagon_S2_lsr_i_r_xacc, // llvm.hexagon.S2.lsr.i.r.xa cc
hexagon_S2_lsr_i_vh, // llvm.hexagon.S2.lsr.i.vh hexagon_S2_lsr_i_vh, // llvm.hexagon.S2.lsr.i.vh
hexagon_S2_lsr_i_vw, // llvm.hexagon.S2.lsr.i.vw hexagon_S2_lsr_i_vw, // llvm.hexagon.S2.lsr.i.vw
hexagon_S2_lsr_r_p, // llvm.hexagon.S2.lsr.r.p hexagon_S2_lsr_r_p, // llvm.hexagon.S2.lsr.r.p
hexagon_S2_lsr_r_p_acc, // llvm.hexagon.S2.lsr.r.p.ac c hexagon_S2_lsr_r_p_acc, // llvm.hexagon.S2.lsr.r.p.ac c
hexagon_S2_lsr_r_p_and, // llvm.hexagon.S2.lsr.r.p.an d hexagon_S2_lsr_r_p_and, // llvm.hexagon.S2.lsr.r.p.an d
hexagon_S2_lsr_r_p_nac, // llvm.hexagon.S2.lsr.r.p.na c hexagon_S2_lsr_r_p_nac, // llvm.hexagon.S2.lsr.r.p.na c
hexagon_S2_lsr_r_p_or, // llvm.hexagon.S2.lsr.r.p.or hexagon_S2_lsr_r_p_or, // llvm.hexagon.S2.lsr.r.p.or
hexagon_S2_lsr_r_p_xor, // llvm.hexagon.S2.lsr.r.p.xo r
hexagon_S2_lsr_r_r, // llvm.hexagon.S2.lsr.r.r hexagon_S2_lsr_r_r, // llvm.hexagon.S2.lsr.r.r
hexagon_S2_lsr_r_r_acc, // llvm.hexagon.S2.lsr.r.r.ac c hexagon_S2_lsr_r_r_acc, // llvm.hexagon.S2.lsr.r.r.ac c
hexagon_S2_lsr_r_r_and, // llvm.hexagon.S2.lsr.r.r.an d hexagon_S2_lsr_r_r_and, // llvm.hexagon.S2.lsr.r.r.an d
hexagon_S2_lsr_r_r_nac, // llvm.hexagon.S2.lsr.r.r.na c hexagon_S2_lsr_r_r_nac, // llvm.hexagon.S2.lsr.r.r.na c
hexagon_S2_lsr_r_r_or, // llvm.hexagon.S2.lsr.r.r.or hexagon_S2_lsr_r_r_or, // llvm.hexagon.S2.lsr.r.r.or
hexagon_S2_lsr_r_vh, // llvm.hexagon.S2.lsr.r.vh hexagon_S2_lsr_r_vh, // llvm.hexagon.S2.lsr.r.vh
hexagon_S2_lsr_r_vw, // llvm.hexagon.S2.lsr.r.vw hexagon_S2_lsr_r_vw, // llvm.hexagon.S2.lsr.r.vw
hexagon_S2_packhl, // llvm.hexagon.S2.packhl hexagon_S2_packhl, // llvm.hexagon.S2.packhl
hexagon_S2_parityp, // llvm.hexagon.S2.parityp hexagon_S2_parityp, // llvm.hexagon.S2.parityp
hexagon_S2_setbit_i, // llvm.hexagon.S2.setbit.i hexagon_S2_setbit_i, // llvm.hexagon.S2.setbit.i
skipping to change at line 812 skipping to change at line 977
hexagon_S2_tableidxb_goodsyntax, // llvm.hexagon.S2.tableidxb. goodsyntax hexagon_S2_tableidxb_goodsyntax, // llvm.hexagon.S2.tableidxb. goodsyntax
hexagon_S2_tableidxd_goodsyntax, // llvm.hexagon.S2.tableidxd. goodsyntax hexagon_S2_tableidxd_goodsyntax, // llvm.hexagon.S2.tableidxd. goodsyntax
hexagon_S2_tableidxh_goodsyntax, // llvm.hexagon.S2.tableidxh. goodsyntax hexagon_S2_tableidxh_goodsyntax, // llvm.hexagon.S2.tableidxh. goodsyntax
hexagon_S2_tableidxw_goodsyntax, // llvm.hexagon.S2.tableidxw. goodsyntax hexagon_S2_tableidxw_goodsyntax, // llvm.hexagon.S2.tableidxw. goodsyntax
hexagon_S2_togglebit_i, // llvm.hexagon.S2.togglebit. i hexagon_S2_togglebit_i, // llvm.hexagon.S2.togglebit. i
hexagon_S2_togglebit_r, // llvm.hexagon.S2.togglebit. r hexagon_S2_togglebit_r, // llvm.hexagon.S2.togglebit. r
hexagon_S2_tstbit_i, // llvm.hexagon.S2.tstbit.i hexagon_S2_tstbit_i, // llvm.hexagon.S2.tstbit.i
hexagon_S2_tstbit_r, // llvm.hexagon.S2.tstbit.r hexagon_S2_tstbit_r, // llvm.hexagon.S2.tstbit.r
hexagon_S2_valignib, // llvm.hexagon.S2.valignib hexagon_S2_valignib, // llvm.hexagon.S2.valignib
hexagon_S2_valignrb, // llvm.hexagon.S2.valignrb hexagon_S2_valignrb, // llvm.hexagon.S2.valignrb
hexagon_S2_vcnegh, // llvm.hexagon.S2.vcnegh
hexagon_S2_vcrotate, // llvm.hexagon.S2.vcrotate hexagon_S2_vcrotate, // llvm.hexagon.S2.vcrotate
hexagon_S2_vrcnegh, // llvm.hexagon.S2.vrcnegh
hexagon_S2_vrndpackwh, // llvm.hexagon.S2.vrndpackwh hexagon_S2_vrndpackwh, // llvm.hexagon.S2.vrndpackwh
hexagon_S2_vrndpackwhs, // llvm.hexagon.S2.vrndpackwh s hexagon_S2_vrndpackwhs, // llvm.hexagon.S2.vrndpackwh s
hexagon_S2_vsathb, // llvm.hexagon.S2.vsathb hexagon_S2_vsathb, // llvm.hexagon.S2.vsathb
hexagon_S2_vsathb_nopack, // llvm.hexagon.S2.vsathb.nop ack hexagon_S2_vsathb_nopack, // llvm.hexagon.S2.vsathb.nop ack
hexagon_S2_vsathub, // llvm.hexagon.S2.vsathub hexagon_S2_vsathub, // llvm.hexagon.S2.vsathub
hexagon_S2_vsathub_nopack, // llvm.hexagon.S2.vsathub.no pack hexagon_S2_vsathub_nopack, // llvm.hexagon.S2.vsathub.no pack
hexagon_S2_vsatwh, // llvm.hexagon.S2.vsatwh hexagon_S2_vsatwh, // llvm.hexagon.S2.vsatwh
hexagon_S2_vsatwh_nopack, // llvm.hexagon.S2.vsatwh.nop ack hexagon_S2_vsatwh_nopack, // llvm.hexagon.S2.vsatwh.nop ack
hexagon_S2_vsatwuh, // llvm.hexagon.S2.vsatwuh hexagon_S2_vsatwuh, // llvm.hexagon.S2.vsatwuh
hexagon_S2_vsatwuh_nopack, // llvm.hexagon.S2.vsatwuh.no pack hexagon_S2_vsatwuh_nopack, // llvm.hexagon.S2.vsatwuh.no pack
skipping to change at line 836 skipping to change at line 1003
hexagon_S2_vsplicerb, // llvm.hexagon.S2.vsplicerb hexagon_S2_vsplicerb, // llvm.hexagon.S2.vsplicerb
hexagon_S2_vsxtbh, // llvm.hexagon.S2.vsxtbh hexagon_S2_vsxtbh, // llvm.hexagon.S2.vsxtbh
hexagon_S2_vsxthw, // llvm.hexagon.S2.vsxthw hexagon_S2_vsxthw, // llvm.hexagon.S2.vsxthw
hexagon_S2_vtrunehb, // llvm.hexagon.S2.vtrunehb hexagon_S2_vtrunehb, // llvm.hexagon.S2.vtrunehb
hexagon_S2_vtrunewh, // llvm.hexagon.S2.vtrunewh hexagon_S2_vtrunewh, // llvm.hexagon.S2.vtrunewh
hexagon_S2_vtrunohb, // llvm.hexagon.S2.vtrunohb hexagon_S2_vtrunohb, // llvm.hexagon.S2.vtrunohb
hexagon_S2_vtrunowh, // llvm.hexagon.S2.vtrunowh hexagon_S2_vtrunowh, // llvm.hexagon.S2.vtrunowh
hexagon_S2_vzxtbh, // llvm.hexagon.S2.vzxtbh hexagon_S2_vzxtbh, // llvm.hexagon.S2.vzxtbh
hexagon_S2_vzxthw, // llvm.hexagon.S2.vzxthw hexagon_S2_vzxthw, // llvm.hexagon.S2.vzxthw
hexagon_S4_addaddi, // llvm.hexagon.S4.addaddi hexagon_S4_addaddi, // llvm.hexagon.S4.addaddi
hexagon_S4_andnp, // llvm.hexagon.S4.andnp hexagon_S4_addi_asl_ri, // llvm.hexagon.S4.addi.asl.r
i
hexagon_S4_addi_lsr_ri, // llvm.hexagon.S4.addi.lsr.r
i
hexagon_S4_andi_asl_ri, // llvm.hexagon.S4.andi.asl.r
i
hexagon_S4_andi_lsr_ri, // llvm.hexagon.S4.andi.lsr.r
i
hexagon_S4_clbaddi, // llvm.hexagon.S4.clbaddi
hexagon_S4_clbpaddi, // llvm.hexagon.S4.clbpaddi
hexagon_S4_clbpnorm, // llvm.hexagon.S4.clbpnorm
hexagon_S4_extract, // llvm.hexagon.S4.extract
hexagon_S4_extract_rp, // llvm.hexagon.S4.extract.rp
hexagon_S4_extractp, // llvm.hexagon.S4.extractp
hexagon_S4_extractp_rp, // llvm.hexagon.S4.extractp.r
p
hexagon_S4_lsli, // llvm.hexagon.S4.lsli
hexagon_S4_ntstbit_i, // llvm.hexagon.S4.ntstbit.i
hexagon_S4_ntstbit_r, // llvm.hexagon.S4.ntstbit.r
hexagon_S4_or_andi, // llvm.hexagon.S4.or.andi hexagon_S4_or_andi, // llvm.hexagon.S4.or.andi
hexagon_S4_or_andix, // llvm.hexagon.S4.or.andix hexagon_S4_or_andix, // llvm.hexagon.S4.or.andix
hexagon_S4_or_ori, // llvm.hexagon.S4.or.ori hexagon_S4_or_ori, // llvm.hexagon.S4.or.ori
hexagon_S4_ornp, // llvm.hexagon.S4.ornp hexagon_S4_ori_asl_ri, // llvm.hexagon.S4.ori.asl.ri
hexagon_S4_ori_lsr_ri, // llvm.hexagon.S4.ori.lsr.ri
hexagon_S4_parity, // llvm.hexagon.S4.parity
hexagon_S4_subaddi, // llvm.hexagon.S4.subaddi hexagon_S4_subaddi, // llvm.hexagon.S4.subaddi
hexagon_S4_subi_asl_ri, // llvm.hexagon.S4.subi.asl.r
i
hexagon_S4_subi_lsr_ri, // llvm.hexagon.S4.subi.lsr.r
i
hexagon_S4_vrcrotate, // llvm.hexagon.S4.vrcrotate
hexagon_S4_vrcrotate_acc, // llvm.hexagon.S4.vrcrotate.
acc
hexagon_S4_vxaddsubh, // llvm.hexagon.S4.vxaddsubh
hexagon_S4_vxaddsubhr, // llvm.hexagon.S4.vxaddsubhr
hexagon_S4_vxaddsubw, // llvm.hexagon.S4.vxaddsubw
hexagon_S4_vxsubaddh, // llvm.hexagon.S4.vxsubaddh
hexagon_S4_vxsubaddhr, // llvm.hexagon.S4.vxsubaddhr
hexagon_S4_vxsubaddw, // llvm.hexagon.S4.vxsubaddw
hexagon_S5_asrhub_rnd_sat_goodsyntax, // llvm.hexagon.S5.asrhub.rnd
.sat.goodsyntax
hexagon_S5_asrhub_sat, // llvm.hexagon.S5.asrhub.sat
hexagon_S5_popcountp, // llvm.hexagon.S5.popcountp
hexagon_S5_vasrhrnd_goodsyntax, // llvm.hexagon.S5.vasrhrnd.g
oodsyntax
hexagon_SI_to_SXTHI_asrh, // llvm.hexagon.SI.to.SXTHI.a srh hexagon_SI_to_SXTHI_asrh, // llvm.hexagon.SI.to.SXTHI.a srh
hexagon_circ_ldd, // llvm.hexagon.circ.ldd
init_trampoline, // llvm.init.trampoline init_trampoline, // llvm.init.trampoline
invariant_end, // llvm.invariant.end invariant_end, // llvm.invariant.end
invariant_start, // llvm.invariant.start invariant_start, // llvm.invariant.start
lifetime_end, // llvm.lifetime.end lifetime_end, // llvm.lifetime.end
lifetime_start, // llvm.lifetime.start lifetime_start, // llvm.lifetime.start
log, // llvm.log log, // llvm.log
log10, // llvm.log10 log10, // llvm.log10
log2, // llvm.log2 log2, // llvm.log2
longjmp, // llvm.longjmp longjmp, // llvm.longjmp
memcpy, // llvm.memcpy memcpy, // llvm.memcpy
memmove, // llvm.memmove memmove, // llvm.memmove
memset, // llvm.memset memset, // llvm.memset
mips_absq_s_ph, // llvm.mips.absq.s.ph
mips_absq_s_qb, // llvm.mips.absq.s.qb
mips_absq_s_w, // llvm.mips.absq.s.w
mips_addq_ph, // llvm.mips.addq.ph
mips_addq_s_ph, // llvm.mips.addq.s.ph
mips_addq_s_w, // llvm.mips.addq.s.w
mips_addqh_ph, // llvm.mips.addqh.ph
mips_addqh_r_ph, // llvm.mips.addqh.r.ph
mips_addqh_r_w, // llvm.mips.addqh.r.w
mips_addqh_w, // llvm.mips.addqh.w
mips_addsc, // llvm.mips.addsc
mips_addu_ph, // llvm.mips.addu.ph
mips_addu_qb, // llvm.mips.addu.qb
mips_addu_s_ph, // llvm.mips.addu.s.ph
mips_addu_s_qb, // llvm.mips.addu.s.qb
mips_adduh_qb, // llvm.mips.adduh.qb
mips_adduh_r_qb, // llvm.mips.adduh.r.qb
mips_addwc, // llvm.mips.addwc
mips_append, // llvm.mips.append
mips_balign, // llvm.mips.balign
mips_bitrev, // llvm.mips.bitrev
mips_bposge32, // llvm.mips.bposge32
mips_cmp_eq_ph, // llvm.mips.cmp.eq.ph
mips_cmp_le_ph, // llvm.mips.cmp.le.ph
mips_cmp_lt_ph, // llvm.mips.cmp.lt.ph
mips_cmpgdu_eq_qb, // llvm.mips.cmpgdu.eq.qb
mips_cmpgdu_le_qb, // llvm.mips.cmpgdu.le.qb
mips_cmpgdu_lt_qb, // llvm.mips.cmpgdu.lt.qb
mips_cmpgu_eq_qb, // llvm.mips.cmpgu.eq.qb
mips_cmpgu_le_qb, // llvm.mips.cmpgu.le.qb
mips_cmpgu_lt_qb, // llvm.mips.cmpgu.lt.qb
mips_cmpu_eq_qb, // llvm.mips.cmpu.eq.qb
mips_cmpu_le_qb, // llvm.mips.cmpu.le.qb
mips_cmpu_lt_qb, // llvm.mips.cmpu.lt.qb
mips_dpa_w_ph, // llvm.mips.dpa.w.ph
mips_dpaq_s_w_ph, // llvm.mips.dpaq.s.w.ph
mips_dpaq_sa_l_w, // llvm.mips.dpaq.sa.l.w
mips_dpaqx_s_w_ph, // llvm.mips.dpaqx.s.w.ph
mips_dpaqx_sa_w_ph, // llvm.mips.dpaqx.sa.w.ph
mips_dpau_h_qbl, // llvm.mips.dpau.h.qbl
mips_dpau_h_qbr, // llvm.mips.dpau.h.qbr
mips_dpax_w_ph, // llvm.mips.dpax.w.ph
mips_dps_w_ph, // llvm.mips.dps.w.ph
mips_dpsq_s_w_ph, // llvm.mips.dpsq.s.w.ph
mips_dpsq_sa_l_w, // llvm.mips.dpsq.sa.l.w
mips_dpsqx_s_w_ph, // llvm.mips.dpsqx.s.w.ph
mips_dpsqx_sa_w_ph, // llvm.mips.dpsqx.sa.w.ph
mips_dpsu_h_qbl, // llvm.mips.dpsu.h.qbl
mips_dpsu_h_qbr, // llvm.mips.dpsu.h.qbr
mips_dpsx_w_ph, // llvm.mips.dpsx.w.ph
mips_extp, // llvm.mips.extp
mips_extpdp, // llvm.mips.extpdp
mips_extr_r_w, // llvm.mips.extr.r.w
mips_extr_rs_w, // llvm.mips.extr.rs.w
mips_extr_s_h, // llvm.mips.extr.s.h
mips_extr_w, // llvm.mips.extr.w
mips_insv, // llvm.mips.insv
mips_lbux, // llvm.mips.lbux
mips_lhx, // llvm.mips.lhx
mips_lwx, // llvm.mips.lwx
mips_madd, // llvm.mips.madd
mips_maddu, // llvm.mips.maddu
mips_maq_s_w_phl, // llvm.mips.maq.s.w.phl
mips_maq_s_w_phr, // llvm.mips.maq.s.w.phr
mips_maq_sa_w_phl, // llvm.mips.maq.sa.w.phl
mips_maq_sa_w_phr, // llvm.mips.maq.sa.w.phr
mips_modsub, // llvm.mips.modsub
mips_msub, // llvm.mips.msub
mips_msubu, // llvm.mips.msubu
mips_mthlip, // llvm.mips.mthlip
mips_mul_ph, // llvm.mips.mul.ph
mips_mul_s_ph, // llvm.mips.mul.s.ph
mips_muleq_s_w_phl, // llvm.mips.muleq.s.w.phl
mips_muleq_s_w_phr, // llvm.mips.muleq.s.w.phr
mips_muleu_s_ph_qbl, // llvm.mips.muleu.s.ph.qbl
mips_muleu_s_ph_qbr, // llvm.mips.muleu.s.ph.qbr
mips_mulq_rs_ph, // llvm.mips.mulq.rs.ph
mips_mulq_rs_w, // llvm.mips.mulq.rs.w
mips_mulq_s_ph, // llvm.mips.mulq.s.ph
mips_mulq_s_w, // llvm.mips.mulq.s.w
mips_mulsa_w_ph, // llvm.mips.mulsa.w.ph
mips_mulsaq_s_w_ph, // llvm.mips.mulsaq.s.w.ph
mips_mult, // llvm.mips.mult
mips_multu, // llvm.mips.multu
mips_packrl_ph, // llvm.mips.packrl.ph
mips_pick_ph, // llvm.mips.pick.ph
mips_pick_qb, // llvm.mips.pick.qb
mips_preceq_w_phl, // llvm.mips.preceq.w.phl
mips_preceq_w_phr, // llvm.mips.preceq.w.phr
mips_precequ_ph_qbl, // llvm.mips.precequ.ph.qbl
mips_precequ_ph_qbla, // llvm.mips.precequ.ph.qbla
mips_precequ_ph_qbr, // llvm.mips.precequ.ph.qbr
mips_precequ_ph_qbra, // llvm.mips.precequ.ph.qbra
mips_preceu_ph_qbl, // llvm.mips.preceu.ph.qbl
mips_preceu_ph_qbla, // llvm.mips.preceu.ph.qbla
mips_preceu_ph_qbr, // llvm.mips.preceu.ph.qbr
mips_preceu_ph_qbra, // llvm.mips.preceu.ph.qbra
mips_precr_qb_ph, // llvm.mips.precr.qb.ph
mips_precr_sra_ph_w, // llvm.mips.precr.sra.ph.w
mips_precr_sra_r_ph_w, // llvm.mips.precr.sra.r.ph.w
mips_precrq_ph_w, // llvm.mips.precrq.ph.w
mips_precrq_qb_ph, // llvm.mips.precrq.qb.ph
mips_precrq_rs_ph_w, // llvm.mips.precrq.rs.ph.w
mips_precrqu_s_qb_ph, // llvm.mips.precrqu.s.qb.ph
mips_prepend, // llvm.mips.prepend
mips_raddu_w_qb, // llvm.mips.raddu.w.qb
mips_rddsp, // llvm.mips.rddsp
mips_repl_ph, // llvm.mips.repl.ph
mips_repl_qb, // llvm.mips.repl.qb
mips_shilo, // llvm.mips.shilo
mips_shll_ph, // llvm.mips.shll.ph
mips_shll_qb, // llvm.mips.shll.qb
mips_shll_s_ph, // llvm.mips.shll.s.ph
mips_shll_s_w, // llvm.mips.shll.s.w
mips_shra_ph, // llvm.mips.shra.ph
mips_shra_qb, // llvm.mips.shra.qb
mips_shra_r_ph, // llvm.mips.shra.r.ph
mips_shra_r_qb, // llvm.mips.shra.r.qb
mips_shra_r_w, // llvm.mips.shra.r.w
mips_shrl_ph, // llvm.mips.shrl.ph
mips_shrl_qb, // llvm.mips.shrl.qb
mips_subq_ph, // llvm.mips.subq.ph
mips_subq_s_ph, // llvm.mips.subq.s.ph
mips_subq_s_w, // llvm.mips.subq.s.w
mips_subqh_ph, // llvm.mips.subqh.ph
mips_subqh_r_ph, // llvm.mips.subqh.r.ph
mips_subqh_r_w, // llvm.mips.subqh.r.w
mips_subqh_w, // llvm.mips.subqh.w
mips_subu_ph, // llvm.mips.subu.ph
mips_subu_qb, // llvm.mips.subu.qb
mips_subu_s_ph, // llvm.mips.subu.s.ph
mips_subu_s_qb, // llvm.mips.subu.s.qb
mips_subuh_qb, // llvm.mips.subuh.qb
mips_subuh_r_qb, // llvm.mips.subuh.r.qb
mips_wrdsp, // llvm.mips.wrdsp
nvvm_abs_i, // llvm.nvvm.abs.i
nvvm_abs_ll, // llvm.nvvm.abs.ll
nvvm_add_rm_d, // llvm.nvvm.add.rm.d
nvvm_add_rm_f, // llvm.nvvm.add.rm.f
nvvm_add_rm_ftz_f, // llvm.nvvm.add.rm.ftz.f
nvvm_add_rn_d, // llvm.nvvm.add.rn.d
nvvm_add_rn_f, // llvm.nvvm.add.rn.f
nvvm_add_rn_ftz_f, // llvm.nvvm.add.rn.ftz.f
nvvm_add_rp_d, // llvm.nvvm.add.rp.d
nvvm_add_rp_f, // llvm.nvvm.add.rp.f
nvvm_add_rp_ftz_f, // llvm.nvvm.add.rp.ftz.f
nvvm_add_rz_d, // llvm.nvvm.add.rz.d
nvvm_add_rz_f, // llvm.nvvm.add.rz.f
nvvm_add_rz_ftz_f, // llvm.nvvm.add.rz.ftz.f
nvvm_atomic_load_add_f32, // llvm.nvvm.atomic.load.add.
f32
nvvm_atomic_load_dec_32, // llvm.nvvm.atomic.load.dec.
32
nvvm_atomic_load_inc_32, // llvm.nvvm.atomic.load.inc.
32
nvvm_barrier0, // llvm.nvvm.barrier0
nvvm_barrier0_and, // llvm.nvvm.barrier0.and
nvvm_barrier0_or, // llvm.nvvm.barrier0.or
nvvm_barrier0_popc, // llvm.nvvm.barrier0.popc
nvvm_bitcast_d2ll, // llvm.nvvm.bitcast.d2ll
nvvm_bitcast_f2i, // llvm.nvvm.bitcast.f2i
nvvm_bitcast_i2f, // llvm.nvvm.bitcast.i2f
nvvm_bitcast_ll2d, // llvm.nvvm.bitcast.ll2d
nvvm_brev32, // llvm.nvvm.brev32
nvvm_brev64, // llvm.nvvm.brev64
nvvm_ceil_d, // llvm.nvvm.ceil.d
nvvm_ceil_f, // llvm.nvvm.ceil.f
nvvm_ceil_ftz_f, // llvm.nvvm.ceil.ftz.f
nvvm_clz_i, // llvm.nvvm.clz.i
nvvm_clz_ll, // llvm.nvvm.clz.ll
nvvm_compiler_error, // llvm.nvvm.compiler.error
nvvm_compiler_warn, // llvm.nvvm.compiler.warn
nvvm_cos_approx_f, // llvm.nvvm.cos.approx.f
nvvm_cos_approx_ftz_f, // llvm.nvvm.cos.approx.ftz.f
nvvm_d2f_rm, // llvm.nvvm.d2f.rm
nvvm_d2f_rm_ftz, // llvm.nvvm.d2f.rm.ftz
nvvm_d2f_rn, // llvm.nvvm.d2f.rn
nvvm_d2f_rn_ftz, // llvm.nvvm.d2f.rn.ftz
nvvm_d2f_rp, // llvm.nvvm.d2f.rp
nvvm_d2f_rp_ftz, // llvm.nvvm.d2f.rp.ftz
nvvm_d2f_rz, // llvm.nvvm.d2f.rz
nvvm_d2f_rz_ftz, // llvm.nvvm.d2f.rz.ftz
nvvm_d2i_hi, // llvm.nvvm.d2i.hi
nvvm_d2i_lo, // llvm.nvvm.d2i.lo
nvvm_d2i_rm, // llvm.nvvm.d2i.rm
nvvm_d2i_rn, // llvm.nvvm.d2i.rn
nvvm_d2i_rp, // llvm.nvvm.d2i.rp
nvvm_d2i_rz, // llvm.nvvm.d2i.rz
nvvm_d2ll_rm, // llvm.nvvm.d2ll.rm
nvvm_d2ll_rn, // llvm.nvvm.d2ll.rn
nvvm_d2ll_rp, // llvm.nvvm.d2ll.rp
nvvm_d2ll_rz, // llvm.nvvm.d2ll.rz
nvvm_d2ui_rm, // llvm.nvvm.d2ui.rm
nvvm_d2ui_rn, // llvm.nvvm.d2ui.rn
nvvm_d2ui_rp, // llvm.nvvm.d2ui.rp
nvvm_d2ui_rz, // llvm.nvvm.d2ui.rz
nvvm_d2ull_rm, // llvm.nvvm.d2ull.rm
nvvm_d2ull_rn, // llvm.nvvm.d2ull.rn
nvvm_d2ull_rp, // llvm.nvvm.d2ull.rp
nvvm_d2ull_rz, // llvm.nvvm.d2ull.rz
nvvm_div_approx_f, // llvm.nvvm.div.approx.f
nvvm_div_approx_ftz_f, // llvm.nvvm.div.approx.ftz.f
nvvm_div_rm_d, // llvm.nvvm.div.rm.d
nvvm_div_rm_f, // llvm.nvvm.div.rm.f
nvvm_div_rm_ftz_f, // llvm.nvvm.div.rm.ftz.f
nvvm_div_rn_d, // llvm.nvvm.div.rn.d
nvvm_div_rn_f, // llvm.nvvm.div.rn.f
nvvm_div_rn_ftz_f, // llvm.nvvm.div.rn.ftz.f
nvvm_div_rp_d, // llvm.nvvm.div.rp.d
nvvm_div_rp_f, // llvm.nvvm.div.rp.f
nvvm_div_rp_ftz_f, // llvm.nvvm.div.rp.ftz.f
nvvm_div_rz_d, // llvm.nvvm.div.rz.d
nvvm_div_rz_f, // llvm.nvvm.div.rz.f
nvvm_div_rz_ftz_f, // llvm.nvvm.div.rz.ftz.f
nvvm_ex2_approx_d, // llvm.nvvm.ex2.approx.d
nvvm_ex2_approx_f, // llvm.nvvm.ex2.approx.f
nvvm_ex2_approx_ftz_f, // llvm.nvvm.ex2.approx.ftz.f
nvvm_f2h_rn, // llvm.nvvm.f2h.rn
nvvm_f2h_rn_ftz, // llvm.nvvm.f2h.rn.ftz
nvvm_f2i_rm, // llvm.nvvm.f2i.rm
nvvm_f2i_rm_ftz, // llvm.nvvm.f2i.rm.ftz
nvvm_f2i_rn, // llvm.nvvm.f2i.rn
nvvm_f2i_rn_ftz, // llvm.nvvm.f2i.rn.ftz
nvvm_f2i_rp, // llvm.nvvm.f2i.rp
nvvm_f2i_rp_ftz, // llvm.nvvm.f2i.rp.ftz
nvvm_f2i_rz, // llvm.nvvm.f2i.rz
nvvm_f2i_rz_ftz, // llvm.nvvm.f2i.rz.ftz
nvvm_f2ll_rm, // llvm.nvvm.f2ll.rm
nvvm_f2ll_rm_ftz, // llvm.nvvm.f2ll.rm.ftz
nvvm_f2ll_rn, // llvm.nvvm.f2ll.rn
nvvm_f2ll_rn_ftz, // llvm.nvvm.f2ll.rn.ftz
nvvm_f2ll_rp, // llvm.nvvm.f2ll.rp
nvvm_f2ll_rp_ftz, // llvm.nvvm.f2ll.rp.ftz
nvvm_f2ll_rz, // llvm.nvvm.f2ll.rz
nvvm_f2ll_rz_ftz, // llvm.nvvm.f2ll.rz.ftz
nvvm_f2ui_rm, // llvm.nvvm.f2ui.rm
nvvm_f2ui_rm_ftz, // llvm.nvvm.f2ui.rm.ftz
nvvm_f2ui_rn, // llvm.nvvm.f2ui.rn
nvvm_f2ui_rn_ftz, // llvm.nvvm.f2ui.rn.ftz
nvvm_f2ui_rp, // llvm.nvvm.f2ui.rp
nvvm_f2ui_rp_ftz, // llvm.nvvm.f2ui.rp.ftz
nvvm_f2ui_rz, // llvm.nvvm.f2ui.rz
nvvm_f2ui_rz_ftz, // llvm.nvvm.f2ui.rz.ftz
nvvm_f2ull_rm, // llvm.nvvm.f2ull.rm
nvvm_f2ull_rm_ftz, // llvm.nvvm.f2ull.rm.ftz
nvvm_f2ull_rn, // llvm.nvvm.f2ull.rn
nvvm_f2ull_rn_ftz, // llvm.nvvm.f2ull.rn.ftz
nvvm_f2ull_rp, // llvm.nvvm.f2ull.rp
nvvm_f2ull_rp_ftz, // llvm.nvvm.f2ull.rp.ftz
nvvm_f2ull_rz, // llvm.nvvm.f2ull.rz
nvvm_f2ull_rz_ftz, // llvm.nvvm.f2ull.rz.ftz
nvvm_fabs_d, // llvm.nvvm.fabs.d
nvvm_fabs_f, // llvm.nvvm.fabs.f
nvvm_fabs_ftz_f, // llvm.nvvm.fabs.ftz.f
nvvm_floor_d, // llvm.nvvm.floor.d
nvvm_floor_f, // llvm.nvvm.floor.f
nvvm_floor_ftz_f, // llvm.nvvm.floor.ftz.f
nvvm_fma_rm_d, // llvm.nvvm.fma.rm.d
nvvm_fma_rm_f, // llvm.nvvm.fma.rm.f
nvvm_fma_rm_ftz_f, // llvm.nvvm.fma.rm.ftz.f
nvvm_fma_rn_d, // llvm.nvvm.fma.rn.d
nvvm_fma_rn_f, // llvm.nvvm.fma.rn.f
nvvm_fma_rn_ftz_f, // llvm.nvvm.fma.rn.ftz.f
nvvm_fma_rp_d, // llvm.nvvm.fma.rp.d
nvvm_fma_rp_f, // llvm.nvvm.fma.rp.f
nvvm_fma_rp_ftz_f, // llvm.nvvm.fma.rp.ftz.f
nvvm_fma_rz_d, // llvm.nvvm.fma.rz.d
nvvm_fma_rz_f, // llvm.nvvm.fma.rz.f
nvvm_fma_rz_ftz_f, // llvm.nvvm.fma.rz.ftz.f
nvvm_fmax_d, // llvm.nvvm.fmax.d
nvvm_fmax_f, // llvm.nvvm.fmax.f
nvvm_fmax_ftz_f, // llvm.nvvm.fmax.ftz.f
nvvm_fmin_d, // llvm.nvvm.fmin.d
nvvm_fmin_f, // llvm.nvvm.fmin.f
nvvm_fmin_ftz_f, // llvm.nvvm.fmin.ftz.f
nvvm_h2f, // llvm.nvvm.h2f
nvvm_i2d_rm, // llvm.nvvm.i2d.rm
nvvm_i2d_rn, // llvm.nvvm.i2d.rn
nvvm_i2d_rp, // llvm.nvvm.i2d.rp
nvvm_i2d_rz, // llvm.nvvm.i2d.rz
nvvm_i2f_rm, // llvm.nvvm.i2f.rm
nvvm_i2f_rn, // llvm.nvvm.i2f.rn
nvvm_i2f_rp, // llvm.nvvm.i2f.rp
nvvm_i2f_rz, // llvm.nvvm.i2f.rz
nvvm_ldu_global_f, // llvm.nvvm.ldu.global.f
nvvm_ldu_global_i, // llvm.nvvm.ldu.global.i
nvvm_ldu_global_p, // llvm.nvvm.ldu.global.p
nvvm_lg2_approx_d, // llvm.nvvm.lg2.approx.d
nvvm_lg2_approx_f, // llvm.nvvm.lg2.approx.f
nvvm_lg2_approx_ftz_f, // llvm.nvvm.lg2.approx.ftz.f
nvvm_ll2d_rm, // llvm.nvvm.ll2d.rm
nvvm_ll2d_rn, // llvm.nvvm.ll2d.rn
nvvm_ll2d_rp, // llvm.nvvm.ll2d.rp
nvvm_ll2d_rz, // llvm.nvvm.ll2d.rz
nvvm_ll2f_rm, // llvm.nvvm.ll2f.rm
nvvm_ll2f_rn, // llvm.nvvm.ll2f.rn
nvvm_ll2f_rp, // llvm.nvvm.ll2f.rp
nvvm_ll2f_rz, // llvm.nvvm.ll2f.rz
nvvm_lohi_i2d, // llvm.nvvm.lohi.i2d
nvvm_max_i, // llvm.nvvm.max.i
nvvm_max_ll, // llvm.nvvm.max.ll
nvvm_max_ui, // llvm.nvvm.max.ui
nvvm_max_ull, // llvm.nvvm.max.ull
nvvm_membar_cta, // llvm.nvvm.membar.cta
nvvm_membar_gl, // llvm.nvvm.membar.gl
nvvm_membar_sys, // llvm.nvvm.membar.sys
nvvm_min_i, // llvm.nvvm.min.i
nvvm_min_ll, // llvm.nvvm.min.ll
nvvm_min_ui, // llvm.nvvm.min.ui
nvvm_min_ull, // llvm.nvvm.min.ull
nvvm_move_double, // llvm.nvvm.move.double
nvvm_move_float, // llvm.nvvm.move.float
nvvm_move_i16, // llvm.nvvm.move.i16
nvvm_move_i32, // llvm.nvvm.move.i32
nvvm_move_i64, // llvm.nvvm.move.i64
nvvm_move_i8, // llvm.nvvm.move.i8
nvvm_move_ptr, // llvm.nvvm.move.ptr
nvvm_mul24_i, // llvm.nvvm.mul24.i
nvvm_mul24_ui, // llvm.nvvm.mul24.ui
nvvm_mul_rm_d, // llvm.nvvm.mul.rm.d
nvvm_mul_rm_f, // llvm.nvvm.mul.rm.f
nvvm_mul_rm_ftz_f, // llvm.nvvm.mul.rm.ftz.f
nvvm_mul_rn_d, // llvm.nvvm.mul.rn.d
nvvm_mul_rn_f, // llvm.nvvm.mul.rn.f
nvvm_mul_rn_ftz_f, // llvm.nvvm.mul.rn.ftz.f
nvvm_mul_rp_d, // llvm.nvvm.mul.rp.d
nvvm_mul_rp_f, // llvm.nvvm.mul.rp.f
nvvm_mul_rp_ftz_f, // llvm.nvvm.mul.rp.ftz.f
nvvm_mul_rz_d, // llvm.nvvm.mul.rz.d
nvvm_mul_rz_f, // llvm.nvvm.mul.rz.f
nvvm_mul_rz_ftz_f, // llvm.nvvm.mul.rz.ftz.f
nvvm_mulhi_i, // llvm.nvvm.mulhi.i
nvvm_mulhi_ll, // llvm.nvvm.mulhi.ll
nvvm_mulhi_ui, // llvm.nvvm.mulhi.ui
nvvm_mulhi_ull, // llvm.nvvm.mulhi.ull
nvvm_popc_i, // llvm.nvvm.popc.i
nvvm_popc_ll, // llvm.nvvm.popc.ll
nvvm_prmt, // llvm.nvvm.prmt
nvvm_ptr_constant_to_gen, // llvm.nvvm.ptr.constant.to.
gen
nvvm_ptr_gen_to_constant, // llvm.nvvm.ptr.gen.to.const
ant
nvvm_ptr_gen_to_global, // llvm.nvvm.ptr.gen.to.globa
l
nvvm_ptr_gen_to_local, // llvm.nvvm.ptr.gen.to.local
nvvm_ptr_gen_to_param, // llvm.nvvm.ptr.gen.to.param
nvvm_ptr_gen_to_shared, // llvm.nvvm.ptr.gen.to.share
d
nvvm_ptr_global_to_gen, // llvm.nvvm.ptr.global.to.ge
n
nvvm_ptr_local_to_gen, // llvm.nvvm.ptr.local.to.gen
nvvm_ptr_shared_to_gen, // llvm.nvvm.ptr.shared.to.ge
n
nvvm_rcp_approx_ftz_d, // llvm.nvvm.rcp.approx.ftz.d
nvvm_rcp_rm_d, // llvm.nvvm.rcp.rm.d
nvvm_rcp_rm_f, // llvm.nvvm.rcp.rm.f
nvvm_rcp_rm_ftz_f, // llvm.nvvm.rcp.rm.ftz.f
nvvm_rcp_rn_d, // llvm.nvvm.rcp.rn.d
nvvm_rcp_rn_f, // llvm.nvvm.rcp.rn.f
nvvm_rcp_rn_ftz_f, // llvm.nvvm.rcp.rn.ftz.f
nvvm_rcp_rp_d, // llvm.nvvm.rcp.rp.d
nvvm_rcp_rp_f, // llvm.nvvm.rcp.rp.f
nvvm_rcp_rp_ftz_f, // llvm.nvvm.rcp.rp.ftz.f
nvvm_rcp_rz_d, // llvm.nvvm.rcp.rz.d
nvvm_rcp_rz_f, // llvm.nvvm.rcp.rz.f
nvvm_rcp_rz_ftz_f, // llvm.nvvm.rcp.rz.ftz.f
nvvm_read_ptx_sreg_ctaid_x, // llvm.nvvm.read.ptx.sreg.ct
aid.x
nvvm_read_ptx_sreg_ctaid_y, // llvm.nvvm.read.ptx.sreg.ct
aid.y
nvvm_read_ptx_sreg_ctaid_z, // llvm.nvvm.read.ptx.sreg.ct
aid.z
nvvm_read_ptx_sreg_nctaid_x, // llvm.nvvm.read.ptx.sreg.nc
taid.x
nvvm_read_ptx_sreg_nctaid_y, // llvm.nvvm.read.ptx.sreg.nc
taid.y
nvvm_read_ptx_sreg_nctaid_z, // llvm.nvvm.read.ptx.sreg.nc
taid.z
nvvm_read_ptx_sreg_ntid_x, // llvm.nvvm.read.ptx.sreg.nt
id.x
nvvm_read_ptx_sreg_ntid_y, // llvm.nvvm.read.ptx.sreg.nt
id.y
nvvm_read_ptx_sreg_ntid_z, // llvm.nvvm.read.ptx.sreg.nt
id.z
nvvm_read_ptx_sreg_tid_x, // llvm.nvvm.read.ptx.sreg.ti
d.x
nvvm_read_ptx_sreg_tid_y, // llvm.nvvm.read.ptx.sreg.ti
d.y
nvvm_read_ptx_sreg_tid_z, // llvm.nvvm.read.ptx.sreg.ti
d.z
nvvm_read_ptx_sreg_warpsize, // llvm.nvvm.read.ptx.sreg.wa
rpsize
nvvm_round_d, // llvm.nvvm.round.d
nvvm_round_f, // llvm.nvvm.round.f
nvvm_round_ftz_f, // llvm.nvvm.round.ftz.f
nvvm_rsqrt_approx_d, // llvm.nvvm.rsqrt.approx.d
nvvm_rsqrt_approx_f, // llvm.nvvm.rsqrt.approx.f
nvvm_rsqrt_approx_ftz_f, // llvm.nvvm.rsqrt.approx.ftz
.f
nvvm_sad_i, // llvm.nvvm.sad.i
nvvm_sad_ui, // llvm.nvvm.sad.ui
nvvm_saturate_d, // llvm.nvvm.saturate.d
nvvm_saturate_f, // llvm.nvvm.saturate.f
nvvm_saturate_ftz_f, // llvm.nvvm.saturate.ftz.f
nvvm_sin_approx_f, // llvm.nvvm.sin.approx.f
nvvm_sin_approx_ftz_f, // llvm.nvvm.sin.approx.ftz.f
nvvm_sqrt_approx_f, // llvm.nvvm.sqrt.approx.f
nvvm_sqrt_approx_ftz_f, // llvm.nvvm.sqrt.approx.ftz.
f
nvvm_sqrt_rm_d, // llvm.nvvm.sqrt.rm.d
nvvm_sqrt_rm_f, // llvm.nvvm.sqrt.rm.f
nvvm_sqrt_rm_ftz_f, // llvm.nvvm.sqrt.rm.ftz.f
nvvm_sqrt_rn_d, // llvm.nvvm.sqrt.rn.d
nvvm_sqrt_rn_f, // llvm.nvvm.sqrt.rn.f
nvvm_sqrt_rn_ftz_f, // llvm.nvvm.sqrt.rn.ftz.f
nvvm_sqrt_rp_d, // llvm.nvvm.sqrt.rp.d
nvvm_sqrt_rp_f, // llvm.nvvm.sqrt.rp.f
nvvm_sqrt_rp_ftz_f, // llvm.nvvm.sqrt.rp.ftz.f
nvvm_sqrt_rz_d, // llvm.nvvm.sqrt.rz.d
nvvm_sqrt_rz_f, // llvm.nvvm.sqrt.rz.f
nvvm_sqrt_rz_ftz_f, // llvm.nvvm.sqrt.rz.ftz.f
nvvm_trunc_d, // llvm.nvvm.trunc.d
nvvm_trunc_f, // llvm.nvvm.trunc.f
nvvm_trunc_ftz_f, // llvm.nvvm.trunc.ftz.f
nvvm_ui2d_rm, // llvm.nvvm.ui2d.rm
nvvm_ui2d_rn, // llvm.nvvm.ui2d.rn
nvvm_ui2d_rp, // llvm.nvvm.ui2d.rp
nvvm_ui2d_rz, // llvm.nvvm.ui2d.rz
nvvm_ui2f_rm, // llvm.nvvm.ui2f.rm
nvvm_ui2f_rn, // llvm.nvvm.ui2f.rn
nvvm_ui2f_rp, // llvm.nvvm.ui2f.rp
nvvm_ui2f_rz, // llvm.nvvm.ui2f.rz
nvvm_ull2d_rm, // llvm.nvvm.ull2d.rm
nvvm_ull2d_rn, // llvm.nvvm.ull2d.rn
nvvm_ull2d_rp, // llvm.nvvm.ull2d.rp
nvvm_ull2d_rz, // llvm.nvvm.ull2d.rz
nvvm_ull2f_rm, // llvm.nvvm.ull2f.rm
nvvm_ull2f_rn, // llvm.nvvm.ull2f.rn
nvvm_ull2f_rp, // llvm.nvvm.ull2f.rp
nvvm_ull2f_rz, // llvm.nvvm.ull2f.rz
objectsize, // llvm.objectsize objectsize, // llvm.objectsize
pcmarker, // llvm.pcmarker pcmarker, // llvm.pcmarker
pow, // llvm.pow pow, // llvm.pow
powi, // llvm.powi powi, // llvm.powi
ppc_altivec_dss, // llvm.ppc.altivec.dss ppc_altivec_dss, // llvm.ppc.altivec.dss
ppc_altivec_dssall, // llvm.ppc.altivec.dssall ppc_altivec_dssall, // llvm.ppc.altivec.dssall
ppc_altivec_dst, // llvm.ppc.altivec.dst ppc_altivec_dst, // llvm.ppc.altivec.dst
ppc_altivec_dstst, // llvm.ppc.altivec.dstst ppc_altivec_dstst, // llvm.ppc.altivec.dstst
ppc_altivec_dststt, // llvm.ppc.altivec.dststt ppc_altivec_dststt, // llvm.ppc.altivec.dststt
ppc_altivec_dstt, // llvm.ppc.altivec.dstt ppc_altivec_dstt, // llvm.ppc.altivec.dstt
skipping to change at line 1184 skipping to change at line 1797
x86_3dnowa_pfnacc, // llvm.x86.3dnowa.pfnacc x86_3dnowa_pfnacc, // llvm.x86.3dnowa.pfnacc
x86_3dnowa_pfpnacc, // llvm.x86.3dnowa.pfpnacc x86_3dnowa_pfpnacc, // llvm.x86.3dnowa.pfpnacc
x86_3dnowa_pi2fw, // llvm.x86.3dnowa.pi2fw x86_3dnowa_pi2fw, // llvm.x86.3dnowa.pi2fw
x86_3dnowa_pswapd, // llvm.x86.3dnowa.pswapd x86_3dnowa_pswapd, // llvm.x86.3dnowa.pswapd
x86_aesni_aesdec, // llvm.x86.aesni.aesdec x86_aesni_aesdec, // llvm.x86.aesni.aesdec
x86_aesni_aesdeclast, // llvm.x86.aesni.aesdeclast x86_aesni_aesdeclast, // llvm.x86.aesni.aesdeclast
x86_aesni_aesenc, // llvm.x86.aesni.aesenc x86_aesni_aesenc, // llvm.x86.aesni.aesenc
x86_aesni_aesenclast, // llvm.x86.aesni.aesenclast x86_aesni_aesenclast, // llvm.x86.aesni.aesenclast
x86_aesni_aesimc, // llvm.x86.aesni.aesimc x86_aesni_aesimc, // llvm.x86.aesni.aesimc
x86_aesni_aeskeygenassist, // llvm.x86.aesni.aeskeygenas sist x86_aesni_aeskeygenassist, // llvm.x86.aesni.aeskeygenas sist
x86_avx2_gather_d_d, // llvm.x86.avx2.gather.d.d
x86_avx2_gather_d_d_256, // llvm.x86.avx2.gather.d.d.2
56
x86_avx2_gather_d_pd, // llvm.x86.avx2.gather.d.pd
x86_avx2_gather_d_pd_256, // llvm.x86.avx2.gather.d.pd.
256
x86_avx2_gather_d_ps, // llvm.x86.avx2.gather.d.ps
x86_avx2_gather_d_ps_256, // llvm.x86.avx2.gather.d.ps.
256
x86_avx2_gather_d_q, // llvm.x86.avx2.gather.d.q
x86_avx2_gather_d_q_256, // llvm.x86.avx2.gather.d.q.2
56
x86_avx2_gather_q_d, // llvm.x86.avx2.gather.q.d
x86_avx2_gather_q_d_256, // llvm.x86.avx2.gather.q.d.2
56
x86_avx2_gather_q_pd, // llvm.x86.avx2.gather.q.pd
x86_avx2_gather_q_pd_256, // llvm.x86.avx2.gather.q.pd.
256
x86_avx2_gather_q_ps, // llvm.x86.avx2.gather.q.ps
x86_avx2_gather_q_ps_256, // llvm.x86.avx2.gather.q.ps.
256
x86_avx2_gather_q_q, // llvm.x86.avx2.gather.q.q
x86_avx2_gather_q_q_256, // llvm.x86.avx2.gather.q.q.2
56
x86_avx2_maskload_d, // llvm.x86.avx2.maskload.d x86_avx2_maskload_d, // llvm.x86.avx2.maskload.d
x86_avx2_maskload_d_256, // llvm.x86.avx2.maskload.d.2 56 x86_avx2_maskload_d_256, // llvm.x86.avx2.maskload.d.2 56
x86_avx2_maskload_q, // llvm.x86.avx2.maskload.q x86_avx2_maskload_q, // llvm.x86.avx2.maskload.q
x86_avx2_maskload_q_256, // llvm.x86.avx2.maskload.q.2 56 x86_avx2_maskload_q_256, // llvm.x86.avx2.maskload.q.2 56
x86_avx2_maskstore_d, // llvm.x86.avx2.maskstore.d x86_avx2_maskstore_d, // llvm.x86.avx2.maskstore.d
x86_avx2_maskstore_d_256, // llvm.x86.avx2.maskstore.d. 256 x86_avx2_maskstore_d_256, // llvm.x86.avx2.maskstore.d. 256
x86_avx2_maskstore_q, // llvm.x86.avx2.maskstore.q x86_avx2_maskstore_q, // llvm.x86.avx2.maskstore.q
x86_avx2_maskstore_q_256, // llvm.x86.avx2.maskstore.q. 256 x86_avx2_maskstore_q_256, // llvm.x86.avx2.maskstore.q. 256
x86_avx2_movntdqa, // llvm.x86.avx2.movntdqa x86_avx2_movntdqa, // llvm.x86.avx2.movntdqa
x86_avx2_mpsadbw, // llvm.x86.avx2.mpsadbw x86_avx2_mpsadbw, // llvm.x86.avx2.mpsadbw
skipping to change at line 1341 skipping to change at line 1970
x86_avx_maskstore_pd, // llvm.x86.avx.maskstore.pd x86_avx_maskstore_pd, // llvm.x86.avx.maskstore.pd
x86_avx_maskstore_pd_256, // llvm.x86.avx.maskstore.pd. 256 x86_avx_maskstore_pd_256, // llvm.x86.avx.maskstore.pd. 256
x86_avx_maskstore_ps, // llvm.x86.avx.maskstore.ps x86_avx_maskstore_ps, // llvm.x86.avx.maskstore.ps
x86_avx_maskstore_ps_256, // llvm.x86.avx.maskstore.ps. 256 x86_avx_maskstore_ps_256, // llvm.x86.avx.maskstore.ps. 256
x86_avx_max_pd_256, // llvm.x86.avx.max.pd.256 x86_avx_max_pd_256, // llvm.x86.avx.max.pd.256
x86_avx_max_ps_256, // llvm.x86.avx.max.ps.256 x86_avx_max_ps_256, // llvm.x86.avx.max.ps.256
x86_avx_min_pd_256, // llvm.x86.avx.min.pd.256 x86_avx_min_pd_256, // llvm.x86.avx.min.pd.256
x86_avx_min_ps_256, // llvm.x86.avx.min.ps.256 x86_avx_min_ps_256, // llvm.x86.avx.min.ps.256
x86_avx_movmsk_pd_256, // llvm.x86.avx.movmsk.pd.256 x86_avx_movmsk_pd_256, // llvm.x86.avx.movmsk.pd.256
x86_avx_movmsk_ps_256, // llvm.x86.avx.movmsk.ps.256 x86_avx_movmsk_ps_256, // llvm.x86.avx.movmsk.ps.256
x86_avx_movnt_dq_256, // llvm.x86.avx.movnt.dq.256
x86_avx_movnt_pd_256, // llvm.x86.avx.movnt.pd.256
x86_avx_movnt_ps_256, // llvm.x86.avx.movnt.ps.256
x86_avx_ptestc_256, // llvm.x86.avx.ptestc.256 x86_avx_ptestc_256, // llvm.x86.avx.ptestc.256
x86_avx_ptestnzc_256, // llvm.x86.avx.ptestnzc.256 x86_avx_ptestnzc_256, // llvm.x86.avx.ptestnzc.256
x86_avx_ptestz_256, // llvm.x86.avx.ptestz.256 x86_avx_ptestz_256, // llvm.x86.avx.ptestz.256
x86_avx_rcp_ps_256, // llvm.x86.avx.rcp.ps.256 x86_avx_rcp_ps_256, // llvm.x86.avx.rcp.ps.256
x86_avx_round_pd_256, // llvm.x86.avx.round.pd.256 x86_avx_round_pd_256, // llvm.x86.avx.round.pd.256
x86_avx_round_ps_256, // llvm.x86.avx.round.ps.256 x86_avx_round_ps_256, // llvm.x86.avx.round.ps.256
x86_avx_rsqrt_ps_256, // llvm.x86.avx.rsqrt.ps.256 x86_avx_rsqrt_ps_256, // llvm.x86.avx.rsqrt.ps.256
x86_avx_sqrt_pd_256, // llvm.x86.avx.sqrt.pd.256 x86_avx_sqrt_pd_256, // llvm.x86.avx.sqrt.pd.256
x86_avx_sqrt_ps_256, // llvm.x86.avx.sqrt.ps.256 x86_avx_sqrt_ps_256, // llvm.x86.avx.sqrt.ps.256
x86_avx_storeu_dq_256, // llvm.x86.avx.storeu.dq.256 x86_avx_storeu_dq_256, // llvm.x86.avx.storeu.dq.256
skipping to change at line 1396 skipping to change at line 2022
x86_avx_vzeroall, // llvm.x86.avx.vzeroall x86_avx_vzeroall, // llvm.x86.avx.vzeroall
x86_avx_vzeroupper, // llvm.x86.avx.vzeroupper x86_avx_vzeroupper, // llvm.x86.avx.vzeroupper
x86_bmi_bextr_32, // llvm.x86.bmi.bextr.32 x86_bmi_bextr_32, // llvm.x86.bmi.bextr.32
x86_bmi_bextr_64, // llvm.x86.bmi.bextr.64 x86_bmi_bextr_64, // llvm.x86.bmi.bextr.64
x86_bmi_bzhi_32, // llvm.x86.bmi.bzhi.32 x86_bmi_bzhi_32, // llvm.x86.bmi.bzhi.32
x86_bmi_bzhi_64, // llvm.x86.bmi.bzhi.64 x86_bmi_bzhi_64, // llvm.x86.bmi.bzhi.64
x86_bmi_pdep_32, // llvm.x86.bmi.pdep.32 x86_bmi_pdep_32, // llvm.x86.bmi.pdep.32
x86_bmi_pdep_64, // llvm.x86.bmi.pdep.64 x86_bmi_pdep_64, // llvm.x86.bmi.pdep.64
x86_bmi_pext_32, // llvm.x86.bmi.pext.32 x86_bmi_pext_32, // llvm.x86.bmi.pext.32
x86_bmi_pext_64, // llvm.x86.bmi.pext.64 x86_bmi_pext_64, // llvm.x86.bmi.pext.64
x86_fma4_vfmadd_pd, // llvm.x86.fma4.vfmadd.pd x86_fma_vfmadd_pd, // llvm.x86.fma.vfmadd.pd
x86_fma4_vfmadd_pd_256, // llvm.x86.fma4.vfmadd.pd.25 x86_fma_vfmadd_pd_256, // llvm.x86.fma.vfmadd.pd.256
6 x86_fma_vfmadd_ps, // llvm.x86.fma.vfmadd.ps
x86_fma4_vfmadd_ps, // llvm.x86.fma4.vfmadd.ps x86_fma_vfmadd_ps_256, // llvm.x86.fma.vfmadd.ps.256
x86_fma4_vfmadd_ps_256, // llvm.x86.fma4.vfmadd.ps.25 x86_fma_vfmadd_sd, // llvm.x86.fma.vfmadd.sd
6 x86_fma_vfmadd_ss, // llvm.x86.fma.vfmadd.ss
x86_fma4_vfmadd_sd, // llvm.x86.fma4.vfmadd.sd x86_fma_vfmaddsub_pd, // llvm.x86.fma.vfmaddsub.pd
x86_fma4_vfmadd_ss, // llvm.x86.fma4.vfmadd.ss x86_fma_vfmaddsub_pd_256, // llvm.x86.fma.vfmaddsub.pd.
x86_fma4_vfmaddsub_pd, // llvm.x86.fma4.vfmaddsub.pd 256
x86_fma4_vfmaddsub_pd_256, // llvm.x86.fma4.vfmaddsub.pd x86_fma_vfmaddsub_ps, // llvm.x86.fma.vfmaddsub.ps
.256 x86_fma_vfmaddsub_ps_256, // llvm.x86.fma.vfmaddsub.ps.
x86_fma4_vfmaddsub_ps, // llvm.x86.fma4.vfmaddsub.ps 256
x86_fma4_vfmaddsub_ps_256, // llvm.x86.fma4.vfmaddsub.ps x86_fma_vfmsub_pd, // llvm.x86.fma.vfmsub.pd
.256 x86_fma_vfmsub_pd_256, // llvm.x86.fma.vfmsub.pd.256
x86_fma4_vfmsub_pd, // llvm.x86.fma4.vfmsub.pd x86_fma_vfmsub_ps, // llvm.x86.fma.vfmsub.ps
x86_fma4_vfmsub_pd_256, // llvm.x86.fma4.vfmsub.pd.25 x86_fma_vfmsub_ps_256, // llvm.x86.fma.vfmsub.ps.256
6 x86_fma_vfmsub_sd, // llvm.x86.fma.vfmsub.sd
x86_fma4_vfmsub_ps, // llvm.x86.fma4.vfmsub.ps x86_fma_vfmsub_ss, // llvm.x86.fma.vfmsub.ss
x86_fma4_vfmsub_ps_256, // llvm.x86.fma4.vfmsub.ps.25 x86_fma_vfmsubadd_pd, // llvm.x86.fma.vfmsubadd.pd
6 x86_fma_vfmsubadd_pd_256, // llvm.x86.fma.vfmsubadd.pd.
x86_fma4_vfmsub_sd, // llvm.x86.fma4.vfmsub.sd 256
x86_fma4_vfmsub_ss, // llvm.x86.fma4.vfmsub.ss x86_fma_vfmsubadd_ps, // llvm.x86.fma.vfmsubadd.ps
x86_fma4_vfmsubadd_pd, // llvm.x86.fma4.vfmsubadd.pd x86_fma_vfmsubadd_ps_256, // llvm.x86.fma.vfmsubadd.ps.
x86_fma4_vfmsubadd_pd_256, // llvm.x86.fma4.vfmsubadd.pd 256
.256 x86_fma_vfnmadd_pd, // llvm.x86.fma.vfnmadd.pd
x86_fma4_vfmsubadd_ps, // llvm.x86.fma4.vfmsubadd.ps x86_fma_vfnmadd_pd_256, // llvm.x86.fma.vfnmadd.pd.25
x86_fma4_vfmsubadd_ps_256, // llvm.x86.fma4.vfmsubadd.ps 6
.256 x86_fma_vfnmadd_ps, // llvm.x86.fma.vfnmadd.ps
x86_fma4_vfnmadd_pd, // llvm.x86.fma4.vfnmadd.pd x86_fma_vfnmadd_ps_256, // llvm.x86.fma.vfnmadd.ps.25
x86_fma4_vfnmadd_pd_256, // llvm.x86.fma4.vfnmadd.pd.2 6
56 x86_fma_vfnmadd_sd, // llvm.x86.fma.vfnmadd.sd
x86_fma4_vfnmadd_ps, // llvm.x86.fma4.vfnmadd.ps x86_fma_vfnmadd_ss, // llvm.x86.fma.vfnmadd.ss
x86_fma4_vfnmadd_ps_256, // llvm.x86.fma4.vfnmadd.ps.2 x86_fma_vfnmsub_pd, // llvm.x86.fma.vfnmsub.pd
56 x86_fma_vfnmsub_pd_256, // llvm.x86.fma.vfnmsub.pd.25
x86_fma4_vfnmadd_sd, // llvm.x86.fma4.vfnmadd.sd 6
x86_fma4_vfnmadd_ss, // llvm.x86.fma4.vfnmadd.ss x86_fma_vfnmsub_ps, // llvm.x86.fma.vfnmsub.ps
x86_fma4_vfnmsub_pd, // llvm.x86.fma4.vfnmsub.pd x86_fma_vfnmsub_ps_256, // llvm.x86.fma.vfnmsub.ps.25
x86_fma4_vfnmsub_pd_256, // llvm.x86.fma4.vfnmsub.pd.2 6
56 x86_fma_vfnmsub_sd, // llvm.x86.fma.vfnmsub.sd
x86_fma4_vfnmsub_ps, // llvm.x86.fma4.vfnmsub.ps x86_fma_vfnmsub_ss, // llvm.x86.fma.vfnmsub.ss
x86_fma4_vfnmsub_ps_256, // llvm.x86.fma4.vfnmsub.ps.2
56
x86_fma4_vfnmsub_sd, // llvm.x86.fma4.vfnmsub.sd
x86_fma4_vfnmsub_ss, // llvm.x86.fma4.vfnmsub.ss
x86_int, // llvm.x86.int x86_int, // llvm.x86.int
x86_mmx_emms, // llvm.x86.mmx.emms x86_mmx_emms, // llvm.x86.mmx.emms
x86_mmx_femms, // llvm.x86.mmx.femms x86_mmx_femms, // llvm.x86.mmx.femms
x86_mmx_maskmovq, // llvm.x86.mmx.maskmovq x86_mmx_maskmovq, // llvm.x86.mmx.maskmovq
x86_mmx_movnt_dq, // llvm.x86.mmx.movnt.dq x86_mmx_movnt_dq, // llvm.x86.mmx.movnt.dq
x86_mmx_packssdw, // llvm.x86.mmx.packssdw x86_mmx_packssdw, // llvm.x86.mmx.packssdw
x86_mmx_packsswb, // llvm.x86.mmx.packsswb x86_mmx_packsswb, // llvm.x86.mmx.packsswb
x86_mmx_packuswb, // llvm.x86.mmx.packuswb x86_mmx_packuswb, // llvm.x86.mmx.packuswb
x86_mmx_padd_b, // llvm.x86.mmx.padd.b x86_mmx_padd_b, // llvm.x86.mmx.padd.b
x86_mmx_padd_d, // llvm.x86.mmx.padd.d x86_mmx_padd_d, // llvm.x86.mmx.padd.d
skipping to change at line 1500 skipping to change at line 2126
x86_mmx_psubs_w, // llvm.x86.mmx.psubs.w x86_mmx_psubs_w, // llvm.x86.mmx.psubs.w
x86_mmx_psubus_b, // llvm.x86.mmx.psubus.b x86_mmx_psubus_b, // llvm.x86.mmx.psubus.b
x86_mmx_psubus_w, // llvm.x86.mmx.psubus.w x86_mmx_psubus_w, // llvm.x86.mmx.psubus.w
x86_mmx_punpckhbw, // llvm.x86.mmx.punpckhbw x86_mmx_punpckhbw, // llvm.x86.mmx.punpckhbw
x86_mmx_punpckhdq, // llvm.x86.mmx.punpckhdq x86_mmx_punpckhdq, // llvm.x86.mmx.punpckhdq
x86_mmx_punpckhwd, // llvm.x86.mmx.punpckhwd x86_mmx_punpckhwd, // llvm.x86.mmx.punpckhwd
x86_mmx_punpcklbw, // llvm.x86.mmx.punpcklbw x86_mmx_punpcklbw, // llvm.x86.mmx.punpcklbw
x86_mmx_punpckldq, // llvm.x86.mmx.punpckldq x86_mmx_punpckldq, // llvm.x86.mmx.punpckldq
x86_mmx_punpcklwd, // llvm.x86.mmx.punpcklwd x86_mmx_punpcklwd, // llvm.x86.mmx.punpcklwd
x86_mmx_pxor, // llvm.x86.mmx.pxor x86_mmx_pxor, // llvm.x86.mmx.pxor
x86_pclmulqdq, // llvm.x86.pclmulqdq
x86_rdfsbase_32, // llvm.x86.rdfsbase.32 x86_rdfsbase_32, // llvm.x86.rdfsbase.32
x86_rdfsbase_64, // llvm.x86.rdfsbase.64 x86_rdfsbase_64, // llvm.x86.rdfsbase.64
x86_rdgsbase_32, // llvm.x86.rdgsbase.32 x86_rdgsbase_32, // llvm.x86.rdgsbase.32
x86_rdgsbase_64, // llvm.x86.rdgsbase.64 x86_rdgsbase_64, // llvm.x86.rdgsbase.64
x86_rdrand_16, // llvm.x86.rdrand.16
x86_rdrand_32, // llvm.x86.rdrand.32
x86_rdrand_64, // llvm.x86.rdrand.64
x86_sse2_add_sd, // llvm.x86.sse2.add.sd x86_sse2_add_sd, // llvm.x86.sse2.add.sd
x86_sse2_clflush, // llvm.x86.sse2.clflush x86_sse2_clflush, // llvm.x86.sse2.clflush
x86_sse2_cmp_pd, // llvm.x86.sse2.cmp.pd x86_sse2_cmp_pd, // llvm.x86.sse2.cmp.pd
x86_sse2_cmp_sd, // llvm.x86.sse2.cmp.sd x86_sse2_cmp_sd, // llvm.x86.sse2.cmp.sd
x86_sse2_comieq_sd, // llvm.x86.sse2.comieq.sd x86_sse2_comieq_sd, // llvm.x86.sse2.comieq.sd
x86_sse2_comige_sd, // llvm.x86.sse2.comige.sd x86_sse2_comige_sd, // llvm.x86.sse2.comige.sd
x86_sse2_comigt_sd, // llvm.x86.sse2.comigt.sd x86_sse2_comigt_sd, // llvm.x86.sse2.comigt.sd
x86_sse2_comile_sd, // llvm.x86.sse2.comile.sd x86_sse2_comile_sd, // llvm.x86.sse2.comile.sd
x86_sse2_comilt_sd, // llvm.x86.sse2.comilt.sd x86_sse2_comilt_sd, // llvm.x86.sse2.comilt.sd
x86_sse2_comineq_sd, // llvm.x86.sse2.comineq.sd x86_sse2_comineq_sd, // llvm.x86.sse2.comineq.sd
skipping to change at line 1668 skipping to change at line 2298
x86_sse42_pcmpestris128, // llvm.x86.sse42.pcmpestris1 28 x86_sse42_pcmpestris128, // llvm.x86.sse42.pcmpestris1 28
x86_sse42_pcmpestriz128, // llvm.x86.sse42.pcmpestriz1 28 x86_sse42_pcmpestriz128, // llvm.x86.sse42.pcmpestriz1 28
x86_sse42_pcmpestrm128, // llvm.x86.sse42.pcmpestrm12 8 x86_sse42_pcmpestrm128, // llvm.x86.sse42.pcmpestrm12 8
x86_sse42_pcmpistri128, // llvm.x86.sse42.pcmpistri12 8 x86_sse42_pcmpistri128, // llvm.x86.sse42.pcmpistri12 8
x86_sse42_pcmpistria128, // llvm.x86.sse42.pcmpistria1 28 x86_sse42_pcmpistria128, // llvm.x86.sse42.pcmpistria1 28
x86_sse42_pcmpistric128, // llvm.x86.sse42.pcmpistric1 28 x86_sse42_pcmpistric128, // llvm.x86.sse42.pcmpistric1 28
x86_sse42_pcmpistrio128, // llvm.x86.sse42.pcmpistrio1 28 x86_sse42_pcmpistrio128, // llvm.x86.sse42.pcmpistrio1 28
x86_sse42_pcmpistris128, // llvm.x86.sse42.pcmpistris1 28 x86_sse42_pcmpistris128, // llvm.x86.sse42.pcmpistris1 28
x86_sse42_pcmpistriz128, // llvm.x86.sse42.pcmpistriz1 28 x86_sse42_pcmpistriz128, // llvm.x86.sse42.pcmpistriz1 28
x86_sse42_pcmpistrm128, // llvm.x86.sse42.pcmpistrm12 8 x86_sse42_pcmpistrm128, // llvm.x86.sse42.pcmpistrm12 8
x86_sse4a_extrq, // llvm.x86.sse4a.extrq
x86_sse4a_extrqi, // llvm.x86.sse4a.extrqi
x86_sse4a_insertq, // llvm.x86.sse4a.insertq
x86_sse4a_insertqi, // llvm.x86.sse4a.insertqi
x86_sse4a_movnt_sd, // llvm.x86.sse4a.movnt.sd
x86_sse4a_movnt_ss, // llvm.x86.sse4a.movnt.ss
x86_sse_add_ss, // llvm.x86.sse.add.ss x86_sse_add_ss, // llvm.x86.sse.add.ss
x86_sse_cmp_ps, // llvm.x86.sse.cmp.ps x86_sse_cmp_ps, // llvm.x86.sse.cmp.ps
x86_sse_cmp_ss, // llvm.x86.sse.cmp.ss x86_sse_cmp_ss, // llvm.x86.sse.cmp.ss
x86_sse_comieq_ss, // llvm.x86.sse.comieq.ss x86_sse_comieq_ss, // llvm.x86.sse.comieq.ss
x86_sse_comige_ss, // llvm.x86.sse.comige.ss x86_sse_comige_ss, // llvm.x86.sse.comige.ss
x86_sse_comigt_ss, // llvm.x86.sse.comigt.ss x86_sse_comigt_ss, // llvm.x86.sse.comigt.ss
x86_sse_comile_ss, // llvm.x86.sse.comile.ss x86_sse_comile_ss, // llvm.x86.sse.comile.ss
x86_sse_comilt_ss, // llvm.x86.sse.comilt.ss x86_sse_comilt_ss, // llvm.x86.sse.comilt.ss
x86_sse_comineq_ss, // llvm.x86.sse.comineq.ss x86_sse_comineq_ss, // llvm.x86.sse.comineq.ss
x86_sse_cvtpd2pi, // llvm.x86.sse.cvtpd2pi x86_sse_cvtpd2pi, // llvm.x86.sse.cvtpd2pi
skipping to change at line 1752 skipping to change at line 2388
x86_ssse3_psign_w, // llvm.x86.ssse3.psign.w x86_ssse3_psign_w, // llvm.x86.ssse3.psign.w
x86_ssse3_psign_w_128, // llvm.x86.ssse3.psign.w.128 x86_ssse3_psign_w_128, // llvm.x86.ssse3.psign.w.128
x86_vcvtph2ps_128, // llvm.x86.vcvtph2ps.128 x86_vcvtph2ps_128, // llvm.x86.vcvtph2ps.128
x86_vcvtph2ps_256, // llvm.x86.vcvtph2ps.256 x86_vcvtph2ps_256, // llvm.x86.vcvtph2ps.256
x86_vcvtps2ph_128, // llvm.x86.vcvtps2ph.128 x86_vcvtps2ph_128, // llvm.x86.vcvtps2ph.128
x86_vcvtps2ph_256, // llvm.x86.vcvtps2ph.256 x86_vcvtps2ph_256, // llvm.x86.vcvtps2ph.256
x86_wrfsbase_32, // llvm.x86.wrfsbase.32 x86_wrfsbase_32, // llvm.x86.wrfsbase.32
x86_wrfsbase_64, // llvm.x86.wrfsbase.64 x86_wrfsbase_64, // llvm.x86.wrfsbase.64
x86_wrgsbase_32, // llvm.x86.wrgsbase.32 x86_wrgsbase_32, // llvm.x86.wrgsbase.32
x86_wrgsbase_64, // llvm.x86.wrgsbase.64 x86_wrgsbase_64, // llvm.x86.wrgsbase.64
x86_xabort, // llvm.x86.xabort
x86_xbegin, // llvm.x86.xbegin
x86_xend, // llvm.x86.xend
x86_xop_vfrcz_pd, // llvm.x86.xop.vfrcz.pd x86_xop_vfrcz_pd, // llvm.x86.xop.vfrcz.pd
x86_xop_vfrcz_pd_256, // llvm.x86.xop.vfrcz.pd.256 x86_xop_vfrcz_pd_256, // llvm.x86.xop.vfrcz.pd.256
x86_xop_vfrcz_ps, // llvm.x86.xop.vfrcz.ps x86_xop_vfrcz_ps, // llvm.x86.xop.vfrcz.ps
x86_xop_vfrcz_ps_256, // llvm.x86.xop.vfrcz.ps.256 x86_xop_vfrcz_ps_256, // llvm.x86.xop.vfrcz.ps.256
x86_xop_vfrcz_sd, // llvm.x86.xop.vfrcz.sd x86_xop_vfrcz_sd, // llvm.x86.xop.vfrcz.sd
x86_xop_vfrcz_ss, // llvm.x86.xop.vfrcz.ss x86_xop_vfrcz_ss, // llvm.x86.xop.vfrcz.ss
x86_xop_vpcmov, // llvm.x86.xop.vpcmov x86_xop_vpcmov, // llvm.x86.xop.vpcmov
x86_xop_vpcmov_256, // llvm.x86.xop.vpcmov.256 x86_xop_vpcmov_256, // llvm.x86.xop.vpcmov.256
x86_xop_vpcomeqb, // llvm.x86.xop.vpcomeqb x86_xop_vpcomb, // llvm.x86.xop.vpcomb
x86_xop_vpcomeqd, // llvm.x86.xop.vpcomeqd x86_xop_vpcomd, // llvm.x86.xop.vpcomd
x86_xop_vpcomeqq, // llvm.x86.xop.vpcomeqq x86_xop_vpcomq, // llvm.x86.xop.vpcomq
x86_xop_vpcomequb, // llvm.x86.xop.vpcomequb x86_xop_vpcomub, // llvm.x86.xop.vpcomub
x86_xop_vpcomequd, // llvm.x86.xop.vpcomequd x86_xop_vpcomud, // llvm.x86.xop.vpcomud
x86_xop_vpcomequq, // llvm.x86.xop.vpcomequq x86_xop_vpcomuq, // llvm.x86.xop.vpcomuq
x86_xop_vpcomequw, // llvm.x86.xop.vpcomequw x86_xop_vpcomuw, // llvm.x86.xop.vpcomuw
x86_xop_vpcomeqw, // llvm.x86.xop.vpcomeqw x86_xop_vpcomw, // llvm.x86.xop.vpcomw
x86_xop_vpcomfalseb, // llvm.x86.xop.vpcomfalseb
x86_xop_vpcomfalsed, // llvm.x86.xop.vpcomfalsed
x86_xop_vpcomfalseq, // llvm.x86.xop.vpcomfalseq
x86_xop_vpcomfalseub, // llvm.x86.xop.vpcomfalseub
x86_xop_vpcomfalseud, // llvm.x86.xop.vpcomfalseud
x86_xop_vpcomfalseuq, // llvm.x86.xop.vpcomfalseuq
x86_xop_vpcomfalseuw, // llvm.x86.xop.vpcomfalseuw
x86_xop_vpcomfalsew, // llvm.x86.xop.vpcomfalsew
x86_xop_vpcomgeb, // llvm.x86.xop.vpcomgeb
x86_xop_vpcomged, // llvm.x86.xop.vpcomged
x86_xop_vpcomgeq, // llvm.x86.xop.vpcomgeq
x86_xop_vpcomgeub, // llvm.x86.xop.vpcomgeub
x86_xop_vpcomgeud, // llvm.x86.xop.vpcomgeud
x86_xop_vpcomgeuq, // llvm.x86.xop.vpcomgeuq
x86_xop_vpcomgeuw, // llvm.x86.xop.vpcomgeuw
x86_xop_vpcomgew, // llvm.x86.xop.vpcomgew
x86_xop_vpcomgtb, // llvm.x86.xop.vpcomgtb
x86_xop_vpcomgtd, // llvm.x86.xop.vpcomgtd
x86_xop_vpcomgtq, // llvm.x86.xop.vpcomgtq
x86_xop_vpcomgtub, // llvm.x86.xop.vpcomgtub
x86_xop_vpcomgtud, // llvm.x86.xop.vpcomgtud
x86_xop_vpcomgtuq, // llvm.x86.xop.vpcomgtuq
x86_xop_vpcomgtuw, // llvm.x86.xop.vpcomgtuw
x86_xop_vpcomgtw, // llvm.x86.xop.vpcomgtw
x86_xop_vpcomleb, // llvm.x86.xop.vpcomleb
x86_xop_vpcomled, // llvm.x86.xop.vpcomled
x86_xop_vpcomleq, // llvm.x86.xop.vpcomleq
x86_xop_vpcomleub, // llvm.x86.xop.vpcomleub
x86_xop_vpcomleud, // llvm.x86.xop.vpcomleud
x86_xop_vpcomleuq, // llvm.x86.xop.vpcomleuq
x86_xop_vpcomleuw, // llvm.x86.xop.vpcomleuw
x86_xop_vpcomlew, // llvm.x86.xop.vpcomlew
x86_xop_vpcomltb, // llvm.x86.xop.vpcomltb
x86_xop_vpcomltd, // llvm.x86.xop.vpcomltd
x86_xop_vpcomltq, // llvm.x86.xop.vpcomltq
x86_xop_vpcomltub, // llvm.x86.xop.vpcomltub
x86_xop_vpcomltud, // llvm.x86.xop.vpcomltud
x86_xop_vpcomltuq, // llvm.x86.xop.vpcomltuq
x86_xop_vpcomltuw, // llvm.x86.xop.vpcomltuw
x86_xop_vpcomltw, // llvm.x86.xop.vpcomltw
x86_xop_vpcomneb, // llvm.x86.xop.vpcomneb
x86_xop_vpcomned, // llvm.x86.xop.vpcomned
x86_xop_vpcomneq, // llvm.x86.xop.vpcomneq
x86_xop_vpcomneub, // llvm.x86.xop.vpcomneub
x86_xop_vpcomneud, // llvm.x86.xop.vpcomneud
x86_xop_vpcomneuq, // llvm.x86.xop.vpcomneuq
x86_xop_vpcomneuw, // llvm.x86.xop.vpcomneuw
x86_xop_vpcomnew, // llvm.x86.xop.vpcomnew
x86_xop_vpcomtrueb, // llvm.x86.xop.vpcomtrueb
x86_xop_vpcomtrued, // llvm.x86.xop.vpcomtrued
x86_xop_vpcomtrueq, // llvm.x86.xop.vpcomtrueq
x86_xop_vpcomtrueub, // llvm.x86.xop.vpcomtrueub
x86_xop_vpcomtrueud, // llvm.x86.xop.vpcomtrueud
x86_xop_vpcomtrueuq, // llvm.x86.xop.vpcomtrueuq
x86_xop_vpcomtrueuw, // llvm.x86.xop.vpcomtrueuw
x86_xop_vpcomtruew, // llvm.x86.xop.vpcomtruew
x86_xop_vpermil2pd, // llvm.x86.xop.vpermil2pd x86_xop_vpermil2pd, // llvm.x86.xop.vpermil2pd
x86_xop_vpermil2pd_256, // llvm.x86.xop.vpermil2pd.25 6 x86_xop_vpermil2pd_256, // llvm.x86.xop.vpermil2pd.25 6
x86_xop_vpermil2ps, // llvm.x86.xop.vpermil2ps x86_xop_vpermil2ps, // llvm.x86.xop.vpermil2ps
x86_xop_vpermil2ps_256, // llvm.x86.xop.vpermil2ps.25 6 x86_xop_vpermil2ps_256, // llvm.x86.xop.vpermil2ps.25 6
x86_xop_vphaddbd, // llvm.x86.xop.vphaddbd x86_xop_vphaddbd, // llvm.x86.xop.vphaddbd
x86_xop_vphaddbq, // llvm.x86.xop.vphaddbq x86_xop_vphaddbq, // llvm.x86.xop.vphaddbq
x86_xop_vphaddbw, // llvm.x86.xop.vphaddbw x86_xop_vphaddbw, // llvm.x86.xop.vphaddbw
x86_xop_vphadddq, // llvm.x86.xop.vphadddq x86_xop_vphadddq, // llvm.x86.xop.vphadddq
x86_xop_vphaddubd, // llvm.x86.xop.vphaddubd x86_xop_vphaddubd, // llvm.x86.xop.vphaddubd
x86_xop_vphaddubq, // llvm.x86.xop.vphaddubq x86_xop_vphaddubq, // llvm.x86.xop.vphaddubq
skipping to change at line 1857 skipping to change at line 2440
x86_xop_vpmacssdqh, // llvm.x86.xop.vpmacssdqh x86_xop_vpmacssdqh, // llvm.x86.xop.vpmacssdqh
x86_xop_vpmacssdql, // llvm.x86.xop.vpmacssdql x86_xop_vpmacssdql, // llvm.x86.xop.vpmacssdql
x86_xop_vpmacsswd, // llvm.x86.xop.vpmacsswd x86_xop_vpmacsswd, // llvm.x86.xop.vpmacsswd
x86_xop_vpmacssww, // llvm.x86.xop.vpmacssww x86_xop_vpmacssww, // llvm.x86.xop.vpmacssww
x86_xop_vpmacswd, // llvm.x86.xop.vpmacswd x86_xop_vpmacswd, // llvm.x86.xop.vpmacswd
x86_xop_vpmacsww, // llvm.x86.xop.vpmacsww x86_xop_vpmacsww, // llvm.x86.xop.vpmacsww
x86_xop_vpmadcsswd, // llvm.x86.xop.vpmadcsswd x86_xop_vpmadcsswd, // llvm.x86.xop.vpmadcsswd
x86_xop_vpmadcswd, // llvm.x86.xop.vpmadcswd x86_xop_vpmadcswd, // llvm.x86.xop.vpmadcswd
x86_xop_vpperm, // llvm.x86.xop.vpperm x86_xop_vpperm, // llvm.x86.xop.vpperm
x86_xop_vprotb, // llvm.x86.xop.vprotb x86_xop_vprotb, // llvm.x86.xop.vprotb
x86_xop_vprotbi, // llvm.x86.xop.vprotbi
x86_xop_vprotd, // llvm.x86.xop.vprotd x86_xop_vprotd, // llvm.x86.xop.vprotd
x86_xop_vprotdi, // llvm.x86.xop.vprotdi
x86_xop_vprotq, // llvm.x86.xop.vprotq x86_xop_vprotq, // llvm.x86.xop.vprotq
x86_xop_vprotqi, // llvm.x86.xop.vprotqi
x86_xop_vprotw, // llvm.x86.xop.vprotw x86_xop_vprotw, // llvm.x86.xop.vprotw
x86_xop_vprotwi, // llvm.x86.xop.vprotwi
x86_xop_vpshab, // llvm.x86.xop.vpshab x86_xop_vpshab, // llvm.x86.xop.vpshab
x86_xop_vpshad, // llvm.x86.xop.vpshad x86_xop_vpshad, // llvm.x86.xop.vpshad
x86_xop_vpshaq, // llvm.x86.xop.vpshaq x86_xop_vpshaq, // llvm.x86.xop.vpshaq
x86_xop_vpshaw, // llvm.x86.xop.vpshaw x86_xop_vpshaw, // llvm.x86.xop.vpshaw
x86_xop_vpshlb, // llvm.x86.xop.vpshlb x86_xop_vpshlb, // llvm.x86.xop.vpshlb
x86_xop_vpshld, // llvm.x86.xop.vpshld x86_xop_vpshld, // llvm.x86.xop.vpshld
x86_xop_vpshlq, // llvm.x86.xop.vpshlq x86_xop_vpshlq, // llvm.x86.xop.vpshlq
x86_xop_vpshlw, // llvm.x86.xop.vpshlw x86_xop_vpshlw, // llvm.x86.xop.vpshlw
xcore_bitrev, // llvm.xcore.bitrev xcore_bitrev, // llvm.xcore.bitrev
xcore_checkevent, // llvm.xcore.checkevent xcore_checkevent, // llvm.xcore.checkevent
skipping to change at line 1944 skipping to change at line 2531
"llvm.arm.mrc", "llvm.arm.mrc",
"llvm.arm.mrc2", "llvm.arm.mrc2",
"llvm.arm.neon.vabds", "llvm.arm.neon.vabds",
"llvm.arm.neon.vabdu", "llvm.arm.neon.vabdu",
"llvm.arm.neon.vabs", "llvm.arm.neon.vabs",
"llvm.arm.neon.vacged", "llvm.arm.neon.vacged",
"llvm.arm.neon.vacgeq", "llvm.arm.neon.vacgeq",
"llvm.arm.neon.vacgtd", "llvm.arm.neon.vacgtd",
"llvm.arm.neon.vacgtq", "llvm.arm.neon.vacgtq",
"llvm.arm.neon.vaddhn", "llvm.arm.neon.vaddhn",
"llvm.arm.neon.vbsl",
"llvm.arm.neon.vcls", "llvm.arm.neon.vcls",
"llvm.arm.neon.vclz", "llvm.arm.neon.vclz",
"llvm.arm.neon.vcnt", "llvm.arm.neon.vcnt",
"llvm.arm.neon.vcvtfp2fxs", "llvm.arm.neon.vcvtfp2fxs",
"llvm.arm.neon.vcvtfp2fxu", "llvm.arm.neon.vcvtfp2fxu",
"llvm.arm.neon.vcvtfp2hf", "llvm.arm.neon.vcvtfp2hf",
"llvm.arm.neon.vcvtfxs2fp", "llvm.arm.neon.vcvtfxs2fp",
"llvm.arm.neon.vcvtfxu2fp", "llvm.arm.neon.vcvtfxu2fp",
"llvm.arm.neon.vcvthf2fp", "llvm.arm.neon.vcvthf2fp",
"llvm.arm.neon.vhadds", "llvm.arm.neon.vhadds",
skipping to change at line 2064 skipping to change at line 2652
"llvm.convertsif", "llvm.convertsif",
"llvm.convertss", "llvm.convertss",
"llvm.convertsu", "llvm.convertsu",
"llvm.convertuif", "llvm.convertuif",
"llvm.convertus", "llvm.convertus",
"llvm.convertuu", "llvm.convertuu",
"llvm.cos", "llvm.cos",
"llvm.ctlz", "llvm.ctlz",
"llvm.ctpop", "llvm.ctpop",
"llvm.cttz", "llvm.cttz",
"llvm.cuda.syncthreads",
"llvm.dbg.declare", "llvm.dbg.declare",
"llvm.dbg.value", "llvm.dbg.value",
"llvm.debugtrap",
"llvm.donothing",
"llvm.eh.dwarf.cfa", "llvm.eh.dwarf.cfa",
"llvm.eh.return.i32", "llvm.eh.return.i32",
"llvm.eh.return.i64", "llvm.eh.return.i64",
"llvm.eh.sjlj.callsite", "llvm.eh.sjlj.callsite",
"llvm.eh.sjlj.functioncontext", "llvm.eh.sjlj.functioncontext",
"llvm.eh.sjlj.longjmp", "llvm.eh.sjlj.longjmp",
"llvm.eh.sjlj.lsda", "llvm.eh.sjlj.lsda",
"llvm.eh.sjlj.setjmp", "llvm.eh.sjlj.setjmp",
"llvm.eh.typeid.for", "llvm.eh.typeid.for",
"llvm.eh.unwind.init", "llvm.eh.unwind.init",
"llvm.exp", "llvm.exp",
"llvm.exp2", "llvm.exp2",
"llvm.expect", "llvm.expect",
"llvm.fabs",
"llvm.floor",
"llvm.flt.rounds", "llvm.flt.rounds",
"llvm.fma", "llvm.fma",
"llvm.fmuladd",
"llvm.frameaddress", "llvm.frameaddress",
"llvm.gcread", "llvm.gcread",
"llvm.gcroot", "llvm.gcroot",
"llvm.gcwrite", "llvm.gcwrite",
"llvm.hexagon.A2.abs", "llvm.hexagon.A2.abs",
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"llvm.hexagon.A2.andp", "llvm.hexagon.A2.andp",
"llvm.hexagon.A2.aslh", "llvm.hexagon.A2.aslh",
skipping to change at line 2137 skipping to change at line 2727
"llvm.hexagon.A2.minu", "llvm.hexagon.A2.minu",
"llvm.hexagon.A2.minup", "llvm.hexagon.A2.minup",
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"llvm.hexagon.A2.subh.h16.ll", "llvm.hexagon.A2.subh.h16.ll",
skipping to change at line 2181 skipping to change at line 2772
"llvm.hexagon.A2.tfr", "llvm.hexagon.A2.tfr",
"llvm.hexagon.A2.tfrih", "llvm.hexagon.A2.tfrih",
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"llvm.hexagon.A2.vavghcr", "llvm.hexagon.A2.vavghcr",
"llvm.hexagon.A2.vavghr", "llvm.hexagon.A2.vavghr",
skipping to change at line 2209 skipping to change at line 2801
"llvm.hexagon.A2.vavgwr", "llvm.hexagon.A2.vavgwr",
"llvm.hexagon.A2.vcmpbeq", "llvm.hexagon.A2.vcmpbeq",
"llvm.hexagon.A2.vcmpbgtu", "llvm.hexagon.A2.vcmpbgtu",
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"llvm.hexagon.A2.vcmphgt", "llvm.hexagon.A2.vcmphgt",
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"llvm.hexagon.A2.vminb",
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"llvm.hexagon.A2.vnavgwr", "llvm.hexagon.A2.vnavgwr",
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skipping to change at line 2303 skipping to change at line 2934
"llvm.hexagon.C4.and.or", "llvm.hexagon.C4.and.or",
"llvm.hexagon.C4.and.orn", "llvm.hexagon.C4.and.orn",
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skipping to change at line 2337 skipping to change at line 3037
"llvm.hexagon.M2.cnacsc.s0", "llvm.hexagon.M2.cnacsc.s0",
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skipping to change at line 2438 skipping to change at line 3140
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skipping to change at line 2472 skipping to change at line 3176
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skipping to change at line 2545 skipping to change at line 3250
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skipping to change at line 2599 skipping to change at line 3342
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skipping to change at line 2690 skipping to change at line 3441
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"llvm.hexagon.S2.lsr.r.r.or", "llvm.hexagon.S2.lsr.r.r.or",
"llvm.hexagon.S2.lsr.r.vh", "llvm.hexagon.S2.lsr.r.vh",
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skipping to change at line 2717 skipping to change at line 3469
"llvm.hexagon.S2.tableidxb.goodsyntax", "llvm.hexagon.S2.tableidxb.goodsyntax",
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"llvm.hexagon.S2.vsatwuh.nopack", "llvm.hexagon.S2.vsatwuh.nopack",
skipping to change at line 2741 skipping to change at line 3495
"llvm.hexagon.S2.vsplicerb", "llvm.hexagon.S2.vsplicerb",
"llvm.hexagon.S2.vsxtbh", "llvm.hexagon.S2.vsxtbh",
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"llvm.nvvm.ui2d.rp",
"llvm.nvvm.ui2d.rz",
"llvm.nvvm.ui2f.rm",
"llvm.nvvm.ui2f.rn",
"llvm.nvvm.ui2f.rp",
"llvm.nvvm.ui2f.rz",
"llvm.nvvm.ull2d.rm",
"llvm.nvvm.ull2d.rn",
"llvm.nvvm.ull2d.rp",
"llvm.nvvm.ull2d.rz",
"llvm.nvvm.ull2f.rm",
"llvm.nvvm.ull2f.rn",
"llvm.nvvm.ull2f.rp",
"llvm.nvvm.ull2f.rz",
"llvm.objectsize", "llvm.objectsize",
"llvm.pcmarker", "llvm.pcmarker",
"llvm.pow", "llvm.pow",
"llvm.powi", "llvm.powi",
"llvm.ppc.altivec.dss", "llvm.ppc.altivec.dss",
"llvm.ppc.altivec.dssall", "llvm.ppc.altivec.dssall",
"llvm.ppc.altivec.dst", "llvm.ppc.altivec.dst",
"llvm.ppc.altivec.dstst", "llvm.ppc.altivec.dstst",
"llvm.ppc.altivec.dststt", "llvm.ppc.altivec.dststt",
"llvm.ppc.altivec.dstt", "llvm.ppc.altivec.dstt",
skipping to change at line 3089 skipping to change at line 4289
"llvm.x86.3dnowa.pfnacc", "llvm.x86.3dnowa.pfnacc",
"llvm.x86.3dnowa.pfpnacc", "llvm.x86.3dnowa.pfpnacc",
"llvm.x86.3dnowa.pi2fw", "llvm.x86.3dnowa.pi2fw",
"llvm.x86.3dnowa.pswapd", "llvm.x86.3dnowa.pswapd",
"llvm.x86.aesni.aesdec", "llvm.x86.aesni.aesdec",
"llvm.x86.aesni.aesdeclast", "llvm.x86.aesni.aesdeclast",
"llvm.x86.aesni.aesenc", "llvm.x86.aesni.aesenc",
"llvm.x86.aesni.aesenclast", "llvm.x86.aesni.aesenclast",
"llvm.x86.aesni.aesimc", "llvm.x86.aesni.aesimc",
"llvm.x86.aesni.aeskeygenassist", "llvm.x86.aesni.aeskeygenassist",
"llvm.x86.avx2.gather.d.d",
"llvm.x86.avx2.gather.d.d.256",
"llvm.x86.avx2.gather.d.pd",
"llvm.x86.avx2.gather.d.pd.256",
"llvm.x86.avx2.gather.d.ps",
"llvm.x86.avx2.gather.d.ps.256",
"llvm.x86.avx2.gather.d.q",
"llvm.x86.avx2.gather.d.q.256",
"llvm.x86.avx2.gather.q.d",
"llvm.x86.avx2.gather.q.d.256",
"llvm.x86.avx2.gather.q.pd",
"llvm.x86.avx2.gather.q.pd.256",
"llvm.x86.avx2.gather.q.ps",
"llvm.x86.avx2.gather.q.ps.256",
"llvm.x86.avx2.gather.q.q",
"llvm.x86.avx2.gather.q.q.256",
"llvm.x86.avx2.maskload.d", "llvm.x86.avx2.maskload.d",
"llvm.x86.avx2.maskload.d.256", "llvm.x86.avx2.maskload.d.256",
"llvm.x86.avx2.maskload.q", "llvm.x86.avx2.maskload.q",
"llvm.x86.avx2.maskload.q.256", "llvm.x86.avx2.maskload.q.256",
"llvm.x86.avx2.maskstore.d", "llvm.x86.avx2.maskstore.d",
"llvm.x86.avx2.maskstore.d.256", "llvm.x86.avx2.maskstore.d.256",
"llvm.x86.avx2.maskstore.q", "llvm.x86.avx2.maskstore.q",
"llvm.x86.avx2.maskstore.q.256", "llvm.x86.avx2.maskstore.q.256",
"llvm.x86.avx2.movntdqa", "llvm.x86.avx2.movntdqa",
"llvm.x86.avx2.mpsadbw", "llvm.x86.avx2.mpsadbw",
skipping to change at line 3246 skipping to change at line 4462
"llvm.x86.avx.maskstore.pd", "llvm.x86.avx.maskstore.pd",
"llvm.x86.avx.maskstore.pd.256", "llvm.x86.avx.maskstore.pd.256",
"llvm.x86.avx.maskstore.ps", "llvm.x86.avx.maskstore.ps",
"llvm.x86.avx.maskstore.ps.256", "llvm.x86.avx.maskstore.ps.256",
"llvm.x86.avx.max.pd.256", "llvm.x86.avx.max.pd.256",
"llvm.x86.avx.max.ps.256", "llvm.x86.avx.max.ps.256",
"llvm.x86.avx.min.pd.256", "llvm.x86.avx.min.pd.256",
"llvm.x86.avx.min.ps.256", "llvm.x86.avx.min.ps.256",
"llvm.x86.avx.movmsk.pd.256", "llvm.x86.avx.movmsk.pd.256",
"llvm.x86.avx.movmsk.ps.256", "llvm.x86.avx.movmsk.ps.256",
"llvm.x86.avx.movnt.dq.256",
"llvm.x86.avx.movnt.pd.256",
"llvm.x86.avx.movnt.ps.256",
"llvm.x86.avx.ptestc.256", "llvm.x86.avx.ptestc.256",
"llvm.x86.avx.ptestnzc.256", "llvm.x86.avx.ptestnzc.256",
"llvm.x86.avx.ptestz.256", "llvm.x86.avx.ptestz.256",
"llvm.x86.avx.rcp.ps.256", "llvm.x86.avx.rcp.ps.256",
"llvm.x86.avx.round.pd.256", "llvm.x86.avx.round.pd.256",
"llvm.x86.avx.round.ps.256", "llvm.x86.avx.round.ps.256",
"llvm.x86.avx.rsqrt.ps.256", "llvm.x86.avx.rsqrt.ps.256",
"llvm.x86.avx.sqrt.pd.256", "llvm.x86.avx.sqrt.pd.256",
"llvm.x86.avx.sqrt.ps.256", "llvm.x86.avx.sqrt.ps.256",
"llvm.x86.avx.storeu.dq.256", "llvm.x86.avx.storeu.dq.256",
skipping to change at line 3301 skipping to change at line 4514
"llvm.x86.avx.vzeroall", "llvm.x86.avx.vzeroall",
"llvm.x86.avx.vzeroupper", "llvm.x86.avx.vzeroupper",
"llvm.x86.bmi.bextr.32", "llvm.x86.bmi.bextr.32",
"llvm.x86.bmi.bextr.64", "llvm.x86.bmi.bextr.64",
"llvm.x86.bmi.bzhi.32", "llvm.x86.bmi.bzhi.32",
"llvm.x86.bmi.bzhi.64", "llvm.x86.bmi.bzhi.64",
"llvm.x86.bmi.pdep.32", "llvm.x86.bmi.pdep.32",
"llvm.x86.bmi.pdep.64", "llvm.x86.bmi.pdep.64",
"llvm.x86.bmi.pext.32", "llvm.x86.bmi.pext.32",
"llvm.x86.bmi.pext.64", "llvm.x86.bmi.pext.64",
"llvm.x86.fma4.vfmadd.pd", "llvm.x86.fma.vfmadd.pd",
"llvm.x86.fma4.vfmadd.pd.256", "llvm.x86.fma.vfmadd.pd.256",
"llvm.x86.fma4.vfmadd.ps", "llvm.x86.fma.vfmadd.ps",
"llvm.x86.fma4.vfmadd.ps.256", "llvm.x86.fma.vfmadd.ps.256",
"llvm.x86.fma4.vfmadd.sd", "llvm.x86.fma.vfmadd.sd",
"llvm.x86.fma4.vfmadd.ss", "llvm.x86.fma.vfmadd.ss",
"llvm.x86.fma4.vfmaddsub.pd", "llvm.x86.fma.vfmaddsub.pd",
"llvm.x86.fma4.vfmaddsub.pd.256", "llvm.x86.fma.vfmaddsub.pd.256",
"llvm.x86.fma4.vfmaddsub.ps", "llvm.x86.fma.vfmaddsub.ps",
"llvm.x86.fma4.vfmaddsub.ps.256", "llvm.x86.fma.vfmaddsub.ps.256",
"llvm.x86.fma4.vfmsub.pd", "llvm.x86.fma.vfmsub.pd",
"llvm.x86.fma4.vfmsub.pd.256", "llvm.x86.fma.vfmsub.pd.256",
"llvm.x86.fma4.vfmsub.ps", "llvm.x86.fma.vfmsub.ps",
"llvm.x86.fma4.vfmsub.ps.256", "llvm.x86.fma.vfmsub.ps.256",
"llvm.x86.fma4.vfmsub.sd", "llvm.x86.fma.vfmsub.sd",
"llvm.x86.fma4.vfmsub.ss", "llvm.x86.fma.vfmsub.ss",
"llvm.x86.fma4.vfmsubadd.pd", "llvm.x86.fma.vfmsubadd.pd",
"llvm.x86.fma4.vfmsubadd.pd.256", "llvm.x86.fma.vfmsubadd.pd.256",
"llvm.x86.fma4.vfmsubadd.ps", "llvm.x86.fma.vfmsubadd.ps",
"llvm.x86.fma4.vfmsubadd.ps.256", "llvm.x86.fma.vfmsubadd.ps.256",
"llvm.x86.fma4.vfnmadd.pd", "llvm.x86.fma.vfnmadd.pd",
"llvm.x86.fma4.vfnmadd.pd.256", "llvm.x86.fma.vfnmadd.pd.256",
"llvm.x86.fma4.vfnmadd.ps", "llvm.x86.fma.vfnmadd.ps",
"llvm.x86.fma4.vfnmadd.ps.256", "llvm.x86.fma.vfnmadd.ps.256",
"llvm.x86.fma4.vfnmadd.sd", "llvm.x86.fma.vfnmadd.sd",
"llvm.x86.fma4.vfnmadd.ss", "llvm.x86.fma.vfnmadd.ss",
"llvm.x86.fma4.vfnmsub.pd", "llvm.x86.fma.vfnmsub.pd",
"llvm.x86.fma4.vfnmsub.pd.256", "llvm.x86.fma.vfnmsub.pd.256",
"llvm.x86.fma4.vfnmsub.ps", "llvm.x86.fma.vfnmsub.ps",
"llvm.x86.fma4.vfnmsub.ps.256", "llvm.x86.fma.vfnmsub.ps.256",
"llvm.x86.fma4.vfnmsub.sd", "llvm.x86.fma.vfnmsub.sd",
"llvm.x86.fma4.vfnmsub.ss", "llvm.x86.fma.vfnmsub.ss",
"llvm.x86.int", "llvm.x86.int",
"llvm.x86.mmx.emms", "llvm.x86.mmx.emms",
"llvm.x86.mmx.femms", "llvm.x86.mmx.femms",
"llvm.x86.mmx.maskmovq", "llvm.x86.mmx.maskmovq",
"llvm.x86.mmx.movnt.dq", "llvm.x86.mmx.movnt.dq",
"llvm.x86.mmx.packssdw", "llvm.x86.mmx.packssdw",
"llvm.x86.mmx.packsswb", "llvm.x86.mmx.packsswb",
"llvm.x86.mmx.packuswb", "llvm.x86.mmx.packuswb",
"llvm.x86.mmx.padd.b", "llvm.x86.mmx.padd.b",
"llvm.x86.mmx.padd.d", "llvm.x86.mmx.padd.d",
skipping to change at line 3405 skipping to change at line 4618
"llvm.x86.mmx.psubs.w", "llvm.x86.mmx.psubs.w",
"llvm.x86.mmx.psubus.b", "llvm.x86.mmx.psubus.b",
"llvm.x86.mmx.psubus.w", "llvm.x86.mmx.psubus.w",
"llvm.x86.mmx.punpckhbw", "llvm.x86.mmx.punpckhbw",
"llvm.x86.mmx.punpckhdq", "llvm.x86.mmx.punpckhdq",
"llvm.x86.mmx.punpckhwd", "llvm.x86.mmx.punpckhwd",
"llvm.x86.mmx.punpcklbw", "llvm.x86.mmx.punpcklbw",
"llvm.x86.mmx.punpckldq", "llvm.x86.mmx.punpckldq",
"llvm.x86.mmx.punpcklwd", "llvm.x86.mmx.punpcklwd",
"llvm.x86.mmx.pxor", "llvm.x86.mmx.pxor",
"llvm.x86.pclmulqdq",
"llvm.x86.rdfsbase.32", "llvm.x86.rdfsbase.32",
"llvm.x86.rdfsbase.64", "llvm.x86.rdfsbase.64",
"llvm.x86.rdgsbase.32", "llvm.x86.rdgsbase.32",
"llvm.x86.rdgsbase.64", "llvm.x86.rdgsbase.64",
"llvm.x86.rdrand.16",
"llvm.x86.rdrand.32",
"llvm.x86.rdrand.64",
"llvm.x86.sse2.add.sd", "llvm.x86.sse2.add.sd",
"llvm.x86.sse2.clflush", "llvm.x86.sse2.clflush",
"llvm.x86.sse2.cmp.pd", "llvm.x86.sse2.cmp.pd",
"llvm.x86.sse2.cmp.sd", "llvm.x86.sse2.cmp.sd",
"llvm.x86.sse2.comieq.sd", "llvm.x86.sse2.comieq.sd",
"llvm.x86.sse2.comige.sd", "llvm.x86.sse2.comige.sd",
"llvm.x86.sse2.comigt.sd", "llvm.x86.sse2.comigt.sd",
"llvm.x86.sse2.comile.sd", "llvm.x86.sse2.comile.sd",
"llvm.x86.sse2.comilt.sd", "llvm.x86.sse2.comilt.sd",
"llvm.x86.sse2.comineq.sd", "llvm.x86.sse2.comineq.sd",
skipping to change at line 3573 skipping to change at line 4790
"llvm.x86.sse42.pcmpestris128", "llvm.x86.sse42.pcmpestris128",
"llvm.x86.sse42.pcmpestriz128", "llvm.x86.sse42.pcmpestriz128",
"llvm.x86.sse42.pcmpestrm128", "llvm.x86.sse42.pcmpestrm128",
"llvm.x86.sse42.pcmpistri128", "llvm.x86.sse42.pcmpistri128",
"llvm.x86.sse42.pcmpistria128", "llvm.x86.sse42.pcmpistria128",
"llvm.x86.sse42.pcmpistric128", "llvm.x86.sse42.pcmpistric128",
"llvm.x86.sse42.pcmpistrio128", "llvm.x86.sse42.pcmpistrio128",
"llvm.x86.sse42.pcmpistris128", "llvm.x86.sse42.pcmpistris128",
"llvm.x86.sse42.pcmpistriz128", "llvm.x86.sse42.pcmpistriz128",
"llvm.x86.sse42.pcmpistrm128", "llvm.x86.sse42.pcmpistrm128",
"llvm.x86.sse4a.extrq",
"llvm.x86.sse4a.extrqi",
"llvm.x86.sse4a.insertq",
"llvm.x86.sse4a.insertqi",
"llvm.x86.sse4a.movnt.sd",
"llvm.x86.sse4a.movnt.ss",
"llvm.x86.sse.add.ss", "llvm.x86.sse.add.ss",
"llvm.x86.sse.cmp.ps", "llvm.x86.sse.cmp.ps",
"llvm.x86.sse.cmp.ss", "llvm.x86.sse.cmp.ss",
"llvm.x86.sse.comieq.ss", "llvm.x86.sse.comieq.ss",
"llvm.x86.sse.comige.ss", "llvm.x86.sse.comige.ss",
"llvm.x86.sse.comigt.ss", "llvm.x86.sse.comigt.ss",
"llvm.x86.sse.comile.ss", "llvm.x86.sse.comile.ss",
"llvm.x86.sse.comilt.ss", "llvm.x86.sse.comilt.ss",
"llvm.x86.sse.comineq.ss", "llvm.x86.sse.comineq.ss",
"llvm.x86.sse.cvtpd2pi", "llvm.x86.sse.cvtpd2pi",
skipping to change at line 3657 skipping to change at line 4880
"llvm.x86.ssse3.psign.w", "llvm.x86.ssse3.psign.w",
"llvm.x86.ssse3.psign.w.128", "llvm.x86.ssse3.psign.w.128",
"llvm.x86.vcvtph2ps.128", "llvm.x86.vcvtph2ps.128",
"llvm.x86.vcvtph2ps.256", "llvm.x86.vcvtph2ps.256",
"llvm.x86.vcvtps2ph.128", "llvm.x86.vcvtps2ph.128",
"llvm.x86.vcvtps2ph.256", "llvm.x86.vcvtps2ph.256",
"llvm.x86.wrfsbase.32", "llvm.x86.wrfsbase.32",
"llvm.x86.wrfsbase.64", "llvm.x86.wrfsbase.64",
"llvm.x86.wrgsbase.32", "llvm.x86.wrgsbase.32",
"llvm.x86.wrgsbase.64", "llvm.x86.wrgsbase.64",
"llvm.x86.xabort",
"llvm.x86.xbegin",
"llvm.x86.xend",
"llvm.x86.xop.vfrcz.pd", "llvm.x86.xop.vfrcz.pd",
"llvm.x86.xop.vfrcz.pd.256", "llvm.x86.xop.vfrcz.pd.256",
"llvm.x86.xop.vfrcz.ps", "llvm.x86.xop.vfrcz.ps",
"llvm.x86.xop.vfrcz.ps.256", "llvm.x86.xop.vfrcz.ps.256",
"llvm.x86.xop.vfrcz.sd", "llvm.x86.xop.vfrcz.sd",
"llvm.x86.xop.vfrcz.ss", "llvm.x86.xop.vfrcz.ss",
"llvm.x86.xop.vpcmov", "llvm.x86.xop.vpcmov",
"llvm.x86.xop.vpcmov.256", "llvm.x86.xop.vpcmov.256",
"llvm.x86.xop.vpcomeqb", "llvm.x86.xop.vpcomb",
"llvm.x86.xop.vpcomeqd", "llvm.x86.xop.vpcomd",
"llvm.x86.xop.vpcomeqq", "llvm.x86.xop.vpcomq",
"llvm.x86.xop.vpcomequb", "llvm.x86.xop.vpcomub",
"llvm.x86.xop.vpcomequd", "llvm.x86.xop.vpcomud",
"llvm.x86.xop.vpcomequq", "llvm.x86.xop.vpcomuq",
"llvm.x86.xop.vpcomequw", "llvm.x86.xop.vpcomuw",
"llvm.x86.xop.vpcomeqw", "llvm.x86.xop.vpcomw",
"llvm.x86.xop.vpcomfalseb",
"llvm.x86.xop.vpcomfalsed",
"llvm.x86.xop.vpcomfalseq",
"llvm.x86.xop.vpcomfalseub",
"llvm.x86.xop.vpcomfalseud",
"llvm.x86.xop.vpcomfalseuq",
"llvm.x86.xop.vpcomfalseuw",
"llvm.x86.xop.vpcomfalsew",
"llvm.x86.xop.vpcomgeb",
"llvm.x86.xop.vpcomged",
"llvm.x86.xop.vpcomgeq",
"llvm.x86.xop.vpcomgeub",
"llvm.x86.xop.vpcomgeud",
"llvm.x86.xop.vpcomgeuq",
"llvm.x86.xop.vpcomgeuw",
"llvm.x86.xop.vpcomgew",
"llvm.x86.xop.vpcomgtb",
"llvm.x86.xop.vpcomgtd",
"llvm.x86.xop.vpcomgtq",
"llvm.x86.xop.vpcomgtub",
"llvm.x86.xop.vpcomgtud",
"llvm.x86.xop.vpcomgtuq",
"llvm.x86.xop.vpcomgtuw",
"llvm.x86.xop.vpcomgtw",
"llvm.x86.xop.vpcomleb",
"llvm.x86.xop.vpcomled",
"llvm.x86.xop.vpcomleq",
"llvm.x86.xop.vpcomleub",
"llvm.x86.xop.vpcomleud",
"llvm.x86.xop.vpcomleuq",
"llvm.x86.xop.vpcomleuw",
"llvm.x86.xop.vpcomlew",
"llvm.x86.xop.vpcomltb",
"llvm.x86.xop.vpcomltd",
"llvm.x86.xop.vpcomltq",
"llvm.x86.xop.vpcomltub",
"llvm.x86.xop.vpcomltud",
"llvm.x86.xop.vpcomltuq",
"llvm.x86.xop.vpcomltuw",
"llvm.x86.xop.vpcomltw",
"llvm.x86.xop.vpcomneb",
"llvm.x86.xop.vpcomned",
"llvm.x86.xop.vpcomneq",
"llvm.x86.xop.vpcomneub",
"llvm.x86.xop.vpcomneud",
"llvm.x86.xop.vpcomneuq",
"llvm.x86.xop.vpcomneuw",
"llvm.x86.xop.vpcomnew",
"llvm.x86.xop.vpcomtrueb",
"llvm.x86.xop.vpcomtrued",
"llvm.x86.xop.vpcomtrueq",
"llvm.x86.xop.vpcomtrueub",
"llvm.x86.xop.vpcomtrueud",
"llvm.x86.xop.vpcomtrueuq",
"llvm.x86.xop.vpcomtrueuw",
"llvm.x86.xop.vpcomtruew",
"llvm.x86.xop.vpermil2pd", "llvm.x86.xop.vpermil2pd",
"llvm.x86.xop.vpermil2pd.256", "llvm.x86.xop.vpermil2pd.256",
"llvm.x86.xop.vpermil2ps", "llvm.x86.xop.vpermil2ps",
"llvm.x86.xop.vpermil2ps.256", "llvm.x86.xop.vpermil2ps.256",
"llvm.x86.xop.vphaddbd", "llvm.x86.xop.vphaddbd",
"llvm.x86.xop.vphaddbq", "llvm.x86.xop.vphaddbq",
"llvm.x86.xop.vphaddbw", "llvm.x86.xop.vphaddbw",
"llvm.x86.xop.vphadddq", "llvm.x86.xop.vphadddq",
"llvm.x86.xop.vphaddubd", "llvm.x86.xop.vphaddubd",
"llvm.x86.xop.vphaddubq", "llvm.x86.xop.vphaddubq",
skipping to change at line 3762 skipping to change at line 4932
"llvm.x86.xop.vpmacssdqh", "llvm.x86.xop.vpmacssdqh",
"llvm.x86.xop.vpmacssdql", "llvm.x86.xop.vpmacssdql",
"llvm.x86.xop.vpmacsswd", "llvm.x86.xop.vpmacsswd",
"llvm.x86.xop.vpmacssww", "llvm.x86.xop.vpmacssww",
"llvm.x86.xop.vpmacswd", "llvm.x86.xop.vpmacswd",
"llvm.x86.xop.vpmacsww", "llvm.x86.xop.vpmacsww",
"llvm.x86.xop.vpmadcsswd", "llvm.x86.xop.vpmadcsswd",
"llvm.x86.xop.vpmadcswd", "llvm.x86.xop.vpmadcswd",
"llvm.x86.xop.vpperm", "llvm.x86.xop.vpperm",
"llvm.x86.xop.vprotb", "llvm.x86.xop.vprotb",
"llvm.x86.xop.vprotbi",
"llvm.x86.xop.vprotd", "llvm.x86.xop.vprotd",
"llvm.x86.xop.vprotdi",
"llvm.x86.xop.vprotq", "llvm.x86.xop.vprotq",
"llvm.x86.xop.vprotqi",
"llvm.x86.xop.vprotw", "llvm.x86.xop.vprotw",
"llvm.x86.xop.vprotwi",
"llvm.x86.xop.vpshab", "llvm.x86.xop.vpshab",
"llvm.x86.xop.vpshad", "llvm.x86.xop.vpshad",
"llvm.x86.xop.vpshaq", "llvm.x86.xop.vpshaq",
"llvm.x86.xop.vpshaw", "llvm.x86.xop.vpshaw",
"llvm.x86.xop.vpshlb", "llvm.x86.xop.vpshlb",
"llvm.x86.xop.vpshld", "llvm.x86.xop.vpshld",
"llvm.x86.xop.vpshlq", "llvm.x86.xop.vpshlq",
"llvm.x86.xop.vpshlw", "llvm.x86.xop.vpshlw",
"llvm.xcore.bitrev", "llvm.xcore.bitrev",
"llvm.xcore.checkevent", "llvm.xcore.checkevent",
skipping to change at line 3832 skipping to change at line 5006
"llvm.xcore.waitevent", "llvm.xcore.waitevent",
"llvm.xcore.zext", "llvm.xcore.zext",
#endif #endif
// Intrinsic ID to overload bitset // Intrinsic ID to overload bitset
#ifdef GET_INTRINSIC_OVERLOAD_TABLE #ifdef GET_INTRINSIC_OVERLOAD_TABLE
static const uint8_t OTable[] = { static const uint8_t OTable[] = {
0 | (1<<2), 0 | (1<<2),
0 | (1<<5) | (1<<6) | (1<<7), 0 | (1<<5) | (1<<6) | (1<<7),
0 | (1<<4) | (1<<5) | (1<<6) | (1<<7), 0 | (1<<4) | (1<<5) | (1<<6) | (1<<7),
0 | (1<<0) | (1<<1) | (1<<3) | (1<<4) | (1<<6) | (1<<7), 0 | (1<<0) | (1<<1) | (1<<2) | (1<<4) | (1<<5) | (1<<7),
0 | (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5) | (1<<6) | (1<<7) , 0 | (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5) | (1<<6) | (1<<7) ,
0 | (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5) | (1<<6) | (1<<7) , 0 | (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5) | (1<<6) | (1<<7) ,
0 | (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5) | (1<<6) | (1<<7) , 0 | (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5) | (1<<6) | (1<<7) ,
0 | (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5) | (1<<6) | (1<<7) , 0 | (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5) | (1<<6) | (1<<7) ,
0 | (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5) | (1<<6) | (1<<7) , 0 | (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5) | (1<<6) | (1<<7) ,
0 | (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5) | (1<<6) | (1<<7) , 0 | (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5) | (1<<6) | (1<<7) ,
0 | (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5) | (1<<6) | (1<<7) , 0 | (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5) | (1<<6) | (1<<7) ,
0 | (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5) | (1<<6) | (1<<7) , 0 | (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5) | (1<<6) | (1<<7) ,
0 | (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5) | (1<<6) | (1<<7) , 0 | (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5) | (1<<6) | (1<<7) ,
0 | (1<<0) | (1<<1) | (1<<2) | (1<<3),
0,
0 | (1<<3) | (1<<4) | (1<<5),
0 | (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5) | (1<<6) | (1<<7)
,
0 | (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4), 0 | (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4),
0, 0,
0 | (1<<1) | (1<<2) | (1<<3) | (1<<5), 0 | (1<<4) | (1<<5) | (1<<6),
0 | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5) | (1<<6) | (1<<7),
0 | (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5),
0,
0 | (1<<5) | (1<<6) | (1<<7),
0 | (1<<0) | (1<<1) | (1<<3) | (1<<4),
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
skipping to change at line 3932 skipping to change at line 5107
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0 | (1<<6) | (1<<7),
0 | (1<<0) | (1<<2) | (1<<3) | (1<<4) | (1<<5) | (1<<7),
0 | (1<<0),
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0 | (1<<6),
0, 0,
0, 0,
0, 0,
0, 0,
0 | (1<<3) | (1<<7), 0,
0 | (1<<0), 0,
0 | (1<<3) | (1<<4) | (1<<5) | (1<<7),
0 | (1<<0) | (1<<1),
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0 | (1<<7),
0 | (1<<0) | (1<<1),
0,
0 | (1<<1) | (1<<2),
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0 | (1<<3) | (1<<4) | (1<<5),
0,
0,
0,
0 | (1<<3),
0,
0,
0 | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5) | (1<<6) | (1<<7),
0 | (1<<0) | (1<<1),
0,
0,
0,
0,
0,
0,
0,
0,
0 | (1<<2) | (1<<4) | (1<<5),
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0 | (1<<3) | (1<<4), 0 | (1<<3),
0 | (1<<1) | (1<<2) | (1<<3),
0, 0,
0, 0,
0, 0,
0, 0,
0 | (1<<0) | (1<<4) | (1<<5),
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0 | (1<<0) | (1<<1) | (1<<6) | (1<<7),
0 | (1<<0),
0,
0,
0,
0,
0,
0,
0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
skipping to change at line 4060 skipping to change at line 5304
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0 | (1<<4), 0,
0 | (1<<1) | (1<<2) | (1<<3), 0,
0,
0 | (1<<7),
0 | (1<<4) | (1<<5) | (1<<6),
0 | (1<<3) | (1<<4) | (1<<5) | (1<<6) | (1<<7),
0 | (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5) | (1<<6) | (1<<7) , 0 | (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5) | (1<<6) | (1<<7) ,
0 | (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5) | (1<<6) | (1<<7) , 0 | (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5) | (1<<6) | (1<<7) ,
0 | (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5) | (1<<6), 0 | (1<<0) | (1<<1) | (1<<3) | (1<<4) | (1<<5) | (1<<7),
0 | (1<<0) | (1<<1) | (1<<2) | (1<<4) | (1<<5), 0 | (1<<0) | (1<<3) | (1<<4) | (1<<5)
0 | (1<<0) | (1<<1) | (1<<2)
}; };
return (OTable[id/8] & (1 << (id%8))) != 0; return (OTable[id/8] & (1 << (id%8))) != 0;
#endif #endif
// Function name -> enum value recognizer code. // Function name -> enum value recognizer code.
#ifdef GET_FUNCTION_RECOGNIZER #ifdef GET_FUNCTION_RECOGNIZER
StringRef NameR(Name+6, Len-6); // Skip over 'llvm.' StringRef NameR(Name+6, Len-6); // Skip over 'llvm.'
switch (Name[5]) { // Dispatch on first letter. switch (Name[5]) { // Dispatch on first letter.
default: break; default: break;
case 'a': case 'a':
if (NameR.startswith("nnotation.")) return Intrinsic::annotation; if (NameR.startswith("nnotation.")) return Intrinsic::annotation;
if (NameR.startswith("rm.neon.vabds.")) return Intrinsic::arm_neon_vabd s; if (NameR.startswith("rm.neon.vabds.")) return Intrinsic::arm_neon_vabd s;
if (NameR.startswith("rm.neon.vabdu.")) return Intrinsic::arm_neon_vabd u; if (NameR.startswith("rm.neon.vabdu.")) return Intrinsic::arm_neon_vabd u;
if (NameR.startswith("rm.neon.vabs.")) return Intrinsic::arm_neon_vabs; if (NameR.startswith("rm.neon.vabs.")) return Intrinsic::arm_neon_vabs;
if (NameR.startswith("rm.neon.vaddhn.")) return Intrinsic::arm_neon_vad dhn; if (NameR.startswith("rm.neon.vaddhn.")) return Intrinsic::arm_neon_vad dhn;
if (NameR.startswith("rm.neon.vbsl.")) return Intrinsic::arm_neon_vbsl;
if (NameR.startswith("rm.neon.vcls.")) return Intrinsic::arm_neon_vcls; if (NameR.startswith("rm.neon.vcls.")) return Intrinsic::arm_neon_vcls;
if (NameR.startswith("rm.neon.vclz.")) return Intrinsic::arm_neon_vclz; if (NameR.startswith("rm.neon.vclz.")) return Intrinsic::arm_neon_vclz;
if (NameR.startswith("rm.neon.vcnt.")) return Intrinsic::arm_neon_vcnt; if (NameR.startswith("rm.neon.vcnt.")) return Intrinsic::arm_neon_vcnt;
if (NameR.startswith("rm.neon.vcvtfp2fxs.")) return Intrinsic::arm_neon _vcvtfp2fxs; if (NameR.startswith("rm.neon.vcvtfp2fxs.")) return Intrinsic::arm_neon _vcvtfp2fxs;
if (NameR.startswith("rm.neon.vcvtfp2fxu.")) return Intrinsic::arm_neon _vcvtfp2fxu; if (NameR.startswith("rm.neon.vcvtfp2fxu.")) return Intrinsic::arm_neon _vcvtfp2fxu;
if (NameR.startswith("rm.neon.vcvtfxs2fp.")) return Intrinsic::arm_neon _vcvtfxs2fp; if (NameR.startswith("rm.neon.vcvtfxs2fp.")) return Intrinsic::arm_neon _vcvtfxs2fp;
if (NameR.startswith("rm.neon.vcvtfxu2fp.")) return Intrinsic::arm_neon _vcvtfxu2fp; if (NameR.startswith("rm.neon.vcvtfxu2fp.")) return Intrinsic::arm_neon _vcvtfxu2fp;
if (NameR.startswith("rm.neon.vhadds.")) return Intrinsic::arm_neon_vha dds; if (NameR.startswith("rm.neon.vhadds.")) return Intrinsic::arm_neon_vha dds;
if (NameR.startswith("rm.neon.vhaddu.")) return Intrinsic::arm_neon_vha ddu; if (NameR.startswith("rm.neon.vhaddu.")) return Intrinsic::arm_neon_vha ddu;
if (NameR.startswith("rm.neon.vhsubs.")) return Intrinsic::arm_neon_vhs ubs; if (NameR.startswith("rm.neon.vhsubs.")) return Intrinsic::arm_neon_vhs ubs;
skipping to change at line 4173 skipping to change at line 5421
if (NameR.startswith("rm.neon.vst3.")) return Intrinsic::arm_neon_vst3; if (NameR.startswith("rm.neon.vst3.")) return Intrinsic::arm_neon_vst3;
if (NameR.startswith("rm.neon.vst3lane.")) return Intrinsic::arm_neon_v st3lane; if (NameR.startswith("rm.neon.vst3lane.")) return Intrinsic::arm_neon_v st3lane;
if (NameR.startswith("rm.neon.vst4.")) return Intrinsic::arm_neon_vst4; if (NameR.startswith("rm.neon.vst4.")) return Intrinsic::arm_neon_vst4;
if (NameR.startswith("rm.neon.vst4lane.")) return Intrinsic::arm_neon_v st4lane; if (NameR.startswith("rm.neon.vst4lane.")) return Intrinsic::arm_neon_v st4lane;
if (NameR.startswith("rm.neon.vsubhn.")) return Intrinsic::arm_neon_vsu bhn; if (NameR.startswith("rm.neon.vsubhn.")) return Intrinsic::arm_neon_vsu bhn;
if (NameR.startswith("rm.vcvtr.")) return Intrinsic::arm_vcvtr; if (NameR.startswith("rm.vcvtr.")) return Intrinsic::arm_vcvtr;
if (NameR.startswith("rm.vcvtru.")) return Intrinsic::arm_vcvtru; if (NameR.startswith("rm.vcvtru.")) return Intrinsic::arm_vcvtru;
switch (NameR.size()) { switch (NameR.size()) {
default: break; default: break;
case 6: // 3 strings to match. case 6: // 3 strings to match.
if (NameR.substr(0, 3) != "rm.") if (memcmp(NameR.data()+0, "rm.", 3))
break; break;
switch (NameR[3]) { switch (NameR[3]) {
default: break; default: break;
case 'c': // 1 string to match. case 'c': // 1 string to match.
if (NameR.substr(4, 2) != "dp") if (memcmp(NameR.data()+4, "dp", 2))
break; break;
return Intrinsic::arm_cdp; // "rm.cdp" return Intrinsic::arm_cdp; // "rm.cdp"
case 'm': // 2 strings to match. case 'm': // 2 strings to match.
switch (NameR[4]) { switch (NameR[4]) {
default: break; default: break;
case 'c': // 1 string to match. case 'c': // 1 string to match.
if (NameR[5] != 'r') if (NameR[5] != 'r')
break; break;
return Intrinsic::arm_mcr; // "rm.mcr" return Intrinsic::arm_mcr; // "rm.mcr"
case 'r': // 1 string to match. case 'r': // 1 string to match.
if (NameR[5] != 'c') if (NameR[5] != 'c')
break; break;
return Intrinsic::arm_mrc; // "rm.mrc" return Intrinsic::arm_mrc; // "rm.mrc"
} }
break; break;
} }
break; break;
case 7: // 8 strings to match. case 7: // 8 strings to match.
if (NameR.substr(0, 3) != "rm.") if (memcmp(NameR.data()+0, "rm.", 3))
break; break;
switch (NameR[3]) { switch (NameR[3]) {
default: break; default: break;
case 'c': // 1 string to match. case 'c': // 1 string to match.
if (NameR.substr(4, 3) != "dp2") if (memcmp(NameR.data()+4, "dp2", 3))
break; break;
return Intrinsic::arm_cdp2; // "rm.cdp2" return Intrinsic::arm_cdp2; // "rm.cdp2"
case 'm': // 3 strings to match. case 'm': // 3 strings to match.
switch (NameR[4]) { switch (NameR[4]) {
default: break; default: break;
case 'c': // 2 strings to match. case 'c': // 2 strings to match.
if (NameR[5] != 'r') if (NameR[5] != 'r')
break; break;
switch (NameR[6]) { switch (NameR[6]) {
default: break; default: break;
case '2': // 1 string to match. case '2': // 1 string to match.
return Intrinsic::arm_mcr2; // "rm.mcr2" return Intrinsic::arm_mcr2; // "rm.mcr2"
case 'r': // 1 string to match. case 'r': // 1 string to match.
return Intrinsic::arm_mcrr; // "rm.mcrr" return Intrinsic::arm_mcrr; // "rm.mcrr"
} }
break; break;
case 'r': // 1 string to match. case 'r': // 1 string to match.
if (NameR.substr(5, 2) != "c2") if (memcmp(NameR.data()+5, "c2", 2))
break; break;
return Intrinsic::arm_mrc2; // "rm.mrc2" return Intrinsic::arm_mrc2; // "rm.mrc2"
} }
break; break;
case 'q': // 2 strings to match. case 'q': // 2 strings to match.
switch (NameR[4]) { switch (NameR[4]) {
default: break; default: break;
case 'a': // 1 string to match. case 'a': // 1 string to match.
if (NameR.substr(5, 2) != "dd") if (memcmp(NameR.data()+5, "dd", 2))
break; break;
return Intrinsic::arm_qadd; // "rm.qadd" return Intrinsic::arm_qadd; // "rm.qadd"
case 's': // 1 string to match. case 's': // 1 string to match.
if (NameR.substr(5, 2) != "ub") if (memcmp(NameR.data()+5, "ub", 2))
break; break;
return Intrinsic::arm_qsub; // "rm.qsub" return Intrinsic::arm_qsub; // "rm.qsub"
} }
break; break;
case 's': // 1 string to match. case 's': // 1 string to match.
if (NameR.substr(4, 3) != "sat") if (memcmp(NameR.data()+4, "sat", 3))
break; break;
return Intrinsic::arm_ssat; // "rm.ssat" return Intrinsic::arm_ssat; // "rm.ssat"
case 'u': // 1 string to match. case 'u': // 1 string to match.
if (NameR.substr(4, 3) != "sat") if (memcmp(NameR.data()+4, "sat", 3))
break; break;
return Intrinsic::arm_usat; // "rm.usat" return Intrinsic::arm_usat; // "rm.usat"
} }
break; break;
case 8: // 1 string to match. case 8: // 1 string to match.
if (NameR.substr(0, 8) != "rm.mcrr2") if (memcmp(NameR.data()+0, "rm.mcrr2", 8))
break; break;
return Intrinsic::arm_mcrr2; // "rm.mcrr2" return Intrinsic::arm_mcrr2; // "rm.mcrr2"
case 9: // 2 strings to match. case 9: // 2 strings to match.
if (NameR.substr(0, 3) != "rm.") if (memcmp(NameR.data()+0, "rm.", 3))
break; break;
switch (NameR[3]) { switch (NameR[3]) {
default: break; default: break;
case 'l': // 1 string to match. case 'l': // 1 string to match.
if (NameR.substr(4, 5) != "drexd") if (memcmp(NameR.data()+4, "drexd", 5))
break; break;
return Intrinsic::arm_ldrexd; // "rm.ldrexd" return Intrinsic::arm_ldrexd; // "rm.ldrexd"
case 's': // 1 string to match. case 's': // 1 string to match.
if (NameR.substr(4, 5) != "trexd") if (memcmp(NameR.data()+4, "trexd", 5))
break; break;
return Intrinsic::arm_strexd; // "rm.strexd" return Intrinsic::arm_strexd; // "rm.strexd"
} }
break; break;
case 12: // 2 strings to match. case 12: // 2 strings to match.
if (NameR.substr(0, 3) != "rm.") if (memcmp(NameR.data()+0, "rm.", 3))
break; break;
switch (NameR[3]) { switch (NameR[3]) {
default: break; default: break;
case 'g': // 1 string to match. case 'g': // 1 string to match.
if (NameR.substr(4, 8) != "et.fpscr") if (memcmp(NameR.data()+4, "et.fpscr", 8))
break; break;
return Intrinsic::arm_get_fpscr; // "rm.get.fpscr" return Intrinsic::arm_get_fpscr; // "rm.get.fpscr"
case 's': // 1 string to match. case 's': // 1 string to match.
if (NameR.substr(4, 8) != "et.fpscr") if (memcmp(NameR.data()+4, "et.fpscr", 8))
break; break;
return Intrinsic::arm_set_fpscr; // "rm.set.fpscr" return Intrinsic::arm_set_fpscr; // "rm.set.fpscr"
} }
break; break;
case 13: // 8 strings to match. case 13: // 8 strings to match.
if (NameR.substr(0, 11) != "rm.neon.vtb") if (memcmp(NameR.data()+0, "rm.neon.vtb", 11))
break; break;
switch (NameR[11]) { switch (NameR[11]) {
default: break; default: break;
case 'l': // 4 strings to match. case 'l': // 4 strings to match.
switch (NameR[12]) { switch (NameR[12]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
return Intrinsic::arm_neon_vtbl1; // "rm.neon.vtbl1" return Intrinsic::arm_neon_vtbl1; // "rm.neon.vtbl1"
case '2': // 1 string to match. case '2': // 1 string to match.
return Intrinsic::arm_neon_vtbl2; // "rm.neon.vtbl2" return Intrinsic::arm_neon_vtbl2; // "rm.neon.vtbl2"
skipping to change at line 4316 skipping to change at line 5564
return Intrinsic::arm_neon_vtbx2; // "rm.neon.vtbx2" return Intrinsic::arm_neon_vtbx2; // "rm.neon.vtbx2"
case '3': // 1 string to match. case '3': // 1 string to match.
return Intrinsic::arm_neon_vtbx3; // "rm.neon.vtbx3" return Intrinsic::arm_neon_vtbx3; // "rm.neon.vtbx3"
case '4': // 1 string to match. case '4': // 1 string to match.
return Intrinsic::arm_neon_vtbx4; // "rm.neon.vtbx4" return Intrinsic::arm_neon_vtbx4; // "rm.neon.vtbx4"
} }
break; break;
} }
break; break;
case 14: // 4 strings to match. case 14: // 4 strings to match.
if (NameR.substr(0, 12) != "rm.neon.vacg") if (memcmp(NameR.data()+0, "rm.neon.vacg", 12))
break; break;
switch (NameR[12]) { switch (NameR[12]) {
default: break; default: break;
case 'e': // 2 strings to match. case 'e': // 2 strings to match.
switch (NameR[13]) { switch (NameR[13]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
return Intrinsic::arm_neon_vacged; // "rm.neon.vacged" return Intrinsic::arm_neon_vacged; // "rm.neon.vacged"
case 'q': // 1 string to match. case 'q': // 1 string to match.
return Intrinsic::arm_neon_vacgeq; // "rm.neon.vacgeq" return Intrinsic::arm_neon_vacgeq; // "rm.neon.vacgeq"
skipping to change at line 4341 skipping to change at line 5589
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
return Intrinsic::arm_neon_vacgtd; // "rm.neon.vacgtd" return Intrinsic::arm_neon_vacgtd; // "rm.neon.vacgtd"
case 'q': // 1 string to match. case 'q': // 1 string to match.
return Intrinsic::arm_neon_vacgtq; // "rm.neon.vacgtq" return Intrinsic::arm_neon_vacgtq; // "rm.neon.vacgtq"
} }
break; break;
} }
break; break;
case 16: // 1 string to match. case 16: // 1 string to match.
if (NameR.substr(0, 16) != "djust.trampoline") if (memcmp(NameR.data()+0, "djust.trampoline", 16))
break; break;
return Intrinsic::adjust_trampoline; // "djust.trampoline" return Intrinsic::adjust_trampoline; // "djust.trampoline"
case 17: // 3 strings to match. case 17: // 3 strings to match.
if (NameR.substr(0, 3) != "rm.") if (memcmp(NameR.data()+0, "rm.", 3))
break; break;
switch (NameR[3]) { switch (NameR[3]) {
default: break; default: break;
case 'n': // 2 strings to match. case 'n': // 2 strings to match.
if (NameR.substr(4, 8) != "eon.vcvt") if (memcmp(NameR.data()+4, "eon.vcvt", 8))
break; break;
switch (NameR[12]) { switch (NameR[12]) {
default: break; default: break;
case 'f': // 1 string to match. case 'f': // 1 string to match.
if (NameR.substr(13, 4) != "p2hf") if (memcmp(NameR.data()+13, "p2hf", 4))
break; break;
return Intrinsic::arm_neon_vcvtfp2hf; // "rm.neon.vcvtfp2 hf" return Intrinsic::arm_neon_vcvtfp2hf; // "rm.neon.vcvtfp2 hf"
case 'h': // 1 string to match. case 'h': // 1 string to match.
if (NameR.substr(13, 4) != "f2fp") if (memcmp(NameR.data()+13, "f2fp", 4))
break; break;
return Intrinsic::arm_neon_vcvthf2fp; // "rm.neon.vcvthf2 fp" return Intrinsic::arm_neon_vcvthf2fp; // "rm.neon.vcvthf2 fp"
} }
break; break;
case 't': // 1 string to match. case 't': // 1 string to match.
if (NameR.substr(4, 13) != "hread.pointer") if (memcmp(NameR.data()+4, "hread.pointer", 13))
break; break;
return Intrinsic::arm_thread_pointer; // "rm.thread.pointer" return Intrinsic::arm_thread_pointer; // "rm.thread.pointer"
} }
break; break;
} }
break; // end of 'a' case. break; // end of 'a' case.
case 'b': case 'b':
if (NameR.startswith("swap.")) return Intrinsic::bswap; if (NameR.startswith("swap.")) return Intrinsic::bswap;
break; // end of 'b' case. break; // end of 'b' case.
case 'c': case 'c':
skipping to change at line 4392 skipping to change at line 5640
if (NameR.startswith("onvertuif.")) return Intrinsic::convertuif; if (NameR.startswith("onvertuif.")) return Intrinsic::convertuif;
if (NameR.startswith("onvertus.")) return Intrinsic::convertus; if (NameR.startswith("onvertus.")) return Intrinsic::convertus;
if (NameR.startswith("onvertuu.")) return Intrinsic::convertuu; if (NameR.startswith("onvertuu.")) return Intrinsic::convertuu;
if (NameR.startswith("os.")) return Intrinsic::cos; if (NameR.startswith("os.")) return Intrinsic::cos;
if (NameR.startswith("tlz.")) return Intrinsic::ctlz; if (NameR.startswith("tlz.")) return Intrinsic::ctlz;
if (NameR.startswith("tpop.")) return Intrinsic::ctpop; if (NameR.startswith("tpop.")) return Intrinsic::ctpop;
if (NameR.startswith("ttz.")) return Intrinsic::cttz; if (NameR.startswith("ttz.")) return Intrinsic::cttz;
switch (NameR.size()) { switch (NameR.size()) {
default: break; default: break;
case 14: // 1 string to match. case 14: // 1 string to match.
if (NameR.substr(0, 14) != "onvert.to.fp16") if (memcmp(NameR.data()+0, "onvert.to.fp16", 14))
break; break;
return Intrinsic::convert_to_fp16; // "onvert.to.fp16" return Intrinsic::convert_to_fp16; // "onvert.to.fp16"
case 15: // 1 string to match.
if (memcmp(NameR.data()+0, "uda.syncthreads", 15))
break;
return Intrinsic::cuda_syncthreads; // "uda.syncthreads"
case 16: // 1 string to match. case 16: // 1 string to match.
if (NameR.substr(0, 16) != "onvert.from.fp16") if (memcmp(NameR.data()+0, "onvert.from.fp16", 16))
break; break;
return Intrinsic::convert_from_fp16; // "onvert.from.fp16" return Intrinsic::convert_from_fp16; // "onvert.from.fp16"
} }
break; // end of 'c' case. break; // end of 'c' case.
case 'd': case 'd':
switch (NameR.size()) { switch (NameR.size()) {
default: break; default: break;
case 8: // 1 string to match. case 8: // 3 strings to match.
if (NameR.substr(0, 8) != "bg.value") switch (NameR[0]) {
break; default: break;
return Intrinsic::dbg_value; // "bg.value" case 'b': // 1 string to match.
if (memcmp(NameR.data()+1, "g.value", 7))
break;
return Intrinsic::dbg_value; // "bg.value"
case 'e': // 1 string to match.
if (memcmp(NameR.data()+1, "bugtrap", 7))
break;
return Intrinsic::debugtrap; // "ebugtrap"
case 'o': // 1 string to match.
if (memcmp(NameR.data()+1, "nothing", 7))
break;
return Intrinsic::donothing; // "onothing"
}
break;
case 10: // 1 string to match. case 10: // 1 string to match.
if (NameR.substr(0, 10) != "bg.declare") if (memcmp(NameR.data()+0, "bg.declare", 10))
break; break;
return Intrinsic::dbg_declare; // "bg.declare" return Intrinsic::dbg_declare; // "bg.declare"
} }
break; // end of 'd' case. break; // end of 'd' case.
case 'e': case 'e':
if (NameR.startswith("xp.")) return Intrinsic::exp; if (NameR.startswith("xp.")) return Intrinsic::exp;
if (NameR.startswith("xp2.")) return Intrinsic::exp2; if (NameR.startswith("xp2.")) return Intrinsic::exp2;
if (NameR.startswith("xpect.")) return Intrinsic::expect; if (NameR.startswith("xpect.")) return Intrinsic::expect;
switch (NameR.size()) { switch (NameR.size()) {
default: break; default: break;
case 11: // 2 strings to match. case 11: // 2 strings to match.
if (NameR.substr(0, 2) != "h.") if (memcmp(NameR.data()+0, "h.", 2))
break; break;
switch (NameR[2]) { switch (NameR[2]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
if (NameR.substr(3, 8) != "warf.cfa") if (memcmp(NameR.data()+3, "warf.cfa", 8))
break; break;
return Intrinsic::eh_dwarf_cfa; // "h.dwarf.cfa" return Intrinsic::eh_dwarf_cfa; // "h.dwarf.cfa"
case 's': // 1 string to match. case 's': // 1 string to match.
if (NameR.substr(3, 8) != "jlj.lsda") if (memcmp(NameR.data()+3, "jlj.lsda", 8))
break; break;
return Intrinsic::eh_sjlj_lsda; // "h.sjlj.lsda" return Intrinsic::eh_sjlj_lsda; // "h.sjlj.lsda"
} }
break; break;
case 12: // 3 strings to match. case 12: // 3 strings to match.
if (NameR.substr(0, 2) != "h.") if (memcmp(NameR.data()+0, "h.", 2))
break; break;
switch (NameR[2]) { switch (NameR[2]) {
default: break; default: break;
case 'r': // 2 strings to match. case 'r': // 2 strings to match.
if (NameR.substr(3, 7) != "eturn.i") if (memcmp(NameR.data()+3, "eturn.i", 7))
break; break;
switch (NameR[10]) { switch (NameR[10]) {
default: break; default: break;
case '3': // 1 string to match. case '3': // 1 string to match.
if (NameR[11] != '2') if (NameR[11] != '2')
break; break;
return Intrinsic::eh_return_i32; // "h.return.i32" return Intrinsic::eh_return_i32; // "h.return.i32"
case '6': // 1 string to match. case '6': // 1 string to match.
if (NameR[11] != '4') if (NameR[11] != '4')
break; break;
return Intrinsic::eh_return_i64; // "h.return.i64" return Intrinsic::eh_return_i64; // "h.return.i64"
} }
break; break;
case 't': // 1 string to match. case 't': // 1 string to match.
if (NameR.substr(3, 9) != "ypeid.for") if (memcmp(NameR.data()+3, "ypeid.for", 9))
break; break;
return Intrinsic::eh_typeid_for; // "h.typeid.for" return Intrinsic::eh_typeid_for; // "h.typeid.for"
} }
break; break;
case 13: // 2 strings to match. case 13: // 2 strings to match.
if (NameR.substr(0, 2) != "h.") if (memcmp(NameR.data()+0, "h.", 2))
break; break;
switch (NameR[2]) { switch (NameR[2]) {
default: break; default: break;
case 's': // 1 string to match. case 's': // 1 string to match.
if (NameR.substr(3, 10) != "jlj.setjmp") if (memcmp(NameR.data()+3, "jlj.setjmp", 10))
break; break;
return Intrinsic::eh_sjlj_setjmp; // "h.sjlj.setjmp" return Intrinsic::eh_sjlj_setjmp; // "h.sjlj.setjmp"
case 'u': // 1 string to match. case 'u': // 1 string to match.
if (NameR.substr(3, 10) != "nwind.init") if (memcmp(NameR.data()+3, "nwind.init", 10))
break; break;
return Intrinsic::eh_unwind_init; // "h.unwind.init" return Intrinsic::eh_unwind_init; // "h.unwind.init"
} }
break; break;
case 14: // 1 string to match. case 14: // 1 string to match.
if (NameR.substr(0, 14) != "h.sjlj.longjmp") if (memcmp(NameR.data()+0, "h.sjlj.longjmp", 14))
break; break;
return Intrinsic::eh_sjlj_longjmp; // "h.sjlj.longjmp" return Intrinsic::eh_sjlj_longjmp; // "h.sjlj.longjmp"
case 15: // 1 string to match. case 15: // 1 string to match.
if (NameR.substr(0, 15) != "h.sjlj.callsite") if (memcmp(NameR.data()+0, "h.sjlj.callsite", 15))
break; break;
return Intrinsic::eh_sjlj_callsite; // "h.sjlj.callsite" return Intrinsic::eh_sjlj_callsite; // "h.sjlj.callsite"
case 22: // 1 string to match. case 22: // 1 string to match.
if (NameR.substr(0, 22) != "h.sjlj.functioncontext") if (memcmp(NameR.data()+0, "h.sjlj.functioncontext", 22))
break; break;
return Intrinsic::eh_sjlj_functioncontext; // "h.sjlj.function context" return Intrinsic::eh_sjlj_functioncontext; // "h.sjlj.function context"
} }
break; // end of 'e' case. break; // end of 'e' case.
case 'f': case 'f':
if (NameR.startswith("abs.")) return Intrinsic::fabs;
if (NameR.startswith("loor.")) return Intrinsic::floor;
if (NameR.startswith("ma.")) return Intrinsic::fma; if (NameR.startswith("ma.")) return Intrinsic::fma;
if (NameR.startswith("muladd.")) return Intrinsic::fmuladd;
switch (NameR.size()) { switch (NameR.size()) {
default: break; default: break;
case 9: // 1 string to match. case 9: // 1 string to match.
if (NameR.substr(0, 9) != "lt.rounds") if (memcmp(NameR.data()+0, "lt.rounds", 9))
break; break;
return Intrinsic::flt_rounds; // "lt.rounds" return Intrinsic::flt_rounds; // "lt.rounds"
case 11: // 1 string to match. case 11: // 1 string to match.
if (NameR.substr(0, 11) != "rameaddress") if (memcmp(NameR.data()+0, "rameaddress", 11))
break; break;
return Intrinsic::frameaddress; // "rameaddress" return Intrinsic::frameaddress; // "rameaddress"
} }
break; // end of 'f' case. break; // end of 'f' case.
case 'g': case 'g':
switch (NameR.size()) { switch (NameR.size()) {
default: break; default: break;
case 5: // 2 strings to match. case 5: // 2 strings to match.
if (NameR.substr(0, 2) != "cr") if (memcmp(NameR.data()+0, "cr", 2))
break; break;
switch (NameR[2]) { switch (NameR[2]) {
default: break; default: break;
case 'e': // 1 string to match. case 'e': // 1 string to match.
if (NameR.substr(3, 2) != "ad") if (memcmp(NameR.data()+3, "ad", 2))
break; break;
return Intrinsic::gcread; // "cread" return Intrinsic::gcread; // "cread"
case 'o': // 1 string to match. case 'o': // 1 string to match.
if (NameR.substr(3, 2) != "ot") if (memcmp(NameR.data()+3, "ot", 2))
break; break;
return Intrinsic::gcroot; // "croot" return Intrinsic::gcroot; // "croot"
} }
break; break;
case 6: // 1 string to match. case 6: // 1 string to match.
if (NameR.substr(0, 6) != "cwrite") if (memcmp(NameR.data()+0, "cwrite", 6))
break; break;
return Intrinsic::gcwrite; // "cwrite" return Intrinsic::gcwrite; // "cwrite"
} }
break; // end of 'g' case. break; // end of 'g' case.
case 'h': case 'h':
switch (NameR.size()) { switch (NameR.size()) {
default: break; default: break;
case 12: // 2 strings to match. case 12: // 2 strings to match.
if (NameR.substr(0, 7) != "exagon.") if (memcmp(NameR.data()+0, "exagon.", 7))
break; break;
switch (NameR[7]) { switch (NameR[7]) {
default: break; default: break;
case 'A': // 1 string to match. case 'A': // 1 string to match.
if (NameR.substr(8, 4) != "2.or") if (memcmp(NameR.data()+8, "2.or", 4))
break; break;
return Intrinsic::hexagon_A2_or; // "exagon.A2.or" return Intrinsic::hexagon_A2_or; // "exagon.A2.or"
case 'C': // 1 string to match. case 'C': // 1 string to match.
if (NameR.substr(8, 4) != "2.or") if (memcmp(NameR.data()+8, "2.or", 4))
break; break;
return Intrinsic::hexagon_C2_or; // "exagon.C2.or" return Intrinsic::hexagon_C2_or; // "exagon.C2.or"
} }
break; break;
case 13: // 23 strings to match. case 13: // 23 strings to match.
if (NameR.substr(0, 7) != "exagon.") if (memcmp(NameR.data()+0, "exagon.", 7))
break; break;
switch (NameR[7]) { switch (NameR[7]) {
default: break; default: break;
case 'A': // 13 strings to match. case 'A': // 13 strings to match.
switch (NameR[8]) { switch (NameR[8]) {
default: break; default: break;
case '2': // 12 strings to match. case '2': // 12 strings to match.
if (NameR[9] != '.') if (NameR[9] != '.')
break; break;
switch (NameR[10]) { switch (NameR[10]) {
skipping to change at line 4603 skipping to change at line 5871
if (NameR[12] != 'g') if (NameR[12] != 'g')
break; break;
return Intrinsic::hexagon_A2_neg; // "exagon.A2.neg" return Intrinsic::hexagon_A2_neg; // "exagon.A2.neg"
case 'o': // 1 string to match. case 'o': // 1 string to match.
if (NameR[12] != 't') if (NameR[12] != 't')
break; break;
return Intrinsic::hexagon_A2_not; // "exagon.A2.not" return Intrinsic::hexagon_A2_not; // "exagon.A2.not"
} }
break; break;
case 'o': // 1 string to match. case 'o': // 1 string to match.
if (NameR.substr(11, 2) != "rp") if (memcmp(NameR.data()+11, "rp", 2))
break; break;
return Intrinsic::hexagon_A2_orp; // "exagon.A2.orp" return Intrinsic::hexagon_A2_orp; // "exagon.A2.orp"
case 's': // 2 strings to match. case 's': // 2 strings to match.
switch (NameR[11]) { switch (NameR[11]) {
default: break; default: break;
case 'a': // 1 string to match. case 'a': // 1 string to match.
if (NameR[12] != 't') if (NameR[12] != 't')
break; break;
return Intrinsic::hexagon_A2_sat; // "exagon.A2.sat" return Intrinsic::hexagon_A2_sat; // "exagon.A2.sat"
case 'u': // 1 string to match. case 'u': // 1 string to match.
if (NameR[12] != 'b') if (NameR[12] != 'b')
break; break;
return Intrinsic::hexagon_A2_sub; // "exagon.A2.sub" return Intrinsic::hexagon_A2_sub; // "exagon.A2.sub"
} }
break; break;
case 't': // 1 string to match. case 't': // 1 string to match.
if (NameR.substr(11, 2) != "fr") if (memcmp(NameR.data()+11, "fr", 2))
break; break;
return Intrinsic::hexagon_A2_tfr; // "exagon.A2.tfr" return Intrinsic::hexagon_A2_tfr; // "exagon.A2.tfr"
case 'x': // 1 string to match. case 'x': // 1 string to match.
if (NameR.substr(11, 2) != "or") if (memcmp(NameR.data()+11, "or", 2))
break; break;
return Intrinsic::hexagon_A2_xor; // "exagon.A2.xor" return Intrinsic::hexagon_A2_xor; // "exagon.A2.xor"
} }
break; break;
case '4': // 1 string to match. case '4': // 1 string to match.
if (NameR.substr(9, 4) != ".orn") if (memcmp(NameR.data()+9, ".orn", 4))
break; break;
return Intrinsic::hexagon_A4_orn; // "exagon.A4.orn" return Intrinsic::hexagon_A4_orn; // "exagon.A4.orn"
} }
break; break;
case 'C': // 5 strings to match. case 'C': // 5 strings to match.
if (NameR.substr(8, 2) != "2.") if (memcmp(NameR.data()+8, "2.", 2))
break; break;
switch (NameR[10]) { switch (NameR[10]) {
default: break; default: break;
case 'a': // 1 string to match. case 'a': // 1 string to match.
if (NameR.substr(11, 2) != "nd") if (memcmp(NameR.data()+11, "nd", 2))
break; break;
return Intrinsic::hexagon_C2_and; // "exagon.C2.and" return Intrinsic::hexagon_C2_and; // "exagon.C2.and"
case 'm': // 1 string to match. case 'm': // 1 string to match.
if (NameR.substr(11, 2) != "ux") if (memcmp(NameR.data()+11, "ux", 2))
break; break;
return Intrinsic::hexagon_C2_mux; // "exagon.C2.mux" return Intrinsic::hexagon_C2_mux; // "exagon.C2.mux"
case 'n': // 1 string to match. case 'n': // 1 string to match.
if (NameR.substr(11, 2) != "ot") if (memcmp(NameR.data()+11, "ot", 2))
break; break;
return Intrinsic::hexagon_C2_not; // "exagon.C2.not" return Intrinsic::hexagon_C2_not; // "exagon.C2.not"
case 'o': // 1 string to match. case 'o': // 1 string to match.
if (NameR.substr(11, 2) != "rn") if (memcmp(NameR.data()+11, "rn", 2))
break; break;
return Intrinsic::hexagon_C2_orn; // "exagon.C2.orn" return Intrinsic::hexagon_C2_orn; // "exagon.C2.orn"
case 'x': // 1 string to match. case 'x': // 1 string to match.
if (NameR.substr(11, 2) != "or") if (memcmp(NameR.data()+11, "or", 2))
break; break;
return Intrinsic::hexagon_C2_xor; // "exagon.C2.xor" return Intrinsic::hexagon_C2_xor; // "exagon.C2.xor"
} }
break; break;
case 'S': // 5 strings to match. case 'S': // 5 strings to match.
if (NameR.substr(8, 3) != "2.c") if (memcmp(NameR.data()+8, "2.c", 3))
break; break;
switch (NameR[11]) { switch (NameR[11]) {
default: break; default: break;
case 'l': // 3 strings to match. case 'l': // 3 strings to match.
switch (NameR[12]) { switch (NameR[12]) {
default: break; default: break;
case '0': // 1 string to match. case '0': // 1 string to match.
return Intrinsic::hexagon_S2_cl0; // "exagon.S2.cl0" return Intrinsic::hexagon_S2_cl0; // "exagon.S2.cl0"
case '1': // 1 string to match. case '1': // 1 string to match.
return Intrinsic::hexagon_S2_cl1; // "exagon.S2.cl1" return Intrinsic::hexagon_S2_cl1; // "exagon.S2.cl1"
skipping to change at line 4691 skipping to change at line 5959
case '0': // 1 string to match. case '0': // 1 string to match.
return Intrinsic::hexagon_S2_ct0; // "exagon.S2.ct0" return Intrinsic::hexagon_S2_ct0; // "exagon.S2.ct0"
case '1': // 1 string to match. case '1': // 1 string to match.
return Intrinsic::hexagon_S2_ct1; // "exagon.S2.ct1" return Intrinsic::hexagon_S2_ct1; // "exagon.S2.ct1"
} }
break; break;
} }
break; break;
} }
break; break;
case 14: // 40 strings to match. case 14: // 42 strings to match.
if (NameR.substr(0, 7) != "exagon.") if (memcmp(NameR.data()+0, "exagon.", 7))
break; break;
switch (NameR[7]) { switch (NameR[7]) {
default: break; default: break;
case 'A': // 26 strings to match. case 'A': // 26 strings to match.
switch (NameR[8]) { switch (NameR[8]) {
default: break; default: break;
case '2': // 24 strings to match. case '2': // 24 strings to match.
if (NameR[9] != '.') if (NameR[9] != '.')
break; break;
switch (NameR[10]) { switch (NameR[10]) {
default: break; default: break;
case 'a': // 6 strings to match. case 'a': // 6 strings to match.
switch (NameR[11]) { switch (NameR[11]) {
default: break; default: break;
case 'b': // 1 string to match. case 'b': // 1 string to match.
if (NameR.substr(12, 2) != "sp") if (memcmp(NameR.data()+12, "sp", 2))
break; break;
return Intrinsic::hexagon_A2_absp; // "exagon.A2.absp" return Intrinsic::hexagon_A2_absp; // "exagon.A2.absp"
case 'd': // 2 strings to match. case 'd': // 2 strings to match.
if (NameR[12] != 'd') if (NameR[12] != 'd')
break; break;
switch (NameR[13]) { switch (NameR[13]) {
default: break; default: break;
case 'i': // 1 string to match. case 'i': // 1 string to match.
return Intrinsic::hexagon_A2_addi; // "exagon.A2.addi" return Intrinsic::hexagon_A2_addi; // "exagon.A2.addi"
case 'p': // 1 string to match. case 'p': // 1 string to match.
return Intrinsic::hexagon_A2_addp; // "exagon.A2.addp" return Intrinsic::hexagon_A2_addp; // "exagon.A2.addp"
} }
break; break;
case 'n': // 1 string to match. case 'n': // 1 string to match.
if (NameR.substr(12, 2) != "dp") if (memcmp(NameR.data()+12, "dp", 2))
break; break;
return Intrinsic::hexagon_A2_andp; // "exagon.A2.andp" return Intrinsic::hexagon_A2_andp; // "exagon.A2.andp"
case 's': // 2 strings to match. case 's': // 2 strings to match.
switch (NameR[12]) { switch (NameR[12]) {
default: break; default: break;
case 'l': // 1 string to match. case 'l': // 1 string to match.
if (NameR[13] != 'h') if (NameR[13] != 'h')
break; break;
return Intrinsic::hexagon_A2_aslh; // "exagon.A2.aslh" return Intrinsic::hexagon_A2_aslh; // "exagon.A2.aslh"
case 'r': // 1 string to match. case 'r': // 1 string to match.
skipping to change at line 4772 skipping to change at line 6040
case 'u': // 1 string to match. case 'u': // 1 string to match.
return Intrinsic::hexagon_A2_minu; // "exagon.A2.minu" return Intrinsic::hexagon_A2_minu; // "exagon.A2.minu"
} }
break; break;
} }
break; break;
case 'n': // 2 strings to match. case 'n': // 2 strings to match.
switch (NameR[11]) { switch (NameR[11]) {
default: break; default: break;
case 'e': // 1 string to match. case 'e': // 1 string to match.
if (NameR.substr(12, 2) != "gp") if (memcmp(NameR.data()+12, "gp", 2))
break; break;
return Intrinsic::hexagon_A2_negp; // "exagon.A2.negp" return Intrinsic::hexagon_A2_negp; // "exagon.A2.negp"
case 'o': // 1 string to match. case 'o': // 1 string to match.
if (NameR.substr(12, 2) != "tp") if (memcmp(NameR.data()+12, "tp", 2))
break; break;
return Intrinsic::hexagon_A2_notp; // "exagon.A2.notp" return Intrinsic::hexagon_A2_notp; // "exagon.A2.notp"
} }
break; break;
case 'o': // 1 string to match. case 'o': // 1 string to match.
if (NameR.substr(11, 3) != "rir") if (memcmp(NameR.data()+11, "rir", 3))
break; break;
return Intrinsic::hexagon_A2_orir; // "exagon.A2.orir" return Intrinsic::hexagon_A2_orir; // "exagon.A2.orir"
case 's': // 7 strings to match. case 's': // 7 strings to match.
switch (NameR[11]) { switch (NameR[11]) {
default: break; default: break;
case 'a': // 2 strings to match. case 'a': // 2 strings to match.
if (NameR[12] != 't') if (NameR[12] != 't')
break; break;
switch (NameR[13]) { switch (NameR[13]) {
default: break; default: break;
case 'b': // 1 string to match. case 'b': // 1 string to match.
return Intrinsic::hexagon_A2_satb; // "exagon.A2.satb" return Intrinsic::hexagon_A2_satb; // "exagon.A2.satb"
case 'h': // 1 string to match. case 'h': // 1 string to match.
return Intrinsic::hexagon_A2_sath; // "exagon.A2.sath" return Intrinsic::hexagon_A2_sath; // "exagon.A2.sath"
} }
break; break;
case 'u': // 1 string to match. case 'u': // 1 string to match.
if (NameR.substr(12, 2) != "bp") if (memcmp(NameR.data()+12, "bp", 2))
break; break;
return Intrinsic::hexagon_A2_subp; // "exagon.A2.subp" return Intrinsic::hexagon_A2_subp; // "exagon.A2.subp"
case 'w': // 1 string to match. case 'w': // 1 string to match.
if (NameR.substr(12, 2) != "iz") if (memcmp(NameR.data()+12, "iz", 2))
break; break;
return Intrinsic::hexagon_A2_swiz; // "exagon.A2.swiz" return Intrinsic::hexagon_A2_swiz; // "exagon.A2.swiz"
case 'x': // 3 strings to match. case 'x': // 3 strings to match.
if (NameR[12] != 't') if (NameR[12] != 't')
break; break;
switch (NameR[13]) { switch (NameR[13]) {
default: break; default: break;
case 'b': // 1 string to match. case 'b': // 1 string to match.
return Intrinsic::hexagon_A2_sxtb; // "exagon.A2.sxtb" return Intrinsic::hexagon_A2_sxtb; // "exagon.A2.sxtb"
case 'h': // 1 string to match. case 'h': // 1 string to match.
return Intrinsic::hexagon_A2_sxth; // "exagon.A2.sxth" return Intrinsic::hexagon_A2_sxth; // "exagon.A2.sxth"
case 'w': // 1 string to match. case 'w': // 1 string to match.
return Intrinsic::hexagon_A2_sxtw; // "exagon.A2.sxtw" return Intrinsic::hexagon_A2_sxtw; // "exagon.A2.sxtw"
} }
break; break;
} }
break; break;
case 't': // 1 string to match. case 't': // 1 string to match.
if (NameR.substr(11, 3) != "frp") if (memcmp(NameR.data()+11, "frp", 3))
break; break;
return Intrinsic::hexagon_A2_tfrp; // "exagon.A2.tfrp" return Intrinsic::hexagon_A2_tfrp; // "exagon.A2.tfrp"
case 'x': // 1 string to match. case 'x': // 1 string to match.
if (NameR.substr(11, 3) != "orp") if (memcmp(NameR.data()+11, "orp", 3))
break; break;
return Intrinsic::hexagon_A2_xorp; // "exagon.A2.xorp" return Intrinsic::hexagon_A2_xorp; // "exagon.A2.xorp"
case 'z': // 2 strings to match. case 'z': // 2 strings to match.
if (NameR.substr(11, 2) != "xt") if (memcmp(NameR.data()+11, "xt", 2))
break; break;
switch (NameR[13]) { switch (NameR[13]) {
default: break; default: break;
case 'b': // 1 string to match. case 'b': // 1 string to match.
return Intrinsic::hexagon_A2_zxtb; // "exagon.A2.zxtb" return Intrinsic::hexagon_A2_zxtb; // "exagon.A2.zxtb"
case 'h': // 1 string to match. case 'h': // 1 string to match.
return Intrinsic::hexagon_A2_zxth; // "exagon.A2.zxth" return Intrinsic::hexagon_A2_zxth; // "exagon.A2.zxth"
} }
break; break;
} }
break; break;
case '4': // 2 strings to match. case '4': // 2 strings to match.
if (NameR[9] != '.') if (NameR[9] != '.')
break; break;
switch (NameR[10]) { switch (NameR[10]) {
default: break; default: break;
case 'a': // 1 string to match. case 'a': // 1 string to match.
if (NameR.substr(11, 3) != "ndn") if (memcmp(NameR.data()+11, "ndn", 3))
break; break;
return Intrinsic::hexagon_A4_andn; // "exagon.A4.andn" return Intrinsic::hexagon_A4_andn; // "exagon.A4.andn"
case 'o': // 1 string to match. case 'o': // 1 string to match.
if (NameR.substr(11, 3) != "rnp") if (memcmp(NameR.data()+11, "rnp", 3))
break; break;
return Intrinsic::hexagon_A4_ornp; // "exagon.A4.ornp" return Intrinsic::hexagon_A4_ornp; // "exagon.A4.ornp"
} }
break; break;
} }
break; break;
case 'C': // 5 strings to match. case 'C': // 5 strings to match.
if (NameR.substr(8, 2) != "2.") if (memcmp(NameR.data()+8, "2.", 2))
break; break;
switch (NameR[10]) { switch (NameR[10]) {
default: break; default: break;
case 'a': // 3 strings to match. case 'a': // 3 strings to match.
switch (NameR[11]) { switch (NameR[11]) {
default: break; default: break;
case 'l': // 1 string to match. case 'l': // 1 string to match.
if (NameR.substr(12, 2) != "l8") if (memcmp(NameR.data()+12, "l8", 2))
break; break;
return Intrinsic::hexagon_C2_all8; // "exagon.C2.all8" return Intrinsic::hexagon_C2_all8; // "exagon.C2.all8"
case 'n': // 2 strings to match. case 'n': // 2 strings to match.
switch (NameR[12]) { switch (NameR[12]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
if (NameR[13] != 'n') if (NameR[13] != 'n')
break; break;
return Intrinsic::hexagon_C2_andn; // "exagon.C2.andn" return Intrinsic::hexagon_C2_andn; // "exagon.C2.andn"
case 'y': // 1 string to match. case 'y': // 1 string to match.
if (NameR[13] != '8') if (NameR[13] != '8')
break; break;
return Intrinsic::hexagon_C2_any8; // "exagon.C2.any8" return Intrinsic::hexagon_C2_any8; // "exagon.C2.any8"
} }
break; break;
} }
break; break;
case 'm': // 1 string to match. case 'm': // 1 string to match.
if (NameR.substr(11, 3) != "ask") if (memcmp(NameR.data()+11, "ask", 3))
break; break;
return Intrinsic::hexagon_C2_mask; // "exagon.C2.mask" return Intrinsic::hexagon_C2_mask; // "exagon.C2.mask"
case 'v': // 1 string to match. case 'v': // 1 string to match.
if (NameR.substr(11, 3) != "mux") if (memcmp(NameR.data()+11, "mux", 3))
break; break;
return Intrinsic::hexagon_C2_vmux; // "exagon.C2.vmux" return Intrinsic::hexagon_C2_vmux; // "exagon.C2.vmux"
} }
break; break;
case 'M': // 3 strings to match. case 'M': // 3 strings to match.
if (NameR.substr(8, 2) != "2.") if (memcmp(NameR.data()+8, "2.", 2))
break; break;
switch (NameR[10]) { switch (NameR[10]) {
default: break; default: break;
case 'a': // 1 string to match. case 'a': // 1 string to match.
if (NameR.substr(11, 3) != "cci") if (memcmp(NameR.data()+11, "cci", 3))
break; break;
return Intrinsic::hexagon_M2_acci; // "exagon.M2.acci" return Intrinsic::hexagon_M2_acci; // "exagon.M2.acci"
case 'm': // 2 strings to match. case 'm': // 2 strings to match.
switch (NameR[11]) { switch (NameR[11]) {
default: break; default: break;
case 'a': // 1 string to match. case 'a': // 1 string to match.
if (NameR.substr(12, 2) != "ci") if (memcmp(NameR.data()+12, "ci", 2))
break; break;
return Intrinsic::hexagon_M2_maci; // "exagon.M2.maci" return Intrinsic::hexagon_M2_maci; // "exagon.M2.maci"
case 'p': // 1 string to match. case 'p': // 1 string to match.
if (NameR.substr(12, 2) != "yi") if (memcmp(NameR.data()+12, "yi", 2))
break; break;
return Intrinsic::hexagon_M2_mpyi; // "exagon.M2.mpyi" return Intrinsic::hexagon_M2_mpyi; // "exagon.M2.mpyi"
} }
break; break;
} }
break; break;
case 'S': // 6 strings to match. case 'S': // 8 strings to match.
switch (NameR[8]) { switch (NameR[8]) {
default: break; default: break;
case '2': // 5 strings to match. case '2': // 7 strings to match.
if (NameR[9] != '.') if (NameR[9] != '.')
break; break;
switch (NameR[10]) { switch (NameR[10]) {
default: break; default: break;
case 'b': // 1 string to match. case 'b': // 1 string to match.
if (NameR.substr(11, 3) != "rev") if (memcmp(NameR.data()+11, "rev", 3))
break; break;
return Intrinsic::hexagon_S2_brev; // "exagon.S2.brev" return Intrinsic::hexagon_S2_brev; // "exagon.S2.brev"
case 'c': // 3 strings to match. case 'c': // 5 strings to match.
if (NameR[11] != 'l') switch (NameR[11]) {
break;
switch (NameR[12]) {
default: break; default: break;
case '0': // 1 string to match. case 'l': // 3 strings to match.
if (NameR[13] != 'p') switch (NameR[12]) {
break; default: break;
return Intrinsic::hexagon_S2_cl0p; // "exagon.S2.cl0p" case '0': // 1 string to match.
case '1': // 1 string to match. if (NameR[13] != 'p')
if (NameR[13] != 'p') break;
break; return Intrinsic::hexagon_S2_cl0p; // "exagon.S2.cl0p"
return Intrinsic::hexagon_S2_cl1p; // "exagon.S2.cl1p" case '1': // 1 string to match.
case 'b': // 1 string to match. if (NameR[13] != 'p')
if (NameR[13] != 'p') break;
break; return Intrinsic::hexagon_S2_cl1p; // "exagon.S2.cl1p"
return Intrinsic::hexagon_S2_clbp; // "exagon.S2.clbp" case 'b': // 1 string to match.
if (NameR[13] != 'p')
break;
return Intrinsic::hexagon_S2_clbp; // "exagon.S2.clbp"
}
break;
case 't': // 2 strings to match.
switch (NameR[12]) {
default: break;
case '0': // 1 string to match.
if (NameR[13] != 'p')
break;
return Intrinsic::hexagon_S2_ct0p; // "exagon.S2.ct0p"
case '1': // 1 string to match.
if (NameR[13] != 'p')
break;
return Intrinsic::hexagon_S2_ct1p; // "exagon.S2.ct1p"
}
break;
} }
break; break;
case 'l': // 1 string to match. case 'l': // 1 string to match.
if (NameR.substr(11, 3) != "fsp") if (memcmp(NameR.data()+11, "fsp", 3))
break; break;
return Intrinsic::hexagon_S2_lfsp; // "exagon.S2.lfsp" return Intrinsic::hexagon_S2_lfsp; // "exagon.S2.lfsp"
} }
break; break;
case '4': // 1 string to match. case '4': // 1 string to match.
if (NameR.substr(9, 5) != ".ornp") if (memcmp(NameR.data()+9, ".lsli", 5))
break; break;
return Intrinsic::hexagon_S4_ornp; // "exagon.S4.ornp" return Intrinsic::hexagon_S4_lsli; // "exagon.S4.lsli"
} }
break; break;
} }
break; break;
case 15: // 40 strings to match. case 15: // 58 strings to match.
if (NameR.substr(0, 7) != "exagon.") if (memcmp(NameR.data()+0, "exagon.", 7))
break; break;
switch (NameR[7]) { switch (NameR[7]) {
default: break; default: break;
case 'A': // 25 strings to match. case 'A': // 27 strings to match.
switch (NameR[8]) { switch (NameR[8]) {
default: break; default: break;
case '2': // 24 strings to match. case '2': // 26 strings to match.
if (NameR[9] != '.') if (NameR[9] != '.')
break; break;
switch (NameR[10]) { switch (NameR[10]) {
default: break; default: break;
case 'a': // 2 strings to match. case 'a': // 2 strings to match.
switch (NameR[11]) { switch (NameR[11]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
if (NameR.substr(12, 3) != "dsp") if (memcmp(NameR.data()+12, "dsp", 3))
break; break;
return Intrinsic::hexagon_A2_addsp; // "exagon.A2.addsp " return Intrinsic::hexagon_A2_addsp; // "exagon.A2.addsp "
case 'n': // 1 string to match. case 'n': // 1 string to match.
if (NameR.substr(12, 3) != "dir") if (memcmp(NameR.data()+12, "dir", 3))
break; break;
return Intrinsic::hexagon_A2_andir; // "exagon.A2.andir " return Intrinsic::hexagon_A2_andir; // "exagon.A2.andir "
} }
break; break;
case 'm': // 2 strings to match. case 'm': // 2 strings to match.
switch (NameR[11]) { switch (NameR[11]) {
default: break; default: break;
case 'a': // 1 string to match. case 'a': // 1 string to match.
if (NameR.substr(12, 3) != "xup") if (memcmp(NameR.data()+12, "xup", 3))
break; break;
return Intrinsic::hexagon_A2_maxup; // "exagon.A2.maxup " return Intrinsic::hexagon_A2_maxup; // "exagon.A2.maxup "
case 'i': // 1 string to match. case 'i': // 1 string to match.
if (NameR.substr(12, 3) != "nup") if (memcmp(NameR.data()+12, "nup", 3))
break; break;
return Intrinsic::hexagon_A2_minup; // "exagon.A2.minup " return Intrinsic::hexagon_A2_minup; // "exagon.A2.minup "
} }
break; break;
case 's': // 3 strings to match. case 's': // 3 strings to match.
switch (NameR[11]) { switch (NameR[11]) {
default: break; default: break;
case 'a': // 2 strings to match. case 'a': // 2 strings to match.
if (NameR.substr(12, 2) != "tu") if (memcmp(NameR.data()+12, "tu", 2))
break; break;
switch (NameR[14]) { switch (NameR[14]) {
default: break; default: break;
case 'b': // 1 string to match. case 'b': // 1 string to match.
return Intrinsic::hexagon_A2_satub; // "exagon.A2.satub " return Intrinsic::hexagon_A2_satub; // "exagon.A2.satub "
case 'h': // 1 string to match. case 'h': // 1 string to match.
return Intrinsic::hexagon_A2_satuh; // "exagon.A2.satuh " return Intrinsic::hexagon_A2_satuh; // "exagon.A2.satuh "
} }
break; break;
case 'u': // 1 string to match. case 'u': // 1 string to match.
if (NameR.substr(12, 3) != "bri") if (memcmp(NameR.data()+12, "bri", 3))
break; break;
return Intrinsic::hexagon_A2_subri; // "exagon.A2.subri " return Intrinsic::hexagon_A2_subri; // "exagon.A2.subri "
} }
break; break;
case 't': // 4 strings to match. case 't': // 4 strings to match.
if (NameR.substr(11, 2) != "fr") if (memcmp(NameR.data()+11, "fr", 2))
break; break;
switch (NameR[13]) { switch (NameR[13]) {
default: break; default: break;
case 'i': // 2 strings to match. case 'i': // 2 strings to match.
switch (NameR[14]) { switch (NameR[14]) {
default: break; default: break;
case 'h': // 1 string to match. case 'h': // 1 string to match.
return Intrinsic::hexagon_A2_tfrih; // "exagon.A2.tfrih " return Intrinsic::hexagon_A2_tfrih; // "exagon.A2.tfrih "
case 'l': // 1 string to match. case 'l': // 1 string to match.
return Intrinsic::hexagon_A2_tfril; // "exagon.A2.tfril " return Intrinsic::hexagon_A2_tfril; // "exagon.A2.tfril "
skipping to change at line 5049 skipping to change at line 6333
case 'p': // 1 string to match. case 'p': // 1 string to match.
if (NameR[14] != 'i') if (NameR[14] != 'i')
break; break;
return Intrinsic::hexagon_A2_tfrpi; // "exagon.A2.tfrpi " return Intrinsic::hexagon_A2_tfrpi; // "exagon.A2.tfrpi "
case 's': // 1 string to match. case 's': // 1 string to match.
if (NameR[14] != 'i') if (NameR[14] != 'i')
break; break;
return Intrinsic::hexagon_A2_tfrsi; // "exagon.A2.tfrsi " return Intrinsic::hexagon_A2_tfrsi; // "exagon.A2.tfrsi "
} }
break; break;
case 'v': // 13 strings to match. case 'v': // 15 strings to match.
switch (NameR[11]) { switch (NameR[11]) {
default: break; default: break;
case 'a': // 6 strings to match. case 'a': // 6 strings to match.
switch (NameR[12]) { switch (NameR[12]) {
default: break; default: break;
case 'b': // 2 strings to match. case 'b': // 2 strings to match.
if (NameR[13] != 's') if (NameR[13] != 's')
break; break;
switch (NameR[14]) { switch (NameR[14]) {
default: break; default: break;
skipping to change at line 5091 skipping to change at line 6375
default: break; default: break;
case 'h': // 1 string to match. case 'h': // 1 string to match.
return Intrinsic::hexagon_A2_vavgh; // "exagon.A2.vavgh " return Intrinsic::hexagon_A2_vavgh; // "exagon.A2.vavgh "
case 'w': // 1 string to match. case 'w': // 1 string to match.
return Intrinsic::hexagon_A2_vavgw; // "exagon.A2.vavgw " return Intrinsic::hexagon_A2_vavgw; // "exagon.A2.vavgw "
} }
break; break;
} }
break; break;
case 'c': // 1 string to match. case 'c': // 1 string to match.
if (NameR.substr(12, 3) != "onj") if (memcmp(NameR.data()+12, "onj", 3))
break; break;
return Intrinsic::hexagon_A2_vconj; // "exagon.A2.vconj " return Intrinsic::hexagon_A2_vconj; // "exagon.A2.vconj "
case 'm': // 4 strings to match. case 'm': // 6 strings to match.
switch (NameR[12]) { switch (NameR[12]) {
default: break; default: break;
case 'a': // 2 strings to match. case 'a': // 3 strings to match.
if (NameR[13] != 'x') if (NameR[13] != 'x')
break; break;
switch (NameR[14]) { switch (NameR[14]) {
default: break; default: break;
case 'b': // 1 string to match.
return Intrinsic::hexagon_A2_vmaxb; // "exagon.A2.vmaxb
"
case 'h': // 1 string to match. case 'h': // 1 string to match.
return Intrinsic::hexagon_A2_vmaxh; // "exagon.A2.vmaxh " return Intrinsic::hexagon_A2_vmaxh; // "exagon.A2.vmaxh "
case 'w': // 1 string to match. case 'w': // 1 string to match.
return Intrinsic::hexagon_A2_vmaxw; // "exagon.A2.vmaxw " return Intrinsic::hexagon_A2_vmaxw; // "exagon.A2.vmaxw "
} }
break; break;
case 'i': // 2 strings to match. case 'i': // 3 strings to match.
if (NameR[13] != 'n') if (NameR[13] != 'n')
break; break;
switch (NameR[14]) { switch (NameR[14]) {
default: break; default: break;
case 'b': // 1 string to match.
return Intrinsic::hexagon_A2_vminb; // "exagon.A2.vminb
"
case 'h': // 1 string to match. case 'h': // 1 string to match.
return Intrinsic::hexagon_A2_vminh; // "exagon.A2.vminh " return Intrinsic::hexagon_A2_vminh; // "exagon.A2.vminh "
case 'w': // 1 string to match. case 'w': // 1 string to match.
return Intrinsic::hexagon_A2_vminw; // "exagon.A2.vminw " return Intrinsic::hexagon_A2_vminw; // "exagon.A2.vminw "
} }
break; break;
} }
break; break;
case 's': // 2 strings to match. case 's': // 2 strings to match.
if (NameR.substr(12, 2) != "ub") if (memcmp(NameR.data()+12, "ub", 2))
break; break;
switch (NameR[14]) { switch (NameR[14]) {
default: break; default: break;
case 'h': // 1 string to match. case 'h': // 1 string to match.
return Intrinsic::hexagon_A2_vsubh; // "exagon.A2.vsubh " return Intrinsic::hexagon_A2_vsubh; // "exagon.A2.vsubh "
case 'w': // 1 string to match. case 'w': // 1 string to match.
return Intrinsic::hexagon_A2_vsubw; // "exagon.A2.vsubw " return Intrinsic::hexagon_A2_vsubw; // "exagon.A2.vsubw "
} }
break; break;
} }
break; break;
} }
break; break;
case '4': // 1 string to match. case '4': // 1 string to match.
if (NameR.substr(9, 6) != ".andnp") if (memcmp(NameR.data()+9, ".andnp", 6))
break; break;
return Intrinsic::hexagon_A4_andnp; // "exagon.A4.andnp" return Intrinsic::hexagon_A4_andnp; // "exagon.A4.andnp"
} }
break; break;
case 'C': // 9 strings to match. case 'C': // 9 strings to match.
switch (NameR[8]) { switch (NameR[8]) {
default: break; default: break;
case '2': // 8 strings to match. case '2': // 8 strings to match.
if (NameR[9] != '.') if (NameR[9] != '.')
break; break;
switch (NameR[10]) { switch (NameR[10]) {
default: break; default: break;
case 'c': // 3 strings to match. case 'c': // 3 strings to match.
if (NameR.substr(11, 2) != "mp") if (memcmp(NameR.data()+11, "mp", 2))
break; break;
switch (NameR[13]) { switch (NameR[13]) {
default: break; default: break;
case 'e': // 1 string to match. case 'e': // 1 string to match.
if (NameR[14] != 'q') if (NameR[14] != 'q')
break; break;
return Intrinsic::hexagon_C2_cmpeq; // "exagon.C2.cmpeq " return Intrinsic::hexagon_C2_cmpeq; // "exagon.C2.cmpeq "
case 'g': // 1 string to match. case 'g': // 1 string to match.
if (NameR[14] != 't') if (NameR[14] != 't')
break; break;
return Intrinsic::hexagon_C2_cmpgt; // "exagon.C2.cmpgt " return Intrinsic::hexagon_C2_cmpgt; // "exagon.C2.cmpgt "
case 'l': // 1 string to match. case 'l': // 1 string to match.
if (NameR[14] != 't') if (NameR[14] != 't')
break; break;
return Intrinsic::hexagon_C2_cmplt; // "exagon.C2.cmplt " return Intrinsic::hexagon_C2_cmplt; // "exagon.C2.cmplt "
} }
break; break;
case 'm': // 3 strings to match. case 'm': // 3 strings to match.
if (NameR.substr(11, 2) != "ux") if (memcmp(NameR.data()+11, "ux", 2))
break; break;
switch (NameR[13]) { switch (NameR[13]) {
default: break; default: break;
case 'i': // 2 strings to match. case 'i': // 2 strings to match.
switch (NameR[14]) { switch (NameR[14]) {
default: break; default: break;
case 'i': // 1 string to match. case 'i': // 1 string to match.
return Intrinsic::hexagon_C2_muxii; // "exagon.C2.muxii " return Intrinsic::hexagon_C2_muxii; // "exagon.C2.muxii "
case 'r': // 1 string to match. case 'r': // 1 string to match.
return Intrinsic::hexagon_C2_muxir; // "exagon.C2.muxir " return Intrinsic::hexagon_C2_muxir; // "exagon.C2.muxir "
} }
break; break;
case 'r': // 1 string to match. case 'r': // 1 string to match.
if (NameR[14] != 'i') if (NameR[14] != 'i')
break; break;
return Intrinsic::hexagon_C2_muxri; // "exagon.C2.muxri " return Intrinsic::hexagon_C2_muxri; // "exagon.C2.muxri "
} }
break; break;
case 't': // 2 strings to match. case 't': // 2 strings to match.
if (NameR.substr(11, 2) != "fr") if (memcmp(NameR.data()+11, "fr", 2))
break; break;
switch (NameR[13]) { switch (NameR[13]) {
default: break; default: break;
case 'p': // 1 string to match. case 'p': // 1 string to match.
if (NameR[14] != 'r') if (NameR[14] != 'r')
break; break;
return Intrinsic::hexagon_C2_tfrpr; // "exagon.C2.tfrpr " return Intrinsic::hexagon_C2_tfrpr; // "exagon.C2.tfrpr "
case 'r': // 1 string to match. case 'r': // 1 string to match.
if (NameR[14] != 'p') if (NameR[14] != 'p')
break; break;
return Intrinsic::hexagon_C2_tfrrp; // "exagon.C2.tfrrp " return Intrinsic::hexagon_C2_tfrrp; // "exagon.C2.tfrrp "
} }
break; break;
} }
break; break;
case '4': // 1 string to match. case '4': // 1 string to match.
if (NameR.substr(9, 6) != ".or.or") if (memcmp(NameR.data()+9, ".or.or", 6))
break; break;
return Intrinsic::hexagon_C4_or_or; // "exagon.C4.or.or" return Intrinsic::hexagon_C4_or_or; // "exagon.C4.or.or"
} }
break; break;
case 'M': // 5 strings to match. case 'F': // 14 strings to match.
if (memcmp(NameR.data()+8, "2.", 2))
break;
switch (NameR[10]) {
default: break;
case 'd': // 7 strings to match.
if (NameR[11] != 'f')
break;
switch (NameR[12]) {
default: break;
case 'a': // 1 string to match.
if (memcmp(NameR.data()+13, "dd", 2))
break;
return Intrinsic::hexagon_F2_dfadd; // "exagon.F2.dfadd
"
case 'f': // 2 strings to match.
if (NameR[13] != 'm')
break;
switch (NameR[14]) {
default: break;
case 'a': // 1 string to match.
return Intrinsic::hexagon_F2_dffma; // "exagon.F2.dffma
"
case 's': // 1 string to match.
return Intrinsic::hexagon_F2_dffms; // "exagon.F2.dffms
"
}
break;
case 'm': // 3 strings to match.
switch (NameR[13]) {
default: break;
case 'a': // 1 string to match.
if (NameR[14] != 'x')
break;
return Intrinsic::hexagon_F2_dfmax; // "exagon.F2.dfmax
"
case 'i': // 1 string to match.
if (NameR[14] != 'n')
break;
return Intrinsic::hexagon_F2_dfmin; // "exagon.F2.dfmin
"
case 'p': // 1 string to match.
if (NameR[14] != 'y')
break;
return Intrinsic::hexagon_F2_dfmpy; // "exagon.F2.dfmpy
"
}
break;
case 's': // 1 string to match.
if (memcmp(NameR.data()+13, "ub", 2))
break;
return Intrinsic::hexagon_F2_dfsub; // "exagon.F2.dfsub
"
}
break;
case 's': // 7 strings to match.
if (NameR[11] != 'f')
break;
switch (NameR[12]) {
default: break;
case 'a': // 1 string to match.
if (memcmp(NameR.data()+13, "dd", 2))
break;
return Intrinsic::hexagon_F2_sfadd; // "exagon.F2.sfadd
"
case 'f': // 2 strings to match.
if (NameR[13] != 'm')
break;
switch (NameR[14]) {
default: break;
case 'a': // 1 string to match.
return Intrinsic::hexagon_F2_sffma; // "exagon.F2.sffma
"
case 's': // 1 string to match.
return Intrinsic::hexagon_F2_sffms; // "exagon.F2.sffms
"
}
break;
case 'm': // 3 strings to match.
switch (NameR[13]) {
default: break;
case 'a': // 1 string to match.
if (NameR[14] != 'x')
break;
return Intrinsic::hexagon_F2_sfmax; // "exagon.F2.sfmax
"
case 'i': // 1 string to match.
if (NameR[14] != 'n')
break;
return Intrinsic::hexagon_F2_sfmin; // "exagon.F2.sfmin
"
case 'p': // 1 string to match.
if (NameR[14] != 'y')
break;
return Intrinsic::hexagon_F2_sfmpy; // "exagon.F2.sfmpy
"
}
break;
case 's': // 1 string to match.
if (memcmp(NameR.data()+13, "ub", 2))
break;
return Intrinsic::hexagon_F2_sfsub; // "exagon.F2.sfsub
"
}
break;
}
break;
case 'M': // 6 strings to match.
switch (NameR[8]) { switch (NameR[8]) {
default: break; default: break;
case '2': // 4 strings to match. case '2': // 4 strings to match.
if (NameR[9] != '.') if (NameR[9] != '.')
break; break;
switch (NameR[10]) { switch (NameR[10]) {
default: break; default: break;
case 'a': // 1 string to match. case 'a': // 1 string to match.
if (NameR.substr(11, 4) != "ccii") if (memcmp(NameR.data()+11, "ccii", 4))
break; break;
return Intrinsic::hexagon_M2_accii; // "exagon.M2.accii " return Intrinsic::hexagon_M2_accii; // "exagon.M2.accii "
case 'm': // 1 string to match. case 'm': // 1 string to match.
if (NameR.substr(11, 4) != "pyui") if (memcmp(NameR.data()+11, "pyui", 4))
break; break;
return Intrinsic::hexagon_M2_mpyui; // "exagon.M2.mpyui " return Intrinsic::hexagon_M2_mpyui; // "exagon.M2.mpyui "
case 'n': // 1 string to match. case 'n': // 1 string to match.
if (NameR.substr(11, 4) != "acci") if (memcmp(NameR.data()+11, "acci", 4))
break; break;
return Intrinsic::hexagon_M2_nacci; // "exagon.M2.nacci " return Intrinsic::hexagon_M2_nacci; // "exagon.M2.nacci "
case 'v': // 1 string to match. case 'v': // 1 string to match.
if (NameR.substr(11, 4) != "mac2") if (memcmp(NameR.data()+11, "mac2", 4))
break; break;
return Intrinsic::hexagon_M2_vmac2; // "exagon.M2.vmac2 " return Intrinsic::hexagon_M2_vmac2; // "exagon.M2.vmac2 "
} }
break; break;
case '4': // 1 string to match. case '4': // 2 strings to match.
if (NameR.substr(9, 6) != ".or.or") if (NameR[9] != '.')
break; break;
return Intrinsic::hexagon_M4_or_or; // "exagon.M4.or.or" switch (NameR[10]) {
default: break;
case 'o': // 1 string to match.
if (memcmp(NameR.data()+11, "r.or", 4))
break;
return Intrinsic::hexagon_M4_or_or; // "exagon.M4.or.or
"
case 'p': // 1 string to match.
if (memcmp(NameR.data()+11, "mpyw", 4))
break;
return Intrinsic::hexagon_M4_pmpyw; // "exagon.M4.pmpyw
"
}
break;
} }
break; break;
case 'S': // 1 string to match. case 'S': // 1 string to match.
if (NameR.substr(8, 7) != "4.andnp") if (memcmp(NameR.data()+8, "2.brevp", 7))
break;
return Intrinsic::hexagon_S2_brevp; // "exagon.S2.brevp"
case 'c': // 1 string to match.
if (memcmp(NameR.data()+8, "irc.ldd", 7))
break; break;
return Intrinsic::hexagon_S4_andnp; // "exagon.S4.andnp" return Intrinsic::hexagon_circ_ldd; // "exagon.circ.ldd"
} }
break; break;
case 16: // 58 strings to match. case 16: // 70 strings to match.
if (NameR.substr(0, 7) != "exagon.") if (memcmp(NameR.data()+0, "exagon.", 7))
break; break;
switch (NameR[7]) { switch (NameR[7]) {
default: break; default: break;
case 'A': // 27 strings to match. case 'A': // 35 strings to match.
switch (NameR[8]) { switch (NameR[8]) {
default: break; default: break;
case '2': // 26 strings to match. case '2': // 26 strings to match.
if (NameR[9] != '.') if (NameR[9] != '.')
break; break;
switch (NameR[10]) { switch (NameR[10]) {
default: break; default: break;
case 'a': // 2 strings to match. case 'a': // 2 strings to match.
switch (NameR[11]) { switch (NameR[11]) {
default: break; default: break;
case 'b': // 1 string to match. case 'b': // 1 string to match.
if (NameR.substr(12, 4) != "ssat") if (memcmp(NameR.data()+12, "ssat", 4))
break; break;
return Intrinsic::hexagon_A2_abssat; // "exagon.A2.abssa t" return Intrinsic::hexagon_A2_abssat; // "exagon.A2.abssa t"
case 'd': // 1 string to match. case 'd': // 1 string to match.
if (NameR.substr(12, 4) != "dsat") if (memcmp(NameR.data()+12, "dsat", 4))
break; break;
return Intrinsic::hexagon_A2_addsat; // "exagon.A2.addsa t" return Intrinsic::hexagon_A2_addsat; // "exagon.A2.addsa t"
} }
break; break;
case 'n': // 1 string to match. case 'n': // 1 string to match.
if (NameR.substr(11, 5) != "egsat") if (memcmp(NameR.data()+11, "egsat", 5))
break; break;
return Intrinsic::hexagon_A2_negsat; // "exagon.A2.negsa t" return Intrinsic::hexagon_A2_negsat; // "exagon.A2.negsa t"
case 's': // 4 strings to match. case 's': // 4 strings to match.
switch (NameR[11]) { switch (NameR[11]) {
default: break; default: break;
case 'u': // 1 string to match. case 'u': // 1 string to match.
if (NameR.substr(12, 4) != "bsat") if (memcmp(NameR.data()+12, "bsat", 4))
break; break;
return Intrinsic::hexagon_A2_subsat; // "exagon.A2.subsa t" return Intrinsic::hexagon_A2_subsat; // "exagon.A2.subsa t"
case 'v': // 3 strings to match. case 'v': // 3 strings to match.
switch (NameR[12]) { switch (NameR[12]) {
default: break; default: break;
case 'a': // 2 strings to match. case 'a': // 2 strings to match.
switch (NameR[13]) { switch (NameR[13]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
if (NameR.substr(14, 2) != "dh") if (memcmp(NameR.data()+14, "dh", 2))
break; break;
return Intrinsic::hexagon_A2_svaddh; // "exagon.A2.svadd h" return Intrinsic::hexagon_A2_svaddh; // "exagon.A2.svadd h"
case 'v': // 1 string to match. case 'v': // 1 string to match.
if (NameR.substr(14, 2) != "gh") if (memcmp(NameR.data()+14, "gh", 2))
break; break;
return Intrinsic::hexagon_A2_svavgh; // "exagon.A2.svavg h" return Intrinsic::hexagon_A2_svavgh; // "exagon.A2.svavg h"
} }
break; break;
case 's': // 1 string to match. case 's': // 1 string to match.
if (NameR.substr(13, 3) != "ubh") if (memcmp(NameR.data()+13, "ubh", 3))
break; break;
return Intrinsic::hexagon_A2_svsubh; // "exagon.A2.svsub h" return Intrinsic::hexagon_A2_svsubh; // "exagon.A2.svsub h"
} }
break; break;
} }
break; break;
case 'v': // 19 strings to match. case 'v': // 19 strings to match.
switch (NameR[11]) { switch (NameR[11]) {
default: break; default: break;
case 'a': // 8 strings to match. case 'a': // 8 strings to match.
skipping to change at line 5368 skipping to change at line 6764
break; break;
return Intrinsic::hexagon_A2_vavgwr; // "exagon.A2.vavgw r" return Intrinsic::hexagon_A2_vavgwr; // "exagon.A2.vavgw r"
} }
break; break;
} }
break; break;
case 'm': // 6 strings to match. case 'm': // 6 strings to match.
switch (NameR[12]) { switch (NameR[12]) {
default: break; default: break;
case 'a': // 3 strings to match. case 'a': // 3 strings to match.
if (NameR.substr(13, 2) != "xu") if (memcmp(NameR.data()+13, "xu", 2))
break; break;
switch (NameR[15]) { switch (NameR[15]) {
default: break; default: break;
case 'b': // 1 string to match. case 'b': // 1 string to match.
return Intrinsic::hexagon_A2_vmaxub; // "exagon.A2.vmaxu b" return Intrinsic::hexagon_A2_vmaxub; // "exagon.A2.vmaxu b"
case 'h': // 1 string to match. case 'h': // 1 string to match.
return Intrinsic::hexagon_A2_vmaxuh; // "exagon.A2.vmaxu h" return Intrinsic::hexagon_A2_vmaxuh; // "exagon.A2.vmaxu h"
case 'w': // 1 string to match. case 'w': // 1 string to match.
return Intrinsic::hexagon_A2_vmaxuw; // "exagon.A2.vmaxu w" return Intrinsic::hexagon_A2_vmaxuw; // "exagon.A2.vmaxu w"
} }
break; break;
case 'i': // 3 strings to match. case 'i': // 3 strings to match.
if (NameR.substr(13, 2) != "nu") if (memcmp(NameR.data()+13, "nu", 2))
break; break;
switch (NameR[15]) { switch (NameR[15]) {
default: break; default: break;
case 'b': // 1 string to match. case 'b': // 1 string to match.
return Intrinsic::hexagon_A2_vminub; // "exagon.A2.vminu b" return Intrinsic::hexagon_A2_vminub; // "exagon.A2.vminu b"
case 'h': // 1 string to match. case 'h': // 1 string to match.
return Intrinsic::hexagon_A2_vminuh; // "exagon.A2.vminu h" return Intrinsic::hexagon_A2_vminuh; // "exagon.A2.vminu h"
case 'w': // 1 string to match. case 'w': // 1 string to match.
return Intrinsic::hexagon_A2_vminuw; // "exagon.A2.vminu w" return Intrinsic::hexagon_A2_vminuw; // "exagon.A2.vminu w"
} }
break; break;
} }
break; break;
case 'n': // 2 strings to match. case 'n': // 2 strings to match.
if (NameR.substr(12, 3) != "avg") if (memcmp(NameR.data()+12, "avg", 3))
break; break;
switch (NameR[15]) { switch (NameR[15]) {
default: break; default: break;
case 'h': // 1 string to match. case 'h': // 1 string to match.
return Intrinsic::hexagon_A2_vnavgh; // "exagon.A2.vnavg h" return Intrinsic::hexagon_A2_vnavgh; // "exagon.A2.vnavg h"
case 'w': // 1 string to match. case 'w': // 1 string to match.
return Intrinsic::hexagon_A2_vnavgw; // "exagon.A2.vnavg w" return Intrinsic::hexagon_A2_vnavgw; // "exagon.A2.vnavg w"
} }
break; break;
case 's': // 3 strings to match. case 's': // 3 strings to match.
if (NameR.substr(12, 2) != "ub") if (memcmp(NameR.data()+12, "ub", 2))
break; break;
switch (NameR[14]) { switch (NameR[14]) {
default: break; default: break;
case 'h': // 1 string to match. case 'h': // 1 string to match.
if (NameR[15] != 's') if (NameR[15] != 's')
break; break;
return Intrinsic::hexagon_A2_vsubhs; // "exagon.A2.vsubh s" return Intrinsic::hexagon_A2_vsubhs; // "exagon.A2.vsubh s"
case 'u': // 1 string to match. case 'u': // 1 string to match.
if (NameR[15] != 'b') if (NameR[15] != 'b')
break; break;
skipping to change at line 5429 skipping to change at line 6825
case 'w': // 1 string to match. case 'w': // 1 string to match.
if (NameR[15] != 's') if (NameR[15] != 's')
break; break;
return Intrinsic::hexagon_A2_vsubws; // "exagon.A2.vsubw s" return Intrinsic::hexagon_A2_vsubws; // "exagon.A2.vsubw s"
} }
break; break;
} }
break; break;
} }
break; break;
case '4': // 1 string to match. case '4': // 9 strings to match.
if (NameR.substr(9, 7) != ".rcmpeq") if (NameR[9] != '.')
break;
return Intrinsic::hexagon_A4_rcmpeq; // "exagon.A4.rcmpeq"
}
break;
case 'C': // 12 strings to match.
switch (NameR[8]) {
default: break;
case '2': // 7 strings to match.
if (NameR.substr(9, 4) != ".cmp")
break; break;
switch (NameR[13]) { switch (NameR[10]) {
default: break; default: break;
case 'e': // 2 strings to match. case 'c': // 4 strings to match.
if (NameR[14] != 'q') if (memcmp(NameR.data()+11, "mp", 2))
break; break;
switch (NameR[15]) { switch (NameR[13]) {
default: break;
case 'i': // 1 string to match.
return Intrinsic::hexagon_C2_cmpeqi; // "exagon.C2.cmpeq
i"
case 'p': // 1 string to match.
return Intrinsic::hexagon_C2_cmpeqp; // "exagon.C2.cmpeq
p"
}
break;
case 'g': // 4 strings to match.
switch (NameR[14]) {
default: break; default: break;
case 'e': // 1 string to match. case 'b': // 2 strings to match.
if (NameR[15] != 'i') switch (NameR[14]) {
break;
return Intrinsic::hexagon_C2_cmpgei; // "exagon.C2.cmpge
i"
case 't': // 3 strings to match.
switch (NameR[15]) {
default: break; default: break;
case 'i': // 1 string to match. case 'e': // 1 string to match.
return Intrinsic::hexagon_C2_cmpgti; // "exagon.C2.cmpgt if (NameR[15] != 'q')
i" break;
case 'p': // 1 string to match. return Intrinsic::hexagon_A4_cmpbeq; // "exagon.A4.cmpbe
return Intrinsic::hexagon_C2_cmpgtp; // "exagon.C2.cmpgt q"
p" case 'g': // 1 string to match.
case 'u': // 1 string to match. if (NameR[15] != 't')
return Intrinsic::hexagon_C2_cmpgtu; // "exagon.C2.cmpgt break;
u" return Intrinsic::hexagon_A4_cmpbgt; // "exagon.A4.cmpbg
t"
} }
break; break;
} case 'h': // 2 strings to match.
break; switch (NameR[14]) {
default: break;
case 'e': // 1 string to match.
if (NameR[15] != 'q')
break;
return Intrinsic::hexagon_A4_cmpheq; // "exagon.A4.cmphe
q"
case 'g': // 1 string to match.
if (NameR[15] != 't')
break;
return Intrinsic::hexagon_A4_cmphgt; // "exagon.A4.cmphg
t"
}
break;
}
break;
case 'r': // 1 string to match.
if (memcmp(NameR.data()+11, "cmpeq", 5))
break;
return Intrinsic::hexagon_A4_rcmpeq; // "exagon.A4.rcmpe
q"
case 'v': // 4 strings to match.
if (memcmp(NameR.data()+11, "rm", 2))
break;
switch (NameR[13]) {
default: break;
case 'a': // 2 strings to match.
if (NameR[14] != 'x')
break;
switch (NameR[15]) {
default: break;
case 'h': // 1 string to match.
return Intrinsic::hexagon_A4_vrmaxh; // "exagon.A4.vrmax
h"
case 'w': // 1 string to match.
return Intrinsic::hexagon_A4_vrmaxw; // "exagon.A4.vrmax
w"
}
break;
case 'i': // 2 strings to match.
if (NameR[14] != 'n')
break;
switch (NameR[15]) {
default: break;
case 'h': // 1 string to match.
return Intrinsic::hexagon_A4_vrminh; // "exagon.A4.vrmin
h"
case 'w': // 1 string to match.
return Intrinsic::hexagon_A4_vrminw; // "exagon.A4.vrmin
w"
}
break;
}
break;
}
break;
}
break;
case 'C': // 12 strings to match.
switch (NameR[8]) {
default: break;
case '2': // 7 strings to match.
if (memcmp(NameR.data()+9, ".cmp", 4))
break;
switch (NameR[13]) {
default: break;
case 'e': // 2 strings to match.
if (NameR[14] != 'q')
break;
switch (NameR[15]) {
default: break;
case 'i': // 1 string to match.
return Intrinsic::hexagon_C2_cmpeqi; // "exagon.C2.cmpeq
i"
case 'p': // 1 string to match.
return Intrinsic::hexagon_C2_cmpeqp; // "exagon.C2.cmpeq
p"
}
break;
case 'g': // 4 strings to match.
switch (NameR[14]) {
default: break;
case 'e': // 1 string to match.
if (NameR[15] != 'i')
break;
return Intrinsic::hexagon_C2_cmpgei; // "exagon.C2.cmpge
i"
case 't': // 3 strings to match.
switch (NameR[15]) {
default: break;
case 'i': // 1 string to match.
return Intrinsic::hexagon_C2_cmpgti; // "exagon.C2.cmpgt
i"
case 'p': // 1 string to match.
return Intrinsic::hexagon_C2_cmpgtp; // "exagon.C2.cmpgt
p"
case 'u': // 1 string to match.
return Intrinsic::hexagon_C2_cmpgtu; // "exagon.C2.cmpgt
u"
}
break;
}
break;
case 'l': // 1 string to match. case 'l': // 1 string to match.
if (NameR.substr(14, 2) != "tu") if (memcmp(NameR.data()+14, "tu", 2))
break; break;
return Intrinsic::hexagon_C2_cmpltu; // "exagon.C2.cmplt u" return Intrinsic::hexagon_C2_cmpltu; // "exagon.C2.cmplt u"
} }
break; break;
case '4': // 5 strings to match. case '4': // 5 strings to match.
if (NameR[9] != '.') if (NameR[9] != '.')
break; break;
switch (NameR[10]) { switch (NameR[10]) {
default: break; default: break;
case 'a': // 1 string to match. case 'a': // 1 string to match.
if (NameR.substr(11, 5) != "nd.or") if (memcmp(NameR.data()+11, "nd.or", 5))
break; break;
return Intrinsic::hexagon_C4_and_or; // "exagon.C4.and.o r" return Intrinsic::hexagon_C4_and_or; // "exagon.C4.and.o r"
case 'c': // 2 strings to match. case 'c': // 2 strings to match.
if (NameR.substr(11, 2) != "mp") if (memcmp(NameR.data()+11, "mp", 2))
break; break;
switch (NameR[13]) { switch (NameR[13]) {
default: break; default: break;
case 'l': // 1 string to match. case 'l': // 1 string to match.
if (NameR.substr(14, 2) != "te") if (memcmp(NameR.data()+14, "te", 2))
break; break;
return Intrinsic::hexagon_C4_cmplte; // "exagon.C4.cmplt e" return Intrinsic::hexagon_C4_cmplte; // "exagon.C4.cmplt e"
case 'n': // 1 string to match. case 'n': // 1 string to match.
if (NameR.substr(14, 2) != "eq") if (memcmp(NameR.data()+14, "eq", 2))
break; break;
return Intrinsic::hexagon_C4_cmpneq; // "exagon.C4.cmpne q" return Intrinsic::hexagon_C4_cmpneq; // "exagon.C4.cmpne q"
} }
break; break;
case 'o': // 2 strings to match. case 'o': // 2 strings to match.
if (NameR.substr(11, 2) != "r.") if (memcmp(NameR.data()+11, "r.", 2))
break; break;
switch (NameR[13]) { switch (NameR[13]) {
default: break; default: break;
case 'a': // 1 string to match. case 'a': // 1 string to match.
if (NameR.substr(14, 2) != "nd") if (memcmp(NameR.data()+14, "nd", 2))
break; break;
return Intrinsic::hexagon_C4_or_and; // "exagon.C4.or.an d" return Intrinsic::hexagon_C4_or_and; // "exagon.C4.or.an d"
case 'o': // 1 string to match. case 'o': // 1 string to match.
if (NameR.substr(14, 2) != "rn") if (memcmp(NameR.data()+14, "rn", 2))
break; break;
return Intrinsic::hexagon_C4_or_orn; // "exagon.C4.or.or n" return Intrinsic::hexagon_C4_or_orn; // "exagon.C4.or.or n"
} }
break; break;
} }
break; break;
} }
break; break;
case 'M': // 10 strings to match. case 'M': // 12 strings to match.
switch (NameR[8]) { switch (NameR[8]) {
default: break; default: break;
case '2': // 6 strings to match. case '2': // 7 strings to match.
if (NameR[9] != '.') if (NameR[9] != '.')
break; break;
switch (NameR[10]) { switch (NameR[10]) {
default: break; default: break;
case 'm': // 4 strings to match. case 'm': // 4 strings to match.
switch (NameR[11]) { switch (NameR[11]) {
default: break; default: break;
case 'a': // 2 strings to match. case 'a': // 2 strings to match.
if (NameR.substr(12, 3) != "csi") if (memcmp(NameR.data()+12, "csi", 3))
break; break;
switch (NameR[15]) { switch (NameR[15]) {
default: break; default: break;
case 'n': // 1 string to match. case 'n': // 1 string to match.
return Intrinsic::hexagon_M2_macsin; // "exagon.M2.macsi n" return Intrinsic::hexagon_M2_macsin; // "exagon.M2.macsi n"
case 'p': // 1 string to match. case 'p': // 1 string to match.
return Intrinsic::hexagon_M2_macsip; // "exagon.M2.macsi p" return Intrinsic::hexagon_M2_macsip; // "exagon.M2.macsi p"
} }
break; break;
case 'p': // 2 strings to match. case 'p': // 2 strings to match.
if (NameR[12] != 'y') if (NameR[12] != 'y')
break; break;
switch (NameR[13]) { switch (NameR[13]) {
default: break; default: break;
case '.': // 1 string to match. case '.': // 1 string to match.
if (NameR.substr(14, 2) != "up") if (memcmp(NameR.data()+14, "up", 2))
break; break;
return Intrinsic::hexagon_M2_mpy_up; // "exagon.M2.mpy.u p" return Intrinsic::hexagon_M2_mpy_up; // "exagon.M2.mpy.u p"
case 's': // 1 string to match. case 's': // 1 string to match.
if (NameR.substr(14, 2) != "mi") if (memcmp(NameR.data()+14, "mi", 2))
break; break;
return Intrinsic::hexagon_M2_mpysmi; // "exagon.M2.mpysm i" return Intrinsic::hexagon_M2_mpysmi; // "exagon.M2.mpysm i"
} }
break; break;
} }
break; break;
case 'n': // 1 string to match. case 'n': // 1 string to match.
if (NameR.substr(11, 5) != "accii") if (memcmp(NameR.data()+11, "accii", 5))
break; break;
return Intrinsic::hexagon_M2_naccii; // "exagon.M2.nacci i" return Intrinsic::hexagon_M2_naccii; // "exagon.M2.nacci i"
case 's': // 1 string to match. case 's': // 1 string to match.
if (NameR.substr(11, 5) != "ubacc") if (memcmp(NameR.data()+11, "ubacc", 5))
break; break;
return Intrinsic::hexagon_M2_subacc; // "exagon.M2.subac c" return Intrinsic::hexagon_M2_subacc; // "exagon.M2.subac c"
case 'v': // 1 string to match.
if (memcmp(NameR.data()+11, "raddh", 5))
break;
return Intrinsic::hexagon_M2_vraddh; // "exagon.M2.vradd
h"
} }
break; break;
case '4': // 4 strings to match. case '4': // 5 strings to match.
if (NameR[9] != '.') if (NameR[9] != '.')
break; break;
switch (NameR[10]) { switch (NameR[10]) {
default: break; default: break;
case 'a': // 1 string to match. case 'a': // 1 string to match.
if (NameR.substr(11, 5) != "nd.or") if (memcmp(NameR.data()+11, "nd.or", 5))
break; break;
return Intrinsic::hexagon_M4_and_or; // "exagon.M4.and.o r" return Intrinsic::hexagon_M4_and_or; // "exagon.M4.and.o r"
case 'o': // 2 strings to match. case 'o': // 2 strings to match.
if (NameR.substr(11, 2) != "r.") if (memcmp(NameR.data()+11, "r.", 2))
break; break;
switch (NameR[13]) { switch (NameR[13]) {
default: break; default: break;
case 'a': // 1 string to match. case 'a': // 1 string to match.
if (NameR.substr(14, 2) != "nd") if (memcmp(NameR.data()+14, "nd", 2))
break; break;
return Intrinsic::hexagon_M4_or_and; // "exagon.M4.or.an d" return Intrinsic::hexagon_M4_or_and; // "exagon.M4.or.an d"
case 'x': // 1 string to match. case 'x': // 1 string to match.
if (NameR.substr(14, 2) != "or") if (memcmp(NameR.data()+14, "or", 2))
break; break;
return Intrinsic::hexagon_M4_or_xor; // "exagon.M4.or.xo r" return Intrinsic::hexagon_M4_or_xor; // "exagon.M4.or.xo r"
} }
break; break;
case 'v': // 1 string to match.
if (memcmp(NameR.data()+11, "pmpyh", 5))
break;
return Intrinsic::hexagon_M4_vpmpyh; // "exagon.M4.vpmpy
h"
case 'x': // 1 string to match. case 'x': // 1 string to match.
if (NameR.substr(11, 5) != "or.or") if (memcmp(NameR.data()+11, "or.or", 5))
break; break;
return Intrinsic::hexagon_M4_xor_or; // "exagon.M4.xor.o r" return Intrinsic::hexagon_M4_xor_or; // "exagon.M4.xor.o r"
} }
break; break;
} }
break; break;
case 'S': // 9 strings to match. case 'S': // 11 strings to match.
switch (NameR[8]) { switch (NameR[8]) {
default: break; default: break;
case '2': // 8 strings to match. case '2': // 9 strings to match.
if (NameR[9] != '.') if (NameR[9] != '.')
break; break;
switch (NameR[10]) { switch (NameR[10]) {
default: break; default: break;
case 'i': // 1 string to match. case 'i': // 1 string to match.
if (NameR.substr(11, 5) != "nsert") if (memcmp(NameR.data()+11, "nsert", 5))
break; break;
return Intrinsic::hexagon_S2_insert; // "exagon.S2.inser t" return Intrinsic::hexagon_S2_insert; // "exagon.S2.inser t"
case 'p': // 1 string to match. case 'p': // 1 string to match.
if (NameR.substr(11, 5) != "ackhl") if (memcmp(NameR.data()+11, "ackhl", 5))
break; break;
return Intrinsic::hexagon_S2_packhl; // "exagon.S2.packh l" return Intrinsic::hexagon_S2_packhl; // "exagon.S2.packh l"
case 'v': // 6 strings to match. case 'v': // 7 strings to match.
switch (NameR[11]) { switch (NameR[11]) {
default: break; default: break;
case 'c': // 1 string to match.
if (memcmp(NameR.data()+12, "negh", 4))
break;
return Intrinsic::hexagon_S2_vcnegh; // "exagon.S2.vcneg
h"
case 's': // 4 strings to match. case 's': // 4 strings to match.
switch (NameR[12]) { switch (NameR[12]) {
default: break; default: break;
case 'a': // 2 strings to match. case 'a': // 2 strings to match.
if (NameR[13] != 't') if (NameR[13] != 't')
break; break;
switch (NameR[14]) { switch (NameR[14]) {
default: break; default: break;
case 'h': // 1 string to match. case 'h': // 1 string to match.
if (NameR[15] != 'b') if (NameR[15] != 'b')
skipping to change at line 5659 skipping to change at line 7136
return Intrinsic::hexagon_S2_vsxtbh; // "exagon.S2.vsxtb h" return Intrinsic::hexagon_S2_vsxtbh; // "exagon.S2.vsxtb h"
case 'h': // 1 string to match. case 'h': // 1 string to match.
if (NameR[15] != 'w') if (NameR[15] != 'w')
break; break;
return Intrinsic::hexagon_S2_vsxthw; // "exagon.S2.vsxth w" return Intrinsic::hexagon_S2_vsxthw; // "exagon.S2.vsxth w"
} }
break; break;
} }
break; break;
case 'z': // 2 strings to match. case 'z': // 2 strings to match.
if (NameR.substr(12, 2) != "xt") if (memcmp(NameR.data()+12, "xt", 2))
break; break;
switch (NameR[14]) { switch (NameR[14]) {
default: break; default: break;
case 'b': // 1 string to match. case 'b': // 1 string to match.
if (NameR[15] != 'h') if (NameR[15] != 'h')
break; break;
return Intrinsic::hexagon_S2_vzxtbh; // "exagon.S2.vzxtb h" return Intrinsic::hexagon_S2_vzxtbh; // "exagon.S2.vzxtb h"
case 'h': // 1 string to match. case 'h': // 1 string to match.
if (NameR[15] != 'w') if (NameR[15] != 'w')
break; break;
return Intrinsic::hexagon_S2_vzxthw; // "exagon.S2.vzxth w" return Intrinsic::hexagon_S2_vzxthw; // "exagon.S2.vzxth w"
} }
break; break;
} }
break; break;
} }
break; break;
case '4': // 1 string to match. case '4': // 2 strings to match.
if (NameR.substr(9, 7) != ".or.ori") if (NameR[9] != '.')
break; break;
return Intrinsic::hexagon_S4_or_ori; // "exagon.S4.or.ori" switch (NameR[10]) {
default: break;
case 'o': // 1 string to match.
if (memcmp(NameR.data()+11, "r.ori", 5))
break;
return Intrinsic::hexagon_S4_or_ori; // "exagon.S4.or.or
i"
case 'p': // 1 string to match.
if (memcmp(NameR.data()+11, "arity", 5))
break;
return Intrinsic::hexagon_S4_parity; // "exagon.S4.parit
y"
}
break;
} }
break; break;
} }
break; break;
case 17: // 71 strings to match. case 17: // 103 strings to match.
if (NameR.substr(0, 7) != "exagon.") if (memcmp(NameR.data()+0, "exagon.", 7))
break; break;
switch (NameR[7]) { switch (NameR[7]) {
default: break; default: break;
case 'A': // 25 strings to match. case 'A': // 36 strings to match.
switch (NameR[8]) { switch (NameR[8]) {
default: break; default: break;
case '2': // 23 strings to match. case '2': // 23 strings to match.
if (NameR[9] != '.') if (NameR[9] != '.')
break; break;
switch (NameR[10]) { switch (NameR[10]) {
default: break; default: break;
case 'a': // 1 string to match. case 'a': // 1 string to match.
if (NameR.substr(11, 6) != "ddpsat") if (memcmp(NameR.data()+11, "ddpsat", 6))
break; break;
return Intrinsic::hexagon_A2_addpsat; // "exagon.A2.addps at" return Intrinsic::hexagon_A2_addpsat; // "exagon.A2.addps at"
case 's': // 4 strings to match. case 's': // 4 strings to match.
if (NameR[11] != 'v') if (NameR[11] != 'v')
break; break;
switch (NameR[12]) { switch (NameR[12]) {
default: break; default: break;
case 'a': // 2 strings to match. case 'a': // 2 strings to match.
switch (NameR[13]) { switch (NameR[13]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
if (NameR.substr(14, 3) != "dhs") if (memcmp(NameR.data()+14, "dhs", 3))
break; break;
return Intrinsic::hexagon_A2_svaddhs; // "exagon.A2.svadd hs" return Intrinsic::hexagon_A2_svaddhs; // "exagon.A2.svadd hs"
case 'v': // 1 string to match. case 'v': // 1 string to match.
if (NameR.substr(14, 3) != "ghs") if (memcmp(NameR.data()+14, "ghs", 3))
break; break;
return Intrinsic::hexagon_A2_svavghs; // "exagon.A2.svavg hs" return Intrinsic::hexagon_A2_svavghs; // "exagon.A2.svavg hs"
} }
break; break;
case 'n': // 1 string to match. case 'n': // 1 string to match.
if (NameR.substr(13, 4) != "avgh") if (memcmp(NameR.data()+13, "avgh", 4))
break; break;
return Intrinsic::hexagon_A2_svnavgh; // "exagon.A2.svnav gh" return Intrinsic::hexagon_A2_svnavgh; // "exagon.A2.svnav gh"
case 's': // 1 string to match. case 's': // 1 string to match.
if (NameR.substr(13, 4) != "ubhs") if (memcmp(NameR.data()+13, "ubhs", 4))
break; break;
return Intrinsic::hexagon_A2_svsubhs; // "exagon.A2.svsub hs" return Intrinsic::hexagon_A2_svsubhs; // "exagon.A2.svsub hs"
} }
break; break;
case 'v': // 18 strings to match. case 'v': // 18 strings to match.
switch (NameR[11]) { switch (NameR[11]) {
default: break; default: break;
case 'a': // 7 strings to match. case 'a': // 7 strings to match.
switch (NameR[12]) { switch (NameR[12]) {
default: break; default: break;
case 'd': // 2 strings to match. case 'd': // 2 strings to match.
if (NameR.substr(13, 2) != "du") if (memcmp(NameR.data()+13, "du", 2))
break; break;
switch (NameR[15]) { switch (NameR[15]) {
default: break; default: break;
case 'b': // 1 string to match. case 'b': // 1 string to match.
if (NameR[16] != 's') if (NameR[16] != 's')
break; break;
return Intrinsic::hexagon_A2_vaddubs; // "exagon. A2.vaddubs" return Intrinsic::hexagon_A2_vaddubs; // "exagon. A2.vaddubs"
case 'h': // 1 string to match. case 'h': // 1 string to match.
if (NameR[16] != 's') if (NameR[16] != 's')
break; break;
return Intrinsic::hexagon_A2_vadduhs; // "exagon. A2.vadduhs" return Intrinsic::hexagon_A2_vadduhs; // "exagon. A2.vadduhs"
} }
break; break;
case 'v': // 5 strings to match. case 'v': // 5 strings to match.
if (NameR[13] != 'g') if (NameR[13] != 'g')
break; break;
switch (NameR[14]) { switch (NameR[14]) {
default: break; default: break;
case 'h': // 1 string to match. case 'h': // 1 string to match.
if (NameR.substr(15, 2) != "cr") if (memcmp(NameR.data()+15, "cr", 2))
break; break;
return Intrinsic::hexagon_A2_vavghcr; // "exagon. A2.vavghcr" return Intrinsic::hexagon_A2_vavghcr; // "exagon. A2.vavghcr"
case 'u': // 3 strings to match. case 'u': // 3 strings to match.
switch (NameR[15]) { switch (NameR[15]) {
default: break; default: break;
case 'b': // 1 string to match. case 'b': // 1 string to match.
if (NameR[16] != 'r') if (NameR[16] != 'r')
break; break;
return Intrinsic::hexagon_A2_vavgubr; // "exagon. A2.vavgubr" return Intrinsic::hexagon_A2_vavgubr; // "exagon. A2.vavgubr"
case 'h': // 1 string to match. case 'h': // 1 string to match.
if (NameR[16] != 'r') if (NameR[16] != 'r')
break; break;
return Intrinsic::hexagon_A2_vavguhr; // "exagon. A2.vavguhr" return Intrinsic::hexagon_A2_vavguhr; // "exagon. A2.vavguhr"
case 'w': // 1 string to match. case 'w': // 1 string to match.
if (NameR[16] != 'r') if (NameR[16] != 'r')
break; break;
return Intrinsic::hexagon_A2_vavguwr; // "exagon. A2.vavguwr" return Intrinsic::hexagon_A2_vavguwr; // "exagon. A2.vavguwr"
} }
break; break;
case 'w': // 1 string to match. case 'w': // 1 string to match.
if (NameR.substr(15, 2) != "cr") if (memcmp(NameR.data()+15, "cr", 2))
break; break;
return Intrinsic::hexagon_A2_vavgwcr; // "exagon. A2.vavgwcr" return Intrinsic::hexagon_A2_vavgwcr; // "exagon. A2.vavgwcr"
} }
break; break;
} }
break; break;
case 'c': // 5 strings to match. case 'c': // 5 strings to match.
if (NameR.substr(12, 2) != "mp") if (memcmp(NameR.data()+12, "mp", 2))
break; break;
switch (NameR[14]) { switch (NameR[14]) {
default: break; default: break;
case 'b': // 1 string to match. case 'b': // 1 string to match.
if (NameR.substr(15, 2) != "eq") if (memcmp(NameR.data()+15, "eq", 2))
break; break;
return Intrinsic::hexagon_A2_vcmpbeq; // "exagon.A2.vcmpb eq" return Intrinsic::hexagon_A2_vcmpbeq; // "exagon.A2.vcmpb eq"
case 'h': // 2 strings to match. case 'h': // 2 strings to match.
switch (NameR[15]) { switch (NameR[15]) {
default: break; default: break;
case 'e': // 1 string to match. case 'e': // 1 string to match.
if (NameR[16] != 'q') if (NameR[16] != 'q')
break; break;
return Intrinsic::hexagon_A2_vcmpheq; // "exagon. A2.vcmpheq" return Intrinsic::hexagon_A2_vcmpheq; // "exagon. A2.vcmpheq"
case 'g': // 1 string to match. case 'g': // 1 string to match.
skipping to change at line 5823 skipping to change at line 7311
return Intrinsic::hexagon_A2_vcmpweq; // "exagon. A2.vcmpweq" return Intrinsic::hexagon_A2_vcmpweq; // "exagon. A2.vcmpweq"
case 'g': // 1 string to match. case 'g': // 1 string to match.
if (NameR[16] != 't') if (NameR[16] != 't')
break; break;
return Intrinsic::hexagon_A2_vcmpwgt; // "exagon. A2.vcmpwgt" return Intrinsic::hexagon_A2_vcmpwgt; // "exagon. A2.vcmpwgt"
} }
break; break;
} }
break; break;
case 'n': // 2 strings to match. case 'n': // 2 strings to match.
if (NameR.substr(12, 3) != "avg") if (memcmp(NameR.data()+12, "avg", 3))
break; break;
switch (NameR[15]) { switch (NameR[15]) {
default: break; default: break;
case 'h': // 1 string to match. case 'h': // 1 string to match.
if (NameR[16] != 'r') if (NameR[16] != 'r')
break; break;
return Intrinsic::hexagon_A2_vnavghr; // "exagon.A2.vnavg hr" return Intrinsic::hexagon_A2_vnavghr; // "exagon.A2.vnavg hr"
case 'w': // 1 string to match. case 'w': // 1 string to match.
if (NameR[16] != 'r') if (NameR[16] != 'r')
break; break;
return Intrinsic::hexagon_A2_vnavgwr; // "exagon.A2.vnavg wr" return Intrinsic::hexagon_A2_vnavgwr; // "exagon.A2.vnavg wr"
} }
break; break;
case 'r': // 2 strings to match. case 'r': // 2 strings to match.
switch (NameR[12]) { switch (NameR[12]) {
default: break; default: break;
case 'a': // 1 string to match. case 'a': // 1 string to match.
if (NameR.substr(13, 4) != "ddub") if (memcmp(NameR.data()+13, "ddub", 4))
break; break;
return Intrinsic::hexagon_A2_vraddub; // "exagon.A2.vradd ub" return Intrinsic::hexagon_A2_vraddub; // "exagon.A2.vradd ub"
case 's': // 1 string to match. case 's': // 1 string to match.
if (NameR.substr(13, 4) != "adub") if (memcmp(NameR.data()+13, "adub", 4))
break; break;
return Intrinsic::hexagon_A2_vrsadub; // "exagon.A2.vrsad ub" return Intrinsic::hexagon_A2_vrsadub; // "exagon.A2.vrsad ub"
} }
break; break;
case 's': // 2 strings to match. case 's': // 2 strings to match.
if (NameR.substr(12, 3) != "ubu") if (memcmp(NameR.data()+12, "ubu", 3))
break; break;
switch (NameR[15]) { switch (NameR[15]) {
default: break; default: break;
case 'b': // 1 string to match. case 'b': // 1 string to match.
if (NameR[16] != 's') if (NameR[16] != 's')
break; break;
return Intrinsic::hexagon_A2_vsububs; // "exagon.A2.vsubu bs" return Intrinsic::hexagon_A2_vsububs; // "exagon.A2.vsubu bs"
case 'h': // 1 string to match. case 'h': // 1 string to match.
if (NameR[16] != 's') if (NameR[16] != 's')
break; break;
return Intrinsic::hexagon_A2_vsubuhs; // "exagon.A2.vsubu hs" return Intrinsic::hexagon_A2_vsubuhs; // "exagon.A2.vsubu hs"
} }
break; break;
} }
break; break;
} }
break; break;
case '4': // 2 strings to match. case '4': // 13 strings to match.
if (NameR.substr(9, 5) != ".rcmp") if (NameR[9] != '.')
break; break;
switch (NameR[14]) { switch (NameR[10]) {
default: break; default: break;
case 'e': // 1 string to match. case 'c': // 6 strings to match.
if (NameR.substr(15, 2) != "qi") if (memcmp(NameR.data()+11, "mp", 2))
break; break;
return Intrinsic::hexagon_A4_rcmpeqi; // "exagon.A4.rcmpe switch (NameR[13]) {
qi" default: break;
case 'n': // 1 string to match. case 'b': // 3 strings to match.
if (NameR.substr(15, 2) != "eq") switch (NameR[14]) {
default: break;
case 'e': // 1 string to match.
if (memcmp(NameR.data()+15, "qi", 2))
break;
return Intrinsic::hexagon_A4_cmpbeqi; // "exagon.A4.cmpbe
qi"
case 'g': // 2 strings to match.
if (NameR[15] != 't')
break;
switch (NameR[16]) {
default: break;
case 'i': // 1 string to match.
return Intrinsic::hexagon_A4_cmpbgti; // "exagon.
A4.cmpbgti"
case 'u': // 1 string to match.
return Intrinsic::hexagon_A4_cmpbgtu; // "exagon.
A4.cmpbgtu"
}
break;
}
break;
case 'h': // 3 strings to match.
switch (NameR[14]) {
default: break;
case 'e': // 1 string to match.
if (memcmp(NameR.data()+15, "qi", 2))
break;
return Intrinsic::hexagon_A4_cmpheqi; // "exagon.A4.cmphe
qi"
case 'g': // 2 strings to match.
if (NameR[15] != 't')
break;
switch (NameR[16]) {
default: break;
case 'i': // 1 string to match.
return Intrinsic::hexagon_A4_cmphgti; // "exagon.
A4.cmphgti"
case 'u': // 1 string to match.
return Intrinsic::hexagon_A4_cmphgtu; // "exagon.
A4.cmphgtu"
}
break;
}
break;
}
break;
case 'r': // 2 strings to match.
if (memcmp(NameR.data()+11, "cmp", 3))
break;
switch (NameR[14]) {
default: break;
case 'e': // 1 string to match.
if (memcmp(NameR.data()+15, "qi", 2))
break;
return Intrinsic::hexagon_A4_rcmpeqi; // "exagon.A4.rcmpe
qi"
case 'n': // 1 string to match.
if (memcmp(NameR.data()+15, "eq", 2))
break;
return Intrinsic::hexagon_A4_rcmpneq; // "exagon.A4.rcmpn
eq"
}
break;
case 'v': // 5 strings to match.
switch (NameR[11]) {
default: break;
case 'c': // 1 string to match.
if (memcmp(NameR.data()+12, "mpbgt", 5))
break;
return Intrinsic::hexagon_A4_vcmpbgt; // "exagon.A4.vcmpb
gt"
case 'r': // 4 strings to match.
if (NameR[12] != 'm')
break;
switch (NameR[13]) {
default: break;
case 'a': // 2 strings to match.
if (memcmp(NameR.data()+14, "xu", 2))
break;
switch (NameR[16]) {
default: break;
case 'h': // 1 string to match.
return Intrinsic::hexagon_A4_vrmaxuh; // "exagon.
A4.vrmaxuh"
case 'w': // 1 string to match.
return Intrinsic::hexagon_A4_vrmaxuw; // "exagon.
A4.vrmaxuw"
}
break;
case 'i': // 2 strings to match.
if (memcmp(NameR.data()+14, "nu", 2))
break;
switch (NameR[16]) {
default: break;
case 'h': // 1 string to match.
return Intrinsic::hexagon_A4_vrminuh; // "exagon.
A4.vrminuh"
case 'w': // 1 string to match.
return Intrinsic::hexagon_A4_vrminuw; // "exagon.
A4.vrminuw"
}
break;
}
break; break;
return Intrinsic::hexagon_A4_rcmpneq; // "exagon.A4.rcmpn }
eq" break;
} }
break; break;
} }
break; break;
case 'C': // 12 strings to match. case 'C': // 12 strings to match.
switch (NameR[8]) { switch (NameR[8]) {
default: break; default: break;
case '2': // 6 strings to match. case '2': // 6 strings to match.
if (NameR[9] != '.') if (NameR[9] != '.')
break; break;
switch (NameR[10]) { switch (NameR[10]) {
default: break; default: break;
case 'b': // 2 strings to match. case 'b': // 2 strings to match.
if (NameR.substr(11, 3) != "its") if (memcmp(NameR.data()+11, "its", 3))
break; break;
switch (NameR[14]) { switch (NameR[14]) {
default: break; default: break;
case 'c': // 1 string to match. case 'c': // 1 string to match.
if (NameR.substr(15, 2) != "lr") if (memcmp(NameR.data()+15, "lr", 2))
break; break;
return Intrinsic::hexagon_C2_bitsclr; // "exagon.C2.bitsc lr" return Intrinsic::hexagon_C2_bitsclr; // "exagon.C2.bitsc lr"
case 's': // 1 string to match. case 's': // 1 string to match.
if (NameR.substr(15, 2) != "et") if (memcmp(NameR.data()+15, "et", 2))
break; break;
return Intrinsic::hexagon_C2_bitsset; // "exagon.C2.bitss et" return Intrinsic::hexagon_C2_bitsset; // "exagon.C2.bitss et"
} }
break; break;
case 'c': // 3 strings to match. case 'c': // 3 strings to match.
if (NameR.substr(11, 3) != "mpg") if (memcmp(NameR.data()+11, "mpg", 3))
break; break;
switch (NameR[14]) { switch (NameR[14]) {
default: break; default: break;
case 'e': // 1 string to match. case 'e': // 1 string to match.
if (NameR.substr(15, 2) != "ui") if (memcmp(NameR.data()+15, "ui", 2))
break; break;
return Intrinsic::hexagon_C2_cmpgeui; // "exagon.C2.cmpge ui" return Intrinsic::hexagon_C2_cmpgeui; // "exagon.C2.cmpge ui"
case 't': // 2 strings to match. case 't': // 2 strings to match.
if (NameR[15] != 'u') if (NameR[15] != 'u')
break; break;
switch (NameR[16]) { switch (NameR[16]) {
default: break; default: break;
case 'i': // 1 string to match. case 'i': // 1 string to match.
return Intrinsic::hexagon_C2_cmpgtui; // "exagon.C2.cmpgt ui" return Intrinsic::hexagon_C2_cmpgtui; // "exagon.C2.cmpgt ui"
case 'p': // 1 string to match. case 'p': // 1 string to match.
return Intrinsic::hexagon_C2_cmpgtup; // "exagon.C2.cmpgt up" return Intrinsic::hexagon_C2_cmpgtup; // "exagon.C2.cmpgt up"
} }
break; break;
} }
break; break;
case 'v': // 1 string to match. case 'v': // 1 string to match.
if (NameR.substr(11, 6) != "itpack") if (memcmp(NameR.data()+11, "itpack", 6))
break; break;
return Intrinsic::hexagon_C2_vitpack; // "exagon.C2.vitpa ck" return Intrinsic::hexagon_C2_vitpack; // "exagon.C2.vitpa ck"
} }
break; break;
case '4': // 6 strings to match. case '4': // 6 strings to match.
if (NameR[9] != '.') if (NameR[9] != '.')
break; break;
switch (NameR[10]) { switch (NameR[10]) {
default: break; default: break;
case 'a': // 2 strings to match. case 'a': // 2 strings to match.
if (NameR.substr(11, 3) != "nd.") if (memcmp(NameR.data()+11, "nd.", 3))
break; break;
switch (NameR[14]) { switch (NameR[14]) {
default: break; default: break;
case 'a': // 1 string to match. case 'a': // 1 string to match.
if (NameR.substr(15, 2) != "nd") if (memcmp(NameR.data()+15, "nd", 2))
break; break;
return Intrinsic::hexagon_C4_and_and; // "exagon.C4.and.a nd" return Intrinsic::hexagon_C4_and_and; // "exagon.C4.and.a nd"
case 'o': // 1 string to match. case 'o': // 1 string to match.
if (NameR.substr(15, 2) != "rn") if (memcmp(NameR.data()+15, "rn", 2))
break; break;
return Intrinsic::hexagon_C4_and_orn; // "exagon.C4.and.o rn" return Intrinsic::hexagon_C4_and_orn; // "exagon.C4.and.o rn"
} }
break; break;
case 'c': // 3 strings to match. case 'c': // 3 strings to match.
if (NameR.substr(11, 2) != "mp") if (memcmp(NameR.data()+11, "mp", 2))
break; break;
switch (NameR[13]) { switch (NameR[13]) {
default: break; default: break;
case 'l': // 2 strings to match. case 'l': // 2 strings to match.
if (NameR.substr(14, 2) != "te") if (memcmp(NameR.data()+14, "te", 2))
break; break;
switch (NameR[16]) { switch (NameR[16]) {
default: break; default: break;
case 'i': // 1 string to match. case 'i': // 1 string to match.
return Intrinsic::hexagon_C4_cmpltei; // "exagon.C4.cmplt ei" return Intrinsic::hexagon_C4_cmpltei; // "exagon.C4.cmplt ei"
case 'u': // 1 string to match. case 'u': // 1 string to match.
return Intrinsic::hexagon_C4_cmplteu; // "exagon.C4.cmplt eu" return Intrinsic::hexagon_C4_cmplteu; // "exagon.C4.cmplt eu"
} }
break; break;
case 'n': // 1 string to match. case 'n': // 1 string to match.
if (NameR.substr(14, 3) != "eqi") if (memcmp(NameR.data()+14, "eqi", 3))
break; break;
return Intrinsic::hexagon_C4_cmpneqi; // "exagon.C4.cmpne qi" return Intrinsic::hexagon_C4_cmpneqi; // "exagon.C4.cmpne qi"
} }
break; break;
case 'o': // 1 string to match. case 'o': // 1 string to match.
if (NameR.substr(11, 6) != "r.andn") if (memcmp(NameR.data()+11, "r.andn", 6))
break; break;
return Intrinsic::hexagon_C4_or_andn; // "exagon.C4.or.an dn" return Intrinsic::hexagon_C4_or_andn; // "exagon.C4.or.an dn"
} }
break; break;
} }
break; break;
case 'M': // 7 strings to match. case 'F': // 14 strings to match.
switch (NameR[8]) { if (memcmp(NameR.data()+8, "2.", 2))
break;
switch (NameR[10]) {
default: break; default: break;
case '2': // 3 strings to match. case 'd': // 7 strings to match.
if (NameR[9] != '.') if (NameR[11] != 'f')
break; break;
switch (NameR[10]) { switch (NameR[12]) {
default: break; default: break;
case 'm': // 1 string to match. case 'c': // 5 strings to match.
if (NameR.substr(11, 6) != "pyu.up") switch (NameR[13]) {
break;
return Intrinsic::hexagon_M2_mpyu_up; // "exagon.M2.mpyu.
up"
case 'v': // 2 strings to match.
switch (NameR[11]) {
default: break; default: break;
case 'm': // 1 string to match. case 'l': // 1 string to match.
if (NameR.substr(12, 5) != "ac2es") if (memcmp(NameR.data()+14, "ass", 3))
break; break;
return Intrinsic::hexagon_M2_vmac2es; // "exagon.M2.vmac2 return Intrinsic::hexagon_F2_dfclass; // "exagon.F2.dfcla
es" ss"
case 'r': // 1 string to match. case 'm': // 4 strings to match.
if (NameR.substr(12, 5) != "adduh") if (NameR[14] != 'p')
break; break;
return Intrinsic::hexagon_M2_vradduh; // "exagon.M2.vradd switch (NameR[15]) {
uh" default: break;
case 'e': // 1 string to match.
if (NameR[16] != 'q')
break;
return Intrinsic::hexagon_F2_dfcmpeq; // "exagon.F2.dfcmp
eq"
case 'g': // 2 strings to match.
switch (NameR[16]) {
default: break;
case 'e': // 1 string to match.
return Intrinsic::hexagon_F2_dfcmpge; // "exagon.
F2.dfcmpge"
case 't': // 1 string to match.
return Intrinsic::hexagon_F2_dfcmpgt; // "exagon.
F2.dfcmpgt"
}
break;
case 'u': // 1 string to match.
if (NameR[16] != 'o')
break;
return Intrinsic::hexagon_F2_dfcmpuo; // "exagon.F2.dfcmp
uo"
}
break;
} }
break; break;
} case 'i': // 2 strings to match.
break; if (memcmp(NameR.data()+13, "mm.", 3))
case '4': // 4 strings to match.
if (NameR[9] != '.')
break;
switch (NameR[10]) {
default: break;
case 'a': // 2 strings to match.
if (NameR.substr(11, 3) != "nd.")
break; break;
switch (NameR[14]) { switch (NameR[16]) {
default: break; default: break;
case 'a': // 1 string to match. case 'n': // 1 string to match.
if (NameR.substr(15, 2) != "nd") return Intrinsic::hexagon_F2_dfimm_n; // "exagon.F2.dfimm
break; .n"
return Intrinsic::hexagon_M4_and_and; // "exagon.M4.and.a case 'p': // 1 string to match.
nd" return Intrinsic::hexagon_F2_dfimm_p; // "exagon.F2.dfimm
case 'x': // 1 string to match. .p"
if (NameR.substr(15, 2) != "or")
break;
return Intrinsic::hexagon_M4_and_xor; // "exagon.M4.and.x
or"
} }
break; break;
case 'o': // 1 string to match.
if (NameR.substr(11, 6) != "r.andn")
break;
return Intrinsic::hexagon_M4_or_andn; // "exagon.M4.or.an
dn"
case 'x': // 1 string to match.
if (NameR.substr(11, 6) != "or.and")
break;
return Intrinsic::hexagon_M4_xor_and; // "exagon.M4.xor.a
nd"
} }
break; break;
} case 's': // 7 strings to match.
break; if (NameR[11] != 'f')
case 'S': // 27 strings to match.
switch (NameR[8]) {
default: break;
case '2': // 24 strings to match.
if (NameR[9] != '.')
break; break;
switch (NameR[10]) { switch (NameR[12]) {
default: break; default: break;
case 'a': // 8 strings to match. case 'c': // 5 strings to match.
if (NameR[11] != 's') switch (NameR[13]) {
break;
switch (NameR[12]) {
default: break; default: break;
case 'l': // 4 strings to match. case 'l': // 1 string to match.
if (memcmp(NameR.data()+14, "ass", 3))
break;
return Intrinsic::hexagon_F2_sfclass; // "exagon.F2.sfcla
ss"
case 'm': // 4 strings to match.
if (NameR[14] != 'p')
break;
switch (NameR[15]) {
default: break;
case 'e': // 1 string to match.
if (NameR[16] != 'q')
break;
return Intrinsic::hexagon_F2_sfcmpeq; // "exagon.F2.sfcmp
eq"
case 'g': // 2 strings to match.
switch (NameR[16]) {
default: break;
case 'e': // 1 string to match.
return Intrinsic::hexagon_F2_sfcmpge; // "exagon.
F2.sfcmpge"
case 't': // 1 string to match.
return Intrinsic::hexagon_F2_sfcmpgt; // "exagon.
F2.sfcmpgt"
}
break;
case 'u': // 1 string to match.
if (NameR[16] != 'o')
break;
return Intrinsic::hexagon_F2_sfcmpuo; // "exagon.F2.sfcmp
uo"
}
break;
}
break;
case 'i': // 2 strings to match.
if (memcmp(NameR.data()+13, "mm.", 3))
break;
switch (NameR[16]) {
default: break;
case 'n': // 1 string to match.
return Intrinsic::hexagon_F2_sfimm_n; // "exagon.F2.sfimm
.n"
case 'p': // 1 string to match.
return Intrinsic::hexagon_F2_sfimm_p; // "exagon.F2.sfimm
.p"
}
break;
}
break;
}
break;
case 'M': // 11 strings to match.
switch (NameR[8]) {
default: break;
case '2': // 3 strings to match.
if (NameR[9] != '.')
break;
switch (NameR[10]) {
default: break;
case 'm': // 1 string to match.
if (memcmp(NameR.data()+11, "pyu.up", 6))
break;
return Intrinsic::hexagon_M2_mpyu_up; // "exagon.M2.mpyu.
up"
case 'v': // 2 strings to match.
switch (NameR[11]) {
default: break;
case 'm': // 1 string to match.
if (memcmp(NameR.data()+12, "ac2es", 5))
break;
return Intrinsic::hexagon_M2_vmac2es; // "exagon.M2.vmac2
es"
case 'r': // 1 string to match.
if (memcmp(NameR.data()+12, "adduh", 5))
break;
return Intrinsic::hexagon_M2_vradduh; // "exagon.M2.vradd
uh"
}
break;
}
break;
case '4': // 4 strings to match.
if (NameR[9] != '.')
break;
switch (NameR[10]) {
default: break;
case 'a': // 2 strings to match.
if (memcmp(NameR.data()+11, "nd.", 3))
break;
switch (NameR[14]) {
default: break;
case 'a': // 1 string to match.
if (memcmp(NameR.data()+15, "nd", 2))
break;
return Intrinsic::hexagon_M4_and_and; // "exagon.M4.and.a
nd"
case 'x': // 1 string to match.
if (memcmp(NameR.data()+15, "or", 2))
break;
return Intrinsic::hexagon_M4_and_xor; // "exagon.M4.and.x
or"
}
break;
case 'o': // 1 string to match.
if (memcmp(NameR.data()+11, "r.andn", 6))
break;
return Intrinsic::hexagon_M4_or_andn; // "exagon.M4.or.an
dn"
case 'x': // 1 string to match.
if (memcmp(NameR.data()+11, "or.and", 6))
break;
return Intrinsic::hexagon_M4_xor_and; // "exagon.M4.xor.a
nd"
}
break;
case '5': // 4 strings to match.
if (memcmp(NameR.data()+9, ".vm", 3))
break;
switch (NameR[12]) {
default: break;
case 'a': // 2 strings to match.
if (memcmp(NameR.data()+13, "cb", 2))
break;
switch (NameR[15]) {
default: break;
case 's': // 1 string to match.
if (NameR[16] != 'u')
break;
return Intrinsic::hexagon_M5_vmacbsu; // "exagon.M5.vmacb
su"
case 'u': // 1 string to match.
if (NameR[16] != 'u')
break;
return Intrinsic::hexagon_M5_vmacbuu; // "exagon.M5.vmacb
uu"
}
break;
case 'p': // 2 strings to match.
if (memcmp(NameR.data()+13, "yb", 2))
break;
switch (NameR[15]) {
default: break;
case 's': // 1 string to match.
if (NameR[16] != 'u')
break;
return Intrinsic::hexagon_M5_vmpybsu; // "exagon.M5.vmpyb
su"
case 'u': // 1 string to match.
if (NameR[16] != 'u')
break;
return Intrinsic::hexagon_M5_vmpybuu; // "exagon.M5.vmpyb
uu"
}
break;
}
break;
}
break;
case 'S': // 30 strings to match.
switch (NameR[8]) {
default: break;
case '2': // 25 strings to match.
if (NameR[9] != '.')
break;
switch (NameR[10]) {
default: break;
case 'a': // 8 strings to match.
if (NameR[11] != 's')
break;
switch (NameR[12]) {
default: break;
case 'l': // 4 strings to match.
if (NameR[13] != '.') if (NameR[13] != '.')
break; break;
switch (NameR[14]) { switch (NameR[14]) {
default: break; default: break;
case 'i': // 2 strings to match. case 'i': // 2 strings to match.
if (NameR[15] != '.') if (NameR[15] != '.')
break; break;
switch (NameR[16]) { switch (NameR[16]) {
default: break; default: break;
case 'p': // 1 string to match. case 'p': // 1 string to match.
skipping to change at line 6120 skipping to change at line 7846
return Intrinsic::hexagon_S2_asr_r_p; // "exagon. S2.asr.r.p" return Intrinsic::hexagon_S2_asr_r_p; // "exagon. S2.asr.r.p"
case 'r': // 1 string to match. case 'r': // 1 string to match.
return Intrinsic::hexagon_S2_asr_r_r; // "exagon. S2.asr.r.r" return Intrinsic::hexagon_S2_asr_r_r; // "exagon. S2.asr.r.r"
} }
break; break;
} }
break; break;
} }
break; break;
case 'c': // 1 string to match. case 'c': // 1 string to match.
if (NameR.substr(11, 6) != "lbnorm") if (memcmp(NameR.data()+11, "lbnorm", 6))
break; break;
return Intrinsic::hexagon_S2_clbnorm; // "exagon.S2.clbno rm" return Intrinsic::hexagon_S2_clbnorm; // "exagon.S2.clbno rm"
case 'i': // 1 string to match. case 'i': // 1 string to match.
if (NameR.substr(11, 6) != "nsertp") if (memcmp(NameR.data()+11, "nsertp", 6))
break; break;
return Intrinsic::hexagon_S2_insertp; // "exagon.S2.inser tp" return Intrinsic::hexagon_S2_insertp; // "exagon.S2.inser tp"
case 'l': // 6 strings to match. case 'l': // 6 strings to match.
if (NameR[11] != 's') if (NameR[11] != 's')
break; break;
switch (NameR[12]) { switch (NameR[12]) {
default: break; default: break;
case 'l': // 2 strings to match. case 'l': // 2 strings to match.
if (NameR.substr(13, 3) != ".r.") if (memcmp(NameR.data()+13, ".r.", 3))
break; break;
switch (NameR[16]) { switch (NameR[16]) {
default: break; default: break;
case 'p': // 1 string to match. case 'p': // 1 string to match.
return Intrinsic::hexagon_S2_lsl_r_p; // "exagon.S2.lsl.r .p" return Intrinsic::hexagon_S2_lsl_r_p; // "exagon.S2.lsl.r .p"
case 'r': // 1 string to match. case 'r': // 1 string to match.
return Intrinsic::hexagon_S2_lsl_r_r; // "exagon.S2.lsl.r .r" return Intrinsic::hexagon_S2_lsl_r_r; // "exagon.S2.lsl.r .r"
} }
break; break;
case 'r': // 4 strings to match. case 'r': // 4 strings to match.
skipping to change at line 6175 skipping to change at line 7901
return Intrinsic::hexagon_S2_lsr_r_p; // "exagon. S2.lsr.r.p" return Intrinsic::hexagon_S2_lsr_r_p; // "exagon. S2.lsr.r.p"
case 'r': // 1 string to match. case 'r': // 1 string to match.
return Intrinsic::hexagon_S2_lsr_r_r; // "exagon. S2.lsr.r.r" return Intrinsic::hexagon_S2_lsr_r_r; // "exagon. S2.lsr.r.r"
} }
break; break;
} }
break; break;
} }
break; break;
case 'p': // 1 string to match. case 'p': // 1 string to match.
if (NameR.substr(11, 6) != "arityp") if (memcmp(NameR.data()+11, "arityp", 6))
break; break;
return Intrinsic::hexagon_S2_parityp; // "exagon.S2.parit yp" return Intrinsic::hexagon_S2_parityp; // "exagon.S2.parit yp"
case 's': // 5 strings to match. case 's': // 5 strings to match.
switch (NameR[11]) { switch (NameR[11]) {
default: break; default: break;
case 'h': // 4 strings to match. case 'h': // 4 strings to match.
if (NameR.substr(12, 3) != "uff") if (memcmp(NameR.data()+12, "uff", 3))
break; break;
switch (NameR[15]) { switch (NameR[15]) {
default: break; default: break;
case 'e': // 2 strings to match. case 'e': // 2 strings to match.
switch (NameR[16]) { switch (NameR[16]) {
default: break; default: break;
case 'b': // 1 string to match. case 'b': // 1 string to match.
return Intrinsic::hexagon_S2_shuffeb; // "exagon. S2.shuffeb" return Intrinsic::hexagon_S2_shuffeb; // "exagon. S2.shuffeb"
case 'h': // 1 string to match. case 'h': // 1 string to match.
return Intrinsic::hexagon_S2_shuffeh; // "exagon. S2.shuffeh" return Intrinsic::hexagon_S2_shuffeh; // "exagon. S2.shuffeh"
skipping to change at line 6207 skipping to change at line 7933
default: break; default: break;
case 'b': // 1 string to match. case 'b': // 1 string to match.
return Intrinsic::hexagon_S2_shuffob; // "exagon. S2.shuffob" return Intrinsic::hexagon_S2_shuffob; // "exagon. S2.shuffob"
case 'h': // 1 string to match. case 'h': // 1 string to match.
return Intrinsic::hexagon_S2_shuffoh; // "exagon. S2.shuffoh" return Intrinsic::hexagon_S2_shuffoh; // "exagon. S2.shuffoh"
} }
break; break;
} }
break; break;
case 'v': // 1 string to match. case 'v': // 1 string to match.
if (NameR.substr(12, 5) != "sathb") if (memcmp(NameR.data()+12, "sathb", 5))
break; break;
return Intrinsic::hexagon_S2_svsathb; // "exagon.S2.svsat hb" return Intrinsic::hexagon_S2_svsathb; // "exagon.S2.svsat hb"
} }
break; break;
case 'v': // 2 strings to match. case 'v': // 3 strings to match.
if (NameR.substr(11, 3) != "sat") switch (NameR[11]) {
break;
switch (NameR[14]) {
default: break; default: break;
case 'h': // 1 string to match. case 'r': // 1 string to match.
if (NameR.substr(15, 2) != "ub") if (memcmp(NameR.data()+12, "cnegh", 5))
break; break;
return Intrinsic::hexagon_S2_vsathub; // "exagon.S2.vsath return Intrinsic::hexagon_S2_vrcnegh; // "exagon.S2.vrcne
ub" gh"
case 'w': // 1 string to match. case 's': // 2 strings to match.
if (NameR.substr(15, 2) != "uh") if (memcmp(NameR.data()+12, "at", 2))
break; break;
return Intrinsic::hexagon_S2_vsatwuh; // "exagon.S2.vsatw switch (NameR[14]) {
uh" default: break;
case 'h': // 1 string to match.
if (memcmp(NameR.data()+15, "ub", 2))
break;
return Intrinsic::hexagon_S2_vsathub; // "exagon.S2.vsath
ub"
case 'w': // 1 string to match.
if (memcmp(NameR.data()+15, "uh", 2))
break;
return Intrinsic::hexagon_S2_vsatwuh; // "exagon.S2.vsatw
uh"
}
break;
} }
break; break;
} }
break; break;
case '4': // 3 strings to match. case '4': // 5 strings to match.
if (NameR[9] != '.') if (NameR[9] != '.')
break; break;
switch (NameR[10]) { switch (NameR[10]) {
default: break; default: break;
case 'a': // 1 string to match. case 'a': // 1 string to match.
if (NameR.substr(11, 6) != "ddaddi") if (memcmp(NameR.data()+11, "ddaddi", 6))
break; break;
return Intrinsic::hexagon_S4_addaddi; // "exagon.S4.addad di" return Intrinsic::hexagon_S4_addaddi; // "exagon.S4.addad di"
case 'c': // 1 string to match.
if (memcmp(NameR.data()+11, "lbaddi", 6))
break;
return Intrinsic::hexagon_S4_clbaddi; // "exagon.S4.clbad
di"
case 'e': // 1 string to match.
if (memcmp(NameR.data()+11, "xtract", 6))
break;
return Intrinsic::hexagon_S4_extract; // "exagon.S4.extra
ct"
case 'o': // 1 string to match. case 'o': // 1 string to match.
if (NameR.substr(11, 6) != "r.andi") if (memcmp(NameR.data()+11, "r.andi", 6))
break; break;
return Intrinsic::hexagon_S4_or_andi; // "exagon.S4.or.an di" return Intrinsic::hexagon_S4_or_andi; // "exagon.S4.or.an di"
case 's': // 1 string to match. case 's': // 1 string to match.
if (NameR.substr(11, 6) != "ubaddi") if (memcmp(NameR.data()+11, "ubaddi", 6))
break; break;
return Intrinsic::hexagon_S4_subaddi; // "exagon.S4.subad di" return Intrinsic::hexagon_S4_subaddi; // "exagon.S4.subad di"
} }
break; break;
} }
break; break;
} }
break; break;
case 18: // 69 strings to match. case 18: // 103 strings to match.
if (NameR.substr(0, 7) != "exagon.") if (memcmp(NameR.data()+0, "exagon.", 7))
break; break;
switch (NameR[7]) { switch (NameR[7]) {
default: break; default: break;
case 'A': // 14 strings to match. case 'A': // 26 strings to match.
switch (NameR[8]) { switch (NameR[8]) {
default: break; default: break;
case '2': // 10 strings to match. case '2': // 11 strings to match.
if (NameR[9] != '.') if (NameR[9] != '.')
break; break;
switch (NameR[10]) { switch (NameR[10]) {
default: break; default: break;
case 'c': // 1 string to match. case 'c': // 1 string to match.
if (NameR.substr(11, 7) != "ombinew") if (memcmp(NameR.data()+11, "ombinew", 7))
break; break;
return Intrinsic::hexagon_A2_combinew; // "exagon.A2.combi new" return Intrinsic::hexagon_A2_combinew; // "exagon.A2.combi new"
case 'r': // 1 string to match.
if (memcmp(NameR.data()+11, "oundsat", 7))
break;
return Intrinsic::hexagon_A2_roundsat; // "exagon.A2.round
sat"
case 's': // 2 strings to match. case 's': // 2 strings to match.
if (NameR[11] != 'v') if (NameR[11] != 'v')
break; break;
switch (NameR[12]) { switch (NameR[12]) {
default: break; default: break;
case 'a': // 1 string to match. case 'a': // 1 string to match.
if (NameR.substr(13, 5) != "dduhs") if (memcmp(NameR.data()+13, "dduhs", 5))
break; break;
return Intrinsic::hexagon_A2_svadduhs; // "exagon.A2.svadd uhs" return Intrinsic::hexagon_A2_svadduhs; // "exagon.A2.svadd uhs"
case 's': // 1 string to match. case 's': // 1 string to match.
if (NameR.substr(13, 5) != "ubuhs") if (memcmp(NameR.data()+13, "ubuhs", 5))
break; break;
return Intrinsic::hexagon_A2_svsubuhs; // "exagon.A2.svsub uhs" return Intrinsic::hexagon_A2_svsubuhs; // "exagon.A2.svsub uhs"
} }
break; break;
case 'v': // 7 strings to match. case 'v': // 7 strings to match.
switch (NameR[11]) { switch (NameR[11]) {
default: break; default: break;
case 'a': // 2 strings to match. case 'a': // 2 strings to match.
if (NameR.substr(12, 2) != "bs") if (memcmp(NameR.data()+12, "bs", 2))
break; break;
switch (NameR[14]) { switch (NameR[14]) {
default: break; default: break;
case 'h': // 1 string to match. case 'h': // 1 string to match.
if (NameR.substr(15, 3) != "sat") if (memcmp(NameR.data()+15, "sat", 3))
break; break;
return Intrinsic::hexagon_A2_vabshsat; // "exagon.A2.vabsh sat" return Intrinsic::hexagon_A2_vabshsat; // "exagon.A2.vabsh sat"
case 'w': // 1 string to match. case 'w': // 1 string to match.
if (NameR.substr(15, 3) != "sat") if (memcmp(NameR.data()+15, "sat", 3))
break; break;
return Intrinsic::hexagon_A2_vabswsat; // "exagon.A2.vabsw sat" return Intrinsic::hexagon_A2_vabswsat; // "exagon.A2.vabsw sat"
} }
break; break;
case 'c': // 3 strings to match. case 'c': // 3 strings to match.
if (NameR.substr(12, 2) != "mp") if (memcmp(NameR.data()+12, "mp", 2))
break; break;
switch (NameR[14]) { switch (NameR[14]) {
default: break; default: break;
case 'b': // 1 string to match. case 'b': // 1 string to match.
if (NameR.substr(15, 3) != "gtu") if (memcmp(NameR.data()+15, "gtu", 3))
break; break;
return Intrinsic::hexagon_A2_vcmpbgtu; // "exagon.A2.vcmpb gtu" return Intrinsic::hexagon_A2_vcmpbgtu; // "exagon.A2.vcmpb gtu"
case 'h': // 1 string to match. case 'h': // 1 string to match.
if (NameR.substr(15, 3) != "gtu") if (memcmp(NameR.data()+15, "gtu", 3))
break; break;
return Intrinsic::hexagon_A2_vcmphgtu; // "exagon.A2.vcmph gtu" return Intrinsic::hexagon_A2_vcmphgtu; // "exagon.A2.vcmph gtu"
case 'w': // 1 string to match. case 'w': // 1 string to match.
if (NameR.substr(15, 3) != "gtu") if (memcmp(NameR.data()+15, "gtu", 3))
break; break;
return Intrinsic::hexagon_A2_vcmpwgtu; // "exagon.A2.vcmpw gtu" return Intrinsic::hexagon_A2_vcmpwgtu; // "exagon.A2.vcmpw gtu"
} }
break; break;
case 'n': // 2 strings to match. case 'n': // 2 strings to match.
if (NameR.substr(12, 3) != "avg") if (memcmp(NameR.data()+12, "avg", 3))
break; break;
switch (NameR[15]) { switch (NameR[15]) {
default: break; default: break;
case 'h': // 1 string to match. case 'h': // 1 string to match.
if (NameR.substr(16, 2) != "cr") if (memcmp(NameR.data()+16, "cr", 2))
break; break;
return Intrinsic::hexagon_A2_vnavghcr; // "exagon.A2.vnavg hcr" return Intrinsic::hexagon_A2_vnavghcr; // "exagon.A2.vnavg hcr"
case 'w': // 1 string to match. case 'w': // 1 string to match.
if (NameR.substr(16, 2) != "cr") if (memcmp(NameR.data()+16, "cr", 2))
break; break;
return Intrinsic::hexagon_A2_vnavgwcr; // "exagon.A2.vnavg wcr" return Intrinsic::hexagon_A2_vnavgwcr; // "exagon.A2.vnavg wcr"
} }
break; break;
} }
break; break;
} }
break; break;
case '4': // 4 strings to match. case '4': // 14 strings to match.
if (NameR[9] != '.') if (NameR[9] != '.')
break; break;
switch (NameR[10]) { switch (NameR[10]) {
default: break; default: break;
case 'b': // 1 string to match.
if (memcmp(NameR.data()+11, "itsplit", 7))
break;
return Intrinsic::hexagon_A4_bitsplit; // "exagon.A4.bitsp
lit"
case 'c': // 2 strings to match.
if (memcmp(NameR.data()+11, "mp", 2))
break;
switch (NameR[13]) {
default: break;
case 'b': // 1 string to match.
if (memcmp(NameR.data()+14, "gtui", 4))
break;
return Intrinsic::hexagon_A4_cmpbgtui; // "exagon.A4.cmpbg
tui"
case 'h': // 1 string to match.
if (memcmp(NameR.data()+14, "gtui", 4))
break;
return Intrinsic::hexagon_A4_cmphgtui; // "exagon.A4.cmphg
tui"
}
break;
case 'm': // 1 string to match. case 'm': // 1 string to match.
if (NameR.substr(11, 7) != "odwrapu") if (memcmp(NameR.data()+11, "odwrapu", 7))
break; break;
return Intrinsic::hexagon_A4_modwrapu; // "exagon.A4.modwr apu" return Intrinsic::hexagon_A4_modwrapu; // "exagon.A4.modwr apu"
case 'r': // 3 strings to match. case 'r': // 3 strings to match.
switch (NameR[11]) { switch (NameR[11]) {
default: break; default: break;
case 'c': // 1 string to match. case 'c': // 1 string to match.
if (NameR.substr(12, 6) != "mpneqi") if (memcmp(NameR.data()+12, "mpneqi", 6))
break; break;
return Intrinsic::hexagon_A4_rcmpneqi; // "exagon.A4.rcmpn eqi" return Intrinsic::hexagon_A4_rcmpneqi; // "exagon.A4.rcmpn eqi"
case 'o': // 2 strings to match. case 'o': // 2 strings to match.
if (NameR.substr(12, 5) != "und.r") if (memcmp(NameR.data()+12, "und.r", 5))
break; break;
switch (NameR[17]) { switch (NameR[17]) {
default: break; default: break;
case 'i': // 1 string to match. case 'i': // 1 string to match.
return Intrinsic::hexagon_A4_round_ri; // "exagon.A4.round .ri" return Intrinsic::hexagon_A4_round_ri; // "exagon.A4.round .ri"
case 'r': // 1 string to match. case 'r': // 1 string to match.
return Intrinsic::hexagon_A4_round_rr; // "exagon.A4.round .rr" return Intrinsic::hexagon_A4_round_rr; // "exagon.A4.round .rr"
} }
break; break;
} }
break; break;
case 't': // 1 string to match.
if (memcmp(NameR.data()+11, "lbmatch", 7))
break;
return Intrinsic::hexagon_A4_tlbmatch; // "exagon.A4.tlbma
tch"
case 'v': // 6 strings to match.
if (memcmp(NameR.data()+11, "cmp", 3))
break;
switch (NameR[14]) {
default: break;
case 'b': // 2 strings to match.
switch (NameR[15]) {
default: break;
case 'e': // 1 string to match.
if (memcmp(NameR.data()+16, "qi", 2))
break;
return Intrinsic::hexagon_A4_vcmpbeqi; // "exagon.A4.vcmpb
eqi"
case 'g': // 1 string to match.
if (memcmp(NameR.data()+16, "ti", 2))
break;
return Intrinsic::hexagon_A4_vcmpbgti; // "exagon.A4.vcmpb
gti"
}
break;
case 'h': // 2 strings to match.
switch (NameR[15]) {
default: break;
case 'e': // 1 string to match.
if (memcmp(NameR.data()+16, "qi", 2))
break;
return Intrinsic::hexagon_A4_vcmpheqi; // "exagon.A4.vcmph
eqi"
case 'g': // 1 string to match.
if (memcmp(NameR.data()+16, "ti", 2))
break;
return Intrinsic::hexagon_A4_vcmphgti; // "exagon.A4.vcmph
gti"
}
break;
case 'w': // 2 strings to match.
switch (NameR[15]) {
default: break;
case 'e': // 1 string to match.
if (memcmp(NameR.data()+16, "qi", 2))
break;
return Intrinsic::hexagon_A4_vcmpweqi; // "exagon.A4.vcmpw
eqi"
case 'g': // 1 string to match.
if (memcmp(NameR.data()+16, "ti", 2))
break;
return Intrinsic::hexagon_A4_vcmpwgti; // "exagon.A4.vcmpw
gti"
}
break;
}
break;
} }
break; break;
case '5': // 1 string to match.
if (memcmp(NameR.data()+9, ".vaddhubs", 9))
break;
return Intrinsic::hexagon_A5_vaddhubs; // "exagon.A5.vaddh
ubs"
} }
break; break;
case 'C': // 3 strings to match. case 'C': // 5 strings to match.
switch (NameR[8]) { switch (NameR[8]) {
default: break; default: break;
case '2': // 1 string to match. case '2': // 1 string to match.
if (NameR.substr(9, 9) != ".bitsclri") if (memcmp(NameR.data()+9, ".bitsclri", 9))
break; break;
return Intrinsic::hexagon_C2_bitsclri; // "exagon.C2.bitsc lri" return Intrinsic::hexagon_C2_bitsclri; // "exagon.C2.bitsc lri"
case '4': // 2 strings to match. case '4': // 4 strings to match.
if (NameR[9] != '.') if (NameR[9] != '.')
break; break;
switch (NameR[10]) { switch (NameR[10]) {
default: break; default: break;
case 'a': // 1 string to match. case 'a': // 1 string to match.
if (NameR.substr(11, 7) != "nd.andn") if (memcmp(NameR.data()+11, "nd.andn", 7))
break; break;
return Intrinsic::hexagon_C4_and_andn; // "exagon.C4.and.a ndn" return Intrinsic::hexagon_C4_and_andn; // "exagon.C4.and.a ndn"
case 'c': // 1 string to match. case 'c': // 1 string to match.
if (NameR.substr(11, 7) != "mplteui") if (memcmp(NameR.data()+11, "mplteui", 7))
break; break;
return Intrinsic::hexagon_C4_cmplteui; // "exagon.C4.cmplt eui" return Intrinsic::hexagon_C4_cmplteui; // "exagon.C4.cmplt eui"
case 'n': // 2 strings to match.
if (memcmp(NameR.data()+11, "bits", 4))
break;
switch (NameR[15]) {
default: break;
case 'c': // 1 string to match.
if (memcmp(NameR.data()+16, "lr", 2))
break;
return Intrinsic::hexagon_C4_nbitsclr; // "exagon.C4.nbits
clr"
case 's': // 1 string to match.
if (memcmp(NameR.data()+16, "et", 2))
break;
return Intrinsic::hexagon_C4_nbitsset; // "exagon.C4.nbits
set"
}
break;
}
break;
}
break;
case 'F': // 8 strings to match.
if (memcmp(NameR.data()+8, "2.", 2))
break;
switch (NameR[10]) {
default: break;
case 'd': // 4 strings to match.
if (memcmp(NameR.data()+11, "ff", 2))
break;
switch (NameR[13]) {
default: break;
case 'i': // 3 strings to match.
if (memcmp(NameR.data()+14, "xup", 3))
break;
switch (NameR[17]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::hexagon_F2_dffixupd; // "exagon.F2.dffix
upd"
case 'n': // 1 string to match.
return Intrinsic::hexagon_F2_dffixupn; // "exagon.F2.dffix
upn"
case 'r': // 1 string to match.
return Intrinsic::hexagon_F2_dffixupr; // "exagon.F2.dffix
upr"
}
break;
case 'm': // 1 string to match.
if (memcmp(NameR.data()+14, "a.sc", 4))
break;
return Intrinsic::hexagon_F2_dffma_sc; // "exagon.F2.dffma
.sc"
}
break;
case 's': // 4 strings to match.
if (memcmp(NameR.data()+11, "ff", 2))
break;
switch (NameR[13]) {
default: break;
case 'i': // 3 strings to match.
if (memcmp(NameR.data()+14, "xup", 3))
break;
switch (NameR[17]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::hexagon_F2_sffixupd; // "exagon.F2.sffix
upd"
case 'n': // 1 string to match.
return Intrinsic::hexagon_F2_sffixupn; // "exagon.F2.sffix
upn"
case 'r': // 1 string to match.
return Intrinsic::hexagon_F2_sffixupr; // "exagon.F2.sffix
upr"
}
break;
case 'm': // 1 string to match.
if (memcmp(NameR.data()+14, "a.sc", 4))
break;
return Intrinsic::hexagon_F2_sffma_sc; // "exagon.F2.sffma
.sc"
} }
break; break;
} }
break; break;
case 'M': // 20 strings to match. case 'M': // 29 strings to match.
switch (NameR[8]) { switch (NameR[8]) {
default: break; default: break;
case '2': // 17 strings to match. case '2': // 18 strings to match.
if (NameR[9] != '.') if (NameR[9] != '.')
break; break;
switch (NameR[10]) { switch (NameR[10]) {
default: break; default: break;
case 'c': // 10 strings to match. case 'c': // 10 strings to match.
switch (NameR[11]) { switch (NameR[11]) {
default: break; default: break;
case 'm': // 8 strings to match. case 'm': // 8 strings to match.
switch (NameR[12]) { switch (NameR[12]) {
default: break; default: break;
case 'a': // 4 strings to match. case 'a': // 4 strings to match.
if (NameR[13] != 'c') if (NameR[13] != 'c')
break; break;
switch (NameR[14]) { switch (NameR[14]) {
default: break; default: break;
case 'i': // 1 string to match. case 'i': // 1 string to match.
if (NameR.substr(15, 3) != ".s0") if (memcmp(NameR.data()+15, ".s0", 3))
break; break;
return Intrinsic::hexagon_M2_cmaci_s0; // "exagon. M2.cmaci.s0" return Intrinsic::hexagon_M2_cmaci_s0; // "exagon. M2.cmaci.s0"
case 'r': // 1 string to match. case 'r': // 1 string to match.
if (NameR.substr(15, 3) != ".s0") if (memcmp(NameR.data()+15, ".s0", 3))
break; break;
return Intrinsic::hexagon_M2_cmacr_s0; // "exagon. M2.cmacr.s0" return Intrinsic::hexagon_M2_cmacr_s0; // "exagon. M2.cmacr.s0"
case 's': // 2 strings to match. case 's': // 2 strings to match.
if (NameR.substr(15, 2) != ".s") if (memcmp(NameR.data()+15, ".s", 2))
break; break;
switch (NameR[17]) { switch (NameR[17]) {
default: break; default: break;
case '0': // 1 string to match. case '0': // 1 string to match.
return Intrinsic::hexagon_M2_cmacs_s0; // "exagon. M2.cmacs.s0" return Intrinsic::hexagon_M2_cmacs_s0; // "exagon. M2.cmacs.s0"
case '1': // 1 string to match. case '1': // 1 string to match.
return Intrinsic::hexagon_M2_cmacs_s1; // "exagon. M2.cmacs.s1" return Intrinsic::hexagon_M2_cmacs_s1; // "exagon. M2.cmacs.s1"
} }
break; break;
} }
break; break;
case 'p': // 4 strings to match. case 'p': // 4 strings to match.
if (NameR[13] != 'y') if (NameR[13] != 'y')
break; break;
switch (NameR[14]) { switch (NameR[14]) {
default: break; default: break;
case 'i': // 1 string to match. case 'i': // 1 string to match.
if (NameR.substr(15, 3) != ".s0") if (memcmp(NameR.data()+15, ".s0", 3))
break; break;
return Intrinsic::hexagon_M2_cmpyi_s0; // "exagon. M2.cmpyi.s0" return Intrinsic::hexagon_M2_cmpyi_s0; // "exagon. M2.cmpyi.s0"
case 'r': // 1 string to match. case 'r': // 1 string to match.
if (NameR.substr(15, 3) != ".s0") if (memcmp(NameR.data()+15, ".s0", 3))
break; break;
return Intrinsic::hexagon_M2_cmpyr_s0; // "exagon. M2.cmpyr.s0" return Intrinsic::hexagon_M2_cmpyr_s0; // "exagon. M2.cmpyr.s0"
case 's': // 2 strings to match. case 's': // 2 strings to match.
if (NameR.substr(15, 2) != ".s") if (memcmp(NameR.data()+15, ".s", 2))
break; break;
switch (NameR[17]) { switch (NameR[17]) {
default: break; default: break;
case '0': // 1 string to match. case '0': // 1 string to match.
return Intrinsic::hexagon_M2_cmpys_s0; // "exagon. M2.cmpys.s0" return Intrinsic::hexagon_M2_cmpys_s0; // "exagon. M2.cmpys.s0"
case '1': // 1 string to match. case '1': // 1 string to match.
return Intrinsic::hexagon_M2_cmpys_s1; // "exagon. M2.cmpys.s1" return Intrinsic::hexagon_M2_cmpys_s1; // "exagon. M2.cmpys.s1"
} }
break; break;
} }
break; break;
} }
break; break;
case 'n': // 2 strings to match. case 'n': // 2 strings to match.
if (NameR.substr(12, 5) != "acs.s") if (memcmp(NameR.data()+12, "acs.s", 5))
break; break;
switch (NameR[17]) { switch (NameR[17]) {
default: break; default: break;
case '0': // 1 string to match. case '0': // 1 string to match.
return Intrinsic::hexagon_M2_cnacs_s0; // "exagon.M2.cnacs .s0" return Intrinsic::hexagon_M2_cnacs_s0; // "exagon.M2.cnacs .s0"
case '1': // 1 string to match. case '1': // 1 string to match.
return Intrinsic::hexagon_M2_cnacs_s1; // "exagon.M2.cnacs .s1" return Intrinsic::hexagon_M2_cnacs_s1; // "exagon.M2.cnacs .s1"
} }
break; break;
} }
break; break;
case 'm': // 4 strings to match. case 'm': // 5 strings to match.
if (NameR.substr(11, 3) != "mpy") switch (NameR[11]) {
break;
switch (NameR[14]) {
default: break; default: break;
case 'h': // 2 strings to match. case 'm': // 4 strings to match.
if (NameR.substr(15, 2) != ".s") if (memcmp(NameR.data()+12, "py", 2))
break; break;
switch (NameR[17]) { switch (NameR[14]) {
default: break; default: break;
case '0': // 1 string to match. case 'h': // 2 strings to match.
return Intrinsic::hexagon_M2_mmpyh_s0; // "exagon.M2.mmpyh if (memcmp(NameR.data()+15, ".s", 2))
.s0" break;
case '1': // 1 string to match. switch (NameR[17]) {
return Intrinsic::hexagon_M2_mmpyh_s1; // "exagon.M2.mmpyh default: break;
.s1" case '0': // 1 string to match.
} return Intrinsic::hexagon_M2_mmpyh_s0; // "exagon.
break; M2.mmpyh.s0"
case 'l': // 2 strings to match. case '1': // 1 string to match.
if (NameR.substr(15, 2) != ".s") return Intrinsic::hexagon_M2_mmpyh_s1; // "exagon.
M2.mmpyh.s1"
}
break;
case 'l': // 2 strings to match.
if (memcmp(NameR.data()+15, ".s", 2))
break;
switch (NameR[17]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mmpyl_s0; // "exagon.
M2.mmpyl.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mmpyl_s1; // "exagon.
M2.mmpyl.s1"
}
break; break;
switch (NameR[17]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mmpyl_s0; // "exagon.M2.mmpyl
.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mmpyl_s1; // "exagon.M2.mmpyl
.s1"
} }
break; break;
case 'p': // 1 string to match.
if (memcmp(NameR.data()+12, "ysu.up", 6))
break;
return Intrinsic::hexagon_M2_mpysu_up; // "exagon.M2.mpysu
.up"
} }
break; break;
case 'v': // 2 strings to match. case 'v': // 2 strings to match.
if (NameR.substr(11, 2) != "rm") if (memcmp(NameR.data()+11, "rm", 2))
break; break;
switch (NameR[13]) { switch (NameR[13]) {
default: break; default: break;
case 'a': // 1 string to match. case 'a': // 1 string to match.
if (NameR.substr(14, 4) != "c.s0") if (memcmp(NameR.data()+14, "c.s0", 4))
break; break;
return Intrinsic::hexagon_M2_vrmac_s0; // "exagon.M2.vrmac .s0" return Intrinsic::hexagon_M2_vrmac_s0; // "exagon.M2.vrmac .s0"
case 'p': // 1 string to match. case 'p': // 1 string to match.
if (NameR.substr(14, 4) != "y.s0") if (memcmp(NameR.data()+14, "y.s0", 4))
break; break;
return Intrinsic::hexagon_M2_vrmpy_s0; // "exagon.M2.vrmpy .s0" return Intrinsic::hexagon_M2_vrmpy_s0; // "exagon.M2.vrmpy .s0"
} }
break; break;
case 'x': // 1 string to match. case 'x': // 1 string to match.
if (NameR.substr(11, 7) != "or.xacc") if (memcmp(NameR.data()+11, "or.xacc", 7))
break; break;
return Intrinsic::hexagon_M2_xor_xacc; // "exagon.M2.xor.x acc" return Intrinsic::hexagon_M2_xor_xacc; // "exagon.M2.xor.x acc"
} }
break; break;
case '4': // 3 strings to match. case '4': // 5 strings to match.
if (NameR[9] != '.') if (NameR[9] != '.')
break; break;
switch (NameR[10]) { switch (NameR[10]) {
default: break; default: break;
case 'a': // 1 string to match. case 'a': // 1 string to match.
if (NameR.substr(11, 7) != "nd.andn") if (memcmp(NameR.data()+11, "nd.andn", 7))
break; break;
return Intrinsic::hexagon_M4_and_andn; // "exagon.M4.and.a ndn" return Intrinsic::hexagon_M4_and_andn; // "exagon.M4.and.a ndn"
case 'c': // 2 strings to match.
if (memcmp(NameR.data()+11, "mpy", 3))
break;
switch (NameR[14]) {
default: break;
case 'i': // 1 string to match.
if (memcmp(NameR.data()+15, ".wh", 3))
break;
return Intrinsic::hexagon_M4_cmpyi_wh; // "exagon.M4.cmpyi
.wh"
case 'r': // 1 string to match.
if (memcmp(NameR.data()+15, ".wh", 3))
break;
return Intrinsic::hexagon_M4_cmpyr_wh; // "exagon.M4.cmpyr
.wh"
}
break;
case 'x': // 2 strings to match. case 'x': // 2 strings to match.
if (NameR.substr(11, 3) != "or.") if (memcmp(NameR.data()+11, "or.", 3))
break; break;
switch (NameR[14]) { switch (NameR[14]) {
default: break; default: break;
case 'a': // 1 string to match. case 'a': // 1 string to match.
if (NameR.substr(15, 3) != "ndn") if (memcmp(NameR.data()+15, "ndn", 3))
break; break;
return Intrinsic::hexagon_M4_xor_andn; // "exagon.M4.xor.a ndn" return Intrinsic::hexagon_M4_xor_andn; // "exagon.M4.xor.a ndn"
case 'x': // 1 string to match. case 'x': // 1 string to match.
if (NameR.substr(15, 3) != "acc") if (memcmp(NameR.data()+15, "acc", 3))
break; break;
return Intrinsic::hexagon_M4_xor_xacc; // "exagon.M4.xor.x acc" return Intrinsic::hexagon_M4_xor_xacc; // "exagon.M4.xor.x acc"
} }
break; break;
} }
break; break;
case '5': // 6 strings to match.
if (memcmp(NameR.data()+9, ".v", 2))
break;
switch (NameR[11]) {
default: break;
case 'd': // 2 strings to match.
if (NameR[12] != 'm')
break;
switch (NameR[13]) {
default: break;
case 'a': // 1 string to match.
if (memcmp(NameR.data()+14, "cbsu", 4))
break;
return Intrinsic::hexagon_M5_vdmacbsu; // "exagon.M5.vdmac
bsu"
case 'p': // 1 string to match.
if (memcmp(NameR.data()+14, "ybsu", 4))
break;
return Intrinsic::hexagon_M5_vdmpybsu; // "exagon.M5.vdmpy
bsu"
}
break;
case 'r': // 4 strings to match.
if (NameR[12] != 'm')
break;
switch (NameR[13]) {
default: break;
case 'a': // 2 strings to match.
if (memcmp(NameR.data()+14, "cb", 2))
break;
switch (NameR[16]) {
default: break;
case 's': // 1 string to match.
if (NameR[17] != 'u')
break;
return Intrinsic::hexagon_M5_vrmacbsu; // "exagon.M5.vrmac
bsu"
case 'u': // 1 string to match.
if (NameR[17] != 'u')
break;
return Intrinsic::hexagon_M5_vrmacbuu; // "exagon.M5.vrmac
buu"
}
break;
case 'p': // 2 strings to match.
if (memcmp(NameR.data()+14, "yb", 2))
break;
switch (NameR[16]) {
default: break;
case 's': // 1 string to match.
if (NameR[17] != 'u')
break;
return Intrinsic::hexagon_M5_vrmpybsu; // "exagon.M5.vrmpy
bsu"
case 'u': // 1 string to match.
if (NameR[17] != 'u')
break;
return Intrinsic::hexagon_M5_vrmpybuu; // "exagon.M5.vrmpy
buu"
}
break;
}
break;
}
break;
} }
break; break;
case 'S': // 32 strings to match. case 'S': // 35 strings to match.
switch (NameR[8]) { switch (NameR[8]) {
default: break; default: break;
case '2': // 31 strings to match. case '2': // 31 strings to match.
if (NameR[9] != '.') if (NameR[9] != '.')
break; break;
switch (NameR[10]) { switch (NameR[10]) {
default: break; default: break;
case 'a': // 8 strings to match. case 'a': // 8 strings to match.
if (NameR[11] != 's') if (NameR[11] != 's')
break; break;
switch (NameR[12]) { switch (NameR[12]) {
default: break; default: break;
case 'l': // 4 strings to match. case 'l': // 4 strings to match.
if (NameR[13] != '.') if (NameR[13] != '.')
break; break;
switch (NameR[14]) { switch (NameR[14]) {
default: break; default: break;
case 'i': // 2 strings to match. case 'i': // 2 strings to match.
if (NameR.substr(15, 2) != ".v") if (memcmp(NameR.data()+15, ".v", 2))
break; break;
switch (NameR[17]) { switch (NameR[17]) {
default: break; default: break;
case 'h': // 1 string to match. case 'h': // 1 string to match.
return Intrinsic::hexagon_S2_asl_i_vh; // "exagon. S2.asl.i.vh" return Intrinsic::hexagon_S2_asl_i_vh; // "exagon. S2.asl.i.vh"
case 'w': // 1 string to match. case 'w': // 1 string to match.
return Intrinsic::hexagon_S2_asl_i_vw; // "exagon. S2.asl.i.vw" return Intrinsic::hexagon_S2_asl_i_vw; // "exagon. S2.asl.i.vw"
} }
break; break;
case 'r': // 2 strings to match. case 'r': // 2 strings to match.
if (NameR.substr(15, 2) != ".v") if (memcmp(NameR.data()+15, ".v", 2))
break; break;
switch (NameR[17]) { switch (NameR[17]) {
default: break; default: break;
case 'h': // 1 string to match. case 'h': // 1 string to match.
return Intrinsic::hexagon_S2_asl_r_vh; // "exagon. S2.asl.r.vh" return Intrinsic::hexagon_S2_asl_r_vh; // "exagon. S2.asl.r.vh"
case 'w': // 1 string to match. case 'w': // 1 string to match.
return Intrinsic::hexagon_S2_asl_r_vw; // "exagon. S2.asl.r.vw" return Intrinsic::hexagon_S2_asl_r_vw; // "exagon. S2.asl.r.vw"
} }
break; break;
} }
break; break;
case 'r': // 4 strings to match. case 'r': // 4 strings to match.
if (NameR[13] != '.') if (NameR[13] != '.')
break; break;
switch (NameR[14]) { switch (NameR[14]) {
default: break; default: break;
case 'i': // 2 strings to match. case 'i': // 2 strings to match.
if (NameR.substr(15, 2) != ".v") if (memcmp(NameR.data()+15, ".v", 2))
break; break;
switch (NameR[17]) { switch (NameR[17]) {
default: break; default: break;
case 'h': // 1 string to match. case 'h': // 1 string to match.
return Intrinsic::hexagon_S2_asr_i_vh; // "exagon. S2.asr.i.vh" return Intrinsic::hexagon_S2_asr_i_vh; // "exagon. S2.asr.i.vh"
case 'w': // 1 string to match. case 'w': // 1 string to match.
return Intrinsic::hexagon_S2_asr_i_vw; // "exagon. S2.asr.i.vw" return Intrinsic::hexagon_S2_asr_i_vw; // "exagon. S2.asr.i.vw"
} }
break; break;
case 'r': // 2 strings to match. case 'r': // 2 strings to match.
if (NameR.substr(15, 2) != ".v") if (memcmp(NameR.data()+15, ".v", 2))
break; break;
switch (NameR[17]) { switch (NameR[17]) {
default: break; default: break;
case 'h': // 1 string to match. case 'h': // 1 string to match.
return Intrinsic::hexagon_S2_asr_r_vh; // "exagon. S2.asr.r.vh" return Intrinsic::hexagon_S2_asr_r_vh; // "exagon. S2.asr.r.vh"
case 'w': // 1 string to match. case 'w': // 1 string to match.
return Intrinsic::hexagon_S2_asr_r_vw; // "exagon. S2.asr.r.vw" return Intrinsic::hexagon_S2_asr_r_vw; // "exagon. S2.asr.r.vw"
} }
break; break;
} }
break; break;
} }
break; break;
case 'c': // 2 strings to match. case 'c': // 2 strings to match.
if (NameR.substr(11, 6) != "lrbit.") if (memcmp(NameR.data()+11, "lrbit.", 6))
break; break;
switch (NameR[17]) { switch (NameR[17]) {
default: break; default: break;
case 'i': // 1 string to match. case 'i': // 1 string to match.
return Intrinsic::hexagon_S2_clrbit_i; // "exagon.S2.clrbi t.i" return Intrinsic::hexagon_S2_clrbit_i; // "exagon.S2.clrbi t.i"
case 'r': // 1 string to match. case 'r': // 1 string to match.
return Intrinsic::hexagon_S2_clrbit_r; // "exagon.S2.clrbi t.r" return Intrinsic::hexagon_S2_clrbit_r; // "exagon.S2.clrbi t.r"
} }
break; break;
case 'e': // 1 string to match. case 'e': // 1 string to match.
if (NameR.substr(11, 7) != "xtractu") if (memcmp(NameR.data()+11, "xtractu", 7))
break; break;
return Intrinsic::hexagon_S2_extractu; // "exagon.S2.extra ctu" return Intrinsic::hexagon_S2_extractu; // "exagon.S2.extra ctu"
case 'l': // 6 strings to match. case 'l': // 6 strings to match.
if (NameR[11] != 's') if (NameR[11] != 's')
break; break;
switch (NameR[12]) { switch (NameR[12]) {
default: break; default: break;
case 'l': // 2 strings to match. case 'l': // 2 strings to match.
if (NameR.substr(13, 4) != ".r.v") if (memcmp(NameR.data()+13, ".r.v", 4))
break; break;
switch (NameR[17]) { switch (NameR[17]) {
default: break; default: break;
case 'h': // 1 string to match. case 'h': // 1 string to match.
return Intrinsic::hexagon_S2_lsl_r_vh; // "exagon.S2.lsl.r .vh" return Intrinsic::hexagon_S2_lsl_r_vh; // "exagon.S2.lsl.r .vh"
case 'w': // 1 string to match. case 'w': // 1 string to match.
return Intrinsic::hexagon_S2_lsl_r_vw; // "exagon.S2.lsl.r .vw" return Intrinsic::hexagon_S2_lsl_r_vw; // "exagon.S2.lsl.r .vw"
} }
break; break;
case 'r': // 4 strings to match. case 'r': // 4 strings to match.
if (NameR[13] != '.') if (NameR[13] != '.')
break; break;
switch (NameR[14]) { switch (NameR[14]) {
default: break; default: break;
case 'i': // 2 strings to match. case 'i': // 2 strings to match.
if (NameR.substr(15, 2) != ".v") if (memcmp(NameR.data()+15, ".v", 2))
break; break;
switch (NameR[17]) { switch (NameR[17]) {
default: break; default: break;
case 'h': // 1 string to match. case 'h': // 1 string to match.
return Intrinsic::hexagon_S2_lsr_i_vh; // "exagon. S2.lsr.i.vh" return Intrinsic::hexagon_S2_lsr_i_vh; // "exagon. S2.lsr.i.vh"
case 'w': // 1 string to match. case 'w': // 1 string to match.
return Intrinsic::hexagon_S2_lsr_i_vw; // "exagon. S2.lsr.i.vw" return Intrinsic::hexagon_S2_lsr_i_vw; // "exagon. S2.lsr.i.vw"
} }
break; break;
case 'r': // 2 strings to match. case 'r': // 2 strings to match.
if (NameR.substr(15, 2) != ".v") if (memcmp(NameR.data()+15, ".v", 2))
break; break;
switch (NameR[17]) { switch (NameR[17]) {
default: break; default: break;
case 'h': // 1 string to match. case 'h': // 1 string to match.
return Intrinsic::hexagon_S2_lsr_r_vh; // "exagon. S2.lsr.r.vh" return Intrinsic::hexagon_S2_lsr_r_vh; // "exagon. S2.lsr.r.vh"
case 'w': // 1 string to match. case 'w': // 1 string to match.
return Intrinsic::hexagon_S2_lsr_r_vw; // "exagon. S2.lsr.r.vw" return Intrinsic::hexagon_S2_lsr_r_vw; // "exagon. S2.lsr.r.vw"
} }
break; break;
} }
break; break;
} }
break; break;
case 's': // 3 strings to match. case 's': // 3 strings to match.
switch (NameR[11]) { switch (NameR[11]) {
default: break; default: break;
case 'e': // 2 strings to match. case 'e': // 2 strings to match.
if (NameR.substr(12, 5) != "tbit.") if (memcmp(NameR.data()+12, "tbit.", 5))
break; break;
switch (NameR[17]) { switch (NameR[17]) {
default: break; default: break;
case 'i': // 1 string to match. case 'i': // 1 string to match.
return Intrinsic::hexagon_S2_setbit_i; // "exagon.S2.setbi t.i" return Intrinsic::hexagon_S2_setbit_i; // "exagon.S2.setbi t.i"
case 'r': // 1 string to match. case 'r': // 1 string to match.
return Intrinsic::hexagon_S2_setbit_r; // "exagon.S2.setbi t.r" return Intrinsic::hexagon_S2_setbit_r; // "exagon.S2.setbi t.r"
} }
break; break;
case 'v': // 1 string to match. case 'v': // 1 string to match.
if (NameR.substr(12, 6) != "sathub") if (memcmp(NameR.data()+12, "sathub", 6))
break; break;
return Intrinsic::hexagon_S2_svsathub; // "exagon.S2.svsat hub" return Intrinsic::hexagon_S2_svsathub; // "exagon.S2.svsat hub"
} }
break; break;
case 't': // 2 strings to match. case 't': // 2 strings to match.
if (NameR.substr(11, 6) != "stbit.") if (memcmp(NameR.data()+11, "stbit.", 6))
break; break;
switch (NameR[17]) { switch (NameR[17]) {
default: break; default: break;
case 'i': // 1 string to match. case 'i': // 1 string to match.
return Intrinsic::hexagon_S2_tstbit_i; // "exagon.S2.tstbi t.i" return Intrinsic::hexagon_S2_tstbit_i; // "exagon.S2.tstbi t.i"
case 'r': // 1 string to match. case 'r': // 1 string to match.
return Intrinsic::hexagon_S2_tstbit_r; // "exagon.S2.tstbi t.r" return Intrinsic::hexagon_S2_tstbit_r; // "exagon.S2.tstbi t.r"
} }
break; break;
case 'v': // 9 strings to match. case 'v': // 9 strings to match.
switch (NameR[11]) { switch (NameR[11]) {
default: break; default: break;
case 'a': // 2 strings to match. case 'a': // 2 strings to match.
if (NameR.substr(12, 4) != "lign") if (memcmp(NameR.data()+12, "lign", 4))
break; break;
switch (NameR[16]) { switch (NameR[16]) {
default: break; default: break;
case 'i': // 1 string to match. case 'i': // 1 string to match.
if (NameR[17] != 'b') if (NameR[17] != 'b')
break; break;
return Intrinsic::hexagon_S2_valignib; // "exagon.S2.valig nib" return Intrinsic::hexagon_S2_valignib; // "exagon.S2.valig nib"
case 'r': // 1 string to match. case 'r': // 1 string to match.
if (NameR[17] != 'b') if (NameR[17] != 'b')
break; break;
return Intrinsic::hexagon_S2_valignrb; // "exagon.S2.valig nrb" return Intrinsic::hexagon_S2_valignrb; // "exagon.S2.valig nrb"
} }
break; break;
case 'c': // 1 string to match. case 'c': // 1 string to match.
if (NameR.substr(12, 6) != "rotate") if (memcmp(NameR.data()+12, "rotate", 6))
break; break;
return Intrinsic::hexagon_S2_vcrotate; // "exagon.S2.vcrot ate" return Intrinsic::hexagon_S2_vcrotate; // "exagon.S2.vcrot ate"
case 's': // 2 strings to match. case 's': // 2 strings to match.
if (NameR.substr(12, 5) != "platr") if (memcmp(NameR.data()+12, "platr", 5))
break; break;
switch (NameR[17]) { switch (NameR[17]) {
default: break; default: break;
case 'b': // 1 string to match. case 'b': // 1 string to match.
return Intrinsic::hexagon_S2_vsplatrb; // "exagon.S2.vspla trb" return Intrinsic::hexagon_S2_vsplatrb; // "exagon.S2.vspla trb"
case 'h': // 1 string to match. case 'h': // 1 string to match.
return Intrinsic::hexagon_S2_vsplatrh; // "exagon.S2.vspla trh" return Intrinsic::hexagon_S2_vsplatrh; // "exagon.S2.vspla trh"
} }
break; break;
case 't': // 4 strings to match. case 't': // 4 strings to match.
if (NameR.substr(12, 3) != "run") if (memcmp(NameR.data()+12, "run", 3))
break; break;
switch (NameR[15]) { switch (NameR[15]) {
default: break; default: break;
case 'e': // 2 strings to match. case 'e': // 2 strings to match.
switch (NameR[16]) { switch (NameR[16]) {
default: break; default: break;
case 'h': // 1 string to match. case 'h': // 1 string to match.
if (NameR[17] != 'b') if (NameR[17] != 'b')
break; break;
return Intrinsic::hexagon_S2_vtrunehb; // "exagon. S2.vtrunehb" return Intrinsic::hexagon_S2_vtrunehb; // "exagon. S2.vtrunehb"
skipping to change at line 6792 skipping to change at line 8765
break; break;
return Intrinsic::hexagon_S2_vtrunowh; // "exagon. S2.vtrunowh" return Intrinsic::hexagon_S2_vtrunowh; // "exagon. S2.vtrunowh"
} }
break; break;
} }
break; break;
} }
break; break;
} }
break; break;
case '4': // 1 string to match. case '4': // 4 strings to match.
if (NameR.substr(9, 9) != ".or.andix") if (NameR[9] != '.')
break;
switch (NameR[10]) {
default: break;
case 'c': // 2 strings to match.
if (memcmp(NameR.data()+11, "lbp", 3))
break;
switch (NameR[14]) {
default: break;
case 'a': // 1 string to match.
if (memcmp(NameR.data()+15, "ddi", 3))
break;
return Intrinsic::hexagon_S4_clbpaddi; // "exagon.S4.clbpa
ddi"
case 'n': // 1 string to match.
if (memcmp(NameR.data()+15, "orm", 3))
break;
return Intrinsic::hexagon_S4_clbpnorm; // "exagon.S4.clbpn
orm"
}
break; break;
return Intrinsic::hexagon_S4_or_andix; // "exagon.S4.or.an case 'e': // 1 string to match.
dix" if (memcmp(NameR.data()+11, "xtractp", 7))
break;
return Intrinsic::hexagon_S4_extractp; // "exagon.S4.extra
ctp"
case 'o': // 1 string to match.
if (memcmp(NameR.data()+11, "r.andix", 7))
break;
return Intrinsic::hexagon_S4_or_andix; // "exagon.S4.or.an
dix"
}
break;
} }
break; break;
} }
break; break;
case 19: // 48 strings to match. case 19: // 81 strings to match.
if (NameR.substr(0, 7) != "exagon.") if (memcmp(NameR.data()+0, "exagon.", 7))
break; break;
switch (NameR[7]) { switch (NameR[7]) {
default: break; default: break;
case 'A': // 5 strings to match. case 'A': // 11 strings to match.
switch (NameR[8]) { switch (NameR[8]) {
default: break; default: break;
case '2': // 1 string to match. case '2': // 3 strings to match.
if (NameR.substr(9, 10) != ".combineii") if (NameR[9] != '.')
break; break;
return Intrinsic::hexagon_A2_combineii; // "exagon.A2.combi switch (NameR[10]) {
neii" default: break;
case '4': // 4 strings to match. case 'c': // 1 string to match.
if (NameR.substr(9, 2) != ".c") if (memcmp(NameR.data()+11, "ombineii", 8))
break;
return Intrinsic::hexagon_A2_combineii; // "exagon.A2.combi
neii"
case 'v': // 2 strings to match.
switch (NameR[11]) {
default: break;
case 'a': // 1 string to match.
if (memcmp(NameR.data()+12, "ddb.map", 7))
break;
return Intrinsic::hexagon_A2_vaddb_map; // "exagon.A2.vaddb
.map"
case 's': // 1 string to match.
if (memcmp(NameR.data()+12, "ubb.map", 7))
break;
return Intrinsic::hexagon_A2_vsubb_map; // "exagon.A2.vsubb
.map"
}
break; break;
switch (NameR[11]) { }
break;
case '4': // 8 strings to match.
if (NameR[9] != '.')
break;
switch (NameR[10]) {
default: break; default: break;
case 'o': // 2 strings to match. case 'b': // 1 string to match.
if (NameR.substr(12, 5) != "mbine") if (memcmp(NameR.data()+11, "itspliti", 8))
break; break;
switch (NameR[17]) { return Intrinsic::hexagon_A4_bitspliti; // "exagon.A4.bitsp
liti"
case 'c': // 4 strings to match.
switch (NameR[11]) {
default: break; default: break;
case 'i': // 1 string to match. case 'o': // 2 strings to match.
if (NameR[18] != 'r') if (memcmp(NameR.data()+12, "mbine", 5))
break; break;
return Intrinsic::hexagon_A4_combineir; // "exagon.A4.combi switch (NameR[17]) {
neir" default: break;
case 'r': // 1 string to match. case 'i': // 1 string to match.
if (NameR[18] != 'i') if (NameR[18] != 'r')
break;
return Intrinsic::hexagon_A4_combineir; // "exagon.
A4.combineir"
case 'r': // 1 string to match.
if (NameR[18] != 'i')
break;
return Intrinsic::hexagon_A4_combineri; // "exagon.
A4.combineri"
}
break;
case 'r': // 2 strings to match.
if (memcmp(NameR.data()+12, "ound.r", 6))
break; break;
return Intrinsic::hexagon_A4_combineri; // "exagon.A4.combi switch (NameR[18]) {
neri" default: break;
case 'i': // 1 string to match.
return Intrinsic::hexagon_A4_cround_ri; // "exagon.
A4.cround.ri"
case 'r': // 1 string to match.
return Intrinsic::hexagon_A4_cround_rr; // "exagon.
A4.cround.rr"
}
break;
} }
break; break;
case 'r': // 2 strings to match. case 'v': // 3 strings to match.
if (NameR.substr(12, 6) != "ound.r") if (memcmp(NameR.data()+11, "cmp", 3))
break; break;
switch (NameR[18]) { switch (NameR[14]) {
default: break; default: break;
case 'i': // 1 string to match. case 'b': // 1 string to match.
return Intrinsic::hexagon_A4_cround_ri; // "exagon.A4.croun if (memcmp(NameR.data()+15, "gtui", 4))
d.ri" break;
case 'r': // 1 string to match. return Intrinsic::hexagon_A4_vcmpbgtui; // "exagon.A4.vcmpb
return Intrinsic::hexagon_A4_cround_rr; // "exagon.A4.croun gtui"
d.rr" case 'h': // 1 string to match.
if (memcmp(NameR.data()+15, "gtui", 4))
break;
return Intrinsic::hexagon_A4_vcmphgtui; // "exagon.A4.vcmph
gtui"
case 'w': // 1 string to match.
if (memcmp(NameR.data()+15, "gtui", 4))
break;
return Intrinsic::hexagon_A4_vcmpwgtui; // "exagon.A4.vcmpw
gtui"
} }
break; break;
} }
break; break;
} }
break; break;
case 'C': // 1 string to match. case 'C': // 2 strings to match.
if (NameR.substr(8, 11) != "2.pxfer.map") switch (NameR[8]) {
break; default: break;
return Intrinsic::hexagon_C2_pxfer_map; // "exagon.C2.pxfer case '2': // 1 string to match.
.map" if (memcmp(NameR.data()+9, ".pxfer.map", 10))
case 'M': // 38 strings to match. break;
if (NameR.substr(8, 2) != "2.") return Intrinsic::hexagon_C2_pxfer_map; // "exagon.C2.pxfer
.map"
case '4': // 1 string to match.
if (memcmp(NameR.data()+9, ".nbitsclri", 10))
break;
return Intrinsic::hexagon_C4_nbitsclri; // "exagon.C4.nbits
clri"
}
break;
case 'F': // 12 strings to match.
if (memcmp(NameR.data()+8, "2.", 2))
break; break;
switch (NameR[10]) { switch (NameR[10]) {
default: break; default: break;
case 'c': // 8 strings to match. case 'c': // 8 strings to match.
switch (NameR[11]) { if (memcmp(NameR.data()+11, "onv.", 4))
break;
switch (NameR[15]) {
default: break; default: break;
case 'm': // 6 strings to match. case 'd': // 4 strings to match.
switch (NameR[12]) { switch (NameR[16]) {
default: break; default: break;
case 'a': // 2 strings to match. case '2': // 2 strings to match.
if (NameR.substr(13, 5) != "csc.s") switch (NameR[17]) {
break;
switch (NameR[18]) {
default: break; default: break;
case '0': // 1 string to match. case 'd': // 1 string to match.
return Intrinsic::hexagon_M2_cmacsc_s0; // "exagon. if (NameR[18] != 'f')
M2.cmacsc.s0" break;
case '1': // 1 string to match. return Intrinsic::hexagon_F2_conv_d2df; // "exagon.
return Intrinsic::hexagon_M2_cmacsc_s1; // "exagon. F2.conv.d2df"
M2.cmacsc.s1" case 's': // 1 string to match.
if (NameR[18] != 'f')
break;
return Intrinsic::hexagon_F2_conv_d2sf; // "exagon.
F2.conv.d2sf"
} }
break; break;
case 'p': // 4 strings to match. case 'f': // 2 strings to match.
if (NameR[13] != 'y') if (NameR[17] != '2')
break; break;
switch (NameR[14]) { switch (NameR[18]) {
default: break; default: break;
case 'r': // 2 strings to match. case 'd': // 1 string to match.
if (NameR.substr(15, 3) != "s.s") return Intrinsic::hexagon_F2_conv_df2d; // "exagon.
break; F2.conv.df2d"
switch (NameR[18]) { case 'w': // 1 string to match.
default: break; return Intrinsic::hexagon_F2_conv_df2w; // "exagon.
case '0': // 1 string to match. F2.conv.df2w"
return Intrinsic::hexagon_M2_cmpyrs_s0; // "exagon.
M2.cmpyrs.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_cmpyrs_s1; // "exagon.
M2.cmpyrs.s1"
}
break;
case 's': // 2 strings to match.
if (NameR.substr(15, 3) != "c.s")
break;
switch (NameR[18]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_cmpysc_s0; // "exagon.
M2.cmpysc.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_cmpysc_s1; // "exagon.
M2.cmpysc.s1"
}
break;
} }
break; break;
} }
break; break;
case 'n': // 2 strings to match. case 's': // 2 strings to match.
if (NameR.substr(12, 6) != "acsc.s") if (memcmp(NameR.data()+16, "f2", 2))
break; break;
switch (NameR[18]) { switch (NameR[18]) {
default: break; default: break;
case '0': // 1 string to match. case 'd': // 1 string to match.
return Intrinsic::hexagon_M2_cnacsc_s0; // "exagon.M2.cnacs return Intrinsic::hexagon_F2_conv_sf2d; // "exagon.F2.conv.
c.s0" sf2d"
case '1': // 1 string to match. case 'w': // 1 string to match.
return Intrinsic::hexagon_M2_cnacsc_s1; // "exagon.M2.cnacs return Intrinsic::hexagon_F2_conv_sf2w; // "exagon.F2.conv.
c.s1" sf2w"
} }
break; break;
} case 'w': // 2 strings to match.
break; if (NameR[16] != '2')
case 'm': // 20 strings to match. break;
switch (NameR[11]) { switch (NameR[17]) {
default: break;
case 'm': // 12 strings to match.
switch (NameR[12]) {
default: break; default: break;
case 'a': // 4 strings to match. case 'd': // 1 string to match.
if (NameR[13] != 'c') if (NameR[18] != 'f')
break;
switch (NameR[14]) {
default: break;
case 'h': // 2 strings to match.
if (NameR.substr(15, 3) != "s.s")
break;
switch (NameR[18]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mmachs_s0; // "exagon.
M2.mmachs.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mmachs_s1; // "exagon.
M2.mmachs.s1"
}
break; break;
case 'l': // 2 strings to match. return Intrinsic::hexagon_F2_conv_w2df; // "exagon.F2.conv.
if (NameR.substr(15, 3) != "s.s") w2df"
break; case 's': // 1 string to match.
switch (NameR[18]) { if (NameR[18] != 'f')
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mmacls_s0; // "exagon.
M2.mmacls.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mmacls_s1; // "exagon.
M2.mmacls.s1"
}
break; break;
} return Intrinsic::hexagon_F2_conv_w2sf; // "exagon.F2.conv.
w2sf"
}
break;
}
break;
case 'd': // 2 strings to match.
if (memcmp(NameR.data()+11, "ffm", 3))
break;
switch (NameR[14]) {
default: break;
case 'a': // 1 string to match.
if (memcmp(NameR.data()+15, ".lib", 4))
break; break;
case 'p': // 8 strings to match. return Intrinsic::hexagon_F2_dffma_lib; // "exagon.F2.dffma
if (NameR[13] != 'y') .lib"
break; case 's': // 1 string to match.
switch (NameR[14]) { if (memcmp(NameR.data()+15, ".lib", 4))
break;
return Intrinsic::hexagon_F2_dffms_lib; // "exagon.F2.dffms
.lib"
}
break;
case 's': // 2 strings to match.
if (memcmp(NameR.data()+11, "ffm", 3))
break;
switch (NameR[14]) {
default: break;
case 'a': // 1 string to match.
if (memcmp(NameR.data()+15, ".lib", 4))
break;
return Intrinsic::hexagon_F2_sffma_lib; // "exagon.F2.sffma
.lib"
case 's': // 1 string to match.
if (memcmp(NameR.data()+15, ".lib", 4))
break;
return Intrinsic::hexagon_F2_sffms_lib; // "exagon.F2.sffms
.lib"
}
break;
}
break;
case 'M': // 44 strings to match.
switch (NameR[8]) {
default: break;
case '2': // 41 strings to match.
if (NameR[9] != '.')
break;
switch (NameR[10]) {
default: break;
case 'c': // 8 strings to match.
switch (NameR[11]) {
default: break;
case 'm': // 6 strings to match.
switch (NameR[12]) {
default: break; default: break;
case 'h': // 2 strings to match. case 'a': // 2 strings to match.
if (NameR.substr(15, 3) != ".rs") if (memcmp(NameR.data()+13, "csc.s", 5))
break; break;
switch (NameR[18]) { switch (NameR[18]) {
default: break; default: break;
case '0': // 1 string to match. case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mmpyh_rs0; // "exagon. M2.mmpyh.rs0" return Intrinsic::hexagon_M2_cmacsc_s0; // "exagon. M2.cmacsc.s0"
case '1': // 1 string to match. case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mmpyh_rs1; // "exagon. M2.mmpyh.rs1" return Intrinsic::hexagon_M2_cmacsc_s1; // "exagon. M2.cmacsc.s1"
} }
break; break;
case 'l': // 2 strings to match. case 'p': // 4 strings to match.
if (NameR.substr(15, 3) != ".rs") if (NameR[13] != 'y')
break; break;
switch (NameR[18]) { switch (NameR[14]) {
default: break; default: break;
case '0': // 1 string to match. case 'r': // 2 strings to match.
return Intrinsic::hexagon_M2_mmpyl_rs0; // "exagon. if (memcmp(NameR.data()+15, "s.s", 3))
M2.mmpyl.rs0" break;
case '1': // 1 string to match. switch (NameR[18]) {
return Intrinsic::hexagon_M2_mmpyl_rs1; // "exagon. default: break;
M2.mmpyl.rs1" case '0': // 1 string to match.
return Intrinsic::hexagon_M2_cmpyrs_s0; // "exagon.
M2.cmpyrs.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_cmpyrs_s1; // "exagon.
M2.cmpyrs.s1"
}
break;
case 's': // 2 strings to match.
if (memcmp(NameR.data()+15, "c.s", 3))
break;
switch (NameR[18]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_cmpysc_s0; // "exagon.
M2.cmpysc.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_cmpysc_s1; // "exagon.
M2.cmpysc.s1"
}
break;
} }
break; break;
case 'u': // 4 strings to match. }
break;
case 'n': // 2 strings to match.
if (memcmp(NameR.data()+12, "acsc.s", 6))
break;
switch (NameR[18]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_cnacsc_s0; // "exagon.
M2.cnacsc.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_cnacsc_s1; // "exagon.
M2.cnacsc.s1"
}
break;
}
break;
case 'h': // 2 strings to match.
if (memcmp(NameR.data()+11, "mmpy", 4))
break;
switch (NameR[15]) {
default: break;
case 'h': // 1 string to match.
if (memcmp(NameR.data()+16, ".s1", 3))
break;
return Intrinsic::hexagon_M2_hmmpyh_s1; // "exagon.M2.hmmpy
h.s1"
case 'l': // 1 string to match.
if (memcmp(NameR.data()+16, ".s1", 3))
break;
return Intrinsic::hexagon_M2_hmmpyl_s1; // "exagon.M2.hmmpy
l.s1"
}
break;
case 'm': // 21 strings to match.
switch (NameR[11]) {
default: break;
case 'm': // 12 strings to match.
switch (NameR[12]) {
default: break;
case 'a': // 4 strings to match.
if (NameR[13] != 'c')
break;
switch (NameR[14]) {
default: break;
case 'h': // 2 strings to match.
if (memcmp(NameR.data()+15, "s.s", 3))
break;
switch (NameR[18]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mmachs_s0; // "exagon.
M2.mmachs.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mmachs_s1; // "exagon.
M2.mmachs.s1"
}
break;
case 'l': // 2 strings to match.
if (memcmp(NameR.data()+15, "s.s", 3))
break;
switch (NameR[18]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mmacls_s0; // "exagon.
M2.mmacls.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mmacls_s1; // "exagon.
M2.mmacls.s1"
}
break;
}
break;
case 'p': // 8 strings to match.
if (NameR[13] != 'y')
break;
switch (NameR[14]) {
default: break;
case 'h': // 2 strings to match.
if (memcmp(NameR.data()+15, ".rs", 3))
break;
switch (NameR[18]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mmpyh_rs0; // "exagon.
M2.mmpyh.rs0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mmpyh_rs1; // "exagon.
M2.mmpyh.rs1"
}
break;
case 'l': // 2 strings to match.
if (memcmp(NameR.data()+15, ".rs", 3))
break;
switch (NameR[18]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mmpyl_rs0; // "exagon.
M2.mmpyl.rs0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mmpyl_rs1; // "exagon.
M2.mmpyl.rs1"
}
break;
case 'u': // 4 strings to match.
switch (NameR[15]) {
default: break;
case 'h': // 2 strings to match.
if (memcmp(NameR.data()+16, ".s", 2))
break;
switch (NameR[18]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mmpyuh_s0; // "exagon.
M2.mmpyuh.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mmpyuh_s1; // "exagon.
M2.mmpyuh.s1"
}
break;
case 'l': // 2 strings to match.
if (memcmp(NameR.data()+16, ".s", 2))
break;
switch (NameR[18]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mmpyul_s0; // "exagon.
M2.mmpyul.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mmpyul_s1; // "exagon.
M2.mmpyul.s1"
}
break;
}
break;
}
break;
}
break;
case 'p': // 9 strings to match.
if (memcmp(NameR.data()+12, "y.", 2))
break;
switch (NameR[14]) {
default: break;
case 'h': // 4 strings to match.
switch (NameR[15]) {
default: break;
case 'h': // 2 strings to match.
if (memcmp(NameR.data()+16, ".s", 2))
break;
switch (NameR[18]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_hh_s0; // "exagon.
M2.mpy.hh.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_hh_s1; // "exagon.
M2.mpy.hh.s1"
}
break;
case 'l': // 2 strings to match.
if (memcmp(NameR.data()+16, ".s", 2))
break;
switch (NameR[18]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_hl_s0; // "exagon.
M2.mpy.hl.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_hl_s1; // "exagon.
M2.mpy.hl.s1"
}
break;
}
break;
case 'l': // 4 strings to match.
switch (NameR[15]) { switch (NameR[15]) {
default: break; default: break;
case 'h': // 2 strings to match. case 'h': // 2 strings to match.
if (NameR.substr(16, 2) != ".s") if (memcmp(NameR.data()+16, ".s", 2))
break; break;
switch (NameR[18]) { switch (NameR[18]) {
default: break; default: break;
case '0': // 1 string to match. case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mmpyuh_s0; // "exagon. M2.mmpyuh.s0" return Intrinsic::hexagon_M2_mpy_lh_s0; // "exagon. M2.mpy.lh.s0"
case '1': // 1 string to match. case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mmpyuh_s1; // "exagon. M2.mmpyuh.s1" return Intrinsic::hexagon_M2_mpy_lh_s1; // "exagon. M2.mpy.lh.s1"
} }
break; break;
case 'l': // 2 strings to match. case 'l': // 2 strings to match.
if (NameR.substr(16, 2) != ".s") if (memcmp(NameR.data()+16, ".s", 2))
break; break;
switch (NameR[18]) { switch (NameR[18]) {
default: break; default: break;
case '0': // 1 string to match. case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mmpyul_s0; // "exagon. M2.mmpyul.s0" return Intrinsic::hexagon_M2_mpy_ll_s0; // "exagon. M2.mpy.ll.s0"
case '1': // 1 string to match. case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mmpyul_s1; // "exagon. M2.mmpyul.s1" return Intrinsic::hexagon_M2_mpy_ll_s1; // "exagon. M2.mpy.ll.s1"
} }
break; break;
} }
break; break;
case 'u': // 1 string to match.
if (memcmp(NameR.data()+15, "p.s1", 4))
break;
return Intrinsic::hexagon_M2_mpy_up_s1; // "exagon.
M2.mpy.up.s1"
} }
break; break;
} }
break; break;
case 'p': // 8 strings to match. case 'v': // 10 strings to match.
if (NameR.substr(12, 2) != "y.") switch (NameR[11]) {
break;
switch (NameR[14]) {
default: break; default: break;
case 'h': // 4 strings to match. case 'a': // 2 strings to match.
switch (NameR[15]) { if (memcmp(NameR.data()+12, "bsdiff", 6))
break;
switch (NameR[18]) {
default: break; default: break;
case 'h': // 2 strings to match. case 'h': // 1 string to match.
if (NameR.substr(16, 2) != ".s") return Intrinsic::hexagon_M2_vabsdiffh; // "exagon.
M2.vabsdiffh"
case 'w': // 1 string to match.
return Intrinsic::hexagon_M2_vabsdiffw; // "exagon.
M2.vabsdiffw"
}
break;
case 'd': // 4 strings to match.
if (NameR[12] != 'm')
break;
switch (NameR[13]) {
default: break;
case 'a': // 2 strings to match.
if (memcmp(NameR.data()+14, "cs.s", 4))
break; break;
switch (NameR[18]) { switch (NameR[18]) {
default: break; default: break;
case '0': // 1 string to match. case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_hh_s0; // "exagon. M2.mpy.hh.s0" return Intrinsic::hexagon_M2_vdmacs_s0; // "exagon. M2.vdmacs.s0"
case '1': // 1 string to match. case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_hh_s1; // "exagon. M2.mpy.hh.s1" return Intrinsic::hexagon_M2_vdmacs_s1; // "exagon. M2.vdmacs.s1"
} }
break; break;
case 'l': // 2 strings to match. case 'p': // 2 strings to match.
if (NameR.substr(16, 2) != ".s") if (memcmp(NameR.data()+14, "ys.s", 4))
break; break;
switch (NameR[18]) { switch (NameR[18]) {
default: break; default: break;
case '0': // 1 string to match. case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_hl_s0; // "exagon. M2.mpy.hl.s0" return Intrinsic::hexagon_M2_vdmpys_s0; // "exagon. M2.vdmpys.s0"
case '1': // 1 string to match. case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_hl_s1; // "exagon. M2.mpy.hl.s1" return Intrinsic::hexagon_M2_vdmpys_s1; // "exagon. M2.vdmpys.s1"
} }
break; break;
} }
break; break;
case 'l': // 4 strings to match. case 'm': // 4 strings to match.
switch (NameR[15]) { switch (NameR[12]) {
default: break; default: break;
case 'h': // 2 strings to match. case 'a': // 2 strings to match.
if (NameR.substr(16, 2) != ".s") if (memcmp(NameR.data()+13, "c2s.s", 5))
break; break;
switch (NameR[18]) { switch (NameR[18]) {
default: break; default: break;
case '0': // 1 string to match. case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_lh_s0; // "exagon. M2.mpy.lh.s0" return Intrinsic::hexagon_M2_vmac2s_s0; // "exagon. M2.vmac2s.s0"
case '1': // 1 string to match. case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_lh_s1; // "exagon. M2.mpy.lh.s1" return Intrinsic::hexagon_M2_vmac2s_s1; // "exagon. M2.vmac2s.s1"
} }
break; break;
case 'l': // 2 strings to match. case 'p': // 2 strings to match.
if (NameR.substr(16, 2) != ".s") if (memcmp(NameR.data()+13, "y2s.s", 5))
break; break;
switch (NameR[18]) { switch (NameR[18]) {
default: break; default: break;
case '0': // 1 string to match. case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_ll_s0; // "exagon. M2.mpy.ll.s0" return Intrinsic::hexagon_M2_vmpy2s_s0; // "exagon. M2.vmpy2s.s0"
case '1': // 1 string to match. case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_ll_s1; // "exagon. M2.mpy.ll.s1" return Intrinsic::hexagon_M2_vmpy2s_s1; // "exagon. M2.vmpy2s.s1"
} }
break; break;
} }
break; break;
} }
break; break;
} }
break; break;
case 'v': // 10 strings to match. case '4': // 3 strings to match.
switch (NameR[11]) { if (NameR[9] != '.')
default: break;
case 'a': // 2 strings to match.
if (NameR.substr(12, 6) != "bsdiff")
break;
switch (NameR[18]) {
default: break;
case 'h': // 1 string to match.
return Intrinsic::hexagon_M2_vabsdiffh; // "exagon.M2.vabsd
iffh"
case 'w': // 1 string to match.
return Intrinsic::hexagon_M2_vabsdiffw; // "exagon.M2.vabsd
iffw"
}
break; break;
case 'd': // 4 strings to match. switch (NameR[10]) {
if (NameR[12] != 'm') default: break;
case 'c': // 2 strings to match.
if (memcmp(NameR.data()+11, "mpy", 3))
break; break;
switch (NameR[13]) { switch (NameR[14]) {
default: break; default: break;
case 'a': // 2 strings to match. case 'i': // 1 string to match.
if (NameR.substr(14, 4) != "cs.s") if (memcmp(NameR.data()+15, ".whc", 4))
break; break;
switch (NameR[18]) { return Intrinsic::hexagon_M4_cmpyi_whc; // "exagon.M4.cmpyi
default: break; .whc"
case '0': // 1 string to match. case 'r': // 1 string to match.
return Intrinsic::hexagon_M2_vdmacs_s0; // "exagon. if (memcmp(NameR.data()+15, ".whc", 4))
M2.vdmacs.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_vdmacs_s1; // "exagon.
M2.vdmacs.s1"
}
break;
case 'p': // 2 strings to match.
if (NameR.substr(14, 4) != "ys.s")
break; break;
switch (NameR[18]) { return Intrinsic::hexagon_M4_cmpyr_whc; // "exagon.M4.cmpyr
default: break; .whc"
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_vdmpys_s0; // "exagon.
M2.vdmpys.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_vdmpys_s1; // "exagon.
M2.vdmpys.s1"
}
break;
} }
break; break;
case 'm': // 4 strings to match. case 'p': // 1 string to match.
switch (NameR[12]) { if (memcmp(NameR.data()+11, "mpyw.acc", 8))
default: break;
case 'a': // 2 strings to match.
if (NameR.substr(13, 5) != "c2s.s")
break;
switch (NameR[18]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_vmac2s_s0; // "exagon.
M2.vmac2s.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_vmac2s_s1; // "exagon.
M2.vmac2s.s1"
}
break;
case 'p': // 2 strings to match.
if (NameR.substr(13, 5) != "y2s.s")
break;
switch (NameR[18]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_vmpy2s_s0; // "exagon.
M2.vmpy2s.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_vmpy2s_s1; // "exagon.
M2.vmpy2s.s1"
}
break; break;
} return Intrinsic::hexagon_M4_pmpyw_acc; // "exagon.M4.pmpyw
break; .acc"
} }
break; break;
} }
break; break;
case 'S': // 4 strings to match. case 'S': // 12 strings to match.
if (NameR.substr(8, 2) != "2.") switch (NameR[8]) {
break;
switch (NameR[10]) {
default: break; default: break;
case 'e': // 1 string to match. case '2': // 4 strings to match.
if (NameR.substr(11, 8) != "xtractup") if (NameR[9] != '.')
break;
return Intrinsic::hexagon_S2_extractup; // "exagon.S2.extra
ctup"
case 'i': // 1 string to match.
if (NameR.substr(11, 8) != "nsert.rp")
break;
return Intrinsic::hexagon_S2_insert_rp; // "exagon.S2.inser
t.rp"
case 'v': // 2 strings to match.
if (NameR.substr(11, 6) != "splice")
break; break;
switch (NameR[17]) { switch (NameR[10]) {
default: break; default: break;
case 'e': // 1 string to match.
if (memcmp(NameR.data()+11, "xtractup", 8))
break;
return Intrinsic::hexagon_S2_extractup; // "exagon.S2.extra
ctup"
case 'i': // 1 string to match. case 'i': // 1 string to match.
if (NameR[18] != 'b') if (memcmp(NameR.data()+11, "nsert.rp", 8))
break; break;
return Intrinsic::hexagon_S2_vspliceib; // "exagon.S2.vspli return Intrinsic::hexagon_S2_insert_rp; // "exagon.S2.inser
ceib" t.rp"
case 'r': // 1 string to match. case 'v': // 2 strings to match.
if (NameR[18] != 'b') if (memcmp(NameR.data()+11, "splice", 6))
break;
switch (NameR[17]) {
default: break;
case 'i': // 1 string to match.
if (NameR[18] != 'b')
break;
return Intrinsic::hexagon_S2_vspliceib; // "exagon.S2.vspli
ceib"
case 'r': // 1 string to match.
if (NameR[18] != 'b')
break;
return Intrinsic::hexagon_S2_vsplicerb; // "exagon.S2.vspli
cerb"
}
break;
}
break;
case '4': // 7 strings to match.
if (NameR[9] != '.')
break;
switch (NameR[10]) {
default: break;
case 'n': // 2 strings to match.
if (memcmp(NameR.data()+11, "tstbit.", 7))
break;
switch (NameR[18]) {
default: break;
case 'i': // 1 string to match.
return Intrinsic::hexagon_S4_ntstbit_i; // "exagon.S4.ntstb
it.i"
case 'r': // 1 string to match.
return Intrinsic::hexagon_S4_ntstbit_r; // "exagon.S4.ntstb
it.r"
}
break;
case 'v': // 5 strings to match.
switch (NameR[11]) {
default: break;
case 'r': // 1 string to match.
if (memcmp(NameR.data()+12, "crotate", 7))
break;
return Intrinsic::hexagon_S4_vrcrotate; // "exagon.S4.vrcro
tate"
case 'x': // 4 strings to match.
switch (NameR[12]) {
default: break;
case 'a': // 2 strings to match.
if (memcmp(NameR.data()+13, "ddsub", 5))
break;
switch (NameR[18]) {
default: break;
case 'h': // 1 string to match.
return Intrinsic::hexagon_S4_vxaddsubh; // "exagon.
S4.vxaddsubh"
case 'w': // 1 string to match.
return Intrinsic::hexagon_S4_vxaddsubw; // "exagon.
S4.vxaddsubw"
}
break;
case 's': // 2 strings to match.
if (memcmp(NameR.data()+13, "ubadd", 5))
break;
switch (NameR[18]) {
default: break;
case 'h': // 1 string to match.
return Intrinsic::hexagon_S4_vxsubaddh; // "exagon.
S4.vxsubaddh"
case 'w': // 1 string to match.
return Intrinsic::hexagon_S4_vxsubaddw; // "exagon.
S4.vxsubaddw"
}
break;
}
break; break;
return Intrinsic::hexagon_S2_vsplicerb; // "exagon.S2.vspli }
cerb" break;
} }
break; break;
case '5': // 1 string to match.
if (memcmp(NameR.data()+9, ".popcountp", 10))
break;
return Intrinsic::hexagon_S5_popcountp; // "exagon.S5.popco
untp"
} }
break; break;
} }
break; break;
case 20: // 66 strings to match. case 20: // 95 strings to match.
if (NameR.substr(0, 7) != "exagon.") if (memcmp(NameR.data()+0, "exagon.", 7))
break; break;
switch (NameR[7]) { switch (NameR[7]) {
default: break; default: break;
case 'A': // 4 strings to match. case 'A': // 4 strings to match.
if (NameR.substr(8, 10) != "2.combine.") if (memcmp(NameR.data()+8, "2.combine.", 10))
break; break;
switch (NameR[18]) { switch (NameR[18]) {
default: break; default: break;
case 'h': // 2 strings to match. case 'h': // 2 strings to match.
switch (NameR[19]) { switch (NameR[19]) {
default: break; default: break;
case 'h': // 1 string to match. case 'h': // 1 string to match.
return Intrinsic::hexagon_A2_combine_hh; // "exagon.A2.combi ne.hh" return Intrinsic::hexagon_A2_combine_hh; // "exagon.A2.combi ne.hh"
case 'l': // 1 string to match. case 'l': // 1 string to match.
return Intrinsic::hexagon_A2_combine_hl; // "exagon.A2.combi ne.hl" return Intrinsic::hexagon_A2_combine_hl; // "exagon.A2.combi ne.hl"
skipping to change at line 7209 skipping to change at line 9477
switch (NameR[19]) { switch (NameR[19]) {
default: break; default: break;
case 'h': // 1 string to match. case 'h': // 1 string to match.
return Intrinsic::hexagon_A2_combine_lh; // "exagon.A2.combi ne.lh" return Intrinsic::hexagon_A2_combine_lh; // "exagon.A2.combi ne.lh"
case 'l': // 1 string to match. case 'l': // 1 string to match.
return Intrinsic::hexagon_A2_combine_ll; // "exagon.A2.combi ne.ll" return Intrinsic::hexagon_A2_combine_ll; // "exagon.A2.combi ne.ll"
} }
break; break;
} }
break; break;
case 'M': // 45 strings to match. case 'F': // 10 strings to match.
if (NameR.substr(8, 2) != "2.") if (memcmp(NameR.data()+8, "2.conv.", 7))
break; break;
switch (NameR[10]) { switch (NameR[15]) {
default: break; default: break;
case 'c': // 2 strings to match. case 'd': // 3 strings to match.
if (NameR.substr(11, 8) != "mpyrsc.s") if (memcmp(NameR.data()+16, "f2", 2))
break;
switch (NameR[19]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_cmpyrsc_s0; // "exagon.M2.cmpyr
sc.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_cmpyrsc_s1; // "exagon.M2.cmpyr
sc.s1"
}
break;
case 'd': // 2 strings to match.
if (NameR.substr(11, 4) != "pmpy")
break; break;
switch (NameR[15]) { switch (NameR[18]) {
default: break; default: break;
case 's': // 1 string to match. case 's': // 1 string to match.
if (NameR.substr(16, 4) != "s.s0") if (NameR[19] != 'f')
break;
return Intrinsic::hexagon_M2_dpmpyss_s0; // "exagon.M2.dpmpy
ss.s0"
case 'u': // 1 string to match.
if (NameR.substr(16, 4) != "u.s0")
break; break;
return Intrinsic::hexagon_M2_dpmpyuu_s0; // "exagon.M2.dpmpy return Intrinsic::hexagon_F2_conv_df2sf; // "exagon.F2.conv.
uu.s0" df2sf"
case 'u': // 2 strings to match.
switch (NameR[19]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::hexagon_F2_conv_df2ud; // "exagon.F2.conv.
df2ud"
case 'w': // 1 string to match.
return Intrinsic::hexagon_F2_conv_df2uw; // "exagon.F2.conv.
df2uw"
}
break;
} }
break; break;
case 'h': // 2 strings to match. case 's': // 3 strings to match.
if (NameR.substr(11, 4) != "mmpy") if (memcmp(NameR.data()+16, "f2", 2))
break; break;
switch (NameR[15]) { switch (NameR[18]) {
default: break; default: break;
case 'h': // 1 string to match. case 'd': // 1 string to match.
if (NameR.substr(16, 4) != ".rs1") if (NameR[19] != 'f')
break;
return Intrinsic::hexagon_M2_hmmpyh_rs1; // "exagon.M2.hmmpy
h.rs1"
case 'l': // 1 string to match.
if (NameR.substr(16, 4) != ".rs1")
break; break;
return Intrinsic::hexagon_M2_hmmpyl_rs1; // "exagon.M2.hmmpy return Intrinsic::hexagon_F2_conv_sf2df; // "exagon.F2.conv.
l.rs1" sf2df"
case 'u': // 2 strings to match.
switch (NameR[19]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::hexagon_F2_conv_sf2ud; // "exagon.F2.conv.
sf2ud"
case 'w': // 1 string to match.
return Intrinsic::hexagon_F2_conv_sf2uw; // "exagon.F2.conv.
sf2uw"
}
break;
} }
break; break;
case 'm': // 28 strings to match. case 'u': // 4 strings to match.
switch (NameR[11]) { switch (NameR[16]) {
default: break; default: break;
case 'm': // 12 strings to match. case 'd': // 2 strings to match.
switch (NameR[12]) { if (NameR[17] != '2')
break;
switch (NameR[18]) {
default: break; default: break;
case 'a': // 8 strings to match. case 'd': // 1 string to match.
if (NameR[13] != 'c') if (NameR[19] != 'f')
break; break;
switch (NameR[14]) { return Intrinsic::hexagon_F2_conv_ud2df; // "exagon.F2.conv.
default: break; ud2df"
case 'h': // 2 strings to match. case 's': // 1 string to match.
if (NameR.substr(15, 4) != "s.rs") if (NameR[19] != 'f')
break;
switch (NameR[19]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mmachs_rs0; // "exagon.
M2.mmachs.rs0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mmachs_rs1; // "exagon.
M2.mmachs.rs1"
}
break; break;
case 'l': // 2 strings to match. return Intrinsic::hexagon_F2_conv_ud2sf; // "exagon.F2.conv.
if (NameR.substr(15, 4) != "s.rs") ud2sf"
break; }
switch (NameR[19]) { break;
default: break; case 'w': // 2 strings to match.
case '0': // 1 string to match. if (NameR[17] != '2')
return Intrinsic::hexagon_M2_mmacls_rs0; // "exagon. break;
M2.mmacls.rs0" switch (NameR[18]) {
case '1': // 1 string to match. default: break;
return Intrinsic::hexagon_M2_mmacls_rs1; // "exagon. case 'd': // 1 string to match.
M2.mmacls.rs1" if (NameR[19] != 'f')
}
break; break;
case 'u': // 4 strings to match. return Intrinsic::hexagon_F2_conv_uw2df; // "exagon.F2.conv.
switch (NameR[15]) { uw2df"
default: break; case 's': // 1 string to match.
case 'h': // 2 strings to match. if (NameR[19] != 'f')
if (NameR.substr(16, 3) != "s.s")
break;
switch (NameR[19]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mmacuhs_s0; // "exagon.
M2.mmacuhs.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mmacuhs_s1; // "exagon.
M2.mmacuhs.s1"
}
break;
case 'l': // 2 strings to match.
if (NameR.substr(16, 3) != "s.s")
break;
switch (NameR[19]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mmaculs_s0; // "exagon.
M2.mmaculs.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mmaculs_s1; // "exagon.
M2.mmaculs.s1"
}
break;
}
break; break;
} return Intrinsic::hexagon_F2_conv_uw2sf; // "exagon.F2.conv.
uw2sf"
}
break;
}
break;
}
break;
case 'M': // 58 strings to match.
switch (NameR[8]) {
default: break;
case '2': // 49 strings to match.
if (NameR[9] != '.')
break;
switch (NameR[10]) {
default: break;
case 'c': // 2 strings to match.
if (memcmp(NameR.data()+11, "mpyrsc.s", 8))
break; break;
case 'p': // 4 strings to match. switch (NameR[19]) {
if (NameR.substr(13, 2) != "yu") default: break;
break; case '0': // 1 string to match.
switch (NameR[15]) { return Intrinsic::hexagon_M2_cmpyrsc_s0; // "exagon.M2.cmpyr
default: break; sc.s0"
case 'h': // 2 strings to match. case '1': // 1 string to match.
if (NameR.substr(16, 3) != ".rs") return Intrinsic::hexagon_M2_cmpyrsc_s1; // "exagon.M2.cmpyr
break; sc.s1"
switch (NameR[19]) { }
default: break; break;
case '0': // 1 string to match. case 'd': // 2 strings to match.
return Intrinsic::hexagon_M2_mmpyuh_rs0; // "exagon. if (memcmp(NameR.data()+11, "pmpy", 4))
M2.mmpyuh.rs0" break;
case '1': // 1 string to match. switch (NameR[15]) {
return Intrinsic::hexagon_M2_mmpyuh_rs1; // "exagon. default: break;
M2.mmpyuh.rs1" case 's': // 1 string to match.
} if (memcmp(NameR.data()+16, "s.s0", 4))
break; break;
case 'l': // 2 strings to match. return Intrinsic::hexagon_M2_dpmpyss_s0; // "exagon.M2.dpmpy
if (NameR.substr(16, 3) != ".rs") ss.s0"
break; case 'u': // 1 string to match.
switch (NameR[19]) { if (memcmp(NameR.data()+16, "u.s0", 4))
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mmpyul_rs0; // "exagon.
M2.mmpyul.rs0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mmpyul_rs1; // "exagon.
M2.mmpyul.rs1"
}
break; break;
} return Intrinsic::hexagon_M2_dpmpyuu_s0; // "exagon.M2.dpmpy
break; uu.s0"
} }
break; break;
case 'p': // 16 strings to match. case 'h': // 2 strings to match.
if (NameR[12] != 'y') if (memcmp(NameR.data()+11, "mmpy", 4))
break; break;
switch (NameR[13]) { switch (NameR[15]) {
default: break; default: break;
case 'd': // 8 strings to match. case 'h': // 1 string to match.
if (NameR[14] != '.') if (memcmp(NameR.data()+16, ".rs1", 4))
break; break;
switch (NameR[15]) { return Intrinsic::hexagon_M2_hmmpyh_rs1; // "exagon.M2.hmmpy
h.rs1"
case 'l': // 1 string to match.
if (memcmp(NameR.data()+16, ".rs1", 4))
break;
return Intrinsic::hexagon_M2_hmmpyl_rs1; // "exagon.M2.hmmpy
l.rs1"
}
break;
case 'm': // 28 strings to match.
switch (NameR[11]) {
default: break;
case 'm': // 12 strings to match.
switch (NameR[12]) {
default: break; default: break;
case 'h': // 4 strings to match. case 'a': // 8 strings to match.
switch (NameR[16]) { if (NameR[13] != 'c')
break;
switch (NameR[14]) {
default: break; default: break;
case 'h': // 2 strings to match. case 'h': // 2 strings to match.
if (NameR.substr(17, 2) != ".s") if (memcmp(NameR.data()+15, "s.rs", 4))
break; break;
switch (NameR[19]) { switch (NameR[19]) {
default: break; default: break;
case '0': // 1 string to match. case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_hh_s0; // "exagon. M2.mpyd.hh.s0" return Intrinsic::hexagon_M2_mmachs_rs0; // "exagon. M2.mmachs.rs0"
case '1': // 1 string to match. case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_hh_s1; // "exagon. M2.mpyd.hh.s1" return Intrinsic::hexagon_M2_mmachs_rs1; // "exagon. M2.mmachs.rs1"
} }
break; break;
case 'l': // 2 strings to match. case 'l': // 2 strings to match.
if (NameR.substr(17, 2) != ".s") if (memcmp(NameR.data()+15, "s.rs", 4))
break; break;
switch (NameR[19]) { switch (NameR[19]) {
default: break; default: break;
case '0': // 1 string to match. case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_hl_s0; // "exagon. M2.mpyd.hl.s0" return Intrinsic::hexagon_M2_mmacls_rs0; // "exagon. M2.mmacls.rs0"
case '1': // 1 string to match. case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_hl_s1; // "exagon. return Intrinsic::hexagon_M2_mmacls_rs1; // "exagon.
M2.mpyd.hl.s1" M2.mmacls.rs1"
}
break;
case 'u': // 4 strings to match.
switch (NameR[15]) {
default: break;
case 'h': // 2 strings to match.
if (memcmp(NameR.data()+16, "s.s", 3))
break;
switch (NameR[19]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mmacuhs_s0; // "exagon.
M2.mmacuhs.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mmacuhs_s1; // "exagon.
M2.mmacuhs.s1"
}
break;
case 'l': // 2 strings to match.
if (memcmp(NameR.data()+16, "s.s", 3))
break;
switch (NameR[19]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mmaculs_s0; // "exagon.
M2.mmaculs.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mmaculs_s1; // "exagon.
M2.mmaculs.s1"
}
break;
} }
break; break;
} }
break; break;
case 'l': // 4 strings to match. case 'p': // 4 strings to match.
switch (NameR[16]) { if (memcmp(NameR.data()+13, "yu", 2))
break;
switch (NameR[15]) {
default: break; default: break;
case 'h': // 2 strings to match. case 'h': // 2 strings to match.
if (NameR.substr(17, 2) != ".s") if (memcmp(NameR.data()+16, ".rs", 3))
break; break;
switch (NameR[19]) { switch (NameR[19]) {
default: break; default: break;
case '0': // 1 string to match. case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_lh_s0; // "exagon. M2.mpyd.lh.s0" return Intrinsic::hexagon_M2_mmpyuh_rs0; // "exagon. M2.mmpyuh.rs0"
case '1': // 1 string to match. case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_lh_s1; // "exagon. M2.mpyd.lh.s1" return Intrinsic::hexagon_M2_mmpyuh_rs1; // "exagon. M2.mmpyuh.rs1"
} }
break; break;
case 'l': // 2 strings to match. case 'l': // 2 strings to match.
if (NameR.substr(17, 2) != ".s") if (memcmp(NameR.data()+16, ".rs", 3))
break; break;
switch (NameR[19]) { switch (NameR[19]) {
default: break; default: break;
case '0': // 1 string to match. case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_ll_s0; // "exagon. M2.mpyd.ll.s0" return Intrinsic::hexagon_M2_mmpyul_rs0; // "exagon. M2.mmpyul.rs0"
case '1': // 1 string to match. case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_ll_s1; // "exagon. M2.mpyd.ll.s1" return Intrinsic::hexagon_M2_mmpyul_rs1; // "exagon. M2.mmpyul.rs1"
} }
break; break;
} }
break; break;
} }
break; break;
case 'u': // 8 strings to match. case 'p': // 16 strings to match.
if (NameR[14] != '.') if (NameR[12] != 'y')
break; break;
switch (NameR[15]) { switch (NameR[13]) {
default: break; default: break;
case 'h': // 4 strings to match. case 'd': // 8 strings to match.
switch (NameR[16]) { if (NameR[14] != '.')
break;
switch (NameR[15]) {
default: break; default: break;
case 'h': // 2 strings to match. case 'h': // 4 strings to match.
if (NameR.substr(17, 2) != ".s") switch (NameR[16]) {
break;
switch (NameR[19]) {
default: break; default: break;
case '0': // 1 string to match. case 'h': // 2 strings to match.
return Intrinsic::hexagon_M2_mpyu_hh_s0; // "exagon. if (memcmp(NameR.data()+17, ".s", 2))
M2.mpyu.hh.s0" break;
case '1': // 1 string to match. switch (NameR[19]) {
return Intrinsic::hexagon_M2_mpyu_hh_s1; // "exagon. default: break;
M2.mpyu.hh.s1" case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_hh_s0; // "exagon.
M2.mpyd.hh.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_hh_s1; // "exagon.
M2.mpyd.hh.s1"
}
break;
case 'l': // 2 strings to match.
if (memcmp(NameR.data()+17, ".s", 2))
break;
switch (NameR[19]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_hl_s0; // "exagon.
M2.mpyd.hl.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_hl_s1; // "exagon.
M2.mpyd.hl.s1"
}
break;
} }
break; break;
case 'l': // 2 strings to match. case 'l': // 4 strings to match.
if (NameR.substr(17, 2) != ".s") switch (NameR[16]) {
break;
switch (NameR[19]) {
default: break; default: break;
case '0': // 1 string to match. case 'h': // 2 strings to match.
return Intrinsic::hexagon_M2_mpyu_hl_s0; // "exagon. if (memcmp(NameR.data()+17, ".s", 2))
M2.mpyu.hl.s0" break;
case '1': // 1 string to match. switch (NameR[19]) {
return Intrinsic::hexagon_M2_mpyu_hl_s1; // "exagon. default: break;
M2.mpyu.hl.s1" case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_lh_s0; // "exagon.
M2.mpyd.lh.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_lh_s1; // "exagon.
M2.mpyd.lh.s1"
}
break;
case 'l': // 2 strings to match.
if (memcmp(NameR.data()+17, ".s", 2))
break;
switch (NameR[19]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_ll_s0; // "exagon.
M2.mpyd.ll.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_ll_s1; // "exagon.
M2.mpyd.ll.s1"
}
break;
} }
break; break;
} }
break; break;
case 'l': // 4 strings to match. case 'u': // 8 strings to match.
switch (NameR[16]) { if (NameR[14] != '.')
break;
switch (NameR[15]) {
default: break; default: break;
case 'h': // 2 strings to match. case 'h': // 4 strings to match.
if (NameR.substr(17, 2) != ".s") switch (NameR[16]) {
break;
switch (NameR[19]) {
default: break; default: break;
case '0': // 1 string to match. case 'h': // 2 strings to match.
return Intrinsic::hexagon_M2_mpyu_lh_s0; // "exagon. if (memcmp(NameR.data()+17, ".s", 2))
M2.mpyu.lh.s0" break;
case '1': // 1 string to match. switch (NameR[19]) {
return Intrinsic::hexagon_M2_mpyu_lh_s1; // "exagon. default: break;
M2.mpyu.lh.s1" case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyu_hh_s0; // "exagon.
M2.mpyu.hh.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyu_hh_s1; // "exagon.
M2.mpyu.hh.s1"
}
break;
case 'l': // 2 strings to match.
if (memcmp(NameR.data()+17, ".s", 2))
break;
switch (NameR[19]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyu_hl_s0; // "exagon.
M2.mpyu.hl.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyu_hl_s1; // "exagon.
M2.mpyu.hl.s1"
}
break;
} }
break; break;
case 'l': // 2 strings to match. case 'l': // 4 strings to match.
if (NameR.substr(17, 2) != ".s") switch (NameR[16]) {
break;
switch (NameR[19]) {
default: break; default: break;
case '0': // 1 string to match. case 'h': // 2 strings to match.
return Intrinsic::hexagon_M2_mpyu_ll_s0; // "exagon. if (memcmp(NameR.data()+17, ".s", 2))
M2.mpyu.ll.s0" break;
case '1': // 1 string to match. switch (NameR[19]) {
return Intrinsic::hexagon_M2_mpyu_ll_s1; // "exagon. default: break;
M2.mpyu.ll.s1" case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyu_lh_s0; // "exagon.
M2.mpyu.lh.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyu_lh_s1; // "exagon.
M2.mpyu.lh.s1"
}
break;
case 'l': // 2 strings to match.
if (memcmp(NameR.data()+17, ".s", 2))
break;
switch (NameR[19]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyu_ll_s0; // "exagon.
M2.mpyu.ll.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyu_ll_s1; // "exagon.
M2.mpyu.ll.s1"
}
break;
} }
break; break;
} }
break; break;
} }
break; break;
} }
break; break;
} case 'v': // 15 strings to match.
break; switch (NameR[11]) {
case 'v': // 11 strings to match.
switch (NameR[11]) {
default: break;
case 'd': // 2 strings to match.
if (NameR.substr(12, 7) != "mpyrs.s")
break;
switch (NameR[19]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_vdmpyrs_s0; // "exagon.M2.vdmpy
rs.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_vdmpyrs_s1; // "exagon.M2.vdmpy
rs.s1"
}
break;
case 'm': // 4 strings to match.
switch (NameR[12]) {
default: break; default: break;
case 'a': // 2 strings to match. case 'd': // 2 strings to match.
if (NameR.substr(13, 6) != "c2es.s") if (memcmp(NameR.data()+12, "mpyrs.s", 7))
break; break;
switch (NameR[19]) { switch (NameR[19]) {
default: break; default: break;
case '0': // 1 string to match. case '0': // 1 string to match.
return Intrinsic::hexagon_M2_vmac2es_s0; // "exagon. M2.vmac2es.s0" return Intrinsic::hexagon_M2_vdmpyrs_s0; // "exagon. M2.vdmpyrs.s0"
case '1': // 1 string to match. case '1': // 1 string to match.
return Intrinsic::hexagon_M2_vmac2es_s1; // "exagon. M2.vmac2es.s1" return Intrinsic::hexagon_M2_vdmpyrs_s1; // "exagon. M2.vdmpyrs.s1"
} }
break; break;
case 'p': // 2 strings to match. case 'm': // 8 strings to match.
if (NameR.substr(13, 6) != "y2es.s") switch (NameR[12]) {
break;
switch (NameR[19]) {
default: break; default: break;
case '0': // 1 string to match. case 'a': // 4 strings to match.
return Intrinsic::hexagon_M2_vmpy2es_s0; // "exagon. if (memcmp(NameR.data()+13, "c2", 2))
M2.vmpy2es.s0" break;
case '1': // 1 string to match. switch (NameR[15]) {
return Intrinsic::hexagon_M2_vmpy2es_s1; // "exagon. default: break;
M2.vmpy2es.s1" case 'e': // 2 strings to match.
} if (memcmp(NameR.data()+16, "s.s", 3))
break; break;
} switch (NameR[19]) {
break; default: break;
case 'r': // 5 strings to match. case '0': // 1 string to match.
if (NameR.substr(12, 2) != "cm") return Intrinsic::hexagon_M2_vmac2es_s0; // "exagon.
break; M2.vmac2es.s0"
switch (NameR[14]) { case '1': // 1 string to match.
default: break; return Intrinsic::hexagon_M2_vmac2es_s1; // "exagon.
case 'a': // 2 strings to match. M2.vmac2es.s1"
if (NameR[15] != 'c') }
break;
case 's': // 2 strings to match.
if (memcmp(NameR.data()+16, "u.s", 3))
break;
switch (NameR[19]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_vmac2su_s0; // "exagon.
M2.vmac2su.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_vmac2su_s1; // "exagon.
M2.vmac2su.s1"
}
break;
}
break; break;
switch (NameR[16]) { case 'p': // 4 strings to match.
default: break; if (memcmp(NameR.data()+13, "y2", 2))
case 'i': // 1 string to match.
if (NameR.substr(17, 3) != ".s0")
break; break;
return Intrinsic::hexagon_M2_vrcmaci_s0; // "exagon. switch (NameR[15]) {
M2.vrcmaci.s0" default: break;
case 'r': // 1 string to match. case 'e': // 2 strings to match.
if (NameR.substr(17, 3) != ".s0") if (memcmp(NameR.data()+16, "s.s", 3))
break;
switch (NameR[19]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_vmpy2es_s0; // "exagon.
M2.vmpy2es.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_vmpy2es_s1; // "exagon.
M2.vmpy2es.s1"
}
break;
case 's': // 2 strings to match.
if (memcmp(NameR.data()+16, "u.s", 3))
break;
switch (NameR[19]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_vmpy2su_s0; // "exagon.
M2.vmpy2su.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_vmpy2su_s1; // "exagon.
M2.vmpy2su.s1"
}
break; break;
return Intrinsic::hexagon_M2_vrcmacr_s0; // "exagon. }
M2.vrcmacr.s0" break;
} }
break; break;
case 'p': // 3 strings to match. case 'r': // 5 strings to match.
if (NameR[15] != 'y') if (memcmp(NameR.data()+12, "cm", 2))
break; break;
switch (NameR[16]) { switch (NameR[14]) {
default: break; default: break;
case 'i': // 1 string to match. case 'a': // 2 strings to match.
if (NameR.substr(17, 3) != ".s0") if (NameR[15] != 'c')
break;
return Intrinsic::hexagon_M2_vrcmpyi_s0; // "exagon.
M2.vrcmpyi.s0"
case 'r': // 1 string to match.
if (NameR.substr(17, 3) != ".s0")
break; break;
return Intrinsic::hexagon_M2_vrcmpyr_s0; // "exagon. switch (NameR[16]) {
M2.vrcmpyr.s0" default: break;
case 's': // 1 string to match. case 'i': // 1 string to match.
if (NameR.substr(17, 3) != ".s1") if (memcmp(NameR.data()+17, ".s0", 3))
break;
return Intrinsic::hexagon_M2_vrcmaci_s0; // "exagon.
M2.vrcmaci.s0"
case 'r': // 1 string to match.
if (memcmp(NameR.data()+17, ".s0", 3))
break;
return Intrinsic::hexagon_M2_vrcmacr_s0; // "exagon.
M2.vrcmacr.s0"
}
break;
case 'p': // 3 strings to match.
if (NameR[15] != 'y')
break; break;
return Intrinsic::hexagon_M2_vrcmpys_s1; // "exagon. switch (NameR[16]) {
M2.vrcmpys.s1" default: break;
case 'i': // 1 string to match.
if (memcmp(NameR.data()+17, ".s0", 3))
break;
return Intrinsic::hexagon_M2_vrcmpyi_s0; // "exagon.
M2.vrcmpyi.s0"
case 'r': // 1 string to match.
if (memcmp(NameR.data()+17, ".s0", 3))
break;
return Intrinsic::hexagon_M2_vrcmpyr_s0; // "exagon.
M2.vrcmpyr.s0"
case 's': // 1 string to match.
if (memcmp(NameR.data()+17, ".s1", 3))
break;
return Intrinsic::hexagon_M2_vrcmpys_s1; // "exagon.
M2.vrcmpys.s1"
}
break;
} }
break; break;
} }
break; break;
} }
break; break;
} case '4': // 9 strings to match.
break; if (NameR[9] != '.')
case 'S': // 17 strings to match.
if (NameR.substr(8, 2) != "2.")
break;
switch (NameR[10]) {
default: break;
case 'a': // 8 strings to match.
if (NameR[11] != 's')
break; break;
switch (NameR[12]) { switch (NameR[10]) {
default: break; default: break;
case 'l': // 4 strings to match. case 'm': // 4 strings to match.
if (NameR[13] != '.') if (memcmp(NameR.data()+11, "pyr", 3))
break; break;
switch (NameR[14]) { switch (NameR[14]) {
default: break; default: break;
case 'i': // 2 strings to match. case 'i': // 2 strings to match.
if (NameR[15] != '.') if (memcmp(NameR.data()+15, ".add", 4))
break; break;
switch (NameR[16]) { switch (NameR[19]) {
default: break; default: break;
case 'p': // 1 string to match. case 'i': // 1 string to match.
if (NameR.substr(17, 3) != ".or") return Intrinsic::hexagon_M4_mpyri_addi; // "exagon.
break; M4.mpyri.addi"
return Intrinsic::hexagon_S2_asl_i_p_or; // "exagon.
S2.asl.i.p.or"
case 'r': // 1 string to match. case 'r': // 1 string to match.
if (NameR.substr(17, 3) != ".or") return Intrinsic::hexagon_M4_mpyri_addr; // "exagon.
break; M4.mpyri.addr"
return Intrinsic::hexagon_S2_asl_i_r_or; // "exagon.
S2.asl.i.r.or"
} }
break; break;
case 'r': // 2 strings to match. case 'r': // 2 strings to match.
if (NameR[15] != '.') if (memcmp(NameR.data()+15, ".add", 4))
break; break;
switch (NameR[16]) { switch (NameR[19]) {
default: break; default: break;
case 'p': // 1 string to match. case 'i': // 1 string to match.
if (NameR.substr(17, 3) != ".or") return Intrinsic::hexagon_M4_mpyrr_addi; // "exagon.
break; M4.mpyrr.addi"
return Intrinsic::hexagon_S2_asl_r_p_or; // "exagon.
S2.asl.r.p.or"
case 'r': // 1 string to match. case 'r': // 1 string to match.
if (NameR.substr(17, 3) != ".or") return Intrinsic::hexagon_M4_mpyrr_addr; // "exagon.
break; M4.mpyrr.addr"
return Intrinsic::hexagon_S2_asl_r_r_or; // "exagon.
S2.asl.r.r.or"
} }
break; break;
} }
break; break;
case 'r': // 4 strings to match. case 'v': // 5 strings to match.
if (NameR[13] != '.') switch (NameR[11]) {
break;
switch (NameR[14]) {
default: break; default: break;
case 'i': // 2 strings to match. case 'p': // 1 string to match.
if (NameR[15] != '.') if (memcmp(NameR.data()+12, "mpyh.acc", 8))
break; break;
switch (NameR[16]) { return Intrinsic::hexagon_M4_vpmpyh_acc; // "exagon.M4.vpmpy
default: break; h.acc"
case 'p': // 1 string to match. case 'r': // 4 strings to match.
if (NameR.substr(17, 3) != ".or") if (memcmp(NameR.data()+12, "mpy", 3))
break;
return Intrinsic::hexagon_S2_asr_i_p_or; // "exagon.
S2.asr.i.p.or"
case 'r': // 1 string to match.
if (NameR.substr(17, 3) != ".or")
break;
return Intrinsic::hexagon_S2_asr_i_r_or; // "exagon.
S2.asr.i.r.or"
}
break;
case 'r': // 2 strings to match.
if (NameR[15] != '.')
break; break;
switch (NameR[16]) { switch (NameR[15]) {
default: break; default: break;
case 'p': // 1 string to match. case 'e': // 2 strings to match.
if (NameR.substr(17, 3) != ".or") if (memcmp(NameR.data()+16, "h.s", 3))
break; break;
return Intrinsic::hexagon_S2_asr_r_p_or; // "exagon. switch (NameR[19]) {
S2.asr.r.p.or" default: break;
case 'r': // 1 string to match. case '0': // 1 string to match.
if (NameR.substr(17, 3) != ".or") return Intrinsic::hexagon_M4_vrmpyeh_s0; // "exagon.
M4.vrmpyeh.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M4_vrmpyeh_s1; // "exagon.
M4.vrmpyeh.s1"
}
break;
case 'o': // 2 strings to match.
if (memcmp(NameR.data()+16, "h.s", 3))
break; break;
return Intrinsic::hexagon_S2_asr_r_r_or; // "exagon. switch (NameR[19]) {
S2.asr.r.r.or" default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M4_vrmpyoh_s0; // "exagon.
M4.vrmpyoh.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M4_vrmpyoh_s1; // "exagon.
M4.vrmpyoh.s1"
}
break;
} }
break; break;
} }
break; break;
} }
break; break;
case 'i': // 2 strings to match. }
if (NameR[11] != 'n') break;
break; case 'S': // 23 strings to match.
switch (NameR[12]) { switch (NameR[8]) {
default: break; default: break;
case 's': // 1 string to match. case '2': // 17 strings to match.
if (NameR.substr(13, 7) != "ertp.rp") if (NameR[9] != '.')
break;
return Intrinsic::hexagon_S2_insertp_rp; // "exagon.S2.inser
tp.rp"
case 't': // 1 string to match.
if (NameR.substr(13, 7) != "erleave")
break;
return Intrinsic::hexagon_S2_interleave; // "exagon.S2.inter
leave"
}
break;
case 'l': // 6 strings to match.
if (NameR[11] != 's')
break; break;
switch (NameR[12]) { switch (NameR[10]) {
default: break; default: break;
case 'l': // 2 strings to match. case 'a': // 8 strings to match.
if (NameR.substr(13, 3) != ".r.") if (NameR[11] != 's')
break; break;
switch (NameR[16]) { switch (NameR[12]) {
default: break; default: break;
case 'p': // 1 string to match. case 'l': // 4 strings to match.
if (NameR.substr(17, 3) != ".or") if (NameR[13] != '.')
break;
return Intrinsic::hexagon_S2_lsl_r_p_or; // "exagon.S2.lsl.r
.p.or"
case 'r': // 1 string to match.
if (NameR.substr(17, 3) != ".or")
break; break;
return Intrinsic::hexagon_S2_lsl_r_r_or; // "exagon.S2.lsl.r switch (NameR[14]) {
.r.or" default: break;
} case 'i': // 2 strings to match.
if (NameR[15] != '.')
break;
switch (NameR[16]) {
default: break;
case 'p': // 1 string to match.
if (memcmp(NameR.data()+17, ".or", 3))
break;
return Intrinsic::hexagon_S2_asl_i_p_or; // "exagon.
S2.asl.i.p.or"
case 'r': // 1 string to match.
if (memcmp(NameR.data()+17, ".or", 3))
break;
return Intrinsic::hexagon_S2_asl_i_r_or; // "exagon.
S2.asl.i.r.or"
}
break;
case 'r': // 2 strings to match.
if (NameR[15] != '.')
break;
switch (NameR[16]) {
default: break;
case 'p': // 1 string to match.
if (memcmp(NameR.data()+17, ".or", 3))
break;
return Intrinsic::hexagon_S2_asl_r_p_or; // "exagon.
S2.asl.r.p.or"
case 'r': // 1 string to match.
if (memcmp(NameR.data()+17, ".or", 3))
break;
return Intrinsic::hexagon_S2_asl_r_r_or; // "exagon.
S2.asl.r.r.or"
}
break;
}
break;
case 'r': // 4 strings to match.
if (NameR[13] != '.')
break;
switch (NameR[14]) {
default: break;
case 'i': // 2 strings to match.
if (NameR[15] != '.')
break;
switch (NameR[16]) {
default: break;
case 'p': // 1 string to match.
if (memcmp(NameR.data()+17, ".or", 3))
break;
return Intrinsic::hexagon_S2_asr_i_p_or; // "exagon.
S2.asr.i.p.or"
case 'r': // 1 string to match.
if (memcmp(NameR.data()+17, ".or", 3))
break;
return Intrinsic::hexagon_S2_asr_i_r_or; // "exagon.
S2.asr.i.r.or"
}
break;
case 'r': // 2 strings to match.
if (NameR[15] != '.')
break;
switch (NameR[16]) {
default: break;
case 'p': // 1 string to match.
if (memcmp(NameR.data()+17, ".or", 3))
break;
return Intrinsic::hexagon_S2_asr_r_p_or; // "exagon.
S2.asr.r.p.or"
case 'r': // 1 string to match.
if (memcmp(NameR.data()+17, ".or", 3))
break;
return Intrinsic::hexagon_S2_asr_r_r_or; // "exagon.
S2.asr.r.r.or"
}
break;
}
break;
}
break; break;
case 'r': // 4 strings to match. case 'i': // 2 strings to match.
if (NameR[13] != '.') if (NameR[11] != 'n')
break; break;
switch (NameR[14]) { switch (NameR[12]) {
default: break; default: break;
case 'i': // 2 strings to match. case 's': // 1 string to match.
if (NameR[15] != '.') if (memcmp(NameR.data()+13, "ertp.rp", 7))
break;
return Intrinsic::hexagon_S2_insertp_rp; // "exagon.S2.inser
tp.rp"
case 't': // 1 string to match.
if (memcmp(NameR.data()+13, "erleave", 7))
break;
return Intrinsic::hexagon_S2_interleave; // "exagon.S2.inter
leave"
}
break;
case 'l': // 6 strings to match.
if (NameR[11] != 's')
break;
switch (NameR[12]) {
default: break;
case 'l': // 2 strings to match.
if (memcmp(NameR.data()+13, ".r.", 3))
break; break;
switch (NameR[16]) { switch (NameR[16]) {
default: break; default: break;
case 'p': // 1 string to match. case 'p': // 1 string to match.
if (NameR.substr(17, 3) != ".or") if (memcmp(NameR.data()+17, ".or", 3))
break; break;
return Intrinsic::hexagon_S2_lsr_i_p_or; // "exagon. S2.lsr.i.p.or" return Intrinsic::hexagon_S2_lsl_r_p_or; // "exagon. S2.lsl.r.p.or"
case 'r': // 1 string to match. case 'r': // 1 string to match.
if (NameR.substr(17, 3) != ".or") if (memcmp(NameR.data()+17, ".or", 3))
break; break;
return Intrinsic::hexagon_S2_lsr_i_r_or; // "exagon. S2.lsr.i.r.or" return Intrinsic::hexagon_S2_lsl_r_r_or; // "exagon. S2.lsl.r.r.or"
} }
break; break;
case 'r': // 2 strings to match. case 'r': // 4 strings to match.
if (NameR[15] != '.') if (NameR[13] != '.')
break; break;
switch (NameR[16]) { switch (NameR[14]) {
default: break; default: break;
case 'p': // 1 string to match. case 'i': // 2 strings to match.
if (NameR.substr(17, 3) != ".or") if (NameR[15] != '.')
break; break;
return Intrinsic::hexagon_S2_lsr_r_p_or; // "exagon. switch (NameR[16]) {
S2.lsr.r.p.or" default: break;
case 'r': // 1 string to match. case 'p': // 1 string to match.
if (NameR.substr(17, 3) != ".or") if (memcmp(NameR.data()+17, ".or", 3))
break;
return Intrinsic::hexagon_S2_lsr_i_p_or; // "exagon.
S2.lsr.i.p.or"
case 'r': // 1 string to match.
if (memcmp(NameR.data()+17, ".or", 3))
break;
return Intrinsic::hexagon_S2_lsr_i_r_or; // "exagon.
S2.lsr.i.r.or"
}
break;
case 'r': // 2 strings to match.
if (NameR[15] != '.')
break; break;
return Intrinsic::hexagon_S2_lsr_r_r_or; // "exagon. switch (NameR[16]) {
S2.lsr.r.r.or" default: break;
case 'p': // 1 string to match.
if (memcmp(NameR.data()+17, ".or", 3))
break;
return Intrinsic::hexagon_S2_lsr_r_p_or; // "exagon.
S2.lsr.r.p.or"
case 'r': // 1 string to match.
if (memcmp(NameR.data()+17, ".or", 3))
break;
return Intrinsic::hexagon_S2_lsr_r_r_or; // "exagon.
S2.lsr.r.r.or"
}
break;
} }
break; break;
} }
break; break;
case 'v': // 1 string to match.
if (memcmp(NameR.data()+11, "rndpackwh", 9))
break;
return Intrinsic::hexagon_S2_vrndpackwh; // "exagon.S2.vrndp
ackwh"
} }
break; break;
case 'v': // 1 string to match. case '4': // 5 strings to match.
if (NameR.substr(11, 9) != "rndpackwh") if (NameR[9] != '.')
break;
switch (NameR[10]) {
default: break;
case 'e': // 1 string to match.
if (memcmp(NameR.data()+11, "xtract.rp", 9))
break;
return Intrinsic::hexagon_S4_extract_rp; // "exagon.S4.extra
ct.rp"
case 'o': // 2 strings to match.
if (memcmp(NameR.data()+11, "ri.", 3))
break;
switch (NameR[14]) {
default: break;
case 'a': // 1 string to match.
if (memcmp(NameR.data()+15, "sl.ri", 5))
break;
return Intrinsic::hexagon_S4_ori_asl_ri; // "exagon.S4.ori.a
sl.ri"
case 'l': // 1 string to match.
if (memcmp(NameR.data()+15, "sr.ri", 5))
break;
return Intrinsic::hexagon_S4_ori_lsr_ri; // "exagon.S4.ori.l
sr.ri"
}
break;
case 'v': // 2 strings to match.
if (NameR[11] != 'x')
break;
switch (NameR[12]) {
default: break;
case 'a': // 1 string to match.
if (memcmp(NameR.data()+13, "ddsubhr", 7))
break;
return Intrinsic::hexagon_S4_vxaddsubhr; // "exagon.S4.vxadd
subhr"
case 's': // 1 string to match.
if (memcmp(NameR.data()+13, "ubaddhr", 7))
break;
return Intrinsic::hexagon_S4_vxsubaddhr; // "exagon.S4.vxsub
addhr"
}
break;
}
break;
case '5': // 1 string to match.
if (memcmp(NameR.data()+9, ".asrhub.sat", 11))
break; break;
return Intrinsic::hexagon_S2_vrndpackwh; // "exagon.S2.vrndp ackwh" return Intrinsic::hexagon_S5_asrhub_sat; // "exagon.S5.asrhu b.sat"
} }
break; break;
} }
break; break;
case 21: // 84 strings to match. case 21: // 96 strings to match.
if (NameR.substr(0, 7) != "exagon.") if (memcmp(NameR.data()+0, "exagon.", 7))
break; break;
switch (NameR[7]) { switch (NameR[7]) {
default: break; default: break;
case 'A': // 16 strings to match. case 'A': // 16 strings to match.
if (NameR.substr(8, 2) != "2.") switch (NameR[8]) {
break;
switch (NameR[10]) {
default: break; default: break;
case 'a': // 8 strings to match. case '2': // 14 strings to match.
if (NameR.substr(11, 4) != "ddh.") if (NameR[9] != '.')
break; break;
switch (NameR[15]) { switch (NameR[10]) {
default: break; default: break;
case 'h': // 4 strings to match. case 'a': // 6 strings to match.
if (NameR.substr(16, 3) != "16.") if (memcmp(NameR.data()+11, "ddh.", 4))
break; break;
switch (NameR[19]) { switch (NameR[15]) {
default: break; default: break;
case 'h': // 2 strings to match. case 'h': // 4 strings to match.
switch (NameR[20]) { if (memcmp(NameR.data()+16, "16.", 3))
break;
switch (NameR[19]) {
default: break; default: break;
case 'h': // 1 string to match. case 'h': // 2 strings to match.
return Intrinsic::hexagon_A2_addh_h16_hh; // "exagon. switch (NameR[20]) {
A2.addh.h16.hh" default: break;
case 'l': // 1 string to match. case 'h': // 1 string to match.
return Intrinsic::hexagon_A2_addh_h16_hl; // "exagon. return Intrinsic::hexagon_A2_addh_h16_hh; // "exagon.
A2.addh.h16.hl" A2.addh.h16.hh"
case 'l': // 1 string to match.
return Intrinsic::hexagon_A2_addh_h16_hl; // "exagon.
A2.addh.h16.hl"
}
break;
case 'l': // 2 strings to match.
switch (NameR[20]) {
default: break;
case 'h': // 1 string to match.
return Intrinsic::hexagon_A2_addh_h16_lh; // "exagon.
A2.addh.h16.lh"
case 'l': // 1 string to match.
return Intrinsic::hexagon_A2_addh_h16_ll; // "exagon.
A2.addh.h16.ll"
}
break;
} }
break; break;
case 'l': // 2 strings to match. case 'l': // 2 strings to match.
switch (NameR[20]) { if (memcmp(NameR.data()+16, "16.", 3))
default: break; break;
case 'h': // 1 string to match. switch (NameR[19]) {
return Intrinsic::hexagon_A2_addh_h16_lh; // "exagon.
A2.addh.h16.lh"
case 'l': // 1 string to match.
return Intrinsic::hexagon_A2_addh_h16_ll; // "exagon.
A2.addh.h16.ll"
}
break;
}
break;
case 'l': // 4 strings to match.
if (NameR.substr(16, 3) != "16.")
break;
switch (NameR[19]) {
default: break;
case 'h': // 2 strings to match.
switch (NameR[20]) {
default: break; default: break;
case 'h': // 1 string to match. case 'h': // 1 string to match.
return Intrinsic::hexagon_A2_addh_l16_hh; // "exagon. if (NameR[20] != 'l')
A2.addh.l16.hh" break;
case 'l': // 1 string to match.
return Intrinsic::hexagon_A2_addh_l16_hl; // "exagon. A2.addh.l16.hl" return Intrinsic::hexagon_A2_addh_l16_hl; // "exagon. A2.addh.l16.hl"
}
break;
case 'l': // 2 strings to match.
switch (NameR[20]) {
default: break;
case 'h': // 1 string to match.
return Intrinsic::hexagon_A2_addh_l16_lh; // "exagon.
A2.addh.l16.lh"
case 'l': // 1 string to match. case 'l': // 1 string to match.
if (NameR[20] != 'l')
break;
return Intrinsic::hexagon_A2_addh_l16_ll; // "exagon. A2.addh.l16.ll" return Intrinsic::hexagon_A2_addh_l16_ll; // "exagon. A2.addh.l16.ll"
} }
break; break;
} }
break; break;
} case 's': // 6 strings to match.
break; if (memcmp(NameR.data()+11, "ubh.", 4))
case 's': // 6 strings to match.
if (NameR.substr(11, 4) != "ubh.")
break;
switch (NameR[15]) {
default: break;
case 'h': // 4 strings to match.
if (NameR.substr(16, 3) != "16.")
break; break;
switch (NameR[19]) { switch (NameR[15]) {
default: break; default: break;
case 'h': // 2 strings to match. case 'h': // 4 strings to match.
switch (NameR[20]) { if (memcmp(NameR.data()+16, "16.", 3))
break;
switch (NameR[19]) {
default: break; default: break;
case 'h': // 1 string to match. case 'h': // 2 strings to match.
return Intrinsic::hexagon_A2_subh_h16_hh; // "exagon. switch (NameR[20]) {
A2.subh.h16.hh" default: break;
case 'l': // 1 string to match. case 'h': // 1 string to match.
return Intrinsic::hexagon_A2_subh_h16_hl; // "exagon. return Intrinsic::hexagon_A2_subh_h16_hh; // "exagon.
A2.subh.h16.hl" A2.subh.h16.hh"
case 'l': // 1 string to match.
return Intrinsic::hexagon_A2_subh_h16_hl; // "exagon.
A2.subh.h16.hl"
}
break;
case 'l': // 2 strings to match.
switch (NameR[20]) {
default: break;
case 'h': // 1 string to match.
return Intrinsic::hexagon_A2_subh_h16_lh; // "exagon.
A2.subh.h16.lh"
case 'l': // 1 string to match.
return Intrinsic::hexagon_A2_subh_h16_ll; // "exagon.
A2.subh.h16.ll"
}
break;
} }
break; break;
case 'l': // 2 strings to match. case 'l': // 2 strings to match.
switch (NameR[20]) { if (memcmp(NameR.data()+16, "16.", 3))
break;
switch (NameR[19]) {
default: break; default: break;
case 'h': // 1 string to match. case 'h': // 1 string to match.
return Intrinsic::hexagon_A2_subh_h16_lh; // "exagon. if (NameR[20] != 'l')
A2.subh.h16.lh" break;
return Intrinsic::hexagon_A2_subh_l16_hl; // "exagon.
A2.subh.l16.hl"
case 'l': // 1 string to match. case 'l': // 1 string to match.
return Intrinsic::hexagon_A2_subh_h16_ll; // "exagon. if (NameR[20] != 'l')
A2.subh.h16.ll" break;
return Intrinsic::hexagon_A2_subh_l16_ll; // "exagon.
A2.subh.l16.ll"
} }
break; break;
} }
break; break;
case 'l': // 2 strings to match. case 'v': // 2 strings to match.
if (NameR.substr(16, 3) != "16.") if (NameR[11] != 'r')
break; break;
switch (NameR[19]) { switch (NameR[12]) {
default: break; default: break;
case 'h': // 1 string to match. case 'a': // 1 string to match.
if (NameR[20] != 'l') if (memcmp(NameR.data()+13, "ddub.acc", 8))
break; break;
return Intrinsic::hexagon_A2_subh_l16_hl; // "exagon. return Intrinsic::hexagon_A2_vraddub_acc; // "exagon.
A2.subh.l16.hl" A2.vraddub.acc"
case 'l': // 1 string to match. case 's': // 1 string to match.
if (NameR[20] != 'l') if (memcmp(NameR.data()+13, "adub.acc", 8))
break; break;
return Intrinsic::hexagon_A2_subh_l16_ll; // "exagon. A2.subh.l16.ll" return Intrinsic::hexagon_A2_vrsadub_acc; // "exagon. A2.vrsadub.acc"
} }
break; break;
} }
break; break;
case 'v': // 2 strings to match. case '4': // 2 strings to match.
if (NameR[11] != 'r') if (NameR[9] != '.')
break; break;
switch (NameR[12]) { switch (NameR[10]) {
default: break; default: break;
case 'a': // 1 string to match. case 'b': // 1 string to match.
if (NameR.substr(13, 8) != "ddub.acc") if (memcmp(NameR.data()+11, "oundscheck", 10))
break; break;
return Intrinsic::hexagon_A2_vraddub_acc; // "exagon.A2.vradd return Intrinsic::hexagon_A4_boundscheck; // "exagon.A4.bound
ub.acc" scheck"
case 's': // 1 string to match. case 'v': // 1 string to match.
if (NameR.substr(13, 8) != "adub.acc") if (memcmp(NameR.data()+11, "cmpbeq.any", 10))
break; break;
return Intrinsic::hexagon_A2_vrsadub_acc; // "exagon.A2.vrsad ub.acc" return Intrinsic::hexagon_A4_vcmpbeq_any; // "exagon.A4.vcmpb eq.any"
} }
break; break;
} }
break; break;
case 'C': // 1 string to match. case 'C': // 1 string to match.
if (NameR.substr(8, 13) != "4.fastcorner9") if (memcmp(NameR.data()+8, "4.fastcorner9", 13))
break; break;
return Intrinsic::hexagon_C4_fastcorner9; // "exagon.C4.fastc orner9" return Intrinsic::hexagon_C4_fastcorner9; // "exagon.C4.fastc orner9"
case 'M': // 16 strings to match. case 'M': // 16 strings to match.
if (NameR.substr(8, 2) != "2.") if (memcmp(NameR.data()+8, "2.", 2))
break; break;
switch (NameR[10]) { switch (NameR[10]) {
default: break; default: break;
case 'm': // 12 strings to match. case 'm': // 12 strings to match.
switch (NameR[11]) { switch (NameR[11]) {
default: break; default: break;
case 'm': // 4 strings to match. case 'm': // 4 strings to match.
if (NameR.substr(12, 3) != "acu") if (memcmp(NameR.data()+12, "acu", 3))
break; break;
switch (NameR[15]) { switch (NameR[15]) {
default: break; default: break;
case 'h': // 2 strings to match. case 'h': // 2 strings to match.
if (NameR.substr(16, 4) != "s.rs") if (memcmp(NameR.data()+16, "s.rs", 4))
break; break;
switch (NameR[20]) { switch (NameR[20]) {
default: break; default: break;
case '0': // 1 string to match. case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mmacuhs_rs0; // "exagon. M2.mmacuhs.rs0" return Intrinsic::hexagon_M2_mmacuhs_rs0; // "exagon. M2.mmacuhs.rs0"
case '1': // 1 string to match. case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mmacuhs_rs1; // "exagon. M2.mmacuhs.rs1" return Intrinsic::hexagon_M2_mmacuhs_rs1; // "exagon. M2.mmacuhs.rs1"
} }
break; break;
case 'l': // 2 strings to match. case 'l': // 2 strings to match.
if (NameR.substr(16, 4) != "s.rs") if (memcmp(NameR.data()+16, "s.rs", 4))
break; break;
switch (NameR[20]) { switch (NameR[20]) {
default: break; default: break;
case '0': // 1 string to match. case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mmaculs_rs0; // "exagon. M2.mmaculs.rs0" return Intrinsic::hexagon_M2_mmaculs_rs0; // "exagon. M2.mmaculs.rs0"
case '1': // 1 string to match. case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mmaculs_rs1; // "exagon. M2.mmaculs.rs1" return Intrinsic::hexagon_M2_mmaculs_rs1; // "exagon. M2.mmaculs.rs1"
} }
break; break;
} }
break; break;
case 'p': // 8 strings to match. case 'p': // 8 strings to match.
if (NameR.substr(12, 4) != "yud.") if (memcmp(NameR.data()+12, "yud.", 4))
break; break;
switch (NameR[16]) { switch (NameR[16]) {
default: break; default: break;
case 'h': // 4 strings to match. case 'h': // 4 strings to match.
switch (NameR[17]) { switch (NameR[17]) {
default: break; default: break;
case 'h': // 2 strings to match. case 'h': // 2 strings to match.
if (NameR.substr(18, 2) != ".s") if (memcmp(NameR.data()+18, ".s", 2))
break; break;
switch (NameR[20]) { switch (NameR[20]) {
default: break; default: break;
case '0': // 1 string to match. case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyud_hh_s0; // "exagon. M2.mpyud.hh.s0" return Intrinsic::hexagon_M2_mpyud_hh_s0; // "exagon. M2.mpyud.hh.s0"
case '1': // 1 string to match. case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyud_hh_s1; // "exagon. M2.mpyud.hh.s1" return Intrinsic::hexagon_M2_mpyud_hh_s1; // "exagon. M2.mpyud.hh.s1"
} }
break; break;
case 'l': // 2 strings to match. case 'l': // 2 strings to match.
if (NameR.substr(18, 2) != ".s") if (memcmp(NameR.data()+18, ".s", 2))
break; break;
switch (NameR[20]) { switch (NameR[20]) {
default: break; default: break;
case '0': // 1 string to match. case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyud_hl_s0; // "exagon. M2.mpyud.hl.s0" return Intrinsic::hexagon_M2_mpyud_hl_s0; // "exagon. M2.mpyud.hl.s0"
case '1': // 1 string to match. case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyud_hl_s1; // "exagon. M2.mpyud.hl.s1" return Intrinsic::hexagon_M2_mpyud_hl_s1; // "exagon. M2.mpyud.hl.s1"
} }
break; break;
} }
break; break;
case 'l': // 4 strings to match. case 'l': // 4 strings to match.
switch (NameR[17]) { switch (NameR[17]) {
default: break; default: break;
case 'h': // 2 strings to match. case 'h': // 2 strings to match.
if (NameR.substr(18, 2) != ".s") if (memcmp(NameR.data()+18, ".s", 2))
break; break;
switch (NameR[20]) { switch (NameR[20]) {
default: break; default: break;
case '0': // 1 string to match. case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyud_lh_s0; // "exagon. M2.mpyud.lh.s0" return Intrinsic::hexagon_M2_mpyud_lh_s0; // "exagon. M2.mpyud.lh.s0"
case '1': // 1 string to match. case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyud_lh_s1; // "exagon. M2.mpyud.lh.s1" return Intrinsic::hexagon_M2_mpyud_lh_s1; // "exagon. M2.mpyud.lh.s1"
} }
break; break;
case 'l': // 2 strings to match. case 'l': // 2 strings to match.
if (NameR.substr(18, 2) != ".s") if (memcmp(NameR.data()+18, ".s", 2))
break; break;
switch (NameR[20]) { switch (NameR[20]) {
default: break; default: break;
case '0': // 1 string to match. case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyud_ll_s0; // "exagon. M2.mpyud.ll.s0" return Intrinsic::hexagon_M2_mpyud_ll_s0; // "exagon. M2.mpyud.ll.s0"
case '1': // 1 string to match. case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyud_ll_s1; // "exagon. M2.mpyud.ll.s1" return Intrinsic::hexagon_M2_mpyud_ll_s1; // "exagon. M2.mpyud.ll.s1"
} }
break; break;
} }
break; break;
} }
break; break;
} }
break; break;
case 'v': // 4 strings to match. case 'v': // 4 strings to match.
if (NameR.substr(11, 3) != "rcm") if (memcmp(NameR.data()+11, "rcm", 3))
break; break;
switch (NameR[14]) { switch (NameR[14]) {
default: break; default: break;
case 'a': // 2 strings to match. case 'a': // 2 strings to match.
if (NameR[15] != 'c') if (NameR[15] != 'c')
break; break;
switch (NameR[16]) { switch (NameR[16]) {
default: break; default: break;
case 'i': // 1 string to match. case 'i': // 1 string to match.
if (NameR.substr(17, 4) != ".s0c") if (memcmp(NameR.data()+17, ".s0c", 4))
break; break;
return Intrinsic::hexagon_M2_vrcmaci_s0c; // "exagon. M2.vrcmaci.s0c" return Intrinsic::hexagon_M2_vrcmaci_s0c; // "exagon. M2.vrcmaci.s0c"
case 'r': // 1 string to match. case 'r': // 1 string to match.
if (NameR.substr(17, 4) != ".s0c") if (memcmp(NameR.data()+17, ".s0c", 4))
break; break;
return Intrinsic::hexagon_M2_vrcmacr_s0c; // "exagon. M2.vrcmacr.s0c" return Intrinsic::hexagon_M2_vrcmacr_s0c; // "exagon. M2.vrcmacr.s0c"
} }
break; break;
case 'p': // 2 strings to match. case 'p': // 2 strings to match.
if (NameR[15] != 'y') if (NameR[15] != 'y')
break; break;
switch (NameR[16]) { switch (NameR[16]) {
default: break; default: break;
case 'i': // 1 string to match. case 'i': // 1 string to match.
if (NameR.substr(17, 4) != ".s0c") if (memcmp(NameR.data()+17, ".s0c", 4))
break; break;
return Intrinsic::hexagon_M2_vrcmpyi_s0c; // "exagon. M2.vrcmpyi.s0c" return Intrinsic::hexagon_M2_vrcmpyi_s0c; // "exagon. M2.vrcmpyi.s0c"
case 'r': // 1 string to match. case 'r': // 1 string to match.
if (NameR.substr(17, 4) != ".s0c") if (memcmp(NameR.data()+17, ".s0c", 4))
break; break;
return Intrinsic::hexagon_M2_vrcmpyr_s0c; // "exagon. M2.vrcmpyr.s0c" return Intrinsic::hexagon_M2_vrcmpyr_s0c; // "exagon. M2.vrcmpyr.s0c"
} }
break; break;
} }
break; break;
} }
break; break;
case 'S': // 51 strings to match. case 'S': // 63 strings to match.
if (NameR.substr(8, 2) != "2.") switch (NameR[8]) {
break;
switch (NameR[10]) {
default: break; default: break;
case 'a': // 29 strings to match. case '2': // 56 strings to match.
switch (NameR[11]) { if (NameR[9] != '.')
break;
switch (NameR[10]) {
default: break; default: break;
case 'd': // 1 string to match. case 'a': // 32 strings to match.
if (NameR.substr(12, 9) != "dasl.rrri") switch (NameR[11]) {
break;
return Intrinsic::hexagon_S2_addasl_rrri; // "exagon.S2.addas
l.rrri"
case 's': // 28 strings to match.
switch (NameR[12]) {
default: break; default: break;
case 'l': // 14 strings to match. case 'd': // 1 string to match.
if (NameR[13] != '.') if (memcmp(NameR.data()+12, "dasl.rrri", 9))
break; break;
switch (NameR[14]) { return Intrinsic::hexagon_S2_addasl_rrri; // "exagon.
S2.addasl.rrri"
case 's': // 31 strings to match.
switch (NameR[12]) {
default: break; default: break;
case 'i': // 7 strings to match. case 'l': // 15 strings to match.
if (NameR[15] != '.') if (NameR[13] != '.')
break; break;
switch (NameR[16]) { switch (NameR[14]) {
default: break; default: break;
case 'p': // 3 strings to match. case 'i': // 7 strings to match.
if (NameR[17] != '.') if (NameR[15] != '.')
break; break;
switch (NameR[18]) { switch (NameR[16]) {
default: break; default: break;
case 'a': // 2 strings to match. case 'p': // 3 strings to match.
switch (NameR[19]) { if (NameR[17] != '.')
break;
switch (NameR[18]) {
default: break; default: break;
case 'c': // 1 string to match. case 'a': // 2 strings to match.
if (NameR[20] != 'c') switch (NameR[19]) {
break; default: break;
return Intrinsic::hexagon_S2_asl_i_p_acc; // case 'c': // 1 string to match.
"exagon.S2.asl.i.p.acc" if (NameR[20] != 'c')
break;
return Intrinsic::hexagon_S2_asl_i_p_acc; //
"exagon.S2.asl.i.p.acc"
case 'n': // 1 string to match.
if (NameR[20] != 'd')
break;
return Intrinsic::hexagon_S2_asl_i_p_and; //
"exagon.S2.asl.i.p.and"
}
break;
case 'n': // 1 string to match. case 'n': // 1 string to match.
if (NameR[20] != 'd') if (memcmp(NameR.data()+19, "ac", 2))
break; break;
return Intrinsic::hexagon_S2_asl_i_p_and; // "exagon.S2.asl.i.p.and" return Intrinsic::hexagon_S2_asl_i_p_nac; // "exagon.S2.asl.i.p.nac"
} }
break; break;
case 'n': // 1 string to match. case 'r': // 4 strings to match.
if (NameR.substr(19, 2) != "ac") if (NameR[17] != '.')
break;
switch (NameR[18]) {
default: break;
case 'a': // 2 strings to match.
switch (NameR[19]) {
default: break;
case 'c': // 1 string to match.
if (NameR[20] != 'c')
break;
return Intrinsic::hexagon_S2_asl_i_r_acc; //
"exagon.S2.asl.i.r.acc"
case 'n': // 1 string to match.
if (NameR[20] != 'd')
break;
return Intrinsic::hexagon_S2_asl_i_r_and; //
"exagon.S2.asl.i.r.and"
}
break; break;
return Intrinsic::hexagon_S2_asl_i_p_nac; // "exagon. case 'n': // 1 string to match.
S2.asl.i.p.nac" if (memcmp(NameR.data()+19, "ac", 2))
break;
return Intrinsic::hexagon_S2_asl_i_r_nac; //
"exagon.S2.asl.i.r.nac"
case 's': // 1 string to match.
if (memcmp(NameR.data()+19, "at", 2))
break;
return Intrinsic::hexagon_S2_asl_i_r_sat; //
"exagon.S2.asl.i.r.sat"
}
break;
} }
break; break;
case 'r': // 4 strings to match. case 'r': // 8 strings to match.
if (NameR[17] != '.') if (NameR[15] != '.')
break; break;
switch (NameR[18]) { switch (NameR[16]) {
default: break; default: break;
case 'a': // 2 strings to match. case 'p': // 4 strings to match.
switch (NameR[19]) { if (NameR[17] != '.')
break;
switch (NameR[18]) {
default: break; default: break;
case 'c': // 1 string to match. case 'a': // 2 strings to match.
if (NameR[20] != 'c') switch (NameR[19]) {
break; default: break;
return Intrinsic::hexagon_S2_asl_i_r_acc; // case 'c': // 1 string to match.
"exagon.S2.asl.i.r.acc" if (NameR[20] != 'c')
break;
return Intrinsic::hexagon_S2_asl_r_p_acc; //
"exagon.S2.asl.r.p.acc"
case 'n': // 1 string to match.
if (NameR[20] != 'd')
break;
return Intrinsic::hexagon_S2_asl_r_p_and; //
"exagon.S2.asl.r.p.and"
}
break;
case 'n': // 1 string to match. case 'n': // 1 string to match.
if (NameR[20] != 'd') if (memcmp(NameR.data()+19, "ac", 2))
break;
return Intrinsic::hexagon_S2_asl_r_p_nac; //
"exagon.S2.asl.r.p.nac"
case 'x': // 1 string to match.
if (memcmp(NameR.data()+19, "or", 2))
break; break;
return Intrinsic::hexagon_S2_asl_i_r_and; // "exagon.S2.asl.i.r.and" return Intrinsic::hexagon_S2_asl_r_p_xor; // "exagon.S2.asl.r.p.xor"
} }
break; break;
case 'n': // 1 string to match. case 'r': // 4 strings to match.
if (NameR.substr(19, 2) != "ac") if (NameR[17] != '.')
break; break;
return Intrinsic::hexagon_S2_asl_i_r_nac; // "exagon. switch (NameR[18]) {
S2.asl.i.r.nac" default: break;
case 's': // 1 string to match. case 'a': // 2 strings to match.
if (NameR.substr(19, 2) != "at") switch (NameR[19]) {
default: break;
case 'c': // 1 string to match.
if (NameR[20] != 'c')
break;
return Intrinsic::hexagon_S2_asl_r_r_acc; //
"exagon.S2.asl.r.r.acc"
case 'n': // 1 string to match.
if (NameR[20] != 'd')
break;
return Intrinsic::hexagon_S2_asl_r_r_and; //
"exagon.S2.asl.r.r.and"
}
break; break;
return Intrinsic::hexagon_S2_asl_i_r_sat; // "exagon. case 'n': // 1 string to match.
S2.asl.i.r.sat" if (memcmp(NameR.data()+19, "ac", 2))
break;
return Intrinsic::hexagon_S2_asl_r_r_nac; //
"exagon.S2.asl.r.r.nac"
case 's': // 1 string to match.
if (memcmp(NameR.data()+19, "at", 2))
break;
return Intrinsic::hexagon_S2_asl_r_r_sat; //
"exagon.S2.asl.r.r.sat"
}
break;
} }
break; break;
} }
break; break;
case 'r': // 7 strings to match. case 'r': // 16 strings to match.
if (NameR[15] != '.') if (NameR[13] != '.')
break; break;
switch (NameR[16]) { switch (NameR[14]) {
default: break; default: break;
case 'p': // 3 strings to match. case 'i': // 8 strings to match.
if (NameR[17] != '.') if (NameR[15] != '.')
break; break;
switch (NameR[18]) { switch (NameR[16]) {
default: break; default: break;
case 'a': // 2 strings to match. case 'p': // 4 strings to match.
switch (NameR[19]) { if (NameR[17] != '.')
break;
switch (NameR[18]) {
default: break; default: break;
case 'c': // 1 string to match. case 'a': // 2 strings to match.
if (NameR[20] != 'c') switch (NameR[19]) {
break; default: break;
return Intrinsic::hexagon_S2_asl_r_p_acc; // case 'c': // 1 string to match.
"exagon.S2.asl.r.p.acc" if (NameR[20] != 'c')
break;
return Intrinsic::hexagon_S2_asr_i_p_acc; //
"exagon.S2.asr.i.p.acc"
case 'n': // 1 string to match.
if (NameR[20] != 'd')
break;
return Intrinsic::hexagon_S2_asr_i_p_and; //
"exagon.S2.asr.i.p.and"
}
break;
case 'n': // 1 string to match. case 'n': // 1 string to match.
if (NameR[20] != 'd') if (memcmp(NameR.data()+19, "ac", 2))
break; break;
return Intrinsic::hexagon_S2_asl_r_p_and; // return Intrinsic::hexagon_S2_asr_i_p_nac; //
"exagon.S2.asl.r.p.and" "exagon.S2.asr.i.p.nac"
case 'r': // 1 string to match.
if (memcmp(NameR.data()+19, "nd", 2))
break;
return Intrinsic::hexagon_S2_asr_i_p_rnd; //
"exagon.S2.asr.i.p.rnd"
} }
break; break;
case 'n': // 1 string to match. case 'r': // 4 strings to match.
if (NameR.substr(19, 2) != "ac") if (NameR[17] != '.')
break;
switch (NameR[18]) {
default: break;
case 'a': // 2 strings to match.
switch (NameR[19]) {
default: break;
case 'c': // 1 string to match.
if (NameR[20] != 'c')
break;
return Intrinsic::hexagon_S2_asr_i_r_acc; //
"exagon.S2.asr.i.r.acc"
case 'n': // 1 string to match.
if (NameR[20] != 'd')
break;
return Intrinsic::hexagon_S2_asr_i_r_and; //
"exagon.S2.asr.i.r.and"
}
break; break;
return Intrinsic::hexagon_S2_asl_r_p_nac; // "exagon. case 'n': // 1 string to match.
S2.asl.r.p.nac" if (memcmp(NameR.data()+19, "ac", 2))
break;
return Intrinsic::hexagon_S2_asr_i_r_nac; //
"exagon.S2.asr.i.r.nac"
case 'r': // 1 string to match.
if (memcmp(NameR.data()+19, "nd", 2))
break;
return Intrinsic::hexagon_S2_asr_i_r_rnd; //
"exagon.S2.asr.i.r.rnd"
}
break;
} }
break; break;
case 'r': // 4 strings to match. case 'r': // 8 strings to match.
if (NameR[17] != '.') if (NameR[15] != '.')
break; break;
switch (NameR[18]) { switch (NameR[16]) {
default: break; default: break;
case 'a': // 2 strings to match. case 'p': // 4 strings to match.
switch (NameR[19]) { if (NameR[17] != '.')
break;
switch (NameR[18]) {
default: break; default: break;
case 'c': // 1 string to match. case 'a': // 2 strings to match.
if (NameR[20] != 'c') switch (NameR[19]) {
default: break;
case 'c': // 1 string to match.
if (NameR[20] != 'c')
break;
return Intrinsic::hexagon_S2_asr_r_p_acc; //
"exagon.S2.asr.r.p.acc"
case 'n': // 1 string to match.
if (NameR[20] != 'd')
break;
return Intrinsic::hexagon_S2_asr_r_p_and; //
"exagon.S2.asr.r.p.and"
}
break;
case 'n': // 1 string to match.
if (memcmp(NameR.data()+19, "ac", 2))
break;
return Intrinsic::hexagon_S2_asr_r_p_nac; //
"exagon.S2.asr.r.p.nac"
case 'x': // 1 string to match.
if (memcmp(NameR.data()+19, "or", 2))
break; break;
return Intrinsic::hexagon_S2_asl_r_r_acc; // return Intrinsic::hexagon_S2_asr_r_p_xor; //
"exagon.S2.asl.r.r.acc" "exagon.S2.asr.r.p.xor"
}
break;
case 'r': // 4 strings to match.
if (NameR[17] != '.')
break;
switch (NameR[18]) {
default: break;
case 'a': // 2 strings to match.
switch (NameR[19]) {
default: break;
case 'c': // 1 string to match.
if (NameR[20] != 'c')
break;
return Intrinsic::hexagon_S2_asr_r_r_acc; //
"exagon.S2.asr.r.r.acc"
case 'n': // 1 string to match.
if (NameR[20] != 'd')
break;
return Intrinsic::hexagon_S2_asr_r_r_and; //
"exagon.S2.asr.r.r.and"
}
break;
case 'n': // 1 string to match. case 'n': // 1 string to match.
if (NameR[20] != 'd') if (memcmp(NameR.data()+19, "ac", 2))
break;
return Intrinsic::hexagon_S2_asr_r_r_nac; //
"exagon.S2.asr.r.r.nac"
case 's': // 1 string to match.
if (memcmp(NameR.data()+19, "at", 2))
break; break;
return Intrinsic::hexagon_S2_asl_r_r_and; // "exagon.S2.asl.r.r.and" return Intrinsic::hexagon_S2_asr_r_r_sat; // "exagon.S2.asr.r.r.sat"
} }
break; break;
}
break;
}
break;
}
break;
}
break;
case 'e': // 1 string to match.
if (memcmp(NameR.data()+11, "xtractu.rp", 10))
break;
return Intrinsic::hexagon_S2_extractu_rp; // "exagon.S2.extra
ctu.rp"
case 'l': // 20 strings to match.
if (NameR[11] != 's')
break;
switch (NameR[12]) {
default: break;
case 'l': // 7 strings to match.
if (memcmp(NameR.data()+13, ".r.", 3))
break;
switch (NameR[16]) {
default: break;
case 'p': // 4 strings to match.
if (NameR[17] != '.')
break;
switch (NameR[18]) {
default: break;
case 'a': // 2 strings to match.
switch (NameR[19]) {
default: break;
case 'c': // 1 string to match.
if (NameR[20] != 'c')
break;
return Intrinsic::hexagon_S2_lsl_r_p_acc; // "exagon.
S2.lsl.r.p.acc"
case 'n': // 1 string to match. case 'n': // 1 string to match.
if (NameR.substr(19, 2) != "ac") if (NameR[20] != 'd')
break; break;
return Intrinsic::hexagon_S2_asl_r_r_nac; // "exagon. return Intrinsic::hexagon_S2_lsl_r_p_and; // "exagon.
S2.asl.r.r.nac" S2.lsl.r.p.and"
case 's': // 1 string to match. }
if (NameR.substr(19, 2) != "at") break;
case 'n': // 1 string to match.
if (memcmp(NameR.data()+19, "ac", 2))
break;
return Intrinsic::hexagon_S2_lsl_r_p_nac; // "exagon.
S2.lsl.r.p.nac"
case 'x': // 1 string to match.
if (memcmp(NameR.data()+19, "or", 2))
break;
return Intrinsic::hexagon_S2_lsl_r_p_xor; // "exagon.
S2.lsl.r.p.xor"
}
break;
case 'r': // 3 strings to match.
if (NameR[17] != '.')
break;
switch (NameR[18]) {
default: break;
case 'a': // 2 strings to match.
switch (NameR[19]) {
default: break;
case 'c': // 1 string to match.
if (NameR[20] != 'c')
break; break;
return Intrinsic::hexagon_S2_asl_r_r_sat; // "exagon. return Intrinsic::hexagon_S2_lsl_r_r_acc; // "exagon.
S2.asl.r.r.sat" S2.lsl.r.r.acc"
case 'n': // 1 string to match.
if (NameR[20] != 'd')
break;
return Intrinsic::hexagon_S2_lsl_r_r_and; // "exagon.
S2.lsl.r.r.and"
} }
break; break;
case 'n': // 1 string to match.
if (memcmp(NameR.data()+19, "ac", 2))
break;
return Intrinsic::hexagon_S2_lsl_r_r_nac; // "exagon.
S2.lsl.r.r.nac"
} }
break; break;
} }
break; break;
case 'r': // 14 strings to match. case 'r': // 13 strings to match.
if (NameR[13] != '.') if (NameR[13] != '.')
break; break;
switch (NameR[14]) { switch (NameR[14]) {
default: break; default: break;
case 'i': // 7 strings to match. case 'i': // 6 strings to match.
if (NameR[15] != '.') if (NameR[15] != '.')
break; break;
switch (NameR[16]) { switch (NameR[16]) {
default: break; default: break;
case 'p': // 3 strings to match. case 'p': // 3 strings to match.
if (NameR[17] != '.') if (NameR[17] != '.')
break; break;
switch (NameR[18]) { switch (NameR[18]) {
default: break; default: break;
case 'a': // 2 strings to match. case 'a': // 2 strings to match.
switch (NameR[19]) { switch (NameR[19]) {
default: break; default: break;
case 'c': // 1 string to match. case 'c': // 1 string to match.
if (NameR[20] != 'c') if (NameR[20] != 'c')
break; break;
return Intrinsic::hexagon_S2_asr_i_p_acc; // "exagon.S2.asr.i.p.acc" return Intrinsic::hexagon_S2_lsr_i_p_acc; // "exagon.S2.lsr.i.p.acc"
case 'n': // 1 string to match. case 'n': // 1 string to match.
if (NameR[20] != 'd') if (NameR[20] != 'd')
break; break;
return Intrinsic::hexagon_S2_asr_i_p_and; // "exagon.S2.asr.i.p.and" return Intrinsic::hexagon_S2_lsr_i_p_and; // "exagon.S2.lsr.i.p.and"
} }
break; break;
case 'n': // 1 string to match. case 'n': // 1 string to match.
if (NameR.substr(19, 2) != "ac") if (memcmp(NameR.data()+19, "ac", 2))
break; break;
return Intrinsic::hexagon_S2_asr_i_p_nac; // "exagon. S2.asr.i.p.nac" return Intrinsic::hexagon_S2_lsr_i_p_nac; // "exagon. S2.lsr.i.p.nac"
} }
break; break;
case 'r': // 4 strings to match. case 'r': // 3 strings to match.
if (NameR[17] != '.') if (NameR[17] != '.')
break; break;
switch (NameR[18]) { switch (NameR[18]) {
default: break; default: break;
case 'a': // 2 strings to match. case 'a': // 2 strings to match.
switch (NameR[19]) { switch (NameR[19]) {
default: break; default: break;
case 'c': // 1 string to match. case 'c': // 1 string to match.
if (NameR[20] != 'c') if (NameR[20] != 'c')
break; break;
return Intrinsic::hexagon_S2_asr_i_r_acc; // "exagon.S2.asr.i.r.acc" return Intrinsic::hexagon_S2_lsr_i_r_acc; // "exagon.S2.lsr.i.r.acc"
case 'n': // 1 string to match. case 'n': // 1 string to match.
if (NameR[20] != 'd') if (NameR[20] != 'd')
break; break;
return Intrinsic::hexagon_S2_asr_i_r_and; // "exagon.S2.asr.i.r.and" return Intrinsic::hexagon_S2_lsr_i_r_and; // "exagon.S2.lsr.i.r.and"
} }
break; break;
case 'n': // 1 string to match. case 'n': // 1 string to match.
if (NameR.substr(19, 2) != "ac") if (memcmp(NameR.data()+19, "ac", 2))
break; break;
return Intrinsic::hexagon_S2_asr_i_r_nac; // "exagon. return Intrinsic::hexagon_S2_lsr_i_r_nac; // "exagon.
S2.asr.i.r.nac" S2.lsr.i.r.nac"
case 'r': // 1 string to match.
if (NameR.substr(19, 2) != "nd")
break;
return Intrinsic::hexagon_S2_asr_i_r_rnd; // "exagon.
S2.asr.i.r.rnd"
} }
break; break;
} }
break; break;
case 'r': // 7 strings to match. case 'r': // 7 strings to match.
if (NameR[15] != '.') if (NameR[15] != '.')
break; break;
switch (NameR[16]) { switch (NameR[16]) {
default: break; default: break;
case 'p': // 3 strings to match. case 'p': // 4 strings to match.
if (NameR[17] != '.') if (NameR[17] != '.')
break; break;
switch (NameR[18]) { switch (NameR[18]) {
default: break; default: break;
case 'a': // 2 strings to match. case 'a': // 2 strings to match.
switch (NameR[19]) { switch (NameR[19]) {
default: break; default: break;
case 'c': // 1 string to match. case 'c': // 1 string to match.
if (NameR[20] != 'c') if (NameR[20] != 'c')
break; break;
return Intrinsic::hexagon_S2_asr_r_p_acc; // "exagon.S2.asr.r.p.acc" return Intrinsic::hexagon_S2_lsr_r_p_acc; // "exagon.S2.lsr.r.p.acc"
case 'n': // 1 string to match. case 'n': // 1 string to match.
if (NameR[20] != 'd') if (NameR[20] != 'd')
break; break;
return Intrinsic::hexagon_S2_asr_r_p_and; // "exagon.S2.asr.r.p.and" return Intrinsic::hexagon_S2_lsr_r_p_and; // "exagon.S2.lsr.r.p.and"
} }
break; break;
case 'n': // 1 string to match. case 'n': // 1 string to match.
if (NameR.substr(19, 2) != "ac") if (memcmp(NameR.data()+19, "ac", 2))
break; break;
return Intrinsic::hexagon_S2_asr_r_p_nac; // "exagon. return Intrinsic::hexagon_S2_lsr_r_p_nac; // "exagon.
S2.asr.r.p.nac" S2.lsr.r.p.nac"
case 'x': // 1 string to match.
if (memcmp(NameR.data()+19, "or", 2))
break;
return Intrinsic::hexagon_S2_lsr_r_p_xor; // "exagon.
S2.lsr.r.p.xor"
} }
break; break;
case 'r': // 4 strings to match. case 'r': // 3 strings to match.
if (NameR[17] != '.') if (NameR[17] != '.')
break; break;
switch (NameR[18]) { switch (NameR[18]) {
default: break; default: break;
case 'a': // 2 strings to match. case 'a': // 2 strings to match.
switch (NameR[19]) { switch (NameR[19]) {
default: break; default: break;
case 'c': // 1 string to match. case 'c': // 1 string to match.
if (NameR[20] != 'c') if (NameR[20] != 'c')
break; break;
return Intrinsic::hexagon_S2_asr_r_r_acc; // "exagon.S2.asr.r.r.acc" return Intrinsic::hexagon_S2_lsr_r_r_acc; // "exagon.S2.lsr.r.r.acc"
case 'n': // 1 string to match. case 'n': // 1 string to match.
if (NameR[20] != 'd') if (NameR[20] != 'd')
break; break;
return Intrinsic::hexagon_S2_asr_r_r_and; // "exagon.S2.asr.r.r.and" return Intrinsic::hexagon_S2_lsr_r_r_and; // "exagon.S2.lsr.r.r.and"
} }
break; break;
case 'n': // 1 string to match. case 'n': // 1 string to match.
if (NameR.substr(19, 2) != "ac") if (memcmp(NameR.data()+19, "ac", 2))
break;
return Intrinsic::hexagon_S2_asr_r_r_nac; // "exagon.
S2.asr.r.r.nac"
case 's': // 1 string to match.
if (NameR.substr(19, 2) != "at")
break; break;
return Intrinsic::hexagon_S2_asr_r_r_sat; // "exagon. S2.asr.r.r.sat" return Intrinsic::hexagon_S2_lsr_r_r_nac; // "exagon. S2.lsr.r.r.nac"
} }
break; break;
} }
break; break;
} }
break; break;
} }
break; break;
case 't': // 2 strings to match.
if (memcmp(NameR.data()+11, "ogglebit.", 9))
break;
switch (NameR[20]) {
default: break;
case 'i': // 1 string to match.
return Intrinsic::hexagon_S2_togglebit_i; // "exagon.
S2.togglebit.i"
case 'r': // 1 string to match.
return Intrinsic::hexagon_S2_togglebit_r; // "exagon.
S2.togglebit.r"
}
break;
case 'v': // 1 string to match.
if (memcmp(NameR.data()+11, "rndpackwhs", 10))
break;
return Intrinsic::hexagon_S2_vrndpackwhs; // "exagon.S2.vrndp
ackwhs"
} }
break; break;
case 'e': // 1 string to match. case '4': // 7 strings to match.
if (NameR.substr(11, 10) != "xtractu.rp") if (NameR[9] != '.')
break;
return Intrinsic::hexagon_S2_extractu_rp; // "exagon.S2.extra
ctu.rp"
case 'l': // 18 strings to match.
if (NameR[11] != 's')
break; break;
switch (NameR[12]) { switch (NameR[10]) {
default: break; default: break;
case 'l': // 6 strings to match. case 'a': // 4 strings to match.
if (NameR.substr(13, 3) != ".r.") switch (NameR[11]) {
break;
switch (NameR[16]) {
default: break; default: break;
case 'p': // 3 strings to match. case 'd': // 2 strings to match.
if (NameR[17] != '.') if (memcmp(NameR.data()+12, "di.", 3))
break; break;
switch (NameR[18]) { switch (NameR[15]) {
default: break; default: break;
case 'a': // 2 strings to match. case 'a': // 1 string to match.
switch (NameR[19]) { if (memcmp(NameR.data()+16, "sl.ri", 5))
default: break; break;
case 'c': // 1 string to match. return Intrinsic::hexagon_S4_addi_asl_ri; // "exagon.
if (NameR[20] != 'c') S4.addi.asl.ri"
break; case 'l': // 1 string to match.
return Intrinsic::hexagon_S2_lsl_r_p_acc; // "exagon. if (memcmp(NameR.data()+16, "sr.ri", 5))
S2.lsl.r.p.acc"
case 'n': // 1 string to match.
if (NameR[20] != 'd')
break;
return Intrinsic::hexagon_S2_lsl_r_p_and; // "exagon.
S2.lsl.r.p.and"
}
break;
case 'n': // 1 string to match.
if (NameR.substr(19, 2) != "ac")
break; break;
return Intrinsic::hexagon_S2_lsl_r_p_nac; // "exagon. S2.lsl.r.p.nac" return Intrinsic::hexagon_S4_addi_lsr_ri; // "exagon. S4.addi.lsr.ri"
} }
break; break;
case 'r': // 3 strings to match. case 'n': // 2 strings to match.
if (NameR[17] != '.') if (memcmp(NameR.data()+12, "di.", 3))
break; break;
switch (NameR[18]) { switch (NameR[15]) {
default: break; default: break;
case 'a': // 2 strings to match. case 'a': // 1 string to match.
switch (NameR[19]) { if (memcmp(NameR.data()+16, "sl.ri", 5))
default: break;
case 'c': // 1 string to match.
if (NameR[20] != 'c')
break;
return Intrinsic::hexagon_S2_lsl_r_r_acc; // "exagon.
S2.lsl.r.r.acc"
case 'n': // 1 string to match.
if (NameR[20] != 'd')
break;
return Intrinsic::hexagon_S2_lsl_r_r_and; // "exagon.
S2.lsl.r.r.and"
}
break;
case 'n': // 1 string to match.
if (NameR.substr(19, 2) != "ac")
break; break;
return Intrinsic::hexagon_S2_lsl_r_r_nac; // "exagon. return Intrinsic::hexagon_S4_andi_asl_ri; // "exagon.
S2.lsl.r.r.nac" S4.andi.asl.ri"
case 'l': // 1 string to match.
if (memcmp(NameR.data()+16, "sr.ri", 5))
break;
return Intrinsic::hexagon_S4_andi_lsr_ri; // "exagon.
S4.andi.lsr.ri"
} }
break; break;
} }
break; break;
case 'r': // 12 strings to match. case 'e': // 1 string to match.
if (NameR[13] != '.') if (memcmp(NameR.data()+11, "xtractp.rp", 10))
break; break;
switch (NameR[14]) { return Intrinsic::hexagon_S4_extractp_rp; // "exagon.S4.extra
ctp.rp"
case 's': // 2 strings to match.
if (memcmp(NameR.data()+11, "ubi.", 4))
break;
switch (NameR[15]) {
default: break; default: break;
case 'i': // 6 strings to match. case 'a': // 1 string to match.
if (NameR[15] != '.') if (memcmp(NameR.data()+16, "sl.ri", 5))
break; break;
switch (NameR[16]) { return Intrinsic::hexagon_S4_subi_asl_ri; // "exagon.
default: break; S4.subi.asl.ri"
case 'p': // 3 strings to match. case 'l': // 1 string to match.
if (NameR[17] != '.') if (memcmp(NameR.data()+16, "sr.ri", 5))
break;
switch (NameR[18]) {
default: break;
case 'a': // 2 strings to match.
switch (NameR[19]) {
default: break;
case 'c': // 1 string to match.
if (NameR[20] != 'c')
break;
return Intrinsic::hexagon_S2_lsr_i_p_acc; // "exagon.
S2.lsr.i.p.acc"
case 'n': // 1 string to match.
if (NameR[20] != 'd')
break;
return Intrinsic::hexagon_S2_lsr_i_p_and; // "exagon.
S2.lsr.i.p.and"
}
break;
case 'n': // 1 string to match.
if (NameR.substr(19, 2) != "ac")
break;
return Intrinsic::hexagon_S2_lsr_i_p_nac; // "exagon.
S2.lsr.i.p.nac"
}
break;
case 'r': // 3 strings to match.
if (NameR[17] != '.')
break;
switch (NameR[18]) {
default: break;
case 'a': // 2 strings to match.
switch (NameR[19]) {
default: break;
case 'c': // 1 string to match.
if (NameR[20] != 'c')
break;
return Intrinsic::hexagon_S2_lsr_i_r_acc; // "exagon.
S2.lsr.i.r.acc"
case 'n': // 1 string to match.
if (NameR[20] != 'd')
break;
return Intrinsic::hexagon_S2_lsr_i_r_and; // "exagon.
S2.lsr.i.r.and"
}
break;
case 'n': // 1 string to match.
if (NameR.substr(19, 2) != "ac")
break;
return Intrinsic::hexagon_S2_lsr_i_r_nac; // "exagon.
S2.lsr.i.r.nac"
}
break;
}
break;
case 'r': // 6 strings to match.
if (NameR[15] != '.')
break;
switch (NameR[16]) {
default: break;
case 'p': // 3 strings to match.
if (NameR[17] != '.')
break;
switch (NameR[18]) {
default: break;
case 'a': // 2 strings to match.
switch (NameR[19]) {
default: break;
case 'c': // 1 string to match.
if (NameR[20] != 'c')
break;
return Intrinsic::hexagon_S2_lsr_r_p_acc; // "exagon.
S2.lsr.r.p.acc"
case 'n': // 1 string to match.
if (NameR[20] != 'd')
break;
return Intrinsic::hexagon_S2_lsr_r_p_and; // "exagon.
S2.lsr.r.p.and"
}
break;
case 'n': // 1 string to match.
if (NameR.substr(19, 2) != "ac")
break;
return Intrinsic::hexagon_S2_lsr_r_p_nac; // "exagon.
S2.lsr.r.p.nac"
}
break;
case 'r': // 3 strings to match.
if (NameR[17] != '.')
break;
switch (NameR[18]) {
default: break;
case 'a': // 2 strings to match.
switch (NameR[19]) {
default: break;
case 'c': // 1 string to match.
if (NameR[20] != 'c')
break;
return Intrinsic::hexagon_S2_lsr_r_r_acc; // "exagon.
S2.lsr.r.r.acc"
case 'n': // 1 string to match.
if (NameR[20] != 'd')
break;
return Intrinsic::hexagon_S2_lsr_r_r_and; // "exagon.
S2.lsr.r.r.and"
}
break;
case 'n': // 1 string to match.
if (NameR.substr(19, 2) != "ac")
break;
return Intrinsic::hexagon_S2_lsr_r_r_nac; // "exagon.
S2.lsr.r.r.nac"
}
break; break;
} return Intrinsic::hexagon_S4_subi_lsr_ri; // "exagon.
break; S4.subi.lsr.ri"
} }
break; break;
} }
break; break;
case 't': // 2 strings to match.
if (NameR.substr(11, 9) != "ogglebit.")
break;
switch (NameR[20]) {
default: break;
case 'i': // 1 string to match.
return Intrinsic::hexagon_S2_togglebit_i; // "exagon.S2.toggl
ebit.i"
case 'r': // 1 string to match.
return Intrinsic::hexagon_S2_togglebit_r; // "exagon.S2.toggl
ebit.r"
}
break;
case 'v': // 1 string to match.
if (NameR.substr(11, 10) != "rndpackwhs")
break;
return Intrinsic::hexagon_S2_vrndpackwhs; // "exagon.S2.vrndp
ackwhs"
} }
break; break;
} }
break; break;
case 22: // 9 strings to match. case 22: // 9 strings to match.
if (NameR.substr(0, 7) != "exagon.") if (memcmp(NameR.data()+0, "exagon.", 7))
break; break;
switch (NameR[7]) { switch (NameR[7]) {
default: break; default: break;
case 'A': // 2 strings to match. case 'A': // 2 strings to match.
if (NameR.substr(8, 9) != "4.round.r") if (memcmp(NameR.data()+8, "4.round.r", 9))
break; break;
switch (NameR[17]) { switch (NameR[17]) {
default: break; default: break;
case 'i': // 1 string to match. case 'i': // 1 string to match.
if (NameR.substr(18, 4) != ".sat") if (memcmp(NameR.data()+18, ".sat", 4))
break; break;
return Intrinsic::hexagon_A4_round_ri_sat; // "exagon.A4.round .ri.sat" return Intrinsic::hexagon_A4_round_ri_sat; // "exagon.A4.round .ri.sat"
case 'r': // 1 string to match. case 'r': // 1 string to match.
if (NameR.substr(18, 4) != ".sat") if (memcmp(NameR.data()+18, ".sat", 4))
break; break;
return Intrinsic::hexagon_A4_round_rr_sat; // "exagon.A4.round .rr.sat" return Intrinsic::hexagon_A4_round_rr_sat; // "exagon.A4.round .rr.sat"
} }
break; break;
case 'M': // 1 string to match. case 'M': // 1 string to match.
if (NameR.substr(8, 14) != "2.vrcmpys.s1rp") if (memcmp(NameR.data()+8, "2.vrcmpys.s1rp", 14))
break; break;
return Intrinsic::hexagon_M2_vrcmpys_s1rp; // "exagon.M2.vrcmp ys.s1rp" return Intrinsic::hexagon_M2_vrcmpys_s1rp; // "exagon.M2.vrcmp ys.s1rp"
case 'S': // 6 strings to match. case 'S': // 6 strings to match.
if (NameR.substr(8, 2) != "2.") if (memcmp(NameR.data()+8, "2.", 2))
break; break;
switch (NameR[10]) { switch (NameR[10]) {
default: break; default: break;
case 'a': // 2 strings to match. case 'a': // 2 strings to match.
if (NameR.substr(11, 5) != "sl.i.") if (memcmp(NameR.data()+11, "sl.i.", 5))
break; break;
switch (NameR[16]) { switch (NameR[16]) {
default: break; default: break;
case 'p': // 1 string to match. case 'p': // 1 string to match.
if (NameR.substr(17, 5) != ".xacc") if (memcmp(NameR.data()+17, ".xacc", 5))
break; break;
return Intrinsic::hexagon_S2_asl_i_p_xacc; // "exagon.S2.asl.i .p.xacc" return Intrinsic::hexagon_S2_asl_i_p_xacc; // "exagon.S2.asl.i .p.xacc"
case 'r': // 1 string to match. case 'r': // 1 string to match.
if (NameR.substr(17, 5) != ".xacc") if (memcmp(NameR.data()+17, ".xacc", 5))
break; break;
return Intrinsic::hexagon_S2_asl_i_r_xacc; // "exagon.S2.asl.i .r.xacc" return Intrinsic::hexagon_S2_asl_i_r_xacc; // "exagon.S2.asl.i .r.xacc"
} }
break; break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
if (NameR.substr(11, 11) != "einterleave") if (memcmp(NameR.data()+11, "einterleave", 11))
break; break;
return Intrinsic::hexagon_S2_deinterleave; // "exagon.S2.deint erleave" return Intrinsic::hexagon_S2_deinterleave; // "exagon.S2.deint erleave"
case 'e': // 1 string to match. case 'e': // 1 string to match.
if (NameR.substr(11, 11) != "xtractup.rp") if (memcmp(NameR.data()+11, "xtractup.rp", 11))
break; break;
return Intrinsic::hexagon_S2_extractup_rp; // "exagon.S2.extra ctup.rp" return Intrinsic::hexagon_S2_extractup_rp; // "exagon.S2.extra ctup.rp"
case 'l': // 2 strings to match. case 'l': // 2 strings to match.
if (NameR.substr(11, 5) != "sr.i.") if (memcmp(NameR.data()+11, "sr.i.", 5))
break; break;
switch (NameR[16]) { switch (NameR[16]) {
default: break; default: break;
case 'p': // 1 string to match. case 'p': // 1 string to match.
if (NameR.substr(17, 5) != ".xacc") if (memcmp(NameR.data()+17, ".xacc", 5))
break; break;
return Intrinsic::hexagon_S2_lsr_i_p_xacc; // "exagon.S2.lsr.i .p.xacc" return Intrinsic::hexagon_S2_lsr_i_p_xacc; // "exagon.S2.lsr.i .p.xacc"
case 'r': // 1 string to match. case 'r': // 1 string to match.
if (NameR.substr(17, 5) != ".xacc") if (memcmp(NameR.data()+17, ".xacc", 5))
break; break;
return Intrinsic::hexagon_S2_lsr_i_r_xacc; // "exagon.S2.lsr.i .r.xacc" return Intrinsic::hexagon_S2_lsr_i_r_xacc; // "exagon.S2.lsr.i .r.xacc"
} }
break; break;
} }
break; break;
} }
break; break;
case 23: // 37 strings to match. case 23: // 42 strings to match.
if (NameR.substr(0, 7) != "exagon.") if (memcmp(NameR.data()+0, "exagon.", 7))
break; break;
switch (NameR[7]) { switch (NameR[7]) {
default: break; default: break;
case 'M': // 34 strings to match. case 'M': // 38 strings to match.
if (NameR.substr(8, 2) != "2.") switch (NameR[8]) {
break;
switch (NameR[10]) {
default: break; default: break;
case 'm': // 32 strings to match. case '2': // 35 strings to match.
if (NameR.substr(11, 3) != "py.") if (NameR[9] != '.')
break; break;
switch (NameR[14]) { switch (NameR[10]) {
default: break; default: break;
case 'a': // 8 strings to match. case 'm': // 33 strings to match.
if (NameR.substr(15, 3) != "cc.") if (memcmp(NameR.data()+11, "py.", 3))
break; break;
switch (NameR[18]) { switch (NameR[14]) {
default: break; default: break;
case 'h': // 4 strings to match. case 'a': // 8 strings to match.
switch (NameR[19]) { if (memcmp(NameR.data()+15, "cc.", 3))
break;
switch (NameR[18]) {
default: break; default: break;
case 'h': // 2 strings to match. case 'h': // 4 strings to match.
if (NameR.substr(20, 2) != ".s") switch (NameR[19]) {
break;
switch (NameR[22]) {
default: break; default: break;
case '0': // 1 string to match. case 'h': // 2 strings to match.
return Intrinsic::hexagon_M2_mpy_acc_hh_s0; // "exagon. if (memcmp(NameR.data()+20, ".s", 2))
M2.mpy.acc.hh.s0" break;
case '1': // 1 string to match. switch (NameR[22]) {
return Intrinsic::hexagon_M2_mpy_acc_hh_s1; // "exagon. default: break;
M2.mpy.acc.hh.s1" case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_acc_hh_s0; //
"exagon.M2.mpy.acc.hh.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_acc_hh_s1; //
"exagon.M2.mpy.acc.hh.s1"
}
break;
case 'l': // 2 strings to match.
if (memcmp(NameR.data()+20, ".s", 2))
break;
switch (NameR[22]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_acc_hl_s0; //
"exagon.M2.mpy.acc.hl.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_acc_hl_s1; //
"exagon.M2.mpy.acc.hl.s1"
}
break;
} }
break; break;
case 'l': // 2 strings to match. case 'l': // 4 strings to match.
if (NameR.substr(20, 2) != ".s") switch (NameR[19]) {
break;
switch (NameR[22]) {
default: break; default: break;
case '0': // 1 string to match. case 'h': // 2 strings to match.
return Intrinsic::hexagon_M2_mpy_acc_hl_s0; // "exagon. if (memcmp(NameR.data()+20, ".s", 2))
M2.mpy.acc.hl.s0" break;
case '1': // 1 string to match. switch (NameR[22]) {
return Intrinsic::hexagon_M2_mpy_acc_hl_s1; // "exagon. default: break;
M2.mpy.acc.hl.s1" case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_acc_lh_s0; //
"exagon.M2.mpy.acc.lh.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_acc_lh_s1; //
"exagon.M2.mpy.acc.lh.s1"
}
break;
case 'l': // 2 strings to match.
if (memcmp(NameR.data()+20, ".s", 2))
break;
switch (NameR[22]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_acc_ll_s0; //
"exagon.M2.mpy.acc.ll.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_acc_ll_s1; //
"exagon.M2.mpy.acc.ll.s1"
}
break;
} }
break; break;
} }
break; break;
case 'l': // 4 strings to match. case 'n': // 8 strings to match.
switch (NameR[19]) { if (memcmp(NameR.data()+15, "ac.", 3))
break;
switch (NameR[18]) {
default: break; default: break;
case 'h': // 2 strings to match. case 'h': // 4 strings to match.
if (NameR.substr(20, 2) != ".s") switch (NameR[19]) {
break;
switch (NameR[22]) {
default: break; default: break;
case '0': // 1 string to match. case 'h': // 2 strings to match.
return Intrinsic::hexagon_M2_mpy_acc_lh_s0; // "exagon. if (memcmp(NameR.data()+20, ".s", 2))
M2.mpy.acc.lh.s0" break;
case '1': // 1 string to match. switch (NameR[22]) {
return Intrinsic::hexagon_M2_mpy_acc_lh_s1; // "exagon. default: break;
M2.mpy.acc.lh.s1" case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_nac_hh_s0; //
"exagon.M2.mpy.nac.hh.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_nac_hh_s1; //
"exagon.M2.mpy.nac.hh.s1"
}
break;
case 'l': // 2 strings to match.
if (memcmp(NameR.data()+20, ".s", 2))
break;
switch (NameR[22]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_nac_hl_s0; //
"exagon.M2.mpy.nac.hl.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_nac_hl_s1; //
"exagon.M2.mpy.nac.hl.s1"
}
break;
} }
break; break;
case 'l': // 2 strings to match. case 'l': // 4 strings to match.
if (NameR.substr(20, 2) != ".s") switch (NameR[19]) {
break;
switch (NameR[22]) {
default: break; default: break;
case '0': // 1 string to match. case 'h': // 2 strings to match.
return Intrinsic::hexagon_M2_mpy_acc_ll_s0; // "exagon. if (memcmp(NameR.data()+20, ".s", 2))
M2.mpy.acc.ll.s0" break;
case '1': // 1 string to match. switch (NameR[22]) {
return Intrinsic::hexagon_M2_mpy_acc_ll_s1; // "exagon. default: break;
M2.mpy.acc.ll.s1" case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_nac_lh_s0; //
"exagon.M2.mpy.nac.lh.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_nac_lh_s1; //
"exagon.M2.mpy.nac.lh.s1"
}
break;
case 'l': // 2 strings to match.
if (memcmp(NameR.data()+20, ".s", 2))
break;
switch (NameR[22]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_nac_ll_s0; //
"exagon.M2.mpy.nac.ll.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_nac_ll_s1; //
"exagon.M2.mpy.nac.ll.s1"
}
break;
} }
break; break;
} }
break; break;
} case 'r': // 8 strings to match.
break; if (memcmp(NameR.data()+15, "nd.", 3))
case 'n': // 8 strings to match. break;
if (NameR.substr(15, 3) != "ac.") switch (NameR[18]) {
break;
switch (NameR[18]) {
default: break;
case 'h': // 4 strings to match.
switch (NameR[19]) {
default: break; default: break;
case 'h': // 2 strings to match. case 'h': // 4 strings to match.
if (NameR.substr(20, 2) != ".s") switch (NameR[19]) {
break;
switch (NameR[22]) {
default: break; default: break;
case '0': // 1 string to match. case 'h': // 2 strings to match.
return Intrinsic::hexagon_M2_mpy_nac_hh_s0; // "exagon. if (memcmp(NameR.data()+20, ".s", 2))
M2.mpy.nac.hh.s0" break;
case '1': // 1 string to match. switch (NameR[22]) {
return Intrinsic::hexagon_M2_mpy_nac_hh_s1; // "exagon. default: break;
M2.mpy.nac.hh.s1" case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_rnd_hh_s0; //
"exagon.M2.mpy.rnd.hh.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_rnd_hh_s1; //
"exagon.M2.mpy.rnd.hh.s1"
}
break;
case 'l': // 2 strings to match.
if (memcmp(NameR.data()+20, ".s", 2))
break;
switch (NameR[22]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_rnd_hl_s0; //
"exagon.M2.mpy.rnd.hl.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_rnd_hl_s1; //
"exagon.M2.mpy.rnd.hl.s1"
}
break;
} }
break; break;
case 'l': // 2 strings to match. case 'l': // 4 strings to match.
if (NameR.substr(20, 2) != ".s") switch (NameR[19]) {
break;
switch (NameR[22]) {
default: break; default: break;
case '0': // 1 string to match. case 'h': // 2 strings to match.
return Intrinsic::hexagon_M2_mpy_nac_hl_s0; // "exagon. if (memcmp(NameR.data()+20, ".s", 2))
M2.mpy.nac.hl.s0" break;
case '1': // 1 string to match. switch (NameR[22]) {
return Intrinsic::hexagon_M2_mpy_nac_hl_s1; // "exagon. default: break;
M2.mpy.nac.hl.s1" case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_rnd_lh_s0; //
"exagon.M2.mpy.rnd.lh.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_rnd_lh_s1; //
"exagon.M2.mpy.rnd.lh.s1"
}
break;
case 'l': // 2 strings to match.
if (memcmp(NameR.data()+20, ".s", 2))
break;
switch (NameR[22]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_rnd_ll_s0; //
"exagon.M2.mpy.rnd.ll.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_rnd_ll_s1; //
"exagon.M2.mpy.rnd.ll.s1"
}
break;
} }
break; break;
} }
break; break;
case 'l': // 4 strings to match. case 's': // 8 strings to match.
switch (NameR[19]) { if (memcmp(NameR.data()+15, "at.", 3))
break;
switch (NameR[18]) {
default: break; default: break;
case 'h': // 2 strings to match. case 'h': // 4 strings to match.
if (NameR.substr(20, 2) != ".s") switch (NameR[19]) {
break;
switch (NameR[22]) {
default: break; default: break;
case '0': // 1 string to match. case 'h': // 2 strings to match.
return Intrinsic::hexagon_M2_mpy_nac_lh_s0; // "exagon. if (memcmp(NameR.data()+20, ".s", 2))
M2.mpy.nac.lh.s0" break;
case '1': // 1 string to match. switch (NameR[22]) {
return Intrinsic::hexagon_M2_mpy_nac_lh_s1; // "exagon. default: break;
M2.mpy.nac.lh.s1" case '0': // 1 string to match.
} return Intrinsic::hexagon_M2_mpy_sat_hh_s0; //
break; "exagon.M2.mpy.sat.hh.s0"
case 'l': // 2 strings to match. case '1': // 1 string to match.
if (NameR.substr(20, 2) != ".s") return Intrinsic::hexagon_M2_mpy_sat_hh_s1; //
"exagon.M2.mpy.sat.hh.s1"
}
break; break;
switch (NameR[22]) { case 'l': // 2 strings to match.
default: break; if (memcmp(NameR.data()+20, ".s", 2))
case '0': // 1 string to match. break;
return Intrinsic::hexagon_M2_mpy_nac_ll_s0; // "exagon. switch (NameR[22]) {
M2.mpy.nac.ll.s0" default: break;
case '1': // 1 string to match. case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_nac_ll_s1; // "exagon. return Intrinsic::hexagon_M2_mpy_sat_hl_s0; //
M2.mpy.nac.ll.s1" "exagon.M2.mpy.sat.hl.s0"
} case '1': // 1 string to match.
break; return Intrinsic::hexagon_M2_mpy_sat_hl_s1; //
} "exagon.M2.mpy.sat.hl.s1"
break; }
}
break;
case 'r': // 8 strings to match.
if (NameR.substr(15, 3) != "nd.")
break;
switch (NameR[18]) {
default: break;
case 'h': // 4 strings to match.
switch (NameR[19]) {
default: break;
case 'h': // 2 strings to match.
if (NameR.substr(20, 2) != ".s")
break; break;
switch (NameR[22]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_rnd_hh_s0; // "exagon.
M2.mpy.rnd.hh.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_rnd_hh_s1; // "exagon.
M2.mpy.rnd.hh.s1"
} }
break; break;
case 'l': // 2 strings to match. case 'l': // 4 strings to match.
if (NameR.substr(20, 2) != ".s") switch (NameR[19]) {
break;
switch (NameR[22]) {
default: break; default: break;
case '0': // 1 string to match. case 'h': // 2 strings to match.
return Intrinsic::hexagon_M2_mpy_rnd_hl_s0; // "exagon. if (memcmp(NameR.data()+20, ".s", 2))
M2.mpy.rnd.hl.s0" break;
case '1': // 1 string to match. switch (NameR[22]) {
return Intrinsic::hexagon_M2_mpy_rnd_hl_s1; // "exagon. default: break;
M2.mpy.rnd.hl.s1" case '0': // 1 string to match.
} return Intrinsic::hexagon_M2_mpy_sat_lh_s0; //
break; "exagon.M2.mpy.sat.lh.s0"
} case '1': // 1 string to match.
break; return Intrinsic::hexagon_M2_mpy_sat_lh_s1; //
case 'l': // 4 strings to match. "exagon.M2.mpy.sat.lh.s1"
switch (NameR[19]) { }
default: break;
case 'h': // 2 strings to match.
if (NameR.substr(20, 2) != ".s")
break; break;
switch (NameR[22]) { case 'l': // 2 strings to match.
default: break; if (memcmp(NameR.data()+20, ".s", 2))
case '0': // 1 string to match. break;
return Intrinsic::hexagon_M2_mpy_rnd_lh_s0; // "exagon. switch (NameR[22]) {
M2.mpy.rnd.lh.s0" default: break;
case '1': // 1 string to match. case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_rnd_lh_s1; // "exagon. return Intrinsic::hexagon_M2_mpy_sat_ll_s0; //
M2.mpy.rnd.lh.s1" "exagon.M2.mpy.sat.ll.s0"
} case '1': // 1 string to match.
break; return Intrinsic::hexagon_M2_mpy_sat_ll_s1; //
case 'l': // 2 strings to match. "exagon.M2.mpy.sat.ll.s1"
if (NameR.substr(20, 2) != ".s") }
break; break;
switch (NameR[22]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_rnd_ll_s0; // "exagon.
M2.mpy.rnd.ll.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_rnd_ll_s1; // "exagon.
M2.mpy.rnd.ll.s1"
} }
break; break;
} }
break; break;
case 'u': // 1 string to match.
if (memcmp(NameR.data()+15, "p.s1.sat", 8))
break;
return Intrinsic::hexagon_M2_mpy_up_s1_sat; // "exagon.
M2.mpy.up.s1.sat"
} }
break; break;
case 's': // 8 strings to match. case 'v': // 2 strings to match.
if (NameR.substr(15, 3) != "at.") if (memcmp(NameR.data()+11, "mpy2s.s", 7))
break; break;
switch (NameR[18]) { switch (NameR[18]) {
default: break; default: break;
case 'h': // 4 strings to match. case '0': // 1 string to match.
switch (NameR[19]) { if (memcmp(NameR.data()+19, "pack", 4))
default: break;
case 'h': // 2 strings to match.
if (NameR.substr(20, 2) != ".s")
break;
switch (NameR[22]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_sat_hh_s0; // "exagon.
M2.mpy.sat.hh.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_sat_hh_s1; // "exagon.
M2.mpy.sat.hh.s1"
}
break;
case 'l': // 2 strings to match.
if (NameR.substr(20, 2) != ".s")
break;
switch (NameR[22]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_sat_hl_s0; // "exagon.
M2.mpy.sat.hl.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_sat_hl_s1; // "exagon.
M2.mpy.sat.hl.s1"
}
break;
}
break;
case 'l': // 4 strings to match.
switch (NameR[19]) {
default: break;
case 'h': // 2 strings to match.
if (NameR.substr(20, 2) != ".s")
break;
switch (NameR[22]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_sat_lh_s0; // "exagon.
M2.mpy.sat.lh.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_sat_lh_s1; // "exagon.
M2.mpy.sat.lh.s1"
}
break; break;
case 'l': // 2 strings to match. return Intrinsic::hexagon_M2_vmpy2s_s0pack; // "exagon.
if (NameR.substr(20, 2) != ".s") M2.vmpy2s.s0pack"
break; case '1': // 1 string to match.
switch (NameR[22]) { if (memcmp(NameR.data()+19, "pack", 4))
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_sat_ll_s0; // "exagon.
M2.mpy.sat.ll.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_sat_ll_s1; // "exagon.
M2.mpy.sat.ll.s1"
}
break; break;
} return Intrinsic::hexagon_M2_vmpy2s_s1pack; // "exagon.
break; M2.vmpy2s.s1pack"
} }
break; break;
} }
break; break;
case 'v': // 2 strings to match. case '4': // 3 strings to match.
if (NameR.substr(11, 7) != "mpy2s.s") if (NameR[9] != '.')
break; break;
switch (NameR[18]) { switch (NameR[10]) {
default: break; default: break;
case '0': // 1 string to match. case 'm': // 2 strings to match.
if (NameR.substr(19, 4) != "pack") switch (NameR[11]) {
break; default: break;
return Intrinsic::hexagon_M2_vmpy2s_s0pack; // "exagon. case 'a': // 1 string to match.
M2.vmpy2s.s0pack" if (memcmp(NameR.data()+12, "c.up.s1.sat", 11))
case '1': // 1 string to match. break;
if (NameR.substr(19, 4) != "pack") return Intrinsic::hexagon_M4_mac_up_s1_sat; // "exagon.
M4.mac.up.s1.sat"
case 'p': // 1 string to match.
if (memcmp(NameR.data()+12, "yri.addr.u2", 11))
break;
return Intrinsic::hexagon_M4_mpyri_addr_u2; // "exagon.
M4.mpyri.addr.u2"
}
break;
case 'n': // 1 string to match.
if (memcmp(NameR.data()+11, "ac.up.s1.sat", 12))
break; break;
return Intrinsic::hexagon_M2_vmpy2s_s1pack; // "exagon. M2.vmpy2s.s1pack" return Intrinsic::hexagon_M4_nac_up_s1_sat; // "exagon. M4.nac.up.s1.sat"
} }
break; break;
} }
break; break;
case 'S': // 3 strings to match. case 'S': // 4 strings to match.
switch (NameR[8]) { switch (NameR[8]) {
default: break; default: break;
case '2': // 2 strings to match. case '2': // 2 strings to match.
if (NameR.substr(9, 5) != ".vsat") if (memcmp(NameR.data()+9, ".vsat", 5))
break; break;
switch (NameR[14]) { switch (NameR[14]) {
default: break; default: break;
case 'h': // 1 string to match. case 'h': // 1 string to match.
if (NameR.substr(15, 8) != "b.nopack") if (memcmp(NameR.data()+15, "b.nopack", 8))
break; break;
return Intrinsic::hexagon_S2_vsathb_nopack; // "exagon. S2.vsathb.nopack" return Intrinsic::hexagon_S2_vsathb_nopack; // "exagon. S2.vsathb.nopack"
case 'w': // 1 string to match. case 'w': // 1 string to match.
if (NameR.substr(15, 8) != "h.nopack") if (memcmp(NameR.data()+15, "h.nopack", 8))
break; break;
return Intrinsic::hexagon_S2_vsatwh_nopack; // "exagon. S2.vsatwh.nopack" return Intrinsic::hexagon_S2_vsatwh_nopack; // "exagon. S2.vsatwh.nopack"
} }
break; break;
case '4': // 1 string to match.
if (memcmp(NameR.data()+9, ".vrcrotate.acc", 14))
break;
return Intrinsic::hexagon_S4_vrcrotate_acc; // "exagon.S4.vrcro
tate.acc"
case 'I': // 1 string to match. case 'I': // 1 string to match.
if (NameR.substr(9, 14) != ".to.SXTHI.asrh") if (memcmp(NameR.data()+9, ".to.SXTHI.asrh", 14))
break; break;
return Intrinsic::hexagon_SI_to_SXTHI_asrh; // "exagon.SI.to.SX THI.asrh" return Intrinsic::hexagon_SI_to_SXTHI_asrh; // "exagon.SI.to.SX THI.asrh"
} }
break; break;
} }
break; break;
case 24: // 56 strings to match. case 24: // 64 strings to match.
if (NameR.substr(0, 7) != "exagon.") if (memcmp(NameR.data()+0, "exagon.", 7))
break; break;
switch (NameR[7]) { switch (NameR[7]) {
default: break; default: break;
case 'M': // 52 strings to match. case 'F': // 4 strings to match.
if (NameR.substr(8, 2) != "2.") if (memcmp(NameR.data()+8, "2.conv.", 7))
break; break;
switch (NameR[10]) { switch (NameR[15]) {
default: break; default: break;
case 'd': // 5 strings to match. case 'd': // 2 strings to match.
if (NameR.substr(11, 4) != "pmpy") if (memcmp(NameR.data()+16, "f2", 2))
break; break;
switch (NameR[15]) { switch (NameR[18]) {
default: break; default: break;
case 's': // 3 strings to match. case 'd': // 1 string to match.
if (NameR.substr(16, 2) != "s.") if (memcmp(NameR.data()+19, ".chop", 5))
break; break;
switch (NameR[18]) { return Intrinsic::hexagon_F2_conv_df2d_chop; // "exagon.
default: break; F2.conv.df2d.chop"
case 'a': // 1 string to match. case 'w': // 1 string to match.
if (NameR.substr(19, 5) != "cc.s0") if (memcmp(NameR.data()+19, ".chop", 5))
break;
return Intrinsic::hexagon_M2_dpmpyss_acc_s0; // "exagon.
M2.dpmpyss.acc.s0"
case 'n': // 1 string to match.
if (NameR.substr(19, 5) != "ac.s0")
break;
return Intrinsic::hexagon_M2_dpmpyss_nac_s0; // "exagon.
M2.dpmpyss.nac.s0"
case 'r': // 1 string to match.
if (NameR.substr(19, 5) != "nd.s0")
break;
return Intrinsic::hexagon_M2_dpmpyss_rnd_s0; // "exagon.
M2.dpmpyss.rnd.s0"
}
break;
case 'u': // 2 strings to match.
if (NameR.substr(16, 2) != "u.")
break; break;
switch (NameR[18]) { return Intrinsic::hexagon_F2_conv_df2w_chop; // "exagon.
default: break; F2.conv.df2w.chop"
case 'a': // 1 string to match. }
if (NameR.substr(19, 5) != "cc.s0") break;
break; case 's': // 2 strings to match.
return Intrinsic::hexagon_M2_dpmpyuu_acc_s0; // "exagon. if (memcmp(NameR.data()+16, "f2", 2))
M2.dpmpyuu.acc.s0"
case 'n': // 1 string to match.
if (NameR.substr(19, 5) != "ac.s0")
break;
return Intrinsic::hexagon_M2_dpmpyuu_nac_s0; // "exagon.
M2.dpmpyuu.nac.s0"
}
break; break;
switch (NameR[18]) {
default: break;
case 'd': // 1 string to match.
if (memcmp(NameR.data()+19, ".chop", 5))
break;
return Intrinsic::hexagon_F2_conv_sf2d_chop; // "exagon.
F2.conv.sf2d.chop"
case 'w': // 1 string to match.
if (memcmp(NameR.data()+19, ".chop", 5))
break;
return Intrinsic::hexagon_F2_conv_sf2w_chop; // "exagon.
F2.conv.sf2w.chop"
} }
break; break;
case 'm': // 40 strings to match. }
if (NameR.substr(11, 2) != "py") break;
case 'M': // 56 strings to match.
switch (NameR[8]) {
default: break;
case '2': // 52 strings to match.
if (NameR[9] != '.')
break; break;
switch (NameR[13]) { switch (NameR[10]) {
default: break; default: break;
case 'd': // 24 strings to match. case 'd': // 5 strings to match.
if (NameR[14] != '.') if (memcmp(NameR.data()+11, "pmpy", 4))
break; break;
switch (NameR[15]) { switch (NameR[15]) {
default: break; default: break;
case 'a': // 8 strings to match. case 's': // 3 strings to match.
if (NameR.substr(16, 3) != "cc.") if (memcmp(NameR.data()+16, "s.", 2))
break; break;
switch (NameR[19]) { switch (NameR[18]) {
default: break; default: break;
case 'h': // 4 strings to match. case 'a': // 1 string to match.
switch (NameR[20]) { if (memcmp(NameR.data()+19, "cc.s0", 5))
default: break;
case 'h': // 2 strings to match.
if (NameR.substr(21, 2) != ".s")
break;
switch (NameR[23]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_acc_hh_s0; //
"exagon.M2.mpyd.acc.hh.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_acc_hh_s1; //
"exagon.M2.mpyd.acc.hh.s1"
}
break; break;
case 'l': // 2 strings to match. return Intrinsic::hexagon_M2_dpmpyss_acc_s0; // "exagon.
if (NameR.substr(21, 2) != ".s") M2.dpmpyss.acc.s0"
break; case 'n': // 1 string to match.
switch (NameR[23]) { if (memcmp(NameR.data()+19, "ac.s0", 5))
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_acc_hl_s0; //
"exagon.M2.mpyd.acc.hl.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_acc_hl_s1; //
"exagon.M2.mpyd.acc.hl.s1"
}
break; break;
} return Intrinsic::hexagon_M2_dpmpyss_nac_s0; // "exagon.
M2.dpmpyss.nac.s0"
case 'r': // 1 string to match.
if (memcmp(NameR.data()+19, "nd.s0", 5))
break;
return Intrinsic::hexagon_M2_dpmpyss_rnd_s0; // "exagon.
M2.dpmpyss.rnd.s0"
}
break;
case 'u': // 2 strings to match.
if (memcmp(NameR.data()+16, "u.", 2))
break; break;
case 'l': // 4 strings to match. switch (NameR[18]) {
switch (NameR[20]) { default: break;
default: break; case 'a': // 1 string to match.
case 'h': // 2 strings to match. if (memcmp(NameR.data()+19, "cc.s0", 5))
if (NameR.substr(21, 2) != ".s")
break;
switch (NameR[23]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_acc_lh_s0; //
"exagon.M2.mpyd.acc.lh.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_acc_lh_s1; //
"exagon.M2.mpyd.acc.lh.s1"
}
break; break;
case 'l': // 2 strings to match. return Intrinsic::hexagon_M2_dpmpyuu_acc_s0; // "exagon.
if (NameR.substr(21, 2) != ".s") M2.dpmpyuu.acc.s0"
break; case 'n': // 1 string to match.
switch (NameR[23]) { if (memcmp(NameR.data()+19, "ac.s0", 5))
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_acc_ll_s0; //
"exagon.M2.mpyd.acc.ll.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_acc_ll_s1; //
"exagon.M2.mpyd.acc.ll.s1"
}
break; break;
} return Intrinsic::hexagon_M2_dpmpyuu_nac_s0; // "exagon.
break; M2.dpmpyuu.nac.s0"
} }
break; break;
case 'n': // 8 strings to match. }
if (NameR.substr(16, 3) != "ac.") break;
case 'm': // 40 strings to match.
if (memcmp(NameR.data()+11, "py", 2))
break;
switch (NameR[13]) {
default: break;
case 'd': // 24 strings to match.
if (NameR[14] != '.')
break; break;
switch (NameR[19]) { switch (NameR[15]) {
default: break; default: break;
case 'h': // 4 strings to match. case 'a': // 8 strings to match.
switch (NameR[20]) { if (memcmp(NameR.data()+16, "cc.", 3))
break;
switch (NameR[19]) {
default: break; default: break;
case 'h': // 2 strings to match. case 'h': // 4 strings to match.
if (NameR.substr(21, 2) != ".s") switch (NameR[20]) {
break;
switch (NameR[23]) {
default: break; default: break;
case '0': // 1 string to match. case 'h': // 2 strings to match.
return Intrinsic::hexagon_M2_mpyd_nac_hh_s0; // if (memcmp(NameR.data()+21, ".s", 2))
"exagon.M2.mpyd.nac.hh.s0" break;
case '1': // 1 string to match. switch (NameR[23]) {
return Intrinsic::hexagon_M2_mpyd_nac_hh_s1; // default: break;
"exagon.M2.mpyd.nac.hh.s1" case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_acc_hh_s0; //
"exagon.M2.mpyd.acc.hh.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_acc_hh_s1; //
"exagon.M2.mpyd.acc.hh.s1"
}
break;
case 'l': // 2 strings to match.
if (memcmp(NameR.data()+21, ".s", 2))
break;
switch (NameR[23]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_acc_hl_s0; //
"exagon.M2.mpyd.acc.hl.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_acc_hl_s1; //
"exagon.M2.mpyd.acc.hl.s1"
}
break;
} }
break; break;
case 'l': // 2 strings to match. case 'l': // 4 strings to match.
if (NameR.substr(21, 2) != ".s") switch (NameR[20]) {
break;
switch (NameR[23]) {
default: break; default: break;
case '0': // 1 string to match. case 'h': // 2 strings to match.
return Intrinsic::hexagon_M2_mpyd_nac_hl_s0; // if (memcmp(NameR.data()+21, ".s", 2))
"exagon.M2.mpyd.nac.hl.s0" break;
case '1': // 1 string to match. switch (NameR[23]) {
return Intrinsic::hexagon_M2_mpyd_nac_hl_s1; // default: break;
"exagon.M2.mpyd.nac.hl.s1" case '0': // 1 string to match.
} return Intrinsic::hexagon_M2_mpyd_acc_lh_s0; //
break; "exagon.M2.mpyd.acc.lh.s0"
} case '1': // 1 string to match.
break; return Intrinsic::hexagon_M2_mpyd_acc_lh_s1; //
case 'l': // 4 strings to match. "exagon.M2.mpyd.acc.lh.s1"
switch (NameR[20]) { }
default: break;
case 'h': // 2 strings to match.
if (NameR.substr(21, 2) != ".s")
break; break;
switch (NameR[23]) { case 'l': // 2 strings to match.
default: break; if (memcmp(NameR.data()+21, ".s", 2))
case '0': // 1 string to match. break;
return Intrinsic::hexagon_M2_mpyd_nac_lh_s0; // switch (NameR[23]) {
"exagon.M2.mpyd.nac.lh.s0" default: break;
case '1': // 1 string to match. case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_nac_lh_s1; // return Intrinsic::hexagon_M2_mpyd_acc_ll_s0; //
"exagon.M2.mpyd.nac.lh.s1" "exagon.M2.mpyd.acc.ll.s0"
} case '1': // 1 string to match.
break; return Intrinsic::hexagon_M2_mpyd_acc_ll_s1; //
case 'l': // 2 strings to match. "exagon.M2.mpyd.acc.ll.s1"
if (NameR.substr(21, 2) != ".s") }
break; break;
switch (NameR[23]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_nac_ll_s0; //
"exagon.M2.mpyd.nac.ll.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_nac_ll_s1; //
"exagon.M2.mpyd.nac.ll.s1"
} }
break; break;
} }
break; break;
} case 'n': // 8 strings to match.
break; if (memcmp(NameR.data()+16, "ac.", 3))
case 'r': // 8 strings to match. break;
if (NameR.substr(16, 3) != "nd.") switch (NameR[19]) {
break;
switch (NameR[19]) {
default: break;
case 'h': // 4 strings to match.
switch (NameR[20]) {
default: break; default: break;
case 'h': // 2 strings to match. case 'h': // 4 strings to match.
if (NameR.substr(21, 2) != ".s") switch (NameR[20]) {
break;
switch (NameR[23]) {
default: break; default: break;
case '0': // 1 string to match. case 'h': // 2 strings to match.
return Intrinsic::hexagon_M2_mpyd_rnd_hh_s0; // if (memcmp(NameR.data()+21, ".s", 2))
"exagon.M2.mpyd.rnd.hh.s0" break;
case '1': // 1 string to match. switch (NameR[23]) {
return Intrinsic::hexagon_M2_mpyd_rnd_hh_s1; // default: break;
"exagon.M2.mpyd.rnd.hh.s1" case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_nac_hh_s0; //
"exagon.M2.mpyd.nac.hh.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_nac_hh_s1; //
"exagon.M2.mpyd.nac.hh.s1"
}
break;
case 'l': // 2 strings to match.
if (memcmp(NameR.data()+21, ".s", 2))
break;
switch (NameR[23]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_nac_hl_s0; //
"exagon.M2.mpyd.nac.hl.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_nac_hl_s1; //
"exagon.M2.mpyd.nac.hl.s1"
}
break;
} }
break; break;
case 'l': // 2 strings to match. case 'l': // 4 strings to match.
if (NameR.substr(21, 2) != ".s") switch (NameR[20]) {
break;
switch (NameR[23]) {
default: break; default: break;
case '0': // 1 string to match. case 'h': // 2 strings to match.
return Intrinsic::hexagon_M2_mpyd_rnd_hl_s0; // if (memcmp(NameR.data()+21, ".s", 2))
"exagon.M2.mpyd.rnd.hl.s0" break;
case '1': // 1 string to match. switch (NameR[23]) {
return Intrinsic::hexagon_M2_mpyd_rnd_hl_s1; // default: break;
"exagon.M2.mpyd.rnd.hl.s1" case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_nac_lh_s0; //
"exagon.M2.mpyd.nac.lh.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_nac_lh_s1; //
"exagon.M2.mpyd.nac.lh.s1"
}
break;
case 'l': // 2 strings to match.
if (memcmp(NameR.data()+21, ".s", 2))
break;
switch (NameR[23]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_nac_ll_s0; //
"exagon.M2.mpyd.nac.ll.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_nac_ll_s1; //
"exagon.M2.mpyd.nac.ll.s1"
}
break;
} }
break; break;
} }
break; break;
case 'l': // 4 strings to match. case 'r': // 8 strings to match.
switch (NameR[20]) { if (memcmp(NameR.data()+16, "nd.", 3))
break;
switch (NameR[19]) {
default: break; default: break;
case 'h': // 2 strings to match. case 'h': // 4 strings to match.
if (NameR.substr(21, 2) != ".s") switch (NameR[20]) {
break;
switch (NameR[23]) {
default: break; default: break;
case '0': // 1 string to match. case 'h': // 2 strings to match.
return Intrinsic::hexagon_M2_mpyd_rnd_lh_s0; // if (memcmp(NameR.data()+21, ".s", 2))
"exagon.M2.mpyd.rnd.lh.s0" break;
case '1': // 1 string to match. switch (NameR[23]) {
return Intrinsic::hexagon_M2_mpyd_rnd_lh_s1; // default: break;
"exagon.M2.mpyd.rnd.lh.s1" case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_rnd_hh_s0; //
"exagon.M2.mpyd.rnd.hh.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_rnd_hh_s1; //
"exagon.M2.mpyd.rnd.hh.s1"
}
break;
case 'l': // 2 strings to match.
if (memcmp(NameR.data()+21, ".s", 2))
break;
switch (NameR[23]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_rnd_hl_s0; //
"exagon.M2.mpyd.rnd.hl.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_rnd_hl_s1; //
"exagon.M2.mpyd.rnd.hl.s1"
}
break;
} }
break; break;
case 'l': // 2 strings to match. case 'l': // 4 strings to match.
if (NameR.substr(21, 2) != ".s") switch (NameR[20]) {
break;
switch (NameR[23]) {
default: break; default: break;
case '0': // 1 string to match. case 'h': // 2 strings to match.
return Intrinsic::hexagon_M2_mpyd_rnd_ll_s0; // if (memcmp(NameR.data()+21, ".s", 2))
"exagon.M2.mpyd.rnd.ll.s0" break;
case '1': // 1 string to match. switch (NameR[23]) {
return Intrinsic::hexagon_M2_mpyd_rnd_ll_s1; // default: break;
"exagon.M2.mpyd.rnd.ll.s1" case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_rnd_lh_s0; //
"exagon.M2.mpyd.rnd.lh.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_rnd_lh_s1; //
"exagon.M2.mpyd.rnd.lh.s1"
}
break;
case 'l': // 2 strings to match.
if (memcmp(NameR.data()+21, ".s", 2))
break;
switch (NameR[23]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_rnd_ll_s0; //
"exagon.M2.mpyd.rnd.ll.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_rnd_ll_s1; //
"exagon.M2.mpyd.rnd.ll.s1"
}
break;
} }
break; break;
} }
break; break;
} }
break; break;
} case 'u': // 16 strings to match.
break; if (NameR[14] != '.')
case 'u': // 16 strings to match.
if (NameR[14] != '.')
break;
switch (NameR[15]) {
default: break;
case 'a': // 8 strings to match.
if (NameR.substr(16, 3) != "cc.")
break; break;
switch (NameR[19]) { switch (NameR[15]) {
default: break; default: break;
case 'h': // 4 strings to match. case 'a': // 8 strings to match.
switch (NameR[20]) { if (memcmp(NameR.data()+16, "cc.", 3))
break;
switch (NameR[19]) {
default: break; default: break;
case 'h': // 2 strings to match. case 'h': // 4 strings to match.
if (NameR.substr(21, 2) != ".s") switch (NameR[20]) {
break;
switch (NameR[23]) {
default: break; default: break;
case '0': // 1 string to match. case 'h': // 2 strings to match.
return Intrinsic::hexagon_M2_mpyu_acc_hh_s0; // if (memcmp(NameR.data()+21, ".s", 2))
"exagon.M2.mpyu.acc.hh.s0" break;
case '1': // 1 string to match. switch (NameR[23]) {
return Intrinsic::hexagon_M2_mpyu_acc_hh_s1; // default: break;
"exagon.M2.mpyu.acc.hh.s1" case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyu_acc_hh_s0; //
"exagon.M2.mpyu.acc.hh.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyu_acc_hh_s1; //
"exagon.M2.mpyu.acc.hh.s1"
}
break;
case 'l': // 2 strings to match.
if (memcmp(NameR.data()+21, ".s", 2))
break;
switch (NameR[23]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyu_acc_hl_s0; //
"exagon.M2.mpyu.acc.hl.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyu_acc_hl_s1; //
"exagon.M2.mpyu.acc.hl.s1"
}
break;
} }
break; break;
case 'l': // 2 strings to match. case 'l': // 4 strings to match.
if (NameR.substr(21, 2) != ".s") switch (NameR[20]) {
break;
switch (NameR[23]) {
default: break; default: break;
case '0': // 1 string to match. case 'h': // 2 strings to match.
return Intrinsic::hexagon_M2_mpyu_acc_hl_s0; // if (memcmp(NameR.data()+21, ".s", 2))
"exagon.M2.mpyu.acc.hl.s0" break;
case '1': // 1 string to match. switch (NameR[23]) {
return Intrinsic::hexagon_M2_mpyu_acc_hl_s1; // default: break;
"exagon.M2.mpyu.acc.hl.s1" case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyu_acc_lh_s0; //
"exagon.M2.mpyu.acc.lh.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyu_acc_lh_s1; //
"exagon.M2.mpyu.acc.lh.s1"
}
break;
case 'l': // 2 strings to match.
if (memcmp(NameR.data()+21, ".s", 2))
break;
switch (NameR[23]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyu_acc_ll_s0; //
"exagon.M2.mpyu.acc.ll.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyu_acc_ll_s1; //
"exagon.M2.mpyu.acc.ll.s1"
}
break;
} }
break; break;
} }
break; break;
case 'l': // 4 strings to match. case 'n': // 8 strings to match.
switch (NameR[20]) { if (memcmp(NameR.data()+16, "ac.", 3))
break;
switch (NameR[19]) {
default: break; default: break;
case 'h': // 2 strings to match. case 'h': // 4 strings to match.
if (NameR.substr(21, 2) != ".s") switch (NameR[20]) {
break;
switch (NameR[23]) {
default: break; default: break;
case '0': // 1 string to match. case 'h': // 2 strings to match.
return Intrinsic::hexagon_M2_mpyu_acc_lh_s0; // if (memcmp(NameR.data()+21, ".s", 2))
"exagon.M2.mpyu.acc.lh.s0" break;
case '1': // 1 string to match. switch (NameR[23]) {
return Intrinsic::hexagon_M2_mpyu_acc_lh_s1; // default: break;
"exagon.M2.mpyu.acc.lh.s1" case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyu_nac_hh_s0; //
"exagon.M2.mpyu.nac.hh.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyu_nac_hh_s1; //
"exagon.M2.mpyu.nac.hh.s1"
}
break;
case 'l': // 2 strings to match.
if (memcmp(NameR.data()+21, ".s", 2))
break;
switch (NameR[23]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyu_nac_hl_s0; //
"exagon.M2.mpyu.nac.hl.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyu_nac_hl_s1; //
"exagon.M2.mpyu.nac.hl.s1"
}
break;
} }
break; break;
case 'l': // 2 strings to match. case 'l': // 4 strings to match.
if (NameR.substr(21, 2) != ".s") switch (NameR[20]) {
break;
switch (NameR[23]) {
default: break; default: break;
case '0': // 1 string to match. case 'h': // 2 strings to match.
return Intrinsic::hexagon_M2_mpyu_acc_ll_s0; // if (memcmp(NameR.data()+21, ".s", 2))
"exagon.M2.mpyu.acc.ll.s0" break;
case '1': // 1 string to match. switch (NameR[23]) {
return Intrinsic::hexagon_M2_mpyu_acc_ll_s1; // default: break;
"exagon.M2.mpyu.acc.ll.s1" case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyu_nac_lh_s0; //
"exagon.M2.mpyu.nac.lh.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyu_nac_lh_s1; //
"exagon.M2.mpyu.nac.lh.s1"
}
break;
case 'l': // 2 strings to match.
if (memcmp(NameR.data()+21, ".s", 2))
break;
switch (NameR[23]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyu_nac_ll_s0; //
"exagon.M2.mpyu.nac.ll.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyu_nac_ll_s1; //
"exagon.M2.mpyu.nac.ll.s1"
}
break;
} }
break; break;
} }
break; break;
} }
break; break;
case 'n': // 8 strings to match. }
if (NameR.substr(16, 3) != "ac.") break;
case 'v': // 7 strings to match.
switch (NameR[11]) {
default: break;
case 'c': // 6 strings to match.
if (NameR[12] != 'm')
break; break;
switch (NameR[19]) { switch (NameR[13]) {
default: break; default: break;
case 'h': // 4 strings to match. case 'a': // 2 strings to match.
switch (NameR[20]) { if (memcmp(NameR.data()+14, "c.s0.sat.", 9))
default: break;
case 'h': // 2 strings to match.
if (NameR.substr(21, 2) != ".s")
break;
switch (NameR[23]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyu_nac_hh_s0; //
"exagon.M2.mpyu.nac.hh.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyu_nac_hh_s1; //
"exagon.M2.mpyu.nac.hh.s1"
}
break;
case 'l': // 2 strings to match.
if (NameR.substr(21, 2) != ".s")
break;
switch (NameR[23]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyu_nac_hl_s0; //
"exagon.M2.mpyu.nac.hl.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyu_nac_hl_s1; //
"exagon.M2.mpyu.nac.hl.s1"
}
break; break;
switch (NameR[23]) {
default: break;
case 'i': // 1 string to match.
return Intrinsic::hexagon_M2_vcmac_s0_sat_i; // "exagon.
M2.vcmac.s0.sat.i"
case 'r': // 1 string to match.
return Intrinsic::hexagon_M2_vcmac_s0_sat_r; // "exagon.
M2.vcmac.s0.sat.r"
} }
break; break;
case 'l': // 4 strings to match. case 'p': // 4 strings to match.
switch (NameR[20]) { if (memcmp(NameR.data()+14, "y.s", 3))
break;
switch (NameR[17]) {
default: break; default: break;
case 'h': // 2 strings to match. case '0': // 2 strings to match.
if (NameR.substr(21, 2) != ".s") if (memcmp(NameR.data()+18, ".sat.", 5))
break; break;
switch (NameR[23]) { switch (NameR[23]) {
default: break; default: break;
case '0': // 1 string to match. case 'i': // 1 string to match.
return Intrinsic::hexagon_M2_mpyu_nac_lh_s0; // return Intrinsic::hexagon_M2_vcmpy_s0_sat_i; //
"exagon.M2.mpyu.nac.lh.s0" "exagon.M2.vcmpy.s0.sat.i"
case '1': // 1 string to match. case 'r': // 1 string to match.
return Intrinsic::hexagon_M2_mpyu_nac_lh_s1; // return Intrinsic::hexagon_M2_vcmpy_s0_sat_r; //
"exagon.M2.mpyu.nac.lh.s1" "exagon.M2.vcmpy.s0.sat.r"
} }
break; break;
case 'l': // 2 strings to match. case '1': // 2 strings to match.
if (NameR.substr(21, 2) != ".s") if (memcmp(NameR.data()+18, ".sat.", 5))
break; break;
switch (NameR[23]) { switch (NameR[23]) {
default: break; default: break;
case '0': // 1 string to match. case 'i': // 1 string to match.
return Intrinsic::hexagon_M2_mpyu_nac_ll_s0; // return Intrinsic::hexagon_M2_vcmpy_s1_sat_i; //
"exagon.M2.mpyu.nac.ll.s0" "exagon.M2.vcmpy.s1.sat.i"
case '1': // 1 string to match. case 'r': // 1 string to match.
return Intrinsic::hexagon_M2_mpyu_nac_ll_s1; // return Intrinsic::hexagon_M2_vcmpy_s1_sat_r; //
"exagon.M2.mpyu.nac.ll.s1" "exagon.M2.vcmpy.s1.sat.r"
} }
break; break;
} }
break; break;
} }
break; break;
case 'r': // 1 string to match.
if (memcmp(NameR.data()+12, "cmpys.acc.s1", 12))
break;
return Intrinsic::hexagon_M2_vrcmpys_acc_s1; // "exagon.
M2.vrcmpys.acc.s1"
} }
break; break;
} }
break; break;
case 'v': // 7 strings to match. case '4': // 4 strings to match.
switch (NameR[11]) { if (memcmp(NameR.data()+9, ".vrmpy", 6))
break;
switch (NameR[15]) {
default: break; default: break;
case 'c': // 6 strings to match. case 'e': // 2 strings to match.
if (NameR[12] != 'm') if (memcmp(NameR.data()+16, "h.acc.s", 7))
break; break;
switch (NameR[13]) { switch (NameR[23]) {
default: break; default: break;
case 'a': // 2 strings to match. case '0': // 1 string to match.
if (NameR.substr(14, 9) != "c.s0.sat.") return Intrinsic::hexagon_M4_vrmpyeh_acc_s0; // "exagon.
break; M4.vrmpyeh.acc.s0"
switch (NameR[23]) { case '1': // 1 string to match.
default: break; return Intrinsic::hexagon_M4_vrmpyeh_acc_s1; // "exagon.
case 'i': // 1 string to match. M4.vrmpyeh.acc.s1"
return Intrinsic::hexagon_M2_vcmac_s0_sat_i; // "exagon. }
M2.vcmac.s0.sat.i" break;
case 'r': // 1 string to match. case 'o': // 2 strings to match.
return Intrinsic::hexagon_M2_vcmac_s0_sat_r; // "exagon. if (memcmp(NameR.data()+16, "h.acc.s", 7))
M2.vcmac.s0.sat.r"
}
break;
case 'p': // 4 strings to match.
if (NameR.substr(14, 3) != "y.s")
break;
switch (NameR[17]) {
default: break;
case '0': // 2 strings to match.
if (NameR.substr(18, 5) != ".sat.")
break;
switch (NameR[23]) {
default: break;
case 'i': // 1 string to match.
return Intrinsic::hexagon_M2_vcmpy_s0_sat_i; // "exagon.
M2.vcmpy.s0.sat.i"
case 'r': // 1 string to match.
return Intrinsic::hexagon_M2_vcmpy_s0_sat_r; // "exagon.
M2.vcmpy.s0.sat.r"
}
break;
case '1': // 2 strings to match.
if (NameR.substr(18, 5) != ".sat.")
break;
switch (NameR[23]) {
default: break;
case 'i': // 1 string to match.
return Intrinsic::hexagon_M2_vcmpy_s1_sat_i; // "exagon.
M2.vcmpy.s1.sat.i"
case 'r': // 1 string to match.
return Intrinsic::hexagon_M2_vcmpy_s1_sat_r; // "exagon.
M2.vcmpy.s1.sat.r"
}
break;
}
break; break;
switch (NameR[23]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M4_vrmpyoh_acc_s0; // "exagon.
M4.vrmpyoh.acc.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M4_vrmpyoh_acc_s1; // "exagon.
M4.vrmpyoh.acc.s1"
} }
break; break;
case 'r': // 1 string to match.
if (NameR.substr(12, 12) != "cmpys.acc.s1")
break;
return Intrinsic::hexagon_M2_vrcmpys_acc_s1; // "exagon.
M2.vrcmpys.acc.s1"
} }
break; break;
} }
break; break;
case 'S': // 4 strings to match. case 'S': // 4 strings to match.
if (NameR.substr(8, 2) != "2.") if (memcmp(NameR.data()+8, "2.", 2))
break; break;
switch (NameR[10]) { switch (NameR[10]) {
default: break; default: break;
case 'a': // 2 strings to match. case 'a': // 2 strings to match.
if (NameR.substr(11, 3) != "sr.") if (memcmp(NameR.data()+11, "sr.", 3))
break; break;
switch (NameR[14]) { switch (NameR[14]) {
default: break; default: break;
case 'i': // 1 string to match. case 'i': // 1 string to match.
if (NameR.substr(15, 9) != ".svw.trun") if (memcmp(NameR.data()+15, ".svw.trun", 9))
break; break;
return Intrinsic::hexagon_S2_asr_i_svw_trun; // "exagon. S2.asr.i.svw.trun" return Intrinsic::hexagon_S2_asr_i_svw_trun; // "exagon. S2.asr.i.svw.trun"
case 'r': // 1 string to match. case 'r': // 1 string to match.
if (NameR.substr(15, 9) != ".svw.trun") if (memcmp(NameR.data()+15, ".svw.trun", 9))
break; break;
return Intrinsic::hexagon_S2_asr_r_svw_trun; // "exagon. S2.asr.r.svw.trun" return Intrinsic::hexagon_S2_asr_r_svw_trun; // "exagon. S2.asr.r.svw.trun"
} }
break; break;
case 'v': // 2 strings to match. case 'v': // 2 strings to match.
if (NameR.substr(11, 3) != "sat") if (memcmp(NameR.data()+11, "sat", 3))
break; break;
switch (NameR[14]) { switch (NameR[14]) {
default: break; default: break;
case 'h': // 1 string to match. case 'h': // 1 string to match.
if (NameR.substr(15, 9) != "ub.nopack") if (memcmp(NameR.data()+15, "ub.nopack", 9))
break; break;
return Intrinsic::hexagon_S2_vsathub_nopack; // "exagon. S2.vsathub.nopack" return Intrinsic::hexagon_S2_vsathub_nopack; // "exagon. S2.vsathub.nopack"
case 'w': // 1 string to match. case 'w': // 1 string to match.
if (NameR.substr(15, 9) != "uh.nopack") if (memcmp(NameR.data()+15, "uh.nopack", 9))
break; break;
return Intrinsic::hexagon_S2_vsatwuh_nopack; // "exagon. S2.vsatwuh.nopack" return Intrinsic::hexagon_S2_vsatwuh_nopack; // "exagon. S2.vsatwuh.nopack"
} }
break; break;
} }
break; break;
} }
break; break;
case 25: // 31 strings to match. case 25: // 33 strings to match.
if (NameR.substr(0, 7) != "exagon.") if (memcmp(NameR.data()+0, "exagon.", 7))
break; break;
switch (NameR[7]) { switch (NameR[7]) {
default: break; default: break;
case 'A': // 14 strings to match. case 'A': // 12 strings to match.
if (NameR.substr(8, 2) != "2.") if (memcmp(NameR.data()+8, "2.", 2))
break; break;
switch (NameR[10]) { switch (NameR[10]) {
default: break; default: break;
case 'a': // 8 strings to match. case 'a': // 6 strings to match.
if (NameR.substr(11, 4) != "ddh.") if (memcmp(NameR.data()+11, "ddh.", 4))
break; break;
switch (NameR[15]) { switch (NameR[15]) {
default: break; default: break;
case 'h': // 4 strings to match. case 'h': // 4 strings to match.
if (NameR.substr(16, 7) != "16.sat.") if (memcmp(NameR.data()+16, "16.sat.", 7))
break; break;
switch (NameR[23]) { switch (NameR[23]) {
default: break; default: break;
case 'h': // 2 strings to match. case 'h': // 2 strings to match.
switch (NameR[24]) { switch (NameR[24]) {
default: break; default: break;
case 'h': // 1 string to match. case 'h': // 1 string to match.
return Intrinsic::hexagon_A2_addh_h16_sat_hh; // "exagon. A2.addh.h16.sat.hh" return Intrinsic::hexagon_A2_addh_h16_sat_hh; // "exagon. A2.addh.h16.sat.hh"
case 'l': // 1 string to match. case 'l': // 1 string to match.
return Intrinsic::hexagon_A2_addh_h16_sat_hl; // "exagon. A2.addh.h16.sat.hl" return Intrinsic::hexagon_A2_addh_h16_sat_hl; // "exagon. A2.addh.h16.sat.hl"
skipping to change at line 9367 skipping to change at line 12086
switch (NameR[24]) { switch (NameR[24]) {
default: break; default: break;
case 'h': // 1 string to match. case 'h': // 1 string to match.
return Intrinsic::hexagon_A2_addh_h16_sat_lh; // "exagon. A2.addh.h16.sat.lh" return Intrinsic::hexagon_A2_addh_h16_sat_lh; // "exagon. A2.addh.h16.sat.lh"
case 'l': // 1 string to match. case 'l': // 1 string to match.
return Intrinsic::hexagon_A2_addh_h16_sat_ll; // "exagon. A2.addh.h16.sat.ll" return Intrinsic::hexagon_A2_addh_h16_sat_ll; // "exagon. A2.addh.h16.sat.ll"
} }
break; break;
} }
break; break;
case 'l': // 4 strings to match. case 'l': // 2 strings to match.
if (NameR.substr(16, 7) != "16.sat.") if (memcmp(NameR.data()+16, "16.sat.", 7))
break; break;
switch (NameR[23]) { switch (NameR[23]) {
default: break; default: break;
case 'h': // 2 strings to match. case 'h': // 1 string to match.
switch (NameR[24]) { if (NameR[24] != 'l')
default: break; break;
case 'h': // 1 string to match. return Intrinsic::hexagon_A2_addh_l16_sat_hl; // "exagon.
return Intrinsic::hexagon_A2_addh_l16_sat_hh; // "exagon. A2.addh.l16.sat.hl"
A2.addh.l16.sat.hh" case 'l': // 1 string to match.
case 'l': // 1 string to match. if (NameR[24] != 'l')
return Intrinsic::hexagon_A2_addh_l16_sat_hl; // "exagon. break;
A2.addh.l16.sat.hl" return Intrinsic::hexagon_A2_addh_l16_sat_ll; // "exagon.
} A2.addh.l16.sat.ll"
break;
case 'l': // 2 strings to match.
switch (NameR[24]) {
default: break;
case 'h': // 1 string to match.
return Intrinsic::hexagon_A2_addh_l16_sat_lh; // "exagon.
A2.addh.l16.sat.lh"
case 'l': // 1 string to match.
return Intrinsic::hexagon_A2_addh_l16_sat_ll; // "exagon.
A2.addh.l16.sat.ll"
}
break;
} }
break; break;
} }
break; break;
case 's': // 6 strings to match. case 's': // 6 strings to match.
if (NameR.substr(11, 4) != "ubh.") if (memcmp(NameR.data()+11, "ubh.", 4))
break; break;
switch (NameR[15]) { switch (NameR[15]) {
default: break; default: break;
case 'h': // 4 strings to match. case 'h': // 4 strings to match.
if (NameR.substr(16, 7) != "16.sat.") if (memcmp(NameR.data()+16, "16.sat.", 7))
break; break;
switch (NameR[23]) { switch (NameR[23]) {
default: break; default: break;
case 'h': // 2 strings to match. case 'h': // 2 strings to match.
switch (NameR[24]) { switch (NameR[24]) {
default: break; default: break;
case 'h': // 1 string to match. case 'h': // 1 string to match.
return Intrinsic::hexagon_A2_subh_h16_sat_hh; // "exagon. A2.subh.h16.sat.hh" return Intrinsic::hexagon_A2_subh_h16_sat_hh; // "exagon. A2.subh.h16.sat.hh"
case 'l': // 1 string to match. case 'l': // 1 string to match.
return Intrinsic::hexagon_A2_subh_h16_sat_hl; // "exagon. A2.subh.h16.sat.hl" return Intrinsic::hexagon_A2_subh_h16_sat_hl; // "exagon. A2.subh.h16.sat.hl"
skipping to change at line 9425 skipping to change at line 12134
default: break; default: break;
case 'h': // 1 string to match. case 'h': // 1 string to match.
return Intrinsic::hexagon_A2_subh_h16_sat_lh; // "exagon. A2.subh.h16.sat.lh" return Intrinsic::hexagon_A2_subh_h16_sat_lh; // "exagon. A2.subh.h16.sat.lh"
case 'l': // 1 string to match. case 'l': // 1 string to match.
return Intrinsic::hexagon_A2_subh_h16_sat_ll; // "exagon. A2.subh.h16.sat.ll" return Intrinsic::hexagon_A2_subh_h16_sat_ll; // "exagon. A2.subh.h16.sat.ll"
} }
break; break;
} }
break; break;
case 'l': // 2 strings to match. case 'l': // 2 strings to match.
if (NameR.substr(16, 7) != "16.sat.") if (memcmp(NameR.data()+16, "16.sat.", 7))
break; break;
switch (NameR[23]) { switch (NameR[23]) {
default: break; default: break;
case 'h': // 1 string to match. case 'h': // 1 string to match.
if (NameR[24] != 'l') if (NameR[24] != 'l')
break; break;
return Intrinsic::hexagon_A2_subh_l16_sat_hl; // "exagon. A2.subh.l16.sat.hl" return Intrinsic::hexagon_A2_subh_l16_sat_hl; // "exagon. A2.subh.l16.sat.hl"
case 'l': // 1 string to match. case 'l': // 1 string to match.
if (NameR[24] != 'l') if (NameR[24] != 'l')
break; break;
return Intrinsic::hexagon_A2_subh_l16_sat_ll; // "exagon. A2.subh.l16.sat.ll" return Intrinsic::hexagon_A2_subh_l16_sat_ll; // "exagon. A2.subh.l16.sat.ll"
} }
break; break;
} }
break; break;
} }
break; break;
case 'C': // 1 string to match. case 'C': // 1 string to match.
if (NameR.substr(8, 17) != "4.fastcorner9.not") if (memcmp(NameR.data()+8, "4.fastcorner9.not", 17))
break; break;
return Intrinsic::hexagon_C4_fastcorner9_not; // "exagon.C4.fastc orner9.not" return Intrinsic::hexagon_C4_fastcorner9_not; // "exagon.C4.fastc orner9.not"
case 'F': // 4 strings to match.
if (memcmp(NameR.data()+8, "2.conv.", 7))
break;
switch (NameR[15]) {
default: break;
case 'd': // 2 strings to match.
if (memcmp(NameR.data()+16, "f2u", 3))
break;
switch (NameR[19]) {
default: break;
case 'd': // 1 string to match.
if (memcmp(NameR.data()+20, ".chop", 5))
break;
return Intrinsic::hexagon_F2_conv_df2ud_chop; // "exagon.
F2.conv.df2ud.chop"
case 'w': // 1 string to match.
if (memcmp(NameR.data()+20, ".chop", 5))
break;
return Intrinsic::hexagon_F2_conv_df2uw_chop; // "exagon.
F2.conv.df2uw.chop"
}
break;
case 's': // 2 strings to match.
if (memcmp(NameR.data()+16, "f2u", 3))
break;
switch (NameR[19]) {
default: break;
case 'd': // 1 string to match.
if (memcmp(NameR.data()+20, ".chop", 5))
break;
return Intrinsic::hexagon_F2_conv_sf2ud_chop; // "exagon.
F2.conv.sf2ud.chop"
case 'w': // 1 string to match.
if (memcmp(NameR.data()+20, ".chop", 5))
break;
return Intrinsic::hexagon_F2_conv_sf2uw_chop; // "exagon.
F2.conv.sf2uw.chop"
}
break;
}
break;
case 'M': // 16 strings to match. case 'M': // 16 strings to match.
if (NameR.substr(8, 8) != "2.mpyud.") if (memcmp(NameR.data()+8, "2.mpyud.", 8))
break; break;
switch (NameR[16]) { switch (NameR[16]) {
default: break; default: break;
case 'a': // 8 strings to match. case 'a': // 8 strings to match.
if (NameR.substr(17, 3) != "cc.") if (memcmp(NameR.data()+17, "cc.", 3))
break; break;
switch (NameR[20]) { switch (NameR[20]) {
default: break; default: break;
case 'h': // 4 strings to match. case 'h': // 4 strings to match.
switch (NameR[21]) { switch (NameR[21]) {
default: break; default: break;
case 'h': // 2 strings to match. case 'h': // 2 strings to match.
if (NameR.substr(22, 2) != ".s") if (memcmp(NameR.data()+22, ".s", 2))
break; break;
switch (NameR[24]) { switch (NameR[24]) {
default: break; default: break;
case '0': // 1 string to match. case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyud_acc_hh_s0; // "exagon. M2.mpyud.acc.hh.s0" return Intrinsic::hexagon_M2_mpyud_acc_hh_s0; // "exagon. M2.mpyud.acc.hh.s0"
case '1': // 1 string to match. case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyud_acc_hh_s1; // "exagon. M2.mpyud.acc.hh.s1" return Intrinsic::hexagon_M2_mpyud_acc_hh_s1; // "exagon. M2.mpyud.acc.hh.s1"
} }
break; break;
case 'l': // 2 strings to match. case 'l': // 2 strings to match.
if (NameR.substr(22, 2) != ".s") if (memcmp(NameR.data()+22, ".s", 2))
break; break;
switch (NameR[24]) { switch (NameR[24]) {
default: break; default: break;
case '0': // 1 string to match. case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyud_acc_hl_s0; // "exagon. M2.mpyud.acc.hl.s0" return Intrinsic::hexagon_M2_mpyud_acc_hl_s0; // "exagon. M2.mpyud.acc.hl.s0"
case '1': // 1 string to match. case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyud_acc_hl_s1; // "exagon. M2.mpyud.acc.hl.s1" return Intrinsic::hexagon_M2_mpyud_acc_hl_s1; // "exagon. M2.mpyud.acc.hl.s1"
} }
break; break;
} }
break; break;
case 'l': // 4 strings to match. case 'l': // 4 strings to match.
switch (NameR[21]) { switch (NameR[21]) {
default: break; default: break;
case 'h': // 2 strings to match. case 'h': // 2 strings to match.
if (NameR.substr(22, 2) != ".s") if (memcmp(NameR.data()+22, ".s", 2))
break; break;
switch (NameR[24]) { switch (NameR[24]) {
default: break; default: break;
case '0': // 1 string to match. case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyud_acc_lh_s0; // "exagon. M2.mpyud.acc.lh.s0" return Intrinsic::hexagon_M2_mpyud_acc_lh_s0; // "exagon. M2.mpyud.acc.lh.s0"
case '1': // 1 string to match. case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyud_acc_lh_s1; // "exagon. M2.mpyud.acc.lh.s1" return Intrinsic::hexagon_M2_mpyud_acc_lh_s1; // "exagon. M2.mpyud.acc.lh.s1"
} }
break; break;
case 'l': // 2 strings to match. case 'l': // 2 strings to match.
if (NameR.substr(22, 2) != ".s") if (memcmp(NameR.data()+22, ".s", 2))
break; break;
switch (NameR[24]) { switch (NameR[24]) {
default: break; default: break;
case '0': // 1 string to match. case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyud_acc_ll_s0; // "exagon. M2.mpyud.acc.ll.s0" return Intrinsic::hexagon_M2_mpyud_acc_ll_s0; // "exagon. M2.mpyud.acc.ll.s0"
case '1': // 1 string to match. case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyud_acc_ll_s1; // "exagon. M2.mpyud.acc.ll.s1" return Intrinsic::hexagon_M2_mpyud_acc_ll_s1; // "exagon. M2.mpyud.acc.ll.s1"
} }
break; break;
} }
break; break;
} }
break; break;
case 'n': // 8 strings to match. case 'n': // 8 strings to match.
if (NameR.substr(17, 3) != "ac.") if (memcmp(NameR.data()+17, "ac.", 3))
break; break;
switch (NameR[20]) { switch (NameR[20]) {
default: break; default: break;
case 'h': // 4 strings to match. case 'h': // 4 strings to match.
switch (NameR[21]) { switch (NameR[21]) {
default: break; default: break;
case 'h': // 2 strings to match. case 'h': // 2 strings to match.
if (NameR.substr(22, 2) != ".s") if (memcmp(NameR.data()+22, ".s", 2))
break; break;
switch (NameR[24]) { switch (NameR[24]) {
default: break; default: break;
case '0': // 1 string to match. case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyud_nac_hh_s0; // "exagon. M2.mpyud.nac.hh.s0" return Intrinsic::hexagon_M2_mpyud_nac_hh_s0; // "exagon. M2.mpyud.nac.hh.s0"
case '1': // 1 string to match. case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyud_nac_hh_s1; // "exagon. M2.mpyud.nac.hh.s1" return Intrinsic::hexagon_M2_mpyud_nac_hh_s1; // "exagon. M2.mpyud.nac.hh.s1"
} }
break; break;
case 'l': // 2 strings to match. case 'l': // 2 strings to match.
if (NameR.substr(22, 2) != ".s") if (memcmp(NameR.data()+22, ".s", 2))
break; break;
switch (NameR[24]) { switch (NameR[24]) {
default: break; default: break;
case '0': // 1 string to match. case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyud_nac_hl_s0; // "exagon. M2.mpyud.nac.hl.s0" return Intrinsic::hexagon_M2_mpyud_nac_hl_s0; // "exagon. M2.mpyud.nac.hl.s0"
case '1': // 1 string to match. case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyud_nac_hl_s1; // "exagon. M2.mpyud.nac.hl.s1" return Intrinsic::hexagon_M2_mpyud_nac_hl_s1; // "exagon. M2.mpyud.nac.hl.s1"
} }
break; break;
} }
break; break;
case 'l': // 4 strings to match. case 'l': // 4 strings to match.
switch (NameR[21]) { switch (NameR[21]) {
default: break; default: break;
case 'h': // 2 strings to match. case 'h': // 2 strings to match.
if (NameR.substr(22, 2) != ".s") if (memcmp(NameR.data()+22, ".s", 2))
break; break;
switch (NameR[24]) { switch (NameR[24]) {
default: break; default: break;
case '0': // 1 string to match. case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyud_nac_lh_s0; // "exagon. M2.mpyud.nac.lh.s0" return Intrinsic::hexagon_M2_mpyud_nac_lh_s0; // "exagon. M2.mpyud.nac.lh.s0"
case '1': // 1 string to match. case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyud_nac_lh_s1; // "exagon. M2.mpyud.nac.lh.s1" return Intrinsic::hexagon_M2_mpyud_nac_lh_s1; // "exagon. M2.mpyud.nac.lh.s1"
} }
break; break;
case 'l': // 2 strings to match. case 'l': // 2 strings to match.
if (NameR.substr(22, 2) != ".s") if (memcmp(NameR.data()+22, ".s", 2))
break; break;
switch (NameR[24]) { switch (NameR[24]) {
default: break; default: break;
case '0': // 1 string to match. case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyud_nac_ll_s0; // "exagon. M2.mpyud.nac.ll.s0" return Intrinsic::hexagon_M2_mpyud_nac_ll_s0; // "exagon. M2.mpyud.nac.ll.s0"
case '1': // 1 string to match. case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyud_nac_ll_s1; // "exagon. M2.mpyud.nac.ll.s1" return Intrinsic::hexagon_M2_mpyud_nac_ll_s1; // "exagon. M2.mpyud.nac.ll.s1"
} }
break; break;
} }
break; break;
} }
break; break;
} }
break; break;
} }
break; break;
case 27: // 24 strings to match. case 27: // 24 strings to match.
if (NameR.substr(0, 14) != "exagon.M2.mpy.") if (memcmp(NameR.data()+0, "exagon.M2.mpy.", 14))
break; break;
switch (NameR[14]) { switch (NameR[14]) {
default: break; default: break;
case 'a': // 8 strings to match. case 'a': // 8 strings to match.
if (NameR.substr(15, 7) != "cc.sat.") if (memcmp(NameR.data()+15, "cc.sat.", 7))
break; break;
switch (NameR[22]) { switch (NameR[22]) {
default: break; default: break;
case 'h': // 4 strings to match. case 'h': // 4 strings to match.
switch (NameR[23]) { switch (NameR[23]) {
default: break; default: break;
case 'h': // 2 strings to match. case 'h': // 2 strings to match.
if (NameR.substr(24, 2) != ".s") if (memcmp(NameR.data()+24, ".s", 2))
break; break;
switch (NameR[26]) { switch (NameR[26]) {
default: break; default: break;
case '0': // 1 string to match. case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_acc_sat_hh_s0; // "exagon. M2.mpy.acc.sat.hh.s0" return Intrinsic::hexagon_M2_mpy_acc_sat_hh_s0; // "exagon. M2.mpy.acc.sat.hh.s0"
case '1': // 1 string to match. case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_acc_sat_hh_s1; // "exagon. M2.mpy.acc.sat.hh.s1" return Intrinsic::hexagon_M2_mpy_acc_sat_hh_s1; // "exagon. M2.mpy.acc.sat.hh.s1"
} }
break; break;
case 'l': // 2 strings to match. case 'l': // 2 strings to match.
if (NameR.substr(24, 2) != ".s") if (memcmp(NameR.data()+24, ".s", 2))
break; break;
switch (NameR[26]) { switch (NameR[26]) {
default: break; default: break;
case '0': // 1 string to match. case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_acc_sat_hl_s0; // "exagon. M2.mpy.acc.sat.hl.s0" return Intrinsic::hexagon_M2_mpy_acc_sat_hl_s0; // "exagon. M2.mpy.acc.sat.hl.s0"
case '1': // 1 string to match. case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_acc_sat_hl_s1; // "exagon. M2.mpy.acc.sat.hl.s1" return Intrinsic::hexagon_M2_mpy_acc_sat_hl_s1; // "exagon. M2.mpy.acc.sat.hl.s1"
} }
break; break;
} }
break; break;
case 'l': // 4 strings to match. case 'l': // 4 strings to match.
switch (NameR[23]) { switch (NameR[23]) {
default: break; default: break;
case 'h': // 2 strings to match. case 'h': // 2 strings to match.
if (NameR.substr(24, 2) != ".s") if (memcmp(NameR.data()+24, ".s", 2))
break; break;
switch (NameR[26]) { switch (NameR[26]) {
default: break; default: break;
case '0': // 1 string to match. case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_acc_sat_lh_s0; // "exagon. M2.mpy.acc.sat.lh.s0" return Intrinsic::hexagon_M2_mpy_acc_sat_lh_s0; // "exagon. M2.mpy.acc.sat.lh.s0"
case '1': // 1 string to match. case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_acc_sat_lh_s1; // "exagon. M2.mpy.acc.sat.lh.s1" return Intrinsic::hexagon_M2_mpy_acc_sat_lh_s1; // "exagon. M2.mpy.acc.sat.lh.s1"
} }
break; break;
case 'l': // 2 strings to match. case 'l': // 2 strings to match.
if (NameR.substr(24, 2) != ".s") if (memcmp(NameR.data()+24, ".s", 2))
break; break;
switch (NameR[26]) { switch (NameR[26]) {
default: break; default: break;
case '0': // 1 string to match. case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_acc_sat_ll_s0; // "exagon. M2.mpy.acc.sat.ll.s0" return Intrinsic::hexagon_M2_mpy_acc_sat_ll_s0; // "exagon. M2.mpy.acc.sat.ll.s0"
case '1': // 1 string to match. case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_acc_sat_ll_s1; // "exagon. M2.mpy.acc.sat.ll.s1" return Intrinsic::hexagon_M2_mpy_acc_sat_ll_s1; // "exagon. M2.mpy.acc.sat.ll.s1"
} }
break; break;
} }
break; break;
} }
break; break;
case 'n': // 8 strings to match. case 'n': // 8 strings to match.
if (NameR.substr(15, 7) != "ac.sat.") if (memcmp(NameR.data()+15, "ac.sat.", 7))
break; break;
switch (NameR[22]) { switch (NameR[22]) {
default: break; default: break;
case 'h': // 4 strings to match. case 'h': // 4 strings to match.
switch (NameR[23]) { switch (NameR[23]) {
default: break; default: break;
case 'h': // 2 strings to match. case 'h': // 2 strings to match.
if (NameR.substr(24, 2) != ".s") if (memcmp(NameR.data()+24, ".s", 2))
break; break;
switch (NameR[26]) { switch (NameR[26]) {
default: break; default: break;
case '0': // 1 string to match. case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_nac_sat_hh_s0; // "exagon. M2.mpy.nac.sat.hh.s0" return Intrinsic::hexagon_M2_mpy_nac_sat_hh_s0; // "exagon. M2.mpy.nac.sat.hh.s0"
case '1': // 1 string to match. case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_nac_sat_hh_s1; // "exagon. M2.mpy.nac.sat.hh.s1" return Intrinsic::hexagon_M2_mpy_nac_sat_hh_s1; // "exagon. M2.mpy.nac.sat.hh.s1"
} }
break; break;
case 'l': // 2 strings to match. case 'l': // 2 strings to match.
if (NameR.substr(24, 2) != ".s") if (memcmp(NameR.data()+24, ".s", 2))
break; break;
switch (NameR[26]) { switch (NameR[26]) {
default: break; default: break;
case '0': // 1 string to match. case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_nac_sat_hl_s0; // "exagon. M2.mpy.nac.sat.hl.s0" return Intrinsic::hexagon_M2_mpy_nac_sat_hl_s0; // "exagon. M2.mpy.nac.sat.hl.s0"
case '1': // 1 string to match. case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_nac_sat_hl_s1; // "exagon. M2.mpy.nac.sat.hl.s1" return Intrinsic::hexagon_M2_mpy_nac_sat_hl_s1; // "exagon. M2.mpy.nac.sat.hl.s1"
} }
break; break;
} }
break; break;
case 'l': // 4 strings to match. case 'l': // 4 strings to match.
switch (NameR[23]) { switch (NameR[23]) {
default: break; default: break;
case 'h': // 2 strings to match. case 'h': // 2 strings to match.
if (NameR.substr(24, 2) != ".s") if (memcmp(NameR.data()+24, ".s", 2))
break; break;
switch (NameR[26]) { switch (NameR[26]) {
default: break; default: break;
case '0': // 1 string to match. case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_nac_sat_lh_s0; // "exagon. M2.mpy.nac.sat.lh.s0" return Intrinsic::hexagon_M2_mpy_nac_sat_lh_s0; // "exagon. M2.mpy.nac.sat.lh.s0"
case '1': // 1 string to match. case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_nac_sat_lh_s1; // "exagon. M2.mpy.nac.sat.lh.s1" return Intrinsic::hexagon_M2_mpy_nac_sat_lh_s1; // "exagon. M2.mpy.nac.sat.lh.s1"
} }
break; break;
case 'l': // 2 strings to match. case 'l': // 2 strings to match.
if (NameR.substr(24, 2) != ".s") if (memcmp(NameR.data()+24, ".s", 2))
break; break;
switch (NameR[26]) { switch (NameR[26]) {
default: break; default: break;
case '0': // 1 string to match. case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_nac_sat_ll_s0; // "exagon. M2.mpy.nac.sat.ll.s0" return Intrinsic::hexagon_M2_mpy_nac_sat_ll_s0; // "exagon. M2.mpy.nac.sat.ll.s0"
case '1': // 1 string to match. case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_nac_sat_ll_s1; // "exagon. M2.mpy.nac.sat.ll.s1" return Intrinsic::hexagon_M2_mpy_nac_sat_ll_s1; // "exagon. M2.mpy.nac.sat.ll.s1"
} }
break; break;
} }
break; break;
} }
break; break;
case 's': // 8 strings to match. case 's': // 8 strings to match.
if (NameR.substr(15, 7) != "at.rnd.") if (memcmp(NameR.data()+15, "at.rnd.", 7))
break; break;
switch (NameR[22]) { switch (NameR[22]) {
default: break; default: break;
case 'h': // 4 strings to match. case 'h': // 4 strings to match.
switch (NameR[23]) { switch (NameR[23]) {
default: break; default: break;
case 'h': // 2 strings to match. case 'h': // 2 strings to match.
if (NameR.substr(24, 2) != ".s") if (memcmp(NameR.data()+24, ".s", 2))
break; break;
switch (NameR[26]) { switch (NameR[26]) {
default: break; default: break;
case '0': // 1 string to match. case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_sat_rnd_hh_s0; // "exagon. M2.mpy.sat.rnd.hh.s0" return Intrinsic::hexagon_M2_mpy_sat_rnd_hh_s0; // "exagon. M2.mpy.sat.rnd.hh.s0"
case '1': // 1 string to match. case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_sat_rnd_hh_s1; // "exagon. M2.mpy.sat.rnd.hh.s1" return Intrinsic::hexagon_M2_mpy_sat_rnd_hh_s1; // "exagon. M2.mpy.sat.rnd.hh.s1"
} }
break; break;
case 'l': // 2 strings to match. case 'l': // 2 strings to match.
if (NameR.substr(24, 2) != ".s") if (memcmp(NameR.data()+24, ".s", 2))
break; break;
switch (NameR[26]) { switch (NameR[26]) {
default: break; default: break;
case '0': // 1 string to match. case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_sat_rnd_hl_s0; // "exagon. M2.mpy.sat.rnd.hl.s0" return Intrinsic::hexagon_M2_mpy_sat_rnd_hl_s0; // "exagon. M2.mpy.sat.rnd.hl.s0"
case '1': // 1 string to match. case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_sat_rnd_hl_s1; // "exagon. M2.mpy.sat.rnd.hl.s1" return Intrinsic::hexagon_M2_mpy_sat_rnd_hl_s1; // "exagon. M2.mpy.sat.rnd.hl.s1"
} }
break; break;
} }
break; break;
case 'l': // 4 strings to match. case 'l': // 4 strings to match.
switch (NameR[23]) { switch (NameR[23]) {
default: break; default: break;
case 'h': // 2 strings to match. case 'h': // 2 strings to match.
if (NameR.substr(24, 2) != ".s") if (memcmp(NameR.data()+24, ".s", 2))
break; break;
switch (NameR[26]) { switch (NameR[26]) {
default: break; default: break;
case '0': // 1 string to match. case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_sat_rnd_lh_s0; // "exagon. M2.mpy.sat.rnd.lh.s0" return Intrinsic::hexagon_M2_mpy_sat_rnd_lh_s0; // "exagon. M2.mpy.sat.rnd.lh.s0"
case '1': // 1 string to match. case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_sat_rnd_lh_s1; // "exagon. M2.mpy.sat.rnd.lh.s1" return Intrinsic::hexagon_M2_mpy_sat_rnd_lh_s1; // "exagon. M2.mpy.sat.rnd.lh.s1"
} }
break; break;
case 'l': // 2 strings to match. case 'l': // 2 strings to match.
if (NameR.substr(24, 2) != ".s") if (memcmp(NameR.data()+24, ".s", 2))
break; break;
switch (NameR[26]) { switch (NameR[26]) {
default: break; default: break;
case '0': // 1 string to match. case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_sat_rnd_ll_s0; // "exagon. M2.mpy.sat.rnd.ll.s0" return Intrinsic::hexagon_M2_mpy_sat_rnd_ll_s0; // "exagon. M2.mpy.sat.rnd.ll.s0"
case '1': // 1 string to match. case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_sat_rnd_ll_s1; // "exagon. M2.mpy.sat.rnd.ll.s1" return Intrinsic::hexagon_M2_mpy_sat_rnd_ll_s1; // "exagon. M2.mpy.sat.rnd.ll.s1"
} }
break; break;
} }
break; break;
} }
break; break;
} }
break; break;
case 29: // 1 string to match.
if (memcmp(NameR.data()+0, "exagon.S5.vasrhrnd.goodsyntax", 29))
break;
return Intrinsic::hexagon_S5_vasrhrnd_goodsyntax; // "exagon.
S5.vasrhrnd.goodsyntax"
case 30: // 4 strings to match. case 30: // 4 strings to match.
if (NameR.substr(0, 18) != "exagon.S2.tableidx") if (memcmp(NameR.data()+0, "exagon.S2.tableidx", 18))
break; break;
switch (NameR[18]) { switch (NameR[18]) {
default: break; default: break;
case 'b': // 1 string to match. case 'b': // 1 string to match.
if (NameR.substr(19, 11) != ".goodsyntax") if (memcmp(NameR.data()+19, ".goodsyntax", 11))
break; break;
return Intrinsic::hexagon_S2_tableidxb_goodsyntax; // "exagon. S2.tableidxb.goodsyntax" return Intrinsic::hexagon_S2_tableidxb_goodsyntax; // "exagon. S2.tableidxb.goodsyntax"
case 'd': // 1 string to match. case 'd': // 1 string to match.
if (NameR.substr(19, 11) != ".goodsyntax") if (memcmp(NameR.data()+19, ".goodsyntax", 11))
break; break;
return Intrinsic::hexagon_S2_tableidxd_goodsyntax; // "exagon. S2.tableidxd.goodsyntax" return Intrinsic::hexagon_S2_tableidxd_goodsyntax; // "exagon. S2.tableidxd.goodsyntax"
case 'h': // 1 string to match. case 'h': // 1 string to match.
if (NameR.substr(19, 11) != ".goodsyntax") if (memcmp(NameR.data()+19, ".goodsyntax", 11))
break; break;
return Intrinsic::hexagon_S2_tableidxh_goodsyntax; // "exagon. S2.tableidxh.goodsyntax" return Intrinsic::hexagon_S2_tableidxh_goodsyntax; // "exagon. S2.tableidxh.goodsyntax"
case 'w': // 1 string to match. case 'w': // 1 string to match.
if (NameR.substr(19, 11) != ".goodsyntax") if (memcmp(NameR.data()+19, ".goodsyntax", 11))
break; break;
return Intrinsic::hexagon_S2_tableidxw_goodsyntax; // "exagon. S2.tableidxw.goodsyntax" return Intrinsic::hexagon_S2_tableidxw_goodsyntax; // "exagon. S2.tableidxw.goodsyntax"
} }
break; break;
case 32: // 1 string to match. case 32: // 2 strings to match.
if (NameR.substr(0, 32) != "exagon.S2.asr.i.r.rnd.goodsyntax") if (memcmp(NameR.data()+0, "exagon.S2.asr.i.", 16))
break;
switch (NameR[16]) {
default: break;
case 'p': // 1 string to match.
if (memcmp(NameR.data()+17, ".rnd.goodsyntax", 15))
break;
return Intrinsic::hexagon_S2_asr_i_p_rnd_goodsyntax; // "exagon.
S2.asr.i.p.rnd.goodsyntax"
case 'r': // 1 string to match.
if (memcmp(NameR.data()+17, ".rnd.goodsyntax", 15))
break;
return Intrinsic::hexagon_S2_asr_i_r_rnd_goodsyntax; // "exagon.
S2.asr.i.r.rnd.goodsyntax"
}
break;
case 35: // 1 string to match.
if (memcmp(NameR.data()+0, "exagon.S5.asrhub.rnd.sat.goodsyntax", 35)
)
break; break;
return Intrinsic::hexagon_S2_asr_i_r_rnd_goodsyntax; // "exagon. S2.asr.i.r.rnd.goodsyntax" return Intrinsic::hexagon_S5_asrhub_rnd_sat_goodsyntax; // "exagon. S5.asrhub.rnd.sat.goodsyntax"
} }
break; // end of 'h' case. break; // end of 'h' case.
case 'i': case 'i':
switch (NameR.size()) { switch (NameR.size()) {
default: break; default: break;
case 12: // 1 string to match. case 12: // 1 string to match.
if (NameR.substr(0, 12) != "nvariant.end") if (memcmp(NameR.data()+0, "nvariant.end", 12))
break; break;
return Intrinsic::invariant_end; // "nvariant.end" return Intrinsic::invariant_end; // "nvariant.end"
case 14: // 2 strings to match. case 14: // 2 strings to match.
if (NameR[0] != 'n') if (NameR[0] != 'n')
break; break;
switch (NameR[1]) { switch (NameR[1]) {
default: break; default: break;
case 'i': // 1 string to match. case 'i': // 1 string to match.
if (NameR.substr(2, 12) != "t.trampoline") if (memcmp(NameR.data()+2, "t.trampoline", 12))
break; break;
return Intrinsic::init_trampoline; // "nit.trampoline" return Intrinsic::init_trampoline; // "nit.trampoline"
case 'v': // 1 string to match. case 'v': // 1 string to match.
if (NameR.substr(2, 12) != "ariant.start") if (memcmp(NameR.data()+2, "ariant.start", 12))
break; break;
return Intrinsic::invariant_start; // "nvariant.start" return Intrinsic::invariant_start; // "nvariant.start"
} }
break; break;
} }
break; // end of 'i' case. break; // end of 'i' case.
case 'l': case 'l':
if (NameR.startswith("og.")) return Intrinsic::log; if (NameR.startswith("og.")) return Intrinsic::log;
if (NameR.startswith("og10.")) return Intrinsic::log10; if (NameR.startswith("og10.")) return Intrinsic::log10;
if (NameR.startswith("og2.")) return Intrinsic::log2; if (NameR.startswith("og2.")) return Intrinsic::log2;
switch (NameR.size()) { switch (NameR.size()) {
default: break; default: break;
case 6: // 1 string to match. case 6: // 1 string to match.
if (NameR.substr(0, 6) != "ongjmp") if (memcmp(NameR.data()+0, "ongjmp", 6))
break; break;
return Intrinsic::longjmp; // "ongjmp" return Intrinsic::longjmp; // "ongjmp"
case 11: // 1 string to match. case 11: // 1 string to match.
if (NameR.substr(0, 11) != "ifetime.end") if (memcmp(NameR.data()+0, "ifetime.end", 11))
break; break;
return Intrinsic::lifetime_end; // "ifetime.end" return Intrinsic::lifetime_end; // "ifetime.end"
case 13: // 1 string to match. case 13: // 1 string to match.
if (NameR.substr(0, 13) != "ifetime.start") if (memcmp(NameR.data()+0, "ifetime.start", 13))
break; break;
return Intrinsic::lifetime_start; // "ifetime.start" return Intrinsic::lifetime_start; // "ifetime.start"
} }
break; // end of 'l' case. break; // end of 'l' case.
case 'm': case 'm':
if (NameR.startswith("emcpy.")) return Intrinsic::memcpy; if (NameR.startswith("emcpy.")) return Intrinsic::memcpy;
if (NameR.startswith("emmove.")) return Intrinsic::memmove; if (NameR.startswith("emmove.")) return Intrinsic::memmove;
if (NameR.startswith("emset.")) return Intrinsic::memset; if (NameR.startswith("emset.")) return Intrinsic::memset;
break; // end of 'm' case.
case 'o':
if (NameR.startswith("bjectsize.")) return Intrinsic::objectsize;
break; // end of 'o' case.
case 'p':
if (NameR.startswith("ow.")) return Intrinsic::pow;
if (NameR.startswith("owi.")) return Intrinsic::powi;
if (NameR.startswith("tr.annotation.")) return Intrinsic::ptr_annotatio
n;
switch (NameR.size()) { switch (NameR.size()) {
default: break; default: break;
case 7: // 8 strings to match. case 7: // 2 strings to match.
switch (NameR[0]) { if (memcmp(NameR.data()+0, "ips.l", 5))
default: break;
case 'c': // 1 string to match.
if (NameR.substr(1, 6) != "marker")
break;
return Intrinsic::pcmarker; // "cmarker"
case 'p': // 6 strings to match.
if (NameR.substr(1, 2) != "c.")
break;
switch (NameR[3]) {
default: break;
case 'd': // 5 strings to match.
if (NameR.substr(4, 2) != "cb")
break;
switch (NameR[6]) {
default: break;
case 'a': // 1 string to match.
return Intrinsic::ppc_dcba; // "pc.dcba"
case 'f': // 1 string to match.
return Intrinsic::ppc_dcbf; // "pc.dcbf"
case 'i': // 1 string to match.
return Intrinsic::ppc_dcbi; // "pc.dcbi"
case 't': // 1 string to match.
return Intrinsic::ppc_dcbt; // "pc.dcbt"
case 'z': // 1 string to match.
return Intrinsic::ppc_dcbz; // "pc.dcbz"
}
break;
case 's': // 1 string to match.
if (NameR.substr(4, 3) != "ync")
break;
return Intrinsic::ppc_sync; // "pc.sync"
}
break;
case 'r': // 1 string to match.
if (NameR.substr(1, 6) != "efetch")
break;
return Intrinsic::prefetch; // "refetch"
}
break;
case 8: // 2 strings to match.
if (NameR.substr(0, 6) != "pc.dcb")
break; break;
switch (NameR[6]) { switch (NameR[5]) {
default: break; default: break;
case 's': // 1 string to match. case 'h': // 1 string to match.
if (NameR[7] != 't') if (NameR[6] != 'x')
break; break;
return Intrinsic::ppc_dcbst; // "pc.dcbst" return Intrinsic::mips_lhx; // "ips.lhx"
case 'z': // 1 string to match. case 'w': // 1 string to match.
if (NameR[7] != 'l') if (NameR[6] != 'x')
break; break;
return Intrinsic::ppc_dcbzl; // "pc.dcbzl" return Intrinsic::mips_lwx; // "ips.lwx"
} }
break; break;
case 9: // 1 string to match. case 8: // 6 strings to match.
if (NameR.substr(0, 9) != "pc.dcbtst") if (memcmp(NameR.data()+0, "ips.", 4))
break;
return Intrinsic::ppc_dcbtst; // "pc.dcbtst"
case 11: // 5 strings to match.
if (NameR.substr(0, 3) != "tx.")
break; break;
switch (NameR[3]) { switch (NameR[4]) {
default: break; default: break;
case 'b': // 1 string to match. case 'e': // 1 string to match.
if (NameR.substr(4, 7) != "ar.sync") if (memcmp(NameR.data()+5, "xtp", 3))
break; break;
return Intrinsic::ptx_bar_sync; // "tx.bar.sync" return Intrinsic::mips_extp; // "ips.extp"
case 'r': // 4 strings to match. case 'i': // 1 string to match.
if (NameR.substr(4, 6) != "ead.pm") if (memcmp(NameR.data()+5, "nsv", 3))
break; break;
switch (NameR[10]) { return Intrinsic::mips_insv; // "ips.insv"
case 'l': // 1 string to match.
if (memcmp(NameR.data()+5, "bux", 3))
break;
return Intrinsic::mips_lbux; // "ips.lbux"
case 'm': // 3 strings to match.
switch (NameR[5]) {
default: break; default: break;
case '0': // 1 string to match. case 'a': // 1 string to match.
return Intrinsic::ptx_read_pm0; // "tx.read.pm0" if (memcmp(NameR.data()+6, "dd", 2))
case '1': // 1 string to match. break;
return Intrinsic::ptx_read_pm1; // "tx.read.pm1" return Intrinsic::mips_madd; // "ips.madd"
case '2': // 1 string to match. case 's': // 1 string to match.
return Intrinsic::ptx_read_pm2; // "tx.read.pm2" if (memcmp(NameR.data()+6, "ub", 2))
case '3': // 1 string to match. break;
return Intrinsic::ptx_read_pm3; // "tx.read.pm3" return Intrinsic::mips_msub; // "ips.msub"
case 'u': // 1 string to match.
if (memcmp(NameR.data()+6, "lt", 2))
break;
return Intrinsic::mips_mult; // "ips.mult"
} }
break; break;
} }
break; break;
case 12: // 1 string to match. case 9: // 8 strings to match.
if (NameR.substr(0, 12) != "tx.read.smid") if (memcmp(NameR.data()+0, "ips.", 4))
break;
return Intrinsic::ptx_read_smid; // "tx.read.smid"
case 13: // 6 strings to match.
if (NameR.substr(0, 8) != "tx.read.")
break; break;
switch (NameR[8]) { switch (NameR[4]) {
default: break; default: break;
case 'c': // 1 string to match. case 'a': // 2 strings to match.
if (NameR.substr(9, 4) != "lock") if (memcmp(NameR.data()+5, "dd", 2))
break;
return Intrinsic::ptx_read_clock; // "tx.read.clock"
case 'n': // 1 string to match.
if (NameR.substr(9, 4) != "smid")
break;
return Intrinsic::ptx_read_nsmid; // "tx.read.nsmid"
case 't': // 4 strings to match.
if (NameR.substr(9, 3) != "id.")
break; break;
switch (NameR[12]) { switch (NameR[7]) {
default: break; default: break;
case 's': // 1 string to match.
if (NameR[8] != 'c')
break;
return Intrinsic::mips_addsc; // "ips.addsc"
case 'w': // 1 string to match. case 'w': // 1 string to match.
return Intrinsic::ptx_read_tid_w; // "tx.read.tid.w" if (NameR[8] != 'c')
case 'x': // 1 string to match. break;
return Intrinsic::ptx_read_tid_x; // "tx.read.tid.x" return Intrinsic::mips_addwc; // "ips.addwc"
case 'y': // 1 string to match. }
return Intrinsic::ptx_read_tid_y; // "tx.read.tid.y" break;
case 'z': // 1 string to match. case 'm': // 3 strings to match.
return Intrinsic::ptx_read_tid_z; // "tx.read.tid.z" switch (NameR[5]) {
default: break;
case 'a': // 1 string to match.
if (memcmp(NameR.data()+6, "ddu", 3))
break;
return Intrinsic::mips_maddu; // "ips.maddu"
case 's': // 1 string to match.
if (memcmp(NameR.data()+6, "ubu", 3))
break;
return Intrinsic::mips_msubu; // "ips.msubu"
case 'u': // 1 string to match.
if (memcmp(NameR.data()+6, "ltu", 3))
break;
return Intrinsic::mips_multu; // "ips.multu"
} }
break; break;
case 'r': // 1 string to match.
if (memcmp(NameR.data()+5, "ddsp", 4))
break;
return Intrinsic::mips_rddsp; // "ips.rddsp"
case 's': // 1 string to match.
if (memcmp(NameR.data()+5, "hilo", 4))
break;
return Intrinsic::mips_shilo; // "ips.shilo"
case 'w': // 1 string to match.
if (memcmp(NameR.data()+5, "rdsp", 4))
break;
return Intrinsic::mips_wrdsp; // "ips.wrdsp"
} }
break; break;
case 14: // 12 strings to match. case 10: // 8 strings to match.
switch (NameR[0]) { if (memcmp(NameR.data()+0, "ips.", 4))
break;
switch (NameR[4]) {
default: break; default: break;
case 'p': // 5 strings to match. case 'a': // 1 string to match.
if (NameR.substr(1, 10) != "c.altivec.") if (memcmp(NameR.data()+5, "ppend", 5))
break; break;
switch (NameR[11]) { return Intrinsic::mips_append; // "ips.append"
case 'b': // 2 strings to match.
switch (NameR[5]) {
default: break; default: break;
case 'd': // 2 strings to match. case 'a': // 1 string to match.
if (NameR[12] != 's') if (memcmp(NameR.data()+6, "lign", 4))
break; break;
switch (NameR[13]) { return Intrinsic::mips_balign; // "ips.balign"
default: break; case 'i': // 1 string to match.
case 's': // 1 string to match. if (memcmp(NameR.data()+6, "trev", 4))
return Intrinsic::ppc_altivec_dss; // "pc.altivec.dss" break;
case 't': // 1 string to match. return Intrinsic::mips_bitrev; // "ips.bitrev"
return Intrinsic::ppc_altivec_dst; // "pc.altivec.dst" }
} break;
case 'e': // 2 strings to match.
if (memcmp(NameR.data()+5, "xt", 2))
break; break;
case 'l': // 1 string to match. switch (NameR[7]) {
if (NameR.substr(12, 2) != "vx") default: break;
case 'p': // 1 string to match.
if (memcmp(NameR.data()+8, "dp", 2))
break; break;
return Intrinsic::ppc_altivec_lvx; // "pc.altivec.lvx" return Intrinsic::mips_extpdp; // "ips.extpdp"
case 'v': // 2 strings to match. case 'r': // 1 string to match.
if (NameR[12] != 's') if (memcmp(NameR.data()+8, ".w", 2))
break; break;
switch (NameR[13]) { return Intrinsic::mips_extr_w; // "ips.extr.w"
default: break;
case 'l': // 1 string to match.
return Intrinsic::ppc_altivec_vsl; // "pc.altivec.vsl"
case 'r': // 1 string to match.
return Intrinsic::ppc_altivec_vsr; // "pc.altivec.vsr"
}
break;
} }
break; break;
case 't': // 7 strings to match. case 'm': // 3 strings to match.
if (NameR.substr(1, 7) != "x.read.") switch (NameR[5]) {
break;
switch (NameR[8]) {
default: break; default: break;
case 'g': // 1 string to match. case 'o': // 1 string to match.
if (NameR.substr(9, 5) != "ridid") if (memcmp(NameR.data()+6, "dsub", 4))
break; break;
return Intrinsic::ptx_read_gridid; // "tx.read.gridid" return Intrinsic::mips_modsub; // "ips.modsub"
case 'l': // 1 string to match. case 't': // 1 string to match.
if (NameR.substr(9, 5) != "aneid") if (memcmp(NameR.data()+6, "hlip", 4))
break; break;
return Intrinsic::ptx_read_laneid; // "tx.read.laneid" return Intrinsic::mips_mthlip; // "ips.mthlip"
case 'n': // 4 strings to match. case 'u': // 1 string to match.
if (NameR.substr(9, 4) != "tid.") if (memcmp(NameR.data()+6, "l.ph", 4))
break; break;
switch (NameR[13]) { return Intrinsic::mips_mul_ph; // "ips.mul.ph"
default: break;
case 'w': // 1 string to match.
return Intrinsic::ptx_read_ntid_w; // "tx.read.ntid.w"
case 'x': // 1 string to match.
return Intrinsic::ptx_read_ntid_x; // "tx.read.ntid.x"
case 'y': // 1 string to match.
return Intrinsic::ptx_read_ntid_y; // "tx.read.ntid.y"
case 'z': // 1 string to match.
return Intrinsic::ptx_read_ntid_z; // "tx.read.ntid.z"
}
break;
case 'w': // 1 string to match.
if (NameR.substr(9, 5) != "arpid")
break;
return Intrinsic::ptx_read_warpid; // "tx.read.warpid"
} }
break; break;
} }
break; break;
case 15: // 23 strings to match. case 11: // 19 strings to match.
switch (NameR[0]) { if (memcmp(NameR.data()+0, "ips.", 4))
break;
switch (NameR[4]) {
default: break; default: break;
case 'p': // 17 strings to match. case 'a': // 4 strings to match.
if (NameR.substr(1, 10) != "c.altivec.") if (memcmp(NameR.data()+5, "dd", 2))
break; break;
switch (NameR[11]) { switch (NameR[7]) {
default: break; default: break;
case 'd': // 1 string to match. case 'q': // 2 strings to match.
if (NameR.substr(12, 3) != "stt") switch (NameR[8]) {
break;
return Intrinsic::ppc_altivec_dstt; // "pc.altivec.dstt"
case 'l': // 3 strings to match.
if (NameR[12] != 'v')
break;
switch (NameR[13]) {
default: break; default: break;
case 's': // 2 strings to match. case '.': // 1 string to match.
switch (NameR[14]) { if (memcmp(NameR.data()+9, "ph", 2))
default: break;
case 'l': // 1 string to match.
return Intrinsic::ppc_altivec_lvsl; // "pc.altivec.lvsl
"
case 'r': // 1 string to match.
return Intrinsic::ppc_altivec_lvsr; // "pc.altivec.lvsr
"
}
break;
case 'x': // 1 string to match.
if (NameR[14] != 'l')
break; break;
return Intrinsic::ppc_altivec_lvxl; // "pc.altivec.lvxl return Intrinsic::mips_addq_ph; // "ips.addq.ph"
" case 'h': // 1 string to match.
if (memcmp(NameR.data()+9, ".w", 2))
break;
return Intrinsic::mips_addqh_w; // "ips.addqh.w"
} }
break; break;
case 's': // 1 string to match. case 'u': // 2 strings to match.
if (NameR.substr(12, 3) != "tvx") if (NameR[8] != '.')
break; break;
return Intrinsic::ppc_altivec_stvx; // "pc.altivec.stvx" switch (NameR[9]) {
case 'v': // 12 strings to match.
switch (NameR[12]) {
default: break; default: break;
case 'r': // 3 strings to match. case 'p': // 1 string to match.
if (NameR[13] != 'l') if (NameR[10] != 'h')
break;
switch (NameR[14]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::ppc_altivec_vrlb; // "pc.altivec.vrlb
"
case 'h': // 1 string to match.
return Intrinsic::ppc_altivec_vrlh; // "pc.altivec.vrlh
"
case 'w': // 1 string to match.
return Intrinsic::ppc_altivec_vrlw; // "pc.altivec.vrlw
"
}
break;
case 's': // 9 strings to match.
switch (NameR[13]) {
default: break;
case 'e': // 1 string to match.
if (NameR[14] != 'l')
break;
return Intrinsic::ppc_altivec_vsel; // "pc.altivec.vsel
"
case 'l': // 4 strings to match.
switch (NameR[14]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::ppc_altivec_vslb; // "pc.altivec.vslb
"
case 'h': // 1 string to match.
return Intrinsic::ppc_altivec_vslh; // "pc.altivec.vslh
"
case 'o': // 1 string to match.
return Intrinsic::ppc_altivec_vslo; // "pc.altivec.vslo
"
case 'w': // 1 string to match.
return Intrinsic::ppc_altivec_vslw; // "pc.altivec.vslw
"
}
break; break;
case 'r': // 4 strings to match. return Intrinsic::mips_addu_ph; // "ips.addu.ph"
switch (NameR[14]) { case 'q': // 1 string to match.
default: break; if (NameR[10] != 'b')
case 'b': // 1 string to match.
return Intrinsic::ppc_altivec_vsrb; // "pc.altivec.vsrb
"
case 'h': // 1 string to match.
return Intrinsic::ppc_altivec_vsrh; // "pc.altivec.vsrh
"
case 'o': // 1 string to match.
return Intrinsic::ppc_altivec_vsro; // "pc.altivec.vsro
"
case 'w': // 1 string to match.
return Intrinsic::ppc_altivec_vsrw; // "pc.altivec.vsrw
"
}
break; break;
} return Intrinsic::mips_addu_qb; // "ips.addu.qb"
break;
} }
break; break;
} }
break; break;
case 't': // 6 strings to match. case 'p': // 3 strings to match.
if (NameR.substr(1, 7) != "x.read.") switch (NameR[5]) {
break;
switch (NameR[8]) {
default: break; default: break;
case 'c': // 5 strings to match. case 'i': // 2 strings to match.
if (memcmp(NameR.data()+6, "ck.", 3))
break;
switch (NameR[9]) { switch (NameR[9]) {
default: break; default: break;
case 'l': // 1 string to match. case 'p': // 1 string to match.
if (NameR.substr(10, 5) != "ock64") if (NameR[10] != 'h')
break; break;
return Intrinsic::ptx_read_clock64; // "tx.read.clock64 return Intrinsic::mips_pick_ph; // "ips.pick.ph"
" case 'q': // 1 string to match.
case 't': // 4 strings to match. if (NameR[10] != 'b')
if (NameR.substr(10, 4) != "aid.")
break; break;
switch (NameR[14]) { return Intrinsic::mips_pick_qb; // "ips.pick.qb"
default: break;
case 'w': // 1 string to match.
return Intrinsic::ptx_read_ctaid_w; // "tx.read.ctaid.w
"
case 'x': // 1 string to match.
return Intrinsic::ptx_read_ctaid_x; // "tx.read.ctaid.x
"
case 'y': // 1 string to match.
return Intrinsic::ptx_read_ctaid_y; // "tx.read.ctaid.y
"
case 'z': // 1 string to match.
return Intrinsic::ptx_read_ctaid_z; // "tx.read.ctaid.z
"
}
break;
} }
break; break;
case 'n': // 1 string to match. case 'r': // 1 string to match.
if (NameR.substr(9, 6) != "warpid") if (memcmp(NameR.data()+6, "epend", 5))
break; break;
return Intrinsic::ptx_read_nwarpid; // "tx.read.nwarpid" return Intrinsic::mips_prepend; // "ips.prepend"
} }
break; break;
} case 'r': // 2 strings to match.
break; if (memcmp(NameR.data()+5, "epl.", 4))
case 16: // 21 strings to match.
switch (NameR[0]) {
default: break;
case 'p': // 17 strings to match.
if (NameR.substr(1, 10) != "c.altivec.")
break; break;
switch (NameR[11]) { switch (NameR[9]) {
default: break; default: break;
case 'd': // 1 string to match. case 'p': // 1 string to match.
if (NameR.substr(12, 4) != "stst") if (NameR[10] != 'h')
break;
return Intrinsic::ppc_altivec_dstst; // "pc.altivec.dstst"
case 'l': // 3 strings to match.
if (NameR.substr(12, 2) != "ve")
break; break;
switch (NameR[14]) { return Intrinsic::mips_repl_ph; // "ips.repl.ph"
default: break; case 'q': // 1 string to match.
case 'b': // 1 string to match. if (NameR[10] != 'b')
if (NameR[15] != 'x')
break;
return Intrinsic::ppc_altivec_lvebx; // "pc.altivec.lveb
x"
case 'h': // 1 string to match.
if (NameR[15] != 'x')
break;
return Intrinsic::ppc_altivec_lvehx; // "pc.altivec.lveh
x"
case 'w': // 1 string to match.
if (NameR[15] != 'x')
break;
return Intrinsic::ppc_altivec_lvewx; // "pc.altivec.lvew
x"
}
break;
case 's': // 1 string to match.
if (NameR.substr(12, 4) != "tvxl")
break; break;
return Intrinsic::ppc_altivec_stvxl; // "pc.altivec.stvxl" return Intrinsic::mips_repl_qb; // "ips.repl.qb"
case 'v': // 12 strings to match. }
switch (NameR[12]) { break;
case 's': // 10 strings to match.
switch (NameR[5]) {
default: break;
case 'h': // 6 strings to match.
switch (NameR[6]) {
default: break; default: break;
case 'c': // 2 strings to match. case 'l': // 2 strings to match.
if (NameR[13] != 'f') if (memcmp(NameR.data()+7, "l.", 2))
break; break;
switch (NameR[14]) { switch (NameR[9]) {
default: break; default: break;
case 's': // 1 string to match. case 'p': // 1 string to match.
if (NameR[15] != 'x') if (NameR[10] != 'h')
break; break;
return Intrinsic::ppc_altivec_vcfsx; // "pc.altivec.vcfs return Intrinsic::mips_shll_ph; // "ips.shll.ph"
x" case 'q': // 1 string to match.
case 'u': // 1 string to match. if (NameR[10] != 'b')
if (NameR[15] != 'x')
break; break;
return Intrinsic::ppc_altivec_vcfux; // "pc.altivec.vcfu x" return Intrinsic::mips_shll_qb; // "ips.shll.qb"
} }
break; break;
case 'p': // 2 strings to match. case 'r': // 4 strings to match.
switch (NameR[13]) { switch (NameR[7]) {
default: break; default: break;
case 'e': // 1 string to match. case 'a': // 2 strings to match.
if (NameR.substr(14, 2) != "rm") if (NameR[8] != '.')
break; break;
return Intrinsic::ppc_altivec_vperm; // "pc.altivec.vper switch (NameR[9]) {
m" default: break;
case 'k': // 1 string to match. case 'p': // 1 string to match.
if (NameR.substr(14, 2) != "px") if (NameR[10] != 'h')
break;
return Intrinsic::mips_shra_ph; // "ips.shra.ph"
case 'q': // 1 string to match.
if (NameR[10] != 'b')
break;
return Intrinsic::mips_shra_qb; // "ips.shra.qb"
}
break;
case 'l': // 2 strings to match.
if (NameR[8] != '.')
break; break;
return Intrinsic::ppc_altivec_vpkpx; // "pc.altivec.vpkp switch (NameR[9]) {
x" default: break;
case 'p': // 1 string to match.
if (NameR[10] != 'h')
break;
return Intrinsic::mips_shrl_ph; // "ips.shrl.ph"
case 'q': // 1 string to match.
if (NameR[10] != 'b')
break;
return Intrinsic::mips_shrl_qb; // "ips.shrl.qb"
}
break;
} }
break; break;
case 'r': // 5 strings to match. }
switch (NameR[13]) { break;
case 'u': // 4 strings to match.
if (NameR[6] != 'b')
break;
switch (NameR[7]) {
default: break;
case 'q': // 2 strings to match.
switch (NameR[8]) {
default: break; default: break;
case 'e': // 1 string to match. case '.': // 1 string to match.
if (NameR.substr(14, 2) != "fp") if (memcmp(NameR.data()+9, "ph", 2))
break; break;
return Intrinsic::ppc_altivec_vrefp; // "pc.altivec.vref return Intrinsic::mips_subq_ph; // "ips.subq.ph"
p" case 'h': // 1 string to match.
case 'f': // 4 strings to match. if (memcmp(NameR.data()+9, ".w", 2))
if (NameR[14] != 'i')
break; break;
switch (NameR[15]) { return Intrinsic::mips_subqh_w; // "ips.subqh.w"
default: break;
case 'm': // 1 string to match.
return Intrinsic::ppc_altivec_vrfim; // "pc.altivec.vrfi
m"
case 'n': // 1 string to match.
return Intrinsic::ppc_altivec_vrfin; // "pc.altivec.vrfi
n"
case 'p': // 1 string to match.
return Intrinsic::ppc_altivec_vrfip; // "pc.altivec.vrfi
p"
case 'z': // 1 string to match.
return Intrinsic::ppc_altivec_vrfiz; // "pc.altivec.vrfi
z"
}
break;
} }
break; break;
case 's': // 3 strings to match. case 'u': // 2 strings to match.
if (NameR.substr(13, 2) != "ra") if (NameR[8] != '.')
break; break;
switch (NameR[15]) { switch (NameR[9]) {
default: break; default: break;
case 'b': // 1 string to match. case 'p': // 1 string to match.
return Intrinsic::ppc_altivec_vsrab; // "pc.altivec.vsra if (NameR[10] != 'h')
b" break;
case 'h': // 1 string to match. return Intrinsic::mips_subu_ph; // "ips.subu.ph"
return Intrinsic::ppc_altivec_vsrah; // "pc.altivec.vsra case 'q': // 1 string to match.
h" if (NameR[10] != 'b')
case 'w': // 1 string to match. break;
return Intrinsic::ppc_altivec_vsraw; // "pc.altivec.vsra return Intrinsic::mips_subu_qb; // "ips.subu.qb"
w"
} }
break; break;
} }
break; break;
} }
break; break;
case 't': // 4 strings to match.
if (NameR.substr(1, 14) != "x.read.nctaid.")
break;
switch (NameR[15]) {
default: break;
case 'w': // 1 string to match.
return Intrinsic::ptx_read_nctaid_w; // "tx.read.nctaid.w"
case 'x': // 1 string to match.
return Intrinsic::ptx_read_nctaid_x; // "tx.read.nctaid.x"
case 'y': // 1 string to match.
return Intrinsic::ptx_read_nctaid_y; // "tx.read.nctaid.y"
case 'z': // 1 string to match.
return Intrinsic::ptx_read_nctaid_z; // "tx.read.nctaid.z"
}
break;
} }
break; break;
case 17: // 29 strings to match. case 12: // 16 strings to match.
if (NameR.substr(0, 11) != "pc.altivec.") if (memcmp(NameR.data()+0, "ips.", 4))
break; break;
switch (NameR[11]) { switch (NameR[4]) {
default: break; default: break;
case 'a': // 4 strings to match.
switch (NameR[5]) {
default: break;
case 'b': // 1 string to match.
if (memcmp(NameR.data()+6, "sq.s.w", 6))
break;
return Intrinsic::mips_absq_s_w; // "ips.absq.s.w"
case 'd': // 3 strings to match.
if (NameR[6] != 'd')
break;
switch (NameR[7]) {
default: break;
case 'q': // 2 strings to match.
switch (NameR[8]) {
default: break;
case '.': // 1 string to match.
if (memcmp(NameR.data()+9, "s.w", 3))
break;
return Intrinsic::mips_addq_s_w; // "ips.addq.s.w"
case 'h': // 1 string to match.
if (memcmp(NameR.data()+9, ".ph", 3))
break;
return Intrinsic::mips_addqh_ph; // "ips.addqh.ph"
}
break;
case 'u': // 1 string to match.
if (memcmp(NameR.data()+8, "h.qb", 4))
break;
return Intrinsic::mips_adduh_qb; // "ips.adduh.qb"
}
break;
}
break;
case 'b': // 1 string to match.
if (memcmp(NameR.data()+5, "posge32", 7))
break;
return Intrinsic::mips_bposge32; // "ips.bposge32"
case 'd': // 2 strings to match. case 'd': // 2 strings to match.
if (NameR[12] != 's') if (NameR[5] != 'p')
break; break;
switch (NameR[13]) { switch (NameR[6]) {
default: break; default: break;
case 's': // 1 string to match. case 'a': // 1 string to match.
if (NameR.substr(14, 3) != "all") if (memcmp(NameR.data()+7, ".w.ph", 5))
break; break;
return Intrinsic::ppc_altivec_dssall; // "pc.altivec.dssa return Intrinsic::mips_dpa_w_ph; // "ips.dpa.w.ph"
ll" case 's': // 1 string to match.
case 't': // 1 string to match. if (memcmp(NameR.data()+7, ".w.ph", 5))
if (NameR.substr(14, 3) != "stt")
break; break;
return Intrinsic::ppc_altivec_dststt; // "pc.altivec.dsts tt" return Intrinsic::mips_dps_w_ph; // "ips.dps.w.ph"
} }
break; break;
case 'm': // 2 strings to match. case 'e': // 2 strings to match.
switch (NameR[12]) { if (memcmp(NameR.data()+5, "xtr.", 4))
break;
switch (NameR[9]) {
default: break; default: break;
case 'f': // 1 string to match. case 'r': // 1 string to match.
if (NameR.substr(13, 4) != "vscr") if (memcmp(NameR.data()+10, ".w", 2))
break; break;
return Intrinsic::ppc_altivec_mfvscr; // "pc.altivec.mfvs return Intrinsic::mips_extr_r_w; // "ips.extr.r.w"
cr" case 's': // 1 string to match.
case 't': // 1 string to match. if (memcmp(NameR.data()+10, ".h", 2))
if (NameR.substr(13, 4) != "vscr")
break; break;
return Intrinsic::ppc_altivec_mtvscr; // "pc.altivec.mtvs cr" return Intrinsic::mips_extr_s_h; // "ips.extr.s.h"
} }
break; break;
case 's': // 3 strings to match. case 'm': // 2 strings to match.
if (NameR.substr(12, 3) != "tve") if (memcmp(NameR.data()+5, "ul", 2))
break; break;
switch (NameR[15]) { switch (NameR[7]) {
default: break; default: break;
case 'b': // 1 string to match. case '.': // 1 string to match.
if (NameR[16] != 'x') if (memcmp(NameR.data()+8, "s.ph", 4))
break;
return Intrinsic::ppc_altivec_stvebx; // "pc.altivec.stve
bx"
case 'h': // 1 string to match.
if (NameR[16] != 'x')
break; break;
return Intrinsic::ppc_altivec_stvehx; // "pc.altivec.stve return Intrinsic::mips_mul_s_ph; // "ips.mul.s.ph"
hx" case 'q': // 1 string to match.
case 'w': // 1 string to match. if (memcmp(NameR.data()+8, ".s.w", 4))
if (NameR[16] != 'x')
break; break;
return Intrinsic::ppc_altivec_stvewx; // "pc.altivec.stve wx" return Intrinsic::mips_mulq_s_w; // "ips.mulq.s.w"
} }
break; break;
case 'v': // 22 strings to match. case 's': // 5 strings to match.
switch (NameR[12]) { switch (NameR[5]) {
default: break; default: break;
case 'a': // 6 strings to match. case 'h': // 2 strings to match.
if (NameR.substr(13, 2) != "vg") switch (NameR[6]) {
break;
switch (NameR[15]) {
default: break; default: break;
case 's': // 3 strings to match. case 'l': // 1 string to match.
switch (NameR[16]) { if (memcmp(NameR.data()+7, "l.s.w", 5))
default: break; break;
case 'b': // 1 string to match. return Intrinsic::mips_shll_s_w; // "ips.shll.s.w"
return Intrinsic::ppc_altivec_vavgsb; // "pc.altivec.vavg case 'r': // 1 string to match.
sb" if (memcmp(NameR.data()+7, "a.r.w", 5))
case 'h': // 1 string to match. break;
return Intrinsic::ppc_altivec_vavgsh; // "pc.altivec.vavg return Intrinsic::mips_shra_r_w; // "ips.shra.r.w"
sh" }
case 'w': // 1 string to match. break;
return Intrinsic::ppc_altivec_vavgsw; // "pc.altivec.vavg case 'u': // 3 strings to match.
sw" if (NameR[6] != 'b')
}
break; break;
case 'u': // 3 strings to match. switch (NameR[7]) {
switch (NameR[16]) { default: break;
case 'q': // 2 strings to match.
switch (NameR[8]) {
default: break; default: break;
case 'b': // 1 string to match. case '.': // 1 string to match.
return Intrinsic::ppc_altivec_vavgub; // "pc.altivec.vavg if (memcmp(NameR.data()+9, "s.w", 3))
ub" break;
return Intrinsic::mips_subq_s_w; // "ips.subq.s.w"
case 'h': // 1 string to match. case 'h': // 1 string to match.
return Intrinsic::ppc_altivec_vavguh; // "pc.altivec.vavg if (memcmp(NameR.data()+9, ".ph", 3))
uh" break;
case 'w': // 1 string to match. return Intrinsic::mips_subqh_ph; // "ips.subqh.ph"
return Intrinsic::ppc_altivec_vavguw; // "pc.altivec.vavg
uw"
} }
break; break;
case 'u': // 1 string to match.
if (memcmp(NameR.data()+8, "h.qb", 4))
break;
return Intrinsic::mips_subuh_qb; // "ips.subuh.qb"
} }
break; break;
case 'c': // 2 strings to match. }
if (NameR[13] != 't') break;
}
break;
case 13: // 22 strings to match.
if (memcmp(NameR.data()+0, "ips.", 4))
break;
switch (NameR[4]) {
default: break;
case 'a': // 6 strings to match.
switch (NameR[5]) {
default: break;
case 'b': // 2 strings to match.
if (memcmp(NameR.data()+6, "sq.s.", 5))
break; break;
switch (NameR[14]) { switch (NameR[11]) {
default: break; default: break;
case 's': // 1 string to match. case 'p': // 1 string to match.
if (NameR.substr(15, 2) != "xs") if (NameR[12] != 'h')
break; break;
return Intrinsic::ppc_altivec_vctsxs; // "pc.altivec.vcts return Intrinsic::mips_absq_s_ph; // "ips.absq.s.ph"
xs" case 'q': // 1 string to match.
case 'u': // 1 string to match. if (NameR[12] != 'b')
if (NameR.substr(15, 2) != "xs")
break; break;
return Intrinsic::ppc_altivec_vctuxs; // "pc.altivec.vctu xs" return Intrinsic::mips_absq_s_qb; // "ips.absq.s.qb"
} }
break; break;
case 'm': // 14 strings to match. case 'd': // 4 strings to match.
switch (NameR[13]) { if (NameR[6] != 'd')
break;
switch (NameR[7]) {
default: break; default: break;
case 'a': // 7 strings to match. case 'q': // 2 strings to match.
if (NameR[14] != 'x') switch (NameR[8]) {
break;
switch (NameR[15]) {
default: break; default: break;
case 'f': // 1 string to match. case '.': // 1 string to match.
if (NameR[16] != 'p') if (memcmp(NameR.data()+9, "s.ph", 4))
break; break;
return Intrinsic::ppc_altivec_vmaxfp; // "pc.altivec.vmax return Intrinsic::mips_addq_s_ph; // "ips.addq.s.ph"
fp" case 'h': // 1 string to match.
case 's': // 3 strings to match. if (memcmp(NameR.data()+9, ".r.w", 4))
switch (NameR[16]) { break;
default: break; return Intrinsic::mips_addqh_r_w; // "ips.addqh.r.w"
case 'b': // 1 string to match.
return Intrinsic::ppc_altivec_vmaxsb; // "pc.altivec.vmax
sb"
case 'h': // 1 string to match.
return Intrinsic::ppc_altivec_vmaxsh; // "pc.altivec.vmax
sh"
case 'w': // 1 string to match.
return Intrinsic::ppc_altivec_vmaxsw; // "pc.altivec.vmax
sw"
}
break;
case 'u': // 3 strings to match.
switch (NameR[16]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::ppc_altivec_vmaxub; // "pc.altivec.vmax
ub"
case 'h': // 1 string to match.
return Intrinsic::ppc_altivec_vmaxuh; // "pc.altivec.vmax
uh"
case 'w': // 1 string to match.
return Intrinsic::ppc_altivec_vmaxuw; // "pc.altivec.vmax
uw"
}
break;
} }
break; break;
case 'i': // 7 strings to match. case 'u': // 2 strings to match.
if (NameR[14] != 'n') if (memcmp(NameR.data()+8, ".s.", 3))
break; break;
switch (NameR[15]) { switch (NameR[11]) {
default: break; default: break;
case 'f': // 1 string to match. case 'p': // 1 string to match.
if (NameR[16] != 'p') if (NameR[12] != 'h')
break; break;
return Intrinsic::ppc_altivec_vminfp; // "pc.altivec.vmin return Intrinsic::mips_addu_s_ph; // "ips.addu.s.ph"
fp" case 'q': // 1 string to match.
case 's': // 3 strings to match. if (NameR[12] != 'b')
switch (NameR[16]) { break;
default: break; return Intrinsic::mips_addu_s_qb; // "ips.addu.s.qb"
case 'b': // 1 string to match.
return Intrinsic::ppc_altivec_vminsb; // "pc.altivec.vmin
sb"
case 'h': // 1 string to match.
return Intrinsic::ppc_altivec_vminsh; // "pc.altivec.vmin
sh"
case 'w': // 1 string to match.
return Intrinsic::ppc_altivec_vminsw; // "pc.altivec.vmin
sw"
}
break;
case 'u': // 3 strings to match.
switch (NameR[16]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::ppc_altivec_vminub; // "pc.altivec.vmin
ub"
case 'h': // 1 string to match.
return Intrinsic::ppc_altivec_vminuh; // "pc.altivec.vmin
uh"
case 'w': // 1 string to match.
return Intrinsic::ppc_altivec_vminuw; // "pc.altivec.vmin
uw"
}
break;
} }
break; break;
} }
break; break;
} }
break; break;
} case 'c': // 3 strings to match.
break; if (memcmp(NameR.data()+5, "mp.", 3))
case 18: // 38 strings to match.
if (NameR.substr(0, 12) != "pc.altivec.v")
break;
switch (NameR[12]) {
default: break;
case 'a': // 7 strings to match.
if (NameR.substr(13, 2) != "dd")
break; break;
switch (NameR[15]) { switch (NameR[8]) {
default: break; default: break;
case 'c': // 1 string to match. case 'e': // 1 string to match.
if (NameR.substr(16, 2) != "uw") if (memcmp(NameR.data()+9, "q.ph", 4))
break; break;
return Intrinsic::ppc_altivec_vaddcuw; // "pc.altivec.vadd return Intrinsic::mips_cmp_eq_ph; // "ips.cmp.eq.ph"
cuw" case 'l': // 2 strings to match.
case 's': // 3 strings to match. switch (NameR[9]) {
switch (NameR[16]) {
default: break;
case 'b': // 1 string to match.
if (NameR[17] != 's')
break;
return Intrinsic::ppc_altivec_vaddsbs; // "pc.altivec.vadd
sbs"
case 'h': // 1 string to match.
if (NameR[17] != 's')
break;
return Intrinsic::ppc_altivec_vaddshs; // "pc.altivec.vadd
shs"
case 'w': // 1 string to match.
if (NameR[17] != 's')
break;
return Intrinsic::ppc_altivec_vaddsws; // "pc.altivec.vadd
sws"
}
break;
case 'u': // 3 strings to match.
switch (NameR[16]) {
default: break; default: break;
case 'b': // 1 string to match. case 'e': // 1 string to match.
if (NameR[17] != 's') if (memcmp(NameR.data()+10, ".ph", 3))
break;
return Intrinsic::ppc_altivec_vaddubs; // "pc.altivec.vadd
ubs"
case 'h': // 1 string to match.
if (NameR[17] != 's')
break; break;
return Intrinsic::ppc_altivec_vadduhs; // "pc.altivec.vadd return Intrinsic::mips_cmp_le_ph; // "ips.cmp.le.ph"
uhs" case 't': // 1 string to match.
case 'w': // 1 string to match. if (memcmp(NameR.data()+10, ".ph", 3))
if (NameR[17] != 's')
break; break;
return Intrinsic::ppc_altivec_vadduws; // "pc.altivec.vadd uws" return Intrinsic::mips_cmp_lt_ph; // "ips.cmp.lt.ph"
} }
break; break;
} }
break; break;
case 'c': // 1 string to match. case 'd': // 2 strings to match.
if (NameR.substr(13, 5) != "mpbfp") if (NameR[5] != 'p')
break; break;
return Intrinsic::ppc_altivec_vcmpbfp; // "pc.altivec.vcmpbfp" switch (NameR[6]) {
case 'l': // 1 string to match.
if (NameR.substr(13, 5) != "ogefp")
break;
return Intrinsic::ppc_altivec_vlogefp; // "pc.altivec.vlogefp"
case 'm': // 9 strings to match.
switch (NameR[13]) {
default: break; default: break;
case 'a': // 1 string to match. case 'a': // 1 string to match.
if (NameR.substr(14, 4) != "ddfp") if (memcmp(NameR.data()+7, "x.w.ph", 6))
break; break;
return Intrinsic::ppc_altivec_vmaddfp; // "pc.altivec.vmad return Intrinsic::mips_dpax_w_ph; // "ips.dpax.w.ph"
dfp" case 's': // 1 string to match.
case 'u': // 8 strings to match. if (memcmp(NameR.data()+7, "x.w.ph", 6))
if (NameR[14] != 'l')
break; break;
switch (NameR[15]) { return Intrinsic::mips_dpsx_w_ph; // "ips.dpsx.w.ph"
default: break; }
case 'e': // 4 strings to match. break;
switch (NameR[16]) { case 'e': // 1 string to match.
default: break; if (memcmp(NameR.data()+5, "xtr.rs.w", 8))
case 's': // 2 strings to match. break;
switch (NameR[17]) { return Intrinsic::mips_extr_rs_w; // "ips.extr.rs.w"
default: break; case 'm': // 2 strings to match.
case 'b': // 1 string to match. if (memcmp(NameR.data()+5, "ulq.", 4))
return Intrinsic::ppc_altivec_vmulesb; // "pc.altivec.vmul break;
esb" switch (NameR[9]) {
case 'h': // 1 string to match. default: break;
return Intrinsic::ppc_altivec_vmulesh; // "pc.altivec.vmul case 'r': // 1 string to match.
esh" if (memcmp(NameR.data()+10, "s.w", 3))
}
break;
case 'u': // 2 strings to match.
switch (NameR[17]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::ppc_altivec_vmuleub; // "pc.altivec.vmul
eub"
case 'h': // 1 string to match.
return Intrinsic::ppc_altivec_vmuleuh; // "pc.altivec.vmul
euh"
}
break;
}
break; break;
case 'o': // 4 strings to match. return Intrinsic::mips_mulq_rs_w; // "ips.mulq.rs.w"
switch (NameR[16]) { case 's': // 1 string to match.
default: break; if (memcmp(NameR.data()+10, ".ph", 3))
case 's': // 2 strings to match.
switch (NameR[17]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::ppc_altivec_vmulosb; // "pc.altivec.vmul
osb"
case 'h': // 1 string to match.
return Intrinsic::ppc_altivec_vmulosh; // "pc.altivec.vmul
osh"
}
break;
case 'u': // 2 strings to match.
switch (NameR[17]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::ppc_altivec_vmuloub; // "pc.altivec.vmul
oub"
case 'h': // 1 string to match.
return Intrinsic::ppc_altivec_vmulouh; // "pc.altivec.vmul
ouh"
}
break;
}
break; break;
} return Intrinsic::mips_mulq_s_ph; // "ips.mulq.s.ph"
break;
} }
break; break;
case 'p': // 6 strings to match. case 'p': // 1 string to match.
if (NameR[13] != 'k') if (memcmp(NameR.data()+5, "ackrl.ph", 8))
break; break;
switch (NameR[14]) { return Intrinsic::mips_packrl_ph; // "ips.packrl.ph"
case 's': // 7 strings to match.
switch (NameR[5]) {
default: break; default: break;
case 's': // 4 strings to match. case 'h': // 3 strings to match.
switch (NameR[15]) { switch (NameR[6]) {
default: break; default: break;
case 'h': // 2 strings to match. case 'l': // 1 string to match.
switch (NameR[16]) { if (memcmp(NameR.data()+7, "l.s.ph", 6))
default: break; break;
case 's': // 1 string to match. return Intrinsic::mips_shll_s_ph; // "ips.shll.s.ph"
if (NameR[17] != 's') case 'r': // 2 strings to match.
break; if (memcmp(NameR.data()+7, "a.r.", 4))
return Intrinsic::ppc_altivec_vpkshss; // "pc.altivec.vpks break;
hss" switch (NameR[11]) {
case 'u': // 1 string to match.
if (NameR[17] != 's')
break;
return Intrinsic::ppc_altivec_vpkshus; // "pc.altivec.vpks
hus"
}
break;
case 'w': // 2 strings to match.
switch (NameR[16]) {
default: break; default: break;
case 's': // 1 string to match. case 'p': // 1 string to match.
if (NameR[17] != 's') if (NameR[12] != 'h')
break; break;
return Intrinsic::ppc_altivec_vpkswss; // "pc.altivec.vpks return Intrinsic::mips_shra_r_ph; // "ips.shra.r.ph"
wss" case 'q': // 1 string to match.
case 'u': // 1 string to match. if (NameR[12] != 'b')
if (NameR[17] != 's')
break; break;
return Intrinsic::ppc_altivec_vpkswus; // "pc.altivec.vpks wus" return Intrinsic::mips_shra_r_qb; // "ips.shra.r.qb"
} }
break; break;
} }
break; break;
case 'u': // 2 strings to match. case 'u': // 4 strings to match.
switch (NameR[15]) { if (NameR[6] != 'b')
default: break; break;
case 'h': // 1 string to match. switch (NameR[7]) {
if (NameR.substr(16, 2) != "us")
break;
return Intrinsic::ppc_altivec_vpkuhus; // "pc.altivec.vpku
hus"
case 'w': // 1 string to match.
if (NameR.substr(16, 2) != "us")
break;
return Intrinsic::ppc_altivec_vpkuwus; // "pc.altivec.vpku
wus"
}
break;
}
break;
case 's': // 8 strings to match.
if (NameR[13] != 'u')
break;
switch (NameR[14]) {
default: break;
case 'b': // 7 strings to match.
switch (NameR[15]) {
default: break; default: break;
case 'c': // 1 string to match. case 'q': // 2 strings to match.
if (NameR.substr(16, 2) != "uw") switch (NameR[8]) {
break;
return Intrinsic::ppc_altivec_vsubcuw; // "pc.altivec.vsub
cuw"
case 's': // 3 strings to match.
switch (NameR[16]) {
default: break; default: break;
case 'b': // 1 string to match. case '.': // 1 string to match.
if (NameR[17] != 's') if (memcmp(NameR.data()+9, "s.ph", 4))
break; break;
return Intrinsic::ppc_altivec_vsubsbs; // "pc.altivec.vsub sbs" return Intrinsic::mips_subq_s_ph; // "ips.subq.s.ph"
case 'h': // 1 string to match. case 'h': // 1 string to match.
if (NameR[17] != 's') if (memcmp(NameR.data()+9, ".r.w", 4))
break;
return Intrinsic::ppc_altivec_vsubshs; // "pc.altivec.vsub
shs"
case 'w': // 1 string to match.
if (NameR[17] != 's')
break; break;
return Intrinsic::ppc_altivec_vsubsws; // "pc.altivec.vsub sws" return Intrinsic::mips_subqh_r_w; // "ips.subqh.r.w"
} }
break; break;
case 'u': // 3 strings to match. case 'u': // 2 strings to match.
switch (NameR[16]) { if (memcmp(NameR.data()+8, ".s.", 3))
break;
switch (NameR[11]) {
default: break; default: break;
case 'b': // 1 string to match. case 'p': // 1 string to match.
if (NameR[17] != 's') if (NameR[12] != 'h')
break;
return Intrinsic::ppc_altivec_vsububs; // "pc.altivec.vsub
ubs"
case 'h': // 1 string to match.
if (NameR[17] != 's')
break; break;
return Intrinsic::ppc_altivec_vsubuhs; // "pc.altivec.vsub return Intrinsic::mips_subu_s_ph; // "ips.subu.s.ph"
uhs" case 'q': // 1 string to match.
case 'w': // 1 string to match. if (NameR[12] != 'b')
if (NameR[17] != 's')
break; break;
return Intrinsic::ppc_altivec_vsubuws; // "pc.altivec.vsub uws" return Intrinsic::mips_subu_s_qb; // "ips.subu.s.qb"
} }
break; break;
} }
break; break;
case 'm': // 1 string to match. }
if (NameR.substr(15, 3) != "sws") break;
}
break;
case 14: // 14 strings to match.
if (memcmp(NameR.data()+0, "ips.", 4))
break;
switch (NameR[4]) {
default: break;
case 'a': // 2 strings to match.
if (memcmp(NameR.data()+5, "dd", 2))
break;
switch (NameR[7]) {
default: break;
case 'q': // 1 string to match.
if (memcmp(NameR.data()+8, "h.r.ph", 6))
break; break;
return Intrinsic::ppc_altivec_vsumsws; // "pc.altivec.vsum return Intrinsic::mips_addqh_r_ph; // "ips.addqh.r.ph"
sws" case 'u': // 1 string to match.
if (memcmp(NameR.data()+8, "h.r.qb", 6))
break;
return Intrinsic::mips_adduh_r_qb; // "ips.adduh.r.qb"
} }
break; break;
case 'u': // 6 strings to match. case 'c': // 3 strings to match.
if (NameR.substr(13, 2) != "pk") if (memcmp(NameR.data()+5, "mpu.", 4))
break; break;
switch (NameR[15]) { switch (NameR[9]) {
default: break; default: break;
case 'h': // 3 strings to match. case 'e': // 1 string to match.
switch (NameR[16]) { if (memcmp(NameR.data()+10, "q.qb", 4))
break;
return Intrinsic::mips_cmpu_eq_qb; // "ips.cmpu.eq.qb"
case 'l': // 2 strings to match.
switch (NameR[10]) {
default: break; default: break;
case 'p': // 1 string to match. case 'e': // 1 string to match.
if (NameR[17] != 'x') if (memcmp(NameR.data()+11, ".qb", 3))
break; break;
return Intrinsic::ppc_altivec_vupkhpx; // "pc.altivec.vupk return Intrinsic::mips_cmpu_le_qb; // "ips.cmpu.le.qb"
hpx" case 't': // 1 string to match.
case 's': // 2 strings to match. if (memcmp(NameR.data()+11, ".qb", 3))
switch (NameR[17]) { break;
default: break; return Intrinsic::mips_cmpu_lt_qb; // "ips.cmpu.lt.qb"
case 'b': // 1 string to match.
return Intrinsic::ppc_altivec_vupkhsb; // "pc.altivec.vupk
hsb"
case 'h': // 1 string to match.
return Intrinsic::ppc_altivec_vupkhsh; // "pc.altivec.vupk
hsh"
}
break;
} }
break; break;
case 'l': // 3 strings to match. }
switch (NameR[16]) { break;
case 'd': // 4 strings to match.
if (NameR[5] != 'p')
break;
switch (NameR[6]) {
default: break;
case 'a': // 2 strings to match.
if (memcmp(NameR.data()+7, "u.h.qb", 6))
break;
switch (NameR[13]) {
default: break; default: break;
case 'p': // 1 string to match. case 'l': // 1 string to match.
if (NameR[17] != 'x') return Intrinsic::mips_dpau_h_qbl; // "ips.dpau.h.qbl"
break; case 'r': // 1 string to match.
return Intrinsic::ppc_altivec_vupklpx; // "pc.altivec.vupk return Intrinsic::mips_dpau_h_qbr; // "ips.dpau.h.qbr"
lpx" }
case 's': // 2 strings to match. break;
switch (NameR[17]) { case 's': // 2 strings to match.
default: break; if (memcmp(NameR.data()+7, "u.h.qb", 6))
case 'b': // 1 string to match.
return Intrinsic::ppc_altivec_vupklsb; // "pc.altivec.vupk
lsb"
case 'h': // 1 string to match.
return Intrinsic::ppc_altivec_vupklsh; // "pc.altivec.vupk
lsh"
}
break; break;
switch (NameR[13]) {
default: break;
case 'l': // 1 string to match.
return Intrinsic::mips_dpsu_h_qbl; // "ips.dpsu.h.qbl"
case 'r': // 1 string to match.
return Intrinsic::mips_dpsu_h_qbr; // "ips.dpsu.h.qbr"
} }
break; break;
} }
break; break;
} case 'm': // 2 strings to match.
break; if (memcmp(NameR.data()+5, "ul", 2))
case 19: // 29 strings to match.
switch (NameR[0]) {
default: break;
case 'p': // 24 strings to match.
if (NameR.substr(1, 11) != "c.altivec.v")
break; break;
switch (NameR[12]) { switch (NameR[7]) {
default: break; default: break;
case 'c': // 12 strings to match. case 'q': // 1 string to match.
if (NameR.substr(13, 2) != "mp") if (memcmp(NameR.data()+8, ".rs.ph", 6))
break; break;
switch (NameR[15]) { return Intrinsic::mips_mulq_rs_ph; // "ips.mulq.rs.ph"
default: break; case 's': // 1 string to match.
case 'e': // 4 strings to match. if (memcmp(NameR.data()+8, "a.w.ph", 6))
if (NameR[16] != 'q')
break;
switch (NameR[17]) {
default: break;
case 'f': // 1 string to match.
if (NameR[18] != 'p')
break;
return Intrinsic::ppc_altivec_vcmpeqfp; // "pc.altivec.vcmp
eqfp"
case 'u': // 3 strings to match.
switch (NameR[18]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::ppc_altivec_vcmpequb; // "pc.alti
vec.vcmpequb"
case 'h': // 1 string to match.
return Intrinsic::ppc_altivec_vcmpequh; // "pc.alti
vec.vcmpequh"
case 'w': // 1 string to match.
return Intrinsic::ppc_altivec_vcmpequw; // "pc.alti
vec.vcmpequw"
}
break;
}
break; break;
case 'g': // 8 strings to match. return Intrinsic::mips_mulsa_w_ph; // "ips.mulsa.w.ph"
switch (NameR[16]) { }
default: break; break;
case 'e': // 1 string to match. case 'r': // 1 string to match.
if (NameR.substr(17, 2) != "fp") if (memcmp(NameR.data()+5, "addu.w.qb", 9))
break; break;
return Intrinsic::ppc_altivec_vcmpgefp; // "pc.altivec.vcmp return Intrinsic::mips_raddu_w_qb; // "ips.raddu.w.qb"
gefp" case 's': // 2 strings to match.
case 't': // 7 strings to match. if (memcmp(NameR.data()+5, "ub", 2))
switch (NameR[17]) { break;
default: break; switch (NameR[7]) {
case 'f': // 1 string to match. default: break;
if (NameR[18] != 'p') case 'q': // 1 string to match.
break; if (memcmp(NameR.data()+8, "h.r.ph", 6))
return Intrinsic::ppc_altivec_vcmpgtfp; // "pc.alti
vec.vcmpgtfp"
case 's': // 3 strings to match.
switch (NameR[18]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::ppc_altivec_vcmpgtsb; // "pc.alti
vec.vcmpgtsb"
case 'h': // 1 string to match.
return Intrinsic::ppc_altivec_vcmpgtsh; // "pc.alti
vec.vcmpgtsh"
case 'w': // 1 string to match.
return Intrinsic::ppc_altivec_vcmpgtsw; // "pc.alti
vec.vcmpgtsw"
}
break;
case 'u': // 3 strings to match.
switch (NameR[18]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::ppc_altivec_vcmpgtub; // "pc.alti
vec.vcmpgtub"
case 'h': // 1 string to match.
return Intrinsic::ppc_altivec_vcmpgtuh; // "pc.alti
vec.vcmpgtuh"
case 'w': // 1 string to match.
return Intrinsic::ppc_altivec_vcmpgtuw; // "pc.alti
vec.vcmpgtuw"
}
break;
}
break;
}
break; break;
} return Intrinsic::mips_subqh_r_ph; // "ips.subqh.r.ph"
case 'u': // 1 string to match.
if (memcmp(NameR.data()+8, "h.r.qb", 6))
break;
return Intrinsic::mips_subuh_r_qb; // "ips.subuh.r.qb"
}
break;
}
break;
case 15: // 11 strings to match.
if (memcmp(NameR.data()+0, "ips.", 4))
break;
switch (NameR[4]) {
default: break;
case 'c': // 3 strings to match.
if (memcmp(NameR.data()+5, "mpgu.", 5))
break; break;
switch (NameR[10]) {
default: break;
case 'e': // 1 string to match. case 'e': // 1 string to match.
if (NameR.substr(13, 6) != "xptefp") if (memcmp(NameR.data()+11, "q.qb", 4))
break;
return Intrinsic::ppc_altivec_vexptefp; // "pc.altivec.vexp
tefp"
case 'm': // 6 strings to match.
if (NameR.substr(13, 3) != "sum")
break; break;
switch (NameR[16]) { return Intrinsic::mips_cmpgu_eq_qb; // "ips.cmpgu.eq.qb"
case 'l': // 2 strings to match.
switch (NameR[11]) {
default: break; default: break;
case 'm': // 1 string to match. case 'e': // 1 string to match.
if (NameR.substr(17, 2) != "bm") if (memcmp(NameR.data()+12, ".qb", 3))
break; break;
return Intrinsic::ppc_altivec_vmsummbm; // "pc.altivec.vmsu return Intrinsic::mips_cmpgu_le_qb; // "ips.cmpgu.le.qb
mmbm" "
case 's': // 2 strings to match. case 't': // 1 string to match.
if (NameR[17] != 'h') if (memcmp(NameR.data()+12, ".qb", 3))
break; break;
switch (NameR[18]) { return Intrinsic::mips_cmpgu_lt_qb; // "ips.cmpgu.lt.qb
default: break; "
case 'm': // 1 string to match. }
return Intrinsic::ppc_altivec_vmsumshm; // "pc.altivec.vmsu break;
mshm" }
case 's': // 1 string to match. break;
return Intrinsic::ppc_altivec_vmsumshs; // "pc.altivec.vmsu case 'd': // 4 strings to match.
mshs" if (NameR[5] != 'p')
} break;
switch (NameR[6]) {
default: break;
case 'a': // 2 strings to match.
if (memcmp(NameR.data()+7, "q.s", 3))
break; break;
case 'u': // 3 strings to match. switch (NameR[10]) {
switch (NameR[17]) { default: break;
default: break; case '.': // 1 string to match.
case 'b': // 1 string to match. if (memcmp(NameR.data()+11, "w.ph", 4))
if (NameR[18] != 'm')
break;
return Intrinsic::ppc_altivec_vmsumubm; // "pc.altivec.vmsu
mubm"
case 'h': // 2 strings to match.
switch (NameR[18]) {
default: break;
case 'm': // 1 string to match.
return Intrinsic::ppc_altivec_vmsumuhm; // "pc.alti
vec.vmsumuhm"
case 's': // 1 string to match.
return Intrinsic::ppc_altivec_vmsumuhs; // "pc.alti
vec.vmsumuhs"
}
break; break;
} return Intrinsic::mips_dpaq_s_w_ph; // "ips.dpaq.s.w.ph
break; "
case 'a': // 1 string to match.
if (memcmp(NameR.data()+11, ".l.w", 4))
break;
return Intrinsic::mips_dpaq_sa_l_w; // "ips.dpaq.sa.l.w
"
} }
break; break;
case 'n': // 1 string to match. case 's': // 2 strings to match.
if (NameR.substr(13, 6) != "msubfp") if (memcmp(NameR.data()+7, "q.s", 3))
break;
return Intrinsic::ppc_altivec_vnmsubfp; // "pc.altivec.vnms
ubfp"
case 's': // 4 strings to match.
if (NameR.substr(13, 2) != "um")
break; break;
switch (NameR[15]) { switch (NameR[10]) {
default: break; default: break;
case '2': // 1 string to match. case '.': // 1 string to match.
if (NameR.substr(16, 3) != "sws") if (memcmp(NameR.data()+11, "w.ph", 4))
break; break;
return Intrinsic::ppc_altivec_vsum2sws; // "pc.altivec.vsum return Intrinsic::mips_dpsq_s_w_ph; // "ips.dpsq.s.w.ph
2sws" "
case '4': // 3 strings to match. case 'a': // 1 string to match.
switch (NameR[16]) { if (memcmp(NameR.data()+11, ".l.w", 4))
default: break;
case 's': // 2 strings to match.
switch (NameR[17]) {
default: break;
case 'b': // 1 string to match.
if (NameR[18] != 's')
break;
return Intrinsic::ppc_altivec_vsum4sbs; // "pc.alti
vec.vsum4sbs"
case 'h': // 1 string to match.
if (NameR[18] != 's')
break;
return Intrinsic::ppc_altivec_vsum4shs; // "pc.alti
vec.vsum4shs"
}
break; break;
case 'u': // 1 string to match. return Intrinsic::mips_dpsq_sa_l_w; // "ips.dpsq.sa.l.w
if (NameR.substr(17, 2) != "bs") "
break;
return Intrinsic::ppc_altivec_vsum4ubs; // "pc.altivec.vsum
4ubs"
}
break;
} }
break; break;
} }
break; break;
case 't': // 5 strings to match. case 'm': // 2 strings to match.
if (NameR.substr(1, 16) != "x.read.lanemask.") if (memcmp(NameR.data()+5, "aq.s.w.ph", 9))
break; break;
switch (NameR[17]) { switch (NameR[14]) {
default: break;
case 'l': // 1 string to match.
return Intrinsic::mips_maq_s_w_phl; // "ips.maq.s.w.phl"
case 'r': // 1 string to match.
return Intrinsic::mips_maq_s_w_phr; // "ips.maq.s.w.phr"
}
break;
case 'p': // 2 strings to match.
if (memcmp(NameR.data()+5, "recr", 4))
break;
switch (NameR[9]) {
default: break;
case '.': // 1 string to match.
if (memcmp(NameR.data()+10, "qb.ph", 5))
break;
return Intrinsic::mips_precr_qb_ph; // "ips.precr.qb.ph"
case 'q': // 1 string to match.
if (memcmp(NameR.data()+10, ".ph.w", 5))
break;
return Intrinsic::mips_precrq_ph_w; // "ips.precrq.ph.w"
}
break;
}
break;
case 16: // 10 strings to match.
if (memcmp(NameR.data()+0, "ips.", 4))
break;
switch (NameR[4]) {
default: break;
case 'c': // 3 strings to match.
if (memcmp(NameR.data()+5, "mpgdu.", 6))
break;
switch (NameR[11]) {
default: break; default: break;
case 'e': // 1 string to match. case 'e': // 1 string to match.
if (NameR[18] != 'q') if (memcmp(NameR.data()+12, "q.qb", 4))
break; break;
return Intrinsic::ptx_read_lanemask_eq; // "tx.read.lanemas return Intrinsic::mips_cmpgdu_eq_qb; // "ips.cmpgdu.eq.qb"
k.eq" case 'l': // 2 strings to match.
case 'g': // 2 strings to match. switch (NameR[12]) {
switch (NameR[18]) {
default: break; default: break;
case 'e': // 1 string to match. case 'e': // 1 string to match.
return Intrinsic::ptx_read_lanemask_ge; // "tx.read.lanemas if (memcmp(NameR.data()+13, ".qb", 3))
k.ge" break;
return Intrinsic::mips_cmpgdu_le_qb; // "ips.cmpgdu.le.q
b"
case 't': // 1 string to match. case 't': // 1 string to match.
return Intrinsic::ptx_read_lanemask_gt; // "tx.read.lanemas if (memcmp(NameR.data()+13, ".qb", 3))
k.gt" break;
return Intrinsic::mips_cmpgdu_lt_qb; // "ips.cmpgdu.lt.q
b"
} }
break; break;
case 'l': // 2 strings to match. }
switch (NameR[18]) { break;
case 'd': // 2 strings to match.
if (NameR[5] != 'p')
break;
switch (NameR[6]) {
default: break;
case 'a': // 1 string to match.
if (memcmp(NameR.data()+7, "qx.s.w.ph", 9))
break;
return Intrinsic::mips_dpaqx_s_w_ph; // "ips.dpaqx.s.w.ph"
case 's': // 1 string to match.
if (memcmp(NameR.data()+7, "qx.s.w.ph", 9))
break;
return Intrinsic::mips_dpsqx_s_w_ph; // "ips.dpsqx.s.w.ph"
}
break;
case 'm': // 2 strings to match.
if (memcmp(NameR.data()+5, "aq.sa.w.ph", 10))
break;
switch (NameR[15]) {
default: break;
case 'l': // 1 string to match.
return Intrinsic::mips_maq_sa_w_phl; // "ips.maq.sa.w.phl"
case 'r': // 1 string to match.
return Intrinsic::mips_maq_sa_w_phr; // "ips.maq.sa.w.phr"
}
break;
case 'p': // 3 strings to match.
if (memcmp(NameR.data()+5, "rec", 3))
break;
switch (NameR[8]) {
default: break;
case 'e': // 2 strings to match.
if (memcmp(NameR.data()+9, "q.w.ph", 6))
break;
switch (NameR[15]) {
default: break; default: break;
case 'e': // 1 string to match. case 'l': // 1 string to match.
return Intrinsic::ptx_read_lanemask_le; // "tx.read.lanemas return Intrinsic::mips_preceq_w_phl; // "ips.preceq.w.ph
k.le" l"
case 't': // 1 string to match. case 'r': // 1 string to match.
return Intrinsic::ptx_read_lanemask_lt; // "tx.read.lanemas return Intrinsic::mips_preceq_w_phr; // "ips.preceq.w.ph
k.lt" r"
} }
break; break;
case 'r': // 1 string to match.
if (memcmp(NameR.data()+9, "q.qb.ph", 7))
break;
return Intrinsic::mips_precrq_qb_ph; // "ips.precrq.qb.ph"
} }
break; break;
} }
break; break;
case 20: // 4 strings to match. case 17: // 7 strings to match.
if (NameR.substr(0, 12) != "pc.altivec.v") if (memcmp(NameR.data()+0, "ips.", 4))
break; break;
switch (NameR[12]) { switch (NameR[4]) {
default: break; default: break;
case 'c': // 1 string to match. case 'd': // 2 strings to match.
if (NameR.substr(13, 7) != "mpbfp.p") if (NameR[5] != 'p')
break; break;
return Intrinsic::ppc_altivec_vcmpbfp_p; // "pc.altivec.vcmp switch (NameR[6]) {
bfp.p"
case 'm': // 2 strings to match.
switch (NameR[13]) {
default: break; default: break;
case 'h': // 1 string to match. case 'a': // 1 string to match.
if (NameR.substr(14, 6) != "addshs") if (memcmp(NameR.data()+7, "qx.sa.w.ph", 10))
break; break;
return Intrinsic::ppc_altivec_vmhaddshs; // "pc.altivec.vmha return Intrinsic::mips_dpaqx_sa_w_ph; // "ips.dpaqx.sa.w.
ddshs" ph"
case 'l': // 1 string to match. case 's': // 1 string to match.
if (NameR.substr(14, 6) != "adduhm") if (memcmp(NameR.data()+7, "qx.sa.w.ph", 10))
break; break;
return Intrinsic::ppc_altivec_vmladduhm; // "pc.altivec.vmla dduhm" return Intrinsic::mips_dpsqx_sa_w_ph; // "ips.dpsqx.sa.w. ph"
} }
break; break;
case 'r': // 1 string to match. case 'm': // 3 strings to match.
if (NameR.substr(13, 7) != "sqrtefp") if (memcmp(NameR.data()+5, "ul", 2))
break;
return Intrinsic::ppc_altivec_vrsqrtefp; // "pc.altivec.vrsq
rtefp"
}
break;
case 21: // 13 strings to match.
if (NameR.substr(0, 12) != "pc.altivec.v")
break;
switch (NameR[12]) {
default: break;
case 'c': // 12 strings to match.
if (NameR.substr(13, 2) != "mp")
break; break;
switch (NameR[15]) { switch (NameR[7]) {
default: break; default: break;
case 'e': // 4 strings to match. case 'e': // 2 strings to match.
if (NameR[16] != 'q') if (memcmp(NameR.data()+8, "q.s.w.ph", 8))
break; break;
switch (NameR[17]) { switch (NameR[16]) {
default: break; default: break;
case 'f': // 1 string to match. case 'l': // 1 string to match.
if (NameR.substr(18, 3) != "p.p") return Intrinsic::mips_muleq_s_w_phl; // "ips.muleq.s.w.p
hl"
case 'r': // 1 string to match.
return Intrinsic::mips_muleq_s_w_phr; // "ips.muleq.s.w.p
hr"
}
break;
case 's': // 1 string to match.
if (memcmp(NameR.data()+8, "aq.s.w.ph", 9))
break;
return Intrinsic::mips_mulsaq_s_w_ph; // "ips.mulsaq.s.w.
ph"
}
break;
case 'p': // 2 strings to match.
if (memcmp(NameR.data()+5, "receu.ph.qb", 11))
break;
switch (NameR[16]) {
default: break;
case 'l': // 1 string to match.
return Intrinsic::mips_preceu_ph_qbl; // "ips.preceu.ph.q
bl"
case 'r': // 1 string to match.
return Intrinsic::mips_preceu_ph_qbr; // "ips.preceu.ph.q
br"
}
break;
}
break;
case 18: // 8 strings to match.
if (memcmp(NameR.data()+0, "ips.", 4))
break;
switch (NameR[4]) {
default: break;
case 'm': // 2 strings to match.
if (memcmp(NameR.data()+5, "uleu.s.ph.qb", 12))
break;
switch (NameR[17]) {
default: break;
case 'l': // 1 string to match.
return Intrinsic::mips_muleu_s_ph_qbl; // "ips.muleu.s.ph.
qbl"
case 'r': // 1 string to match.
return Intrinsic::mips_muleu_s_ph_qbr; // "ips.muleu.s.ph.
qbr"
}
break;
case 'p': // 6 strings to match.
if (memcmp(NameR.data()+5, "rec", 3))
break;
switch (NameR[8]) {
default: break;
case 'e': // 4 strings to match.
switch (NameR[9]) {
default: break;
case 'q': // 2 strings to match.
if (memcmp(NameR.data()+10, "u.ph.qb", 7))
break; break;
return Intrinsic::ppc_altivec_vcmpeqfp_p; // "pc.altivec.vcmp switch (NameR[17]) {
eqfp.p"
case 'u': // 3 strings to match.
switch (NameR[18]) {
default: break; default: break;
case 'b': // 1 string to match. case 'l': // 1 string to match.
if (NameR.substr(19, 2) != ".p") return Intrinsic::mips_precequ_ph_qbl; // "ips.precequ.ph.
break; qbl"
return Intrinsic::ppc_altivec_vcmpequb_p; // "pc.alti case 'r': // 1 string to match.
vec.vcmpequb.p" return Intrinsic::mips_precequ_ph_qbr; // "ips.precequ.ph.
case 'h': // 1 string to match. qbr"
if (NameR.substr(19, 2) != ".p") }
break;
case 'u': // 2 strings to match.
if (memcmp(NameR.data()+10, ".ph.qb", 6))
break;
switch (NameR[16]) {
default: break;
case 'l': // 1 string to match.
if (NameR[17] != 'a')
break; break;
return Intrinsic::ppc_altivec_vcmpequh_p; // "pc.alti return Intrinsic::mips_preceu_ph_qbla; // "ips.preceu.ph.q
vec.vcmpequh.p" bla"
case 'w': // 1 string to match. case 'r': // 1 string to match.
if (NameR.substr(19, 2) != ".p") if (NameR[17] != 'a')
break; break;
return Intrinsic::ppc_altivec_vcmpequw_p; // "pc.alti vec.vcmpequw.p" return Intrinsic::mips_preceu_ph_qbra; // "ips.preceu.ph.q bra"
} }
break; break;
} }
break; break;
case 'g': // 8 strings to match. case 'r': // 2 strings to match.
switch (NameR[16]) { switch (NameR[9]) {
default: break; default: break;
case 'e': // 1 string to match. case '.': // 1 string to match.
if (NameR.substr(17, 4) != "fp.p") if (memcmp(NameR.data()+10, "sra.ph.w", 8))
break;
return Intrinsic::ppc_altivec_vcmpgefp_p; // "pc.altivec.vcmp
gefp.p"
case 't': // 7 strings to match.
switch (NameR[17]) {
default: break;
case 'f': // 1 string to match.
if (NameR.substr(18, 3) != "p.p")
break;
return Intrinsic::ppc_altivec_vcmpgtfp_p; // "pc.alti
vec.vcmpgtfp.p"
case 's': // 3 strings to match.
switch (NameR[18]) {
default: break;
case 'b': // 1 string to match.
if (NameR.substr(19, 2) != ".p")
break;
return Intrinsic::ppc_altivec_vcmpgtsb_p; // "pc.alti
vec.vcmpgtsb.p"
case 'h': // 1 string to match.
if (NameR.substr(19, 2) != ".p")
break;
return Intrinsic::ppc_altivec_vcmpgtsh_p; // "pc.alti
vec.vcmpgtsh.p"
case 'w': // 1 string to match.
if (NameR.substr(19, 2) != ".p")
break;
return Intrinsic::ppc_altivec_vcmpgtsw_p; // "pc.alti
vec.vcmpgtsw.p"
}
break; break;
case 'u': // 3 strings to match. return Intrinsic::mips_precr_sra_ph_w; // "ips.precr.sra.p
switch (NameR[18]) { h.w"
default: break; case 'q': // 1 string to match.
case 'b': // 1 string to match. if (memcmp(NameR.data()+10, ".rs.ph.w", 8))
if (NameR.substr(19, 2) != ".p")
break;
return Intrinsic::ppc_altivec_vcmpgtub_p; // "pc.alti
vec.vcmpgtub.p"
case 'h': // 1 string to match.
if (NameR.substr(19, 2) != ".p")
break;
return Intrinsic::ppc_altivec_vcmpgtuh_p; // "pc.alti
vec.vcmpgtuh.p"
case 'w': // 1 string to match.
if (NameR.substr(19, 2) != ".p")
break;
return Intrinsic::ppc_altivec_vcmpgtuw_p; // "pc.alti
vec.vcmpgtuw.p"
}
break; break;
} return Intrinsic::mips_precrq_rs_ph_w; // "ips.precrq.rs.p
break; h.w"
} }
break; break;
} }
break; break;
case 'm': // 1 string to match.
if (NameR.substr(13, 8) != "hraddshs")
break;
return Intrinsic::ppc_altivec_vmhraddshs; // "pc.altivec.vmhr
addshs"
} }
break; break;
} case 19: // 3 strings to match.
break; // end of 'p' case. if (memcmp(NameR.data()+0, "ips.prec", 8))
case 'r':
switch (NameR.size()) {
default: break;
case 12: // 1 string to match.
if (NameR.substr(0, 12) != "eturnaddress")
break; break;
return Intrinsic::returnaddress; // "eturnaddress" switch (NameR[8]) {
case 15: // 1 string to match. default: break;
if (NameR.substr(0, 15) != "eadcyclecounter") case 'e': // 2 strings to match.
if (memcmp(NameR.data()+9, "qu.ph.qb", 8))
break;
switch (NameR[17]) {
default: break;
case 'l': // 1 string to match.
if (NameR[18] != 'a')
break;
return Intrinsic::mips_precequ_ph_qbla; // "ips.precequ.ph.
qbla"
case 'r': // 1 string to match.
if (NameR[18] != 'a')
break;
return Intrinsic::mips_precequ_ph_qbra; // "ips.precequ.ph.
qbra"
}
break; break;
return Intrinsic::readcyclecounter; // "eadcyclecounter" case 'r': // 1 string to match.
if (memcmp(NameR.data()+9, "qu.s.qb.ph", 10))
break;
return Intrinsic::mips_precrqu_s_qb_ph; // "ips.precrqu.s.q
b.ph"
}
break;
case 20: // 1 string to match.
if (memcmp(NameR.data()+0, "ips.precr.sra.r.ph.w", 20))
break;
return Intrinsic::mips_precr_sra_r_ph_w; // "ips.precr.sra.r.ph.w"
} }
break; // end of 'r' case. break; // end of 'm' case.
case 's': case 'n':
if (NameR.startswith("add.with.overflow.")) return Intrinsic::sadd_with if (NameR.startswith("vvm.atomic.load.add.f32.")) return Intrinsic::nvv
_overflow; m_atomic_load_add_f32;
if (NameR.startswith("in.")) return Intrinsic::sin; if (NameR.startswith("vvm.atomic.load.dec.32.")) return Intrinsic::nvvm
if (NameR.startswith("mul.with.overflow.")) return Intrinsic::smul_with _atomic_load_dec_32;
_overflow; if (NameR.startswith("vvm.atomic.load.inc.32.")) return Intrinsic::nvvm
if (NameR.startswith("qrt.")) return Intrinsic::sqrt; _atomic_load_inc_32;
if (NameR.startswith("sub.with.overflow.")) return Intrinsic::ssub_with if (NameR.startswith("vvm.compiler.error.")) return Intrinsic::nvvm_com
_overflow; piler_error;
if (NameR.startswith("vvm.compiler.warn.")) return Intrinsic::nvvm_comp
iler_warn;
if (NameR.startswith("vvm.ldu.global.f.")) return Intrinsic::nvvm_ldu_g
lobal_f;
if (NameR.startswith("vvm.ldu.global.i.")) return Intrinsic::nvvm_ldu_g
lobal_i;
if (NameR.startswith("vvm.ldu.global.p.")) return Intrinsic::nvvm_ldu_g
lobal_p;
if (NameR.startswith("vvm.move.ptr.")) return Intrinsic::nvvm_move_ptr;
if (NameR.startswith("vvm.ptr.constant.to.gen.")) return Intrinsic::nvv
m_ptr_constant_to_gen;
if (NameR.startswith("vvm.ptr.gen.to.constant.")) return Intrinsic::nvv
m_ptr_gen_to_constant;
if (NameR.startswith("vvm.ptr.gen.to.global.")) return Intrinsic::nvvm_
ptr_gen_to_global;
if (NameR.startswith("vvm.ptr.gen.to.local.")) return Intrinsic::nvvm_p
tr_gen_to_local;
if (NameR.startswith("vvm.ptr.gen.to.param.")) return Intrinsic::nvvm_p
tr_gen_to_param;
if (NameR.startswith("vvm.ptr.gen.to.shared.")) return Intrinsic::nvvm_
ptr_gen_to_shared;
if (NameR.startswith("vvm.ptr.global.to.gen.")) return Intrinsic::nvvm_
ptr_global_to_gen;
if (NameR.startswith("vvm.ptr.local.to.gen.")) return Intrinsic::nvvm_p
tr_local_to_gen;
if (NameR.startswith("vvm.ptr.shared.to.gen.")) return Intrinsic::nvvm_
ptr_shared_to_gen;
switch (NameR.size()) { switch (NameR.size()) {
default: break; default: break;
case 5: // 1 string to match.
if (NameR.substr(0, 5) != "etjmp")
break;
return Intrinsic::setjmp; // "etjmp"
case 7: // 1 string to match. case 7: // 1 string to match.
if (NameR.substr(0, 7) != "pu.si.a") if (memcmp(NameR.data()+0, "vvm.h2f", 7))
break; break;
return Intrinsic::spu_si_a; // "pu.si.a" return Intrinsic::nvvm_h2f; // "vvm.h2f"
case 8: // 11 strings to match. case 8: // 1 string to match.
switch (NameR[0]) { if (memcmp(NameR.data()+0, "vvm.prmt", 8))
break;
return Intrinsic::nvvm_prmt; // "vvm.prmt"
case 9: // 5 strings to match.
if (memcmp(NameR.data()+0, "vvm.", 4))
break;
switch (NameR[4]) {
default: break; default: break;
case 'i': // 1 string to match. case 'a': // 1 string to match.
if (NameR.substr(1, 7) != "gsetjmp") if (memcmp(NameR.data()+5, "bs.i", 4))
break; break;
return Intrinsic::sigsetjmp; // "igsetjmp" return Intrinsic::nvvm_abs_i; // "vvm.abs.i"
case 'p': // 9 strings to match. case 'c': // 1 string to match.
if (NameR.substr(1, 5) != "u.si.") if (memcmp(NameR.data()+5, "lz.i", 4))
break; break;
switch (NameR[6]) { return Intrinsic::nvvm_clz_i; // "vvm.clz.i"
case 'm': // 2 strings to match.
switch (NameR[5]) {
default: break; default: break;
case 'a': // 2 strings to match. case 'a': // 1 string to match.
switch (NameR[7]) { if (memcmp(NameR.data()+6, "x.i", 3))
default: break;
case 'h': // 1 string to match.
return Intrinsic::spu_si_ah; // "pu.si.ah"
case 'i': // 1 string to match.
return Intrinsic::spu_si_ai; // "pu.si.ai"
}
break;
case 'b': // 1 string to match.
if (NameR[7] != 'g')
break;
return Intrinsic::spu_si_bg; // "pu.si.bg"
case 'c': // 1 string to match.
if (NameR[7] != 'g')
break;
return Intrinsic::spu_si_cg; // "pu.si.cg"
case 'f': // 3 strings to match.
switch (NameR[7]) {
default: break;
case 'a': // 1 string to match.
return Intrinsic::spu_si_fa; // "pu.si.fa"
case 'm': // 1 string to match.
return Intrinsic::spu_si_fm; // "pu.si.fm"
case 's': // 1 string to match.
return Intrinsic::spu_si_fs; // "pu.si.fs"
}
break;
case 'o': // 1 string to match.
if (NameR[7] != 'r')
break; break;
return Intrinsic::spu_si_or; // "pu.si.or" return Intrinsic::nvvm_max_i; // "vvm.max.i"
case 's': // 1 string to match. case 'i': // 1 string to match.
if (NameR[7] != 'f') if (memcmp(NameR.data()+6, "n.i", 3))
break; break;
return Intrinsic::spu_si_sf; // "pu.si.sf" return Intrinsic::nvvm_min_i; // "vvm.min.i"
} }
break; break;
case 't': // 1 string to match. case 's': // 1 string to match.
if (NameR.substr(1, 7) != "acksave") if (memcmp(NameR.data()+5, "ad.i", 4))
break; break;
return Intrinsic::stacksave; // "tacksave" return Intrinsic::nvvm_sad_i; // "vvm.sad.i"
} }
break; break;
case 9: // 20 strings to match. case 10: // 41 strings to match.
switch (NameR[0]) { if (memcmp(NameR.data()+0, "vvm.", 4))
break;
switch (NameR[4]) {
default: break; default: break;
case 'i': // 1 string to match. case 'a': // 1 string to match.
if (NameR.substr(1, 8) != "glongjmp") if (memcmp(NameR.data()+5, "bs.ll", 5))
break; break;
return Intrinsic::siglongjmp; // "iglongjmp" return Intrinsic::nvvm_abs_ll; // "vvm.abs.ll"
case 'p': // 19 strings to match. case 'b': // 2 strings to match.
if (NameR.substr(1, 5) != "u.si.") if (memcmp(NameR.data()+5, "rev", 3))
break;
switch (NameR[8]) {
default: break;
case '3': // 1 string to match.
if (NameR[9] != '2')
break;
return Intrinsic::nvvm_brev32; // "vvm.brev32"
case '6': // 1 string to match.
if (NameR[9] != '4')
break;
return Intrinsic::nvvm_brev64; // "vvm.brev64"
}
break;
case 'c': // 3 strings to match.
switch (NameR[5]) {
default: break;
case 'e': // 2 strings to match.
if (memcmp(NameR.data()+6, "il.", 3))
break;
switch (NameR[9]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::nvvm_ceil_d; // "vvm.ceil.d"
case 'f': // 1 string to match.
return Intrinsic::nvvm_ceil_f; // "vvm.ceil.f"
}
break;
case 'l': // 1 string to match.
if (memcmp(NameR.data()+6, "z.ll", 4))
break;
return Intrinsic::nvvm_clz_ll; // "vvm.clz.ll"
}
break;
case 'd': // 10 strings to match.
if (NameR[5] != '2')
break; break;
switch (NameR[6]) { switch (NameR[6]) {
default: break; default: break;
case 'a': // 2 strings to match. case 'f': // 4 strings to match.
switch (NameR[7]) { if (memcmp(NameR.data()+7, ".r", 2))
break;
switch (NameR[9]) {
default: break; default: break;
case 'h': // 1 string to match. case 'm': // 1 string to match.
if (NameR[8] != 'i') return Intrinsic::nvvm_d2f_rm; // "vvm.d2f.rm"
break;
return Intrinsic::spu_si_ahi; // "pu.si.ahi"
case 'n': // 1 string to match. case 'n': // 1 string to match.
if (NameR[8] != 'd') return Intrinsic::nvvm_d2f_rn; // "vvm.d2f.rn"
break; case 'p': // 1 string to match.
return Intrinsic::spu_si_and; // "pu.si.and" return Intrinsic::nvvm_d2f_rp; // "vvm.d2f.rp"
case 'z': // 1 string to match.
return Intrinsic::nvvm_d2f_rz; // "vvm.d2f.rz"
} }
break; break;
case 'b': // 1 string to match. case 'i': // 6 strings to match.
if (NameR.substr(7, 2) != "gx") if (NameR[7] != '.')
break; break;
return Intrinsic::spu_si_bgx; // "pu.si.bgx" switch (NameR[8]) {
case 'c': // 3 strings to match.
switch (NameR[7]) {
default: break; default: break;
case 'e': // 1 string to match. case 'h': // 1 string to match.
if (NameR[8] != 'q') if (NameR[9] != 'i')
break; break;
return Intrinsic::spu_si_ceq; // "pu.si.ceq" return Intrinsic::nvvm_d2i_hi; // "vvm.d2i.hi"
case 'g': // 2 strings to match. case 'l': // 1 string to match.
switch (NameR[8]) { if (NameR[9] != 'o')
default: break; break;
case 't': // 1 string to match. return Intrinsic::nvvm_d2i_lo; // "vvm.d2i.lo"
return Intrinsic::spu_si_cgt; // "pu.si.cgt" case 'r': // 4 strings to match.
case 'x': // 1 string to match. switch (NameR[9]) {
return Intrinsic::spu_si_cgx; // "pu.si.cgx" default: break;
case 'm': // 1 string to match.
return Intrinsic::nvvm_d2i_rm; // "vvm.d2i.rm"
case 'n': // 1 string to match.
return Intrinsic::nvvm_d2i_rn; // "vvm.d2i.rn"
case 'p': // 1 string to match.
return Intrinsic::nvvm_d2i_rp; // "vvm.d2i.rp"
case 'z': // 1 string to match.
return Intrinsic::nvvm_d2i_rz; // "vvm.d2i.rz"
} }
break; break;
} }
break; break;
case 'd': // 3 strings to match. }
if (NameR[7] != 'f') break;
break; case 'f': // 11 strings to match.
switch (NameR[8]) { switch (NameR[5]) {
default: break;
case '2': // 5 strings to match.
switch (NameR[6]) {
default: break; default: break;
case 'a': // 1 string to match. case 'h': // 1 string to match.
return Intrinsic::spu_si_dfa; // "pu.si.dfa" if (memcmp(NameR.data()+7, ".rn", 3))
case 'm': // 1 string to match. break;
return Intrinsic::spu_si_dfm; // "pu.si.dfm" return Intrinsic::nvvm_f2h_rn; // "vvm.f2h.rn"
case 's': // 1 string to match. case 'i': // 4 strings to match.
return Intrinsic::spu_si_dfs; // "pu.si.dfs" if (memcmp(NameR.data()+7, ".r", 2))
break;
switch (NameR[9]) {
default: break;
case 'm': // 1 string to match.
return Intrinsic::nvvm_f2i_rm; // "vvm.f2i.rm"
case 'n': // 1 string to match.
return Intrinsic::nvvm_f2i_rn; // "vvm.f2i.rn"
case 'p': // 1 string to match.
return Intrinsic::nvvm_f2i_rp; // "vvm.f2i.rp"
case 'z': // 1 string to match.
return Intrinsic::nvvm_f2i_rz; // "vvm.f2i.rz"
}
break;
} }
break; break;
case 'f': // 2 strings to match. case 'a': // 2 strings to match.
if (NameR[7] != 'm') if (memcmp(NameR.data()+6, "bs.", 3))
break; break;
switch (NameR[8]) { switch (NameR[9]) {
default: break; default: break;
case 'a': // 1 string to match. case 'd': // 1 string to match.
return Intrinsic::spu_si_fma; // "pu.si.fma" return Intrinsic::nvvm_fabs_d; // "vvm.fabs.d"
case 's': // 1 string to match. case 'f': // 1 string to match.
return Intrinsic::spu_si_fms; // "pu.si.fms" return Intrinsic::nvvm_fabs_f; // "vvm.fabs.f"
} }
break; break;
case 'm': // 1 string to match. case 'm': // 4 strings to match.
if (NameR.substr(7, 2) != "py") switch (NameR[6]) {
default: break;
case 'a': // 2 strings to match.
if (memcmp(NameR.data()+7, "x.", 2))
break;
switch (NameR[9]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::nvvm_fmax_d; // "vvm.fmax.d"
case 'f': // 1 string to match.
return Intrinsic::nvvm_fmax_f; // "vvm.fmax.f"
}
break; break;
return Intrinsic::spu_si_mpy; // "pu.si.mpy" case 'i': // 2 strings to match.
case 'n': // 1 string to match. if (memcmp(NameR.data()+7, "n.", 2))
if (NameR.substr(7, 2) != "or") break;
switch (NameR[9]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::nvvm_fmin_d; // "vvm.fmin.d"
case 'f': // 1 string to match.
return Intrinsic::nvvm_fmin_f; // "vvm.fmin.f"
}
break; break;
return Intrinsic::spu_si_nor; // "pu.si.nor" }
case 'o': // 2 strings to match. break;
if (NameR[7] != 'r') }
break;
case 'i': // 8 strings to match.
if (NameR[5] != '2')
break;
switch (NameR[6]) {
default: break;
case 'd': // 4 strings to match.
if (memcmp(NameR.data()+7, ".r", 2))
break; break;
switch (NameR[8]) { switch (NameR[9]) {
default: break; default: break;
case 'c': // 1 string to match. case 'm': // 1 string to match.
return Intrinsic::spu_si_orc; // "pu.si.orc" return Intrinsic::nvvm_i2d_rm; // "vvm.i2d.rm"
case 'i': // 1 string to match. case 'n': // 1 string to match.
return Intrinsic::spu_si_ori; // "pu.si.ori" return Intrinsic::nvvm_i2d_rn; // "vvm.i2d.rn"
case 'p': // 1 string to match.
return Intrinsic::nvvm_i2d_rp; // "vvm.i2d.rp"
case 'z': // 1 string to match.
return Intrinsic::nvvm_i2d_rz; // "vvm.i2d.rz"
} }
break; break;
case 's': // 3 strings to match. case 'f': // 4 strings to match.
if (NameR[7] != 'f') if (memcmp(NameR.data()+7, ".r", 2))
break;
switch (NameR[9]) {
default: break;
case 'm': // 1 string to match.
return Intrinsic::nvvm_i2f_rm; // "vvm.i2f.rm"
case 'n': // 1 string to match.
return Intrinsic::nvvm_i2f_rn; // "vvm.i2f.rn"
case 'p': // 1 string to match.
return Intrinsic::nvvm_i2f_rp; // "vvm.i2f.rp"
case 'z': // 1 string to match.
return Intrinsic::nvvm_i2f_rz; // "vvm.i2f.rz"
}
break;
}
break;
case 'm': // 4 strings to match.
switch (NameR[5]) {
default: break;
case 'a': // 2 strings to match.
if (memcmp(NameR.data()+6, "x.", 2))
break; break;
switch (NameR[8]) { switch (NameR[8]) {
default: break; default: break;
case 'h': // 1 string to match. case 'l': // 1 string to match.
return Intrinsic::spu_si_sfh; // "pu.si.sfh" if (NameR[9] != 'l')
case 'i': // 1 string to match. break;
return Intrinsic::spu_si_sfi; // "pu.si.sfi" return Intrinsic::nvvm_max_ll; // "vvm.max.ll"
case 'x': // 1 string to match. case 'u': // 1 string to match.
return Intrinsic::spu_si_sfx; // "pu.si.sfx" if (NameR[9] != 'i')
break;
return Intrinsic::nvvm_max_ui; // "vvm.max.ui"
} }
break; break;
case 'x': // 1 string to match. case 'i': // 2 strings to match.
if (NameR.substr(7, 2) != "or") if (memcmp(NameR.data()+6, "n.", 2))
break; break;
return Intrinsic::spu_si_xor; // "pu.si.xor" switch (NameR[8]) {
default: break;
case 'l': // 1 string to match.
if (NameR[9] != 'l')
break;
return Intrinsic::nvvm_min_ll; // "vvm.min.ll"
case 'u': // 1 string to match.
if (NameR[9] != 'i')
break;
return Intrinsic::nvvm_min_ui; // "vvm.min.ui"
}
break;
} }
break; break;
case 'p': // 1 string to match.
if (memcmp(NameR.data()+5, "opc.i", 5))
break;
return Intrinsic::nvvm_popc_i; // "vvm.popc.i"
case 's': // 1 string to match.
if (memcmp(NameR.data()+5, "ad.ui", 5))
break;
return Intrinsic::nvvm_sad_ui; // "vvm.sad.ui"
} }
break; break;
case 10: // 26 strings to match. case 11: // 44 strings to match.
if (NameR.substr(0, 6) != "pu.si.") if (memcmp(NameR.data()+0, "vvm.", 4))
break; break;
switch (NameR[6]) { switch (NameR[4]) {
default: break; default: break;
case 'a': // 3 strings to match. case 'd': // 8 strings to match.
switch (NameR[7]) { if (NameR[5] != '2')
break;
switch (NameR[6]) {
default: break; default: break;
case 'd': // 1 string to match. case 'l': // 4 strings to match.
if (NameR.substr(8, 2) != "dx") if (memcmp(NameR.data()+7, "l.r", 3))
break; break;
return Intrinsic::spu_si_addx; // "pu.si.addx" switch (NameR[10]) {
case 'n': // 2 strings to match. default: break;
if (NameR[8] != 'd') case 'm': // 1 string to match.
return Intrinsic::nvvm_d2ll_rm; // "vvm.d2ll.rm"
case 'n': // 1 string to match.
return Intrinsic::nvvm_d2ll_rn; // "vvm.d2ll.rn"
case 'p': // 1 string to match.
return Intrinsic::nvvm_d2ll_rp; // "vvm.d2ll.rp"
case 'z': // 1 string to match.
return Intrinsic::nvvm_d2ll_rz; // "vvm.d2ll.rz"
}
break;
case 'u': // 4 strings to match.
if (memcmp(NameR.data()+7, "i.r", 3))
break; break;
switch (NameR[9]) { switch (NameR[10]) {
default: break; default: break;
case 'c': // 1 string to match. case 'm': // 1 string to match.
return Intrinsic::spu_si_andc; // "pu.si.andc" return Intrinsic::nvvm_d2ui_rm; // "vvm.d2ui.rm"
case 'i': // 1 string to match. case 'n': // 1 string to match.
return Intrinsic::spu_si_andi; // "pu.si.andi" return Intrinsic::nvvm_d2ui_rn; // "vvm.d2ui.rn"
case 'p': // 1 string to match.
return Intrinsic::nvvm_d2ui_rp; // "vvm.d2ui.rp"
case 'z': // 1 string to match.
return Intrinsic::nvvm_d2ui_rz; // "vvm.d2ui.rz"
} }
break; break;
} }
break; break;
case 'c': // 7 strings to match. case 'f': // 10 strings to match.
switch (NameR[7]) { switch (NameR[5]) {
default: break; default: break;
case 'e': // 3 strings to match. case '2': // 8 strings to match.
if (NameR[8] != 'q') switch (NameR[6]) {
break;
switch (NameR[9]) {
default: break; default: break;
case 'b': // 1 string to match. case 'l': // 4 strings to match.
return Intrinsic::spu_si_ceqb; // "pu.si.ceqb" if (memcmp(NameR.data()+7, "l.r", 3))
case 'h': // 1 string to match. break;
return Intrinsic::spu_si_ceqh; // "pu.si.ceqh" switch (NameR[10]) {
case 'i': // 1 string to match. default: break;
return Intrinsic::spu_si_ceqi; // "pu.si.ceqi" case 'm': // 1 string to match.
return Intrinsic::nvvm_f2ll_rm; // "vvm.f2ll.rm"
case 'n': // 1 string to match.
return Intrinsic::nvvm_f2ll_rn; // "vvm.f2ll.rn"
case 'p': // 1 string to match.
return Intrinsic::nvvm_f2ll_rp; // "vvm.f2ll.rp"
case 'z': // 1 string to match.
return Intrinsic::nvvm_f2ll_rz; // "vvm.f2ll.rz"
}
break;
case 'u': // 4 strings to match.
if (memcmp(NameR.data()+7, "i.r", 3))
break;
switch (NameR[10]) {
default: break;
case 'm': // 1 string to match.
return Intrinsic::nvvm_f2ui_rm; // "vvm.f2ui.rm"
case 'n': // 1 string to match.
return Intrinsic::nvvm_f2ui_rn; // "vvm.f2ui.rn"
case 'p': // 1 string to match.
return Intrinsic::nvvm_f2ui_rp; // "vvm.f2ui.rp"
case 'z': // 1 string to match.
return Intrinsic::nvvm_f2ui_rz; // "vvm.f2ui.rz"
}
break;
} }
break; break;
case 'g': // 3 strings to match. case 'l': // 2 strings to match.
if (NameR[8] != 't') if (memcmp(NameR.data()+6, "oor.", 4))
break; break;
switch (NameR[9]) { switch (NameR[10]) {
default: break; default: break;
case 'b': // 1 string to match. case 'd': // 1 string to match.
return Intrinsic::spu_si_cgtb; // "pu.si.cgtb" return Intrinsic::nvvm_floor_d; // "vvm.floor.d"
case 'h': // 1 string to match. case 'f': // 1 string to match.
return Intrinsic::spu_si_cgth; // "pu.si.cgth" return Intrinsic::nvvm_floor_f; // "vvm.floor.f"
case 'i': // 1 string to match.
return Intrinsic::spu_si_cgti; // "pu.si.cgti"
} }
break; break;
case 'l': // 1 string to match.
if (NameR.substr(8, 2) != "gt")
break;
return Intrinsic::spu_si_clgt; // "pu.si.clgt"
} }
break; break;
case 'd': // 2 strings to match. case 'l': // 8 strings to match.
if (NameR.substr(7, 2) != "fm") if (memcmp(NameR.data()+5, "l2", 2))
break; break;
switch (NameR[9]) {
default: break;
case 'a': // 1 string to match.
return Intrinsic::spu_si_dfma; // "pu.si.dfma"
case 's': // 1 string to match.
return Intrinsic::spu_si_dfms; // "pu.si.dfms"
}
break;
case 'f': // 3 strings to match.
switch (NameR[7]) { switch (NameR[7]) {
default: break; default: break;
case 'c': // 2 strings to match. case 'd': // 4 strings to match.
switch (NameR[8]) { if (memcmp(NameR.data()+8, ".r", 2))
break;
switch (NameR[10]) {
default: break; default: break;
case 'e': // 1 string to match. case 'm': // 1 string to match.
if (NameR[9] != 'q') return Intrinsic::nvvm_ll2d_rm; // "vvm.ll2d.rm"
break; case 'n': // 1 string to match.
return Intrinsic::spu_si_fceq; // "pu.si.fceq" return Intrinsic::nvvm_ll2d_rn; // "vvm.ll2d.rn"
case 'g': // 1 string to match. case 'p': // 1 string to match.
if (NameR[9] != 't') return Intrinsic::nvvm_ll2d_rp; // "vvm.ll2d.rp"
break; case 'z': // 1 string to match.
return Intrinsic::spu_si_fcgt; // "pu.si.fcgt" return Intrinsic::nvvm_ll2d_rz; // "vvm.ll2d.rz"
} }
break; break;
case 'n': // 1 string to match. case 'f': // 4 strings to match.
if (NameR.substr(8, 2) != "ms") if (memcmp(NameR.data()+8, ".r", 2))
break; break;
return Intrinsic::spu_si_fnms; // "pu.si.fnms" switch (NameR[10]) {
default: break;
case 'm': // 1 string to match.
return Intrinsic::nvvm_ll2f_rm; // "vvm.ll2f.rm"
case 'n': // 1 string to match.
return Intrinsic::nvvm_ll2f_rn; // "vvm.ll2f.rn"
case 'p': // 1 string to match.
return Intrinsic::nvvm_ll2f_rp; // "vvm.ll2f.rp"
case 'z': // 1 string to match.
return Intrinsic::nvvm_ll2f_rz; // "vvm.ll2f.rz"
}
break;
} }
break; break;
case 'm': // 5 strings to match. case 'm': // 5 strings to match.
if (NameR.substr(7, 2) != "py") switch (NameR[5]) {
break;
switch (NameR[9]) {
default: break; default: break;
case 'a': // 1 string to match. case 'a': // 1 string to match.
return Intrinsic::spu_si_mpya; // "pu.si.mpya" if (memcmp(NameR.data()+6, "x.ull", 5))
case 'h': // 1 string to match. break;
return Intrinsic::spu_si_mpyh; // "pu.si.mpyh" return Intrinsic::nvvm_max_ull; // "vvm.max.ull"
case 'i': // 1 string to match. case 'i': // 1 string to match.
return Intrinsic::spu_si_mpyi; // "pu.si.mpyi" if (memcmp(NameR.data()+6, "n.ull", 5))
case 's': // 1 string to match. break;
return Intrinsic::spu_si_mpys; // "pu.si.mpys" return Intrinsic::nvvm_min_ull; // "vvm.min.ull"
case 'u': // 1 string to match. case 'o': // 1 string to match.
return Intrinsic::spu_si_mpyu; // "pu.si.mpyu" if (memcmp(NameR.data()+6, "ve.i8", 5))
break;
return Intrinsic::nvvm_move_i8; // "vvm.move.i8"
case 'u': // 2 strings to match.
if (NameR[6] != 'l')
break;
switch (NameR[7]) {
default: break;
case '2': // 1 string to match.
if (memcmp(NameR.data()+8, "4.i", 3))
break;
return Intrinsic::nvvm_mul24_i; // "vvm.mul24.i"
case 'h': // 1 string to match.
if (memcmp(NameR.data()+8, "i.i", 3))
break;
return Intrinsic::nvvm_mulhi_i; // "vvm.mulhi.i"
}
break;
} }
break; break;
case 'n': // 1 string to match. case 'p': // 1 string to match.
if (NameR.substr(7, 3) != "and") if (memcmp(NameR.data()+5, "opc.ll", 6))
break; break;
return Intrinsic::spu_si_nand; // "pu.si.nand" return Intrinsic::nvvm_popc_ll; // "vvm.popc.ll"
case 'o': // 2 strings to match. case 'r': // 2 strings to match.
if (NameR[7] != 'r') if (memcmp(NameR.data()+5, "ound.", 5))
break; break;
switch (NameR[8]) { switch (NameR[10]) {
default: break; default: break;
case 'b': // 1 string to match. case 'd': // 1 string to match.
if (NameR[9] != 'i') return Intrinsic::nvvm_round_d; // "vvm.round.d"
break; case 'f': // 1 string to match.
return Intrinsic::spu_si_orbi; // "pu.si.orbi" return Intrinsic::nvvm_round_f; // "vvm.round.f"
case 'h': // 1 string to match.
if (NameR[9] != 'i')
break;
return Intrinsic::spu_si_orhi; // "pu.si.orhi"
} }
break; break;
case 's': // 2 strings to match. case 't': // 2 strings to match.
switch (NameR[7]) { if (memcmp(NameR.data()+5, "runc.", 5))
break;
switch (NameR[10]) {
default: break; default: break;
case 'd': // 1 string to match.
return Intrinsic::nvvm_trunc_d; // "vvm.trunc.d"
case 'f': // 1 string to match. case 'f': // 1 string to match.
if (NameR.substr(8, 2) != "hi") return Intrinsic::nvvm_trunc_f; // "vvm.trunc.f"
}
break;
case 'u': // 8 strings to match.
if (memcmp(NameR.data()+5, "i2", 2))
break;
switch (NameR[7]) {
default: break;
case 'd': // 4 strings to match.
if (memcmp(NameR.data()+8, ".r", 2))
break; break;
return Intrinsic::spu_si_sfhi; // "pu.si.sfhi" switch (NameR[10]) {
case 'h': // 1 string to match. default: break;
if (NameR.substr(8, 2) != "li") case 'm': // 1 string to match.
return Intrinsic::nvvm_ui2d_rm; // "vvm.ui2d.rm"
case 'n': // 1 string to match.
return Intrinsic::nvvm_ui2d_rn; // "vvm.ui2d.rn"
case 'p': // 1 string to match.
return Intrinsic::nvvm_ui2d_rp; // "vvm.ui2d.rp"
case 'z': // 1 string to match.
return Intrinsic::nvvm_ui2d_rz; // "vvm.ui2d.rz"
}
break;
case 'f': // 4 strings to match.
if (memcmp(NameR.data()+8, ".r", 2))
break; break;
return Intrinsic::spu_si_shli; // "pu.si.shli" switch (NameR[10]) {
default: break;
case 'm': // 1 string to match.
return Intrinsic::nvvm_ui2f_rm; // "vvm.ui2f.rm"
case 'n': // 1 string to match.
return Intrinsic::nvvm_ui2f_rn; // "vvm.ui2f.rn"
case 'p': // 1 string to match.
return Intrinsic::nvvm_ui2f_rp; // "vvm.ui2f.rp"
case 'z': // 1 string to match.
return Intrinsic::nvvm_ui2f_rz; // "vvm.ui2f.rz"
}
break;
} }
break; break;
case 'x': // 1 string to match.
if (NameR.substr(7, 3) != "ori")
break;
return Intrinsic::spu_si_xori; // "pu.si.xori"
} }
break; break;
case 11: // 19 strings to match. case 12: // 64 strings to match.
switch (NameR[0]) { if (memcmp(NameR.data()+0, "vvm.", 4))
break;
switch (NameR[4]) {
default: break; default: break;
case 'p': // 18 strings to match. case 'a': // 8 strings to match.
if (NameR.substr(1, 5) != "u.si.") if (memcmp(NameR.data()+5, "dd.r", 4))
break; break;
switch (NameR[6]) { switch (NameR[9]) {
default: break; default: break;
case 'a': // 2 strings to match. case 'm': // 2 strings to match.
if (NameR.substr(7, 2) != "nd") if (NameR[10] != '.')
break; break;
switch (NameR[9]) { switch (NameR[11]) {
default: break; default: break;
case 'b': // 1 string to match. case 'd': // 1 string to match.
if (NameR[10] != 'i') return Intrinsic::nvvm_add_rm_d; // "vvm.add.rm.d"
break; case 'f': // 1 string to match.
return Intrinsic::spu_si_andbi; // "pu.si.andbi" return Intrinsic::nvvm_add_rm_f; // "vvm.add.rm.f"
case 'h': // 1 string to match.
if (NameR[10] != 'i')
break;
return Intrinsic::spu_si_andhi; // "pu.si.andhi"
} }
break; break;
case 'c': // 7 strings to match. case 'n': // 2 strings to match.
switch (NameR[7]) { if (NameR[10] != '.')
break;
switch (NameR[11]) {
default: break; default: break;
case 'e': // 2 strings to match. case 'd': // 1 string to match.
if (NameR[8] != 'q') return Intrinsic::nvvm_add_rn_d; // "vvm.add.rn.d"
case 'f': // 1 string to match.
return Intrinsic::nvvm_add_rn_f; // "vvm.add.rn.f"
}
break;
case 'p': // 2 strings to match.
if (NameR[10] != '.')
break;
switch (NameR[11]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::nvvm_add_rp_d; // "vvm.add.rp.d"
case 'f': // 1 string to match.
return Intrinsic::nvvm_add_rp_f; // "vvm.add.rp.f"
}
break;
case 'z': // 2 strings to match.
if (NameR[10] != '.')
break;
switch (NameR[11]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::nvvm_add_rz_d; // "vvm.add.rz.d"
case 'f': // 1 string to match.
return Intrinsic::nvvm_add_rz_f; // "vvm.add.rz.f"
}
break;
}
break;
case 'b': // 1 string to match.
if (memcmp(NameR.data()+5, "arrier0", 7))
break;
return Intrinsic::nvvm_barrier0; // "vvm.barrier0"
case 'd': // 12 strings to match.
switch (NameR[5]) {
default: break;
case '2': // 4 strings to match.
if (memcmp(NameR.data()+6, "ull.r", 5))
break;
switch (NameR[11]) {
default: break;
case 'm': // 1 string to match.
return Intrinsic::nvvm_d2ull_rm; // "vvm.d2ull.rm"
case 'n': // 1 string to match.
return Intrinsic::nvvm_d2ull_rn; // "vvm.d2ull.rn"
case 'p': // 1 string to match.
return Intrinsic::nvvm_d2ull_rp; // "vvm.d2ull.rp"
case 'z': // 1 string to match.
return Intrinsic::nvvm_d2ull_rz; // "vvm.d2ull.rz"
}
break;
case 'i': // 8 strings to match.
if (memcmp(NameR.data()+6, "v.r", 3))
break;
switch (NameR[9]) {
default: break;
case 'm': // 2 strings to match.
if (NameR[10] != '.')
break; break;
switch (NameR[9]) { switch (NameR[11]) {
default: break; default: break;
case 'b': // 1 string to match. case 'd': // 1 string to match.
if (NameR[10] != 'i') return Intrinsic::nvvm_div_rm_d; // "vvm.div.rm.d"
break; case 'f': // 1 string to match.
return Intrinsic::spu_si_ceqbi; // "pu.si.ceqbi" return Intrinsic::nvvm_div_rm_f; // "vvm.div.rm.f"
case 'h': // 1 string to match.
if (NameR[10] != 'i')
break;
return Intrinsic::spu_si_ceqhi; // "pu.si.ceqhi"
} }
break; break;
case 'g': // 2 strings to match. case 'n': // 2 strings to match.
if (NameR[8] != 't') if (NameR[10] != '.')
break; break;
switch (NameR[9]) { switch (NameR[11]) {
default: break; default: break;
case 'b': // 1 string to match. case 'd': // 1 string to match.
if (NameR[10] != 'i') return Intrinsic::nvvm_div_rn_d; // "vvm.div.rn.d"
break; case 'f': // 1 string to match.
return Intrinsic::spu_si_cgtbi; // "pu.si.cgtbi" return Intrinsic::nvvm_div_rn_f; // "vvm.div.rn.f"
case 'h': // 1 string to match.
if (NameR[10] != 'i')
break;
return Intrinsic::spu_si_cgthi; // "pu.si.cgthi"
} }
break; break;
case 'l': // 3 strings to match. case 'p': // 2 strings to match.
if (NameR.substr(8, 2) != "gt") if (NameR[10] != '.')
break; break;
switch (NameR[10]) { switch (NameR[11]) {
default: break; default: break;
case 'b': // 1 string to match. case 'd': // 1 string to match.
return Intrinsic::spu_si_clgtb; // "pu.si.clgtb" return Intrinsic::nvvm_div_rp_d; // "vvm.div.rp.d"
case 'h': // 1 string to match. case 'f': // 1 string to match.
return Intrinsic::spu_si_clgth; // "pu.si.clgth" return Intrinsic::nvvm_div_rp_f; // "vvm.div.rp.f"
case 'i': // 1 string to match.
return Intrinsic::spu_si_clgti; // "pu.si.clgti"
} }
break; break;
} case 'z': // 2 strings to match.
break; if (NameR[10] != '.')
case 'd': // 2 strings to match.
if (NameR.substr(7, 3) != "fnm")
break;
switch (NameR[10]) {
default: break;
case 'a': // 1 string to match.
return Intrinsic::spu_si_dfnma; // "pu.si.dfnma"
case 's': // 1 string to match.
return Intrinsic::spu_si_dfnms; // "pu.si.dfnms"
}
break;
case 'f': // 3 strings to match.
switch (NameR[7]) {
default: break;
case 'c': // 2 strings to match.
if (NameR[8] != 'm')
break; break;
switch (NameR[9]) { switch (NameR[11]) {
default: break; default: break;
case 'e': // 1 string to match. case 'd': // 1 string to match.
if (NameR[10] != 'q') return Intrinsic::nvvm_div_rz_d; // "vvm.div.rz.d"
break; case 'f': // 1 string to match.
return Intrinsic::spu_si_fcmeq; // "pu.si.fcmeq" return Intrinsic::nvvm_div_rz_f; // "vvm.div.rz.f"
case 'g': // 1 string to match.
if (NameR[10] != 't')
break;
return Intrinsic::spu_si_fcmgt; // "pu.si.fcmgt"
} }
break; break;
case 's': // 1 string to match.
if (NameR.substr(8, 3) != "mbi")
break;
return Intrinsic::spu_si_fsmbi; // "pu.si.fsmbi"
} }
break; break;
case 'm': // 2 strings to match. }
if (NameR.substr(7, 2) != "py") break;
case 'f': // 12 strings to match.
switch (NameR[5]) {
default: break;
case '2': // 4 strings to match.
if (memcmp(NameR.data()+6, "ull.r", 5))
break; break;
switch (NameR[9]) { switch (NameR[11]) {
default: break; default: break;
case 'h': // 1 string to match. case 'm': // 1 string to match.
if (NameR[10] != 'h') return Intrinsic::nvvm_f2ull_rm; // "vvm.f2ull.rm"
break; case 'n': // 1 string to match.
return Intrinsic::spu_si_mpyhh; // "pu.si.mpyhh" return Intrinsic::nvvm_f2ull_rn; // "vvm.f2ull.rn"
case 'u': // 1 string to match. case 'p': // 1 string to match.
if (NameR[10] != 'i') return Intrinsic::nvvm_f2ull_rp; // "vvm.f2ull.rp"
break; case 'z': // 1 string to match.
return Intrinsic::spu_si_mpyui; // "pu.si.mpyui" return Intrinsic::nvvm_f2ull_rz; // "vvm.f2ull.rz"
} }
break; break;
case 'x': // 2 strings to match. case 'm': // 8 strings to match.
if (NameR.substr(7, 2) != "or") if (memcmp(NameR.data()+6, "a.r", 3))
break; break;
switch (NameR[9]) { switch (NameR[9]) {
default: break; default: break;
case 'b': // 1 string to match. case 'm': // 2 strings to match.
if (NameR[10] != 'i') if (NameR[10] != '.')
break; break;
return Intrinsic::spu_si_xorbi; // "pu.si.xorbi" switch (NameR[11]) {
case 'h': // 1 string to match. default: break;
if (NameR[10] != 'i') case 'd': // 1 string to match.
return Intrinsic::nvvm_fma_rm_d; // "vvm.fma.rm.d"
case 'f': // 1 string to match.
return Intrinsic::nvvm_fma_rm_f; // "vvm.fma.rm.f"
}
break;
case 'n': // 2 strings to match.
if (NameR[10] != '.')
break; break;
return Intrinsic::spu_si_xorhi; // "pu.si.xorhi" switch (NameR[11]) {
} default: break;
break; case 'd': // 1 string to match.
} return Intrinsic::nvvm_fma_rn_d; // "vvm.fma.rn.d"
break; case 'f': // 1 string to match.
case 't': // 1 string to match. return Intrinsic::nvvm_fma_rn_f; // "vvm.fma.rn.f"
if (NameR.substr(1, 10) != "ackrestore") }
break;
case 'p': // 2 strings to match.
if (NameR[10] != '.')
break;
switch (NameR[11]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::nvvm_fma_rp_d; // "vvm.fma.rp.d"
case 'f': // 1 string to match.
return Intrinsic::nvvm_fma_rp_f; // "vvm.fma.rp.f"
}
break;
case 'z': // 2 strings to match.
if (NameR[10] != '.')
break;
switch (NameR[11]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::nvvm_fma_rz_d; // "vvm.fma.rz.d"
case 'f': // 1 string to match.
return Intrinsic::nvvm_fma_rz_f; // "vvm.fma.rz.f"
}
break;
}
break; break;
return Intrinsic::stackrestore; // "tackrestore" }
}
break;
case 12: // 6 strings to match.
if (NameR.substr(0, 6) != "pu.si.")
break; break;
switch (NameR[6]) { case 'l': // 1 string to match.
default: break; if (memcmp(NameR.data()+5, "ohi.i2d", 7))
case 'c': // 2 strings to match.
if (NameR.substr(7, 3) != "lgt")
break; break;
switch (NameR[10]) { return Intrinsic::nvvm_lohi_i2d; // "vvm.lohi.i2d"
case 'm': // 14 strings to match.
switch (NameR[5]) {
default: break; default: break;
case 'b': // 1 string to match. case 'o': // 3 strings to match.
if (NameR[11] != 'i') if (memcmp(NameR.data()+6, "ve.i", 4))
break; break;
return Intrinsic::spu_si_clgtbi; // "pu.si.clgtbi" switch (NameR[10]) {
case 'h': // 1 string to match. default: break;
if (NameR[11] != 'i') case '1': // 1 string to match.
if (NameR[11] != '6')
break;
return Intrinsic::nvvm_move_i16; // "vvm.move.i16"
case '3': // 1 string to match.
if (NameR[11] != '2')
break;
return Intrinsic::nvvm_move_i32; // "vvm.move.i32"
case '6': // 1 string to match.
if (NameR[11] != '4')
break;
return Intrinsic::nvvm_move_i64; // "vvm.move.i64"
}
break;
case 'u': // 11 strings to match.
if (NameR[6] != 'l')
break; break;
return Intrinsic::spu_si_clgthi; // "pu.si.clgthi" switch (NameR[7]) {
default: break;
case '.': // 8 strings to match.
if (NameR[8] != 'r')
break;
switch (NameR[9]) {
default: break;
case 'm': // 2 strings to match.
if (NameR[10] != '.')
break;
switch (NameR[11]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::nvvm_mul_rm_d; // "vvm.mul.rm.d"
case 'f': // 1 string to match.
return Intrinsic::nvvm_mul_rm_f; // "vvm.mul.rm.f"
}
break;
case 'n': // 2 strings to match.
if (NameR[10] != '.')
break;
switch (NameR[11]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::nvvm_mul_rn_d; // "vvm.mul.rn.d"
case 'f': // 1 string to match.
return Intrinsic::nvvm_mul_rn_f; // "vvm.mul.rn.f"
}
break;
case 'p': // 2 strings to match.
if (NameR[10] != '.')
break;
switch (NameR[11]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::nvvm_mul_rp_d; // "vvm.mul.rp.d"
case 'f': // 1 string to match.
return Intrinsic::nvvm_mul_rp_f; // "vvm.mul.rp.f"
}
break;
case 'z': // 2 strings to match.
if (NameR[10] != '.')
break;
switch (NameR[11]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::nvvm_mul_rz_d; // "vvm.mul.rz.d"
case 'f': // 1 string to match.
return Intrinsic::nvvm_mul_rz_f; // "vvm.mul.rz.f"
}
break;
}
break;
case '2': // 1 string to match.
if (memcmp(NameR.data()+8, "4.ui", 4))
break;
return Intrinsic::nvvm_mul24_ui; // "vvm.mul24.ui"
case 'h': // 2 strings to match.
if (memcmp(NameR.data()+8, "i.", 2))
break;
switch (NameR[10]) {
default: break;
case 'l': // 1 string to match.
if (NameR[11] != 'l')
break;
return Intrinsic::nvvm_mulhi_ll; // "vvm.mulhi.ll"
case 'u': // 1 string to match.
if (NameR[11] != 'i')
break;
return Intrinsic::nvvm_mulhi_ui; // "vvm.mulhi.ui"
}
break;
}
break;
} }
break; break;
case 'm': // 2 strings to match. case 'r': // 8 strings to match.
if (NameR.substr(7, 4) != "pyhh") if (memcmp(NameR.data()+5, "cp.r", 4))
break; break;
switch (NameR[11]) { switch (NameR[9]) {
default: break; default: break;
case 'a': // 1 string to match. case 'm': // 2 strings to match.
return Intrinsic::spu_si_mpyhha; // "pu.si.mpyhha" if (NameR[10] != '.')
case 'u': // 1 string to match. break;
return Intrinsic::spu_si_mpyhhu; // "pu.si.mpyhhu" switch (NameR[11]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::nvvm_rcp_rm_d; // "vvm.rcp.rm.d"
case 'f': // 1 string to match.
return Intrinsic::nvvm_rcp_rm_f; // "vvm.rcp.rm.f"
}
break;
case 'n': // 2 strings to match.
if (NameR[10] != '.')
break;
switch (NameR[11]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::nvvm_rcp_rn_d; // "vvm.rcp.rn.d"
case 'f': // 1 string to match.
return Intrinsic::nvvm_rcp_rn_f; // "vvm.rcp.rn.f"
}
break;
case 'p': // 2 strings to match.
if (NameR[10] != '.')
break;
switch (NameR[11]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::nvvm_rcp_rp_d; // "vvm.rcp.rp.d"
case 'f': // 1 string to match.
return Intrinsic::nvvm_rcp_rp_f; // "vvm.rcp.rp.f"
}
break;
case 'z': // 2 strings to match.
if (NameR[10] != '.')
break;
switch (NameR[11]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::nvvm_rcp_rz_d; // "vvm.rcp.rz.d"
case 'f': // 1 string to match.
return Intrinsic::nvvm_rcp_rz_f; // "vvm.rcp.rz.f"
}
break;
} }
break; break;
case 's': // 2 strings to match. case 'u': // 8 strings to match.
if (NameR.substr(7, 4) != "hlqb") if (memcmp(NameR.data()+5, "ll2", 3))
break; break;
switch (NameR[11]) { switch (NameR[8]) {
default: break; default: break;
case 'i': // 1 string to match. case 'd': // 4 strings to match.
return Intrinsic::spu_si_shlqbi; // "pu.si.shlqbi" if (memcmp(NameR.data()+9, ".r", 2))
case 'y': // 1 string to match. break;
return Intrinsic::spu_si_shlqby; // "pu.si.shlqby" switch (NameR[11]) {
default: break;
case 'm': // 1 string to match.
return Intrinsic::nvvm_ull2d_rm; // "vvm.ull2d.rm"
case 'n': // 1 string to match.
return Intrinsic::nvvm_ull2d_rn; // "vvm.ull2d.rn"
case 'p': // 1 string to match.
return Intrinsic::nvvm_ull2d_rp; // "vvm.ull2d.rp"
case 'z': // 1 string to match.
return Intrinsic::nvvm_ull2d_rz; // "vvm.ull2d.rz"
}
break;
case 'f': // 4 strings to match.
if (memcmp(NameR.data()+9, ".r", 2))
break;
switch (NameR[11]) {
default: break;
case 'm': // 1 string to match.
return Intrinsic::nvvm_ull2f_rm; // "vvm.ull2f.rm"
case 'n': // 1 string to match.
return Intrinsic::nvvm_ull2f_rn; // "vvm.ull2f.rn"
case 'p': // 1 string to match.
return Intrinsic::nvvm_ull2f_rp; // "vvm.ull2f.rp"
case 'z': // 1 string to match.
return Intrinsic::nvvm_ull2f_rz; // "vvm.ull2f.rz"
}
break;
} }
break; break;
} }
break; break;
case 13: // 4 strings to match. case 13: // 10 strings to match.
switch (NameR[0]) { if (memcmp(NameR.data()+0, "vvm.", 4))
break;
switch (NameR[4]) {
default: break; default: break;
case 'p': // 3 strings to match. case 'm': // 2 strings to match.
if (NameR.substr(1, 5) != "u.si.") switch (NameR[5]) {
default: break;
case 'e': // 1 string to match.
if (memcmp(NameR.data()+6, "mbar.gl", 7))
break;
return Intrinsic::nvvm_membar_gl; // "vvm.membar.gl"
case 'u': // 1 string to match.
if (memcmp(NameR.data()+6, "lhi.ull", 7))
break;
return Intrinsic::nvvm_mulhi_ull; // "vvm.mulhi.ull"
}
break;
case 's': // 8 strings to match.
if (memcmp(NameR.data()+5, "qrt.r", 5))
break; break;
switch (NameR[6]) { switch (NameR[10]) {
default: break; default: break;
case 'm': // 1 string to match. case 'm': // 2 strings to match.
if (NameR.substr(7, 6) != "pyhhau") if (NameR[11] != '.')
break; break;
return Intrinsic::spu_si_mpyhhau; // "pu.si.mpyhhau" switch (NameR[12]) {
case 's': // 2 strings to match. default: break;
if (NameR.substr(7, 4) != "hlqb") case 'd': // 1 string to match.
return Intrinsic::nvvm_sqrt_rm_d; // "vvm.sqrt.rm.d"
case 'f': // 1 string to match.
return Intrinsic::nvvm_sqrt_rm_f; // "vvm.sqrt.rm.f"
}
break;
case 'n': // 2 strings to match.
if (NameR[11] != '.')
break; break;
switch (NameR[11]) { switch (NameR[12]) {
default: break; default: break;
case 'i': // 1 string to match. case 'd': // 1 string to match.
if (NameR[12] != 'i') return Intrinsic::nvvm_sqrt_rn_d; // "vvm.sqrt.rn.d"
break; case 'f': // 1 string to match.
return Intrinsic::spu_si_shlqbii; // "pu.si.shlqbii" return Intrinsic::nvvm_sqrt_rn_f; // "vvm.sqrt.rn.f"
case 'y': // 1 string to match. }
if (NameR[12] != 'i') break;
break; case 'p': // 2 strings to match.
return Intrinsic::spu_si_shlqbyi; // "pu.si.shlqbyi" if (NameR[11] != '.')
break;
switch (NameR[12]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::nvvm_sqrt_rp_d; // "vvm.sqrt.rp.d"
case 'f': // 1 string to match.
return Intrinsic::nvvm_sqrt_rp_f; // "vvm.sqrt.rp.f"
}
break;
case 'z': // 2 strings to match.
if (NameR[11] != '.')
break;
switch (NameR[12]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::nvvm_sqrt_rz_d; // "vvm.sqrt.rz.d"
case 'f': // 1 string to match.
return Intrinsic::nvvm_sqrt_rz_f; // "vvm.sqrt.rz.f"
} }
break; break;
} }
break; break;
case 't': // 1 string to match.
if (NameR.substr(1, 12) != "ackprotector")
break;
return Intrinsic::stackprotector; // "tackprotector"
} }
break; break;
} case 14: // 18 strings to match.
break; // end of 's' case. if (memcmp(NameR.data()+0, "vvm.", 4))
case 't':
switch (NameR.size()) {
default: break;
case 3: // 1 string to match.
if (NameR.substr(0, 3) != "rap")
break;
return Intrinsic::trap; // "rap"
}
break; // end of 't' case.
case 'u':
if (NameR.startswith("add.with.overflow.")) return Intrinsic::uadd_with
_overflow;
if (NameR.startswith("mul.with.overflow.")) return Intrinsic::umul_with
_overflow;
if (NameR.startswith("sub.with.overflow.")) return Intrinsic::usub_with
_overflow;
break; // end of 'u' case.
case 'v':
switch (NameR.size()) {
default: break;
case 5: // 1 string to match.
if (NameR.substr(0, 5) != "a_end")
break;
return Intrinsic::vaend; // "a_end"
case 6: // 1 string to match.
if (NameR.substr(0, 6) != "a_copy")
break; break;
return Intrinsic::vacopy; // "a_copy" switch (NameR[4]) {
case 7: // 1 string to match.
if (NameR.substr(0, 7) != "a_start")
break;
return Intrinsic::vastart; // "a_start"
case 13: // 1 string to match.
if (NameR.substr(0, 13) != "ar.annotation")
break;
return Intrinsic::var_annotation; // "ar.annotation"
}
break; // end of 'v' case.
case 'x':
if (NameR.startswith("core.chkct.")) return Intrinsic::xcore_chkct;
if (NameR.startswith("core.eeu.")) return Intrinsic::xcore_eeu;
if (NameR.startswith("core.endin.")) return Intrinsic::xcore_endin;
if (NameR.startswith("core.freer.")) return Intrinsic::xcore_freer;
if (NameR.startswith("core.getr.")) return Intrinsic::xcore_getr;
if (NameR.startswith("core.getst.")) return Intrinsic::xcore_getst;
if (NameR.startswith("core.getts.")) return Intrinsic::xcore_getts;
if (NameR.startswith("core.in.")) return Intrinsic::xcore_in;
if (NameR.startswith("core.inct.")) return Intrinsic::xcore_inct;
if (NameR.startswith("core.initcp.")) return Intrinsic::xcore_initcp;
if (NameR.startswith("core.initdp.")) return Intrinsic::xcore_initdp;
if (NameR.startswith("core.initlr.")) return Intrinsic::xcore_initlr;
if (NameR.startswith("core.initpc.")) return Intrinsic::xcore_initpc;
if (NameR.startswith("core.initsp.")) return Intrinsic::xcore_initsp;
if (NameR.startswith("core.inshr.")) return Intrinsic::xcore_inshr;
if (NameR.startswith("core.int.")) return Intrinsic::xcore_int;
if (NameR.startswith("core.mjoin.")) return Intrinsic::xcore_mjoin;
if (NameR.startswith("core.msync.")) return Intrinsic::xcore_msync;
if (NameR.startswith("core.out.")) return Intrinsic::xcore_out;
if (NameR.startswith("core.outct.")) return Intrinsic::xcore_outct;
if (NameR.startswith("core.outshr.")) return Intrinsic::xcore_outshr;
if (NameR.startswith("core.outt.")) return Intrinsic::xcore_outt;
if (NameR.startswith("core.peek.")) return Intrinsic::xcore_peek;
if (NameR.startswith("core.setc.")) return Intrinsic::xcore_setc;
if (NameR.startswith("core.setclk.")) return Intrinsic::xcore_setclk;
if (NameR.startswith("core.setd.")) return Intrinsic::xcore_setd;
if (NameR.startswith("core.setev.")) return Intrinsic::xcore_setev;
if (NameR.startswith("core.setpsc.")) return Intrinsic::xcore_setpsc;
if (NameR.startswith("core.setpt.")) return Intrinsic::xcore_setpt;
if (NameR.startswith("core.setrdy.")) return Intrinsic::xcore_setrdy;
if (NameR.startswith("core.settw.")) return Intrinsic::xcore_settw;
if (NameR.startswith("core.setv.")) return Intrinsic::xcore_setv;
if (NameR.startswith("core.syncr.")) return Intrinsic::xcore_syncr;
if (NameR.startswith("core.testct.")) return Intrinsic::xcore_testct;
if (NameR.startswith("core.testwct.")) return Intrinsic::xcore_testwct;
switch (NameR.size()) {
default: break;
case 6: // 1 string to match.
if (NameR.substr(0, 6) != "86.int")
break;
return Intrinsic::x86_int; // "86.int"
case 9: // 4 strings to match.
if (NameR.substr(0, 5) != "core.")
break;
switch (NameR[5]) {
default: break; default: break;
case 'c': // 2 strings to match. case 'c': // 1 string to match.
switch (NameR[6]) { if (memcmp(NameR.data()+5, "eil.ftz.f", 9))
break;
return Intrinsic::nvvm_ceil_ftz_f; // "vvm.ceil.ftz.f"
case 'd': // 4 strings to match.
if (memcmp(NameR.data()+5, "2f.r", 4))
break;
switch (NameR[9]) {
default: break; default: break;
case 'l': // 1 string to match. case 'm': // 1 string to match.
if (NameR.substr(7, 2) != "re") if (memcmp(NameR.data()+10, ".ftz", 4))
break; break;
return Intrinsic::xcore_clre; // "core.clre" return Intrinsic::nvvm_d2f_rm_ftz; // "vvm.d2f.rm.ftz"
case 'r': // 1 string to match. case 'n': // 1 string to match.
if (NameR.substr(7, 2) != "c8") if (memcmp(NameR.data()+10, ".ftz", 4))
break;
return Intrinsic::nvvm_d2f_rn_ftz; // "vvm.d2f.rn.ftz"
case 'p': // 1 string to match.
if (memcmp(NameR.data()+10, ".ftz", 4))
break;
return Intrinsic::nvvm_d2f_rp_ftz; // "vvm.d2f.rp.ftz"
case 'z': // 1 string to match.
if (memcmp(NameR.data()+10, ".ftz", 4))
break; break;
return Intrinsic::xcore_crc8; // "core.crc8" return Intrinsic::nvvm_d2f_rz_ftz; // "vvm.d2f.rz.ftz"
} }
break; break;
case 's': // 1 string to match. case 'f': // 8 strings to match.
if (NameR.substr(6, 3) != "ext")
break;
return Intrinsic::xcore_sext; // "core.sext"
case 'z': // 1 string to match.
if (NameR.substr(6, 3) != "ext")
break;
return Intrinsic::xcore_zext; // "core.zext"
}
break;
case 10: // 10 strings to match.
switch (NameR[0]) {
default: break;
case '8': // 1 string to match.
if (NameR.substr(1, 9) != "6.mmx.por")
break;
return Intrinsic::x86_mmx_por; // "86.mmx.por"
case 'c': // 9 strings to match.
if (NameR.substr(1, 4) != "ore.")
break;
switch (NameR[5]) { switch (NameR[5]) {
default: break; default: break;
case 'c': // 2 strings to match. case '2': // 5 strings to match.
switch (NameR[6]) { switch (NameR[6]) {
default: break; default: break;
case 'l': // 1 string to match. case 'h': // 1 string to match.
if (NameR.substr(7, 3) != "rsr") if (memcmp(NameR.data()+7, ".rn.ftz", 7))
break; break;
return Intrinsic::xcore_clrsr; // "core.clrsr" return Intrinsic::nvvm_f2h_rn_ftz; // "vvm.f2h.rn.ftz"
case 'r': // 1 string to match. case 'i': // 4 strings to match.
if (NameR.substr(7, 3) != "c32") if (memcmp(NameR.data()+7, ".r", 2))
break; break;
return Intrinsic::xcore_crc32; // "core.crc32"
}
break;
case 'g': // 4 strings to match.
if (NameR.substr(6, 2) != "et")
break;
switch (NameR[8]) {
default: break;
case 'e': // 2 strings to match.
switch (NameR[9]) { switch (NameR[9]) {
default: break; default: break;
case 'd': // 1 string to match. case 'm': // 1 string to match.
return Intrinsic::xcore_geted; // "core.geted" if (memcmp(NameR.data()+10, ".ftz", 4))
case 't': // 1 string to match. break;
return Intrinsic::xcore_getet; // "core.getet" return Intrinsic::nvvm_f2i_rm_ftz; // "vvm.f2i.rm.ftz"
case 'n': // 1 string to match.
if (memcmp(NameR.data()+10, ".ftz", 4))
break;
return Intrinsic::nvvm_f2i_rn_ftz; // "vvm.f2i.rn.ftz"
case 'p': // 1 string to match.
if (memcmp(NameR.data()+10, ".ftz", 4))
break;
return Intrinsic::nvvm_f2i_rp_ftz; // "vvm.f2i.rp.ftz"
case 'z': // 1 string to match.
if (memcmp(NameR.data()+10, ".ftz", 4))
break;
return Intrinsic::nvvm_f2i_rz_ftz; // "vvm.f2i.rz.ftz"
} }
break; break;
case 'i': // 1 string to match.
if (NameR[9] != 'd')
break;
return Intrinsic::xcore_getid; // "core.getid"
case 'p': // 1 string to match.
if (NameR[9] != 's')
break;
return Intrinsic::xcore_getps; // "core.getps"
} }
break; break;
case 's': // 3 strings to match. case 'a': // 1 string to match.
if (memcmp(NameR.data()+6, "bs.ftz.f", 8))
break;
return Intrinsic::nvvm_fabs_ftz_f; // "vvm.fabs.ftz.f"
case 'm': // 2 strings to match.
switch (NameR[6]) { switch (NameR[6]) {
default: break; default: break;
case 'e': // 2 strings to match. case 'a': // 1 string to match.
if (NameR[7] != 't') if (memcmp(NameR.data()+7, "x.ftz.f", 7))
break; break;
switch (NameR[8]) { return Intrinsic::nvvm_fmax_ftz_f; // "vvm.fmax.ftz.f"
default: break; case 'i': // 1 string to match.
case 'p': // 1 string to match. if (memcmp(NameR.data()+7, "n.ftz.f", 7))
if (NameR[9] != 's')
break;
return Intrinsic::xcore_setps; // "core.setps"
case 's': // 1 string to match.
if (NameR[9] != 'r')
break;
return Intrinsic::xcore_setsr; // "core.setsr"
}
break;
case 's': // 1 string to match.
if (NameR.substr(7, 3) != "ync")
break; break;
return Intrinsic::xcore_ssync; // "core.ssync" return Intrinsic::nvvm_fmin_ftz_f; // "vvm.fmin.ftz.f"
} }
break; break;
} }
break; break;
} case 'm': // 3 strings to match.
break; switch (NameR[5]) {
case 11: // 4 strings to match.
switch (NameR[0]) {
default: break;
case '8': // 3 strings to match.
if (NameR.substr(1, 6) != "6.mmx.")
break;
switch (NameR[7]) {
default: break; default: break;
case 'e': // 1 string to match. case 'e': // 2 strings to match.
if (NameR.substr(8, 3) != "mms") if (memcmp(NameR.data()+6, "mbar.", 5))
break; break;
return Intrinsic::x86_mmx_emms; // "86.mmx.emms" switch (NameR[11]) {
case 'p': // 2 strings to match.
switch (NameR[8]) {
default: break; default: break;
case 'a': // 1 string to match. case 'c': // 1 string to match.
if (NameR.substr(9, 2) != "nd") if (memcmp(NameR.data()+12, "ta", 2))
break; break;
return Intrinsic::x86_mmx_pand; // "86.mmx.pand" return Intrinsic::nvvm_membar_cta; // "vvm.membar.cta"
case 'x': // 1 string to match. case 's': // 1 string to match.
if (NameR.substr(9, 2) != "or") if (memcmp(NameR.data()+12, "ys", 2))
break; break;
return Intrinsic::x86_mmx_pxor; // "86.mmx.pxor" return Intrinsic::nvvm_membar_sys; // "vvm.membar.sys"
} }
break; break;
case 'o': // 1 string to match.
if (memcmp(NameR.data()+6, "ve.float", 8))
break;
return Intrinsic::nvvm_move_float; // "vvm.move.float"
} }
break; break;
case 'c': // 1 string to match. case 's': // 2 strings to match.
if (NameR.substr(1, 10) != "ore.bitrev") if (memcmp(NameR.data()+5, "aturate.", 8))
break; break;
return Intrinsic::xcore_bitrev; // "core.bitrev" switch (NameR[13]) {
} default: break;
break; case 'd': // 1 string to match.
case 12: // 2 strings to match. return Intrinsic::nvvm_saturate_d; // "vvm.saturate.d"
if (NameR.substr(0, 7) != "86.mmx.") case 'f': // 1 string to match.
return Intrinsic::nvvm_saturate_f; // "vvm.saturate.f"
}
break; break;
switch (NameR[7]) {
default: break;
case 'f': // 1 string to match.
if (NameR.substr(8, 4) != "emms")
break;
return Intrinsic::x86_mmx_femms; // "86.mmx.femms"
case 'p': // 1 string to match.
if (NameR.substr(8, 4) != "andn")
break;
return Intrinsic::x86_mmx_pandn; // "86.mmx.pandn"
} }
break; break;
case 13: // 49 strings to match. case 15: // 15 strings to match.
if (NameR.substr(0, 3) != "86.") if (memcmp(NameR.data()+0, "vvm.", 4))
break; break;
switch (NameR[3]) { switch (NameR[4]) {
default: break; default: break;
case 'a': // 1 string to match. case 'b': // 3 strings to match.
if (NameR.substr(4, 9) != "vx2.permd") switch (NameR[5]) {
break;
return Intrinsic::x86_avx2_permd; // "86.avx2.permd"
case 'm': // 18 strings to match.
if (NameR.substr(4, 4) != "mx.p")
break;
switch (NameR[8]) {
default: break; default: break;
case 'a': // 6 strings to match. case 'a': // 1 string to match.
switch (NameR[9]) { if (memcmp(NameR.data()+6, "rrier0.or", 9))
break;
return Intrinsic::nvvm_barrier0_or; // "vvm.barrier0.or"
case 'i': // 2 strings to match.
if (memcmp(NameR.data()+6, "tcast.", 6))
break;
switch (NameR[12]) {
default: break; default: break;
case 'd': // 4 strings to match. case 'f': // 1 string to match.
if (NameR.substr(10, 2) != "d.") if (memcmp(NameR.data()+13, "2i", 2))
break; break;
switch (NameR[12]) { return Intrinsic::nvvm_bitcast_f2i; // "vvm.bitcast.f2i
default: break; "
case 'b': // 1 string to match. case 'i': // 1 string to match.
return Intrinsic::x86_mmx_padd_b; // "86.mmx.padd.b" if (memcmp(NameR.data()+13, "2f", 2))
case 'd': // 1 string to match.
return Intrinsic::x86_mmx_padd_d; // "86.mmx.padd.d"
case 'q': // 1 string to match.
return Intrinsic::x86_mmx_padd_q; // "86.mmx.padd.q"
case 'w': // 1 string to match.
return Intrinsic::x86_mmx_padd_w; // "86.mmx.padd.w"
}
break;
case 'v': // 2 strings to match.
if (NameR.substr(10, 2) != "g.")
break; break;
switch (NameR[12]) { return Intrinsic::nvvm_bitcast_i2f; // "vvm.bitcast.i2f
default: break; "
case 'b': // 1 string to match.
return Intrinsic::x86_mmx_pavg_b; // "86.mmx.pavg.b"
case 'w': // 1 string to match.
return Intrinsic::x86_mmx_pavg_w; // "86.mmx.pavg.w"
}
break;
} }
break; break;
case 's': // 12 strings to match. }
switch (NameR[9]) { break;
case 'f': // 9 strings to match.
switch (NameR[5]) {
default: break;
case '2': // 8 strings to match.
switch (NameR[6]) {
default: break; default: break;
case 'l': // 3 strings to match. case 'l': // 4 strings to match.
if (NameR.substr(10, 2) != "l.") if (memcmp(NameR.data()+7, "l.r", 3))
break; break;
switch (NameR[12]) { switch (NameR[10]) {
default: break; default: break;
case 'd': // 1 string to match. case 'm': // 1 string to match.
return Intrinsic::x86_mmx_psll_d; // "86.mmx.psll.d" if (memcmp(NameR.data()+11, ".ftz", 4))
case 'q': // 1 string to match. break;
return Intrinsic::x86_mmx_psll_q; // "86.mmx.psll.q" return Intrinsic::nvvm_f2ll_rm_ftz; // "vvm.f2ll.rm.ftz
case 'w': // 1 string to match. "
return Intrinsic::x86_mmx_psll_w; // "86.mmx.psll.w" case 'n': // 1 string to match.
if (memcmp(NameR.data()+11, ".ftz", 4))
break;
return Intrinsic::nvvm_f2ll_rn_ftz; // "vvm.f2ll.rn.ftz
"
case 'p': // 1 string to match.
if (memcmp(NameR.data()+11, ".ftz", 4))
break;
return Intrinsic::nvvm_f2ll_rp_ftz; // "vvm.f2ll.rp.ftz
"
case 'z': // 1 string to match.
if (memcmp(NameR.data()+11, ".ftz", 4))
break;
return Intrinsic::nvvm_f2ll_rz_ftz; // "vvm.f2ll.rz.ftz
"
} }
break; break;
case 'r': // 5 strings to match. case 'u': // 4 strings to match.
if (memcmp(NameR.data()+7, "i.r", 3))
break;
switch (NameR[10]) { switch (NameR[10]) {
default: break; default: break;
case 'a': // 2 strings to match. case 'm': // 1 string to match.
if (NameR[11] != '.') if (memcmp(NameR.data()+11, ".ftz", 4))
break; break;
switch (NameR[12]) { return Intrinsic::nvvm_f2ui_rm_ftz; // "vvm.f2ui.rm.ftz
default: break; "
case 'd': // 1 string to match. case 'n': // 1 string to match.
return Intrinsic::x86_mmx_psra_d; // "86.mmx.psra.d" if (memcmp(NameR.data()+11, ".ftz", 4))
case 'w': // 1 string to match.
return Intrinsic::x86_mmx_psra_w; // "86.mmx.psra.w"
}
break;
case 'l': // 3 strings to match.
if (NameR[11] != '.')
break; break;
switch (NameR[12]) { return Intrinsic::nvvm_f2ui_rn_ftz; // "vvm.f2ui.rn.ftz
default: break; "
case 'd': // 1 string to match. case 'p': // 1 string to match.
return Intrinsic::x86_mmx_psrl_d; // "86.mmx.psrl.d" if (memcmp(NameR.data()+11, ".ftz", 4))
case 'q': // 1 string to match. break;
return Intrinsic::x86_mmx_psrl_q; // "86.mmx.psrl.q" return Intrinsic::nvvm_f2ui_rp_ftz; // "vvm.f2ui.rp.ftz
case 'w': // 1 string to match. "
return Intrinsic::x86_mmx_psrl_w; // "86.mmx.psrl.w" case 'z': // 1 string to match.
} if (memcmp(NameR.data()+11, ".ftz", 4))
break; break;
} return Intrinsic::nvvm_f2ui_rz_ftz; // "vvm.f2ui.rz.ftz
break; "
case 'u': // 4 strings to match.
if (NameR.substr(10, 2) != "b.")
break;
switch (NameR[12]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::x86_mmx_psub_b; // "86.mmx.psub.b"
case 'd': // 1 string to match.
return Intrinsic::x86_mmx_psub_d; // "86.mmx.psub.d"
case 'q': // 1 string to match.
return Intrinsic::x86_mmx_psub_q; // "86.mmx.psub.q"
case 'w': // 1 string to match.
return Intrinsic::x86_mmx_psub_w; // "86.mmx.psub.w"
} }
break; break;
} }
break; break;
case 'l': // 1 string to match.
if (memcmp(NameR.data()+6, "oor.ftz.f", 9))
break;
return Intrinsic::nvvm_floor_ftz_f; // "vvm.floor.ftz.f"
} }
break; break;
case 's': // 16 strings to match. case 'm': // 1 string to match.
if (NameR.substr(4, 2) != "se") if (memcmp(NameR.data()+5, "ove.double", 10))
break; break;
switch (NameR[6]) { return Intrinsic::nvvm_move_double; // "vvm.move.double"
case 'r': // 1 string to match.
if (memcmp(NameR.data()+5, "ound.ftz.f", 10))
break;
return Intrinsic::nvvm_round_ftz_f; // "vvm.round.ftz.f"
case 't': // 1 string to match.
if (memcmp(NameR.data()+5, "runc.ftz.f", 10))
break;
return Intrinsic::nvvm_trunc_ftz_f; // "vvm.trunc.ftz.f"
}
break;
case 16: // 34 strings to match.
if (memcmp(NameR.data()+0, "vvm.", 4))
break;
switch (NameR[4]) {
default: break;
case 'a': // 4 strings to match.
if (memcmp(NameR.data()+5, "dd.r", 4))
break;
switch (NameR[9]) {
default: break; default: break;
case '.': // 13 strings to match. case 'm': // 1 string to match.
switch (NameR[7]) { if (memcmp(NameR.data()+10, ".ftz.f", 6))
default: break;
case 'a': // 1 string to match.
if (NameR.substr(8, 5) != "dd.ss")
break;
return Intrinsic::x86_sse_add_ss; // "86.sse.add.ss"
case 'c': // 2 strings to match.
if (NameR.substr(8, 3) != "mp.")
break;
switch (NameR[11]) {
default: break;
case 'p': // 1 string to match.
if (NameR[12] != 's')
break;
return Intrinsic::x86_sse_cmp_ps; // "86.sse.cmp.ps"
case 's': // 1 string to match.
if (NameR[12] != 's')
break;
return Intrinsic::x86_sse_cmp_ss; // "86.sse.cmp.ss"
}
break; break;
case 'd': // 1 string to match. return Intrinsic::nvvm_add_rm_ftz_f; // "vvm.add.rm.ftz.f"
if (NameR.substr(8, 5) != "iv.ss") case 'n': // 1 string to match.
break; if (memcmp(NameR.data()+10, ".ftz.f", 6))
return Intrinsic::x86_sse_div_ss; // "86.sse.div.ss"
case 'm': // 5 strings to match.
switch (NameR[8]) {
default: break;
case 'a': // 2 strings to match.
if (NameR.substr(9, 2) != "x.")
break;
switch (NameR[11]) {
default: break;
case 'p': // 1 string to match.
if (NameR[12] != 's')
break;
return Intrinsic::x86_sse_max_ps; // "86.sse.max.ps"
case 's': // 1 string to match.
if (NameR[12] != 's')
break;
return Intrinsic::x86_sse_max_ss; // "86.sse.max.ss"
}
break;
case 'i': // 2 strings to match.
if (NameR.substr(9, 2) != "n.")
break;
switch (NameR[11]) {
default: break;
case 'p': // 1 string to match.
if (NameR[12] != 's')
break;
return Intrinsic::x86_sse_min_ps; // "86.sse.min.ps"
case 's': // 1 string to match.
if (NameR[12] != 's')
break;
return Intrinsic::x86_sse_min_ss; // "86.sse.min.ss"
}
break;
case 'u': // 1 string to match.
if (NameR.substr(9, 4) != "l.ss")
break;
return Intrinsic::x86_sse_mul_ss; // "86.sse.mul.ss"
}
break; break;
case 'r': // 2 strings to match. return Intrinsic::nvvm_add_rn_ftz_f; // "vvm.add.rn.ftz.f"
if (NameR.substr(8, 3) != "cp.") case 'p': // 1 string to match.
break; if (memcmp(NameR.data()+10, ".ftz.f", 6))
switch (NameR[11]) {
default: break;
case 'p': // 1 string to match.
if (NameR[12] != 's')
break;
return Intrinsic::x86_sse_rcp_ps; // "86.sse.rcp.ps"
case 's': // 1 string to match.
if (NameR[12] != 's')
break;
return Intrinsic::x86_sse_rcp_ss; // "86.sse.rcp.ss"
}
break; break;
case 's': // 2 strings to match. return Intrinsic::nvvm_add_rp_ftz_f; // "vvm.add.rp.ftz.f"
switch (NameR[8]) { case 'z': // 1 string to match.
default: break; if (memcmp(NameR.data()+10, ".ftz.f", 6))
case 'f': // 1 string to match.
if (NameR.substr(9, 4) != "ence")
break;
return Intrinsic::x86_sse_sfence; // "86.sse.sfence"
case 'u': // 1 string to match.
if (NameR.substr(9, 4) != "b.ss")
break;
return Intrinsic::x86_sse_sub_ss; // "86.sse.sub.ss"
}
break; break;
} return Intrinsic::nvvm_add_rz_ftz_f; // "vvm.add.rz.ftz.f"
break; }
case '3': // 1 string to match. break;
if (NameR.substr(7, 6) != ".mwait") case 'b': // 3 strings to match.
switch (NameR[5]) {
default: break;
case 'a': // 1 string to match.
if (memcmp(NameR.data()+6, "rrier0.and", 10))
break; break;
return Intrinsic::x86_sse3_mwait; // "86.sse3.mwait" return Intrinsic::nvvm_barrier0_and; // "vvm.barrier0.and"
case '4': // 2 strings to match. case 'i': // 2 strings to match.
if (NameR.substr(7, 5) != "1.dpp") if (memcmp(NameR.data()+6, "tcast.", 6))
break; break;
switch (NameR[12]) { switch (NameR[12]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
return Intrinsic::x86_sse41_dppd; // "86.sse41.dppd" if (memcmp(NameR.data()+13, "2ll", 3))
case 's': // 1 string to match. break;
return Intrinsic::x86_sse41_dpps; // "86.sse41.dpps" return Intrinsic::nvvm_bitcast_d2ll; // "vvm.bitcast.d2l
l"
case 'l': // 1 string to match.
if (memcmp(NameR.data()+13, "l2d", 3))
break;
return Intrinsic::nvvm_bitcast_ll2d; // "vvm.bitcast.ll2
d"
} }
break; break;
} }
break; break;
case 'x': // 14 strings to match. case 'c': // 1 string to match.
if (NameR.substr(4, 5) != "op.vp") if (memcmp(NameR.data()+5, "os.approx.f", 11))
break; break;
switch (NameR[9]) { return Intrinsic::nvvm_cos_approx_f; // "vvm.cos.approx.f"
case 'd': // 5 strings to match.
if (memcmp(NameR.data()+5, "iv.", 3))
break;
switch (NameR[8]) {
default: break; default: break;
case 'c': // 1 string to match. case 'a': // 1 string to match.
if (NameR.substr(10, 3) != "mov") if (memcmp(NameR.data()+9, "pprox.f", 7))
break;
return Intrinsic::x86_xop_vpcmov; // "86.xop.vpcmov"
case 'p': // 1 string to match.
if (NameR.substr(10, 3) != "erm")
break; break;
return Intrinsic::x86_xop_vpperm; // "86.xop.vpperm" return Intrinsic::nvvm_div_approx_f; // "vvm.div.approx.f"
case 'r': // 4 strings to match. case 'r': // 4 strings to match.
if (NameR.substr(10, 2) != "ot") switch (NameR[9]) {
break;
switch (NameR[12]) {
default: break; default: break;
case 'b': // 1 string to match. case 'm': // 1 string to match.
return Intrinsic::x86_xop_vprotb; // "86.xop.vprotb" if (memcmp(NameR.data()+10, ".ftz.f", 6))
case 'd': // 1 string to match. break;
return Intrinsic::x86_xop_vprotd; // "86.xop.vprotd" return Intrinsic::nvvm_div_rm_ftz_f; // "vvm.div.rm.ftz.
case 'q': // 1 string to match. f"
return Intrinsic::x86_xop_vprotq; // "86.xop.vprotq" case 'n': // 1 string to match.
case 'w': // 1 string to match. if (memcmp(NameR.data()+10, ".ftz.f", 6))
return Intrinsic::x86_xop_vprotw; // "86.xop.vprotw" break;
return Intrinsic::nvvm_div_rn_ftz_f; // "vvm.div.rn.ftz.
f"
case 'p': // 1 string to match.
if (memcmp(NameR.data()+10, ".ftz.f", 6))
break;
return Intrinsic::nvvm_div_rp_ftz_f; // "vvm.div.rp.ftz.
f"
case 'z': // 1 string to match.
if (memcmp(NameR.data()+10, ".ftz.f", 6))
break;
return Intrinsic::nvvm_div_rz_ftz_f; // "vvm.div.rz.ftz.
f"
} }
break; break;
case 's': // 8 strings to match. }
if (NameR[10] != 'h') break;
case 'e': // 2 strings to match.
if (memcmp(NameR.data()+5, "x2.approx.", 10))
break;
switch (NameR[15]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::nvvm_ex2_approx_d; // "vvm.ex2.approx.d"
case 'f': // 1 string to match.
return Intrinsic::nvvm_ex2_approx_f; // "vvm.ex2.approx.f"
}
break;
case 'f': // 8 strings to match.
switch (NameR[5]) {
default: break;
case '2': // 4 strings to match.
if (memcmp(NameR.data()+6, "ull.r", 5))
break; break;
switch (NameR[11]) { switch (NameR[11]) {
default: break; default: break;
case 'a': // 4 strings to match. case 'm': // 1 string to match.
switch (NameR[12]) { if (memcmp(NameR.data()+12, ".ftz", 4))
default: break; break;
case 'b': // 1 string to match. return Intrinsic::nvvm_f2ull_rm_ftz; // "vvm.f2ull.rm.ft
return Intrinsic::x86_xop_vpshab; // "86.xop.vpshab" z"
case 'd': // 1 string to match. case 'n': // 1 string to match.
return Intrinsic::x86_xop_vpshad; // "86.xop.vpshad" if (memcmp(NameR.data()+12, ".ftz", 4))
case 'q': // 1 string to match. break;
return Intrinsic::x86_xop_vpshaq; // "86.xop.vpshaq" return Intrinsic::nvvm_f2ull_rn_ftz; // "vvm.f2ull.rn.ft
case 'w': // 1 string to match. z"
return Intrinsic::x86_xop_vpshaw; // "86.xop.vpshaw" case 'p': // 1 string to match.
} if (memcmp(NameR.data()+12, ".ftz", 4))
break; break;
case 'l': // 4 strings to match. return Intrinsic::nvvm_f2ull_rp_ftz; // "vvm.f2ull.rp.ft
switch (NameR[12]) { z"
default: break; case 'z': // 1 string to match.
case 'b': // 1 string to match. if (memcmp(NameR.data()+12, ".ftz", 4))
return Intrinsic::x86_xop_vpshlb; // "86.xop.vpshlb" break;
case 'd': // 1 string to match. return Intrinsic::nvvm_f2ull_rz_ftz; // "vvm.f2ull.rz.ft
return Intrinsic::x86_xop_vpshld; // "86.xop.vpshld" z"
case 'q': // 1 string to match. }
return Intrinsic::x86_xop_vpshlq; // "86.xop.vpshlq" break;
case 'w': // 1 string to match. case 'm': // 4 strings to match.
return Intrinsic::x86_xop_vpshlw; // "86.xop.vpshlw" if (memcmp(NameR.data()+6, "a.r", 3))
}
break; break;
switch (NameR[9]) {
default: break;
case 'm': // 1 string to match.
if (memcmp(NameR.data()+10, ".ftz.f", 6))
break;
return Intrinsic::nvvm_fma_rm_ftz_f; // "vvm.fma.rm.ftz.
f"
case 'n': // 1 string to match.
if (memcmp(NameR.data()+10, ".ftz.f", 6))
break;
return Intrinsic::nvvm_fma_rn_ftz_f; // "vvm.fma.rn.ftz.
f"
case 'p': // 1 string to match.
if (memcmp(NameR.data()+10, ".ftz.f", 6))
break;
return Intrinsic::nvvm_fma_rp_ftz_f; // "vvm.fma.rp.ftz.
f"
case 'z': // 1 string to match.
if (memcmp(NameR.data()+10, ".ftz.f", 6))
break;
return Intrinsic::nvvm_fma_rz_ftz_f; // "vvm.fma.rz.ftz.
f"
} }
break; break;
} }
break; break;
} case 'l': // 2 strings to match.
break; if (memcmp(NameR.data()+5, "g2.approx.", 10))
case 14: // 87 strings to match.
switch (NameR[0]) {
default: break;
case '8': // 86 strings to match.
if (NameR.substr(1, 2) != "6.")
break; break;
switch (NameR[3]) { switch (NameR[15]) {
default: break; default: break;
case '3': // 9 strings to match. case 'd': // 1 string to match.
if (NameR.substr(4, 6) != "dnow.p") return Intrinsic::nvvm_lg2_approx_d; // "vvm.lg2.approx.d"
break; case 'f': // 1 string to match.
switch (NameR[10]) { return Intrinsic::nvvm_lg2_approx_f; // "vvm.lg2.approx.f"
default: break; }
case 'f': // 8 strings to match. break;
switch (NameR[11]) { case 'm': // 4 strings to match.
default: break; if (memcmp(NameR.data()+5, "ul.r", 4))
case '2': // 1 string to match.
if (NameR.substr(12, 2) != "id")
break;
return Intrinsic::x86_3dnow_pf2id; // "86.3dnow.pf2id"
case 'a': // 2 strings to match.
switch (NameR[12]) {
default: break;
case 'c': // 1 string to match.
if (NameR[13] != 'c')
break;
return Intrinsic::x86_3dnow_pfacc; // "86.3dnow.pfacc"
case 'd': // 1 string to match.
if (NameR[13] != 'd')
break;
return Intrinsic::x86_3dnow_pfadd; // "86.3dnow.pfadd"
}
break;
case 'm': // 3 strings to match.
switch (NameR[12]) {
default: break;
case 'a': // 1 string to match.
if (NameR[13] != 'x')
break;
return Intrinsic::x86_3dnow_pfmax; // "86.3dnow.pfmax"
case 'i': // 1 string to match.
if (NameR[13] != 'n')
break;
return Intrinsic::x86_3dnow_pfmin; // "86.3dnow.pfmin"
case 'u': // 1 string to match.
if (NameR[13] != 'l')
break;
return Intrinsic::x86_3dnow_pfmul; // "86.3dnow.pfmul"
}
break;
case 'r': // 1 string to match.
if (NameR.substr(12, 2) != "cp")
break;
return Intrinsic::x86_3dnow_pfrcp; // "86.3dnow.pfrcp"
case 's': // 1 string to match.
if (NameR.substr(12, 2) != "ub")
break;
return Intrinsic::x86_3dnow_pfsub; // "86.3dnow.pfsub"
}
break;
case 'i': // 1 string to match.
if (NameR.substr(11, 3) != "2fd")
break;
return Intrinsic::x86_3dnow_pi2fd; // "86.3dnow.pi2fd"
}
break; break;
case 'a': // 14 strings to match. switch (NameR[9]) {
if (NameR.substr(4, 5) != "vx2.p") default: break;
case 'm': // 1 string to match.
if (memcmp(NameR.data()+10, ".ftz.f", 6))
break; break;
switch (NameR[9]) { return Intrinsic::nvvm_mul_rm_ftz_f; // "vvm.mul.rm.ftz.f"
default: break; case 'n': // 1 string to match.
case 'a': // 5 strings to match. if (memcmp(NameR.data()+10, ".ftz.f", 6))
switch (NameR[10]) {
default: break;
case 'b': // 3 strings to match.
if (NameR.substr(11, 2) != "s.")
break;
switch (NameR[13]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::x86_avx2_pabs_b; // "86.avx2.pabs.b"
case 'd': // 1 string to match.
return Intrinsic::x86_avx2_pabs_d; // "86.avx2.pabs.d"
case 'w': // 1 string to match.
return Intrinsic::x86_avx2_pabs_w; // "86.avx2.pabs.w"
}
break;
case 'v': // 2 strings to match.
if (NameR.substr(11, 2) != "g.")
break;
switch (NameR[13]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::x86_avx2_pavg_b; // "86.avx2.pavg.b"
case 'w': // 1 string to match.
return Intrinsic::x86_avx2_pavg_w; // "86.avx2.pavg.w"
}
break;
}
break; break;
case 'e': // 1 string to match. return Intrinsic::nvvm_mul_rn_ftz_f; // "vvm.mul.rn.ftz.f"
if (NameR.substr(10, 4) != "rmps") case 'p': // 1 string to match.
break; if (memcmp(NameR.data()+10, ".ftz.f", 6))
return Intrinsic::x86_avx2_permps; // "86.avx2.permps"
case 's': // 8 strings to match.
switch (NameR[10]) {
default: break;
case 'l': // 3 strings to match.
if (NameR.substr(11, 2) != "l.")
break;
switch (NameR[13]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::x86_avx2_psll_d; // "86.avx2.psll.d"
case 'q': // 1 string to match.
return Intrinsic::x86_avx2_psll_q; // "86.avx2.psll.q"
case 'w': // 1 string to match.
return Intrinsic::x86_avx2_psll_w; // "86.avx2.psll.w"
}
break;
case 'r': // 5 strings to match.
switch (NameR[11]) {
default: break;
case 'a': // 2 strings to match.
if (NameR[12] != '.')
break;
switch (NameR[13]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::x86_avx2_psra_d; // "86.avx2.psra.d"
case 'w': // 1 string to match.
return Intrinsic::x86_avx2_psra_w; // "86.avx2.psra.w"
}
break;
case 'l': // 3 strings to match.
if (NameR[12] != '.')
break;
switch (NameR[13]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::x86_avx2_psrl_d; // "86.avx2.psrl.d"
case 'q': // 1 string to match.
return Intrinsic::x86_avx2_psrl_q; // "86.avx2.psrl.q"
case 'w': // 1 string to match.
return Intrinsic::x86_avx2_psrl_w; // "86.avx2.psrl.w"
}
break;
}
break;
}
break; break;
} return Intrinsic::nvvm_mul_rp_ftz_f; // "vvm.mul.rp.ftz.f"
case 'z': // 1 string to match.
if (memcmp(NameR.data()+10, ".ftz.f", 6))
break;
return Intrinsic::nvvm_mul_rz_ftz_f; // "vvm.mul.rz.ftz.f"
}
break;
case 'r': // 4 strings to match.
if (memcmp(NameR.data()+5, "cp.r", 4))
break; break;
case 'b': // 6 strings to match. switch (NameR[9]) {
if (NameR.substr(4, 3) != "mi.") default: break;
case 'm': // 1 string to match.
if (memcmp(NameR.data()+10, ".ftz.f", 6))
break; break;
switch (NameR[7]) { return Intrinsic::nvvm_rcp_rm_ftz_f; // "vvm.rcp.rm.ftz.f"
default: break; case 'n': // 1 string to match.
case 'b': // 2 strings to match. if (memcmp(NameR.data()+10, ".ftz.f", 6))
if (NameR.substr(8, 4) != "zhi.")
break;
switch (NameR[12]) {
default: break;
case '3': // 1 string to match.
if (NameR[13] != '2')
break;
return Intrinsic::x86_bmi_bzhi_32; // "86.bmi.bzhi.32"
case '6': // 1 string to match.
if (NameR[13] != '4')
break;
return Intrinsic::x86_bmi_bzhi_64; // "86.bmi.bzhi.64"
}
break; break;
case 'p': // 4 strings to match. return Intrinsic::nvvm_rcp_rn_ftz_f; // "vvm.rcp.rn.ftz.f"
switch (NameR[8]) { case 'p': // 1 string to match.
default: break; if (memcmp(NameR.data()+10, ".ftz.f", 6))
case 'd': // 2 strings to match.
if (NameR.substr(9, 3) != "ep.")
break;
switch (NameR[12]) {
default: break;
case '3': // 1 string to match.
if (NameR[13] != '2')
break;
return Intrinsic::x86_bmi_pdep_32; // "86.bmi.pdep.32"
case '6': // 1 string to match.
if (NameR[13] != '4')
break;
return Intrinsic::x86_bmi_pdep_64; // "86.bmi.pdep.64"
}
break;
case 'e': // 2 strings to match.
if (NameR.substr(9, 3) != "xt.")
break;
switch (NameR[12]) {
default: break;
case '3': // 1 string to match.
if (NameR[13] != '2')
break;
return Intrinsic::x86_bmi_pext_32; // "86.bmi.pext.32"
case '6': // 1 string to match.
if (NameR[13] != '4')
break;
return Intrinsic::x86_bmi_pext_64; // "86.bmi.pext.64"
}
break;
}
break; break;
} return Intrinsic::nvvm_rcp_rp_ftz_f; // "vvm.rcp.rp.ftz.f"
case 'z': // 1 string to match.
if (memcmp(NameR.data()+10, ".ftz.f", 6))
break;
return Intrinsic::nvvm_rcp_rz_ftz_f; // "vvm.rcp.rz.ftz.f"
}
break;
case 's': // 1 string to match.
if (memcmp(NameR.data()+5, "in.approx.f", 11))
break; break;
case 'm': // 21 strings to match. return Intrinsic::nvvm_sin_approx_f; // "vvm.sin.approx.f"
if (NameR.substr(4, 4) != "mx.p") }
break;
case 17: // 6 strings to match.
if (memcmp(NameR.data()+0, "vvm.", 4))
break;
switch (NameR[4]) {
default: break;
case 'b': // 1 string to match.
if (memcmp(NameR.data()+5, "arrier0.popc", 12))
break;
return Intrinsic::nvvm_barrier0_popc; // "vvm.barrier0.popc"
case 's': // 5 strings to match.
if (memcmp(NameR.data()+5, "qrt.", 4))
break;
switch (NameR[9]) {
default: break;
case 'a': // 1 string to match.
if (memcmp(NameR.data()+10, "pprox.f", 7))
break; break;
switch (NameR[8]) { return Intrinsic::nvvm_sqrt_approx_f; // "vvm.sqrt.approx
.f"
case 'r': // 4 strings to match.
switch (NameR[10]) {
default: break; default: break;
case 'a': // 2 strings to match. case 'm': // 1 string to match.
if (NameR.substr(9, 4) != "dds.") if (memcmp(NameR.data()+11, ".ftz.f", 6))
break;
switch (NameR[13]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::x86_mmx_padds_b; // "86.mmx.padds.b"
case 'w': // 1 string to match.
return Intrinsic::x86_mmx_padds_w; // "86.mmx.padds.w"
}
break;
case 'e': // 1 string to match.
if (NameR.substr(9, 5) != "xtr.w")
break; break;
return Intrinsic::x86_mmx_pextr_w; // "86.mmx.pextr.w" return Intrinsic::nvvm_sqrt_rm_ftz_f; // "vvm.sqrt.rm.ftz
case 'i': // 1 string to match. .f"
if (NameR.substr(9, 5) != "nsr.w") case 'n': // 1 string to match.
if (memcmp(NameR.data()+11, ".ftz.f", 6))
break; break;
return Intrinsic::x86_mmx_pinsr_w; // "86.mmx.pinsr.w" return Intrinsic::nvvm_sqrt_rn_ftz_f; // "vvm.sqrt.rn.ftz
case 'm': // 6 strings to match. .f"
switch (NameR[9]) { case 'p': // 1 string to match.
default: break; if (memcmp(NameR.data()+11, ".ftz.f", 6))
case 'a': // 2 strings to match.
if (NameR[10] != 'x')
break;
switch (NameR[11]) {
default: break;
case 's': // 1 string to match.
if (NameR.substr(12, 2) != ".w")
break;
return Intrinsic::x86_mmx_pmaxs_w; // "86.mmx.pmaxs.w"
case 'u': // 1 string to match.
if (NameR.substr(12, 2) != ".b")
break;
return Intrinsic::x86_mmx_pmaxu_b; // "86.mmx.pmaxu.b"
}
break; break;
case 'i': // 2 strings to match. return Intrinsic::nvvm_sqrt_rp_ftz_f; // "vvm.sqrt.rp.ftz
if (NameR[10] != 'n') .f"
break; case 'z': // 1 string to match.
switch (NameR[11]) { if (memcmp(NameR.data()+11, ".ftz.f", 6))
default: break;
case 's': // 1 string to match.
if (NameR.substr(12, 2) != ".w")
break;
return Intrinsic::x86_mmx_pmins_w; // "86.mmx.pmins.w"
case 'u': // 1 string to match.
if (NameR.substr(12, 2) != ".b")
break;
return Intrinsic::x86_mmx_pminu_b; // "86.mmx.pminu.b"
}
break; break;
case 'u': // 2 strings to match. return Intrinsic::nvvm_sqrt_rz_ftz_f; // "vvm.sqrt.rz.ftz
if (NameR[10] != 'l') .f"
break;
switch (NameR[11]) {
default: break;
case 'h': // 1 string to match.
if (NameR.substr(12, 2) != ".w")
break;
return Intrinsic::x86_mmx_pmulh_w; // "86.mmx.pmulh.w"
case 'l': // 1 string to match.
if (NameR.substr(12, 2) != ".w")
break;
return Intrinsic::x86_mmx_pmull_w; // "86.mmx.pmull.w"
}
break;
}
break;
case 's': // 11 strings to match.
switch (NameR[9]) {
default: break;
case 'a': // 1 string to match.
if (NameR.substr(10, 4) != "d.bw")
break;
return Intrinsic::x86_mmx_psad_bw; // "86.mmx.psad.bw"
case 'l': // 3 strings to match.
if (NameR.substr(10, 3) != "li.")
break;
switch (NameR[13]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::x86_mmx_pslli_d; // "86.mmx.pslli.d"
case 'q': // 1 string to match.
return Intrinsic::x86_mmx_pslli_q; // "86.mmx.pslli.q"
case 'w': // 1 string to match.
return Intrinsic::x86_mmx_pslli_w; // "86.mmx.pslli.w"
}
break;
case 'r': // 5 strings to match.
switch (NameR[10]) {
default: break;
case 'a': // 2 strings to match.
if (NameR.substr(11, 2) != "i.")
break;
switch (NameR[13]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::x86_mmx_psrai_d; // "86.mmx.psrai.d"
case 'w': // 1 string to match.
return Intrinsic::x86_mmx_psrai_w; // "86.mmx.psrai.w"
}
break;
case 'l': // 3 strings to match.
if (NameR.substr(11, 2) != "i.")
break;
switch (NameR[13]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::x86_mmx_psrli_d; // "86.mmx.psrli.d"
case 'q': // 1 string to match.
return Intrinsic::x86_mmx_psrli_q; // "86.mmx.psrli.q"
case 'w': // 1 string to match.
return Intrinsic::x86_mmx_psrli_w; // "86.mmx.psrli.w"
}
break;
}
break;
case 'u': // 2 strings to match.
if (NameR.substr(10, 3) != "bs.")
break;
switch (NameR[13]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::x86_mmx_psubs_b; // "86.mmx.psubs.b"
case 'w': // 1 string to match.
return Intrinsic::x86_mmx_psubs_w; // "86.mmx.psubs.w"
}
break;
}
break;
} }
break; break;
case 'r': // 4 strings to match. }
if (NameR[4] != 'd') break;
break; }
switch (NameR[5]) { break;
default: break; case 18: // 3 strings to match.
case 'f': // 2 strings to match. if (memcmp(NameR.data()+0, "vvm.", 4))
if (NameR.substr(6, 6) != "sbase.") break;
break; switch (NameR[4]) {
switch (NameR[12]) { default: break;
default: break; case 'r': // 2 strings to match.
case '3': // 1 string to match. if (memcmp(NameR.data()+5, "sqrt.approx.", 12))
if (NameR[13] != '2') break;
break; switch (NameR[17]) {
return Intrinsic::x86_rdfsbase_32; // "86.rdfsbase.32" default: break;
case '6': // 1 string to match. case 'd': // 1 string to match.
if (NameR[13] != '4') return Intrinsic::nvvm_rsqrt_approx_d; // "vvm.rsqrt.appro
break; x.d"
return Intrinsic::x86_rdfsbase_64; // "86.rdfsbase.64" case 'f': // 1 string to match.
} return Intrinsic::nvvm_rsqrt_approx_f; // "vvm.rsqrt.appro
break; x.f"
case 'g': // 2 strings to match. }
if (NameR.substr(6, 6) != "sbase.") break;
break; case 's': // 1 string to match.
switch (NameR[12]) { if (memcmp(NameR.data()+5, "aturate.ftz.f", 13))
default: break; break;
case '3': // 1 string to match. return Intrinsic::nvvm_saturate_ftz_f; // "vvm.saturate.ftz.f"
if (NameR[13] != '2') }
break; break;
return Intrinsic::x86_rdgsbase_32; // "86.rdgsbase.32" case 20: // 6 strings to match.
case '6': // 1 string to match. if (memcmp(NameR.data()+0, "vvm.", 4))
if (NameR[13] != '4') break;
break; switch (NameR[4]) {
return Intrinsic::x86_rdgsbase_64; // "86.rdgsbase.64" default: break;
} case 'c': // 1 string to match.
break; if (memcmp(NameR.data()+5, "os.approx.ftz.f", 15))
} break;
return Intrinsic::nvvm_cos_approx_ftz_f; // "vvm.cos.approx.
ftz.f"
case 'd': // 1 string to match.
if (memcmp(NameR.data()+5, "iv.approx.ftz.f", 15))
break;
return Intrinsic::nvvm_div_approx_ftz_f; // "vvm.div.approx.
ftz.f"
case 'e': // 1 string to match.
if (memcmp(NameR.data()+5, "x2.approx.ftz.f", 15))
break;
return Intrinsic::nvvm_ex2_approx_ftz_f; // "vvm.ex2.approx.
ftz.f"
case 'l': // 1 string to match.
if (memcmp(NameR.data()+5, "g2.approx.ftz.f", 15))
break;
return Intrinsic::nvvm_lg2_approx_ftz_f; // "vvm.lg2.approx.
ftz.f"
case 'r': // 1 string to match.
if (memcmp(NameR.data()+5, "cp.approx.ftz.d", 15))
break;
return Intrinsic::nvvm_rcp_approx_ftz_d; // "vvm.rcp.approx.
ftz.d"
case 's': // 1 string to match.
if (memcmp(NameR.data()+5, "in.approx.ftz.f", 15))
break;
return Intrinsic::nvvm_sin_approx_ftz_f; // "vvm.sin.approx.
ftz.f"
}
break;
case 21: // 1 string to match.
if (memcmp(NameR.data()+0, "vvm.sqrt.approx.ftz.f", 21))
break;
return Intrinsic::nvvm_sqrt_approx_ftz_f; // "vvm.sqrt.approx
.ftz.f"
case 22: // 1 string to match.
if (memcmp(NameR.data()+0, "vvm.rsqrt.approx.ftz.f", 22))
break;
return Intrinsic::nvvm_rsqrt_approx_ftz_f; // "vvm.rsqrt.appro
x.ftz.f"
case 23: // 3 strings to match.
if (memcmp(NameR.data()+0, "vvm.read.ptx.sreg.tid.", 22))
break;
switch (NameR[22]) {
default: break;
case 'x': // 1 string to match.
return Intrinsic::nvvm_read_ptx_sreg_tid_x; // "vvm.read.ptx.sr
eg.tid.x"
case 'y': // 1 string to match.
return Intrinsic::nvvm_read_ptx_sreg_tid_y; // "vvm.read.ptx.sr
eg.tid.y"
case 'z': // 1 string to match.
return Intrinsic::nvvm_read_ptx_sreg_tid_z; // "vvm.read.ptx.sr
eg.tid.z"
}
break;
case 24: // 3 strings to match.
if (memcmp(NameR.data()+0, "vvm.read.ptx.sreg.ntid.", 23))
break;
switch (NameR[23]) {
default: break;
case 'x': // 1 string to match.
return Intrinsic::nvvm_read_ptx_sreg_ntid_x; // "vvm.read.ptx.sr
eg.ntid.x"
case 'y': // 1 string to match.
return Intrinsic::nvvm_read_ptx_sreg_ntid_y; // "vvm.read.ptx.sr
eg.ntid.y"
case 'z': // 1 string to match.
return Intrinsic::nvvm_read_ptx_sreg_ntid_z; // "vvm.read.ptx.sr
eg.ntid.z"
}
break;
case 25: // 3 strings to match.
if (memcmp(NameR.data()+0, "vvm.read.ptx.sreg.ctaid.", 24))
break;
switch (NameR[24]) {
default: break;
case 'x': // 1 string to match.
return Intrinsic::nvvm_read_ptx_sreg_ctaid_x; // "vvm.read.ptx.sr
eg.ctaid.x"
case 'y': // 1 string to match.
return Intrinsic::nvvm_read_ptx_sreg_ctaid_y; // "vvm.read.ptx.sr
eg.ctaid.y"
case 'z': // 1 string to match.
return Intrinsic::nvvm_read_ptx_sreg_ctaid_z; // "vvm.read.ptx.sr
eg.ctaid.z"
}
break;
case 26: // 4 strings to match.
if (memcmp(NameR.data()+0, "vvm.read.ptx.sreg.", 18))
break;
switch (NameR[18]) {
default: break;
case 'n': // 3 strings to match.
if (memcmp(NameR.data()+19, "ctaid.", 6))
break;
switch (NameR[25]) {
default: break;
case 'x': // 1 string to match.
return Intrinsic::nvvm_read_ptx_sreg_nctaid_x; // "vvm.rea
d.ptx.sreg.nctaid.x"
case 'y': // 1 string to match.
return Intrinsic::nvvm_read_ptx_sreg_nctaid_y; // "vvm.rea
d.ptx.sreg.nctaid.y"
case 'z': // 1 string to match.
return Intrinsic::nvvm_read_ptx_sreg_nctaid_z; // "vvm.rea
d.ptx.sreg.nctaid.z"
}
break;
case 'w': // 1 string to match.
if (memcmp(NameR.data()+19, "arpsize", 7))
break;
return Intrinsic::nvvm_read_ptx_sreg_warpsize; // "vvm.read.ptx.sr
eg.warpsize"
}
break;
}
break; // end of 'n' case.
case 'o':
if (NameR.startswith("bjectsize.")) return Intrinsic::objectsize;
break; // end of 'o' case.
case 'p':
if (NameR.startswith("ow.")) return Intrinsic::pow;
if (NameR.startswith("owi.")) return Intrinsic::powi;
if (NameR.startswith("tr.annotation.")) return Intrinsic::ptr_annotatio
n;
switch (NameR.size()) {
default: break;
case 7: // 8 strings to match.
switch (NameR[0]) {
default: break;
case 'c': // 1 string to match.
if (memcmp(NameR.data()+1, "marker", 6))
break;
return Intrinsic::pcmarker; // "cmarker"
case 'p': // 6 strings to match.
if (memcmp(NameR.data()+1, "c.", 2))
break; break;
case 's': // 28 strings to match. switch (NameR[3]) {
if (NameR.substr(4, 2) != "se") default: break;
case 'd': // 5 strings to match.
if (memcmp(NameR.data()+4, "cb", 2))
break; break;
switch (NameR[6]) { switch (NameR[6]) {
default: break; default: break;
case '.': // 5 strings to match. case 'a': // 1 string to match.
switch (NameR[7]) { return Intrinsic::ppc_dcba; // "pc.dcba"
default: break; case 'f': // 1 string to match.
case 'l': // 1 string to match. return Intrinsic::ppc_dcbf; // "pc.dcbf"
if (NameR.substr(8, 6) != "dmxcsr") case 'i': // 1 string to match.
break; return Intrinsic::ppc_dcbi; // "pc.dcbi"
return Intrinsic::x86_sse_ldmxcsr; // "86.sse.ldmxcsr" case 't': // 1 string to match.
case 'p': // 1 string to match. return Intrinsic::ppc_dcbt; // "pc.dcbt"
if (NameR.substr(8, 6) != "shuf.w") case 'z': // 1 string to match.
break; return Intrinsic::ppc_dcbz; // "pc.dcbz"
return Intrinsic::x86_sse_pshuf_w; // "86.sse.pshuf.w" }
case 's': // 3 strings to match. break;
switch (NameR[8]) { case 's': // 1 string to match.
default: break; if (memcmp(NameR.data()+4, "ync", 3))
case 'q': // 2 strings to match.
if (NameR.substr(9, 3) != "rt.")
break;
switch (NameR[12]) {
default: break;
case 'p': // 1 string to match.
if (NameR[13] != 's')
break;
return Intrinsic::x86_sse_sqrt_ps; // "86.sse.sqrt.ps"
case 's': // 1 string to match.
if (NameR[13] != 's')
break;
return Intrinsic::x86_sse_sqrt_ss; // "86.sse.sqrt.ss"
}
break;
case 't': // 1 string to match.
if (NameR.substr(9, 5) != "mxcsr")
break;
return Intrinsic::x86_sse_stmxcsr; // "86.sse.stmxcsr"
}
break;
}
break; break;
case '2': // 22 strings to match. return Intrinsic::ppc_sync; // "pc.sync"
if (NameR[7] != '.') }
break; break;
switch (NameR[8]) { case 'r': // 1 string to match.
default: break; if (memcmp(NameR.data()+1, "efetch", 6))
case 'a': // 1 string to match.
if (NameR.substr(9, 5) != "dd.sd")
break;
return Intrinsic::x86_sse2_add_sd; // "86.sse2.add.sd"
case 'c': // 2 strings to match.
if (NameR.substr(9, 3) != "mp.")
break;
switch (NameR[12]) {
default: break;
case 'p': // 1 string to match.
if (NameR[13] != 'd')
break;
return Intrinsic::x86_sse2_cmp_pd; // "86.sse2.cmp.pd"
case 's': // 1 string to match.
if (NameR[13] != 'd')
break;
return Intrinsic::x86_sse2_cmp_sd; // "86.sse2.cmp.sd"
}
break;
case 'd': // 1 string to match.
if (NameR.substr(9, 5) != "iv.sd")
break;
return Intrinsic::x86_sse2_div_sd; // "86.sse2.div.sd"
case 'l': // 1 string to match.
if (NameR.substr(9, 5) != "fence")
break;
return Intrinsic::x86_sse2_lfence; // "86.sse2.lfence"
case 'm': // 6 strings to match.
switch (NameR[9]) {
default: break;
case 'a': // 2 strings to match.
if (NameR.substr(10, 2) != "x.")
break;
switch (NameR[12]) {
default: break;
case 'p': // 1 string to match.
if (NameR[13] != 'd')
break;
return Intrinsic::x86_sse2_max_pd; // "86.sse2.max.pd"
case 's': // 1 string to match.
if (NameR[13] != 'd')
break;
return Intrinsic::x86_sse2_max_sd; // "86.sse2.max.sd"
}
break;
case 'f': // 1 string to match.
if (NameR.substr(10, 4) != "ence")
break;
return Intrinsic::x86_sse2_mfence; // "86.sse2.mfence"
case 'i': // 2 strings to match.
if (NameR.substr(10, 2) != "n.")
break;
switch (NameR[12]) {
default: break;
case 'p': // 1 string to match.
if (NameR[13] != 'd')
break;
return Intrinsic::x86_sse2_min_pd; // "86.sse2.min.pd"
case 's': // 1 string to match.
if (NameR[13] != 'd')
break;
return Intrinsic::x86_sse2_min_sd; // "86.sse2.min.sd"
}
break;
case 'u': // 1 string to match.
if (NameR.substr(10, 4) != "l.sd")
break;
return Intrinsic::x86_sse2_mul_sd; // "86.sse2.mul.sd"
}
break;
case 'p': // 10 strings to match.
switch (NameR[9]) {
default: break;
case 'a': // 2 strings to match.
if (NameR.substr(10, 3) != "vg.")
break;
switch (NameR[13]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::x86_sse2_pavg_b; // "86.sse2.pavg.b"
case 'w': // 1 string to match.
return Intrinsic::x86_sse2_pavg_w; // "86.sse2.pavg.w"
}
break;
case 's': // 8 strings to match.
switch (NameR[10]) {
default: break;
case 'l': // 3 strings to match.
if (NameR.substr(11, 2) != "l.")
break;
switch (NameR[13]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::x86_sse2_psll_d; // "86.sse2.psll.d"
case 'q': // 1 string to match.
return Intrinsic::x86_sse2_psll_q; // "86.sse2.psll.q"
case 'w': // 1 string to match.
return Intrinsic::x86_sse2_psll_w; // "86.sse2.psll.w"
}
break;
case 'r': // 5 strings to match.
switch (NameR[11]) {
default: break;
case 'a': // 2 strings to match.
if (NameR[12] != '.')
break;
switch (NameR[13]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::x86_sse2_psra_d; // "86.sse2
.psra.d"
case 'w': // 1 string to match.
return Intrinsic::x86_sse2_psra_w; // "86.sse2
.psra.w"
}
break;
case 'l': // 3 strings to match.
if (NameR[12] != '.')
break;
switch (NameR[13]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::x86_sse2_psrl_d; // "86.sse2
.psrl.d"
case 'q': // 1 string to match.
return Intrinsic::x86_sse2_psrl_q; // "86.sse2
.psrl.q"
case 'w': // 1 string to match.
return Intrinsic::x86_sse2_psrl_w; // "86.sse2
.psrl.w"
}
break;
}
break;
}
break;
}
break;
case 's': // 1 string to match.
if (NameR.substr(9, 5) != "ub.sd")
break;
return Intrinsic::x86_sse2_sub_sd; // "86.sse2.sub.sd"
}
break;
case '3': // 1 string to match.
if (NameR.substr(7, 7) != ".ldu.dq")
break;
return Intrinsic::x86_sse3_ldu_dq; // "86.sse3.ldu.dq"
}
break; break;
case 'w': // 4 strings to match. return Intrinsic::prefetch; // "refetch"
if (NameR[4] != 'r') }
break; break;
switch (NameR[5]) { case 8: // 2 strings to match.
default: break; if (memcmp(NameR.data()+0, "pc.dcb", 6))
case 'f': // 2 strings to match. break;
if (NameR.substr(6, 6) != "sbase.") switch (NameR[6]) {
break; default: break;
switch (NameR[12]) { case 's': // 1 string to match.
default: break; if (NameR[7] != 't')
case '3': // 1 string to match. break;
if (NameR[13] != '2') return Intrinsic::ppc_dcbst; // "pc.dcbst"
break; case 'z': // 1 string to match.
return Intrinsic::x86_wrfsbase_32; // "86.wrfsbase.32" if (NameR[7] != 'l')
case '6': // 1 string to match. break;
if (NameR[13] != '4') return Intrinsic::ppc_dcbzl; // "pc.dcbzl"
break; }
return Intrinsic::x86_wrfsbase_64; // "86.wrfsbase.64" break;
} case 9: // 1 string to match.
break; if (memcmp(NameR.data()+0, "pc.dcbtst", 9))
case 'g': // 2 strings to match. break;
if (NameR.substr(6, 6) != "sbase.") return Intrinsic::ppc_dcbtst; // "pc.dcbtst"
break; case 11: // 5 strings to match.
switch (NameR[12]) { if (memcmp(NameR.data()+0, "tx.", 3))
default: break; break;
case '3': // 1 string to match. switch (NameR[3]) {
if (NameR[13] != '2') default: break;
break; case 'b': // 1 string to match.
return Intrinsic::x86_wrgsbase_32; // "86.wrgsbase.32" if (memcmp(NameR.data()+4, "ar.sync", 7))
case '6': // 1 string to match. break;
if (NameR[13] != '4') return Intrinsic::ptx_bar_sync; // "tx.bar.sync"
break; case 'r': // 4 strings to match.
return Intrinsic::x86_wrgsbase_64; // "86.wrgsbase.64" if (memcmp(NameR.data()+4, "ead.pm", 6))
}
break;
}
break; break;
switch (NameR[10]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::ptx_read_pm0; // "tx.read.pm0"
case '1': // 1 string to match.
return Intrinsic::ptx_read_pm1; // "tx.read.pm1"
case '2': // 1 string to match.
return Intrinsic::ptx_read_pm2; // "tx.read.pm2"
case '3': // 1 string to match.
return Intrinsic::ptx_read_pm3; // "tx.read.pm3"
} }
break; break;
}
break;
case 12: // 1 string to match.
if (memcmp(NameR.data()+0, "tx.read.smid", 12))
break;
return Intrinsic::ptx_read_smid; // "tx.read.smid"
case 13: // 6 strings to match.
if (memcmp(NameR.data()+0, "tx.read.", 8))
break;
switch (NameR[8]) {
default: break;
case 'c': // 1 string to match. case 'c': // 1 string to match.
if (NameR.substr(1, 13) != "ore.waitevent") if (memcmp(NameR.data()+9, "lock", 4))
break; break;
return Intrinsic::xcore_waitevent; // "core.waitevent" return Intrinsic::ptx_read_clock; // "tx.read.clock"
case 'n': // 1 string to match.
if (memcmp(NameR.data()+9, "smid", 4))
break;
return Intrinsic::ptx_read_nsmid; // "tx.read.nsmid"
case 't': // 4 strings to match.
if (memcmp(NameR.data()+9, "id.", 3))
break;
switch (NameR[12]) {
default: break;
case 'w': // 1 string to match.
return Intrinsic::ptx_read_tid_w; // "tx.read.tid.w"
case 'x': // 1 string to match.
return Intrinsic::ptx_read_tid_x; // "tx.read.tid.x"
case 'y': // 1 string to match.
return Intrinsic::ptx_read_tid_y; // "tx.read.tid.y"
case 'z': // 1 string to match.
return Intrinsic::ptx_read_tid_z; // "tx.read.tid.z"
}
break;
} }
break; break;
case 15: // 166 strings to match. case 14: // 12 strings to match.
switch (NameR[0]) { switch (NameR[0]) {
default: break; default: break;
case '8': // 165 strings to match. case 'p': // 5 strings to match.
if (NameR.substr(1, 2) != "6.") if (memcmp(NameR.data()+1, "c.altivec.", 10))
break; break;
switch (NameR[3]) { switch (NameR[11]) {
default: break; default: break;
case '3': // 3 strings to match. case 'd': // 2 strings to match.
if (NameR.substr(4, 4) != "dnow") if (NameR[12] != 's')
break; break;
switch (NameR[8]) { switch (NameR[13]) {
default: break; default: break;
case '.': // 1 string to match. case 's': // 1 string to match.
if (NameR.substr(9, 6) != "pfsubr") return Intrinsic::ppc_altivec_dss; // "pc.altivec.dss"
break; case 't': // 1 string to match.
return Intrinsic::x86_3dnow_pfsubr; // "86.3dnow.pfsubr return Intrinsic::ppc_altivec_dst; // "pc.altivec.dst"
"
case 'a': // 2 strings to match.
if (NameR.substr(9, 2) != ".p")
break;
switch (NameR[11]) {
default: break;
case 'f': // 1 string to match.
if (NameR.substr(12, 3) != "2iw")
break;
return Intrinsic::x86_3dnowa_pf2iw; // "86.3dnowa.pf2iw
"
case 'i': // 1 string to match.
if (NameR.substr(12, 3) != "2fw")
break;
return Intrinsic::x86_3dnowa_pi2fw; // "86.3dnowa.pi2fw
"
}
break;
} }
break; break;
case 'a': // 48 strings to match. case 'l': // 1 string to match.
switch (NameR[4]) { if (memcmp(NameR.data()+12, "vx", 2))
break;
return Intrinsic::ppc_altivec_lvx; // "pc.altivec.lvx"
case 'v': // 2 strings to match.
if (NameR[12] != 's')
break;
switch (NameR[13]) {
default: break; default: break;
case 'e': // 3 strings to match. case 'l': // 1 string to match.
if (NameR.substr(5, 7) != "sni.aes") return Intrinsic::ppc_altivec_vsl; // "pc.altivec.vsl"
case 'r': // 1 string to match.
return Intrinsic::ppc_altivec_vsr; // "pc.altivec.vsr"
}
break;
}
break;
case 't': // 7 strings to match.
if (memcmp(NameR.data()+1, "x.read.", 7))
break;
switch (NameR[8]) {
default: break;
case 'g': // 1 string to match.
if (memcmp(NameR.data()+9, "ridid", 5))
break;
return Intrinsic::ptx_read_gridid; // "tx.read.gridid"
case 'l': // 1 string to match.
if (memcmp(NameR.data()+9, "aneid", 5))
break;
return Intrinsic::ptx_read_laneid; // "tx.read.laneid"
case 'n': // 4 strings to match.
if (memcmp(NameR.data()+9, "tid.", 4))
break;
switch (NameR[13]) {
default: break;
case 'w': // 1 string to match.
return Intrinsic::ptx_read_ntid_w; // "tx.read.ntid.w"
case 'x': // 1 string to match.
return Intrinsic::ptx_read_ntid_x; // "tx.read.ntid.x"
case 'y': // 1 string to match.
return Intrinsic::ptx_read_ntid_y; // "tx.read.ntid.y"
case 'z': // 1 string to match.
return Intrinsic::ptx_read_ntid_z; // "tx.read.ntid.z"
}
break;
case 'w': // 1 string to match.
if (memcmp(NameR.data()+9, "arpid", 5))
break;
return Intrinsic::ptx_read_warpid; // "tx.read.warpid"
}
break;
}
break;
case 15: // 23 strings to match.
switch (NameR[0]) {
default: break;
case 'p': // 17 strings to match.
if (memcmp(NameR.data()+1, "c.altivec.", 10))
break;
switch (NameR[11]) {
default: break;
case 'd': // 1 string to match.
if (memcmp(NameR.data()+12, "stt", 3))
break;
return Intrinsic::ppc_altivec_dstt; // "pc.altivec.dstt"
case 'l': // 3 strings to match.
if (NameR[12] != 'v')
break;
switch (NameR[13]) {
default: break;
case 's': // 2 strings to match.
switch (NameR[14]) {
default: break;
case 'l': // 1 string to match.
return Intrinsic::ppc_altivec_lvsl; // "pc.altivec.lvsl
"
case 'r': // 1 string to match.
return Intrinsic::ppc_altivec_lvsr; // "pc.altivec.lvsr
"
}
break;
case 'x': // 1 string to match.
if (NameR[14] != 'l')
break; break;
switch (NameR[12]) { return Intrinsic::ppc_altivec_lvxl; // "pc.altivec.lvxl
"
}
break;
case 's': // 1 string to match.
if (memcmp(NameR.data()+12, "tvx", 3))
break;
return Intrinsic::ppc_altivec_stvx; // "pc.altivec.stvx"
case 'v': // 12 strings to match.
switch (NameR[12]) {
default: break;
case 'r': // 3 strings to match.
if (NameR[13] != 'l')
break;
switch (NameR[14]) {
default: break; default: break;
case 'd': // 1 string to match. case 'b': // 1 string to match.
if (NameR.substr(13, 2) != "ec") return Intrinsic::ppc_altivec_vrlb; // "pc.altivec.vrlb
"
case 'h': // 1 string to match.
return Intrinsic::ppc_altivec_vrlh; // "pc.altivec.vrlh
"
case 'w': // 1 string to match.
return Intrinsic::ppc_altivec_vrlw; // "pc.altivec.vrlw
"
}
break;
case 's': // 9 strings to match.
switch (NameR[13]) {
default: break;
case 'e': // 1 string to match.
if (NameR[14] != 'l')
break; break;
return Intrinsic::x86_aesni_aesdec; // "86.aesni.aesdec return Intrinsic::ppc_altivec_vsel; // "pc.altivec.vsel
" "
case 'l': // 4 strings to match.
switch (NameR[14]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::ppc_altivec_vslb; // "pc.altivec.vslb
"
case 'h': // 1 string to match.
return Intrinsic::ppc_altivec_vslh; // "pc.altivec.vslh
"
case 'o': // 1 string to match.
return Intrinsic::ppc_altivec_vslo; // "pc.altivec.vslo
"
case 'w': // 1 string to match.
return Intrinsic::ppc_altivec_vslw; // "pc.altivec.vslw
"
}
break;
case 'r': // 4 strings to match.
switch (NameR[14]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::ppc_altivec_vsrb; // "pc.altivec.vsrb
"
case 'h': // 1 string to match.
return Intrinsic::ppc_altivec_vsrh; // "pc.altivec.vsrh
"
case 'o': // 1 string to match.
return Intrinsic::ppc_altivec_vsro; // "pc.altivec.vsro
"
case 'w': // 1 string to match.
return Intrinsic::ppc_altivec_vsrw; // "pc.altivec.vsrw
"
}
break;
}
break;
}
break;
}
break;
case 't': // 6 strings to match.
if (memcmp(NameR.data()+1, "x.read.", 7))
break;
switch (NameR[8]) {
default: break;
case 'c': // 5 strings to match.
switch (NameR[9]) {
default: break;
case 'l': // 1 string to match.
if (memcmp(NameR.data()+10, "ock64", 5))
break;
return Intrinsic::ptx_read_clock64; // "tx.read.clock64
"
case 't': // 4 strings to match.
if (memcmp(NameR.data()+10, "aid.", 4))
break;
switch (NameR[14]) {
default: break;
case 'w': // 1 string to match.
return Intrinsic::ptx_read_ctaid_w; // "tx.read.ctaid.w
"
case 'x': // 1 string to match.
return Intrinsic::ptx_read_ctaid_x; // "tx.read.ctaid.x
"
case 'y': // 1 string to match.
return Intrinsic::ptx_read_ctaid_y; // "tx.read.ctaid.y
"
case 'z': // 1 string to match.
return Intrinsic::ptx_read_ctaid_z; // "tx.read.ctaid.z
"
}
break;
}
break;
case 'n': // 1 string to match.
if (memcmp(NameR.data()+9, "warpid", 6))
break;
return Intrinsic::ptx_read_nwarpid; // "tx.read.nwarpid"
}
break;
}
break;
case 16: // 21 strings to match.
switch (NameR[0]) {
default: break;
case 'p': // 17 strings to match.
if (memcmp(NameR.data()+1, "c.altivec.", 10))
break;
switch (NameR[11]) {
default: break;
case 'd': // 1 string to match.
if (memcmp(NameR.data()+12, "stst", 4))
break;
return Intrinsic::ppc_altivec_dstst; // "pc.altivec.dstst"
case 'l': // 3 strings to match.
if (memcmp(NameR.data()+12, "ve", 2))
break;
switch (NameR[14]) {
default: break;
case 'b': // 1 string to match.
if (NameR[15] != 'x')
break;
return Intrinsic::ppc_altivec_lvebx; // "pc.altivec.lveb
x"
case 'h': // 1 string to match.
if (NameR[15] != 'x')
break;
return Intrinsic::ppc_altivec_lvehx; // "pc.altivec.lveh
x"
case 'w': // 1 string to match.
if (NameR[15] != 'x')
break;
return Intrinsic::ppc_altivec_lvewx; // "pc.altivec.lvew
x"
}
break;
case 's': // 1 string to match.
if (memcmp(NameR.data()+12, "tvxl", 4))
break;
return Intrinsic::ppc_altivec_stvxl; // "pc.altivec.stvxl"
case 'v': // 12 strings to match.
switch (NameR[12]) {
default: break;
case 'c': // 2 strings to match.
if (NameR[13] != 'f')
break;
switch (NameR[14]) {
default: break;
case 's': // 1 string to match.
if (NameR[15] != 'x')
break;
return Intrinsic::ppc_altivec_vcfsx; // "pc.altivec.vcfs
x"
case 'u': // 1 string to match.
if (NameR[15] != 'x')
break;
return Intrinsic::ppc_altivec_vcfux; // "pc.altivec.vcfu
x"
}
break;
case 'p': // 2 strings to match.
switch (NameR[13]) {
default: break;
case 'e': // 1 string to match. case 'e': // 1 string to match.
if (NameR.substr(13, 2) != "nc") if (memcmp(NameR.data()+14, "rm", 2))
break; break;
return Intrinsic::x86_aesni_aesenc; // "86.aesni.aesenc return Intrinsic::ppc_altivec_vperm; // "pc.altivec.vper
" m"
case 'i': // 1 string to match. case 'k': // 1 string to match.
if (NameR.substr(13, 2) != "mc") if (memcmp(NameR.data()+14, "px", 2))
break; break;
return Intrinsic::x86_aesni_aesimc; // "86.aesni.aesimc " return Intrinsic::ppc_altivec_vpkpx; // "pc.altivec.vpkp x"
} }
break; break;
case 'v': // 45 strings to match. case 'r': // 5 strings to match.
if (NameR[5] != 'x') switch (NameR[13]) {
break;
switch (NameR[6]) {
default: break; default: break;
case '.': // 1 string to match. case 'e': // 1 string to match.
if (NameR.substr(7, 8) != "vzeroall") if (memcmp(NameR.data()+14, "fp", 2))
break; break;
return Intrinsic::x86_avx_vzeroall; // "86.avx.vzeroall return Intrinsic::ppc_altivec_vrefp; // "pc.altivec.vref
" p"
case '2': // 44 strings to match. case 'f': // 4 strings to match.
if (NameR[7] != '.') if (NameR[14] != 'i')
break; break;
switch (NameR[8]) { switch (NameR[15]) {
default: break; default: break;
case 'm': // 1 string to match. case 'm': // 1 string to match.
if (NameR.substr(9, 6) != "psadbw") return Intrinsic::ppc_altivec_vrfim; // "pc.altivec.vrfi
break; m"
return Intrinsic::x86_avx2_mpsadbw; // "86.avx2.mpsadbw case 'n': // 1 string to match.
" return Intrinsic::ppc_altivec_vrfin; // "pc.altivec.vrfi
case 'p': // 43 strings to match. n"
switch (NameR[9]) { case 'p': // 1 string to match.
default: break; return Intrinsic::ppc_altivec_vrfip; // "pc.altivec.vrfi
case 'a': // 2 strings to match. p"
if (NameR.substr(10, 4) != "dds.") case 'z': // 1 string to match.
break; return Intrinsic::ppc_altivec_vrfiz; // "pc.altivec.vrfi
switch (NameR[14]) { z"
default: break;
case 'b': // 1 string to match.
return Intrinsic::x86_avx2_padds_b; // "86.avx2
.padds.b"
case 'w': // 1 string to match.
return Intrinsic::x86_avx2_padds_w; // "86.avx2
.padds.w"
}
break;
case 'b': // 1 string to match.
if (NameR.substr(10, 5) != "lendw")
break;
return Intrinsic::x86_avx2_pblendw; // "86.avx2.pblendw
"
case 'h': // 4 strings to match.
switch (NameR[10]) {
default: break;
case 'a': // 2 strings to match.
if (NameR.substr(11, 3) != "dd.")
break;
switch (NameR[14]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::x86_avx2_phadd_d; // "86.avx2
.phadd.d"
case 'w': // 1 string to match.
return Intrinsic::x86_avx2_phadd_w; // "86.avx2
.phadd.w"
}
break;
case 's': // 2 strings to match.
if (NameR.substr(11, 3) != "ub.")
break;
switch (NameR[14]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::x86_avx2_phsub_d; // "86.avx2
.phsub.d"
case 'w': // 1 string to match.
return Intrinsic::x86_avx2_phsub_w; // "86.avx2
.phsub.w"
}
break;
}
break;
case 'm': // 14 strings to match.
switch (NameR[10]) {
default: break;
case 'a': // 6 strings to match.
if (NameR[11] != 'x')
break;
switch (NameR[12]) {
default: break;
case 's': // 3 strings to match.
if (NameR[13] != '.')
break;
switch (NameR[14]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::x86_avx2_pmaxs_b; // "86.avx2
.pmaxs.b"
case 'd': // 1 string to match.
return Intrinsic::x86_avx2_pmaxs_d; // "86.avx2
.pmaxs.d"
case 'w': // 1 string to match.
return Intrinsic::x86_avx2_pmaxs_w; // "86.avx2
.pmaxs.w"
}
break;
case 'u': // 3 strings to match.
if (NameR[13] != '.')
break;
switch (NameR[14]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::x86_avx2_pmaxu_b; // "86.avx2
.pmaxu.b"
case 'd': // 1 string to match.
return Intrinsic::x86_avx2_pmaxu_d; // "86.avx2
.pmaxu.d"
case 'w': // 1 string to match.
return Intrinsic::x86_avx2_pmaxu_w; // "86.avx2
.pmaxu.w"
}
break;
}
break;
case 'i': // 6 strings to match.
if (NameR[11] != 'n')
break;
switch (NameR[12]) {
default: break;
case 's': // 3 strings to match.
if (NameR[13] != '.')
break;
switch (NameR[14]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::x86_avx2_pmins_b; // "86.avx2
.pmins.b"
case 'd': // 1 string to match.
return Intrinsic::x86_avx2_pmins_d; // "86.avx2
.pmins.d"
case 'w': // 1 string to match.
return Intrinsic::x86_avx2_pmins_w; // "86.avx2
.pmins.w"
}
break;
case 'u': // 3 strings to match.
if (NameR[13] != '.')
break;
switch (NameR[14]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::x86_avx2_pminu_b; // "86.avx2
.pminu.b"
case 'd': // 1 string to match.
return Intrinsic::x86_avx2_pminu_d; // "86.avx2
.pminu.d"
case 'w': // 1 string to match.
return Intrinsic::x86_avx2_pminu_w; // "86.avx2
.pminu.w"
}
break;
}
break;
case 'u': // 2 strings to match.
if (NameR[11] != 'l')
break;
switch (NameR[12]) {
default: break;
case '.': // 1 string to match.
if (NameR.substr(13, 2) != "dq")
break;
return Intrinsic::x86_avx2_pmul_dq; // "86.avx2
.pmul.dq"
case 'h': // 1 string to match.
if (NameR.substr(13, 2) != ".w")
break;
return Intrinsic::x86_avx2_pmulh_w; // "86.avx2
.pmulh.w"
}
break;
}
break;
case 's': // 22 strings to match.
switch (NameR[10]) {
default: break;
case 'a': // 1 string to match.
if (NameR.substr(11, 4) != "d.bw")
break;
return Intrinsic::x86_avx2_psad_bw; // "86.avx2
.psad.bw"
case 'h': // 1 string to match.
if (NameR.substr(11, 4) != "uf.b")
break;
return Intrinsic::x86_avx2_pshuf_b; // "86.avx2
.pshuf.b"
case 'i': // 3 strings to match.
if (NameR.substr(11, 3) != "gn.")
break;
switch (NameR[14]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::x86_avx2_psign_b; // "86.avx2
.psign.b"
case 'd': // 1 string to match.
return Intrinsic::x86_avx2_psign_d; // "86.avx2
.psign.d"
case 'w': // 1 string to match.
return Intrinsic::x86_avx2_psign_w; // "86.avx2
.psign.w"
}
break;
case 'l': // 6 strings to match.
if (NameR[11] != 'l')
break;
switch (NameR[12]) {
default: break;
case '.': // 1 string to match.
if (NameR.substr(13, 2) != "dq")
break;
return Intrinsic::x86_avx2_psll_dq; // "86.avx2
.psll.dq"
case 'i': // 3 strings to match.
if (NameR[13] != '.')
break;
switch (NameR[14]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::x86_avx2_pslli_d; // "86.avx2
.pslli.d"
case 'q': // 1 string to match.
return Intrinsic::x86_avx2_pslli_q; // "86.avx2
.pslli.q"
case 'w': // 1 string to match.
return Intrinsic::x86_avx2_pslli_w; // "86.avx2
.pslli.w"
}
break;
case 'v': // 2 strings to match.
if (NameR[13] != '.')
break;
switch (NameR[14]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::x86_avx2_psllv_d; // "86.avx2
.psllv.d"
case 'q': // 1 string to match.
return Intrinsic::x86_avx2_psllv_q; // "86.avx2
.psllv.q"
}
break;
}
break;
case 'r': // 9 strings to match.
switch (NameR[11]) {
default: break;
case 'a': // 3 strings to match.
switch (NameR[12]) {
default: break;
case 'i': // 2 strings to match.
if (NameR[13] != '.')
break;
switch (NameR[14]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::x86_avx2_psrai_d; // "86.avx2
.psrai.d"
case 'w': // 1 string to match.
return Intrinsic::x86_avx2_psrai_w; // "86.avx2
.psrai.w"
}
break;
case 'v': // 1 string to match.
if (NameR.substr(13, 2) != ".d")
break;
return Intrinsic::x86_avx2_psrav_d; // "86.avx2
.psrav.d"
}
break;
case 'l': // 6 strings to match.
switch (NameR[12]) {
default: break;
case '.': // 1 string to match.
if (NameR.substr(13, 2) != "dq")
break;
return Intrinsic::x86_avx2_psrl_dq; // "86.avx2
.psrl.dq"
case 'i': // 3 strings to match.
if (NameR[13] != '.')
break;
switch (NameR[14]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::x86_avx2_psrli_d; // "86.avx2
.psrli.d"
case 'q': // 1 string to match.
return Intrinsic::x86_avx2_psrli_q; // "86.avx2
.psrli.q"
case 'w': // 1 string to match.
return Intrinsic::x86_avx2_psrli_w; // "86.avx2
.psrli.w"
}
break;
case 'v': // 2 strings to match.
if (NameR[13] != '.')
break;
switch (NameR[14]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::x86_avx2_psrlv_d; // "86.avx2
.psrlv.d"
case 'q': // 1 string to match.
return Intrinsic::x86_avx2_psrlv_q; // "86.avx2
.psrlv.q"
}
break;
}
break;
}
break;
case 'u': // 2 strings to match.
if (NameR.substr(11, 3) != "bs.")
break;
switch (NameR[14]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::x86_avx2_psubs_b; // "86.avx2
.psubs.b"
case 'w': // 1 string to match.
return Intrinsic::x86_avx2_psubs_w; // "86.avx2
.psubs.w"
}
break;
}
break;
}
break;
} }
break; break;
} }
break; break;
} case 's': // 3 strings to match.
break; if (memcmp(NameR.data()+13, "ra", 2))
case 'b': // 2 strings to match.
if (NameR.substr(4, 9) != "mi.bextr.")
break;
switch (NameR[13]) {
default: break;
case '3': // 1 string to match.
if (NameR[14] != '2')
break; break;
return Intrinsic::x86_bmi_bextr_32; // "86.bmi.bextr.32 switch (NameR[15]) {
" default: break;
case '6': // 1 string to match. case 'b': // 1 string to match.
if (NameR[14] != '4') return Intrinsic::ppc_altivec_vsrab; // "pc.altivec.vsra
break; b"
return Intrinsic::x86_bmi_bextr_64; // "86.bmi.bextr.64 case 'h': // 1 string to match.
" return Intrinsic::ppc_altivec_vsrah; // "pc.altivec.vsra
h"
case 'w': // 1 string to match.
return Intrinsic::ppc_altivec_vsraw; // "pc.altivec.vsra
w"
}
break;
} }
break; break;
case 'm': // 19 strings to match. }
if (NameR.substr(4, 3) != "mx.") break;
case 't': // 4 strings to match.
if (memcmp(NameR.data()+1, "x.read.nctaid.", 14))
break;
switch (NameR[15]) {
default: break;
case 'w': // 1 string to match.
return Intrinsic::ptx_read_nctaid_w; // "tx.read.nctaid.w"
case 'x': // 1 string to match.
return Intrinsic::ptx_read_nctaid_x; // "tx.read.nctaid.x"
case 'y': // 1 string to match.
return Intrinsic::ptx_read_nctaid_y; // "tx.read.nctaid.y"
case 'z': // 1 string to match.
return Intrinsic::ptx_read_nctaid_z; // "tx.read.nctaid.z"
}
break;
}
break;
case 17: // 29 strings to match.
if (memcmp(NameR.data()+0, "pc.altivec.", 11))
break;
switch (NameR[11]) {
default: break;
case 'd': // 2 strings to match.
if (NameR[12] != 's')
break;
switch (NameR[13]) {
default: break;
case 's': // 1 string to match.
if (memcmp(NameR.data()+14, "all", 3))
break; break;
switch (NameR[7]) { return Intrinsic::ppc_altivec_dssall; // "pc.altivec.dssa
ll"
case 't': // 1 string to match.
if (memcmp(NameR.data()+14, "stt", 3))
break;
return Intrinsic::ppc_altivec_dststt; // "pc.altivec.dsts
tt"
}
break;
case 'm': // 2 strings to match.
switch (NameR[12]) {
default: break;
case 'f': // 1 string to match.
if (memcmp(NameR.data()+13, "vscr", 4))
break;
return Intrinsic::ppc_altivec_mfvscr; // "pc.altivec.mfvs
cr"
case 't': // 1 string to match.
if (memcmp(NameR.data()+13, "vscr", 4))
break;
return Intrinsic::ppc_altivec_mtvscr; // "pc.altivec.mtvs
cr"
}
break;
case 's': // 3 strings to match.
if (memcmp(NameR.data()+12, "tve", 3))
break;
switch (NameR[15]) {
default: break;
case 'b': // 1 string to match.
if (NameR[16] != 'x')
break;
return Intrinsic::ppc_altivec_stvebx; // "pc.altivec.stve
bx"
case 'h': // 1 string to match.
if (NameR[16] != 'x')
break;
return Intrinsic::ppc_altivec_stvehx; // "pc.altivec.stve
hx"
case 'w': // 1 string to match.
if (NameR[16] != 'x')
break;
return Intrinsic::ppc_altivec_stvewx; // "pc.altivec.stve
wx"
}
break;
case 'v': // 22 strings to match.
switch (NameR[12]) {
default: break;
case 'a': // 6 strings to match.
if (memcmp(NameR.data()+13, "vg", 2))
break;
switch (NameR[15]) {
default: break; default: break;
case 'm': // 2 strings to match. case 's': // 3 strings to match.
switch (NameR[8]) { switch (NameR[16]) {
default: break; default: break;
case 'a': // 1 string to match. case 'b': // 1 string to match.
if (NameR.substr(9, 6) != "skmovq") return Intrinsic::ppc_altivec_vavgsb; // "pc.altivec.vavg
break; sb"
return Intrinsic::x86_mmx_maskmovq; // "86.mmx.maskmovq case 'h': // 1 string to match.
" return Intrinsic::ppc_altivec_vavgsh; // "pc.altivec.vavg
case 'o': // 1 string to match. sh"
if (NameR.substr(9, 6) != "vnt.dq") case 'w': // 1 string to match.
break; return Intrinsic::ppc_altivec_vavgsw; // "pc.altivec.vavg
return Intrinsic::x86_mmx_movnt_dq; // "86.mmx.movnt.dq sw"
"
} }
break; break;
case 'p': // 17 strings to match. case 'u': // 3 strings to match.
switch (NameR[8]) { switch (NameR[16]) {
default: break; default: break;
case 'a': // 5 strings to match. case 'b': // 1 string to match.
switch (NameR[9]) { return Intrinsic::ppc_altivec_vavgub; // "pc.altivec.vavg
default: break; ub"
case 'c': // 3 strings to match. case 'h': // 1 string to match.
if (NameR[10] != 'k') return Intrinsic::ppc_altivec_vavguh; // "pc.altivec.vavg
break; uh"
switch (NameR[11]) { case 'w': // 1 string to match.
default: break; return Intrinsic::ppc_altivec_vavguw; // "pc.altivec.vavg
case 's': // 2 strings to match. uw"
if (NameR[12] != 's') }
break; break;
switch (NameR[13]) { }
default: break; break;
case 'd': // 1 string to match. case 'c': // 2 strings to match.
if (NameR[14] != 'w') if (NameR[13] != 't')
break; break;
return Intrinsic::x86_mmx_packssdw; // "86.mmx. switch (NameR[14]) {
packssdw" default: break;
case 'w': // 1 string to match. case 's': // 1 string to match.
if (NameR[14] != 'b') if (memcmp(NameR.data()+15, "xs", 2))
break;
return Intrinsic::x86_mmx_packsswb; // "86.mmx.
packsswb"
}
break;
case 'u': // 1 string to match.
if (NameR.substr(12, 3) != "swb")
break;
return Intrinsic::x86_mmx_packuswb; // "86.mmx.packuswb
"
}
break;
case 'd': // 2 strings to match.
if (NameR.substr(10, 4) != "dus.")
break;
switch (NameR[14]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::x86_mmx_paddus_b; // "86.mmx.paddus.b
"
case 'w': // 1 string to match.
return Intrinsic::x86_mmx_paddus_w; // "86.mmx.paddus.w
"
}
break;
}
break; break;
case 'c': // 6 strings to match. return Intrinsic::ppc_altivec_vctsxs; // "pc.altivec.vcts
if (NameR.substr(9, 2) != "mp") xs"
break; case 'u': // 1 string to match.
switch (NameR[11]) { if (memcmp(NameR.data()+15, "xs", 2))
default: break;
case 'e': // 3 strings to match.
if (NameR.substr(12, 2) != "q.")
break;
switch (NameR[14]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::x86_mmx_pcmpeq_b; // "86.mmx.pcmpeq.b
"
case 'd': // 1 string to match.
return Intrinsic::x86_mmx_pcmpeq_d; // "86.mmx.pcmpeq.d
"
case 'w': // 1 string to match.
return Intrinsic::x86_mmx_pcmpeq_w; // "86.mmx.pcmpeq.w
"
}
break;
case 'g': // 3 strings to match.
if (NameR.substr(12, 2) != "t.")
break;
switch (NameR[14]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::x86_mmx_pcmpgt_b; // "86.mmx.pcmpgt.b
"
case 'd': // 1 string to match.
return Intrinsic::x86_mmx_pcmpgt_d; // "86.mmx.pcmpgt.d
"
case 'w': // 1 string to match.
return Intrinsic::x86_mmx_pcmpgt_w; // "86.mmx.pcmpgt.w
"
}
break;
}
break; break;
case 'm': // 4 strings to match. return Intrinsic::ppc_altivec_vctuxs; // "pc.altivec.vctu
switch (NameR[9]) { xs"
default: break; }
case 'a': // 1 string to match. break;
if (NameR.substr(10, 5) != "dd.wd") case 'm': // 14 strings to match.
break; switch (NameR[13]) {
return Intrinsic::x86_mmx_pmadd_wd; // "86.mmx.pmadd.wd default: break;
" case 'a': // 7 strings to match.
case 'o': // 1 string to match. if (NameR[14] != 'x')
if (NameR.substr(10, 5) != "vmskb") break;
break; switch (NameR[15]) {
return Intrinsic::x86_mmx_pmovmskb; // "86.mmx.pmovmskb default: break;
" case 'f': // 1 string to match.
case 'u': // 2 strings to match. if (NameR[16] != 'p')
if (NameR[10] != 'l')
break;
switch (NameR[11]) {
default: break;
case 'h': // 1 string to match.
if (NameR.substr(12, 3) != "u.w")
break;
return Intrinsic::x86_mmx_pmulhu_w; // "86.mmx.pmulhu.w
"
case 'u': // 1 string to match.
if (NameR.substr(12, 3) != ".dq")
break;
return Intrinsic::x86_mmx_pmulu_dq; // "86.mmx.pmulu.dq
"
}
break; break;
return Intrinsic::ppc_altivec_vmaxfp; // "pc.altivec.vmax
fp"
case 's': // 3 strings to match.
switch (NameR[16]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::ppc_altivec_vmaxsb; // "pc.altivec.vmax
sb"
case 'h': // 1 string to match.
return Intrinsic::ppc_altivec_vmaxsh; // "pc.altivec.vmax
sh"
case 'w': // 1 string to match.
return Intrinsic::ppc_altivec_vmaxsw; // "pc.altivec.vmax
sw"
} }
break; break;
case 's': // 2 strings to match. case 'u': // 3 strings to match.
if (NameR.substr(9, 5) != "ubus.") switch (NameR[16]) {
break;
switch (NameR[14]) {
default: break; default: break;
case 'b': // 1 string to match. case 'b': // 1 string to match.
return Intrinsic::x86_mmx_psubus_b; // "86.mmx.psubus.b return Intrinsic::ppc_altivec_vmaxub; // "pc.altivec.vmax
" ub"
case 'h': // 1 string to match.
return Intrinsic::ppc_altivec_vmaxuh; // "pc.altivec.vmax
uh"
case 'w': // 1 string to match. case 'w': // 1 string to match.
return Intrinsic::x86_mmx_psubus_w; // "86.mmx.psubus.w " return Intrinsic::ppc_altivec_vmaxuw; // "pc.altivec.vmax uw"
} }
break; break;
} }
break; break;
} case 'i': // 7 strings to match.
break; if (NameR[14] != 'n')
case 's': // 53 strings to match.
if (NameR[4] != 's')
break;
switch (NameR[5]) {
default: break;
case 'e': // 50 strings to match.
switch (NameR[6]) {
default: break;
case '.': // 8 strings to match.
switch (NameR[7]) {
default: break;
case 'c': // 6 strings to match.
if (NameR.substr(8, 2) != "vt")
break;
switch (NameR[10]) {
default: break;
case 'p': // 4 strings to match.
switch (NameR[11]) {
default: break;
case 'd': // 1 string to match.
if (NameR.substr(12, 3) != "2pi")
break;
return Intrinsic::x86_sse_cvtpd2pi; // "86.sse.
cvtpd2pi"
case 'i': // 2 strings to match.
if (NameR.substr(12, 2) != "2p")
break;
switch (NameR[14]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::x86_sse_cvtpi2pd; // "86.sse.
cvtpi2pd"
case 's': // 1 string to match.
return Intrinsic::x86_sse_cvtpi2ps; // "86.sse.
cvtpi2ps"
}
break;
case 's': // 1 string to match.
if (NameR.substr(12, 3) != "2pi")
break;
return Intrinsic::x86_sse_cvtps2pi; // "86.sse.
cvtps2pi"
}
break;
case 's': // 2 strings to match.
switch (NameR[11]) {
default: break;
case 'i': // 1 string to match.
if (NameR.substr(12, 3) != "2ss")
break;
return Intrinsic::x86_sse_cvtsi2ss; // "86.sse.
cvtsi2ss"
case 's': // 1 string to match.
if (NameR.substr(12, 3) != "2si")
break;
return Intrinsic::x86_sse_cvtss2si; // "86.sse.
cvtss2si"
}
break;
}
break;
case 'r': // 2 strings to match.
if (NameR.substr(8, 5) != "sqrt.")
break;
switch (NameR[13]) {
default: break;
case 'p': // 1 string to match.
if (NameR[14] != 's')
break;
return Intrinsic::x86_sse_rsqrt_ps; // "86.sse.rsqrt.ps
"
case 's': // 1 string to match.
if (NameR[14] != 's')
break;
return Intrinsic::x86_sse_rsqrt_ss; // "86.sse.rsqrt.ss
"
}
break;
}
break; break;
case '2': // 23 strings to match. switch (NameR[15]) {
if (NameR[7] != '.') default: break;
case 'f': // 1 string to match.
if (NameR[16] != 'p')
break; break;
switch (NameR[8]) { return Intrinsic::ppc_altivec_vminfp; // "pc.altivec.vmin
fp"
case 's': // 3 strings to match.
switch (NameR[16]) {
default: break; default: break;
case 'c': // 1 string to match. case 'b': // 1 string to match.
if (NameR.substr(9, 6) != "lflush") return Intrinsic::ppc_altivec_vminsb; // "pc.altivec.vmin
break; sb"
return Intrinsic::x86_sse2_clflush; // "86.sse2.clflush case 'h': // 1 string to match.
" return Intrinsic::ppc_altivec_vminsh; // "pc.altivec.vmin
case 'p': // 20 strings to match. sh"
switch (NameR[9]) { case 'w': // 1 string to match.
default: break; return Intrinsic::ppc_altivec_vminsw; // "pc.altivec.vmin
case 'a': // 2 strings to match. sw"
if (NameR.substr(10, 4) != "dds.")
break;
switch (NameR[14]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::x86_sse2_padds_b; // "86.sse2
.padds.b"
case 'w': // 1 string to match.
return Intrinsic::x86_sse2_padds_w; // "86.sse2
.padds.w"
}
break;
case 'm': // 5 strings to match.
switch (NameR[10]) {
default: break;
case 'a': // 2 strings to match.
if (NameR[11] != 'x')
break;
switch (NameR[12]) {
default: break;
case 's': // 1 string to match.
if (NameR.substr(13, 2) != ".w")
break;
return Intrinsic::x86_sse2_pmaxs_w; // "86.sse2
.pmaxs.w"
case 'u': // 1 string to match.
if (NameR.substr(13, 2) != ".b")
break;
return Intrinsic::x86_sse2_pmaxu_b; // "86.sse2
.pmaxu.b"
}
break;
case 'i': // 2 strings to match.
if (NameR[11] != 'n')
break;
switch (NameR[12]) {
default: break;
case 's': // 1 string to match.
if (NameR.substr(13, 2) != ".w")
break;
return Intrinsic::x86_sse2_pmins_w; // "86.sse2
.pmins.w"
case 'u': // 1 string to match.
if (NameR.substr(13, 2) != ".b")
break;
return Intrinsic::x86_sse2_pminu_b; // "86.sse2
.pminu.b"
}
break;
case 'u': // 1 string to match.
if (NameR.substr(11, 4) != "lh.w")
break;
return Intrinsic::x86_sse2_pmulh_w; // "86.sse2
.pmulh.w"
}
break;
case 's': // 13 strings to match.
switch (NameR[10]) {
default: break;
case 'a': // 1 string to match.
if (NameR.substr(11, 4) != "d.bw")
break;
return Intrinsic::x86_sse2_psad_bw; // "86.sse2
.psad.bw"
case 'l': // 4 strings to match.
if (NameR[11] != 'l')
break;
switch (NameR[12]) {
default: break;
case '.': // 1 string to match.
if (NameR.substr(13, 2) != "dq")
break;
return Intrinsic::x86_sse2_psll_dq; // "86.sse2
.psll.dq"
case 'i': // 3 strings to match.
if (NameR[13] != '.')
break;
switch (NameR[14]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::x86_sse2_pslli_d; // "86.sse2
.pslli.d"
case 'q': // 1 string to match.
return Intrinsic::x86_sse2_pslli_q; // "86.sse2
.pslli.q"
case 'w': // 1 string to match.
return Intrinsic::x86_sse2_pslli_w; // "86.sse2
.pslli.w"
}
break;
}
break;
case 'r': // 6 strings to match.
switch (NameR[11]) {
default: break;
case 'a': // 2 strings to match.
if (NameR.substr(12, 2) != "i.")
break;
switch (NameR[14]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::x86_sse2_psrai_d; // "86.sse2
.psrai.d"
case 'w': // 1 string to match.
return Intrinsic::x86_sse2_psrai_w; // "86.sse2
.psrai.w"
}
break;
case 'l': // 4 strings to match.
switch (NameR[12]) {
default: break;
case '.': // 1 string to match.
if (NameR.substr(13, 2) != "dq")
break;
return Intrinsic::x86_sse2_psrl_dq; // "86.sse2
.psrl.dq"
case 'i': // 3 strings to match.
if (NameR[13] != '.')
break;
switch (NameR[14]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::x86_sse2_psrli_d; // "86.sse2
.psrli.d"
case 'q': // 1 string to match.
return Intrinsic::x86_sse2_psrli_q; // "86.sse2
.psrli.q"
case 'w': // 1 string to match.
return Intrinsic::x86_sse2_psrli_w; // "86.sse2
.psrli.w"
}
break;
}
break;
}
break;
case 'u': // 2 strings to match.
if (NameR.substr(11, 3) != "bs.")
break;
switch (NameR[14]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::x86_sse2_psubs_b; // "86.sse2
.psubs.b"
case 'w': // 1 string to match.
return Intrinsic::x86_sse2_psubs_w; // "86.sse2
.psubs.w"
}
break;
}
break;
}
break;
case 's': // 2 strings to match.
if (NameR.substr(9, 4) != "qrt.")
break;
switch (NameR[13]) {
default: break;
case 'p': // 1 string to match.
if (NameR[14] != 'd')
break;
return Intrinsic::x86_sse2_sqrt_pd; // "86.sse2.sqrt.pd
"
case 's': // 1 string to match.
if (NameR[14] != 'd')
break;
return Intrinsic::x86_sse2_sqrt_sd; // "86.sse2.sqrt.sd
"
}
break;
} }
break; break;
case '3': // 5 strings to match. case 'u': // 3 strings to match.
if (NameR[7] != '.') switch (NameR[16]) {
break;
switch (NameR[8]) {
default: break; default: break;
case 'h': // 4 strings to match. case 'b': // 1 string to match.
switch (NameR[9]) { return Intrinsic::ppc_altivec_vminub; // "pc.altivec.vmin
default: break; ub"
case 'a': // 2 strings to match. case 'h': // 1 string to match.
if (NameR.substr(10, 4) != "dd.p") return Intrinsic::ppc_altivec_vminuh; // "pc.altivec.vmin
break; uh"
switch (NameR[14]) { case 'w': // 1 string to match.
default: break; return Intrinsic::ppc_altivec_vminuw; // "pc.altivec.vmin
case 'd': // 1 string to match. uw"
return Intrinsic::x86_sse3_hadd_pd; // "86.sse3
.hadd.pd"
case 's': // 1 string to match.
return Intrinsic::x86_sse3_hadd_ps; // "86.sse3
.hadd.ps"
}
break;
case 's': // 2 strings to match.
if (NameR.substr(10, 4) != "ub.p")
break;
switch (NameR[14]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::x86_sse3_hsub_pd; // "86.sse3
.hsub.pd"
case 's': // 1 string to match.
return Intrinsic::x86_sse3_hsub_ps; // "86.sse3
.hsub.ps"
}
break;
}
break;
case 'm': // 1 string to match.
if (NameR.substr(9, 6) != "onitor")
break;
return Intrinsic::x86_sse3_monitor; // "86.sse3.monitor
"
} }
break; break;
case '4': // 14 strings to match.
if (NameR.substr(7, 3) != "1.p")
break;
switch (NameR[10]) {
default: break;
case 'e': // 3 strings to match.
if (NameR.substr(11, 3) != "xtr")
break;
switch (NameR[14]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::x86_sse41_pextrb; // "86.sse41.pextrb
"
case 'd': // 1 string to match.
return Intrinsic::x86_sse41_pextrd; // "86.sse41.pextrd
"
case 'q': // 1 string to match.
return Intrinsic::x86_sse41_pextrq; // "86.sse41.pextrq
"
}
break;
case 'm': // 9 strings to match.
switch (NameR[11]) {
default: break;
case 'a': // 4 strings to match.
if (NameR[12] != 'x')
break;
switch (NameR[13]) {
default: break;
case 's': // 2 strings to match.
switch (NameR[14]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::x86_sse41_pmaxsb; // "86.sse4
1.pmaxsb"
case 'd': // 1 string to match.
return Intrinsic::x86_sse41_pmaxsd; // "86.sse4
1.pmaxsd"
}
break;
case 'u': // 2 strings to match.
switch (NameR[14]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::x86_sse41_pmaxud; // "86.sse4
1.pmaxud"
case 'w': // 1 string to match.
return Intrinsic::x86_sse41_pmaxuw; // "86.sse4
1.pmaxuw"
}
break;
}
break;
case 'i': // 4 strings to match.
if (NameR[12] != 'n')
break;
switch (NameR[13]) {
default: break;
case 's': // 2 strings to match.
switch (NameR[14]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::x86_sse41_pminsb; // "86.sse4
1.pminsb"
case 'd': // 1 string to match.
return Intrinsic::x86_sse41_pminsd; // "86.sse4
1.pminsd"
}
break;
case 'u': // 2 strings to match.
switch (NameR[14]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::x86_sse41_pminud; // "86.sse4
1.pminud"
case 'w': // 1 string to match.
return Intrinsic::x86_sse41_pminuw; // "86.sse4
1.pminuw"
}
break;
}
break;
case 'u': // 1 string to match.
if (NameR.substr(12, 3) != "ldq")
break;
return Intrinsic::x86_sse41_pmuldq; // "86.sse41.pmuldq
"
}
break;
case 't': // 2 strings to match.
if (NameR.substr(11, 3) != "est")
break;
switch (NameR[14]) {
default: break;
case 'c': // 1 string to match.
return Intrinsic::x86_sse41_ptestc; // "86.sse41.ptestc
"
case 'z': // 1 string to match.
return Intrinsic::x86_sse41_ptestz; // "86.sse41.ptestz
"
}
break;
}
break;
}
break;
case 's': // 3 strings to match.
if (NameR.substr(6, 8) != "e3.pabs.")
break;
switch (NameR[14]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::x86_ssse3_pabs_b; // "86.ssse3.pabs.b
"
case 'd': // 1 string to match.
return Intrinsic::x86_ssse3_pabs_d; // "86.ssse3.pabs.d
"
case 'w': // 1 string to match.
return Intrinsic::x86_ssse3_pabs_w; // "86.ssse3.pabs.w
"
} }
break; break;
} }
break; break;
case 'x': // 40 strings to match. }
if (NameR.substr(4, 4) != "op.v") break;
}
break;
case 18: // 38 strings to match.
if (memcmp(NameR.data()+0, "pc.altivec.v", 12))
break;
switch (NameR[12]) {
default: break;
case 'a': // 7 strings to match.
if (memcmp(NameR.data()+13, "dd", 2))
break;
switch (NameR[15]) {
default: break;
case 'c': // 1 string to match.
if (memcmp(NameR.data()+16, "uw", 2))
break; break;
switch (NameR[8]) { return Intrinsic::ppc_altivec_vaddcuw; // "pc.altivec.vadd
cuw"
case 's': // 3 strings to match.
switch (NameR[16]) {
default: break; default: break;
case 'f': // 4 strings to match. case 'b': // 1 string to match.
if (NameR.substr(9, 4) != "rcz.") if (NameR[17] != 's')
break; break;
switch (NameR[13]) { return Intrinsic::ppc_altivec_vaddsbs; // "pc.altivec.vadd
sbs"
case 'h': // 1 string to match.
if (NameR[17] != 's')
break;
return Intrinsic::ppc_altivec_vaddshs; // "pc.altivec.vadd
shs"
case 'w': // 1 string to match.
if (NameR[17] != 's')
break;
return Intrinsic::ppc_altivec_vaddsws; // "pc.altivec.vadd
sws"
}
break;
case 'u': // 3 strings to match.
switch (NameR[16]) {
default: break;
case 'b': // 1 string to match.
if (NameR[17] != 's')
break;
return Intrinsic::ppc_altivec_vaddubs; // "pc.altivec.vadd
ubs"
case 'h': // 1 string to match.
if (NameR[17] != 's')
break;
return Intrinsic::ppc_altivec_vadduhs; // "pc.altivec.vadd
uhs"
case 'w': // 1 string to match.
if (NameR[17] != 's')
break;
return Intrinsic::ppc_altivec_vadduws; // "pc.altivec.vadd
uws"
}
break;
}
break;
case 'c': // 1 string to match.
if (memcmp(NameR.data()+13, "mpbfp", 5))
break;
return Intrinsic::ppc_altivec_vcmpbfp; // "pc.altivec.vcmpbfp"
case 'l': // 1 string to match.
if (memcmp(NameR.data()+13, "ogefp", 5))
break;
return Intrinsic::ppc_altivec_vlogefp; // "pc.altivec.vlogefp"
case 'm': // 9 strings to match.
switch (NameR[13]) {
default: break;
case 'a': // 1 string to match.
if (memcmp(NameR.data()+14, "ddfp", 4))
break;
return Intrinsic::ppc_altivec_vmaddfp; // "pc.altivec.vmad
dfp"
case 'u': // 8 strings to match.
if (NameR[14] != 'l')
break;
switch (NameR[15]) {
default: break;
case 'e': // 4 strings to match.
switch (NameR[16]) {
default: break; default: break;
case 'p': // 2 strings to match. case 's': // 2 strings to match.
switch (NameR[14]) { switch (NameR[17]) {
default: break; default: break;
case 'd': // 1 string to match. case 'b': // 1 string to match.
return Intrinsic::x86_xop_vfrcz_pd; // "86.xop.vfrcz.pd return Intrinsic::ppc_altivec_vmulesb; // "pc.altivec.vmul
" esb"
case 's': // 1 string to match. case 'h': // 1 string to match.
return Intrinsic::x86_xop_vfrcz_ps; // "86.xop.vfrcz.ps return Intrinsic::ppc_altivec_vmulesh; // "pc.altivec.vmul
" esh"
} }
break; break;
case 's': // 2 strings to match. case 'u': // 2 strings to match.
switch (NameR[14]) { switch (NameR[17]) {
default: break; default: break;
case 'd': // 1 string to match. case 'b': // 1 string to match.
return Intrinsic::x86_xop_vfrcz_sd; // "86.xop.vfrcz.sd return Intrinsic::ppc_altivec_vmuleub; // "pc.altivec.vmul
" eub"
case 's': // 1 string to match. case 'h': // 1 string to match.
return Intrinsic::x86_xop_vfrcz_ss; // "86.xop.vfrcz.ss return Intrinsic::ppc_altivec_vmuleuh; // "pc.altivec.vmul
" euh"
} }
break; break;
} }
break; break;
case 'p': // 36 strings to match. case 'o': // 4 strings to match.
switch (NameR[9]) { switch (NameR[16]) {
default: break; default: break;
case 'c': // 24 strings to match. case 's': // 2 strings to match.
if (NameR.substr(10, 2) != "om") switch (NameR[17]) {
break;
switch (NameR[12]) {
default: break; default: break;
case 'e': // 4 strings to match. case 'b': // 1 string to match.
if (NameR[13] != 'q') return Intrinsic::ppc_altivec_vmulosb; // "pc.altivec.vmul
break; osb"
switch (NameR[14]) { case 'h': // 1 string to match.
default: break; return Intrinsic::ppc_altivec_vmulosh; // "pc.altivec.vmul
case 'b': // 1 string to match. osh"
return Intrinsic::x86_xop_vpcomeqb; // "86.xop.vpcomeqb
"
case 'd': // 1 string to match.
return Intrinsic::x86_xop_vpcomeqd; // "86.xop.vpcomeqd
"
case 'q': // 1 string to match.
return Intrinsic::x86_xop_vpcomeqq; // "86.xop.vpcomeqq
"
case 'w': // 1 string to match.
return Intrinsic::x86_xop_vpcomeqw; // "86.xop.vpcomeqw
"
}
break;
case 'g': // 8 strings to match.
switch (NameR[13]) {
default: break;
case 'e': // 4 strings to match.
switch (NameR[14]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::x86_xop_vpcomgeb; // "86.xop.
vpcomgeb"
case 'd': // 1 string to match.
return Intrinsic::x86_xop_vpcomged; // "86.xop.
vpcomged"
case 'q': // 1 string to match.
return Intrinsic::x86_xop_vpcomgeq; // "86.xop.
vpcomgeq"
case 'w': // 1 string to match.
return Intrinsic::x86_xop_vpcomgew; // "86.xop.
vpcomgew"
}
break;
case 't': // 4 strings to match.
switch (NameR[14]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::x86_xop_vpcomgtb; // "86.xop.
vpcomgtb"
case 'd': // 1 string to match.
return Intrinsic::x86_xop_vpcomgtd; // "86.xop.
vpcomgtd"
case 'q': // 1 string to match.
return Intrinsic::x86_xop_vpcomgtq; // "86.xop.
vpcomgtq"
case 'w': // 1 string to match.
return Intrinsic::x86_xop_vpcomgtw; // "86.xop.
vpcomgtw"
}
break;
}
break;
case 'l': // 8 strings to match.
switch (NameR[13]) {
default: break;
case 'e': // 4 strings to match.
switch (NameR[14]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::x86_xop_vpcomleb; // "86.xop.
vpcomleb"
case 'd': // 1 string to match.
return Intrinsic::x86_xop_vpcomled; // "86.xop.
vpcomled"
case 'q': // 1 string to match.
return Intrinsic::x86_xop_vpcomleq; // "86.xop.
vpcomleq"
case 'w': // 1 string to match.
return Intrinsic::x86_xop_vpcomlew; // "86.xop.
vpcomlew"
}
break;
case 't': // 4 strings to match.
switch (NameR[14]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::x86_xop_vpcomltb; // "86.xop.
vpcomltb"
case 'd': // 1 string to match.
return Intrinsic::x86_xop_vpcomltd; // "86.xop.
vpcomltd"
case 'q': // 1 string to match.
return Intrinsic::x86_xop_vpcomltq; // "86.xop.
vpcomltq"
case 'w': // 1 string to match.
return Intrinsic::x86_xop_vpcomltw; // "86.xop.
vpcomltw"
}
break;
}
break;
case 'n': // 4 strings to match.
if (NameR[13] != 'e')
break;
switch (NameR[14]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::x86_xop_vpcomneb; // "86.xop.vpcomneb
"
case 'd': // 1 string to match.
return Intrinsic::x86_xop_vpcomned; // "86.xop.vpcomned
"
case 'q': // 1 string to match.
return Intrinsic::x86_xop_vpcomneq; // "86.xop.vpcomneq
"
case 'w': // 1 string to match.
return Intrinsic::x86_xop_vpcomnew; // "86.xop.vpcomnew
"
}
break;
} }
break; break;
case 'h': // 9 strings to match. case 'u': // 2 strings to match.
switch (NameR[10]) { switch (NameR[17]) {
default: break; default: break;
case 'a': // 6 strings to match. case 'b': // 1 string to match.
if (NameR.substr(11, 2) != "dd") return Intrinsic::ppc_altivec_vmuloub; // "pc.altivec.vmul
break; oub"
switch (NameR[13]) { case 'h': // 1 string to match.
default: break; return Intrinsic::ppc_altivec_vmulouh; // "pc.altivec.vmul
case 'b': // 3 strings to match. ouh"
switch (NameR[14]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::x86_xop_vphaddbd; // "86.xop.
vphaddbd"
case 'q': // 1 string to match.
return Intrinsic::x86_xop_vphaddbq; // "86.xop.
vphaddbq"
case 'w': // 1 string to match.
return Intrinsic::x86_xop_vphaddbw; // "86.xop.
vphaddbw"
}
break;
case 'd': // 1 string to match.
if (NameR[14] != 'q')
break;
return Intrinsic::x86_xop_vphadddq; // "86.xop.vphadddq
"
case 'w': // 2 strings to match.
switch (NameR[14]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::x86_xop_vphaddwd; // "86.xop.
vphaddwd"
case 'q': // 1 string to match.
return Intrinsic::x86_xop_vphaddwq; // "86.xop.
vphaddwq"
}
break;
}
break;
case 's': // 3 strings to match.
if (NameR.substr(11, 2) != "ub")
break;
switch (NameR[13]) {
default: break;
case 'b': // 1 string to match.
if (NameR[14] != 'w')
break;
return Intrinsic::x86_xop_vphsubbw; // "86.xop.vphsubbw
"
case 'd': // 1 string to match.
if (NameR[14] != 'q')
break;
return Intrinsic::x86_xop_vphsubdq; // "86.xop.vphsubdq
"
case 'w': // 1 string to match.
if (NameR[14] != 'd')
break;
return Intrinsic::x86_xop_vphsubwd; // "86.xop.vphsubwd
"
}
break;
}
break;
case 'm': // 3 strings to match.
if (NameR.substr(10, 3) != "acs")
break;
switch (NameR[13]) {
default: break;
case 'd': // 1 string to match.
if (NameR[14] != 'd')
break;
return Intrinsic::x86_xop_vpmacsdd; // "86.xop.vpmacsdd
"
case 'w': // 2 strings to match.
switch (NameR[14]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::x86_xop_vpmacswd; // "86.xop.vpmacswd
"
case 'w': // 1 string to match.
return Intrinsic::x86_xop_vpmacsww; // "86.xop.vpmacsww
"
}
break;
} }
break; break;
} }
break; break;
} }
break; break;
} }
break; break;
case 'c': // 1 string to match. case 'p': // 6 strings to match.
if (NameR.substr(1, 14) != "ore.checkevent") if (NameR[13] != 'k')
break;
return Intrinsic::xcore_checkevent; // "core.checkevent"
}
break;
case 16: // 127 strings to match.
if (NameR.substr(0, 3) != "86.")
break;
switch (NameR[3]) {
default: break;
case '3': // 8 strings to match.
if (NameR.substr(4, 4) != "dnow")
break; break;
switch (NameR[8]) { switch (NameR[14]) {
default: break; default: break;
case '.': // 6 strings to match. case 's': // 4 strings to match.
if (NameR[9] != 'p') switch (NameR[15]) {
break;
switch (NameR[10]) {
default: break; default: break;
case 'a': // 1 string to match. case 'h': // 2 strings to match.
if (NameR.substr(11, 5) != "vgusb") switch (NameR[16]) {
break;
return Intrinsic::x86_3dnow_pavgusb; // "86.3dnow.pavgus
b"
case 'f': // 4 strings to match.
switch (NameR[11]) {
default: break; default: break;
case 'c': // 3 strings to match. case 's': // 1 string to match.
if (NameR.substr(12, 2) != "mp") if (NameR[17] != 's')
break; break;
switch (NameR[14]) { return Intrinsic::ppc_altivec_vpkshss; // "pc.altivec.vpks
default: break; hss"
case 'e': // 1 string to match. case 'u': // 1 string to match.
if (NameR[15] != 'q') if (NameR[17] != 's')
break;
return Intrinsic::x86_3dnow_pfcmpeq; // "86.3dnow.pfcmpe
q"
case 'g': // 2 strings to match.
switch (NameR[15]) {
default: break;
case 'e': // 1 string to match.
return Intrinsic::x86_3dnow_pfcmpge; // "86.3dnow.pfcmpg
e"
case 't': // 1 string to match.
return Intrinsic::x86_3dnow_pfcmpgt; // "86.3dnow.pfcmpg
t"
}
break; break;
} return Intrinsic::ppc_altivec_vpkshus; // "pc.altivec.vpks
break; hus"
case 'r': // 1 string to match. }
if (NameR.substr(12, 4) != "sqrt") break;
case 'w': // 2 strings to match.
switch (NameR[16]) {
default: break;
case 's': // 1 string to match.
if (NameR[17] != 's')
break; break;
return Intrinsic::x86_3dnow_pfrsqrt; // "86.3dnow.pfrsqr return Intrinsic::ppc_altivec_vpkswss; // "pc.altivec.vpks
t" wss"
case 'u': // 1 string to match.
if (NameR[17] != 's')
break;
return Intrinsic::ppc_altivec_vpkswus; // "pc.altivec.vpks
wus"
} }
break; break;
case 'm': // 1 string to match.
if (NameR.substr(11, 5) != "ulhrw")
break;
return Intrinsic::x86_3dnow_pmulhrw; // "86.3dnow.pmulhr
w"
} }
break; break;
case 'a': // 2 strings to match. case 'u': // 2 strings to match.
if (NameR.substr(9, 2) != ".p") switch (NameR[15]) {
break;
switch (NameR[11]) {
default: break; default: break;
case 'f': // 1 string to match. case 'h': // 1 string to match.
if (NameR.substr(12, 4) != "nacc") if (memcmp(NameR.data()+16, "us", 2))
break; break;
return Intrinsic::x86_3dnowa_pfnacc; // "86.3dnowa.pfnac return Intrinsic::ppc_altivec_vpkuhus; // "pc.altivec.vpku
c" hus"
case 's': // 1 string to match. case 'w': // 1 string to match.
if (NameR.substr(12, 4) != "wapd") if (memcmp(NameR.data()+16, "us", 2))
break; break;
return Intrinsic::x86_3dnowa_pswapd; // "86.3dnowa.pswap d" return Intrinsic::ppc_altivec_vpkuwus; // "pc.altivec.vpku wus"
} }
break; break;
} }
break; break;
case 'a': // 33 strings to match. case 's': // 8 strings to match.
if (NameR.substr(4, 2) != "vx") if (NameR[13] != 'u')
break; break;
switch (NameR[6]) { switch (NameR[14]) {
default: break; default: break;
case '.': // 5 strings to match. case 'b': // 7 strings to match.
switch (NameR[7]) { switch (NameR[15]) {
default: break; default: break;
case 'd': // 1 string to match. case 'c': // 1 string to match.
if (NameR.substr(8, 8) != "p.ps.256") if (memcmp(NameR.data()+16, "uw", 2))
break;
return Intrinsic::x86_avx_dp_ps_256; // "86.avx.dp.ps.25
6"
case 'v': // 4 strings to match.
if (NameR.substr(8, 4) != "test")
break; break;
switch (NameR[12]) { return Intrinsic::ppc_altivec_vsubcuw; // "pc.altivec.vsub
cuw"
case 's': // 3 strings to match.
switch (NameR[16]) {
default: break; default: break;
case 'c': // 2 strings to match. case 'b': // 1 string to match.
if (NameR.substr(13, 2) != ".p") if (NameR[17] != 's')
break; break;
switch (NameR[15]) { return Intrinsic::ppc_altivec_vsubsbs; // "pc.altivec.vsub
default: break; sbs"
case 'd': // 1 string to match. case 'h': // 1 string to match.
return Intrinsic::x86_avx_vtestc_pd; // "86.avx.vtestc.p if (NameR[17] != 's')
d"
case 's': // 1 string to match.
return Intrinsic::x86_avx_vtestc_ps; // "86.avx.vtestc.p
s"
}
break;
case 'z': // 2 strings to match.
if (NameR.substr(13, 2) != ".p")
break; break;
switch (NameR[15]) { return Intrinsic::ppc_altivec_vsubshs; // "pc.altivec.vsub
default: break; shs"
case 'd': // 1 string to match. case 'w': // 1 string to match.
return Intrinsic::x86_avx_vtestz_pd; // "86.avx.vtestz.p if (NameR[17] != 's')
d" break;
case 's': // 1 string to match. return Intrinsic::ppc_altivec_vsubsws; // "pc.altivec.vsub
return Intrinsic::x86_avx_vtestz_ps; // "86.avx.vtestz.p sws"
s" }
} break;
break; case 'u': // 3 strings to match.
switch (NameR[16]) {
default: break;
case 'b': // 1 string to match.
if (NameR[17] != 's')
break;
return Intrinsic::ppc_altivec_vsububs; // "pc.altivec.vsub
ubs"
case 'h': // 1 string to match.
if (NameR[17] != 's')
break;
return Intrinsic::ppc_altivec_vsubuhs; // "pc.altivec.vsub
uhs"
case 'w': // 1 string to match.
if (NameR[17] != 's')
break;
return Intrinsic::ppc_altivec_vsubuws; // "pc.altivec.vsub
uws"
} }
break; break;
} }
break; break;
case '2': // 28 strings to match. case 'm': // 1 string to match.
if (NameR[7] != '.') if (memcmp(NameR.data()+15, "sws", 3))
break; break;
switch (NameR[8]) { return Intrinsic::ppc_altivec_vsumsws; // "pc.altivec.vsum
sws"
}
break;
case 'u': // 6 strings to match.
if (memcmp(NameR.data()+13, "pk", 2))
break;
switch (NameR[15]) {
default: break;
case 'h': // 3 strings to match.
switch (NameR[16]) {
default: break; default: break;
case 'm': // 1 string to match. case 'p': // 1 string to match.
if (NameR.substr(9, 7) != "ovntdqa") if (NameR[17] != 'x')
break; break;
return Intrinsic::x86_avx2_movntdqa; // "86.avx2.movntdq return Intrinsic::ppc_altivec_vupkhpx; // "pc.altivec.vupk
a" hpx"
case 'p': // 27 strings to match. case 's': // 2 strings to match.
switch (NameR[9]) { switch (NameR[17]) {
default: break; default: break;
case 'a': // 6 strings to match. case 'b': // 1 string to match.
switch (NameR[10]) { return Intrinsic::ppc_altivec_vupkhsb; // "pc.altivec.vupk
default: break; hsb"
case 'c': // 4 strings to match. case 'h': // 1 string to match.
if (NameR[11] != 'k') return Intrinsic::ppc_altivec_vupkhsh; // "pc.altivec.vupk
break; hsh"
switch (NameR[12]) { }
default: break; break;
case 's': // 2 strings to match. }
if (NameR[13] != 's') break;
break; case 'l': // 3 strings to match.
switch (NameR[14]) { switch (NameR[16]) {
default: break; default: break;
case 'd': // 1 string to match. case 'p': // 1 string to match.
if (NameR[15] != 'w') if (NameR[17] != 'x')
break;
return Intrinsic::x86_avx2_packssdw; // "86.avx2
.packssdw"
case 'w': // 1 string to match.
if (NameR[15] != 'b')
break;
return Intrinsic::x86_avx2_packsswb; // "86.avx2
.packsswb"
}
break;
case 'u': // 2 strings to match.
if (NameR[13] != 's')
break;
switch (NameR[14]) {
default: break;
case 'd': // 1 string to match.
if (NameR[15] != 'w')
break;
return Intrinsic::x86_avx2_packusdw; // "86.avx2
.packusdw"
case 'w': // 1 string to match.
if (NameR[15] != 'b')
break;
return Intrinsic::x86_avx2_packuswb; // "86.avx2
.packuswb"
}
break;
}
break;
case 'd': // 2 strings to match.
if (NameR.substr(11, 4) != "dus.")
break;
switch (NameR[15]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::x86_avx2_paddus_b; // "86.avx2.paddus.
b"
case 'w': // 1 string to match.
return Intrinsic::x86_avx2_paddus_w; // "86.avx2.paddus.
w"
}
break;
}
break; break;
return Intrinsic::ppc_altivec_vupklpx; // "pc.altivec.vupk
lpx"
case 's': // 2 strings to match.
switch (NameR[17]) {
default: break;
case 'b': // 1 string to match. case 'b': // 1 string to match.
if (NameR.substr(10, 6) != "lendvb") return Intrinsic::ppc_altivec_vupklsb; // "pc.altivec.vupk
lsb"
case 'h': // 1 string to match.
return Intrinsic::ppc_altivec_vupklsh; // "pc.altivec.vupk
lsh"
}
break;
}
break;
}
break;
}
break;
case 19: // 29 strings to match.
switch (NameR[0]) {
default: break;
case 'p': // 24 strings to match.
if (memcmp(NameR.data()+1, "c.altivec.v", 11))
break;
switch (NameR[12]) {
default: break;
case 'c': // 12 strings to match.
if (memcmp(NameR.data()+13, "mp", 2))
break;
switch (NameR[15]) {
default: break;
case 'e': // 4 strings to match.
if (NameR[16] != 'q')
break;
switch (NameR[17]) {
default: break;
case 'f': // 1 string to match.
if (NameR[18] != 'p')
break; break;
return Intrinsic::x86_avx2_pblendvb; // "86.avx2.pblendv return Intrinsic::ppc_altivec_vcmpeqfp; // "pc.altivec.vcmp
b" eqfp"
case 'h': // 2 strings to match. case 'u': // 3 strings to match.
switch (NameR[10]) { switch (NameR[18]) {
default: break; default: break;
case 'a': // 1 string to match. case 'b': // 1 string to match.
if (NameR.substr(11, 5) != "dd.sw") return Intrinsic::ppc_altivec_vcmpequb; // "pc.alti
break; vec.vcmpequb"
return Intrinsic::x86_avx2_phadd_sw; // "86.avx2.phadd.s case 'h': // 1 string to match.
w" return Intrinsic::ppc_altivec_vcmpequh; // "pc.alti
case 's': // 1 string to match. vec.vcmpequh"
if (NameR.substr(11, 5) != "ub.sw") case 'w': // 1 string to match.
break; return Intrinsic::ppc_altivec_vcmpequw; // "pc.alti
return Intrinsic::x86_avx2_phsub_sw; // "86.avx2.phsub.s vec.vcmpequw"
w"
} }
break; break;
case 'm': // 16 strings to match. }
switch (NameR[10]) { break;
case 'g': // 8 strings to match.
switch (NameR[16]) {
default: break;
case 'e': // 1 string to match.
if (memcmp(NameR.data()+17, "fp", 2))
break;
return Intrinsic::ppc_altivec_vcmpgefp; // "pc.altivec.vcmp
gefp"
case 't': // 7 strings to match.
switch (NameR[17]) {
default: break; default: break;
case 'a': // 1 string to match. case 'f': // 1 string to match.
if (NameR.substr(11, 5) != "dd.wd") if (NameR[18] != 'p')
break;
return Intrinsic::x86_avx2_pmadd_wd; // "86.avx2.pmadd.w
d"
case 'o': // 13 strings to match.
if (NameR[11] != 'v')
break; break;
switch (NameR[12]) { return Intrinsic::ppc_altivec_vcmpgtfp; // "pc.alti
vec.vcmpgtfp"
case 's': // 3 strings to match.
switch (NameR[18]) {
default: break; default: break;
case 'm': // 1 string to match. case 'b': // 1 string to match.
if (NameR.substr(13, 3) != "skb") return Intrinsic::ppc_altivec_vcmpgtsb; // "pc.alti
break; vec.vcmpgtsb"
return Intrinsic::x86_avx2_pmovmskb; // "86.avx2.pmovmsk case 'h': // 1 string to match.
b" return Intrinsic::ppc_altivec_vcmpgtsh; // "pc.alti
case 's': // 6 strings to match. vec.vcmpgtsh"
if (NameR[13] != 'x') case 'w': // 1 string to match.
break; return Intrinsic::ppc_altivec_vcmpgtsw; // "pc.alti
switch (NameR[14]) { vec.vcmpgtsw"
default: break;
case 'b': // 3 strings to match.
switch (NameR[15]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::x86_avx2_pmovsxbd; // "86.avx2
.pmovsxbd"
case 'q': // 1 string to match.
return Intrinsic::x86_avx2_pmovsxbq; // "86.avx2
.pmovsxbq"
case 'w': // 1 string to match.
return Intrinsic::x86_avx2_pmovsxbw; // "86.avx2
.pmovsxbw"
}
break;
case 'd': // 1 string to match.
if (NameR[15] != 'q')
break;
return Intrinsic::x86_avx2_pmovsxdq; // "86.avx2
.pmovsxdq"
case 'w': // 2 strings to match.
switch (NameR[15]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::x86_avx2_pmovsxwd; // "86.avx2
.pmovsxwd"
case 'q': // 1 string to match.
return Intrinsic::x86_avx2_pmovsxwq; // "86.avx2
.pmovsxwq"
}
break;
}
break;
case 'z': // 6 strings to match.
if (NameR[13] != 'x')
break;
switch (NameR[14]) {
default: break;
case 'b': // 3 strings to match.
switch (NameR[15]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::x86_avx2_pmovzxbd; // "86.avx2
.pmovzxbd"
case 'q': // 1 string to match.
return Intrinsic::x86_avx2_pmovzxbq; // "86.avx2
.pmovzxbq"
case 'w': // 1 string to match.
return Intrinsic::x86_avx2_pmovzxbw; // "86.avx2
.pmovzxbw"
}
break;
case 'd': // 1 string to match.
if (NameR[15] != 'q')
break;
return Intrinsic::x86_avx2_pmovzxdq; // "86.avx2
.pmovzxdq"
case 'w': // 2 strings to match.
switch (NameR[15]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::x86_avx2_pmovzxwd; // "86.avx2
.pmovzxwd"
case 'q': // 1 string to match.
return Intrinsic::x86_avx2_pmovzxwq; // "86.avx2
.pmovzxwq"
}
break;
}
break;
} }
break; break;
case 'u': // 2 strings to match. case 'u': // 3 strings to match.
if (NameR[11] != 'l') switch (NameR[18]) {
break;
switch (NameR[12]) {
default: break; default: break;
case 'b': // 1 string to match.
return Intrinsic::ppc_altivec_vcmpgtub; // "pc.alti
vec.vcmpgtub"
case 'h': // 1 string to match. case 'h': // 1 string to match.
if (NameR.substr(13, 3) != "u.w") return Intrinsic::ppc_altivec_vcmpgtuh; // "pc.alti
break; vec.vcmpgtuh"
return Intrinsic::x86_avx2_pmulhu_w; // "86.avx2.pmulhu. case 'w': // 1 string to match.
w" return Intrinsic::ppc_altivec_vcmpgtuw; // "pc.alti
case 'u': // 1 string to match. vec.vcmpgtuw"
if (NameR.substr(13, 3) != ".dq")
break;
return Intrinsic::x86_avx2_pmulu_dq; // "86.avx2.pmulu.d
q"
} }
break; break;
} }
break; break;
case 's': // 2 strings to match.
if (NameR.substr(10, 5) != "ubus.")
break;
switch (NameR[15]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::x86_avx2_psubus_b; // "86.avx2.psubus.
b"
case 'w': // 1 string to match.
return Intrinsic::x86_avx2_psubus_w; // "86.avx2.psubus.
w"
}
break;
} }
break; break;
} }
break; break;
} case 'e': // 1 string to match.
break; if (memcmp(NameR.data()+13, "xptefp", 6))
case 'm': // 7 strings to match.
if (NameR.substr(4, 4) != "mx.p")
break;
switch (NameR[8]) {
default: break;
case 'a': // 1 string to match.
if (NameR.substr(9, 7) != "lignr.b")
break; break;
return Intrinsic::x86_mmx_palignr_b; // "86.mmx.palignr.b" return Intrinsic::ppc_altivec_vexptefp; // "pc.altivec.vexp
case 'u': // 6 strings to match. tefp"
if (NameR.substr(9, 4) != "npck") case 'm': // 6 strings to match.
if (memcmp(NameR.data()+13, "sum", 3))
break; break;
switch (NameR[13]) { switch (NameR[16]) {
default: break; default: break;
case 'h': // 3 strings to match. case 'm': // 1 string to match.
switch (NameR[14]) { if (memcmp(NameR.data()+17, "bm", 2))
break;
return Intrinsic::ppc_altivec_vmsummbm; // "pc.altivec.vmsu
mmbm"
case 's': // 2 strings to match.
if (NameR[17] != 'h')
break;
switch (NameR[18]) {
default: break; default: break;
case 'b': // 1 string to match. case 'm': // 1 string to match.
if (NameR[15] != 'w') return Intrinsic::ppc_altivec_vmsumshm; // "pc.altivec.vmsu
break; mshm"
return Intrinsic::x86_mmx_punpckhbw; // "86.mmx.punpckhb case 's': // 1 string to match.
w" return Intrinsic::ppc_altivec_vmsumshs; // "pc.altivec.vmsu
case 'd': // 1 string to match. mshs"
if (NameR[15] != 'q')
break;
return Intrinsic::x86_mmx_punpckhdq; // "86.mmx.punpckhd
q"
case 'w': // 1 string to match.
if (NameR[15] != 'd')
break;
return Intrinsic::x86_mmx_punpckhwd; // "86.mmx.punpckhw
d"
} }
break; break;
case 'l': // 3 strings to match. case 'u': // 3 strings to match.
switch (NameR[14]) { switch (NameR[17]) {
default: break; default: break;
case 'b': // 1 string to match. case 'b': // 1 string to match.
if (NameR[15] != 'w') if (NameR[18] != 'm')
break;
return Intrinsic::x86_mmx_punpcklbw; // "86.mmx.punpcklb
w"
case 'd': // 1 string to match.
if (NameR[15] != 'q')
break;
return Intrinsic::x86_mmx_punpckldq; // "86.mmx.punpckld
q"
case 'w': // 1 string to match.
if (NameR[15] != 'd')
break; break;
return Intrinsic::x86_mmx_punpcklwd; // "86.mmx.punpcklw return Intrinsic::ppc_altivec_vmsumubm; // "pc.altivec.vmsu
d" mubm"
} case 'h': // 2 strings to match.
break; switch (NameR[18]) {
default: break;
case 'm': // 1 string to match.
return Intrinsic::ppc_altivec_vmsumuhm; // "pc.alti
vec.vmsumuhm"
case 's': // 1 string to match.
return Intrinsic::ppc_altivec_vmsumuhs; // "pc.alti
vec.vmsumuhs"
}
break;
}
break;
} }
break; break;
} case 'n': // 1 string to match.
break; if (memcmp(NameR.data()+13, "msubfp", 6))
case 's': // 39 strings to match. break;
if (NameR[4] != 's') return Intrinsic::ppc_altivec_vnmsubfp; // "pc.altivec.vnms
break; ubfp"
switch (NameR[5]) { case 's': // 4 strings to match.
default: break; if (memcmp(NameR.data()+13, "um", 2))
case 'e': // 31 strings to match. break;
switch (NameR[6]) { switch (NameR[15]) {
default: break; default: break;
case '.': // 10 strings to match. case '2': // 1 string to match.
switch (NameR[7]) { if (memcmp(NameR.data()+16, "sws", 3))
break;
return Intrinsic::ppc_altivec_vsum2sws; // "pc.altivec.vsum
2sws"
case '4': // 3 strings to match.
switch (NameR[16]) {
default: break; default: break;
case 'c': // 8 strings to match. case 's': // 2 strings to match.
switch (NameR[8]) { switch (NameR[17]) {
default: break; default: break;
case 'o': // 5 strings to match. case 'b': // 1 string to match.
if (NameR.substr(9, 2) != "mi") if (NameR[18] != 's')
break;
switch (NameR[11]) {
default: break;
case 'e': // 1 string to match.
if (NameR.substr(12, 4) != "q.ss")
break;
return Intrinsic::x86_sse_comieq_ss; // "86.sse.comieq.s
s"
case 'g': // 2 strings to match.
switch (NameR[12]) {
default: break;
case 'e': // 1 string to match.
if (NameR.substr(13, 3) != ".ss")
break;
return Intrinsic::x86_sse_comige_ss; // "86.sse.
comige.ss"
case 't': // 1 string to match.
if (NameR.substr(13, 3) != ".ss")
break;
return Intrinsic::x86_sse_comigt_ss; // "86.sse.
comigt.ss"
}
break;
case 'l': // 2 strings to match.
switch (NameR[12]) {
default: break;
case 'e': // 1 string to match.
if (NameR.substr(13, 3) != ".ss")
break;
return Intrinsic::x86_sse_comile_ss; // "86.sse.
comile.ss"
case 't': // 1 string to match.
if (NameR.substr(13, 3) != ".ss")
break;
return Intrinsic::x86_sse_comilt_ss; // "86.sse.
comilt.ss"
}
break;
}
break;
case 'v': // 3 strings to match.
if (NameR.substr(9, 2) != "tt")
break; break;
switch (NameR[11]) { return Intrinsic::ppc_altivec_vsum4sbs; // "pc.alti
default: break; vec.vsum4sbs"
case 'p': // 2 strings to match. case 'h': // 1 string to match.
switch (NameR[12]) { if (NameR[18] != 's')
default: break;
case 'd': // 1 string to match.
if (NameR.substr(13, 3) != "2pi")
break;
return Intrinsic::x86_sse_cvttpd2pi; // "86.sse.
cvttpd2pi"
case 's': // 1 string to match.
if (NameR.substr(13, 3) != "2pi")
break;
return Intrinsic::x86_sse_cvttps2pi; // "86.sse.
cvttps2pi"
}
break; break;
case 's': // 1 string to match. return Intrinsic::ppc_altivec_vsum4shs; // "pc.alti
if (NameR.substr(12, 4) != "s2si") vec.vsum4shs"
break;
return Intrinsic::x86_sse_cvttss2si; // "86.sse.cvttss2s
i"
}
break;
} }
break; break;
case 'm': // 1 string to match. case 'u': // 1 string to match.
if (NameR.substr(8, 8) != "ovmsk.ps") if (memcmp(NameR.data()+17, "bs", 2))
break; break;
return Intrinsic::x86_sse_movmsk_ps; // "86.sse.movmsk.p return Intrinsic::ppc_altivec_vsum4ubs; // "pc.altivec.vsum
s" 4ubs"
case 's': // 1 string to match. }
if (NameR.substr(8, 8) != "toreu.ps") break;
}
break;
}
break;
case 't': // 5 strings to match.
if (memcmp(NameR.data()+1, "x.read.lanemask.", 16))
break;
switch (NameR[17]) {
default: break;
case 'e': // 1 string to match.
if (NameR[18] != 'q')
break;
return Intrinsic::ptx_read_lanemask_eq; // "tx.read.lanemas
k.eq"
case 'g': // 2 strings to match.
switch (NameR[18]) {
default: break;
case 'e': // 1 string to match.
return Intrinsic::ptx_read_lanemask_ge; // "tx.read.lanemas
k.ge"
case 't': // 1 string to match.
return Intrinsic::ptx_read_lanemask_gt; // "tx.read.lanemas
k.gt"
}
break;
case 'l': // 2 strings to match.
switch (NameR[18]) {
default: break;
case 'e': // 1 string to match.
return Intrinsic::ptx_read_lanemask_le; // "tx.read.lanemas
k.le"
case 't': // 1 string to match.
return Intrinsic::ptx_read_lanemask_lt; // "tx.read.lanemas
k.lt"
}
break;
}
break;
}
break;
case 20: // 4 strings to match.
if (memcmp(NameR.data()+0, "pc.altivec.v", 12))
break;
switch (NameR[12]) {
default: break;
case 'c': // 1 string to match.
if (memcmp(NameR.data()+13, "mpbfp.p", 7))
break;
return Intrinsic::ppc_altivec_vcmpbfp_p; // "pc.altivec.vcmp
bfp.p"
case 'm': // 2 strings to match.
switch (NameR[13]) {
default: break;
case 'h': // 1 string to match.
if (memcmp(NameR.data()+14, "addshs", 6))
break;
return Intrinsic::ppc_altivec_vmhaddshs; // "pc.altivec.vmha
ddshs"
case 'l': // 1 string to match.
if (memcmp(NameR.data()+14, "adduhm", 6))
break;
return Intrinsic::ppc_altivec_vmladduhm; // "pc.altivec.vmla
dduhm"
}
break;
case 'r': // 1 string to match.
if (memcmp(NameR.data()+13, "sqrtefp", 7))
break;
return Intrinsic::ppc_altivec_vrsqrtefp; // "pc.altivec.vrsq
rtefp"
}
break;
case 21: // 13 strings to match.
if (memcmp(NameR.data()+0, "pc.altivec.v", 12))
break;
switch (NameR[12]) {
default: break;
case 'c': // 12 strings to match.
if (memcmp(NameR.data()+13, "mp", 2))
break;
switch (NameR[15]) {
default: break;
case 'e': // 4 strings to match.
if (NameR[16] != 'q')
break;
switch (NameR[17]) {
default: break;
case 'f': // 1 string to match.
if (memcmp(NameR.data()+18, "p.p", 3))
break;
return Intrinsic::ppc_altivec_vcmpeqfp_p; // "pc.altivec.vcmp
eqfp.p"
case 'u': // 3 strings to match.
switch (NameR[18]) {
default: break;
case 'b': // 1 string to match.
if (memcmp(NameR.data()+19, ".p", 2))
break; break;
return Intrinsic::x86_sse_storeu_ps; // "86.sse.storeu.p return Intrinsic::ppc_altivec_vcmpequb_p; // "pc.alti
s" vec.vcmpequb.p"
case 'h': // 1 string to match.
if (memcmp(NameR.data()+19, ".p", 2))
break;
return Intrinsic::ppc_altivec_vcmpequh_p; // "pc.alti
vec.vcmpequh.p"
case 'w': // 1 string to match.
if (memcmp(NameR.data()+19, ".p", 2))
break;
return Intrinsic::ppc_altivec_vcmpequw_p; // "pc.alti
vec.vcmpequw.p"
} }
break; break;
case '2': // 17 strings to match. }
if (NameR[7] != '.') break;
case 'g': // 8 strings to match.
switch (NameR[16]) {
default: break;
case 'e': // 1 string to match.
if (memcmp(NameR.data()+17, "fp.p", 4))
break; break;
switch (NameR[8]) { return Intrinsic::ppc_altivec_vcmpgefp_p; // "pc.altivec.vcmp
gefp.p"
case 't': // 7 strings to match.
switch (NameR[17]) {
default: break; default: break;
case 'c': // 10 strings to match. case 'f': // 1 string to match.
if (NameR.substr(9, 2) != "vt") if (memcmp(NameR.data()+18, "p.p", 3))
break; break;
switch (NameR[11]) { return Intrinsic::ppc_altivec_vcmpgtfp_p; // "pc.alti
vec.vcmpgtfp.p"
case 's': // 3 strings to match.
switch (NameR[18]) {
default: break; default: break;
case 'd': // 2 strings to match. case 'b': // 1 string to match.
if (NameR.substr(12, 3) != "q2p") if (memcmp(NameR.data()+19, ".p", 2))
break; break;
switch (NameR[15]) { return Intrinsic::ppc_altivec_vcmpgtsb_p; // "pc.alti
default: break; vec.vcmpgtsb.p"
case 'd': // 1 string to match. case 'h': // 1 string to match.
return Intrinsic::x86_sse2_cvtdq2pd; // "86.sse2.cvtdq2p if (memcmp(NameR.data()+19, ".p", 2))
d"
case 's': // 1 string to match.
return Intrinsic::x86_sse2_cvtdq2ps; // "86.sse2.cvtdq2p
s"
}
break;
case 'p': // 4 strings to match.
switch (NameR[12]) {
default: break;
case 'd': // 2 strings to match.
if (NameR[13] != '2')
break;
switch (NameR[14]) {
default: break;
case 'd': // 1 string to match.
if (NameR[15] != 'q')
break;
return Intrinsic::x86_sse2_cvtpd2dq; // "86.sse2
.cvtpd2dq"
case 'p': // 1 string to match.
if (NameR[15] != 's')
break;
return Intrinsic::x86_sse2_cvtpd2ps; // "86.sse2
.cvtpd2ps"
}
break; break;
case 's': // 2 strings to match. return Intrinsic::ppc_altivec_vcmpgtsh_p; // "pc.alti
if (NameR[13] != '2') vec.vcmpgtsh.p"
break; case 'w': // 1 string to match.
switch (NameR[14]) { if (memcmp(NameR.data()+19, ".p", 2))
default: break;
case 'd': // 1 string to match.
if (NameR[15] != 'q')
break;
return Intrinsic::x86_sse2_cvtps2dq; // "86.sse2
.cvtps2dq"
case 'p': // 1 string to match.
if (NameR[15] != 'd')
break;
return Intrinsic::x86_sse2_cvtps2pd; // "86.sse2
.cvtps2pd"
}
break; break;
} return Intrinsic::ppc_altivec_vcmpgtsw_p; // "pc.alti
break; vec.vcmpgtsw.p"
case 's': // 4 strings to match.
switch (NameR[12]) {
default: break;
case 'd': // 2 strings to match.
if (NameR.substr(13, 2) != "2s")
break;
switch (NameR[15]) {
default: break;
case 'i': // 1 string to match.
return Intrinsic::x86_sse2_cvtsd2si; // "86.sse2
.cvtsd2si"
case 's': // 1 string to match.
return Intrinsic::x86_sse2_cvtsd2ss; // "86.sse2
.cvtsd2ss"
}
break;
case 'i': // 1 string to match.
if (NameR.substr(13, 3) != "2sd")
break;
return Intrinsic::x86_sse2_cvtsi2sd; // "86.sse2.cvtsi2s
d"
case 's': // 1 string to match.
if (NameR.substr(13, 3) != "2sd")
break;
return Intrinsic::x86_sse2_cvtss2sd; // "86.sse2.cvtss2s
d"
}
break;
} }
break; break;
case 'p': // 7 strings to match. case 'u': // 3 strings to match.
switch (NameR[9]) { switch (NameR[18]) {
default: break; default: break;
case 'a': // 2 strings to match. case 'b': // 1 string to match.
if (NameR.substr(10, 5) != "ddus.") if (memcmp(NameR.data()+19, ".p", 2))
break; break;
switch (NameR[15]) { return Intrinsic::ppc_altivec_vcmpgtub_p; // "pc.alti
default: break; vec.vcmpgtub.p"
case 'b': // 1 string to match. case 'h': // 1 string to match.
return Intrinsic::x86_sse2_paddus_b; // "86.sse2.paddus. if (memcmp(NameR.data()+19, ".p", 2))
b"
case 'w': // 1 string to match.
return Intrinsic::x86_sse2_paddus_w; // "86.sse2.paddus.
w"
}
break;
case 'm': // 3 strings to match.
switch (NameR[10]) {
default: break;
case 'a': // 1 string to match.
if (NameR.substr(11, 5) != "dd.wd")
break;
return Intrinsic::x86_sse2_pmadd_wd; // "86.sse2.pmadd.w
d"
case 'u': // 2 strings to match.
if (NameR[11] != 'l')
break;
switch (NameR[12]) {
default: break;
case 'h': // 1 string to match.
if (NameR.substr(13, 3) != "u.w")
break;
return Intrinsic::x86_sse2_pmulhu_w; // "86.sse2
.pmulhu.w"
case 'u': // 1 string to match.
if (NameR.substr(13, 3) != ".dq")
break;
return Intrinsic::x86_sse2_pmulu_dq; // "86.sse2
.pmulu.dq"
}
break; break;
} return Intrinsic::ppc_altivec_vcmpgtuh_p; // "pc.alti
break; vec.vcmpgtuh.p"
case 's': // 2 strings to match. case 'w': // 1 string to match.
if (NameR.substr(10, 5) != "ubus.") if (memcmp(NameR.data()+19, ".p", 2))
break; break;
switch (NameR[15]) { return Intrinsic::ppc_altivec_vcmpgtuw_p; // "pc.alti
default: break; vec.vcmpgtuw.p"
case 'b': // 1 string to match.
return Intrinsic::x86_sse2_psubus_b; // "86.sse2.psubus.
b"
case 'w': // 1 string to match.
return Intrinsic::x86_sse2_psubus_w; // "86.sse2.psubus.
w"
}
break;
}
break;
}
break;
case '4': // 4 strings to match.
if (NameR.substr(7, 2) != "1.")
break;
switch (NameR[9]) {
default: break;
case 'b': // 2 strings to match.
if (NameR.substr(10, 5) != "lendp")
break;
switch (NameR[15]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::x86_sse41_blendpd; // "86.sse41.blendp
d"
case 's': // 1 string to match.
return Intrinsic::x86_sse41_blendps; // "86.sse41.blendp
s"
} }
break; break;
case 'm': // 1 string to match.
if (NameR.substr(10, 6) != "psadbw")
break;
return Intrinsic::x86_sse41_mpsadbw; // "86.sse41.mpsadb
w"
case 'p': // 1 string to match.
if (NameR.substr(10, 6) != "blendw")
break;
return Intrinsic::x86_sse41_pblendw; // "86.sse41.pblend
w"
} }
break; break;
} }
break; break;
case 's': // 8 strings to match. }
if (NameR.substr(6, 4) != "e3.p") break;
break; case 'm': // 1 string to match.
switch (NameR[10]) { if (memcmp(NameR.data()+13, "hraddshs", 8))
break;
return Intrinsic::ppc_altivec_vmhraddshs; // "pc.altivec.vmhr
addshs"
}
break;
}
break; // end of 'p' case.
case 'r':
switch (NameR.size()) {
default: break;
case 12: // 1 string to match.
if (memcmp(NameR.data()+0, "eturnaddress", 12))
break;
return Intrinsic::returnaddress; // "eturnaddress"
case 15: // 1 string to match.
if (memcmp(NameR.data()+0, "eadcyclecounter", 15))
break;
return Intrinsic::readcyclecounter; // "eadcyclecounter"
}
break; // end of 'r' case.
case 's':
if (NameR.startswith("add.with.overflow.")) return Intrinsic::sadd_with
_overflow;
if (NameR.startswith("in.")) return Intrinsic::sin;
if (NameR.startswith("mul.with.overflow.")) return Intrinsic::smul_with
_overflow;
if (NameR.startswith("qrt.")) return Intrinsic::sqrt;
if (NameR.startswith("sub.with.overflow.")) return Intrinsic::ssub_with
_overflow;
switch (NameR.size()) {
default: break;
case 5: // 1 string to match.
if (memcmp(NameR.data()+0, "etjmp", 5))
break;
return Intrinsic::setjmp; // "etjmp"
case 7: // 1 string to match.
if (memcmp(NameR.data()+0, "pu.si.a", 7))
break;
return Intrinsic::spu_si_a; // "pu.si.a"
case 8: // 11 strings to match.
switch (NameR[0]) {
default: break;
case 'i': // 1 string to match.
if (memcmp(NameR.data()+1, "gsetjmp", 7))
break;
return Intrinsic::sigsetjmp; // "igsetjmp"
case 'p': // 9 strings to match.
if (memcmp(NameR.data()+1, "u.si.", 5))
break;
switch (NameR[6]) {
default: break;
case 'a': // 2 strings to match.
switch (NameR[7]) {
default: break; default: break;
case 'h': // 4 strings to match. case 'h': // 1 string to match.
switch (NameR[11]) { return Intrinsic::spu_si_ah; // "pu.si.ah"
default: break; case 'i': // 1 string to match.
case 'a': // 2 strings to match. return Intrinsic::spu_si_ai; // "pu.si.ai"
if (NameR.substr(12, 3) != "dd.") }
break; break;
switch (NameR[15]) { case 'b': // 1 string to match.
default: break; if (NameR[7] != 'g')
case 'd': // 1 string to match.
return Intrinsic::x86_ssse3_phadd_d; // "86.ssse3.phadd.
d"
case 'w': // 1 string to match.
return Intrinsic::x86_ssse3_phadd_w; // "86.ssse3.phadd.
w"
}
break;
case 's': // 2 strings to match.
if (NameR.substr(12, 3) != "ub.")
break;
switch (NameR[15]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::x86_ssse3_phsub_d; // "86.ssse3.phsub.
d"
case 'w': // 1 string to match.
return Intrinsic::x86_ssse3_phsub_w; // "86.ssse3.phsub.
w"
}
break;
}
break; break;
case 's': // 4 strings to match. return Intrinsic::spu_si_bg; // "pu.si.bg"
switch (NameR[11]) { case 'c': // 1 string to match.
default: break; if (NameR[7] != 'g')
case 'h': // 1 string to match.
if (NameR.substr(12, 4) != "uf.b")
break;
return Intrinsic::x86_ssse3_pshuf_b; // "86.ssse3.pshuf.
b"
case 'i': // 3 strings to match.
if (NameR.substr(12, 3) != "gn.")
break;
switch (NameR[15]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::x86_ssse3_psign_b; // "86.ssse3.psign.
b"
case 'd': // 1 string to match.
return Intrinsic::x86_ssse3_psign_d; // "86.ssse3.psign.
d"
case 'w': // 1 string to match.
return Intrinsic::x86_ssse3_psign_w; // "86.ssse3.psign.
w"
}
break;
}
break; break;
return Intrinsic::spu_si_cg; // "pu.si.cg"
case 'f': // 3 strings to match.
switch (NameR[7]) {
default: break;
case 'a': // 1 string to match.
return Intrinsic::spu_si_fa; // "pu.si.fa"
case 'm': // 1 string to match.
return Intrinsic::spu_si_fm; // "pu.si.fm"
case 's': // 1 string to match.
return Intrinsic::spu_si_fs; // "pu.si.fs"
} }
break; break;
case 'o': // 1 string to match.
if (NameR[7] != 'r')
break;
return Intrinsic::spu_si_or; // "pu.si.or"
case 's': // 1 string to match.
if (NameR[7] != 'f')
break;
return Intrinsic::spu_si_sf; // "pu.si.sf"
} }
break; break;
case 'v': // 4 strings to match. case 't': // 1 string to match.
if (NameR.substr(4, 4) != "cvtp") if (memcmp(NameR.data()+1, "acksave", 7))
break; break;
switch (NameR[8]) { return Intrinsic::stacksave; // "tacksave"
}
break;
case 9: // 20 strings to match.
switch (NameR[0]) {
default: break;
case 'i': // 1 string to match.
if (memcmp(NameR.data()+1, "glongjmp", 8))
break;
return Intrinsic::siglongjmp; // "iglongjmp"
case 'p': // 19 strings to match.
if (memcmp(NameR.data()+1, "u.si.", 5))
break;
switch (NameR[6]) {
default: break; default: break;
case 'h': // 2 strings to match. case 'a': // 2 strings to match.
if (NameR.substr(9, 4) != "2ps.") switch (NameR[7]) {
break;
switch (NameR[13]) {
default: break; default: break;
case '1': // 1 string to match. case 'h': // 1 string to match.
if (NameR.substr(14, 2) != "28") if (NameR[8] != 'i')
break; break;
return Intrinsic::x86_vcvtph2ps_128; // "86.vcvtph2ps.12 return Intrinsic::spu_si_ahi; // "pu.si.ahi"
8" case 'n': // 1 string to match.
case '2': // 1 string to match. if (NameR[8] != 'd')
if (NameR.substr(14, 2) != "56")
break; break;
return Intrinsic::x86_vcvtph2ps_256; // "86.vcvtph2ps.25 6" return Intrinsic::spu_si_and; // "pu.si.and"
} }
break; break;
case 's': // 2 strings to match. case 'b': // 1 string to match.
if (NameR.substr(9, 4) != "2ph.") if (memcmp(NameR.data()+7, "gx", 2))
break; break;
switch (NameR[13]) { return Intrinsic::spu_si_bgx; // "pu.si.bgx"
case 'c': // 3 strings to match.
switch (NameR[7]) {
default: break; default: break;
case '1': // 1 string to match. case 'e': // 1 string to match.
if (NameR.substr(14, 2) != "28") if (NameR[8] != 'q')
break;
return Intrinsic::x86_vcvtps2ph_128; // "86.vcvtps2ph.12
8"
case '2': // 1 string to match.
if (NameR.substr(14, 2) != "56")
break; break;
return Intrinsic::x86_vcvtps2ph_256; // "86.vcvtps2ph.25 return Intrinsic::spu_si_ceq; // "pu.si.ceq"
6" case 'g': // 2 strings to match.
switch (NameR[8]) {
default: break;
case 't': // 1 string to match.
return Intrinsic::spu_si_cgt; // "pu.si.cgt"
case 'x': // 1 string to match.
return Intrinsic::spu_si_cgx; // "pu.si.cgx"
}
break;
} }
break; break;
} case 'd': // 3 strings to match.
break; if (NameR[7] != 'f')
case 'x': // 36 strings to match.
if (NameR.substr(4, 5) != "op.vp")
break;
switch (NameR[9]) {
default: break;
case 'c': // 24 strings to match.
if (NameR.substr(10, 2) != "om")
break; break;
switch (NameR[12]) { switch (NameR[8]) {
default: break; default: break;
case 'e': // 4 strings to match. case 'a': // 1 string to match.
if (NameR.substr(13, 2) != "qu") return Intrinsic::spu_si_dfa; // "pu.si.dfa"
break; case 'm': // 1 string to match.
switch (NameR[15]) { return Intrinsic::spu_si_dfm; // "pu.si.dfm"
default: break; case 's': // 1 string to match.
case 'b': // 1 string to match. return Intrinsic::spu_si_dfs; // "pu.si.dfs"
return Intrinsic::x86_xop_vpcomequb; // "86.xop.vpcomequ
b"
case 'd': // 1 string to match.
return Intrinsic::x86_xop_vpcomequd; // "86.xop.vpcomequ
d"
case 'q': // 1 string to match.
return Intrinsic::x86_xop_vpcomequq; // "86.xop.vpcomequ
q"
case 'w': // 1 string to match.
return Intrinsic::x86_xop_vpcomequw; // "86.xop.vpcomequ
w"
}
break;
case 'g': // 8 strings to match.
switch (NameR[13]) {
default: break;
case 'e': // 4 strings to match.
if (NameR[14] != 'u')
break;
switch (NameR[15]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::x86_xop_vpcomgeub; // "86.xop.vpcomgeu
b"
case 'd': // 1 string to match.
return Intrinsic::x86_xop_vpcomgeud; // "86.xop.vpcomgeu
d"
case 'q': // 1 string to match.
return Intrinsic::x86_xop_vpcomgeuq; // "86.xop.vpcomgeu
q"
case 'w': // 1 string to match.
return Intrinsic::x86_xop_vpcomgeuw; // "86.xop.vpcomgeu
w"
}
break;
case 't': // 4 strings to match.
if (NameR[14] != 'u')
break;
switch (NameR[15]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::x86_xop_vpcomgtub; // "86.xop.vpcomgtu
b"
case 'd': // 1 string to match.
return Intrinsic::x86_xop_vpcomgtud; // "86.xop.vpcomgtu
d"
case 'q': // 1 string to match.
return Intrinsic::x86_xop_vpcomgtuq; // "86.xop.vpcomgtu
q"
case 'w': // 1 string to match.
return Intrinsic::x86_xop_vpcomgtuw; // "86.xop.vpcomgtu
w"
}
break;
}
break;
case 'l': // 8 strings to match.
switch (NameR[13]) {
default: break;
case 'e': // 4 strings to match.
if (NameR[14] != 'u')
break;
switch (NameR[15]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::x86_xop_vpcomleub; // "86.xop.vpcomleu
b"
case 'd': // 1 string to match.
return Intrinsic::x86_xop_vpcomleud; // "86.xop.vpcomleu
d"
case 'q': // 1 string to match.
return Intrinsic::x86_xop_vpcomleuq; // "86.xop.vpcomleu
q"
case 'w': // 1 string to match.
return Intrinsic::x86_xop_vpcomleuw; // "86.xop.vpcomleu
w"
}
break;
case 't': // 4 strings to match.
if (NameR[14] != 'u')
break;
switch (NameR[15]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::x86_xop_vpcomltub; // "86.xop.vpcomltu
b"
case 'd': // 1 string to match.
return Intrinsic::x86_xop_vpcomltud; // "86.xop.vpcomltu
d"
case 'q': // 1 string to match.
return Intrinsic::x86_xop_vpcomltuq; // "86.xop.vpcomltu
q"
case 'w': // 1 string to match.
return Intrinsic::x86_xop_vpcomltuw; // "86.xop.vpcomltu
w"
}
break;
}
break;
case 'n': // 4 strings to match.
if (NameR.substr(13, 2) != "eu")
break;
switch (NameR[15]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::x86_xop_vpcomneub; // "86.xop.vpcomneu
b"
case 'd': // 1 string to match.
return Intrinsic::x86_xop_vpcomneud; // "86.xop.vpcomneu
d"
case 'q': // 1 string to match.
return Intrinsic::x86_xop_vpcomneuq; // "86.xop.vpcomneu
q"
case 'w': // 1 string to match.
return Intrinsic::x86_xop_vpcomneuw; // "86.xop.vpcomneu
w"
}
break;
} }
break; break;
case 'h': // 6 strings to match. case 'f': // 2 strings to match.
if (NameR.substr(10, 4) != "addu") if (NameR[7] != 'm')
break; break;
switch (NameR[14]) { switch (NameR[8]) {
default: break; default: break;
case 'b': // 3 strings to match. case 'a': // 1 string to match.
switch (NameR[15]) { return Intrinsic::spu_si_fma; // "pu.si.fma"
default: break; case 's': // 1 string to match.
case 'd': // 1 string to match. return Intrinsic::spu_si_fms; // "pu.si.fms"
return Intrinsic::x86_xop_vphaddubd; // "86.xop.vphaddub }
d" break;
case 'q': // 1 string to match. case 'm': // 1 string to match.
return Intrinsic::x86_xop_vphaddubq; // "86.xop.vphaddub if (memcmp(NameR.data()+7, "py", 2))
q"
case 'w': // 1 string to match.
return Intrinsic::x86_xop_vphaddubw; // "86.xop.vphaddub
w"
}
break; break;
case 'd': // 1 string to match. return Intrinsic::spu_si_mpy; // "pu.si.mpy"
if (NameR[15] != 'q') case 'n': // 1 string to match.
break; if (memcmp(NameR.data()+7, "or", 2))
return Intrinsic::x86_xop_vphaddudq; // "86.xop.vphaddud break;
q" return Intrinsic::spu_si_nor; // "pu.si.nor"
case 'w': // 2 strings to match. case 'o': // 2 strings to match.
switch (NameR[15]) { if (NameR[7] != 'r')
default: break;
case 'd': // 1 string to match.
return Intrinsic::x86_xop_vphadduwd; // "86.xop.vphadduw
d"
case 'q': // 1 string to match.
return Intrinsic::x86_xop_vphadduwq; // "86.xop.vphadduw
q"
}
break; break;
switch (NameR[8]) {
default: break;
case 'c': // 1 string to match.
return Intrinsic::spu_si_orc; // "pu.si.orc"
case 'i': // 1 string to match.
return Intrinsic::spu_si_ori; // "pu.si.ori"
} }
break; break;
case 'm': // 6 strings to match. case 's': // 3 strings to match.
if (NameR[10] != 'a') if (NameR[7] != 'f')
break; break;
switch (NameR[11]) { switch (NameR[8]) {
default: break; default: break;
case 'c': // 5 strings to match. case 'h': // 1 string to match.
if (NameR[12] != 's') return Intrinsic::spu_si_sfh; // "pu.si.sfh"
break; case 'i': // 1 string to match.
switch (NameR[13]) { return Intrinsic::spu_si_sfi; // "pu.si.sfi"
default: break; case 'x': // 1 string to match.
case 'd': // 2 strings to match. return Intrinsic::spu_si_sfx; // "pu.si.sfx"
if (NameR[14] != 'q')
break;
switch (NameR[15]) {
default: break;
case 'h': // 1 string to match.
return Intrinsic::x86_xop_vpmacsdqh; // "86.xop.vpmacsdq
h"
case 'l': // 1 string to match.
return Intrinsic::x86_xop_vpmacsdql; // "86.xop.vpmacsdq
l"
}
break;
case 's': // 3 strings to match.
switch (NameR[14]) {
default: break;
case 'd': // 1 string to match.
if (NameR[15] != 'd')
break;
return Intrinsic::x86_xop_vpmacssdd; // "86.xop.vpmacssd
d"
case 'w': // 2 strings to match.
switch (NameR[15]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::x86_xop_vpmacsswd; // "86.xop.vpmacssw
d"
case 'w': // 1 string to match.
return Intrinsic::x86_xop_vpmacssww; // "86.xop.vpmacssw
w"
}
break;
}
break;
}
break;
case 'd': // 1 string to match.
if (NameR.substr(12, 4) != "cswd")
break;
return Intrinsic::x86_xop_vpmadcswd; // "86.xop.vpmadcsw
d"
} }
break; break;
case 'x': // 1 string to match.
if (memcmp(NameR.data()+7, "or", 2))
break;
return Intrinsic::spu_si_xor; // "pu.si.xor"
} }
break; break;
} }
break; break;
case 17: // 80 strings to match. case 10: // 26 strings to match.
if (NameR.substr(0, 3) != "86.") if (memcmp(NameR.data()+0, "pu.si.", 6))
break; break;
switch (NameR[3]) { switch (NameR[6]) {
default: break; default: break;
case '3': // 4 strings to match. case 'a': // 3 strings to match.
if (NameR.substr(4, 4) != "dnow") switch (NameR[7]) {
break;
switch (NameR[8]) {
default: break; default: break;
case '.': // 3 strings to match. case 'd': // 1 string to match.
if (NameR.substr(9, 3) != "pfr") if (memcmp(NameR.data()+8, "dx", 2))
break; break;
switch (NameR[12]) { return Intrinsic::spu_si_addx; // "pu.si.addx"
default: break; case 'n': // 2 strings to match.
case 'c': // 2 strings to match. if (NameR[8] != 'd')
if (NameR.substr(13, 3) != "pit")
break;
switch (NameR[16]) {
default: break;
case '1': // 1 string to match.
return Intrinsic::x86_3dnow_pfrcpit1; // "86.3dnow.pfrcpi
t1"
case '2': // 1 string to match.
return Intrinsic::x86_3dnow_pfrcpit2; // "86.3dnow.pfrcpi
t2"
}
break; break;
case 's': // 1 string to match. switch (NameR[9]) {
if (NameR.substr(13, 4) != "qit1") default: break;
break; case 'c': // 1 string to match.
return Intrinsic::x86_3dnow_pfrsqit1; // "86.3dnow.pfrsqi return Intrinsic::spu_si_andc; // "pu.si.andc"
t1" case 'i': // 1 string to match.
return Intrinsic::spu_si_andi; // "pu.si.andi"
} }
break; break;
case 'a': // 1 string to match.
if (NameR.substr(9, 8) != ".pfpnacc")
break;
return Intrinsic::x86_3dnowa_pfpnacc; // "86.3dnowa.pfpna
cc"
} }
break; break;
case 'a': // 11 strings to match. case 'c': // 7 strings to match.
if (NameR.substr(4, 3) != "vx.")
break;
switch (NameR[7]) { switch (NameR[7]) {
default: break; default: break;
case 'c': // 2 strings to match. case 'e': // 3 strings to match.
if (NameR.substr(8, 4) != "mp.p") if (NameR[8] != 'q')
break; break;
switch (NameR[12]) { switch (NameR[9]) {
default: break; default: break;
case 'd': // 1 string to match. case 'b': // 1 string to match.
if (NameR.substr(13, 4) != ".256") return Intrinsic::spu_si_ceqb; // "pu.si.ceqb"
break; case 'h': // 1 string to match.
return Intrinsic::x86_avx_cmp_pd_256; // "86.avx.cmp.pd.2 return Intrinsic::spu_si_ceqh; // "pu.si.ceqh"
56" case 'i': // 1 string to match.
case 's': // 1 string to match. return Intrinsic::spu_si_ceqi; // "pu.si.ceqi"
if (NameR.substr(13, 4) != ".256")
break;
return Intrinsic::x86_avx_cmp_ps_256; // "86.avx.cmp.ps.2
56"
} }
break; break;
case 'l': // 1 string to match. case 'g': // 3 strings to match.
if (NameR.substr(8, 9) != "du.dq.256") if (NameR[8] != 't')
break; break;
return Intrinsic::x86_avx_ldu_dq_256; // "86.avx.ldu.dq.2 switch (NameR[9]) {
56"
case 'm': // 4 strings to match.
switch (NameR[8]) {
default: break; default: break;
case 'a': // 2 strings to match. case 'b': // 1 string to match.
if (NameR.substr(9, 3) != "x.p") return Intrinsic::spu_si_cgtb; // "pu.si.cgtb"
break; case 'h': // 1 string to match.
switch (NameR[12]) { return Intrinsic::spu_si_cgth; // "pu.si.cgth"
default: break; case 'i': // 1 string to match.
case 'd': // 1 string to match. return Intrinsic::spu_si_cgti; // "pu.si.cgti"
if (NameR.substr(13, 4) != ".256")
break;
return Intrinsic::x86_avx_max_pd_256; // "86.avx.max.pd.2
56"
case 's': // 1 string to match.
if (NameR.substr(13, 4) != ".256")
break;
return Intrinsic::x86_avx_max_ps_256; // "86.avx.max.ps.2
56"
}
break;
case 'i': // 2 strings to match.
if (NameR.substr(9, 3) != "n.p")
break;
switch (NameR[12]) {
default: break;
case 'd': // 1 string to match.
if (NameR.substr(13, 4) != ".256")
break;
return Intrinsic::x86_avx_min_pd_256; // "86.avx.min.pd.2
56"
case 's': // 1 string to match.
if (NameR.substr(13, 4) != ".256")
break;
return Intrinsic::x86_avx_min_ps_256; // "86.avx.min.ps.2
56"
}
break;
} }
break; break;
case 'p': // 2 strings to match. case 'l': // 1 string to match.
if (NameR.substr(8, 4) != "test") if (memcmp(NameR.data()+8, "gt", 2))
break; break;
switch (NameR[12]) { return Intrinsic::spu_si_clgt; // "pu.si.clgt"
}
break;
case 'd': // 2 strings to match.
if (memcmp(NameR.data()+7, "fm", 2))
break;
switch (NameR[9]) {
default: break;
case 'a': // 1 string to match.
return Intrinsic::spu_si_dfma; // "pu.si.dfma"
case 's': // 1 string to match.
return Intrinsic::spu_si_dfms; // "pu.si.dfms"
}
break;
case 'f': // 3 strings to match.
switch (NameR[7]) {
default: break;
case 'c': // 2 strings to match.
switch (NameR[8]) {
default: break; default: break;
case 'c': // 1 string to match. case 'e': // 1 string to match.
if (NameR.substr(13, 4) != ".256") if (NameR[9] != 'q')
break; break;
return Intrinsic::x86_avx_ptestc_256; // "86.avx.ptestc.2 return Intrinsic::spu_si_fceq; // "pu.si.fceq"
56" case 'g': // 1 string to match.
case 'z': // 1 string to match. if (NameR[9] != 't')
if (NameR.substr(13, 4) != ".256")
break; break;
return Intrinsic::x86_avx_ptestz_256; // "86.avx.ptestz.2 56" return Intrinsic::spu_si_fcgt; // "pu.si.fcgt"
} }
break; break;
case 'r': // 1 string to match. case 'n': // 1 string to match.
if (NameR.substr(8, 9) != "cp.ps.256") if (memcmp(NameR.data()+8, "ms", 2))
break; break;
return Intrinsic::x86_avx_rcp_ps_256; // "86.avx.rcp.ps.2 return Intrinsic::spu_si_fnms; // "pu.si.fnms"
56" }
case 'v': // 1 string to match. break;
if (NameR.substr(8, 9) != "zeroupper") case 'm': // 5 strings to match.
if (memcmp(NameR.data()+7, "py", 2))
break;
switch (NameR[9]) {
default: break;
case 'a': // 1 string to match.
return Intrinsic::spu_si_mpya; // "pu.si.mpya"
case 'h': // 1 string to match.
return Intrinsic::spu_si_mpyh; // "pu.si.mpyh"
case 'i': // 1 string to match.
return Intrinsic::spu_si_mpyi; // "pu.si.mpyi"
case 's': // 1 string to match.
return Intrinsic::spu_si_mpys; // "pu.si.mpys"
case 'u': // 1 string to match.
return Intrinsic::spu_si_mpyu; // "pu.si.mpyu"
}
break;
case 'n': // 1 string to match.
if (memcmp(NameR.data()+7, "and", 3))
break;
return Intrinsic::spu_si_nand; // "pu.si.nand"
case 'o': // 2 strings to match.
if (NameR[7] != 'r')
break;
switch (NameR[8]) {
default: break;
case 'b': // 1 string to match.
if (NameR[9] != 'i')
break; break;
return Intrinsic::x86_avx_vzeroupper; // "86.avx.vzeroupp return Intrinsic::spu_si_orbi; // "pu.si.orbi"
er" case 'h': // 1 string to match.
if (NameR[9] != 'i')
break;
return Intrinsic::spu_si_orhi; // "pu.si.orhi"
} }
break; break;
case 'f': // 8 strings to match. case 's': // 2 strings to match.
if (NameR.substr(4, 7) != "ma4.vfm") switch (NameR[7]) {
default: break;
case 'f': // 1 string to match.
if (memcmp(NameR.data()+8, "hi", 2))
break;
return Intrinsic::spu_si_sfhi; // "pu.si.sfhi"
case 'h': // 1 string to match.
if (memcmp(NameR.data()+8, "li", 2))
break;
return Intrinsic::spu_si_shli; // "pu.si.shli"
}
break;
case 'x': // 1 string to match.
if (memcmp(NameR.data()+7, "ori", 3))
break; break;
switch (NameR[11]) { return Intrinsic::spu_si_xori; // "pu.si.xori"
}
break;
case 11: // 19 strings to match.
switch (NameR[0]) {
default: break;
case 'p': // 18 strings to match.
if (memcmp(NameR.data()+1, "u.si.", 5))
break;
switch (NameR[6]) {
default: break; default: break;
case 'a': // 4 strings to match. case 'a': // 2 strings to match.
if (NameR.substr(12, 3) != "dd.") if (memcmp(NameR.data()+7, "nd", 2))
break; break;
switch (NameR[15]) { switch (NameR[9]) {
default: break; default: break;
case 'p': // 2 strings to match. case 'b': // 1 string to match.
switch (NameR[16]) { if (NameR[10] != 'i')
break;
return Intrinsic::spu_si_andbi; // "pu.si.andbi"
case 'h': // 1 string to match.
if (NameR[10] != 'i')
break;
return Intrinsic::spu_si_andhi; // "pu.si.andhi"
}
break;
case 'c': // 7 strings to match.
switch (NameR[7]) {
default: break;
case 'e': // 2 strings to match.
if (NameR[8] != 'q')
break;
switch (NameR[9]) {
default: break; default: break;
case 'd': // 1 string to match. case 'b': // 1 string to match.
return Intrinsic::x86_fma4_vfmadd_pd; // "86.fma4.vfmadd. if (NameR[10] != 'i')
pd" break;
case 's': // 1 string to match. return Intrinsic::spu_si_ceqbi; // "pu.si.ceqbi"
return Intrinsic::x86_fma4_vfmadd_ps; // "86.fma4.vfmadd. case 'h': // 1 string to match.
ps" if (NameR[10] != 'i')
break;
return Intrinsic::spu_si_ceqhi; // "pu.si.ceqhi"
} }
break; break;
case 's': // 2 strings to match. case 'g': // 2 strings to match.
switch (NameR[16]) { if (NameR[8] != 't')
break;
switch (NameR[9]) {
default: break; default: break;
case 'd': // 1 string to match. case 'b': // 1 string to match.
return Intrinsic::x86_fma4_vfmadd_sd; // "86.fma4.vfmadd. if (NameR[10] != 'i')
sd" break;
case 's': // 1 string to match. return Intrinsic::spu_si_cgtbi; // "pu.si.cgtbi"
return Intrinsic::x86_fma4_vfmadd_ss; // "86.fma4.vfmadd. case 'h': // 1 string to match.
ss" if (NameR[10] != 'i')
break;
return Intrinsic::spu_si_cgthi; // "pu.si.cgthi"
}
break;
case 'l': // 3 strings to match.
if (memcmp(NameR.data()+8, "gt", 2))
break;
switch (NameR[10]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::spu_si_clgtb; // "pu.si.clgtb"
case 'h': // 1 string to match.
return Intrinsic::spu_si_clgth; // "pu.si.clgth"
case 'i': // 1 string to match.
return Intrinsic::spu_si_clgti; // "pu.si.clgti"
} }
break; break;
} }
break; break;
case 's': // 4 strings to match. case 'd': // 2 strings to match.
if (NameR.substr(12, 3) != "ub.") if (memcmp(NameR.data()+7, "fnm", 3))
break; break;
switch (NameR[15]) { switch (NameR[10]) {
default: break; default: break;
case 'p': // 2 strings to match. case 'a': // 1 string to match.
switch (NameR[16]) { return Intrinsic::spu_si_dfnma; // "pu.si.dfnma"
case 's': // 1 string to match.
return Intrinsic::spu_si_dfnms; // "pu.si.dfnms"
}
break;
case 'f': // 3 strings to match.
switch (NameR[7]) {
default: break;
case 'c': // 2 strings to match.
if (NameR[8] != 'm')
break;
switch (NameR[9]) {
default: break; default: break;
case 'd': // 1 string to match. case 'e': // 1 string to match.
return Intrinsic::x86_fma4_vfmsub_pd; // "86.fma4.vfmsub. if (NameR[10] != 'q')
pd" break;
case 's': // 1 string to match. return Intrinsic::spu_si_fcmeq; // "pu.si.fcmeq"
return Intrinsic::x86_fma4_vfmsub_ps; // "86.fma4.vfmsub. case 'g': // 1 string to match.
ps" if (NameR[10] != 't')
break;
return Intrinsic::spu_si_fcmgt; // "pu.si.fcmgt"
} }
break; break;
case 's': // 2 strings to match. case 's': // 1 string to match.
switch (NameR[16]) { if (memcmp(NameR.data()+8, "mbi", 3))
default: break; break;
case 'd': // 1 string to match. return Intrinsic::spu_si_fsmbi; // "pu.si.fsmbi"
return Intrinsic::x86_fma4_vfmsub_sd; // "86.fma4.vfmsub. }
sd" break;
case 's': // 1 string to match. case 'm': // 2 strings to match.
return Intrinsic::x86_fma4_vfmsub_ss; // "86.fma4.vfmsub. if (memcmp(NameR.data()+7, "py", 2))
ss" break;
} switch (NameR[9]) {
default: break;
case 'h': // 1 string to match.
if (NameR[10] != 'h')
break;
return Intrinsic::spu_si_mpyhh; // "pu.si.mpyhh"
case 'u': // 1 string to match.
if (NameR[10] != 'i')
break;
return Intrinsic::spu_si_mpyui; // "pu.si.mpyui"
}
break;
case 'x': // 2 strings to match.
if (memcmp(NameR.data()+7, "or", 2))
break; break;
switch (NameR[9]) {
default: break;
case 'b': // 1 string to match.
if (NameR[10] != 'i')
break;
return Intrinsic::spu_si_xorbi; // "pu.si.xorbi"
case 'h': // 1 string to match.
if (NameR[10] != 'i')
break;
return Intrinsic::spu_si_xorhi; // "pu.si.xorhi"
} }
break; break;
} }
break; break;
case 's': // 47 strings to match. case 't': // 1 string to match.
if (NameR[4] != 's') if (memcmp(NameR.data()+1, "ackrestore", 10))
break; break;
switch (NameR[5]) { return Intrinsic::stackrestore; // "tackrestore"
}
break;
case 12: // 6 strings to match.
if (memcmp(NameR.data()+0, "pu.si.", 6))
break;
switch (NameR[6]) {
default: break;
case 'c': // 2 strings to match.
if (memcmp(NameR.data()+7, "lgt", 3))
break;
switch (NameR[10]) {
default: break; default: break;
case 'e': // 45 strings to match. case 'b': // 1 string to match.
switch (NameR[6]) { if (NameR[11] != 'i')
default: break;
case '.': // 8 strings to match.
switch (NameR[7]) {
default: break;
case 'c': // 3 strings to match.
switch (NameR[8]) {
default: break;
case 'o': // 1 string to match.
if (NameR.substr(9, 8) != "mineq.ss")
break;
return Intrinsic::x86_sse_comineq_ss; // "86.sse.comineq.
ss"
case 'v': // 2 strings to match.
if (NameR.substr(9, 2) != "ts")
break;
switch (NameR[11]) {
default: break;
case 'i': // 1 string to match.
if (NameR.substr(12, 5) != "642ss")
break;
return Intrinsic::x86_sse_cvtsi642ss; // "86.sse.
cvtsi642ss"
case 's': // 1 string to match.
if (NameR.substr(12, 5) != "2si64")
break;
return Intrinsic::x86_sse_cvtss2si64; // "86.sse.
cvtss2si64"
}
break;
}
break;
case 'u': // 5 strings to match.
if (NameR.substr(8, 4) != "comi")
break;
switch (NameR[12]) {
default: break;
case 'e': // 1 string to match.
if (NameR.substr(13, 4) != "q.ss")
break;
return Intrinsic::x86_sse_ucomieq_ss; // "86.sse.ucomieq.
ss"
case 'g': // 2 strings to match.
switch (NameR[13]) {
default: break;
case 'e': // 1 string to match.
if (NameR.substr(14, 3) != ".ss")
break;
return Intrinsic::x86_sse_ucomige_ss; // "86.sse.
ucomige.ss"
case 't': // 1 string to match.
if (NameR.substr(14, 3) != ".ss")
break;
return Intrinsic::x86_sse_ucomigt_ss; // "86.sse.
ucomigt.ss"
}
break;
case 'l': // 2 strings to match.
switch (NameR[13]) {
default: break;
case 'e': // 1 string to match.
if (NameR.substr(14, 3) != ".ss")
break;
return Intrinsic::x86_sse_ucomile_ss; // "86.sse.
ucomile.ss"
case 't': // 1 string to match.
if (NameR.substr(14, 3) != ".ss")
break;
return Intrinsic::x86_sse_ucomilt_ss; // "86.sse.
ucomilt.ss"
}
break;
}
break;
}
break; break;
case '2': // 12 strings to match. return Intrinsic::spu_si_clgtbi; // "pu.si.clgtbi"
if (NameR[7] != '.') case 'h': // 1 string to match.
break; if (NameR[11] != 'i')
switch (NameR[8]) {
default: break;
case 'c': // 8 strings to match.
switch (NameR[9]) {
default: break;
case 'o': // 5 strings to match.
if (NameR.substr(10, 2) != "mi")
break;
switch (NameR[12]) {
default: break;
case 'e': // 1 string to match.
if (NameR.substr(13, 4) != "q.sd")
break;
return Intrinsic::x86_sse2_comieq_sd; // "86.sse2
.comieq.sd"
case 'g': // 2 strings to match.
switch (NameR[13]) {
default: break;
case 'e': // 1 string to match.
if (NameR.substr(14, 3) != ".sd")
break;
return Intrinsic::x86_sse2_comige_sd; // "86.sse2
.comige.sd"
case 't': // 1 string to match.
if (NameR.substr(14, 3) != ".sd")
break;
return Intrinsic::x86_sse2_comigt_sd; // "86.sse2
.comigt.sd"
}
break;
case 'l': // 2 strings to match.
switch (NameR[13]) {
default: break;
case 'e': // 1 string to match.
if (NameR.substr(14, 3) != ".sd")
break;
return Intrinsic::x86_sse2_comile_sd; // "86.sse2
.comile.sd"
case 't': // 1 string to match.
if (NameR.substr(14, 3) != ".sd")
break;
return Intrinsic::x86_sse2_comilt_sd; // "86.sse2
.comilt.sd"
}
break;
}
break;
case 'v': // 3 strings to match.
if (NameR.substr(10, 2) != "tt")
break;
switch (NameR[12]) {
default: break;
case 'p': // 2 strings to match.
switch (NameR[13]) {
default: break;
case 'd': // 1 string to match.
if (NameR.substr(14, 3) != "2dq")
break;
return Intrinsic::x86_sse2_cvttpd2dq; // "86.sse2
.cvttpd2dq"
case 's': // 1 string to match.
if (NameR.substr(14, 3) != "2dq")
break;
return Intrinsic::x86_sse2_cvttps2dq; // "86.sse2
.cvttps2dq"
}
break;
case 's': // 1 string to match.
if (NameR.substr(13, 4) != "d2si")
break;
return Intrinsic::x86_sse2_cvttsd2si; // "86.sse2
.cvttsd2si"
}
break;
}
break;
case 'm': // 1 string to match.
if (NameR.substr(9, 8) != "ovmsk.pd")
break;
return Intrinsic::x86_sse2_movmsk_pd; // "86.sse2.movmsk.
pd"
case 's': // 3 strings to match.
if (NameR.substr(9, 4) != "tore")
break;
switch (NameR[13]) {
default: break;
case 'l': // 1 string to match.
if (NameR.substr(14, 3) != ".dq")
break;
return Intrinsic::x86_sse2_storel_dq; // "86.sse2.storel.
dq"
case 'u': // 2 strings to match.
if (NameR[14] != '.')
break;
switch (NameR[15]) {
default: break;
case 'd': // 1 string to match.
if (NameR[16] != 'q')
break;
return Intrinsic::x86_sse2_storeu_dq; // "86.sse2
.storeu.dq"
case 'p': // 1 string to match.
if (NameR[16] != 'd')
break;
return Intrinsic::x86_sse2_storeu_pd; // "86.sse2
.storeu.pd"
}
break;
}
break;
}
break; break;
case '3': // 2 strings to match. return Intrinsic::spu_si_clgthi; // "pu.si.clgthi"
if (NameR.substr(7, 9) != ".addsub.p") }
break; break;
switch (NameR[16]) { case 'm': // 2 strings to match.
default: break; if (memcmp(NameR.data()+7, "pyhh", 4))
case 'd': // 1 string to match. break;
return Intrinsic::x86_sse3_addsub_pd; // "86.sse3.addsub. switch (NameR[11]) {
pd" default: break;
case 's': // 1 string to match. case 'a': // 1 string to match.
return Intrinsic::x86_sse3_addsub_ps; // "86.sse3.addsub. return Intrinsic::spu_si_mpyhha; // "pu.si.mpyhha"
ps" case 'u': // 1 string to match.
} return Intrinsic::spu_si_mpyhhu; // "pu.si.mpyhhu"
}
break;
case 's': // 2 strings to match.
if (memcmp(NameR.data()+7, "hlqb", 4))
break;
switch (NameR[11]) {
default: break;
case 'i': // 1 string to match.
return Intrinsic::spu_si_shlqbi; // "pu.si.shlqbi"
case 'y': // 1 string to match.
return Intrinsic::spu_si_shlqby; // "pu.si.shlqby"
}
break;
}
break;
case 13: // 4 strings to match.
switch (NameR[0]) {
default: break;
case 'p': // 3 strings to match.
if (memcmp(NameR.data()+1, "u.si.", 5))
break;
switch (NameR[6]) {
default: break;
case 'm': // 1 string to match.
if (memcmp(NameR.data()+7, "pyhhau", 6))
break; break;
case '4': // 23 strings to match. return Intrinsic::spu_si_mpyhhau; // "pu.si.mpyhhau"
if (NameR.substr(7, 2) != "1.") case 's': // 2 strings to match.
if (memcmp(NameR.data()+7, "hlqb", 4))
break;
switch (NameR[11]) {
default: break;
case 'i': // 1 string to match.
if (NameR[12] != 'i')
break; break;
switch (NameR[9]) { return Intrinsic::spu_si_shlqbii; // "pu.si.shlqbii"
default: break; case 'y': // 1 string to match.
case 'b': // 2 strings to match. if (NameR[12] != 'i')
if (NameR.substr(10, 6) != "lendvp")
break;
switch (NameR[16]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::x86_sse41_blendvpd; // "86.sse41.blendv
pd"
case 's': // 1 string to match.
return Intrinsic::x86_sse41_blendvps; // "86.sse41.blendv
ps"
}
break; break;
case 'i': // 1 string to match. return Intrinsic::spu_si_shlqbyi; // "pu.si.shlqbyi"
if (NameR.substr(10, 7) != "nsertps")
break;
return Intrinsic::x86_sse41_insertps; // "86.sse41.insert
ps"
case 'm': // 1 string to match.
if (NameR.substr(10, 7) != "ovntdqa")
break;
return Intrinsic::x86_sse41_movntdqa; // "86.sse41.movntd
qa"
case 'p': // 15 strings to match.
switch (NameR[10]) {
default: break;
case 'a': // 1 string to match.
if (NameR.substr(11, 6) != "ckusdw")
break;
return Intrinsic::x86_sse41_packusdw; // "86.sse41.packus
dw"
case 'b': // 1 string to match.
if (NameR.substr(11, 6) != "lendvb")
break;
return Intrinsic::x86_sse41_pblendvb; // "86.sse41.pblend
vb"
case 'm': // 12 strings to match.
if (NameR.substr(11, 2) != "ov")
break;
switch (NameR[13]) {
default: break;
case 's': // 6 strings to match.
if (NameR[14] != 'x')
break;
switch (NameR[15]) {
default: break;
case 'b': // 3 strings to match.
switch (NameR[16]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::x86_sse41_pmovsxbd; // "86.sse4
1.pmovsxbd"
case 'q': // 1 string to match.
return Intrinsic::x86_sse41_pmovsxbq; // "86.sse4
1.pmovsxbq"
case 'w': // 1 string to match.
return Intrinsic::x86_sse41_pmovsxbw; // "86.sse4
1.pmovsxbw"
}
break;
case 'd': // 1 string to match.
if (NameR[16] != 'q')
break;
return Intrinsic::x86_sse41_pmovsxdq; // "86.sse4
1.pmovsxdq"
case 'w': // 2 strings to match.
switch (NameR[16]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::x86_sse41_pmovsxwd; // "86.sse4
1.pmovsxwd"
case 'q': // 1 string to match.
return Intrinsic::x86_sse41_pmovsxwq; // "86.sse4
1.pmovsxwq"
}
break;
}
break;
case 'z': // 6 strings to match.
if (NameR[14] != 'x')
break;
switch (NameR[15]) {
default: break;
case 'b': // 3 strings to match.
switch (NameR[16]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::x86_sse41_pmovzxbd; // "86.sse4
1.pmovzxbd"
case 'q': // 1 string to match.
return Intrinsic::x86_sse41_pmovzxbq; // "86.sse4
1.pmovzxbq"
case 'w': // 1 string to match.
return Intrinsic::x86_sse41_pmovzxbw; // "86.sse4
1.pmovzxbw"
}
break;
case 'd': // 1 string to match.
if (NameR[16] != 'q')
break;
return Intrinsic::x86_sse41_pmovzxdq; // "86.sse4
1.pmovzxdq"
case 'w': // 2 strings to match.
switch (NameR[16]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::x86_sse41_pmovzxwd; // "86.sse4
1.pmovzxwd"
case 'q': // 1 string to match.
return Intrinsic::x86_sse41_pmovzxwq; // "86.sse4
1.pmovzxwq"
}
break;
}
break;
}
break;
case 't': // 1 string to match.
if (NameR.substr(11, 6) != "estnzc")
break;
return Intrinsic::x86_sse41_ptestnzc; // "86.sse41.ptestn
zc"
}
break;
case 'r': // 4 strings to match.
if (NameR.substr(10, 5) != "ound.")
break;
switch (NameR[15]) {
default: break;
case 'p': // 2 strings to match.
switch (NameR[16]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::x86_sse41_round_pd; // "86.sse4
1.round.pd"
case 's': // 1 string to match.
return Intrinsic::x86_sse41_round_ps; // "86.sse4
1.round.ps"
}
break;
case 's': // 2 strings to match.
switch (NameR[16]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::x86_sse41_round_sd; // "86.sse4
1.round.sd"
case 's': // 1 string to match.
return Intrinsic::x86_sse41_round_ss; // "86.sse4
1.round.ss"
}
break;
}
break;
}
break;
} }
break; break;
case 's': // 2 strings to match. }
if (NameR.substr(6, 5) != "e3.ph") break;
case 't': // 1 string to match.
if (memcmp(NameR.data()+1, "ackprotector", 12))
break;
return Intrinsic::stackprotector; // "tackprotector"
}
break;
}
break; // end of 's' case.
case 't':
switch (NameR.size()) {
default: break;
case 3: // 1 string to match.
if (memcmp(NameR.data()+0, "rap", 3))
break;
return Intrinsic::trap; // "rap"
}
break; // end of 't' case.
case 'u':
if (NameR.startswith("add.with.overflow.")) return Intrinsic::uadd_with
_overflow;
if (NameR.startswith("mul.with.overflow.")) return Intrinsic::umul_with
_overflow;
if (NameR.startswith("sub.with.overflow.")) return Intrinsic::usub_with
_overflow;
break; // end of 'u' case.
case 'v':
switch (NameR.size()) {
default: break;
case 5: // 1 string to match.
if (memcmp(NameR.data()+0, "a_end", 5))
break;
return Intrinsic::vaend; // "a_end"
case 6: // 1 string to match.
if (memcmp(NameR.data()+0, "a_copy", 6))
break;
return Intrinsic::vacopy; // "a_copy"
case 7: // 1 string to match.
if (memcmp(NameR.data()+0, "a_start", 7))
break;
return Intrinsic::vastart; // "a_start"
case 13: // 1 string to match.
if (memcmp(NameR.data()+0, "ar.annotation", 13))
break;
return Intrinsic::var_annotation; // "ar.annotation"
}
break; // end of 'v' case.
case 'x':
if (NameR.startswith("core.chkct.")) return Intrinsic::xcore_chkct;
if (NameR.startswith("core.eeu.")) return Intrinsic::xcore_eeu;
if (NameR.startswith("core.endin.")) return Intrinsic::xcore_endin;
if (NameR.startswith("core.freer.")) return Intrinsic::xcore_freer;
if (NameR.startswith("core.getr.")) return Intrinsic::xcore_getr;
if (NameR.startswith("core.getst.")) return Intrinsic::xcore_getst;
if (NameR.startswith("core.getts.")) return Intrinsic::xcore_getts;
if (NameR.startswith("core.in.")) return Intrinsic::xcore_in;
if (NameR.startswith("core.inct.")) return Intrinsic::xcore_inct;
if (NameR.startswith("core.initcp.")) return Intrinsic::xcore_initcp;
if (NameR.startswith("core.initdp.")) return Intrinsic::xcore_initdp;
if (NameR.startswith("core.initlr.")) return Intrinsic::xcore_initlr;
if (NameR.startswith("core.initpc.")) return Intrinsic::xcore_initpc;
if (NameR.startswith("core.initsp.")) return Intrinsic::xcore_initsp;
if (NameR.startswith("core.inshr.")) return Intrinsic::xcore_inshr;
if (NameR.startswith("core.int.")) return Intrinsic::xcore_int;
if (NameR.startswith("core.mjoin.")) return Intrinsic::xcore_mjoin;
if (NameR.startswith("core.msync.")) return Intrinsic::xcore_msync;
if (NameR.startswith("core.out.")) return Intrinsic::xcore_out;
if (NameR.startswith("core.outct.")) return Intrinsic::xcore_outct;
if (NameR.startswith("core.outshr.")) return Intrinsic::xcore_outshr;
if (NameR.startswith("core.outt.")) return Intrinsic::xcore_outt;
if (NameR.startswith("core.peek.")) return Intrinsic::xcore_peek;
if (NameR.startswith("core.setc.")) return Intrinsic::xcore_setc;
if (NameR.startswith("core.setclk.")) return Intrinsic::xcore_setclk;
if (NameR.startswith("core.setd.")) return Intrinsic::xcore_setd;
if (NameR.startswith("core.setev.")) return Intrinsic::xcore_setev;
if (NameR.startswith("core.setpsc.")) return Intrinsic::xcore_setpsc;
if (NameR.startswith("core.setpt.")) return Intrinsic::xcore_setpt;
if (NameR.startswith("core.setrdy.")) return Intrinsic::xcore_setrdy;
if (NameR.startswith("core.settw.")) return Intrinsic::xcore_settw;
if (NameR.startswith("core.setv.")) return Intrinsic::xcore_setv;
if (NameR.startswith("core.syncr.")) return Intrinsic::xcore_syncr;
if (NameR.startswith("core.testct.")) return Intrinsic::xcore_testct;
if (NameR.startswith("core.testwct.")) return Intrinsic::xcore_testwct;
switch (NameR.size()) {
default: break;
case 6: // 1 string to match.
if (memcmp(NameR.data()+0, "86.int", 6))
break;
return Intrinsic::x86_int; // "86.int"
case 7: // 1 string to match.
if (memcmp(NameR.data()+0, "86.xend", 7))
break;
return Intrinsic::x86_xend; // "86.xend"
case 9: // 6 strings to match.
switch (NameR[0]) {
default: break;
case '8': // 2 strings to match.
if (memcmp(NameR.data()+1, "6.x", 3))
break;
switch (NameR[4]) {
default: break;
case 'a': // 1 string to match.
if (memcmp(NameR.data()+5, "bort", 4))
break; break;
switch (NameR[11]) { return Intrinsic::x86_xabort; // "86.xabort"
case 'b': // 1 string to match.
if (memcmp(NameR.data()+5, "egin", 4))
break;
return Intrinsic::x86_xbegin; // "86.xbegin"
}
break;
case 'c': // 4 strings to match.
if (memcmp(NameR.data()+1, "ore.", 4))
break;
switch (NameR[5]) {
default: break;
case 'c': // 2 strings to match.
switch (NameR[6]) {
default: break; default: break;
case 'a': // 1 string to match. case 'l': // 1 string to match.
if (NameR.substr(12, 5) != "dd.sw") if (memcmp(NameR.data()+7, "re", 2))
break; break;
return Intrinsic::x86_ssse3_phadd_sw; // "86.ssse3.phadd. return Intrinsic::xcore_clre; // "core.clre"
sw" case 'r': // 1 string to match.
case 's': // 1 string to match. if (memcmp(NameR.data()+7, "c8", 2))
if (NameR.substr(12, 5) != "ub.sw")
break; break;
return Intrinsic::x86_ssse3_phsub_sw; // "86.ssse3.phsub. sw" return Intrinsic::xcore_crc8; // "core.crc8"
} }
break; break;
case 's': // 1 string to match.
if (memcmp(NameR.data()+6, "ext", 3))
break;
return Intrinsic::xcore_sext; // "core.sext"
case 'z': // 1 string to match.
if (memcmp(NameR.data()+6, "ext", 3))
break;
return Intrinsic::xcore_zext; // "core.zext"
} }
break; break;
case 'x': // 10 strings to match. }
if (NameR.substr(4, 5) != "op.vp") break;
case 10: // 10 strings to match.
switch (NameR[0]) {
default: break;
case '8': // 1 string to match.
if (memcmp(NameR.data()+1, "6.mmx.por", 9))
break; break;
switch (NameR[9]) { return Intrinsic::x86_mmx_por; // "86.mmx.por"
case 'c': // 9 strings to match.
if (memcmp(NameR.data()+1, "ore.", 4))
break;
switch (NameR[5]) {
default: break; default: break;
case 'c': // 5 strings to match. case 'c': // 2 strings to match.
switch (NameR[10]) { switch (NameR[6]) {
default: break; default: break;
case 'm': // 1 string to match. case 'l': // 1 string to match.
if (NameR.substr(11, 6) != "ov.256") if (memcmp(NameR.data()+7, "rsr", 3))
break; break;
return Intrinsic::x86_xop_vpcmov_256; // "86.xop.vpcmov.2 return Intrinsic::xcore_clrsr; // "core.clrsr"
56" case 'r': // 1 string to match.
case 'o': // 4 strings to match. if (memcmp(NameR.data()+7, "c32", 3))
if (NameR.substr(11, 5) != "mtrue")
break; break;
switch (NameR[16]) { return Intrinsic::xcore_crc32; // "core.crc32"
}
break;
case 'g': // 4 strings to match.
if (memcmp(NameR.data()+6, "et", 2))
break;
switch (NameR[8]) {
default: break;
case 'e': // 2 strings to match.
switch (NameR[9]) {
default: break; default: break;
case 'b': // 1 string to match.
return Intrinsic::x86_xop_vpcomtrueb; // "86.xop.vpcomtru
eb"
case 'd': // 1 string to match. case 'd': // 1 string to match.
return Intrinsic::x86_xop_vpcomtrued; // "86.xop.vpcomtru return Intrinsic::xcore_geted; // "core.geted"
ed" case 't': // 1 string to match.
case 'q': // 1 string to match. return Intrinsic::xcore_getet; // "core.getet"
return Intrinsic::x86_xop_vpcomtrueq; // "86.xop.vpcomtru
eq"
case 'w': // 1 string to match.
return Intrinsic::x86_xop_vpcomtruew; // "86.xop.vpcomtru
ew"
} }
break; break;
case 'i': // 1 string to match.
if (NameR[9] != 'd')
break;
return Intrinsic::xcore_getid; // "core.getid"
case 'p': // 1 string to match.
if (NameR[9] != 's')
break;
return Intrinsic::xcore_getps; // "core.getps"
} }
break; break;
case 'e': // 2 strings to match. case 's': // 3 strings to match.
if (NameR.substr(10, 6) != "rmil2p") switch (NameR[6]) {
break;
switch (NameR[16]) {
default: break; default: break;
case 'd': // 1 string to match. case 'e': // 2 strings to match.
return Intrinsic::x86_xop_vpermil2pd; // "86.xop.vpermil2 if (NameR[7] != 't')
pd" break;
switch (NameR[8]) {
default: break;
case 'p': // 1 string to match.
if (NameR[9] != 's')
break;
return Intrinsic::xcore_setps; // "core.setps"
case 's': // 1 string to match.
if (NameR[9] != 'r')
break;
return Intrinsic::xcore_setsr; // "core.setsr"
}
break;
case 's': // 1 string to match. case 's': // 1 string to match.
return Intrinsic::x86_xop_vpermil2ps; // "86.xop.vpermil2 if (memcmp(NameR.data()+7, "ync", 3))
ps" break;
return Intrinsic::xcore_ssync; // "core.ssync"
} }
break; break;
case 'm': // 3 strings to match. }
if (NameR[10] != 'a') break;
}
break;
case 11: // 4 strings to match.
switch (NameR[0]) {
default: break;
case '8': // 3 strings to match.
if (memcmp(NameR.data()+1, "6.mmx.", 6))
break;
switch (NameR[7]) {
default: break;
case 'e': // 1 string to match.
if (memcmp(NameR.data()+8, "mms", 3))
break; break;
switch (NameR[11]) { return Intrinsic::x86_mmx_emms; // "86.mmx.emms"
case 'p': // 2 strings to match.
switch (NameR[8]) {
default: break; default: break;
case 'c': // 2 strings to match. case 'a': // 1 string to match.
if (NameR.substr(12, 4) != "ssdq") if (memcmp(NameR.data()+9, "nd", 2))
break; break;
switch (NameR[16]) { return Intrinsic::x86_mmx_pand; // "86.mmx.pand"
default: break; case 'x': // 1 string to match.
case 'h': // 1 string to match. if (memcmp(NameR.data()+9, "or", 2))
return Intrinsic::x86_xop_vpmacssdqh; // "86.xop.vpmacssd
qh"
case 'l': // 1 string to match.
return Intrinsic::x86_xop_vpmacssdql; // "86.xop.vpmacssd
ql"
}
break;
case 'd': // 1 string to match.
if (NameR.substr(12, 5) != "csswd")
break; break;
return Intrinsic::x86_xop_vpmadcsswd; // "86.xop.vpmadcss wd" return Intrinsic::x86_mmx_pxor; // "86.mmx.pxor"
} }
break; break;
} }
break; break;
case 'c': // 1 string to match.
if (memcmp(NameR.data()+1, "ore.bitrev", 10))
break;
return Intrinsic::xcore_bitrev; // "core.bitrev"
} }
break; break;
case 18: // 45 strings to match. case 12: // 6 strings to match.
if (NameR.substr(0, 3) != "86.") if (memcmp(NameR.data()+0, "86.", 3))
break; break;
switch (NameR[3]) { switch (NameR[3]) {
default: break; default: break;
case 'a': // 16 strings to match. case 'm': // 2 strings to match.
if (NameR.substr(4, 2) != "vx") if (memcmp(NameR.data()+4, "mx.", 3))
break; break;
switch (NameR[6]) { switch (NameR[7]) {
default: break; default: break;
case '.': // 10 strings to match. case 'f': // 1 string to match.
switch (NameR[7]) { if (memcmp(NameR.data()+8, "emms", 4))
default: break;
case 'h': // 4 strings to match.
switch (NameR[8]) {
default: break;
case 'a': // 2 strings to match.
if (NameR.substr(9, 4) != "dd.p")
break;
switch (NameR[13]) {
default: break;
case 'd': // 1 string to match.
if (NameR.substr(14, 4) != ".256")
break;
return Intrinsic::x86_avx_hadd_pd_256; // "86.avx.hadd.pd.
256"
case 's': // 1 string to match.
if (NameR.substr(14, 4) != ".256")
break;
return Intrinsic::x86_avx_hadd_ps_256; // "86.avx.hadd.ps.
256"
}
break;
case 's': // 2 strings to match.
if (NameR.substr(9, 4) != "ub.p")
break;
switch (NameR[13]) {
default: break;
case 'd': // 1 string to match.
if (NameR.substr(14, 4) != ".256")
break;
return Intrinsic::x86_avx_hsub_pd_256; // "86.avx.hsub.pd.
256"
case 's': // 1 string to match.
if (NameR.substr(14, 4) != ".256")
break;
return Intrinsic::x86_avx_hsub_ps_256; // "86.avx.hsub.ps.
256"
}
break;
}
break; break;
case 'm': // 2 strings to match. return Intrinsic::x86_mmx_femms; // "86.mmx.femms"
if (NameR.substr(8, 9) != "askload.p") case 'p': // 1 string to match.
break; if (memcmp(NameR.data()+8, "andn", 4))
switch (NameR[17]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::x86_avx_maskload_pd; // "86.avx.maskload
.pd"
case 's': // 1 string to match.
return Intrinsic::x86_avx_maskload_ps; // "86.avx.maskload
.ps"
}
break; break;
case 's': // 2 strings to match. return Intrinsic::x86_mmx_pandn; // "86.mmx.pandn"
if (NameR.substr(8, 5) != "qrt.p") }
break;
case 'p': // 1 string to match.
if (memcmp(NameR.data()+4, "clmulqdq", 8))
break;
return Intrinsic::x86_pclmulqdq; // "86.pclmulqdq"
case 'r': // 3 strings to match.
if (memcmp(NameR.data()+4, "drand.", 6))
break;
switch (NameR[10]) {
default: break;
case '1': // 1 string to match.
if (NameR[11] != '6')
break;
return Intrinsic::x86_rdrand_16; // "86.rdrand.16"
case '3': // 1 string to match.
if (NameR[11] != '2')
break;
return Intrinsic::x86_rdrand_32; // "86.rdrand.32"
case '6': // 1 string to match.
if (NameR[11] != '4')
break;
return Intrinsic::x86_rdrand_64; // "86.rdrand.64"
}
break;
}
break;
case 13: // 53 strings to match.
if (memcmp(NameR.data()+0, "86.", 3))
break;
switch (NameR[3]) {
default: break;
case 'a': // 1 string to match.
if (memcmp(NameR.data()+4, "vx2.permd", 9))
break;
return Intrinsic::x86_avx2_permd; // "86.avx2.permd"
case 'm': // 18 strings to match.
if (memcmp(NameR.data()+4, "mx.p", 4))
break;
switch (NameR[8]) {
default: break;
case 'a': // 6 strings to match.
switch (NameR[9]) {
default: break;
case 'd': // 4 strings to match.
if (memcmp(NameR.data()+10, "d.", 2))
break; break;
switch (NameR[13]) { switch (NameR[12]) {
default: break; default: break;
case 'b': // 1 string to match.
return Intrinsic::x86_mmx_padd_b; // "86.mmx.padd.b"
case 'd': // 1 string to match. case 'd': // 1 string to match.
if (NameR.substr(14, 4) != ".256") return Intrinsic::x86_mmx_padd_d; // "86.mmx.padd.d"
break; case 'q': // 1 string to match.
return Intrinsic::x86_avx_sqrt_pd_256; // "86.avx.sqrt.pd. return Intrinsic::x86_mmx_padd_q; // "86.mmx.padd.q"
256" case 'w': // 1 string to match.
case 's': // 1 string to match. return Intrinsic::x86_mmx_padd_w; // "86.mmx.padd.w"
if (NameR.substr(14, 4) != ".256")
break;
return Intrinsic::x86_avx_sqrt_ps_256; // "86.avx.sqrt.ps.
256"
} }
break; break;
case 'v': // 2 strings to match. case 'v': // 2 strings to match.
if (NameR.substr(8, 9) != "testnzc.p") if (memcmp(NameR.data()+10, "g.", 2))
break; break;
switch (NameR[17]) { switch (NameR[12]) {
default: break; default: break;
case 'd': // 1 string to match. case 'b': // 1 string to match.
return Intrinsic::x86_avx_vtestnzc_pd; // "86.avx.vtestnzc return Intrinsic::x86_mmx_pavg_b; // "86.mmx.pavg.b"
.pd" case 'w': // 1 string to match.
case 's': // 1 string to match. return Intrinsic::x86_mmx_pavg_w; // "86.mmx.pavg.w"
return Intrinsic::x86_avx_vtestnzc_ps; // "86.avx.vtestnzc
.ps"
} }
break; break;
} }
break; break;
case '2': // 6 strings to match. case 's': // 12 strings to match.
if (NameR[7] != '.') switch (NameR[9]) {
break;
switch (NameR[8]) {
default: break; default: break;
case 'm': // 2 strings to match. case 'l': // 3 strings to match.
if (NameR.substr(9, 8) != "askload.") if (memcmp(NameR.data()+10, "l.", 2))
break; break;
switch (NameR[17]) { switch (NameR[12]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
return Intrinsic::x86_avx2_maskload_d; // "86.avx2.maskloa d.d" return Intrinsic::x86_mmx_psll_d; // "86.mmx.psll.d"
case 'q': // 1 string to match. case 'q': // 1 string to match.
return Intrinsic::x86_avx2_maskload_q; // "86.avx2.maskloa return Intrinsic::x86_mmx_psll_q; // "86.mmx.psll.q"
d.q" case 'w': // 1 string to match.
return Intrinsic::x86_mmx_psll_w; // "86.mmx.psll.w"
} }
break; break;
case 'p': // 3 strings to match. case 'r': // 5 strings to match.
switch (NameR[9]) { switch (NameR[10]) {
default: break; default: break;
case 'm': // 1 string to match. case 'a': // 2 strings to match.
if (NameR.substr(10, 8) != "ul.hr.sw") if (NameR[11] != '.')
break; break;
return Intrinsic::x86_avx2_pmul_hr_sw; // "86.avx2.pmul.hr switch (NameR[12]) {
.sw"
case 's': // 2 strings to match.
switch (NameR[10]) {
default: break; default: break;
case 'l': // 1 string to match. case 'd': // 1 string to match.
if (NameR.substr(11, 7) != "l.dq.bs") return Intrinsic::x86_mmx_psra_d; // "86.mmx.psra.d"
break; case 'w': // 1 string to match.
return Intrinsic::x86_avx2_psll_dq_bs; // "86.avx2.psll.dq return Intrinsic::x86_mmx_psra_w; // "86.mmx.psra.w"
.bs" }
case 'r': // 1 string to match. break;
if (NameR.substr(11, 7) != "l.dq.bs") case 'l': // 3 strings to match.
break; if (NameR[11] != '.')
return Intrinsic::x86_avx2_psrl_dq_bs; // "86.avx2.psrl.dq break;
.bs" switch (NameR[12]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::x86_mmx_psrl_d; // "86.mmx.psrl.d"
case 'q': // 1 string to match.
return Intrinsic::x86_mmx_psrl_q; // "86.mmx.psrl.q"
case 'w': // 1 string to match.
return Intrinsic::x86_mmx_psrl_w; // "86.mmx.psrl.w"
} }
break; break;
} }
break; break;
case 'v': // 1 string to match. case 'u': // 4 strings to match.
if (NameR.substr(9, 9) != "perm2i128") if (memcmp(NameR.data()+10, "b.", 2))
break; break;
return Intrinsic::x86_avx2_vperm2i128; // "86.avx2.vperm2i switch (NameR[12]) {
128" default: break;
case 'b': // 1 string to match.
return Intrinsic::x86_mmx_psub_b; // "86.mmx.psub.b"
case 'd': // 1 string to match.
return Intrinsic::x86_mmx_psub_d; // "86.mmx.psub.d"
case 'q': // 1 string to match.
return Intrinsic::x86_mmx_psub_q; // "86.mmx.psub.q"
case 'w': // 1 string to match.
return Intrinsic::x86_mmx_psub_w; // "86.mmx.psub.w"
}
break;
} }
break; break;
} }
break; break;
case 'f': // 8 strings to match. case 's': // 16 strings to match.
if (NameR.substr(4, 8) != "ma4.vfnm") if (memcmp(NameR.data()+4, "se", 2))
break; break;
switch (NameR[12]) { switch (NameR[6]) {
default: break; default: break;
case 'a': // 4 strings to match. case '.': // 13 strings to match.
if (NameR.substr(13, 3) != "dd.") switch (NameR[7]) {
break;
switch (NameR[16]) {
default: break; default: break;
case 'p': // 2 strings to match. case 'a': // 1 string to match.
switch (NameR[17]) { if (memcmp(NameR.data()+8, "dd.ss", 5))
break;
return Intrinsic::x86_sse_add_ss; // "86.sse.add.ss"
case 'c': // 2 strings to match.
if (memcmp(NameR.data()+8, "mp.", 3))
break;
switch (NameR[11]) {
default: break; default: break;
case 'd': // 1 string to match. case 'p': // 1 string to match.
return Intrinsic::x86_fma4_vfnmadd_pd; // "86.fma4.vfnmadd if (NameR[12] != 's')
.pd" break;
return Intrinsic::x86_sse_cmp_ps; // "86.sse.cmp.ps"
case 's': // 1 string to match. case 's': // 1 string to match.
return Intrinsic::x86_fma4_vfnmadd_ps; // "86.fma4.vfnmadd if (NameR[12] != 's')
.ps" break;
return Intrinsic::x86_sse_cmp_ss; // "86.sse.cmp.ss"
} }
break; break;
case 's': // 2 strings to match. case 'd': // 1 string to match.
switch (NameR[17]) { if (memcmp(NameR.data()+8, "iv.ss", 5))
break;
return Intrinsic::x86_sse_div_ss; // "86.sse.div.ss"
case 'm': // 5 strings to match.
switch (NameR[8]) {
default: break; default: break;
case 'd': // 1 string to match. case 'a': // 2 strings to match.
return Intrinsic::x86_fma4_vfnmadd_sd; // "86.fma4.vfnmadd if (memcmp(NameR.data()+9, "x.", 2))
.sd" break;
case 's': // 1 string to match. switch (NameR[11]) {
return Intrinsic::x86_fma4_vfnmadd_ss; // "86.fma4.vfnmadd default: break;
.ss" case 'p': // 1 string to match.
if (NameR[12] != 's')
break;
return Intrinsic::x86_sse_max_ps; // "86.sse.max.ps"
case 's': // 1 string to match.
if (NameR[12] != 's')
break;
return Intrinsic::x86_sse_max_ss; // "86.sse.max.ss"
}
break;
case 'i': // 2 strings to match.
if (memcmp(NameR.data()+9, "n.", 2))
break;
switch (NameR[11]) {
default: break;
case 'p': // 1 string to match.
if (NameR[12] != 's')
break;
return Intrinsic::x86_sse_min_ps; // "86.sse.min.ps"
case 's': // 1 string to match.
if (NameR[12] != 's')
break;
return Intrinsic::x86_sse_min_ss; // "86.sse.min.ss"
}
break;
case 'u': // 1 string to match.
if (memcmp(NameR.data()+9, "l.ss", 4))
break;
return Intrinsic::x86_sse_mul_ss; // "86.sse.mul.ss"
} }
break; break;
} case 'r': // 2 strings to match.
break; if (memcmp(NameR.data()+8, "cp.", 3))
case 's': // 4 strings to match. break;
if (NameR.substr(13, 3) != "ub.") switch (NameR[11]) {
break;
switch (NameR[16]) {
default: break;
case 'p': // 2 strings to match.
switch (NameR[17]) {
default: break; default: break;
case 'd': // 1 string to match. case 'p': // 1 string to match.
return Intrinsic::x86_fma4_vfnmsub_pd; // "86.fma4.vfnmsub if (NameR[12] != 's')
.pd" break;
return Intrinsic::x86_sse_rcp_ps; // "86.sse.rcp.ps"
case 's': // 1 string to match. case 's': // 1 string to match.
return Intrinsic::x86_fma4_vfnmsub_ps; // "86.fma4.vfnmsub if (NameR[12] != 's')
.ps" break;
return Intrinsic::x86_sse_rcp_ss; // "86.sse.rcp.ss"
} }
break; break;
case 's': // 2 strings to match. case 's': // 2 strings to match.
switch (NameR[17]) { switch (NameR[8]) {
default: break; default: break;
case 'd': // 1 string to match. case 'f': // 1 string to match.
return Intrinsic::x86_fma4_vfnmsub_sd; // "86.fma4.vfnmsub if (memcmp(NameR.data()+9, "ence", 4))
.sd" break;
case 's': // 1 string to match. return Intrinsic::x86_sse_sfence; // "86.sse.sfence"
return Intrinsic::x86_fma4_vfnmsub_ss; // "86.fma4.vfnmsub case 'u': // 1 string to match.
.ss" if (memcmp(NameR.data()+9, "b.ss", 4))
break;
return Intrinsic::x86_sse_sub_ss; // "86.sse.sub.ss"
} }
break; break;
} }
break; break;
} case '3': // 1 string to match.
break; if (memcmp(NameR.data()+7, ".mwait", 6))
case 's': // 13 strings to match. break;
if (NameR.substr(4, 2) != "se") return Intrinsic::x86_sse3_mwait; // "86.sse3.mwait"
break; case '4': // 2 strings to match.
switch (NameR[6]) { if (memcmp(NameR.data()+7, "1.dpp", 5))
default: break; break;
case '.': // 2 strings to match. switch (NameR[12]) {
switch (NameR[7]) {
default: break; default: break;
case 'c': // 1 string to match. case 'd': // 1 string to match.
if (NameR.substr(8, 10) != "vttss2si64") return Intrinsic::x86_sse41_dppd; // "86.sse41.dppd"
break; case 's': // 1 string to match.
return Intrinsic::x86_sse_cvttss2si64; // "86.sse.cvttss2s return Intrinsic::x86_sse41_dpps; // "86.sse41.dpps"
i64"
case 'u': // 1 string to match.
if (NameR.substr(8, 10) != "comineq.ss")
break;
return Intrinsic::x86_sse_ucomineq_ss; // "86.sse.ucomineq
.ss"
} }
break; break;
case '2': // 10 strings to match. }
if (NameR[7] != '.') break;
break; case 'x': // 18 strings to match.
switch (NameR[8]) { if (memcmp(NameR.data()+4, "op.vp", 5))
break;
switch (NameR[9]) {
default: break;
case 'c': // 5 strings to match.
switch (NameR[10]) {
default: break; default: break;
case 'c': // 3 strings to match. case 'm': // 1 string to match.
switch (NameR[9]) { if (memcmp(NameR.data()+11, "ov", 2))
default: break;
case 'o': // 1 string to match.
if (NameR.substr(10, 8) != "mineq.sd")
break;
return Intrinsic::x86_sse2_comineq_sd; // "86.sse2.comineq
.sd"
case 'v': // 2 strings to match.
if (NameR.substr(10, 2) != "ts")
break;
switch (NameR[12]) {
default: break;
case 'd': // 1 string to match.
if (NameR.substr(13, 5) != "2si64")
break;
return Intrinsic::x86_sse2_cvtsd2si64; // "86.sse2.cvtsd2s
i64"
case 'i': // 1 string to match.
if (NameR.substr(13, 5) != "642sd")
break;
return Intrinsic::x86_sse2_cvtsi642sd; // "86.sse2.cvtsi64
2sd"
}
break;
}
break;
case 'p': // 2 strings to match.
if (NameR[9] != 's')
break; break;
switch (NameR[10]) { return Intrinsic::x86_xop_vpcmov; // "86.xop.vpcmov"
default: break; case 'o': // 4 strings to match.
case 'l': // 1 string to match. if (NameR[11] != 'm')
if (NameR.substr(11, 7) != "l.dq.bs")
break;
return Intrinsic::x86_sse2_psll_dq_bs; // "86.sse2.psll.dq
.bs"
case 'r': // 1 string to match.
if (NameR.substr(11, 7) != "l.dq.bs")
break;
return Intrinsic::x86_sse2_psrl_dq_bs; // "86.sse2.psrl.dq
.bs"
}
break;
case 'u': // 5 strings to match.
if (NameR.substr(9, 4) != "comi")
break; break;
switch (NameR[13]) { switch (NameR[12]) {
default: break; default: break;
case 'e': // 1 string to match. case 'b': // 1 string to match.
if (NameR.substr(14, 4) != "q.sd") return Intrinsic::x86_xop_vpcomb; // "86.xop.vpcomb"
break; case 'd': // 1 string to match.
return Intrinsic::x86_sse2_ucomieq_sd; // "86.sse2.ucomieq return Intrinsic::x86_xop_vpcomd; // "86.xop.vpcomd"
.sd" case 'q': // 1 string to match.
case 'g': // 2 strings to match. return Intrinsic::x86_xop_vpcomq; // "86.xop.vpcomq"
switch (NameR[14]) { case 'w': // 1 string to match.
default: break; return Intrinsic::x86_xop_vpcomw; // "86.xop.vpcomw"
case 'e': // 1 string to match.
if (NameR.substr(15, 3) != ".sd")
break;
return Intrinsic::x86_sse2_ucomige_sd; // "86.sse2.ucomige
.sd"
case 't': // 1 string to match.
if (NameR.substr(15, 3) != ".sd")
break;
return Intrinsic::x86_sse2_ucomigt_sd; // "86.sse2.ucomigt
.sd"
}
break;
case 'l': // 2 strings to match.
switch (NameR[14]) {
default: break;
case 'e': // 1 string to match.
if (NameR.substr(15, 3) != ".sd")
break;
return Intrinsic::x86_sse2_ucomile_sd; // "86.sse2.ucomile
.sd"
case 't': // 1 string to match.
if (NameR.substr(15, 3) != ".sd")
break;
return Intrinsic::x86_sse2_ucomilt_sd; // "86.sse2.ucomilt
.sd"
}
break;
} }
break; break;
} }
break; break;
case '4': // 1 string to match. case 'p': // 1 string to match.
if (NameR.substr(7, 11) != "1.extractps") if (memcmp(NameR.data()+10, "erm", 3))
break; break;
return Intrinsic::x86_sse41_extractps; // "86.sse41.extrac return Intrinsic::x86_xop_vpperm; // "86.xop.vpperm"
tps" case 'r': // 4 strings to match.
} if (memcmp(NameR.data()+10, "ot", 2))
break;
case 'x': // 8 strings to match.
if (NameR.substr(4, 8) != "op.vpcom")
break;
switch (NameR[12]) {
default: break;
case 'f': // 4 strings to match.
if (NameR.substr(13, 4) != "alse")
break; break;
switch (NameR[17]) { switch (NameR[12]) {
default: break; default: break;
case 'b': // 1 string to match. case 'b': // 1 string to match.
return Intrinsic::x86_xop_vpcomfalseb; // "86.xop.vpcomfal seb" return Intrinsic::x86_xop_vprotb; // "86.xop.vprotb"
case 'd': // 1 string to match. case 'd': // 1 string to match.
return Intrinsic::x86_xop_vpcomfalsed; // "86.xop.vpcomfal sed" return Intrinsic::x86_xop_vprotd; // "86.xop.vprotd"
case 'q': // 1 string to match. case 'q': // 1 string to match.
return Intrinsic::x86_xop_vpcomfalseq; // "86.xop.vpcomfal seq" return Intrinsic::x86_xop_vprotq; // "86.xop.vprotq"
case 'w': // 1 string to match. case 'w': // 1 string to match.
return Intrinsic::x86_xop_vpcomfalsew; // "86.xop.vpcomfal sew" return Intrinsic::x86_xop_vprotw; // "86.xop.vprotw"
} }
break; break;
case 't': // 4 strings to match. case 's': // 8 strings to match.
if (NameR.substr(13, 4) != "rueu") if (NameR[10] != 'h')
break; break;
switch (NameR[17]) { switch (NameR[11]) {
default: break; default: break;
case 'b': // 1 string to match. case 'a': // 4 strings to match.
return Intrinsic::x86_xop_vpcomtrueub; // "86.xop.vpcomtru switch (NameR[12]) {
eub" default: break;
case 'd': // 1 string to match. case 'b': // 1 string to match.
return Intrinsic::x86_xop_vpcomtrueud; // "86.xop.vpcomtru return Intrinsic::x86_xop_vpshab; // "86.xop.vpshab"
eud" case 'd': // 1 string to match.
case 'q': // 1 string to match. return Intrinsic::x86_xop_vpshad; // "86.xop.vpshad"
return Intrinsic::x86_xop_vpcomtrueuq; // "86.xop.vpcomtru case 'q': // 1 string to match.
euq" return Intrinsic::x86_xop_vpshaq; // "86.xop.vpshaq"
case 'w': // 1 string to match. case 'w': // 1 string to match.
return Intrinsic::x86_xop_vpcomtrueuw; // "86.xop.vpcomtru return Intrinsic::x86_xop_vpshaw; // "86.xop.vpshaw"
euw" }
break;
case 'l': // 4 strings to match.
switch (NameR[12]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::x86_xop_vpshlb; // "86.xop.vpshlb"
case 'd': // 1 string to match.
return Intrinsic::x86_xop_vpshld; // "86.xop.vpshld"
case 'q': // 1 string to match.
return Intrinsic::x86_xop_vpshlq; // "86.xop.vpshlq"
case 'w': // 1 string to match.
return Intrinsic::x86_xop_vpshlw; // "86.xop.vpshlw"
}
break;
} }
break; break;
} }
break; break;
} }
break; break;
case 19: // 40 strings to match. case 14: // 96 strings to match.
if (NameR.substr(0, 3) != "86.") switch (NameR[0]) {
break;
switch (NameR[3]) {
default: break; default: break;
case 'a': // 24 strings to match. case '8': // 95 strings to match.
switch (NameR[4]) { if (memcmp(NameR.data()+1, "6.", 2))
default: break;
case 'e': // 2 strings to match.
if (NameR.substr(5, 7) != "sni.aes")
break;
switch (NameR[12]) {
default: break;
case 'd': // 1 string to match.
if (NameR.substr(13, 6) != "eclast")
break;
return Intrinsic::x86_aesni_aesdeclast; // "86.aesni.aesdec
last"
case 'e': // 1 string to match.
if (NameR.substr(13, 6) != "nclast")
break;
return Intrinsic::x86_aesni_aesenclast; // "86.aesni.aesenc
last"
}
break; break;
case 'v': // 22 strings to match. switch (NameR[3]) {
if (NameR[5] != 'x') default: break;
case '3': // 9 strings to match.
if (memcmp(NameR.data()+4, "dnow.p", 6))
break; break;
switch (NameR[6]) { switch (NameR[10]) {
default: break; default: break;
case '.': // 11 strings to match. case 'f': // 8 strings to match.
switch (NameR[7]) { switch (NameR[11]) {
default: break; default: break;
case 'b': // 2 strings to match. case '2': // 1 string to match.
if (NameR.substr(8, 6) != "lend.p") if (memcmp(NameR.data()+12, "id", 2))
break; break;
switch (NameR[14]) { return Intrinsic::x86_3dnow_pf2id; // "86.3dnow.pf2id"
case 'a': // 2 strings to match.
switch (NameR[12]) {
default: break; default: break;
case 'd': // 1 string to match. case 'c': // 1 string to match.
if (NameR.substr(15, 4) != ".256") if (NameR[13] != 'c')
break; break;
return Intrinsic::x86_avx_blend_pd_256; // "86.avx. return Intrinsic::x86_3dnow_pfacc; // "86.3dnow.pfacc"
blend.pd.256" case 'd': // 1 string to match.
case 's': // 1 string to match. if (NameR[13] != 'd')
if (NameR.substr(15, 4) != ".256")
break; break;
return Intrinsic::x86_avx_blend_ps_256; // "86.avx. blend.ps.256" return Intrinsic::x86_3dnow_pfadd; // "86.3dnow.pfadd"
} }
break; break;
case 'm': // 5 strings to match. case 'm': // 3 strings to match.
switch (NameR[8]) { switch (NameR[12]) {
default: break; default: break;
case 'a': // 2 strings to match. case 'a': // 1 string to match.
if (NameR.substr(9, 9) != "skstore.p") if (NameR[13] != 'x')
break; break;
switch (NameR[18]) { return Intrinsic::x86_3dnow_pfmax; // "86.3dnow.pfmax"
default: break; case 'i': // 1 string to match.
case 'd': // 1 string to match. if (NameR[13] != 'n')
return Intrinsic::x86_avx_maskstore_pd; // "86.avx.
maskstore.pd"
case 's': // 1 string to match.
return Intrinsic::x86_avx_maskstore_ps; // "86.avx.
maskstore.ps"
}
break;
case 'o': // 3 strings to match.
if (NameR.substr(9, 4) != "vnt.")
break; break;
switch (NameR[13]) { return Intrinsic::x86_3dnow_pfmin; // "86.3dnow.pfmin"
default: break; case 'u': // 1 string to match.
case 'd': // 1 string to match. if (NameR[13] != 'l')
if (NameR.substr(14, 5) != "q.256")
break;
return Intrinsic::x86_avx_movnt_dq_256; // "86.avx.
movnt.dq.256"
case 'p': // 2 strings to match.
switch (NameR[14]) {
default: break;
case 'd': // 1 string to match.
if (NameR.substr(15, 4) != ".256")
break;
return Intrinsic::x86_avx_movnt_pd_256; // "86.avx.
movnt.pd.256"
case 's': // 1 string to match.
if (NameR.substr(15, 4) != ".256")
break;
return Intrinsic::x86_avx_movnt_ps_256; // "86.avx.
movnt.ps.256"
}
break; break;
} return Intrinsic::x86_3dnow_pfmul; // "86.3dnow.pfmul"
break;
} }
break; break;
case 'p': // 1 string to match. case 'r': // 1 string to match.
if (NameR.substr(8, 11) != "testnzc.256") if (memcmp(NameR.data()+12, "cp", 2))
break; break;
return Intrinsic::x86_avx_ptestnzc_256; // "86.avx.ptestnzc return Intrinsic::x86_3dnow_pfrcp; // "86.3dnow.pfrcp"
.256" case 's': // 1 string to match.
case 'r': // 3 strings to match. if (memcmp(NameR.data()+12, "ub", 2))
switch (NameR[8]) {
default: break;
case 'o': // 2 strings to match.
if (NameR.substr(9, 5) != "und.p")
break;
switch (NameR[14]) {
default: break;
case 'd': // 1 string to match.
if (NameR.substr(15, 4) != ".256")
break;
return Intrinsic::x86_avx_round_pd_256; // "86.avx.
round.pd.256"
case 's': // 1 string to match.
if (NameR.substr(15, 4) != ".256")
break;
return Intrinsic::x86_avx_round_ps_256; // "86.avx.
round.ps.256"
}
break; break;
case 's': // 1 string to match. return Intrinsic::x86_3dnow_pfsub; // "86.3dnow.pfsub"
if (NameR.substr(9, 10) != "qrt.ps.256")
break;
return Intrinsic::x86_avx_rsqrt_ps_256; // "86.avx.
rsqrt.ps.256"
}
break;
} }
break; break;
case '2': // 11 strings to match. case 'i': // 1 string to match.
if (NameR[7] != '.') if (memcmp(NameR.data()+11, "2fd", 3))
break; break;
switch (NameR[8]) { return Intrinsic::x86_3dnow_pi2fd; // "86.3dnow.pi2fd"
default: break; }
case 'm': // 2 strings to match. break;
if (NameR.substr(9, 9) != "askstore.") case 'a': // 14 strings to match.
if (memcmp(NameR.data()+4, "vx2.p", 5))
break;
switch (NameR[9]) {
default: break;
case 'a': // 5 strings to match.
switch (NameR[10]) {
default: break;
case 'b': // 3 strings to match.
if (memcmp(NameR.data()+11, "s.", 2))
break; break;
switch (NameR[18]) { switch (NameR[13]) {
default: break; default: break;
case 'b': // 1 string to match.
return Intrinsic::x86_avx2_pabs_b; // "86.avx2.pabs.b"
case 'd': // 1 string to match. case 'd': // 1 string to match.
return Intrinsic::x86_avx2_maskstore_d; // "86.avx2 return Intrinsic::x86_avx2_pabs_d; // "86.avx2.pabs.d"
.maskstore.d" case 'w': // 1 string to match.
return Intrinsic::x86_avx2_pabs_w; // "86.avx2.pabs.w"
}
break;
case 'v': // 2 strings to match.
if (memcmp(NameR.data()+11, "g.", 2))
break;
switch (NameR[13]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::x86_avx2_pavg_b; // "86.avx2.pavg.b"
case 'w': // 1 string to match.
return Intrinsic::x86_avx2_pavg_w; // "86.avx2.pavg.w"
}
break;
}
break;
case 'e': // 1 string to match.
if (memcmp(NameR.data()+10, "rmps", 4))
break;
return Intrinsic::x86_avx2_permps; // "86.avx2.permps"
case 's': // 8 strings to match.
switch (NameR[10]) {
default: break;
case 'l': // 3 strings to match.
if (memcmp(NameR.data()+11, "l.", 2))
break;
switch (NameR[13]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::x86_avx2_psll_d; // "86.avx2.psll.d"
case 'q': // 1 string to match. case 'q': // 1 string to match.
return Intrinsic::x86_avx2_maskstore_q; // "86.avx2 return Intrinsic::x86_avx2_psll_q; // "86.avx2.psll.q"
.maskstore.q" case 'w': // 1 string to match.
return Intrinsic::x86_avx2_psll_w; // "86.avx2.psll.w"
} }
break; break;
case 'p': // 8 strings to match. case 'r': // 5 strings to match.
switch (NameR[9]) { switch (NameR[11]) {
default: break; default: break;
case 'b': // 2 strings to match. case 'a': // 2 strings to match.
if (NameR.substr(10, 6) != "lendd.") if (NameR[12] != '.')
break; break;
switch (NameR[16]) { switch (NameR[13]) {
default: break; default: break;
case '1': // 1 string to match. case 'd': // 1 string to match.
if (NameR.substr(17, 2) != "28") return Intrinsic::x86_avx2_psra_d; // "86.avx2.psra.d"
break; case 'w': // 1 string to match.
return Intrinsic::x86_avx2_pblendd_128; // "86.avx2 return Intrinsic::x86_avx2_psra_w; // "86.avx2.psra.w"
.pblendd.128"
case '2': // 1 string to match.
if (NameR.substr(17, 2) != "56")
break;
return Intrinsic::x86_avx2_pblendd_256; // "86.avx2
.pblendd.256"
} }
break; break;
case 'm': // 1 string to match. case 'l': // 3 strings to match.
if (NameR.substr(10, 9) != "add.ub.sw") if (NameR[12] != '.')
break; break;
return Intrinsic::x86_avx2_pmadd_ub_sw; // "86.avx2 switch (NameR[13]) {
.pmadd.ub.sw"
case 's': // 5 strings to match.
switch (NameR[10]) {
default: break; default: break;
case 'l': // 2 strings to match. case 'd': // 1 string to match.
if (NameR.substr(11, 3) != "lv.") return Intrinsic::x86_avx2_psrl_d; // "86.avx2.psrl.d"
break; case 'q': // 1 string to match.
switch (NameR[14]) { return Intrinsic::x86_avx2_psrl_q; // "86.avx2.psrl.q"
default: break; case 'w': // 1 string to match.
case 'd': // 1 string to match. return Intrinsic::x86_avx2_psrl_w; // "86.avx2.psrl.w"
if (NameR.substr(15, 4) != ".256")
break;
return Intrinsic::x86_avx2_psllv_d_256; // "86.avx2
.psllv.d.256"
case 'q': // 1 string to match.
if (NameR.substr(15, 4) != ".256")
break;
return Intrinsic::x86_avx2_psllv_q_256; // "86.avx2
.psllv.q.256"
}
break;
case 'r': // 3 strings to match.
switch (NameR[11]) {
default: break;
case 'a': // 1 string to match.
if (NameR.substr(12, 7) != "v.d.256")
break;
return Intrinsic::x86_avx2_psrav_d_256; // "86.avx2
.psrav.d.256"
case 'l': // 2 strings to match.
if (NameR.substr(12, 2) != "v.")
break;
switch (NameR[14]) {
default: break;
case 'd': // 1 string to match.
if (NameR.substr(15, 4) != ".256")
break;
return Intrinsic::x86_avx2_psrlv_d_256; // "86.avx2
.psrlv.d.256"
case 'q': // 1 string to match.
if (NameR.substr(15, 4) != ".256")
break;
return Intrinsic::x86_avx2_psrlv_q_256; // "86.avx2
.psrlv.q.256"
}
break;
}
break;
} }
break; break;
} }
break; break;
case 'v': // 1 string to match.
if (NameR.substr(9, 10) != "inserti128")
break;
return Intrinsic::x86_avx2_vinserti128; // "86.avx2.vinsert
i128"
} }
break; break;
} }
break; break;
} case 'b': // 6 strings to match.
break; if (memcmp(NameR.data()+4, "mi.", 3))
case 's': // 10 strings to match. break;
if (NameR[4] != 's') switch (NameR[7]) {
break;
switch (NameR[5]) {
default: break;
case 'e': // 6 strings to match.
switch (NameR[6]) {
default: break; default: break;
case '2': // 3 strings to match. case 'b': // 2 strings to match.
if (NameR[7] != '.') if (memcmp(NameR.data()+8, "zhi.", 4))
break; break;
switch (NameR[8]) { switch (NameR[12]) {
default: break; default: break;
case 'c': // 1 string to match. case '3': // 1 string to match.
if (NameR.substr(9, 10) != "vttsd2si64") if (NameR[13] != '2')
break;
return Intrinsic::x86_sse2_cvttsd2si64; // "86.sse2.cvttsd2
si64"
case 'm': // 1 string to match.
if (NameR.substr(9, 10) != "askmov.dqu")
break; break;
return Intrinsic::x86_sse2_maskmov_dqu; // "86.sse2.maskmov return Intrinsic::x86_bmi_bzhi_32; // "86.bmi.bzhi.32"
.dqu" case '6': // 1 string to match.
case 'u': // 1 string to match. if (NameR[13] != '4')
if (NameR.substr(9, 10) != "comineq.sd")
break; break;
return Intrinsic::x86_sse2_ucomineq_sd; // "86.sse2.ucomine q.sd" return Intrinsic::x86_bmi_bzhi_64; // "86.bmi.bzhi.64"
} }
break; break;
case '4': // 3 strings to match. case 'p': // 4 strings to match.
switch (NameR[7]) { switch (NameR[8]) {
default: break; default: break;
case '1': // 1 string to match. case 'd': // 2 strings to match.
if (NameR.substr(8, 11) != ".phminposuw") if (memcmp(NameR.data()+9, "ep.", 3))
break; break;
return Intrinsic::x86_sse41_phminposuw; // "86.sse41.phminp switch (NameR[12]) {
osuw" default: break;
case '2': // 2 strings to match. case '3': // 1 string to match.
if (NameR.substr(8, 7) != ".crc32.") if (NameR[13] != '2')
break;
return Intrinsic::x86_bmi_pdep_32; // "86.bmi.pdep.32"
case '6': // 1 string to match.
if (NameR[13] != '4')
break;
return Intrinsic::x86_bmi_pdep_64; // "86.bmi.pdep.64"
}
break;
case 'e': // 2 strings to match.
if (memcmp(NameR.data()+9, "xt.", 3))
break; break;
switch (NameR[15]) { switch (NameR[12]) {
default: break; default: break;
case '3': // 1 string to match. case '3': // 1 string to match.
if (NameR.substr(16, 3) != "2.8") if (NameR[13] != '2')
break; break;
return Intrinsic::x86_sse42_crc32_32_8; // "86.sse4 2.crc32.32.8" return Intrinsic::x86_bmi_pext_32; // "86.bmi.pext.32"
case '6': // 1 string to match. case '6': // 1 string to match.
if (NameR.substr(16, 3) != "4.8") if (NameR[13] != '4')
break; break;
return Intrinsic::x86_sse42_crc32_64_8; // "86.sse4 2.crc32.64.8" return Intrinsic::x86_bmi_pext_64; // "86.bmi.pext.64"
} }
break; break;
} }
break; break;
} }
break; break;
case 's': // 4 strings to match. case 'm': // 21 strings to match.
if (NameR.substr(6, 4) != "e3.p") if (memcmp(NameR.data()+4, "mx.p", 4))
break; break;
switch (NameR[10]) { switch (NameR[8]) {
default: break; default: break;
case 'a': // 3 strings to match. case 'a': // 2 strings to match.
if (NameR.substr(11, 3) != "bs.") if (memcmp(NameR.data()+9, "dds.", 4))
break; break;
switch (NameR[14]) { switch (NameR[13]) {
default: break; default: break;
case 'b': // 1 string to match. case 'b': // 1 string to match.
if (NameR.substr(15, 4) != ".128") return Intrinsic::x86_mmx_padds_b; // "86.mmx.padds.b"
break;
return Intrinsic::x86_ssse3_pabs_b_128; // "86.ssse3.pabs.b
.128"
case 'd': // 1 string to match.
if (NameR.substr(15, 4) != ".128")
break;
return Intrinsic::x86_ssse3_pabs_d_128; // "86.ssse3.pabs.d
.128"
case 'w': // 1 string to match. case 'w': // 1 string to match.
if (NameR.substr(15, 4) != ".128") return Intrinsic::x86_mmx_padds_w; // "86.mmx.padds.w"
break;
return Intrinsic::x86_ssse3_pabs_w_128; // "86.ssse3.pabs.w
.128"
} }
break; break;
case 'm': // 1 string to match. case 'e': // 1 string to match.
if (NameR.substr(11, 8) != "ul.hr.sw") if (memcmp(NameR.data()+9, "xtr.w", 5))
break;
return Intrinsic::x86_ssse3_pmul_hr_sw; // "86.ssse3.pmul.h
r.sw"
}
break;
}
break;
case 'x': // 6 strings to match.
if (NameR.substr(4, 4) != "op.v")
break;
switch (NameR[8]) {
default: break;
case 'f': // 2 strings to match.
if (NameR.substr(9, 5) != "rcz.p")
break;
switch (NameR[14]) {
default: break;
case 'd': // 1 string to match.
if (NameR.substr(15, 4) != ".256")
break;
return Intrinsic::x86_xop_vfrcz_pd_256; // "86.xop.vfrcz.pd
.256"
case 's': // 1 string to match.
if (NameR.substr(15, 4) != ".256")
break; break;
return Intrinsic::x86_xop_vfrcz_ps_256; // "86.xop.vfrcz.ps return Intrinsic::x86_mmx_pextr_w; // "86.mmx.pextr.w"
.256" case 'i': // 1 string to match.
} if (memcmp(NameR.data()+9, "nsr.w", 5))
break;
case 'p': // 4 strings to match.
if (NameR.substr(9, 9) != "comfalseu")
break;
switch (NameR[18]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::x86_xop_vpcomfalseub; // "86.xop.vpcomfal
seub"
case 'd': // 1 string to match.
return Intrinsic::x86_xop_vpcomfalseud; // "86.xop.vpcomfal
seud"
case 'q': // 1 string to match.
return Intrinsic::x86_xop_vpcomfalseuq; // "86.xop.vpcomfal
seuq"
case 'w': // 1 string to match.
return Intrinsic::x86_xop_vpcomfalseuw; // "86.xop.vpcomfal
seuw"
}
break;
}
break;
}
break;
case 20: // 41 strings to match.
if (NameR.substr(0, 3) != "86.")
break;
switch (NameR[3]) {
default: break;
case 'a': // 21 strings to match.
if (NameR.substr(4, 2) != "vx")
break;
switch (NameR[6]) {
default: break;
case '.': // 20 strings to match.
switch (NameR[7]) {
default: break;
case 'a': // 2 strings to match.
if (NameR.substr(8, 7) != "ddsub.p")
break; break;
switch (NameR[15]) { return Intrinsic::x86_mmx_pinsr_w; // "86.mmx.pinsr.w"
case 'm': // 6 strings to match.
switch (NameR[9]) {
default: break; default: break;
case 'd': // 1 string to match. case 'a': // 2 strings to match.
if (NameR.substr(16, 4) != ".256") if (NameR[10] != 'x')
break;
return Intrinsic::x86_avx_addsub_pd_256; // "86.avx.addsub.p
d.256"
case 's': // 1 string to match.
if (NameR.substr(16, 4) != ".256")
break; break;
return Intrinsic::x86_avx_addsub_ps_256; // "86.avx.addsub.p switch (NameR[11]) {
s.256"
}
break;
case 'b': // 2 strings to match.
if (NameR.substr(8, 7) != "lendv.p")
break;
switch (NameR[15]) {
default: break;
case 'd': // 1 string to match.
if (NameR.substr(16, 4) != ".256")
break;
return Intrinsic::x86_avx_blendv_pd_256; // "86.avx.blendv.p
d.256"
case 's': // 1 string to match.
if (NameR.substr(16, 4) != ".256")
break;
return Intrinsic::x86_avx_blendv_ps_256; // "86.avx.blendv.p
s.256"
}
break;
case 'c': // 4 strings to match.
if (NameR.substr(8, 2) != "vt")
break;
switch (NameR[10]) {
default: break;
case '.': // 2 strings to match.
if (NameR[11] != 'p')
break;
switch (NameR[12]) {
default: break; default: break;
case 'd': // 1 string to match.
if (NameR.substr(13, 7) != "2dq.256")
break;
return Intrinsic::x86_avx_cvt_pd2dq_256; // "86.avx.
cvt.pd2dq.256"
case 's': // 1 string to match. case 's': // 1 string to match.
if (NameR.substr(13, 7) != "2dq.256") if (memcmp(NameR.data()+12, ".w", 2))
break; break;
return Intrinsic::x86_avx_cvt_ps2dq_256; // "86.avx. return Intrinsic::x86_mmx_pmaxs_w; // "86.mmx.pmaxs.w"
cvt.ps2dq.256" case 'u': // 1 string to match.
if (memcmp(NameR.data()+12, ".b", 2))
break;
return Intrinsic::x86_mmx_pmaxu_b; // "86.mmx.pmaxu.b"
} }
break; break;
case 'd': // 2 strings to match. case 'i': // 2 strings to match.
if (NameR.substr(11, 4) != "q2.p") if (NameR[10] != 'n')
break; break;
switch (NameR[15]) { switch (NameR[11]) {
default: break; default: break;
case 'd': // 1 string to match.
if (NameR.substr(16, 4) != ".256")
break;
return Intrinsic::x86_avx_cvtdq2_pd_256; // "86.avx.
cvtdq2.pd.256"
case 's': // 1 string to match. case 's': // 1 string to match.
if (NameR.substr(16, 4) != ".256") if (memcmp(NameR.data()+12, ".w", 2))
break; break;
return Intrinsic::x86_avx_cvtdq2_ps_256; // "86.avx. return Intrinsic::x86_mmx_pmins_w; // "86.mmx.pmins.w"
cvtdq2.ps.256" case 'u': // 1 string to match.
if (memcmp(NameR.data()+12, ".b", 2))
break;
return Intrinsic::x86_mmx_pminu_b; // "86.mmx.pminu.b"
} }
break; break;
} case 'u': // 2 strings to match.
break; if (NameR[10] != 'l')
case 'm': // 2 strings to match.
if (NameR.substr(8, 7) != "ovmsk.p")
break;
switch (NameR[15]) {
default: break;
case 'd': // 1 string to match.
if (NameR.substr(16, 4) != ".256")
break;
return Intrinsic::x86_avx_movmsk_pd_256; // "86.avx.movmsk.p
d.256"
case 's': // 1 string to match.
if (NameR.substr(16, 4) != ".256")
break;
return Intrinsic::x86_avx_movmsk_ps_256; // "86.avx.movmsk.p
s.256"
}
break;
case 's': // 3 strings to match.
if (NameR.substr(8, 6) != "toreu.")
break;
switch (NameR[14]) {
default: break;
case 'd': // 1 string to match.
if (NameR.substr(15, 5) != "q.256")
break; break;
return Intrinsic::x86_avx_storeu_dq_256; // "86.avx.storeu.d switch (NameR[11]) {
q.256"
case 'p': // 2 strings to match.
switch (NameR[15]) {
default: break; default: break;
case 'd': // 1 string to match. case 'h': // 1 string to match.
if (NameR.substr(16, 4) != ".256") if (memcmp(NameR.data()+12, ".w", 2))
break; break;
return Intrinsic::x86_avx_storeu_pd_256; // "86.avx. return Intrinsic::x86_mmx_pmulh_w; // "86.mmx.pmulh.w"
storeu.pd.256" case 'l': // 1 string to match.
case 's': // 1 string to match. if (memcmp(NameR.data()+12, ".w", 2))
if (NameR.substr(16, 4) != ".256")
break; break;
return Intrinsic::x86_avx_storeu_ps_256; // "86.avx. storeu.ps.256" return Intrinsic::x86_mmx_pmull_w; // "86.mmx.pmull.w"
} }
break; break;
} }
break; break;
case 'v': // 7 strings to match. case 's': // 11 strings to match.
switch (NameR[8]) { switch (NameR[9]) {
default: break; default: break;
case 'b': // 1 string to match. case 'a': // 1 string to match.
if (NameR.substr(9, 11) != "roadcast.ss") if (memcmp(NameR.data()+10, "d.bw", 4))
break; break;
return Intrinsic::x86_avx_vbroadcast_ss; // "86.avx.vbroadca return Intrinsic::x86_mmx_psad_bw; // "86.mmx.psad.bw"
st.ss" case 'l': // 3 strings to match.
case 'p': // 2 strings to match. if (memcmp(NameR.data()+10, "li.", 3))
if (NameR.substr(9, 10) != "ermilvar.p")
break; break;
switch (NameR[19]) { switch (NameR[13]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
return Intrinsic::x86_avx_vpermilvar_pd; // "86.avx. return Intrinsic::x86_mmx_pslli_d; // "86.mmx.pslli.d"
vpermilvar.pd" case 'q': // 1 string to match.
case 's': // 1 string to match. return Intrinsic::x86_mmx_pslli_q; // "86.mmx.pslli.q"
return Intrinsic::x86_avx_vpermilvar_ps; // "86.avx. case 'w': // 1 string to match.
vpermilvar.ps" return Intrinsic::x86_mmx_pslli_w; // "86.mmx.pslli.w"
} }
break; break;
case 't': // 4 strings to match. case 'r': // 5 strings to match.
if (NameR.substr(9, 3) != "est") switch (NameR[10]) {
break;
switch (NameR[12]) {
default: break; default: break;
case 'c': // 2 strings to match. case 'a': // 2 strings to match.
if (NameR.substr(13, 2) != ".p") if (memcmp(NameR.data()+11, "i.", 2))
break; break;
switch (NameR[15]) { switch (NameR[13]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
if (NameR.substr(16, 4) != ".256") return Intrinsic::x86_mmx_psrai_d; // "86.mmx.psrai.d"
break; case 'w': // 1 string to match.
return Intrinsic::x86_avx_vtestc_pd_256; // "86.avx. return Intrinsic::x86_mmx_psrai_w; // "86.mmx.psrai.w"
vtestc.pd.256"
case 's': // 1 string to match.
if (NameR.substr(16, 4) != ".256")
break;
return Intrinsic::x86_avx_vtestc_ps_256; // "86.avx.
vtestc.ps.256"
} }
break; break;
case 'z': // 2 strings to match. case 'l': // 3 strings to match.
if (NameR.substr(13, 2) != ".p") if (memcmp(NameR.data()+11, "i.", 2))
break; break;
switch (NameR[15]) { switch (NameR[13]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
if (NameR.substr(16, 4) != ".256") return Intrinsic::x86_mmx_psrli_d; // "86.mmx.psrli.d"
break; case 'q': // 1 string to match.
return Intrinsic::x86_avx_vtestz_pd_256; // "86.avx. return Intrinsic::x86_mmx_psrli_q; // "86.mmx.psrli.q"
vtestz.pd.256" case 'w': // 1 string to match.
case 's': // 1 string to match. return Intrinsic::x86_mmx_psrli_w; // "86.mmx.psrli.w"
if (NameR.substr(16, 4) != ".256")
break;
return Intrinsic::x86_avx_vtestz_ps_256; // "86.avx.
vtestz.ps.256"
} }
break; break;
} }
break; break;
case 'u': // 2 strings to match.
if (memcmp(NameR.data()+10, "bs.", 3))
break;
switch (NameR[13]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::x86_mmx_psubs_b; // "86.mmx.psubs.b"
case 'w': // 1 string to match.
return Intrinsic::x86_mmx_psubs_w; // "86.mmx.psubs.w"
}
break;
} }
break; break;
} }
break; break;
case '2': // 1 string to match. case 'r': // 4 strings to match.
if (NameR.substr(7, 13) != ".vextracti128") if (NameR[4] != 'd')
break;
return Intrinsic::x86_avx2_vextracti128; // "86.avx2.vextrac
ti128"
}
break;
case 'f': // 4 strings to match.
if (NameR.substr(4, 7) != "ma4.vfm")
break;
switch (NameR[11]) {
default: break;
case 'a': // 2 strings to match.
if (NameR.substr(12, 7) != "ddsub.p")
break; break;
switch (NameR[19]) { switch (NameR[5]) {
default: break; default: break;
case 'd': // 1 string to match. case 'f': // 2 strings to match.
return Intrinsic::x86_fma4_vfmaddsub_pd; // "86.fma4.vfmadds if (memcmp(NameR.data()+6, "sbase.", 6))
ub.pd" break;
case 's': // 1 string to match. switch (NameR[12]) {
return Intrinsic::x86_fma4_vfmaddsub_ps; // "86.fma4.vfmadds default: break;
ub.ps" case '3': // 1 string to match.
} if (NameR[13] != '2')
break; break;
case 's': // 2 strings to match. return Intrinsic::x86_rdfsbase_32; // "86.rdfsbase.32"
if (NameR.substr(12, 7) != "ubadd.p") case '6': // 1 string to match.
if (NameR[13] != '4')
break;
return Intrinsic::x86_rdfsbase_64; // "86.rdfsbase.64"
}
break;
case 'g': // 2 strings to match.
if (memcmp(NameR.data()+6, "sbase.", 6))
break;
switch (NameR[12]) {
default: break;
case '3': // 1 string to match.
if (NameR[13] != '2')
break;
return Intrinsic::x86_rdgsbase_32; // "86.rdgsbase.32"
case '6': // 1 string to match.
if (NameR[13] != '4')
break;
return Intrinsic::x86_rdgsbase_64; // "86.rdgsbase.64"
}
break; break;
switch (NameR[19]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::x86_fma4_vfmsubadd_pd; // "86.fma4.vfmsuba
dd.pd"
case 's': // 1 string to match.
return Intrinsic::x86_fma4_vfmsubadd_ps; // "86.fma4.vfmsuba
dd.ps"
} }
break; break;
} case 's': // 29 strings to match.
break; if (memcmp(NameR.data()+4, "se", 2))
case 's': // 16 strings to match. break;
if (NameR[4] != 's')
break;
switch (NameR[5]) {
default: break;
case 'e': // 7 strings to match.
switch (NameR[6]) { switch (NameR[6]) {
default: break; default: break;
case '2': // 4 strings to match. case '.': // 5 strings to match.
if (NameR.substr(7, 2) != ".p") switch (NameR[7]) {
break;
switch (NameR[9]) {
default: break; default: break;
case 'a': // 3 strings to match. case 'l': // 1 string to match.
if (NameR.substr(10, 2) != "ck") if (memcmp(NameR.data()+8, "dmxcsr", 6))
break; break;
switch (NameR[12]) { return Intrinsic::x86_sse_ldmxcsr; // "86.sse.ldmxcsr"
case 'p': // 1 string to match.
if (memcmp(NameR.data()+8, "shuf.w", 6))
break;
return Intrinsic::x86_sse_pshuf_w; // "86.sse.pshuf.w"
case 's': // 3 strings to match.
switch (NameR[8]) {
default: break; default: break;
case 's': // 2 strings to match. case 'q': // 2 strings to match.
if (NameR[13] != 's') if (memcmp(NameR.data()+9, "rt.", 3))
break; break;
switch (NameR[14]) { switch (NameR[12]) {
default: break; default: break;
case 'd': // 1 string to match. case 'p': // 1 string to match.
if (NameR.substr(15, 5) != "w.128") if (NameR[13] != 's')
break; break;
return Intrinsic::x86_sse2_packssdw_128; // "86.sse2 return Intrinsic::x86_sse_sqrt_ps; // "86.sse.sqrt.ps"
.packssdw.128" case 's': // 1 string to match.
case 'w': // 1 string to match. if (NameR[13] != 's')
if (NameR.substr(15, 5) != "b.128")
break; break;
return Intrinsic::x86_sse2_packsswb_128; // "86.sse2 .packsswb.128" return Intrinsic::x86_sse_sqrt_ss; // "86.sse.sqrt.ss"
} }
break; break;
case 'u': // 1 string to match. case 't': // 1 string to match.
if (NameR.substr(13, 7) != "swb.128") if (memcmp(NameR.data()+9, "mxcsr", 5))
break; break;
return Intrinsic::x86_sse2_packuswb_128; // "86.sse2 .packuswb.128" return Intrinsic::x86_sse_stmxcsr; // "86.sse.stmxcsr"
} }
break; break;
case 'm': // 1 string to match.
if (NameR.substr(10, 10) != "ovmskb.128")
break;
return Intrinsic::x86_sse2_pmovmskb_128; // "86.sse2.pmovmsk
b.128"
} }
break; break;
case '4': // 3 strings to match. case '2': // 22 strings to match.
if (NameR.substr(7, 8) != "2.crc32.") if (NameR[7] != '.')
break; break;
switch (NameR[15]) { switch (NameR[8]) {
default: break; default: break;
case '3': // 2 strings to match. case 'a': // 1 string to match.
if (NameR.substr(16, 2) != "2.") if (memcmp(NameR.data()+9, "dd.sd", 5))
break; break;
switch (NameR[18]) { return Intrinsic::x86_sse2_add_sd; // "86.sse2.add.sd"
case 'c': // 2 strings to match.
if (memcmp(NameR.data()+9, "mp.", 3))
break;
switch (NameR[12]) {
default: break; default: break;
case '1': // 1 string to match. case 'p': // 1 string to match.
if (NameR[19] != '6') if (NameR[13] != 'd')
break; break;
return Intrinsic::x86_sse42_crc32_32_16; // "86.sse4 return Intrinsic::x86_sse2_cmp_pd; // "86.sse2.cmp.pd"
2.crc32.32.16" case 's': // 1 string to match.
case '3': // 1 string to match. if (NameR[13] != 'd')
if (NameR[19] != '2')
break; break;
return Intrinsic::x86_sse42_crc32_32_32; // "86.sse4 2.crc32.32.32" return Intrinsic::x86_sse2_cmp_sd; // "86.sse2.cmp.sd"
} }
break; break;
case '6': // 1 string to match. case 'd': // 1 string to match.
if (NameR.substr(16, 4) != "4.64") if (memcmp(NameR.data()+9, "iv.sd", 5))
break; break;
return Intrinsic::x86_sse42_crc32_64_64; // "86.sse42.crc32. return Intrinsic::x86_sse2_div_sd; // "86.sse2.div.sd"
64.64" case 'l': // 1 string to match.
} if (memcmp(NameR.data()+9, "fence", 5))
break;
}
break;
case 's': // 9 strings to match.
if (NameR.substr(6, 4) != "e3.p")
break;
switch (NameR[10]) {
default: break;
case 'h': // 4 strings to match.
switch (NameR[11]) {
default: break;
case 'a': // 2 strings to match.
if (NameR.substr(12, 3) != "dd.")
break; break;
switch (NameR[15]) { return Intrinsic::x86_sse2_lfence; // "86.sse2.lfence"
case 'm': // 6 strings to match.
switch (NameR[9]) {
default: break; default: break;
case 'd': // 1 string to match. case 'a': // 2 strings to match.
if (NameR.substr(16, 4) != ".128") if (memcmp(NameR.data()+10, "x.", 2))
break;
return Intrinsic::x86_ssse3_phadd_d_128; // "86.ssse
3.phadd.d.128"
case 'w': // 1 string to match.
if (NameR.substr(16, 4) != ".128")
break; break;
return Intrinsic::x86_ssse3_phadd_w_128; // "86.ssse switch (NameR[12]) {
3.phadd.w.128" default: break;
} case 'p': // 1 string to match.
break; if (NameR[13] != 'd')
case 's': // 2 strings to match. break;
if (NameR.substr(12, 3) != "ub.") return Intrinsic::x86_sse2_max_pd; // "86.sse2.max.pd"
case 's': // 1 string to match.
if (NameR[13] != 'd')
break;
return Intrinsic::x86_sse2_max_sd; // "86.sse2.max.sd"
}
break; break;
switch (NameR[15]) { case 'f': // 1 string to match.
default: break; if (memcmp(NameR.data()+10, "ence", 4))
case 'd': // 1 string to match.
if (NameR.substr(16, 4) != ".128")
break; break;
return Intrinsic::x86_ssse3_phsub_d_128; // "86.ssse return Intrinsic::x86_sse2_mfence; // "86.sse2.mfence"
3.phsub.d.128" case 'i': // 2 strings to match.
case 'w': // 1 string to match. if (memcmp(NameR.data()+10, "n.", 2))
if (NameR.substr(16, 4) != ".128")
break; break;
return Intrinsic::x86_ssse3_phsub_w_128; // "86.ssse switch (NameR[12]) {
3.phsub.w.128" default: break;
case 'p': // 1 string to match.
if (NameR[13] != 'd')
break;
return Intrinsic::x86_sse2_min_pd; // "86.sse2.min.pd"
case 's': // 1 string to match.
if (NameR[13] != 'd')
break;
return Intrinsic::x86_sse2_min_sd; // "86.sse2.min.sd"
}
break;
case 'u': // 1 string to match.
if (memcmp(NameR.data()+10, "l.sd", 4))
break;
return Intrinsic::x86_sse2_mul_sd; // "86.sse2.mul.sd"
} }
break; break;
} case 'p': // 10 strings to match.
break; switch (NameR[9]) {
case 'm': // 1 string to match.
if (NameR.substr(11, 9) != "add.ub.sw")
break;
return Intrinsic::x86_ssse3_pmadd_ub_sw; // "86.ssse3.pmadd.
ub.sw"
case 's': // 4 strings to match.
switch (NameR[11]) {
default: break;
case 'h': // 1 string to match.
if (NameR.substr(12, 8) != "uf.b.128")
break;
return Intrinsic::x86_ssse3_pshuf_b_128; // "86.ssse3.pshuf.
b.128"
case 'i': // 3 strings to match.
if (NameR.substr(12, 3) != "gn.")
break;
switch (NameR[15]) {
default: break; default: break;
case 'b': // 1 string to match. case 'a': // 2 strings to match.
if (NameR.substr(16, 4) != ".128") if (memcmp(NameR.data()+10, "vg.", 3))
break; break;
return Intrinsic::x86_ssse3_psign_b_128; // "86.ssse switch (NameR[13]) {
3.psign.b.128" default: break;
case 'd': // 1 string to match. case 'b': // 1 string to match.
if (NameR.substr(16, 4) != ".128") return Intrinsic::x86_sse2_pavg_b; // "86.sse2.pavg.b"
case 'w': // 1 string to match.
return Intrinsic::x86_sse2_pavg_w; // "86.sse2.pavg.w"
}
break;
case 's': // 8 strings to match.
switch (NameR[10]) {
default: break;
case 'l': // 3 strings to match.
if (memcmp(NameR.data()+11, "l.", 2))
break;
switch (NameR[13]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::x86_sse2_psll_d; // "86.sse2.psll.d"
case 'q': // 1 string to match.
return Intrinsic::x86_sse2_psll_q; // "86.sse2.psll.q"
case 'w': // 1 string to match.
return Intrinsic::x86_sse2_psll_w; // "86.sse2.psll.w"
}
break; break;
return Intrinsic::x86_ssse3_psign_d_128; // "86.ssse case 'r': // 5 strings to match.
3.psign.d.128" switch (NameR[11]) {
case 'w': // 1 string to match. default: break;
if (NameR.substr(16, 4) != ".128") case 'a': // 2 strings to match.
if (NameR[12] != '.')
break;
switch (NameR[13]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::x86_sse2_psra_d; // "86.sse2
.psra.d"
case 'w': // 1 string to match.
return Intrinsic::x86_sse2_psra_w; // "86.sse2
.psra.w"
}
break;
case 'l': // 3 strings to match.
if (NameR[12] != '.')
break;
switch (NameR[13]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::x86_sse2_psrl_d; // "86.sse2
.psrl.d"
case 'q': // 1 string to match.
return Intrinsic::x86_sse2_psrl_q; // "86.sse2
.psrl.q"
case 'w': // 1 string to match.
return Intrinsic::x86_sse2_psrl_w; // "86.sse2
.psrl.w"
}
break;
}
break; break;
return Intrinsic::x86_ssse3_psign_w_128; // "86.ssse }
3.psign.w.128" break;
} }
break; break;
case 's': // 1 string to match.
if (memcmp(NameR.data()+9, "ub.sd", 5))
break;
return Intrinsic::x86_sse2_sub_sd; // "86.sse2.sub.sd"
} }
break; break;
case '3': // 1 string to match.
if (memcmp(NameR.data()+7, ".ldu.dq", 7))
break;
return Intrinsic::x86_sse3_ldu_dq; // "86.sse3.ldu.dq"
case '4': // 1 string to match.
if (memcmp(NameR.data()+7, "a.extrq", 7))
break;
return Intrinsic::x86_sse4a_extrq; // "86.sse4a.extrq"
} }
break; break;
} case 'w': // 4 strings to match.
break; if (NameR[4] != 'r')
}
break;
case 21: // 16 strings to match.
if (NameR.substr(0, 3) != "86.")
break;
switch (NameR[3]) {
default: break;
case 'a': // 4 strings to match.
if (NameR.substr(4, 6) != "vx.cvt")
break;
switch (NameR[10]) {
default: break;
case '.': // 2 strings to match.
if (NameR[11] != 'p')
break; break;
switch (NameR[12]) { switch (NameR[5]) {
default: break; default: break;
case 'd': // 1 string to match. case 'f': // 2 strings to match.
if (NameR.substr(13, 8) != "2.ps.256") if (memcmp(NameR.data()+6, "sbase.", 6))
break; break;
return Intrinsic::x86_avx_cvt_pd2_ps_256; // "86.avx.cvt.pd2. switch (NameR[12]) {
ps.256" default: break;
case 's': // 1 string to match. case '3': // 1 string to match.
if (NameR.substr(13, 8) != "2.pd.256") if (NameR[13] != '2')
break;
return Intrinsic::x86_wrfsbase_32; // "86.wrfsbase.32"
case '6': // 1 string to match.
if (NameR[13] != '4')
break;
return Intrinsic::x86_wrfsbase_64; // "86.wrfsbase.64"
}
break;
case 'g': // 2 strings to match.
if (memcmp(NameR.data()+6, "sbase.", 6))
break; break;
return Intrinsic::x86_avx_cvt_ps2_pd_256; // "86.avx.cvt.ps2. switch (NameR[12]) {
pd.256" default: break;
case '3': // 1 string to match.
if (NameR[13] != '2')
break;
return Intrinsic::x86_wrgsbase_32; // "86.wrgsbase.32"
case '6': // 1 string to match.
if (NameR[13] != '4')
break;
return Intrinsic::x86_wrgsbase_64; // "86.wrgsbase.64"
}
break;
} }
break; break;
case 't': // 2 strings to match. case 'x': // 8 strings to match.
if (NameR.substr(11, 2) != ".p") if (memcmp(NameR.data()+4, "op.vp", 5))
break; break;
switch (NameR[13]) { switch (NameR[9]) {
default: break; default: break;
case 'd': // 1 string to match. case 'c': // 4 strings to match.
if (NameR.substr(14, 7) != "2dq.256") if (memcmp(NameR.data()+10, "omu", 3))
break; break;
return Intrinsic::x86_avx_cvtt_pd2dq_256; // "86.avx.cvtt.pd2 switch (NameR[13]) {
dq.256" default: break;
case 's': // 1 string to match. case 'b': // 1 string to match.
if (NameR.substr(14, 7) != "2dq.256") return Intrinsic::x86_xop_vpcomub; // "86.xop.vpcomub"
case 'd': // 1 string to match.
return Intrinsic::x86_xop_vpcomud; // "86.xop.vpcomud"
case 'q': // 1 string to match.
return Intrinsic::x86_xop_vpcomuq; // "86.xop.vpcomuq"
case 'w': // 1 string to match.
return Intrinsic::x86_xop_vpcomuw; // "86.xop.vpcomuw"
}
break;
case 'r': // 4 strings to match.
if (memcmp(NameR.data()+10, "ot", 2))
break; break;
return Intrinsic::x86_avx_cvtt_ps2dq_256; // "86.avx.cvtt.ps2 switch (NameR[12]) {
dq.256" default: break;
case 'b': // 1 string to match.
if (NameR[13] != 'i')
break;
return Intrinsic::x86_xop_vprotbi; // "86.xop.vprotbi"
case 'd': // 1 string to match.
if (NameR[13] != 'i')
break;
return Intrinsic::x86_xop_vprotdi; // "86.xop.vprotdi"
case 'q': // 1 string to match.
if (NameR[13] != 'i')
break;
return Intrinsic::x86_xop_vprotqi; // "86.xop.vprotqi"
case 'w': // 1 string to match.
if (NameR[13] != 'i')
break;
return Intrinsic::x86_xop_vprotwi; // "86.xop.vprotwi"
}
break;
} }
break; break;
} }
break; break;
case 'f': // 4 strings to match. case 'c': // 1 string to match.
if (NameR.substr(4, 7) != "ma4.vfm") if (memcmp(NameR.data()+1, "ore.waitevent", 13))
break; break;
switch (NameR[11]) { return Intrinsic::xcore_waitevent; // "core.waitevent"
}
break;
case 15: // 143 strings to match.
switch (NameR[0]) {
default: break;
case '8': // 142 strings to match.
if (memcmp(NameR.data()+1, "6.", 2))
break;
switch (NameR[3]) {
default: break; default: break;
case 'a': // 2 strings to match. case '3': // 3 strings to match.
if (NameR.substr(12, 4) != "dd.p") if (memcmp(NameR.data()+4, "dnow", 4))
break; break;
switch (NameR[16]) { switch (NameR[8]) {
default: break; default: break;
case 'd': // 1 string to match. case '.': // 1 string to match.
if (NameR.substr(17, 4) != ".256") if (memcmp(NameR.data()+9, "pfsubr", 6))
break; break;
return Intrinsic::x86_fma4_vfmadd_pd_256; // "86.fma4.vfmadd. return Intrinsic::x86_3dnow_pfsubr; // "86.3dnow.pfsubr
pd.256" "
case 's': // 1 string to match. case 'a': // 2 strings to match.
if (NameR.substr(17, 4) != ".256") if (memcmp(NameR.data()+9, ".p", 2))
break; break;
return Intrinsic::x86_fma4_vfmadd_ps_256; // "86.fma4.vfmadd. switch (NameR[11]) {
ps.256" default: break;
case 'f': // 1 string to match.
if (memcmp(NameR.data()+12, "2iw", 3))
break;
return Intrinsic::x86_3dnowa_pf2iw; // "86.3dnowa.pf2iw
"
case 'i': // 1 string to match.
if (memcmp(NameR.data()+12, "2fw", 3))
break;
return Intrinsic::x86_3dnowa_pi2fw; // "86.3dnowa.pi2fw
"
}
break;
} }
break; break;
case 's': // 2 strings to match. case 'a': // 48 strings to match.
if (NameR.substr(12, 4) != "ub.p") switch (NameR[4]) {
break;
switch (NameR[16]) {
default: break; default: break;
case 'd': // 1 string to match. case 'e': // 3 strings to match.
if (NameR.substr(17, 4) != ".256") if (memcmp(NameR.data()+5, "sni.aes", 7))
break;
return Intrinsic::x86_fma4_vfmsub_pd_256; // "86.fma4.vfmsub.
pd.256"
case 's': // 1 string to match.
if (NameR.substr(17, 4) != ".256")
break;
return Intrinsic::x86_fma4_vfmsub_ps_256; // "86.fma4.vfmsub.
ps.256"
}
break;
}
break;
case 's': // 6 strings to match.
if (NameR[4] != 's')
break;
switch (NameR[5]) {
default: break;
case 'e': // 4 strings to match.
if (NameR.substr(6, 7) != "42.pcmp")
break;
switch (NameR[13]) {
default: break;
case 'e': // 2 strings to match.
if (NameR.substr(14, 3) != "str")
break;
switch (NameR[17]) {
default: break;
case 'i': // 1 string to match.
if (NameR.substr(18, 3) != "128")
break;
return Intrinsic::x86_sse42_pcmpestri128; // "86.sse4
2.pcmpestri128"
case 'm': // 1 string to match.
if (NameR.substr(18, 3) != "128")
break;
return Intrinsic::x86_sse42_pcmpestrm128; // "86.sse4
2.pcmpestrm128"
}
break;
case 'i': // 2 strings to match.
if (NameR.substr(14, 3) != "str")
break;
switch (NameR[17]) {
default: break;
case 'i': // 1 string to match.
if (NameR.substr(18, 3) != "128")
break;
return Intrinsic::x86_sse42_pcmpistri128; // "86.sse4
2.pcmpistri128"
case 'm': // 1 string to match.
if (NameR.substr(18, 3) != "128")
break;
return Intrinsic::x86_sse42_pcmpistrm128; // "86.sse4
2.pcmpistrm128"
}
break;
}
break;
case 's': // 2 strings to match.
if (NameR.substr(6, 5) != "e3.ph")
break;
switch (NameR[11]) {
default: break;
case 'a': // 1 string to match.
if (NameR.substr(12, 9) != "dd.sw.128")
break;
return Intrinsic::x86_ssse3_phadd_sw_128; // "86.ssse3.phadd.
sw.128"
case 's': // 1 string to match.
if (NameR.substr(12, 9) != "ub.sw.128")
break;
return Intrinsic::x86_ssse3_phsub_sw_128; // "86.ssse3.phsub.
sw.128"
}
break;
}
break;
case 'x': // 2 strings to match.
if (NameR.substr(4, 12) != "op.vpermil2p")
break;
switch (NameR[16]) {
default: break;
case 'd': // 1 string to match.
if (NameR.substr(17, 4) != ".256")
break;
return Intrinsic::x86_xop_vpermil2pd_256; // "86.xop.vpermil2
pd.256"
case 's': // 1 string to match.
if (NameR.substr(17, 4) != ".256")
break;
return Intrinsic::x86_xop_vpermil2ps_256; // "86.xop.vpermil2
ps.256"
}
break;
}
break;
case 22: // 21 strings to match.
if (NameR.substr(0, 3) != "86.")
break;
switch (NameR[3]) {
default: break;
case 'a': // 7 strings to match.
if (NameR.substr(4, 2) != "vx")
break;
switch (NameR[6]) {
default: break;
case '.': // 4 strings to match.
switch (NameR[7]) {
default: break;
case 'm': // 2 strings to match.
if (NameR.substr(8, 9) != "askload.p")
break;
switch (NameR[17]) {
default: break;
case 'd': // 1 string to match.
if (NameR.substr(18, 4) != ".256")
break;
return Intrinsic::x86_avx_maskload_pd_256; // "86.avx.
maskload.pd.256"
case 's': // 1 string to match.
if (NameR.substr(18, 4) != ".256")
break;
return Intrinsic::x86_avx_maskload_ps_256; // "86.avx.
maskload.ps.256"
}
break;
case 'v': // 2 strings to match.
if (NameR.substr(8, 9) != "testnzc.p")
break; break;
switch (NameR[17]) { switch (NameR[12]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
if (NameR.substr(18, 4) != ".256") if (memcmp(NameR.data()+13, "ec", 2))
break;
return Intrinsic::x86_avx_vtestnzc_pd_256; // "86.avx.
vtestnzc.pd.256"
case 's': // 1 string to match.
if (NameR.substr(18, 4) != ".256")
break; break;
return Intrinsic::x86_avx_vtestnzc_ps_256; // "86.avx. return Intrinsic::x86_aesni_aesdec; // "86.aesni.aesdec
vtestnzc.ps.256" "
} case 'e': // 1 string to match.
break; if (memcmp(NameR.data()+13, "nc", 2))
}
break;
case '2': // 3 strings to match.
if (NameR[7] != '.')
break;
switch (NameR[8]) {
default: break;
case 'm': // 2 strings to match.
if (NameR.substr(9, 8) != "askload.")
break;
switch (NameR[17]) {
default: break;
case 'd': // 1 string to match.
if (NameR.substr(18, 4) != ".256")
break; break;
return Intrinsic::x86_avx2_maskload_d_256; // "86.avx2 return Intrinsic::x86_aesni_aesenc; // "86.aesni.aesenc
.maskload.d.256" "
case 'q': // 1 string to match. case 'i': // 1 string to match.
if (NameR.substr(18, 4) != ".256") if (memcmp(NameR.data()+13, "mc", 2))
break; break;
return Intrinsic::x86_avx2_maskload_q_256; // "86.avx2 .maskload.q.256" return Intrinsic::x86_aesni_aesimc; // "86.aesni.aesimc "
} }
break; break;
case 'v': // 1 string to match. case 'v': // 45 strings to match.
if (NameR.substr(9, 13) != "broadcasti128") if (NameR[5] != 'x')
break;
return Intrinsic::x86_avx2_vbroadcasti128; // "86.avx2.vbroadc
asti128"
}
break;
}
break;
case 'f': // 4 strings to match.
if (NameR.substr(4, 8) != "ma4.vfnm")
break;
switch (NameR[12]) {
default: break;
case 'a': // 2 strings to match.
if (NameR.substr(13, 4) != "dd.p")
break;
switch (NameR[17]) {
default: break;
case 'd': // 1 string to match.
if (NameR.substr(18, 4) != ".256")
break;
return Intrinsic::x86_fma4_vfnmadd_pd_256; // "86.fma4.vfnmadd
.pd.256"
case 's': // 1 string to match.
if (NameR.substr(18, 4) != ".256")
break;
return Intrinsic::x86_fma4_vfnmadd_ps_256; // "86.fma4.vfnmadd
.ps.256"
}
break;
case 's': // 2 strings to match.
if (NameR.substr(13, 4) != "ub.p")
break;
switch (NameR[17]) {
default: break;
case 'd': // 1 string to match.
if (NameR.substr(18, 4) != ".256")
break;
return Intrinsic::x86_fma4_vfnmsub_pd_256; // "86.fma4.vfnmsub
.pd.256"
case 's': // 1 string to match.
if (NameR.substr(18, 4) != ".256")
break;
return Intrinsic::x86_fma4_vfnmsub_ps_256; // "86.fma4.vfnmsub
.ps.256"
}
break;
}
break;
case 's': // 10 strings to match.
if (NameR.substr(4, 9) != "se42.pcmp")
break;
switch (NameR[13]) {
default: break;
case 'e': // 5 strings to match.
if (NameR.substr(14, 4) != "stri")
break;
switch (NameR[18]) {
default: break;
case 'a': // 1 string to match.
if (NameR.substr(19, 3) != "128")
break;
return Intrinsic::x86_sse42_pcmpestria128; // "86.sse42.pcmpes
tria128"
case 'c': // 1 string to match.
if (NameR.substr(19, 3) != "128")
break;
return Intrinsic::x86_sse42_pcmpestric128; // "86.sse42.pcmpes
tric128"
case 'o': // 1 string to match.
if (NameR.substr(19, 3) != "128")
break;
return Intrinsic::x86_sse42_pcmpestrio128; // "86.sse42.pcmpes
trio128"
case 's': // 1 string to match.
if (NameR.substr(19, 3) != "128")
break;
return Intrinsic::x86_sse42_pcmpestris128; // "86.sse42.pcmpes
tris128"
case 'z': // 1 string to match.
if (NameR.substr(19, 3) != "128")
break;
return Intrinsic::x86_sse42_pcmpestriz128; // "86.sse42.pcmpes
triz128"
}
break;
case 'i': // 5 strings to match.
if (NameR.substr(14, 4) != "stri")
break;
switch (NameR[18]) {
default: break;
case 'a': // 1 string to match.
if (NameR.substr(19, 3) != "128")
break;
return Intrinsic::x86_sse42_pcmpistria128; // "86.sse42.pcmpis
tria128"
case 'c': // 1 string to match.
if (NameR.substr(19, 3) != "128")
break;
return Intrinsic::x86_sse42_pcmpistric128; // "86.sse42.pcmpis
tric128"
case 'o': // 1 string to match.
if (NameR.substr(19, 3) != "128")
break;
return Intrinsic::x86_sse42_pcmpistrio128; // "86.sse42.pcmpis
trio128"
case 's': // 1 string to match.
if (NameR.substr(19, 3) != "128")
break;
return Intrinsic::x86_sse42_pcmpistris128; // "86.sse42.pcmpis
tris128"
case 'z': // 1 string to match.
if (NameR.substr(19, 3) != "128")
break;
return Intrinsic::x86_sse42_pcmpistriz128; // "86.sse42.pcmpis
triz128"
}
break;
}
break;
}
break;
case 23: // 13 strings to match.
if (NameR.substr(0, 3) != "86.")
break;
switch (NameR[3]) {
default: break;
case 'a': // 12 strings to match.
if (NameR.substr(4, 2) != "vx")
break;
switch (NameR[6]) {
default: break;
case '.': // 2 strings to match.
if (NameR.substr(7, 11) != "maskstore.p")
break;
switch (NameR[18]) {
default: break;
case 'd': // 1 string to match.
if (NameR.substr(19, 4) != ".256")
break;
return Intrinsic::x86_avx_maskstore_pd_256; // "86.avx.
maskstore.pd.256"
case 's': // 1 string to match.
if (NameR.substr(19, 4) != ".256")
break;
return Intrinsic::x86_avx_maskstore_ps_256; // "86.avx.
maskstore.ps.256"
}
break;
case '2': // 10 strings to match.
if (NameR[7] != '.')
break;
switch (NameR[8]) {
default: break;
case 'm': // 2 strings to match.
if (NameR.substr(9, 9) != "askstore.")
break; break;
switch (NameR[18]) { switch (NameR[6]) {
default: break; default: break;
case 'd': // 1 string to match. case '.': // 1 string to match.
if (NameR.substr(19, 4) != ".256") if (memcmp(NameR.data()+7, "vzeroall", 8))
break;
return Intrinsic::x86_avx2_maskstore_d_256; // "86.avx2
.maskstore.d.256"
case 'q': // 1 string to match.
if (NameR.substr(19, 4) != ".256")
break; break;
return Intrinsic::x86_avx2_maskstore_q_256; // "86.avx2 return Intrinsic::x86_avx_vzeroall; // "86.avx.vzeroall
.maskstore.q.256" "
} case '2': // 44 strings to match.
break; if (NameR[7] != '.')
case 'p': // 8 strings to match.
if (NameR.substr(9, 9) != "broadcast")
break;
switch (NameR[18]) {
default: break;
case 'b': // 2 strings to match.
if (NameR[19] != '.')
break; break;
switch (NameR[20]) { switch (NameR[8]) {
default: break; default: break;
case '1': // 1 string to match. case 'm': // 1 string to match.
if (NameR.substr(21, 2) != "28") if (memcmp(NameR.data()+9, "psadbw", 6))
break; break;
return Intrinsic::x86_avx2_pbroadcastb_128; // "86.avx2 return Intrinsic::x86_avx2_mpsadbw; // "86.avx2.mpsadbw
.pbroadcastb.128" "
case '2': // 1 string to match. case 'p': // 43 strings to match.
if (NameR.substr(21, 2) != "56") switch (NameR[9]) {
break;
return Intrinsic::x86_avx2_pbroadcastb_256; // "86.avx2
.pbroadcastb.256"
}
break;
case 'd': // 2 strings to match.
if (NameR[19] != '.')
break;
switch (NameR[20]) {
default: break;
case '1': // 1 string to match.
if (NameR.substr(21, 2) != "28")
break;
return Intrinsic::x86_avx2_pbroadcastd_128; // "86.avx2
.pbroadcastd.128"
case '2': // 1 string to match.
if (NameR.substr(21, 2) != "56")
break;
return Intrinsic::x86_avx2_pbroadcastd_256; // "86.avx2
.pbroadcastd.256"
}
break;
case 'q': // 2 strings to match.
if (NameR[19] != '.')
break;
switch (NameR[20]) {
default: break;
case '1': // 1 string to match.
if (NameR.substr(21, 2) != "28")
break;
return Intrinsic::x86_avx2_pbroadcastq_128; // "86.avx2
.pbroadcastq.128"
case '2': // 1 string to match.
if (NameR.substr(21, 2) != "56")
break;
return Intrinsic::x86_avx2_pbroadcastq_256; // "86.avx2
.pbroadcastq.256"
}
break;
case 'w': // 2 strings to match.
if (NameR[19] != '.')
break;
switch (NameR[20]) {
default: break;
case '1': // 1 string to match.
if (NameR.substr(21, 2) != "28")
break;
return Intrinsic::x86_avx2_pbroadcastw_128; // "86.avx2
.pbroadcastw.128"
case '2': // 1 string to match.
if (NameR.substr(21, 2) != "56")
break;
return Intrinsic::x86_avx2_pbroadcastw_256; // "86.avx2
.pbroadcastw.256"
}
break;
}
break;
}
break;
}
break;
case 's': // 1 string to match.
if (NameR.substr(4, 19) != "sse3.pmul.hr.sw.128")
break;
return Intrinsic::x86_ssse3_pmul_hr_sw_128; // "86.ssse3.pmul.h
r.sw.128"
}
break;
case 24: // 14 strings to match.
if (NameR.substr(0, 3) != "86.")
break;
switch (NameR[3]) {
default: break;
case 'a': // 9 strings to match.
switch (NameR[4]) {
default: break;
case 'e': // 1 string to match.
if (NameR.substr(5, 19) != "sni.aeskeygenassist")
break;
return Intrinsic::x86_aesni_aeskeygenassist; // "86.aesni.aeskey
genassist"
case 'v': // 8 strings to match.
if (NameR[5] != 'x')
break;
switch (NameR[6]) {
default: break;
case '.': // 7 strings to match.
if (NameR[7] != 'v')
break;
switch (NameR[8]) {
default: break;
case 'b': // 2 strings to match.
if (NameR.substr(9, 10) != "roadcast.s")
break;
switch (NameR[19]) {
default: break;
case 'd': // 1 string to match.
if (NameR.substr(20, 4) != ".256")
break;
return Intrinsic::x86_avx_vbroadcast_sd_256; // "86.avx.
vbroadcast.sd.256"
case 's': // 1 string to match.
if (NameR.substr(20, 4) != ".256")
break;
return Intrinsic::x86_avx_vbroadcast_ss_256; // "86.avx.
vbroadcast.ss.256"
}
break;
case 'p': // 5 strings to match.
if (NameR.substr(9, 3) != "erm")
break;
switch (NameR[12]) {
default: break;
case '2': // 3 strings to match.
if (NameR.substr(13, 5) != "f128.")
break;
switch (NameR[18]) {
default: break; default: break;
case 'p': // 2 strings to match. case 'a': // 2 strings to match.
switch (NameR[19]) { if (memcmp(NameR.data()+10, "dds.", 4))
break;
switch (NameR[14]) {
default: break; default: break;
case 'd': // 1 string to match. case 'b': // 1 string to match.
if (NameR.substr(20, 4) != ".256") return Intrinsic::x86_avx2_padds_b; // "86.avx2
.padds.b"
case 'w': // 1 string to match.
return Intrinsic::x86_avx2_padds_w; // "86.avx2
.padds.w"
}
break;
case 'b': // 1 string to match.
if (memcmp(NameR.data()+10, "lendw", 5))
break;
return Intrinsic::x86_avx2_pblendw; // "86.avx2.pblendw
"
case 'h': // 4 strings to match.
switch (NameR[10]) {
default: break;
case 'a': // 2 strings to match.
if (memcmp(NameR.data()+11, "dd.", 3))
break; break;
return Intrinsic::x86_avx_vperm2f128_pd_256; // switch (NameR[14]) {
"86.avx.vperm2f128.pd.256" default: break;
case 's': // 1 string to match. case 'd': // 1 string to match.
if (NameR.substr(20, 4) != ".256") return Intrinsic::x86_avx2_phadd_d; // "86.avx2
.phadd.d"
case 'w': // 1 string to match.
return Intrinsic::x86_avx2_phadd_w; // "86.avx2
.phadd.w"
}
break;
case 's': // 2 strings to match.
if (memcmp(NameR.data()+11, "ub.", 3))
break; break;
return Intrinsic::x86_avx_vperm2f128_ps_256; // switch (NameR[14]) {
"86.avx.vperm2f128.ps.256" default: break;
case 'd': // 1 string to match.
return Intrinsic::x86_avx2_phsub_d; // "86.avx2
.phsub.d"
case 'w': // 1 string to match.
return Intrinsic::x86_avx2_phsub_w; // "86.avx2
.phsub.w"
}
break;
} }
break; break;
case 's': // 1 string to match. case 'm': // 14 strings to match.
if (NameR.substr(19, 5) != "i.256") switch (NameR[10]) {
default: break;
case 'a': // 6 strings to match.
if (NameR[11] != 'x')
break;
switch (NameR[12]) {
default: break;
case 's': // 3 strings to match.
if (NameR[13] != '.')
break;
switch (NameR[14]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::x86_avx2_pmaxs_b; // "86.avx2
.pmaxs.b"
case 'd': // 1 string to match.
return Intrinsic::x86_avx2_pmaxs_d; // "86.avx2
.pmaxs.d"
case 'w': // 1 string to match.
return Intrinsic::x86_avx2_pmaxs_w; // "86.avx2
.pmaxs.w"
}
break;
case 'u': // 3 strings to match.
if (NameR[13] != '.')
break;
switch (NameR[14]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::x86_avx2_pmaxu_b; // "86.avx2
.pmaxu.b"
case 'd': // 1 string to match.
return Intrinsic::x86_avx2_pmaxu_d; // "86.avx2
.pmaxu.d"
case 'w': // 1 string to match.
return Intrinsic::x86_avx2_pmaxu_w; // "86.avx2
.pmaxu.w"
}
break;
}
break; break;
return Intrinsic::x86_avx_vperm2f128_si_256; // "86.avx. case 'i': // 6 strings to match.
vperm2f128.si.256" if (NameR[11] != 'n')
} break;
break; switch (NameR[12]) {
case 'i': // 2 strings to match. default: break;
if (NameR.substr(13, 6) != "lvar.p") case 's': // 3 strings to match.
break; if (NameR[13] != '.')
switch (NameR[19]) { break;
default: break; switch (NameR[14]) {
case 'd': // 1 string to match. default: break;
if (NameR.substr(20, 4) != ".256") case 'b': // 1 string to match.
return Intrinsic::x86_avx2_pmins_b; // "86.avx2
.pmins.b"
case 'd': // 1 string to match.
return Intrinsic::x86_avx2_pmins_d; // "86.avx2
.pmins.d"
case 'w': // 1 string to match.
return Intrinsic::x86_avx2_pmins_w; // "86.avx2
.pmins.w"
}
break;
case 'u': // 3 strings to match.
if (NameR[13] != '.')
break;
switch (NameR[14]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::x86_avx2_pminu_b; // "86.avx2
.pminu.b"
case 'd': // 1 string to match.
return Intrinsic::x86_avx2_pminu_d; // "86.avx2
.pminu.d"
case 'w': // 1 string to match.
return Intrinsic::x86_avx2_pminu_w; // "86.avx2
.pminu.w"
}
break;
}
break; break;
return Intrinsic::x86_avx_vpermilvar_pd_256; // "86.avx. case 'u': // 2 strings to match.
vpermilvar.pd.256" if (NameR[11] != 'l')
case 's': // 1 string to match. break;
if (NameR.substr(20, 4) != ".256") switch (NameR[12]) {
default: break;
case '.': // 1 string to match.
if (memcmp(NameR.data()+13, "dq", 2))
break;
return Intrinsic::x86_avx2_pmul_dq; // "86.avx2
.pmul.dq"
case 'h': // 1 string to match.
if (memcmp(NameR.data()+13, ".w", 2))
break;
return Intrinsic::x86_avx2_pmulh_w; // "86.avx2
.pmulh.w"
}
break; break;
return Intrinsic::x86_avx_vpermilvar_ps_256; // "86.avx. }
vpermilvar.ps.256" break;
} case 's': // 22 strings to match.
break; switch (NameR[10]) {
} default: break;
break; case 'a': // 1 string to match.
} if (memcmp(NameR.data()+11, "d.bw", 4))
break; break;
case '2': // 1 string to match. return Intrinsic::x86_avx2_psad_bw; // "86.avx2
if (NameR.substr(7, 17) != ".vbroadcast.ss.ps") .psad.bw"
break; case 'h': // 1 string to match.
return Intrinsic::x86_avx2_vbroadcast_ss_ps; // "86.avx2 if (memcmp(NameR.data()+11, "uf.b", 4))
.vbroadcast.ss.ps" break;
} return Intrinsic::x86_avx2_pshuf_b; // "86.avx2
break; .pshuf.b"
} case 'i': // 3 strings to match.
break; if (memcmp(NameR.data()+11, "gn.", 3))
case 'f': // 4 strings to match. break;
if (NameR.substr(4, 7) != "ma4.vfm") switch (NameR[14]) {
break; default: break;
switch (NameR[11]) { case 'b': // 1 string to match.
default: break; return Intrinsic::x86_avx2_psign_b; // "86.avx2
case 'a': // 2 strings to match. .psign.b"
if (NameR.substr(12, 7) != "ddsub.p") case 'd': // 1 string to match.
break; return Intrinsic::x86_avx2_psign_d; // "86.avx2
switch (NameR[19]) { .psign.d"
default: break; case 'w': // 1 string to match.
case 'd': // 1 string to match. return Intrinsic::x86_avx2_psign_w; // "86.avx2
if (NameR.substr(20, 4) != ".256") .psign.w"
break; }
return Intrinsic::x86_fma4_vfmaddsub_pd_256; // "86.fma4 break;
.vfmaddsub.pd.256" case 'l': // 6 strings to match.
case 's': // 1 string to match. if (NameR[11] != 'l')
if (NameR.substr(20, 4) != ".256") break;
break; switch (NameR[12]) {
return Intrinsic::x86_fma4_vfmaddsub_ps_256; // "86.fma4 default: break;
.vfmaddsub.ps.256" case '.': // 1 string to match.
} if (memcmp(NameR.data()+13, "dq", 2))
break; break;
case 's': // 2 strings to match. return Intrinsic::x86_avx2_psll_dq; // "86.avx2
if (NameR.substr(12, 7) != "ubadd.p") .psll.dq"
break; case 'i': // 3 strings to match.
switch (NameR[19]) { if (NameR[13] != '.')
default: break; break;
case 'd': // 1 string to match. switch (NameR[14]) {
if (NameR.substr(20, 4) != ".256") default: break;
break; case 'd': // 1 string to match.
return Intrinsic::x86_fma4_vfmsubadd_pd_256; // "86.fma4 return Intrinsic::x86_avx2_pslli_d; // "86.avx2
.vfmsubadd.pd.256" .pslli.d"
case 's': // 1 string to match. case 'q': // 1 string to match.
if (NameR.substr(20, 4) != ".256") return Intrinsic::x86_avx2_pslli_q; // "86.avx2
.pslli.q"
case 'w': // 1 string to match.
return Intrinsic::x86_avx2_pslli_w; // "86.avx2
.pslli.w"
}
break;
case 'v': // 2 strings to match.
if (NameR[13] != '.')
break;
switch (NameR[14]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::x86_avx2_psllv_d; // "86.avx2
.psllv.d"
case 'q': // 1 string to match.
return Intrinsic::x86_avx2_psllv_q; // "86.avx2
.psllv.q"
}
break;
}
break;
case 'r': // 9 strings to match.
switch (NameR[11]) {
default: break;
case 'a': // 3 strings to match.
switch (NameR[12]) {
default: break;
case 'i': // 2 strings to match.
if (NameR[13] != '.')
break;
switch (NameR[14]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::x86_avx2_psrai_d; // "86.avx2
.psrai.d"
case 'w': // 1 string to match.
return Intrinsic::x86_avx2_psrai_w; // "86.avx2
.psrai.w"
}
break;
case 'v': // 1 string to match.
if (memcmp(NameR.data()+13, ".d", 2))
break;
return Intrinsic::x86_avx2_psrav_d; // "86.avx2
.psrav.d"
}
break;
case 'l': // 6 strings to match.
switch (NameR[12]) {
default: break;
case '.': // 1 string to match.
if (memcmp(NameR.data()+13, "dq", 2))
break;
return Intrinsic::x86_avx2_psrl_dq; // "86.avx2
.psrl.dq"
case 'i': // 3 strings to match.
if (NameR[13] != '.')
break;
switch (NameR[14]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::x86_avx2_psrli_d; // "86.avx2
.psrli.d"
case 'q': // 1 string to match.
return Intrinsic::x86_avx2_psrli_q; // "86.avx2
.psrli.q"
case 'w': // 1 string to match.
return Intrinsic::x86_avx2_psrli_w; // "86.avx2
.psrli.w"
}
break;
case 'v': // 2 strings to match.
if (NameR[13] != '.')
break;
switch (NameR[14]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::x86_avx2_psrlv_d; // "86.avx2
.psrlv.d"
case 'q': // 1 string to match.
return Intrinsic::x86_avx2_psrlv_q; // "86.avx2
.psrlv.q"
}
break;
}
break;
}
break;
case 'u': // 2 strings to match.
if (memcmp(NameR.data()+11, "bs.", 3))
break;
switch (NameR[14]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::x86_avx2_psubs_b; // "86.avx2
.psubs.b"
case 'w': // 1 string to match.
return Intrinsic::x86_avx2_psubs_w; // "86.avx2
.psubs.w"
}
break;
}
break;
}
break;
}
break; break;
return Intrinsic::x86_fma4_vfmsubadd_ps_256; // "86.fma4 }
.vfmsubadd.ps.256"
}
break;
}
break;
case 's': // 1 string to match.
if (NameR.substr(4, 20) != "sse3.pmadd.ub.sw.128")
break;
return Intrinsic::x86_ssse3_pmadd_ub_sw_128; // "86.ssse3.pmadd.
ub.sw.128"
}
break;
case 25: // 3 strings to match.
if (NameR.substr(0, 19) != "86.avx.vinsertf128.")
break;
switch (NameR[19]) {
default: break;
case 'p': // 2 strings to match.
switch (NameR[20]) {
default: break;
case 'd': // 1 string to match.
if (NameR.substr(21, 4) != ".256")
break;
return Intrinsic::x86_avx_vinsertf128_pd_256; // "86.avx.
vinsertf128.pd.256"
case 's': // 1 string to match.
if (NameR.substr(21, 4) != ".256")
break;
return Intrinsic::x86_avx_vinsertf128_ps_256; // "86.avx.
vinsertf128.ps.256"
}
break;
case 's': // 1 string to match.
if (NameR.substr(20, 5) != "i.256")
break;
return Intrinsic::x86_avx_vinsertf128_si_256; // "86.avx.vinsertf
128.si.256"
}
break;
case 26: // 3 strings to match.
if (NameR.substr(0, 20) != "86.avx.vextractf128.")
break;
switch (NameR[20]) {
default: break;
case 'p': // 2 strings to match.
switch (NameR[21]) {
default: break;
case 'd': // 1 string to match.
if (NameR.substr(22, 4) != ".256")
break;
return Intrinsic::x86_avx_vextractf128_pd_256; // "86.avx.
vextractf128.pd.256"
case 's': // 1 string to match.
if (NameR.substr(22, 4) != ".256")
break; break;
return Intrinsic::x86_avx_vextractf128_ps_256; // "86.avx. }
vextractf128.ps.256"
}
break;
case 's': // 1 string to match.
if (NameR.substr(21, 5) != "i.256")
break;
return Intrinsic::x86_avx_vextractf128_si_256; // "86.avx.vextract
f128.si.256"
}
break;
case 28: // 4 strings to match.
if (NameR.substr(0, 6) != "86.avx")
break;
switch (NameR[6]) {
default: break;
case '.': // 2 strings to match.
if (NameR.substr(7, 16) != "vbroadcastf128.p")
break; break;
switch (NameR[23]) { case 'b': // 2 strings to match.
default: break; if (memcmp(NameR.data()+4, "mi.bextr.", 9))
case 'd': // 1 string to match.
if (NameR.substr(24, 4) != ".256")
break;
return Intrinsic::x86_avx_vbroadcastf128_pd_256; // "86.avx.
vbroadcastf128.pd.256"
case 's': // 1 string to match.
if (NameR.substr(24, 4) != ".256")
break; break;
return Intrinsic::x86_avx_vbroadcastf128_ps_256; // "86.avx. switch (NameR[13]) {
vbroadcastf128.ps.256" default: break;
} case '3': // 1 string to match.
break; if (NameR[14] != '2')
case '2': // 2 strings to match. break;
if (NameR.substr(7, 13) != ".vbroadcast.s") return Intrinsic::x86_bmi_bextr_32; // "86.bmi.bextr.32
"
case '6': // 1 string to match.
if (NameR[14] != '4')
break;
return Intrinsic::x86_bmi_bextr_64; // "86.bmi.bextr.64
"
}
break; break;
switch (NameR[20]) { case 'm': // 19 strings to match.
default: break; if (memcmp(NameR.data()+4, "mx.", 3))
case 'd': // 1 string to match.
if (NameR.substr(21, 7) != ".pd.256")
break; break;
return Intrinsic::x86_avx2_vbroadcast_sd_pd_256; // "86.avx2 switch (NameR[7]) {
.vbroadcast.sd.pd.256" default: break;
case 's': // 1 string to match. case 'm': // 2 strings to match.
if (NameR.substr(21, 7) != ".ps.256") switch (NameR[8]) {
default: break;
case 'a': // 1 string to match.
if (memcmp(NameR.data()+9, "skmovq", 6))
break;
return Intrinsic::x86_mmx_maskmovq; // "86.mmx.maskmovq
"
case 'o': // 1 string to match.
if (memcmp(NameR.data()+9, "vnt.dq", 6))
break;
return Intrinsic::x86_mmx_movnt_dq; // "86.mmx.movnt.dq
"
}
break; break;
return Intrinsic::x86_avx2_vbroadcast_ss_ps_256; // "86.avx2 case 'p': // 17 strings to match.
.vbroadcast.ss.ps.256" switch (NameR[8]) {
} default: break;
break; case 'a': // 5 strings to match.
} switch (NameR[9]) {
break; default: break;
} case 'c': // 3 strings to match.
break; // end of 'x' case. if (NameR[10] != 'k')
} break;
#endif switch (NameR[11]) {
default: break;
// Verifier::visitIntrinsicFunctionCall code. case 's': // 2 strings to match.
#ifdef GET_INTRINSIC_VERIFIER if (NameR[12] != 's')
switch (ID) { break;
default: llvm_unreachable("Invalid intrinsic!"); switch (NameR[13]) {
case Intrinsic::eh_unwind_init: // llvm.eh.unwind.init default: break;
case Intrinsic::ppc_altivec_dssall: // llvm.ppc.altivec.dssall case 'd': // 1 string to match.
case Intrinsic::ppc_sync: // llvm.ppc.sync if (NameR[14] != 'w')
case Intrinsic::trap: // llvm.trap break;
case Intrinsic::x86_avx_vzeroall: // llvm.x86.avx.vzeroall return Intrinsic::x86_mmx_packssdw; // "86.mmx.
case Intrinsic::x86_avx_vzeroupper: // llvm.x86.avx.vzeroupper packssdw"
case Intrinsic::x86_mmx_emms: // llvm.x86.mmx.emms case 'w': // 1 string to match.
case Intrinsic::x86_mmx_femms: // llvm.x86.mmx.femms if (NameR[14] != 'b')
case Intrinsic::x86_sse2_lfence: // llvm.x86.sse2.lfence break;
case Intrinsic::x86_sse2_mfence: // llvm.x86.sse2.mfence return Intrinsic::x86_mmx_packsswb; // "86.mmx.
case Intrinsic::x86_sse_sfence: // llvm.x86.sse.sfence packsswb"
case Intrinsic::xcore_clre: // llvm.xcore.clre }
case Intrinsic::xcore_ssync: // llvm.xcore.ssync break;
VerifyIntrinsicPrototype(ID, IF, 0, 0); case 'u': // 1 string to match.
break; if (memcmp(NameR.data()+12, "swb", 3))
case Intrinsic::xcore_eeu: // llvm.xcore.eeu break;
case Intrinsic::xcore_freer: // llvm.xcore.freer return Intrinsic::x86_mmx_packuswb; // "86.mmx.packuswb
case Intrinsic::xcore_mjoin: // llvm.xcore.mjoin "
case Intrinsic::xcore_msync: // llvm.xcore.msync }
case Intrinsic::xcore_syncr: // llvm.xcore.syncr break;
VerifyIntrinsicPrototype(ID, IF, 0, 1, MVT::iPTRAny); case 'd': // 2 strings to match.
break; if (memcmp(NameR.data()+10, "dus.", 4))
case Intrinsic::xcore_setclk: // llvm.xcore.setclk break;
case Intrinsic::xcore_setrdy: // llvm.xcore.setrdy switch (NameR[14]) {
VerifyIntrinsicPrototype(ID, IF, 0, 2, MVT::iPTRAny, MVT::iPTRAny); default: break;
break; case 'b': // 1 string to match.
case Intrinsic::memcpy: // llvm.memcpy return Intrinsic::x86_mmx_paddus_b; // "86.mmx.paddus.b
case Intrinsic::memmove: // llvm.memmove "
VerifyIntrinsicPrototype(ID, IF, 0, 5, MVT::iPTRAny, MVT::iPTRAny, MVT: case 'w': // 1 string to match.
:iAny, MVT::i32, MVT::i1); return Intrinsic::x86_mmx_paddus_w; // "86.mmx.paddus.w
break; "
case Intrinsic::xcore_chkct: // llvm.xcore.chkct }
case Intrinsic::xcore_out: // llvm.xcore.out break;
case Intrinsic::xcore_outct: // llvm.xcore.outct }
case Intrinsic::xcore_outt: // llvm.xcore.outt break;
case Intrinsic::xcore_setc: // llvm.xcore.setc case 'c': // 6 strings to match.
case Intrinsic::xcore_setd: // llvm.xcore.setd if (memcmp(NameR.data()+9, "mp", 2))
case Intrinsic::xcore_setpsc: // llvm.xcore.setpsc break;
case Intrinsic::xcore_setpt: // llvm.xcore.setpt switch (NameR[11]) {
case Intrinsic::xcore_settw: // llvm.xcore.settw default: break;
VerifyIntrinsicPrototype(ID, IF, 0, 2, MVT::iPTRAny, MVT::i32); case 'e': // 3 strings to match.
break; if (memcmp(NameR.data()+12, "q.", 2))
case Intrinsic::memset: // llvm.memset break;
VerifyIntrinsicPrototype(ID, IF, 0, 5, MVT::iPTRAny, MVT::i8, MVT::iAny switch (NameR[14]) {
, MVT::i32, MVT::i1); default: break;
break; case 'b': // 1 string to match.
case Intrinsic::xcore_initcp: // llvm.xcore.initcp return Intrinsic::x86_mmx_pcmpeq_b; // "86.mmx.pcmpeq.b
case Intrinsic::xcore_initdp: // llvm.xcore.initdp "
case Intrinsic::xcore_initlr: // llvm.xcore.initlr case 'd': // 1 string to match.
case Intrinsic::xcore_initpc: // llvm.xcore.initpc return Intrinsic::x86_mmx_pcmpeq_d; // "86.mmx.pcmpeq.d
case Intrinsic::xcore_initsp: // llvm.xcore.initsp "
case Intrinsic::xcore_setev: // llvm.xcore.setev case 'w': // 1 string to match.
case Intrinsic::xcore_setv: // llvm.xcore.setv return Intrinsic::x86_mmx_pcmpeq_w; // "86.mmx.pcmpeq.w
VerifyIntrinsicPrototype(ID, IF, 0, 2, MVT::iPTRAny, MVT::iPTR); "
break; }
case Intrinsic::invariant_end: // llvm.invariant.end break;
VerifyIntrinsicPrototype(ID, IF, 0, 3, MVT::iPTR, MVT::i64, MVT::iPTR); case 'g': // 3 strings to match.
break; if (memcmp(NameR.data()+12, "t.", 2))
case Intrinsic::arm_set_fpscr: // llvm.arm.set.fpscr break;
case Intrinsic::eh_sjlj_callsite: // llvm.eh.sjlj.callsite switch (NameR[14]) {
case Intrinsic::pcmarker: // llvm.pcmarker default: break;
case Intrinsic::ppc_altivec_dss: // llvm.ppc.altivec.dss case 'b': // 1 string to match.
case Intrinsic::ptx_bar_sync: // llvm.ptx.bar.sync return Intrinsic::x86_mmx_pcmpgt_b; // "86.mmx.pcmpgt.b
case Intrinsic::x86_wrfsbase_32: // llvm.x86.wrfsbase.32 "
case Intrinsic::x86_wrgsbase_32: // llvm.x86.wrgsbase.32 case 'd': // 1 string to match.
case Intrinsic::xcore_clrsr: // llvm.xcore.clrsr return Intrinsic::x86_mmx_pcmpgt_d; // "86.mmx.pcmpgt.d
case Intrinsic::xcore_setsr: // llvm.xcore.setsr "
VerifyIntrinsicPrototype(ID, IF, 0, 1, MVT::i32); case 'w': // 1 string to match.
break; return Intrinsic::x86_mmx_pcmpgt_w; // "86.mmx.pcmpgt.w
case Intrinsic::x86_sse3_mwait: // llvm.x86.sse3.mwait "
case Intrinsic::xcore_setps: // llvm.xcore.setps }
VerifyIntrinsicPrototype(ID, IF, 0, 2, MVT::i32, MVT::i32); break;
break; }
case Intrinsic::arm_mcrr: // llvm.arm.mcrr break;
case Intrinsic::arm_mcrr2: // llvm.arm.mcrr2 case 'm': // 4 strings to match.
VerifyIntrinsicPrototype(ID, IF, 0, 5, MVT::i32, MVT::i32, MVT::i32, MV switch (NameR[9]) {
T::i32, MVT::i32); default: break;
break; case 'a': // 1 string to match.
case Intrinsic::arm_cdp: // llvm.arm.cdp if (memcmp(NameR.data()+10, "dd.wd", 5))
case Intrinsic::arm_cdp2: // llvm.arm.cdp2 break;
case Intrinsic::arm_mcr: // llvm.arm.mcr return Intrinsic::x86_mmx_pmadd_wd; // "86.mmx.pmadd.wd
case Intrinsic::arm_mcr2: // llvm.arm.mcr2 "
VerifyIntrinsicPrototype(ID, IF, 0, 6, MVT::i32, MVT::i32, MVT::i32, MV case 'o': // 1 string to match.
T::i32, MVT::i32, MVT::i32); if (memcmp(NameR.data()+10, "vmskb", 5))
break; break;
case Intrinsic::eh_return_i32: // llvm.eh.return.i32 return Intrinsic::x86_mmx_pmovmskb; // "86.mmx.pmovmskb
VerifyIntrinsicPrototype(ID, IF, 0, 2, MVT::i32, MVT::iPTR); "
break; case 'u': // 2 strings to match.
case Intrinsic::x86_wrfsbase_64: // llvm.x86.wrfsbase.64 if (NameR[10] != 'l')
case Intrinsic::x86_wrgsbase_64: // llvm.x86.wrgsbase.64 break;
VerifyIntrinsicPrototype(ID, IF, 0, 1, MVT::i64); switch (NameR[11]) {
break; default: break;
case Intrinsic::eh_return_i64: // llvm.eh.return.i64 case 'h': // 1 string to match.
case Intrinsic::lifetime_end: // llvm.lifetime.end if (memcmp(NameR.data()+12, "u.w", 3))
case Intrinsic::lifetime_start: // llvm.lifetime.start break;
VerifyIntrinsicPrototype(ID, IF, 0, 2, MVT::i64, MVT::iPTR); return Intrinsic::x86_mmx_pmulhu_w; // "86.mmx.pmulhu.w
break; "
case Intrinsic::x86_int: // llvm.x86.int case 'u': // 1 string to match.
VerifyIntrinsicPrototype(ID, IF, 0, 1, MVT::i8); if (memcmp(NameR.data()+12, ".dq", 3))
break; break;
case Intrinsic::dbg_value: // llvm.dbg.value return Intrinsic::x86_mmx_pmulu_dq; // "86.mmx.pmulu.dq
VerifyIntrinsicPrototype(ID, IF, 0, 3, MVT::Metadata, MVT::i64, MVT::Me "
tadata); }
break; break;
case Intrinsic::dbg_declare: // llvm.dbg.declare }
VerifyIntrinsicPrototype(ID, IF, 0, 2, MVT::Metadata, MVT::Metadata); break;
break; case 's': // 2 strings to match.
case Intrinsic::eh_sjlj_functioncontext: // llvm.eh.sjlj.func if (memcmp(NameR.data()+9, "ubus.", 5))
tioncontext break;
case Intrinsic::eh_sjlj_longjmp: // llvm.eh.sjlj.longjmp switch (NameR[14]) {
case Intrinsic::ppc_dcba: // llvm.ppc.dcba default: break;
case Intrinsic::ppc_dcbf: // llvm.ppc.dcbf case 'b': // 1 string to match.
case Intrinsic::ppc_dcbi: // llvm.ppc.dcbi return Intrinsic::x86_mmx_psubus_b; // "86.mmx.psubus.b
case Intrinsic::ppc_dcbst: // llvm.ppc.dcbst "
case Intrinsic::ppc_dcbt: // llvm.ppc.dcbt case 'w': // 1 string to match.
case Intrinsic::ppc_dcbtst: // llvm.ppc.dcbtst return Intrinsic::x86_mmx_psubus_w; // "86.mmx.psubus.w
case Intrinsic::ppc_dcbz: // llvm.ppc.dcbz "
case Intrinsic::ppc_dcbzl: // llvm.ppc.dcbzl }
case Intrinsic::stackrestore: // llvm.stackrestore break;
case Intrinsic::vaend: // llvm.va_end }
case Intrinsic::vastart: // llvm.va_start break;
case Intrinsic::x86_sse2_clflush: // llvm.x86.sse2.clflush }
case Intrinsic::x86_sse_ldmxcsr: // llvm.x86.sse.ldmxcsr break;
case Intrinsic::x86_sse_stmxcsr: // llvm.x86.sse.stmxcsr case 's': // 54 strings to match.
VerifyIntrinsicPrototype(ID, IF, 0, 1, MVT::iPTR); if (NameR[4] != 's')
break; break;
case Intrinsic::arm_neon_vst2: // llvm.arm.neon.vst2 switch (NameR[5]) {
VerifyIntrinsicPrototype(ID, IF, 0, 4, MVT::iPTR, MVT::vAny, ~1, MVT::i default: break;
32); case 'e': // 51 strings to match.
break; switch (NameR[6]) {
case Intrinsic::arm_neon_vst3: // llvm.arm.neon.vst3 default: break;
VerifyIntrinsicPrototype(ID, IF, 0, 5, MVT::iPTR, MVT::vAny, ~1, ~1, MV case '.': // 8 strings to match.
T::i32); switch (NameR[7]) {
break; default: break;
case Intrinsic::arm_neon_vst4: // llvm.arm.neon.vst4 case 'c': // 6 strings to match.
VerifyIntrinsicPrototype(ID, IF, 0, 6, MVT::iPTR, MVT::vAny, ~1, ~1, ~1 if (memcmp(NameR.data()+8, "vt", 2))
, MVT::i32); break;
break; switch (NameR[10]) {
case Intrinsic::arm_neon_vst2lane: // llvm.arm.neon.vst2lane default: break;
VerifyIntrinsicPrototype(ID, IF, 0, 5, MVT::iPTR, MVT::vAny, ~1, MVT::i case 'p': // 4 strings to match.
32, MVT::i32); switch (NameR[11]) {
break; default: break;
case Intrinsic::arm_neon_vst3lane: // llvm.arm.neon.vst3lane case 'd': // 1 string to match.
VerifyIntrinsicPrototype(ID, IF, 0, 6, MVT::iPTR, MVT::vAny, ~1, ~1, MV if (memcmp(NameR.data()+12, "2pi", 3))
T::i32, MVT::i32); break;
break; return Intrinsic::x86_sse_cvtpd2pi; // "86.sse.
case Intrinsic::arm_neon_vst4lane: // llvm.arm.neon.vst4lane cvtpd2pi"
VerifyIntrinsicPrototype(ID, IF, 0, 7, MVT::iPTR, MVT::vAny, ~1, ~1, ~1 case 'i': // 2 strings to match.
, MVT::i32, MVT::i32); if (memcmp(NameR.data()+12, "2p", 2))
break; break;
case Intrinsic::arm_neon_vst1: // llvm.arm.neon.vst1 switch (NameR[14]) {
VerifyIntrinsicPrototype(ID, IF, 0, 3, MVT::iPTR, MVT::vAny, MVT::i32); default: break;
break; case 'd': // 1 string to match.
case Intrinsic::longjmp: // llvm.longjmp return Intrinsic::x86_sse_cvtpi2pd; // "86.sse.
case Intrinsic::siglongjmp: // llvm.siglongjmp cvtpi2pd"
VerifyIntrinsicPrototype(ID, IF, 0, 2, MVT::iPTR, MVT::i32); case 's': // 1 string to match.
break; return Intrinsic::x86_sse_cvtpi2ps; // "86.sse.
case Intrinsic::ppc_altivec_dst: // llvm.ppc.altivec.dst cvtpi2ps"
case Intrinsic::ppc_altivec_dstst: // llvm.ppc.altivec.dstst }
case Intrinsic::ppc_altivec_dststt: // llvm.ppc.altivec.dststt break;
case Intrinsic::ppc_altivec_dstt: // llvm.ppc.altivec.dstt case 's': // 1 string to match.
case Intrinsic::x86_sse3_monitor: // llvm.x86.sse3.monitor if (memcmp(NameR.data()+12, "2pi", 3))
VerifyIntrinsicPrototype(ID, IF, 0, 3, MVT::iPTR, MVT::i32, MVT::i32); break;
break; return Intrinsic::x86_sse_cvtps2pi; // "86.sse.
case Intrinsic::prefetch: // llvm.prefetch cvtps2pi"
VerifyIntrinsicPrototype(ID, IF, 0, 4, MVT::iPTR, MVT::i32, MVT::i32, M }
VT::i32); break;
break; case 's': // 2 strings to match.
case Intrinsic::vacopy: // llvm.va_copy switch (NameR[11]) {
VerifyIntrinsicPrototype(ID, IF, 0, 2, MVT::iPTR, MVT::iPTR); default: break;
break; case 'i': // 1 string to match.
case Intrinsic::init_trampoline: // llvm.init.trampoline if (memcmp(NameR.data()+12, "2ss", 3))
VerifyIntrinsicPrototype(ID, IF, 0, 3, MVT::iPTR, MVT::iPTR, MVT::iPTR) break;
; return Intrinsic::x86_sse_cvtsi2ss; // "86.sse.
break; cvtsi2ss"
case Intrinsic::var_annotation: // llvm.var.annotation case 's': // 1 string to match.
VerifyIntrinsicPrototype(ID, IF, 0, 4, MVT::iPTR, MVT::iPTR, MVT::iPTR, if (memcmp(NameR.data()+12, "2si", 3))
MVT::i32); break;
break; return Intrinsic::x86_sse_cvtss2si; // "86.sse.
case Intrinsic::gcwrite: // llvm.gcwrite cvtss2si"
VerifyIntrinsicPrototype(ID, IF, 0, 3, MVT::iPTR, MVT::iPTR, MVT::iPTR) }
; break;
break; }
case Intrinsic::stackprotector: // llvm.stackprotector break;
VerifyIntrinsicPrototype(ID, IF, 0, 2, MVT::iPTR, MVT::iPTR); case 'r': // 2 strings to match.
break; if (memcmp(NameR.data()+8, "sqrt.", 5))
case Intrinsic::x86_sse2_storeu_dq: // llvm.x86.sse2.storeu.dq break;
VerifyIntrinsicPrototype(ID, IF, 0, 2, MVT::iPTR, MVT::v16i8); switch (NameR[13]) {
break; default: break;
case Intrinsic::x86_sse2_storeu_pd: // llvm.x86.sse2.storeu.pd case 'p': // 1 string to match.
VerifyIntrinsicPrototype(ID, IF, 0, 2, MVT::iPTR, MVT::v2f64); if (NameR[14] != 's')
break; break;
case Intrinsic::x86_avx_maskstore_pd: // llvm.x86.avx.mask return Intrinsic::x86_sse_rsqrt_ps; // "86.sse.rsqrt.ps
store.pd "
VerifyIntrinsicPrototype(ID, IF, 0, 3, MVT::iPTR, MVT::v2f64, MVT::v2f6 case 's': // 1 string to match.
4); if (NameR[14] != 's')
break; break;
case Intrinsic::x86_avx2_maskstore_q: // llvm.x86.avx2.mas return Intrinsic::x86_sse_rsqrt_ss; // "86.sse.rsqrt.ss
kstore.q "
VerifyIntrinsicPrototype(ID, IF, 0, 3, MVT::iPTR, MVT::v2i64, MVT::v2i6 }
4); break;
break; }
case Intrinsic::x86_avx_storeu_dq_256: // llvm.x86.avx.stor break;
eu.dq.256 case '2': // 23 strings to match.
VerifyIntrinsicPrototype(ID, IF, 0, 2, MVT::iPTR, MVT::v32i8); if (NameR[7] != '.')
break; break;
case Intrinsic::x86_sse_storeu_ps: // llvm.x86.sse.storeu.ps switch (NameR[8]) {
VerifyIntrinsicPrototype(ID, IF, 0, 2, MVT::iPTR, MVT::v4f32); default: break;
break; case 'c': // 1 string to match.
case Intrinsic::x86_avx_maskstore_ps: // llvm.x86.avx.mask if (memcmp(NameR.data()+9, "lflush", 6))
store.ps break;
VerifyIntrinsicPrototype(ID, IF, 0, 3, MVT::iPTR, MVT::v4f32, MVT::v4f3 return Intrinsic::x86_sse2_clflush; // "86.sse2.clflush
2); "
break; case 'p': // 20 strings to match.
case Intrinsic::x86_avx_movnt_pd_256: // llvm.x86.avx.movn switch (NameR[9]) {
t.pd.256 default: break;
case Intrinsic::x86_avx_storeu_pd_256: // llvm.x86.avx.stor case 'a': // 2 strings to match.
eu.pd.256 if (memcmp(NameR.data()+10, "dds.", 4))
VerifyIntrinsicPrototype(ID, IF, 0, 2, MVT::iPTR, MVT::v4f64); break;
break; switch (NameR[14]) {
case Intrinsic::x86_avx_maskstore_pd_256: // llvm.x86.avx.mask default: break;
store.pd.256 case 'b': // 1 string to match.
VerifyIntrinsicPrototype(ID, IF, 0, 3, MVT::iPTR, MVT::v4f64, MVT::v4f6 return Intrinsic::x86_sse2_padds_b; // "86.sse2
4); .padds.b"
break; case 'w': // 1 string to match.
case Intrinsic::x86_sse2_storel_dq: // llvm.x86.sse2.storel.dq return Intrinsic::x86_sse2_padds_w; // "86.sse2
VerifyIntrinsicPrototype(ID, IF, 0, 2, MVT::iPTR, MVT::v4i32); .padds.w"
break; }
case Intrinsic::x86_avx2_maskstore_d: // llvm.x86.avx2.mas break;
kstore.d case 'm': // 5 strings to match.
VerifyIntrinsicPrototype(ID, IF, 0, 3, MVT::iPTR, MVT::v4i32, MVT::v4i3 switch (NameR[10]) {
2); default: break;
break; case 'a': // 2 strings to match.
case Intrinsic::x86_avx_movnt_dq_256: // llvm.x86.avx.movn if (NameR[11] != 'x')
t.dq.256 break;
VerifyIntrinsicPrototype(ID, IF, 0, 2, MVT::iPTR, MVT::v4i64); switch (NameR[12]) {
break; default: break;
case Intrinsic::x86_avx2_maskstore_q_256: // llvm.x86.avx2.mas case 's': // 1 string to match.
kstore.q.256 if (memcmp(NameR.data()+13, ".w", 2))
VerifyIntrinsicPrototype(ID, IF, 0, 3, MVT::iPTR, MVT::v4i64, MVT::v4i6 break;
4); return Intrinsic::x86_sse2_pmaxs_w; // "86.sse2
break; .pmaxs.w"
case Intrinsic::x86_avx_movnt_ps_256: // llvm.x86.avx.movn case 'u': // 1 string to match.
t.ps.256 if (memcmp(NameR.data()+13, ".b", 2))
case Intrinsic::x86_avx_storeu_ps_256: // llvm.x86.avx.stor break;
eu.ps.256 return Intrinsic::x86_sse2_pmaxu_b; // "86.sse2
VerifyIntrinsicPrototype(ID, IF, 0, 2, MVT::iPTR, MVT::v8f32); .pmaxu.b"
break; }
case Intrinsic::x86_avx_maskstore_ps_256: // llvm.x86.avx.mask break;
store.ps.256 case 'i': // 2 strings to match.
VerifyIntrinsicPrototype(ID, IF, 0, 3, MVT::iPTR, MVT::v8f32, MVT::v8f3 if (NameR[11] != 'n')
2); break;
break; switch (NameR[12]) {
case Intrinsic::x86_avx2_maskstore_d_256: // llvm.x86.avx2.mas default: break;
kstore.d.256 case 's': // 1 string to match.
VerifyIntrinsicPrototype(ID, IF, 0, 3, MVT::iPTR, MVT::v8i32, MVT::v8i3 if (memcmp(NameR.data()+13, ".w", 2))
2); break;
break; return Intrinsic::x86_sse2_pmins_w; // "86.sse2
case Intrinsic::gcroot: // llvm.gcroot .pmins.w"
VerifyIntrinsicPrototype(ID, IF, 0, 2, MVT::iPTR, MVT::iPTR); case 'u': // 1 string to match.
break; if (memcmp(NameR.data()+13, ".b", 2))
case Intrinsic::x86_mmx_movnt_dq: // llvm.x86.mmx.movnt.dq break;
VerifyIntrinsicPrototype(ID, IF, 0, 2, MVT::iPTR, MVT::x86mmx); return Intrinsic::x86_sse2_pminu_b; // "86.sse2
break; .pminu.b"
case Intrinsic::ppc_altivec_stvebx: // llvm.ppc.altivec.stvebx }
VerifyIntrinsicPrototype(ID, IF, 0, 2, MVT::v16i8, MVT::iPTR); break;
break; case 'u': // 1 string to match.
case Intrinsic::x86_sse2_maskmov_dqu: // llvm.x86.sse2.mas if (memcmp(NameR.data()+11, "lh.w", 4))
kmov.dqu break;
VerifyIntrinsicPrototype(ID, IF, 0, 3, MVT::v16i8, MVT::v16i8, MVT::iPT return Intrinsic::x86_sse2_pmulh_w; // "86.sse2
R); .pmulh.w"
break; }
case Intrinsic::ppc_altivec_mtvscr: // llvm.ppc.altivec.mtvscr break;
VerifyIntrinsicPrototype(ID, IF, 0, 1, MVT::v4i32); case 's': // 13 strings to match.
break; switch (NameR[10]) {
case Intrinsic::ppc_altivec_stvewx: // llvm.ppc.altivec.stvewx default: break;
case Intrinsic::ppc_altivec_stvx: // llvm.ppc.altivec.stvx case 'a': // 1 string to match.
case Intrinsic::ppc_altivec_stvxl: // llvm.ppc.altivec.stvxl if (memcmp(NameR.data()+11, "d.bw", 4))
VerifyIntrinsicPrototype(ID, IF, 0, 2, MVT::v4i32, MVT::iPTR); break;
break; return Intrinsic::x86_sse2_psad_bw; // "86.sse2
case Intrinsic::ppc_altivec_stvehx: // llvm.ppc.altivec.stvehx .psad.bw"
VerifyIntrinsicPrototype(ID, IF, 0, 2, MVT::v8i16, MVT::iPTR); case 'l': // 4 strings to match.
break; if (NameR[11] != 'l')
case Intrinsic::x86_mmx_maskmovq: // llvm.x86.mmx.maskmovq break;
VerifyIntrinsicPrototype(ID, IF, 0, 3, MVT::x86mmx, MVT::x86mmx, MVT::i switch (NameR[12]) {
PTR); default: break;
break; case '.': // 1 string to match.
case Intrinsic::ptr_annotation: // llvm.ptr.annotation if (memcmp(NameR.data()+13, "dq", 2))
VerifyIntrinsicPrototype(ID, IF, 1, 4, MVT::iPTRAny, ~0, MVT::iPTR, MVT break;
::iPTR, MVT::i32); return Intrinsic::x86_sse2_psll_dq; // "86.sse2
break; .psll.dq"
case Intrinsic::sin: // llvm.sin case 'i': // 3 strings to match.
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::fAny, ~0); if (NameR[13] != '.')
break; break;
case Intrinsic::cos: // llvm.cos switch (NameR[14]) {
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::fAny, ~0); default: break;
break; case 'd': // 1 string to match.
case Intrinsic::pow: // llvm.pow return Intrinsic::x86_sse2_pslli_d; // "86.sse2
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::fAny, ~0, ~0); .pslli.d"
break; case 'q': // 1 string to match.
case Intrinsic::log: // llvm.log return Intrinsic::x86_sse2_pslli_q; // "86.sse2
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::fAny, ~0); .pslli.q"
break; case 'w': // 1 string to match.
case Intrinsic::log10: // llvm.log10 return Intrinsic::x86_sse2_pslli_w; // "86.sse2
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::fAny, ~0); .pslli.w"
break; }
case Intrinsic::log2: // llvm.log2 break;
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::fAny, ~0); }
break; break;
case Intrinsic::exp: // llvm.exp case 'r': // 6 strings to match.
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::fAny, ~0); switch (NameR[11]) {
break; default: break;
case Intrinsic::exp2: // llvm.exp2 case 'a': // 2 strings to match.
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::fAny, ~0); if (memcmp(NameR.data()+12, "i.", 2))
break; break;
case Intrinsic::fma: // llvm.fma switch (NameR[14]) {
VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::fAny, ~0, ~0, ~0); default: break;
break; case 'd': // 1 string to match.
case Intrinsic::sqrt: // llvm.sqrt return Intrinsic::x86_sse2_psrai_d; // "86.sse2
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::fAny, ~0); .psrai.d"
break; case 'w': // 1 string to match.
case Intrinsic::powi: // llvm.powi return Intrinsic::x86_sse2_psrai_w; // "86.sse2
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::fAny, ~0, MVT::i32); .psrai.w"
break; }
case Intrinsic::convertff: // llvm.convertff break;
VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::fAny, MVT::fAny, MVT::i32, case 'l': // 4 strings to match.
MVT::i32); switch (NameR[12]) {
break; default: break;
case Intrinsic::arm_neon_vcvtfxs2fp: // llvm.arm.neon.vcvtfxs2fp case '.': // 1 string to match.
case Intrinsic::arm_neon_vcvtfxu2fp: // llvm.arm.neon.vcvtfxu2fp if (memcmp(NameR.data()+13, "dq", 2))
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::fAny, MVT::iAny, MVT::i32); break;
break; return Intrinsic::x86_sse2_psrl_dq; // "86.sse2
case Intrinsic::convertfsi: // llvm.convertfsi .psrl.dq"
case Intrinsic::convertfui: // llvm.convertfui case 'i': // 3 strings to match.
VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::fAny, MVT::iAny, MVT::i32, if (NameR[13] != '.')
MVT::i32); break;
break; switch (NameR[14]) {
case Intrinsic::expect: // llvm.expect default: break;
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::iAny, ~0, ~0); case 'd': // 1 string to match.
break; return Intrinsic::x86_sse2_psrli_d; // "86.sse2
case Intrinsic::bswap: // llvm.bswap .psrli.d"
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::iAny, ~0); case 'q': // 1 string to match.
break; return Intrinsic::x86_sse2_psrli_q; // "86.sse2
case Intrinsic::ctpop: // llvm.ctpop .psrli.q"
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::iAny, ~0); case 'w': // 1 string to match.
break; return Intrinsic::x86_sse2_psrli_w; // "86.sse2
case Intrinsic::ctlz: // llvm.ctlz .psrli.w"
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::iAny, ~0, MVT::i1); }
break; break;
case Intrinsic::cttz: // llvm.cttz }
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::iAny, ~0, MVT::i1); break;
break; }
case Intrinsic::annotation: // llvm.annotation break;
VerifyIntrinsicPrototype(ID, IF, 1, 4, MVT::iAny, ~0, MVT::iPTR, MVT::i case 'u': // 2 strings to match.
PTR, MVT::i32); if (memcmp(NameR.data()+11, "bs.", 3))
break; break;
case Intrinsic::arm_neon_vcvtfp2fxs: // llvm.arm.neon.vcvtfp2fxs switch (NameR[14]) {
case Intrinsic::arm_neon_vcvtfp2fxu: // llvm.arm.neon.vcvtfp2fxu default: break;
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::iAny, MVT::fAny, MVT::i32); case 'b': // 1 string to match.
break; return Intrinsic::x86_sse2_psubs_b; // "86.sse2
case Intrinsic::convertsif: // llvm.convertsif .psubs.b"
case Intrinsic::convertuif: // llvm.convertuif case 'w': // 1 string to match.
VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::iAny, MVT::fAny, MVT::i32, return Intrinsic::x86_sse2_psubs_w; // "86.sse2
MVT::i32); .psubs.w"
break; }
case Intrinsic::convertss: // llvm.convertss break;
case Intrinsic::convertsu: // llvm.convertsu }
case Intrinsic::convertus: // llvm.convertus break;
case Intrinsic::convertuu: // llvm.convertuu }
VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::iAny, MVT::iAny, MVT::i32, break;
MVT::i32); case 's': // 2 strings to match.
break; if (memcmp(NameR.data()+9, "qrt.", 4))
case Intrinsic::objectsize: // llvm.objectsize break;
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::iAny, MVT::iPTR, MVT::i1); switch (NameR[13]) {
break; default: break;
case Intrinsic::sadd_with_overflow: // llvm.sadd.with.overflow case 'p': // 1 string to match.
VerifyIntrinsicPrototype(ID, IF, 2, 2, MVT::iAny, MVT::i1, ~0, ~0); if (NameR[14] != 'd')
break; break;
case Intrinsic::uadd_with_overflow: // llvm.uadd.with.overflow return Intrinsic::x86_sse2_sqrt_pd; // "86.sse2.sqrt.pd
VerifyIntrinsicPrototype(ID, IF, 2, 2, MVT::iAny, MVT::i1, ~0, ~0); "
break; case 's': // 1 string to match.
case Intrinsic::ssub_with_overflow: // llvm.ssub.with.overflow if (NameR[14] != 'd')
VerifyIntrinsicPrototype(ID, IF, 2, 2, MVT::iAny, MVT::i1, ~0, ~0); break;
break; return Intrinsic::x86_sse2_sqrt_sd; // "86.sse2.sqrt.sd
case Intrinsic::usub_with_overflow: // llvm.usub.with.overflow "
VerifyIntrinsicPrototype(ID, IF, 2, 2, MVT::iAny, MVT::i1, ~0, ~0); }
break; break;
case Intrinsic::smul_with_overflow: // llvm.smul.with.overflow }
VerifyIntrinsicPrototype(ID, IF, 2, 2, MVT::iAny, MVT::i1, ~0, ~0); break;
break; case '3': // 5 strings to match.
case Intrinsic::umul_with_overflow: // llvm.umul.with.overflow if (NameR[7] != '.')
VerifyIntrinsicPrototype(ID, IF, 2, 2, MVT::iAny, MVT::i1, ~0, ~0); break;
break; switch (NameR[8]) {
case Intrinsic::xcore_getst: // llvm.xcore.getst default: break;
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::iPTRAny, MVT::iPTRAny); case 'h': // 4 strings to match.
break; switch (NameR[9]) {
case Intrinsic::xcore_getr: // llvm.xcore.getr default: break;
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::iPTRAny, MVT::i32); case 'a': // 2 strings to match.
break; if (memcmp(NameR.data()+10, "dd.p", 4))
case Intrinsic::arm_neon_vabs: // llvm.arm.neon.vabs break;
case Intrinsic::arm_neon_vcls: // llvm.arm.neon.vcls switch (NameR[14]) {
case Intrinsic::arm_neon_vclz: // llvm.arm.neon.vclz default: break;
case Intrinsic::arm_neon_vcnt: // llvm.arm.neon.vcnt case 'd': // 1 string to match.
case Intrinsic::arm_neon_vqabs: // llvm.arm.neon.vqabs return Intrinsic::x86_sse3_hadd_pd; // "86.sse3
case Intrinsic::arm_neon_vqneg: // llvm.arm.neon.vqneg .hadd.pd"
case Intrinsic::arm_neon_vrecpe: // llvm.arm.neon.vrecpe case 's': // 1 string to match.
case Intrinsic::arm_neon_vrsqrte: // llvm.arm.neon.vrsqrte return Intrinsic::x86_sse3_hadd_ps; // "86.sse3
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::vAny, ~0); .hadd.ps"
break; }
case Intrinsic::arm_neon_vqmovns: // llvm.arm.neon.vqmovns break;
case Intrinsic::arm_neon_vqmovnsu: // llvm.arm.neon.vqmovnsu case 's': // 2 strings to match.
case Intrinsic::arm_neon_vqmovnu: // llvm.arm.neon.vqmovnu if (memcmp(NameR.data()+10, "ub.p", 4))
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::vAny, ~(ExtendedElementVect break;
orType | 0)); switch (NameR[14]) {
break; default: break;
case Intrinsic::arm_neon_vabds: // llvm.arm.neon.vabds case 'd': // 1 string to match.
case Intrinsic::arm_neon_vabdu: // llvm.arm.neon.vabdu return Intrinsic::x86_sse3_hsub_pd; // "86.sse3
case Intrinsic::arm_neon_vhadds: // llvm.arm.neon.vhadds .hsub.pd"
case Intrinsic::arm_neon_vhaddu: // llvm.arm.neon.vhaddu case 's': // 1 string to match.
case Intrinsic::arm_neon_vhsubs: // llvm.arm.neon.vhsubs return Intrinsic::x86_sse3_hsub_ps; // "86.sse3
case Intrinsic::arm_neon_vhsubu: // llvm.arm.neon.vhsubu .hsub.ps"
case Intrinsic::arm_neon_vmaxs: // llvm.arm.neon.vmaxs }
case Intrinsic::arm_neon_vmaxu: // llvm.arm.neon.vmaxu break;
case Intrinsic::arm_neon_vmins: // llvm.arm.neon.vmins }
case Intrinsic::arm_neon_vminu: // llvm.arm.neon.vminu break;
case Intrinsic::arm_neon_vmulp: // llvm.arm.neon.vmulp case 'm': // 1 string to match.
case Intrinsic::arm_neon_vpadd: // llvm.arm.neon.vpadd if (memcmp(NameR.data()+9, "onitor", 6))
case Intrinsic::arm_neon_vpmaxs: // llvm.arm.neon.vpmaxs break;
case Intrinsic::arm_neon_vpmaxu: // llvm.arm.neon.vpmaxu return Intrinsic::x86_sse3_monitor; // "86.sse3.monitor
case Intrinsic::arm_neon_vpmins: // llvm.arm.neon.vpmins "
case Intrinsic::arm_neon_vpminu: // llvm.arm.neon.vpminu }
case Intrinsic::arm_neon_vqadds: // llvm.arm.neon.vqadds break;
case Intrinsic::arm_neon_vqaddu: // llvm.arm.neon.vqaddu case '4': // 15 strings to match.
case Intrinsic::arm_neon_vqdmulh: // llvm.arm.neon.vqdmulh switch (NameR[7]) {
case Intrinsic::arm_neon_vqrdmulh: // llvm.arm.neon.vqrdmulh default: break;
case Intrinsic::arm_neon_vqrshifts: // llvm.arm.neon.vqrshifts case '1': // 14 strings to match.
case Intrinsic::arm_neon_vqrshiftu: // llvm.arm.neon.vqrshiftu if (memcmp(NameR.data()+8, ".p", 2))
case Intrinsic::arm_neon_vqshifts: // llvm.arm.neon.vqshifts break;
case Intrinsic::arm_neon_vqshiftsu: // llvm.arm.neon.vqshiftsu switch (NameR[10]) {
case Intrinsic::arm_neon_vqshiftu: // llvm.arm.neon.vqshiftu default: break;
case Intrinsic::arm_neon_vqsubs: // llvm.arm.neon.vqsubs case 'e': // 3 strings to match.
case Intrinsic::arm_neon_vqsubu: // llvm.arm.neon.vqsubu if (memcmp(NameR.data()+11, "xtr", 3))
case Intrinsic::arm_neon_vrecps: // llvm.arm.neon.vrecps break;
case Intrinsic::arm_neon_vrhadds: // llvm.arm.neon.vrhadds switch (NameR[14]) {
case Intrinsic::arm_neon_vrhaddu: // llvm.arm.neon.vrhaddu default: break;
case Intrinsic::arm_neon_vrshifts: // llvm.arm.neon.vrshifts case 'b': // 1 string to match.
case Intrinsic::arm_neon_vrshiftu: // llvm.arm.neon.vrshiftu return Intrinsic::x86_sse41_pextrb; // "86.sse4
case Intrinsic::arm_neon_vrsqrts: // llvm.arm.neon.vrsqrts 1.pextrb"
case Intrinsic::arm_neon_vshifts: // llvm.arm.neon.vshifts case 'd': // 1 string to match.
case Intrinsic::arm_neon_vshiftu: // llvm.arm.neon.vshiftu return Intrinsic::x86_sse41_pextrd; // "86.sse4
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::vAny, ~0, ~0); 1.pextrd"
break; case 'q': // 1 string to match.
case Intrinsic::arm_neon_vaddhn: // llvm.arm.neon.vaddhn return Intrinsic::x86_sse41_pextrq; // "86.sse4
case Intrinsic::arm_neon_vqrshiftns: // llvm.arm.neon.vqrshiftns 1.pextrq"
case Intrinsic::arm_neon_vqrshiftnsu: // llvm.arm.neon.vqr }
shiftnsu break;
case Intrinsic::arm_neon_vqrshiftnu: // llvm.arm.neon.vqrshiftnu case 'm': // 9 strings to match.
case Intrinsic::arm_neon_vqshiftns: // llvm.arm.neon.vqshiftns switch (NameR[11]) {
case Intrinsic::arm_neon_vqshiftnsu: // llvm.arm.neon.vqshiftnsu default: break;
case Intrinsic::arm_neon_vqshiftnu: // llvm.arm.neon.vqshiftnu case 'a': // 4 strings to match.
case Intrinsic::arm_neon_vraddhn: // llvm.arm.neon.vraddhn if (NameR[12] != 'x')
case Intrinsic::arm_neon_vrshiftn: // llvm.arm.neon.vrshiftn break;
case Intrinsic::arm_neon_vrsubhn: // llvm.arm.neon.vrsubhn switch (NameR[13]) {
case Intrinsic::arm_neon_vshiftn: // llvm.arm.neon.vshiftn default: break;
case Intrinsic::arm_neon_vsubhn: // llvm.arm.neon.vsubhn case 's': // 2 strings to match.
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::vAny, ~(ExtendedElementVect switch (NameR[14]) {
orType | 0), ~(ExtendedElementVectorType | 0)); default: break;
break; case 'b': // 1 string to match.
case Intrinsic::arm_neon_vmullp: // llvm.arm.neon.vmullp return Intrinsic::x86_sse41_pmaxsb; // "86.sse4
case Intrinsic::arm_neon_vmulls: // llvm.arm.neon.vmulls 1.pmaxsb"
case Intrinsic::arm_neon_vmullu: // llvm.arm.neon.vmullu case 'd': // 1 string to match.
case Intrinsic::arm_neon_vqdmull: // llvm.arm.neon.vqdmull return Intrinsic::x86_sse41_pmaxsd; // "86.sse4
case Intrinsic::arm_neon_vshiftls: // llvm.arm.neon.vshiftls 1.pmaxsd"
case Intrinsic::arm_neon_vshiftlu: // llvm.arm.neon.vshiftlu }
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::vAny, ~(TruncatedElementVec break;
torType | 0), ~(TruncatedElementVectorType | 0)); case 'u': // 2 strings to match.
break; switch (NameR[14]) {
case Intrinsic::arm_neon_vshiftins: // llvm.arm.neon.vshiftins default: break;
VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::vAny, ~0, ~0, ~0); case 'd': // 1 string to match.
break; return Intrinsic::x86_sse41_pmaxud; // "86.sse4
case Intrinsic::arm_neon_vqdmlal: // llvm.arm.neon.vqdmlal 1.pmaxud"
case Intrinsic::arm_neon_vqdmlsl: // llvm.arm.neon.vqdmlsl case 'w': // 1 string to match.
VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::vAny, ~0, ~(TruncatedElemen return Intrinsic::x86_sse41_pmaxuw; // "86.sse4
tVectorType | 0), ~(TruncatedElementVectorType | 0)); 1.pmaxuw"
break; }
case Intrinsic::arm_neon_vpadals: // llvm.arm.neon.vpadals break;
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::vAny, ~0, MVT::vAny); }
break; break;
case Intrinsic::arm_neon_vpadalu: // llvm.arm.neon.vpadalu case 'i': // 4 strings to match.
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::vAny, ~0, MVT::vAny); if (NameR[12] != 'n')
break; break;
case Intrinsic::arm_neon_vpaddls: // llvm.arm.neon.vpaddls switch (NameR[13]) {
case Intrinsic::arm_neon_vpaddlu: // llvm.arm.neon.vpaddlu default: break;
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::vAny, MVT::vAny); case 's': // 2 strings to match.
break; switch (NameR[14]) {
case Intrinsic::arm_neon_vld1: // llvm.arm.neon.vld1 default: break;
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::vAny, MVT::iPTR, MVT::i32); case 'b': // 1 string to match.
break; return Intrinsic::x86_sse41_pminsb; // "86.sse4
case Intrinsic::arm_neon_vld2: // llvm.arm.neon.vld2 1.pminsb"
VerifyIntrinsicPrototype(ID, IF, 2, 2, MVT::vAny, ~0, MVT::iPTR, MVT::i case 'd': // 1 string to match.
32); return Intrinsic::x86_sse41_pminsd; // "86.sse4
break; 1.pminsd"
case Intrinsic::arm_neon_vld3: // llvm.arm.neon.vld3 }
VerifyIntrinsicPrototype(ID, IF, 3, 2, MVT::vAny, ~0, ~0, MVT::iPTR, MV break;
T::i32); case 'u': // 2 strings to match.
break; switch (NameR[14]) {
case Intrinsic::arm_neon_vld4: // llvm.arm.neon.vld4 default: break;
VerifyIntrinsicPrototype(ID, IF, 4, 2, MVT::vAny, ~0, ~0, ~0, MVT::iPTR case 'd': // 1 string to match.
, MVT::i32); return Intrinsic::x86_sse41_pminud; // "86.sse4
break; 1.pminud"
case Intrinsic::arm_neon_vld2lane: // llvm.arm.neon.vld2lane case 'w': // 1 string to match.
VerifyIntrinsicPrototype(ID, IF, 2, 5, MVT::vAny, ~0, MVT::iPTR, ~0, ~0 return Intrinsic::x86_sse41_pminuw; // "86.sse4
, MVT::i32, MVT::i32); 1.pminuw"
break; }
case Intrinsic::arm_neon_vld3lane: // llvm.arm.neon.vld3lane break;
VerifyIntrinsicPrototype(ID, IF, 3, 6, MVT::vAny, ~0, ~0, MVT::iPTR, ~0 }
, ~0, ~0, MVT::i32, MVT::i32); break;
break; case 'u': // 1 string to match.
case Intrinsic::arm_neon_vld4lane: // llvm.arm.neon.vld4lane if (memcmp(NameR.data()+12, "ldq", 3))
VerifyIntrinsicPrototype(ID, IF, 4, 7, MVT::vAny, ~0, ~0, ~0, MVT::iPTR break;
, ~0, ~0, ~0, ~0, MVT::i32, MVT::i32); return Intrinsic::x86_sse41_pmuldq; // "86.sse4
break; 1.pmuldq"
case Intrinsic::invariant_start: // llvm.invariant.start }
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::iPTR, MVT::i64, MVT::iPTR); break;
break; case 't': // 2 strings to match.
case Intrinsic::arm_vcvtr: // llvm.arm.vcvtr if (memcmp(NameR.data()+11, "est", 3))
case Intrinsic::arm_vcvtru: // llvm.arm.vcvtru break;
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::f32, MVT::fAny); switch (NameR[14]) {
break; default: break;
case Intrinsic::convert_from_fp16: // llvm.convert.from.fp16 case 'c': // 1 string to match.
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::f32, MVT::i16); return Intrinsic::x86_sse41_ptestc; // "86.sse4
break; 1.ptestc"
case Intrinsic::convert_to_fp16: // llvm.convert.to.fp16 case 'z': // 1 string to match.
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::i16, MVT::f32); return Intrinsic::x86_sse41_ptestz; // "86.sse4
break; 1.ptestz"
case Intrinsic::hexagon_C2_all8: // llvm.hexagon.C2.all8 }
case Intrinsic::hexagon_C2_any8: // llvm.hexagon.C2.any8 break;
case Intrinsic::hexagon_C2_not: // llvm.hexagon.C2.not }
case Intrinsic::hexagon_C2_pxfer_map: // llvm.hexagon.C2.p break;
xfer.map case 'a': // 1 string to match.
case Intrinsic::hexagon_C2_tfrrp: // llvm.hexagon.C2.tfrrp if (memcmp(NameR.data()+8, ".extrqi", 7))
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::i1, MVT::i32); break;
break; return Intrinsic::x86_sse4a_extrqi; // "86.sse4a.extrqi
case Intrinsic::hexagon_C2_and: // llvm.hexagon.C2.and "
case Intrinsic::hexagon_C2_andn: // llvm.hexagon.C2.andn }
case Intrinsic::hexagon_C2_bitsclr: // llvm.hexagon.C2.bitsclr break;
case Intrinsic::hexagon_C2_bitsclri: // llvm.hexagon.C2.bitsclri }
case Intrinsic::hexagon_C2_bitsset: // llvm.hexagon.C2.bitsset break;
case Intrinsic::hexagon_C2_cmpeq: // llvm.hexagon.C2.cmpeq case 's': // 3 strings to match.
case Intrinsic::hexagon_C2_cmpeqi: // llvm.hexagon.C2.cmpeqi if (memcmp(NameR.data()+6, "e3.pabs.", 8))
case Intrinsic::hexagon_C2_cmpgei: // llvm.hexagon.C2.cmpgei break;
case Intrinsic::hexagon_C2_cmpgeui: // llvm.hexagon.C2.cmpgeui switch (NameR[14]) {
case Intrinsic::hexagon_C2_cmpgt: // llvm.hexagon.C2.cmpgt default: break;
case Intrinsic::hexagon_C2_cmpgti: // llvm.hexagon.C2.cmpgti case 'b': // 1 string to match.
case Intrinsic::hexagon_C2_cmpgtu: // llvm.hexagon.C2.cmpgtu return Intrinsic::x86_ssse3_pabs_b; // "86.ssse3.pabs.b
case Intrinsic::hexagon_C2_cmpgtui: // llvm.hexagon.C2.cmpgtui "
case Intrinsic::hexagon_C2_cmplt: // llvm.hexagon.C2.cmplt case 'd': // 1 string to match.
case Intrinsic::hexagon_C2_cmpltu: // llvm.hexagon.C2.cmpltu return Intrinsic::x86_ssse3_pabs_d; // "86.ssse3.pabs.d
case Intrinsic::hexagon_C2_or: // llvm.hexagon.C2.or "
case Intrinsic::hexagon_C2_orn: // llvm.hexagon.C2.orn case 'w': // 1 string to match.
case Intrinsic::hexagon_C2_xor: // llvm.hexagon.C2.xor return Intrinsic::x86_ssse3_pabs_w; // "86.ssse3.pabs.w
case Intrinsic::hexagon_C4_cmplte: // llvm.hexagon.C4.cmplte "
case Intrinsic::hexagon_C4_cmpltei: // llvm.hexagon.C4.cmpltei }
case Intrinsic::hexagon_C4_cmplteu: // llvm.hexagon.C4.cmplteu break;
case Intrinsic::hexagon_C4_cmplteui: // llvm.hexagon.C4.cmplteui }
case Intrinsic::hexagon_C4_cmpneq: // llvm.hexagon.C4.cmpneq break;
case Intrinsic::hexagon_C4_cmpneqi: // llvm.hexagon.C4.cmpneqi case 'x': // 16 strings to match.
case Intrinsic::hexagon_C4_fastcorner9: // llvm.hexagon.C4.f if (memcmp(NameR.data()+4, "op.v", 4))
astcorner9 break;
case Intrinsic::hexagon_C4_fastcorner9_not: // llvm.hexagon.C4.f switch (NameR[8]) {
astcorner9.not default: break;
case Intrinsic::hexagon_S2_tstbit_i: // llvm.hexagon.S2.tstbit.i case 'f': // 4 strings to match.
case Intrinsic::hexagon_S2_tstbit_r: // llvm.hexagon.S2.tstbit.r if (memcmp(NameR.data()+9, "rcz.", 4))
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::i1, MVT::i32, MVT::i32); break;
break; switch (NameR[13]) {
case Intrinsic::hexagon_C4_and_and: // llvm.hexagon.C4.and.and default: break;
case Intrinsic::hexagon_C4_and_andn: // llvm.hexagon.C4.and.andn case 'p': // 2 strings to match.
case Intrinsic::hexagon_C4_and_or: // llvm.hexagon.C4.and.or switch (NameR[14]) {
case Intrinsic::hexagon_C4_and_orn: // llvm.hexagon.C4.and.orn default: break;
case Intrinsic::hexagon_C4_or_and: // llvm.hexagon.C4.or.and case 'd': // 1 string to match.
case Intrinsic::hexagon_C4_or_andn: // llvm.hexagon.C4.or.andn return Intrinsic::x86_xop_vfrcz_pd; // "86.xop.vfrcz.pd
case Intrinsic::hexagon_C4_or_or: // llvm.hexagon.C4.or.or "
case Intrinsic::hexagon_C4_or_orn: // llvm.hexagon.C4.or.orn case 's': // 1 string to match.
VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::i1, MVT::i32, MVT::i32, MVT return Intrinsic::x86_xop_vfrcz_ps; // "86.xop.vfrcz.ps
::i32); "
break; }
case Intrinsic::hexagon_A2_vcmpbeq: // llvm.hexagon.A2.vcmpbeq break;
case Intrinsic::hexagon_A2_vcmpbgtu: // llvm.hexagon.A2.vcmpbgtu case 's': // 2 strings to match.
case Intrinsic::hexagon_A2_vcmpheq: // llvm.hexagon.A2.vcmpheq switch (NameR[14]) {
case Intrinsic::hexagon_A2_vcmphgt: // llvm.hexagon.A2.vcmphgt default: break;
case Intrinsic::hexagon_A2_vcmphgtu: // llvm.hexagon.A2.vcmphgtu case 'd': // 1 string to match.
case Intrinsic::hexagon_A2_vcmpweq: // llvm.hexagon.A2.vcmpweq return Intrinsic::x86_xop_vfrcz_sd; // "86.xop.vfrcz.sd
case Intrinsic::hexagon_A2_vcmpwgt: // llvm.hexagon.A2.vcmpwgt "
case Intrinsic::hexagon_A2_vcmpwgtu: // llvm.hexagon.A2.vcmpwgtu case 's': // 1 string to match.
case Intrinsic::hexagon_C2_cmpeqp: // llvm.hexagon.C2.cmpeqp return Intrinsic::x86_xop_vfrcz_ss; // "86.xop.vfrcz.ss
case Intrinsic::hexagon_C2_cmpgtp: // llvm.hexagon.C2.cmpgtp "
case Intrinsic::hexagon_C2_cmpgtup: // llvm.hexagon.C2.cmpgtup }
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::i1, MVT::i64, MVT::i64); break;
break; }
case Intrinsic::arm_get_fpscr: // llvm.arm.get.fpscr break;
case Intrinsic::flt_rounds: // llvm.flt.rounds case 'p': // 12 strings to match.
case Intrinsic::ptx_read_clock: // llvm.ptx.read.clock switch (NameR[9]) {
case Intrinsic::ptx_read_ctaid_w: // llvm.ptx.read.ctaid.w default: break;
case Intrinsic::ptx_read_ctaid_x: // llvm.ptx.read.ctaid.x case 'h': // 9 strings to match.
case Intrinsic::ptx_read_ctaid_y: // llvm.ptx.read.ctaid.y switch (NameR[10]) {
case Intrinsic::ptx_read_ctaid_z: // llvm.ptx.read.ctaid.z default: break;
case Intrinsic::ptx_read_gridid: // llvm.ptx.read.gridid case 'a': // 6 strings to match.
case Intrinsic::ptx_read_laneid: // llvm.ptx.read.laneid if (memcmp(NameR.data()+11, "dd", 2))
case Intrinsic::ptx_read_lanemask_eq: // llvm.ptx.read.lan break;
emask.eq switch (NameR[13]) {
case Intrinsic::ptx_read_lanemask_ge: // llvm.ptx.read.lan default: break;
emask.ge case 'b': // 3 strings to match.
case Intrinsic::ptx_read_lanemask_gt: // llvm.ptx.read.lan switch (NameR[14]) {
emask.gt default: break;
case Intrinsic::ptx_read_lanemask_le: // llvm.ptx.read.lan case 'd': // 1 string to match.
emask.le return Intrinsic::x86_xop_vphaddbd; // "86.xop.
case Intrinsic::ptx_read_lanemask_lt: // llvm.ptx.read.lan vphaddbd"
emask.lt case 'q': // 1 string to match.
case Intrinsic::ptx_read_nctaid_w: // llvm.ptx.read.nctaid.w return Intrinsic::x86_xop_vphaddbq; // "86.xop.
case Intrinsic::ptx_read_nctaid_x: // llvm.ptx.read.nctaid.x vphaddbq"
case Intrinsic::ptx_read_nctaid_y: // llvm.ptx.read.nctaid.y case 'w': // 1 string to match.
case Intrinsic::ptx_read_nctaid_z: // llvm.ptx.read.nctaid.z return Intrinsic::x86_xop_vphaddbw; // "86.xop.
case Intrinsic::ptx_read_nsmid: // llvm.ptx.read.nsmid vphaddbw"
case Intrinsic::ptx_read_ntid_w: // llvm.ptx.read.ntid.w }
case Intrinsic::ptx_read_ntid_x: // llvm.ptx.read.ntid.x break;
case Intrinsic::ptx_read_ntid_y: // llvm.ptx.read.ntid.y case 'd': // 1 string to match.
case Intrinsic::ptx_read_ntid_z: // llvm.ptx.read.ntid.z if (NameR[14] != 'q')
case Intrinsic::ptx_read_nwarpid: // llvm.ptx.read.nwarpid break;
case Intrinsic::ptx_read_pm0: // llvm.ptx.read.pm0 return Intrinsic::x86_xop_vphadddq; // "86.xop.vphadddq
case Intrinsic::ptx_read_pm1: // llvm.ptx.read.pm1 "
case Intrinsic::ptx_read_pm2: // llvm.ptx.read.pm2 case 'w': // 2 strings to match.
case Intrinsic::ptx_read_pm3: // llvm.ptx.read.pm3 switch (NameR[14]) {
case Intrinsic::ptx_read_smid: // llvm.ptx.read.smid default: break;
case Intrinsic::ptx_read_tid_w: // llvm.ptx.read.tid.w case 'd': // 1 string to match.
case Intrinsic::ptx_read_tid_x: // llvm.ptx.read.tid.x return Intrinsic::x86_xop_vphaddwd; // "86.xop.
case Intrinsic::ptx_read_tid_y: // llvm.ptx.read.tid.y vphaddwd"
case Intrinsic::ptx_read_tid_z: // llvm.ptx.read.tid.z case 'q': // 1 string to match.
case Intrinsic::ptx_read_warpid: // llvm.ptx.read.warpid return Intrinsic::x86_xop_vphaddwq; // "86.xop.
case Intrinsic::x86_rdfsbase_32: // llvm.x86.rdfsbase.32 vphaddwq"
case Intrinsic::x86_rdgsbase_32: // llvm.x86.rdgsbase.32 }
case Intrinsic::xcore_geted: // llvm.xcore.geted break;
case Intrinsic::xcore_getet: // llvm.xcore.getet }
case Intrinsic::xcore_getid: // llvm.xcore.getid break;
VerifyIntrinsicPrototype(ID, IF, 1, 0, MVT::i32); case 's': // 3 strings to match.
break; if (memcmp(NameR.data()+11, "ub", 2))
case Intrinsic::xcore_endin: // llvm.xcore.endin break;
case Intrinsic::xcore_getts: // llvm.xcore.getts switch (NameR[13]) {
case Intrinsic::xcore_in: // llvm.xcore.in default: break;
case Intrinsic::xcore_inct: // llvm.xcore.inct case 'b': // 1 string to match.
case Intrinsic::xcore_int: // llvm.xcore.int if (NameR[14] != 'w')
case Intrinsic::xcore_peek: // llvm.xcore.peek break;
case Intrinsic::xcore_testct: // llvm.xcore.testct return Intrinsic::x86_xop_vphsubbw; // "86.xop.vphsubbw
case Intrinsic::xcore_testwct: // llvm.xcore.testwct "
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::i32, MVT::iPTRAny); case 'd': // 1 string to match.
break; if (NameR[14] != 'q')
case Intrinsic::xcore_inshr: // llvm.xcore.inshr break;
case Intrinsic::xcore_outshr: // llvm.xcore.outshr return Intrinsic::x86_xop_vphsubdq; // "86.xop.vphsubdq
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::i32, MVT::iPTRAny, MVT::i32 "
); case 'w': // 1 string to match.
break; if (NameR[14] != 'd')
case Intrinsic::hexagon_A2_abs: // llvm.hexagon.A2.abs break;
case Intrinsic::hexagon_A2_abssat: // llvm.hexagon.A2.abssat return Intrinsic::x86_xop_vphsubwd; // "86.xop.vphsubwd
case Intrinsic::hexagon_A2_aslh: // llvm.hexagon.A2.aslh "
case Intrinsic::hexagon_A2_asrh: // llvm.hexagon.A2.asrh }
case Intrinsic::hexagon_A2_neg: // llvm.hexagon.A2.neg break;
case Intrinsic::hexagon_A2_negsat: // llvm.hexagon.A2.negsat }
case Intrinsic::hexagon_A2_not: // llvm.hexagon.A2.not break;
case Intrinsic::hexagon_A2_satb: // llvm.hexagon.A2.satb case 'm': // 3 strings to match.
case Intrinsic::hexagon_A2_sath: // llvm.hexagon.A2.sath if (memcmp(NameR.data()+10, "acs", 3))
case Intrinsic::hexagon_A2_satub: // llvm.hexagon.A2.satub break;
case Intrinsic::hexagon_A2_satuh: // llvm.hexagon.A2.satuh switch (NameR[13]) {
case Intrinsic::hexagon_A2_swiz: // llvm.hexagon.A2.swiz default: break;
case Intrinsic::hexagon_A2_sxtb: // llvm.hexagon.A2.sxtb case 'd': // 1 string to match.
case Intrinsic::hexagon_A2_sxth: // llvm.hexagon.A2.sxth if (NameR[14] != 'd')
case Intrinsic::hexagon_A2_tfr: // llvm.hexagon.A2.tfr break;
case Intrinsic::hexagon_A2_tfrsi: // llvm.hexagon.A2.tfrsi return Intrinsic::x86_xop_vpmacsdd; // "86.xop.vpmacsdd
case Intrinsic::hexagon_A2_zxtb: // llvm.hexagon.A2.zxtb "
case Intrinsic::hexagon_A2_zxth: // llvm.hexagon.A2.zxth case 'w': // 2 strings to match.
case Intrinsic::hexagon_C2_tfrpr: // llvm.hexagon.C2.tfrpr switch (NameR[14]) {
case Intrinsic::hexagon_S2_brev: // llvm.hexagon.S2.brev default: break;
case Intrinsic::hexagon_S2_cl0: // llvm.hexagon.S2.cl0 case 'd': // 1 string to match.
case Intrinsic::hexagon_S2_cl1: // llvm.hexagon.S2.cl1 return Intrinsic::x86_xop_vpmacswd; // "86.xop.vpmacswd
case Intrinsic::hexagon_S2_clb: // llvm.hexagon.S2.clb "
case Intrinsic::hexagon_S2_clbnorm: // llvm.hexagon.S2.clbnorm case 'w': // 1 string to match.
case Intrinsic::hexagon_S2_ct0: // llvm.hexagon.S2.ct0 return Intrinsic::x86_xop_vpmacsww; // "86.xop.vpmacsww
case Intrinsic::hexagon_S2_ct1: // llvm.hexagon.S2.ct1 "
case Intrinsic::hexagon_S2_svsathb: // llvm.hexagon.S2.svsathb }
case Intrinsic::hexagon_S2_svsathub: // llvm.hexagon.S2.svsathub break;
case Intrinsic::hexagon_S2_vsplatrb: // llvm.hexagon.S2.vsplatrb }
case Intrinsic::hexagon_SI_to_SXTHI_asrh: // llvm.hexagon.SI.t break;
o.SXTHI.asrh }
case Intrinsic::xcore_bitrev: // llvm.xcore.bitrev break;
case Intrinsic::xcore_getps: // llvm.xcore.getps }
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::i32, MVT::i32); break;
break; }
case Intrinsic::x86_sse42_crc32_32_16: // llvm.x86.sse42.cr break;
c32.32.16 case 'c': // 1 string to match.
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::i32, MVT::i32, MVT::i16); if (memcmp(NameR.data()+1, "ore.checkevent", 14))
break; break;
case Intrinsic::arm_qadd: // llvm.arm.qadd return Intrinsic::xcore_checkevent; // "core.checkevent"
case Intrinsic::arm_qsub: // llvm.arm.qsub }
case Intrinsic::arm_ssat: // llvm.arm.ssat break;
case Intrinsic::arm_usat: // llvm.arm.usat case 16: // 112 strings to match.
case Intrinsic::hexagon_A2_add: // llvm.hexagon.A2.add if (memcmp(NameR.data()+0, "86.", 3))
case Intrinsic::hexagon_A2_addh_h16_hh: // llvm.hexagon.A2.a break;
ddh.h16.hh switch (NameR[3]) {
case Intrinsic::hexagon_A2_addh_h16_hl: // llvm.hexagon.A2.a default: break;
ddh.h16.hl case '3': // 8 strings to match.
case Intrinsic::hexagon_A2_addh_h16_lh: // llvm.hexagon.A2.a if (memcmp(NameR.data()+4, "dnow", 4))
ddh.h16.lh break;
case Intrinsic::hexagon_A2_addh_h16_ll: // llvm.hexagon.A2.a switch (NameR[8]) {
ddh.h16.ll default: break;
case Intrinsic::hexagon_A2_addh_h16_sat_hh: // llvm.hexagon.A2.a case '.': // 6 strings to match.
ddh.h16.sat.hh if (NameR[9] != 'p')
case Intrinsic::hexagon_A2_addh_h16_sat_hl: // llvm.hexagon.A2.a break;
ddh.h16.sat.hl switch (NameR[10]) {
case Intrinsic::hexagon_A2_addh_h16_sat_lh: // llvm.hexagon.A2.a default: break;
ddh.h16.sat.lh case 'a': // 1 string to match.
case Intrinsic::hexagon_A2_addh_h16_sat_ll: // llvm.hexagon.A2.a if (memcmp(NameR.data()+11, "vgusb", 5))
ddh.h16.sat.ll break;
case Intrinsic::hexagon_A2_addh_l16_hh: // llvm.hexagon.A2.a return Intrinsic::x86_3dnow_pavgusb; // "86.3dnow.pavgus
ddh.l16.hh b"
case Intrinsic::hexagon_A2_addh_l16_hl: // llvm.hexagon.A2.a case 'f': // 4 strings to match.
ddh.l16.hl switch (NameR[11]) {
case Intrinsic::hexagon_A2_addh_l16_lh: // llvm.hexagon.A2.a default: break;
ddh.l16.lh case 'c': // 3 strings to match.
case Intrinsic::hexagon_A2_addh_l16_ll: // llvm.hexagon.A2.a if (memcmp(NameR.data()+12, "mp", 2))
ddh.l16.ll break;
case Intrinsic::hexagon_A2_addh_l16_sat_hh: // llvm.hexagon.A2.a switch (NameR[14]) {
ddh.l16.sat.hh default: break;
case Intrinsic::hexagon_A2_addh_l16_sat_hl: // llvm.hexagon.A2.a case 'e': // 1 string to match.
ddh.l16.sat.hl if (NameR[15] != 'q')
case Intrinsic::hexagon_A2_addh_l16_sat_lh: // llvm.hexagon.A2.a break;
ddh.l16.sat.lh return Intrinsic::x86_3dnow_pfcmpeq; // "86.3dnow.pfcmpe
case Intrinsic::hexagon_A2_addh_l16_sat_ll: // llvm.hexagon.A2.a q"
ddh.l16.sat.ll case 'g': // 2 strings to match.
case Intrinsic::hexagon_A2_addi: // llvm.hexagon.A2.addi switch (NameR[15]) {
case Intrinsic::hexagon_A2_addsat: // llvm.hexagon.A2.addsat default: break;
case Intrinsic::hexagon_A2_and: // llvm.hexagon.A2.and case 'e': // 1 string to match.
case Intrinsic::hexagon_A2_andir: // llvm.hexagon.A2.andir return Intrinsic::x86_3dnow_pfcmpge; // "86.3dnow.pfcmpg
case Intrinsic::hexagon_A2_combine_hh: // llvm.hexagon.A2.c e"
ombine.hh case 't': // 1 string to match.
case Intrinsic::hexagon_A2_combine_hl: // llvm.hexagon.A2.c return Intrinsic::x86_3dnow_pfcmpgt; // "86.3dnow.pfcmpg
ombine.hl t"
case Intrinsic::hexagon_A2_combine_lh: // llvm.hexagon.A2.c }
ombine.lh break;
case Intrinsic::hexagon_A2_combine_ll: // llvm.hexagon.A2.c }
ombine.ll break;
case Intrinsic::hexagon_A2_max: // llvm.hexagon.A2.max case 'r': // 1 string to match.
case Intrinsic::hexagon_A2_maxu: // llvm.hexagon.A2.maxu if (memcmp(NameR.data()+12, "sqrt", 4))
case Intrinsic::hexagon_A2_min: // llvm.hexagon.A2.min break;
case Intrinsic::hexagon_A2_minu: // llvm.hexagon.A2.minu return Intrinsic::x86_3dnow_pfrsqrt; // "86.3dnow.pfrsqr
case Intrinsic::hexagon_A2_or: // llvm.hexagon.A2.or t"
case Intrinsic::hexagon_A2_orir: // llvm.hexagon.A2.orir }
case Intrinsic::hexagon_A2_sub: // llvm.hexagon.A2.sub break;
case Intrinsic::hexagon_A2_subh_h16_hh: // llvm.hexagon.A2.s case 'm': // 1 string to match.
ubh.h16.hh if (memcmp(NameR.data()+11, "ulhrw", 5))
case Intrinsic::hexagon_A2_subh_h16_hl: // llvm.hexagon.A2.s break;
ubh.h16.hl return Intrinsic::x86_3dnow_pmulhrw; // "86.3dnow.pmulhr
case Intrinsic::hexagon_A2_subh_h16_lh: // llvm.hexagon.A2.s w"
ubh.h16.lh }
case Intrinsic::hexagon_A2_subh_h16_ll: // llvm.hexagon.A2.s break;
ubh.h16.ll case 'a': // 2 strings to match.
case Intrinsic::hexagon_A2_subh_h16_sat_hh: // llvm.hexagon.A2.s if (memcmp(NameR.data()+9, ".p", 2))
ubh.h16.sat.hh break;
case Intrinsic::hexagon_A2_subh_h16_sat_hl: // llvm.hexagon.A2.s switch (NameR[11]) {
ubh.h16.sat.hl default: break;
case Intrinsic::hexagon_A2_subh_h16_sat_lh: // llvm.hexagon.A2.s case 'f': // 1 string to match.
ubh.h16.sat.lh if (memcmp(NameR.data()+12, "nacc", 4))
case Intrinsic::hexagon_A2_subh_h16_sat_ll: // llvm.hexagon.A2.s break;
ubh.h16.sat.ll return Intrinsic::x86_3dnowa_pfnacc; // "86.3dnowa.pfnac
case Intrinsic::hexagon_A2_subh_l16_hl: // llvm.hexagon.A2.s c"
ubh.l16.hl case 's': // 1 string to match.
case Intrinsic::hexagon_A2_subh_l16_ll: // llvm.hexagon.A2.s if (memcmp(NameR.data()+12, "wapd", 4))
ubh.l16.ll break;
case Intrinsic::hexagon_A2_subh_l16_sat_hl: // llvm.hexagon.A2.s return Intrinsic::x86_3dnowa_pswapd; // "86.3dnowa.pswap
ubh.l16.sat.hl d"
case Intrinsic::hexagon_A2_subh_l16_sat_ll: // llvm.hexagon.A2.s }
ubh.l16.sat.ll break;
case Intrinsic::hexagon_A2_subri: // llvm.hexagon.A2.subri }
case Intrinsic::hexagon_A2_subsat: // llvm.hexagon.A2.subsat break;
case Intrinsic::hexagon_A2_svaddh: // llvm.hexagon.A2.svaddh case 'a': // 33 strings to match.
case Intrinsic::hexagon_A2_svaddhs: // llvm.hexagon.A2.svaddhs if (memcmp(NameR.data()+4, "vx", 2))
case Intrinsic::hexagon_A2_svadduhs: // llvm.hexagon.A2.svadduhs break;
case Intrinsic::hexagon_A2_svavgh: // llvm.hexagon.A2.svavgh switch (NameR[6]) {
case Intrinsic::hexagon_A2_svavghs: // llvm.hexagon.A2.svavghs default: break;
case Intrinsic::hexagon_A2_svnavgh: // llvm.hexagon.A2.svnavgh case '.': // 5 strings to match.
case Intrinsic::hexagon_A2_svsubh: // llvm.hexagon.A2.svsubh switch (NameR[7]) {
case Intrinsic::hexagon_A2_svsubhs: // llvm.hexagon.A2.svsubhs default: break;
case Intrinsic::hexagon_A2_svsubuhs: // llvm.hexagon.A2.svsubuhs case 'd': // 1 string to match.
case Intrinsic::hexagon_A2_tfrih: // llvm.hexagon.A2.tfrih if (memcmp(NameR.data()+8, "p.ps.256", 8))
case Intrinsic::hexagon_A2_tfril: // llvm.hexagon.A2.tfril break;
case Intrinsic::hexagon_A2_xor: // llvm.hexagon.A2.xor return Intrinsic::x86_avx_dp_ps_256; // "86.avx.dp.ps.25
case Intrinsic::hexagon_A4_andn: // llvm.hexagon.A4.andn 6"
case Intrinsic::hexagon_A4_cround_ri: // llvm.hexagon.A4.c case 'v': // 4 strings to match.
round.ri if (memcmp(NameR.data()+8, "test", 4))
case Intrinsic::hexagon_A4_cround_rr: // llvm.hexagon.A4.c break;
round.rr switch (NameR[12]) {
case Intrinsic::hexagon_A4_modwrapu: // llvm.hexagon.A4.modwrapu default: break;
case Intrinsic::hexagon_A4_orn: // llvm.hexagon.A4.orn case 'c': // 2 strings to match.
case Intrinsic::hexagon_A4_rcmpeq: // llvm.hexagon.A4.rcmpeq if (memcmp(NameR.data()+13, ".p", 2))
case Intrinsic::hexagon_A4_rcmpeqi: // llvm.hexagon.A4.rcmpeqi break;
case Intrinsic::hexagon_A4_rcmpneq: // llvm.hexagon.A4.rcmpneq switch (NameR[15]) {
case Intrinsic::hexagon_A4_rcmpneqi: // llvm.hexagon.A4.rcmpneqi default: break;
case Intrinsic::hexagon_A4_round_ri: // llvm.hexagon.A4.round.ri case 'd': // 1 string to match.
case Intrinsic::hexagon_A4_round_ri_sat: // llvm.hexagon.A4.r return Intrinsic::x86_avx_vtestc_pd; // "86.avx.vtestc.p
ound.ri.sat d"
case Intrinsic::hexagon_A4_round_rr: // llvm.hexagon.A4.round.rr case 's': // 1 string to match.
case Intrinsic::hexagon_A4_round_rr_sat: // llvm.hexagon.A4.r return Intrinsic::x86_avx_vtestc_ps; // "86.avx.vtestc.p
ound.rr.sat s"
case Intrinsic::hexagon_C2_vitpack: // llvm.hexagon.C2.vitpack }
case Intrinsic::hexagon_M2_cmpyrs_s0: // llvm.hexagon.M2.c break;
mpyrs.s0 case 'z': // 2 strings to match.
case Intrinsic::hexagon_M2_cmpyrs_s1: // llvm.hexagon.M2.c if (memcmp(NameR.data()+13, ".p", 2))
mpyrs.s1 break;
case Intrinsic::hexagon_M2_cmpyrsc_s0: // llvm.hexagon.M2.c switch (NameR[15]) {
mpyrsc.s0 default: break;
case Intrinsic::hexagon_M2_cmpyrsc_s1: // llvm.hexagon.M2.c case 'd': // 1 string to match.
mpyrsc.s1 return Intrinsic::x86_avx_vtestz_pd; // "86.avx.vtestz.p
case Intrinsic::hexagon_M2_dpmpyss_rnd_s0: // llvm.hexagon.M2.d d"
pmpyss.rnd.s0 case 's': // 1 string to match.
case Intrinsic::hexagon_M2_hmmpyh_rs1: // llvm.hexagon.M2.h return Intrinsic::x86_avx_vtestz_ps; // "86.avx.vtestz.p
mmpyh.rs1 s"
case Intrinsic::hexagon_M2_hmmpyl_rs1: // llvm.hexagon.M2.h }
mmpyl.rs1 break;
case Intrinsic::hexagon_M2_mpy_hh_s0: // llvm.hexagon.M2.m }
py.hh.s0 break;
case Intrinsic::hexagon_M2_mpy_hh_s1: // llvm.hexagon.M2.m }
py.hh.s1 break;
case Intrinsic::hexagon_M2_mpy_hl_s0: // llvm.hexagon.M2.m case '2': // 28 strings to match.
py.hl.s0 if (NameR[7] != '.')
case Intrinsic::hexagon_M2_mpy_hl_s1: // llvm.hexagon.M2.m break;
py.hl.s1 switch (NameR[8]) {
case Intrinsic::hexagon_M2_mpy_lh_s0: // llvm.hexagon.M2.m default: break;
py.lh.s0 case 'm': // 1 string to match.
case Intrinsic::hexagon_M2_mpy_lh_s1: // llvm.hexagon.M2.m if (memcmp(NameR.data()+9, "ovntdqa", 7))
py.lh.s1 break;
case Intrinsic::hexagon_M2_mpy_ll_s0: // llvm.hexagon.M2.m return Intrinsic::x86_avx2_movntdqa; // "86.avx2.movntdq
py.ll.s0 a"
case Intrinsic::hexagon_M2_mpy_ll_s1: // llvm.hexagon.M2.m case 'p': // 27 strings to match.
py.ll.s1 switch (NameR[9]) {
case Intrinsic::hexagon_M2_mpy_rnd_hh_s0: // llvm.hexagon.M2.m default: break;
py.rnd.hh.s0 case 'a': // 6 strings to match.
case Intrinsic::hexagon_M2_mpy_rnd_hh_s1: // llvm.hexagon.M2.m switch (NameR[10]) {
py.rnd.hh.s1 default: break;
case Intrinsic::hexagon_M2_mpy_rnd_hl_s0: // llvm.hexagon.M2.m case 'c': // 4 strings to match.
py.rnd.hl.s0 if (NameR[11] != 'k')
case Intrinsic::hexagon_M2_mpy_rnd_hl_s1: // llvm.hexagon.M2.m break;
py.rnd.hl.s1 switch (NameR[12]) {
case Intrinsic::hexagon_M2_mpy_rnd_lh_s0: // llvm.hexagon.M2.m default: break;
py.rnd.lh.s0 case 's': // 2 strings to match.
case Intrinsic::hexagon_M2_mpy_rnd_lh_s1: // llvm.hexagon.M2.m if (NameR[13] != 's')
py.rnd.lh.s1 break;
case Intrinsic::hexagon_M2_mpy_rnd_ll_s0: // llvm.hexagon.M2.m switch (NameR[14]) {
py.rnd.ll.s0 default: break;
case Intrinsic::hexagon_M2_mpy_rnd_ll_s1: // llvm.hexagon.M2.m case 'd': // 1 string to match.
py.rnd.ll.s1 if (NameR[15] != 'w')
case Intrinsic::hexagon_M2_mpy_sat_hh_s0: // llvm.hexagon.M2.m break;
py.sat.hh.s0 return Intrinsic::x86_avx2_packssdw; // "86.avx2
case Intrinsic::hexagon_M2_mpy_sat_hh_s1: // llvm.hexagon.M2.m .packssdw"
py.sat.hh.s1 case 'w': // 1 string to match.
case Intrinsic::hexagon_M2_mpy_sat_hl_s0: // llvm.hexagon.M2.m if (NameR[15] != 'b')
py.sat.hl.s0 break;
case Intrinsic::hexagon_M2_mpy_sat_hl_s1: // llvm.hexagon.M2.m return Intrinsic::x86_avx2_packsswb; // "86.avx2
py.sat.hl.s1 .packsswb"
case Intrinsic::hexagon_M2_mpy_sat_lh_s0: // llvm.hexagon.M2.m }
py.sat.lh.s0 break;
case Intrinsic::hexagon_M2_mpy_sat_lh_s1: // llvm.hexagon.M2.m case 'u': // 2 strings to match.
py.sat.lh.s1 if (NameR[13] != 's')
case Intrinsic::hexagon_M2_mpy_sat_ll_s0: // llvm.hexagon.M2.m break;
py.sat.ll.s0 switch (NameR[14]) {
case Intrinsic::hexagon_M2_mpy_sat_ll_s1: // llvm.hexagon.M2.m default: break;
py.sat.ll.s1 case 'd': // 1 string to match.
case Intrinsic::hexagon_M2_mpy_sat_rnd_hh_s0: // llvm.hexa if (NameR[15] != 'w')
gon.M2.mpy.sat.rnd.hh.s0 break;
case Intrinsic::hexagon_M2_mpy_sat_rnd_hh_s1: // llvm.hexa return Intrinsic::x86_avx2_packusdw; // "86.avx2
gon.M2.mpy.sat.rnd.hh.s1 .packusdw"
case Intrinsic::hexagon_M2_mpy_sat_rnd_hl_s0: // llvm.hexa case 'w': // 1 string to match.
gon.M2.mpy.sat.rnd.hl.s0 if (NameR[15] != 'b')
case Intrinsic::hexagon_M2_mpy_sat_rnd_hl_s1: // llvm.hexa break;
gon.M2.mpy.sat.rnd.hl.s1 return Intrinsic::x86_avx2_packuswb; // "86.avx2
case Intrinsic::hexagon_M2_mpy_sat_rnd_lh_s0: // llvm.hexa .packuswb"
gon.M2.mpy.sat.rnd.lh.s0 }
case Intrinsic::hexagon_M2_mpy_sat_rnd_lh_s1: // llvm.hexa break;
gon.M2.mpy.sat.rnd.lh.s1 }
case Intrinsic::hexagon_M2_mpy_sat_rnd_ll_s0: // llvm.hexa break;
gon.M2.mpy.sat.rnd.ll.s0 case 'd': // 2 strings to match.
case Intrinsic::hexagon_M2_mpy_sat_rnd_ll_s1: // llvm.hexa if (memcmp(NameR.data()+11, "dus.", 4))
gon.M2.mpy.sat.rnd.ll.s1 break;
case Intrinsic::hexagon_M2_mpy_up: // llvm.hexagon.M2.mpy.up switch (NameR[15]) {
case Intrinsic::hexagon_M2_mpyi: // llvm.hexagon.M2.mpyi default: break;
case Intrinsic::hexagon_M2_mpysmi: // llvm.hexagon.M2.mpysmi case 'b': // 1 string to match.
case Intrinsic::hexagon_M2_mpyu_hh_s0: // llvm.hexagon.M2.m return Intrinsic::x86_avx2_paddus_b; // "86.avx2.paddus.
pyu.hh.s0 b"
case Intrinsic::hexagon_M2_mpyu_hh_s1: // llvm.hexagon.M2.m case 'w': // 1 string to match.
pyu.hh.s1 return Intrinsic::x86_avx2_paddus_w; // "86.avx2.paddus.
case Intrinsic::hexagon_M2_mpyu_hl_s0: // llvm.hexagon.M2.m w"
pyu.hl.s0 }
case Intrinsic::hexagon_M2_mpyu_hl_s1: // llvm.hexagon.M2.m break;
pyu.hl.s1 }
case Intrinsic::hexagon_M2_mpyu_lh_s0: // llvm.hexagon.M2.m break;
pyu.lh.s0 case 'b': // 1 string to match.
case Intrinsic::hexagon_M2_mpyu_lh_s1: // llvm.hexagon.M2.m if (memcmp(NameR.data()+10, "lendvb", 6))
pyu.lh.s1 break;
case Intrinsic::hexagon_M2_mpyu_ll_s0: // llvm.hexagon.M2.m return Intrinsic::x86_avx2_pblendvb; // "86.avx2.pblendv
pyu.ll.s0 b"
case Intrinsic::hexagon_M2_mpyu_ll_s1: // llvm.hexagon.M2.m case 'h': // 2 strings to match.
pyu.ll.s1 switch (NameR[10]) {
case Intrinsic::hexagon_M2_mpyu_up: // llvm.hexagon.M2.mpyu.up default: break;
case Intrinsic::hexagon_M2_mpyui: // llvm.hexagon.M2.mpyui case 'a': // 1 string to match.
case Intrinsic::hexagon_M2_vmpy2s_s0pack: // llvm.hexagon.M2.v if (memcmp(NameR.data()+11, "dd.sw", 5))
mpy2s.s0pack break;
case Intrinsic::hexagon_M2_vmpy2s_s1pack: // llvm.hexagon.M2.v return Intrinsic::x86_avx2_phadd_sw; // "86.avx2.phadd.s
mpy2s.s1pack w"
case Intrinsic::hexagon_S2_asl_i_r: // llvm.hexagon.S2.asl.i.r case 's': // 1 string to match.
case Intrinsic::hexagon_S2_asl_i_r_sat: // llvm.hexagon.S2.a if (memcmp(NameR.data()+11, "ub.sw", 5))
sl.i.r.sat break;
case Intrinsic::hexagon_S2_asl_r_r: // llvm.hexagon.S2.asl.r.r return Intrinsic::x86_avx2_phsub_sw; // "86.avx2.phsub.s
case Intrinsic::hexagon_S2_asl_r_r_sat: // llvm.hexagon.S2.a w"
sl.r.r.sat }
case Intrinsic::hexagon_S2_asr_i_r: // llvm.hexagon.S2.asr.i.r break;
case Intrinsic::hexagon_S2_asr_i_r_rnd: // llvm.hexagon.S2.a case 'm': // 16 strings to match.
sr.i.r.rnd switch (NameR[10]) {
case Intrinsic::hexagon_S2_asr_i_r_rnd_goodsyntax: // llvm.hexa default: break;
gon.S2.asr.i.r.rnd.goodsyntax case 'a': // 1 string to match.
case Intrinsic::hexagon_S2_asr_r_r: // llvm.hexagon.S2.asr.r.r if (memcmp(NameR.data()+11, "dd.wd", 5))
case Intrinsic::hexagon_S2_asr_r_r_sat: // llvm.hexagon.S2.a break;
sr.r.r.sat return Intrinsic::x86_avx2_pmadd_wd; // "86.avx2.pmadd.w
case Intrinsic::hexagon_S2_clrbit_i: // llvm.hexagon.S2.clrbit.i d"
case Intrinsic::hexagon_S2_clrbit_r: // llvm.hexagon.S2.clrbit.r case 'o': // 13 strings to match.
case Intrinsic::hexagon_S2_lsl_r_r: // llvm.hexagon.S2.lsl.r.r if (NameR[11] != 'v')
case Intrinsic::hexagon_S2_lsr_i_r: // llvm.hexagon.S2.lsr.i.r break;
case Intrinsic::hexagon_S2_lsr_r_r: // llvm.hexagon.S2.lsr.r.r switch (NameR[12]) {
case Intrinsic::hexagon_S2_setbit_i: // llvm.hexagon.S2.setbit.i default: break;
case Intrinsic::hexagon_S2_setbit_r: // llvm.hexagon.S2.setbit.r case 'm': // 1 string to match.
case Intrinsic::hexagon_S2_togglebit_i: // llvm.hexagon.S2.t if (memcmp(NameR.data()+13, "skb", 3))
ogglebit.i break;
case Intrinsic::hexagon_S2_togglebit_r: // llvm.hexagon.S2.t return Intrinsic::x86_avx2_pmovmskb; // "86.avx2.pmovmsk
ogglebit.r b"
case Intrinsic::x86_bmi_bextr_32: // llvm.x86.bmi.bextr.32 case 's': // 6 strings to match.
case Intrinsic::x86_bmi_bzhi_32: // llvm.x86.bmi.bzhi.32 if (NameR[13] != 'x')
case Intrinsic::x86_bmi_pdep_32: // llvm.x86.bmi.pdep.32 break;
case Intrinsic::x86_bmi_pext_32: // llvm.x86.bmi.pext.32 switch (NameR[14]) {
case Intrinsic::x86_sse42_crc32_32_32: // llvm.x86.sse42.cr default: break;
c32.32.32 case 'b': // 3 strings to match.
case Intrinsic::xcore_sext: // llvm.xcore.sext switch (NameR[15]) {
case Intrinsic::xcore_zext: // llvm.xcore.zext default: break;
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::i32, MVT::i32, MVT::i32); case 'd': // 1 string to match.
break; return Intrinsic::x86_avx2_pmovsxbd; // "86.avx2
case Intrinsic::hexagon_C2_mux: // llvm.hexagon.C2.mux .pmovsxbd"
case Intrinsic::hexagon_C2_muxii: // llvm.hexagon.C2.muxii case 'q': // 1 string to match.
case Intrinsic::hexagon_C2_muxir: // llvm.hexagon.C2.muxir return Intrinsic::x86_avx2_pmovsxbq; // "86.avx2
case Intrinsic::hexagon_C2_muxri: // llvm.hexagon.C2.muxri .pmovsxbq"
case Intrinsic::hexagon_M2_acci: // llvm.hexagon.M2.acci case 'w': // 1 string to match.
case Intrinsic::hexagon_M2_accii: // llvm.hexagon.M2.accii return Intrinsic::x86_avx2_pmovsxbw; // "86.avx2
case Intrinsic::hexagon_M2_maci: // llvm.hexagon.M2.maci .pmovsxbw"
case Intrinsic::hexagon_M2_macsin: // llvm.hexagon.M2.macsin }
case Intrinsic::hexagon_M2_macsip: // llvm.hexagon.M2.macsip break;
case Intrinsic::hexagon_M2_mpy_acc_hh_s0: // llvm.hexagon.M2.m case 'd': // 1 string to match.
py.acc.hh.s0 if (NameR[15] != 'q')
case Intrinsic::hexagon_M2_mpy_acc_hh_s1: // llvm.hexagon.M2.m break;
py.acc.hh.s1 return Intrinsic::x86_avx2_pmovsxdq; // "86.avx2
case Intrinsic::hexagon_M2_mpy_acc_hl_s0: // llvm.hexagon.M2.m .pmovsxdq"
py.acc.hl.s0 case 'w': // 2 strings to match.
case Intrinsic::hexagon_M2_mpy_acc_hl_s1: // llvm.hexagon.M2.m switch (NameR[15]) {
py.acc.hl.s1 default: break;
case Intrinsic::hexagon_M2_mpy_acc_lh_s0: // llvm.hexagon.M2.m case 'd': // 1 string to match.
py.acc.lh.s0 return Intrinsic::x86_avx2_pmovsxwd; // "86.avx2
case Intrinsic::hexagon_M2_mpy_acc_lh_s1: // llvm.hexagon.M2.m .pmovsxwd"
py.acc.lh.s1 case 'q': // 1 string to match.
case Intrinsic::hexagon_M2_mpy_acc_ll_s0: // llvm.hexagon.M2.m return Intrinsic::x86_avx2_pmovsxwq; // "86.avx2
py.acc.ll.s0 .pmovsxwq"
case Intrinsic::hexagon_M2_mpy_acc_ll_s1: // llvm.hexagon.M2.m }
py.acc.ll.s1 break;
case Intrinsic::hexagon_M2_mpy_acc_sat_hh_s0: // llvm.hexa }
gon.M2.mpy.acc.sat.hh.s0 break;
case Intrinsic::hexagon_M2_mpy_acc_sat_hh_s1: // llvm.hexa case 'z': // 6 strings to match.
gon.M2.mpy.acc.sat.hh.s1 if (NameR[13] != 'x')
case Intrinsic::hexagon_M2_mpy_acc_sat_hl_s0: // llvm.hexa break;
gon.M2.mpy.acc.sat.hl.s0 switch (NameR[14]) {
case Intrinsic::hexagon_M2_mpy_acc_sat_hl_s1: // llvm.hexa default: break;
gon.M2.mpy.acc.sat.hl.s1 case 'b': // 3 strings to match.
case Intrinsic::hexagon_M2_mpy_acc_sat_lh_s0: // llvm.hexa switch (NameR[15]) {
gon.M2.mpy.acc.sat.lh.s0 default: break;
case Intrinsic::hexagon_M2_mpy_acc_sat_lh_s1: // llvm.hexa case 'd': // 1 string to match.
gon.M2.mpy.acc.sat.lh.s1 return Intrinsic::x86_avx2_pmovzxbd; // "86.avx2
case Intrinsic::hexagon_M2_mpy_acc_sat_ll_s0: // llvm.hexa .pmovzxbd"
gon.M2.mpy.acc.sat.ll.s0 case 'q': // 1 string to match.
case Intrinsic::hexagon_M2_mpy_acc_sat_ll_s1: // llvm.hexa return Intrinsic::x86_avx2_pmovzxbq; // "86.avx2
gon.M2.mpy.acc.sat.ll.s1 .pmovzxbq"
case Intrinsic::hexagon_M2_mpy_nac_hh_s0: // llvm.hexagon.M2.m case 'w': // 1 string to match.
py.nac.hh.s0 return Intrinsic::x86_avx2_pmovzxbw; // "86.avx2
case Intrinsic::hexagon_M2_mpy_nac_hh_s1: // llvm.hexagon.M2.m .pmovzxbw"
py.nac.hh.s1 }
case Intrinsic::hexagon_M2_mpy_nac_hl_s0: // llvm.hexagon.M2.m break;
py.nac.hl.s0 case 'd': // 1 string to match.
case Intrinsic::hexagon_M2_mpy_nac_hl_s1: // llvm.hexagon.M2.m if (NameR[15] != 'q')
py.nac.hl.s1 break;
case Intrinsic::hexagon_M2_mpy_nac_lh_s0: // llvm.hexagon.M2.m return Intrinsic::x86_avx2_pmovzxdq; // "86.avx2
py.nac.lh.s0 .pmovzxdq"
case Intrinsic::hexagon_M2_mpy_nac_lh_s1: // llvm.hexagon.M2.m case 'w': // 2 strings to match.
py.nac.lh.s1 switch (NameR[15]) {
case Intrinsic::hexagon_M2_mpy_nac_ll_s0: // llvm.hexagon.M2.m default: break;
py.nac.ll.s0 case 'd': // 1 string to match.
case Intrinsic::hexagon_M2_mpy_nac_ll_s1: // llvm.hexagon.M2.m return Intrinsic::x86_avx2_pmovzxwd; // "86.avx2
py.nac.ll.s1 .pmovzxwd"
case Intrinsic::hexagon_M2_mpy_nac_sat_hh_s0: // llvm.hexa case 'q': // 1 string to match.
gon.M2.mpy.nac.sat.hh.s0 return Intrinsic::x86_avx2_pmovzxwq; // "86.avx2
case Intrinsic::hexagon_M2_mpy_nac_sat_hh_s1: // llvm.hexa .pmovzxwq"
gon.M2.mpy.nac.sat.hh.s1 }
case Intrinsic::hexagon_M2_mpy_nac_sat_hl_s0: // llvm.hexa break;
gon.M2.mpy.nac.sat.hl.s0 }
case Intrinsic::hexagon_M2_mpy_nac_sat_hl_s1: // llvm.hexa break;
gon.M2.mpy.nac.sat.hl.s1 }
case Intrinsic::hexagon_M2_mpy_nac_sat_lh_s0: // llvm.hexa break;
gon.M2.mpy.nac.sat.lh.s0 case 'u': // 2 strings to match.
case Intrinsic::hexagon_M2_mpy_nac_sat_lh_s1: // llvm.hexa if (NameR[11] != 'l')
gon.M2.mpy.nac.sat.lh.s1 break;
case Intrinsic::hexagon_M2_mpy_nac_sat_ll_s0: // llvm.hexa switch (NameR[12]) {
gon.M2.mpy.nac.sat.ll.s0 default: break;
case Intrinsic::hexagon_M2_mpy_nac_sat_ll_s1: // llvm.hexa case 'h': // 1 string to match.
gon.M2.mpy.nac.sat.ll.s1 if (memcmp(NameR.data()+13, "u.w", 3))
case Intrinsic::hexagon_M2_mpyu_acc_hh_s0: // llvm.hexagon.M2.m break;
pyu.acc.hh.s0 return Intrinsic::x86_avx2_pmulhu_w; // "86.avx2.pmulhu.
case Intrinsic::hexagon_M2_mpyu_acc_hh_s1: // llvm.hexagon.M2.m w"
pyu.acc.hh.s1 case 'u': // 1 string to match.
case Intrinsic::hexagon_M2_mpyu_acc_hl_s0: // llvm.hexagon.M2.m if (memcmp(NameR.data()+13, ".dq", 3))
pyu.acc.hl.s0 break;
case Intrinsic::hexagon_M2_mpyu_acc_hl_s1: // llvm.hexagon.M2.m return Intrinsic::x86_avx2_pmulu_dq; // "86.avx2.pmulu.d
pyu.acc.hl.s1 q"
case Intrinsic::hexagon_M2_mpyu_acc_lh_s0: // llvm.hexagon.M2.m }
pyu.acc.lh.s0 break;
case Intrinsic::hexagon_M2_mpyu_acc_lh_s1: // llvm.hexagon.M2.m }
pyu.acc.lh.s1 break;
case Intrinsic::hexagon_M2_mpyu_acc_ll_s0: // llvm.hexagon.M2.m case 's': // 2 strings to match.
pyu.acc.ll.s0 if (memcmp(NameR.data()+10, "ubus.", 5))
case Intrinsic::hexagon_M2_mpyu_acc_ll_s1: // llvm.hexagon.M2.m break;
pyu.acc.ll.s1 switch (NameR[15]) {
case Intrinsic::hexagon_M2_mpyu_nac_hh_s0: // llvm.hexagon.M2.m default: break;
pyu.nac.hh.s0 case 'b': // 1 string to match.
case Intrinsic::hexagon_M2_mpyu_nac_hh_s1: // llvm.hexagon.M2.m return Intrinsic::x86_avx2_psubus_b; // "86.avx2.psubus.
pyu.nac.hh.s1 b"
case Intrinsic::hexagon_M2_mpyu_nac_hl_s0: // llvm.hexagon.M2.m case 'w': // 1 string to match.
pyu.nac.hl.s0 return Intrinsic::x86_avx2_psubus_w; // "86.avx2.psubus.
case Intrinsic::hexagon_M2_mpyu_nac_hl_s1: // llvm.hexagon.M2.m w"
pyu.nac.hl.s1 }
case Intrinsic::hexagon_M2_mpyu_nac_lh_s0: // llvm.hexagon.M2.m break;
pyu.nac.lh.s0 }
case Intrinsic::hexagon_M2_mpyu_nac_lh_s1: // llvm.hexagon.M2.m break;
pyu.nac.lh.s1 }
case Intrinsic::hexagon_M2_mpyu_nac_ll_s0: // llvm.hexagon.M2.m break;
pyu.nac.ll.s0 }
case Intrinsic::hexagon_M2_mpyu_nac_ll_s1: // llvm.hexagon.M2.m break;
pyu.nac.ll.s1 case 'f': // 8 strings to match.
case Intrinsic::hexagon_M2_nacci: // llvm.hexagon.M2.nacci if (memcmp(NameR.data()+4, "ma.vfm", 6))
case Intrinsic::hexagon_M2_naccii: // llvm.hexagon.M2.naccii break;
case Intrinsic::hexagon_M2_subacc: // llvm.hexagon.M2.subacc switch (NameR[10]) {
case Intrinsic::hexagon_M2_xor_xacc: // llvm.hexagon.M2.xor.xacc default: break;
case Intrinsic::hexagon_M4_and_and: // llvm.hexagon.M4.and.and case 'a': // 4 strings to match.
case Intrinsic::hexagon_M4_and_andn: // llvm.hexagon.M4.and.andn if (memcmp(NameR.data()+11, "dd.", 3))
case Intrinsic::hexagon_M4_and_or: // llvm.hexagon.M4.and.or break;
case Intrinsic::hexagon_M4_and_xor: // llvm.hexagon.M4.and.xor switch (NameR[14]) {
case Intrinsic::hexagon_M4_or_and: // llvm.hexagon.M4.or.and default: break;
case Intrinsic::hexagon_M4_or_andn: // llvm.hexagon.M4.or.andn case 'p': // 2 strings to match.
case Intrinsic::hexagon_M4_or_or: // llvm.hexagon.M4.or.or switch (NameR[15]) {
case Intrinsic::hexagon_M4_or_xor: // llvm.hexagon.M4.or.xor default: break;
case Intrinsic::hexagon_M4_xor_and: // llvm.hexagon.M4.xor.and case 'd': // 1 string to match.
case Intrinsic::hexagon_M4_xor_andn: // llvm.hexagon.M4.xor.andn return Intrinsic::x86_fma_vfmadd_pd; // "86.fma.vfmadd.p
case Intrinsic::hexagon_M4_xor_or: // llvm.hexagon.M4.xor.or d"
case Intrinsic::hexagon_S2_addasl_rrri: // llvm.hexagon.S2.a case 's': // 1 string to match.
ddasl.rrri return Intrinsic::x86_fma_vfmadd_ps; // "86.fma.vfmadd.p
case Intrinsic::hexagon_S2_asl_i_r_acc: // llvm.hexagon.S2.a s"
sl.i.r.acc }
case Intrinsic::hexagon_S2_asl_i_r_and: // llvm.hexagon.S2.a break;
sl.i.r.and case 's': // 2 strings to match.
case Intrinsic::hexagon_S2_asl_i_r_nac: // llvm.hexagon.S2.a switch (NameR[15]) {
sl.i.r.nac default: break;
case Intrinsic::hexagon_S2_asl_i_r_or: // llvm.hexagon.S2.a case 'd': // 1 string to match.
sl.i.r.or return Intrinsic::x86_fma_vfmadd_sd; // "86.fma.vfmadd.s
case Intrinsic::hexagon_S2_asl_i_r_xacc: // llvm.hexagon.S2.a d"
sl.i.r.xacc case 's': // 1 string to match.
case Intrinsic::hexagon_S2_asl_r_r_acc: // llvm.hexagon.S2.a return Intrinsic::x86_fma_vfmadd_ss; // "86.fma.vfmadd.s
sl.r.r.acc s"
case Intrinsic::hexagon_S2_asl_r_r_and: // llvm.hexagon.S2.a }
sl.r.r.and break;
case Intrinsic::hexagon_S2_asl_r_r_nac: // llvm.hexagon.S2.a }
sl.r.r.nac break;
case Intrinsic::hexagon_S2_asl_r_r_or: // llvm.hexagon.S2.a case 's': // 4 strings to match.
sl.r.r.or if (memcmp(NameR.data()+11, "ub.", 3))
case Intrinsic::hexagon_S2_asr_i_r_acc: // llvm.hexagon.S2.a break;
sr.i.r.acc switch (NameR[14]) {
case Intrinsic::hexagon_S2_asr_i_r_and: // llvm.hexagon.S2.a default: break;
sr.i.r.and case 'p': // 2 strings to match.
case Intrinsic::hexagon_S2_asr_i_r_nac: // llvm.hexagon.S2.a switch (NameR[15]) {
sr.i.r.nac default: break;
case Intrinsic::hexagon_S2_asr_i_r_or: // llvm.hexagon.S2.a case 'd': // 1 string to match.
sr.i.r.or return Intrinsic::x86_fma_vfmsub_pd; // "86.fma.vfmsub.p
case Intrinsic::hexagon_S2_asr_r_r_acc: // llvm.hexagon.S2.a d"
sr.r.r.acc case 's': // 1 string to match.
case Intrinsic::hexagon_S2_asr_r_r_and: // llvm.hexagon.S2.a return Intrinsic::x86_fma_vfmsub_ps; // "86.fma.vfmsub.p
sr.r.r.and s"
case Intrinsic::hexagon_S2_asr_r_r_nac: // llvm.hexagon.S2.a }
sr.r.r.nac break;
case Intrinsic::hexagon_S2_asr_r_r_or: // llvm.hexagon.S2.a case 's': // 2 strings to match.
sr.r.r.or switch (NameR[15]) {
case Intrinsic::hexagon_S2_extractu: // llvm.hexagon.S2.extractu default: break;
case Intrinsic::hexagon_S2_lsl_r_r_acc: // llvm.hexagon.S2.l case 'd': // 1 string to match.
sl.r.r.acc return Intrinsic::x86_fma_vfmsub_sd; // "86.fma.vfmsub.s
case Intrinsic::hexagon_S2_lsl_r_r_and: // llvm.hexagon.S2.l d"
sl.r.r.and case 's': // 1 string to match.
case Intrinsic::hexagon_S2_lsl_r_r_nac: // llvm.hexagon.S2.l return Intrinsic::x86_fma_vfmsub_ss; // "86.fma.vfmsub.s
sl.r.r.nac s"
case Intrinsic::hexagon_S2_lsl_r_r_or: // llvm.hexagon.S2.l }
sl.r.r.or break;
case Intrinsic::hexagon_S2_lsr_i_r_acc: // llvm.hexagon.S2.l }
sr.i.r.acc break;
case Intrinsic::hexagon_S2_lsr_i_r_and: // llvm.hexagon.S2.l }
sr.i.r.and break;
case Intrinsic::hexagon_S2_lsr_i_r_nac: // llvm.hexagon.S2.l case 'm': // 7 strings to match.
sr.i.r.nac if (memcmp(NameR.data()+4, "mx.p", 4))
case Intrinsic::hexagon_S2_lsr_i_r_or: // llvm.hexagon.S2.l break;
sr.i.r.or switch (NameR[8]) {
case Intrinsic::hexagon_S2_lsr_i_r_xacc: // llvm.hexagon.S2.l default: break;
sr.i.r.xacc case 'a': // 1 string to match.
case Intrinsic::hexagon_S2_lsr_r_r_acc: // llvm.hexagon.S2.l if (memcmp(NameR.data()+9, "lignr.b", 7))
sr.r.r.acc break;
case Intrinsic::hexagon_S2_lsr_r_r_and: // llvm.hexagon.S2.l return Intrinsic::x86_mmx_palignr_b; // "86.mmx.palignr.b"
sr.r.r.and case 'u': // 6 strings to match.
case Intrinsic::hexagon_S2_lsr_r_r_nac: // llvm.hexagon.S2.l if (memcmp(NameR.data()+9, "npck", 4))
sr.r.r.nac break;
case Intrinsic::hexagon_S2_lsr_r_r_or: // llvm.hexagon.S2.l switch (NameR[13]) {
sr.r.r.or default: break;
case Intrinsic::hexagon_S4_addaddi: // llvm.hexagon.S4.addaddi case 'h': // 3 strings to match.
case Intrinsic::hexagon_S4_or_andi: // llvm.hexagon.S4.or.andi switch (NameR[14]) {
case Intrinsic::hexagon_S4_or_andix: // llvm.hexagon.S4.or.andix default: break;
case Intrinsic::hexagon_S4_or_ori: // llvm.hexagon.S4.or.ori case 'b': // 1 string to match.
case Intrinsic::hexagon_S4_subaddi: // llvm.hexagon.S4.subaddi if (NameR[15] != 'w')
case Intrinsic::xcore_crc32: // llvm.xcore.crc32 break;
VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::i32, MVT::i32, MVT::i32, MV return Intrinsic::x86_mmx_punpckhbw; // "86.mmx.punpckhb
T::i32); w"
break; case 'd': // 1 string to match.
case Intrinsic::hexagon_S2_insert: // llvm.hexagon.S2.insert if (NameR[15] != 'q')
case Intrinsic::hexagon_S2_tableidxb_goodsyntax: // llvm.hexa break;
gon.S2.tableidxb.goodsyntax return Intrinsic::x86_mmx_punpckhdq; // "86.mmx.punpckhd
case Intrinsic::hexagon_S2_tableidxd_goodsyntax: // llvm.hexa q"
gon.S2.tableidxd.goodsyntax case 'w': // 1 string to match.
case Intrinsic::hexagon_S2_tableidxh_goodsyntax: // llvm.hexa if (NameR[15] != 'd')
gon.S2.tableidxh.goodsyntax break;
case Intrinsic::hexagon_S2_tableidxw_goodsyntax: // llvm.hexa return Intrinsic::x86_mmx_punpckhwd; // "86.mmx.punpckhw
gon.S2.tableidxw.goodsyntax d"
VerifyIntrinsicPrototype(ID, IF, 1, 4, MVT::i32, MVT::i32, MVT::i32, MV }
T::i32, MVT::i32); break;
break; case 'l': // 3 strings to match.
case Intrinsic::arm_mrc: // llvm.arm.mrc switch (NameR[14]) {
case Intrinsic::arm_mrc2: // llvm.arm.mrc2 default: break;
VerifyIntrinsicPrototype(ID, IF, 1, 5, MVT::i32, MVT::i32, MVT::i32, MV case 'b': // 1 string to match.
T::i32, MVT::i32, MVT::i32); if (NameR[15] != 'w')
break; break;
case Intrinsic::hexagon_S2_insert_rp: // llvm.hexagon.S2.i return Intrinsic::x86_mmx_punpcklbw; // "86.mmx.punpcklb
nsert.rp w"
VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::i32, MVT::i32, MVT::i32, MV case 'd': // 1 string to match.
T::i64); if (NameR[15] != 'q')
break; break;
case Intrinsic::arm_strexd: // llvm.arm.strexd return Intrinsic::x86_mmx_punpckldq; // "86.mmx.punpckld
VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::i32, MVT::i32, MVT::i32, MV q"
T::iPTR); case 'w': // 1 string to match.
break; if (NameR[15] != 'd')
case Intrinsic::hexagon_S2_extractu_rp: // llvm.hexagon.S2.e break;
xtractu.rp return Intrinsic::x86_mmx_punpcklwd; // "86.mmx.punpcklw
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::i32, MVT::i32, MVT::i64); d"
break; }
case Intrinsic::x86_sse42_crc32_32_8: // llvm.x86.sse42.cr break;
c32.32.8 }
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::i32, MVT::i32, MVT::i8); break;
break; }
case Intrinsic::ppc_altivec_vcmpequb_p: // llvm.ppc.altivec. break;
vcmpequb.p case 's': // 40 strings to match.
case Intrinsic::ppc_altivec_vcmpgtsb_p: // llvm.ppc.altivec. if (NameR[4] != 's')
vcmpgtsb.p break;
case Intrinsic::ppc_altivec_vcmpgtub_p: // llvm.ppc.altivec. switch (NameR[5]) {
vcmpgtub.p default: break;
VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::i32, MVT::i32, MVT::v16i8, case 'e': // 32 strings to match.
MVT::v16i8); switch (NameR[6]) {
break; default: break;
case Intrinsic::ppc_altivec_vcmpbfp_p: // llvm.ppc.altivec. case '.': // 10 strings to match.
vcmpbfp.p switch (NameR[7]) {
case Intrinsic::ppc_altivec_vcmpeqfp_p: // llvm.ppc.altivec. default: break;
vcmpeqfp.p case 'c': // 8 strings to match.
case Intrinsic::ppc_altivec_vcmpgefp_p: // llvm.ppc.altivec. switch (NameR[8]) {
vcmpgefp.p default: break;
case Intrinsic::ppc_altivec_vcmpgtfp_p: // llvm.ppc.altivec. case 'o': // 5 strings to match.
vcmpgtfp.p if (memcmp(NameR.data()+9, "mi", 2))
VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::i32, MVT::i32, MVT::v4f32, break;
MVT::v4f32); switch (NameR[11]) {
break; default: break;
case Intrinsic::ppc_altivec_vcmpequw_p: // llvm.ppc.altivec. case 'e': // 1 string to match.
vcmpequw.p if (memcmp(NameR.data()+12, "q.ss", 4))
case Intrinsic::ppc_altivec_vcmpgtsw_p: // llvm.ppc.altivec. break;
vcmpgtsw.p return Intrinsic::x86_sse_comieq_ss; // "86.sse.comieq.s
case Intrinsic::ppc_altivec_vcmpgtuw_p: // llvm.ppc.altivec. s"
vcmpgtuw.p case 'g': // 2 strings to match.
VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::i32, MVT::i32, MVT::v4i32, switch (NameR[12]) {
MVT::v4i32); default: break;
break; case 'e': // 1 string to match.
case Intrinsic::ppc_altivec_vcmpequh_p: // llvm.ppc.altivec. if (memcmp(NameR.data()+13, ".ss", 3))
vcmpequh.p break;
case Intrinsic::ppc_altivec_vcmpgtsh_p: // llvm.ppc.altivec. return Intrinsic::x86_sse_comige_ss; // "86.sse.
vcmpgtsh.p comige.ss"
case Intrinsic::ppc_altivec_vcmpgtuh_p: // llvm.ppc.altivec. case 't': // 1 string to match.
vcmpgtuh.p if (memcmp(NameR.data()+13, ".ss", 3))
VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::i32, MVT::i32, MVT::v8i16, break;
MVT::v8i16); return Intrinsic::x86_sse_comigt_ss; // "86.sse.
break; comigt.ss"
case Intrinsic::hexagon_A2_sat: // llvm.hexagon.A2.sat }
case Intrinsic::hexagon_S2_cl0p: // llvm.hexagon.S2.cl0p break;
case Intrinsic::hexagon_S2_cl1p: // llvm.hexagon.S2.cl1p case 'l': // 2 strings to match.
case Intrinsic::hexagon_S2_clbp: // llvm.hexagon.S2.clbp switch (NameR[12]) {
case Intrinsic::hexagon_S2_vrndpackwh: // llvm.hexagon.S2.v default: break;
rndpackwh case 'e': // 1 string to match.
case Intrinsic::hexagon_S2_vrndpackwhs: // llvm.hexagon.S2.v if (memcmp(NameR.data()+13, ".ss", 3))
rndpackwhs break;
case Intrinsic::hexagon_S2_vsathb: // llvm.hexagon.S2.vsathb return Intrinsic::x86_sse_comile_ss; // "86.sse.
case Intrinsic::hexagon_S2_vsathub: // llvm.hexagon.S2.vsathub comile.ss"
case Intrinsic::hexagon_S2_vsatwh: // llvm.hexagon.S2.vsatwh case 't': // 1 string to match.
case Intrinsic::hexagon_S2_vsatwuh: // llvm.hexagon.S2.vsatwuh if (memcmp(NameR.data()+13, ".ss", 3))
case Intrinsic::hexagon_S2_vtrunehb: // llvm.hexagon.S2.vtrunehb break;
case Intrinsic::hexagon_S2_vtrunohb: // llvm.hexagon.S2.vtrunohb return Intrinsic::x86_sse_comilt_ss; // "86.sse.
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::i32, MVT::i64); comilt.ss"
break; }
case Intrinsic::hexagon_M2_vrcmpys_s1rp: // llvm.hexagon.M2.v break;
rcmpys.s1rp }
case Intrinsic::hexagon_S2_asr_i_svw_trun: // llvm.hexagon.S2.a break;
sr.i.svw.trun case 'v': // 3 strings to match.
case Intrinsic::hexagon_S2_asr_r_svw_trun: // llvm.hexagon.S2.a if (memcmp(NameR.data()+9, "tt", 2))
sr.r.svw.trun break;
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::i32, MVT::i64, MVT::i32); switch (NameR[11]) {
break; default: break;
case Intrinsic::hexagon_M2_vdmpyrs_s0: // llvm.hexagon.M2.v case 'p': // 2 strings to match.
dmpyrs.s0 switch (NameR[12]) {
case Intrinsic::hexagon_M2_vdmpyrs_s1: // llvm.hexagon.M2.v default: break;
dmpyrs.s1 case 'd': // 1 string to match.
case Intrinsic::hexagon_M2_vradduh: // llvm.hexagon.M2.vradduh if (memcmp(NameR.data()+13, "2pi", 3))
case Intrinsic::hexagon_S2_parityp: // llvm.hexagon.S2.parityp break;
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::i32, MVT::i64, MVT::i64); return Intrinsic::x86_sse_cvttpd2pi; // "86.sse.
break; cvttpd2pi"
case Intrinsic::eh_sjlj_setjmp: // llvm.eh.sjlj.setjmp case 's': // 1 string to match.
case Intrinsic::eh_typeid_for: // llvm.eh.typeid.for if (memcmp(NameR.data()+13, "2pi", 3))
case Intrinsic::setjmp: // llvm.setjmp break;
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::i32, MVT::iPTR); return Intrinsic::x86_sse_cvttps2pi; // "86.sse.
break; cvttps2pi"
case Intrinsic::sigsetjmp: // llvm.sigsetjmp }
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::i32, MVT::iPTR, MVT::i32); break;
break; case 's': // 1 string to match.
case Intrinsic::x86_sse2_pmovmskb_128: // llvm.x86.sse2.pmo if (memcmp(NameR.data()+12, "s2si", 4))
vmskb.128 break;
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::i32, MVT::v16i8); return Intrinsic::x86_sse_cvttss2si; // "86.sse.cvttss2s
break; i"
case Intrinsic::x86_sse41_pextrb: // llvm.x86.sse41.pextrb }
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::i32, MVT::v16i8, MVT::i32); break;
break; }
case Intrinsic::x86_sse42_pcmpestri128: // llvm.x86.sse42.pc break;
mpestri128 case 'm': // 1 string to match.
case Intrinsic::x86_sse42_pcmpestria128: // llvm.x86.sse42.pc if (memcmp(NameR.data()+8, "ovmsk.ps", 8))
mpestria128 break;
case Intrinsic::x86_sse42_pcmpestric128: // llvm.x86.sse42.pc return Intrinsic::x86_sse_movmsk_ps; // "86.sse.movmsk.p
mpestric128 s"
case Intrinsic::x86_sse42_pcmpestrio128: // llvm.x86.sse42.pc case 's': // 1 string to match.
mpestrio128 if (memcmp(NameR.data()+8, "toreu.ps", 8))
case Intrinsic::x86_sse42_pcmpestris128: // llvm.x86.sse42.pc break;
mpestris128 return Intrinsic::x86_sse_storeu_ps; // "86.sse.storeu.p
case Intrinsic::x86_sse42_pcmpestriz128: // llvm.x86.sse42.pc s"
mpestriz128 }
VerifyIntrinsicPrototype(ID, IF, 1, 5, MVT::i32, MVT::v16i8, MVT::i32, break;
MVT::v16i8, MVT::i32, MVT::i8); case '2': // 17 strings to match.
break; if (NameR[7] != '.')
case Intrinsic::x86_sse42_pcmpistri128: // llvm.x86.sse42.pc break;
mpistri128 switch (NameR[8]) {
case Intrinsic::x86_sse42_pcmpistria128: // llvm.x86.sse42.pc default: break;
mpistria128 case 'c': // 10 strings to match.
case Intrinsic::x86_sse42_pcmpistric128: // llvm.x86.sse42.pc if (memcmp(NameR.data()+9, "vt", 2))
mpistric128 break;
case Intrinsic::x86_sse42_pcmpistrio128: // llvm.x86.sse42.pc switch (NameR[11]) {
mpistrio128 default: break;
case Intrinsic::x86_sse42_pcmpistris128: // llvm.x86.sse42.pc case 'd': // 2 strings to match.
mpistris128 if (memcmp(NameR.data()+12, "q2p", 3))
case Intrinsic::x86_sse42_pcmpistriz128: // llvm.x86.sse42.pc break;
mpistriz128 switch (NameR[15]) {
VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::i32, MVT::v16i8, MVT::v16i8 default: break;
, MVT::i8); case 'd': // 1 string to match.
break; return Intrinsic::x86_sse2_cvtdq2pd; // "86.sse2.cvtdq2p
case Intrinsic::x86_sse2_cvtsd2si: // llvm.x86.sse2.cvtsd2si d"
case Intrinsic::x86_sse2_cvttsd2si: // llvm.x86.sse2.cvttsd2si case 's': // 1 string to match.
case Intrinsic::x86_sse2_movmsk_pd: // llvm.x86.sse2.movmsk.pd return Intrinsic::x86_sse2_cvtdq2ps; // "86.sse2.cvtdq2p
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::i32, MVT::v2f64); s"
break; }
case Intrinsic::x86_avx_vtestc_pd: // llvm.x86.avx.vtestc.pd break;
case Intrinsic::x86_avx_vtestnzc_pd: // llvm.x86.avx.vtestnzc.pd case 'p': // 4 strings to match.
case Intrinsic::x86_avx_vtestz_pd: // llvm.x86.avx.vtestz.pd switch (NameR[12]) {
case Intrinsic::x86_sse2_comieq_sd: // llvm.x86.sse2.comieq.sd default: break;
case Intrinsic::x86_sse2_comige_sd: // llvm.x86.sse2.comige.sd case 'd': // 2 strings to match.
case Intrinsic::x86_sse2_comigt_sd: // llvm.x86.sse2.comigt.sd if (NameR[13] != '2')
case Intrinsic::x86_sse2_comile_sd: // llvm.x86.sse2.comile.sd break;
case Intrinsic::x86_sse2_comilt_sd: // llvm.x86.sse2.comilt.sd switch (NameR[14]) {
case Intrinsic::x86_sse2_comineq_sd: // llvm.x86.sse2.comineq.sd default: break;
case Intrinsic::x86_sse2_ucomieq_sd: // llvm.x86.sse2.ucomieq.sd case 'd': // 1 string to match.
case Intrinsic::x86_sse2_ucomige_sd: // llvm.x86.sse2.ucomige.sd if (NameR[15] != 'q')
case Intrinsic::x86_sse2_ucomigt_sd: // llvm.x86.sse2.ucomigt.sd break;
case Intrinsic::x86_sse2_ucomile_sd: // llvm.x86.sse2.ucomile.sd return Intrinsic::x86_sse2_cvtpd2dq; // "86.sse2
case Intrinsic::x86_sse2_ucomilt_sd: // llvm.x86.sse2.ucomilt.sd .cvtpd2dq"
case Intrinsic::x86_sse2_ucomineq_sd: // llvm.x86.sse2.uco case 'p': // 1 string to match.
mineq.sd if (NameR[15] != 's')
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::i32, MVT::v2f64, MVT::v2f64 break;
); return Intrinsic::x86_sse2_cvtpd2ps; // "86.sse2
break; .cvtpd2ps"
case Intrinsic::x86_sse41_ptestc: // llvm.x86.sse41.ptestc }
case Intrinsic::x86_sse41_ptestnzc: // llvm.x86.sse41.ptestnzc break;
case Intrinsic::x86_sse41_ptestz: // llvm.x86.sse41.ptestz case 's': // 2 strings to match.
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::i32, MVT::v2i64, MVT::v2i64 if (NameR[13] != '2')
); break;
break; switch (NameR[14]) {
case Intrinsic::x86_avx2_pmovmskb: // llvm.x86.avx2.pmovmskb default: break;
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::i32, MVT::v32i8); case 'd': // 1 string to match.
break; if (NameR[15] != 'q')
case Intrinsic::x86_sse_cvtss2si: // llvm.x86.sse.cvtss2si break;
case Intrinsic::x86_sse_cvttss2si: // llvm.x86.sse.cvttss2si return Intrinsic::x86_sse2_cvtps2dq; // "86.sse2
case Intrinsic::x86_sse_movmsk_ps: // llvm.x86.sse.movmsk.ps .cvtps2dq"
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::i32, MVT::v4f32); case 'p': // 1 string to match.
break; if (NameR[15] != 'd')
case Intrinsic::x86_sse41_extractps: // llvm.x86.sse41.extractps break;
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::i32, MVT::v4f32, MVT::i32); return Intrinsic::x86_sse2_cvtps2pd; // "86.sse2
break; .cvtps2pd"
case Intrinsic::x86_avx_vtestc_ps: // llvm.x86.avx.vtestc.ps }
case Intrinsic::x86_avx_vtestnzc_ps: // llvm.x86.avx.vtestnzc.ps break;
case Intrinsic::x86_avx_vtestz_ps: // llvm.x86.avx.vtestz.ps }
case Intrinsic::x86_sse_comieq_ss: // llvm.x86.sse.comieq.ss break;
case Intrinsic::x86_sse_comige_ss: // llvm.x86.sse.comige.ss case 's': // 4 strings to match.
case Intrinsic::x86_sse_comigt_ss: // llvm.x86.sse.comigt.ss switch (NameR[12]) {
case Intrinsic::x86_sse_comile_ss: // llvm.x86.sse.comile.ss default: break;
case Intrinsic::x86_sse_comilt_ss: // llvm.x86.sse.comilt.ss case 'd': // 2 strings to match.
case Intrinsic::x86_sse_comineq_ss: // llvm.x86.sse.comineq.ss if (memcmp(NameR.data()+13, "2s", 2))
case Intrinsic::x86_sse_ucomieq_ss: // llvm.x86.sse.ucomieq.ss break;
case Intrinsic::x86_sse_ucomige_ss: // llvm.x86.sse.ucomige.ss switch (NameR[15]) {
case Intrinsic::x86_sse_ucomigt_ss: // llvm.x86.sse.ucomigt.ss default: break;
case Intrinsic::x86_sse_ucomile_ss: // llvm.x86.sse.ucomile.ss case 'i': // 1 string to match.
case Intrinsic::x86_sse_ucomilt_ss: // llvm.x86.sse.ucomilt.ss return Intrinsic::x86_sse2_cvtsd2si; // "86.sse2
case Intrinsic::x86_sse_ucomineq_ss: // llvm.x86.sse.ucomineq.ss .cvtsd2si"
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::i32, MVT::v4f32, MVT::v4f32 case 's': // 1 string to match.
); return Intrinsic::x86_sse2_cvtsd2ss; // "86.sse2
break; .cvtsd2ss"
case Intrinsic::x86_avx_movmsk_pd_256: // llvm.x86.avx.movm }
sk.pd.256 break;
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::i32, MVT::v4f64); case 'i': // 1 string to match.
break; if (memcmp(NameR.data()+13, "2sd", 3))
case Intrinsic::x86_avx_vtestc_pd_256: // llvm.x86.avx.vtes break;
tc.pd.256 return Intrinsic::x86_sse2_cvtsi2sd; // "86.sse2.cvtsi2s
case Intrinsic::x86_avx_vtestnzc_pd_256: // llvm.x86.avx.vtes d"
tnzc.pd.256 case 's': // 1 string to match.
case Intrinsic::x86_avx_vtestz_pd_256: // llvm.x86.avx.vtes if (memcmp(NameR.data()+13, "2sd", 3))
tz.pd.256 break;
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::i32, MVT::v4f64, MVT::v4f64 return Intrinsic::x86_sse2_cvtss2sd; // "86.sse2.cvtss2s
); d"
break; }
case Intrinsic::x86_sse41_pextrd: // llvm.x86.sse41.pextrd break;
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::i32, MVT::v4i32, MVT::i32); }
break; break;
case Intrinsic::x86_avx_ptestc_256: // llvm.x86.avx.ptestc.256 case 'p': // 7 strings to match.
case Intrinsic::x86_avx_ptestnzc_256: // llvm.x86.avx.ptes switch (NameR[9]) {
tnzc.256 default: break;
case Intrinsic::x86_avx_ptestz_256: // llvm.x86.avx.ptestz.256 case 'a': // 2 strings to match.
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::i32, MVT::v4i64, MVT::v4i64 if (memcmp(NameR.data()+10, "ddus.", 5))
); break;
break; switch (NameR[15]) {
case Intrinsic::x86_avx_movmsk_ps_256: // llvm.x86.avx.movm default: break;
sk.ps.256 case 'b': // 1 string to match.
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::i32, MVT::v8f32); return Intrinsic::x86_sse2_paddus_b; // "86.sse2.paddus.
break; b"
case Intrinsic::x86_avx_vtestc_ps_256: // llvm.x86.avx.vtes case 'w': // 1 string to match.
tc.ps.256 return Intrinsic::x86_sse2_paddus_w; // "86.sse2.paddus.
case Intrinsic::x86_avx_vtestnzc_ps_256: // llvm.x86.avx.vtes w"
tnzc.ps.256 }
case Intrinsic::x86_avx_vtestz_ps_256: // llvm.x86.avx.vtes break;
tz.ps.256 case 'm': // 3 strings to match.
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::i32, MVT::v8f32, MVT::v8f32 switch (NameR[10]) {
); default: break;
break; case 'a': // 1 string to match.
case Intrinsic::x86_mmx_pmovmskb: // llvm.x86.mmx.pmovmskb if (memcmp(NameR.data()+11, "dd.wd", 5))
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::i32, MVT::x86mmx); break;
break; return Intrinsic::x86_sse2_pmadd_wd; // "86.sse2.pmadd.w
case Intrinsic::x86_mmx_pextr_w: // llvm.x86.mmx.pextr.w d"
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::i32, MVT::x86mmx, MVT::i32) case 'u': // 2 strings to match.
; if (NameR[11] != 'l')
break; break;
case Intrinsic::xcore_crc8: // llvm.xcore.crc8 switch (NameR[12]) {
VerifyIntrinsicPrototype(ID, IF, 2, 3, MVT::i32, MVT::i32, MVT::i32, MV default: break;
T::i32, MVT::i32); case 'h': // 1 string to match.
break; if (memcmp(NameR.data()+13, "u.w", 3))
case Intrinsic::arm_ldrexd: // llvm.arm.ldrexd break;
VerifyIntrinsicPrototype(ID, IF, 2, 1, MVT::i32, MVT::i32, MVT::iPTR); return Intrinsic::x86_sse2_pmulhu_w; // "86.sse2
break; .pmulhu.w"
case Intrinsic::ptx_read_clock64: // llvm.ptx.read.clock64 case 'u': // 1 string to match.
case Intrinsic::readcyclecounter: // llvm.readcyclecounter if (memcmp(NameR.data()+13, ".dq", 3))
case Intrinsic::x86_rdfsbase_64: // llvm.x86.rdfsbase.64 break;
case Intrinsic::x86_rdgsbase_64: // llvm.x86.rdgsbase.64 return Intrinsic::x86_sse2_pmulu_dq; // "86.sse2
VerifyIntrinsicPrototype(ID, IF, 1, 0, MVT::i64); .pmulu.dq"
break; }
case Intrinsic::hexagon_A2_sxtw: // llvm.hexagon.A2.sxtw break;
case Intrinsic::hexagon_A2_tfrpi: // llvm.hexagon.A2.tfrpi }
case Intrinsic::hexagon_C2_mask: // llvm.hexagon.C2.mask break;
case Intrinsic::hexagon_S2_vsplatrh: // llvm.hexagon.S2.vsplatrh case 's': // 2 strings to match.
case Intrinsic::hexagon_S2_vsxtbh: // llvm.hexagon.S2.vsxtbh if (memcmp(NameR.data()+10, "ubus.", 5))
case Intrinsic::hexagon_S2_vsxthw: // llvm.hexagon.S2.vsxthw break;
case Intrinsic::hexagon_S2_vzxtbh: // llvm.hexagon.S2.vzxtbh switch (NameR[15]) {
case Intrinsic::hexagon_S2_vzxthw: // llvm.hexagon.S2.vzxthw default: break;
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::i64, MVT::i32); case 'b': // 1 string to match.
break; return Intrinsic::x86_sse2_psubus_b; // "86.sse2.psubus.
case Intrinsic::hexagon_A2_combineii: // llvm.hexagon.A2.c b"
ombineii case 'w': // 1 string to match.
case Intrinsic::hexagon_A2_combinew: // llvm.hexagon.A2.combinew return Intrinsic::x86_sse2_psubus_w; // "86.sse2.psubus.
case Intrinsic::hexagon_A4_combineir: // llvm.hexagon.A4.c w"
ombineir }
case Intrinsic::hexagon_A4_combineri: // llvm.hexagon.A4.c break;
ombineri }
case Intrinsic::hexagon_M2_cmpyi_s0: // llvm.hexagon.M2.cmpyi.s0 break;
case Intrinsic::hexagon_M2_cmpyr_s0: // llvm.hexagon.M2.cmpyr.s0 }
case Intrinsic::hexagon_M2_cmpys_s0: // llvm.hexagon.M2.cmpys.s0 break;
case Intrinsic::hexagon_M2_cmpys_s1: // llvm.hexagon.M2.cmpys.s1 case '4': // 5 strings to match.
case Intrinsic::hexagon_M2_cmpysc_s0: // llvm.hexagon.M2.c switch (NameR[7]) {
mpysc.s0 default: break;
case Intrinsic::hexagon_M2_cmpysc_s1: // llvm.hexagon.M2.c case '1': // 4 strings to match.
mpysc.s1 if (NameR[8] != '.')
case Intrinsic::hexagon_M2_dpmpyss_s0: // llvm.hexagon.M2.d break;
pmpyss.s0 switch (NameR[9]) {
case Intrinsic::hexagon_M2_dpmpyuu_s0: // llvm.hexagon.M2.d default: break;
pmpyuu.s0 case 'b': // 2 strings to match.
case Intrinsic::hexagon_M2_mpyd_hh_s0: // llvm.hexagon.M2.m if (memcmp(NameR.data()+10, "lendp", 5))
pyd.hh.s0 break;
case Intrinsic::hexagon_M2_mpyd_hh_s1: // llvm.hexagon.M2.m switch (NameR[15]) {
pyd.hh.s1 default: break;
case Intrinsic::hexagon_M2_mpyd_hl_s0: // llvm.hexagon.M2.m case 'd': // 1 string to match.
pyd.hl.s0 return Intrinsic::x86_sse41_blendpd; // "86.sse41.blendp
case Intrinsic::hexagon_M2_mpyd_hl_s1: // llvm.hexagon.M2.m d"
pyd.hl.s1 case 's': // 1 string to match.
case Intrinsic::hexagon_M2_mpyd_lh_s0: // llvm.hexagon.M2.m return Intrinsic::x86_sse41_blendps; // "86.sse41.blendp
pyd.lh.s0 s"
case Intrinsic::hexagon_M2_mpyd_lh_s1: // llvm.hexagon.M2.m }
pyd.lh.s1 break;
case Intrinsic::hexagon_M2_mpyd_ll_s0: // llvm.hexagon.M2.m case 'm': // 1 string to match.
pyd.ll.s0 if (memcmp(NameR.data()+10, "psadbw", 6))
case Intrinsic::hexagon_M2_mpyd_ll_s1: // llvm.hexagon.M2.m break;
pyd.ll.s1 return Intrinsic::x86_sse41_mpsadbw; // "86.sse41.mpsadb
case Intrinsic::hexagon_M2_mpyd_rnd_hh_s0: // llvm.hexagon.M2.m w"
pyd.rnd.hh.s0 case 'p': // 1 string to match.
case Intrinsic::hexagon_M2_mpyd_rnd_hh_s1: // llvm.hexagon.M2.m if (memcmp(NameR.data()+10, "blendw", 6))
pyd.rnd.hh.s1 break;
case Intrinsic::hexagon_M2_mpyd_rnd_hl_s0: // llvm.hexagon.M2.m return Intrinsic::x86_sse41_pblendw; // "86.sse41.pblend
pyd.rnd.hl.s0 w"
case Intrinsic::hexagon_M2_mpyd_rnd_hl_s1: // llvm.hexagon.M2.m }
pyd.rnd.hl.s1 break;
case Intrinsic::hexagon_M2_mpyd_rnd_lh_s0: // llvm.hexagon.M2.m case 'a': // 1 string to match.
pyd.rnd.lh.s0 if (memcmp(NameR.data()+8, ".insertq", 8))
case Intrinsic::hexagon_M2_mpyd_rnd_lh_s1: // llvm.hexagon.M2.m break;
pyd.rnd.lh.s1 return Intrinsic::x86_sse4a_insertq; // "86.sse4a.insert
case Intrinsic::hexagon_M2_mpyd_rnd_ll_s0: // llvm.hexagon.M2.m q"
pyd.rnd.ll.s0 }
case Intrinsic::hexagon_M2_mpyd_rnd_ll_s1: // llvm.hexagon.M2.m break;
pyd.rnd.ll.s1 }
case Intrinsic::hexagon_M2_mpyud_hh_s0: // llvm.hexagon.M2.m break;
pyud.hh.s0 case 's': // 8 strings to match.
case Intrinsic::hexagon_M2_mpyud_hh_s1: // llvm.hexagon.M2.m if (memcmp(NameR.data()+6, "e3.p", 4))
pyud.hh.s1 break;
case Intrinsic::hexagon_M2_mpyud_hl_s0: // llvm.hexagon.M2.m switch (NameR[10]) {
pyud.hl.s0 default: break;
case Intrinsic::hexagon_M2_mpyud_hl_s1: // llvm.hexagon.M2.m case 'h': // 4 strings to match.
pyud.hl.s1 switch (NameR[11]) {
case Intrinsic::hexagon_M2_mpyud_lh_s0: // llvm.hexagon.M2.m default: break;
pyud.lh.s0 case 'a': // 2 strings to match.
case Intrinsic::hexagon_M2_mpyud_lh_s1: // llvm.hexagon.M2.m if (memcmp(NameR.data()+12, "dd.", 3))
pyud.lh.s1 break;
case Intrinsic::hexagon_M2_mpyud_ll_s0: // llvm.hexagon.M2.m switch (NameR[15]) {
pyud.ll.s0 default: break;
case Intrinsic::hexagon_M2_mpyud_ll_s1: // llvm.hexagon.M2.m case 'd': // 1 string to match.
pyud.ll.s1 return Intrinsic::x86_ssse3_phadd_d; // "86.ssse3.phadd.
case Intrinsic::hexagon_M2_vmpy2s_s0: // llvm.hexagon.M2.v d"
mpy2s.s0 case 'w': // 1 string to match.
case Intrinsic::hexagon_M2_vmpy2s_s1: // llvm.hexagon.M2.v return Intrinsic::x86_ssse3_phadd_w; // "86.ssse3.phadd.
mpy2s.s1 w"
case Intrinsic::hexagon_S2_packhl: // llvm.hexagon.S2.packhl }
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::i64, MVT::i32, MVT::i32); break;
break; case 's': // 2 strings to match.
case Intrinsic::hexagon_A2_addsp: // llvm.hexagon.A2.addsp if (memcmp(NameR.data()+12, "ub.", 3))
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::i64, MVT::i32, MVT::i64); break;
break; switch (NameR[15]) {
case Intrinsic::hexagon_C2_vmux: // llvm.hexagon.C2.vmux default: break;
VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::i64, MVT::i32, MVT::i64, MV case 'd': // 1 string to match.
T::i64); return Intrinsic::x86_ssse3_phsub_d; // "86.ssse3.phsub.
break; d"
case Intrinsic::hexagon_A2_absp: // llvm.hexagon.A2.absp case 'w': // 1 string to match.
case Intrinsic::hexagon_A2_negp: // llvm.hexagon.A2.negp return Intrinsic::x86_ssse3_phsub_w; // "86.ssse3.phsub.
case Intrinsic::hexagon_A2_notp: // llvm.hexagon.A2.notp w"
case Intrinsic::hexagon_A2_tfrp: // llvm.hexagon.A2.tfrp }
case Intrinsic::hexagon_A2_vabsh: // llvm.hexagon.A2.vabsh break;
case Intrinsic::hexagon_A2_vabshsat: // llvm.hexagon.A2.vabshsat }
case Intrinsic::hexagon_A2_vabsw: // llvm.hexagon.A2.vabsw break;
case Intrinsic::hexagon_A2_vabswsat: // llvm.hexagon.A2.vabswsat case 's': // 4 strings to match.
case Intrinsic::hexagon_A2_vconj: // llvm.hexagon.A2.vconj switch (NameR[11]) {
case Intrinsic::hexagon_S2_deinterleave: // llvm.hexagon.S2.d default: break;
einterleave case 'h': // 1 string to match.
case Intrinsic::hexagon_S2_interleave: // llvm.hexagon.S2.i if (memcmp(NameR.data()+12, "uf.b", 4))
nterleave break;
case Intrinsic::hexagon_S2_vsathb_nopack: // llvm.hexagon.S2.v return Intrinsic::x86_ssse3_pshuf_b; // "86.ssse3.pshuf.
sathb.nopack b"
case Intrinsic::hexagon_S2_vsathub_nopack: // llvm.hexagon.S2.v case 'i': // 3 strings to match.
sathub.nopack if (memcmp(NameR.data()+12, "gn.", 3))
case Intrinsic::hexagon_S2_vsatwh_nopack: // llvm.hexagon.S2.v break;
satwh.nopack switch (NameR[15]) {
case Intrinsic::hexagon_S2_vsatwuh_nopack: // llvm.hexagon.S2.v default: break;
satwuh.nopack case 'b': // 1 string to match.
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::i64, MVT::i64); return Intrinsic::x86_ssse3_psign_b; // "86.ssse3.psign.
break; b"
case Intrinsic::hexagon_M2_vrcmpys_s1: // llvm.hexagon.M2.v case 'd': // 1 string to match.
rcmpys.s1 return Intrinsic::x86_ssse3_psign_d; // "86.ssse3.psign.
case Intrinsic::hexagon_S2_asl_i_p: // llvm.hexagon.S2.asl.i.p d"
case Intrinsic::hexagon_S2_asl_i_vh: // llvm.hexagon.S2.asl.i.vh case 'w': // 1 string to match.
case Intrinsic::hexagon_S2_asl_i_vw: // llvm.hexagon.S2.asl.i.vw return Intrinsic::x86_ssse3_psign_w; // "86.ssse3.psign.
case Intrinsic::hexagon_S2_asl_r_p: // llvm.hexagon.S2.asl.r.p w"
case Intrinsic::hexagon_S2_asl_r_vh: // llvm.hexagon.S2.asl.r.vh }
case Intrinsic::hexagon_S2_asl_r_vw: // llvm.hexagon.S2.asl.r.vw break;
case Intrinsic::hexagon_S2_asr_i_p: // llvm.hexagon.S2.asr.i.p }
case Intrinsic::hexagon_S2_asr_i_vh: // llvm.hexagon.S2.asr.i.vh break;
case Intrinsic::hexagon_S2_asr_i_vw: // llvm.hexagon.S2.asr.i.vw }
case Intrinsic::hexagon_S2_asr_r_p: // llvm.hexagon.S2.asr.r.p break;
case Intrinsic::hexagon_S2_asr_r_vh: // llvm.hexagon.S2.asr.r.vh }
case Intrinsic::hexagon_S2_asr_r_vw: // llvm.hexagon.S2.asr.r.vw break;
case Intrinsic::hexagon_S2_lsl_r_p: // llvm.hexagon.S2.lsl.r.p case 'v': // 4 strings to match.
case Intrinsic::hexagon_S2_lsl_r_vh: // llvm.hexagon.S2.lsl.r.vh if (memcmp(NameR.data()+4, "cvtp", 4))
case Intrinsic::hexagon_S2_lsl_r_vw: // llvm.hexagon.S2.lsl.r.vw break;
case Intrinsic::hexagon_S2_lsr_i_p: // llvm.hexagon.S2.lsr.i.p switch (NameR[8]) {
case Intrinsic::hexagon_S2_lsr_i_vh: // llvm.hexagon.S2.lsr.i.vh default: break;
case Intrinsic::hexagon_S2_lsr_i_vw: // llvm.hexagon.S2.lsr.i.vw case 'h': // 2 strings to match.
case Intrinsic::hexagon_S2_lsr_r_p: // llvm.hexagon.S2.lsr.r.p if (memcmp(NameR.data()+9, "2ps.", 4))
case Intrinsic::hexagon_S2_lsr_r_vh: // llvm.hexagon.S2.lsr.r.vh break;
case Intrinsic::hexagon_S2_lsr_r_vw: // llvm.hexagon.S2.lsr.r.vw switch (NameR[13]) {
case Intrinsic::hexagon_S2_vcrotate: // llvm.hexagon.S2.vcrotate default: break;
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::i64, MVT::i64, MVT::i32); case '1': // 1 string to match.
break; if (memcmp(NameR.data()+14, "28", 2))
case Intrinsic::hexagon_M2_cmaci_s0: // llvm.hexagon.M2.cmaci.s0 break;
case Intrinsic::hexagon_M2_cmacr_s0: // llvm.hexagon.M2.cmacr.s0 return Intrinsic::x86_vcvtph2ps_128; // "86.vcvtph2ps.12
case Intrinsic::hexagon_M2_cmacs_s0: // llvm.hexagon.M2.cmacs.s0 8"
case Intrinsic::hexagon_M2_cmacs_s1: // llvm.hexagon.M2.cmacs.s1 case '2': // 1 string to match.
case Intrinsic::hexagon_M2_cmacsc_s0: // llvm.hexagon.M2.c if (memcmp(NameR.data()+14, "56", 2))
macsc.s0 break;
case Intrinsic::hexagon_M2_cmacsc_s1: // llvm.hexagon.M2.c return Intrinsic::x86_vcvtph2ps_256; // "86.vcvtph2ps.25
macsc.s1 6"
case Intrinsic::hexagon_M2_cnacs_s0: // llvm.hexagon.M2.cnacs.s0 }
case Intrinsic::hexagon_M2_cnacs_s1: // llvm.hexagon.M2.cnacs.s1 break;
case Intrinsic::hexagon_M2_cnacsc_s0: // llvm.hexagon.M2.c case 's': // 2 strings to match.
nacsc.s0 if (memcmp(NameR.data()+9, "2ph.", 4))
case Intrinsic::hexagon_M2_cnacsc_s1: // llvm.hexagon.M2.c break;
nacsc.s1 switch (NameR[13]) {
case Intrinsic::hexagon_M2_dpmpyss_acc_s0: // llvm.hexagon.M2.d default: break;
pmpyss.acc.s0 case '1': // 1 string to match.
case Intrinsic::hexagon_M2_dpmpyss_nac_s0: // llvm.hexagon.M2.d if (memcmp(NameR.data()+14, "28", 2))
pmpyss.nac.s0 break;
case Intrinsic::hexagon_M2_dpmpyuu_acc_s0: // llvm.hexagon.M2.d return Intrinsic::x86_vcvtps2ph_128; // "86.vcvtps2ph.12
pmpyuu.acc.s0 8"
case Intrinsic::hexagon_M2_dpmpyuu_nac_s0: // llvm.hexagon.M2.d case '2': // 1 string to match.
pmpyuu.nac.s0 if (memcmp(NameR.data()+14, "56", 2))
case Intrinsic::hexagon_M2_mpyd_acc_hh_s0: // llvm.hexagon.M2.m break;
pyd.acc.hh.s0 return Intrinsic::x86_vcvtps2ph_256; // "86.vcvtps2ph.25
case Intrinsic::hexagon_M2_mpyd_acc_hh_s1: // llvm.hexagon.M2.m 6"
pyd.acc.hh.s1 }
case Intrinsic::hexagon_M2_mpyd_acc_hl_s0: // llvm.hexagon.M2.m break;
pyd.acc.hl.s0 }
case Intrinsic::hexagon_M2_mpyd_acc_hl_s1: // llvm.hexagon.M2.m break;
pyd.acc.hl.s1 case 'x': // 12 strings to match.
case Intrinsic::hexagon_M2_mpyd_acc_lh_s0: // llvm.hexagon.M2.m if (memcmp(NameR.data()+4, "op.vp", 5))
pyd.acc.lh.s0 break;
case Intrinsic::hexagon_M2_mpyd_acc_lh_s1: // llvm.hexagon.M2.m switch (NameR[9]) {
pyd.acc.lh.s1 default: break;
case Intrinsic::hexagon_M2_mpyd_acc_ll_s0: // llvm.hexagon.M2.m case 'h': // 6 strings to match.
pyd.acc.ll.s0 if (memcmp(NameR.data()+10, "addu", 4))
case Intrinsic::hexagon_M2_mpyd_acc_ll_s1: // llvm.hexagon.M2.m break;
pyd.acc.ll.s1 switch (NameR[14]) {
case Intrinsic::hexagon_M2_mpyd_nac_hh_s0: // llvm.hexagon.M2.m default: break;
pyd.nac.hh.s0 case 'b': // 3 strings to match.
case Intrinsic::hexagon_M2_mpyd_nac_hh_s1: // llvm.hexagon.M2.m switch (NameR[15]) {
pyd.nac.hh.s1 default: break;
case Intrinsic::hexagon_M2_mpyd_nac_hl_s0: // llvm.hexagon.M2.m case 'd': // 1 string to match.
pyd.nac.hl.s0 return Intrinsic::x86_xop_vphaddubd; // "86.xop.vphaddub
case Intrinsic::hexagon_M2_mpyd_nac_hl_s1: // llvm.hexagon.M2.m d"
pyd.nac.hl.s1 case 'q': // 1 string to match.
case Intrinsic::hexagon_M2_mpyd_nac_lh_s0: // llvm.hexagon.M2.m return Intrinsic::x86_xop_vphaddubq; // "86.xop.vphaddub
pyd.nac.lh.s0 q"
case Intrinsic::hexagon_M2_mpyd_nac_lh_s1: // llvm.hexagon.M2.m case 'w': // 1 string to match.
pyd.nac.lh.s1 return Intrinsic::x86_xop_vphaddubw; // "86.xop.vphaddub
case Intrinsic::hexagon_M2_mpyd_nac_ll_s0: // llvm.hexagon.M2.m w"
pyd.nac.ll.s0 }
case Intrinsic::hexagon_M2_mpyd_nac_ll_s1: // llvm.hexagon.M2.m break;
pyd.nac.ll.s1 case 'd': // 1 string to match.
case Intrinsic::hexagon_M2_mpyud_acc_hh_s0: // llvm.hexagon.M2.m if (NameR[15] != 'q')
pyud.acc.hh.s0 break;
case Intrinsic::hexagon_M2_mpyud_acc_hh_s1: // llvm.hexagon.M2.m return Intrinsic::x86_xop_vphaddudq; // "86.xop.vphaddud
pyud.acc.hh.s1 q"
case Intrinsic::hexagon_M2_mpyud_acc_hl_s0: // llvm.hexagon.M2.m case 'w': // 2 strings to match.
pyud.acc.hl.s0 switch (NameR[15]) {
case Intrinsic::hexagon_M2_mpyud_acc_hl_s1: // llvm.hexagon.M2.m default: break;
pyud.acc.hl.s1 case 'd': // 1 string to match.
case Intrinsic::hexagon_M2_mpyud_acc_lh_s0: // llvm.hexagon.M2.m return Intrinsic::x86_xop_vphadduwd; // "86.xop.vphadduw
pyud.acc.lh.s0 d"
case Intrinsic::hexagon_M2_mpyud_acc_lh_s1: // llvm.hexagon.M2.m case 'q': // 1 string to match.
pyud.acc.lh.s1 return Intrinsic::x86_xop_vphadduwq; // "86.xop.vphadduw
case Intrinsic::hexagon_M2_mpyud_acc_ll_s0: // llvm.hexagon.M2.m q"
pyud.acc.ll.s0 }
case Intrinsic::hexagon_M2_mpyud_acc_ll_s1: // llvm.hexagon.M2.m break;
pyud.acc.ll.s1 }
case Intrinsic::hexagon_M2_mpyud_nac_hh_s0: // llvm.hexagon.M2.m break;
pyud.nac.hh.s0 case 'm': // 6 strings to match.
case Intrinsic::hexagon_M2_mpyud_nac_hh_s1: // llvm.hexagon.M2.m if (NameR[10] != 'a')
pyud.nac.hh.s1 break;
case Intrinsic::hexagon_M2_mpyud_nac_hl_s0: // llvm.hexagon.M2.m switch (NameR[11]) {
pyud.nac.hl.s0 default: break;
case Intrinsic::hexagon_M2_mpyud_nac_hl_s1: // llvm.hexagon.M2.m case 'c': // 5 strings to match.
pyud.nac.hl.s1 if (NameR[12] != 's')
case Intrinsic::hexagon_M2_mpyud_nac_lh_s0: // llvm.hexagon.M2.m break;
pyud.nac.lh.s0 switch (NameR[13]) {
case Intrinsic::hexagon_M2_mpyud_nac_lh_s1: // llvm.hexagon.M2.m default: break;
pyud.nac.lh.s1 case 'd': // 2 strings to match.
case Intrinsic::hexagon_M2_mpyud_nac_ll_s0: // llvm.hexagon.M2.m if (NameR[14] != 'q')
pyud.nac.ll.s0 break;
case Intrinsic::hexagon_M2_mpyud_nac_ll_s1: // llvm.hexagon.M2.m switch (NameR[15]) {
pyud.nac.ll.s1 default: break;
case Intrinsic::hexagon_M2_vmac2: // llvm.hexagon.M2.vmac2 case 'h': // 1 string to match.
case Intrinsic::hexagon_M2_vmac2s_s0: // llvm.hexagon.M2.v return Intrinsic::x86_xop_vpmacsdqh; // "86.xop.vpmacsdq
mac2s.s0 h"
case Intrinsic::hexagon_M2_vmac2s_s1: // llvm.hexagon.M2.v case 'l': // 1 string to match.
mac2s.s1 return Intrinsic::x86_xop_vpmacsdql; // "86.xop.vpmacsdq
case Intrinsic::hexagon_S2_extractup: // llvm.hexagon.S2.e l"
xtractup }
VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::i64, MVT::i64, MVT::i32, MV break;
T::i32); case 's': // 3 strings to match.
break; switch (NameR[14]) {
case Intrinsic::hexagon_A2_addp: // llvm.hexagon.A2.addp default: break;
case Intrinsic::hexagon_A2_addpsat: // llvm.hexagon.A2.addpsat case 'd': // 1 string to match.
case Intrinsic::hexagon_A2_andp: // llvm.hexagon.A2.andp if (NameR[15] != 'd')
case Intrinsic::hexagon_A2_maxp: // llvm.hexagon.A2.maxp break;
case Intrinsic::hexagon_A2_maxup: // llvm.hexagon.A2.maxup return Intrinsic::x86_xop_vpmacssdd; // "86.xop.vpmacssd
case Intrinsic::hexagon_A2_minp: // llvm.hexagon.A2.minp d"
case Intrinsic::hexagon_A2_minup: // llvm.hexagon.A2.minup case 'w': // 2 strings to match.
case Intrinsic::hexagon_A2_orp: // llvm.hexagon.A2.orp switch (NameR[15]) {
case Intrinsic::hexagon_A2_subp: // llvm.hexagon.A2.subp default: break;
case Intrinsic::hexagon_A2_vaddh: // llvm.hexagon.A2.vaddh case 'd': // 1 string to match.
case Intrinsic::hexagon_A2_vaddhs: // llvm.hexagon.A2.vaddhs return Intrinsic::x86_xop_vpmacsswd; // "86.xop.vpmacssw
case Intrinsic::hexagon_A2_vaddub: // llvm.hexagon.A2.vaddub d"
case Intrinsic::hexagon_A2_vaddubs: // llvm.hexagon.A2.vaddubs case 'w': // 1 string to match.
case Intrinsic::hexagon_A2_vadduhs: // llvm.hexagon.A2.vadduhs return Intrinsic::x86_xop_vpmacssww; // "86.xop.vpmacssw
case Intrinsic::hexagon_A2_vaddw: // llvm.hexagon.A2.vaddw w"
case Intrinsic::hexagon_A2_vaddws: // llvm.hexagon.A2.vaddws }
case Intrinsic::hexagon_A2_vavgh: // llvm.hexagon.A2.vavgh break;
case Intrinsic::hexagon_A2_vavghcr: // llvm.hexagon.A2.vavghcr }
case Intrinsic::hexagon_A2_vavghr: // llvm.hexagon.A2.vavghr break;
case Intrinsic::hexagon_A2_vavgub: // llvm.hexagon.A2.vavgub }
case Intrinsic::hexagon_A2_vavgubr: // llvm.hexagon.A2.vavgubr break;
case Intrinsic::hexagon_A2_vavguh: // llvm.hexagon.A2.vavguh case 'd': // 1 string to match.
case Intrinsic::hexagon_A2_vavguhr: // llvm.hexagon.A2.vavguhr if (memcmp(NameR.data()+12, "cswd", 4))
case Intrinsic::hexagon_A2_vavguw: // llvm.hexagon.A2.vavguw break;
case Intrinsic::hexagon_A2_vavguwr: // llvm.hexagon.A2.vavguwr return Intrinsic::x86_xop_vpmadcswd; // "86.xop.vpmadcsw
case Intrinsic::hexagon_A2_vavgw: // llvm.hexagon.A2.vavgw d"
case Intrinsic::hexagon_A2_vavgwcr: // llvm.hexagon.A2.vavgwcr }
case Intrinsic::hexagon_A2_vavgwr: // llvm.hexagon.A2.vavgwr break;
case Intrinsic::hexagon_A2_vmaxh: // llvm.hexagon.A2.vmaxh }
case Intrinsic::hexagon_A2_vmaxub: // llvm.hexagon.A2.vmaxub break;
case Intrinsic::hexagon_A2_vmaxuh: // llvm.hexagon.A2.vmaxuh }
case Intrinsic::hexagon_A2_vmaxuw: // llvm.hexagon.A2.vmaxuw break;
case Intrinsic::hexagon_A2_vmaxw: // llvm.hexagon.A2.vmaxw case 17: // 79 strings to match.
case Intrinsic::hexagon_A2_vminh: // llvm.hexagon.A2.vminh if (memcmp(NameR.data()+0, "86.", 3))
case Intrinsic::hexagon_A2_vminub: // llvm.hexagon.A2.vminub break;
case Intrinsic::hexagon_A2_vminuh: // llvm.hexagon.A2.vminuh switch (NameR[3]) {
case Intrinsic::hexagon_A2_vminuw: // llvm.hexagon.A2.vminuw default: break;
case Intrinsic::hexagon_A2_vminw: // llvm.hexagon.A2.vminw case '3': // 4 strings to match.
case Intrinsic::hexagon_A2_vnavgh: // llvm.hexagon.A2.vnavgh if (memcmp(NameR.data()+4, "dnow", 4))
case Intrinsic::hexagon_A2_vnavghcr: // llvm.hexagon.A2.vnavghcr break;
case Intrinsic::hexagon_A2_vnavghr: // llvm.hexagon.A2.vnavghr switch (NameR[8]) {
case Intrinsic::hexagon_A2_vnavgw: // llvm.hexagon.A2.vnavgw default: break;
case Intrinsic::hexagon_A2_vnavgwcr: // llvm.hexagon.A2.vnavgwcr case '.': // 3 strings to match.
case Intrinsic::hexagon_A2_vnavgwr: // llvm.hexagon.A2.vnavgwr if (memcmp(NameR.data()+9, "pfr", 3))
case Intrinsic::hexagon_A2_vraddub: // llvm.hexagon.A2.vraddub break;
case Intrinsic::hexagon_A2_vrsadub: // llvm.hexagon.A2.vrsadub switch (NameR[12]) {
case Intrinsic::hexagon_A2_vsubh: // llvm.hexagon.A2.vsubh default: break;
case Intrinsic::hexagon_A2_vsubhs: // llvm.hexagon.A2.vsubhs case 'c': // 2 strings to match.
case Intrinsic::hexagon_A2_vsubub: // llvm.hexagon.A2.vsubub if (memcmp(NameR.data()+13, "pit", 3))
case Intrinsic::hexagon_A2_vsububs: // llvm.hexagon.A2.vsububs break;
case Intrinsic::hexagon_A2_vsubuhs: // llvm.hexagon.A2.vsubuhs switch (NameR[16]) {
case Intrinsic::hexagon_A2_vsubw: // llvm.hexagon.A2.vsubw default: break;
case Intrinsic::hexagon_A2_vsubws: // llvm.hexagon.A2.vsubws case '1': // 1 string to match.
case Intrinsic::hexagon_A2_xorp: // llvm.hexagon.A2.xorp return Intrinsic::x86_3dnow_pfrcpit1; // "86.3dnow.pfrcpi
case Intrinsic::hexagon_A4_andnp: // llvm.hexagon.A4.andnp t1"
case Intrinsic::hexagon_A4_ornp: // llvm.hexagon.A4.ornp case '2': // 1 string to match.
case Intrinsic::hexagon_M2_mmpyh_rs0: // llvm.hexagon.M2.m return Intrinsic::x86_3dnow_pfrcpit2; // "86.3dnow.pfrcpi
mpyh.rs0 t2"
case Intrinsic::hexagon_M2_mmpyh_rs1: // llvm.hexagon.M2.m }
mpyh.rs1 break;
case Intrinsic::hexagon_M2_mmpyh_s0: // llvm.hexagon.M2.mmpyh.s0 case 's': // 1 string to match.
case Intrinsic::hexagon_M2_mmpyh_s1: // llvm.hexagon.M2.mmpyh.s1 if (memcmp(NameR.data()+13, "qit1", 4))
case Intrinsic::hexagon_M2_mmpyl_rs0: // llvm.hexagon.M2.m break;
mpyl.rs0 return Intrinsic::x86_3dnow_pfrsqit1; // "86.3dnow.pfrsqi
case Intrinsic::hexagon_M2_mmpyl_rs1: // llvm.hexagon.M2.m t1"
mpyl.rs1 }
case Intrinsic::hexagon_M2_mmpyl_s0: // llvm.hexagon.M2.mmpyl.s0 break;
case Intrinsic::hexagon_M2_mmpyl_s1: // llvm.hexagon.M2.mmpyl.s1 case 'a': // 1 string to match.
case Intrinsic::hexagon_M2_mmpyuh_rs0: // llvm.hexagon.M2.m if (memcmp(NameR.data()+9, ".pfpnacc", 8))
mpyuh.rs0 break;
case Intrinsic::hexagon_M2_mmpyuh_rs1: // llvm.hexagon.M2.m return Intrinsic::x86_3dnowa_pfpnacc; // "86.3dnowa.pfpna
mpyuh.rs1 cc"
case Intrinsic::hexagon_M2_mmpyuh_s0: // llvm.hexagon.M2.m }
mpyuh.s0 break;
case Intrinsic::hexagon_M2_mmpyuh_s1: // llvm.hexagon.M2.m case 'a': // 11 strings to match.
mpyuh.s1 if (memcmp(NameR.data()+4, "vx.", 3))
case Intrinsic::hexagon_M2_mmpyul_rs0: // llvm.hexagon.M2.m break;
mpyul.rs0 switch (NameR[7]) {
case Intrinsic::hexagon_M2_mmpyul_rs1: // llvm.hexagon.M2.m default: break;
mpyul.rs1 case 'c': // 2 strings to match.
case Intrinsic::hexagon_M2_mmpyul_s0: // llvm.hexagon.M2.m if (memcmp(NameR.data()+8, "mp.p", 4))
mpyul.s0 break;
case Intrinsic::hexagon_M2_mmpyul_s1: // llvm.hexagon.M2.m switch (NameR[12]) {
mpyul.s1 default: break;
case Intrinsic::hexagon_M2_vabsdiffh: // llvm.hexagon.M2.v case 'd': // 1 string to match.
absdiffh if (memcmp(NameR.data()+13, ".256", 4))
case Intrinsic::hexagon_M2_vabsdiffw: // llvm.hexagon.M2.v break;
absdiffw return Intrinsic::x86_avx_cmp_pd_256; // "86.avx.cmp.pd.2
case Intrinsic::hexagon_M2_vcmpy_s0_sat_i: // llvm.hexagon.M2.v 56"
cmpy.s0.sat.i case 's': // 1 string to match.
case Intrinsic::hexagon_M2_vcmpy_s0_sat_r: // llvm.hexagon.M2.v if (memcmp(NameR.data()+13, ".256", 4))
cmpy.s0.sat.r break;
case Intrinsic::hexagon_M2_vcmpy_s1_sat_i: // llvm.hexagon.M2.v return Intrinsic::x86_avx_cmp_ps_256; // "86.avx.cmp.ps.2
cmpy.s1.sat.i 56"
case Intrinsic::hexagon_M2_vcmpy_s1_sat_r: // llvm.hexagon.M2.v }
cmpy.s1.sat.r break;
case Intrinsic::hexagon_M2_vdmpys_s0: // llvm.hexagon.M2.v case 'l': // 1 string to match.
dmpys.s0 if (memcmp(NameR.data()+8, "du.dq.256", 9))
case Intrinsic::hexagon_M2_vdmpys_s1: // llvm.hexagon.M2.v break;
dmpys.s1 return Intrinsic::x86_avx_ldu_dq_256; // "86.avx.ldu.dq.2
case Intrinsic::hexagon_M2_vmpy2es_s0: // llvm.hexagon.M2.v 56"
mpy2es.s0 case 'm': // 4 strings to match.
case Intrinsic::hexagon_M2_vmpy2es_s1: // llvm.hexagon.M2.v switch (NameR[8]) {
mpy2es.s1 default: break;
case Intrinsic::hexagon_M2_vrcmpyi_s0: // llvm.hexagon.M2.v case 'a': // 2 strings to match.
rcmpyi.s0 if (memcmp(NameR.data()+9, "x.p", 3))
case Intrinsic::hexagon_M2_vrcmpyi_s0c: // llvm.hexagon.M2.v break;
rcmpyi.s0c switch (NameR[12]) {
case Intrinsic::hexagon_M2_vrcmpyr_s0: // llvm.hexagon.M2.v default: break;
rcmpyr.s0 case 'd': // 1 string to match.
case Intrinsic::hexagon_M2_vrcmpyr_s0c: // llvm.hexagon.M2.v if (memcmp(NameR.data()+13, ".256", 4))
rcmpyr.s0c break;
case Intrinsic::hexagon_M2_vrmpy_s0: // llvm.hexagon.M2.vrmpy.s0 return Intrinsic::x86_avx_max_pd_256; // "86.avx.max.pd.2
case Intrinsic::hexagon_S2_extractup_rp: // llvm.hexagon.S2.e 56"
xtractup.rp case 's': // 1 string to match.
case Intrinsic::hexagon_S2_lfsp: // llvm.hexagon.S2.lfsp if (memcmp(NameR.data()+13, ".256", 4))
case Intrinsic::hexagon_S2_shuffeb: // llvm.hexagon.S2.shuffeb break;
case Intrinsic::hexagon_S2_shuffeh: // llvm.hexagon.S2.shuffeh return Intrinsic::x86_avx_max_ps_256; // "86.avx.max.ps.2
case Intrinsic::hexagon_S2_shuffob: // llvm.hexagon.S2.shuffob 56"
case Intrinsic::hexagon_S2_shuffoh: // llvm.hexagon.S2.shuffoh }
case Intrinsic::hexagon_S2_vtrunewh: // llvm.hexagon.S2.vtrunewh break;
case Intrinsic::hexagon_S2_vtrunowh: // llvm.hexagon.S2.vtrunowh case 'i': // 2 strings to match.
case Intrinsic::hexagon_S4_andnp: // llvm.hexagon.S4.andnp if (memcmp(NameR.data()+9, "n.p", 3))
case Intrinsic::hexagon_S4_ornp: // llvm.hexagon.S4.ornp break;
case Intrinsic::x86_bmi_bextr_64: // llvm.x86.bmi.bextr.64 switch (NameR[12]) {
case Intrinsic::x86_bmi_bzhi_64: // llvm.x86.bmi.bzhi.64 default: break;
case Intrinsic::x86_bmi_pdep_64: // llvm.x86.bmi.pdep.64 case 'd': // 1 string to match.
case Intrinsic::x86_bmi_pext_64: // llvm.x86.bmi.pext.64 if (memcmp(NameR.data()+13, ".256", 4))
case Intrinsic::x86_sse42_crc32_64_64: // llvm.x86.sse42.cr break;
c32.64.64 return Intrinsic::x86_avx_min_pd_256; // "86.avx.min.pd.2
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::i64, MVT::i64, MVT::i64); 56"
break; case 's': // 1 string to match.
case Intrinsic::hexagon_M2_vrcmpys_acc_s1: // llvm.hexagon.M2.v if (memcmp(NameR.data()+13, ".256", 4))
rcmpys.acc.s1 break;
case Intrinsic::hexagon_S2_asl_i_p_acc: // llvm.hexagon.S2.a return Intrinsic::x86_avx_min_ps_256; // "86.avx.min.ps.2
sl.i.p.acc 56"
case Intrinsic::hexagon_S2_asl_i_p_and: // llvm.hexagon.S2.a }
sl.i.p.and break;
case Intrinsic::hexagon_S2_asl_i_p_nac: // llvm.hexagon.S2.a }
sl.i.p.nac break;
case Intrinsic::hexagon_S2_asl_i_p_or: // llvm.hexagon.S2.a case 'p': // 2 strings to match.
sl.i.p.or if (memcmp(NameR.data()+8, "test", 4))
case Intrinsic::hexagon_S2_asl_i_p_xacc: // llvm.hexagon.S2.a break;
sl.i.p.xacc switch (NameR[12]) {
case Intrinsic::hexagon_S2_asl_r_p_acc: // llvm.hexagon.S2.a default: break;
sl.r.p.acc case 'c': // 1 string to match.
case Intrinsic::hexagon_S2_asl_r_p_and: // llvm.hexagon.S2.a if (memcmp(NameR.data()+13, ".256", 4))
sl.r.p.and break;
case Intrinsic::hexagon_S2_asl_r_p_nac: // llvm.hexagon.S2.a return Intrinsic::x86_avx_ptestc_256; // "86.avx.ptestc.2
sl.r.p.nac 56"
case Intrinsic::hexagon_S2_asl_r_p_or: // llvm.hexagon.S2.a case 'z': // 1 string to match.
sl.r.p.or if (memcmp(NameR.data()+13, ".256", 4))
case Intrinsic::hexagon_S2_asr_i_p_acc: // llvm.hexagon.S2.a break;
sr.i.p.acc return Intrinsic::x86_avx_ptestz_256; // "86.avx.ptestz.2
case Intrinsic::hexagon_S2_asr_i_p_and: // llvm.hexagon.S2.a 56"
sr.i.p.and }
case Intrinsic::hexagon_S2_asr_i_p_nac: // llvm.hexagon.S2.a break;
sr.i.p.nac case 'r': // 1 string to match.
case Intrinsic::hexagon_S2_asr_i_p_or: // llvm.hexagon.S2.a if (memcmp(NameR.data()+8, "cp.ps.256", 9))
sr.i.p.or break;
case Intrinsic::hexagon_S2_asr_r_p_acc: // llvm.hexagon.S2.a return Intrinsic::x86_avx_rcp_ps_256; // "86.avx.rcp.ps.2
sr.r.p.acc 56"
case Intrinsic::hexagon_S2_asr_r_p_and: // llvm.hexagon.S2.a case 'v': // 1 string to match.
sr.r.p.and if (memcmp(NameR.data()+8, "zeroupper", 9))
case Intrinsic::hexagon_S2_asr_r_p_nac: // llvm.hexagon.S2.a break;
sr.r.p.nac return Intrinsic::x86_avx_vzeroupper; // "86.avx.vzeroupp
case Intrinsic::hexagon_S2_asr_r_p_or: // llvm.hexagon.S2.a er"
sr.r.p.or }
case Intrinsic::hexagon_S2_lsl_r_p_acc: // llvm.hexagon.S2.l break;
sl.r.p.acc case 'f': // 8 strings to match.
case Intrinsic::hexagon_S2_lsl_r_p_and: // llvm.hexagon.S2.l if (memcmp(NameR.data()+4, "ma.vfnm", 7))
sl.r.p.and break;
case Intrinsic::hexagon_S2_lsl_r_p_nac: // llvm.hexagon.S2.l switch (NameR[11]) {
sl.r.p.nac default: break;
case Intrinsic::hexagon_S2_lsl_r_p_or: // llvm.hexagon.S2.l case 'a': // 4 strings to match.
sl.r.p.or if (memcmp(NameR.data()+12, "dd.", 3))
case Intrinsic::hexagon_S2_lsr_i_p_acc: // llvm.hexagon.S2.l break;
sr.i.p.acc switch (NameR[15]) {
case Intrinsic::hexagon_S2_lsr_i_p_and: // llvm.hexagon.S2.l default: break;
sr.i.p.and case 'p': // 2 strings to match.
case Intrinsic::hexagon_S2_lsr_i_p_nac: // llvm.hexagon.S2.l switch (NameR[16]) {
sr.i.p.nac default: break;
case Intrinsic::hexagon_S2_lsr_i_p_or: // llvm.hexagon.S2.l case 'd': // 1 string to match.
sr.i.p.or return Intrinsic::x86_fma_vfnmadd_pd; // "86.fma.vfnmadd.
case Intrinsic::hexagon_S2_lsr_i_p_xacc: // llvm.hexagon.S2.l pd"
sr.i.p.xacc case 's': // 1 string to match.
case Intrinsic::hexagon_S2_lsr_r_p_acc: // llvm.hexagon.S2.l return Intrinsic::x86_fma_vfnmadd_ps; // "86.fma.vfnmadd.
sr.r.p.acc ps"
case Intrinsic::hexagon_S2_lsr_r_p_and: // llvm.hexagon.S2.l }
sr.r.p.and break;
case Intrinsic::hexagon_S2_lsr_r_p_nac: // llvm.hexagon.S2.l case 's': // 2 strings to match.
sr.r.p.nac switch (NameR[16]) {
case Intrinsic::hexagon_S2_lsr_r_p_or: // llvm.hexagon.S2.l default: break;
sr.r.p.or case 'd': // 1 string to match.
case Intrinsic::hexagon_S2_valignib: // llvm.hexagon.S2.valignib return Intrinsic::x86_fma_vfnmadd_sd; // "86.fma.vfnmadd.
case Intrinsic::hexagon_S2_valignrb: // llvm.hexagon.S2.valignrb sd"
case Intrinsic::hexagon_S2_vspliceib: // llvm.hexagon.S2.v case 's': // 1 string to match.
spliceib return Intrinsic::x86_fma_vfnmadd_ss; // "86.fma.vfnmadd.
case Intrinsic::hexagon_S2_vsplicerb: // llvm.hexagon.S2.v ss"
splicerb }
VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::i64, MVT::i64, MVT::i64, MV break;
T::i32); }
break; break;
case Intrinsic::hexagon_S2_insertp: // llvm.hexagon.S2.insertp case 's': // 4 strings to match.
VerifyIntrinsicPrototype(ID, IF, 1, 4, MVT::i64, MVT::i64, MVT::i64, MV if (memcmp(NameR.data()+12, "ub.", 3))
T::i32, MVT::i32); break;
break; switch (NameR[15]) {
case Intrinsic::hexagon_A2_vraddub_acc: // llvm.hexagon.A2.v default: break;
raddub.acc case 'p': // 2 strings to match.
case Intrinsic::hexagon_A2_vrsadub_acc: // llvm.hexagon.A2.v switch (NameR[16]) {
rsadub.acc default: break;
case Intrinsic::hexagon_M2_mmachs_rs0: // llvm.hexagon.M2.m case 'd': // 1 string to match.
machs.rs0 return Intrinsic::x86_fma_vfnmsub_pd; // "86.fma.vfnmsub.
case Intrinsic::hexagon_M2_mmachs_rs1: // llvm.hexagon.M2.m pd"
machs.rs1 case 's': // 1 string to match.
case Intrinsic::hexagon_M2_mmachs_s0: // llvm.hexagon.M2.m return Intrinsic::x86_fma_vfnmsub_ps; // "86.fma.vfnmsub.
machs.s0 ps"
case Intrinsic::hexagon_M2_mmachs_s1: // llvm.hexagon.M2.m }
machs.s1 break;
case Intrinsic::hexagon_M2_mmacls_rs0: // llvm.hexagon.M2.m case 's': // 2 strings to match.
macls.rs0 switch (NameR[16]) {
case Intrinsic::hexagon_M2_mmacls_rs1: // llvm.hexagon.M2.m default: break;
macls.rs1 case 'd': // 1 string to match.
case Intrinsic::hexagon_M2_mmacls_s0: // llvm.hexagon.M2.m return Intrinsic::x86_fma_vfnmsub_sd; // "86.fma.vfnmsub.
macls.s0 sd"
case Intrinsic::hexagon_M2_mmacls_s1: // llvm.hexagon.M2.m case 's': // 1 string to match.
macls.s1 return Intrinsic::x86_fma_vfnmsub_ss; // "86.fma.vfnmsub.
case Intrinsic::hexagon_M2_mmacuhs_rs0: // llvm.hexagon.M2.m ss"
macuhs.rs0 }
case Intrinsic::hexagon_M2_mmacuhs_rs1: // llvm.hexagon.M2.m break;
macuhs.rs1 }
case Intrinsic::hexagon_M2_mmacuhs_s0: // llvm.hexagon.M2.m break;
macuhs.s0 }
case Intrinsic::hexagon_M2_mmacuhs_s1: // llvm.hexagon.M2.m break;
macuhs.s1 case 's': // 50 strings to match.
case Intrinsic::hexagon_M2_mmaculs_rs0: // llvm.hexagon.M2.m if (NameR[4] != 's')
maculs.rs0 break;
case Intrinsic::hexagon_M2_mmaculs_rs1: // llvm.hexagon.M2.m switch (NameR[5]) {
maculs.rs1 default: break;
case Intrinsic::hexagon_M2_mmaculs_s0: // llvm.hexagon.M2.m case 'e': // 48 strings to match.
maculs.s0 switch (NameR[6]) {
case Intrinsic::hexagon_M2_mmaculs_s1: // llvm.hexagon.M2.m default: break;
maculs.s1 case '.': // 8 strings to match.
case Intrinsic::hexagon_M2_vcmac_s0_sat_i: // llvm.hexagon.M2.v switch (NameR[7]) {
cmac.s0.sat.i default: break;
case Intrinsic::hexagon_M2_vcmac_s0_sat_r: // llvm.hexagon.M2.v case 'c': // 3 strings to match.
cmac.s0.sat.r switch (NameR[8]) {
case Intrinsic::hexagon_M2_vdmacs_s0: // llvm.hexagon.M2.v default: break;
dmacs.s0 case 'o': // 1 string to match.
case Intrinsic::hexagon_M2_vdmacs_s1: // llvm.hexagon.M2.v if (memcmp(NameR.data()+9, "mineq.ss", 8))
dmacs.s1 break;
case Intrinsic::hexagon_M2_vmac2es: // llvm.hexagon.M2.vmac2es return Intrinsic::x86_sse_comineq_ss; // "86.sse.comineq.
case Intrinsic::hexagon_M2_vmac2es_s0: // llvm.hexagon.M2.v ss"
mac2es.s0 case 'v': // 2 strings to match.
case Intrinsic::hexagon_M2_vmac2es_s1: // llvm.hexagon.M2.v if (memcmp(NameR.data()+9, "ts", 2))
mac2es.s1 break;
case Intrinsic::hexagon_M2_vrcmaci_s0: // llvm.hexagon.M2.v switch (NameR[11]) {
rcmaci.s0 default: break;
case Intrinsic::hexagon_M2_vrcmaci_s0c: // llvm.hexagon.M2.v case 'i': // 1 string to match.
rcmaci.s0c if (memcmp(NameR.data()+12, "642ss", 5))
case Intrinsic::hexagon_M2_vrcmacr_s0: // llvm.hexagon.M2.v break;
rcmacr.s0 return Intrinsic::x86_sse_cvtsi642ss; // "86.sse.
case Intrinsic::hexagon_M2_vrcmacr_s0c: // llvm.hexagon.M2.v cvtsi642ss"
rcmacr.s0c case 's': // 1 string to match.
case Intrinsic::hexagon_M2_vrmac_s0: // llvm.hexagon.M2.vrmac.s0 if (memcmp(NameR.data()+12, "2si64", 5))
case Intrinsic::hexagon_M4_xor_xacc: // llvm.hexagon.M4.xor.xacc break;
case Intrinsic::hexagon_S2_insertp_rp: // llvm.hexagon.S2.i return Intrinsic::x86_sse_cvtss2si64; // "86.sse.
nsertp.rp cvtss2si64"
VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::i64, MVT::i64, MVT::i64, MV }
T::i64); break;
break; }
case Intrinsic::x86_sse42_crc32_64_8: // llvm.x86.sse42.cr break;
c32.64.8 case 'u': // 5 strings to match.
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::i64, MVT::i64, MVT::i8); if (memcmp(NameR.data()+8, "comi", 4))
break; break;
case Intrinsic::x86_sse2_cvtsd2si64: // llvm.x86.sse2.cvtsd2si64 switch (NameR[12]) {
case Intrinsic::x86_sse2_cvttsd2si64: // llvm.x86.sse2.cvt default: break;
tsd2si64 case 'e': // 1 string to match.
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::i64, MVT::v2f64); if (memcmp(NameR.data()+13, "q.ss", 4))
break; break;
case Intrinsic::x86_sse41_pextrq: // llvm.x86.sse41.pextrq return Intrinsic::x86_sse_ucomieq_ss; // "86.sse.ucomieq.
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::i64, MVT::v2i64, MVT::i32); ss"
break; case 'g': // 2 strings to match.
case Intrinsic::x86_sse_cvtss2si64: // llvm.x86.sse.cvtss2si64 switch (NameR[13]) {
case Intrinsic::x86_sse_cvttss2si64: // llvm.x86.sse.cvttss2si64 default: break;
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::i64, MVT::v4f32); case 'e': // 1 string to match.
break; if (memcmp(NameR.data()+14, ".ss", 3))
case Intrinsic::arm_thread_pointer: // llvm.arm.thread.pointer break;
case Intrinsic::eh_sjlj_lsda: // llvm.eh.sjlj.lsda return Intrinsic::x86_sse_ucomige_ss; // "86.sse.
case Intrinsic::stacksave: // llvm.stacksave ucomige.ss"
case Intrinsic::xcore_waitevent: // llvm.xcore.waitevent case 't': // 1 string to match.
VerifyIntrinsicPrototype(ID, IF, 1, 0, MVT::iPTR); if (memcmp(NameR.data()+14, ".ss", 3))
break; break;
case Intrinsic::eh_dwarf_cfa: // llvm.eh.dwarf.cfa return Intrinsic::x86_sse_ucomigt_ss; // "86.sse.
case Intrinsic::frameaddress: // llvm.frameaddress ucomigt.ss"
case Intrinsic::returnaddress: // llvm.returnaddress }
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::iPTR, MVT::i32); break;
break; case 'l': // 2 strings to match.
case Intrinsic::adjust_trampoline: // llvm.adjust.trampoline switch (NameR[13]) {
case Intrinsic::xcore_checkevent: // llvm.xcore.checkevent default: break;
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::iPTR, MVT::iPTR); case 'e': // 1 string to match.
break; if (memcmp(NameR.data()+14, ".ss", 3))
case Intrinsic::gcread: // llvm.gcread break;
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::iPTR, MVT::iPTR, MVT::iPTR) return Intrinsic::x86_sse_ucomile_ss; // "86.sse.
; ucomile.ss"
break; case 't': // 1 string to match.
case Intrinsic::x86_avx2_pabs_w: // llvm.x86.avx2.pabs.w if (memcmp(NameR.data()+14, ".ss", 3))
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v16i16, MVT::v16i16); break;
break; return Intrinsic::x86_sse_ucomilt_ss; // "86.sse.
case Intrinsic::x86_avx2_pslli_w: // llvm.x86.avx2.pslli.w ucomilt.ss"
case Intrinsic::x86_avx2_psrai_w: // llvm.x86.avx2.psrai.w }
case Intrinsic::x86_avx2_psrli_w: // llvm.x86.avx2.psrli.w break;
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v16i16, MVT::v16i16, MVT::i }
32); break;
break; }
case Intrinsic::x86_avx2_padds_w: // llvm.x86.avx2.padds.w break;
case Intrinsic::x86_avx2_paddus_w: // llvm.x86.avx2.paddus.w case '2': // 12 strings to match.
case Intrinsic::x86_avx2_pavg_w: // llvm.x86.avx2.pavg.w if (NameR[7] != '.')
case Intrinsic::x86_avx2_phadd_sw: // llvm.x86.avx2.phadd.sw break;
case Intrinsic::x86_avx2_phadd_w: // llvm.x86.avx2.phadd.w switch (NameR[8]) {
case Intrinsic::x86_avx2_phsub_sw: // llvm.x86.avx2.phsub.sw default: break;
case Intrinsic::x86_avx2_phsub_w: // llvm.x86.avx2.phsub.w case 'c': // 8 strings to match.
case Intrinsic::x86_avx2_pmaxs_w: // llvm.x86.avx2.pmaxs.w switch (NameR[9]) {
case Intrinsic::x86_avx2_pmaxu_w: // llvm.x86.avx2.pmaxu.w default: break;
case Intrinsic::x86_avx2_pmins_w: // llvm.x86.avx2.pmins.w case 'o': // 5 strings to match.
case Intrinsic::x86_avx2_pminu_w: // llvm.x86.avx2.pminu.w if (memcmp(NameR.data()+10, "mi", 2))
case Intrinsic::x86_avx2_pmul_hr_sw: // llvm.x86.avx2.pmul.hr.sw break;
case Intrinsic::x86_avx2_pmulh_w: // llvm.x86.avx2.pmulh.w switch (NameR[12]) {
case Intrinsic::x86_avx2_pmulhu_w: // llvm.x86.avx2.pmulhu.w default: break;
case Intrinsic::x86_avx2_psign_w: // llvm.x86.avx2.psign.w case 'e': // 1 string to match.
case Intrinsic::x86_avx2_psubs_w: // llvm.x86.avx2.psubs.w if (memcmp(NameR.data()+13, "q.sd", 4))
case Intrinsic::x86_avx2_psubus_w: // llvm.x86.avx2.psubus.w break;
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v16i16, MVT::v16i16, MVT::v return Intrinsic::x86_sse2_comieq_sd; // "86.sse2
16i16); .comieq.sd"
break; case 'g': // 2 strings to match.
case Intrinsic::x86_avx2_pblendw: // llvm.x86.avx2.pblendw switch (NameR[13]) {
VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v16i16, MVT::v16i16, MVT::v default: break;
16i16, MVT::i32); case 'e': // 1 string to match.
break; if (memcmp(NameR.data()+14, ".sd", 3))
case Intrinsic::x86_avx2_psll_w: // llvm.x86.avx2.psll.w break;
case Intrinsic::x86_avx2_psra_w: // llvm.x86.avx2.psra.w return Intrinsic::x86_sse2_comige_sd; // "86.sse2
case Intrinsic::x86_avx2_psrl_w: // llvm.x86.avx2.psrl.w .comige.sd"
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v16i16, MVT::v16i16, MVT::v case 't': // 1 string to match.
8i16); if (memcmp(NameR.data()+14, ".sd", 3))
break; break;
case Intrinsic::x86_avx2_pmovsxbw: // llvm.x86.avx2.pmovsxbw return Intrinsic::x86_sse2_comigt_sd; // "86.sse2
case Intrinsic::x86_avx2_pmovzxbw: // llvm.x86.avx2.pmovzxbw .comigt.sd"
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v16i16, MVT::v16i8); }
break; break;
case Intrinsic::x86_avx2_pmadd_ub_sw: // llvm.x86.avx2.pma case 'l': // 2 strings to match.
dd.ub.sw switch (NameR[13]) {
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v16i16, MVT::v32i8, MVT::v3 default: break;
2i8); case 'e': // 1 string to match.
break; if (memcmp(NameR.data()+14, ".sd", 3))
case Intrinsic::x86_avx2_mpsadbw: // llvm.x86.avx2.mpsadbw break;
VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v16i16, MVT::v32i8, MVT::v3 return Intrinsic::x86_sse2_comile_sd; // "86.sse2
2i8, MVT::i32); .comile.sd"
break; case 't': // 1 string to match.
case Intrinsic::x86_avx2_pbroadcastw_256: // llvm.x86.avx2.pbr if (memcmp(NameR.data()+14, ".sd", 3))
oadcastw.256 break;
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v16i16, MVT::v8i16); return Intrinsic::x86_sse2_comilt_sd; // "86.sse2
break; .comilt.sd"
case Intrinsic::x86_avx2_packssdw: // llvm.x86.avx2.packssdw }
case Intrinsic::x86_avx2_packusdw: // llvm.x86.avx2.packusdw break;
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v16i16, MVT::v8i32, MVT::v8 }
i32); break;
break; case 'v': // 3 strings to match.
case Intrinsic::ppc_altivec_lvebx: // llvm.ppc.altivec.lvebx if (memcmp(NameR.data()+10, "tt", 2))
case Intrinsic::ppc_altivec_lvsl: // llvm.ppc.altivec.lvsl break;
case Intrinsic::ppc_altivec_lvsr: // llvm.ppc.altivec.lvsr switch (NameR[12]) {
case Intrinsic::x86_sse3_ldu_dq: // llvm.x86.sse3.ldu.dq default: break;
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v16i8, MVT::iPTR); case 'p': // 2 strings to match.
break; switch (NameR[13]) {
case Intrinsic::x86_avx2_pbroadcastb_128: // llvm.x86.avx2.pbr default: break;
oadcastb.128 case 'd': // 1 string to match.
case Intrinsic::x86_ssse3_pabs_b_128: // llvm.x86.ssse3.pa if (memcmp(NameR.data()+14, "2dq", 3))
bs.b.128 break;
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v16i8, MVT::v16i8); return Intrinsic::x86_sse2_cvttpd2dq; // "86.sse2
break; .cvttpd2dq"
case Intrinsic::spu_si_shlqbii: // llvm.spu.si.shlqbii case 's': // 1 string to match.
case Intrinsic::spu_si_shlqbyi: // llvm.spu.si.shlqbyi if (memcmp(NameR.data()+14, "2dq", 3))
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v16i8, MVT::v16i8, MVT::i8) break;
; return Intrinsic::x86_sse2_cvttps2dq; // "86.sse2
break; .cvttps2dq"
case Intrinsic::x86_sse42_pcmpestrm128: // llvm.x86.sse42.pc }
mpestrm128 break;
VerifyIntrinsicPrototype(ID, IF, 1, 5, MVT::v16i8, MVT::v16i8, MVT::i32 case 's': // 1 string to match.
, MVT::v16i8, MVT::i32, MVT::i8); if (memcmp(NameR.data()+13, "d2si", 4))
break; break;
case Intrinsic::spu_si_andbi: // llvm.spu.si.andbi return Intrinsic::x86_sse2_cvttsd2si; // "86.sse2
case Intrinsic::spu_si_ceqbi: // llvm.spu.si.ceqbi .cvttsd2si"
case Intrinsic::spu_si_cgtbi: // llvm.spu.si.cgtbi }
case Intrinsic::spu_si_clgtbi: // llvm.spu.si.clgtbi break;
case Intrinsic::spu_si_orbi: // llvm.spu.si.orbi }
case Intrinsic::spu_si_xorbi: // llvm.spu.si.xorbi break;
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v16i8, MVT::v16i8, MVT::i8) case 'm': // 1 string to match.
; if (memcmp(NameR.data()+9, "ovmsk.pd", 8))
break; break;
case Intrinsic::ppc_altivec_vaddsbs: // llvm.ppc.altivec.vaddsbs return Intrinsic::x86_sse2_movmsk_pd; // "86.sse2.movmsk.
case Intrinsic::ppc_altivec_vaddubs: // llvm.ppc.altivec.vaddubs pd"
case Intrinsic::ppc_altivec_vavgsb: // llvm.ppc.altivec.vavgsb case 's': // 3 strings to match.
case Intrinsic::ppc_altivec_vavgub: // llvm.ppc.altivec.vavgub if (memcmp(NameR.data()+9, "tore", 4))
case Intrinsic::ppc_altivec_vcmpequb: // llvm.ppc.altivec. break;
vcmpequb switch (NameR[13]) {
case Intrinsic::ppc_altivec_vcmpgtsb: // llvm.ppc.altivec. default: break;
vcmpgtsb case 'l': // 1 string to match.
case Intrinsic::ppc_altivec_vcmpgtub: // llvm.ppc.altivec. if (memcmp(NameR.data()+14, ".dq", 3))
vcmpgtub break;
case Intrinsic::ppc_altivec_vmaxsb: // llvm.ppc.altivec.vmaxsb return Intrinsic::x86_sse2_storel_dq; // "86.sse2.storel.
case Intrinsic::ppc_altivec_vmaxub: // llvm.ppc.altivec.vmaxub dq"
case Intrinsic::ppc_altivec_vminsb: // llvm.ppc.altivec.vminsb case 'u': // 2 strings to match.
case Intrinsic::ppc_altivec_vminub: // llvm.ppc.altivec.vminub if (NameR[14] != '.')
case Intrinsic::ppc_altivec_vrlb: // llvm.ppc.altivec.vrlb break;
case Intrinsic::ppc_altivec_vslb: // llvm.ppc.altivec.vslb switch (NameR[15]) {
case Intrinsic::ppc_altivec_vsrab: // llvm.ppc.altivec.vsrab default: break;
case Intrinsic::ppc_altivec_vsrb: // llvm.ppc.altivec.vsrb case 'd': // 1 string to match.
case Intrinsic::ppc_altivec_vsubsbs: // llvm.ppc.altivec.vsubsbs if (NameR[16] != 'q')
case Intrinsic::ppc_altivec_vsububs: // llvm.ppc.altivec.vsububs break;
case Intrinsic::spu_si_ceqb: // llvm.spu.si.ceqb return Intrinsic::x86_sse2_storeu_dq; // "86.sse2
case Intrinsic::spu_si_cgtb: // llvm.spu.si.cgtb .storeu.dq"
case Intrinsic::spu_si_clgtb: // llvm.spu.si.clgtb case 'p': // 1 string to match.
case Intrinsic::x86_sse2_padds_b: // llvm.x86.sse2.padds.b if (NameR[16] != 'd')
case Intrinsic::x86_sse2_paddus_b: // llvm.x86.sse2.paddus.b break;
case Intrinsic::x86_sse2_pavg_b: // llvm.x86.sse2.pavg.b return Intrinsic::x86_sse2_storeu_pd; // "86.sse2
case Intrinsic::x86_sse2_pmaxu_b: // llvm.x86.sse2.pmaxu.b .storeu.pd"
case Intrinsic::x86_sse2_pminu_b: // llvm.x86.sse2.pminu.b }
case Intrinsic::x86_sse2_psubs_b: // llvm.x86.sse2.psubs.b break;
case Intrinsic::x86_sse2_psubus_b: // llvm.x86.sse2.psubus.b }
case Intrinsic::x86_sse41_pmaxsb: // llvm.x86.sse41.pmaxsb break;
case Intrinsic::x86_sse41_pminsb: // llvm.x86.sse41.pminsb }
case Intrinsic::x86_ssse3_pshuf_b_128: // llvm.x86.ssse3.ps break;
huf.b.128 case '3': // 2 strings to match.
case Intrinsic::x86_ssse3_psign_b_128: // llvm.x86.ssse3.ps if (memcmp(NameR.data()+7, ".addsub.p", 9))
ign.b.128 break;
case Intrinsic::x86_xop_vpcomeqb: // llvm.x86.xop.vpcomeqb switch (NameR[16]) {
case Intrinsic::x86_xop_vpcomequb: // llvm.x86.xop.vpcomequb default: break;
case Intrinsic::x86_xop_vpcomfalseb: // llvm.x86.xop.vpcomfalseb case 'd': // 1 string to match.
case Intrinsic::x86_xop_vpcomfalseub: // llvm.x86.xop.vpco return Intrinsic::x86_sse3_addsub_pd; // "86.sse3.addsub.
mfalseub pd"
case Intrinsic::x86_xop_vpcomgeb: // llvm.x86.xop.vpcomgeb case 's': // 1 string to match.
case Intrinsic::x86_xop_vpcomgeub: // llvm.x86.xop.vpcomgeub return Intrinsic::x86_sse3_addsub_ps; // "86.sse3.addsub.
case Intrinsic::x86_xop_vpcomgtb: // llvm.x86.xop.vpcomgtb ps"
case Intrinsic::x86_xop_vpcomgtub: // llvm.x86.xop.vpcomgtub }
case Intrinsic::x86_xop_vpcomleb: // llvm.x86.xop.vpcomleb break;
case Intrinsic::x86_xop_vpcomleub: // llvm.x86.xop.vpcomleub case '4': // 26 strings to match.
case Intrinsic::x86_xop_vpcomltb: // llvm.x86.xop.vpcomltb switch (NameR[7]) {
case Intrinsic::x86_xop_vpcomltub: // llvm.x86.xop.vpcomltub default: break;
case Intrinsic::x86_xop_vpcomneb: // llvm.x86.xop.vpcomneb case '1': // 23 strings to match.
case Intrinsic::x86_xop_vpcomneub: // llvm.x86.xop.vpcomneub if (NameR[8] != '.')
case Intrinsic::x86_xop_vpcomtrueb: // llvm.x86.xop.vpcomtrueb break;
case Intrinsic::x86_xop_vpcomtrueub: // llvm.x86.xop.vpcomtrueub switch (NameR[9]) {
case Intrinsic::x86_xop_vprotb: // llvm.x86.xop.vprotb default: break;
case Intrinsic::x86_xop_vpshab: // llvm.x86.xop.vpshab case 'b': // 2 strings to match.
case Intrinsic::x86_xop_vpshlb: // llvm.x86.xop.vpshlb if (memcmp(NameR.data()+10, "lendvp", 6))
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v16i8, MVT::v16i8, MVT::v16 break;
i8); switch (NameR[16]) {
break; default: break;
case Intrinsic::x86_sse42_pcmpistrm128: // llvm.x86.sse42.pc case 'd': // 1 string to match.
mpistrm128 return Intrinsic::x86_sse41_blendvpd; // "86.sse4
VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v16i8, MVT::v16i8, MVT::v16 1.blendvpd"
i8, MVT::i8); case 's': // 1 string to match.
break; return Intrinsic::x86_sse41_blendvps; // "86.sse4
case Intrinsic::x86_sse41_pblendvb: // llvm.x86.sse41.pblendvb 1.blendvps"
case Intrinsic::x86_xop_vpperm: // llvm.x86.xop.vpperm }
VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v16i8, MVT::v16i8, MVT::v16 break;
i8, MVT::v16i8); case 'i': // 1 string to match.
break; if (memcmp(NameR.data()+10, "nsertps", 7))
case Intrinsic::ppc_altivec_vpkswss: // llvm.ppc.altivec.vpkswss break;
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v16i8, MVT::v4i32, MVT::v4i return Intrinsic::x86_sse41_insertps; // "86.sse41.insert
32); ps"
break; case 'm': // 1 string to match.
case Intrinsic::ppc_altivec_vpkshss: // llvm.ppc.altivec.vpkshss if (memcmp(NameR.data()+10, "ovntdqa", 7))
case Intrinsic::ppc_altivec_vpkshus: // llvm.ppc.altivec.vpkshus break;
case Intrinsic::ppc_altivec_vpkuhus: // llvm.ppc.altivec.vpkuhus return Intrinsic::x86_sse41_movntdqa; // "86.sse41.movntd
case Intrinsic::x86_sse2_packsswb_128: // llvm.x86.sse2.pac qa"
ksswb.128 case 'p': // 15 strings to match.
case Intrinsic::x86_sse2_packuswb_128: // llvm.x86.sse2.pac switch (NameR[10]) {
kuswb.128 default: break;
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v16i8, MVT::v8i16, MVT::v8i case 'a': // 1 string to match.
16); if (memcmp(NameR.data()+11, "ckusdw", 6))
break; break;
case Intrinsic::x86_avx_maskload_pd: // llvm.x86.avx.maskload.pd return Intrinsic::x86_sse41_packusdw; // "86.sse4
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v2f64, MVT::iPTR, MVT::v2f6 1.packusdw"
4); case 'b': // 1 string to match.
break; if (memcmp(NameR.data()+11, "lendvb", 6))
case Intrinsic::x86_sse2_sqrt_pd: // llvm.x86.sse2.sqrt.pd break;
case Intrinsic::x86_sse2_sqrt_sd: // llvm.x86.sse2.sqrt.sd return Intrinsic::x86_sse41_pblendvb; // "86.sse4
case Intrinsic::x86_xop_vfrcz_pd: // llvm.x86.xop.vfrcz.pd 1.pblendvb"
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v2f64, MVT::v2f64); case 'm': // 12 strings to match.
break; if (memcmp(NameR.data()+11, "ov", 2))
case Intrinsic::x86_sse2_cvtsi2sd: // llvm.x86.sse2.cvtsi2sd break;
case Intrinsic::x86_sse41_round_pd: // llvm.x86.sse41.round.pd switch (NameR[13]) {
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v2f64, MVT::v2f64, MVT::i32 default: break;
); case 's': // 6 strings to match.
break; if (NameR[14] != 'x')
case Intrinsic::x86_sse2_cvtsi642sd: // llvm.x86.sse2.cvtsi642sd break;
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v2f64, MVT::v2f64, MVT::i64 switch (NameR[15]) {
); default: break;
break; case 'b': // 3 strings to match.
case Intrinsic::spu_si_dfa: // llvm.spu.si.dfa switch (NameR[16]) {
case Intrinsic::spu_si_dfm: // llvm.spu.si.dfm default: break;
case Intrinsic::spu_si_dfma: // llvm.spu.si.dfma case 'd': // 1 string to match.
case Intrinsic::spu_si_dfms: // llvm.spu.si.dfms return Intrinsic::x86_sse41_pmovsxbd; // "86.sse4
case Intrinsic::spu_si_dfnma: // llvm.spu.si.dfnma 1.pmovsxbd"
case Intrinsic::spu_si_dfnms: // llvm.spu.si.dfnms case 'q': // 1 string to match.
case Intrinsic::spu_si_dfs: // llvm.spu.si.dfs return Intrinsic::x86_sse41_pmovsxbq; // "86.sse4
case Intrinsic::x86_sse2_add_sd: // llvm.x86.sse2.add.sd 1.pmovsxbq"
case Intrinsic::x86_sse2_div_sd: // llvm.x86.sse2.div.sd case 'w': // 1 string to match.
case Intrinsic::x86_sse2_max_pd: // llvm.x86.sse2.max.pd return Intrinsic::x86_sse41_pmovsxbw; // "86.sse4
case Intrinsic::x86_sse2_max_sd: // llvm.x86.sse2.max.sd 1.pmovsxbw"
case Intrinsic::x86_sse2_min_pd: // llvm.x86.sse2.min.pd }
case Intrinsic::x86_sse2_min_sd: // llvm.x86.sse2.min.sd break;
case Intrinsic::x86_sse2_mul_sd: // llvm.x86.sse2.mul.sd case 'd': // 1 string to match.
case Intrinsic::x86_sse2_sub_sd: // llvm.x86.sse2.sub.sd if (NameR[16] != 'q')
case Intrinsic::x86_sse3_addsub_pd: // llvm.x86.sse3.addsub.pd break;
case Intrinsic::x86_sse3_hadd_pd: // llvm.x86.sse3.hadd.pd return Intrinsic::x86_sse41_pmovsxdq; // "86.sse4
case Intrinsic::x86_sse3_hsub_pd: // llvm.x86.sse3.hsub.pd 1.pmovsxdq"
case Intrinsic::x86_xop_vfrcz_sd: // llvm.x86.xop.vfrcz.sd case 'w': // 2 strings to match.
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v2f64, MVT::v2f64, MVT::v2f switch (NameR[16]) {
64); default: break;
break; case 'd': // 1 string to match.
case Intrinsic::x86_sse41_blendpd: // llvm.x86.sse41.blendpd return Intrinsic::x86_sse41_pmovsxwd; // "86.sse4
case Intrinsic::x86_sse41_dppd: // llvm.x86.sse41.dppd 1.pmovsxwd"
case Intrinsic::x86_sse41_round_sd: // llvm.x86.sse41.round.sd case 'q': // 1 string to match.
VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v2f64, MVT::v2f64, MVT::v2f return Intrinsic::x86_sse41_pmovsxwq; // "86.sse4
64, MVT::i32); 1.pmovsxwq"
break; }
case Intrinsic::x86_sse2_cmp_pd: // llvm.x86.sse2.cmp.pd break;
case Intrinsic::x86_sse2_cmp_sd: // llvm.x86.sse2.cmp.sd }
VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v2f64, MVT::v2f64, MVT::v2f break;
64, MVT::i8); case 'z': // 6 strings to match.
break; if (NameR[14] != 'x')
case Intrinsic::x86_fma4_vfmadd_pd: // llvm.x86.fma4.vfmadd.pd break;
case Intrinsic::x86_fma4_vfmadd_sd: // llvm.x86.fma4.vfmadd.sd switch (NameR[15]) {
case Intrinsic::x86_fma4_vfmaddsub_pd: // llvm.x86.fma4.vfm default: break;
addsub.pd case 'b': // 3 strings to match.
case Intrinsic::x86_fma4_vfmsub_pd: // llvm.x86.fma4.vfmsub.pd switch (NameR[16]) {
case Intrinsic::x86_fma4_vfmsub_sd: // llvm.x86.fma4.vfmsub.sd default: break;
case Intrinsic::x86_fma4_vfmsubadd_pd: // llvm.x86.fma4.vfm case 'd': // 1 string to match.
subadd.pd return Intrinsic::x86_sse41_pmovzxbd; // "86.sse4
case Intrinsic::x86_fma4_vfnmadd_pd: // llvm.x86.fma4.vfnmadd.pd 1.pmovzxbd"
case Intrinsic::x86_fma4_vfnmadd_sd: // llvm.x86.fma4.vfnmadd.sd case 'q': // 1 string to match.
case Intrinsic::x86_fma4_vfnmsub_pd: // llvm.x86.fma4.vfnmsub.pd return Intrinsic::x86_sse41_pmovzxbq; // "86.sse4
case Intrinsic::x86_fma4_vfnmsub_sd: // llvm.x86.fma4.vfnmsub.sd 1.pmovzxbq"
case Intrinsic::x86_sse41_blendvpd: // llvm.x86.sse41.blendvpd case 'w': // 1 string to match.
VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v2f64, MVT::v2f64, MVT::v2f return Intrinsic::x86_sse41_pmovzxbw; // "86.sse4
64, MVT::v2f64); 1.pmovzxbw"
break; }
case Intrinsic::x86_xop_vpermil2pd: // llvm.x86.xop.vpermil2pd break;
VerifyIntrinsicPrototype(ID, IF, 1, 4, MVT::v2f64, MVT::v2f64, MVT::v2f case 'd': // 1 string to match.
64, MVT::v2f64, MVT::i8); if (NameR[16] != 'q')
break; break;
case Intrinsic::x86_avx_vpermilvar_pd: // llvm.x86.avx.vper return Intrinsic::x86_sse41_pmovzxdq; // "86.sse4
milvar.pd 1.pmovzxdq"
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v2f64, MVT::v2f64, MVT::v2i case 'w': // 2 strings to match.
64); switch (NameR[16]) {
break; default: break;
case Intrinsic::x86_sse2_cvtss2sd: // llvm.x86.sse2.cvtss2sd case 'd': // 1 string to match.
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v2f64, MVT::v2f64, MVT::v4f return Intrinsic::x86_sse41_pmovzxwd; // "86.sse4
32); 1.pmovzxwd"
break; case 'q': // 1 string to match.
case Intrinsic::x86_sse2_cvtps2pd: // llvm.x86.sse2.cvtps2pd return Intrinsic::x86_sse41_pmovzxwq; // "86.sse4
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v2f64, MVT::v4f32); 1.pmovzxwq"
break; }
case Intrinsic::x86_avx_vextractf128_pd_256: // llvm.x86.avx.vext break;
ractf128.pd.256 }
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v2f64, MVT::v4f64, MVT::i8) break;
; }
break; break;
case Intrinsic::x86_sse2_cvtdq2pd: // llvm.x86.sse2.cvtdq2pd case 't': // 1 string to match.
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v2f64, MVT::v4i32); if (memcmp(NameR.data()+11, "estnzc", 6))
break; break;
case Intrinsic::x86_sse_cvtpi2pd: // llvm.x86.sse.cvtpi2pd return Intrinsic::x86_sse41_ptestnzc; // "86.sse4
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v2f64, MVT::x86mmx); 1.ptestnzc"
break; }
case Intrinsic::arm_neon_vacged: // llvm.arm.neon.vacged break;
case Intrinsic::arm_neon_vacgtd: // llvm.arm.neon.vacgtd case 'r': // 4 strings to match.
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v2i32, MVT::v2f32, MVT::v2f if (memcmp(NameR.data()+10, "ound.", 5))
32); break;
break; switch (NameR[15]) {
case Intrinsic::x86_sse41_movntdqa: // llvm.x86.sse41.movntdqa default: break;
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v2i64, MVT::iPTR); case 'p': // 2 strings to match.
break; switch (NameR[16]) {
case Intrinsic::x86_avx2_maskload_q: // llvm.x86.avx2.maskload.q default: break;
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v2i64, MVT::iPTR, MVT::v2i6 case 'd': // 1 string to match.
4); return Intrinsic::x86_sse41_round_pd; // "86.sse4
break; 1.round.pd"
case Intrinsic::x86_sse41_pmovsxbq: // llvm.x86.sse41.pmovsxbq case 's': // 1 string to match.
case Intrinsic::x86_sse41_pmovzxbq: // llvm.x86.sse41.pmovzxbq return Intrinsic::x86_sse41_round_ps; // "86.sse4
case Intrinsic::x86_xop_vphaddbq: // llvm.x86.xop.vphaddbq 1.round.ps"
case Intrinsic::x86_xop_vphaddubq: // llvm.x86.xop.vphaddubq }
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v2i64, MVT::v16i8); break;
break; case 's': // 2 strings to match.
case Intrinsic::x86_sse2_psad_bw: // llvm.x86.sse2.psad.bw switch (NameR[16]) {
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v2i64, MVT::v16i8, MVT::v16 default: break;
i8); case 'd': // 1 string to match.
break; return Intrinsic::x86_sse41_round_sd; // "86.sse4
case Intrinsic::x86_aesni_aesimc: // llvm.x86.aesni.aesimc 1.round.sd"
case Intrinsic::x86_avx2_pbroadcastq_128: // llvm.x86.avx2.pbr case 's': // 1 string to match.
oadcastq.128 return Intrinsic::x86_sse41_round_ss; // "86.sse4
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v2i64, MVT::v2i64); 1.round.ss"
break; }
case Intrinsic::x86_sse2_psll_dq: // llvm.x86.sse2.psll.dq break;
case Intrinsic::x86_sse2_psll_dq_bs: // llvm.x86.sse2.psll.dq.bs }
case Intrinsic::x86_sse2_pslli_q: // llvm.x86.sse2.pslli.q break;
case Intrinsic::x86_sse2_psrl_dq: // llvm.x86.sse2.psrl.dq }
case Intrinsic::x86_sse2_psrl_dq_bs: // llvm.x86.sse2.psrl.dq.bs break;
case Intrinsic::x86_sse2_psrli_q: // llvm.x86.sse2.psrli.q case 'a': // 3 strings to match.
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v2i64, MVT::v2i64, MVT::i32 if (NameR[8] != '.')
); break;
break; switch (NameR[9]) {
case Intrinsic::x86_aesni_aeskeygenassist: // llvm.x86.aesni.ae default: break;
skeygenassist case 'i': // 1 string to match.
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v2i64, MVT::v2i64, MVT::i8) if (memcmp(NameR.data()+10, "nsertqi", 7))
; break;
break; return Intrinsic::x86_sse4a_insertqi; // "86.sse4a.insert
case Intrinsic::x86_aesni_aesdec: // llvm.x86.aesni.aesdec qi"
case Intrinsic::x86_aesni_aesdeclast: // llvm.x86.aesni.ae case 'm': // 2 strings to match.
sdeclast if (memcmp(NameR.data()+10, "ovnt.s", 6))
case Intrinsic::x86_aesni_aesenc: // llvm.x86.aesni.aesenc break;
case Intrinsic::x86_aesni_aesenclast: // llvm.x86.aesni.ae switch (NameR[16]) {
senclast default: break;
case Intrinsic::x86_avx2_psllv_q: // llvm.x86.avx2.psllv.q case 'd': // 1 string to match.
case Intrinsic::x86_avx2_psrlv_q: // llvm.x86.avx2.psrlv.q return Intrinsic::x86_sse4a_movnt_sd; // "86.sse4
case Intrinsic::x86_sse2_psll_q: // llvm.x86.sse2.psll.q a.movnt.sd"
case Intrinsic::x86_sse2_psrl_q: // llvm.x86.sse2.psrl.q case 's': // 1 string to match.
case Intrinsic::x86_xop_vpcomeqq: // llvm.x86.xop.vpcomeqq return Intrinsic::x86_sse4a_movnt_ss; // "86.sse4
case Intrinsic::x86_xop_vpcomequq: // llvm.x86.xop.vpcomequq a.movnt.ss"
case Intrinsic::x86_xop_vpcomfalseq: // llvm.x86.xop.vpcomfalseq }
case Intrinsic::x86_xop_vpcomfalseuq: // llvm.x86.xop.vpco break;
mfalseuq }
case Intrinsic::x86_xop_vpcomgeq: // llvm.x86.xop.vpcomgeq break;
case Intrinsic::x86_xop_vpcomgeuq: // llvm.x86.xop.vpcomgeuq }
case Intrinsic::x86_xop_vpcomgtq: // llvm.x86.xop.vpcomgtq break;
case Intrinsic::x86_xop_vpcomgtuq: // llvm.x86.xop.vpcomgtuq }
case Intrinsic::x86_xop_vpcomleq: // llvm.x86.xop.vpcomleq break;
case Intrinsic::x86_xop_vpcomleuq: // llvm.x86.xop.vpcomleuq case 's': // 2 strings to match.
case Intrinsic::x86_xop_vpcomltq: // llvm.x86.xop.vpcomltq if (memcmp(NameR.data()+6, "e3.ph", 5))
case Intrinsic::x86_xop_vpcomltuq: // llvm.x86.xop.vpcomltuq break;
case Intrinsic::x86_xop_vpcomneq: // llvm.x86.xop.vpcomneq switch (NameR[11]) {
case Intrinsic::x86_xop_vpcomneuq: // llvm.x86.xop.vpcomneuq default: break;
case Intrinsic::x86_xop_vpcomtrueq: // llvm.x86.xop.vpcomtrueq case 'a': // 1 string to match.
case Intrinsic::x86_xop_vpcomtrueuq: // llvm.x86.xop.vpcomtrueuq if (memcmp(NameR.data()+12, "dd.sw", 5))
case Intrinsic::x86_xop_vprotq: // llvm.x86.xop.vprotq break;
case Intrinsic::x86_xop_vpshaq: // llvm.x86.xop.vpshaq return Intrinsic::x86_ssse3_phadd_sw; // "86.ssse3.phadd.
case Intrinsic::x86_xop_vpshlq: // llvm.x86.xop.vpshlq sw"
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v2i64, MVT::v2i64, MVT::v2i case 's': // 1 string to match.
64); if (memcmp(NameR.data()+12, "ub.sw", 5))
break; break;
case Intrinsic::x86_xop_vpcmov: // llvm.x86.xop.vpcmov return Intrinsic::x86_ssse3_phsub_sw; // "86.ssse3.phsub.
VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v2i64, MVT::v2i64, MVT::v2i sw"
64, MVT::v2i64); }
break; break;
case Intrinsic::x86_sse41_pmovsxdq: // llvm.x86.sse41.pmovsxdq }
case Intrinsic::x86_sse41_pmovzxdq: // llvm.x86.sse41.pmovzxdq break;
case Intrinsic::x86_xop_vphadddq: // llvm.x86.xop.vphadddq case 'x': // 6 strings to match.
case Intrinsic::x86_xop_vphaddudq: // llvm.x86.xop.vphaddudq if (memcmp(NameR.data()+4, "op.vp", 5))
case Intrinsic::x86_xop_vphsubdq: // llvm.x86.xop.vphsubdq break;
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v2i64, MVT::v4i32); switch (NameR[9]) {
break; default: break;
case Intrinsic::x86_sse2_pmulu_dq: // llvm.x86.sse2.pmulu.dq case 'c': // 1 string to match.
case Intrinsic::x86_sse41_pmuldq: // llvm.x86.sse41.pmuldq if (memcmp(NameR.data()+10, "mov.256", 7))
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v2i64, MVT::v4i32, MVT::v4i break;
32); return Intrinsic::x86_xop_vpcmov_256; // "86.xop.vpcmov.2
break; 56"
case Intrinsic::x86_xop_vpmacsdqh: // llvm.x86.xop.vpmacsdqh case 'e': // 2 strings to match.
case Intrinsic::x86_xop_vpmacsdql: // llvm.x86.xop.vpmacsdql if (memcmp(NameR.data()+10, "rmil2p", 6))
case Intrinsic::x86_xop_vpmacssdqh: // llvm.x86.xop.vpmacssdqh break;
case Intrinsic::x86_xop_vpmacssdql: // llvm.x86.xop.vpmacssdql switch (NameR[16]) {
VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v2i64, MVT::v4i32, MVT::v4i default: break;
32, MVT::v2i64); case 'd': // 1 string to match.
break; return Intrinsic::x86_xop_vpermil2pd; // "86.xop.vpermil2
case Intrinsic::x86_avx2_vextracti128: // llvm.x86.avx2.vex pd"
tracti128 case 's': // 1 string to match.
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v2i64, MVT::v4i64, MVT::i8) return Intrinsic::x86_xop_vpermil2ps; // "86.xop.vpermil2
; ps"
break; }
case Intrinsic::x86_sse41_pmovsxwq: // llvm.x86.sse41.pmovsxwq break;
case Intrinsic::x86_sse41_pmovzxwq: // llvm.x86.sse41.pmovzxwq case 'm': // 3 strings to match.
case Intrinsic::x86_xop_vphadduwq: // llvm.x86.xop.vphadduwq if (NameR[10] != 'a')
case Intrinsic::x86_xop_vphaddwq: // llvm.x86.xop.vphaddwq break;
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v2i64, MVT::v8i16); switch (NameR[11]) {
break; default: break;
case Intrinsic::x86_avx_ldu_dq_256: // llvm.x86.avx.ldu.dq.256 case 'c': // 2 strings to match.
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v32i8, MVT::iPTR); if (memcmp(NameR.data()+12, "ssdq", 4))
break; break;
case Intrinsic::x86_avx2_packsswb: // llvm.x86.avx2.packsswb switch (NameR[16]) {
case Intrinsic::x86_avx2_packuswb: // llvm.x86.avx2.packuswb default: break;
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v32i8, MVT::v16i16, MVT::v1 case 'h': // 1 string to match.
6i16); return Intrinsic::x86_xop_vpmacssdqh; // "86.xop.vpmacssd
break; qh"
case Intrinsic::x86_avx2_pbroadcastb_256: // llvm.x86.avx2.pbr case 'l': // 1 string to match.
oadcastb.256 return Intrinsic::x86_xop_vpmacssdql; // "86.xop.vpmacssd
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v32i8, MVT::v16i8); ql"
break; }
case Intrinsic::x86_avx2_pabs_b: // llvm.x86.avx2.pabs.b break;
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v32i8, MVT::v32i8); case 'd': // 1 string to match.
break; if (memcmp(NameR.data()+12, "csswd", 5))
case Intrinsic::x86_avx2_padds_b: // llvm.x86.avx2.padds.b break;
case Intrinsic::x86_avx2_paddus_b: // llvm.x86.avx2.paddus.b return Intrinsic::x86_xop_vpmadcsswd; // "86.xop.vpmadcss
case Intrinsic::x86_avx2_pavg_b: // llvm.x86.avx2.pavg.b wd"
case Intrinsic::x86_avx2_pmaxs_b: // llvm.x86.avx2.pmaxs.b }
case Intrinsic::x86_avx2_pmaxu_b: // llvm.x86.avx2.pmaxu.b break;
case Intrinsic::x86_avx2_pmins_b: // llvm.x86.avx2.pmins.b }
case Intrinsic::x86_avx2_pminu_b: // llvm.x86.avx2.pminu.b break;
case Intrinsic::x86_avx2_pshuf_b: // llvm.x86.avx2.pshuf.b }
case Intrinsic::x86_avx2_psign_b: // llvm.x86.avx2.psign.b break;
case Intrinsic::x86_avx2_psubs_b: // llvm.x86.avx2.psubs.b case 18: // 33 strings to match.
case Intrinsic::x86_avx2_psubus_b: // llvm.x86.avx2.psubus.b if (memcmp(NameR.data()+0, "86.", 3))
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v32i8, MVT::v32i8, MVT::v32 break;
i8); switch (NameR[3]) {
break; default: break;
case Intrinsic::x86_avx2_pblendvb: // llvm.x86.avx2.pblendvb case 'a': // 20 strings to match.
VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v32i8, MVT::v32i8, MVT::v32 if (memcmp(NameR.data()+4, "vx", 2))
i8, MVT::v32i8); break;
break; switch (NameR[6]) {
case Intrinsic::x86_avx_vbroadcast_ss: // llvm.x86.avx.vbro default: break;
adcast.ss case '.': // 10 strings to match.
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v4f32, MVT::iPTR); switch (NameR[7]) {
break; default: break;
case Intrinsic::x86_avx_maskload_ps: // llvm.x86.avx.maskload.ps case 'h': // 4 strings to match.
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4f32, MVT::iPTR, MVT::v4f3 switch (NameR[8]) {
2); default: break;
break; case 'a': // 2 strings to match.
case Intrinsic::x86_sse2_cvtpd2ps: // llvm.x86.sse2.cvtpd2ps if (memcmp(NameR.data()+9, "dd.p", 4))
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v4f32, MVT::v2f64); break;
break; switch (NameR[13]) {
case Intrinsic::ppc_altivec_vexptefp: // llvm.ppc.altivec. default: break;
vexptefp case 'd': // 1 string to match.
case Intrinsic::ppc_altivec_vlogefp: // llvm.ppc.altivec.vlogefp if (memcmp(NameR.data()+14, ".256", 4))
case Intrinsic::ppc_altivec_vrefp: // llvm.ppc.altivec.vrefp break;
case Intrinsic::ppc_altivec_vrfim: // llvm.ppc.altivec.vrfim return Intrinsic::x86_avx_hadd_pd_256; // "86.avx.hadd.pd.
case Intrinsic::ppc_altivec_vrfin: // llvm.ppc.altivec.vrfin 256"
case Intrinsic::ppc_altivec_vrfip: // llvm.ppc.altivec.vrfip case 's': // 1 string to match.
case Intrinsic::ppc_altivec_vrfiz: // llvm.ppc.altivec.vrfiz if (memcmp(NameR.data()+14, ".256", 4))
case Intrinsic::ppc_altivec_vrsqrtefp: // llvm.ppc.altivec. break;
vrsqrtefp return Intrinsic::x86_avx_hadd_ps_256; // "86.avx.hadd.ps.
case Intrinsic::x86_avx2_vbroadcast_ss_ps: // llvm.x86.avx2.vbr 256"
oadcast.ss.ps }
case Intrinsic::x86_sse_rcp_ps: // llvm.x86.sse.rcp.ps break;
case Intrinsic::x86_sse_rcp_ss: // llvm.x86.sse.rcp.ss case 's': // 2 strings to match.
case Intrinsic::x86_sse_rsqrt_ps: // llvm.x86.sse.rsqrt.ps if (memcmp(NameR.data()+9, "ub.p", 4))
case Intrinsic::x86_sse_rsqrt_ss: // llvm.x86.sse.rsqrt.ss break;
case Intrinsic::x86_sse_sqrt_ps: // llvm.x86.sse.sqrt.ps switch (NameR[13]) {
case Intrinsic::x86_sse_sqrt_ss: // llvm.x86.sse.sqrt.ss default: break;
case Intrinsic::x86_xop_vfrcz_ps: // llvm.x86.xop.vfrcz.ps case 'd': // 1 string to match.
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v4f32, MVT::v4f32); if (memcmp(NameR.data()+14, ".256", 4))
break; break;
case Intrinsic::x86_sse41_round_ps: // llvm.x86.sse41.round.ps return Intrinsic::x86_avx_hsub_pd_256; // "86.avx.hsub.pd.
case Intrinsic::x86_sse_cvtsi2ss: // llvm.x86.sse.cvtsi2ss 256"
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4f32, MVT::v4f32, MVT::i32 case 's': // 1 string to match.
); if (memcmp(NameR.data()+14, ".256", 4))
break; break;
case Intrinsic::x86_sse_cvtsi642ss: // llvm.x86.sse.cvtsi642ss return Intrinsic::x86_avx_hsub_ps_256; // "86.avx.hsub.ps.
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4f32, MVT::v4f32, MVT::i64 256"
); }
break; break;
case Intrinsic::x86_sse2_cvtsd2ss: // llvm.x86.sse2.cvtsd2ss }
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4f32, MVT::v4f32, MVT::v2f break;
64); case 'm': // 2 strings to match.
break; if (memcmp(NameR.data()+8, "askload.p", 9))
case Intrinsic::ppc_altivec_vmaxfp: // llvm.ppc.altivec.vmaxfp break;
case Intrinsic::ppc_altivec_vminfp: // llvm.ppc.altivec.vminfp switch (NameR[17]) {
case Intrinsic::spu_si_fa: // llvm.spu.si.fa default: break;
case Intrinsic::spu_si_fceq: // llvm.spu.si.fceq case 'd': // 1 string to match.
case Intrinsic::spu_si_fcgt: // llvm.spu.si.fcgt return Intrinsic::x86_avx_maskload_pd; // "86.avx.maskload
case Intrinsic::spu_si_fcmeq: // llvm.spu.si.fcmeq .pd"
case Intrinsic::spu_si_fcmgt: // llvm.spu.si.fcmgt case 's': // 1 string to match.
case Intrinsic::spu_si_fm: // llvm.spu.si.fm return Intrinsic::x86_avx_maskload_ps; // "86.avx.maskload
case Intrinsic::spu_si_fs: // llvm.spu.si.fs .ps"
case Intrinsic::x86_sse3_addsub_ps: // llvm.x86.sse3.addsub.ps }
case Intrinsic::x86_sse3_hadd_ps: // llvm.x86.sse3.hadd.ps break;
case Intrinsic::x86_sse3_hsub_ps: // llvm.x86.sse3.hsub.ps case 's': // 2 strings to match.
case Intrinsic::x86_sse_add_ss: // llvm.x86.sse.add.ss if (memcmp(NameR.data()+8, "qrt.p", 5))
case Intrinsic::x86_sse_div_ss: // llvm.x86.sse.div.ss break;
case Intrinsic::x86_sse_max_ps: // llvm.x86.sse.max.ps switch (NameR[13]) {
case Intrinsic::x86_sse_max_ss: // llvm.x86.sse.max.ss default: break;
case Intrinsic::x86_sse_min_ps: // llvm.x86.sse.min.ps case 'd': // 1 string to match.
case Intrinsic::x86_sse_min_ss: // llvm.x86.sse.min.ss if (memcmp(NameR.data()+14, ".256", 4))
case Intrinsic::x86_sse_mul_ss: // llvm.x86.sse.mul.ss break;
case Intrinsic::x86_sse_sub_ss: // llvm.x86.sse.sub.ss return Intrinsic::x86_avx_sqrt_pd_256; // "86.avx.sqrt.pd.
case Intrinsic::x86_xop_vfrcz_ss: // llvm.x86.xop.vfrcz.ss 256"
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4f32, MVT::v4f32, MVT::v4f case 's': // 1 string to match.
32); if (memcmp(NameR.data()+14, ".256", 4))
break; break;
case Intrinsic::x86_sse41_blendps: // llvm.x86.sse41.blendps return Intrinsic::x86_avx_sqrt_ps_256; // "86.avx.sqrt.ps.
case Intrinsic::x86_sse41_dpps: // llvm.x86.sse41.dpps 256"
case Intrinsic::x86_sse41_insertps: // llvm.x86.sse41.insertps }
case Intrinsic::x86_sse41_round_ss: // llvm.x86.sse41.round.ss break;
VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v4f32, MVT::v4f32, MVT::v4f case 'v': // 2 strings to match.
32, MVT::i32); if (memcmp(NameR.data()+8, "testnzc.p", 9))
break; break;
case Intrinsic::x86_sse_cmp_ps: // llvm.x86.sse.cmp.ps switch (NameR[17]) {
case Intrinsic::x86_sse_cmp_ss: // llvm.x86.sse.cmp.ss default: break;
VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v4f32, MVT::v4f32, MVT::v4f case 'd': // 1 string to match.
32, MVT::i8); return Intrinsic::x86_avx_vtestnzc_pd; // "86.avx.vtestnzc
break; .pd"
case Intrinsic::ppc_altivec_vmaddfp: // llvm.ppc.altivec.vmaddfp case 's': // 1 string to match.
case Intrinsic::ppc_altivec_vnmsubfp: // llvm.ppc.altivec. return Intrinsic::x86_avx_vtestnzc_ps; // "86.avx.vtestnzc
vnmsubfp .ps"
case Intrinsic::spu_si_fma: // llvm.spu.si.fma }
case Intrinsic::spu_si_fms: // llvm.spu.si.fms break;
case Intrinsic::spu_si_fnms: // llvm.spu.si.fnms }
case Intrinsic::x86_fma4_vfmadd_ps: // llvm.x86.fma4.vfmadd.ps break;
case Intrinsic::x86_fma4_vfmadd_ss: // llvm.x86.fma4.vfmadd.ss case '2': // 10 strings to match.
case Intrinsic::x86_fma4_vfmaddsub_ps: // llvm.x86.fma4.vfm if (NameR[7] != '.')
addsub.ps break;
case Intrinsic::x86_fma4_vfmsub_ps: // llvm.x86.fma4.vfmsub.ps switch (NameR[8]) {
case Intrinsic::x86_fma4_vfmsub_ss: // llvm.x86.fma4.vfmsub.ss default: break;
case Intrinsic::x86_fma4_vfmsubadd_ps: // llvm.x86.fma4.vfm case 'g': // 4 strings to match.
subadd.ps if (memcmp(NameR.data()+9, "ather.", 6))
case Intrinsic::x86_fma4_vfnmadd_ps: // llvm.x86.fma4.vfnmadd.ps break;
case Intrinsic::x86_fma4_vfnmadd_ss: // llvm.x86.fma4.vfnmadd.ss switch (NameR[15]) {
case Intrinsic::x86_fma4_vfnmsub_ps: // llvm.x86.fma4.vfnmsub.ps default: break;
case Intrinsic::x86_fma4_vfnmsub_ss: // llvm.x86.fma4.vfnmsub.ss case 'd': // 2 strings to match.
case Intrinsic::x86_sse41_blendvps: // llvm.x86.sse41.blendvps if (NameR[16] != '.')
VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v4f32, MVT::v4f32, MVT::v4f break;
32, MVT::v4f32); switch (NameR[17]) {
break; default: break;
case Intrinsic::x86_xop_vpermil2ps: // llvm.x86.xop.vpermil2ps case 'd': // 1 string to match.
VerifyIntrinsicPrototype(ID, IF, 1, 4, MVT::v4f32, MVT::v4f32, MVT::v4f return Intrinsic::x86_avx2_gather_d_d; // "86.avx2.gather.
32, MVT::v4f32, MVT::i8); d.d"
break; case 'q': // 1 string to match.
case Intrinsic::x86_avx_vpermilvar_ps: // llvm.x86.avx.vper return Intrinsic::x86_avx2_gather_d_q; // "86.avx2.gather.
milvar.ps d.q"
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4f32, MVT::v4f32, MVT::v4i }
32); break;
break; case 'q': // 2 strings to match.
case Intrinsic::x86_sse_cvtpi2ps: // llvm.x86.sse.cvtpi2ps if (NameR[16] != '.')
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4f32, MVT::v4f32, MVT::x86 break;
mmx); switch (NameR[17]) {
break; default: break;
case Intrinsic::x86_avx_cvt_pd2_ps_256: // llvm.x86.avx.cvt. case 'd': // 1 string to match.
pd2.ps.256 return Intrinsic::x86_avx2_gather_q_d; // "86.avx2.gather.
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v4f32, MVT::v4f64); q.d"
break; case 'q': // 1 string to match.
case Intrinsic::arm_neon_vcvthf2fp: // llvm.arm.neon.vcvthf2fp return Intrinsic::x86_avx2_gather_q_q; // "86.avx2.gather.
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v4f32, MVT::v4i16); q.q"
break; }
case Intrinsic::x86_sse2_cvtdq2ps: // llvm.x86.sse2.cvtdq2ps break;
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v4f32, MVT::v4i32); }
break; break;
case Intrinsic::ppc_altivec_vcfsx: // llvm.ppc.altivec.vcfsx case 'm': // 2 strings to match.
case Intrinsic::ppc_altivec_vcfux: // llvm.ppc.altivec.vcfux if (memcmp(NameR.data()+9, "askload.", 8))
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4f32, MVT::v4i32, MVT::i32 break;
); switch (NameR[17]) {
break; default: break;
case Intrinsic::x86_avx_vextractf128_ps_256: // llvm.x86.avx.vext case 'd': // 1 string to match.
ractf128.ps.256 return Intrinsic::x86_avx2_maskload_d; // "86.avx2.maskloa
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4f32, MVT::v8f32, MVT::i8) d.d"
; case 'q': // 1 string to match.
break; return Intrinsic::x86_avx2_maskload_q; // "86.avx2.maskloa
case Intrinsic::x86_vcvtph2ps_128: // llvm.x86.vcvtph2ps.128 d.q"
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v4f32, MVT::v8i16); }
break; break;
case Intrinsic::x86_avx_vbroadcast_sd_256: // llvm.x86.avx.vbro case 'p': // 3 strings to match.
adcast.sd.256 switch (NameR[9]) {
case Intrinsic::x86_avx_vbroadcastf128_pd_256: // llvm.x86. default: break;
avx.vbroadcastf128.pd.256 case 'm': // 1 string to match.
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v4f64, MVT::iPTR); if (memcmp(NameR.data()+10, "ul.hr.sw", 8))
break; break;
case Intrinsic::x86_avx_maskload_pd_256: // llvm.x86.avx.mask return Intrinsic::x86_avx2_pmul_hr_sw; // "86.avx2.pmul.hr
load.pd.256 .sw"
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4f64, MVT::iPTR, MVT::v4f6 case 's': // 2 strings to match.
4); switch (NameR[10]) {
break; default: break;
case Intrinsic::x86_avx2_vbroadcast_sd_pd_256: // llvm.x86. case 'l': // 1 string to match.
avx2.vbroadcast.sd.pd.256 if (memcmp(NameR.data()+11, "l.dq.bs", 7))
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v4f64, MVT::v2f64); break;
break; return Intrinsic::x86_avx2_psll_dq_bs; // "86.avx2.psll.dq
case Intrinsic::x86_avx_cvt_ps2_pd_256: // llvm.x86.avx.cvt. .bs"
ps2.pd.256 case 'r': // 1 string to match.
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v4f64, MVT::v4f32); if (memcmp(NameR.data()+11, "l.dq.bs", 7))
break; break;
case Intrinsic::x86_avx_sqrt_pd_256: // llvm.x86.avx.sqrt.pd.256 return Intrinsic::x86_avx2_psrl_dq_bs; // "86.avx2.psrl.dq
case Intrinsic::x86_xop_vfrcz_pd_256: // llvm.x86.xop.vfrc .bs"
z.pd.256 }
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v4f64, MVT::v4f64); break;
break; }
case Intrinsic::x86_avx_round_pd_256: // llvm.x86.avx.roun break;
d.pd.256 case 'v': // 1 string to match.
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4f64, MVT::v4f64, MVT::i32 if (memcmp(NameR.data()+9, "perm2i128", 9))
); break;
break; return Intrinsic::x86_avx2_vperm2i128; // "86.avx2.vperm2i
case Intrinsic::x86_avx_vinsertf128_pd_256: // llvm.x86.avx.vins 128"
ertf128.pd.256 }
VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v4f64, MVT::v4f64, MVT::v2f break;
64, MVT::i8); }
break; break;
case Intrinsic::x86_avx_addsub_pd_256: // llvm.x86.avx.adds case 's': // 13 strings to match.
ub.pd.256 if (memcmp(NameR.data()+4, "se", 2))
case Intrinsic::x86_avx_hadd_pd_256: // llvm.x86.avx.hadd.pd.256 break;
case Intrinsic::x86_avx_hsub_pd_256: // llvm.x86.avx.hsub.pd.256 switch (NameR[6]) {
case Intrinsic::x86_avx_max_pd_256: // llvm.x86.avx.max.pd.256 default: break;
case Intrinsic::x86_avx_min_pd_256: // llvm.x86.avx.min.pd.256 case '.': // 2 strings to match.
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4f64, MVT::v4f64, MVT::v4f switch (NameR[7]) {
64); default: break;
break; case 'c': // 1 string to match.
case Intrinsic::x86_avx_blend_pd_256: // llvm.x86.avx.blen if (memcmp(NameR.data()+8, "vttss2si64", 10))
d.pd.256 break;
VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v4f64, MVT::v4f64, MVT::v4f return Intrinsic::x86_sse_cvttss2si64; // "86.sse.cvttss2s
64, MVT::i32); i64"
break; case 'u': // 1 string to match.
case Intrinsic::x86_avx_cmp_pd_256: // llvm.x86.avx.cmp.pd.256 if (memcmp(NameR.data()+8, "comineq.ss", 10))
case Intrinsic::x86_avx_vperm2f128_pd_256: // llvm.x86.avx.vper break;
m2f128.pd.256 return Intrinsic::x86_sse_ucomineq_ss; // "86.sse.ucomineq
VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v4f64, MVT::v4f64, MVT::v4f .ss"
64, MVT::i8); }
break; break;
case Intrinsic::x86_avx_blendv_pd_256: // llvm.x86.avx.blen case '2': // 10 strings to match.
dv.pd.256 if (NameR[7] != '.')
case Intrinsic::x86_fma4_vfmadd_pd_256: // llvm.x86.fma4.vfm break;
add.pd.256 switch (NameR[8]) {
case Intrinsic::x86_fma4_vfmaddsub_pd_256: // llvm.x86.fma4.vfm default: break;
addsub.pd.256 case 'c': // 3 strings to match.
case Intrinsic::x86_fma4_vfmsub_pd_256: // llvm.x86.fma4.vfm switch (NameR[9]) {
sub.pd.256 default: break;
case Intrinsic::x86_fma4_vfmsubadd_pd_256: // llvm.x86.fma4.vfm case 'o': // 1 string to match.
subadd.pd.256 if (memcmp(NameR.data()+10, "mineq.sd", 8))
case Intrinsic::x86_fma4_vfnmadd_pd_256: // llvm.x86.fma4.vfn break;
madd.pd.256 return Intrinsic::x86_sse2_comineq_sd; // "86.sse2.comineq
case Intrinsic::x86_fma4_vfnmsub_pd_256: // llvm.x86.fma4.vfn .sd"
msub.pd.256 case 'v': // 2 strings to match.
VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v4f64, MVT::v4f64, MVT::v4f if (memcmp(NameR.data()+10, "ts", 2))
64, MVT::v4f64); break;
break; switch (NameR[12]) {
case Intrinsic::x86_xop_vpermil2pd_256: // llvm.x86.xop.vper default: break;
mil2pd.256 case 'd': // 1 string to match.
VerifyIntrinsicPrototype(ID, IF, 1, 4, MVT::v4f64, MVT::v4f64, MVT::v4f if (memcmp(NameR.data()+13, "2si64", 5))
64, MVT::v4f64, MVT::i8); break;
break; return Intrinsic::x86_sse2_cvtsd2si64; // "86.sse2.cvtsd2s
case Intrinsic::x86_avx_vpermilvar_pd_256: // llvm.x86.avx.vper i64"
milvar.pd.256 case 'i': // 1 string to match.
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4f64, MVT::v4f64, MVT::v4i if (memcmp(NameR.data()+13, "642sd", 5))
64); break;
break; return Intrinsic::x86_sse2_cvtsi642sd; // "86.sse2.cvtsi64
case Intrinsic::x86_avx_cvtdq2_pd_256: // llvm.x86.avx.cvtd 2sd"
q2.pd.256 }
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v4f64, MVT::v4i32); break;
break; }
case Intrinsic::arm_neon_vcvtfp2hf: // llvm.arm.neon.vcvtfp2hf break;
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v4i16, MVT::v4f32); case 'p': // 2 strings to match.
break; if (NameR[9] != 's')
case Intrinsic::ppc_altivec_lvewx: // llvm.ppc.altivec.lvewx break;
case Intrinsic::ppc_altivec_lvx: // llvm.ppc.altivec.lvx switch (NameR[10]) {
case Intrinsic::ppc_altivec_lvxl: // llvm.ppc.altivec.lvxl default: break;
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v4i32, MVT::iPTR); case 'l': // 1 string to match.
break; if (memcmp(NameR.data()+11, "l.dq.bs", 7))
case Intrinsic::x86_avx2_maskload_d: // llvm.x86.avx2.maskload.d break;
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4i32, MVT::iPTR, MVT::v4i3 return Intrinsic::x86_sse2_psll_dq_bs; // "86.sse2.psll.dq
2); .bs"
break; case 'r': // 1 string to match.
case Intrinsic::x86_sse41_pmovsxbd: // llvm.x86.sse41.pmovsxbd if (memcmp(NameR.data()+11, "l.dq.bs", 7))
case Intrinsic::x86_sse41_pmovzxbd: // llvm.x86.sse41.pmovzxbd break;
case Intrinsic::x86_xop_vphaddbd: // llvm.x86.xop.vphaddbd return Intrinsic::x86_sse2_psrl_dq_bs; // "86.sse2.psrl.dq
case Intrinsic::x86_xop_vphaddubd: // llvm.x86.xop.vphaddubd .bs"
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v4i32, MVT::v16i8); }
break; break;
case Intrinsic::ppc_altivec_vmsummbm: // llvm.ppc.altivec. case 'u': // 5 strings to match.
vmsummbm if (memcmp(NameR.data()+9, "comi", 4))
case Intrinsic::ppc_altivec_vmsumubm: // llvm.ppc.altivec. break;
vmsumubm switch (NameR[13]) {
VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v4i32, MVT::v16i8, MVT::v16 default: break;
i8, MVT::v4i32); case 'e': // 1 string to match.
break; if (memcmp(NameR.data()+14, "q.sd", 4))
case Intrinsic::ppc_altivec_vsum4sbs: // llvm.ppc.altivec. break;
vsum4sbs return Intrinsic::x86_sse2_ucomieq_sd; // "86.sse2.ucomieq
case Intrinsic::ppc_altivec_vsum4ubs: // llvm.ppc.altivec. .sd"
vsum4ubs case 'g': // 2 strings to match.
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4i32, MVT::v16i8, MVT::v4i switch (NameR[14]) {
32); default: break;
break; case 'e': // 1 string to match.
case Intrinsic::x86_sse2_cvtpd2dq: // llvm.x86.sse2.cvtpd2dq if (memcmp(NameR.data()+15, ".sd", 3))
case Intrinsic::x86_sse2_cvttpd2dq: // llvm.x86.sse2.cvttpd2dq break;
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v4i32, MVT::v2f64); return Intrinsic::x86_sse2_ucomige_sd; // "86.sse2.ucomige
break; .sd"
case Intrinsic::x86_sse2_cvtps2dq: // llvm.x86.sse2.cvtps2dq case 't': // 1 string to match.
case Intrinsic::x86_sse2_cvttps2dq: // llvm.x86.sse2.cvttps2dq if (memcmp(NameR.data()+15, ".sd", 3))
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v4i32, MVT::v4f32); break;
break; return Intrinsic::x86_sse2_ucomigt_sd; // "86.sse2.ucomigt
case Intrinsic::ppc_altivec_vctsxs: // llvm.ppc.altivec.vctsxs .sd"
case Intrinsic::ppc_altivec_vctuxs: // llvm.ppc.altivec.vctuxs }
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4i32, MVT::v4f32, MVT::i32 break;
); case 'l': // 2 strings to match.
break; switch (NameR[14]) {
case Intrinsic::arm_neon_vacgeq: // llvm.arm.neon.vacgeq default: break;
case Intrinsic::arm_neon_vacgtq: // llvm.arm.neon.vacgtq case 'e': // 1 string to match.
case Intrinsic::ppc_altivec_vcmpbfp: // llvm.ppc.altivec.vcmpbfp if (memcmp(NameR.data()+15, ".sd", 3))
case Intrinsic::ppc_altivec_vcmpeqfp: // llvm.ppc.altivec. break;
vcmpeqfp return Intrinsic::x86_sse2_ucomile_sd; // "86.sse2.ucomile
case Intrinsic::ppc_altivec_vcmpgefp: // llvm.ppc.altivec. .sd"
vcmpgefp case 't': // 1 string to match.
case Intrinsic::ppc_altivec_vcmpgtfp: // llvm.ppc.altivec. if (memcmp(NameR.data()+15, ".sd", 3))
vcmpgtfp break;
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4i32, MVT::v4f32, MVT::v4f return Intrinsic::x86_sse2_ucomilt_sd; // "86.sse2.ucomilt
32); .sd"
break; }
case Intrinsic::x86_avx_cvt_pd2dq_256: // llvm.x86.avx.cvt. break;
pd2dq.256 }
case Intrinsic::x86_avx_cvtt_pd2dq_256: // llvm.x86.avx.cvtt break;
.pd2dq.256 }
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v4i32, MVT::v4f64); break;
break; case '4': // 1 string to match.
case Intrinsic::x86_avx2_pbroadcastd_128: // llvm.x86.avx2.pbr if (memcmp(NameR.data()+7, "1.extractps", 11))
oadcastd.128 break;
case Intrinsic::x86_ssse3_pabs_d_128: // llvm.x86.ssse3.pa return Intrinsic::x86_sse41_extractps; // "86.sse41.extrac
bs.d.128 tps"
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v4i32, MVT::v4i32); }
break; break;
case Intrinsic::spu_si_shli: // llvm.spu.si.shli }
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4i32, MVT::v4i32, MVT::i8) break;
; case 19: // 41 strings to match.
break; if (memcmp(NameR.data()+0, "86.", 3))
case Intrinsic::spu_si_ai: // llvm.spu.si.ai break;
case Intrinsic::spu_si_andi: // llvm.spu.si.andi switch (NameR[3]) {
case Intrinsic::spu_si_ceqi: // llvm.spu.si.ceqi default: break;
case Intrinsic::spu_si_cgti: // llvm.spu.si.cgti case 'a': // 25 strings to match.
case Intrinsic::spu_si_clgti: // llvm.spu.si.clgti switch (NameR[4]) {
case Intrinsic::spu_si_ori: // llvm.spu.si.ori default: break;
case Intrinsic::spu_si_sfi: // llvm.spu.si.sfi case 'e': // 2 strings to match.
case Intrinsic::spu_si_xori: // llvm.spu.si.xori if (memcmp(NameR.data()+5, "sni.aes", 7))
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4i32, MVT::v4i32, MVT::i16 break;
); switch (NameR[12]) {
break; default: break;
case Intrinsic::x86_sse2_pslli_d: // llvm.x86.sse2.pslli.d case 'd': // 1 string to match.
case Intrinsic::x86_sse2_psrai_d: // llvm.x86.sse2.psrai.d if (memcmp(NameR.data()+13, "eclast", 6))
case Intrinsic::x86_sse2_psrli_d: // llvm.x86.sse2.psrli.d break;
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4i32, MVT::v4i32, MVT::i32 return Intrinsic::x86_aesni_aesdeclast; // "86.aesni.aesdec
); last"
break; case 'e': // 1 string to match.
case Intrinsic::ppc_altivec_vaddcuw: // llvm.ppc.altivec.vaddcuw if (memcmp(NameR.data()+13, "nclast", 6))
case Intrinsic::ppc_altivec_vaddsws: // llvm.ppc.altivec.vaddsws break;
case Intrinsic::ppc_altivec_vadduws: // llvm.ppc.altivec.vadduws return Intrinsic::x86_aesni_aesenclast; // "86.aesni.aesenc
case Intrinsic::ppc_altivec_vavgsw: // llvm.ppc.altivec.vavgsw last"
case Intrinsic::ppc_altivec_vavguw: // llvm.ppc.altivec.vavguw }
case Intrinsic::ppc_altivec_vcmpequw: // llvm.ppc.altivec. break;
vcmpequw case 'v': // 23 strings to match.
case Intrinsic::ppc_altivec_vcmpgtsw: // llvm.ppc.altivec. if (NameR[5] != 'x')
vcmpgtsw break;
case Intrinsic::ppc_altivec_vcmpgtuw: // llvm.ppc.altivec. switch (NameR[6]) {
vcmpgtuw default: break;
case Intrinsic::ppc_altivec_vmaxsw: // llvm.ppc.altivec.vmaxsw case '.': // 8 strings to match.
case Intrinsic::ppc_altivec_vmaxuw: // llvm.ppc.altivec.vmaxuw switch (NameR[7]) {
case Intrinsic::ppc_altivec_vminsw: // llvm.ppc.altivec.vminsw default: break;
case Intrinsic::ppc_altivec_vminuw: // llvm.ppc.altivec.vminuw case 'b': // 2 strings to match.
case Intrinsic::ppc_altivec_vrlw: // llvm.ppc.altivec.vrlw if (memcmp(NameR.data()+8, "lend.p", 6))
case Intrinsic::ppc_altivec_vsl: // llvm.ppc.altivec.vsl break;
case Intrinsic::ppc_altivec_vslo: // llvm.ppc.altivec.vslo switch (NameR[14]) {
case Intrinsic::ppc_altivec_vslw: // llvm.ppc.altivec.vslw default: break;
case Intrinsic::ppc_altivec_vsr: // llvm.ppc.altivec.vsr case 'd': // 1 string to match.
case Intrinsic::ppc_altivec_vsraw: // llvm.ppc.altivec.vsraw if (memcmp(NameR.data()+15, ".256", 4))
case Intrinsic::ppc_altivec_vsro: // llvm.ppc.altivec.vsro break;
case Intrinsic::ppc_altivec_vsrw: // llvm.ppc.altivec.vsrw return Intrinsic::x86_avx_blend_pd_256; // "86.avx.
case Intrinsic::ppc_altivec_vsubcuw: // llvm.ppc.altivec.vsubcuw blend.pd.256"
case Intrinsic::ppc_altivec_vsubsws: // llvm.ppc.altivec.vsubsws case 's': // 1 string to match.
case Intrinsic::ppc_altivec_vsubuws: // llvm.ppc.altivec.vsubuws if (memcmp(NameR.data()+15, ".256", 4))
case Intrinsic::ppc_altivec_vsum2sws: // llvm.ppc.altivec. break;
vsum2sws return Intrinsic::x86_avx_blend_ps_256; // "86.avx.
case Intrinsic::ppc_altivec_vsumsws: // llvm.ppc.altivec.vsumsws blend.ps.256"
case Intrinsic::spu_si_a: // llvm.spu.si.a }
case Intrinsic::spu_si_addx: // llvm.spu.si.addx break;
case Intrinsic::spu_si_and: // llvm.spu.si.and case 'm': // 2 strings to match.
case Intrinsic::spu_si_andc: // llvm.spu.si.andc if (memcmp(NameR.data()+8, "askstore.p", 10))
case Intrinsic::spu_si_bg: // llvm.spu.si.bg break;
case Intrinsic::spu_si_bgx: // llvm.spu.si.bgx switch (NameR[18]) {
case Intrinsic::spu_si_ceq: // llvm.spu.si.ceq default: break;
case Intrinsic::spu_si_cg: // llvm.spu.si.cg case 'd': // 1 string to match.
case Intrinsic::spu_si_cgt: // llvm.spu.si.cgt return Intrinsic::x86_avx_maskstore_pd; // "86.avx.
case Intrinsic::spu_si_cgx: // llvm.spu.si.cgx maskstore.pd"
case Intrinsic::spu_si_clgt: // llvm.spu.si.clgt case 's': // 1 string to match.
case Intrinsic::spu_si_nand: // llvm.spu.si.nand return Intrinsic::x86_avx_maskstore_ps; // "86.avx.
case Intrinsic::spu_si_nor: // llvm.spu.si.nor maskstore.ps"
case Intrinsic::spu_si_or: // llvm.spu.si.or }
case Intrinsic::spu_si_orc: // llvm.spu.si.orc break;
case Intrinsic::spu_si_sf: // llvm.spu.si.sf case 'p': // 1 string to match.
case Intrinsic::spu_si_sfx: // llvm.spu.si.sfx if (memcmp(NameR.data()+8, "testnzc.256", 11))
case Intrinsic::spu_si_xor: // llvm.spu.si.xor break;
case Intrinsic::x86_avx2_psllv_d: // llvm.x86.avx2.psllv.d return Intrinsic::x86_avx_ptestnzc_256; // "86.avx.ptestnzc
case Intrinsic::x86_avx2_psrav_d: // llvm.x86.avx2.psrav.d .256"
case Intrinsic::x86_avx2_psrlv_d: // llvm.x86.avx2.psrlv.d case 'r': // 3 strings to match.
case Intrinsic::x86_sse2_psll_d: // llvm.x86.sse2.psll.d switch (NameR[8]) {
case Intrinsic::x86_sse2_psra_d: // llvm.x86.sse2.psra.d default: break;
case Intrinsic::x86_sse2_psrl_d: // llvm.x86.sse2.psrl.d case 'o': // 2 strings to match.
case Intrinsic::x86_sse41_pmaxsd: // llvm.x86.sse41.pmaxsd if (memcmp(NameR.data()+9, "und.p", 5))
case Intrinsic::x86_sse41_pmaxud: // llvm.x86.sse41.pmaxud break;
case Intrinsic::x86_sse41_pminsd: // llvm.x86.sse41.pminsd switch (NameR[14]) {
case Intrinsic::x86_sse41_pminud: // llvm.x86.sse41.pminud default: break;
case Intrinsic::x86_ssse3_phadd_d_128: // llvm.x86.ssse3.ph case 'd': // 1 string to match.
add.d.128 if (memcmp(NameR.data()+15, ".256", 4))
case Intrinsic::x86_ssse3_phsub_d_128: // llvm.x86.ssse3.ph break;
sub.d.128 return Intrinsic::x86_avx_round_pd_256; // "86.avx.
case Intrinsic::x86_ssse3_psign_d_128: // llvm.x86.ssse3.ps round.pd.256"
ign.d.128 case 's': // 1 string to match.
case Intrinsic::x86_xop_vpcomeqd: // llvm.x86.xop.vpcomeqd if (memcmp(NameR.data()+15, ".256", 4))
case Intrinsic::x86_xop_vpcomequd: // llvm.x86.xop.vpcomequd break;
case Intrinsic::x86_xop_vpcomfalsed: // llvm.x86.xop.vpcomfalsed return Intrinsic::x86_avx_round_ps_256; // "86.avx.
case Intrinsic::x86_xop_vpcomfalseud: // llvm.x86.xop.vpco round.ps.256"
mfalseud }
case Intrinsic::x86_xop_vpcomged: // llvm.x86.xop.vpcomged break;
case Intrinsic::x86_xop_vpcomgeud: // llvm.x86.xop.vpcomgeud case 's': // 1 string to match.
case Intrinsic::x86_xop_vpcomgtd: // llvm.x86.xop.vpcomgtd if (memcmp(NameR.data()+9, "qrt.ps.256", 10))
case Intrinsic::x86_xop_vpcomgtud: // llvm.x86.xop.vpcomgtud break;
case Intrinsic::x86_xop_vpcomled: // llvm.x86.xop.vpcomled return Intrinsic::x86_avx_rsqrt_ps_256; // "86.avx.
case Intrinsic::x86_xop_vpcomleud: // llvm.x86.xop.vpcomleud rsqrt.ps.256"
case Intrinsic::x86_xop_vpcomltd: // llvm.x86.xop.vpcomltd }
case Intrinsic::x86_xop_vpcomltud: // llvm.x86.xop.vpcomltud break;
case Intrinsic::x86_xop_vpcomned: // llvm.x86.xop.vpcomned }
case Intrinsic::x86_xop_vpcomneud: // llvm.x86.xop.vpcomneud break;
case Intrinsic::x86_xop_vpcomtrued: // llvm.x86.xop.vpcomtrued case '2': // 15 strings to match.
case Intrinsic::x86_xop_vpcomtrueud: // llvm.x86.xop.vpcomtrueud if (NameR[7] != '.')
case Intrinsic::x86_xop_vprotd: // llvm.x86.xop.vprotd break;
case Intrinsic::x86_xop_vpshad: // llvm.x86.xop.vpshad switch (NameR[8]) {
case Intrinsic::x86_xop_vpshld: // llvm.x86.xop.vpshld default: break;
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4i32, MVT::v4i32, MVT::v4i case 'g': // 4 strings to match.
32); if (memcmp(NameR.data()+9, "ather.", 6))
break; break;
case Intrinsic::x86_avx2_pblendd_128: // llvm.x86.avx2.pbl switch (NameR[15]) {
endd.128 default: break;
VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v4i32, MVT::v4i32, MVT::v4i case 'd': // 2 strings to match.
32, MVT::i32); if (memcmp(NameR.data()+16, ".p", 2))
break; break;
case Intrinsic::ppc_altivec_vperm: // llvm.ppc.altivec.vperm switch (NameR[18]) {
VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v4i32, MVT::v4i32, MVT::v4i default: break;
32, MVT::v16i8); case 'd': // 1 string to match.
break; return Intrinsic::x86_avx2_gather_d_pd; // "86.avx2
case Intrinsic::ppc_altivec_vsel: // llvm.ppc.altivec.vsel .gather.d.pd"
case Intrinsic::x86_xop_vpmacsdd: // llvm.x86.xop.vpmacsdd case 's': // 1 string to match.
case Intrinsic::x86_xop_vpmacssdd: // llvm.x86.xop.vpmacssdd return Intrinsic::x86_avx2_gather_d_ps; // "86.avx2
VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v4i32, MVT::v4i32, MVT::v4i .gather.d.ps"
32, MVT::v4i32); }
break; break;
case Intrinsic::spu_si_mpyh: // llvm.spu.si.mpyh case 'q': // 2 strings to match.
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4i32, MVT::v4i32, MVT::v8i if (memcmp(NameR.data()+16, ".p", 2))
16); break;
break; switch (NameR[18]) {
case Intrinsic::ppc_altivec_vupkhpx: // llvm.ppc.altivec.vupkhpx default: break;
case Intrinsic::ppc_altivec_vupkhsh: // llvm.ppc.altivec.vupkhsh case 'd': // 1 string to match.
case Intrinsic::ppc_altivec_vupklpx: // llvm.ppc.altivec.vupklpx return Intrinsic::x86_avx2_gather_q_pd; // "86.avx2
case Intrinsic::ppc_altivec_vupklsh: // llvm.ppc.altivec.vupklsh .gather.q.pd"
case Intrinsic::x86_sse41_pmovsxwd: // llvm.x86.sse41.pmovsxwd case 's': // 1 string to match.
case Intrinsic::x86_sse41_pmovzxwd: // llvm.x86.sse41.pmovzxwd return Intrinsic::x86_avx2_gather_q_ps; // "86.avx2
case Intrinsic::x86_xop_vphadduwd: // llvm.x86.xop.vphadduwd .gather.q.ps"
case Intrinsic::x86_xop_vphaddwd: // llvm.x86.xop.vphaddwd }
case Intrinsic::x86_xop_vphsubwd: // llvm.x86.xop.vphsubwd break;
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v4i32, MVT::v8i16); }
break; break;
case Intrinsic::spu_si_mpyi: // llvm.spu.si.mpyi case 'm': // 2 strings to match.
case Intrinsic::spu_si_mpyui: // llvm.spu.si.mpyui if (memcmp(NameR.data()+9, "askstore.", 9))
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4i32, MVT::v8i16, MVT::i16 break;
); switch (NameR[18]) {
break; default: break;
case Intrinsic::ppc_altivec_vsum4shs: // llvm.ppc.altivec. case 'd': // 1 string to match.
vsum4shs return Intrinsic::x86_avx2_maskstore_d; // "86.avx2
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4i32, MVT::v8i16, MVT::v4i .maskstore.d"
32); case 'q': // 1 string to match.
break; return Intrinsic::x86_avx2_maskstore_q; // "86.avx2
case Intrinsic::ppc_altivec_vmulesh: // llvm.ppc.altivec.vmulesh .maskstore.q"
case Intrinsic::ppc_altivec_vmuleuh: // llvm.ppc.altivec.vmuleuh }
case Intrinsic::ppc_altivec_vmulosh: // llvm.ppc.altivec.vmulosh break;
case Intrinsic::ppc_altivec_vmulouh: // llvm.ppc.altivec.vmulouh case 'p': // 8 strings to match.
case Intrinsic::spu_si_mpy: // llvm.spu.si.mpy switch (NameR[9]) {
case Intrinsic::spu_si_mpyhh: // llvm.spu.si.mpyhh default: break;
case Intrinsic::spu_si_mpyhha: // llvm.spu.si.mpyhha case 'b': // 2 strings to match.
case Intrinsic::spu_si_mpyhhau: // llvm.spu.si.mpyhhau if (memcmp(NameR.data()+10, "lendd.", 6))
case Intrinsic::spu_si_mpyhhu: // llvm.spu.si.mpyhhu break;
case Intrinsic::spu_si_mpys: // llvm.spu.si.mpys switch (NameR[16]) {
case Intrinsic::spu_si_mpyu: // llvm.spu.si.mpyu default: break;
case Intrinsic::x86_sse2_pmadd_wd: // llvm.x86.sse2.pmadd.wd case '1': // 1 string to match.
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4i32, MVT::v8i16, MVT::v8i if (memcmp(NameR.data()+17, "28", 2))
16); break;
break; return Intrinsic::x86_avx2_pblendd_128; // "86.avx2
case Intrinsic::ppc_altivec_vmsumshm: // llvm.ppc.altivec. .pblendd.128"
vmsumshm case '2': // 1 string to match.
case Intrinsic::ppc_altivec_vmsumshs: // llvm.ppc.altivec. if (memcmp(NameR.data()+17, "56", 2))
vmsumshs break;
case Intrinsic::ppc_altivec_vmsumuhm: // llvm.ppc.altivec. return Intrinsic::x86_avx2_pblendd_256; // "86.avx2
vmsumuhm .pblendd.256"
case Intrinsic::ppc_altivec_vmsumuhs: // llvm.ppc.altivec. }
vmsumuhs break;
case Intrinsic::x86_xop_vpmacsswd: // llvm.x86.xop.vpmacsswd case 'm': // 1 string to match.
case Intrinsic::x86_xop_vpmacswd: // llvm.x86.xop.vpmacswd if (memcmp(NameR.data()+10, "add.ub.sw", 9))
case Intrinsic::x86_xop_vpmadcsswd: // llvm.x86.xop.vpmadcsswd break;
case Intrinsic::x86_xop_vpmadcswd: // llvm.x86.xop.vpmadcswd return Intrinsic::x86_avx2_pmadd_ub_sw; // "86.avx2
VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v4i32, MVT::v8i16, MVT::v8i .pmadd.ub.sw"
16, MVT::v4i32); case 's': // 5 strings to match.
break; switch (NameR[10]) {
case Intrinsic::spu_si_mpya: // llvm.spu.si.mpya default: break;
VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v4i32, MVT::v8i16, MVT::v8i case 'l': // 2 strings to match.
16, MVT::v8i16); if (memcmp(NameR.data()+11, "lv.", 3))
break; break;
case Intrinsic::x86_avx_vextractf128_si_256: // llvm.x86.avx.vext switch (NameR[14]) {
ractf128.si.256 default: break;
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4i32, MVT::v8i32, MVT::i8) case 'd': // 1 string to match.
; if (memcmp(NameR.data()+15, ".256", 4))
break; break;
case Intrinsic::x86_avx2_movntdqa: // llvm.x86.avx2.movntdqa return Intrinsic::x86_avx2_psllv_d_256; // "86.avx2
case Intrinsic::x86_avx2_vbroadcasti128: // llvm.x86.avx2.vbr .psllv.d.256"
oadcasti128 case 'q': // 1 string to match.
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v4i64, MVT::iPTR); if (memcmp(NameR.data()+15, ".256", 4))
break; break;
case Intrinsic::x86_avx2_maskload_q_256: // llvm.x86.avx2.mas return Intrinsic::x86_avx2_psllv_q_256; // "86.avx2
kload.q.256 .psllv.q.256"
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4i64, MVT::iPTR, MVT::v4i6 }
4); break;
break; case 'r': // 3 strings to match.
case Intrinsic::x86_avx2_pmovsxbq: // llvm.x86.avx2.pmovsxbq switch (NameR[11]) {
case Intrinsic::x86_avx2_pmovzxbq: // llvm.x86.avx2.pmovzxbq default: break;
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v4i64, MVT::v16i8); case 'a': // 1 string to match.
break; if (memcmp(NameR.data()+12, "v.d.256", 7))
case Intrinsic::x86_avx2_pbroadcastq_256: // llvm.x86.avx2.pbr break;
oadcastq.256 return Intrinsic::x86_avx2_psrav_d_256; // "86.avx2
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v4i64, MVT::v2i64); .psrav.d.256"
break; case 'l': // 2 strings to match.
case Intrinsic::x86_avx2_psad_bw: // llvm.x86.avx2.psad.bw if (memcmp(NameR.data()+12, "v.", 2))
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4i64, MVT::v32i8, MVT::v32 break;
i8); switch (NameR[14]) {
break; default: break;
case Intrinsic::x86_avx2_pmovsxdq: // llvm.x86.avx2.pmovsxdq case 'd': // 1 string to match.
case Intrinsic::x86_avx2_pmovzxdq: // llvm.x86.avx2.pmovzxdq if (memcmp(NameR.data()+15, ".256", 4))
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v4i64, MVT::v4i32); break;
break; return Intrinsic::x86_avx2_psrlv_d_256; // "86.avx2
case Intrinsic::x86_avx2_psll_dq: // llvm.x86.avx2.psll.dq .psrlv.d.256"
case Intrinsic::x86_avx2_psll_dq_bs: // llvm.x86.avx2.psll.dq.bs case 'q': // 1 string to match.
case Intrinsic::x86_avx2_pslli_q: // llvm.x86.avx2.pslli.q if (memcmp(NameR.data()+15, ".256", 4))
case Intrinsic::x86_avx2_psrl_dq: // llvm.x86.avx2.psrl.dq break;
case Intrinsic::x86_avx2_psrl_dq_bs: // llvm.x86.avx2.psrl.dq.bs return Intrinsic::x86_avx2_psrlv_q_256; // "86.avx2
case Intrinsic::x86_avx2_psrli_q: // llvm.x86.avx2.psrli.q .psrlv.q.256"
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4i64, MVT::v4i64, MVT::i32 }
); break;
break; }
case Intrinsic::x86_avx2_psll_q: // llvm.x86.avx2.psll.q break;
case Intrinsic::x86_avx2_psrl_q: // llvm.x86.avx2.psrl.q }
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4i64, MVT::v4i64, MVT::v2i break;
64); }
break; break;
case Intrinsic::x86_avx2_vinserti128: // llvm.x86.avx2.vin case 'v': // 1 string to match.
serti128 if (memcmp(NameR.data()+9, "inserti128", 10))
VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v4i64, MVT::v4i64, MVT::v2i break;
64, MVT::i8); return Intrinsic::x86_avx2_vinserti128; // "86.avx2.vinsert
break; i128"
case Intrinsic::x86_avx2_psllv_q_256: // llvm.x86.avx2.psl }
lv.q.256 break;
case Intrinsic::x86_avx2_psrlv_q_256: // llvm.x86.avx2.psr }
lv.q.256 break;
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4i64, MVT::v4i64, MVT::v4i }
64); break;
break; case 'f': // 4 strings to match.
case Intrinsic::x86_avx2_vperm2i128: // llvm.x86.avx2.vperm2i128 if (memcmp(NameR.data()+4, "ma.vfm", 6))
VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v4i64, MVT::v4i64, MVT::v4i break;
64, MVT::i8); switch (NameR[10]) {
break; default: break;
case Intrinsic::x86_xop_vpcmov_256: // llvm.x86.xop.vpcmov.256 case 'a': // 2 strings to match.
VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v4i64, MVT::v4i64, MVT::v4i if (memcmp(NameR.data()+11, "ddsub.p", 7))
64, MVT::v4i64); break;
break; switch (NameR[18]) {
case Intrinsic::x86_avx2_pmovsxwq: // llvm.x86.avx2.pmovsxwq default: break;
case Intrinsic::x86_avx2_pmovzxwq: // llvm.x86.avx2.pmovzxwq case 'd': // 1 string to match.
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v4i64, MVT::v8i16); return Intrinsic::x86_fma_vfmaddsub_pd; // "86.fma.vfmaddsu
break; b.pd"
case Intrinsic::x86_avx2_pmul_dq: // llvm.x86.avx2.pmul.dq case 's': // 1 string to match.
case Intrinsic::x86_avx2_pmulu_dq: // llvm.x86.avx2.pmulu.dq return Intrinsic::x86_fma_vfmaddsub_ps; // "86.fma.vfmaddsu
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4i64, MVT::v8i32, MVT::v8i b.ps"
32); }
break; break;
case Intrinsic::x86_avx_vbroadcast_ss_256: // llvm.x86.avx.vbro case 's': // 2 strings to match.
adcast.ss.256 if (memcmp(NameR.data()+11, "ubadd.p", 7))
case Intrinsic::x86_avx_vbroadcastf128_ps_256: // llvm.x86. break;
avx.vbroadcastf128.ps.256 switch (NameR[18]) {
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v8f32, MVT::iPTR); default: break;
break; case 'd': // 1 string to match.
case Intrinsic::x86_avx_maskload_ps_256: // llvm.x86.avx.mask return Intrinsic::x86_fma_vfmsubadd_pd; // "86.fma.vfmsubad
load.ps.256 d.pd"
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v8f32, MVT::iPTR, MVT::v8f3 case 's': // 1 string to match.
2); return Intrinsic::x86_fma_vfmsubadd_ps; // "86.fma.vfmsubad
break; d.ps"
case Intrinsic::x86_avx2_vbroadcast_ss_ps_256: // llvm.x86. }
avx2.vbroadcast.ss.ps.256 break;
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v8f32, MVT::v4f32); }
break; break;
case Intrinsic::x86_avx_rcp_ps_256: // llvm.x86.avx.rcp.ps.256 case 's': // 10 strings to match.
case Intrinsic::x86_avx_rsqrt_ps_256: // llvm.x86.avx.rsqr if (NameR[4] != 's')
t.ps.256 break;
case Intrinsic::x86_avx_sqrt_ps_256: // llvm.x86.avx.sqrt.ps.256 switch (NameR[5]) {
case Intrinsic::x86_xop_vfrcz_ps_256: // llvm.x86.xop.vfrc default: break;
z.ps.256 case 'e': // 6 strings to match.
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v8f32, MVT::v8f32); switch (NameR[6]) {
break; default: break;
case Intrinsic::x86_avx_round_ps_256: // llvm.x86.avx.roun case '2': // 3 strings to match.
d.ps.256 if (NameR[7] != '.')
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v8f32, MVT::v8f32, MVT::i32 break;
); switch (NameR[8]) {
break; default: break;
case Intrinsic::x86_avx_vinsertf128_ps_256: // llvm.x86.avx.vins case 'c': // 1 string to match.
ertf128.ps.256 if (memcmp(NameR.data()+9, "vttsd2si64", 10))
VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v8f32, MVT::v8f32, MVT::v4f break;
32, MVT::i8); return Intrinsic::x86_sse2_cvttsd2si64; // "86.sse2.cvttsd2
break; si64"
case Intrinsic::x86_avx2_permps: // llvm.x86.avx2.permps case 'm': // 1 string to match.
case Intrinsic::x86_avx_addsub_ps_256: // llvm.x86.avx.adds if (memcmp(NameR.data()+9, "askmov.dqu", 10))
ub.ps.256 break;
case Intrinsic::x86_avx_hadd_ps_256: // llvm.x86.avx.hadd.ps.256 return Intrinsic::x86_sse2_maskmov_dqu; // "86.sse2.maskmov
case Intrinsic::x86_avx_hsub_ps_256: // llvm.x86.avx.hsub.ps.256 .dqu"
case Intrinsic::x86_avx_max_ps_256: // llvm.x86.avx.max.ps.256 case 'u': // 1 string to match.
case Intrinsic::x86_avx_min_ps_256: // llvm.x86.avx.min.ps.256 if (memcmp(NameR.data()+9, "comineq.sd", 10))
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v8f32, MVT::v8f32, MVT::v8f break;
32); return Intrinsic::x86_sse2_ucomineq_sd; // "86.sse2.ucomine
break; q.sd"
case Intrinsic::x86_avx_blend_ps_256: // llvm.x86.avx.blen }
d.ps.256 break;
case Intrinsic::x86_avx_dp_ps_256: // llvm.x86.avx.dp.ps.256 case '4': // 3 strings to match.
VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v8f32, MVT::v8f32, MVT::v8f switch (NameR[7]) {
32, MVT::i32); default: break;
break; case '1': // 1 string to match.
case Intrinsic::x86_avx_cmp_ps_256: // llvm.x86.avx.cmp.ps.256 if (memcmp(NameR.data()+8, ".phminposuw", 11))
case Intrinsic::x86_avx_vperm2f128_ps_256: // llvm.x86.avx.vper break;
m2f128.ps.256 return Intrinsic::x86_sse41_phminposuw; // "86.sse41.phminp
VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v8f32, MVT::v8f32, MVT::v8f osuw"
32, MVT::i8); case '2': // 2 strings to match.
break; if (memcmp(NameR.data()+8, ".crc32.", 7))
case Intrinsic::x86_avx_blendv_ps_256: // llvm.x86.avx.blen break;
dv.ps.256 switch (NameR[15]) {
case Intrinsic::x86_fma4_vfmadd_ps_256: // llvm.x86.fma4.vfm default: break;
add.ps.256 case '3': // 1 string to match.
case Intrinsic::x86_fma4_vfmaddsub_ps_256: // llvm.x86.fma4.vfm if (memcmp(NameR.data()+16, "2.8", 3))
addsub.ps.256 break;
case Intrinsic::x86_fma4_vfmsub_ps_256: // llvm.x86.fma4.vfm return Intrinsic::x86_sse42_crc32_32_8; // "86.sse4
sub.ps.256 2.crc32.32.8"
case Intrinsic::x86_fma4_vfmsubadd_ps_256: // llvm.x86.fma4.vfm case '6': // 1 string to match.
subadd.ps.256 if (memcmp(NameR.data()+16, "4.8", 3))
case Intrinsic::x86_fma4_vfnmadd_ps_256: // llvm.x86.fma4.vfn break;
madd.ps.256 return Intrinsic::x86_sse42_crc32_64_8; // "86.sse4
case Intrinsic::x86_fma4_vfnmsub_ps_256: // llvm.x86.fma4.vfn 2.crc32.64.8"
msub.ps.256 }
VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v8f32, MVT::v8f32, MVT::v8f break;
32, MVT::v8f32); }
break; break;
case Intrinsic::x86_xop_vpermil2ps_256: // llvm.x86.xop.vper }
mil2ps.256 break;
VerifyIntrinsicPrototype(ID, IF, 1, 4, MVT::v8f32, MVT::v8f32, MVT::v8f case 's': // 4 strings to match.
32, MVT::v8f32, MVT::i8); if (memcmp(NameR.data()+6, "e3.p", 4))
break; break;
case Intrinsic::x86_avx_vpermilvar_ps_256: // llvm.x86.avx.vper switch (NameR[10]) {
milvar.ps.256 default: break;
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v8f32, MVT::v8f32, MVT::v8i case 'a': // 3 strings to match.
32); if (memcmp(NameR.data()+11, "bs.", 3))
break; break;
case Intrinsic::x86_vcvtph2ps_256: // llvm.x86.vcvtph2ps.256 switch (NameR[14]) {
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v8f32, MVT::v8i16); default: break;
break; case 'b': // 1 string to match.
case Intrinsic::x86_avx_cvtdq2_ps_256: // llvm.x86.avx.cvtd if (memcmp(NameR.data()+15, ".128", 4))
q2.ps.256 break;
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v8f32, MVT::v8i32); return Intrinsic::x86_ssse3_pabs_b_128; // "86.ssse3.pabs.b
break; .128"
case Intrinsic::ppc_altivec_mfvscr: // llvm.ppc.altivec.mfvscr case 'd': // 1 string to match.
VerifyIntrinsicPrototype(ID, IF, 1, 0, MVT::v8i16); if (memcmp(NameR.data()+15, ".128", 4))
break; break;
case Intrinsic::ppc_altivec_lvehx: // llvm.ppc.altivec.lvehx return Intrinsic::x86_ssse3_pabs_d_128; // "86.ssse3.pabs.d
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v8i16, MVT::iPTR); .128"
break; case 'w': // 1 string to match.
case Intrinsic::ppc_altivec_vupkhsb: // llvm.ppc.altivec.vupkhsb if (memcmp(NameR.data()+15, ".128", 4))
case Intrinsic::ppc_altivec_vupklsb: // llvm.ppc.altivec.vupklsb break;
case Intrinsic::x86_sse41_pmovsxbw: // llvm.x86.sse41.pmovsxbw return Intrinsic::x86_ssse3_pabs_w_128; // "86.ssse3.pabs.w
case Intrinsic::x86_sse41_pmovzxbw: // llvm.x86.sse41.pmovzxbw .128"
case Intrinsic::x86_xop_vphaddbw: // llvm.x86.xop.vphaddbw }
case Intrinsic::x86_xop_vphaddubw: // llvm.x86.xop.vphaddubw break;
case Intrinsic::x86_xop_vphsubbw: // llvm.x86.xop.vphsubbw case 'm': // 1 string to match.
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v8i16, MVT::v16i8); if (memcmp(NameR.data()+11, "ul.hr.sw", 8))
break; break;
case Intrinsic::ppc_altivec_vmulesb: // llvm.ppc.altivec.vmulesb return Intrinsic::x86_ssse3_pmul_hr_sw; // "86.ssse3.pmul.h
case Intrinsic::ppc_altivec_vmuleub: // llvm.ppc.altivec.vmuleub r.sw"
case Intrinsic::ppc_altivec_vmulosb: // llvm.ppc.altivec.vmulosb }
case Intrinsic::ppc_altivec_vmuloub: // llvm.ppc.altivec.vmuloub break;
case Intrinsic::x86_ssse3_pmadd_ub_sw_128: // llvm.x86.ssse3.pm }
add.ub.sw.128 break;
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v8i16, MVT::v16i8, MVT::v16 case 'x': // 2 strings to match.
i8); if (memcmp(NameR.data()+4, "op.vfrcz.p", 10))
break; break;
case Intrinsic::x86_sse41_mpsadbw: // llvm.x86.sse41.mpsadbw switch (NameR[14]) {
VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v8i16, MVT::v16i8, MVT::v16 default: break;
i8, MVT::i32); case 'd': // 1 string to match.
break; if (memcmp(NameR.data()+15, ".256", 4))
case Intrinsic::x86_vcvtps2ph_128: // llvm.x86.vcvtps2ph.128 break;
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v8i16, MVT::v4f32, MVT::i32 return Intrinsic::x86_xop_vfrcz_pd_256; // "86.xop.vfrcz.pd
); .256"
break; case 's': // 1 string to match.
case Intrinsic::ppc_altivec_vpkpx: // llvm.ppc.altivec.vpkpx if (memcmp(NameR.data()+15, ".256", 4))
case Intrinsic::ppc_altivec_vpkswus: // llvm.ppc.altivec.vpkswus break;
case Intrinsic::ppc_altivec_vpkuwus: // llvm.ppc.altivec.vpkuwus return Intrinsic::x86_xop_vfrcz_ps_256; // "86.xop.vfrcz.ps
case Intrinsic::x86_sse2_packssdw_128: // llvm.x86.sse2.pac .256"
kssdw.128 }
case Intrinsic::x86_sse41_packusdw: // llvm.x86.sse41.packusdw break;
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v8i16, MVT::v4i32, MVT::v4i }
32); break;
break; case 20: // 41 strings to match.
case Intrinsic::x86_vcvtps2ph_256: // llvm.x86.vcvtps2ph.256 if (memcmp(NameR.data()+0, "86.", 3))
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v8i16, MVT::v8f32, MVT::i32 break;
); switch (NameR[3]) {
break; default: break;
case Intrinsic::x86_avx2_pbroadcastw_128: // llvm.x86.avx2.pbr case 'a': // 21 strings to match.
oadcastw.128 if (memcmp(NameR.data()+4, "vx", 2))
case Intrinsic::x86_sse41_phminposuw: // llvm.x86.sse41.ph break;
minposuw switch (NameR[6]) {
case Intrinsic::x86_ssse3_pabs_w_128: // llvm.x86.ssse3.pa default: break;
bs.w.128 case '.': // 20 strings to match.
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v8i16, MVT::v8i16); switch (NameR[7]) {
break; default: break;
case Intrinsic::spu_si_ahi: // llvm.spu.si.ahi case 'a': // 2 strings to match.
case Intrinsic::spu_si_andhi: // llvm.spu.si.andhi if (memcmp(NameR.data()+8, "ddsub.p", 7))
case Intrinsic::spu_si_ceqhi: // llvm.spu.si.ceqhi break;
case Intrinsic::spu_si_cgthi: // llvm.spu.si.cgthi switch (NameR[15]) {
case Intrinsic::spu_si_clgthi: // llvm.spu.si.clgthi default: break;
case Intrinsic::spu_si_fsmbi: // llvm.spu.si.fsmbi case 'd': // 1 string to match.
case Intrinsic::spu_si_orhi: // llvm.spu.si.orhi if (memcmp(NameR.data()+16, ".256", 4))
case Intrinsic::spu_si_sfhi: // llvm.spu.si.sfhi break;
case Intrinsic::spu_si_xorhi: // llvm.spu.si.xorhi return Intrinsic::x86_avx_addsub_pd_256; // "86.avx.addsub.p
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v8i16, MVT::v8i16, MVT::i16 d.256"
); case 's': // 1 string to match.
break; if (memcmp(NameR.data()+16, ".256", 4))
case Intrinsic::spu_si_shlqbi: // llvm.spu.si.shlqbi break;
case Intrinsic::spu_si_shlqby: // llvm.spu.si.shlqby return Intrinsic::x86_avx_addsub_ps_256; // "86.avx.addsub.p
case Intrinsic::x86_sse2_pslli_w: // llvm.x86.sse2.pslli.w s.256"
case Intrinsic::x86_sse2_psrai_w: // llvm.x86.sse2.psrai.w }
case Intrinsic::x86_sse2_psrli_w: // llvm.x86.sse2.psrli.w break;
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v8i16, MVT::v8i16, MVT::i32 case 'b': // 2 strings to match.
); if (memcmp(NameR.data()+8, "lendv.p", 7))
break; break;
case Intrinsic::ppc_altivec_vaddshs: // llvm.ppc.altivec.vaddshs switch (NameR[15]) {
case Intrinsic::ppc_altivec_vadduhs: // llvm.ppc.altivec.vadduhs default: break;
case Intrinsic::ppc_altivec_vavgsh: // llvm.ppc.altivec.vavgsh case 'd': // 1 string to match.
case Intrinsic::ppc_altivec_vavguh: // llvm.ppc.altivec.vavguh if (memcmp(NameR.data()+16, ".256", 4))
case Intrinsic::ppc_altivec_vcmpequh: // llvm.ppc.altivec. break;
vcmpequh return Intrinsic::x86_avx_blendv_pd_256; // "86.avx.blendv.p
case Intrinsic::ppc_altivec_vcmpgtsh: // llvm.ppc.altivec. d.256"
vcmpgtsh case 's': // 1 string to match.
case Intrinsic::ppc_altivec_vcmpgtuh: // llvm.ppc.altivec. if (memcmp(NameR.data()+16, ".256", 4))
vcmpgtuh break;
case Intrinsic::ppc_altivec_vmaxsh: // llvm.ppc.altivec.vmaxsh return Intrinsic::x86_avx_blendv_ps_256; // "86.avx.blendv.p
case Intrinsic::ppc_altivec_vmaxuh: // llvm.ppc.altivec.vmaxuh s.256"
case Intrinsic::ppc_altivec_vminsh: // llvm.ppc.altivec.vminsh }
case Intrinsic::ppc_altivec_vminuh: // llvm.ppc.altivec.vminuh break;
case Intrinsic::ppc_altivec_vrlh: // llvm.ppc.altivec.vrlh case 'c': // 4 strings to match.
case Intrinsic::ppc_altivec_vslh: // llvm.ppc.altivec.vslh if (memcmp(NameR.data()+8, "vt", 2))
case Intrinsic::ppc_altivec_vsrah: // llvm.ppc.altivec.vsrah break;
case Intrinsic::ppc_altivec_vsrh: // llvm.ppc.altivec.vsrh switch (NameR[10]) {
case Intrinsic::ppc_altivec_vsubshs: // llvm.ppc.altivec.vsubshs default: break;
case Intrinsic::ppc_altivec_vsubuhs: // llvm.ppc.altivec.vsubuhs case '.': // 2 strings to match.
case Intrinsic::spu_si_ah: // llvm.spu.si.ah if (NameR[11] != 'p')
case Intrinsic::spu_si_ceqh: // llvm.spu.si.ceqh break;
case Intrinsic::spu_si_cgth: // llvm.spu.si.cgth switch (NameR[12]) {
case Intrinsic::spu_si_clgth: // llvm.spu.si.clgth default: break;
case Intrinsic::spu_si_sfh: // llvm.spu.si.sfh case 'd': // 1 string to match.
case Intrinsic::x86_sse2_padds_w: // llvm.x86.sse2.padds.w if (memcmp(NameR.data()+13, "2dq.256", 7))
case Intrinsic::x86_sse2_paddus_w: // llvm.x86.sse2.paddus.w break;
case Intrinsic::x86_sse2_pavg_w: // llvm.x86.sse2.pavg.w return Intrinsic::x86_avx_cvt_pd2dq_256; // "86.avx.
case Intrinsic::x86_sse2_pmaxs_w: // llvm.x86.sse2.pmaxs.w cvt.pd2dq.256"
case Intrinsic::x86_sse2_pmins_w: // llvm.x86.sse2.pmins.w case 's': // 1 string to match.
case Intrinsic::x86_sse2_pmulh_w: // llvm.x86.sse2.pmulh.w if (memcmp(NameR.data()+13, "2dq.256", 7))
case Intrinsic::x86_sse2_pmulhu_w: // llvm.x86.sse2.pmulhu.w break;
case Intrinsic::x86_sse2_psll_w: // llvm.x86.sse2.psll.w return Intrinsic::x86_avx_cvt_ps2dq_256; // "86.avx.
case Intrinsic::x86_sse2_psra_w: // llvm.x86.sse2.psra.w cvt.ps2dq.256"
case Intrinsic::x86_sse2_psrl_w: // llvm.x86.sse2.psrl.w }
case Intrinsic::x86_sse2_psubs_w: // llvm.x86.sse2.psubs.w break;
case Intrinsic::x86_sse2_psubus_w: // llvm.x86.sse2.psubus.w case 'd': // 2 strings to match.
case Intrinsic::x86_sse41_pmaxuw: // llvm.x86.sse41.pmaxuw if (memcmp(NameR.data()+11, "q2.p", 4))
case Intrinsic::x86_sse41_pminuw: // llvm.x86.sse41.pminuw break;
case Intrinsic::x86_ssse3_phadd_sw_128: // llvm.x86.ssse3.ph switch (NameR[15]) {
add.sw.128 default: break;
case Intrinsic::x86_ssse3_phadd_w_128: // llvm.x86.ssse3.ph case 'd': // 1 string to match.
add.w.128 if (memcmp(NameR.data()+16, ".256", 4))
case Intrinsic::x86_ssse3_phsub_sw_128: // llvm.x86.ssse3.ph break;
sub.sw.128 return Intrinsic::x86_avx_cvtdq2_pd_256; // "86.avx.
case Intrinsic::x86_ssse3_phsub_w_128: // llvm.x86.ssse3.ph cvtdq2.pd.256"
sub.w.128 case 's': // 1 string to match.
case Intrinsic::x86_ssse3_pmul_hr_sw_128: // llvm.x86.ssse3.pm if (memcmp(NameR.data()+16, ".256", 4))
ul.hr.sw.128 break;
case Intrinsic::x86_ssse3_psign_w_128: // llvm.x86.ssse3.ps return Intrinsic::x86_avx_cvtdq2_ps_256; // "86.avx.
ign.w.128 cvtdq2.ps.256"
case Intrinsic::x86_xop_vpcomequw: // llvm.x86.xop.vpcomequw }
case Intrinsic::x86_xop_vpcomeqw: // llvm.x86.xop.vpcomeqw break;
case Intrinsic::x86_xop_vpcomfalseuw: // llvm.x86.xop.vpco }
mfalseuw break;
case Intrinsic::x86_xop_vpcomfalsew: // llvm.x86.xop.vpcomfalsew case 'm': // 2 strings to match.
case Intrinsic::x86_xop_vpcomgeuw: // llvm.x86.xop.vpcomgeuw if (memcmp(NameR.data()+8, "ovmsk.p", 7))
case Intrinsic::x86_xop_vpcomgew: // llvm.x86.xop.vpcomgew break;
case Intrinsic::x86_xop_vpcomgtuw: // llvm.x86.xop.vpcomgtuw switch (NameR[15]) {
case Intrinsic::x86_xop_vpcomgtw: // llvm.x86.xop.vpcomgtw default: break;
case Intrinsic::x86_xop_vpcomleuw: // llvm.x86.xop.vpcomleuw case 'd': // 1 string to match.
case Intrinsic::x86_xop_vpcomlew: // llvm.x86.xop.vpcomlew if (memcmp(NameR.data()+16, ".256", 4))
case Intrinsic::x86_xop_vpcomltuw: // llvm.x86.xop.vpcomltuw break;
case Intrinsic::x86_xop_vpcomltw: // llvm.x86.xop.vpcomltw return Intrinsic::x86_avx_movmsk_pd_256; // "86.avx.movmsk.p
case Intrinsic::x86_xop_vpcomneuw: // llvm.x86.xop.vpcomneuw d.256"
case Intrinsic::x86_xop_vpcomnew: // llvm.x86.xop.vpcomnew case 's': // 1 string to match.
case Intrinsic::x86_xop_vpcomtrueuw: // llvm.x86.xop.vpcomtrueuw if (memcmp(NameR.data()+16, ".256", 4))
case Intrinsic::x86_xop_vpcomtruew: // llvm.x86.xop.vpcomtruew break;
case Intrinsic::x86_xop_vprotw: // llvm.x86.xop.vprotw return Intrinsic::x86_avx_movmsk_ps_256; // "86.avx.movmsk.p
case Intrinsic::x86_xop_vpshaw: // llvm.x86.xop.vpshaw s.256"
case Intrinsic::x86_xop_vpshlw: // llvm.x86.xop.vpshlw }
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v8i16, MVT::v8i16, MVT::v8i break;
16); case 's': // 3 strings to match.
break; if (memcmp(NameR.data()+8, "toreu.", 6))
case Intrinsic::x86_sse41_pblendw: // llvm.x86.sse41.pblendw break;
VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v8i16, MVT::v8i16, MVT::v8i switch (NameR[14]) {
16, MVT::i32); default: break;
break; case 'd': // 1 string to match.
case Intrinsic::ppc_altivec_vmhaddshs: // llvm.ppc.altivec. if (memcmp(NameR.data()+15, "q.256", 5))
vmhaddshs break;
case Intrinsic::ppc_altivec_vmhraddshs: // llvm.ppc.altivec. return Intrinsic::x86_avx_storeu_dq_256; // "86.avx.storeu.d
vmhraddshs q.256"
case Intrinsic::ppc_altivec_vmladduhm: // llvm.ppc.altivec. case 'p': // 2 strings to match.
vmladduhm switch (NameR[15]) {
case Intrinsic::x86_xop_vpmacssww: // llvm.x86.xop.vpmacssww default: break;
case Intrinsic::x86_xop_vpmacsww: // llvm.x86.xop.vpmacsww case 'd': // 1 string to match.
VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v8i16, MVT::v8i16, MVT::v8i if (memcmp(NameR.data()+16, ".256", 4))
16, MVT::v8i16); break;
break; return Intrinsic::x86_avx_storeu_pd_256; // "86.avx.
case Intrinsic::x86_avx2_maskload_d_256: // llvm.x86.avx2.mas storeu.pd.256"
kload.d.256 case 's': // 1 string to match.
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v8i32, MVT::iPTR, MVT::v8i3 if (memcmp(NameR.data()+16, ".256", 4))
2); break;
break; return Intrinsic::x86_avx_storeu_ps_256; // "86.avx.
case Intrinsic::x86_avx2_pmadd_wd: // llvm.x86.avx2.pmadd.wd storeu.ps.256"
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v8i32, MVT::v16i16, MVT::v1 }
6i16); break;
break; }
case Intrinsic::x86_avx2_pmovsxbd: // llvm.x86.avx2.pmovsxbd break;
case Intrinsic::x86_avx2_pmovzxbd: // llvm.x86.avx2.pmovzxbd case 'v': // 7 strings to match.
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v8i32, MVT::v16i8); switch (NameR[8]) {
break; default: break;
case Intrinsic::x86_avx2_pbroadcastd_256: // llvm.x86.avx2.pbr case 'b': // 1 string to match.
oadcastd.256 if (memcmp(NameR.data()+9, "roadcast.ss", 11))
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v8i32, MVT::v4i32); break;
break; return Intrinsic::x86_avx_vbroadcast_ss; // "86.avx.vbroadca
case Intrinsic::x86_avx_cvt_ps2dq_256: // llvm.x86.avx.cvt. st.ss"
ps2dq.256 case 'p': // 2 strings to match.
case Intrinsic::x86_avx_cvtt_ps2dq_256: // llvm.x86.avx.cvtt if (memcmp(NameR.data()+9, "ermilvar.p", 10))
.ps2dq.256 break;
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v8i32, MVT::v8f32); switch (NameR[19]) {
break; default: break;
case Intrinsic::x86_avx2_pmovsxwd: // llvm.x86.avx2.pmovsxwd case 'd': // 1 string to match.
case Intrinsic::x86_avx2_pmovzxwd: // llvm.x86.avx2.pmovzxwd return Intrinsic::x86_avx_vpermilvar_pd; // "86.avx.
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v8i32, MVT::v8i16); vpermilvar.pd"
break; case 's': // 1 string to match.
case Intrinsic::x86_avx2_pabs_d: // llvm.x86.avx2.pabs.d return Intrinsic::x86_avx_vpermilvar_ps; // "86.avx.
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v8i32, MVT::v8i32); vpermilvar.ps"
break; }
case Intrinsic::x86_avx2_pslli_d: // llvm.x86.avx2.pslli.d break;
case Intrinsic::x86_avx2_psrai_d: // llvm.x86.avx2.psrai.d case 't': // 4 strings to match.
case Intrinsic::x86_avx2_psrli_d: // llvm.x86.avx2.psrli.d if (memcmp(NameR.data()+9, "est", 3))
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v8i32, MVT::v8i32, MVT::i32 break;
); switch (NameR[12]) {
break; default: break;
case Intrinsic::x86_avx2_psll_d: // llvm.x86.avx2.psll.d case 'c': // 2 strings to match.
case Intrinsic::x86_avx2_psra_d: // llvm.x86.avx2.psra.d if (memcmp(NameR.data()+13, ".p", 2))
case Intrinsic::x86_avx2_psrl_d: // llvm.x86.avx2.psrl.d break;
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v8i32, MVT::v8i32, MVT::v4i switch (NameR[15]) {
32); default: break;
break; case 'd': // 1 string to match.
case Intrinsic::x86_avx_vinsertf128_si_256: // llvm.x86.avx.vins if (memcmp(NameR.data()+16, ".256", 4))
ertf128.si.256 break;
VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v8i32, MVT::v8i32, MVT::v4i return Intrinsic::x86_avx_vtestc_pd_256; // "86.avx.
32, MVT::i8); vtestc.pd.256"
break; case 's': // 1 string to match.
case Intrinsic::x86_avx2_permd: // llvm.x86.avx2.permd if (memcmp(NameR.data()+16, ".256", 4))
case Intrinsic::x86_avx2_phadd_d: // llvm.x86.avx2.phadd.d break;
case Intrinsic::x86_avx2_phsub_d: // llvm.x86.avx2.phsub.d return Intrinsic::x86_avx_vtestc_ps_256; // "86.avx.
case Intrinsic::x86_avx2_pmaxs_d: // llvm.x86.avx2.pmaxs.d vtestc.ps.256"
case Intrinsic::x86_avx2_pmaxu_d: // llvm.x86.avx2.pmaxu.d }
case Intrinsic::x86_avx2_pmins_d: // llvm.x86.avx2.pmins.d break;
case Intrinsic::x86_avx2_pminu_d: // llvm.x86.avx2.pminu.d case 'z': // 2 strings to match.
case Intrinsic::x86_avx2_psign_d: // llvm.x86.avx2.psign.d if (memcmp(NameR.data()+13, ".p", 2))
case Intrinsic::x86_avx2_psllv_d_256: // llvm.x86.avx2.psl break;
lv.d.256 switch (NameR[15]) {
case Intrinsic::x86_avx2_psrav_d_256: // llvm.x86.avx2.psr default: break;
av.d.256 case 'd': // 1 string to match.
case Intrinsic::x86_avx2_psrlv_d_256: // llvm.x86.avx2.psr if (memcmp(NameR.data()+16, ".256", 4))
lv.d.256 break;
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v8i32, MVT::v8i32, MVT::v8i return Intrinsic::x86_avx_vtestz_pd_256; // "86.avx.
32); vtestz.pd.256"
break; case 's': // 1 string to match.
case Intrinsic::x86_avx2_pblendd_256: // llvm.x86.avx2.pbl if (memcmp(NameR.data()+16, ".256", 4))
endd.256 break;
VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v8i32, MVT::v8i32, MVT::v8i return Intrinsic::x86_avx_vtestz_ps_256; // "86.avx.
32, MVT::i32); vtestz.ps.256"
break; }
case Intrinsic::x86_avx_vperm2f128_si_256: // llvm.x86.avx.vper break;
m2f128.si.256 }
VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v8i32, MVT::v8i32, MVT::v8i break;
32, MVT::i8); }
break; break;
case Intrinsic::arm_neon_vtbl1: // llvm.arm.neon.vtbl1 }
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v8i8, MVT::v8i8, MVT::v8i8) break;
; case '2': // 1 string to match.
break; if (memcmp(NameR.data()+7, ".vextracti128", 13))
case Intrinsic::arm_neon_vtbl2: // llvm.arm.neon.vtbl2 break;
case Intrinsic::arm_neon_vtbx1: // llvm.arm.neon.vtbx1 return Intrinsic::x86_avx2_vextracti128; // "86.avx2.vextrac
VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v8i8, MVT::v8i8, MVT::v8i8, ti128"
MVT::v8i8); }
break; break;
case Intrinsic::arm_neon_vtbl3: // llvm.arm.neon.vtbl3 case 'f': // 4 strings to match.
case Intrinsic::arm_neon_vtbx2: // llvm.arm.neon.vtbx2 if (memcmp(NameR.data()+4, "ma.vfm", 6))
VerifyIntrinsicPrototype(ID, IF, 1, 4, MVT::v8i8, MVT::v8i8, MVT::v8i8, break;
MVT::v8i8, MVT::v8i8); switch (NameR[10]) {
break; default: break;
case Intrinsic::arm_neon_vtbl4: // llvm.arm.neon.vtbl4 case 'a': // 2 strings to match.
case Intrinsic::arm_neon_vtbx3: // llvm.arm.neon.vtbx3 if (memcmp(NameR.data()+11, "dd.p", 4))
VerifyIntrinsicPrototype(ID, IF, 1, 5, MVT::v8i8, MVT::v8i8, MVT::v8i8, break;
MVT::v8i8, MVT::v8i8, MVT::v8i8); switch (NameR[15]) {
break; default: break;
case Intrinsic::arm_neon_vtbx4: // llvm.arm.neon.vtbx4 case 'd': // 1 string to match.
VerifyIntrinsicPrototype(ID, IF, 1, 6, MVT::v8i8, MVT::v8i8, MVT::v8i8, if (memcmp(NameR.data()+16, ".256", 4))
MVT::v8i8, MVT::v8i8, MVT::v8i8, MVT::v8i8); break;
break; return Intrinsic::x86_fma_vfmadd_pd_256; // "86.fma.vfmadd.p
case Intrinsic::x86_sse_cvtpd2pi: // llvm.x86.sse.cvtpd2pi d.256"
case Intrinsic::x86_sse_cvttpd2pi: // llvm.x86.sse.cvttpd2pi case 's': // 1 string to match.
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::x86mmx, MVT::v2f64); if (memcmp(NameR.data()+16, ".256", 4))
break; break;
case Intrinsic::x86_sse_cvtps2pi: // llvm.x86.sse.cvtps2pi return Intrinsic::x86_fma_vfmadd_ps_256; // "86.fma.vfmadd.p
case Intrinsic::x86_sse_cvttps2pi: // llvm.x86.sse.cvttps2pi s.256"
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::x86mmx, MVT::v4f32); }
break; break;
case Intrinsic::x86_3dnow_pf2id: // llvm.x86.3dnow.pf2id case 's': // 2 strings to match.
case Intrinsic::x86_3dnow_pfrcp: // llvm.x86.3dnow.pfrcp if (memcmp(NameR.data()+11, "ub.p", 4))
case Intrinsic::x86_3dnow_pfrsqrt: // llvm.x86.3dnow.pfrsqrt break;
case Intrinsic::x86_3dnow_pi2fd: // llvm.x86.3dnow.pi2fd switch (NameR[15]) {
case Intrinsic::x86_3dnowa_pf2iw: // llvm.x86.3dnowa.pf2iw default: break;
case Intrinsic::x86_3dnowa_pi2fw: // llvm.x86.3dnowa.pi2fw case 'd': // 1 string to match.
case Intrinsic::x86_3dnowa_pswapd: // llvm.x86.3dnowa.pswapd if (memcmp(NameR.data()+16, ".256", 4))
case Intrinsic::x86_ssse3_pabs_b: // llvm.x86.ssse3.pabs.b break;
case Intrinsic::x86_ssse3_pabs_d: // llvm.x86.ssse3.pabs.d return Intrinsic::x86_fma_vfmsub_pd_256; // "86.fma.vfmsub.p
case Intrinsic::x86_ssse3_pabs_w: // llvm.x86.ssse3.pabs.w d.256"
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::x86mmx, MVT::x86mmx); case 's': // 1 string to match.
break; if (memcmp(NameR.data()+16, ".256", 4))
case Intrinsic::x86_mmx_pslli_d: // llvm.x86.mmx.pslli.d break;
case Intrinsic::x86_mmx_pslli_q: // llvm.x86.mmx.pslli.q return Intrinsic::x86_fma_vfmsub_ps_256; // "86.fma.vfmsub.p
case Intrinsic::x86_mmx_pslli_w: // llvm.x86.mmx.pslli.w s.256"
case Intrinsic::x86_mmx_psrai_d: // llvm.x86.mmx.psrai.d }
case Intrinsic::x86_mmx_psrai_w: // llvm.x86.mmx.psrai.w break;
case Intrinsic::x86_mmx_psrli_d: // llvm.x86.mmx.psrli.d }
case Intrinsic::x86_mmx_psrli_q: // llvm.x86.mmx.psrli.q break;
case Intrinsic::x86_mmx_psrli_w: // llvm.x86.mmx.psrli.w case 's': // 16 strings to match.
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::x86mmx, MVT::x86mmx, MVT::i if (NameR[4] != 's')
32); break;
break; switch (NameR[5]) {
case Intrinsic::x86_mmx_pinsr_w: // llvm.x86.mmx.pinsr.w default: break;
VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::x86mmx, MVT::x86mmx, MVT::i case 'e': // 7 strings to match.
32, MVT::i32); switch (NameR[6]) {
break; default: break;
case Intrinsic::x86_sse_pshuf_w: // llvm.x86.sse.pshuf.w case '2': // 4 strings to match.
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::x86mmx, MVT::x86mmx, MVT::i if (memcmp(NameR.data()+7, ".p", 2))
8); break;
break; switch (NameR[9]) {
case Intrinsic::x86_3dnow_pavgusb: // llvm.x86.3dnow.pavgusb default: break;
case Intrinsic::x86_3dnow_pfacc: // llvm.x86.3dnow.pfacc case 'a': // 3 strings to match.
case Intrinsic::x86_3dnow_pfadd: // llvm.x86.3dnow.pfadd if (memcmp(NameR.data()+10, "ck", 2))
case Intrinsic::x86_3dnow_pfcmpeq: // llvm.x86.3dnow.pfcmpeq break;
case Intrinsic::x86_3dnow_pfcmpge: // llvm.x86.3dnow.pfcmpge switch (NameR[12]) {
case Intrinsic::x86_3dnow_pfcmpgt: // llvm.x86.3dnow.pfcmpgt default: break;
case Intrinsic::x86_3dnow_pfmax: // llvm.x86.3dnow.pfmax case 's': // 2 strings to match.
case Intrinsic::x86_3dnow_pfmin: // llvm.x86.3dnow.pfmin if (NameR[13] != 's')
case Intrinsic::x86_3dnow_pfmul: // llvm.x86.3dnow.pfmul break;
case Intrinsic::x86_3dnow_pfrcpit1: // llvm.x86.3dnow.pfrcpit1 switch (NameR[14]) {
case Intrinsic::x86_3dnow_pfrcpit2: // llvm.x86.3dnow.pfrcpit2 default: break;
case Intrinsic::x86_3dnow_pfrsqit1: // llvm.x86.3dnow.pfrsqit1 case 'd': // 1 string to match.
case Intrinsic::x86_3dnow_pfsub: // llvm.x86.3dnow.pfsub if (memcmp(NameR.data()+15, "w.128", 5))
case Intrinsic::x86_3dnow_pfsubr: // llvm.x86.3dnow.pfsubr break;
case Intrinsic::x86_3dnow_pmulhrw: // llvm.x86.3dnow.pmulhrw return Intrinsic::x86_sse2_packssdw_128; // "86.sse2
case Intrinsic::x86_3dnowa_pfnacc: // llvm.x86.3dnowa.pfnacc .packssdw.128"
case Intrinsic::x86_3dnowa_pfpnacc: // llvm.x86.3dnowa.pfpnacc case 'w': // 1 string to match.
case Intrinsic::x86_mmx_packssdw: // llvm.x86.mmx.packssdw if (memcmp(NameR.data()+15, "b.128", 5))
case Intrinsic::x86_mmx_packsswb: // llvm.x86.mmx.packsswb break;
case Intrinsic::x86_mmx_packuswb: // llvm.x86.mmx.packuswb return Intrinsic::x86_sse2_packsswb_128; // "86.sse2
case Intrinsic::x86_mmx_padd_b: // llvm.x86.mmx.padd.b .packsswb.128"
case Intrinsic::x86_mmx_padd_d: // llvm.x86.mmx.padd.d }
case Intrinsic::x86_mmx_padd_q: // llvm.x86.mmx.padd.q break;
case Intrinsic::x86_mmx_padd_w: // llvm.x86.mmx.padd.w case 'u': // 1 string to match.
case Intrinsic::x86_mmx_padds_b: // llvm.x86.mmx.padds.b if (memcmp(NameR.data()+13, "swb.128", 7))
case Intrinsic::x86_mmx_padds_w: // llvm.x86.mmx.padds.w break;
case Intrinsic::x86_mmx_paddus_b: // llvm.x86.mmx.paddus.b return Intrinsic::x86_sse2_packuswb_128; // "86.sse2
case Intrinsic::x86_mmx_paddus_w: // llvm.x86.mmx.paddus.w .packuswb.128"
case Intrinsic::x86_mmx_pand: // llvm.x86.mmx.pand }
case Intrinsic::x86_mmx_pandn: // llvm.x86.mmx.pandn break;
case Intrinsic::x86_mmx_pavg_b: // llvm.x86.mmx.pavg.b case 'm': // 1 string to match.
case Intrinsic::x86_mmx_pavg_w: // llvm.x86.mmx.pavg.w if (memcmp(NameR.data()+10, "ovmskb.128", 10))
case Intrinsic::x86_mmx_pcmpeq_b: // llvm.x86.mmx.pcmpeq.b break;
case Intrinsic::x86_mmx_pcmpeq_d: // llvm.x86.mmx.pcmpeq.d return Intrinsic::x86_sse2_pmovmskb_128; // "86.sse2.pmovmsk
case Intrinsic::x86_mmx_pcmpeq_w: // llvm.x86.mmx.pcmpeq.w b.128"
case Intrinsic::x86_mmx_pcmpgt_b: // llvm.x86.mmx.pcmpgt.b }
case Intrinsic::x86_mmx_pcmpgt_d: // llvm.x86.mmx.pcmpgt.d break;
case Intrinsic::x86_mmx_pcmpgt_w: // llvm.x86.mmx.pcmpgt.w case '4': // 3 strings to match.
case Intrinsic::x86_mmx_pmadd_wd: // llvm.x86.mmx.pmadd.wd if (memcmp(NameR.data()+7, "2.crc32.", 8))
case Intrinsic::x86_mmx_pmaxs_w: // llvm.x86.mmx.pmaxs.w break;
case Intrinsic::x86_mmx_pmaxu_b: // llvm.x86.mmx.pmaxu.b switch (NameR[15]) {
case Intrinsic::x86_mmx_pmins_w: // llvm.x86.mmx.pmins.w default: break;
case Intrinsic::x86_mmx_pminu_b: // llvm.x86.mmx.pminu.b case '3': // 2 strings to match.
case Intrinsic::x86_mmx_pmulh_w: // llvm.x86.mmx.pmulh.w if (memcmp(NameR.data()+16, "2.", 2))
case Intrinsic::x86_mmx_pmulhu_w: // llvm.x86.mmx.pmulhu.w break;
case Intrinsic::x86_mmx_pmull_w: // llvm.x86.mmx.pmull.w switch (NameR[18]) {
case Intrinsic::x86_mmx_pmulu_dq: // llvm.x86.mmx.pmulu.dq default: break;
case Intrinsic::x86_mmx_por: // llvm.x86.mmx.por case '1': // 1 string to match.
case Intrinsic::x86_mmx_psad_bw: // llvm.x86.mmx.psad.bw if (NameR[19] != '6')
case Intrinsic::x86_mmx_psll_d: // llvm.x86.mmx.psll.d break;
case Intrinsic::x86_mmx_psll_q: // llvm.x86.mmx.psll.q return Intrinsic::x86_sse42_crc32_32_16; // "86.sse4
case Intrinsic::x86_mmx_psll_w: // llvm.x86.mmx.psll.w 2.crc32.32.16"
case Intrinsic::x86_mmx_psra_d: // llvm.x86.mmx.psra.d case '3': // 1 string to match.
case Intrinsic::x86_mmx_psra_w: // llvm.x86.mmx.psra.w if (NameR[19] != '2')
case Intrinsic::x86_mmx_psrl_d: // llvm.x86.mmx.psrl.d break;
case Intrinsic::x86_mmx_psrl_q: // llvm.x86.mmx.psrl.q return Intrinsic::x86_sse42_crc32_32_32; // "86.sse4
case Intrinsic::x86_mmx_psrl_w: // llvm.x86.mmx.psrl.w 2.crc32.32.32"
case Intrinsic::x86_mmx_psub_b: // llvm.x86.mmx.psub.b }
case Intrinsic::x86_mmx_psub_d: // llvm.x86.mmx.psub.d break;
case Intrinsic::x86_mmx_psub_q: // llvm.x86.mmx.psub.q case '6': // 1 string to match.
case Intrinsic::x86_mmx_psub_w: // llvm.x86.mmx.psub.w if (memcmp(NameR.data()+16, "4.64", 4))
case Intrinsic::x86_mmx_psubs_b: // llvm.x86.mmx.psubs.b break;
case Intrinsic::x86_mmx_psubs_w: // llvm.x86.mmx.psubs.w return Intrinsic::x86_sse42_crc32_64_64; // "86.sse42.crc32.
case Intrinsic::x86_mmx_psubus_b: // llvm.x86.mmx.psubus.b 64.64"
case Intrinsic::x86_mmx_psubus_w: // llvm.x86.mmx.psubus.w }
case Intrinsic::x86_mmx_punpckhbw: // llvm.x86.mmx.punpckhbw break;
case Intrinsic::x86_mmx_punpckhdq: // llvm.x86.mmx.punpckhdq }
case Intrinsic::x86_mmx_punpckhwd: // llvm.x86.mmx.punpckhwd break;
case Intrinsic::x86_mmx_punpcklbw: // llvm.x86.mmx.punpcklbw case 's': // 9 strings to match.
case Intrinsic::x86_mmx_punpckldq: // llvm.x86.mmx.punpckldq if (memcmp(NameR.data()+6, "e3.p", 4))
case Intrinsic::x86_mmx_punpcklwd: // llvm.x86.mmx.punpcklwd break;
case Intrinsic::x86_mmx_pxor: // llvm.x86.mmx.pxor switch (NameR[10]) {
case Intrinsic::x86_ssse3_phadd_d: // llvm.x86.ssse3.phadd.d default: break;
case Intrinsic::x86_ssse3_phadd_sw: // llvm.x86.ssse3.phadd.sw case 'h': // 4 strings to match.
case Intrinsic::x86_ssse3_phadd_w: // llvm.x86.ssse3.phadd.w switch (NameR[11]) {
case Intrinsic::x86_ssse3_phsub_d: // llvm.x86.ssse3.phsub.d default: break;
case Intrinsic::x86_ssse3_phsub_sw: // llvm.x86.ssse3.phsub.sw case 'a': // 2 strings to match.
case Intrinsic::x86_ssse3_phsub_w: // llvm.x86.ssse3.phsub.w if (memcmp(NameR.data()+12, "dd.", 3))
case Intrinsic::x86_ssse3_pmadd_ub_sw: // llvm.x86.ssse3.pm break;
add.ub.sw switch (NameR[15]) {
case Intrinsic::x86_ssse3_pmul_hr_sw: // llvm.x86.ssse3.pm default: break;
ul.hr.sw case 'd': // 1 string to match.
case Intrinsic::x86_ssse3_pshuf_b: // llvm.x86.ssse3.pshuf.b if (memcmp(NameR.data()+16, ".128", 4))
case Intrinsic::x86_ssse3_psign_b: // llvm.x86.ssse3.psign.b break;
case Intrinsic::x86_ssse3_psign_d: // llvm.x86.ssse3.psign.d return Intrinsic::x86_ssse3_phadd_d_128; // "86.ssse
case Intrinsic::x86_ssse3_psign_w: // llvm.x86.ssse3.psign.w 3.phadd.d.128"
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::x86mmx, MVT::x86mmx, MVT::x case 'w': // 1 string to match.
86mmx); if (memcmp(NameR.data()+16, ".128", 4))
break; break;
case Intrinsic::x86_mmx_palignr_b: // llvm.x86.mmx.palignr.b return Intrinsic::x86_ssse3_phadd_w_128; // "86.ssse
VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::x86mmx, MVT::x86mmx, MVT::x 3.phadd.w.128"
86mmx, MVT::i8); }
break; break;
} case 's': // 2 strings to match.
#endif if (memcmp(NameR.data()+12, "ub.", 3))
break;
// Code for generating Intrinsic function declarations. switch (NameR[15]) {
#ifdef GET_INTRINSIC_GENERATOR default: break;
switch (id) { case 'd': // 1 string to match.
default: llvm_unreachable("Invalid intrinsic!"); if (memcmp(NameR.data()+16, ".128", 4))
case Intrinsic::eh_unwind_init: // llvm.eh.unwind.init break;
case Intrinsic::ppc_altivec_dssall: // llvm.ppc.altivec.dssall return Intrinsic::x86_ssse3_phsub_d_128; // "86.ssse
case Intrinsic::ppc_sync: // llvm.ppc.sync 3.phsub.d.128"
case Intrinsic::trap: // llvm.trap case 'w': // 1 string to match.
case Intrinsic::x86_avx_vzeroall: // llvm.x86.avx.vzeroall if (memcmp(NameR.data()+16, ".128", 4))
case Intrinsic::x86_avx_vzeroupper: // llvm.x86.avx.vzeroupper break;
case Intrinsic::x86_mmx_emms: // llvm.x86.mmx.emms return Intrinsic::x86_ssse3_phsub_w_128; // "86.ssse
case Intrinsic::x86_mmx_femms: // llvm.x86.mmx.femms 3.phsub.w.128"
case Intrinsic::x86_sse2_lfence: // llvm.x86.sse2.lfence }
case Intrinsic::x86_sse2_mfence: // llvm.x86.sse2.mfence break;
case Intrinsic::x86_sse_sfence: // llvm.x86.sse.sfence }
case Intrinsic::xcore_clre: // llvm.xcore.clre break;
case Intrinsic::xcore_ssync: // llvm.xcore.ssync case 'm': // 1 string to match.
ResultTy = Type::getVoidTy(Context); if (memcmp(NameR.data()+11, "add.ub.sw", 9))
break; break;
case Intrinsic::xcore_eeu: // llvm.xcore.eeu return Intrinsic::x86_ssse3_pmadd_ub_sw; // "86.ssse3.pmadd.
case Intrinsic::xcore_freer: // llvm.xcore.freer ub.sw"
case Intrinsic::xcore_mjoin: // llvm.xcore.mjoin case 's': // 4 strings to match.
case Intrinsic::xcore_msync: // llvm.xcore.msync switch (NameR[11]) {
case Intrinsic::xcore_syncr: // llvm.xcore.syncr default: break;
ResultTy = Type::getVoidTy(Context); case 'h': // 1 string to match.
ArgTys.push_back((0 < Tys.size()) ? Tys[0] : PointerType::getUnqual(Int if (memcmp(NameR.data()+12, "uf.b.128", 8))
egerType::get(Context, 8))); break;
break; return Intrinsic::x86_ssse3_pshuf_b_128; // "86.ssse3.pshuf.
case Intrinsic::xcore_setclk: // llvm.xcore.setclk b.128"
case Intrinsic::xcore_setrdy: // llvm.xcore.setrdy case 'i': // 3 strings to match.
ResultTy = Type::getVoidTy(Context); if (memcmp(NameR.data()+12, "gn.", 3))
ArgTys.push_back((0 < Tys.size()) ? Tys[0] : PointerType::getUnqual(Int break;
egerType::get(Context, 8))); switch (NameR[15]) {
ArgTys.push_back((1 < Tys.size()) ? Tys[1] : PointerType::getUnqual(Int default: break;
egerType::get(Context, 8))); case 'b': // 1 string to match.
break; if (memcmp(NameR.data()+16, ".128", 4))
case Intrinsic::memcpy: // llvm.memcpy break;
case Intrinsic::memmove: // llvm.memmove return Intrinsic::x86_ssse3_psign_b_128; // "86.ssse
ResultTy = Type::getVoidTy(Context); 3.psign.b.128"
ArgTys.push_back((0 < Tys.size()) ? Tys[0] : PointerType::getUnqual(Int case 'd': // 1 string to match.
egerType::get(Context, 8))); if (memcmp(NameR.data()+16, ".128", 4))
ArgTys.push_back((1 < Tys.size()) ? Tys[1] : PointerType::getUnqual(Int break;
egerType::get(Context, 8))); return Intrinsic::x86_ssse3_psign_d_128; // "86.ssse
ArgTys.push_back(Tys[2]); 3.psign.d.128"
ArgTys.push_back(IntegerType::get(Context, 32)); case 'w': // 1 string to match.
ArgTys.push_back(IntegerType::get(Context, 1)); if (memcmp(NameR.data()+16, ".128", 4))
break; break;
case Intrinsic::xcore_chkct: // llvm.xcore.chkct return Intrinsic::x86_ssse3_psign_w_128; // "86.ssse
case Intrinsic::xcore_out: // llvm.xcore.out 3.psign.w.128"
case Intrinsic::xcore_outct: // llvm.xcore.outct }
case Intrinsic::xcore_outt: // llvm.xcore.outt break;
case Intrinsic::xcore_setc: // llvm.xcore.setc }
case Intrinsic::xcore_setd: // llvm.xcore.setd break;
case Intrinsic::xcore_setpsc: // llvm.xcore.setpsc }
case Intrinsic::xcore_setpt: // llvm.xcore.setpt break;
case Intrinsic::xcore_settw: // llvm.xcore.settw }
ResultTy = Type::getVoidTy(Context); break;
ArgTys.push_back((0 < Tys.size()) ? Tys[0] : PointerType::getUnqual(Int }
egerType::get(Context, 8))); break;
ArgTys.push_back(IntegerType::get(Context, 32)); case 21: // 16 strings to match.
break; if (memcmp(NameR.data()+0, "86.", 3))
case Intrinsic::memset: // llvm.memset break;
ResultTy = Type::getVoidTy(Context); switch (NameR[3]) {
ArgTys.push_back((0 < Tys.size()) ? Tys[0] : PointerType::getUnqual(Int default: break;
egerType::get(Context, 8))); case 'a': // 4 strings to match.
ArgTys.push_back(IntegerType::get(Context, 8)); if (memcmp(NameR.data()+4, "vx.cvt", 6))
ArgTys.push_back(Tys[1]); break;
ArgTys.push_back(IntegerType::get(Context, 32)); switch (NameR[10]) {
ArgTys.push_back(IntegerType::get(Context, 1)); default: break;
break; case '.': // 2 strings to match.
case Intrinsic::xcore_initcp: // llvm.xcore.initcp if (NameR[11] != 'p')
case Intrinsic::xcore_initdp: // llvm.xcore.initdp break;
case Intrinsic::xcore_initlr: // llvm.xcore.initlr switch (NameR[12]) {
case Intrinsic::xcore_initpc: // llvm.xcore.initpc default: break;
case Intrinsic::xcore_initsp: // llvm.xcore.initsp case 'd': // 1 string to match.
case Intrinsic::xcore_setev: // llvm.xcore.setev if (memcmp(NameR.data()+13, "2.ps.256", 8))
case Intrinsic::xcore_setv: // llvm.xcore.setv break;
ResultTy = Type::getVoidTy(Context); return Intrinsic::x86_avx_cvt_pd2_ps_256; // "86.avx.cvt.pd2.
ArgTys.push_back((0 < Tys.size()) ? Tys[0] : PointerType::getUnqual(Int ps.256"
egerType::get(Context, 8))); case 's': // 1 string to match.
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8))); if (memcmp(NameR.data()+13, "2.pd.256", 8))
break; break;
case Intrinsic::invariant_end: // llvm.invariant.end return Intrinsic::x86_avx_cvt_ps2_pd_256; // "86.avx.cvt.ps2.
ResultTy = Type::getVoidTy(Context); pd.256"
ArgTys.push_back(PointerType::getUnqual(StructType::get(Context))); }
ArgTys.push_back(IntegerType::get(Context, 64)); break;
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8))); case 't': // 2 strings to match.
break; if (memcmp(NameR.data()+11, ".p", 2))
case Intrinsic::arm_set_fpscr: // llvm.arm.set.fpscr break;
case Intrinsic::eh_sjlj_callsite: // llvm.eh.sjlj.callsite switch (NameR[13]) {
case Intrinsic::pcmarker: // llvm.pcmarker default: break;
case Intrinsic::ppc_altivec_dss: // llvm.ppc.altivec.dss case 'd': // 1 string to match.
case Intrinsic::ptx_bar_sync: // llvm.ptx.bar.sync if (memcmp(NameR.data()+14, "2dq.256", 7))
case Intrinsic::x86_wrfsbase_32: // llvm.x86.wrfsbase.32 break;
case Intrinsic::x86_wrgsbase_32: // llvm.x86.wrgsbase.32 return Intrinsic::x86_avx_cvtt_pd2dq_256; // "86.avx.cvtt.pd2
case Intrinsic::xcore_clrsr: // llvm.xcore.clrsr dq.256"
case Intrinsic::xcore_setsr: // llvm.xcore.setsr case 's': // 1 string to match.
ResultTy = Type::getVoidTy(Context); if (memcmp(NameR.data()+14, "2dq.256", 7))
ArgTys.push_back(IntegerType::get(Context, 32)); break;
break; return Intrinsic::x86_avx_cvtt_ps2dq_256; // "86.avx.cvtt.ps2
case Intrinsic::x86_sse3_mwait: // llvm.x86.sse3.mwait dq.256"
case Intrinsic::xcore_setps: // llvm.xcore.setps }
ResultTy = Type::getVoidTy(Context); break;
ArgTys.push_back(IntegerType::get(Context, 32)); }
ArgTys.push_back(IntegerType::get(Context, 32)); break;
break; case 'f': // 4 strings to match.
case Intrinsic::arm_mcrr: // llvm.arm.mcrr if (memcmp(NameR.data()+4, "ma.vfnm", 7))
case Intrinsic::arm_mcrr2: // llvm.arm.mcrr2 break;
ResultTy = Type::getVoidTy(Context); switch (NameR[11]) {
ArgTys.push_back(IntegerType::get(Context, 32)); default: break;
ArgTys.push_back(IntegerType::get(Context, 32)); case 'a': // 2 strings to match.
ArgTys.push_back(IntegerType::get(Context, 32)); if (memcmp(NameR.data()+12, "dd.p", 4))
ArgTys.push_back(IntegerType::get(Context, 32)); break;
ArgTys.push_back(IntegerType::get(Context, 32)); switch (NameR[16]) {
break; default: break;
case Intrinsic::arm_cdp: // llvm.arm.cdp case 'd': // 1 string to match.
case Intrinsic::arm_cdp2: // llvm.arm.cdp2 if (memcmp(NameR.data()+17, ".256", 4))
case Intrinsic::arm_mcr: // llvm.arm.mcr break;
case Intrinsic::arm_mcr2: // llvm.arm.mcr2 return Intrinsic::x86_fma_vfnmadd_pd_256; // "86.fma.vfnmadd.
ResultTy = Type::getVoidTy(Context); pd.256"
ArgTys.push_back(IntegerType::get(Context, 32)); case 's': // 1 string to match.
ArgTys.push_back(IntegerType::get(Context, 32)); if (memcmp(NameR.data()+17, ".256", 4))
ArgTys.push_back(IntegerType::get(Context, 32)); break;
ArgTys.push_back(IntegerType::get(Context, 32)); return Intrinsic::x86_fma_vfnmadd_ps_256; // "86.fma.vfnmadd.
ArgTys.push_back(IntegerType::get(Context, 32)); ps.256"
ArgTys.push_back(IntegerType::get(Context, 32)); }
break; break;
case Intrinsic::eh_return_i32: // llvm.eh.return.i32 case 's': // 2 strings to match.
ResultTy = Type::getVoidTy(Context); if (memcmp(NameR.data()+12, "ub.p", 4))
ArgTys.push_back(IntegerType::get(Context, 32)); break;
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8))); switch (NameR[16]) {
break; default: break;
case Intrinsic::x86_wrfsbase_64: // llvm.x86.wrfsbase.64 case 'd': // 1 string to match.
case Intrinsic::x86_wrgsbase_64: // llvm.x86.wrgsbase.64 if (memcmp(NameR.data()+17, ".256", 4))
ResultTy = Type::getVoidTy(Context); break;
ArgTys.push_back(IntegerType::get(Context, 64)); return Intrinsic::x86_fma_vfnmsub_pd_256; // "86.fma.vfnmsub.
break; pd.256"
case Intrinsic::eh_return_i64: // llvm.eh.return.i64 case 's': // 1 string to match.
case Intrinsic::lifetime_end: // llvm.lifetime.end if (memcmp(NameR.data()+17, ".256", 4))
case Intrinsic::lifetime_start: // llvm.lifetime.start break;
ResultTy = Type::getVoidTy(Context); return Intrinsic::x86_fma_vfnmsub_ps_256; // "86.fma.vfnmsub.
ArgTys.push_back(IntegerType::get(Context, 64)); ps.256"
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8))); }
break; break;
case Intrinsic::x86_int: // llvm.x86.int }
ResultTy = Type::getVoidTy(Context); break;
ArgTys.push_back(IntegerType::get(Context, 8)); case 's': // 6 strings to match.
break; if (NameR[4] != 's')
case Intrinsic::dbg_value: // llvm.dbg.value break;
ResultTy = Type::getVoidTy(Context); switch (NameR[5]) {
ArgTys.push_back(Type::getMetadataTy(Context)); default: break;
ArgTys.push_back(IntegerType::get(Context, 64)); case 'e': // 4 strings to match.
ArgTys.push_back(Type::getMetadataTy(Context)); if (memcmp(NameR.data()+6, "42.pcmp", 7))
break; break;
case Intrinsic::dbg_declare: // llvm.dbg.declare switch (NameR[13]) {
ResultTy = Type::getVoidTy(Context); default: break;
ArgTys.push_back(Type::getMetadataTy(Context)); case 'e': // 2 strings to match.
ArgTys.push_back(Type::getMetadataTy(Context)); if (memcmp(NameR.data()+14, "str", 3))
break; break;
case Intrinsic::eh_sjlj_functioncontext: // llvm.eh.sjlj.func switch (NameR[17]) {
tioncontext default: break;
case Intrinsic::eh_sjlj_longjmp: // llvm.eh.sjlj.longjmp case 'i': // 1 string to match.
case Intrinsic::ppc_dcba: // llvm.ppc.dcba if (memcmp(NameR.data()+18, "128", 3))
case Intrinsic::ppc_dcbf: // llvm.ppc.dcbf break;
case Intrinsic::ppc_dcbi: // llvm.ppc.dcbi return Intrinsic::x86_sse42_pcmpestri128; // "86.sse4
case Intrinsic::ppc_dcbst: // llvm.ppc.dcbst 2.pcmpestri128"
case Intrinsic::ppc_dcbt: // llvm.ppc.dcbt case 'm': // 1 string to match.
case Intrinsic::ppc_dcbtst: // llvm.ppc.dcbtst if (memcmp(NameR.data()+18, "128", 3))
case Intrinsic::ppc_dcbz: // llvm.ppc.dcbz break;
case Intrinsic::ppc_dcbzl: // llvm.ppc.dcbzl return Intrinsic::x86_sse42_pcmpestrm128; // "86.sse4
case Intrinsic::stackrestore: // llvm.stackrestore 2.pcmpestrm128"
case Intrinsic::vaend: // llvm.va_end }
case Intrinsic::vastart: // llvm.va_start break;
case Intrinsic::x86_sse2_clflush: // llvm.x86.sse2.clflush case 'i': // 2 strings to match.
case Intrinsic::x86_sse_ldmxcsr: // llvm.x86.sse.ldmxcsr if (memcmp(NameR.data()+14, "str", 3))
case Intrinsic::x86_sse_stmxcsr: // llvm.x86.sse.stmxcsr break;
ResultTy = Type::getVoidTy(Context); switch (NameR[17]) {
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8))); default: break;
break; case 'i': // 1 string to match.
case Intrinsic::arm_neon_vst2: // llvm.arm.neon.vst2 if (memcmp(NameR.data()+18, "128", 3))
ResultTy = Type::getVoidTy(Context); break;
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8))); return Intrinsic::x86_sse42_pcmpistri128; // "86.sse4
ArgTys.push_back(Tys[0]); 2.pcmpistri128"
ArgTys.push_back(Tys[0]); case 'm': // 1 string to match.
ArgTys.push_back(IntegerType::get(Context, 32)); if (memcmp(NameR.data()+18, "128", 3))
break; break;
case Intrinsic::arm_neon_vst3: // llvm.arm.neon.vst3 return Intrinsic::x86_sse42_pcmpistrm128; // "86.sse4
ResultTy = Type::getVoidTy(Context); 2.pcmpistrm128"
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8))); }
ArgTys.push_back(Tys[0]); break;
ArgTys.push_back(Tys[0]); }
ArgTys.push_back(Tys[0]); break;
ArgTys.push_back(IntegerType::get(Context, 32)); case 's': // 2 strings to match.
break; if (memcmp(NameR.data()+6, "e3.ph", 5))
case Intrinsic::arm_neon_vst4: // llvm.arm.neon.vst4 break;
ResultTy = Type::getVoidTy(Context); switch (NameR[11]) {
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8))); default: break;
ArgTys.push_back(Tys[0]); case 'a': // 1 string to match.
ArgTys.push_back(Tys[0]); if (memcmp(NameR.data()+12, "dd.sw.128", 9))
ArgTys.push_back(Tys[0]); break;
ArgTys.push_back(Tys[0]); return Intrinsic::x86_ssse3_phadd_sw_128; // "86.ssse3.phadd.
ArgTys.push_back(IntegerType::get(Context, 32)); sw.128"
break; case 's': // 1 string to match.
case Intrinsic::arm_neon_vst2lane: // llvm.arm.neon.vst2lane if (memcmp(NameR.data()+12, "ub.sw.128", 9))
ResultTy = Type::getVoidTy(Context); break;
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8))); return Intrinsic::x86_ssse3_phsub_sw_128; // "86.ssse3.phsub.
ArgTys.push_back(Tys[0]); sw.128"
ArgTys.push_back(Tys[0]); }
ArgTys.push_back(IntegerType::get(Context, 32)); break;
ArgTys.push_back(IntegerType::get(Context, 32)); }
break; break;
case Intrinsic::arm_neon_vst3lane: // llvm.arm.neon.vst3lane case 'x': // 2 strings to match.
ResultTy = Type::getVoidTy(Context); if (memcmp(NameR.data()+4, "op.vpermil2p", 12))
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8))); break;
ArgTys.push_back(Tys[0]); switch (NameR[16]) {
ArgTys.push_back(Tys[0]); default: break;
ArgTys.push_back(Tys[0]); case 'd': // 1 string to match.
ArgTys.push_back(IntegerType::get(Context, 32)); if (memcmp(NameR.data()+17, ".256", 4))
ArgTys.push_back(IntegerType::get(Context, 32)); break;
break; return Intrinsic::x86_xop_vpermil2pd_256; // "86.xop.vpermil2
case Intrinsic::arm_neon_vst4lane: // llvm.arm.neon.vst4lane pd.256"
ResultTy = Type::getVoidTy(Context); case 's': // 1 string to match.
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8))); if (memcmp(NameR.data()+17, ".256", 4))
ArgTys.push_back(Tys[0]); break;
ArgTys.push_back(Tys[0]); return Intrinsic::x86_xop_vpermil2ps_256; // "86.xop.vpermil2
ArgTys.push_back(Tys[0]); ps.256"
ArgTys.push_back(Tys[0]); }
ArgTys.push_back(IntegerType::get(Context, 32)); break;
ArgTys.push_back(IntegerType::get(Context, 32)); }
break; break;
case Intrinsic::arm_neon_vst1: // llvm.arm.neon.vst1 case 22: // 21 strings to match.
ResultTy = Type::getVoidTy(Context); if (memcmp(NameR.data()+0, "86.", 3))
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8))); break;
ArgTys.push_back(Tys[0]); switch (NameR[3]) {
ArgTys.push_back(IntegerType::get(Context, 32)); default: break;
break; case 'a': // 11 strings to match.
case Intrinsic::longjmp: // llvm.longjmp if (memcmp(NameR.data()+4, "vx", 2))
case Intrinsic::siglongjmp: // llvm.siglongjmp break;
ResultTy = Type::getVoidTy(Context); switch (NameR[6]) {
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8))); default: break;
ArgTys.push_back(IntegerType::get(Context, 32)); case '.': // 4 strings to match.
break; switch (NameR[7]) {
case Intrinsic::ppc_altivec_dst: // llvm.ppc.altivec.dst default: break;
case Intrinsic::ppc_altivec_dstst: // llvm.ppc.altivec.dstst case 'm': // 2 strings to match.
case Intrinsic::ppc_altivec_dststt: // llvm.ppc.altivec.dststt if (memcmp(NameR.data()+8, "askload.p", 9))
case Intrinsic::ppc_altivec_dstt: // llvm.ppc.altivec.dstt break;
case Intrinsic::x86_sse3_monitor: // llvm.x86.sse3.monitor switch (NameR[17]) {
ResultTy = Type::getVoidTy(Context); default: break;
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8))); case 'd': // 1 string to match.
ArgTys.push_back(IntegerType::get(Context, 32)); if (memcmp(NameR.data()+18, ".256", 4))
ArgTys.push_back(IntegerType::get(Context, 32)); break;
break; return Intrinsic::x86_avx_maskload_pd_256; // "86.avx.
case Intrinsic::prefetch: // llvm.prefetch maskload.pd.256"
ResultTy = Type::getVoidTy(Context); case 's': // 1 string to match.
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8))); if (memcmp(NameR.data()+18, ".256", 4))
ArgTys.push_back(IntegerType::get(Context, 32)); break;
ArgTys.push_back(IntegerType::get(Context, 32)); return Intrinsic::x86_avx_maskload_ps_256; // "86.avx.
ArgTys.push_back(IntegerType::get(Context, 32)); maskload.ps.256"
break; }
case Intrinsic::vacopy: // llvm.va_copy break;
ResultTy = Type::getVoidTy(Context); case 'v': // 2 strings to match.
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8))); if (memcmp(NameR.data()+8, "testnzc.p", 9))
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8))); break;
break; switch (NameR[17]) {
case Intrinsic::init_trampoline: // llvm.init.trampoline default: break;
ResultTy = Type::getVoidTy(Context); case 'd': // 1 string to match.
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8))); if (memcmp(NameR.data()+18, ".256", 4))
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8))); break;
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8))); return Intrinsic::x86_avx_vtestnzc_pd_256; // "86.avx.
break; vtestnzc.pd.256"
case Intrinsic::var_annotation: // llvm.var.annotation case 's': // 1 string to match.
ResultTy = Type::getVoidTy(Context); if (memcmp(NameR.data()+18, ".256", 4))
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8))); break;
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8))); return Intrinsic::x86_avx_vtestnzc_ps_256; // "86.avx.
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8))); vtestnzc.ps.256"
ArgTys.push_back(IntegerType::get(Context, 32)); }
break; break;
case Intrinsic::gcwrite: // llvm.gcwrite }
ResultTy = Type::getVoidTy(Context); break;
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8))); case '2': // 7 strings to match.
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8))); if (NameR[7] != '.')
ArgTys.push_back(PointerType::getUnqual(PointerType::getUnqual(IntegerT break;
ype::get(Context, 8)))); switch (NameR[8]) {
break; default: break;
case Intrinsic::stackprotector: // llvm.stackprotector case 'g': // 4 strings to match.
ResultTy = Type::getVoidTy(Context); if (memcmp(NameR.data()+9, "ather.", 6))
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8))); break;
ArgTys.push_back(PointerType::getUnqual(PointerType::getUnqual(IntegerT switch (NameR[15]) {
ype::get(Context, 8)))); default: break;
break; case 'd': // 2 strings to match.
case Intrinsic::x86_sse2_storeu_dq: // llvm.x86.sse2.storeu.dq if (NameR[16] != '.')
ResultTy = Type::getVoidTy(Context); break;
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8))); switch (NameR[17]) {
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16)); default: break;
break; case 'd': // 1 string to match.
case Intrinsic::x86_sse2_storeu_pd: // llvm.x86.sse2.storeu.pd if (memcmp(NameR.data()+18, ".256", 4))
ResultTy = Type::getVoidTy(Context); break;
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8))); return Intrinsic::x86_avx2_gather_d_d_256; // "86.avx2
ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2)); .gather.d.d.256"
break; case 'q': // 1 string to match.
case Intrinsic::x86_avx_maskstore_pd: // llvm.x86.avx.mask if (memcmp(NameR.data()+18, ".256", 4))
store.pd break;
ResultTy = Type::getVoidTy(Context); return Intrinsic::x86_avx2_gather_d_q_256; // "86.avx2
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8))); .gather.d.q.256"
ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2)); }
ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2)); break;
break; case 'q': // 2 strings to match.
case Intrinsic::x86_avx2_maskstore_q: // llvm.x86.avx2.mas if (NameR[16] != '.')
kstore.q break;
ResultTy = Type::getVoidTy(Context); switch (NameR[17]) {
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8))); default: break;
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 2)); case 'd': // 1 string to match.
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 2)); if (memcmp(NameR.data()+18, ".256", 4))
break; break;
case Intrinsic::x86_avx_storeu_dq_256: // llvm.x86.avx.stor return Intrinsic::x86_avx2_gather_q_d_256; // "86.avx2
eu.dq.256 .gather.q.d.256"
ResultTy = Type::getVoidTy(Context); case 'q': // 1 string to match.
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8))); if (memcmp(NameR.data()+18, ".256", 4))
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 32)); break;
break; return Intrinsic::x86_avx2_gather_q_q_256; // "86.avx2
case Intrinsic::x86_sse_storeu_ps: // llvm.x86.sse.storeu.ps .gather.q.q.256"
ResultTy = Type::getVoidTy(Context); }
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8))); break;
ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4)); }
break; break;
case Intrinsic::x86_avx_maskstore_ps: // llvm.x86.avx.mask case 'm': // 2 strings to match.
store.ps if (memcmp(NameR.data()+9, "askload.", 8))
ResultTy = Type::getVoidTy(Context); break;
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8))); switch (NameR[17]) {
ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4)); default: break;
ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4)); case 'd': // 1 string to match.
break; if (memcmp(NameR.data()+18, ".256", 4))
case Intrinsic::x86_avx_movnt_pd_256: // llvm.x86.avx.movn break;
t.pd.256 return Intrinsic::x86_avx2_maskload_d_256; // "86.avx2
case Intrinsic::x86_avx_storeu_pd_256: // llvm.x86.avx.stor .maskload.d.256"
eu.pd.256 case 'q': // 1 string to match.
ResultTy = Type::getVoidTy(Context); if (memcmp(NameR.data()+18, ".256", 4))
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8))); break;
ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 4)); return Intrinsic::x86_avx2_maskload_q_256; // "86.avx2
break; .maskload.q.256"
case Intrinsic::x86_avx_maskstore_pd_256: // llvm.x86.avx.mask }
store.pd.256 break;
ResultTy = Type::getVoidTy(Context); case 'v': // 1 string to match.
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8))); if (memcmp(NameR.data()+9, "broadcasti128", 13))
ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 4)); break;
ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 4)); return Intrinsic::x86_avx2_vbroadcasti128; // "86.avx2.vbroadc
break; asti128"
case Intrinsic::x86_sse2_storel_dq: // llvm.x86.sse2.storel.dq }
ResultTy = Type::getVoidTy(Context); break;
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8))); }
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4)); break;
break; case 's': // 10 strings to match.
case Intrinsic::x86_avx2_maskstore_d: // llvm.x86.avx2.mas if (memcmp(NameR.data()+4, "se42.pcmp", 9))
kstore.d break;
ResultTy = Type::getVoidTy(Context); switch (NameR[13]) {
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8))); default: break;
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4)); case 'e': // 5 strings to match.
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4)); if (memcmp(NameR.data()+14, "stri", 4))
break; break;
case Intrinsic::x86_avx_movnt_dq_256: // llvm.x86.avx.movn switch (NameR[18]) {
t.dq.256 default: break;
ResultTy = Type::getVoidTy(Context); case 'a': // 1 string to match.
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8))); if (memcmp(NameR.data()+19, "128", 3))
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 4)); break;
break; return Intrinsic::x86_sse42_pcmpestria128; // "86.sse42.pcmpes
case Intrinsic::x86_avx2_maskstore_q_256: // llvm.x86.avx2.mas tria128"
kstore.q.256 case 'c': // 1 string to match.
ResultTy = Type::getVoidTy(Context); if (memcmp(NameR.data()+19, "128", 3))
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8))); break;
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 4)); return Intrinsic::x86_sse42_pcmpestric128; // "86.sse42.pcmpes
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 4)); tric128"
break; case 'o': // 1 string to match.
case Intrinsic::x86_avx_movnt_ps_256: // llvm.x86.avx.movn if (memcmp(NameR.data()+19, "128", 3))
t.ps.256 break;
case Intrinsic::x86_avx_storeu_ps_256: // llvm.x86.avx.stor return Intrinsic::x86_sse42_pcmpestrio128; // "86.sse42.pcmpes
eu.ps.256 trio128"
ResultTy = Type::getVoidTy(Context); case 's': // 1 string to match.
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8))); if (memcmp(NameR.data()+19, "128", 3))
ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 8)); break;
break; return Intrinsic::x86_sse42_pcmpestris128; // "86.sse42.pcmpes
case Intrinsic::x86_avx_maskstore_ps_256: // llvm.x86.avx.mask tris128"
store.ps.256 case 'z': // 1 string to match.
ResultTy = Type::getVoidTy(Context); if (memcmp(NameR.data()+19, "128", 3))
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8))); break;
ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 8)); return Intrinsic::x86_sse42_pcmpestriz128; // "86.sse42.pcmpes
ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 8)); triz128"
break; }
case Intrinsic::x86_avx2_maskstore_d_256: // llvm.x86.avx2.mas break;
kstore.d.256 case 'i': // 5 strings to match.
ResultTy = Type::getVoidTy(Context); if (memcmp(NameR.data()+14, "stri", 4))
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8))); break;
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 8)); switch (NameR[18]) {
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 8)); default: break;
break; case 'a': // 1 string to match.
case Intrinsic::gcroot: // llvm.gcroot if (memcmp(NameR.data()+19, "128", 3))
ResultTy = Type::getVoidTy(Context); break;
ArgTys.push_back(PointerType::getUnqual(PointerType::getUnqual(IntegerT return Intrinsic::x86_sse42_pcmpistria128; // "86.sse42.pcmpis
ype::get(Context, 8)))); tria128"
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8))); case 'c': // 1 string to match.
break; if (memcmp(NameR.data()+19, "128", 3))
case Intrinsic::x86_mmx_movnt_dq: // llvm.x86.mmx.movnt.dq break;
ResultTy = Type::getVoidTy(Context); return Intrinsic::x86_sse42_pcmpistric128; // "86.sse42.pcmpis
ArgTys.push_back(PointerType::getUnqual(Type::getX86_MMXTy(Context))); tric128"
ArgTys.push_back(Type::getX86_MMXTy(Context)); case 'o': // 1 string to match.
break; if (memcmp(NameR.data()+19, "128", 3))
case Intrinsic::ppc_altivec_stvebx: // llvm.ppc.altivec.stvebx break;
ResultTy = Type::getVoidTy(Context); return Intrinsic::x86_sse42_pcmpistrio128; // "86.sse42.pcmpis
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16)); trio128"
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8))); case 's': // 1 string to match.
break; if (memcmp(NameR.data()+19, "128", 3))
case Intrinsic::x86_sse2_maskmov_dqu: // llvm.x86.sse2.mas break;
kmov.dqu return Intrinsic::x86_sse42_pcmpistris128; // "86.sse42.pcmpis
ResultTy = Type::getVoidTy(Context); tris128"
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16)); case 'z': // 1 string to match.
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16)); if (memcmp(NameR.data()+19, "128", 3))
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8))); break;
break; return Intrinsic::x86_sse42_pcmpistriz128; // "86.sse42.pcmpis
case Intrinsic::ppc_altivec_mtvscr: // llvm.ppc.altivec.mtvscr triz128"
ResultTy = Type::getVoidTy(Context); }
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4)); break;
break; }
case Intrinsic::ppc_altivec_stvewx: // llvm.ppc.altivec.stvewx break;
case Intrinsic::ppc_altivec_stvx: // llvm.ppc.altivec.stvx }
case Intrinsic::ppc_altivec_stvxl: // llvm.ppc.altivec.stvxl break;
ResultTy = Type::getVoidTy(Context); case 23: // 21 strings to match.
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4)); if (memcmp(NameR.data()+0, "86.", 3))
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8))); break;
break; switch (NameR[3]) {
case Intrinsic::ppc_altivec_stvehx: // llvm.ppc.altivec.stvehx default: break;
ResultTy = Type::getVoidTy(Context); case 'a': // 16 strings to match.
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8)); if (memcmp(NameR.data()+4, "vx", 2))
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8))); break;
break; switch (NameR[6]) {
case Intrinsic::x86_mmx_maskmovq: // llvm.x86.mmx.maskmovq default: break;
ResultTy = Type::getVoidTy(Context); case '.': // 2 strings to match.
ArgTys.push_back(Type::getX86_MMXTy(Context)); if (memcmp(NameR.data()+7, "maskstore.p", 11))
ArgTys.push_back(Type::getX86_MMXTy(Context)); break;
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8))); switch (NameR[18]) {
break; default: break;
case Intrinsic::ptr_annotation: // llvm.ptr.annotation case 'd': // 1 string to match.
ResultTy = (0 < Tys.size()) ? Tys[0] : PointerType::getUnqual(Tys[0]); if (memcmp(NameR.data()+19, ".256", 4))
ArgTys.push_back(Tys[0]); break;
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8))); return Intrinsic::x86_avx_maskstore_pd_256; // "86.avx.
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8))); maskstore.pd.256"
ArgTys.push_back(IntegerType::get(Context, 32)); case 's': // 1 string to match.
break; if (memcmp(NameR.data()+19, ".256", 4))
case Intrinsic::sin: // llvm.sin break;
ResultTy = Tys[0]; return Intrinsic::x86_avx_maskstore_ps_256; // "86.avx.
ArgTys.push_back(Tys[0]); maskstore.ps.256"
break; }
case Intrinsic::cos: // llvm.cos break;
ResultTy = Tys[0]; case '2': // 14 strings to match.
ArgTys.push_back(Tys[0]); if (NameR[7] != '.')
break; break;
case Intrinsic::pow: // llvm.pow switch (NameR[8]) {
ResultTy = Tys[0]; default: break;
ArgTys.push_back(Tys[0]); case 'g': // 4 strings to match.
ArgTys.push_back(Tys[0]); if (memcmp(NameR.data()+9, "ather.", 6))
break; break;
case Intrinsic::log: // llvm.log switch (NameR[15]) {
ResultTy = Tys[0]; default: break;
ArgTys.push_back(Tys[0]); case 'd': // 2 strings to match.
break; if (memcmp(NameR.data()+16, ".p", 2))
case Intrinsic::log10: // llvm.log10 break;
ResultTy = Tys[0]; switch (NameR[18]) {
ArgTys.push_back(Tys[0]); default: break;
break; case 'd': // 1 string to match.
case Intrinsic::log2: // llvm.log2 if (memcmp(NameR.data()+19, ".256", 4))
ResultTy = Tys[0]; break;
ArgTys.push_back(Tys[0]); return Intrinsic::x86_avx2_gather_d_pd_256; // "86.avx2
break; .gather.d.pd.256"
case Intrinsic::exp: // llvm.exp case 's': // 1 string to match.
ResultTy = Tys[0]; if (memcmp(NameR.data()+19, ".256", 4))
ArgTys.push_back(Tys[0]); break;
break; return Intrinsic::x86_avx2_gather_d_ps_256; // "86.avx2
case Intrinsic::exp2: // llvm.exp2 .gather.d.ps.256"
ResultTy = Tys[0]; }
ArgTys.push_back(Tys[0]); break;
break; case 'q': // 2 strings to match.
case Intrinsic::fma: // llvm.fma if (memcmp(NameR.data()+16, ".p", 2))
ResultTy = Tys[0]; break;
ArgTys.push_back(Tys[0]); switch (NameR[18]) {
ArgTys.push_back(Tys[0]); default: break;
ArgTys.push_back(Tys[0]); case 'd': // 1 string to match.
break; if (memcmp(NameR.data()+19, ".256", 4))
case Intrinsic::sqrt: // llvm.sqrt break;
ResultTy = Tys[0]; return Intrinsic::x86_avx2_gather_q_pd_256; // "86.avx2
ArgTys.push_back(Tys[0]); .gather.q.pd.256"
break; case 's': // 1 string to match.
case Intrinsic::powi: // llvm.powi if (memcmp(NameR.data()+19, ".256", 4))
ResultTy = Tys[0]; break;
ArgTys.push_back(Tys[0]); return Intrinsic::x86_avx2_gather_q_ps_256; // "86.avx2
ArgTys.push_back(IntegerType::get(Context, 32)); .gather.q.ps.256"
break; }
case Intrinsic::convertff: // llvm.convertff break;
ResultTy = Tys[0]; }
ArgTys.push_back(Tys[1]); break;
ArgTys.push_back(IntegerType::get(Context, 32)); case 'm': // 2 strings to match.
ArgTys.push_back(IntegerType::get(Context, 32)); if (memcmp(NameR.data()+9, "askstore.", 9))
break; break;
case Intrinsic::arm_neon_vcvtfxs2fp: // llvm.arm.neon.vcvtfxs2fp switch (NameR[18]) {
case Intrinsic::arm_neon_vcvtfxu2fp: // llvm.arm.neon.vcvtfxu2fp default: break;
ResultTy = Tys[0]; case 'd': // 1 string to match.
ArgTys.push_back(Tys[1]); if (memcmp(NameR.data()+19, ".256", 4))
ArgTys.push_back(IntegerType::get(Context, 32)); break;
break; return Intrinsic::x86_avx2_maskstore_d_256; // "86.avx2
case Intrinsic::convertfsi: // llvm.convertfsi .maskstore.d.256"
case Intrinsic::convertfui: // llvm.convertfui case 'q': // 1 string to match.
ResultTy = Tys[0]; if (memcmp(NameR.data()+19, ".256", 4))
ArgTys.push_back(Tys[1]); break;
ArgTys.push_back(IntegerType::get(Context, 32)); return Intrinsic::x86_avx2_maskstore_q_256; // "86.avx2
ArgTys.push_back(IntegerType::get(Context, 32)); .maskstore.q.256"
break; }
case Intrinsic::expect: // llvm.expect break;
ResultTy = Tys[0]; case 'p': // 8 strings to match.
ArgTys.push_back(Tys[0]); if (memcmp(NameR.data()+9, "broadcast", 9))
ArgTys.push_back(Tys[0]); break;
break; switch (NameR[18]) {
case Intrinsic::bswap: // llvm.bswap default: break;
ResultTy = Tys[0]; case 'b': // 2 strings to match.
ArgTys.push_back(Tys[0]); if (NameR[19] != '.')
break; break;
case Intrinsic::ctpop: // llvm.ctpop switch (NameR[20]) {
ResultTy = Tys[0]; default: break;
ArgTys.push_back(Tys[0]); case '1': // 1 string to match.
break; if (memcmp(NameR.data()+21, "28", 2))
case Intrinsic::ctlz: // llvm.ctlz break;
ResultTy = Tys[0]; return Intrinsic::x86_avx2_pbroadcastb_128; // "86.avx2
ArgTys.push_back(Tys[0]); .pbroadcastb.128"
ArgTys.push_back(IntegerType::get(Context, 1)); case '2': // 1 string to match.
break; if (memcmp(NameR.data()+21, "56", 2))
case Intrinsic::cttz: // llvm.cttz break;
ResultTy = Tys[0]; return Intrinsic::x86_avx2_pbroadcastb_256; // "86.avx2
ArgTys.push_back(Tys[0]); .pbroadcastb.256"
ArgTys.push_back(IntegerType::get(Context, 1)); }
break; break;
case Intrinsic::annotation: // llvm.annotation case 'd': // 2 strings to match.
ResultTy = Tys[0]; if (NameR[19] != '.')
ArgTys.push_back(Tys[0]); break;
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8))); switch (NameR[20]) {
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8))); default: break;
ArgTys.push_back(IntegerType::get(Context, 32)); case '1': // 1 string to match.
break; if (memcmp(NameR.data()+21, "28", 2))
case Intrinsic::arm_neon_vcvtfp2fxs: // llvm.arm.neon.vcvtfp2fxs break;
case Intrinsic::arm_neon_vcvtfp2fxu: // llvm.arm.neon.vcvtfp2fxu return Intrinsic::x86_avx2_pbroadcastd_128; // "86.avx2
ResultTy = Tys[0]; .pbroadcastd.128"
ArgTys.push_back(Tys[1]); case '2': // 1 string to match.
ArgTys.push_back(IntegerType::get(Context, 32)); if (memcmp(NameR.data()+21, "56", 2))
break; break;
case Intrinsic::convertsif: // llvm.convertsif return Intrinsic::x86_avx2_pbroadcastd_256; // "86.avx2
case Intrinsic::convertuif: // llvm.convertuif .pbroadcastd.256"
ResultTy = Tys[0]; }
ArgTys.push_back(Tys[1]); break;
ArgTys.push_back(IntegerType::get(Context, 32)); case 'q': // 2 strings to match.
ArgTys.push_back(IntegerType::get(Context, 32)); if (NameR[19] != '.')
break; break;
case Intrinsic::convertss: // llvm.convertss switch (NameR[20]) {
case Intrinsic::convertsu: // llvm.convertsu default: break;
case Intrinsic::convertus: // llvm.convertus case '1': // 1 string to match.
case Intrinsic::convertuu: // llvm.convertuu if (memcmp(NameR.data()+21, "28", 2))
ResultTy = Tys[0]; break;
ArgTys.push_back(Tys[1]); return Intrinsic::x86_avx2_pbroadcastq_128; // "86.avx2
ArgTys.push_back(IntegerType::get(Context, 32)); .pbroadcastq.128"
ArgTys.push_back(IntegerType::get(Context, 32)); case '2': // 1 string to match.
break; if (memcmp(NameR.data()+21, "56", 2))
case Intrinsic::objectsize: // llvm.objectsize break;
ResultTy = Tys[0]; return Intrinsic::x86_avx2_pbroadcastq_256; // "86.avx2
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8))); .pbroadcastq.256"
ArgTys.push_back(IntegerType::get(Context, 1)); }
break; break;
case Intrinsic::sadd_with_overflow: // llvm.sadd.with.overflow case 'w': // 2 strings to match.
ResultTy = StructType::get(Tys[0], IntegerType::get(Context, 1), NULL) if (NameR[19] != '.')
; break;
ArgTys.push_back(Tys[0]); switch (NameR[20]) {
ArgTys.push_back(Tys[0]); default: break;
break; case '1': // 1 string to match.
case Intrinsic::uadd_with_overflow: // llvm.uadd.with.overflow if (memcmp(NameR.data()+21, "28", 2))
ResultTy = StructType::get(Tys[0], IntegerType::get(Context, 1), NULL) break;
; return Intrinsic::x86_avx2_pbroadcastw_128; // "86.avx2
ArgTys.push_back(Tys[0]); .pbroadcastw.128"
ArgTys.push_back(Tys[0]); case '2': // 1 string to match.
break; if (memcmp(NameR.data()+21, "56", 2))
case Intrinsic::ssub_with_overflow: // llvm.ssub.with.overflow break;
ResultTy = StructType::get(Tys[0], IntegerType::get(Context, 1), NULL) return Intrinsic::x86_avx2_pbroadcastw_256; // "86.avx2
; .pbroadcastw.256"
ArgTys.push_back(Tys[0]); }
ArgTys.push_back(Tys[0]); break;
break; }
case Intrinsic::usub_with_overflow: // llvm.usub.with.overflow break;
ResultTy = StructType::get(Tys[0], IntegerType::get(Context, 1), NULL) }
; break;
ArgTys.push_back(Tys[0]); }
ArgTys.push_back(Tys[0]); break;
break; case 'f': // 4 strings to match.
case Intrinsic::smul_with_overflow: // llvm.smul.with.overflow if (memcmp(NameR.data()+4, "ma.vfm", 6))
ResultTy = StructType::get(Tys[0], IntegerType::get(Context, 1), NULL) break;
; switch (NameR[10]) {
ArgTys.push_back(Tys[0]); default: break;
ArgTys.push_back(Tys[0]); case 'a': // 2 strings to match.
break; if (memcmp(NameR.data()+11, "ddsub.p", 7))
case Intrinsic::umul_with_overflow: // llvm.umul.with.overflow break;
ResultTy = StructType::get(Tys[0], IntegerType::get(Context, 1), NULL) switch (NameR[18]) {
; default: break;
ArgTys.push_back(Tys[0]); case 'd': // 1 string to match.
ArgTys.push_back(Tys[0]); if (memcmp(NameR.data()+19, ".256", 4))
break; break;
case Intrinsic::xcore_getst: // llvm.xcore.getst return Intrinsic::x86_fma_vfmaddsub_pd_256; // "86.fma.
ResultTy = (0 < Tys.size()) ? Tys[0] : PointerType::getUnqual(IntegerTy vfmaddsub.pd.256"
pe::get(Context, 8)); case 's': // 1 string to match.
ArgTys.push_back((1 < Tys.size()) ? Tys[1] : PointerType::getUnqual(Int if (memcmp(NameR.data()+19, ".256", 4))
egerType::get(Context, 8))); break;
break; return Intrinsic::x86_fma_vfmaddsub_ps_256; // "86.fma.
case Intrinsic::xcore_getr: // llvm.xcore.getr vfmaddsub.ps.256"
ResultTy = (0 < Tys.size()) ? Tys[0] : PointerType::getUnqual(IntegerTy }
pe::get(Context, 8)); break;
ArgTys.push_back(IntegerType::get(Context, 32)); case 's': // 2 strings to match.
break; if (memcmp(NameR.data()+11, "ubadd.p", 7))
case Intrinsic::arm_neon_vabs: // llvm.arm.neon.vabs break;
case Intrinsic::arm_neon_vcls: // llvm.arm.neon.vcls switch (NameR[18]) {
case Intrinsic::arm_neon_vclz: // llvm.arm.neon.vclz default: break;
case Intrinsic::arm_neon_vcnt: // llvm.arm.neon.vcnt case 'd': // 1 string to match.
case Intrinsic::arm_neon_vqabs: // llvm.arm.neon.vqabs if (memcmp(NameR.data()+19, ".256", 4))
case Intrinsic::arm_neon_vqneg: // llvm.arm.neon.vqneg break;
case Intrinsic::arm_neon_vrecpe: // llvm.arm.neon.vrecpe return Intrinsic::x86_fma_vfmsubadd_pd_256; // "86.fma.
case Intrinsic::arm_neon_vrsqrte: // llvm.arm.neon.vrsqrte vfmsubadd.pd.256"
ResultTy = Tys[0]; case 's': // 1 string to match.
ArgTys.push_back(Tys[0]); if (memcmp(NameR.data()+19, ".256", 4))
break; break;
case Intrinsic::arm_neon_vqmovns: // llvm.arm.neon.vqmovns return Intrinsic::x86_fma_vfmsubadd_ps_256; // "86.fma.
case Intrinsic::arm_neon_vqmovnsu: // llvm.arm.neon.vqmovnsu vfmsubadd.ps.256"
case Intrinsic::arm_neon_vqmovnu: // llvm.arm.neon.vqmovnu }
ResultTy = Tys[0]; break;
ArgTys.push_back(VectorType::getExtendedElementVectorType(dyn_cast<Vect }
orType>(Tys[0]))); break;
break; case 's': // 1 string to match.
case Intrinsic::arm_neon_vabds: // llvm.arm.neon.vabds if (memcmp(NameR.data()+4, "sse3.pmul.hr.sw.128", 19))
case Intrinsic::arm_neon_vabdu: // llvm.arm.neon.vabdu break;
case Intrinsic::arm_neon_vhadds: // llvm.arm.neon.vhadds return Intrinsic::x86_ssse3_pmul_hr_sw_128; // "86.ssse3.pmul.h
case Intrinsic::arm_neon_vhaddu: // llvm.arm.neon.vhaddu r.sw.128"
case Intrinsic::arm_neon_vhsubs: // llvm.arm.neon.vhsubs }
case Intrinsic::arm_neon_vhsubu: // llvm.arm.neon.vhsubu break;
case Intrinsic::arm_neon_vmaxs: // llvm.arm.neon.vmaxs case 24: // 10 strings to match.
case Intrinsic::arm_neon_vmaxu: // llvm.arm.neon.vmaxu if (memcmp(NameR.data()+0, "86.", 3))
case Intrinsic::arm_neon_vmins: // llvm.arm.neon.vmins break;
case Intrinsic::arm_neon_vminu: // llvm.arm.neon.vminu switch (NameR[3]) {
case Intrinsic::arm_neon_vmulp: // llvm.arm.neon.vmulp default: break;
case Intrinsic::arm_neon_vpadd: // llvm.arm.neon.vpadd case 'a': // 9 strings to match.
case Intrinsic::arm_neon_vpmaxs: // llvm.arm.neon.vpmaxs switch (NameR[4]) {
case Intrinsic::arm_neon_vpmaxu: // llvm.arm.neon.vpmaxu default: break;
case Intrinsic::arm_neon_vpmins: // llvm.arm.neon.vpmins case 'e': // 1 string to match.
case Intrinsic::arm_neon_vpminu: // llvm.arm.neon.vpminu if (memcmp(NameR.data()+5, "sni.aeskeygenassist", 19))
case Intrinsic::arm_neon_vqadds: // llvm.arm.neon.vqadds break;
case Intrinsic::arm_neon_vqaddu: // llvm.arm.neon.vqaddu return Intrinsic::x86_aesni_aeskeygenassist; // "86.aesni.aeskey
case Intrinsic::arm_neon_vqdmulh: // llvm.arm.neon.vqdmulh genassist"
case Intrinsic::arm_neon_vqrdmulh: // llvm.arm.neon.vqrdmulh case 'v': // 8 strings to match.
case Intrinsic::arm_neon_vqrshifts: // llvm.arm.neon.vqrshifts if (NameR[5] != 'x')
case Intrinsic::arm_neon_vqrshiftu: // llvm.arm.neon.vqrshiftu break;
case Intrinsic::arm_neon_vqshifts: // llvm.arm.neon.vqshifts switch (NameR[6]) {
case Intrinsic::arm_neon_vqshiftsu: // llvm.arm.neon.vqshiftsu default: break;
case Intrinsic::arm_neon_vqshiftu: // llvm.arm.neon.vqshiftu case '.': // 7 strings to match.
case Intrinsic::arm_neon_vqsubs: // llvm.arm.neon.vqsubs if (NameR[7] != 'v')
case Intrinsic::arm_neon_vqsubu: // llvm.arm.neon.vqsubu break;
case Intrinsic::arm_neon_vrecps: // llvm.arm.neon.vrecps switch (NameR[8]) {
case Intrinsic::arm_neon_vrhadds: // llvm.arm.neon.vrhadds default: break;
case Intrinsic::arm_neon_vrhaddu: // llvm.arm.neon.vrhaddu case 'b': // 2 strings to match.
case Intrinsic::arm_neon_vrshifts: // llvm.arm.neon.vrshifts if (memcmp(NameR.data()+9, "roadcast.s", 10))
case Intrinsic::arm_neon_vrshiftu: // llvm.arm.neon.vrshiftu break;
case Intrinsic::arm_neon_vrsqrts: // llvm.arm.neon.vrsqrts switch (NameR[19]) {
case Intrinsic::arm_neon_vshifts: // llvm.arm.neon.vshifts default: break;
case Intrinsic::arm_neon_vshiftu: // llvm.arm.neon.vshiftu case 'd': // 1 string to match.
ResultTy = Tys[0]; if (memcmp(NameR.data()+20, ".256", 4))
ArgTys.push_back(Tys[0]); break;
ArgTys.push_back(Tys[0]); return Intrinsic::x86_avx_vbroadcast_sd_256; // "86.avx.
break; vbroadcast.sd.256"
case Intrinsic::arm_neon_vaddhn: // llvm.arm.neon.vaddhn case 's': // 1 string to match.
case Intrinsic::arm_neon_vqrshiftns: // llvm.arm.neon.vqrshiftns if (memcmp(NameR.data()+20, ".256", 4))
case Intrinsic::arm_neon_vqrshiftnsu: // llvm.arm.neon.vqr break;
shiftnsu return Intrinsic::x86_avx_vbroadcast_ss_256; // "86.avx.
case Intrinsic::arm_neon_vqrshiftnu: // llvm.arm.neon.vqrshiftnu vbroadcast.ss.256"
case Intrinsic::arm_neon_vqshiftns: // llvm.arm.neon.vqshiftns }
case Intrinsic::arm_neon_vqshiftnsu: // llvm.arm.neon.vqshiftnsu break;
case Intrinsic::arm_neon_vqshiftnu: // llvm.arm.neon.vqshiftnu case 'p': // 5 strings to match.
case Intrinsic::arm_neon_vraddhn: // llvm.arm.neon.vraddhn if (memcmp(NameR.data()+9, "erm", 3))
case Intrinsic::arm_neon_vrshiftn: // llvm.arm.neon.vrshiftn break;
case Intrinsic::arm_neon_vrsubhn: // llvm.arm.neon.vrsubhn switch (NameR[12]) {
case Intrinsic::arm_neon_vshiftn: // llvm.arm.neon.vshiftn default: break;
case Intrinsic::arm_neon_vsubhn: // llvm.arm.neon.vsubhn case '2': // 3 strings to match.
ResultTy = Tys[0]; if (memcmp(NameR.data()+13, "f128.", 5))
ArgTys.push_back(VectorType::getExtendedElementVectorType(dyn_cast<Vect break;
orType>(Tys[0]))); switch (NameR[18]) {
ArgTys.push_back(VectorType::getExtendedElementVectorType(dyn_cast<Vect default: break;
orType>(Tys[0]))); case 'p': // 2 strings to match.
break; switch (NameR[19]) {
case Intrinsic::arm_neon_vmullp: // llvm.arm.neon.vmullp default: break;
case Intrinsic::arm_neon_vmulls: // llvm.arm.neon.vmulls case 'd': // 1 string to match.
case Intrinsic::arm_neon_vmullu: // llvm.arm.neon.vmullu if (memcmp(NameR.data()+20, ".256", 4))
case Intrinsic::arm_neon_vqdmull: // llvm.arm.neon.vqdmull break;
case Intrinsic::arm_neon_vshiftls: // llvm.arm.neon.vshiftls return Intrinsic::x86_avx_vperm2f128_pd_256; //
case Intrinsic::arm_neon_vshiftlu: // llvm.arm.neon.vshiftlu "86.avx.vperm2f128.pd.256"
ResultTy = Tys[0]; case 's': // 1 string to match.
ArgTys.push_back(VectorType::getTruncatedElementVectorType(dyn_cast<Vec if (memcmp(NameR.data()+20, ".256", 4))
torType>(Tys[0]))); break;
ArgTys.push_back(VectorType::getTruncatedElementVectorType(dyn_cast<Vec return Intrinsic::x86_avx_vperm2f128_ps_256; //
torType>(Tys[0]))); "86.avx.vperm2f128.ps.256"
break; }
case Intrinsic::arm_neon_vshiftins: // llvm.arm.neon.vshiftins break;
ResultTy = Tys[0]; case 's': // 1 string to match.
ArgTys.push_back(Tys[0]); if (memcmp(NameR.data()+19, "i.256", 5))
ArgTys.push_back(Tys[0]); break;
ArgTys.push_back(Tys[0]); return Intrinsic::x86_avx_vperm2f128_si_256; // "86.avx.
break; vperm2f128.si.256"
case Intrinsic::arm_neon_vqdmlal: // llvm.arm.neon.vqdmlal }
case Intrinsic::arm_neon_vqdmlsl: // llvm.arm.neon.vqdmlsl break;
ResultTy = Tys[0]; case 'i': // 2 strings to match.
ArgTys.push_back(Tys[0]); if (memcmp(NameR.data()+13, "lvar.p", 6))
ArgTys.push_back(VectorType::getTruncatedElementVectorType(dyn_cast<Vec break;
torType>(Tys[0]))); switch (NameR[19]) {
ArgTys.push_back(VectorType::getTruncatedElementVectorType(dyn_cast<Vec default: break;
torType>(Tys[0]))); case 'd': // 1 string to match.
break; if (memcmp(NameR.data()+20, ".256", 4))
case Intrinsic::arm_neon_vpadals: // llvm.arm.neon.vpadals break;
ResultTy = Tys[0]; return Intrinsic::x86_avx_vpermilvar_pd_256; // "86.avx.
ArgTys.push_back(Tys[0]); vpermilvar.pd.256"
ArgTys.push_back(Tys[1]); case 's': // 1 string to match.
break; if (memcmp(NameR.data()+20, ".256", 4))
case Intrinsic::arm_neon_vpadalu: // llvm.arm.neon.vpadalu break;
ResultTy = Tys[0]; return Intrinsic::x86_avx_vpermilvar_ps_256; // "86.avx.
ArgTys.push_back(Tys[0]); vpermilvar.ps.256"
ArgTys.push_back(Tys[1]); }
break; break;
case Intrinsic::arm_neon_vpaddls: // llvm.arm.neon.vpaddls }
case Intrinsic::arm_neon_vpaddlu: // llvm.arm.neon.vpaddlu break;
ResultTy = Tys[0]; }
ArgTys.push_back(Tys[1]); break;
break; case '2': // 1 string to match.
case Intrinsic::arm_neon_vld1: // llvm.arm.neon.vld1 if (memcmp(NameR.data()+7, ".vbroadcast.ss.ps", 17))
ResultTy = Tys[0]; break;
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8))); return Intrinsic::x86_avx2_vbroadcast_ss_ps; // "86.avx2
ArgTys.push_back(IntegerType::get(Context, 32)); .vbroadcast.ss.ps"
break; }
case Intrinsic::arm_neon_vld2: // llvm.arm.neon.vld2 break;
ResultTy = StructType::get(Tys[0], Tys[0], NULL); }
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8))); break;
ArgTys.push_back(IntegerType::get(Context, 32)); case 's': // 1 string to match.
break; if (memcmp(NameR.data()+4, "sse3.pmadd.ub.sw.128", 20))
case Intrinsic::arm_neon_vld3: // llvm.arm.neon.vld3 break;
ResultTy = StructType::get(Tys[0], Tys[0], Tys[0], NULL); return Intrinsic::x86_ssse3_pmadd_ub_sw_128; // "86.ssse3.pmadd.
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8))); ub.sw.128"
ArgTys.push_back(IntegerType::get(Context, 32)); }
break; break;
case Intrinsic::arm_neon_vld4: // llvm.arm.neon.vld4 case 25: // 3 strings to match.
ResultTy = StructType::get(Tys[0], Tys[0], Tys[0], Tys[0], NULL); if (memcmp(NameR.data()+0, "86.avx.vinsertf128.", 19))
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8))); break;
ArgTys.push_back(IntegerType::get(Context, 32)); switch (NameR[19]) {
break; default: break;
case Intrinsic::arm_neon_vld2lane: // llvm.arm.neon.vld2lane case 'p': // 2 strings to match.
ResultTy = StructType::get(Tys[0], Tys[0], NULL); switch (NameR[20]) {
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8))); default: break;
ArgTys.push_back(Tys[0]); case 'd': // 1 string to match.
ArgTys.push_back(Tys[0]); if (memcmp(NameR.data()+21, ".256", 4))
ArgTys.push_back(IntegerType::get(Context, 32)); break;
ArgTys.push_back(IntegerType::get(Context, 32)); return Intrinsic::x86_avx_vinsertf128_pd_256; // "86.avx.
break; vinsertf128.pd.256"
case Intrinsic::arm_neon_vld3lane: // llvm.arm.neon.vld3lane case 's': // 1 string to match.
ResultTy = StructType::get(Tys[0], Tys[0], Tys[0], NULL); if (memcmp(NameR.data()+21, ".256", 4))
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8))); break;
ArgTys.push_back(Tys[0]); return Intrinsic::x86_avx_vinsertf128_ps_256; // "86.avx.
ArgTys.push_back(Tys[0]); vinsertf128.ps.256"
ArgTys.push_back(Tys[0]); }
ArgTys.push_back(IntegerType::get(Context, 32)); break;
ArgTys.push_back(IntegerType::get(Context, 32)); case 's': // 1 string to match.
break; if (memcmp(NameR.data()+20, "i.256", 5))
case Intrinsic::arm_neon_vld4lane: // llvm.arm.neon.vld4lane break;
ResultTy = StructType::get(Tys[0], Tys[0], Tys[0], Tys[0], NULL); return Intrinsic::x86_avx_vinsertf128_si_256; // "86.avx.vinsertf
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8))); 128.si.256"
ArgTys.push_back(Tys[0]); }
ArgTys.push_back(Tys[0]); break;
ArgTys.push_back(Tys[0]); case 26: // 3 strings to match.
ArgTys.push_back(Tys[0]); if (memcmp(NameR.data()+0, "86.avx.vextractf128.", 20))
ArgTys.push_back(IntegerType::get(Context, 32)); break;
ArgTys.push_back(IntegerType::get(Context, 32)); switch (NameR[20]) {
break; default: break;
case Intrinsic::invariant_start: // llvm.invariant.start case 'p': // 2 strings to match.
ResultTy = PointerType::getUnqual(StructType::get(Context)); switch (NameR[21]) {
ArgTys.push_back(IntegerType::get(Context, 64)); default: break;
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8))); case 'd': // 1 string to match.
break; if (memcmp(NameR.data()+22, ".256", 4))
case Intrinsic::arm_vcvtr: // llvm.arm.vcvtr break;
case Intrinsic::arm_vcvtru: // llvm.arm.vcvtru return Intrinsic::x86_avx_vextractf128_pd_256; // "86.avx.
ResultTy = Type::getFloatTy(Context); vextractf128.pd.256"
ArgTys.push_back(Tys[0]); case 's': // 1 string to match.
break; if (memcmp(NameR.data()+22, ".256", 4))
case Intrinsic::convert_from_fp16: // llvm.convert.from.fp16 break;
ResultTy = Type::getFloatTy(Context); return Intrinsic::x86_avx_vextractf128_ps_256; // "86.avx.
ArgTys.push_back(IntegerType::get(Context, 16)); vextractf128.ps.256"
break; }
case Intrinsic::convert_to_fp16: // llvm.convert.to.fp16 break;
ResultTy = IntegerType::get(Context, 16); case 's': // 1 string to match.
ArgTys.push_back(Type::getFloatTy(Context)); if (memcmp(NameR.data()+21, "i.256", 5))
break; break;
case Intrinsic::hexagon_C2_all8: // llvm.hexagon.C2.all8 return Intrinsic::x86_avx_vextractf128_si_256; // "86.avx.vextract
case Intrinsic::hexagon_C2_any8: // llvm.hexagon.C2.any8 f128.si.256"
case Intrinsic::hexagon_C2_not: // llvm.hexagon.C2.not }
case Intrinsic::hexagon_C2_pxfer_map: // llvm.hexagon.C2.p break;
xfer.map case 28: // 4 strings to match.
case Intrinsic::hexagon_C2_tfrrp: // llvm.hexagon.C2.tfrrp if (memcmp(NameR.data()+0, "86.avx", 6))
ResultTy = IntegerType::get(Context, 1); break;
ArgTys.push_back(IntegerType::get(Context, 32)); switch (NameR[6]) {
break; default: break;
case Intrinsic::hexagon_C2_and: // llvm.hexagon.C2.and case '.': // 2 strings to match.
case Intrinsic::hexagon_C2_andn: // llvm.hexagon.C2.andn if (memcmp(NameR.data()+7, "vbroadcastf128.p", 16))
case Intrinsic::hexagon_C2_bitsclr: // llvm.hexagon.C2.bitsclr break;
case Intrinsic::hexagon_C2_bitsclri: // llvm.hexagon.C2.bitsclri switch (NameR[23]) {
case Intrinsic::hexagon_C2_bitsset: // llvm.hexagon.C2.bitsset default: break;
case Intrinsic::hexagon_C2_cmpeq: // llvm.hexagon.C2.cmpeq case 'd': // 1 string to match.
case Intrinsic::hexagon_C2_cmpeqi: // llvm.hexagon.C2.cmpeqi if (memcmp(NameR.data()+24, ".256", 4))
case Intrinsic::hexagon_C2_cmpgei: // llvm.hexagon.C2.cmpgei break;
case Intrinsic::hexagon_C2_cmpgeui: // llvm.hexagon.C2.cmpgeui return Intrinsic::x86_avx_vbroadcastf128_pd_256; // "86.avx.
case Intrinsic::hexagon_C2_cmpgt: // llvm.hexagon.C2.cmpgt vbroadcastf128.pd.256"
case Intrinsic::hexagon_C2_cmpgti: // llvm.hexagon.C2.cmpgti case 's': // 1 string to match.
case Intrinsic::hexagon_C2_cmpgtu: // llvm.hexagon.C2.cmpgtu if (memcmp(NameR.data()+24, ".256", 4))
case Intrinsic::hexagon_C2_cmpgtui: // llvm.hexagon.C2.cmpgtui break;
case Intrinsic::hexagon_C2_cmplt: // llvm.hexagon.C2.cmplt return Intrinsic::x86_avx_vbroadcastf128_ps_256; // "86.avx.
case Intrinsic::hexagon_C2_cmpltu: // llvm.hexagon.C2.cmpltu vbroadcastf128.ps.256"
case Intrinsic::hexagon_C2_or: // llvm.hexagon.C2.or }
case Intrinsic::hexagon_C2_orn: // llvm.hexagon.C2.orn break;
case Intrinsic::hexagon_C2_xor: // llvm.hexagon.C2.xor case '2': // 2 strings to match.
case Intrinsic::hexagon_C4_cmplte: // llvm.hexagon.C4.cmplte if (memcmp(NameR.data()+7, ".vbroadcast.s", 13))
case Intrinsic::hexagon_C4_cmpltei: // llvm.hexagon.C4.cmpltei break;
case Intrinsic::hexagon_C4_cmplteu: // llvm.hexagon.C4.cmplteu switch (NameR[20]) {
case Intrinsic::hexagon_C4_cmplteui: // llvm.hexagon.C4.cmplteui default: break;
case Intrinsic::hexagon_C4_cmpneq: // llvm.hexagon.C4.cmpneq case 'd': // 1 string to match.
case Intrinsic::hexagon_C4_cmpneqi: // llvm.hexagon.C4.cmpneqi if (memcmp(NameR.data()+21, ".pd.256", 7))
case Intrinsic::hexagon_C4_fastcorner9: // llvm.hexagon.C4.f break;
astcorner9 return Intrinsic::x86_avx2_vbroadcast_sd_pd_256; // "86.avx2
case Intrinsic::hexagon_C4_fastcorner9_not: // llvm.hexagon.C4.f .vbroadcast.sd.pd.256"
astcorner9.not case 's': // 1 string to match.
case Intrinsic::hexagon_S2_tstbit_i: // llvm.hexagon.S2.tstbit.i if (memcmp(NameR.data()+21, ".ps.256", 7))
case Intrinsic::hexagon_S2_tstbit_r: // llvm.hexagon.S2.tstbit.r break;
ResultTy = IntegerType::get(Context, 1); return Intrinsic::x86_avx2_vbroadcast_ss_ps_256; // "86.avx2
ArgTys.push_back(IntegerType::get(Context, 32)); .vbroadcast.ss.ps.256"
ArgTys.push_back(IntegerType::get(Context, 32)); }
break; break;
case Intrinsic::hexagon_C4_and_and: // llvm.hexagon.C4.and.and }
case Intrinsic::hexagon_C4_and_andn: // llvm.hexagon.C4.and.andn break;
case Intrinsic::hexagon_C4_and_or: // llvm.hexagon.C4.and.or }
case Intrinsic::hexagon_C4_and_orn: // llvm.hexagon.C4.and.orn break; // end of 'x' case.
case Intrinsic::hexagon_C4_or_and: // llvm.hexagon.C4.or.and }
case Intrinsic::hexagon_C4_or_andn: // llvm.hexagon.C4.or.andn #endif
case Intrinsic::hexagon_C4_or_or: // llvm.hexagon.C4.or.or
case Intrinsic::hexagon_C4_or_orn: // llvm.hexagon.C4.or.orn // Global intrinsic function declaration type table.
ResultTy = IntegerType::get(Context, 1); #ifdef GET_INTRINSIC_GENERATOR_GLOBAL
ArgTys.push_back(IntegerType::get(Context, 32)); static const unsigned IIT_Table[] = {
ArgTys.push_back(IntegerType::get(Context, 32)); 0x2E2E, (1U<<31) | 310, 0x4444440, 0x4444440, 0x4, (1U<<31) | 276, 0x4444
ArgTys.push_back(IntegerType::get(Context, 32)); 440,
break; 0x4444440, 0x444440, 0x444440, 0x444444, 0x444444, 0x2F2F2F, 0x2F2F2F, 0x
case Intrinsic::hexagon_A2_vcmpbeq: // llvm.hexagon.A2.vcmpbeq 2F2F,
case Intrinsic::hexagon_A2_vcmpbgtu: // llvm.hexagon.A2.vcmpbgtu 0x686848, 0x696949, 0x686848, 0x696949, (1U<<31) | 294, 0x2F2F2F2F, 0x2F2
case Intrinsic::hexagon_A2_vcmpheq: // llvm.hexagon.A2.vcmpheq F, 0x2F2F,
case Intrinsic::hexagon_A2_vcmphgt: // llvm.hexagon.A2.vcmphgt 0x2F2F, 0x45F0F, 0x45F0F, 0x6939, 0x44F1F, 0x44F1F, 0x3969, 0x2F2F2F,
case Intrinsic::hexagon_A2_vcmphgtu: // llvm.hexagon.A2.vcmphgtu 0x2F2F2F, 0x2F2F2F, 0x2F2F2F, 0x42E2F, (1U<<31) | 354, (1U<<31) | 401, (1
case Intrinsic::hexagon_A2_vcmpweq: // llvm.hexagon.A2.vcmpweq U<<31) | 343, (1U<<31) | 427,
case Intrinsic::hexagon_A2_vcmpwgt: // llvm.hexagon.A2.vcmpwgt (1U<<31) | 330, (1U<<31) | 459, 0x2F2F2F, 0x2F2F2F, 0x2F2F2F, 0x2F2F2F, (
case Intrinsic::hexagon_A2_vcmpwgtu: // llvm.hexagon.A2.vcmpwgtu 1U<<31) | 303, (1U<<31) | 303,
case Intrinsic::hexagon_C2_cmpeqp: // llvm.hexagon.C2.cmpeqp (1U<<31) | 303, 0x2F2F2F, 0x6F2F2F, 0x6F2F2F, 0x2F2F2F, 0x6F2F, 0x6F2F, 0
case Intrinsic::hexagon_C2_cmpgtp: // llvm.hexagon.C2.cmpgtp x2F2F2F,
case Intrinsic::hexagon_C2_cmpgtup: // llvm.hexagon.C2.cmpgtup 0x2F2F2F, 0x2F2F2F, 0x2F2F2F, 0x2F2F, 0x2F2F2F, 0x2F2F2F, (1U<<31) | 301,
ResultTy = IntegerType::get(Context, 1); (1U<<31) | 301,
ArgTys.push_back(IntegerType::get(Context, 64)); 0x2F2F2F, (1U<<31) | 303, (1U<<31) | 289, (1U<<31) | 289, (1U<<31) | 289,
ArgTys.push_back(IntegerType::get(Context, 64)); 0x2F2F, 0x2F2F2F, (1U<<31) | 294,
break; (1U<<31) | 294, (1U<<31) | 294, 0x2F2F2F, 0x2F2F2F, (1U<<31) | 294, (1U<<
case Intrinsic::arm_get_fpscr: // llvm.arm.get.fpscr 31) | 294, (1U<<31) | 294, 0x2F2F2F,
case Intrinsic::flt_rounds: // llvm.flt.rounds 0x2F2F2F, 0x2F2F2F, 0x2F2F2F, 0x2F2F2F, (1U<<31) | 294, 0x2F2F, 0x2F2F2F,
case Intrinsic::ptx_read_clock: // llvm.ptx.read.clock 0x2F2F2F,
case Intrinsic::ptx_read_ctaid_w: // llvm.ptx.read.ctaid.w 0x2F2F2F, (1U<<31) | 294, 0x2F2F2F, 0x2F2F2F, 0x2F2F, 0x2F2F2F, (1U<<31)
case Intrinsic::ptx_read_ctaid_x: // llvm.ptx.read.ctaid.x | 294, 0x2F2F2F2F,
case Intrinsic::ptx_read_ctaid_y: // llvm.ptx.read.ctaid.y (1U<<31) | 303, (1U<<31) | 303, (1U<<31) | 294, 0x2F2F2F, 0x2F2F2F, 0x42F
case Intrinsic::ptx_read_ctaid_z: // llvm.ptx.read.ctaid.z 2E0, 0x42F2F2E0, (1U<<31) | 391,
case Intrinsic::ptx_read_gridid: // llvm.ptx.read.gridid (1U<<31) | 363, (1U<<31) | 415, (1U<<31) | 374, (1U<<31) | 445, (1U<<31)
case Intrinsic::ptx_read_laneid: // llvm.ptx.read.laneid | 294, 0x2A2A2A, 0x2A2A2A2A, (1U<<31) | 265,
case Intrinsic::ptx_read_lanemask_eq: // llvm.ptx.read.lan (1U<<31) | 263, 0x2A2A2A2A, (1U<<31) | 265, (1U<<31) | 263, (1U<<31) | 26
emask.eq 1, 0x444, 0x444, 0x40,
case Intrinsic::ptx_read_lanemask_ge: // llvm.ptx.read.lan 0x444, 0x2E444, 0x2E, 0x444, 0x1F6, 0x1F6, 0xF0F, 0x36,
emask.ge 0x63, 0x445F1F, 0x444F1F, 0x444F1F, 0x445F0F, 0x444F0F, 0x444F0F, 0x445F0
case Intrinsic::ptx_read_lanemask_gt: // llvm.ptx.read.lan F,
emask.gt 0x444F0F, 0x444F0F, 0x1F1F, 0x10F0F, 0xF0F, 0x10F0F, 0x0, (1U<<31) | 501,
case Intrinsic::ptx_read_lanemask_le: // llvm.ptx.read.lan (1U<<31) | 496, 0x0, 0x0, 0x42E, 0x2E40, 0x2E50, 0x40, 0x2E0,
emask.le 0x2E0, 0x2E, 0x2E4, 0x2E4, 0x0, 0x1F1F, 0x1F1F, 0xF0F0F,
case Intrinsic::ptx_read_lanemask_lt: // llvm.ptx.read.lan 0x1F1F, 0x1F1F, 0x4, 0x1F1F1F1F, 0x1F1F1F1F, 0x42E, 0x2EE2E2E, 0x2E2EE0,
emask.lt 0x2EE2E2E0, 0x44, 0x55, 0x44, 0x444, 0x444, 0x444, 0x444,
case Intrinsic::ptx_read_nctaid_w: // llvm.ptx.read.nctaid.w 0x444, 0x444, 0x444, 0x444, 0x444, 0x444, 0x444, 0x444,
case Intrinsic::ptx_read_nctaid_x: // llvm.ptx.read.nctaid.x 0x444, 0x444, 0x555, 0x555, 0x444, 0x545, 0x444, 0x444,
case Intrinsic::ptx_read_nctaid_y: // llvm.ptx.read.nctaid.y 0x555, 0x44, 0x44, 0x444, 0x444, 0x444, 0x444, 0x445,
case Intrinsic::ptx_read_nctaid_z: // llvm.ptx.read.nctaid.z 0x445, 0x444, 0x555, 0x444, 0x555, 0x444, 0x555, 0x444,
case Intrinsic::ptx_read_nsmid: // llvm.ptx.read.nsmid 0x555, 0x44, 0x55, 0x44, 0x44, 0x55, 0x444, 0x444,
case Intrinsic::ptx_read_ntid_w: // llvm.ptx.read.ntid.w 0x555, 0x54, 0x54, 0x44, 0x44, 0x44, 0x44, 0x444,
case Intrinsic::ptx_read_ntid_x: // llvm.ptx.read.ntid.x 0x444, 0x444, 0x444, 0x444, 0x444, 0x444, 0x444, 0x444,
case Intrinsic::ptx_read_ntid_y: // llvm.ptx.read.ntid.y 0x444, 0x444, 0x444, 0x444, 0x555, 0x444, 0x444, 0x444,
case Intrinsic::ptx_read_ntid_z: // llvm.ptx.read.ntid.z 0x444, 0x444, 0x444, 0x444, 0x444, 0x444, 0x444, 0x444,
case Intrinsic::ptx_read_nwarpid: // llvm.ptx.read.nwarpid 0x44, 0x44, 0x44, 0x45, 0x44, 0x444, 0x444, 0x55,
case Intrinsic::ptx_read_pm0: // llvm.ptx.read.pm0 0x45, 0x44, 0x55, 0x55, 0x55, 0x55, 0x555, 0x555,
case Intrinsic::ptx_read_pm1: // llvm.ptx.read.pm1 0x555, 0x555, 0x555, 0x555, 0x555, 0x555, 0x555, 0x555,
case Intrinsic::ptx_read_pm2: // llvm.ptx.read.pm2 0x555, 0x555, 0x555, 0x555, 0x555, 0x555, 0x555, 0x555,
case Intrinsic::ptx_read_pm3: // llvm.ptx.read.pm3 0x555, 0x555, 0x551, 0x551, 0x551, 0x551, 0x551, 0x551,
case Intrinsic::ptx_read_smid: // llvm.ptx.read.smid 0x551, 0x551, 0x55, 0x555, 0x555, 0x555, 0x555, 0x555,
case Intrinsic::ptx_read_tid_w: // llvm.ptx.read.tid.w 0x555, 0x555, 0x555, 0x555, 0x555, 0x555, 0x555, 0x555,
case Intrinsic::ptx_read_tid_x: // llvm.ptx.read.tid.x 0x555, 0x555, 0x555, 0x555, 0x555, 0x555, 0x5555, 0x555,
case Intrinsic::ptx_read_tid_y: // llvm.ptx.read.tid.y 0x5555, 0x555, 0x555, 0x555, 0x555, 0x555, 0x555, 0x555,
case Intrinsic::ptx_read_tid_z: // llvm.ptx.read.tid.z 0x555, 0x444, 0x555, 0x44, 0x44, 0x444, 0x555, 0x445,
case Intrinsic::ptx_read_warpid: // llvm.ptx.read.warpid 0x445, 0x541, 0x441, 0x441, 0x441, 0x441, 0x441, 0x441,
case Intrinsic::x86_rdfsbase_32: // llvm.x86.rdfsbase.32 0x441, 0x441, 0x441, 0x441, 0x441, 0x441, 0x445, 0x445,
case Intrinsic::x86_rdgsbase_32: // llvm.x86.rdgsbase.32 0x444, 0x444, 0x444, 0x444, 0x555, 0x444, 0x444, 0x444,
case Intrinsic::xcore_geted: // llvm.xcore.geted 0x444, 0x444, 0x444, 0x444, 0x444, 0x451, 0x551, 0x451,
case Intrinsic::xcore_getet: // llvm.xcore.getet 0x551, 0x451, 0x451, 0x451, 0x451, 0x451, 0x451, 0x451,
case Intrinsic::xcore_getid: // llvm.xcore.getid 0x451, 0x4555, 0x4555, 0x4555, 0x4555, 0x4555, 0x4555, 0x4555,
ResultTy = IntegerType::get(Context, 32); 0x4555, 0x554, 0x41, 0x441, 0x441, 0x41, 0x441, 0x441,
break; 0x441, 0x441, 0x441, 0x551, 0x441, 0x441, 0x441, 0x441,
case Intrinsic::xcore_endin: // llvm.xcore.endin 0x551, 0x441, 0x441, 0x551, 0x441, 0x441, 0x45, 0x4444,
case Intrinsic::xcore_getts: // llvm.xcore.getts 0x4444, 0x4444, 0x4444, 0x41, 0x441, 0x441, 0x41, 0x44,
case Intrinsic::xcore_in: // llvm.xcore.in 0x41, 0x444, 0x5545, 0x441, 0x4441, 0x4441, 0x4441, 0x4441,
case Intrinsic::xcore_inct: // llvm.xcore.inct 0x441, 0x441, 0x441, 0x441, 0x441, 0x441, 0x441, 0x441,
case Intrinsic::xcore_int: // llvm.xcore.int 0x441, 0x441, 0x441, 0x4441, 0x4441, 0x4441, 0x4441, 0x57,
case Intrinsic::xcore_peek: // llvm.xcore.peek 0x56, 0x75, 0x75, 0x76, 0x75, 0x75, 0x74, 0x74,
case Intrinsic::xcore_testct: // llvm.xcore.testct 0x74, 0x74, 0x65, 0x65, 0x67, 0x65, 0x65, 0x64,
case Intrinsic::xcore_testwct: // llvm.xcore.testwct 0x64, 0x64, 0x64, 0x57, 0x56, 0x47, 0x46, 0x47,
ResultTy = IntegerType::get(Context, 32); 0x46, 0x777, 0x471, 0x771, 0x771, 0x771, 0x771, 0x777,
ArgTys.push_back((0 < Tys.size()) ? Tys[0] : PointerType::getUnqual(Int 0x777, 0x77, 0x7777, 0x7777, 0x47777, 0x7777, 0x7777, 0x47,
egerType::get(Context, 8))); 0x47, 0x777, 0x777, 0x777, 0x777, 0x666, 0x461, 0x661,
break; 0x661, 0x661, 0x661, 0x666, 0x666, 0x66, 0x6666, 0x6666,
case Intrinsic::xcore_inshr: // llvm.xcore.inshr 0x46666, 0x6666, 0x6666, 0x46, 0x46, 0x666, 0x666, 0x666,
case Intrinsic::xcore_outshr: // llvm.xcore.outshr 0x666, 0x4444, 0x4444, 0x4455, 0x4455, 0x4455, 0x4455, 0x4455,
ResultTy = IntegerType::get(Context, 32); 0x4455, 0x445, 0x445, 0x444, 0x444, 0x444, 0x444, 0x445,
ArgTys.push_back((0 < Tys.size()) ? Tys[0] : PointerType::getUnqual(Int 0x445, 0x445, 0x445, 0x4455, 0x4455, 0x4455, 0x4455, 0x4455,
egerType::get(Context, 8))); 0x4455, 0x444, 0x445, 0x4455, 0x4455, 0x445, 0x444, 0x444,
ArgTys.push_back(IntegerType::get(Context, 32)); 0x444, 0x444, 0x4444, 0x4444, 0x4444, 0x5555, 0x5555, 0x5555,
break; 0x5555, 0x5555, 0x5555, 0x5555, 0x5555, 0x5555, 0x5555, 0x5555,
case Intrinsic::hexagon_A2_abs: // llvm.hexagon.A2.abs 0x5555, 0x5555, 0x5555, 0x5555, 0x5555, 0x555, 0x555, 0x555,
case Intrinsic::hexagon_A2_abssat: // llvm.hexagon.A2.abssat 0x555, 0x555, 0x555, 0x555, 0x555, 0x555, 0x555, 0x555,
case Intrinsic::hexagon_A2_aslh: // llvm.hexagon.A2.aslh 0x555, 0x555, 0x555, 0x555, 0x555, 0x4444, 0x4444, 0x4444,
case Intrinsic::hexagon_A2_asrh: // llvm.hexagon.A2.asrh 0x4444, 0x4444, 0x4444, 0x4444, 0x4444, 0x4444, 0x4444, 0x4444,
case Intrinsic::hexagon_A2_neg: // llvm.hexagon.A2.neg 0x4444, 0x4444, 0x4444, 0x4444, 0x4444, 0x444, 0x444, 0x444,
case Intrinsic::hexagon_A2_negsat: // llvm.hexagon.A2.negsat 0x444, 0x444, 0x444, 0x444, 0x444, 0x4444, 0x4444, 0x4444,
case Intrinsic::hexagon_A2_not: // llvm.hexagon.A2.not 0x4444, 0x4444, 0x4444, 0x4444, 0x4444, 0x4444, 0x4444, 0x4444,
case Intrinsic::hexagon_A2_satb: // llvm.hexagon.A2.satb 0x4444, 0x4444, 0x4444, 0x4444, 0x4444, 0x444, 0x444, 0x444,
case Intrinsic::hexagon_A2_sath: // llvm.hexagon.A2.sath 0x444, 0x444, 0x444, 0x444, 0x444, 0x444, 0x444, 0x444,
case Intrinsic::hexagon_A2_satub: // llvm.hexagon.A2.satub 0x444, 0x444, 0x444, 0x444, 0x444, 0x444, 0x444, 0x444,
case Intrinsic::hexagon_A2_satuh: // llvm.hexagon.A2.satuh 0x444, 0x444, 0x444, 0x444, 0x444, 0x444, 0x444, 0x444,
case Intrinsic::hexagon_A2_swiz: // llvm.hexagon.A2.swiz 0x4455, 0x4455, 0x4455, 0x4455, 0x4455, 0x4455, 0x4455, 0x4455,
case Intrinsic::hexagon_A2_sxtb: // llvm.hexagon.A2.sxtb 0x445, 0x445, 0x445, 0x445, 0x445, 0x445, 0x445, 0x445,
case Intrinsic::hexagon_A2_sxth: // llvm.hexagon.A2.sxth 0x4455, 0x4455, 0x4455, 0x4455, 0x4455, 0x4455, 0x4455, 0x4455,
case Intrinsic::hexagon_A2_tfr: // llvm.hexagon.A2.tfr 0x445, 0x445, 0x445, 0x445, 0x445, 0x445, 0x445, 0x445,
case Intrinsic::hexagon_A2_tfrsi: // llvm.hexagon.A2.tfrsi 0x444, 0x444, 0x444, 0x4444, 0x4444, 0x4444, 0x4444, 0x4444,
case Intrinsic::hexagon_A2_zxtb: // llvm.hexagon.A2.zxtb 0x4444, 0x4444, 0x4444, 0x444, 0x444, 0x444, 0x444, 0x444,
case Intrinsic::hexagon_A2_zxth: // llvm.hexagon.A2.zxth 0x444, 0x444, 0x444, 0x4444, 0x4444, 0x4444, 0x4444, 0x4444,
case Intrinsic::hexagon_C2_tfrpr: // llvm.hexagon.C2.tfrpr 0x4444, 0x4444, 0x4444, 0x444, 0x4455, 0x4455, 0x4455, 0x4455,
case Intrinsic::hexagon_S2_brev: // llvm.hexagon.S2.brev 0x4455, 0x4455, 0x4455, 0x4455, 0x445, 0x445, 0x445, 0x445,
case Intrinsic::hexagon_S2_cl0: // llvm.hexagon.S2.cl0 0x445, 0x445, 0x445, 0x445, 0x4455, 0x4455, 0x4455, 0x4455,
case Intrinsic::hexagon_S2_cl1: // llvm.hexagon.S2.cl1 0x4455, 0x4455, 0x4455, 0x4455, 0x444, 0x4444, 0x4444, 0x4444,
case Intrinsic::hexagon_S2_clb: // llvm.hexagon.S2.clb 0x555, 0x555, 0x5555, 0x5555, 0x555, 0x555, 0x555, 0x555,
case Intrinsic::hexagon_S2_clbnorm: // llvm.hexagon.S2.clbnorm 0x5555, 0x5555, 0x554, 0x554, 0x555, 0x555, 0x4455, 0x5555,
case Intrinsic::hexagon_S2_ct0: // llvm.hexagon.S2.ct0 0x5555, 0x5555, 0x4455, 0x4455, 0x4455, 0x4455, 0x555, 0x555,
case Intrinsic::hexagon_S2_ct1: // llvm.hexagon.S2.ct1 0x445, 0x444, 0x445, 0x444, 0x445, 0x445, 0x554, 0x554,
case Intrinsic::hexagon_S2_svsathb: // llvm.hexagon.S2.svsathb 0x5555, 0x5555, 0x5555, 0x5555, 0x555, 0x555, 0x555, 0x555,
case Intrinsic::hexagon_S2_svsathub: // llvm.hexagon.S2.svsathub 0x4555, 0x455, 0x454, 0x5555, 0x555, 0x4444, 0x4444, 0x4444,
case Intrinsic::hexagon_S2_vsplatrb: // llvm.hexagon.S2.vsplatrb 0x4444, 0x4444, 0x454, 0x454, 0x454, 0x454, 0x4444, 0x4444,
case Intrinsic::hexagon_SI_to_SXTHI_asrh: // llvm.hexagon.SI.t 0x4444, 0x4444, 0x4444, 0x4444, 0x4444, 0x4444, 0x4444, 0x4444,
o.SXTHI.asrh 0x4444, 0x445, 0x4455, 0x445, 0x4455, 0x5555, 0x5555, 0x555,
case Intrinsic::xcore_bitrev: // llvm.xcore.bitrev 0x555, 0x5555, 0x5555, 0x555, 0x555, 0x4444, 0x4444, 0x4444,
case Intrinsic::xcore_getps: // llvm.xcore.getps 0x5555, 0x5555, 0x555, 0x4455, 0x4455, 0x445, 0x445, 0x5555,
ResultTy = IntegerType::get(Context, 32); 0x5555, 0x555, 0x555, 0x4444, 0x455, 0x4555, 0x4555, 0x4555,
ArgTys.push_back(IntegerType::get(Context, 32)); 0x4555, 0x4555, 0x444, 0x4444, 0x4444, 0x4444, 0x4444, 0x444,
break; 0x4444, 0x455, 0x455, 0x455, 0x4555, 0x4555, 0x4555, 0x4555,
case Intrinsic::x86_sse42_crc32_32_16: // llvm.x86.sse42.cr 0x4555, 0x444, 0x4444, 0x4444, 0x4444, 0x4444, 0x444, 0x455,
c32.32.16 0x455, 0x455, 0x4555, 0x4555, 0x4555, 0x4555, 0x455, 0x455,
ResultTy = IntegerType::get(Context, 32); 0x444, 0x4444, 0x4444, 0x4444, 0x4444, 0x444, 0x444, 0x454,
ArgTys.push_back(IntegerType::get(Context, 32)); 0x455, 0x455, 0x455, 0x4555, 0x4555, 0x4555, 0x4555, 0x4555,
ArgTys.push_back(IntegerType::get(Context, 16)); 0x444, 0x4444, 0x4444, 0x4444, 0x4444, 0x444, 0x454, 0x455,
break; 0x455, 0x44, 0x55, 0x44, 0x54, 0x44, 0x54, 0x44,
case Intrinsic::arm_qadd: // llvm.arm.qadd 0x44, 0x54, 0x444, 0x444, 0x44, 0x54, 0x44, 0x54,
case Intrinsic::arm_qsub: // llvm.arm.qsub 0x55, 0x4444, 0x544, 0x4455, 0x555, 0x44444, 0x5444, 0x44555,
case Intrinsic::arm_ssat: // llvm.arm.ssat 0x5555, 0x55, 0x555, 0x455, 0x4555, 0x4555, 0x4555, 0x4555,
case Intrinsic::arm_usat: // llvm.arm.usat 0x4555, 0x444, 0x4444, 0x4444, 0x4444, 0x4444, 0x455, 0x455,
case Intrinsic::hexagon_A2_add: // llvm.hexagon.A2.add 0x455, 0x4555, 0x4555, 0x4555, 0x4555, 0x4555, 0x444, 0x4444,
case Intrinsic::hexagon_A2_addh_h16_hh: // llvm.hexagon.A2.a 0x4444, 0x4444, 0x4444, 0x4444, 0x455, 0x455, 0x455, 0x4555,
ddh.h16.hh 0x4555, 0x4555, 0x4555, 0x4555, 0x444, 0x4444, 0x4444, 0x4444,
case Intrinsic::hexagon_A2_addh_h16_hl: // llvm.hexagon.A2.a 0x4444, 0x455, 0x455, 0x445, 0x554, 0x444, 0x444, 0x555,
ddh.h16.hl 0x555, 0x555, 0x555, 0x44, 0x44, 0x44444, 0x44444, 0x44444,
case Intrinsic::hexagon_A2_addh_h16_lh: // llvm.hexagon.A2.a 0x44444, 0x444, 0x444, 0x441, 0x441, 0x4555, 0x4555, 0x455,
ddh.h16.lh 0x455, 0x4555, 0x54, 0x54, 0x54, 0x55, 0x54, 0x55,
case Intrinsic::hexagon_A2_addh_h16_ll: // llvm.hexagon.A2.a 0x54, 0x55, 0x54, 0x55, 0x44, 0x45, 0x4555, 0x4555,
ddh.h16.ll 0x45, 0x45, 0x54, 0x555, 0x54, 0x555, 0x45, 0x45,
case Intrinsic::hexagon_A2_addh_h16_sat_hh: // llvm.hexagon.A2.a 0x4444, 0x4444, 0x4444, 0x4444, 0x4444, 0x444, 0x454, 0x54,
ddh.h16.sat.hh 0x4444, 0x544, 0x4455, 0x555, 0x444, 0x441, 0x441, 0x4444,
case Intrinsic::hexagon_A2_addh_h16_sat_hl: // llvm.hexagon.A2.a 0x4444, 0x4444, 0x4444, 0x4444, 0x444, 0x4444, 0x4444, 0x4444,
ddh.h16.sat.hl 0x4455, 0x44555, 0x555, 0x555, 0x555, 0x555, 0x555, 0x555,
case Intrinsic::hexagon_A2_addh_h16_sat_lh: // llvm.hexagon.A2.a 0x454, 0x454, 0x54, 0x455, 0x44, 0x442E2E2E, 0x2E2E2E0, (1U<<31) | 282,
ddh.h16.sat.lh (1U<<31) | 283, 0x2E50, 0x2E50, 0x1F1F, 0x1F1F, 0x1F1F, 0x42E0, (1U<<31)
case Intrinsic::hexagon_A2_addh_h16_sat_ll: // llvm.hexagon.A2.a | 9,
ddh.h16.sat.ll (1U<<31) | 9, 0x144F23F0, 0x3838, 0x2929, 0x44, 0x383838, 0x383838, 0x444
case Intrinsic::hexagon_A2_addh_l16_hh: // llvm.hexagon.A2.a ,
ddh.l16.hh 0x383838, 0x383838, 0x444, 0x444, 0x444, 0x383838, 0x292929, 0x383838,
case Intrinsic::hexagon_A2_addh_l16_hl: // llvm.hexagon.A2.a 0x292929, 0x292929, 0x292929, 0x444, 0x4444, 0x4444, 0x44, 0x4,
ddh.l16.hl 0x38380, 0x38380, 0x38380, 0x29294, 0x29294, 0x29294, 0x29294, 0x29294,
case Intrinsic::hexagon_A2_addh_l16_lh: // llvm.hexagon.A2.a 0x29294, 0x29290, 0x29290, 0x29290, 0x383855, 0x383855, 0x4455, 0x383855,
ddh.l16.lh 0x383855, 0x292955, 0x292955, 0x383855, 0x383855, 0x383855, 0x4455, 0x383
case Intrinsic::hexagon_A2_addh_l16_ll: // llvm.hexagon.A2.a 855,
ddh.l16.ll 0x383855, 0x292955, 0x292955, 0x383855, 0x454, 0x454, 0x454, 0x454,
case Intrinsic::hexagon_A2_addh_l16_sat_hh: // llvm.hexagon.A2.a 0x454, 0x454, 0x444, 0x42E4, 0x42E4, 0x42E4, 0x4455, 0x4455,
ddh.l16.sat.hh 0x383855, 0x383855, 0x383855, 0x383855, 0x444, 0x4455, 0x4455, 0x455,
case Intrinsic::hexagon_A2_addh_l16_sat_hl: // llvm.hexagon.A2.a 0x383838, 0x383838, 0x38384, 0x38384, 0x382938, 0x382938, 0x383838, 0x444
ddh.l16.sat.hl ,
case Intrinsic::hexagon_A2_addh_l16_sat_lh: // llvm.hexagon.A2.a 0x383838, 0x444, 0x383855, 0x383855, 0x445, 0x445, 0x383838, 0x383838,
ddh.l16.sat.lh 0x292929, 0x384, 0x384, 0x2938, 0x2938, 0x2938, 0x2938, 0x2938,
case Intrinsic::hexagon_A2_addh_l16_sat_ll: // llvm.hexagon.A2.a 0x2938, 0x2938, 0x2938, 0x383829, 0x44438, 0x44438, 0x4438, 0x383829,
ddh.l16.sat.ll 0x4438, 0x383829, 0x4444, 0x294, 0x44, 0x438, 0x429, 0x455,
case Intrinsic::hexagon_A2_addi: // llvm.hexagon.A2.addi 0x43838, 0x42929, 0x43838, 0x444, 0x43838, 0x42929, 0x43838, 0x42929,
case Intrinsic::hexagon_A2_addsat: // llvm.hexagon.A2.addsat 0x444, 0x43838, 0x42929, 0x383838, 0x383838, 0x444, 0x383838, 0x383838,
case Intrinsic::hexagon_A2_and: // llvm.hexagon.A2.and 0x444, 0x444, 0x383838, 0x292929, 0x383838, 0x292929, 0x292929, 0x292929,
case Intrinsic::hexagon_A2_andir: // llvm.hexagon.A2.andir 0x440, 0x44, 0x55, 0x777, 0x666, 0x666, 0x777, 0x666,
case Intrinsic::hexagon_A2_combine_hh: // llvm.hexagon.A2.c 0x666, 0x777, 0x666, 0x666, 0x777, 0x666, 0x666, 0x63F6,
ombine.hh 0x43F4, 0x43F4, 0x0, 0x44, 0x44, 0x44, 0x75, 0x64,
case Intrinsic::hexagon_A2_combine_hl: // llvm.hexagon.A2.c 0x46, 0x57, 0x44, 0x55, 0x77, 0x66, 0x66, 0x44,
ombine.hl 0x54, 0x3F0, 0x3F0, 0x66, 0x66, 0x76, 0x76, 0x76,
case Intrinsic::hexagon_A2_combine_lh: // llvm.hexagon.A2.c 0x76, 0x76, 0x76, 0x76, 0x76, 0x74, 0x74, 0x74,
ombine.lh 0x74, 0x74, 0x74, 0x75, 0x75, 0x75, 0x75, 0x74,
case Intrinsic::hexagon_A2_combine_ll: // llvm.hexagon.A2.c 0x74, 0x74, 0x74, 0x75, 0x75, 0x75, 0x75, 0x666,
ombine.ll 0x666, 0x777, 0x666, 0x666, 0x777, 0x666, 0x666, 0x777,
case Intrinsic::hexagon_A2_max: // llvm.hexagon.A2.max 0x666, 0x666, 0x777, 0x666, 0x666, 0x77, 0x66, 0x66,
case Intrinsic::hexagon_A2_maxu: // llvm.hexagon.A2.maxu 0x63, 0x63, 0x64, 0x64, 0x64, 0x64, 0x64, 0x64,
case Intrinsic::hexagon_A2_min: // llvm.hexagon.A2.min 0x64, 0x64, 0x65, 0x65, 0x65, 0x65, 0x65, 0x65,
case Intrinsic::hexagon_A2_minu: // llvm.hexagon.A2.minu 0x65, 0x65, 0x64, 0x64, 0x64, 0x64, 0x64, 0x64,
case Intrinsic::hexagon_A2_or: // llvm.hexagon.A2.or 0x64, 0x64, 0x65, 0x65, 0x65, 0x65, 0x65, 0x65,
case Intrinsic::hexagon_A2_orir: // llvm.hexagon.A2.orir 0x65, 0x65, 0x77, 0x66, 0x66, 0x77, 0x66, 0x66,
case Intrinsic::hexagon_A2_sub: // llvm.hexagon.A2.sub 0x7777, 0x6666, 0x6666, 0x7777, 0x6666, 0x6666, 0x7777, 0x6666,
case Intrinsic::hexagon_A2_subh_h16_hh: // llvm.hexagon.A2.s 0x6666, 0x7777, 0x6666, 0x6666, 0x777, 0x666, 0x666, 0x777,
ubh.h16.hh 0x666, 0x666, 0x36, 0x47, 0x47, 0x47, 0x47, 0x46,
case Intrinsic::hexagon_A2_subh_h16_hl: // llvm.hexagon.A2.s 0x46, 0x46, 0x46, 0x1FE1F, 0xFE0F, 0x3FE3F, 0x77, 0x66,
ubh.h16.hl 0x66, 0x57, 0x57, 0x57, 0x57, 0x56, 0x56, 0x56,
case Intrinsic::hexagon_A2_subh_h16_lh: // llvm.hexagon.A2.s 0x56, 0x447, 0x444, 0x555, 0x444, 0x555, 0x0, 0x0,
ubh.h16.lh 0x0, 0x444, 0x555, 0x444, 0x555, 0x77, 0x66, 0x33,
case Intrinsic::hexagon_A2_subh_h16_ll: // llvm.hexagon.A2.s 0x44, 0x55, 0x22, 0x7F3F, 0x444, 0x444, 0x777, 0x666,
ubh.h16.ll 0x666, 0x777, 0x666, 0x666, 0x777, 0x666, 0x666, 0x777,
case Intrinsic::hexagon_A2_subh_h16_sat_hh: // llvm.hexagon.A2.s 0x666, 0x666, 0x444, 0x555, 0x444, 0x555, 0x44, 0x54,
ubh.h16.sat.hh 0x4444, 0x7F3F, 0x7F3F, 0x7F3F, 0x7F3F, 0x7F3F, 0x7F3F, 0x7F3F,
case Intrinsic::hexagon_A2_subh_h16_sat_hl: // llvm.hexagon.A2.s 0x7F3F, 0x7F3F, 0x77, 0x77, 0x66, 0x66, 0x77, 0x66,
ubh.h16.sat.hl 0x66, 0x77, 0x66, 0x66, 0x77, 0x66, 0x66, 0x4,
case Intrinsic::hexagon_A2_subh_h16_sat_lh: // llvm.hexagon.A2.s 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4,
ubh.h16.sat.lh 0x4, 0x4, 0x4, 0x4, 0x77, 0x66, 0x66, 0x77,
case Intrinsic::hexagon_A2_subh_h16_sat_ll: // llvm.hexagon.A2.s 0x66, 0x66, 0x4444, 0x4444, 0x77, 0x66, 0x66, 0x66,
ubh.h16.sat.ll 0x66, 0x66, 0x66, 0x77, 0x66, 0x66, 0x77, 0x66,
case Intrinsic::hexagon_A2_subh_l16_hl: // llvm.hexagon.A2.s 0x66, 0x77, 0x66, 0x66, 0x77, 0x66, 0x66, 0x77,
ubh.l16.hl 0x66, 0x66, 0x47, 0x47, 0x47, 0x47, 0x46, 0x46,
case Intrinsic::hexagon_A2_subh_l16_ll: // llvm.hexagon.A2.s 0x46, 0x46, 0x57, 0x57, 0x57, 0x57, 0x56, 0x56,
ubh.l16.ll 0x56, 0x56, 0x12E0F, 0x40, 0x1F1F1F, 0x41F1F, 0x40, 0x0,
case Intrinsic::hexagon_A2_subh_l16_sat_hl: // llvm.hexagon.A2.s 0x442E0, 0x442E0, 0x442E0, 0x442E0, 0x2E2B, 0x2E3A, 0x2E49, 0x2E2B,
ubh.l16.sat.hl 0x2E2B, 0x2E49, 0x2E49, 0x3A, 0x490, 0x2E2B0, 0x2E3A0, 0x2E490,
case Intrinsic::hexagon_A2_subh_l16_sat_ll: // llvm.hexagon.A2.s 0x2E490, 0x2E490, 0x494949, 0x2B2B2B, 0x3A3A3A, 0x494949, 0x2B2B2B, 0x3A3
ubh.l16.sat.ll A3A,
case Intrinsic::hexagon_A2_subri: // llvm.hexagon.A2.subri 0x494949, 0x2B2B2B, 0x3A3A3A, 0x494949, 0x2B2B2B, 0x3A3A3A, 0x494949, 0x4
case Intrinsic::hexagon_A2_subsat: // llvm.hexagon.A2.subsat 4969,
case Intrinsic::hexagon_A2_svaddh: // llvm.hexagon.A2.svaddh 0x44969, 0x696949, 0x696944, 0x696949, 0x696944, 0x2B2B2B, 0x2B2B44, 0x3A
case Intrinsic::hexagon_A2_svaddhs: // llvm.hexagon.A2.svaddhs 3A3A,
case Intrinsic::hexagon_A2_svadduhs: // llvm.hexagon.A2.svadduhs 0x3A3A44, 0x494949, 0x494944, 0x696949, 0x696944, 0x696949, 0x696944, 0x2
case Intrinsic::hexagon_A2_svavgh: // llvm.hexagon.A2.svavgh B2B2B,
case Intrinsic::hexagon_A2_svavghs: // llvm.hexagon.A2.svavghs 0x2B2B44, 0x3A3A3A, 0x3A3A44, 0x494949, 0x494944, 0x2B2B2B, 0x2B2B44, 0x3
case Intrinsic::hexagon_A2_svnavgh: // llvm.hexagon.A2.svnavgh A3A3A,
case Intrinsic::hexagon_A2_svsubh: // llvm.hexagon.A2.svsubh 0x3A3A44, 0x494949, 0x494944, 0x46949, 0x46949, 0x6969, 0x6969, 0x6969696
case Intrinsic::hexagon_A2_svsubhs: // llvm.hexagon.A2.svsubhs 9,
case Intrinsic::hexagon_A2_svsubuhs: // llvm.hexagon.A2.svsubuhs 0x696969, 0x2B2B2B, 0x3A3A3A, 0x494949, 0x2B2B2B, 0x3A3A3A, 0x494949, 0x3
case Intrinsic::hexagon_A2_tfrih: // llvm.hexagon.A2.tfrih A3A3A3A,
case Intrinsic::hexagon_A2_tfril: // llvm.hexagon.A2.tfril 0x3A3A3A3A, 0x696969, 0x2B2B2B, 0x3A3A3A, 0x494949, 0x2B2B2B, 0x3A3A3A, 0
case Intrinsic::hexagon_A2_xor: // llvm.hexagon.A2.xor x494949,
case Intrinsic::hexagon_A4_andn: // llvm.hexagon.A4.andn 0x3A3A3A3A, 0x492B2B49, 0x493A3A49, 0x493A3A49, 0x492B2B49, 0x493A3A49, 0
case Intrinsic::hexagon_A4_cround_ri: // llvm.hexagon.A4.c x493A3A49, 0x2B2B3A,
round.ri 0x3A3A49, 0x2B2B3A, 0x3A3A49, 0x2B2B3A, 0x3A3A49, 0x2B2B3A, 0x3A3A49, 0x6
case Intrinsic::hexagon_A4_cround_rr: // llvm.hexagon.A4.c 9696969,
round.rr 0x2B494949, 0x49493A, 0x3A3A2B, 0x3A3A2B, 0x49492B, 0x49493A, 0x3A3A2B, 0
case Intrinsic::hexagon_A4_modwrapu: // llvm.hexagon.A4.modwrapu x49493A,
case Intrinsic::hexagon_A4_orn: // llvm.hexagon.A4.orn 0x6969, 0x6969, 0x6969, 0x6969, 0x6969, 0x2B2B2B, 0x3A3A3A, 0x494949,
case Intrinsic::hexagon_A4_rcmpeq: // llvm.hexagon.A4.rcmpeq 0x6969, 0x49494949, 0x494949, 0x2B2B2B, 0x3A3A3A, 0x494949, 0x494949, 0x4
case Intrinsic::hexagon_A4_rcmpeqi: // llvm.hexagon.A4.rcmpeqi 94949,
case Intrinsic::hexagon_A4_rcmpneq: // llvm.hexagon.A4.rcmpneq 0x2B2B2B, 0x3A3A3A, 0x494949, 0x2B2B2B, 0x3A3A3A, 0x494949, 0x494949, 0x4
case Intrinsic::hexagon_A4_rcmpneqi: // llvm.hexagon.A4.rcmpneqi 94949,
case Intrinsic::hexagon_A4_round_ri: // llvm.hexagon.A4.round.ri 0x2B2B2B, 0x3A3A3A, 0x494949, 0x2B2B2B, 0x3A3A3A, 0x494949, 0x494949, 0x4
case Intrinsic::hexagon_A4_round_ri_sat: // llvm.hexagon.A4.r 92B49,
ound.ri.sat 0x493A49, 0x492B49, 0x494949, 0x3A49, 0x2B3A, 0x3A49, 0x3A49, 0x2B3A,
case Intrinsic::hexagon_A4_round_rr: // llvm.hexagon.A4.round.rr 0x3A49, 0x2E0, 0x2E0, 0x2E0, 0x2E0, 0x2E0, 0x2E0, 0x2E0,
case Intrinsic::hexagon_A4_round_rr_sat: // llvm.hexagon.A4.r 0x2E0, 0x0, 0x4442E0, (1U<<31) | 320, 0x40, 0x4, 0x5, 0x4,
ound.rr.sat 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4,
case Intrinsic::hexagon_C2_vitpack: // llvm.hexagon.C2.vitpack 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4,
case Intrinsic::hexagon_M2_cmpyrs_s0: // llvm.hexagon.M2.c 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4,
mpyrs.s0 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x5, 0x42E,
case Intrinsic::hexagon_M2_cmpyrs_s1: // llvm.hexagon.M2.c (1U<<31) | 0, 0x2E4, 0x42E0, 0x42E4, 0x1F1F, (1U<<31) | 0, 0x494949, 0x49
mpyrs.s1 4949,
case Intrinsic::hexagon_M2_cmpyrsc_s0: // llvm.hexagon.M2.c 0x3A3A3A, 0x33A3A, 0x34949, 0x494949, 0x22B2B, 0x494949, 0x33A3A, 0x34949
mpyrsc.s0 ,
case Intrinsic::hexagon_M2_cmpyrsc_s1: // llvm.hexagon.M2.c 0x494949, 0x494949, 0x494949, 0x2B2B2B, 0x22B2B, 0x3A3A3A, 0x33A3A, 0x349
mpyrsc.s1 49,
case Intrinsic::hexagon_M2_dpmpyss_rnd_s0: // llvm.hexagon.M2.d 0x494949, 0x494949, 0x2B2B2B, 0x22B2B, 0x3A3A3A, 0x33A3A, 0x34949, 0x4949
pmpyss.rnd.s0 49,
case Intrinsic::hexagon_M2_hmmpyh_rs1: // llvm.hexagon.M2.h 0x494949, 0x2B2B2B, 0x22B2B, 0x3A3A3A, 0x33A3A, 0x34949, 0x787878, 0x7878
mmpyh.rs1 78,
case Intrinsic::hexagon_M2_hmmpyl_rs1: // llvm.hexagon.M2.h 0x787878, 0x787878, 0x787878, 0x787878, 0x787878, 0x696969, 0x696969, 0x6
mmpyl.rs1 96969,
case Intrinsic::hexagon_M2_mpy_hh_s0: // llvm.hexagon.M2.m 0x696969, 0x696969, 0x696969, 0x69696969, 0x69696969, 0x69696969, 0x69696
py.hh.s0 9, 0x33A3A,
case Intrinsic::hexagon_M2_mpy_hh_s1: // llvm.hexagon.M2.m 0x3A3A49, 0x3A3A3A49, 0x3A4949, 0x3A3A49, 0x3A3A49, 0x3A3A49, 0x3A3A49, 0
py.hh.s1 x33A49,
case Intrinsic::hexagon_M2_mpy_hl_s0: // llvm.hexagon.M2.m 0x3A3A49, 0x3A3A49, 0x33A49, 0x494949, 0x494949, 0x494949, 0x22B2B, 0x494
py.hl.s0 949,
case Intrinsic::hexagon_M2_mpy_hl_s1: // llvm.hexagon.M2.m 0x33A3A, 0x34949, 0x494949, 0x3A3A3A, 0x33A3A, 0x34949, 0x494949, 0x24949
py.hl.s1 ,
case Intrinsic::hexagon_M2_mpy_lh_s0: // llvm.hexagon.M2.m 0x43A3A, 0x22B2B, 0x43A3A, 0x22B2B, 0x494949, 0x22B2B, 0x33A3A, 0x34949,
py.lh.s0 0x1F1F, (1U<<31) | 0, 0x2EE2E0, 0x2E0, 0x2E, 0x0, (1U<<31) | 0, (1U<<31)
case Intrinsic::hexagon_M2_mpy_lh_s1: // llvm.hexagon.M2.m | 0,
py.lh.s1 (1U<<31) | 0, 0x2E2E0, 0x2E0, 0x42E2E2E0, 0x2E0, 0xDDD, 0xDD, 0xDDD,
case Intrinsic::hexagon_M2_mpy_ll_s0: // llvm.hexagon.M2.m 0xDDD, 0xDDD, 0xDDD, 0xDDD, 0xDDD, 0xDDD, 0xDDD, 0xDD,
py.ll.s0 0xDDD, 0xDDD, 0xDDD, 0xDD, 0xDDD, 0xDDD, 0xDD, 0xDDD,
case Intrinsic::hexagon_M2_mpy_ll_s1: // llvm.hexagon.M2.m 0xDD, 0xDDD, 0xDDD, 0xDD, 0xDD, 0x585858, 0x585858, 0x585858,
py.ll.s1 0x585858, 0x5858, 0x25858, (1U<<31) | 29, (1U<<31) | 65, (1U<<31) | 193,
case Intrinsic::hexagon_M2_mpy_rnd_hh_s0: // llvm.hexagon.M2.m (1U<<31) | 227, (1U<<31) | 125,
py.rnd.hh.s0 (1U<<31) | 171, (1U<<31) | 77, (1U<<31) | 101, (1U<<31) | 41, (1U<<31) |
case Intrinsic::hexagon_M2_mpy_rnd_hh_s1: // llvm.hexagon.M2.m 53, (1U<<31) | 205, (1U<<31) | 239, (1U<<31) | 137,
py.rnd.hh.s1 (1U<<31) | 149, (1U<<31) | 89, (1U<<31) | 113, 0x492E49, 0x4A2E4A, 0x582E
case Intrinsic::hexagon_M2_mpy_rnd_hl_s0: // llvm.hexagon.M2.m 58, 0x592E59, 0x49492E0,
py.rnd.hl.s0 0x4A4A2E0, 0x58582E0, 0x59592E0, 0x2E59, 0x42C2C3B, 0x2C2C, 0x4A4A, 0x3B3
case Intrinsic::hexagon_M2_mpy_rnd_hl_s1: // llvm.hexagon.M2.m B,
py.rnd.hl.s1 0x4A4A3B, 0x3B3B2C, 0x4A4A3B, 0x3B3B2C, 0x2C2C2C, 0x3B3B3B, 0x2C2C2C, 0x3
case Intrinsic::hexagon_M2_mpy_rnd_lh_s0: // llvm.hexagon.M2.m B3B3B,
py.rnd.lh.s0 0x2C2C2C, 0x3B3B3B, 0x4494949, 0x44A4A4A, 0x2C2C2C2C, 0x43B3B3B, 0x2B2B,
case Intrinsic::hexagon_M2_mpy_rnd_lh_s1: // llvm.hexagon.M2.m 0x2B2C,
py.rnd.lh.s1 0x4949, 0x494A, 0x5858, 0x5859, 0x3A3A, 0x3A3B, 0x4A4A4A, 0x6A6A6A,
case Intrinsic::hexagon_M2_mpy_rnd_ll_s0: // llvm.hexagon.M2.m 0x4A4A4A, 0x3B3B3B, 0x3B3B3B, 0x4A4A4A, 0x3B3B3B, 0x3B3B3B, 0x2C2C3B, 0x3
py.rnd.ll.s0 B3B4A,
case Intrinsic::hexagon_M2_mpy_rnd_ll_s1: // llvm.hexagon.M2.m 0x2C2C2C, 0x4A4A4A, 0x3B3B3B, 0x2C2C2C, 0x4A4A4A, 0x3B3B3B, 0x2C2C2C, 0x4
py.rnd.ll.s1 A4A4A,
case Intrinsic::hexagon_M2_mpy_sat_hh_s0: // llvm.hexagon.M2.m 0x3B3B3B, 0x2C2C2C, 0x4A4A4A, 0x3B3B3B, 0x2C4, 0x2B4A, 0x2B59, 0x2B3B,
py.sat.hh.s0 0x4959, 0x3A4A, 0x3A59, 0x2B4A, 0x2B59, 0x2B3B, 0x4959, 0x3A4A,
case Intrinsic::hexagon_M2_mpy_sat_hh_s1: // llvm.hexagon.M2.m 0x3A59, 0x4A4A59, 0x3B3B3B, 0x3B3B3B, 0x3B3B3B, 0x4A4A59, 0x2C2C59, 0x2C2
py.sat.hh.s1 C2C,
case Intrinsic::hexagon_M2_mpy_sat_hl_s0: // llvm.hexagon.M2.m 0x2C2C2C, 0x4A4A4A, 0x3B3B3B, 0x494A4A, 0x45959, 0x45959, 0x585959, 0x3A3
py.sat.hl.s0 B3B,
case Intrinsic::hexagon_M2_mpy_sat_hl_s1: // llvm.hexagon.M2.m 0x44A4A, 0x45959, 0x43B3B, 0x494949, 0x4A4A4A, 0x585858, 0x595959, 0x494A
py.sat.hl.s1 4A,
case Intrinsic::hexagon_M2_mpy_sat_lh_s0: // llvm.hexagon.M2.m 0x3A3B3B, 0x44A4A, 0x43B3B, 0x494949, 0x4A4A4A, 0x494A4A, 0x45959, 0x4595
py.sat.lh.s0 9,
case Intrinsic::hexagon_M2_mpy_sat_lh_s1: // llvm.hexagon.M2.m 0x585959, 0x3A3B3B, 0x44A4A, 0x45959, 0x43B3B, 0x494949, 0x4A4A4A, 0x5858
py.sat.lh.s1 58,
case Intrinsic::hexagon_M2_mpy_sat_ll_s0: // llvm.hexagon.M2.m 0x595959, 0x2C2C2C, 0x3B3B3B, 0x2C2C2C, 0x3B3B3B, 0x7879, 0x6969, 0x696A,
py.sat.ll.s0 0x2E59, 0x25958, 0x2585959, 0x2595959, 0x797979, 0x6A6A6A, 0x4797979, 0x4
case Intrinsic::hexagon_M2_mpy_sat_ll_s1: // llvm.hexagon.M2.m 6A6A6A,
py.sat.ll.s1 0x79797979, 0x6A6A6A6A, 0x2797979, 0x26A6A6A, 0x7969, 0x7949, 0x6979, 0x6
case Intrinsic::hexagon_M2_mpy_sat_rnd_hh_s0: // llvm.hexa A4A,
gon.M2.mpy.sat.rnd.hh.s0 0x4979, 0x4A6A, 0x7949, 0x6A4A, 0x46A6A6A, 0x797979, 0x6A6A6A, 0x797979,
case Intrinsic::hexagon_M2_mpy_sat_rnd_hh_s1: // llvm.hexa 0x6A6A6A, 0x2E2C, 0x782E78, 0x792E79, 0x692E69, 0x6A2E6A, 0x78782E0, 0x79
gon.M2.mpy.sat.rnd.hh.s1 792E0,
case Intrinsic::hexagon_M2_mpy_sat_rnd_hl_s0: // llvm.hexa 0x69692E0, 0x6A6A2E0, 0x797979, 0x6A6A6A, 0x797979, 0x6A6A6A, 0x794, 0x6A
gon.M2.mpy.sat.rnd.hl.s0 4,
case Intrinsic::hexagon_M2_mpy_sat_rnd_hl_s1: // llvm.hexa 0x59594, 0x59594, 0x59594, 0x6A6A, 0x47979, 0x46A6A, 0x6A6A, 0x7979,
gon.M2.mpy.sat.rnd.hl.s1 0x6A6A, 0x2C2E0, 0x792E0, 0x6A2E0, 0x2E79, 0x2E69, 0x2E6A, 0x2E79,
case Intrinsic::hexagon_M2_mpy_sat_rnd_lh_s0: // llvm.hexa 0x2E6A, 0x27978, 0x26A69, 0x24A49, 0x2787979, 0x2696A6A, 0x2494A4A, 0x279
gon.M2.mpy.sat.rnd.lh.s0 7979,
case Intrinsic::hexagon_M2_mpy_sat_rnd_lh_s1: // llvm.hexa 0x26A6A6A, 0x24A4A4A, 0x587878, 0x597979, 0x496969, 0x4A6A6A, 0x78784, 0x
gon.M2.mpy.sat.rnd.lh.s1 79794,
case Intrinsic::hexagon_M2_mpy_sat_rnd_ll_s0: // llvm.hexa 0x69694, 0x6A6A4, 0x78784, 0x79794, 0x69694, 0x6A6A4, 0x78784, 0x79794,
gon.M2.mpy.sat.rnd.ll.s0 0x69694, 0x6A6A4, 0x0, 0x0, 0x444, 0x555, 0x444, 0x555,
case Intrinsic::hexagon_M2_mpy_sat_rnd_ll_s1: // llvm.hexa 0x444, 0x555, 0x444, 0x555, 0x78787878, 0x79797979, 0x69696969, 0x6A6A6A6
gon.M2.mpy.sat.rnd.ll.s1 A,
case Intrinsic::hexagon_M2_mpy_up: // llvm.hexagon.M2.mpy.up 0x78787878, 0x69696969, 0x78787878, 0x79797979, 0x69696969, 0x6A6A6A6A, 0
case Intrinsic::hexagon_M2_mpyi: // llvm.hexagon.M2.mpyi x78787878, 0x79797979,
case Intrinsic::hexagon_M2_mpysmi: // llvm.hexagon.M2.mpysmi 0x69696969, 0x6A6A6A6A, 0x78787878, 0x69696969, 0x78787878, 0x79797979, 0
case Intrinsic::hexagon_M2_mpyu_hh_s0: // llvm.hexagon.M2.m x69696969, 0x6A6A6A6A,
pyu.hh.s0 0x78787878, 0x79797979, 0x69696969, 0x6A6A6A6A, 0x78787878, 0x69696969, 0
case Intrinsic::hexagon_M2_mpyu_hh_s1: // llvm.hexagon.M2.m x78787878, 0x79797979,
pyu.hh.s1 0x69696969, 0x6A6A6A6A, 0x78787878, 0x69696969, 0x20, 0x0, 0x0, 0x2EDD0,
case Intrinsic::hexagon_M2_mpyu_hl_s0: // llvm.hexagon.M2.m 0xDDE0, 0xDDD, 0xDDD, 0xDDD, 0xDDD, 0xDDD, 0xDDD, 0xDDD,
pyu.hl.s0 0xDDD, 0xDDD, 0xDDD, 0xDDD, 0x2DDD, 0xDDD, 0xDDD, 0xDDD,
case Intrinsic::hexagon_M2_mpyu_hl_s1: // llvm.hexagon.M2.m 0xDDD, 0xDDD, 0xDDD, 0xDDD, 0xDDD, 0xDDD, 0xDDD, 0x4D4,
pyu.hl.s1 0x44DD, 0xDDD, 0xDDD, 0xDDD, 0xDDD, 0xDDD, 0xD4, 0xDDD,
case Intrinsic::hexagon_M2_mpyu_lh_s0: // llvm.hexagon.M2.m 0xDDD, 0xDDD, 0xDDD, 0xDDD, 0xDDD, 0xDDD, 0xDDD, 0xDDD,
pyu.lh.s0 0x4DD, 0x4DD, 0x4DD, 0xDDD, 0xDDD, 0x4DD, 0x4DD, 0xDDD,
case Intrinsic::hexagon_M2_mpyu_lh_s1: // llvm.hexagon.M2.m 0xDDD, 0xDDD, 0x4DD, 0x4DD, 0x4DD, 0xDDD, 0xDDD, 0xDDD,
pyu.lh.s1 0xDDD, 0xDDD, 0xDDD, 0xDDD, 0xDDD, 0xDDD, 0xDDD, 0xDDD,
case Intrinsic::hexagon_M2_mpyu_ll_s0: // llvm.hexagon.M2.m 0xDDD, 0xDDD, 0xDDD, 0xDDD, 0x2585858, 0x4, 0x5, 0x4,
pyu.ll.s0 0x5, (1U<<31) | 387, (1U<<31) | 488, (1U<<31) | 492, 0x787878, 0x2E0, 0x2
case Intrinsic::hexagon_M2_mpyu_ll_s1: // llvm.hexagon.M2.m 787878, 0x2787878,
pyu.ll.s1 0x78784, 0x78784, 0x78784, 0x78784, 0x78784, 0x78784, 0x4978, 0x4969,
case Intrinsic::hexagon_M2_mpyu_up: // llvm.hexagon.M2.mpyu.up 0x7849, 0x7869, 0x6949, 0x6978, 0x784, 0x785, 0x786969, 0x47878,
case Intrinsic::hexagon_M2_mpyui: // llvm.hexagon.M2.mpyui 0x57878, 0x697878, 0x7849, 0x6949, 0x784, 0x785, 0x787878, 0x0,
case Intrinsic::hexagon_M2_vmpy2s_s0pack: // llvm.hexagon.M2.v 0x2E2B2B0, 0x787878, 0x787878, 0x0, 0x787878, 0x787878, 0x784, 0x787878,
mpy2s.s0pack 0x49493A, 0x3A3A2B, 0x3A3A2B, 0x2B2B2B, 0x3A3A3A, 0x2B2B2B, 0x3A3A3A, 0x2
case Intrinsic::hexagon_M2_vmpy2s_s1pack: // llvm.hexagon.M2.v B2B2B,
mpy2s.s1pack 0x3A3A3A, 0x3A3A49, 0x3A3A3A, 0x2B2B2B, 0x3A3A3A, 0x2B2B2B, 0x2B4, 0x3A3A
case Intrinsic::hexagon_S2_asl_i_r: // llvm.hexagon.S2.asl.i.r 3A,
case Intrinsic::hexagon_S2_asl_i_r_sat: // llvm.hexagon.S2.a 0x3A3A3A, 0x494958, 0x2B2B58, 0x494949, 0x45858, 0x45858, 0x585858, 0x3A3
sl.i.r.sat A3A,
case Intrinsic::hexagon_S2_asl_r_r: // llvm.hexagon.S2.asl.r.r 0x44949, 0x45858, 0x43A3A, 0x494949, 0x3A3A3A, 0x44949, 0x43A3A, 0x494949
case Intrinsic::hexagon_S2_asl_r_r_sat: // llvm.hexagon.S2.a ,
sl.r.r.sat 0x45858, 0x45858, 0x585858, 0x3A3A3A, 0x44949, 0x45858, 0x43A3A, 0x2B2B2B
case Intrinsic::hexagon_S2_asr_i_r: // llvm.hexagon.S2.asr.i.r ,
case Intrinsic::hexagon_S2_asr_i_r_rnd: // llvm.hexagon.S2.a 0x3A3A3A, 0x2B2B2B, 0x3A3A3A, 0x7878, 0x7878, 0x492E0, 0x2B2E0, 0x782E0,
sr.i.r.rnd 0x787878, 0x78784, 0x78784, 0x78784, 0x78784, 0x78784, 0x78784, 0x787878,
case Intrinsic::hexagon_S2_asr_i_r_rnd_goodsyntax: // llvm.hexa 0x696969, 0x787878, 0x696969, 0x787878, 0x696969, 0x2E2B, 0x442E0, 0x440,
gon.S2.asr.i.r.rnd.goodsyntax 0x4787878, 0x4696969, 0x78787878, 0x69696969, 0x4787878, 0x4696969, 0x469
case Intrinsic::hexagon_S2_asr_r_r: // llvm.hexagon.S2.asr.r.r 4, 0x4696969,
case Intrinsic::hexagon_S2_asr_r_r_sat: // llvm.hexagon.S2.a 0x2E58, 0x42B2B3A, 0x49493A, 0x2B2B2B2B, 0x43A3A3A, 0x42B4, 0x4494, 0x458
sr.r.r.sat 5,
case Intrinsic::hexagon_S2_clrbit_i: // llvm.hexagon.S2.clrbit.i 0x3A3A, 0x2B2B2B, 0x494949, 0x494949, 0x3A3A3A, 0x2B2B2B, 0x494949, 0x494
case Intrinsic::hexagon_S2_clrbit_r: // llvm.hexagon.S2.clrbit.r 949,
case Intrinsic::hexagon_S2_lsl_r_r: // llvm.hexagon.S2.lsl.r.r 0x3A3A3A, 0x2B49, 0x2B58, 0x2B3A, 0x4958, 0x3A49, 0x3A58, 0x2B49,
case Intrinsic::hexagon_S2_lsr_i_r: // llvm.hexagon.S2.lsr.i.r 0x2B58, 0x2B3A, 0x4958, 0x3A49, 0x3A58, 0x494958, 0x58584, 0x58584,
case Intrinsic::hexagon_S2_lsr_r_r: // llvm.hexagon.S2.lsr.r.r 0x58584, 0x47878, 0x46969, 0x4787878, 0x4696969, 0x344, 0x444, 0x244,
case Intrinsic::hexagon_S2_setbit_i: // llvm.hexagon.S2.setbit.i 0x555, 0x255, 0x242B42B4, 0x242B42B4, 0x242B42B4, 0x242B42B4, 0x242B42B4,
case Intrinsic::hexagon_S2_setbit_r: // llvm.hexagon.S2.setbit.r 0x242B42B4,
case Intrinsic::hexagon_S2_togglebit_i: // llvm.hexagon.S2.t (1U<<31) | 19, 0x22B2B4, 0x22B2B4, 0x22B2B4, 0x22B2B4, 0x22B2B4, 0x22B2B4
ogglebit.i , 0x22B2B2B,
case Intrinsic::hexagon_S2_togglebit_r: // llvm.hexagon.S2.t 0x2B5858, 0x225858, 0x585858, 0x22585858, 0x782E0, 0x692E0, 0x696969, 0x2
ogglebit.r 696969,
case Intrinsic::x86_bmi_bextr_32: // llvm.x86.bmi.bextr.32 0x2696969, 0x69694, 0x69694, 0x69694, 0x69694, 0x69694, 0x69694, 0x78D,
case Intrinsic::x86_bmi_bzhi_32: // llvm.x86.bmi.bzhi.32 0xD78, 0xD6969, 0x69D, 0x46969, 0x56969, 0x694, 0x695, 0x78D,
case Intrinsic::x86_bmi_pdep_32: // llvm.x86.bmi.pdep.32 0x69D, 0x694, 0x695, 0x696969, 0x2E0, 0x696969, 0x696969, 0x696969,
case Intrinsic::x86_bmi_pext_32: // llvm.x86.bmi.pext.32 0x696969, 0x694, 0x696969, 0x2DD, 0x6969, 0x6969, 0x6969, 0x6969,
case Intrinsic::x86_sse42_crc32_32_32: // llvm.x86.sse42.cr 0x0, 0x6969, 0x6969, 0x2E0, 0x692E0, 0x696969, 0x69694, 0x69694,
c32.32.32 0x69694, 0x69694, 0x69694, 0x69694, 0xDD, 0x2B2B, 0xDD, 0x4949,
case Intrinsic::xcore_sext: // llvm.xcore.sext 0xDD, 0x3A3A, 0xDDD, 0x494949, 0xDDD, 0x3A3A3A, 0xDDD, 0x3A3A3A,
case Intrinsic::xcore_zext: // llvm.xcore.zext 0xDDD, 0x494949, 0xDDD, 0x3A3A3A, 0xDDD, 0x3A3A3A, 0xDDD, 0x2B2B3A,
ResultTy = IntegerType::get(Context, 32); 0xDDD, 0x3A3A3A, 0xDDD, 0x2B2B2B, 0xDDD, 0x2B2B2B, 0xDDD, 0x494949,
ArgTys.push_back(IntegerType::get(Context, 32)); 0xDDD, 0x3A3A3A, 0x3A69, 0x3A6A, 0x4693A, 0x46A3A, 0x40, 0x50,
ArgTys.push_back(IntegerType::get(Context, 32)); 0x40, 0x50, 0x20, 0x4, 0x0, 0x7878, 0x7979, 0x6969,
break; 0x6A6A, 0x7878, 0x6969, 0x58585858, 0x59595959, 0x22B2B2B, 0x2494949, 0x2
case Intrinsic::hexagon_C2_mux: // llvm.hexagon.C2.mux 585858,
case Intrinsic::hexagon_C2_muxii: // llvm.hexagon.C2.muxii 0x22B2B2B, 0x2494949, 0x2585858, 0x23A3A3A, 0x23A3A3A, (1U<<31) | 217, (1
case Intrinsic::hexagon_C2_muxir: // llvm.hexagon.C2.muxir U<<31) | 251, (1U<<31) | 161,
case Intrinsic::hexagon_C2_muxri: // llvm.hexagon.C2.muxri (1U<<31) | 183, 0x2B49, 0x2B58, 0x2B3A, 0x4958, 0x2B49, 0x2B58, 0x2B3A,
case Intrinsic::hexagon_M2_acci: // llvm.hexagon.M2.acci 0x4958, 0x3A49, 0x3A58, 0x3A49, 0x3A58, 0x2B3A, 0x4958, 0x3A49,
case Intrinsic::hexagon_M2_accii: // llvm.hexagon.M2.accii 0x49494949, 0x58494958, 0x58494958, 0x49494949, 0x58494958, 0x58494958, 0
case Intrinsic::hexagon_M2_maci: // llvm.hexagon.M2.maci x493A3A49, 0x3A3A3A3A,
case Intrinsic::hexagon_M2_macsin: // llvm.hexagon.M2.macsin 0x493A3A49, 0x3A3A3A3A, 0x493A3A49, 0x493A3A49, 0x2B2B2B2B, 0x2B2B2B, 0x2
case Intrinsic::hexagon_M2_macsip: // llvm.hexagon.M2.macsip 2B2B, 0x494949,
case Intrinsic::hexagon_M2_mpy_acc_hh_s0: // llvm.hexagon.M2.m 0x24949, 0x585858, 0x25858, 0x3A3A3A, 0x23A3A, 0x2B2B2B, 0x494949, 0x5858
py.acc.hh.s0 58,
case Intrinsic::hexagon_M2_mpy_acc_hh_s1: // llvm.hexagon.M2.m 0x3A3A3A, 0x2B2B2B, 0x494949, 0x585858, 0x3A3A3A, 0x44, 0x2E2E, 0x43F0,
py.acc.hh.s1 0x0, 0x40, 0x4444, (1U<<31) | 481, 0x3F0, 0x3F4, 0x3F0, 0x4,
case Intrinsic::hexagon_M2_mpy_acc_hl_s0: // llvm.hexagon.M2.m 0x4, 0x4, 0x44, 0x43F, 0x7F3F, 0x3F4, 0x3F4, 0x3F4,
py.acc.hl.s0 0x2E3F0, 0x2E3F0, 0x2E3F0, 0x2E3F0, 0x2E3F0, 0x43F4, 0x3F4, 0x3F0,
case Intrinsic::hexagon_M2_mpy_acc_hl_s1: // llvm.hexagon.M2.m 0x3F0, 0x43F0, 0x43F0, 0x43F4, 0x43F0, 0x3F4, 0x43F0, 0x7F3F0,
py.acc.hl.s1 0x43F0, 0x2E3F0, 0x440, 0x43F0, 0x43F0, 0x7F3F0, 0x40, 0x43F0,
case Intrinsic::hexagon_M2_mpy_acc_lh_s0: // llvm.hexagon.M2.m 0x2E3F0, 0x444, 0x0, 0x3F0, 0x3F4, 0x3F4, 0x2E, 0x444, 0
py.acc.lh.s0 };
case Intrinsic::hexagon_M2_mpy_acc_lh_s1: // llvm.hexagon.M2.m
py.acc.lh.s1 static const unsigned char IIT_LongEncodingTable[] = {
case Intrinsic::hexagon_M2_mpy_acc_ll_s0: // llvm.hexagon.M2.m /* 0 */ 18, 15, 0, 1, 15, 0, 15, 0, 0,
py.acc.ll.s0 /* 9 */ 0, 15, 3, 15, 7, 15, 8, 4, 1, 0,
case Intrinsic::hexagon_M2_mpy_acc_ll_s1: // llvm.hexagon.M2.m /* 19 */ 11, 2, 11, 2, 4, 11, 2, 4, 2, 0,
py.acc.ll.s1 /* 29 */ 9, 4, 9, 4, 14, 2, 9, 4, 9, 4, 2, 0,
case Intrinsic::hexagon_M2_mpy_acc_sat_hh_s0: // llvm.hexa /* 41 */ 9, 4, 9, 4, 14, 2, 8, 5, 9, 4, 2, 0,
gon.M2.mpy.acc.sat.hh.s0 /* 53 */ 9, 4, 9, 4, 14, 2, 9, 5, 9, 4, 2, 0,
case Intrinsic::hexagon_M2_mpy_acc_sat_hh_s1: // llvm.hexa /* 65 */ 10, 4, 10, 4, 14, 2, 10, 4, 10, 4, 2, 0,
gon.M2.mpy.acc.sat.hh.s1 /* 77 */ 8, 5, 8, 5, 14, 2, 9, 4, 8, 5, 2, 0,
case Intrinsic::hexagon_M2_mpy_acc_sat_hl_s0: // llvm.hexa /* 89 */ 8, 5, 8, 5, 14, 2, 8, 5, 8, 5, 2, 0,
gon.M2.mpy.acc.sat.hl.s0 /* 101 */ 9, 5, 9, 5, 14, 2, 9, 4, 9, 5, 2, 0,
case Intrinsic::hexagon_M2_mpy_acc_sat_hl_s1: // llvm.hexa /* 113 */ 9, 5, 9, 5, 14, 2, 9, 5, 9, 5, 2, 0,
gon.M2.mpy.acc.sat.hl.s1 /* 125 */ 9, 6, 9, 6, 14, 2, 9, 4, 9, 6, 2, 0,
case Intrinsic::hexagon_M2_mpy_acc_sat_lh_s0: // llvm.hexa /* 137 */ 9, 6, 9, 6, 14, 2, 8, 5, 9, 6, 2, 0,
gon.M2.mpy.acc.sat.lh.s0 /* 149 */ 9, 6, 9, 6, 14, 2, 9, 5, 9, 6, 2, 0,
case Intrinsic::hexagon_M2_mpy_acc_sat_lh_s1: // llvm.hexa /* 161 */ 9, 6, 9, 6, 9, 6, 9, 6, 2, 0,
gon.M2.mpy.acc.sat.lh.s1 /* 171 */ 10, 6, 10, 6, 14, 2, 10, 4, 10, 6, 2, 0,
case Intrinsic::hexagon_M2_mpy_acc_sat_ll_s0: // llvm.hexa /* 183 */ 10, 6, 10, 6, 10, 6, 10, 6, 2, 0,
gon.M2.mpy.acc.sat.ll.s0 /* 193 */ 8, 7, 8, 7, 14, 2, 9, 4, 8, 7, 2, 0,
case Intrinsic::hexagon_M2_mpy_acc_sat_ll_s1: // llvm.hexa /* 205 */ 8, 7, 8, 7, 14, 2, 8, 5, 8, 7, 2, 0,
gon.M2.mpy.acc.sat.ll.s1 /* 217 */ 8, 7, 8, 7, 8, 7, 8, 7, 2, 0,
case Intrinsic::hexagon_M2_mpy_nac_hh_s0: // llvm.hexagon.M2.m /* 227 */ 9, 7, 9, 7, 14, 2, 9, 4, 9, 7, 2, 0,
py.nac.hh.s0 /* 239 */ 9, 7, 9, 7, 14, 2, 9, 5, 9, 7, 2, 0,
case Intrinsic::hexagon_M2_mpy_nac_hh_s1: // llvm.hexagon.M2.m /* 251 */ 9, 7, 9, 7, 9, 7, 9, 7, 2, 0,
py.nac.hh.s1 /* 261 */ 10, 2, 10, 2, 10, 2, 10, 2, 10, 2, 10, 2, 10, 2, 0,
case Intrinsic::hexagon_M2_mpy_nac_hl_s0: // llvm.hexagon.M2.m /* 276 */ 18, 4, 4, 14, 2, 0,
py.nac.hl.s0 /* 282 */ 0, 14, 17, 5, 14, 2, 0,
case Intrinsic::hexagon_M2_mpy_nac_hl_s1: // llvm.hexagon.M2.m /* 289 */ 15, 2, 22, 2, 0,
py.nac.hl.s1 /* 294 */ 15, 2, 22, 2, 22, 2, 0,
case Intrinsic::hexagon_M2_mpy_nac_lh_s0: // llvm.hexagon.M2.m /* 301 */ 15, 2, 15, 2, 23, 2, 23, 2, 0,
py.nac.lh.s0 /* 310 */ 15, 0, 15, 0, 14, 2, 14, 2, 4, 0,
case Intrinsic::hexagon_M2_mpy_nac_lh_s1: // llvm.hexagon.M2.m /* 320 */ 15, 3, 15, 3, 14, 2, 14, 2, 4, 0,
py.nac.lh.s1 /* 330 */ 20, 15, 2, 15, 2, 15, 2, 15, 2, 14, 2, 4, 0,
case Intrinsic::hexagon_M2_mpy_nac_ll_s0: // llvm.hexagon.M2.m /* 343 */ 19, 15, 2, 15, 2, 15, 2, 14, 2, 4, 0,
py.nac.ll.s0 /* 354 */ 18, 15, 2, 15, 2, 14, 2, 4, 0,
case Intrinsic::hexagon_M2_mpy_nac_ll_s1: // llvm.hexagon.M2.m /* 363 */ 0, 14, 2, 15, 2, 15, 2, 15, 2, 4, 0,
py.nac.ll.s1 /* 374 */ 0, 14, 2, 15, 2, 15, 2, 15, 2, 15, 2, 4, 0,
case Intrinsic::hexagon_M2_mpy_nac_sat_hh_s0: // llvm.hexa /* 387 */ 18, 3, 4, 0,
gon.M2.mpy.nac.sat.hh.s0 /* 391 */ 0, 14, 2, 15, 2, 15, 2, 4, 4, 0,
case Intrinsic::hexagon_M2_mpy_nac_sat_hh_s1: // llvm.hexa /* 401 */ 18, 15, 2, 15, 2, 14, 2, 15, 2, 15, 2, 4, 4, 0,
gon.M2.mpy.nac.sat.hh.s1 /* 415 */ 0, 14, 2, 15, 2, 15, 2, 15, 2, 4, 4, 0,
case Intrinsic::hexagon_M2_mpy_nac_sat_hl_s0: // llvm.hexa /* 427 */ 19, 15, 2, 15, 2, 15, 2, 14, 2, 15, 2, 15, 2, 15, 2, 4, 4, 0,
gon.M2.mpy.nac.sat.hl.s0 /* 445 */ 0, 14, 2, 15, 2, 15, 2, 15, 2, 15, 2, 4, 4, 0,
case Intrinsic::hexagon_M2_mpy_nac_sat_hl_s1: // llvm.hexa /* 459 */ 20, 15, 2, 15, 2, 15, 2, 15, 2, 14, 2, 15, 2, 15, 2, 15, 2, 15,
gon.M2.mpy.nac.sat.hl.s1 2, 4, 4, 0,
case Intrinsic::hexagon_M2_mpy_nac_sat_lh_s0: // llvm.hexa /* 481 */ 18, 4, 4, 4, 4, 4, 0,
gon.M2.mpy.nac.sat.lh.s0 /* 488 */ 18, 4, 4, 0,
case Intrinsic::hexagon_M2_mpy_nac_sat_lh_s1: // llvm.hexa /* 492 */ 18, 5, 4, 0,
gon.M2.mpy.nac.sat.lh.s1 /* 496 */ 0, 16, 5, 16, 0,
case Intrinsic::hexagon_M2_mpy_nac_sat_ll_s0: // llvm.hexa /* 501 */ 0, 16, 16, 0,
gon.M2.mpy.nac.sat.ll.s0 255
case Intrinsic::hexagon_M2_mpy_nac_sat_ll_s1: // llvm.hexa };
gon.M2.mpy.nac.sat.ll.s1
case Intrinsic::hexagon_M2_mpyu_acc_hh_s0: // llvm.hexagon.M2.m #endif
pyu.acc.hh.s0
case Intrinsic::hexagon_M2_mpyu_acc_hh_s1: // llvm.hexagon.M2.m // Add parameter attributes that are not common to all intrinsics.
pyu.acc.hh.s1 #ifdef GET_INTRINSIC_ATTRIBUTES
case Intrinsic::hexagon_M2_mpyu_acc_hl_s0: // llvm.hexagon.M2.m AttrListPtr Intrinsic::getAttributes(LLVMContext &C, ID id) {
pyu.acc.hl.s0 static const uint8_t IntrinsicsToAttributesMap[] = {
case Intrinsic::hexagon_M2_mpyu_acc_hl_s1: // llvm.hexagon.M2.m 1, // llvm.adjust.trampoline
pyu.acc.hl.s1 2, // llvm.annotation
case Intrinsic::hexagon_M2_mpyu_acc_lh_s0: // llvm.hexagon.M2.m 2, // llvm.arm.cdp
pyu.acc.lh.s0 2, // llvm.arm.cdp2
case Intrinsic::hexagon_M2_mpyu_acc_lh_s1: // llvm.hexagon.M2.m 3, // llvm.arm.get.fpscr
pyu.acc.lh.s1 1, // llvm.arm.ldrexd
case Intrinsic::hexagon_M2_mpyu_acc_ll_s0: // llvm.hexagon.M2.m 2, // llvm.arm.mcr
pyu.acc.ll.s0
case Intrinsic::hexagon_M2_mpyu_acc_ll_s1: // llvm.hexagon.M2.m
pyu.acc.ll.s1
case Intrinsic::hexagon_M2_mpyu_nac_hh_s0: // llvm.hexagon.M2.m
pyu.nac.hh.s0
case Intrinsic::hexagon_M2_mpyu_nac_hh_s1: // llvm.hexagon.M2.m
pyu.nac.hh.s1
case Intrinsic::hexagon_M2_mpyu_nac_hl_s0: // llvm.hexagon.M2.m
pyu.nac.hl.s0
case Intrinsic::hexagon_M2_mpyu_nac_hl_s1: // llvm.hexagon.M2.m
pyu.nac.hl.s1
case Intrinsic::hexagon_M2_mpyu_nac_lh_s0: // llvm.hexagon.M2.m
pyu.nac.lh.s0
case Intrinsic::hexagon_M2_mpyu_nac_lh_s1: // llvm.hexagon.M2.m
pyu.nac.lh.s1
case Intrinsic::hexagon_M2_mpyu_nac_ll_s0: // llvm.hexagon.M2.m
pyu.nac.ll.s0
case Intrinsic::hexagon_M2_mpyu_nac_ll_s1: // llvm.hexagon.M2.m
pyu.nac.ll.s1
case Intrinsic::hexagon_M2_nacci: // llvm.hexagon.M2.nacci
case Intrinsic::hexagon_M2_naccii: // llvm.hexagon.M2.naccii
case Intrinsic::hexagon_M2_subacc: // llvm.hexagon.M2.subacc
case Intrinsic::hexagon_M2_xor_xacc: // llvm.hexagon.M2.xor.xacc
case Intrinsic::hexagon_M4_and_and: // llvm.hexagon.M4.and.and
case Intrinsic::hexagon_M4_and_andn: // llvm.hexagon.M4.and.andn
case Intrinsic::hexagon_M4_and_or: // llvm.hexagon.M4.and.or
case Intrinsic::hexagon_M4_and_xor: // llvm.hexagon.M4.and.xor
case Intrinsic::hexagon_M4_or_and: // llvm.hexagon.M4.or.and
case Intrinsic::hexagon_M4_or_andn: // llvm.hexagon.M4.or.andn
case Intrinsic::hexagon_M4_or_or: // llvm.hexagon.M4.or.or
case Intrinsic::hexagon_M4_or_xor: // llvm.hexagon.M4.or.xor
case Intrinsic::hexagon_M4_xor_and: // llvm.hexagon.M4.xor.and
case Intrinsic::hexagon_M4_xor_andn: // llvm.hexagon.M4.xor.andn
case Intrinsic::hexagon_M4_xor_or: // llvm.hexagon.M4.xor.or
case Intrinsic::hexagon_S2_addasl_rrri: // llvm.hexagon.S2.a
ddasl.rrri
case Intrinsic::hexagon_S2_asl_i_r_acc: // llvm.hexagon.S2.a
sl.i.r.acc
case Intrinsic::hexagon_S2_asl_i_r_and: // llvm.hexagon.S2.a
sl.i.r.and
case Intrinsic::hexagon_S2_asl_i_r_nac: // llvm.hexagon.S2.a
sl.i.r.nac
case Intrinsic::hexagon_S2_asl_i_r_or: // llvm.hexagon.S2.a
sl.i.r.or
case Intrinsic::hexagon_S2_asl_i_r_xacc: // llvm.hexagon.S2.a
sl.i.r.xacc
case Intrinsic::hexagon_S2_asl_r_r_acc: // llvm.hexagon.S2.a
sl.r.r.acc
case Intrinsic::hexagon_S2_asl_r_r_and: // llvm.hexagon.S2.a
sl.r.r.and
case Intrinsic::hexagon_S2_asl_r_r_nac: // llvm.hexagon.S2.a
sl.r.r.nac
case Intrinsic::hexagon_S2_asl_r_r_or: // llvm.hexagon.S2.a
sl.r.r.or
case Intrinsic::hexagon_S2_asr_i_r_acc: // llvm.hexagon.S2.a
sr.i.r.acc
case Intrinsic::hexagon_S2_asr_i_r_and: // llvm.hexagon.S2.a
sr.i.r.and
case Intrinsic::hexagon_S2_asr_i_r_nac: // llvm.hexagon.S2.a
sr.i.r.nac
case Intrinsic::hexagon_S2_asr_i_r_or: // llvm.hexagon.S2.a
sr.i.r.or
case Intrinsic::hexagon_S2_asr_r_r_acc: // llvm.hexagon.S2.a
sr.r.r.acc
case Intrinsic::hexagon_S2_asr_r_r_and: // llvm.hexagon.S2.a
sr.r.r.and
case Intrinsic::hexagon_S2_asr_r_r_nac: // llvm.hexagon.S2.a
sr.r.r.nac
case Intrinsic::hexagon_S2_asr_r_r_or: // llvm.hexagon.S2.a
sr.r.r.or
case Intrinsic::hexagon_S2_extractu: // llvm.hexagon.S2.extractu
case Intrinsic::hexagon_S2_lsl_r_r_acc: // llvm.hexagon.S2.l
sl.r.r.acc
case Intrinsic::hexagon_S2_lsl_r_r_and: // llvm.hexagon.S2.l
sl.r.r.and
case Intrinsic::hexagon_S2_lsl_r_r_nac: // llvm.hexagon.S2.l
sl.r.r.nac
case Intrinsic::hexagon_S2_lsl_r_r_or: // llvm.hexagon.S2.l
sl.r.r.or
case Intrinsic::hexagon_S2_lsr_i_r_acc: // llvm.hexagon.S2.l
sr.i.r.acc
case Intrinsic::hexagon_S2_lsr_i_r_and: // llvm.hexagon.S2.l
sr.i.r.and
case Intrinsic::hexagon_S2_lsr_i_r_nac: // llvm.hexagon.S2.l
sr.i.r.nac
case Intrinsic::hexagon_S2_lsr_i_r_or: // llvm.hexagon.S2.l
sr.i.r.or
case Intrinsic::hexagon_S2_lsr_i_r_xacc: // llvm.hexagon.S2.l
sr.i.r.xacc
case Intrinsic::hexagon_S2_lsr_r_r_acc: // llvm.hexagon.S2.l
sr.r.r.acc
case Intrinsic::hexagon_S2_lsr_r_r_and: // llvm.hexagon.S2.l
sr.r.r.and
case Intrinsic::hexagon_S2_lsr_r_r_nac: // llvm.hexagon.S2.l
sr.r.r.nac
case Intrinsic::hexagon_S2_lsr_r_r_or: // llvm.hexagon.S2.l
sr.r.r.or
case Intrinsic::hexagon_S4_addaddi: // llvm.hexagon.S4.addaddi
case Intrinsic::hexagon_S4_or_andi: // llvm.hexagon.S4.or.andi
case Intrinsic::hexagon_S4_or_andix: // llvm.hexagon.S4.or.andix
case Intrinsic::hexagon_S4_or_ori: // llvm.hexagon.S4.or.ori
case Intrinsic::hexagon_S4_subaddi: // llvm.hexagon.S4.subaddi
case Intrinsic::xcore_crc32: // llvm.xcore.crc32
ResultTy = IntegerType::get(Context, 32);
ArgTys.push_back(IntegerType::get(Context, 32));
ArgTys.push_back(IntegerType::get(Context, 32));
ArgTys.push_back(IntegerType::get(Context, 32));
break;
case Intrinsic::hexagon_S2_insert: // llvm.hexagon.S2.insert
case Intrinsic::hexagon_S2_tableidxb_goodsyntax: // llvm.hexa
gon.S2.tableidxb.goodsyntax
case Intrinsic::hexagon_S2_tableidxd_goodsyntax: // llvm.hexa
gon.S2.tableidxd.goodsyntax
case Intrinsic::hexagon_S2_tableidxh_goodsyntax: // llvm.hexa
gon.S2.tableidxh.goodsyntax
case Intrinsic::hexagon_S2_tableidxw_goodsyntax: // llvm.hexa
gon.S2.tableidxw.goodsyntax
ResultTy = IntegerType::get(Context, 32);
ArgTys.push_back(IntegerType::get(Context, 32));
ArgTys.push_back(IntegerType::get(Context, 32));
ArgTys.push_back(IntegerType::get(Context, 32));
ArgTys.push_back(IntegerType::get(Context, 32));
break;
case Intrinsic::arm_mrc: // llvm.arm.mrc
case Intrinsic::arm_mrc2: // llvm.arm.mrc2
ResultTy = IntegerType::get(Context, 32);
ArgTys.push_back(IntegerType::get(Context, 32));
ArgTys.push_back(IntegerType::get(Context, 32));
ArgTys.push_back(IntegerType::get(Context, 32));
ArgTys.push_back(IntegerType::get(Context, 32));
ArgTys.push_back(IntegerType::get(Context, 32));
break;
case Intrinsic::hexagon_S2_insert_rp: // llvm.hexagon.S2.i
nsert.rp
ResultTy = IntegerType::get(Context, 32);
ArgTys.push_back(IntegerType::get(Context, 32));
ArgTys.push_back(IntegerType::get(Context, 32));
ArgTys.push_back(IntegerType::get(Context, 64));
break;
case Intrinsic::arm_strexd: // llvm.arm.strexd
ResultTy = IntegerType::get(Context, 32);
ArgTys.push_back(IntegerType::get(Context, 32));
ArgTys.push_back(IntegerType::get(Context, 32));
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
break;
case Intrinsic::hexagon_S2_extractu_rp: // llvm.hexagon.S2.e
xtractu.rp
ResultTy = IntegerType::get(Context, 32);
ArgTys.push_back(IntegerType::get(Context, 32));
ArgTys.push_back(IntegerType::get(Context, 64));
break;
case Intrinsic::x86_sse42_crc32_32_8: // llvm.x86.sse42.cr
c32.32.8
ResultTy = IntegerType::get(Context, 32);
ArgTys.push_back(IntegerType::get(Context, 32));
ArgTys.push_back(IntegerType::get(Context, 8));
break;
case Intrinsic::ppc_altivec_vcmpequb_p: // llvm.ppc.altivec.
vcmpequb.p
case Intrinsic::ppc_altivec_vcmpgtsb_p: // llvm.ppc.altivec.
vcmpgtsb.p
case Intrinsic::ppc_altivec_vcmpgtub_p: // llvm.ppc.altivec.
vcmpgtub.p
ResultTy = IntegerType::get(Context, 32);
ArgTys.push_back(IntegerType::get(Context, 32));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
break;
case Intrinsic::ppc_altivec_vcmpbfp_p: // llvm.ppc.altivec.
vcmpbfp.p
case Intrinsic::ppc_altivec_vcmpeqfp_p: // llvm.ppc.altivec.
vcmpeqfp.p
case Intrinsic::ppc_altivec_vcmpgefp_p: // llvm.ppc.altivec.
vcmpgefp.p
case Intrinsic::ppc_altivec_vcmpgtfp_p: // llvm.ppc.altivec.
vcmpgtfp.p
ResultTy = IntegerType::get(Context, 32);
ArgTys.push_back(IntegerType::get(Context, 32));
ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
break;
case Intrinsic::ppc_altivec_vcmpequw_p: // llvm.ppc.altivec.
vcmpequw.p
case Intrinsic::ppc_altivec_vcmpgtsw_p: // llvm.ppc.altivec.
vcmpgtsw.p
case Intrinsic::ppc_altivec_vcmpgtuw_p: // llvm.ppc.altivec.
vcmpgtuw.p
ResultTy = IntegerType::get(Context, 32);
ArgTys.push_back(IntegerType::get(Context, 32));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
break;
case Intrinsic::ppc_altivec_vcmpequh_p: // llvm.ppc.altivec.
vcmpequh.p
case Intrinsic::ppc_altivec_vcmpgtsh_p: // llvm.ppc.altivec.
vcmpgtsh.p
case Intrinsic::ppc_altivec_vcmpgtuh_p: // llvm.ppc.altivec.
vcmpgtuh.p
ResultTy = IntegerType::get(Context, 32);
ArgTys.push_back(IntegerType::get(Context, 32));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
break;
case Intrinsic::hexagon_A2_sat: // llvm.hexagon.A2.sat
case Intrinsic::hexagon_S2_cl0p: // llvm.hexagon.S2.cl0p
case Intrinsic::hexagon_S2_cl1p: // llvm.hexagon.S2.cl1p
case Intrinsic::hexagon_S2_clbp: // llvm.hexagon.S2.clbp
case Intrinsic::hexagon_S2_vrndpackwh: // llvm.hexagon.S2.v
rndpackwh
case Intrinsic::hexagon_S2_vrndpackwhs: // llvm.hexagon.S2.v
rndpackwhs
case Intrinsic::hexagon_S2_vsathb: // llvm.hexagon.S2.vsathb
case Intrinsic::hexagon_S2_vsathub: // llvm.hexagon.S2.vsathub
case Intrinsic::hexagon_S2_vsatwh: // llvm.hexagon.S2.vsatwh
case Intrinsic::hexagon_S2_vsatwuh: // llvm.hexagon.S2.vsatwuh
case Intrinsic::hexagon_S2_vtrunehb: // llvm.hexagon.S2.vtrunehb
case Intrinsic::hexagon_S2_vtrunohb: // llvm.hexagon.S2.vtrunohb
ResultTy = IntegerType::get(Context, 32);
ArgTys.push_back(IntegerType::get(Context, 64));
break;
case Intrinsic::hexagon_M2_vrcmpys_s1rp: // llvm.hexagon.M2.v
rcmpys.s1rp
case Intrinsic::hexagon_S2_asr_i_svw_trun: // llvm.hexagon.S2.a
sr.i.svw.trun
case Intrinsic::hexagon_S2_asr_r_svw_trun: // llvm.hexagon.S2.a
sr.r.svw.trun
ResultTy = IntegerType::get(Context, 32);
ArgTys.push_back(IntegerType::get(Context, 64));
ArgTys.push_back(IntegerType::get(Context, 32));
break;
case Intrinsic::hexagon_M2_vdmpyrs_s0: // llvm.hexagon.M2.v
dmpyrs.s0
case Intrinsic::hexagon_M2_vdmpyrs_s1: // llvm.hexagon.M2.v
dmpyrs.s1
case Intrinsic::hexagon_M2_vradduh: // llvm.hexagon.M2.vradduh
case Intrinsic::hexagon_S2_parityp: // llvm.hexagon.S2.parityp
ResultTy = IntegerType::get(Context, 32);
ArgTys.push_back(IntegerType::get(Context, 64));
ArgTys.push_back(IntegerType::get(Context, 64));
break;
case Intrinsic::eh_sjlj_setjmp: // llvm.eh.sjlj.setjmp
case Intrinsic::eh_typeid_for: // llvm.eh.typeid.for
case Intrinsic::setjmp: // llvm.setjmp
ResultTy = IntegerType::get(Context, 32);
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
break;
case Intrinsic::sigsetjmp: // llvm.sigsetjmp
ResultTy = IntegerType::get(Context, 32);
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
ArgTys.push_back(IntegerType::get(Context, 32));
break;
case Intrinsic::x86_sse2_pmovmskb_128: // llvm.x86.sse2.pmo
vmskb.128
ResultTy = IntegerType::get(Context, 32);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
break;
case Intrinsic::x86_sse41_pextrb: // llvm.x86.sse41.pextrb
ResultTy = IntegerType::get(Context, 32);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
ArgTys.push_back(IntegerType::get(Context, 32));
break;
case Intrinsic::x86_sse42_pcmpestri128: // llvm.x86.sse42.pc
mpestri128
case Intrinsic::x86_sse42_pcmpestria128: // llvm.x86.sse42.pc
mpestria128
case Intrinsic::x86_sse42_pcmpestric128: // llvm.x86.sse42.pc
mpestric128
case Intrinsic::x86_sse42_pcmpestrio128: // llvm.x86.sse42.pc
mpestrio128
case Intrinsic::x86_sse42_pcmpestris128: // llvm.x86.sse42.pc
mpestris128
case Intrinsic::x86_sse42_pcmpestriz128: // llvm.x86.sse42.pc
mpestriz128
ResultTy = IntegerType::get(Context, 32);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
ArgTys.push_back(IntegerType::get(Context, 32));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
ArgTys.push_back(IntegerType::get(Context, 32));
ArgTys.push_back(IntegerType::get(Context, 8));
break;
case Intrinsic::x86_sse42_pcmpistri128: // llvm.x86.sse42.pc
mpistri128
case Intrinsic::x86_sse42_pcmpistria128: // llvm.x86.sse42.pc
mpistria128
case Intrinsic::x86_sse42_pcmpistric128: // llvm.x86.sse42.pc
mpistric128
case Intrinsic::x86_sse42_pcmpistrio128: // llvm.x86.sse42.pc
mpistrio128
case Intrinsic::x86_sse42_pcmpistris128: // llvm.x86.sse42.pc
mpistris128
case Intrinsic::x86_sse42_pcmpistriz128: // llvm.x86.sse42.pc
mpistriz128
ResultTy = IntegerType::get(Context, 32);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
ArgTys.push_back(IntegerType::get(Context, 8));
break;
case Intrinsic::x86_sse2_cvtsd2si: // llvm.x86.sse2.cvtsd2si
case Intrinsic::x86_sse2_cvttsd2si: // llvm.x86.sse2.cvttsd2si
case Intrinsic::x86_sse2_movmsk_pd: // llvm.x86.sse2.movmsk.pd
ResultTy = IntegerType::get(Context, 32);
ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
break;
case Intrinsic::x86_avx_vtestc_pd: // llvm.x86.avx.vtestc.pd
case Intrinsic::x86_avx_vtestnzc_pd: // llvm.x86.avx.vtestnzc.pd
case Intrinsic::x86_avx_vtestz_pd: // llvm.x86.avx.vtestz.pd
case Intrinsic::x86_sse2_comieq_sd: // llvm.x86.sse2.comieq.sd
case Intrinsic::x86_sse2_comige_sd: // llvm.x86.sse2.comige.sd
case Intrinsic::x86_sse2_comigt_sd: // llvm.x86.sse2.comigt.sd
case Intrinsic::x86_sse2_comile_sd: // llvm.x86.sse2.comile.sd
case Intrinsic::x86_sse2_comilt_sd: // llvm.x86.sse2.comilt.sd
case Intrinsic::x86_sse2_comineq_sd: // llvm.x86.sse2.comineq.sd
case Intrinsic::x86_sse2_ucomieq_sd: // llvm.x86.sse2.ucomieq.sd
case Intrinsic::x86_sse2_ucomige_sd: // llvm.x86.sse2.ucomige.sd
case Intrinsic::x86_sse2_ucomigt_sd: // llvm.x86.sse2.ucomigt.sd
case Intrinsic::x86_sse2_ucomile_sd: // llvm.x86.sse2.ucomile.sd
case Intrinsic::x86_sse2_ucomilt_sd: // llvm.x86.sse2.ucomilt.sd
case Intrinsic::x86_sse2_ucomineq_sd: // llvm.x86.sse2.uco
mineq.sd
ResultTy = IntegerType::get(Context, 32);
ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
break;
case Intrinsic::x86_sse41_ptestc: // llvm.x86.sse41.ptestc
case Intrinsic::x86_sse41_ptestnzc: // llvm.x86.sse41.ptestnzc
case Intrinsic::x86_sse41_ptestz: // llvm.x86.sse41.ptestz
ResultTy = IntegerType::get(Context, 32);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 2));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 2));
break;
case Intrinsic::x86_avx2_pmovmskb: // llvm.x86.avx2.pmovmskb
ResultTy = IntegerType::get(Context, 32);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 32));
break;
case Intrinsic::x86_sse_cvtss2si: // llvm.x86.sse.cvtss2si
case Intrinsic::x86_sse_cvttss2si: // llvm.x86.sse.cvttss2si
case Intrinsic::x86_sse_movmsk_ps: // llvm.x86.sse.movmsk.ps
ResultTy = IntegerType::get(Context, 32);
ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
break;
case Intrinsic::x86_sse41_extractps: // llvm.x86.sse41.extractps
ResultTy = IntegerType::get(Context, 32);
ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
ArgTys.push_back(IntegerType::get(Context, 32));
break;
case Intrinsic::x86_avx_vtestc_ps: // llvm.x86.avx.vtestc.ps
case Intrinsic::x86_avx_vtestnzc_ps: // llvm.x86.avx.vtestnzc.ps
case Intrinsic::x86_avx_vtestz_ps: // llvm.x86.avx.vtestz.ps
case Intrinsic::x86_sse_comieq_ss: // llvm.x86.sse.comieq.ss
case Intrinsic::x86_sse_comige_ss: // llvm.x86.sse.comige.ss
case Intrinsic::x86_sse_comigt_ss: // llvm.x86.sse.comigt.ss
case Intrinsic::x86_sse_comile_ss: // llvm.x86.sse.comile.ss
case Intrinsic::x86_sse_comilt_ss: // llvm.x86.sse.comilt.ss
case Intrinsic::x86_sse_comineq_ss: // llvm.x86.sse.comineq.ss
case Intrinsic::x86_sse_ucomieq_ss: // llvm.x86.sse.ucomieq.ss
case Intrinsic::x86_sse_ucomige_ss: // llvm.x86.sse.ucomige.ss
case Intrinsic::x86_sse_ucomigt_ss: // llvm.x86.sse.ucomigt.ss
case Intrinsic::x86_sse_ucomile_ss: // llvm.x86.sse.ucomile.ss
case Intrinsic::x86_sse_ucomilt_ss: // llvm.x86.sse.ucomilt.ss
case Intrinsic::x86_sse_ucomineq_ss: // llvm.x86.sse.ucomineq.ss
ResultTy = IntegerType::get(Context, 32);
ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
break;
case Intrinsic::x86_avx_movmsk_pd_256: // llvm.x86.avx.movm
sk.pd.256
ResultTy = IntegerType::get(Context, 32);
ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 4));
break;
case Intrinsic::x86_avx_vtestc_pd_256: // llvm.x86.avx.vtes
tc.pd.256
case Intrinsic::x86_avx_vtestnzc_pd_256: // llvm.x86.avx.vtes
tnzc.pd.256
case Intrinsic::x86_avx_vtestz_pd_256: // llvm.x86.avx.vtes
tz.pd.256
ResultTy = IntegerType::get(Context, 32);
ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 4));
ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 4));
break;
case Intrinsic::x86_sse41_pextrd: // llvm.x86.sse41.pextrd
ResultTy = IntegerType::get(Context, 32);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
ArgTys.push_back(IntegerType::get(Context, 32));
break;
case Intrinsic::x86_avx_ptestc_256: // llvm.x86.avx.ptestc.256
case Intrinsic::x86_avx_ptestnzc_256: // llvm.x86.avx.ptes
tnzc.256
case Intrinsic::x86_avx_ptestz_256: // llvm.x86.avx.ptestz.256
ResultTy = IntegerType::get(Context, 32);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 4));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 4));
break;
case Intrinsic::x86_avx_movmsk_ps_256: // llvm.x86.avx.movm
sk.ps.256
ResultTy = IntegerType::get(Context, 32);
ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 8));
break;
case Intrinsic::x86_avx_vtestc_ps_256: // llvm.x86.avx.vtes
tc.ps.256
case Intrinsic::x86_avx_vtestnzc_ps_256: // llvm.x86.avx.vtes
tnzc.ps.256
case Intrinsic::x86_avx_vtestz_ps_256: // llvm.x86.avx.vtes
tz.ps.256
ResultTy = IntegerType::get(Context, 32);
ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 8));
ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 8));
break;
case Intrinsic::x86_mmx_pmovmskb: // llvm.x86.mmx.pmovmskb
ResultTy = IntegerType::get(Context, 32);
ArgTys.push_back(Type::getX86_MMXTy(Context));
break;
case Intrinsic::x86_mmx_pextr_w: // llvm.x86.mmx.pextr.w
ResultTy = IntegerType::get(Context, 32);
ArgTys.push_back(Type::getX86_MMXTy(Context));
ArgTys.push_back(IntegerType::get(Context, 32));
break;
case Intrinsic::xcore_crc8: // llvm.xcore.crc8
ResultTy = StructType::get(IntegerType::get(Context, 32), IntegerType::
get(Context, 32), NULL);
ArgTys.push_back(IntegerType::get(Context, 32));
ArgTys.push_back(IntegerType::get(Context, 32));
ArgTys.push_back(IntegerType::get(Context, 32));
break;
case Intrinsic::arm_ldrexd: // llvm.arm.ldrexd
ResultTy = StructType::get(IntegerType::get(Context, 32), IntegerType::
get(Context, 32), NULL);
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
break;
case Intrinsic::ptx_read_clock64: // llvm.ptx.read.clock64
case Intrinsic::readcyclecounter: // llvm.readcyclecounter
case Intrinsic::x86_rdfsbase_64: // llvm.x86.rdfsbase.64
case Intrinsic::x86_rdgsbase_64: // llvm.x86.rdgsbase.64
ResultTy = IntegerType::get(Context, 64);
break;
case Intrinsic::hexagon_A2_sxtw: // llvm.hexagon.A2.sxtw
case Intrinsic::hexagon_A2_tfrpi: // llvm.hexagon.A2.tfrpi
case Intrinsic::hexagon_C2_mask: // llvm.hexagon.C2.mask
case Intrinsic::hexagon_S2_vsplatrh: // llvm.hexagon.S2.vsplatrh
case Intrinsic::hexagon_S2_vsxtbh: // llvm.hexagon.S2.vsxtbh
case Intrinsic::hexagon_S2_vsxthw: // llvm.hexagon.S2.vsxthw
case Intrinsic::hexagon_S2_vzxtbh: // llvm.hexagon.S2.vzxtbh
case Intrinsic::hexagon_S2_vzxthw: // llvm.hexagon.S2.vzxthw
ResultTy = IntegerType::get(Context, 64);
ArgTys.push_back(IntegerType::get(Context, 32));
break;
case Intrinsic::hexagon_A2_combineii: // llvm.hexagon.A2.c
ombineii
case Intrinsic::hexagon_A2_combinew: // llvm.hexagon.A2.combinew
case Intrinsic::hexagon_A4_combineir: // llvm.hexagon.A4.c
ombineir
case Intrinsic::hexagon_A4_combineri: // llvm.hexagon.A4.c
ombineri
case Intrinsic::hexagon_M2_cmpyi_s0: // llvm.hexagon.M2.cmpyi.s0
case Intrinsic::hexagon_M2_cmpyr_s0: // llvm.hexagon.M2.cmpyr.s0
case Intrinsic::hexagon_M2_cmpys_s0: // llvm.hexagon.M2.cmpys.s0
case Intrinsic::hexagon_M2_cmpys_s1: // llvm.hexagon.M2.cmpys.s1
case Intrinsic::hexagon_M2_cmpysc_s0: // llvm.hexagon.M2.c
mpysc.s0
case Intrinsic::hexagon_M2_cmpysc_s1: // llvm.hexagon.M2.c
mpysc.s1
case Intrinsic::hexagon_M2_dpmpyss_s0: // llvm.hexagon.M2.d
pmpyss.s0
case Intrinsic::hexagon_M2_dpmpyuu_s0: // llvm.hexagon.M2.d
pmpyuu.s0
case Intrinsic::hexagon_M2_mpyd_hh_s0: // llvm.hexagon.M2.m
pyd.hh.s0
case Intrinsic::hexagon_M2_mpyd_hh_s1: // llvm.hexagon.M2.m
pyd.hh.s1
case Intrinsic::hexagon_M2_mpyd_hl_s0: // llvm.hexagon.M2.m
pyd.hl.s0
case Intrinsic::hexagon_M2_mpyd_hl_s1: // llvm.hexagon.M2.m
pyd.hl.s1
case Intrinsic::hexagon_M2_mpyd_lh_s0: // llvm.hexagon.M2.m
pyd.lh.s0
case Intrinsic::hexagon_M2_mpyd_lh_s1: // llvm.hexagon.M2.m
pyd.lh.s1
case Intrinsic::hexagon_M2_mpyd_ll_s0: // llvm.hexagon.M2.m
pyd.ll.s0
case Intrinsic::hexagon_M2_mpyd_ll_s1: // llvm.hexagon.M2.m
pyd.ll.s1
case Intrinsic::hexagon_M2_mpyd_rnd_hh_s0: // llvm.hexagon.M2.m
pyd.rnd.hh.s0
case Intrinsic::hexagon_M2_mpyd_rnd_hh_s1: // llvm.hexagon.M2.m
pyd.rnd.hh.s1
case Intrinsic::hexagon_M2_mpyd_rnd_hl_s0: // llvm.hexagon.M2.m
pyd.rnd.hl.s0
case Intrinsic::hexagon_M2_mpyd_rnd_hl_s1: // llvm.hexagon.M2.m
pyd.rnd.hl.s1
case Intrinsic::hexagon_M2_mpyd_rnd_lh_s0: // llvm.hexagon.M2.m
pyd.rnd.lh.s0
case Intrinsic::hexagon_M2_mpyd_rnd_lh_s1: // llvm.hexagon.M2.m
pyd.rnd.lh.s1
case Intrinsic::hexagon_M2_mpyd_rnd_ll_s0: // llvm.hexagon.M2.m
pyd.rnd.ll.s0
case Intrinsic::hexagon_M2_mpyd_rnd_ll_s1: // llvm.hexagon.M2.m
pyd.rnd.ll.s1
case Intrinsic::hexagon_M2_mpyud_hh_s0: // llvm.hexagon.M2.m
pyud.hh.s0
case Intrinsic::hexagon_M2_mpyud_hh_s1: // llvm.hexagon.M2.m
pyud.hh.s1
case Intrinsic::hexagon_M2_mpyud_hl_s0: // llvm.hexagon.M2.m
pyud.hl.s0
case Intrinsic::hexagon_M2_mpyud_hl_s1: // llvm.hexagon.M2.m
pyud.hl.s1
case Intrinsic::hexagon_M2_mpyud_lh_s0: // llvm.hexagon.M2.m
pyud.lh.s0
case Intrinsic::hexagon_M2_mpyud_lh_s1: // llvm.hexagon.M2.m
pyud.lh.s1
case Intrinsic::hexagon_M2_mpyud_ll_s0: // llvm.hexagon.M2.m
pyud.ll.s0
case Intrinsic::hexagon_M2_mpyud_ll_s1: // llvm.hexagon.M2.m
pyud.ll.s1
case Intrinsic::hexagon_M2_vmpy2s_s0: // llvm.hexagon.M2.v
mpy2s.s0
case Intrinsic::hexagon_M2_vmpy2s_s1: // llvm.hexagon.M2.v
mpy2s.s1
case Intrinsic::hexagon_S2_packhl: // llvm.hexagon.S2.packhl
ResultTy = IntegerType::get(Context, 64);
ArgTys.push_back(IntegerType::get(Context, 32));
ArgTys.push_back(IntegerType::get(Context, 32));
break;
case Intrinsic::hexagon_A2_addsp: // llvm.hexagon.A2.addsp
ResultTy = IntegerType::get(Context, 64);
ArgTys.push_back(IntegerType::get(Context, 32));
ArgTys.push_back(IntegerType::get(Context, 64));
break;
case Intrinsic::hexagon_C2_vmux: // llvm.hexagon.C2.vmux
ResultTy = IntegerType::get(Context, 64);
ArgTys.push_back(IntegerType::get(Context, 32));
ArgTys.push_back(IntegerType::get(Context, 64));
ArgTys.push_back(IntegerType::get(Context, 64));
break;
case Intrinsic::hexagon_A2_absp: // llvm.hexagon.A2.absp
case Intrinsic::hexagon_A2_negp: // llvm.hexagon.A2.negp
case Intrinsic::hexagon_A2_notp: // llvm.hexagon.A2.notp
case Intrinsic::hexagon_A2_tfrp: // llvm.hexagon.A2.tfrp
case Intrinsic::hexagon_A2_vabsh: // llvm.hexagon.A2.vabsh
case Intrinsic::hexagon_A2_vabshsat: // llvm.hexagon.A2.vabshsat
case Intrinsic::hexagon_A2_vabsw: // llvm.hexagon.A2.vabsw
case Intrinsic::hexagon_A2_vabswsat: // llvm.hexagon.A2.vabswsat
case Intrinsic::hexagon_A2_vconj: // llvm.hexagon.A2.vconj
case Intrinsic::hexagon_S2_deinterleave: // llvm.hexagon.S2.d
einterleave
case Intrinsic::hexagon_S2_interleave: // llvm.hexagon.S2.i
nterleave
case Intrinsic::hexagon_S2_vsathb_nopack: // llvm.hexagon.S2.v
sathb.nopack
case Intrinsic::hexagon_S2_vsathub_nopack: // llvm.hexagon.S2.v
sathub.nopack
case Intrinsic::hexagon_S2_vsatwh_nopack: // llvm.hexagon.S2.v
satwh.nopack
case Intrinsic::hexagon_S2_vsatwuh_nopack: // llvm.hexagon.S2.v
satwuh.nopack
ResultTy = IntegerType::get(Context, 64);
ArgTys.push_back(IntegerType::get(Context, 64));
break;
case Intrinsic::hexagon_M2_vrcmpys_s1: // llvm.hexagon.M2.v
rcmpys.s1
case Intrinsic::hexagon_S2_asl_i_p: // llvm.hexagon.S2.asl.i.p
case Intrinsic::hexagon_S2_asl_i_vh: // llvm.hexagon.S2.asl.i.vh
case Intrinsic::hexagon_S2_asl_i_vw: // llvm.hexagon.S2.asl.i.vw
case Intrinsic::hexagon_S2_asl_r_p: // llvm.hexagon.S2.asl.r.p
case Intrinsic::hexagon_S2_asl_r_vh: // llvm.hexagon.S2.asl.r.vh
case Intrinsic::hexagon_S2_asl_r_vw: // llvm.hexagon.S2.asl.r.vw
case Intrinsic::hexagon_S2_asr_i_p: // llvm.hexagon.S2.asr.i.p
case Intrinsic::hexagon_S2_asr_i_vh: // llvm.hexagon.S2.asr.i.vh
case Intrinsic::hexagon_S2_asr_i_vw: // llvm.hexagon.S2.asr.i.vw
case Intrinsic::hexagon_S2_asr_r_p: // llvm.hexagon.S2.asr.r.p
case Intrinsic::hexagon_S2_asr_r_vh: // llvm.hexagon.S2.asr.r.vh
case Intrinsic::hexagon_S2_asr_r_vw: // llvm.hexagon.S2.asr.r.vw
case Intrinsic::hexagon_S2_lsl_r_p: // llvm.hexagon.S2.lsl.r.p
case Intrinsic::hexagon_S2_lsl_r_vh: // llvm.hexagon.S2.lsl.r.vh
case Intrinsic::hexagon_S2_lsl_r_vw: // llvm.hexagon.S2.lsl.r.vw
case Intrinsic::hexagon_S2_lsr_i_p: // llvm.hexagon.S2.lsr.i.p
case Intrinsic::hexagon_S2_lsr_i_vh: // llvm.hexagon.S2.lsr.i.vh
case Intrinsic::hexagon_S2_lsr_i_vw: // llvm.hexagon.S2.lsr.i.vw
case Intrinsic::hexagon_S2_lsr_r_p: // llvm.hexagon.S2.lsr.r.p
case Intrinsic::hexagon_S2_lsr_r_vh: // llvm.hexagon.S2.lsr.r.vh
case Intrinsic::hexagon_S2_lsr_r_vw: // llvm.hexagon.S2.lsr.r.vw
case Intrinsic::hexagon_S2_vcrotate: // llvm.hexagon.S2.vcrotate
ResultTy = IntegerType::get(Context, 64);
ArgTys.push_back(IntegerType::get(Context, 64));
ArgTys.push_back(IntegerType::get(Context, 32));
break;
case Intrinsic::hexagon_M2_cmaci_s0: // llvm.hexagon.M2.cmaci.s0
case Intrinsic::hexagon_M2_cmacr_s0: // llvm.hexagon.M2.cmacr.s0
case Intrinsic::hexagon_M2_cmacs_s0: // llvm.hexagon.M2.cmacs.s0
case Intrinsic::hexagon_M2_cmacs_s1: // llvm.hexagon.M2.cmacs.s1
case Intrinsic::hexagon_M2_cmacsc_s0: // llvm.hexagon.M2.c
macsc.s0
case Intrinsic::hexagon_M2_cmacsc_s1: // llvm.hexagon.M2.c
macsc.s1
case Intrinsic::hexagon_M2_cnacs_s0: // llvm.hexagon.M2.cnacs.s0
case Intrinsic::hexagon_M2_cnacs_s1: // llvm.hexagon.M2.cnacs.s1
case Intrinsic::hexagon_M2_cnacsc_s0: // llvm.hexagon.M2.c
nacsc.s0
case Intrinsic::hexagon_M2_cnacsc_s1: // llvm.hexagon.M2.c
nacsc.s1
case Intrinsic::hexagon_M2_dpmpyss_acc_s0: // llvm.hexagon.M2.d
pmpyss.acc.s0
case Intrinsic::hexagon_M2_dpmpyss_nac_s0: // llvm.hexagon.M2.d
pmpyss.nac.s0
case Intrinsic::hexagon_M2_dpmpyuu_acc_s0: // llvm.hexagon.M2.d
pmpyuu.acc.s0
case Intrinsic::hexagon_M2_dpmpyuu_nac_s0: // llvm.hexagon.M2.d
pmpyuu.nac.s0
case Intrinsic::hexagon_M2_mpyd_acc_hh_s0: // llvm.hexagon.M2.m
pyd.acc.hh.s0
case Intrinsic::hexagon_M2_mpyd_acc_hh_s1: // llvm.hexagon.M2.m
pyd.acc.hh.s1
case Intrinsic::hexagon_M2_mpyd_acc_hl_s0: // llvm.hexagon.M2.m
pyd.acc.hl.s0
case Intrinsic::hexagon_M2_mpyd_acc_hl_s1: // llvm.hexagon.M2.m
pyd.acc.hl.s1
case Intrinsic::hexagon_M2_mpyd_acc_lh_s0: // llvm.hexagon.M2.m
pyd.acc.lh.s0
case Intrinsic::hexagon_M2_mpyd_acc_lh_s1: // llvm.hexagon.M2.m
pyd.acc.lh.s1
case Intrinsic::hexagon_M2_mpyd_acc_ll_s0: // llvm.hexagon.M2.m
pyd.acc.ll.s0
case Intrinsic::hexagon_M2_mpyd_acc_ll_s1: // llvm.hexagon.M2.m
pyd.acc.ll.s1
case Intrinsic::hexagon_M2_mpyd_nac_hh_s0: // llvm.hexagon.M2.m
pyd.nac.hh.s0
case Intrinsic::hexagon_M2_mpyd_nac_hh_s1: // llvm.hexagon.M2.m
pyd.nac.hh.s1
case Intrinsic::hexagon_M2_mpyd_nac_hl_s0: // llvm.hexagon.M2.m
pyd.nac.hl.s0
case Intrinsic::hexagon_M2_mpyd_nac_hl_s1: // llvm.hexagon.M2.m
pyd.nac.hl.s1
case Intrinsic::hexagon_M2_mpyd_nac_lh_s0: // llvm.hexagon.M2.m
pyd.nac.lh.s0
case Intrinsic::hexagon_M2_mpyd_nac_lh_s1: // llvm.hexagon.M2.m
pyd.nac.lh.s1
case Intrinsic::hexagon_M2_mpyd_nac_ll_s0: // llvm.hexagon.M2.m
pyd.nac.ll.s0
case Intrinsic::hexagon_M2_mpyd_nac_ll_s1: // llvm.hexagon.M2.m
pyd.nac.ll.s1
case Intrinsic::hexagon_M2_mpyud_acc_hh_s0: // llvm.hexagon.M2.m
pyud.acc.hh.s0
case Intrinsic::hexagon_M2_mpyud_acc_hh_s1: // llvm.hexagon.M2.m
pyud.acc.hh.s1
case Intrinsic::hexagon_M2_mpyud_acc_hl_s0: // llvm.hexagon.M2.m
pyud.acc.hl.s0
case Intrinsic::hexagon_M2_mpyud_acc_hl_s1: // llvm.hexagon.M2.m
pyud.acc.hl.s1
case Intrinsic::hexagon_M2_mpyud_acc_lh_s0: // llvm.hexagon.M2.m
pyud.acc.lh.s0
case Intrinsic::hexagon_M2_mpyud_acc_lh_s1: // llvm.hexagon.M2.m
pyud.acc.lh.s1
case Intrinsic::hexagon_M2_mpyud_acc_ll_s0: // llvm.hexagon.M2.m
pyud.acc.ll.s0
case Intrinsic::hexagon_M2_mpyud_acc_ll_s1: // llvm.hexagon.M2.m
pyud.acc.ll.s1
case Intrinsic::hexagon_M2_mpyud_nac_hh_s0: // llvm.hexagon.M2.m
pyud.nac.hh.s0
case Intrinsic::hexagon_M2_mpyud_nac_hh_s1: // llvm.hexagon.M2.m
pyud.nac.hh.s1
case Intrinsic::hexagon_M2_mpyud_nac_hl_s0: // llvm.hexagon.M2.m
pyud.nac.hl.s0
case Intrinsic::hexagon_M2_mpyud_nac_hl_s1: // llvm.hexagon.M2.m
pyud.nac.hl.s1
case Intrinsic::hexagon_M2_mpyud_nac_lh_s0: // llvm.hexagon.M2.m
pyud.nac.lh.s0
case Intrinsic::hexagon_M2_mpyud_nac_lh_s1: // llvm.hexagon.M2.m
pyud.nac.lh.s1
case Intrinsic::hexagon_M2_mpyud_nac_ll_s0: // llvm.hexagon.M2.m
pyud.nac.ll.s0
case Intrinsic::hexagon_M2_mpyud_nac_ll_s1: // llvm.hexagon.M2.m
pyud.nac.ll.s1
case Intrinsic::hexagon_M2_vmac2: // llvm.hexagon.M2.vmac2
case Intrinsic::hexagon_M2_vmac2s_s0: // llvm.hexagon.M2.v
mac2s.s0
case Intrinsic::hexagon_M2_vmac2s_s1: // llvm.hexagon.M2.v
mac2s.s1
case Intrinsic::hexagon_S2_extractup: // llvm.hexagon.S2.e
xtractup
ResultTy = IntegerType::get(Context, 64);
ArgTys.push_back(IntegerType::get(Context, 64));
ArgTys.push_back(IntegerType::get(Context, 32));
ArgTys.push_back(IntegerType::get(Context, 32));
break;
case Intrinsic::hexagon_A2_addp: // llvm.hexagon.A2.addp
case Intrinsic::hexagon_A2_addpsat: // llvm.hexagon.A2.addpsat
case Intrinsic::hexagon_A2_andp: // llvm.hexagon.A2.andp
case Intrinsic::hexagon_A2_maxp: // llvm.hexagon.A2.maxp
case Intrinsic::hexagon_A2_maxup: // llvm.hexagon.A2.maxup
case Intrinsic::hexagon_A2_minp: // llvm.hexagon.A2.minp
case Intrinsic::hexagon_A2_minup: // llvm.hexagon.A2.minup
case Intrinsic::hexagon_A2_orp: // llvm.hexagon.A2.orp
case Intrinsic::hexagon_A2_subp: // llvm.hexagon.A2.subp
case Intrinsic::hexagon_A2_vaddh: // llvm.hexagon.A2.vaddh
case Intrinsic::hexagon_A2_vaddhs: // llvm.hexagon.A2.vaddhs
case Intrinsic::hexagon_A2_vaddub: // llvm.hexagon.A2.vaddub
case Intrinsic::hexagon_A2_vaddubs: // llvm.hexagon.A2.vaddubs
case Intrinsic::hexagon_A2_vadduhs: // llvm.hexagon.A2.vadduhs
case Intrinsic::hexagon_A2_vaddw: // llvm.hexagon.A2.vaddw
case Intrinsic::hexagon_A2_vaddws: // llvm.hexagon.A2.vaddws
case Intrinsic::hexagon_A2_vavgh: // llvm.hexagon.A2.vavgh
case Intrinsic::hexagon_A2_vavghcr: // llvm.hexagon.A2.vavghcr
case Intrinsic::hexagon_A2_vavghr: // llvm.hexagon.A2.vavghr
case Intrinsic::hexagon_A2_vavgub: // llvm.hexagon.A2.vavgub
case Intrinsic::hexagon_A2_vavgubr: // llvm.hexagon.A2.vavgubr
case Intrinsic::hexagon_A2_vavguh: // llvm.hexagon.A2.vavguh
case Intrinsic::hexagon_A2_vavguhr: // llvm.hexagon.A2.vavguhr
case Intrinsic::hexagon_A2_vavguw: // llvm.hexagon.A2.vavguw
case Intrinsic::hexagon_A2_vavguwr: // llvm.hexagon.A2.vavguwr
case Intrinsic::hexagon_A2_vavgw: // llvm.hexagon.A2.vavgw
case Intrinsic::hexagon_A2_vavgwcr: // llvm.hexagon.A2.vavgwcr
case Intrinsic::hexagon_A2_vavgwr: // llvm.hexagon.A2.vavgwr
case Intrinsic::hexagon_A2_vmaxh: // llvm.hexagon.A2.vmaxh
case Intrinsic::hexagon_A2_vmaxub: // llvm.hexagon.A2.vmaxub
case Intrinsic::hexagon_A2_vmaxuh: // llvm.hexagon.A2.vmaxuh
case Intrinsic::hexagon_A2_vmaxuw: // llvm.hexagon.A2.vmaxuw
case Intrinsic::hexagon_A2_vmaxw: // llvm.hexagon.A2.vmaxw
case Intrinsic::hexagon_A2_vminh: // llvm.hexagon.A2.vminh
case Intrinsic::hexagon_A2_vminub: // llvm.hexagon.A2.vminub
case Intrinsic::hexagon_A2_vminuh: // llvm.hexagon.A2.vminuh
case Intrinsic::hexagon_A2_vminuw: // llvm.hexagon.A2.vminuw
case Intrinsic::hexagon_A2_vminw: // llvm.hexagon.A2.vminw
case Intrinsic::hexagon_A2_vnavgh: // llvm.hexagon.A2.vnavgh
case Intrinsic::hexagon_A2_vnavghcr: // llvm.hexagon.A2.vnavghcr
case Intrinsic::hexagon_A2_vnavghr: // llvm.hexagon.A2.vnavghr
case Intrinsic::hexagon_A2_vnavgw: // llvm.hexagon.A2.vnavgw
case Intrinsic::hexagon_A2_vnavgwcr: // llvm.hexagon.A2.vnavgwcr
case Intrinsic::hexagon_A2_vnavgwr: // llvm.hexagon.A2.vnavgwr
case Intrinsic::hexagon_A2_vraddub: // llvm.hexagon.A2.vraddub
case Intrinsic::hexagon_A2_vrsadub: // llvm.hexagon.A2.vrsadub
case Intrinsic::hexagon_A2_vsubh: // llvm.hexagon.A2.vsubh
case Intrinsic::hexagon_A2_vsubhs: // llvm.hexagon.A2.vsubhs
case Intrinsic::hexagon_A2_vsubub: // llvm.hexagon.A2.vsubub
case Intrinsic::hexagon_A2_vsububs: // llvm.hexagon.A2.vsububs
case Intrinsic::hexagon_A2_vsubuhs: // llvm.hexagon.A2.vsubuhs
case Intrinsic::hexagon_A2_vsubw: // llvm.hexagon.A2.vsubw
case Intrinsic::hexagon_A2_vsubws: // llvm.hexagon.A2.vsubws
case Intrinsic::hexagon_A2_xorp: // llvm.hexagon.A2.xorp
case Intrinsic::hexagon_A4_andnp: // llvm.hexagon.A4.andnp
case Intrinsic::hexagon_A4_ornp: // llvm.hexagon.A4.ornp
case Intrinsic::hexagon_M2_mmpyh_rs0: // llvm.hexagon.M2.m
mpyh.rs0
case Intrinsic::hexagon_M2_mmpyh_rs1: // llvm.hexagon.M2.m
mpyh.rs1
case Intrinsic::hexagon_M2_mmpyh_s0: // llvm.hexagon.M2.mmpyh.s0
case Intrinsic::hexagon_M2_mmpyh_s1: // llvm.hexagon.M2.mmpyh.s1
case Intrinsic::hexagon_M2_mmpyl_rs0: // llvm.hexagon.M2.m
mpyl.rs0
case Intrinsic::hexagon_M2_mmpyl_rs1: // llvm.hexagon.M2.m
mpyl.rs1
case Intrinsic::hexagon_M2_mmpyl_s0: // llvm.hexagon.M2.mmpyl.s0
case Intrinsic::hexagon_M2_mmpyl_s1: // llvm.hexagon.M2.mmpyl.s1
case Intrinsic::hexagon_M2_mmpyuh_rs0: // llvm.hexagon.M2.m
mpyuh.rs0
case Intrinsic::hexagon_M2_mmpyuh_rs1: // llvm.hexagon.M2.m
mpyuh.rs1
case Intrinsic::hexagon_M2_mmpyuh_s0: // llvm.hexagon.M2.m
mpyuh.s0
case Intrinsic::hexagon_M2_mmpyuh_s1: // llvm.hexagon.M2.m
mpyuh.s1
case Intrinsic::hexagon_M2_mmpyul_rs0: // llvm.hexagon.M2.m
mpyul.rs0
case Intrinsic::hexagon_M2_mmpyul_rs1: // llvm.hexagon.M2.m
mpyul.rs1
case Intrinsic::hexagon_M2_mmpyul_s0: // llvm.hexagon.M2.m
mpyul.s0
case Intrinsic::hexagon_M2_mmpyul_s1: // llvm.hexagon.M2.m
mpyul.s1
case Intrinsic::hexagon_M2_vabsdiffh: // llvm.hexagon.M2.v
absdiffh
case Intrinsic::hexagon_M2_vabsdiffw: // llvm.hexagon.M2.v
absdiffw
case Intrinsic::hexagon_M2_vcmpy_s0_sat_i: // llvm.hexagon.M2.v
cmpy.s0.sat.i
case Intrinsic::hexagon_M2_vcmpy_s0_sat_r: // llvm.hexagon.M2.v
cmpy.s0.sat.r
case Intrinsic::hexagon_M2_vcmpy_s1_sat_i: // llvm.hexagon.M2.v
cmpy.s1.sat.i
case Intrinsic::hexagon_M2_vcmpy_s1_sat_r: // llvm.hexagon.M2.v
cmpy.s1.sat.r
case Intrinsic::hexagon_M2_vdmpys_s0: // llvm.hexagon.M2.v
dmpys.s0
case Intrinsic::hexagon_M2_vdmpys_s1: // llvm.hexagon.M2.v
dmpys.s1
case Intrinsic::hexagon_M2_vmpy2es_s0: // llvm.hexagon.M2.v
mpy2es.s0
case Intrinsic::hexagon_M2_vmpy2es_s1: // llvm.hexagon.M2.v
mpy2es.s1
case Intrinsic::hexagon_M2_vrcmpyi_s0: // llvm.hexagon.M2.v
rcmpyi.s0
case Intrinsic::hexagon_M2_vrcmpyi_s0c: // llvm.hexagon.M2.v
rcmpyi.s0c
case Intrinsic::hexagon_M2_vrcmpyr_s0: // llvm.hexagon.M2.v
rcmpyr.s0
case Intrinsic::hexagon_M2_vrcmpyr_s0c: // llvm.hexagon.M2.v
rcmpyr.s0c
case Intrinsic::hexagon_M2_vrmpy_s0: // llvm.hexagon.M2.vrmpy.s0
case Intrinsic::hexagon_S2_extractup_rp: // llvm.hexagon.S2.e
xtractup.rp
case Intrinsic::hexagon_S2_lfsp: // llvm.hexagon.S2.lfsp
case Intrinsic::hexagon_S2_shuffeb: // llvm.hexagon.S2.shuffeb
case Intrinsic::hexagon_S2_shuffeh: // llvm.hexagon.S2.shuffeh
case Intrinsic::hexagon_S2_shuffob: // llvm.hexagon.S2.shuffob
case Intrinsic::hexagon_S2_shuffoh: // llvm.hexagon.S2.shuffoh
case Intrinsic::hexagon_S2_vtrunewh: // llvm.hexagon.S2.vtrunewh
case Intrinsic::hexagon_S2_vtrunowh: // llvm.hexagon.S2.vtrunowh
case Intrinsic::hexagon_S4_andnp: // llvm.hexagon.S4.andnp
case Intrinsic::hexagon_S4_ornp: // llvm.hexagon.S4.ornp
case Intrinsic::x86_bmi_bextr_64: // llvm.x86.bmi.bextr.64
case Intrinsic::x86_bmi_bzhi_64: // llvm.x86.bmi.bzhi.64
case Intrinsic::x86_bmi_pdep_64: // llvm.x86.bmi.pdep.64
case Intrinsic::x86_bmi_pext_64: // llvm.x86.bmi.pext.64
case Intrinsic::x86_sse42_crc32_64_64: // llvm.x86.sse42.cr
c32.64.64
ResultTy = IntegerType::get(Context, 64);
ArgTys.push_back(IntegerType::get(Context, 64));
ArgTys.push_back(IntegerType::get(Context, 64));
break;
case Intrinsic::hexagon_M2_vrcmpys_acc_s1: // llvm.hexagon.M2.v
rcmpys.acc.s1
case Intrinsic::hexagon_S2_asl_i_p_acc: // llvm.hexagon.S2.a
sl.i.p.acc
case Intrinsic::hexagon_S2_asl_i_p_and: // llvm.hexagon.S2.a
sl.i.p.and
case Intrinsic::hexagon_S2_asl_i_p_nac: // llvm.hexagon.S2.a
sl.i.p.nac
case Intrinsic::hexagon_S2_asl_i_p_or: // llvm.hexagon.S2.a
sl.i.p.or
case Intrinsic::hexagon_S2_asl_i_p_xacc: // llvm.hexagon.S2.a
sl.i.p.xacc
case Intrinsic::hexagon_S2_asl_r_p_acc: // llvm.hexagon.S2.a
sl.r.p.acc
case Intrinsic::hexagon_S2_asl_r_p_and: // llvm.hexagon.S2.a
sl.r.p.and
case Intrinsic::hexagon_S2_asl_r_p_nac: // llvm.hexagon.S2.a
sl.r.p.nac
case Intrinsic::hexagon_S2_asl_r_p_or: // llvm.hexagon.S2.a
sl.r.p.or
case Intrinsic::hexagon_S2_asr_i_p_acc: // llvm.hexagon.S2.a
sr.i.p.acc
case Intrinsic::hexagon_S2_asr_i_p_and: // llvm.hexagon.S2.a
sr.i.p.and
case Intrinsic::hexagon_S2_asr_i_p_nac: // llvm.hexagon.S2.a
sr.i.p.nac
case Intrinsic::hexagon_S2_asr_i_p_or: // llvm.hexagon.S2.a
sr.i.p.or
case Intrinsic::hexagon_S2_asr_r_p_acc: // llvm.hexagon.S2.a
sr.r.p.acc
case Intrinsic::hexagon_S2_asr_r_p_and: // llvm.hexagon.S2.a
sr.r.p.and
case Intrinsic::hexagon_S2_asr_r_p_nac: // llvm.hexagon.S2.a
sr.r.p.nac
case Intrinsic::hexagon_S2_asr_r_p_or: // llvm.hexagon.S2.a
sr.r.p.or
case Intrinsic::hexagon_S2_lsl_r_p_acc: // llvm.hexagon.S2.l
sl.r.p.acc
case Intrinsic::hexagon_S2_lsl_r_p_and: // llvm.hexagon.S2.l
sl.r.p.and
case Intrinsic::hexagon_S2_lsl_r_p_nac: // llvm.hexagon.S2.l
sl.r.p.nac
case Intrinsic::hexagon_S2_lsl_r_p_or: // llvm.hexagon.S2.l
sl.r.p.or
case Intrinsic::hexagon_S2_lsr_i_p_acc: // llvm.hexagon.S2.l
sr.i.p.acc
case Intrinsic::hexagon_S2_lsr_i_p_and: // llvm.hexagon.S2.l
sr.i.p.and
case Intrinsic::hexagon_S2_lsr_i_p_nac: // llvm.hexagon.S2.l
sr.i.p.nac
case Intrinsic::hexagon_S2_lsr_i_p_or: // llvm.hexagon.S2.l
sr.i.p.or
case Intrinsic::hexagon_S2_lsr_i_p_xacc: // llvm.hexagon.S2.l
sr.i.p.xacc
case Intrinsic::hexagon_S2_lsr_r_p_acc: // llvm.hexagon.S2.l
sr.r.p.acc
case Intrinsic::hexagon_S2_lsr_r_p_and: // llvm.hexagon.S2.l
sr.r.p.and
case Intrinsic::hexagon_S2_lsr_r_p_nac: // llvm.hexagon.S2.l
sr.r.p.nac
case Intrinsic::hexagon_S2_lsr_r_p_or: // llvm.hexagon.S2.l
sr.r.p.or
case Intrinsic::hexagon_S2_valignib: // llvm.hexagon.S2.valignib
case Intrinsic::hexagon_S2_valignrb: // llvm.hexagon.S2.valignrb
case Intrinsic::hexagon_S2_vspliceib: // llvm.hexagon.S2.v
spliceib
case Intrinsic::hexagon_S2_vsplicerb: // llvm.hexagon.S2.v
splicerb
ResultTy = IntegerType::get(Context, 64);
ArgTys.push_back(IntegerType::get(Context, 64));
ArgTys.push_back(IntegerType::get(Context, 64));
ArgTys.push_back(IntegerType::get(Context, 32));
break;
case Intrinsic::hexagon_S2_insertp: // llvm.hexagon.S2.insertp
ResultTy = IntegerType::get(Context, 64);
ArgTys.push_back(IntegerType::get(Context, 64));
ArgTys.push_back(IntegerType::get(Context, 64));
ArgTys.push_back(IntegerType::get(Context, 32));
ArgTys.push_back(IntegerType::get(Context, 32));
break;
case Intrinsic::hexagon_A2_vraddub_acc: // llvm.hexagon.A2.v
raddub.acc
case Intrinsic::hexagon_A2_vrsadub_acc: // llvm.hexagon.A2.v
rsadub.acc
case Intrinsic::hexagon_M2_mmachs_rs0: // llvm.hexagon.M2.m
machs.rs0
case Intrinsic::hexagon_M2_mmachs_rs1: // llvm.hexagon.M2.m
machs.rs1
case Intrinsic::hexagon_M2_mmachs_s0: // llvm.hexagon.M2.m
machs.s0
case Intrinsic::hexagon_M2_mmachs_s1: // llvm.hexagon.M2.m
machs.s1
case Intrinsic::hexagon_M2_mmacls_rs0: // llvm.hexagon.M2.m
macls.rs0
case Intrinsic::hexagon_M2_mmacls_rs1: // llvm.hexagon.M2.m
macls.rs1
case Intrinsic::hexagon_M2_mmacls_s0: // llvm.hexagon.M2.m
macls.s0
case Intrinsic::hexagon_M2_mmacls_s1: // llvm.hexagon.M2.m
macls.s1
case Intrinsic::hexagon_M2_mmacuhs_rs0: // llvm.hexagon.M2.m
macuhs.rs0
case Intrinsic::hexagon_M2_mmacuhs_rs1: // llvm.hexagon.M2.m
macuhs.rs1
case Intrinsic::hexagon_M2_mmacuhs_s0: // llvm.hexagon.M2.m
macuhs.s0
case Intrinsic::hexagon_M2_mmacuhs_s1: // llvm.hexagon.M2.m
macuhs.s1
case Intrinsic::hexagon_M2_mmaculs_rs0: // llvm.hexagon.M2.m
maculs.rs0
case Intrinsic::hexagon_M2_mmaculs_rs1: // llvm.hexagon.M2.m
maculs.rs1
case Intrinsic::hexagon_M2_mmaculs_s0: // llvm.hexagon.M2.m
maculs.s0
case Intrinsic::hexagon_M2_mmaculs_s1: // llvm.hexagon.M2.m
maculs.s1
case Intrinsic::hexagon_M2_vcmac_s0_sat_i: // llvm.hexagon.M2.v
cmac.s0.sat.i
case Intrinsic::hexagon_M2_vcmac_s0_sat_r: // llvm.hexagon.M2.v
cmac.s0.sat.r
case Intrinsic::hexagon_M2_vdmacs_s0: // llvm.hexagon.M2.v
dmacs.s0
case Intrinsic::hexagon_M2_vdmacs_s1: // llvm.hexagon.M2.v
dmacs.s1
case Intrinsic::hexagon_M2_vmac2es: // llvm.hexagon.M2.vmac2es
case Intrinsic::hexagon_M2_vmac2es_s0: // llvm.hexagon.M2.v
mac2es.s0
case Intrinsic::hexagon_M2_vmac2es_s1: // llvm.hexagon.M2.v
mac2es.s1
case Intrinsic::hexagon_M2_vrcmaci_s0: // llvm.hexagon.M2.v
rcmaci.s0
case Intrinsic::hexagon_M2_vrcmaci_s0c: // llvm.hexagon.M2.v
rcmaci.s0c
case Intrinsic::hexagon_M2_vrcmacr_s0: // llvm.hexagon.M2.v
rcmacr.s0
case Intrinsic::hexagon_M2_vrcmacr_s0c: // llvm.hexagon.M2.v
rcmacr.s0c
case Intrinsic::hexagon_M2_vrmac_s0: // llvm.hexagon.M2.vrmac.s0
case Intrinsic::hexagon_M4_xor_xacc: // llvm.hexagon.M4.xor.xacc
case Intrinsic::hexagon_S2_insertp_rp: // llvm.hexagon.S2.i
nsertp.rp
ResultTy = IntegerType::get(Context, 64);
ArgTys.push_back(IntegerType::get(Context, 64));
ArgTys.push_back(IntegerType::get(Context, 64));
ArgTys.push_back(IntegerType::get(Context, 64));
break;
case Intrinsic::x86_sse42_crc32_64_8: // llvm.x86.sse42.cr
c32.64.8
ResultTy = IntegerType::get(Context, 64);
ArgTys.push_back(IntegerType::get(Context, 64));
ArgTys.push_back(IntegerType::get(Context, 8));
break;
case Intrinsic::x86_sse2_cvtsd2si64: // llvm.x86.sse2.cvtsd2si64
case Intrinsic::x86_sse2_cvttsd2si64: // llvm.x86.sse2.cvt
tsd2si64
ResultTy = IntegerType::get(Context, 64);
ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
break;
case Intrinsic::x86_sse41_pextrq: // llvm.x86.sse41.pextrq
ResultTy = IntegerType::get(Context, 64);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 2));
ArgTys.push_back(IntegerType::get(Context, 32));
break;
case Intrinsic::x86_sse_cvtss2si64: // llvm.x86.sse.cvtss2si64
case Intrinsic::x86_sse_cvttss2si64: // llvm.x86.sse.cvttss2si64
ResultTy = IntegerType::get(Context, 64);
ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
break;
case Intrinsic::arm_thread_pointer: // llvm.arm.thread.pointer
case Intrinsic::eh_sjlj_lsda: // llvm.eh.sjlj.lsda
case Intrinsic::stacksave: // llvm.stacksave
case Intrinsic::xcore_waitevent: // llvm.xcore.waitevent
ResultTy = PointerType::getUnqual(IntegerType::get(Context, 8));
break;
case Intrinsic::eh_dwarf_cfa: // llvm.eh.dwarf.cfa
case Intrinsic::frameaddress: // llvm.frameaddress
case Intrinsic::returnaddress: // llvm.returnaddress
ResultTy = PointerType::getUnqual(IntegerType::get(Context, 8));
ArgTys.push_back(IntegerType::get(Context, 32));
break;
case Intrinsic::adjust_trampoline: // llvm.adjust.trampoline
case Intrinsic::xcore_checkevent: // llvm.xcore.checkevent
ResultTy = PointerType::getUnqual(IntegerType::get(Context, 8));
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
break;
case Intrinsic::gcread: // llvm.gcread
ResultTy = PointerType::getUnqual(IntegerType::get(Context, 8));
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
ArgTys.push_back(PointerType::getUnqual(PointerType::getUnqual(IntegerT
ype::get(Context, 8))));
break;
case Intrinsic::x86_avx2_pabs_w: // llvm.x86.avx2.pabs.w
ResultTy = VectorType::get(IntegerType::get(Context, 16), 16);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 16));
break;
case Intrinsic::x86_avx2_pslli_w: // llvm.x86.avx2.pslli.w
case Intrinsic::x86_avx2_psrai_w: // llvm.x86.avx2.psrai.w
case Intrinsic::x86_avx2_psrli_w: // llvm.x86.avx2.psrli.w
ResultTy = VectorType::get(IntegerType::get(Context, 16), 16);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 16));
ArgTys.push_back(IntegerType::get(Context, 32));
break;
case Intrinsic::x86_avx2_padds_w: // llvm.x86.avx2.padds.w
case Intrinsic::x86_avx2_paddus_w: // llvm.x86.avx2.paddus.w
case Intrinsic::x86_avx2_pavg_w: // llvm.x86.avx2.pavg.w
case Intrinsic::x86_avx2_phadd_sw: // llvm.x86.avx2.phadd.sw
case Intrinsic::x86_avx2_phadd_w: // llvm.x86.avx2.phadd.w
case Intrinsic::x86_avx2_phsub_sw: // llvm.x86.avx2.phsub.sw
case Intrinsic::x86_avx2_phsub_w: // llvm.x86.avx2.phsub.w
case Intrinsic::x86_avx2_pmaxs_w: // llvm.x86.avx2.pmaxs.w
case Intrinsic::x86_avx2_pmaxu_w: // llvm.x86.avx2.pmaxu.w
case Intrinsic::x86_avx2_pmins_w: // llvm.x86.avx2.pmins.w
case Intrinsic::x86_avx2_pminu_w: // llvm.x86.avx2.pminu.w
case Intrinsic::x86_avx2_pmul_hr_sw: // llvm.x86.avx2.pmul.hr.sw
case Intrinsic::x86_avx2_pmulh_w: // llvm.x86.avx2.pmulh.w
case Intrinsic::x86_avx2_pmulhu_w: // llvm.x86.avx2.pmulhu.w
case Intrinsic::x86_avx2_psign_w: // llvm.x86.avx2.psign.w
case Intrinsic::x86_avx2_psubs_w: // llvm.x86.avx2.psubs.w
case Intrinsic::x86_avx2_psubus_w: // llvm.x86.avx2.psubus.w
ResultTy = VectorType::get(IntegerType::get(Context, 16), 16);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 16));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 16));
break;
case Intrinsic::x86_avx2_pblendw: // llvm.x86.avx2.pblendw
ResultTy = VectorType::get(IntegerType::get(Context, 16), 16);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 16));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 16));
ArgTys.push_back(IntegerType::get(Context, 32));
break;
case Intrinsic::x86_avx2_psll_w: // llvm.x86.avx2.psll.w
case Intrinsic::x86_avx2_psra_w: // llvm.x86.avx2.psra.w
case Intrinsic::x86_avx2_psrl_w: // llvm.x86.avx2.psrl.w
ResultTy = VectorType::get(IntegerType::get(Context, 16), 16);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 16));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
break;
case Intrinsic::x86_avx2_pmovsxbw: // llvm.x86.avx2.pmovsxbw
case Intrinsic::x86_avx2_pmovzxbw: // llvm.x86.avx2.pmovzxbw
ResultTy = VectorType::get(IntegerType::get(Context, 16), 16);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
break;
case Intrinsic::x86_avx2_pmadd_ub_sw: // llvm.x86.avx2.pma
dd.ub.sw
ResultTy = VectorType::get(IntegerType::get(Context, 16), 16);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 32));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 32));
break;
case Intrinsic::x86_avx2_mpsadbw: // llvm.x86.avx2.mpsadbw
ResultTy = VectorType::get(IntegerType::get(Context, 16), 16);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 32));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 32));
ArgTys.push_back(IntegerType::get(Context, 32));
break;
case Intrinsic::x86_avx2_pbroadcastw_256: // llvm.x86.avx2.pbr
oadcastw.256
ResultTy = VectorType::get(IntegerType::get(Context, 16), 16);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
break;
case Intrinsic::x86_avx2_packssdw: // llvm.x86.avx2.packssdw
case Intrinsic::x86_avx2_packusdw: // llvm.x86.avx2.packusdw
ResultTy = VectorType::get(IntegerType::get(Context, 16), 16);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 8));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 8));
break;
case Intrinsic::ppc_altivec_lvebx: // llvm.ppc.altivec.lvebx
case Intrinsic::ppc_altivec_lvsl: // llvm.ppc.altivec.lvsl
case Intrinsic::ppc_altivec_lvsr: // llvm.ppc.altivec.lvsr
case Intrinsic::x86_sse3_ldu_dq: // llvm.x86.sse3.ldu.dq
ResultTy = VectorType::get(IntegerType::get(Context, 8), 16);
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
break;
case Intrinsic::x86_avx2_pbroadcastb_128: // llvm.x86.avx2.pbr
oadcastb.128
case Intrinsic::x86_ssse3_pabs_b_128: // llvm.x86.ssse3.pa
bs.b.128
ResultTy = VectorType::get(IntegerType::get(Context, 8), 16);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
break;
case Intrinsic::spu_si_shlqbii: // llvm.spu.si.shlqbii
case Intrinsic::spu_si_shlqbyi: // llvm.spu.si.shlqbyi
ResultTy = VectorType::get(IntegerType::get(Context, 8), 16);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
ArgTys.push_back(IntegerType::get(Context, 8));
break;
case Intrinsic::x86_sse42_pcmpestrm128: // llvm.x86.sse42.pc
mpestrm128
ResultTy = VectorType::get(IntegerType::get(Context, 8), 16);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
ArgTys.push_back(IntegerType::get(Context, 32));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
ArgTys.push_back(IntegerType::get(Context, 32));
ArgTys.push_back(IntegerType::get(Context, 8));
break;
case Intrinsic::spu_si_andbi: // llvm.spu.si.andbi
case Intrinsic::spu_si_ceqbi: // llvm.spu.si.ceqbi
case Intrinsic::spu_si_cgtbi: // llvm.spu.si.cgtbi
case Intrinsic::spu_si_clgtbi: // llvm.spu.si.clgtbi
case Intrinsic::spu_si_orbi: // llvm.spu.si.orbi
case Intrinsic::spu_si_xorbi: // llvm.spu.si.xorbi
ResultTy = VectorType::get(IntegerType::get(Context, 8), 16);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
ArgTys.push_back(IntegerType::get(Context, 8));
break;
case Intrinsic::ppc_altivec_vaddsbs: // llvm.ppc.altivec.vaddsbs
case Intrinsic::ppc_altivec_vaddubs: // llvm.ppc.altivec.vaddubs
case Intrinsic::ppc_altivec_vavgsb: // llvm.ppc.altivec.vavgsb
case Intrinsic::ppc_altivec_vavgub: // llvm.ppc.altivec.vavgub
case Intrinsic::ppc_altivec_vcmpequb: // llvm.ppc.altivec.
vcmpequb
case Intrinsic::ppc_altivec_vcmpgtsb: // llvm.ppc.altivec.
vcmpgtsb
case Intrinsic::ppc_altivec_vcmpgtub: // llvm.ppc.altivec.
vcmpgtub
case Intrinsic::ppc_altivec_vmaxsb: // llvm.ppc.altivec.vmaxsb
case Intrinsic::ppc_altivec_vmaxub: // llvm.ppc.altivec.vmaxub
case Intrinsic::ppc_altivec_vminsb: // llvm.ppc.altivec.vminsb
case Intrinsic::ppc_altivec_vminub: // llvm.ppc.altivec.vminub
case Intrinsic::ppc_altivec_vrlb: // llvm.ppc.altivec.vrlb
case Intrinsic::ppc_altivec_vslb: // llvm.ppc.altivec.vslb
case Intrinsic::ppc_altivec_vsrab: // llvm.ppc.altivec.vsrab
case Intrinsic::ppc_altivec_vsrb: // llvm.ppc.altivec.vsrb
case Intrinsic::ppc_altivec_vsubsbs: // llvm.ppc.altivec.vsubsbs
case Intrinsic::ppc_altivec_vsububs: // llvm.ppc.altivec.vsububs
case Intrinsic::spu_si_ceqb: // llvm.spu.si.ceqb
case Intrinsic::spu_si_cgtb: // llvm.spu.si.cgtb
case Intrinsic::spu_si_clgtb: // llvm.spu.si.clgtb
case Intrinsic::x86_sse2_padds_b: // llvm.x86.sse2.padds.b
case Intrinsic::x86_sse2_paddus_b: // llvm.x86.sse2.paddus.b
case Intrinsic::x86_sse2_pavg_b: // llvm.x86.sse2.pavg.b
case Intrinsic::x86_sse2_pmaxu_b: // llvm.x86.sse2.pmaxu.b
case Intrinsic::x86_sse2_pminu_b: // llvm.x86.sse2.pminu.b
case Intrinsic::x86_sse2_psubs_b: // llvm.x86.sse2.psubs.b
case Intrinsic::x86_sse2_psubus_b: // llvm.x86.sse2.psubus.b
case Intrinsic::x86_sse41_pmaxsb: // llvm.x86.sse41.pmaxsb
case Intrinsic::x86_sse41_pminsb: // llvm.x86.sse41.pminsb
case Intrinsic::x86_ssse3_pshuf_b_128: // llvm.x86.ssse3.ps
huf.b.128
case Intrinsic::x86_ssse3_psign_b_128: // llvm.x86.ssse3.ps
ign.b.128
case Intrinsic::x86_xop_vpcomeqb: // llvm.x86.xop.vpcomeqb
case Intrinsic::x86_xop_vpcomequb: // llvm.x86.xop.vpcomequb
case Intrinsic::x86_xop_vpcomfalseb: // llvm.x86.xop.vpcomfalseb
case Intrinsic::x86_xop_vpcomfalseub: // llvm.x86.xop.vpco
mfalseub
case Intrinsic::x86_xop_vpcomgeb: // llvm.x86.xop.vpcomgeb
case Intrinsic::x86_xop_vpcomgeub: // llvm.x86.xop.vpcomgeub
case Intrinsic::x86_xop_vpcomgtb: // llvm.x86.xop.vpcomgtb
case Intrinsic::x86_xop_vpcomgtub: // llvm.x86.xop.vpcomgtub
case Intrinsic::x86_xop_vpcomleb: // llvm.x86.xop.vpcomleb
case Intrinsic::x86_xop_vpcomleub: // llvm.x86.xop.vpcomleub
case Intrinsic::x86_xop_vpcomltb: // llvm.x86.xop.vpcomltb
case Intrinsic::x86_xop_vpcomltub: // llvm.x86.xop.vpcomltub
case Intrinsic::x86_xop_vpcomneb: // llvm.x86.xop.vpcomneb
case Intrinsic::x86_xop_vpcomneub: // llvm.x86.xop.vpcomneub
case Intrinsic::x86_xop_vpcomtrueb: // llvm.x86.xop.vpcomtrueb
case Intrinsic::x86_xop_vpcomtrueub: // llvm.x86.xop.vpcomtrueub
case Intrinsic::x86_xop_vprotb: // llvm.x86.xop.vprotb
case Intrinsic::x86_xop_vpshab: // llvm.x86.xop.vpshab
case Intrinsic::x86_xop_vpshlb: // llvm.x86.xop.vpshlb
ResultTy = VectorType::get(IntegerType::get(Context, 8), 16);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
break;
case Intrinsic::x86_sse42_pcmpistrm128: // llvm.x86.sse42.pc
mpistrm128
ResultTy = VectorType::get(IntegerType::get(Context, 8), 16);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
ArgTys.push_back(IntegerType::get(Context, 8));
break;
case Intrinsic::x86_sse41_pblendvb: // llvm.x86.sse41.pblendvb
case Intrinsic::x86_xop_vpperm: // llvm.x86.xop.vpperm
ResultTy = VectorType::get(IntegerType::get(Context, 8), 16);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
break;
case Intrinsic::ppc_altivec_vpkswss: // llvm.ppc.altivec.vpkswss
ResultTy = VectorType::get(IntegerType::get(Context, 8), 16);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
break;
case Intrinsic::ppc_altivec_vpkshss: // llvm.ppc.altivec.vpkshss
case Intrinsic::ppc_altivec_vpkshus: // llvm.ppc.altivec.vpkshus
case Intrinsic::ppc_altivec_vpkuhus: // llvm.ppc.altivec.vpkuhus
case Intrinsic::x86_sse2_packsswb_128: // llvm.x86.sse2.pac
ksswb.128
case Intrinsic::x86_sse2_packuswb_128: // llvm.x86.sse2.pac
kuswb.128
ResultTy = VectorType::get(IntegerType::get(Context, 8), 16);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
break;
case Intrinsic::x86_avx_maskload_pd: // llvm.x86.avx.maskload.pd
ResultTy = VectorType::get(Type::getDoubleTy(Context), 2);
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
break;
case Intrinsic::x86_sse2_sqrt_pd: // llvm.x86.sse2.sqrt.pd
case Intrinsic::x86_sse2_sqrt_sd: // llvm.x86.sse2.sqrt.sd
case Intrinsic::x86_xop_vfrcz_pd: // llvm.x86.xop.vfrcz.pd
ResultTy = VectorType::get(Type::getDoubleTy(Context), 2);
ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
break;
case Intrinsic::x86_sse2_cvtsi2sd: // llvm.x86.sse2.cvtsi2sd
case Intrinsic::x86_sse41_round_pd: // llvm.x86.sse41.round.pd
ResultTy = VectorType::get(Type::getDoubleTy(Context), 2);
ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
ArgTys.push_back(IntegerType::get(Context, 32));
break;
case Intrinsic::x86_sse2_cvtsi642sd: // llvm.x86.sse2.cvtsi642sd
ResultTy = VectorType::get(Type::getDoubleTy(Context), 2);
ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
ArgTys.push_back(IntegerType::get(Context, 64));
break;
case Intrinsic::spu_si_dfa: // llvm.spu.si.dfa
case Intrinsic::spu_si_dfm: // llvm.spu.si.dfm
case Intrinsic::spu_si_dfma: // llvm.spu.si.dfma
case Intrinsic::spu_si_dfms: // llvm.spu.si.dfms
case Intrinsic::spu_si_dfnma: // llvm.spu.si.dfnma
case Intrinsic::spu_si_dfnms: // llvm.spu.si.dfnms
case Intrinsic::spu_si_dfs: // llvm.spu.si.dfs
case Intrinsic::x86_sse2_add_sd: // llvm.x86.sse2.add.sd
case Intrinsic::x86_sse2_div_sd: // llvm.x86.sse2.div.sd
case Intrinsic::x86_sse2_max_pd: // llvm.x86.sse2.max.pd
case Intrinsic::x86_sse2_max_sd: // llvm.x86.sse2.max.sd
case Intrinsic::x86_sse2_min_pd: // llvm.x86.sse2.min.pd
case Intrinsic::x86_sse2_min_sd: // llvm.x86.sse2.min.sd
case Intrinsic::x86_sse2_mul_sd: // llvm.x86.sse2.mul.sd
case Intrinsic::x86_sse2_sub_sd: // llvm.x86.sse2.sub.sd
case Intrinsic::x86_sse3_addsub_pd: // llvm.x86.sse3.addsub.pd
case Intrinsic::x86_sse3_hadd_pd: // llvm.x86.sse3.hadd.pd
case Intrinsic::x86_sse3_hsub_pd: // llvm.x86.sse3.hsub.pd
case Intrinsic::x86_xop_vfrcz_sd: // llvm.x86.xop.vfrcz.sd
ResultTy = VectorType::get(Type::getDoubleTy(Context), 2);
ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
break;
case Intrinsic::x86_sse41_blendpd: // llvm.x86.sse41.blendpd
case Intrinsic::x86_sse41_dppd: // llvm.x86.sse41.dppd
case Intrinsic::x86_sse41_round_sd: // llvm.x86.sse41.round.sd
ResultTy = VectorType::get(Type::getDoubleTy(Context), 2);
ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
ArgTys.push_back(IntegerType::get(Context, 32));
break;
case Intrinsic::x86_sse2_cmp_pd: // llvm.x86.sse2.cmp.pd
case Intrinsic::x86_sse2_cmp_sd: // llvm.x86.sse2.cmp.sd
ResultTy = VectorType::get(Type::getDoubleTy(Context), 2);
ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
ArgTys.push_back(IntegerType::get(Context, 8));
break;
case Intrinsic::x86_fma4_vfmadd_pd: // llvm.x86.fma4.vfmadd.pd
case Intrinsic::x86_fma4_vfmadd_sd: // llvm.x86.fma4.vfmadd.sd
case Intrinsic::x86_fma4_vfmaddsub_pd: // llvm.x86.fma4.vfm
addsub.pd
case Intrinsic::x86_fma4_vfmsub_pd: // llvm.x86.fma4.vfmsub.pd
case Intrinsic::x86_fma4_vfmsub_sd: // llvm.x86.fma4.vfmsub.sd
case Intrinsic::x86_fma4_vfmsubadd_pd: // llvm.x86.fma4.vfm
subadd.pd
case Intrinsic::x86_fma4_vfnmadd_pd: // llvm.x86.fma4.vfnmadd.pd
case Intrinsic::x86_fma4_vfnmadd_sd: // llvm.x86.fma4.vfnmadd.sd
case Intrinsic::x86_fma4_vfnmsub_pd: // llvm.x86.fma4.vfnmsub.pd
case Intrinsic::x86_fma4_vfnmsub_sd: // llvm.x86.fma4.vfnmsub.sd
case Intrinsic::x86_sse41_blendvpd: // llvm.x86.sse41.blendvpd
ResultTy = VectorType::get(Type::getDoubleTy(Context), 2);
ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
break;
case Intrinsic::x86_xop_vpermil2pd: // llvm.x86.xop.vpermil2pd
ResultTy = VectorType::get(Type::getDoubleTy(Context), 2);
ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
ArgTys.push_back(IntegerType::get(Context, 8));
break;
case Intrinsic::x86_avx_vpermilvar_pd: // llvm.x86.avx.vper
milvar.pd
ResultTy = VectorType::get(Type::getDoubleTy(Context), 2);
ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 2));
break;
case Intrinsic::x86_sse2_cvtss2sd: // llvm.x86.sse2.cvtss2sd
ResultTy = VectorType::get(Type::getDoubleTy(Context), 2);
ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
break;
case Intrinsic::x86_sse2_cvtps2pd: // llvm.x86.sse2.cvtps2pd
ResultTy = VectorType::get(Type::getDoubleTy(Context), 2);
ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
break;
case Intrinsic::x86_avx_vextractf128_pd_256: // llvm.x86.avx.vext
ractf128.pd.256
ResultTy = VectorType::get(Type::getDoubleTy(Context), 2);
ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 4));
ArgTys.push_back(IntegerType::get(Context, 8));
break;
case Intrinsic::x86_sse2_cvtdq2pd: // llvm.x86.sse2.cvtdq2pd
ResultTy = VectorType::get(Type::getDoubleTy(Context), 2);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
break;
case Intrinsic::x86_sse_cvtpi2pd: // llvm.x86.sse.cvtpi2pd
ResultTy = VectorType::get(Type::getDoubleTy(Context), 2);
ArgTys.push_back(Type::getX86_MMXTy(Context));
break;
case Intrinsic::arm_neon_vacged: // llvm.arm.neon.vacged
case Intrinsic::arm_neon_vacgtd: // llvm.arm.neon.vacgtd
ResultTy = VectorType::get(IntegerType::get(Context, 32), 2);
ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 2));
ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 2));
break;
case Intrinsic::x86_sse41_movntdqa: // llvm.x86.sse41.movntdqa
ResultTy = VectorType::get(IntegerType::get(Context, 64), 2);
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
break;
case Intrinsic::x86_avx2_maskload_q: // llvm.x86.avx2.maskload.q
ResultTy = VectorType::get(IntegerType::get(Context, 64), 2);
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 2));
break;
case Intrinsic::x86_sse41_pmovsxbq: // llvm.x86.sse41.pmovsxbq
case Intrinsic::x86_sse41_pmovzxbq: // llvm.x86.sse41.pmovzxbq
case Intrinsic::x86_xop_vphaddbq: // llvm.x86.xop.vphaddbq
case Intrinsic::x86_xop_vphaddubq: // llvm.x86.xop.vphaddubq
ResultTy = VectorType::get(IntegerType::get(Context, 64), 2);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
break;
case Intrinsic::x86_sse2_psad_bw: // llvm.x86.sse2.psad.bw
ResultTy = VectorType::get(IntegerType::get(Context, 64), 2);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
break;
case Intrinsic::x86_aesni_aesimc: // llvm.x86.aesni.aesimc
case Intrinsic::x86_avx2_pbroadcastq_128: // llvm.x86.avx2.pbr
oadcastq.128
ResultTy = VectorType::get(IntegerType::get(Context, 64), 2);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 2));
break;
case Intrinsic::x86_sse2_psll_dq: // llvm.x86.sse2.psll.dq
case Intrinsic::x86_sse2_psll_dq_bs: // llvm.x86.sse2.psll.dq.bs
case Intrinsic::x86_sse2_pslli_q: // llvm.x86.sse2.pslli.q
case Intrinsic::x86_sse2_psrl_dq: // llvm.x86.sse2.psrl.dq
case Intrinsic::x86_sse2_psrl_dq_bs: // llvm.x86.sse2.psrl.dq.bs
case Intrinsic::x86_sse2_psrli_q: // llvm.x86.sse2.psrli.q
ResultTy = VectorType::get(IntegerType::get(Context, 64), 2);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 2));
ArgTys.push_back(IntegerType::get(Context, 32));
break;
case Intrinsic::x86_aesni_aeskeygenassist: // llvm.x86.aesni.ae
skeygenassist
ResultTy = VectorType::get(IntegerType::get(Context, 64), 2);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 2));
ArgTys.push_back(IntegerType::get(Context, 8));
break;
case Intrinsic::x86_aesni_aesdec: // llvm.x86.aesni.aesdec
case Intrinsic::x86_aesni_aesdeclast: // llvm.x86.aesni.ae
sdeclast
case Intrinsic::x86_aesni_aesenc: // llvm.x86.aesni.aesenc
case Intrinsic::x86_aesni_aesenclast: // llvm.x86.aesni.ae
senclast
case Intrinsic::x86_avx2_psllv_q: // llvm.x86.avx2.psllv.q
case Intrinsic::x86_avx2_psrlv_q: // llvm.x86.avx2.psrlv.q
case Intrinsic::x86_sse2_psll_q: // llvm.x86.sse2.psll.q
case Intrinsic::x86_sse2_psrl_q: // llvm.x86.sse2.psrl.q
case Intrinsic::x86_xop_vpcomeqq: // llvm.x86.xop.vpcomeqq
case Intrinsic::x86_xop_vpcomequq: // llvm.x86.xop.vpcomequq
case Intrinsic::x86_xop_vpcomfalseq: // llvm.x86.xop.vpcomfalseq
case Intrinsic::x86_xop_vpcomfalseuq: // llvm.x86.xop.vpco
mfalseuq
case Intrinsic::x86_xop_vpcomgeq: // llvm.x86.xop.vpcomgeq
case Intrinsic::x86_xop_vpcomgeuq: // llvm.x86.xop.vpcomgeuq
case Intrinsic::x86_xop_vpcomgtq: // llvm.x86.xop.vpcomgtq
case Intrinsic::x86_xop_vpcomgtuq: // llvm.x86.xop.vpcomgtuq
case Intrinsic::x86_xop_vpcomleq: // llvm.x86.xop.vpcomleq
case Intrinsic::x86_xop_vpcomleuq: // llvm.x86.xop.vpcomleuq
case Intrinsic::x86_xop_vpcomltq: // llvm.x86.xop.vpcomltq
case Intrinsic::x86_xop_vpcomltuq: // llvm.x86.xop.vpcomltuq
case Intrinsic::x86_xop_vpcomneq: // llvm.x86.xop.vpcomneq
case Intrinsic::x86_xop_vpcomneuq: // llvm.x86.xop.vpcomneuq
case Intrinsic::x86_xop_vpcomtrueq: // llvm.x86.xop.vpcomtrueq
case Intrinsic::x86_xop_vpcomtrueuq: // llvm.x86.xop.vpcomtrueuq
case Intrinsic::x86_xop_vprotq: // llvm.x86.xop.vprotq
case Intrinsic::x86_xop_vpshaq: // llvm.x86.xop.vpshaq
case Intrinsic::x86_xop_vpshlq: // llvm.x86.xop.vpshlq
ResultTy = VectorType::get(IntegerType::get(Context, 64), 2);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 2));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 2));
break;
case Intrinsic::x86_xop_vpcmov: // llvm.x86.xop.vpcmov
ResultTy = VectorType::get(IntegerType::get(Context, 64), 2);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 2));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 2));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 2));
break;
case Intrinsic::x86_sse41_pmovsxdq: // llvm.x86.sse41.pmovsxdq
case Intrinsic::x86_sse41_pmovzxdq: // llvm.x86.sse41.pmovzxdq
case Intrinsic::x86_xop_vphadddq: // llvm.x86.xop.vphadddq
case Intrinsic::x86_xop_vphaddudq: // llvm.x86.xop.vphaddudq
case Intrinsic::x86_xop_vphsubdq: // llvm.x86.xop.vphsubdq
ResultTy = VectorType::get(IntegerType::get(Context, 64), 2);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
break;
case Intrinsic::x86_sse2_pmulu_dq: // llvm.x86.sse2.pmulu.dq
case Intrinsic::x86_sse41_pmuldq: // llvm.x86.sse41.pmuldq
ResultTy = VectorType::get(IntegerType::get(Context, 64), 2);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
break;
case Intrinsic::x86_xop_vpmacsdqh: // llvm.x86.xop.vpmacsdqh
case Intrinsic::x86_xop_vpmacsdql: // llvm.x86.xop.vpmacsdql
case Intrinsic::x86_xop_vpmacssdqh: // llvm.x86.xop.vpmacssdqh
case Intrinsic::x86_xop_vpmacssdql: // llvm.x86.xop.vpmacssdql
ResultTy = VectorType::get(IntegerType::get(Context, 64), 2);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 2));
break;
case Intrinsic::x86_avx2_vextracti128: // llvm.x86.avx2.vex
tracti128
ResultTy = VectorType::get(IntegerType::get(Context, 64), 2);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 4));
ArgTys.push_back(IntegerType::get(Context, 8));
break;
case Intrinsic::x86_sse41_pmovsxwq: // llvm.x86.sse41.pmovsxwq
case Intrinsic::x86_sse41_pmovzxwq: // llvm.x86.sse41.pmovzxwq
case Intrinsic::x86_xop_vphadduwq: // llvm.x86.xop.vphadduwq
case Intrinsic::x86_xop_vphaddwq: // llvm.x86.xop.vphaddwq
ResultTy = VectorType::get(IntegerType::get(Context, 64), 2);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
break;
case Intrinsic::x86_avx_ldu_dq_256: // llvm.x86.avx.ldu.dq.256
ResultTy = VectorType::get(IntegerType::get(Context, 8), 32);
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
break;
case Intrinsic::x86_avx2_packsswb: // llvm.x86.avx2.packsswb
case Intrinsic::x86_avx2_packuswb: // llvm.x86.avx2.packuswb
ResultTy = VectorType::get(IntegerType::get(Context, 8), 32);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 16));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 16));
break;
case Intrinsic::x86_avx2_pbroadcastb_256: // llvm.x86.avx2.pbr
oadcastb.256
ResultTy = VectorType::get(IntegerType::get(Context, 8), 32);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
break;
case Intrinsic::x86_avx2_pabs_b: // llvm.x86.avx2.pabs.b
ResultTy = VectorType::get(IntegerType::get(Context, 8), 32);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 32));
break;
case Intrinsic::x86_avx2_padds_b: // llvm.x86.avx2.padds.b
case Intrinsic::x86_avx2_paddus_b: // llvm.x86.avx2.paddus.b
case Intrinsic::x86_avx2_pavg_b: // llvm.x86.avx2.pavg.b
case Intrinsic::x86_avx2_pmaxs_b: // llvm.x86.avx2.pmaxs.b
case Intrinsic::x86_avx2_pmaxu_b: // llvm.x86.avx2.pmaxu.b
case Intrinsic::x86_avx2_pmins_b: // llvm.x86.avx2.pmins.b
case Intrinsic::x86_avx2_pminu_b: // llvm.x86.avx2.pminu.b
case Intrinsic::x86_avx2_pshuf_b: // llvm.x86.avx2.pshuf.b
case Intrinsic::x86_avx2_psign_b: // llvm.x86.avx2.psign.b
case Intrinsic::x86_avx2_psubs_b: // llvm.x86.avx2.psubs.b
case Intrinsic::x86_avx2_psubus_b: // llvm.x86.avx2.psubus.b
ResultTy = VectorType::get(IntegerType::get(Context, 8), 32);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 32));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 32));
break;
case Intrinsic::x86_avx2_pblendvb: // llvm.x86.avx2.pblendvb
ResultTy = VectorType::get(IntegerType::get(Context, 8), 32);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 32));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 32));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 32));
break;
case Intrinsic::x86_avx_vbroadcast_ss: // llvm.x86.avx.vbro
adcast.ss
ResultTy = VectorType::get(Type::getFloatTy(Context), 4);
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
break;
case Intrinsic::x86_avx_maskload_ps: // llvm.x86.avx.maskload.ps
ResultTy = VectorType::get(Type::getFloatTy(Context), 4);
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
break;
case Intrinsic::x86_sse2_cvtpd2ps: // llvm.x86.sse2.cvtpd2ps
ResultTy = VectorType::get(Type::getFloatTy(Context), 4);
ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
break;
case Intrinsic::ppc_altivec_vexptefp: // llvm.ppc.altivec.
vexptefp
case Intrinsic::ppc_altivec_vlogefp: // llvm.ppc.altivec.vlogefp
case Intrinsic::ppc_altivec_vrefp: // llvm.ppc.altivec.vrefp
case Intrinsic::ppc_altivec_vrfim: // llvm.ppc.altivec.vrfim
case Intrinsic::ppc_altivec_vrfin: // llvm.ppc.altivec.vrfin
case Intrinsic::ppc_altivec_vrfip: // llvm.ppc.altivec.vrfip
case Intrinsic::ppc_altivec_vrfiz: // llvm.ppc.altivec.vrfiz
case Intrinsic::ppc_altivec_vrsqrtefp: // llvm.ppc.altivec.
vrsqrtefp
case Intrinsic::x86_avx2_vbroadcast_ss_ps: // llvm.x86.avx2.vbr
oadcast.ss.ps
case Intrinsic::x86_sse_rcp_ps: // llvm.x86.sse.rcp.ps
case Intrinsic::x86_sse_rcp_ss: // llvm.x86.sse.rcp.ss
case Intrinsic::x86_sse_rsqrt_ps: // llvm.x86.sse.rsqrt.ps
case Intrinsic::x86_sse_rsqrt_ss: // llvm.x86.sse.rsqrt.ss
case Intrinsic::x86_sse_sqrt_ps: // llvm.x86.sse.sqrt.ps
case Intrinsic::x86_sse_sqrt_ss: // llvm.x86.sse.sqrt.ss
case Intrinsic::x86_xop_vfrcz_ps: // llvm.x86.xop.vfrcz.ps
ResultTy = VectorType::get(Type::getFloatTy(Context), 4);
ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
break;
case Intrinsic::x86_sse41_round_ps: // llvm.x86.sse41.round.ps
case Intrinsic::x86_sse_cvtsi2ss: // llvm.x86.sse.cvtsi2ss
ResultTy = VectorType::get(Type::getFloatTy(Context), 4);
ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
ArgTys.push_back(IntegerType::get(Context, 32));
break;
case Intrinsic::x86_sse_cvtsi642ss: // llvm.x86.sse.cvtsi642ss
ResultTy = VectorType::get(Type::getFloatTy(Context), 4);
ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
ArgTys.push_back(IntegerType::get(Context, 64));
break;
case Intrinsic::x86_sse2_cvtsd2ss: // llvm.x86.sse2.cvtsd2ss
ResultTy = VectorType::get(Type::getFloatTy(Context), 4);
ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
break;
case Intrinsic::ppc_altivec_vmaxfp: // llvm.ppc.altivec.vmaxfp
case Intrinsic::ppc_altivec_vminfp: // llvm.ppc.altivec.vminfp
case Intrinsic::spu_si_fa: // llvm.spu.si.fa
case Intrinsic::spu_si_fceq: // llvm.spu.si.fceq
case Intrinsic::spu_si_fcgt: // llvm.spu.si.fcgt
case Intrinsic::spu_si_fcmeq: // llvm.spu.si.fcmeq
case Intrinsic::spu_si_fcmgt: // llvm.spu.si.fcmgt
case Intrinsic::spu_si_fm: // llvm.spu.si.fm
case Intrinsic::spu_si_fs: // llvm.spu.si.fs
case Intrinsic::x86_sse3_addsub_ps: // llvm.x86.sse3.addsub.ps
case Intrinsic::x86_sse3_hadd_ps: // llvm.x86.sse3.hadd.ps
case Intrinsic::x86_sse3_hsub_ps: // llvm.x86.sse3.hsub.ps
case Intrinsic::x86_sse_add_ss: // llvm.x86.sse.add.ss
case Intrinsic::x86_sse_div_ss: // llvm.x86.sse.div.ss
case Intrinsic::x86_sse_max_ps: // llvm.x86.sse.max.ps
case Intrinsic::x86_sse_max_ss: // llvm.x86.sse.max.ss
case Intrinsic::x86_sse_min_ps: // llvm.x86.sse.min.ps
case Intrinsic::x86_sse_min_ss: // llvm.x86.sse.min.ss
case Intrinsic::x86_sse_mul_ss: // llvm.x86.sse.mul.ss
case Intrinsic::x86_sse_sub_ss: // llvm.x86.sse.sub.ss
case Intrinsic::x86_xop_vfrcz_ss: // llvm.x86.xop.vfrcz.ss
ResultTy = VectorType::get(Type::getFloatTy(Context), 4);
ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
break;
case Intrinsic::x86_sse41_blendps: // llvm.x86.sse41.blendps
case Intrinsic::x86_sse41_dpps: // llvm.x86.sse41.dpps
case Intrinsic::x86_sse41_insertps: // llvm.x86.sse41.insertps
case Intrinsic::x86_sse41_round_ss: // llvm.x86.sse41.round.ss
ResultTy = VectorType::get(Type::getFloatTy(Context), 4);
ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
ArgTys.push_back(IntegerType::get(Context, 32));
break;
case Intrinsic::x86_sse_cmp_ps: // llvm.x86.sse.cmp.ps
case Intrinsic::x86_sse_cmp_ss: // llvm.x86.sse.cmp.ss
ResultTy = VectorType::get(Type::getFloatTy(Context), 4);
ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
ArgTys.push_back(IntegerType::get(Context, 8));
break;
case Intrinsic::ppc_altivec_vmaddfp: // llvm.ppc.altivec.vmaddfp
case Intrinsic::ppc_altivec_vnmsubfp: // llvm.ppc.altivec.
vnmsubfp
case Intrinsic::spu_si_fma: // llvm.spu.si.fma
case Intrinsic::spu_si_fms: // llvm.spu.si.fms
case Intrinsic::spu_si_fnms: // llvm.spu.si.fnms
case Intrinsic::x86_fma4_vfmadd_ps: // llvm.x86.fma4.vfmadd.ps
case Intrinsic::x86_fma4_vfmadd_ss: // llvm.x86.fma4.vfmadd.ss
case Intrinsic::x86_fma4_vfmaddsub_ps: // llvm.x86.fma4.vfm
addsub.ps
case Intrinsic::x86_fma4_vfmsub_ps: // llvm.x86.fma4.vfmsub.ps
case Intrinsic::x86_fma4_vfmsub_ss: // llvm.x86.fma4.vfmsub.ss
case Intrinsic::x86_fma4_vfmsubadd_ps: // llvm.x86.fma4.vfm
subadd.ps
case Intrinsic::x86_fma4_vfnmadd_ps: // llvm.x86.fma4.vfnmadd.ps
case Intrinsic::x86_fma4_vfnmadd_ss: // llvm.x86.fma4.vfnmadd.ss
case Intrinsic::x86_fma4_vfnmsub_ps: // llvm.x86.fma4.vfnmsub.ps
case Intrinsic::x86_fma4_vfnmsub_ss: // llvm.x86.fma4.vfnmsub.ss
case Intrinsic::x86_sse41_blendvps: // llvm.x86.sse41.blendvps
ResultTy = VectorType::get(Type::getFloatTy(Context), 4);
ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
break;
case Intrinsic::x86_xop_vpermil2ps: // llvm.x86.xop.vpermil2ps
ResultTy = VectorType::get(Type::getFloatTy(Context), 4);
ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
ArgTys.push_back(IntegerType::get(Context, 8));
break;
case Intrinsic::x86_avx_vpermilvar_ps: // llvm.x86.avx.vper
milvar.ps
ResultTy = VectorType::get(Type::getFloatTy(Context), 4);
ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
break;
case Intrinsic::x86_sse_cvtpi2ps: // llvm.x86.sse.cvtpi2ps
ResultTy = VectorType::get(Type::getFloatTy(Context), 4);
ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
ArgTys.push_back(Type::getX86_MMXTy(Context));
break;
case Intrinsic::x86_avx_cvt_pd2_ps_256: // llvm.x86.avx.cvt.
pd2.ps.256
ResultTy = VectorType::get(Type::getFloatTy(Context), 4);
ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 4));
break;
case Intrinsic::arm_neon_vcvthf2fp: // llvm.arm.neon.vcvthf2fp
ResultTy = VectorType::get(Type::getFloatTy(Context), 4);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 4));
break;
case Intrinsic::x86_sse2_cvtdq2ps: // llvm.x86.sse2.cvtdq2ps
ResultTy = VectorType::get(Type::getFloatTy(Context), 4);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
break;
case Intrinsic::ppc_altivec_vcfsx: // llvm.ppc.altivec.vcfsx
case Intrinsic::ppc_altivec_vcfux: // llvm.ppc.altivec.vcfux
ResultTy = VectorType::get(Type::getFloatTy(Context), 4);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
ArgTys.push_back(IntegerType::get(Context, 32));
break;
case Intrinsic::x86_avx_vextractf128_ps_256: // llvm.x86.avx.vext
ractf128.ps.256
ResultTy = VectorType::get(Type::getFloatTy(Context), 4);
ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 8));
ArgTys.push_back(IntegerType::get(Context, 8));
break;
case Intrinsic::x86_vcvtph2ps_128: // llvm.x86.vcvtph2ps.128
ResultTy = VectorType::get(Type::getFloatTy(Context), 4);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
break;
case Intrinsic::x86_avx_vbroadcast_sd_256: // llvm.x86.avx.vbro
adcast.sd.256
case Intrinsic::x86_avx_vbroadcastf128_pd_256: // llvm.x86.
avx.vbroadcastf128.pd.256
ResultTy = VectorType::get(Type::getDoubleTy(Context), 4);
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
break;
case Intrinsic::x86_avx_maskload_pd_256: // llvm.x86.avx.mask
load.pd.256
ResultTy = VectorType::get(Type::getDoubleTy(Context), 4);
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 4));
break;
case Intrinsic::x86_avx2_vbroadcast_sd_pd_256: // llvm.x86.
avx2.vbroadcast.sd.pd.256
ResultTy = VectorType::get(Type::getDoubleTy(Context), 4);
ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
break;
case Intrinsic::x86_avx_cvt_ps2_pd_256: // llvm.x86.avx.cvt.
ps2.pd.256
ResultTy = VectorType::get(Type::getDoubleTy(Context), 4);
ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
break;
case Intrinsic::x86_avx_sqrt_pd_256: // llvm.x86.avx.sqrt.pd.256
case Intrinsic::x86_xop_vfrcz_pd_256: // llvm.x86.xop.vfrc
z.pd.256
ResultTy = VectorType::get(Type::getDoubleTy(Context), 4);
ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 4));
break;
case Intrinsic::x86_avx_round_pd_256: // llvm.x86.avx.roun
d.pd.256
ResultTy = VectorType::get(Type::getDoubleTy(Context), 4);
ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 4));
ArgTys.push_back(IntegerType::get(Context, 32));
break;
case Intrinsic::x86_avx_vinsertf128_pd_256: // llvm.x86.avx.vins
ertf128.pd.256
ResultTy = VectorType::get(Type::getDoubleTy(Context), 4);
ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 4));
ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
ArgTys.push_back(IntegerType::get(Context, 8));
break;
case Intrinsic::x86_avx_addsub_pd_256: // llvm.x86.avx.adds
ub.pd.256
case Intrinsic::x86_avx_hadd_pd_256: // llvm.x86.avx.hadd.pd.256
case Intrinsic::x86_avx_hsub_pd_256: // llvm.x86.avx.hsub.pd.256
case Intrinsic::x86_avx_max_pd_256: // llvm.x86.avx.max.pd.256
case Intrinsic::x86_avx_min_pd_256: // llvm.x86.avx.min.pd.256
ResultTy = VectorType::get(Type::getDoubleTy(Context), 4);
ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 4));
ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 4));
break;
case Intrinsic::x86_avx_blend_pd_256: // llvm.x86.avx.blen
d.pd.256
ResultTy = VectorType::get(Type::getDoubleTy(Context), 4);
ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 4));
ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 4));
ArgTys.push_back(IntegerType::get(Context, 32));
break;
case Intrinsic::x86_avx_cmp_pd_256: // llvm.x86.avx.cmp.pd.256
case Intrinsic::x86_avx_vperm2f128_pd_256: // llvm.x86.avx.vper
m2f128.pd.256
ResultTy = VectorType::get(Type::getDoubleTy(Context), 4);
ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 4));
ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 4));
ArgTys.push_back(IntegerType::get(Context, 8));
break;
case Intrinsic::x86_avx_blendv_pd_256: // llvm.x86.avx.blen
dv.pd.256
case Intrinsic::x86_fma4_vfmadd_pd_256: // llvm.x86.fma4.vfm
add.pd.256
case Intrinsic::x86_fma4_vfmaddsub_pd_256: // llvm.x86.fma4.vfm
addsub.pd.256
case Intrinsic::x86_fma4_vfmsub_pd_256: // llvm.x86.fma4.vfm
sub.pd.256
case Intrinsic::x86_fma4_vfmsubadd_pd_256: // llvm.x86.fma4.vfm
subadd.pd.256
case Intrinsic::x86_fma4_vfnmadd_pd_256: // llvm.x86.fma4.vfn
madd.pd.256
case Intrinsic::x86_fma4_vfnmsub_pd_256: // llvm.x86.fma4.vfn
msub.pd.256
ResultTy = VectorType::get(Type::getDoubleTy(Context), 4);
ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 4));
ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 4));
ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 4));
break;
case Intrinsic::x86_xop_vpermil2pd_256: // llvm.x86.xop.vper
mil2pd.256
ResultTy = VectorType::get(Type::getDoubleTy(Context), 4);
ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 4));
ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 4));
ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 4));
ArgTys.push_back(IntegerType::get(Context, 8));
break;
case Intrinsic::x86_avx_vpermilvar_pd_256: // llvm.x86.avx.vper
milvar.pd.256
ResultTy = VectorType::get(Type::getDoubleTy(Context), 4);
ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 4));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 4));
break;
case Intrinsic::x86_avx_cvtdq2_pd_256: // llvm.x86.avx.cvtd
q2.pd.256
ResultTy = VectorType::get(Type::getDoubleTy(Context), 4);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
break;
case Intrinsic::arm_neon_vcvtfp2hf: // llvm.arm.neon.vcvtfp2hf
ResultTy = VectorType::get(IntegerType::get(Context, 16), 4);
ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
break;
case Intrinsic::ppc_altivec_lvewx: // llvm.ppc.altivec.lvewx
case Intrinsic::ppc_altivec_lvx: // llvm.ppc.altivec.lvx
case Intrinsic::ppc_altivec_lvxl: // llvm.ppc.altivec.lvxl
ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
break;
case Intrinsic::x86_avx2_maskload_d: // llvm.x86.avx2.maskload.d
ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
break;
case Intrinsic::x86_sse41_pmovsxbd: // llvm.x86.sse41.pmovsxbd
case Intrinsic::x86_sse41_pmovzxbd: // llvm.x86.sse41.pmovzxbd
case Intrinsic::x86_xop_vphaddbd: // llvm.x86.xop.vphaddbd
case Intrinsic::x86_xop_vphaddubd: // llvm.x86.xop.vphaddubd
ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
break;
case Intrinsic::ppc_altivec_vmsummbm: // llvm.ppc.altivec.
vmsummbm
case Intrinsic::ppc_altivec_vmsumubm: // llvm.ppc.altivec.
vmsumubm
ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
break;
case Intrinsic::ppc_altivec_vsum4sbs: // llvm.ppc.altivec.
vsum4sbs
case Intrinsic::ppc_altivec_vsum4ubs: // llvm.ppc.altivec.
vsum4ubs
ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
break;
case Intrinsic::x86_sse2_cvtpd2dq: // llvm.x86.sse2.cvtpd2dq
case Intrinsic::x86_sse2_cvttpd2dq: // llvm.x86.sse2.cvttpd2dq
ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);
ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
break;
case Intrinsic::x86_sse2_cvtps2dq: // llvm.x86.sse2.cvtps2dq
case Intrinsic::x86_sse2_cvttps2dq: // llvm.x86.sse2.cvttps2dq
ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);
ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
break;
case Intrinsic::ppc_altivec_vctsxs: // llvm.ppc.altivec.vctsxs
case Intrinsic::ppc_altivec_vctuxs: // llvm.ppc.altivec.vctuxs
ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);
ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
ArgTys.push_back(IntegerType::get(Context, 32));
break;
case Intrinsic::arm_neon_vacgeq: // llvm.arm.neon.vacgeq
case Intrinsic::arm_neon_vacgtq: // llvm.arm.neon.vacgtq
case Intrinsic::ppc_altivec_vcmpbfp: // llvm.ppc.altivec.vcmpbfp
case Intrinsic::ppc_altivec_vcmpeqfp: // llvm.ppc.altivec.
vcmpeqfp
case Intrinsic::ppc_altivec_vcmpgefp: // llvm.ppc.altivec.
vcmpgefp
case Intrinsic::ppc_altivec_vcmpgtfp: // llvm.ppc.altivec.
vcmpgtfp
ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);
ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
break;
case Intrinsic::x86_avx_cvt_pd2dq_256: // llvm.x86.avx.cvt.
pd2dq.256
case Intrinsic::x86_avx_cvtt_pd2dq_256: // llvm.x86.avx.cvtt
.pd2dq.256
ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);
ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 4));
break;
case Intrinsic::x86_avx2_pbroadcastd_128: // llvm.x86.avx2.pbr
oadcastd.128
case Intrinsic::x86_ssse3_pabs_d_128: // llvm.x86.ssse3.pa
bs.d.128
ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
break;
case Intrinsic::spu_si_shli: // llvm.spu.si.shli
ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
ArgTys.push_back(IntegerType::get(Context, 8));
break;
case Intrinsic::spu_si_ai: // llvm.spu.si.ai
case Intrinsic::spu_si_andi: // llvm.spu.si.andi
case Intrinsic::spu_si_ceqi: // llvm.spu.si.ceqi
case Intrinsic::spu_si_cgti: // llvm.spu.si.cgti
case Intrinsic::spu_si_clgti: // llvm.spu.si.clgti
case Intrinsic::spu_si_ori: // llvm.spu.si.ori
case Intrinsic::spu_si_sfi: // llvm.spu.si.sfi
case Intrinsic::spu_si_xori: // llvm.spu.si.xori
ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
ArgTys.push_back(IntegerType::get(Context, 16));
break;
case Intrinsic::x86_sse2_pslli_d: // llvm.x86.sse2.pslli.d
case Intrinsic::x86_sse2_psrai_d: // llvm.x86.sse2.psrai.d
case Intrinsic::x86_sse2_psrli_d: // llvm.x86.sse2.psrli.d
ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
ArgTys.push_back(IntegerType::get(Context, 32));
break;
case Intrinsic::ppc_altivec_vaddcuw: // llvm.ppc.altivec.vaddcuw
case Intrinsic::ppc_altivec_vaddsws: // llvm.ppc.altivec.vaddsws
case Intrinsic::ppc_altivec_vadduws: // llvm.ppc.altivec.vadduws
case Intrinsic::ppc_altivec_vavgsw: // llvm.ppc.altivec.vavgsw
case Intrinsic::ppc_altivec_vavguw: // llvm.ppc.altivec.vavguw
case Intrinsic::ppc_altivec_vcmpequw: // llvm.ppc.altivec.
vcmpequw
case Intrinsic::ppc_altivec_vcmpgtsw: // llvm.ppc.altivec.
vcmpgtsw
case Intrinsic::ppc_altivec_vcmpgtuw: // llvm.ppc.altivec.
vcmpgtuw
case Intrinsic::ppc_altivec_vmaxsw: // llvm.ppc.altivec.vmaxsw
case Intrinsic::ppc_altivec_vmaxuw: // llvm.ppc.altivec.vmaxuw
case Intrinsic::ppc_altivec_vminsw: // llvm.ppc.altivec.vminsw
case Intrinsic::ppc_altivec_vminuw: // llvm.ppc.altivec.vminuw
case Intrinsic::ppc_altivec_vrlw: // llvm.ppc.altivec.vrlw
case Intrinsic::ppc_altivec_vsl: // llvm.ppc.altivec.vsl
case Intrinsic::ppc_altivec_vslo: // llvm.ppc.altivec.vslo
case Intrinsic::ppc_altivec_vslw: // llvm.ppc.altivec.vslw
case Intrinsic::ppc_altivec_vsr: // llvm.ppc.altivec.vsr
case Intrinsic::ppc_altivec_vsraw: // llvm.ppc.altivec.vsraw
case Intrinsic::ppc_altivec_vsro: // llvm.ppc.altivec.vsro
case Intrinsic::ppc_altivec_vsrw: // llvm.ppc.altivec.vsrw
case Intrinsic::ppc_altivec_vsubcuw: // llvm.ppc.altivec.vsubcuw
case Intrinsic::ppc_altivec_vsubsws: // llvm.ppc.altivec.vsubsws
case Intrinsic::ppc_altivec_vsubuws: // llvm.ppc.altivec.vsubuws
case Intrinsic::ppc_altivec_vsum2sws: // llvm.ppc.altivec.
vsum2sws
case Intrinsic::ppc_altivec_vsumsws: // llvm.ppc.altivec.vsumsws
case Intrinsic::spu_si_a: // llvm.spu.si.a
case Intrinsic::spu_si_addx: // llvm.spu.si.addx
case Intrinsic::spu_si_and: // llvm.spu.si.and
case Intrinsic::spu_si_andc: // llvm.spu.si.andc
case Intrinsic::spu_si_bg: // llvm.spu.si.bg
case Intrinsic::spu_si_bgx: // llvm.spu.si.bgx
case Intrinsic::spu_si_ceq: // llvm.spu.si.ceq
case Intrinsic::spu_si_cg: // llvm.spu.si.cg
case Intrinsic::spu_si_cgt: // llvm.spu.si.cgt
case Intrinsic::spu_si_cgx: // llvm.spu.si.cgx
case Intrinsic::spu_si_clgt: // llvm.spu.si.clgt
case Intrinsic::spu_si_nand: // llvm.spu.si.nand
case Intrinsic::spu_si_nor: // llvm.spu.si.nor
case Intrinsic::spu_si_or: // llvm.spu.si.or
case Intrinsic::spu_si_orc: // llvm.spu.si.orc
case Intrinsic::spu_si_sf: // llvm.spu.si.sf
case Intrinsic::spu_si_sfx: // llvm.spu.si.sfx
case Intrinsic::spu_si_xor: // llvm.spu.si.xor
case Intrinsic::x86_avx2_psllv_d: // llvm.x86.avx2.psllv.d
case Intrinsic::x86_avx2_psrav_d: // llvm.x86.avx2.psrav.d
case Intrinsic::x86_avx2_psrlv_d: // llvm.x86.avx2.psrlv.d
case Intrinsic::x86_sse2_psll_d: // llvm.x86.sse2.psll.d
case Intrinsic::x86_sse2_psra_d: // llvm.x86.sse2.psra.d
case Intrinsic::x86_sse2_psrl_d: // llvm.x86.sse2.psrl.d
case Intrinsic::x86_sse41_pmaxsd: // llvm.x86.sse41.pmaxsd
case Intrinsic::x86_sse41_pmaxud: // llvm.x86.sse41.pmaxud
case Intrinsic::x86_sse41_pminsd: // llvm.x86.sse41.pminsd
case Intrinsic::x86_sse41_pminud: // llvm.x86.sse41.pminud
case Intrinsic::x86_ssse3_phadd_d_128: // llvm.x86.ssse3.ph
add.d.128
case Intrinsic::x86_ssse3_phsub_d_128: // llvm.x86.ssse3.ph
sub.d.128
case Intrinsic::x86_ssse3_psign_d_128: // llvm.x86.ssse3.ps
ign.d.128
case Intrinsic::x86_xop_vpcomeqd: // llvm.x86.xop.vpcomeqd
case Intrinsic::x86_xop_vpcomequd: // llvm.x86.xop.vpcomequd
case Intrinsic::x86_xop_vpcomfalsed: // llvm.x86.xop.vpcomfalsed
case Intrinsic::x86_xop_vpcomfalseud: // llvm.x86.xop.vpco
mfalseud
case Intrinsic::x86_xop_vpcomged: // llvm.x86.xop.vpcomged
case Intrinsic::x86_xop_vpcomgeud: // llvm.x86.xop.vpcomgeud
case Intrinsic::x86_xop_vpcomgtd: // llvm.x86.xop.vpcomgtd
case Intrinsic::x86_xop_vpcomgtud: // llvm.x86.xop.vpcomgtud
case Intrinsic::x86_xop_vpcomled: // llvm.x86.xop.vpcomled
case Intrinsic::x86_xop_vpcomleud: // llvm.x86.xop.vpcomleud
case Intrinsic::x86_xop_vpcomltd: // llvm.x86.xop.vpcomltd
case Intrinsic::x86_xop_vpcomltud: // llvm.x86.xop.vpcomltud
case Intrinsic::x86_xop_vpcomned: // llvm.x86.xop.vpcomned
case Intrinsic::x86_xop_vpcomneud: // llvm.x86.xop.vpcomneud
case Intrinsic::x86_xop_vpcomtrued: // llvm.x86.xop.vpcomtrued
case Intrinsic::x86_xop_vpcomtrueud: // llvm.x86.xop.vpcomtrueud
case Intrinsic::x86_xop_vprotd: // llvm.x86.xop.vprotd
case Intrinsic::x86_xop_vpshad: // llvm.x86.xop.vpshad
case Intrinsic::x86_xop_vpshld: // llvm.x86.xop.vpshld
ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
break;
case Intrinsic::x86_avx2_pblendd_128: // llvm.x86.avx2.pbl
endd.128
ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
ArgTys.push_back(IntegerType::get(Context, 32));
break;
case Intrinsic::ppc_altivec_vperm: // llvm.ppc.altivec.vperm
ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
break;
case Intrinsic::ppc_altivec_vsel: // llvm.ppc.altivec.vsel
case Intrinsic::x86_xop_vpmacsdd: // llvm.x86.xop.vpmacsdd
case Intrinsic::x86_xop_vpmacssdd: // llvm.x86.xop.vpmacssdd
ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
break;
case Intrinsic::spu_si_mpyh: // llvm.spu.si.mpyh
ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
break;
case Intrinsic::ppc_altivec_vupkhpx: // llvm.ppc.altivec.vupkhpx
case Intrinsic::ppc_altivec_vupkhsh: // llvm.ppc.altivec.vupkhsh
case Intrinsic::ppc_altivec_vupklpx: // llvm.ppc.altivec.vupklpx
case Intrinsic::ppc_altivec_vupklsh: // llvm.ppc.altivec.vupklsh
case Intrinsic::x86_sse41_pmovsxwd: // llvm.x86.sse41.pmovsxwd
case Intrinsic::x86_sse41_pmovzxwd: // llvm.x86.sse41.pmovzxwd
case Intrinsic::x86_xop_vphadduwd: // llvm.x86.xop.vphadduwd
case Intrinsic::x86_xop_vphaddwd: // llvm.x86.xop.vphaddwd
case Intrinsic::x86_xop_vphsubwd: // llvm.x86.xop.vphsubwd
ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
break;
case Intrinsic::spu_si_mpyi: // llvm.spu.si.mpyi
case Intrinsic::spu_si_mpyui: // llvm.spu.si.mpyui
ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
ArgTys.push_back(IntegerType::get(Context, 16));
break;
case Intrinsic::ppc_altivec_vsum4shs: // llvm.ppc.altivec.
vsum4shs
ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
break;
case Intrinsic::ppc_altivec_vmulesh: // llvm.ppc.altivec.vmulesh
case Intrinsic::ppc_altivec_vmuleuh: // llvm.ppc.altivec.vmuleuh
case Intrinsic::ppc_altivec_vmulosh: // llvm.ppc.altivec.vmulosh
case Intrinsic::ppc_altivec_vmulouh: // llvm.ppc.altivec.vmulouh
case Intrinsic::spu_si_mpy: // llvm.spu.si.mpy
case Intrinsic::spu_si_mpyhh: // llvm.spu.si.mpyhh
case Intrinsic::spu_si_mpyhha: // llvm.spu.si.mpyhha
case Intrinsic::spu_si_mpyhhau: // llvm.spu.si.mpyhhau
case Intrinsic::spu_si_mpyhhu: // llvm.spu.si.mpyhhu
case Intrinsic::spu_si_mpys: // llvm.spu.si.mpys
case Intrinsic::spu_si_mpyu: // llvm.spu.si.mpyu
case Intrinsic::x86_sse2_pmadd_wd: // llvm.x86.sse2.pmadd.wd
ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
break;
case Intrinsic::ppc_altivec_vmsumshm: // llvm.ppc.altivec.
vmsumshm
case Intrinsic::ppc_altivec_vmsumshs: // llvm.ppc.altivec.
vmsumshs
case Intrinsic::ppc_altivec_vmsumuhm: // llvm.ppc.altivec.
vmsumuhm
case Intrinsic::ppc_altivec_vmsumuhs: // llvm.ppc.altivec.
vmsumuhs
case Intrinsic::x86_xop_vpmacsswd: // llvm.x86.xop.vpmacsswd
case Intrinsic::x86_xop_vpmacswd: // llvm.x86.xop.vpmacswd
case Intrinsic::x86_xop_vpmadcsswd: // llvm.x86.xop.vpmadcsswd
case Intrinsic::x86_xop_vpmadcswd: // llvm.x86.xop.vpmadcswd
ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
break;
case Intrinsic::spu_si_mpya: // llvm.spu.si.mpya
ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
break;
case Intrinsic::x86_avx_vextractf128_si_256: // llvm.x86.avx.vext
ractf128.si.256
ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 8));
ArgTys.push_back(IntegerType::get(Context, 8));
break;
case Intrinsic::x86_avx2_movntdqa: // llvm.x86.avx2.movntdqa
case Intrinsic::x86_avx2_vbroadcasti128: // llvm.x86.avx2.vbr
oadcasti128
ResultTy = VectorType::get(IntegerType::get(Context, 64), 4);
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
break;
case Intrinsic::x86_avx2_maskload_q_256: // llvm.x86.avx2.mas
kload.q.256
ResultTy = VectorType::get(IntegerType::get(Context, 64), 4);
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 4));
break;
case Intrinsic::x86_avx2_pmovsxbq: // llvm.x86.avx2.pmovsxbq
case Intrinsic::x86_avx2_pmovzxbq: // llvm.x86.avx2.pmovzxbq
ResultTy = VectorType::get(IntegerType::get(Context, 64), 4);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
break;
case Intrinsic::x86_avx2_pbroadcastq_256: // llvm.x86.avx2.pbr
oadcastq.256
ResultTy = VectorType::get(IntegerType::get(Context, 64), 4);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 2));
break;
case Intrinsic::x86_avx2_psad_bw: // llvm.x86.avx2.psad.bw
ResultTy = VectorType::get(IntegerType::get(Context, 64), 4);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 32));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 32));
break;
case Intrinsic::x86_avx2_pmovsxdq: // llvm.x86.avx2.pmovsxdq
case Intrinsic::x86_avx2_pmovzxdq: // llvm.x86.avx2.pmovzxdq
ResultTy = VectorType::get(IntegerType::get(Context, 64), 4);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
break;
case Intrinsic::x86_avx2_psll_dq: // llvm.x86.avx2.psll.dq
case Intrinsic::x86_avx2_psll_dq_bs: // llvm.x86.avx2.psll.dq.bs
case Intrinsic::x86_avx2_pslli_q: // llvm.x86.avx2.pslli.q
case Intrinsic::x86_avx2_psrl_dq: // llvm.x86.avx2.psrl.dq
case Intrinsic::x86_avx2_psrl_dq_bs: // llvm.x86.avx2.psrl.dq.bs
case Intrinsic::x86_avx2_psrli_q: // llvm.x86.avx2.psrli.q
ResultTy = VectorType::get(IntegerType::get(Context, 64), 4);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 4));
ArgTys.push_back(IntegerType::get(Context, 32));
break;
case Intrinsic::x86_avx2_psll_q: // llvm.x86.avx2.psll.q
case Intrinsic::x86_avx2_psrl_q: // llvm.x86.avx2.psrl.q
ResultTy = VectorType::get(IntegerType::get(Context, 64), 4);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 4));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 2));
break;
case Intrinsic::x86_avx2_vinserti128: // llvm.x86.avx2.vin
serti128
ResultTy = VectorType::get(IntegerType::get(Context, 64), 4);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 4));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 2));
ArgTys.push_back(IntegerType::get(Context, 8));
break;
case Intrinsic::x86_avx2_psllv_q_256: // llvm.x86.avx2.psl
lv.q.256
case Intrinsic::x86_avx2_psrlv_q_256: // llvm.x86.avx2.psr
lv.q.256
ResultTy = VectorType::get(IntegerType::get(Context, 64), 4);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 4));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 4));
break;
case Intrinsic::x86_avx2_vperm2i128: // llvm.x86.avx2.vperm2i128
ResultTy = VectorType::get(IntegerType::get(Context, 64), 4);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 4));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 4));
ArgTys.push_back(IntegerType::get(Context, 8));
break;
case Intrinsic::x86_xop_vpcmov_256: // llvm.x86.xop.vpcmov.256
ResultTy = VectorType::get(IntegerType::get(Context, 64), 4);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 4));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 4));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 4));
break;
case Intrinsic::x86_avx2_pmovsxwq: // llvm.x86.avx2.pmovsxwq
case Intrinsic::x86_avx2_pmovzxwq: // llvm.x86.avx2.pmovzxwq
ResultTy = VectorType::get(IntegerType::get(Context, 64), 4);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
break;
case Intrinsic::x86_avx2_pmul_dq: // llvm.x86.avx2.pmul.dq
case Intrinsic::x86_avx2_pmulu_dq: // llvm.x86.avx2.pmulu.dq
ResultTy = VectorType::get(IntegerType::get(Context, 64), 4);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 8));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 8));
break;
case Intrinsic::x86_avx_vbroadcast_ss_256: // llvm.x86.avx.vbro
adcast.ss.256
case Intrinsic::x86_avx_vbroadcastf128_ps_256: // llvm.x86.
avx.vbroadcastf128.ps.256
ResultTy = VectorType::get(Type::getFloatTy(Context), 8);
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
break;
case Intrinsic::x86_avx_maskload_ps_256: // llvm.x86.avx.mask
load.ps.256
ResultTy = VectorType::get(Type::getFloatTy(Context), 8);
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 8));
break;
case Intrinsic::x86_avx2_vbroadcast_ss_ps_256: // llvm.x86.
avx2.vbroadcast.ss.ps.256
ResultTy = VectorType::get(Type::getFloatTy(Context), 8);
ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
break;
case Intrinsic::x86_avx_rcp_ps_256: // llvm.x86.avx.rcp.ps.256
case Intrinsic::x86_avx_rsqrt_ps_256: // llvm.x86.avx.rsqr
t.ps.256
case Intrinsic::x86_avx_sqrt_ps_256: // llvm.x86.avx.sqrt.ps.256
case Intrinsic::x86_xop_vfrcz_ps_256: // llvm.x86.xop.vfrc
z.ps.256
ResultTy = VectorType::get(Type::getFloatTy(Context), 8);
ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 8));
break;
case Intrinsic::x86_avx_round_ps_256: // llvm.x86.avx.roun
d.ps.256
ResultTy = VectorType::get(Type::getFloatTy(Context), 8);
ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 8));
ArgTys.push_back(IntegerType::get(Context, 32));
break;
case Intrinsic::x86_avx_vinsertf128_ps_256: // llvm.x86.avx.vins
ertf128.ps.256
ResultTy = VectorType::get(Type::getFloatTy(Context), 8);
ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 8));
ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
ArgTys.push_back(IntegerType::get(Context, 8));
break;
case Intrinsic::x86_avx2_permps: // llvm.x86.avx2.permps
case Intrinsic::x86_avx_addsub_ps_256: // llvm.x86.avx.adds
ub.ps.256
case Intrinsic::x86_avx_hadd_ps_256: // llvm.x86.avx.hadd.ps.256
case Intrinsic::x86_avx_hsub_ps_256: // llvm.x86.avx.hsub.ps.256
case Intrinsic::x86_avx_max_ps_256: // llvm.x86.avx.max.ps.256
case Intrinsic::x86_avx_min_ps_256: // llvm.x86.avx.min.ps.256
ResultTy = VectorType::get(Type::getFloatTy(Context), 8);
ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 8));
ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 8));
break;
case Intrinsic::x86_avx_blend_ps_256: // llvm.x86.avx.blen
d.ps.256
case Intrinsic::x86_avx_dp_ps_256: // llvm.x86.avx.dp.ps.256
ResultTy = VectorType::get(Type::getFloatTy(Context), 8);
ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 8));
ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 8));
ArgTys.push_back(IntegerType::get(Context, 32));
break;
case Intrinsic::x86_avx_cmp_ps_256: // llvm.x86.avx.cmp.ps.256
case Intrinsic::x86_avx_vperm2f128_ps_256: // llvm.x86.avx.vper
m2f128.ps.256
ResultTy = VectorType::get(Type::getFloatTy(Context), 8);
ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 8));
ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 8));
ArgTys.push_back(IntegerType::get(Context, 8));
break;
case Intrinsic::x86_avx_blendv_ps_256: // llvm.x86.avx.blen
dv.ps.256
case Intrinsic::x86_fma4_vfmadd_ps_256: // llvm.x86.fma4.vfm
add.ps.256
case Intrinsic::x86_fma4_vfmaddsub_ps_256: // llvm.x86.fma4.vfm
addsub.ps.256
case Intrinsic::x86_fma4_vfmsub_ps_256: // llvm.x86.fma4.vfm
sub.ps.256
case Intrinsic::x86_fma4_vfmsubadd_ps_256: // llvm.x86.fma4.vfm
subadd.ps.256
case Intrinsic::x86_fma4_vfnmadd_ps_256: // llvm.x86.fma4.vfn
madd.ps.256
case Intrinsic::x86_fma4_vfnmsub_ps_256: // llvm.x86.fma4.vfn
msub.ps.256
ResultTy = VectorType::get(Type::getFloatTy(Context), 8);
ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 8));
ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 8));
ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 8));
break;
case Intrinsic::x86_xop_vpermil2ps_256: // llvm.x86.xop.vper
mil2ps.256
ResultTy = VectorType::get(Type::getFloatTy(Context), 8);
ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 8));
ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 8));
ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 8));
ArgTys.push_back(IntegerType::get(Context, 8));
break;
case Intrinsic::x86_avx_vpermilvar_ps_256: // llvm.x86.avx.vper
milvar.ps.256
ResultTy = VectorType::get(Type::getFloatTy(Context), 8);
ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 8));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 8));
break;
case Intrinsic::x86_vcvtph2ps_256: // llvm.x86.vcvtph2ps.256
ResultTy = VectorType::get(Type::getFloatTy(Context), 8);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
break;
case Intrinsic::x86_avx_cvtdq2_ps_256: // llvm.x86.avx.cvtd
q2.ps.256
ResultTy = VectorType::get(Type::getFloatTy(Context), 8);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 8));
break;
case Intrinsic::ppc_altivec_mfvscr: // llvm.ppc.altivec.mfvscr
ResultTy = VectorType::get(IntegerType::get(Context, 16), 8);
break;
case Intrinsic::ppc_altivec_lvehx: // llvm.ppc.altivec.lvehx
ResultTy = VectorType::get(IntegerType::get(Context, 16), 8);
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
break;
case Intrinsic::ppc_altivec_vupkhsb: // llvm.ppc.altivec.vupkhsb
case Intrinsic::ppc_altivec_vupklsb: // llvm.ppc.altivec.vupklsb
case Intrinsic::x86_sse41_pmovsxbw: // llvm.x86.sse41.pmovsxbw
case Intrinsic::x86_sse41_pmovzxbw: // llvm.x86.sse41.pmovzxbw
case Intrinsic::x86_xop_vphaddbw: // llvm.x86.xop.vphaddbw
case Intrinsic::x86_xop_vphaddubw: // llvm.x86.xop.vphaddubw
case Intrinsic::x86_xop_vphsubbw: // llvm.x86.xop.vphsubbw
ResultTy = VectorType::get(IntegerType::get(Context, 16), 8);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
break;
case Intrinsic::ppc_altivec_vmulesb: // llvm.ppc.altivec.vmulesb
case Intrinsic::ppc_altivec_vmuleub: // llvm.ppc.altivec.vmuleub
case Intrinsic::ppc_altivec_vmulosb: // llvm.ppc.altivec.vmulosb
case Intrinsic::ppc_altivec_vmuloub: // llvm.ppc.altivec.vmuloub
case Intrinsic::x86_ssse3_pmadd_ub_sw_128: // llvm.x86.ssse3.pm
add.ub.sw.128
ResultTy = VectorType::get(IntegerType::get(Context, 16), 8);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
break;
case Intrinsic::x86_sse41_mpsadbw: // llvm.x86.sse41.mpsadbw
ResultTy = VectorType::get(IntegerType::get(Context, 16), 8);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
ArgTys.push_back(IntegerType::get(Context, 32));
break;
case Intrinsic::x86_vcvtps2ph_128: // llvm.x86.vcvtps2ph.128
ResultTy = VectorType::get(IntegerType::get(Context, 16), 8);
ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
ArgTys.push_back(IntegerType::get(Context, 32));
break;
case Intrinsic::ppc_altivec_vpkpx: // llvm.ppc.altivec.vpkpx
case Intrinsic::ppc_altivec_vpkswus: // llvm.ppc.altivec.vpkswus
case Intrinsic::ppc_altivec_vpkuwus: // llvm.ppc.altivec.vpkuwus
case Intrinsic::x86_sse2_packssdw_128: // llvm.x86.sse2.pac
kssdw.128
case Intrinsic::x86_sse41_packusdw: // llvm.x86.sse41.packusdw
ResultTy = VectorType::get(IntegerType::get(Context, 16), 8);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
break;
case Intrinsic::x86_vcvtps2ph_256: // llvm.x86.vcvtps2ph.256
ResultTy = VectorType::get(IntegerType::get(Context, 16), 8);
ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 8));
ArgTys.push_back(IntegerType::get(Context, 32));
break;
case Intrinsic::x86_avx2_pbroadcastw_128: // llvm.x86.avx2.pbr
oadcastw.128
case Intrinsic::x86_sse41_phminposuw: // llvm.x86.sse41.ph
minposuw
case Intrinsic::x86_ssse3_pabs_w_128: // llvm.x86.ssse3.pa
bs.w.128
ResultTy = VectorType::get(IntegerType::get(Context, 16), 8);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
break;
case Intrinsic::spu_si_ahi: // llvm.spu.si.ahi
case Intrinsic::spu_si_andhi: // llvm.spu.si.andhi
case Intrinsic::spu_si_ceqhi: // llvm.spu.si.ceqhi
case Intrinsic::spu_si_cgthi: // llvm.spu.si.cgthi
case Intrinsic::spu_si_clgthi: // llvm.spu.si.clgthi
case Intrinsic::spu_si_fsmbi: // llvm.spu.si.fsmbi
case Intrinsic::spu_si_orhi: // llvm.spu.si.orhi
case Intrinsic::spu_si_sfhi: // llvm.spu.si.sfhi
case Intrinsic::spu_si_xorhi: // llvm.spu.si.xorhi
ResultTy = VectorType::get(IntegerType::get(Context, 16), 8);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
ArgTys.push_back(IntegerType::get(Context, 16));
break;
case Intrinsic::spu_si_shlqbi: // llvm.spu.si.shlqbi
case Intrinsic::spu_si_shlqby: // llvm.spu.si.shlqby
case Intrinsic::x86_sse2_pslli_w: // llvm.x86.sse2.pslli.w
case Intrinsic::x86_sse2_psrai_w: // llvm.x86.sse2.psrai.w
case Intrinsic::x86_sse2_psrli_w: // llvm.x86.sse2.psrli.w
ResultTy = VectorType::get(IntegerType::get(Context, 16), 8);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
ArgTys.push_back(IntegerType::get(Context, 32));
break;
case Intrinsic::ppc_altivec_vaddshs: // llvm.ppc.altivec.vaddshs
case Intrinsic::ppc_altivec_vadduhs: // llvm.ppc.altivec.vadduhs
case Intrinsic::ppc_altivec_vavgsh: // llvm.ppc.altivec.vavgsh
case Intrinsic::ppc_altivec_vavguh: // llvm.ppc.altivec.vavguh
case Intrinsic::ppc_altivec_vcmpequh: // llvm.ppc.altivec.
vcmpequh
case Intrinsic::ppc_altivec_vcmpgtsh: // llvm.ppc.altivec.
vcmpgtsh
case Intrinsic::ppc_altivec_vcmpgtuh: // llvm.ppc.altivec.
vcmpgtuh
case Intrinsic::ppc_altivec_vmaxsh: // llvm.ppc.altivec.vmaxsh
case Intrinsic::ppc_altivec_vmaxuh: // llvm.ppc.altivec.vmaxuh
case Intrinsic::ppc_altivec_vminsh: // llvm.ppc.altivec.vminsh
case Intrinsic::ppc_altivec_vminuh: // llvm.ppc.altivec.vminuh
case Intrinsic::ppc_altivec_vrlh: // llvm.ppc.altivec.vrlh
case Intrinsic::ppc_altivec_vslh: // llvm.ppc.altivec.vslh
case Intrinsic::ppc_altivec_vsrah: // llvm.ppc.altivec.vsrah
case Intrinsic::ppc_altivec_vsrh: // llvm.ppc.altivec.vsrh
case Intrinsic::ppc_altivec_vsubshs: // llvm.ppc.altivec.vsubshs
case Intrinsic::ppc_altivec_vsubuhs: // llvm.ppc.altivec.vsubuhs
case Intrinsic::spu_si_ah: // llvm.spu.si.ah
case Intrinsic::spu_si_ceqh: // llvm.spu.si.ceqh
case Intrinsic::spu_si_cgth: // llvm.spu.si.cgth
case Intrinsic::spu_si_clgth: // llvm.spu.si.clgth
case Intrinsic::spu_si_sfh: // llvm.spu.si.sfh
case Intrinsic::x86_sse2_padds_w: // llvm.x86.sse2.padds.w
case Intrinsic::x86_sse2_paddus_w: // llvm.x86.sse2.paddus.w
case Intrinsic::x86_sse2_pavg_w: // llvm.x86.sse2.pavg.w
case Intrinsic::x86_sse2_pmaxs_w: // llvm.x86.sse2.pmaxs.w
case Intrinsic::x86_sse2_pmins_w: // llvm.x86.sse2.pmins.w
case Intrinsic::x86_sse2_pmulh_w: // llvm.x86.sse2.pmulh.w
case Intrinsic::x86_sse2_pmulhu_w: // llvm.x86.sse2.pmulhu.w
case Intrinsic::x86_sse2_psll_w: // llvm.x86.sse2.psll.w
case Intrinsic::x86_sse2_psra_w: // llvm.x86.sse2.psra.w
case Intrinsic::x86_sse2_psrl_w: // llvm.x86.sse2.psrl.w
case Intrinsic::x86_sse2_psubs_w: // llvm.x86.sse2.psubs.w
case Intrinsic::x86_sse2_psubus_w: // llvm.x86.sse2.psubus.w
case Intrinsic::x86_sse41_pmaxuw: // llvm.x86.sse41.pmaxuw
case Intrinsic::x86_sse41_pminuw: // llvm.x86.sse41.pminuw
case Intrinsic::x86_ssse3_phadd_sw_128: // llvm.x86.ssse3.ph
add.sw.128
case Intrinsic::x86_ssse3_phadd_w_128: // llvm.x86.ssse3.ph
add.w.128
case Intrinsic::x86_ssse3_phsub_sw_128: // llvm.x86.ssse3.ph
sub.sw.128
case Intrinsic::x86_ssse3_phsub_w_128: // llvm.x86.ssse3.ph
sub.w.128
case Intrinsic::x86_ssse3_pmul_hr_sw_128: // llvm.x86.ssse3.pm
ul.hr.sw.128
case Intrinsic::x86_ssse3_psign_w_128: // llvm.x86.ssse3.ps
ign.w.128
case Intrinsic::x86_xop_vpcomequw: // llvm.x86.xop.vpcomequw
case Intrinsic::x86_xop_vpcomeqw: // llvm.x86.xop.vpcomeqw
case Intrinsic::x86_xop_vpcomfalseuw: // llvm.x86.xop.vpco
mfalseuw
case Intrinsic::x86_xop_vpcomfalsew: // llvm.x86.xop.vpcomfalsew
case Intrinsic::x86_xop_vpcomgeuw: // llvm.x86.xop.vpcomgeuw
case Intrinsic::x86_xop_vpcomgew: // llvm.x86.xop.vpcomgew
case Intrinsic::x86_xop_vpcomgtuw: // llvm.x86.xop.vpcomgtuw
case Intrinsic::x86_xop_vpcomgtw: // llvm.x86.xop.vpcomgtw
case Intrinsic::x86_xop_vpcomleuw: // llvm.x86.xop.vpcomleuw
case Intrinsic::x86_xop_vpcomlew: // llvm.x86.xop.vpcomlew
case Intrinsic::x86_xop_vpcomltuw: // llvm.x86.xop.vpcomltuw
case Intrinsic::x86_xop_vpcomltw: // llvm.x86.xop.vpcomltw
case Intrinsic::x86_xop_vpcomneuw: // llvm.x86.xop.vpcomneuw
case Intrinsic::x86_xop_vpcomnew: // llvm.x86.xop.vpcomnew
case Intrinsic::x86_xop_vpcomtrueuw: // llvm.x86.xop.vpcomtrueuw
case Intrinsic::x86_xop_vpcomtruew: // llvm.x86.xop.vpcomtruew
case Intrinsic::x86_xop_vprotw: // llvm.x86.xop.vprotw
case Intrinsic::x86_xop_vpshaw: // llvm.x86.xop.vpshaw
case Intrinsic::x86_xop_vpshlw: // llvm.x86.xop.vpshlw
ResultTy = VectorType::get(IntegerType::get(Context, 16), 8);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
break;
case Intrinsic::x86_sse41_pblendw: // llvm.x86.sse41.pblendw
ResultTy = VectorType::get(IntegerType::get(Context, 16), 8);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
ArgTys.push_back(IntegerType::get(Context, 32));
break;
case Intrinsic::ppc_altivec_vmhaddshs: // llvm.ppc.altivec.
vmhaddshs
case Intrinsic::ppc_altivec_vmhraddshs: // llvm.ppc.altivec.
vmhraddshs
case Intrinsic::ppc_altivec_vmladduhm: // llvm.ppc.altivec.
vmladduhm
case Intrinsic::x86_xop_vpmacssww: // llvm.x86.xop.vpmacssww
case Intrinsic::x86_xop_vpmacsww: // llvm.x86.xop.vpmacsww
ResultTy = VectorType::get(IntegerType::get(Context, 16), 8);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
break;
case Intrinsic::x86_avx2_maskload_d_256: // llvm.x86.avx2.mas
kload.d.256
ResultTy = VectorType::get(IntegerType::get(Context, 32), 8);
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 8));
break;
case Intrinsic::x86_avx2_pmadd_wd: // llvm.x86.avx2.pmadd.wd
ResultTy = VectorType::get(IntegerType::get(Context, 32), 8);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 16));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 16));
break;
case Intrinsic::x86_avx2_pmovsxbd: // llvm.x86.avx2.pmovsxbd
case Intrinsic::x86_avx2_pmovzxbd: // llvm.x86.avx2.pmovzxbd
ResultTy = VectorType::get(IntegerType::get(Context, 32), 8);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
break;
case Intrinsic::x86_avx2_pbroadcastd_256: // llvm.x86.avx2.pbr
oadcastd.256
ResultTy = VectorType::get(IntegerType::get(Context, 32), 8);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
break;
case Intrinsic::x86_avx_cvt_ps2dq_256: // llvm.x86.avx.cvt.
ps2dq.256
case Intrinsic::x86_avx_cvtt_ps2dq_256: // llvm.x86.avx.cvtt
.ps2dq.256
ResultTy = VectorType::get(IntegerType::get(Context, 32), 8);
ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 8));
break;
case Intrinsic::x86_avx2_pmovsxwd: // llvm.x86.avx2.pmovsxwd
case Intrinsic::x86_avx2_pmovzxwd: // llvm.x86.avx2.pmovzxwd
ResultTy = VectorType::get(IntegerType::get(Context, 32), 8);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
break;
case Intrinsic::x86_avx2_pabs_d: // llvm.x86.avx2.pabs.d
ResultTy = VectorType::get(IntegerType::get(Context, 32), 8);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 8));
break;
case Intrinsic::x86_avx2_pslli_d: // llvm.x86.avx2.pslli.d
case Intrinsic::x86_avx2_psrai_d: // llvm.x86.avx2.psrai.d
case Intrinsic::x86_avx2_psrli_d: // llvm.x86.avx2.psrli.d
ResultTy = VectorType::get(IntegerType::get(Context, 32), 8);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 8));
ArgTys.push_back(IntegerType::get(Context, 32));
break;
case Intrinsic::x86_avx2_psll_d: // llvm.x86.avx2.psll.d
case Intrinsic::x86_avx2_psra_d: // llvm.x86.avx2.psra.d
case Intrinsic::x86_avx2_psrl_d: // llvm.x86.avx2.psrl.d
ResultTy = VectorType::get(IntegerType::get(Context, 32), 8);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 8));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
break;
case Intrinsic::x86_avx_vinsertf128_si_256: // llvm.x86.avx.vins
ertf128.si.256
ResultTy = VectorType::get(IntegerType::get(Context, 32), 8);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 8));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
ArgTys.push_back(IntegerType::get(Context, 8));
break;
case Intrinsic::x86_avx2_permd: // llvm.x86.avx2.permd
case Intrinsic::x86_avx2_phadd_d: // llvm.x86.avx2.phadd.d
case Intrinsic::x86_avx2_phsub_d: // llvm.x86.avx2.phsub.d
case Intrinsic::x86_avx2_pmaxs_d: // llvm.x86.avx2.pmaxs.d
case Intrinsic::x86_avx2_pmaxu_d: // llvm.x86.avx2.pmaxu.d
case Intrinsic::x86_avx2_pmins_d: // llvm.x86.avx2.pmins.d
case Intrinsic::x86_avx2_pminu_d: // llvm.x86.avx2.pminu.d
case Intrinsic::x86_avx2_psign_d: // llvm.x86.avx2.psign.d
case Intrinsic::x86_avx2_psllv_d_256: // llvm.x86.avx2.psl
lv.d.256
case Intrinsic::x86_avx2_psrav_d_256: // llvm.x86.avx2.psr
av.d.256
case Intrinsic::x86_avx2_psrlv_d_256: // llvm.x86.avx2.psr
lv.d.256
ResultTy = VectorType::get(IntegerType::get(Context, 32), 8);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 8));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 8));
break;
case Intrinsic::x86_avx2_pblendd_256: // llvm.x86.avx2.pbl
endd.256
ResultTy = VectorType::get(IntegerType::get(Context, 32), 8);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 8));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 8));
ArgTys.push_back(IntegerType::get(Context, 32));
break;
case Intrinsic::x86_avx_vperm2f128_si_256: // llvm.x86.avx.vper
m2f128.si.256
ResultTy = VectorType::get(IntegerType::get(Context, 32), 8);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 8));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 8));
ArgTys.push_back(IntegerType::get(Context, 8));
break;
case Intrinsic::arm_neon_vtbl1: // llvm.arm.neon.vtbl1
ResultTy = VectorType::get(IntegerType::get(Context, 8), 8);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));
break;
case Intrinsic::arm_neon_vtbl2: // llvm.arm.neon.vtbl2
case Intrinsic::arm_neon_vtbx1: // llvm.arm.neon.vtbx1
ResultTy = VectorType::get(IntegerType::get(Context, 8), 8);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));
break;
case Intrinsic::arm_neon_vtbl3: // llvm.arm.neon.vtbl3
case Intrinsic::arm_neon_vtbx2: // llvm.arm.neon.vtbx2
ResultTy = VectorType::get(IntegerType::get(Context, 8), 8);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));
break;
case Intrinsic::arm_neon_vtbl4: // llvm.arm.neon.vtbl4
case Intrinsic::arm_neon_vtbx3: // llvm.arm.neon.vtbx3
ResultTy = VectorType::get(IntegerType::get(Context, 8), 8);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));
break;
case Intrinsic::arm_neon_vtbx4: // llvm.arm.neon.vtbx4
ResultTy = VectorType::get(IntegerType::get(Context, 8), 8);
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));
ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));
break;
case Intrinsic::x86_sse_cvtpd2pi: // llvm.x86.sse.cvtpd2pi
case Intrinsic::x86_sse_cvttpd2pi: // llvm.x86.sse.cvttpd2pi
ResultTy = Type::getX86_MMXTy(Context);
ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
break;
case Intrinsic::x86_sse_cvtps2pi: // llvm.x86.sse.cvtps2pi
case Intrinsic::x86_sse_cvttps2pi: // llvm.x86.sse.cvttps2pi
ResultTy = Type::getX86_MMXTy(Context);
ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
break;
case Intrinsic::x86_3dnow_pf2id: // llvm.x86.3dnow.pf2id
case Intrinsic::x86_3dnow_pfrcp: // llvm.x86.3dnow.pfrcp
case Intrinsic::x86_3dnow_pfrsqrt: // llvm.x86.3dnow.pfrsqrt
case Intrinsic::x86_3dnow_pi2fd: // llvm.x86.3dnow.pi2fd
case Intrinsic::x86_3dnowa_pf2iw: // llvm.x86.3dnowa.pf2iw
case Intrinsic::x86_3dnowa_pi2fw: // llvm.x86.3dnowa.pi2fw
case Intrinsic::x86_3dnowa_pswapd: // llvm.x86.3dnowa.pswapd
case Intrinsic::x86_ssse3_pabs_b: // llvm.x86.ssse3.pabs.b
case Intrinsic::x86_ssse3_pabs_d: // llvm.x86.ssse3.pabs.d
case Intrinsic::x86_ssse3_pabs_w: // llvm.x86.ssse3.pabs.w
ResultTy = Type::getX86_MMXTy(Context);
ArgTys.push_back(Type::getX86_MMXTy(Context));
break;
case Intrinsic::x86_mmx_pslli_d: // llvm.x86.mmx.pslli.d
case Intrinsic::x86_mmx_pslli_q: // llvm.x86.mmx.pslli.q
case Intrinsic::x86_mmx_pslli_w: // llvm.x86.mmx.pslli.w
case Intrinsic::x86_mmx_psrai_d: // llvm.x86.mmx.psrai.d
case Intrinsic::x86_mmx_psrai_w: // llvm.x86.mmx.psrai.w
case Intrinsic::x86_mmx_psrli_d: // llvm.x86.mmx.psrli.d
case Intrinsic::x86_mmx_psrli_q: // llvm.x86.mmx.psrli.q
case Intrinsic::x86_mmx_psrli_w: // llvm.x86.mmx.psrli.w
ResultTy = Type::getX86_MMXTy(Context);
ArgTys.push_back(Type::getX86_MMXTy(Context));
ArgTys.push_back(IntegerType::get(Context, 32));
break;
case Intrinsic::x86_mmx_pinsr_w: // llvm.x86.mmx.pinsr.w
ResultTy = Type::getX86_MMXTy(Context);
ArgTys.push_back(Type::getX86_MMXTy(Context));
ArgTys.push_back(IntegerType::get(Context, 32));
ArgTys.push_back(IntegerType::get(Context, 32));
break;
case Intrinsic::x86_sse_pshuf_w: // llvm.x86.sse.pshuf.w
ResultTy = Type::getX86_MMXTy(Context);
ArgTys.push_back(Type::getX86_MMXTy(Context));
ArgTys.push_back(IntegerType::get(Context, 8));
break;
case Intrinsic::x86_3dnow_pavgusb: // llvm.x86.3dnow.pavgusb
case Intrinsic::x86_3dnow_pfacc: // llvm.x86.3dnow.pfacc
case Intrinsic::x86_3dnow_pfadd: // llvm.x86.3dnow.pfadd
case Intrinsic::x86_3dnow_pfcmpeq: // llvm.x86.3dnow.pfcmpeq
case Intrinsic::x86_3dnow_pfcmpge: // llvm.x86.3dnow.pfcmpge
case Intrinsic::x86_3dnow_pfcmpgt: // llvm.x86.3dnow.pfcmpgt
case Intrinsic::x86_3dnow_pfmax: // llvm.x86.3dnow.pfmax
case Intrinsic::x86_3dnow_pfmin: // llvm.x86.3dnow.pfmin
case Intrinsic::x86_3dnow_pfmul: // llvm.x86.3dnow.pfmul
case Intrinsic::x86_3dnow_pfrcpit1: // llvm.x86.3dnow.pfrcpit1
case Intrinsic::x86_3dnow_pfrcpit2: // llvm.x86.3dnow.pfrcpit2
case Intrinsic::x86_3dnow_pfrsqit1: // llvm.x86.3dnow.pfrsqit1
case Intrinsic::x86_3dnow_pfsub: // llvm.x86.3dnow.pfsub
case Intrinsic::x86_3dnow_pfsubr: // llvm.x86.3dnow.pfsubr
case Intrinsic::x86_3dnow_pmulhrw: // llvm.x86.3dnow.pmulhrw
case Intrinsic::x86_3dnowa_pfnacc: // llvm.x86.3dnowa.pfnacc
case Intrinsic::x86_3dnowa_pfpnacc: // llvm.x86.3dnowa.pfpnacc
case Intrinsic::x86_mmx_packssdw: // llvm.x86.mmx.packssdw
case Intrinsic::x86_mmx_packsswb: // llvm.x86.mmx.packsswb
case Intrinsic::x86_mmx_packuswb: // llvm.x86.mmx.packuswb
case Intrinsic::x86_mmx_padd_b: // llvm.x86.mmx.padd.b
case Intrinsic::x86_mmx_padd_d: // llvm.x86.mmx.padd.d
case Intrinsic::x86_mmx_padd_q: // llvm.x86.mmx.padd.q
case Intrinsic::x86_mmx_padd_w: // llvm.x86.mmx.padd.w
case Intrinsic::x86_mmx_padds_b: // llvm.x86.mmx.padds.b
case Intrinsic::x86_mmx_padds_w: // llvm.x86.mmx.padds.w
case Intrinsic::x86_mmx_paddus_b: // llvm.x86.mmx.paddus.b
case Intrinsic::x86_mmx_paddus_w: // llvm.x86.mmx.paddus.w
case Intrinsic::x86_mmx_pand: // llvm.x86.mmx.pand
case Intrinsic::x86_mmx_pandn: // llvm.x86.mmx.pandn
case Intrinsic::x86_mmx_pavg_b: // llvm.x86.mmx.pavg.b
case Intrinsic::x86_mmx_pavg_w: // llvm.x86.mmx.pavg.w
case Intrinsic::x86_mmx_pcmpeq_b: // llvm.x86.mmx.pcmpeq.b
case Intrinsic::x86_mmx_pcmpeq_d: // llvm.x86.mmx.pcmpeq.d
case Intrinsic::x86_mmx_pcmpeq_w: // llvm.x86.mmx.pcmpeq.w
case Intrinsic::x86_mmx_pcmpgt_b: // llvm.x86.mmx.pcmpgt.b
case Intrinsic::x86_mmx_pcmpgt_d: // llvm.x86.mmx.pcmpgt.d
case Intrinsic::x86_mmx_pcmpgt_w: // llvm.x86.mmx.pcmpgt.w
case Intrinsic::x86_mmx_pmadd_wd: // llvm.x86.mmx.pmadd.wd
case Intrinsic::x86_mmx_pmaxs_w: // llvm.x86.mmx.pmaxs.w
case Intrinsic::x86_mmx_pmaxu_b: // llvm.x86.mmx.pmaxu.b
case Intrinsic::x86_mmx_pmins_w: // llvm.x86.mmx.pmins.w
case Intrinsic::x86_mmx_pminu_b: // llvm.x86.mmx.pminu.b
case Intrinsic::x86_mmx_pmulh_w: // llvm.x86.mmx.pmulh.w
case Intrinsic::x86_mmx_pmulhu_w: // llvm.x86.mmx.pmulhu.w
case Intrinsic::x86_mmx_pmull_w: // llvm.x86.mmx.pmull.w
case Intrinsic::x86_mmx_pmulu_dq: // llvm.x86.mmx.pmulu.dq
case Intrinsic::x86_mmx_por: // llvm.x86.mmx.por
case Intrinsic::x86_mmx_psad_bw: // llvm.x86.mmx.psad.bw
case Intrinsic::x86_mmx_psll_d: // llvm.x86.mmx.psll.d
case Intrinsic::x86_mmx_psll_q: // llvm.x86.mmx.psll.q
case Intrinsic::x86_mmx_psll_w: // llvm.x86.mmx.psll.w
case Intrinsic::x86_mmx_psra_d: // llvm.x86.mmx.psra.d
case Intrinsic::x86_mmx_psra_w: // llvm.x86.mmx.psra.w
case Intrinsic::x86_mmx_psrl_d: // llvm.x86.mmx.psrl.d
case Intrinsic::x86_mmx_psrl_q: // llvm.x86.mmx.psrl.q
case Intrinsic::x86_mmx_psrl_w: // llvm.x86.mmx.psrl.w
case Intrinsic::x86_mmx_psub_b: // llvm.x86.mmx.psub.b
case Intrinsic::x86_mmx_psub_d: // llvm.x86.mmx.psub.d
case Intrinsic::x86_mmx_psub_q: // llvm.x86.mmx.psub.q
case Intrinsic::x86_mmx_psub_w: // llvm.x86.mmx.psub.w
case Intrinsic::x86_mmx_psubs_b: // llvm.x86.mmx.psubs.b
case Intrinsic::x86_mmx_psubs_w: // llvm.x86.mmx.psubs.w
case Intrinsic::x86_mmx_psubus_b: // llvm.x86.mmx.psubus.b
case Intrinsic::x86_mmx_psubus_w: // llvm.x86.mmx.psubus.w
case Intrinsic::x86_mmx_punpckhbw: // llvm.x86.mmx.punpckhbw
case Intrinsic::x86_mmx_punpckhdq: // llvm.x86.mmx.punpckhdq
case Intrinsic::x86_mmx_punpckhwd: // llvm.x86.mmx.punpckhwd
case Intrinsic::x86_mmx_punpcklbw: // llvm.x86.mmx.punpcklbw
case Intrinsic::x86_mmx_punpckldq: // llvm.x86.mmx.punpckldq
case Intrinsic::x86_mmx_punpcklwd: // llvm.x86.mmx.punpcklwd
case Intrinsic::x86_mmx_pxor: // llvm.x86.mmx.pxor
case Intrinsic::x86_ssse3_phadd_d: // llvm.x86.ssse3.phadd.d
case Intrinsic::x86_ssse3_phadd_sw: // llvm.x86.ssse3.phadd.sw
case Intrinsic::x86_ssse3_phadd_w: // llvm.x86.ssse3.phadd.w
case Intrinsic::x86_ssse3_phsub_d: // llvm.x86.ssse3.phsub.d
case Intrinsic::x86_ssse3_phsub_sw: // llvm.x86.ssse3.phsub.sw
case Intrinsic::x86_ssse3_phsub_w: // llvm.x86.ssse3.phsub.w
case Intrinsic::x86_ssse3_pmadd_ub_sw: // llvm.x86.ssse3.pm
add.ub.sw
case Intrinsic::x86_ssse3_pmul_hr_sw: // llvm.x86.ssse3.pm
ul.hr.sw
case Intrinsic::x86_ssse3_pshuf_b: // llvm.x86.ssse3.pshuf.b
case Intrinsic::x86_ssse3_psign_b: // llvm.x86.ssse3.psign.b
case Intrinsic::x86_ssse3_psign_d: // llvm.x86.ssse3.psign.d
case Intrinsic::x86_ssse3_psign_w: // llvm.x86.ssse3.psign.w
ResultTy = Type::getX86_MMXTy(Context);
ArgTys.push_back(Type::getX86_MMXTy(Context));
ArgTys.push_back(Type::getX86_MMXTy(Context));
break;
case Intrinsic::x86_mmx_palignr_b: // llvm.x86.mmx.palignr.b
ResultTy = Type::getX86_MMXTy(Context);
ArgTys.push_back(Type::getX86_MMXTy(Context));
ArgTys.push_back(Type::getX86_MMXTy(Context));
ArgTys.push_back(IntegerType::get(Context, 8));
break;
}
#endif
// Add parameter attributes that are not common to all intrinsics.
#ifdef GET_INTRINSIC_ATTRIBUTES
AttrListPtr Intrinsic::getAttributes(ID id) {
static const uint8_t IntrinsicsToAttributesMap[] = {
1, // llvm.adjust.trampoline
2, // llvm.annotation
2, // llvm.arm.cdp
2, // llvm.arm.cdp2
3, // llvm.arm.get.fpscr
1, // llvm.arm.ldrexd
2, // llvm.arm.mcr
2, // llvm.arm.mcr2 2, // llvm.arm.mcr2
2, // llvm.arm.mcrr 2, // llvm.arm.mcrr
2, // llvm.arm.mcrr2 2, // llvm.arm.mcrr2
2, // llvm.arm.mrc 2, // llvm.arm.mrc
2, // llvm.arm.mrc2 2, // llvm.arm.mrc2
3, // llvm.arm.neon.vabds 3, // llvm.arm.neon.vabds
3, // llvm.arm.neon.vabdu 3, // llvm.arm.neon.vabdu
3, // llvm.arm.neon.vabs 3, // llvm.arm.neon.vabs
3, // llvm.arm.neon.vacged 3, // llvm.arm.neon.vacged
3, // llvm.arm.neon.vacgeq 3, // llvm.arm.neon.vacgeq
3, // llvm.arm.neon.vacgtd 3, // llvm.arm.neon.vacgtd
3, // llvm.arm.neon.vacgtq 3, // llvm.arm.neon.vacgtq
3, // llvm.arm.neon.vaddhn 3, // llvm.arm.neon.vaddhn
3, // llvm.arm.neon.vbsl
3, // llvm.arm.neon.vcls 3, // llvm.arm.neon.vcls
3, // llvm.arm.neon.vclz 3, // llvm.arm.neon.vclz
3, // llvm.arm.neon.vcnt 3, // llvm.arm.neon.vcnt
3, // llvm.arm.neon.vcvtfp2fxs 3, // llvm.arm.neon.vcvtfp2fxs
3, // llvm.arm.neon.vcvtfp2fxu 3, // llvm.arm.neon.vcvtfp2fxu
3, // llvm.arm.neon.vcvtfp2hf 3, // llvm.arm.neon.vcvtfp2hf
3, // llvm.arm.neon.vcvtfxs2fp 3, // llvm.arm.neon.vcvtfxs2fp
3, // llvm.arm.neon.vcvtfxu2fp 3, // llvm.arm.neon.vcvtfxu2fp
3, // llvm.arm.neon.vcvthf2fp 3, // llvm.arm.neon.vcvthf2fp
3, // llvm.arm.neon.vhadds 3, // llvm.arm.neon.vhadds
skipping to change at line 23261 skipping to change at line 23035
2, // llvm.convertsif 2, // llvm.convertsif
2, // llvm.convertss 2, // llvm.convertss
2, // llvm.convertsu 2, // llvm.convertsu
2, // llvm.convertuif 2, // llvm.convertuif
2, // llvm.convertus 2, // llvm.convertus
2, // llvm.convertuu 2, // llvm.convertuu
1, // llvm.cos 1, // llvm.cos
3, // llvm.ctlz 3, // llvm.ctlz
3, // llvm.ctpop 3, // llvm.ctpop
3, // llvm.cttz 3, // llvm.cttz
2, // llvm.cuda.syncthreads
3, // llvm.dbg.declare 3, // llvm.dbg.declare
3, // llvm.dbg.value 3, // llvm.dbg.value
2, // llvm.debugtrap
3, // llvm.donothing
2, // llvm.eh.dwarf.cfa 2, // llvm.eh.dwarf.cfa
2, // llvm.eh.return.i32 2, // llvm.eh.return.i32
2, // llvm.eh.return.i64 2, // llvm.eh.return.i64
3, // llvm.eh.sjlj.callsite 3, // llvm.eh.sjlj.callsite
2, // llvm.eh.sjlj.functioncontext 2, // llvm.eh.sjlj.functioncontext
2, // llvm.eh.sjlj.longjmp 4, // llvm.eh.sjlj.longjmp
3, // llvm.eh.sjlj.lsda 3, // llvm.eh.sjlj.lsda
2, // llvm.eh.sjlj.setjmp 2, // llvm.eh.sjlj.setjmp
3, // llvm.eh.typeid.for 3, // llvm.eh.typeid.for
2, // llvm.eh.unwind.init 2, // llvm.eh.unwind.init
1, // llvm.exp 1, // llvm.exp
1, // llvm.exp2 1, // llvm.exp2
3, // llvm.expect 3, // llvm.expect
1, // llvm.fabs
1, // llvm.floor
2, // llvm.flt.rounds 2, // llvm.flt.rounds
3, // llvm.fma 3, // llvm.fma
3, // llvm.fmuladd
3, // llvm.frameaddress 3, // llvm.frameaddress
1, // llvm.gcread 1, // llvm.gcread
2, // llvm.gcroot 2, // llvm.gcroot
4, // llvm.gcwrite 5, // llvm.gcwrite
3, // llvm.hexagon.A2.abs 3, // llvm.hexagon.A2.abs
3, // llvm.hexagon.A2.absp 3, // llvm.hexagon.A2.absp
3, // llvm.hexagon.A2.abssat 3, // llvm.hexagon.A2.abssat
3, // llvm.hexagon.A2.add 3, // llvm.hexagon.A2.add
3, // llvm.hexagon.A2.addh.h16.hh 3, // llvm.hexagon.A2.addh.h16.hh
3, // llvm.hexagon.A2.addh.h16.hl 3, // llvm.hexagon.A2.addh.h16.hl
3, // llvm.hexagon.A2.addh.h16.lh 3, // llvm.hexagon.A2.addh.h16.lh
3, // llvm.hexagon.A2.addh.h16.ll 3, // llvm.hexagon.A2.addh.h16.ll
3, // llvm.hexagon.A2.addh.h16.sat.hh 3, // llvm.hexagon.A2.addh.h16.sat.hh
3, // llvm.hexagon.A2.addh.h16.sat.hl 3, // llvm.hexagon.A2.addh.h16.sat.hl
3, // llvm.hexagon.A2.addh.h16.sat.lh 3, // llvm.hexagon.A2.addh.h16.sat.lh
3, // llvm.hexagon.A2.addh.h16.sat.ll 3, // llvm.hexagon.A2.addh.h16.sat.ll
3, // llvm.hexagon.A2.addh.l16.hh
3, // llvm.hexagon.A2.addh.l16.hl 3, // llvm.hexagon.A2.addh.l16.hl
3, // llvm.hexagon.A2.addh.l16.lh
3, // llvm.hexagon.A2.addh.l16.ll 3, // llvm.hexagon.A2.addh.l16.ll
3, // llvm.hexagon.A2.addh.l16.sat.hh
3, // llvm.hexagon.A2.addh.l16.sat.hl 3, // llvm.hexagon.A2.addh.l16.sat.hl
3, // llvm.hexagon.A2.addh.l16.sat.lh
3, // llvm.hexagon.A2.addh.l16.sat.ll 3, // llvm.hexagon.A2.addh.l16.sat.ll
3, // llvm.hexagon.A2.addi 3, // llvm.hexagon.A2.addi
3, // llvm.hexagon.A2.addp 3, // llvm.hexagon.A2.addp
3, // llvm.hexagon.A2.addpsat 3, // llvm.hexagon.A2.addpsat
3, // llvm.hexagon.A2.addsat 3, // llvm.hexagon.A2.addsat
3, // llvm.hexagon.A2.addsp 3, // llvm.hexagon.A2.addsp
3, // llvm.hexagon.A2.and 3, // llvm.hexagon.A2.and
3, // llvm.hexagon.A2.andir 3, // llvm.hexagon.A2.andir
3, // llvm.hexagon.A2.andp 3, // llvm.hexagon.A2.andp
3, // llvm.hexagon.A2.aslh 3, // llvm.hexagon.A2.aslh
skipping to change at line 23334 skipping to change at line 23110
3, // llvm.hexagon.A2.minu 3, // llvm.hexagon.A2.minu
3, // llvm.hexagon.A2.minup 3, // llvm.hexagon.A2.minup
3, // llvm.hexagon.A2.neg 3, // llvm.hexagon.A2.neg
3, // llvm.hexagon.A2.negp 3, // llvm.hexagon.A2.negp
3, // llvm.hexagon.A2.negsat 3, // llvm.hexagon.A2.negsat
3, // llvm.hexagon.A2.not 3, // llvm.hexagon.A2.not
3, // llvm.hexagon.A2.notp 3, // llvm.hexagon.A2.notp
3, // llvm.hexagon.A2.or 3, // llvm.hexagon.A2.or
3, // llvm.hexagon.A2.orir 3, // llvm.hexagon.A2.orir
3, // llvm.hexagon.A2.orp 3, // llvm.hexagon.A2.orp
3, // llvm.hexagon.A2.roundsat
3, // llvm.hexagon.A2.sat 3, // llvm.hexagon.A2.sat
3, // llvm.hexagon.A2.satb 3, // llvm.hexagon.A2.satb
3, // llvm.hexagon.A2.sath 3, // llvm.hexagon.A2.sath
3, // llvm.hexagon.A2.satub 3, // llvm.hexagon.A2.satub
3, // llvm.hexagon.A2.satuh 3, // llvm.hexagon.A2.satuh
3, // llvm.hexagon.A2.sub 3, // llvm.hexagon.A2.sub
3, // llvm.hexagon.A2.subh.h16.hh 3, // llvm.hexagon.A2.subh.h16.hh
3, // llvm.hexagon.A2.subh.h16.hl 3, // llvm.hexagon.A2.subh.h16.hl
3, // llvm.hexagon.A2.subh.h16.lh 3, // llvm.hexagon.A2.subh.h16.lh
3, // llvm.hexagon.A2.subh.h16.ll 3, // llvm.hexagon.A2.subh.h16.ll
skipping to change at line 23378 skipping to change at line 23155
3, // llvm.hexagon.A2.tfr 3, // llvm.hexagon.A2.tfr
3, // llvm.hexagon.A2.tfrih 3, // llvm.hexagon.A2.tfrih
3, // llvm.hexagon.A2.tfril 3, // llvm.hexagon.A2.tfril
3, // llvm.hexagon.A2.tfrp 3, // llvm.hexagon.A2.tfrp
3, // llvm.hexagon.A2.tfrpi 3, // llvm.hexagon.A2.tfrpi
3, // llvm.hexagon.A2.tfrsi 3, // llvm.hexagon.A2.tfrsi
3, // llvm.hexagon.A2.vabsh 3, // llvm.hexagon.A2.vabsh
3, // llvm.hexagon.A2.vabshsat 3, // llvm.hexagon.A2.vabshsat
3, // llvm.hexagon.A2.vabsw 3, // llvm.hexagon.A2.vabsw
3, // llvm.hexagon.A2.vabswsat 3, // llvm.hexagon.A2.vabswsat
3, // llvm.hexagon.A2.vaddb.map
3, // llvm.hexagon.A2.vaddh 3, // llvm.hexagon.A2.vaddh
3, // llvm.hexagon.A2.vaddhs 3, // llvm.hexagon.A2.vaddhs
3, // llvm.hexagon.A2.vaddub 3, // llvm.hexagon.A2.vaddub
3, // llvm.hexagon.A2.vaddubs 3, // llvm.hexagon.A2.vaddubs
3, // llvm.hexagon.A2.vadduhs 3, // llvm.hexagon.A2.vadduhs
3, // llvm.hexagon.A2.vaddw 3, // llvm.hexagon.A2.vaddw
3, // llvm.hexagon.A2.vaddws 3, // llvm.hexagon.A2.vaddws
3, // llvm.hexagon.A2.vavgh 3, // llvm.hexagon.A2.vavgh
3, // llvm.hexagon.A2.vavghcr 3, // llvm.hexagon.A2.vavghcr
3, // llvm.hexagon.A2.vavghr 3, // llvm.hexagon.A2.vavghr
skipping to change at line 23406 skipping to change at line 23184
3, // llvm.hexagon.A2.vavgwr 3, // llvm.hexagon.A2.vavgwr
3, // llvm.hexagon.A2.vcmpbeq 3, // llvm.hexagon.A2.vcmpbeq
3, // llvm.hexagon.A2.vcmpbgtu 3, // llvm.hexagon.A2.vcmpbgtu
3, // llvm.hexagon.A2.vcmpheq 3, // llvm.hexagon.A2.vcmpheq
3, // llvm.hexagon.A2.vcmphgt 3, // llvm.hexagon.A2.vcmphgt
3, // llvm.hexagon.A2.vcmphgtu 3, // llvm.hexagon.A2.vcmphgtu
3, // llvm.hexagon.A2.vcmpweq 3, // llvm.hexagon.A2.vcmpweq
3, // llvm.hexagon.A2.vcmpwgt 3, // llvm.hexagon.A2.vcmpwgt
3, // llvm.hexagon.A2.vcmpwgtu 3, // llvm.hexagon.A2.vcmpwgtu
3, // llvm.hexagon.A2.vconj 3, // llvm.hexagon.A2.vconj
3, // llvm.hexagon.A2.vmaxb
3, // llvm.hexagon.A2.vmaxh 3, // llvm.hexagon.A2.vmaxh
3, // llvm.hexagon.A2.vmaxub 3, // llvm.hexagon.A2.vmaxub
3, // llvm.hexagon.A2.vmaxuh 3, // llvm.hexagon.A2.vmaxuh
3, // llvm.hexagon.A2.vmaxuw 3, // llvm.hexagon.A2.vmaxuw
3, // llvm.hexagon.A2.vmaxw 3, // llvm.hexagon.A2.vmaxw
3, // llvm.hexagon.A2.vminb
3, // llvm.hexagon.A2.vminh 3, // llvm.hexagon.A2.vminh
3, // llvm.hexagon.A2.vminub 3, // llvm.hexagon.A2.vminub
3, // llvm.hexagon.A2.vminuh 3, // llvm.hexagon.A2.vminuh
3, // llvm.hexagon.A2.vminuw 3, // llvm.hexagon.A2.vminuw
3, // llvm.hexagon.A2.vminw 3, // llvm.hexagon.A2.vminw
3, // llvm.hexagon.A2.vnavgh 3, // llvm.hexagon.A2.vnavgh
3, // llvm.hexagon.A2.vnavghcr 3, // llvm.hexagon.A2.vnavghcr
3, // llvm.hexagon.A2.vnavghr 3, // llvm.hexagon.A2.vnavghr
3, // llvm.hexagon.A2.vnavgw 3, // llvm.hexagon.A2.vnavgw
3, // llvm.hexagon.A2.vnavgwcr 3, // llvm.hexagon.A2.vnavgwcr
3, // llvm.hexagon.A2.vnavgwr 3, // llvm.hexagon.A2.vnavgwr
3, // llvm.hexagon.A2.vraddub 3, // llvm.hexagon.A2.vraddub
3, // llvm.hexagon.A2.vraddub.acc 3, // llvm.hexagon.A2.vraddub.acc
3, // llvm.hexagon.A2.vrsadub 3, // llvm.hexagon.A2.vrsadub
3, // llvm.hexagon.A2.vrsadub.acc 3, // llvm.hexagon.A2.vrsadub.acc
3, // llvm.hexagon.A2.vsubb.map
3, // llvm.hexagon.A2.vsubh 3, // llvm.hexagon.A2.vsubh
3, // llvm.hexagon.A2.vsubhs 3, // llvm.hexagon.A2.vsubhs
3, // llvm.hexagon.A2.vsubub 3, // llvm.hexagon.A2.vsubub
3, // llvm.hexagon.A2.vsububs 3, // llvm.hexagon.A2.vsububs
3, // llvm.hexagon.A2.vsubuhs 3, // llvm.hexagon.A2.vsubuhs
3, // llvm.hexagon.A2.vsubw 3, // llvm.hexagon.A2.vsubw
3, // llvm.hexagon.A2.vsubws 3, // llvm.hexagon.A2.vsubws
3, // llvm.hexagon.A2.xor 3, // llvm.hexagon.A2.xor
3, // llvm.hexagon.A2.xorp 3, // llvm.hexagon.A2.xorp
3, // llvm.hexagon.A2.zxtb 3, // llvm.hexagon.A2.zxtb
3, // llvm.hexagon.A2.zxth 3, // llvm.hexagon.A2.zxth
3, // llvm.hexagon.A4.andn 3, // llvm.hexagon.A4.andn
3, // llvm.hexagon.A4.andnp 3, // llvm.hexagon.A4.andnp
3, // llvm.hexagon.A4.bitsplit
3, // llvm.hexagon.A4.bitspliti
3, // llvm.hexagon.A4.boundscheck
3, // llvm.hexagon.A4.cmpbeq
3, // llvm.hexagon.A4.cmpbeqi
3, // llvm.hexagon.A4.cmpbgt
3, // llvm.hexagon.A4.cmpbgti
3, // llvm.hexagon.A4.cmpbgtu
3, // llvm.hexagon.A4.cmpbgtui
3, // llvm.hexagon.A4.cmpheq
3, // llvm.hexagon.A4.cmpheqi
3, // llvm.hexagon.A4.cmphgt
3, // llvm.hexagon.A4.cmphgti
3, // llvm.hexagon.A4.cmphgtu
3, // llvm.hexagon.A4.cmphgtui
3, // llvm.hexagon.A4.combineir 3, // llvm.hexagon.A4.combineir
3, // llvm.hexagon.A4.combineri 3, // llvm.hexagon.A4.combineri
3, // llvm.hexagon.A4.cround.ri 3, // llvm.hexagon.A4.cround.ri
3, // llvm.hexagon.A4.cround.rr 3, // llvm.hexagon.A4.cround.rr
3, // llvm.hexagon.A4.modwrapu 3, // llvm.hexagon.A4.modwrapu
3, // llvm.hexagon.A4.orn 3, // llvm.hexagon.A4.orn
3, // llvm.hexagon.A4.ornp 3, // llvm.hexagon.A4.ornp
3, // llvm.hexagon.A4.rcmpeq 3, // llvm.hexagon.A4.rcmpeq
3, // llvm.hexagon.A4.rcmpeqi 3, // llvm.hexagon.A4.rcmpeqi
3, // llvm.hexagon.A4.rcmpneq 3, // llvm.hexagon.A4.rcmpneq
3, // llvm.hexagon.A4.rcmpneqi 3, // llvm.hexagon.A4.rcmpneqi
3, // llvm.hexagon.A4.round.ri 3, // llvm.hexagon.A4.round.ri
3, // llvm.hexagon.A4.round.ri.sat 3, // llvm.hexagon.A4.round.ri.sat
3, // llvm.hexagon.A4.round.rr 3, // llvm.hexagon.A4.round.rr
3, // llvm.hexagon.A4.round.rr.sat 3, // llvm.hexagon.A4.round.rr.sat
3, // llvm.hexagon.A4.tlbmatch
3, // llvm.hexagon.A4.vcmpbeq.any
3, // llvm.hexagon.A4.vcmpbeqi
3, // llvm.hexagon.A4.vcmpbgt
3, // llvm.hexagon.A4.vcmpbgti
3, // llvm.hexagon.A4.vcmpbgtui
3, // llvm.hexagon.A4.vcmpheqi
3, // llvm.hexagon.A4.vcmphgti
3, // llvm.hexagon.A4.vcmphgtui
3, // llvm.hexagon.A4.vcmpweqi
3, // llvm.hexagon.A4.vcmpwgti
3, // llvm.hexagon.A4.vcmpwgtui
3, // llvm.hexagon.A4.vrmaxh
3, // llvm.hexagon.A4.vrmaxuh
3, // llvm.hexagon.A4.vrmaxuw
3, // llvm.hexagon.A4.vrmaxw
3, // llvm.hexagon.A4.vrminh
3, // llvm.hexagon.A4.vrminuh
3, // llvm.hexagon.A4.vrminuw
3, // llvm.hexagon.A4.vrminw
3, // llvm.hexagon.A5.vaddhubs
3, // llvm.hexagon.C2.all8 3, // llvm.hexagon.C2.all8
3, // llvm.hexagon.C2.and 3, // llvm.hexagon.C2.and
3, // llvm.hexagon.C2.andn 3, // llvm.hexagon.C2.andn
3, // llvm.hexagon.C2.any8 3, // llvm.hexagon.C2.any8
3, // llvm.hexagon.C2.bitsclr 3, // llvm.hexagon.C2.bitsclr
3, // llvm.hexagon.C2.bitsclri 3, // llvm.hexagon.C2.bitsclri
3, // llvm.hexagon.C2.bitsset 3, // llvm.hexagon.C2.bitsset
3, // llvm.hexagon.C2.cmpeq 3, // llvm.hexagon.C2.cmpeq
3, // llvm.hexagon.C2.cmpeqi 3, // llvm.hexagon.C2.cmpeqi
3, // llvm.hexagon.C2.cmpeqp 3, // llvm.hexagon.C2.cmpeqp
skipping to change at line 23500 skipping to change at line 23317
3, // llvm.hexagon.C4.and.or 3, // llvm.hexagon.C4.and.or
3, // llvm.hexagon.C4.and.orn 3, // llvm.hexagon.C4.and.orn
3, // llvm.hexagon.C4.cmplte 3, // llvm.hexagon.C4.cmplte
3, // llvm.hexagon.C4.cmpltei 3, // llvm.hexagon.C4.cmpltei
3, // llvm.hexagon.C4.cmplteu 3, // llvm.hexagon.C4.cmplteu
3, // llvm.hexagon.C4.cmplteui 3, // llvm.hexagon.C4.cmplteui
3, // llvm.hexagon.C4.cmpneq 3, // llvm.hexagon.C4.cmpneq
3, // llvm.hexagon.C4.cmpneqi 3, // llvm.hexagon.C4.cmpneqi
3, // llvm.hexagon.C4.fastcorner9 3, // llvm.hexagon.C4.fastcorner9
3, // llvm.hexagon.C4.fastcorner9.not 3, // llvm.hexagon.C4.fastcorner9.not
3, // llvm.hexagon.C4.nbitsclr
3, // llvm.hexagon.C4.nbitsclri
3, // llvm.hexagon.C4.nbitsset
3, // llvm.hexagon.C4.or.and 3, // llvm.hexagon.C4.or.and
3, // llvm.hexagon.C4.or.andn 3, // llvm.hexagon.C4.or.andn
3, // llvm.hexagon.C4.or.or 3, // llvm.hexagon.C4.or.or
3, // llvm.hexagon.C4.or.orn 3, // llvm.hexagon.C4.or.orn
3, // llvm.hexagon.F2.conv.d2df
3, // llvm.hexagon.F2.conv.d2sf
3, // llvm.hexagon.F2.conv.df2d
3, // llvm.hexagon.F2.conv.df2d.chop
3, // llvm.hexagon.F2.conv.df2sf
3, // llvm.hexagon.F2.conv.df2ud
3, // llvm.hexagon.F2.conv.df2ud.chop
3, // llvm.hexagon.F2.conv.df2uw
3, // llvm.hexagon.F2.conv.df2uw.chop
3, // llvm.hexagon.F2.conv.df2w
3, // llvm.hexagon.F2.conv.df2w.chop
3, // llvm.hexagon.F2.conv.sf2d
3, // llvm.hexagon.F2.conv.sf2d.chop
3, // llvm.hexagon.F2.conv.sf2df
3, // llvm.hexagon.F2.conv.sf2ud
3, // llvm.hexagon.F2.conv.sf2ud.chop
3, // llvm.hexagon.F2.conv.sf2uw
3, // llvm.hexagon.F2.conv.sf2uw.chop
3, // llvm.hexagon.F2.conv.sf2w
3, // llvm.hexagon.F2.conv.sf2w.chop
3, // llvm.hexagon.F2.conv.ud2df
3, // llvm.hexagon.F2.conv.ud2sf
3, // llvm.hexagon.F2.conv.uw2df
3, // llvm.hexagon.F2.conv.uw2sf
3, // llvm.hexagon.F2.conv.w2df
3, // llvm.hexagon.F2.conv.w2sf
3, // llvm.hexagon.F2.dfadd
3, // llvm.hexagon.F2.dfclass
3, // llvm.hexagon.F2.dfcmpeq
3, // llvm.hexagon.F2.dfcmpge
3, // llvm.hexagon.F2.dfcmpgt
3, // llvm.hexagon.F2.dfcmpuo
3, // llvm.hexagon.F2.dffixupd
3, // llvm.hexagon.F2.dffixupn
3, // llvm.hexagon.F2.dffixupr
3, // llvm.hexagon.F2.dffma
3, // llvm.hexagon.F2.dffma.lib
3, // llvm.hexagon.F2.dffma.sc
3, // llvm.hexagon.F2.dffms
3, // llvm.hexagon.F2.dffms.lib
3, // llvm.hexagon.F2.dfimm.n
3, // llvm.hexagon.F2.dfimm.p
3, // llvm.hexagon.F2.dfmax
3, // llvm.hexagon.F2.dfmin
3, // llvm.hexagon.F2.dfmpy
3, // llvm.hexagon.F2.dfsub
3, // llvm.hexagon.F2.sfadd
3, // llvm.hexagon.F2.sfclass
3, // llvm.hexagon.F2.sfcmpeq
3, // llvm.hexagon.F2.sfcmpge
3, // llvm.hexagon.F2.sfcmpgt
3, // llvm.hexagon.F2.sfcmpuo
3, // llvm.hexagon.F2.sffixupd
3, // llvm.hexagon.F2.sffixupn
3, // llvm.hexagon.F2.sffixupr
3, // llvm.hexagon.F2.sffma
3, // llvm.hexagon.F2.sffma.lib
3, // llvm.hexagon.F2.sffma.sc
3, // llvm.hexagon.F2.sffms
3, // llvm.hexagon.F2.sffms.lib
3, // llvm.hexagon.F2.sfimm.n
3, // llvm.hexagon.F2.sfimm.p
3, // llvm.hexagon.F2.sfmax
3, // llvm.hexagon.F2.sfmin
3, // llvm.hexagon.F2.sfmpy
3, // llvm.hexagon.F2.sfsub
3, // llvm.hexagon.M2.acci 3, // llvm.hexagon.M2.acci
3, // llvm.hexagon.M2.accii 3, // llvm.hexagon.M2.accii
3, // llvm.hexagon.M2.cmaci.s0 3, // llvm.hexagon.M2.cmaci.s0
3, // llvm.hexagon.M2.cmacr.s0 3, // llvm.hexagon.M2.cmacr.s0
3, // llvm.hexagon.M2.cmacs.s0 3, // llvm.hexagon.M2.cmacs.s0
3, // llvm.hexagon.M2.cmacs.s1 3, // llvm.hexagon.M2.cmacs.s1
3, // llvm.hexagon.M2.cmacsc.s0 3, // llvm.hexagon.M2.cmacsc.s0
3, // llvm.hexagon.M2.cmacsc.s1 3, // llvm.hexagon.M2.cmacsc.s1
3, // llvm.hexagon.M2.cmpyi.s0 3, // llvm.hexagon.M2.cmpyi.s0
3, // llvm.hexagon.M2.cmpyr.s0 3, // llvm.hexagon.M2.cmpyr.s0
skipping to change at line 23534 skipping to change at line 23420
3, // llvm.hexagon.M2.cnacsc.s0 3, // llvm.hexagon.M2.cnacsc.s0
3, // llvm.hexagon.M2.cnacsc.s1 3, // llvm.hexagon.M2.cnacsc.s1
3, // llvm.hexagon.M2.dpmpyss.acc.s0 3, // llvm.hexagon.M2.dpmpyss.acc.s0
3, // llvm.hexagon.M2.dpmpyss.nac.s0 3, // llvm.hexagon.M2.dpmpyss.nac.s0
3, // llvm.hexagon.M2.dpmpyss.rnd.s0 3, // llvm.hexagon.M2.dpmpyss.rnd.s0
3, // llvm.hexagon.M2.dpmpyss.s0 3, // llvm.hexagon.M2.dpmpyss.s0
3, // llvm.hexagon.M2.dpmpyuu.acc.s0 3, // llvm.hexagon.M2.dpmpyuu.acc.s0
3, // llvm.hexagon.M2.dpmpyuu.nac.s0 3, // llvm.hexagon.M2.dpmpyuu.nac.s0
3, // llvm.hexagon.M2.dpmpyuu.s0 3, // llvm.hexagon.M2.dpmpyuu.s0
3, // llvm.hexagon.M2.hmmpyh.rs1 3, // llvm.hexagon.M2.hmmpyh.rs1
3, // llvm.hexagon.M2.hmmpyh.s1
3, // llvm.hexagon.M2.hmmpyl.rs1 3, // llvm.hexagon.M2.hmmpyl.rs1
3, // llvm.hexagon.M2.hmmpyl.s1
3, // llvm.hexagon.M2.maci 3, // llvm.hexagon.M2.maci
3, // llvm.hexagon.M2.macsin 3, // llvm.hexagon.M2.macsin
3, // llvm.hexagon.M2.macsip 3, // llvm.hexagon.M2.macsip
3, // llvm.hexagon.M2.mmachs.rs0 3, // llvm.hexagon.M2.mmachs.rs0
3, // llvm.hexagon.M2.mmachs.rs1 3, // llvm.hexagon.M2.mmachs.rs1
3, // llvm.hexagon.M2.mmachs.s0 3, // llvm.hexagon.M2.mmachs.s0
3, // llvm.hexagon.M2.mmachs.s1 3, // llvm.hexagon.M2.mmachs.s1
3, // llvm.hexagon.M2.mmacls.rs0 3, // llvm.hexagon.M2.mmacls.rs0
3, // llvm.hexagon.M2.mmacls.rs1 3, // llvm.hexagon.M2.mmacls.rs1
3, // llvm.hexagon.M2.mmacls.s0 3, // llvm.hexagon.M2.mmacls.s0
skipping to change at line 23635 skipping to change at line 23523
3, // llvm.hexagon.M2.mpy.sat.ll.s1 3, // llvm.hexagon.M2.mpy.sat.ll.s1
3, // llvm.hexagon.M2.mpy.sat.rnd.hh.s0 3, // llvm.hexagon.M2.mpy.sat.rnd.hh.s0
3, // llvm.hexagon.M2.mpy.sat.rnd.hh.s1 3, // llvm.hexagon.M2.mpy.sat.rnd.hh.s1
3, // llvm.hexagon.M2.mpy.sat.rnd.hl.s0 3, // llvm.hexagon.M2.mpy.sat.rnd.hl.s0
3, // llvm.hexagon.M2.mpy.sat.rnd.hl.s1 3, // llvm.hexagon.M2.mpy.sat.rnd.hl.s1
3, // llvm.hexagon.M2.mpy.sat.rnd.lh.s0 3, // llvm.hexagon.M2.mpy.sat.rnd.lh.s0
3, // llvm.hexagon.M2.mpy.sat.rnd.lh.s1 3, // llvm.hexagon.M2.mpy.sat.rnd.lh.s1
3, // llvm.hexagon.M2.mpy.sat.rnd.ll.s0 3, // llvm.hexagon.M2.mpy.sat.rnd.ll.s0
3, // llvm.hexagon.M2.mpy.sat.rnd.ll.s1 3, // llvm.hexagon.M2.mpy.sat.rnd.ll.s1
3, // llvm.hexagon.M2.mpy.up 3, // llvm.hexagon.M2.mpy.up
3, // llvm.hexagon.M2.mpy.up.s1
3, // llvm.hexagon.M2.mpy.up.s1.sat
3, // llvm.hexagon.M2.mpyd.acc.hh.s0 3, // llvm.hexagon.M2.mpyd.acc.hh.s0
3, // llvm.hexagon.M2.mpyd.acc.hh.s1 3, // llvm.hexagon.M2.mpyd.acc.hh.s1
3, // llvm.hexagon.M2.mpyd.acc.hl.s0 3, // llvm.hexagon.M2.mpyd.acc.hl.s0
3, // llvm.hexagon.M2.mpyd.acc.hl.s1 3, // llvm.hexagon.M2.mpyd.acc.hl.s1
3, // llvm.hexagon.M2.mpyd.acc.lh.s0 3, // llvm.hexagon.M2.mpyd.acc.lh.s0
3, // llvm.hexagon.M2.mpyd.acc.lh.s1 3, // llvm.hexagon.M2.mpyd.acc.lh.s1
3, // llvm.hexagon.M2.mpyd.acc.ll.s0 3, // llvm.hexagon.M2.mpyd.acc.ll.s0
3, // llvm.hexagon.M2.mpyd.acc.ll.s1 3, // llvm.hexagon.M2.mpyd.acc.ll.s1
3, // llvm.hexagon.M2.mpyd.hh.s0 3, // llvm.hexagon.M2.mpyd.hh.s0
3, // llvm.hexagon.M2.mpyd.hh.s1 3, // llvm.hexagon.M2.mpyd.hh.s1
skipping to change at line 23669 skipping to change at line 23559
3, // llvm.hexagon.M2.mpyd.rnd.hh.s0 3, // llvm.hexagon.M2.mpyd.rnd.hh.s0
3, // llvm.hexagon.M2.mpyd.rnd.hh.s1 3, // llvm.hexagon.M2.mpyd.rnd.hh.s1
3, // llvm.hexagon.M2.mpyd.rnd.hl.s0 3, // llvm.hexagon.M2.mpyd.rnd.hl.s0
3, // llvm.hexagon.M2.mpyd.rnd.hl.s1 3, // llvm.hexagon.M2.mpyd.rnd.hl.s1
3, // llvm.hexagon.M2.mpyd.rnd.lh.s0 3, // llvm.hexagon.M2.mpyd.rnd.lh.s0
3, // llvm.hexagon.M2.mpyd.rnd.lh.s1 3, // llvm.hexagon.M2.mpyd.rnd.lh.s1
3, // llvm.hexagon.M2.mpyd.rnd.ll.s0 3, // llvm.hexagon.M2.mpyd.rnd.ll.s0
3, // llvm.hexagon.M2.mpyd.rnd.ll.s1 3, // llvm.hexagon.M2.mpyd.rnd.ll.s1
3, // llvm.hexagon.M2.mpyi 3, // llvm.hexagon.M2.mpyi
3, // llvm.hexagon.M2.mpysmi 3, // llvm.hexagon.M2.mpysmi
3, // llvm.hexagon.M2.mpysu.up
3, // llvm.hexagon.M2.mpyu.acc.hh.s0 3, // llvm.hexagon.M2.mpyu.acc.hh.s0
3, // llvm.hexagon.M2.mpyu.acc.hh.s1 3, // llvm.hexagon.M2.mpyu.acc.hh.s1
3, // llvm.hexagon.M2.mpyu.acc.hl.s0 3, // llvm.hexagon.M2.mpyu.acc.hl.s0
3, // llvm.hexagon.M2.mpyu.acc.hl.s1 3, // llvm.hexagon.M2.mpyu.acc.hl.s1
3, // llvm.hexagon.M2.mpyu.acc.lh.s0 3, // llvm.hexagon.M2.mpyu.acc.lh.s0
3, // llvm.hexagon.M2.mpyu.acc.lh.s1 3, // llvm.hexagon.M2.mpyu.acc.lh.s1
3, // llvm.hexagon.M2.mpyu.acc.ll.s0 3, // llvm.hexagon.M2.mpyu.acc.ll.s0
3, // llvm.hexagon.M2.mpyu.acc.ll.s1 3, // llvm.hexagon.M2.mpyu.acc.ll.s1
3, // llvm.hexagon.M2.mpyu.hh.s0 3, // llvm.hexagon.M2.mpyu.hh.s0
3, // llvm.hexagon.M2.mpyu.hh.s1 3, // llvm.hexagon.M2.mpyu.hh.s1
skipping to change at line 23742 skipping to change at line 23633
3, // llvm.hexagon.M2.vdmpyrs.s0 3, // llvm.hexagon.M2.vdmpyrs.s0
3, // llvm.hexagon.M2.vdmpyrs.s1 3, // llvm.hexagon.M2.vdmpyrs.s1
3, // llvm.hexagon.M2.vdmpys.s0 3, // llvm.hexagon.M2.vdmpys.s0
3, // llvm.hexagon.M2.vdmpys.s1 3, // llvm.hexagon.M2.vdmpys.s1
3, // llvm.hexagon.M2.vmac2 3, // llvm.hexagon.M2.vmac2
3, // llvm.hexagon.M2.vmac2es 3, // llvm.hexagon.M2.vmac2es
3, // llvm.hexagon.M2.vmac2es.s0 3, // llvm.hexagon.M2.vmac2es.s0
3, // llvm.hexagon.M2.vmac2es.s1 3, // llvm.hexagon.M2.vmac2es.s1
3, // llvm.hexagon.M2.vmac2s.s0 3, // llvm.hexagon.M2.vmac2s.s0
3, // llvm.hexagon.M2.vmac2s.s1 3, // llvm.hexagon.M2.vmac2s.s1
3, // llvm.hexagon.M2.vmac2su.s0
3, // llvm.hexagon.M2.vmac2su.s1
3, // llvm.hexagon.M2.vmpy2es.s0 3, // llvm.hexagon.M2.vmpy2es.s0
3, // llvm.hexagon.M2.vmpy2es.s1 3, // llvm.hexagon.M2.vmpy2es.s1
3, // llvm.hexagon.M2.vmpy2s.s0 3, // llvm.hexagon.M2.vmpy2s.s0
3, // llvm.hexagon.M2.vmpy2s.s0pack 3, // llvm.hexagon.M2.vmpy2s.s0pack
3, // llvm.hexagon.M2.vmpy2s.s1 3, // llvm.hexagon.M2.vmpy2s.s1
3, // llvm.hexagon.M2.vmpy2s.s1pack 3, // llvm.hexagon.M2.vmpy2s.s1pack
3, // llvm.hexagon.M2.vmpy2su.s0
3, // llvm.hexagon.M2.vmpy2su.s1
3, // llvm.hexagon.M2.vraddh
3, // llvm.hexagon.M2.vradduh 3, // llvm.hexagon.M2.vradduh
3, // llvm.hexagon.M2.vrcmaci.s0 3, // llvm.hexagon.M2.vrcmaci.s0
3, // llvm.hexagon.M2.vrcmaci.s0c 3, // llvm.hexagon.M2.vrcmaci.s0c
3, // llvm.hexagon.M2.vrcmacr.s0 3, // llvm.hexagon.M2.vrcmacr.s0
3, // llvm.hexagon.M2.vrcmacr.s0c 3, // llvm.hexagon.M2.vrcmacr.s0c
3, // llvm.hexagon.M2.vrcmpyi.s0 3, // llvm.hexagon.M2.vrcmpyi.s0
3, // llvm.hexagon.M2.vrcmpyi.s0c 3, // llvm.hexagon.M2.vrcmpyi.s0c
3, // llvm.hexagon.M2.vrcmpyr.s0 3, // llvm.hexagon.M2.vrcmpyr.s0
3, // llvm.hexagon.M2.vrcmpyr.s0c 3, // llvm.hexagon.M2.vrcmpyr.s0c
3, // llvm.hexagon.M2.vrcmpys.acc.s1 3, // llvm.hexagon.M2.vrcmpys.acc.s1
3, // llvm.hexagon.M2.vrcmpys.s1 3, // llvm.hexagon.M2.vrcmpys.s1
3, // llvm.hexagon.M2.vrcmpys.s1rp 3, // llvm.hexagon.M2.vrcmpys.s1rp
3, // llvm.hexagon.M2.vrmac.s0 3, // llvm.hexagon.M2.vrmac.s0
3, // llvm.hexagon.M2.vrmpy.s0 3, // llvm.hexagon.M2.vrmpy.s0
3, // llvm.hexagon.M2.xor.xacc 3, // llvm.hexagon.M2.xor.xacc
3, // llvm.hexagon.M4.and.and 3, // llvm.hexagon.M4.and.and
3, // llvm.hexagon.M4.and.andn 3, // llvm.hexagon.M4.and.andn
3, // llvm.hexagon.M4.and.or 3, // llvm.hexagon.M4.and.or
3, // llvm.hexagon.M4.and.xor 3, // llvm.hexagon.M4.and.xor
3, // llvm.hexagon.M4.cmpyi.wh
3, // llvm.hexagon.M4.cmpyi.whc
3, // llvm.hexagon.M4.cmpyr.wh
3, // llvm.hexagon.M4.cmpyr.whc
3, // llvm.hexagon.M4.mac.up.s1.sat
3, // llvm.hexagon.M4.mpyri.addi
3, // llvm.hexagon.M4.mpyri.addr
3, // llvm.hexagon.M4.mpyri.addr.u2
3, // llvm.hexagon.M4.mpyrr.addi
3, // llvm.hexagon.M4.mpyrr.addr
3, // llvm.hexagon.M4.nac.up.s1.sat
3, // llvm.hexagon.M4.or.and 3, // llvm.hexagon.M4.or.and
3, // llvm.hexagon.M4.or.andn 3, // llvm.hexagon.M4.or.andn
3, // llvm.hexagon.M4.or.or 3, // llvm.hexagon.M4.or.or
3, // llvm.hexagon.M4.or.xor 3, // llvm.hexagon.M4.or.xor
3, // llvm.hexagon.M4.pmpyw
3, // llvm.hexagon.M4.pmpyw.acc
3, // llvm.hexagon.M4.vpmpyh
3, // llvm.hexagon.M4.vpmpyh.acc
3, // llvm.hexagon.M4.vrmpyeh.acc.s0
3, // llvm.hexagon.M4.vrmpyeh.acc.s1
3, // llvm.hexagon.M4.vrmpyeh.s0
3, // llvm.hexagon.M4.vrmpyeh.s1
3, // llvm.hexagon.M4.vrmpyoh.acc.s0
3, // llvm.hexagon.M4.vrmpyoh.acc.s1
3, // llvm.hexagon.M4.vrmpyoh.s0
3, // llvm.hexagon.M4.vrmpyoh.s1
3, // llvm.hexagon.M4.xor.and 3, // llvm.hexagon.M4.xor.and
3, // llvm.hexagon.M4.xor.andn 3, // llvm.hexagon.M4.xor.andn
3, // llvm.hexagon.M4.xor.or 3, // llvm.hexagon.M4.xor.or
3, // llvm.hexagon.M4.xor.xacc 3, // llvm.hexagon.M4.xor.xacc
3, // llvm.hexagon.M5.vdmacbsu
3, // llvm.hexagon.M5.vdmpybsu
3, // llvm.hexagon.M5.vmacbsu
3, // llvm.hexagon.M5.vmacbuu
3, // llvm.hexagon.M5.vmpybsu
3, // llvm.hexagon.M5.vmpybuu
3, // llvm.hexagon.M5.vrmacbsu
3, // llvm.hexagon.M5.vrmacbuu
3, // llvm.hexagon.M5.vrmpybsu
3, // llvm.hexagon.M5.vrmpybuu
3, // llvm.hexagon.S2.addasl.rrri 3, // llvm.hexagon.S2.addasl.rrri
3, // llvm.hexagon.S2.asl.i.p 3, // llvm.hexagon.S2.asl.i.p
3, // llvm.hexagon.S2.asl.i.p.acc 3, // llvm.hexagon.S2.asl.i.p.acc
3, // llvm.hexagon.S2.asl.i.p.and 3, // llvm.hexagon.S2.asl.i.p.and
3, // llvm.hexagon.S2.asl.i.p.nac 3, // llvm.hexagon.S2.asl.i.p.nac
3, // llvm.hexagon.S2.asl.i.p.or 3, // llvm.hexagon.S2.asl.i.p.or
3, // llvm.hexagon.S2.asl.i.p.xacc 3, // llvm.hexagon.S2.asl.i.p.xacc
3, // llvm.hexagon.S2.asl.i.r 3, // llvm.hexagon.S2.asl.i.r
3, // llvm.hexagon.S2.asl.i.r.acc 3, // llvm.hexagon.S2.asl.i.r.acc
3, // llvm.hexagon.S2.asl.i.r.and 3, // llvm.hexagon.S2.asl.i.r.and
skipping to change at line 23796 skipping to change at line 23725
3, // llvm.hexagon.S2.asl.i.r.or 3, // llvm.hexagon.S2.asl.i.r.or
3, // llvm.hexagon.S2.asl.i.r.sat 3, // llvm.hexagon.S2.asl.i.r.sat
3, // llvm.hexagon.S2.asl.i.r.xacc 3, // llvm.hexagon.S2.asl.i.r.xacc
3, // llvm.hexagon.S2.asl.i.vh 3, // llvm.hexagon.S2.asl.i.vh
3, // llvm.hexagon.S2.asl.i.vw 3, // llvm.hexagon.S2.asl.i.vw
3, // llvm.hexagon.S2.asl.r.p 3, // llvm.hexagon.S2.asl.r.p
3, // llvm.hexagon.S2.asl.r.p.acc 3, // llvm.hexagon.S2.asl.r.p.acc
3, // llvm.hexagon.S2.asl.r.p.and 3, // llvm.hexagon.S2.asl.r.p.and
3, // llvm.hexagon.S2.asl.r.p.nac 3, // llvm.hexagon.S2.asl.r.p.nac
3, // llvm.hexagon.S2.asl.r.p.or 3, // llvm.hexagon.S2.asl.r.p.or
3, // llvm.hexagon.S2.asl.r.p.xor
3, // llvm.hexagon.S2.asl.r.r 3, // llvm.hexagon.S2.asl.r.r
3, // llvm.hexagon.S2.asl.r.r.acc 3, // llvm.hexagon.S2.asl.r.r.acc
3, // llvm.hexagon.S2.asl.r.r.and 3, // llvm.hexagon.S2.asl.r.r.and
3, // llvm.hexagon.S2.asl.r.r.nac 3, // llvm.hexagon.S2.asl.r.r.nac
3, // llvm.hexagon.S2.asl.r.r.or 3, // llvm.hexagon.S2.asl.r.r.or
3, // llvm.hexagon.S2.asl.r.r.sat 3, // llvm.hexagon.S2.asl.r.r.sat
3, // llvm.hexagon.S2.asl.r.vh 3, // llvm.hexagon.S2.asl.r.vh
3, // llvm.hexagon.S2.asl.r.vw 3, // llvm.hexagon.S2.asl.r.vw
3, // llvm.hexagon.S2.asr.i.p 3, // llvm.hexagon.S2.asr.i.p
3, // llvm.hexagon.S2.asr.i.p.acc 3, // llvm.hexagon.S2.asr.i.p.acc
3, // llvm.hexagon.S2.asr.i.p.and 3, // llvm.hexagon.S2.asr.i.p.and
3, // llvm.hexagon.S2.asr.i.p.nac 3, // llvm.hexagon.S2.asr.i.p.nac
3, // llvm.hexagon.S2.asr.i.p.or 3, // llvm.hexagon.S2.asr.i.p.or
3, // llvm.hexagon.S2.asr.i.p.rnd
3, // llvm.hexagon.S2.asr.i.p.rnd.goodsyntax
3, // llvm.hexagon.S2.asr.i.r 3, // llvm.hexagon.S2.asr.i.r
3, // llvm.hexagon.S2.asr.i.r.acc 3, // llvm.hexagon.S2.asr.i.r.acc
3, // llvm.hexagon.S2.asr.i.r.and 3, // llvm.hexagon.S2.asr.i.r.and
3, // llvm.hexagon.S2.asr.i.r.nac 3, // llvm.hexagon.S2.asr.i.r.nac
3, // llvm.hexagon.S2.asr.i.r.or 3, // llvm.hexagon.S2.asr.i.r.or
3, // llvm.hexagon.S2.asr.i.r.rnd 3, // llvm.hexagon.S2.asr.i.r.rnd
3, // llvm.hexagon.S2.asr.i.r.rnd.goodsyntax 3, // llvm.hexagon.S2.asr.i.r.rnd.goodsyntax
3, // llvm.hexagon.S2.asr.i.svw.trun 3, // llvm.hexagon.S2.asr.i.svw.trun
3, // llvm.hexagon.S2.asr.i.vh 3, // llvm.hexagon.S2.asr.i.vh
3, // llvm.hexagon.S2.asr.i.vw 3, // llvm.hexagon.S2.asr.i.vw
3, // llvm.hexagon.S2.asr.r.p 3, // llvm.hexagon.S2.asr.r.p
3, // llvm.hexagon.S2.asr.r.p.acc 3, // llvm.hexagon.S2.asr.r.p.acc
3, // llvm.hexagon.S2.asr.r.p.and 3, // llvm.hexagon.S2.asr.r.p.and
3, // llvm.hexagon.S2.asr.r.p.nac 3, // llvm.hexagon.S2.asr.r.p.nac
3, // llvm.hexagon.S2.asr.r.p.or 3, // llvm.hexagon.S2.asr.r.p.or
3, // llvm.hexagon.S2.asr.r.p.xor
3, // llvm.hexagon.S2.asr.r.r 3, // llvm.hexagon.S2.asr.r.r
3, // llvm.hexagon.S2.asr.r.r.acc 3, // llvm.hexagon.S2.asr.r.r.acc
3, // llvm.hexagon.S2.asr.r.r.and 3, // llvm.hexagon.S2.asr.r.r.and
3, // llvm.hexagon.S2.asr.r.r.nac 3, // llvm.hexagon.S2.asr.r.r.nac
3, // llvm.hexagon.S2.asr.r.r.or 3, // llvm.hexagon.S2.asr.r.r.or
3, // llvm.hexagon.S2.asr.r.r.sat 3, // llvm.hexagon.S2.asr.r.r.sat
3, // llvm.hexagon.S2.asr.r.svw.trun 3, // llvm.hexagon.S2.asr.r.svw.trun
3, // llvm.hexagon.S2.asr.r.vh 3, // llvm.hexagon.S2.asr.r.vh
3, // llvm.hexagon.S2.asr.r.vw 3, // llvm.hexagon.S2.asr.r.vw
3, // llvm.hexagon.S2.brev 3, // llvm.hexagon.S2.brev
3, // llvm.hexagon.S2.brevp
3, // llvm.hexagon.S2.cl0 3, // llvm.hexagon.S2.cl0
3, // llvm.hexagon.S2.cl0p 3, // llvm.hexagon.S2.cl0p
3, // llvm.hexagon.S2.cl1 3, // llvm.hexagon.S2.cl1
3, // llvm.hexagon.S2.cl1p 3, // llvm.hexagon.S2.cl1p
3, // llvm.hexagon.S2.clb 3, // llvm.hexagon.S2.clb
3, // llvm.hexagon.S2.clbnorm 3, // llvm.hexagon.S2.clbnorm
3, // llvm.hexagon.S2.clbp 3, // llvm.hexagon.S2.clbp
3, // llvm.hexagon.S2.clrbit.i 3, // llvm.hexagon.S2.clrbit.i
3, // llvm.hexagon.S2.clrbit.r 3, // llvm.hexagon.S2.clrbit.r
3, // llvm.hexagon.S2.ct0 3, // llvm.hexagon.S2.ct0
3, // llvm.hexagon.S2.ct0p
3, // llvm.hexagon.S2.ct1 3, // llvm.hexagon.S2.ct1
3, // llvm.hexagon.S2.ct1p
3, // llvm.hexagon.S2.deinterleave 3, // llvm.hexagon.S2.deinterleave
3, // llvm.hexagon.S2.extractu 3, // llvm.hexagon.S2.extractu
3, // llvm.hexagon.S2.extractu.rp 3, // llvm.hexagon.S2.extractu.rp
3, // llvm.hexagon.S2.extractup 3, // llvm.hexagon.S2.extractup
3, // llvm.hexagon.S2.extractup.rp 3, // llvm.hexagon.S2.extractup.rp
3, // llvm.hexagon.S2.insert 3, // llvm.hexagon.S2.insert
3, // llvm.hexagon.S2.insert.rp 3, // llvm.hexagon.S2.insert.rp
3, // llvm.hexagon.S2.insertp 3, // llvm.hexagon.S2.insertp
3, // llvm.hexagon.S2.insertp.rp 3, // llvm.hexagon.S2.insertp.rp
3, // llvm.hexagon.S2.interleave 3, // llvm.hexagon.S2.interleave
3, // llvm.hexagon.S2.lfsp 3, // llvm.hexagon.S2.lfsp
3, // llvm.hexagon.S2.lsl.r.p 3, // llvm.hexagon.S2.lsl.r.p
3, // llvm.hexagon.S2.lsl.r.p.acc 3, // llvm.hexagon.S2.lsl.r.p.acc
3, // llvm.hexagon.S2.lsl.r.p.and 3, // llvm.hexagon.S2.lsl.r.p.and
3, // llvm.hexagon.S2.lsl.r.p.nac 3, // llvm.hexagon.S2.lsl.r.p.nac
3, // llvm.hexagon.S2.lsl.r.p.or 3, // llvm.hexagon.S2.lsl.r.p.or
3, // llvm.hexagon.S2.lsl.r.p.xor
3, // llvm.hexagon.S2.lsl.r.r 3, // llvm.hexagon.S2.lsl.r.r
3, // llvm.hexagon.S2.lsl.r.r.acc 3, // llvm.hexagon.S2.lsl.r.r.acc
3, // llvm.hexagon.S2.lsl.r.r.and 3, // llvm.hexagon.S2.lsl.r.r.and
3, // llvm.hexagon.S2.lsl.r.r.nac 3, // llvm.hexagon.S2.lsl.r.r.nac
3, // llvm.hexagon.S2.lsl.r.r.or 3, // llvm.hexagon.S2.lsl.r.r.or
3, // llvm.hexagon.S2.lsl.r.vh 3, // llvm.hexagon.S2.lsl.r.vh
3, // llvm.hexagon.S2.lsl.r.vw 3, // llvm.hexagon.S2.lsl.r.vw
3, // llvm.hexagon.S2.lsr.i.p 3, // llvm.hexagon.S2.lsr.i.p
3, // llvm.hexagon.S2.lsr.i.p.acc 3, // llvm.hexagon.S2.lsr.i.p.acc
3, // llvm.hexagon.S2.lsr.i.p.and 3, // llvm.hexagon.S2.lsr.i.p.and
skipping to change at line 23887 skipping to change at line 23824
3, // llvm.hexagon.S2.lsr.i.r.nac 3, // llvm.hexagon.S2.lsr.i.r.nac
3, // llvm.hexagon.S2.lsr.i.r.or 3, // llvm.hexagon.S2.lsr.i.r.or
3, // llvm.hexagon.S2.lsr.i.r.xacc 3, // llvm.hexagon.S2.lsr.i.r.xacc
3, // llvm.hexagon.S2.lsr.i.vh 3, // llvm.hexagon.S2.lsr.i.vh
3, // llvm.hexagon.S2.lsr.i.vw 3, // llvm.hexagon.S2.lsr.i.vw
3, // llvm.hexagon.S2.lsr.r.p 3, // llvm.hexagon.S2.lsr.r.p
3, // llvm.hexagon.S2.lsr.r.p.acc 3, // llvm.hexagon.S2.lsr.r.p.acc
3, // llvm.hexagon.S2.lsr.r.p.and 3, // llvm.hexagon.S2.lsr.r.p.and
3, // llvm.hexagon.S2.lsr.r.p.nac 3, // llvm.hexagon.S2.lsr.r.p.nac
3, // llvm.hexagon.S2.lsr.r.p.or 3, // llvm.hexagon.S2.lsr.r.p.or
3, // llvm.hexagon.S2.lsr.r.p.xor
3, // llvm.hexagon.S2.lsr.r.r 3, // llvm.hexagon.S2.lsr.r.r
3, // llvm.hexagon.S2.lsr.r.r.acc 3, // llvm.hexagon.S2.lsr.r.r.acc
3, // llvm.hexagon.S2.lsr.r.r.and 3, // llvm.hexagon.S2.lsr.r.r.and
3, // llvm.hexagon.S2.lsr.r.r.nac 3, // llvm.hexagon.S2.lsr.r.r.nac
3, // llvm.hexagon.S2.lsr.r.r.or 3, // llvm.hexagon.S2.lsr.r.r.or
3, // llvm.hexagon.S2.lsr.r.vh 3, // llvm.hexagon.S2.lsr.r.vh
3, // llvm.hexagon.S2.lsr.r.vw 3, // llvm.hexagon.S2.lsr.r.vw
3, // llvm.hexagon.S2.packhl 3, // llvm.hexagon.S2.packhl
3, // llvm.hexagon.S2.parityp 3, // llvm.hexagon.S2.parityp
3, // llvm.hexagon.S2.setbit.i 3, // llvm.hexagon.S2.setbit.i
skipping to change at line 23914 skipping to change at line 23852
3, // llvm.hexagon.S2.tableidxb.goodsyntax 3, // llvm.hexagon.S2.tableidxb.goodsyntax
3, // llvm.hexagon.S2.tableidxd.goodsyntax 3, // llvm.hexagon.S2.tableidxd.goodsyntax
3, // llvm.hexagon.S2.tableidxh.goodsyntax 3, // llvm.hexagon.S2.tableidxh.goodsyntax
3, // llvm.hexagon.S2.tableidxw.goodsyntax 3, // llvm.hexagon.S2.tableidxw.goodsyntax
3, // llvm.hexagon.S2.togglebit.i 3, // llvm.hexagon.S2.togglebit.i
3, // llvm.hexagon.S2.togglebit.r 3, // llvm.hexagon.S2.togglebit.r
3, // llvm.hexagon.S2.tstbit.i 3, // llvm.hexagon.S2.tstbit.i
3, // llvm.hexagon.S2.tstbit.r 3, // llvm.hexagon.S2.tstbit.r
3, // llvm.hexagon.S2.valignib 3, // llvm.hexagon.S2.valignib
3, // llvm.hexagon.S2.valignrb 3, // llvm.hexagon.S2.valignrb
3, // llvm.hexagon.S2.vcnegh
3, // llvm.hexagon.S2.vcrotate 3, // llvm.hexagon.S2.vcrotate
3, // llvm.hexagon.S2.vrcnegh
3, // llvm.hexagon.S2.vrndpackwh 3, // llvm.hexagon.S2.vrndpackwh
3, // llvm.hexagon.S2.vrndpackwhs 3, // llvm.hexagon.S2.vrndpackwhs
3, // llvm.hexagon.S2.vsathb 3, // llvm.hexagon.S2.vsathb
3, // llvm.hexagon.S2.vsathb.nopack 3, // llvm.hexagon.S2.vsathb.nopack
3, // llvm.hexagon.S2.vsathub 3, // llvm.hexagon.S2.vsathub
3, // llvm.hexagon.S2.vsathub.nopack 3, // llvm.hexagon.S2.vsathub.nopack
3, // llvm.hexagon.S2.vsatwh 3, // llvm.hexagon.S2.vsatwh
3, // llvm.hexagon.S2.vsatwh.nopack 3, // llvm.hexagon.S2.vsatwh.nopack
3, // llvm.hexagon.S2.vsatwuh 3, // llvm.hexagon.S2.vsatwuh
3, // llvm.hexagon.S2.vsatwuh.nopack 3, // llvm.hexagon.S2.vsatwuh.nopack
skipping to change at line 23938 skipping to change at line 23878
3, // llvm.hexagon.S2.vsplicerb 3, // llvm.hexagon.S2.vsplicerb
3, // llvm.hexagon.S2.vsxtbh 3, // llvm.hexagon.S2.vsxtbh
3, // llvm.hexagon.S2.vsxthw 3, // llvm.hexagon.S2.vsxthw
3, // llvm.hexagon.S2.vtrunehb 3, // llvm.hexagon.S2.vtrunehb
3, // llvm.hexagon.S2.vtrunewh 3, // llvm.hexagon.S2.vtrunewh
3, // llvm.hexagon.S2.vtrunohb 3, // llvm.hexagon.S2.vtrunohb
3, // llvm.hexagon.S2.vtrunowh 3, // llvm.hexagon.S2.vtrunowh
3, // llvm.hexagon.S2.vzxtbh 3, // llvm.hexagon.S2.vzxtbh
3, // llvm.hexagon.S2.vzxthw 3, // llvm.hexagon.S2.vzxthw
3, // llvm.hexagon.S4.addaddi 3, // llvm.hexagon.S4.addaddi
3, // llvm.hexagon.S4.andnp 3, // llvm.hexagon.S4.addi.asl.ri
3, // llvm.hexagon.S4.addi.lsr.ri
3, // llvm.hexagon.S4.andi.asl.ri
3, // llvm.hexagon.S4.andi.lsr.ri
3, // llvm.hexagon.S4.clbaddi
3, // llvm.hexagon.S4.clbpaddi
3, // llvm.hexagon.S4.clbpnorm
3, // llvm.hexagon.S4.extract
3, // llvm.hexagon.S4.extract.rp
3, // llvm.hexagon.S4.extractp
3, // llvm.hexagon.S4.extractp.rp
3, // llvm.hexagon.S4.lsli
3, // llvm.hexagon.S4.ntstbit.i
3, // llvm.hexagon.S4.ntstbit.r
3, // llvm.hexagon.S4.or.andi 3, // llvm.hexagon.S4.or.andi
3, // llvm.hexagon.S4.or.andix 3, // llvm.hexagon.S4.or.andix
3, // llvm.hexagon.S4.or.ori 3, // llvm.hexagon.S4.or.ori
3, // llvm.hexagon.S4.ornp 3, // llvm.hexagon.S4.ori.asl.ri
3, // llvm.hexagon.S4.ori.lsr.ri
3, // llvm.hexagon.S4.parity
3, // llvm.hexagon.S4.subaddi 3, // llvm.hexagon.S4.subaddi
3, // llvm.hexagon.S4.subi.asl.ri
3, // llvm.hexagon.S4.subi.lsr.ri
3, // llvm.hexagon.S4.vrcrotate
3, // llvm.hexagon.S4.vrcrotate.acc
3, // llvm.hexagon.S4.vxaddsubh
3, // llvm.hexagon.S4.vxaddsubhr
3, // llvm.hexagon.S4.vxaddsubw
3, // llvm.hexagon.S4.vxsubaddh
3, // llvm.hexagon.S4.vxsubaddhr
3, // llvm.hexagon.S4.vxsubaddw
3, // llvm.hexagon.S5.asrhub.rnd.sat.goodsyntax
3, // llvm.hexagon.S5.asrhub.sat
3, // llvm.hexagon.S5.popcountp
3, // llvm.hexagon.S5.vasrhrnd.goodsyntax
3, // llvm.hexagon.SI.to.SXTHI.asrh 3, // llvm.hexagon.SI.to.SXTHI.asrh
5, // llvm.init.trampoline 2, // llvm.hexagon.circ.ldd
6, // llvm.invariant.end 6, // llvm.init.trampoline
7, // llvm.invariant.start 7, // llvm.invariant.end
7, // llvm.lifetime.end 8, // llvm.invariant.start
7, // llvm.lifetime.start 8, // llvm.lifetime.end
8, // llvm.lifetime.start
1, // llvm.log 1, // llvm.log
1, // llvm.log10 1, // llvm.log10
1, // llvm.log2 1, // llvm.log2
2, // llvm.longjmp 4, // llvm.longjmp
8, // llvm.memcpy 9, // llvm.memcpy
8, // llvm.memmove 9, // llvm.memmove
5, // llvm.memset 6, // llvm.memset
2, // llvm.mips.absq.s.ph
2, // llvm.mips.absq.s.qb
2, // llvm.mips.absq.s.w
2, // llvm.mips.addq.ph
2, // llvm.mips.addq.s.ph
2, // llvm.mips.addq.s.w
3, // llvm.mips.addqh.ph
3, // llvm.mips.addqh.r.ph
3, // llvm.mips.addqh.r.w
3, // llvm.mips.addqh.w
2, // llvm.mips.addsc
2, // llvm.mips.addu.ph
2, // llvm.mips.addu.qb
2, // llvm.mips.addu.s.ph
2, // llvm.mips.addu.s.qb
3, // llvm.mips.adduh.qb
3, // llvm.mips.adduh.r.qb
2, // llvm.mips.addwc
3, // llvm.mips.append
3, // llvm.mips.balign
3, // llvm.mips.bitrev
1, // llvm.mips.bposge32
2, // llvm.mips.cmp.eq.ph
2, // llvm.mips.cmp.le.ph
2, // llvm.mips.cmp.lt.ph
2, // llvm.mips.cmpgdu.eq.qb
2, // llvm.mips.cmpgdu.le.qb
2, // llvm.mips.cmpgdu.lt.qb
2, // llvm.mips.cmpgu.eq.qb
2, // llvm.mips.cmpgu.le.qb
2, // llvm.mips.cmpgu.lt.qb
2, // llvm.mips.cmpu.eq.qb
2, // llvm.mips.cmpu.le.qb
2, // llvm.mips.cmpu.lt.qb
3, // llvm.mips.dpa.w.ph
2, // llvm.mips.dpaq.s.w.ph
2, // llvm.mips.dpaq.sa.l.w
2, // llvm.mips.dpaqx.s.w.ph
2, // llvm.mips.dpaqx.sa.w.ph
3, // llvm.mips.dpau.h.qbl
3, // llvm.mips.dpau.h.qbr
3, // llvm.mips.dpax.w.ph
3, // llvm.mips.dps.w.ph
2, // llvm.mips.dpsq.s.w.ph
2, // llvm.mips.dpsq.sa.l.w
2, // llvm.mips.dpsqx.s.w.ph
2, // llvm.mips.dpsqx.sa.w.ph
3, // llvm.mips.dpsu.h.qbl
3, // llvm.mips.dpsu.h.qbr
3, // llvm.mips.dpsx.w.ph
2, // llvm.mips.extp
2, // llvm.mips.extpdp
2, // llvm.mips.extr.r.w
2, // llvm.mips.extr.rs.w
2, // llvm.mips.extr.s.h
2, // llvm.mips.extr.w
1, // llvm.mips.insv
1, // llvm.mips.lbux
1, // llvm.mips.lhx
1, // llvm.mips.lwx
3, // llvm.mips.madd
3, // llvm.mips.maddu
2, // llvm.mips.maq.s.w.phl
2, // llvm.mips.maq.s.w.phr
2, // llvm.mips.maq.sa.w.phl
2, // llvm.mips.maq.sa.w.phr
3, // llvm.mips.modsub
3, // llvm.mips.msub
3, // llvm.mips.msubu
2, // llvm.mips.mthlip
2, // llvm.mips.mul.ph
2, // llvm.mips.mul.s.ph
2, // llvm.mips.muleq.s.w.phl
2, // llvm.mips.muleq.s.w.phr
2, // llvm.mips.muleu.s.ph.qbl
2, // llvm.mips.muleu.s.ph.qbr
2, // llvm.mips.mulq.rs.ph
2, // llvm.mips.mulq.rs.w
2, // llvm.mips.mulq.s.ph
2, // llvm.mips.mulq.s.w
3, // llvm.mips.mulsa.w.ph
2, // llvm.mips.mulsaq.s.w.ph
3, // llvm.mips.mult
3, // llvm.mips.multu
3, // llvm.mips.packrl.ph
1, // llvm.mips.pick.ph
1, // llvm.mips.pick.qb
3, // llvm.mips.preceq.w.phl
3, // llvm.mips.preceq.w.phr
3, // llvm.mips.precequ.ph.qbl
3, // llvm.mips.precequ.ph.qbla
3, // llvm.mips.precequ.ph.qbr
3, // llvm.mips.precequ.ph.qbra
3, // llvm.mips.preceu.ph.qbl
3, // llvm.mips.preceu.ph.qbla
3, // llvm.mips.preceu.ph.qbr
3, // llvm.mips.preceu.ph.qbra
2, // llvm.mips.precr.qb.ph
3, // llvm.mips.precr.sra.ph.w
3, // llvm.mips.precr.sra.r.ph.w
3, // llvm.mips.precrq.ph.w
3, // llvm.mips.precrq.qb.ph
2, // llvm.mips.precrq.rs.ph.w
2, // llvm.mips.precrqu.s.qb.ph
3, // llvm.mips.prepend
3, // llvm.mips.raddu.w.qb
1, // llvm.mips.rddsp
3, // llvm.mips.repl.ph
3, // llvm.mips.repl.qb
3, // llvm.mips.shilo
2, // llvm.mips.shll.ph
2, // llvm.mips.shll.qb
2, // llvm.mips.shll.s.ph
2, // llvm.mips.shll.s.w
3, // llvm.mips.shra.ph
3, // llvm.mips.shra.qb
3, // llvm.mips.shra.r.ph
3, // llvm.mips.shra.r.qb
3, // llvm.mips.shra.r.w
3, // llvm.mips.shrl.ph
3, // llvm.mips.shrl.qb
2, // llvm.mips.subq.ph
2, // llvm.mips.subq.s.ph
2, // llvm.mips.subq.s.w
3, // llvm.mips.subqh.ph
3, // llvm.mips.subqh.r.ph
3, // llvm.mips.subqh.r.w
3, // llvm.mips.subqh.w
2, // llvm.mips.subu.ph
2, // llvm.mips.subu.qb
2, // llvm.mips.subu.s.ph
2, // llvm.mips.subu.s.qb
3, // llvm.mips.subuh.qb
3, // llvm.mips.subuh.r.qb
2, // llvm.mips.wrdsp
3, // llvm.nvvm.abs.i
3, // llvm.nvvm.abs.ll
3, // llvm.nvvm.add.rm.d
3, // llvm.nvvm.add.rm.f
3, // llvm.nvvm.add.rm.ftz.f
3, // llvm.nvvm.add.rn.d
3, // llvm.nvvm.add.rn.f
3, // llvm.nvvm.add.rn.ftz.f
3, // llvm.nvvm.add.rp.d
3, // llvm.nvvm.add.rp.f
3, // llvm.nvvm.add.rp.ftz.f
3, // llvm.nvvm.add.rz.d
3, // llvm.nvvm.add.rz.f
3, // llvm.nvvm.add.rz.ftz.f
6, // llvm.nvvm.atomic.load.add.f32
6, // llvm.nvvm.atomic.load.dec.32
6, // llvm.nvvm.atomic.load.inc.32
2, // llvm.nvvm.barrier0
2, // llvm.nvvm.barrier0.and
2, // llvm.nvvm.barrier0.or
2, // llvm.nvvm.barrier0.popc
3, // llvm.nvvm.bitcast.d2ll
3, // llvm.nvvm.bitcast.f2i
3, // llvm.nvvm.bitcast.i2f
3, // llvm.nvvm.bitcast.ll2d
3, // llvm.nvvm.brev32
3, // llvm.nvvm.brev64
3, // llvm.nvvm.ceil.d
3, // llvm.nvvm.ceil.f
3, // llvm.nvvm.ceil.ftz.f
3, // llvm.nvvm.clz.i
3, // llvm.nvvm.clz.ll
2, // llvm.nvvm.compiler.error
2, // llvm.nvvm.compiler.warn
3, // llvm.nvvm.cos.approx.f
3, // llvm.nvvm.cos.approx.ftz.f
3, // llvm.nvvm.d2f.rm
3, // llvm.nvvm.d2f.rm.ftz
3, // llvm.nvvm.d2f.rn
3, // llvm.nvvm.d2f.rn.ftz
3, // llvm.nvvm.d2f.rp
3, // llvm.nvvm.d2f.rp.ftz
3, // llvm.nvvm.d2f.rz
3, // llvm.nvvm.d2f.rz.ftz
3, // llvm.nvvm.d2i.hi
3, // llvm.nvvm.d2i.lo
3, // llvm.nvvm.d2i.rm
3, // llvm.nvvm.d2i.rn
3, // llvm.nvvm.d2i.rp
3, // llvm.nvvm.d2i.rz
3, // llvm.nvvm.d2ll.rm
3, // llvm.nvvm.d2ll.rn
3, // llvm.nvvm.d2ll.rp
3, // llvm.nvvm.d2ll.rz
3, // llvm.nvvm.d2ui.rm
3, // llvm.nvvm.d2ui.rn
3, // llvm.nvvm.d2ui.rp
3, // llvm.nvvm.d2ui.rz
3, // llvm.nvvm.d2ull.rm
3, // llvm.nvvm.d2ull.rn
3, // llvm.nvvm.d2ull.rp
3, // llvm.nvvm.d2ull.rz
3, // llvm.nvvm.div.approx.f
3, // llvm.nvvm.div.approx.ftz.f
3, // llvm.nvvm.div.rm.d
3, // llvm.nvvm.div.rm.f
3, // llvm.nvvm.div.rm.ftz.f
3, // llvm.nvvm.div.rn.d
3, // llvm.nvvm.div.rn.f
3, // llvm.nvvm.div.rn.ftz.f
3, // llvm.nvvm.div.rp.d
3, // llvm.nvvm.div.rp.f
3, // llvm.nvvm.div.rp.ftz.f
3, // llvm.nvvm.div.rz.d
3, // llvm.nvvm.div.rz.f
3, // llvm.nvvm.div.rz.ftz.f
3, // llvm.nvvm.ex2.approx.d
3, // llvm.nvvm.ex2.approx.f
3, // llvm.nvvm.ex2.approx.ftz.f
3, // llvm.nvvm.f2h.rn
3, // llvm.nvvm.f2h.rn.ftz
3, // llvm.nvvm.f2i.rm
3, // llvm.nvvm.f2i.rm.ftz
3, // llvm.nvvm.f2i.rn
3, // llvm.nvvm.f2i.rn.ftz
3, // llvm.nvvm.f2i.rp
3, // llvm.nvvm.f2i.rp.ftz
3, // llvm.nvvm.f2i.rz
3, // llvm.nvvm.f2i.rz.ftz
3, // llvm.nvvm.f2ll.rm
3, // llvm.nvvm.f2ll.rm.ftz
3, // llvm.nvvm.f2ll.rn
3, // llvm.nvvm.f2ll.rn.ftz
3, // llvm.nvvm.f2ll.rp
3, // llvm.nvvm.f2ll.rp.ftz
3, // llvm.nvvm.f2ll.rz
3, // llvm.nvvm.f2ll.rz.ftz
3, // llvm.nvvm.f2ui.rm
3, // llvm.nvvm.f2ui.rm.ftz
3, // llvm.nvvm.f2ui.rn
3, // llvm.nvvm.f2ui.rn.ftz
3, // llvm.nvvm.f2ui.rp
3, // llvm.nvvm.f2ui.rp.ftz
3, // llvm.nvvm.f2ui.rz
3, // llvm.nvvm.f2ui.rz.ftz
3, // llvm.nvvm.f2ull.rm
3, // llvm.nvvm.f2ull.rm.ftz
3, // llvm.nvvm.f2ull.rn
3, // llvm.nvvm.f2ull.rn.ftz
3, // llvm.nvvm.f2ull.rp
3, // llvm.nvvm.f2ull.rp.ftz
3, // llvm.nvvm.f2ull.rz
3, // llvm.nvvm.f2ull.rz.ftz
3, // llvm.nvvm.fabs.d
3, // llvm.nvvm.fabs.f
3, // llvm.nvvm.fabs.ftz.f
3, // llvm.nvvm.floor.d
3, // llvm.nvvm.floor.f
3, // llvm.nvvm.floor.ftz.f
3, // llvm.nvvm.fma.rm.d
3, // llvm.nvvm.fma.rm.f
3, // llvm.nvvm.fma.rm.ftz.f
3, // llvm.nvvm.fma.rn.d
3, // llvm.nvvm.fma.rn.f
3, // llvm.nvvm.fma.rn.ftz.f
3, // llvm.nvvm.fma.rp.d
3, // llvm.nvvm.fma.rp.f
3, // llvm.nvvm.fma.rp.ftz.f
3, // llvm.nvvm.fma.rz.d
3, // llvm.nvvm.fma.rz.f
3, // llvm.nvvm.fma.rz.ftz.f
3, // llvm.nvvm.fmax.d
3, // llvm.nvvm.fmax.f
3, // llvm.nvvm.fmax.ftz.f
3, // llvm.nvvm.fmin.d
3, // llvm.nvvm.fmin.f
3, // llvm.nvvm.fmin.ftz.f
3, // llvm.nvvm.h2f
3, // llvm.nvvm.i2d.rm
3, // llvm.nvvm.i2d.rn
3, // llvm.nvvm.i2d.rp
3, // llvm.nvvm.i2d.rz
3, // llvm.nvvm.i2f.rm
3, // llvm.nvvm.i2f.rn
3, // llvm.nvvm.i2f.rp
3, // llvm.nvvm.i2f.rz
10, // llvm.nvvm.ldu.global.f
10, // llvm.nvvm.ldu.global.i
10, // llvm.nvvm.ldu.global.p
3, // llvm.nvvm.lg2.approx.d
3, // llvm.nvvm.lg2.approx.f
3, // llvm.nvvm.lg2.approx.ftz.f
3, // llvm.nvvm.ll2d.rm
3, // llvm.nvvm.ll2d.rn
3, // llvm.nvvm.ll2d.rp
3, // llvm.nvvm.ll2d.rz
3, // llvm.nvvm.ll2f.rm
3, // llvm.nvvm.ll2f.rn
3, // llvm.nvvm.ll2f.rp
3, // llvm.nvvm.ll2f.rz
3, // llvm.nvvm.lohi.i2d
3, // llvm.nvvm.max.i
3, // llvm.nvvm.max.ll
3, // llvm.nvvm.max.ui
3, // llvm.nvvm.max.ull
2, // llvm.nvvm.membar.cta
2, // llvm.nvvm.membar.gl
2, // llvm.nvvm.membar.sys
3, // llvm.nvvm.min.i
3, // llvm.nvvm.min.ll
3, // llvm.nvvm.min.ui
3, // llvm.nvvm.min.ull
3, // llvm.nvvm.move.double
3, // llvm.nvvm.move.float
3, // llvm.nvvm.move.i16
3, // llvm.nvvm.move.i32
3, // llvm.nvvm.move.i64
3, // llvm.nvvm.move.i8
11, // llvm.nvvm.move.ptr
3, // llvm.nvvm.mul24.i
3, // llvm.nvvm.mul24.ui
3, // llvm.nvvm.mul.rm.d
3, // llvm.nvvm.mul.rm.f
3, // llvm.nvvm.mul.rm.ftz.f
3, // llvm.nvvm.mul.rn.d
3, // llvm.nvvm.mul.rn.f
3, // llvm.nvvm.mul.rn.ftz.f
3, // llvm.nvvm.mul.rp.d
3, // llvm.nvvm.mul.rp.f
3, // llvm.nvvm.mul.rp.ftz.f
3, // llvm.nvvm.mul.rz.d
3, // llvm.nvvm.mul.rz.f
3, // llvm.nvvm.mul.rz.ftz.f
3, // llvm.nvvm.mulhi.i
3, // llvm.nvvm.mulhi.ll
3, // llvm.nvvm.mulhi.ui
3, // llvm.nvvm.mulhi.ull
3, // llvm.nvvm.popc.i
3, // llvm.nvvm.popc.ll
3, // llvm.nvvm.prmt
11, // llvm.nvvm.ptr.constant.to.gen
11, // llvm.nvvm.ptr.gen.to.constant
11, // llvm.nvvm.ptr.gen.to.global
11, // llvm.nvvm.ptr.gen.to.local
11, // llvm.nvvm.ptr.gen.to.param
11, // llvm.nvvm.ptr.gen.to.shared
11, // llvm.nvvm.ptr.global.to.gen
11, // llvm.nvvm.ptr.local.to.gen
11, // llvm.nvvm.ptr.shared.to.gen
3, // llvm.nvvm.rcp.approx.ftz.d
3, // llvm.nvvm.rcp.rm.d
3, // llvm.nvvm.rcp.rm.f
3, // llvm.nvvm.rcp.rm.ftz.f
3, // llvm.nvvm.rcp.rn.d
3, // llvm.nvvm.rcp.rn.f
3, // llvm.nvvm.rcp.rn.ftz.f
3, // llvm.nvvm.rcp.rp.d
3, // llvm.nvvm.rcp.rp.f
3, // llvm.nvvm.rcp.rp.ftz.f
3, // llvm.nvvm.rcp.rz.d
3, // llvm.nvvm.rcp.rz.f
3, // llvm.nvvm.rcp.rz.ftz.f
3, // llvm.nvvm.read.ptx.sreg.ctaid.x
3, // llvm.nvvm.read.ptx.sreg.ctaid.y
3, // llvm.nvvm.read.ptx.sreg.ctaid.z
3, // llvm.nvvm.read.ptx.sreg.nctaid.x
3, // llvm.nvvm.read.ptx.sreg.nctaid.y
3, // llvm.nvvm.read.ptx.sreg.nctaid.z
3, // llvm.nvvm.read.ptx.sreg.ntid.x
3, // llvm.nvvm.read.ptx.sreg.ntid.y
3, // llvm.nvvm.read.ptx.sreg.ntid.z
3, // llvm.nvvm.read.ptx.sreg.tid.x
3, // llvm.nvvm.read.ptx.sreg.tid.y
3, // llvm.nvvm.read.ptx.sreg.tid.z
3, // llvm.nvvm.read.ptx.sreg.warpsize
3, // llvm.nvvm.round.d
3, // llvm.nvvm.round.f
3, // llvm.nvvm.round.ftz.f
3, // llvm.nvvm.rsqrt.approx.d
3, // llvm.nvvm.rsqrt.approx.f
3, // llvm.nvvm.rsqrt.approx.ftz.f
3, // llvm.nvvm.sad.i
3, // llvm.nvvm.sad.ui
3, // llvm.nvvm.saturate.d
3, // llvm.nvvm.saturate.f
3, // llvm.nvvm.saturate.ftz.f
3, // llvm.nvvm.sin.approx.f
3, // llvm.nvvm.sin.approx.ftz.f
3, // llvm.nvvm.sqrt.approx.f
3, // llvm.nvvm.sqrt.approx.ftz.f
3, // llvm.nvvm.sqrt.rm.d
3, // llvm.nvvm.sqrt.rm.f
3, // llvm.nvvm.sqrt.rm.ftz.f
3, // llvm.nvvm.sqrt.rn.d
3, // llvm.nvvm.sqrt.rn.f
3, // llvm.nvvm.sqrt.rn.ftz.f
3, // llvm.nvvm.sqrt.rp.d
3, // llvm.nvvm.sqrt.rp.f
3, // llvm.nvvm.sqrt.rp.ftz.f
3, // llvm.nvvm.sqrt.rz.d
3, // llvm.nvvm.sqrt.rz.f
3, // llvm.nvvm.sqrt.rz.ftz.f
3, // llvm.nvvm.trunc.d
3, // llvm.nvvm.trunc.f
3, // llvm.nvvm.trunc.ftz.f
3, // llvm.nvvm.ui2d.rm
3, // llvm.nvvm.ui2d.rn
3, // llvm.nvvm.ui2d.rp
3, // llvm.nvvm.ui2d.rz
3, // llvm.nvvm.ui2f.rm
3, // llvm.nvvm.ui2f.rn
3, // llvm.nvvm.ui2f.rp
3, // llvm.nvvm.ui2f.rz
3, // llvm.nvvm.ull2d.rm
3, // llvm.nvvm.ull2d.rn
3, // llvm.nvvm.ull2d.rp
3, // llvm.nvvm.ull2d.rz
3, // llvm.nvvm.ull2f.rm
3, // llvm.nvvm.ull2f.rn
3, // llvm.nvvm.ull2f.rp
3, // llvm.nvvm.ull2f.rz
3, // llvm.objectsize 3, // llvm.objectsize
2, // llvm.pcmarker 2, // llvm.pcmarker
1, // llvm.pow 1, // llvm.pow
1, // llvm.powi 1, // llvm.powi
2, // llvm.ppc.altivec.dss 2, // llvm.ppc.altivec.dss
2, // llvm.ppc.altivec.dssall 2, // llvm.ppc.altivec.dssall
2, // llvm.ppc.altivec.dst 2, // llvm.ppc.altivec.dst
2, // llvm.ppc.altivec.dstst 2, // llvm.ppc.altivec.dstst
2, // llvm.ppc.altivec.dststt 2, // llvm.ppc.altivec.dststt
2, // llvm.ppc.altivec.dstt 2, // llvm.ppc.altivec.dstt
skipping to change at line 24117 skipping to change at line 24503
3, // llvm.ppc.altivec.vupklsh 3, // llvm.ppc.altivec.vupklsh
2, // llvm.ppc.dcba 2, // llvm.ppc.dcba
2, // llvm.ppc.dcbf 2, // llvm.ppc.dcbf
2, // llvm.ppc.dcbi 2, // llvm.ppc.dcbi
2, // llvm.ppc.dcbst 2, // llvm.ppc.dcbst
2, // llvm.ppc.dcbt 2, // llvm.ppc.dcbt
2, // llvm.ppc.dcbtst 2, // llvm.ppc.dcbtst
2, // llvm.ppc.dcbz 2, // llvm.ppc.dcbz
2, // llvm.ppc.dcbzl 2, // llvm.ppc.dcbzl
2, // llvm.ppc.sync 2, // llvm.ppc.sync
5, // llvm.prefetch 6, // llvm.prefetch
2, // llvm.ptr.annotation 2, // llvm.ptr.annotation
2, // llvm.ptx.bar.sync 2, // llvm.ptx.bar.sync
3, // llvm.ptx.read.clock 3, // llvm.ptx.read.clock
3, // llvm.ptx.read.clock64 3, // llvm.ptx.read.clock64
3, // llvm.ptx.read.ctaid.w 3, // llvm.ptx.read.ctaid.w
3, // llvm.ptx.read.ctaid.x 3, // llvm.ptx.read.ctaid.x
3, // llvm.ptx.read.ctaid.y 3, // llvm.ptx.read.ctaid.y
3, // llvm.ptx.read.ctaid.z 3, // llvm.ptx.read.ctaid.z
3, // llvm.ptx.read.gridid 3, // llvm.ptx.read.gridid
3, // llvm.ptx.read.laneid 3, // llvm.ptx.read.laneid
skipping to change at line 24157 skipping to change at line 24543
3, // llvm.ptx.read.smid 3, // llvm.ptx.read.smid
3, // llvm.ptx.read.tid.w 3, // llvm.ptx.read.tid.w
3, // llvm.ptx.read.tid.x 3, // llvm.ptx.read.tid.x
3, // llvm.ptx.read.tid.y 3, // llvm.ptx.read.tid.y
3, // llvm.ptx.read.tid.z 3, // llvm.ptx.read.tid.z
3, // llvm.ptx.read.warpid 3, // llvm.ptx.read.warpid
2, // llvm.readcyclecounter 2, // llvm.readcyclecounter
3, // llvm.returnaddress 3, // llvm.returnaddress
3, // llvm.sadd.with.overflow 3, // llvm.sadd.with.overflow
2, // llvm.setjmp 2, // llvm.setjmp
2, // llvm.siglongjmp 4, // llvm.siglongjmp
2, // llvm.sigsetjmp 2, // llvm.sigsetjmp
1, // llvm.sin 1, // llvm.sin
3, // llvm.smul.with.overflow 3, // llvm.smul.with.overflow
3, // llvm.spu.si.a 3, // llvm.spu.si.a
3, // llvm.spu.si.addx 3, // llvm.spu.si.addx
3, // llvm.spu.si.ah 3, // llvm.spu.si.ah
3, // llvm.spu.si.ahi 3, // llvm.spu.si.ahi
3, // llvm.spu.si.ai 3, // llvm.spu.si.ai
3, // llvm.spu.si.and 3, // llvm.spu.si.and
3, // llvm.spu.si.andbi 3, // llvm.spu.si.andbi
skipping to change at line 24248 skipping to change at line 24634
3, // llvm.spu.si.shlqbyi 3, // llvm.spu.si.shlqbyi
3, // llvm.spu.si.xor 3, // llvm.spu.si.xor
3, // llvm.spu.si.xorbi 3, // llvm.spu.si.xorbi
3, // llvm.spu.si.xorhi 3, // llvm.spu.si.xorhi
3, // llvm.spu.si.xori 3, // llvm.spu.si.xori
1, // llvm.sqrt 1, // llvm.sqrt
3, // llvm.ssub.with.overflow 3, // llvm.ssub.with.overflow
2, // llvm.stackprotector 2, // llvm.stackprotector
2, // llvm.stackrestore 2, // llvm.stackrestore
2, // llvm.stacksave 2, // llvm.stacksave
2, // llvm.trap 4, // llvm.trap
3, // llvm.uadd.with.overflow 3, // llvm.uadd.with.overflow
3, // llvm.umul.with.overflow 3, // llvm.umul.with.overflow
3, // llvm.usub.with.overflow 3, // llvm.usub.with.overflow
2, // llvm.va_copy 2, // llvm.va_copy
2, // llvm.va_end 2, // llvm.va_end
2, // llvm.var.annotation 2, // llvm.var.annotation
2, // llvm.va_start 2, // llvm.va_start
3, // llvm.x86.3dnow.pavgusb 3, // llvm.x86.3dnow.pavgusb
3, // llvm.x86.3dnow.pf2id 3, // llvm.x86.3dnow.pf2id
3, // llvm.x86.3dnow.pfacc 3, // llvm.x86.3dnow.pfacc
skipping to change at line 24286 skipping to change at line 24672
3, // llvm.x86.3dnowa.pfnacc 3, // llvm.x86.3dnowa.pfnacc
3, // llvm.x86.3dnowa.pfpnacc 3, // llvm.x86.3dnowa.pfpnacc
3, // llvm.x86.3dnowa.pi2fw 3, // llvm.x86.3dnowa.pi2fw
3, // llvm.x86.3dnowa.pswapd 3, // llvm.x86.3dnowa.pswapd
3, // llvm.x86.aesni.aesdec 3, // llvm.x86.aesni.aesdec
3, // llvm.x86.aesni.aesdeclast 3, // llvm.x86.aesni.aesdeclast
3, // llvm.x86.aesni.aesenc 3, // llvm.x86.aesni.aesenc
3, // llvm.x86.aesni.aesenclast 3, // llvm.x86.aesni.aesenclast
3, // llvm.x86.aesni.aesimc 3, // llvm.x86.aesni.aesimc
3, // llvm.x86.aesni.aeskeygenassist 3, // llvm.x86.aesni.aeskeygenassist
1, // llvm.x86.avx2.gather.d.d
1, // llvm.x86.avx2.gather.d.d.256
1, // llvm.x86.avx2.gather.d.pd
1, // llvm.x86.avx2.gather.d.pd.256
1, // llvm.x86.avx2.gather.d.ps
1, // llvm.x86.avx2.gather.d.ps.256
1, // llvm.x86.avx2.gather.d.q
1, // llvm.x86.avx2.gather.d.q.256
1, // llvm.x86.avx2.gather.q.d
1, // llvm.x86.avx2.gather.q.d.256
1, // llvm.x86.avx2.gather.q.pd
1, // llvm.x86.avx2.gather.q.pd.256
1, // llvm.x86.avx2.gather.q.ps
1, // llvm.x86.avx2.gather.q.ps.256
1, // llvm.x86.avx2.gather.q.q
1, // llvm.x86.avx2.gather.q.q.256
1, // llvm.x86.avx2.maskload.d 1, // llvm.x86.avx2.maskload.d
1, // llvm.x86.avx2.maskload.d.256 1, // llvm.x86.avx2.maskload.d.256
1, // llvm.x86.avx2.maskload.q 1, // llvm.x86.avx2.maskload.q
1, // llvm.x86.avx2.maskload.q.256 1, // llvm.x86.avx2.maskload.q.256
2, // llvm.x86.avx2.maskstore.d 2, // llvm.x86.avx2.maskstore.d
2, // llvm.x86.avx2.maskstore.d.256 2, // llvm.x86.avx2.maskstore.d.256
2, // llvm.x86.avx2.maskstore.q 2, // llvm.x86.avx2.maskstore.q
2, // llvm.x86.avx2.maskstore.q.256 2, // llvm.x86.avx2.maskstore.q.256
1, // llvm.x86.avx2.movntdqa 1, // llvm.x86.avx2.movntdqa
3, // llvm.x86.avx2.mpsadbw 3, // llvm.x86.avx2.mpsadbw
skipping to change at line 24443 skipping to change at line 24845
2, // llvm.x86.avx.maskstore.pd 2, // llvm.x86.avx.maskstore.pd
2, // llvm.x86.avx.maskstore.pd.256 2, // llvm.x86.avx.maskstore.pd.256
2, // llvm.x86.avx.maskstore.ps 2, // llvm.x86.avx.maskstore.ps
2, // llvm.x86.avx.maskstore.ps.256 2, // llvm.x86.avx.maskstore.ps.256
3, // llvm.x86.avx.max.pd.256 3, // llvm.x86.avx.max.pd.256
3, // llvm.x86.avx.max.ps.256 3, // llvm.x86.avx.max.ps.256
3, // llvm.x86.avx.min.pd.256 3, // llvm.x86.avx.min.pd.256
3, // llvm.x86.avx.min.ps.256 3, // llvm.x86.avx.min.ps.256
3, // llvm.x86.avx.movmsk.pd.256 3, // llvm.x86.avx.movmsk.pd.256
3, // llvm.x86.avx.movmsk.ps.256 3, // llvm.x86.avx.movmsk.ps.256
2, // llvm.x86.avx.movnt.dq.256
2, // llvm.x86.avx.movnt.pd.256
2, // llvm.x86.avx.movnt.ps.256
3, // llvm.x86.avx.ptestc.256 3, // llvm.x86.avx.ptestc.256
3, // llvm.x86.avx.ptestnzc.256 3, // llvm.x86.avx.ptestnzc.256
3, // llvm.x86.avx.ptestz.256 3, // llvm.x86.avx.ptestz.256
3, // llvm.x86.avx.rcp.ps.256 3, // llvm.x86.avx.rcp.ps.256
3, // llvm.x86.avx.round.pd.256 3, // llvm.x86.avx.round.pd.256
3, // llvm.x86.avx.round.ps.256 3, // llvm.x86.avx.round.ps.256
3, // llvm.x86.avx.rsqrt.ps.256 3, // llvm.x86.avx.rsqrt.ps.256
3, // llvm.x86.avx.sqrt.pd.256 3, // llvm.x86.avx.sqrt.pd.256
3, // llvm.x86.avx.sqrt.ps.256 3, // llvm.x86.avx.sqrt.ps.256
2, // llvm.x86.avx.storeu.dq.256 2, // llvm.x86.avx.storeu.dq.256
skipping to change at line 24498 skipping to change at line 24897
2, // llvm.x86.avx.vzeroall 2, // llvm.x86.avx.vzeroall
2, // llvm.x86.avx.vzeroupper 2, // llvm.x86.avx.vzeroupper
3, // llvm.x86.bmi.bextr.32 3, // llvm.x86.bmi.bextr.32
3, // llvm.x86.bmi.bextr.64 3, // llvm.x86.bmi.bextr.64
3, // llvm.x86.bmi.bzhi.32 3, // llvm.x86.bmi.bzhi.32
3, // llvm.x86.bmi.bzhi.64 3, // llvm.x86.bmi.bzhi.64
3, // llvm.x86.bmi.pdep.32 3, // llvm.x86.bmi.pdep.32
3, // llvm.x86.bmi.pdep.64 3, // llvm.x86.bmi.pdep.64
3, // llvm.x86.bmi.pext.32 3, // llvm.x86.bmi.pext.32
3, // llvm.x86.bmi.pext.64 3, // llvm.x86.bmi.pext.64
3, // llvm.x86.fma4.vfmadd.pd 3, // llvm.x86.fma.vfmadd.pd
3, // llvm.x86.fma4.vfmadd.pd.256 3, // llvm.x86.fma.vfmadd.pd.256
3, // llvm.x86.fma4.vfmadd.ps 3, // llvm.x86.fma.vfmadd.ps
3, // llvm.x86.fma4.vfmadd.ps.256 3, // llvm.x86.fma.vfmadd.ps.256
3, // llvm.x86.fma4.vfmadd.sd 3, // llvm.x86.fma.vfmadd.sd
3, // llvm.x86.fma4.vfmadd.ss 3, // llvm.x86.fma.vfmadd.ss
3, // llvm.x86.fma4.vfmaddsub.pd 3, // llvm.x86.fma.vfmaddsub.pd
3, // llvm.x86.fma4.vfmaddsub.pd.256 3, // llvm.x86.fma.vfmaddsub.pd.256
3, // llvm.x86.fma4.vfmaddsub.ps 3, // llvm.x86.fma.vfmaddsub.ps
3, // llvm.x86.fma4.vfmaddsub.ps.256 3, // llvm.x86.fma.vfmaddsub.ps.256
3, // llvm.x86.fma4.vfmsub.pd 3, // llvm.x86.fma.vfmsub.pd
3, // llvm.x86.fma4.vfmsub.pd.256 3, // llvm.x86.fma.vfmsub.pd.256
3, // llvm.x86.fma4.vfmsub.ps 3, // llvm.x86.fma.vfmsub.ps
3, // llvm.x86.fma4.vfmsub.ps.256 3, // llvm.x86.fma.vfmsub.ps.256
3, // llvm.x86.fma4.vfmsub.sd 3, // llvm.x86.fma.vfmsub.sd
3, // llvm.x86.fma4.vfmsub.ss 3, // llvm.x86.fma.vfmsub.ss
3, // llvm.x86.fma4.vfmsubadd.pd 3, // llvm.x86.fma.vfmsubadd.pd
3, // llvm.x86.fma4.vfmsubadd.pd.256 3, // llvm.x86.fma.vfmsubadd.pd.256
3, // llvm.x86.fma4.vfmsubadd.ps 3, // llvm.x86.fma.vfmsubadd.ps
3, // llvm.x86.fma4.vfmsubadd.ps.256 3, // llvm.x86.fma.vfmsubadd.ps.256
3, // llvm.x86.fma4.vfnmadd.pd 3, // llvm.x86.fma.vfnmadd.pd
3, // llvm.x86.fma4.vfnmadd.pd.256 3, // llvm.x86.fma.vfnmadd.pd.256
3, // llvm.x86.fma4.vfnmadd.ps 3, // llvm.x86.fma.vfnmadd.ps
3, // llvm.x86.fma4.vfnmadd.ps.256 3, // llvm.x86.fma.vfnmadd.ps.256
3, // llvm.x86.fma4.vfnmadd.sd 3, // llvm.x86.fma.vfnmadd.sd
3, // llvm.x86.fma4.vfnmadd.ss 3, // llvm.x86.fma.vfnmadd.ss
3, // llvm.x86.fma4.vfnmsub.pd 3, // llvm.x86.fma.vfnmsub.pd
3, // llvm.x86.fma4.vfnmsub.pd.256 3, // llvm.x86.fma.vfnmsub.pd.256
3, // llvm.x86.fma4.vfnmsub.ps 3, // llvm.x86.fma.vfnmsub.ps
3, // llvm.x86.fma4.vfnmsub.ps.256 3, // llvm.x86.fma.vfnmsub.ps.256
3, // llvm.x86.fma4.vfnmsub.sd 3, // llvm.x86.fma.vfnmsub.sd
3, // llvm.x86.fma4.vfnmsub.ss 3, // llvm.x86.fma.vfnmsub.ss
2, // llvm.x86.int 2, // llvm.x86.int
2, // llvm.x86.mmx.emms 2, // llvm.x86.mmx.emms
2, // llvm.x86.mmx.femms 2, // llvm.x86.mmx.femms
2, // llvm.x86.mmx.maskmovq 2, // llvm.x86.mmx.maskmovq
2, // llvm.x86.mmx.movnt.dq 2, // llvm.x86.mmx.movnt.dq
3, // llvm.x86.mmx.packssdw 3, // llvm.x86.mmx.packssdw
3, // llvm.x86.mmx.packsswb 3, // llvm.x86.mmx.packsswb
3, // llvm.x86.mmx.packuswb 3, // llvm.x86.mmx.packuswb
3, // llvm.x86.mmx.padd.b 3, // llvm.x86.mmx.padd.b
3, // llvm.x86.mmx.padd.d 3, // llvm.x86.mmx.padd.d
skipping to change at line 24602 skipping to change at line 25001
3, // llvm.x86.mmx.psubs.w 3, // llvm.x86.mmx.psubs.w
3, // llvm.x86.mmx.psubus.b 3, // llvm.x86.mmx.psubus.b
3, // llvm.x86.mmx.psubus.w 3, // llvm.x86.mmx.psubus.w
3, // llvm.x86.mmx.punpckhbw 3, // llvm.x86.mmx.punpckhbw
3, // llvm.x86.mmx.punpckhdq 3, // llvm.x86.mmx.punpckhdq
3, // llvm.x86.mmx.punpckhwd 3, // llvm.x86.mmx.punpckhwd
3, // llvm.x86.mmx.punpcklbw 3, // llvm.x86.mmx.punpcklbw
3, // llvm.x86.mmx.punpckldq 3, // llvm.x86.mmx.punpckldq
3, // llvm.x86.mmx.punpcklwd 3, // llvm.x86.mmx.punpcklwd
3, // llvm.x86.mmx.pxor 3, // llvm.x86.mmx.pxor
3, // llvm.x86.pclmulqdq
2, // llvm.x86.rdfsbase.32 2, // llvm.x86.rdfsbase.32
2, // llvm.x86.rdfsbase.64 2, // llvm.x86.rdfsbase.64
2, // llvm.x86.rdgsbase.32 2, // llvm.x86.rdgsbase.32
2, // llvm.x86.rdgsbase.64 2, // llvm.x86.rdgsbase.64
2, // llvm.x86.rdrand.16
2, // llvm.x86.rdrand.32
2, // llvm.x86.rdrand.64
3, // llvm.x86.sse2.add.sd 3, // llvm.x86.sse2.add.sd
2, // llvm.x86.sse2.clflush 2, // llvm.x86.sse2.clflush
3, // llvm.x86.sse2.cmp.pd 3, // llvm.x86.sse2.cmp.pd
3, // llvm.x86.sse2.cmp.sd 3, // llvm.x86.sse2.cmp.sd
3, // llvm.x86.sse2.comieq.sd 3, // llvm.x86.sse2.comieq.sd
3, // llvm.x86.sse2.comige.sd 3, // llvm.x86.sse2.comige.sd
3, // llvm.x86.sse2.comigt.sd 3, // llvm.x86.sse2.comigt.sd
3, // llvm.x86.sse2.comile.sd 3, // llvm.x86.sse2.comile.sd
3, // llvm.x86.sse2.comilt.sd 3, // llvm.x86.sse2.comilt.sd
3, // llvm.x86.sse2.comineq.sd 3, // llvm.x86.sse2.comineq.sd
skipping to change at line 24770 skipping to change at line 25173
3, // llvm.x86.sse42.pcmpestris128 3, // llvm.x86.sse42.pcmpestris128
3, // llvm.x86.sse42.pcmpestriz128 3, // llvm.x86.sse42.pcmpestriz128
3, // llvm.x86.sse42.pcmpestrm128 3, // llvm.x86.sse42.pcmpestrm128
3, // llvm.x86.sse42.pcmpistri128 3, // llvm.x86.sse42.pcmpistri128
3, // llvm.x86.sse42.pcmpistria128 3, // llvm.x86.sse42.pcmpistria128
3, // llvm.x86.sse42.pcmpistric128 3, // llvm.x86.sse42.pcmpistric128
3, // llvm.x86.sse42.pcmpistrio128 3, // llvm.x86.sse42.pcmpistrio128
3, // llvm.x86.sse42.pcmpistris128 3, // llvm.x86.sse42.pcmpistris128
3, // llvm.x86.sse42.pcmpistriz128 3, // llvm.x86.sse42.pcmpistriz128
3, // llvm.x86.sse42.pcmpistrm128 3, // llvm.x86.sse42.pcmpistrm128
3, // llvm.x86.sse4a.extrq
3, // llvm.x86.sse4a.extrqi
3, // llvm.x86.sse4a.insertq
3, // llvm.x86.sse4a.insertqi
2, // llvm.x86.sse4a.movnt.sd
2, // llvm.x86.sse4a.movnt.ss
3, // llvm.x86.sse.add.ss 3, // llvm.x86.sse.add.ss
3, // llvm.x86.sse.cmp.ps 3, // llvm.x86.sse.cmp.ps
3, // llvm.x86.sse.cmp.ss 3, // llvm.x86.sse.cmp.ss
3, // llvm.x86.sse.comieq.ss 3, // llvm.x86.sse.comieq.ss
3, // llvm.x86.sse.comige.ss 3, // llvm.x86.sse.comige.ss
3, // llvm.x86.sse.comigt.ss 3, // llvm.x86.sse.comigt.ss
3, // llvm.x86.sse.comile.ss 3, // llvm.x86.sse.comile.ss
3, // llvm.x86.sse.comilt.ss 3, // llvm.x86.sse.comilt.ss
3, // llvm.x86.sse.comineq.ss 3, // llvm.x86.sse.comineq.ss
3, // llvm.x86.sse.cvtpd2pi 3, // llvm.x86.sse.cvtpd2pi
skipping to change at line 24854 skipping to change at line 25263
3, // llvm.x86.ssse3.psign.w 3, // llvm.x86.ssse3.psign.w
3, // llvm.x86.ssse3.psign.w.128 3, // llvm.x86.ssse3.psign.w.128
3, // llvm.x86.vcvtph2ps.128 3, // llvm.x86.vcvtph2ps.128
3, // llvm.x86.vcvtph2ps.256 3, // llvm.x86.vcvtph2ps.256
3, // llvm.x86.vcvtps2ph.128 3, // llvm.x86.vcvtps2ph.128
3, // llvm.x86.vcvtps2ph.256 3, // llvm.x86.vcvtps2ph.256
2, // llvm.x86.wrfsbase.32 2, // llvm.x86.wrfsbase.32
2, // llvm.x86.wrfsbase.64 2, // llvm.x86.wrfsbase.64
2, // llvm.x86.wrgsbase.32 2, // llvm.x86.wrgsbase.32
2, // llvm.x86.wrgsbase.64 2, // llvm.x86.wrgsbase.64
4, // llvm.x86.xabort
2, // llvm.x86.xbegin
2, // llvm.x86.xend
3, // llvm.x86.xop.vfrcz.pd 3, // llvm.x86.xop.vfrcz.pd
3, // llvm.x86.xop.vfrcz.pd.256 3, // llvm.x86.xop.vfrcz.pd.256
3, // llvm.x86.xop.vfrcz.ps 3, // llvm.x86.xop.vfrcz.ps
3, // llvm.x86.xop.vfrcz.ps.256 3, // llvm.x86.xop.vfrcz.ps.256
3, // llvm.x86.xop.vfrcz.sd 3, // llvm.x86.xop.vfrcz.sd
3, // llvm.x86.xop.vfrcz.ss 3, // llvm.x86.xop.vfrcz.ss
3, // llvm.x86.xop.vpcmov 3, // llvm.x86.xop.vpcmov
3, // llvm.x86.xop.vpcmov.256 3, // llvm.x86.xop.vpcmov.256
3, // llvm.x86.xop.vpcomeqb 3, // llvm.x86.xop.vpcomb
3, // llvm.x86.xop.vpcomeqd 3, // llvm.x86.xop.vpcomd
3, // llvm.x86.xop.vpcomeqq 3, // llvm.x86.xop.vpcomq
3, // llvm.x86.xop.vpcomequb 3, // llvm.x86.xop.vpcomub
3, // llvm.x86.xop.vpcomequd 3, // llvm.x86.xop.vpcomud
3, // llvm.x86.xop.vpcomequq 3, // llvm.x86.xop.vpcomuq
3, // llvm.x86.xop.vpcomequw 3, // llvm.x86.xop.vpcomuw
3, // llvm.x86.xop.vpcomeqw 3, // llvm.x86.xop.vpcomw
3, // llvm.x86.xop.vpcomfalseb
3, // llvm.x86.xop.vpcomfalsed
3, // llvm.x86.xop.vpcomfalseq
3, // llvm.x86.xop.vpcomfalseub
3, // llvm.x86.xop.vpcomfalseud
3, // llvm.x86.xop.vpcomfalseuq
3, // llvm.x86.xop.vpcomfalseuw
3, // llvm.x86.xop.vpcomfalsew
3, // llvm.x86.xop.vpcomgeb
3, // llvm.x86.xop.vpcomged
3, // llvm.x86.xop.vpcomgeq
3, // llvm.x86.xop.vpcomgeub
3, // llvm.x86.xop.vpcomgeud
3, // llvm.x86.xop.vpcomgeuq
3, // llvm.x86.xop.vpcomgeuw
3, // llvm.x86.xop.vpcomgew
3, // llvm.x86.xop.vpcomgtb
3, // llvm.x86.xop.vpcomgtd
3, // llvm.x86.xop.vpcomgtq
3, // llvm.x86.xop.vpcomgtub
3, // llvm.x86.xop.vpcomgtud
3, // llvm.x86.xop.vpcomgtuq
3, // llvm.x86.xop.vpcomgtuw
3, // llvm.x86.xop.vpcomgtw
3, // llvm.x86.xop.vpcomleb
3, // llvm.x86.xop.vpcomled
3, // llvm.x86.xop.vpcomleq
3, // llvm.x86.xop.vpcomleub
3, // llvm.x86.xop.vpcomleud
3, // llvm.x86.xop.vpcomleuq
3, // llvm.x86.xop.vpcomleuw
3, // llvm.x86.xop.vpcomlew
3, // llvm.x86.xop.vpcomltb
3, // llvm.x86.xop.vpcomltd
3, // llvm.x86.xop.vpcomltq
3, // llvm.x86.xop.vpcomltub
3, // llvm.x86.xop.vpcomltud
3, // llvm.x86.xop.vpcomltuq
3, // llvm.x86.xop.vpcomltuw
3, // llvm.x86.xop.vpcomltw
3, // llvm.x86.xop.vpcomneb
3, // llvm.x86.xop.vpcomned
3, // llvm.x86.xop.vpcomneq
3, // llvm.x86.xop.vpcomneub
3, // llvm.x86.xop.vpcomneud
3, // llvm.x86.xop.vpcomneuq
3, // llvm.x86.xop.vpcomneuw
3, // llvm.x86.xop.vpcomnew
3, // llvm.x86.xop.vpcomtrueb
3, // llvm.x86.xop.vpcomtrued
3, // llvm.x86.xop.vpcomtrueq
3, // llvm.x86.xop.vpcomtrueub
3, // llvm.x86.xop.vpcomtrueud
3, // llvm.x86.xop.vpcomtrueuq
3, // llvm.x86.xop.vpcomtrueuw
3, // llvm.x86.xop.vpcomtruew
3, // llvm.x86.xop.vpermil2pd 3, // llvm.x86.xop.vpermil2pd
3, // llvm.x86.xop.vpermil2pd.256 3, // llvm.x86.xop.vpermil2pd.256
3, // llvm.x86.xop.vpermil2ps 3, // llvm.x86.xop.vpermil2ps
3, // llvm.x86.xop.vpermil2ps.256 3, // llvm.x86.xop.vpermil2ps.256
3, // llvm.x86.xop.vphaddbd 3, // llvm.x86.xop.vphaddbd
3, // llvm.x86.xop.vphaddbq 3, // llvm.x86.xop.vphaddbq
3, // llvm.x86.xop.vphaddbw 3, // llvm.x86.xop.vphaddbw
3, // llvm.x86.xop.vphadddq 3, // llvm.x86.xop.vphadddq
3, // llvm.x86.xop.vphaddubd 3, // llvm.x86.xop.vphaddubd
3, // llvm.x86.xop.vphaddubq 3, // llvm.x86.xop.vphaddubq
skipping to change at line 24959 skipping to change at line 25315
3, // llvm.x86.xop.vpmacssdqh 3, // llvm.x86.xop.vpmacssdqh
3, // llvm.x86.xop.vpmacssdql 3, // llvm.x86.xop.vpmacssdql
3, // llvm.x86.xop.vpmacsswd 3, // llvm.x86.xop.vpmacsswd
3, // llvm.x86.xop.vpmacssww 3, // llvm.x86.xop.vpmacssww
3, // llvm.x86.xop.vpmacswd 3, // llvm.x86.xop.vpmacswd
3, // llvm.x86.xop.vpmacsww 3, // llvm.x86.xop.vpmacsww
3, // llvm.x86.xop.vpmadcsswd 3, // llvm.x86.xop.vpmadcsswd
3, // llvm.x86.xop.vpmadcswd 3, // llvm.x86.xop.vpmadcswd
3, // llvm.x86.xop.vpperm 3, // llvm.x86.xop.vpperm
3, // llvm.x86.xop.vprotb 3, // llvm.x86.xop.vprotb
3, // llvm.x86.xop.vprotbi
3, // llvm.x86.xop.vprotd 3, // llvm.x86.xop.vprotd
3, // llvm.x86.xop.vprotdi
3, // llvm.x86.xop.vprotq 3, // llvm.x86.xop.vprotq
3, // llvm.x86.xop.vprotqi
3, // llvm.x86.xop.vprotw 3, // llvm.x86.xop.vprotw
3, // llvm.x86.xop.vprotwi
3, // llvm.x86.xop.vpshab 3, // llvm.x86.xop.vpshab
3, // llvm.x86.xop.vpshad 3, // llvm.x86.xop.vpshad
3, // llvm.x86.xop.vpshaq 3, // llvm.x86.xop.vpshaq
3, // llvm.x86.xop.vpshaw 3, // llvm.x86.xop.vpshaw
3, // llvm.x86.xop.vpshlb 3, // llvm.x86.xop.vpshlb
3, // llvm.x86.xop.vpshld 3, // llvm.x86.xop.vpshld
3, // llvm.x86.xop.vpshlq 3, // llvm.x86.xop.vpshlq
3, // llvm.x86.xop.vpshlw 3, // llvm.x86.xop.vpshlw
3, // llvm.xcore.bitrev 3, // llvm.xcore.bitrev
2, // llvm.xcore.checkevent 2, // llvm.xcore.checkevent
5, // llvm.xcore.chkct 6, // llvm.xcore.chkct
2, // llvm.xcore.clre 2, // llvm.xcore.clre
2, // llvm.xcore.clrsr 2, // llvm.xcore.clrsr
3, // llvm.xcore.crc32 3, // llvm.xcore.crc32
3, // llvm.xcore.crc8 3, // llvm.xcore.crc8
5, // llvm.xcore.eeu 6, // llvm.xcore.eeu
5, // llvm.xcore.endin 6, // llvm.xcore.endin
5, // llvm.xcore.freer 6, // llvm.xcore.freer
2, // llvm.xcore.geted 2, // llvm.xcore.geted
2, // llvm.xcore.getet 2, // llvm.xcore.getet
3, // llvm.xcore.getid 3, // llvm.xcore.getid
2, // llvm.xcore.getps 2, // llvm.xcore.getps
2, // llvm.xcore.getr 2, // llvm.xcore.getr
5, // llvm.xcore.getst 6, // llvm.xcore.getst
5, // llvm.xcore.getts 6, // llvm.xcore.getts
5, // llvm.xcore.in 6, // llvm.xcore.in
5, // llvm.xcore.inct 6, // llvm.xcore.inct
5, // llvm.xcore.initcp 6, // llvm.xcore.initcp
5, // llvm.xcore.initdp 6, // llvm.xcore.initdp
5, // llvm.xcore.initlr 6, // llvm.xcore.initlr
5, // llvm.xcore.initpc 6, // llvm.xcore.initpc
5, // llvm.xcore.initsp 6, // llvm.xcore.initsp
5, // llvm.xcore.inshr 6, // llvm.xcore.inshr
5, // llvm.xcore.int 6, // llvm.xcore.int
5, // llvm.xcore.mjoin 6, // llvm.xcore.mjoin
5, // llvm.xcore.msync 6, // llvm.xcore.msync
5, // llvm.xcore.out 6, // llvm.xcore.out
5, // llvm.xcore.outct 6, // llvm.xcore.outct
5, // llvm.xcore.outshr 6, // llvm.xcore.outshr
5, // llvm.xcore.outt 6, // llvm.xcore.outt
5, // llvm.xcore.peek 6, // llvm.xcore.peek
5, // llvm.xcore.setc 6, // llvm.xcore.setc
8, // llvm.xcore.setclk 9, // llvm.xcore.setclk
5, // llvm.xcore.setd 6, // llvm.xcore.setd
5, // llvm.xcore.setev 6, // llvm.xcore.setev
2, // llvm.xcore.setps 2, // llvm.xcore.setps
5, // llvm.xcore.setpsc 6, // llvm.xcore.setpsc
5, // llvm.xcore.setpt 6, // llvm.xcore.setpt
8, // llvm.xcore.setrdy 9, // llvm.xcore.setrdy
2, // llvm.xcore.setsr 2, // llvm.xcore.setsr
5, // llvm.xcore.settw 6, // llvm.xcore.settw
5, // llvm.xcore.setv 6, // llvm.xcore.setv
3, // llvm.xcore.sext 3, // llvm.xcore.sext
2, // llvm.xcore.ssync 2, // llvm.xcore.ssync
5, // llvm.xcore.syncr 6, // llvm.xcore.syncr
5, // llvm.xcore.testct 6, // llvm.xcore.testct
5, // llvm.xcore.testwct 6, // llvm.xcore.testwct
1, // llvm.xcore.waitevent 1, // llvm.xcore.waitevent
3, // llvm.xcore.zext 3, // llvm.xcore.zext
}; };
AttributeWithIndex AWI[3]; AttributeWithIndex AWI[3];
unsigned NumAttrs = 0; unsigned NumAttrs = 0;
if (id != 0) { if (id != 0) {
SmallVector<Attributes::AttrVal, 8> AttrVec;
switch(IntrinsicsToAttributesMap[id - 1]) { switch(IntrinsicsToAttributesMap[id - 1]) {
default: llvm_unreachable("Invalid attribute number"); default: llvm_unreachable("Invalid attribute number");
case 3: case 3:
AWI[0] = AttributeWithIndex::get(~0, Attribute::NoUnwind|Attribute::R AttrVec.clear();
eadNone); AttrVec.push_back(Attributes::NoUnwind);
AttrVec.push_back(Attributes::ReadNone);
AWI[0] = AttributeWithIndex::get(C, AttrListPtr::FunctionIndex, AttrV
ec);
NumAttrs = 1; NumAttrs = 1;
break; break;
case 11:
AttrVec.clear();
AttrVec.push_back(Attributes::NoCapture);
AWI[0] = AttributeWithIndex::get(C, 1, AttrVec);
AttrVec.clear();
AttrVec.push_back(Attributes::NoUnwind);
AttrVec.push_back(Attributes::ReadNone);
AWI[1] = AttributeWithIndex::get(C, AttrListPtr::FunctionIndex, AttrV
ec);
NumAttrs = 2;
break;
case 1: case 1:
AWI[0] = AttributeWithIndex::get(~0, Attribute::NoUnwind|Attribute::R AttrVec.clear();
eadOnly); AttrVec.push_back(Attributes::NoUnwind);
AttrVec.push_back(Attributes::ReadOnly);
AWI[0] = AttributeWithIndex::get(C, AttrListPtr::FunctionIndex, AttrV
ec);
NumAttrs = 1; NumAttrs = 1;
break; break;
case 10:
AttrVec.clear();
AttrVec.push_back(Attributes::NoCapture);
AWI[0] = AttributeWithIndex::get(C, 1, AttrVec);
AttrVec.clear();
AttrVec.push_back(Attributes::NoUnwind);
AttrVec.push_back(Attributes::ReadOnly);
AWI[1] = AttributeWithIndex::get(C, AttrListPtr::FunctionIndex, AttrV
ec);
NumAttrs = 2;
break;
case 2: case 2:
AWI[0] = AttributeWithIndex::get(~0, Attribute::NoUnwind); AttrVec.clear();
AttrVec.push_back(Attributes::NoUnwind);
AWI[0] = AttributeWithIndex::get(C, AttrListPtr::FunctionIndex, AttrV
ec);
NumAttrs = 1; NumAttrs = 1;
break; break;
case 5: case 6:
AWI[0] = AttributeWithIndex::get(1, Attribute::NoCapture); AttrVec.clear();
AWI[1] = AttributeWithIndex::get(~0, Attribute::NoUnwind); AttrVec.push_back(Attributes::NoCapture);
AWI[0] = AttributeWithIndex::get(C, 1, AttrVec);
AttrVec.clear();
AttrVec.push_back(Attributes::NoUnwind);
AWI[1] = AttributeWithIndex::get(C, AttrListPtr::FunctionIndex, AttrV
ec);
NumAttrs = 2; NumAttrs = 2;
break; break;
case 8: case 9:
AWI[0] = AttributeWithIndex::get(1, Attribute::NoCapture); AttrVec.clear();
AWI[1] = AttributeWithIndex::get(2, Attribute::NoCapture); AttrVec.push_back(Attributes::NoCapture);
AWI[2] = AttributeWithIndex::get(~0, Attribute::NoUnwind); AWI[0] = AttributeWithIndex::get(C, 1, AttrVec);
AttrVec.clear();
AttrVec.push_back(Attributes::NoCapture);
AWI[1] = AttributeWithIndex::get(C, 2, AttrVec);
AttrVec.clear();
AttrVec.push_back(Attributes::NoUnwind);
AWI[2] = AttributeWithIndex::get(C, AttrListPtr::FunctionIndex, AttrV
ec);
NumAttrs = 3; NumAttrs = 3;
break; break;
case 7: case 8:
AWI[0] = AttributeWithIndex::get(2, Attribute::NoCapture); AttrVec.clear();
AWI[1] = AttributeWithIndex::get(~0, Attribute::NoUnwind); AttrVec.push_back(Attributes::NoCapture);
AWI[0] = AttributeWithIndex::get(C, 2, AttrVec);
AttrVec.clear();
AttrVec.push_back(Attributes::NoUnwind);
AWI[1] = AttributeWithIndex::get(C, AttrListPtr::FunctionIndex, AttrV
ec);
NumAttrs = 2; NumAttrs = 2;
break; break;
case 4: case 5:
AWI[0] = AttributeWithIndex::get(2, Attribute::NoCapture); AttrVec.clear();
AWI[1] = AttributeWithIndex::get(3, Attribute::NoCapture); AttrVec.push_back(Attributes::NoCapture);
AWI[2] = AttributeWithIndex::get(~0, Attribute::NoUnwind); AWI[0] = AttributeWithIndex::get(C, 2, AttrVec);
AttrVec.clear();
AttrVec.push_back(Attributes::NoCapture);
AWI[1] = AttributeWithIndex::get(C, 3, AttrVec);
AttrVec.clear();
AttrVec.push_back(Attributes::NoUnwind);
AWI[2] = AttributeWithIndex::get(C, AttrListPtr::FunctionIndex, AttrV
ec);
NumAttrs = 3; NumAttrs = 3;
break; break;
case 6: case 7:
AWI[0] = AttributeWithIndex::get(3, Attribute::NoCapture); AttrVec.clear();
AWI[1] = AttributeWithIndex::get(~0, Attribute::NoUnwind); AttrVec.push_back(Attributes::NoCapture);
AWI[0] = AttributeWithIndex::get(C, 3, AttrVec);
AttrVec.clear();
AttrVec.push_back(Attributes::NoUnwind);
AWI[1] = AttributeWithIndex::get(C, AttrListPtr::FunctionIndex, AttrV
ec);
NumAttrs = 2; NumAttrs = 2;
break; break;
case 4:
AttrVec.clear();
AttrVec.push_back(Attributes::NoUnwind);
AttrVec.push_back(Attributes::NoReturn);
AWI[0] = AttributeWithIndex::get(C, AttrListPtr::FunctionIndex, AttrV
ec);
NumAttrs = 1;
break;
} }
} }
return AttrListPtr::get(AWI, NumAttrs); return AttrListPtr::get(C, ArrayRef<AttributeWithIndex>(AWI, NumAttrs));
} }
#endif // GET_INTRINSIC_ATTRIBUTES #endif // GET_INTRINSIC_ATTRIBUTES
// Determine intrinsic alias analysis mod/ref behavior. // Determine intrinsic alias analysis mod/ref behavior.
#ifdef GET_INTRINSIC_MODREF_BEHAVIOR #ifdef GET_INTRINSIC_MODREF_BEHAVIOR
assert(iid <= Intrinsic::xcore_zext && "Unknown intrinsic."); assert(iid <= Intrinsic::xcore_zext && "Unknown intrinsic.");
static const uint8_t IntrinsicModRefBehavior[] = { static const uint8_t IntrinsicModRefBehavior[] = {
/* invalid */ UnknownModRefBehavior, /* invalid */ UnknownModRefBehavior,
/* adjust_trampoline */ OnlyReadsArgumentPointees, /* adjust_trampoline */ OnlyReadsArgumentPointees,
skipping to change at line 25099 skipping to change at line 25519
/* arm_mrc */ UnknownModRefBehavior, /* arm_mrc */ UnknownModRefBehavior,
/* arm_mrc2 */ UnknownModRefBehavior, /* arm_mrc2 */ UnknownModRefBehavior,
/* arm_neon_vabds */ DoesNotAccessMemory, /* arm_neon_vabds */ DoesNotAccessMemory,
/* arm_neon_vabdu */ DoesNotAccessMemory, /* arm_neon_vabdu */ DoesNotAccessMemory,
/* arm_neon_vabs */ DoesNotAccessMemory, /* arm_neon_vabs */ DoesNotAccessMemory,
/* arm_neon_vacged */ DoesNotAccessMemory, /* arm_neon_vacged */ DoesNotAccessMemory,
/* arm_neon_vacgeq */ DoesNotAccessMemory, /* arm_neon_vacgeq */ DoesNotAccessMemory,
/* arm_neon_vacgtd */ DoesNotAccessMemory, /* arm_neon_vacgtd */ DoesNotAccessMemory,
/* arm_neon_vacgtq */ DoesNotAccessMemory, /* arm_neon_vacgtq */ DoesNotAccessMemory,
/* arm_neon_vaddhn */ DoesNotAccessMemory, /* arm_neon_vaddhn */ DoesNotAccessMemory,
/* arm_neon_vbsl */ DoesNotAccessMemory,
/* arm_neon_vcls */ DoesNotAccessMemory, /* arm_neon_vcls */ DoesNotAccessMemory,
/* arm_neon_vclz */ DoesNotAccessMemory, /* arm_neon_vclz */ DoesNotAccessMemory,
/* arm_neon_vcnt */ DoesNotAccessMemory, /* arm_neon_vcnt */ DoesNotAccessMemory,
/* arm_neon_vcvtfp2fxs */ DoesNotAccessMemory, /* arm_neon_vcvtfp2fxs */ DoesNotAccessMemory,
/* arm_neon_vcvtfp2fxu */ DoesNotAccessMemory, /* arm_neon_vcvtfp2fxu */ DoesNotAccessMemory,
/* arm_neon_vcvtfp2hf */ DoesNotAccessMemory, /* arm_neon_vcvtfp2hf */ DoesNotAccessMemory,
/* arm_neon_vcvtfxs2fp */ DoesNotAccessMemory, /* arm_neon_vcvtfxs2fp */ DoesNotAccessMemory,
/* arm_neon_vcvtfxu2fp */ DoesNotAccessMemory, /* arm_neon_vcvtfxu2fp */ DoesNotAccessMemory,
/* arm_neon_vcvthf2fp */ DoesNotAccessMemory, /* arm_neon_vcvthf2fp */ DoesNotAccessMemory,
/* arm_neon_vhadds */ DoesNotAccessMemory, /* arm_neon_vhadds */ DoesNotAccessMemory,
skipping to change at line 25219 skipping to change at line 25640
/* convertsif */ UnknownModRefBehavior, /* convertsif */ UnknownModRefBehavior,
/* convertss */ UnknownModRefBehavior, /* convertss */ UnknownModRefBehavior,
/* convertsu */ UnknownModRefBehavior, /* convertsu */ UnknownModRefBehavior,
/* convertuif */ UnknownModRefBehavior, /* convertuif */ UnknownModRefBehavior,
/* convertus */ UnknownModRefBehavior, /* convertus */ UnknownModRefBehavior,
/* convertuu */ UnknownModRefBehavior, /* convertuu */ UnknownModRefBehavior,
/* cos */ OnlyReadsMemory, /* cos */ OnlyReadsMemory,
/* ctlz */ DoesNotAccessMemory, /* ctlz */ DoesNotAccessMemory,
/* ctpop */ DoesNotAccessMemory, /* ctpop */ DoesNotAccessMemory,
/* cttz */ DoesNotAccessMemory, /* cttz */ DoesNotAccessMemory,
/* cuda_syncthreads */ UnknownModRefBehavior,
/* dbg_declare */ DoesNotAccessMemory, /* dbg_declare */ DoesNotAccessMemory,
/* dbg_value */ DoesNotAccessMemory, /* dbg_value */ DoesNotAccessMemory,
/* debugtrap */ UnknownModRefBehavior,
/* donothing */ DoesNotAccessMemory,
/* eh_dwarf_cfa */ UnknownModRefBehavior, /* eh_dwarf_cfa */ UnknownModRefBehavior,
/* eh_return_i32 */ UnknownModRefBehavior, /* eh_return_i32 */ UnknownModRefBehavior,
/* eh_return_i64 */ UnknownModRefBehavior, /* eh_return_i64 */ UnknownModRefBehavior,
/* eh_sjlj_callsite */ DoesNotAccessMemory, /* eh_sjlj_callsite */ DoesNotAccessMemory,
/* eh_sjlj_functioncontext */ UnknownModRefBehavior, /* eh_sjlj_functioncontext */ UnknownModRefBehavior,
/* eh_sjlj_longjmp */ UnknownModRefBehavior, /* eh_sjlj_longjmp */ UnknownModRefBehavior,
/* eh_sjlj_lsda */ DoesNotAccessMemory, /* eh_sjlj_lsda */ DoesNotAccessMemory,
/* eh_sjlj_setjmp */ UnknownModRefBehavior, /* eh_sjlj_setjmp */ UnknownModRefBehavior,
/* eh_typeid_for */ DoesNotAccessMemory, /* eh_typeid_for */ DoesNotAccessMemory,
/* eh_unwind_init */ UnknownModRefBehavior, /* eh_unwind_init */ UnknownModRefBehavior,
/* exp */ OnlyReadsMemory, /* exp */ OnlyReadsMemory,
/* exp2 */ OnlyReadsMemory, /* exp2 */ OnlyReadsMemory,
/* expect */ DoesNotAccessMemory, /* expect */ DoesNotAccessMemory,
/* fabs */ OnlyReadsMemory,
/* floor */ OnlyReadsMemory,
/* flt_rounds */ UnknownModRefBehavior, /* flt_rounds */ UnknownModRefBehavior,
/* fma */ DoesNotAccessMemory, /* fma */ DoesNotAccessMemory,
/* fmuladd */ DoesNotAccessMemory,
/* frameaddress */ DoesNotAccessMemory, /* frameaddress */ DoesNotAccessMemory,
/* gcread */ OnlyReadsArgumentPointees, /* gcread */ OnlyReadsArgumentPointees,
/* gcroot */ UnknownModRefBehavior, /* gcroot */ UnknownModRefBehavior,
/* gcwrite */ OnlyAccessesArgumentPointees, /* gcwrite */ OnlyAccessesArgumentPointees,
/* hexagon_A2_abs */ DoesNotAccessMemory, /* hexagon_A2_abs */ DoesNotAccessMemory,
/* hexagon_A2_absp */ DoesNotAccessMemory, /* hexagon_A2_absp */ DoesNotAccessMemory,
/* hexagon_A2_abssat */ DoesNotAccessMemory, /* hexagon_A2_abssat */ DoesNotAccessMemory,
/* hexagon_A2_add */ DoesNotAccessMemory, /* hexagon_A2_add */ DoesNotAccessMemory,
/* hexagon_A2_addh_h16_hh */ DoesNotAccessMemory, /* hexagon_A2_addh_h16_hh */ DoesNotAccessMemory,
/* hexagon_A2_addh_h16_hl */ DoesNotAccessMemory, /* hexagon_A2_addh_h16_hl */ DoesNotAccessMemory,
/* hexagon_A2_addh_h16_lh */ DoesNotAccessMemory, /* hexagon_A2_addh_h16_lh */ DoesNotAccessMemory,
/* hexagon_A2_addh_h16_ll */ DoesNotAccessMemory, /* hexagon_A2_addh_h16_ll */ DoesNotAccessMemory,
/* hexagon_A2_addh_h16_sat_hh */ DoesNotAccessMemory, /* hexagon_A2_addh_h16_sat_hh */ DoesNotAccessMemory,
/* hexagon_A2_addh_h16_sat_hl */ DoesNotAccessMemory, /* hexagon_A2_addh_h16_sat_hl */ DoesNotAccessMemory,
/* hexagon_A2_addh_h16_sat_lh */ DoesNotAccessMemory, /* hexagon_A2_addh_h16_sat_lh */ DoesNotAccessMemory,
/* hexagon_A2_addh_h16_sat_ll */ DoesNotAccessMemory, /* hexagon_A2_addh_h16_sat_ll */ DoesNotAccessMemory,
/* hexagon_A2_addh_l16_hh */ DoesNotAccessMemory,
/* hexagon_A2_addh_l16_hl */ DoesNotAccessMemory, /* hexagon_A2_addh_l16_hl */ DoesNotAccessMemory,
/* hexagon_A2_addh_l16_lh */ DoesNotAccessMemory,
/* hexagon_A2_addh_l16_ll */ DoesNotAccessMemory, /* hexagon_A2_addh_l16_ll */ DoesNotAccessMemory,
/* hexagon_A2_addh_l16_sat_hh */ DoesNotAccessMemory,
/* hexagon_A2_addh_l16_sat_hl */ DoesNotAccessMemory, /* hexagon_A2_addh_l16_sat_hl */ DoesNotAccessMemory,
/* hexagon_A2_addh_l16_sat_lh */ DoesNotAccessMemory,
/* hexagon_A2_addh_l16_sat_ll */ DoesNotAccessMemory, /* hexagon_A2_addh_l16_sat_ll */ DoesNotAccessMemory,
/* hexagon_A2_addi */ DoesNotAccessMemory, /* hexagon_A2_addi */ DoesNotAccessMemory,
/* hexagon_A2_addp */ DoesNotAccessMemory, /* hexagon_A2_addp */ DoesNotAccessMemory,
/* hexagon_A2_addpsat */ DoesNotAccessMemory, /* hexagon_A2_addpsat */ DoesNotAccessMemory,
/* hexagon_A2_addsat */ DoesNotAccessMemory, /* hexagon_A2_addsat */ DoesNotAccessMemory,
/* hexagon_A2_addsp */ DoesNotAccessMemory, /* hexagon_A2_addsp */ DoesNotAccessMemory,
/* hexagon_A2_and */ DoesNotAccessMemory, /* hexagon_A2_and */ DoesNotAccessMemory,
/* hexagon_A2_andir */ DoesNotAccessMemory, /* hexagon_A2_andir */ DoesNotAccessMemory,
/* hexagon_A2_andp */ DoesNotAccessMemory, /* hexagon_A2_andp */ DoesNotAccessMemory,
/* hexagon_A2_aslh */ DoesNotAccessMemory, /* hexagon_A2_aslh */ DoesNotAccessMemory,
skipping to change at line 25292 skipping to change at line 25715
/* hexagon_A2_minu */ DoesNotAccessMemory, /* hexagon_A2_minu */ DoesNotAccessMemory,
/* hexagon_A2_minup */ DoesNotAccessMemory, /* hexagon_A2_minup */ DoesNotAccessMemory,
/* hexagon_A2_neg */ DoesNotAccessMemory, /* hexagon_A2_neg */ DoesNotAccessMemory,
/* hexagon_A2_negp */ DoesNotAccessMemory, /* hexagon_A2_negp */ DoesNotAccessMemory,
/* hexagon_A2_negsat */ DoesNotAccessMemory, /* hexagon_A2_negsat */ DoesNotAccessMemory,
/* hexagon_A2_not */ DoesNotAccessMemory, /* hexagon_A2_not */ DoesNotAccessMemory,
/* hexagon_A2_notp */ DoesNotAccessMemory, /* hexagon_A2_notp */ DoesNotAccessMemory,
/* hexagon_A2_or */ DoesNotAccessMemory, /* hexagon_A2_or */ DoesNotAccessMemory,
/* hexagon_A2_orir */ DoesNotAccessMemory, /* hexagon_A2_orir */ DoesNotAccessMemory,
/* hexagon_A2_orp */ DoesNotAccessMemory, /* hexagon_A2_orp */ DoesNotAccessMemory,
/* hexagon_A2_roundsat */ DoesNotAccessMemory,
/* hexagon_A2_sat */ DoesNotAccessMemory, /* hexagon_A2_sat */ DoesNotAccessMemory,
/* hexagon_A2_satb */ DoesNotAccessMemory, /* hexagon_A2_satb */ DoesNotAccessMemory,
/* hexagon_A2_sath */ DoesNotAccessMemory, /* hexagon_A2_sath */ DoesNotAccessMemory,
/* hexagon_A2_satub */ DoesNotAccessMemory, /* hexagon_A2_satub */ DoesNotAccessMemory,
/* hexagon_A2_satuh */ DoesNotAccessMemory, /* hexagon_A2_satuh */ DoesNotAccessMemory,
/* hexagon_A2_sub */ DoesNotAccessMemory, /* hexagon_A2_sub */ DoesNotAccessMemory,
/* hexagon_A2_subh_h16_hh */ DoesNotAccessMemory, /* hexagon_A2_subh_h16_hh */ DoesNotAccessMemory,
/* hexagon_A2_subh_h16_hl */ DoesNotAccessMemory, /* hexagon_A2_subh_h16_hl */ DoesNotAccessMemory,
/* hexagon_A2_subh_h16_lh */ DoesNotAccessMemory, /* hexagon_A2_subh_h16_lh */ DoesNotAccessMemory,
/* hexagon_A2_subh_h16_ll */ DoesNotAccessMemory, /* hexagon_A2_subh_h16_ll */ DoesNotAccessMemory,
skipping to change at line 25336 skipping to change at line 25760
/* hexagon_A2_tfr */ DoesNotAccessMemory, /* hexagon_A2_tfr */ DoesNotAccessMemory,
/* hexagon_A2_tfrih */ DoesNotAccessMemory, /* hexagon_A2_tfrih */ DoesNotAccessMemory,
/* hexagon_A2_tfril */ DoesNotAccessMemory, /* hexagon_A2_tfril */ DoesNotAccessMemory,
/* hexagon_A2_tfrp */ DoesNotAccessMemory, /* hexagon_A2_tfrp */ DoesNotAccessMemory,
/* hexagon_A2_tfrpi */ DoesNotAccessMemory, /* hexagon_A2_tfrpi */ DoesNotAccessMemory,
/* hexagon_A2_tfrsi */ DoesNotAccessMemory, /* hexagon_A2_tfrsi */ DoesNotAccessMemory,
/* hexagon_A2_vabsh */ DoesNotAccessMemory, /* hexagon_A2_vabsh */ DoesNotAccessMemory,
/* hexagon_A2_vabshsat */ DoesNotAccessMemory, /* hexagon_A2_vabshsat */ DoesNotAccessMemory,
/* hexagon_A2_vabsw */ DoesNotAccessMemory, /* hexagon_A2_vabsw */ DoesNotAccessMemory,
/* hexagon_A2_vabswsat */ DoesNotAccessMemory, /* hexagon_A2_vabswsat */ DoesNotAccessMemory,
/* hexagon_A2_vaddb_map */ DoesNotAccessMemory,
/* hexagon_A2_vaddh */ DoesNotAccessMemory, /* hexagon_A2_vaddh */ DoesNotAccessMemory,
/* hexagon_A2_vaddhs */ DoesNotAccessMemory, /* hexagon_A2_vaddhs */ DoesNotAccessMemory,
/* hexagon_A2_vaddub */ DoesNotAccessMemory, /* hexagon_A2_vaddub */ DoesNotAccessMemory,
/* hexagon_A2_vaddubs */ DoesNotAccessMemory, /* hexagon_A2_vaddubs */ DoesNotAccessMemory,
/* hexagon_A2_vadduhs */ DoesNotAccessMemory, /* hexagon_A2_vadduhs */ DoesNotAccessMemory,
/* hexagon_A2_vaddw */ DoesNotAccessMemory, /* hexagon_A2_vaddw */ DoesNotAccessMemory,
/* hexagon_A2_vaddws */ DoesNotAccessMemory, /* hexagon_A2_vaddws */ DoesNotAccessMemory,
/* hexagon_A2_vavgh */ DoesNotAccessMemory, /* hexagon_A2_vavgh */ DoesNotAccessMemory,
/* hexagon_A2_vavghcr */ DoesNotAccessMemory, /* hexagon_A2_vavghcr */ DoesNotAccessMemory,
/* hexagon_A2_vavghr */ DoesNotAccessMemory, /* hexagon_A2_vavghr */ DoesNotAccessMemory,
skipping to change at line 25364 skipping to change at line 25789
/* hexagon_A2_vavgwr */ DoesNotAccessMemory, /* hexagon_A2_vavgwr */ DoesNotAccessMemory,
/* hexagon_A2_vcmpbeq */ DoesNotAccessMemory, /* hexagon_A2_vcmpbeq */ DoesNotAccessMemory,
/* hexagon_A2_vcmpbgtu */ DoesNotAccessMemory, /* hexagon_A2_vcmpbgtu */ DoesNotAccessMemory,
/* hexagon_A2_vcmpheq */ DoesNotAccessMemory, /* hexagon_A2_vcmpheq */ DoesNotAccessMemory,
/* hexagon_A2_vcmphgt */ DoesNotAccessMemory, /* hexagon_A2_vcmphgt */ DoesNotAccessMemory,
/* hexagon_A2_vcmphgtu */ DoesNotAccessMemory, /* hexagon_A2_vcmphgtu */ DoesNotAccessMemory,
/* hexagon_A2_vcmpweq */ DoesNotAccessMemory, /* hexagon_A2_vcmpweq */ DoesNotAccessMemory,
/* hexagon_A2_vcmpwgt */ DoesNotAccessMemory, /* hexagon_A2_vcmpwgt */ DoesNotAccessMemory,
/* hexagon_A2_vcmpwgtu */ DoesNotAccessMemory, /* hexagon_A2_vcmpwgtu */ DoesNotAccessMemory,
/* hexagon_A2_vconj */ DoesNotAccessMemory, /* hexagon_A2_vconj */ DoesNotAccessMemory,
/* hexagon_A2_vmaxb */ DoesNotAccessMemory,
/* hexagon_A2_vmaxh */ DoesNotAccessMemory, /* hexagon_A2_vmaxh */ DoesNotAccessMemory,
/* hexagon_A2_vmaxub */ DoesNotAccessMemory, /* hexagon_A2_vmaxub */ DoesNotAccessMemory,
/* hexagon_A2_vmaxuh */ DoesNotAccessMemory, /* hexagon_A2_vmaxuh */ DoesNotAccessMemory,
/* hexagon_A2_vmaxuw */ DoesNotAccessMemory, /* hexagon_A2_vmaxuw */ DoesNotAccessMemory,
/* hexagon_A2_vmaxw */ DoesNotAccessMemory, /* hexagon_A2_vmaxw */ DoesNotAccessMemory,
/* hexagon_A2_vminb */ DoesNotAccessMemory,
/* hexagon_A2_vminh */ DoesNotAccessMemory, /* hexagon_A2_vminh */ DoesNotAccessMemory,
/* hexagon_A2_vminub */ DoesNotAccessMemory, /* hexagon_A2_vminub */ DoesNotAccessMemory,
/* hexagon_A2_vminuh */ DoesNotAccessMemory, /* hexagon_A2_vminuh */ DoesNotAccessMemory,
/* hexagon_A2_vminuw */ DoesNotAccessMemory, /* hexagon_A2_vminuw */ DoesNotAccessMemory,
/* hexagon_A2_vminw */ DoesNotAccessMemory, /* hexagon_A2_vminw */ DoesNotAccessMemory,
/* hexagon_A2_vnavgh */ DoesNotAccessMemory, /* hexagon_A2_vnavgh */ DoesNotAccessMemory,
/* hexagon_A2_vnavghcr */ DoesNotAccessMemory, /* hexagon_A2_vnavghcr */ DoesNotAccessMemory,
/* hexagon_A2_vnavghr */ DoesNotAccessMemory, /* hexagon_A2_vnavghr */ DoesNotAccessMemory,
/* hexagon_A2_vnavgw */ DoesNotAccessMemory, /* hexagon_A2_vnavgw */ DoesNotAccessMemory,
/* hexagon_A2_vnavgwcr */ DoesNotAccessMemory, /* hexagon_A2_vnavgwcr */ DoesNotAccessMemory,
/* hexagon_A2_vnavgwr */ DoesNotAccessMemory, /* hexagon_A2_vnavgwr */ DoesNotAccessMemory,
/* hexagon_A2_vraddub */ DoesNotAccessMemory, /* hexagon_A2_vraddub */ DoesNotAccessMemory,
/* hexagon_A2_vraddub_acc */ DoesNotAccessMemory, /* hexagon_A2_vraddub_acc */ DoesNotAccessMemory,
/* hexagon_A2_vrsadub */ DoesNotAccessMemory, /* hexagon_A2_vrsadub */ DoesNotAccessMemory,
/* hexagon_A2_vrsadub_acc */ DoesNotAccessMemory, /* hexagon_A2_vrsadub_acc */ DoesNotAccessMemory,
/* hexagon_A2_vsubb_map */ DoesNotAccessMemory,
/* hexagon_A2_vsubh */ DoesNotAccessMemory, /* hexagon_A2_vsubh */ DoesNotAccessMemory,
/* hexagon_A2_vsubhs */ DoesNotAccessMemory, /* hexagon_A2_vsubhs */ DoesNotAccessMemory,
/* hexagon_A2_vsubub */ DoesNotAccessMemory, /* hexagon_A2_vsubub */ DoesNotAccessMemory,
/* hexagon_A2_vsububs */ DoesNotAccessMemory, /* hexagon_A2_vsububs */ DoesNotAccessMemory,
/* hexagon_A2_vsubuhs */ DoesNotAccessMemory, /* hexagon_A2_vsubuhs */ DoesNotAccessMemory,
/* hexagon_A2_vsubw */ DoesNotAccessMemory, /* hexagon_A2_vsubw */ DoesNotAccessMemory,
/* hexagon_A2_vsubws */ DoesNotAccessMemory, /* hexagon_A2_vsubws */ DoesNotAccessMemory,
/* hexagon_A2_xor */ DoesNotAccessMemory, /* hexagon_A2_xor */ DoesNotAccessMemory,
/* hexagon_A2_xorp */ DoesNotAccessMemory, /* hexagon_A2_xorp */ DoesNotAccessMemory,
/* hexagon_A2_zxtb */ DoesNotAccessMemory, /* hexagon_A2_zxtb */ DoesNotAccessMemory,
/* hexagon_A2_zxth */ DoesNotAccessMemory, /* hexagon_A2_zxth */ DoesNotAccessMemory,
/* hexagon_A4_andn */ DoesNotAccessMemory, /* hexagon_A4_andn */ DoesNotAccessMemory,
/* hexagon_A4_andnp */ DoesNotAccessMemory, /* hexagon_A4_andnp */ DoesNotAccessMemory,
/* hexagon_A4_bitsplit */ DoesNotAccessMemory,
/* hexagon_A4_bitspliti */ DoesNotAccessMemory,
/* hexagon_A4_boundscheck */ DoesNotAccessMemory,
/* hexagon_A4_cmpbeq */ DoesNotAccessMemory,
/* hexagon_A4_cmpbeqi */ DoesNotAccessMemory,
/* hexagon_A4_cmpbgt */ DoesNotAccessMemory,
/* hexagon_A4_cmpbgti */ DoesNotAccessMemory,
/* hexagon_A4_cmpbgtu */ DoesNotAccessMemory,
/* hexagon_A4_cmpbgtui */ DoesNotAccessMemory,
/* hexagon_A4_cmpheq */ DoesNotAccessMemory,
/* hexagon_A4_cmpheqi */ DoesNotAccessMemory,
/* hexagon_A4_cmphgt */ DoesNotAccessMemory,
/* hexagon_A4_cmphgti */ DoesNotAccessMemory,
/* hexagon_A4_cmphgtu */ DoesNotAccessMemory,
/* hexagon_A4_cmphgtui */ DoesNotAccessMemory,
/* hexagon_A4_combineir */ DoesNotAccessMemory, /* hexagon_A4_combineir */ DoesNotAccessMemory,
/* hexagon_A4_combineri */ DoesNotAccessMemory, /* hexagon_A4_combineri */ DoesNotAccessMemory,
/* hexagon_A4_cround_ri */ DoesNotAccessMemory, /* hexagon_A4_cround_ri */ DoesNotAccessMemory,
/* hexagon_A4_cround_rr */ DoesNotAccessMemory, /* hexagon_A4_cround_rr */ DoesNotAccessMemory,
/* hexagon_A4_modwrapu */ DoesNotAccessMemory, /* hexagon_A4_modwrapu */ DoesNotAccessMemory,
/* hexagon_A4_orn */ DoesNotAccessMemory, /* hexagon_A4_orn */ DoesNotAccessMemory,
/* hexagon_A4_ornp */ DoesNotAccessMemory, /* hexagon_A4_ornp */ DoesNotAccessMemory,
/* hexagon_A4_rcmpeq */ DoesNotAccessMemory, /* hexagon_A4_rcmpeq */ DoesNotAccessMemory,
/* hexagon_A4_rcmpeqi */ DoesNotAccessMemory, /* hexagon_A4_rcmpeqi */ DoesNotAccessMemory,
/* hexagon_A4_rcmpneq */ DoesNotAccessMemory, /* hexagon_A4_rcmpneq */ DoesNotAccessMemory,
/* hexagon_A4_rcmpneqi */ DoesNotAccessMemory, /* hexagon_A4_rcmpneqi */ DoesNotAccessMemory,
/* hexagon_A4_round_ri */ DoesNotAccessMemory, /* hexagon_A4_round_ri */ DoesNotAccessMemory,
/* hexagon_A4_round_ri_sat */ DoesNotAccessMemory, /* hexagon_A4_round_ri_sat */ DoesNotAccessMemory,
/* hexagon_A4_round_rr */ DoesNotAccessMemory, /* hexagon_A4_round_rr */ DoesNotAccessMemory,
/* hexagon_A4_round_rr_sat */ DoesNotAccessMemory, /* hexagon_A4_round_rr_sat */ DoesNotAccessMemory,
/* hexagon_A4_tlbmatch */ DoesNotAccessMemory,
/* hexagon_A4_vcmpbeq_any */ DoesNotAccessMemory,
/* hexagon_A4_vcmpbeqi */ DoesNotAccessMemory,
/* hexagon_A4_vcmpbgt */ DoesNotAccessMemory,
/* hexagon_A4_vcmpbgti */ DoesNotAccessMemory,
/* hexagon_A4_vcmpbgtui */ DoesNotAccessMemory,
/* hexagon_A4_vcmpheqi */ DoesNotAccessMemory,
/* hexagon_A4_vcmphgti */ DoesNotAccessMemory,
/* hexagon_A4_vcmphgtui */ DoesNotAccessMemory,
/* hexagon_A4_vcmpweqi */ DoesNotAccessMemory,
/* hexagon_A4_vcmpwgti */ DoesNotAccessMemory,
/* hexagon_A4_vcmpwgtui */ DoesNotAccessMemory,
/* hexagon_A4_vrmaxh */ DoesNotAccessMemory,
/* hexagon_A4_vrmaxuh */ DoesNotAccessMemory,
/* hexagon_A4_vrmaxuw */ DoesNotAccessMemory,
/* hexagon_A4_vrmaxw */ DoesNotAccessMemory,
/* hexagon_A4_vrminh */ DoesNotAccessMemory,
/* hexagon_A4_vrminuh */ DoesNotAccessMemory,
/* hexagon_A4_vrminuw */ DoesNotAccessMemory,
/* hexagon_A4_vrminw */ DoesNotAccessMemory,
/* hexagon_A5_vaddhubs */ DoesNotAccessMemory,
/* hexagon_C2_all8 */ DoesNotAccessMemory, /* hexagon_C2_all8 */ DoesNotAccessMemory,
/* hexagon_C2_and */ DoesNotAccessMemory, /* hexagon_C2_and */ DoesNotAccessMemory,
/* hexagon_C2_andn */ DoesNotAccessMemory, /* hexagon_C2_andn */ DoesNotAccessMemory,
/* hexagon_C2_any8 */ DoesNotAccessMemory, /* hexagon_C2_any8 */ DoesNotAccessMemory,
/* hexagon_C2_bitsclr */ DoesNotAccessMemory, /* hexagon_C2_bitsclr */ DoesNotAccessMemory,
/* hexagon_C2_bitsclri */ DoesNotAccessMemory, /* hexagon_C2_bitsclri */ DoesNotAccessMemory,
/* hexagon_C2_bitsset */ DoesNotAccessMemory, /* hexagon_C2_bitsset */ DoesNotAccessMemory,
/* hexagon_C2_cmpeq */ DoesNotAccessMemory, /* hexagon_C2_cmpeq */ DoesNotAccessMemory,
/* hexagon_C2_cmpeqi */ DoesNotAccessMemory, /* hexagon_C2_cmpeqi */ DoesNotAccessMemory,
/* hexagon_C2_cmpeqp */ DoesNotAccessMemory, /* hexagon_C2_cmpeqp */ DoesNotAccessMemory,
skipping to change at line 25458 skipping to change at line 25922
/* hexagon_C4_and_or */ DoesNotAccessMemory, /* hexagon_C4_and_or */ DoesNotAccessMemory,
/* hexagon_C4_and_orn */ DoesNotAccessMemory, /* hexagon_C4_and_orn */ DoesNotAccessMemory,
/* hexagon_C4_cmplte */ DoesNotAccessMemory, /* hexagon_C4_cmplte */ DoesNotAccessMemory,
/* hexagon_C4_cmpltei */ DoesNotAccessMemory, /* hexagon_C4_cmpltei */ DoesNotAccessMemory,
/* hexagon_C4_cmplteu */ DoesNotAccessMemory, /* hexagon_C4_cmplteu */ DoesNotAccessMemory,
/* hexagon_C4_cmplteui */ DoesNotAccessMemory, /* hexagon_C4_cmplteui */ DoesNotAccessMemory,
/* hexagon_C4_cmpneq */ DoesNotAccessMemory, /* hexagon_C4_cmpneq */ DoesNotAccessMemory,
/* hexagon_C4_cmpneqi */ DoesNotAccessMemory, /* hexagon_C4_cmpneqi */ DoesNotAccessMemory,
/* hexagon_C4_fastcorner9 */ DoesNotAccessMemory, /* hexagon_C4_fastcorner9 */ DoesNotAccessMemory,
/* hexagon_C4_fastcorner9_not */ DoesNotAccessMemory, /* hexagon_C4_fastcorner9_not */ DoesNotAccessMemory,
/* hexagon_C4_nbitsclr */ DoesNotAccessMemory,
/* hexagon_C4_nbitsclri */ DoesNotAccessMemory,
/* hexagon_C4_nbitsset */ DoesNotAccessMemory,
/* hexagon_C4_or_and */ DoesNotAccessMemory, /* hexagon_C4_or_and */ DoesNotAccessMemory,
/* hexagon_C4_or_andn */ DoesNotAccessMemory, /* hexagon_C4_or_andn */ DoesNotAccessMemory,
/* hexagon_C4_or_or */ DoesNotAccessMemory, /* hexagon_C4_or_or */ DoesNotAccessMemory,
/* hexagon_C4_or_orn */ DoesNotAccessMemory, /* hexagon_C4_or_orn */ DoesNotAccessMemory,
/* hexagon_F2_conv_d2df */ DoesNotAccessMemory,
/* hexagon_F2_conv_d2sf */ DoesNotAccessMemory,
/* hexagon_F2_conv_df2d */ DoesNotAccessMemory,
/* hexagon_F2_conv_df2d_chop */ DoesNotAccessMemory,
/* hexagon_F2_conv_df2sf */ DoesNotAccessMemory,
/* hexagon_F2_conv_df2ud */ DoesNotAccessMemory,
/* hexagon_F2_conv_df2ud_chop */ DoesNotAccessMemory,
/* hexagon_F2_conv_df2uw */ DoesNotAccessMemory,
/* hexagon_F2_conv_df2uw_chop */ DoesNotAccessMemory,
/* hexagon_F2_conv_df2w */ DoesNotAccessMemory,
/* hexagon_F2_conv_df2w_chop */ DoesNotAccessMemory,
/* hexagon_F2_conv_sf2d */ DoesNotAccessMemory,
/* hexagon_F2_conv_sf2d_chop */ DoesNotAccessMemory,
/* hexagon_F2_conv_sf2df */ DoesNotAccessMemory,
/* hexagon_F2_conv_sf2ud */ DoesNotAccessMemory,
/* hexagon_F2_conv_sf2ud_chop */ DoesNotAccessMemory,
/* hexagon_F2_conv_sf2uw */ DoesNotAccessMemory,
/* hexagon_F2_conv_sf2uw_chop */ DoesNotAccessMemory,
/* hexagon_F2_conv_sf2w */ DoesNotAccessMemory,
/* hexagon_F2_conv_sf2w_chop */ DoesNotAccessMemory,
/* hexagon_F2_conv_ud2df */ DoesNotAccessMemory,
/* hexagon_F2_conv_ud2sf */ DoesNotAccessMemory,
/* hexagon_F2_conv_uw2df */ DoesNotAccessMemory,
/* hexagon_F2_conv_uw2sf */ DoesNotAccessMemory,
/* hexagon_F2_conv_w2df */ DoesNotAccessMemory,
/* hexagon_F2_conv_w2sf */ DoesNotAccessMemory,
/* hexagon_F2_dfadd */ DoesNotAccessMemory,
/* hexagon_F2_dfclass */ DoesNotAccessMemory,
/* hexagon_F2_dfcmpeq */ DoesNotAccessMemory,
/* hexagon_F2_dfcmpge */ DoesNotAccessMemory,
/* hexagon_F2_dfcmpgt */ DoesNotAccessMemory,
/* hexagon_F2_dfcmpuo */ DoesNotAccessMemory,
/* hexagon_F2_dffixupd */ DoesNotAccessMemory,
/* hexagon_F2_dffixupn */ DoesNotAccessMemory,
/* hexagon_F2_dffixupr */ DoesNotAccessMemory,
/* hexagon_F2_dffma */ DoesNotAccessMemory,
/* hexagon_F2_dffma_lib */ DoesNotAccessMemory,
/* hexagon_F2_dffma_sc */ DoesNotAccessMemory,
/* hexagon_F2_dffms */ DoesNotAccessMemory,
/* hexagon_F2_dffms_lib */ DoesNotAccessMemory,
/* hexagon_F2_dfimm_n */ DoesNotAccessMemory,
/* hexagon_F2_dfimm_p */ DoesNotAccessMemory,
/* hexagon_F2_dfmax */ DoesNotAccessMemory,
/* hexagon_F2_dfmin */ DoesNotAccessMemory,
/* hexagon_F2_dfmpy */ DoesNotAccessMemory,
/* hexagon_F2_dfsub */ DoesNotAccessMemory,
/* hexagon_F2_sfadd */ DoesNotAccessMemory,
/* hexagon_F2_sfclass */ DoesNotAccessMemory,
/* hexagon_F2_sfcmpeq */ DoesNotAccessMemory,
/* hexagon_F2_sfcmpge */ DoesNotAccessMemory,
/* hexagon_F2_sfcmpgt */ DoesNotAccessMemory,
/* hexagon_F2_sfcmpuo */ DoesNotAccessMemory,
/* hexagon_F2_sffixupd */ DoesNotAccessMemory,
/* hexagon_F2_sffixupn */ DoesNotAccessMemory,
/* hexagon_F2_sffixupr */ DoesNotAccessMemory,
/* hexagon_F2_sffma */ DoesNotAccessMemory,
/* hexagon_F2_sffma_lib */ DoesNotAccessMemory,
/* hexagon_F2_sffma_sc */ DoesNotAccessMemory,
/* hexagon_F2_sffms */ DoesNotAccessMemory,
/* hexagon_F2_sffms_lib */ DoesNotAccessMemory,
/* hexagon_F2_sfimm_n */ DoesNotAccessMemory,
/* hexagon_F2_sfimm_p */ DoesNotAccessMemory,
/* hexagon_F2_sfmax */ DoesNotAccessMemory,
/* hexagon_F2_sfmin */ DoesNotAccessMemory,
/* hexagon_F2_sfmpy */ DoesNotAccessMemory,
/* hexagon_F2_sfsub */ DoesNotAccessMemory,
/* hexagon_M2_acci */ DoesNotAccessMemory, /* hexagon_M2_acci */ DoesNotAccessMemory,
/* hexagon_M2_accii */ DoesNotAccessMemory, /* hexagon_M2_accii */ DoesNotAccessMemory,
/* hexagon_M2_cmaci_s0 */ DoesNotAccessMemory, /* hexagon_M2_cmaci_s0 */ DoesNotAccessMemory,
/* hexagon_M2_cmacr_s0 */ DoesNotAccessMemory, /* hexagon_M2_cmacr_s0 */ DoesNotAccessMemory,
/* hexagon_M2_cmacs_s0 */ DoesNotAccessMemory, /* hexagon_M2_cmacs_s0 */ DoesNotAccessMemory,
/* hexagon_M2_cmacs_s1 */ DoesNotAccessMemory, /* hexagon_M2_cmacs_s1 */ DoesNotAccessMemory,
/* hexagon_M2_cmacsc_s0 */ DoesNotAccessMemory, /* hexagon_M2_cmacsc_s0 */ DoesNotAccessMemory,
/* hexagon_M2_cmacsc_s1 */ DoesNotAccessMemory, /* hexagon_M2_cmacsc_s1 */ DoesNotAccessMemory,
/* hexagon_M2_cmpyi_s0 */ DoesNotAccessMemory, /* hexagon_M2_cmpyi_s0 */ DoesNotAccessMemory,
/* hexagon_M2_cmpyr_s0 */ DoesNotAccessMemory, /* hexagon_M2_cmpyr_s0 */ DoesNotAccessMemory,
skipping to change at line 25492 skipping to change at line 26025
/* hexagon_M2_cnacsc_s0 */ DoesNotAccessMemory, /* hexagon_M2_cnacsc_s0 */ DoesNotAccessMemory,
/* hexagon_M2_cnacsc_s1 */ DoesNotAccessMemory, /* hexagon_M2_cnacsc_s1 */ DoesNotAccessMemory,
/* hexagon_M2_dpmpyss_acc_s0 */ DoesNotAccessMemory, /* hexagon_M2_dpmpyss_acc_s0 */ DoesNotAccessMemory,
/* hexagon_M2_dpmpyss_nac_s0 */ DoesNotAccessMemory, /* hexagon_M2_dpmpyss_nac_s0 */ DoesNotAccessMemory,
/* hexagon_M2_dpmpyss_rnd_s0 */ DoesNotAccessMemory, /* hexagon_M2_dpmpyss_rnd_s0 */ DoesNotAccessMemory,
/* hexagon_M2_dpmpyss_s0 */ DoesNotAccessMemory, /* hexagon_M2_dpmpyss_s0 */ DoesNotAccessMemory,
/* hexagon_M2_dpmpyuu_acc_s0 */ DoesNotAccessMemory, /* hexagon_M2_dpmpyuu_acc_s0 */ DoesNotAccessMemory,
/* hexagon_M2_dpmpyuu_nac_s0 */ DoesNotAccessMemory, /* hexagon_M2_dpmpyuu_nac_s0 */ DoesNotAccessMemory,
/* hexagon_M2_dpmpyuu_s0 */ DoesNotAccessMemory, /* hexagon_M2_dpmpyuu_s0 */ DoesNotAccessMemory,
/* hexagon_M2_hmmpyh_rs1 */ DoesNotAccessMemory, /* hexagon_M2_hmmpyh_rs1 */ DoesNotAccessMemory,
/* hexagon_M2_hmmpyh_s1 */ DoesNotAccessMemory,
/* hexagon_M2_hmmpyl_rs1 */ DoesNotAccessMemory, /* hexagon_M2_hmmpyl_rs1 */ DoesNotAccessMemory,
/* hexagon_M2_hmmpyl_s1 */ DoesNotAccessMemory,
/* hexagon_M2_maci */ DoesNotAccessMemory, /* hexagon_M2_maci */ DoesNotAccessMemory,
/* hexagon_M2_macsin */ DoesNotAccessMemory, /* hexagon_M2_macsin */ DoesNotAccessMemory,
/* hexagon_M2_macsip */ DoesNotAccessMemory, /* hexagon_M2_macsip */ DoesNotAccessMemory,
/* hexagon_M2_mmachs_rs0 */ DoesNotAccessMemory, /* hexagon_M2_mmachs_rs0 */ DoesNotAccessMemory,
/* hexagon_M2_mmachs_rs1 */ DoesNotAccessMemory, /* hexagon_M2_mmachs_rs1 */ DoesNotAccessMemory,
/* hexagon_M2_mmachs_s0 */ DoesNotAccessMemory, /* hexagon_M2_mmachs_s0 */ DoesNotAccessMemory,
/* hexagon_M2_mmachs_s1 */ DoesNotAccessMemory, /* hexagon_M2_mmachs_s1 */ DoesNotAccessMemory,
/* hexagon_M2_mmacls_rs0 */ DoesNotAccessMemory, /* hexagon_M2_mmacls_rs0 */ DoesNotAccessMemory,
/* hexagon_M2_mmacls_rs1 */ DoesNotAccessMemory, /* hexagon_M2_mmacls_rs1 */ DoesNotAccessMemory,
/* hexagon_M2_mmacls_s0 */ DoesNotAccessMemory, /* hexagon_M2_mmacls_s0 */ DoesNotAccessMemory,
skipping to change at line 25593 skipping to change at line 26128
/* hexagon_M2_mpy_sat_ll_s1 */ DoesNotAccessMemory, /* hexagon_M2_mpy_sat_ll_s1 */ DoesNotAccessMemory,
/* hexagon_M2_mpy_sat_rnd_hh_s0 */ DoesNotAccessMemory, /* hexagon_M2_mpy_sat_rnd_hh_s0 */ DoesNotAccessMemory,
/* hexagon_M2_mpy_sat_rnd_hh_s1 */ DoesNotAccessMemory, /* hexagon_M2_mpy_sat_rnd_hh_s1 */ DoesNotAccessMemory,
/* hexagon_M2_mpy_sat_rnd_hl_s0 */ DoesNotAccessMemory, /* hexagon_M2_mpy_sat_rnd_hl_s0 */ DoesNotAccessMemory,
/* hexagon_M2_mpy_sat_rnd_hl_s1 */ DoesNotAccessMemory, /* hexagon_M2_mpy_sat_rnd_hl_s1 */ DoesNotAccessMemory,
/* hexagon_M2_mpy_sat_rnd_lh_s0 */ DoesNotAccessMemory, /* hexagon_M2_mpy_sat_rnd_lh_s0 */ DoesNotAccessMemory,
/* hexagon_M2_mpy_sat_rnd_lh_s1 */ DoesNotAccessMemory, /* hexagon_M2_mpy_sat_rnd_lh_s1 */ DoesNotAccessMemory,
/* hexagon_M2_mpy_sat_rnd_ll_s0 */ DoesNotAccessMemory, /* hexagon_M2_mpy_sat_rnd_ll_s0 */ DoesNotAccessMemory,
/* hexagon_M2_mpy_sat_rnd_ll_s1 */ DoesNotAccessMemory, /* hexagon_M2_mpy_sat_rnd_ll_s1 */ DoesNotAccessMemory,
/* hexagon_M2_mpy_up */ DoesNotAccessMemory, /* hexagon_M2_mpy_up */ DoesNotAccessMemory,
/* hexagon_M2_mpy_up_s1 */ DoesNotAccessMemory,
/* hexagon_M2_mpy_up_s1_sat */ DoesNotAccessMemory,
/* hexagon_M2_mpyd_acc_hh_s0 */ DoesNotAccessMemory, /* hexagon_M2_mpyd_acc_hh_s0 */ DoesNotAccessMemory,
/* hexagon_M2_mpyd_acc_hh_s1 */ DoesNotAccessMemory, /* hexagon_M2_mpyd_acc_hh_s1 */ DoesNotAccessMemory,
/* hexagon_M2_mpyd_acc_hl_s0 */ DoesNotAccessMemory, /* hexagon_M2_mpyd_acc_hl_s0 */ DoesNotAccessMemory,
/* hexagon_M2_mpyd_acc_hl_s1 */ DoesNotAccessMemory, /* hexagon_M2_mpyd_acc_hl_s1 */ DoesNotAccessMemory,
/* hexagon_M2_mpyd_acc_lh_s0 */ DoesNotAccessMemory, /* hexagon_M2_mpyd_acc_lh_s0 */ DoesNotAccessMemory,
/* hexagon_M2_mpyd_acc_lh_s1 */ DoesNotAccessMemory, /* hexagon_M2_mpyd_acc_lh_s1 */ DoesNotAccessMemory,
/* hexagon_M2_mpyd_acc_ll_s0 */ DoesNotAccessMemory, /* hexagon_M2_mpyd_acc_ll_s0 */ DoesNotAccessMemory,
/* hexagon_M2_mpyd_acc_ll_s1 */ DoesNotAccessMemory, /* hexagon_M2_mpyd_acc_ll_s1 */ DoesNotAccessMemory,
/* hexagon_M2_mpyd_hh_s0 */ DoesNotAccessMemory, /* hexagon_M2_mpyd_hh_s0 */ DoesNotAccessMemory,
/* hexagon_M2_mpyd_hh_s1 */ DoesNotAccessMemory, /* hexagon_M2_mpyd_hh_s1 */ DoesNotAccessMemory,
skipping to change at line 25627 skipping to change at line 26164
/* hexagon_M2_mpyd_rnd_hh_s0 */ DoesNotAccessMemory, /* hexagon_M2_mpyd_rnd_hh_s0 */ DoesNotAccessMemory,
/* hexagon_M2_mpyd_rnd_hh_s1 */ DoesNotAccessMemory, /* hexagon_M2_mpyd_rnd_hh_s1 */ DoesNotAccessMemory,
/* hexagon_M2_mpyd_rnd_hl_s0 */ DoesNotAccessMemory, /* hexagon_M2_mpyd_rnd_hl_s0 */ DoesNotAccessMemory,
/* hexagon_M2_mpyd_rnd_hl_s1 */ DoesNotAccessMemory, /* hexagon_M2_mpyd_rnd_hl_s1 */ DoesNotAccessMemory,
/* hexagon_M2_mpyd_rnd_lh_s0 */ DoesNotAccessMemory, /* hexagon_M2_mpyd_rnd_lh_s0 */ DoesNotAccessMemory,
/* hexagon_M2_mpyd_rnd_lh_s1 */ DoesNotAccessMemory, /* hexagon_M2_mpyd_rnd_lh_s1 */ DoesNotAccessMemory,
/* hexagon_M2_mpyd_rnd_ll_s0 */ DoesNotAccessMemory, /* hexagon_M2_mpyd_rnd_ll_s0 */ DoesNotAccessMemory,
/* hexagon_M2_mpyd_rnd_ll_s1 */ DoesNotAccessMemory, /* hexagon_M2_mpyd_rnd_ll_s1 */ DoesNotAccessMemory,
/* hexagon_M2_mpyi */ DoesNotAccessMemory, /* hexagon_M2_mpyi */ DoesNotAccessMemory,
/* hexagon_M2_mpysmi */ DoesNotAccessMemory, /* hexagon_M2_mpysmi */ DoesNotAccessMemory,
/* hexagon_M2_mpysu_up */ DoesNotAccessMemory,
/* hexagon_M2_mpyu_acc_hh_s0 */ DoesNotAccessMemory, /* hexagon_M2_mpyu_acc_hh_s0 */ DoesNotAccessMemory,
/* hexagon_M2_mpyu_acc_hh_s1 */ DoesNotAccessMemory, /* hexagon_M2_mpyu_acc_hh_s1 */ DoesNotAccessMemory,
/* hexagon_M2_mpyu_acc_hl_s0 */ DoesNotAccessMemory, /* hexagon_M2_mpyu_acc_hl_s0 */ DoesNotAccessMemory,
/* hexagon_M2_mpyu_acc_hl_s1 */ DoesNotAccessMemory, /* hexagon_M2_mpyu_acc_hl_s1 */ DoesNotAccessMemory,
/* hexagon_M2_mpyu_acc_lh_s0 */ DoesNotAccessMemory, /* hexagon_M2_mpyu_acc_lh_s0 */ DoesNotAccessMemory,
/* hexagon_M2_mpyu_acc_lh_s1 */ DoesNotAccessMemory, /* hexagon_M2_mpyu_acc_lh_s1 */ DoesNotAccessMemory,
/* hexagon_M2_mpyu_acc_ll_s0 */ DoesNotAccessMemory, /* hexagon_M2_mpyu_acc_ll_s0 */ DoesNotAccessMemory,
/* hexagon_M2_mpyu_acc_ll_s1 */ DoesNotAccessMemory, /* hexagon_M2_mpyu_acc_ll_s1 */ DoesNotAccessMemory,
/* hexagon_M2_mpyu_hh_s0 */ DoesNotAccessMemory, /* hexagon_M2_mpyu_hh_s0 */ DoesNotAccessMemory,
/* hexagon_M2_mpyu_hh_s1 */ DoesNotAccessMemory, /* hexagon_M2_mpyu_hh_s1 */ DoesNotAccessMemory,
skipping to change at line 25700 skipping to change at line 26238
/* hexagon_M2_vdmpyrs_s0 */ DoesNotAccessMemory, /* hexagon_M2_vdmpyrs_s0 */ DoesNotAccessMemory,
/* hexagon_M2_vdmpyrs_s1 */ DoesNotAccessMemory, /* hexagon_M2_vdmpyrs_s1 */ DoesNotAccessMemory,
/* hexagon_M2_vdmpys_s0 */ DoesNotAccessMemory, /* hexagon_M2_vdmpys_s0 */ DoesNotAccessMemory,
/* hexagon_M2_vdmpys_s1 */ DoesNotAccessMemory, /* hexagon_M2_vdmpys_s1 */ DoesNotAccessMemory,
/* hexagon_M2_vmac2 */ DoesNotAccessMemory, /* hexagon_M2_vmac2 */ DoesNotAccessMemory,
/* hexagon_M2_vmac2es */ DoesNotAccessMemory, /* hexagon_M2_vmac2es */ DoesNotAccessMemory,
/* hexagon_M2_vmac2es_s0 */ DoesNotAccessMemory, /* hexagon_M2_vmac2es_s0 */ DoesNotAccessMemory,
/* hexagon_M2_vmac2es_s1 */ DoesNotAccessMemory, /* hexagon_M2_vmac2es_s1 */ DoesNotAccessMemory,
/* hexagon_M2_vmac2s_s0 */ DoesNotAccessMemory, /* hexagon_M2_vmac2s_s0 */ DoesNotAccessMemory,
/* hexagon_M2_vmac2s_s1 */ DoesNotAccessMemory, /* hexagon_M2_vmac2s_s1 */ DoesNotAccessMemory,
/* hexagon_M2_vmac2su_s0 */ DoesNotAccessMemory,
/* hexagon_M2_vmac2su_s1 */ DoesNotAccessMemory,
/* hexagon_M2_vmpy2es_s0 */ DoesNotAccessMemory, /* hexagon_M2_vmpy2es_s0 */ DoesNotAccessMemory,
/* hexagon_M2_vmpy2es_s1 */ DoesNotAccessMemory, /* hexagon_M2_vmpy2es_s1 */ DoesNotAccessMemory,
/* hexagon_M2_vmpy2s_s0 */ DoesNotAccessMemory, /* hexagon_M2_vmpy2s_s0 */ DoesNotAccessMemory,
/* hexagon_M2_vmpy2s_s0pack */ DoesNotAccessMemory, /* hexagon_M2_vmpy2s_s0pack */ DoesNotAccessMemory,
/* hexagon_M2_vmpy2s_s1 */ DoesNotAccessMemory, /* hexagon_M2_vmpy2s_s1 */ DoesNotAccessMemory,
/* hexagon_M2_vmpy2s_s1pack */ DoesNotAccessMemory, /* hexagon_M2_vmpy2s_s1pack */ DoesNotAccessMemory,
/* hexagon_M2_vmpy2su_s0 */ DoesNotAccessMemory,
/* hexagon_M2_vmpy2su_s1 */ DoesNotAccessMemory,
/* hexagon_M2_vraddh */ DoesNotAccessMemory,
/* hexagon_M2_vradduh */ DoesNotAccessMemory, /* hexagon_M2_vradduh */ DoesNotAccessMemory,
/* hexagon_M2_vrcmaci_s0 */ DoesNotAccessMemory, /* hexagon_M2_vrcmaci_s0 */ DoesNotAccessMemory,
/* hexagon_M2_vrcmaci_s0c */ DoesNotAccessMemory, /* hexagon_M2_vrcmaci_s0c */ DoesNotAccessMemory,
/* hexagon_M2_vrcmacr_s0 */ DoesNotAccessMemory, /* hexagon_M2_vrcmacr_s0 */ DoesNotAccessMemory,
/* hexagon_M2_vrcmacr_s0c */ DoesNotAccessMemory, /* hexagon_M2_vrcmacr_s0c */ DoesNotAccessMemory,
/* hexagon_M2_vrcmpyi_s0 */ DoesNotAccessMemory, /* hexagon_M2_vrcmpyi_s0 */ DoesNotAccessMemory,
/* hexagon_M2_vrcmpyi_s0c */ DoesNotAccessMemory, /* hexagon_M2_vrcmpyi_s0c */ DoesNotAccessMemory,
/* hexagon_M2_vrcmpyr_s0 */ DoesNotAccessMemory, /* hexagon_M2_vrcmpyr_s0 */ DoesNotAccessMemory,
/* hexagon_M2_vrcmpyr_s0c */ DoesNotAccessMemory, /* hexagon_M2_vrcmpyr_s0c */ DoesNotAccessMemory,
/* hexagon_M2_vrcmpys_acc_s1 */ DoesNotAccessMemory, /* hexagon_M2_vrcmpys_acc_s1 */ DoesNotAccessMemory,
/* hexagon_M2_vrcmpys_s1 */ DoesNotAccessMemory, /* hexagon_M2_vrcmpys_s1 */ DoesNotAccessMemory,
/* hexagon_M2_vrcmpys_s1rp */ DoesNotAccessMemory, /* hexagon_M2_vrcmpys_s1rp */ DoesNotAccessMemory,
/* hexagon_M2_vrmac_s0 */ DoesNotAccessMemory, /* hexagon_M2_vrmac_s0 */ DoesNotAccessMemory,
/* hexagon_M2_vrmpy_s0 */ DoesNotAccessMemory, /* hexagon_M2_vrmpy_s0 */ DoesNotAccessMemory,
/* hexagon_M2_xor_xacc */ DoesNotAccessMemory, /* hexagon_M2_xor_xacc */ DoesNotAccessMemory,
/* hexagon_M4_and_and */ DoesNotAccessMemory, /* hexagon_M4_and_and */ DoesNotAccessMemory,
/* hexagon_M4_and_andn */ DoesNotAccessMemory, /* hexagon_M4_and_andn */ DoesNotAccessMemory,
/* hexagon_M4_and_or */ DoesNotAccessMemory, /* hexagon_M4_and_or */ DoesNotAccessMemory,
/* hexagon_M4_and_xor */ DoesNotAccessMemory, /* hexagon_M4_and_xor */ DoesNotAccessMemory,
/* hexagon_M4_cmpyi_wh */ DoesNotAccessMemory,
/* hexagon_M4_cmpyi_whc */ DoesNotAccessMemory,
/* hexagon_M4_cmpyr_wh */ DoesNotAccessMemory,
/* hexagon_M4_cmpyr_whc */ DoesNotAccessMemory,
/* hexagon_M4_mac_up_s1_sat */ DoesNotAccessMemory,
/* hexagon_M4_mpyri_addi */ DoesNotAccessMemory,
/* hexagon_M4_mpyri_addr */ DoesNotAccessMemory,
/* hexagon_M4_mpyri_addr_u2 */ DoesNotAccessMemory,
/* hexagon_M4_mpyrr_addi */ DoesNotAccessMemory,
/* hexagon_M4_mpyrr_addr */ DoesNotAccessMemory,
/* hexagon_M4_nac_up_s1_sat */ DoesNotAccessMemory,
/* hexagon_M4_or_and */ DoesNotAccessMemory, /* hexagon_M4_or_and */ DoesNotAccessMemory,
/* hexagon_M4_or_andn */ DoesNotAccessMemory, /* hexagon_M4_or_andn */ DoesNotAccessMemory,
/* hexagon_M4_or_or */ DoesNotAccessMemory, /* hexagon_M4_or_or */ DoesNotAccessMemory,
/* hexagon_M4_or_xor */ DoesNotAccessMemory, /* hexagon_M4_or_xor */ DoesNotAccessMemory,
/* hexagon_M4_pmpyw */ DoesNotAccessMemory,
/* hexagon_M4_pmpyw_acc */ DoesNotAccessMemory,
/* hexagon_M4_vpmpyh */ DoesNotAccessMemory,
/* hexagon_M4_vpmpyh_acc */ DoesNotAccessMemory,
/* hexagon_M4_vrmpyeh_acc_s0 */ DoesNotAccessMemory,
/* hexagon_M4_vrmpyeh_acc_s1 */ DoesNotAccessMemory,
/* hexagon_M4_vrmpyeh_s0 */ DoesNotAccessMemory,
/* hexagon_M4_vrmpyeh_s1 */ DoesNotAccessMemory,
/* hexagon_M4_vrmpyoh_acc_s0 */ DoesNotAccessMemory,
/* hexagon_M4_vrmpyoh_acc_s1 */ DoesNotAccessMemory,
/* hexagon_M4_vrmpyoh_s0 */ DoesNotAccessMemory,
/* hexagon_M4_vrmpyoh_s1 */ DoesNotAccessMemory,
/* hexagon_M4_xor_and */ DoesNotAccessMemory, /* hexagon_M4_xor_and */ DoesNotAccessMemory,
/* hexagon_M4_xor_andn */ DoesNotAccessMemory, /* hexagon_M4_xor_andn */ DoesNotAccessMemory,
/* hexagon_M4_xor_or */ DoesNotAccessMemory, /* hexagon_M4_xor_or */ DoesNotAccessMemory,
/* hexagon_M4_xor_xacc */ DoesNotAccessMemory, /* hexagon_M4_xor_xacc */ DoesNotAccessMemory,
/* hexagon_M5_vdmacbsu */ DoesNotAccessMemory,
/* hexagon_M5_vdmpybsu */ DoesNotAccessMemory,
/* hexagon_M5_vmacbsu */ DoesNotAccessMemory,
/* hexagon_M5_vmacbuu */ DoesNotAccessMemory,
/* hexagon_M5_vmpybsu */ DoesNotAccessMemory,
/* hexagon_M5_vmpybuu */ DoesNotAccessMemory,
/* hexagon_M5_vrmacbsu */ DoesNotAccessMemory,
/* hexagon_M5_vrmacbuu */ DoesNotAccessMemory,
/* hexagon_M5_vrmpybsu */ DoesNotAccessMemory,
/* hexagon_M5_vrmpybuu */ DoesNotAccessMemory,
/* hexagon_S2_addasl_rrri */ DoesNotAccessMemory, /* hexagon_S2_addasl_rrri */ DoesNotAccessMemory,
/* hexagon_S2_asl_i_p */ DoesNotAccessMemory, /* hexagon_S2_asl_i_p */ DoesNotAccessMemory,
/* hexagon_S2_asl_i_p_acc */ DoesNotAccessMemory, /* hexagon_S2_asl_i_p_acc */ DoesNotAccessMemory,
/* hexagon_S2_asl_i_p_and */ DoesNotAccessMemory, /* hexagon_S2_asl_i_p_and */ DoesNotAccessMemory,
/* hexagon_S2_asl_i_p_nac */ DoesNotAccessMemory, /* hexagon_S2_asl_i_p_nac */ DoesNotAccessMemory,
/* hexagon_S2_asl_i_p_or */ DoesNotAccessMemory, /* hexagon_S2_asl_i_p_or */ DoesNotAccessMemory,
/* hexagon_S2_asl_i_p_xacc */ DoesNotAccessMemory, /* hexagon_S2_asl_i_p_xacc */ DoesNotAccessMemory,
/* hexagon_S2_asl_i_r */ DoesNotAccessMemory, /* hexagon_S2_asl_i_r */ DoesNotAccessMemory,
/* hexagon_S2_asl_i_r_acc */ DoesNotAccessMemory, /* hexagon_S2_asl_i_r_acc */ DoesNotAccessMemory,
/* hexagon_S2_asl_i_r_and */ DoesNotAccessMemory, /* hexagon_S2_asl_i_r_and */ DoesNotAccessMemory,
skipping to change at line 25754 skipping to change at line 26330
/* hexagon_S2_asl_i_r_or */ DoesNotAccessMemory, /* hexagon_S2_asl_i_r_or */ DoesNotAccessMemory,
/* hexagon_S2_asl_i_r_sat */ DoesNotAccessMemory, /* hexagon_S2_asl_i_r_sat */ DoesNotAccessMemory,
/* hexagon_S2_asl_i_r_xacc */ DoesNotAccessMemory, /* hexagon_S2_asl_i_r_xacc */ DoesNotAccessMemory,
/* hexagon_S2_asl_i_vh */ DoesNotAccessMemory, /* hexagon_S2_asl_i_vh */ DoesNotAccessMemory,
/* hexagon_S2_asl_i_vw */ DoesNotAccessMemory, /* hexagon_S2_asl_i_vw */ DoesNotAccessMemory,
/* hexagon_S2_asl_r_p */ DoesNotAccessMemory, /* hexagon_S2_asl_r_p */ DoesNotAccessMemory,
/* hexagon_S2_asl_r_p_acc */ DoesNotAccessMemory, /* hexagon_S2_asl_r_p_acc */ DoesNotAccessMemory,
/* hexagon_S2_asl_r_p_and */ DoesNotAccessMemory, /* hexagon_S2_asl_r_p_and */ DoesNotAccessMemory,
/* hexagon_S2_asl_r_p_nac */ DoesNotAccessMemory, /* hexagon_S2_asl_r_p_nac */ DoesNotAccessMemory,
/* hexagon_S2_asl_r_p_or */ DoesNotAccessMemory, /* hexagon_S2_asl_r_p_or */ DoesNotAccessMemory,
/* hexagon_S2_asl_r_p_xor */ DoesNotAccessMemory,
/* hexagon_S2_asl_r_r */ DoesNotAccessMemory, /* hexagon_S2_asl_r_r */ DoesNotAccessMemory,
/* hexagon_S2_asl_r_r_acc */ DoesNotAccessMemory, /* hexagon_S2_asl_r_r_acc */ DoesNotAccessMemory,
/* hexagon_S2_asl_r_r_and */ DoesNotAccessMemory, /* hexagon_S2_asl_r_r_and */ DoesNotAccessMemory,
/* hexagon_S2_asl_r_r_nac */ DoesNotAccessMemory, /* hexagon_S2_asl_r_r_nac */ DoesNotAccessMemory,
/* hexagon_S2_asl_r_r_or */ DoesNotAccessMemory, /* hexagon_S2_asl_r_r_or */ DoesNotAccessMemory,
/* hexagon_S2_asl_r_r_sat */ DoesNotAccessMemory, /* hexagon_S2_asl_r_r_sat */ DoesNotAccessMemory,
/* hexagon_S2_asl_r_vh */ DoesNotAccessMemory, /* hexagon_S2_asl_r_vh */ DoesNotAccessMemory,
/* hexagon_S2_asl_r_vw */ DoesNotAccessMemory, /* hexagon_S2_asl_r_vw */ DoesNotAccessMemory,
/* hexagon_S2_asr_i_p */ DoesNotAccessMemory, /* hexagon_S2_asr_i_p */ DoesNotAccessMemory,
/* hexagon_S2_asr_i_p_acc */ DoesNotAccessMemory, /* hexagon_S2_asr_i_p_acc */ DoesNotAccessMemory,
/* hexagon_S2_asr_i_p_and */ DoesNotAccessMemory, /* hexagon_S2_asr_i_p_and */ DoesNotAccessMemory,
/* hexagon_S2_asr_i_p_nac */ DoesNotAccessMemory, /* hexagon_S2_asr_i_p_nac */ DoesNotAccessMemory,
/* hexagon_S2_asr_i_p_or */ DoesNotAccessMemory, /* hexagon_S2_asr_i_p_or */ DoesNotAccessMemory,
/* hexagon_S2_asr_i_p_rnd */ DoesNotAccessMemory,
/* hexagon_S2_asr_i_p_rnd_goodsyntax */ DoesNotAccessMemory,
/* hexagon_S2_asr_i_r */ DoesNotAccessMemory, /* hexagon_S2_asr_i_r */ DoesNotAccessMemory,
/* hexagon_S2_asr_i_r_acc */ DoesNotAccessMemory, /* hexagon_S2_asr_i_r_acc */ DoesNotAccessMemory,
/* hexagon_S2_asr_i_r_and */ DoesNotAccessMemory, /* hexagon_S2_asr_i_r_and */ DoesNotAccessMemory,
/* hexagon_S2_asr_i_r_nac */ DoesNotAccessMemory, /* hexagon_S2_asr_i_r_nac */ DoesNotAccessMemory,
/* hexagon_S2_asr_i_r_or */ DoesNotAccessMemory, /* hexagon_S2_asr_i_r_or */ DoesNotAccessMemory,
/* hexagon_S2_asr_i_r_rnd */ DoesNotAccessMemory, /* hexagon_S2_asr_i_r_rnd */ DoesNotAccessMemory,
/* hexagon_S2_asr_i_r_rnd_goodsyntax */ DoesNotAccessMemory, /* hexagon_S2_asr_i_r_rnd_goodsyntax */ DoesNotAccessMemory,
/* hexagon_S2_asr_i_svw_trun */ DoesNotAccessMemory, /* hexagon_S2_asr_i_svw_trun */ DoesNotAccessMemory,
/* hexagon_S2_asr_i_vh */ DoesNotAccessMemory, /* hexagon_S2_asr_i_vh */ DoesNotAccessMemory,
/* hexagon_S2_asr_i_vw */ DoesNotAccessMemory, /* hexagon_S2_asr_i_vw */ DoesNotAccessMemory,
/* hexagon_S2_asr_r_p */ DoesNotAccessMemory, /* hexagon_S2_asr_r_p */ DoesNotAccessMemory,
/* hexagon_S2_asr_r_p_acc */ DoesNotAccessMemory, /* hexagon_S2_asr_r_p_acc */ DoesNotAccessMemory,
/* hexagon_S2_asr_r_p_and */ DoesNotAccessMemory, /* hexagon_S2_asr_r_p_and */ DoesNotAccessMemory,
/* hexagon_S2_asr_r_p_nac */ DoesNotAccessMemory, /* hexagon_S2_asr_r_p_nac */ DoesNotAccessMemory,
/* hexagon_S2_asr_r_p_or */ DoesNotAccessMemory, /* hexagon_S2_asr_r_p_or */ DoesNotAccessMemory,
/* hexagon_S2_asr_r_p_xor */ DoesNotAccessMemory,
/* hexagon_S2_asr_r_r */ DoesNotAccessMemory, /* hexagon_S2_asr_r_r */ DoesNotAccessMemory,
/* hexagon_S2_asr_r_r_acc */ DoesNotAccessMemory, /* hexagon_S2_asr_r_r_acc */ DoesNotAccessMemory,
/* hexagon_S2_asr_r_r_and */ DoesNotAccessMemory, /* hexagon_S2_asr_r_r_and */ DoesNotAccessMemory,
/* hexagon_S2_asr_r_r_nac */ DoesNotAccessMemory, /* hexagon_S2_asr_r_r_nac */ DoesNotAccessMemory,
/* hexagon_S2_asr_r_r_or */ DoesNotAccessMemory, /* hexagon_S2_asr_r_r_or */ DoesNotAccessMemory,
/* hexagon_S2_asr_r_r_sat */ DoesNotAccessMemory, /* hexagon_S2_asr_r_r_sat */ DoesNotAccessMemory,
/* hexagon_S2_asr_r_svw_trun */ DoesNotAccessMemory, /* hexagon_S2_asr_r_svw_trun */ DoesNotAccessMemory,
/* hexagon_S2_asr_r_vh */ DoesNotAccessMemory, /* hexagon_S2_asr_r_vh */ DoesNotAccessMemory,
/* hexagon_S2_asr_r_vw */ DoesNotAccessMemory, /* hexagon_S2_asr_r_vw */ DoesNotAccessMemory,
/* hexagon_S2_brev */ DoesNotAccessMemory, /* hexagon_S2_brev */ DoesNotAccessMemory,
/* hexagon_S2_brevp */ DoesNotAccessMemory,
/* hexagon_S2_cl0 */ DoesNotAccessMemory, /* hexagon_S2_cl0 */ DoesNotAccessMemory,
/* hexagon_S2_cl0p */ DoesNotAccessMemory, /* hexagon_S2_cl0p */ DoesNotAccessMemory,
/* hexagon_S2_cl1 */ DoesNotAccessMemory, /* hexagon_S2_cl1 */ DoesNotAccessMemory,
/* hexagon_S2_cl1p */ DoesNotAccessMemory, /* hexagon_S2_cl1p */ DoesNotAccessMemory,
/* hexagon_S2_clb */ DoesNotAccessMemory, /* hexagon_S2_clb */ DoesNotAccessMemory,
/* hexagon_S2_clbnorm */ DoesNotAccessMemory, /* hexagon_S2_clbnorm */ DoesNotAccessMemory,
/* hexagon_S2_clbp */ DoesNotAccessMemory, /* hexagon_S2_clbp */ DoesNotAccessMemory,
/* hexagon_S2_clrbit_i */ DoesNotAccessMemory, /* hexagon_S2_clrbit_i */ DoesNotAccessMemory,
/* hexagon_S2_clrbit_r */ DoesNotAccessMemory, /* hexagon_S2_clrbit_r */ DoesNotAccessMemory,
/* hexagon_S2_ct0 */ DoesNotAccessMemory, /* hexagon_S2_ct0 */ DoesNotAccessMemory,
/* hexagon_S2_ct0p */ DoesNotAccessMemory,
/* hexagon_S2_ct1 */ DoesNotAccessMemory, /* hexagon_S2_ct1 */ DoesNotAccessMemory,
/* hexagon_S2_ct1p */ DoesNotAccessMemory,
/* hexagon_S2_deinterleave */ DoesNotAccessMemory, /* hexagon_S2_deinterleave */ DoesNotAccessMemory,
/* hexagon_S2_extractu */ DoesNotAccessMemory, /* hexagon_S2_extractu */ DoesNotAccessMemory,
/* hexagon_S2_extractu_rp */ DoesNotAccessMemory, /* hexagon_S2_extractu_rp */ DoesNotAccessMemory,
/* hexagon_S2_extractup */ DoesNotAccessMemory, /* hexagon_S2_extractup */ DoesNotAccessMemory,
/* hexagon_S2_extractup_rp */ DoesNotAccessMemory, /* hexagon_S2_extractup_rp */ DoesNotAccessMemory,
/* hexagon_S2_insert */ DoesNotAccessMemory, /* hexagon_S2_insert */ DoesNotAccessMemory,
/* hexagon_S2_insert_rp */ DoesNotAccessMemory, /* hexagon_S2_insert_rp */ DoesNotAccessMemory,
/* hexagon_S2_insertp */ DoesNotAccessMemory, /* hexagon_S2_insertp */ DoesNotAccessMemory,
/* hexagon_S2_insertp_rp */ DoesNotAccessMemory, /* hexagon_S2_insertp_rp */ DoesNotAccessMemory,
/* hexagon_S2_interleave */ DoesNotAccessMemory, /* hexagon_S2_interleave */ DoesNotAccessMemory,
/* hexagon_S2_lfsp */ DoesNotAccessMemory, /* hexagon_S2_lfsp */ DoesNotAccessMemory,
/* hexagon_S2_lsl_r_p */ DoesNotAccessMemory, /* hexagon_S2_lsl_r_p */ DoesNotAccessMemory,
/* hexagon_S2_lsl_r_p_acc */ DoesNotAccessMemory, /* hexagon_S2_lsl_r_p_acc */ DoesNotAccessMemory,
/* hexagon_S2_lsl_r_p_and */ DoesNotAccessMemory, /* hexagon_S2_lsl_r_p_and */ DoesNotAccessMemory,
/* hexagon_S2_lsl_r_p_nac */ DoesNotAccessMemory, /* hexagon_S2_lsl_r_p_nac */ DoesNotAccessMemory,
/* hexagon_S2_lsl_r_p_or */ DoesNotAccessMemory, /* hexagon_S2_lsl_r_p_or */ DoesNotAccessMemory,
/* hexagon_S2_lsl_r_p_xor */ DoesNotAccessMemory,
/* hexagon_S2_lsl_r_r */ DoesNotAccessMemory, /* hexagon_S2_lsl_r_r */ DoesNotAccessMemory,
/* hexagon_S2_lsl_r_r_acc */ DoesNotAccessMemory, /* hexagon_S2_lsl_r_r_acc */ DoesNotAccessMemory,
/* hexagon_S2_lsl_r_r_and */ DoesNotAccessMemory, /* hexagon_S2_lsl_r_r_and */ DoesNotAccessMemory,
/* hexagon_S2_lsl_r_r_nac */ DoesNotAccessMemory, /* hexagon_S2_lsl_r_r_nac */ DoesNotAccessMemory,
/* hexagon_S2_lsl_r_r_or */ DoesNotAccessMemory, /* hexagon_S2_lsl_r_r_or */ DoesNotAccessMemory,
/* hexagon_S2_lsl_r_vh */ DoesNotAccessMemory, /* hexagon_S2_lsl_r_vh */ DoesNotAccessMemory,
/* hexagon_S2_lsl_r_vw */ DoesNotAccessMemory, /* hexagon_S2_lsl_r_vw */ DoesNotAccessMemory,
/* hexagon_S2_lsr_i_p */ DoesNotAccessMemory, /* hexagon_S2_lsr_i_p */ DoesNotAccessMemory,
/* hexagon_S2_lsr_i_p_acc */ DoesNotAccessMemory, /* hexagon_S2_lsr_i_p_acc */ DoesNotAccessMemory,
/* hexagon_S2_lsr_i_p_and */ DoesNotAccessMemory, /* hexagon_S2_lsr_i_p_and */ DoesNotAccessMemory,
skipping to change at line 25845 skipping to change at line 26429
/* hexagon_S2_lsr_i_r_nac */ DoesNotAccessMemory, /* hexagon_S2_lsr_i_r_nac */ DoesNotAccessMemory,
/* hexagon_S2_lsr_i_r_or */ DoesNotAccessMemory, /* hexagon_S2_lsr_i_r_or */ DoesNotAccessMemory,
/* hexagon_S2_lsr_i_r_xacc */ DoesNotAccessMemory, /* hexagon_S2_lsr_i_r_xacc */ DoesNotAccessMemory,
/* hexagon_S2_lsr_i_vh */ DoesNotAccessMemory, /* hexagon_S2_lsr_i_vh */ DoesNotAccessMemory,
/* hexagon_S2_lsr_i_vw */ DoesNotAccessMemory, /* hexagon_S2_lsr_i_vw */ DoesNotAccessMemory,
/* hexagon_S2_lsr_r_p */ DoesNotAccessMemory, /* hexagon_S2_lsr_r_p */ DoesNotAccessMemory,
/* hexagon_S2_lsr_r_p_acc */ DoesNotAccessMemory, /* hexagon_S2_lsr_r_p_acc */ DoesNotAccessMemory,
/* hexagon_S2_lsr_r_p_and */ DoesNotAccessMemory, /* hexagon_S2_lsr_r_p_and */ DoesNotAccessMemory,
/* hexagon_S2_lsr_r_p_nac */ DoesNotAccessMemory, /* hexagon_S2_lsr_r_p_nac */ DoesNotAccessMemory,
/* hexagon_S2_lsr_r_p_or */ DoesNotAccessMemory, /* hexagon_S2_lsr_r_p_or */ DoesNotAccessMemory,
/* hexagon_S2_lsr_r_p_xor */ DoesNotAccessMemory,
/* hexagon_S2_lsr_r_r */ DoesNotAccessMemory, /* hexagon_S2_lsr_r_r */ DoesNotAccessMemory,
/* hexagon_S2_lsr_r_r_acc */ DoesNotAccessMemory, /* hexagon_S2_lsr_r_r_acc */ DoesNotAccessMemory,
/* hexagon_S2_lsr_r_r_and */ DoesNotAccessMemory, /* hexagon_S2_lsr_r_r_and */ DoesNotAccessMemory,
/* hexagon_S2_lsr_r_r_nac */ DoesNotAccessMemory, /* hexagon_S2_lsr_r_r_nac */ DoesNotAccessMemory,
/* hexagon_S2_lsr_r_r_or */ DoesNotAccessMemory, /* hexagon_S2_lsr_r_r_or */ DoesNotAccessMemory,
/* hexagon_S2_lsr_r_vh */ DoesNotAccessMemory, /* hexagon_S2_lsr_r_vh */ DoesNotAccessMemory,
/* hexagon_S2_lsr_r_vw */ DoesNotAccessMemory, /* hexagon_S2_lsr_r_vw */ DoesNotAccessMemory,
/* hexagon_S2_packhl */ DoesNotAccessMemory, /* hexagon_S2_packhl */ DoesNotAccessMemory,
/* hexagon_S2_parityp */ DoesNotAccessMemory, /* hexagon_S2_parityp */ DoesNotAccessMemory,
/* hexagon_S2_setbit_i */ DoesNotAccessMemory, /* hexagon_S2_setbit_i */ DoesNotAccessMemory,
skipping to change at line 25872 skipping to change at line 26457
/* hexagon_S2_tableidxb_goodsyntax */ DoesNotAccessMemory, /* hexagon_S2_tableidxb_goodsyntax */ DoesNotAccessMemory,
/* hexagon_S2_tableidxd_goodsyntax */ DoesNotAccessMemory, /* hexagon_S2_tableidxd_goodsyntax */ DoesNotAccessMemory,
/* hexagon_S2_tableidxh_goodsyntax */ DoesNotAccessMemory, /* hexagon_S2_tableidxh_goodsyntax */ DoesNotAccessMemory,
/* hexagon_S2_tableidxw_goodsyntax */ DoesNotAccessMemory, /* hexagon_S2_tableidxw_goodsyntax */ DoesNotAccessMemory,
/* hexagon_S2_togglebit_i */ DoesNotAccessMemory, /* hexagon_S2_togglebit_i */ DoesNotAccessMemory,
/* hexagon_S2_togglebit_r */ DoesNotAccessMemory, /* hexagon_S2_togglebit_r */ DoesNotAccessMemory,
/* hexagon_S2_tstbit_i */ DoesNotAccessMemory, /* hexagon_S2_tstbit_i */ DoesNotAccessMemory,
/* hexagon_S2_tstbit_r */ DoesNotAccessMemory, /* hexagon_S2_tstbit_r */ DoesNotAccessMemory,
/* hexagon_S2_valignib */ DoesNotAccessMemory, /* hexagon_S2_valignib */ DoesNotAccessMemory,
/* hexagon_S2_valignrb */ DoesNotAccessMemory, /* hexagon_S2_valignrb */ DoesNotAccessMemory,
/* hexagon_S2_vcnegh */ DoesNotAccessMemory,
/* hexagon_S2_vcrotate */ DoesNotAccessMemory, /* hexagon_S2_vcrotate */ DoesNotAccessMemory,
/* hexagon_S2_vrcnegh */ DoesNotAccessMemory,
/* hexagon_S2_vrndpackwh */ DoesNotAccessMemory, /* hexagon_S2_vrndpackwh */ DoesNotAccessMemory,
/* hexagon_S2_vrndpackwhs */ DoesNotAccessMemory, /* hexagon_S2_vrndpackwhs */ DoesNotAccessMemory,
/* hexagon_S2_vsathb */ DoesNotAccessMemory, /* hexagon_S2_vsathb */ DoesNotAccessMemory,
/* hexagon_S2_vsathb_nopack */ DoesNotAccessMemory, /* hexagon_S2_vsathb_nopack */ DoesNotAccessMemory,
/* hexagon_S2_vsathub */ DoesNotAccessMemory, /* hexagon_S2_vsathub */ DoesNotAccessMemory,
/* hexagon_S2_vsathub_nopack */ DoesNotAccessMemory, /* hexagon_S2_vsathub_nopack */ DoesNotAccessMemory,
/* hexagon_S2_vsatwh */ DoesNotAccessMemory, /* hexagon_S2_vsatwh */ DoesNotAccessMemory,
/* hexagon_S2_vsatwh_nopack */ DoesNotAccessMemory, /* hexagon_S2_vsatwh_nopack */ DoesNotAccessMemory,
/* hexagon_S2_vsatwuh */ DoesNotAccessMemory, /* hexagon_S2_vsatwuh */ DoesNotAccessMemory,
/* hexagon_S2_vsatwuh_nopack */ DoesNotAccessMemory, /* hexagon_S2_vsatwuh_nopack */ DoesNotAccessMemory,
skipping to change at line 25896 skipping to change at line 26483
/* hexagon_S2_vsplicerb */ DoesNotAccessMemory, /* hexagon_S2_vsplicerb */ DoesNotAccessMemory,
/* hexagon_S2_vsxtbh */ DoesNotAccessMemory, /* hexagon_S2_vsxtbh */ DoesNotAccessMemory,
/* hexagon_S2_vsxthw */ DoesNotAccessMemory, /* hexagon_S2_vsxthw */ DoesNotAccessMemory,
/* hexagon_S2_vtrunehb */ DoesNotAccessMemory, /* hexagon_S2_vtrunehb */ DoesNotAccessMemory,
/* hexagon_S2_vtrunewh */ DoesNotAccessMemory, /* hexagon_S2_vtrunewh */ DoesNotAccessMemory,
/* hexagon_S2_vtrunohb */ DoesNotAccessMemory, /* hexagon_S2_vtrunohb */ DoesNotAccessMemory,
/* hexagon_S2_vtrunowh */ DoesNotAccessMemory, /* hexagon_S2_vtrunowh */ DoesNotAccessMemory,
/* hexagon_S2_vzxtbh */ DoesNotAccessMemory, /* hexagon_S2_vzxtbh */ DoesNotAccessMemory,
/* hexagon_S2_vzxthw */ DoesNotAccessMemory, /* hexagon_S2_vzxthw */ DoesNotAccessMemory,
/* hexagon_S4_addaddi */ DoesNotAccessMemory, /* hexagon_S4_addaddi */ DoesNotAccessMemory,
/* hexagon_S4_andnp */ DoesNotAccessMemory, /* hexagon_S4_addi_asl_ri */ DoesNotAccessMemory,
/* hexagon_S4_addi_lsr_ri */ DoesNotAccessMemory,
/* hexagon_S4_andi_asl_ri */ DoesNotAccessMemory,
/* hexagon_S4_andi_lsr_ri */ DoesNotAccessMemory,
/* hexagon_S4_clbaddi */ DoesNotAccessMemory,
/* hexagon_S4_clbpaddi */ DoesNotAccessMemory,
/* hexagon_S4_clbpnorm */ DoesNotAccessMemory,
/* hexagon_S4_extract */ DoesNotAccessMemory,
/* hexagon_S4_extract_rp */ DoesNotAccessMemory,
/* hexagon_S4_extractp */ DoesNotAccessMemory,
/* hexagon_S4_extractp_rp */ DoesNotAccessMemory,
/* hexagon_S4_lsli */ DoesNotAccessMemory,
/* hexagon_S4_ntstbit_i */ DoesNotAccessMemory,
/* hexagon_S4_ntstbit_r */ DoesNotAccessMemory,
/* hexagon_S4_or_andi */ DoesNotAccessMemory, /* hexagon_S4_or_andi */ DoesNotAccessMemory,
/* hexagon_S4_or_andix */ DoesNotAccessMemory, /* hexagon_S4_or_andix */ DoesNotAccessMemory,
/* hexagon_S4_or_ori */ DoesNotAccessMemory, /* hexagon_S4_or_ori */ DoesNotAccessMemory,
/* hexagon_S4_ornp */ DoesNotAccessMemory, /* hexagon_S4_ori_asl_ri */ DoesNotAccessMemory,
/* hexagon_S4_ori_lsr_ri */ DoesNotAccessMemory,
/* hexagon_S4_parity */ DoesNotAccessMemory,
/* hexagon_S4_subaddi */ DoesNotAccessMemory, /* hexagon_S4_subaddi */ DoesNotAccessMemory,
/* hexagon_S4_subi_asl_ri */ DoesNotAccessMemory,
/* hexagon_S4_subi_lsr_ri */ DoesNotAccessMemory,
/* hexagon_S4_vrcrotate */ DoesNotAccessMemory,
/* hexagon_S4_vrcrotate_acc */ DoesNotAccessMemory,
/* hexagon_S4_vxaddsubh */ DoesNotAccessMemory,
/* hexagon_S4_vxaddsubhr */ DoesNotAccessMemory,
/* hexagon_S4_vxaddsubw */ DoesNotAccessMemory,
/* hexagon_S4_vxsubaddh */ DoesNotAccessMemory,
/* hexagon_S4_vxsubaddhr */ DoesNotAccessMemory,
/* hexagon_S4_vxsubaddw */ DoesNotAccessMemory,
/* hexagon_S5_asrhub_rnd_sat_goodsyntax */ DoesNotAccessMemory,
/* hexagon_S5_asrhub_sat */ DoesNotAccessMemory,
/* hexagon_S5_popcountp */ DoesNotAccessMemory,
/* hexagon_S5_vasrhrnd_goodsyntax */ DoesNotAccessMemory,
/* hexagon_SI_to_SXTHI_asrh */ DoesNotAccessMemory, /* hexagon_SI_to_SXTHI_asrh */ DoesNotAccessMemory,
/* hexagon_circ_ldd */ OnlyAccessesArgumentPointees,
/* init_trampoline */ OnlyAccessesArgumentPointees, /* init_trampoline */ OnlyAccessesArgumentPointees,
/* invariant_end */ OnlyAccessesArgumentPointees, /* invariant_end */ OnlyAccessesArgumentPointees,
/* invariant_start */ OnlyAccessesArgumentPointees, /* invariant_start */ OnlyAccessesArgumentPointees,
/* lifetime_end */ OnlyAccessesArgumentPointees, /* lifetime_end */ OnlyAccessesArgumentPointees,
/* lifetime_start */ OnlyAccessesArgumentPointees, /* lifetime_start */ OnlyAccessesArgumentPointees,
/* log */ OnlyReadsMemory, /* log */ OnlyReadsMemory,
/* log10 */ OnlyReadsMemory, /* log10 */ OnlyReadsMemory,
/* log2 */ OnlyReadsMemory, /* log2 */ OnlyReadsMemory,
/* longjmp */ UnknownModRefBehavior, /* longjmp */ UnknownModRefBehavior,
/* memcpy */ OnlyAccessesArgumentPointees, /* memcpy */ OnlyAccessesArgumentPointees,
/* memmove */ OnlyAccessesArgumentPointees, /* memmove */ OnlyAccessesArgumentPointees,
/* memset */ OnlyAccessesArgumentPointees, /* memset */ OnlyAccessesArgumentPointees,
/* mips_absq_s_ph */ UnknownModRefBehavior,
/* mips_absq_s_qb */ UnknownModRefBehavior,
/* mips_absq_s_w */ UnknownModRefBehavior,
/* mips_addq_ph */ UnknownModRefBehavior,
/* mips_addq_s_ph */ UnknownModRefBehavior,
/* mips_addq_s_w */ UnknownModRefBehavior,
/* mips_addqh_ph */ DoesNotAccessMemory,
/* mips_addqh_r_ph */ DoesNotAccessMemory,
/* mips_addqh_r_w */ DoesNotAccessMemory,
/* mips_addqh_w */ DoesNotAccessMemory,
/* mips_addsc */ UnknownModRefBehavior,
/* mips_addu_ph */ UnknownModRefBehavior,
/* mips_addu_qb */ UnknownModRefBehavior,
/* mips_addu_s_ph */ UnknownModRefBehavior,
/* mips_addu_s_qb */ UnknownModRefBehavior,
/* mips_adduh_qb */ DoesNotAccessMemory,
/* mips_adduh_r_qb */ DoesNotAccessMemory,
/* mips_addwc */ UnknownModRefBehavior,
/* mips_append */ DoesNotAccessMemory,
/* mips_balign */ DoesNotAccessMemory,
/* mips_bitrev */ DoesNotAccessMemory,
/* mips_bposge32 */ OnlyReadsMemory,
/* mips_cmp_eq_ph */ UnknownModRefBehavior,
/* mips_cmp_le_ph */ UnknownModRefBehavior,
/* mips_cmp_lt_ph */ UnknownModRefBehavior,
/* mips_cmpgdu_eq_qb */ UnknownModRefBehavior,
/* mips_cmpgdu_le_qb */ UnknownModRefBehavior,
/* mips_cmpgdu_lt_qb */ UnknownModRefBehavior,
/* mips_cmpgu_eq_qb */ UnknownModRefBehavior,
/* mips_cmpgu_le_qb */ UnknownModRefBehavior,
/* mips_cmpgu_lt_qb */ UnknownModRefBehavior,
/* mips_cmpu_eq_qb */ UnknownModRefBehavior,
/* mips_cmpu_le_qb */ UnknownModRefBehavior,
/* mips_cmpu_lt_qb */ UnknownModRefBehavior,
/* mips_dpa_w_ph */ DoesNotAccessMemory,
/* mips_dpaq_s_w_ph */ UnknownModRefBehavior,
/* mips_dpaq_sa_l_w */ UnknownModRefBehavior,
/* mips_dpaqx_s_w_ph */ UnknownModRefBehavior,
/* mips_dpaqx_sa_w_ph */ UnknownModRefBehavior,
/* mips_dpau_h_qbl */ DoesNotAccessMemory,
/* mips_dpau_h_qbr */ DoesNotAccessMemory,
/* mips_dpax_w_ph */ DoesNotAccessMemory,
/* mips_dps_w_ph */ DoesNotAccessMemory,
/* mips_dpsq_s_w_ph */ UnknownModRefBehavior,
/* mips_dpsq_sa_l_w */ UnknownModRefBehavior,
/* mips_dpsqx_s_w_ph */ UnknownModRefBehavior,
/* mips_dpsqx_sa_w_ph */ UnknownModRefBehavior,
/* mips_dpsu_h_qbl */ DoesNotAccessMemory,
/* mips_dpsu_h_qbr */ DoesNotAccessMemory,
/* mips_dpsx_w_ph */ DoesNotAccessMemory,
/* mips_extp */ UnknownModRefBehavior,
/* mips_extpdp */ UnknownModRefBehavior,
/* mips_extr_r_w */ UnknownModRefBehavior,
/* mips_extr_rs_w */ UnknownModRefBehavior,
/* mips_extr_s_h */ UnknownModRefBehavior,
/* mips_extr_w */ UnknownModRefBehavior,
/* mips_insv */ OnlyReadsMemory,
/* mips_lbux */ OnlyReadsArgumentPointees,
/* mips_lhx */ OnlyReadsArgumentPointees,
/* mips_lwx */ OnlyReadsArgumentPointees,
/* mips_madd */ DoesNotAccessMemory,
/* mips_maddu */ DoesNotAccessMemory,
/* mips_maq_s_w_phl */ UnknownModRefBehavior,
/* mips_maq_s_w_phr */ UnknownModRefBehavior,
/* mips_maq_sa_w_phl */ UnknownModRefBehavior,
/* mips_maq_sa_w_phr */ UnknownModRefBehavior,
/* mips_modsub */ DoesNotAccessMemory,
/* mips_msub */ DoesNotAccessMemory,
/* mips_msubu */ DoesNotAccessMemory,
/* mips_mthlip */ UnknownModRefBehavior,
/* mips_mul_ph */ UnknownModRefBehavior,
/* mips_mul_s_ph */ UnknownModRefBehavior,
/* mips_muleq_s_w_phl */ UnknownModRefBehavior,
/* mips_muleq_s_w_phr */ UnknownModRefBehavior,
/* mips_muleu_s_ph_qbl */ UnknownModRefBehavior,
/* mips_muleu_s_ph_qbr */ UnknownModRefBehavior,
/* mips_mulq_rs_ph */ UnknownModRefBehavior,
/* mips_mulq_rs_w */ UnknownModRefBehavior,
/* mips_mulq_s_ph */ UnknownModRefBehavior,
/* mips_mulq_s_w */ UnknownModRefBehavior,
/* mips_mulsa_w_ph */ DoesNotAccessMemory,
/* mips_mulsaq_s_w_ph */ UnknownModRefBehavior,
/* mips_mult */ DoesNotAccessMemory,
/* mips_multu */ DoesNotAccessMemory,
/* mips_packrl_ph */ DoesNotAccessMemory,
/* mips_pick_ph */ OnlyReadsMemory,
/* mips_pick_qb */ OnlyReadsMemory,
/* mips_preceq_w_phl */ DoesNotAccessMemory,
/* mips_preceq_w_phr */ DoesNotAccessMemory,
/* mips_precequ_ph_qbl */ DoesNotAccessMemory,
/* mips_precequ_ph_qbla */ DoesNotAccessMemory,
/* mips_precequ_ph_qbr */ DoesNotAccessMemory,
/* mips_precequ_ph_qbra */ DoesNotAccessMemory,
/* mips_preceu_ph_qbl */ DoesNotAccessMemory,
/* mips_preceu_ph_qbla */ DoesNotAccessMemory,
/* mips_preceu_ph_qbr */ DoesNotAccessMemory,
/* mips_preceu_ph_qbra */ DoesNotAccessMemory,
/* mips_precr_qb_ph */ UnknownModRefBehavior,
/* mips_precr_sra_ph_w */ DoesNotAccessMemory,
/* mips_precr_sra_r_ph_w */ DoesNotAccessMemory,
/* mips_precrq_ph_w */ DoesNotAccessMemory,
/* mips_precrq_qb_ph */ DoesNotAccessMemory,
/* mips_precrq_rs_ph_w */ UnknownModRefBehavior,
/* mips_precrqu_s_qb_ph */ UnknownModRefBehavior,
/* mips_prepend */ DoesNotAccessMemory,
/* mips_raddu_w_qb */ DoesNotAccessMemory,
/* mips_rddsp */ OnlyReadsMemory,
/* mips_repl_ph */ DoesNotAccessMemory,
/* mips_repl_qb */ DoesNotAccessMemory,
/* mips_shilo */ DoesNotAccessMemory,
/* mips_shll_ph */ UnknownModRefBehavior,
/* mips_shll_qb */ UnknownModRefBehavior,
/* mips_shll_s_ph */ UnknownModRefBehavior,
/* mips_shll_s_w */ UnknownModRefBehavior,
/* mips_shra_ph */ DoesNotAccessMemory,
/* mips_shra_qb */ DoesNotAccessMemory,
/* mips_shra_r_ph */ DoesNotAccessMemory,
/* mips_shra_r_qb */ DoesNotAccessMemory,
/* mips_shra_r_w */ DoesNotAccessMemory,
/* mips_shrl_ph */ DoesNotAccessMemory,
/* mips_shrl_qb */ DoesNotAccessMemory,
/* mips_subq_ph */ UnknownModRefBehavior,
/* mips_subq_s_ph */ UnknownModRefBehavior,
/* mips_subq_s_w */ UnknownModRefBehavior,
/* mips_subqh_ph */ DoesNotAccessMemory,
/* mips_subqh_r_ph */ DoesNotAccessMemory,
/* mips_subqh_r_w */ DoesNotAccessMemory,
/* mips_subqh_w */ DoesNotAccessMemory,
/* mips_subu_ph */ UnknownModRefBehavior,
/* mips_subu_qb */ UnknownModRefBehavior,
/* mips_subu_s_ph */ UnknownModRefBehavior,
/* mips_subu_s_qb */ UnknownModRefBehavior,
/* mips_subuh_qb */ DoesNotAccessMemory,
/* mips_subuh_r_qb */ DoesNotAccessMemory,
/* mips_wrdsp */ UnknownModRefBehavior,
/* nvvm_abs_i */ DoesNotAccessMemory,
/* nvvm_abs_ll */ DoesNotAccessMemory,
/* nvvm_add_rm_d */ DoesNotAccessMemory,
/* nvvm_add_rm_f */ DoesNotAccessMemory,
/* nvvm_add_rm_ftz_f */ DoesNotAccessMemory,
/* nvvm_add_rn_d */ DoesNotAccessMemory,
/* nvvm_add_rn_f */ DoesNotAccessMemory,
/* nvvm_add_rn_ftz_f */ DoesNotAccessMemory,
/* nvvm_add_rp_d */ DoesNotAccessMemory,
/* nvvm_add_rp_f */ DoesNotAccessMemory,
/* nvvm_add_rp_ftz_f */ DoesNotAccessMemory,
/* nvvm_add_rz_d */ DoesNotAccessMemory,
/* nvvm_add_rz_f */ DoesNotAccessMemory,
/* nvvm_add_rz_ftz_f */ DoesNotAccessMemory,
/* nvvm_atomic_load_add_f32 */ OnlyAccessesArgumentPointees,
/* nvvm_atomic_load_dec_32 */ OnlyAccessesArgumentPointees,
/* nvvm_atomic_load_inc_32 */ OnlyAccessesArgumentPointees,
/* nvvm_barrier0 */ UnknownModRefBehavior,
/* nvvm_barrier0_and */ UnknownModRefBehavior,
/* nvvm_barrier0_or */ UnknownModRefBehavior,
/* nvvm_barrier0_popc */ UnknownModRefBehavior,
/* nvvm_bitcast_d2ll */ DoesNotAccessMemory,
/* nvvm_bitcast_f2i */ DoesNotAccessMemory,
/* nvvm_bitcast_i2f */ DoesNotAccessMemory,
/* nvvm_bitcast_ll2d */ DoesNotAccessMemory,
/* nvvm_brev32 */ DoesNotAccessMemory,
/* nvvm_brev64 */ DoesNotAccessMemory,
/* nvvm_ceil_d */ DoesNotAccessMemory,
/* nvvm_ceil_f */ DoesNotAccessMemory,
/* nvvm_ceil_ftz_f */ DoesNotAccessMemory,
/* nvvm_clz_i */ DoesNotAccessMemory,
/* nvvm_clz_ll */ DoesNotAccessMemory,
/* nvvm_compiler_error */ UnknownModRefBehavior,
/* nvvm_compiler_warn */ UnknownModRefBehavior,
/* nvvm_cos_approx_f */ DoesNotAccessMemory,
/* nvvm_cos_approx_ftz_f */ DoesNotAccessMemory,
/* nvvm_d2f_rm */ DoesNotAccessMemory,
/* nvvm_d2f_rm_ftz */ DoesNotAccessMemory,
/* nvvm_d2f_rn */ DoesNotAccessMemory,
/* nvvm_d2f_rn_ftz */ DoesNotAccessMemory,
/* nvvm_d2f_rp */ DoesNotAccessMemory,
/* nvvm_d2f_rp_ftz */ DoesNotAccessMemory,
/* nvvm_d2f_rz */ DoesNotAccessMemory,
/* nvvm_d2f_rz_ftz */ DoesNotAccessMemory,
/* nvvm_d2i_hi */ DoesNotAccessMemory,
/* nvvm_d2i_lo */ DoesNotAccessMemory,
/* nvvm_d2i_rm */ DoesNotAccessMemory,
/* nvvm_d2i_rn */ DoesNotAccessMemory,
/* nvvm_d2i_rp */ DoesNotAccessMemory,
/* nvvm_d2i_rz */ DoesNotAccessMemory,
/* nvvm_d2ll_rm */ DoesNotAccessMemory,
/* nvvm_d2ll_rn */ DoesNotAccessMemory,
/* nvvm_d2ll_rp */ DoesNotAccessMemory,
/* nvvm_d2ll_rz */ DoesNotAccessMemory,
/* nvvm_d2ui_rm */ DoesNotAccessMemory,
/* nvvm_d2ui_rn */ DoesNotAccessMemory,
/* nvvm_d2ui_rp */ DoesNotAccessMemory,
/* nvvm_d2ui_rz */ DoesNotAccessMemory,
/* nvvm_d2ull_rm */ DoesNotAccessMemory,
/* nvvm_d2ull_rn */ DoesNotAccessMemory,
/* nvvm_d2ull_rp */ DoesNotAccessMemory,
/* nvvm_d2ull_rz */ DoesNotAccessMemory,
/* nvvm_div_approx_f */ DoesNotAccessMemory,
/* nvvm_div_approx_ftz_f */ DoesNotAccessMemory,
/* nvvm_div_rm_d */ DoesNotAccessMemory,
/* nvvm_div_rm_f */ DoesNotAccessMemory,
/* nvvm_div_rm_ftz_f */ DoesNotAccessMemory,
/* nvvm_div_rn_d */ DoesNotAccessMemory,
/* nvvm_div_rn_f */ DoesNotAccessMemory,
/* nvvm_div_rn_ftz_f */ DoesNotAccessMemory,
/* nvvm_div_rp_d */ DoesNotAccessMemory,
/* nvvm_div_rp_f */ DoesNotAccessMemory,
/* nvvm_div_rp_ftz_f */ DoesNotAccessMemory,
/* nvvm_div_rz_d */ DoesNotAccessMemory,
/* nvvm_div_rz_f */ DoesNotAccessMemory,
/* nvvm_div_rz_ftz_f */ DoesNotAccessMemory,
/* nvvm_ex2_approx_d */ DoesNotAccessMemory,
/* nvvm_ex2_approx_f */ DoesNotAccessMemory,
/* nvvm_ex2_approx_ftz_f */ DoesNotAccessMemory,
/* nvvm_f2h_rn */ DoesNotAccessMemory,
/* nvvm_f2h_rn_ftz */ DoesNotAccessMemory,
/* nvvm_f2i_rm */ DoesNotAccessMemory,
/* nvvm_f2i_rm_ftz */ DoesNotAccessMemory,
/* nvvm_f2i_rn */ DoesNotAccessMemory,
/* nvvm_f2i_rn_ftz */ DoesNotAccessMemory,
/* nvvm_f2i_rp */ DoesNotAccessMemory,
/* nvvm_f2i_rp_ftz */ DoesNotAccessMemory,
/* nvvm_f2i_rz */ DoesNotAccessMemory,
/* nvvm_f2i_rz_ftz */ DoesNotAccessMemory,
/* nvvm_f2ll_rm */ DoesNotAccessMemory,
/* nvvm_f2ll_rm_ftz */ DoesNotAccessMemory,
/* nvvm_f2ll_rn */ DoesNotAccessMemory,
/* nvvm_f2ll_rn_ftz */ DoesNotAccessMemory,
/* nvvm_f2ll_rp */ DoesNotAccessMemory,
/* nvvm_f2ll_rp_ftz */ DoesNotAccessMemory,
/* nvvm_f2ll_rz */ DoesNotAccessMemory,
/* nvvm_f2ll_rz_ftz */ DoesNotAccessMemory,
/* nvvm_f2ui_rm */ DoesNotAccessMemory,
/* nvvm_f2ui_rm_ftz */ DoesNotAccessMemory,
/* nvvm_f2ui_rn */ DoesNotAccessMemory,
/* nvvm_f2ui_rn_ftz */ DoesNotAccessMemory,
/* nvvm_f2ui_rp */ DoesNotAccessMemory,
/* nvvm_f2ui_rp_ftz */ DoesNotAccessMemory,
/* nvvm_f2ui_rz */ DoesNotAccessMemory,
/* nvvm_f2ui_rz_ftz */ DoesNotAccessMemory,
/* nvvm_f2ull_rm */ DoesNotAccessMemory,
/* nvvm_f2ull_rm_ftz */ DoesNotAccessMemory,
/* nvvm_f2ull_rn */ DoesNotAccessMemory,
/* nvvm_f2ull_rn_ftz */ DoesNotAccessMemory,
/* nvvm_f2ull_rp */ DoesNotAccessMemory,
/* nvvm_f2ull_rp_ftz */ DoesNotAccessMemory,
/* nvvm_f2ull_rz */ DoesNotAccessMemory,
/* nvvm_f2ull_rz_ftz */ DoesNotAccessMemory,
/* nvvm_fabs_d */ DoesNotAccessMemory,
/* nvvm_fabs_f */ DoesNotAccessMemory,
/* nvvm_fabs_ftz_f */ DoesNotAccessMemory,
/* nvvm_floor_d */ DoesNotAccessMemory,
/* nvvm_floor_f */ DoesNotAccessMemory,
/* nvvm_floor_ftz_f */ DoesNotAccessMemory,
/* nvvm_fma_rm_d */ DoesNotAccessMemory,
/* nvvm_fma_rm_f */ DoesNotAccessMemory,
/* nvvm_fma_rm_ftz_f */ DoesNotAccessMemory,
/* nvvm_fma_rn_d */ DoesNotAccessMemory,
/* nvvm_fma_rn_f */ DoesNotAccessMemory,
/* nvvm_fma_rn_ftz_f */ DoesNotAccessMemory,
/* nvvm_fma_rp_d */ DoesNotAccessMemory,
/* nvvm_fma_rp_f */ DoesNotAccessMemory,
/* nvvm_fma_rp_ftz_f */ DoesNotAccessMemory,
/* nvvm_fma_rz_d */ DoesNotAccessMemory,
/* nvvm_fma_rz_f */ DoesNotAccessMemory,
/* nvvm_fma_rz_ftz_f */ DoesNotAccessMemory,
/* nvvm_fmax_d */ DoesNotAccessMemory,
/* nvvm_fmax_f */ DoesNotAccessMemory,
/* nvvm_fmax_ftz_f */ DoesNotAccessMemory,
/* nvvm_fmin_d */ DoesNotAccessMemory,
/* nvvm_fmin_f */ DoesNotAccessMemory,
/* nvvm_fmin_ftz_f */ DoesNotAccessMemory,
/* nvvm_h2f */ DoesNotAccessMemory,
/* nvvm_i2d_rm */ DoesNotAccessMemory,
/* nvvm_i2d_rn */ DoesNotAccessMemory,
/* nvvm_i2d_rp */ DoesNotAccessMemory,
/* nvvm_i2d_rz */ DoesNotAccessMemory,
/* nvvm_i2f_rm */ DoesNotAccessMemory,
/* nvvm_i2f_rn */ DoesNotAccessMemory,
/* nvvm_i2f_rp */ DoesNotAccessMemory,
/* nvvm_i2f_rz */ DoesNotAccessMemory,
/* nvvm_ldu_global_f */ OnlyReadsMemory,
/* nvvm_ldu_global_i */ OnlyReadsMemory,
/* nvvm_ldu_global_p */ OnlyReadsMemory,
/* nvvm_lg2_approx_d */ DoesNotAccessMemory,
/* nvvm_lg2_approx_f */ DoesNotAccessMemory,
/* nvvm_lg2_approx_ftz_f */ DoesNotAccessMemory,
/* nvvm_ll2d_rm */ DoesNotAccessMemory,
/* nvvm_ll2d_rn */ DoesNotAccessMemory,
/* nvvm_ll2d_rp */ DoesNotAccessMemory,
/* nvvm_ll2d_rz */ DoesNotAccessMemory,
/* nvvm_ll2f_rm */ DoesNotAccessMemory,
/* nvvm_ll2f_rn */ DoesNotAccessMemory,
/* nvvm_ll2f_rp */ DoesNotAccessMemory,
/* nvvm_ll2f_rz */ DoesNotAccessMemory,
/* nvvm_lohi_i2d */ DoesNotAccessMemory,
/* nvvm_max_i */ DoesNotAccessMemory,
/* nvvm_max_ll */ DoesNotAccessMemory,
/* nvvm_max_ui */ DoesNotAccessMemory,
/* nvvm_max_ull */ DoesNotAccessMemory,
/* nvvm_membar_cta */ UnknownModRefBehavior,
/* nvvm_membar_gl */ UnknownModRefBehavior,
/* nvvm_membar_sys */ UnknownModRefBehavior,
/* nvvm_min_i */ DoesNotAccessMemory,
/* nvvm_min_ll */ DoesNotAccessMemory,
/* nvvm_min_ui */ DoesNotAccessMemory,
/* nvvm_min_ull */ DoesNotAccessMemory,
/* nvvm_move_double */ DoesNotAccessMemory,
/* nvvm_move_float */ DoesNotAccessMemory,
/* nvvm_move_i16 */ DoesNotAccessMemory,
/* nvvm_move_i32 */ DoesNotAccessMemory,
/* nvvm_move_i64 */ DoesNotAccessMemory,
/* nvvm_move_i8 */ DoesNotAccessMemory,
/* nvvm_move_ptr */ DoesNotAccessMemory,
/* nvvm_mul24_i */ DoesNotAccessMemory,
/* nvvm_mul24_ui */ DoesNotAccessMemory,
/* nvvm_mul_rm_d */ DoesNotAccessMemory,
/* nvvm_mul_rm_f */ DoesNotAccessMemory,
/* nvvm_mul_rm_ftz_f */ DoesNotAccessMemory,
/* nvvm_mul_rn_d */ DoesNotAccessMemory,
/* nvvm_mul_rn_f */ DoesNotAccessMemory,
/* nvvm_mul_rn_ftz_f */ DoesNotAccessMemory,
/* nvvm_mul_rp_d */ DoesNotAccessMemory,
/* nvvm_mul_rp_f */ DoesNotAccessMemory,
/* nvvm_mul_rp_ftz_f */ DoesNotAccessMemory,
/* nvvm_mul_rz_d */ DoesNotAccessMemory,
/* nvvm_mul_rz_f */ DoesNotAccessMemory,
/* nvvm_mul_rz_ftz_f */ DoesNotAccessMemory,
/* nvvm_mulhi_i */ DoesNotAccessMemory,
/* nvvm_mulhi_ll */ DoesNotAccessMemory,
/* nvvm_mulhi_ui */ DoesNotAccessMemory,
/* nvvm_mulhi_ull */ DoesNotAccessMemory,
/* nvvm_popc_i */ DoesNotAccessMemory,
/* nvvm_popc_ll */ DoesNotAccessMemory,
/* nvvm_prmt */ DoesNotAccessMemory,
/* nvvm_ptr_constant_to_gen */ DoesNotAccessMemory,
/* nvvm_ptr_gen_to_constant */ DoesNotAccessMemory,
/* nvvm_ptr_gen_to_global */ DoesNotAccessMemory,
/* nvvm_ptr_gen_to_local */ DoesNotAccessMemory,
/* nvvm_ptr_gen_to_param */ DoesNotAccessMemory,
/* nvvm_ptr_gen_to_shared */ DoesNotAccessMemory,
/* nvvm_ptr_global_to_gen */ DoesNotAccessMemory,
/* nvvm_ptr_local_to_gen */ DoesNotAccessMemory,
/* nvvm_ptr_shared_to_gen */ DoesNotAccessMemory,
/* nvvm_rcp_approx_ftz_d */ DoesNotAccessMemory,
/* nvvm_rcp_rm_d */ DoesNotAccessMemory,
/* nvvm_rcp_rm_f */ DoesNotAccessMemory,
/* nvvm_rcp_rm_ftz_f */ DoesNotAccessMemory,
/* nvvm_rcp_rn_d */ DoesNotAccessMemory,
/* nvvm_rcp_rn_f */ DoesNotAccessMemory,
/* nvvm_rcp_rn_ftz_f */ DoesNotAccessMemory,
/* nvvm_rcp_rp_d */ DoesNotAccessMemory,
/* nvvm_rcp_rp_f */ DoesNotAccessMemory,
/* nvvm_rcp_rp_ftz_f */ DoesNotAccessMemory,
/* nvvm_rcp_rz_d */ DoesNotAccessMemory,
/* nvvm_rcp_rz_f */ DoesNotAccessMemory,
/* nvvm_rcp_rz_ftz_f */ DoesNotAccessMemory,
/* nvvm_read_ptx_sreg_ctaid_x */ DoesNotAccessMemory,
/* nvvm_read_ptx_sreg_ctaid_y */ DoesNotAccessMemory,
/* nvvm_read_ptx_sreg_ctaid_z */ DoesNotAccessMemory,
/* nvvm_read_ptx_sreg_nctaid_x */ DoesNotAccessMemory,
/* nvvm_read_ptx_sreg_nctaid_y */ DoesNotAccessMemory,
/* nvvm_read_ptx_sreg_nctaid_z */ DoesNotAccessMemory,
/* nvvm_read_ptx_sreg_ntid_x */ DoesNotAccessMemory,
/* nvvm_read_ptx_sreg_ntid_y */ DoesNotAccessMemory,
/* nvvm_read_ptx_sreg_ntid_z */ DoesNotAccessMemory,
/* nvvm_read_ptx_sreg_tid_x */ DoesNotAccessMemory,
/* nvvm_read_ptx_sreg_tid_y */ DoesNotAccessMemory,
/* nvvm_read_ptx_sreg_tid_z */ DoesNotAccessMemory,
/* nvvm_read_ptx_sreg_warpsize */ DoesNotAccessMemory,
/* nvvm_round_d */ DoesNotAccessMemory,
/* nvvm_round_f */ DoesNotAccessMemory,
/* nvvm_round_ftz_f */ DoesNotAccessMemory,
/* nvvm_rsqrt_approx_d */ DoesNotAccessMemory,
/* nvvm_rsqrt_approx_f */ DoesNotAccessMemory,
/* nvvm_rsqrt_approx_ftz_f */ DoesNotAccessMemory,
/* nvvm_sad_i */ DoesNotAccessMemory,
/* nvvm_sad_ui */ DoesNotAccessMemory,
/* nvvm_saturate_d */ DoesNotAccessMemory,
/* nvvm_saturate_f */ DoesNotAccessMemory,
/* nvvm_saturate_ftz_f */ DoesNotAccessMemory,
/* nvvm_sin_approx_f */ DoesNotAccessMemory,
/* nvvm_sin_approx_ftz_f */ DoesNotAccessMemory,
/* nvvm_sqrt_approx_f */ DoesNotAccessMemory,
/* nvvm_sqrt_approx_ftz_f */ DoesNotAccessMemory,
/* nvvm_sqrt_rm_d */ DoesNotAccessMemory,
/* nvvm_sqrt_rm_f */ DoesNotAccessMemory,
/* nvvm_sqrt_rm_ftz_f */ DoesNotAccessMemory,
/* nvvm_sqrt_rn_d */ DoesNotAccessMemory,
/* nvvm_sqrt_rn_f */ DoesNotAccessMemory,
/* nvvm_sqrt_rn_ftz_f */ DoesNotAccessMemory,
/* nvvm_sqrt_rp_d */ DoesNotAccessMemory,
/* nvvm_sqrt_rp_f */ DoesNotAccessMemory,
/* nvvm_sqrt_rp_ftz_f */ DoesNotAccessMemory,
/* nvvm_sqrt_rz_d */ DoesNotAccessMemory,
/* nvvm_sqrt_rz_f */ DoesNotAccessMemory,
/* nvvm_sqrt_rz_ftz_f */ DoesNotAccessMemory,
/* nvvm_trunc_d */ DoesNotAccessMemory,
/* nvvm_trunc_f */ DoesNotAccessMemory,
/* nvvm_trunc_ftz_f */ DoesNotAccessMemory,
/* nvvm_ui2d_rm */ DoesNotAccessMemory,
/* nvvm_ui2d_rn */ DoesNotAccessMemory,
/* nvvm_ui2d_rp */ DoesNotAccessMemory,
/* nvvm_ui2d_rz */ DoesNotAccessMemory,
/* nvvm_ui2f_rm */ DoesNotAccessMemory,
/* nvvm_ui2f_rn */ DoesNotAccessMemory,
/* nvvm_ui2f_rp */ DoesNotAccessMemory,
/* nvvm_ui2f_rz */ DoesNotAccessMemory,
/* nvvm_ull2d_rm */ DoesNotAccessMemory,
/* nvvm_ull2d_rn */ DoesNotAccessMemory,
/* nvvm_ull2d_rp */ DoesNotAccessMemory,
/* nvvm_ull2d_rz */ DoesNotAccessMemory,
/* nvvm_ull2f_rm */ DoesNotAccessMemory,
/* nvvm_ull2f_rn */ DoesNotAccessMemory,
/* nvvm_ull2f_rp */ DoesNotAccessMemory,
/* nvvm_ull2f_rz */ DoesNotAccessMemory,
/* objectsize */ DoesNotAccessMemory, /* objectsize */ DoesNotAccessMemory,
/* pcmarker */ UnknownModRefBehavior, /* pcmarker */ UnknownModRefBehavior,
/* pow */ OnlyReadsMemory, /* pow */ OnlyReadsMemory,
/* powi */ OnlyReadsMemory, /* powi */ OnlyReadsMemory,
/* ppc_altivec_dss */ UnknownModRefBehavior, /* ppc_altivec_dss */ UnknownModRefBehavior,
/* ppc_altivec_dssall */ UnknownModRefBehavior, /* ppc_altivec_dssall */ UnknownModRefBehavior,
/* ppc_altivec_dst */ UnknownModRefBehavior, /* ppc_altivec_dst */ UnknownModRefBehavior,
/* ppc_altivec_dstst */ UnknownModRefBehavior, /* ppc_altivec_dstst */ UnknownModRefBehavior,
/* ppc_altivec_dststt */ UnknownModRefBehavior, /* ppc_altivec_dststt */ UnknownModRefBehavior,
/* ppc_altivec_dstt */ UnknownModRefBehavior, /* ppc_altivec_dstt */ UnknownModRefBehavior,
skipping to change at line 26244 skipping to change at line 27277
/* x86_3dnowa_pfnacc */ DoesNotAccessMemory, /* x86_3dnowa_pfnacc */ DoesNotAccessMemory,
/* x86_3dnowa_pfpnacc */ DoesNotAccessMemory, /* x86_3dnowa_pfpnacc */ DoesNotAccessMemory,
/* x86_3dnowa_pi2fw */ DoesNotAccessMemory, /* x86_3dnowa_pi2fw */ DoesNotAccessMemory,
/* x86_3dnowa_pswapd */ DoesNotAccessMemory, /* x86_3dnowa_pswapd */ DoesNotAccessMemory,
/* x86_aesni_aesdec */ DoesNotAccessMemory, /* x86_aesni_aesdec */ DoesNotAccessMemory,
/* x86_aesni_aesdeclast */ DoesNotAccessMemory, /* x86_aesni_aesdeclast */ DoesNotAccessMemory,
/* x86_aesni_aesenc */ DoesNotAccessMemory, /* x86_aesni_aesenc */ DoesNotAccessMemory,
/* x86_aesni_aesenclast */ DoesNotAccessMemory, /* x86_aesni_aesenclast */ DoesNotAccessMemory,
/* x86_aesni_aesimc */ DoesNotAccessMemory, /* x86_aesni_aesimc */ DoesNotAccessMemory,
/* x86_aesni_aeskeygenassist */ DoesNotAccessMemory, /* x86_aesni_aeskeygenassist */ DoesNotAccessMemory,
/* x86_avx2_maskload_d */ OnlyReadsMemory, /* x86_avx2_gather_d_d */ OnlyReadsMemory,
/* x86_avx2_maskload_d_256 */ OnlyReadsMemory, /* x86_avx2_gather_d_d_256 */ OnlyReadsMemory,
/* x86_avx2_maskload_q */ OnlyReadsMemory, /* x86_avx2_gather_d_pd */ OnlyReadsMemory,
/* x86_avx2_maskload_q_256 */ OnlyReadsMemory, /* x86_avx2_gather_d_pd_256 */ OnlyReadsMemory,
/* x86_avx2_maskstore_d */ UnknownModRefBehavior, /* x86_avx2_gather_d_ps */ OnlyReadsMemory,
/* x86_avx2_maskstore_d_256 */ UnknownModRefBehavior, /* x86_avx2_gather_d_ps_256 */ OnlyReadsMemory,
/* x86_avx2_maskstore_q */ UnknownModRefBehavior, /* x86_avx2_gather_d_q */ OnlyReadsMemory,
/* x86_avx2_maskstore_q_256 */ UnknownModRefBehavior, /* x86_avx2_gather_d_q_256 */ OnlyReadsMemory,
/* x86_avx2_gather_q_d */ OnlyReadsMemory,
/* x86_avx2_gather_q_d_256 */ OnlyReadsMemory,
/* x86_avx2_gather_q_pd */ OnlyReadsMemory,
/* x86_avx2_gather_q_pd_256 */ OnlyReadsMemory,
/* x86_avx2_gather_q_ps */ OnlyReadsMemory,
/* x86_avx2_gather_q_ps_256 */ OnlyReadsMemory,
/* x86_avx2_gather_q_q */ OnlyReadsMemory,
/* x86_avx2_gather_q_q_256 */ OnlyReadsMemory,
/* x86_avx2_maskload_d */ OnlyReadsArgumentPointees,
/* x86_avx2_maskload_d_256 */ OnlyReadsArgumentPointees,
/* x86_avx2_maskload_q */ OnlyReadsArgumentPointees,
/* x86_avx2_maskload_q_256 */ OnlyReadsArgumentPointees,
/* x86_avx2_maskstore_d */ OnlyAccessesArgumentPointees,
/* x86_avx2_maskstore_d_256 */ OnlyAccessesArgumentPointees,
/* x86_avx2_maskstore_q */ OnlyAccessesArgumentPointees,
/* x86_avx2_maskstore_q_256 */ OnlyAccessesArgumentPointees,
/* x86_avx2_movntdqa */ OnlyReadsMemory, /* x86_avx2_movntdqa */ OnlyReadsMemory,
/* x86_avx2_mpsadbw */ DoesNotAccessMemory, /* x86_avx2_mpsadbw */ DoesNotAccessMemory,
/* x86_avx2_pabs_b */ DoesNotAccessMemory, /* x86_avx2_pabs_b */ DoesNotAccessMemory,
/* x86_avx2_pabs_d */ DoesNotAccessMemory, /* x86_avx2_pabs_d */ DoesNotAccessMemory,
/* x86_avx2_pabs_w */ DoesNotAccessMemory, /* x86_avx2_pabs_w */ DoesNotAccessMemory,
/* x86_avx2_packssdw */ DoesNotAccessMemory, /* x86_avx2_packssdw */ DoesNotAccessMemory,
/* x86_avx2_packsswb */ DoesNotAccessMemory, /* x86_avx2_packsswb */ DoesNotAccessMemory,
/* x86_avx2_packusdw */ DoesNotAccessMemory, /* x86_avx2_packusdw */ DoesNotAccessMemory,
/* x86_avx2_packuswb */ DoesNotAccessMemory, /* x86_avx2_packuswb */ DoesNotAccessMemory,
/* x86_avx2_padds_b */ DoesNotAccessMemory, /* x86_avx2_padds_b */ DoesNotAccessMemory,
skipping to change at line 26361 skipping to change at line 27410
/* x86_avx2_psrlv_d_256 */ DoesNotAccessMemory, /* x86_avx2_psrlv_d_256 */ DoesNotAccessMemory,
/* x86_avx2_psrlv_q */ DoesNotAccessMemory, /* x86_avx2_psrlv_q */ DoesNotAccessMemory,
/* x86_avx2_psrlv_q_256 */ DoesNotAccessMemory, /* x86_avx2_psrlv_q_256 */ DoesNotAccessMemory,
/* x86_avx2_psubs_b */ DoesNotAccessMemory, /* x86_avx2_psubs_b */ DoesNotAccessMemory,
/* x86_avx2_psubs_w */ DoesNotAccessMemory, /* x86_avx2_psubs_w */ DoesNotAccessMemory,
/* x86_avx2_psubus_b */ DoesNotAccessMemory, /* x86_avx2_psubus_b */ DoesNotAccessMemory,
/* x86_avx2_psubus_w */ DoesNotAccessMemory, /* x86_avx2_psubus_w */ DoesNotAccessMemory,
/* x86_avx2_vbroadcast_sd_pd_256 */ DoesNotAccessMemory, /* x86_avx2_vbroadcast_sd_pd_256 */ DoesNotAccessMemory,
/* x86_avx2_vbroadcast_ss_ps */ DoesNotAccessMemory, /* x86_avx2_vbroadcast_ss_ps */ DoesNotAccessMemory,
/* x86_avx2_vbroadcast_ss_ps_256 */ DoesNotAccessMemory, /* x86_avx2_vbroadcast_ss_ps_256 */ DoesNotAccessMemory,
/* x86_avx2_vbroadcasti128 */ OnlyReadsMemory, /* x86_avx2_vbroadcasti128 */ OnlyReadsArgumentPointees,
/* x86_avx2_vextracti128 */ DoesNotAccessMemory, /* x86_avx2_vextracti128 */ DoesNotAccessMemory,
/* x86_avx2_vinserti128 */ DoesNotAccessMemory, /* x86_avx2_vinserti128 */ DoesNotAccessMemory,
/* x86_avx2_vperm2i128 */ DoesNotAccessMemory, /* x86_avx2_vperm2i128 */ DoesNotAccessMemory,
/* x86_avx_addsub_pd_256 */ DoesNotAccessMemory, /* x86_avx_addsub_pd_256 */ DoesNotAccessMemory,
/* x86_avx_addsub_ps_256 */ DoesNotAccessMemory, /* x86_avx_addsub_ps_256 */ DoesNotAccessMemory,
/* x86_avx_blend_pd_256 */ DoesNotAccessMemory, /* x86_avx_blend_pd_256 */ DoesNotAccessMemory,
/* x86_avx_blend_ps_256 */ DoesNotAccessMemory, /* x86_avx_blend_ps_256 */ DoesNotAccessMemory,
/* x86_avx_blendv_pd_256 */ DoesNotAccessMemory, /* x86_avx_blendv_pd_256 */ DoesNotAccessMemory,
/* x86_avx_blendv_ps_256 */ DoesNotAccessMemory, /* x86_avx_blendv_ps_256 */ DoesNotAccessMemory,
/* x86_avx_cmp_pd_256 */ DoesNotAccessMemory, /* x86_avx_cmp_pd_256 */ DoesNotAccessMemory,
skipping to change at line 26387 skipping to change at line 27436
/* x86_avx_cvtdq2_pd_256 */ DoesNotAccessMemory, /* x86_avx_cvtdq2_pd_256 */ DoesNotAccessMemory,
/* x86_avx_cvtdq2_ps_256 */ DoesNotAccessMemory, /* x86_avx_cvtdq2_ps_256 */ DoesNotAccessMemory,
/* x86_avx_cvtt_pd2dq_256 */ DoesNotAccessMemory, /* x86_avx_cvtt_pd2dq_256 */ DoesNotAccessMemory,
/* x86_avx_cvtt_ps2dq_256 */ DoesNotAccessMemory, /* x86_avx_cvtt_ps2dq_256 */ DoesNotAccessMemory,
/* x86_avx_dp_ps_256 */ DoesNotAccessMemory, /* x86_avx_dp_ps_256 */ DoesNotAccessMemory,
/* x86_avx_hadd_pd_256 */ DoesNotAccessMemory, /* x86_avx_hadd_pd_256 */ DoesNotAccessMemory,
/* x86_avx_hadd_ps_256 */ DoesNotAccessMemory, /* x86_avx_hadd_ps_256 */ DoesNotAccessMemory,
/* x86_avx_hsub_pd_256 */ DoesNotAccessMemory, /* x86_avx_hsub_pd_256 */ DoesNotAccessMemory,
/* x86_avx_hsub_ps_256 */ DoesNotAccessMemory, /* x86_avx_hsub_ps_256 */ DoesNotAccessMemory,
/* x86_avx_ldu_dq_256 */ OnlyReadsMemory, /* x86_avx_ldu_dq_256 */ OnlyReadsMemory,
/* x86_avx_maskload_pd */ OnlyReadsMemory, /* x86_avx_maskload_pd */ OnlyReadsArgumentPointees,
/* x86_avx_maskload_pd_256 */ OnlyReadsMemory, /* x86_avx_maskload_pd_256 */ OnlyReadsArgumentPointees,
/* x86_avx_maskload_ps */ OnlyReadsMemory, /* x86_avx_maskload_ps */ OnlyReadsArgumentPointees,
/* x86_avx_maskload_ps_256 */ OnlyReadsMemory, /* x86_avx_maskload_ps_256 */ OnlyReadsArgumentPointees,
/* x86_avx_maskstore_pd */ UnknownModRefBehavior, /* x86_avx_maskstore_pd */ OnlyAccessesArgumentPointees,
/* x86_avx_maskstore_pd_256 */ UnknownModRefBehavior, /* x86_avx_maskstore_pd_256 */ OnlyAccessesArgumentPointees,
/* x86_avx_maskstore_ps */ UnknownModRefBehavior, /* x86_avx_maskstore_ps */ OnlyAccessesArgumentPointees,
/* x86_avx_maskstore_ps_256 */ UnknownModRefBehavior, /* x86_avx_maskstore_ps_256 */ OnlyAccessesArgumentPointees,
/* x86_avx_max_pd_256 */ DoesNotAccessMemory, /* x86_avx_max_pd_256 */ DoesNotAccessMemory,
/* x86_avx_max_ps_256 */ DoesNotAccessMemory, /* x86_avx_max_ps_256 */ DoesNotAccessMemory,
/* x86_avx_min_pd_256 */ DoesNotAccessMemory, /* x86_avx_min_pd_256 */ DoesNotAccessMemory,
/* x86_avx_min_ps_256 */ DoesNotAccessMemory, /* x86_avx_min_ps_256 */ DoesNotAccessMemory,
/* x86_avx_movmsk_pd_256 */ DoesNotAccessMemory, /* x86_avx_movmsk_pd_256 */ DoesNotAccessMemory,
/* x86_avx_movmsk_ps_256 */ DoesNotAccessMemory, /* x86_avx_movmsk_ps_256 */ DoesNotAccessMemory,
/* x86_avx_movnt_dq_256 */ UnknownModRefBehavior,
/* x86_avx_movnt_pd_256 */ UnknownModRefBehavior,
/* x86_avx_movnt_ps_256 */ UnknownModRefBehavior,
/* x86_avx_ptestc_256 */ DoesNotAccessMemory, /* x86_avx_ptestc_256 */ DoesNotAccessMemory,
/* x86_avx_ptestnzc_256 */ DoesNotAccessMemory, /* x86_avx_ptestnzc_256 */ DoesNotAccessMemory,
/* x86_avx_ptestz_256 */ DoesNotAccessMemory, /* x86_avx_ptestz_256 */ DoesNotAccessMemory,
/* x86_avx_rcp_ps_256 */ DoesNotAccessMemory, /* x86_avx_rcp_ps_256 */ DoesNotAccessMemory,
/* x86_avx_round_pd_256 */ DoesNotAccessMemory, /* x86_avx_round_pd_256 */ DoesNotAccessMemory,
/* x86_avx_round_ps_256 */ DoesNotAccessMemory, /* x86_avx_round_ps_256 */ DoesNotAccessMemory,
/* x86_avx_rsqrt_ps_256 */ DoesNotAccessMemory, /* x86_avx_rsqrt_ps_256 */ DoesNotAccessMemory,
/* x86_avx_sqrt_pd_256 */ DoesNotAccessMemory, /* x86_avx_sqrt_pd_256 */ DoesNotAccessMemory,
/* x86_avx_sqrt_ps_256 */ DoesNotAccessMemory, /* x86_avx_sqrt_ps_256 */ DoesNotAccessMemory,
/* x86_avx_storeu_dq_256 */ UnknownModRefBehavior, /* x86_avx_storeu_dq_256 */ OnlyAccessesArgumentPointees,
/* x86_avx_storeu_pd_256 */ UnknownModRefBehavior, /* x86_avx_storeu_pd_256 */ OnlyAccessesArgumentPointees,
/* x86_avx_storeu_ps_256 */ UnknownModRefBehavior, /* x86_avx_storeu_ps_256 */ OnlyAccessesArgumentPointees,
/* x86_avx_vbroadcast_sd_256 */ OnlyReadsMemory, /* x86_avx_vbroadcast_sd_256 */ OnlyReadsArgumentPointees,
/* x86_avx_vbroadcast_ss */ OnlyReadsMemory, /* x86_avx_vbroadcast_ss */ OnlyReadsArgumentPointees,
/* x86_avx_vbroadcast_ss_256 */ OnlyReadsMemory, /* x86_avx_vbroadcast_ss_256 */ OnlyReadsArgumentPointees,
/* x86_avx_vbroadcastf128_pd_256 */ OnlyReadsMemory, /* x86_avx_vbroadcastf128_pd_256 */ OnlyReadsArgumentPointees,
/* x86_avx_vbroadcastf128_ps_256 */ OnlyReadsMemory, /* x86_avx_vbroadcastf128_ps_256 */ OnlyReadsArgumentPointees,
/* x86_avx_vextractf128_pd_256 */ DoesNotAccessMemory, /* x86_avx_vextractf128_pd_256 */ DoesNotAccessMemory,
/* x86_avx_vextractf128_ps_256 */ DoesNotAccessMemory, /* x86_avx_vextractf128_ps_256 */ DoesNotAccessMemory,
/* x86_avx_vextractf128_si_256 */ DoesNotAccessMemory, /* x86_avx_vextractf128_si_256 */ DoesNotAccessMemory,
/* x86_avx_vinsertf128_pd_256 */ DoesNotAccessMemory, /* x86_avx_vinsertf128_pd_256 */ DoesNotAccessMemory,
/* x86_avx_vinsertf128_ps_256 */ DoesNotAccessMemory, /* x86_avx_vinsertf128_ps_256 */ DoesNotAccessMemory,
/* x86_avx_vinsertf128_si_256 */ DoesNotAccessMemory, /* x86_avx_vinsertf128_si_256 */ DoesNotAccessMemory,
/* x86_avx_vperm2f128_pd_256 */ DoesNotAccessMemory, /* x86_avx_vperm2f128_pd_256 */ DoesNotAccessMemory,
/* x86_avx_vperm2f128_ps_256 */ DoesNotAccessMemory, /* x86_avx_vperm2f128_ps_256 */ DoesNotAccessMemory,
/* x86_avx_vperm2f128_si_256 */ DoesNotAccessMemory, /* x86_avx_vperm2f128_si_256 */ DoesNotAccessMemory,
/* x86_avx_vpermilvar_pd */ DoesNotAccessMemory, /* x86_avx_vpermilvar_pd */ DoesNotAccessMemory,
skipping to change at line 26456 skipping to change at line 27502
/* x86_avx_vzeroall */ UnknownModRefBehavior, /* x86_avx_vzeroall */ UnknownModRefBehavior,
/* x86_avx_vzeroupper */ UnknownModRefBehavior, /* x86_avx_vzeroupper */ UnknownModRefBehavior,
/* x86_bmi_bextr_32 */ DoesNotAccessMemory, /* x86_bmi_bextr_32 */ DoesNotAccessMemory,
/* x86_bmi_bextr_64 */ DoesNotAccessMemory, /* x86_bmi_bextr_64 */ DoesNotAccessMemory,
/* x86_bmi_bzhi_32 */ DoesNotAccessMemory, /* x86_bmi_bzhi_32 */ DoesNotAccessMemory,
/* x86_bmi_bzhi_64 */ DoesNotAccessMemory, /* x86_bmi_bzhi_64 */ DoesNotAccessMemory,
/* x86_bmi_pdep_32 */ DoesNotAccessMemory, /* x86_bmi_pdep_32 */ DoesNotAccessMemory,
/* x86_bmi_pdep_64 */ DoesNotAccessMemory, /* x86_bmi_pdep_64 */ DoesNotAccessMemory,
/* x86_bmi_pext_32 */ DoesNotAccessMemory, /* x86_bmi_pext_32 */ DoesNotAccessMemory,
/* x86_bmi_pext_64 */ DoesNotAccessMemory, /* x86_bmi_pext_64 */ DoesNotAccessMemory,
/* x86_fma4_vfmadd_pd */ DoesNotAccessMemory, /* x86_fma_vfmadd_pd */ DoesNotAccessMemory,
/* x86_fma4_vfmadd_pd_256 */ DoesNotAccessMemory, /* x86_fma_vfmadd_pd_256 */ DoesNotAccessMemory,
/* x86_fma4_vfmadd_ps */ DoesNotAccessMemory, /* x86_fma_vfmadd_ps */ DoesNotAccessMemory,
/* x86_fma4_vfmadd_ps_256 */ DoesNotAccessMemory, /* x86_fma_vfmadd_ps_256 */ DoesNotAccessMemory,
/* x86_fma4_vfmadd_sd */ DoesNotAccessMemory, /* x86_fma_vfmadd_sd */ DoesNotAccessMemory,
/* x86_fma4_vfmadd_ss */ DoesNotAccessMemory, /* x86_fma_vfmadd_ss */ DoesNotAccessMemory,
/* x86_fma4_vfmaddsub_pd */ DoesNotAccessMemory, /* x86_fma_vfmaddsub_pd */ DoesNotAccessMemory,
/* x86_fma4_vfmaddsub_pd_256 */ DoesNotAccessMemory, /* x86_fma_vfmaddsub_pd_256 */ DoesNotAccessMemory,
/* x86_fma4_vfmaddsub_ps */ DoesNotAccessMemory, /* x86_fma_vfmaddsub_ps */ DoesNotAccessMemory,
/* x86_fma4_vfmaddsub_ps_256 */ DoesNotAccessMemory, /* x86_fma_vfmaddsub_ps_256 */ DoesNotAccessMemory,
/* x86_fma4_vfmsub_pd */ DoesNotAccessMemory, /* x86_fma_vfmsub_pd */ DoesNotAccessMemory,
/* x86_fma4_vfmsub_pd_256 */ DoesNotAccessMemory, /* x86_fma_vfmsub_pd_256 */ DoesNotAccessMemory,
/* x86_fma4_vfmsub_ps */ DoesNotAccessMemory, /* x86_fma_vfmsub_ps */ DoesNotAccessMemory,
/* x86_fma4_vfmsub_ps_256 */ DoesNotAccessMemory, /* x86_fma_vfmsub_ps_256 */ DoesNotAccessMemory,
/* x86_fma4_vfmsub_sd */ DoesNotAccessMemory, /* x86_fma_vfmsub_sd */ DoesNotAccessMemory,
/* x86_fma4_vfmsub_ss */ DoesNotAccessMemory, /* x86_fma_vfmsub_ss */ DoesNotAccessMemory,
/* x86_fma4_vfmsubadd_pd */ DoesNotAccessMemory, /* x86_fma_vfmsubadd_pd */ DoesNotAccessMemory,
/* x86_fma4_vfmsubadd_pd_256 */ DoesNotAccessMemory, /* x86_fma_vfmsubadd_pd_256 */ DoesNotAccessMemory,
/* x86_fma4_vfmsubadd_ps */ DoesNotAccessMemory, /* x86_fma_vfmsubadd_ps */ DoesNotAccessMemory,
/* x86_fma4_vfmsubadd_ps_256 */ DoesNotAccessMemory, /* x86_fma_vfmsubadd_ps_256 */ DoesNotAccessMemory,
/* x86_fma4_vfnmadd_pd */ DoesNotAccessMemory, /* x86_fma_vfnmadd_pd */ DoesNotAccessMemory,
/* x86_fma4_vfnmadd_pd_256 */ DoesNotAccessMemory, /* x86_fma_vfnmadd_pd_256 */ DoesNotAccessMemory,
/* x86_fma4_vfnmadd_ps */ DoesNotAccessMemory, /* x86_fma_vfnmadd_ps */ DoesNotAccessMemory,
/* x86_fma4_vfnmadd_ps_256 */ DoesNotAccessMemory, /* x86_fma_vfnmadd_ps_256 */ DoesNotAccessMemory,
/* x86_fma4_vfnmadd_sd */ DoesNotAccessMemory, /* x86_fma_vfnmadd_sd */ DoesNotAccessMemory,
/* x86_fma4_vfnmadd_ss */ DoesNotAccessMemory, /* x86_fma_vfnmadd_ss */ DoesNotAccessMemory,
/* x86_fma4_vfnmsub_pd */ DoesNotAccessMemory, /* x86_fma_vfnmsub_pd */ DoesNotAccessMemory,
/* x86_fma4_vfnmsub_pd_256 */ DoesNotAccessMemory, /* x86_fma_vfnmsub_pd_256 */ DoesNotAccessMemory,
/* x86_fma4_vfnmsub_ps */ DoesNotAccessMemory, /* x86_fma_vfnmsub_ps */ DoesNotAccessMemory,
/* x86_fma4_vfnmsub_ps_256 */ DoesNotAccessMemory, /* x86_fma_vfnmsub_ps_256 */ DoesNotAccessMemory,
/* x86_fma4_vfnmsub_sd */ DoesNotAccessMemory, /* x86_fma_vfnmsub_sd */ DoesNotAccessMemory,
/* x86_fma4_vfnmsub_ss */ DoesNotAccessMemory, /* x86_fma_vfnmsub_ss */ DoesNotAccessMemory,
/* x86_int */ UnknownModRefBehavior, /* x86_int */ UnknownModRefBehavior,
/* x86_mmx_emms */ UnknownModRefBehavior, /* x86_mmx_emms */ UnknownModRefBehavior,
/* x86_mmx_femms */ UnknownModRefBehavior, /* x86_mmx_femms */ UnknownModRefBehavior,
/* x86_mmx_maskmovq */ UnknownModRefBehavior, /* x86_mmx_maskmovq */ UnknownModRefBehavior,
/* x86_mmx_movnt_dq */ UnknownModRefBehavior, /* x86_mmx_movnt_dq */ UnknownModRefBehavior,
/* x86_mmx_packssdw */ DoesNotAccessMemory, /* x86_mmx_packssdw */ DoesNotAccessMemory,
/* x86_mmx_packsswb */ DoesNotAccessMemory, /* x86_mmx_packsswb */ DoesNotAccessMemory,
/* x86_mmx_packuswb */ DoesNotAccessMemory, /* x86_mmx_packuswb */ DoesNotAccessMemory,
/* x86_mmx_padd_b */ DoesNotAccessMemory, /* x86_mmx_padd_b */ DoesNotAccessMemory,
/* x86_mmx_padd_d */ DoesNotAccessMemory, /* x86_mmx_padd_d */ DoesNotAccessMemory,
skipping to change at line 26560 skipping to change at line 27606
/* x86_mmx_psubs_w */ DoesNotAccessMemory, /* x86_mmx_psubs_w */ DoesNotAccessMemory,
/* x86_mmx_psubus_b */ DoesNotAccessMemory, /* x86_mmx_psubus_b */ DoesNotAccessMemory,
/* x86_mmx_psubus_w */ DoesNotAccessMemory, /* x86_mmx_psubus_w */ DoesNotAccessMemory,
/* x86_mmx_punpckhbw */ DoesNotAccessMemory, /* x86_mmx_punpckhbw */ DoesNotAccessMemory,
/* x86_mmx_punpckhdq */ DoesNotAccessMemory, /* x86_mmx_punpckhdq */ DoesNotAccessMemory,
/* x86_mmx_punpckhwd */ DoesNotAccessMemory, /* x86_mmx_punpckhwd */ DoesNotAccessMemory,
/* x86_mmx_punpcklbw */ DoesNotAccessMemory, /* x86_mmx_punpcklbw */ DoesNotAccessMemory,
/* x86_mmx_punpckldq */ DoesNotAccessMemory, /* x86_mmx_punpckldq */ DoesNotAccessMemory,
/* x86_mmx_punpcklwd */ DoesNotAccessMemory, /* x86_mmx_punpcklwd */ DoesNotAccessMemory,
/* x86_mmx_pxor */ DoesNotAccessMemory, /* x86_mmx_pxor */ DoesNotAccessMemory,
/* x86_pclmulqdq */ DoesNotAccessMemory,
/* x86_rdfsbase_32 */ UnknownModRefBehavior, /* x86_rdfsbase_32 */ UnknownModRefBehavior,
/* x86_rdfsbase_64 */ UnknownModRefBehavior, /* x86_rdfsbase_64 */ UnknownModRefBehavior,
/* x86_rdgsbase_32 */ UnknownModRefBehavior, /* x86_rdgsbase_32 */ UnknownModRefBehavior,
/* x86_rdgsbase_64 */ UnknownModRefBehavior, /* x86_rdgsbase_64 */ UnknownModRefBehavior,
/* x86_rdrand_16 */ UnknownModRefBehavior,
/* x86_rdrand_32 */ UnknownModRefBehavior,
/* x86_rdrand_64 */ UnknownModRefBehavior,
/* x86_sse2_add_sd */ DoesNotAccessMemory, /* x86_sse2_add_sd */ DoesNotAccessMemory,
/* x86_sse2_clflush */ UnknownModRefBehavior, /* x86_sse2_clflush */ UnknownModRefBehavior,
/* x86_sse2_cmp_pd */ DoesNotAccessMemory, /* x86_sse2_cmp_pd */ DoesNotAccessMemory,
/* x86_sse2_cmp_sd */ DoesNotAccessMemory, /* x86_sse2_cmp_sd */ DoesNotAccessMemory,
/* x86_sse2_comieq_sd */ DoesNotAccessMemory, /* x86_sse2_comieq_sd */ DoesNotAccessMemory,
/* x86_sse2_comige_sd */ DoesNotAccessMemory, /* x86_sse2_comige_sd */ DoesNotAccessMemory,
/* x86_sse2_comigt_sd */ DoesNotAccessMemory, /* x86_sse2_comigt_sd */ DoesNotAccessMemory,
/* x86_sse2_comile_sd */ DoesNotAccessMemory, /* x86_sse2_comile_sd */ DoesNotAccessMemory,
/* x86_sse2_comilt_sd */ DoesNotAccessMemory, /* x86_sse2_comilt_sd */ DoesNotAccessMemory,
/* x86_sse2_comineq_sd */ DoesNotAccessMemory, /* x86_sse2_comineq_sd */ DoesNotAccessMemory,
skipping to change at line 26645 skipping to change at line 27695
/* x86_sse2_psrl_w */ DoesNotAccessMemory, /* x86_sse2_psrl_w */ DoesNotAccessMemory,
/* x86_sse2_psrli_d */ DoesNotAccessMemory, /* x86_sse2_psrli_d */ DoesNotAccessMemory,
/* x86_sse2_psrli_q */ DoesNotAccessMemory, /* x86_sse2_psrli_q */ DoesNotAccessMemory,
/* x86_sse2_psrli_w */ DoesNotAccessMemory, /* x86_sse2_psrli_w */ DoesNotAccessMemory,
/* x86_sse2_psubs_b */ DoesNotAccessMemory, /* x86_sse2_psubs_b */ DoesNotAccessMemory,
/* x86_sse2_psubs_w */ DoesNotAccessMemory, /* x86_sse2_psubs_w */ DoesNotAccessMemory,
/* x86_sse2_psubus_b */ DoesNotAccessMemory, /* x86_sse2_psubus_b */ DoesNotAccessMemory,
/* x86_sse2_psubus_w */ DoesNotAccessMemory, /* x86_sse2_psubus_w */ DoesNotAccessMemory,
/* x86_sse2_sqrt_pd */ DoesNotAccessMemory, /* x86_sse2_sqrt_pd */ DoesNotAccessMemory,
/* x86_sse2_sqrt_sd */ DoesNotAccessMemory, /* x86_sse2_sqrt_sd */ DoesNotAccessMemory,
/* x86_sse2_storel_dq */ UnknownModRefBehavior, /* x86_sse2_storel_dq */ OnlyAccessesArgumentPointees,
/* x86_sse2_storeu_dq */ UnknownModRefBehavior, /* x86_sse2_storeu_dq */ OnlyAccessesArgumentPointees,
/* x86_sse2_storeu_pd */ UnknownModRefBehavior, /* x86_sse2_storeu_pd */ OnlyAccessesArgumentPointees,
/* x86_sse2_sub_sd */ DoesNotAccessMemory, /* x86_sse2_sub_sd */ DoesNotAccessMemory,
/* x86_sse2_ucomieq_sd */ DoesNotAccessMemory, /* x86_sse2_ucomieq_sd */ DoesNotAccessMemory,
/* x86_sse2_ucomige_sd */ DoesNotAccessMemory, /* x86_sse2_ucomige_sd */ DoesNotAccessMemory,
/* x86_sse2_ucomigt_sd */ DoesNotAccessMemory, /* x86_sse2_ucomigt_sd */ DoesNotAccessMemory,
/* x86_sse2_ucomile_sd */ DoesNotAccessMemory, /* x86_sse2_ucomile_sd */ DoesNotAccessMemory,
/* x86_sse2_ucomilt_sd */ DoesNotAccessMemory, /* x86_sse2_ucomilt_sd */ DoesNotAccessMemory,
/* x86_sse2_ucomineq_sd */ DoesNotAccessMemory, /* x86_sse2_ucomineq_sd */ DoesNotAccessMemory,
/* x86_sse3_addsub_pd */ DoesNotAccessMemory, /* x86_sse3_addsub_pd */ DoesNotAccessMemory,
/* x86_sse3_addsub_ps */ DoesNotAccessMemory, /* x86_sse3_addsub_ps */ DoesNotAccessMemory,
/* x86_sse3_hadd_pd */ DoesNotAccessMemory, /* x86_sse3_hadd_pd */ DoesNotAccessMemory,
skipping to change at line 26728 skipping to change at line 27778
/* x86_sse42_pcmpestris128 */ DoesNotAccessMemory, /* x86_sse42_pcmpestris128 */ DoesNotAccessMemory,
/* x86_sse42_pcmpestriz128 */ DoesNotAccessMemory, /* x86_sse42_pcmpestriz128 */ DoesNotAccessMemory,
/* x86_sse42_pcmpestrm128 */ DoesNotAccessMemory, /* x86_sse42_pcmpestrm128 */ DoesNotAccessMemory,
/* x86_sse42_pcmpistri128 */ DoesNotAccessMemory, /* x86_sse42_pcmpistri128 */ DoesNotAccessMemory,
/* x86_sse42_pcmpistria128 */ DoesNotAccessMemory, /* x86_sse42_pcmpistria128 */ DoesNotAccessMemory,
/* x86_sse42_pcmpistric128 */ DoesNotAccessMemory, /* x86_sse42_pcmpistric128 */ DoesNotAccessMemory,
/* x86_sse42_pcmpistrio128 */ DoesNotAccessMemory, /* x86_sse42_pcmpistrio128 */ DoesNotAccessMemory,
/* x86_sse42_pcmpistris128 */ DoesNotAccessMemory, /* x86_sse42_pcmpistris128 */ DoesNotAccessMemory,
/* x86_sse42_pcmpistriz128 */ DoesNotAccessMemory, /* x86_sse42_pcmpistriz128 */ DoesNotAccessMemory,
/* x86_sse42_pcmpistrm128 */ DoesNotAccessMemory, /* x86_sse42_pcmpistrm128 */ DoesNotAccessMemory,
/* x86_sse4a_extrq */ DoesNotAccessMemory,
/* x86_sse4a_extrqi */ DoesNotAccessMemory,
/* x86_sse4a_insertq */ DoesNotAccessMemory,
/* x86_sse4a_insertqi */ DoesNotAccessMemory,
/* x86_sse4a_movnt_sd */ UnknownModRefBehavior,
/* x86_sse4a_movnt_ss */ UnknownModRefBehavior,
/* x86_sse_add_ss */ DoesNotAccessMemory, /* x86_sse_add_ss */ DoesNotAccessMemory,
/* x86_sse_cmp_ps */ DoesNotAccessMemory, /* x86_sse_cmp_ps */ DoesNotAccessMemory,
/* x86_sse_cmp_ss */ DoesNotAccessMemory, /* x86_sse_cmp_ss */ DoesNotAccessMemory,
/* x86_sse_comieq_ss */ DoesNotAccessMemory, /* x86_sse_comieq_ss */ DoesNotAccessMemory,
/* x86_sse_comige_ss */ DoesNotAccessMemory, /* x86_sse_comige_ss */ DoesNotAccessMemory,
/* x86_sse_comigt_ss */ DoesNotAccessMemory, /* x86_sse_comigt_ss */ DoesNotAccessMemory,
/* x86_sse_comile_ss */ DoesNotAccessMemory, /* x86_sse_comile_ss */ DoesNotAccessMemory,
/* x86_sse_comilt_ss */ DoesNotAccessMemory, /* x86_sse_comilt_ss */ DoesNotAccessMemory,
/* x86_sse_comineq_ss */ DoesNotAccessMemory, /* x86_sse_comineq_ss */ DoesNotAccessMemory,
/* x86_sse_cvtpd2pi */ DoesNotAccessMemory, /* x86_sse_cvtpd2pi */ DoesNotAccessMemory,
skipping to change at line 26766 skipping to change at line 27822
/* x86_sse_mul_ss */ DoesNotAccessMemory, /* x86_sse_mul_ss */ DoesNotAccessMemory,
/* x86_sse_pshuf_w */ DoesNotAccessMemory, /* x86_sse_pshuf_w */ DoesNotAccessMemory,
/* x86_sse_rcp_ps */ DoesNotAccessMemory, /* x86_sse_rcp_ps */ DoesNotAccessMemory,
/* x86_sse_rcp_ss */ DoesNotAccessMemory, /* x86_sse_rcp_ss */ DoesNotAccessMemory,
/* x86_sse_rsqrt_ps */ DoesNotAccessMemory, /* x86_sse_rsqrt_ps */ DoesNotAccessMemory,
/* x86_sse_rsqrt_ss */ DoesNotAccessMemory, /* x86_sse_rsqrt_ss */ DoesNotAccessMemory,
/* x86_sse_sfence */ UnknownModRefBehavior, /* x86_sse_sfence */ UnknownModRefBehavior,
/* x86_sse_sqrt_ps */ DoesNotAccessMemory, /* x86_sse_sqrt_ps */ DoesNotAccessMemory,
/* x86_sse_sqrt_ss */ DoesNotAccessMemory, /* x86_sse_sqrt_ss */ DoesNotAccessMemory,
/* x86_sse_stmxcsr */ UnknownModRefBehavior, /* x86_sse_stmxcsr */ UnknownModRefBehavior,
/* x86_sse_storeu_ps */ UnknownModRefBehavior, /* x86_sse_storeu_ps */ OnlyAccessesArgumentPointees,
/* x86_sse_sub_ss */ DoesNotAccessMemory, /* x86_sse_sub_ss */ DoesNotAccessMemory,
/* x86_sse_ucomieq_ss */ DoesNotAccessMemory, /* x86_sse_ucomieq_ss */ DoesNotAccessMemory,
/* x86_sse_ucomige_ss */ DoesNotAccessMemory, /* x86_sse_ucomige_ss */ DoesNotAccessMemory,
/* x86_sse_ucomigt_ss */ DoesNotAccessMemory, /* x86_sse_ucomigt_ss */ DoesNotAccessMemory,
/* x86_sse_ucomile_ss */ DoesNotAccessMemory, /* x86_sse_ucomile_ss */ DoesNotAccessMemory,
/* x86_sse_ucomilt_ss */ DoesNotAccessMemory, /* x86_sse_ucomilt_ss */ DoesNotAccessMemory,
/* x86_sse_ucomineq_ss */ DoesNotAccessMemory, /* x86_sse_ucomineq_ss */ DoesNotAccessMemory,
/* x86_ssse3_pabs_b */ DoesNotAccessMemory, /* x86_ssse3_pabs_b */ DoesNotAccessMemory,
/* x86_ssse3_pabs_b_128 */ DoesNotAccessMemory, /* x86_ssse3_pabs_b_128 */ DoesNotAccessMemory,
/* x86_ssse3_pabs_d */ DoesNotAccessMemory, /* x86_ssse3_pabs_d */ DoesNotAccessMemory,
skipping to change at line 26812 skipping to change at line 27868
/* x86_ssse3_psign_w */ DoesNotAccessMemory, /* x86_ssse3_psign_w */ DoesNotAccessMemory,
/* x86_ssse3_psign_w_128 */ DoesNotAccessMemory, /* x86_ssse3_psign_w_128 */ DoesNotAccessMemory,
/* x86_vcvtph2ps_128 */ DoesNotAccessMemory, /* x86_vcvtph2ps_128 */ DoesNotAccessMemory,
/* x86_vcvtph2ps_256 */ DoesNotAccessMemory, /* x86_vcvtph2ps_256 */ DoesNotAccessMemory,
/* x86_vcvtps2ph_128 */ DoesNotAccessMemory, /* x86_vcvtps2ph_128 */ DoesNotAccessMemory,
/* x86_vcvtps2ph_256 */ DoesNotAccessMemory, /* x86_vcvtps2ph_256 */ DoesNotAccessMemory,
/* x86_wrfsbase_32 */ UnknownModRefBehavior, /* x86_wrfsbase_32 */ UnknownModRefBehavior,
/* x86_wrfsbase_64 */ UnknownModRefBehavior, /* x86_wrfsbase_64 */ UnknownModRefBehavior,
/* x86_wrgsbase_32 */ UnknownModRefBehavior, /* x86_wrgsbase_32 */ UnknownModRefBehavior,
/* x86_wrgsbase_64 */ UnknownModRefBehavior, /* x86_wrgsbase_64 */ UnknownModRefBehavior,
/* x86_xabort */ UnknownModRefBehavior,
/* x86_xbegin */ UnknownModRefBehavior,
/* x86_xend */ UnknownModRefBehavior,
/* x86_xop_vfrcz_pd */ DoesNotAccessMemory, /* x86_xop_vfrcz_pd */ DoesNotAccessMemory,
/* x86_xop_vfrcz_pd_256 */ DoesNotAccessMemory, /* x86_xop_vfrcz_pd_256 */ DoesNotAccessMemory,
/* x86_xop_vfrcz_ps */ DoesNotAccessMemory, /* x86_xop_vfrcz_ps */ DoesNotAccessMemory,
/* x86_xop_vfrcz_ps_256 */ DoesNotAccessMemory, /* x86_xop_vfrcz_ps_256 */ DoesNotAccessMemory,
/* x86_xop_vfrcz_sd */ DoesNotAccessMemory, /* x86_xop_vfrcz_sd */ DoesNotAccessMemory,
/* x86_xop_vfrcz_ss */ DoesNotAccessMemory, /* x86_xop_vfrcz_ss */ DoesNotAccessMemory,
/* x86_xop_vpcmov */ DoesNotAccessMemory, /* x86_xop_vpcmov */ DoesNotAccessMemory,
/* x86_xop_vpcmov_256 */ DoesNotAccessMemory, /* x86_xop_vpcmov_256 */ DoesNotAccessMemory,
/* x86_xop_vpcomeqb */ DoesNotAccessMemory, /* x86_xop_vpcomb */ DoesNotAccessMemory,
/* x86_xop_vpcomeqd */ DoesNotAccessMemory, /* x86_xop_vpcomd */ DoesNotAccessMemory,
/* x86_xop_vpcomeqq */ DoesNotAccessMemory, /* x86_xop_vpcomq */ DoesNotAccessMemory,
/* x86_xop_vpcomequb */ DoesNotAccessMemory, /* x86_xop_vpcomub */ DoesNotAccessMemory,
/* x86_xop_vpcomequd */ DoesNotAccessMemory, /* x86_xop_vpcomud */ DoesNotAccessMemory,
/* x86_xop_vpcomequq */ DoesNotAccessMemory, /* x86_xop_vpcomuq */ DoesNotAccessMemory,
/* x86_xop_vpcomequw */ DoesNotAccessMemory, /* x86_xop_vpcomuw */ DoesNotAccessMemory,
/* x86_xop_vpcomeqw */ DoesNotAccessMemory, /* x86_xop_vpcomw */ DoesNotAccessMemory,
/* x86_xop_vpcomfalseb */ DoesNotAccessMemory,
/* x86_xop_vpcomfalsed */ DoesNotAccessMemory,
/* x86_xop_vpcomfalseq */ DoesNotAccessMemory,
/* x86_xop_vpcomfalseub */ DoesNotAccessMemory,
/* x86_xop_vpcomfalseud */ DoesNotAccessMemory,
/* x86_xop_vpcomfalseuq */ DoesNotAccessMemory,
/* x86_xop_vpcomfalseuw */ DoesNotAccessMemory,
/* x86_xop_vpcomfalsew */ DoesNotAccessMemory,
/* x86_xop_vpcomgeb */ DoesNotAccessMemory,
/* x86_xop_vpcomged */ DoesNotAccessMemory,
/* x86_xop_vpcomgeq */ DoesNotAccessMemory,
/* x86_xop_vpcomgeub */ DoesNotAccessMemory,
/* x86_xop_vpcomgeud */ DoesNotAccessMemory,
/* x86_xop_vpcomgeuq */ DoesNotAccessMemory,
/* x86_xop_vpcomgeuw */ DoesNotAccessMemory,
/* x86_xop_vpcomgew */ DoesNotAccessMemory,
/* x86_xop_vpcomgtb */ DoesNotAccessMemory,
/* x86_xop_vpcomgtd */ DoesNotAccessMemory,
/* x86_xop_vpcomgtq */ DoesNotAccessMemory,
/* x86_xop_vpcomgtub */ DoesNotAccessMemory,
/* x86_xop_vpcomgtud */ DoesNotAccessMemory,
/* x86_xop_vpcomgtuq */ DoesNotAccessMemory,
/* x86_xop_vpcomgtuw */ DoesNotAccessMemory,
/* x86_xop_vpcomgtw */ DoesNotAccessMemory,
/* x86_xop_vpcomleb */ DoesNotAccessMemory,
/* x86_xop_vpcomled */ DoesNotAccessMemory,
/* x86_xop_vpcomleq */ DoesNotAccessMemory,
/* x86_xop_vpcomleub */ DoesNotAccessMemory,
/* x86_xop_vpcomleud */ DoesNotAccessMemory,
/* x86_xop_vpcomleuq */ DoesNotAccessMemory,
/* x86_xop_vpcomleuw */ DoesNotAccessMemory,
/* x86_xop_vpcomlew */ DoesNotAccessMemory,
/* x86_xop_vpcomltb */ DoesNotAccessMemory,
/* x86_xop_vpcomltd */ DoesNotAccessMemory,
/* x86_xop_vpcomltq */ DoesNotAccessMemory,
/* x86_xop_vpcomltub */ DoesNotAccessMemory,
/* x86_xop_vpcomltud */ DoesNotAccessMemory,
/* x86_xop_vpcomltuq */ DoesNotAccessMemory,
/* x86_xop_vpcomltuw */ DoesNotAccessMemory,
/* x86_xop_vpcomltw */ DoesNotAccessMemory,
/* x86_xop_vpcomneb */ DoesNotAccessMemory,
/* x86_xop_vpcomned */ DoesNotAccessMemory,
/* x86_xop_vpcomneq */ DoesNotAccessMemory,
/* x86_xop_vpcomneub */ DoesNotAccessMemory,
/* x86_xop_vpcomneud */ DoesNotAccessMemory,
/* x86_xop_vpcomneuq */ DoesNotAccessMemory,
/* x86_xop_vpcomneuw */ DoesNotAccessMemory,
/* x86_xop_vpcomnew */ DoesNotAccessMemory,
/* x86_xop_vpcomtrueb */ DoesNotAccessMemory,
/* x86_xop_vpcomtrued */ DoesNotAccessMemory,
/* x86_xop_vpcomtrueq */ DoesNotAccessMemory,
/* x86_xop_vpcomtrueub */ DoesNotAccessMemory,
/* x86_xop_vpcomtrueud */ DoesNotAccessMemory,
/* x86_xop_vpcomtrueuq */ DoesNotAccessMemory,
/* x86_xop_vpcomtrueuw */ DoesNotAccessMemory,
/* x86_xop_vpcomtruew */ DoesNotAccessMemory,
/* x86_xop_vpermil2pd */ DoesNotAccessMemory, /* x86_xop_vpermil2pd */ DoesNotAccessMemory,
/* x86_xop_vpermil2pd_256 */ DoesNotAccessMemory, /* x86_xop_vpermil2pd_256 */ DoesNotAccessMemory,
/* x86_xop_vpermil2ps */ DoesNotAccessMemory, /* x86_xop_vpermil2ps */ DoesNotAccessMemory,
/* x86_xop_vpermil2ps_256 */ DoesNotAccessMemory, /* x86_xop_vpermil2ps_256 */ DoesNotAccessMemory,
/* x86_xop_vphaddbd */ DoesNotAccessMemory, /* x86_xop_vphaddbd */ DoesNotAccessMemory,
/* x86_xop_vphaddbq */ DoesNotAccessMemory, /* x86_xop_vphaddbq */ DoesNotAccessMemory,
/* x86_xop_vphaddbw */ DoesNotAccessMemory, /* x86_xop_vphaddbw */ DoesNotAccessMemory,
/* x86_xop_vphadddq */ DoesNotAccessMemory, /* x86_xop_vphadddq */ DoesNotAccessMemory,
/* x86_xop_vphaddubd */ DoesNotAccessMemory, /* x86_xop_vphaddubd */ DoesNotAccessMemory,
/* x86_xop_vphaddubq */ DoesNotAccessMemory, /* x86_xop_vphaddubq */ DoesNotAccessMemory,
skipping to change at line 26917 skipping to change at line 27920
/* x86_xop_vpmacssdqh */ DoesNotAccessMemory, /* x86_xop_vpmacssdqh */ DoesNotAccessMemory,
/* x86_xop_vpmacssdql */ DoesNotAccessMemory, /* x86_xop_vpmacssdql */ DoesNotAccessMemory,
/* x86_xop_vpmacsswd */ DoesNotAccessMemory, /* x86_xop_vpmacsswd */ DoesNotAccessMemory,
/* x86_xop_vpmacssww */ DoesNotAccessMemory, /* x86_xop_vpmacssww */ DoesNotAccessMemory,
/* x86_xop_vpmacswd */ DoesNotAccessMemory, /* x86_xop_vpmacswd */ DoesNotAccessMemory,
/* x86_xop_vpmacsww */ DoesNotAccessMemory, /* x86_xop_vpmacsww */ DoesNotAccessMemory,
/* x86_xop_vpmadcsswd */ DoesNotAccessMemory, /* x86_xop_vpmadcsswd */ DoesNotAccessMemory,
/* x86_xop_vpmadcswd */ DoesNotAccessMemory, /* x86_xop_vpmadcswd */ DoesNotAccessMemory,
/* x86_xop_vpperm */ DoesNotAccessMemory, /* x86_xop_vpperm */ DoesNotAccessMemory,
/* x86_xop_vprotb */ DoesNotAccessMemory, /* x86_xop_vprotb */ DoesNotAccessMemory,
/* x86_xop_vprotbi */ DoesNotAccessMemory,
/* x86_xop_vprotd */ DoesNotAccessMemory, /* x86_xop_vprotd */ DoesNotAccessMemory,
/* x86_xop_vprotdi */ DoesNotAccessMemory,
/* x86_xop_vprotq */ DoesNotAccessMemory, /* x86_xop_vprotq */ DoesNotAccessMemory,
/* x86_xop_vprotqi */ DoesNotAccessMemory,
/* x86_xop_vprotw */ DoesNotAccessMemory, /* x86_xop_vprotw */ DoesNotAccessMemory,
/* x86_xop_vprotwi */ DoesNotAccessMemory,
/* x86_xop_vpshab */ DoesNotAccessMemory, /* x86_xop_vpshab */ DoesNotAccessMemory,
/* x86_xop_vpshad */ DoesNotAccessMemory, /* x86_xop_vpshad */ DoesNotAccessMemory,
/* x86_xop_vpshaq */ DoesNotAccessMemory, /* x86_xop_vpshaq */ DoesNotAccessMemory,
/* x86_xop_vpshaw */ DoesNotAccessMemory, /* x86_xop_vpshaw */ DoesNotAccessMemory,
/* x86_xop_vpshlb */ DoesNotAccessMemory, /* x86_xop_vpshlb */ DoesNotAccessMemory,
/* x86_xop_vpshld */ DoesNotAccessMemory, /* x86_xop_vpshld */ DoesNotAccessMemory,
/* x86_xop_vpshlq */ DoesNotAccessMemory, /* x86_xop_vpshlq */ DoesNotAccessMemory,
/* x86_xop_vpshlw */ DoesNotAccessMemory, /* x86_xop_vpshlw */ DoesNotAccessMemory,
/* xcore_bitrev */ DoesNotAccessMemory, /* xcore_bitrev */ DoesNotAccessMemory,
/* xcore_checkevent */ UnknownModRefBehavior, /* xcore_checkevent */ UnknownModRefBehavior,
skipping to change at line 26996 skipping to change at line 28003
// in as BuiltinName, and a target prefix (e.g. 'ppc') is passed // in as BuiltinName, and a target prefix (e.g. 'ppc') is passed
// in as TargetPrefix. The result is assigned to 'IntrinsicID'. // in as TargetPrefix. The result is assigned to 'IntrinsicID'.
#ifdef GET_LLVM_INTRINSIC_FOR_GCC_BUILTIN #ifdef GET_LLVM_INTRINSIC_FOR_GCC_BUILTIN
Intrinsic::ID Intrinsic::getIntrinsicForGCCBuiltin(const char *TargetPrefix Str, const char *BuiltinNameStr) { Intrinsic::ID Intrinsic::getIntrinsicForGCCBuiltin(const char *TargetPrefix Str, const char *BuiltinNameStr) {
StringRef BuiltinName(BuiltinNameStr); StringRef BuiltinName(BuiltinNameStr);
StringRef TargetPrefix(TargetPrefixStr); StringRef TargetPrefix(TargetPrefixStr);
/* Target Independent Builtins */ { /* Target Independent Builtins */ {
switch (BuiltinName.size()) { switch (BuiltinName.size()) {
default: break; default: break;
case 14: // 3 strings to match. case 10: // 1 string to match.
if (BuiltinName.substr(0, 2) != "__") if (memcmp(BuiltinName.data()+0, "__nvvm_h2f", 10))
break;
return Intrinsic::nvvm_h2f; // "__nvvm_h2f"
case 11: // 2 strings to match.
if (memcmp(BuiltinName.data()+0, "__nvvm_", 7))
break;
switch (BuiltinName[7]) {
default: break;
case 'b': // 1 string to match.
if (memcmp(BuiltinName.data()+8, "ar0", 3))
break;
return Intrinsic::nvvm_barrier0; // "__nvvm_bar0"
case 'p': // 1 string to match.
if (memcmp(BuiltinName.data()+8, "rmt", 3))
break;
return Intrinsic::nvvm_prmt; // "__nvvm_prmt"
}
break;
case 12: // 5 strings to match.
if (memcmp(BuiltinName.data()+0, "__nvvm_", 7))
break;
switch (BuiltinName[7]) {
default: break;
case 'a': // 1 string to match.
if (memcmp(BuiltinName.data()+8, "bs_i", 4))
break;
return Intrinsic::nvvm_abs_i; // "__nvvm_abs_i"
case 'c': // 1 string to match.
if (memcmp(BuiltinName.data()+8, "lz_i", 4))
break;
return Intrinsic::nvvm_clz_i; // "__nvvm_clz_i"
case 'm': // 2 strings to match.
switch (BuiltinName[8]) {
default: break;
case 'a': // 1 string to match.
if (memcmp(BuiltinName.data()+9, "x_i", 3))
break;
return Intrinsic::nvvm_max_i; // "__nvvm_max_i"
case 'i': // 1 string to match.
if (memcmp(BuiltinName.data()+9, "n_i", 3))
break;
return Intrinsic::nvvm_min_i; // "__nvvm_min_i"
}
break;
case 's': // 1 string to match.
if (memcmp(BuiltinName.data()+8, "ad_i", 4))
break;
return Intrinsic::nvvm_sad_i; // "__nvvm_sad_i"
}
break;
case 13: // 42 strings to match.
if (memcmp(BuiltinName.data()+0, "__", 2))
break;
switch (BuiltinName[2]) {
default: break;
case 'n': // 41 strings to match.
if (memcmp(BuiltinName.data()+3, "vvm_", 4))
break;
switch (BuiltinName[7]) {
default: break;
case 'a': // 1 string to match.
if (memcmp(BuiltinName.data()+8, "bs_ll", 5))
break;
return Intrinsic::nvvm_abs_ll; // "__nvvm_abs_ll"
case 'b': // 2 strings to match.
if (memcmp(BuiltinName.data()+8, "rev", 3))
break;
switch (BuiltinName[11]) {
default: break;
case '3': // 1 string to match.
if (BuiltinName[12] != '2')
break;
return Intrinsic::nvvm_brev32; // "__nvvm_brev32"
case '6': // 1 string to match.
if (BuiltinName[12] != '4')
break;
return Intrinsic::nvvm_brev64; // "__nvvm_brev64"
}
break;
case 'c': // 3 strings to match.
switch (BuiltinName[8]) {
default: break;
case 'e': // 2 strings to match.
if (memcmp(BuiltinName.data()+9, "il_", 3))
break;
switch (BuiltinName[12]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::nvvm_ceil_d; // "__nvvm_ceil_d"
case 'f': // 1 string to match.
return Intrinsic::nvvm_ceil_f; // "__nvvm_ceil_f"
}
break;
case 'l': // 1 string to match.
if (memcmp(BuiltinName.data()+9, "z_ll", 4))
break;
return Intrinsic::nvvm_clz_ll; // "__nvvm_clz_ll"
}
break;
case 'd': // 10 strings to match.
if (BuiltinName[8] != '2')
break;
switch (BuiltinName[9]) {
default: break;
case 'f': // 4 strings to match.
if (memcmp(BuiltinName.data()+10, "_r", 2))
break;
switch (BuiltinName[12]) {
default: break;
case 'm': // 1 string to match.
return Intrinsic::nvvm_d2f_rm; // "__nvvm_d2f_rm"
case 'n': // 1 string to match.
return Intrinsic::nvvm_d2f_rn; // "__nvvm_d2f_rn"
case 'p': // 1 string to match.
return Intrinsic::nvvm_d2f_rp; // "__nvvm_d2f_rp"
case 'z': // 1 string to match.
return Intrinsic::nvvm_d2f_rz; // "__nvvm_d2f_rz"
}
break;
case 'i': // 6 strings to match.
if (BuiltinName[10] != '_')
break;
switch (BuiltinName[11]) {
default: break;
case 'h': // 1 string to match.
if (BuiltinName[12] != 'i')
break;
return Intrinsic::nvvm_d2i_hi; // "__nvvm_d2i_hi"
case 'l': // 1 string to match.
if (BuiltinName[12] != 'o')
break;
return Intrinsic::nvvm_d2i_lo; // "__nvvm_d2i_lo"
case 'r': // 4 strings to match.
switch (BuiltinName[12]) {
default: break;
case 'm': // 1 string to match.
return Intrinsic::nvvm_d2i_rm; // "__nvvm_d2i_rm"
case 'n': // 1 string to match.
return Intrinsic::nvvm_d2i_rn; // "__nvvm_d2i_rn"
case 'p': // 1 string to match.
return Intrinsic::nvvm_d2i_rp; // "__nvvm_d2i_rp"
case 'z': // 1 string to match.
return Intrinsic::nvvm_d2i_rz; // "__nvvm_d2i_rz"
}
break;
}
break;
}
break;
case 'f': // 11 strings to match.
switch (BuiltinName[8]) {
default: break;
case '2': // 5 strings to match.
switch (BuiltinName[9]) {
default: break;
case 'h': // 1 string to match.
if (memcmp(BuiltinName.data()+10, "_rn", 3))
break;
return Intrinsic::nvvm_f2h_rn; // "__nvvm_f2h_rn"
case 'i': // 4 strings to match.
if (memcmp(BuiltinName.data()+10, "_r", 2))
break;
switch (BuiltinName[12]) {
default: break;
case 'm': // 1 string to match.
return Intrinsic::nvvm_f2i_rm; // "__nvvm_f2i_rm"
case 'n': // 1 string to match.
return Intrinsic::nvvm_f2i_rn; // "__nvvm_f2i_rn"
case 'p': // 1 string to match.
return Intrinsic::nvvm_f2i_rp; // "__nvvm_f2i_rp"
case 'z': // 1 string to match.
return Intrinsic::nvvm_f2i_rz; // "__nvvm_f2i_rz"
}
break;
}
break;
case 'a': // 2 strings to match.
if (memcmp(BuiltinName.data()+9, "bs_", 3))
break;
switch (BuiltinName[12]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::nvvm_fabs_d; // "__nvvm_fabs_d"
case 'f': // 1 string to match.
return Intrinsic::nvvm_fabs_f; // "__nvvm_fabs_f"
}
break;
case 'm': // 4 strings to match.
switch (BuiltinName[9]) {
default: break;
case 'a': // 2 strings to match.
if (memcmp(BuiltinName.data()+10, "x_", 2))
break;
switch (BuiltinName[12]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::nvvm_fmax_d; // "__nvvm_fmax_d"
case 'f': // 1 string to match.
return Intrinsic::nvvm_fmax_f; // "__nvvm_fmax_f"
}
break;
case 'i': // 2 strings to match.
if (memcmp(BuiltinName.data()+10, "n_", 2))
break;
switch (BuiltinName[12]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::nvvm_fmin_d; // "__nvvm_fmin_d"
case 'f': // 1 string to match.
return Intrinsic::nvvm_fmin_f; // "__nvvm_fmin_f"
}
break;
}
break;
}
break;
case 'i': // 8 strings to match.
if (BuiltinName[8] != '2')
break;
switch (BuiltinName[9]) {
default: break;
case 'd': // 4 strings to match.
if (memcmp(BuiltinName.data()+10, "_r", 2))
break;
switch (BuiltinName[12]) {
default: break;
case 'm': // 1 string to match.
return Intrinsic::nvvm_i2d_rm; // "__nvvm_i2d_rm"
case 'n': // 1 string to match.
return Intrinsic::nvvm_i2d_rn; // "__nvvm_i2d_rn"
case 'p': // 1 string to match.
return Intrinsic::nvvm_i2d_rp; // "__nvvm_i2d_rp"
case 'z': // 1 string to match.
return Intrinsic::nvvm_i2d_rz; // "__nvvm_i2d_rz"
}
break;
case 'f': // 4 strings to match.
if (memcmp(BuiltinName.data()+10, "_r", 2))
break;
switch (BuiltinName[12]) {
default: break;
case 'm': // 1 string to match.
return Intrinsic::nvvm_i2f_rm; // "__nvvm_i2f_rm"
case 'n': // 1 string to match.
return Intrinsic::nvvm_i2f_rn; // "__nvvm_i2f_rn"
case 'p': // 1 string to match.
return Intrinsic::nvvm_i2f_rp; // "__nvvm_i2f_rp"
case 'z': // 1 string to match.
return Intrinsic::nvvm_i2f_rz; // "__nvvm_i2f_rz"
}
break;
}
break;
case 'm': // 4 strings to match.
switch (BuiltinName[8]) {
default: break;
case 'a': // 2 strings to match.
if (memcmp(BuiltinName.data()+9, "x_", 2))
break;
switch (BuiltinName[11]) {
default: break;
case 'l': // 1 string to match.
if (BuiltinName[12] != 'l')
break;
return Intrinsic::nvvm_max_ll; // "__nvvm_max_ll"
case 'u': // 1 string to match.
if (BuiltinName[12] != 'i')
break;
return Intrinsic::nvvm_max_ui; // "__nvvm_max_ui"
}
break;
case 'i': // 2 strings to match.
if (memcmp(BuiltinName.data()+9, "n_", 2))
break;
switch (BuiltinName[11]) {
default: break;
case 'l': // 1 string to match.
if (BuiltinName[12] != 'l')
break;
return Intrinsic::nvvm_min_ll; // "__nvvm_min_ll"
case 'u': // 1 string to match.
if (BuiltinName[12] != 'i')
break;
return Intrinsic::nvvm_min_ui; // "__nvvm_min_ui"
}
break;
}
break;
case 'p': // 1 string to match.
if (memcmp(BuiltinName.data()+8, "opc_i", 5))
break;
return Intrinsic::nvvm_popc_i; // "__nvvm_popc_i"
case 's': // 1 string to match.
if (memcmp(BuiltinName.data()+8, "ad_ui", 5))
break;
return Intrinsic::nvvm_sad_ui; // "__nvvm_sad_ui"
}
break;
case 's': // 1 string to match.
if (memcmp(BuiltinName.data()+3, "yncthreads", 10))
break;
return Intrinsic::cuda_syncthreads; // "__syncthreads"
}
break;
case 14: // 47 strings to match.
if (memcmp(BuiltinName.data()+0, "__", 2))
break;
switch (BuiltinName[2]) {
default: break;
case 'b': // 1 string to match.
if (memcmp(BuiltinName.data()+3, "uiltin_trap", 11))
break;
return Intrinsic::trap; // "__builtin_trap"
case 'g': // 2 strings to match.
if (memcmp(BuiltinName.data()+3, "nu_", 3))
break;
switch (BuiltinName[6]) {
default: break;
case 'f': // 1 string to match.
if (memcmp(BuiltinName.data()+7, "2h_ieee", 7))
break;
return Intrinsic::convert_to_fp16; // "__gnu_f2h_ieee"
case 'h': // 1 string to match.
if (memcmp(BuiltinName.data()+7, "2f_ieee", 7))
break;
return Intrinsic::convert_from_fp16; // "__gnu_h2f_ieee"
}
break;
case 'n': // 44 strings to match.
if (memcmp(BuiltinName.data()+3, "vvm_", 4))
break;
switch (BuiltinName[7]) {
default: break;
case 'b': // 1 string to match.
if (memcmp(BuiltinName.data()+8, "ar0_or", 6))
break;
return Intrinsic::nvvm_barrier0_or; // "__nvvm_bar0_or"
case 'd': // 8 strings to match.
if (BuiltinName[8] != '2')
break;
switch (BuiltinName[9]) {
default: break;
case 'l': // 4 strings to match.
if (memcmp(BuiltinName.data()+10, "l_r", 3))
break;
switch (BuiltinName[13]) {
default: break;
case 'm': // 1 string to match.
return Intrinsic::nvvm_d2ll_rm; // "__nvvm_d2ll_rm"
case 'n': // 1 string to match.
return Intrinsic::nvvm_d2ll_rn; // "__nvvm_d2ll_rn"
case 'p': // 1 string to match.
return Intrinsic::nvvm_d2ll_rp; // "__nvvm_d2ll_rp"
case 'z': // 1 string to match.
return Intrinsic::nvvm_d2ll_rz; // "__nvvm_d2ll_rz"
}
break;
case 'u': // 4 strings to match.
if (memcmp(BuiltinName.data()+10, "i_r", 3))
break;
switch (BuiltinName[13]) {
default: break;
case 'm': // 1 string to match.
return Intrinsic::nvvm_d2ui_rm; // "__nvvm_d2ui_rm"
case 'n': // 1 string to match.
return Intrinsic::nvvm_d2ui_rn; // "__nvvm_d2ui_rn"
case 'p': // 1 string to match.
return Intrinsic::nvvm_d2ui_rp; // "__nvvm_d2ui_rp"
case 'z': // 1 string to match.
return Intrinsic::nvvm_d2ui_rz; // "__nvvm_d2ui_rz"
}
break;
}
break;
case 'f': // 10 strings to match.
switch (BuiltinName[8]) {
default: break;
case '2': // 8 strings to match.
switch (BuiltinName[9]) {
default: break;
case 'l': // 4 strings to match.
if (memcmp(BuiltinName.data()+10, "l_r", 3))
break;
switch (BuiltinName[13]) {
default: break;
case 'm': // 1 string to match.
return Intrinsic::nvvm_f2ll_rm; // "__nvvm_f2ll_rm"
case 'n': // 1 string to match.
return Intrinsic::nvvm_f2ll_rn; // "__nvvm_f2ll_rn"
case 'p': // 1 string to match.
return Intrinsic::nvvm_f2ll_rp; // "__nvvm_f2ll_rp"
case 'z': // 1 string to match.
return Intrinsic::nvvm_f2ll_rz; // "__nvvm_f2ll_rz"
}
break;
case 'u': // 4 strings to match.
if (memcmp(BuiltinName.data()+10, "i_r", 3))
break;
switch (BuiltinName[13]) {
default: break;
case 'm': // 1 string to match.
return Intrinsic::nvvm_f2ui_rm; // "__nvvm_f2ui_rm"
case 'n': // 1 string to match.
return Intrinsic::nvvm_f2ui_rn; // "__nvvm_f2ui_rn"
case 'p': // 1 string to match.
return Intrinsic::nvvm_f2ui_rp; // "__nvvm_f2ui_rp"
case 'z': // 1 string to match.
return Intrinsic::nvvm_f2ui_rz; // "__nvvm_f2ui_rz"
}
break;
}
break;
case 'l': // 2 strings to match.
if (memcmp(BuiltinName.data()+9, "oor_", 4))
break;
switch (BuiltinName[13]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::nvvm_floor_d; // "__nvvm_floor_d"
case 'f': // 1 string to match.
return Intrinsic::nvvm_floor_f; // "__nvvm_floor_f"
}
break;
}
break;
case 'l': // 8 strings to match.
if (memcmp(BuiltinName.data()+8, "l2", 2))
break;
switch (BuiltinName[10]) {
default: break;
case 'd': // 4 strings to match.
if (memcmp(BuiltinName.data()+11, "_r", 2))
break;
switch (BuiltinName[13]) {
default: break;
case 'm': // 1 string to match.
return Intrinsic::nvvm_ll2d_rm; // "__nvvm_ll2d_rm"
case 'n': // 1 string to match.
return Intrinsic::nvvm_ll2d_rn; // "__nvvm_ll2d_rn"
case 'p': // 1 string to match.
return Intrinsic::nvvm_ll2d_rp; // "__nvvm_ll2d_rp"
case 'z': // 1 string to match.
return Intrinsic::nvvm_ll2d_rz; // "__nvvm_ll2d_rz"
}
break;
case 'f': // 4 strings to match.
if (memcmp(BuiltinName.data()+11, "_r", 2))
break;
switch (BuiltinName[13]) {
default: break;
case 'm': // 1 string to match.
return Intrinsic::nvvm_ll2f_rm; // "__nvvm_ll2f_rm"
case 'n': // 1 string to match.
return Intrinsic::nvvm_ll2f_rn; // "__nvvm_ll2f_rn"
case 'p': // 1 string to match.
return Intrinsic::nvvm_ll2f_rp; // "__nvvm_ll2f_rp"
case 'z': // 1 string to match.
return Intrinsic::nvvm_ll2f_rz; // "__nvvm_ll2f_rz"
}
break;
}
break;
case 'm': // 4 strings to match.
switch (BuiltinName[8]) {
default: break;
case 'a': // 1 string to match.
if (memcmp(BuiltinName.data()+9, "x_ull", 5))
break;
return Intrinsic::nvvm_max_ull; // "__nvvm_max_ull"
case 'i': // 1 string to match.
if (memcmp(BuiltinName.data()+9, "n_ull", 5))
break;
return Intrinsic::nvvm_min_ull; // "__nvvm_min_ull"
case 'u': // 2 strings to match.
if (BuiltinName[9] != 'l')
break;
switch (BuiltinName[10]) {
default: break;
case '2': // 1 string to match.
if (memcmp(BuiltinName.data()+11, "4_i", 3))
break;
return Intrinsic::nvvm_mul24_i; // "__nvvm_mul24_i"
case 'h': // 1 string to match.
if (memcmp(BuiltinName.data()+11, "i_i", 3))
break;
return Intrinsic::nvvm_mulhi_i; // "__nvvm_mulhi_i"
}
break;
}
break;
case 'p': // 1 string to match.
if (memcmp(BuiltinName.data()+8, "opc_ll", 6))
break;
return Intrinsic::nvvm_popc_ll; // "__nvvm_popc_ll"
case 'r': // 2 strings to match.
if (memcmp(BuiltinName.data()+8, "ound_", 5))
break;
switch (BuiltinName[13]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::nvvm_round_d; // "__nvvm_round_d"
case 'f': // 1 string to match.
return Intrinsic::nvvm_round_f; // "__nvvm_round_f"
}
break;
case 't': // 2 strings to match.
if (memcmp(BuiltinName.data()+8, "runc_", 5))
break;
switch (BuiltinName[13]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::nvvm_trunc_d; // "__nvvm_trunc_d"
case 'f': // 1 string to match.
return Intrinsic::nvvm_trunc_f; // "__nvvm_trunc_f"
}
break;
case 'u': // 8 strings to match.
if (memcmp(BuiltinName.data()+8, "i2", 2))
break;
switch (BuiltinName[10]) {
default: break;
case 'd': // 4 strings to match.
if (memcmp(BuiltinName.data()+11, "_r", 2))
break;
switch (BuiltinName[13]) {
default: break;
case 'm': // 1 string to match.
return Intrinsic::nvvm_ui2d_rm; // "__nvvm_ui2d_rm"
case 'n': // 1 string to match.
return Intrinsic::nvvm_ui2d_rn; // "__nvvm_ui2d_rn"
case 'p': // 1 string to match.
return Intrinsic::nvvm_ui2d_rp; // "__nvvm_ui2d_rp"
case 'z': // 1 string to match.
return Intrinsic::nvvm_ui2d_rz; // "__nvvm_ui2d_rz"
}
break;
case 'f': // 4 strings to match.
if (memcmp(BuiltinName.data()+11, "_r", 2))
break;
switch (BuiltinName[13]) {
default: break;
case 'm': // 1 string to match.
return Intrinsic::nvvm_ui2f_rm; // "__nvvm_ui2f_rm"
case 'n': // 1 string to match.
return Intrinsic::nvvm_ui2f_rn; // "__nvvm_ui2f_rn"
case 'p': // 1 string to match.
return Intrinsic::nvvm_ui2f_rp; // "__nvvm_ui2f_rp"
case 'z': // 1 string to match.
return Intrinsic::nvvm_ui2f_rz; // "__nvvm_ui2f_rz"
}
break;
}
break;
}
break;
}
break;
case 15: // 61 strings to match.
if (memcmp(BuiltinName.data()+0, "__nvvm_", 7))
break;
switch (BuiltinName[7]) {
default: break;
case 'a': // 8 strings to match.
if (memcmp(BuiltinName.data()+8, "dd_r", 4))
break;
switch (BuiltinName[12]) {
default: break;
case 'm': // 2 strings to match.
if (BuiltinName[13] != '_')
break;
switch (BuiltinName[14]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::nvvm_add_rm_d; // "__nvvm_add_rm_d"
case 'f': // 1 string to match.
return Intrinsic::nvvm_add_rm_f; // "__nvvm_add_rm_f"
}
break;
case 'n': // 2 strings to match.
if (BuiltinName[13] != '_')
break;
switch (BuiltinName[14]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::nvvm_add_rn_d; // "__nvvm_add_rn_d"
case 'f': // 1 string to match.
return Intrinsic::nvvm_add_rn_f; // "__nvvm_add_rn_f"
}
break;
case 'p': // 2 strings to match.
if (BuiltinName[13] != '_')
break;
switch (BuiltinName[14]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::nvvm_add_rp_d; // "__nvvm_add_rp_d"
case 'f': // 1 string to match.
return Intrinsic::nvvm_add_rp_f; // "__nvvm_add_rp_f"
}
break;
case 'z': // 2 strings to match.
if (BuiltinName[13] != '_')
break;
switch (BuiltinName[14]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::nvvm_add_rz_d; // "__nvvm_add_rz_d"
case 'f': // 1 string to match.
return Intrinsic::nvvm_add_rz_f; // "__nvvm_add_rz_f"
}
break;
}
break;
case 'b': // 1 string to match.
if (memcmp(BuiltinName.data()+8, "ar0_and", 7))
break;
return Intrinsic::nvvm_barrier0_and; // "__nvvm_bar0_and"
case 'd': // 12 strings to match.
switch (BuiltinName[8]) {
default: break;
case '2': // 4 strings to match.
if (memcmp(BuiltinName.data()+9, "ull_r", 5))
break;
switch (BuiltinName[14]) {
default: break;
case 'm': // 1 string to match.
return Intrinsic::nvvm_d2ull_rm; // "__nvvm_d2ull_rm"
case 'n': // 1 string to match.
return Intrinsic::nvvm_d2ull_rn; // "__nvvm_d2ull_rn"
case 'p': // 1 string to match.
return Intrinsic::nvvm_d2ull_rp; // "__nvvm_d2ull_rp"
case 'z': // 1 string to match.
return Intrinsic::nvvm_d2ull_rz; // "__nvvm_d2ull_rz"
}
break;
case 'i': // 8 strings to match.
if (memcmp(BuiltinName.data()+9, "v_r", 3))
break;
switch (BuiltinName[12]) {
default: break;
case 'm': // 2 strings to match.
if (BuiltinName[13] != '_')
break;
switch (BuiltinName[14]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::nvvm_div_rm_d; // "__nvvm_div_rm_d"
case 'f': // 1 string to match.
return Intrinsic::nvvm_div_rm_f; // "__nvvm_div_rm_f"
}
break;
case 'n': // 2 strings to match.
if (BuiltinName[13] != '_')
break;
switch (BuiltinName[14]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::nvvm_div_rn_d; // "__nvvm_div_rn_d"
case 'f': // 1 string to match.
return Intrinsic::nvvm_div_rn_f; // "__nvvm_div_rn_f"
}
break;
case 'p': // 2 strings to match.
if (BuiltinName[13] != '_')
break;
switch (BuiltinName[14]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::nvvm_div_rp_d; // "__nvvm_div_rp_d"
case 'f': // 1 string to match.
return Intrinsic::nvvm_div_rp_f; // "__nvvm_div_rp_f"
}
break;
case 'z': // 2 strings to match.
if (BuiltinName[13] != '_')
break;
switch (BuiltinName[14]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::nvvm_div_rz_d; // "__nvvm_div_rz_d"
case 'f': // 1 string to match.
return Intrinsic::nvvm_div_rz_f; // "__nvvm_div_rz_f"
}
break;
}
break;
}
break;
case 'f': // 12 strings to match.
switch (BuiltinName[8]) {
default: break;
case '2': // 4 strings to match.
if (memcmp(BuiltinName.data()+9, "ull_r", 5))
break;
switch (BuiltinName[14]) {
default: break;
case 'm': // 1 string to match.
return Intrinsic::nvvm_f2ull_rm; // "__nvvm_f2ull_rm"
case 'n': // 1 string to match.
return Intrinsic::nvvm_f2ull_rn; // "__nvvm_f2ull_rn"
case 'p': // 1 string to match.
return Intrinsic::nvvm_f2ull_rp; // "__nvvm_f2ull_rp"
case 'z': // 1 string to match.
return Intrinsic::nvvm_f2ull_rz; // "__nvvm_f2ull_rz"
}
break;
case 'm': // 8 strings to match.
if (memcmp(BuiltinName.data()+9, "a_r", 3))
break;
switch (BuiltinName[12]) {
default: break;
case 'm': // 2 strings to match.
if (BuiltinName[13] != '_')
break;
switch (BuiltinName[14]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::nvvm_fma_rm_d; // "__nvvm_fma_rm_d"
case 'f': // 1 string to match.
return Intrinsic::nvvm_fma_rm_f; // "__nvvm_fma_rm_f"
}
break;
case 'n': // 2 strings to match.
if (BuiltinName[13] != '_')
break;
switch (BuiltinName[14]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::nvvm_fma_rn_d; // "__nvvm_fma_rn_d"
case 'f': // 1 string to match.
return Intrinsic::nvvm_fma_rn_f; // "__nvvm_fma_rn_f"
}
break;
case 'p': // 2 strings to match.
if (BuiltinName[13] != '_')
break;
switch (BuiltinName[14]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::nvvm_fma_rp_d; // "__nvvm_fma_rp_d"
case 'f': // 1 string to match.
return Intrinsic::nvvm_fma_rp_f; // "__nvvm_fma_rp_f"
}
break;
case 'z': // 2 strings to match.
if (BuiltinName[13] != '_')
break;
switch (BuiltinName[14]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::nvvm_fma_rz_d; // "__nvvm_fma_rz_d"
case 'f': // 1 string to match.
return Intrinsic::nvvm_fma_rz_f; // "__nvvm_fma_rz_f"
}
break;
}
break;
}
break;
case 'l': // 1 string to match.
if (memcmp(BuiltinName.data()+8, "ohi_i2d", 7))
break;
return Intrinsic::nvvm_lohi_i2d; // "__nvvm_lohi_i2d"
case 'm': // 11 strings to match.
if (memcmp(BuiltinName.data()+8, "ul", 2))
break;
switch (BuiltinName[10]) {
default: break;
case '2': // 1 string to match.
if (memcmp(BuiltinName.data()+11, "4_ui", 4))
break;
return Intrinsic::nvvm_mul24_ui; // "__nvvm_mul24_ui"
case '_': // 8 strings to match.
if (BuiltinName[11] != 'r')
break;
switch (BuiltinName[12]) {
default: break;
case 'm': // 2 strings to match.
if (BuiltinName[13] != '_')
break;
switch (BuiltinName[14]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::nvvm_mul_rm_d; // "__nvvm_mul_rm_d"
case 'f': // 1 string to match.
return Intrinsic::nvvm_mul_rm_f; // "__nvvm_mul_rm_f"
}
break;
case 'n': // 2 strings to match.
if (BuiltinName[13] != '_')
break;
switch (BuiltinName[14]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::nvvm_mul_rn_d; // "__nvvm_mul_rn_d"
case 'f': // 1 string to match.
return Intrinsic::nvvm_mul_rn_f; // "__nvvm_mul_rn_f"
}
break;
case 'p': // 2 strings to match.
if (BuiltinName[13] != '_')
break;
switch (BuiltinName[14]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::nvvm_mul_rp_d; // "__nvvm_mul_rp_d"
case 'f': // 1 string to match.
return Intrinsic::nvvm_mul_rp_f; // "__nvvm_mul_rp_f"
}
break;
case 'z': // 2 strings to match.
if (BuiltinName[13] != '_')
break;
switch (BuiltinName[14]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::nvvm_mul_rz_d; // "__nvvm_mul_rz_d"
case 'f': // 1 string to match.
return Intrinsic::nvvm_mul_rz_f; // "__nvvm_mul_rz_f"
}
break;
}
break;
case 'h': // 2 strings to match.
if (memcmp(BuiltinName.data()+11, "i_", 2))
break;
switch (BuiltinName[13]) {
default: break;
case 'l': // 1 string to match.
if (BuiltinName[14] != 'l')
break;
return Intrinsic::nvvm_mulhi_ll; // "__nvvm_mulhi_ll"
case 'u': // 1 string to match.
if (BuiltinName[14] != 'i')
break;
return Intrinsic::nvvm_mulhi_ui; // "__nvvm_mulhi_ui"
}
break;
}
break;
case 'r': // 8 strings to match.
if (memcmp(BuiltinName.data()+8, "cp_r", 4))
break;
switch (BuiltinName[12]) {
default: break;
case 'm': // 2 strings to match.
if (BuiltinName[13] != '_')
break;
switch (BuiltinName[14]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::nvvm_rcp_rm_d; // "__nvvm_rcp_rm_d"
case 'f': // 1 string to match.
return Intrinsic::nvvm_rcp_rm_f; // "__nvvm_rcp_rm_f"
}
break;
case 'n': // 2 strings to match.
if (BuiltinName[13] != '_')
break;
switch (BuiltinName[14]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::nvvm_rcp_rn_d; // "__nvvm_rcp_rn_d"
case 'f': // 1 string to match.
return Intrinsic::nvvm_rcp_rn_f; // "__nvvm_rcp_rn_f"
}
break;
case 'p': // 2 strings to match.
if (BuiltinName[13] != '_')
break;
switch (BuiltinName[14]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::nvvm_rcp_rp_d; // "__nvvm_rcp_rp_d"
case 'f': // 1 string to match.
return Intrinsic::nvvm_rcp_rp_f; // "__nvvm_rcp_rp_f"
}
break;
case 'z': // 2 strings to match.
if (BuiltinName[13] != '_')
break;
switch (BuiltinName[14]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::nvvm_rcp_rz_d; // "__nvvm_rcp_rz_d"
case 'f': // 1 string to match.
return Intrinsic::nvvm_rcp_rz_f; // "__nvvm_rcp_rz_f"
}
break;
}
break;
case 'u': // 8 strings to match.
if (memcmp(BuiltinName.data()+8, "ll2", 3))
break;
switch (BuiltinName[11]) {
default: break;
case 'd': // 4 strings to match.
if (memcmp(BuiltinName.data()+12, "_r", 2))
break;
switch (BuiltinName[14]) {
default: break;
case 'm': // 1 string to match.
return Intrinsic::nvvm_ull2d_rm; // "__nvvm_ull2d_rm"
case 'n': // 1 string to match.
return Intrinsic::nvvm_ull2d_rn; // "__nvvm_ull2d_rn"
case 'p': // 1 string to match.
return Intrinsic::nvvm_ull2d_rp; // "__nvvm_ull2d_rp"
case 'z': // 1 string to match.
return Intrinsic::nvvm_ull2d_rz; // "__nvvm_ull2d_rz"
}
break;
case 'f': // 4 strings to match.
if (memcmp(BuiltinName.data()+12, "_r", 2))
break;
switch (BuiltinName[14]) {
default: break;
case 'm': // 1 string to match.
return Intrinsic::nvvm_ull2f_rm; // "__nvvm_ull2f_rm"
case 'n': // 1 string to match.
return Intrinsic::nvvm_ull2f_rn; // "__nvvm_ull2f_rn"
case 'p': // 1 string to match.
return Intrinsic::nvvm_ull2f_rp; // "__nvvm_ull2f_rp"
case 'z': // 1 string to match.
return Intrinsic::nvvm_ull2f_rz; // "__nvvm_ull2f_rz"
}
break;
}
break;
}
break;
case 16: // 11 strings to match.
if (memcmp(BuiltinName.data()+0, "__nvvm_", 7))
break;
switch (BuiltinName[7]) {
default: break;
case 'b': // 1 string to match.
if (memcmp(BuiltinName.data()+8, "ar0_popc", 8))
break;
return Intrinsic::nvvm_barrier0_popc; // "__nvvm_bar0_popc"
case 'm': // 2 strings to match.
switch (BuiltinName[8]) {
default: break;
case 'e': // 1 string to match.
if (memcmp(BuiltinName.data()+9, "mbar_gl", 7))
break;
return Intrinsic::nvvm_membar_gl; // "__nvvm_membar_gl"
case 'u': // 1 string to match.
if (memcmp(BuiltinName.data()+9, "lhi_ull", 7))
break;
return Intrinsic::nvvm_mulhi_ull; // "__nvvm_mulhi_ull"
}
break;
case 's': // 8 strings to match.
if (memcmp(BuiltinName.data()+8, "qrt_r", 5))
break;
switch (BuiltinName[13]) {
default: break;
case 'm': // 2 strings to match.
if (BuiltinName[14] != '_')
break;
switch (BuiltinName[15]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::nvvm_sqrt_rm_d; // "__nvvm_sqrt_rm_d"
case 'f': // 1 string to match.
return Intrinsic::nvvm_sqrt_rm_f; // "__nvvm_sqrt_rm_f"
}
break;
case 'n': // 2 strings to match.
if (BuiltinName[14] != '_')
break;
switch (BuiltinName[15]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::nvvm_sqrt_rn_d; // "__nvvm_sqrt_rn_d"
case 'f': // 1 string to match.
return Intrinsic::nvvm_sqrt_rn_f; // "__nvvm_sqrt_rn_f"
}
break;
case 'p': // 2 strings to match.
if (BuiltinName[14] != '_')
break;
switch (BuiltinName[15]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::nvvm_sqrt_rp_d; // "__nvvm_sqrt_rp_d"
case 'f': // 1 string to match.
return Intrinsic::nvvm_sqrt_rp_f; // "__nvvm_sqrt_rp_f"
}
break;
case 'z': // 2 strings to match.
if (BuiltinName[14] != '_')
break;
switch (BuiltinName[15]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::nvvm_sqrt_rz_d; // "__nvvm_sqrt_rz_d"
case 'f': // 1 string to match.
return Intrinsic::nvvm_sqrt_rz_f; // "__nvvm_sqrt_rz_f"
}
break;
}
break;
}
break;
case 17: // 17 strings to match.
if (memcmp(BuiltinName.data()+0, "__nvvm_", 7))
break;
switch (BuiltinName[7]) {
default: break;
case 'c': // 1 string to match.
if (memcmp(BuiltinName.data()+8, "eil_ftz_f", 9))
break;
return Intrinsic::nvvm_ceil_ftz_f; // "__nvvm_ceil_ftz_f"
case 'd': // 4 strings to match.
if (memcmp(BuiltinName.data()+8, "2f_r", 4))
break;
switch (BuiltinName[12]) {
default: break;
case 'm': // 1 string to match.
if (memcmp(BuiltinName.data()+13, "_ftz", 4))
break;
return Intrinsic::nvvm_d2f_rm_ftz; // "__nvvm_d2f_rm_ftz"
case 'n': // 1 string to match.
if (memcmp(BuiltinName.data()+13, "_ftz", 4))
break;
return Intrinsic::nvvm_d2f_rn_ftz; // "__nvvm_d2f_rn_ftz"
case 'p': // 1 string to match.
if (memcmp(BuiltinName.data()+13, "_ftz", 4))
break;
return Intrinsic::nvvm_d2f_rp_ftz; // "__nvvm_d2f_rp_ftz"
case 'z': // 1 string to match.
if (memcmp(BuiltinName.data()+13, "_ftz", 4))
break;
return Intrinsic::nvvm_d2f_rz_ftz; // "__nvvm_d2f_rz_ftz"
}
break;
case 'f': // 8 strings to match.
switch (BuiltinName[8]) {
default: break;
case '2': // 5 strings to match.
switch (BuiltinName[9]) {
default: break;
case 'h': // 1 string to match.
if (memcmp(BuiltinName.data()+10, "_rn_ftz", 7))
break;
return Intrinsic::nvvm_f2h_rn_ftz; // "__nvvm_f2h_rn_ftz"
case 'i': // 4 strings to match.
if (memcmp(BuiltinName.data()+10, "_r", 2))
break;
switch (BuiltinName[12]) {
default: break;
case 'm': // 1 string to match.
if (memcmp(BuiltinName.data()+13, "_ftz", 4))
break;
return Intrinsic::nvvm_f2i_rm_ftz; // "__nvvm_f2i_rm_ftz"
case 'n': // 1 string to match.
if (memcmp(BuiltinName.data()+13, "_ftz", 4))
break;
return Intrinsic::nvvm_f2i_rn_ftz; // "__nvvm_f2i_rn_ftz"
case 'p': // 1 string to match.
if (memcmp(BuiltinName.data()+13, "_ftz", 4))
break;
return Intrinsic::nvvm_f2i_rp_ftz; // "__nvvm_f2i_rp_ftz"
case 'z': // 1 string to match.
if (memcmp(BuiltinName.data()+13, "_ftz", 4))
break;
return Intrinsic::nvvm_f2i_rz_ftz; // "__nvvm_f2i_rz_ftz"
}
break;
}
break;
case 'a': // 1 string to match.
if (memcmp(BuiltinName.data()+9, "bs_ftz_f", 8))
break;
return Intrinsic::nvvm_fabs_ftz_f; // "__nvvm_fabs_ftz_f"
case 'm': // 2 strings to match.
switch (BuiltinName[9]) {
default: break;
case 'a': // 1 string to match.
if (memcmp(BuiltinName.data()+10, "x_ftz_f", 7))
break;
return Intrinsic::nvvm_fmax_ftz_f; // "__nvvm_fmax_ftz_f"
case 'i': // 1 string to match.
if (memcmp(BuiltinName.data()+10, "n_ftz_f", 7))
break;
return Intrinsic::nvvm_fmin_ftz_f; // "__nvvm_fmin_ftz_f"
}
break;
}
break;
case 'm': // 2 strings to match.
if (memcmp(BuiltinName.data()+8, "embar_", 6))
break;
switch (BuiltinName[14]) {
default: break;
case 'c': // 1 string to match.
if (memcmp(BuiltinName.data()+15, "ta", 2))
break;
return Intrinsic::nvvm_membar_cta; // "__nvvm_membar_cta"
case 's': // 1 string to match.
if (memcmp(BuiltinName.data()+15, "ys", 2))
break;
return Intrinsic::nvvm_membar_sys; // "__nvvm_membar_sys"
}
break;
case 's': // 2 strings to match.
if (memcmp(BuiltinName.data()+8, "aturate_", 8))
break;
switch (BuiltinName[16]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::nvvm_saturate_d; // "__nvvm_saturate_d"
case 'f': // 1 string to match.
return Intrinsic::nvvm_saturate_f; // "__nvvm_saturate_f"
}
break;
}
break;
case 18: // 13 strings to match.
if (memcmp(BuiltinName.data()+0, "__nvvm_", 7))
break;
switch (BuiltinName[7]) {
default: break;
case 'b': // 2 strings to match.
if (memcmp(BuiltinName.data()+8, "itcast_", 7))
break;
switch (BuiltinName[15]) {
default: break;
case 'f': // 1 string to match.
if (memcmp(BuiltinName.data()+16, "2i", 2))
break;
return Intrinsic::nvvm_bitcast_f2i; // "__nvvm_bitcast_f2i"
case 'i': // 1 string to match.
if (memcmp(BuiltinName.data()+16, "2f", 2))
break;
return Intrinsic::nvvm_bitcast_i2f; // "__nvvm_bitcast_i2f"
}
break;
case 'f': // 9 strings to match.
switch (BuiltinName[8]) {
default: break;
case '2': // 8 strings to match.
switch (BuiltinName[9]) {
default: break;
case 'l': // 4 strings to match.
if (memcmp(BuiltinName.data()+10, "l_r", 3))
break;
switch (BuiltinName[13]) {
default: break;
case 'm': // 1 string to match.
if (memcmp(BuiltinName.data()+14, "_ftz", 4))
break;
return Intrinsic::nvvm_f2ll_rm_ftz; // "__nvvm_f2ll_rm_
ftz"
case 'n': // 1 string to match.
if (memcmp(BuiltinName.data()+14, "_ftz", 4))
break;
return Intrinsic::nvvm_f2ll_rn_ftz; // "__nvvm_f2ll_rn_
ftz"
case 'p': // 1 string to match.
if (memcmp(BuiltinName.data()+14, "_ftz", 4))
break;
return Intrinsic::nvvm_f2ll_rp_ftz; // "__nvvm_f2ll_rp_
ftz"
case 'z': // 1 string to match.
if (memcmp(BuiltinName.data()+14, "_ftz", 4))
break;
return Intrinsic::nvvm_f2ll_rz_ftz; // "__nvvm_f2ll_rz_
ftz"
}
break;
case 'u': // 4 strings to match.
if (memcmp(BuiltinName.data()+10, "i_r", 3))
break;
switch (BuiltinName[13]) {
default: break;
case 'm': // 1 string to match.
if (memcmp(BuiltinName.data()+14, "_ftz", 4))
break;
return Intrinsic::nvvm_f2ui_rm_ftz; // "__nvvm_f2ui_rm_
ftz"
case 'n': // 1 string to match.
if (memcmp(BuiltinName.data()+14, "_ftz", 4))
break;
return Intrinsic::nvvm_f2ui_rn_ftz; // "__nvvm_f2ui_rn_
ftz"
case 'p': // 1 string to match.
if (memcmp(BuiltinName.data()+14, "_ftz", 4))
break;
return Intrinsic::nvvm_f2ui_rp_ftz; // "__nvvm_f2ui_rp_
ftz"
case 'z': // 1 string to match.
if (memcmp(BuiltinName.data()+14, "_ftz", 4))
break;
return Intrinsic::nvvm_f2ui_rz_ftz; // "__nvvm_f2ui_rz_
ftz"
}
break;
}
break;
case 'l': // 1 string to match.
if (memcmp(BuiltinName.data()+9, "oor_ftz_f", 9))
break;
return Intrinsic::nvvm_floor_ftz_f; // "__nvvm_floor_ftz_f"
}
break;
case 'r': // 1 string to match.
if (memcmp(BuiltinName.data()+8, "ound_ftz_f", 10))
break;
return Intrinsic::nvvm_round_ftz_f; // "__nvvm_round_ftz_f"
case 't': // 1 string to match.
if (memcmp(BuiltinName.data()+8, "runc_ftz_f", 10))
break;
return Intrinsic::nvvm_trunc_ftz_f; // "__nvvm_trunc_ftz_f"
}
break;
case 19: // 34 strings to match.
if (memcmp(BuiltinName.data()+0, "__", 2))
break;
switch (BuiltinName[2]) {
default: break;
case 'b': // 1 string to match.
if (memcmp(BuiltinName.data()+3, "uiltin_debugtrap", 16))
break;
return Intrinsic::debugtrap; // "__builtin_debugtrap"
case 'n': // 33 strings to match.
if (memcmp(BuiltinName.data()+3, "vvm_", 4))
break;
switch (BuiltinName[7]) {
default: break;
case 'a': // 4 strings to match.
if (memcmp(BuiltinName.data()+8, "dd_r", 4))
break;
switch (BuiltinName[12]) {
default: break;
case 'm': // 1 string to match.
if (memcmp(BuiltinName.data()+13, "_ftz_f", 6))
break;
return Intrinsic::nvvm_add_rm_ftz_f; // "__nvvm_add_rm_ftz_f"
case 'n': // 1 string to match.
if (memcmp(BuiltinName.data()+13, "_ftz_f", 6))
break;
return Intrinsic::nvvm_add_rn_ftz_f; // "__nvvm_add_rn_ftz_f"
case 'p': // 1 string to match.
if (memcmp(BuiltinName.data()+13, "_ftz_f", 6))
break;
return Intrinsic::nvvm_add_rp_ftz_f; // "__nvvm_add_rp_ftz_f"
case 'z': // 1 string to match.
if (memcmp(BuiltinName.data()+13, "_ftz_f", 6))
break;
return Intrinsic::nvvm_add_rz_ftz_f; // "__nvvm_add_rz_ftz_f"
}
break;
case 'b': // 2 strings to match.
if (memcmp(BuiltinName.data()+8, "itcast_", 7))
break;
switch (BuiltinName[15]) {
default: break;
case 'd': // 1 string to match.
if (memcmp(BuiltinName.data()+16, "2ll", 3))
break;
return Intrinsic::nvvm_bitcast_d2ll; // "__nvvm_bitcast_d2ll"
case 'l': // 1 string to match.
if (memcmp(BuiltinName.data()+16, "l2d", 3))
break;
return Intrinsic::nvvm_bitcast_ll2d; // "__nvvm_bitcast_ll2d"
}
break;
case 'c': // 1 string to match.
if (memcmp(BuiltinName.data()+8, "os_approx_f", 11))
break;
return Intrinsic::nvvm_cos_approx_f; // "__nvvm_cos_approx_f"
case 'd': // 5 strings to match.
if (memcmp(BuiltinName.data()+8, "iv_", 3))
break;
switch (BuiltinName[11]) {
default: break;
case 'a': // 1 string to match.
if (memcmp(BuiltinName.data()+12, "pprox_f", 7))
break;
return Intrinsic::nvvm_div_approx_f; // "__nvvm_div_approx_f"
case 'r': // 4 strings to match.
switch (BuiltinName[12]) {
default: break;
case 'm': // 1 string to match.
if (memcmp(BuiltinName.data()+13, "_ftz_f", 6))
break;
return Intrinsic::nvvm_div_rm_ftz_f; // "__nvvm_div_rm_f
tz_f"
case 'n': // 1 string to match.
if (memcmp(BuiltinName.data()+13, "_ftz_f", 6))
break;
return Intrinsic::nvvm_div_rn_ftz_f; // "__nvvm_div_rn_f
tz_f"
case 'p': // 1 string to match.
if (memcmp(BuiltinName.data()+13, "_ftz_f", 6))
break;
return Intrinsic::nvvm_div_rp_ftz_f; // "__nvvm_div_rp_f
tz_f"
case 'z': // 1 string to match.
if (memcmp(BuiltinName.data()+13, "_ftz_f", 6))
break;
return Intrinsic::nvvm_div_rz_ftz_f; // "__nvvm_div_rz_f
tz_f"
}
break;
}
break;
case 'e': // 2 strings to match.
if (memcmp(BuiltinName.data()+8, "x2_approx_", 10))
break;
switch (BuiltinName[18]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::nvvm_ex2_approx_d; // "__nvvm_ex2_approx_d"
case 'f': // 1 string to match.
return Intrinsic::nvvm_ex2_approx_f; // "__nvvm_ex2_approx_f"
}
break;
case 'f': // 8 strings to match.
switch (BuiltinName[8]) {
default: break;
case '2': // 4 strings to match.
if (memcmp(BuiltinName.data()+9, "ull_r", 5))
break;
switch (BuiltinName[14]) {
default: break;
case 'm': // 1 string to match.
if (memcmp(BuiltinName.data()+15, "_ftz", 4))
break;
return Intrinsic::nvvm_f2ull_rm_ftz; // "__nvvm_f2ull_rm
_ftz"
case 'n': // 1 string to match.
if (memcmp(BuiltinName.data()+15, "_ftz", 4))
break;
return Intrinsic::nvvm_f2ull_rn_ftz; // "__nvvm_f2ull_rn
_ftz"
case 'p': // 1 string to match.
if (memcmp(BuiltinName.data()+15, "_ftz", 4))
break;
return Intrinsic::nvvm_f2ull_rp_ftz; // "__nvvm_f2ull_rp
_ftz"
case 'z': // 1 string to match.
if (memcmp(BuiltinName.data()+15, "_ftz", 4))
break;
return Intrinsic::nvvm_f2ull_rz_ftz; // "__nvvm_f2ull_rz
_ftz"
}
break;
case 'm': // 4 strings to match.
if (memcmp(BuiltinName.data()+9, "a_r", 3))
break;
switch (BuiltinName[12]) {
default: break;
case 'm': // 1 string to match.
if (memcmp(BuiltinName.data()+13, "_ftz_f", 6))
break;
return Intrinsic::nvvm_fma_rm_ftz_f; // "__nvvm_fma_rm_f
tz_f"
case 'n': // 1 string to match.
if (memcmp(BuiltinName.data()+13, "_ftz_f", 6))
break;
return Intrinsic::nvvm_fma_rn_ftz_f; // "__nvvm_fma_rn_f
tz_f"
case 'p': // 1 string to match.
if (memcmp(BuiltinName.data()+13, "_ftz_f", 6))
break;
return Intrinsic::nvvm_fma_rp_ftz_f; // "__nvvm_fma_rp_f
tz_f"
case 'z': // 1 string to match.
if (memcmp(BuiltinName.data()+13, "_ftz_f", 6))
break;
return Intrinsic::nvvm_fma_rz_ftz_f; // "__nvvm_fma_rz_f
tz_f"
}
break;
}
break;
case 'l': // 2 strings to match.
if (memcmp(BuiltinName.data()+8, "g2_approx_", 10))
break;
switch (BuiltinName[18]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::nvvm_lg2_approx_d; // "__nvvm_lg2_approx_d"
case 'f': // 1 string to match.
return Intrinsic::nvvm_lg2_approx_f; // "__nvvm_lg2_approx_f"
}
break;
case 'm': // 4 strings to match.
if (memcmp(BuiltinName.data()+8, "ul_r", 4))
break;
switch (BuiltinName[12]) {
default: break;
case 'm': // 1 string to match.
if (memcmp(BuiltinName.data()+13, "_ftz_f", 6))
break;
return Intrinsic::nvvm_mul_rm_ftz_f; // "__nvvm_mul_rm_ftz_f"
case 'n': // 1 string to match.
if (memcmp(BuiltinName.data()+13, "_ftz_f", 6))
break;
return Intrinsic::nvvm_mul_rn_ftz_f; // "__nvvm_mul_rn_ftz_f"
case 'p': // 1 string to match.
if (memcmp(BuiltinName.data()+13, "_ftz_f", 6))
break;
return Intrinsic::nvvm_mul_rp_ftz_f; // "__nvvm_mul_rp_ftz_f"
case 'z': // 1 string to match.
if (memcmp(BuiltinName.data()+13, "_ftz_f", 6))
break;
return Intrinsic::nvvm_mul_rz_ftz_f; // "__nvvm_mul_rz_ftz_f"
}
break;
case 'r': // 4 strings to match.
if (memcmp(BuiltinName.data()+8, "cp_r", 4))
break;
switch (BuiltinName[12]) {
default: break;
case 'm': // 1 string to match.
if (memcmp(BuiltinName.data()+13, "_ftz_f", 6))
break;
return Intrinsic::nvvm_rcp_rm_ftz_f; // "__nvvm_rcp_rm_ftz_f"
case 'n': // 1 string to match.
if (memcmp(BuiltinName.data()+13, "_ftz_f", 6))
break;
return Intrinsic::nvvm_rcp_rn_ftz_f; // "__nvvm_rcp_rn_ftz_f"
case 'p': // 1 string to match.
if (memcmp(BuiltinName.data()+13, "_ftz_f", 6))
break;
return Intrinsic::nvvm_rcp_rp_ftz_f; // "__nvvm_rcp_rp_ftz_f"
case 'z': // 1 string to match.
if (memcmp(BuiltinName.data()+13, "_ftz_f", 6))
break;
return Intrinsic::nvvm_rcp_rz_ftz_f; // "__nvvm_rcp_rz_ftz_f"
}
break;
case 's': // 1 string to match.
if (memcmp(BuiltinName.data()+8, "in_approx_f", 11))
break;
return Intrinsic::nvvm_sin_approx_f; // "__nvvm_sin_approx_f"
}
break;
}
break;
case 20: // 7 strings to match.
if (memcmp(BuiltinName.data()+0, "__", 2))
break;
switch (BuiltinName[2]) {
default: break;
case 'b': // 2 strings to match.
if (memcmp(BuiltinName.data()+3, "uiltin_", 7))
break;
switch (BuiltinName[10]) {
default: break;
case 'f': // 1 string to match.
if (memcmp(BuiltinName.data()+11, "lt_rounds", 9))
break;
return Intrinsic::flt_rounds; // "__builtin_flt_rounds"
case 's': // 1 string to match.
if (memcmp(BuiltinName.data()+11, "tack_save", 9))
break;
return Intrinsic::stacksave; // "__builtin_stack_save"
}
break;
case 'n': // 5 strings to match.
if (memcmp(BuiltinName.data()+3, "vvm_sqrt_", 9))
break;
switch (BuiltinName[12]) {
default: break;
case 'a': // 1 string to match.
if (memcmp(BuiltinName.data()+13, "pprox_f", 7))
break;
return Intrinsic::nvvm_sqrt_approx_f; // "__nvvm_sqrt_approx_f"
case 'r': // 4 strings to match.
switch (BuiltinName[13]) {
default: break;
case 'm': // 1 string to match.
if (memcmp(BuiltinName.data()+14, "_ftz_f", 6))
break;
return Intrinsic::nvvm_sqrt_rm_ftz_f; // "__nvvm_sqrt_rm_
ftz_f"
case 'n': // 1 string to match.
if (memcmp(BuiltinName.data()+14, "_ftz_f", 6))
break;
return Intrinsic::nvvm_sqrt_rn_ftz_f; // "__nvvm_sqrt_rn_
ftz_f"
case 'p': // 1 string to match.
if (memcmp(BuiltinName.data()+14, "_ftz_f", 6))
break;
return Intrinsic::nvvm_sqrt_rp_ftz_f; // "__nvvm_sqrt_rp_
ftz_f"
case 'z': // 1 string to match.
if (memcmp(BuiltinName.data()+14, "_ftz_f", 6))
break;
return Intrinsic::nvvm_sqrt_rz_ftz_f; // "__nvvm_sqrt_rz_
ftz_f"
}
break;
}
break;
}
break;
case 21: // 23 strings to match.
if (memcmp(BuiltinName.data()+0, "__", 2))
break;
switch (BuiltinName[2]) {
default: break;
case 'b': // 20 strings to match.
if (memcmp(BuiltinName.data()+3, "uiltin_", 7))
break;
switch (BuiltinName[10]) {
default: break;
case 'i': // 18 strings to match.
if (memcmp(BuiltinName.data()+11, "a32_vp", 6))
break;
switch (BuiltinName[17]) {
default: break;
case 'c': // 5 strings to match.
switch (BuiltinName[18]) {
default: break;
case 'm': // 1 string to match.
if (memcmp(BuiltinName.data()+19, "ov", 2))
break;
return Intrinsic::x86_xop_vpcmov; // "__builtin_ia32_vpcmov"
case 'o': // 4 strings to match.
if (BuiltinName[19] != 'm')
break;
switch (BuiltinName[20]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::x86_xop_vpcomb; // "__builtin_ia32_
vpcomb"
case 'd': // 1 string to match.
return Intrinsic::x86_xop_vpcomd; // "__builtin_ia32_
vpcomd"
case 'q': // 1 string to match.
return Intrinsic::x86_xop_vpcomq; // "__builtin_ia32_
vpcomq"
case 'w': // 1 string to match.
return Intrinsic::x86_xop_vpcomw; // "__builtin_ia32_
vpcomw"
}
break;
}
break;
case 'p': // 1 string to match.
if (memcmp(BuiltinName.data()+18, "erm", 3))
break;
return Intrinsic::x86_xop_vpperm; // "__builtin_ia32_vpperm"
case 'r': // 4 strings to match.
if (memcmp(BuiltinName.data()+18, "ot", 2))
break;
switch (BuiltinName[20]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::x86_xop_vprotb; // "__builtin_ia32_vprotb"
case 'd': // 1 string to match.
return Intrinsic::x86_xop_vprotd; // "__builtin_ia32_vprotd"
case 'q': // 1 string to match.
return Intrinsic::x86_xop_vprotq; // "__builtin_ia32_vprotq"
case 'w': // 1 string to match.
return Intrinsic::x86_xop_vprotw; // "__builtin_ia32_vprotw"
}
break;
case 's': // 8 strings to match.
if (BuiltinName[18] != 'h')
break;
switch (BuiltinName[19]) {
default: break;
case 'a': // 4 strings to match.
switch (BuiltinName[20]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::x86_xop_vpshab; // "__builtin_ia32_
vpshab"
case 'd': // 1 string to match.
return Intrinsic::x86_xop_vpshad; // "__builtin_ia32_
vpshad"
case 'q': // 1 string to match.
return Intrinsic::x86_xop_vpshaq; // "__builtin_ia32_
vpshaq"
case 'w': // 1 string to match.
return Intrinsic::x86_xop_vpshaw; // "__builtin_ia32_
vpshaw"
}
break;
case 'l': // 4 strings to match.
switch (BuiltinName[20]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::x86_xop_vpshlb; // "__builtin_ia32_
vpshlb"
case 'd': // 1 string to match.
return Intrinsic::x86_xop_vpshld; // "__builtin_ia32_
vpshld"
case 'q': // 1 string to match.
return Intrinsic::x86_xop_vpshlq; // "__builtin_ia32_
vpshlq"
case 'w': // 1 string to match.
return Intrinsic::x86_xop_vpshlw; // "__builtin_ia32_
vpshlw"
}
break;
}
break;
}
break;
case 'o': // 1 string to match.
if (memcmp(BuiltinName.data()+11, "bject_size", 10))
break;
return Intrinsic::objectsize; // "__builtin_object_size"
case 'u': // 1 string to match.
if (memcmp(BuiltinName.data()+11, "nwind_init", 10))
break;
return Intrinsic::eh_unwind_init; // "__builtin_unwind_init"
}
break;
case 'n': // 3 strings to match.
if (memcmp(BuiltinName.data()+3, "vvm_", 4))
break;
switch (BuiltinName[7]) {
default: break;
case 'r': // 2 strings to match.
if (memcmp(BuiltinName.data()+8, "sqrt_approx_", 12))
break;
switch (BuiltinName[20]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::nvvm_rsqrt_approx_d; // "__nvvm_rsqrt_ap
prox_d"
case 'f': // 1 string to match.
return Intrinsic::nvvm_rsqrt_approx_f; // "__nvvm_rsqrt_ap
prox_f"
}
break;
case 's': // 1 string to match.
if (memcmp(BuiltinName.data()+8, "aturate_ftz_f", 13))
break;
return Intrinsic::nvvm_saturate_ftz_f; // "__nvvm_saturate_ftz_f"
}
break;
}
break;
case 22: // 17 strings to match.
if (memcmp(BuiltinName.data()+0, "__builtin_", 10))
break;
switch (BuiltinName[10]) {
default: break;
case 'i': // 12 strings to match.
if (memcmp(BuiltinName.data()+11, "a32_v", 5))
break;
switch (BuiltinName[16]) {
default: break;
case 'f': // 4 strings to match.
if (memcmp(BuiltinName.data()+17, "rcz", 3))
break;
switch (BuiltinName[20]) {
default: break;
case 'p': // 2 strings to match.
switch (BuiltinName[21]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::x86_xop_vfrcz_pd; // "__builtin_ia32_
vfrczpd"
case 's': // 1 string to match.
return Intrinsic::x86_xop_vfrcz_ps; // "__builtin_ia32_
vfrczps"
}
break;
case 's': // 2 strings to match.
switch (BuiltinName[21]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::x86_xop_vfrcz_sd; // "__builtin_ia32_
vfrczsd"
case 's': // 1 string to match.
return Intrinsic::x86_xop_vfrcz_ss; // "__builtin_ia32_
vfrczss"
}
break;
}
break;
case 'p': // 8 strings to match.
switch (BuiltinName[17]) {
default: break;
case 'c': // 4 strings to match.
if (memcmp(BuiltinName.data()+18, "omu", 3))
break;
switch (BuiltinName[21]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::x86_xop_vpcomub; // "__builtin_ia32_vpcomub"
case 'd': // 1 string to match.
return Intrinsic::x86_xop_vpcomud; // "__builtin_ia32_vpcomud"
case 'q': // 1 string to match.
return Intrinsic::x86_xop_vpcomuq; // "__builtin_ia32_vpcomuq"
case 'w': // 1 string to match.
return Intrinsic::x86_xop_vpcomuw; // "__builtin_ia32_vpcomuw"
}
break;
case 'r': // 4 strings to match.
if (memcmp(BuiltinName.data()+18, "ot", 2))
break;
switch (BuiltinName[20]) {
default: break;
case 'b': // 1 string to match.
if (BuiltinName[21] != 'i')
break;
return Intrinsic::x86_xop_vprotbi; // "__builtin_ia32_vprotbi"
case 'd': // 1 string to match.
if (BuiltinName[21] != 'i')
break;
return Intrinsic::x86_xop_vprotdi; // "__builtin_ia32_vprotdi"
case 'q': // 1 string to match.
if (BuiltinName[21] != 'i')
break;
return Intrinsic::x86_xop_vprotqi; // "__builtin_ia32_vprotqi"
case 'w': // 1 string to match.
if (BuiltinName[21] != 'i')
break;
return Intrinsic::x86_xop_vprotwi; // "__builtin_ia32_vprotwi"
}
break;
}
break;
}
break;
case 'p': // 5 strings to match.
if (memcmp(BuiltinName.data()+11, "tx_", 3))
break;
switch (BuiltinName[14]) {
default: break;
case 'b': // 1 string to match.
if (memcmp(BuiltinName.data()+15, "ar_sync", 7))
break;
return Intrinsic::ptx_bar_sync; // "__builtin_ptx_bar_sync"
case 'r': // 4 strings to match.
if (memcmp(BuiltinName.data()+15, "ead_pm", 6))
break;
switch (BuiltinName[21]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::ptx_read_pm0; // "__builtin_ptx_read_pm0"
case '1': // 1 string to match.
return Intrinsic::ptx_read_pm1; // "__builtin_ptx_read_pm1"
case '2': // 1 string to match.
return Intrinsic::ptx_read_pm2; // "__builtin_ptx_read_pm2"
case '3': // 1 string to match.
return Intrinsic::ptx_read_pm3; // "__builtin_ptx_read_pm3"
}
break;
}
break;
}
break;
case 23: // 20 strings to match.
if (memcmp(BuiltinName.data()+0, "__", 2))
break;
switch (BuiltinName[2]) {
default: break;
case 'b': // 14 strings to match.
if (memcmp(BuiltinName.data()+3, "uiltin_", 7))
break;
switch (BuiltinName[10]) {
default: break;
case 'i': // 12 strings to match.
if (memcmp(BuiltinName.data()+11, "a32_vp", 6))
break;
switch (BuiltinName[17]) {
default: break;
case 'h': // 9 strings to match.
switch (BuiltinName[18]) {
default: break;
case 'a': // 6 strings to match.
if (memcmp(BuiltinName.data()+19, "dd", 2))
break;
switch (BuiltinName[21]) {
default: break;
case 'b': // 3 strings to match.
switch (BuiltinName[22]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::x86_xop_vphaddbd; // "__builtin_ia32_
vphaddbd"
case 'q': // 1 string to match.
return Intrinsic::x86_xop_vphaddbq; // "__builtin_ia32_
vphaddbq"
case 'w': // 1 string to match.
return Intrinsic::x86_xop_vphaddbw; // "__builtin_ia32_
vphaddbw"
}
break;
case 'd': // 1 string to match.
if (BuiltinName[22] != 'q')
break;
return Intrinsic::x86_xop_vphadddq; // "__builtin_ia32_
vphadddq"
case 'w': // 2 strings to match.
switch (BuiltinName[22]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::x86_xop_vphaddwd; // "__builtin_ia32_
vphaddwd"
case 'q': // 1 string to match.
return Intrinsic::x86_xop_vphaddwq; // "__builtin_ia32_
vphaddwq"
}
break;
}
break;
case 's': // 3 strings to match.
if (memcmp(BuiltinName.data()+19, "ub", 2))
break;
switch (BuiltinName[21]) {
default: break;
case 'b': // 1 string to match.
if (BuiltinName[22] != 'w')
break;
return Intrinsic::x86_xop_vphsubbw; // "__builtin_ia32_
vphsubbw"
case 'd': // 1 string to match.
if (BuiltinName[22] != 'q')
break;
return Intrinsic::x86_xop_vphsubdq; // "__builtin_ia32_
vphsubdq"
case 'w': // 1 string to match.
if (BuiltinName[22] != 'd')
break;
return Intrinsic::x86_xop_vphsubwd; // "__builtin_ia32_
vphsubwd"
}
break;
}
break;
case 'm': // 3 strings to match.
if (memcmp(BuiltinName.data()+18, "acs", 3))
break;
switch (BuiltinName[21]) {
default: break;
case 'd': // 1 string to match.
if (BuiltinName[22] != 'd')
break;
return Intrinsic::x86_xop_vpmacsdd; // "__builtin_ia32_
vpmacsdd"
case 'w': // 2 strings to match.
switch (BuiltinName[22]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::x86_xop_vpmacswd; // "__builtin_ia32_
vpmacswd"
case 'w': // 1 string to match.
return Intrinsic::x86_xop_vpmacsww; // "__builtin_ia32_
vpmacsww"
}
break;
}
break;
}
break;
case 'p': // 1 string to match.
if (memcmp(BuiltinName.data()+11, "tx_read_smid", 12))
break;
return Intrinsic::ptx_read_smid; // "__builtin_ptx_read_smid
"
case 's': // 1 string to match.
if (memcmp(BuiltinName.data()+11, "tack_restore", 12))
break;
return Intrinsic::stackrestore; // "__builtin_stack_restore
"
}
break;
case 'n': // 6 strings to match.
if (memcmp(BuiltinName.data()+3, "vvm_", 4))
break;
switch (BuiltinName[7]) {
default: break;
case 'c': // 1 string to match.
if (memcmp(BuiltinName.data()+8, "os_approx_ftz_f", 15))
break;
return Intrinsic::nvvm_cos_approx_ftz_f; // "__nvvm_cos_appr
ox_ftz_f"
case 'd': // 1 string to match.
if (memcmp(BuiltinName.data()+8, "iv_approx_ftz_f", 15))
break;
return Intrinsic::nvvm_div_approx_ftz_f; // "__nvvm_div_appr
ox_ftz_f"
case 'e': // 1 string to match.
if (memcmp(BuiltinName.data()+8, "x2_approx_ftz_f", 15))
break;
return Intrinsic::nvvm_ex2_approx_ftz_f; // "__nvvm_ex2_appr
ox_ftz_f"
case 'l': // 1 string to match.
if (memcmp(BuiltinName.data()+8, "g2_approx_ftz_f", 15))
break;
return Intrinsic::nvvm_lg2_approx_ftz_f; // "__nvvm_lg2_appr
ox_ftz_f"
case 'r': // 1 string to match.
if (memcmp(BuiltinName.data()+8, "cp_approx_ftz_d", 15))
break;
return Intrinsic::nvvm_rcp_approx_ftz_d; // "__nvvm_rcp_appr
ox_ftz_d"
case 's': // 1 string to match.
if (memcmp(BuiltinName.data()+8, "in_approx_ftz_f", 15))
break;
return Intrinsic::nvvm_sin_approx_ftz_f; // "__nvvm_sin_appr
ox_ftz_f"
}
break;
}
break;
case 24: // 19 strings to match.
if (memcmp(BuiltinName.data()+0, "__", 2))
break;
switch (BuiltinName[2]) {
default: break;
case 'b': // 18 strings to match.
if (memcmp(BuiltinName.data()+3, "uiltin_", 7))
break;
switch (BuiltinName[10]) {
default: break;
case 'i': // 12 strings to match.
if (memcmp(BuiltinName.data()+11, "a32_vp", 6))
break;
switch (BuiltinName[17]) {
default: break;
case 'h': // 6 strings to match.
if (memcmp(BuiltinName.data()+18, "addu", 4))
break;
switch (BuiltinName[22]) {
default: break;
case 'b': // 3 strings to match.
switch (BuiltinName[23]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::x86_xop_vphaddubd; // "__builtin_ia32_
vphaddubd"
case 'q': // 1 string to match.
return Intrinsic::x86_xop_vphaddubq; // "__builtin_ia32_
vphaddubq"
case 'w': // 1 string to match.
return Intrinsic::x86_xop_vphaddubw; // "__builtin_ia32_
vphaddubw"
}
break;
case 'd': // 1 string to match.
if (BuiltinName[23] != 'q')
break;
return Intrinsic::x86_xop_vphaddudq; // "__builtin_ia32_
vphaddudq"
case 'w': // 2 strings to match.
switch (BuiltinName[23]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::x86_xop_vphadduwd; // "__builtin_ia32_
vphadduwd"
case 'q': // 1 string to match.
return Intrinsic::x86_xop_vphadduwq; // "__builtin_ia32_
vphadduwq"
}
break;
}
break;
case 'm': // 6 strings to match.
if (BuiltinName[18] != 'a')
break;
switch (BuiltinName[19]) {
default: break;
case 'c': // 5 strings to match.
if (BuiltinName[20] != 's')
break;
switch (BuiltinName[21]) {
default: break;
case 'd': // 2 strings to match.
if (BuiltinName[22] != 'q')
break;
switch (BuiltinName[23]) {
default: break;
case 'h': // 1 string to match.
return Intrinsic::x86_xop_vpmacsdqh; // "__builtin_ia32_
vpmacsdqh"
case 'l': // 1 string to match.
return Intrinsic::x86_xop_vpmacsdql; // "__builtin_ia32_
vpmacsdql"
}
break;
case 's': // 3 strings to match.
switch (BuiltinName[22]) {
default: break;
case 'd': // 1 string to match.
if (BuiltinName[23] != 'd')
break;
return Intrinsic::x86_xop_vpmacssdd; // "__builtin_ia32_
vpmacssdd"
case 'w': // 2 strings to match.
switch (BuiltinName[23]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::x86_xop_vpmacsswd; // "__builtin_ia32_
vpmacsswd"
case 'w': // 1 string to match.
return Intrinsic::x86_xop_vpmacssww; // "__builtin_ia32_
vpmacssww"
}
break;
}
break;
}
break;
case 'd': // 1 string to match.
if (memcmp(BuiltinName.data()+20, "cswd", 4))
break;
return Intrinsic::x86_xop_vpmadcswd; // "__builtin_ia32_
vpmadcswd"
}
break;
}
break;
case 'p': // 6 strings to match.
if (memcmp(BuiltinName.data()+11, "tx_read_", 8))
break;
switch (BuiltinName[19]) {
default: break;
case 'c': // 1 string to match.
if (memcmp(BuiltinName.data()+20, "lock", 4))
break;
return Intrinsic::ptx_read_clock; // "__builtin_ptx_read_cloc
k"
case 'n': // 1 string to match.
if (memcmp(BuiltinName.data()+20, "smid", 4))
break;
return Intrinsic::ptx_read_nsmid; // "__builtin_ptx_read_nsmi
d"
case 't': // 4 strings to match.
if (memcmp(BuiltinName.data()+20, "id_", 3))
break;
switch (BuiltinName[23]) {
default: break;
case 'w': // 1 string to match.
return Intrinsic::ptx_read_tid_w; // "__builtin_ptx_read_tid_
w"
case 'x': // 1 string to match.
return Intrinsic::ptx_read_tid_x; // "__builtin_ptx_read_tid_
x"
case 'y': // 1 string to match.
return Intrinsic::ptx_read_tid_y; // "__builtin_ptx_read_tid_
y"
case 'z': // 1 string to match.
return Intrinsic::ptx_read_tid_z; // "__builtin_ptx_read_tid_
z"
}
break;
}
break;
}
break;
case 'n': // 1 string to match.
if (memcmp(BuiltinName.data()+3, "vvm_sqrt_approx_ftz_f", 21))
break;
return Intrinsic::nvvm_sqrt_approx_ftz_f; // "__nvvm_sqrt_app
rox_ftz_f"
}
break;
case 25: // 17 strings to match.
if (memcmp(BuiltinName.data()+0, "__", 2))
break;
switch (BuiltinName[2]) {
default: break;
case 'b': // 16 strings to match.
if (memcmp(BuiltinName.data()+3, "uiltin_", 7))
break;
switch (BuiltinName[10]) {
default: break;
case 'i': // 9 strings to match.
switch (BuiltinName[11]) {
default: break;
case 'a': // 8 strings to match.
if (memcmp(BuiltinName.data()+12, "32_v", 4))
break;
switch (BuiltinName[16]) {
default: break;
case 'f': // 2 strings to match.
if (memcmp(BuiltinName.data()+17, "rczp", 4))
break;
switch (BuiltinName[21]) {
default: break;
case 'd': // 1 string to match.
if (memcmp(BuiltinName.data()+22, "256", 3))
break;
return Intrinsic::x86_xop_vfrcz_pd_256; // "__builtin_ia32_
vfrczpd256"
case 's': // 1 string to match.
if (memcmp(BuiltinName.data()+22, "256", 3))
break;
return Intrinsic::x86_xop_vfrcz_ps_256; // "__builtin_ia32_
vfrczps256"
}
break;
case 'p': // 6 strings to match.
switch (BuiltinName[17]) {
default: break;
case 'c': // 1 string to match.
if (memcmp(BuiltinName.data()+18, "mov_256", 7))
break;
return Intrinsic::x86_xop_vpcmov_256; // "__builtin_ia32_
vpcmov_256"
case 'e': // 2 strings to match.
if (memcmp(BuiltinName.data()+18, "rmil2p", 6))
break;
switch (BuiltinName[24]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::x86_xop_vpermil2pd; // "__builtin_ia32_
vpermil2pd"
case 's': // 1 string to match.
return Intrinsic::x86_xop_vpermil2ps; // "__builtin_ia32_
vpermil2ps"
}
break;
case 'm': // 3 strings to match.
if (BuiltinName[18] != 'a')
break;
switch (BuiltinName[19]) {
default: break;
case 'c': // 2 strings to match.
if (memcmp(BuiltinName.data()+20, "ssdq", 4))
break;
switch (BuiltinName[24]) {
default: break;
case 'h': // 1 string to match.
return Intrinsic::x86_xop_vpmacssdqh; // "__built
in_ia32_vpmacssdqh"
case 'l': // 1 string to match.
return Intrinsic::x86_xop_vpmacssdql; // "__built
in_ia32_vpmacssdql"
}
break;
case 'd': // 1 string to match.
if (memcmp(BuiltinName.data()+20, "csswd", 5))
break;
return Intrinsic::x86_xop_vpmadcsswd; // "__builtin_ia32_
vpmadcsswd"
}
break;
}
break;
}
break;
case 'n': // 1 string to match.
if (memcmp(BuiltinName.data()+12, "it_trampoline", 13))
break;
return Intrinsic::init_trampoline; // "__builtin_init_trampoli
ne"
}
break;
case 'p': // 7 strings to match.
if (memcmp(BuiltinName.data()+11, "tx_read_", 8))
break;
switch (BuiltinName[19]) {
default: break;
case 'g': // 1 string to match.
if (memcmp(BuiltinName.data()+20, "ridid", 5))
break;
return Intrinsic::ptx_read_gridid; // "__builtin_ptx_read_grid
id"
case 'l': // 1 string to match.
if (memcmp(BuiltinName.data()+20, "aneid", 5))
break;
return Intrinsic::ptx_read_laneid; // "__builtin_ptx_read_lane
id"
case 'n': // 4 strings to match.
if (memcmp(BuiltinName.data()+20, "tid_", 4))
break;
switch (BuiltinName[24]) {
default: break;
case 'w': // 1 string to match.
return Intrinsic::ptx_read_ntid_w; // "__builtin_ptx_read_ntid
_w"
case 'x': // 1 string to match.
return Intrinsic::ptx_read_ntid_x; // "__builtin_ptx_read_ntid
_x"
case 'y': // 1 string to match.
return Intrinsic::ptx_read_ntid_y; // "__builtin_ptx_read_ntid
_y"
case 'z': // 1 string to match.
return Intrinsic::ptx_read_ntid_z; // "__builtin_ptx_read_ntid
_z"
}
break;
case 'w': // 1 string to match.
if (memcmp(BuiltinName.data()+20, "arpid", 5))
break;
return Intrinsic::ptx_read_warpid; // "__builtin_ptx_read_warp
id"
}
break;
}
break;
case 'n': // 1 string to match.
if (memcmp(BuiltinName.data()+3, "vvm_rsqrt_approx_ftz_f", 22))
break;
return Intrinsic::nvvm_rsqrt_approx_ftz_f; // "__nvvm_rsqrt_ap
prox_ftz_f"
}
break;
case 26: // 9 strings to match.
if (memcmp(BuiltinName.data()+0, "__", 2))
break;
switch (BuiltinName[2]) {
default: break;
case 'b': // 6 strings to match.
if (memcmp(BuiltinName.data()+3, "uiltin_ptx_read_", 16))
break;
switch (BuiltinName[19]) {
default: break;
case 'c': // 5 strings to match.
switch (BuiltinName[20]) {
default: break;
case 'l': // 1 string to match.
if (memcmp(BuiltinName.data()+21, "ock64", 5))
break;
return Intrinsic::ptx_read_clock64; // "__builtin_ptx_read_cloc
k64"
case 't': // 4 strings to match.
if (memcmp(BuiltinName.data()+21, "aid_", 4))
break;
switch (BuiltinName[25]) {
default: break;
case 'w': // 1 string to match.
return Intrinsic::ptx_read_ctaid_w; // "__builtin_ptx_r
ead_ctaid_w"
case 'x': // 1 string to match.
return Intrinsic::ptx_read_ctaid_x; // "__builtin_ptx_r
ead_ctaid_x"
case 'y': // 1 string to match.
return Intrinsic::ptx_read_ctaid_y; // "__builtin_ptx_r
ead_ctaid_y"
case 'z': // 1 string to match.
return Intrinsic::ptx_read_ctaid_z; // "__builtin_ptx_r
ead_ctaid_z"
}
break;
}
break;
case 'n': // 1 string to match.
if (memcmp(BuiltinName.data()+20, "warpid", 6))
break;
return Intrinsic::ptx_read_nwarpid; // "__builtin_ptx_read_nwar
pid"
}
break;
case 'n': // 3 strings to match.
if (memcmp(BuiltinName.data()+3, "vvm_read_ptx_sreg_tid_", 22))
break;
switch (BuiltinName[25]) {
default: break;
case 'x': // 1 string to match.
return Intrinsic::nvvm_read_ptx_sreg_tid_x; // "__nvvm_read_ptx
_sreg_tid_x"
case 'y': // 1 string to match.
return Intrinsic::nvvm_read_ptx_sreg_tid_y; // "__nvvm_read_ptx
_sreg_tid_y"
case 'z': // 1 string to match.
return Intrinsic::nvvm_read_ptx_sreg_tid_z; // "__nvvm_read_ptx
_sreg_tid_z"
}
break;
}
break;
case 27: // 8 strings to match.
if (memcmp(BuiltinName.data()+0, "__", 2))
break;
switch (BuiltinName[2]) {
default: break;
case 'b': // 5 strings to match.
if (memcmp(BuiltinName.data()+3, "uiltin_", 7))
break;
switch (BuiltinName[10]) {
default: break;
case 'a': // 1 string to match.
if (memcmp(BuiltinName.data()+11, "djust_trampoline", 16))
break;
return Intrinsic::adjust_trampoline; // "__builtin_adjust_trampo
line"
case 'p': // 4 strings to match.
if (memcmp(BuiltinName.data()+11, "tx_read_nctaid_", 15))
break;
switch (BuiltinName[26]) {
default: break;
case 'w': // 1 string to match.
return Intrinsic::ptx_read_nctaid_w; // "__builtin_ptx_read_ncta
id_w"
case 'x': // 1 string to match.
return Intrinsic::ptx_read_nctaid_x; // "__builtin_ptx_read_ncta
id_x"
case 'y': // 1 string to match.
return Intrinsic::ptx_read_nctaid_y; // "__builtin_ptx_read_ncta
id_y"
case 'z': // 1 string to match.
return Intrinsic::ptx_read_nctaid_z; // "__builtin_ptx_read_ncta
id_z"
}
break;
}
break;
case 'n': // 3 strings to match.
if (memcmp(BuiltinName.data()+3, "vvm_read_ptx_sreg_ntid_", 23))
break;
switch (BuiltinName[26]) {
default: break;
case 'x': // 1 string to match.
return Intrinsic::nvvm_read_ptx_sreg_ntid_x; // "__nvvm_read_ptx
_sreg_ntid_x"
case 'y': // 1 string to match.
return Intrinsic::nvvm_read_ptx_sreg_ntid_y; // "__nvvm_read_ptx
_sreg_ntid_y"
case 'z': // 1 string to match.
return Intrinsic::nvvm_read_ptx_sreg_ntid_z; // "__nvvm_read_ptx
_sreg_ntid_z"
}
break;
}
break;
case 28: // 5 strings to match.
if (memcmp(BuiltinName.data()+0, "__", 2))
break;
switch (BuiltinName[2]) {
default: break;
case 'b': // 2 strings to match.
if (memcmp(BuiltinName.data()+3, "uiltin_ia32_vpermil2p", 21))
break;
switch (BuiltinName[24]) {
default: break;
case 'd': // 1 string to match.
if (memcmp(BuiltinName.data()+25, "256", 3))
break;
return Intrinsic::x86_xop_vpermil2pd_256; // "__builtin_ia32_
vpermil2pd256"
case 's': // 1 string to match.
if (memcmp(BuiltinName.data()+25, "256", 3))
break;
return Intrinsic::x86_xop_vpermil2ps_256; // "__builtin_ia32_
vpermil2ps256"
}
break;
case 'n': // 3 strings to match.
if (memcmp(BuiltinName.data()+3, "vvm_read_ptx_sreg_ctaid_", 24))
break;
switch (BuiltinName[27]) {
default: break;
case 'x': // 1 string to match.
return Intrinsic::nvvm_read_ptx_sreg_ctaid_x; // "__nvvm_read_ptx
_sreg_ctaid_x"
case 'y': // 1 string to match.
return Intrinsic::nvvm_read_ptx_sreg_ctaid_y; // "__nvvm_read_ptx
_sreg_ctaid_y"
case 'z': // 1 string to match.
return Intrinsic::nvvm_read_ptx_sreg_ctaid_z; // "__nvvm_read_ptx
_sreg_ctaid_z"
}
break;
}
break;
case 29: // 4 strings to match.
if (memcmp(BuiltinName.data()+0, "__nvvm_read_ptx_sreg_", 21))
break;
switch (BuiltinName[21]) {
default: break;
case 'n': // 3 strings to match.
if (memcmp(BuiltinName.data()+22, "ctaid_", 6))
break;
switch (BuiltinName[28]) {
default: break;
case 'x': // 1 string to match.
return Intrinsic::nvvm_read_ptx_sreg_nctaid_x; // "__nvvm_read_ptx
_sreg_nctaid_x"
case 'y': // 1 string to match.
return Intrinsic::nvvm_read_ptx_sreg_nctaid_y; // "__nvvm_read_ptx
_sreg_nctaid_y"
case 'z': // 1 string to match.
return Intrinsic::nvvm_read_ptx_sreg_nctaid_z; // "__nvvm_read_ptx
_sreg_nctaid_z"
}
break;
case 'w': // 1 string to match.
if (memcmp(BuiltinName.data()+22, "arpsize", 7))
break;
return Intrinsic::nvvm_read_ptx_sreg_warpsize; // "__nvvm_read_ptx
_sreg_warpsize"
}
break;
case 30: // 5 strings to match.
if (memcmp(BuiltinName.data()+0, "__builtin_ptx_read_lanemask_", 28))
break;
switch (BuiltinName[28]) {
default: break;
case 'e': // 1 string to match.
if (BuiltinName[29] != 'q')
break;
return Intrinsic::ptx_read_lanemask_eq; // "__builtin_ptx_read_lane
mask_eq"
case 'g': // 2 strings to match.
switch (BuiltinName[29]) {
default: break;
case 'e': // 1 string to match.
return Intrinsic::ptx_read_lanemask_ge; // "__builtin_ptx_r
ead_lanemask_ge"
case 't': // 1 string to match.
return Intrinsic::ptx_read_lanemask_gt; // "__builtin_ptx_r
ead_lanemask_gt"
}
break;
case 'l': // 2 strings to match.
switch (BuiltinName[29]) {
default: break;
case 'e': // 1 string to match.
return Intrinsic::ptx_read_lanemask_le; // "__builtin_ptx_r
ead_lanemask_le"
case 't': // 1 string to match.
return Intrinsic::ptx_read_lanemask_lt; // "__builtin_ptx_r
ead_lanemask_lt"
}
break;
}
break;
}
}
if (TargetPrefix == "arm") {
switch (BuiltinName.size()) {
default: break;
case 17: // 3 strings to match.
if (memcmp(BuiltinName.data()+0, "__builtin_arm_", 14))
break;
switch (BuiltinName[14]) {
default: break;
case 'c': // 1 string to match.
if (memcmp(BuiltinName.data()+15, "dp", 2))
break;
return Intrinsic::arm_cdp; // "__builtin_arm_cdp"
case 'm': // 2 strings to match.
switch (BuiltinName[15]) {
default: break;
case 'c': // 1 string to match.
if (BuiltinName[16] != 'r')
break;
return Intrinsic::arm_mcr; // "__builtin_arm_mcr"
case 'r': // 1 string to match.
if (BuiltinName[16] != 'c')
break;
return Intrinsic::arm_mrc; // "__builtin_arm_mrc"
}
break;
}
break;
case 18: // 8 strings to match.
if (memcmp(BuiltinName.data()+0, "__builtin_arm_", 14))
break;
switch (BuiltinName[14]) {
default: break;
case 'c': // 1 string to match.
if (memcmp(BuiltinName.data()+15, "dp2", 3))
break;
return Intrinsic::arm_cdp2; // "__builtin_arm_cdp2"
case 'm': // 3 strings to match.
switch (BuiltinName[15]) {
default: break;
case 'c': // 2 strings to match.
if (BuiltinName[16] != 'r')
break;
switch (BuiltinName[17]) {
default: break;
case '2': // 1 string to match.
return Intrinsic::arm_mcr2; // "__builtin_arm_mcr2"
case 'r': // 1 string to match.
return Intrinsic::arm_mcrr; // "__builtin_arm_mcrr"
}
break;
case 'r': // 1 string to match.
if (memcmp(BuiltinName.data()+16, "c2", 2))
break;
return Intrinsic::arm_mrc2; // "__builtin_arm_mrc2"
}
break;
case 'q': // 2 strings to match.
switch (BuiltinName[15]) {
default: break;
case 'a': // 1 string to match.
if (memcmp(BuiltinName.data()+16, "dd", 2))
break;
return Intrinsic::arm_qadd; // "__builtin_arm_qadd"
case 's': // 1 string to match.
if (memcmp(BuiltinName.data()+16, "ub", 2))
break;
return Intrinsic::arm_qsub; // "__builtin_arm_qsub"
}
break;
case 's': // 1 string to match.
if (memcmp(BuiltinName.data()+15, "sat", 3))
break;
return Intrinsic::arm_ssat; // "__builtin_arm_ssat"
case 'u': // 1 string to match.
if (memcmp(BuiltinName.data()+15, "sat", 3))
break;
return Intrinsic::arm_usat; // "__builtin_arm_usat"
}
break;
case 19: // 1 string to match.
if (memcmp(BuiltinName.data()+0, "__builtin_arm_mcrr2", 19))
break;
return Intrinsic::arm_mcrr2; // "__builtin_arm_mcrr2"
case 23: // 2 strings to match.
if (memcmp(BuiltinName.data()+0, "__builtin_arm_", 14))
break;
switch (BuiltinName[14]) {
default: break;
case 'g': // 1 string to match.
if (memcmp(BuiltinName.data()+15, "et_fpscr", 8))
break;
return Intrinsic::arm_get_fpscr; // "__builtin_arm_get_fpscr"
case 's': // 1 string to match.
if (memcmp(BuiltinName.data()+15, "et_fpscr", 8))
break;
return Intrinsic::arm_set_fpscr; // "__builtin_arm_set_fpscr"
}
break;
case 24: // 1 string to match.
if (memcmp(BuiltinName.data()+0, "__builtin_thread_pointer", 24))
break;
return Intrinsic::arm_thread_pointer; // "__builtin_thread_pointe
r"
}
}
if (TargetPrefix == "hexagon") {
switch (BuiltinName.size()) {
default: break;
case 18: // 1 string to match.
if (memcmp(BuiltinName.data()+0, "__builtin_circ_ldd", 18))
break;
return Intrinsic::hexagon_circ_ldd; // "__builtin_circ_ldd"
case 23: // 2 strings to match.
if (memcmp(BuiltinName.data()+0, "__builtin_HEXAGON_", 18))
break;
switch (BuiltinName[18]) {
default: break;
case 'A': // 1 string to match.
if (memcmp(BuiltinName.data()+19, "2_or", 4))
break;
return Intrinsic::hexagon_A2_or; // "__builtin_HEXAGON_A2_or"
case 'C': // 1 string to match.
if (memcmp(BuiltinName.data()+19, "2_or", 4))
break;
return Intrinsic::hexagon_C2_or; // "__builtin_HEXAGON_C2_or"
}
break;
case 24: // 23 strings to match.
if (memcmp(BuiltinName.data()+0, "__builtin_HEXAGON_", 18))
break;
switch (BuiltinName[18]) {
default: break;
case 'A': // 13 strings to match.
switch (BuiltinName[19]) {
default: break;
case '2': // 12 strings to match.
if (BuiltinName[20] != '_')
break;
switch (BuiltinName[21]) {
default: break;
case 'a': // 3 strings to match.
switch (BuiltinName[22]) {
default: break;
case 'b': // 1 string to match.
if (BuiltinName[23] != 's')
break;
return Intrinsic::hexagon_A2_abs; // "__builtin_HEXAGON_A2_ab
s"
case 'd': // 1 string to match.
if (BuiltinName[23] != 'd')
break;
return Intrinsic::hexagon_A2_add; // "__builtin_HEXAGON_A2_ad
d"
case 'n': // 1 string to match.
if (BuiltinName[23] != 'd')
break;
return Intrinsic::hexagon_A2_and; // "__builtin_HEXAGON_A2_an
d"
}
break;
case 'm': // 2 strings to match.
switch (BuiltinName[22]) {
default: break;
case 'a': // 1 string to match.
if (BuiltinName[23] != 'x')
break;
return Intrinsic::hexagon_A2_max; // "__builtin_HEXAGON_A2_ma
x"
case 'i': // 1 string to match.
if (BuiltinName[23] != 'n')
break;
return Intrinsic::hexagon_A2_min; // "__builtin_HEXAGON_A2_mi
n"
}
break;
case 'n': // 2 strings to match.
switch (BuiltinName[22]) {
default: break;
case 'e': // 1 string to match.
if (BuiltinName[23] != 'g')
break;
return Intrinsic::hexagon_A2_neg; // "__builtin_HEXAGON_A2_ne
g"
case 'o': // 1 string to match.
if (BuiltinName[23] != 't')
break;
return Intrinsic::hexagon_A2_not; // "__builtin_HEXAGON_A2_no
t"
}
break;
case 'o': // 1 string to match.
if (memcmp(BuiltinName.data()+22, "rp", 2))
break;
return Intrinsic::hexagon_A2_orp; // "__builtin_HEXAGON_A2_or
p"
case 's': // 2 strings to match.
switch (BuiltinName[22]) {
default: break;
case 'a': // 1 string to match.
if (BuiltinName[23] != 't')
break;
return Intrinsic::hexagon_A2_sat; // "__builtin_HEXAGON_A2_sa
t"
case 'u': // 1 string to match.
if (BuiltinName[23] != 'b')
break;
return Intrinsic::hexagon_A2_sub; // "__builtin_HEXAGON_A2_su
b"
}
break;
case 't': // 1 string to match.
if (memcmp(BuiltinName.data()+22, "fr", 2))
break;
return Intrinsic::hexagon_A2_tfr; // "__builtin_HEXAGON_A2_tf
r"
case 'x': // 1 string to match.
if (memcmp(BuiltinName.data()+22, "or", 2))
break;
return Intrinsic::hexagon_A2_xor; // "__builtin_HEXAGON_A2_xo
r"
}
break;
case '4': // 1 string to match.
if (memcmp(BuiltinName.data()+20, "_orn", 4))
break;
return Intrinsic::hexagon_A4_orn; // "__builtin_HEXAGON_A4_or
n"
}
break;
case 'C': // 5 strings to match.
if (memcmp(BuiltinName.data()+19, "2_", 2))
break;
switch (BuiltinName[21]) {
default: break;
case 'a': // 1 string to match.
if (memcmp(BuiltinName.data()+22, "nd", 2))
break;
return Intrinsic::hexagon_C2_and; // "__builtin_HEXAGON_C2_an
d"
case 'm': // 1 string to match.
if (memcmp(BuiltinName.data()+22, "ux", 2))
break;
return Intrinsic::hexagon_C2_mux; // "__builtin_HEXAGON_C2_mu
x"
case 'n': // 1 string to match.
if (memcmp(BuiltinName.data()+22, "ot", 2))
break;
return Intrinsic::hexagon_C2_not; // "__builtin_HEXAGON_C2_no
t"
case 'o': // 1 string to match.
if (memcmp(BuiltinName.data()+22, "rn", 2))
break;
return Intrinsic::hexagon_C2_orn; // "__builtin_HEXAGON_C2_or
n"
case 'x': // 1 string to match.
if (memcmp(BuiltinName.data()+22, "or", 2))
break;
return Intrinsic::hexagon_C2_xor; // "__builtin_HEXAGON_C2_xo
r"
}
break;
case 'S': // 5 strings to match.
if (memcmp(BuiltinName.data()+19, "2_c", 3))
break;
switch (BuiltinName[22]) {
default: break;
case 'l': // 3 strings to match.
switch (BuiltinName[23]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_S2_cl0; // "__builtin_HEXAGON_S2_cl
0"
case '1': // 1 string to match.
return Intrinsic::hexagon_S2_cl1; // "__builtin_HEXAGON_S2_cl
1"
case 'b': // 1 string to match.
return Intrinsic::hexagon_S2_clb; // "__builtin_HEXAGON_S2_cl
b"
}
break;
case 't': // 2 strings to match.
switch (BuiltinName[23]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_S2_ct0; // "__builtin_HEXAGON_S2_ct
0"
case '1': // 1 string to match.
return Intrinsic::hexagon_S2_ct1; // "__builtin_HEXAGON_S2_ct
1"
}
break;
}
break;
}
break;
case 25: // 42 strings to match.
if (memcmp(BuiltinName.data()+0, "__builtin_HEXAGON_", 18))
break;
switch (BuiltinName[18]) {
default: break;
case 'A': // 26 strings to match.
switch (BuiltinName[19]) {
default: break;
case '2': // 24 strings to match.
if (BuiltinName[20] != '_')
break;
switch (BuiltinName[21]) {
default: break;
case 'a': // 6 strings to match.
switch (BuiltinName[22]) {
default: break;
case 'b': // 1 string to match.
if (memcmp(BuiltinName.data()+23, "sp", 2))
break;
return Intrinsic::hexagon_A2_absp; // "__builtin_HEXAGON_A2_ab
sp"
case 'd': // 2 strings to match.
if (BuiltinName[23] != 'd')
break;
switch (BuiltinName[24]) {
default: break;
case 'i': // 1 string to match.
return Intrinsic::hexagon_A2_addi; // "__builtin_HEXAG
ON_A2_addi"
case 'p': // 1 string to match.
return Intrinsic::hexagon_A2_addp; // "__builtin_HEXAG
ON_A2_addp"
}
break;
case 'n': // 1 string to match.
if (memcmp(BuiltinName.data()+23, "dp", 2))
break;
return Intrinsic::hexagon_A2_andp; // "__builtin_HEXAGON_A2_an
dp"
case 's': // 2 strings to match.
switch (BuiltinName[23]) {
default: break;
case 'l': // 1 string to match.
if (BuiltinName[24] != 'h')
break;
return Intrinsic::hexagon_A2_aslh; // "__builtin_HEXAG
ON_A2_aslh"
case 'r': // 1 string to match.
if (BuiltinName[24] != 'h')
break;
return Intrinsic::hexagon_A2_asrh; // "__builtin_HEXAG
ON_A2_asrh"
}
break;
}
break;
case 'm': // 4 strings to match.
switch (BuiltinName[22]) {
default: break;
case 'a': // 2 strings to match.
if (BuiltinName[23] != 'x')
break;
switch (BuiltinName[24]) {
default: break;
case 'p': // 1 string to match.
return Intrinsic::hexagon_A2_maxp; // "__builtin_HEXAG
ON_A2_maxp"
case 'u': // 1 string to match.
return Intrinsic::hexagon_A2_maxu; // "__builtin_HEXAG
ON_A2_maxu"
}
break;
case 'i': // 2 strings to match.
if (BuiltinName[23] != 'n')
break;
switch (BuiltinName[24]) {
default: break;
case 'p': // 1 string to match.
return Intrinsic::hexagon_A2_minp; // "__builtin_HEXAG
ON_A2_minp"
case 'u': // 1 string to match.
return Intrinsic::hexagon_A2_minu; // "__builtin_HEXAG
ON_A2_minu"
}
break;
}
break;
case 'n': // 2 strings to match.
switch (BuiltinName[22]) {
default: break;
case 'e': // 1 string to match.
if (memcmp(BuiltinName.data()+23, "gp", 2))
break;
return Intrinsic::hexagon_A2_negp; // "__builtin_HEXAGON_A2_ne
gp"
case 'o': // 1 string to match.
if (memcmp(BuiltinName.data()+23, "tp", 2))
break;
return Intrinsic::hexagon_A2_notp; // "__builtin_HEXAGON_A2_no
tp"
}
break;
case 'o': // 1 string to match.
if (memcmp(BuiltinName.data()+22, "rir", 3))
break;
return Intrinsic::hexagon_A2_orir; // "__builtin_HEXAGON_A2_or
ir"
case 's': // 7 strings to match.
switch (BuiltinName[22]) {
default: break;
case 'a': // 2 strings to match.
if (BuiltinName[23] != 't')
break;
switch (BuiltinName[24]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::hexagon_A2_satb; // "__builtin_HEXAG
ON_A2_satb"
case 'h': // 1 string to match.
return Intrinsic::hexagon_A2_sath; // "__builtin_HEXAG
ON_A2_sath"
}
break;
case 'u': // 1 string to match.
if (memcmp(BuiltinName.data()+23, "bp", 2))
break;
return Intrinsic::hexagon_A2_subp; // "__builtin_HEXAGON_A2_su
bp"
case 'w': // 1 string to match.
if (memcmp(BuiltinName.data()+23, "iz", 2))
break;
return Intrinsic::hexagon_A2_swiz; // "__builtin_HEXAGON_A2_sw
iz"
case 'x': // 3 strings to match.
if (BuiltinName[23] != 't')
break;
switch (BuiltinName[24]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::hexagon_A2_sxtb; // "__builtin_HEXAG
ON_A2_sxtb"
case 'h': // 1 string to match.
return Intrinsic::hexagon_A2_sxth; // "__builtin_HEXAG
ON_A2_sxth"
case 'w': // 1 string to match.
return Intrinsic::hexagon_A2_sxtw; // "__builtin_HEXAG
ON_A2_sxtw"
}
break;
}
break;
case 't': // 1 string to match.
if (memcmp(BuiltinName.data()+22, "frp", 3))
break;
return Intrinsic::hexagon_A2_tfrp; // "__builtin_HEXAGON_A2_tf
rp"
case 'x': // 1 string to match.
if (memcmp(BuiltinName.data()+22, "orp", 3))
break;
return Intrinsic::hexagon_A2_xorp; // "__builtin_HEXAGON_A2_xo
rp"
case 'z': // 2 strings to match.
if (memcmp(BuiltinName.data()+22, "xt", 2))
break;
switch (BuiltinName[24]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::hexagon_A2_zxtb; // "__builtin_HEXAGON_A2_zx
tb"
case 'h': // 1 string to match.
return Intrinsic::hexagon_A2_zxth; // "__builtin_HEXAGON_A2_zx
th"
}
break;
}
break;
case '4': // 2 strings to match.
if (BuiltinName[20] != '_')
break;
switch (BuiltinName[21]) {
default: break;
case 'a': // 1 string to match.
if (memcmp(BuiltinName.data()+22, "ndn", 3))
break;
return Intrinsic::hexagon_A4_andn; // "__builtin_HEXAGON_A4_an
dn"
case 'o': // 1 string to match.
if (memcmp(BuiltinName.data()+22, "rnp", 3))
break;
return Intrinsic::hexagon_A4_ornp; // "__builtin_HEXAGON_A4_or
np"
}
break;
}
break;
case 'C': // 5 strings to match.
if (memcmp(BuiltinName.data()+19, "2_", 2))
break;
switch (BuiltinName[21]) {
default: break;
case 'a': // 3 strings to match.
switch (BuiltinName[22]) {
default: break;
case 'l': // 1 string to match.
if (memcmp(BuiltinName.data()+23, "l8", 2))
break;
return Intrinsic::hexagon_C2_all8; // "__builtin_HEXAGON_C2_al
l8"
case 'n': // 2 strings to match.
switch (BuiltinName[23]) {
default: break;
case 'd': // 1 string to match.
if (BuiltinName[24] != 'n')
break;
return Intrinsic::hexagon_C2_andn; // "__builtin_HEXAGON_C2_an
dn"
case 'y': // 1 string to match.
if (BuiltinName[24] != '8')
break;
return Intrinsic::hexagon_C2_any8; // "__builtin_HEXAGON_C2_an
y8"
}
break;
}
break;
case 'm': // 1 string to match.
if (memcmp(BuiltinName.data()+22, "ask", 3))
break;
return Intrinsic::hexagon_C2_mask; // "__builtin_HEXAGON_C2_ma
sk"
case 'v': // 1 string to match.
if (memcmp(BuiltinName.data()+22, "mux", 3))
break;
return Intrinsic::hexagon_C2_vmux; // "__builtin_HEXAGON_C2_vm
ux"
}
break;
case 'M': // 3 strings to match.
if (memcmp(BuiltinName.data()+19, "2_", 2))
break;
switch (BuiltinName[21]) {
default: break;
case 'a': // 1 string to match.
if (memcmp(BuiltinName.data()+22, "cci", 3))
break;
return Intrinsic::hexagon_M2_acci; // "__builtin_HEXAGON_M2_ac
ci"
case 'm': // 2 strings to match.
switch (BuiltinName[22]) {
default: break;
case 'a': // 1 string to match.
if (memcmp(BuiltinName.data()+23, "ci", 2))
break;
return Intrinsic::hexagon_M2_maci; // "__builtin_HEXAGON_M2_ma
ci"
case 'p': // 1 string to match.
if (memcmp(BuiltinName.data()+23, "yi", 2))
break;
return Intrinsic::hexagon_M2_mpyi; // "__builtin_HEXAGON_M2_mp
yi"
}
break;
}
break;
case 'S': // 8 strings to match.
switch (BuiltinName[19]) {
default: break;
case '2': // 7 strings to match.
if (BuiltinName[20] != '_')
break;
switch (BuiltinName[21]) {
default: break;
case 'b': // 1 string to match.
if (memcmp(BuiltinName.data()+22, "rev", 3))
break;
return Intrinsic::hexagon_S2_brev; // "__builtin_HEXAGON_S2_br
ev"
case 'c': // 5 strings to match.
switch (BuiltinName[22]) {
default: break;
case 'l': // 3 strings to match.
switch (BuiltinName[23]) {
default: break;
case '0': // 1 string to match.
if (BuiltinName[24] != 'p')
break;
return Intrinsic::hexagon_S2_cl0p; // "__builtin_HEXAG
ON_S2_cl0p"
case '1': // 1 string to match.
if (BuiltinName[24] != 'p')
break;
return Intrinsic::hexagon_S2_cl1p; // "__builtin_HEXAG
ON_S2_cl1p"
case 'b': // 1 string to match.
if (BuiltinName[24] != 'p')
break;
return Intrinsic::hexagon_S2_clbp; // "__builtin_HEXAG
ON_S2_clbp"
}
break;
case 't': // 2 strings to match.
switch (BuiltinName[23]) {
default: break;
case '0': // 1 string to match.
if (BuiltinName[24] != 'p')
break;
return Intrinsic::hexagon_S2_ct0p; // "__builtin_HEXAG
ON_S2_ct0p"
case '1': // 1 string to match.
if (BuiltinName[24] != 'p')
break;
return Intrinsic::hexagon_S2_ct1p; // "__builtin_HEXAG
ON_S2_ct1p"
}
break;
}
break;
case 'l': // 1 string to match.
if (memcmp(BuiltinName.data()+22, "fsp", 3))
break;
return Intrinsic::hexagon_S2_lfsp; // "__builtin_HEXAGON_S2_lf
sp"
}
break;
case '4': // 1 string to match.
if (memcmp(BuiltinName.data()+20, "_lsli", 5))
break;
return Intrinsic::hexagon_S4_lsli; // "__builtin_HEXAGON_S4_ls
li"
}
break;
}
break;
case 26: // 58 strings to match.
if (memcmp(BuiltinName.data()+0, "__builtin_", 10))
break;
switch (BuiltinName[10]) {
default: break;
case 'H': // 57 strings to match.
if (memcmp(BuiltinName.data()+11, "EXAGON_", 7))
break;
switch (BuiltinName[18]) {
default: break;
case 'A': // 27 strings to match.
switch (BuiltinName[19]) {
default: break;
case '2': // 26 strings to match.
if (BuiltinName[20] != '_')
break;
switch (BuiltinName[21]) {
default: break;
case 'a': // 2 strings to match.
switch (BuiltinName[22]) {
default: break;
case 'd': // 1 string to match.
if (memcmp(BuiltinName.data()+23, "dsp", 3))
break;
return Intrinsic::hexagon_A2_addsp; // "__builtin_HEXAG
ON_A2_addsp"
case 'n': // 1 string to match.
if (memcmp(BuiltinName.data()+23, "dir", 3))
break;
return Intrinsic::hexagon_A2_andir; // "__builtin_HEXAG
ON_A2_andir"
}
break;
case 'm': // 2 strings to match.
switch (BuiltinName[22]) {
default: break;
case 'a': // 1 string to match.
if (memcmp(BuiltinName.data()+23, "xup", 3))
break;
return Intrinsic::hexagon_A2_maxup; // "__builtin_HEXAG
ON_A2_maxup"
case 'i': // 1 string to match.
if (memcmp(BuiltinName.data()+23, "nup", 3))
break;
return Intrinsic::hexagon_A2_minup; // "__builtin_HEXAG
ON_A2_minup"
}
break;
case 's': // 3 strings to match.
switch (BuiltinName[22]) {
default: break;
case 'a': // 2 strings to match.
if (memcmp(BuiltinName.data()+23, "tu", 2))
break;
switch (BuiltinName[25]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::hexagon_A2_satub; // "__builtin_HEXAG
ON_A2_satub"
case 'h': // 1 string to match.
return Intrinsic::hexagon_A2_satuh; // "__builtin_HEXAG
ON_A2_satuh"
}
break;
case 'u': // 1 string to match.
if (memcmp(BuiltinName.data()+23, "bri", 3))
break;
return Intrinsic::hexagon_A2_subri; // "__builtin_HEXAG
ON_A2_subri"
}
break;
case 't': // 4 strings to match.
if (memcmp(BuiltinName.data()+22, "fr", 2))
break;
switch (BuiltinName[24]) {
default: break;
case 'i': // 2 strings to match.
switch (BuiltinName[25]) {
default: break;
case 'h': // 1 string to match.
return Intrinsic::hexagon_A2_tfrih; // "__builtin_HEXAG
ON_A2_tfrih"
case 'l': // 1 string to match.
return Intrinsic::hexagon_A2_tfril; // "__builtin_HEXAG
ON_A2_tfril"
}
break;
case 'p': // 1 string to match.
if (BuiltinName[25] != 'i')
break;
return Intrinsic::hexagon_A2_tfrpi; // "__builtin_HEXAG
ON_A2_tfrpi"
case 's': // 1 string to match.
if (BuiltinName[25] != 'i')
break;
return Intrinsic::hexagon_A2_tfrsi; // "__builtin_HEXAG
ON_A2_tfrsi"
}
break;
case 'v': // 15 strings to match.
switch (BuiltinName[22]) {
default: break;
case 'a': // 6 strings to match.
switch (BuiltinName[23]) {
default: break;
case 'b': // 2 strings to match.
if (BuiltinName[24] != 's')
break;
switch (BuiltinName[25]) {
default: break;
case 'h': // 1 string to match.
return Intrinsic::hexagon_A2_vabsh; // "__builtin_HEXAG
ON_A2_vabsh"
case 'w': // 1 string to match.
return Intrinsic::hexagon_A2_vabsw; // "__builtin_HEXAG
ON_A2_vabsw"
}
break;
case 'd': // 2 strings to match.
if (BuiltinName[24] != 'd')
break;
switch (BuiltinName[25]) {
default: break;
case 'h': // 1 string to match.
return Intrinsic::hexagon_A2_vaddh; // "__builtin_HEXAG
ON_A2_vaddh"
case 'w': // 1 string to match.
return Intrinsic::hexagon_A2_vaddw; // "__builtin_HEXAG
ON_A2_vaddw"
}
break;
case 'v': // 2 strings to match.
if (BuiltinName[24] != 'g')
break;
switch (BuiltinName[25]) {
default: break;
case 'h': // 1 string to match.
return Intrinsic::hexagon_A2_vavgh; // "__builtin_HEXAG
ON_A2_vavgh"
case 'w': // 1 string to match.
return Intrinsic::hexagon_A2_vavgw; // "__builtin_HEXAG
ON_A2_vavgw"
}
break;
}
break;
case 'c': // 1 string to match.
if (memcmp(BuiltinName.data()+23, "onj", 3))
break;
return Intrinsic::hexagon_A2_vconj; // "__builtin_HEXAG
ON_A2_vconj"
case 'm': // 6 strings to match.
switch (BuiltinName[23]) {
default: break;
case 'a': // 3 strings to match.
if (BuiltinName[24] != 'x')
break;
switch (BuiltinName[25]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::hexagon_A2_vmaxb; // "__builtin_HEXAG
ON_A2_vmaxb"
case 'h': // 1 string to match.
return Intrinsic::hexagon_A2_vmaxh; // "__builtin_HEXAG
ON_A2_vmaxh"
case 'w': // 1 string to match.
return Intrinsic::hexagon_A2_vmaxw; // "__builtin_HEXAG
ON_A2_vmaxw"
}
break;
case 'i': // 3 strings to match.
if (BuiltinName[24] != 'n')
break;
switch (BuiltinName[25]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::hexagon_A2_vminb; // "__builtin_HEXAG
ON_A2_vminb"
case 'h': // 1 string to match.
return Intrinsic::hexagon_A2_vminh; // "__builtin_HEXAG
ON_A2_vminh"
case 'w': // 1 string to match.
return Intrinsic::hexagon_A2_vminw; // "__builtin_HEXAG
ON_A2_vminw"
}
break;
}
break;
case 's': // 2 strings to match.
if (memcmp(BuiltinName.data()+23, "ub", 2))
break;
switch (BuiltinName[25]) {
default: break;
case 'h': // 1 string to match.
return Intrinsic::hexagon_A2_vsubh; // "__builtin_HEXAG
ON_A2_vsubh"
case 'w': // 1 string to match.
return Intrinsic::hexagon_A2_vsubw; // "__builtin_HEXAG
ON_A2_vsubw"
}
break;
}
break;
}
break;
case '4': // 1 string to match.
if (memcmp(BuiltinName.data()+20, "_andnp", 6))
break;
return Intrinsic::hexagon_A4_andnp; // "__builtin_HEXAGON_A4_an
dnp"
}
break;
case 'C': // 9 strings to match.
switch (BuiltinName[19]) {
default: break;
case '2': // 8 strings to match.
if (BuiltinName[20] != '_')
break;
switch (BuiltinName[21]) {
default: break;
case 'c': // 3 strings to match.
if (memcmp(BuiltinName.data()+22, "mp", 2))
break;
switch (BuiltinName[24]) {
default: break;
case 'e': // 1 string to match.
if (BuiltinName[25] != 'q')
break;
return Intrinsic::hexagon_C2_cmpeq; // "__builtin_HEXAG
ON_C2_cmpeq"
case 'g': // 1 string to match.
if (BuiltinName[25] != 't')
break;
return Intrinsic::hexagon_C2_cmpgt; // "__builtin_HEXAG
ON_C2_cmpgt"
case 'l': // 1 string to match.
if (BuiltinName[25] != 't')
break;
return Intrinsic::hexagon_C2_cmplt; // "__builtin_HEXAG
ON_C2_cmplt"
}
break;
case 'm': // 3 strings to match.
if (memcmp(BuiltinName.data()+22, "ux", 2))
break;
switch (BuiltinName[24]) {
default: break;
case 'i': // 2 strings to match.
switch (BuiltinName[25]) {
default: break;
case 'i': // 1 string to match.
return Intrinsic::hexagon_C2_muxii; // "__builtin_HEXAG
ON_C2_muxii"
case 'r': // 1 string to match.
return Intrinsic::hexagon_C2_muxir; // "__builtin_HEXAG
ON_C2_muxir"
}
break;
case 'r': // 1 string to match.
if (BuiltinName[25] != 'i')
break;
return Intrinsic::hexagon_C2_muxri; // "__builtin_HEXAG
ON_C2_muxri"
}
break;
case 't': // 2 strings to match.
if (memcmp(BuiltinName.data()+22, "fr", 2))
break;
switch (BuiltinName[24]) {
default: break;
case 'p': // 1 string to match.
if (BuiltinName[25] != 'r')
break;
return Intrinsic::hexagon_C2_tfrpr; // "__builtin_HEXAG
ON_C2_tfrpr"
case 'r': // 1 string to match.
if (BuiltinName[25] != 'p')
break;
return Intrinsic::hexagon_C2_tfrrp; // "__builtin_HEXAG
ON_C2_tfrrp"
}
break;
}
break;
case '4': // 1 string to match.
if (memcmp(BuiltinName.data()+20, "_or_or", 6))
break;
return Intrinsic::hexagon_C4_or_or; // "__builtin_HEXAGON_C4_or
_or"
}
break;
case 'F': // 14 strings to match.
if (memcmp(BuiltinName.data()+19, "2_", 2))
break;
switch (BuiltinName[21]) {
default: break;
case 'd': // 7 strings to match.
if (BuiltinName[22] != 'f')
break;
switch (BuiltinName[23]) {
default: break;
case 'a': // 1 string to match.
if (memcmp(BuiltinName.data()+24, "dd", 2))
break;
return Intrinsic::hexagon_F2_dfadd; // "__builtin_HEXAG
ON_F2_dfadd"
case 'f': // 2 strings to match.
if (BuiltinName[24] != 'm')
break;
switch (BuiltinName[25]) {
default: break;
case 'a': // 1 string to match.
return Intrinsic::hexagon_F2_dffma; // "__builtin_HEXAG
ON_F2_dffma"
case 's': // 1 string to match.
return Intrinsic::hexagon_F2_dffms; // "__builtin_HEXAG
ON_F2_dffms"
}
break;
case 'm': // 3 strings to match.
switch (BuiltinName[24]) {
default: break;
case 'a': // 1 string to match.
if (BuiltinName[25] != 'x')
break;
return Intrinsic::hexagon_F2_dfmax; // "__builtin_HEXAG
ON_F2_dfmax"
case 'i': // 1 string to match.
if (BuiltinName[25] != 'n')
break;
return Intrinsic::hexagon_F2_dfmin; // "__builtin_HEXAG
ON_F2_dfmin"
case 'p': // 1 string to match.
if (BuiltinName[25] != 'y')
break;
return Intrinsic::hexagon_F2_dfmpy; // "__builtin_HEXAG
ON_F2_dfmpy"
}
break;
case 's': // 1 string to match.
if (memcmp(BuiltinName.data()+24, "ub", 2))
break;
return Intrinsic::hexagon_F2_dfsub; // "__builtin_HEXAG
ON_F2_dfsub"
}
break;
case 's': // 7 strings to match.
if (BuiltinName[22] != 'f')
break;
switch (BuiltinName[23]) {
default: break;
case 'a': // 1 string to match.
if (memcmp(BuiltinName.data()+24, "dd", 2))
break;
return Intrinsic::hexagon_F2_sfadd; // "__builtin_HEXAG
ON_F2_sfadd"
case 'f': // 2 strings to match.
if (BuiltinName[24] != 'm')
break;
switch (BuiltinName[25]) {
default: break;
case 'a': // 1 string to match.
return Intrinsic::hexagon_F2_sffma; // "__builtin_HEXAG
ON_F2_sffma"
case 's': // 1 string to match.
return Intrinsic::hexagon_F2_sffms; // "__builtin_HEXAG
ON_F2_sffms"
}
break;
case 'm': // 3 strings to match.
switch (BuiltinName[24]) {
default: break;
case 'a': // 1 string to match.
if (BuiltinName[25] != 'x')
break;
return Intrinsic::hexagon_F2_sfmax; // "__builtin_HEXAG
ON_F2_sfmax"
case 'i': // 1 string to match.
if (BuiltinName[25] != 'n')
break;
return Intrinsic::hexagon_F2_sfmin; // "__builtin_HEXAG
ON_F2_sfmin"
case 'p': // 1 string to match.
if (BuiltinName[25] != 'y')
break;
return Intrinsic::hexagon_F2_sfmpy; // "__builtin_HEXAG
ON_F2_sfmpy"
}
break;
case 's': // 1 string to match.
if (memcmp(BuiltinName.data()+24, "ub", 2))
break;
return Intrinsic::hexagon_F2_sfsub; // "__builtin_HEXAG
ON_F2_sfsub"
}
break;
}
break;
case 'M': // 6 strings to match.
switch (BuiltinName[19]) {
default: break;
case '2': // 4 strings to match.
if (BuiltinName[20] != '_')
break;
switch (BuiltinName[21]) {
default: break;
case 'a': // 1 string to match.
if (memcmp(BuiltinName.data()+22, "ccii", 4))
break;
return Intrinsic::hexagon_M2_accii; // "__builtin_HEXAG
ON_M2_accii"
case 'm': // 1 string to match.
if (memcmp(BuiltinName.data()+22, "pyui", 4))
break;
return Intrinsic::hexagon_M2_mpyui; // "__builtin_HEXAG
ON_M2_mpyui"
case 'n': // 1 string to match.
if (memcmp(BuiltinName.data()+22, "acci", 4))
break;
return Intrinsic::hexagon_M2_nacci; // "__builtin_HEXAG
ON_M2_nacci"
case 'v': // 1 string to match.
if (memcmp(BuiltinName.data()+22, "mac2", 4))
break;
return Intrinsic::hexagon_M2_vmac2; // "__builtin_HEXAG
ON_M2_vmac2"
}
break;
case '4': // 2 strings to match.
if (BuiltinName[20] != '_')
break;
switch (BuiltinName[21]) {
default: break;
case 'o': // 1 string to match.
if (memcmp(BuiltinName.data()+22, "r_or", 4))
break;
return Intrinsic::hexagon_M4_or_or; // "__builtin_HEXAG
ON_M4_or_or"
case 'p': // 1 string to match.
if (memcmp(BuiltinName.data()+22, "mpyw", 4))
break;
return Intrinsic::hexagon_M4_pmpyw; // "__builtin_HEXAG
ON_M4_pmpyw"
}
break;
}
break;
case 'S': // 1 string to match.
if (memcmp(BuiltinName.data()+19, "2_brevp", 7))
break;
return Intrinsic::hexagon_S2_brevp; // "__builtin_HEXAGON_S2_br
evp"
}
break; break;
switch (BuiltinName[2]) { case 'S': // 1 string to match.
default: break; if (memcmp(BuiltinName.data()+11, "I_to_SXTHI_asrh", 15))
case 'b': // 1 string to match.
if (BuiltinName.substr(3, 11) != "uiltin_trap")
break; break;
return Intrinsic::trap; // "__builtin_trap" return Intrinsic::hexagon_SI_to_SXTHI_asrh; // "__builtin_SI_to
case 'g': // 2 strings to match. _SXTHI_asrh"
if (BuiltinName.substr(3, 3) != "nu_") }
break;
case 27: // 70 strings to match.
if (memcmp(BuiltinName.data()+0, "__builtin_HEXAGON_", 18))
break;
switch (BuiltinName[18]) {
default: break;
case 'A': // 35 strings to match.
switch (BuiltinName[19]) {
default: break;
case '2': // 26 strings to match.
if (BuiltinName[20] != '_')
break;
switch (BuiltinName[21]) {
default: break;
case 'a': // 2 strings to match.
switch (BuiltinName[22]) {
default: break;
case 'b': // 1 string to match.
if (memcmp(BuiltinName.data()+23, "ssat", 4))
break;
return Intrinsic::hexagon_A2_abssat; // "__builtin_HEXAG
ON_A2_abssat"
case 'd': // 1 string to match.
if (memcmp(BuiltinName.data()+23, "dsat", 4))
break;
return Intrinsic::hexagon_A2_addsat; // "__builtin_HEXAG
ON_A2_addsat"
}
break;
case 'n': // 1 string to match.
if (memcmp(BuiltinName.data()+22, "egsat", 5))
break;
return Intrinsic::hexagon_A2_negsat; // "__builtin_HEXAGON_A2_ne
gsat"
case 's': // 4 strings to match.
switch (BuiltinName[22]) {
default: break;
case 'u': // 1 string to match.
if (memcmp(BuiltinName.data()+23, "bsat", 4))
break;
return Intrinsic::hexagon_A2_subsat; // "__builtin_HEXAG
ON_A2_subsat"
case 'v': // 3 strings to match.
switch (BuiltinName[23]) {
default: break;
case 'a': // 2 strings to match.
switch (BuiltinName[24]) {
default: break;
case 'd': // 1 string to match.
if (memcmp(BuiltinName.data()+25, "dh", 2))
break;
return Intrinsic::hexagon_A2_svaddh; // "__builtin_HEXAG
ON_A2_svaddh"
case 'v': // 1 string to match.
if (memcmp(BuiltinName.data()+25, "gh", 2))
break;
return Intrinsic::hexagon_A2_svavgh; // "__builtin_HEXAG
ON_A2_svavgh"
}
break;
case 's': // 1 string to match.
if (memcmp(BuiltinName.data()+24, "ubh", 3))
break;
return Intrinsic::hexagon_A2_svsubh; // "__builtin_HEXAG
ON_A2_svsubh"
}
break;
}
break;
case 'v': // 19 strings to match.
switch (BuiltinName[22]) {
default: break;
case 'a': // 8 strings to match.
switch (BuiltinName[23]) {
default: break;
case 'd': // 3 strings to match.
if (BuiltinName[24] != 'd')
break;
switch (BuiltinName[25]) {
default: break;
case 'h': // 1 string to match.
if (BuiltinName[26] != 's')
break;
return Intrinsic::hexagon_A2_vaddhs; // "__builtin_HEXAG
ON_A2_vaddhs"
case 'u': // 1 string to match.
if (BuiltinName[26] != 'b')
break;
return Intrinsic::hexagon_A2_vaddub; // "__builtin_HEXAG
ON_A2_vaddub"
case 'w': // 1 string to match.
if (BuiltinName[26] != 's')
break;
return Intrinsic::hexagon_A2_vaddws; // "__builtin_HEXAG
ON_A2_vaddws"
}
break;
case 'v': // 5 strings to match.
if (BuiltinName[24] != 'g')
break;
switch (BuiltinName[25]) {
default: break;
case 'h': // 1 string to match.
if (BuiltinName[26] != 'r')
break;
return Intrinsic::hexagon_A2_vavghr; // "__builtin_HEXAG
ON_A2_vavghr"
case 'u': // 3 strings to match.
switch (BuiltinName[26]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::hexagon_A2_vavgub; // "__builtin_HEXAG
ON_A2_vavgub"
case 'h': // 1 string to match.
return Intrinsic::hexagon_A2_vavguh; // "__builtin_HEXAG
ON_A2_vavguh"
case 'w': // 1 string to match.
return Intrinsic::hexagon_A2_vavguw; // "__builtin_HEXAG
ON_A2_vavguw"
}
break;
case 'w': // 1 string to match.
if (BuiltinName[26] != 'r')
break;
return Intrinsic::hexagon_A2_vavgwr; // "__builtin_HEXAG
ON_A2_vavgwr"
}
break;
}
break;
case 'm': // 6 strings to match.
switch (BuiltinName[23]) {
default: break;
case 'a': // 3 strings to match.
if (memcmp(BuiltinName.data()+24, "xu", 2))
break;
switch (BuiltinName[26]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::hexagon_A2_vmaxub; // "__builtin_HEXAG
ON_A2_vmaxub"
case 'h': // 1 string to match.
return Intrinsic::hexagon_A2_vmaxuh; // "__builtin_HEXAG
ON_A2_vmaxuh"
case 'w': // 1 string to match.
return Intrinsic::hexagon_A2_vmaxuw; // "__builtin_HEXAG
ON_A2_vmaxuw"
}
break;
case 'i': // 3 strings to match.
if (memcmp(BuiltinName.data()+24, "nu", 2))
break;
switch (BuiltinName[26]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::hexagon_A2_vminub; // "__builtin_HEXAG
ON_A2_vminub"
case 'h': // 1 string to match.
return Intrinsic::hexagon_A2_vminuh; // "__builtin_HEXAG
ON_A2_vminuh"
case 'w': // 1 string to match.
return Intrinsic::hexagon_A2_vminuw; // "__builtin_HEXAG
ON_A2_vminuw"
}
break;
}
break;
case 'n': // 2 strings to match.
if (memcmp(BuiltinName.data()+23, "avg", 3))
break;
switch (BuiltinName[26]) {
default: break;
case 'h': // 1 string to match.
return Intrinsic::hexagon_A2_vnavgh; // "__builtin_HEXAG
ON_A2_vnavgh"
case 'w': // 1 string to match.
return Intrinsic::hexagon_A2_vnavgw; // "__builtin_HEXAG
ON_A2_vnavgw"
}
break;
case 's': // 3 strings to match.
if (memcmp(BuiltinName.data()+23, "ub", 2))
break;
switch (BuiltinName[25]) {
default: break;
case 'h': // 1 string to match.
if (BuiltinName[26] != 's')
break;
return Intrinsic::hexagon_A2_vsubhs; // "__builtin_HEXAG
ON_A2_vsubhs"
case 'u': // 1 string to match.
if (BuiltinName[26] != 'b')
break;
return Intrinsic::hexagon_A2_vsubub; // "__builtin_HEXAG
ON_A2_vsubub"
case 'w': // 1 string to match.
if (BuiltinName[26] != 's')
break;
return Intrinsic::hexagon_A2_vsubws; // "__builtin_HEXAG
ON_A2_vsubws"
}
break;
}
break;
}
break; break;
switch (BuiltinName[6]) { case '4': // 9 strings to match.
default: break; if (BuiltinName[20] != '_')
case 'f': // 1 string to match.
if (BuiltinName.substr(7, 7) != "2h_ieee")
break; break;
return Intrinsic::convert_to_fp16; // "__gnu_f2h_ieee" switch (BuiltinName[21]) {
case 'h': // 1 string to match. default: break;
if (BuiltinName.substr(7, 7) != "2f_ieee") case 'c': // 4 strings to match.
if (memcmp(BuiltinName.data()+22, "mp", 2))
break;
switch (BuiltinName[24]) {
default: break;
case 'b': // 2 strings to match.
switch (BuiltinName[25]) {
default: break;
case 'e': // 1 string to match.
if (BuiltinName[26] != 'q')
break;
return Intrinsic::hexagon_A4_cmpbeq; // "__builtin_HEXAG
ON_A4_cmpbeq"
case 'g': // 1 string to match.
if (BuiltinName[26] != 't')
break;
return Intrinsic::hexagon_A4_cmpbgt; // "__builtin_HEXAG
ON_A4_cmpbgt"
}
break;
case 'h': // 2 strings to match.
switch (BuiltinName[25]) {
default: break;
case 'e': // 1 string to match.
if (BuiltinName[26] != 'q')
break;
return Intrinsic::hexagon_A4_cmpheq; // "__builtin_HEXAG
ON_A4_cmpheq"
case 'g': // 1 string to match.
if (BuiltinName[26] != 't')
break;
return Intrinsic::hexagon_A4_cmphgt; // "__builtin_HEXAG
ON_A4_cmphgt"
}
break;
}
break; break;
return Intrinsic::convert_from_fp16; // "__gnu_h2f_ieee" case 'r': // 1 string to match.
if (memcmp(BuiltinName.data()+22, "cmpeq", 5))
break;
return Intrinsic::hexagon_A4_rcmpeq; // "__builtin_HEXAGON_A4_rc
mpeq"
case 'v': // 4 strings to match.
if (memcmp(BuiltinName.data()+22, "rm", 2))
break;
switch (BuiltinName[24]) {
default: break;
case 'a': // 2 strings to match.
if (BuiltinName[25] != 'x')
break;
switch (BuiltinName[26]) {
default: break;
case 'h': // 1 string to match.
return Intrinsic::hexagon_A4_vrmaxh; // "__builtin_HEXAG
ON_A4_vrmaxh"
case 'w': // 1 string to match.
return Intrinsic::hexagon_A4_vrmaxw; // "__builtin_HEXAG
ON_A4_vrmaxw"
}
break;
case 'i': // 2 strings to match.
if (BuiltinName[25] != 'n')
break;
switch (BuiltinName[26]) {
default: break;
case 'h': // 1 string to match.
return Intrinsic::hexagon_A4_vrminh; // "__builtin_HEXAG
ON_A4_vrminh"
case 'w': // 1 string to match.
return Intrinsic::hexagon_A4_vrminw; // "__builtin_HEXAG
ON_A4_vrminw"
}
break;
}
break;
}
break;
} }
break; break;
} case 'C': // 12 strings to match.
break; switch (BuiltinName[19]) {
case 20: // 2 strings to match. default: break;
if (BuiltinName.substr(0, 10) != "__builtin_") case '2': // 7 strings to match.
break; if (memcmp(BuiltinName.data()+20, "_cmp", 4))
switch (BuiltinName[10]) { break;
default: break; switch (BuiltinName[24]) {
case 'f': // 1 string to match. default: break;
if (BuiltinName.substr(11, 9) != "lt_rounds") case 'e': // 2 strings to match.
if (BuiltinName[25] != 'q')
break;
switch (BuiltinName[26]) {
default: break;
case 'i': // 1 string to match.
return Intrinsic::hexagon_C2_cmpeqi; // "__builtin_HEXAG
ON_C2_cmpeqi"
case 'p': // 1 string to match.
return Intrinsic::hexagon_C2_cmpeqp; // "__builtin_HEXAG
ON_C2_cmpeqp"
}
break;
case 'g': // 4 strings to match.
switch (BuiltinName[25]) {
default: break;
case 'e': // 1 string to match.
if (BuiltinName[26] != 'i')
break;
return Intrinsic::hexagon_C2_cmpgei; // "__builtin_HEXAG
ON_C2_cmpgei"
case 't': // 3 strings to match.
switch (BuiltinName[26]) {
default: break;
case 'i': // 1 string to match.
return Intrinsic::hexagon_C2_cmpgti; // "__builtin_HEXAG
ON_C2_cmpgti"
case 'p': // 1 string to match.
return Intrinsic::hexagon_C2_cmpgtp; // "__builtin_HEXAG
ON_C2_cmpgtp"
case 'u': // 1 string to match.
return Intrinsic::hexagon_C2_cmpgtu; // "__builtin_HEXAG
ON_C2_cmpgtu"
}
break;
}
break;
case 'l': // 1 string to match.
if (memcmp(BuiltinName.data()+25, "tu", 2))
break;
return Intrinsic::hexagon_C2_cmpltu; // "__builtin_HEXAGON_C2_cm
pltu"
}
break; break;
return Intrinsic::flt_rounds; // "__builtin_flt_rounds" case '4': // 5 strings to match.
case 's': // 1 string to match. if (BuiltinName[20] != '_')
if (BuiltinName.substr(11, 9) != "tack_save") break;
switch (BuiltinName[21]) {
default: break;
case 'a': // 1 string to match.
if (memcmp(BuiltinName.data()+22, "nd_or", 5))
break;
return Intrinsic::hexagon_C4_and_or; // "__builtin_HEXAGON_C4_an
d_or"
case 'c': // 2 strings to match.
if (memcmp(BuiltinName.data()+22, "mp", 2))
break;
switch (BuiltinName[24]) {
default: break;
case 'l': // 1 string to match.
if (memcmp(BuiltinName.data()+25, "te", 2))
break;
return Intrinsic::hexagon_C4_cmplte; // "__builtin_HEXAG
ON_C4_cmplte"
case 'n': // 1 string to match.
if (memcmp(BuiltinName.data()+25, "eq", 2))
break;
return Intrinsic::hexagon_C4_cmpneq; // "__builtin_HEXAG
ON_C4_cmpneq"
}
break;
case 'o': // 2 strings to match.
if (memcmp(BuiltinName.data()+22, "r_", 2))
break;
switch (BuiltinName[24]) {
default: break;
case 'a': // 1 string to match.
if (memcmp(BuiltinName.data()+25, "nd", 2))
break;
return Intrinsic::hexagon_C4_or_and; // "__builtin_HEXAG
ON_C4_or_and"
case 'o': // 1 string to match.
if (memcmp(BuiltinName.data()+25, "rn", 2))
break;
return Intrinsic::hexagon_C4_or_orn; // "__builtin_HEXAG
ON_C4_or_orn"
}
break;
}
break; break;
return Intrinsic::stacksave; // "__builtin_stack_save" }
}
break;
case 21: // 16 strings to match.
if (BuiltinName.substr(0, 10) != "__builtin_")
break; break;
switch (BuiltinName[10]) { case 'M': // 12 strings to match.
default: break; switch (BuiltinName[19]) {
case 'i': // 14 strings to match.
if (BuiltinName.substr(11, 6) != "a32_vp")
break;
switch (BuiltinName[17]) {
default: break; default: break;
case 'c': // 1 string to match. case '2': // 7 strings to match.
if (BuiltinName.substr(18, 3) != "mov") if (BuiltinName[20] != '_')
break;
return Intrinsic::x86_xop_vpcmov; // "__builtin_ia32_vpcmov"
case 'p': // 1 string to match.
if (BuiltinName.substr(18, 3) != "erm")
break;
return Intrinsic::x86_xop_vpperm; // "__builtin_ia32_vpperm"
case 'r': // 4 strings to match.
if (BuiltinName.substr(18, 2) != "ot")
break; break;
switch (BuiltinName[20]) { switch (BuiltinName[21]) {
default: break; default: break;
case 'b': // 1 string to match. case 'm': // 4 strings to match.
return Intrinsic::x86_xop_vprotb; // "__builtin_ia32_vprotb" switch (BuiltinName[22]) {
case 'd': // 1 string to match. default: break;
return Intrinsic::x86_xop_vprotd; // "__builtin_ia32_vprotd" case 'a': // 2 strings to match.
case 'q': // 1 string to match. if (memcmp(BuiltinName.data()+23, "csi", 3))
return Intrinsic::x86_xop_vprotq; // "__builtin_ia32_vprotq" break;
case 'w': // 1 string to match. switch (BuiltinName[26]) {
return Intrinsic::x86_xop_vprotw; // "__builtin_ia32_vprotw" default: break;
case 'n': // 1 string to match.
return Intrinsic::hexagon_M2_macsin; // "__builtin_HEXAG
ON_M2_macsin"
case 'p': // 1 string to match.
return Intrinsic::hexagon_M2_macsip; // "__builtin_HEXAG
ON_M2_macsip"
}
break;
case 'p': // 2 strings to match.
if (BuiltinName[23] != 'y')
break;
switch (BuiltinName[24]) {
default: break;
case '_': // 1 string to match.
if (memcmp(BuiltinName.data()+25, "up", 2))
break;
return Intrinsic::hexagon_M2_mpy_up; // "__builtin_HEXAG
ON_M2_mpy_up"
case 's': // 1 string to match.
if (memcmp(BuiltinName.data()+25, "mi", 2))
break;
return Intrinsic::hexagon_M2_mpysmi; // "__builtin_HEXAG
ON_M2_mpysmi"
}
break;
}
break;
case 'n': // 1 string to match.
if (memcmp(BuiltinName.data()+22, "accii", 5))
break;
return Intrinsic::hexagon_M2_naccii; // "__builtin_HEXAGON_M2_na
ccii"
case 's': // 1 string to match.
if (memcmp(BuiltinName.data()+22, "ubacc", 5))
break;
return Intrinsic::hexagon_M2_subacc; // "__builtin_HEXAGON_M2_su
bacc"
case 'v': // 1 string to match.
if (memcmp(BuiltinName.data()+22, "raddh", 5))
break;
return Intrinsic::hexagon_M2_vraddh; // "__builtin_HEXAGON_M2_vr
addh"
} }
break; break;
case 's': // 8 strings to match. case '4': // 5 strings to match.
if (BuiltinName[18] != 'h') if (BuiltinName[20] != '_')
break; break;
switch (BuiltinName[19]) { switch (BuiltinName[21]) {
default: break; default: break;
case 'a': // 4 strings to match. case 'a': // 1 string to match.
switch (BuiltinName[20]) { if (memcmp(BuiltinName.data()+22, "nd_or", 5))
break;
return Intrinsic::hexagon_M4_and_or; // "__builtin_HEXAGON_M4_an
d_or"
case 'o': // 2 strings to match.
if (memcmp(BuiltinName.data()+22, "r_", 2))
break;
switch (BuiltinName[24]) {
default: break; default: break;
case 'b': // 1 string to match. case 'a': // 1 string to match.
return Intrinsic::x86_xop_vpshab; // "__builtin_ia32_vpshab" if (memcmp(BuiltinName.data()+25, "nd", 2))
case 'd': // 1 string to match. break;
return Intrinsic::x86_xop_vpshad; // "__builtin_ia32_vpshad" return Intrinsic::hexagon_M4_or_and; // "__builtin_HEXAG
case 'q': // 1 string to match. ON_M4_or_and"
return Intrinsic::x86_xop_vpshaq; // "__builtin_ia32_vpshaq" case 'x': // 1 string to match.
case 'w': // 1 string to match. if (memcmp(BuiltinName.data()+25, "or", 2))
return Intrinsic::x86_xop_vpshaw; // "__builtin_ia32_vpshaw" break;
return Intrinsic::hexagon_M4_or_xor; // "__builtin_HEXAG
ON_M4_or_xor"
} }
break; break;
case 'l': // 4 strings to match. case 'v': // 1 string to match.
switch (BuiltinName[20]) { if (memcmp(BuiltinName.data()+22, "pmpyh", 5))
break;
return Intrinsic::hexagon_M4_vpmpyh; // "__builtin_HEXAGON_M4_vp
mpyh"
case 'x': // 1 string to match.
if (memcmp(BuiltinName.data()+22, "or_or", 5))
break;
return Intrinsic::hexagon_M4_xor_or; // "__builtin_HEXAGON_M4_xo
r_or"
}
break;
}
break;
case 'S': // 11 strings to match.
switch (BuiltinName[19]) {
default: break;
case '2': // 9 strings to match.
if (BuiltinName[20] != '_')
break;
switch (BuiltinName[21]) {
default: break;
case 'i': // 1 string to match.
if (memcmp(BuiltinName.data()+22, "nsert", 5))
break;
return Intrinsic::hexagon_S2_insert; // "__builtin_HEXAGON_S2_in
sert"
case 'p': // 1 string to match.
if (memcmp(BuiltinName.data()+22, "ackhl", 5))
break;
return Intrinsic::hexagon_S2_packhl; // "__builtin_HEXAGON_S2_pa
ckhl"
case 'v': // 7 strings to match.
switch (BuiltinName[22]) {
default: break; default: break;
case 'b': // 1 string to match. case 'c': // 1 string to match.
return Intrinsic::x86_xop_vpshlb; // "__builtin_ia32_vpshlb" if (memcmp(BuiltinName.data()+23, "negh", 4))
case 'd': // 1 string to match. break;
return Intrinsic::x86_xop_vpshld; // "__builtin_ia32_vpshld" return Intrinsic::hexagon_S2_vcnegh; // "__builtin_HEXAG
case 'q': // 1 string to match. ON_S2_vcnegh"
return Intrinsic::x86_xop_vpshlq; // "__builtin_ia32_vpshlq" case 's': // 4 strings to match.
case 'w': // 1 string to match. switch (BuiltinName[23]) {
return Intrinsic::x86_xop_vpshlw; // "__builtin_ia32_vpshlw" default: break;
case 'a': // 2 strings to match.
if (BuiltinName[24] != 't')
break;
switch (BuiltinName[25]) {
default: break;
case 'h': // 1 string to match.
if (BuiltinName[26] != 'b')
break;
return Intrinsic::hexagon_S2_vsathb; // "__builtin_HEXAG
ON_S2_vsathb"
case 'w': // 1 string to match.
if (BuiltinName[26] != 'h')
break;
return Intrinsic::hexagon_S2_vsatwh; // "__builtin_HEXAG
ON_S2_vsatwh"
}
break;
case 'x': // 2 strings to match.
if (BuiltinName[24] != 't')
break;
switch (BuiltinName[25]) {
default: break;
case 'b': // 1 string to match.
if (BuiltinName[26] != 'h')
break;
return Intrinsic::hexagon_S2_vsxtbh; // "__builtin_HEXAG
ON_S2_vsxtbh"
case 'h': // 1 string to match.
if (BuiltinName[26] != 'w')
break;
return Intrinsic::hexagon_S2_vsxthw; // "__builtin_HEXAG
ON_S2_vsxthw"
}
break;
}
break;
case 'z': // 2 strings to match.
if (memcmp(BuiltinName.data()+23, "xt", 2))
break;
switch (BuiltinName[25]) {
default: break;
case 'b': // 1 string to match.
if (BuiltinName[26] != 'h')
break;
return Intrinsic::hexagon_S2_vzxtbh; // "__builtin_HEXAG
ON_S2_vzxtbh"
case 'h': // 1 string to match.
if (BuiltinName[26] != 'w')
break;
return Intrinsic::hexagon_S2_vzxthw; // "__builtin_HEXAG
ON_S2_vzxthw"
}
break;
} }
break; break;
} }
break; break;
} case '4': // 2 strings to match.
break; if (BuiltinName[20] != '_')
case 'o': // 1 string to match. break;
if (BuiltinName.substr(11, 10) != "bject_size") switch (BuiltinName[21]) {
break; default: break;
return Intrinsic::objectsize; // "__builtin_object_size" case 'o': // 1 string to match.
case 'u': // 1 string to match. if (memcmp(BuiltinName.data()+22, "r_ori", 5))
if (BuiltinName.substr(11, 10) != "nwind_init") break;
return Intrinsic::hexagon_S4_or_ori; // "__builtin_HEXAGON_S4_or
_ori"
case 'p': // 1 string to match.
if (memcmp(BuiltinName.data()+22, "arity", 5))
break;
return Intrinsic::hexagon_S4_parity; // "__builtin_HEXAGON_S4_pa
rity"
}
break; break;
return Intrinsic::eh_unwind_init; // "__builtin_unwind_init"
}
break;
case 22: // 4 strings to match.
if (BuiltinName.substr(0, 20) != "__builtin_ia32_vfrcz")
break;
switch (BuiltinName[20]) {
default: break;
case 'p': // 2 strings to match.
switch (BuiltinName[21]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::x86_xop_vfrcz_pd; // "__builtin_ia32_vfrczpd"
case 's': // 1 string to match.
return Intrinsic::x86_xop_vfrcz_ps; // "__builtin_ia32_vfrczps"
}
break;
case 's': // 2 strings to match.
switch (BuiltinName[21]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::x86_xop_vfrcz_sd; // "__builtin_ia32_vfrczsd"
case 's': // 1 string to match.
return Intrinsic::x86_xop_vfrcz_ss; // "__builtin_ia32_vfrczss"
} }
break; break;
} }
break; break;
case 23: // 37 strings to match. case 28: // 103 strings to match.
if (BuiltinName.substr(0, 10) != "__builtin_") if (memcmp(BuiltinName.data()+0, "__builtin_HEXAGON_", 18))
break; break;
switch (BuiltinName[10]) { switch (BuiltinName[18]) {
default: break; default: break;
case 'i': // 36 strings to match. case 'A': // 36 strings to match.
if (BuiltinName.substr(11, 6) != "a32_vp") switch (BuiltinName[19]) {
break;
switch (BuiltinName[17]) {
default: break; default: break;
case 'c': // 24 strings to match. case '2': // 23 strings to match.
if (BuiltinName.substr(18, 2) != "om") if (BuiltinName[20] != '_')
break; break;
switch (BuiltinName[20]) { switch (BuiltinName[21]) {
default: break; default: break;
case 'e': // 4 strings to match. case 'a': // 1 string to match.
if (BuiltinName[21] != 'q') if (memcmp(BuiltinName.data()+22, "ddpsat", 6))
break; break;
switch (BuiltinName[22]) { return Intrinsic::hexagon_A2_addpsat; // "__builtin_HEXAG
ON_A2_addpsat"
case 's': // 4 strings to match.
if (BuiltinName[22] != 'v')
break;
switch (BuiltinName[23]) {
default: break; default: break;
case 'b': // 1 string to match. case 'a': // 2 strings to match.
return Intrinsic::x86_xop_vpcomeqb; // "__builtin_ia32_ switch (BuiltinName[24]) {
vpcomeqb" default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
return Intrinsic::x86_xop_vpcomeqd; // "__builtin_ia32_ if (memcmp(BuiltinName.data()+25, "dhs", 3))
vpcomeqd" break;
case 'q': // 1 string to match. return Intrinsic::hexagon_A2_svaddhs; // "__builtin_HEXAG
return Intrinsic::x86_xop_vpcomeqq; // "__builtin_ia32_ ON_A2_svaddhs"
vpcomeqq" case 'v': // 1 string to match.
case 'w': // 1 string to match. if (memcmp(BuiltinName.data()+25, "ghs", 3))
return Intrinsic::x86_xop_vpcomeqw; // "__builtin_ia32_ break;
vpcomeqw" return Intrinsic::hexagon_A2_svavghs; // "__builtin_HEXAG
ON_A2_svavghs"
}
break;
case 'n': // 1 string to match.
if (memcmp(BuiltinName.data()+24, "avgh", 4))
break;
return Intrinsic::hexagon_A2_svnavgh; // "__builtin_HEXAG
ON_A2_svnavgh"
case 's': // 1 string to match.
if (memcmp(BuiltinName.data()+24, "ubhs", 4))
break;
return Intrinsic::hexagon_A2_svsubhs; // "__builtin_HEXAG
ON_A2_svsubhs"
} }
break; break;
case 'g': // 8 strings to match. case 'v': // 18 strings to match.
switch (BuiltinName[21]) { switch (BuiltinName[22]) {
default: break; default: break;
case 'e': // 4 strings to match. case 'a': // 7 strings to match.
switch (BuiltinName[22]) { switch (BuiltinName[23]) {
default: break;
case 'd': // 2 strings to match.
if (memcmp(BuiltinName.data()+24, "du", 2))
break;
switch (BuiltinName[26]) {
default: break;
case 'b': // 1 string to match.
if (BuiltinName[27] != 's')
break;
return Intrinsic::hexagon_A2_vaddubs; // "__builtin_HEXAG
ON_A2_vaddubs"
case 'h': // 1 string to match.
if (BuiltinName[27] != 's')
break;
return Intrinsic::hexagon_A2_vadduhs; // "__builtin_HEXAG
ON_A2_vadduhs"
}
break;
case 'v': // 5 strings to match.
if (BuiltinName[24] != 'g')
break;
switch (BuiltinName[25]) {
default: break;
case 'h': // 1 string to match.
if (memcmp(BuiltinName.data()+26, "cr", 2))
break;
return Intrinsic::hexagon_A2_vavghcr; // "__builtin_HEXAG
ON_A2_vavghcr"
case 'u': // 3 strings to match.
switch (BuiltinName[26]) {
default: break;
case 'b': // 1 string to match.
if (BuiltinName[27] != 'r')
break;
return Intrinsic::hexagon_A2_vavgubr; // "__built
in_HEXAGON_A2_vavgubr"
case 'h': // 1 string to match.
if (BuiltinName[27] != 'r')
break;
return Intrinsic::hexagon_A2_vavguhr; // "__built
in_HEXAGON_A2_vavguhr"
case 'w': // 1 string to match.
if (BuiltinName[27] != 'r')
break;
return Intrinsic::hexagon_A2_vavguwr; // "__built
in_HEXAGON_A2_vavguwr"
}
break;
case 'w': // 1 string to match.
if (memcmp(BuiltinName.data()+26, "cr", 2))
break;
return Intrinsic::hexagon_A2_vavgwcr; // "__builtin_HEXAG
ON_A2_vavgwcr"
}
break;
}
break;
case 'c': // 5 strings to match.
if (memcmp(BuiltinName.data()+23, "mp", 2))
break;
switch (BuiltinName[25]) {
default: break; default: break;
case 'b': // 1 string to match. case 'b': // 1 string to match.
return Intrinsic::x86_xop_vpcomgeb; // "__builtin_ia32_ if (memcmp(BuiltinName.data()+26, "eq", 2))
vpcomgeb" break;
case 'd': // 1 string to match. return Intrinsic::hexagon_A2_vcmpbeq; // "__builtin_HEXAG
return Intrinsic::x86_xop_vpcomged; // "__builtin_ia32_ ON_A2_vcmpbeq"
vpcomged" case 'h': // 2 strings to match.
case 'q': // 1 string to match. switch (BuiltinName[26]) {
return Intrinsic::x86_xop_vpcomgeq; // "__builtin_ia32_ default: break;
vpcomgeq" case 'e': // 1 string to match.
if (BuiltinName[27] != 'q')
break;
return Intrinsic::hexagon_A2_vcmpheq; // "__builtin_HEXAG
ON_A2_vcmpheq"
case 'g': // 1 string to match.
if (BuiltinName[27] != 't')
break;
return Intrinsic::hexagon_A2_vcmphgt; // "__builtin_HEXAG
ON_A2_vcmphgt"
}
break;
case 'w': // 2 strings to match.
switch (BuiltinName[26]) {
default: break;
case 'e': // 1 string to match.
if (BuiltinName[27] != 'q')
break;
return Intrinsic::hexagon_A2_vcmpweq; // "__builtin_HEXAG
ON_A2_vcmpweq"
case 'g': // 1 string to match.
if (BuiltinName[27] != 't')
break;
return Intrinsic::hexagon_A2_vcmpwgt; // "__builtin_HEXAG
ON_A2_vcmpwgt"
}
break;
}
break;
case 'n': // 2 strings to match.
if (memcmp(BuiltinName.data()+23, "avg", 3))
break;
switch (BuiltinName[26]) {
default: break;
case 'h': // 1 string to match.
if (BuiltinName[27] != 'r')
break;
return Intrinsic::hexagon_A2_vnavghr; // "__builtin_HEXAG
ON_A2_vnavghr"
case 'w': // 1 string to match. case 'w': // 1 string to match.
return Intrinsic::x86_xop_vpcomgew; // "__builtin_ia32_ if (BuiltinName[27] != 'r')
vpcomgew" break;
return Intrinsic::hexagon_A2_vnavgwr; // "__builtin_HEXAG
ON_A2_vnavgwr"
} }
break; break;
case 't': // 4 strings to match. case 'r': // 2 strings to match.
switch (BuiltinName[22]) { switch (BuiltinName[23]) {
default: break;
case 'a': // 1 string to match.
if (memcmp(BuiltinName.data()+24, "ddub", 4))
break;
return Intrinsic::hexagon_A2_vraddub; // "__builtin_HEXAG
ON_A2_vraddub"
case 's': // 1 string to match.
if (memcmp(BuiltinName.data()+24, "adub", 4))
break;
return Intrinsic::hexagon_A2_vrsadub; // "__builtin_HEXAG
ON_A2_vrsadub"
}
break;
case 's': // 2 strings to match.
if (memcmp(BuiltinName.data()+23, "ubu", 3))
break;
switch (BuiltinName[26]) {
default: break; default: break;
case 'b': // 1 string to match. case 'b': // 1 string to match.
return Intrinsic::x86_xop_vpcomgtb; // "__builtin_ia32_ if (BuiltinName[27] != 's')
vpcomgtb" break;
case 'd': // 1 string to match. return Intrinsic::hexagon_A2_vsububs; // "__builtin_HEXAG
return Intrinsic::x86_xop_vpcomgtd; // "__builtin_ia32_ ON_A2_vsububs"
vpcomgtd" case 'h': // 1 string to match.
case 'q': // 1 string to match. if (BuiltinName[27] != 's')
return Intrinsic::x86_xop_vpcomgtq; // "__builtin_ia32_ break;
vpcomgtq" return Intrinsic::hexagon_A2_vsubuhs; // "__builtin_HEXAG
case 'w': // 1 string to match. ON_A2_vsubuhs"
return Intrinsic::x86_xop_vpcomgtw; // "__builtin_ia32_
vpcomgtw"
} }
break; break;
} }
break; break;
case 'l': // 8 strings to match. }
switch (BuiltinName[21]) { break;
case '4': // 13 strings to match.
if (BuiltinName[20] != '_')
break;
switch (BuiltinName[21]) {
default: break;
case 'c': // 6 strings to match.
if (memcmp(BuiltinName.data()+22, "mp", 2))
break;
switch (BuiltinName[24]) {
default: break; default: break;
case 'e': // 4 strings to match. case 'b': // 3 strings to match.
switch (BuiltinName[22]) { switch (BuiltinName[25]) {
default: break; default: break;
case 'b': // 1 string to match. case 'e': // 1 string to match.
return Intrinsic::x86_xop_vpcomleb; // "__builtin_ia32_ if (memcmp(BuiltinName.data()+26, "qi", 2))
vpcomleb" break;
case 'd': // 1 string to match. return Intrinsic::hexagon_A4_cmpbeqi; // "__builtin_HEXAG
return Intrinsic::x86_xop_vpcomled; // "__builtin_ia32_ ON_A4_cmpbeqi"
vpcomled" case 'g': // 2 strings to match.
case 'q': // 1 string to match. if (BuiltinName[26] != 't')
return Intrinsic::x86_xop_vpcomleq; // "__builtin_ia32_ break;
vpcomleq" switch (BuiltinName[27]) {
case 'w': // 1 string to match. default: break;
return Intrinsic::x86_xop_vpcomlew; // "__builtin_ia32_ case 'i': // 1 string to match.
vpcomlew" return Intrinsic::hexagon_A4_cmpbgti; // "__builtin_HEXAG
ON_A4_cmpbgti"
case 'u': // 1 string to match.
return Intrinsic::hexagon_A4_cmpbgtu; // "__builtin_HEXAG
ON_A4_cmpbgtu"
}
break;
} }
break; break;
case 't': // 4 strings to match. case 'h': // 3 strings to match.
switch (BuiltinName[22]) { switch (BuiltinName[25]) {
default: break; default: break;
case 'b': // 1 string to match. case 'e': // 1 string to match.
return Intrinsic::x86_xop_vpcomltb; // "__builtin_ia32_ if (memcmp(BuiltinName.data()+26, "qi", 2))
vpcomltb" break;
case 'd': // 1 string to match. return Intrinsic::hexagon_A4_cmpheqi; // "__builtin_HEXAG
return Intrinsic::x86_xop_vpcomltd; // "__builtin_ia32_ ON_A4_cmpheqi"
vpcomltd" case 'g': // 2 strings to match.
case 'q': // 1 string to match. if (BuiltinName[26] != 't')
return Intrinsic::x86_xop_vpcomltq; // "__builtin_ia32_ break;
vpcomltq" switch (BuiltinName[27]) {
case 'w': // 1 string to match. default: break;
return Intrinsic::x86_xop_vpcomltw; // "__builtin_ia32_ case 'i': // 1 string to match.
vpcomltw" return Intrinsic::hexagon_A4_cmphgti; // "__builtin_HEXAG
ON_A4_cmphgti"
case 'u': // 1 string to match.
return Intrinsic::hexagon_A4_cmphgtu; // "__builtin_HEXAG
ON_A4_cmphgtu"
}
break;
}
break;
}
break;
case 'r': // 2 strings to match.
if (memcmp(BuiltinName.data()+22, "cmp", 3))
break;
switch (BuiltinName[25]) {
default: break;
case 'e': // 1 string to match.
if (memcmp(BuiltinName.data()+26, "qi", 2))
break;
return Intrinsic::hexagon_A4_rcmpeqi; // "__builtin_HEXAG
ON_A4_rcmpeqi"
case 'n': // 1 string to match.
if (memcmp(BuiltinName.data()+26, "eq", 2))
break;
return Intrinsic::hexagon_A4_rcmpneq; // "__builtin_HEXAG
ON_A4_rcmpneq"
}
break;
case 'v': // 5 strings to match.
switch (BuiltinName[22]) {
default: break;
case 'c': // 1 string to match.
if (memcmp(BuiltinName.data()+23, "mpbgt", 5))
break;
return Intrinsic::hexagon_A4_vcmpbgt; // "__builtin_HEXAG
ON_A4_vcmpbgt"
case 'r': // 4 strings to match.
if (BuiltinName[23] != 'm')
break;
switch (BuiltinName[24]) {
default: break;
case 'a': // 2 strings to match.
if (memcmp(BuiltinName.data()+25, "xu", 2))
break;
switch (BuiltinName[27]) {
default: break;
case 'h': // 1 string to match.
return Intrinsic::hexagon_A4_vrmaxuh; // "__builtin_HEXAG
ON_A4_vrmaxuh"
case 'w': // 1 string to match.
return Intrinsic::hexagon_A4_vrmaxuw; // "__builtin_HEXAG
ON_A4_vrmaxuw"
}
break;
case 'i': // 2 strings to match.
if (memcmp(BuiltinName.data()+25, "nu", 2))
break;
switch (BuiltinName[27]) {
default: break;
case 'h': // 1 string to match.
return Intrinsic::hexagon_A4_vrminuh; // "__builtin_HEXAG
ON_A4_vrminuh"
case 'w': // 1 string to match.
return Intrinsic::hexagon_A4_vrminuw; // "__builtin_HEXAG
ON_A4_vrminuw"
}
break;
} }
break; break;
} }
break; break;
case 'n': // 4 strings to match.
if (BuiltinName[21] != 'e')
break;
switch (BuiltinName[22]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::x86_xop_vpcomneb; // "__builtin_ia32_
vpcomneb"
case 'd': // 1 string to match.
return Intrinsic::x86_xop_vpcomned; // "__builtin_ia32_
vpcomned"
case 'q': // 1 string to match.
return Intrinsic::x86_xop_vpcomneq; // "__builtin_ia32_
vpcomneq"
case 'w': // 1 string to match.
return Intrinsic::x86_xop_vpcomnew; // "__builtin_ia32_
vpcomnew"
}
break;
} }
break; break;
case 'h': // 9 strings to match. }
switch (BuiltinName[18]) { break;
case 'C': // 12 strings to match.
switch (BuiltinName[19]) {
default: break;
case '2': // 6 strings to match.
if (BuiltinName[20] != '_')
break;
switch (BuiltinName[21]) {
default: break; default: break;
case 'a': // 6 strings to match. case 'b': // 2 strings to match.
if (BuiltinName.substr(19, 2) != "dd") if (memcmp(BuiltinName.data()+22, "its", 3))
break; break;
switch (BuiltinName[21]) { switch (BuiltinName[25]) {
default: break; default: break;
case 'b': // 3 strings to match. case 'c': // 1 string to match.
switch (BuiltinName[22]) { if (memcmp(BuiltinName.data()+26, "lr", 2))
default: break;
case 'd': // 1 string to match.
return Intrinsic::x86_xop_vphaddbd; // "__builtin_ia32_
vphaddbd"
case 'q': // 1 string to match.
return Intrinsic::x86_xop_vphaddbq; // "__builtin_ia32_
vphaddbq"
case 'w': // 1 string to match.
return Intrinsic::x86_xop_vphaddbw; // "__builtin_ia32_
vphaddbw"
}
break;
case 'd': // 1 string to match.
if (BuiltinName[22] != 'q')
break; break;
return Intrinsic::x86_xop_vphadddq; // "__builtin_ia32_ return Intrinsic::hexagon_C2_bitsclr; // "__builtin_HEXAG
vphadddq" ON_C2_bitsclr"
case 'w': // 2 strings to match. case 's': // 1 string to match.
switch (BuiltinName[22]) { if (memcmp(BuiltinName.data()+26, "et", 2))
default: break; break;
case 'd': // 1 string to match. return Intrinsic::hexagon_C2_bitsset; // "__builtin_HEXAG
return Intrinsic::x86_xop_vphaddwd; // "__builtin_ia32_ ON_C2_bitsset"
vphaddwd"
case 'q': // 1 string to match.
return Intrinsic::x86_xop_vphaddwq; // "__builtin_ia32_
vphaddwq"
}
break;
} }
break; break;
case 's': // 3 strings to match. case 'c': // 3 strings to match.
if (BuiltinName.substr(19, 2) != "ub") if (memcmp(BuiltinName.data()+22, "mpg", 3))
break; break;
switch (BuiltinName[21]) { switch (BuiltinName[25]) {
default: break; default: break;
case 'b': // 1 string to match. case 'e': // 1 string to match.
if (BuiltinName[22] != 'w') if (memcmp(BuiltinName.data()+26, "ui", 2))
break;
return Intrinsic::x86_xop_vphsubbw; // "__builtin_ia32_
vphsubbw"
case 'd': // 1 string to match.
if (BuiltinName[22] != 'q')
break; break;
return Intrinsic::x86_xop_vphsubdq; // "__builtin_ia32_ return Intrinsic::hexagon_C2_cmpgeui; // "__builtin_HEXAG
vphsubdq" ON_C2_cmpgeui"
case 'w': // 1 string to match. case 't': // 2 strings to match.
if (BuiltinName[22] != 'd') if (BuiltinName[26] != 'u')
break; break;
return Intrinsic::x86_xop_vphsubwd; // "__builtin_ia32_ switch (BuiltinName[27]) {
vphsubwd" default: break;
case 'i': // 1 string to match.
return Intrinsic::hexagon_C2_cmpgtui; // "__builtin_HEXAG
ON_C2_cmpgtui"
case 'p': // 1 string to match.
return Intrinsic::hexagon_C2_cmpgtup; // "__builtin_HEXAG
ON_C2_cmpgtup"
}
break;
} }
break; break;
case 'v': // 1 string to match.
if (memcmp(BuiltinName.data()+22, "itpack", 6))
break;
return Intrinsic::hexagon_C2_vitpack; // "__builtin_HEXAG
ON_C2_vitpack"
} }
break; break;
case 'm': // 3 strings to match. case '4': // 6 strings to match.
if (BuiltinName.substr(18, 3) != "acs") if (BuiltinName[20] != '_')
break; break;
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case 'd': // 1 string to match. case 'a': // 2 strings to match.
if (BuiltinName[22] != 'd') if (memcmp(BuiltinName.data()+22, "nd_", 3))
break; break;
return Intrinsic::x86_xop_vpmacsdd; // "__builtin_ia32_vpmacsdd switch (BuiltinName[25]) {
"
case 'w': // 2 strings to match.
switch (BuiltinName[22]) {
default: break; default: break;
case 'd': // 1 string to match. case 'a': // 1 string to match.
return Intrinsic::x86_xop_vpmacswd; // "__builtin_ia32_ if (memcmp(BuiltinName.data()+26, "nd", 2))
vpmacswd" break;
case 'w': // 1 string to match. return Intrinsic::hexagon_C4_and_and; // "__builtin_HEXAG
return Intrinsic::x86_xop_vpmacsww; // "__builtin_ia32_ ON_C4_and_and"
vpmacsww" case 'o': // 1 string to match.
if (memcmp(BuiltinName.data()+26, "rn", 2))
break;
return Intrinsic::hexagon_C4_and_orn; // "__builtin_HEXAG
ON_C4_and_orn"
}
break;
case 'c': // 3 strings to match.
if (memcmp(BuiltinName.data()+22, "mp", 2))
break;
switch (BuiltinName[24]) {
default: break;
case 'l': // 2 strings to match.
if (memcmp(BuiltinName.data()+25, "te", 2))
break;
switch (BuiltinName[27]) {
default: break;
case 'i': // 1 string to match.
return Intrinsic::hexagon_C4_cmpltei; // "__builtin_HEXAG
ON_C4_cmpltei"
case 'u': // 1 string to match.
return Intrinsic::hexagon_C4_cmplteu; // "__builtin_HEXAG
ON_C4_cmplteu"
}
break;
case 'n': // 1 string to match.
if (memcmp(BuiltinName.data()+25, "eqi", 3))
break;
return Intrinsic::hexagon_C4_cmpneqi; // "__builtin_HEXAG
ON_C4_cmpneqi"
} }
break; break;
case 'o': // 1 string to match.
if (memcmp(BuiltinName.data()+22, "r_andn", 6))
break;
return Intrinsic::hexagon_C4_or_andn; // "__builtin_HEXAG
ON_C4_or_andn"
} }
break; break;
} }
break; break;
case 's': // 1 string to match. case 'F': // 14 strings to match.
if (BuiltinName.substr(11, 12) != "tack_restore") if (memcmp(BuiltinName.data()+19, "2_", 2))
break;
return Intrinsic::stackrestore; // "__builtin_stack_restore"
}
break;
case 24: // 36 strings to match.
if (BuiltinName.substr(0, 17) != "__builtin_ia32_vp")
break;
switch (BuiltinName[17]) {
default: break;
case 'c': // 24 strings to match.
if (BuiltinName.substr(18, 2) != "om")
break; break;
switch (BuiltinName[20]) { switch (BuiltinName[21]) {
default: break; default: break;
case 'e': // 4 strings to match. case 'd': // 7 strings to match.
if (BuiltinName.substr(21, 2) != "qu") if (BuiltinName[22] != 'f')
break; break;
switch (BuiltinName[23]) { switch (BuiltinName[23]) {
default: break; default: break;
case 'b': // 1 string to match. case 'c': // 5 strings to match.
return Intrinsic::x86_xop_vpcomequb; // "__builtin_ia32_vpcomequ switch (BuiltinName[24]) {
b"
case 'd': // 1 string to match.
return Intrinsic::x86_xop_vpcomequd; // "__builtin_ia32_vpcomequ
d"
case 'q': // 1 string to match.
return Intrinsic::x86_xop_vpcomequq; // "__builtin_ia32_vpcomequ
q"
case 'w': // 1 string to match.
return Intrinsic::x86_xop_vpcomequw; // "__builtin_ia32_vpcomequ
w"
}
break;
case 'g': // 8 strings to match.
switch (BuiltinName[21]) {
default: break;
case 'e': // 4 strings to match.
if (BuiltinName[22] != 'u')
break;
switch (BuiltinName[23]) {
default: break; default: break;
case 'b': // 1 string to match. case 'l': // 1 string to match.
return Intrinsic::x86_xop_vpcomgeub; // "__builtin_ia32_ if (memcmp(BuiltinName.data()+25, "ass", 3))
vpcomgeub" break;
case 'd': // 1 string to match. return Intrinsic::hexagon_F2_dfclass; // "__builtin_HEXAG
return Intrinsic::x86_xop_vpcomgeud; // "__builtin_ia32_ ON_F2_dfclass"
vpcomgeud" case 'm': // 4 strings to match.
case 'q': // 1 string to match. if (BuiltinName[25] != 'p')
return Intrinsic::x86_xop_vpcomgeuq; // "__builtin_ia32_ break;
vpcomgeuq" switch (BuiltinName[26]) {
case 'w': // 1 string to match. default: break;
return Intrinsic::x86_xop_vpcomgeuw; // "__builtin_ia32_ case 'e': // 1 string to match.
vpcomgeuw" if (BuiltinName[27] != 'q')
break;
return Intrinsic::hexagon_F2_dfcmpeq; // "__builtin_HEXAG
ON_F2_dfcmpeq"
case 'g': // 2 strings to match.
switch (BuiltinName[27]) {
default: break;
case 'e': // 1 string to match.
return Intrinsic::hexagon_F2_dfcmpge; // "__builtin_HEXAG
ON_F2_dfcmpge"
case 't': // 1 string to match.
return Intrinsic::hexagon_F2_dfcmpgt; // "__builtin_HEXAG
ON_F2_dfcmpgt"
}
break;
case 'u': // 1 string to match.
if (BuiltinName[27] != 'o')
break;
return Intrinsic::hexagon_F2_dfcmpuo; // "__builtin_HEXAG
ON_F2_dfcmpuo"
}
break;
} }
break; break;
case 't': // 4 strings to match. case 'i': // 2 strings to match.
if (BuiltinName[22] != 'u') if (memcmp(BuiltinName.data()+24, "mm_", 3))
break; break;
switch (BuiltinName[23]) { switch (BuiltinName[27]) {
default: break; default: break;
case 'b': // 1 string to match. case 'n': // 1 string to match.
return Intrinsic::x86_xop_vpcomgtub; // "__builtin_ia32_ return Intrinsic::hexagon_F2_dfimm_n; // "__builtin_HEXAG
vpcomgtub" ON_F2_dfimm_n"
case 'd': // 1 string to match. case 'p': // 1 string to match.
return Intrinsic::x86_xop_vpcomgtud; // "__builtin_ia32_ return Intrinsic::hexagon_F2_dfimm_p; // "__builtin_HEXAG
vpcomgtud" ON_F2_dfimm_p"
case 'q': // 1 string to match.
return Intrinsic::x86_xop_vpcomgtuq; // "__builtin_ia32_
vpcomgtuq"
case 'w': // 1 string to match.
return Intrinsic::x86_xop_vpcomgtuw; // "__builtin_ia32_
vpcomgtuw"
} }
break; break;
} }
break; break;
case 'l': // 8 strings to match. case 's': // 7 strings to match.
switch (BuiltinName[21]) { if (BuiltinName[22] != 'f')
break;
switch (BuiltinName[23]) {
default: break; default: break;
case 'e': // 4 strings to match. case 'c': // 5 strings to match.
if (BuiltinName[22] != 'u') switch (BuiltinName[24]) {
break;
switch (BuiltinName[23]) {
default: break; default: break;
case 'b': // 1 string to match. case 'l': // 1 string to match.
return Intrinsic::x86_xop_vpcomleub; // "__builtin_ia32_ if (memcmp(BuiltinName.data()+25, "ass", 3))
vpcomleub" break;
case 'd': // 1 string to match. return Intrinsic::hexagon_F2_sfclass; // "__builtin_HEXAG
return Intrinsic::x86_xop_vpcomleud; // "__builtin_ia32_ ON_F2_sfclass"
vpcomleud" case 'm': // 4 strings to match.
case 'q': // 1 string to match. if (BuiltinName[25] != 'p')
return Intrinsic::x86_xop_vpcomleuq; // "__builtin_ia32_ break;
vpcomleuq" switch (BuiltinName[26]) {
case 'w': // 1 string to match. default: break;
return Intrinsic::x86_xop_vpcomleuw; // "__builtin_ia32_ case 'e': // 1 string to match.
vpcomleuw" if (BuiltinName[27] != 'q')
break;
return Intrinsic::hexagon_F2_sfcmpeq; // "__builtin_HEXAG
ON_F2_sfcmpeq"
case 'g': // 2 strings to match.
switch (BuiltinName[27]) {
default: break;
case 'e': // 1 string to match.
return Intrinsic::hexagon_F2_sfcmpge; // "__builtin_HEXAG
ON_F2_sfcmpge"
case 't': // 1 string to match.
return Intrinsic::hexagon_F2_sfcmpgt; // "__builtin_HEXAG
ON_F2_sfcmpgt"
}
break;
case 'u': // 1 string to match.
if (BuiltinName[27] != 'o')
break;
return Intrinsic::hexagon_F2_sfcmpuo; // "__builtin_HEXAG
ON_F2_sfcmpuo"
}
break;
} }
break; break;
case 't': // 4 strings to match. case 'i': // 2 strings to match.
if (BuiltinName[22] != 'u') if (memcmp(BuiltinName.data()+24, "mm_", 3))
break; break;
switch (BuiltinName[23]) { switch (BuiltinName[27]) {
default: break; default: break;
case 'b': // 1 string to match. case 'n': // 1 string to match.
return Intrinsic::x86_xop_vpcomltub; // "__builtin_ia32_ return Intrinsic::hexagon_F2_sfimm_n; // "__builtin_HEXAG
vpcomltub" ON_F2_sfimm_n"
case 'd': // 1 string to match. case 'p': // 1 string to match.
return Intrinsic::x86_xop_vpcomltud; // "__builtin_ia32_ return Intrinsic::hexagon_F2_sfimm_p; // "__builtin_HEXAG
vpcomltud" ON_F2_sfimm_p"
case 'q': // 1 string to match.
return Intrinsic::x86_xop_vpcomltuq; // "__builtin_ia32_
vpcomltuq"
case 'w': // 1 string to match.
return Intrinsic::x86_xop_vpcomltuw; // "__builtin_ia32_
vpcomltuw"
} }
break; break;
} }
break; break;
case 'n': // 4 strings to match.
if (BuiltinName.substr(21, 2) != "eu")
break;
switch (BuiltinName[23]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::x86_xop_vpcomneub; // "__builtin_ia32_vpcomneu
b"
case 'd': // 1 string to match.
return Intrinsic::x86_xop_vpcomneud; // "__builtin_ia32_vpcomneu
d"
case 'q': // 1 string to match.
return Intrinsic::x86_xop_vpcomneuq; // "__builtin_ia32_vpcomneu
q"
case 'w': // 1 string to match.
return Intrinsic::x86_xop_vpcomneuw; // "__builtin_ia32_vpcomneu
w"
}
break;
} }
break; break;
case 'h': // 6 strings to match. case 'M': // 11 strings to match.
if (BuiltinName.substr(18, 4) != "addu") switch (BuiltinName[19]) {
break;
switch (BuiltinName[22]) {
default: break; default: break;
case 'b': // 3 strings to match. case '2': // 3 strings to match.
switch (BuiltinName[23]) { if (BuiltinName[20] != '_')
break;
switch (BuiltinName[21]) {
default: break; default: break;
case 'd': // 1 string to match. case 'm': // 1 string to match.
return Intrinsic::x86_xop_vphaddubd; // "__builtin_ia32_vphaddub if (memcmp(BuiltinName.data()+22, "pyu_up", 6))
d" break;
case 'q': // 1 string to match. return Intrinsic::hexagon_M2_mpyu_up; // "__builtin_HEXAG
return Intrinsic::x86_xop_vphaddubq; // "__builtin_ia32_vphaddub ON_M2_mpyu_up"
q" case 'v': // 2 strings to match.
case 'w': // 1 string to match. switch (BuiltinName[22]) {
return Intrinsic::x86_xop_vphaddubw; // "__builtin_ia32_vphaddub default: break;
w" case 'm': // 1 string to match.
if (memcmp(BuiltinName.data()+23, "ac2es", 5))
break;
return Intrinsic::hexagon_M2_vmac2es; // "__builtin_HEXAG
ON_M2_vmac2es"
case 'r': // 1 string to match.
if (memcmp(BuiltinName.data()+23, "adduh", 5))
break;
return Intrinsic::hexagon_M2_vradduh; // "__builtin_HEXAG
ON_M2_vradduh"
}
break;
} }
break; break;
case 'd': // 1 string to match. case '4': // 4 strings to match.
if (BuiltinName[23] != 'q') if (BuiltinName[20] != '_')
break; break;
return Intrinsic::x86_xop_vphaddudq; // "__builtin_ia32_vphaddud switch (BuiltinName[21]) {
q"
case 'w': // 2 strings to match.
switch (BuiltinName[23]) {
default: break; default: break;
case 'd': // 1 string to match. case 'a': // 2 strings to match.
return Intrinsic::x86_xop_vphadduwd; // "__builtin_ia32_vphadduw if (memcmp(BuiltinName.data()+22, "nd_", 3))
d" break;
case 'q': // 1 string to match. switch (BuiltinName[25]) {
return Intrinsic::x86_xop_vphadduwq; // "__builtin_ia32_vphadduw default: break;
q" case 'a': // 1 string to match.
if (memcmp(BuiltinName.data()+26, "nd", 2))
break;
return Intrinsic::hexagon_M4_and_and; // "__builtin_HEXAG
ON_M4_and_and"
case 'x': // 1 string to match.
if (memcmp(BuiltinName.data()+26, "or", 2))
break;
return Intrinsic::hexagon_M4_and_xor; // "__builtin_HEXAG
ON_M4_and_xor"
}
break;
case 'o': // 1 string to match.
if (memcmp(BuiltinName.data()+22, "r_andn", 6))
break;
return Intrinsic::hexagon_M4_or_andn; // "__builtin_HEXAG
ON_M4_or_andn"
case 'x': // 1 string to match.
if (memcmp(BuiltinName.data()+22, "or_and", 6))
break;
return Intrinsic::hexagon_M4_xor_and; // "__builtin_HEXAG
ON_M4_xor_and"
} }
break; break;
} case '5': // 4 strings to match.
break; if (memcmp(BuiltinName.data()+20, "_vm", 3))
case 'm': // 6 strings to match.
if (BuiltinName[18] != 'a')
break;
switch (BuiltinName[19]) {
default: break;
case 'c': // 5 strings to match.
if (BuiltinName[20] != 's')
break; break;
switch (BuiltinName[21]) { switch (BuiltinName[23]) {
default: break; default: break;
case 'd': // 2 strings to match. case 'a': // 2 strings to match.
if (BuiltinName[22] != 'q') if (memcmp(BuiltinName.data()+24, "cb", 2))
break; break;
switch (BuiltinName[23]) { switch (BuiltinName[26]) {
default: break; default: break;
case 'h': // 1 string to match. case 's': // 1 string to match.
return Intrinsic::x86_xop_vpmacsdqh; // "__builtin_ia32_ if (BuiltinName[27] != 'u')
vpmacsdqh" break;
case 'l': // 1 string to match. return Intrinsic::hexagon_M5_vmacbsu; // "__builtin_HEXAG
return Intrinsic::x86_xop_vpmacsdql; // "__builtin_ia32_ ON_M5_vmacbsu"
vpmacsdql" case 'u': // 1 string to match.
if (BuiltinName[27] != 'u')
break;
return Intrinsic::hexagon_M5_vmacbuu; // "__builtin_HEXAG
ON_M5_vmacbuu"
} }
break; break;
case 's': // 3 strings to match. case 'p': // 2 strings to match.
switch (BuiltinName[22]) { if (memcmp(BuiltinName.data()+24, "yb", 2))
break;
switch (BuiltinName[26]) {
default: break; default: break;
case 'd': // 1 string to match. case 's': // 1 string to match.
if (BuiltinName[23] != 'd') if (BuiltinName[27] != 'u')
break; break;
return Intrinsic::x86_xop_vpmacssdd; // "__builtin_ia32_ return Intrinsic::hexagon_M5_vmpybsu; // "__builtin_HEXAG
vpmacssdd" ON_M5_vmpybsu"
case 'w': // 2 strings to match. case 'u': // 1 string to match.
switch (BuiltinName[23]) { if (BuiltinName[27] != 'u')
default: break; break;
case 'd': // 1 string to match. return Intrinsic::hexagon_M5_vmpybuu; // "__builtin_HEXAG
return Intrinsic::x86_xop_vpmacsswd; // "__builtin_ia32_ ON_M5_vmpybuu"
vpmacsswd"
case 'w': // 1 string to match.
return Intrinsic::x86_xop_vpmacssww; // "__builtin_ia32_
vpmacssww"
}
break;
} }
break; break;
} }
break; break;
case 'd': // 1 string to match.
if (BuiltinName.substr(20, 4) != "cswd")
break;
return Intrinsic::x86_xop_vpmadcswd; // "__builtin_ia32_vpmadcsw
d"
} }
break; break;
} case 'S': // 30 strings to match.
break; switch (BuiltinName[19]) {
case 25: // 13 strings to match.
if (BuiltinName.substr(0, 11) != "__builtin_i")
break;
switch (BuiltinName[11]) {
default: break;
case 'a': // 12 strings to match.
if (BuiltinName.substr(12, 4) != "32_v")
break;
switch (BuiltinName[16]) {
default: break; default: break;
case 'f': // 2 strings to match. case '2': // 25 strings to match.
if (BuiltinName.substr(17, 4) != "rczp") if (BuiltinName[20] != '_')
break; break;
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case 'd': // 1 string to match. case 'a': // 8 strings to match.
if (BuiltinName.substr(22, 3) != "256") if (BuiltinName[22] != 's')
break;
return Intrinsic::x86_xop_vfrcz_pd_256; // "__builtin_ia32_
vfrczpd256"
case 's': // 1 string to match.
if (BuiltinName.substr(22, 3) != "256")
break; break;
return Intrinsic::x86_xop_vfrcz_ps_256; // "__builtin_ia32_ switch (BuiltinName[23]) {
vfrczps256"
}
break;
case 'p': // 10 strings to match.
switch (BuiltinName[17]) {
default: break;
case 'c': // 5 strings to match.
switch (BuiltinName[18]) {
default: break; default: break;
case 'm': // 1 string to match. case 'l': // 4 strings to match.
if (BuiltinName.substr(19, 6) != "ov_256") if (BuiltinName[24] != '_')
break; break;
return Intrinsic::x86_xop_vpcmov_256; // "__builtin_ia32_ switch (BuiltinName[25]) {
vpcmov_256" default: break;
case 'o': // 4 strings to match. case 'i': // 2 strings to match.
if (BuiltinName.substr(19, 5) != "mtrue") if (BuiltinName[26] != '_')
break;
switch (BuiltinName[27]) {
default: break;
case 'p': // 1 string to match.
return Intrinsic::hexagon_S2_asl_i_p; // "__builtin_HEXAG
ON_S2_asl_i_p"
case 'r': // 1 string to match.
return Intrinsic::hexagon_S2_asl_i_r; // "__builtin_HEXAG
ON_S2_asl_i_r"
}
break; break;
switch (BuiltinName[24]) { case 'r': // 2 strings to match.
if (BuiltinName[26] != '_')
break;
switch (BuiltinName[27]) {
default: break;
case 'p': // 1 string to match.
return Intrinsic::hexagon_S2_asl_r_p; // "__builtin_HEXAG
ON_S2_asl_r_p"
case 'r': // 1 string to match.
return Intrinsic::hexagon_S2_asl_r_r; // "__builtin_HEXAG
ON_S2_asl_r_r"
}
break;
}
break;
case 'r': // 4 strings to match.
if (BuiltinName[24] != '_')
break;
switch (BuiltinName[25]) {
default: break; default: break;
case 'b': // 1 string to match. case 'i': // 2 strings to match.
return Intrinsic::x86_xop_vpcomtrueb; // "__builtin_ia32_ if (BuiltinName[26] != '_')
vpcomtrueb" break;
case 'd': // 1 string to match. switch (BuiltinName[27]) {
return Intrinsic::x86_xop_vpcomtrued; // "__builtin_ia32_ default: break;
vpcomtrued" case 'p': // 1 string to match.
case 'q': // 1 string to match. return Intrinsic::hexagon_S2_asr_i_p; // "__builtin_HEXAG
return Intrinsic::x86_xop_vpcomtrueq; // "__builtin_ia32_ ON_S2_asr_i_p"
vpcomtrueq" case 'r': // 1 string to match.
case 'w': // 1 string to match. return Intrinsic::hexagon_S2_asr_i_r; // "__builtin_HEXAG
return Intrinsic::x86_xop_vpcomtruew; // "__builtin_ia32_ ON_S2_asr_i_r"
vpcomtruew" }
break;
case 'r': // 2 strings to match.
if (BuiltinName[26] != '_')
break;
switch (BuiltinName[27]) {
default: break;
case 'p': // 1 string to match.
return Intrinsic::hexagon_S2_asr_r_p; // "__builtin_HEXAG
ON_S2_asr_r_p"
case 'r': // 1 string to match.
return Intrinsic::hexagon_S2_asr_r_r; // "__builtin_HEXAG
ON_S2_asr_r_r"
}
break;
} }
break; break;
} }
break; break;
case 'e': // 2 strings to match. case 'c': // 1 string to match.
if (BuiltinName.substr(18, 6) != "rmil2p") if (memcmp(BuiltinName.data()+22, "lbnorm", 6))
break; break;
switch (BuiltinName[24]) { return Intrinsic::hexagon_S2_clbnorm; // "__builtin_HEXAG
ON_S2_clbnorm"
case 'i': // 1 string to match.
if (memcmp(BuiltinName.data()+22, "nsertp", 6))
break;
return Intrinsic::hexagon_S2_insertp; // "__builtin_HEXAG
ON_S2_insertp"
case 'l': // 6 strings to match.
if (BuiltinName[22] != 's')
break;
switch (BuiltinName[23]) {
default: break; default: break;
case 'd': // 1 string to match. case 'l': // 2 strings to match.
return Intrinsic::x86_xop_vpermil2pd; // "__builtin_ia32_ if (memcmp(BuiltinName.data()+24, "_r_", 3))
vpermil2pd" break;
case 's': // 1 string to match. switch (BuiltinName[27]) {
return Intrinsic::x86_xop_vpermil2ps; // "__builtin_ia32_ default: break;
vpermil2ps" case 'p': // 1 string to match.
return Intrinsic::hexagon_S2_lsl_r_p; // "__builtin_HEXAG
ON_S2_lsl_r_p"
case 'r': // 1 string to match.
return Intrinsic::hexagon_S2_lsl_r_r; // "__builtin_HEXAG
ON_S2_lsl_r_r"
}
break;
case 'r': // 4 strings to match.
if (BuiltinName[24] != '_')
break;
switch (BuiltinName[25]) {
default: break;
case 'i': // 2 strings to match.
if (BuiltinName[26] != '_')
break;
switch (BuiltinName[27]) {
default: break;
case 'p': // 1 string to match.
return Intrinsic::hexagon_S2_lsr_i_p; // "__builtin_HEXAG
ON_S2_lsr_i_p"
case 'r': // 1 string to match.
return Intrinsic::hexagon_S2_lsr_i_r; // "__builtin_HEXAG
ON_S2_lsr_i_r"
}
break;
case 'r': // 2 strings to match.
if (BuiltinName[26] != '_')
break;
switch (BuiltinName[27]) {
default: break;
case 'p': // 1 string to match.
return Intrinsic::hexagon_S2_lsr_r_p; // "__builtin_HEXAG
ON_S2_lsr_r_p"
case 'r': // 1 string to match.
return Intrinsic::hexagon_S2_lsr_r_r; // "__builtin_HEXAG
ON_S2_lsr_r_r"
}
break;
}
break;
} }
break; break;
case 'm': // 3 strings to match. case 'p': // 1 string to match.
if (BuiltinName[18] != 'a') if (memcmp(BuiltinName.data()+22, "arityp", 6))
break; break;
switch (BuiltinName[19]) { return Intrinsic::hexagon_S2_parityp; // "__builtin_HEXAG
ON_S2_parityp"
case 's': // 5 strings to match.
switch (BuiltinName[22]) {
default: break; default: break;
case 'c': // 2 strings to match. case 'h': // 4 strings to match.
if (BuiltinName.substr(20, 4) != "ssdq") if (memcmp(BuiltinName.data()+23, "uff", 3))
break; break;
switch (BuiltinName[24]) { switch (BuiltinName[26]) {
default: break; default: break;
case 'h': // 1 string to match. case 'e': // 2 strings to match.
return Intrinsic::x86_xop_vpmacssdqh; // "__builtin_ia32_ switch (BuiltinName[27]) {
vpmacssdqh" default: break;
case 'l': // 1 string to match. case 'b': // 1 string to match.
return Intrinsic::x86_xop_vpmacssdql; // "__builtin_ia32_ return Intrinsic::hexagon_S2_shuffeb; // "__builtin_HEXAG
vpmacssdql" ON_S2_shuffeb"
case 'h': // 1 string to match.
return Intrinsic::hexagon_S2_shuffeh; // "__builtin_HEXAG
ON_S2_shuffeh"
}
break;
case 'o': // 2 strings to match.
switch (BuiltinName[27]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::hexagon_S2_shuffob; // "__builtin_HEXAG
ON_S2_shuffob"
case 'h': // 1 string to match.
return Intrinsic::hexagon_S2_shuffoh; // "__builtin_HEXAG
ON_S2_shuffoh"
}
break;
} }
break; break;
case 'd': // 1 string to match. case 'v': // 1 string to match.
if (BuiltinName.substr(20, 5) != "csswd") if (memcmp(BuiltinName.data()+23, "sathb", 5))
break; break;
return Intrinsic::x86_xop_vpmadcsswd; // "__builtin_ia32_ vpmadcsswd" return Intrinsic::hexagon_S2_svsathb; // "__builtin_HEXAG ON_S2_svsathb"
} }
break; break;
} case 'v': // 3 strings to match.
break; switch (BuiltinName[22]) {
} default: break;
break; case 'r': // 1 string to match.
case 'n': // 1 string to match. if (memcmp(BuiltinName.data()+23, "cnegh", 5))
if (BuiltinName.substr(12, 13) != "it_trampoline") break;
break; return Intrinsic::hexagon_S2_vrcnegh; // "__builtin_HEXAG
return Intrinsic::init_trampoline; // "__builtin_init_trampoli ON_S2_vrcnegh"
ne" case 's': // 2 strings to match.
} if (memcmp(BuiltinName.data()+23, "at", 2))
break; break;
case 26: // 8 strings to match. switch (BuiltinName[25]) {
if (BuiltinName.substr(0, 20) != "__builtin_ia32_vpcom") default: break;
break; case 'h': // 1 string to match.
switch (BuiltinName[20]) { if (memcmp(BuiltinName.data()+26, "ub", 2))
default: break; break;
case 'f': // 4 strings to match. return Intrinsic::hexagon_S2_vsathub; // "__builtin_HEXAG
if (BuiltinName.substr(21, 4) != "alse") ON_S2_vsathub"
break; case 'w': // 1 string to match.
switch (BuiltinName[25]) { if (memcmp(BuiltinName.data()+26, "uh", 2))
default: break; break;
case 'b': // 1 string to match. return Intrinsic::hexagon_S2_vsatwuh; // "__builtin_HEXAG
return Intrinsic::x86_xop_vpcomfalseb; // "__builtin_ia32_vpcomfal ON_S2_vsatwuh"
seb" }
case 'd': // 1 string to match. break;
return Intrinsic::x86_xop_vpcomfalsed; // "__builtin_ia32_vpcomfal }
sed"
case 'q': // 1 string to match.
return Intrinsic::x86_xop_vpcomfalseq; // "__builtin_ia32_vpcomfal
seq"
case 'w': // 1 string to match.
return Intrinsic::x86_xop_vpcomfalsew; // "__builtin_ia32_vpcomfal
sew"
}
break;
case 't': // 4 strings to match.
if (BuiltinName.substr(21, 4) != "rueu")
break;
switch (BuiltinName[25]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::x86_xop_vpcomtrueub; // "__builtin_ia32_vpcomtru
eub"
case 'd': // 1 string to match.
return Intrinsic::x86_xop_vpcomtrueud; // "__builtin_ia32_vpcomtru
eud"
case 'q': // 1 string to match.
return Intrinsic::x86_xop_vpcomtrueuq; // "__builtin_ia32_vpcomtru
euq"
case 'w': // 1 string to match.
return Intrinsic::x86_xop_vpcomtrueuw; // "__builtin_ia32_vpcomtru
euw"
}
break;
}
break;
case 27: // 5 strings to match.
if (BuiltinName.substr(0, 10) != "__builtin_")
break;
switch (BuiltinName[10]) {
default: break;
case 'a': // 1 string to match.
if (BuiltinName.substr(11, 16) != "djust_trampoline")
break;
return Intrinsic::adjust_trampoline; // "__builtin_adjust_trampo
line"
case 'i': // 4 strings to match.
if (BuiltinName.substr(11, 15) != "a32_vpcomfalseu")
break;
switch (BuiltinName[26]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::x86_xop_vpcomfalseub; // "__builtin_ia32_
vpcomfalseub"
case 'd': // 1 string to match.
return Intrinsic::x86_xop_vpcomfalseud; // "__builtin_ia32_
vpcomfalseud"
case 'q': // 1 string to match.
return Intrinsic::x86_xop_vpcomfalseuq; // "__builtin_ia32_
vpcomfalseuq"
case 'w': // 1 string to match.
return Intrinsic::x86_xop_vpcomfalseuw; // "__builtin_ia32_
vpcomfalseuw"
}
break;
}
break;
case 28: // 2 strings to match.
if (BuiltinName.substr(0, 24) != "__builtin_ia32_vpermil2p")
break;
switch (BuiltinName[24]) {
default: break;
case 'd': // 1 string to match.
if (BuiltinName.substr(25, 3) != "256")
break;
return Intrinsic::x86_xop_vpermil2pd_256; // "__builtin_ia32_
vpermil2pd256"
case 's': // 1 string to match.
if (BuiltinName.substr(25, 3) != "256")
break;
return Intrinsic::x86_xop_vpermil2ps_256; // "__builtin_ia32_
vpermil2ps256"
}
break;
}
}
if (TargetPrefix == "arm") {
switch (BuiltinName.size()) {
default: break;
case 17: // 3 strings to match.
if (BuiltinName.substr(0, 14) != "__builtin_arm_")
break;
switch (BuiltinName[14]) {
default: break;
case 'c': // 1 string to match.
if (BuiltinName.substr(15, 2) != "dp")
break;
return Intrinsic::arm_cdp; // "__builtin_arm_cdp"
case 'm': // 2 strings to match.
switch (BuiltinName[15]) {
default: break;
case 'c': // 1 string to match.
if (BuiltinName[16] != 'r')
break;
return Intrinsic::arm_mcr; // "__builtin_arm_mcr"
case 'r': // 1 string to match.
if (BuiltinName[16] != 'c')
break; break;
return Intrinsic::arm_mrc; // "__builtin_arm_mrc" }
}
break;
}
break;
case 18: // 8 strings to match.
if (BuiltinName.substr(0, 14) != "__builtin_arm_")
break;
switch (BuiltinName[14]) {
default: break;
case 'c': // 1 string to match.
if (BuiltinName.substr(15, 3) != "dp2")
break; break;
return Intrinsic::arm_cdp2; // "__builtin_arm_cdp2" case '4': // 5 strings to match.
case 'm': // 3 strings to match. if (BuiltinName[20] != '_')
switch (BuiltinName[15]) {
default: break;
case 'c': // 2 strings to match.
if (BuiltinName[16] != 'r')
break; break;
switch (BuiltinName[17]) { switch (BuiltinName[21]) {
default: break; default: break;
case '2': // 1 string to match. case 'a': // 1 string to match.
return Intrinsic::arm_mcr2; // "__builtin_arm_mcr2" if (memcmp(BuiltinName.data()+22, "ddaddi", 6))
case 'r': // 1 string to match. break;
return Intrinsic::arm_mcrr; // "__builtin_arm_mcrr" return Intrinsic::hexagon_S4_addaddi; // "__builtin_HEXAG
ON_S4_addaddi"
case 'c': // 1 string to match.
if (memcmp(BuiltinName.data()+22, "lbaddi", 6))
break;
return Intrinsic::hexagon_S4_clbaddi; // "__builtin_HEXAG
ON_S4_clbaddi"
case 'e': // 1 string to match.
if (memcmp(BuiltinName.data()+22, "xtract", 6))
break;
return Intrinsic::hexagon_S4_extract; // "__builtin_HEXAG
ON_S4_extract"
case 'o': // 1 string to match.
if (memcmp(BuiltinName.data()+22, "r_andi", 6))
break;
return Intrinsic::hexagon_S4_or_andi; // "__builtin_HEXAG
ON_S4_or_andi"
case 's': // 1 string to match.
if (memcmp(BuiltinName.data()+22, "ubaddi", 6))
break;
return Intrinsic::hexagon_S4_subaddi; // "__builtin_HEXAG
ON_S4_subaddi"
} }
break; break;
case 'r': // 1 string to match.
if (BuiltinName.substr(16, 2) != "c2")
break;
return Intrinsic::arm_mrc2; // "__builtin_arm_mrc2"
}
break;
case 'q': // 2 strings to match.
switch (BuiltinName[15]) {
default: break;
case 'a': // 1 string to match.
if (BuiltinName.substr(16, 2) != "dd")
break;
return Intrinsic::arm_qadd; // "__builtin_arm_qadd"
case 's': // 1 string to match.
if (BuiltinName.substr(16, 2) != "ub")
break;
return Intrinsic::arm_qsub; // "__builtin_arm_qsub"
} }
break; break;
case 's': // 1 string to match.
if (BuiltinName.substr(15, 3) != "sat")
break;
return Intrinsic::arm_ssat; // "__builtin_arm_ssat"
case 'u': // 1 string to match.
if (BuiltinName.substr(15, 3) != "sat")
break;
return Intrinsic::arm_usat; // "__builtin_arm_usat"
}
break;
case 19: // 1 string to match.
if (BuiltinName.substr(0, 19) != "__builtin_arm_mcrr2")
break;
return Intrinsic::arm_mcrr2; // "__builtin_arm_mcrr2"
case 23: // 2 strings to match.
if (BuiltinName.substr(0, 14) != "__builtin_arm_")
break;
switch (BuiltinName[14]) {
default: break;
case 'g': // 1 string to match.
if (BuiltinName.substr(15, 8) != "et_fpscr")
break;
return Intrinsic::arm_get_fpscr; // "__builtin_arm_get_fpscr"
case 's': // 1 string to match.
if (BuiltinName.substr(15, 8) != "et_fpscr")
break;
return Intrinsic::arm_set_fpscr; // "__builtin_arm_set_fpscr"
}
break;
case 24: // 1 string to match.
if (BuiltinName.substr(0, 24) != "__builtin_thread_pointer")
break;
return Intrinsic::arm_thread_pointer; // "__builtin_thread_pointe
r"
}
}
if (TargetPrefix == "hexagon") {
switch (BuiltinName.size()) {
default: break;
case 23: // 2 strings to match.
if (BuiltinName.substr(0, 18) != "__builtin_HEXAGON.")
break;
switch (BuiltinName[18]) {
default: break;
case 'A': // 1 string to match.
if (BuiltinName.substr(19, 4) != "2.or")
break;
return Intrinsic::hexagon_A2_or; // "__builtin_HEXAGON.A2.or"
case 'C': // 1 string to match.
if (BuiltinName.substr(19, 4) != "2.or")
break;
return Intrinsic::hexagon_C2_or; // "__builtin_HEXAGON.C2.or"
} }
break; break;
case 24: // 23 strings to match. case 29: // 103 strings to match.
if (BuiltinName.substr(0, 18) != "__builtin_HEXAGON.") if (memcmp(BuiltinName.data()+0, "__builtin_HEXAGON_", 18))
break; break;
switch (BuiltinName[18]) { switch (BuiltinName[18]) {
default: break; default: break;
case 'A': // 13 strings to match. case 'A': // 26 strings to match.
switch (BuiltinName[19]) { switch (BuiltinName[19]) {
default: break; default: break;
case '2': // 12 strings to match. case '2': // 11 strings to match.
if (BuiltinName[20] != '.') if (BuiltinName[20] != '_')
break; break;
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case 'a': // 3 strings to match. case 'c': // 1 string to match.
switch (BuiltinName[22]) { if (memcmp(BuiltinName.data()+22, "ombinew", 7))
break;
return Intrinsic::hexagon_A2_combinew; // "__builtin_HEXAG
ON_A2_combinew"
case 'r': // 1 string to match.
if (memcmp(BuiltinName.data()+22, "oundsat", 7))
break;
return Intrinsic::hexagon_A2_roundsat; // "__builtin_HEXAG
ON_A2_roundsat"
case 's': // 2 strings to match.
if (BuiltinName[22] != 'v')
break;
switch (BuiltinName[23]) {
default: break; default: break;
case 'b': // 1 string to match. case 'a': // 1 string to match.
if (BuiltinName[23] != 's') if (memcmp(BuiltinName.data()+24, "dduhs", 5))
break;
return Intrinsic::hexagon_A2_abs; // "__builtin_HEXAGON.A2.ab
s"
case 'd': // 1 string to match.
if (BuiltinName[23] != 'd')
break; break;
return Intrinsic::hexagon_A2_add; // "__builtin_HEXAGON.A2.ad return Intrinsic::hexagon_A2_svadduhs; // "__builtin_HEXAG
d" ON_A2_svadduhs"
case 'n': // 1 string to match. case 's': // 1 string to match.
if (BuiltinName[23] != 'd') if (memcmp(BuiltinName.data()+24, "ubuhs", 5))
break; break;
return Intrinsic::hexagon_A2_and; // "__builtin_HEXAGON.A2.an d" return Intrinsic::hexagon_A2_svsubuhs; // "__builtin_HEXAG ON_A2_svsubuhs"
} }
break; break;
case 'm': // 2 strings to match. case 'v': // 7 strings to match.
switch (BuiltinName[22]) { switch (BuiltinName[22]) {
default: break; default: break;
case 'a': // 1 string to match. case 'a': // 2 strings to match.
if (BuiltinName[23] != 'x') if (memcmp(BuiltinName.data()+23, "bs", 2))
break; break;
return Intrinsic::hexagon_A2_max; // "__builtin_HEXAGON.A2.ma switch (BuiltinName[25]) {
x" default: break;
case 'i': // 1 string to match. case 'h': // 1 string to match.
if (BuiltinName[23] != 'n') if (memcmp(BuiltinName.data()+26, "sat", 3))
break;
return Intrinsic::hexagon_A2_vabshsat; // "__builtin_HEXAG
ON_A2_vabshsat"
case 'w': // 1 string to match.
if (memcmp(BuiltinName.data()+26, "sat", 3))
break;
return Intrinsic::hexagon_A2_vabswsat; // "__builtin_HEXAG
ON_A2_vabswsat"
}
break;
case 'c': // 3 strings to match.
if (memcmp(BuiltinName.data()+23, "mp", 2))
break;
switch (BuiltinName[25]) {
default: break;
case 'b': // 1 string to match.
if (memcmp(BuiltinName.data()+26, "gtu", 3))
break;
return Intrinsic::hexagon_A2_vcmpbgtu; // "__builtin_HEXAG
ON_A2_vcmpbgtu"
case 'h': // 1 string to match.
if (memcmp(BuiltinName.data()+26, "gtu", 3))
break;
return Intrinsic::hexagon_A2_vcmphgtu; // "__builtin_HEXAG
ON_A2_vcmphgtu"
case 'w': // 1 string to match.
if (memcmp(BuiltinName.data()+26, "gtu", 3))
break;
return Intrinsic::hexagon_A2_vcmpwgtu; // "__builtin_HEXAG
ON_A2_vcmpwgtu"
}
break;
case 'n': // 2 strings to match.
if (memcmp(BuiltinName.data()+23, "avg", 3))
break; break;
return Intrinsic::hexagon_A2_min; // "__builtin_HEXAGON.A2.mi switch (BuiltinName[26]) {
n" default: break;
case 'h': // 1 string to match.
if (memcmp(BuiltinName.data()+27, "cr", 2))
break;
return Intrinsic::hexagon_A2_vnavghcr; // "__builtin_HEXAG
ON_A2_vnavghcr"
case 'w': // 1 string to match.
if (memcmp(BuiltinName.data()+27, "cr", 2))
break;
return Intrinsic::hexagon_A2_vnavgwcr; // "__builtin_HEXAG
ON_A2_vnavgwcr"
}
break;
} }
break; break;
case 'n': // 2 strings to match. }
switch (BuiltinName[22]) { break;
case '4': // 14 strings to match.
if (BuiltinName[20] != '_')
break;
switch (BuiltinName[21]) {
default: break;
case 'b': // 1 string to match.
if (memcmp(BuiltinName.data()+22, "itsplit", 7))
break;
return Intrinsic::hexagon_A4_bitsplit; // "__builtin_HEXAG
ON_A4_bitsplit"
case 'c': // 2 strings to match.
if (memcmp(BuiltinName.data()+22, "mp", 2))
break;
switch (BuiltinName[24]) {
default: break; default: break;
case 'e': // 1 string to match. case 'b': // 1 string to match.
if (BuiltinName[23] != 'g') if (memcmp(BuiltinName.data()+25, "gtui", 4))
break; break;
return Intrinsic::hexagon_A2_neg; // "__builtin_HEXAGON.A2.ne return Intrinsic::hexagon_A4_cmpbgtui; // "__builtin_HEXAG
g" ON_A4_cmpbgtui"
case 'o': // 1 string to match. case 'h': // 1 string to match.
if (BuiltinName[23] != 't') if (memcmp(BuiltinName.data()+25, "gtui", 4))
break; break;
return Intrinsic::hexagon_A2_not; // "__builtin_HEXAGON.A2.no t" return Intrinsic::hexagon_A4_cmphgtui; // "__builtin_HEXAG ON_A4_cmphgtui"
} }
break; break;
case 'o': // 1 string to match. case 'm': // 1 string to match.
if (BuiltinName.substr(22, 2) != "rp") if (memcmp(BuiltinName.data()+22, "odwrapu", 7))
break; break;
return Intrinsic::hexagon_A2_orp; // "__builtin_HEXAGON.A2.or return Intrinsic::hexagon_A4_modwrapu; // "__builtin_HEXAG
p" ON_A4_modwrapu"
case 's': // 2 strings to match. case 'r': // 3 strings to match.
switch (BuiltinName[22]) { switch (BuiltinName[22]) {
default: break; default: break;
case 'a': // 1 string to match. case 'c': // 1 string to match.
if (BuiltinName[23] != 't') if (memcmp(BuiltinName.data()+23, "mpneqi", 6))
break; break;
return Intrinsic::hexagon_A2_sat; // "__builtin_HEXAGON.A2.sa return Intrinsic::hexagon_A4_rcmpneqi; // "__builtin_HEXAG
t" ON_A4_rcmpneqi"
case 'u': // 1 string to match. case 'o': // 2 strings to match.
if (BuiltinName[23] != 'b') if (memcmp(BuiltinName.data()+23, "und_r", 5))
break; break;
return Intrinsic::hexagon_A2_sub; // "__builtin_HEXAGON.A2.su switch (BuiltinName[28]) {
b" default: break;
case 'i': // 1 string to match.
return Intrinsic::hexagon_A4_round_ri; // "__builtin_HEXAG
ON_A4_round_ri"
case 'r': // 1 string to match.
return Intrinsic::hexagon_A4_round_rr; // "__builtin_HEXAG
ON_A4_round_rr"
}
break;
} }
break; break;
case 't': // 1 string to match. case 't': // 1 string to match.
if (BuiltinName.substr(22, 2) != "fr") if (memcmp(BuiltinName.data()+22, "lbmatch", 7))
break; break;
return Intrinsic::hexagon_A2_tfr; // "__builtin_HEXAGON.A2.tf return Intrinsic::hexagon_A4_tlbmatch; // "__builtin_HEXAG
r" ON_A4_tlbmatch"
case 'x': // 1 string to match. case 'v': // 6 strings to match.
if (BuiltinName.substr(22, 2) != "or") if (memcmp(BuiltinName.data()+22, "cmp", 3))
break;
switch (BuiltinName[25]) {
default: break;
case 'b': // 2 strings to match.
switch (BuiltinName[26]) {
default: break;
case 'e': // 1 string to match.
if (memcmp(BuiltinName.data()+27, "qi", 2))
break;
return Intrinsic::hexagon_A4_vcmpbeqi; // "__builtin_HEXAG
ON_A4_vcmpbeqi"
case 'g': // 1 string to match.
if (memcmp(BuiltinName.data()+27, "ti", 2))
break;
return Intrinsic::hexagon_A4_vcmpbgti; // "__builtin_HEXAG
ON_A4_vcmpbgti"
}
break;
case 'h': // 2 strings to match.
switch (BuiltinName[26]) {
default: break;
case 'e': // 1 string to match.
if (memcmp(BuiltinName.data()+27, "qi", 2))
break;
return Intrinsic::hexagon_A4_vcmpheqi; // "__builtin_HEXAG
ON_A4_vcmpheqi"
case 'g': // 1 string to match.
if (memcmp(BuiltinName.data()+27, "ti", 2))
break;
return Intrinsic::hexagon_A4_vcmphgti; // "__builtin_HEXAG
ON_A4_vcmphgti"
}
break;
case 'w': // 2 strings to match.
switch (BuiltinName[26]) {
default: break;
case 'e': // 1 string to match.
if (memcmp(BuiltinName.data()+27, "qi", 2))
break;
return Intrinsic::hexagon_A4_vcmpweqi; // "__builtin_HEXAG
ON_A4_vcmpweqi"
case 'g': // 1 string to match.
if (memcmp(BuiltinName.data()+27, "ti", 2))
break;
return Intrinsic::hexagon_A4_vcmpwgti; // "__builtin_HEXAG
ON_A4_vcmpwgti"
}
break; break;
return Intrinsic::hexagon_A2_xor; // "__builtin_HEXAGON.A2.xo }
r" break;
} }
break; break;
case '4': // 1 string to match. case '5': // 1 string to match.
if (BuiltinName.substr(20, 4) != ".orn") if (memcmp(BuiltinName.data()+20, "_vaddhubs", 9))
break; break;
return Intrinsic::hexagon_A4_orn; // "__builtin_HEXAGON.A4.or n" return Intrinsic::hexagon_A5_vaddhubs; // "__builtin_HEXAGON_A5_va ddhubs"
} }
break; break;
case 'C': // 5 strings to match. case 'C': // 5 strings to match.
if (BuiltinName.substr(19, 2) != "2.") switch (BuiltinName[19]) {
break;
switch (BuiltinName[21]) {
default: break; default: break;
case 'a': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(22, 2) != "nd") if (memcmp(BuiltinName.data()+20, "_bitsclri", 9))
break;
return Intrinsic::hexagon_C2_and; // "__builtin_HEXAGON.C2.an
d"
case 'm': // 1 string to match.
if (BuiltinName.substr(22, 2) != "ux")
break;
return Intrinsic::hexagon_C2_mux; // "__builtin_HEXAGON.C2.mu
x"
case 'n': // 1 string to match.
if (BuiltinName.substr(22, 2) != "ot")
break; break;
return Intrinsic::hexagon_C2_not; // "__builtin_HEXAGON.C2.no return Intrinsic::hexagon_C2_bitsclri; // "__builtin_HEXAGON_C2_bi
t" tsclri"
case 'o': // 1 string to match. case '4': // 4 strings to match.
if (BuiltinName.substr(22, 2) != "rn") if (BuiltinName[20] != '_')
break; break;
return Intrinsic::hexagon_C2_orn; // "__builtin_HEXAGON.C2.or switch (BuiltinName[21]) {
n" default: break;
case 'x': // 1 string to match. case 'a': // 1 string to match.
if (BuiltinName.substr(22, 2) != "or") if (memcmp(BuiltinName.data()+22, "nd_andn", 7))
break;
return Intrinsic::hexagon_C4_and_andn; // "__builtin_HEXAG
ON_C4_and_andn"
case 'c': // 1 string to match.
if (memcmp(BuiltinName.data()+22, "mplteui", 7))
break;
return Intrinsic::hexagon_C4_cmplteui; // "__builtin_HEXAG
ON_C4_cmplteui"
case 'n': // 2 strings to match.
if (memcmp(BuiltinName.data()+22, "bits", 4))
break;
switch (BuiltinName[26]) {
default: break;
case 'c': // 1 string to match.
if (memcmp(BuiltinName.data()+27, "lr", 2))
break;
return Intrinsic::hexagon_C4_nbitsclr; // "__builtin_HEXAG
ON_C4_nbitsclr"
case 's': // 1 string to match.
if (memcmp(BuiltinName.data()+27, "et", 2))
break;
return Intrinsic::hexagon_C4_nbitsset; // "__builtin_HEXAG
ON_C4_nbitsset"
}
break; break;
return Intrinsic::hexagon_C2_xor; // "__builtin_HEXAGON.C2.xo }
r" break;
} }
break; break;
case 'S': // 5 strings to match. case 'F': // 8 strings to match.
if (BuiltinName.substr(19, 3) != "2.c") if (memcmp(BuiltinName.data()+19, "2_", 2))
break; break;
switch (BuiltinName[22]) { switch (BuiltinName[21]) {
default: break; default: break;
case 'l': // 3 strings to match. case 'd': // 4 strings to match.
switch (BuiltinName[23]) { if (memcmp(BuiltinName.data()+22, "ff", 2))
break;
switch (BuiltinName[24]) {
default: break; default: break;
case '0': // 1 string to match. case 'i': // 3 strings to match.
return Intrinsic::hexagon_S2_cl0; // "__builtin_HEXAGON.S2.cl if (memcmp(BuiltinName.data()+25, "xup", 3))
0" break;
case '1': // 1 string to match. switch (BuiltinName[28]) {
return Intrinsic::hexagon_S2_cl1; // "__builtin_HEXAGON.S2.cl default: break;
1" case 'd': // 1 string to match.
case 'b': // 1 string to match. return Intrinsic::hexagon_F2_dffixupd; // "__builtin_HEXAG
return Intrinsic::hexagon_S2_clb; // "__builtin_HEXAGON.S2.cl ON_F2_dffixupd"
b" case 'n': // 1 string to match.
return Intrinsic::hexagon_F2_dffixupn; // "__builtin_HEXAG
ON_F2_dffixupn"
case 'r': // 1 string to match.
return Intrinsic::hexagon_F2_dffixupr; // "__builtin_HEXAG
ON_F2_dffixupr"
}
break;
case 'm': // 1 string to match.
if (memcmp(BuiltinName.data()+25, "a_sc", 4))
break;
return Intrinsic::hexagon_F2_dffma_sc; // "__builtin_HEXAG
ON_F2_dffma_sc"
} }
break; break;
case 't': // 2 strings to match. case 's': // 4 strings to match.
switch (BuiltinName[23]) { if (memcmp(BuiltinName.data()+22, "ff", 2))
break;
switch (BuiltinName[24]) {
default: break; default: break;
case '0': // 1 string to match. case 'i': // 3 strings to match.
return Intrinsic::hexagon_S2_ct0; // "__builtin_HEXAGON.S2.ct if (memcmp(BuiltinName.data()+25, "xup", 3))
0" break;
case '1': // 1 string to match. switch (BuiltinName[28]) {
return Intrinsic::hexagon_S2_ct1; // "__builtin_HEXAGON.S2.ct default: break;
1" case 'd': // 1 string to match.
return Intrinsic::hexagon_F2_sffixupd; // "__builtin_HEXAG
ON_F2_sffixupd"
case 'n': // 1 string to match.
return Intrinsic::hexagon_F2_sffixupn; // "__builtin_HEXAG
ON_F2_sffixupn"
case 'r': // 1 string to match.
return Intrinsic::hexagon_F2_sffixupr; // "__builtin_HEXAG
ON_F2_sffixupr"
}
break;
case 'm': // 1 string to match.
if (memcmp(BuiltinName.data()+25, "a_sc", 4))
break;
return Intrinsic::hexagon_F2_sffma_sc; // "__builtin_HEXAG
ON_F2_sffma_sc"
} }
break; break;
} }
break; break;
} case 'M': // 29 strings to match.
break;
case 25: // 40 strings to match.
if (BuiltinName.substr(0, 18) != "__builtin_HEXAGON.")
break;
switch (BuiltinName[18]) {
default: break;
case 'A': // 26 strings to match.
switch (BuiltinName[19]) { switch (BuiltinName[19]) {
default: break; default: break;
case '2': // 24 strings to match. case '2': // 18 strings to match.
if (BuiltinName[20] != '.') if (BuiltinName[20] != '_')
break; break;
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case 'a': // 6 strings to match. case 'c': // 10 strings to match.
switch (BuiltinName[22]) { switch (BuiltinName[22]) {
default: break; default: break;
case 'b': // 1 string to match. case 'm': // 8 strings to match.
if (BuiltinName.substr(23, 2) != "sp")
break;
return Intrinsic::hexagon_A2_absp; // "__builtin_HEXAGON.A2.ab
sp"
case 'd': // 2 strings to match.
if (BuiltinName[23] != 'd')
break;
switch (BuiltinName[24]) {
default: break;
case 'i': // 1 string to match.
return Intrinsic::hexagon_A2_addi; // "__builtin_HEXAG
ON.A2.addi"
case 'p': // 1 string to match.
return Intrinsic::hexagon_A2_addp; // "__builtin_HEXAG
ON.A2.addp"
}
break;
case 'n': // 1 string to match.
if (BuiltinName.substr(23, 2) != "dp")
break;
return Intrinsic::hexagon_A2_andp; // "__builtin_HEXAGON.A2.an
dp"
case 's': // 2 strings to match.
switch (BuiltinName[23]) { switch (BuiltinName[23]) {
default: break; default: break;
case 'l': // 1 string to match. case 'a': // 4 strings to match.
if (BuiltinName[24] != 'h') if (BuiltinName[24] != 'c')
break; break;
return Intrinsic::hexagon_A2_aslh; // "__builtin_HEXAG switch (BuiltinName[25]) {
ON.A2.aslh" default: break;
case 'r': // 1 string to match. case 'i': // 1 string to match.
if (BuiltinName[24] != 'h') if (memcmp(BuiltinName.data()+26, "_s0", 3))
break;
return Intrinsic::hexagon_M2_cmaci_s0; // "__builtin_HEXAG
ON_M2_cmaci_s0"
case 'r': // 1 string to match.
if (memcmp(BuiltinName.data()+26, "_s0", 3))
break;
return Intrinsic::hexagon_M2_cmacr_s0; // "__builtin_HEXAG
ON_M2_cmacr_s0"
case 's': // 2 strings to match.
if (memcmp(BuiltinName.data()+26, "_s", 2))
break;
switch (BuiltinName[28]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_cmacs_s0; // "__built
in_HEXAGON_M2_cmacs_s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_cmacs_s1; // "__built
in_HEXAGON_M2_cmacs_s1"
}
break; break;
return Intrinsic::hexagon_A2_asrh; // "__builtin_HEXAG }
ON.A2.asrh" break;
} case 'p': // 4 strings to match.
break; if (BuiltinName[24] != 'y')
} break;
break; switch (BuiltinName[25]) {
case 'm': // 4 strings to match. default: break;
switch (BuiltinName[22]) { case 'i': // 1 string to match.
default: break; if (memcmp(BuiltinName.data()+26, "_s0", 3))
case 'a': // 2 strings to match. break;
if (BuiltinName[23] != 'x') return Intrinsic::hexagon_M2_cmpyi_s0; // "__builtin_HEXAG
ON_M2_cmpyi_s0"
case 'r': // 1 string to match.
if (memcmp(BuiltinName.data()+26, "_s0", 3))
break;
return Intrinsic::hexagon_M2_cmpyr_s0; // "__builtin_HEXAG
ON_M2_cmpyr_s0"
case 's': // 2 strings to match.
if (memcmp(BuiltinName.data()+26, "_s", 2))
break;
switch (BuiltinName[28]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_cmpys_s0; // "__built
in_HEXAGON_M2_cmpys_s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_cmpys_s1; // "__built
in_HEXAGON_M2_cmpys_s1"
}
break;
}
break; break;
switch (BuiltinName[24]) {
default: break;
case 'p': // 1 string to match.
return Intrinsic::hexagon_A2_maxp; // "__builtin_HEXAG
ON.A2.maxp"
case 'u': // 1 string to match.
return Intrinsic::hexagon_A2_maxu; // "__builtin_HEXAG
ON.A2.maxu"
} }
break; break;
case 'i': // 2 strings to match. case 'n': // 2 strings to match.
if (BuiltinName[23] != 'n') if (memcmp(BuiltinName.data()+23, "acs_s", 5))
break; break;
switch (BuiltinName[24]) { switch (BuiltinName[28]) {
default: break; default: break;
case 'p': // 1 string to match. case '0': // 1 string to match.
return Intrinsic::hexagon_A2_minp; // "__builtin_HEXAG return Intrinsic::hexagon_M2_cnacs_s0; // "__builtin_HEXAG
ON.A2.minp" ON_M2_cnacs_s0"
case 'u': // 1 string to match. case '1': // 1 string to match.
return Intrinsic::hexagon_A2_minu; // "__builtin_HEXAG return Intrinsic::hexagon_M2_cnacs_s1; // "__builtin_HEXAG
ON.A2.minu" ON_M2_cnacs_s1"
} }
break; break;
} }
break; break;
case 'n': // 2 strings to match. case 'm': // 5 strings to match.
switch (BuiltinName[22]) {
default: break;
case 'e': // 1 string to match.
if (BuiltinName.substr(23, 2) != "gp")
break;
return Intrinsic::hexagon_A2_negp; // "__builtin_HEXAGON.A2.ne
gp"
case 'o': // 1 string to match.
if (BuiltinName.substr(23, 2) != "tp")
break;
return Intrinsic::hexagon_A2_notp; // "__builtin_HEXAGON.A2.no
tp"
}
break;
case 'o': // 1 string to match.
if (BuiltinName.substr(22, 3) != "rir")
break;
return Intrinsic::hexagon_A2_orir; // "__builtin_HEXAGON.A2.or
ir"
case 's': // 7 strings to match.
switch (BuiltinName[22]) { switch (BuiltinName[22]) {
default: break; default: break;
case 'a': // 2 strings to match. case 'm': // 4 strings to match.
if (BuiltinName[23] != 't') if (memcmp(BuiltinName.data()+23, "py", 2))
break; break;
switch (BuiltinName[24]) { switch (BuiltinName[25]) {
default: break; default: break;
case 'b': // 1 string to match. case 'h': // 2 strings to match.
return Intrinsic::hexagon_A2_satb; // "__builtin_HEXAG if (memcmp(BuiltinName.data()+26, "_s", 2))
ON.A2.satb" break;
case 'h': // 1 string to match. switch (BuiltinName[28]) {
return Intrinsic::hexagon_A2_sath; // "__builtin_HEXAG default: break;
ON.A2.sath" case '0': // 1 string to match.
} return Intrinsic::hexagon_M2_mmpyh_s0; // "__builtin_HEXAG
break; ON_M2_mmpyh_s0"
case 'u': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(23, 2) != "bp") return Intrinsic::hexagon_M2_mmpyh_s1; // "__builtin_HEXAG
break; ON_M2_mmpyh_s1"
return Intrinsic::hexagon_A2_subp; // "__builtin_HEXAGON.A2.su }
bp"
case 'w': // 1 string to match.
if (BuiltinName.substr(23, 2) != "iz")
break; break;
return Intrinsic::hexagon_A2_swiz; // "__builtin_HEXAGON.A2.sw case 'l': // 2 strings to match.
iz" if (memcmp(BuiltinName.data()+26, "_s", 2))
case 'x': // 3 strings to match. break;
if (BuiltinName[23] != 't') switch (BuiltinName[28]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mmpyl_s0; // "__builtin_HEXAG
ON_M2_mmpyl_s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mmpyl_s1; // "__builtin_HEXAG
ON_M2_mmpyl_s1"
}
break; break;
switch (BuiltinName[24]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::hexagon_A2_sxtb; // "__builtin_HEXAG
ON.A2.sxtb"
case 'h': // 1 string to match.
return Intrinsic::hexagon_A2_sxth; // "__builtin_HEXAG
ON.A2.sxth"
case 'w': // 1 string to match.
return Intrinsic::hexagon_A2_sxtw; // "__builtin_HEXAG
ON.A2.sxtw"
} }
break; break;
case 'p': // 1 string to match.
if (memcmp(BuiltinName.data()+23, "ysu_up", 6))
break;
return Intrinsic::hexagon_M2_mpysu_up; // "__builtin_HEXAG
ON_M2_mpysu_up"
} }
break; break;
case 't': // 1 string to match. case 'v': // 2 strings to match.
if (BuiltinName.substr(22, 3) != "frp") if (memcmp(BuiltinName.data()+22, "rm", 2))
break;
return Intrinsic::hexagon_A2_tfrp; // "__builtin_HEXAGON.A2.tf
rp"
case 'x': // 1 string to match.
if (BuiltinName.substr(22, 3) != "orp")
break;
return Intrinsic::hexagon_A2_xorp; // "__builtin_HEXAGON.A2.xo
rp"
case 'z': // 2 strings to match.
if (BuiltinName.substr(22, 2) != "xt")
break; break;
switch (BuiltinName[24]) { switch (BuiltinName[24]) {
default: break; default: break;
case 'b': // 1 string to match. case 'a': // 1 string to match.
return Intrinsic::hexagon_A2_zxtb; // "__builtin_HEXAGON.A2.zx if (memcmp(BuiltinName.data()+25, "c_s0", 4))
tb" break;
case 'h': // 1 string to match. return Intrinsic::hexagon_M2_vrmac_s0; // "__builtin_HEXAG
return Intrinsic::hexagon_A2_zxth; // "__builtin_HEXAGON.A2.zx ON_M2_vrmac_s0"
th" case 'p': // 1 string to match.
if (memcmp(BuiltinName.data()+25, "y_s0", 4))
break;
return Intrinsic::hexagon_M2_vrmpy_s0; // "__builtin_HEXAG
ON_M2_vrmpy_s0"
} }
break; break;
case 'x': // 1 string to match.
if (memcmp(BuiltinName.data()+22, "or_xacc", 7))
break;
return Intrinsic::hexagon_M2_xor_xacc; // "__builtin_HEXAG
ON_M2_xor_xacc"
} }
break; break;
case '4': // 2 strings to match. case '4': // 5 strings to match.
if (BuiltinName[20] != '.') if (BuiltinName[20] != '_')
break; break;
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case 'a': // 1 string to match. case 'a': // 1 string to match.
if (BuiltinName.substr(22, 3) != "ndn") if (memcmp(BuiltinName.data()+22, "nd_andn", 7))
break; break;
return Intrinsic::hexagon_A4_andn; // "__builtin_HEXAGON.A4.an return Intrinsic::hexagon_M4_and_andn; // "__builtin_HEXAG
dn" ON_M4_and_andn"
case 'o': // 1 string to match. case 'c': // 2 strings to match.
if (BuiltinName.substr(22, 3) != "rnp") if (memcmp(BuiltinName.data()+22, "mpy", 3))
break; break;
return Intrinsic::hexagon_A4_ornp; // "__builtin_HEXAGON.A4.or switch (BuiltinName[25]) {
np" default: break;
} case 'i': // 1 string to match.
break; if (memcmp(BuiltinName.data()+26, "_wh", 3))
} break;
break; return Intrinsic::hexagon_M4_cmpyi_wh; // "__builtin_HEXAG
case 'C': // 5 strings to match. ON_M4_cmpyi_wh"
if (BuiltinName.substr(19, 2) != "2.") case 'r': // 1 string to match.
break; if (memcmp(BuiltinName.data()+26, "_wh", 3))
switch (BuiltinName[21]) { break;
default: break; return Intrinsic::hexagon_M4_cmpyr_wh; // "__builtin_HEXAG
case 'a': // 3 strings to match. ON_M4_cmpyr_wh"
switch (BuiltinName[22]) { }
default: break; break;
case 'l': // 1 string to match. case 'x': // 2 strings to match.
if (BuiltinName.substr(23, 2) != "l8") if (memcmp(BuiltinName.data()+22, "or_", 3))
break; break;
return Intrinsic::hexagon_C2_all8; // "__builtin_HEXAGON.C2.al switch (BuiltinName[25]) {
l8"
case 'n': // 2 strings to match.
switch (BuiltinName[23]) {
default: break; default: break;
case 'd': // 1 string to match. case 'a': // 1 string to match.
if (BuiltinName[24] != 'n') if (memcmp(BuiltinName.data()+26, "ndn", 3))
break; break;
return Intrinsic::hexagon_C2_andn; // "__builtin_HEXAGON.C2.an return Intrinsic::hexagon_M4_xor_andn; // "__builtin_HEXAG
dn" ON_M4_xor_andn"
case 'y': // 1 string to match. case 'x': // 1 string to match.
if (BuiltinName[24] != '8') if (memcmp(BuiltinName.data()+26, "acc", 3))
break; break;
return Intrinsic::hexagon_C2_any8; // "__builtin_HEXAGON.C2.an y8" return Intrinsic::hexagon_M4_xor_xacc; // "__builtin_HEXAG ON_M4_xor_xacc"
} }
break; break;
} }
break; break;
case 'm': // 1 string to match. case '5': // 6 strings to match.
if (BuiltinName.substr(22, 3) != "ask") if (memcmp(BuiltinName.data()+20, "_v", 2))
break;
return Intrinsic::hexagon_C2_mask; // "__builtin_HEXAGON.C2.ma
sk"
case 'v': // 1 string to match.
if (BuiltinName.substr(22, 3) != "mux")
break;
return Intrinsic::hexagon_C2_vmux; // "__builtin_HEXAGON.C2.vm
ux"
}
break;
case 'M': // 3 strings to match.
if (BuiltinName.substr(19, 2) != "2.")
break;
switch (BuiltinName[21]) {
default: break;
case 'a': // 1 string to match.
if (BuiltinName.substr(22, 3) != "cci")
break; break;
return Intrinsic::hexagon_M2_acci; // "__builtin_HEXAGON.M2.ac
ci"
case 'm': // 2 strings to match.
switch (BuiltinName[22]) { switch (BuiltinName[22]) {
default: break; default: break;
case 'a': // 1 string to match. case 'd': // 2 strings to match.
if (BuiltinName.substr(23, 2) != "ci") if (BuiltinName[23] != 'm')
break;
switch (BuiltinName[24]) {
default: break;
case 'a': // 1 string to match.
if (memcmp(BuiltinName.data()+25, "cbsu", 4))
break;
return Intrinsic::hexagon_M5_vdmacbsu; // "__builtin_HEXAG
ON_M5_vdmacbsu"
case 'p': // 1 string to match.
if (memcmp(BuiltinName.data()+25, "ybsu", 4))
break;
return Intrinsic::hexagon_M5_vdmpybsu; // "__builtin_HEXAG
ON_M5_vdmpybsu"
}
break;
case 'r': // 4 strings to match.
if (BuiltinName[23] != 'm')
break;
switch (BuiltinName[24]) {
default: break;
case 'a': // 2 strings to match.
if (memcmp(BuiltinName.data()+25, "cb", 2))
break;
switch (BuiltinName[27]) {
default: break;
case 's': // 1 string to match.
if (BuiltinName[28] != 'u')
break;
return Intrinsic::hexagon_M5_vrmacbsu; // "__builtin_HEXAG
ON_M5_vrmacbsu"
case 'u': // 1 string to match.
if (BuiltinName[28] != 'u')
break;
return Intrinsic::hexagon_M5_vrmacbuu; // "__builtin_HEXAG
ON_M5_vrmacbuu"
}
break; break;
return Intrinsic::hexagon_M2_maci; // "__builtin_HEXAGON.M2.ma case 'p': // 2 strings to match.
ci" if (memcmp(BuiltinName.data()+25, "yb", 2))
case 'p': // 1 string to match. break;
if (BuiltinName.substr(23, 2) != "yi") switch (BuiltinName[27]) {
default: break;
case 's': // 1 string to match.
if (BuiltinName[28] != 'u')
break;
return Intrinsic::hexagon_M5_vrmpybsu; // "__builtin_HEXAG
ON_M5_vrmpybsu"
case 'u': // 1 string to match.
if (BuiltinName[28] != 'u')
break;
return Intrinsic::hexagon_M5_vrmpybuu; // "__builtin_HEXAG
ON_M5_vrmpybuu"
}
break; break;
return Intrinsic::hexagon_M2_mpyi; // "__builtin_HEXAGON.M2.mp }
yi" break;
} }
break; break;
} }
break; break;
case 'S': // 6 strings to match. case 'S': // 35 strings to match.
switch (BuiltinName[19]) { switch (BuiltinName[19]) {
default: break; default: break;
case '2': // 5 strings to match. case '2': // 31 strings to match.
if (BuiltinName[20] != '.') if (BuiltinName[20] != '_')
break; break;
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case 'b': // 1 string to match. case 'a': // 8 strings to match.
if (BuiltinName.substr(22, 3) != "rev") if (BuiltinName[22] != 's')
break;
return Intrinsic::hexagon_S2_brev; // "__builtin_HEXAGON.S2.br
ev"
case 'c': // 3 strings to match.
if (BuiltinName[22] != 'l')
break; break;
switch (BuiltinName[23]) { switch (BuiltinName[23]) {
default: break; default: break;
case '0': // 1 string to match. case 'l': // 4 strings to match.
if (BuiltinName[24] != 'p') if (BuiltinName[24] != '_')
break; break;
return Intrinsic::hexagon_S2_cl0p; // "__builtin_HEXAGON.S2.cl switch (BuiltinName[25]) {
0p" default: break;
case '1': // 1 string to match. case 'i': // 2 strings to match.
if (BuiltinName[24] != 'p') if (memcmp(BuiltinName.data()+26, "_v", 2))
break;
switch (BuiltinName[28]) {
default: break;
case 'h': // 1 string to match.
return Intrinsic::hexagon_S2_asl_i_vh; // "__builtin_HEXAG
ON_S2_asl_i_vh"
case 'w': // 1 string to match.
return Intrinsic::hexagon_S2_asl_i_vw; // "__builtin_HEXAG
ON_S2_asl_i_vw"
}
break; break;
return Intrinsic::hexagon_S2_cl1p; // "__builtin_HEXAGON.S2.cl case 'r': // 2 strings to match.
1p" if (memcmp(BuiltinName.data()+26, "_v", 2))
case 'b': // 1 string to match. break;
if (BuiltinName[24] != 'p') switch (BuiltinName[28]) {
default: break;
case 'h': // 1 string to match.
return Intrinsic::hexagon_S2_asl_r_vh; // "__builtin_HEXAG
ON_S2_asl_r_vh"
case 'w': // 1 string to match.
return Intrinsic::hexagon_S2_asl_r_vw; // "__builtin_HEXAG
ON_S2_asl_r_vw"
}
break; break;
return Intrinsic::hexagon_S2_clbp; // "__builtin_HEXAGON.S2.cl }
bp"
}
break;
case 'l': // 1 string to match.
if (BuiltinName.substr(22, 3) != "fsp")
break;
return Intrinsic::hexagon_S2_lfsp; // "__builtin_HEXAGON.S2.lf
sp"
}
break;
case '4': // 1 string to match.
if (BuiltinName.substr(20, 5) != ".ornp")
break;
return Intrinsic::hexagon_S4_ornp; // "__builtin_HEXAGON.S4.or
np"
}
break;
}
break;
case 26: // 41 strings to match.
if (BuiltinName.substr(0, 10) != "__builtin_")
break;
switch (BuiltinName[10]) {
default: break;
case 'H': // 40 strings to match.
if (BuiltinName.substr(11, 7) != "EXAGON.")
break;
switch (BuiltinName[18]) {
default: break;
case 'A': // 25 strings to match.
switch (BuiltinName[19]) {
default: break;
case '2': // 24 strings to match.
if (BuiltinName[20] != '.')
break; break;
switch (BuiltinName[21]) { case 'r': // 4 strings to match.
default: break; if (BuiltinName[24] != '_')
case 'a': // 2 strings to match. break;
switch (BuiltinName[22]) { switch (BuiltinName[25]) {
default: break; default: break;
case 'd': // 1 string to match. case 'i': // 2 strings to match.
if (BuiltinName.substr(23, 3) != "dsp") if (memcmp(BuiltinName.data()+26, "_v", 2))
break; break;
return Intrinsic::hexagon_A2_addsp; // "__builtin_HEXAG switch (BuiltinName[28]) {
ON.A2.addsp" default: break;
case 'n': // 1 string to match. case 'h': // 1 string to match.
if (BuiltinName.substr(23, 3) != "dir") return Intrinsic::hexagon_S2_asr_i_vh; // "__builtin_HEXAG
ON_S2_asr_i_vh"
case 'w': // 1 string to match.
return Intrinsic::hexagon_S2_asr_i_vw; // "__builtin_HEXAG
ON_S2_asr_i_vw"
}
break;
case 'r': // 2 strings to match.
if (memcmp(BuiltinName.data()+26, "_v", 2))
break; break;
return Intrinsic::hexagon_A2_andir; // "__builtin_HEXAG switch (BuiltinName[28]) {
ON.A2.andir" default: break;
case 'h': // 1 string to match.
return Intrinsic::hexagon_S2_asr_r_vh; // "__builtin_HEXAG
ON_S2_asr_r_vh"
case 'w': // 1 string to match.
return Intrinsic::hexagon_S2_asr_r_vw; // "__builtin_HEXAG
ON_S2_asr_r_vw"
}
break;
} }
break; break;
case 'm': // 2 strings to match. }
switch (BuiltinName[22]) { break;
case 'c': // 2 strings to match.
if (memcmp(BuiltinName.data()+22, "lrbit_", 6))
break;
switch (BuiltinName[28]) {
default: break;
case 'i': // 1 string to match.
return Intrinsic::hexagon_S2_clrbit_i; // "__builtin_HEXAG
ON_S2_clrbit_i"
case 'r': // 1 string to match.
return Intrinsic::hexagon_S2_clrbit_r; // "__builtin_HEXAG
ON_S2_clrbit_r"
}
break;
case 'e': // 1 string to match.
if (memcmp(BuiltinName.data()+22, "xtractu", 7))
break;
return Intrinsic::hexagon_S2_extractu; // "__builtin_HEXAG
ON_S2_extractu"
case 'l': // 6 strings to match.
if (BuiltinName[22] != 's')
break;
switch (BuiltinName[23]) {
default: break;
case 'l': // 2 strings to match.
if (memcmp(BuiltinName.data()+24, "_r_v", 4))
break;
switch (BuiltinName[28]) {
default: break; default: break;
case 'a': // 1 string to match. case 'h': // 1 string to match.
if (BuiltinName.substr(23, 3) != "xup") return Intrinsic::hexagon_S2_lsl_r_vh; // "__builtin_HEXAG
break; ON_S2_lsl_r_vh"
return Intrinsic::hexagon_A2_maxup; // "__builtin_HEXAG case 'w': // 1 string to match.
ON.A2.maxup" return Intrinsic::hexagon_S2_lsl_r_vw; // "__builtin_HEXAG
case 'i': // 1 string to match. ON_S2_lsl_r_vw"
if (BuiltinName.substr(23, 3) != "nup")
break;
return Intrinsic::hexagon_A2_minup; // "__builtin_HEXAG
ON.A2.minup"
} }
break; break;
case 's': // 3 strings to match. case 'r': // 4 strings to match.
switch (BuiltinName[22]) { if (BuiltinName[24] != '_')
break;
switch (BuiltinName[25]) {
default: break; default: break;
case 'a': // 2 strings to match. case 'i': // 2 strings to match.
if (BuiltinName.substr(23, 2) != "tu") if (memcmp(BuiltinName.data()+26, "_v", 2))
break; break;
switch (BuiltinName[25]) { switch (BuiltinName[28]) {
default: break; default: break;
case 'b': // 1 string to match.
return Intrinsic::hexagon_A2_satub; // "__builtin_HEXAG
ON.A2.satub"
case 'h': // 1 string to match. case 'h': // 1 string to match.
return Intrinsic::hexagon_A2_satuh; // "__builtin_HEXAG return Intrinsic::hexagon_S2_lsr_i_vh; // "__builtin_HEXAG
ON.A2.satuh" ON_S2_lsr_i_vh"
case 'w': // 1 string to match.
return Intrinsic::hexagon_S2_lsr_i_vw; // "__builtin_HEXAG
ON_S2_lsr_i_vw"
} }
break; break;
case 'u': // 1 string to match. case 'r': // 2 strings to match.
if (BuiltinName.substr(23, 3) != "bri") if (memcmp(BuiltinName.data()+26, "_v", 2))
break; break;
return Intrinsic::hexagon_A2_subri; // "__builtin_HEXAG switch (BuiltinName[28]) {
ON.A2.subri" default: break;
case 'h': // 1 string to match.
return Intrinsic::hexagon_S2_lsr_r_vh; // "__builtin_HEXAG
ON_S2_lsr_r_vh"
case 'w': // 1 string to match.
return Intrinsic::hexagon_S2_lsr_r_vw; // "__builtin_HEXAG
ON_S2_lsr_r_vw"
}
break;
} }
break; break;
case 't': // 4 strings to match. }
if (BuiltinName.substr(22, 2) != "fr") break;
case 's': // 3 strings to match.
switch (BuiltinName[22]) {
default: break;
case 'e': // 2 strings to match.
if (memcmp(BuiltinName.data()+23, "tbit_", 5))
break; break;
switch (BuiltinName[24]) { switch (BuiltinName[28]) {
default: break; default: break;
case 'i': // 2 strings to match. case 'i': // 1 string to match.
switch (BuiltinName[25]) { return Intrinsic::hexagon_S2_setbit_i; // "__builtin_HEXAG
default: break; ON_S2_setbit_i"
case 'h': // 1 string to match. case 'r': // 1 string to match.
return Intrinsic::hexagon_A2_tfrih; // "__builtin_HEXAG return Intrinsic::hexagon_S2_setbit_r; // "__builtin_HEXAG
ON.A2.tfrih" ON_S2_setbit_r"
case 'l': // 1 string to match. }
return Intrinsic::hexagon_A2_tfril; // "__builtin_HEXAG break;
ON.A2.tfril" case 'v': // 1 string to match.
} if (memcmp(BuiltinName.data()+23, "sathub", 6))
break; break;
case 'p': // 1 string to match. return Intrinsic::hexagon_S2_svsathub; // "__builtin_HEXAG
if (BuiltinName[25] != 'i') ON_S2_svsathub"
}
break;
case 't': // 2 strings to match.
if (memcmp(BuiltinName.data()+22, "stbit_", 6))
break;
switch (BuiltinName[28]) {
default: break;
case 'i': // 1 string to match.
return Intrinsic::hexagon_S2_tstbit_i; // "__builtin_HEXAG
ON_S2_tstbit_i"
case 'r': // 1 string to match.
return Intrinsic::hexagon_S2_tstbit_r; // "__builtin_HEXAG
ON_S2_tstbit_r"
}
break;
case 'v': // 9 strings to match.
switch (BuiltinName[22]) {
default: break;
case 'a': // 2 strings to match.
if (memcmp(BuiltinName.data()+23, "lign", 4))
break;
switch (BuiltinName[27]) {
default: break;
case 'i': // 1 string to match.
if (BuiltinName[28] != 'b')
break; break;
return Intrinsic::hexagon_A2_tfrpi; // "__builtin_HEXAG return Intrinsic::hexagon_S2_valignib; // "__builtin_HEXAG
ON.A2.tfrpi" ON_S2_valignib"
case 's': // 1 string to match. case 'r': // 1 string to match.
if (BuiltinName[25] != 'i') if (BuiltinName[28] != 'b')
break; break;
return Intrinsic::hexagon_A2_tfrsi; // "__builtin_HEXAG ON.A2.tfrsi" return Intrinsic::hexagon_S2_valignrb; // "__builtin_HEXAG ON_S2_valignrb"
} }
break; break;
case 'v': // 13 strings to match. case 'c': // 1 string to match.
switch (BuiltinName[22]) { if (memcmp(BuiltinName.data()+23, "rotate", 6))
break;
return Intrinsic::hexagon_S2_vcrotate; // "__builtin_HEXAG
ON_S2_vcrotate"
case 's': // 2 strings to match.
if (memcmp(BuiltinName.data()+23, "platr", 5))
break;
switch (BuiltinName[28]) {
default: break; default: break;
case 'a': // 6 strings to match. case 'b': // 1 string to match.
switch (BuiltinName[23]) { return Intrinsic::hexagon_S2_vsplatrb; // "__builtin_HEXAG
default: break; ON_S2_vsplatrb"
case 'b': // 2 strings to match. case 'h': // 1 string to match.
if (BuiltinName[24] != 's') return Intrinsic::hexagon_S2_vsplatrh; // "__builtin_HEXAG
break; ON_S2_vsplatrh"
switch (BuiltinName[25]) { }
default: break; break;
case 'h': // 1 string to match. case 't': // 4 strings to match.
return Intrinsic::hexagon_A2_vabsh; // "__builtin_HEXAG if (memcmp(BuiltinName.data()+23, "run", 3))
ON.A2.vabsh"
case 'w': // 1 string to match.
return Intrinsic::hexagon_A2_vabsw; // "__builtin_HEXAG
ON.A2.vabsw"
}
break;
case 'd': // 2 strings to match.
if (BuiltinName[24] != 'd')
break;
switch (BuiltinName[25]) {
default: break;
case 'h': // 1 string to match.
return Intrinsic::hexagon_A2_vaddh; // "__builtin_HEXAG
ON.A2.vaddh"
case 'w': // 1 string to match.
return Intrinsic::hexagon_A2_vaddw; // "__builtin_HEXAG
ON.A2.vaddw"
}
break;
case 'v': // 2 strings to match.
if (BuiltinName[24] != 'g')
break;
switch (BuiltinName[25]) {
default: break;
case 'h': // 1 string to match.
return Intrinsic::hexagon_A2_vavgh; // "__builtin_HEXAG
ON.A2.vavgh"
case 'w': // 1 string to match.
return Intrinsic::hexagon_A2_vavgw; // "__builtin_HEXAG
ON.A2.vavgw"
}
break;
}
break; break;
case 'c': // 1 string to match. switch (BuiltinName[26]) {
if (BuiltinName.substr(23, 3) != "onj") default: break;
break; case 'e': // 2 strings to match.
return Intrinsic::hexagon_A2_vconj; // "__builtin_HEXAG switch (BuiltinName[27]) {
ON.A2.vconj"
case 'm': // 4 strings to match.
switch (BuiltinName[23]) {
default: break; default: break;
case 'a': // 2 strings to match. case 'h': // 1 string to match.
if (BuiltinName[24] != 'x') if (BuiltinName[28] != 'b')
break; break;
switch (BuiltinName[25]) { return Intrinsic::hexagon_S2_vtrunehb; // "__builtin_HEXAG
default: break; ON_S2_vtrunehb"
case 'h': // 1 string to match. case 'w': // 1 string to match.
return Intrinsic::hexagon_A2_vmaxh; // "__builtin_HEXAG if (BuiltinName[28] != 'h')
ON.A2.vmaxh"
case 'w': // 1 string to match.
return Intrinsic::hexagon_A2_vmaxw; // "__builtin_HEXAG
ON.A2.vmaxw"
}
break;
case 'i': // 2 strings to match.
if (BuiltinName[24] != 'n')
break; break;
switch (BuiltinName[25]) { return Intrinsic::hexagon_S2_vtrunewh; // "__builtin_HEXAG
default: break; ON_S2_vtrunewh"
case 'h': // 1 string to match. }
return Intrinsic::hexagon_A2_vminh; // "__builtin_HEXAG break;
ON.A2.vminh" case 'o': // 2 strings to match.
case 'w': // 1 string to match. switch (BuiltinName[27]) {
return Intrinsic::hexagon_A2_vminw; // "__builtin_HEXAG
ON.A2.vminw"
}
break;
}
break;
case 's': // 2 strings to match.
if (BuiltinName.substr(23, 2) != "ub")
break;
switch (BuiltinName[25]) {
default: break; default: break;
case 'h': // 1 string to match. case 'h': // 1 string to match.
return Intrinsic::hexagon_A2_vsubh; // "__builtin_HEXAG if (BuiltinName[28] != 'b')
ON.A2.vsubh" break;
return Intrinsic::hexagon_S2_vtrunohb; // "__builtin_HEXAG
ON_S2_vtrunohb"
case 'w': // 1 string to match. case 'w': // 1 string to match.
return Intrinsic::hexagon_A2_vsubw; // "__builtin_HEXAG if (BuiltinName[28] != 'h')
ON.A2.vsubw" break;
return Intrinsic::hexagon_S2_vtrunowh; // "__builtin_HEXAG
ON_S2_vtrunowh"
} }
break; break;
} }
break; break;
} }
break; break;
case '4': // 1 string to match. }
if (BuiltinName.substr(20, 6) != ".andnp") break;
case '4': // 4 strings to match.
if (BuiltinName[20] != '_')
break;
switch (BuiltinName[21]) {
default: break;
case 'c': // 2 strings to match.
if (memcmp(BuiltinName.data()+22, "lbp", 3))
break; break;
return Intrinsic::hexagon_A4_andnp; // "__builtin_HEXAGON.A4.an switch (BuiltinName[25]) {
dnp" default: break;
case 'a': // 1 string to match.
if (memcmp(BuiltinName.data()+26, "ddi", 3))
break;
return Intrinsic::hexagon_S4_clbpaddi; // "__builtin_HEXAG
ON_S4_clbpaddi"
case 'n': // 1 string to match.
if (memcmp(BuiltinName.data()+26, "orm", 3))
break;
return Intrinsic::hexagon_S4_clbpnorm; // "__builtin_HEXAG
ON_S4_clbpnorm"
}
break;
case 'e': // 1 string to match.
if (memcmp(BuiltinName.data()+22, "xtractp", 7))
break;
return Intrinsic::hexagon_S4_extractp; // "__builtin_HEXAG
ON_S4_extractp"
case 'o': // 1 string to match.
if (memcmp(BuiltinName.data()+22, "r_andix", 7))
break;
return Intrinsic::hexagon_S4_or_andix; // "__builtin_HEXAG
ON_S4_or_andix"
} }
break; break;
case 'C': // 9 strings to match. }
switch (BuiltinName[19]) { break;
}
break;
case 30: // 81 strings to match.
if (memcmp(BuiltinName.data()+0, "__builtin_HEXAGON_", 18))
break;
switch (BuiltinName[18]) {
default: break;
case 'A': // 11 strings to match.
switch (BuiltinName[19]) {
default: break;
case '2': // 3 strings to match.
if (BuiltinName[20] != '_')
break;
switch (BuiltinName[21]) {
default: break; default: break;
case '2': // 8 strings to match. case 'c': // 1 string to match.
if (BuiltinName[20] != '.') if (memcmp(BuiltinName.data()+22, "ombineii", 8))
break; break;
switch (BuiltinName[21]) { return Intrinsic::hexagon_A2_combineii; // "__builtin_HEXAG
ON_A2_combineii"
case 'v': // 2 strings to match.
switch (BuiltinName[22]) {
default: break; default: break;
case 'c': // 3 strings to match. case 'a': // 1 string to match.
if (BuiltinName.substr(22, 2) != "mp") if (memcmp(BuiltinName.data()+23, "ddb_map", 7))
break; break;
switch (BuiltinName[24]) { return Intrinsic::hexagon_A2_vaddb_map; // "__builtin_HEXAG
default: break; ON_A2_vaddb_map"
case 'e': // 1 string to match. case 's': // 1 string to match.
if (BuiltinName[25] != 'q') if (memcmp(BuiltinName.data()+23, "ubb_map", 7))
break; break;
return Intrinsic::hexagon_C2_cmpeq; // "__builtin_HEXAG return Intrinsic::hexagon_A2_vsubb_map; // "__builtin_HEXAG
ON.C2.cmpeq" ON_A2_vsubb_map"
case 'g': // 1 string to match. }
if (BuiltinName[25] != 't') break;
break; }
return Intrinsic::hexagon_C2_cmpgt; // "__builtin_HEXAG break;
ON.C2.cmpgt" case '4': // 8 strings to match.
case 'l': // 1 string to match. if (BuiltinName[20] != '_')
if (BuiltinName[25] != 't') break;
break; switch (BuiltinName[21]) {
return Intrinsic::hexagon_C2_cmplt; // "__builtin_HEXAG default: break;
ON.C2.cmplt" case 'b': // 1 string to match.
} if (memcmp(BuiltinName.data()+22, "itspliti", 8))
break; break;
case 'm': // 3 strings to match. return Intrinsic::hexagon_A4_bitspliti; // "__builtin_HEXAG
if (BuiltinName.substr(22, 2) != "ux") ON_A4_bitspliti"
case 'c': // 4 strings to match.
switch (BuiltinName[22]) {
default: break;
case 'o': // 2 strings to match.
if (memcmp(BuiltinName.data()+23, "mbine", 5))
break; break;
switch (BuiltinName[24]) { switch (BuiltinName[28]) {
default: break; default: break;
case 'i': // 2 strings to match. case 'i': // 1 string to match.
switch (BuiltinName[25]) { if (BuiltinName[29] != 'r')
default: break; break;
case 'i': // 1 string to match. return Intrinsic::hexagon_A4_combineir; // "__builtin_HEXAG
return Intrinsic::hexagon_C2_muxii; // "__builtin_HEXAG ON_A4_combineir"
ON.C2.muxii"
case 'r': // 1 string to match.
return Intrinsic::hexagon_C2_muxir; // "__builtin_HEXAG
ON.C2.muxir"
}
break;
case 'r': // 1 string to match. case 'r': // 1 string to match.
if (BuiltinName[25] != 'i') if (BuiltinName[29] != 'i')
break; break;
return Intrinsic::hexagon_C2_muxri; // "__builtin_HEXAG ON.C2.muxri" return Intrinsic::hexagon_A4_combineri; // "__builtin_HEXAG ON_A4_combineri"
} }
break; break;
case 't': // 2 strings to match. case 'r': // 2 strings to match.
if (BuiltinName.substr(22, 2) != "fr") if (memcmp(BuiltinName.data()+23, "ound_r", 6))
break; break;
switch (BuiltinName[24]) { switch (BuiltinName[29]) {
default: break; default: break;
case 'p': // 1 string to match. case 'i': // 1 string to match.
if (BuiltinName[25] != 'r') return Intrinsic::hexagon_A4_cround_ri; // "__builtin_HEXAG
break; ON_A4_cround_ri"
return Intrinsic::hexagon_C2_tfrpr; // "__builtin_HEXAG
ON.C2.tfrpr"
case 'r': // 1 string to match. case 'r': // 1 string to match.
if (BuiltinName[25] != 'p') return Intrinsic::hexagon_A4_cround_rr; // "__builtin_HEXAG
break; ON_A4_cround_rr"
return Intrinsic::hexagon_C2_tfrrp; // "__builtin_HEXAG
ON.C2.tfrrp"
} }
break; break;
} }
break; break;
case '4': // 1 string to match. case 'v': // 3 strings to match.
if (BuiltinName.substr(20, 6) != ".or_or") if (memcmp(BuiltinName.data()+22, "cmp", 3))
break;
return Intrinsic::hexagon_C4_or_or; // "__builtin_HEXAGON.C4.or
_or"
}
break;
case 'M': // 5 strings to match.
switch (BuiltinName[19]) {
default: break;
case '2': // 4 strings to match.
if (BuiltinName[20] != '.')
break; break;
switch (BuiltinName[21]) { switch (BuiltinName[25]) {
default: break; default: break;
case 'a': // 1 string to match. case 'b': // 1 string to match.
if (BuiltinName.substr(22, 4) != "ccii") if (memcmp(BuiltinName.data()+26, "gtui", 4))
break;
return Intrinsic::hexagon_M2_accii; // "__builtin_HEXAG
ON.M2.accii"
case 'm': // 1 string to match.
if (BuiltinName.substr(22, 4) != "pyui")
break; break;
return Intrinsic::hexagon_M2_mpyui; // "__builtin_HEXAG return Intrinsic::hexagon_A4_vcmpbgtui; // "__builtin_HEXAG
ON.M2.mpyui" ON_A4_vcmpbgtui"
case 'n': // 1 string to match. case 'h': // 1 string to match.
if (BuiltinName.substr(22, 4) != "acci") if (memcmp(BuiltinName.data()+26, "gtui", 4))
break; break;
return Intrinsic::hexagon_M2_nacci; // "__builtin_HEXAG return Intrinsic::hexagon_A4_vcmphgtui; // "__builtin_HEXAG
ON.M2.nacci" ON_A4_vcmphgtui"
case 'v': // 1 string to match. case 'w': // 1 string to match.
if (BuiltinName.substr(22, 4) != "mac2") if (memcmp(BuiltinName.data()+26, "gtui", 4))
break; break;
return Intrinsic::hexagon_M2_vmac2; // "__builtin_HEXAG ON.M2.vmac2" return Intrinsic::hexagon_A4_vcmpwgtui; // "__builtin_HEXAG ON_A4_vcmpwgtui"
} }
break; break;
case '4': // 1 string to match.
if (BuiltinName.substr(20, 6) != ".or_or")
break;
return Intrinsic::hexagon_M4_or_or; // "__builtin_HEXAGON.M4.or
_or"
} }
break; break;
case 'S': // 1 string to match. }
if (BuiltinName.substr(19, 7) != "4.andnp") break;
case 'C': // 2 strings to match.
switch (BuiltinName[19]) {
default: break;
case '2': // 1 string to match.
if (memcmp(BuiltinName.data()+20, "_pxfer_map", 10))
break;
return Intrinsic::hexagon_C2_pxfer_map; // "__builtin_HEXAG
ON_C2_pxfer_map"
case '4': // 1 string to match.
if (memcmp(BuiltinName.data()+20, "_nbitsclri", 10))
break; break;
return Intrinsic::hexagon_S4_andnp; // "__builtin_HEXAGON.S4.an dnp" return Intrinsic::hexagon_C4_nbitsclri; // "__builtin_HEXAG ON_C4_nbitsclri"
} }
break; break;
case 'S': // 1 string to match. case 'F': // 12 strings to match.
if (BuiltinName.substr(11, 15) != "I.to.SXTHI.asrh") if (memcmp(BuiltinName.data()+19, "2_", 2))
break; break;
return Intrinsic::hexagon_SI_to_SXTHI_asrh; // "__builtin_SI.to switch (BuiltinName[21]) {
.SXTHI.asrh"
}
break;
case 27: // 58 strings to match.
if (BuiltinName.substr(0, 18) != "__builtin_HEXAGON.")
break;
switch (BuiltinName[18]) {
default: break;
case 'A': // 27 strings to match.
switch (BuiltinName[19]) {
default: break; default: break;
case '2': // 26 strings to match. case 'c': // 8 strings to match.
if (BuiltinName[20] != '.') if (memcmp(BuiltinName.data()+22, "onv_", 4))
break; break;
switch (BuiltinName[21]) { switch (BuiltinName[26]) {
default: break; default: break;
case 'a': // 2 strings to match. case 'd': // 4 strings to match.
switch (BuiltinName[22]) { switch (BuiltinName[27]) {
default: break; default: break;
case 'b': // 1 string to match. case '2': // 2 strings to match.
if (BuiltinName.substr(23, 4) != "ssat") switch (BuiltinName[28]) {
default: break;
case 'd': // 1 string to match.
if (BuiltinName[29] != 'f')
break;
return Intrinsic::hexagon_F2_conv_d2df; // "__builtin_HEXAG
ON_F2_conv_d2df"
case 's': // 1 string to match.
if (BuiltinName[29] != 'f')
break;
return Intrinsic::hexagon_F2_conv_d2sf; // "__builtin_HEXAG
ON_F2_conv_d2sf"
}
break;
case 'f': // 2 strings to match.
if (BuiltinName[28] != '2')
break; break;
return Intrinsic::hexagon_A2_abssat; // "__builtin_HEXAG switch (BuiltinName[29]) {
ON.A2.abssat" default: break;
case 'd': // 1 string to match.
return Intrinsic::hexagon_F2_conv_df2d; // "__builtin_HEXAG
ON_F2_conv_df2d"
case 'w': // 1 string to match.
return Intrinsic::hexagon_F2_conv_df2w; // "__builtin_HEXAG
ON_F2_conv_df2w"
}
break;
}
break;
case 's': // 2 strings to match.
if (memcmp(BuiltinName.data()+27, "f2", 2))
break;
switch (BuiltinName[29]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::hexagon_F2_conv_sf2d; // "__builtin_HEXAG
ON_F2_conv_sf2d"
case 'w': // 1 string to match.
return Intrinsic::hexagon_F2_conv_sf2w; // "__builtin_HEXAG
ON_F2_conv_sf2w"
}
break;
case 'w': // 2 strings to match.
if (BuiltinName[27] != '2')
break;
switch (BuiltinName[28]) {
default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
if (BuiltinName.substr(23, 4) != "dsat") if (BuiltinName[29] != 'f')
break;
return Intrinsic::hexagon_F2_conv_w2df; // "__builtin_HEXAG
ON_F2_conv_w2df"
case 's': // 1 string to match.
if (BuiltinName[29] != 'f')
break; break;
return Intrinsic::hexagon_A2_addsat; // "__builtin_HEXAG ON.A2.addsat" return Intrinsic::hexagon_F2_conv_w2sf; // "__builtin_HEXAG ON_F2_conv_w2sf"
} }
break; break;
case 'n': // 1 string to match. }
if (BuiltinName.substr(22, 5) != "egsat") break;
case 'd': // 2 strings to match.
if (memcmp(BuiltinName.data()+22, "ffm", 3))
break;
switch (BuiltinName[25]) {
default: break;
case 'a': // 1 string to match.
if (memcmp(BuiltinName.data()+26, "_lib", 4))
break; break;
return Intrinsic::hexagon_A2_negsat; // "__builtin_HEXAGON.A2.ne return Intrinsic::hexagon_F2_dffma_lib; // "__builtin_HEXAG
gsat" ON_F2_dffma_lib"
case 's': // 4 strings to match. case 's': // 1 string to match.
if (memcmp(BuiltinName.data()+26, "_lib", 4))
break;
return Intrinsic::hexagon_F2_dffms_lib; // "__builtin_HEXAG
ON_F2_dffms_lib"
}
break;
case 's': // 2 strings to match.
if (memcmp(BuiltinName.data()+22, "ffm", 3))
break;
switch (BuiltinName[25]) {
default: break;
case 'a': // 1 string to match.
if (memcmp(BuiltinName.data()+26, "_lib", 4))
break;
return Intrinsic::hexagon_F2_sffma_lib; // "__builtin_HEXAG
ON_F2_sffma_lib"
case 's': // 1 string to match.
if (memcmp(BuiltinName.data()+26, "_lib", 4))
break;
return Intrinsic::hexagon_F2_sffms_lib; // "__builtin_HEXAG
ON_F2_sffms_lib"
}
break;
}
break;
case 'M': // 44 strings to match.
switch (BuiltinName[19]) {
default: break;
case '2': // 41 strings to match.
if (BuiltinName[20] != '_')
break;
switch (BuiltinName[21]) {
default: break;
case 'c': // 8 strings to match.
switch (BuiltinName[22]) { switch (BuiltinName[22]) {
default: break; default: break;
case 'u': // 1 string to match. case 'm': // 6 strings to match.
if (BuiltinName.substr(23, 4) != "bsat")
break;
return Intrinsic::hexagon_A2_subsat; // "__builtin_HEXAG
ON.A2.subsat"
case 'v': // 3 strings to match.
switch (BuiltinName[23]) { switch (BuiltinName[23]) {
default: break; default: break;
case 'a': // 2 strings to match. case 'a': // 2 strings to match.
switch (BuiltinName[24]) { if (memcmp(BuiltinName.data()+24, "csc_s", 5))
break;
switch (BuiltinName[29]) {
default: break; default: break;
case 'd': // 1 string to match. case '0': // 1 string to match.
if (BuiltinName.substr(25, 2) != "dh") return Intrinsic::hexagon_M2_cmacsc_s0; // "__built
in_HEXAGON_M2_cmacsc_s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_cmacsc_s1; // "__built
in_HEXAGON_M2_cmacsc_s1"
}
break;
case 'p': // 4 strings to match.
if (BuiltinName[24] != 'y')
break;
switch (BuiltinName[25]) {
default: break;
case 'r': // 2 strings to match.
if (memcmp(BuiltinName.data()+26, "s_s", 3))
break; break;
return Intrinsic::hexagon_A2_svaddh; // "__builtin_HEXAG switch (BuiltinName[29]) {
ON.A2.svaddh" default: break;
case 'v': // 1 string to match. case '0': // 1 string to match.
if (BuiltinName.substr(25, 2) != "gh") return Intrinsic::hexagon_M2_cmpyrs_s0; // "__built
in_HEXAGON_M2_cmpyrs_s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_cmpyrs_s1; // "__built
in_HEXAGON_M2_cmpyrs_s1"
}
break;
case 's': // 2 strings to match.
if (memcmp(BuiltinName.data()+26, "c_s", 3))
break; break;
return Intrinsic::hexagon_A2_svavgh; // "__builtin_HEXAG switch (BuiltinName[29]) {
ON.A2.svavgh" default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_cmpysc_s0; // "__built
in_HEXAGON_M2_cmpysc_s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_cmpysc_s1; // "__built
in_HEXAGON_M2_cmpysc_s1"
}
break;
} }
break; break;
case 's': // 1 string to match. }
if (BuiltinName.substr(24, 3) != "ubh") break;
break; case 'n': // 2 strings to match.
return Intrinsic::hexagon_A2_svsubh; // "__builtin_HEXAG if (memcmp(BuiltinName.data()+23, "acsc_s", 6))
ON.A2.svsubh" break;
switch (BuiltinName[29]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_cnacsc_s0; // "__builtin_HEXAG
ON_M2_cnacsc_s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_cnacsc_s1; // "__builtin_HEXAG
ON_M2_cnacsc_s1"
} }
break; break;
} }
break; break;
case 'v': // 19 strings to match. case 'h': // 2 strings to match.
if (memcmp(BuiltinName.data()+22, "mmpy", 4))
break;
switch (BuiltinName[26]) {
default: break;
case 'h': // 1 string to match.
if (memcmp(BuiltinName.data()+27, "_s1", 3))
break;
return Intrinsic::hexagon_M2_hmmpyh_s1; // "__builtin_HEXAG
ON_M2_hmmpyh_s1"
case 'l': // 1 string to match.
if (memcmp(BuiltinName.data()+27, "_s1", 3))
break;
return Intrinsic::hexagon_M2_hmmpyl_s1; // "__builtin_HEXAG
ON_M2_hmmpyl_s1"
}
break;
case 'm': // 21 strings to match.
switch (BuiltinName[22]) { switch (BuiltinName[22]) {
default: break; default: break;
case 'a': // 8 strings to match. case 'm': // 12 strings to match.
switch (BuiltinName[23]) { switch (BuiltinName[23]) {
default: break; default: break;
case 'd': // 3 strings to match. case 'a': // 4 strings to match.
if (BuiltinName[24] != 'd') if (BuiltinName[24] != 'c')
break; break;
switch (BuiltinName[25]) { switch (BuiltinName[25]) {
default: break; default: break;
case 'h': // 1 string to match. case 'h': // 2 strings to match.
if (BuiltinName[26] != 's') if (memcmp(BuiltinName.data()+26, "s_s", 3))
break;
return Intrinsic::hexagon_A2_vaddhs; // "__builtin_HEXAG
ON.A2.vaddhs"
case 'u': // 1 string to match.
if (BuiltinName[26] != 'b')
break; break;
return Intrinsic::hexagon_A2_vaddub; // "__builtin_HEXAG switch (BuiltinName[29]) {
ON.A2.vaddub" default: break;
case 'w': // 1 string to match. case '0': // 1 string to match.
if (BuiltinName[26] != 's') return Intrinsic::hexagon_M2_mmachs_s0; // "__built
in_HEXAGON_M2_mmachs_s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mmachs_s1; // "__built
in_HEXAGON_M2_mmachs_s1"
}
break;
case 'l': // 2 strings to match.
if (memcmp(BuiltinName.data()+26, "s_s", 3))
break; break;
return Intrinsic::hexagon_A2_vaddws; // "__builtin_HEXAG switch (BuiltinName[29]) {
ON.A2.vaddws" default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mmacls_s0; // "__built
in_HEXAGON_M2_mmacls_s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mmacls_s1; // "__built
in_HEXAGON_M2_mmacls_s1"
}
break;
} }
break; break;
case 'v': // 5 strings to match. case 'p': // 8 strings to match.
if (BuiltinName[24] != 'g') if (BuiltinName[24] != 'y')
break; break;
switch (BuiltinName[25]) { switch (BuiltinName[25]) {
default: break; default: break;
case 'h': // 1 string to match. case 'h': // 2 strings to match.
if (BuiltinName[26] != 'r') if (memcmp(BuiltinName.data()+26, "_rs", 3))
break; break;
return Intrinsic::hexagon_A2_vavghr; // "__builtin_HEXAG switch (BuiltinName[29]) {
ON.A2.vavghr"
case 'u': // 3 strings to match.
switch (BuiltinName[26]) {
default: break; default: break;
case 'b': // 1 string to match. case '0': // 1 string to match.
return Intrinsic::hexagon_A2_vavgub; // "__builtin_HEXAG return Intrinsic::hexagon_M2_mmpyh_rs0; // "__built
ON.A2.vavgub" in_HEXAGON_M2_mmpyh_rs0"
case 'h': // 1 string to match. case '1': // 1 string to match.
return Intrinsic::hexagon_A2_vavguh; // "__builtin_HEXAG return Intrinsic::hexagon_M2_mmpyh_rs1; // "__built
ON.A2.vavguh" in_HEXAGON_M2_mmpyh_rs1"
case 'w': // 1 string to match.
return Intrinsic::hexagon_A2_vavguw; // "__builtin_HEXAG
ON.A2.vavguw"
} }
break; break;
case 'w': // 1 string to match. case 'l': // 2 strings to match.
if (BuiltinName[26] != 'r') if (memcmp(BuiltinName.data()+26, "_rs", 3))
break;
switch (BuiltinName[29]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mmpyl_rs0; // "__built
in_HEXAGON_M2_mmpyl_rs0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mmpyl_rs1; // "__built
in_HEXAGON_M2_mmpyl_rs1"
}
break;
case 'u': // 4 strings to match.
switch (BuiltinName[26]) {
default: break;
case 'h': // 2 strings to match.
if (memcmp(BuiltinName.data()+27, "_s", 2))
break;
switch (BuiltinName[29]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mmpyuh_s0; // "__built
in_HEXAGON_M2_mmpyuh_s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mmpyuh_s1; // "__built
in_HEXAGON_M2_mmpyuh_s1"
}
break;
case 'l': // 2 strings to match.
if (memcmp(BuiltinName.data()+27, "_s", 2))
break;
switch (BuiltinName[29]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mmpyul_s0; // "__built
in_HEXAGON_M2_mmpyul_s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mmpyul_s1; // "__built
in_HEXAGON_M2_mmpyul_s1"
}
break; break;
return Intrinsic::hexagon_A2_vavgwr; // "__builtin_HEXAG }
ON.A2.vavgwr" break;
} }
break; break;
} }
break; break;
case 'm': // 6 strings to match. case 'p': // 9 strings to match.
switch (BuiltinName[23]) { if (memcmp(BuiltinName.data()+23, "y_", 2))
break;
switch (BuiltinName[25]) {
default: break; default: break;
case 'a': // 3 strings to match. case 'h': // 4 strings to match.
if (BuiltinName.substr(24, 2) != "xu")
break;
switch (BuiltinName[26]) { switch (BuiltinName[26]) {
default: break; default: break;
case 'b': // 1 string to match. case 'h': // 2 strings to match.
return Intrinsic::hexagon_A2_vmaxub; // "__builtin_HEXAG if (memcmp(BuiltinName.data()+27, "_s", 2))
ON.A2.vmaxub" break;
case 'h': // 1 string to match. switch (BuiltinName[29]) {
return Intrinsic::hexagon_A2_vmaxuh; // "__builtin_HEXAG default: break;
ON.A2.vmaxuh" case '0': // 1 string to match.
case 'w': // 1 string to match. return Intrinsic::hexagon_M2_mpy_hh_s0; // "__built
return Intrinsic::hexagon_A2_vmaxuw; // "__builtin_HEXAG in_HEXAGON_M2_mpy_hh_s0"
ON.A2.vmaxuw" case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_hh_s1; // "__built
in_HEXAGON_M2_mpy_hh_s1"
}
break;
case 'l': // 2 strings to match.
if (memcmp(BuiltinName.data()+27, "_s", 2))
break;
switch (BuiltinName[29]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_hl_s0; // "__built
in_HEXAGON_M2_mpy_hl_s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_hl_s1; // "__built
in_HEXAGON_M2_mpy_hl_s1"
}
break;
} }
break; break;
case 'i': // 3 strings to match. case 'l': // 4 strings to match.
if (BuiltinName.substr(24, 2) != "nu")
break;
switch (BuiltinName[26]) { switch (BuiltinName[26]) {
default: break; default: break;
case 'b': // 1 string to match. case 'h': // 2 strings to match.
return Intrinsic::hexagon_A2_vminub; // "__builtin_HEXAG if (memcmp(BuiltinName.data()+27, "_s", 2))
ON.A2.vminub" break;
case 'h': // 1 string to match. switch (BuiltinName[29]) {
return Intrinsic::hexagon_A2_vminuh; // "__builtin_HEXAG default: break;
ON.A2.vminuh" case '0': // 1 string to match.
case 'w': // 1 string to match. return Intrinsic::hexagon_M2_mpy_lh_s0; // "__built
return Intrinsic::hexagon_A2_vminuw; // "__builtin_HEXAG in_HEXAGON_M2_mpy_lh_s0"
ON.A2.vminuw" case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_lh_s1; // "__built
in_HEXAGON_M2_mpy_lh_s1"
}
break;
case 'l': // 2 strings to match.
if (memcmp(BuiltinName.data()+27, "_s", 2))
break;
switch (BuiltinName[29]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_ll_s0; // "__built
in_HEXAGON_M2_mpy_ll_s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_ll_s1; // "__built
in_HEXAGON_M2_mpy_ll_s1"
}
break;
} }
break; break;
}
break;
case 'n': // 2 strings to match.
if (BuiltinName.substr(23, 3) != "avg")
break;
switch (BuiltinName[26]) {
default: break;
case 'h': // 1 string to match.
return Intrinsic::hexagon_A2_vnavgh; // "__builtin_HEXAG
ON.A2.vnavgh"
case 'w': // 1 string to match.
return Intrinsic::hexagon_A2_vnavgw; // "__builtin_HEXAG
ON.A2.vnavgw"
}
break;
case 's': // 3 strings to match.
if (BuiltinName.substr(23, 2) != "ub")
break;
switch (BuiltinName[25]) {
default: break;
case 'h': // 1 string to match.
if (BuiltinName[26] != 's')
break;
return Intrinsic::hexagon_A2_vsubhs; // "__builtin_HEXAG
ON.A2.vsubhs"
case 'u': // 1 string to match. case 'u': // 1 string to match.
if (BuiltinName[26] != 'b') if (memcmp(BuiltinName.data()+26, "p_s1", 4))
break;
return Intrinsic::hexagon_A2_vsubub; // "__builtin_HEXAG
ON.A2.vsubub"
case 'w': // 1 string to match.
if (BuiltinName[26] != 's')
break; break;
return Intrinsic::hexagon_A2_vsubws; // "__builtin_HEXAG ON.A2.vsubws" return Intrinsic::hexagon_M2_mpy_up_s1; // "__builtin_HEXAG ON_M2_mpy_up_s1"
} }
break; break;
} }
break; break;
} case 'v': // 10 strings to match.
break; switch (BuiltinName[22]) {
case '4': // 1 string to match.
if (BuiltinName.substr(20, 7) != ".rcmpeq")
break;
return Intrinsic::hexagon_A4_rcmpeq; // "__builtin_HEXAGON.A4.rc
mpeq"
}
break;
case 'C': // 12 strings to match.
switch (BuiltinName[19]) {
default: break;
case '2': // 7 strings to match.
if (BuiltinName.substr(20, 4) != ".cmp")
break;
switch (BuiltinName[24]) {
default: break;
case 'e': // 2 strings to match.
if (BuiltinName[25] != 'q')
break;
switch (BuiltinName[26]) {
default: break;
case 'i': // 1 string to match.
return Intrinsic::hexagon_C2_cmpeqi; // "__builtin_HEXAG
ON.C2.cmpeqi"
case 'p': // 1 string to match.
return Intrinsic::hexagon_C2_cmpeqp; // "__builtin_HEXAG
ON.C2.cmpeqp"
}
break;
case 'g': // 4 strings to match.
switch (BuiltinName[25]) {
default: break; default: break;
case 'e': // 1 string to match. case 'a': // 2 strings to match.
if (BuiltinName[26] != 'i') if (memcmp(BuiltinName.data()+23, "bsdiff", 6))
break; break;
return Intrinsic::hexagon_C2_cmpgei; // "__builtin_HEXAG switch (BuiltinName[29]) {
ON.C2.cmpgei"
case 't': // 3 strings to match.
switch (BuiltinName[26]) {
default: break; default: break;
case 'i': // 1 string to match. case 'h': // 1 string to match.
return Intrinsic::hexagon_C2_cmpgti; // "__builtin_HEXAG return Intrinsic::hexagon_M2_vabsdiffh; // "__builtin_HEXAG
ON.C2.cmpgti" ON_M2_vabsdiffh"
case 'p': // 1 string to match. case 'w': // 1 string to match.
return Intrinsic::hexagon_C2_cmpgtp; // "__builtin_HEXAG return Intrinsic::hexagon_M2_vabsdiffw; // "__builtin_HEXAG
ON.C2.cmpgtp" ON_M2_vabsdiffw"
case 'u': // 1 string to match.
return Intrinsic::hexagon_C2_cmpgtu; // "__builtin_HEXAG
ON.C2.cmpgtu"
} }
break; break;
} case 'd': // 4 strings to match.
break; if (BuiltinName[23] != 'm')
case 'l': // 1 string to match.
if (BuiltinName.substr(25, 2) != "tu")
break;
return Intrinsic::hexagon_C2_cmpltu; // "__builtin_HEXAGON.C2.cm
pltu"
}
break;
case '4': // 5 strings to match.
if (BuiltinName[20] != '.')
break;
switch (BuiltinName[21]) {
default: break;
case 'a': // 1 string to match.
if (BuiltinName.substr(22, 5) != "nd_or")
break;
return Intrinsic::hexagon_C4_and_or; // "__builtin_HEXAGON.C4.an
d_or"
case 'c': // 2 strings to match.
if (BuiltinName.substr(22, 2) != "mp")
break;
switch (BuiltinName[24]) {
default: break;
case 'l': // 1 string to match.
if (BuiltinName.substr(25, 2) != "te")
break;
return Intrinsic::hexagon_C4_cmplte; // "__builtin_HEXAG
ON.C4.cmplte"
case 'n': // 1 string to match.
if (BuiltinName.substr(25, 2) != "eq")
break;
return Intrinsic::hexagon_C4_cmpneq; // "__builtin_HEXAG
ON.C4.cmpneq"
}
break;
case 'o': // 2 strings to match.
if (BuiltinName.substr(22, 2) != "r_")
break;
switch (BuiltinName[24]) {
default: break;
case 'a': // 1 string to match.
if (BuiltinName.substr(25, 2) != "nd")
break; break;
return Intrinsic::hexagon_C4_or_and; // "__builtin_HEXAG switch (BuiltinName[24]) {
ON.C4.or_and" default: break;
case 'o': // 1 string to match. case 'a': // 2 strings to match.
if (BuiltinName.substr(25, 2) != "rn") if (memcmp(BuiltinName.data()+25, "cs_s", 4))
break;
switch (BuiltinName[29]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_vdmacs_s0; // "__built
in_HEXAGON_M2_vdmacs_s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_vdmacs_s1; // "__built
in_HEXAGON_M2_vdmacs_s1"
}
break; break;
return Intrinsic::hexagon_C4_or_orn; // "__builtin_HEXAG case 'p': // 2 strings to match.
ON.C4.or_orn" if (memcmp(BuiltinName.data()+25, "ys_s", 4))
} break;
break; switch (BuiltinName[29]) {
} default: break;
break; case '0': // 1 string to match.
} return Intrinsic::hexagon_M2_vdmpys_s0; // "__built
break; in_HEXAGON_M2_vdmpys_s0"
case 'M': // 10 strings to match. case '1': // 1 string to match.
switch (BuiltinName[19]) { return Intrinsic::hexagon_M2_vdmpys_s1; // "__built
default: break; in_HEXAGON_M2_vdmpys_s1"
case '2': // 6 strings to match. }
if (BuiltinName[20] != '.')
break;
switch (BuiltinName[21]) {
default: break;
case 'm': // 4 strings to match.
switch (BuiltinName[22]) {
default: break;
case 'a': // 2 strings to match.
if (BuiltinName.substr(23, 3) != "csi")
break; break;
switch (BuiltinName[26]) {
default: break;
case 'n': // 1 string to match.
return Intrinsic::hexagon_M2_macsin; // "__builtin_HEXAG
ON.M2.macsin"
case 'p': // 1 string to match.
return Intrinsic::hexagon_M2_macsip; // "__builtin_HEXAG
ON.M2.macsip"
} }
break; break;
case 'p': // 2 strings to match. case 'm': // 4 strings to match.
if (BuiltinName[23] != 'y') switch (BuiltinName[23]) {
break;
switch (BuiltinName[24]) {
default: break; default: break;
case '.': // 1 string to match. case 'a': // 2 strings to match.
if (BuiltinName.substr(25, 2) != "up") if (memcmp(BuiltinName.data()+24, "c2s_s", 5))
break; break;
return Intrinsic::hexagon_M2_mpy_up; // "__builtin_HEXAG switch (BuiltinName[29]) {
ON.M2.mpy.up" default: break;
case 's': // 1 string to match. case '0': // 1 string to match.
if (BuiltinName.substr(25, 2) != "mi") return Intrinsic::hexagon_M2_vmac2s_s0; // "__built
in_HEXAGON_M2_vmac2s_s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_vmac2s_s1; // "__built
in_HEXAGON_M2_vmac2s_s1"
}
break;
case 'p': // 2 strings to match.
if (memcmp(BuiltinName.data()+24, "y2s_s", 5))
break; break;
return Intrinsic::hexagon_M2_mpysmi; // "__builtin_HEXAG switch (BuiltinName[29]) {
ON.M2.mpysmi" default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_vmpy2s_s0; // "__built
in_HEXAGON_M2_vmpy2s_s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_vmpy2s_s1; // "__built
in_HEXAGON_M2_vmpy2s_s1"
}
break;
} }
break; break;
} }
break; break;
case 'n': // 1 string to match.
if (BuiltinName.substr(22, 5) != "accii")
break;
return Intrinsic::hexagon_M2_naccii; // "__builtin_HEXAGON.M2.na
ccii"
case 's': // 1 string to match.
if (BuiltinName.substr(22, 5) != "ubacc")
break;
return Intrinsic::hexagon_M2_subacc; // "__builtin_HEXAGON.M2.su
bacc"
} }
break; break;
case '4': // 4 strings to match. case '4': // 3 strings to match.
if (BuiltinName[20] != '.') if (BuiltinName[20] != '_')
break; break;
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case 'a': // 1 string to match. case 'c': // 2 strings to match.
if (BuiltinName.substr(22, 5) != "nd_or") if (memcmp(BuiltinName.data()+22, "mpy", 3))
break;
return Intrinsic::hexagon_M4_and_or; // "__builtin_HEXAGON.M4.an
d_or"
case 'o': // 2 strings to match.
if (BuiltinName.substr(22, 2) != "r_")
break; break;
switch (BuiltinName[24]) { switch (BuiltinName[25]) {
default: break; default: break;
case 'a': // 1 string to match. case 'i': // 1 string to match.
if (BuiltinName.substr(25, 2) != "nd") if (memcmp(BuiltinName.data()+26, "_whc", 4))
break; break;
return Intrinsic::hexagon_M4_or_and; // "__builtin_HEXAG return Intrinsic::hexagon_M4_cmpyi_whc; // "__builtin_HEXAG
ON.M4.or_and" ON_M4_cmpyi_whc"
case 'x': // 1 string to match. case 'r': // 1 string to match.
if (BuiltinName.substr(25, 2) != "or") if (memcmp(BuiltinName.data()+26, "_whc", 4))
break; break;
return Intrinsic::hexagon_M4_or_xor; // "__builtin_HEXAG ON.M4.or_xor" return Intrinsic::hexagon_M4_cmpyr_whc; // "__builtin_HEXAG ON_M4_cmpyr_whc"
} }
break; break;
case 'x': // 1 string to match. case 'p': // 1 string to match.
if (BuiltinName.substr(22, 5) != "or_or") if (memcmp(BuiltinName.data()+22, "mpyw_acc", 8))
break; break;
return Intrinsic::hexagon_M4_xor_or; // "__builtin_HEXAGON.M4.xo r_or" return Intrinsic::hexagon_M4_pmpyw_acc; // "__builtin_HEXAG ON_M4_pmpyw_acc"
} }
break; break;
} }
break; break;
case 'S': // 9 strings to match. case 'S': // 12 strings to match.
switch (BuiltinName[19]) { switch (BuiltinName[19]) {
default: break; default: break;
case '2': // 8 strings to match. case '2': // 4 strings to match.
if (BuiltinName[20] != '.') if (BuiltinName[20] != '_')
break; break;
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case 'e': // 1 string to match.
if (memcmp(BuiltinName.data()+22, "xtractup", 8))
break;
return Intrinsic::hexagon_S2_extractup; // "__builtin_HEXAG
ON_S2_extractup"
case 'i': // 1 string to match. case 'i': // 1 string to match.
if (BuiltinName.substr(22, 5) != "nsert") if (memcmp(BuiltinName.data()+22, "nsert_rp", 8))
break; break;
return Intrinsic::hexagon_S2_insert; // "__builtin_HEXAGON.S2.in return Intrinsic::hexagon_S2_insert_rp; // "__builtin_HEXAG
sert" ON_S2_insert_rp"
case 'p': // 1 string to match. case 'v': // 2 strings to match.
if (BuiltinName.substr(22, 5) != "ackhl") if (memcmp(BuiltinName.data()+22, "splice", 6))
break; break;
return Intrinsic::hexagon_S2_packhl; // "__builtin_HEXAGON.S2.pa switch (BuiltinName[28]) {
ckhl"
case 'v': // 6 strings to match.
switch (BuiltinName[22]) {
default: break; default: break;
case 's': // 4 strings to match. case 'i': // 1 string to match.
switch (BuiltinName[23]) { if (BuiltinName[29] != 'b')
default: break;
case 'a': // 2 strings to match.
if (BuiltinName[24] != 't')
break;
switch (BuiltinName[25]) {
default: break;
case 'h': // 1 string to match.
if (BuiltinName[26] != 'b')
break;
return Intrinsic::hexagon_S2_vsathb; // "__builtin_HEXAG
ON.S2.vsathb"
case 'w': // 1 string to match.
if (BuiltinName[26] != 'h')
break;
return Intrinsic::hexagon_S2_vsatwh; // "__builtin_HEXAG
ON.S2.vsatwh"
}
break;
case 'x': // 2 strings to match.
if (BuiltinName[24] != 't')
break;
switch (BuiltinName[25]) {
default: break;
case 'b': // 1 string to match.
if (BuiltinName[26] != 'h')
break;
return Intrinsic::hexagon_S2_vsxtbh; // "__builtin_HEXAG
ON.S2.vsxtbh"
case 'h': // 1 string to match.
if (BuiltinName[26] != 'w')
break;
return Intrinsic::hexagon_S2_vsxthw; // "__builtin_HEXAG
ON.S2.vsxthw"
}
break; break;
} return Intrinsic::hexagon_S2_vspliceib; // "__builtin_HEXAG
break; ON_S2_vspliceib"
case 'z': // 2 strings to match. case 'r': // 1 string to match.
if (BuiltinName.substr(23, 2) != "xt") if (BuiltinName[29] != 'b')
break; break;
switch (BuiltinName[25]) { return Intrinsic::hexagon_S2_vsplicerb; // "__builtin_HEXAG
default: break; ON_S2_vsplicerb"
case 'b': // 1 string to match.
if (BuiltinName[26] != 'h')
break;
return Intrinsic::hexagon_S2_vzxtbh; // "__builtin_HEXAG
ON.S2.vzxtbh"
case 'h': // 1 string to match.
if (BuiltinName[26] != 'w')
break;
return Intrinsic::hexagon_S2_vzxthw; // "__builtin_HEXAG
ON.S2.vzxthw"
}
break;
} }
break; break;
} }
break; break;
case '4': // 1 string to match. case '4': // 7 strings to match.
if (BuiltinName.substr(20, 7) != ".or_ori") if (BuiltinName[20] != '_')
break;
return Intrinsic::hexagon_S4_or_ori; // "__builtin_HEXAGON.S4.or
_ori"
}
break;
}
break;
case 28: // 71 strings to match.
if (BuiltinName.substr(0, 18) != "__builtin_HEXAGON.")
break;
switch (BuiltinName[18]) {
default: break;
case 'A': // 25 strings to match.
switch (BuiltinName[19]) {
default: break;
case '2': // 23 strings to match.
if (BuiltinName[20] != '.')
break; break;
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case 'a': // 1 string to match. case 'n': // 2 strings to match.
if (BuiltinName.substr(22, 6) != "ddpsat") if (memcmp(BuiltinName.data()+22, "tstbit_", 7))
break;
return Intrinsic::hexagon_A2_addpsat; // "__builtin_HEXAG
ON.A2.addpsat"
case 's': // 4 strings to match.
if (BuiltinName[22] != 'v')
break; break;
switch (BuiltinName[23]) { switch (BuiltinName[29]) {
default: break; default: break;
case 'a': // 2 strings to match. case 'i': // 1 string to match.
switch (BuiltinName[24]) { return Intrinsic::hexagon_S4_ntstbit_i; // "__builtin_HEXAG
default: break; ON_S4_ntstbit_i"
case 'd': // 1 string to match. case 'r': // 1 string to match.
if (BuiltinName.substr(25, 3) != "dhs") return Intrinsic::hexagon_S4_ntstbit_r; // "__builtin_HEXAG
break; ON_S4_ntstbit_r"
return Intrinsic::hexagon_A2_svaddhs; // "__builtin_HEXAG
ON.A2.svaddhs"
case 'v': // 1 string to match.
if (BuiltinName.substr(25, 3) != "ghs")
break;
return Intrinsic::hexagon_A2_svavghs; // "__builtin_HEXAG
ON.A2.svavghs"
}
break;
case 'n': // 1 string to match.
if (BuiltinName.substr(24, 4) != "avgh")
break;
return Intrinsic::hexagon_A2_svnavgh; // "__builtin_HEXAG
ON.A2.svnavgh"
case 's': // 1 string to match.
if (BuiltinName.substr(24, 4) != "ubhs")
break;
return Intrinsic::hexagon_A2_svsubhs; // "__builtin_HEXAG
ON.A2.svsubhs"
} }
break; break;
case 'v': // 18 strings to match. case 'v': // 5 strings to match.
switch (BuiltinName[22]) { switch (BuiltinName[22]) {
default: break; default: break;
case 'a': // 7 strings to match. case 'r': // 1 string to match.
if (memcmp(BuiltinName.data()+23, "crotate", 7))
break;
return Intrinsic::hexagon_S4_vrcrotate; // "__builtin_HEXAG
ON_S4_vrcrotate"
case 'x': // 4 strings to match.
switch (BuiltinName[23]) { switch (BuiltinName[23]) {
default: break; default: break;
case 'd': // 2 strings to match. case 'a': // 2 strings to match.
if (BuiltinName.substr(24, 2) != "du") if (memcmp(BuiltinName.data()+24, "ddsub", 5))
break; break;
switch (BuiltinName[26]) { switch (BuiltinName[29]) {
default: break; default: break;
case 'b': // 1 string to match.
if (BuiltinName[27] != 's')
break;
return Intrinsic::hexagon_A2_vaddubs; // "__builtin_HEXAG
ON.A2.vaddubs"
case 'h': // 1 string to match. case 'h': // 1 string to match.
if (BuiltinName[27] != 's') return Intrinsic::hexagon_S4_vxaddsubh; // "__built
break; in_HEXAGON_S4_vxaddsubh"
return Intrinsic::hexagon_A2_vadduhs; // "__builtin_HEXAG case 'w': // 1 string to match.
ON.A2.vadduhs" return Intrinsic::hexagon_S4_vxaddsubw; // "__built
in_HEXAGON_S4_vxaddsubw"
} }
break; break;
case 'v': // 5 strings to match. case 's': // 2 strings to match.
if (BuiltinName[24] != 'g') if (memcmp(BuiltinName.data()+24, "ubadd", 5))
break; break;
switch (BuiltinName[25]) { switch (BuiltinName[29]) {
default: break; default: break;
case 'h': // 1 string to match. case 'h': // 1 string to match.
if (BuiltinName.substr(26, 2) != "cr") return Intrinsic::hexagon_S4_vxsubaddh; // "__built
break; in_HEXAGON_S4_vxsubaddh"
return Intrinsic::hexagon_A2_vavghcr; // "__builtin_HEXAG
ON.A2.vavghcr"
case 'u': // 3 strings to match.
switch (BuiltinName[26]) {
default: break;
case 'b': // 1 string to match.
if (BuiltinName[27] != 'r')
break;
return Intrinsic::hexagon_A2_vavgubr; // "__built
in_HEXAGON.A2.vavgubr"
case 'h': // 1 string to match.
if (BuiltinName[27] != 'r')
break;
return Intrinsic::hexagon_A2_vavguhr; // "__built
in_HEXAGON.A2.vavguhr"
case 'w': // 1 string to match.
if (BuiltinName[27] != 'r')
break;
return Intrinsic::hexagon_A2_vavguwr; // "__built
in_HEXAGON.A2.vavguwr"
}
break;
case 'w': // 1 string to match. case 'w': // 1 string to match.
if (BuiltinName.substr(26, 2) != "cr") return Intrinsic::hexagon_S4_vxsubaddw; // "__built
break; in_HEXAGON_S4_vxsubaddw"
return Intrinsic::hexagon_A2_vavgwcr; // "__builtin_HEXAG
ON.A2.vavgwcr"
}
break;
}
break;
case 'c': // 5 strings to match.
if (BuiltinName.substr(23, 2) != "mp")
break;
switch (BuiltinName[25]) {
default: break;
case 'b': // 1 string to match.
if (BuiltinName.substr(26, 2) != "eq")
break;
return Intrinsic::hexagon_A2_vcmpbeq; // "__builtin_HEXAG
ON.A2.vcmpbeq"
case 'h': // 2 strings to match.
switch (BuiltinName[26]) {
default: break;
case 'e': // 1 string to match.
if (BuiltinName[27] != 'q')
break;
return Intrinsic::hexagon_A2_vcmpheq; // "__builtin_HEXAG
ON.A2.vcmpheq"
case 'g': // 1 string to match.
if (BuiltinName[27] != 't')
break;
return Intrinsic::hexagon_A2_vcmphgt; // "__builtin_HEXAG
ON.A2.vcmphgt"
}
break;
case 'w': // 2 strings to match.
switch (BuiltinName[26]) {
default: break;
case 'e': // 1 string to match.
if (BuiltinName[27] != 'q')
break;
return Intrinsic::hexagon_A2_vcmpweq; // "__builtin_HEXAG
ON.A2.vcmpweq"
case 'g': // 1 string to match.
if (BuiltinName[27] != 't')
break;
return Intrinsic::hexagon_A2_vcmpwgt; // "__builtin_HEXAG
ON.A2.vcmpwgt"
} }
break; break;
} }
break; break;
case 'n': // 2 strings to match.
if (BuiltinName.substr(23, 3) != "avg")
break;
switch (BuiltinName[26]) {
default: break;
case 'h': // 1 string to match.
if (BuiltinName[27] != 'r')
break;
return Intrinsic::hexagon_A2_vnavghr; // "__builtin_HEXAG
ON.A2.vnavghr"
case 'w': // 1 string to match.
if (BuiltinName[27] != 'r')
break;
return Intrinsic::hexagon_A2_vnavgwr; // "__builtin_HEXAG
ON.A2.vnavgwr"
}
break;
case 'r': // 2 strings to match.
switch (BuiltinName[23]) {
default: break;
case 'a': // 1 string to match.
if (BuiltinName.substr(24, 4) != "ddub")
break;
return Intrinsic::hexagon_A2_vraddub; // "__builtin_HEXAG
ON.A2.vraddub"
case 's': // 1 string to match.
if (BuiltinName.substr(24, 4) != "adub")
break;
return Intrinsic::hexagon_A2_vrsadub; // "__builtin_HEXAG
ON.A2.vrsadub"
}
break;
case 's': // 2 strings to match.
if (BuiltinName.substr(23, 3) != "ubu")
break;
switch (BuiltinName[26]) {
default: break;
case 'b': // 1 string to match.
if (BuiltinName[27] != 's')
break;
return Intrinsic::hexagon_A2_vsububs; // "__builtin_HEXAG
ON.A2.vsububs"
case 'h': // 1 string to match.
if (BuiltinName[27] != 's')
break;
return Intrinsic::hexagon_A2_vsubuhs; // "__builtin_HEXAG
ON.A2.vsubuhs"
}
break;
} }
break; break;
} }
break; break;
case '4': // 2 strings to match. case '5': // 1 string to match.
if (BuiltinName.substr(20, 5) != ".rcmp") if (memcmp(BuiltinName.data()+20, "_popcountp", 10))
break; break;
switch (BuiltinName[25]) { return Intrinsic::hexagon_S5_popcountp; // "__builtin_HEXAG
ON_S5_popcountp"
}
break;
}
break;
case 31: // 95 strings to match.
if (memcmp(BuiltinName.data()+0, "__builtin_HEXAGON_", 18))
break;
switch (BuiltinName[18]) {
default: break;
case 'A': // 4 strings to match.
if (memcmp(BuiltinName.data()+19, "2_combine_", 10))
break;
switch (BuiltinName[29]) {
default: break;
case 'h': // 2 strings to match.
switch (BuiltinName[30]) {
default: break; default: break;
case 'e': // 1 string to match. case 'h': // 1 string to match.
if (BuiltinName.substr(26, 2) != "qi") return Intrinsic::hexagon_A2_combine_hh; // "__builtin_HEXAG
break; ON_A2_combine_hh"
return Intrinsic::hexagon_A4_rcmpeqi; // "__builtin_HEXAG case 'l': // 1 string to match.
ON.A4.rcmpeqi" return Intrinsic::hexagon_A2_combine_hl; // "__builtin_HEXAG
case 'n': // 1 string to match. ON_A2_combine_hl"
if (BuiltinName.substr(26, 2) != "eq") }
break; break;
return Intrinsic::hexagon_A4_rcmpneq; // "__builtin_HEXAG case 'l': // 2 strings to match.
ON.A4.rcmpneq" switch (BuiltinName[30]) {
default: break;
case 'h': // 1 string to match.
return Intrinsic::hexagon_A2_combine_lh; // "__builtin_HEXAG
ON_A2_combine_lh"
case 'l': // 1 string to match.
return Intrinsic::hexagon_A2_combine_ll; // "__builtin_HEXAG
ON_A2_combine_ll"
} }
break; break;
} }
break; break;
case 'C': // 12 strings to match. case 'F': // 10 strings to match.
switch (BuiltinName[19]) { if (memcmp(BuiltinName.data()+19, "2_conv_", 7))
break;
switch (BuiltinName[26]) {
default: break; default: break;
case '2': // 6 strings to match. case 'd': // 3 strings to match.
if (BuiltinName[20] != '.') if (memcmp(BuiltinName.data()+27, "f2", 2))
break; break;
switch (BuiltinName[21]) { switch (BuiltinName[29]) {
default: break; default: break;
case 'b': // 2 strings to match. case 's': // 1 string to match.
if (BuiltinName.substr(22, 3) != "its") if (BuiltinName[30] != 'f')
break; break;
switch (BuiltinName[25]) { return Intrinsic::hexagon_F2_conv_df2sf; // "__builtin_HEXAG
ON_F2_conv_df2sf"
case 'u': // 2 strings to match.
switch (BuiltinName[30]) {
default: break; default: break;
case 'c': // 1 string to match. case 'd': // 1 string to match.
if (BuiltinName.substr(26, 2) != "lr") return Intrinsic::hexagon_F2_conv_df2ud; // "__builtin_HEXAG
break; ON_F2_conv_df2ud"
return Intrinsic::hexagon_C2_bitsclr; // "__builtin_HEXAG case 'w': // 1 string to match.
ON.C2.bitsclr" return Intrinsic::hexagon_F2_conv_df2uw; // "__builtin_HEXAG
case 's': // 1 string to match. ON_F2_conv_df2uw"
if (BuiltinName.substr(26, 2) != "et")
break;
return Intrinsic::hexagon_C2_bitsset; // "__builtin_HEXAG
ON.C2.bitsset"
} }
break; break;
case 'c': // 3 strings to match. }
if (BuiltinName.substr(22, 3) != "mpg") break;
case 's': // 3 strings to match.
if (memcmp(BuiltinName.data()+27, "f2", 2))
break;
switch (BuiltinName[29]) {
default: break;
case 'd': // 1 string to match.
if (BuiltinName[30] != 'f')
break; break;
switch (BuiltinName[25]) { return Intrinsic::hexagon_F2_conv_sf2df; // "__builtin_HEXAG
ON_F2_conv_sf2df"
case 'u': // 2 strings to match.
switch (BuiltinName[30]) {
default: break; default: break;
case 'e': // 1 string to match. case 'd': // 1 string to match.
if (BuiltinName.substr(26, 2) != "ui") return Intrinsic::hexagon_F2_conv_sf2ud; // "__builtin_HEXAG
break; ON_F2_conv_sf2ud"
return Intrinsic::hexagon_C2_cmpgeui; // "__builtin_HEXAG case 'w': // 1 string to match.
ON.C2.cmpgeui" return Intrinsic::hexagon_F2_conv_sf2uw; // "__builtin_HEXAG
case 't': // 2 strings to match. ON_F2_conv_sf2uw"
if (BuiltinName[26] != 'u')
break;
switch (BuiltinName[27]) {
default: break;
case 'i': // 1 string to match.
return Intrinsic::hexagon_C2_cmpgtui; // "__builtin_HEXAG
ON.C2.cmpgtui"
case 'p': // 1 string to match.
return Intrinsic::hexagon_C2_cmpgtup; // "__builtin_HEXAG
ON.C2.cmpgtup"
}
break;
} }
break; break;
case 'v': // 1 string to match.
if (BuiltinName.substr(22, 6) != "itpack")
break;
return Intrinsic::hexagon_C2_vitpack; // "__builtin_HEXAG
ON.C2.vitpack"
} }
break; break;
case '4': // 6 strings to match. case 'u': // 4 strings to match.
if (BuiltinName[20] != '.') switch (BuiltinName[27]) {
break;
switch (BuiltinName[21]) {
default: break; default: break;
case 'a': // 2 strings to match. case 'd': // 2 strings to match.
if (BuiltinName.substr(22, 3) != "nd_") if (BuiltinName[28] != '2')
break; break;
switch (BuiltinName[25]) { switch (BuiltinName[29]) {
default: break; default: break;
case 'a': // 1 string to match. case 'd': // 1 string to match.
if (BuiltinName.substr(26, 2) != "nd") if (BuiltinName[30] != 'f')
break; break;
return Intrinsic::hexagon_C4_and_and; // "__builtin_HEXAG return Intrinsic::hexagon_F2_conv_ud2df; // "__builtin_HEXAG
ON.C4.and_and" ON_F2_conv_ud2df"
case 'o': // 1 string to match. case 's': // 1 string to match.
if (BuiltinName.substr(26, 2) != "rn") if (BuiltinName[30] != 'f')
break; break;
return Intrinsic::hexagon_C4_and_orn; // "__builtin_HEXAG ON.C4.and_orn" return Intrinsic::hexagon_F2_conv_ud2sf; // "__builtin_HEXAG ON_F2_conv_ud2sf"
} }
break; break;
case 'c': // 3 strings to match. case 'w': // 2 strings to match.
if (BuiltinName.substr(22, 2) != "mp") if (BuiltinName[28] != '2')
break; break;
switch (BuiltinName[24]) { switch (BuiltinName[29]) {
default: break; default: break;
case 'l': // 2 strings to match. case 'd': // 1 string to match.
if (BuiltinName.substr(25, 2) != "te") if (BuiltinName[30] != 'f')
break; break;
switch (BuiltinName[27]) { return Intrinsic::hexagon_F2_conv_uw2df; // "__builtin_HEXAG
default: break; ON_F2_conv_uw2df"
case 'i': // 1 string to match. case 's': // 1 string to match.
return Intrinsic::hexagon_C4_cmpltei; // "__builtin_HEXAG if (BuiltinName[30] != 'f')
ON.C4.cmpltei"
case 'u': // 1 string to match.
return Intrinsic::hexagon_C4_cmplteu; // "__builtin_HEXAG
ON.C4.cmplteu"
}
break;
case 'n': // 1 string to match.
if (BuiltinName.substr(25, 3) != "eqi")
break; break;
return Intrinsic::hexagon_C4_cmpneqi; // "__builtin_HEXAG ON.C4.cmpneqi" return Intrinsic::hexagon_F2_conv_uw2sf; // "__builtin_HEXAG ON_F2_conv_uw2sf"
} }
break; break;
case 'o': // 1 string to match.
if (BuiltinName.substr(22, 6) != "r_andn")
break;
return Intrinsic::hexagon_C4_or_andn; // "__builtin_HEXAG
ON.C4.or_andn"
} }
break; break;
} }
break; break;
case 'M': // 7 strings to match. case 'M': // 58 strings to match.
switch (BuiltinName[19]) { switch (BuiltinName[19]) {
default: break; default: break;
case '2': // 3 strings to match. case '2': // 49 strings to match.
if (BuiltinName[20] != '.') if (BuiltinName[20] != '_')
break; break;
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case 'm': // 1 string to match. case 'c': // 2 strings to match.
if (BuiltinName.substr(22, 6) != "pyu.up") if (memcmp(BuiltinName.data()+22, "mpyrsc_s", 8))
break; break;
return Intrinsic::hexagon_M2_mpyu_up; // "__builtin_HEXAG switch (BuiltinName[30]) {
ON.M2.mpyu.up"
case 'v': // 2 strings to match.
switch (BuiltinName[22]) {
default: break; default: break;
case 'm': // 1 string to match. case '0': // 1 string to match.
if (BuiltinName.substr(23, 5) != "ac2es") return Intrinsic::hexagon_M2_cmpyrsc_s0; // "__builtin_HEXAG
break; ON_M2_cmpyrsc_s0"
return Intrinsic::hexagon_M2_vmac2es; // "__builtin_HEXAG case '1': // 1 string to match.
ON.M2.vmac2es" return Intrinsic::hexagon_M2_cmpyrsc_s1; // "__builtin_HEXAG
case 'r': // 1 string to match. ON_M2_cmpyrsc_s1"
if (BuiltinName.substr(23, 5) != "adduh")
break;
return Intrinsic::hexagon_M2_vradduh; // "__builtin_HEXAG
ON.M2.vradduh"
} }
break; break;
} case 'd': // 2 strings to match.
break; if (memcmp(BuiltinName.data()+22, "pmpy", 4))
case '4': // 4 strings to match.
if (BuiltinName[20] != '.')
break;
switch (BuiltinName[21]) {
default: break;
case 'a': // 2 strings to match.
if (BuiltinName.substr(22, 3) != "nd_")
break; break;
switch (BuiltinName[25]) { switch (BuiltinName[26]) {
default: break; default: break;
case 'a': // 1 string to match. case 's': // 1 string to match.
if (BuiltinName.substr(26, 2) != "nd") if (memcmp(BuiltinName.data()+27, "s_s0", 4))
break; break;
return Intrinsic::hexagon_M4_and_and; // "__builtin_HEXAG return Intrinsic::hexagon_M2_dpmpyss_s0; // "__builtin_HEXAG
ON.M4.and_and" ON_M2_dpmpyss_s0"
case 'x': // 1 string to match. case 'u': // 1 string to match.
if (BuiltinName.substr(26, 2) != "or") if (memcmp(BuiltinName.data()+27, "u_s0", 4))
break; break;
return Intrinsic::hexagon_M4_and_xor; // "__builtin_HEXAG ON.M4.and_xor" return Intrinsic::hexagon_M2_dpmpyuu_s0; // "__builtin_HEXAG ON_M2_dpmpyuu_s0"
} }
break; break;
case 'o': // 1 string to match. case 'h': // 2 strings to match.
if (BuiltinName.substr(22, 6) != "r_andn") if (memcmp(BuiltinName.data()+22, "mmpy", 4))
break;
return Intrinsic::hexagon_M4_or_andn; // "__builtin_HEXAG
ON.M4.or_andn"
case 'x': // 1 string to match.
if (BuiltinName.substr(22, 6) != "or_and")
break;
return Intrinsic::hexagon_M4_xor_and; // "__builtin_HEXAG
ON.M4.xor_and"
}
break;
}
break;
case 'S': // 27 strings to match.
switch (BuiltinName[19]) {
default: break;
case '2': // 24 strings to match.
if (BuiltinName[20] != '.')
break;
switch (BuiltinName[21]) {
default: break;
case 'a': // 8 strings to match.
if (BuiltinName[22] != 's')
break; break;
switch (BuiltinName[23]) { switch (BuiltinName[26]) {
default: break; default: break;
case 'l': // 4 strings to match. case 'h': // 1 string to match.
if (BuiltinName[24] != '.') if (memcmp(BuiltinName.data()+27, "_rs1", 4))
break; break;
switch (BuiltinName[25]) { return Intrinsic::hexagon_M2_hmmpyh_rs1; // "__builtin_HEXAG
ON_M2_hmmpyh_rs1"
case 'l': // 1 string to match.
if (memcmp(BuiltinName.data()+27, "_rs1", 4))
break;
return Intrinsic::hexagon_M2_hmmpyl_rs1; // "__builtin_HEXAG
ON_M2_hmmpyl_rs1"
}
break;
case 'm': // 28 strings to match.
switch (BuiltinName[22]) {
default: break;
case 'm': // 12 strings to match.
switch (BuiltinName[23]) {
default: break; default: break;
case 'i': // 2 strings to match. case 'a': // 8 strings to match.
if (BuiltinName[26] != '.') if (BuiltinName[24] != 'c')
break; break;
switch (BuiltinName[27]) { switch (BuiltinName[25]) {
default: break; default: break;
case 'p': // 1 string to match. case 'h': // 2 strings to match.
return Intrinsic::hexagon_S2_asl_i_p; // "__builtin_HEXAG if (memcmp(BuiltinName.data()+26, "s_rs", 4))
ON.S2.asl.i.p" break;
case 'r': // 1 string to match. switch (BuiltinName[30]) {
return Intrinsic::hexagon_S2_asl_i_r; // "__builtin_HEXAG default: break;
ON.S2.asl.i.r" case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mmachs_rs0; // "__built
in_HEXAGON_M2_mmachs_rs0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mmachs_rs1; // "__built
in_HEXAGON_M2_mmachs_rs1"
}
break;
case 'l': // 2 strings to match.
if (memcmp(BuiltinName.data()+26, "s_rs", 4))
break;
switch (BuiltinName[30]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mmacls_rs0; // "__built
in_HEXAGON_M2_mmacls_rs0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mmacls_rs1; // "__built
in_HEXAGON_M2_mmacls_rs1"
}
break;
case 'u': // 4 strings to match.
switch (BuiltinName[26]) {
default: break;
case 'h': // 2 strings to match.
if (memcmp(BuiltinName.data()+27, "s_s", 3))
break;
switch (BuiltinName[30]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mmacuhs_s0; // "__built
in_HEXAGON_M2_mmacuhs_s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mmacuhs_s1; // "__built
in_HEXAGON_M2_mmacuhs_s1"
}
break;
case 'l': // 2 strings to match.
if (memcmp(BuiltinName.data()+27, "s_s", 3))
break;
switch (BuiltinName[30]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mmaculs_s0; // "__built
in_HEXAGON_M2_mmaculs_s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mmaculs_s1; // "__built
in_HEXAGON_M2_mmaculs_s1"
}
break;
}
break;
} }
break; break;
case 'r': // 2 strings to match. case 'p': // 4 strings to match.
if (BuiltinName[26] != '.') if (memcmp(BuiltinName.data()+24, "yu", 2))
break; break;
switch (BuiltinName[27]) { switch (BuiltinName[26]) {
default: break; default: break;
case 'p': // 1 string to match. case 'h': // 2 strings to match.
return Intrinsic::hexagon_S2_asl_r_p; // "__builtin_HEXAG if (memcmp(BuiltinName.data()+27, "_rs", 3))
ON.S2.asl.r.p" break;
case 'r': // 1 string to match. switch (BuiltinName[30]) {
return Intrinsic::hexagon_S2_asl_r_r; // "__builtin_HEXAG default: break;
ON.S2.asl.r.r" case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mmpyuh_rs0; // "__built
in_HEXAGON_M2_mmpyuh_rs0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mmpyuh_rs1; // "__built
in_HEXAGON_M2_mmpyuh_rs1"
}
break;
case 'l': // 2 strings to match.
if (memcmp(BuiltinName.data()+27, "_rs", 3))
break;
switch (BuiltinName[30]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mmpyul_rs0; // "__built
in_HEXAGON_M2_mmpyul_rs0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mmpyul_rs1; // "__built
in_HEXAGON_M2_mmpyul_rs1"
}
break;
} }
break; break;
} }
break; break;
case 'r': // 4 strings to match. case 'p': // 16 strings to match.
if (BuiltinName[24] != '.') if (BuiltinName[23] != 'y')
break; break;
switch (BuiltinName[25]) { switch (BuiltinName[24]) {
default: break; default: break;
case 'i': // 2 strings to match. case 'd': // 8 strings to match.
if (BuiltinName[26] != '.') if (BuiltinName[25] != '_')
break; break;
switch (BuiltinName[27]) { switch (BuiltinName[26]) {
default: break; default: break;
case 'p': // 1 string to match. case 'h': // 4 strings to match.
return Intrinsic::hexagon_S2_asr_i_p; // "__builtin_HEXAG switch (BuiltinName[27]) {
ON.S2.asr.i.p" default: break;
case 'r': // 1 string to match. case 'h': // 2 strings to match.
return Intrinsic::hexagon_S2_asr_i_r; // "__builtin_HEXAG if (memcmp(BuiltinName.data()+28, "_s", 2))
ON.S2.asr.i.r" break;
switch (BuiltinName[30]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_hh_s0; // "__built
in_HEXAGON_M2_mpyd_hh_s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_hh_s1; // "__built
in_HEXAGON_M2_mpyd_hh_s1"
}
break;
case 'l': // 2 strings to match.
if (memcmp(BuiltinName.data()+28, "_s", 2))
break;
switch (BuiltinName[30]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_hl_s0; // "__built
in_HEXAGON_M2_mpyd_hl_s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_hl_s1; // "__built
in_HEXAGON_M2_mpyd_hl_s1"
}
break;
}
break;
case 'l': // 4 strings to match.
switch (BuiltinName[27]) {
default: break;
case 'h': // 2 strings to match.
if (memcmp(BuiltinName.data()+28, "_s", 2))
break;
switch (BuiltinName[30]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_lh_s0; // "__built
in_HEXAGON_M2_mpyd_lh_s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_lh_s1; // "__built
in_HEXAGON_M2_mpyd_lh_s1"
}
break;
case 'l': // 2 strings to match.
if (memcmp(BuiltinName.data()+28, "_s", 2))
break;
switch (BuiltinName[30]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_ll_s0; // "__built
in_HEXAGON_M2_mpyd_ll_s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_ll_s1; // "__built
in_HEXAGON_M2_mpyd_ll_s1"
}
break;
}
break;
} }
break; break;
case 'r': // 2 strings to match. case 'u': // 8 strings to match.
if (BuiltinName[26] != '.') if (BuiltinName[25] != '_')
break;
switch (BuiltinName[26]) {
default: break;
case 'h': // 4 strings to match.
switch (BuiltinName[27]) {
default: break;
case 'h': // 2 strings to match.
if (memcmp(BuiltinName.data()+28, "_s", 2))
break;
switch (BuiltinName[30]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyu_hh_s0; // "__built
in_HEXAGON_M2_mpyu_hh_s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyu_hh_s1; // "__built
in_HEXAGON_M2_mpyu_hh_s1"
}
break;
case 'l': // 2 strings to match.
if (memcmp(BuiltinName.data()+28, "_s", 2))
break;
switch (BuiltinName[30]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyu_hl_s0; // "__built
in_HEXAGON_M2_mpyu_hl_s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyu_hl_s1; // "__built
in_HEXAGON_M2_mpyu_hl_s1"
}
break;
}
break;
case 'l': // 4 strings to match.
switch (BuiltinName[27]) {
default: break;
case 'h': // 2 strings to match.
if (memcmp(BuiltinName.data()+28, "_s", 2))
break;
switch (BuiltinName[30]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyu_lh_s0; // "__built
in_HEXAGON_M2_mpyu_lh_s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyu_lh_s1; // "__built
in_HEXAGON_M2_mpyu_lh_s1"
}
break;
case 'l': // 2 strings to match.
if (memcmp(BuiltinName.data()+28, "_s", 2))
break;
switch (BuiltinName[30]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyu_ll_s0; // "__built
in_HEXAGON_M2_mpyu_ll_s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyu_ll_s1; // "__built
in_HEXAGON_M2_mpyu_ll_s1"
}
break;
}
break; break;
switch (BuiltinName[27]) {
default: break;
case 'p': // 1 string to match.
return Intrinsic::hexagon_S2_asr_r_p; // "__builtin_HEXAG
ON.S2.asr.r.p"
case 'r': // 1 string to match.
return Intrinsic::hexagon_S2_asr_r_r; // "__builtin_HEXAG
ON.S2.asr.r.r"
} }
break; break;
} }
break; break;
} }
break; break;
case 'c': // 1 string to match. case 'v': // 15 strings to match.
if (BuiltinName.substr(22, 6) != "lbnorm") switch (BuiltinName[22]) {
break;
return Intrinsic::hexagon_S2_clbnorm; // "__builtin_HEXAG
ON.S2.clbnorm"
case 'i': // 1 string to match.
if (BuiltinName.substr(22, 6) != "nsertp")
break;
return Intrinsic::hexagon_S2_insertp; // "__builtin_HEXAG
ON.S2.insertp"
case 'l': // 6 strings to match.
if (BuiltinName[22] != 's')
break;
switch (BuiltinName[23]) {
default: break; default: break;
case 'l': // 2 strings to match. case 'd': // 2 strings to match.
if (BuiltinName.substr(24, 3) != ".r.") if (memcmp(BuiltinName.data()+23, "mpyrs_s", 7))
break; break;
switch (BuiltinName[27]) { switch (BuiltinName[30]) {
default: break; default: break;
case 'p': // 1 string to match. case '0': // 1 string to match.
return Intrinsic::hexagon_S2_lsl_r_p; // "__builtin_HEXAG return Intrinsic::hexagon_M2_vdmpyrs_s0; // "__builtin_HEXAG
ON.S2.lsl.r.p" ON_M2_vdmpyrs_s0"
case 'r': // 1 string to match. case '1': // 1 string to match.
return Intrinsic::hexagon_S2_lsl_r_r; // "__builtin_HEXAG return Intrinsic::hexagon_M2_vdmpyrs_s1; // "__builtin_HEXAG
ON.S2.lsl.r.r" ON_M2_vdmpyrs_s1"
} }
break; break;
case 'r': // 4 strings to match. case 'm': // 8 strings to match.
if (BuiltinName[24] != '.') switch (BuiltinName[23]) {
break;
switch (BuiltinName[25]) {
default: break; default: break;
case 'i': // 2 strings to match. case 'a': // 4 strings to match.
if (BuiltinName[26] != '.') if (memcmp(BuiltinName.data()+24, "c2", 2))
break; break;
switch (BuiltinName[27]) { switch (BuiltinName[26]) {
default: break; default: break;
case 'p': // 1 string to match. case 'e': // 2 strings to match.
return Intrinsic::hexagon_S2_lsr_i_p; // "__builtin_HEXAG if (memcmp(BuiltinName.data()+27, "s_s", 3))
ON.S2.lsr.i.p" break;
case 'r': // 1 string to match. switch (BuiltinName[30]) {
return Intrinsic::hexagon_S2_lsr_i_r; // "__builtin_HEXAG default: break;
ON.S2.lsr.i.r" case '0': // 1 string to match.
return Intrinsic::hexagon_M2_vmac2es_s0; // "__built
in_HEXAGON_M2_vmac2es_s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_vmac2es_s1; // "__built
in_HEXAGON_M2_vmac2es_s1"
}
break;
case 's': // 2 strings to match.
if (memcmp(BuiltinName.data()+27, "u_s", 3))
break;
switch (BuiltinName[30]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_vmac2su_s0; // "__built
in_HEXAGON_M2_vmac2su_s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_vmac2su_s1; // "__built
in_HEXAGON_M2_vmac2su_s1"
}
break;
} }
break; break;
case 'r': // 2 strings to match. case 'p': // 4 strings to match.
if (BuiltinName[26] != '.') if (memcmp(BuiltinName.data()+24, "y2", 2))
break; break;
switch (BuiltinName[27]) { switch (BuiltinName[26]) {
default: break; default: break;
case 'p': // 1 string to match. case 'e': // 2 strings to match.
return Intrinsic::hexagon_S2_lsr_r_p; // "__builtin_HEXAG if (memcmp(BuiltinName.data()+27, "s_s", 3))
ON.S2.lsr.r.p" break;
case 'r': // 1 string to match. switch (BuiltinName[30]) {
return Intrinsic::hexagon_S2_lsr_r_r; // "__builtin_HEXAG default: break;
ON.S2.lsr.r.r" case '0': // 1 string to match.
return Intrinsic::hexagon_M2_vmpy2es_s0; // "__built
in_HEXAGON_M2_vmpy2es_s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_vmpy2es_s1; // "__built
in_HEXAGON_M2_vmpy2es_s1"
}
break;
case 's': // 2 strings to match.
if (memcmp(BuiltinName.data()+27, "u_s", 3))
break;
switch (BuiltinName[30]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_vmpy2su_s0; // "__built
in_HEXAGON_M2_vmpy2su_s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_vmpy2su_s1; // "__built
in_HEXAGON_M2_vmpy2su_s1"
}
break;
} }
break; break;
} }
break; break;
} case 'r': // 5 strings to match.
break; if (memcmp(BuiltinName.data()+23, "cm", 2))
case 'p': // 1 string to match.
if (BuiltinName.substr(22, 6) != "arityp")
break;
return Intrinsic::hexagon_S2_parityp; // "__builtin_HEXAG
ON.S2.parityp"
case 's': // 5 strings to match.
switch (BuiltinName[22]) {
default: break;
case 'h': // 4 strings to match.
if (BuiltinName.substr(23, 3) != "uff")
break; break;
switch (BuiltinName[26]) { switch (BuiltinName[25]) {
default: break; default: break;
case 'e': // 2 strings to match. case 'a': // 2 strings to match.
if (BuiltinName[26] != 'c')
break;
switch (BuiltinName[27]) { switch (BuiltinName[27]) {
default: break; default: break;
case 'b': // 1 string to match. case 'i': // 1 string to match.
return Intrinsic::hexagon_S2_shuffeb; // "__builtin_HEXAG if (memcmp(BuiltinName.data()+28, "_s0", 3))
ON.S2.shuffeb" break;
case 'h': // 1 string to match. return Intrinsic::hexagon_M2_vrcmaci_s0; // "__built
return Intrinsic::hexagon_S2_shuffeh; // "__builtin_HEXAG in_HEXAGON_M2_vrcmaci_s0"
ON.S2.shuffeh" case 'r': // 1 string to match.
if (memcmp(BuiltinName.data()+28, "_s0", 3))
break;
return Intrinsic::hexagon_M2_vrcmacr_s0; // "__built
in_HEXAGON_M2_vrcmacr_s0"
} }
break; break;
case 'o': // 2 strings to match. case 'p': // 3 strings to match.
if (BuiltinName[26] != 'y')
break;
switch (BuiltinName[27]) { switch (BuiltinName[27]) {
default: break; default: break;
case 'b': // 1 string to match. case 'i': // 1 string to match.
return Intrinsic::hexagon_S2_shuffob; // "__builtin_HEXAG if (memcmp(BuiltinName.data()+28, "_s0", 3))
ON.S2.shuffob" break;
case 'h': // 1 string to match. return Intrinsic::hexagon_M2_vrcmpyi_s0; // "__built
return Intrinsic::hexagon_S2_shuffoh; // "__builtin_HEXAG in_HEXAGON_M2_vrcmpyi_s0"
ON.S2.shuffoh" case 'r': // 1 string to match.
if (memcmp(BuiltinName.data()+28, "_s0", 3))
break;
return Intrinsic::hexagon_M2_vrcmpyr_s0; // "__built
in_HEXAGON_M2_vrcmpyr_s0"
case 's': // 1 string to match.
if (memcmp(BuiltinName.data()+28, "_s1", 3))
break;
return Intrinsic::hexagon_M2_vrcmpys_s1; // "__built
in_HEXAGON_M2_vrcmpys_s1"
} }
break; break;
} }
break; break;
case 'v': // 1 string to match.
if (BuiltinName.substr(23, 5) != "sathb")
break;
return Intrinsic::hexagon_S2_svsathb; // "__builtin_HEXAG
ON.S2.svsathb"
}
break;
case 'v': // 2 strings to match.
if (BuiltinName.substr(22, 3) != "sat")
break;
switch (BuiltinName[25]) {
default: break;
case 'h': // 1 string to match.
if (BuiltinName.substr(26, 2) != "ub")
break;
return Intrinsic::hexagon_S2_vsathub; // "__builtin_HEXAG
ON.S2.vsathub"
case 'w': // 1 string to match.
if (BuiltinName.substr(26, 2) != "uh")
break;
return Intrinsic::hexagon_S2_vsatwuh; // "__builtin_HEXAG
ON.S2.vsatwuh"
} }
break; break;
} }
break; break;
case '4': // 3 strings to match. case '4': // 9 strings to match.
if (BuiltinName[20] != '.') if (BuiltinName[20] != '_')
break;
switch (BuiltinName[21]) {
default: break;
case 'a': // 1 string to match.
if (BuiltinName.substr(22, 6) != "ddaddi")
break;
return Intrinsic::hexagon_S4_addaddi; // "__builtin_HEXAG
ON.S4.addaddi"
case 'o': // 1 string to match.
if (BuiltinName.substr(22, 6) != "r_andi")
break;
return Intrinsic::hexagon_S4_or_andi; // "__builtin_HEXAG
ON.S4.or_andi"
case 's': // 1 string to match.
if (BuiltinName.substr(22, 6) != "ubaddi")
break;
return Intrinsic::hexagon_S4_subaddi; // "__builtin_HEXAG
ON.S4.subaddi"
}
break;
}
break;
}
break;
case 29: // 69 strings to match.
if (BuiltinName.substr(0, 18) != "__builtin_HEXAGON.")
break;
switch (BuiltinName[18]) {
default: break;
case 'A': // 14 strings to match.
switch (BuiltinName[19]) {
default: break;
case '2': // 10 strings to match.
if (BuiltinName[20] != '.')
break; break;
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case 'c': // 1 string to match. case 'm': // 4 strings to match.
if (BuiltinName.substr(22, 7) != "ombinew") if (memcmp(BuiltinName.data()+22, "pyr", 3))
break;
return Intrinsic::hexagon_A2_combinew; // "__builtin_HEXAG
ON.A2.combinew"
case 's': // 2 strings to match.
if (BuiltinName[22] != 'v')
break; break;
switch (BuiltinName[23]) { switch (BuiltinName[25]) {
default: break;
case 'a': // 1 string to match.
if (BuiltinName.substr(24, 5) != "dduhs")
break;
return Intrinsic::hexagon_A2_svadduhs; // "__builtin_HEXAG
ON.A2.svadduhs"
case 's': // 1 string to match.
if (BuiltinName.substr(24, 5) != "ubuhs")
break;
return Intrinsic::hexagon_A2_svsubuhs; // "__builtin_HEXAG
ON.A2.svsubuhs"
}
break;
case 'v': // 7 strings to match.
switch (BuiltinName[22]) {
default: break; default: break;
case 'a': // 2 strings to match. case 'i': // 2 strings to match.
if (BuiltinName.substr(23, 2) != "bs") if (memcmp(BuiltinName.data()+26, "_add", 4))
break;
switch (BuiltinName[25]) {
default: break;
case 'h': // 1 string to match.
if (BuiltinName.substr(26, 3) != "sat")
break;
return Intrinsic::hexagon_A2_vabshsat; // "__builtin_HEXAG
ON.A2.vabshsat"
case 'w': // 1 string to match.
if (BuiltinName.substr(26, 3) != "sat")
break;
return Intrinsic::hexagon_A2_vabswsat; // "__builtin_HEXAG
ON.A2.vabswsat"
}
break;
case 'c': // 3 strings to match.
if (BuiltinName.substr(23, 2) != "mp")
break; break;
switch (BuiltinName[25]) { switch (BuiltinName[30]) {
default: break; default: break;
case 'b': // 1 string to match. case 'i': // 1 string to match.
if (BuiltinName.substr(26, 3) != "gtu") return Intrinsic::hexagon_M4_mpyri_addi; // "__builtin_HEXAG
break; ON_M4_mpyri_addi"
return Intrinsic::hexagon_A2_vcmpbgtu; // "__builtin_HEXAG case 'r': // 1 string to match.
ON.A2.vcmpbgtu" return Intrinsic::hexagon_M4_mpyri_addr; // "__builtin_HEXAG
case 'h': // 1 string to match. ON_M4_mpyri_addr"
if (BuiltinName.substr(26, 3) != "gtu")
break;
return Intrinsic::hexagon_A2_vcmphgtu; // "__builtin_HEXAG
ON.A2.vcmphgtu"
case 'w': // 1 string to match.
if (BuiltinName.substr(26, 3) != "gtu")
break;
return Intrinsic::hexagon_A2_vcmpwgtu; // "__builtin_HEXAG
ON.A2.vcmpwgtu"
} }
break; break;
case 'n': // 2 strings to match. case 'r': // 2 strings to match.
if (BuiltinName.substr(23, 3) != "avg") if (memcmp(BuiltinName.data()+26, "_add", 4))
break; break;
switch (BuiltinName[26]) { switch (BuiltinName[30]) {
default: break; default: break;
case 'h': // 1 string to match. case 'i': // 1 string to match.
if (BuiltinName.substr(27, 2) != "cr") return Intrinsic::hexagon_M4_mpyrr_addi; // "__builtin_HEXAG
break; ON_M4_mpyrr_addi"
return Intrinsic::hexagon_A2_vnavghcr; // "__builtin_HEXAG case 'r': // 1 string to match.
ON.A2.vnavghcr" return Intrinsic::hexagon_M4_mpyrr_addr; // "__builtin_HEXAG
case 'w': // 1 string to match. ON_M4_mpyrr_addr"
if (BuiltinName.substr(27, 2) != "cr")
break;
return Intrinsic::hexagon_A2_vnavgwcr; // "__builtin_HEXAG
ON.A2.vnavgwcr"
} }
break; break;
} }
break; break;
} case 'v': // 5 strings to match.
break;
case '4': // 4 strings to match.
if (BuiltinName[20] != '.')
break;
switch (BuiltinName[21]) {
default: break;
case 'm': // 1 string to match.
if (BuiltinName.substr(22, 7) != "odwrapu")
break;
return Intrinsic::hexagon_A4_modwrapu; // "__builtin_HEXAG
ON.A4.modwrapu"
case 'r': // 3 strings to match.
switch (BuiltinName[22]) { switch (BuiltinName[22]) {
default: break; default: break;
case 'c': // 1 string to match. case 'p': // 1 string to match.
if (BuiltinName.substr(23, 6) != "mpneqi") if (memcmp(BuiltinName.data()+23, "mpyh_acc", 8))
break; break;
return Intrinsic::hexagon_A4_rcmpneqi; // "__builtin_HEXAG return Intrinsic::hexagon_M4_vpmpyh_acc; // "__builtin_HEXAG
ON.A4.rcmpneqi" ON_M4_vpmpyh_acc"
case 'o': // 2 strings to match. case 'r': // 4 strings to match.
if (BuiltinName.substr(23, 5) != "und_r") if (memcmp(BuiltinName.data()+23, "mpy", 3))
break; break;
switch (BuiltinName[28]) { switch (BuiltinName[26]) {
default: break; default: break;
case 'i': // 1 string to match. case 'e': // 2 strings to match.
return Intrinsic::hexagon_A4_round_ri; // "__builtin_HEXAG if (memcmp(BuiltinName.data()+27, "h_s", 3))
ON.A4.round_ri" break;
case 'r': // 1 string to match. switch (BuiltinName[30]) {
return Intrinsic::hexagon_A4_round_rr; // "__builtin_HEXAG default: break;
ON.A4.round_rr" case '0': // 1 string to match.
return Intrinsic::hexagon_M4_vrmpyeh_s0; // "__built
in_HEXAGON_M4_vrmpyeh_s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M4_vrmpyeh_s1; // "__built
in_HEXAGON_M4_vrmpyeh_s1"
}
break;
case 'o': // 2 strings to match.
if (memcmp(BuiltinName.data()+27, "h_s", 3))
break;
switch (BuiltinName[30]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M4_vrmpyoh_s0; // "__built
in_HEXAGON_M4_vrmpyoh_s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M4_vrmpyoh_s1; // "__built
in_HEXAGON_M4_vrmpyoh_s1"
}
break;
} }
break; break;
} }
break; break;
} }
break; break;
} }
break; break;
case 'C': // 3 strings to match. case 'S': // 23 strings to match.
switch (BuiltinName[19]) {
default: break;
case '2': // 1 string to match.
if (BuiltinName.substr(20, 9) != ".bitsclri")
break;
return Intrinsic::hexagon_C2_bitsclri; // "__builtin_HEXAGON.C2.bi
tsclri"
case '4': // 2 strings to match.
if (BuiltinName[20] != '.')
break;
switch (BuiltinName[21]) {
default: break;
case 'a': // 1 string to match.
if (BuiltinName.substr(22, 7) != "nd_andn")
break;
return Intrinsic::hexagon_C4_and_andn; // "__builtin_HEXAG
ON.C4.and_andn"
case 'c': // 1 string to match.
if (BuiltinName.substr(22, 7) != "mplteui")
break;
return Intrinsic::hexagon_C4_cmplteui; // "__builtin_HEXAG
ON.C4.cmplteui"
}
break;
}
break;
case 'M': // 20 strings to match.
switch (BuiltinName[19]) { switch (BuiltinName[19]) {
default: break; default: break;
case '2': // 17 strings to match. case '2': // 17 strings to match.
if (BuiltinName[20] != '.') if (BuiltinName[20] != '_')
break; break;
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case 'c': // 10 strings to match. case 'a': // 8 strings to match.
switch (BuiltinName[22]) { if (BuiltinName[22] != 's')
break;
switch (BuiltinName[23]) {
default: break; default: break;
case 'm': // 8 strings to match. case 'l': // 4 strings to match.
switch (BuiltinName[23]) { if (BuiltinName[24] != '_')
break;
switch (BuiltinName[25]) {
default: break; default: break;
case 'a': // 4 strings to match. case 'i': // 2 strings to match.
if (BuiltinName[24] != 'c') if (BuiltinName[26] != '_')
break; break;
switch (BuiltinName[25]) { switch (BuiltinName[27]) {
default: break; default: break;
case 'i': // 1 string to match. case 'p': // 1 string to match.
if (BuiltinName.substr(26, 3) != ".s0") if (memcmp(BuiltinName.data()+28, "_or", 3))
break; break;
return Intrinsic::hexagon_M2_cmaci_s0; // "__builtin_HEXAG ON.M2.cmaci.s0" return Intrinsic::hexagon_S2_asl_i_p_or; // "__built in_HEXAGON_S2_asl_i_p_or"
case 'r': // 1 string to match. case 'r': // 1 string to match.
if (BuiltinName.substr(26, 3) != ".s0") if (memcmp(BuiltinName.data()+28, "_or", 3))
break;
return Intrinsic::hexagon_M2_cmacr_s0; // "__builtin_HEXAG
ON.M2.cmacr.s0"
case 's': // 2 strings to match.
if (BuiltinName.substr(26, 2) != ".s")
break; break;
switch (BuiltinName[28]) { return Intrinsic::hexagon_S2_asl_i_r_or; // "__built
default: break; in_HEXAGON_S2_asl_i_r_or"
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_cmacs_s0; // "__built
in_HEXAGON.M2.cmacs.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_cmacs_s1; // "__built
in_HEXAGON.M2.cmacs.s1"
}
break;
} }
break; break;
case 'p': // 4 strings to match. case 'r': // 2 strings to match.
if (BuiltinName[24] != 'y') if (BuiltinName[26] != '_')
break; break;
switch (BuiltinName[25]) { switch (BuiltinName[27]) {
default: break; default: break;
case 'i': // 1 string to match. case 'p': // 1 string to match.
if (BuiltinName.substr(26, 3) != ".s0") if (memcmp(BuiltinName.data()+28, "_or", 3))
break; break;
return Intrinsic::hexagon_M2_cmpyi_s0; // "__builtin_HEXAG ON.M2.cmpyi.s0" return Intrinsic::hexagon_S2_asl_r_p_or; // "__built in_HEXAGON_S2_asl_r_p_or"
case 'r': // 1 string to match. case 'r': // 1 string to match.
if (BuiltinName.substr(26, 3) != ".s0") if (memcmp(BuiltinName.data()+28, "_or", 3))
break; break;
return Intrinsic::hexagon_M2_cmpyr_s0; // "__builtin_HEXAG return Intrinsic::hexagon_S2_asl_r_r_or; // "__built
ON.M2.cmpyr.s0" in_HEXAGON_S2_asl_r_r_or"
case 's': // 2 strings to match.
if (BuiltinName.substr(26, 2) != ".s")
break;
switch (BuiltinName[28]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_cmpys_s0; // "__built
in_HEXAGON.M2.cmpys.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_cmpys_s1; // "__built
in_HEXAGON.M2.cmpys.s1"
}
break;
} }
break; break;
} }
break; break;
case 'n': // 2 strings to match. case 'r': // 4 strings to match.
if (BuiltinName.substr(23, 5) != "acs.s") if (BuiltinName[24] != '_')
break; break;
switch (BuiltinName[28]) { switch (BuiltinName[25]) {
default: break; default: break;
case '0': // 1 string to match. case 'i': // 2 strings to match.
return Intrinsic::hexagon_M2_cnacs_s0; // "__builtin_HEXAG if (BuiltinName[26] != '_')
ON.M2.cnacs.s0" break;
case '1': // 1 string to match. switch (BuiltinName[27]) {
return Intrinsic::hexagon_M2_cnacs_s1; // "__builtin_HEXAG default: break;
ON.M2.cnacs.s1" case 'p': // 1 string to match.
if (memcmp(BuiltinName.data()+28, "_or", 3))
break;
return Intrinsic::hexagon_S2_asr_i_p_or; // "__built
in_HEXAGON_S2_asr_i_p_or"
case 'r': // 1 string to match.
if (memcmp(BuiltinName.data()+28, "_or", 3))
break;
return Intrinsic::hexagon_S2_asr_i_r_or; // "__built
in_HEXAGON_S2_asr_i_r_or"
}
break;
case 'r': // 2 strings to match.
if (BuiltinName[26] != '_')
break;
switch (BuiltinName[27]) {
default: break;
case 'p': // 1 string to match.
if (memcmp(BuiltinName.data()+28, "_or", 3))
break;
return Intrinsic::hexagon_S2_asr_r_p_or; // "__built
in_HEXAGON_S2_asr_r_p_or"
case 'r': // 1 string to match.
if (memcmp(BuiltinName.data()+28, "_or", 3))
break;
return Intrinsic::hexagon_S2_asr_r_r_or; // "__built
in_HEXAGON_S2_asr_r_r_or"
}
break;
} }
break; break;
} }
break; break;
case 'm': // 4 strings to match. case 'i': // 2 strings to match.
if (BuiltinName.substr(22, 3) != "mpy") if (BuiltinName[22] != 'n')
break; break;
switch (BuiltinName[25]) { switch (BuiltinName[23]) {
default: break; default: break;
case 'h': // 2 strings to match. case 's': // 1 string to match.
if (BuiltinName.substr(26, 2) != ".s") if (memcmp(BuiltinName.data()+24, "ertp_rp", 7))
break; break;
switch (BuiltinName[28]) { return Intrinsic::hexagon_S2_insertp_rp; // "__builtin_HEXAG
default: break; ON_S2_insertp_rp"
case '0': // 1 string to match. case 't': // 1 string to match.
return Intrinsic::hexagon_M2_mmpyh_s0; // "__builtin_HEXAG if (memcmp(BuiltinName.data()+24, "erleave", 7))
ON.M2.mmpyh.s0" break;
case '1': // 1 string to match. return Intrinsic::hexagon_S2_interleave; // "__builtin_HEXAG
return Intrinsic::hexagon_M2_mmpyh_s1; // "__builtin_HEXAG ON_S2_interleave"
ON.M2.mmpyh.s1" }
} break;
case 'l': // 6 strings to match.
if (BuiltinName[22] != 's')
break; break;
switch (BuiltinName[23]) {
default: break;
case 'l': // 2 strings to match. case 'l': // 2 strings to match.
if (BuiltinName.substr(26, 2) != ".s") if (memcmp(BuiltinName.data()+24, "_r_", 3))
break; break;
switch (BuiltinName[28]) { switch (BuiltinName[27]) {
default: break; default: break;
case '0': // 1 string to match. case 'p': // 1 string to match.
return Intrinsic::hexagon_M2_mmpyl_s0; // "__builtin_HEXAG if (memcmp(BuiltinName.data()+28, "_or", 3))
ON.M2.mmpyl.s0" break;
case '1': // 1 string to match. return Intrinsic::hexagon_S2_lsl_r_p_or; // "__builtin_HEXAG
return Intrinsic::hexagon_M2_mmpyl_s1; // "__builtin_HEXAG ON_S2_lsl_r_p_or"
ON.M2.mmpyl.s1" case 'r': // 1 string to match.
if (memcmp(BuiltinName.data()+28, "_or", 3))
break;
return Intrinsic::hexagon_S2_lsl_r_r_or; // "__builtin_HEXAG
ON_S2_lsl_r_r_or"
} }
break; break;
} case 'r': // 4 strings to match.
break; if (BuiltinName[24] != '_')
case 'v': // 2 strings to match.
if (BuiltinName.substr(22, 2) != "rm")
break;
switch (BuiltinName[24]) {
default: break;
case 'a': // 1 string to match.
if (BuiltinName.substr(25, 4) != "c.s0")
break; break;
return Intrinsic::hexagon_M2_vrmac_s0; // "__builtin_HEXAG switch (BuiltinName[25]) {
ON.M2.vrmac.s0" default: break;
case 'p': // 1 string to match. case 'i': // 2 strings to match.
if (BuiltinName.substr(25, 4) != "y.s0") if (BuiltinName[26] != '_')
break;
switch (BuiltinName[27]) {
default: break;
case 'p': // 1 string to match.
if (memcmp(BuiltinName.data()+28, "_or", 3))
break;
return Intrinsic::hexagon_S2_lsr_i_p_or; // "__built
in_HEXAGON_S2_lsr_i_p_or"
case 'r': // 1 string to match.
if (memcmp(BuiltinName.data()+28, "_or", 3))
break;
return Intrinsic::hexagon_S2_lsr_i_r_or; // "__built
in_HEXAGON_S2_lsr_i_r_or"
}
break;
case 'r': // 2 strings to match.
if (BuiltinName[26] != '_')
break;
switch (BuiltinName[27]) {
default: break;
case 'p': // 1 string to match.
if (memcmp(BuiltinName.data()+28, "_or", 3))
break;
return Intrinsic::hexagon_S2_lsr_r_p_or; // "__built
in_HEXAGON_S2_lsr_r_p_or"
case 'r': // 1 string to match.
if (memcmp(BuiltinName.data()+28, "_or", 3))
break;
return Intrinsic::hexagon_S2_lsr_r_r_or; // "__built
in_HEXAGON_S2_lsr_r_r_or"
}
break; break;
return Intrinsic::hexagon_M2_vrmpy_s0; // "__builtin_HEXAG }
ON.M2.vrmpy.s0" break;
} }
break; break;
case 'x': // 1 string to match. case 'v': // 1 string to match.
if (BuiltinName.substr(22, 7) != "or.xacc") if (memcmp(BuiltinName.data()+22, "rndpackwh", 9))
break; break;
return Intrinsic::hexagon_M2_xor_xacc; // "__builtin_HEXAG ON.M2.xor.xacc" return Intrinsic::hexagon_S2_vrndpackwh; // "__builtin_HEXAG ON_S2_vrndpackwh"
} }
break; break;
case '4': // 3 strings to match. case '4': // 5 strings to match.
if (BuiltinName[20] != '.') if (BuiltinName[20] != '_')
break; break;
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case 'a': // 1 string to match. case 'e': // 1 string to match.
if (BuiltinName.substr(22, 7) != "nd_andn") if (memcmp(BuiltinName.data()+22, "xtract_rp", 9))
break; break;
return Intrinsic::hexagon_M4_and_andn; // "__builtin_HEXAG return Intrinsic::hexagon_S4_extract_rp; // "__builtin_HEXAG
ON.M4.and_andn" ON_S4_extract_rp"
case 'x': // 2 strings to match. case 'o': // 2 strings to match.
if (BuiltinName.substr(22, 3) != "or_") if (memcmp(BuiltinName.data()+22, "ri_", 3))
break; break;
switch (BuiltinName[25]) { switch (BuiltinName[25]) {
default: break; default: break;
case 'a': // 1 string to match. case 'a': // 1 string to match.
if (BuiltinName.substr(26, 3) != "ndn") if (memcmp(BuiltinName.data()+26, "sl_ri", 5))
break; break;
return Intrinsic::hexagon_M4_xor_andn; // "__builtin_HEXAG return Intrinsic::hexagon_S4_ori_asl_ri; // "__builtin_HEXAG
ON.M4.xor_andn" ON_S4_ori_asl_ri"
case 'x': // 1 string to match. case 'l': // 1 string to match.
if (BuiltinName.substr(26, 3) != "acc") if (memcmp(BuiltinName.data()+26, "sr_ri", 5))
break;
return Intrinsic::hexagon_S4_ori_lsr_ri; // "__builtin_HEXAG
ON_S4_ori_lsr_ri"
}
break;
case 'v': // 2 strings to match.
if (BuiltinName[22] != 'x')
break;
switch (BuiltinName[23]) {
default: break;
case 'a': // 1 string to match.
if (memcmp(BuiltinName.data()+24, "ddsubhr", 7))
break; break;
return Intrinsic::hexagon_M4_xor_xacc; // "__builtin_HEXAG return Intrinsic::hexagon_S4_vxaddsubhr; // "__builtin_HEXAG
ON.M4.xor_xacc" ON_S4_vxaddsubhr"
case 's': // 1 string to match.
if (memcmp(BuiltinName.data()+24, "ubaddhr", 7))
break;
return Intrinsic::hexagon_S4_vxsubaddhr; // "__builtin_HEXAG
ON_S4_vxsubaddhr"
} }
break; break;
} }
break; break;
case '5': // 1 string to match.
if (memcmp(BuiltinName.data()+20, "_asrhub_sat", 11))
break;
return Intrinsic::hexagon_S5_asrhub_sat; // "__builtin_HEXAG
ON_S5_asrhub_sat"
} }
break; break;
case 'S': // 32 strings to match. }
break;
case 32: // 96 strings to match.
if (memcmp(BuiltinName.data()+0, "__builtin_HEXAGON_", 18))
break;
switch (BuiltinName[18]) {
default: break;
case 'A': // 16 strings to match.
switch (BuiltinName[19]) { switch (BuiltinName[19]) {
default: break; default: break;
case '2': // 31 strings to match. case '2': // 14 strings to match.
if (BuiltinName[20] != '.') if (BuiltinName[20] != '_')
break; break;
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case 'a': // 8 strings to match. case 'a': // 6 strings to match.
if (BuiltinName[22] != 's') if (memcmp(BuiltinName.data()+22, "ddh_", 4))
break; break;
switch (BuiltinName[23]) { switch (BuiltinName[26]) {
default: break; default: break;
case 'l': // 4 strings to match. case 'h': // 4 strings to match.
if (BuiltinName[24] != '.') if (memcmp(BuiltinName.data()+27, "16_", 3))
break; break;
switch (BuiltinName[25]) { switch (BuiltinName[30]) {
default: break; default: break;
case 'i': // 2 strings to match. case 'h': // 2 strings to match.
if (BuiltinName.substr(26, 2) != ".v") switch (BuiltinName[31]) {
break;
switch (BuiltinName[28]) {
default: break; default: break;
case 'h': // 1 string to match. case 'h': // 1 string to match.
return Intrinsic::hexagon_S2_asl_i_vh; // "__builtin_HEXAG return Intrinsic::hexagon_A2_addh_h16_hh; // "__built
ON.S2.asl.i.vh" in_HEXAGON_A2_addh_h16_hh"
case 'w': // 1 string to match. case 'l': // 1 string to match.
return Intrinsic::hexagon_S2_asl_i_vw; // "__builtin_HEXAG return Intrinsic::hexagon_A2_addh_h16_hl; // "__built
ON.S2.asl.i.vw" in_HEXAGON_A2_addh_h16_hl"
} }
break; break;
case 'r': // 2 strings to match. case 'l': // 2 strings to match.
if (BuiltinName.substr(26, 2) != ".v") switch (BuiltinName[31]) {
break;
switch (BuiltinName[28]) {
default: break; default: break;
case 'h': // 1 string to match. case 'h': // 1 string to match.
return Intrinsic::hexagon_S2_asl_r_vh; // "__builtin_HEXAG return Intrinsic::hexagon_A2_addh_h16_lh; // "__built
ON.S2.asl.r.vh" in_HEXAGON_A2_addh_h16_lh"
case 'w': // 1 string to match. case 'l': // 1 string to match.
return Intrinsic::hexagon_S2_asl_r_vw; // "__builtin_HEXAG return Intrinsic::hexagon_A2_addh_h16_ll; // "__built
ON.S2.asl.r.vw" in_HEXAGON_A2_addh_h16_ll"
} }
break; break;
} }
break; break;
case 'r': // 4 strings to match. case 'l': // 2 strings to match.
if (BuiltinName[24] != '.') if (memcmp(BuiltinName.data()+27, "16_", 3))
break; break;
switch (BuiltinName[25]) { switch (BuiltinName[30]) {
default: break; default: break;
case 'i': // 2 strings to match. case 'h': // 1 string to match.
if (BuiltinName.substr(26, 2) != ".v") if (BuiltinName[31] != 'l')
break; break;
switch (BuiltinName[28]) { return Intrinsic::hexagon_A2_addh_l16_hl; // "__built
in_HEXAGON_A2_addh_l16_hl"
case 'l': // 1 string to match.
if (BuiltinName[31] != 'l')
break;
return Intrinsic::hexagon_A2_addh_l16_ll; // "__built
in_HEXAGON_A2_addh_l16_ll"
}
break;
}
break;
case 's': // 6 strings to match.
if (memcmp(BuiltinName.data()+22, "ubh_", 4))
break;
switch (BuiltinName[26]) {
default: break;
case 'h': // 4 strings to match.
if (memcmp(BuiltinName.data()+27, "16_", 3))
break;
switch (BuiltinName[30]) {
default: break;
case 'h': // 2 strings to match.
switch (BuiltinName[31]) {
default: break; default: break;
case 'h': // 1 string to match. case 'h': // 1 string to match.
return Intrinsic::hexagon_S2_asr_i_vh; // "__builtin_HEXAG return Intrinsic::hexagon_A2_subh_h16_hh; // "__built
ON.S2.asr.i.vh" in_HEXAGON_A2_subh_h16_hh"
case 'w': // 1 string to match. case 'l': // 1 string to match.
return Intrinsic::hexagon_S2_asr_i_vw; // "__builtin_HEXAG return Intrinsic::hexagon_A2_subh_h16_hl; // "__built
ON.S2.asr.i.vw" in_HEXAGON_A2_subh_h16_hl"
} }
break; break;
case 'r': // 2 strings to match. case 'l': // 2 strings to match.
if (BuiltinName.substr(26, 2) != ".v") switch (BuiltinName[31]) {
break;
switch (BuiltinName[28]) {
default: break; default: break;
case 'h': // 1 string to match. case 'h': // 1 string to match.
return Intrinsic::hexagon_S2_asr_r_vh; // "__builtin_HEXAG return Intrinsic::hexagon_A2_subh_h16_lh; // "__built
ON.S2.asr.r.vh" in_HEXAGON_A2_subh_h16_lh"
case 'w': // 1 string to match. case 'l': // 1 string to match.
return Intrinsic::hexagon_S2_asr_r_vw; // "__builtin_HEXAG return Intrinsic::hexagon_A2_subh_h16_ll; // "__built
ON.S2.asr.r.vw" in_HEXAGON_A2_subh_h16_ll"
} }
break; break;
} }
break; break;
case 'l': // 2 strings to match.
if (memcmp(BuiltinName.data()+27, "16_", 3))
break;
switch (BuiltinName[30]) {
default: break;
case 'h': // 1 string to match.
if (BuiltinName[31] != 'l')
break;
return Intrinsic::hexagon_A2_subh_l16_hl; // "__built
in_HEXAGON_A2_subh_l16_hl"
case 'l': // 1 string to match.
if (BuiltinName[31] != 'l')
break;
return Intrinsic::hexagon_A2_subh_l16_ll; // "__built
in_HEXAGON_A2_subh_l16_ll"
}
break;
} }
break; break;
case 'c': // 2 strings to match. case 'v': // 2 strings to match.
if (BuiltinName.substr(22, 6) != "lrbit.") if (BuiltinName[22] != 'r')
break; break;
switch (BuiltinName[28]) { switch (BuiltinName[23]) {
default: break; default: break;
case 'i': // 1 string to match. case 'a': // 1 string to match.
return Intrinsic::hexagon_S2_clrbit_i; // "__builtin_HEXAG if (memcmp(BuiltinName.data()+24, "ddub_acc", 8))
ON.S2.clrbit.i" break;
case 'r': // 1 string to match. return Intrinsic::hexagon_A2_vraddub_acc; // "__builtin_HEXAG
return Intrinsic::hexagon_S2_clrbit_r; // "__builtin_HEXAG ON_A2_vraddub_acc"
ON.S2.clrbit.r" case 's': // 1 string to match.
if (memcmp(BuiltinName.data()+24, "adub_acc", 8))
break;
return Intrinsic::hexagon_A2_vrsadub_acc; // "__builtin_HEXAG
ON_A2_vrsadub_acc"
} }
break; break;
case 'e': // 1 string to match. }
if (BuiltinName.substr(22, 7) != "xtractu") break;
case '4': // 2 strings to match.
if (BuiltinName[20] != '_')
break;
switch (BuiltinName[21]) {
default: break;
case 'b': // 1 string to match.
if (memcmp(BuiltinName.data()+22, "oundscheck", 10))
break; break;
return Intrinsic::hexagon_S2_extractu; // "__builtin_HEXAG return Intrinsic::hexagon_A4_boundscheck; // "__builtin_HEXAG
ON.S2.extractu" ON_A4_boundscheck"
case 'l': // 6 strings to match. case 'v': // 1 string to match.
if (BuiltinName[22] != 's') if (memcmp(BuiltinName.data()+22, "cmpbeq_any", 10))
break; break;
switch (BuiltinName[23]) { return Intrinsic::hexagon_A4_vcmpbeq_any; // "__builtin_HEXAG
default: break; ON_A4_vcmpbeq_any"
case 'l': // 2 strings to match. }
if (BuiltinName.substr(24, 4) != ".r.v") break;
break; }
switch (BuiltinName[28]) { break;
default: break; case 'C': // 1 string to match.
case 'h': // 1 string to match. if (memcmp(BuiltinName.data()+19, "4_fastcorner9", 13))
return Intrinsic::hexagon_S2_lsl_r_vh; // "__builtin_HEXAG break;
ON.S2.lsl.r.vh" return Intrinsic::hexagon_C4_fastcorner9; // "__builtin_HEXAG
case 'w': // 1 string to match. ON_C4_fastcorner9"
return Intrinsic::hexagon_S2_lsl_r_vw; // "__builtin_HEXAG case 'M': // 16 strings to match.
ON.S2.lsl.r.vw" if (memcmp(BuiltinName.data()+19, "2_", 2))
} break;
switch (BuiltinName[21]) {
default: break;
case 'm': // 12 strings to match.
switch (BuiltinName[22]) {
default: break;
case 'm': // 4 strings to match.
if (memcmp(BuiltinName.data()+23, "acu", 3))
break; break;
case 'r': // 4 strings to match. switch (BuiltinName[26]) {
if (BuiltinName[24] != '.') default: break;
case 'h': // 2 strings to match.
if (memcmp(BuiltinName.data()+27, "s_rs", 4))
break; break;
switch (BuiltinName[25]) { switch (BuiltinName[31]) {
default: break; default: break;
case 'i': // 2 strings to match. case '0': // 1 string to match.
if (BuiltinName.substr(26, 2) != ".v") return Intrinsic::hexagon_M2_mmacuhs_rs0; // "__built
break; in_HEXAGON_M2_mmacuhs_rs0"
switch (BuiltinName[28]) { case '1': // 1 string to match.
default: break; return Intrinsic::hexagon_M2_mmacuhs_rs1; // "__built
case 'h': // 1 string to match. in_HEXAGON_M2_mmacuhs_rs1"
return Intrinsic::hexagon_S2_lsr_i_vh; // "__builtin_HEXAG
ON.S2.lsr.i.vh"
case 'w': // 1 string to match.
return Intrinsic::hexagon_S2_lsr_i_vw; // "__builtin_HEXAG
ON.S2.lsr.i.vw"
}
break;
case 'r': // 2 strings to match.
if (BuiltinName.substr(26, 2) != ".v")
break;
switch (BuiltinName[28]) {
default: break;
case 'h': // 1 string to match.
return Intrinsic::hexagon_S2_lsr_r_vh; // "__builtin_HEXAG
ON.S2.lsr.r.vh"
case 'w': // 1 string to match.
return Intrinsic::hexagon_S2_lsr_r_vw; // "__builtin_HEXAG
ON.S2.lsr.r.vw"
}
break;
} }
break; break;
} case 'l': // 2 strings to match.
break; if (memcmp(BuiltinName.data()+27, "s_rs", 4))
case 's': // 3 strings to match.
switch (BuiltinName[22]) {
default: break;
case 'e': // 2 strings to match.
if (BuiltinName.substr(23, 5) != "tbit.")
break; break;
switch (BuiltinName[28]) { switch (BuiltinName[31]) {
default: break; default: break;
case 'i': // 1 string to match. case '0': // 1 string to match.
return Intrinsic::hexagon_S2_setbit_i; // "__builtin_HEXAG return Intrinsic::hexagon_M2_mmaculs_rs0; // "__built
ON.S2.setbit.i" in_HEXAGON_M2_mmaculs_rs0"
case 'r': // 1 string to match. case '1': // 1 string to match.
return Intrinsic::hexagon_S2_setbit_r; // "__builtin_HEXAG return Intrinsic::hexagon_M2_mmaculs_rs1; // "__built
ON.S2.setbit.r" in_HEXAGON_M2_mmaculs_rs1"
} }
break; break;
case 'v': // 1 string to match.
if (BuiltinName.substr(23, 6) != "sathub")
break;
return Intrinsic::hexagon_S2_svsathub; // "__builtin_HEXAG
ON.S2.svsathub"
} }
break; break;
case 't': // 2 strings to match. case 'p': // 8 strings to match.
if (BuiltinName.substr(22, 6) != "stbit.") if (memcmp(BuiltinName.data()+23, "yud_", 4))
break; break;
switch (BuiltinName[28]) { switch (BuiltinName[27]) {
default: break;
case 'i': // 1 string to match.
return Intrinsic::hexagon_S2_tstbit_i; // "__builtin_HEXAG
ON.S2.tstbit.i"
case 'r': // 1 string to match.
return Intrinsic::hexagon_S2_tstbit_r; // "__builtin_HEXAG
ON.S2.tstbit.r"
}
break;
case 'v': // 9 strings to match.
switch (BuiltinName[22]) {
default: break; default: break;
case 'a': // 2 strings to match. case 'h': // 4 strings to match.
if (BuiltinName.substr(23, 4) != "lign") switch (BuiltinName[28]) {
break;
switch (BuiltinName[27]) {
default: break; default: break;
case 'i': // 1 string to match. case 'h': // 2 strings to match.
if (BuiltinName[28] != 'b') if (memcmp(BuiltinName.data()+29, "_s", 2))
break;
return Intrinsic::hexagon_S2_valignib; // "__builtin_HEXAG
ON.S2.valignib"
case 'r': // 1 string to match.
if (BuiltinName[28] != 'b')
break; break;
return Intrinsic::hexagon_S2_valignrb; // "__builtin_HEXAG switch (BuiltinName[31]) {
ON.S2.valignrb" default: break;
} case '0': // 1 string to match.
break; return Intrinsic::hexagon_M2_mpyud_hh_s0; // "__built
case 'c': // 1 string to match. in_HEXAGON_M2_mpyud_hh_s0"
if (BuiltinName.substr(23, 6) != "rotate") case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyud_hh_s1; // "__built
in_HEXAGON_M2_mpyud_hh_s1"
}
break; break;
return Intrinsic::hexagon_S2_vcrotate; // "__builtin_HEXAG case 'l': // 2 strings to match.
ON.S2.vcrotate" if (memcmp(BuiltinName.data()+29, "_s", 2))
case 's': // 2 strings to match. break;
if (BuiltinName.substr(23, 5) != "platr") switch (BuiltinName[31]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyud_hl_s0; // "__built
in_HEXAGON_M2_mpyud_hl_s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyud_hl_s1; // "__built
in_HEXAGON_M2_mpyud_hl_s1"
}
break; break;
switch (BuiltinName[28]) {
default: break;
case 'b': // 1 string to match.
return Intrinsic::hexagon_S2_vsplatrb; // "__builtin_HEXAG
ON.S2.vsplatrb"
case 'h': // 1 string to match.
return Intrinsic::hexagon_S2_vsplatrh; // "__builtin_HEXAG
ON.S2.vsplatrh"
} }
break; break;
case 't': // 4 strings to match. case 'l': // 4 strings to match.
if (BuiltinName.substr(23, 3) != "run") switch (BuiltinName[28]) {
break;
switch (BuiltinName[26]) {
default: break; default: break;
case 'e': // 2 strings to match. case 'h': // 2 strings to match.
switch (BuiltinName[27]) { if (memcmp(BuiltinName.data()+29, "_s", 2))
break;
switch (BuiltinName[31]) {
default: break; default: break;
case 'h': // 1 string to match. case '0': // 1 string to match.
if (BuiltinName[28] != 'b') return Intrinsic::hexagon_M2_mpyud_lh_s0; // "__built
break; in_HEXAGON_M2_mpyud_lh_s0"
return Intrinsic::hexagon_S2_vtrunehb; // "__builtin_HEXAG case '1': // 1 string to match.
ON.S2.vtrunehb" return Intrinsic::hexagon_M2_mpyud_lh_s1; // "__built
case 'w': // 1 string to match. in_HEXAGON_M2_mpyud_lh_s1"
if (BuiltinName[28] != 'h')
break;
return Intrinsic::hexagon_S2_vtrunewh; // "__builtin_HEXAG
ON.S2.vtrunewh"
} }
break; break;
case 'o': // 2 strings to match. case 'l': // 2 strings to match.
switch (BuiltinName[27]) { if (memcmp(BuiltinName.data()+29, "_s", 2))
break;
switch (BuiltinName[31]) {
default: break; default: break;
case 'h': // 1 string to match. case '0': // 1 string to match.
if (BuiltinName[28] != 'b') return Intrinsic::hexagon_M2_mpyud_ll_s0; // "__built
break; in_HEXAGON_M2_mpyud_ll_s0"
return Intrinsic::hexagon_S2_vtrunohb; // "__builtin_HEXAG case '1': // 1 string to match.
ON.S2.vtrunohb" return Intrinsic::hexagon_M2_mpyud_ll_s1; // "__built
case 'w': // 1 string to match. in_HEXAGON_M2_mpyud_ll_s1"
if (BuiltinName[28] != 'h')
break;
return Intrinsic::hexagon_S2_vtrunowh; // "__builtin_HEXAG
ON.S2.vtrunowh"
} }
break; break;
} }
break; break;
} }
break; break;
} }
break; break;
case '4': // 1 string to match. case 'v': // 4 strings to match.
if (BuiltinName.substr(20, 9) != ".or_andix") if (memcmp(BuiltinName.data()+22, "rcm", 3))
break;
return Intrinsic::hexagon_S4_or_andix; // "__builtin_HEXAGON.S4.or
_andix"
}
break;
}
break;
case 30: // 48 strings to match.
if (BuiltinName.substr(0, 18) != "__builtin_HEXAGON.")
break;
switch (BuiltinName[18]) {
default: break;
case 'A': // 5 strings to match.
switch (BuiltinName[19]) {
default: break;
case '2': // 1 string to match.
if (BuiltinName.substr(20, 10) != ".combineii")
break;
return Intrinsic::hexagon_A2_combineii; // "__builtin_HEXAG
ON.A2.combineii"
case '4': // 4 strings to match.
if (BuiltinName.substr(20, 2) != ".c")
break; break;
switch (BuiltinName[22]) { switch (BuiltinName[25]) {
default: break; default: break;
case 'o': // 2 strings to match. case 'a': // 2 strings to match.
if (BuiltinName.substr(23, 5) != "mbine") if (BuiltinName[26] != 'c')
break; break;
switch (BuiltinName[28]) { switch (BuiltinName[27]) {
default: break; default: break;
case 'i': // 1 string to match. case 'i': // 1 string to match.
if (BuiltinName[29] != 'r') if (memcmp(BuiltinName.data()+28, "_s0c", 4))
break; break;
return Intrinsic::hexagon_A4_combineir; // "__builtin_HEXAG ON.A4.combineir" return Intrinsic::hexagon_M2_vrcmaci_s0c; // "__builtin_HEXAG ON_M2_vrcmaci_s0c"
case 'r': // 1 string to match. case 'r': // 1 string to match.
if (BuiltinName[29] != 'i') if (memcmp(BuiltinName.data()+28, "_s0c", 4))
break; break;
return Intrinsic::hexagon_A4_combineri; // "__builtin_HEXAG ON.A4.combineri" return Intrinsic::hexagon_M2_vrcmacr_s0c; // "__builtin_HEXAG ON_M2_vrcmacr_s0c"
} }
break; break;
case 'r': // 2 strings to match. case 'p': // 2 strings to match.
if (BuiltinName.substr(23, 6) != "ound_r") if (BuiltinName[26] != 'y')
break; break;
switch (BuiltinName[29]) { switch (BuiltinName[27]) {
default: break; default: break;
case 'i': // 1 string to match. case 'i': // 1 string to match.
return Intrinsic::hexagon_A4_cround_ri; // "__builtin_HEXAG if (memcmp(BuiltinName.data()+28, "_s0c", 4))
ON.A4.cround_ri" break;
return Intrinsic::hexagon_M2_vrcmpyi_s0c; // "__builtin_HEXAG
ON_M2_vrcmpyi_s0c"
case 'r': // 1 string to match. case 'r': // 1 string to match.
return Intrinsic::hexagon_A4_cround_rr; // "__builtin_HEXAG if (memcmp(BuiltinName.data()+28, "_s0c", 4))
ON.A4.cround_rr" break;
return Intrinsic::hexagon_M2_vrcmpyr_s0c; // "__builtin_HEXAG
ON_M2_vrcmpyr_s0c"
} }
break; break;
} }
break; break;
} }
break; break;
case 'C': // 1 string to match. case 'S': // 63 strings to match.
if (BuiltinName.substr(19, 11) != "2.pxfer.map") switch (BuiltinName[19]) {
break;
return Intrinsic::hexagon_C2_pxfer_map; // "__builtin_HEXAGON.C2.px
fer.map"
case 'M': // 38 strings to match.
if (BuiltinName.substr(19, 2) != "2.")
break;
switch (BuiltinName[21]) {
default: break; default: break;
case 'c': // 8 strings to match. case '2': // 56 strings to match.
switch (BuiltinName[22]) { if (BuiltinName[20] != '_')
break;
switch (BuiltinName[21]) {
default: break; default: break;
case 'm': // 6 strings to match. case 'a': // 32 strings to match.
switch (BuiltinName[23]) { switch (BuiltinName[22]) {
default: break; default: break;
case 'a': // 2 strings to match. case 'd': // 1 string to match.
if (BuiltinName.substr(24, 5) != "csc.s") if (memcmp(BuiltinName.data()+23, "dasl_rrri", 9))
break; break;
switch (BuiltinName[29]) { return Intrinsic::hexagon_S2_addasl_rrri; // "__builtin_HEXAG
ON_S2_addasl_rrri"
case 's': // 31 strings to match.
switch (BuiltinName[23]) {
default: break; default: break;
case '0': // 1 string to match. case 'l': // 15 strings to match.
return Intrinsic::hexagon_M2_cmacsc_s0; // "__builtin_HEXAG if (BuiltinName[24] != '_')
ON.M2.cmacsc.s0" break;
case '1': // 1 string to match. switch (BuiltinName[25]) {
return Intrinsic::hexagon_M2_cmacsc_s1; // "__builtin_HEXAG default: break;
ON.M2.cmacsc.s1" case 'i': // 7 strings to match.
} if (BuiltinName[26] != '_')
break; break;
case 'p': // 4 strings to match. switch (BuiltinName[27]) {
if (BuiltinName[24] != 'y') default: break;
case 'p': // 3 strings to match.
if (BuiltinName[28] != '_')
break;
switch (BuiltinName[29]) {
default: break;
case 'a': // 2 strings to match.
switch (BuiltinName[30]) {
default: break;
case 'c': // 1 string to match.
if (BuiltinName[31] != 'c')
break;
return Intrinsic::hexagon_S2_asl_i_p_acc; //
"__builtin_HEXAGON_S2_asl_i_p_acc"
case 'n': // 1 string to match.
if (BuiltinName[31] != 'd')
break;
return Intrinsic::hexagon_S2_asl_i_p_and; //
"__builtin_HEXAGON_S2_asl_i_p_and"
}
break;
case 'n': // 1 string to match.
if (memcmp(BuiltinName.data()+30, "ac", 2))
break;
return Intrinsic::hexagon_S2_asl_i_p_nac; // "__built
in_HEXAGON_S2_asl_i_p_nac"
}
break;
case 'r': // 4 strings to match.
if (BuiltinName[28] != '_')
break;
switch (BuiltinName[29]) {
default: break;
case 'a': // 2 strings to match.
switch (BuiltinName[30]) {
default: break;
case 'c': // 1 string to match.
if (BuiltinName[31] != 'c')
break;
return Intrinsic::hexagon_S2_asl_i_r_acc; //
"__builtin_HEXAGON_S2_asl_i_r_acc"
case 'n': // 1 string to match.
if (BuiltinName[31] != 'd')
break;
return Intrinsic::hexagon_S2_asl_i_r_and; //
"__builtin_HEXAGON_S2_asl_i_r_and"
}
break;
case 'n': // 1 string to match.
if (memcmp(BuiltinName.data()+30, "ac", 2))
break;
return Intrinsic::hexagon_S2_asl_i_r_nac; // "__built
in_HEXAGON_S2_asl_i_r_nac"
case 's': // 1 string to match.
if (memcmp(BuiltinName.data()+30, "at", 2))
break;
return Intrinsic::hexagon_S2_asl_i_r_sat; // "__built
in_HEXAGON_S2_asl_i_r_sat"
}
break;
}
break;
case 'r': // 8 strings to match.
if (BuiltinName[26] != '_')
break;
switch (BuiltinName[27]) {
default: break;
case 'p': // 4 strings to match.
if (BuiltinName[28] != '_')
break;
switch (BuiltinName[29]) {
default: break;
case 'a': // 2 strings to match.
switch (BuiltinName[30]) {
default: break;
case 'c': // 1 string to match.
if (BuiltinName[31] != 'c')
break;
return Intrinsic::hexagon_S2_asl_r_p_acc; //
"__builtin_HEXAGON_S2_asl_r_p_acc"
case 'n': // 1 string to match.
if (BuiltinName[31] != 'd')
break;
return Intrinsic::hexagon_S2_asl_r_p_and; //
"__builtin_HEXAGON_S2_asl_r_p_and"
}
break;
case 'n': // 1 string to match.
if (memcmp(BuiltinName.data()+30, "ac", 2))
break;
return Intrinsic::hexagon_S2_asl_r_p_nac; // "__built
in_HEXAGON_S2_asl_r_p_nac"
case 'x': // 1 string to match.
if (memcmp(BuiltinName.data()+30, "or", 2))
break;
return Intrinsic::hexagon_S2_asl_r_p_xor; // "__built
in_HEXAGON_S2_asl_r_p_xor"
}
break;
case 'r': // 4 strings to match.
if (BuiltinName[28] != '_')
break;
switch (BuiltinName[29]) {
default: break;
case 'a': // 2 strings to match.
switch (BuiltinName[30]) {
default: break;
case 'c': // 1 string to match.
if (BuiltinName[31] != 'c')
break;
return Intrinsic::hexagon_S2_asl_r_r_acc; //
"__builtin_HEXAGON_S2_asl_r_r_acc"
case 'n': // 1 string to match.
if (BuiltinName[31] != 'd')
break;
return Intrinsic::hexagon_S2_asl_r_r_and; //
"__builtin_HEXAGON_S2_asl_r_r_and"
}
break;
case 'n': // 1 string to match.
if (memcmp(BuiltinName.data()+30, "ac", 2))
break;
return Intrinsic::hexagon_S2_asl_r_r_nac; // "__built
in_HEXAGON_S2_asl_r_r_nac"
case 's': // 1 string to match.
if (memcmp(BuiltinName.data()+30, "at", 2))
break;
return Intrinsic::hexagon_S2_asl_r_r_sat; // "__built
in_HEXAGON_S2_asl_r_r_sat"
}
break;
}
break;
}
break; break;
switch (BuiltinName[25]) { case 'r': // 16 strings to match.
default: break; if (BuiltinName[24] != '_')
case 'r': // 2 strings to match. break;
if (BuiltinName.substr(26, 3) != "s.s") switch (BuiltinName[25]) {
default: break;
case 'i': // 8 strings to match.
if (BuiltinName[26] != '_')
break;
switch (BuiltinName[27]) {
default: break;
case 'p': // 4 strings to match.
if (BuiltinName[28] != '_')
break;
switch (BuiltinName[29]) {
default: break;
case 'a': // 2 strings to match.
switch (BuiltinName[30]) {
default: break;
case 'c': // 1 string to match.
if (BuiltinName[31] != 'c')
break;
return Intrinsic::hexagon_S2_asr_i_p_acc; //
"__builtin_HEXAGON_S2_asr_i_p_acc"
case 'n': // 1 string to match.
if (BuiltinName[31] != 'd')
break;
return Intrinsic::hexagon_S2_asr_i_p_and; //
"__builtin_HEXAGON_S2_asr_i_p_and"
}
break;
case 'n': // 1 string to match.
if (memcmp(BuiltinName.data()+30, "ac", 2))
break;
return Intrinsic::hexagon_S2_asr_i_p_nac; // "__built
in_HEXAGON_S2_asr_i_p_nac"
case 'r': // 1 string to match.
if (memcmp(BuiltinName.data()+30, "nd", 2))
break;
return Intrinsic::hexagon_S2_asr_i_p_rnd; // "__built
in_HEXAGON_S2_asr_i_p_rnd"
}
break;
case 'r': // 4 strings to match.
if (BuiltinName[28] != '_')
break;
switch (BuiltinName[29]) {
default: break;
case 'a': // 2 strings to match.
switch (BuiltinName[30]) {
default: break;
case 'c': // 1 string to match.
if (BuiltinName[31] != 'c')
break;
return Intrinsic::hexagon_S2_asr_i_r_acc; //
"__builtin_HEXAGON_S2_asr_i_r_acc"
case 'n': // 1 string to match.
if (BuiltinName[31] != 'd')
break;
return Intrinsic::hexagon_S2_asr_i_r_and; //
"__builtin_HEXAGON_S2_asr_i_r_and"
}
break;
case 'n': // 1 string to match.
if (memcmp(BuiltinName.data()+30, "ac", 2))
break;
return Intrinsic::hexagon_S2_asr_i_r_nac; // "__built
in_HEXAGON_S2_asr_i_r_nac"
case 'r': // 1 string to match.
if (memcmp(BuiltinName.data()+30, "nd", 2))
break;
return Intrinsic::hexagon_S2_asr_i_r_rnd; // "__built
in_HEXAGON_S2_asr_i_r_rnd"
}
break;
}
break; break;
switch (BuiltinName[29]) { case 'r': // 8 strings to match.
default: break; if (BuiltinName[26] != '_')
case '0': // 1 string to match. break;
return Intrinsic::hexagon_M2_cmpyrs_s0; // "__built switch (BuiltinName[27]) {
in_HEXAGON.M2.cmpyrs.s0" default: break;
case '1': // 1 string to match. case 'p': // 4 strings to match.
return Intrinsic::hexagon_M2_cmpyrs_s1; // "__built if (BuiltinName[28] != '_')
in_HEXAGON.M2.cmpyrs.s1" break;
} switch (BuiltinName[29]) {
break; default: break;
case 's': // 2 strings to match. case 'a': // 2 strings to match.
if (BuiltinName.substr(26, 3) != "c.s") switch (BuiltinName[30]) {
default: break;
case 'c': // 1 string to match.
if (BuiltinName[31] != 'c')
break;
return Intrinsic::hexagon_S2_asr_r_p_acc; //
"__builtin_HEXAGON_S2_asr_r_p_acc"
case 'n': // 1 string to match.
if (BuiltinName[31] != 'd')
break;
return Intrinsic::hexagon_S2_asr_r_p_and; //
"__builtin_HEXAGON_S2_asr_r_p_and"
}
break;
case 'n': // 1 string to match.
if (memcmp(BuiltinName.data()+30, "ac", 2))
break;
return Intrinsic::hexagon_S2_asr_r_p_nac; // "__built
in_HEXAGON_S2_asr_r_p_nac"
case 'x': // 1 string to match.
if (memcmp(BuiltinName.data()+30, "or", 2))
break;
return Intrinsic::hexagon_S2_asr_r_p_xor; // "__built
in_HEXAGON_S2_asr_r_p_xor"
}
break;
case 'r': // 4 strings to match.
if (BuiltinName[28] != '_')
break;
switch (BuiltinName[29]) {
default: break;
case 'a': // 2 strings to match.
switch (BuiltinName[30]) {
default: break;
case 'c': // 1 string to match.
if (BuiltinName[31] != 'c')
break;
return Intrinsic::hexagon_S2_asr_r_r_acc; //
"__builtin_HEXAGON_S2_asr_r_r_acc"
case 'n': // 1 string to match.
if (BuiltinName[31] != 'd')
break;
return Intrinsic::hexagon_S2_asr_r_r_and; //
"__builtin_HEXAGON_S2_asr_r_r_and"
}
break;
case 'n': // 1 string to match.
if (memcmp(BuiltinName.data()+30, "ac", 2))
break;
return Intrinsic::hexagon_S2_asr_r_r_nac; // "__built
in_HEXAGON_S2_asr_r_r_nac"
case 's': // 1 string to match.
if (memcmp(BuiltinName.data()+30, "at", 2))
break;
return Intrinsic::hexagon_S2_asr_r_r_sat; // "__built
in_HEXAGON_S2_asr_r_r_sat"
}
break;
}
break; break;
switch (BuiltinName[29]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_cmpysc_s0; // "__built
in_HEXAGON.M2.cmpysc.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_cmpysc_s1; // "__built
in_HEXAGON.M2.cmpysc.s1"
} }
break; break;
} }
break; break;
} }
break; break;
case 'n': // 2 strings to match. case 'e': // 1 string to match.
if (BuiltinName.substr(23, 6) != "acsc.s") if (memcmp(BuiltinName.data()+22, "xtractu_rp", 10))
break;
return Intrinsic::hexagon_S2_extractu_rp; // "__builtin_HEXAG
ON_S2_extractu_rp"
case 'l': // 20 strings to match.
if (BuiltinName[22] != 's')
break; break;
switch (BuiltinName[29]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_cnacsc_s0; // "__builtin_HEXAG
ON.M2.cnacsc.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_cnacsc_s1; // "__builtin_HEXAG
ON.M2.cnacsc.s1"
}
break;
}
break;
case 'm': // 20 strings to match.
switch (BuiltinName[22]) {
default: break;
case 'm': // 12 strings to match.
switch (BuiltinName[23]) { switch (BuiltinName[23]) {
default: break; default: break;
case 'a': // 4 strings to match. case 'l': // 7 strings to match.
if (BuiltinName[24] != 'c') if (memcmp(BuiltinName.data()+24, "_r_", 3))
break; break;
switch (BuiltinName[25]) { switch (BuiltinName[27]) {
default: break; default: break;
case 'h': // 2 strings to match. case 'p': // 4 strings to match.
if (BuiltinName.substr(26, 3) != "s.s") if (BuiltinName[28] != '_')
break; break;
switch (BuiltinName[29]) { switch (BuiltinName[29]) {
default: break; default: break;
case '0': // 1 string to match. case 'a': // 2 strings to match.
return Intrinsic::hexagon_M2_mmachs_s0; // "__built switch (BuiltinName[30]) {
in_HEXAGON.M2.mmachs.s0" default: break;
case '1': // 1 string to match. case 'c': // 1 string to match.
return Intrinsic::hexagon_M2_mmachs_s1; // "__built if (BuiltinName[31] != 'c')
in_HEXAGON.M2.mmachs.s1" break;
return Intrinsic::hexagon_S2_lsl_r_p_acc; // "__built
in_HEXAGON_S2_lsl_r_p_acc"
case 'n': // 1 string to match.
if (BuiltinName[31] != 'd')
break;
return Intrinsic::hexagon_S2_lsl_r_p_and; // "__built
in_HEXAGON_S2_lsl_r_p_and"
}
break;
case 'n': // 1 string to match.
if (memcmp(BuiltinName.data()+30, "ac", 2))
break;
return Intrinsic::hexagon_S2_lsl_r_p_nac; // "__built
in_HEXAGON_S2_lsl_r_p_nac"
case 'x': // 1 string to match.
if (memcmp(BuiltinName.data()+30, "or", 2))
break;
return Intrinsic::hexagon_S2_lsl_r_p_xor; // "__built
in_HEXAGON_S2_lsl_r_p_xor"
} }
break; break;
case 'l': // 2 strings to match. case 'r': // 3 strings to match.
if (BuiltinName.substr(26, 3) != "s.s") if (BuiltinName[28] != '_')
break; break;
switch (BuiltinName[29]) { switch (BuiltinName[29]) {
default: break; default: break;
case '0': // 1 string to match. case 'a': // 2 strings to match.
return Intrinsic::hexagon_M2_mmacls_s0; // "__built switch (BuiltinName[30]) {
in_HEXAGON.M2.mmacls.s0" default: break;
case '1': // 1 string to match. case 'c': // 1 string to match.
return Intrinsic::hexagon_M2_mmacls_s1; // "__built if (BuiltinName[31] != 'c')
in_HEXAGON.M2.mmacls.s1" break;
return Intrinsic::hexagon_S2_lsl_r_r_acc; // "__built
in_HEXAGON_S2_lsl_r_r_acc"
case 'n': // 1 string to match.
if (BuiltinName[31] != 'd')
break;
return Intrinsic::hexagon_S2_lsl_r_r_and; // "__built
in_HEXAGON_S2_lsl_r_r_and"
}
break;
case 'n': // 1 string to match.
if (memcmp(BuiltinName.data()+30, "ac", 2))
break;
return Intrinsic::hexagon_S2_lsl_r_r_nac; // "__built
in_HEXAGON_S2_lsl_r_r_nac"
} }
break; break;
} }
break; break;
case 'p': // 8 strings to match. case 'r': // 13 strings to match.
if (BuiltinName[24] != 'y') if (BuiltinName[24] != '_')
break; break;
switch (BuiltinName[25]) { switch (BuiltinName[25]) {
default: break; default: break;
case 'h': // 2 strings to match. case 'i': // 6 strings to match.
if (BuiltinName.substr(26, 3) != ".rs") if (BuiltinName[26] != '_')
break;
switch (BuiltinName[29]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mmpyh_rs0; // "__built
in_HEXAGON.M2.mmpyh.rs0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mmpyh_rs1; // "__built
in_HEXAGON.M2.mmpyh.rs1"
}
break;
case 'l': // 2 strings to match.
if (BuiltinName.substr(26, 3) != ".rs")
break; break;
switch (BuiltinName[29]) { switch (BuiltinName[27]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mmpyl_rs0; // "__built
in_HEXAGON.M2.mmpyl.rs0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mmpyl_rs1; // "__built
in_HEXAGON.M2.mmpyl.rs1"
}
break;
case 'u': // 4 strings to match.
switch (BuiltinName[26]) {
default: break; default: break;
case 'h': // 2 strings to match. case 'p': // 3 strings to match.
if (BuiltinName.substr(27, 2) != ".s") if (BuiltinName[28] != '_')
break; break;
switch (BuiltinName[29]) { switch (BuiltinName[29]) {
default: break; default: break;
case '0': // 1 string to match. case 'a': // 2 strings to match.
return Intrinsic::hexagon_M2_mmpyuh_s0; // "__built switch (BuiltinName[30]) {
in_HEXAGON.M2.mmpyuh.s0" default: break;
case '1': // 1 string to match. case 'c': // 1 string to match.
return Intrinsic::hexagon_M2_mmpyuh_s1; // "__built if (BuiltinName[31] != 'c')
in_HEXAGON.M2.mmpyuh.s1" break;
return Intrinsic::hexagon_S2_lsr_i_p_acc; // "__built
in_HEXAGON_S2_lsr_i_p_acc"
case 'n': // 1 string to match.
if (BuiltinName[31] != 'd')
break;
return Intrinsic::hexagon_S2_lsr_i_p_and; // "__built
in_HEXAGON_S2_lsr_i_p_and"
}
break;
case 'n': // 1 string to match.
if (memcmp(BuiltinName.data()+30, "ac", 2))
break;
return Intrinsic::hexagon_S2_lsr_i_p_nac; // "__built
in_HEXAGON_S2_lsr_i_p_nac"
} }
break; break;
case 'l': // 2 strings to match. case 'r': // 3 strings to match.
if (BuiltinName.substr(27, 2) != ".s") if (BuiltinName[28] != '_')
break; break;
switch (BuiltinName[29]) { switch (BuiltinName[29]) {
default: break; default: break;
case '0': // 1 string to match. case 'a': // 2 strings to match.
return Intrinsic::hexagon_M2_mmpyul_s0; // "__built switch (BuiltinName[30]) {
in_HEXAGON.M2.mmpyul.s0" default: break;
case '1': // 1 string to match. case 'c': // 1 string to match.
return Intrinsic::hexagon_M2_mmpyul_s1; // "__built if (BuiltinName[31] != 'c')
in_HEXAGON.M2.mmpyul.s1" break;
return Intrinsic::hexagon_S2_lsr_i_r_acc; // "__built
in_HEXAGON_S2_lsr_i_r_acc"
case 'n': // 1 string to match.
if (BuiltinName[31] != 'd')
break;
return Intrinsic::hexagon_S2_lsr_i_r_and; // "__built
in_HEXAGON_S2_lsr_i_r_and"
}
break;
case 'n': // 1 string to match.
if (memcmp(BuiltinName.data()+30, "ac", 2))
break;
return Intrinsic::hexagon_S2_lsr_i_r_nac; // "__built
in_HEXAGON_S2_lsr_i_r_nac"
} }
break; break;
} }
break; break;
} case 'r': // 7 strings to match.
break; if (BuiltinName[26] != '_')
}
break;
case 'p': // 8 strings to match.
if (BuiltinName.substr(23, 2) != "y.")
break;
switch (BuiltinName[25]) {
default: break;
case 'h': // 4 strings to match.
switch (BuiltinName[26]) {
default: break;
case 'h': // 2 strings to match.
if (BuiltinName.substr(27, 2) != ".s")
break;
switch (BuiltinName[29]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_hh_s0; // "__built
in_HEXAGON.M2.mpy.hh.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_hh_s1; // "__built
in_HEXAGON.M2.mpy.hh.s1"
}
break;
case 'l': // 2 strings to match.
if (BuiltinName.substr(27, 2) != ".s")
break; break;
switch (BuiltinName[29]) { switch (BuiltinName[27]) {
default: break; default: break;
case '0': // 1 string to match. case 'p': // 4 strings to match.
return Intrinsic::hexagon_M2_mpy_hl_s0; // "__built if (BuiltinName[28] != '_')
in_HEXAGON.M2.mpy.hl.s0" break;
case '1': // 1 string to match. switch (BuiltinName[29]) {
return Intrinsic::hexagon_M2_mpy_hl_s1; // "__built default: break;
in_HEXAGON.M2.mpy.hl.s1" case 'a': // 2 strings to match.
} switch (BuiltinName[30]) {
break; default: break;
} case 'c': // 1 string to match.
break; if (BuiltinName[31] != 'c')
case 'l': // 4 strings to match. break;
switch (BuiltinName[26]) { return Intrinsic::hexagon_S2_lsr_r_p_acc; // "__built
default: break; in_HEXAGON_S2_lsr_r_p_acc"
case 'h': // 2 strings to match. case 'n': // 1 string to match.
if (BuiltinName.substr(27, 2) != ".s") if (BuiltinName[31] != 'd')
break;
return Intrinsic::hexagon_S2_lsr_r_p_and; // "__built
in_HEXAGON_S2_lsr_r_p_and"
}
break;
case 'n': // 1 string to match.
if (memcmp(BuiltinName.data()+30, "ac", 2))
break;
return Intrinsic::hexagon_S2_lsr_r_p_nac; // "__built
in_HEXAGON_S2_lsr_r_p_nac"
case 'x': // 1 string to match.
if (memcmp(BuiltinName.data()+30, "or", 2))
break;
return Intrinsic::hexagon_S2_lsr_r_p_xor; // "__built
in_HEXAGON_S2_lsr_r_p_xor"
}
break; break;
switch (BuiltinName[29]) { case 'r': // 3 strings to match.
default: break; if (BuiltinName[28] != '_')
case '0': // 1 string to match. break;
return Intrinsic::hexagon_M2_mpy_lh_s0; // "__built switch (BuiltinName[29]) {
in_HEXAGON.M2.mpy.lh.s0" default: break;
case '1': // 1 string to match. case 'a': // 2 strings to match.
return Intrinsic::hexagon_M2_mpy_lh_s1; // "__built switch (BuiltinName[30]) {
in_HEXAGON.M2.mpy.lh.s1" default: break;
} case 'c': // 1 string to match.
break; if (BuiltinName[31] != 'c')
case 'l': // 2 strings to match. break;
if (BuiltinName.substr(27, 2) != ".s") return Intrinsic::hexagon_S2_lsr_r_r_acc; // "__built
in_HEXAGON_S2_lsr_r_r_acc"
case 'n': // 1 string to match.
if (BuiltinName[31] != 'd')
break;
return Intrinsic::hexagon_S2_lsr_r_r_and; // "__built
in_HEXAGON_S2_lsr_r_r_and"
}
break;
case 'n': // 1 string to match.
if (memcmp(BuiltinName.data()+30, "ac", 2))
break;
return Intrinsic::hexagon_S2_lsr_r_r_nac; // "__built
in_HEXAGON_S2_lsr_r_r_nac"
}
break; break;
switch (BuiltinName[29]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_ll_s0; // "__built
in_HEXAGON.M2.mpy.ll.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_ll_s1; // "__built
in_HEXAGON.M2.mpy.ll.s1"
} }
break; break;
} }
break; break;
} }
break; break;
} case 't': // 2 strings to match.
break; if (memcmp(BuiltinName.data()+22, "ogglebit_", 9))
case 'v': // 10 strings to match.
switch (BuiltinName[22]) {
default: break;
case 'a': // 2 strings to match.
if (BuiltinName.substr(23, 6) != "bsdiff")
break; break;
switch (BuiltinName[29]) { switch (BuiltinName[31]) {
default: break; default: break;
case 'h': // 1 string to match. case 'i': // 1 string to match.
return Intrinsic::hexagon_M2_vabsdiffh; // "__builtin_HEXAG return Intrinsic::hexagon_S2_togglebit_i; // "__builtin_HEXAG
ON.M2.vabsdiffh" ON_S2_togglebit_i"
case 'w': // 1 string to match. case 'r': // 1 string to match.
return Intrinsic::hexagon_M2_vabsdiffw; // "__builtin_HEXAG return Intrinsic::hexagon_S2_togglebit_r; // "__builtin_HEXAG
ON.M2.vabsdiffw" ON_S2_togglebit_r"
} }
break; break;
case 'd': // 4 strings to match. case 'v': // 1 string to match.
if (BuiltinName[23] != 'm') if (memcmp(BuiltinName.data()+22, "rndpackwhs", 10))
break; break;
switch (BuiltinName[24]) { return Intrinsic::hexagon_S2_vrndpackwhs; // "__builtin_HEXAG
ON_S2_vrndpackwhs"
}
break;
case '4': // 7 strings to match.
if (BuiltinName[20] != '_')
break;
switch (BuiltinName[21]) {
default: break;
case 'a': // 4 strings to match.
switch (BuiltinName[22]) {
default: break; default: break;
case 'a': // 2 strings to match. case 'd': // 2 strings to match.
if (BuiltinName.substr(25, 4) != "cs.s") if (memcmp(BuiltinName.data()+23, "di_", 3))
break; break;
switch (BuiltinName[29]) { switch (BuiltinName[26]) {
default: break; default: break;
case '0': // 1 string to match. case 'a': // 1 string to match.
return Intrinsic::hexagon_M2_vdmacs_s0; // "__builtin_HEXAG if (memcmp(BuiltinName.data()+27, "sl_ri", 5))
ON.M2.vdmacs.s0" break;
case '1': // 1 string to match. return Intrinsic::hexagon_S4_addi_asl_ri; // "__built
return Intrinsic::hexagon_M2_vdmacs_s1; // "__builtin_HEXAG in_HEXAGON_S4_addi_asl_ri"
ON.M2.vdmacs.s1" case 'l': // 1 string to match.
if (memcmp(BuiltinName.data()+27, "sr_ri", 5))
break;
return Intrinsic::hexagon_S4_addi_lsr_ri; // "__built
in_HEXAGON_S4_addi_lsr_ri"
} }
break; break;
case 'p': // 2 strings to match. case 'n': // 2 strings to match.
if (BuiltinName.substr(25, 4) != "ys.s") if (memcmp(BuiltinName.data()+23, "di_", 3))
break; break;
switch (BuiltinName[29]) { switch (BuiltinName[26]) {
default: break; default: break;
case '0': // 1 string to match. case 'a': // 1 string to match.
return Intrinsic::hexagon_M2_vdmpys_s0; // "__builtin_HEXAG if (memcmp(BuiltinName.data()+27, "sl_ri", 5))
ON.M2.vdmpys.s0" break;
case '1': // 1 string to match. return Intrinsic::hexagon_S4_andi_asl_ri; // "__built
return Intrinsic::hexagon_M2_vdmpys_s1; // "__builtin_HEXAG in_HEXAGON_S4_andi_asl_ri"
ON.M2.vdmpys.s1" case 'l': // 1 string to match.
if (memcmp(BuiltinName.data()+27, "sr_ri", 5))
break;
return Intrinsic::hexagon_S4_andi_lsr_ri; // "__built
in_HEXAGON_S4_andi_lsr_ri"
} }
break; break;
} }
break; break;
case 'm': // 4 strings to match. case 'e': // 1 string to match.
switch (BuiltinName[23]) { if (memcmp(BuiltinName.data()+22, "xtractp_rp", 10))
break;
return Intrinsic::hexagon_S4_extractp_rp; // "__builtin_HEXAG
ON_S4_extractp_rp"
case 's': // 2 strings to match.
if (memcmp(BuiltinName.data()+22, "ubi_", 4))
break;
switch (BuiltinName[26]) {
default: break; default: break;
case 'a': // 2 strings to match. case 'a': // 1 string to match.
if (BuiltinName.substr(24, 5) != "c2s.s") if (memcmp(BuiltinName.data()+27, "sl_ri", 5))
break; break;
switch (BuiltinName[29]) { return Intrinsic::hexagon_S4_subi_asl_ri; // "__builtin_HEXAG
default: break; ON_S4_subi_asl_ri"
case '0': // 1 string to match. case 'l': // 1 string to match.
return Intrinsic::hexagon_M2_vmac2s_s0; // "__builtin_HEXAG if (memcmp(BuiltinName.data()+27, "sr_ri", 5))
ON.M2.vmac2s.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_vmac2s_s1; // "__builtin_HEXAG
ON.M2.vmac2s.s1"
}
break;
case 'p': // 2 strings to match.
if (BuiltinName.substr(24, 5) != "y2s.s")
break; break;
switch (BuiltinName[29]) { return Intrinsic::hexagon_S4_subi_lsr_ri; // "__builtin_HEXAG
default: break; ON_S4_subi_lsr_ri"
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_vmpy2s_s0; // "__builtin_HEXAG
ON.M2.vmpy2s.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_vmpy2s_s1; // "__builtin_HEXAG
ON.M2.vmpy2s.s1"
}
break;
} }
break; break;
} }
break; break;
} }
break; break;
case 'S': // 4 strings to match.
if (BuiltinName.substr(19, 2) != "2.")
break;
switch (BuiltinName[21]) {
default: break;
case 'e': // 1 string to match.
if (BuiltinName.substr(22, 8) != "xtractup")
break;
return Intrinsic::hexagon_S2_extractup; // "__builtin_HEXAG
ON.S2.extractup"
case 'i': // 1 string to match.
if (BuiltinName.substr(22, 8) != "nsert.rp")
break;
return Intrinsic::hexagon_S2_insert_rp; // "__builtin_HEXAG
ON.S2.insert.rp"
case 'v': // 2 strings to match.
if (BuiltinName.substr(22, 6) != "splice")
break;
switch (BuiltinName[28]) {
default: break;
case 'i': // 1 string to match.
if (BuiltinName[29] != 'b')
break;
return Intrinsic::hexagon_S2_vspliceib; // "__builtin_HEXAG
ON.S2.vspliceib"
case 'r': // 1 string to match.
if (BuiltinName[29] != 'b')
break;
return Intrinsic::hexagon_S2_vsplicerb; // "__builtin_HEXAG
ON.S2.vsplicerb"
}
break;
}
break;
} }
break; break;
case 31: // 66 strings to match. case 33: // 9 strings to match.
if (BuiltinName.substr(0, 18) != "__builtin_HEXAGON.") if (memcmp(BuiltinName.data()+0, "__builtin_HEXAGON_", 18))
break; break;
switch (BuiltinName[18]) { switch (BuiltinName[18]) {
default: break; default: break;
case 'A': // 4 strings to match. case 'A': // 2 strings to match.
if (BuiltinName.substr(19, 10) != "2.combine.") if (memcmp(BuiltinName.data()+19, "4_round_r", 9))
break; break;
switch (BuiltinName[29]) { switch (BuiltinName[28]) {
default: break; default: break;
case 'h': // 2 strings to match. case 'i': // 1 string to match.
switch (BuiltinName[30]) { if (memcmp(BuiltinName.data()+29, "_sat", 4))
default: break; break;
case 'h': // 1 string to match. return Intrinsic::hexagon_A4_round_ri_sat; // "__builtin_HEXAG
return Intrinsic::hexagon_A2_combine_hh; // "__builtin_HEXAG ON_A4_round_ri_sat"
ON.A2.combine.hh" case 'r': // 1 string to match.
case 'l': // 1 string to match. if (memcmp(BuiltinName.data()+29, "_sat", 4))
return Intrinsic::hexagon_A2_combine_hl; // "__builtin_HEXAG break;
ON.A2.combine.hl" return Intrinsic::hexagon_A4_round_rr_sat; // "__builtin_HEXAG
} ON_A4_round_rr_sat"
break;
case 'l': // 2 strings to match.
switch (BuiltinName[30]) {
default: break;
case 'h': // 1 string to match.
return Intrinsic::hexagon_A2_combine_lh; // "__builtin_HEXAG
ON.A2.combine.lh"
case 'l': // 1 string to match.
return Intrinsic::hexagon_A2_combine_ll; // "__builtin_HEXAG
ON.A2.combine.ll"
}
break;
} }
break; break;
case 'M': // 45 strings to match. case 'M': // 1 string to match.
if (BuiltinName.substr(19, 2) != "2.") if (memcmp(BuiltinName.data()+19, "2_vrcmpys_s1rp", 14))
break;
return Intrinsic::hexagon_M2_vrcmpys_s1rp; // "__builtin_HEXAG
ON_M2_vrcmpys_s1rp"
case 'S': // 6 strings to match.
if (memcmp(BuiltinName.data()+19, "2_", 2))
break; break;
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case 'c': // 2 strings to match. case 'a': // 2 strings to match.
if (BuiltinName.substr(22, 8) != "mpyrsc.s") if (memcmp(BuiltinName.data()+22, "sl_i_", 5))
break;
switch (BuiltinName[30]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_cmpyrsc_s0; // "__builtin_HEXAG
ON.M2.cmpyrsc.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_cmpyrsc_s1; // "__builtin_HEXAG
ON.M2.cmpyrsc.s1"
}
break;
case 'd': // 2 strings to match.
if (BuiltinName.substr(22, 4) != "pmpy")
break; break;
switch (BuiltinName[26]) { switch (BuiltinName[27]) {
default: break; default: break;
case 's': // 1 string to match. case 'p': // 1 string to match.
if (BuiltinName.substr(27, 4) != "s.s0") if (memcmp(BuiltinName.data()+28, "_xacc", 5))
break; break;
return Intrinsic::hexagon_M2_dpmpyss_s0; // "__builtin_HEXAG return Intrinsic::hexagon_S2_asl_i_p_xacc; // "__builtin_HEXAG
ON.M2.dpmpyss.s0" ON_S2_asl_i_p_xacc"
case 'u': // 1 string to match. case 'r': // 1 string to match.
if (BuiltinName.substr(27, 4) != "u.s0") if (memcmp(BuiltinName.data()+28, "_xacc", 5))
break; break;
return Intrinsic::hexagon_M2_dpmpyuu_s0; // "__builtin_HEXAG ON.M2.dpmpyuu.s0" return Intrinsic::hexagon_S2_asl_i_r_xacc; // "__builtin_HEXAG ON_S2_asl_i_r_xacc"
} }
break; break;
case 'h': // 2 strings to match. case 'd': // 1 string to match.
if (BuiltinName.substr(22, 4) != "mmpy") if (memcmp(BuiltinName.data()+22, "einterleave", 11))
break; break;
switch (BuiltinName[26]) { return Intrinsic::hexagon_S2_deinterleave; // "__builtin_HEXAG
ON_S2_deinterleave"
case 'e': // 1 string to match.
if (memcmp(BuiltinName.data()+22, "xtractup_rp", 11))
break;
return Intrinsic::hexagon_S2_extractup_rp; // "__builtin_HEXAG
ON_S2_extractup_rp"
case 'l': // 2 strings to match.
if (memcmp(BuiltinName.data()+22, "sr_i_", 5))
break;
switch (BuiltinName[27]) {
default: break; default: break;
case 'h': // 1 string to match. case 'p': // 1 string to match.
if (BuiltinName.substr(27, 4) != ".rs1") if (memcmp(BuiltinName.data()+28, "_xacc", 5))
break; break;
return Intrinsic::hexagon_M2_hmmpyh_rs1; // "__builtin_HEXAG return Intrinsic::hexagon_S2_lsr_i_p_xacc; // "__builtin_HEXAG
ON.M2.hmmpyh.rs1" ON_S2_lsr_i_p_xacc"
case 'l': // 1 string to match. case 'r': // 1 string to match.
if (BuiltinName.substr(27, 4) != ".rs1") if (memcmp(BuiltinName.data()+28, "_xacc", 5))
break; break;
return Intrinsic::hexagon_M2_hmmpyl_rs1; // "__builtin_HEXAG ON.M2.hmmpyl.rs1" return Intrinsic::hexagon_S2_lsr_i_r_xacc; // "__builtin_HEXAG ON_S2_lsr_i_r_xacc"
} }
break; break;
case 'm': // 28 strings to match. }
switch (BuiltinName[22]) { break;
}
break;
case 34: // 41 strings to match.
if (memcmp(BuiltinName.data()+0, "__builtin_HEXAGON_", 18))
break;
switch (BuiltinName[18]) {
default: break;
case 'M': // 38 strings to match.
switch (BuiltinName[19]) {
default: break;
case '2': // 35 strings to match.
if (BuiltinName[20] != '_')
break;
switch (BuiltinName[21]) {
default: break; default: break;
case 'm': // 12 strings to match. case 'm': // 33 strings to match.
switch (BuiltinName[23]) { if (memcmp(BuiltinName.data()+22, "py_", 3))
break;
switch (BuiltinName[25]) {
default: break; default: break;
case 'a': // 8 strings to match. case 'a': // 8 strings to match.
if (BuiltinName[24] != 'c') if (memcmp(BuiltinName.data()+26, "cc_", 3))
break; break;
switch (BuiltinName[25]) { switch (BuiltinName[29]) {
default: break; default: break;
case 'h': // 2 strings to match. case 'h': // 4 strings to match.
if (BuiltinName.substr(26, 4) != "s.rs")
break;
switch (BuiltinName[30]) { switch (BuiltinName[30]) {
default: break; default: break;
case '0': // 1 string to match. case 'h': // 2 strings to match.
return Intrinsic::hexagon_M2_mmachs_rs0; // "__built if (memcmp(BuiltinName.data()+31, "_s", 2))
in_HEXAGON.M2.mmachs.rs0" break;
case '1': // 1 string to match. switch (BuiltinName[33]) {
return Intrinsic::hexagon_M2_mmachs_rs1; // "__built default: break;
in_HEXAGON.M2.mmachs.rs1" case '0': // 1 string to match.
} return Intrinsic::hexagon_M2_mpy_acc_hh_s0; // "__built
break; in_HEXAGON_M2_mpy_acc_hh_s0"
case 'l': // 2 strings to match. case '1': // 1 string to match.
if (BuiltinName.substr(26, 4) != "s.rs") return Intrinsic::hexagon_M2_mpy_acc_hh_s1; // "__built
in_HEXAGON_M2_mpy_acc_hh_s1"
}
break;
case 'l': // 2 strings to match.
if (memcmp(BuiltinName.data()+31, "_s", 2))
break;
switch (BuiltinName[33]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_acc_hl_s0; // "__built
in_HEXAGON_M2_mpy_acc_hl_s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_acc_hl_s1; // "__built
in_HEXAGON_M2_mpy_acc_hl_s1"
}
break; break;
switch (BuiltinName[30]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mmacls_rs0; // "__built
in_HEXAGON.M2.mmacls.rs0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mmacls_rs1; // "__built
in_HEXAGON.M2.mmacls.rs1"
} }
break; break;
case 'u': // 4 strings to match. case 'l': // 4 strings to match.
switch (BuiltinName[26]) { switch (BuiltinName[30]) {
default: break; default: break;
case 'h': // 2 strings to match. case 'h': // 2 strings to match.
if (BuiltinName.substr(27, 3) != "s.s") if (memcmp(BuiltinName.data()+31, "_s", 2))
break; break;
switch (BuiltinName[30]) { switch (BuiltinName[33]) {
default: break; default: break;
case '0': // 1 string to match. case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mmacuhs_s0; // "__built in_HEXAGON.M2.mmacuhs.s0" return Intrinsic::hexagon_M2_mpy_acc_lh_s0; // "__built in_HEXAGON_M2_mpy_acc_lh_s0"
case '1': // 1 string to match. case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mmacuhs_s1; // "__built in_HEXAGON.M2.mmacuhs.s1" return Intrinsic::hexagon_M2_mpy_acc_lh_s1; // "__built in_HEXAGON_M2_mpy_acc_lh_s1"
} }
break; break;
case 'l': // 2 strings to match. case 'l': // 2 strings to match.
if (BuiltinName.substr(27, 3) != "s.s") if (memcmp(BuiltinName.data()+31, "_s", 2))
break; break;
switch (BuiltinName[30]) { switch (BuiltinName[33]) {
default: break; default: break;
case '0': // 1 string to match. case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mmaculs_s0; // "__built in_HEXAGON.M2.mmaculs.s0" return Intrinsic::hexagon_M2_mpy_acc_ll_s0; // "__built in_HEXAGON_M2_mpy_acc_ll_s0"
case '1': // 1 string to match. case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mmaculs_s1; // "__built in_HEXAGON.M2.mmaculs.s1" return Intrinsic::hexagon_M2_mpy_acc_ll_s1; // "__built in_HEXAGON_M2_mpy_acc_ll_s1"
} }
break; break;
} }
break; break;
} }
break; break;
case 'p': // 4 strings to match. case 'n': // 8 strings to match.
if (BuiltinName.substr(24, 2) != "yu") if (memcmp(BuiltinName.data()+26, "ac_", 3))
break; break;
switch (BuiltinName[26]) { switch (BuiltinName[29]) {
default: break; default: break;
case 'h': // 2 strings to match. case 'h': // 4 strings to match.
if (BuiltinName.substr(27, 3) != ".rs")
break;
switch (BuiltinName[30]) { switch (BuiltinName[30]) {
default: break; default: break;
case '0': // 1 string to match. case 'h': // 2 strings to match.
return Intrinsic::hexagon_M2_mmpyuh_rs0; // "__built if (memcmp(BuiltinName.data()+31, "_s", 2))
in_HEXAGON.M2.mmpyuh.rs0" break;
case '1': // 1 string to match. switch (BuiltinName[33]) {
return Intrinsic::hexagon_M2_mmpyuh_rs1; // "__built default: break;
in_HEXAGON.M2.mmpyuh.rs1" case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_nac_hh_s0; // "__built
in_HEXAGON_M2_mpy_nac_hh_s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_nac_hh_s1; // "__built
in_HEXAGON_M2_mpy_nac_hh_s1"
}
break;
case 'l': // 2 strings to match.
if (memcmp(BuiltinName.data()+31, "_s", 2))
break;
switch (BuiltinName[33]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_nac_hl_s0; // "__built
in_HEXAGON_M2_mpy_nac_hl_s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_nac_hl_s1; // "__built
in_HEXAGON_M2_mpy_nac_hl_s1"
}
break;
} }
break; break;
case 'l': // 2 strings to match. case 'l': // 4 strings to match.
if (BuiltinName.substr(27, 3) != ".rs")
break;
switch (BuiltinName[30]) { switch (BuiltinName[30]) {
default: break; default: break;
case '0': // 1 string to match. case 'h': // 2 strings to match.
return Intrinsic::hexagon_M2_mmpyul_rs0; // "__built if (memcmp(BuiltinName.data()+31, "_s", 2))
in_HEXAGON.M2.mmpyul.rs0" break;
case '1': // 1 string to match. switch (BuiltinName[33]) {
return Intrinsic::hexagon_M2_mmpyul_rs1; // "__built default: break;
in_HEXAGON.M2.mmpyul.rs1" case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_nac_lh_s0; // "__built
in_HEXAGON_M2_mpy_nac_lh_s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_nac_lh_s1; // "__built
in_HEXAGON_M2_mpy_nac_lh_s1"
}
break;
case 'l': // 2 strings to match.
if (memcmp(BuiltinName.data()+31, "_s", 2))
break;
switch (BuiltinName[33]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_nac_ll_s0; // "__built
in_HEXAGON_M2_mpy_nac_ll_s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_nac_ll_s1; // "__built
in_HEXAGON_M2_mpy_nac_ll_s1"
}
break;
} }
break; break;
} }
break; break;
} case 'r': // 8 strings to match.
break; if (memcmp(BuiltinName.data()+26, "nd_", 3))
case 'p': // 16 strings to match.
if (BuiltinName[23] != 'y')
break;
switch (BuiltinName[24]) {
default: break;
case 'd': // 8 strings to match.
if (BuiltinName[25] != '.')
break; break;
switch (BuiltinName[26]) { switch (BuiltinName[29]) {
default: break; default: break;
case 'h': // 4 strings to match. case 'h': // 4 strings to match.
switch (BuiltinName[27]) { switch (BuiltinName[30]) {
default: break; default: break;
case 'h': // 2 strings to match. case 'h': // 2 strings to match.
if (BuiltinName.substr(28, 2) != ".s") if (memcmp(BuiltinName.data()+31, "_s", 2))
break; break;
switch (BuiltinName[30]) { switch (BuiltinName[33]) {
default: break; default: break;
case '0': // 1 string to match. case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_hh_s0; // "__built in_HEXAGON.M2.mpyd.hh.s0" return Intrinsic::hexagon_M2_mpy_rnd_hh_s0; // "__built in_HEXAGON_M2_mpy_rnd_hh_s0"
case '1': // 1 string to match. case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_hh_s1; // "__built in_HEXAGON.M2.mpyd.hh.s1" return Intrinsic::hexagon_M2_mpy_rnd_hh_s1; // "__built in_HEXAGON_M2_mpy_rnd_hh_s1"
} }
break; break;
case 'l': // 2 strings to match. case 'l': // 2 strings to match.
if (BuiltinName.substr(28, 2) != ".s") if (memcmp(BuiltinName.data()+31, "_s", 2))
break; break;
switch (BuiltinName[30]) { switch (BuiltinName[33]) {
default: break; default: break;
case '0': // 1 string to match. case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_hl_s0; // "__built in_HEXAGON.M2.mpyd.hl.s0" return Intrinsic::hexagon_M2_mpy_rnd_hl_s0; // "__built in_HEXAGON_M2_mpy_rnd_hl_s0"
case '1': // 1 string to match. case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_hl_s1; // "__built in_HEXAGON.M2.mpyd.hl.s1" return Intrinsic::hexagon_M2_mpy_rnd_hl_s1; // "__built in_HEXAGON_M2_mpy_rnd_hl_s1"
} }
break; break;
} }
break; break;
case 'l': // 4 strings to match. case 'l': // 4 strings to match.
switch (BuiltinName[27]) { switch (BuiltinName[30]) {
default: break; default: break;
case 'h': // 2 strings to match. case 'h': // 2 strings to match.
if (BuiltinName.substr(28, 2) != ".s") if (memcmp(BuiltinName.data()+31, "_s", 2))
break; break;
switch (BuiltinName[30]) { switch (BuiltinName[33]) {
default: break; default: break;
case '0': // 1 string to match. case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_lh_s0; // "__built in_HEXAGON.M2.mpyd.lh.s0" return Intrinsic::hexagon_M2_mpy_rnd_lh_s0; // "__built in_HEXAGON_M2_mpy_rnd_lh_s0"
case '1': // 1 string to match. case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_lh_s1; // "__built in_HEXAGON.M2.mpyd.lh.s1" return Intrinsic::hexagon_M2_mpy_rnd_lh_s1; // "__built in_HEXAGON_M2_mpy_rnd_lh_s1"
} }
break; break;
case 'l': // 2 strings to match. case 'l': // 2 strings to match.
if (BuiltinName.substr(28, 2) != ".s") if (memcmp(BuiltinName.data()+31, "_s", 2))
break; break;
switch (BuiltinName[30]) { switch (BuiltinName[33]) {
default: break; default: break;
case '0': // 1 string to match. case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_ll_s0; // "__built in_HEXAGON.M2.mpyd.ll.s0" return Intrinsic::hexagon_M2_mpy_rnd_ll_s0; // "__built in_HEXAGON_M2_mpy_rnd_ll_s0"
case '1': // 1 string to match. case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_ll_s1; // "__built in_HEXAGON.M2.mpyd.ll.s1" return Intrinsic::hexagon_M2_mpy_rnd_ll_s1; // "__built in_HEXAGON_M2_mpy_rnd_ll_s1"
} }
break; break;
} }
break; break;
} }
break; break;
case 'u': // 8 strings to match. case 's': // 8 strings to match.
if (BuiltinName[25] != '.') if (memcmp(BuiltinName.data()+26, "at_", 3))
break; break;
switch (BuiltinName[26]) { switch (BuiltinName[29]) {
default: break; default: break;
case 'h': // 4 strings to match. case 'h': // 4 strings to match.
switch (BuiltinName[27]) { switch (BuiltinName[30]) {
default: break; default: break;
case 'h': // 2 strings to match. case 'h': // 2 strings to match.
if (BuiltinName.substr(28, 2) != ".s") if (memcmp(BuiltinName.data()+31, "_s", 2))
break; break;
switch (BuiltinName[30]) { switch (BuiltinName[33]) {
default: break; default: break;
case '0': // 1 string to match. case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyu_hh_s0; // "__built in_HEXAGON.M2.mpyu.hh.s0" return Intrinsic::hexagon_M2_mpy_sat_hh_s0; // "__built in_HEXAGON_M2_mpy_sat_hh_s0"
case '1': // 1 string to match. case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyu_hh_s1; // "__built in_HEXAGON.M2.mpyu.hh.s1" return Intrinsic::hexagon_M2_mpy_sat_hh_s1; // "__built in_HEXAGON_M2_mpy_sat_hh_s1"
} }
break; break;
case 'l': // 2 strings to match. case 'l': // 2 strings to match.
if (BuiltinName.substr(28, 2) != ".s") if (memcmp(BuiltinName.data()+31, "_s", 2))
break; break;
switch (BuiltinName[30]) { switch (BuiltinName[33]) {
default: break; default: break;
case '0': // 1 string to match. case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyu_hl_s0; // "__built in_HEXAGON.M2.mpyu.hl.s0" return Intrinsic::hexagon_M2_mpy_sat_hl_s0; // "__built in_HEXAGON_M2_mpy_sat_hl_s0"
case '1': // 1 string to match. case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyu_hl_s1; // "__built in_HEXAGON.M2.mpyu.hl.s1" return Intrinsic::hexagon_M2_mpy_sat_hl_s1; // "__built in_HEXAGON_M2_mpy_sat_hl_s1"
} }
break; break;
} }
break; break;
case 'l': // 4 strings to match. case 'l': // 4 strings to match.
switch (BuiltinName[27]) { switch (BuiltinName[30]) {
default: break; default: break;
case 'h': // 2 strings to match. case 'h': // 2 strings to match.
if (BuiltinName.substr(28, 2) != ".s") if (memcmp(BuiltinName.data()+31, "_s", 2))
break; break;
switch (BuiltinName[30]) { switch (BuiltinName[33]) {
default: break; default: break;
case '0': // 1 string to match. case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyu_lh_s0; // "__built in_HEXAGON.M2.mpyu.lh.s0" return Intrinsic::hexagon_M2_mpy_sat_lh_s0; // "__built in_HEXAGON_M2_mpy_sat_lh_s0"
case '1': // 1 string to match. case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyu_lh_s1; // "__built in_HEXAGON.M2.mpyu.lh.s1" return Intrinsic::hexagon_M2_mpy_sat_lh_s1; // "__built in_HEXAGON_M2_mpy_sat_lh_s1"
} }
break; break;
case 'l': // 2 strings to match. case 'l': // 2 strings to match.
if (BuiltinName.substr(28, 2) != ".s") if (memcmp(BuiltinName.data()+31, "_s", 2))
break; break;
switch (BuiltinName[30]) { switch (BuiltinName[33]) {
default: break; default: break;
case '0': // 1 string to match. case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyu_ll_s0; // "__built in_HEXAGON.M2.mpyu.ll.s0" return Intrinsic::hexagon_M2_mpy_sat_ll_s0; // "__built in_HEXAGON_M2_mpy_sat_ll_s0"
case '1': // 1 string to match. case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyu_ll_s1; // "__built in_HEXAGON.M2.mpyu.ll.s1" return Intrinsic::hexagon_M2_mpy_sat_ll_s1; // "__built in_HEXAGON_M2_mpy_sat_ll_s1"
} }
break; break;
} }
break; break;
} }
break; break;
} case 'u': // 1 string to match.
break; if (memcmp(BuiltinName.data()+26, "p_s1_sat", 8))
}
break;
case 'v': // 11 strings to match.
switch (BuiltinName[22]) {
default: break;
case 'd': // 2 strings to match.
if (BuiltinName.substr(23, 7) != "mpyrs.s")
break;
switch (BuiltinName[30]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_vdmpyrs_s0; // "__builtin_HEXAG
ON.M2.vdmpyrs.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_vdmpyrs_s1; // "__builtin_HEXAG
ON.M2.vdmpyrs.s1"
}
break;
case 'm': // 4 strings to match.
switch (BuiltinName[23]) {
default: break;
case 'a': // 2 strings to match.
if (BuiltinName.substr(24, 6) != "c2es.s")
break;
switch (BuiltinName[30]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_vmac2es_s0; // "__builtin_HEXAG
ON.M2.vmac2es.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_vmac2es_s1; // "__builtin_HEXAG
ON.M2.vmac2es.s1"
}
break;
case 'p': // 2 strings to match.
if (BuiltinName.substr(24, 6) != "y2es.s")
break; break;
switch (BuiltinName[30]) { return Intrinsic::hexagon_M2_mpy_up_s1_sat; // "__built
default: break; in_HEXAGON_M2_mpy_up_s1_sat"
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_vmpy2es_s0; // "__builtin_HEXAG
ON.M2.vmpy2es.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_vmpy2es_s1; // "__builtin_HEXAG
ON.M2.vmpy2es.s1"
}
break;
} }
break; break;
case 'r': // 5 strings to match. case 'v': // 2 strings to match.
if (BuiltinName.substr(23, 2) != "cm") if (memcmp(BuiltinName.data()+22, "mpy2s_s", 7))
break; break;
switch (BuiltinName[25]) { switch (BuiltinName[29]) {
default: break; default: break;
case 'a': // 2 strings to match. case '0': // 1 string to match.
if (BuiltinName[26] != 'c') if (memcmp(BuiltinName.data()+30, "pack", 4))
break; break;
switch (BuiltinName[27]) { return Intrinsic::hexagon_M2_vmpy2s_s0pack; // "__built
default: break; in_HEXAGON_M2_vmpy2s_s0pack"
case 'i': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(28, 3) != ".s0") if (memcmp(BuiltinName.data()+30, "pack", 4))
break;
return Intrinsic::hexagon_M2_vrcmaci_s0; // "__builtin_HEXAG
ON.M2.vrcmaci.s0"
case 'r': // 1 string to match.
if (BuiltinName.substr(28, 3) != ".s0")
break;
return Intrinsic::hexagon_M2_vrcmacr_s0; // "__builtin_HEXAG
ON.M2.vrcmacr.s0"
}
break;
case 'p': // 3 strings to match.
if (BuiltinName[26] != 'y')
break; break;
switch (BuiltinName[27]) { return Intrinsic::hexagon_M2_vmpy2s_s1pack; // "__built
default: break; in_HEXAGON_M2_vmpy2s_s1pack"
case 'i': // 1 string to match.
if (BuiltinName.substr(28, 3) != ".s0")
break;
return Intrinsic::hexagon_M2_vrcmpyi_s0; // "__builtin_HEXAG
ON.M2.vrcmpyi.s0"
case 'r': // 1 string to match.
if (BuiltinName.substr(28, 3) != ".s0")
break;
return Intrinsic::hexagon_M2_vrcmpyr_s0; // "__builtin_HEXAG
ON.M2.vrcmpyr.s0"
case 's': // 1 string to match.
if (BuiltinName.substr(28, 3) != ".s1")
break;
return Intrinsic::hexagon_M2_vrcmpys_s1; // "__builtin_HEXAG
ON.M2.vrcmpys.s1"
}
break;
} }
break; break;
} }
break; break;
} case '4': // 3 strings to match.
break; if (BuiltinName[20] != '_')
case 'S': // 17 strings to match.
if (BuiltinName.substr(19, 2) != "2.")
break;
switch (BuiltinName[21]) {
default: break;
case 'a': // 8 strings to match.
if (BuiltinName[22] != 's')
break; break;
switch (BuiltinName[23]) { switch (BuiltinName[21]) {
default: break; default: break;
case 'l': // 4 strings to match. case 'm': // 2 strings to match.
if (BuiltinName[24] != '.') switch (BuiltinName[22]) {
break;
switch (BuiltinName[25]) {
default: break;
case 'i': // 2 strings to match.
if (BuiltinName[26] != '.')
break;
switch (BuiltinName[27]) {
default: break;
case 'p': // 1 string to match.
if (BuiltinName.substr(28, 3) != ".or")
break;
return Intrinsic::hexagon_S2_asl_i_p_or; // "__builtin_HEXAG
ON.S2.asl.i.p.or"
case 'r': // 1 string to match.
if (BuiltinName.substr(28, 3) != ".or")
break;
return Intrinsic::hexagon_S2_asl_i_r_or; // "__builtin_HEXAG
ON.S2.asl.i.r.or"
}
break;
case 'r': // 2 strings to match.
if (BuiltinName[26] != '.')
break;
switch (BuiltinName[27]) {
default: break;
case 'p': // 1 string to match.
if (BuiltinName.substr(28, 3) != ".or")
break;
return Intrinsic::hexagon_S2_asl_r_p_or; // "__builtin_HEXAG
ON.S2.asl.r.p.or"
case 'r': // 1 string to match.
if (BuiltinName.substr(28, 3) != ".or")
break;
return Intrinsic::hexagon_S2_asl_r_r_or; // "__builtin_HEXAG
ON.S2.asl.r.r.or"
}
break;
}
break;
case 'r': // 4 strings to match.
if (BuiltinName[24] != '.')
break;
switch (BuiltinName[25]) {
default: break; default: break;
case 'i': // 2 strings to match. case 'a': // 1 string to match.
if (BuiltinName[26] != '.') if (memcmp(BuiltinName.data()+23, "c_up_s1_sat", 11))
break;
switch (BuiltinName[27]) {
default: break;
case 'p': // 1 string to match.
if (BuiltinName.substr(28, 3) != ".or")
break;
return Intrinsic::hexagon_S2_asr_i_p_or; // "__builtin_HEXAG
ON.S2.asr.i.p.or"
case 'r': // 1 string to match.
if (BuiltinName.substr(28, 3) != ".or")
break;
return Intrinsic::hexagon_S2_asr_i_r_or; // "__builtin_HEXAG
ON.S2.asr.i.r.or"
}
break;
case 'r': // 2 strings to match.
if (BuiltinName[26] != '.')
break; break;
switch (BuiltinName[27]) { return Intrinsic::hexagon_M4_mac_up_s1_sat; // "__built
default: break; in_HEXAGON_M4_mac_up_s1_sat"
case 'p': // 1 string to match.
if (BuiltinName.substr(28, 3) != ".or")
break;
return Intrinsic::hexagon_S2_asr_r_p_or; // "__builtin_HEXAG
ON.S2.asr.r.p.or"
case 'r': // 1 string to match.
if (BuiltinName.substr(28, 3) != ".or")
break;
return Intrinsic::hexagon_S2_asr_r_r_or; // "__builtin_HEXAG
ON.S2.asr.r.r.or"
}
break;
}
break;
}
break;
case 'i': // 2 strings to match.
if (BuiltinName[22] != 'n')
break;
switch (BuiltinName[23]) {
default: break;
case 's': // 1 string to match.
if (BuiltinName.substr(24, 7) != "ertp.rp")
break;
return Intrinsic::hexagon_S2_insertp_rp; // "__builtin_HEXAG
ON.S2.insertp.rp"
case 't': // 1 string to match.
if (BuiltinName.substr(24, 7) != "erleave")
break;
return Intrinsic::hexagon_S2_interleave; // "__builtin_HEXAG
ON.S2.interleave"
}
break;
case 'l': // 6 strings to match.
if (BuiltinName[22] != 's')
break;
switch (BuiltinName[23]) {
default: break;
case 'l': // 2 strings to match.
if (BuiltinName.substr(24, 3) != ".r.")
break;
switch (BuiltinName[27]) {
default: break;
case 'p': // 1 string to match. case 'p': // 1 string to match.
if (BuiltinName.substr(28, 3) != ".or") if (memcmp(BuiltinName.data()+23, "yri_addr_u2", 11))
break;
return Intrinsic::hexagon_S2_lsl_r_p_or; // "__builtin_HEXAG
ON.S2.lsl.r.p.or"
case 'r': // 1 string to match.
if (BuiltinName.substr(28, 3) != ".or")
break; break;
return Intrinsic::hexagon_S2_lsl_r_r_or; // "__builtin_HEXAG ON.S2.lsl.r.r.or" return Intrinsic::hexagon_M4_mpyri_addr_u2; // "__built in_HEXAGON_M4_mpyri_addr_u2"
} }
break; break;
case 'r': // 4 strings to match. case 'n': // 1 string to match.
if (BuiltinName[24] != '.') if (memcmp(BuiltinName.data()+22, "ac_up_s1_sat", 12))
break;
switch (BuiltinName[25]) {
default: break;
case 'i': // 2 strings to match.
if (BuiltinName[26] != '.')
break;
switch (BuiltinName[27]) {
default: break;
case 'p': // 1 string to match.
if (BuiltinName.substr(28, 3) != ".or")
break;
return Intrinsic::hexagon_S2_lsr_i_p_or; // "__builtin_HEXAG
ON.S2.lsr.i.p.or"
case 'r': // 1 string to match.
if (BuiltinName.substr(28, 3) != ".or")
break;
return Intrinsic::hexagon_S2_lsr_i_r_or; // "__builtin_HEXAG
ON.S2.lsr.i.r.or"
}
break;
case 'r': // 2 strings to match.
if (BuiltinName[26] != '.')
break;
switch (BuiltinName[27]) {
default: break;
case 'p': // 1 string to match.
if (BuiltinName.substr(28, 3) != ".or")
break;
return Intrinsic::hexagon_S2_lsr_r_p_or; // "__builtin_HEXAG
ON.S2.lsr.r.p.or"
case 'r': // 1 string to match.
if (BuiltinName.substr(28, 3) != ".or")
break;
return Intrinsic::hexagon_S2_lsr_r_r_or; // "__builtin_HEXAG
ON.S2.lsr.r.r.or"
}
break; break;
} return Intrinsic::hexagon_M4_nac_up_s1_sat; // "__builtin_HEXAG
break; ON_M4_nac_up_s1_sat"
} }
break; break;
case 'v': // 1 string to match.
if (BuiltinName.substr(22, 9) != "rndpackwh")
break;
return Intrinsic::hexagon_S2_vrndpackwh; // "__builtin_HEXAG
ON.S2.vrndpackwh"
} }
break; break;
} case 'S': // 3 strings to match.
break; switch (BuiltinName[19]) {
case 32: // 84 strings to match.
if (BuiltinName.substr(0, 18) != "__builtin_HEXAGON.")
break;
switch (BuiltinName[18]) {
default: break;
case 'A': // 16 strings to match.
if (BuiltinName.substr(19, 2) != "2.")
break;
switch (BuiltinName[21]) {
default: break; default: break;
case 'a': // 8 strings to match. case '2': // 2 strings to match.
if (BuiltinName.substr(22, 4) != "ddh.") if (memcmp(BuiltinName.data()+20, "_vsat", 5))
break; break;
switch (BuiltinName[26]) { switch (BuiltinName[25]) {
default: break; default: break;
case 'h': // 4 strings to match. case 'h': // 1 string to match.
if (BuiltinName.substr(27, 3) != "16.") if (memcmp(BuiltinName.data()+26, "b_nopack", 8))
break;
switch (BuiltinName[30]) {
default: break;
case 'h': // 2 strings to match.
switch (BuiltinName[31]) {
default: break;
case 'h': // 1 string to match.
return Intrinsic::hexagon_A2_addh_h16_hh; // "__built
in_HEXAGON.A2.addh.h16.hh"
case 'l': // 1 string to match.
return Intrinsic::hexagon_A2_addh_h16_hl; // "__built
in_HEXAGON.A2.addh.h16.hl"
}
break;
case 'l': // 2 strings to match.
switch (BuiltinName[31]) {
default: break;
case 'h': // 1 string to match.
return Intrinsic::hexagon_A2_addh_h16_lh; // "__built
in_HEXAGON.A2.addh.h16.lh"
case 'l': // 1 string to match.
return Intrinsic::hexagon_A2_addh_h16_ll; // "__built
in_HEXAGON.A2.addh.h16.ll"
}
break;
}
break;
case 'l': // 4 strings to match.
if (BuiltinName.substr(27, 3) != "16.")
break;
switch (BuiltinName[30]) {
default: break;
case 'h': // 2 strings to match.
switch (BuiltinName[31]) {
default: break;
case 'h': // 1 string to match.
return Intrinsic::hexagon_A2_addh_l16_hh; // "__built
in_HEXAGON.A2.addh.l16.hh"
case 'l': // 1 string to match.
return Intrinsic::hexagon_A2_addh_l16_hl; // "__built
in_HEXAGON.A2.addh.l16.hl"
}
break; break;
case 'l': // 2 strings to match. return Intrinsic::hexagon_S2_vsathb_nopack; // "__builtin_HEXAG
switch (BuiltinName[31]) { ON_S2_vsathb_nopack"
default: break; case 'w': // 1 string to match.
case 'h': // 1 string to match. if (memcmp(BuiltinName.data()+26, "h_nopack", 8))
return Intrinsic::hexagon_A2_addh_l16_lh; // "__built
in_HEXAGON.A2.addh.l16.lh"
case 'l': // 1 string to match.
return Intrinsic::hexagon_A2_addh_l16_ll; // "__built
in_HEXAGON.A2.addh.l16.ll"
}
break; break;
} return Intrinsic::hexagon_S2_vsatwh_nopack; // "__builtin_HEXAG
break; ON_S2_vsatwh_nopack"
} }
break; break;
case 's': // 6 strings to match. case '4': // 1 string to match.
if (BuiltinName.substr(22, 4) != "ubh.") if (memcmp(BuiltinName.data()+20, "_vrcrotate_acc", 14))
break; break;
switch (BuiltinName[26]) { return Intrinsic::hexagon_S4_vrcrotate_acc; // "__builtin_HEXAG
default: break; ON_S4_vrcrotate_acc"
case 'h': // 4 strings to match. }
if (BuiltinName.substr(27, 3) != "16.") break;
break; }
switch (BuiltinName[30]) { break;
default: break; case 35: // 64 strings to match.
case 'h': // 2 strings to match. if (memcmp(BuiltinName.data()+0, "__builtin_HEXAGON_", 18))
switch (BuiltinName[31]) { break;
default: break; switch (BuiltinName[18]) {
case 'h': // 1 string to match. default: break;
return Intrinsic::hexagon_A2_subh_h16_hh; // "__built case 'F': // 4 strings to match.
in_HEXAGON.A2.subh.h16.hh" if (memcmp(BuiltinName.data()+19, "2_conv_", 7))
case 'l': // 1 string to match. break;
return Intrinsic::hexagon_A2_subh_h16_hl; // "__built switch (BuiltinName[26]) {
in_HEXAGON.A2.subh.h16.hl" default: break;
} case 'd': // 2 strings to match.
break; if (memcmp(BuiltinName.data()+27, "f2", 2))
case 'l': // 2 strings to match.
switch (BuiltinName[31]) {
default: break;
case 'h': // 1 string to match.
return Intrinsic::hexagon_A2_subh_h16_lh; // "__built
in_HEXAGON.A2.subh.h16.lh"
case 'l': // 1 string to match.
return Intrinsic::hexagon_A2_subh_h16_ll; // "__built
in_HEXAGON.A2.subh.h16.ll"
}
break;
}
break; break;
case 'l': // 2 strings to match. switch (BuiltinName[29]) {
if (BuiltinName.substr(27, 3) != "16.") default: break;
case 'd': // 1 string to match.
if (memcmp(BuiltinName.data()+30, "_chop", 5))
break; break;
switch (BuiltinName[30]) { return Intrinsic::hexagon_F2_conv_df2d_chop; // "__builtin_HEXAG
default: break; ON_F2_conv_df2d_chop"
case 'h': // 1 string to match. case 'w': // 1 string to match.
if (BuiltinName[31] != 'l') if (memcmp(BuiltinName.data()+30, "_chop", 5))
break; break;
return Intrinsic::hexagon_A2_subh_l16_hl; // "__builtin_HEXAG return Intrinsic::hexagon_F2_conv_df2w_chop; // "__builtin_HEXAG
ON.A2.subh.l16.hl" ON_F2_conv_df2w_chop"
case 'l': // 1 string to match.
if (BuiltinName[31] != 'l')
break;
return Intrinsic::hexagon_A2_subh_l16_ll; // "__builtin_HEXAG
ON.A2.subh.l16.ll"
}
break;
} }
break; break;
case 'v': // 2 strings to match. case 's': // 2 strings to match.
if (BuiltinName[22] != 'r') if (memcmp(BuiltinName.data()+27, "f2", 2))
break; break;
switch (BuiltinName[23]) { switch (BuiltinName[29]) {
default: break; default: break;
case 'a': // 1 string to match. case 'd': // 1 string to match.
if (BuiltinName.substr(24, 8) != "ddub.acc") if (memcmp(BuiltinName.data()+30, "_chop", 5))
break; break;
return Intrinsic::hexagon_A2_vraddub_acc; // "__builtin_HEXAG return Intrinsic::hexagon_F2_conv_sf2d_chop; // "__builtin_HEXAG
ON.A2.vraddub.acc" ON_F2_conv_sf2d_chop"
case 's': // 1 string to match. case 'w': // 1 string to match.
if (BuiltinName.substr(24, 8) != "adub.acc") if (memcmp(BuiltinName.data()+30, "_chop", 5))
break; break;
return Intrinsic::hexagon_A2_vrsadub_acc; // "__builtin_HEXAG ON.A2.vrsadub.acc" return Intrinsic::hexagon_F2_conv_sf2w_chop; // "__builtin_HEXAG ON_F2_conv_sf2w_chop"
} }
break; break;
} }
break; break;
case 'C': // 1 string to match. case 'M': // 56 strings to match.
if (BuiltinName.substr(19, 13) != "4.fastcorner9") switch (BuiltinName[19]) {
break;
return Intrinsic::hexagon_C4_fastcorner9; // "__builtin_HEXAG
ON.C4.fastcorner9"
case 'M': // 16 strings to match.
if (BuiltinName.substr(19, 2) != "2.")
break;
switch (BuiltinName[21]) {
default: break; default: break;
case 'm': // 12 strings to match. case '2': // 52 strings to match.
switch (BuiltinName[22]) { if (BuiltinName[20] != '_')
break;
switch (BuiltinName[21]) {
default: break; default: break;
case 'm': // 4 strings to match. case 'd': // 5 strings to match.
if (BuiltinName.substr(23, 3) != "acu") if (memcmp(BuiltinName.data()+22, "pmpy", 4))
break; break;
switch (BuiltinName[26]) { switch (BuiltinName[26]) {
default: break; default: break;
case 'h': // 2 strings to match. case 's': // 3 strings to match.
if (BuiltinName.substr(27, 4) != "s.rs") if (memcmp(BuiltinName.data()+27, "s_", 2))
break;
switch (BuiltinName[31]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mmacuhs_rs0; // "__built
in_HEXAGON.M2.mmacuhs.rs0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mmacuhs_rs1; // "__built
in_HEXAGON.M2.mmacuhs.rs1"
}
break;
case 'l': // 2 strings to match.
if (BuiltinName.substr(27, 4) != "s.rs")
break; break;
switch (BuiltinName[31]) { switch (BuiltinName[29]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mmaculs_rs0; // "__built
in_HEXAGON.M2.mmaculs.rs0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mmaculs_rs1; // "__built
in_HEXAGON.M2.mmaculs.rs1"
}
break;
}
break;
case 'p': // 8 strings to match.
if (BuiltinName.substr(23, 4) != "yud.")
break;
switch (BuiltinName[27]) {
default: break;
case 'h': // 4 strings to match.
switch (BuiltinName[28]) {
default: break; default: break;
case 'h': // 2 strings to match. case 'a': // 1 string to match.
if (BuiltinName.substr(29, 2) != ".s") if (memcmp(BuiltinName.data()+30, "cc_s0", 5))
break; break;
switch (BuiltinName[31]) { return Intrinsic::hexagon_M2_dpmpyss_acc_s0; // "__built
default: break; in_HEXAGON_M2_dpmpyss_acc_s0"
case '0': // 1 string to match. case 'n': // 1 string to match.
return Intrinsic::hexagon_M2_mpyud_hh_s0; // "__built if (memcmp(BuiltinName.data()+30, "ac_s0", 5))
in_HEXAGON.M2.mpyud.hh.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyud_hh_s1; // "__built
in_HEXAGON.M2.mpyud.hh.s1"
}
break;
case 'l': // 2 strings to match.
if (BuiltinName.substr(29, 2) != ".s")
break; break;
switch (BuiltinName[31]) { return Intrinsic::hexagon_M2_dpmpyss_nac_s0; // "__built
default: break; in_HEXAGON_M2_dpmpyss_nac_s0"
case '0': // 1 string to match. case 'r': // 1 string to match.
return Intrinsic::hexagon_M2_mpyud_hl_s0; // "__built if (memcmp(BuiltinName.data()+30, "nd_s0", 5))
in_HEXAGON.M2.mpyud.hl.s0" break;
case '1': // 1 string to match. return Intrinsic::hexagon_M2_dpmpyss_rnd_s0; // "__built
return Intrinsic::hexagon_M2_mpyud_hl_s1; // "__built in_HEXAGON_M2_dpmpyss_rnd_s0"
in_HEXAGON.M2.mpyud.hl.s1"
}
break;
} }
break; break;
case 'l': // 4 strings to match. case 'u': // 2 strings to match.
switch (BuiltinName[28]) { if (memcmp(BuiltinName.data()+27, "u_", 2))
break;
switch (BuiltinName[29]) {
default: break; default: break;
case 'h': // 2 strings to match. case 'a': // 1 string to match.
if (BuiltinName.substr(29, 2) != ".s") if (memcmp(BuiltinName.data()+30, "cc_s0", 5))
break; break;
switch (BuiltinName[31]) { return Intrinsic::hexagon_M2_dpmpyuu_acc_s0; // "__built
default: break; in_HEXAGON_M2_dpmpyuu_acc_s0"
case '0': // 1 string to match. case 'n': // 1 string to match.
return Intrinsic::hexagon_M2_mpyud_lh_s0; // "__built if (memcmp(BuiltinName.data()+30, "ac_s0", 5))
in_HEXAGON.M2.mpyud.lh.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyud_lh_s1; // "__built
in_HEXAGON.M2.mpyud.lh.s1"
}
break;
case 'l': // 2 strings to match.
if (BuiltinName.substr(29, 2) != ".s")
break; break;
switch (BuiltinName[31]) { return Intrinsic::hexagon_M2_dpmpyuu_nac_s0; // "__built
default: break; in_HEXAGON_M2_dpmpyuu_nac_s0"
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyud_ll_s0; // "__built
in_HEXAGON.M2.mpyud.ll.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyud_ll_s1; // "__built
in_HEXAGON.M2.mpyud.ll.s1"
}
break;
} }
break; break;
} }
break; break;
} case 'm': // 40 strings to match.
break; if (memcmp(BuiltinName.data()+22, "py", 2))
case 'v': // 4 strings to match.
if (BuiltinName.substr(22, 3) != "rcm")
break;
switch (BuiltinName[25]) {
default: break;
case 'a': // 2 strings to match.
if (BuiltinName[26] != 'c')
break;
switch (BuiltinName[27]) {
default: break;
case 'i': // 1 string to match.
if (BuiltinName.substr(28, 4) != ".s0c")
break;
return Intrinsic::hexagon_M2_vrcmaci_s0c; // "__builtin_HEXAG
ON.M2.vrcmaci.s0c"
case 'r': // 1 string to match.
if (BuiltinName.substr(28, 4) != ".s0c")
break;
return Intrinsic::hexagon_M2_vrcmacr_s0c; // "__builtin_HEXAG
ON.M2.vrcmacr.s0c"
}
break;
case 'p': // 2 strings to match.
if (BuiltinName[26] != 'y')
break;
switch (BuiltinName[27]) {
default: break;
case 'i': // 1 string to match.
if (BuiltinName.substr(28, 4) != ".s0c")
break;
return Intrinsic::hexagon_M2_vrcmpyi_s0c; // "__builtin_HEXAG
ON.M2.vrcmpyi.s0c"
case 'r': // 1 string to match.
if (BuiltinName.substr(28, 4) != ".s0c")
break;
return Intrinsic::hexagon_M2_vrcmpyr_s0c; // "__builtin_HEXAG
ON.M2.vrcmpyr.s0c"
}
break;
}
break;
}
break;
case 'S': // 51 strings to match.
if (BuiltinName.substr(19, 2) != "2.")
break;
switch (BuiltinName[21]) {
default: break;
case 'a': // 29 strings to match.
switch (BuiltinName[22]) {
default: break;
case 'd': // 1 string to match.
if (BuiltinName.substr(23, 9) != "dasl.rrri")
break; break;
return Intrinsic::hexagon_S2_addasl_rrri; // "__builtin_HEXAG switch (BuiltinName[24]) {
ON.S2.addasl.rrri"
case 's': // 28 strings to match.
switch (BuiltinName[23]) {
default: break; default: break;
case 'l': // 14 strings to match. case 'd': // 24 strings to match.
if (BuiltinName[24] != '.') if (BuiltinName[25] != '_')
break; break;
switch (BuiltinName[25]) { switch (BuiltinName[26]) {
default: break; default: break;
case 'i': // 7 strings to match. case 'a': // 8 strings to match.
if (BuiltinName[26] != '.') if (memcmp(BuiltinName.data()+27, "cc_", 3))
break; break;
switch (BuiltinName[27]) { switch (BuiltinName[30]) {
default: break; default: break;
case 'p': // 3 strings to match. case 'h': // 4 strings to match.
if (BuiltinName[28] != '.') switch (BuiltinName[31]) {
break;
switch (BuiltinName[29]) {
default: break; default: break;
case 'a': // 2 strings to match. case 'h': // 2 strings to match.
switch (BuiltinName[30]) { if (memcmp(BuiltinName.data()+32, "_s", 2))
break;
switch (BuiltinName[34]) {
default: break; default: break;
case 'c': // 1 string to match. case '0': // 1 string to match.
if (BuiltinName[31] != 'c') return Intrinsic::hexagon_M2_mpyd_acc_hh_s0; //
break; "__builtin_HEXAGON_M2_mpyd_acc_hh_s0"
return Intrinsic::hexagon_S2_asl_i_p_acc; // "__built case '1': // 1 string to match.
in_HEXAGON.S2.asl.i.p.acc" return Intrinsic::hexagon_M2_mpyd_acc_hh_s1; //
case 'n': // 1 string to match. "__builtin_HEXAGON_M2_mpyd_acc_hh_s1"
if (BuiltinName[31] != 'd')
break;
return Intrinsic::hexagon_S2_asl_i_p_and; // "__built
in_HEXAGON.S2.asl.i.p.and"
} }
break; break;
case 'n': // 1 string to match. case 'l': // 2 strings to match.
if (BuiltinName.substr(30, 2) != "ac") if (memcmp(BuiltinName.data()+32, "_s", 2))
break; break;
return Intrinsic::hexagon_S2_asl_i_p_nac; // "__built switch (BuiltinName[34]) {
in_HEXAGON.S2.asl.i.p.nac"
}
break;
case 'r': // 4 strings to match.
if (BuiltinName[28] != '.')
break;
switch (BuiltinName[29]) {
default: break;
case 'a': // 2 strings to match.
switch (BuiltinName[30]) {
default: break; default: break;
case 'c': // 1 string to match. case '0': // 1 string to match.
if (BuiltinName[31] != 'c') return Intrinsic::hexagon_M2_mpyd_acc_hl_s0; //
break; "__builtin_HEXAGON_M2_mpyd_acc_hl_s0"
return Intrinsic::hexagon_S2_asl_i_r_acc; // "__built case '1': // 1 string to match.
in_HEXAGON.S2.asl.i.r.acc" return Intrinsic::hexagon_M2_mpyd_acc_hl_s1; //
case 'n': // 1 string to match. "__builtin_HEXAGON_M2_mpyd_acc_hl_s1"
if (BuiltinName[31] != 'd')
break;
return Intrinsic::hexagon_S2_asl_i_r_and; // "__built
in_HEXAGON.S2.asl.i.r.and"
} }
break; break;
case 'n': // 1 string to match.
if (BuiltinName.substr(30, 2) != "ac")
break;
return Intrinsic::hexagon_S2_asl_i_r_nac; // "__built
in_HEXAGON.S2.asl.i.r.nac"
case 's': // 1 string to match.
if (BuiltinName.substr(30, 2) != "at")
break;
return Intrinsic::hexagon_S2_asl_i_r_sat; // "__built
in_HEXAGON.S2.asl.i.r.sat"
} }
break; break;
} case 'l': // 4 strings to match.
break; switch (BuiltinName[31]) {
case 'r': // 7 strings to match.
if (BuiltinName[26] != '.')
break;
switch (BuiltinName[27]) {
default: break;
case 'p': // 3 strings to match.
if (BuiltinName[28] != '.')
break;
switch (BuiltinName[29]) {
default: break; default: break;
case 'a': // 2 strings to match. case 'h': // 2 strings to match.
switch (BuiltinName[30]) { if (memcmp(BuiltinName.data()+32, "_s", 2))
break;
switch (BuiltinName[34]) {
default: break; default: break;
case 'c': // 1 string to match. case '0': // 1 string to match.
if (BuiltinName[31] != 'c') return Intrinsic::hexagon_M2_mpyd_acc_lh_s0; //
break; "__builtin_HEXAGON_M2_mpyd_acc_lh_s0"
return Intrinsic::hexagon_S2_asl_r_p_acc; // "__built case '1': // 1 string to match.
in_HEXAGON.S2.asl.r.p.acc" return Intrinsic::hexagon_M2_mpyd_acc_lh_s1; //
case 'n': // 1 string to match. "__builtin_HEXAGON_M2_mpyd_acc_lh_s1"
if (BuiltinName[31] != 'd')
break;
return Intrinsic::hexagon_S2_asl_r_p_and; // "__built
in_HEXAGON.S2.asl.r.p.and"
} }
break; break;
case 'n': // 1 string to match. case 'l': // 2 strings to match.
if (BuiltinName.substr(30, 2) != "ac") if (memcmp(BuiltinName.data()+32, "_s", 2))
break; break;
return Intrinsic::hexagon_S2_asl_r_p_nac; // "__built switch (BuiltinName[34]) {
in_HEXAGON.S2.asl.r.p.nac"
}
break;
case 'r': // 4 strings to match.
if (BuiltinName[28] != '.')
break;
switch (BuiltinName[29]) {
default: break;
case 'a': // 2 strings to match.
switch (BuiltinName[30]) {
default: break; default: break;
case 'c': // 1 string to match. case '0': // 1 string to match.
if (BuiltinName[31] != 'c') return Intrinsic::hexagon_M2_mpyd_acc_ll_s0; //
break; "__builtin_HEXAGON_M2_mpyd_acc_ll_s0"
return Intrinsic::hexagon_S2_asl_r_r_acc; // "__built case '1': // 1 string to match.
in_HEXAGON.S2.asl.r.r.acc" return Intrinsic::hexagon_M2_mpyd_acc_ll_s1; //
case 'n': // 1 string to match. "__builtin_HEXAGON_M2_mpyd_acc_ll_s1"
if (BuiltinName[31] != 'd')
break;
return Intrinsic::hexagon_S2_asl_r_r_and; // "__built
in_HEXAGON.S2.asl.r.r.and"
} }
break; break;
case 'n': // 1 string to match.
if (BuiltinName.substr(30, 2) != "ac")
break;
return Intrinsic::hexagon_S2_asl_r_r_nac; // "__built
in_HEXAGON.S2.asl.r.r.nac"
case 's': // 1 string to match.
if (BuiltinName.substr(30, 2) != "at")
break;
return Intrinsic::hexagon_S2_asl_r_r_sat; // "__built
in_HEXAGON.S2.asl.r.r.sat"
} }
break; break;
} }
break; break;
} case 'n': // 8 strings to match.
break; if (memcmp(BuiltinName.data()+27, "ac_", 3))
case 'r': // 14 strings to match.
if (BuiltinName[24] != '.')
break;
switch (BuiltinName[25]) {
default: break;
case 'i': // 7 strings to match.
if (BuiltinName[26] != '.')
break; break;
switch (BuiltinName[27]) { switch (BuiltinName[30]) {
default: break; default: break;
case 'p': // 3 strings to match. case 'h': // 4 strings to match.
if (BuiltinName[28] != '.') switch (BuiltinName[31]) {
break; default: break;
switch (BuiltinName[29]) { case 'h': // 2 strings to match.
default: break; if (memcmp(BuiltinName.data()+32, "_s", 2))
case 'a': // 2 strings to match. break;
switch (BuiltinName[30]) { switch (BuiltinName[34]) {
default: break; default: break;
case 'c': // 1 string to match. case '0': // 1 string to match.
if (BuiltinName[31] != 'c') return Intrinsic::hexagon_M2_mpyd_nac_hh_s0; //
break; "__builtin_HEXAGON_M2_mpyd_nac_hh_s0"
return Intrinsic::hexagon_S2_asr_i_p_acc; // "__built case '1': // 1 string to match.
in_HEXAGON.S2.asr.i.p.acc" return Intrinsic::hexagon_M2_mpyd_nac_hh_s1; //
case 'n': // 1 string to match. "__builtin_HEXAGON_M2_mpyd_nac_hh_s1"
if (BuiltinName[31] != 'd')
break;
return Intrinsic::hexagon_S2_asr_i_p_and; // "__built
in_HEXAGON.S2.asr.i.p.and"
} }
break; break;
case 'n': // 1 string to match. case 'l': // 2 strings to match.
if (BuiltinName.substr(30, 2) != "ac") if (memcmp(BuiltinName.data()+32, "_s", 2))
break; break;
return Intrinsic::hexagon_S2_asr_i_p_nac; // "__built switch (BuiltinName[34]) {
in_HEXAGON.S2.asr.i.p.nac" default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_nac_hl_s0; //
"__builtin_HEXAGON_M2_mpyd_nac_hl_s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_nac_hl_s1; //
"__builtin_HEXAGON_M2_mpyd_nac_hl_s1"
}
break;
} }
break; break;
case 'r': // 4 strings to match. case 'l': // 4 strings to match.
if (BuiltinName[28] != '.') switch (BuiltinName[31]) {
break;
switch (BuiltinName[29]) {
default: break; default: break;
case 'a': // 2 strings to match. case 'h': // 2 strings to match.
switch (BuiltinName[30]) { if (memcmp(BuiltinName.data()+32, "_s", 2))
break;
switch (BuiltinName[34]) {
default: break; default: break;
case 'c': // 1 string to match. case '0': // 1 string to match.
if (BuiltinName[31] != 'c') return Intrinsic::hexagon_M2_mpyd_nac_lh_s0; //
break; "__builtin_HEXAGON_M2_mpyd_nac_lh_s0"
return Intrinsic::hexagon_S2_asr_i_r_acc; // "__built case '1': // 1 string to match.
in_HEXAGON.S2.asr.i.r.acc" return Intrinsic::hexagon_M2_mpyd_nac_lh_s1; //
case 'n': // 1 string to match. "__builtin_HEXAGON_M2_mpyd_nac_lh_s1"
if (BuiltinName[31] != 'd')
break;
return Intrinsic::hexagon_S2_asr_i_r_and; // "__built
in_HEXAGON.S2.asr.i.r.and"
} }
break; break;
case 'n': // 1 string to match. case 'l': // 2 strings to match.
if (BuiltinName.substr(30, 2) != "ac") if (memcmp(BuiltinName.data()+32, "_s", 2))
break;
return Intrinsic::hexagon_S2_asr_i_r_nac; // "__built
in_HEXAGON.S2.asr.i.r.nac"
case 'r': // 1 string to match.
if (BuiltinName.substr(30, 2) != "nd")
break; break;
return Intrinsic::hexagon_S2_asr_i_r_rnd; // "__built switch (BuiltinName[34]) {
in_HEXAGON.S2.asr.i.r.rnd" default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_nac_ll_s0; //
"__builtin_HEXAGON_M2_mpyd_nac_ll_s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_nac_ll_s1; //
"__builtin_HEXAGON_M2_mpyd_nac_ll_s1"
}
break;
} }
break; break;
} }
break; break;
case 'r': // 7 strings to match. case 'r': // 8 strings to match.
if (BuiltinName[26] != '.') if (memcmp(BuiltinName.data()+27, "nd_", 3))
break; break;
switch (BuiltinName[27]) { switch (BuiltinName[30]) {
default: break; default: break;
case 'p': // 3 strings to match. case 'h': // 4 strings to match.
if (BuiltinName[28] != '.') switch (BuiltinName[31]) {
break;
switch (BuiltinName[29]) {
default: break; default: break;
case 'a': // 2 strings to match. case 'h': // 2 strings to match.
switch (BuiltinName[30]) { if (memcmp(BuiltinName.data()+32, "_s", 2))
break;
switch (BuiltinName[34]) {
default: break; default: break;
case 'c': // 1 string to match. case '0': // 1 string to match.
if (BuiltinName[31] != 'c') return Intrinsic::hexagon_M2_mpyd_rnd_hh_s0; //
break; "__builtin_HEXAGON_M2_mpyd_rnd_hh_s0"
return Intrinsic::hexagon_S2_asr_r_p_acc; // "__built case '1': // 1 string to match.
in_HEXAGON.S2.asr.r.p.acc" return Intrinsic::hexagon_M2_mpyd_rnd_hh_s1; //
case 'n': // 1 string to match. "__builtin_HEXAGON_M2_mpyd_rnd_hh_s1"
if (BuiltinName[31] != 'd')
break;
return Intrinsic::hexagon_S2_asr_r_p_and; // "__built
in_HEXAGON.S2.asr.r.p.and"
} }
break; break;
case 'n': // 1 string to match. case 'l': // 2 strings to match.
if (BuiltinName.substr(30, 2) != "ac") if (memcmp(BuiltinName.data()+32, "_s", 2))
break; break;
return Intrinsic::hexagon_S2_asr_r_p_nac; // "__built switch (BuiltinName[34]) {
in_HEXAGON.S2.asr.r.p.nac" default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_rnd_hl_s0; //
"__builtin_HEXAGON_M2_mpyd_rnd_hl_s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_rnd_hl_s1; //
"__builtin_HEXAGON_M2_mpyd_rnd_hl_s1"
}
break;
} }
break; break;
case 'r': // 4 strings to match. case 'l': // 4 strings to match.
if (BuiltinName[28] != '.') switch (BuiltinName[31]) {
break;
switch (BuiltinName[29]) {
default: break; default: break;
case 'a': // 2 strings to match. case 'h': // 2 strings to match.
switch (BuiltinName[30]) { if (memcmp(BuiltinName.data()+32, "_s", 2))
break;
switch (BuiltinName[34]) {
default: break; default: break;
case 'c': // 1 string to match. case '0': // 1 string to match.
if (BuiltinName[31] != 'c') return Intrinsic::hexagon_M2_mpyd_rnd_lh_s0; //
break; "__builtin_HEXAGON_M2_mpyd_rnd_lh_s0"
return Intrinsic::hexagon_S2_asr_r_r_acc; // "__built case '1': // 1 string to match.
in_HEXAGON.S2.asr.r.r.acc" return Intrinsic::hexagon_M2_mpyd_rnd_lh_s1; //
case 'n': // 1 string to match. "__builtin_HEXAGON_M2_mpyd_rnd_lh_s1"
if (BuiltinName[31] != 'd')
break;
return Intrinsic::hexagon_S2_asr_r_r_and; // "__built
in_HEXAGON.S2.asr.r.r.and"
} }
break; break;
case 'n': // 1 string to match. case 'l': // 2 strings to match.
if (BuiltinName.substr(30, 2) != "ac") if (memcmp(BuiltinName.data()+32, "_s", 2))
break;
return Intrinsic::hexagon_S2_asr_r_r_nac; // "__built
in_HEXAGON.S2.asr.r.r.nac"
case 's': // 1 string to match.
if (BuiltinName.substr(30, 2) != "at")
break; break;
return Intrinsic::hexagon_S2_asr_r_r_sat; // "__built switch (BuiltinName[34]) {
in_HEXAGON.S2.asr.r.r.sat" default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_rnd_ll_s0; //
"__builtin_HEXAGON_M2_mpyd_rnd_ll_s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_rnd_ll_s1; //
"__builtin_HEXAGON_M2_mpyd_rnd_ll_s1"
}
break;
} }
break; break;
} }
break; break;
} }
break; break;
} case 'u': // 16 strings to match.
break; if (BuiltinName[25] != '_')
}
break;
case 'e': // 1 string to match.
if (BuiltinName.substr(22, 10) != "xtractu.rp")
break;
return Intrinsic::hexagon_S2_extractu_rp; // "__builtin_HEXAG
ON.S2.extractu.rp"
case 'l': // 18 strings to match.
if (BuiltinName[22] != 's')
break;
switch (BuiltinName[23]) {
default: break;
case 'l': // 6 strings to match.
if (BuiltinName.substr(24, 3) != ".r.")
break;
switch (BuiltinName[27]) {
default: break;
case 'p': // 3 strings to match.
if (BuiltinName[28] != '.')
break; break;
switch (BuiltinName[29]) { switch (BuiltinName[26]) {
default: break; default: break;
case 'a': // 2 strings to match. case 'a': // 8 strings to match.
switch (BuiltinName[30]) { if (memcmp(BuiltinName.data()+27, "cc_", 3))
default: break;
case 'c': // 1 string to match.
if (BuiltinName[31] != 'c')
break;
return Intrinsic::hexagon_S2_lsl_r_p_acc; // "__built
in_HEXAGON.S2.lsl.r.p.acc"
case 'n': // 1 string to match.
if (BuiltinName[31] != 'd')
break;
return Intrinsic::hexagon_S2_lsl_r_p_and; // "__built
in_HEXAGON.S2.lsl.r.p.and"
}
break;
case 'n': // 1 string to match.
if (BuiltinName.substr(30, 2) != "ac")
break; break;
return Intrinsic::hexagon_S2_lsl_r_p_nac; // "__built
in_HEXAGON.S2.lsl.r.p.nac"
}
break;
case 'r': // 3 strings to match.
if (BuiltinName[28] != '.')
break;
switch (BuiltinName[29]) {
default: break;
case 'a': // 2 strings to match.
switch (BuiltinName[30]) { switch (BuiltinName[30]) {
default: break; default: break;
case 'c': // 1 string to match. case 'h': // 4 strings to match.
if (BuiltinName[31] != 'c') switch (BuiltinName[31]) {
default: break;
case 'h': // 2 strings to match.
if (memcmp(BuiltinName.data()+32, "_s", 2))
break;
switch (BuiltinName[34]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyu_acc_hh_s0; //
"__builtin_HEXAGON_M2_mpyu_acc_hh_s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyu_acc_hh_s1; //
"__builtin_HEXAGON_M2_mpyu_acc_hh_s1"
}
break; break;
return Intrinsic::hexagon_S2_lsl_r_r_acc; // "__built case 'l': // 2 strings to match.
in_HEXAGON.S2.lsl.r.r.acc" if (memcmp(BuiltinName.data()+32, "_s", 2))
case 'n': // 1 string to match. break;
if (BuiltinName[31] != 'd') switch (BuiltinName[34]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyu_acc_hl_s0; //
"__builtin_HEXAGON_M2_mpyu_acc_hl_s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyu_acc_hl_s1; //
"__builtin_HEXAGON_M2_mpyu_acc_hl_s1"
}
break; break;
return Intrinsic::hexagon_S2_lsl_r_r_and; // "__built }
in_HEXAGON.S2.lsl.r.r.and"
}
break;
case 'n': // 1 string to match.
if (BuiltinName.substr(30, 2) != "ac")
break;
return Intrinsic::hexagon_S2_lsl_r_r_nac; // "__built
in_HEXAGON.S2.lsl.r.r.nac"
}
break;
}
break;
case 'r': // 12 strings to match.
if (BuiltinName[24] != '.')
break;
switch (BuiltinName[25]) {
default: break;
case 'i': // 6 strings to match.
if (BuiltinName[26] != '.')
break;
switch (BuiltinName[27]) {
default: break;
case 'p': // 3 strings to match.
if (BuiltinName[28] != '.')
break; break;
switch (BuiltinName[29]) { case 'l': // 4 strings to match.
default: break; switch (BuiltinName[31]) {
case 'a': // 2 strings to match.
switch (BuiltinName[30]) {
default: break; default: break;
case 'c': // 1 string to match. case 'h': // 2 strings to match.
if (BuiltinName[31] != 'c') if (memcmp(BuiltinName.data()+32, "_s", 2))
break; break;
return Intrinsic::hexagon_S2_lsr_i_p_acc; // "__built switch (BuiltinName[34]) {
in_HEXAGON.S2.lsr.i.p.acc" default: break;
case 'n': // 1 string to match. case '0': // 1 string to match.
if (BuiltinName[31] != 'd') return Intrinsic::hexagon_M2_mpyu_acc_lh_s0; //
"__builtin_HEXAGON_M2_mpyu_acc_lh_s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyu_acc_lh_s1; //
"__builtin_HEXAGON_M2_mpyu_acc_lh_s1"
}
break;
case 'l': // 2 strings to match.
if (memcmp(BuiltinName.data()+32, "_s", 2))
break; break;
return Intrinsic::hexagon_S2_lsr_i_p_and; // "__built switch (BuiltinName[34]) {
in_HEXAGON.S2.lsr.i.p.and" default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyu_acc_ll_s0; //
"__builtin_HEXAGON_M2_mpyu_acc_ll_s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyu_acc_ll_s1; //
"__builtin_HEXAGON_M2_mpyu_acc_ll_s1"
}
break;
} }
break; break;
case 'n': // 1 string to match.
if (BuiltinName.substr(30, 2) != "ac")
break;
return Intrinsic::hexagon_S2_lsr_i_p_nac; // "__built
in_HEXAGON.S2.lsr.i.p.nac"
} }
break; break;
case 'r': // 3 strings to match. case 'n': // 8 strings to match.
if (BuiltinName[28] != '.') if (memcmp(BuiltinName.data()+27, "ac_", 3))
break; break;
switch (BuiltinName[29]) { switch (BuiltinName[30]) {
default: break; default: break;
case 'a': // 2 strings to match. case 'h': // 4 strings to match.
switch (BuiltinName[30]) { switch (BuiltinName[31]) {
default: break; default: break;
case 'c': // 1 string to match. case 'h': // 2 strings to match.
if (BuiltinName[31] != 'c') if (memcmp(BuiltinName.data()+32, "_s", 2))
break; break;
return Intrinsic::hexagon_S2_lsr_i_r_acc; // "__built switch (BuiltinName[34]) {
in_HEXAGON.S2.lsr.i.r.acc" default: break;
case 'n': // 1 string to match. case '0': // 1 string to match.
if (BuiltinName[31] != 'd') return Intrinsic::hexagon_M2_mpyu_nac_hh_s0; //
"__builtin_HEXAGON_M2_mpyu_nac_hh_s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyu_nac_hh_s1; //
"__builtin_HEXAGON_M2_mpyu_nac_hh_s1"
}
break;
case 'l': // 2 strings to match.
if (memcmp(BuiltinName.data()+32, "_s", 2))
break; break;
return Intrinsic::hexagon_S2_lsr_i_r_and; // "__built switch (BuiltinName[34]) {
in_HEXAGON.S2.lsr.i.r.and" default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyu_nac_hl_s0; //
"__builtin_HEXAGON_M2_mpyu_nac_hl_s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyu_nac_hl_s1; //
"__builtin_HEXAGON_M2_mpyu_nac_hl_s1"
}
break;
} }
break; break;
case 'n': // 1 string to match. case 'l': // 4 strings to match.
if (BuiltinName.substr(30, 2) != "ac") switch (BuiltinName[31]) {
default: break;
case 'h': // 2 strings to match.
if (memcmp(BuiltinName.data()+32, "_s", 2))
break;
switch (BuiltinName[34]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyu_nac_lh_s0; //
"__builtin_HEXAGON_M2_mpyu_nac_lh_s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyu_nac_lh_s1; //
"__builtin_HEXAGON_M2_mpyu_nac_lh_s1"
}
break;
case 'l': // 2 strings to match.
if (memcmp(BuiltinName.data()+32, "_s", 2))
break;
switch (BuiltinName[34]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyu_nac_ll_s0; //
"__builtin_HEXAGON_M2_mpyu_nac_ll_s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyu_nac_ll_s1; //
"__builtin_HEXAGON_M2_mpyu_nac_ll_s1"
}
break; break;
return Intrinsic::hexagon_S2_lsr_i_r_nac; // "__built }
in_HEXAGON.S2.lsr.i.r.nac" break;
} }
break; break;
} }
break; break;
case 'r': // 6 strings to match. }
if (BuiltinName[26] != '.') break;
case 'v': // 7 strings to match.
switch (BuiltinName[22]) {
default: break;
case 'c': // 6 strings to match.
if (BuiltinName[23] != 'm')
break; break;
switch (BuiltinName[27]) { switch (BuiltinName[24]) {
default: break; default: break;
case 'p': // 3 strings to match. case 'a': // 2 strings to match.
if (BuiltinName[28] != '.') if (memcmp(BuiltinName.data()+25, "c_s0_sat_", 9))
break; break;
switch (BuiltinName[29]) { switch (BuiltinName[34]) {
default: break; default: break;
case 'a': // 2 strings to match. case 'i': // 1 string to match.
switch (BuiltinName[30]) { return Intrinsic::hexagon_M2_vcmac_s0_sat_i; // "__built
default: break; in_HEXAGON_M2_vcmac_s0_sat_i"
case 'c': // 1 string to match. case 'r': // 1 string to match.
if (BuiltinName[31] != 'c') return Intrinsic::hexagon_M2_vcmac_s0_sat_r; // "__built
break; in_HEXAGON_M2_vcmac_s0_sat_r"
return Intrinsic::hexagon_S2_lsr_r_p_acc; // "__built
in_HEXAGON.S2.lsr.r.p.acc"
case 'n': // 1 string to match.
if (BuiltinName[31] != 'd')
break;
return Intrinsic::hexagon_S2_lsr_r_p_and; // "__built
in_HEXAGON.S2.lsr.r.p.and"
}
break;
case 'n': // 1 string to match.
if (BuiltinName.substr(30, 2) != "ac")
break;
return Intrinsic::hexagon_S2_lsr_r_p_nac; // "__built
in_HEXAGON.S2.lsr.r.p.nac"
} }
break; break;
case 'r': // 3 strings to match. case 'p': // 4 strings to match.
if (BuiltinName[28] != '.') if (memcmp(BuiltinName.data()+25, "y_s", 3))
break; break;
switch (BuiltinName[29]) { switch (BuiltinName[28]) {
default: break; default: break;
case 'a': // 2 strings to match. case '0': // 2 strings to match.
switch (BuiltinName[30]) { if (memcmp(BuiltinName.data()+29, "_sat_", 5))
break;
switch (BuiltinName[34]) {
default: break; default: break;
case 'c': // 1 string to match. case 'i': // 1 string to match.
if (BuiltinName[31] != 'c') return Intrinsic::hexagon_M2_vcmpy_s0_sat_i; // "__built
break; in_HEXAGON_M2_vcmpy_s0_sat_i"
return Intrinsic::hexagon_S2_lsr_r_r_acc; // "__built case 'r': // 1 string to match.
in_HEXAGON.S2.lsr.r.r.acc" return Intrinsic::hexagon_M2_vcmpy_s0_sat_r; // "__built
case 'n': // 1 string to match. in_HEXAGON_M2_vcmpy_s0_sat_r"
if (BuiltinName[31] != 'd')
break;
return Intrinsic::hexagon_S2_lsr_r_r_and; // "__built
in_HEXAGON.S2.lsr.r.r.and"
} }
break; break;
case 'n': // 1 string to match. case '1': // 2 strings to match.
if (BuiltinName.substr(30, 2) != "ac") if (memcmp(BuiltinName.data()+29, "_sat_", 5))
break; break;
return Intrinsic::hexagon_S2_lsr_r_r_nac; // "__built switch (BuiltinName[34]) {
in_HEXAGON.S2.lsr.r.r.nac" default: break;
case 'i': // 1 string to match.
return Intrinsic::hexagon_M2_vcmpy_s1_sat_i; // "__built
in_HEXAGON_M2_vcmpy_s1_sat_i"
case 'r': // 1 string to match.
return Intrinsic::hexagon_M2_vcmpy_s1_sat_r; // "__built
in_HEXAGON_M2_vcmpy_s1_sat_r"
}
break;
} }
break; break;
} }
break; break;
case 'r': // 1 string to match.
if (memcmp(BuiltinName.data()+23, "cmpys_acc_s1", 12))
break;
return Intrinsic::hexagon_M2_vrcmpys_acc_s1; // "__built
in_HEXAGON_M2_vrcmpys_acc_s1"
} }
break; break;
} }
break; break;
case 't': // 2 strings to match. case '4': // 4 strings to match.
if (BuiltinName.substr(22, 9) != "ogglebit.") if (memcmp(BuiltinName.data()+20, "_vrmpy", 6))
break; break;
switch (BuiltinName[31]) { switch (BuiltinName[26]) {
default: break;
case 'e': // 2 strings to match.
if (memcmp(BuiltinName.data()+27, "h_acc_s", 7))
break;
switch (BuiltinName[34]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M4_vrmpyeh_acc_s0; // "__built
in_HEXAGON_M4_vrmpyeh_acc_s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M4_vrmpyeh_acc_s1; // "__built
in_HEXAGON_M4_vrmpyeh_acc_s1"
}
break;
case 'o': // 2 strings to match.
if (memcmp(BuiltinName.data()+27, "h_acc_s", 7))
break;
switch (BuiltinName[34]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M4_vrmpyoh_acc_s0; // "__built
in_HEXAGON_M4_vrmpyoh_acc_s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M4_vrmpyoh_acc_s1; // "__built
in_HEXAGON_M4_vrmpyoh_acc_s1"
}
break;
}
break;
}
break;
case 'S': // 4 strings to match.
if (memcmp(BuiltinName.data()+19, "2_", 2))
break;
switch (BuiltinName[21]) {
default: break;
case 'a': // 2 strings to match.
if (memcmp(BuiltinName.data()+22, "sr_", 3))
break;
switch (BuiltinName[25]) {
default: break; default: break;
case 'i': // 1 string to match. case 'i': // 1 string to match.
return Intrinsic::hexagon_S2_togglebit_i; // "__builtin_HEXAG if (memcmp(BuiltinName.data()+26, "_svw_trun", 9))
ON.S2.togglebit.i" break;
return Intrinsic::hexagon_S2_asr_i_svw_trun; // "__builtin_HEXAG
ON_S2_asr_i_svw_trun"
case 'r': // 1 string to match. case 'r': // 1 string to match.
return Intrinsic::hexagon_S2_togglebit_r; // "__builtin_HEXAG if (memcmp(BuiltinName.data()+26, "_svw_trun", 9))
ON.S2.togglebit.r" break;
return Intrinsic::hexagon_S2_asr_r_svw_trun; // "__builtin_HEXAG
ON_S2_asr_r_svw_trun"
} }
break; break;
case 'v': // 1 string to match. case 'v': // 2 strings to match.
if (BuiltinName.substr(22, 10) != "rndpackwhs") if (memcmp(BuiltinName.data()+22, "sat", 3))
break; break;
return Intrinsic::hexagon_S2_vrndpackwhs; // "__builtin_HEXAG switch (BuiltinName[25]) {
ON.S2.vrndpackwhs" default: break;
case 'h': // 1 string to match.
if (memcmp(BuiltinName.data()+26, "ub_nopack", 9))
break;
return Intrinsic::hexagon_S2_vsathub_nopack; // "__builtin_HEXAG
ON_S2_vsathub_nopack"
case 'w': // 1 string to match.
if (memcmp(BuiltinName.data()+26, "uh_nopack", 9))
break;
return Intrinsic::hexagon_S2_vsatwuh_nopack; // "__builtin_HEXAG
ON_S2_vsatwuh_nopack"
}
break;
} }
break; break;
} }
break; break;
case 33: // 9 strings to match. case 36: // 33 strings to match.
if (BuiltinName.substr(0, 18) != "__builtin_HEXAGON.") if (memcmp(BuiltinName.data()+0, "__builtin_HEXAGON_", 18))
break; break;
switch (BuiltinName[18]) { switch (BuiltinName[18]) {
default: break; default: break;
case 'A': // 2 strings to match. case 'A': // 12 strings to match.
if (BuiltinName.substr(19, 9) != "4.round_r") if (memcmp(BuiltinName.data()+19, "2_", 2))
break; break;
switch (BuiltinName[28]) { switch (BuiltinName[21]) {
default: break; default: break;
case 'i': // 1 string to match. case 'a': // 6 strings to match.
if (BuiltinName.substr(29, 4) != "_sat") if (memcmp(BuiltinName.data()+22, "ddh_", 4))
break; break;
return Intrinsic::hexagon_A4_round_ri_sat; // "__builtin_HEXAG switch (BuiltinName[26]) {
ON.A4.round_ri_sat" default: break;
case 'r': // 1 string to match. case 'h': // 4 strings to match.
if (BuiltinName.substr(29, 4) != "_sat") if (memcmp(BuiltinName.data()+27, "16_sat_", 7))
break;
switch (BuiltinName[34]) {
default: break;
case 'h': // 2 strings to match.
switch (BuiltinName[35]) {
default: break;
case 'h': // 1 string to match.
return Intrinsic::hexagon_A2_addh_h16_sat_hh; // "__built
in_HEXAGON_A2_addh_h16_sat_hh"
case 'l': // 1 string to match.
return Intrinsic::hexagon_A2_addh_h16_sat_hl; // "__built
in_HEXAGON_A2_addh_h16_sat_hl"
}
break;
case 'l': // 2 strings to match.
switch (BuiltinName[35]) {
default: break;
case 'h': // 1 string to match.
return Intrinsic::hexagon_A2_addh_h16_sat_lh; // "__built
in_HEXAGON_A2_addh_h16_sat_lh"
case 'l': // 1 string to match.
return Intrinsic::hexagon_A2_addh_h16_sat_ll; // "__built
in_HEXAGON_A2_addh_h16_sat_ll"
}
break;
}
break;
case 'l': // 2 strings to match.
if (memcmp(BuiltinName.data()+27, "16_sat_", 7))
break;
switch (BuiltinName[34]) {
default: break;
case 'h': // 1 string to match.
if (BuiltinName[35] != 'l')
break;
return Intrinsic::hexagon_A2_addh_l16_sat_hl; // "__built
in_HEXAGON_A2_addh_l16_sat_hl"
case 'l': // 1 string to match.
if (BuiltinName[35] != 'l')
break;
return Intrinsic::hexagon_A2_addh_l16_sat_ll; // "__built
in_HEXAGON_A2_addh_l16_sat_ll"
}
break;
}
break;
case 's': // 6 strings to match.
if (memcmp(BuiltinName.data()+22, "ubh_", 4))
break;
switch (BuiltinName[26]) {
default: break;
case 'h': // 4 strings to match.
if (memcmp(BuiltinName.data()+27, "16_sat_", 7))
break;
switch (BuiltinName[34]) {
default: break;
case 'h': // 2 strings to match.
switch (BuiltinName[35]) {
default: break;
case 'h': // 1 string to match.
return Intrinsic::hexagon_A2_subh_h16_sat_hh; // "__built
in_HEXAGON_A2_subh_h16_sat_hh"
case 'l': // 1 string to match.
return Intrinsic::hexagon_A2_subh_h16_sat_hl; // "__built
in_HEXAGON_A2_subh_h16_sat_hl"
}
break;
case 'l': // 2 strings to match.
switch (BuiltinName[35]) {
default: break;
case 'h': // 1 string to match.
return Intrinsic::hexagon_A2_subh_h16_sat_lh; // "__built
in_HEXAGON_A2_subh_h16_sat_lh"
case 'l': // 1 string to match.
return Intrinsic::hexagon_A2_subh_h16_sat_ll; // "__built
in_HEXAGON_A2_subh_h16_sat_ll"
}
break;
}
break;
case 'l': // 2 strings to match.
if (memcmp(BuiltinName.data()+27, "16_sat_", 7))
break;
switch (BuiltinName[34]) {
default: break;
case 'h': // 1 string to match.
if (BuiltinName[35] != 'l')
break;
return Intrinsic::hexagon_A2_subh_l16_sat_hl; // "__built
in_HEXAGON_A2_subh_l16_sat_hl"
case 'l': // 1 string to match.
if (BuiltinName[35] != 'l')
break;
return Intrinsic::hexagon_A2_subh_l16_sat_ll; // "__built
in_HEXAGON_A2_subh_l16_sat_ll"
}
break; break;
return Intrinsic::hexagon_A4_round_rr_sat; // "__builtin_HEXAG }
ON.A4.round_rr_sat" break;
} }
break; break;
case 'M': // 1 string to match. case 'C': // 1 string to match.
if (BuiltinName.substr(19, 14) != "2.vrcmpys.s1rp") if (memcmp(BuiltinName.data()+19, "4_fastcorner9_not", 17))
break; break;
return Intrinsic::hexagon_M2_vrcmpys_s1rp; // "__builtin_HEXAG return Intrinsic::hexagon_C4_fastcorner9_not; // "__builtin_HEXAG
ON.M2.vrcmpys.s1rp" ON_C4_fastcorner9_not"
case 'S': // 6 strings to match. case 'F': // 4 strings to match.
if (BuiltinName.substr(19, 2) != "2.") if (memcmp(BuiltinName.data()+19, "2_conv_", 7))
break; break;
switch (BuiltinName[21]) { switch (BuiltinName[26]) {
default: break; default: break;
case 'a': // 2 strings to match. case 'd': // 2 strings to match.
if (BuiltinName.substr(22, 5) != "sl.i.") if (memcmp(BuiltinName.data()+27, "f2u", 3))
break; break;
switch (BuiltinName[27]) { switch (BuiltinName[30]) {
default: break; default: break;
case 'p': // 1 string to match. case 'd': // 1 string to match.
if (BuiltinName.substr(28, 5) != ".xacc") if (memcmp(BuiltinName.data()+31, "_chop", 5))
break; break;
return Intrinsic::hexagon_S2_asl_i_p_xacc; // "__builtin_HEXAG return Intrinsic::hexagon_F2_conv_df2ud_chop; // "__built
ON.S2.asl.i.p.xacc" in_HEXAGON_F2_conv_df2ud_chop"
case 'r': // 1 string to match. case 'w': // 1 string to match.
if (BuiltinName.substr(28, 5) != ".xacc") if (memcmp(BuiltinName.data()+31, "_chop", 5))
break; break;
return Intrinsic::hexagon_S2_asl_i_r_xacc; // "__builtin_HEXAG ON.S2.asl.i.r.xacc" return Intrinsic::hexagon_F2_conv_df2uw_chop; // "__built in_HEXAGON_F2_conv_df2uw_chop"
} }
break; break;
case 'd': // 1 string to match. case 's': // 2 strings to match.
if (BuiltinName.substr(22, 11) != "einterleave") if (memcmp(BuiltinName.data()+27, "f2u", 3))
break; break;
return Intrinsic::hexagon_S2_deinterleave; // "__builtin_HEXAG switch (BuiltinName[30]) {
ON.S2.deinterleave" default: break;
case 'e': // 1 string to match. case 'd': // 1 string to match.
if (BuiltinName.substr(22, 11) != "xtractup.rp") if (memcmp(BuiltinName.data()+31, "_chop", 5))
break;
return Intrinsic::hexagon_F2_conv_sf2ud_chop; // "__built
in_HEXAGON_F2_conv_sf2ud_chop"
case 'w': // 1 string to match.
if (memcmp(BuiltinName.data()+31, "_chop", 5))
break;
return Intrinsic::hexagon_F2_conv_sf2uw_chop; // "__built
in_HEXAGON_F2_conv_sf2uw_chop"
}
break;
}
break;
case 'M': // 16 strings to match.
if (memcmp(BuiltinName.data()+19, "2_mpyud_", 8))
break;
switch (BuiltinName[27]) {
default: break;
case 'a': // 8 strings to match.
if (memcmp(BuiltinName.data()+28, "cc_", 3))
break; break;
return Intrinsic::hexagon_S2_extractup_rp; // "__builtin_HEXAG switch (BuiltinName[31]) {
ON.S2.extractup.rp" default: break;
case 'l': // 2 strings to match. case 'h': // 4 strings to match.
if (BuiltinName.substr(22, 5) != "sr.i.") switch (BuiltinName[32]) {
default: break;
case 'h': // 2 strings to match.
if (memcmp(BuiltinName.data()+33, "_s", 2))
break;
switch (BuiltinName[35]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyud_acc_hh_s0; // "__built
in_HEXAGON_M2_mpyud_acc_hh_s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyud_acc_hh_s1; // "__built
in_HEXAGON_M2_mpyud_acc_hh_s1"
}
break;
case 'l': // 2 strings to match.
if (memcmp(BuiltinName.data()+33, "_s", 2))
break;
switch (BuiltinName[35]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyud_acc_hl_s0; // "__built
in_HEXAGON_M2_mpyud_acc_hl_s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyud_acc_hl_s1; // "__built
in_HEXAGON_M2_mpyud_acc_hl_s1"
}
break;
}
break; break;
switch (BuiltinName[27]) { case 'l': // 4 strings to match.
switch (BuiltinName[32]) {
default: break;
case 'h': // 2 strings to match.
if (memcmp(BuiltinName.data()+33, "_s", 2))
break;
switch (BuiltinName[35]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyud_acc_lh_s0; // "__built
in_HEXAGON_M2_mpyud_acc_lh_s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyud_acc_lh_s1; // "__built
in_HEXAGON_M2_mpyud_acc_lh_s1"
}
break;
case 'l': // 2 strings to match.
if (memcmp(BuiltinName.data()+33, "_s", 2))
break;
switch (BuiltinName[35]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyud_acc_ll_s0; // "__built
in_HEXAGON_M2_mpyud_acc_ll_s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyud_acc_ll_s1; // "__built
in_HEXAGON_M2_mpyud_acc_ll_s1"
}
break;
}
break;
}
break;
case 'n': // 8 strings to match.
if (memcmp(BuiltinName.data()+28, "ac_", 3))
break;
switch (BuiltinName[31]) {
default: break; default: break;
case 'p': // 1 string to match. case 'h': // 4 strings to match.
if (BuiltinName.substr(28, 5) != ".xacc") switch (BuiltinName[32]) {
default: break;
case 'h': // 2 strings to match.
if (memcmp(BuiltinName.data()+33, "_s", 2))
break;
switch (BuiltinName[35]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyud_nac_hh_s0; // "__built
in_HEXAGON_M2_mpyud_nac_hh_s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyud_nac_hh_s1; // "__built
in_HEXAGON_M2_mpyud_nac_hh_s1"
}
break;
case 'l': // 2 strings to match.
if (memcmp(BuiltinName.data()+33, "_s", 2))
break;
switch (BuiltinName[35]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyud_nac_hl_s0; // "__built
in_HEXAGON_M2_mpyud_nac_hl_s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyud_nac_hl_s1; // "__built
in_HEXAGON_M2_mpyud_nac_hl_s1"
}
break;
}
break;
case 'l': // 4 strings to match.
switch (BuiltinName[32]) {
default: break;
case 'h': // 2 strings to match.
if (memcmp(BuiltinName.data()+33, "_s", 2))
break;
switch (BuiltinName[35]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyud_nac_lh_s0; // "__built
in_HEXAGON_M2_mpyud_nac_lh_s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyud_nac_lh_s1; // "__built
in_HEXAGON_M2_mpyud_nac_lh_s1"
}
break; break;
return Intrinsic::hexagon_S2_lsr_i_p_xacc; // "__builtin_HEXAG case 'l': // 2 strings to match.
ON.S2.lsr.i.p.xacc" if (memcmp(BuiltinName.data()+33, "_s", 2))
case 'r': // 1 string to match. break;
if (BuiltinName.substr(28, 5) != ".xacc") switch (BuiltinName[35]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyud_nac_ll_s0; // "__built
in_HEXAGON_M2_mpyud_nac_ll_s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyud_nac_ll_s1; // "__built
in_HEXAGON_M2_mpyud_nac_ll_s1"
}
break; break;
return Intrinsic::hexagon_S2_lsr_i_r_xacc; // "__builtin_HEXAG }
ON.S2.lsr.i.r.xacc" break;
} }
break; break;
} }
break; break;
} }
break; break;
case 34: // 36 strings to match. case 38: // 24 strings to match.
if (BuiltinName.substr(0, 18) != "__builtin_HEXAGON.") if (memcmp(BuiltinName.data()+0, "__builtin_HEXAGON_M2_mpy_", 25))
break; break;
switch (BuiltinName[18]) { switch (BuiltinName[25]) {
default: break; default: break;
case 'M': // 34 strings to match. case 'a': // 8 strings to match.
if (BuiltinName.substr(19, 2) != "2.") if (memcmp(BuiltinName.data()+26, "cc_sat_", 7))
break; break;
switch (BuiltinName[21]) { switch (BuiltinName[33]) {
default: break; default: break;
case 'm': // 32 strings to match. case 'h': // 4 strings to match.
if (BuiltinName.substr(22, 3) != "py.") switch (BuiltinName[34]) {
break;
switch (BuiltinName[25]) {
default: break; default: break;
case 'a': // 8 strings to match. case 'h': // 2 strings to match.
if (BuiltinName.substr(26, 3) != "cc.") if (memcmp(BuiltinName.data()+35, "_s", 2))
break; break;
switch (BuiltinName[29]) { switch (BuiltinName[37]) {
default: break; default: break;
case 'h': // 4 strings to match. case '0': // 1 string to match.
switch (BuiltinName[30]) { return Intrinsic::hexagon_M2_mpy_acc_sat_hh_s0; // "__built
default: break; in_HEXAGON_M2_mpy_acc_sat_hh_s0"
case 'h': // 2 strings to match. case '1': // 1 string to match.
if (BuiltinName.substr(31, 2) != ".s") return Intrinsic::hexagon_M2_mpy_acc_sat_hh_s1; // "__built
break; in_HEXAGON_M2_mpy_acc_sat_hh_s1"
switch (BuiltinName[33]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_acc_hh_s0; // "__built
in_HEXAGON.M2.mpy.acc.hh.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_acc_hh_s1; // "__built
in_HEXAGON.M2.mpy.acc.hh.s1"
}
break;
case 'l': // 2 strings to match.
if (BuiltinName.substr(31, 2) != ".s")
break;
switch (BuiltinName[33]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_acc_hl_s0; // "__built
in_HEXAGON.M2.mpy.acc.hl.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_acc_hl_s1; // "__built
in_HEXAGON.M2.mpy.acc.hl.s1"
}
break;
}
break;
case 'l': // 4 strings to match.
switch (BuiltinName[30]) {
default: break;
case 'h': // 2 strings to match.
if (BuiltinName.substr(31, 2) != ".s")
break;
switch (BuiltinName[33]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_acc_lh_s0; // "__built
in_HEXAGON.M2.mpy.acc.lh.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_acc_lh_s1; // "__built
in_HEXAGON.M2.mpy.acc.lh.s1"
}
break;
case 'l': // 2 strings to match.
if (BuiltinName.substr(31, 2) != ".s")
break;
switch (BuiltinName[33]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_acc_ll_s0; // "__built
in_HEXAGON.M2.mpy.acc.ll.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_acc_ll_s1; // "__built
in_HEXAGON.M2.mpy.acc.ll.s1"
}
break;
}
break;
} }
break; break;
case 'n': // 8 strings to match. case 'l': // 2 strings to match.
if (BuiltinName.substr(26, 3) != "ac.") if (memcmp(BuiltinName.data()+35, "_s", 2))
break; break;
switch (BuiltinName[29]) { switch (BuiltinName[37]) {
default: break; default: break;
case 'h': // 4 strings to match. case '0': // 1 string to match.
switch (BuiltinName[30]) { return Intrinsic::hexagon_M2_mpy_acc_sat_hl_s0; // "__built
default: break; in_HEXAGON_M2_mpy_acc_sat_hl_s0"
case 'h': // 2 strings to match. case '1': // 1 string to match.
if (BuiltinName.substr(31, 2) != ".s") return Intrinsic::hexagon_M2_mpy_acc_sat_hl_s1; // "__built
break; in_HEXAGON_M2_mpy_acc_sat_hl_s1"
switch (BuiltinName[33]) { }
default: break; break;
case '0': // 1 string to match. }
return Intrinsic::hexagon_M2_mpy_nac_hh_s0; // "__built break;
in_HEXAGON.M2.mpy.nac.hh.s0" case 'l': // 4 strings to match.
case '1': // 1 string to match. switch (BuiltinName[34]) {
return Intrinsic::hexagon_M2_mpy_nac_hh_s1; // "__built default: break;
in_HEXAGON.M2.mpy.nac.hh.s1" case 'h': // 2 strings to match.
} if (memcmp(BuiltinName.data()+35, "_s", 2))
break;
case 'l': // 2 strings to match.
if (BuiltinName.substr(31, 2) != ".s")
break;
switch (BuiltinName[33]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_nac_hl_s0; // "__built
in_HEXAGON.M2.mpy.nac.hl.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_nac_hl_s1; // "__built
in_HEXAGON.M2.mpy.nac.hl.s1"
}
break;
}
break; break;
case 'l': // 4 strings to match. switch (BuiltinName[37]) {
switch (BuiltinName[30]) { default: break;
default: break; case '0': // 1 string to match.
case 'h': // 2 strings to match. return Intrinsic::hexagon_M2_mpy_acc_sat_lh_s0; // "__built
if (BuiltinName.substr(31, 2) != ".s") in_HEXAGON_M2_mpy_acc_sat_lh_s0"
break; case '1': // 1 string to match.
switch (BuiltinName[33]) { return Intrinsic::hexagon_M2_mpy_acc_sat_lh_s1; // "__built
default: break; in_HEXAGON_M2_mpy_acc_sat_lh_s1"
case '0': // 1 string to match. }
return Intrinsic::hexagon_M2_mpy_nac_lh_s0; // "__built break;
in_HEXAGON.M2.mpy.nac.lh.s0" case 'l': // 2 strings to match.
case '1': // 1 string to match. if (memcmp(BuiltinName.data()+35, "_s", 2))
return Intrinsic::hexagon_M2_mpy_nac_lh_s1; // "__built
in_HEXAGON.M2.mpy.nac.lh.s1"
}
break;
case 'l': // 2 strings to match.
if (BuiltinName.substr(31, 2) != ".s")
break;
switch (BuiltinName[33]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_nac_ll_s0; // "__built
in_HEXAGON.M2.mpy.nac.ll.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_nac_ll_s1; // "__built
in_HEXAGON.M2.mpy.nac.ll.s1"
}
break;
}
break; break;
switch (BuiltinName[37]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_acc_sat_ll_s0; // "__built
in_HEXAGON_M2_mpy_acc_sat_ll_s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_acc_sat_ll_s1; // "__built
in_HEXAGON_M2_mpy_acc_sat_ll_s1"
} }
break; break;
case 'r': // 8 strings to match. }
if (BuiltinName.substr(26, 3) != "nd.") break;
}
break;
case 'n': // 8 strings to match.
if (memcmp(BuiltinName.data()+26, "ac_sat_", 7))
break;
switch (BuiltinName[33]) {
default: break;
case 'h': // 4 strings to match.
switch (BuiltinName[34]) {
default: break;
case 'h': // 2 strings to match.
if (memcmp(BuiltinName.data()+35, "_s", 2))
break; break;
switch (BuiltinName[29]) { switch (BuiltinName[37]) {
default: break; default: break;
case 'h': // 4 strings to match. case '0': // 1 string to match.
switch (BuiltinName[30]) { return Intrinsic::hexagon_M2_mpy_nac_sat_hh_s0; // "__built
default: break; in_HEXAGON_M2_mpy_nac_sat_hh_s0"
case 'h': // 2 strings to match. case '1': // 1 string to match.
if (BuiltinName.substr(31, 2) != ".s") return Intrinsic::hexagon_M2_mpy_nac_sat_hh_s1; // "__built
break; in_HEXAGON_M2_mpy_nac_sat_hh_s1"
switch (BuiltinName[33]) { }
default: break; break;
case '0': // 1 string to match. case 'l': // 2 strings to match.
return Intrinsic::hexagon_M2_mpy_rnd_hh_s0; // "__built if (memcmp(BuiltinName.data()+35, "_s", 2))
in_HEXAGON.M2.mpy.rnd.hh.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_rnd_hh_s1; // "__built
in_HEXAGON.M2.mpy.rnd.hh.s1"
}
break;
case 'l': // 2 strings to match.
if (BuiltinName.substr(31, 2) != ".s")
break;
switch (BuiltinName[33]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_rnd_hl_s0; // "__built
in_HEXAGON.M2.mpy.rnd.hl.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_rnd_hl_s1; // "__built
in_HEXAGON.M2.mpy.rnd.hl.s1"
}
break;
}
break; break;
case 'l': // 4 strings to match. switch (BuiltinName[37]) {
switch (BuiltinName[30]) { default: break;
default: break; case '0': // 1 string to match.
case 'h': // 2 strings to match. return Intrinsic::hexagon_M2_mpy_nac_sat_hl_s0; // "__built
if (BuiltinName.substr(31, 2) != ".s") in_HEXAGON_M2_mpy_nac_sat_hl_s0"
break; case '1': // 1 string to match.
switch (BuiltinName[33]) { return Intrinsic::hexagon_M2_mpy_nac_sat_hl_s1; // "__built
default: break; in_HEXAGON_M2_mpy_nac_sat_hl_s1"
case '0': // 1 string to match. }
return Intrinsic::hexagon_M2_mpy_rnd_lh_s0; // "__built break;
in_HEXAGON.M2.mpy.rnd.lh.s0" }
case '1': // 1 string to match. break;
return Intrinsic::hexagon_M2_mpy_rnd_lh_s1; // "__built case 'l': // 4 strings to match.
in_HEXAGON.M2.mpy.rnd.lh.s1" switch (BuiltinName[34]) {
} default: break;
break; case 'h': // 2 strings to match.
case 'l': // 2 strings to match. if (memcmp(BuiltinName.data()+35, "_s", 2))
if (BuiltinName.substr(31, 2) != ".s")
break;
switch (BuiltinName[33]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_rnd_ll_s0; // "__built
in_HEXAGON.M2.mpy.rnd.ll.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_rnd_ll_s1; // "__built
in_HEXAGON.M2.mpy.rnd.ll.s1"
}
break;
}
break; break;
switch (BuiltinName[37]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_nac_sat_lh_s0; // "__built
in_HEXAGON_M2_mpy_nac_sat_lh_s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_nac_sat_lh_s1; // "__built
in_HEXAGON_M2_mpy_nac_sat_lh_s1"
} }
break; break;
case 's': // 8 strings to match. case 'l': // 2 strings to match.
if (BuiltinName.substr(26, 3) != "at.") if (memcmp(BuiltinName.data()+35, "_s", 2))
break; break;
switch (BuiltinName[29]) { switch (BuiltinName[37]) {
default: break; default: break;
case 'h': // 4 strings to match. case '0': // 1 string to match.
switch (BuiltinName[30]) { return Intrinsic::hexagon_M2_mpy_nac_sat_ll_s0; // "__built
default: break; in_HEXAGON_M2_mpy_nac_sat_ll_s0"
case 'h': // 2 strings to match. case '1': // 1 string to match.
if (BuiltinName.substr(31, 2) != ".s") return Intrinsic::hexagon_M2_mpy_nac_sat_ll_s1; // "__built
break; in_HEXAGON_M2_mpy_nac_sat_ll_s1"
switch (BuiltinName[33]) { }
default: break; break;
case '0': // 1 string to match. }
return Intrinsic::hexagon_M2_mpy_sat_hh_s0; // "__built break;
in_HEXAGON.M2.mpy.sat.hh.s0" }
case '1': // 1 string to match. break;
return Intrinsic::hexagon_M2_mpy_sat_hh_s1; // "__built case 's': // 8 strings to match.
in_HEXAGON.M2.mpy.sat.hh.s1" if (memcmp(BuiltinName.data()+26, "at_rnd_", 7))
} break;
break; switch (BuiltinName[33]) {
case 'l': // 2 strings to match. default: break;
if (BuiltinName.substr(31, 2) != ".s") case 'h': // 4 strings to match.
break; switch (BuiltinName[34]) {
switch (BuiltinName[33]) { default: break;
default: break; case 'h': // 2 strings to match.
case '0': // 1 string to match. if (memcmp(BuiltinName.data()+35, "_s", 2))
return Intrinsic::hexagon_M2_mpy_sat_hl_s0; // "__built
in_HEXAGON.M2.mpy.sat.hl.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_sat_hl_s1; // "__built
in_HEXAGON.M2.mpy.sat.hl.s1"
}
break;
}
break; break;
case 'l': // 4 strings to match. switch (BuiltinName[37]) {
switch (BuiltinName[30]) { default: break;
default: break; case '0': // 1 string to match.
case 'h': // 2 strings to match. return Intrinsic::hexagon_M2_mpy_sat_rnd_hh_s0; // "__built
if (BuiltinName.substr(31, 2) != ".s") in_HEXAGON_M2_mpy_sat_rnd_hh_s0"
break; case '1': // 1 string to match.
switch (BuiltinName[33]) { return Intrinsic::hexagon_M2_mpy_sat_rnd_hh_s1; // "__built
default: break; in_HEXAGON_M2_mpy_sat_rnd_hh_s1"
case '0': // 1 string to match. }
return Intrinsic::hexagon_M2_mpy_sat_lh_s0; // "__built break;
in_HEXAGON.M2.mpy.sat.lh.s0" case 'l': // 2 strings to match.
case '1': // 1 string to match. if (memcmp(BuiltinName.data()+35, "_s", 2))
return Intrinsic::hexagon_M2_mpy_sat_lh_s1; // "__built
in_HEXAGON.M2.mpy.sat.lh.s1"
}
break;
case 'l': // 2 strings to match.
if (BuiltinName.substr(31, 2) != ".s")
break;
switch (BuiltinName[33]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_sat_ll_s0; // "__built
in_HEXAGON.M2.mpy.sat.ll.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_sat_ll_s1; // "__built
in_HEXAGON.M2.mpy.sat.ll.s1"
}
break;
}
break; break;
switch (BuiltinName[37]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_sat_rnd_hl_s0; // "__built
in_HEXAGON_M2_mpy_sat_rnd_hl_s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_sat_rnd_hl_s1; // "__built
in_HEXAGON_M2_mpy_sat_rnd_hl_s1"
} }
break; break;
} }
break; break;
case 'v': // 2 strings to match. case 'l': // 4 strings to match.
if (BuiltinName.substr(22, 7) != "mpy2s.s") switch (BuiltinName[34]) {
break;
switch (BuiltinName[29]) {
default: break; default: break;
case '0': // 1 string to match. case 'h': // 2 strings to match.
if (BuiltinName.substr(30, 4) != "pack") if (memcmp(BuiltinName.data()+35, "_s", 2))
break; break;
return Intrinsic::hexagon_M2_vmpy2s_s0pack; // "__builtin_HEXAG switch (BuiltinName[37]) {
ON.M2.vmpy2s.s0pack" default: break;
case '1': // 1 string to match. case '0': // 1 string to match.
if (BuiltinName.substr(30, 4) != "pack") return Intrinsic::hexagon_M2_mpy_sat_rnd_lh_s0; // "__built
in_HEXAGON_M2_mpy_sat_rnd_lh_s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_sat_rnd_lh_s1; // "__built
in_HEXAGON_M2_mpy_sat_rnd_lh_s1"
}
break;
case 'l': // 2 strings to match.
if (memcmp(BuiltinName.data()+35, "_s", 2))
break; break;
return Intrinsic::hexagon_M2_vmpy2s_s1pack; // "__builtin_HEXAG switch (BuiltinName[37]) {
ON.M2.vmpy2s.s1pack" default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_sat_rnd_ll_s0; // "__built
in_HEXAGON_M2_mpy_sat_rnd_ll_s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_sat_rnd_ll_s1; // "__built
in_HEXAGON_M2_mpy_sat_rnd_ll_s1"
}
break;
} }
break; break;
} }
break; break;
case 'S': // 2 strings to match. }
if (BuiltinName.substr(19, 6) != "2.vsat") break;
case 40: // 1 string to match.
if (memcmp(BuiltinName.data()+0, "__builtin_HEXAGON_S5_vasrhrnd_goodsyn
tax", 40))
break;
return Intrinsic::hexagon_S5_vasrhrnd_goodsyntax; // "__builtin_HEXAG
ON_S5_vasrhrnd_goodsyntax"
case 41: // 4 strings to match.
if (memcmp(BuiltinName.data()+0, "__builtin_HEXAGON_S2_tableidx", 29))
break;
switch (BuiltinName[29]) {
default: break;
case 'b': // 1 string to match.
if (memcmp(BuiltinName.data()+30, "_goodsyntax", 11))
break; break;
switch (BuiltinName[25]) { return Intrinsic::hexagon_S2_tableidxb_goodsyntax; // "__built
in_HEXAGON_S2_tableidxb_goodsyntax"
case 'd': // 1 string to match.
if (memcmp(BuiltinName.data()+30, "_goodsyntax", 11))
break;
return Intrinsic::hexagon_S2_tableidxd_goodsyntax; // "__built
in_HEXAGON_S2_tableidxd_goodsyntax"
case 'h': // 1 string to match.
if (memcmp(BuiltinName.data()+30, "_goodsyntax", 11))
break;
return Intrinsic::hexagon_S2_tableidxh_goodsyntax; // "__built
in_HEXAGON_S2_tableidxh_goodsyntax"
case 'w': // 1 string to match.
if (memcmp(BuiltinName.data()+30, "_goodsyntax", 11))
break;
return Intrinsic::hexagon_S2_tableidxw_goodsyntax; // "__built
in_HEXAGON_S2_tableidxw_goodsyntax"
}
break;
case 43: // 2 strings to match.
if (memcmp(BuiltinName.data()+0, "__builtin_HEXAGON_S2_asr_i_", 27))
break;
switch (BuiltinName[27]) {
default: break;
case 'p': // 1 string to match.
if (memcmp(BuiltinName.data()+28, "_rnd_goodsyntax", 15))
break;
return Intrinsic::hexagon_S2_asr_i_p_rnd_goodsyntax; // "__built
in_HEXAGON_S2_asr_i_p_rnd_goodsyntax"
case 'r': // 1 string to match.
if (memcmp(BuiltinName.data()+28, "_rnd_goodsyntax", 15))
break;
return Intrinsic::hexagon_S2_asr_i_r_rnd_goodsyntax; // "__built
in_HEXAGON_S2_asr_i_r_rnd_goodsyntax"
}
break;
case 46: // 1 string to match.
if (memcmp(BuiltinName.data()+0, "__builtin_HEXAGON_S5_asrhub_rnd_sat_g
oodsyntax", 46))
break;
return Intrinsic::hexagon_S5_asrhub_rnd_sat_goodsyntax; // "__built
in_HEXAGON_S5_asrhub_rnd_sat_goodsyntax"
}
}
if (TargetPrefix == "mips") {
switch (BuiltinName.size()) {
default: break;
case 18: // 2 strings to match.
if (memcmp(BuiltinName.data()+0, "__builtin_mips_l", 16))
break;
switch (BuiltinName[16]) {
default: break;
case 'h': // 1 string to match.
if (BuiltinName[17] != 'x')
break;
return Intrinsic::mips_lhx; // "__builtin_mips_lhx"
case 'w': // 1 string to match.
if (BuiltinName[17] != 'x')
break;
return Intrinsic::mips_lwx; // "__builtin_mips_lwx"
}
break;
case 19: // 6 strings to match.
if (memcmp(BuiltinName.data()+0, "__builtin_mips_", 15))
break;
switch (BuiltinName[15]) {
default: break;
case 'e': // 1 string to match.
if (memcmp(BuiltinName.data()+16, "xtp", 3))
break;
return Intrinsic::mips_extp; // "__builtin_mips_extp"
case 'i': // 1 string to match.
if (memcmp(BuiltinName.data()+16, "nsv", 3))
break;
return Intrinsic::mips_insv; // "__builtin_mips_insv"
case 'l': // 1 string to match.
if (memcmp(BuiltinName.data()+16, "bux", 3))
break;
return Intrinsic::mips_lbux; // "__builtin_mips_lbux"
case 'm': // 3 strings to match.
switch (BuiltinName[16]) {
default: break; default: break;
case 'h': // 1 string to match. case 'a': // 1 string to match.
if (BuiltinName.substr(26, 8) != "b.nopack") if (memcmp(BuiltinName.data()+17, "dd", 2))
break;
return Intrinsic::mips_madd; // "__builtin_mips_madd"
case 's': // 1 string to match.
if (memcmp(BuiltinName.data()+17, "ub", 2))
break;
return Intrinsic::mips_msub; // "__builtin_mips_msub"
case 'u': // 1 string to match.
if (memcmp(BuiltinName.data()+17, "lt", 2))
break;
return Intrinsic::mips_mult; // "__builtin_mips_mult"
}
break;
}
break;
case 20: // 8 strings to match.
if (memcmp(BuiltinName.data()+0, "__builtin_mips_", 15))
break;
switch (BuiltinName[15]) {
default: break;
case 'a': // 2 strings to match.
if (memcmp(BuiltinName.data()+16, "dd", 2))
break;
switch (BuiltinName[18]) {
default: break;
case 's': // 1 string to match.
if (BuiltinName[19] != 'c')
break; break;
return Intrinsic::hexagon_S2_vsathb_nopack; // "__builtin_HEXAG ON.S2.vsathb.nopack" return Intrinsic::mips_addsc; // "__builtin_mips_addsc"
case 'w': // 1 string to match. case 'w': // 1 string to match.
if (BuiltinName.substr(26, 8) != "h.nopack") if (BuiltinName[19] != 'c')
break;
return Intrinsic::mips_addwc; // "__builtin_mips_addwc"
}
break;
case 'm': // 3 strings to match.
switch (BuiltinName[16]) {
default: break;
case 'a': // 1 string to match.
if (memcmp(BuiltinName.data()+17, "ddu", 3))
break;
return Intrinsic::mips_maddu; // "__builtin_mips_maddu"
case 's': // 1 string to match.
if (memcmp(BuiltinName.data()+17, "ubu", 3))
break;
return Intrinsic::mips_msubu; // "__builtin_mips_msubu"
case 'u': // 1 string to match.
if (memcmp(BuiltinName.data()+17, "ltu", 3))
break; break;
return Intrinsic::hexagon_S2_vsatwh_nopack; // "__builtin_HEXAG ON.S2.vsatwh.nopack" return Intrinsic::mips_multu; // "__builtin_mips_multu"
} }
break; break;
case 'r': // 1 string to match.
if (memcmp(BuiltinName.data()+16, "ddsp", 4))
break;
return Intrinsic::mips_rddsp; // "__builtin_mips_rddsp"
case 's': // 1 string to match.
if (memcmp(BuiltinName.data()+16, "hilo", 4))
break;
return Intrinsic::mips_shilo; // "__builtin_mips_shilo"
case 'w': // 1 string to match.
if (memcmp(BuiltinName.data()+16, "rdsp", 4))
break;
return Intrinsic::mips_wrdsp; // "__builtin_mips_wrdsp"
} }
break; break;
case 35: // 56 strings to match. case 21: // 8 strings to match.
if (BuiltinName.substr(0, 18) != "__builtin_HEXAGON.") if (memcmp(BuiltinName.data()+0, "__builtin_mips_", 15))
break; break;
switch (BuiltinName[18]) { switch (BuiltinName[15]) {
default: break; default: break;
case 'M': // 52 strings to match. case 'a': // 1 string to match.
if (BuiltinName.substr(19, 2) != "2.") if (memcmp(BuiltinName.data()+16, "ppend", 5))
break; break;
switch (BuiltinName[21]) { return Intrinsic::mips_append; // "__builtin_mips_append"
case 'b': // 2 strings to match.
switch (BuiltinName[16]) {
default: break; default: break;
case 'd': // 5 strings to match. case 'a': // 1 string to match.
if (BuiltinName.substr(22, 4) != "pmpy") if (memcmp(BuiltinName.data()+17, "lign", 4))
break; break;
switch (BuiltinName[26]) { return Intrinsic::mips_balign; // "__builtin_mips_balign"
case 'i': // 1 string to match.
if (memcmp(BuiltinName.data()+17, "trev", 4))
break;
return Intrinsic::mips_bitrev; // "__builtin_mips_bitrev"
}
break;
case 'e': // 2 strings to match.
if (memcmp(BuiltinName.data()+16, "xt", 2))
break;
switch (BuiltinName[18]) {
default: break;
case 'p': // 1 string to match.
if (memcmp(BuiltinName.data()+19, "dp", 2))
break;
return Intrinsic::mips_extpdp; // "__builtin_mips_extpdp"
case 'r': // 1 string to match.
if (memcmp(BuiltinName.data()+19, "_w", 2))
break;
return Intrinsic::mips_extr_w; // "__builtin_mips_extr_w"
}
break;
case 'm': // 3 strings to match.
switch (BuiltinName[16]) {
default: break;
case 'o': // 1 string to match.
if (memcmp(BuiltinName.data()+17, "dsub", 4))
break;
return Intrinsic::mips_modsub; // "__builtin_mips_modsub"
case 't': // 1 string to match.
if (memcmp(BuiltinName.data()+17, "hlip", 4))
break;
return Intrinsic::mips_mthlip; // "__builtin_mips_mthlip"
case 'u': // 1 string to match.
if (memcmp(BuiltinName.data()+17, "l_ph", 4))
break;
return Intrinsic::mips_mul_ph; // "__builtin_mips_mul_ph"
}
break;
}
break;
case 22: // 19 strings to match.
if (memcmp(BuiltinName.data()+0, "__builtin_mips_", 15))
break;
switch (BuiltinName[15]) {
default: break;
case 'a': // 4 strings to match.
if (memcmp(BuiltinName.data()+16, "dd", 2))
break;
switch (BuiltinName[18]) {
default: break;
case 'q': // 2 strings to match.
switch (BuiltinName[19]) {
default: break; default: break;
case 's': // 3 strings to match. case '_': // 1 string to match.
if (BuiltinName.substr(27, 2) != "s.") if (memcmp(BuiltinName.data()+20, "ph", 2))
break; break;
switch (BuiltinName[29]) { return Intrinsic::mips_addq_ph; // "__builtin_mips_addq_ph"
default: break; case 'h': // 1 string to match.
case 'a': // 1 string to match. if (memcmp(BuiltinName.data()+20, "_w", 2))
if (BuiltinName.substr(30, 5) != "cc.s0")
break;
return Intrinsic::hexagon_M2_dpmpyss_acc_s0; // "__built
in_HEXAGON.M2.dpmpyss.acc.s0"
case 'n': // 1 string to match.
if (BuiltinName.substr(30, 5) != "ac.s0")
break;
return Intrinsic::hexagon_M2_dpmpyss_nac_s0; // "__built
in_HEXAGON.M2.dpmpyss.nac.s0"
case 'r': // 1 string to match.
if (BuiltinName.substr(30, 5) != "nd.s0")
break;
return Intrinsic::hexagon_M2_dpmpyss_rnd_s0; // "__built
in_HEXAGON.M2.dpmpyss.rnd.s0"
}
break;
case 'u': // 2 strings to match.
if (BuiltinName.substr(27, 2) != "u.")
break; break;
switch (BuiltinName[29]) { return Intrinsic::mips_addqh_w; // "__builtin_mips_addqh_w"
default: break; }
case 'a': // 1 string to match. break;
if (BuiltinName.substr(30, 5) != "cc.s0") case 'u': // 2 strings to match.
break; if (BuiltinName[19] != '_')
return Intrinsic::hexagon_M2_dpmpyuu_acc_s0; // "__built
in_HEXAGON.M2.dpmpyuu.acc.s0"
case 'n': // 1 string to match.
if (BuiltinName.substr(30, 5) != "ac.s0")
break;
return Intrinsic::hexagon_M2_dpmpyuu_nac_s0; // "__built
in_HEXAGON.M2.dpmpyuu.nac.s0"
}
break; break;
switch (BuiltinName[20]) {
default: break;
case 'p': // 1 string to match.
if (BuiltinName[21] != 'h')
break;
return Intrinsic::mips_addu_ph; // "__builtin_mips_addu_ph"
case 'q': // 1 string to match.
if (BuiltinName[21] != 'b')
break;
return Intrinsic::mips_addu_qb; // "__builtin_mips_addu_qb"
} }
break; break;
case 'm': // 40 strings to match. }
if (BuiltinName.substr(22, 2) != "py") break;
case 'p': // 3 strings to match.
switch (BuiltinName[16]) {
default: break;
case 'i': // 2 strings to match.
if (memcmp(BuiltinName.data()+17, "ck_", 3))
break; break;
switch (BuiltinName[24]) { switch (BuiltinName[20]) {
default: break; default: break;
case 'd': // 24 strings to match. case 'p': // 1 string to match.
if (BuiltinName[25] != '.') if (BuiltinName[21] != 'h')
break; break;
switch (BuiltinName[26]) { return Intrinsic::mips_pick_ph; // "__builtin_mips_pick_ph"
default: break; case 'q': // 1 string to match.
case 'a': // 8 strings to match. if (BuiltinName[21] != 'b')
if (BuiltinName.substr(27, 3) != "cc.") break;
break; return Intrinsic::mips_pick_qb; // "__builtin_mips_pick_qb"
switch (BuiltinName[30]) { }
default: break; break;
case 'h': // 4 strings to match. case 'r': // 1 string to match.
switch (BuiltinName[31]) { if (memcmp(BuiltinName.data()+17, "epend", 5))
default: break; break;
case 'h': // 2 strings to match. return Intrinsic::mips_prepend; // "__builtin_mips_prepend"
if (BuiltinName.substr(32, 2) != ".s") }
break; break;
switch (BuiltinName[34]) { case 'r': // 2 strings to match.
default: break; if (memcmp(BuiltinName.data()+16, "epl_", 4))
case '0': // 1 string to match. break;
return Intrinsic::hexagon_M2_mpyd_acc_hh_s0; // "__built switch (BuiltinName[20]) {
in_HEXAGON.M2.mpyd.acc.hh.s0" default: break;
case '1': // 1 string to match. case 'p': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_acc_hh_s1; // "__built if (BuiltinName[21] != 'h')
in_HEXAGON.M2.mpyd.acc.hh.s1" break;
} return Intrinsic::mips_repl_ph; // "__builtin_mips_repl_ph"
break; case 'q': // 1 string to match.
case 'l': // 2 strings to match. if (BuiltinName[21] != 'b')
if (BuiltinName.substr(32, 2) != ".s") break;
break; return Intrinsic::mips_repl_qb; // "__builtin_mips_repl_qb"
switch (BuiltinName[34]) { }
default: break; break;
case '0': // 1 string to match. case 's': // 10 strings to match.
return Intrinsic::hexagon_M2_mpyd_acc_hl_s0; // "__built switch (BuiltinName[16]) {
in_HEXAGON.M2.mpyd.acc.hl.s0" default: break;
case '1': // 1 string to match. case 'h': // 6 strings to match.
return Intrinsic::hexagon_M2_mpyd_acc_hl_s1; // "__built switch (BuiltinName[17]) {
in_HEXAGON.M2.mpyd.acc.hl.s1" default: break;
} case 'l': // 2 strings to match.
break; if (memcmp(BuiltinName.data()+18, "l_", 2))
}
break;
case 'l': // 4 strings to match.
switch (BuiltinName[31]) {
default: break;
case 'h': // 2 strings to match.
if (BuiltinName.substr(32, 2) != ".s")
break;
switch (BuiltinName[34]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_acc_lh_s0; // "__built
in_HEXAGON.M2.mpyd.acc.lh.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_acc_lh_s1; // "__built
in_HEXAGON.M2.mpyd.acc.lh.s1"
}
break;
case 'l': // 2 strings to match.
if (BuiltinName.substr(32, 2) != ".s")
break;
switch (BuiltinName[34]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_acc_ll_s0; // "__built
in_HEXAGON.M2.mpyd.acc.ll.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_acc_ll_s1; // "__built
in_HEXAGON.M2.mpyd.acc.ll.s1"
}
break;
}
break;
}
break; break;
case 'n': // 8 strings to match. switch (BuiltinName[20]) {
if (BuiltinName.substr(27, 3) != "ac.") default: break;
case 'p': // 1 string to match.
if (BuiltinName[21] != 'h')
break; break;
switch (BuiltinName[30]) { return Intrinsic::mips_shll_ph; // "__builtin_mips_shll_ph"
default: break; case 'q': // 1 string to match.
case 'h': // 4 strings to match. if (BuiltinName[21] != 'b')
switch (BuiltinName[31]) {
default: break;
case 'h': // 2 strings to match.
if (BuiltinName.substr(32, 2) != ".s")
break;
switch (BuiltinName[34]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_nac_hh_s0; // "__built
in_HEXAGON.M2.mpyd.nac.hh.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_nac_hh_s1; // "__built
in_HEXAGON.M2.mpyd.nac.hh.s1"
}
break;
case 'l': // 2 strings to match.
if (BuiltinName.substr(32, 2) != ".s")
break;
switch (BuiltinName[34]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_nac_hl_s0; // "__built
in_HEXAGON.M2.mpyd.nac.hl.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_nac_hl_s1; // "__built
in_HEXAGON.M2.mpyd.nac.hl.s1"
}
break;
}
break; break;
case 'l': // 4 strings to match. return Intrinsic::mips_shll_qb; // "__builtin_mips_shll_qb"
switch (BuiltinName[31]) { }
default: break; break;
case 'h': // 2 strings to match. case 'r': // 4 strings to match.
if (BuiltinName.substr(32, 2) != ".s") switch (BuiltinName[18]) {
break; default: break;
switch (BuiltinName[34]) { case 'a': // 2 strings to match.
default: break; if (BuiltinName[19] != '_')
case '0': // 1 string to match. break;
return Intrinsic::hexagon_M2_mpyd_nac_lh_s0; // "__built switch (BuiltinName[20]) {
in_HEXAGON.M2.mpyd.nac.lh.s0" default: break;
case '1': // 1 string to match. case 'p': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_nac_lh_s1; // "__built if (BuiltinName[21] != 'h')
in_HEXAGON.M2.mpyd.nac.lh.s1"
}
break; break;
case 'l': // 2 strings to match. return Intrinsic::mips_shra_ph; // "__builtin_mips_shra_ph"
if (BuiltinName.substr(32, 2) != ".s") case 'q': // 1 string to match.
break; if (BuiltinName[21] != 'b')
switch (BuiltinName[34]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_nac_ll_s0; // "__built
in_HEXAGON.M2.mpyd.nac.ll.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_nac_ll_s1; // "__built
in_HEXAGON.M2.mpyd.nac.ll.s1"
}
break; break;
} return Intrinsic::mips_shra_qb; // "__builtin_mips_shra_qb"
break;
} }
break; break;
case 'r': // 8 strings to match. case 'l': // 2 strings to match.
if (BuiltinName.substr(27, 3) != "nd.") if (BuiltinName[19] != '_')
break; break;
switch (BuiltinName[30]) { switch (BuiltinName[20]) {
default: break; default: break;
case 'h': // 4 strings to match. case 'p': // 1 string to match.
switch (BuiltinName[31]) { if (BuiltinName[21] != 'h')
default: break;
case 'h': // 2 strings to match.
if (BuiltinName.substr(32, 2) != ".s")
break;
switch (BuiltinName[34]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_rnd_hh_s0; // "__built
in_HEXAGON.M2.mpyd.rnd.hh.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_rnd_hh_s1; // "__built
in_HEXAGON.M2.mpyd.rnd.hh.s1"
}
break;
case 'l': // 2 strings to match.
if (BuiltinName.substr(32, 2) != ".s")
break;
switch (BuiltinName[34]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_rnd_hl_s0; // "__built
in_HEXAGON.M2.mpyd.rnd.hl.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_rnd_hl_s1; // "__built
in_HEXAGON.M2.mpyd.rnd.hl.s1"
}
break;
}
break;
case 'l': // 4 strings to match.
switch (BuiltinName[31]) {
default: break;
case 'h': // 2 strings to match.
if (BuiltinName.substr(32, 2) != ".s")
break;
switch (BuiltinName[34]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_rnd_lh_s0; // "__built
in_HEXAGON.M2.mpyd.rnd.lh.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_rnd_lh_s1; // "__built
in_HEXAGON.M2.mpyd.rnd.lh.s1"
}
break; break;
case 'l': // 2 strings to match. return Intrinsic::mips_shrl_ph; // "__builtin_mips_shrl_ph"
if (BuiltinName.substr(32, 2) != ".s") case 'q': // 1 string to match.
break; if (BuiltinName[21] != 'b')
switch (BuiltinName[34]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_rnd_ll_s0; // "__built
in_HEXAGON.M2.mpyd.rnd.ll.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyd_rnd_ll_s1; // "__built
in_HEXAGON.M2.mpyd.rnd.ll.s1"
}
break; break;
} return Intrinsic::mips_shrl_qb; // "__builtin_mips_shrl_qb"
break;
} }
break; break;
} }
break; break;
case 'u': // 16 strings to match. }
if (BuiltinName[25] != '.') break;
case 'u': // 4 strings to match.
if (BuiltinName[17] != 'b')
break;
switch (BuiltinName[18]) {
default: break;
case 'q': // 2 strings to match.
switch (BuiltinName[19]) {
default: break;
case '_': // 1 string to match.
if (memcmp(BuiltinName.data()+20, "ph", 2))
break;
return Intrinsic::mips_subq_ph; // "__builtin_mips_subq_ph"
case 'h': // 1 string to match.
if (memcmp(BuiltinName.data()+20, "_w", 2))
break;
return Intrinsic::mips_subqh_w; // "__builtin_mips_subqh_w"
}
break;
case 'u': // 2 strings to match.
if (BuiltinName[19] != '_')
break; break;
switch (BuiltinName[26]) { switch (BuiltinName[20]) {
default: break; default: break;
case 'a': // 8 strings to match. case 'p': // 1 string to match.
if (BuiltinName.substr(27, 3) != "cc.") if (BuiltinName[21] != 'h')
break; break;
switch (BuiltinName[30]) { return Intrinsic::mips_subu_ph; // "__builtin_mips_subu_ph"
default: break; case 'q': // 1 string to match.
case 'h': // 4 strings to match. if (BuiltinName[21] != 'b')
switch (BuiltinName[31]) {
default: break;
case 'h': // 2 strings to match.
if (BuiltinName.substr(32, 2) != ".s")
break;
switch (BuiltinName[34]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyu_acc_hh_s0; // "__built
in_HEXAGON.M2.mpyu.acc.hh.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyu_acc_hh_s1; // "__built
in_HEXAGON.M2.mpyu.acc.hh.s1"
}
break;
case 'l': // 2 strings to match.
if (BuiltinName.substr(32, 2) != ".s")
break;
switch (BuiltinName[34]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyu_acc_hl_s0; // "__built
in_HEXAGON.M2.mpyu.acc.hl.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyu_acc_hl_s1; // "__built
in_HEXAGON.M2.mpyu.acc.hl.s1"
}
break;
}
break; break;
case 'l': // 4 strings to match. return Intrinsic::mips_subu_qb; // "__builtin_mips_subu_qb"
switch (BuiltinName[31]) { }
default: break; break;
case 'h': // 2 strings to match. }
if (BuiltinName.substr(32, 2) != ".s") break;
break; }
switch (BuiltinName[34]) { break;
default: break; }
case '0': // 1 string to match. break;
return Intrinsic::hexagon_M2_mpyu_acc_lh_s0; // "__built case 23: // 16 strings to match.
in_HEXAGON.M2.mpyu.acc.lh.s0" if (memcmp(BuiltinName.data()+0, "__builtin_mips_", 15))
case '1': // 1 string to match. break;
return Intrinsic::hexagon_M2_mpyu_acc_lh_s1; // "__built switch (BuiltinName[15]) {
in_HEXAGON.M2.mpyu.acc.lh.s1" default: break;
} case 'a': // 4 strings to match.
break; switch (BuiltinName[16]) {
case 'l': // 2 strings to match. default: break;
if (BuiltinName.substr(32, 2) != ".s") case 'b': // 1 string to match.
break; if (memcmp(BuiltinName.data()+17, "sq_s_w", 6))
switch (BuiltinName[34]) { break;
default: break; return Intrinsic::mips_absq_s_w; // "__builtin_mips_absq_s_w
case '0': // 1 string to match. "
return Intrinsic::hexagon_M2_mpyu_acc_ll_s0; // "__built case 'd': // 3 strings to match.
in_HEXAGON.M2.mpyu.acc.ll.s0" if (BuiltinName[17] != 'd')
case '1': // 1 string to match. break;
return Intrinsic::hexagon_M2_mpyu_acc_ll_s1; // "__built switch (BuiltinName[18]) {
in_HEXAGON.M2.mpyu.acc.ll.s1" default: break;
} case 'q': // 2 strings to match.
break; switch (BuiltinName[19]) {
} default: break;
case '_': // 1 string to match.
if (memcmp(BuiltinName.data()+20, "s_w", 3))
break; break;
} return Intrinsic::mips_addq_s_w; // "__builtin_mips_addq_s_w
break; "
case 'n': // 8 strings to match. case 'h': // 1 string to match.
if (BuiltinName.substr(27, 3) != "ac.") if (memcmp(BuiltinName.data()+20, "_ph", 3))
break; break;
switch (BuiltinName[30]) { return Intrinsic::mips_addqh_ph; // "__builtin_mips_addqh_ph
default: break; "
case 'h': // 4 strings to match. }
switch (BuiltinName[31]) { break;
default: break; case 'u': // 1 string to match.
case 'h': // 2 strings to match. if (memcmp(BuiltinName.data()+19, "h_qb", 4))
if (BuiltinName.substr(32, 2) != ".s") break;
break; return Intrinsic::mips_adduh_qb; // "__builtin_mips_adduh_qb
switch (BuiltinName[34]) { "
default: break; }
case '0': // 1 string to match. break;
return Intrinsic::hexagon_M2_mpyu_nac_hh_s0; // "__built }
in_HEXAGON.M2.mpyu.nac.hh.s0" break;
case '1': // 1 string to match. case 'b': // 1 string to match.
return Intrinsic::hexagon_M2_mpyu_nac_hh_s1; // "__built if (memcmp(BuiltinName.data()+16, "posge32", 7))
in_HEXAGON.M2.mpyu.nac.hh.s1" break;
} return Intrinsic::mips_bposge32; // "__builtin_mips_bposge32"
break; case 'd': // 2 strings to match.
case 'l': // 2 strings to match. if (BuiltinName[16] != 'p')
if (BuiltinName.substr(32, 2) != ".s") break;
break; switch (BuiltinName[17]) {
switch (BuiltinName[34]) { default: break;
default: break; case 'a': // 1 string to match.
case '0': // 1 string to match. if (memcmp(BuiltinName.data()+18, "_w_ph", 5))
return Intrinsic::hexagon_M2_mpyu_nac_hl_s0; // "__built break;
in_HEXAGON.M2.mpyu.nac.hl.s0" return Intrinsic::mips_dpa_w_ph; // "__builtin_mips_dpa_w_ph
case '1': // 1 string to match. "
return Intrinsic::hexagon_M2_mpyu_nac_hl_s1; // "__built case 's': // 1 string to match.
in_HEXAGON.M2.mpyu.nac.hl.s1" if (memcmp(BuiltinName.data()+18, "_w_ph", 5))
} break;
break; return Intrinsic::mips_dps_w_ph; // "__builtin_mips_dps_w_ph
} "
}
break;
case 'e': // 2 strings to match.
if (memcmp(BuiltinName.data()+16, "xtr_", 4))
break;
switch (BuiltinName[20]) {
default: break;
case 'r': // 1 string to match.
if (memcmp(BuiltinName.data()+21, "_w", 2))
break;
return Intrinsic::mips_extr_r_w; // "__builtin_mips_extr_r_w
"
case 's': // 1 string to match.
if (memcmp(BuiltinName.data()+21, "_h", 2))
break;
return Intrinsic::mips_extr_s_h; // "__builtin_mips_extr_s_h
"
}
break;
case 'm': // 2 strings to match.
if (memcmp(BuiltinName.data()+16, "ul", 2))
break;
switch (BuiltinName[18]) {
default: break;
case '_': // 1 string to match.
if (memcmp(BuiltinName.data()+19, "s_ph", 4))
break;
return Intrinsic::mips_mul_s_ph; // "__builtin_mips_mul_s_ph
"
case 'q': // 1 string to match.
if (memcmp(BuiltinName.data()+19, "_s_w", 4))
break;
return Intrinsic::mips_mulq_s_w; // "__builtin_mips_mulq_s_w
"
}
break;
case 's': // 5 strings to match.
switch (BuiltinName[16]) {
default: break;
case 'h': // 2 strings to match.
switch (BuiltinName[17]) {
default: break;
case 'l': // 1 string to match.
if (memcmp(BuiltinName.data()+18, "l_s_w", 5))
break;
return Intrinsic::mips_shll_s_w; // "__builtin_mips_shll_s_w
"
case 'r': // 1 string to match.
if (memcmp(BuiltinName.data()+18, "a_r_w", 5))
break;
return Intrinsic::mips_shra_r_w; // "__builtin_mips_shra_r_w
"
}
break;
case 'u': // 3 strings to match.
if (BuiltinName[17] != 'b')
break;
switch (BuiltinName[18]) {
default: break;
case 'q': // 2 strings to match.
switch (BuiltinName[19]) {
default: break;
case '_': // 1 string to match.
if (memcmp(BuiltinName.data()+20, "s_w", 3))
break; break;
case 'l': // 4 strings to match. return Intrinsic::mips_subq_s_w; // "__builtin_mips_subq_s_w
switch (BuiltinName[31]) { "
default: break; case 'h': // 1 string to match.
case 'h': // 2 strings to match. if (memcmp(BuiltinName.data()+20, "_ph", 3))
if (BuiltinName.substr(32, 2) != ".s")
break;
switch (BuiltinName[34]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyu_nac_lh_s0; // "__built
in_HEXAGON.M2.mpyu.nac.lh.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyu_nac_lh_s1; // "__built
in_HEXAGON.M2.mpyu.nac.lh.s1"
}
break;
case 'l': // 2 strings to match.
if (BuiltinName.substr(32, 2) != ".s")
break;
switch (BuiltinName[34]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyu_nac_ll_s0; // "__built
in_HEXAGON.M2.mpyu.nac.ll.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyu_nac_ll_s1; // "__built
in_HEXAGON.M2.mpyu.nac.ll.s1"
}
break;
}
break; break;
} return Intrinsic::mips_subqh_ph; // "__builtin_mips_subqh_ph
break; "
} }
break; break;
case 'u': // 1 string to match.
if (memcmp(BuiltinName.data()+19, "h_qb", 4))
break;
return Intrinsic::mips_subuh_qb; // "__builtin_mips_subuh_qb
"
} }
break; break;
case 'v': // 7 strings to match. }
break;
}
break;
case 24: // 22 strings to match.
if (memcmp(BuiltinName.data()+0, "__builtin_mips_", 15))
break;
switch (BuiltinName[15]) {
default: break;
case 'a': // 6 strings to match.
switch (BuiltinName[16]) {
default: break;
case 'b': // 2 strings to match.
if (memcmp(BuiltinName.data()+17, "sq_s_", 5))
break;
switch (BuiltinName[22]) { switch (BuiltinName[22]) {
default: break; default: break;
case 'c': // 6 strings to match. case 'p': // 1 string to match.
if (BuiltinName[23] != 'm') if (BuiltinName[23] != 'h')
break; break;
switch (BuiltinName[24]) { return Intrinsic::mips_absq_s_ph; // "__builtin_mips_absq_s_p
h"
case 'q': // 1 string to match.
if (BuiltinName[23] != 'b')
break;
return Intrinsic::mips_absq_s_qb; // "__builtin_mips_absq_s_q
b"
}
break;
case 'd': // 4 strings to match.
if (BuiltinName[17] != 'd')
break;
switch (BuiltinName[18]) {
default: break;
case 'q': // 2 strings to match.
switch (BuiltinName[19]) {
default: break; default: break;
case 'a': // 2 strings to match. case '_': // 1 string to match.
if (BuiltinName.substr(25, 9) != "c.s0.sat.") if (memcmp(BuiltinName.data()+20, "s_ph", 4))
break; break;
switch (BuiltinName[34]) { return Intrinsic::mips_addq_s_ph; // "__builtin_mips_addq_s_p
default: break; h"
case 'i': // 1 string to match. case 'h': // 1 string to match.
return Intrinsic::hexagon_M2_vcmac_s0_sat_i; // "__built if (memcmp(BuiltinName.data()+20, "_r_w", 4))
in_HEXAGON.M2.vcmac.s0.sat.i"
case 'r': // 1 string to match.
return Intrinsic::hexagon_M2_vcmac_s0_sat_r; // "__built
in_HEXAGON.M2.vcmac.s0.sat.r"
}
break;
case 'p': // 4 strings to match.
if (BuiltinName.substr(25, 3) != "y.s")
break; break;
switch (BuiltinName[28]) { return Intrinsic::mips_addqh_r_w; // "__builtin_mips_addqh_r_
default: break; w"
case '0': // 2 strings to match. }
if (BuiltinName.substr(29, 5) != ".sat.") break;
break; case 'u': // 2 strings to match.
switch (BuiltinName[34]) { if (memcmp(BuiltinName.data()+19, "_s_", 3))
default: break; break;
case 'i': // 1 string to match. switch (BuiltinName[22]) {
return Intrinsic::hexagon_M2_vcmpy_s0_sat_i; // "__built default: break;
in_HEXAGON.M2.vcmpy.s0.sat.i" case 'p': // 1 string to match.
case 'r': // 1 string to match. if (BuiltinName[23] != 'h')
return Intrinsic::hexagon_M2_vcmpy_s0_sat_r; // "__built
in_HEXAGON.M2.vcmpy.s0.sat.r"
}
break; break;
case '1': // 2 strings to match. return Intrinsic::mips_addu_s_ph; // "__builtin_mips_addu_s_p
if (BuiltinName.substr(29, 5) != ".sat.") h"
break; case 'q': // 1 string to match.
switch (BuiltinName[34]) { if (BuiltinName[23] != 'b')
default: break;
case 'i': // 1 string to match.
return Intrinsic::hexagon_M2_vcmpy_s1_sat_i; // "__built
in_HEXAGON.M2.vcmpy.s1.sat.i"
case 'r': // 1 string to match.
return Intrinsic::hexagon_M2_vcmpy_s1_sat_r; // "__built
in_HEXAGON.M2.vcmpy.s1.sat.r"
}
break; break;
} return Intrinsic::mips_addu_s_qb; // "__builtin_mips_addu_s_q
break; b"
} }
break; break;
case 'r': // 1 string to match.
if (BuiltinName.substr(23, 12) != "cmpys.acc.s1")
break;
return Intrinsic::hexagon_M2_vrcmpys_acc_s1; // "__builtin_HEXAG
ON.M2.vrcmpys.acc.s1"
} }
break; break;
} }
break; break;
case 'S': // 4 strings to match. case 'c': // 3 strings to match.
if (BuiltinName.substr(19, 2) != "2.") if (memcmp(BuiltinName.data()+16, "mp_", 3))
break; break;
switch (BuiltinName[21]) { switch (BuiltinName[19]) {
default: break; default: break;
case 'a': // 2 strings to match. case 'e': // 1 string to match.
if (BuiltinName.substr(22, 3) != "sr.") if (memcmp(BuiltinName.data()+20, "q_ph", 4))
break; break;
switch (BuiltinName[25]) { return Intrinsic::mips_cmp_eq_ph; // "__builtin_mips_cmp_eq_p
h"
case 'l': // 2 strings to match.
switch (BuiltinName[20]) {
default: break; default: break;
case 'i': // 1 string to match. case 'e': // 1 string to match.
if (BuiltinName.substr(26, 9) != ".svw.trun") if (memcmp(BuiltinName.data()+21, "_ph", 3))
break; break;
return Intrinsic::hexagon_S2_asr_i_svw_trun; // "__builtin_HEXAG return Intrinsic::mips_cmp_le_ph; // "__builtin_mips_cmp_le_p
ON.S2.asr.i.svw.trun" h"
case 'r': // 1 string to match. case 't': // 1 string to match.
if (BuiltinName.substr(26, 9) != ".svw.trun") if (memcmp(BuiltinName.data()+21, "_ph", 3))
break; break;
return Intrinsic::hexagon_S2_asr_r_svw_trun; // "__builtin_HEXAG ON.S2.asr.r.svw.trun" return Intrinsic::mips_cmp_lt_ph; // "__builtin_mips_cmp_lt_p h"
} }
break; break;
case 'v': // 2 strings to match. }
if (BuiltinName.substr(22, 3) != "sat") break;
case 'd': // 2 strings to match.
if (BuiltinName[16] != 'p')
break;
switch (BuiltinName[17]) {
default: break;
case 'a': // 1 string to match.
if (memcmp(BuiltinName.data()+18, "x_w_ph", 6))
break; break;
switch (BuiltinName[25]) { return Intrinsic::mips_dpax_w_ph; // "__builtin_mips_dpax_w_p
h"
case 's': // 1 string to match.
if (memcmp(BuiltinName.data()+18, "x_w_ph", 6))
break;
return Intrinsic::mips_dpsx_w_ph; // "__builtin_mips_dpsx_w_p
h"
}
break;
case 'e': // 1 string to match.
if (memcmp(BuiltinName.data()+16, "xtr_rs_w", 8))
break;
return Intrinsic::mips_extr_rs_w; // "__builtin_mips_extr_rs_
w"
case 'm': // 2 strings to match.
if (memcmp(BuiltinName.data()+16, "ulq_", 4))
break;
switch (BuiltinName[20]) {
default: break;
case 'r': // 1 string to match.
if (memcmp(BuiltinName.data()+21, "s_w", 3))
break;
return Intrinsic::mips_mulq_rs_w; // "__builtin_mips_mulq_rs_
w"
case 's': // 1 string to match.
if (memcmp(BuiltinName.data()+21, "_ph", 3))
break;
return Intrinsic::mips_mulq_s_ph; // "__builtin_mips_mulq_s_p
h"
}
break;
case 'p': // 1 string to match.
if (memcmp(BuiltinName.data()+16, "ackrl_ph", 8))
break;
return Intrinsic::mips_packrl_ph; // "__builtin_mips_packrl_p
h"
case 's': // 7 strings to match.
switch (BuiltinName[16]) {
default: break;
case 'h': // 3 strings to match.
switch (BuiltinName[17]) {
default: break; default: break;
case 'h': // 1 string to match. case 'l': // 1 string to match.
if (BuiltinName.substr(26, 9) != "ub.nopack") if (memcmp(BuiltinName.data()+18, "l_s_ph", 6))
break; break;
return Intrinsic::hexagon_S2_vsathub_nopack; // "__builtin_HEXAG return Intrinsic::mips_shll_s_ph; // "__builtin_mips_shll_s_p
ON.S2.vsathub.nopack" h"
case 'w': // 1 string to match. case 'r': // 2 strings to match.
if (BuiltinName.substr(26, 9) != "uh.nopack") if (memcmp(BuiltinName.data()+18, "a_r_", 4))
break;
switch (BuiltinName[22]) {
default: break;
case 'p': // 1 string to match.
if (BuiltinName[23] != 'h')
break;
return Intrinsic::mips_shra_r_ph; // "__builtin_mips_shra_r_p
h"
case 'q': // 1 string to match.
if (BuiltinName[23] != 'b')
break;
return Intrinsic::mips_shra_r_qb; // "__builtin_mips_shra_r_q
b"
}
break;
}
break;
case 'u': // 4 strings to match.
if (BuiltinName[17] != 'b')
break;
switch (BuiltinName[18]) {
default: break;
case 'q': // 2 strings to match.
switch (BuiltinName[19]) {
default: break;
case '_': // 1 string to match.
if (memcmp(BuiltinName.data()+20, "s_ph", 4))
break;
return Intrinsic::mips_subq_s_ph; // "__builtin_mips_subq_s_p
h"
case 'h': // 1 string to match.
if (memcmp(BuiltinName.data()+20, "_r_w", 4))
break;
return Intrinsic::mips_subqh_r_w; // "__builtin_mips_subqh_r_
w"
}
break;
case 'u': // 2 strings to match.
if (memcmp(BuiltinName.data()+19, "_s_", 3))
break; break;
return Intrinsic::hexagon_S2_vsatwuh_nopack; // "__builtin_HEXAG switch (BuiltinName[22]) {
ON.S2.vsatwuh.nopack" default: break;
case 'p': // 1 string to match.
if (BuiltinName[23] != 'h')
break;
return Intrinsic::mips_subu_s_ph; // "__builtin_mips_subu_s_p
h"
case 'q': // 1 string to match.
if (BuiltinName[23] != 'b')
break;
return Intrinsic::mips_subu_s_qb; // "__builtin_mips_subu_s_q
b"
}
break;
} }
break; break;
} }
break; break;
} }
break; break;
case 36: // 31 strings to match. case 25: // 14 strings to match.
if (BuiltinName.substr(0, 18) != "__builtin_HEXAGON.") if (memcmp(BuiltinName.data()+0, "__builtin_mips_", 15))
break; break;
switch (BuiltinName[18]) { switch (BuiltinName[15]) {
default: break; default: break;
case 'A': // 14 strings to match. case 'a': // 2 strings to match.
if (BuiltinName.substr(19, 2) != "2.") if (memcmp(BuiltinName.data()+16, "dd", 2))
break; break;
switch (BuiltinName[21]) { switch (BuiltinName[18]) {
default: break; default: break;
case 'a': // 8 strings to match. case 'q': // 1 string to match.
if (BuiltinName.substr(22, 4) != "ddh.") if (memcmp(BuiltinName.data()+19, "h_r_ph", 6))
break; break;
switch (BuiltinName[26]) { return Intrinsic::mips_addqh_r_ph; // "__builtin_mips_addqh_r_
default: break; ph"
case 'h': // 4 strings to match. case 'u': // 1 string to match.
if (BuiltinName.substr(27, 7) != "16.sat.") if (memcmp(BuiltinName.data()+19, "h_r_qb", 6))
break;
switch (BuiltinName[34]) {
default: break;
case 'h': // 2 strings to match.
switch (BuiltinName[35]) {
default: break;
case 'h': // 1 string to match.
return Intrinsic::hexagon_A2_addh_h16_sat_hh; // "__built
in_HEXAGON.A2.addh.h16.sat.hh"
case 'l': // 1 string to match.
return Intrinsic::hexagon_A2_addh_h16_sat_hl; // "__built
in_HEXAGON.A2.addh.h16.sat.hl"
}
break;
case 'l': // 2 strings to match.
switch (BuiltinName[35]) {
default: break;
case 'h': // 1 string to match.
return Intrinsic::hexagon_A2_addh_h16_sat_lh; // "__built
in_HEXAGON.A2.addh.h16.sat.lh"
case 'l': // 1 string to match.
return Intrinsic::hexagon_A2_addh_h16_sat_ll; // "__built
in_HEXAGON.A2.addh.h16.sat.ll"
}
break;
}
break; break;
case 'l': // 4 strings to match. return Intrinsic::mips_adduh_r_qb; // "__builtin_mips_adduh_r_
if (BuiltinName.substr(27, 7) != "16.sat.") qb"
break; }
switch (BuiltinName[34]) { break;
default: break; case 'c': // 3 strings to match.
case 'h': // 2 strings to match. if (memcmp(BuiltinName.data()+16, "mpu_", 4))
switch (BuiltinName[35]) { break;
default: break; switch (BuiltinName[20]) {
case 'h': // 1 string to match. default: break;
return Intrinsic::hexagon_A2_addh_l16_sat_hh; // "__built case 'e': // 1 string to match.
in_HEXAGON.A2.addh.l16.sat.hh" if (memcmp(BuiltinName.data()+21, "q_qb", 4))
case 'l': // 1 string to match. break;
return Intrinsic::hexagon_A2_addh_l16_sat_hl; // "__built return Intrinsic::mips_cmpu_eq_qb; // "__builtin_mips_cmpu_eq_
in_HEXAGON.A2.addh.l16.sat.hl" qb"
} case 'l': // 2 strings to match.
switch (BuiltinName[21]) {
default: break;
case 'e': // 1 string to match.
if (memcmp(BuiltinName.data()+22, "_qb", 3))
break; break;
case 'l': // 2 strings to match. return Intrinsic::mips_cmpu_le_qb; // "__builtin_mips_cmpu_le_
switch (BuiltinName[35]) { qb"
default: break; case 't': // 1 string to match.
case 'h': // 1 string to match. if (memcmp(BuiltinName.data()+22, "_qb", 3))
return Intrinsic::hexagon_A2_addh_l16_sat_lh; // "__built
in_HEXAGON.A2.addh.l16.sat.lh"
case 'l': // 1 string to match.
return Intrinsic::hexagon_A2_addh_l16_sat_ll; // "__built
in_HEXAGON.A2.addh.l16.sat.ll"
}
break; break;
} return Intrinsic::mips_cmpu_lt_qb; // "__builtin_mips_cmpu_lt_
qb"
}
break;
}
break;
case 'd': // 4 strings to match.
if (BuiltinName[16] != 'p')
break;
switch (BuiltinName[17]) {
default: break;
case 'a': // 2 strings to match.
if (memcmp(BuiltinName.data()+18, "u_h_qb", 6))
break; break;
switch (BuiltinName[24]) {
default: break;
case 'l': // 1 string to match.
return Intrinsic::mips_dpau_h_qbl; // "__builtin_mips_dpau_h_q
bl"
case 'r': // 1 string to match.
return Intrinsic::mips_dpau_h_qbr; // "__builtin_mips_dpau_h_q
br"
} }
break; break;
case 's': // 6 strings to match. case 's': // 2 strings to match.
if (BuiltinName.substr(22, 4) != "ubh.") if (memcmp(BuiltinName.data()+18, "u_h_qb", 6))
break; break;
switch (BuiltinName[26]) { switch (BuiltinName[24]) {
default: break; default: break;
case 'h': // 4 strings to match. case 'l': // 1 string to match.
if (BuiltinName.substr(27, 7) != "16.sat.") return Intrinsic::mips_dpsu_h_qbl; // "__builtin_mips_dpsu_h_q
break; bl"
switch (BuiltinName[34]) { case 'r': // 1 string to match.
default: break; return Intrinsic::mips_dpsu_h_qbr; // "__builtin_mips_dpsu_h_q
case 'h': // 2 strings to match. br"
switch (BuiltinName[35]) {
default: break;
case 'h': // 1 string to match.
return Intrinsic::hexagon_A2_subh_h16_sat_hh; // "__built
in_HEXAGON.A2.subh.h16.sat.hh"
case 'l': // 1 string to match.
return Intrinsic::hexagon_A2_subh_h16_sat_hl; // "__built
in_HEXAGON.A2.subh.h16.sat.hl"
}
break;
case 'l': // 2 strings to match.
switch (BuiltinName[35]) {
default: break;
case 'h': // 1 string to match.
return Intrinsic::hexagon_A2_subh_h16_sat_lh; // "__built
in_HEXAGON.A2.subh.h16.sat.lh"
case 'l': // 1 string to match.
return Intrinsic::hexagon_A2_subh_h16_sat_ll; // "__built
in_HEXAGON.A2.subh.h16.sat.ll"
}
break;
}
break;
case 'l': // 2 strings to match.
if (BuiltinName.substr(27, 7) != "16.sat.")
break;
switch (BuiltinName[34]) {
default: break;
case 'h': // 1 string to match.
if (BuiltinName[35] != 'l')
break;
return Intrinsic::hexagon_A2_subh_l16_sat_hl; // "__built
in_HEXAGON.A2.subh.l16.sat.hl"
case 'l': // 1 string to match.
if (BuiltinName[35] != 'l')
break;
return Intrinsic::hexagon_A2_subh_l16_sat_ll; // "__built
in_HEXAGON.A2.subh.l16.sat.ll"
}
break;
} }
break; break;
} }
break; break;
case 'C': // 1 string to match. case 'm': // 2 strings to match.
if (BuiltinName.substr(19, 17) != "4.fastcorner9_not") if (memcmp(BuiltinName.data()+16, "ul", 2))
break; break;
return Intrinsic::hexagon_C4_fastcorner9_not; // "__builtin_HEXAG switch (BuiltinName[18]) {
ON.C4.fastcorner9_not" default: break;
case 'M': // 16 strings to match. case 'q': // 1 string to match.
if (BuiltinName.substr(19, 8) != "2.mpyud.") if (memcmp(BuiltinName.data()+19, "_rs_ph", 6))
break;
return Intrinsic::mips_mulq_rs_ph; // "__builtin_mips_mulq_rs_
ph"
case 's': // 1 string to match.
if (memcmp(BuiltinName.data()+19, "a_w_ph", 6))
break;
return Intrinsic::mips_mulsa_w_ph; // "__builtin_mips_mulsa_w_
ph"
}
break;
case 'r': // 1 string to match.
if (memcmp(BuiltinName.data()+16, "addu_w_qb", 9))
break; break;
switch (BuiltinName[27]) { return Intrinsic::mips_raddu_w_qb; // "__builtin_mips_raddu_w_
qb"
case 's': // 2 strings to match.
if (memcmp(BuiltinName.data()+16, "ub", 2))
break;
switch (BuiltinName[18]) {
default: break; default: break;
case 'a': // 8 strings to match. case 'q': // 1 string to match.
if (BuiltinName.substr(28, 3) != "cc.") if (memcmp(BuiltinName.data()+19, "h_r_ph", 6))
break; break;
switch (BuiltinName[31]) { return Intrinsic::mips_subqh_r_ph; // "__builtin_mips_subqh_r_
default: break; ph"
case 'h': // 4 strings to match. case 'u': // 1 string to match.
switch (BuiltinName[32]) { if (memcmp(BuiltinName.data()+19, "h_r_qb", 6))
default: break;
case 'h': // 2 strings to match.
if (BuiltinName.substr(33, 2) != ".s")
break;
switch (BuiltinName[35]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyud_acc_hh_s0; // "__built
in_HEXAGON.M2.mpyud.acc.hh.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyud_acc_hh_s1; // "__built
in_HEXAGON.M2.mpyud.acc.hh.s1"
}
break;
case 'l': // 2 strings to match.
if (BuiltinName.substr(33, 2) != ".s")
break;
switch (BuiltinName[35]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyud_acc_hl_s0; // "__built
in_HEXAGON.M2.mpyud.acc.hl.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyud_acc_hl_s1; // "__built
in_HEXAGON.M2.mpyud.acc.hl.s1"
}
break;
}
break; break;
case 'l': // 4 strings to match. return Intrinsic::mips_subuh_r_qb; // "__builtin_mips_subuh_r_
switch (BuiltinName[32]) { qb"
default: break; }
case 'h': // 2 strings to match. break;
if (BuiltinName.substr(33, 2) != ".s") }
break; break;
switch (BuiltinName[35]) { case 26: // 11 strings to match.
default: break; if (memcmp(BuiltinName.data()+0, "__builtin_mips_", 15))
case '0': // 1 string to match. break;
return Intrinsic::hexagon_M2_mpyud_acc_lh_s0; // "__built switch (BuiltinName[15]) {
in_HEXAGON.M2.mpyud.acc.lh.s0" default: break;
case '1': // 1 string to match. case 'c': // 3 strings to match.
return Intrinsic::hexagon_M2_mpyud_acc_lh_s1; // "__built if (memcmp(BuiltinName.data()+16, "mpgu_", 5))
in_HEXAGON.M2.mpyud.acc.lh.s1" break;
} switch (BuiltinName[21]) {
default: break;
case 'e': // 1 string to match.
if (memcmp(BuiltinName.data()+22, "q_qb", 4))
break;
return Intrinsic::mips_cmpgu_eq_qb; // "__builtin_mips_cmpgu_eq
_qb"
case 'l': // 2 strings to match.
switch (BuiltinName[22]) {
default: break;
case 'e': // 1 string to match.
if (memcmp(BuiltinName.data()+23, "_qb", 3))
break; break;
case 'l': // 2 strings to match. return Intrinsic::mips_cmpgu_le_qb; // "__builtin_mips_cmpgu_le
if (BuiltinName.substr(33, 2) != ".s") _qb"
break; case 't': // 1 string to match.
switch (BuiltinName[35]) { if (memcmp(BuiltinName.data()+23, "_qb", 3))
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyud_acc_ll_s0; // "__built
in_HEXAGON.M2.mpyud.acc.ll.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyud_acc_ll_s1; // "__built
in_HEXAGON.M2.mpyud.acc.ll.s1"
}
break; break;
} return Intrinsic::mips_cmpgu_lt_qb; // "__builtin_mips_cmpgu_lt
break; _qb"
} }
break; break;
case 'n': // 8 strings to match. }
if (BuiltinName.substr(28, 3) != "ac.") break;
case 'd': // 4 strings to match.
if (BuiltinName[16] != 'p')
break;
switch (BuiltinName[17]) {
default: break;
case 'a': // 2 strings to match.
if (memcmp(BuiltinName.data()+18, "q_s", 3))
break; break;
switch (BuiltinName[31]) { switch (BuiltinName[21]) {
default: break; default: break;
case 'h': // 4 strings to match. case '_': // 1 string to match.
switch (BuiltinName[32]) { if (memcmp(BuiltinName.data()+22, "w_ph", 4))
default: break;
case 'h': // 2 strings to match.
if (BuiltinName.substr(33, 2) != ".s")
break;
switch (BuiltinName[35]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyud_nac_hh_s0; // "__built
in_HEXAGON.M2.mpyud.nac.hh.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyud_nac_hh_s1; // "__built
in_HEXAGON.M2.mpyud.nac.hh.s1"
}
break; break;
case 'l': // 2 strings to match. return Intrinsic::mips_dpaq_s_w_ph; // "__builtin_mips_dpaq_s_w
if (BuiltinName.substr(33, 2) != ".s") _ph"
break; case 'a': // 1 string to match.
switch (BuiltinName[35]) { if (memcmp(BuiltinName.data()+22, "_l_w", 4))
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyud_nac_hl_s0; // "__built
in_HEXAGON.M2.mpyud.nac.hl.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyud_nac_hl_s1; // "__built
in_HEXAGON.M2.mpyud.nac.hl.s1"
}
break; break;
} return Intrinsic::mips_dpaq_sa_l_w; // "__builtin_mips_dpaq_sa_
l_w"
}
break;
case 's': // 2 strings to match.
if (memcmp(BuiltinName.data()+18, "q_s", 3))
break; break;
case 'l': // 4 strings to match. switch (BuiltinName[21]) {
switch (BuiltinName[32]) { default: break;
default: break; case '_': // 1 string to match.
case 'h': // 2 strings to match. if (memcmp(BuiltinName.data()+22, "w_ph", 4))
if (BuiltinName.substr(33, 2) != ".s")
break;
switch (BuiltinName[35]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyud_nac_lh_s0; // "__built
in_HEXAGON.M2.mpyud.nac.lh.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyud_nac_lh_s1; // "__built
in_HEXAGON.M2.mpyud.nac.lh.s1"
}
break; break;
case 'l': // 2 strings to match. return Intrinsic::mips_dpsq_s_w_ph; // "__builtin_mips_dpsq_s_w
if (BuiltinName.substr(33, 2) != ".s") _ph"
break; case 'a': // 1 string to match.
switch (BuiltinName[35]) { if (memcmp(BuiltinName.data()+22, "_l_w", 4))
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpyud_nac_ll_s0; // "__built
in_HEXAGON.M2.mpyud.nac.ll.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpyud_nac_ll_s1; // "__built
in_HEXAGON.M2.mpyud.nac.ll.s1"
}
break; break;
} return Intrinsic::mips_dpsq_sa_l_w; // "__builtin_mips_dpsq_sa_
break; l_w"
} }
break; break;
} }
break; break;
case 'm': // 2 strings to match.
if (memcmp(BuiltinName.data()+16, "aq_s_w_ph", 9))
break;
switch (BuiltinName[25]) {
default: break;
case 'l': // 1 string to match.
return Intrinsic::mips_maq_s_w_phl; // "__builtin_mips_maq_s_w_
phl"
case 'r': // 1 string to match.
return Intrinsic::mips_maq_s_w_phr; // "__builtin_mips_maq_s_w_
phr"
}
break;
case 'p': // 2 strings to match.
if (memcmp(BuiltinName.data()+16, "recr", 4))
break;
switch (BuiltinName[20]) {
default: break;
case '_': // 1 string to match.
if (memcmp(BuiltinName.data()+21, "qb_ph", 5))
break;
return Intrinsic::mips_precr_qb_ph; // "__builtin_mips_precr_qb
_ph"
case 'q': // 1 string to match.
if (memcmp(BuiltinName.data()+21, "_ph_w", 5))
break;
return Intrinsic::mips_precrq_ph_w; // "__builtin_mips_precrq_p
h_w"
}
break;
} }
break; break;
case 38: // 24 strings to match. case 27: // 10 strings to match.
if (BuiltinName.substr(0, 25) != "__builtin_HEXAGON.M2.mpy.") if (memcmp(BuiltinName.data()+0, "__builtin_mips_", 15))
break; break;
switch (BuiltinName[25]) { switch (BuiltinName[15]) {
default: break; default: break;
case 'a': // 8 strings to match. case 'c': // 3 strings to match.
if (BuiltinName.substr(26, 7) != "cc.sat.") if (memcmp(BuiltinName.data()+16, "mpgdu_", 6))
break; break;
switch (BuiltinName[33]) { switch (BuiltinName[22]) {
default: break; default: break;
case 'h': // 4 strings to match. case 'e': // 1 string to match.
switch (BuiltinName[34]) { if (memcmp(BuiltinName.data()+23, "q_qb", 4))
break;
return Intrinsic::mips_cmpgdu_eq_qb; // "__builtin_mips_cmpgdu_e
q_qb"
case 'l': // 2 strings to match.
switch (BuiltinName[23]) {
default: break; default: break;
case 'h': // 2 strings to match. case 'e': // 1 string to match.
if (BuiltinName.substr(35, 2) != ".s") if (memcmp(BuiltinName.data()+24, "_qb", 3))
break; break;
switch (BuiltinName[37]) { return Intrinsic::mips_cmpgdu_le_qb; // "__builtin_mips_cmpgdu_l
default: break; e_qb"
case '0': // 1 string to match. case 't': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_acc_sat_hh_s0; // "__built if (memcmp(BuiltinName.data()+24, "_qb", 3))
in_HEXAGON.M2.mpy.acc.sat.hh.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_acc_sat_hh_s1; // "__built
in_HEXAGON.M2.mpy.acc.sat.hh.s1"
}
break;
case 'l': // 2 strings to match.
if (BuiltinName.substr(35, 2) != ".s")
break; break;
switch (BuiltinName[37]) { return Intrinsic::mips_cmpgdu_lt_qb; // "__builtin_mips_cmpgdu_l
default: break; t_qb"
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_acc_sat_hl_s0; // "__built
in_HEXAGON.M2.mpy.acc.sat.hl.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_acc_sat_hl_s1; // "__built
in_HEXAGON.M2.mpy.acc.sat.hl.s1"
}
break;
} }
break; break;
case 'l': // 4 strings to match. }
switch (BuiltinName[34]) { break;
default: break; case 'd': // 2 strings to match.
case 'h': // 2 strings to match. if (BuiltinName[16] != 'p')
if (BuiltinName.substr(35, 2) != ".s") break;
break; switch (BuiltinName[17]) {
switch (BuiltinName[37]) { default: break;
default: break; case 'a': // 1 string to match.
case '0': // 1 string to match. if (memcmp(BuiltinName.data()+18, "qx_s_w_ph", 9))
return Intrinsic::hexagon_M2_mpy_acc_sat_lh_s0; // "__built
in_HEXAGON.M2.mpy.acc.sat.lh.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_acc_sat_lh_s1; // "__built
in_HEXAGON.M2.mpy.acc.sat.lh.s1"
}
break; break;
case 'l': // 2 strings to match. return Intrinsic::mips_dpaqx_s_w_ph; // "__builtin_mips_dpaqx_s_
if (BuiltinName.substr(35, 2) != ".s") w_ph"
break; case 's': // 1 string to match.
switch (BuiltinName[37]) { if (memcmp(BuiltinName.data()+18, "qx_s_w_ph", 9))
default: break; break;
case '0': // 1 string to match. return Intrinsic::mips_dpsqx_s_w_ph; // "__builtin_mips_dpsqx_s_
return Intrinsic::hexagon_M2_mpy_acc_sat_ll_s0; // "__built w_ph"
in_HEXAGON.M2.mpy.acc.sat.ll.s0" }
case '1': // 1 string to match. break;
return Intrinsic::hexagon_M2_mpy_acc_sat_ll_s1; // "__built case 'm': // 2 strings to match.
in_HEXAGON.M2.mpy.acc.sat.ll.s1" if (memcmp(BuiltinName.data()+16, "aq_sa_w_ph", 10))
} break;
switch (BuiltinName[26]) {
default: break;
case 'l': // 1 string to match.
return Intrinsic::mips_maq_sa_w_phl; // "__builtin_mips_maq_sa_w
_phl"
case 'r': // 1 string to match.
return Intrinsic::mips_maq_sa_w_phr; // "__builtin_mips_maq_sa_w
_phr"
}
break;
case 'p': // 3 strings to match.
if (memcmp(BuiltinName.data()+16, "rec", 3))
break;
switch (BuiltinName[19]) {
default: break;
case 'e': // 2 strings to match.
if (memcmp(BuiltinName.data()+20, "q_w_ph", 6))
break; break;
switch (BuiltinName[26]) {
default: break;
case 'l': // 1 string to match.
return Intrinsic::mips_preceq_w_phl; // "__builtin_mips_preceq_w
_phl"
case 'r': // 1 string to match.
return Intrinsic::mips_preceq_w_phr; // "__builtin_mips_preceq_w
_phr"
} }
break; break;
case 'r': // 1 string to match.
if (memcmp(BuiltinName.data()+20, "q_qb_ph", 7))
break;
return Intrinsic::mips_precrq_qb_ph; // "__builtin_mips_precrq_q
b_ph"
} }
break; break;
case 'n': // 8 strings to match. }
if (BuiltinName.substr(26, 7) != "ac.sat.") break;
case 28: // 7 strings to match.
if (memcmp(BuiltinName.data()+0, "__builtin_mips_", 15))
break;
switch (BuiltinName[15]) {
default: break;
case 'd': // 2 strings to match.
if (BuiltinName[16] != 'p')
break; break;
switch (BuiltinName[33]) { switch (BuiltinName[17]) {
default: break; default: break;
case 'h': // 4 strings to match. case 'a': // 1 string to match.
switch (BuiltinName[34]) { if (memcmp(BuiltinName.data()+18, "qx_sa_w_ph", 10))
default: break;
case 'h': // 2 strings to match.
if (BuiltinName.substr(35, 2) != ".s")
break;
switch (BuiltinName[37]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_nac_sat_hh_s0; // "__built
in_HEXAGON.M2.mpy.nac.sat.hh.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_nac_sat_hh_s1; // "__built
in_HEXAGON.M2.mpy.nac.sat.hh.s1"
}
break; break;
case 'l': // 2 strings to match. return Intrinsic::mips_dpaqx_sa_w_ph; // "__builtin_mips_dpaqx_sa
if (BuiltinName.substr(35, 2) != ".s") _w_ph"
break; case 's': // 1 string to match.
switch (BuiltinName[37]) { if (memcmp(BuiltinName.data()+18, "qx_sa_w_ph", 10))
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_nac_sat_hl_s0; // "__built
in_HEXAGON.M2.mpy.nac.sat.hl.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_nac_sat_hl_s1; // "__built
in_HEXAGON.M2.mpy.nac.sat.hl.s1"
}
break; break;
} return Intrinsic::mips_dpsqx_sa_w_ph; // "__builtin_mips_dpsqx_sa
_w_ph"
}
break;
case 'm': // 3 strings to match.
if (memcmp(BuiltinName.data()+16, "ul", 2))
break; break;
case 'l': // 4 strings to match. switch (BuiltinName[18]) {
switch (BuiltinName[34]) { default: break;
default: break; case 'e': // 2 strings to match.
case 'h': // 2 strings to match. if (memcmp(BuiltinName.data()+19, "q_s_w_ph", 8))
if (BuiltinName.substr(35, 2) != ".s")
break;
switch (BuiltinName[37]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_nac_sat_lh_s0; // "__built
in_HEXAGON.M2.mpy.nac.sat.lh.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_nac_sat_lh_s1; // "__built
in_HEXAGON.M2.mpy.nac.sat.lh.s1"
}
break;
case 'l': // 2 strings to match.
if (BuiltinName.substr(35, 2) != ".s")
break;
switch (BuiltinName[37]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_nac_sat_ll_s0; // "__built
in_HEXAGON.M2.mpy.nac.sat.ll.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_nac_sat_ll_s1; // "__built
in_HEXAGON.M2.mpy.nac.sat.ll.s1"
}
break; break;
switch (BuiltinName[27]) {
default: break;
case 'l': // 1 string to match.
return Intrinsic::mips_muleq_s_w_phl; // "__builtin_mips_
muleq_s_w_phl"
case 'r': // 1 string to match.
return Intrinsic::mips_muleq_s_w_phr; // "__builtin_mips_
muleq_s_w_phr"
} }
break; break;
case 's': // 1 string to match.
if (memcmp(BuiltinName.data()+19, "aq_s_w_ph", 9))
break;
return Intrinsic::mips_mulsaq_s_w_ph; // "__builtin_mips_mulsaq_s
_w_ph"
} }
break; break;
case 's': // 8 strings to match. case 'p': // 2 strings to match.
if (BuiltinName.substr(26, 7) != "at.rnd.") if (memcmp(BuiltinName.data()+16, "receu_ph_qb", 11))
break; break;
switch (BuiltinName[33]) { switch (BuiltinName[27]) {
default: break; default: break;
case 'h': // 4 strings to match. case 'l': // 1 string to match.
switch (BuiltinName[34]) { return Intrinsic::mips_preceu_ph_qbl; // "__builtin_mips_preceu_p
h_qbl"
case 'r': // 1 string to match.
return Intrinsic::mips_preceu_ph_qbr; // "__builtin_mips_preceu_p
h_qbr"
}
break;
}
break;
case 29: // 8 strings to match.
if (memcmp(BuiltinName.data()+0, "__builtin_mips_", 15))
break;
switch (BuiltinName[15]) {
default: break;
case 'm': // 2 strings to match.
if (memcmp(BuiltinName.data()+16, "uleu_s_ph_qb", 12))
break;
switch (BuiltinName[28]) {
default: break;
case 'l': // 1 string to match.
return Intrinsic::mips_muleu_s_ph_qbl; // "__builtin_mips_muleu_s_
ph_qbl"
case 'r': // 1 string to match.
return Intrinsic::mips_muleu_s_ph_qbr; // "__builtin_mips_muleu_s_
ph_qbr"
}
break;
case 'p': // 6 strings to match.
if (memcmp(BuiltinName.data()+16, "rec", 3))
break;
switch (BuiltinName[19]) {
default: break;
case 'e': // 4 strings to match.
switch (BuiltinName[20]) {
default: break; default: break;
case 'h': // 2 strings to match. case 'q': // 2 strings to match.
if (BuiltinName.substr(35, 2) != ".s") if (memcmp(BuiltinName.data()+21, "u_ph_qb", 7))
break; break;
switch (BuiltinName[37]) { switch (BuiltinName[28]) {
default: break; default: break;
case '0': // 1 string to match. case 'l': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_sat_rnd_hh_s0; // "__built return Intrinsic::mips_precequ_ph_qbl; // "__builtin_mips_
in_HEXAGON.M2.mpy.sat.rnd.hh.s0" precequ_ph_qbl"
case '1': // 1 string to match. case 'r': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_sat_rnd_hh_s1; // "__built return Intrinsic::mips_precequ_ph_qbr; // "__builtin_mips_
in_HEXAGON.M2.mpy.sat.rnd.hh.s1" precequ_ph_qbr"
} }
break; break;
case 'l': // 2 strings to match. case 'u': // 2 strings to match.
if (BuiltinName.substr(35, 2) != ".s") if (memcmp(BuiltinName.data()+21, "_ph_qb", 6))
break; break;
switch (BuiltinName[37]) { switch (BuiltinName[27]) {
default: break; default: break;
case '0': // 1 string to match. case 'l': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_sat_rnd_hl_s0; // "__built if (BuiltinName[28] != 'a')
in_HEXAGON.M2.mpy.sat.rnd.hl.s0" break;
case '1': // 1 string to match. return Intrinsic::mips_preceu_ph_qbla; // "__builtin_mips_
return Intrinsic::hexagon_M2_mpy_sat_rnd_hl_s1; // "__built preceu_ph_qbla"
in_HEXAGON.M2.mpy.sat.rnd.hl.s1" case 'r': // 1 string to match.
if (BuiltinName[28] != 'a')
break;
return Intrinsic::mips_preceu_ph_qbra; // "__builtin_mips_
preceu_ph_qbra"
} }
break; break;
} }
break; break;
case 'l': // 4 strings to match. case 'r': // 2 strings to match.
switch (BuiltinName[34]) { switch (BuiltinName[20]) {
default: break; default: break;
case 'h': // 2 strings to match. case '_': // 1 string to match.
if (BuiltinName.substr(35, 2) != ".s") if (memcmp(BuiltinName.data()+21, "sra_ph_w", 8))
break; break;
switch (BuiltinName[37]) { return Intrinsic::mips_precr_sra_ph_w; // "__builtin_mips_
default: break; precr_sra_ph_w"
case '0': // 1 string to match. case 'q': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_sat_rnd_lh_s0; // "__built if (memcmp(BuiltinName.data()+21, "_rs_ph_w", 8))
in_HEXAGON.M2.mpy.sat.rnd.lh.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_sat_rnd_lh_s1; // "__built
in_HEXAGON.M2.mpy.sat.rnd.lh.s1"
}
break;
case 'l': // 2 strings to match.
if (BuiltinName.substr(35, 2) != ".s")
break; break;
switch (BuiltinName[37]) { return Intrinsic::mips_precrq_rs_ph_w; // "__builtin_mips_
default: break; precrq_rs_ph_w"
case '0': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_sat_rnd_ll_s0; // "__built
in_HEXAGON.M2.mpy.sat.rnd.ll.s0"
case '1': // 1 string to match.
return Intrinsic::hexagon_M2_mpy_sat_rnd_ll_s1; // "__built
in_HEXAGON.M2.mpy.sat.rnd.ll.s1"
}
break;
} }
break; break;
} }
break; break;
} }
break; break;
case 41: // 4 strings to match. case 30: // 3 strings to match.
if (BuiltinName.substr(0, 29) != "__builtin_HEXAGON.S2.tableidx") if (memcmp(BuiltinName.data()+0, "__builtin_mips_prec", 19))
break; break;
switch (BuiltinName[29]) { switch (BuiltinName[19]) {
default: break; default: break;
case 'b': // 1 string to match. case 'e': // 2 strings to match.
if (BuiltinName.substr(30, 11) != ".goodsyntax") if (memcmp(BuiltinName.data()+20, "qu_ph_qb", 8))
break;
return Intrinsic::hexagon_S2_tableidxb_goodsyntax; // "__built
in_HEXAGON.S2.tableidxb.goodsyntax"
case 'd': // 1 string to match.
if (BuiltinName.substr(30, 11) != ".goodsyntax")
break;
return Intrinsic::hexagon_S2_tableidxd_goodsyntax; // "__built
in_HEXAGON.S2.tableidxd.goodsyntax"
case 'h': // 1 string to match.
if (BuiltinName.substr(30, 11) != ".goodsyntax")
break; break;
return Intrinsic::hexagon_S2_tableidxh_goodsyntax; // "__built switch (BuiltinName[28]) {
in_HEXAGON.S2.tableidxh.goodsyntax" default: break;
case 'w': // 1 string to match. case 'l': // 1 string to match.
if (BuiltinName.substr(30, 11) != ".goodsyntax") if (BuiltinName[29] != 'a')
break;
return Intrinsic::mips_precequ_ph_qbla; // "__builtin_mips_
precequ_ph_qbla"
case 'r': // 1 string to match.
if (BuiltinName[29] != 'a')
break;
return Intrinsic::mips_precequ_ph_qbra; // "__builtin_mips_
precequ_ph_qbra"
}
break;
case 'r': // 1 string to match.
if (memcmp(BuiltinName.data()+20, "qu_s_qb_ph", 10))
break; break;
return Intrinsic::hexagon_S2_tableidxw_goodsyntax; // "__built in_HEXAGON.S2.tableidxw.goodsyntax" return Intrinsic::mips_precrqu_s_qb_ph; // "__builtin_mips_precrqu_ s_qb_ph"
} }
break; break;
case 43: // 1 string to match. case 31: // 1 string to match.
if (BuiltinName.substr(0, 43) != "__builtin_HEXAGON.S2.asr.i.r.rnd.good if (memcmp(BuiltinName.data()+0, "__builtin_mips_precr_sra_r_ph_w", 31)
syntax") )
break; break;
return Intrinsic::hexagon_S2_asr_i_r_rnd_goodsyntax; // "__built in_HEXAGON.S2.asr.i.r.rnd.goodsyntax" return Intrinsic::mips_precr_sra_r_ph_w; // "__builtin_mips_precr_sr a_r_ph_w"
} }
} }
if (TargetPrefix == "ppc") { if (TargetPrefix == "ppc") {
switch (BuiltinName.size()) { switch (BuiltinName.size()) {
default: break; default: break;
case 21: // 4 strings to match. case 21: // 4 strings to match.
if (BuiltinName.substr(0, 18) != "__builtin_altivec_") if (memcmp(BuiltinName.data()+0, "__builtin_altivec_", 18))
break; break;
switch (BuiltinName[18]) { switch (BuiltinName[18]) {
default: break; default: break;
case 'd': // 2 strings to match. case 'd': // 2 strings to match.
if (BuiltinName[19] != 's') if (BuiltinName[19] != 's')
break; break;
switch (BuiltinName[20]) { switch (BuiltinName[20]) {
default: break; default: break;
case 's': // 1 string to match. case 's': // 1 string to match.
return Intrinsic::ppc_altivec_dss; // "__builtin_altivec_dss" return Intrinsic::ppc_altivec_dss; // "__builtin_altivec_dss"
skipping to change at line 33107 skipping to change at line 38305
default: break; default: break;
case 'l': // 1 string to match. case 'l': // 1 string to match.
return Intrinsic::ppc_altivec_vsl; // "__builtin_altivec_vsl" return Intrinsic::ppc_altivec_vsl; // "__builtin_altivec_vsl"
case 'r': // 1 string to match. case 'r': // 1 string to match.
return Intrinsic::ppc_altivec_vsr; // "__builtin_altivec_vsr" return Intrinsic::ppc_altivec_vsr; // "__builtin_altivec_vsr"
} }
break; break;
} }
break; break;
case 22: // 12 strings to match. case 22: // 12 strings to match.
if (BuiltinName.substr(0, 18) != "__builtin_altivec_") if (memcmp(BuiltinName.data()+0, "__builtin_altivec_", 18))
break; break;
switch (BuiltinName[18]) { switch (BuiltinName[18]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
if (BuiltinName.substr(19, 3) != "stt") if (memcmp(BuiltinName.data()+19, "stt", 3))
break; break;
return Intrinsic::ppc_altivec_dstt; // "__builtin_altivec_dstt" return Intrinsic::ppc_altivec_dstt; // "__builtin_altivec_dstt"
case 'v': // 11 strings to match. case 'v': // 11 strings to match.
switch (BuiltinName[19]) { switch (BuiltinName[19]) {
default: break; default: break;
case 'r': // 3 strings to match. case 'r': // 3 strings to match.
if (BuiltinName[20] != 'l') if (BuiltinName[20] != 'l')
break; break;
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
skipping to change at line 33167 skipping to change at line 38365
return Intrinsic::ppc_altivec_vsrw; // "__builtin_altiv ec_vsrw" return Intrinsic::ppc_altivec_vsrw; // "__builtin_altiv ec_vsrw"
} }
break; break;
} }
break; break;
} }
break; break;
} }
break; break;
case 23: // 12 strings to match. case 23: // 12 strings to match.
if (BuiltinName.substr(0, 18) != "__builtin_altivec_") if (memcmp(BuiltinName.data()+0, "__builtin_altivec_", 18))
break; break;
switch (BuiltinName[18]) { switch (BuiltinName[18]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
if (BuiltinName.substr(19, 4) != "stst") if (memcmp(BuiltinName.data()+19, "stst", 4))
break; break;
return Intrinsic::ppc_altivec_dstst; // "__builtin_altivec_dstst " return Intrinsic::ppc_altivec_dstst; // "__builtin_altivec_dstst "
case 'v': // 11 strings to match. case 'v': // 11 strings to match.
switch (BuiltinName[19]) { switch (BuiltinName[19]) {
default: break; default: break;
case 'c': // 2 strings to match. case 'c': // 2 strings to match.
if (BuiltinName[20] != 'f') if (BuiltinName[20] != 'f')
break; break;
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
skipping to change at line 33194 skipping to change at line 38392
if (BuiltinName[22] != 'x') if (BuiltinName[22] != 'x')
break; break;
return Intrinsic::ppc_altivec_vcfsx; // "__builtin_altivec_vcfsx " return Intrinsic::ppc_altivec_vcfsx; // "__builtin_altivec_vcfsx "
case 'u': // 1 string to match. case 'u': // 1 string to match.
if (BuiltinName[22] != 'x') if (BuiltinName[22] != 'x')
break; break;
return Intrinsic::ppc_altivec_vcfux; // "__builtin_altivec_vcfux " return Intrinsic::ppc_altivec_vcfux; // "__builtin_altivec_vcfux "
} }
break; break;
case 'p': // 1 string to match. case 'p': // 1 string to match.
if (BuiltinName.substr(20, 3) != "kpx") if (memcmp(BuiltinName.data()+20, "kpx", 3))
break; break;
return Intrinsic::ppc_altivec_vpkpx; // "__builtin_altivec_vpkpx " return Intrinsic::ppc_altivec_vpkpx; // "__builtin_altivec_vpkpx "
case 'r': // 5 strings to match. case 'r': // 5 strings to match.
switch (BuiltinName[20]) { switch (BuiltinName[20]) {
default: break; default: break;
case 'e': // 1 string to match. case 'e': // 1 string to match.
if (BuiltinName.substr(21, 2) != "fp") if (memcmp(BuiltinName.data()+21, "fp", 2))
break; break;
return Intrinsic::ppc_altivec_vrefp; // "__builtin_altivec_vrefp " return Intrinsic::ppc_altivec_vrefp; // "__builtin_altivec_vrefp "
case 'f': // 4 strings to match. case 'f': // 4 strings to match.
if (BuiltinName[21] != 'i') if (BuiltinName[21] != 'i')
break; break;
switch (BuiltinName[22]) { switch (BuiltinName[22]) {
default: break; default: break;
case 'm': // 1 string to match. case 'm': // 1 string to match.
return Intrinsic::ppc_altivec_vrfim; // "__builtin_altiv ec_vrfim" return Intrinsic::ppc_altivec_vrfim; // "__builtin_altiv ec_vrfim"
case 'n': // 1 string to match. case 'n': // 1 string to match.
return Intrinsic::ppc_altivec_vrfin; // "__builtin_altiv ec_vrfin" return Intrinsic::ppc_altivec_vrfin; // "__builtin_altiv ec_vrfin"
case 'p': // 1 string to match. case 'p': // 1 string to match.
return Intrinsic::ppc_altivec_vrfip; // "__builtin_altiv ec_vrfip" return Intrinsic::ppc_altivec_vrfip; // "__builtin_altiv ec_vrfip"
case 'z': // 1 string to match. case 'z': // 1 string to match.
return Intrinsic::ppc_altivec_vrfiz; // "__builtin_altiv ec_vrfiz" return Intrinsic::ppc_altivec_vrfiz; // "__builtin_altiv ec_vrfiz"
} }
break; break;
} }
break; break;
case 's': // 3 strings to match. case 's': // 3 strings to match.
if (BuiltinName.substr(20, 2) != "ra") if (memcmp(BuiltinName.data()+20, "ra", 2))
break; break;
switch (BuiltinName[22]) { switch (BuiltinName[22]) {
default: break; default: break;
case 'b': // 1 string to match. case 'b': // 1 string to match.
return Intrinsic::ppc_altivec_vsrab; // "__builtin_altivec_vsrab " return Intrinsic::ppc_altivec_vsrab; // "__builtin_altivec_vsrab "
case 'h': // 1 string to match. case 'h': // 1 string to match.
return Intrinsic::ppc_altivec_vsrah; // "__builtin_altivec_vsrah " return Intrinsic::ppc_altivec_vsrah; // "__builtin_altivec_vsrah "
case 'w': // 1 string to match. case 'w': // 1 string to match.
return Intrinsic::ppc_altivec_vsraw; // "__builtin_altivec_vsraw " return Intrinsic::ppc_altivec_vsraw; // "__builtin_altivec_vsraw "
} }
break; break;
} }
break; break;
} }
break; break;
case 24: // 26 strings to match. case 24: // 26 strings to match.
if (BuiltinName.substr(0, 18) != "__builtin_altivec_") if (memcmp(BuiltinName.data()+0, "__builtin_altivec_", 18))
break; break;
switch (BuiltinName[18]) { switch (BuiltinName[18]) {
default: break; default: break;
case 'd': // 2 strings to match. case 'd': // 2 strings to match.
if (BuiltinName[19] != 's') if (BuiltinName[19] != 's')
break; break;
switch (BuiltinName[20]) { switch (BuiltinName[20]) {
default: break; default: break;
case 's': // 1 string to match. case 's': // 1 string to match.
if (BuiltinName.substr(21, 3) != "all") if (memcmp(BuiltinName.data()+21, "all", 3))
break; break;
return Intrinsic::ppc_altivec_dssall; // "__builtin_altivec_dssal l" return Intrinsic::ppc_altivec_dssall; // "__builtin_altivec_dssal l"
case 't': // 1 string to match. case 't': // 1 string to match.
if (BuiltinName.substr(21, 3) != "stt") if (memcmp(BuiltinName.data()+21, "stt", 3))
break; break;
return Intrinsic::ppc_altivec_dststt; // "__builtin_altivec_dstst t" return Intrinsic::ppc_altivec_dststt; // "__builtin_altivec_dstst t"
} }
break; break;
case 'm': // 2 strings to match. case 'm': // 2 strings to match.
switch (BuiltinName[19]) { switch (BuiltinName[19]) {
default: break; default: break;
case 'f': // 1 string to match. case 'f': // 1 string to match.
if (BuiltinName.substr(20, 4) != "vscr") if (memcmp(BuiltinName.data()+20, "vscr", 4))
break; break;
return Intrinsic::ppc_altivec_mfvscr; // "__builtin_altivec_mfvsc r" return Intrinsic::ppc_altivec_mfvscr; // "__builtin_altivec_mfvsc r"
case 't': // 1 string to match. case 't': // 1 string to match.
if (BuiltinName.substr(20, 4) != "vscr") if (memcmp(BuiltinName.data()+20, "vscr", 4))
break; break;
return Intrinsic::ppc_altivec_mtvscr; // "__builtin_altivec_mtvsc r" return Intrinsic::ppc_altivec_mtvscr; // "__builtin_altivec_mtvsc r"
} }
break; break;
case 'v': // 22 strings to match. case 'v': // 22 strings to match.
switch (BuiltinName[19]) { switch (BuiltinName[19]) {
default: break; default: break;
case 'a': // 6 strings to match. case 'a': // 6 strings to match.
if (BuiltinName.substr(20, 2) != "vg") if (memcmp(BuiltinName.data()+20, "vg", 2))
break; break;
switch (BuiltinName[22]) { switch (BuiltinName[22]) {
default: break; default: break;
case 's': // 3 strings to match. case 's': // 3 strings to match.
switch (BuiltinName[23]) { switch (BuiltinName[23]) {
default: break; default: break;
case 'b': // 1 string to match. case 'b': // 1 string to match.
return Intrinsic::ppc_altivec_vavgsb; // "__builtin_altiv ec_vavgsb" return Intrinsic::ppc_altivec_vavgsb; // "__builtin_altiv ec_vavgsb"
case 'h': // 1 string to match. case 'h': // 1 string to match.
return Intrinsic::ppc_altivec_vavgsh; // "__builtin_altiv ec_vavgsh" return Intrinsic::ppc_altivec_vavgsh; // "__builtin_altiv ec_vavgsh"
skipping to change at line 33309 skipping to change at line 38507
} }
break; break;
} }
break; break;
case 'c': // 2 strings to match. case 'c': // 2 strings to match.
if (BuiltinName[20] != 't') if (BuiltinName[20] != 't')
break; break;
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case 's': // 1 string to match. case 's': // 1 string to match.
if (BuiltinName.substr(22, 2) != "xs") if (memcmp(BuiltinName.data()+22, "xs", 2))
break; break;
return Intrinsic::ppc_altivec_vctsxs; // "__builtin_altiv ec_vctsxs" return Intrinsic::ppc_altivec_vctsxs; // "__builtin_altiv ec_vctsxs"
case 'u': // 1 string to match. case 'u': // 1 string to match.
if (BuiltinName.substr(22, 2) != "xs") if (memcmp(BuiltinName.data()+22, "xs", 2))
break; break;
return Intrinsic::ppc_altivec_vctuxs; // "__builtin_altiv ec_vctuxs" return Intrinsic::ppc_altivec_vctuxs; // "__builtin_altiv ec_vctuxs"
} }
break; break;
case 'm': // 14 strings to match. case 'm': // 14 strings to match.
switch (BuiltinName[20]) { switch (BuiltinName[20]) {
default: break; default: break;
case 'a': // 7 strings to match. case 'a': // 7 strings to match.
if (BuiltinName[21] != 'x') if (BuiltinName[21] != 'x')
break; break;
skipping to change at line 33394 skipping to change at line 38592
break; break;
} }
break; break;
} }
break; break;
} }
break; break;
} }
break; break;
case 25: // 38 strings to match. case 25: // 38 strings to match.
if (BuiltinName.substr(0, 19) != "__builtin_altivec_v") if (memcmp(BuiltinName.data()+0, "__builtin_altivec_v", 19))
break; break;
switch (BuiltinName[19]) { switch (BuiltinName[19]) {
default: break; default: break;
case 'a': // 7 strings to match. case 'a': // 7 strings to match.
if (BuiltinName.substr(20, 2) != "dd") if (memcmp(BuiltinName.data()+20, "dd", 2))
break; break;
switch (BuiltinName[22]) { switch (BuiltinName[22]) {
default: break; default: break;
case 'c': // 1 string to match. case 'c': // 1 string to match.
if (BuiltinName.substr(23, 2) != "uw") if (memcmp(BuiltinName.data()+23, "uw", 2))
break; break;
return Intrinsic::ppc_altivec_vaddcuw; // "__builtin_altivec_vaddc uw" return Intrinsic::ppc_altivec_vaddcuw; // "__builtin_altivec_vaddc uw"
case 's': // 3 strings to match. case 's': // 3 strings to match.
switch (BuiltinName[23]) { switch (BuiltinName[23]) {
default: break; default: break;
case 'b': // 1 string to match. case 'b': // 1 string to match.
if (BuiltinName[24] != 's') if (BuiltinName[24] != 's')
break; break;
return Intrinsic::ppc_altivec_vaddsbs; // "__builtin_altiv ec_vaddsbs" return Intrinsic::ppc_altivec_vaddsbs; // "__builtin_altiv ec_vaddsbs"
case 'h': // 1 string to match. case 'h': // 1 string to match.
skipping to change at line 33444 skipping to change at line 38642
return Intrinsic::ppc_altivec_vadduhs; // "__builtin_altiv ec_vadduhs" return Intrinsic::ppc_altivec_vadduhs; // "__builtin_altiv ec_vadduhs"
case 'w': // 1 string to match. case 'w': // 1 string to match.
if (BuiltinName[24] != 's') if (BuiltinName[24] != 's')
break; break;
return Intrinsic::ppc_altivec_vadduws; // "__builtin_altiv ec_vadduws" return Intrinsic::ppc_altivec_vadduws; // "__builtin_altiv ec_vadduws"
} }
break; break;
} }
break; break;
case 'c': // 1 string to match. case 'c': // 1 string to match.
if (BuiltinName.substr(20, 5) != "mpbfp") if (memcmp(BuiltinName.data()+20, "mpbfp", 5))
break; break;
return Intrinsic::ppc_altivec_vcmpbfp; // "__builtin_altivec_vcmpb fp" return Intrinsic::ppc_altivec_vcmpbfp; // "__builtin_altivec_vcmpb fp"
case 'l': // 1 string to match. case 'l': // 1 string to match.
if (BuiltinName.substr(20, 5) != "ogefp") if (memcmp(BuiltinName.data()+20, "ogefp", 5))
break; break;
return Intrinsic::ppc_altivec_vlogefp; // "__builtin_altivec_vloge fp" return Intrinsic::ppc_altivec_vlogefp; // "__builtin_altivec_vloge fp"
case 'm': // 9 strings to match. case 'm': // 9 strings to match.
switch (BuiltinName[20]) { switch (BuiltinName[20]) {
default: break; default: break;
case 'a': // 1 string to match. case 'a': // 1 string to match.
if (BuiltinName.substr(21, 4) != "ddfp") if (memcmp(BuiltinName.data()+21, "ddfp", 4))
break; break;
return Intrinsic::ppc_altivec_vmaddfp; // "__builtin_altivec_vmadd fp" return Intrinsic::ppc_altivec_vmaddfp; // "__builtin_altivec_vmadd fp"
case 'u': // 8 strings to match. case 'u': // 8 strings to match.
if (BuiltinName[21] != 'l') if (BuiltinName[21] != 'l')
break; break;
switch (BuiltinName[22]) { switch (BuiltinName[22]) {
default: break; default: break;
case 'e': // 4 strings to match. case 'e': // 4 strings to match.
switch (BuiltinName[23]) { switch (BuiltinName[23]) {
default: break; default: break;
skipping to change at line 33553 skipping to change at line 38751
break; break;
return Intrinsic::ppc_altivec_vpkswus; // "__builtin_altiv ec_vpkswus" return Intrinsic::ppc_altivec_vpkswus; // "__builtin_altiv ec_vpkswus"
} }
break; break;
} }
break; break;
case 'u': // 2 strings to match. case 'u': // 2 strings to match.
switch (BuiltinName[22]) { switch (BuiltinName[22]) {
default: break; default: break;
case 'h': // 1 string to match. case 'h': // 1 string to match.
if (BuiltinName.substr(23, 2) != "us") if (memcmp(BuiltinName.data()+23, "us", 2))
break; break;
return Intrinsic::ppc_altivec_vpkuhus; // "__builtin_altiv ec_vpkuhus" return Intrinsic::ppc_altivec_vpkuhus; // "__builtin_altiv ec_vpkuhus"
case 'w': // 1 string to match. case 'w': // 1 string to match.
if (BuiltinName.substr(23, 2) != "us") if (memcmp(BuiltinName.data()+23, "us", 2))
break; break;
return Intrinsic::ppc_altivec_vpkuwus; // "__builtin_altiv ec_vpkuwus" return Intrinsic::ppc_altivec_vpkuwus; // "__builtin_altiv ec_vpkuwus"
} }
break; break;
} }
break; break;
case 's': // 8 strings to match. case 's': // 8 strings to match.
if (BuiltinName[20] != 'u') if (BuiltinName[20] != 'u')
break; break;
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case 'b': // 7 strings to match. case 'b': // 7 strings to match.
switch (BuiltinName[22]) { switch (BuiltinName[22]) {
default: break; default: break;
case 'c': // 1 string to match. case 'c': // 1 string to match.
if (BuiltinName.substr(23, 2) != "uw") if (memcmp(BuiltinName.data()+23, "uw", 2))
break; break;
return Intrinsic::ppc_altivec_vsubcuw; // "__builtin_altiv ec_vsubcuw" return Intrinsic::ppc_altivec_vsubcuw; // "__builtin_altiv ec_vsubcuw"
case 's': // 3 strings to match. case 's': // 3 strings to match.
switch (BuiltinName[23]) { switch (BuiltinName[23]) {
default: break; default: break;
case 'b': // 1 string to match. case 'b': // 1 string to match.
if (BuiltinName[24] != 's') if (BuiltinName[24] != 's')
break; break;
return Intrinsic::ppc_altivec_vsubsbs; // "__builtin_altiv ec_vsubsbs" return Intrinsic::ppc_altivec_vsubsbs; // "__builtin_altiv ec_vsubsbs"
case 'h': // 1 string to match. case 'h': // 1 string to match.
skipping to change at line 33613 skipping to change at line 38811
return Intrinsic::ppc_altivec_vsubuhs; // "__builtin_altiv ec_vsubuhs" return Intrinsic::ppc_altivec_vsubuhs; // "__builtin_altiv ec_vsubuhs"
case 'w': // 1 string to match. case 'w': // 1 string to match.
if (BuiltinName[24] != 's') if (BuiltinName[24] != 's')
break; break;
return Intrinsic::ppc_altivec_vsubuws; // "__builtin_altiv ec_vsubuws" return Intrinsic::ppc_altivec_vsubuws; // "__builtin_altiv ec_vsubuws"
} }
break; break;
} }
break; break;
case 'm': // 1 string to match. case 'm': // 1 string to match.
if (BuiltinName.substr(22, 3) != "sws") if (memcmp(BuiltinName.data()+22, "sws", 3))
break; break;
return Intrinsic::ppc_altivec_vsumsws; // "__builtin_altivec_vsums ws" return Intrinsic::ppc_altivec_vsumsws; // "__builtin_altivec_vsums ws"
} }
break; break;
case 'u': // 6 strings to match. case 'u': // 6 strings to match.
if (BuiltinName.substr(20, 2) != "pk") if (memcmp(BuiltinName.data()+20, "pk", 2))
break; break;
switch (BuiltinName[22]) { switch (BuiltinName[22]) {
default: break; default: break;
case 'h': // 3 strings to match. case 'h': // 3 strings to match.
switch (BuiltinName[23]) { switch (BuiltinName[23]) {
default: break; default: break;
case 'p': // 1 string to match. case 'p': // 1 string to match.
if (BuiltinName[24] != 'x') if (BuiltinName[24] != 'x')
break; break;
return Intrinsic::ppc_altivec_vupkhpx; // "__builtin_altiv ec_vupkhpx" return Intrinsic::ppc_altivec_vupkhpx; // "__builtin_altiv ec_vupkhpx"
skipping to change at line 33664 skipping to change at line 38862
return Intrinsic::ppc_altivec_vupklsh; // "__builtin_altiv ec_vupklsh" return Intrinsic::ppc_altivec_vupklsh; // "__builtin_altiv ec_vupklsh"
} }
break; break;
} }
break; break;
} }
break; break;
} }
break; break;
case 26: // 25 strings to match. case 26: // 25 strings to match.
if (BuiltinName.substr(0, 19) != "__builtin_altivec_v") if (memcmp(BuiltinName.data()+0, "__builtin_altivec_v", 19))
break; break;
switch (BuiltinName[19]) { switch (BuiltinName[19]) {
default: break; default: break;
case 'c': // 12 strings to match. case 'c': // 12 strings to match.
if (BuiltinName.substr(20, 2) != "mp") if (memcmp(BuiltinName.data()+20, "mp", 2))
break; break;
switch (BuiltinName[22]) { switch (BuiltinName[22]) {
default: break; default: break;
case 'e': // 4 strings to match. case 'e': // 4 strings to match.
if (BuiltinName[23] != 'q') if (BuiltinName[23] != 'q')
break; break;
switch (BuiltinName[24]) { switch (BuiltinName[24]) {
default: break; default: break;
case 'f': // 1 string to match. case 'f': // 1 string to match.
if (BuiltinName[25] != 'p') if (BuiltinName[25] != 'p')
skipping to change at line 33699 skipping to change at line 38897
case 'w': // 1 string to match. case 'w': // 1 string to match.
return Intrinsic::ppc_altivec_vcmpequw; // "__builtin_altiv ec_vcmpequw" return Intrinsic::ppc_altivec_vcmpequw; // "__builtin_altiv ec_vcmpequw"
} }
break; break;
} }
break; break;
case 'g': // 8 strings to match. case 'g': // 8 strings to match.
switch (BuiltinName[23]) { switch (BuiltinName[23]) {
default: break; default: break;
case 'e': // 1 string to match. case 'e': // 1 string to match.
if (BuiltinName.substr(24, 2) != "fp") if (memcmp(BuiltinName.data()+24, "fp", 2))
break; break;
return Intrinsic::ppc_altivec_vcmpgefp; // "__builtin_altiv ec_vcmpgefp" return Intrinsic::ppc_altivec_vcmpgefp; // "__builtin_altiv ec_vcmpgefp"
case 't': // 7 strings to match. case 't': // 7 strings to match.
switch (BuiltinName[24]) { switch (BuiltinName[24]) {
default: break; default: break;
case 'f': // 1 string to match. case 'f': // 1 string to match.
if (BuiltinName[25] != 'p') if (BuiltinName[25] != 'p')
break; break;
return Intrinsic::ppc_altivec_vcmpgtfp; // "__builtin_altiv ec_vcmpgtfp" return Intrinsic::ppc_altivec_vcmpgtfp; // "__builtin_altiv ec_vcmpgtfp"
case 's': // 3 strings to match. case 's': // 3 strings to match.
skipping to change at line 33738 skipping to change at line 38936
return Intrinsic::ppc_altivec_vcmpgtuw; // "__builtin_altiv ec_vcmpgtuw" return Intrinsic::ppc_altivec_vcmpgtuw; // "__builtin_altiv ec_vcmpgtuw"
} }
break; break;
} }
break; break;
} }
break; break;
} }
break; break;
case 'e': // 1 string to match. case 'e': // 1 string to match.
if (BuiltinName.substr(20, 6) != "xptefp") if (memcmp(BuiltinName.data()+20, "xptefp", 6))
break; break;
return Intrinsic::ppc_altivec_vexptefp; // "__builtin_altivec_vexpt efp" return Intrinsic::ppc_altivec_vexptefp; // "__builtin_altivec_vexpt efp"
case 'm': // 6 strings to match. case 'm': // 6 strings to match.
if (BuiltinName.substr(20, 3) != "sum") if (memcmp(BuiltinName.data()+20, "sum", 3))
break; break;
switch (BuiltinName[23]) { switch (BuiltinName[23]) {
default: break; default: break;
case 'm': // 1 string to match. case 'm': // 1 string to match.
if (BuiltinName.substr(24, 2) != "bm") if (memcmp(BuiltinName.data()+24, "bm", 2))
break; break;
return Intrinsic::ppc_altivec_vmsummbm; // "__builtin_altiv ec_vmsummbm" return Intrinsic::ppc_altivec_vmsummbm; // "__builtin_altiv ec_vmsummbm"
case 's': // 2 strings to match. case 's': // 2 strings to match.
if (BuiltinName[24] != 'h') if (BuiltinName[24] != 'h')
break; break;
switch (BuiltinName[25]) { switch (BuiltinName[25]) {
default: break; default: break;
case 'm': // 1 string to match. case 'm': // 1 string to match.
return Intrinsic::ppc_altivec_vmsumshm; // "__builtin_altiv ec_vmsumshm" return Intrinsic::ppc_altivec_vmsumshm; // "__builtin_altiv ec_vmsumshm"
case 's': // 1 string to match. case 's': // 1 string to match.
skipping to change at line 33782 skipping to change at line 38980
return Intrinsic::ppc_altivec_vmsumuhm; // "__builtin_altiv ec_vmsumuhm" return Intrinsic::ppc_altivec_vmsumuhm; // "__builtin_altiv ec_vmsumuhm"
case 's': // 1 string to match. case 's': // 1 string to match.
return Intrinsic::ppc_altivec_vmsumuhs; // "__builtin_altiv ec_vmsumuhs" return Intrinsic::ppc_altivec_vmsumuhs; // "__builtin_altiv ec_vmsumuhs"
} }
break; break;
} }
break; break;
} }
break; break;
case 'n': // 1 string to match. case 'n': // 1 string to match.
if (BuiltinName.substr(20, 6) != "msubfp") if (memcmp(BuiltinName.data()+20, "msubfp", 6))
break; break;
return Intrinsic::ppc_altivec_vnmsubfp; // "__builtin_altivec_vnmsu bfp" return Intrinsic::ppc_altivec_vnmsubfp; // "__builtin_altivec_vnmsu bfp"
case 's': // 5 strings to match. case 's': // 5 strings to match.
switch (BuiltinName[20]) { switch (BuiltinName[20]) {
default: break; default: break;
case 'e': // 1 string to match. case 'e': // 1 string to match.
if (BuiltinName.substr(21, 5) != "l_4si") if (memcmp(BuiltinName.data()+21, "l_4si", 5))
break; break;
return Intrinsic::ppc_altivec_vsel; // "__builtin_altivec_vsel_ 4si" return Intrinsic::ppc_altivec_vsel; // "__builtin_altivec_vsel_ 4si"
case 'u': // 4 strings to match. case 'u': // 4 strings to match.
if (BuiltinName[21] != 'm') if (BuiltinName[21] != 'm')
break; break;
switch (BuiltinName[22]) { switch (BuiltinName[22]) {
default: break; default: break;
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(23, 3) != "sws") if (memcmp(BuiltinName.data()+23, "sws", 3))
break; break;
return Intrinsic::ppc_altivec_vsum2sws; // "__builtin_altiv ec_vsum2sws" return Intrinsic::ppc_altivec_vsum2sws; // "__builtin_altiv ec_vsum2sws"
case '4': // 3 strings to match. case '4': // 3 strings to match.
switch (BuiltinName[23]) { switch (BuiltinName[23]) {
default: break; default: break;
case 's': // 2 strings to match. case 's': // 2 strings to match.
switch (BuiltinName[24]) { switch (BuiltinName[24]) {
default: break; default: break;
case 'b': // 1 string to match. case 'b': // 1 string to match.
if (BuiltinName[25] != 's') if (BuiltinName[25] != 's')
break; break;
return Intrinsic::ppc_altivec_vsum4sbs; // "__builtin_altiv ec_vsum4sbs" return Intrinsic::ppc_altivec_vsum4sbs; // "__builtin_altiv ec_vsum4sbs"
case 'h': // 1 string to match. case 'h': // 1 string to match.
if (BuiltinName[25] != 's') if (BuiltinName[25] != 's')
break; break;
return Intrinsic::ppc_altivec_vsum4shs; // "__builtin_altiv ec_vsum4shs" return Intrinsic::ppc_altivec_vsum4shs; // "__builtin_altiv ec_vsum4shs"
} }
break; break;
case 'u': // 1 string to match. case 'u': // 1 string to match.
if (BuiltinName.substr(24, 2) != "bs") if (memcmp(BuiltinName.data()+24, "bs", 2))
break; break;
return Intrinsic::ppc_altivec_vsum4ubs; // "__builtin_altiv ec_vsum4ubs" return Intrinsic::ppc_altivec_vsum4ubs; // "__builtin_altiv ec_vsum4ubs"
} }
break; break;
} }
break; break;
} }
break; break;
} }
break; break;
case 27: // 5 strings to match. case 27: // 5 strings to match.
if (BuiltinName.substr(0, 19) != "__builtin_altivec_v") if (memcmp(BuiltinName.data()+0, "__builtin_altivec_v", 19))
break; break;
switch (BuiltinName[19]) { switch (BuiltinName[19]) {
default: break; default: break;
case 'c': // 1 string to match. case 'c': // 1 string to match.
if (BuiltinName.substr(20, 7) != "mpbfp_p") if (memcmp(BuiltinName.data()+20, "mpbfp_p", 7))
break; break;
return Intrinsic::ppc_altivec_vcmpbfp_p; // "__builtin_altivec_vcmpb fp_p" return Intrinsic::ppc_altivec_vcmpbfp_p; // "__builtin_altivec_vcmpb fp_p"
case 'm': // 2 strings to match. case 'm': // 2 strings to match.
switch (BuiltinName[20]) { switch (BuiltinName[20]) {
default: break; default: break;
case 'h': // 1 string to match. case 'h': // 1 string to match.
if (BuiltinName.substr(21, 6) != "addshs") if (memcmp(BuiltinName.data()+21, "addshs", 6))
break; break;
return Intrinsic::ppc_altivec_vmhaddshs; // "__builtin_altiv ec_vmhaddshs" return Intrinsic::ppc_altivec_vmhaddshs; // "__builtin_altiv ec_vmhaddshs"
case 'l': // 1 string to match. case 'l': // 1 string to match.
if (BuiltinName.substr(21, 6) != "adduhm") if (memcmp(BuiltinName.data()+21, "adduhm", 6))
break; break;
return Intrinsic::ppc_altivec_vmladduhm; // "__builtin_altiv ec_vmladduhm" return Intrinsic::ppc_altivec_vmladduhm; // "__builtin_altiv ec_vmladduhm"
} }
break; break;
case 'p': // 1 string to match. case 'p': // 1 string to match.
if (BuiltinName.substr(20, 7) != "erm_4si") if (memcmp(BuiltinName.data()+20, "erm_4si", 7))
break; break;
return Intrinsic::ppc_altivec_vperm; // "__builtin_altivec_vperm _4si" return Intrinsic::ppc_altivec_vperm; // "__builtin_altivec_vperm _4si"
case 'r': // 1 string to match. case 'r': // 1 string to match.
if (BuiltinName.substr(20, 7) != "sqrtefp") if (memcmp(BuiltinName.data()+20, "sqrtefp", 7))
break; break;
return Intrinsic::ppc_altivec_vrsqrtefp; // "__builtin_altivec_vrsqr tefp" return Intrinsic::ppc_altivec_vrsqrtefp; // "__builtin_altivec_vrsqr tefp"
} }
break; break;
case 28: // 13 strings to match. case 28: // 13 strings to match.
if (BuiltinName.substr(0, 19) != "__builtin_altivec_v") if (memcmp(BuiltinName.data()+0, "__builtin_altivec_v", 19))
break; break;
switch (BuiltinName[19]) { switch (BuiltinName[19]) {
default: break; default: break;
case 'c': // 12 strings to match. case 'c': // 12 strings to match.
if (BuiltinName.substr(20, 2) != "mp") if (memcmp(BuiltinName.data()+20, "mp", 2))
break; break;
switch (BuiltinName[22]) { switch (BuiltinName[22]) {
default: break; default: break;
case 'e': // 4 strings to match. case 'e': // 4 strings to match.
if (BuiltinName[23] != 'q') if (BuiltinName[23] != 'q')
break; break;
switch (BuiltinName[24]) { switch (BuiltinName[24]) {
default: break; default: break;
case 'f': // 1 string to match. case 'f': // 1 string to match.
if (BuiltinName.substr(25, 3) != "p_p") if (memcmp(BuiltinName.data()+25, "p_p", 3))
break; break;
return Intrinsic::ppc_altivec_vcmpeqfp_p; // "__builtin_altiv ec_vcmpeqfp_p" return Intrinsic::ppc_altivec_vcmpeqfp_p; // "__builtin_altiv ec_vcmpeqfp_p"
case 'u': // 3 strings to match. case 'u': // 3 strings to match.
switch (BuiltinName[25]) { switch (BuiltinName[25]) {
default: break; default: break;
case 'b': // 1 string to match. case 'b': // 1 string to match.
if (BuiltinName.substr(26, 2) != "_p") if (memcmp(BuiltinName.data()+26, "_p", 2))
break; break;
return Intrinsic::ppc_altivec_vcmpequb_p; // "__builtin_altiv ec_vcmpequb_p" return Intrinsic::ppc_altivec_vcmpequb_p; // "__builtin_altiv ec_vcmpequb_p"
case 'h': // 1 string to match. case 'h': // 1 string to match.
if (BuiltinName.substr(26, 2) != "_p") if (memcmp(BuiltinName.data()+26, "_p", 2))
break; break;
return Intrinsic::ppc_altivec_vcmpequh_p; // "__builtin_altiv ec_vcmpequh_p" return Intrinsic::ppc_altivec_vcmpequh_p; // "__builtin_altiv ec_vcmpequh_p"
case 'w': // 1 string to match. case 'w': // 1 string to match.
if (BuiltinName.substr(26, 2) != "_p") if (memcmp(BuiltinName.data()+26, "_p", 2))
break; break;
return Intrinsic::ppc_altivec_vcmpequw_p; // "__builtin_altiv ec_vcmpequw_p" return Intrinsic::ppc_altivec_vcmpequw_p; // "__builtin_altiv ec_vcmpequw_p"
} }
break; break;
} }
break; break;
case 'g': // 8 strings to match. case 'g': // 8 strings to match.
switch (BuiltinName[23]) { switch (BuiltinName[23]) {
default: break; default: break;
case 'e': // 1 string to match. case 'e': // 1 string to match.
if (BuiltinName.substr(24, 4) != "fp_p") if (memcmp(BuiltinName.data()+24, "fp_p", 4))
break; break;
return Intrinsic::ppc_altivec_vcmpgefp_p; // "__builtin_altiv ec_vcmpgefp_p" return Intrinsic::ppc_altivec_vcmpgefp_p; // "__builtin_altiv ec_vcmpgefp_p"
case 't': // 7 strings to match. case 't': // 7 strings to match.
switch (BuiltinName[24]) { switch (BuiltinName[24]) {
default: break; default: break;
case 'f': // 1 string to match. case 'f': // 1 string to match.
if (BuiltinName.substr(25, 3) != "p_p") if (memcmp(BuiltinName.data()+25, "p_p", 3))
break; break;
return Intrinsic::ppc_altivec_vcmpgtfp_p; // "__builtin_altiv ec_vcmpgtfp_p" return Intrinsic::ppc_altivec_vcmpgtfp_p; // "__builtin_altiv ec_vcmpgtfp_p"
case 's': // 3 strings to match. case 's': // 3 strings to match.
switch (BuiltinName[25]) { switch (BuiltinName[25]) {
default: break; default: break;
case 'b': // 1 string to match. case 'b': // 1 string to match.
if (BuiltinName.substr(26, 2) != "_p") if (memcmp(BuiltinName.data()+26, "_p", 2))
break; break;
return Intrinsic::ppc_altivec_vcmpgtsb_p; // "__built return Intrinsic::ppc_altivec_vcmpgtsb_p; // "__built
in_altivec_vcmpgtsb_p" in_altivec_vcmpgtsb_p"
case 'h': // 1 string to match. case 'h': // 1 string to match.
if (BuiltinName.substr(26, 2) != "_p") if (memcmp(BuiltinName.data()+26, "_p", 2))
break; break;
return Intrinsic::ppc_altivec_vcmpgtsh_p; // "__built return Intrinsic::ppc_altivec_vcmpgtsh_p; // "__built
in_altivec_vcmpgtsh_p" in_altivec_vcmpgtsh_p"
case 'w': // 1 string to match. case 'w': // 1 string to match.
if (BuiltinName.substr(26, 2) != "_p") if (memcmp(BuiltinName.data()+26, "_p", 2))
break; break;
return Intrinsic::ppc_altivec_vcmpgtsw_p; // "__built return Intrinsic::ppc_altivec_vcmpgtsw_p; // "__built
in_altivec_vcmpgtsw_p" in_altivec_vcmpgtsw_p"
} }
break; break;
case 'u': // 3 strings to match. case 'u': // 3 strings to match.
switch (BuiltinName[25]) { switch (BuiltinName[25]) {
default: break; default: break;
case 'b': // 1 string to match. case 'b': // 1 string to match.
if (BuiltinName.substr(26, 2) != "_p") if (memcmp(BuiltinName.data()+26, "_p", 2))
break; break;
return Intrinsic::ppc_altivec_vcmpgtub_p; // "__built return Intrinsic::ppc_altivec_vcmpgtub_p; // "__built
in_altivec_vcmpgtub_p" in_altivec_vcmpgtub_p"
case 'h': // 1 string to match. case 'h': // 1 string to match.
if (BuiltinName.substr(26, 2) != "_p") if (memcmp(BuiltinName.data()+26, "_p", 2))
break; break;
return Intrinsic::ppc_altivec_vcmpgtuh_p; // "__built return Intrinsic::ppc_altivec_vcmpgtuh_p; // "__built
in_altivec_vcmpgtuh_p" in_altivec_vcmpgtuh_p"
case 'w': // 1 string to match. case 'w': // 1 string to match.
if (BuiltinName.substr(26, 2) != "_p") if (memcmp(BuiltinName.data()+26, "_p", 2))
break; break;
return Intrinsic::ppc_altivec_vcmpgtuw_p; // "__built return Intrinsic::ppc_altivec_vcmpgtuw_p; // "__built
in_altivec_vcmpgtuw_p" in_altivec_vcmpgtuw_p"
} }
break; break;
} }
break;
}
break;
}
break;
case 'm': // 1 string to match.
if (BuiltinName.substr(20, 8) != "hraddshs")
break;
return Intrinsic::ppc_altivec_vmhraddshs; // "__builtin_altiv
ec_vmhraddshs"
}
break;
}
}
if (TargetPrefix == "ptx") {
switch (BuiltinName.size()) {
default: break;
case 22: // 5 strings to match.
if (BuiltinName.substr(0, 14) != "__builtin_ptx_")
break;
switch (BuiltinName[14]) {
default: break;
case 'b': // 1 string to match.
if (BuiltinName.substr(15, 7) != "ar_sync")
break;
return Intrinsic::ptx_bar_sync; // "__builtin_ptx_bar_sync"
case 'r': // 4 strings to match.
if (BuiltinName.substr(15, 6) != "ead_pm")
break;
switch (BuiltinName[21]) {
default: break;
case '0': // 1 string to match.
return Intrinsic::ptx_read_pm0; // "__builtin_ptx_read_pm0"
case '1': // 1 string to match.
return Intrinsic::ptx_read_pm1; // "__builtin_ptx_read_pm1"
case '2': // 1 string to match.
return Intrinsic::ptx_read_pm2; // "__builtin_ptx_read_pm2"
case '3': // 1 string to match.
return Intrinsic::ptx_read_pm3; // "__builtin_ptx_read_pm3"
}
break;
}
break;
case 23: // 1 string to match.
if (BuiltinName.substr(0, 23) != "__builtin_ptx_read_smid")
break;
return Intrinsic::ptx_read_smid; // "__builtin_ptx_read_smid"
case 24: // 6 strings to match.
if (BuiltinName.substr(0, 19) != "__builtin_ptx_read_")
break;
switch (BuiltinName[19]) {
default: break;
case 'c': // 1 string to match.
if (BuiltinName.substr(20, 4) != "lock")
break;
return Intrinsic::ptx_read_clock; // "__builtin_ptx_read_cloc
k"
case 'n': // 1 string to match.
if (BuiltinName.substr(20, 4) != "smid")
break;
return Intrinsic::ptx_read_nsmid; // "__builtin_ptx_read_nsmi
d"
case 't': // 4 strings to match.
if (BuiltinName.substr(20, 3) != "id_")
break;
switch (BuiltinName[23]) {
default: break;
case 'w': // 1 string to match.
return Intrinsic::ptx_read_tid_w; // "__builtin_ptx_read_tid_
w"
case 'x': // 1 string to match.
return Intrinsic::ptx_read_tid_x; // "__builtin_ptx_read_tid_
x"
case 'y': // 1 string to match.
return Intrinsic::ptx_read_tid_y; // "__builtin_ptx_read_tid_
y"
case 'z': // 1 string to match.
return Intrinsic::ptx_read_tid_z; // "__builtin_ptx_read_tid_
z"
}
break;
}
break;
case 25: // 7 strings to match.
if (BuiltinName.substr(0, 19) != "__builtin_ptx_read_")
break;
switch (BuiltinName[19]) {
default: break;
case 'g': // 1 string to match.
if (BuiltinName.substr(20, 5) != "ridid")
break;
return Intrinsic::ptx_read_gridid; // "__builtin_ptx_read_grid
id"
case 'l': // 1 string to match.
if (BuiltinName.substr(20, 5) != "aneid")
break;
return Intrinsic::ptx_read_laneid; // "__builtin_ptx_read_lane
id"
case 'n': // 4 strings to match.
if (BuiltinName.substr(20, 4) != "tid_")
break;
switch (BuiltinName[24]) {
default: break;
case 'w': // 1 string to match.
return Intrinsic::ptx_read_ntid_w; // "__builtin_ptx_read_ntid
_w"
case 'x': // 1 string to match.
return Intrinsic::ptx_read_ntid_x; // "__builtin_ptx_read_ntid
_x"
case 'y': // 1 string to match.
return Intrinsic::ptx_read_ntid_y; // "__builtin_ptx_read_ntid
_y"
case 'z': // 1 string to match.
return Intrinsic::ptx_read_ntid_z; // "__builtin_ptx_read_ntid
_z"
}
break;
case 'w': // 1 string to match.
if (BuiltinName.substr(20, 5) != "arpid")
break;
return Intrinsic::ptx_read_warpid; // "__builtin_ptx_read_warp
id"
}
break;
case 26: // 6 strings to match.
if (BuiltinName.substr(0, 19) != "__builtin_ptx_read_")
break;
switch (BuiltinName[19]) {
default: break;
case 'c': // 5 strings to match.
switch (BuiltinName[20]) {
default: break;
case 'l': // 1 string to match.
if (BuiltinName.substr(21, 5) != "ock64")
break;
return Intrinsic::ptx_read_clock64; // "__builtin_ptx_read_cloc
k64"
case 't': // 4 strings to match.
if (BuiltinName.substr(21, 4) != "aid_")
break; break;
switch (BuiltinName[25]) {
default: break;
case 'w': // 1 string to match.
return Intrinsic::ptx_read_ctaid_w; // "__builtin_ptx_read_ctai
d_w"
case 'x': // 1 string to match.
return Intrinsic::ptx_read_ctaid_x; // "__builtin_ptx_read_ctai
d_x"
case 'y': // 1 string to match.
return Intrinsic::ptx_read_ctaid_y; // "__builtin_ptx_read_ctai
d_y"
case 'z': // 1 string to match.
return Intrinsic::ptx_read_ctaid_z; // "__builtin_ptx_read_ctai
d_z"
} }
break; break;
} }
break; break;
case 'n': // 1 string to match. case 'm': // 1 string to match.
if (BuiltinName.substr(20, 6) != "warpid") if (memcmp(BuiltinName.data()+20, "hraddshs", 8))
break;
return Intrinsic::ptx_read_nwarpid; // "__builtin_ptx_read_nwar
pid"
}
break;
case 27: // 4 strings to match.
if (BuiltinName.substr(0, 26) != "__builtin_ptx_read_nctaid_")
break;
switch (BuiltinName[26]) {
default: break;
case 'w': // 1 string to match.
return Intrinsic::ptx_read_nctaid_w; // "__builtin_ptx_read_ncta
id_w"
case 'x': // 1 string to match.
return Intrinsic::ptx_read_nctaid_x; // "__builtin_ptx_read_ncta
id_x"
case 'y': // 1 string to match.
return Intrinsic::ptx_read_nctaid_y; // "__builtin_ptx_read_ncta
id_y"
case 'z': // 1 string to match.
return Intrinsic::ptx_read_nctaid_z; // "__builtin_ptx_read_ncta
id_z"
}
break;
case 30: // 5 strings to match.
if (BuiltinName.substr(0, 28) != "__builtin_ptx_read_lanemask_")
break;
switch (BuiltinName[28]) {
default: break;
case 'e': // 1 string to match.
if (BuiltinName[29] != 'q')
break; break;
return Intrinsic::ptx_read_lanemask_eq; // "__builtin_ptx_read_lane return Intrinsic::ppc_altivec_vmhraddshs; // "__builtin_altiv
mask_eq" ec_vmhraddshs"
case 'g': // 2 strings to match.
switch (BuiltinName[29]) {
default: break;
case 'e': // 1 string to match.
return Intrinsic::ptx_read_lanemask_ge; // "__builtin_ptx_r
ead_lanemask_ge"
case 't': // 1 string to match.
return Intrinsic::ptx_read_lanemask_gt; // "__builtin_ptx_r
ead_lanemask_gt"
}
break;
case 'l': // 2 strings to match.
switch (BuiltinName[29]) {
default: break;
case 'e': // 1 string to match.
return Intrinsic::ptx_read_lanemask_le; // "__builtin_ptx_r
ead_lanemask_le"
case 't': // 1 string to match.
return Intrinsic::ptx_read_lanemask_lt; // "__builtin_ptx_r
ead_lanemask_lt"
}
break;
} }
break; break;
} }
} }
if (TargetPrefix == "spu") { if (TargetPrefix == "spu") {
switch (BuiltinName.size()) { switch (BuiltinName.size()) {
default: break; default: break;
case 14: // 1 string to match. case 14: // 1 string to match.
if (BuiltinName.substr(0, 14) != "__builtin_si_a") if (memcmp(BuiltinName.data()+0, "__builtin_si_a", 14))
break; break;
return Intrinsic::spu_si_a; // "__builtin_si_a" return Intrinsic::spu_si_a; // "__builtin_si_a"
case 15: // 9 strings to match. case 15: // 9 strings to match.
if (BuiltinName.substr(0, 13) != "__builtin_si_") if (memcmp(BuiltinName.data()+0, "__builtin_si_", 13))
break; break;
switch (BuiltinName[13]) { switch (BuiltinName[13]) {
default: break; default: break;
case 'a': // 2 strings to match. case 'a': // 2 strings to match.
switch (BuiltinName[14]) { switch (BuiltinName[14]) {
default: break; default: break;
case 'h': // 1 string to match. case 'h': // 1 string to match.
return Intrinsic::spu_si_ah; // "__builtin_si_ah" return Intrinsic::spu_si_ah; // "__builtin_si_ah"
case 'i': // 1 string to match. case 'i': // 1 string to match.
return Intrinsic::spu_si_ai; // "__builtin_si_ai" return Intrinsic::spu_si_ai; // "__builtin_si_ai"
skipping to change at line 34190 skipping to change at line 39210
if (BuiltinName[14] != 'r') if (BuiltinName[14] != 'r')
break; break;
return Intrinsic::spu_si_or; // "__builtin_si_or" return Intrinsic::spu_si_or; // "__builtin_si_or"
case 's': // 1 string to match. case 's': // 1 string to match.
if (BuiltinName[14] != 'f') if (BuiltinName[14] != 'f')
break; break;
return Intrinsic::spu_si_sf; // "__builtin_si_sf" return Intrinsic::spu_si_sf; // "__builtin_si_sf"
} }
break; break;
case 16: // 19 strings to match. case 16: // 19 strings to match.
if (BuiltinName.substr(0, 13) != "__builtin_si_") if (memcmp(BuiltinName.data()+0, "__builtin_si_", 13))
break; break;
switch (BuiltinName[13]) { switch (BuiltinName[13]) {
default: break; default: break;
case 'a': // 2 strings to match. case 'a': // 2 strings to match.
switch (BuiltinName[14]) { switch (BuiltinName[14]) {
default: break; default: break;
case 'h': // 1 string to match. case 'h': // 1 string to match.
if (BuiltinName[15] != 'i') if (BuiltinName[15] != 'i')
break; break;
return Intrinsic::spu_si_ahi; // "__builtin_si_ahi" return Intrinsic::spu_si_ahi; // "__builtin_si_ahi"
case 'n': // 1 string to match. case 'n': // 1 string to match.
if (BuiltinName[15] != 'd') if (BuiltinName[15] != 'd')
break; break;
return Intrinsic::spu_si_and; // "__builtin_si_and" return Intrinsic::spu_si_and; // "__builtin_si_and"
} }
break; break;
case 'b': // 1 string to match. case 'b': // 1 string to match.
if (BuiltinName.substr(14, 2) != "gx") if (memcmp(BuiltinName.data()+14, "gx", 2))
break; break;
return Intrinsic::spu_si_bgx; // "__builtin_si_bgx" return Intrinsic::spu_si_bgx; // "__builtin_si_bgx"
case 'c': // 3 strings to match. case 'c': // 3 strings to match.
switch (BuiltinName[14]) { switch (BuiltinName[14]) {
default: break; default: break;
case 'e': // 1 string to match. case 'e': // 1 string to match.
if (BuiltinName[15] != 'q') if (BuiltinName[15] != 'q')
break; break;
return Intrinsic::spu_si_ceq; // "__builtin_si_ceq" return Intrinsic::spu_si_ceq; // "__builtin_si_ceq"
case 'g': // 2 strings to match. case 'g': // 2 strings to match.
skipping to change at line 34254 skipping to change at line 39274
break; break;
switch (BuiltinName[15]) { switch (BuiltinName[15]) {
default: break; default: break;
case 'a': // 1 string to match. case 'a': // 1 string to match.
return Intrinsic::spu_si_fma; // "__builtin_si_fma" return Intrinsic::spu_si_fma; // "__builtin_si_fma"
case 's': // 1 string to match. case 's': // 1 string to match.
return Intrinsic::spu_si_fms; // "__builtin_si_fms" return Intrinsic::spu_si_fms; // "__builtin_si_fms"
} }
break; break;
case 'm': // 1 string to match. case 'm': // 1 string to match.
if (BuiltinName.substr(14, 2) != "py") if (memcmp(BuiltinName.data()+14, "py", 2))
break; break;
return Intrinsic::spu_si_mpy; // "__builtin_si_mpy" return Intrinsic::spu_si_mpy; // "__builtin_si_mpy"
case 'n': // 1 string to match. case 'n': // 1 string to match.
if (BuiltinName.substr(14, 2) != "or") if (memcmp(BuiltinName.data()+14, "or", 2))
break; break;
return Intrinsic::spu_si_nor; // "__builtin_si_nor" return Intrinsic::spu_si_nor; // "__builtin_si_nor"
case 'o': // 2 strings to match. case 'o': // 2 strings to match.
if (BuiltinName[14] != 'r') if (BuiltinName[14] != 'r')
break; break;
switch (BuiltinName[15]) { switch (BuiltinName[15]) {
default: break; default: break;
case 'c': // 1 string to match. case 'c': // 1 string to match.
return Intrinsic::spu_si_orc; // "__builtin_si_orc" return Intrinsic::spu_si_orc; // "__builtin_si_orc"
case 'i': // 1 string to match. case 'i': // 1 string to match.
skipping to change at line 34286 skipping to change at line 39306
default: break; default: break;
case 'h': // 1 string to match. case 'h': // 1 string to match.
return Intrinsic::spu_si_sfh; // "__builtin_si_sfh" return Intrinsic::spu_si_sfh; // "__builtin_si_sfh"
case 'i': // 1 string to match. case 'i': // 1 string to match.
return Intrinsic::spu_si_sfi; // "__builtin_si_sfi" return Intrinsic::spu_si_sfi; // "__builtin_si_sfi"
case 'x': // 1 string to match. case 'x': // 1 string to match.
return Intrinsic::spu_si_sfx; // "__builtin_si_sfx" return Intrinsic::spu_si_sfx; // "__builtin_si_sfx"
} }
break; break;
case 'x': // 1 string to match. case 'x': // 1 string to match.
if (BuiltinName.substr(14, 2) != "or") if (memcmp(BuiltinName.data()+14, "or", 2))
break; break;
return Intrinsic::spu_si_xor; // "__builtin_si_xor" return Intrinsic::spu_si_xor; // "__builtin_si_xor"
} }
break; break;
case 17: // 26 strings to match. case 17: // 26 strings to match.
if (BuiltinName.substr(0, 13) != "__builtin_si_") if (memcmp(BuiltinName.data()+0, "__builtin_si_", 13))
break; break;
switch (BuiltinName[13]) { switch (BuiltinName[13]) {
default: break; default: break;
case 'a': // 3 strings to match. case 'a': // 3 strings to match.
switch (BuiltinName[14]) { switch (BuiltinName[14]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
if (BuiltinName.substr(15, 2) != "dx") if (memcmp(BuiltinName.data()+15, "dx", 2))
break; break;
return Intrinsic::spu_si_addx; // "__builtin_si_addx" return Intrinsic::spu_si_addx; // "__builtin_si_addx"
case 'n': // 2 strings to match. case 'n': // 2 strings to match.
if (BuiltinName[15] != 'd') if (BuiltinName[15] != 'd')
break; break;
switch (BuiltinName[16]) { switch (BuiltinName[16]) {
default: break; default: break;
case 'c': // 1 string to match. case 'c': // 1 string to match.
return Intrinsic::spu_si_andc; // "__builtin_si_andc" return Intrinsic::spu_si_andc; // "__builtin_si_andc"
case 'i': // 1 string to match. case 'i': // 1 string to match.
skipping to change at line 34346 skipping to change at line 39366
default: break; default: break;
case 'b': // 1 string to match. case 'b': // 1 string to match.
return Intrinsic::spu_si_cgtb; // "__builtin_si_cgtb" return Intrinsic::spu_si_cgtb; // "__builtin_si_cgtb"
case 'h': // 1 string to match. case 'h': // 1 string to match.
return Intrinsic::spu_si_cgth; // "__builtin_si_cgth" return Intrinsic::spu_si_cgth; // "__builtin_si_cgth"
case 'i': // 1 string to match. case 'i': // 1 string to match.
return Intrinsic::spu_si_cgti; // "__builtin_si_cgti" return Intrinsic::spu_si_cgti; // "__builtin_si_cgti"
} }
break; break;
case 'l': // 1 string to match. case 'l': // 1 string to match.
if (BuiltinName.substr(15, 2) != "gt") if (memcmp(BuiltinName.data()+15, "gt", 2))
break; break;
return Intrinsic::spu_si_clgt; // "__builtin_si_clgt" return Intrinsic::spu_si_clgt; // "__builtin_si_clgt"
} }
break; break;
case 'd': // 2 strings to match. case 'd': // 2 strings to match.
if (BuiltinName.substr(14, 2) != "fm") if (memcmp(BuiltinName.data()+14, "fm", 2))
break; break;
switch (BuiltinName[16]) { switch (BuiltinName[16]) {
default: break; default: break;
case 'a': // 1 string to match. case 'a': // 1 string to match.
return Intrinsic::spu_si_dfma; // "__builtin_si_dfma" return Intrinsic::spu_si_dfma; // "__builtin_si_dfma"
case 's': // 1 string to match. case 's': // 1 string to match.
return Intrinsic::spu_si_dfms; // "__builtin_si_dfms" return Intrinsic::spu_si_dfms; // "__builtin_si_dfms"
} }
break; break;
case 'f': // 3 strings to match. case 'f': // 3 strings to match.
skipping to change at line 34379 skipping to change at line 39399
if (BuiltinName[16] != 'q') if (BuiltinName[16] != 'q')
break; break;
return Intrinsic::spu_si_fceq; // "__builtin_si_fceq" return Intrinsic::spu_si_fceq; // "__builtin_si_fceq"
case 'g': // 1 string to match. case 'g': // 1 string to match.
if (BuiltinName[16] != 't') if (BuiltinName[16] != 't')
break; break;
return Intrinsic::spu_si_fcgt; // "__builtin_si_fcgt" return Intrinsic::spu_si_fcgt; // "__builtin_si_fcgt"
} }
break; break;
case 'n': // 1 string to match. case 'n': // 1 string to match.
if (BuiltinName.substr(15, 2) != "ms") if (memcmp(BuiltinName.data()+15, "ms", 2))
break; break;
return Intrinsic::spu_si_fnms; // "__builtin_si_fnms" return Intrinsic::spu_si_fnms; // "__builtin_si_fnms"
} }
break; break;
case 'm': // 5 strings to match. case 'm': // 5 strings to match.
if (BuiltinName.substr(14, 2) != "py") if (memcmp(BuiltinName.data()+14, "py", 2))
break; break;
switch (BuiltinName[16]) { switch (BuiltinName[16]) {
default: break; default: break;
case 'a': // 1 string to match. case 'a': // 1 string to match.
return Intrinsic::spu_si_mpya; // "__builtin_si_mpya" return Intrinsic::spu_si_mpya; // "__builtin_si_mpya"
case 'h': // 1 string to match. case 'h': // 1 string to match.
return Intrinsic::spu_si_mpyh; // "__builtin_si_mpyh" return Intrinsic::spu_si_mpyh; // "__builtin_si_mpyh"
case 'i': // 1 string to match. case 'i': // 1 string to match.
return Intrinsic::spu_si_mpyi; // "__builtin_si_mpyi" return Intrinsic::spu_si_mpyi; // "__builtin_si_mpyi"
case 's': // 1 string to match. case 's': // 1 string to match.
return Intrinsic::spu_si_mpys; // "__builtin_si_mpys" return Intrinsic::spu_si_mpys; // "__builtin_si_mpys"
case 'u': // 1 string to match. case 'u': // 1 string to match.
return Intrinsic::spu_si_mpyu; // "__builtin_si_mpyu" return Intrinsic::spu_si_mpyu; // "__builtin_si_mpyu"
} }
break; break;
case 'n': // 1 string to match. case 'n': // 1 string to match.
if (BuiltinName.substr(14, 3) != "and") if (memcmp(BuiltinName.data()+14, "and", 3))
break; break;
return Intrinsic::spu_si_nand; // "__builtin_si_nand" return Intrinsic::spu_si_nand; // "__builtin_si_nand"
case 'o': // 2 strings to match. case 'o': // 2 strings to match.
if (BuiltinName[14] != 'r') if (BuiltinName[14] != 'r')
break; break;
switch (BuiltinName[15]) { switch (BuiltinName[15]) {
default: break; default: break;
case 'b': // 1 string to match. case 'b': // 1 string to match.
if (BuiltinName[16] != 'i') if (BuiltinName[16] != 'i')
break; break;
skipping to change at line 34424 skipping to change at line 39444
case 'h': // 1 string to match. case 'h': // 1 string to match.
if (BuiltinName[16] != 'i') if (BuiltinName[16] != 'i')
break; break;
return Intrinsic::spu_si_orhi; // "__builtin_si_orhi" return Intrinsic::spu_si_orhi; // "__builtin_si_orhi"
} }
break; break;
case 's': // 2 strings to match. case 's': // 2 strings to match.
switch (BuiltinName[14]) { switch (BuiltinName[14]) {
default: break; default: break;
case 'f': // 1 string to match. case 'f': // 1 string to match.
if (BuiltinName.substr(15, 2) != "hi") if (memcmp(BuiltinName.data()+15, "hi", 2))
break; break;
return Intrinsic::spu_si_sfhi; // "__builtin_si_sfhi" return Intrinsic::spu_si_sfhi; // "__builtin_si_sfhi"
case 'h': // 1 string to match. case 'h': // 1 string to match.
if (BuiltinName.substr(15, 2) != "li") if (memcmp(BuiltinName.data()+15, "li", 2))
break; break;
return Intrinsic::spu_si_shli; // "__builtin_si_shli" return Intrinsic::spu_si_shli; // "__builtin_si_shli"
} }
break; break;
case 'x': // 1 string to match. case 'x': // 1 string to match.
if (BuiltinName.substr(14, 3) != "ori") if (memcmp(BuiltinName.data()+14, "ori", 3))
break; break;
return Intrinsic::spu_si_xori; // "__builtin_si_xori" return Intrinsic::spu_si_xori; // "__builtin_si_xori"
} }
break; break;
case 18: // 18 strings to match. case 18: // 18 strings to match.
if (BuiltinName.substr(0, 13) != "__builtin_si_") if (memcmp(BuiltinName.data()+0, "__builtin_si_", 13))
break; break;
switch (BuiltinName[13]) { switch (BuiltinName[13]) {
default: break; default: break;
case 'a': // 2 strings to match. case 'a': // 2 strings to match.
if (BuiltinName.substr(14, 2) != "nd") if (memcmp(BuiltinName.data()+14, "nd", 2))
break; break;
switch (BuiltinName[16]) { switch (BuiltinName[16]) {
default: break; default: break;
case 'b': // 1 string to match. case 'b': // 1 string to match.
if (BuiltinName[17] != 'i') if (BuiltinName[17] != 'i')
break; break;
return Intrinsic::spu_si_andbi; // "__builtin_si_andbi" return Intrinsic::spu_si_andbi; // "__builtin_si_andbi"
case 'h': // 1 string to match. case 'h': // 1 string to match.
if (BuiltinName[17] != 'i') if (BuiltinName[17] != 'i')
break; break;
skipping to change at line 34493 skipping to change at line 39513
if (BuiltinName[17] != 'i') if (BuiltinName[17] != 'i')
break; break;
return Intrinsic::spu_si_cgtbi; // "__builtin_si_cgtbi" return Intrinsic::spu_si_cgtbi; // "__builtin_si_cgtbi"
case 'h': // 1 string to match. case 'h': // 1 string to match.
if (BuiltinName[17] != 'i') if (BuiltinName[17] != 'i')
break; break;
return Intrinsic::spu_si_cgthi; // "__builtin_si_cgthi" return Intrinsic::spu_si_cgthi; // "__builtin_si_cgthi"
} }
break; break;
case 'l': // 3 strings to match. case 'l': // 3 strings to match.
if (BuiltinName.substr(15, 2) != "gt") if (memcmp(BuiltinName.data()+15, "gt", 2))
break; break;
switch (BuiltinName[17]) { switch (BuiltinName[17]) {
default: break; default: break;
case 'b': // 1 string to match. case 'b': // 1 string to match.
return Intrinsic::spu_si_clgtb; // "__builtin_si_clgtb" return Intrinsic::spu_si_clgtb; // "__builtin_si_clgtb"
case 'h': // 1 string to match. case 'h': // 1 string to match.
return Intrinsic::spu_si_clgth; // "__builtin_si_clgth" return Intrinsic::spu_si_clgth; // "__builtin_si_clgth"
case 'i': // 1 string to match. case 'i': // 1 string to match.
return Intrinsic::spu_si_clgti; // "__builtin_si_clgti" return Intrinsic::spu_si_clgti; // "__builtin_si_clgti"
} }
break; break;
} }
break; break;
case 'd': // 2 strings to match. case 'd': // 2 strings to match.
if (BuiltinName.substr(14, 3) != "fnm") if (memcmp(BuiltinName.data()+14, "fnm", 3))
break; break;
switch (BuiltinName[17]) { switch (BuiltinName[17]) {
default: break; default: break;
case 'a': // 1 string to match. case 'a': // 1 string to match.
return Intrinsic::spu_si_dfnma; // "__builtin_si_dfnma" return Intrinsic::spu_si_dfnma; // "__builtin_si_dfnma"
case 's': // 1 string to match. case 's': // 1 string to match.
return Intrinsic::spu_si_dfnms; // "__builtin_si_dfnms" return Intrinsic::spu_si_dfnms; // "__builtin_si_dfnms"
} }
break; break;
case 'f': // 3 strings to match. case 'f': // 3 strings to match.
skipping to change at line 34537 skipping to change at line 39557
if (BuiltinName[17] != 'q') if (BuiltinName[17] != 'q')
break; break;
return Intrinsic::spu_si_fcmeq; // "__builtin_si_fcmeq" return Intrinsic::spu_si_fcmeq; // "__builtin_si_fcmeq"
case 'g': // 1 string to match. case 'g': // 1 string to match.
if (BuiltinName[17] != 't') if (BuiltinName[17] != 't')
break; break;
return Intrinsic::spu_si_fcmgt; // "__builtin_si_fcmgt" return Intrinsic::spu_si_fcmgt; // "__builtin_si_fcmgt"
} }
break; break;
case 's': // 1 string to match. case 's': // 1 string to match.
if (BuiltinName.substr(15, 3) != "mbi") if (memcmp(BuiltinName.data()+15, "mbi", 3))
break; break;
return Intrinsic::spu_si_fsmbi; // "__builtin_si_fsmbi" return Intrinsic::spu_si_fsmbi; // "__builtin_si_fsmbi"
} }
break; break;
case 'm': // 2 strings to match. case 'm': // 2 strings to match.
if (BuiltinName.substr(14, 2) != "py") if (memcmp(BuiltinName.data()+14, "py", 2))
break; break;
switch (BuiltinName[16]) { switch (BuiltinName[16]) {
default: break; default: break;
case 'h': // 1 string to match. case 'h': // 1 string to match.
if (BuiltinName[17] != 'h') if (BuiltinName[17] != 'h')
break; break;
return Intrinsic::spu_si_mpyhh; // "__builtin_si_mpyhh" return Intrinsic::spu_si_mpyhh; // "__builtin_si_mpyhh"
case 'u': // 1 string to match. case 'u': // 1 string to match.
if (BuiltinName[17] != 'i') if (BuiltinName[17] != 'i')
break; break;
return Intrinsic::spu_si_mpyui; // "__builtin_si_mpyui" return Intrinsic::spu_si_mpyui; // "__builtin_si_mpyui"
} }
break; break;
case 'x': // 2 strings to match. case 'x': // 2 strings to match.
if (BuiltinName.substr(14, 2) != "or") if (memcmp(BuiltinName.data()+14, "or", 2))
break; break;
switch (BuiltinName[16]) { switch (BuiltinName[16]) {
default: break; default: break;
case 'b': // 1 string to match. case 'b': // 1 string to match.
if (BuiltinName[17] != 'i') if (BuiltinName[17] != 'i')
break; break;
return Intrinsic::spu_si_xorbi; // "__builtin_si_xorbi" return Intrinsic::spu_si_xorbi; // "__builtin_si_xorbi"
case 'h': // 1 string to match. case 'h': // 1 string to match.
if (BuiltinName[17] != 'i') if (BuiltinName[17] != 'i')
break; break;
return Intrinsic::spu_si_xorhi; // "__builtin_si_xorhi" return Intrinsic::spu_si_xorhi; // "__builtin_si_xorhi"
} }
break; break;
} }
break; break;
case 19: // 6 strings to match. case 19: // 6 strings to match.
if (BuiltinName.substr(0, 13) != "__builtin_si_") if (memcmp(BuiltinName.data()+0, "__builtin_si_", 13))
break; break;
switch (BuiltinName[13]) { switch (BuiltinName[13]) {
default: break; default: break;
case 'c': // 2 strings to match. case 'c': // 2 strings to match.
if (BuiltinName.substr(14, 3) != "lgt") if (memcmp(BuiltinName.data()+14, "lgt", 3))
break; break;
switch (BuiltinName[17]) { switch (BuiltinName[17]) {
default: break; default: break;
case 'b': // 1 string to match. case 'b': // 1 string to match.
if (BuiltinName[18] != 'i') if (BuiltinName[18] != 'i')
break; break;
return Intrinsic::spu_si_clgtbi; // "__builtin_si_clgtbi" return Intrinsic::spu_si_clgtbi; // "__builtin_si_clgtbi"
case 'h': // 1 string to match. case 'h': // 1 string to match.
if (BuiltinName[18] != 'i') if (BuiltinName[18] != 'i')
break; break;
return Intrinsic::spu_si_clgthi; // "__builtin_si_clgthi" return Intrinsic::spu_si_clgthi; // "__builtin_si_clgthi"
} }
break; break;
case 'm': // 2 strings to match. case 'm': // 2 strings to match.
if (BuiltinName.substr(14, 4) != "pyhh") if (memcmp(BuiltinName.data()+14, "pyhh", 4))
break; break;
switch (BuiltinName[18]) { switch (BuiltinName[18]) {
default: break; default: break;
case 'a': // 1 string to match. case 'a': // 1 string to match.
return Intrinsic::spu_si_mpyhha; // "__builtin_si_mpyhha" return Intrinsic::spu_si_mpyhha; // "__builtin_si_mpyhha"
case 'u': // 1 string to match. case 'u': // 1 string to match.
return Intrinsic::spu_si_mpyhhu; // "__builtin_si_mpyhhu" return Intrinsic::spu_si_mpyhhu; // "__builtin_si_mpyhhu"
} }
break; break;
case 's': // 2 strings to match. case 's': // 2 strings to match.
if (BuiltinName.substr(14, 4) != "hlqb") if (memcmp(BuiltinName.data()+14, "hlqb", 4))
break; break;
switch (BuiltinName[18]) { switch (BuiltinName[18]) {
default: break; default: break;
case 'i': // 1 string to match. case 'i': // 1 string to match.
return Intrinsic::spu_si_shlqbi; // "__builtin_si_shlqbi" return Intrinsic::spu_si_shlqbi; // "__builtin_si_shlqbi"
case 'y': // 1 string to match. case 'y': // 1 string to match.
return Intrinsic::spu_si_shlqby; // "__builtin_si_shlqby" return Intrinsic::spu_si_shlqby; // "__builtin_si_shlqby"
} }
break; break;
} }
break; break;
case 20: // 3 strings to match. case 20: // 3 strings to match.
if (BuiltinName.substr(0, 13) != "__builtin_si_") if (memcmp(BuiltinName.data()+0, "__builtin_si_", 13))
break; break;
switch (BuiltinName[13]) { switch (BuiltinName[13]) {
default: break; default: break;
case 'm': // 1 string to match. case 'm': // 1 string to match.
if (BuiltinName.substr(14, 6) != "pyhhau") if (memcmp(BuiltinName.data()+14, "pyhhau", 6))
break; break;
return Intrinsic::spu_si_mpyhhau; // "__builtin_si_mpyhhau" return Intrinsic::spu_si_mpyhhau; // "__builtin_si_mpyhhau"
case 's': // 2 strings to match. case 's': // 2 strings to match.
if (BuiltinName.substr(14, 4) != "hlqb") if (memcmp(BuiltinName.data()+14, "hlqb", 4))
break; break;
switch (BuiltinName[18]) { switch (BuiltinName[18]) {
default: break; default: break;
case 'i': // 1 string to match. case 'i': // 1 string to match.
if (BuiltinName[19] != 'i') if (BuiltinName[19] != 'i')
break; break;
return Intrinsic::spu_si_shlqbii; // "__builtin_si_shlqbii" return Intrinsic::spu_si_shlqbii; // "__builtin_si_shlqbii"
case 'y': // 1 string to match. case 'y': // 1 string to match.
if (BuiltinName[19] != 'i') if (BuiltinName[19] != 'i')
break; break;
skipping to change at line 34650 skipping to change at line 39670
} }
break; break;
} }
break; break;
} }
} }
if (TargetPrefix == "x86") { if (TargetPrefix == "x86") {
switch (BuiltinName.size()) { switch (BuiltinName.size()) {
default: break; default: break;
case 18: // 1 string to match. case 18: // 1 string to match.
if (BuiltinName.substr(0, 18) != "__builtin_ia32_por") if (memcmp(BuiltinName.data()+0, "__builtin_ia32_por", 18))
break; break;
return Intrinsic::x86_mmx_por; // "__builtin_ia32_por" return Intrinsic::x86_mmx_por; // "__builtin_ia32_por"
case 19: // 5 strings to match. case 19: // 6 strings to match.
if (BuiltinName.substr(0, 15) != "__builtin_ia32_") if (memcmp(BuiltinName.data()+0, "__builtin_ia32_", 15))
break; break;
switch (BuiltinName[15]) { switch (BuiltinName[15]) {
default: break; default: break;
case 'd': // 2 strings to match. case 'd': // 2 strings to match.
if (BuiltinName.substr(16, 2) != "pp") if (memcmp(BuiltinName.data()+16, "pp", 2))
break; break;
switch (BuiltinName[18]) { switch (BuiltinName[18]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
return Intrinsic::x86_sse41_dppd; // "__builtin_ia32_dppd" return Intrinsic::x86_sse41_dppd; // "__builtin_ia32_dppd"
case 's': // 1 string to match. case 's': // 1 string to match.
return Intrinsic::x86_sse41_dpps; // "__builtin_ia32_dpps" return Intrinsic::x86_sse41_dpps; // "__builtin_ia32_dpps"
} }
break; break;
case 'e': // 1 string to match. case 'e': // 1 string to match.
if (BuiltinName.substr(16, 3) != "mms") if (memcmp(BuiltinName.data()+16, "mms", 3))
break; break;
return Intrinsic::x86_mmx_emms; // "__builtin_ia32_emms" return Intrinsic::x86_mmx_emms; // "__builtin_ia32_emms"
case 'p': // 2 strings to match. case 'p': // 2 strings to match.
switch (BuiltinName[16]) { switch (BuiltinName[16]) {
default: break; default: break;
case 'a': // 1 string to match. case 'a': // 1 string to match.
if (BuiltinName.substr(17, 2) != "nd") if (memcmp(BuiltinName.data()+17, "nd", 2))
break; break;
return Intrinsic::x86_mmx_pand; // "__builtin_ia32_pand" return Intrinsic::x86_mmx_pand; // "__builtin_ia32_pand"
case 'x': // 1 string to match. case 'x': // 1 string to match.
if (BuiltinName.substr(17, 2) != "or") if (memcmp(BuiltinName.data()+17, "or", 2))
break; break;
return Intrinsic::x86_mmx_pxor; // "__builtin_ia32_pxor" return Intrinsic::x86_mmx_pxor; // "__builtin_ia32_pxor"
} }
break; break;
case 'x': // 1 string to match.
if (memcmp(BuiltinName.data()+16, "end", 3))
break;
return Intrinsic::x86_xend; // "__builtin_ia32_xend"
} }
break; break;
case 20: // 58 strings to match. case 20: // 59 strings to match.
if (BuiltinName.substr(0, 15) != "__builtin_ia32_") if (memcmp(BuiltinName.data()+0, "__builtin_ia32_", 15))
break; break;
switch (BuiltinName[15]) { switch (BuiltinName[15]) {
default: break; default: break;
case 'a': // 2 strings to match. case 'a': // 2 strings to match.
if (BuiltinName.substr(16, 3) != "dds") if (memcmp(BuiltinName.data()+16, "dds", 3))
break; break;
switch (BuiltinName[19]) { switch (BuiltinName[19]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
return Intrinsic::x86_sse2_add_sd; // "__builtin_ia32_addsd" return Intrinsic::x86_sse2_add_sd; // "__builtin_ia32_addsd"
case 's': // 1 string to match. case 's': // 1 string to match.
return Intrinsic::x86_sse_add_ss; // "__builtin_ia32_addss" return Intrinsic::x86_sse_add_ss; // "__builtin_ia32_addss"
} }
break; break;
case 'c': // 4 strings to match. case 'c': // 4 strings to match.
if (BuiltinName.substr(16, 2) != "mp") if (memcmp(BuiltinName.data()+16, "mp", 2))
break; break;
switch (BuiltinName[18]) { switch (BuiltinName[18]) {
default: break; default: break;
case 'p': // 2 strings to match. case 'p': // 2 strings to match.
switch (BuiltinName[19]) { switch (BuiltinName[19]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
return Intrinsic::x86_sse2_cmp_pd; // "__builtin_ia32_cmppd" return Intrinsic::x86_sse2_cmp_pd; // "__builtin_ia32_cmppd"
case 's': // 1 string to match. case 's': // 1 string to match.
return Intrinsic::x86_sse_cmp_ps; // "__builtin_ia32_cmpps" return Intrinsic::x86_sse_cmp_ps; // "__builtin_ia32_cmpps"
skipping to change at line 34730 skipping to change at line 39754
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
return Intrinsic::x86_sse2_cmp_sd; // "__builtin_ia32_cmpsd" return Intrinsic::x86_sse2_cmp_sd; // "__builtin_ia32_cmpsd"
case 's': // 1 string to match. case 's': // 1 string to match.
return Intrinsic::x86_sse_cmp_ss; // "__builtin_ia32_cmpss" return Intrinsic::x86_sse_cmp_ss; // "__builtin_ia32_cmpss"
} }
break; break;
} }
break; break;
case 'd': // 2 strings to match. case 'd': // 2 strings to match.
if (BuiltinName.substr(16, 3) != "ivs") if (memcmp(BuiltinName.data()+16, "ivs", 3))
break; break;
switch (BuiltinName[19]) { switch (BuiltinName[19]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
return Intrinsic::x86_sse2_div_sd; // "__builtin_ia32_divsd" return Intrinsic::x86_sse2_div_sd; // "__builtin_ia32_divsd"
case 's': // 1 string to match. case 's': // 1 string to match.
return Intrinsic::x86_sse_div_ss; // "__builtin_ia32_divss" return Intrinsic::x86_sse_div_ss; // "__builtin_ia32_divss"
} }
break; break;
case 'e': // 1 string to match.
if (memcmp(BuiltinName.data()+16, "xtrq", 4))
break;
return Intrinsic::x86_sse4a_extrq; // "__builtin_ia32_extrq"
case 'f': // 1 string to match. case 'f': // 1 string to match.
if (BuiltinName.substr(16, 4) != "emms") if (memcmp(BuiltinName.data()+16, "emms", 4))
break; break;
return Intrinsic::x86_mmx_femms; // "__builtin_ia32_femms" return Intrinsic::x86_mmx_femms; // "__builtin_ia32_femms"
case 'l': // 1 string to match. case 'l': // 1 string to match.
if (BuiltinName.substr(16, 4) != "ddqu") if (memcmp(BuiltinName.data()+16, "ddqu", 4))
break; break;
return Intrinsic::x86_sse3_ldu_dq; // "__builtin_ia32_lddqu" return Intrinsic::x86_sse3_ldu_dq; // "__builtin_ia32_lddqu"
case 'm': // 11 strings to match. case 'm': // 11 strings to match.
switch (BuiltinName[16]) { switch (BuiltinName[16]) {
default: break; default: break;
case 'a': // 4 strings to match. case 'a': // 4 strings to match.
if (BuiltinName[17] != 'x') if (BuiltinName[17] != 'x')
break; break;
switch (BuiltinName[18]) { switch (BuiltinName[18]) {
default: break; default: break;
skipping to change at line 34802 skipping to change at line 39830
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
return Intrinsic::x86_sse2_min_sd; // "__builtin_ia32_minsd" return Intrinsic::x86_sse2_min_sd; // "__builtin_ia32_minsd"
case 's': // 1 string to match. case 's': // 1 string to match.
return Intrinsic::x86_sse_min_ss; // "__builtin_ia32_minss" return Intrinsic::x86_sse_min_ss; // "__builtin_ia32_minss"
} }
break; break;
} }
break; break;
case 'u': // 2 strings to match. case 'u': // 2 strings to match.
if (BuiltinName.substr(17, 2) != "ls") if (memcmp(BuiltinName.data()+17, "ls", 2))
break; break;
switch (BuiltinName[19]) { switch (BuiltinName[19]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
return Intrinsic::x86_sse2_mul_sd; // "__builtin_ia32_mulsd" return Intrinsic::x86_sse2_mul_sd; // "__builtin_ia32_mulsd"
case 's': // 1 string to match. case 's': // 1 string to match.
return Intrinsic::x86_sse_mul_ss; // "__builtin_ia32_mulss" return Intrinsic::x86_sse_mul_ss; // "__builtin_ia32_mulss"
} }
break; break;
case 'w': // 1 string to match. case 'w': // 1 string to match.
if (BuiltinName.substr(17, 3) != "ait") if (memcmp(BuiltinName.data()+17, "ait", 3))
break; break;
return Intrinsic::x86_sse3_mwait; // "__builtin_ia32_mwait" return Intrinsic::x86_sse3_mwait; // "__builtin_ia32_mwait"
} }
break; break;
case 'p': // 33 strings to match. case 'p': // 33 strings to match.
switch (BuiltinName[16]) { switch (BuiltinName[16]) {
default: break; default: break;
case 'a': // 10 strings to match. case 'a': // 10 strings to match.
switch (BuiltinName[17]) { switch (BuiltinName[17]) {
default: break; default: break;
skipping to change at line 34853 skipping to change at line 39881
return Intrinsic::x86_mmx_padd_b; // "__builtin_ia32_paddb" return Intrinsic::x86_mmx_padd_b; // "__builtin_ia32_paddb"
case 'd': // 1 string to match. case 'd': // 1 string to match.
return Intrinsic::x86_mmx_padd_d; // "__builtin_ia32_paddd" return Intrinsic::x86_mmx_padd_d; // "__builtin_ia32_paddd"
case 'q': // 1 string to match. case 'q': // 1 string to match.
return Intrinsic::x86_mmx_padd_q; // "__builtin_ia32_paddq" return Intrinsic::x86_mmx_padd_q; // "__builtin_ia32_paddq"
case 'w': // 1 string to match. case 'w': // 1 string to match.
return Intrinsic::x86_mmx_padd_w; // "__builtin_ia32_paddw" return Intrinsic::x86_mmx_padd_w; // "__builtin_ia32_paddw"
} }
break; break;
case 'n': // 1 string to match. case 'n': // 1 string to match.
if (BuiltinName.substr(18, 2) != "dn") if (memcmp(BuiltinName.data()+18, "dn", 2))
break; break;
return Intrinsic::x86_mmx_pandn; // "__builtin_ia32_pandn" return Intrinsic::x86_mmx_pandn; // "__builtin_ia32_pandn"
case 'v': // 2 strings to match. case 'v': // 2 strings to match.
if (BuiltinName[18] != 'g') if (BuiltinName[18] != 'g')
break; break;
switch (BuiltinName[19]) { switch (BuiltinName[19]) {
default: break; default: break;
case 'b': // 1 string to match. case 'b': // 1 string to match.
return Intrinsic::x86_mmx_pavg_b; // "__builtin_ia32_pavgb" return Intrinsic::x86_mmx_pavg_b; // "__builtin_ia32_pavgb"
case 'w': // 1 string to match. case 'w': // 1 string to match.
skipping to change at line 34914 skipping to change at line 39942
if (BuiltinName[19] != 'n') if (BuiltinName[19] != 'n')
break; break;
return Intrinsic::x86_3dnow_pfmin; // "__builtin_ia32_pfmin" return Intrinsic::x86_3dnow_pfmin; // "__builtin_ia32_pfmin"
case 'u': // 1 string to match. case 'u': // 1 string to match.
if (BuiltinName[19] != 'l') if (BuiltinName[19] != 'l')
break; break;
return Intrinsic::x86_3dnow_pfmul; // "__builtin_ia32_pfmul" return Intrinsic::x86_3dnow_pfmul; // "__builtin_ia32_pfmul"
} }
break; break;
case 'r': // 1 string to match. case 'r': // 1 string to match.
if (BuiltinName.substr(18, 2) != "cp") if (memcmp(BuiltinName.data()+18, "cp", 2))
break; break;
return Intrinsic::x86_3dnow_pfrcp; // "__builtin_ia32_pfrcp" return Intrinsic::x86_3dnow_pfrcp; // "__builtin_ia32_pfrcp"
case 's': // 1 string to match. case 's': // 1 string to match.
if (BuiltinName.substr(18, 2) != "ub") if (memcmp(BuiltinName.data()+18, "ub", 2))
break; break;
return Intrinsic::x86_3dnow_pfsub; // "__builtin_ia32_pfsub" return Intrinsic::x86_3dnow_pfsub; // "__builtin_ia32_pfsub"
} }
break; break;
case 'i': // 2 strings to match. case 'i': // 2 strings to match.
if (BuiltinName.substr(17, 2) != "2f") if (memcmp(BuiltinName.data()+17, "2f", 2))
break; break;
switch (BuiltinName[19]) { switch (BuiltinName[19]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
return Intrinsic::x86_3dnow_pi2fd; // "__builtin_ia32_pi2fd" return Intrinsic::x86_3dnow_pi2fd; // "__builtin_ia32_pi2fd"
case 'w': // 1 string to match. case 'w': // 1 string to match.
return Intrinsic::x86_3dnowa_pi2fw; // "__builtin_ia32_pi2fw" return Intrinsic::x86_3dnowa_pi2fw; // "__builtin_ia32_pi2fw"
} }
break; break;
case 's': // 12 strings to match. case 's': // 12 strings to match.
skipping to change at line 34995 skipping to change at line 40023
return Intrinsic::x86_mmx_psub_q; // "__builtin_ia32_psubq" return Intrinsic::x86_mmx_psub_q; // "__builtin_ia32_psubq"
case 'w': // 1 string to match. case 'w': // 1 string to match.
return Intrinsic::x86_mmx_psub_w; // "__builtin_ia32_psubw" return Intrinsic::x86_mmx_psub_w; // "__builtin_ia32_psubw"
} }
break; break;
} }
break; break;
} }
break; break;
case 'r': // 2 strings to match. case 'r': // 2 strings to match.
if (BuiltinName.substr(16, 2) != "cp") if (memcmp(BuiltinName.data()+16, "cp", 2))
break; break;
switch (BuiltinName[18]) { switch (BuiltinName[18]) {
default: break; default: break;
case 'p': // 1 string to match. case 'p': // 1 string to match.
if (BuiltinName[19] != 's') if (BuiltinName[19] != 's')
break; break;
return Intrinsic::x86_sse_rcp_ps; // "__builtin_ia32_rcpps" return Intrinsic::x86_sse_rcp_ps; // "__builtin_ia32_rcpps"
case 's': // 1 string to match. case 's': // 1 string to match.
if (BuiltinName[19] != 's') if (BuiltinName[19] != 's')
break; break;
return Intrinsic::x86_sse_rcp_ss; // "__builtin_ia32_rcpss" return Intrinsic::x86_sse_rcp_ss; // "__builtin_ia32_rcpss"
} }
break; break;
case 's': // 2 strings to match. case 's': // 2 strings to match.
if (BuiltinName.substr(16, 3) != "ubs") if (memcmp(BuiltinName.data()+16, "ubs", 3))
break; break;
switch (BuiltinName[19]) { switch (BuiltinName[19]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
return Intrinsic::x86_sse2_sub_sd; // "__builtin_ia32_subsd" return Intrinsic::x86_sse2_sub_sd; // "__builtin_ia32_subsd"
case 's': // 1 string to match. case 's': // 1 string to match.
return Intrinsic::x86_sse_sub_ss; // "__builtin_ia32_subss" return Intrinsic::x86_sse_sub_ss; // "__builtin_ia32_subss"
} }
break; break;
} }
break; break;
case 21: // 47 strings to match. case 21: // 50 strings to match.
if (BuiltinName.substr(0, 15) != "__builtin_ia32_") if (memcmp(BuiltinName.data()+0, "__builtin_ia32_", 15))
break; break;
switch (BuiltinName[15]) { switch (BuiltinName[15]) {
default: break; default: break;
case 'c': // 5 strings to match. case 'c': // 5 strings to match.
if (BuiltinName.substr(16, 3) != "omi") if (memcmp(BuiltinName.data()+16, "omi", 3))
break; break;
switch (BuiltinName[19]) { switch (BuiltinName[19]) {
default: break; default: break;
case 'e': // 1 string to match. case 'e': // 1 string to match.
if (BuiltinName[20] != 'q') if (BuiltinName[20] != 'q')
break; break;
return Intrinsic::x86_sse_comieq_ss; // "__builtin_ia32_comieq" return Intrinsic::x86_sse_comieq_ss; // "__builtin_ia32_comieq"
case 'g': // 2 strings to match. case 'g': // 2 strings to match.
switch (BuiltinName[20]) { switch (BuiltinName[20]) {
default: break; default: break;
skipping to change at line 35056 skipping to change at line 40084
switch (BuiltinName[20]) { switch (BuiltinName[20]) {
default: break; default: break;
case 'e': // 1 string to match. case 'e': // 1 string to match.
return Intrinsic::x86_sse_comile_ss; // "__builtin_ia32_comile" return Intrinsic::x86_sse_comile_ss; // "__builtin_ia32_comile"
case 't': // 1 string to match. case 't': // 1 string to match.
return Intrinsic::x86_sse_comilt_ss; // "__builtin_ia32_comilt" return Intrinsic::x86_sse_comilt_ss; // "__builtin_ia32_comilt"
} }
break; break;
} }
break; break;
case 'e': // 1 string to match.
if (memcmp(BuiltinName.data()+16, "xtrqi", 5))
break;
return Intrinsic::x86_sse4a_extrqi; // "__builtin_ia32_extrqi"
case 'h': // 4 strings to match. case 'h': // 4 strings to match.
switch (BuiltinName[16]) { switch (BuiltinName[16]) {
default: break; default: break;
case 'a': // 2 strings to match. case 'a': // 2 strings to match.
if (BuiltinName.substr(17, 3) != "ddp") if (memcmp(BuiltinName.data()+17, "ddp", 3))
break; break;
switch (BuiltinName[20]) { switch (BuiltinName[20]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
return Intrinsic::x86_sse3_hadd_pd; // "__builtin_ia32_haddpd" return Intrinsic::x86_sse3_hadd_pd; // "__builtin_ia32_haddpd"
case 's': // 1 string to match. case 's': // 1 string to match.
return Intrinsic::x86_sse3_hadd_ps; // "__builtin_ia32_haddps" return Intrinsic::x86_sse3_hadd_ps; // "__builtin_ia32_haddps"
} }
break; break;
case 's': // 2 strings to match. case 's': // 2 strings to match.
if (BuiltinName.substr(17, 3) != "ubp") if (memcmp(BuiltinName.data()+17, "ubp", 3))
break; break;
switch (BuiltinName[20]) { switch (BuiltinName[20]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
return Intrinsic::x86_sse3_hsub_pd; // "__builtin_ia32_hsubpd" return Intrinsic::x86_sse3_hsub_pd; // "__builtin_ia32_hsubpd"
case 's': // 1 string to match. case 's': // 1 string to match.
return Intrinsic::x86_sse3_hsub_ps; // "__builtin_ia32_hsubps" return Intrinsic::x86_sse3_hsub_ps; // "__builtin_ia32_hsubps"
} }
break; break;
} }
break; break;
case 'l': // 1 string to match. case 'l': // 1 string to match.
if (BuiltinName.substr(16, 5) != "fence") if (memcmp(BuiltinName.data()+16, "fence", 5))
break; break;
return Intrinsic::x86_sse2_lfence; // "__builtin_ia32_lfence" return Intrinsic::x86_sse2_lfence; // "__builtin_ia32_lfence"
case 'm': // 2 strings to match. case 'm': // 2 strings to match.
switch (BuiltinName[16]) { switch (BuiltinName[16]) {
default: break; default: break;
case 'f': // 1 string to match. case 'f': // 1 string to match.
if (BuiltinName.substr(17, 4) != "ence") if (memcmp(BuiltinName.data()+17, "ence", 4))
break; break;
return Intrinsic::x86_sse2_mfence; // "__builtin_ia32_mfence" return Intrinsic::x86_sse2_mfence; // "__builtin_ia32_mfence"
case 'o': // 1 string to match. case 'o': // 1 string to match.
if (BuiltinName.substr(17, 4) != "vntq") if (memcmp(BuiltinName.data()+17, "vntq", 4))
break; break;
return Intrinsic::x86_mmx_movnt_dq; // "__builtin_ia32_movntq" return Intrinsic::x86_mmx_movnt_dq; // "__builtin_ia32_movntq"
} }
break; break;
case 'p': // 30 strings to match. case 'p': // 30 strings to match.
switch (BuiltinName[16]) { switch (BuiltinName[16]) {
default: break; default: break;
case 'a': // 2 strings to match. case 'a': // 2 strings to match.
if (BuiltinName.substr(17, 3) != "dds") if (memcmp(BuiltinName.data()+17, "dds", 3))
break; break;
switch (BuiltinName[20]) { switch (BuiltinName[20]) {
default: break; default: break;
case 'b': // 1 string to match. case 'b': // 1 string to match.
return Intrinsic::x86_mmx_padds_b; // "__builtin_ia32_paddsb" return Intrinsic::x86_mmx_padds_b; // "__builtin_ia32_paddsb"
case 'w': // 1 string to match. case 'w': // 1 string to match.
return Intrinsic::x86_mmx_padds_w; // "__builtin_ia32_paddsw" return Intrinsic::x86_mmx_padds_w; // "__builtin_ia32_paddsw"
} }
break; break;
case 'f': // 2 strings to match. case 'f': // 2 strings to match.
switch (BuiltinName[17]) { switch (BuiltinName[17]) {
default: break; default: break;
case 'n': // 1 string to match. case 'n': // 1 string to match.
if (BuiltinName.substr(18, 3) != "acc") if (memcmp(BuiltinName.data()+18, "acc", 3))
break; break;
return Intrinsic::x86_3dnowa_pfnacc; // "__builtin_ia32_pfnacc" return Intrinsic::x86_3dnowa_pfnacc; // "__builtin_ia32_pfnacc"
case 's': // 1 string to match. case 's': // 1 string to match.
if (BuiltinName.substr(18, 3) != "ubr") if (memcmp(BuiltinName.data()+18, "ubr", 3))
break; break;
return Intrinsic::x86_3dnow_pfsubr; // "__builtin_ia32_pfsubr" return Intrinsic::x86_3dnow_pfsubr; // "__builtin_ia32_pfsubr"
} }
break; break;
case 'h': // 4 strings to match. case 'h': // 4 strings to match.
switch (BuiltinName[17]) { switch (BuiltinName[17]) {
default: break; default: break;
case 'a': // 2 strings to match. case 'a': // 2 strings to match.
if (BuiltinName.substr(18, 2) != "dd") if (memcmp(BuiltinName.data()+18, "dd", 2))
break; break;
switch (BuiltinName[20]) { switch (BuiltinName[20]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
return Intrinsic::x86_ssse3_phadd_d; // "__builtin_ia32_ phaddd" return Intrinsic::x86_ssse3_phadd_d; // "__builtin_ia32_ phaddd"
case 'w': // 1 string to match. case 'w': // 1 string to match.
return Intrinsic::x86_ssse3_phadd_w; // "__builtin_ia32_ phaddw" return Intrinsic::x86_ssse3_phadd_w; // "__builtin_ia32_ phaddw"
} }
break; break;
case 's': // 2 strings to match. case 's': // 2 strings to match.
if (BuiltinName.substr(18, 2) != "ub") if (memcmp(BuiltinName.data()+18, "ub", 2))
break; break;
switch (BuiltinName[20]) { switch (BuiltinName[20]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
return Intrinsic::x86_ssse3_phsub_d; // "__builtin_ia32_ phsubd" return Intrinsic::x86_ssse3_phsub_d; // "__builtin_ia32_ phsubd"
case 'w': // 1 string to match. case 'w': // 1 string to match.
return Intrinsic::x86_ssse3_phsub_w; // "__builtin_ia32_ phsubw" return Intrinsic::x86_ssse3_phsub_w; // "__builtin_ia32_ phsubw"
} }
break; break;
} }
skipping to change at line 35208 skipping to change at line 40240
break; break;
return Intrinsic::x86_mmx_pmull_w; // "__builtin_ia32_pmullw" return Intrinsic::x86_mmx_pmull_w; // "__builtin_ia32_pmullw"
} }
break; break;
} }
break; break;
case 's': // 16 strings to match. case 's': // 16 strings to match.
switch (BuiltinName[17]) { switch (BuiltinName[17]) {
default: break; default: break;
case 'a': // 1 string to match. case 'a': // 1 string to match.
if (BuiltinName.substr(18, 3) != "dbw") if (memcmp(BuiltinName.data()+18, "dbw", 3))
break; break;
return Intrinsic::x86_mmx_psad_bw; // "__builtin_ia32_psadbw" return Intrinsic::x86_mmx_psad_bw; // "__builtin_ia32_psadbw"
case 'h': // 2 strings to match. case 'h': // 2 strings to match.
if (BuiltinName.substr(18, 2) != "uf") if (memcmp(BuiltinName.data()+18, "uf", 2))
break; break;
switch (BuiltinName[20]) { switch (BuiltinName[20]) {
default: break; default: break;
case 'b': // 1 string to match. case 'b': // 1 string to match.
return Intrinsic::x86_ssse3_pshuf_b; // "__builtin_ia32_ pshufb" return Intrinsic::x86_ssse3_pshuf_b; // "__builtin_ia32_ pshufb"
case 'w': // 1 string to match. case 'w': // 1 string to match.
return Intrinsic::x86_sse_pshuf_w; // "__builtin_ia32_pshufw" return Intrinsic::x86_sse_pshuf_w; // "__builtin_ia32_pshufw"
} }
break; break;
case 'i': // 3 strings to match. case 'i': // 3 strings to match.
if (BuiltinName.substr(18, 2) != "gn") if (memcmp(BuiltinName.data()+18, "gn", 2))
break; break;
switch (BuiltinName[20]) { switch (BuiltinName[20]) {
default: break; default: break;
case 'b': // 1 string to match. case 'b': // 1 string to match.
return Intrinsic::x86_ssse3_psign_b; // "__builtin_ia32_ psignb" return Intrinsic::x86_ssse3_psign_b; // "__builtin_ia32_ psignb"
case 'd': // 1 string to match. case 'd': // 1 string to match.
return Intrinsic::x86_ssse3_psign_d; // "__builtin_ia32_ psignd" return Intrinsic::x86_ssse3_psign_d; // "__builtin_ia32_ psignd"
case 'w': // 1 string to match. case 'w': // 1 string to match.
return Intrinsic::x86_ssse3_psign_w; // "__builtin_ia32_ psignw" return Intrinsic::x86_ssse3_psign_w; // "__builtin_ia32_ psignw"
} }
skipping to change at line 35290 skipping to change at line 40322
return Intrinsic::x86_mmx_psrli_q; // "__builtin_ia32_ psrlqi" return Intrinsic::x86_mmx_psrli_q; // "__builtin_ia32_ psrlqi"
case 'w': // 1 string to match. case 'w': // 1 string to match.
if (BuiltinName[20] != 'i') if (BuiltinName[20] != 'i')
break; break;
return Intrinsic::x86_mmx_psrli_w; // "__builtin_ia32_ psrlwi" return Intrinsic::x86_mmx_psrli_w; // "__builtin_ia32_ psrlwi"
} }
break; break;
} }
break; break;
case 'u': // 2 strings to match. case 'u': // 2 strings to match.
if (BuiltinName.substr(18, 2) != "bs") if (memcmp(BuiltinName.data()+18, "bs", 2))
break; break;
switch (BuiltinName[20]) { switch (BuiltinName[20]) {
default: break; default: break;
case 'b': // 1 string to match. case 'b': // 1 string to match.
return Intrinsic::x86_mmx_psubs_b; // "__builtin_ia32_psubsb" return Intrinsic::x86_mmx_psubs_b; // "__builtin_ia32_psubsb"
case 'w': // 1 string to match. case 'w': // 1 string to match.
return Intrinsic::x86_mmx_psubs_w; // "__builtin_ia32_psubsw" return Intrinsic::x86_mmx_psubs_w; // "__builtin_ia32_psubsw"
} }
break; break;
} }
break; break;
} }
break; break;
case 's': // 5 strings to match. case 's': // 5 strings to match.
switch (BuiltinName[16]) { switch (BuiltinName[16]) {
default: break; default: break;
case 'f': // 1 string to match. case 'f': // 1 string to match.
if (BuiltinName.substr(17, 4) != "ence") if (memcmp(BuiltinName.data()+17, "ence", 4))
break; break;
return Intrinsic::x86_sse_sfence; // "__builtin_ia32_sfence" return Intrinsic::x86_sse_sfence; // "__builtin_ia32_sfence"
case 'q': // 4 strings to match. case 'q': // 4 strings to match.
if (BuiltinName.substr(17, 2) != "rt") if (memcmp(BuiltinName.data()+17, "rt", 2))
break; break;
switch (BuiltinName[19]) { switch (BuiltinName[19]) {
default: break; default: break;
case 'p': // 2 strings to match. case 'p': // 2 strings to match.
switch (BuiltinName[20]) { switch (BuiltinName[20]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
return Intrinsic::x86_sse2_sqrt_pd; // "__builtin_ia32_ sqrtpd" return Intrinsic::x86_sse2_sqrt_pd; // "__builtin_ia32_ sqrtpd"
case 's': // 1 string to match. case 's': // 1 string to match.
return Intrinsic::x86_sse_sqrt_ps; // "__builtin_ia32_sqrtps" return Intrinsic::x86_sse_sqrt_ps; // "__builtin_ia32_sqrtps"
skipping to change at line 35338 skipping to change at line 40370
case 'd': // 1 string to match. case 'd': // 1 string to match.
return Intrinsic::x86_sse2_sqrt_sd; // "__builtin_ia32_ sqrtsd" return Intrinsic::x86_sse2_sqrt_sd; // "__builtin_ia32_ sqrtsd"
case 's': // 1 string to match. case 's': // 1 string to match.
return Intrinsic::x86_sse_sqrt_ss; // "__builtin_ia32_sqrtss" return Intrinsic::x86_sse_sqrt_ss; // "__builtin_ia32_sqrtss"
} }
break; break;
} }
break; break;
} }
break; break;
case 'x': // 2 strings to match.
switch (BuiltinName[16]) {
default: break;
case 'a': // 1 string to match.
if (memcmp(BuiltinName.data()+17, "bort", 4))
break;
return Intrinsic::x86_xabort; // "__builtin_ia32_xabort"
case 'b': // 1 string to match.
if (memcmp(BuiltinName.data()+17, "egin", 4))
break;
return Intrinsic::x86_xbegin; // "__builtin_ia32_xbegin"
}
break;
} }
break; break;
case 22: // 50 strings to match. case 22: // 53 strings to match.
if (BuiltinName.substr(0, 15) != "__builtin_ia32_") if (memcmp(BuiltinName.data()+0, "__builtin_ia32_", 15))
break; break;
switch (BuiltinName[15]) { switch (BuiltinName[15]) {
default: break; default: break;
case 'b': // 4 strings to match. case 'b': // 4 strings to match.
switch (BuiltinName[16]) { switch (BuiltinName[16]) {
default: break; default: break;
case 'l': // 2 strings to match. case 'l': // 2 strings to match.
if (BuiltinName.substr(17, 4) != "endp") if (memcmp(BuiltinName.data()+17, "endp", 4))
break; break;
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
return Intrinsic::x86_sse41_blendpd; // "__builtin_ia32_blendpd" return Intrinsic::x86_sse41_blendpd; // "__builtin_ia32_blendpd"
case 's': // 1 string to match. case 's': // 1 string to match.
return Intrinsic::x86_sse41_blendps; // "__builtin_ia32_blendps" return Intrinsic::x86_sse41_blendps; // "__builtin_ia32_blendps"
} }
break; break;
case 'z': // 2 strings to match. case 'z': // 2 strings to match.
if (BuiltinName.substr(17, 3) != "hi_") if (memcmp(BuiltinName.data()+17, "hi_", 3))
break; break;
switch (BuiltinName[20]) { switch (BuiltinName[20]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
if (BuiltinName[21] != 'i') if (BuiltinName[21] != 'i')
break; break;
return Intrinsic::x86_bmi_bzhi_64; // "__builtin_ia32_bzhi_di" return Intrinsic::x86_bmi_bzhi_64; // "__builtin_ia32_bzhi_di"
case 's': // 1 string to match. case 's': // 1 string to match.
if (BuiltinName[21] != 'i') if (BuiltinName[21] != 'i')
break; break;
return Intrinsic::x86_bmi_bzhi_32; // "__builtin_ia32_bzhi_si" return Intrinsic::x86_bmi_bzhi_32; // "__builtin_ia32_bzhi_si"
} }
break; break;
} }
break; break;
case 'c': // 6 strings to match. case 'c': // 6 strings to match.
switch (BuiltinName[16]) { switch (BuiltinName[16]) {
default: break; default: break;
case 'l': // 1 string to match. case 'l': // 1 string to match.
if (BuiltinName.substr(17, 5) != "flush") if (memcmp(BuiltinName.data()+17, "flush", 5))
break; break;
return Intrinsic::x86_sse2_clflush; // "__builtin_ia32_clflush" return Intrinsic::x86_sse2_clflush; // "__builtin_ia32_clflush"
case 'o': // 1 string to match. case 'o': // 1 string to match.
if (BuiltinName.substr(17, 5) != "mineq") if (memcmp(BuiltinName.data()+17, "mineq", 5))
break; break;
return Intrinsic::x86_sse_comineq_ss; // "__builtin_ia32_comineq" return Intrinsic::x86_sse_comineq_ss; // "__builtin_ia32_comineq"
case 'r': // 4 strings to match. case 'r': // 4 strings to match.
if (BuiltinName.substr(17, 3) != "c32") if (memcmp(BuiltinName.data()+17, "c32", 3))
break; break;
switch (BuiltinName[20]) { switch (BuiltinName[20]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
if (BuiltinName[21] != 'i') if (BuiltinName[21] != 'i')
break; break;
return Intrinsic::x86_sse42_crc32_64_64; // "__builtin_ia32_ crc32di" return Intrinsic::x86_sse42_crc32_64_64; // "__builtin_ia32_ crc32di"
case 'h': // 1 string to match. case 'h': // 1 string to match.
if (BuiltinName[21] != 'i') if (BuiltinName[21] != 'i')
break; break;
skipping to change at line 35413 skipping to change at line 40458
return Intrinsic::x86_sse42_crc32_32_8; // "__builtin_ia32_ crc32qi" return Intrinsic::x86_sse42_crc32_32_8; // "__builtin_ia32_ crc32qi"
case 's': // 1 string to match. case 's': // 1 string to match.
if (BuiltinName[21] != 'i') if (BuiltinName[21] != 'i')
break; break;
return Intrinsic::x86_sse42_crc32_32_32; // "__builtin_ia32_ crc32si" return Intrinsic::x86_sse42_crc32_32_32; // "__builtin_ia32_ crc32si"
} }
break; break;
} }
break; break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
if (BuiltinName.substr(16, 6) != "pps256") if (memcmp(BuiltinName.data()+16, "pps256", 6))
break; break;
return Intrinsic::x86_avx_dp_ps_256; // "__builtin_ia32_dpps256" return Intrinsic::x86_avx_dp_ps_256; // "__builtin_ia32_dpps256"
case 'm': // 1 string to match. case 'i': // 1 string to match.
if (BuiltinName.substr(16, 6) != "onitor") if (memcmp(BuiltinName.data()+16, "nsertq", 6))
break;
return Intrinsic::x86_sse4a_insertq; // "__builtin_ia32_insertq"
case 'm': // 3 strings to match.
if (BuiltinName[16] != 'o')
break;
switch (BuiltinName[17]) {
default: break;
case 'n': // 1 string to match.
if (memcmp(BuiltinName.data()+18, "itor", 4))
break;
return Intrinsic::x86_sse3_monitor; // "__builtin_ia32_monitor"
case 'v': // 2 strings to match.
if (memcmp(BuiltinName.data()+18, "nts", 3))
break;
switch (BuiltinName[21]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::x86_sse4a_movnt_sd; // "__builtin_ia32_
movntsd"
case 's': // 1 string to match.
return Intrinsic::x86_sse4a_movnt_ss; // "__builtin_ia32_
movntss"
}
break; break;
return Intrinsic::x86_sse3_monitor; // "__builtin_ia32_monitor" }
break;
case 'p': // 27 strings to match. case 'p': // 27 strings to match.
switch (BuiltinName[16]) { switch (BuiltinName[16]) {
default: break; default: break;
case 'a': // 4 strings to match. case 'a': // 4 strings to match.
switch (BuiltinName[17]) { switch (BuiltinName[17]) {
default: break; default: break;
case 'd': // 2 strings to match. case 'd': // 2 strings to match.
if (BuiltinName.substr(18, 3) != "dus") if (memcmp(BuiltinName.data()+18, "dus", 3))
break; break;
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case 'b': // 1 string to match. case 'b': // 1 string to match.
return Intrinsic::x86_mmx_paddus_b; // "__builtin_ia32_ paddusb" return Intrinsic::x86_mmx_paddus_b; // "__builtin_ia32_ paddusb"
case 'w': // 1 string to match. case 'w': // 1 string to match.
return Intrinsic::x86_mmx_paddus_w; // "__builtin_ia32_ paddusw" return Intrinsic::x86_mmx_paddus_w; // "__builtin_ia32_ paddusw"
} }
break; break;
case 'l': // 1 string to match. case 'l': // 1 string to match.
if (BuiltinName.substr(18, 4) != "ignr") if (memcmp(BuiltinName.data()+18, "ignr", 4))
break; break;
return Intrinsic::x86_mmx_palignr_b; // "__builtin_ia32_palignr" return Intrinsic::x86_mmx_palignr_b; // "__builtin_ia32_palignr"
case 'v': // 1 string to match. case 'v': // 1 string to match.
if (BuiltinName.substr(18, 4) != "gusb") if (memcmp(BuiltinName.data()+18, "gusb", 4))
break; break;
return Intrinsic::x86_3dnow_pavgusb; // "__builtin_ia32_pavgusb" return Intrinsic::x86_3dnow_pavgusb; // "__builtin_ia32_pavgusb"
} }
break; break;
case 'c': // 6 strings to match. case 'c': // 6 strings to match.
if (BuiltinName.substr(17, 2) != "mp") if (memcmp(BuiltinName.data()+17, "mp", 2))
break; break;
switch (BuiltinName[19]) { switch (BuiltinName[19]) {
default: break; default: break;
case 'e': // 3 strings to match. case 'e': // 3 strings to match.
if (BuiltinName[20] != 'q') if (BuiltinName[20] != 'q')
break; break;
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case 'b': // 1 string to match. case 'b': // 1 string to match.
return Intrinsic::x86_mmx_pcmpeq_b; // "__builtin_ia32_ pcmpeqb" return Intrinsic::x86_mmx_pcmpeq_b; // "__builtin_ia32_ pcmpeqb"
skipping to change at line 35481 skipping to change at line 40548
return Intrinsic::x86_mmx_pcmpgt_b; // "__builtin_ia32_ pcmpgtb" return Intrinsic::x86_mmx_pcmpgt_b; // "__builtin_ia32_ pcmpgtb"
case 'd': // 1 string to match. case 'd': // 1 string to match.
return Intrinsic::x86_mmx_pcmpgt_d; // "__builtin_ia32_ pcmpgtd" return Intrinsic::x86_mmx_pcmpgt_d; // "__builtin_ia32_ pcmpgtd"
case 'w': // 1 string to match. case 'w': // 1 string to match.
return Intrinsic::x86_mmx_pcmpgt_w; // "__builtin_ia32_ pcmpgtw" return Intrinsic::x86_mmx_pcmpgt_w; // "__builtin_ia32_ pcmpgtw"
} }
break; break;
} }
break; break;
case 'd': // 2 strings to match. case 'd': // 2 strings to match.
if (BuiltinName.substr(17, 3) != "ep_") if (memcmp(BuiltinName.data()+17, "ep_", 3))
break; break;
switch (BuiltinName[20]) { switch (BuiltinName[20]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
if (BuiltinName[21] != 'i') if (BuiltinName[21] != 'i')
break; break;
return Intrinsic::x86_bmi_pdep_64; // "__builtin_ia32_pdep_di" return Intrinsic::x86_bmi_pdep_64; // "__builtin_ia32_pdep_di"
case 's': // 1 string to match. case 's': // 1 string to match.
if (BuiltinName[21] != 'i') if (BuiltinName[21] != 'i')
break; break;
return Intrinsic::x86_bmi_pdep_32; // "__builtin_ia32_pdep_si" return Intrinsic::x86_bmi_pdep_32; // "__builtin_ia32_pdep_si"
} }
break; break;
case 'e': // 2 strings to match. case 'e': // 2 strings to match.
if (BuiltinName.substr(17, 3) != "xt_") if (memcmp(BuiltinName.data()+17, "xt_", 3))
break; break;
switch (BuiltinName[20]) { switch (BuiltinName[20]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
if (BuiltinName[21] != 'i') if (BuiltinName[21] != 'i')
break; break;
return Intrinsic::x86_bmi_pext_64; // "__builtin_ia32_pext_di" return Intrinsic::x86_bmi_pext_64; // "__builtin_ia32_pext_di"
case 's': // 1 string to match. case 's': // 1 string to match.
if (BuiltinName[21] != 'i') if (BuiltinName[21] != 'i')
break; break;
return Intrinsic::x86_bmi_pext_32; // "__builtin_ia32_pext_si" return Intrinsic::x86_bmi_pext_32; // "__builtin_ia32_pext_si"
} }
break; break;
case 'f': // 5 strings to match. case 'f': // 5 strings to match.
switch (BuiltinName[17]) { switch (BuiltinName[17]) {
default: break; default: break;
case 'c': // 3 strings to match. case 'c': // 3 strings to match.
if (BuiltinName.substr(18, 2) != "mp") if (memcmp(BuiltinName.data()+18, "mp", 2))
break; break;
switch (BuiltinName[20]) { switch (BuiltinName[20]) {
default: break; default: break;
case 'e': // 1 string to match. case 'e': // 1 string to match.
if (BuiltinName[21] != 'q') if (BuiltinName[21] != 'q')
break; break;
return Intrinsic::x86_3dnow_pfcmpeq; // "__builtin_ia32_ pfcmpeq" return Intrinsic::x86_3dnow_pfcmpeq; // "__builtin_ia32_ pfcmpeq"
case 'g': // 2 strings to match. case 'g': // 2 strings to match.
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case 'e': // 1 string to match. case 'e': // 1 string to match.
return Intrinsic::x86_3dnow_pfcmpge; // "__builtin_ia32_ pfcmpge" return Intrinsic::x86_3dnow_pfcmpge; // "__builtin_ia32_ pfcmpge"
case 't': // 1 string to match. case 't': // 1 string to match.
return Intrinsic::x86_3dnow_pfcmpgt; // "__builtin_ia32_ pfcmpgt" return Intrinsic::x86_3dnow_pfcmpgt; // "__builtin_ia32_ pfcmpgt"
} }
break; break;
} }
break; break;
case 'p': // 1 string to match. case 'p': // 1 string to match.
if (BuiltinName.substr(18, 4) != "nacc") if (memcmp(BuiltinName.data()+18, "nacc", 4))
break; break;
return Intrinsic::x86_3dnowa_pfpnacc; // "__builtin_ia32_ pfpnacc" return Intrinsic::x86_3dnowa_pfpnacc; // "__builtin_ia32_ pfpnacc"
case 'r': // 1 string to match. case 'r': // 1 string to match.
if (BuiltinName.substr(18, 4) != "sqrt") if (memcmp(BuiltinName.data()+18, "sqrt", 4))
break; break;
return Intrinsic::x86_3dnow_pfrsqrt; // "__builtin_ia32_pfrsqrt" return Intrinsic::x86_3dnow_pfrsqrt; // "__builtin_ia32_pfrsqrt"
} }
break; break;
case 'h': // 2 strings to match. case 'h': // 2 strings to match.
switch (BuiltinName[17]) { switch (BuiltinName[17]) {
default: break; default: break;
case 'a': // 1 string to match. case 'a': // 1 string to match.
if (BuiltinName.substr(18, 4) != "ddsw") if (memcmp(BuiltinName.data()+18, "ddsw", 4))
break; break;
return Intrinsic::x86_ssse3_phadd_sw; // "__builtin_ia32_ phaddsw" return Intrinsic::x86_ssse3_phadd_sw; // "__builtin_ia32_ phaddsw"
case 's': // 1 string to match. case 's': // 1 string to match.
if (BuiltinName.substr(18, 4) != "ubsw") if (memcmp(BuiltinName.data()+18, "ubsw", 4))
break; break;
return Intrinsic::x86_ssse3_phsub_sw; // "__builtin_ia32_ phsubsw" return Intrinsic::x86_ssse3_phsub_sw; // "__builtin_ia32_ phsubsw"
} }
break; break;
case 'm': // 4 strings to match. case 'm': // 4 strings to match.
switch (BuiltinName[17]) { switch (BuiltinName[17]) {
default: break; default: break;
case 'a': // 1 string to match. case 'a': // 1 string to match.
if (BuiltinName.substr(18, 4) != "ddwd") if (memcmp(BuiltinName.data()+18, "ddwd", 4))
break; break;
return Intrinsic::x86_mmx_pmadd_wd; // "__builtin_ia32_pmaddwd" return Intrinsic::x86_mmx_pmadd_wd; // "__builtin_ia32_pmaddwd"
case 'u': // 3 strings to match. case 'u': // 3 strings to match.
if (BuiltinName[18] != 'l') if (BuiltinName[18] != 'l')
break; break;
switch (BuiltinName[19]) { switch (BuiltinName[19]) {
default: break; default: break;
case 'h': // 2 strings to match. case 'h': // 2 strings to match.
switch (BuiltinName[20]) { switch (BuiltinName[20]) {
default: break; default: break;
skipping to change at line 35582 skipping to change at line 40649
if (BuiltinName[21] != 'w') if (BuiltinName[21] != 'w')
break; break;
return Intrinsic::x86_3dnow_pmulhrw; // "__builtin_ia32_ pmulhrw" return Intrinsic::x86_3dnow_pmulhrw; // "__builtin_ia32_ pmulhrw"
case 'u': // 1 string to match. case 'u': // 1 string to match.
if (BuiltinName[21] != 'w') if (BuiltinName[21] != 'w')
break; break;
return Intrinsic::x86_mmx_pmulhu_w; // "__builtin_ia32_ pmulhuw" return Intrinsic::x86_mmx_pmulhu_w; // "__builtin_ia32_ pmulhuw"
} }
break; break;
case 'u': // 1 string to match. case 'u': // 1 string to match.
if (BuiltinName.substr(20, 2) != "dq") if (memcmp(BuiltinName.data()+20, "dq", 2))
break; break;
return Intrinsic::x86_mmx_pmulu_dq; // "__builtin_ia32_ pmuludq" return Intrinsic::x86_mmx_pmulu_dq; // "__builtin_ia32_ pmuludq"
} }
break; break;
} }
break; break;
case 's': // 2 strings to match. case 's': // 2 strings to match.
if (BuiltinName.substr(17, 4) != "ubus") if (memcmp(BuiltinName.data()+17, "ubus", 4))
break; break;
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case 'b': // 1 string to match. case 'b': // 1 string to match.
return Intrinsic::x86_mmx_psubus_b; // "__builtin_ia32_psubusb" return Intrinsic::x86_mmx_psubus_b; // "__builtin_ia32_psubusb"
case 'w': // 1 string to match. case 'w': // 1 string to match.
return Intrinsic::x86_mmx_psubus_w; // "__builtin_ia32_psubusw" return Intrinsic::x86_mmx_psubus_w; // "__builtin_ia32_psubusw"
} }
break; break;
} }
break; break;
case 'r': // 6 strings to match. case 'r': // 6 strings to match.
switch (BuiltinName[16]) { switch (BuiltinName[16]) {
default: break; default: break;
case 'o': // 4 strings to match. case 'o': // 4 strings to match.
if (BuiltinName.substr(17, 3) != "und") if (memcmp(BuiltinName.data()+17, "und", 3))
break; break;
switch (BuiltinName[20]) { switch (BuiltinName[20]) {
default: break; default: break;
case 'p': // 2 strings to match. case 'p': // 2 strings to match.
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
return Intrinsic::x86_sse41_round_pd; // "__builtin_ia32_ roundpd" return Intrinsic::x86_sse41_round_pd; // "__builtin_ia32_ roundpd"
case 's': // 1 string to match. case 's': // 1 string to match.
return Intrinsic::x86_sse41_round_ps; // "__builtin_ia32_ roundps" return Intrinsic::x86_sse41_round_ps; // "__builtin_ia32_ roundps"
skipping to change at line 35631 skipping to change at line 40698
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
return Intrinsic::x86_sse41_round_sd; // "__builtin_ia32_ roundsd" return Intrinsic::x86_sse41_round_sd; // "__builtin_ia32_ roundsd"
case 's': // 1 string to match. case 's': // 1 string to match.
return Intrinsic::x86_sse41_round_ss; // "__builtin_ia32_ roundss" return Intrinsic::x86_sse41_round_ss; // "__builtin_ia32_ roundss"
} }
break; break;
} }
break; break;
case 's': // 2 strings to match. case 's': // 2 strings to match.
if (BuiltinName.substr(17, 3) != "qrt") if (memcmp(BuiltinName.data()+17, "qrt", 3))
break; break;
switch (BuiltinName[20]) { switch (BuiltinName[20]) {
default: break; default: break;
case 'p': // 1 string to match. case 'p': // 1 string to match.
if (BuiltinName[21] != 's') if (BuiltinName[21] != 's')
break; break;
return Intrinsic::x86_sse_rsqrt_ps; // "__builtin_ia32_rsqrtps" return Intrinsic::x86_sse_rsqrt_ps; // "__builtin_ia32_rsqrtps"
case 's': // 1 string to match. case 's': // 1 string to match.
if (BuiltinName[21] != 's') if (BuiltinName[21] != 's')
break; break;
return Intrinsic::x86_sse_rsqrt_ss; // "__builtin_ia32_rsqrtss" return Intrinsic::x86_sse_rsqrt_ss; // "__builtin_ia32_rsqrtss"
} }
break; break;
} }
break; break;
case 'u': // 5 strings to match. case 'u': // 5 strings to match.
if (BuiltinName.substr(16, 4) != "comi") if (memcmp(BuiltinName.data()+16, "comi", 4))
break; break;
switch (BuiltinName[20]) { switch (BuiltinName[20]) {
default: break; default: break;
case 'e': // 1 string to match. case 'e': // 1 string to match.
if (BuiltinName[21] != 'q') if (BuiltinName[21] != 'q')
break; break;
return Intrinsic::x86_sse_ucomieq_ss; // "__builtin_ia32_ucomieq" return Intrinsic::x86_sse_ucomieq_ss; // "__builtin_ia32_ucomieq"
case 'g': // 2 strings to match. case 'g': // 2 strings to match.
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
skipping to change at line 35678 skipping to change at line 40745
case 'e': // 1 string to match. case 'e': // 1 string to match.
return Intrinsic::x86_sse_ucomile_ss; // "__builtin_ia32_ ucomile" return Intrinsic::x86_sse_ucomile_ss; // "__builtin_ia32_ ucomile"
case 't': // 1 string to match. case 't': // 1 string to match.
return Intrinsic::x86_sse_ucomilt_ss; // "__builtin_ia32_ ucomilt" return Intrinsic::x86_sse_ucomilt_ss; // "__builtin_ia32_ ucomilt"
} }
break; break;
} }
break; break;
} }
break; break;
case 23: // 98 strings to match. case 23: // 99 strings to match.
if (BuiltinName.substr(0, 15) != "__builtin_ia32_") if (memcmp(BuiltinName.data()+0, "__builtin_ia32_", 15))
break; break;
switch (BuiltinName[15]) { switch (BuiltinName[15]) {
default: break; default: break;
case 'a': // 2 strings to match. case 'a': // 2 strings to match.
if (BuiltinName.substr(16, 6) != "ddsubp") if (memcmp(BuiltinName.data()+16, "ddsubp", 6))
break; break;
switch (BuiltinName[22]) { switch (BuiltinName[22]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
return Intrinsic::x86_sse3_addsub_pd; // "__builtin_ia32_addsubpd " return Intrinsic::x86_sse3_addsub_pd; // "__builtin_ia32_addsubpd "
case 's': // 1 string to match. case 's': // 1 string to match.
return Intrinsic::x86_sse3_addsub_ps; // "__builtin_ia32_addsubps " return Intrinsic::x86_sse3_addsub_ps; // "__builtin_ia32_addsubps "
} }
break; break;
case 'b': // 2 strings to match. case 'b': // 2 strings to match.
if (BuiltinName.substr(16, 6) != "lendvp") if (memcmp(BuiltinName.data()+16, "lendvp", 6))
break; break;
switch (BuiltinName[22]) { switch (BuiltinName[22]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
return Intrinsic::x86_sse41_blendvpd; // "__builtin_ia32_blendvpd " return Intrinsic::x86_sse41_blendvpd; // "__builtin_ia32_blendvpd "
case 's': // 1 string to match. case 's': // 1 string to match.
return Intrinsic::x86_sse41_blendvps; // "__builtin_ia32_blendvps " return Intrinsic::x86_sse41_blendvps; // "__builtin_ia32_blendvps "
} }
break; break;
case 'c': // 23 strings to match. case 'c': // 23 strings to match.
switch (BuiltinName[16]) { switch (BuiltinName[16]) {
default: break; default: break;
case 'm': // 2 strings to match. case 'm': // 2 strings to match.
if (BuiltinName.substr(17, 2) != "pp") if (memcmp(BuiltinName.data()+17, "pp", 2))
break; break;
switch (BuiltinName[19]) { switch (BuiltinName[19]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
if (BuiltinName.substr(20, 3) != "256") if (memcmp(BuiltinName.data()+20, "256", 3))
break; break;
return Intrinsic::x86_avx_cmp_pd_256; // "__builtin_ia32_ cmppd256" return Intrinsic::x86_avx_cmp_pd_256; // "__builtin_ia32_ cmppd256"
case 's': // 1 string to match. case 's': // 1 string to match.
if (BuiltinName.substr(20, 3) != "256") if (memcmp(BuiltinName.data()+20, "256", 3))
break; break;
return Intrinsic::x86_avx_cmp_ps_256; // "__builtin_ia32_ cmpps256" return Intrinsic::x86_avx_cmp_ps_256; // "__builtin_ia32_ cmpps256"
} }
break; break;
case 'o': // 5 strings to match. case 'o': // 5 strings to match.
if (BuiltinName.substr(17, 4) != "misd") if (memcmp(BuiltinName.data()+17, "misd", 4))
break; break;
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case 'e': // 1 string to match. case 'e': // 1 string to match.
if (BuiltinName[22] != 'q') if (BuiltinName[22] != 'q')
break; break;
return Intrinsic::x86_sse2_comieq_sd; // "__builtin_ia32_ comisdeq" return Intrinsic::x86_sse2_comieq_sd; // "__builtin_ia32_ comisdeq"
case 'g': // 2 strings to match. case 'g': // 2 strings to match.
switch (BuiltinName[22]) { switch (BuiltinName[22]) {
default: break; default: break;
skipping to change at line 35758 skipping to change at line 40825
} }
break; break;
} }
break; break;
case 'v': // 16 strings to match. case 'v': // 16 strings to match.
if (BuiltinName[17] != 't') if (BuiltinName[17] != 't')
break; break;
switch (BuiltinName[18]) { switch (BuiltinName[18]) {
default: break; default: break;
case 'd': // 2 strings to match. case 'd': // 2 strings to match.
if (BuiltinName.substr(19, 3) != "q2p") if (memcmp(BuiltinName.data()+19, "q2p", 3))
break; break;
switch (BuiltinName[22]) { switch (BuiltinName[22]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
return Intrinsic::x86_sse2_cvtdq2pd; // "__builtin_ia32_ cvtdq2pd" return Intrinsic::x86_sse2_cvtdq2pd; // "__builtin_ia32_ cvtdq2pd"
case 's': // 1 string to match. case 's': // 1 string to match.
return Intrinsic::x86_sse2_cvtdq2ps; // "__builtin_ia32_ cvtdq2ps" return Intrinsic::x86_sse2_cvtdq2ps; // "__builtin_ia32_ cvtdq2ps"
} }
break; break;
case 'p': // 8 strings to match. case 'p': // 8 strings to match.
skipping to change at line 35792 skipping to change at line 40859
default: break; default: break;
case 'i': // 1 string to match. case 'i': // 1 string to match.
return Intrinsic::x86_sse_cvtpd2pi; // "__builtin_ia32_ cvtpd2pi" return Intrinsic::x86_sse_cvtpd2pi; // "__builtin_ia32_ cvtpd2pi"
case 's': // 1 string to match. case 's': // 1 string to match.
return Intrinsic::x86_sse2_cvtpd2ps; // "__builtin_ia32_ cvtpd2ps" return Intrinsic::x86_sse2_cvtpd2ps; // "__builtin_ia32_ cvtpd2ps"
} }
break; break;
} }
break; break;
case 'i': // 2 strings to match. case 'i': // 2 strings to match.
if (BuiltinName.substr(20, 2) != "2p") if (memcmp(BuiltinName.data()+20, "2p", 2))
break; break;
switch (BuiltinName[22]) { switch (BuiltinName[22]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
return Intrinsic::x86_sse_cvtpi2pd; // "__builtin_ia32_ cvtpi2pd" return Intrinsic::x86_sse_cvtpi2pd; // "__builtin_ia32_ cvtpi2pd"
case 's': // 1 string to match. case 's': // 1 string to match.
return Intrinsic::x86_sse_cvtpi2ps; // "__builtin_ia32_ cvtpi2ps" return Intrinsic::x86_sse_cvtpi2ps; // "__builtin_ia32_ cvtpi2ps"
} }
break; break;
case 's': // 3 strings to match. case 's': // 3 strings to match.
skipping to change at line 35828 skipping to change at line 40895
} }
break; break;
} }
break; break;
} }
break; break;
case 's': // 6 strings to match. case 's': // 6 strings to match.
switch (BuiltinName[19]) { switch (BuiltinName[19]) {
default: break; default: break;
case 'd': // 2 strings to match. case 'd': // 2 strings to match.
if (BuiltinName.substr(20, 2) != "2s") if (memcmp(BuiltinName.data()+20, "2s", 2))
break; break;
switch (BuiltinName[22]) { switch (BuiltinName[22]) {
default: break; default: break;
case 'i': // 1 string to match. case 'i': // 1 string to match.
return Intrinsic::x86_sse2_cvtsd2si; // "__builtin_ia32_ cvtsd2si" return Intrinsic::x86_sse2_cvtsd2si; // "__builtin_ia32_ cvtsd2si"
case 's': // 1 string to match. case 's': // 1 string to match.
return Intrinsic::x86_sse2_cvtsd2ss; // "__builtin_ia32_ cvtsd2ss" return Intrinsic::x86_sse2_cvtsd2ss; // "__builtin_ia32_ cvtsd2ss"
} }
break; break;
case 'i': // 2 strings to match. case 'i': // 2 strings to match.
if (BuiltinName.substr(20, 2) != "2s") if (memcmp(BuiltinName.data()+20, "2s", 2))
break; break;
switch (BuiltinName[22]) { switch (BuiltinName[22]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
return Intrinsic::x86_sse2_cvtsi2sd; // "__builtin_ia32_ cvtsi2sd" return Intrinsic::x86_sse2_cvtsi2sd; // "__builtin_ia32_ cvtsi2sd"
case 's': // 1 string to match. case 's': // 1 string to match.
return Intrinsic::x86_sse_cvtsi2ss; // "__builtin_ia32_ cvtsi2ss" return Intrinsic::x86_sse_cvtsi2ss; // "__builtin_ia32_ cvtsi2ss"
} }
break; break;
case 's': // 2 strings to match. case 's': // 2 strings to match.
if (BuiltinName.substr(20, 2) != "2s") if (memcmp(BuiltinName.data()+20, "2s", 2))
break; break;
switch (BuiltinName[22]) { switch (BuiltinName[22]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
return Intrinsic::x86_sse2_cvtss2sd; // "__builtin_ia32_ cvtss2sd" return Intrinsic::x86_sse2_cvtss2sd; // "__builtin_ia32_ cvtss2sd"
case 'i': // 1 string to match. case 'i': // 1 string to match.
return Intrinsic::x86_sse_cvtss2si; // "__builtin_ia32_ cvtss2si" return Intrinsic::x86_sse_cvtss2si; // "__builtin_ia32_ cvtss2si"
} }
break; break;
} }
break; break;
} }
break; break;
} }
break; break;
case 'i': // 1 string to match.
if (memcmp(BuiltinName.data()+16, "nsertqi", 7))
break;
return Intrinsic::x86_sse4a_insertqi; // "__builtin_ia32_insertqi
"
case 'l': // 1 string to match. case 'l': // 1 string to match.
if (BuiltinName.substr(16, 7) != "ddqu256") if (memcmp(BuiltinName.data()+16, "ddqu256", 7))
break; break;
return Intrinsic::x86_avx_ldu_dq_256; // "__builtin_ia32_lddqu256 " return Intrinsic::x86_avx_ldu_dq_256; // "__builtin_ia32_lddqu256 "
case 'm': // 8 strings to match. case 'm': // 8 strings to match.
switch (BuiltinName[16]) { switch (BuiltinName[16]) {
default: break; default: break;
case 'a': // 3 strings to match. case 'a': // 3 strings to match.
switch (BuiltinName[17]) { switch (BuiltinName[17]) {
default: break; default: break;
case 's': // 1 string to match. case 's': // 1 string to match.
if (BuiltinName.substr(18, 5) != "kmovq") if (memcmp(BuiltinName.data()+18, "kmovq", 5))
break; break;
return Intrinsic::x86_mmx_maskmovq; // "__builtin_ia32_maskmovq " return Intrinsic::x86_mmx_maskmovq; // "__builtin_ia32_maskmovq "
case 'x': // 2 strings to match. case 'x': // 2 strings to match.
if (BuiltinName[18] != 'p') if (BuiltinName[18] != 'p')
break; break;
switch (BuiltinName[19]) { switch (BuiltinName[19]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
if (BuiltinName.substr(20, 3) != "256") if (memcmp(BuiltinName.data()+20, "256", 3))
break; break;
return Intrinsic::x86_avx_max_pd_256; // "__builtin_ia32_ maxpd256" return Intrinsic::x86_avx_max_pd_256; // "__builtin_ia32_ maxpd256"
case 's': // 1 string to match. case 's': // 1 string to match.
if (BuiltinName.substr(20, 3) != "256") if (memcmp(BuiltinName.data()+20, "256", 3))
break; break;
return Intrinsic::x86_avx_max_ps_256; // "__builtin_ia32_ maxps256" return Intrinsic::x86_avx_max_ps_256; // "__builtin_ia32_ maxps256"
} }
break; break;
} }
break; break;
case 'i': // 2 strings to match. case 'i': // 2 strings to match.
if (BuiltinName.substr(17, 2) != "np") if (memcmp(BuiltinName.data()+17, "np", 2))
break; break;
switch (BuiltinName[19]) { switch (BuiltinName[19]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
if (BuiltinName.substr(20, 3) != "256") if (memcmp(BuiltinName.data()+20, "256", 3))
break; break;
return Intrinsic::x86_avx_min_pd_256; // "__builtin_ia32_ minpd256" return Intrinsic::x86_avx_min_pd_256; // "__builtin_ia32_ minpd256"
case 's': // 1 string to match. case 's': // 1 string to match.
if (BuiltinName.substr(20, 3) != "256") if (memcmp(BuiltinName.data()+20, "256", 3))
break; break;
return Intrinsic::x86_avx_min_ps_256; // "__builtin_ia32_ minps256" return Intrinsic::x86_avx_min_ps_256; // "__builtin_ia32_ minps256"
} }
break; break;
case 'o': // 3 strings to match. case 'o': // 3 strings to match.
if (BuiltinName[17] != 'v') if (BuiltinName[17] != 'v')
break; break;
switch (BuiltinName[18]) { switch (BuiltinName[18]) {
default: break; default: break;
case 'm': // 2 strings to match. case 'm': // 2 strings to match.
if (BuiltinName.substr(19, 3) != "skp") if (memcmp(BuiltinName.data()+19, "skp", 3))
break; break;
switch (BuiltinName[22]) { switch (BuiltinName[22]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
return Intrinsic::x86_sse2_movmsk_pd; // "__builtin_ia32_ movmskpd" return Intrinsic::x86_sse2_movmsk_pd; // "__builtin_ia32_ movmskpd"
case 's': // 1 string to match. case 's': // 1 string to match.
return Intrinsic::x86_sse_movmsk_ps; // "__builtin_ia32_ movmskps" return Intrinsic::x86_sse_movmsk_ps; // "__builtin_ia32_ movmskps"
} }
break; break;
case 'n': // 1 string to match. case 'n': // 1 string to match.
if (BuiltinName.substr(19, 4) != "tdqa") if (memcmp(BuiltinName.data()+19, "tdqa", 4))
break; break;
return Intrinsic::x86_sse41_movntdqa; // "__builtin_ia32_ movntdqa" return Intrinsic::x86_sse41_movntdqa; // "__builtin_ia32_ movntdqa"
} }
break; break;
} }
break; break;
case 'p': // 44 strings to match. case 'p': // 44 strings to match.
switch (BuiltinName[16]) { switch (BuiltinName[16]) {
default: break; default: break;
case 'a': // 13 strings to match. case 'a': // 13 strings to match.
skipping to change at line 35951 skipping to change at line 41022
default: break; default: break;
case 'b': // 6 strings to match. case 'b': // 6 strings to match.
if (BuiltinName[18] != 's') if (BuiltinName[18] != 's')
break; break;
switch (BuiltinName[19]) { switch (BuiltinName[19]) {
default: break; default: break;
case 'b': // 2 strings to match. case 'b': // 2 strings to match.
switch (BuiltinName[20]) { switch (BuiltinName[20]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(21, 2) != "28") if (memcmp(BuiltinName.data()+21, "28", 2))
break; break;
return Intrinsic::x86_ssse3_pabs_b_128; // "__builtin_ia32_ pabsb128" return Intrinsic::x86_ssse3_pabs_b_128; // "__builtin_ia32_ pabsb128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(21, 2) != "56") if (memcmp(BuiltinName.data()+21, "56", 2))
break; break;
return Intrinsic::x86_avx2_pabs_b; // "__builtin_ia32_ pabsb256" return Intrinsic::x86_avx2_pabs_b; // "__builtin_ia32_ pabsb256"
} }
break; break;
case 'd': // 2 strings to match. case 'd': // 2 strings to match.
switch (BuiltinName[20]) { switch (BuiltinName[20]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(21, 2) != "28") if (memcmp(BuiltinName.data()+21, "28", 2))
break; break;
return Intrinsic::x86_ssse3_pabs_d_128; // "__builtin_ia32_ pabsd128" return Intrinsic::x86_ssse3_pabs_d_128; // "__builtin_ia32_ pabsd128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(21, 2) != "56") if (memcmp(BuiltinName.data()+21, "56", 2))
break; break;
return Intrinsic::x86_avx2_pabs_d; // "__builtin_ia32_ pabsd256" return Intrinsic::x86_avx2_pabs_d; // "__builtin_ia32_ pabsd256"
} }
break; break;
case 'w': // 2 strings to match. case 'w': // 2 strings to match.
switch (BuiltinName[20]) { switch (BuiltinName[20]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(21, 2) != "28") if (memcmp(BuiltinName.data()+21, "28", 2))
break; break;
return Intrinsic::x86_ssse3_pabs_w_128; // "__builtin_ia32_ pabsw128" return Intrinsic::x86_ssse3_pabs_w_128; // "__builtin_ia32_ pabsw128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(21, 2) != "56") if (memcmp(BuiltinName.data()+21, "56", 2))
break; break;
return Intrinsic::x86_avx2_pabs_w; // "__builtin_ia32_ pabsw256" return Intrinsic::x86_avx2_pabs_w; // "__builtin_ia32_ pabsw256"
} }
break; break;
} }
break; break;
case 'c': // 3 strings to match. case 'c': // 3 strings to match.
if (BuiltinName[18] != 'k') if (BuiltinName[18] != 'k')
break; break;
switch (BuiltinName[19]) { switch (BuiltinName[19]) {
skipping to change at line 36009 skipping to change at line 41080
if (BuiltinName[22] != 'w') if (BuiltinName[22] != 'w')
break; break;
return Intrinsic::x86_mmx_packssdw; // "__builtin_ia32_ packssdw" return Intrinsic::x86_mmx_packssdw; // "__builtin_ia32_ packssdw"
case 'w': // 1 string to match. case 'w': // 1 string to match.
if (BuiltinName[22] != 'b') if (BuiltinName[22] != 'b')
break; break;
return Intrinsic::x86_mmx_packsswb; // "__builtin_ia32_ packsswb" return Intrinsic::x86_mmx_packsswb; // "__builtin_ia32_ packsswb"
} }
break; break;
case 'u': // 1 string to match. case 'u': // 1 string to match.
if (BuiltinName.substr(20, 3) != "swb") if (memcmp(BuiltinName.data()+20, "swb", 3))
break; break;
return Intrinsic::x86_mmx_packuswb; // "__builtin_ia32_ packuswb" return Intrinsic::x86_mmx_packuswb; // "__builtin_ia32_ packuswb"
} }
break; break;
case 'v': // 4 strings to match. case 'v': // 4 strings to match.
if (BuiltinName[18] != 'g') if (BuiltinName[18] != 'g')
break; break;
switch (BuiltinName[19]) { switch (BuiltinName[19]) {
default: break; default: break;
case 'b': // 2 strings to match. case 'b': // 2 strings to match.
switch (BuiltinName[20]) { switch (BuiltinName[20]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(21, 2) != "28") if (memcmp(BuiltinName.data()+21, "28", 2))
break; break;
return Intrinsic::x86_sse2_pavg_b; // "__builtin_ia32_ pavgb128" return Intrinsic::x86_sse2_pavg_b; // "__builtin_ia32_ pavgb128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(21, 2) != "56") if (memcmp(BuiltinName.data()+21, "56", 2))
break; break;
return Intrinsic::x86_avx2_pavg_b; // "__builtin_ia32_ pavgb256" return Intrinsic::x86_avx2_pavg_b; // "__builtin_ia32_ pavgb256"
} }
break; break;
case 'w': // 2 strings to match. case 'w': // 2 strings to match.
switch (BuiltinName[20]) { switch (BuiltinName[20]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(21, 2) != "28") if (memcmp(BuiltinName.data()+21, "28", 2))
break; break;
return Intrinsic::x86_sse2_pavg_w; // "__builtin_ia32_ pavgw128" return Intrinsic::x86_sse2_pavg_w; // "__builtin_ia32_ pavgw128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(21, 2) != "56") if (memcmp(BuiltinName.data()+21, "56", 2))
break; break;
return Intrinsic::x86_avx2_pavg_w; // "__builtin_ia32_ pavgw256" return Intrinsic::x86_avx2_pavg_w; // "__builtin_ia32_ pavgw256"
} }
break; break;
} }
break; break;
} }
break; break;
case 'f': // 3 strings to match. case 'f': // 3 strings to match.
if (BuiltinName[17] != 'r') if (BuiltinName[17] != 'r')
break; break;
switch (BuiltinName[18]) { switch (BuiltinName[18]) {
default: break; default: break;
case 'c': // 2 strings to match. case 'c': // 2 strings to match.
if (BuiltinName.substr(19, 3) != "pit") if (memcmp(BuiltinName.data()+19, "pit", 3))
break; break;
switch (BuiltinName[22]) { switch (BuiltinName[22]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
return Intrinsic::x86_3dnow_pfrcpit1; // "__builtin_ia32_ pfrcpit1" return Intrinsic::x86_3dnow_pfrcpit1; // "__builtin_ia32_ pfrcpit1"
case '2': // 1 string to match. case '2': // 1 string to match.
return Intrinsic::x86_3dnow_pfrcpit2; // "__builtin_ia32_ pfrcpit2" return Intrinsic::x86_3dnow_pfrcpit2; // "__builtin_ia32_ pfrcpit2"
} }
break; break;
case 's': // 1 string to match. case 's': // 1 string to match.
if (BuiltinName.substr(19, 4) != "qit1") if (memcmp(BuiltinName.data()+19, "qit1", 4))
break; break;
return Intrinsic::x86_3dnow_pfrsqit1; // "__builtin_ia32_ pfrsqit1" return Intrinsic::x86_3dnow_pfrsqit1; // "__builtin_ia32_ pfrsqit1"
} }
break; break;
case 'm': // 2 strings to match. case 'm': // 2 strings to match.
switch (BuiltinName[17]) { switch (BuiltinName[17]) {
default: break; default: break;
case 'o': // 1 string to match. case 'o': // 1 string to match.
if (BuiltinName.substr(18, 5) != "vmskb") if (memcmp(BuiltinName.data()+18, "vmskb", 5))
break; break;
return Intrinsic::x86_mmx_pmovmskb; // "__builtin_ia32_pmovmskb " return Intrinsic::x86_mmx_pmovmskb; // "__builtin_ia32_pmovmskb "
case 'u': // 1 string to match. case 'u': // 1 string to match.
if (BuiltinName.substr(18, 5) != "lhrsw") if (memcmp(BuiltinName.data()+18, "lhrsw", 5))
break; break;
return Intrinsic::x86_ssse3_pmul_hr_sw; // "__builtin_ia32_ pmulhrsw" return Intrinsic::x86_ssse3_pmul_hr_sw; // "__builtin_ia32_ pmulhrsw"
} }
break; break;
case 's': // 26 strings to match. case 's': // 26 strings to match.
switch (BuiltinName[17]) { switch (BuiltinName[17]) {
default: break; default: break;
case 'l': // 10 strings to match. case 'l': // 10 strings to match.
if (BuiltinName[18] != 'l') if (BuiltinName[18] != 'l')
break; break;
switch (BuiltinName[19]) { switch (BuiltinName[19]) {
default: break; default: break;
case 'd': // 2 strings to match. case 'd': // 2 strings to match.
switch (BuiltinName[20]) { switch (BuiltinName[20]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(21, 2) != "28") if (memcmp(BuiltinName.data()+21, "28", 2))
break; break;
return Intrinsic::x86_sse2_psll_d; // "__builtin_ia32_ pslld128" return Intrinsic::x86_sse2_psll_d; // "__builtin_ia32_ pslld128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(21, 2) != "56") if (memcmp(BuiltinName.data()+21, "56", 2))
break; break;
return Intrinsic::x86_avx2_psll_d; // "__builtin_ia32_ pslld256" return Intrinsic::x86_avx2_psll_d; // "__builtin_ia32_ pslld256"
} }
break; break;
case 'q': // 2 strings to match. case 'q': // 2 strings to match.
switch (BuiltinName[20]) { switch (BuiltinName[20]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(21, 2) != "28") if (memcmp(BuiltinName.data()+21, "28", 2))
break; break;
return Intrinsic::x86_sse2_psll_q; // "__builtin_ia32_ psllq128" return Intrinsic::x86_sse2_psll_q; // "__builtin_ia32_ psllq128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(21, 2) != "56") if (memcmp(BuiltinName.data()+21, "56", 2))
break; break;
return Intrinsic::x86_avx2_psll_q; // "__builtin_ia32_ psllq256" return Intrinsic::x86_avx2_psll_q; // "__builtin_ia32_ psllq256"
} }
break; break;
case 'v': // 4 strings to match. case 'v': // 4 strings to match.
switch (BuiltinName[20]) { switch (BuiltinName[20]) {
default: break; default: break;
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(21, 2) != "di") if (memcmp(BuiltinName.data()+21, "di", 2))
break; break;
return Intrinsic::x86_avx2_psllv_q; // "__builtin_ia32_ psllv2di" return Intrinsic::x86_avx2_psllv_q; // "__builtin_ia32_ psllv2di"
case '4': // 2 strings to match. case '4': // 2 strings to match.
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
if (BuiltinName[22] != 'i') if (BuiltinName[22] != 'i')
break; break;
return Intrinsic::x86_avx2_psllv_q_256; // "__built in_ia32_psllv4di" return Intrinsic::x86_avx2_psllv_q_256; // "__built in_ia32_psllv4di"
case 's': // 1 string to match. case 's': // 1 string to match.
if (BuiltinName[22] != 'i') if (BuiltinName[22] != 'i')
break; break;
return Intrinsic::x86_avx2_psllv_d; // "__builtin_ia32_ psllv4si" return Intrinsic::x86_avx2_psllv_d; // "__builtin_ia32_ psllv4si"
} }
break; break;
case '8': // 1 string to match. case '8': // 1 string to match.
if (BuiltinName.substr(21, 2) != "si") if (memcmp(BuiltinName.data()+21, "si", 2))
break; break;
return Intrinsic::x86_avx2_psllv_d_256; // "__builtin_ia32_ psllv8si" return Intrinsic::x86_avx2_psllv_d_256; // "__builtin_ia32_ psllv8si"
} }
break; break;
case 'w': // 2 strings to match. case 'w': // 2 strings to match.
switch (BuiltinName[20]) { switch (BuiltinName[20]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(21, 2) != "28") if (memcmp(BuiltinName.data()+21, "28", 2))
break; break;
return Intrinsic::x86_sse2_psll_w; // "__builtin_ia32_ psllw128" return Intrinsic::x86_sse2_psll_w; // "__builtin_ia32_ psllw128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(21, 2) != "56") if (memcmp(BuiltinName.data()+21, "56", 2))
break; break;
return Intrinsic::x86_avx2_psll_w; // "__builtin_ia32_ psllw256" return Intrinsic::x86_avx2_psll_w; // "__builtin_ia32_ psllw256"
} }
break; break;
} }
break; break;
case 'r': // 16 strings to match. case 'r': // 16 strings to match.
switch (BuiltinName[18]) { switch (BuiltinName[18]) {
default: break; default: break;
case 'a': // 6 strings to match. case 'a': // 6 strings to match.
switch (BuiltinName[19]) { switch (BuiltinName[19]) {
default: break; default: break;
case 'd': // 2 strings to match. case 'd': // 2 strings to match.
switch (BuiltinName[20]) { switch (BuiltinName[20]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(21, 2) != "28") if (memcmp(BuiltinName.data()+21, "28", 2))
break; break;
return Intrinsic::x86_sse2_psra_d; // "__builtin_ia32_ psrad128" return Intrinsic::x86_sse2_psra_d; // "__builtin_ia32_ psrad128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(21, 2) != "56") if (memcmp(BuiltinName.data()+21, "56", 2))
break; break;
return Intrinsic::x86_avx2_psra_d; // "__builtin_ia32_ psrad256" return Intrinsic::x86_avx2_psra_d; // "__builtin_ia32_ psrad256"
} }
break; break;
case 'v': // 2 strings to match. case 'v': // 2 strings to match.
switch (BuiltinName[20]) { switch (BuiltinName[20]) {
default: break; default: break;
case '4': // 1 string to match. case '4': // 1 string to match.
if (BuiltinName.substr(21, 2) != "si") if (memcmp(BuiltinName.data()+21, "si", 2))
break; break;
return Intrinsic::x86_avx2_psrav_d; // "__builtin_ia32_ psrav4si" return Intrinsic::x86_avx2_psrav_d; // "__builtin_ia32_ psrav4si"
case '8': // 1 string to match. case '8': // 1 string to match.
if (BuiltinName.substr(21, 2) != "si") if (memcmp(BuiltinName.data()+21, "si", 2))
break; break;
return Intrinsic::x86_avx2_psrav_d_256; // "__built in_ia32_psrav8si" return Intrinsic::x86_avx2_psrav_d_256; // "__built in_ia32_psrav8si"
} }
break; break;
case 'w': // 2 strings to match. case 'w': // 2 strings to match.
switch (BuiltinName[20]) { switch (BuiltinName[20]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(21, 2) != "28") if (memcmp(BuiltinName.data()+21, "28", 2))
break; break;
return Intrinsic::x86_sse2_psra_w; // "__builtin_ia32_ psraw128" return Intrinsic::x86_sse2_psra_w; // "__builtin_ia32_ psraw128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(21, 2) != "56") if (memcmp(BuiltinName.data()+21, "56", 2))
break; break;
return Intrinsic::x86_avx2_psra_w; // "__builtin_ia32_ psraw256" return Intrinsic::x86_avx2_psra_w; // "__builtin_ia32_ psraw256"
} }
break; break;
} }
break; break;
case 'l': // 10 strings to match. case 'l': // 10 strings to match.
switch (BuiltinName[19]) { switch (BuiltinName[19]) {
default: break; default: break;
case 'd': // 2 strings to match. case 'd': // 2 strings to match.
switch (BuiltinName[20]) { switch (BuiltinName[20]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(21, 2) != "28") if (memcmp(BuiltinName.data()+21, "28", 2))
break; break;
return Intrinsic::x86_sse2_psrl_d; // "__builtin_ia32_ psrld128" return Intrinsic::x86_sse2_psrl_d; // "__builtin_ia32_ psrld128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(21, 2) != "56") if (memcmp(BuiltinName.data()+21, "56", 2))
break; break;
return Intrinsic::x86_avx2_psrl_d; // "__builtin_ia32_ psrld256" return Intrinsic::x86_avx2_psrl_d; // "__builtin_ia32_ psrld256"
} }
break; break;
case 'q': // 2 strings to match. case 'q': // 2 strings to match.
switch (BuiltinName[20]) { switch (BuiltinName[20]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(21, 2) != "28") if (memcmp(BuiltinName.data()+21, "28", 2))
break; break;
return Intrinsic::x86_sse2_psrl_q; // "__builtin_ia32_ psrlq128" return Intrinsic::x86_sse2_psrl_q; // "__builtin_ia32_ psrlq128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(21, 2) != "56") if (memcmp(BuiltinName.data()+21, "56", 2))
break; break;
return Intrinsic::x86_avx2_psrl_q; // "__builtin_ia32_ psrlq256" return Intrinsic::x86_avx2_psrl_q; // "__builtin_ia32_ psrlq256"
} }
break; break;
case 'v': // 4 strings to match. case 'v': // 4 strings to match.
switch (BuiltinName[20]) { switch (BuiltinName[20]) {
default: break; default: break;
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(21, 2) != "di") if (memcmp(BuiltinName.data()+21, "di", 2))
break; break;
return Intrinsic::x86_avx2_psrlv_q; // "__builtin_ia32_ psrlv2di" return Intrinsic::x86_avx2_psrlv_q; // "__builtin_ia32_ psrlv2di"
case '4': // 2 strings to match. case '4': // 2 strings to match.
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
if (BuiltinName[22] != 'i') if (BuiltinName[22] != 'i')
break; break;
return Intrinsic::x86_avx2_psrlv_q_256; // "__built in_ia32_psrlv4di" return Intrinsic::x86_avx2_psrlv_q_256; // "__built in_ia32_psrlv4di"
case 's': // 1 string to match. case 's': // 1 string to match.
if (BuiltinName[22] != 'i') if (BuiltinName[22] != 'i')
break; break;
return Intrinsic::x86_avx2_psrlv_d; // "__builtin_ia32_ psrlv4si" return Intrinsic::x86_avx2_psrlv_d; // "__builtin_ia32_ psrlv4si"
} }
break; break;
case '8': // 1 string to match. case '8': // 1 string to match.
if (BuiltinName.substr(21, 2) != "si") if (memcmp(BuiltinName.data()+21, "si", 2))
break; break;
return Intrinsic::x86_avx2_psrlv_d_256; // "__built in_ia32_psrlv8si" return Intrinsic::x86_avx2_psrlv_d_256; // "__built in_ia32_psrlv8si"
} }
break; break;
case 'w': // 2 strings to match. case 'w': // 2 strings to match.
switch (BuiltinName[20]) { switch (BuiltinName[20]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(21, 2) != "28") if (memcmp(BuiltinName.data()+21, "28", 2))
break; break;
return Intrinsic::x86_sse2_psrl_w; // "__builtin_ia32_ psrlw128" return Intrinsic::x86_sse2_psrl_w; // "__builtin_ia32_ psrlw128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(21, 2) != "56") if (memcmp(BuiltinName.data()+21, "56", 2))
break; break;
return Intrinsic::x86_avx2_psrl_w; // "__builtin_ia32_ psrlw256" return Intrinsic::x86_avx2_psrl_w; // "__builtin_ia32_ psrlw256"
} }
break; break;
} }
break; break;
} }
break; break;
} }
break; break;
} }
break; break;
case 'r': // 1 string to match. case 'r': // 1 string to match.
if (BuiltinName.substr(16, 7) != "cpps256") if (memcmp(BuiltinName.data()+16, "cpps256", 7))
break; break;
return Intrinsic::x86_avx_rcp_ps_256; // "__builtin_ia32_rcpps256 " return Intrinsic::x86_avx_rcp_ps_256; // "__builtin_ia32_rcpps256 "
case 's': // 3 strings to match. case 's': // 3 strings to match.
if (BuiltinName.substr(16, 4) != "tore") if (memcmp(BuiltinName.data()+16, "tore", 4))
break; break;
switch (BuiltinName[20]) { switch (BuiltinName[20]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
if (BuiltinName.substr(21, 2) != "qu") if (memcmp(BuiltinName.data()+21, "qu", 2))
break; break;
return Intrinsic::x86_sse2_storeu_dq; // "__builtin_ia32_storedqu " return Intrinsic::x86_sse2_storeu_dq; // "__builtin_ia32_storedqu "
case 'u': // 2 strings to match. case 'u': // 2 strings to match.
if (BuiltinName[21] != 'p') if (BuiltinName[21] != 'p')
break; break;
switch (BuiltinName[22]) { switch (BuiltinName[22]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
return Intrinsic::x86_sse2_storeu_pd; // "__builtin_ia32_ storeupd" return Intrinsic::x86_sse2_storeu_pd; // "__builtin_ia32_ storeupd"
case 's': // 1 string to match. case 's': // 1 string to match.
return Intrinsic::x86_sse_storeu_ps; // "__builtin_ia32_storeups " return Intrinsic::x86_sse_storeu_ps; // "__builtin_ia32_storeups "
} }
break; break;
} }
break; break;
case 'u': // 1 string to match. case 'u': // 1 string to match.
if (BuiltinName.substr(16, 7) != "comineq") if (memcmp(BuiltinName.data()+16, "comineq", 7))
break; break;
return Intrinsic::x86_sse_ucomineq_ss; // "__builtin_ia32_ucomineq " return Intrinsic::x86_sse_ucomineq_ss; // "__builtin_ia32_ucomineq "
case 'v': // 13 strings to match. case 'v': // 13 strings to match.
switch (BuiltinName[16]) { switch (BuiltinName[16]) {
default: break; default: break;
case 'f': // 8 strings to match. case 'f': // 8 strings to match.
if (BuiltinName[17] != 'm') if (BuiltinName[17] != 'm')
break; break;
switch (BuiltinName[18]) { switch (BuiltinName[18]) {
default: break; default: break;
case 'a': // 4 strings to match. case 'a': // 4 strings to match.
if (BuiltinName.substr(19, 2) != "dd") if (memcmp(BuiltinName.data()+19, "dd", 2))
break; break;
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case 'p': // 2 strings to match. case 'p': // 2 strings to match.
switch (BuiltinName[22]) { switch (BuiltinName[22]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
return Intrinsic::x86_fma4_vfmadd_pd; // "__builtin_ia32_ vfmaddpd" return Intrinsic::x86_fma_vfmadd_pd; // "__builtin_ia32_ vfmaddpd"
case 's': // 1 string to match. case 's': // 1 string to match.
return Intrinsic::x86_fma4_vfmadd_ps; // "__builtin_ia32_ vfmaddps" return Intrinsic::x86_fma_vfmadd_ps; // "__builtin_ia32_ vfmaddps"
} }
break; break;
case 's': // 2 strings to match. case 's': // 2 strings to match.
switch (BuiltinName[22]) { switch (BuiltinName[22]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
return Intrinsic::x86_fma4_vfmadd_sd; // "__builtin_ia32_ vfmaddsd" return Intrinsic::x86_fma_vfmadd_sd; // "__builtin_ia32_ vfmaddsd"
case 's': // 1 string to match. case 's': // 1 string to match.
return Intrinsic::x86_fma4_vfmadd_ss; // "__builtin_ia32_ vfmaddss" return Intrinsic::x86_fma_vfmadd_ss; // "__builtin_ia32_ vfmaddss"
} }
break; break;
} }
break; break;
case 's': // 4 strings to match. case 's': // 4 strings to match.
if (BuiltinName.substr(19, 2) != "ub") if (memcmp(BuiltinName.data()+19, "ub", 2))
break; break;
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case 'p': // 2 strings to match. case 'p': // 2 strings to match.
switch (BuiltinName[22]) { switch (BuiltinName[22]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
return Intrinsic::x86_fma4_vfmsub_pd; // "__builtin_ia32_ vfmsubpd" return Intrinsic::x86_fma_vfmsub_pd; // "__builtin_ia32_ vfmsubpd"
case 's': // 1 string to match. case 's': // 1 string to match.
return Intrinsic::x86_fma4_vfmsub_ps; // "__builtin_ia32_ vfmsubps" return Intrinsic::x86_fma_vfmsub_ps; // "__builtin_ia32_ vfmsubps"
} }
break; break;
case 's': // 2 strings to match. case 's': // 2 strings to match.
switch (BuiltinName[22]) { switch (BuiltinName[22]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
return Intrinsic::x86_fma4_vfmsub_sd; // "__builtin_ia32_ vfmsubsd" return Intrinsic::x86_fma_vfmsub_sd; // "__builtin_ia32_ vfmsubsd"
case 's': // 1 string to match. case 's': // 1 string to match.
return Intrinsic::x86_fma4_vfmsub_ss; // "__builtin_ia32_ vfmsubss" return Intrinsic::x86_fma_vfmsub_ss; // "__builtin_ia32_ vfmsubss"
} }
break; break;
} }
break; break;
} }
break; break;
case 't': // 4 strings to match. case 't': // 4 strings to match.
if (BuiltinName.substr(17, 3) != "est") if (memcmp(BuiltinName.data()+17, "est", 3))
break; break;
switch (BuiltinName[20]) { switch (BuiltinName[20]) {
default: break; default: break;
case 'c': // 2 strings to match. case 'c': // 2 strings to match.
if (BuiltinName[21] != 'p') if (BuiltinName[21] != 'p')
break; break;
switch (BuiltinName[22]) { switch (BuiltinName[22]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
return Intrinsic::x86_avx_vtestc_pd; // "__builtin_ia32_ vtestcpd" return Intrinsic::x86_avx_vtestc_pd; // "__builtin_ia32_ vtestcpd"
skipping to change at line 36402 skipping to change at line 41473
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
return Intrinsic::x86_avx_vtestz_pd; // "__builtin_ia32_ vtestzpd" return Intrinsic::x86_avx_vtestz_pd; // "__builtin_ia32_ vtestzpd"
case 's': // 1 string to match. case 's': // 1 string to match.
return Intrinsic::x86_avx_vtestz_ps; // "__builtin_ia32_ vtestzps" return Intrinsic::x86_avx_vtestz_ps; // "__builtin_ia32_ vtestzps"
} }
break; break;
} }
break; break;
case 'z': // 1 string to match. case 'z': // 1 string to match.
if (BuiltinName.substr(17, 6) != "eroall") if (memcmp(BuiltinName.data()+17, "eroall", 6))
break; break;
return Intrinsic::x86_avx_vzeroall; // "__builtin_ia32_vzeroall " return Intrinsic::x86_avx_vzeroall; // "__builtin_ia32_vzeroall "
} }
break; break;
} }
break; break;
case 24: // 117 strings to match. case 24: // 121 strings to match.
if (BuiltinName.substr(0, 15) != "__builtin_ia32_") if (memcmp(BuiltinName.data()+0, "__builtin_ia32_", 15))
break; break;
switch (BuiltinName[15]) { switch (BuiltinName[15]) {
default: break; default: break;
case 'a': // 3 strings to match. case 'a': // 3 strings to match.
if (BuiltinName.substr(16, 2) != "es") if (memcmp(BuiltinName.data()+16, "es", 2))
break; break;
switch (BuiltinName[18]) { switch (BuiltinName[18]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
if (BuiltinName.substr(19, 5) != "ec128") if (memcmp(BuiltinName.data()+19, "ec128", 5))
break; break;
return Intrinsic::x86_aesni_aesdec; // "__builtin_ia32_aesdec12 8" return Intrinsic::x86_aesni_aesdec; // "__builtin_ia32_aesdec12 8"
case 'e': // 1 string to match. case 'e': // 1 string to match.
if (BuiltinName.substr(19, 5) != "nc128") if (memcmp(BuiltinName.data()+19, "nc128", 5))
break; break;
return Intrinsic::x86_aesni_aesenc; // "__builtin_ia32_aesenc12 8" return Intrinsic::x86_aesni_aesenc; // "__builtin_ia32_aesenc12 8"
case 'i': // 1 string to match. case 'i': // 1 string to match.
if (BuiltinName.substr(19, 5) != "mc128") if (memcmp(BuiltinName.data()+19, "mc128", 5))
break; break;
return Intrinsic::x86_aesni_aesimc; // "__builtin_ia32_aesimc12 8" return Intrinsic::x86_aesni_aesimc; // "__builtin_ia32_aesimc12 8"
} }
break; break;
case 'b': // 2 strings to match. case 'b': // 2 strings to match.
if (BuiltinName.substr(16, 6) != "extr_u") if (memcmp(BuiltinName.data()+16, "extr_u", 6))
break; break;
switch (BuiltinName[22]) { switch (BuiltinName[22]) {
default: break; default: break;
case '3': // 1 string to match. case '3': // 1 string to match.
if (BuiltinName[23] != '2') if (BuiltinName[23] != '2')
break; break;
return Intrinsic::x86_bmi_bextr_32; // "__builtin_ia32_bextr_u3 2" return Intrinsic::x86_bmi_bextr_32; // "__builtin_ia32_bextr_u3 2"
case '6': // 1 string to match. case '6': // 1 string to match.
if (BuiltinName[23] != '4') if (BuiltinName[23] != '4')
break; break;
return Intrinsic::x86_bmi_bextr_64; // "__builtin_ia32_bextr_u6 4" return Intrinsic::x86_bmi_bextr_64; // "__builtin_ia32_bextr_u6 4"
} }
break; break;
case 'c': // 7 strings to match. case 'c': // 7 strings to match.
switch (BuiltinName[16]) { switch (BuiltinName[16]) {
default: break; default: break;
case 'o': // 1 string to match. case 'o': // 1 string to match.
if (BuiltinName.substr(17, 7) != "misdneq") if (memcmp(BuiltinName.data()+17, "misdneq", 7))
break; break;
return Intrinsic::x86_sse2_comineq_sd; // "__builtin_ia32_comisdne q" return Intrinsic::x86_sse2_comineq_sd; // "__builtin_ia32_comisdne q"
case 'v': // 6 strings to match. case 'v': // 6 strings to match.
if (BuiltinName.substr(17, 2) != "tt") if (memcmp(BuiltinName.data()+17, "tt", 2))
break; break;
switch (BuiltinName[19]) { switch (BuiltinName[19]) {
default: break; default: break;
case 'p': // 4 strings to match. case 'p': // 4 strings to match.
switch (BuiltinName[20]) { switch (BuiltinName[20]) {
default: break; default: break;
case 'd': // 2 strings to match. case 'd': // 2 strings to match.
if (BuiltinName[21] != '2') if (BuiltinName[21] != '2')
break; break;
switch (BuiltinName[22]) { switch (BuiltinName[22]) {
skipping to change at line 36499 skipping to change at line 41570
break; break;
return Intrinsic::x86_sse_cvttps2pi; // "__builtin_ia32_ cvttps2pi" return Intrinsic::x86_sse_cvttps2pi; // "__builtin_ia32_ cvttps2pi"
} }
break; break;
} }
break; break;
case 's': // 2 strings to match. case 's': // 2 strings to match.
switch (BuiltinName[20]) { switch (BuiltinName[20]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
if (BuiltinName.substr(21, 3) != "2si") if (memcmp(BuiltinName.data()+21, "2si", 3))
break; break;
return Intrinsic::x86_sse2_cvttsd2si; // "__builtin_ia32_ cvttsd2si" return Intrinsic::x86_sse2_cvttsd2si; // "__builtin_ia32_ cvttsd2si"
case 's': // 1 string to match. case 's': // 1 string to match.
if (BuiltinName.substr(21, 3) != "2si") if (memcmp(BuiltinName.data()+21, "2si", 3))
break; break;
return Intrinsic::x86_sse_cvttss2si; // "__builtin_ia32_ cvttss2si" return Intrinsic::x86_sse_cvttss2si; // "__builtin_ia32_ cvttss2si"
} }
break; break;
} }
break; break;
} }
break; break;
case 'g': // 4 strings to match.
if (memcmp(BuiltinName.data()+16, "ather", 5))
break;
switch (BuiltinName[21]) {
default: break;
case 'd': // 2 strings to match.
if (BuiltinName[22] != '_')
break;
switch (BuiltinName[23]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::x86_avx2_gather_d_d; // "__builtin_ia32_
gatherd_d"
case 'q': // 1 string to match.
return Intrinsic::x86_avx2_gather_d_q; // "__builtin_ia32_
gatherd_q"
}
break;
case 'q': // 2 strings to match.
if (BuiltinName[22] != '_')
break;
switch (BuiltinName[23]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::x86_avx2_gather_q_d; // "__builtin_ia32_
gatherq_d"
case 'q': // 1 string to match.
return Intrinsic::x86_avx2_gather_q_q; // "__builtin_ia32_
gatherq_q"
}
break;
}
break;
case 'h': // 4 strings to match. case 'h': // 4 strings to match.
switch (BuiltinName[16]) { switch (BuiltinName[16]) {
default: break; default: break;
case 'a': // 2 strings to match. case 'a': // 2 strings to match.
if (BuiltinName.substr(17, 3) != "ddp") if (memcmp(BuiltinName.data()+17, "ddp", 3))
break; break;
switch (BuiltinName[20]) { switch (BuiltinName[20]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
if (BuiltinName.substr(21, 3) != "256") if (memcmp(BuiltinName.data()+21, "256", 3))
break; break;
return Intrinsic::x86_avx_hadd_pd_256; // "__builtin_ia32_ haddpd256" return Intrinsic::x86_avx_hadd_pd_256; // "__builtin_ia32_ haddpd256"
case 's': // 1 string to match. case 's': // 1 string to match.
if (BuiltinName.substr(21, 3) != "256") if (memcmp(BuiltinName.data()+21, "256", 3))
break; break;
return Intrinsic::x86_avx_hadd_ps_256; // "__builtin_ia32_ haddps256" return Intrinsic::x86_avx_hadd_ps_256; // "__builtin_ia32_ haddps256"
} }
break; break;
case 's': // 2 strings to match. case 's': // 2 strings to match.
if (BuiltinName.substr(17, 3) != "ubp") if (memcmp(BuiltinName.data()+17, "ubp", 3))
break; break;
switch (BuiltinName[20]) { switch (BuiltinName[20]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
if (BuiltinName.substr(21, 3) != "256") if (memcmp(BuiltinName.data()+21, "256", 3))
break; break;
return Intrinsic::x86_avx_hsub_pd_256; // "__builtin_ia32_ hsubpd256" return Intrinsic::x86_avx_hsub_pd_256; // "__builtin_ia32_ hsubpd256"
case 's': // 1 string to match. case 's': // 1 string to match.
if (BuiltinName.substr(21, 3) != "256") if (memcmp(BuiltinName.data()+21, "256", 3))
break; break;
return Intrinsic::x86_avx_hsub_ps_256; // "__builtin_ia32_ hsubps256" return Intrinsic::x86_avx_hsub_ps_256; // "__builtin_ia32_ hsubps256"
} }
break; break;
} }
break; break;
case 'm': // 2 strings to match. case 'm': // 2 strings to match.
if (BuiltinName.substr(16, 7) != "askload") if (memcmp(BuiltinName.data()+16, "askload", 7))
break; break;
switch (BuiltinName[23]) { switch (BuiltinName[23]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
return Intrinsic::x86_avx2_maskload_d; // "__builtin_ia32_maskload d" return Intrinsic::x86_avx2_maskload_d; // "__builtin_ia32_maskload d"
case 'q': // 1 string to match. case 'q': // 1 string to match.
return Intrinsic::x86_avx2_maskload_q; // "__builtin_ia32_maskload q" return Intrinsic::x86_avx2_maskload_q; // "__builtin_ia32_maskload q"
} }
break; break;
case 'p': // 82 strings to match. case 'p': // 82 strings to match.
switch (BuiltinName[16]) { switch (BuiltinName[16]) {
default: break; default: break;
case 'a': // 4 strings to match. case 'a': // 4 strings to match.
if (BuiltinName.substr(17, 3) != "dds") if (memcmp(BuiltinName.data()+17, "dds", 3))
break; break;
switch (BuiltinName[20]) { switch (BuiltinName[20]) {
default: break; default: break;
case 'b': // 2 strings to match. case 'b': // 2 strings to match.
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(22, 2) != "28") if (memcmp(BuiltinName.data()+22, "28", 2))
break; break;
return Intrinsic::x86_sse2_padds_b; // "__builtin_ia32_ paddsb128" return Intrinsic::x86_sse2_padds_b; // "__builtin_ia32_ paddsb128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(22, 2) != "56") if (memcmp(BuiltinName.data()+22, "56", 2))
break; break;
return Intrinsic::x86_avx2_padds_b; // "__builtin_ia32_ paddsb256" return Intrinsic::x86_avx2_padds_b; // "__builtin_ia32_ paddsb256"
} }
break; break;
case 'w': // 2 strings to match. case 'w': // 2 strings to match.
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(22, 2) != "28") if (memcmp(BuiltinName.data()+22, "28", 2))
break; break;
return Intrinsic::x86_sse2_padds_w; // "__builtin_ia32_ paddsw128" return Intrinsic::x86_sse2_padds_w; // "__builtin_ia32_ paddsw128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(22, 2) != "56") if (memcmp(BuiltinName.data()+22, "56", 2))
break; break;
return Intrinsic::x86_avx2_padds_w; // "__builtin_ia32_ paddsw256" return Intrinsic::x86_avx2_padds_w; // "__builtin_ia32_ paddsw256"
} }
break; break;
} }
break; break;
case 'e': // 1 string to match. case 'e': // 1 string to match.
if (BuiltinName.substr(17, 7) != "rmti256") if (memcmp(BuiltinName.data()+17, "rmti256", 7))
break; break;
return Intrinsic::x86_avx2_vperm2i128; // "__builtin_ia32_permti25 6" return Intrinsic::x86_avx2_vperm2i128; // "__builtin_ia32_permti25 6"
case 'h': // 8 strings to match. case 'h': // 8 strings to match.
switch (BuiltinName[17]) { switch (BuiltinName[17]) {
default: break; default: break;
case 'a': // 4 strings to match. case 'a': // 4 strings to match.
if (BuiltinName.substr(18, 2) != "dd") if (memcmp(BuiltinName.data()+18, "dd", 2))
break; break;
switch (BuiltinName[20]) { switch (BuiltinName[20]) {
default: break; default: break;
case 'd': // 2 strings to match. case 'd': // 2 strings to match.
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(22, 2) != "28") if (memcmp(BuiltinName.data()+22, "28", 2))
break; break;
return Intrinsic::x86_ssse3_phadd_d_128; // "__builtin_ia32_ phaddd128" return Intrinsic::x86_ssse3_phadd_d_128; // "__builtin_ia32_ phaddd128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(22, 2) != "56") if (memcmp(BuiltinName.data()+22, "56", 2))
break; break;
return Intrinsic::x86_avx2_phadd_d; // "__builtin_ia32_ phaddd256" return Intrinsic::x86_avx2_phadd_d; // "__builtin_ia32_ phaddd256"
} }
break; break;
case 'w': // 2 strings to match. case 'w': // 2 strings to match.
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(22, 2) != "28") if (memcmp(BuiltinName.data()+22, "28", 2))
break; break;
return Intrinsic::x86_ssse3_phadd_w_128; // "__builtin_ia32_ phaddw128" return Intrinsic::x86_ssse3_phadd_w_128; // "__builtin_ia32_ phaddw128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(22, 2) != "56") if (memcmp(BuiltinName.data()+22, "56", 2))
break; break;
return Intrinsic::x86_avx2_phadd_w; // "__builtin_ia32_ phaddw256" return Intrinsic::x86_avx2_phadd_w; // "__builtin_ia32_ phaddw256"
} }
break; break;
} }
break; break;
case 's': // 4 strings to match. case 's': // 4 strings to match.
if (BuiltinName.substr(18, 2) != "ub") if (memcmp(BuiltinName.data()+18, "ub", 2))
break; break;
switch (BuiltinName[20]) { switch (BuiltinName[20]) {
default: break; default: break;
case 'd': // 2 strings to match. case 'd': // 2 strings to match.
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(22, 2) != "28") if (memcmp(BuiltinName.data()+22, "28", 2))
break; break;
return Intrinsic::x86_ssse3_phsub_d_128; // "__builtin_ia32_ phsubd128" return Intrinsic::x86_ssse3_phsub_d_128; // "__builtin_ia32_ phsubd128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(22, 2) != "56") if (memcmp(BuiltinName.data()+22, "56", 2))
break; break;
return Intrinsic::x86_avx2_phsub_d; // "__builtin_ia32_ phsubd256" return Intrinsic::x86_avx2_phsub_d; // "__builtin_ia32_ phsubd256"
} }
break; break;
case 'w': // 2 strings to match. case 'w': // 2 strings to match.
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(22, 2) != "28") if (memcmp(BuiltinName.data()+22, "28", 2))
break; break;
return Intrinsic::x86_ssse3_phsub_w_128; // "__builtin_ia32_ phsubw128" return Intrinsic::x86_ssse3_phsub_w_128; // "__builtin_ia32_ phsubw128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(22, 2) != "56") if (memcmp(BuiltinName.data()+22, "56", 2))
break; break;
return Intrinsic::x86_avx2_phsub_w; // "__builtin_ia32_ phsubw256" return Intrinsic::x86_avx2_phsub_w; // "__builtin_ia32_ phsubw256"
} }
break; break;
} }
break; break;
} }
break; break;
case 'm': // 29 strings to match. case 'm': // 29 strings to match.
switch (BuiltinName[17]) { switch (BuiltinName[17]) {
default: break; default: break;
case 'a': // 13 strings to match. case 'a': // 13 strings to match.
switch (BuiltinName[18]) { switch (BuiltinName[18]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
if (BuiltinName.substr(19, 5) != "dubsw") if (memcmp(BuiltinName.data()+19, "dubsw", 5))
break; break;
return Intrinsic::x86_ssse3_pmadd_ub_sw; // "__builtin_ia32_ pmaddubsw" return Intrinsic::x86_ssse3_pmadd_ub_sw; // "__builtin_ia32_ pmaddubsw"
case 'x': // 12 strings to match. case 'x': // 12 strings to match.
switch (BuiltinName[19]) { switch (BuiltinName[19]) {
default: break; default: break;
case 's': // 6 strings to match. case 's': // 6 strings to match.
switch (BuiltinName[20]) { switch (BuiltinName[20]) {
default: break; default: break;
case 'b': // 2 strings to match. case 'b': // 2 strings to match.
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(22, 2) != "28") if (memcmp(BuiltinName.data()+22, "28", 2))
break; break;
return Intrinsic::x86_sse41_pmaxsb; // "__builtin_ia32_ pmaxsb128" return Intrinsic::x86_sse41_pmaxsb; // "__builtin_ia32_ pmaxsb128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(22, 2) != "56") if (memcmp(BuiltinName.data()+22, "56", 2))
break; break;
return Intrinsic::x86_avx2_pmaxs_b; // "__builtin_ia32_ pmaxsb256" return Intrinsic::x86_avx2_pmaxs_b; // "__builtin_ia32_ pmaxsb256"
} }
break; break;
case 'd': // 2 strings to match. case 'd': // 2 strings to match.
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(22, 2) != "28") if (memcmp(BuiltinName.data()+22, "28", 2))
break; break;
return Intrinsic::x86_sse41_pmaxsd; // "__builtin_ia32_ pmaxsd128" return Intrinsic::x86_sse41_pmaxsd; // "__builtin_ia32_ pmaxsd128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(22, 2) != "56") if (memcmp(BuiltinName.data()+22, "56", 2))
break; break;
return Intrinsic::x86_avx2_pmaxs_d; // "__builtin_ia32_ pmaxsd256" return Intrinsic::x86_avx2_pmaxs_d; // "__builtin_ia32_ pmaxsd256"
} }
break; break;
case 'w': // 2 strings to match. case 'w': // 2 strings to match.
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(22, 2) != "28") if (memcmp(BuiltinName.data()+22, "28", 2))
break; break;
return Intrinsic::x86_sse2_pmaxs_w; // "__builtin_ia32_ pmaxsw128" return Intrinsic::x86_sse2_pmaxs_w; // "__builtin_ia32_ pmaxsw128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(22, 2) != "56") if (memcmp(BuiltinName.data()+22, "56", 2))
break; break;
return Intrinsic::x86_avx2_pmaxs_w; // "__builtin_ia32_ pmaxsw256" return Intrinsic::x86_avx2_pmaxs_w; // "__builtin_ia32_ pmaxsw256"
} }
break; break;
} }
break; break;
case 'u': // 6 strings to match. case 'u': // 6 strings to match.
switch (BuiltinName[20]) { switch (BuiltinName[20]) {
default: break; default: break;
case 'b': // 2 strings to match. case 'b': // 2 strings to match.
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(22, 2) != "28") if (memcmp(BuiltinName.data()+22, "28", 2))
break; break;
return Intrinsic::x86_sse2_pmaxu_b; // "__builtin_ia32_ pmaxub128" return Intrinsic::x86_sse2_pmaxu_b; // "__builtin_ia32_ pmaxub128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(22, 2) != "56") if (memcmp(BuiltinName.data()+22, "56", 2))
break; break;
return Intrinsic::x86_avx2_pmaxu_b; // "__builtin_ia32_ pmaxub256" return Intrinsic::x86_avx2_pmaxu_b; // "__builtin_ia32_ pmaxub256"
} }
break; break;
case 'd': // 2 strings to match. case 'd': // 2 strings to match.
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(22, 2) != "28") if (memcmp(BuiltinName.data()+22, "28", 2))
break; break;
return Intrinsic::x86_sse41_pmaxud; // "__builtin_ia32_ pmaxud128" return Intrinsic::x86_sse41_pmaxud; // "__builtin_ia32_ pmaxud128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(22, 2) != "56") if (memcmp(BuiltinName.data()+22, "56", 2))
break; break;
return Intrinsic::x86_avx2_pmaxu_d; // "__builtin_ia32_ pmaxud256" return Intrinsic::x86_avx2_pmaxu_d; // "__builtin_ia32_ pmaxud256"
} }
break; break;
case 'w': // 2 strings to match. case 'w': // 2 strings to match.
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(22, 2) != "28") if (memcmp(BuiltinName.data()+22, "28", 2))
break; break;
return Intrinsic::x86_sse41_pmaxuw; // "__builtin_ia32_ pmaxuw128" return Intrinsic::x86_sse41_pmaxuw; // "__builtin_ia32_ pmaxuw128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(22, 2) != "56") if (memcmp(BuiltinName.data()+22, "56", 2))
break; break;
return Intrinsic::x86_avx2_pmaxu_w; // "__builtin_ia32_ pmaxuw256" return Intrinsic::x86_avx2_pmaxu_w; // "__builtin_ia32_ pmaxuw256"
} }
break; break;
} }
break; break;
} }
break; break;
} }
break; break;
skipping to change at line 36786 skipping to change at line 41886
break; break;
switch (BuiltinName[19]) { switch (BuiltinName[19]) {
default: break; default: break;
case 's': // 6 strings to match. case 's': // 6 strings to match.
switch (BuiltinName[20]) { switch (BuiltinName[20]) {
default: break; default: break;
case 'b': // 2 strings to match. case 'b': // 2 strings to match.
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(22, 2) != "28") if (memcmp(BuiltinName.data()+22, "28", 2))
break; break;
return Intrinsic::x86_sse41_pminsb; // "__builtin_ia32_ pminsb128" return Intrinsic::x86_sse41_pminsb; // "__builtin_ia32_ pminsb128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(22, 2) != "56") if (memcmp(BuiltinName.data()+22, "56", 2))
break; break;
return Intrinsic::x86_avx2_pmins_b; // "__builtin_ia32_ pminsb256" return Intrinsic::x86_avx2_pmins_b; // "__builtin_ia32_ pminsb256"
} }
break; break;
case 'd': // 2 strings to match. case 'd': // 2 strings to match.
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(22, 2) != "28") if (memcmp(BuiltinName.data()+22, "28", 2))
break; break;
return Intrinsic::x86_sse41_pminsd; // "__builtin_ia32_ pminsd128" return Intrinsic::x86_sse41_pminsd; // "__builtin_ia32_ pminsd128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(22, 2) != "56") if (memcmp(BuiltinName.data()+22, "56", 2))
break; break;
return Intrinsic::x86_avx2_pmins_d; // "__builtin_ia32_ pminsd256" return Intrinsic::x86_avx2_pmins_d; // "__builtin_ia32_ pminsd256"
} }
break; break;
case 'w': // 2 strings to match. case 'w': // 2 strings to match.
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(22, 2) != "28") if (memcmp(BuiltinName.data()+22, "28", 2))
break; break;
return Intrinsic::x86_sse2_pmins_w; // "__builtin_ia32_ pminsw128" return Intrinsic::x86_sse2_pmins_w; // "__builtin_ia32_ pminsw128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(22, 2) != "56") if (memcmp(BuiltinName.data()+22, "56", 2))
break; break;
return Intrinsic::x86_avx2_pmins_w; // "__builtin_ia32_ pminsw256" return Intrinsic::x86_avx2_pmins_w; // "__builtin_ia32_ pminsw256"
} }
break; break;
} }
break; break;
case 'u': // 6 strings to match. case 'u': // 6 strings to match.
switch (BuiltinName[20]) { switch (BuiltinName[20]) {
default: break; default: break;
case 'b': // 2 strings to match. case 'b': // 2 strings to match.
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(22, 2) != "28") if (memcmp(BuiltinName.data()+22, "28", 2))
break; break;
return Intrinsic::x86_sse2_pminu_b; // "__builtin_ia32_ pminub128" return Intrinsic::x86_sse2_pminu_b; // "__builtin_ia32_ pminub128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(22, 2) != "56") if (memcmp(BuiltinName.data()+22, "56", 2))
break; break;
return Intrinsic::x86_avx2_pminu_b; // "__builtin_ia32_ pminub256" return Intrinsic::x86_avx2_pminu_b; // "__builtin_ia32_ pminub256"
} }
break; break;
case 'd': // 2 strings to match. case 'd': // 2 strings to match.
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(22, 2) != "28") if (memcmp(BuiltinName.data()+22, "28", 2))
break; break;
return Intrinsic::x86_sse41_pminud; // "__builtin_ia32_ pminud128" return Intrinsic::x86_sse41_pminud; // "__builtin_ia32_ pminud128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(22, 2) != "56") if (memcmp(BuiltinName.data()+22, "56", 2))
break; break;
return Intrinsic::x86_avx2_pminu_d; // "__builtin_ia32_ pminud256" return Intrinsic::x86_avx2_pminu_d; // "__builtin_ia32_ pminud256"
} }
break; break;
case 'w': // 2 strings to match. case 'w': // 2 strings to match.
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(22, 2) != "28") if (memcmp(BuiltinName.data()+22, "28", 2))
break; break;
return Intrinsic::x86_sse41_pminuw; // "__builtin_ia32_ pminuw128" return Intrinsic::x86_sse41_pminuw; // "__builtin_ia32_ pminuw128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(22, 2) != "56") if (memcmp(BuiltinName.data()+22, "56", 2))
break; break;
return Intrinsic::x86_avx2_pminu_w; // "__builtin_ia32_ pminuw256" return Intrinsic::x86_avx2_pminu_w; // "__builtin_ia32_ pminuw256"
} }
break; break;
} }
break; break;
} }
break; break;
case 'u': // 4 strings to match. case 'u': // 4 strings to match.
if (BuiltinName[18] != 'l') if (BuiltinName[18] != 'l')
break; break;
switch (BuiltinName[19]) { switch (BuiltinName[19]) {
default: break; default: break;
case 'd': // 2 strings to match. case 'd': // 2 strings to match.
if (BuiltinName[20] != 'q') if (BuiltinName[20] != 'q')
break; break;
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(22, 2) != "28") if (memcmp(BuiltinName.data()+22, "28", 2))
break; break;
return Intrinsic::x86_sse41_pmuldq; // "__builtin_ia32_ pmuldq128" return Intrinsic::x86_sse41_pmuldq; // "__builtin_ia32_ pmuldq128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(22, 2) != "56") if (memcmp(BuiltinName.data()+22, "56", 2))
break; break;
return Intrinsic::x86_avx2_pmul_dq; // "__builtin_ia32_ pmuldq256" return Intrinsic::x86_avx2_pmul_dq; // "__builtin_ia32_ pmuldq256"
} }
break; break;
case 'h': // 2 strings to match. case 'h': // 2 strings to match.
if (BuiltinName[20] != 'w') if (BuiltinName[20] != 'w')
break; break;
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(22, 2) != "28") if (memcmp(BuiltinName.data()+22, "28", 2))
break; break;
return Intrinsic::x86_sse2_pmulh_w; // "__builtin_ia32_ pmulhw128" return Intrinsic::x86_sse2_pmulh_w; // "__builtin_ia32_ pmulhw128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(22, 2) != "56") if (memcmp(BuiltinName.data()+22, "56", 2))
break; break;
return Intrinsic::x86_avx2_pmulh_w; // "__builtin_ia32_ pmulhw256" return Intrinsic::x86_avx2_pmulh_w; // "__builtin_ia32_ pmulhw256"
} }
break; break;
} }
break; break;
} }
break; break;
case 's': // 30 strings to match. case 's': // 30 strings to match.
switch (BuiltinName[17]) { switch (BuiltinName[17]) {
default: break; default: break;
case 'a': // 2 strings to match. case 'a': // 2 strings to match.
if (BuiltinName.substr(18, 3) != "dbw") if (memcmp(BuiltinName.data()+18, "dbw", 3))
break; break;
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(22, 2) != "28") if (memcmp(BuiltinName.data()+22, "28", 2))
break; break;
return Intrinsic::x86_sse2_psad_bw; // "__builtin_ia32_ psadbw128" return Intrinsic::x86_sse2_psad_bw; // "__builtin_ia32_ psadbw128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(22, 2) != "56") if (memcmp(BuiltinName.data()+22, "56", 2))
break; break;
return Intrinsic::x86_avx2_psad_bw; // "__builtin_ia32_ psadbw256" return Intrinsic::x86_avx2_psad_bw; // "__builtin_ia32_ psadbw256"
} }
break; break;
case 'h': // 2 strings to match. case 'h': // 2 strings to match.
if (BuiltinName.substr(18, 3) != "ufb") if (memcmp(BuiltinName.data()+18, "ufb", 3))
break; break;
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(22, 2) != "28") if (memcmp(BuiltinName.data()+22, "28", 2))
break; break;
return Intrinsic::x86_ssse3_pshuf_b_128; // "__builtin_ia32_ pshufb128" return Intrinsic::x86_ssse3_pshuf_b_128; // "__builtin_ia32_ pshufb128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(22, 2) != "56") if (memcmp(BuiltinName.data()+22, "56", 2))
break; break;
return Intrinsic::x86_avx2_pshuf_b; // "__builtin_ia32_ pshufb256" return Intrinsic::x86_avx2_pshuf_b; // "__builtin_ia32_ pshufb256"
} }
break; break;
case 'i': // 6 strings to match. case 'i': // 6 strings to match.
if (BuiltinName.substr(18, 2) != "gn") if (memcmp(BuiltinName.data()+18, "gn", 2))
break; break;
switch (BuiltinName[20]) { switch (BuiltinName[20]) {
default: break; default: break;
case 'b': // 2 strings to match. case 'b': // 2 strings to match.
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(22, 2) != "28") if (memcmp(BuiltinName.data()+22, "28", 2))
break; break;
return Intrinsic::x86_ssse3_psign_b_128; // "__builtin_ia32_ psignb128" return Intrinsic::x86_ssse3_psign_b_128; // "__builtin_ia32_ psignb128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(22, 2) != "56") if (memcmp(BuiltinName.data()+22, "56", 2))
break; break;
return Intrinsic::x86_avx2_psign_b; // "__builtin_ia32_ psignb256" return Intrinsic::x86_avx2_psign_b; // "__builtin_ia32_ psignb256"
} }
break; break;
case 'd': // 2 strings to match. case 'd': // 2 strings to match.
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(22, 2) != "28") if (memcmp(BuiltinName.data()+22, "28", 2))
break; break;
return Intrinsic::x86_ssse3_psign_d_128; // "__builtin_ia32_ psignd128" return Intrinsic::x86_ssse3_psign_d_128; // "__builtin_ia32_ psignd128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(22, 2) != "56") if (memcmp(BuiltinName.data()+22, "56", 2))
break; break;
return Intrinsic::x86_avx2_psign_d; // "__builtin_ia32_ psignd256" return Intrinsic::x86_avx2_psign_d; // "__builtin_ia32_ psignd256"
} }
break; break;
case 'w': // 2 strings to match. case 'w': // 2 strings to match.
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(22, 2) != "28") if (memcmp(BuiltinName.data()+22, "28", 2))
break; break;
return Intrinsic::x86_ssse3_psign_w_128; // "__builtin_ia32_ psignw128" return Intrinsic::x86_ssse3_psign_w_128; // "__builtin_ia32_ psignw128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(22, 2) != "56") if (memcmp(BuiltinName.data()+22, "56", 2))
break; break;
return Intrinsic::x86_avx2_psign_w; // "__builtin_ia32_ psignw256" return Intrinsic::x86_avx2_psign_w; // "__builtin_ia32_ psignw256"
} }
break; break;
} }
break; break;
case 'l': // 6 strings to match. case 'l': // 6 strings to match.
if (BuiltinName[18] != 'l') if (BuiltinName[18] != 'l')
break; break;
switch (BuiltinName[19]) { switch (BuiltinName[19]) {
default: break; default: break;
case 'd': // 2 strings to match. case 'd': // 2 strings to match.
if (BuiltinName[20] != 'i') if (BuiltinName[20] != 'i')
break; break;
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(22, 2) != "28") if (memcmp(BuiltinName.data()+22, "28", 2))
break; break;
return Intrinsic::x86_sse2_pslli_d; // "__builtin_ia32_ pslldi128" return Intrinsic::x86_sse2_pslli_d; // "__builtin_ia32_ pslldi128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(22, 2) != "56") if (memcmp(BuiltinName.data()+22, "56", 2))
break; break;
return Intrinsic::x86_avx2_pslli_d; // "__builtin_ia32_ pslldi256" return Intrinsic::x86_avx2_pslli_d; // "__builtin_ia32_ pslldi256"
} }
break; break;
case 'q': // 2 strings to match. case 'q': // 2 strings to match.
if (BuiltinName[20] != 'i') if (BuiltinName[20] != 'i')
break; break;
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(22, 2) != "28") if (memcmp(BuiltinName.data()+22, "28", 2))
break; break;
return Intrinsic::x86_sse2_pslli_q; // "__builtin_ia32_ psllqi128" return Intrinsic::x86_sse2_pslli_q; // "__builtin_ia32_ psllqi128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(22, 2) != "56") if (memcmp(BuiltinName.data()+22, "56", 2))
break; break;
return Intrinsic::x86_avx2_pslli_q; // "__builtin_ia32_ psllqi256" return Intrinsic::x86_avx2_pslli_q; // "__builtin_ia32_ psllqi256"
} }
break; break;
case 'w': // 2 strings to match. case 'w': // 2 strings to match.
if (BuiltinName[20] != 'i') if (BuiltinName[20] != 'i')
break; break;
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(22, 2) != "28") if (memcmp(BuiltinName.data()+22, "28", 2))
break; break;
return Intrinsic::x86_sse2_pslli_w; // "__builtin_ia32_ psllwi128" return Intrinsic::x86_sse2_pslli_w; // "__builtin_ia32_ psllwi128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(22, 2) != "56") if (memcmp(BuiltinName.data()+22, "56", 2))
break; break;
return Intrinsic::x86_avx2_pslli_w; // "__builtin_ia32_ psllwi256" return Intrinsic::x86_avx2_pslli_w; // "__builtin_ia32_ psllwi256"
} }
break; break;
} }
break; break;
case 'r': // 10 strings to match. case 'r': // 10 strings to match.
switch (BuiltinName[18]) { switch (BuiltinName[18]) {
default: break; default: break;
case 'a': // 4 strings to match. case 'a': // 4 strings to match.
switch (BuiltinName[19]) { switch (BuiltinName[19]) {
default: break; default: break;
case 'd': // 2 strings to match. case 'd': // 2 strings to match.
if (BuiltinName[20] != 'i') if (BuiltinName[20] != 'i')
break; break;
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(22, 2) != "28") if (memcmp(BuiltinName.data()+22, "28", 2))
break; break;
return Intrinsic::x86_sse2_psrai_d; // "__builtin_ia32_ psradi128" return Intrinsic::x86_sse2_psrai_d; // "__builtin_ia32_ psradi128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(22, 2) != "56") if (memcmp(BuiltinName.data()+22, "56", 2))
break; break;
return Intrinsic::x86_avx2_psrai_d; // "__builtin_ia32_ psradi256" return Intrinsic::x86_avx2_psrai_d; // "__builtin_ia32_ psradi256"
} }
break; break;
case 'w': // 2 strings to match. case 'w': // 2 strings to match.
if (BuiltinName[20] != 'i') if (BuiltinName[20] != 'i')
break; break;
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(22, 2) != "28") if (memcmp(BuiltinName.data()+22, "28", 2))
break; break;
return Intrinsic::x86_sse2_psrai_w; // "__builtin_ia32_ psrawi128" return Intrinsic::x86_sse2_psrai_w; // "__builtin_ia32_ psrawi128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(22, 2) != "56") if (memcmp(BuiltinName.data()+22, "56", 2))
break; break;
return Intrinsic::x86_avx2_psrai_w; // "__builtin_ia32_ psrawi256" return Intrinsic::x86_avx2_psrai_w; // "__builtin_ia32_ psrawi256"
} }
break; break;
} }
break; break;
case 'l': // 6 strings to match. case 'l': // 6 strings to match.
switch (BuiltinName[19]) { switch (BuiltinName[19]) {
default: break; default: break;
case 'd': // 2 strings to match. case 'd': // 2 strings to match.
if (BuiltinName[20] != 'i') if (BuiltinName[20] != 'i')
break; break;
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(22, 2) != "28") if (memcmp(BuiltinName.data()+22, "28", 2))
break; break;
return Intrinsic::x86_sse2_psrli_d; // "__builtin_ia32_ psrldi128" return Intrinsic::x86_sse2_psrli_d; // "__builtin_ia32_ psrldi128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(22, 2) != "56") if (memcmp(BuiltinName.data()+22, "56", 2))
break; break;
return Intrinsic::x86_avx2_psrli_d; // "__builtin_ia32_ psrldi256" return Intrinsic::x86_avx2_psrli_d; // "__builtin_ia32_ psrldi256"
} }
break; break;
case 'q': // 2 strings to match. case 'q': // 2 strings to match.
if (BuiltinName[20] != 'i') if (BuiltinName[20] != 'i')
break; break;
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(22, 2) != "28") if (memcmp(BuiltinName.data()+22, "28", 2))
break; break;
return Intrinsic::x86_sse2_psrli_q; // "__builtin_ia32_ psrlqi128" return Intrinsic::x86_sse2_psrli_q; // "__builtin_ia32_ psrlqi128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(22, 2) != "56") if (memcmp(BuiltinName.data()+22, "56", 2))
break; break;
return Intrinsic::x86_avx2_psrli_q; // "__builtin_ia32_ psrlqi256" return Intrinsic::x86_avx2_psrli_q; // "__builtin_ia32_ psrlqi256"
} }
break; break;
case 'w': // 2 strings to match. case 'w': // 2 strings to match.
if (BuiltinName[20] != 'i') if (BuiltinName[20] != 'i')
break; break;
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(22, 2) != "28") if (memcmp(BuiltinName.data()+22, "28", 2))
break; break;
return Intrinsic::x86_sse2_psrli_w; // "__builtin_ia32_ psrlwi128" return Intrinsic::x86_sse2_psrli_w; // "__builtin_ia32_ psrlwi128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(22, 2) != "56") if (memcmp(BuiltinName.data()+22, "56", 2))
break; break;
return Intrinsic::x86_avx2_psrli_w; // "__builtin_ia32_ psrlwi256" return Intrinsic::x86_avx2_psrli_w; // "__builtin_ia32_ psrlwi256"
} }
break; break;
} }
break; break;
} }
break; break;
case 'u': // 4 strings to match. case 'u': // 4 strings to match.
if (BuiltinName.substr(18, 2) != "bs") if (memcmp(BuiltinName.data()+18, "bs", 2))
break; break;
switch (BuiltinName[20]) { switch (BuiltinName[20]) {
default: break; default: break;
case 'b': // 2 strings to match. case 'b': // 2 strings to match.
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(22, 2) != "28") if (memcmp(BuiltinName.data()+22, "28", 2))
break; break;
return Intrinsic::x86_sse2_psubs_b; // "__builtin_ia32_ psubsb128" return Intrinsic::x86_sse2_psubs_b; // "__builtin_ia32_ psubsb128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(22, 2) != "56") if (memcmp(BuiltinName.data()+22, "56", 2))
break; break;
return Intrinsic::x86_avx2_psubs_b; // "__builtin_ia32_ psubsb256" return Intrinsic::x86_avx2_psubs_b; // "__builtin_ia32_ psubsb256"
} }
break; break;
case 'w': // 2 strings to match. case 'w': // 2 strings to match.
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(22, 2) != "28") if (memcmp(BuiltinName.data()+22, "28", 2))
break; break;
return Intrinsic::x86_sse2_psubs_w; // "__builtin_ia32_ psubsw128" return Intrinsic::x86_sse2_psubs_w; // "__builtin_ia32_ psubsw128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(22, 2) != "56") if (memcmp(BuiltinName.data()+22, "56", 2))
break; break;
return Intrinsic::x86_avx2_psubs_w; // "__builtin_ia32_ psubsw256" return Intrinsic::x86_avx2_psubs_w; // "__builtin_ia32_ psubsw256"
} }
break; break;
} }
break; break;
} }
break; break;
case 't': // 4 strings to match. case 't': // 4 strings to match.
if (BuiltinName.substr(17, 3) != "est") if (memcmp(BuiltinName.data()+17, "est", 3))
break; break;
switch (BuiltinName[20]) { switch (BuiltinName[20]) {
default: break; default: break;
case 'c': // 2 strings to match. case 'c': // 2 strings to match.
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(22, 2) != "28") if (memcmp(BuiltinName.data()+22, "28", 2))
break; break;
return Intrinsic::x86_sse41_ptestc; // "__builtin_ia32_ ptestc128" return Intrinsic::x86_sse41_ptestc; // "__builtin_ia32_ ptestc128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(22, 2) != "56") if (memcmp(BuiltinName.data()+22, "56", 2))
break; break;
return Intrinsic::x86_avx_ptestc_256; // "__builtin_ia32_ ptestc256" return Intrinsic::x86_avx_ptestc_256; // "__builtin_ia32_ ptestc256"
} }
break; break;
case 'z': // 2 strings to match. case 'z': // 2 strings to match.
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(22, 2) != "28") if (memcmp(BuiltinName.data()+22, "28", 2))
break; break;
return Intrinsic::x86_sse41_ptestz; // "__builtin_ia32_ ptestz128" return Intrinsic::x86_sse41_ptestz; // "__builtin_ia32_ ptestz128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(22, 2) != "56") if (memcmp(BuiltinName.data()+22, "56", 2))
break; break;
return Intrinsic::x86_avx_ptestz_256; // "__builtin_ia32_ ptestz256" return Intrinsic::x86_avx_ptestz_256; // "__builtin_ia32_ ptestz256"
} }
break; break;
} }
break; break;
case 'u': // 6 strings to match. case 'u': // 6 strings to match.
if (BuiltinName.substr(17, 4) != "npck") if (memcmp(BuiltinName.data()+17, "npck", 4))
break; break;
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case 'h': // 3 strings to match. case 'h': // 3 strings to match.
switch (BuiltinName[22]) { switch (BuiltinName[22]) {
default: break; default: break;
case 'b': // 1 string to match. case 'b': // 1 string to match.
if (BuiltinName[23] != 'w') if (BuiltinName[23] != 'w')
break; break;
return Intrinsic::x86_mmx_punpckhbw; // "__builtin_ia32_ punpckhbw" return Intrinsic::x86_mmx_punpckhbw; // "__builtin_ia32_ punpckhbw"
skipping to change at line 37241 skipping to change at line 42341
if (BuiltinName[23] != 'd') if (BuiltinName[23] != 'd')
break; break;
return Intrinsic::x86_mmx_punpcklwd; // "__builtin_ia32_ punpcklwd" return Intrinsic::x86_mmx_punpcklwd; // "__builtin_ia32_ punpcklwd"
} }
break; break;
} }
break; break;
} }
break; break;
case 's': // 2 strings to match. case 's': // 2 strings to match.
if (BuiltinName.substr(16, 4) != "qrtp") if (memcmp(BuiltinName.data()+16, "qrtp", 4))
break; break;
switch (BuiltinName[20]) { switch (BuiltinName[20]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
if (BuiltinName.substr(21, 3) != "256") if (memcmp(BuiltinName.data()+21, "256", 3))
break; break;
return Intrinsic::x86_avx_sqrt_pd_256; // "__builtin_ia32_sqrtpd25 6" return Intrinsic::x86_avx_sqrt_pd_256; // "__builtin_ia32_sqrtpd25 6"
case 's': // 1 string to match. case 's': // 1 string to match.
if (BuiltinName.substr(21, 3) != "256") if (memcmp(BuiltinName.data()+21, "256", 3))
break; break;
return Intrinsic::x86_avx_sqrt_ps_256; // "__builtin_ia32_sqrtps25 6" return Intrinsic::x86_avx_sqrt_ps_256; // "__builtin_ia32_sqrtps25 6"
} }
break; break;
case 'u': // 5 strings to match. case 'u': // 5 strings to match.
if (BuiltinName.substr(16, 6) != "comisd") if (memcmp(BuiltinName.data()+16, "comisd", 6))
break; break;
switch (BuiltinName[22]) { switch (BuiltinName[22]) {
default: break; default: break;
case 'e': // 1 string to match. case 'e': // 1 string to match.
if (BuiltinName[23] != 'q') if (BuiltinName[23] != 'q')
break; break;
return Intrinsic::x86_sse2_ucomieq_sd; // "__builtin_ia32_ucomisde q" return Intrinsic::x86_sse2_ucomieq_sd; // "__builtin_ia32_ucomisde q"
case 'g': // 2 strings to match. case 'g': // 2 strings to match.
switch (BuiltinName[23]) { switch (BuiltinName[23]) {
default: break; default: break;
skipping to change at line 37288 skipping to change at line 42388
case 't': // 1 string to match. case 't': // 1 string to match.
return Intrinsic::x86_sse2_ucomilt_sd; // "__builtin_ia32_ ucomisdlt" return Intrinsic::x86_sse2_ucomilt_sd; // "__builtin_ia32_ ucomisdlt"
} }
break; break;
} }
break; break;
case 'v': // 10 strings to match. case 'v': // 10 strings to match.
switch (BuiltinName[16]) { switch (BuiltinName[16]) {
default: break; default: break;
case 'c': // 2 strings to match. case 'c': // 2 strings to match.
if (BuiltinName.substr(17, 3) != "vtp") if (memcmp(BuiltinName.data()+17, "vtp", 3))
break; break;
switch (BuiltinName[20]) { switch (BuiltinName[20]) {
default: break; default: break;
case 'h': // 1 string to match. case 'h': // 1 string to match.
if (BuiltinName.substr(21, 3) != "2ps") if (memcmp(BuiltinName.data()+21, "2ps", 3))
break; break;
return Intrinsic::x86_vcvtph2ps_128; // "__builtin_ia32_vcvtph2p s" return Intrinsic::x86_vcvtph2ps_128; // "__builtin_ia32_vcvtph2p s"
case 's': // 1 string to match. case 's': // 1 string to match.
if (BuiltinName.substr(21, 3) != "2ph") if (memcmp(BuiltinName.data()+21, "2ph", 3))
break; break;
return Intrinsic::x86_vcvtps2ph_128; // "__builtin_ia32_vcvtps2p h" return Intrinsic::x86_vcvtps2ph_128; // "__builtin_ia32_vcvtps2p h"
} }
break; break;
case 'f': // 8 strings to match. case 'f': // 8 strings to match.
if (BuiltinName.substr(17, 2) != "nm") if (memcmp(BuiltinName.data()+17, "nm", 2))
break; break;
switch (BuiltinName[19]) { switch (BuiltinName[19]) {
default: break; default: break;
case 'a': // 4 strings to match. case 'a': // 4 strings to match.
if (BuiltinName.substr(20, 2) != "dd") if (memcmp(BuiltinName.data()+20, "dd", 2))
break; break;
switch (BuiltinName[22]) { switch (BuiltinName[22]) {
default: break; default: break;
case 'p': // 2 strings to match. case 'p': // 2 strings to match.
switch (BuiltinName[23]) { switch (BuiltinName[23]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
return Intrinsic::x86_fma4_vfnmadd_pd; // "__builtin_ia32_ vfnmaddpd" return Intrinsic::x86_fma_vfnmadd_pd; // "__builtin_ia32_ vfnmaddpd"
case 's': // 1 string to match. case 's': // 1 string to match.
return Intrinsic::x86_fma4_vfnmadd_ps; // "__builtin_ia32_ vfnmaddps" return Intrinsic::x86_fma_vfnmadd_ps; // "__builtin_ia32_ vfnmaddps"
} }
break; break;
case 's': // 2 strings to match. case 's': // 2 strings to match.
switch (BuiltinName[23]) { switch (BuiltinName[23]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
return Intrinsic::x86_fma4_vfnmadd_sd; // "__builtin_ia32_ vfnmaddsd" return Intrinsic::x86_fma_vfnmadd_sd; // "__builtin_ia32_ vfnmaddsd"
case 's': // 1 string to match. case 's': // 1 string to match.
return Intrinsic::x86_fma4_vfnmadd_ss; // "__builtin_ia32_ vfnmaddss" return Intrinsic::x86_fma_vfnmadd_ss; // "__builtin_ia32_ vfnmaddss"
} }
break; break;
} }
break; break;
case 's': // 4 strings to match. case 's': // 4 strings to match.
if (BuiltinName.substr(20, 2) != "ub") if (memcmp(BuiltinName.data()+20, "ub", 2))
break; break;
switch (BuiltinName[22]) { switch (BuiltinName[22]) {
default: break; default: break;
case 'p': // 2 strings to match. case 'p': // 2 strings to match.
switch (BuiltinName[23]) { switch (BuiltinName[23]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
return Intrinsic::x86_fma4_vfnmsub_pd; // "__builtin_ia32_ vfnmsubpd" return Intrinsic::x86_fma_vfnmsub_pd; // "__builtin_ia32_ vfnmsubpd"
case 's': // 1 string to match. case 's': // 1 string to match.
return Intrinsic::x86_fma4_vfnmsub_ps; // "__builtin_ia32_ vfnmsubps" return Intrinsic::x86_fma_vfnmsub_ps; // "__builtin_ia32_ vfnmsubps"
} }
break; break;
case 's': // 2 strings to match. case 's': // 2 strings to match.
switch (BuiltinName[23]) { switch (BuiltinName[23]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
return Intrinsic::x86_fma4_vfnmsub_sd; // "__builtin_ia32_ vfnmsubsd" return Intrinsic::x86_fma_vfnmsub_sd; // "__builtin_ia32_ vfnmsubsd"
case 's': // 1 string to match. case 's': // 1 string to match.
return Intrinsic::x86_fma4_vfnmsub_ss; // "__builtin_ia32_ vfnmsubss" return Intrinsic::x86_fma_vfnmsub_ss; // "__builtin_ia32_ vfnmsubss"
} }
break; break;
} }
break; break;
} }
break; break;
} }
break; break;
} }
break; break;
case 25: // 58 strings to match. case 25: // 59 strings to match.
if (BuiltinName.substr(0, 15) != "__builtin_ia32_") if (memcmp(BuiltinName.data()+0, "__builtin_ia32_", 15))
break; break;
switch (BuiltinName[15]) { switch (BuiltinName[15]) {
default: break; default: break;
case 'b': // 2 strings to match. case 'b': // 2 strings to match.
if (BuiltinName.substr(16, 5) != "lendp") if (memcmp(BuiltinName.data()+16, "lendp", 5))
break; break;
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
if (BuiltinName.substr(22, 3) != "256") if (memcmp(BuiltinName.data()+22, "256", 3))
break; break;
return Intrinsic::x86_avx_blend_pd_256; // "__builtin_ia32_ blendpd256" return Intrinsic::x86_avx_blend_pd_256; // "__builtin_ia32_ blendpd256"
case 's': // 1 string to match. case 's': // 1 string to match.
if (BuiltinName.substr(22, 3) != "256") if (memcmp(BuiltinName.data()+22, "256", 3))
break; break;
return Intrinsic::x86_avx_blend_ps_256; // "__builtin_ia32_ blendps256" return Intrinsic::x86_avx_blend_ps_256; // "__builtin_ia32_ blendps256"
} }
break; break;
case 'c': // 4 strings to match. case 'c': // 4 strings to match.
if (BuiltinName.substr(16, 3) != "vts") if (memcmp(BuiltinName.data()+16, "vts", 3))
break; break;
switch (BuiltinName[19]) { switch (BuiltinName[19]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
if (BuiltinName.substr(20, 5) != "2si64") if (memcmp(BuiltinName.data()+20, "2si64", 5))
break; break;
return Intrinsic::x86_sse2_cvtsd2si64; // "__builtin_ia32_cvtsd2si 64" return Intrinsic::x86_sse2_cvtsd2si64; // "__builtin_ia32_cvtsd2si 64"
case 'i': // 2 strings to match. case 'i': // 2 strings to match.
if (BuiltinName.substr(20, 4) != "642s") if (memcmp(BuiltinName.data()+20, "642s", 4))
break; break;
switch (BuiltinName[24]) { switch (BuiltinName[24]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
return Intrinsic::x86_sse2_cvtsi642sd; // "__builtin_ia32_ cvtsi642sd" return Intrinsic::x86_sse2_cvtsi642sd; // "__builtin_ia32_ cvtsi642sd"
case 's': // 1 string to match. case 's': // 1 string to match.
return Intrinsic::x86_sse_cvtsi642ss; // "__builtin_ia32_ cvtsi642ss" return Intrinsic::x86_sse_cvtsi642ss; // "__builtin_ia32_ cvtsi642ss"
} }
break; break;
case 's': // 1 string to match. case 's': // 1 string to match.
if (BuiltinName.substr(20, 5) != "2si64") if (memcmp(BuiltinName.data()+20, "2si64", 5))
break; break;
return Intrinsic::x86_sse_cvtss2si64; // "__builtin_ia32_cvtss2si 64" return Intrinsic::x86_sse_cvtss2si64; // "__builtin_ia32_cvtss2si 64"
} }
break; break;
case 'm': // 10 strings to match. case 'g': // 4 strings to match.
if (memcmp(BuiltinName.data()+16, "ather", 5))
break;
switch (BuiltinName[21]) {
default: break;
case 'd': // 2 strings to match.
if (memcmp(BuiltinName.data()+22, "_p", 2))
break;
switch (BuiltinName[24]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::x86_avx2_gather_d_pd; // "__builtin_ia32_
gatherd_pd"
case 's': // 1 string to match.
return Intrinsic::x86_avx2_gather_d_ps; // "__builtin_ia32_
gatherd_ps"
}
break;
case 'q': // 2 strings to match.
if (memcmp(BuiltinName.data()+22, "_p", 2))
break;
switch (BuiltinName[24]) {
default: break;
case 'd': // 1 string to match.
return Intrinsic::x86_avx2_gather_q_pd; // "__builtin_ia32_
gatherq_pd"
case 's': // 1 string to match.
return Intrinsic::x86_avx2_gather_q_ps; // "__builtin_ia32_
gatherq_ps"
}
break;
}
break;
case 'm': // 7 strings to match.
switch (BuiltinName[16]) { switch (BuiltinName[16]) {
default: break; default: break;
case 'a': // 5 strings to match. case 'a': // 5 strings to match.
if (BuiltinName.substr(17, 2) != "sk") if (memcmp(BuiltinName.data()+17, "sk", 2))
break; break;
switch (BuiltinName[19]) { switch (BuiltinName[19]) {
default: break; default: break;
case 'l': // 2 strings to match. case 'l': // 2 strings to match.
if (BuiltinName.substr(20, 4) != "oadp") if (memcmp(BuiltinName.data()+20, "oadp", 4))
break; break;
switch (BuiltinName[24]) { switch (BuiltinName[24]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
return Intrinsic::x86_avx_maskload_pd; // "__builtin_ia32_ maskloadpd" return Intrinsic::x86_avx_maskload_pd; // "__builtin_ia32_ maskloadpd"
case 's': // 1 string to match. case 's': // 1 string to match.
return Intrinsic::x86_avx_maskload_ps; // "__builtin_ia32_ maskloadps" return Intrinsic::x86_avx_maskload_ps; // "__builtin_ia32_ maskloadps"
} }
break; break;
case 'm': // 1 string to match. case 'm': // 1 string to match.
if (BuiltinName.substr(20, 5) != "ovdqu") if (memcmp(BuiltinName.data()+20, "ovdqu", 5))
break; break;
return Intrinsic::x86_sse2_maskmov_dqu; // "__builtin_ia32_ maskmovdqu" return Intrinsic::x86_sse2_maskmov_dqu; // "__builtin_ia32_ maskmovdqu"
case 's': // 2 strings to match. case 's': // 2 strings to match.
if (BuiltinName.substr(20, 4) != "tore") if (memcmp(BuiltinName.data()+20, "tore", 4))
break; break;
switch (BuiltinName[24]) { switch (BuiltinName[24]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
return Intrinsic::x86_avx2_maskstore_d; // "__builtin_ia32_ maskstored" return Intrinsic::x86_avx2_maskstore_d; // "__builtin_ia32_ maskstored"
case 'q': // 1 string to match. case 'q': // 1 string to match.
return Intrinsic::x86_avx2_maskstore_q; // "__builtin_ia32_ maskstoreq" return Intrinsic::x86_avx2_maskstore_q; // "__builtin_ia32_ maskstoreq"
} }
break; break;
} }
break; break;
case 'o': // 3 strings to match.
if (BuiltinName.substr(17, 3) != "vnt")
break;
switch (BuiltinName[20]) {
default: break;
case 'd': // 1 string to match.
if (BuiltinName.substr(21, 4) != "q256")
break;
return Intrinsic::x86_avx_movnt_dq_256; // "__builtin_ia32_
movntdq256"
case 'p': // 2 strings to match.
switch (BuiltinName[21]) {
default: break;
case 'd': // 1 string to match.
if (BuiltinName.substr(22, 3) != "256")
break;
return Intrinsic::x86_avx_movnt_pd_256; // "__builtin_ia32_
movntpd256"
case 's': // 1 string to match.
if (BuiltinName.substr(22, 3) != "256")
break;
return Intrinsic::x86_avx_movnt_ps_256; // "__builtin_ia32_
movntps256"
}
break;
}
break;
case 'p': // 2 strings to match. case 'p': // 2 strings to match.
if (BuiltinName.substr(17, 5) != "sadbw") if (memcmp(BuiltinName.data()+17, "sadbw", 5))
break; break;
switch (BuiltinName[22]) { switch (BuiltinName[22]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(23, 2) != "28") if (memcmp(BuiltinName.data()+23, "28", 2))
break; break;
return Intrinsic::x86_sse41_mpsadbw; // "__builtin_ia32_mpsadbw1 28" return Intrinsic::x86_sse41_mpsadbw; // "__builtin_ia32_mpsadbw1 28"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(23, 2) != "56") if (memcmp(BuiltinName.data()+23, "56", 2))
break; break;
return Intrinsic::x86_avx2_mpsadbw; // "__builtin_ia32_mpsadbw2 56" return Intrinsic::x86_avx2_mpsadbw; // "__builtin_ia32_mpsadbw2 56"
} }
break; break;
} }
break; break;
case 'p': // 26 strings to match. case 'p': // 26 strings to match.
switch (BuiltinName[16]) { switch (BuiltinName[16]) {
default: break; default: break;
case 'a': // 4 strings to match. case 'a': // 4 strings to match.
if (BuiltinName.substr(17, 4) != "ddus") if (memcmp(BuiltinName.data()+17, "ddus", 4))
break; break;
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case 'b': // 2 strings to match. case 'b': // 2 strings to match.
switch (BuiltinName[22]) { switch (BuiltinName[22]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(23, 2) != "28") if (memcmp(BuiltinName.data()+23, "28", 2))
break; break;
return Intrinsic::x86_sse2_paddus_b; // "__builtin_ia32_ paddusb128" return Intrinsic::x86_sse2_paddus_b; // "__builtin_ia32_ paddusb128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(23, 2) != "56") if (memcmp(BuiltinName.data()+23, "56", 2))
break; break;
return Intrinsic::x86_avx2_paddus_b; // "__builtin_ia32_ paddusb256" return Intrinsic::x86_avx2_paddus_b; // "__builtin_ia32_ paddusb256"
} }
break; break;
case 'w': // 2 strings to match. case 'w': // 2 strings to match.
switch (BuiltinName[22]) { switch (BuiltinName[22]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(23, 2) != "28") if (memcmp(BuiltinName.data()+23, "28", 2))
break; break;
return Intrinsic::x86_sse2_paddus_w; // "__builtin_ia32_ paddusw128" return Intrinsic::x86_sse2_paddus_w; // "__builtin_ia32_ paddusw128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(23, 2) != "56") if (memcmp(BuiltinName.data()+23, "56", 2))
break; break;
return Intrinsic::x86_avx2_paddus_w; // "__builtin_ia32_ paddusw256" return Intrinsic::x86_avx2_paddus_w; // "__builtin_ia32_ paddusw256"
} }
break; break;
} }
break; break;
case 'b': // 4 strings to match. case 'b': // 4 strings to match.
if (BuiltinName.substr(17, 4) != "lend") if (memcmp(BuiltinName.data()+17, "lend", 4))
break; break;
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case 'd': // 2 strings to match. case 'd': // 2 strings to match.
switch (BuiltinName[22]) { switch (BuiltinName[22]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(23, 2) != "28") if (memcmp(BuiltinName.data()+23, "28", 2))
break; break;
return Intrinsic::x86_avx2_pblendd_128; // "__builtin_ia32_ pblendd128" return Intrinsic::x86_avx2_pblendd_128; // "__builtin_ia32_ pblendd128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(23, 2) != "56") if (memcmp(BuiltinName.data()+23, "56", 2))
break; break;
return Intrinsic::x86_avx2_pblendd_256; // "__builtin_ia32_ pblendd256" return Intrinsic::x86_avx2_pblendd_256; // "__builtin_ia32_ pblendd256"
} }
break; break;
case 'w': // 2 strings to match. case 'w': // 2 strings to match.
switch (BuiltinName[22]) { switch (BuiltinName[22]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(23, 2) != "28") if (memcmp(BuiltinName.data()+23, "28", 2))
break; break;
return Intrinsic::x86_sse41_pblendw; // "__builtin_ia32_ pblendw128" return Intrinsic::x86_sse41_pblendw; // "__builtin_ia32_ pblendw128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(23, 2) != "56") if (memcmp(BuiltinName.data()+23, "56", 2))
break; break;
return Intrinsic::x86_avx2_pblendw; // "__builtin_ia32_ pblendw256" return Intrinsic::x86_avx2_pblendw; // "__builtin_ia32_ pblendw256"
} }
break; break;
} }
break; break;
case 'h': // 4 strings to match. case 'h': // 4 strings to match.
switch (BuiltinName[17]) { switch (BuiltinName[17]) {
default: break; default: break;
case 'a': // 2 strings to match. case 'a': // 2 strings to match.
if (BuiltinName.substr(18, 4) != "ddsw") if (memcmp(BuiltinName.data()+18, "ddsw", 4))
break; break;
switch (BuiltinName[22]) { switch (BuiltinName[22]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(23, 2) != "28") if (memcmp(BuiltinName.data()+23, "28", 2))
break; break;
return Intrinsic::x86_ssse3_phadd_sw_128; // "__builtin_ia32_ phaddsw128" return Intrinsic::x86_ssse3_phadd_sw_128; // "__builtin_ia32_ phaddsw128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(23, 2) != "56") if (memcmp(BuiltinName.data()+23, "56", 2))
break; break;
return Intrinsic::x86_avx2_phadd_sw; // "__builtin_ia32_ phaddsw256" return Intrinsic::x86_avx2_phadd_sw; // "__builtin_ia32_ phaddsw256"
} }
break; break;
case 's': // 2 strings to match. case 's': // 2 strings to match.
if (BuiltinName.substr(18, 4) != "ubsw") if (memcmp(BuiltinName.data()+18, "ubsw", 4))
break; break;
switch (BuiltinName[22]) { switch (BuiltinName[22]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(23, 2) != "28") if (memcmp(BuiltinName.data()+23, "28", 2))
break; break;
return Intrinsic::x86_ssse3_phsub_sw_128; // "__builtin_ia32_ phsubsw128" return Intrinsic::x86_ssse3_phsub_sw_128; // "__builtin_ia32_ phsubsw128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(23, 2) != "56") if (memcmp(BuiltinName.data()+23, "56", 2))
break; break;
return Intrinsic::x86_avx2_phsub_sw; // "__builtin_ia32_ phsubsw256" return Intrinsic::x86_avx2_phsub_sw; // "__builtin_ia32_ phsubsw256"
} }
break; break;
} }
break; break;
case 'm': // 6 strings to match. case 'm': // 6 strings to match.
switch (BuiltinName[17]) { switch (BuiltinName[17]) {
default: break; default: break;
case 'a': // 2 strings to match. case 'a': // 2 strings to match.
if (BuiltinName.substr(18, 4) != "ddwd") if (memcmp(BuiltinName.data()+18, "ddwd", 4))
break; break;
switch (BuiltinName[22]) { switch (BuiltinName[22]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(23, 2) != "28") if (memcmp(BuiltinName.data()+23, "28", 2))
break; break;
return Intrinsic::x86_sse2_pmadd_wd; // "__builtin_ia32_ pmaddwd128" return Intrinsic::x86_sse2_pmadd_wd; // "__builtin_ia32_ pmaddwd128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(23, 2) != "56") if (memcmp(BuiltinName.data()+23, "56", 2))
break; break;
return Intrinsic::x86_avx2_pmadd_wd; // "__builtin_ia32_ pmaddwd256" return Intrinsic::x86_avx2_pmadd_wd; // "__builtin_ia32_ pmaddwd256"
} }
break; break;
case 'u': // 4 strings to match. case 'u': // 4 strings to match.
if (BuiltinName[18] != 'l') if (BuiltinName[18] != 'l')
break; break;
switch (BuiltinName[19]) { switch (BuiltinName[19]) {
default: break; default: break;
case 'h': // 2 strings to match. case 'h': // 2 strings to match.
if (BuiltinName.substr(20, 2) != "uw") if (memcmp(BuiltinName.data()+20, "uw", 2))
break; break;
switch (BuiltinName[22]) { switch (BuiltinName[22]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(23, 2) != "28") if (memcmp(BuiltinName.data()+23, "28", 2))
break; break;
return Intrinsic::x86_sse2_pmulhu_w; // "__builtin_ia32_ pmulhuw128" return Intrinsic::x86_sse2_pmulhu_w; // "__builtin_ia32_ pmulhuw128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(23, 2) != "56") if (memcmp(BuiltinName.data()+23, "56", 2))
break; break;
return Intrinsic::x86_avx2_pmulhu_w; // "__builtin_ia32_ pmulhuw256" return Intrinsic::x86_avx2_pmulhu_w; // "__builtin_ia32_ pmulhuw256"
} }
break; break;
case 'u': // 2 strings to match. case 'u': // 2 strings to match.
if (BuiltinName.substr(20, 2) != "dq") if (memcmp(BuiltinName.data()+20, "dq", 2))
break; break;
switch (BuiltinName[22]) { switch (BuiltinName[22]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(23, 2) != "28") if (memcmp(BuiltinName.data()+23, "28", 2))
break; break;
return Intrinsic::x86_sse2_pmulu_dq; // "__builtin_ia32_ pmuludq128" return Intrinsic::x86_sse2_pmulu_dq; // "__builtin_ia32_ pmuludq128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(23, 2) != "56") if (memcmp(BuiltinName.data()+23, "56", 2))
break; break;
return Intrinsic::x86_avx2_pmulu_dq; // "__builtin_ia32_ pmuludq256" return Intrinsic::x86_avx2_pmulu_dq; // "__builtin_ia32_ pmuludq256"
} }
break; break;
} }
break; break;
} }
break; break;
case 's': // 8 strings to match. case 's': // 8 strings to match.
switch (BuiltinName[17]) { switch (BuiltinName[17]) {
default: break; default: break;
case 'l': // 2 strings to match. case 'l': // 2 strings to match.
if (BuiltinName.substr(18, 4) != "ldqi") if (memcmp(BuiltinName.data()+18, "ldqi", 4))
break; break;
switch (BuiltinName[22]) { switch (BuiltinName[22]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(23, 2) != "28") if (memcmp(BuiltinName.data()+23, "28", 2))
break; break;
return Intrinsic::x86_sse2_psll_dq; // "__builtin_ia32_ pslldqi128" return Intrinsic::x86_sse2_psll_dq; // "__builtin_ia32_ pslldqi128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(23, 2) != "56") if (memcmp(BuiltinName.data()+23, "56", 2))
break; break;
return Intrinsic::x86_avx2_psll_dq; // "__builtin_ia32_ pslldqi256" return Intrinsic::x86_avx2_psll_dq; // "__builtin_ia32_ pslldqi256"
} }
break; break;
case 'r': // 2 strings to match. case 'r': // 2 strings to match.
if (BuiltinName.substr(18, 4) != "ldqi") if (memcmp(BuiltinName.data()+18, "ldqi", 4))
break; break;
switch (BuiltinName[22]) { switch (BuiltinName[22]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(23, 2) != "28") if (memcmp(BuiltinName.data()+23, "28", 2))
break; break;
return Intrinsic::x86_sse2_psrl_dq; // "__builtin_ia32_ psrldqi128" return Intrinsic::x86_sse2_psrl_dq; // "__builtin_ia32_ psrldqi128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(23, 2) != "56") if (memcmp(BuiltinName.data()+23, "56", 2))
break; break;
return Intrinsic::x86_avx2_psrl_dq; // "__builtin_ia32_ psrldqi256" return Intrinsic::x86_avx2_psrl_dq; // "__builtin_ia32_ psrldqi256"
} }
break; break;
case 'u': // 4 strings to match. case 'u': // 4 strings to match.
if (BuiltinName.substr(18, 3) != "bus") if (memcmp(BuiltinName.data()+18, "bus", 3))
break; break;
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case 'b': // 2 strings to match. case 'b': // 2 strings to match.
switch (BuiltinName[22]) { switch (BuiltinName[22]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(23, 2) != "28") if (memcmp(BuiltinName.data()+23, "28", 2))
break; break;
return Intrinsic::x86_sse2_psubus_b; // "__builtin_ia32_ psubusb128" return Intrinsic::x86_sse2_psubus_b; // "__builtin_ia32_ psubusb128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(23, 2) != "56") if (memcmp(BuiltinName.data()+23, "56", 2))
break; break;
return Intrinsic::x86_avx2_psubus_b; // "__builtin_ia32_ psubusb256" return Intrinsic::x86_avx2_psubus_b; // "__builtin_ia32_ psubusb256"
} }
break; break;
case 'w': // 2 strings to match. case 'w': // 2 strings to match.
switch (BuiltinName[22]) { switch (BuiltinName[22]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(23, 2) != "28") if (memcmp(BuiltinName.data()+23, "28", 2))
break; break;
return Intrinsic::x86_sse2_psubus_w; // "__builtin_ia32_ psubusw128" return Intrinsic::x86_sse2_psubus_w; // "__builtin_ia32_ psubusw128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(23, 2) != "56") if (memcmp(BuiltinName.data()+23, "56", 2))
break; break;
return Intrinsic::x86_avx2_psubus_w; // "__builtin_ia32_ psubusw256" return Intrinsic::x86_avx2_psubus_w; // "__builtin_ia32_ psubusw256"
} }
break; break;
} }
break; break;
} }
break; break;
} }
break; break;
case 'r': // 7 strings to match. case 'r': // 7 strings to match.
switch (BuiltinName[16]) { switch (BuiltinName[16]) {
default: break; default: break;
case 'd': // 4 strings to match. case 'd': // 4 strings to match.
switch (BuiltinName[17]) { switch (BuiltinName[17]) {
default: break; default: break;
case 'f': // 2 strings to match. case 'f': // 2 strings to match.
if (BuiltinName.substr(18, 5) != "sbase") if (memcmp(BuiltinName.data()+18, "sbase", 5))
break; break;
switch (BuiltinName[23]) { switch (BuiltinName[23]) {
default: break; default: break;
case '3': // 1 string to match. case '3': // 1 string to match.
if (BuiltinName[24] != '2') if (BuiltinName[24] != '2')
break; break;
return Intrinsic::x86_rdfsbase_32; // "__builtin_ia32_rdfsbase 32" return Intrinsic::x86_rdfsbase_32; // "__builtin_ia32_rdfsbase 32"
case '6': // 1 string to match. case '6': // 1 string to match.
if (BuiltinName[24] != '4') if (BuiltinName[24] != '4')
break; break;
return Intrinsic::x86_rdfsbase_64; // "__builtin_ia32_rdfsbase 64" return Intrinsic::x86_rdfsbase_64; // "__builtin_ia32_rdfsbase 64"
} }
break; break;
case 'g': // 2 strings to match. case 'g': // 2 strings to match.
if (BuiltinName.substr(18, 5) != "sbase") if (memcmp(BuiltinName.data()+18, "sbase", 5))
break; break;
switch (BuiltinName[23]) { switch (BuiltinName[23]) {
default: break; default: break;
case '3': // 1 string to match. case '3': // 1 string to match.
if (BuiltinName[24] != '2') if (BuiltinName[24] != '2')
break; break;
return Intrinsic::x86_rdgsbase_32; // "__builtin_ia32_rdgsbase 32" return Intrinsic::x86_rdgsbase_32; // "__builtin_ia32_rdgsbase 32"
case '6': // 1 string to match. case '6': // 1 string to match.
if (BuiltinName[24] != '4') if (BuiltinName[24] != '4')
break; break;
return Intrinsic::x86_rdgsbase_64; // "__builtin_ia32_rdgsbase 64" return Intrinsic::x86_rdgsbase_64; // "__builtin_ia32_rdgsbase 64"
} }
break; break;
} }
break; break;
case 'o': // 2 strings to match. case 'o': // 2 strings to match.
if (BuiltinName.substr(17, 4) != "undp") if (memcmp(BuiltinName.data()+17, "undp", 4))
break; break;
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
if (BuiltinName.substr(22, 3) != "256") if (memcmp(BuiltinName.data()+22, "256", 3))
break; break;
return Intrinsic::x86_avx_round_pd_256; // "__builtin_ia32_ roundpd256" return Intrinsic::x86_avx_round_pd_256; // "__builtin_ia32_ roundpd256"
case 's': // 1 string to match. case 's': // 1 string to match.
if (BuiltinName.substr(22, 3) != "256") if (memcmp(BuiltinName.data()+22, "256", 3))
break; break;
return Intrinsic::x86_avx_round_ps_256; // "__builtin_ia32_ roundps256" return Intrinsic::x86_avx_round_ps_256; // "__builtin_ia32_ roundps256"
} }
break; break;
case 's': // 1 string to match. case 's': // 1 string to match.
if (BuiltinName.substr(17, 8) != "qrtps256") if (memcmp(BuiltinName.data()+17, "qrtps256", 8))
break; break;
return Intrinsic::x86_avx_rsqrt_ps_256; // "__builtin_ia32_ rsqrtps256" return Intrinsic::x86_avx_rsqrt_ps_256; // "__builtin_ia32_ rsqrtps256"
} }
break; break;
case 's': // 1 string to match. case 's': // 1 string to match.
if (BuiltinName.substr(16, 9) != "torelv4si") if (memcmp(BuiltinName.data()+16, "torelv4si", 9))
break; break;
return Intrinsic::x86_sse2_storel_dq; // "__builtin_ia32_storelv4 si" return Intrinsic::x86_sse2_storel_dq; // "__builtin_ia32_storelv4 si"
case 'u': // 1 string to match. case 'u': // 1 string to match.
if (BuiltinName.substr(16, 9) != "comisdneq") if (memcmp(BuiltinName.data()+16, "comisdneq", 9))
break; break;
return Intrinsic::x86_sse2_ucomineq_sd; // "__builtin_ia32_ucomisdn eq" return Intrinsic::x86_sse2_ucomineq_sd; // "__builtin_ia32_ucomisdn eq"
case 'v': // 3 strings to match. case 'v': // 3 strings to match.
switch (BuiltinName[16]) { switch (BuiltinName[16]) {
default: break; default: break;
case 't': // 2 strings to match. case 't': // 2 strings to match.
if (BuiltinName.substr(17, 7) != "estnzcp") if (memcmp(BuiltinName.data()+17, "estnzcp", 7))
break; break;
switch (BuiltinName[24]) { switch (BuiltinName[24]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
return Intrinsic::x86_avx_vtestnzc_pd; // "__builtin_ia32_ vtestnzcpd" return Intrinsic::x86_avx_vtestnzc_pd; // "__builtin_ia32_ vtestnzcpd"
case 's': // 1 string to match. case 's': // 1 string to match.
return Intrinsic::x86_avx_vtestnzc_ps; // "__builtin_ia32_ vtestnzcps" return Intrinsic::x86_avx_vtestnzc_ps; // "__builtin_ia32_ vtestnzcps"
} }
break; break;
case 'z': // 1 string to match. case 'z': // 1 string to match.
if (BuiltinName.substr(17, 8) != "eroupper") if (memcmp(BuiltinName.data()+17, "eroupper", 8))
break; break;
return Intrinsic::x86_avx_vzeroupper; // "__builtin_ia32_vzeroupp er" return Intrinsic::x86_avx_vzeroupper; // "__builtin_ia32_vzeroupp er"
} }
break; break;
case 'w': // 4 strings to match. case 'w': // 4 strings to match.
if (BuiltinName[16] != 'r') if (BuiltinName[16] != 'r')
break; break;
switch (BuiltinName[17]) { switch (BuiltinName[17]) {
default: break; default: break;
case 'f': // 2 strings to match. case 'f': // 2 strings to match.
if (BuiltinName.substr(18, 5) != "sbase") if (memcmp(BuiltinName.data()+18, "sbase", 5))
break; break;
switch (BuiltinName[23]) { switch (BuiltinName[23]) {
default: break; default: break;
case '3': // 1 string to match. case '3': // 1 string to match.
if (BuiltinName[24] != '2') if (BuiltinName[24] != '2')
break; break;
return Intrinsic::x86_wrfsbase_32; // "__builtin_ia32_wrfsbase 32" return Intrinsic::x86_wrfsbase_32; // "__builtin_ia32_wrfsbase 32"
case '6': // 1 string to match. case '6': // 1 string to match.
if (BuiltinName[24] != '4') if (BuiltinName[24] != '4')
break; break;
return Intrinsic::x86_wrfsbase_64; // "__builtin_ia32_wrfsbase 64" return Intrinsic::x86_wrfsbase_64; // "__builtin_ia32_wrfsbase 64"
} }
break; break;
case 'g': // 2 strings to match. case 'g': // 2 strings to match.
if (BuiltinName.substr(18, 5) != "sbase") if (memcmp(BuiltinName.data()+18, "sbase", 5))
break; break;
switch (BuiltinName[23]) { switch (BuiltinName[23]) {
default: break; default: break;
case '3': // 1 string to match. case '3': // 1 string to match.
if (BuiltinName[24] != '2') if (BuiltinName[24] != '2')
break; break;
return Intrinsic::x86_wrgsbase_32; // "__builtin_ia32_wrgsbase 32" return Intrinsic::x86_wrgsbase_32; // "__builtin_ia32_wrgsbase 32"
case '6': // 1 string to match. case '6': // 1 string to match.
if (BuiltinName[24] != '4') if (BuiltinName[24] != '4')
break; break;
return Intrinsic::x86_wrgsbase_64; // "__builtin_ia32_wrgsbase 64" return Intrinsic::x86_wrgsbase_64; // "__builtin_ia32_wrgsbase 64"
} }
break; break;
} }
break; break;
} }
break; break;
case 26: // 73 strings to match. case 26: // 73 strings to match.
if (BuiltinName.substr(0, 15) != "__builtin_ia32_") if (memcmp(BuiltinName.data()+0, "__builtin_ia32_", 15))
break; break;
switch (BuiltinName[15]) { switch (BuiltinName[15]) {
default: break; default: break;
case 'a': // 2 strings to match. case 'a': // 2 strings to match.
if (BuiltinName.substr(16, 6) != "ddsubp") if (memcmp(BuiltinName.data()+16, "ddsubp", 6))
break; break;
switch (BuiltinName[22]) { switch (BuiltinName[22]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
if (BuiltinName.substr(23, 3) != "256") if (memcmp(BuiltinName.data()+23, "256", 3))
break; break;
return Intrinsic::x86_avx_addsub_pd_256; // "__builtin_ia32_ addsubpd256" return Intrinsic::x86_avx_addsub_pd_256; // "__builtin_ia32_ addsubpd256"
case 's': // 1 string to match. case 's': // 1 string to match.
if (BuiltinName.substr(23, 3) != "256") if (memcmp(BuiltinName.data()+23, "256", 3))
break; break;
return Intrinsic::x86_avx_addsub_ps_256; // "__builtin_ia32_ addsubps256" return Intrinsic::x86_avx_addsub_ps_256; // "__builtin_ia32_ addsubps256"
} }
break; break;
case 'b': // 2 strings to match. case 'b': // 2 strings to match.
if (BuiltinName.substr(16, 6) != "lendvp") if (memcmp(BuiltinName.data()+16, "lendvp", 6))
break; break;
switch (BuiltinName[22]) { switch (BuiltinName[22]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
if (BuiltinName.substr(23, 3) != "256") if (memcmp(BuiltinName.data()+23, "256", 3))
break; break;
return Intrinsic::x86_avx_blendv_pd_256; // "__builtin_ia32_ blendvpd256" return Intrinsic::x86_avx_blendv_pd_256; // "__builtin_ia32_ blendvpd256"
case 's': // 1 string to match. case 's': // 1 string to match.
if (BuiltinName.substr(23, 3) != "256") if (memcmp(BuiltinName.data()+23, "256", 3))
break; break;
return Intrinsic::x86_avx_blendv_ps_256; // "__builtin_ia32_ blendvps256" return Intrinsic::x86_avx_blendv_ps_256; // "__builtin_ia32_ blendvps256"
} }
break; break;
case 'c': // 8 strings to match. case 'c': // 8 strings to match.
if (BuiltinName.substr(16, 2) != "vt") if (memcmp(BuiltinName.data()+16, "vt", 2))
break; break;
switch (BuiltinName[18]) { switch (BuiltinName[18]) {
default: break; default: break;
case 'd': // 2 strings to match. case 'd': // 2 strings to match.
if (BuiltinName.substr(19, 3) != "q2p") if (memcmp(BuiltinName.data()+19, "q2p", 3))
break; break;
switch (BuiltinName[22]) { switch (BuiltinName[22]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
if (BuiltinName.substr(23, 3) != "256") if (memcmp(BuiltinName.data()+23, "256", 3))
break; break;
return Intrinsic::x86_avx_cvtdq2_pd_256; // "__builtin_ia32_ cvtdq2pd256" return Intrinsic::x86_avx_cvtdq2_pd_256; // "__builtin_ia32_ cvtdq2pd256"
case 's': // 1 string to match. case 's': // 1 string to match.
if (BuiltinName.substr(23, 3) != "256") if (memcmp(BuiltinName.data()+23, "256", 3))
break; break;
return Intrinsic::x86_avx_cvtdq2_ps_256; // "__builtin_ia32_ cvtdq2ps256" return Intrinsic::x86_avx_cvtdq2_ps_256; // "__builtin_ia32_ cvtdq2ps256"
} }
break; break;
case 'p': // 4 strings to match. case 'p': // 4 strings to match.
switch (BuiltinName[19]) { switch (BuiltinName[19]) {
default: break; default: break;
case 'd': // 2 strings to match. case 'd': // 2 strings to match.
if (BuiltinName[20] != '2') if (BuiltinName[20] != '2')
break; break;
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
if (BuiltinName.substr(22, 4) != "q256") if (memcmp(BuiltinName.data()+22, "q256", 4))
break; break;
return Intrinsic::x86_avx_cvt_pd2dq_256; // "__builtin_ia32_ cvtpd2dq256" return Intrinsic::x86_avx_cvt_pd2dq_256; // "__builtin_ia32_ cvtpd2dq256"
case 'p': // 1 string to match. case 'p': // 1 string to match.
if (BuiltinName.substr(22, 4) != "s256") if (memcmp(BuiltinName.data()+22, "s256", 4))
break; break;
return Intrinsic::x86_avx_cvt_pd2_ps_256; // "__builtin_ia32_ cvtpd2ps256" return Intrinsic::x86_avx_cvt_pd2_ps_256; // "__builtin_ia32_ cvtpd2ps256"
} }
break; break;
case 's': // 2 strings to match. case 's': // 2 strings to match.
if (BuiltinName[20] != '2') if (BuiltinName[20] != '2')
break; break;
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
if (BuiltinName.substr(22, 4) != "q256") if (memcmp(BuiltinName.data()+22, "q256", 4))
break; break;
return Intrinsic::x86_avx_cvt_ps2dq_256; // "__builtin_ia32_ cvtps2dq256" return Intrinsic::x86_avx_cvt_ps2dq_256; // "__builtin_ia32_ cvtps2dq256"
case 'p': // 1 string to match. case 'p': // 1 string to match.
if (BuiltinName.substr(22, 4) != "d256") if (memcmp(BuiltinName.data()+22, "d256", 4))
break; break;
return Intrinsic::x86_avx_cvt_ps2_pd_256; // "__builtin_ia32_ cvtps2pd256" return Intrinsic::x86_avx_cvt_ps2_pd_256; // "__builtin_ia32_ cvtps2pd256"
} }
break; break;
} }
break; break;
case 't': // 2 strings to match. case 't': // 2 strings to match.
if (BuiltinName[19] != 's') if (BuiltinName[19] != 's')
break; break;
switch (BuiltinName[20]) { switch (BuiltinName[20]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
if (BuiltinName.substr(21, 5) != "2si64") if (memcmp(BuiltinName.data()+21, "2si64", 5))
break; break;
return Intrinsic::x86_sse2_cvttsd2si64; // "__builtin_ia32_ cvttsd2si64" return Intrinsic::x86_sse2_cvttsd2si64; // "__builtin_ia32_ cvttsd2si64"
case 's': // 1 string to match. case 's': // 1 string to match.
if (BuiltinName.substr(21, 5) != "2si64") if (memcmp(BuiltinName.data()+21, "2si64", 5))
break; break;
return Intrinsic::x86_sse_cvttss2si64; // "__builtin_ia32_ cvttss2si64" return Intrinsic::x86_sse_cvttss2si64; // "__builtin_ia32_ cvttss2si64"
} }
break; break;
} }
break; break;
case 'i': // 1 string to match. case 'i': // 1 string to match.
if (BuiltinName.substr(16, 10) != "nsertps128") if (memcmp(BuiltinName.data()+16, "nsertps128", 10))
break; break;
return Intrinsic::x86_sse41_insertps; // "__builtin_ia32_insertps 128" return Intrinsic::x86_sse41_insertps; // "__builtin_ia32_insertps 128"
case 'm': // 5 strings to match. case 'm': // 5 strings to match.
switch (BuiltinName[16]) { switch (BuiltinName[16]) {
default: break; default: break;
case 'a': // 2 strings to match. case 'a': // 2 strings to match.
if (BuiltinName.substr(17, 8) != "skstorep") if (memcmp(BuiltinName.data()+17, "skstorep", 8))
break; break;
switch (BuiltinName[25]) { switch (BuiltinName[25]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
return Intrinsic::x86_avx_maskstore_pd; // "__builtin_ia32_ maskstorepd" return Intrinsic::x86_avx_maskstore_pd; // "__builtin_ia32_ maskstorepd"
case 's': // 1 string to match. case 's': // 1 string to match.
return Intrinsic::x86_avx_maskstore_ps; // "__builtin_ia32_ maskstoreps" return Intrinsic::x86_avx_maskstore_ps; // "__builtin_ia32_ maskstoreps"
} }
break; break;
case 'o': // 3 strings to match. case 'o': // 3 strings to match.
if (BuiltinName[17] != 'v') if (BuiltinName[17] != 'v')
break; break;
switch (BuiltinName[18]) { switch (BuiltinName[18]) {
default: break; default: break;
case 'm': // 2 strings to match. case 'm': // 2 strings to match.
if (BuiltinName.substr(19, 3) != "skp") if (memcmp(BuiltinName.data()+19, "skp", 3))
break; break;
switch (BuiltinName[22]) { switch (BuiltinName[22]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
if (BuiltinName.substr(23, 3) != "256") if (memcmp(BuiltinName.data()+23, "256", 3))
break; break;
return Intrinsic::x86_avx_movmsk_pd_256; // "__builtin_ia32_ movmskpd256" return Intrinsic::x86_avx_movmsk_pd_256; // "__builtin_ia32_ movmskpd256"
case 's': // 1 string to match. case 's': // 1 string to match.
if (BuiltinName.substr(23, 3) != "256") if (memcmp(BuiltinName.data()+23, "256", 3))
break; break;
return Intrinsic::x86_avx_movmsk_ps_256; // "__builtin_ia32_ movmskps256" return Intrinsic::x86_avx_movmsk_ps_256; // "__builtin_ia32_ movmskps256"
} }
break; break;
case 'n': // 1 string to match. case 'n': // 1 string to match.
if (BuiltinName.substr(19, 7) != "tdqa256") if (memcmp(BuiltinName.data()+19, "tdqa256", 7))
break; break;
return Intrinsic::x86_avx2_movntdqa; // "__builtin_ia32_movntdqa 256" return Intrinsic::x86_avx2_movntdqa; // "__builtin_ia32_movntdqa 256"
} }
break; break;
} }
break; break;
case 'p': // 40 strings to match. case 'p': // 40 strings to match.
switch (BuiltinName[16]) { switch (BuiltinName[16]) {
default: break; default: break;
case 'a': // 8 strings to match. case 'a': // 8 strings to match.
if (BuiltinName.substr(17, 2) != "ck") if (memcmp(BuiltinName.data()+17, "ck", 2))
break; break;
switch (BuiltinName[19]) { switch (BuiltinName[19]) {
default: break; default: break;
case 's': // 4 strings to match. case 's': // 4 strings to match.
if (BuiltinName[20] != 's') if (BuiltinName[20] != 's')
break; break;
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case 'd': // 2 strings to match. case 'd': // 2 strings to match.
if (BuiltinName[22] != 'w') if (BuiltinName[22] != 'w')
break; break;
switch (BuiltinName[23]) { switch (BuiltinName[23]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(24, 2) != "28") if (memcmp(BuiltinName.data()+24, "28", 2))
break; break;
return Intrinsic::x86_sse2_packssdw_128; // "__builtin_ia32_ packssdw128" return Intrinsic::x86_sse2_packssdw_128; // "__builtin_ia32_ packssdw128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(24, 2) != "56") if (memcmp(BuiltinName.data()+24, "56", 2))
break; break;
return Intrinsic::x86_avx2_packssdw; // "__builtin_ia32_ packssdw256" return Intrinsic::x86_avx2_packssdw; // "__builtin_ia32_ packssdw256"
} }
break; break;
case 'w': // 2 strings to match. case 'w': // 2 strings to match.
if (BuiltinName[22] != 'b') if (BuiltinName[22] != 'b')
break; break;
switch (BuiltinName[23]) { switch (BuiltinName[23]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(24, 2) != "28") if (memcmp(BuiltinName.data()+24, "28", 2))
break; break;
return Intrinsic::x86_sse2_packsswb_128; // "__builtin_ia32_ packsswb128" return Intrinsic::x86_sse2_packsswb_128; // "__builtin_ia32_ packsswb128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(24, 2) != "56") if (memcmp(BuiltinName.data()+24, "56", 2))
break; break;
return Intrinsic::x86_avx2_packsswb; // "__builtin_ia32_ packsswb256" return Intrinsic::x86_avx2_packsswb; // "__builtin_ia32_ packsswb256"
} }
break; break;
} }
break; break;
case 'u': // 4 strings to match. case 'u': // 4 strings to match.
if (BuiltinName[20] != 's') if (BuiltinName[20] != 's')
break; break;
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case 'd': // 2 strings to match. case 'd': // 2 strings to match.
if (BuiltinName[22] != 'w') if (BuiltinName[22] != 'w')
break; break;
switch (BuiltinName[23]) { switch (BuiltinName[23]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(24, 2) != "28") if (memcmp(BuiltinName.data()+24, "28", 2))
break; break;
return Intrinsic::x86_sse41_packusdw; // "__builtin_ia32_ packusdw128" return Intrinsic::x86_sse41_packusdw; // "__builtin_ia32_ packusdw128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(24, 2) != "56") if (memcmp(BuiltinName.data()+24, "56", 2))
break; break;
return Intrinsic::x86_avx2_packusdw; // "__builtin_ia32_ packusdw256" return Intrinsic::x86_avx2_packusdw; // "__builtin_ia32_ packusdw256"
} }
break; break;
case 'w': // 2 strings to match. case 'w': // 2 strings to match.
if (BuiltinName[22] != 'b') if (BuiltinName[22] != 'b')
break; break;
switch (BuiltinName[23]) { switch (BuiltinName[23]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(24, 2) != "28") if (memcmp(BuiltinName.data()+24, "28", 2))
break; break;
return Intrinsic::x86_sse2_packuswb_128; // "__builtin_ia32_ packuswb128" return Intrinsic::x86_sse2_packuswb_128; // "__builtin_ia32_ packuswb128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(24, 2) != "56") if (memcmp(BuiltinName.data()+24, "56", 2))
break; break;
return Intrinsic::x86_avx2_packuswb; // "__builtin_ia32_ packuswb256" return Intrinsic::x86_avx2_packuswb; // "__builtin_ia32_ packuswb256"
} }
break; break;
} }
break; break;
} }
break; break;
case 'b': // 2 strings to match. case 'b': // 2 strings to match.
if (BuiltinName.substr(17, 6) != "lendvb") if (memcmp(BuiltinName.data()+17, "lendvb", 6))
break; break;
switch (BuiltinName[23]) { switch (BuiltinName[23]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(24, 2) != "28") if (memcmp(BuiltinName.data()+24, "28", 2))
break; break;
return Intrinsic::x86_sse41_pblendvb; // "__builtin_ia32_ pblendvb128" return Intrinsic::x86_sse41_pblendvb; // "__builtin_ia32_ pblendvb128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(24, 2) != "56") if (memcmp(BuiltinName.data()+24, "56", 2))
break; break;
return Intrinsic::x86_avx2_pblendvb; // "__builtin_ia32_pblendvb 256" return Intrinsic::x86_avx2_pblendvb; // "__builtin_ia32_pblendvb 256"
} }
break; break;
case 'm': // 28 strings to match. case 'm': // 28 strings to match.
switch (BuiltinName[17]) { switch (BuiltinName[17]) {
default: break; default: break;
case 'o': // 26 strings to match. case 'o': // 26 strings to match.
if (BuiltinName[18] != 'v') if (BuiltinName[18] != 'v')
break; break;
switch (BuiltinName[19]) { switch (BuiltinName[19]) {
default: break; default: break;
case 'm': // 2 strings to match. case 'm': // 2 strings to match.
if (BuiltinName.substr(20, 3) != "skb") if (memcmp(BuiltinName.data()+20, "skb", 3))
break; break;
switch (BuiltinName[23]) { switch (BuiltinName[23]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(24, 2) != "28") if (memcmp(BuiltinName.data()+24, "28", 2))
break; break;
return Intrinsic::x86_sse2_pmovmskb_128; // "__builtin_ia32_ pmovmskb128" return Intrinsic::x86_sse2_pmovmskb_128; // "__builtin_ia32_ pmovmskb128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(24, 2) != "56") if (memcmp(BuiltinName.data()+24, "56", 2))
break; break;
return Intrinsic::x86_avx2_pmovmskb; // "__builtin_ia32_ pmovmskb256" return Intrinsic::x86_avx2_pmovmskb; // "__builtin_ia32_ pmovmskb256"
} }
break; break;
case 's': // 12 strings to match. case 's': // 12 strings to match.
if (BuiltinName[20] != 'x') if (BuiltinName[20] != 'x')
break; break;
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case 'b': // 6 strings to match. case 'b': // 6 strings to match.
switch (BuiltinName[22]) { switch (BuiltinName[22]) {
default: break; default: break;
case 'd': // 2 strings to match. case 'd': // 2 strings to match.
switch (BuiltinName[23]) { switch (BuiltinName[23]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(24, 2) != "28") if (memcmp(BuiltinName.data()+24, "28", 2))
break; break;
return Intrinsic::x86_sse41_pmovsxbd; // "__built in_ia32_pmovsxbd128" return Intrinsic::x86_sse41_pmovsxbd; // "__built in_ia32_pmovsxbd128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(24, 2) != "56") if (memcmp(BuiltinName.data()+24, "56", 2))
break; break;
return Intrinsic::x86_avx2_pmovsxbd; // "__builtin_ia32_ pmovsxbd256" return Intrinsic::x86_avx2_pmovsxbd; // "__builtin_ia32_ pmovsxbd256"
} }
break; break;
case 'q': // 2 strings to match. case 'q': // 2 strings to match.
switch (BuiltinName[23]) { switch (BuiltinName[23]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(24, 2) != "28") if (memcmp(BuiltinName.data()+24, "28", 2))
break; break;
return Intrinsic::x86_sse41_pmovsxbq; // "__built in_ia32_pmovsxbq128" return Intrinsic::x86_sse41_pmovsxbq; // "__built in_ia32_pmovsxbq128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(24, 2) != "56") if (memcmp(BuiltinName.data()+24, "56", 2))
break; break;
return Intrinsic::x86_avx2_pmovsxbq; // "__builtin_ia32_ pmovsxbq256" return Intrinsic::x86_avx2_pmovsxbq; // "__builtin_ia32_ pmovsxbq256"
} }
break; break;
case 'w': // 2 strings to match. case 'w': // 2 strings to match.
switch (BuiltinName[23]) { switch (BuiltinName[23]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(24, 2) != "28") if (memcmp(BuiltinName.data()+24, "28", 2))
break; break;
return Intrinsic::x86_sse41_pmovsxbw; // "__built in_ia32_pmovsxbw128" return Intrinsic::x86_sse41_pmovsxbw; // "__built in_ia32_pmovsxbw128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(24, 2) != "56") if (memcmp(BuiltinName.data()+24, "56", 2))
break; break;
return Intrinsic::x86_avx2_pmovsxbw; // "__builtin_ia32_ pmovsxbw256" return Intrinsic::x86_avx2_pmovsxbw; // "__builtin_ia32_ pmovsxbw256"
} }
break; break;
} }
break; break;
case 'd': // 2 strings to match. case 'd': // 2 strings to match.
if (BuiltinName[22] != 'q') if (BuiltinName[22] != 'q')
break; break;
switch (BuiltinName[23]) { switch (BuiltinName[23]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(24, 2) != "28") if (memcmp(BuiltinName.data()+24, "28", 2))
break; break;
return Intrinsic::x86_sse41_pmovsxdq; // "__builtin_ia32_ pmovsxdq128" return Intrinsic::x86_sse41_pmovsxdq; // "__builtin_ia32_ pmovsxdq128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(24, 2) != "56") if (memcmp(BuiltinName.data()+24, "56", 2))
break; break;
return Intrinsic::x86_avx2_pmovsxdq; // "__builtin_ia32_ pmovsxdq256" return Intrinsic::x86_avx2_pmovsxdq; // "__builtin_ia32_ pmovsxdq256"
} }
break; break;
case 'w': // 4 strings to match. case 'w': // 4 strings to match.
switch (BuiltinName[22]) { switch (BuiltinName[22]) {
default: break; default: break;
case 'd': // 2 strings to match. case 'd': // 2 strings to match.
switch (BuiltinName[23]) { switch (BuiltinName[23]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(24, 2) != "28") if (memcmp(BuiltinName.data()+24, "28", 2))
break; break;
return Intrinsic::x86_sse41_pmovsxwd; // "__built in_ia32_pmovsxwd128" return Intrinsic::x86_sse41_pmovsxwd; // "__built in_ia32_pmovsxwd128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(24, 2) != "56") if (memcmp(BuiltinName.data()+24, "56", 2))
break; break;
return Intrinsic::x86_avx2_pmovsxwd; // "__builtin_ia32_ pmovsxwd256" return Intrinsic::x86_avx2_pmovsxwd; // "__builtin_ia32_ pmovsxwd256"
} }
break; break;
case 'q': // 2 strings to match. case 'q': // 2 strings to match.
switch (BuiltinName[23]) { switch (BuiltinName[23]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(24, 2) != "28") if (memcmp(BuiltinName.data()+24, "28", 2))
break; break;
return Intrinsic::x86_sse41_pmovsxwq; // "__built in_ia32_pmovsxwq128" return Intrinsic::x86_sse41_pmovsxwq; // "__built in_ia32_pmovsxwq128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(24, 2) != "56") if (memcmp(BuiltinName.data()+24, "56", 2))
break; break;
return Intrinsic::x86_avx2_pmovsxwq; // "__builtin_ia32_ pmovsxwq256" return Intrinsic::x86_avx2_pmovsxwq; // "__builtin_ia32_ pmovsxwq256"
} }
break; break;
} }
break; break;
} }
break; break;
case 'z': // 12 strings to match. case 'z': // 12 strings to match.
if (BuiltinName[20] != 'x') if (BuiltinName[20] != 'x')
break; break;
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case 'b': // 6 strings to match. case 'b': // 6 strings to match.
switch (BuiltinName[22]) { switch (BuiltinName[22]) {
default: break; default: break;
case 'd': // 2 strings to match. case 'd': // 2 strings to match.
switch (BuiltinName[23]) { switch (BuiltinName[23]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(24, 2) != "28") if (memcmp(BuiltinName.data()+24, "28", 2))
break; break;
return Intrinsic::x86_sse41_pmovzxbd; // "__built in_ia32_pmovzxbd128" return Intrinsic::x86_sse41_pmovzxbd; // "__built in_ia32_pmovzxbd128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(24, 2) != "56") if (memcmp(BuiltinName.data()+24, "56", 2))
break; break;
return Intrinsic::x86_avx2_pmovzxbd; // "__builtin_ia32_ pmovzxbd256" return Intrinsic::x86_avx2_pmovzxbd; // "__builtin_ia32_ pmovzxbd256"
} }
break; break;
case 'q': // 2 strings to match. case 'q': // 2 strings to match.
switch (BuiltinName[23]) { switch (BuiltinName[23]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(24, 2) != "28") if (memcmp(BuiltinName.data()+24, "28", 2))
break; break;
return Intrinsic::x86_sse41_pmovzxbq; // "__built in_ia32_pmovzxbq128" return Intrinsic::x86_sse41_pmovzxbq; // "__built in_ia32_pmovzxbq128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(24, 2) != "56") if (memcmp(BuiltinName.data()+24, "56", 2))
break; break;
return Intrinsic::x86_avx2_pmovzxbq; // "__builtin_ia32_ pmovzxbq256" return Intrinsic::x86_avx2_pmovzxbq; // "__builtin_ia32_ pmovzxbq256"
} }
break; break;
case 'w': // 2 strings to match. case 'w': // 2 strings to match.
switch (BuiltinName[23]) { switch (BuiltinName[23]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(24, 2) != "28") if (memcmp(BuiltinName.data()+24, "28", 2))
break; break;
return Intrinsic::x86_sse41_pmovzxbw; // "__built in_ia32_pmovzxbw128" return Intrinsic::x86_sse41_pmovzxbw; // "__built in_ia32_pmovzxbw128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(24, 2) != "56") if (memcmp(BuiltinName.data()+24, "56", 2))
break; break;
return Intrinsic::x86_avx2_pmovzxbw; // "__builtin_ia32_ pmovzxbw256" return Intrinsic::x86_avx2_pmovzxbw; // "__builtin_ia32_ pmovzxbw256"
} }
break; break;
} }
break; break;
case 'd': // 2 strings to match. case 'd': // 2 strings to match.
if (BuiltinName[22] != 'q') if (BuiltinName[22] != 'q')
break; break;
switch (BuiltinName[23]) { switch (BuiltinName[23]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(24, 2) != "28") if (memcmp(BuiltinName.data()+24, "28", 2))
break; break;
return Intrinsic::x86_sse41_pmovzxdq; // "__builtin_ia32_ pmovzxdq128" return Intrinsic::x86_sse41_pmovzxdq; // "__builtin_ia32_ pmovzxdq128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(24, 2) != "56") if (memcmp(BuiltinName.data()+24, "56", 2))
break; break;
return Intrinsic::x86_avx2_pmovzxdq; // "__builtin_ia32_ pmovzxdq256" return Intrinsic::x86_avx2_pmovzxdq; // "__builtin_ia32_ pmovzxdq256"
} }
break; break;
case 'w': // 4 strings to match. case 'w': // 4 strings to match.
switch (BuiltinName[22]) { switch (BuiltinName[22]) {
default: break; default: break;
case 'd': // 2 strings to match. case 'd': // 2 strings to match.
switch (BuiltinName[23]) { switch (BuiltinName[23]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(24, 2) != "28") if (memcmp(BuiltinName.data()+24, "28", 2))
break; break;
return Intrinsic::x86_sse41_pmovzxwd; // "__built in_ia32_pmovzxwd128" return Intrinsic::x86_sse41_pmovzxwd; // "__built in_ia32_pmovzxwd128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(24, 2) != "56") if (memcmp(BuiltinName.data()+24, "56", 2))
break; break;
return Intrinsic::x86_avx2_pmovzxwd; // "__builtin_ia32_ pmovzxwd256" return Intrinsic::x86_avx2_pmovzxwd; // "__builtin_ia32_ pmovzxwd256"
} }
break; break;
case 'q': // 2 strings to match. case 'q': // 2 strings to match.
switch (BuiltinName[23]) { switch (BuiltinName[23]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(24, 2) != "28") if (memcmp(BuiltinName.data()+24, "28", 2))
break; break;
return Intrinsic::x86_sse41_pmovzxwq; // "__built in_ia32_pmovzxwq128" return Intrinsic::x86_sse41_pmovzxwq; // "__built in_ia32_pmovzxwq128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(24, 2) != "56") if (memcmp(BuiltinName.data()+24, "56", 2))
break; break;
return Intrinsic::x86_avx2_pmovzxwq; // "__builtin_ia32_ pmovzxwq256" return Intrinsic::x86_avx2_pmovzxwq; // "__builtin_ia32_ pmovzxwq256"
} }
break; break;
} }
break; break;
} }
break; break;
} }
break; break;
case 'u': // 2 strings to match. case 'u': // 2 strings to match.
if (BuiltinName.substr(18, 5) != "lhrsw") if (memcmp(BuiltinName.data()+18, "lhrsw", 5))
break; break;
switch (BuiltinName[23]) { switch (BuiltinName[23]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(24, 2) != "28") if (memcmp(BuiltinName.data()+24, "28", 2))
break; break;
return Intrinsic::x86_ssse3_pmul_hr_sw_128; // "__built in_ia32_pmulhrsw128" return Intrinsic::x86_ssse3_pmul_hr_sw_128; // "__built in_ia32_pmulhrsw128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(24, 2) != "56") if (memcmp(BuiltinName.data()+24, "56", 2))
break; break;
return Intrinsic::x86_avx2_pmul_hr_sw; // "__builtin_ia32_ pmulhrsw256" return Intrinsic::x86_avx2_pmul_hr_sw; // "__builtin_ia32_ pmulhrsw256"
} }
break; break;
} }
break; break;
case 't': // 2 strings to match. case 't': // 2 strings to match.
if (BuiltinName.substr(17, 6) != "estnzc") if (memcmp(BuiltinName.data()+17, "estnzc", 6))
break; break;
switch (BuiltinName[23]) { switch (BuiltinName[23]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(24, 2) != "28") if (memcmp(BuiltinName.data()+24, "28", 2))
break; break;
return Intrinsic::x86_sse41_ptestnzc; // "__builtin_ia32_ ptestnzc128" return Intrinsic::x86_sse41_ptestnzc; // "__builtin_ia32_ ptestnzc128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(24, 2) != "56") if (memcmp(BuiltinName.data()+24, "56", 2))
break; break;
return Intrinsic::x86_avx_ptestnzc_256; // "__builtin_ia32_ ptestnzc256" return Intrinsic::x86_avx_ptestnzc_256; // "__builtin_ia32_ ptestnzc256"
} }
break; break;
} }
break; break;
case 's': // 3 strings to match. case 's': // 3 strings to match.
if (BuiltinName.substr(16, 4) != "tore") if (memcmp(BuiltinName.data()+16, "tore", 4))
break; break;
switch (BuiltinName[20]) { switch (BuiltinName[20]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
if (BuiltinName.substr(21, 5) != "qu256") if (memcmp(BuiltinName.data()+21, "qu256", 5))
break; break;
return Intrinsic::x86_avx_storeu_dq_256; // "__builtin_ia32_ storedqu256" return Intrinsic::x86_avx_storeu_dq_256; // "__builtin_ia32_ storedqu256"
case 'u': // 2 strings to match. case 'u': // 2 strings to match.
if (BuiltinName[21] != 'p') if (BuiltinName[21] != 'p')
break; break;
switch (BuiltinName[22]) { switch (BuiltinName[22]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
if (BuiltinName.substr(23, 3) != "256") if (memcmp(BuiltinName.data()+23, "256", 3))
break; break;
return Intrinsic::x86_avx_storeu_pd_256; // "__builtin_ia32_ storeupd256" return Intrinsic::x86_avx_storeu_pd_256; // "__builtin_ia32_ storeupd256"
case 's': // 1 string to match. case 's': // 1 string to match.
if (BuiltinName.substr(23, 3) != "256") if (memcmp(BuiltinName.data()+23, "256", 3))
break; break;
return Intrinsic::x86_avx_storeu_ps_256; // "__builtin_ia32_ storeups256" return Intrinsic::x86_avx_storeu_ps_256; // "__builtin_ia32_ storeups256"
} }
break; break;
} }
break; break;
case 'v': // 12 strings to match. case 'v': // 12 strings to match.
switch (BuiltinName[16]) { switch (BuiltinName[16]) {
default: break; default: break;
case 'f': // 8 strings to match. case 'f': // 8 strings to match.
if (BuiltinName[17] != 'm') if (BuiltinName[17] != 'm')
break; break;
switch (BuiltinName[18]) { switch (BuiltinName[18]) {
default: break; default: break;
case 'a': // 4 strings to match. case 'a': // 4 strings to match.
if (BuiltinName.substr(19, 2) != "dd") if (memcmp(BuiltinName.data()+19, "dd", 2))
break; break;
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case 'p': // 2 strings to match. case 'p': // 2 strings to match.
switch (BuiltinName[22]) { switch (BuiltinName[22]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
if (BuiltinName.substr(23, 3) != "256") if (memcmp(BuiltinName.data()+23, "256", 3))
break; break;
return Intrinsic::x86_fma4_vfmadd_pd_256; // "__built in_ia32_vfmaddpd256" return Intrinsic::x86_fma_vfmadd_pd_256; // "__builtin_ia32_ vfmaddpd256"
case 's': // 1 string to match. case 's': // 1 string to match.
if (BuiltinName.substr(23, 3) != "256") if (memcmp(BuiltinName.data()+23, "256", 3))
break; break;
return Intrinsic::x86_fma4_vfmadd_ps_256; // "__built in_ia32_vfmaddps256" return Intrinsic::x86_fma_vfmadd_ps_256; // "__builtin_ia32_ vfmaddps256"
} }
break; break;
case 's': // 2 strings to match. case 's': // 2 strings to match.
if (BuiltinName.substr(22, 3) != "ubp") if (memcmp(BuiltinName.data()+22, "ubp", 3))
break; break;
switch (BuiltinName[25]) { switch (BuiltinName[25]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
return Intrinsic::x86_fma4_vfmaddsub_pd; // "__builtin_ia32_ vfmaddsubpd" return Intrinsic::x86_fma_vfmaddsub_pd; // "__builtin_ia32_ vfmaddsubpd"
case 's': // 1 string to match. case 's': // 1 string to match.
return Intrinsic::x86_fma4_vfmaddsub_ps; // "__builtin_ia32_ vfmaddsubps" return Intrinsic::x86_fma_vfmaddsub_ps; // "__builtin_ia32_ vfmaddsubps"
} }
break; break;
} }
break; break;
case 's': // 4 strings to match. case 's': // 4 strings to match.
if (BuiltinName.substr(19, 2) != "ub") if (memcmp(BuiltinName.data()+19, "ub", 2))
break; break;
switch (BuiltinName[21]) { switch (BuiltinName[21]) {
default: break; default: break;
case 'a': // 2 strings to match. case 'a': // 2 strings to match.
if (BuiltinName.substr(22, 3) != "ddp") if (memcmp(BuiltinName.data()+22, "ddp", 3))
break; break;
switch (BuiltinName[25]) { switch (BuiltinName[25]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
return Intrinsic::x86_fma4_vfmsubadd_pd; // "__builtin_ia32_ vfmsubaddpd" return Intrinsic::x86_fma_vfmsubadd_pd; // "__builtin_ia32_ vfmsubaddpd"
case 's': // 1 string to match. case 's': // 1 string to match.
return Intrinsic::x86_fma4_vfmsubadd_ps; // "__builtin_ia32_ vfmsubaddps" return Intrinsic::x86_fma_vfmsubadd_ps; // "__builtin_ia32_ vfmsubaddps"
} }
break; break;
case 'p': // 2 strings to match. case 'p': // 2 strings to match.
switch (BuiltinName[22]) { switch (BuiltinName[22]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
if (BuiltinName.substr(23, 3) != "256") if (memcmp(BuiltinName.data()+23, "256", 3))
break; break;
return Intrinsic::x86_fma4_vfmsub_pd_256; // "__built in_ia32_vfmsubpd256" return Intrinsic::x86_fma_vfmsub_pd_256; // "__builtin_ia32_ vfmsubpd256"
case 's': // 1 string to match. case 's': // 1 string to match.
if (BuiltinName.substr(23, 3) != "256") if (memcmp(BuiltinName.data()+23, "256", 3))
break; break;
return Intrinsic::x86_fma4_vfmsub_ps_256; // "__built in_ia32_vfmsubps256" return Intrinsic::x86_fma_vfmsub_ps_256; // "__builtin_ia32_ vfmsubps256"
} }
break; break;
} }
break; break;
} }
break; break;
case 't': // 4 strings to match. case 't': // 4 strings to match.
if (BuiltinName.substr(17, 3) != "est") if (memcmp(BuiltinName.data()+17, "est", 3))
break; break;
switch (BuiltinName[20]) { switch (BuiltinName[20]) {
default: break; default: break;
case 'c': // 2 strings to match. case 'c': // 2 strings to match.
if (BuiltinName[21] != 'p') if (BuiltinName[21] != 'p')
break; break;
switch (BuiltinName[22]) { switch (BuiltinName[22]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
if (BuiltinName.substr(23, 3) != "256") if (memcmp(BuiltinName.data()+23, "256", 3))
break; break;
return Intrinsic::x86_avx_vtestc_pd_256; // "__builtin_ia32_ vtestcpd256" return Intrinsic::x86_avx_vtestc_pd_256; // "__builtin_ia32_ vtestcpd256"
case 's': // 1 string to match. case 's': // 1 string to match.
if (BuiltinName.substr(23, 3) != "256") if (memcmp(BuiltinName.data()+23, "256", 3))
break; break;
return Intrinsic::x86_avx_vtestc_ps_256; // "__builtin_ia32_ vtestcps256" return Intrinsic::x86_avx_vtestc_ps_256; // "__builtin_ia32_ vtestcps256"
} }
break; break;
case 'z': // 2 strings to match. case 'z': // 2 strings to match.
if (BuiltinName[21] != 'p') if (BuiltinName[21] != 'p')
break; break;
switch (BuiltinName[22]) { switch (BuiltinName[22]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
if (BuiltinName.substr(23, 3) != "256") if (memcmp(BuiltinName.data()+23, "256", 3))
break; break;
return Intrinsic::x86_avx_vtestz_pd_256; // "__builtin_ia32_ vtestzpd256" return Intrinsic::x86_avx_vtestz_pd_256; // "__builtin_ia32_ vtestzpd256"
case 's': // 1 string to match. case 's': // 1 string to match.
if (BuiltinName.substr(23, 3) != "256") if (memcmp(BuiltinName.data()+23, "256", 3))
break; break;
return Intrinsic::x86_avx_vtestz_ps_256; // "__builtin_ia32_ vtestzps256" return Intrinsic::x86_avx_vtestz_ps_256; // "__builtin_ia32_ vtestzps256"
} }
break; break;
} }
break; break;
} }
break; break;
} }
break; break;
case 27: // 24 strings to match. case 27: // 29 strings to match.
if (BuiltinName.substr(0, 15) != "__builtin_ia32_") if (memcmp(BuiltinName.data()+0, "__builtin_ia32_", 15))
break; break;
switch (BuiltinName[15]) { switch (BuiltinName[15]) {
default: break; default: break;
case 'c': // 2 strings to match. case 'c': // 2 strings to match.
if (BuiltinName.substr(16, 4) != "vttp") if (memcmp(BuiltinName.data()+16, "vttp", 4))
break; break;
switch (BuiltinName[20]) { switch (BuiltinName[20]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
if (BuiltinName.substr(21, 6) != "2dq256") if (memcmp(BuiltinName.data()+21, "2dq256", 6))
break; break;
return Intrinsic::x86_avx_cvtt_pd2dq_256; // "__builtin_ia32_ cvttpd2dq256" return Intrinsic::x86_avx_cvtt_pd2dq_256; // "__builtin_ia32_ cvttpd2dq256"
case 's': // 1 string to match. case 's': // 1 string to match.
if (BuiltinName.substr(21, 6) != "2dq256") if (memcmp(BuiltinName.data()+21, "2dq256", 6))
break; break;
return Intrinsic::x86_avx_cvtt_ps2dq_256; // "__builtin_ia32_ cvttps2dq256" return Intrinsic::x86_avx_cvtt_ps2dq_256; // "__builtin_ia32_ cvttps2dq256"
} }
break; break;
case 'e': // 1 string to match. case 'e': // 1 string to match.
if (BuiltinName.substr(16, 11) != "xtractps128") if (memcmp(BuiltinName.data()+16, "xtractps128", 11))
break; break;
return Intrinsic::x86_sse41_extractps; // "__builtin_ia32_extractp s128" return Intrinsic::x86_sse41_extractps; // "__builtin_ia32_extractp s128"
case 'g': // 4 strings to match.
if (memcmp(BuiltinName.data()+16, "ather", 5))
break;
switch (BuiltinName[21]) {
default: break;
case 'd': // 2 strings to match.
if (BuiltinName[22] != '_')
break;
switch (BuiltinName[23]) {
default: break;
case 'd': // 1 string to match.
if (memcmp(BuiltinName.data()+24, "256", 3))
break;
return Intrinsic::x86_avx2_gather_d_d_256; // "__builtin_ia32_
gatherd_d256"
case 'q': // 1 string to match.
if (memcmp(BuiltinName.data()+24, "256", 3))
break;
return Intrinsic::x86_avx2_gather_d_q_256; // "__builtin_ia32_
gatherd_q256"
}
break;
case 'q': // 2 strings to match.
if (BuiltinName[22] != '_')
break;
switch (BuiltinName[23]) {
default: break;
case 'd': // 1 string to match.
if (memcmp(BuiltinName.data()+24, "256", 3))
break;
return Intrinsic::x86_avx2_gather_q_d_256; // "__builtin_ia32_
gatherq_d256"
case 'q': // 1 string to match.
if (memcmp(BuiltinName.data()+24, "256", 3))
break;
return Intrinsic::x86_avx2_gather_q_q_256; // "__builtin_ia32_
gatherq_q256"
}
break;
}
break;
case 'm': // 2 strings to match. case 'm': // 2 strings to match.
if (BuiltinName.substr(16, 7) != "askload") if (memcmp(BuiltinName.data()+16, "askload", 7))
break; break;
switch (BuiltinName[23]) { switch (BuiltinName[23]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
if (BuiltinName.substr(24, 3) != "256") if (memcmp(BuiltinName.data()+24, "256", 3))
break; break;
return Intrinsic::x86_avx2_maskload_d_256; // "__builtin_ia32_ maskloadd256" return Intrinsic::x86_avx2_maskload_d_256; // "__builtin_ia32_ maskloadd256"
case 'q': // 1 string to match. case 'q': // 1 string to match.
if (BuiltinName.substr(24, 3) != "256") if (memcmp(BuiltinName.data()+24, "256", 3))
break; break;
return Intrinsic::x86_avx2_maskload_q_256; // "__builtin_ia32_ maskloadq256" return Intrinsic::x86_avx2_maskload_q_256; // "__builtin_ia32_ maskloadq256"
} }
break; break;
case 'p': // 8 strings to match. case 'p': // 9 strings to match.
switch (BuiltinName[16]) { switch (BuiltinName[16]) {
default: break; default: break;
case 'c': // 4 strings to match. case 'c': // 5 strings to match.
if (BuiltinName.substr(17, 2) != "mp") switch (BuiltinName[17]) {
break;
switch (BuiltinName[19]) {
default: break; default: break;
case 'e': // 2 strings to match. case 'l': // 1 string to match.
if (BuiltinName.substr(20, 3) != "str") if (memcmp(BuiltinName.data()+18, "mulqdq128", 9))
break; break;
switch (BuiltinName[23]) { return Intrinsic::x86_pclmulqdq; // "__builtin_ia32_pclmulqd
default: break; q128"
case 'i': // 1 string to match. case 'm': // 4 strings to match.
if (BuiltinName.substr(24, 3) != "128") if (BuiltinName[18] != 'p')
break;
return Intrinsic::x86_sse42_pcmpestri128; // "__builtin_ia32_
pcmpestri128"
case 'm': // 1 string to match.
if (BuiltinName.substr(24, 3) != "128")
break;
return Intrinsic::x86_sse42_pcmpestrm128; // "__builtin_ia32_
pcmpestrm128"
}
break;
case 'i': // 2 strings to match.
if (BuiltinName.substr(20, 3) != "str")
break; break;
switch (BuiltinName[23]) { switch (BuiltinName[19]) {
default: break; default: break;
case 'i': // 1 string to match. case 'e': // 2 strings to match.
if (BuiltinName.substr(24, 3) != "128") if (memcmp(BuiltinName.data()+20, "str", 3))
break; break;
return Intrinsic::x86_sse42_pcmpistri128; // "__builtin_ia32_ switch (BuiltinName[23]) {
pcmpistri128" default: break;
case 'm': // 1 string to match. case 'i': // 1 string to match.
if (BuiltinName.substr(24, 3) != "128") if (memcmp(BuiltinName.data()+24, "128", 3))
break;
return Intrinsic::x86_sse42_pcmpestri128; // "__built
in_ia32_pcmpestri128"
case 'm': // 1 string to match.
if (memcmp(BuiltinName.data()+24, "128", 3))
break;
return Intrinsic::x86_sse42_pcmpestrm128; // "__built
in_ia32_pcmpestrm128"
}
break;
case 'i': // 2 strings to match.
if (memcmp(BuiltinName.data()+20, "str", 3))
break; break;
return Intrinsic::x86_sse42_pcmpistrm128; // "__builtin_ia32_ switch (BuiltinName[23]) {
pcmpistrm128" default: break;
case 'i': // 1 string to match.
if (memcmp(BuiltinName.data()+24, "128", 3))
break;
return Intrinsic::x86_sse42_pcmpistri128; // "__built
in_ia32_pcmpistri128"
case 'm': // 1 string to match.
if (memcmp(BuiltinName.data()+24, "128", 3))
break;
return Intrinsic::x86_sse42_pcmpistrm128; // "__built
in_ia32_pcmpistrm128"
}
break;
} }
break; break;
} }
break; break;
case 'e': // 2 strings to match. case 'e': // 2 strings to match.
if (BuiltinName.substr(17, 6) != "rmvars") if (memcmp(BuiltinName.data()+17, "rmvars", 6))
break; break;
switch (BuiltinName[23]) { switch (BuiltinName[23]) {
default: break; default: break;
case 'f': // 1 string to match. case 'f': // 1 string to match.
if (BuiltinName.substr(24, 3) != "256") if (memcmp(BuiltinName.data()+24, "256", 3))
break; break;
return Intrinsic::x86_avx2_permps; // "__builtin_ia32_permvars f256" return Intrinsic::x86_avx2_permps; // "__builtin_ia32_permvars f256"
case 'i': // 1 string to match. case 'i': // 1 string to match.
if (BuiltinName.substr(24, 3) != "256") if (memcmp(BuiltinName.data()+24, "256", 3))
break; break;
return Intrinsic::x86_avx2_permd; // "__builtin_ia32_permvars i256" return Intrinsic::x86_avx2_permd; // "__builtin_ia32_permvars i256"
} }
break; break;
case 'm': // 2 strings to match. case 'm': // 2 strings to match.
if (BuiltinName.substr(17, 7) != "addubsw") if (memcmp(BuiltinName.data()+17, "addubsw", 7))
break; break;
switch (BuiltinName[24]) { switch (BuiltinName[24]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(25, 2) != "28") if (memcmp(BuiltinName.data()+25, "28", 2))
break; break;
return Intrinsic::x86_ssse3_pmadd_ub_sw_128; // "__builtin_ia32_ pmaddubsw128" return Intrinsic::x86_ssse3_pmadd_ub_sw_128; // "__builtin_ia32_ pmaddubsw128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(25, 2) != "56") if (memcmp(BuiltinName.data()+25, "56", 2))
break; break;
return Intrinsic::x86_avx2_pmadd_ub_sw; // "__builtin_ia32_ pmaddubsw256" return Intrinsic::x86_avx2_pmadd_ub_sw; // "__builtin_ia32_ pmaddubsw256"
} }
break; break;
} }
break; break;
case 'v': // 11 strings to match. case 'v': // 11 strings to match.
switch (BuiltinName[16]) { switch (BuiltinName[16]) {
default: break; default: break;
case 'b': // 1 string to match. case 'b': // 1 string to match.
if (BuiltinName.substr(17, 10) != "roadcastss") if (memcmp(BuiltinName.data()+17, "roadcastss", 10))
break; break;
return Intrinsic::x86_avx_vbroadcast_ss; // "__builtin_ia32_ vbroadcastss" return Intrinsic::x86_avx_vbroadcast_ss; // "__builtin_ia32_ vbroadcastss"
case 'c': // 2 strings to match. case 'c': // 2 strings to match.
if (BuiltinName.substr(17, 3) != "vtp") if (memcmp(BuiltinName.data()+17, "vtp", 3))
break; break;
switch (BuiltinName[20]) { switch (BuiltinName[20]) {
default: break; default: break;
case 'h': // 1 string to match. case 'h': // 1 string to match.
if (BuiltinName.substr(21, 6) != "2ps256") if (memcmp(BuiltinName.data()+21, "2ps256", 6))
break; break;
return Intrinsic::x86_vcvtph2ps_256; // "__builtin_ia32_vcvtph2p s256" return Intrinsic::x86_vcvtph2ps_256; // "__builtin_ia32_vcvtph2p s256"
case 's': // 1 string to match. case 's': // 1 string to match.
if (BuiltinName.substr(21, 6) != "2ph256") if (memcmp(BuiltinName.data()+21, "2ph256", 6))
break; break;
return Intrinsic::x86_vcvtps2ph_256; // "__builtin_ia32_vcvtps2p h256" return Intrinsic::x86_vcvtps2ph_256; // "__builtin_ia32_vcvtps2p h256"
} }
break; break;
case 'e': // 2 strings to match. case 'e': // 2 strings to match.
if (BuiltinName.substr(17, 2) != "c_") if (memcmp(BuiltinName.data()+17, "c_", 2))
break; break;
switch (BuiltinName[19]) { switch (BuiltinName[19]) {
default: break; default: break;
case 'e': // 1 string to match. case 'e': // 1 string to match.
if (BuiltinName.substr(20, 7) != "xt_v4hi") if (memcmp(BuiltinName.data()+20, "xt_v4hi", 7))
break; break;
return Intrinsic::x86_mmx_pextr_w; // "__builtin_ia32_vec_ext_ v4hi" return Intrinsic::x86_mmx_pextr_w; // "__builtin_ia32_vec_ext_ v4hi"
case 's': // 1 string to match. case 's': // 1 string to match.
if (BuiltinName.substr(20, 7) != "et_v4hi") if (memcmp(BuiltinName.data()+20, "et_v4hi", 7))
break; break;
return Intrinsic::x86_mmx_pinsr_w; // "__builtin_ia32_vec_set_ v4hi" return Intrinsic::x86_mmx_pinsr_w; // "__builtin_ia32_vec_set_ v4hi"
} }
break; break;
case 'f': // 4 strings to match. case 'f': // 4 strings to match.
if (BuiltinName.substr(17, 2) != "nm") if (memcmp(BuiltinName.data()+17, "nm", 2))
break; break;
switch (BuiltinName[19]) { switch (BuiltinName[19]) {
default: break; default: break;
case 'a': // 2 strings to match. case 'a': // 2 strings to match.
if (BuiltinName.substr(20, 3) != "ddp") if (memcmp(BuiltinName.data()+20, "ddp", 3))
break; break;
switch (BuiltinName[23]) { switch (BuiltinName[23]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
if (BuiltinName.substr(24, 3) != "256") if (memcmp(BuiltinName.data()+24, "256", 3))
break; break;
return Intrinsic::x86_fma4_vfnmadd_pd_256; // "__builtin_ia32_ vfnmaddpd256" return Intrinsic::x86_fma_vfnmadd_pd_256; // "__builtin_ia32_ vfnmaddpd256"
case 's': // 1 string to match. case 's': // 1 string to match.
if (BuiltinName.substr(24, 3) != "256") if (memcmp(BuiltinName.data()+24, "256", 3))
break; break;
return Intrinsic::x86_fma4_vfnmadd_ps_256; // "__builtin_ia32_ vfnmaddps256" return Intrinsic::x86_fma_vfnmadd_ps_256; // "__builtin_ia32_ vfnmaddps256"
} }
break; break;
case 's': // 2 strings to match. case 's': // 2 strings to match.
if (BuiltinName.substr(20, 3) != "ubp") if (memcmp(BuiltinName.data()+20, "ubp", 3))
break; break;
switch (BuiltinName[23]) { switch (BuiltinName[23]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
if (BuiltinName.substr(24, 3) != "256") if (memcmp(BuiltinName.data()+24, "256", 3))
break; break;
return Intrinsic::x86_fma4_vfnmsub_pd_256; // "__builtin_ia32_ vfnmsubpd256" return Intrinsic::x86_fma_vfnmsub_pd_256; // "__builtin_ia32_ vfnmsubpd256"
case 's': // 1 string to match. case 's': // 1 string to match.
if (BuiltinName.substr(24, 3) != "256") if (memcmp(BuiltinName.data()+24, "256", 3))
break; break;
return Intrinsic::x86_fma4_vfnmsub_ps_256; // "__builtin_ia32_ vfnmsubps256" return Intrinsic::x86_fma_vfnmsub_ps_256; // "__builtin_ia32_ vfnmsubps256"
} }
break; break;
} }
break; break;
case 'p': // 2 strings to match. case 'p': // 2 strings to match.
if (BuiltinName.substr(17, 9) != "ermilvarp") if (memcmp(BuiltinName.data()+17, "ermilvarp", 9))
break; break;
switch (BuiltinName[26]) { switch (BuiltinName[26]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
return Intrinsic::x86_avx_vpermilvar_pd; // "__builtin_ia32_ vpermilvarpd" return Intrinsic::x86_avx_vpermilvar_pd; // "__builtin_ia32_ vpermilvarpd"
case 's': // 1 string to match. case 's': // 1 string to match.
return Intrinsic::x86_avx_vpermilvar_ps; // "__builtin_ia32_ vpermilvarps" return Intrinsic::x86_avx_vpermilvar_ps; // "__builtin_ia32_ vpermilvarps"
} }
break; break;
} }
break; break;
} }
break; break;
case 28: // 20 strings to match. case 28: // 24 strings to match.
if (BuiltinName.substr(0, 15) != "__builtin_ia32_") if (memcmp(BuiltinName.data()+0, "__builtin_ia32_", 15))
break; break;
switch (BuiltinName[15]) { switch (BuiltinName[15]) {
default: break; default: break;
case 'a': // 2 strings to match. case 'a': // 2 strings to match.
if (BuiltinName.substr(16, 2) != "es") if (memcmp(BuiltinName.data()+16, "es", 2))
break; break;
switch (BuiltinName[18]) { switch (BuiltinName[18]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
if (BuiltinName.substr(19, 9) != "eclast128") if (memcmp(BuiltinName.data()+19, "eclast128", 9))
break; break;
return Intrinsic::x86_aesni_aesdeclast; // "__builtin_ia32_ aesdeclast128" return Intrinsic::x86_aesni_aesdeclast; // "__builtin_ia32_ aesdeclast128"
case 'e': // 1 string to match. case 'e': // 1 string to match.
if (BuiltinName.substr(19, 9) != "nclast128") if (memcmp(BuiltinName.data()+19, "nclast128", 9))
break; break;
return Intrinsic::x86_aesni_aesenclast; // "__builtin_ia32_ aesenclast128" return Intrinsic::x86_aesni_aesenclast; // "__builtin_ia32_ aesenclast128"
} }
break; break;
case 'g': // 4 strings to match.
if (memcmp(BuiltinName.data()+16, "ather", 5))
break;
switch (BuiltinName[21]) {
default: break;
case 'd': // 2 strings to match.
if (memcmp(BuiltinName.data()+22, "_p", 2))
break;
switch (BuiltinName[24]) {
default: break;
case 'd': // 1 string to match.
if (memcmp(BuiltinName.data()+25, "256", 3))
break;
return Intrinsic::x86_avx2_gather_d_pd_256; // "__builtin_ia32_
gatherd_pd256"
case 's': // 1 string to match.
if (memcmp(BuiltinName.data()+25, "256", 3))
break;
return Intrinsic::x86_avx2_gather_d_ps_256; // "__builtin_ia32_
gatherd_ps256"
}
break;
case 'q': // 2 strings to match.
if (memcmp(BuiltinName.data()+22, "_p", 2))
break;
switch (BuiltinName[24]) {
default: break;
case 'd': // 1 string to match.
if (memcmp(BuiltinName.data()+25, "256", 3))
break;
return Intrinsic::x86_avx2_gather_q_pd_256; // "__builtin_ia32_
gatherq_pd256"
case 's': // 1 string to match.
if (memcmp(BuiltinName.data()+25, "256", 3))
break;
return Intrinsic::x86_avx2_gather_q_ps_256; // "__builtin_ia32_
gatherq_ps256"
}
break;
}
break;
case 'i': // 1 string to match. case 'i': // 1 string to match.
if (BuiltinName.substr(16, 12) != "nsert128i256") if (memcmp(BuiltinName.data()+16, "nsert128i256", 12))
break; break;
return Intrinsic::x86_avx2_vinserti128; // "__builtin_ia32_insert12 8i256" return Intrinsic::x86_avx2_vinserti128; // "__builtin_ia32_insert12 8i256"
case 'm': // 4 strings to match. case 'm': // 4 strings to match.
if (BuiltinName.substr(16, 3) != "ask") if (memcmp(BuiltinName.data()+16, "ask", 3))
break; break;
switch (BuiltinName[19]) { switch (BuiltinName[19]) {
default: break; default: break;
case 'l': // 2 strings to match. case 'l': // 2 strings to match.
if (BuiltinName.substr(20, 4) != "oadp") if (memcmp(BuiltinName.data()+20, "oadp", 4))
break; break;
switch (BuiltinName[24]) { switch (BuiltinName[24]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
if (BuiltinName.substr(25, 3) != "256") if (memcmp(BuiltinName.data()+25, "256", 3))
break; break;
return Intrinsic::x86_avx_maskload_pd_256; // "__builtin_ia32_ maskloadpd256" return Intrinsic::x86_avx_maskload_pd_256; // "__builtin_ia32_ maskloadpd256"
case 's': // 1 string to match. case 's': // 1 string to match.
if (BuiltinName.substr(25, 3) != "256") if (memcmp(BuiltinName.data()+25, "256", 3))
break; break;
return Intrinsic::x86_avx_maskload_ps_256; // "__builtin_ia32_ maskloadps256" return Intrinsic::x86_avx_maskload_ps_256; // "__builtin_ia32_ maskloadps256"
} }
break; break;
case 's': // 2 strings to match. case 's': // 2 strings to match.
if (BuiltinName.substr(20, 4) != "tore") if (memcmp(BuiltinName.data()+20, "tore", 4))
break; break;
switch (BuiltinName[24]) { switch (BuiltinName[24]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
if (BuiltinName.substr(25, 3) != "256") if (memcmp(BuiltinName.data()+25, "256", 3))
break; break;
return Intrinsic::x86_avx2_maskstore_d_256; // "__builtin_ia32_ maskstored256" return Intrinsic::x86_avx2_maskstore_d_256; // "__builtin_ia32_ maskstored256"
case 'q': // 1 string to match. case 'q': // 1 string to match.
if (BuiltinName.substr(25, 3) != "256") if (memcmp(BuiltinName.data()+25, "256", 3))
break; break;
return Intrinsic::x86_avx2_maskstore_q_256; // "__builtin_ia32_ maskstoreq256" return Intrinsic::x86_avx2_maskstore_q_256; // "__builtin_ia32_ maskstoreq256"
} }
break; break;
} }
break; break;
case 'p': // 11 strings to match. case 'p': // 11 strings to match.
switch (BuiltinName[16]) { switch (BuiltinName[16]) {
default: break; default: break;
case 'c': // 10 strings to match. case 'c': // 10 strings to match.
if (BuiltinName.substr(17, 2) != "mp") if (memcmp(BuiltinName.data()+17, "mp", 2))
break; break;
switch (BuiltinName[19]) { switch (BuiltinName[19]) {
default: break; default: break;
case 'e': // 5 strings to match. case 'e': // 5 strings to match.
if (BuiltinName.substr(20, 4) != "stri") if (memcmp(BuiltinName.data()+20, "stri", 4))
break; break;
switch (BuiltinName[24]) { switch (BuiltinName[24]) {
default: break; default: break;
case 'a': // 1 string to match. case 'a': // 1 string to match.
if (BuiltinName.substr(25, 3) != "128") if (memcmp(BuiltinName.data()+25, "128", 3))
break; break;
return Intrinsic::x86_sse42_pcmpestria128; // "__builtin_ia32_ pcmpestria128" return Intrinsic::x86_sse42_pcmpestria128; // "__builtin_ia32_ pcmpestria128"
case 'c': // 1 string to match. case 'c': // 1 string to match.
if (BuiltinName.substr(25, 3) != "128") if (memcmp(BuiltinName.data()+25, "128", 3))
break; break;
return Intrinsic::x86_sse42_pcmpestric128; // "__builtin_ia32_ pcmpestric128" return Intrinsic::x86_sse42_pcmpestric128; // "__builtin_ia32_ pcmpestric128"
case 'o': // 1 string to match. case 'o': // 1 string to match.
if (BuiltinName.substr(25, 3) != "128") if (memcmp(BuiltinName.data()+25, "128", 3))
break; break;
return Intrinsic::x86_sse42_pcmpestrio128; // "__builtin_ia32_ pcmpestrio128" return Intrinsic::x86_sse42_pcmpestrio128; // "__builtin_ia32_ pcmpestrio128"
case 's': // 1 string to match. case 's': // 1 string to match.
if (BuiltinName.substr(25, 3) != "128") if (memcmp(BuiltinName.data()+25, "128", 3))
break; break;
return Intrinsic::x86_sse42_pcmpestris128; // "__builtin_ia32_ pcmpestris128" return Intrinsic::x86_sse42_pcmpestris128; // "__builtin_ia32_ pcmpestris128"
case 'z': // 1 string to match. case 'z': // 1 string to match.
if (BuiltinName.substr(25, 3) != "128") if (memcmp(BuiltinName.data()+25, "128", 3))
break; break;
return Intrinsic::x86_sse42_pcmpestriz128; // "__builtin_ia32_ pcmpestriz128" return Intrinsic::x86_sse42_pcmpestriz128; // "__builtin_ia32_ pcmpestriz128"
} }
break; break;
case 'i': // 5 strings to match. case 'i': // 5 strings to match.
if (BuiltinName.substr(20, 4) != "stri") if (memcmp(BuiltinName.data()+20, "stri", 4))
break; break;
switch (BuiltinName[24]) { switch (BuiltinName[24]) {
default: break; default: break;
case 'a': // 1 string to match. case 'a': // 1 string to match.
if (BuiltinName.substr(25, 3) != "128") if (memcmp(BuiltinName.data()+25, "128", 3))
break; break;
return Intrinsic::x86_sse42_pcmpistria128; // "__builtin_ia32_ pcmpistria128" return Intrinsic::x86_sse42_pcmpistria128; // "__builtin_ia32_ pcmpistria128"
case 'c': // 1 string to match. case 'c': // 1 string to match.
if (BuiltinName.substr(25, 3) != "128") if (memcmp(BuiltinName.data()+25, "128", 3))
break; break;
return Intrinsic::x86_sse42_pcmpistric128; // "__builtin_ia32_ pcmpistric128" return Intrinsic::x86_sse42_pcmpistric128; // "__builtin_ia32_ pcmpistric128"
case 'o': // 1 string to match. case 'o': // 1 string to match.
if (BuiltinName.substr(25, 3) != "128") if (memcmp(BuiltinName.data()+25, "128", 3))
break; break;
return Intrinsic::x86_sse42_pcmpistrio128; // "__builtin_ia32_ pcmpistrio128" return Intrinsic::x86_sse42_pcmpistrio128; // "__builtin_ia32_ pcmpistrio128"
case 's': // 1 string to match. case 's': // 1 string to match.
if (BuiltinName.substr(25, 3) != "128") if (memcmp(BuiltinName.data()+25, "128", 3))
break; break;
return Intrinsic::x86_sse42_pcmpistris128; // "__builtin_ia32_ pcmpistris128" return Intrinsic::x86_sse42_pcmpistris128; // "__builtin_ia32_ pcmpistris128"
case 'z': // 1 string to match. case 'z': // 1 string to match.
if (BuiltinName.substr(25, 3) != "128") if (memcmp(BuiltinName.data()+25, "128", 3))
break; break;
return Intrinsic::x86_sse42_pcmpistriz128; // "__builtin_ia32_ pcmpistriz128" return Intrinsic::x86_sse42_pcmpistriz128; // "__builtin_ia32_ pcmpistriz128"
} }
break; break;
} }
break; break;
case 'h': // 1 string to match. case 'h': // 1 string to match.
if (BuiltinName.substr(17, 11) != "minposuw128") if (memcmp(BuiltinName.data()+17, "minposuw128", 11))
break; break;
return Intrinsic::x86_sse41_phminposuw; // "__builtin_ia32_ phminposuw128" return Intrinsic::x86_sse41_phminposuw; // "__builtin_ia32_ phminposuw128"
} }
break; break;
case 'v': // 2 strings to match. case 'v': // 2 strings to match.
if (BuiltinName.substr(16, 8) != "testnzcp") if (memcmp(BuiltinName.data()+16, "testnzcp", 8))
break; break;
switch (BuiltinName[24]) { switch (BuiltinName[24]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
if (BuiltinName.substr(25, 3) != "256") if (memcmp(BuiltinName.data()+25, "256", 3))
break; break;
return Intrinsic::x86_avx_vtestnzc_pd_256; // "__builtin_ia32_ vtestnzcpd256" return Intrinsic::x86_avx_vtestnzc_pd_256; // "__builtin_ia32_ vtestnzcpd256"
case 's': // 1 string to match. case 's': // 1 string to match.
if (BuiltinName.substr(25, 3) != "256") if (memcmp(BuiltinName.data()+25, "256", 3))
break; break;
return Intrinsic::x86_avx_vtestnzc_ps_256; // "__builtin_ia32_ vtestnzcps256" return Intrinsic::x86_avx_vtestnzc_ps_256; // "__builtin_ia32_ vtestnzcps256"
} }
break; break;
} }
break; break;
case 29: // 15 strings to match. case 29: // 15 strings to match.
if (BuiltinName.substr(0, 15) != "__builtin_ia32_") if (memcmp(BuiltinName.data()+0, "__builtin_ia32_", 15))
break; break;
switch (BuiltinName[15]) { switch (BuiltinName[15]) {
default: break; default: break;
case 'e': // 1 string to match. case 'e': // 1 string to match.
if (BuiltinName.substr(16, 13) != "xtract128i256") if (memcmp(BuiltinName.data()+16, "xtract128i256", 13))
break; break;
return Intrinsic::x86_avx2_vextracti128; // "__builtin_ia32_extract1 28i256" return Intrinsic::x86_avx2_vextracti128; // "__builtin_ia32_extract1 28i256"
case 'm': // 2 strings to match. case 'm': // 2 strings to match.
if (BuiltinName.substr(16, 9) != "askstorep") if (memcmp(BuiltinName.data()+16, "askstorep", 9))
break; break;
switch (BuiltinName[25]) { switch (BuiltinName[25]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
if (BuiltinName.substr(26, 3) != "256") if (memcmp(BuiltinName.data()+26, "256", 3))
break; break;
return Intrinsic::x86_avx_maskstore_pd_256; // "__builtin_ia32_ maskstorepd256" return Intrinsic::x86_avx_maskstore_pd_256; // "__builtin_ia32_ maskstorepd256"
case 's': // 1 string to match. case 's': // 1 string to match.
if (BuiltinName.substr(26, 3) != "256") if (memcmp(BuiltinName.data()+26, "256", 3))
break; break;
return Intrinsic::x86_avx_maskstore_ps_256; // "__builtin_ia32_ maskstoreps256" return Intrinsic::x86_avx_maskstore_ps_256; // "__builtin_ia32_ maskstoreps256"
} }
break; break;
case 'p': // 8 strings to match. case 'p': // 8 strings to match.
if (BuiltinName.substr(16, 9) != "broadcast") if (memcmp(BuiltinName.data()+16, "broadcast", 9))
break; break;
switch (BuiltinName[25]) { switch (BuiltinName[25]) {
default: break; default: break;
case 'b': // 2 strings to match. case 'b': // 2 strings to match.
switch (BuiltinName[26]) { switch (BuiltinName[26]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(27, 2) != "28") if (memcmp(BuiltinName.data()+27, "28", 2))
break; break;
return Intrinsic::x86_avx2_pbroadcastb_128; // "__builtin_ia32_ pbroadcastb128" return Intrinsic::x86_avx2_pbroadcastb_128; // "__builtin_ia32_ pbroadcastb128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(27, 2) != "56") if (memcmp(BuiltinName.data()+27, "56", 2))
break; break;
return Intrinsic::x86_avx2_pbroadcastb_256; // "__builtin_ia32_ pbroadcastb256" return Intrinsic::x86_avx2_pbroadcastb_256; // "__builtin_ia32_ pbroadcastb256"
} }
break; break;
case 'd': // 2 strings to match. case 'd': // 2 strings to match.
switch (BuiltinName[26]) { switch (BuiltinName[26]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(27, 2) != "28") if (memcmp(BuiltinName.data()+27, "28", 2))
break; break;
return Intrinsic::x86_avx2_pbroadcastd_128; // "__builtin_ia32_ pbroadcastd128" return Intrinsic::x86_avx2_pbroadcastd_128; // "__builtin_ia32_ pbroadcastd128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(27, 2) != "56") if (memcmp(BuiltinName.data()+27, "56", 2))
break; break;
return Intrinsic::x86_avx2_pbroadcastd_256; // "__builtin_ia32_ pbroadcastd256" return Intrinsic::x86_avx2_pbroadcastd_256; // "__builtin_ia32_ pbroadcastd256"
} }
break; break;
case 'q': // 2 strings to match. case 'q': // 2 strings to match.
switch (BuiltinName[26]) { switch (BuiltinName[26]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(27, 2) != "28") if (memcmp(BuiltinName.data()+27, "28", 2))
break; break;
return Intrinsic::x86_avx2_pbroadcastq_128; // "__builtin_ia32_ pbroadcastq128" return Intrinsic::x86_avx2_pbroadcastq_128; // "__builtin_ia32_ pbroadcastq128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(27, 2) != "56") if (memcmp(BuiltinName.data()+27, "56", 2))
break; break;
return Intrinsic::x86_avx2_pbroadcastq_256; // "__builtin_ia32_ pbroadcastq256" return Intrinsic::x86_avx2_pbroadcastq_256; // "__builtin_ia32_ pbroadcastq256"
} }
break; break;
case 'w': // 2 strings to match. case 'w': // 2 strings to match.
switch (BuiltinName[26]) { switch (BuiltinName[26]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(27, 2) != "28") if (memcmp(BuiltinName.data()+27, "28", 2))
break; break;
return Intrinsic::x86_avx2_pbroadcastw_128; // "__builtin_ia32_ pbroadcastw128" return Intrinsic::x86_avx2_pbroadcastw_128; // "__builtin_ia32_ pbroadcastw128"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(27, 2) != "56") if (memcmp(BuiltinName.data()+27, "56", 2))
break; break;
return Intrinsic::x86_avx2_pbroadcastw_256; // "__builtin_ia32_ pbroadcastw256" return Intrinsic::x86_avx2_pbroadcastw_256; // "__builtin_ia32_ pbroadcastw256"
} }
break; break;
} }
break; break;
case 'v': // 4 strings to match. case 'v': // 4 strings to match.
if (BuiltinName.substr(16, 2) != "fm") if (memcmp(BuiltinName.data()+16, "fm", 2))
break; break;
switch (BuiltinName[18]) { switch (BuiltinName[18]) {
default: break; default: break;
case 'a': // 2 strings to match. case 'a': // 2 strings to match.
if (BuiltinName.substr(19, 6) != "ddsubp") if (memcmp(BuiltinName.data()+19, "ddsubp", 6))
break; break;
switch (BuiltinName[25]) { switch (BuiltinName[25]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
if (BuiltinName.substr(26, 3) != "256") if (memcmp(BuiltinName.data()+26, "256", 3))
break; break;
return Intrinsic::x86_fma4_vfmaddsub_pd_256; // "__builtin_ia32_ vfmaddsubpd256" return Intrinsic::x86_fma_vfmaddsub_pd_256; // "__builtin_ia32_ vfmaddsubpd256"
case 's': // 1 string to match. case 's': // 1 string to match.
if (BuiltinName.substr(26, 3) != "256") if (memcmp(BuiltinName.data()+26, "256", 3))
break; break;
return Intrinsic::x86_fma4_vfmaddsub_ps_256; // "__builtin_ia32_ vfmaddsubps256" return Intrinsic::x86_fma_vfmaddsub_ps_256; // "__builtin_ia32_ vfmaddsubps256"
} }
break; break;
case 's': // 2 strings to match. case 's': // 2 strings to match.
if (BuiltinName.substr(19, 6) != "ubaddp") if (memcmp(BuiltinName.data()+19, "ubaddp", 6))
break; break;
switch (BuiltinName[25]) { switch (BuiltinName[25]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
if (BuiltinName.substr(26, 3) != "256") if (memcmp(BuiltinName.data()+26, "256", 3))
break; break;
return Intrinsic::x86_fma4_vfmsubadd_pd_256; // "__builtin_ia32_ vfmsubaddpd256" return Intrinsic::x86_fma_vfmsubadd_pd_256; // "__builtin_ia32_ vfmsubaddpd256"
case 's': // 1 string to match. case 's': // 1 string to match.
if (BuiltinName.substr(26, 3) != "256") if (memcmp(BuiltinName.data()+26, "256", 3))
break; break;
return Intrinsic::x86_fma4_vfmsubadd_ps_256; // "__builtin_ia32_ vfmsubaddps256" return Intrinsic::x86_fma_vfmsubadd_ps_256; // "__builtin_ia32_ vfmsubaddps256"
} }
break; break;
} }
break; break;
} }
break; break;
case 30: // 6 strings to match. case 30: // 6 strings to match.
if (BuiltinName.substr(0, 16) != "__builtin_ia32_v") if (memcmp(BuiltinName.data()+0, "__builtin_ia32_v", 16))
break; break;
switch (BuiltinName[16]) { switch (BuiltinName[16]) {
default: break; default: break;
case 'b': // 4 strings to match. case 'b': // 4 strings to match.
if (BuiltinName.substr(17, 9) != "roadcasts") if (memcmp(BuiltinName.data()+17, "roadcasts", 9))
break; break;
switch (BuiltinName[26]) { switch (BuiltinName[26]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
if (BuiltinName.substr(27, 3) != "256") if (memcmp(BuiltinName.data()+27, "256", 3))
break; break;
return Intrinsic::x86_avx_vbroadcast_sd_256; // "__builtin_ia32_ vbroadcastsd256" return Intrinsic::x86_avx_vbroadcast_sd_256; // "__builtin_ia32_ vbroadcastsd256"
case 'i': // 1 string to match. case 'i': // 1 string to match.
if (BuiltinName.substr(27, 3) != "256") if (memcmp(BuiltinName.data()+27, "256", 3))
break; break;
return Intrinsic::x86_avx2_vbroadcasti128; // "__builtin_ia32_ vbroadcastsi256" return Intrinsic::x86_avx2_vbroadcasti128; // "__builtin_ia32_ vbroadcastsi256"
case 's': // 2 strings to match. case 's': // 2 strings to match.
switch (BuiltinName[27]) { switch (BuiltinName[27]) {
default: break; default: break;
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(28, 2) != "56") if (memcmp(BuiltinName.data()+28, "56", 2))
break; break;
return Intrinsic::x86_avx_vbroadcast_ss_256; // "__builtin_ia32_ vbroadcastss256" return Intrinsic::x86_avx_vbroadcast_ss_256; // "__builtin_ia32_ vbroadcastss256"
case '_': // 1 string to match. case '_': // 1 string to match.
if (BuiltinName.substr(28, 2) != "ps") if (memcmp(BuiltinName.data()+28, "ps", 2))
break; break;
return Intrinsic::x86_avx2_vbroadcast_ss_ps; // "__builtin_ia32_ vbroadcastss_ps" return Intrinsic::x86_avx2_vbroadcast_ss_ps; // "__builtin_ia32_ vbroadcastss_ps"
} }
break; break;
} }
break; break;
case 'p': // 2 strings to match. case 'p': // 2 strings to match.
if (BuiltinName.substr(17, 9) != "ermilvarp") if (memcmp(BuiltinName.data()+17, "ermilvarp", 9))
break; break;
switch (BuiltinName[26]) { switch (BuiltinName[26]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
if (BuiltinName.substr(27, 3) != "256") if (memcmp(BuiltinName.data()+27, "256", 3))
break; break;
return Intrinsic::x86_avx_vpermilvar_pd_256; // "__builtin_ia32_ vpermilvarpd256" return Intrinsic::x86_avx_vpermilvar_pd_256; // "__builtin_ia32_ vpermilvarpd256"
case 's': // 1 string to match. case 's': // 1 string to match.
if (BuiltinName.substr(27, 3) != "256") if (memcmp(BuiltinName.data()+27, "256", 3))
break; break;
return Intrinsic::x86_avx_vpermilvar_ps_256; // "__builtin_ia32_ vpermilvarps256" return Intrinsic::x86_avx_vpermilvar_ps_256; // "__builtin_ia32_ vpermilvarps256"
} }
break; break;
} }
break; break;
case 31: // 3 strings to match. case 31: // 3 strings to match.
if (BuiltinName.substr(0, 26) != "__builtin_ia32_vperm2f128_") if (memcmp(BuiltinName.data()+0, "__builtin_ia32_vperm2f128_", 26))
break; break;
switch (BuiltinName[26]) { switch (BuiltinName[26]) {
default: break; default: break;
case 'p': // 2 strings to match. case 'p': // 2 strings to match.
switch (BuiltinName[27]) { switch (BuiltinName[27]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
if (BuiltinName.substr(28, 3) != "256") if (memcmp(BuiltinName.data()+28, "256", 3))
break; break;
return Intrinsic::x86_avx_vperm2f128_pd_256; // "__builtin_ia32_ vperm2f128_pd256" return Intrinsic::x86_avx_vperm2f128_pd_256; // "__builtin_ia32_ vperm2f128_pd256"
case 's': // 1 string to match. case 's': // 1 string to match.
if (BuiltinName.substr(28, 3) != "256") if (memcmp(BuiltinName.data()+28, "256", 3))
break; break;
return Intrinsic::x86_avx_vperm2f128_ps_256; // "__builtin_ia32_ vperm2f128_ps256" return Intrinsic::x86_avx_vperm2f128_ps_256; // "__builtin_ia32_ vperm2f128_ps256"
} }
break; break;
case 's': // 1 string to match. case 's': // 1 string to match.
if (BuiltinName.substr(27, 4) != "i256") if (memcmp(BuiltinName.data()+27, "i256", 4))
break; break;
return Intrinsic::x86_avx_vperm2f128_si_256; // "__builtin_ia32_ vperm2f128_si256" return Intrinsic::x86_avx_vperm2f128_si_256; // "__builtin_ia32_ vperm2f128_si256"
} }
break; break;
case 32: // 3 strings to match. case 32: // 3 strings to match.
if (BuiltinName.substr(0, 27) != "__builtin_ia32_vinsertf128_") if (memcmp(BuiltinName.data()+0, "__builtin_ia32_vinsertf128_", 27))
break; break;
switch (BuiltinName[27]) { switch (BuiltinName[27]) {
default: break; default: break;
case 'p': // 2 strings to match. case 'p': // 2 strings to match.
switch (BuiltinName[28]) { switch (BuiltinName[28]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
if (BuiltinName.substr(29, 3) != "256") if (memcmp(BuiltinName.data()+29, "256", 3))
break; break;
return Intrinsic::x86_avx_vinsertf128_pd_256; // "__builtin_ia32_ vinsertf128_pd256" return Intrinsic::x86_avx_vinsertf128_pd_256; // "__builtin_ia32_ vinsertf128_pd256"
case 's': // 1 string to match. case 's': // 1 string to match.
if (BuiltinName.substr(29, 3) != "256") if (memcmp(BuiltinName.data()+29, "256", 3))
break; break;
return Intrinsic::x86_avx_vinsertf128_ps_256; // "__builtin_ia32_ vinsertf128_ps256" return Intrinsic::x86_avx_vinsertf128_ps_256; // "__builtin_ia32_ vinsertf128_ps256"
} }
break; break;
case 's': // 1 string to match. case 's': // 1 string to match.
if (BuiltinName.substr(28, 4) != "i256") if (memcmp(BuiltinName.data()+28, "i256", 4))
break; break;
return Intrinsic::x86_avx_vinsertf128_si_256; // "__builtin_ia32_ vinsertf128_si256" return Intrinsic::x86_avx_vinsertf128_si_256; // "__builtin_ia32_ vinsertf128_si256"
} }
break; break;
case 33: // 6 strings to match. case 33: // 6 strings to match.
if (BuiltinName.substr(0, 15) != "__builtin_ia32_") if (memcmp(BuiltinName.data()+0, "__builtin_ia32_", 15))
break; break;
switch (BuiltinName[15]) { switch (BuiltinName[15]) {
default: break; default: break;
case 'a': // 1 string to match. case 'a': // 1 string to match.
if (BuiltinName.substr(16, 17) != "eskeygenassist128") if (memcmp(BuiltinName.data()+16, "eskeygenassist128", 17))
break; break;
return Intrinsic::x86_aesni_aeskeygenassist; // "__builtin_ia32_ aeskeygenassist128" return Intrinsic::x86_aesni_aeskeygenassist; // "__builtin_ia32_ aeskeygenassist128"
case 'v': // 5 strings to match. case 'v': // 5 strings to match.
switch (BuiltinName[16]) { switch (BuiltinName[16]) {
default: break; default: break;
case 'b': // 2 strings to match. case 'b': // 2 strings to match.
if (BuiltinName.substr(17, 9) != "roadcasts") if (memcmp(BuiltinName.data()+17, "roadcasts", 9))
break; break;
switch (BuiltinName[26]) { switch (BuiltinName[26]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
if (BuiltinName.substr(27, 6) != "_pd256") if (memcmp(BuiltinName.data()+27, "_pd256", 6))
break; break;
return Intrinsic::x86_avx2_vbroadcast_sd_pd_256; // "__built in_ia32_vbroadcastsd_pd256" return Intrinsic::x86_avx2_vbroadcast_sd_pd_256; // "__built in_ia32_vbroadcastsd_pd256"
case 's': // 1 string to match. case 's': // 1 string to match.
if (BuiltinName.substr(27, 6) != "_ps256") if (memcmp(BuiltinName.data()+27, "_ps256", 6))
break; break;
return Intrinsic::x86_avx2_vbroadcast_ss_ps_256; // "__built in_ia32_vbroadcastss_ps256" return Intrinsic::x86_avx2_vbroadcast_ss_ps_256; // "__built in_ia32_vbroadcastss_ps256"
} }
break; break;
case 'e': // 3 strings to match. case 'e': // 3 strings to match.
if (BuiltinName.substr(17, 11) != "xtractf128_") if (memcmp(BuiltinName.data()+17, "xtractf128_", 11))
break; break;
switch (BuiltinName[28]) { switch (BuiltinName[28]) {
default: break; default: break;
case 'p': // 2 strings to match. case 'p': // 2 strings to match.
switch (BuiltinName[29]) { switch (BuiltinName[29]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
if (BuiltinName.substr(30, 3) != "256") if (memcmp(BuiltinName.data()+30, "256", 3))
break; break;
return Intrinsic::x86_avx_vextractf128_pd_256; // "__built in_ia32_vextractf128_pd256" return Intrinsic::x86_avx_vextractf128_pd_256; // "__built in_ia32_vextractf128_pd256"
case 's': // 1 string to match. case 's': // 1 string to match.
if (BuiltinName.substr(30, 3) != "256") if (memcmp(BuiltinName.data()+30, "256", 3))
break; break;
return Intrinsic::x86_avx_vextractf128_ps_256; // "__built in_ia32_vextractf128_ps256" return Intrinsic::x86_avx_vextractf128_ps_256; // "__built in_ia32_vextractf128_ps256"
} }
break; break;
case 's': // 1 string to match. case 's': // 1 string to match.
if (BuiltinName.substr(29, 4) != "i256") if (memcmp(BuiltinName.data()+29, "i256", 4))
break; break;
return Intrinsic::x86_avx_vextractf128_si_256; // "__built in_ia32_vextractf128_si256" return Intrinsic::x86_avx_vextractf128_si_256; // "__built in_ia32_vextractf128_si256"
} }
break; break;
} }
break; break;
} }
break; break;
case 35: // 6 strings to match. case 35: // 6 strings to match.
if (BuiltinName.substr(0, 15) != "__builtin_ia32_") if (memcmp(BuiltinName.data()+0, "__builtin_ia32_", 15))
break; break;
switch (BuiltinName[15]) { switch (BuiltinName[15]) {
default: break; default: break;
case 'p': // 4 strings to match. case 'p': // 4 strings to match.
if (BuiltinName[16] != 's') if (BuiltinName[16] != 's')
break; break;
switch (BuiltinName[17]) { switch (BuiltinName[17]) {
default: break; default: break;
case 'l': // 2 strings to match. case 'l': // 2 strings to match.
if (BuiltinName.substr(18, 4) != "ldqi") if (memcmp(BuiltinName.data()+18, "ldqi", 4))
break; break;
switch (BuiltinName[22]) { switch (BuiltinName[22]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(23, 12) != "28_byteshift") if (memcmp(BuiltinName.data()+23, "28_byteshift", 12))
break; break;
return Intrinsic::x86_sse2_psll_dq_bs; // "__builtin_ia32_ pslldqi128_byteshift" return Intrinsic::x86_sse2_psll_dq_bs; // "__builtin_ia32_ pslldqi128_byteshift"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(23, 12) != "56_byteshift") if (memcmp(BuiltinName.data()+23, "56_byteshift", 12))
break; break;
return Intrinsic::x86_avx2_psll_dq_bs; // "__builtin_ia32_ pslldqi256_byteshift" return Intrinsic::x86_avx2_psll_dq_bs; // "__builtin_ia32_ pslldqi256_byteshift"
} }
break; break;
case 'r': // 2 strings to match. case 'r': // 2 strings to match.
if (BuiltinName.substr(18, 4) != "ldqi") if (memcmp(BuiltinName.data()+18, "ldqi", 4))
break; break;
switch (BuiltinName[22]) { switch (BuiltinName[22]) {
default: break; default: break;
case '1': // 1 string to match. case '1': // 1 string to match.
if (BuiltinName.substr(23, 12) != "28_byteshift") if (memcmp(BuiltinName.data()+23, "28_byteshift", 12))
break; break;
return Intrinsic::x86_sse2_psrl_dq_bs; // "__builtin_ia32_ psrldqi128_byteshift" return Intrinsic::x86_sse2_psrl_dq_bs; // "__builtin_ia32_ psrldqi128_byteshift"
case '2': // 1 string to match. case '2': // 1 string to match.
if (BuiltinName.substr(23, 12) != "56_byteshift") if (memcmp(BuiltinName.data()+23, "56_byteshift", 12))
break; break;
return Intrinsic::x86_avx2_psrl_dq_bs; // "__builtin_ia32_ psrldqi256_byteshift" return Intrinsic::x86_avx2_psrl_dq_bs; // "__builtin_ia32_ psrldqi256_byteshift"
} }
break; break;
} }
break; break;
case 'v': // 2 strings to match. case 'v': // 2 strings to match.
if (BuiltinName.substr(16, 15) != "broadcastf128_p") if (memcmp(BuiltinName.data()+16, "broadcastf128_p", 15))
break; break;
switch (BuiltinName[31]) { switch (BuiltinName[31]) {
default: break; default: break;
case 'd': // 1 string to match. case 'd': // 1 string to match.
if (BuiltinName.substr(32, 3) != "256") if (memcmp(BuiltinName.data()+32, "256", 3))
break; break;
return Intrinsic::x86_avx_vbroadcastf128_pd_256; // "__built in_ia32_vbroadcastf128_pd256" return Intrinsic::x86_avx_vbroadcastf128_pd_256; // "__built in_ia32_vbroadcastf128_pd256"
case 's': // 1 string to match. case 's': // 1 string to match.
if (BuiltinName.substr(32, 3) != "256") if (memcmp(BuiltinName.data()+32, "256", 3))
break; break;
return Intrinsic::x86_avx_vbroadcastf128_ps_256; // "__built in_ia32_vbroadcastf128_ps256" return Intrinsic::x86_avx_vbroadcastf128_ps_256; // "__built in_ia32_vbroadcastf128_ps256"
} }
break; break;
} }
break; break;
} }
} }
return Intrinsic::not_intrinsic; return Intrinsic::not_intrinsic;
} }
 End of changes. 3478 change blocks. 
23237 lines changed or deleted 27800 lines changed or added


 Intrinsics.h   Intrinsics.h 
skipping to change at line 53 skipping to change at line 53
, num_intrinsics , num_intrinsics
}; };
/// Intrinsic::getName(ID) - Return the LLVM name for an intrinsic, such as /// Intrinsic::getName(ID) - Return the LLVM name for an intrinsic, such as
/// "llvm.ppc.altivec.lvx". /// "llvm.ppc.altivec.lvx".
std::string getName(ID id, ArrayRef<Type*> Tys = ArrayRef<Type*>()); std::string getName(ID id, ArrayRef<Type*> Tys = ArrayRef<Type*>());
/// Intrinsic::getType(ID) - Return the function type for an intrinsic. /// Intrinsic::getType(ID) - Return the function type for an intrinsic.
/// ///
FunctionType *getType(LLVMContext &Context, ID id, FunctionType *getType(LLVMContext &Context, ID id,
ArrayRef<Type*> Tys = ArrayRef<Type*>()); ArrayRef<Type*> Tys = ArrayRef<Type*>());
/// Intrinsic::isOverloaded(ID) - Returns true if the intrinsic can be /// Intrinsic::isOverloaded(ID) - Returns true if the intrinsic can be
/// overloaded. /// overloaded.
bool isOverloaded(ID id); bool isOverloaded(ID id);
/// Intrinsic::getAttributes(ID) - Return the attributes for an intrinsic . /// Intrinsic::getAttributes(ID) - Return the attributes for an intrinsic .
/// ///
AttrListPtr getAttributes(ID id); AttrListPtr getAttributes(LLVMContext &C, ID id);
/// Intrinsic::getDeclaration(M, ID) - Create or insert an LLVM Function /// Intrinsic::getDeclaration(M, ID) - Create or insert an LLVM Function
/// declaration for an intrinsic, and return it. /// declaration for an intrinsic, and return it.
/// ///
/// The Tys and numTys parameters are for intrinsics with overloaded type s /// The Tys and numTys parameters are for intrinsics with overloaded type s
/// (e.g., those using iAny, fAny, vAny, or iPTRAny). For a declaration f or an /// (e.g., those using iAny, fAny, vAny, or iPTRAny). For a declaration f or an
/// overloaded intrinsic, Tys should point to an array of numTys pointers to /// overloaded intrinsic, Tys should point to an array of numTys pointers to
/// Type, and must provide exactly one type for each overloaded type in t he /// Type, and must provide exactly one type for each overloaded type in t he
/// intrinsic. /// intrinsic.
Function *getDeclaration(Module *M, ID id, Function *getDeclaration(Module *M, ID id,
ArrayRef<Type*> Tys = ArrayRef<Type*>()); ArrayRef<Type*> Tys = ArrayRef<Type*>());
/// Map a GCC builtin name to an intrinsic ID. /// Map a GCC builtin name to an intrinsic ID.
ID getIntrinsicForGCCBuiltin(const char *Prefix, const char *BuiltinName) ; ID getIntrinsicForGCCBuiltin(const char *Prefix, const char *BuiltinName) ;
/// IITDescriptor - This is a type descriptor which explains the type
/// requirements of an intrinsic. This is returned by
/// getIntrinsicInfoTableEntries.
struct IITDescriptor {
enum IITDescriptorKind {
Void, MMX, Metadata, Float, Double,
Integer, Vector, Pointer, Struct,
Argument, ExtendVecArgument, TruncVecArgument
} Kind;
union {
unsigned Integer_Width;
unsigned Float_Width;
unsigned Vector_Width;
unsigned Pointer_AddressSpace;
unsigned Struct_NumElements;
unsigned Argument_Info;
};
enum ArgKind {
AK_AnyInteger,
AK_AnyFloat,
AK_AnyVector,
AK_AnyPointer
};
unsigned getArgumentNumber() const {
assert(Kind == Argument || Kind == ExtendVecArgument ||
Kind == TruncVecArgument);
return Argument_Info >> 2;
}
ArgKind getArgumentKind() const {
assert(Kind == Argument || Kind == ExtendVecArgument ||
Kind == TruncVecArgument);
return (ArgKind)(Argument_Info&3);
}
static IITDescriptor get(IITDescriptorKind K, unsigned Field) {
IITDescriptor Result = { K, { Field } };
return Result;
}
};
/// getIntrinsicInfoTableEntries - Return the IIT table descriptor for th
e
/// specified intrinsic into an array of IITDescriptors.
///
void getIntrinsicInfoTableEntries(ID id, SmallVectorImpl<IITDescriptor> &
T);
} // End Intrinsic namespace } // End Intrinsic namespace
} // End llvm namespace } // End llvm namespace
#endif #endif
 End of changes. 3 change blocks. 
2 lines changed or deleted 51 lines changed or added


 Intrinsics.td   Intrinsics.td 
skipping to change at line 58 skipping to change at line 58
def Commutative : IntrinsicProperty; def Commutative : IntrinsicProperty;
// Throws - This intrinsic can throw. // Throws - This intrinsic can throw.
def Throws : IntrinsicProperty; def Throws : IntrinsicProperty;
// NoCapture - The specified argument pointer is not captured by the intrin sic. // NoCapture - The specified argument pointer is not captured by the intrin sic.
class NoCapture<int argNo> : IntrinsicProperty { class NoCapture<int argNo> : IntrinsicProperty {
int ArgNo = argNo; int ArgNo = argNo;
} }
def IntrNoReturn : IntrinsicProperty;
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// Types used by intrinsics. // Types used by intrinsics.
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
class LLVMType<ValueType vt> { class LLVMType<ValueType vt> {
ValueType VT = vt; ValueType VT = vt;
} }
class LLVMPointerType<LLVMType elty> class LLVMQualPointerType<LLVMType elty, int addrspace>
: LLVMType<iPTR>{ : LLVMType<iPTR>{
LLVMType ElTy = elty; LLVMType ElTy = elty;
int AddrSpace = addrspace;
} }
class LLVMPointerType<LLVMType elty>
: LLVMQualPointerType<elty, 0>;
class LLVMAnyPointerType<LLVMType elty> class LLVMAnyPointerType<LLVMType elty>
: LLVMType<iPTRAny>{ : LLVMType<iPTRAny>{
LLVMType ElTy = elty; LLVMType ElTy = elty;
} }
// Match the type of another intrinsic parameter. Number is an index into the // Match the type of another intrinsic parameter. Number is an index into the
// list of overloaded types for the intrinsic, excluding all the fixed type s. // list of overloaded types for the intrinsic, excluding all the fixed type s.
// The Number value must refer to a previously listed type. For example: // The Number value must refer to a previously listed type. For example:
// Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_anyfloat_ty, LLVMMatchType <0>]> // Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_anyfloat_ty, LLVMMatchType <0>]>
// has two overloaded types, the 2nd and 3rd arguments. LLVMMatchType<0> // has two overloaded types, the 2nd and 3rd arguments. LLVMMatchType<0>
skipping to change at line 118 skipping to change at line 124
def llvm_ptr_ty : LLVMPointerType<llvm_i8_ty>; // i8* def llvm_ptr_ty : LLVMPointerType<llvm_i8_ty>; // i8*
def llvm_ptrptr_ty : LLVMPointerType<llvm_ptr_ty>; // i8** def llvm_ptrptr_ty : LLVMPointerType<llvm_ptr_ty>; // i8**
def llvm_anyptr_ty : LLVMAnyPointerType<llvm_i8_ty>; // (space )i8* def llvm_anyptr_ty : LLVMAnyPointerType<llvm_i8_ty>; // (space )i8*
def llvm_empty_ty : LLVMType<OtherVT>; // { } def llvm_empty_ty : LLVMType<OtherVT>; // { }
def llvm_descriptor_ty : LLVMPointerType<llvm_empty_ty>; // { }* def llvm_descriptor_ty : LLVMPointerType<llvm_empty_ty>; // { }*
def llvm_metadata_ty : LLVMType<MetadataVT>; // !{...} def llvm_metadata_ty : LLVMType<MetadataVT>; // !{...}
def llvm_x86mmx_ty : LLVMType<x86mmx>; def llvm_x86mmx_ty : LLVMType<x86mmx>;
def llvm_ptrx86mmx_ty : LLVMPointerType<llvm_x86mmx_ty>; // <1 x i 64>* def llvm_ptrx86mmx_ty : LLVMPointerType<llvm_x86mmx_ty>; // <1 x i 64>*
def llvm_v2i1_ty : LLVMType<v2i1>; // 2 x i1
def llvm_v4i1_ty : LLVMType<v4i1>; // 4 x i1
def llvm_v8i1_ty : LLVMType<v8i1>; // 8 x i1
def llvm_v16i1_ty : LLVMType<v16i1>; // 16 x i1
def llvm_v2i8_ty : LLVMType<v2i8>; // 2 x i8 def llvm_v2i8_ty : LLVMType<v2i8>; // 2 x i8
def llvm_v4i8_ty : LLVMType<v4i8>; // 4 x i8 def llvm_v4i8_ty : LLVMType<v4i8>; // 4 x i8
def llvm_v8i8_ty : LLVMType<v8i8>; // 8 x i8 def llvm_v8i8_ty : LLVMType<v8i8>; // 8 x i8
def llvm_v16i8_ty : LLVMType<v16i8>; // 16 x i8 def llvm_v16i8_ty : LLVMType<v16i8>; // 16 x i8
def llvm_v32i8_ty : LLVMType<v32i8>; // 32 x i8 def llvm_v32i8_ty : LLVMType<v32i8>; // 32 x i8
def llvm_v1i16_ty : LLVMType<v1i16>; // 1 x i16
def llvm_v2i16_ty : LLVMType<v2i16>; // 2 x i16 def llvm_v2i16_ty : LLVMType<v2i16>; // 2 x i16
def llvm_v4i16_ty : LLVMType<v4i16>; // 4 x i16 def llvm_v4i16_ty : LLVMType<v4i16>; // 4 x i16
def llvm_v8i16_ty : LLVMType<v8i16>; // 8 x i16 def llvm_v8i16_ty : LLVMType<v8i16>; // 8 x i16
def llvm_v16i16_ty : LLVMType<v16i16>; // 16 x i16 def llvm_v16i16_ty : LLVMType<v16i16>; // 16 x i16
def llvm_v1i32_ty : LLVMType<v1i32>; // 1 x i32
def llvm_v2i32_ty : LLVMType<v2i32>; // 2 x i32 def llvm_v2i32_ty : LLVMType<v2i32>; // 2 x i32
def llvm_v4i32_ty : LLVMType<v4i32>; // 4 x i32 def llvm_v4i32_ty : LLVMType<v4i32>; // 4 x i32
def llvm_v8i32_ty : LLVMType<v8i32>; // 8 x i32 def llvm_v8i32_ty : LLVMType<v8i32>; // 8 x i32
def llvm_v16i32_ty : LLVMType<v16i32>; // 16 x i32
def llvm_v1i64_ty : LLVMType<v1i64>; // 1 x i64 def llvm_v1i64_ty : LLVMType<v1i64>; // 1 x i64
def llvm_v2i64_ty : LLVMType<v2i64>; // 2 x i64 def llvm_v2i64_ty : LLVMType<v2i64>; // 2 x i64
def llvm_v4i64_ty : LLVMType<v4i64>; // 4 x i64 def llvm_v4i64_ty : LLVMType<v4i64>; // 4 x i64
def llvm_v8i64_ty : LLVMType<v8i64>; // 8 x i64
def llvm_v16i64_ty : LLVMType<v16i64>; // 16 x i64
def llvm_v2f32_ty : LLVMType<v2f32>; // 2 x float def llvm_v2f32_ty : LLVMType<v2f32>; // 2 x float
def llvm_v4f32_ty : LLVMType<v4f32>; // 4 x float def llvm_v4f32_ty : LLVMType<v4f32>; // 4 x float
def llvm_v8f32_ty : LLVMType<v8f32>; // 8 x float def llvm_v8f32_ty : LLVMType<v8f32>; // 8 x float
def llvm_v2f64_ty : LLVMType<v2f64>; // 2 x double def llvm_v2f64_ty : LLVMType<v2f64>; // 2 x double
def llvm_v4f64_ty : LLVMType<v4f64>; // 4 x double def llvm_v4f64_ty : LLVMType<v4f64>; // 4 x double
def llvm_vararg_ty : LLVMType<isVoid>; // this means vararg here def llvm_vararg_ty : LLVMType<isVoid>; // this means vararg here
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
skipping to change at line 157 skipping to change at line 172
// intrinsic definition should start with "int_", then match the LLVM intri nsic // intrinsic definition should start with "int_", then match the LLVM intri nsic
// name with the "llvm." prefix removed, and all "."s turned into "_"s. Fo r // name with the "llvm." prefix removed, and all "."s turned into "_"s. Fo r
// example, llvm.bswap.i16 -> int_bswap_i16. // example, llvm.bswap.i16 -> int_bswap_i16.
// //
// * RetTypes is a list containing the return types expected for the // * RetTypes is a list containing the return types expected for the
// intrinsic. // intrinsic.
// * ParamTypes is a list containing the parameter types expected for the // * ParamTypes is a list containing the parameter types expected for the
// intrinsic. // intrinsic.
// * Properties can be set to describe the behavior of the intrinsic. // * Properties can be set to describe the behavior of the intrinsic.
// //
class SDPatternOperator;
class Intrinsic<list<LLVMType> ret_types, class Intrinsic<list<LLVMType> ret_types,
list<LLVMType> param_types = [], list<LLVMType> param_types = [],
list<IntrinsicProperty> properties = [], list<IntrinsicProperty> properties = [],
string name = ""> { string name = ""> : SDPatternOperator {
string LLVMName = name; string LLVMName = name;
string TargetPrefix = ""; // Set to a prefix for target-specific intrin sics. string TargetPrefix = ""; // Set to a prefix for target-specific intrin sics.
list<LLVMType> RetTypes = ret_types; list<LLVMType> RetTypes = ret_types;
list<LLVMType> ParamTypes = param_types; list<LLVMType> ParamTypes = param_types;
list<IntrinsicProperty> Properties = properties; list<IntrinsicProperty> Properties = properties;
bit isTarget = 0; bit isTarget = 0;
} }
/// GCCBuiltin - If this intrinsic exactly corresponds to a GCC builtin, th is /// GCCBuiltin - If this intrinsic exactly corresponds to a GCC builtin, th is
skipping to change at line 254 skipping to change at line 270
def int_powi : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>, llvm_i32_ ty]>; def int_powi : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>, llvm_i32_ ty]>;
def int_sin : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>; def int_sin : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
def int_cos : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>; def int_cos : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
def int_pow : Intrinsic<[llvm_anyfloat_ty], def int_pow : Intrinsic<[llvm_anyfloat_ty],
[LLVMMatchType<0>, LLVMMatchType<0>]>; [LLVMMatchType<0>, LLVMMatchType<0>]>;
def int_log : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>; def int_log : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
def int_log10: Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>; def int_log10: Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
def int_log2 : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>; def int_log2 : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
def int_exp : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>; def int_exp : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
def int_exp2 : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>; def int_exp2 : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
def int_fabs : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
def int_floor : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
} }
let Properties = [IntrNoMem] in { let Properties = [IntrNoMem] in {
def int_fma : Intrinsic<[llvm_anyfloat_ty], def int_fma : Intrinsic<[llvm_anyfloat_ty],
[LLVMMatchType<0>, LLVMMatchType<0>, [LLVMMatchType<0>, LLVMMatchType<0>,
LLVMMatchType<0>]>; LLVMMatchType<0>]>;
def int_fmuladd : Intrinsic<[llvm_anyfloat_ty],
[LLVMMatchType<0>, LLVMMatchType<0>,
LLVMMatchType<0>]>;
} }
// NOTE: these are internal interfaces. // NOTE: these are internal interfaces.
def int_setjmp : Intrinsic<[llvm_i32_ty], [llvm_ptr_ty]>; def int_setjmp : Intrinsic<[llvm_i32_ty], [llvm_ptr_ty]>;
def int_longjmp : Intrinsic<[], [llvm_ptr_ty, llvm_i32_ty]>; def int_longjmp : Intrinsic<[], [llvm_ptr_ty, llvm_i32_ty], [IntrNoRetur n]>;
def int_sigsetjmp : Intrinsic<[llvm_i32_ty] , [llvm_ptr_ty, llvm_i32_ty]>; def int_sigsetjmp : Intrinsic<[llvm_i32_ty] , [llvm_ptr_ty, llvm_i32_ty]>;
def int_siglongjmp : Intrinsic<[], [llvm_ptr_ty, llvm_i32_ty]>; def int_siglongjmp : Intrinsic<[], [llvm_ptr_ty, llvm_i32_ty], [IntrNoRetur n]>;
// Internal interface for object size checking // Internal interface for object size checking
def int_objectsize : Intrinsic<[llvm_anyint_ty], [llvm_ptr_ty, llvm_i1_ty], def int_objectsize : Intrinsic<[llvm_anyint_ty], [llvm_ptr_ty, llvm_i1_ty],
[IntrNoMem]>, [IntrNoMem]>,
GCCBuiltin<"__builtin_object_size">; GCCBuiltin<"__builtin_object_size">;
//===------------------------- Expect Intrinsics -------------------------- ===// //===------------------------- Expect Intrinsics -------------------------- ===//
// //
def int_expect : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, def int_expect : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>,
LLVMMatchType<0>], [IntrNoMem ]>; LLVMMatchType<0>], [IntrNoMem ]>;
skipping to change at line 298 skipping to change at line 320
//===------------------------ Debugger Intrinsics ------------------------- ===// //===------------------------ Debugger Intrinsics ------------------------- ===//
// //
// None of these intrinsics accesses memory at all...but that doesn't mean the // None of these intrinsics accesses memory at all...but that doesn't mean the
// optimizers can change them aggressively. Special handling needed in a f ew // optimizers can change them aggressively. Special handling needed in a f ew
// places. // places.
let Properties = [IntrNoMem] in { let Properties = [IntrNoMem] in {
def int_dbg_declare : Intrinsic<[], def int_dbg_declare : Intrinsic<[],
[llvm_metadata_ty, llvm_metadata_ty] >; [llvm_metadata_ty, llvm_metadata_ty] >;
def int_dbg_value : Intrinsic<[], def int_dbg_value : Intrinsic<[],
[llvm_metadata_ty, llvm_i64_ty, [llvm_metadata_ty, llvm_i64_ty,
llvm_metadata_ty]>; llvm_metadata_ty]>;
} }
//===------------------ Exception Handling Intrinsics---------------------- ===// //===------------------ Exception Handling Intrinsics---------------------- ===//
// //
// The result of eh.typeid.for depends on the enclosing function, but insid e a // The result of eh.typeid.for depends on the enclosing function, but insid e a
// given function it is 'const' and may be CSE'd etc. // given function it is 'const' and may be CSE'd etc.
def int_eh_typeid_for : Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrNoMem] >; def int_eh_typeid_for : Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrNoMem] >;
skipping to change at line 324 skipping to change at line 346
GCCBuiltin<"__builtin_unwind_init">; GCCBuiltin<"__builtin_unwind_init">;
def int_eh_dwarf_cfa : Intrinsic<[llvm_ptr_ty], [llvm_i32_ty]>; def int_eh_dwarf_cfa : Intrinsic<[llvm_ptr_ty], [llvm_i32_ty]>;
let Properties = [IntrNoMem] in { let Properties = [IntrNoMem] in {
def int_eh_sjlj_lsda : Intrinsic<[llvm_ptr_ty]>; def int_eh_sjlj_lsda : Intrinsic<[llvm_ptr_ty]>;
def int_eh_sjlj_callsite : Intrinsic<[], [llvm_i32_ty]>; def int_eh_sjlj_callsite : Intrinsic<[], [llvm_i32_ty]>;
} }
def int_eh_sjlj_functioncontext : Intrinsic<[], [llvm_ptr_ty]>; def int_eh_sjlj_functioncontext : Intrinsic<[], [llvm_ptr_ty]>;
def int_eh_sjlj_setjmp : Intrinsic<[llvm_i32_ty], [llvm_ptr_ty]>; def int_eh_sjlj_setjmp : Intrinsic<[llvm_i32_ty], [llvm_ptr_ty]>;
def int_eh_sjlj_longjmp : Intrinsic<[], [llvm_ptr_ty]>; def int_eh_sjlj_longjmp : Intrinsic<[], [llvm_ptr_ty], [IntrNoRetur n]>;
//===---------------- Generic Variable Attribute Intrinsics---------------- ===// //===---------------- Generic Variable Attribute Intrinsics---------------- ===//
// //
def int_var_annotation : Intrinsic<[], def int_var_annotation : Intrinsic<[],
[llvm_ptr_ty, llvm_ptr_ty, [llvm_ptr_ty, llvm_ptr_ty,
llvm_ptr_ty, llvm_i32_ty], llvm_ptr_ty, llvm_i32_ty],
[], "llvm.var.annotation">; [], "llvm.var.annotation">;
def int_ptr_annotation : Intrinsic<[LLVMAnyPointerType<llvm_anyint_ty>], def int_ptr_annotation : Intrinsic<[LLVMAnyPointerType<llvm_anyint_ty>],
[LLVMMatchType<0>, llvm_ptr_ty, llvm_ptr _ty, [LLVMMatchType<0>, llvm_ptr_ty, llvm_ptr _ty,
llvm_i32_ty], llvm_i32_ty],
skipping to change at line 397 skipping to change at line 419
[IntrReadWriteArgMem, NoCapture<1>]>; [IntrReadWriteArgMem, NoCapture<1>]>;
def int_invariant_end : Intrinsic<[], def int_invariant_end : Intrinsic<[],
[llvm_descriptor_ty, llvm_i64_ty, [llvm_descriptor_ty, llvm_i64_ty,
llvm_ptr_ty], llvm_ptr_ty],
[IntrReadWriteArgMem, NoCapture<2>]>; [IntrReadWriteArgMem, NoCapture<2>]>;
//===-------------------------- Other Intrinsics -------------------------- ===// //===-------------------------- Other Intrinsics -------------------------- ===//
// //
def int_flt_rounds : Intrinsic<[llvm_i32_ty]>, def int_flt_rounds : Intrinsic<[llvm_i32_ty]>,
GCCBuiltin<"__builtin_flt_rounds">; GCCBuiltin<"__builtin_flt_rounds">;
def int_trap : Intrinsic<[]>, def int_trap : Intrinsic<[], [], [IntrNoReturn]>,
GCCBuiltin<"__builtin_trap">; GCCBuiltin<"__builtin_trap">;
def int_debugtrap : Intrinsic<[]>,
GCCBuiltin<"__builtin_debugtrap">;
// NOP: calls/invokes to this intrinsic are removed by codegen
def int_donothing : Intrinsic<[], [], [IntrNoMem]>;
// Intrisics to support half precision floating point format // Intrisics to support half precision floating point format
let Properties = [IntrNoMem] in { let Properties = [IntrNoMem] in {
def int_convert_to_fp16 : Intrinsic<[llvm_i16_ty], [llvm_float_ty]>, def int_convert_to_fp16 : Intrinsic<[llvm_i16_ty], [llvm_float_ty]>,
GCCBuiltin<"__gnu_f2h_ieee">; GCCBuiltin<"__gnu_f2h_ieee">;
def int_convert_from_fp16 : Intrinsic<[llvm_float_ty], [llvm_i16_ty]>, def int_convert_from_fp16 : Intrinsic<[llvm_float_ty], [llvm_i16_ty]>,
GCCBuiltin<"__gnu_h2f_ieee">; GCCBuiltin<"__gnu_h2f_ieee">;
} }
// These convert intrinsics are to support various conversions between // These convert intrinsics are to support various conversions between
skipping to change at line 440 skipping to change at line 467
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// Target-specific intrinsics // Target-specific intrinsics
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
include "llvm/IntrinsicsPowerPC.td" include "llvm/IntrinsicsPowerPC.td"
include "llvm/IntrinsicsX86.td" include "llvm/IntrinsicsX86.td"
include "llvm/IntrinsicsARM.td" include "llvm/IntrinsicsARM.td"
include "llvm/IntrinsicsCellSPU.td" include "llvm/IntrinsicsCellSPU.td"
include "llvm/IntrinsicsXCore.td" include "llvm/IntrinsicsXCore.td"
include "llvm/IntrinsicsPTX.td"
include "llvm/IntrinsicsHexagon.td" include "llvm/IntrinsicsHexagon.td"
include "llvm/IntrinsicsNVVM.td"
include "llvm/IntrinsicsMips.td"
 End of changes. 21 change blocks. 
8 lines changed or deleted 34 lines changed or added


 IntrinsicsARM.td   IntrinsicsARM.td 
skipping to change at line 18 skipping to change at line 18
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// //
// This file defines all of the ARM-specific intrinsics. // This file defines all of the ARM-specific intrinsics.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// TLS // TLS
let TargetPrefix = "arm" in { // All intrinsics start with "llvm.arm.". let TargetPrefix = "arm" in { // All intrinsics start with "llvm.arm.".
def int_arm_thread_pointer : GCCBuiltin<"__builtin_thread_pointer">,
Intrinsic<[llvm_ptr_ty], [], [IntrNoMem]>; def int_arm_thread_pointer : GCCBuiltin<"__builtin_thread_pointer">,
} Intrinsic<[llvm_ptr_ty], [], [IntrNoMem]>;
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// Saturating Arithmentic // Saturating Arithmentic
let TargetPrefix = "arm" in { // All intrinsics start with "llvm.arm.". def int_arm_qadd : GCCBuiltin<"__builtin_arm_qadd">,
def int_arm_qadd : GCCBuiltin<"__builtin_arm_qadd">, Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem, Commutative]>;
[IntrNoMem, Commutative]>; def int_arm_qsub : GCCBuiltin<"__builtin_arm_qsub">,
def int_arm_qsub : GCCBuiltin<"__builtin_arm_qsub">, Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoM def int_arm_ssat : GCCBuiltin<"__builtin_arm_ssat">,
em]>; Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
def int_arm_ssat : GCCBuiltin<"__builtin_arm_ssat">, def int_arm_usat : GCCBuiltin<"__builtin_arm_usat">,
Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoM Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
em]>;
def int_arm_usat : GCCBuiltin<"__builtin_arm_usat">,
Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoM
em]>;
}
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// Load and Store exclusive doubleword // Load and Store exclusive doubleword
let TargetPrefix = "arm" in { // All intrinsics start with "llvm.arm.". def int_arm_strexd : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty,
def int_arm_strexd : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], [IntrReadWriteArgMem]>;
llvm_ptr_ty], [IntrReadWriteArgMem]>; def int_arm_ldrexd : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_ptr_ty],
def int_arm_ldrexd : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_ptr_ty], [IntrReadArgMem]>;
[IntrReadArgMem]>;
}
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// VFP // VFP
let TargetPrefix = "arm" in { // All intrinsics start with "llvm.arm.". def int_arm_get_fpscr : GCCBuiltin<"__builtin_arm_get_fpscr">,
def int_arm_get_fpscr : GCCBuiltin<"__builtin_arm_get_fpscr">, Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>;
Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>; def int_arm_set_fpscr : GCCBuiltin<"__builtin_arm_set_fpscr">,
def int_arm_set_fpscr : GCCBuiltin<"__builtin_arm_set_fpscr">, Intrinsic<[], [llvm_i32_ty], []>;
Intrinsic<[], [llvm_i32_ty], []>; def int_arm_vcvtr : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty],
def int_arm_vcvtr : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty], [IntrNoMem]>;
[IntrNoMem]>; def int_arm_vcvtru : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty],
def int_arm_vcvtru : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty], [IntrNoMem]>;
[IntrNoMem]>;
}
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// Coprocessor // Coprocessor
let TargetPrefix = "arm" in { // All intrinsics start with "llvm.arm.". // Move to coprocessor
// Move to coprocessor def int_arm_mcr : GCCBuiltin<"__builtin_arm_mcr">,
def int_arm_mcr : GCCBuiltin<"__builtin_arm_mcr">, Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>; def int_arm_mcr2 : GCCBuiltin<"__builtin_arm_mcr2">,
def int_arm_mcr2 : GCCBuiltin<"__builtin_arm_mcr2">, Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
// Move from coprocessor
// Move from coprocessor def int_arm_mrc : GCCBuiltin<"__builtin_arm_mrc">,
def int_arm_mrc : GCCBuiltin<"__builtin_arm_mrc">, Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
llvm_i32_ty, llvm_i32_ty], []>; def int_arm_mrc2 : GCCBuiltin<"__builtin_arm_mrc2">,
def int_arm_mrc2 : GCCBuiltin<"__builtin_arm_mrc2">, Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
llvm_i32_ty, llvm_i32_ty], []>;
// Coprocessor data processing
// Coprocessor data processing def int_arm_cdp : GCCBuiltin<"__builtin_arm_cdp">,
def int_arm_cdp : GCCBuiltin<"__builtin_arm_cdp">, Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>; def int_arm_cdp2 : GCCBuiltin<"__builtin_arm_cdp2">,
def int_arm_cdp2 : GCCBuiltin<"__builtin_arm_cdp2">, Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
// Move from two registers to coprocessor
// Move from two registers to coprocessor def int_arm_mcrr : GCCBuiltin<"__builtin_arm_mcrr">,
def int_arm_mcrr : GCCBuiltin<"__builtin_arm_mcrr">, Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
llvm_i32_ty, llvm_i32_ty], []>; def int_arm_mcrr2 : GCCBuiltin<"__builtin_arm_mcrr2">,
def int_arm_mcrr2 : GCCBuiltin<"__builtin_arm_mcrr2">, Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
llvm_i32_ty, llvm_i32_ty], []>;
}
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// Advanced SIMD (NEON) // Advanced SIMD (NEON)
let TargetPrefix = "arm" in { // All intrinsics start with "llvm.arm.". // The following classes do not correspond directly to GCC builtins.
class Neon_1Arg_Intrinsic
// The following classes do not correspond directly to GCC builtins. : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>], [IntrNoMem]>;
class Neon_1Arg_Intrinsic class Neon_1Arg_Narrow_Intrinsic
: Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>], [IntrNoMem]>; : Intrinsic<[llvm_anyvector_ty],
class Neon_1Arg_Narrow_Intrinsic [LLVMExtendedElementVectorType<0>], [IntrNoMem]>;
: Intrinsic<[llvm_anyvector_ty], class Neon_2Arg_Intrinsic
[LLVMExtendedElementVectorType<0>], [IntrNoMem]>; : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
class Neon_2Arg_Intrinsic [IntrNoMem]>;
: Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>], class Neon_2Arg_Narrow_Intrinsic
[IntrNoMem]>; : Intrinsic<[llvm_anyvector_ty],
class Neon_2Arg_Narrow_Intrinsic [LLVMExtendedElementVectorType<0>,
: Intrinsic<[llvm_anyvector_ty], LLVMExtendedElementVectorType<0>],
[LLVMExtendedElementVectorType<0>, [IntrNoMem]>;
LLVMExtendedElementVectorType<0>], class Neon_2Arg_Long_Intrinsic
[IntrNoMem]>; : Intrinsic<[llvm_anyvector_ty],
class Neon_2Arg_Long_Intrinsic [LLVMTruncatedElementVectorType<0>,
: Intrinsic<[llvm_anyvector_ty], LLVMTruncatedElementVectorType<0>],
[LLVMTruncatedElementVectorType<0>, [IntrNoMem]>;
LLVMTruncatedElementVectorType<0>], class Neon_3Arg_Intrinsic
[IntrNoMem]>; : Intrinsic<[llvm_anyvector_ty],
class Neon_3Arg_Intrinsic [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
: Intrinsic<[llvm_anyvector_ty], [IntrNoMem]>;
[LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], class Neon_3Arg_Long_Intrinsic
[IntrNoMem]>; : Intrinsic<[llvm_anyvector_ty],
class Neon_3Arg_Long_Intrinsic [LLVMMatchType<0>,
: Intrinsic<[llvm_anyvector_ty], LLVMTruncatedElementVectorType<0>,
[LLVMMatchType<0>, LLVMTruncatedElementVectorType<0>],
LLVMTruncatedElementVectorType<0>, [IntrNoMem]>;
LLVMTruncatedElementVectorType<0>], class Neon_CvtFxToFP_Intrinsic
[IntrNoMem]>; : Intrinsic<[llvm_anyfloat_ty], [llvm_anyint_ty, llvm_i32_ty], [IntrNoMem
class Neon_CvtFxToFP_Intrinsic ]>;
: Intrinsic<[llvm_anyfloat_ty], [llvm_anyint_ty, llvm_i32_ty], [IntrNoM class Neon_CvtFPToFx_Intrinsic
em]>; : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, llvm_i32_ty], [IntrNoMem
class Neon_CvtFPToFx_Intrinsic ]>;
: Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, llvm_i32_ty], [IntrNoM
em]>; // The table operands for VTBL and VTBX consist of 1 to 4 v8i8 vectors.
// Besides the table, VTBL has one other v8i8 argument and VTBX has two.
// The table operands for VTBL and VTBX consist of 1 to 4 v8i8 vectors. // Overall, the classes range from 2 to 6 v8i8 arguments.
// Besides the table, VTBL has one other v8i8 argument and VTBX has two. class Neon_Tbl2Arg_Intrinsic
// Overall, the classes range from 2 to 6 v8i8 arguments. : Intrinsic<[llvm_v8i8_ty],
class Neon_Tbl2Arg_Intrinsic [llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
: Intrinsic<[llvm_v8i8_ty], class Neon_Tbl3Arg_Intrinsic
[llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>; : Intrinsic<[llvm_v8i8_ty],
class Neon_Tbl3Arg_Intrinsic [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
: Intrinsic<[llvm_v8i8_ty], class Neon_Tbl4Arg_Intrinsic
[llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>; : Intrinsic<[llvm_v8i8_ty],
class Neon_Tbl4Arg_Intrinsic [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty],
: Intrinsic<[llvm_v8i8_ty], [IntrNoMem]>;
[llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty], class Neon_Tbl5Arg_Intrinsic
[IntrNoMem]>; : Intrinsic<[llvm_v8i8_ty],
class Neon_Tbl5Arg_Intrinsic [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty,
: Intrinsic<[llvm_v8i8_ty], llvm_v8i8_ty], [IntrNoMem]>;
[llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, class Neon_Tbl6Arg_Intrinsic
llvm_v8i8_ty], [IntrNoMem]>; : Intrinsic<[llvm_v8i8_ty],
class Neon_Tbl6Arg_Intrinsic [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty,
: Intrinsic<[llvm_v8i8_ty], llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
[llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty,
llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
}
// Arithmetic ops // Arithmetic ops
let Properties = [IntrNoMem, Commutative] in { let Properties = [IntrNoMem, Commutative] in {
// Vector Add. // Vector Add.
def int_arm_neon_vhadds : Neon_2Arg_Intrinsic; def int_arm_neon_vhadds : Neon_2Arg_Intrinsic;
def int_arm_neon_vhaddu : Neon_2Arg_Intrinsic; def int_arm_neon_vhaddu : Neon_2Arg_Intrinsic;
def int_arm_neon_vrhadds : Neon_2Arg_Intrinsic; def int_arm_neon_vrhadds : Neon_2Arg_Intrinsic;
def int_arm_neon_vrhaddu : Neon_2Arg_Intrinsic; def int_arm_neon_vrhaddu : Neon_2Arg_Intrinsic;
skipping to change at line 211 skipping to change at line 200
// Vector Subtract. // Vector Subtract.
def int_arm_neon_vhsubs : Neon_2Arg_Intrinsic; def int_arm_neon_vhsubs : Neon_2Arg_Intrinsic;
def int_arm_neon_vhsubu : Neon_2Arg_Intrinsic; def int_arm_neon_vhsubu : Neon_2Arg_Intrinsic;
def int_arm_neon_vqsubs : Neon_2Arg_Intrinsic; def int_arm_neon_vqsubs : Neon_2Arg_Intrinsic;
def int_arm_neon_vqsubu : Neon_2Arg_Intrinsic; def int_arm_neon_vqsubu : Neon_2Arg_Intrinsic;
def int_arm_neon_vsubhn : Neon_2Arg_Narrow_Intrinsic; def int_arm_neon_vsubhn : Neon_2Arg_Narrow_Intrinsic;
def int_arm_neon_vrsubhn : Neon_2Arg_Narrow_Intrinsic; def int_arm_neon_vrsubhn : Neon_2Arg_Narrow_Intrinsic;
// Vector Absolute Compare. // Vector Absolute Compare.
let TargetPrefix = "arm" in { def int_arm_neon_vacged : Intrinsic<[llvm_v2i32_ty],
def int_arm_neon_vacged : Intrinsic<[llvm_v2i32_ty], [llvm_v2f32_ty, llvm_v2f32_ty],
[llvm_v2f32_ty, llvm_v2f32_ty], [IntrNoMem]>;
[IntrNoMem]>; def int_arm_neon_vacgeq : Intrinsic<[llvm_v4i32_ty],
def int_arm_neon_vacgeq : Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty],
[llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>;
[IntrNoMem]>; def int_arm_neon_vacgtd : Intrinsic<[llvm_v2i32_ty],
def int_arm_neon_vacgtd : Intrinsic<[llvm_v2i32_ty], [llvm_v2f32_ty, llvm_v2f32_ty],
[llvm_v2f32_ty, llvm_v2f32_ty], [IntrNoMem]>;
[IntrNoMem]>; def int_arm_neon_vacgtq : Intrinsic<[llvm_v4i32_ty],
def int_arm_neon_vacgtq : Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty],
[llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>;
[IntrNoMem]>;
}
// Vector Absolute Differences. // Vector Absolute Differences.
def int_arm_neon_vabds : Neon_2Arg_Intrinsic; def int_arm_neon_vabds : Neon_2Arg_Intrinsic;
def int_arm_neon_vabdu : Neon_2Arg_Intrinsic; def int_arm_neon_vabdu : Neon_2Arg_Intrinsic;
// Vector Pairwise Add. // Vector Pairwise Add.
def int_arm_neon_vpadd : Neon_2Arg_Intrinsic; def int_arm_neon_vpadd : Neon_2Arg_Intrinsic;
// Vector Pairwise Add Long. // Vector Pairwise Add Long.
// Note: This is different than the other "long" NEON intrinsics because // Note: This is different than the other "long" NEON intrinsics because
// the result vector has half as many elements as the source vector. // the result vector has half as many elements as the source vector.
// The source and destination vector types must be specified separately. // The source and destination vector types must be specified separately.
let TargetPrefix = "arm" in { def int_arm_neon_vpaddls : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_t
def int_arm_neon_vpaddls : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector y],
_ty], [IntrNoMem]>;
[IntrNoMem]>; def int_arm_neon_vpaddlu : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_t
def int_arm_neon_vpaddlu : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector y],
_ty], [IntrNoMem]>;
[IntrNoMem]>;
}
// Vector Pairwise Add and Accumulate Long. // Vector Pairwise Add and Accumulate Long.
// Note: This is similar to vpaddl but the destination vector also appears // Note: This is similar to vpaddl but the destination vector also appears
// as the first argument. // as the first argument.
let TargetPrefix = "arm" in { def int_arm_neon_vpadals : Intrinsic<[llvm_anyvector_ty],
def int_arm_neon_vpadals : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, llvm_anyvector_ty],
[LLVMMatchType<0>, llvm_anyvector_ty [IntrNoMem]>;
], def int_arm_neon_vpadalu : Intrinsic<[llvm_anyvector_ty],
[IntrNoMem]>; [LLVMMatchType<0>, llvm_anyvector_ty],
def int_arm_neon_vpadalu : Intrinsic<[llvm_anyvector_ty], [IntrNoMem]>;
[LLVMMatchType<0>, llvm_anyvector_ty
],
[IntrNoMem]>;
}
// Vector Pairwise Maximum and Minimum. // Vector Pairwise Maximum and Minimum.
def int_arm_neon_vpmaxs : Neon_2Arg_Intrinsic; def int_arm_neon_vpmaxs : Neon_2Arg_Intrinsic;
def int_arm_neon_vpmaxu : Neon_2Arg_Intrinsic; def int_arm_neon_vpmaxu : Neon_2Arg_Intrinsic;
def int_arm_neon_vpmins : Neon_2Arg_Intrinsic; def int_arm_neon_vpmins : Neon_2Arg_Intrinsic;
def int_arm_neon_vpminu : Neon_2Arg_Intrinsic; def int_arm_neon_vpminu : Neon_2Arg_Intrinsic;
// Vector Shifts: // Vector Shifts:
// //
// The various saturating and rounding vector shift operations need to be // The various saturating and rounding vector shift operations need to be
skipping to change at line 366 skipping to change at line 349
// Vector Table Extension. // Vector Table Extension.
// Some elements of the destination vector may not be updated, so the origi nal // Some elements of the destination vector may not be updated, so the origi nal
// value of that vector is passed as the first argument. The next 1-4 // value of that vector is passed as the first argument. The next 1-4
// arguments after that are the table. // arguments after that are the table.
def int_arm_neon_vtbx1 : Neon_Tbl3Arg_Intrinsic; def int_arm_neon_vtbx1 : Neon_Tbl3Arg_Intrinsic;
def int_arm_neon_vtbx2 : Neon_Tbl4Arg_Intrinsic; def int_arm_neon_vtbx2 : Neon_Tbl4Arg_Intrinsic;
def int_arm_neon_vtbx3 : Neon_Tbl5Arg_Intrinsic; def int_arm_neon_vtbx3 : Neon_Tbl5Arg_Intrinsic;
def int_arm_neon_vtbx4 : Neon_Tbl6Arg_Intrinsic; def int_arm_neon_vtbx4 : Neon_Tbl6Arg_Intrinsic;
let TargetPrefix = "arm" in { // De-interleaving vector loads from N-element structures.
// Source operands are the address and alignment.
def int_arm_neon_vld1 : Intrinsic<[llvm_anyvector_ty],
[llvm_ptr_ty, llvm_i32_ty],
[IntrReadArgMem]>;
def int_arm_neon_vld2 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
[llvm_ptr_ty, llvm_i32_ty],
[IntrReadArgMem]>;
def int_arm_neon_vld3 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
LLVMMatchType<0>],
[llvm_ptr_ty, llvm_i32_ty],
[IntrReadArgMem]>;
def int_arm_neon_vld4 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
LLVMMatchType<0>, LLVMMatchType<0>],
[llvm_ptr_ty, llvm_i32_ty],
[IntrReadArgMem]>;
// Vector load N-element structure to one lane.
// Source operands are: the address, the N input vectors (since only one
// lane is assigned), the lane number, and the alignment.
def int_arm_neon_vld2lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>]
,
[llvm_ptr_ty, LLVMMatchType<0>,
LLVMMatchType<0>, llvm_i32_ty,
llvm_i32_ty], [IntrReadArgMem]>;
def int_arm_neon_vld3lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
LLVMMatchType<0>],
[llvm_ptr_ty, LLVMMatchType<0>,
LLVMMatchType<0>, LLVMMatchType<0>,
llvm_i32_ty, llvm_i32_ty],
[IntrReadArgMem]>;
def int_arm_neon_vld4lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
LLVMMatchType<0>, LLVMMatchType<0>],
[llvm_ptr_ty, LLVMMatchType<0>,
LLVMMatchType<0>, LLVMMatchType<0>,
LLVMMatchType<0>, llvm_i32_ty,
llvm_i32_ty], [IntrReadArgMem]>;
// Interleaving vector stores from N-element structures.
// Source operands are: the address, the N vectors, and the alignment.
def int_arm_neon_vst1 : Intrinsic<[],
[llvm_ptr_ty, llvm_anyvector_ty,
llvm_i32_ty], [IntrReadWriteArgMem]>;
def int_arm_neon_vst2 : Intrinsic<[],
[llvm_ptr_ty, llvm_anyvector_ty,
LLVMMatchType<0>, llvm_i32_ty],
[IntrReadWriteArgMem]>;
def int_arm_neon_vst3 : Intrinsic<[],
[llvm_ptr_ty, llvm_anyvector_ty,
LLVMMatchType<0>, LLVMMatchType<0>,
llvm_i32_ty], [IntrReadWriteArgMem]>;
def int_arm_neon_vst4 : Intrinsic<[],
[llvm_ptr_ty, llvm_anyvector_ty,
LLVMMatchType<0>, LLVMMatchType<0>,
LLVMMatchType<0>, llvm_i32_ty],
[IntrReadWriteArgMem]>;
// Vector store N-element structure from one lane.
// Source operands are: the address, the N vectors, the lane number, and
// the alignment.
def int_arm_neon_vst2lane : Intrinsic<[],
[llvm_ptr_ty, llvm_anyvector_ty,
LLVMMatchType<0>, llvm_i32_ty,
llvm_i32_ty], [IntrReadWriteArgMem]>
;
def int_arm_neon_vst3lane : Intrinsic<[],
[llvm_ptr_ty, llvm_anyvector_ty,
LLVMMatchType<0>, LLVMMatchType<0>,
llvm_i32_ty, llvm_i32_ty],
[IntrReadWriteArgMem]>;
def int_arm_neon_vst4lane : Intrinsic<[],
[llvm_ptr_ty, llvm_anyvector_ty,
LLVMMatchType<0>, LLVMMatchType<0>,
LLVMMatchType<0>, llvm_i32_ty,
llvm_i32_ty], [IntrReadWriteArgMem]>
;
// Vector bitwise select.
def int_arm_neon_vbsl : Intrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<
0>],
[IntrNoMem]>;
// De-interleaving vector loads from N-element structures. } // end TargetPrefix
// Source operands are the address and alignment.
def int_arm_neon_vld1 : Intrinsic<[llvm_anyvector_ty],
[llvm_ptr_ty, llvm_i32_ty],
[IntrReadArgMem]>;
def int_arm_neon_vld2 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
[llvm_ptr_ty, llvm_i32_ty],
[IntrReadArgMem]>;
def int_arm_neon_vld3 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
LLVMMatchType<0>],
[llvm_ptr_ty, llvm_i32_ty],
[IntrReadArgMem]>;
def int_arm_neon_vld4 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
LLVMMatchType<0>, LLVMMatchType<0>],
[llvm_ptr_ty, llvm_i32_ty],
[IntrReadArgMem]>;
// Vector load N-element structure to one lane.
// Source operands are: the address, the N input vectors (since only one
// lane is assigned), the lane number, and the alignment.
def int_arm_neon_vld2lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0
>],
[llvm_ptr_ty, LLVMMatchType<0>,
LLVMMatchType<0>, llvm_i32_ty,
llvm_i32_ty], [IntrReadArgMem]>;
def int_arm_neon_vld3lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0
>,
LLVMMatchType<0>],
[llvm_ptr_ty, LLVMMatchType<0>,
LLVMMatchType<0>, LLVMMatchType<0>
,
llvm_i32_ty, llvm_i32_ty],
[IntrReadArgMem]>;
def int_arm_neon_vld4lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0
>,
LLVMMatchType<0>, LLVMMatchType<0>
],
[llvm_ptr_ty, LLVMMatchType<0>,
LLVMMatchType<0>, LLVMMatchType<0>
,
LLVMMatchType<0>, llvm_i32_ty,
llvm_i32_ty], [IntrReadArgMem]>;
// Interleaving vector stores from N-element structures.
// Source operands are: the address, the N vectors, and the alignment.
def int_arm_neon_vst1 : Intrinsic<[],
[llvm_ptr_ty, llvm_anyvector_ty,
llvm_i32_ty], [IntrReadWriteArgMem]>;
def int_arm_neon_vst2 : Intrinsic<[],
[llvm_ptr_ty, llvm_anyvector_ty,
LLVMMatchType<0>, llvm_i32_ty],
[IntrReadWriteArgMem]>;
def int_arm_neon_vst3 : Intrinsic<[],
[llvm_ptr_ty, llvm_anyvector_ty,
LLVMMatchType<0>, LLVMMatchType<0>,
llvm_i32_ty], [IntrReadWriteArgMem]>;
def int_arm_neon_vst4 : Intrinsic<[],
[llvm_ptr_ty, llvm_anyvector_ty,
LLVMMatchType<0>, LLVMMatchType<0>,
LLVMMatchType<0>, llvm_i32_ty],
[IntrReadWriteArgMem]>;
// Vector store N-element structure from one lane.
// Source operands are: the address, the N vectors, the lane number, and
// the alignment.
def int_arm_neon_vst2lane : Intrinsic<[],
[llvm_ptr_ty, llvm_anyvector_ty,
LLVMMatchType<0>, llvm_i32_ty,
llvm_i32_ty], [IntrReadWriteArgMem
]>;
def int_arm_neon_vst3lane : Intrinsic<[],
[llvm_ptr_ty, llvm_anyvector_ty,
LLVMMatchType<0>, LLVMMatchType<0>
,
llvm_i32_ty, llvm_i32_ty],
[IntrReadWriteArgMem]>;
def int_arm_neon_vst4lane : Intrinsic<[],
[llvm_ptr_ty, llvm_anyvector_ty,
LLVMMatchType<0>, LLVMMatchType<0>
,
LLVMMatchType<0>, llvm_i32_ty,
llvm_i32_ty], [IntrReadWriteArgMem
]>;
}
 End of changes. 11 change blocks. 
159 lines changed or deleted 218 lines changed or added


 IntrinsicsHexagon.td   IntrinsicsHexagon.td 
skipping to change at line 18 skipping to change at line 18
// //
// This file defines all of the Hexagon-specific intrinsics. // This file defines all of the Hexagon-specific intrinsics.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// Definitions for all Hexagon intrinsics. // Definitions for all Hexagon intrinsics.
// //
// All Hexagon intrinsics start with "llvm.hexagon.". // All Hexagon intrinsics start with "llvm.hexagon.".
let TargetPrefix = "hexagon" in { let TargetPrefix = "hexagon" in {
/// Hexagon_Intrinsic - Base class for all altivec intrinsics. /// Hexagon_Intrinsic - Base class for all Hexagon intrinsics.
class Hexagon_Intrinsic<string GCCIntSuffix, list<LLVMType> ret_types, class Hexagon_Intrinsic<string GCCIntSuffix, list<LLVMType> ret_types,
list<LLVMType> param_types, list<LLVMType> param_types,
list<IntrinsicProperty> properties> list<IntrinsicProperty> properties>
: GCCBuiltin<!strconcat("__builtin_", GCCIntSuffix)>, : GCCBuiltin<!strconcat("__builtin_", GCCIntSuffix)>,
Intrinsic<ret_types, param_types, properties>; Intrinsic<ret_types, param_types, properties>;
} }
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// //
// DEF_FUNCTION_TYPE_1(QI_ftype_MEM,BT_BOOL,BT_PTR) -> // DEF_FUNCTION_TYPE_1(QI_ftype_MEM,BT_BOOL,BT_PTR) ->
skipping to change at line 228 skipping to change at line 228
[IntrNoMem]>; [IntrNoMem]>;
// //
// DEF_FUNCTION_TYPE_2(QI_ftype_DIDI,BT_BOOL,BT_LONGLONG,BT_LONGLONG) -> // DEF_FUNCTION_TYPE_2(QI_ftype_DIDI,BT_BOOL,BT_LONGLONG,BT_LONGLONG) ->
// Hexagon_qi_didi_Intrinsic<string GCCIntSuffix> // Hexagon_qi_didi_Intrinsic<string GCCIntSuffix>
// //
class Hexagon_qi_didi_Intrinsic<string GCCIntSuffix> class Hexagon_qi_didi_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix, : Hexagon_Intrinsic<GCCIntSuffix,
[llvm_i1_ty], [llvm_i64_ty, llvm_i64_ty], [llvm_i1_ty], [llvm_i64_ty, llvm_i64_ty],
[IntrNoMem]>; [IntrNoMem]>;
// //
// DEF_FUNCTION_TYPE_2(QI_ftype_SIDI,BT_BOOL,BT_INT,BT_LONGLONG) ->
// Hexagon_qi_didi_Intrinsic<string GCCIntSuffix>
//
class Hexagon_qi_sidi_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_i1_ty], [llvm_i32_ty, llvm_i64_ty],
[IntrNoMem]>;
//
// DEF_FUNCTION_TYPE_2(QI_ftype_DISI,BT_BOOL,BT_LONGLONG,BT_INT) ->
// Hexagon_qi_disi_Intrinsic<string GCCIntSuffix>
//
class Hexagon_qi_disi_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_i1_ty], [llvm_i64_ty, llvm_i32_ty],
[IntrNoMem]>;
//
// DEF_FUNCTION_TYPE_2(QI_ftype_QIQI,BT_BOOL,BT_BOOL,BT_BOOL) -> // DEF_FUNCTION_TYPE_2(QI_ftype_QIQI,BT_BOOL,BT_BOOL,BT_BOOL) ->
// Hexagon_qi_qiqi_Intrinsic<string GCCIntSuffix> // Hexagon_qi_qiqi_Intrinsic<string GCCIntSuffix>
// //
class Hexagon_qi_qiqi_Intrinsic<string GCCIntSuffix> class Hexagon_qi_qiqi_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix, : Hexagon_Intrinsic<GCCIntSuffix,
[llvm_i1_ty], [llvm_i32_ty, llvm_i32_ty], [llvm_i1_ty], [llvm_i32_ty, llvm_i32_ty],
[IntrNoMem]>; [IntrNoMem]>;
// //
// DEF_FUNCTION_TYPE_2(QI_ftype_QIQIQI,BT_BOOL,BT_BOOL,BT_BOOL) -> // DEF_FUNCTION_TYPE_2(QI_ftype_QIQIQI,BT_BOOL,BT_BOOL,BT_BOOL) ->
// Hexagon_qi_qiqiqi_Intrinsic<string GCCIntSuffix> // Hexagon_qi_qiqiqi_Intrinsic<string GCCIntSuffix>
skipping to change at line 409 skipping to change at line 425
// DEF_FUNCTION_TYPE_4(DI_ftype_DIDISISI,BT_LONGLONG,BT_LONGLONG, // DEF_FUNCTION_TYPE_4(DI_ftype_DIDISISI,BT_LONGLONG,BT_LONGLONG,
// BT_LONGLONG,BT_INT,BT_INT) -> // BT_LONGLONG,BT_INT,BT_INT) ->
// Hexagon_di_didisisi_Intrinsic<string GCCIntSuffix> // Hexagon_di_didisisi_Intrinsic<string GCCIntSuffix>
// //
class Hexagon_di_didisisi_Intrinsic<string GCCIntSuffix> class Hexagon_di_didisisi_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix, : Hexagon_Intrinsic<GCCIntSuffix,
[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty, [llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty,
llvm_i32_ty, llvm_i32_ty], llvm_i32_ty, llvm_i32_ty],
[IntrNoMem]>; [IntrNoMem]>;
class Hexagon_mem_memmemsisi_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_ptr_ty], [llvm_ptr_ty, llvm_ptr_ty,
llvm_i32_ty, llvm_i32_ty],
[IntrReadWriteArgMem]>;
//
// Hexagon_sf_df_Intrinsic<string GCCIntSuffix>
//
class Hexagon_sf_si_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_float_ty], [llvm_i32_ty],
[IntrNoMem]>;
//
// Hexagon_sf_df_Intrinsic<string GCCIntSuffix>
//
class Hexagon_sf_df_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_float_ty], [llvm_double_ty],
[IntrNoMem]>;
//
// Hexagon_sf_di_Intrinsic<string GCCIntSuffix>
//
class Hexagon_sf_di_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_float_ty], [llvm_i64_ty],
[IntrNoMem]>;
//
// Hexagon_df_sf_Intrinsic<string GCCIntSuffix>
//
class Hexagon_df_sf_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_double_ty], [llvm_float_ty],
[IntrNoMem]>;
//
// Hexagon_di_sf_Intrinsic<string GCCIntSuffix>
//
class Hexagon_di_sf_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_i64_ty], [llvm_float_ty],
[IntrNoMem]>;
//
// Hexagon_sf_sf_Intrinsic<string GCCIntSuffix>
//
class Hexagon_sf_sf_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_float_ty], [llvm_float_ty],
[IntrNoMem]>;
//
// Hexagon_si_sf_Intrinsic<string GCCIntSuffix>
//
class Hexagon_si_sf_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_i32_ty], [llvm_float_ty],
[IntrNoMem]>;
//
// Hexagon_si_df_Intrinsic<string GCCIntSuffix>
//
class Hexagon_si_df_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_i32_ty], [llvm_double_ty],
[IntrNoMem]>;
//
// Hexagon_sf_sfsf_Intrinsic<string GCCIntSuffix>
//
class Hexagon_sf_sfsf_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_float_ty], [llvm_float_ty, llvm_float_ty],
[IntrNoMem]>;
//
// Hexagon_qi_sfsf_Intrinsic<string GCCIntSuffix>
//
class Hexagon_qi_sfsf_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_i1_ty], [llvm_float_ty, llvm_float_ty],
[IntrNoMem]>;
//
// Hexagon_qi_sfsi_Intrinsic<string GCCIntSuffix>
//
class Hexagon_qi_sfsi_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_i1_ty], [llvm_float_ty, llvm_i32_ty],
[IntrNoMem]>;
//
// Hexagon_qi_sfqi_Intrinsic<string GCCIntSuffix>
//
class Hexagon_qi_sfqi_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_i1_ty], [llvm_float_ty, llvm_i32_ty],
[IntrNoMem]>;
//
// Hexagon_sf_sfsfsf_Intrinsic<string GCCIntSuffix>
//
class Hexagon_sf_sfsfsf_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_float_ty], [llvm_float_ty, llvm_float_ty,
llvm_float_ty],
[IntrNoMem]>;
//
// Hexagon_sf_sfsfsfqi_Intrinsic<string GCCIntSuffix>
//
class Hexagon_sf_sfsfsfqi_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_float_ty], [llvm_float_ty, llvm_float_ty,
llvm_float_ty,
llvm_i32_ty],
[IntrNoMem]>;
//
// Hexagon_di_dididi_Intrinsic<string GCCIntSuffix>
//
class Hexagon_di_dididisi_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty,
llvm_i64_ty, llvm_i32_ty],
[IntrNoMem]>;
//
// Hexagon_df_si_Intrinsic<string GCCIntSuffix>
//
class Hexagon_df_si_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_double_ty], [llvm_i32_ty],
[IntrNoMem]>;
//
// Hexagon_df_di_Intrinsic<string GCCIntSuffix>
//
class Hexagon_df_di_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_double_ty], [llvm_i64_ty],
[IntrNoMem]>;
//
// Hexagon_di_df_Intrinsic<string GCCIntSuffix>
//
class Hexagon_di_df_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_i64_ty], [llvm_double_ty],
[IntrNoMem]>;
//
// Hexagon_df_df_Intrinsic<string GCCIntSuffix>
//
class Hexagon_df_df_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_double_ty], [llvm_double_ty],
[IntrNoMem]>;
//
// Hexagon_df_dfdf_Intrinsic<string GCCIntSuffix>
//
class Hexagon_df_dfdf_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_double_ty], [llvm_double_ty, llvm_double_ty
],
[IntrNoMem]>;
//
// Hexagon_qi_dfdf_Intrinsic<string GCCIntSuffix>
//
class Hexagon_qi_dfdf_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_i1_ty], [llvm_double_ty, llvm_double_ty],
[IntrNoMem]>;
//
// Hexagon_qi_dfsi_Intrinsic<string GCCIntSuffix>
//
class Hexagon_qi_dfsi_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_i1_ty], [llvm_double_ty, llvm_i32_ty],
[IntrNoMem]>;
//
//
// Hexagon_df_dfdfdf_Intrinsic<string GCCIntSuffix>
//
class Hexagon_df_dfdfdf_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_double_ty], [llvm_double_ty, llvm_double_ty
,
llvm_double_ty],
[IntrNoMem]>;
//
// Hexagon_df_dfdfdf_Intrinsic<string GCCIntSuffix>
//
class Hexagon_df_dfdfdfqi_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_double_ty], [llvm_double_ty, llvm_double_ty
,
llvm_double_ty,
llvm_i32_ty],
[IntrNoMem]>;
// This one below will not be generated from iset.py.
// So make sure, you don't overwrite this one.
//
// BUILTIN_INFO(SI_to_SXTHI_asrh,SI_ftype_SI,1)
//
def int_hexagon_SI_to_SXTHI_asrh :
Hexagon_si_si_Intrinsic<"SI_to_SXTHI_asrh">;
//
// BUILTIN_INFO_NONCONST(circ_ldd,PTR_ftype_PTRPTRSISI,4)
//
def int_hexagon_circ_ldd :
Hexagon_mem_memmemsisi_Intrinsic<"circ_ldd">;
// This one above will not be generated from iset.py.
// So make sure, you don't overwrite this one.
// //
// BUILTIN_INFO(HEXAGON.C2_cmpeq,QI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.C2_cmpeq,QI_ftype_SISI,2)
// //
def int_hexagon_C2_cmpeq : Hexagon_qi_sisi_Intrinsic<"HEXAGON.C2.cmpeq">; def int_hexagon_C2_cmpeq :
Hexagon_qi_sisi_Intrinsic<"HEXAGON_C2_cmpeq">;
// //
// BUILTIN_INFO(HEXAGON.C2_cmpgt,QI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.C2_cmpgt,QI_ftype_SISI,2)
// //
def int_hexagon_C2_cmpgt : Hexagon_qi_sisi_Intrinsic<"HEXAGON.C2.cmpgt">; def int_hexagon_C2_cmpgt :
Hexagon_qi_sisi_Intrinsic<"HEXAGON_C2_cmpgt">;
// //
// BUILTIN_INFO(HEXAGON.C2_cmpgtu,QI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.C2_cmpgtu,QI_ftype_SISI,2)
// //
def int_hexagon_C2_cmpgtu : Hexagon_qi_sisi_Intrinsic<"HEXAGON.C2.cmpgtu">; def int_hexagon_C2_cmpgtu :
Hexagon_qi_sisi_Intrinsic<"HEXAGON_C2_cmpgtu">;
// //
// BUILTIN_INFO(HEXAGON.C2_cmpeqp,QI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.C2_cmpeqp,QI_ftype_DIDI,2)
// //
def int_hexagon_C2_cmpeqp : Hexagon_qi_didi_Intrinsic<"HEXAGON.C2.cmpeqp">; def int_hexagon_C2_cmpeqp :
Hexagon_qi_didi_Intrinsic<"HEXAGON_C2_cmpeqp">;
// //
// BUILTIN_INFO(HEXAGON.C2_cmpgtp,QI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.C2_cmpgtp,QI_ftype_DIDI,2)
// //
def int_hexagon_C2_cmpgtp : Hexagon_qi_didi_Intrinsic<"HEXAGON.C2.cmpgtp">; def int_hexagon_C2_cmpgtp :
Hexagon_qi_didi_Intrinsic<"HEXAGON_C2_cmpgtp">;
// //
// BUILTIN_INFO(HEXAGON.C2_cmpgtup,QI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.C2_cmpgtup,QI_ftype_DIDI,2)
// //
def int_hexagon_C2_cmpgtup : Hexagon_qi_didi_Intrinsic<"HEXAGON.C2.cmpgtup" def int_hexagon_C2_cmpgtup :
>; Hexagon_qi_didi_Intrinsic<"HEXAGON_C2_cmpgtup">;
//
// BUILTIN_INFO(HEXAGON.A4_rcmpeqi,SI_ftype_SISI,2)
//
def int_hexagon_A4_rcmpeqi :
Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_rcmpeqi">;
//
// BUILTIN_INFO(HEXAGON.A4_rcmpneqi,SI_ftype_SISI,2)
//
def int_hexagon_A4_rcmpneqi :
Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_rcmpneqi">;
//
// BUILTIN_INFO(HEXAGON.A4_rcmpeq,SI_ftype_SISI,2)
//
def int_hexagon_A4_rcmpeq :
Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_rcmpeq">;
//
// BUILTIN_INFO(HEXAGON.A4_rcmpneq,SI_ftype_SISI,2)
//
def int_hexagon_A4_rcmpneq :
Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_rcmpneq">;
// //
// BUILTIN_INFO(HEXAGON.C2_bitsset,QI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.C2_bitsset,QI_ftype_SISI,2)
// //
def int_hexagon_C2_bitsset : Hexagon_qi_sisi_Intrinsic<"HEXAGON.C2.bitsset" def int_hexagon_C2_bitsset :
>; Hexagon_qi_sisi_Intrinsic<"HEXAGON_C2_bitsset">;
// //
// BUILTIN_INFO(HEXAGON.C2_bitsclr,QI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.C2_bitsclr,QI_ftype_SISI,2)
// //
def int_hexagon_C2_bitsclr : Hexagon_qi_sisi_Intrinsic<"HEXAGON.C2.bitsclr" def int_hexagon_C2_bitsclr :
>; Hexagon_qi_sisi_Intrinsic<"HEXAGON_C2_bitsclr">;
//
// BUILTIN_INFO(HEXAGON.C4_nbitsset,QI_ftype_SISI,2)
//
def int_hexagon_C4_nbitsset :
Hexagon_qi_sisi_Intrinsic<"HEXAGON_C4_nbitsset">;
//
// BUILTIN_INFO(HEXAGON.C4_nbitsclr,QI_ftype_SISI,2)
//
def int_hexagon_C4_nbitsclr :
Hexagon_qi_sisi_Intrinsic<"HEXAGON_C4_nbitsclr">;
// //
// BUILTIN_INFO(HEXAGON.C2_cmpeqi,QI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.C2_cmpeqi,QI_ftype_SISI,2)
// //
def int_hexagon_C2_cmpeqi : Hexagon_qi_sisi_Intrinsic<"HEXAGON.C2.cmpeqi">; def int_hexagon_C2_cmpeqi :
Hexagon_qi_sisi_Intrinsic<"HEXAGON_C2_cmpeqi">;
// //
// BUILTIN_INFO(HEXAGON.C2_cmpgti,QI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.C2_cmpgti,QI_ftype_SISI,2)
// //
def int_hexagon_C2_cmpgti : Hexagon_qi_sisi_Intrinsic<"HEXAGON.C2.cmpgti">; def int_hexagon_C2_cmpgti :
Hexagon_qi_sisi_Intrinsic<"HEXAGON_C2_cmpgti">;
// //
// BUILTIN_INFO(HEXAGON.C2_cmpgtui,QI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.C2_cmpgtui,QI_ftype_SISI,2)
// //
def int_hexagon_C2_cmpgtui : Hexagon_qi_sisi_Intrinsic<"HEXAGON.C2.cmpgtui" def int_hexagon_C2_cmpgtui :
>; Hexagon_qi_sisi_Intrinsic<"HEXAGON_C2_cmpgtui">;
// //
// BUILTIN_INFO(HEXAGON.C2_cmpgei,QI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.C2_cmpgei,QI_ftype_SISI,2)
// //
def int_hexagon_C2_cmpgei : Hexagon_qi_sisi_Intrinsic<"HEXAGON.C2.cmpgei">; def int_hexagon_C2_cmpgei :
Hexagon_qi_sisi_Intrinsic<"HEXAGON_C2_cmpgei">;
// //
// BUILTIN_INFO(HEXAGON.C2_cmpgeui,QI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.C2_cmpgeui,QI_ftype_SISI,2)
// //
def int_hexagon_C2_cmpgeui : Hexagon_qi_sisi_Intrinsic<"HEXAGON.C2.cmpgeui" def int_hexagon_C2_cmpgeui :
>; Hexagon_qi_sisi_Intrinsic<"HEXAGON_C2_cmpgeui">;
// //
// BUILTIN_INFO(HEXAGON.C2_cmplt,QI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.C2_cmplt,QI_ftype_SISI,2)
// //
def int_hexagon_C2_cmplt : Hexagon_qi_sisi_Intrinsic<"HEXAGON.C2.cmplt">; def int_hexagon_C2_cmplt :
Hexagon_qi_sisi_Intrinsic<"HEXAGON_C2_cmplt">;
// //
// BUILTIN_INFO(HEXAGON.C2_cmpltu,QI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.C2_cmpltu,QI_ftype_SISI,2)
// //
def int_hexagon_C2_cmpltu : Hexagon_qi_sisi_Intrinsic<"HEXAGON.C2.cmpltu">; def int_hexagon_C2_cmpltu :
Hexagon_qi_sisi_Intrinsic<"HEXAGON_C2_cmpltu">;
// //
// BUILTIN_INFO(HEXAGON.C2_bitsclri,QI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.C2_bitsclri,QI_ftype_SISI,2)
// //
def int_hexagon_C2_bitsclri : Hexagon_qi_sisi_Intrinsic<"HEXAGON.C2.bitsclr def int_hexagon_C2_bitsclri :
i">; Hexagon_qi_sisi_Intrinsic<"HEXAGON_C2_bitsclri">;
//
// BUILTIN_INFO(HEXAGON.C4_nbitsclri,QI_ftype_SISI,2)
//
def int_hexagon_C4_nbitsclri :
Hexagon_qi_sisi_Intrinsic<"HEXAGON_C4_nbitsclri">;
//
// BUILTIN_INFO(HEXAGON.C4_cmpneqi,QI_ftype_SISI,2)
//
def int_hexagon_C4_cmpneqi :
Hexagon_qi_sisi_Intrinsic<"HEXAGON_C4_cmpneqi">;
//
// BUILTIN_INFO(HEXAGON.C4_cmpltei,QI_ftype_SISI,2)
//
def int_hexagon_C4_cmpltei :
Hexagon_qi_sisi_Intrinsic<"HEXAGON_C4_cmpltei">;
//
// BUILTIN_INFO(HEXAGON.C4_cmplteui,QI_ftype_SISI,2)
//
def int_hexagon_C4_cmplteui :
Hexagon_qi_sisi_Intrinsic<"HEXAGON_C4_cmplteui">;
//
// BUILTIN_INFO(HEXAGON.C4_cmpneq,QI_ftype_SISI,2)
//
def int_hexagon_C4_cmpneq :
Hexagon_qi_sisi_Intrinsic<"HEXAGON_C4_cmpneq">;
//
// BUILTIN_INFO(HEXAGON.C4_cmplte,QI_ftype_SISI,2)
//
def int_hexagon_C4_cmplte :
Hexagon_qi_sisi_Intrinsic<"HEXAGON_C4_cmplte">;
//
// BUILTIN_INFO(HEXAGON.C4_cmplteu,QI_ftype_SISI,2)
//
def int_hexagon_C4_cmplteu :
Hexagon_qi_sisi_Intrinsic<"HEXAGON_C4_cmplteu">;
// //
// BUILTIN_INFO(HEXAGON.C2_and,QI_ftype_QIQI,2) // BUILTIN_INFO(HEXAGON.C2_and,QI_ftype_QIQI,2)
// //
def int_hexagon_C2_and : Hexagon_qi_qiqi_Intrinsic<"HEXAGON.C2.and">; def int_hexagon_C2_and :
Hexagon_qi_qiqi_Intrinsic<"HEXAGON_C2_and">;
// //
// BUILTIN_INFO(HEXAGON.C2_or,QI_ftype_QIQI,2) // BUILTIN_INFO(HEXAGON.C2_or,QI_ftype_QIQI,2)
// //
def int_hexagon_C2_or : Hexagon_qi_qiqi_Intrinsic<"HEXAGON.C2.or">; def int_hexagon_C2_or :
Hexagon_qi_qiqi_Intrinsic<"HEXAGON_C2_or">;
// //
// BUILTIN_INFO(HEXAGON.C2_xor,QI_ftype_QIQI,2) // BUILTIN_INFO(HEXAGON.C2_xor,QI_ftype_QIQI,2)
// //
def int_hexagon_C2_xor : Hexagon_qi_qiqi_Intrinsic<"HEXAGON.C2.xor">; def int_hexagon_C2_xor :
Hexagon_qi_qiqi_Intrinsic<"HEXAGON_C2_xor">;
// //
// BUILTIN_INFO(HEXAGON.C2_andn,QI_ftype_QIQI,2) // BUILTIN_INFO(HEXAGON.C2_andn,QI_ftype_QIQI,2)
// //
def int_hexagon_C2_andn : Hexagon_qi_qiqi_Intrinsic<"HEXAGON.C2.andn">; def int_hexagon_C2_andn :
Hexagon_qi_qiqi_Intrinsic<"HEXAGON_C2_andn">;
// //
// BUILTIN_INFO(HEXAGON.C2_not,QI_ftype_QI,1) // BUILTIN_INFO(HEXAGON.C2_not,QI_ftype_QI,1)
// //
def int_hexagon_C2_not : Hexagon_qi_qi_Intrinsic<"HEXAGON.C2.not">; def int_hexagon_C2_not :
Hexagon_qi_qi_Intrinsic<"HEXAGON_C2_not">;
// //
// BUILTIN_INFO(HEXAGON.C2_orn,QI_ftype_QIQI,2) // BUILTIN_INFO(HEXAGON.C2_orn,QI_ftype_QIQI,2)
// //
def int_hexagon_C2_orn : Hexagon_qi_qiqi_Intrinsic<"HEXAGON.C2.orn">; def int_hexagon_C2_orn :
Hexagon_qi_qiqi_Intrinsic<"HEXAGON_C2_orn">;
//
// BUILTIN_INFO(HEXAGON.C4_and_and,QI_ftype_QIQIQI,3)
//
def int_hexagon_C4_and_and :
Hexagon_qi_qiqiqi_Intrinsic<"HEXAGON_C4_and_and">;
//
// BUILTIN_INFO(HEXAGON.C4_and_or,QI_ftype_QIQIQI,3)
//
def int_hexagon_C4_and_or :
Hexagon_qi_qiqiqi_Intrinsic<"HEXAGON_C4_and_or">;
//
// BUILTIN_INFO(HEXAGON.C4_or_and,QI_ftype_QIQIQI,3)
//
def int_hexagon_C4_or_and :
Hexagon_qi_qiqiqi_Intrinsic<"HEXAGON_C4_or_and">;
//
// BUILTIN_INFO(HEXAGON.C4_or_or,QI_ftype_QIQIQI,3)
//
def int_hexagon_C4_or_or :
Hexagon_qi_qiqiqi_Intrinsic<"HEXAGON_C4_or_or">;
//
// BUILTIN_INFO(HEXAGON.C4_and_andn,QI_ftype_QIQIQI,3)
//
def int_hexagon_C4_and_andn :
Hexagon_qi_qiqiqi_Intrinsic<"HEXAGON_C4_and_andn">;
//
// BUILTIN_INFO(HEXAGON.C4_and_orn,QI_ftype_QIQIQI,3)
//
def int_hexagon_C4_and_orn :
Hexagon_qi_qiqiqi_Intrinsic<"HEXAGON_C4_and_orn">;
//
// BUILTIN_INFO(HEXAGON.C4_or_andn,QI_ftype_QIQIQI,3)
//
def int_hexagon_C4_or_andn :
Hexagon_qi_qiqiqi_Intrinsic<"HEXAGON_C4_or_andn">;
//
// BUILTIN_INFO(HEXAGON.C4_or_orn,QI_ftype_QIQIQI,3)
//
def int_hexagon_C4_or_orn :
Hexagon_qi_qiqiqi_Intrinsic<"HEXAGON_C4_or_orn">;
// //
// BUILTIN_INFO(HEXAGON.C2_pxfer_map,QI_ftype_QI,1) // BUILTIN_INFO(HEXAGON.C2_pxfer_map,QI_ftype_QI,1)
// //
def int_hexagon_C2_pxfer_map : Hexagon_qi_qi_Intrinsic<"HEXAGON.C2.pxfer.ma def int_hexagon_C2_pxfer_map :
p">; Hexagon_qi_qi_Intrinsic<"HEXAGON_C2_pxfer_map">;
// //
// BUILTIN_INFO(HEXAGON.C2_any8,QI_ftype_QI,1) // BUILTIN_INFO(HEXAGON.C2_any8,QI_ftype_QI,1)
// //
def int_hexagon_C2_any8 : Hexagon_qi_qi_Intrinsic<"HEXAGON.C2.any8">; def int_hexagon_C2_any8 :
Hexagon_qi_qi_Intrinsic<"HEXAGON_C2_any8">;
// //
// BUILTIN_INFO(HEXAGON.C2_all8,QI_ftype_QI,1) // BUILTIN_INFO(HEXAGON.C2_all8,QI_ftype_QI,1)
// //
def int_hexagon_C2_all8 : Hexagon_qi_qi_Intrinsic<"HEXAGON.C2.all8">; def int_hexagon_C2_all8 :
Hexagon_qi_qi_Intrinsic<"HEXAGON_C2_all8">;
// //
// BUILTIN_INFO(HEXAGON.C2_vitpack,SI_ftype_QIQI,2) // BUILTIN_INFO(HEXAGON.C2_vitpack,SI_ftype_QIQI,2)
// //
def int_hexagon_C2_vitpack : Hexagon_si_qiqi_Intrinsic<"HEXAGON.C2.vitpack" def int_hexagon_C2_vitpack :
>; Hexagon_si_qiqi_Intrinsic<"HEXAGON_C2_vitpack">;
// //
// BUILTIN_INFO(HEXAGON.C2_mux,SI_ftype_QISISI,3) // BUILTIN_INFO(HEXAGON.C2_mux,SI_ftype_QISISI,3)
// //
def int_hexagon_C2_mux : Hexagon_si_qisisi_Intrinsic<"HEXAGON.C2.mux">; def int_hexagon_C2_mux :
Hexagon_si_qisisi_Intrinsic<"HEXAGON_C2_mux">;
// //
// BUILTIN_INFO(HEXAGON.C2_muxii,SI_ftype_QISISI,3) // BUILTIN_INFO(HEXAGON.C2_muxii,SI_ftype_QISISI,3)
// //
def int_hexagon_C2_muxii : Hexagon_si_qisisi_Intrinsic<"HEXAGON.C2.muxii">; def int_hexagon_C2_muxii :
Hexagon_si_qisisi_Intrinsic<"HEXAGON_C2_muxii">;
// //
// BUILTIN_INFO(HEXAGON.C2_muxir,SI_ftype_QISISI,3) // BUILTIN_INFO(HEXAGON.C2_muxir,SI_ftype_QISISI,3)
// //
def int_hexagon_C2_muxir : Hexagon_si_qisisi_Intrinsic<"HEXAGON.C2.muxir">; def int_hexagon_C2_muxir :
Hexagon_si_qisisi_Intrinsic<"HEXAGON_C2_muxir">;
// //
// BUILTIN_INFO(HEXAGON.C2_muxri,SI_ftype_QISISI,3) // BUILTIN_INFO(HEXAGON.C2_muxri,SI_ftype_QISISI,3)
// //
def int_hexagon_C2_muxri : Hexagon_si_qisisi_Intrinsic<"HEXAGON.C2.muxri">; def int_hexagon_C2_muxri :
Hexagon_si_qisisi_Intrinsic<"HEXAGON_C2_muxri">;
// //
// BUILTIN_INFO(HEXAGON.C2_vmux,DI_ftype_QIDIDI,3) // BUILTIN_INFO(HEXAGON.C2_vmux,DI_ftype_QIDIDI,3)
// //
def int_hexagon_C2_vmux : Hexagon_di_qididi_Intrinsic<"HEXAGON.C2.vmux">; def int_hexagon_C2_vmux :
Hexagon_di_qididi_Intrinsic<"HEXAGON_C2_vmux">;
// //
// BUILTIN_INFO(HEXAGON.C2_mask,DI_ftype_QI,1) // BUILTIN_INFO(HEXAGON.C2_mask,DI_ftype_QI,1)
// //
def int_hexagon_C2_mask : Hexagon_di_qi_Intrinsic<"HEXAGON.C2.mask">; def int_hexagon_C2_mask :
Hexagon_di_qi_Intrinsic<"HEXAGON_C2_mask">;
// //
// BUILTIN_INFO(HEXAGON.A2_vcmpbeq,QI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.A2_vcmpbeq,QI_ftype_DIDI,2)
// //
def int_hexagon_A2_vcmpbeq : Hexagon_qi_didi_Intrinsic<"HEXAGON.A2.vcmpbeq" def int_hexagon_A2_vcmpbeq :
>; Hexagon_qi_didi_Intrinsic<"HEXAGON_A2_vcmpbeq">;
//
// BUILTIN_INFO(HEXAGON.A4_vcmpbeqi,QI_ftype_DISI,2)
//
def int_hexagon_A4_vcmpbeqi :
Hexagon_qi_disi_Intrinsic<"HEXAGON_A4_vcmpbeqi">;
//
// BUILTIN_INFO(HEXAGON.A4_vcmpbeq_any,QI_ftype_DIDI,2)
//
def int_hexagon_A4_vcmpbeq_any :
Hexagon_qi_didi_Intrinsic<"HEXAGON_A4_vcmpbeq_any">;
// //
// BUILTIN_INFO(HEXAGON.A2_vcmpbgtu,QI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.A2_vcmpbgtu,QI_ftype_DIDI,2)
// //
def int_hexagon_A2_vcmpbgtu : Hexagon_qi_didi_Intrinsic<"HEXAGON.A2.vcmpbgt def int_hexagon_A2_vcmpbgtu :
u">; Hexagon_qi_didi_Intrinsic<"HEXAGON_A2_vcmpbgtu">;
//
// BUILTIN_INFO(HEXAGON.A4_vcmpbgtui,QI_ftype_DISI,2)
//
def int_hexagon_A4_vcmpbgtui :
Hexagon_qi_disi_Intrinsic<"HEXAGON_A4_vcmpbgtui">;
//
// BUILTIN_INFO(HEXAGON.A4_vcmpbgt,QI_ftype_DIDI,2)
//
def int_hexagon_A4_vcmpbgt :
Hexagon_qi_didi_Intrinsic<"HEXAGON_A4_vcmpbgt">;
//
// BUILTIN_INFO(HEXAGON.A4_vcmpbgti,QI_ftype_DISI,2)
//
def int_hexagon_A4_vcmpbgti :
Hexagon_qi_disi_Intrinsic<"HEXAGON_A4_vcmpbgti">;
//
// BUILTIN_INFO(HEXAGON.A4_cmpbeq,QI_ftype_SISI,2)
//
def int_hexagon_A4_cmpbeq :
Hexagon_qi_sisi_Intrinsic<"HEXAGON_A4_cmpbeq">;
//
// BUILTIN_INFO(HEXAGON.A4_cmpbeqi,QI_ftype_SISI,2)
//
def int_hexagon_A4_cmpbeqi :
Hexagon_qi_sisi_Intrinsic<"HEXAGON_A4_cmpbeqi">;
//
// BUILTIN_INFO(HEXAGON.A4_cmpbgtu,QI_ftype_SISI,2)
//
def int_hexagon_A4_cmpbgtu :
Hexagon_qi_sisi_Intrinsic<"HEXAGON_A4_cmpbgtu">;
//
// BUILTIN_INFO(HEXAGON.A4_cmpbgtui,QI_ftype_SISI,2)
//
def int_hexagon_A4_cmpbgtui :
Hexagon_qi_sisi_Intrinsic<"HEXAGON_A4_cmpbgtui">;
//
// BUILTIN_INFO(HEXAGON.A4_cmpbgt,QI_ftype_SISI,2)
//
def int_hexagon_A4_cmpbgt :
Hexagon_qi_sisi_Intrinsic<"HEXAGON_A4_cmpbgt">;
//
// BUILTIN_INFO(HEXAGON.A4_cmpbgti,QI_ftype_SISI,2)
//
def int_hexagon_A4_cmpbgti :
Hexagon_qi_sisi_Intrinsic<"HEXAGON_A4_cmpbgti">;
// //
// BUILTIN_INFO(HEXAGON.A2_vcmpheq,QI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.A2_vcmpheq,QI_ftype_DIDI,2)
// //
def int_hexagon_A2_vcmpheq : Hexagon_qi_didi_Intrinsic<"HEXAGON.A2.vcmpheq" def int_hexagon_A2_vcmpheq :
>; Hexagon_qi_didi_Intrinsic<"HEXAGON_A2_vcmpheq">;
// //
// BUILTIN_INFO(HEXAGON.A2_vcmphgt,QI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.A2_vcmphgt,QI_ftype_DIDI,2)
// //
def int_hexagon_A2_vcmphgt : Hexagon_qi_didi_Intrinsic<"HEXAGON.A2.vcmphgt" def int_hexagon_A2_vcmphgt :
>; Hexagon_qi_didi_Intrinsic<"HEXAGON_A2_vcmphgt">;
// //
// BUILTIN_INFO(HEXAGON.A2_vcmphgtu,QI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.A2_vcmphgtu,QI_ftype_DIDI,2)
// //
def int_hexagon_A2_vcmphgtu : Hexagon_qi_didi_Intrinsic<"HEXAGON.A2.vcmphgt def int_hexagon_A2_vcmphgtu :
u">; Hexagon_qi_didi_Intrinsic<"HEXAGON_A2_vcmphgtu">;
//
// BUILTIN_INFO(HEXAGON.A4_vcmpheqi,QI_ftype_DISI,2)
//
def int_hexagon_A4_vcmpheqi :
Hexagon_qi_disi_Intrinsic<"HEXAGON_A4_vcmpheqi">;
//
// BUILTIN_INFO(HEXAGON.A4_vcmphgti,QI_ftype_DISI,2)
//
def int_hexagon_A4_vcmphgti :
Hexagon_qi_disi_Intrinsic<"HEXAGON_A4_vcmphgti">;
//
// BUILTIN_INFO(HEXAGON.A4_vcmphgtui,QI_ftype_DISI,2)
//
def int_hexagon_A4_vcmphgtui :
Hexagon_qi_disi_Intrinsic<"HEXAGON_A4_vcmphgtui">;
//
// BUILTIN_INFO(HEXAGON.A4_cmpheq,QI_ftype_SISI,2)
//
def int_hexagon_A4_cmpheq :
Hexagon_qi_sisi_Intrinsic<"HEXAGON_A4_cmpheq">;
//
// BUILTIN_INFO(HEXAGON.A4_cmphgt,QI_ftype_SISI,2)
//
def int_hexagon_A4_cmphgt :
Hexagon_qi_sisi_Intrinsic<"HEXAGON_A4_cmphgt">;
//
// BUILTIN_INFO(HEXAGON.A4_cmphgtu,QI_ftype_SISI,2)
//
def int_hexagon_A4_cmphgtu :
Hexagon_qi_sisi_Intrinsic<"HEXAGON_A4_cmphgtu">;
//
// BUILTIN_INFO(HEXAGON.A4_cmpheqi,QI_ftype_SISI,2)
//
def int_hexagon_A4_cmpheqi :
Hexagon_qi_sisi_Intrinsic<"HEXAGON_A4_cmpheqi">;
//
// BUILTIN_INFO(HEXAGON.A4_cmphgti,QI_ftype_SISI,2)
//
def int_hexagon_A4_cmphgti :
Hexagon_qi_sisi_Intrinsic<"HEXAGON_A4_cmphgti">;
//
// BUILTIN_INFO(HEXAGON.A4_cmphgtui,QI_ftype_SISI,2)
//
def int_hexagon_A4_cmphgtui :
Hexagon_qi_sisi_Intrinsic<"HEXAGON_A4_cmphgtui">;
// //
// BUILTIN_INFO(HEXAGON.A2_vcmpweq,QI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.A2_vcmpweq,QI_ftype_DIDI,2)
// //
def int_hexagon_A2_vcmpweq : Hexagon_qi_didi_Intrinsic<"HEXAGON.A2.vcmpweq" def int_hexagon_A2_vcmpweq :
>; Hexagon_qi_didi_Intrinsic<"HEXAGON_A2_vcmpweq">;
// //
// BUILTIN_INFO(HEXAGON.A2_vcmpwgt,QI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.A2_vcmpwgt,QI_ftype_DIDI,2)
// //
def int_hexagon_A2_vcmpwgt : Hexagon_qi_didi_Intrinsic<"HEXAGON.A2.vcmpwgt" def int_hexagon_A2_vcmpwgt :
>; Hexagon_qi_didi_Intrinsic<"HEXAGON_A2_vcmpwgt">;
// //
// BUILTIN_INFO(HEXAGON.A2_vcmpwgtu,QI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.A2_vcmpwgtu,QI_ftype_DIDI,2)
// //
def int_hexagon_A2_vcmpwgtu : Hexagon_qi_didi_Intrinsic<"HEXAGON.A2.vcmpwgt def int_hexagon_A2_vcmpwgtu :
u">; Hexagon_qi_didi_Intrinsic<"HEXAGON_A2_vcmpwgtu">;
//
// BUILTIN_INFO(HEXAGON.A4_vcmpweqi,QI_ftype_DISI,2)
//
def int_hexagon_A4_vcmpweqi :
Hexagon_qi_disi_Intrinsic<"HEXAGON_A4_vcmpweqi">;
//
// BUILTIN_INFO(HEXAGON.A4_vcmpwgti,QI_ftype_DISI,2)
//
def int_hexagon_A4_vcmpwgti :
Hexagon_qi_disi_Intrinsic<"HEXAGON_A4_vcmpwgti">;
//
// BUILTIN_INFO(HEXAGON.A4_vcmpwgtui,QI_ftype_DISI,2)
//
def int_hexagon_A4_vcmpwgtui :
Hexagon_qi_disi_Intrinsic<"HEXAGON_A4_vcmpwgtui">;
//
// BUILTIN_INFO(HEXAGON.A4_boundscheck,QI_ftype_SIDI,2)
//
def int_hexagon_A4_boundscheck :
Hexagon_qi_sidi_Intrinsic<"HEXAGON_A4_boundscheck">;
//
// BUILTIN_INFO(HEXAGON.A4_tlbmatch,QI_ftype_DISI,2)
//
def int_hexagon_A4_tlbmatch :
Hexagon_qi_disi_Intrinsic<"HEXAGON_A4_tlbmatch">;
// //
// BUILTIN_INFO(HEXAGON.C2_tfrpr,SI_ftype_QI,1) // BUILTIN_INFO(HEXAGON.C2_tfrpr,SI_ftype_QI,1)
// //
def int_hexagon_C2_tfrpr : Hexagon_si_qi_Intrinsic<"HEXAGON.C2.tfrpr">; def int_hexagon_C2_tfrpr :
Hexagon_si_qi_Intrinsic<"HEXAGON_C2_tfrpr">;
// //
// BUILTIN_INFO(HEXAGON.C2_tfrrp,QI_ftype_SI,1) // BUILTIN_INFO(HEXAGON.C2_tfrrp,QI_ftype_SI,1)
// //
def int_hexagon_C2_tfrrp : Hexagon_qi_si_Intrinsic<"HEXAGON.C2.tfrrp">; def int_hexagon_C2_tfrrp :
Hexagon_qi_si_Intrinsic<"HEXAGON_C2_tfrrp">;
//
// BUILTIN_INFO(HEXAGON.C4_fastcorner9,QI_ftype_QIQI,2)
//
def int_hexagon_C4_fastcorner9 :
Hexagon_qi_qiqi_Intrinsic<"HEXAGON_C4_fastcorner9">;
//
// BUILTIN_INFO(HEXAGON.C4_fastcorner9_not,QI_ftype_QIQI,2)
//
def int_hexagon_C4_fastcorner9_not :
Hexagon_qi_qiqi_Intrinsic<"HEXAGON_C4_fastcorner9_not">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpy_acc_hh_s0,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpy_acc_hh_s0,SI_ftype_SISISI,3)
// //
def int_hexagon_M2_mpy_acc_hh_s0 : def int_hexagon_M2_mpy_acc_hh_s0 :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.M2.mpy.acc.hh.s0">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_acc_hh_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpy_acc_hh_s1,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpy_acc_hh_s1,SI_ftype_SISISI,3)
// //
def int_hexagon_M2_mpy_acc_hh_s1 : def int_hexagon_M2_mpy_acc_hh_s1 :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.M2.mpy.acc.hh.s1">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_acc_hh_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpy_acc_hl_s0,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpy_acc_hl_s0,SI_ftype_SISISI,3)
// //
def int_hexagon_M2_mpy_acc_hl_s0 : def int_hexagon_M2_mpy_acc_hl_s0 :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.M2.mpy.acc.hl.s0">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_acc_hl_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpy_acc_hl_s1,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpy_acc_hl_s1,SI_ftype_SISISI,3)
// //
def int_hexagon_M2_mpy_acc_hl_s1 : def int_hexagon_M2_mpy_acc_hl_s1 :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.M2.mpy.acc.hl.s1">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_acc_hl_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpy_acc_lh_s0,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpy_acc_lh_s0,SI_ftype_SISISI,3)
// //
def int_hexagon_M2_mpy_acc_lh_s0 : def int_hexagon_M2_mpy_acc_lh_s0 :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.M2.mpy.acc.lh.s0">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_acc_lh_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpy_acc_lh_s1,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpy_acc_lh_s1,SI_ftype_SISISI,3)
// //
def int_hexagon_M2_mpy_acc_lh_s1 : def int_hexagon_M2_mpy_acc_lh_s1 :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.M2.mpy.acc.lh.s1">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_acc_lh_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpy_acc_ll_s0,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpy_acc_ll_s0,SI_ftype_SISISI,3)
// //
def int_hexagon_M2_mpy_acc_ll_s0 : def int_hexagon_M2_mpy_acc_ll_s0 :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.M2.mpy.acc.ll.s0">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_acc_ll_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpy_acc_ll_s1,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpy_acc_ll_s1,SI_ftype_SISISI,3)
// //
def int_hexagon_M2_mpy_acc_ll_s1 : def int_hexagon_M2_mpy_acc_ll_s1 :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.M2.mpy.acc.ll.s1">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_acc_ll_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpy_nac_hh_s0,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpy_nac_hh_s0,SI_ftype_SISISI,3)
// //
def int_hexagon_M2_mpy_nac_hh_s0 : def int_hexagon_M2_mpy_nac_hh_s0 :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.M2.mpy.nac.hh.s0">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_nac_hh_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpy_nac_hh_s1,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpy_nac_hh_s1,SI_ftype_SISISI,3)
// //
def int_hexagon_M2_mpy_nac_hh_s1 : def int_hexagon_M2_mpy_nac_hh_s1 :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.M2.mpy.nac.hh.s1">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_nac_hh_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpy_nac_hl_s0,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpy_nac_hl_s0,SI_ftype_SISISI,3)
// //
def int_hexagon_M2_mpy_nac_hl_s0 : def int_hexagon_M2_mpy_nac_hl_s0 :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.M2.mpy.nac.hl.s0">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_nac_hl_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpy_nac_hl_s1,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpy_nac_hl_s1,SI_ftype_SISISI,3)
// //
def int_hexagon_M2_mpy_nac_hl_s1 : def int_hexagon_M2_mpy_nac_hl_s1 :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.M2.mpy.nac.hl.s1">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_nac_hl_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpy_nac_lh_s0,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpy_nac_lh_s0,SI_ftype_SISISI,3)
// //
def int_hexagon_M2_mpy_nac_lh_s0 : def int_hexagon_M2_mpy_nac_lh_s0 :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.M2.mpy.nac.lh.s0">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_nac_lh_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpy_nac_lh_s1,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpy_nac_lh_s1,SI_ftype_SISISI,3)
// //
def int_hexagon_M2_mpy_nac_lh_s1 : def int_hexagon_M2_mpy_nac_lh_s1 :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.M2.mpy.nac.lh.s1">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_nac_lh_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpy_nac_ll_s0,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpy_nac_ll_s0,SI_ftype_SISISI,3)
// //
def int_hexagon_M2_mpy_nac_ll_s0 : def int_hexagon_M2_mpy_nac_ll_s0 :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.M2.mpy.nac.ll.s0">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_nac_ll_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpy_nac_ll_s1,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpy_nac_ll_s1,SI_ftype_SISISI,3)
// //
def int_hexagon_M2_mpy_nac_ll_s1 : def int_hexagon_M2_mpy_nac_ll_s1 :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.M2.mpy.nac.ll.s1">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_nac_ll_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpy_acc_sat_hh_s0,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpy_acc_sat_hh_s0,SI_ftype_SISISI,3)
// //
def int_hexagon_M2_mpy_acc_sat_hh_s0 : def int_hexagon_M2_mpy_acc_sat_hh_s0 :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.M2.mpy.acc.sat.hh.s0">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_acc_sat_hh_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpy_acc_sat_hh_s1,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpy_acc_sat_hh_s1,SI_ftype_SISISI,3)
// //
def int_hexagon_M2_mpy_acc_sat_hh_s1 : def int_hexagon_M2_mpy_acc_sat_hh_s1 :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.M2.mpy.acc.sat.hh.s1">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_acc_sat_hh_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpy_acc_sat_hl_s0,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpy_acc_sat_hl_s0,SI_ftype_SISISI,3)
// //
def int_hexagon_M2_mpy_acc_sat_hl_s0 : def int_hexagon_M2_mpy_acc_sat_hl_s0 :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.M2.mpy.acc.sat.hl.s0">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_acc_sat_hl_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpy_acc_sat_hl_s1,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpy_acc_sat_hl_s1,SI_ftype_SISISI,3)
// //
def int_hexagon_M2_mpy_acc_sat_hl_s1 : def int_hexagon_M2_mpy_acc_sat_hl_s1 :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.M2.mpy.acc.sat.hl.s1">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_acc_sat_hl_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpy_acc_sat_lh_s0,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpy_acc_sat_lh_s0,SI_ftype_SISISI,3)
// //
def int_hexagon_M2_mpy_acc_sat_lh_s0 : def int_hexagon_M2_mpy_acc_sat_lh_s0 :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.M2.mpy.acc.sat.lh.s0">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_acc_sat_lh_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpy_acc_sat_lh_s1,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpy_acc_sat_lh_s1,SI_ftype_SISISI,3)
// //
def int_hexagon_M2_mpy_acc_sat_lh_s1 : def int_hexagon_M2_mpy_acc_sat_lh_s1 :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.M2.mpy.acc.sat.lh.s1">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_acc_sat_lh_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpy_acc_sat_ll_s0,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpy_acc_sat_ll_s0,SI_ftype_SISISI,3)
// //
def int_hexagon_M2_mpy_acc_sat_ll_s0 : def int_hexagon_M2_mpy_acc_sat_ll_s0 :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.M2.mpy.acc.sat.ll.s0">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_acc_sat_ll_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpy_acc_sat_ll_s1,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpy_acc_sat_ll_s1,SI_ftype_SISISI,3)
// //
def int_hexagon_M2_mpy_acc_sat_ll_s1 : def int_hexagon_M2_mpy_acc_sat_ll_s1 :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.M2.mpy.acc.sat.ll.s1">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_acc_sat_ll_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpy_nac_sat_hh_s0,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpy_nac_sat_hh_s0,SI_ftype_SISISI,3)
// //
def int_hexagon_M2_mpy_nac_sat_hh_s0 : def int_hexagon_M2_mpy_nac_sat_hh_s0 :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.M2.mpy.nac.sat.hh.s0">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_nac_sat_hh_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpy_nac_sat_hh_s1,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpy_nac_sat_hh_s1,SI_ftype_SISISI,3)
// //
def int_hexagon_M2_mpy_nac_sat_hh_s1 : def int_hexagon_M2_mpy_nac_sat_hh_s1 :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.M2.mpy.nac.sat.hh.s1">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_nac_sat_hh_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpy_nac_sat_hl_s0,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpy_nac_sat_hl_s0,SI_ftype_SISISI,3)
// //
def int_hexagon_M2_mpy_nac_sat_hl_s0 : def int_hexagon_M2_mpy_nac_sat_hl_s0 :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.M2.mpy.nac.sat.hl.s0">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_nac_sat_hl_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpy_nac_sat_hl_s1,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpy_nac_sat_hl_s1,SI_ftype_SISISI,3)
// //
def int_hexagon_M2_mpy_nac_sat_hl_s1 : def int_hexagon_M2_mpy_nac_sat_hl_s1 :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.M2.mpy.nac.sat.hl.s1">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_nac_sat_hl_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpy_nac_sat_lh_s0,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpy_nac_sat_lh_s0,SI_ftype_SISISI,3)
// //
def int_hexagon_M2_mpy_nac_sat_lh_s0 : def int_hexagon_M2_mpy_nac_sat_lh_s0 :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.M2.mpy.nac.sat.lh.s0">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_nac_sat_lh_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpy_nac_sat_lh_s1,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpy_nac_sat_lh_s1,SI_ftype_SISISI,3)
// //
def int_hexagon_M2_mpy_nac_sat_lh_s1 : def int_hexagon_M2_mpy_nac_sat_lh_s1 :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.M2.mpy.nac.sat.lh.s1">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_nac_sat_lh_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpy_nac_sat_ll_s0,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpy_nac_sat_ll_s0,SI_ftype_SISISI,3)
// //
def int_hexagon_M2_mpy_nac_sat_ll_s0 : def int_hexagon_M2_mpy_nac_sat_ll_s0 :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.M2.mpy.nac.sat.ll.s0">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_nac_sat_ll_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpy_nac_sat_ll_s1,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpy_nac_sat_ll_s1,SI_ftype_SISISI,3)
// //
def int_hexagon_M2_mpy_nac_sat_ll_s1 : def int_hexagon_M2_mpy_nac_sat_ll_s1 :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.M2.mpy.nac.sat.ll.s1">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_nac_sat_ll_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpy_hh_s0,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_mpy_hh_s0,SI_ftype_SISI,2)
// //
def int_hexagon_M2_mpy_hh_s0 : def int_hexagon_M2_mpy_hh_s0 :
Hexagon_si_sisi_Intrinsic<"HEXAGON.M2.mpy.hh.s0">; Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_hh_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpy_hh_s1,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_mpy_hh_s1,SI_ftype_SISI,2)
// //
def int_hexagon_M2_mpy_hh_s1 : def int_hexagon_M2_mpy_hh_s1 :
Hexagon_si_sisi_Intrinsic<"HEXAGON.M2.mpy.hh.s1">; Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_hh_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpy_hl_s0,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_mpy_hl_s0,SI_ftype_SISI,2)
// //
def int_hexagon_M2_mpy_hl_s0 : def int_hexagon_M2_mpy_hl_s0 :
Hexagon_si_sisi_Intrinsic<"HEXAGON.M2.mpy.hl.s0">; Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_hl_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpy_hl_s1,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_mpy_hl_s1,SI_ftype_SISI,2)
// //
def int_hexagon_M2_mpy_hl_s1 : def int_hexagon_M2_mpy_hl_s1 :
Hexagon_si_sisi_Intrinsic<"HEXAGON.M2.mpy.hl.s1">; Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_hl_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpy_lh_s0,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_mpy_lh_s0,SI_ftype_SISI,2)
// //
def int_hexagon_M2_mpy_lh_s0 : def int_hexagon_M2_mpy_lh_s0 :
Hexagon_si_sisi_Intrinsic<"HEXAGON.M2.mpy.lh.s0">; Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_lh_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpy_lh_s1,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_mpy_lh_s1,SI_ftype_SISI,2)
// //
def int_hexagon_M2_mpy_lh_s1 : def int_hexagon_M2_mpy_lh_s1 :
Hexagon_si_sisi_Intrinsic<"HEXAGON.M2.mpy.lh.s1">; Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_lh_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpy_ll_s0,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_mpy_ll_s0,SI_ftype_SISI,2)
// //
def int_hexagon_M2_mpy_ll_s0 : def int_hexagon_M2_mpy_ll_s0 :
Hexagon_si_sisi_Intrinsic<"HEXAGON.M2.mpy.ll.s0">; Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_ll_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpy_ll_s1,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_mpy_ll_s1,SI_ftype_SISI,2)
// //
def int_hexagon_M2_mpy_ll_s1 : def int_hexagon_M2_mpy_ll_s1 :
Hexagon_si_sisi_Intrinsic<"HEXAGON.M2.mpy.ll.s1">; Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_ll_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpy_sat_hh_s0,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_mpy_sat_hh_s0,SI_ftype_SISI,2)
// //
def int_hexagon_M2_mpy_sat_hh_s0 : def int_hexagon_M2_mpy_sat_hh_s0 :
Hexagon_si_sisi_Intrinsic<"HEXAGON.M2.mpy.sat.hh.s0">; Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_sat_hh_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpy_sat_hh_s1,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_mpy_sat_hh_s1,SI_ftype_SISI,2)
// //
def int_hexagon_M2_mpy_sat_hh_s1 : def int_hexagon_M2_mpy_sat_hh_s1 :
Hexagon_si_sisi_Intrinsic<"HEXAGON.M2.mpy.sat.hh.s1">; Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_sat_hh_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpy_sat_hl_s0,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_mpy_sat_hl_s0,SI_ftype_SISI,2)
// //
def int_hexagon_M2_mpy_sat_hl_s0 : def int_hexagon_M2_mpy_sat_hl_s0 :
Hexagon_si_sisi_Intrinsic<"HEXAGON.M2.mpy.sat.hl.s0">; Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_sat_hl_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpy_sat_hl_s1,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_mpy_sat_hl_s1,SI_ftype_SISI,2)
// //
def int_hexagon_M2_mpy_sat_hl_s1 : def int_hexagon_M2_mpy_sat_hl_s1 :
Hexagon_si_sisi_Intrinsic<"HEXAGON.M2.mpy.sat.hl.s1">; Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_sat_hl_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpy_sat_lh_s0,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_mpy_sat_lh_s0,SI_ftype_SISI,2)
// //
def int_hexagon_M2_mpy_sat_lh_s0 : def int_hexagon_M2_mpy_sat_lh_s0 :
Hexagon_si_sisi_Intrinsic<"HEXAGON.M2.mpy.sat.lh.s0">; Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_sat_lh_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpy_sat_lh_s1,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_mpy_sat_lh_s1,SI_ftype_SISI,2)
// //
def int_hexagon_M2_mpy_sat_lh_s1 : def int_hexagon_M2_mpy_sat_lh_s1 :
Hexagon_si_sisi_Intrinsic<"HEXAGON.M2.mpy.sat.lh.s1">; Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_sat_lh_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpy_sat_ll_s0,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_mpy_sat_ll_s0,SI_ftype_SISI,2)
// //
def int_hexagon_M2_mpy_sat_ll_s0 : def int_hexagon_M2_mpy_sat_ll_s0 :
Hexagon_si_sisi_Intrinsic<"HEXAGON.M2.mpy.sat.ll.s0">; Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_sat_ll_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpy_sat_ll_s1,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_mpy_sat_ll_s1,SI_ftype_SISI,2)
// //
def int_hexagon_M2_mpy_sat_ll_s1 : def int_hexagon_M2_mpy_sat_ll_s1 :
Hexagon_si_sisi_Intrinsic<"HEXAGON.M2.mpy.sat.ll.s1">; Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_sat_ll_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpy_rnd_hh_s0,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_mpy_rnd_hh_s0,SI_ftype_SISI,2)
// //
def int_hexagon_M2_mpy_rnd_hh_s0 : def int_hexagon_M2_mpy_rnd_hh_s0 :
Hexagon_si_sisi_Intrinsic<"HEXAGON.M2.mpy.rnd.hh.s0">; Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_rnd_hh_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpy_rnd_hh_s1,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_mpy_rnd_hh_s1,SI_ftype_SISI,2)
// //
def int_hexagon_M2_mpy_rnd_hh_s1 : def int_hexagon_M2_mpy_rnd_hh_s1 :
Hexagon_si_sisi_Intrinsic<"HEXAGON.M2.mpy.rnd.hh.s1">; Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_rnd_hh_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpy_rnd_hl_s0,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_mpy_rnd_hl_s0,SI_ftype_SISI,2)
// //
def int_hexagon_M2_mpy_rnd_hl_s0 : def int_hexagon_M2_mpy_rnd_hl_s0 :
Hexagon_si_sisi_Intrinsic<"HEXAGON.M2.mpy.rnd.hl.s0">; Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_rnd_hl_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpy_rnd_hl_s1,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_mpy_rnd_hl_s1,SI_ftype_SISI,2)
// //
def int_hexagon_M2_mpy_rnd_hl_s1 : def int_hexagon_M2_mpy_rnd_hl_s1 :
Hexagon_si_sisi_Intrinsic<"HEXAGON.M2.mpy.rnd.hl.s1">; Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_rnd_hl_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpy_rnd_lh_s0,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_mpy_rnd_lh_s0,SI_ftype_SISI,2)
// //
def int_hexagon_M2_mpy_rnd_lh_s0 : def int_hexagon_M2_mpy_rnd_lh_s0 :
Hexagon_si_sisi_Intrinsic<"HEXAGON.M2.mpy.rnd.lh.s0">; Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_rnd_lh_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpy_rnd_lh_s1,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_mpy_rnd_lh_s1,SI_ftype_SISI,2)
// //
def int_hexagon_M2_mpy_rnd_lh_s1 : def int_hexagon_M2_mpy_rnd_lh_s1 :
Hexagon_si_sisi_Intrinsic<"HEXAGON.M2.mpy.rnd.lh.s1">; Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_rnd_lh_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpy_rnd_ll_s0,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_mpy_rnd_ll_s0,SI_ftype_SISI,2)
// //
def int_hexagon_M2_mpy_rnd_ll_s0 : def int_hexagon_M2_mpy_rnd_ll_s0 :
Hexagon_si_sisi_Intrinsic<"HEXAGON.M2.mpy.rnd.ll.s0">; Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_rnd_ll_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpy_rnd_ll_s1,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_mpy_rnd_ll_s1,SI_ftype_SISI,2)
// //
def int_hexagon_M2_mpy_rnd_ll_s1 : def int_hexagon_M2_mpy_rnd_ll_s1 :
Hexagon_si_sisi_Intrinsic<"HEXAGON.M2.mpy.rnd.ll.s1">; Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_rnd_ll_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpy_sat_rnd_hh_s0,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_mpy_sat_rnd_hh_s0,SI_ftype_SISI,2)
// //
def int_hexagon_M2_mpy_sat_rnd_hh_s0 : def int_hexagon_M2_mpy_sat_rnd_hh_s0 :
Hexagon_si_sisi_Intrinsic<"HEXAGON.M2.mpy.sat.rnd.hh.s0">; Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_hh_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpy_sat_rnd_hh_s1,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_mpy_sat_rnd_hh_s1,SI_ftype_SISI,2)
// //
def int_hexagon_M2_mpy_sat_rnd_hh_s1 : def int_hexagon_M2_mpy_sat_rnd_hh_s1 :
Hexagon_si_sisi_Intrinsic<"HEXAGON.M2.mpy.sat.rnd.hh.s1">; Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_hh_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpy_sat_rnd_hl_s0,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_mpy_sat_rnd_hl_s0,SI_ftype_SISI,2)
// //
def int_hexagon_M2_mpy_sat_rnd_hl_s0 : def int_hexagon_M2_mpy_sat_rnd_hl_s0 :
Hexagon_si_sisi_Intrinsic<"HEXAGON.M2.mpy.sat.rnd.hl.s0">; Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_hl_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpy_sat_rnd_hl_s1,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_mpy_sat_rnd_hl_s1,SI_ftype_SISI,2)
// //
def int_hexagon_M2_mpy_sat_rnd_hl_s1 : def int_hexagon_M2_mpy_sat_rnd_hl_s1 :
Hexagon_si_sisi_Intrinsic<"HEXAGON.M2.mpy.sat.rnd.hl.s1">; Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_hl_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpy_sat_rnd_lh_s0,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_mpy_sat_rnd_lh_s0,SI_ftype_SISI,2)
// //
def int_hexagon_M2_mpy_sat_rnd_lh_s0 : def int_hexagon_M2_mpy_sat_rnd_lh_s0 :
Hexagon_si_sisi_Intrinsic<"HEXAGON.M2.mpy.sat.rnd.lh.s0">; Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_lh_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpy_sat_rnd_lh_s1,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_mpy_sat_rnd_lh_s1,SI_ftype_SISI,2)
// //
def int_hexagon_M2_mpy_sat_rnd_lh_s1 : def int_hexagon_M2_mpy_sat_rnd_lh_s1 :
Hexagon_si_sisi_Intrinsic<"HEXAGON.M2.mpy.sat.rnd.lh.s1">; Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_lh_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpy_sat_rnd_ll_s0,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_mpy_sat_rnd_ll_s0,SI_ftype_SISI,2)
// //
def int_hexagon_M2_mpy_sat_rnd_ll_s0 : def int_hexagon_M2_mpy_sat_rnd_ll_s0 :
Hexagon_si_sisi_Intrinsic<"HEXAGON.M2.mpy.sat.rnd.ll.s0">; Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_ll_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpy_sat_rnd_ll_s1,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_mpy_sat_rnd_ll_s1,SI_ftype_SISI,2)
// //
def int_hexagon_M2_mpy_sat_rnd_ll_s1 : def int_hexagon_M2_mpy_sat_rnd_ll_s1 :
Hexagon_si_sisi_Intrinsic<"HEXAGON.M2.mpy.sat.rnd.ll.s1">; Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_ll_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyd_acc_hh_s0,DI_ftype_DISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpyd_acc_hh_s0,DI_ftype_DISISI,3)
// //
def int_hexagon_M2_mpyd_acc_hh_s0 : def int_hexagon_M2_mpyd_acc_hh_s0 :
Hexagon_di_disisi_Intrinsic<"HEXAGON.M2.mpyd.acc.hh.s0">; Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyd_acc_hh_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyd_acc_hh_s1,DI_ftype_DISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpyd_acc_hh_s1,DI_ftype_DISISI,3)
// //
def int_hexagon_M2_mpyd_acc_hh_s1 : def int_hexagon_M2_mpyd_acc_hh_s1 :
Hexagon_di_disisi_Intrinsic<"HEXAGON.M2.mpyd.acc.hh.s1">; Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyd_acc_hh_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyd_acc_hl_s0,DI_ftype_DISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpyd_acc_hl_s0,DI_ftype_DISISI,3)
// //
def int_hexagon_M2_mpyd_acc_hl_s0 : def int_hexagon_M2_mpyd_acc_hl_s0 :
Hexagon_di_disisi_Intrinsic<"HEXAGON.M2.mpyd.acc.hl.s0">; Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyd_acc_hl_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyd_acc_hl_s1,DI_ftype_DISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpyd_acc_hl_s1,DI_ftype_DISISI,3)
// //
def int_hexagon_M2_mpyd_acc_hl_s1 : def int_hexagon_M2_mpyd_acc_hl_s1 :
Hexagon_di_disisi_Intrinsic<"HEXAGON.M2.mpyd.acc.hl.s1">; Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyd_acc_hl_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyd_acc_lh_s0,DI_ftype_DISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpyd_acc_lh_s0,DI_ftype_DISISI,3)
// //
def int_hexagon_M2_mpyd_acc_lh_s0 : def int_hexagon_M2_mpyd_acc_lh_s0 :
Hexagon_di_disisi_Intrinsic<"HEXAGON.M2.mpyd.acc.lh.s0">; Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyd_acc_lh_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyd_acc_lh_s1,DI_ftype_DISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpyd_acc_lh_s1,DI_ftype_DISISI,3)
// //
def int_hexagon_M2_mpyd_acc_lh_s1 : def int_hexagon_M2_mpyd_acc_lh_s1 :
Hexagon_di_disisi_Intrinsic<"HEXAGON.M2.mpyd.acc.lh.s1">; Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyd_acc_lh_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyd_acc_ll_s0,DI_ftype_DISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpyd_acc_ll_s0,DI_ftype_DISISI,3)
// //
def int_hexagon_M2_mpyd_acc_ll_s0 : def int_hexagon_M2_mpyd_acc_ll_s0 :
Hexagon_di_disisi_Intrinsic<"HEXAGON.M2.mpyd.acc.ll.s0">; Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyd_acc_ll_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyd_acc_ll_s1,DI_ftype_DISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpyd_acc_ll_s1,DI_ftype_DISISI,3)
// //
def int_hexagon_M2_mpyd_acc_ll_s1 : def int_hexagon_M2_mpyd_acc_ll_s1 :
Hexagon_di_disisi_Intrinsic<"HEXAGON.M2.mpyd.acc.ll.s1">; Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyd_acc_ll_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyd_nac_hh_s0,DI_ftype_DISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpyd_nac_hh_s0,DI_ftype_DISISI,3)
// //
def int_hexagon_M2_mpyd_nac_hh_s0 : def int_hexagon_M2_mpyd_nac_hh_s0 :
Hexagon_di_disisi_Intrinsic<"HEXAGON.M2.mpyd.nac.hh.s0">; Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyd_nac_hh_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyd_nac_hh_s1,DI_ftype_DISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpyd_nac_hh_s1,DI_ftype_DISISI,3)
// //
def int_hexagon_M2_mpyd_nac_hh_s1 : def int_hexagon_M2_mpyd_nac_hh_s1 :
Hexagon_di_disisi_Intrinsic<"HEXAGON.M2.mpyd.nac.hh.s1">; Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyd_nac_hh_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyd_nac_hl_s0,DI_ftype_DISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpyd_nac_hl_s0,DI_ftype_DISISI,3)
// //
def int_hexagon_M2_mpyd_nac_hl_s0 : def int_hexagon_M2_mpyd_nac_hl_s0 :
Hexagon_di_disisi_Intrinsic<"HEXAGON.M2.mpyd.nac.hl.s0">; Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyd_nac_hl_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyd_nac_hl_s1,DI_ftype_DISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpyd_nac_hl_s1,DI_ftype_DISISI,3)
// //
def int_hexagon_M2_mpyd_nac_hl_s1 : def int_hexagon_M2_mpyd_nac_hl_s1 :
Hexagon_di_disisi_Intrinsic<"HEXAGON.M2.mpyd.nac.hl.s1">; Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyd_nac_hl_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyd_nac_lh_s0,DI_ftype_DISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpyd_nac_lh_s0,DI_ftype_DISISI,3)
// //
def int_hexagon_M2_mpyd_nac_lh_s0 : def int_hexagon_M2_mpyd_nac_lh_s0 :
Hexagon_di_disisi_Intrinsic<"HEXAGON.M2.mpyd.nac.lh.s0">; Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyd_nac_lh_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyd_nac_lh_s1,DI_ftype_DISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpyd_nac_lh_s1,DI_ftype_DISISI,3)
// //
def int_hexagon_M2_mpyd_nac_lh_s1 : def int_hexagon_M2_mpyd_nac_lh_s1 :
Hexagon_di_disisi_Intrinsic<"HEXAGON.M2.mpyd.nac.lh.s1">; Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyd_nac_lh_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyd_nac_ll_s0,DI_ftype_DISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpyd_nac_ll_s0,DI_ftype_DISISI,3)
// //
def int_hexagon_M2_mpyd_nac_ll_s0 : def int_hexagon_M2_mpyd_nac_ll_s0 :
Hexagon_di_disisi_Intrinsic<"HEXAGON.M2.mpyd.nac.ll.s0">; Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyd_nac_ll_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyd_nac_ll_s1,DI_ftype_DISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpyd_nac_ll_s1,DI_ftype_DISISI,3)
// //
def int_hexagon_M2_mpyd_nac_ll_s1 : def int_hexagon_M2_mpyd_nac_ll_s1 :
Hexagon_di_disisi_Intrinsic<"HEXAGON.M2.mpyd.nac.ll.s1">; Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyd_nac_ll_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyd_hh_s0,DI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_mpyd_hh_s0,DI_ftype_SISI,2)
// //
def int_hexagon_M2_mpyd_hh_s0 : def int_hexagon_M2_mpyd_hh_s0 :
Hexagon_di_sisi_Intrinsic<"HEXAGON.M2.mpyd.hh.s0">; Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyd_hh_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyd_hh_s1,DI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_mpyd_hh_s1,DI_ftype_SISI,2)
// //
def int_hexagon_M2_mpyd_hh_s1 : def int_hexagon_M2_mpyd_hh_s1 :
Hexagon_di_sisi_Intrinsic<"HEXAGON.M2.mpyd.hh.s1">; Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyd_hh_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyd_hl_s0,DI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_mpyd_hl_s0,DI_ftype_SISI,2)
// //
def int_hexagon_M2_mpyd_hl_s0 : def int_hexagon_M2_mpyd_hl_s0 :
Hexagon_di_sisi_Intrinsic<"HEXAGON.M2.mpyd.hl.s0">; Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyd_hl_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyd_hl_s1,DI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_mpyd_hl_s1,DI_ftype_SISI,2)
// //
def int_hexagon_M2_mpyd_hl_s1 : def int_hexagon_M2_mpyd_hl_s1 :
Hexagon_di_sisi_Intrinsic<"HEXAGON.M2.mpyd.hl.s1">; Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyd_hl_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyd_lh_s0,DI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_mpyd_lh_s0,DI_ftype_SISI,2)
// //
def int_hexagon_M2_mpyd_lh_s0 : def int_hexagon_M2_mpyd_lh_s0 :
Hexagon_di_sisi_Intrinsic<"HEXAGON.M2.mpyd.lh.s0">; Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyd_lh_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyd_lh_s1,DI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_mpyd_lh_s1,DI_ftype_SISI,2)
// //
def int_hexagon_M2_mpyd_lh_s1 : def int_hexagon_M2_mpyd_lh_s1 :
Hexagon_di_sisi_Intrinsic<"HEXAGON.M2.mpyd.lh.s1">; Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyd_lh_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyd_ll_s0,DI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_mpyd_ll_s0,DI_ftype_SISI,2)
// //
def int_hexagon_M2_mpyd_ll_s0 : def int_hexagon_M2_mpyd_ll_s0 :
Hexagon_di_sisi_Intrinsic<"HEXAGON.M2.mpyd.ll.s0">; Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyd_ll_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyd_ll_s1,DI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_mpyd_ll_s1,DI_ftype_SISI,2)
// //
def int_hexagon_M2_mpyd_ll_s1 : def int_hexagon_M2_mpyd_ll_s1 :
Hexagon_di_sisi_Intrinsic<"HEXAGON.M2.mpyd.ll.s1">; Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyd_ll_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyd_rnd_hh_s0,DI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_mpyd_rnd_hh_s0,DI_ftype_SISI,2)
// //
def int_hexagon_M2_mpyd_rnd_hh_s0 : def int_hexagon_M2_mpyd_rnd_hh_s0 :
Hexagon_di_sisi_Intrinsic<"HEXAGON.M2.mpyd.rnd.hh.s0">; Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyd_rnd_hh_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyd_rnd_hh_s1,DI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_mpyd_rnd_hh_s1,DI_ftype_SISI,2)
// //
def int_hexagon_M2_mpyd_rnd_hh_s1 : def int_hexagon_M2_mpyd_rnd_hh_s1 :
Hexagon_di_sisi_Intrinsic<"HEXAGON.M2.mpyd.rnd.hh.s1">; Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyd_rnd_hh_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyd_rnd_hl_s0,DI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_mpyd_rnd_hl_s0,DI_ftype_SISI,2)
// //
def int_hexagon_M2_mpyd_rnd_hl_s0 : def int_hexagon_M2_mpyd_rnd_hl_s0 :
Hexagon_di_sisi_Intrinsic<"HEXAGON.M2.mpyd.rnd.hl.s0">; Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyd_rnd_hl_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyd_rnd_hl_s1,DI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_mpyd_rnd_hl_s1,DI_ftype_SISI,2)
// //
def int_hexagon_M2_mpyd_rnd_hl_s1 : def int_hexagon_M2_mpyd_rnd_hl_s1 :
Hexagon_di_sisi_Intrinsic<"HEXAGON.M2.mpyd.rnd.hl.s1">; Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyd_rnd_hl_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyd_rnd_lh_s0,DI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_mpyd_rnd_lh_s0,DI_ftype_SISI,2)
// //
def int_hexagon_M2_mpyd_rnd_lh_s0 : def int_hexagon_M2_mpyd_rnd_lh_s0 :
Hexagon_di_sisi_Intrinsic<"HEXAGON.M2.mpyd.rnd.lh.s0">; Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyd_rnd_lh_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyd_rnd_lh_s1,DI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_mpyd_rnd_lh_s1,DI_ftype_SISI,2)
// //
def int_hexagon_M2_mpyd_rnd_lh_s1 : def int_hexagon_M2_mpyd_rnd_lh_s1 :
Hexagon_di_sisi_Intrinsic<"HEXAGON.M2.mpyd.rnd.lh.s1">; Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyd_rnd_lh_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyd_rnd_ll_s0,DI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_mpyd_rnd_ll_s0,DI_ftype_SISI,2)
// //
def int_hexagon_M2_mpyd_rnd_ll_s0 : def int_hexagon_M2_mpyd_rnd_ll_s0 :
Hexagon_di_sisi_Intrinsic<"HEXAGON.M2.mpyd.rnd.ll.s0">; Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyd_rnd_ll_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyd_rnd_ll_s1,DI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_mpyd_rnd_ll_s1,DI_ftype_SISI,2)
// //
def int_hexagon_M2_mpyd_rnd_ll_s1 : def int_hexagon_M2_mpyd_rnd_ll_s1 :
Hexagon_di_sisi_Intrinsic<"HEXAGON.M2.mpyd.rnd.ll.s1">; Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyd_rnd_ll_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyu_acc_hh_s0,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpyu_acc_hh_s0,SI_ftype_SISISI,3)
// //
def int_hexagon_M2_mpyu_acc_hh_s0 : def int_hexagon_M2_mpyu_acc_hh_s0 :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.M2.mpyu.acc.hh.s0">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpyu_acc_hh_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyu_acc_hh_s1,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpyu_acc_hh_s1,SI_ftype_SISISI,3)
// //
def int_hexagon_M2_mpyu_acc_hh_s1 : def int_hexagon_M2_mpyu_acc_hh_s1 :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.M2.mpyu.acc.hh.s1">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpyu_acc_hh_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyu_acc_hl_s0,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpyu_acc_hl_s0,SI_ftype_SISISI,3)
// //
def int_hexagon_M2_mpyu_acc_hl_s0 : def int_hexagon_M2_mpyu_acc_hl_s0 :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.M2.mpyu.acc.hl.s0">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpyu_acc_hl_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyu_acc_hl_s1,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpyu_acc_hl_s1,SI_ftype_SISISI,3)
// //
def int_hexagon_M2_mpyu_acc_hl_s1 : def int_hexagon_M2_mpyu_acc_hl_s1 :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.M2.mpyu.acc.hl.s1">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpyu_acc_hl_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyu_acc_lh_s0,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpyu_acc_lh_s0,SI_ftype_SISISI,3)
// //
def int_hexagon_M2_mpyu_acc_lh_s0 : def int_hexagon_M2_mpyu_acc_lh_s0 :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.M2.mpyu.acc.lh.s0">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpyu_acc_lh_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyu_acc_lh_s1,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpyu_acc_lh_s1,SI_ftype_SISISI,3)
// //
def int_hexagon_M2_mpyu_acc_lh_s1 : def int_hexagon_M2_mpyu_acc_lh_s1 :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.M2.mpyu.acc.lh.s1">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpyu_acc_lh_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyu_acc_ll_s0,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpyu_acc_ll_s0,SI_ftype_SISISI,3)
// //
def int_hexagon_M2_mpyu_acc_ll_s0 : def int_hexagon_M2_mpyu_acc_ll_s0 :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.M2.mpyu.acc.ll.s0">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpyu_acc_ll_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyu_acc_ll_s1,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpyu_acc_ll_s1,SI_ftype_SISISI,3)
// //
def int_hexagon_M2_mpyu_acc_ll_s1 : def int_hexagon_M2_mpyu_acc_ll_s1 :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.M2.mpyu.acc.ll.s1">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpyu_acc_ll_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyu_nac_hh_s0,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpyu_nac_hh_s0,SI_ftype_SISISI,3)
// //
def int_hexagon_M2_mpyu_nac_hh_s0 : def int_hexagon_M2_mpyu_nac_hh_s0 :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.M2.mpyu.nac.hh.s0">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpyu_nac_hh_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyu_nac_hh_s1,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpyu_nac_hh_s1,SI_ftype_SISISI,3)
// //
def int_hexagon_M2_mpyu_nac_hh_s1 : def int_hexagon_M2_mpyu_nac_hh_s1 :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.M2.mpyu.nac.hh.s1">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpyu_nac_hh_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyu_nac_hl_s0,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpyu_nac_hl_s0,SI_ftype_SISISI,3)
// //
def int_hexagon_M2_mpyu_nac_hl_s0 : def int_hexagon_M2_mpyu_nac_hl_s0 :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.M2.mpyu.nac.hl.s0">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpyu_nac_hl_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyu_nac_hl_s1,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpyu_nac_hl_s1,SI_ftype_SISISI,3)
// //
def int_hexagon_M2_mpyu_nac_hl_s1 : def int_hexagon_M2_mpyu_nac_hl_s1 :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.M2.mpyu.nac.hl.s1">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpyu_nac_hl_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyu_nac_lh_s0,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpyu_nac_lh_s0,SI_ftype_SISISI,3)
// //
def int_hexagon_M2_mpyu_nac_lh_s0 : def int_hexagon_M2_mpyu_nac_lh_s0 :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.M2.mpyu.nac.lh.s0">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpyu_nac_lh_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyu_nac_lh_s1,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpyu_nac_lh_s1,SI_ftype_SISISI,3)
// //
def int_hexagon_M2_mpyu_nac_lh_s1 : def int_hexagon_M2_mpyu_nac_lh_s1 :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.M2.mpyu.nac.lh.s1">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpyu_nac_lh_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyu_nac_ll_s0,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpyu_nac_ll_s0,SI_ftype_SISISI,3)
// //
def int_hexagon_M2_mpyu_nac_ll_s0 : def int_hexagon_M2_mpyu_nac_ll_s0 :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.M2.mpyu.nac.ll.s0">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpyu_nac_ll_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyu_nac_ll_s1,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpyu_nac_ll_s1,SI_ftype_SISISI,3)
// //
def int_hexagon_M2_mpyu_nac_ll_s1 : def int_hexagon_M2_mpyu_nac_ll_s1 :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.M2.mpyu.nac.ll.s1">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpyu_nac_ll_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyu_hh_s0,USI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_mpyu_hh_s0,USI_ftype_SISI,2)
// //
def int_hexagon_M2_mpyu_hh_s0 : def int_hexagon_M2_mpyu_hh_s0 :
Hexagon_usi_sisi_Intrinsic<"HEXAGON.M2.mpyu.hh.s0">; Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpyu_hh_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyu_hh_s1,USI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_mpyu_hh_s1,USI_ftype_SISI,2)
// //
def int_hexagon_M2_mpyu_hh_s1 : def int_hexagon_M2_mpyu_hh_s1 :
Hexagon_usi_sisi_Intrinsic<"HEXAGON.M2.mpyu.hh.s1">; Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpyu_hh_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyu_hl_s0,USI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_mpyu_hl_s0,USI_ftype_SISI,2)
// //
def int_hexagon_M2_mpyu_hl_s0 : def int_hexagon_M2_mpyu_hl_s0 :
Hexagon_usi_sisi_Intrinsic<"HEXAGON.M2.mpyu.hl.s0">; Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpyu_hl_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyu_hl_s1,USI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_mpyu_hl_s1,USI_ftype_SISI,2)
// //
def int_hexagon_M2_mpyu_hl_s1 : def int_hexagon_M2_mpyu_hl_s1 :
Hexagon_usi_sisi_Intrinsic<"HEXAGON.M2.mpyu.hl.s1">; Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpyu_hl_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyu_lh_s0,USI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_mpyu_lh_s0,USI_ftype_SISI,2)
// //
def int_hexagon_M2_mpyu_lh_s0 : def int_hexagon_M2_mpyu_lh_s0 :
Hexagon_usi_sisi_Intrinsic<"HEXAGON.M2.mpyu.lh.s0">; Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpyu_lh_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyu_lh_s1,USI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_mpyu_lh_s1,USI_ftype_SISI,2)
// //
def int_hexagon_M2_mpyu_lh_s1 : def int_hexagon_M2_mpyu_lh_s1 :
Hexagon_usi_sisi_Intrinsic<"HEXAGON.M2.mpyu.lh.s1">; Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpyu_lh_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyu_ll_s0,USI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_mpyu_ll_s0,USI_ftype_SISI,2)
// //
def int_hexagon_M2_mpyu_ll_s0 : def int_hexagon_M2_mpyu_ll_s0 :
Hexagon_usi_sisi_Intrinsic<"HEXAGON.M2.mpyu.ll.s0">; Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpyu_ll_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyu_ll_s1,USI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_mpyu_ll_s1,USI_ftype_SISI,2)
// //
def int_hexagon_M2_mpyu_ll_s1 : def int_hexagon_M2_mpyu_ll_s1 :
Hexagon_usi_sisi_Intrinsic<"HEXAGON.M2.mpyu.ll.s1">; Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpyu_ll_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyud_acc_hh_s0,DI_ftype_DISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpyud_acc_hh_s0,DI_ftype_DISISI,3)
// //
def int_hexagon_M2_mpyud_acc_hh_s0 : def int_hexagon_M2_mpyud_acc_hh_s0 :
Hexagon_di_disisi_Intrinsic<"HEXAGON.M2.mpyud.acc.hh.s0">; Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyud_acc_hh_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyud_acc_hh_s1,DI_ftype_DISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpyud_acc_hh_s1,DI_ftype_DISISI,3)
// //
def int_hexagon_M2_mpyud_acc_hh_s1 : def int_hexagon_M2_mpyud_acc_hh_s1 :
Hexagon_di_disisi_Intrinsic<"HEXAGON.M2.mpyud.acc.hh.s1">; Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyud_acc_hh_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyud_acc_hl_s0,DI_ftype_DISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpyud_acc_hl_s0,DI_ftype_DISISI,3)
// //
def int_hexagon_M2_mpyud_acc_hl_s0 : def int_hexagon_M2_mpyud_acc_hl_s0 :
Hexagon_di_disisi_Intrinsic<"HEXAGON.M2.mpyud.acc.hl.s0">; Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyud_acc_hl_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyud_acc_hl_s1,DI_ftype_DISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpyud_acc_hl_s1,DI_ftype_DISISI,3)
// //
def int_hexagon_M2_mpyud_acc_hl_s1 : def int_hexagon_M2_mpyud_acc_hl_s1 :
Hexagon_di_disisi_Intrinsic<"HEXAGON.M2.mpyud.acc.hl.s1">; Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyud_acc_hl_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyud_acc_lh_s0,DI_ftype_DISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpyud_acc_lh_s0,DI_ftype_DISISI,3)
// //
def int_hexagon_M2_mpyud_acc_lh_s0 : def int_hexagon_M2_mpyud_acc_lh_s0 :
Hexagon_di_disisi_Intrinsic<"HEXAGON.M2.mpyud.acc.lh.s0">; Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyud_acc_lh_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyud_acc_lh_s1,DI_ftype_DISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpyud_acc_lh_s1,DI_ftype_DISISI,3)
// //
def int_hexagon_M2_mpyud_acc_lh_s1 : def int_hexagon_M2_mpyud_acc_lh_s1 :
Hexagon_di_disisi_Intrinsic<"HEXAGON.M2.mpyud.acc.lh.s1">; Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyud_acc_lh_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyud_acc_ll_s0,DI_ftype_DISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpyud_acc_ll_s0,DI_ftype_DISISI,3)
// //
def int_hexagon_M2_mpyud_acc_ll_s0 : def int_hexagon_M2_mpyud_acc_ll_s0 :
Hexagon_di_disisi_Intrinsic<"HEXAGON.M2.mpyud.acc.ll.s0">; Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyud_acc_ll_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyud_acc_ll_s1,DI_ftype_DISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpyud_acc_ll_s1,DI_ftype_DISISI,3)
// //
def int_hexagon_M2_mpyud_acc_ll_s1 : def int_hexagon_M2_mpyud_acc_ll_s1 :
Hexagon_di_disisi_Intrinsic<"HEXAGON.M2.mpyud.acc.ll.s1">; Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyud_acc_ll_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyud_nac_hh_s0,DI_ftype_DISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpyud_nac_hh_s0,DI_ftype_DISISI,3)
// //
def int_hexagon_M2_mpyud_nac_hh_s0 : def int_hexagon_M2_mpyud_nac_hh_s0 :
Hexagon_di_disisi_Intrinsic<"HEXAGON.M2.mpyud.nac.hh.s0">; Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyud_nac_hh_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyud_nac_hh_s1,DI_ftype_DISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpyud_nac_hh_s1,DI_ftype_DISISI,3)
// //
def int_hexagon_M2_mpyud_nac_hh_s1 : def int_hexagon_M2_mpyud_nac_hh_s1 :
Hexagon_di_disisi_Intrinsic<"HEXAGON.M2.mpyud.nac.hh.s1">; Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyud_nac_hh_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyud_nac_hl_s0,DI_ftype_DISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpyud_nac_hl_s0,DI_ftype_DISISI,3)
// //
def int_hexagon_M2_mpyud_nac_hl_s0 : def int_hexagon_M2_mpyud_nac_hl_s0 :
Hexagon_di_disisi_Intrinsic<"HEXAGON.M2.mpyud.nac.hl.s0">; Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyud_nac_hl_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyud_nac_hl_s1,DI_ftype_DISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpyud_nac_hl_s1,DI_ftype_DISISI,3)
// //
def int_hexagon_M2_mpyud_nac_hl_s1 : def int_hexagon_M2_mpyud_nac_hl_s1 :
Hexagon_di_disisi_Intrinsic<"HEXAGON.M2.mpyud.nac.hl.s1">; Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyud_nac_hl_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyud_nac_lh_s0,DI_ftype_DISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpyud_nac_lh_s0,DI_ftype_DISISI,3)
// //
def int_hexagon_M2_mpyud_nac_lh_s0 : def int_hexagon_M2_mpyud_nac_lh_s0 :
Hexagon_di_disisi_Intrinsic<"HEXAGON.M2.mpyud.nac.lh.s0">; Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyud_nac_lh_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyud_nac_lh_s1,DI_ftype_DISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpyud_nac_lh_s1,DI_ftype_DISISI,3)
// //
def int_hexagon_M2_mpyud_nac_lh_s1 : def int_hexagon_M2_mpyud_nac_lh_s1 :
Hexagon_di_disisi_Intrinsic<"HEXAGON.M2.mpyud.nac.lh.s1">; Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyud_nac_lh_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyud_nac_ll_s0,DI_ftype_DISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpyud_nac_ll_s0,DI_ftype_DISISI,3)
// //
def int_hexagon_M2_mpyud_nac_ll_s0 : def int_hexagon_M2_mpyud_nac_ll_s0 :
Hexagon_di_disisi_Intrinsic<"HEXAGON.M2.mpyud.nac.ll.s0">; Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyud_nac_ll_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyud_nac_ll_s1,DI_ftype_DISISI,3) // BUILTIN_INFO(HEXAGON.M2_mpyud_nac_ll_s1,DI_ftype_DISISI,3)
// //
def int_hexagon_M2_mpyud_nac_ll_s1 : def int_hexagon_M2_mpyud_nac_ll_s1 :
Hexagon_di_disisi_Intrinsic<"HEXAGON.M2.mpyud.nac.ll.s1">; Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyud_nac_ll_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyud_hh_s0,UDI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_mpyud_hh_s0,UDI_ftype_SISI,2)
// //
def int_hexagon_M2_mpyud_hh_s0 : def int_hexagon_M2_mpyud_hh_s0 :
Hexagon_udi_sisi_Intrinsic<"HEXAGON.M2.mpyud.hh.s0">; Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyud_hh_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyud_hh_s1,UDI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_mpyud_hh_s1,UDI_ftype_SISI,2)
// //
def int_hexagon_M2_mpyud_hh_s1 : def int_hexagon_M2_mpyud_hh_s1 :
Hexagon_udi_sisi_Intrinsic<"HEXAGON.M2.mpyud.hh.s1">; Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyud_hh_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyud_hl_s0,UDI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_mpyud_hl_s0,UDI_ftype_SISI,2)
// //
def int_hexagon_M2_mpyud_hl_s0 : def int_hexagon_M2_mpyud_hl_s0 :
Hexagon_udi_sisi_Intrinsic<"HEXAGON.M2.mpyud.hl.s0">; Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyud_hl_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyud_hl_s1,UDI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_mpyud_hl_s1,UDI_ftype_SISI,2)
// //
def int_hexagon_M2_mpyud_hl_s1 : def int_hexagon_M2_mpyud_hl_s1 :
Hexagon_udi_sisi_Intrinsic<"HEXAGON.M2.mpyud.hl.s1">; Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyud_hl_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyud_lh_s0,UDI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_mpyud_lh_s0,UDI_ftype_SISI,2)
// //
def int_hexagon_M2_mpyud_lh_s0 : def int_hexagon_M2_mpyud_lh_s0 :
Hexagon_udi_sisi_Intrinsic<"HEXAGON.M2.mpyud.lh.s0">; Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyud_lh_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyud_lh_s1,UDI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_mpyud_lh_s1,UDI_ftype_SISI,2)
// //
def int_hexagon_M2_mpyud_lh_s1 : def int_hexagon_M2_mpyud_lh_s1 :
Hexagon_udi_sisi_Intrinsic<"HEXAGON.M2.mpyud.lh.s1">; Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyud_lh_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyud_ll_s0,UDI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_mpyud_ll_s0,UDI_ftype_SISI,2)
// //
def int_hexagon_M2_mpyud_ll_s0 : def int_hexagon_M2_mpyud_ll_s0 :
Hexagon_udi_sisi_Intrinsic<"HEXAGON.M2.mpyud.ll.s0">; Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyud_ll_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyud_ll_s1,UDI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_mpyud_ll_s1,UDI_ftype_SISI,2)
// //
def int_hexagon_M2_mpyud_ll_s1 : def int_hexagon_M2_mpyud_ll_s1 :
Hexagon_udi_sisi_Intrinsic<"HEXAGON.M2.mpyud.ll.s1">; Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyud_ll_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpysmi,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_mpysmi,SI_ftype_SISI,2)
// //
def int_hexagon_M2_mpysmi : def int_hexagon_M2_mpysmi :
Hexagon_si_sisi_Intrinsic<"HEXAGON.M2.mpysmi">; Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpysmi">;
// //
// BUILTIN_INFO(HEXAGON.M2_macsip,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.M2_macsip,SI_ftype_SISISI,3)
// //
def int_hexagon_M2_macsip : def int_hexagon_M2_macsip :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.M2.macsip">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_macsip">;
// //
// BUILTIN_INFO(HEXAGON.M2_macsin,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.M2_macsin,SI_ftype_SISISI,3)
// //
def int_hexagon_M2_macsin : def int_hexagon_M2_macsin :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.M2.macsin">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_macsin">;
// //
// BUILTIN_INFO(HEXAGON.M2_dpmpyss_s0,DI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_dpmpyss_s0,DI_ftype_SISI,2)
// //
def int_hexagon_M2_dpmpyss_s0 : def int_hexagon_M2_dpmpyss_s0 :
Hexagon_di_sisi_Intrinsic<"HEXAGON.M2.dpmpyss.s0">; Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_dpmpyss_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_dpmpyss_acc_s0,DI_ftype_DISISI,3) // BUILTIN_INFO(HEXAGON.M2_dpmpyss_acc_s0,DI_ftype_DISISI,3)
// //
def int_hexagon_M2_dpmpyss_acc_s0 : def int_hexagon_M2_dpmpyss_acc_s0 :
Hexagon_di_disisi_Intrinsic<"HEXAGON.M2.dpmpyss.acc.s0">; Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_dpmpyss_acc_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_dpmpyss_nac_s0,DI_ftype_DISISI,3) // BUILTIN_INFO(HEXAGON.M2_dpmpyss_nac_s0,DI_ftype_DISISI,3)
// //
def int_hexagon_M2_dpmpyss_nac_s0 : def int_hexagon_M2_dpmpyss_nac_s0 :
Hexagon_di_disisi_Intrinsic<"HEXAGON.M2.dpmpyss.nac.s0">; Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_dpmpyss_nac_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_dpmpyuu_s0,UDI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_dpmpyuu_s0,UDI_ftype_SISI,2)
// //
def int_hexagon_M2_dpmpyuu_s0 : def int_hexagon_M2_dpmpyuu_s0 :
Hexagon_udi_sisi_Intrinsic<"HEXAGON.M2.dpmpyuu.s0">; Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_dpmpyuu_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_dpmpyuu_acc_s0,DI_ftype_DISISI,3) // BUILTIN_INFO(HEXAGON.M2_dpmpyuu_acc_s0,DI_ftype_DISISI,3)
// //
def int_hexagon_M2_dpmpyuu_acc_s0 : def int_hexagon_M2_dpmpyuu_acc_s0 :
Hexagon_di_disisi_Intrinsic<"HEXAGON.M2.dpmpyuu.acc.s0">; Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_dpmpyuu_acc_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_dpmpyuu_nac_s0,DI_ftype_DISISI,3) // BUILTIN_INFO(HEXAGON.M2_dpmpyuu_nac_s0,DI_ftype_DISISI,3)
// //
def int_hexagon_M2_dpmpyuu_nac_s0 : def int_hexagon_M2_dpmpyuu_nac_s0 :
Hexagon_di_disisi_Intrinsic<"HEXAGON.M2.dpmpyuu.nac.s0">; Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_dpmpyuu_nac_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpy_up,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_mpy_up,SI_ftype_SISI,2)
// //
def int_hexagon_M2_mpy_up : def int_hexagon_M2_mpy_up :
Hexagon_si_sisi_Intrinsic<"HEXAGON.M2.mpy.up">; Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_up">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyu_up,USI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_mpy_up_s1,SI_ftype_SISI,2)
//
def int_hexagon_M2_mpy_up_s1 :
Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_up_s1">;
//
// BUILTIN_INFO(HEXAGON.M2_mpy_up_s1_sat,SI_ftype_SISI,2)
//
def int_hexagon_M2_mpy_up_s1_sat :
Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_up_s1_sat">;
//
// BUILTIN_INFO(HEXAGON.M2_mpyu_up,USI_ftype_SISI,2)
// //
def int_hexagon_M2_mpyu_up : def int_hexagon_M2_mpyu_up :
Hexagon_usi_sisi_Intrinsic<"HEXAGON.M2.mpyu.up">; Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpyu_up">;
//
// BUILTIN_INFO(HEXAGON.M2_mpysu_up,SI_ftype_SISI,2)
//
def int_hexagon_M2_mpysu_up :
Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpysu_up">;
// //
// BUILTIN_INFO(HEXAGON.M2_dpmpyss_rnd_s0,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_dpmpyss_rnd_s0,SI_ftype_SISI,2)
// //
def int_hexagon_M2_dpmpyss_rnd_s0 : def int_hexagon_M2_dpmpyss_rnd_s0 :
Hexagon_si_sisi_Intrinsic<"HEXAGON.M2.dpmpyss.rnd.s0">; Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_dpmpyss_rnd_s0">;
//
// BUILTIN_INFO(HEXAGON.M4_mac_up_s1_sat,SI_ftype_SISISI,3)
//
def int_hexagon_M4_mac_up_s1_sat :
Hexagon_si_sisisi_Intrinsic<"HEXAGON_M4_mac_up_s1_sat">;
//
// BUILTIN_INFO(HEXAGON.M4_nac_up_s1_sat,SI_ftype_SISISI,3)
//
def int_hexagon_M4_nac_up_s1_sat :
Hexagon_si_sisisi_Intrinsic<"HEXAGON_M4_nac_up_s1_sat">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyi,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_mpyi,SI_ftype_SISI,2)
// //
def int_hexagon_M2_mpyi : def int_hexagon_M2_mpyi :
Hexagon_si_sisi_Intrinsic<"HEXAGON.M2.mpyi">; Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpyi">;
// //
// BUILTIN_INFO(HEXAGON.M2_mpyui,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_mpyui,SI_ftype_SISI,2)
// //
def int_hexagon_M2_mpyui : def int_hexagon_M2_mpyui :
Hexagon_si_sisi_Intrinsic<"HEXAGON.M2.mpyui">; Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpyui">;
// //
// BUILTIN_INFO(HEXAGON.M2_maci,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.M2_maci,SI_ftype_SISISI,3)
// //
def int_hexagon_M2_maci : def int_hexagon_M2_maci :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.M2.maci">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_maci">;
// //
// BUILTIN_INFO(HEXAGON.M2_acci,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.M2_acci,SI_ftype_SISISI,3)
// //
def int_hexagon_M2_acci : def int_hexagon_M2_acci :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.M2.acci">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_acci">;
// //
// BUILTIN_INFO(HEXAGON.M2_accii,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.M2_accii,SI_ftype_SISISI,3)
// //
def int_hexagon_M2_accii : def int_hexagon_M2_accii :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.M2.accii">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_accii">;
// //
// BUILTIN_INFO(HEXAGON.M2_nacci,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.M2_nacci,SI_ftype_SISISI,3)
// //
def int_hexagon_M2_nacci : def int_hexagon_M2_nacci :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.M2.nacci">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_nacci">;
// //
// BUILTIN_INFO(HEXAGON.M2_naccii,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.M2_naccii,SI_ftype_SISISI,3)
// //
def int_hexagon_M2_naccii : def int_hexagon_M2_naccii :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.M2.naccii">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_naccii">;
// //
// BUILTIN_INFO(HEXAGON.M2_subacc,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.M2_subacc,SI_ftype_SISISI,3)
// //
def int_hexagon_M2_subacc : def int_hexagon_M2_subacc :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.M2.subacc">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_subacc">;
//
// BUILTIN_INFO(HEXAGON.M4_mpyrr_addr,SI_ftype_SISISI,3)
//
def int_hexagon_M4_mpyrr_addr :
Hexagon_si_sisisi_Intrinsic<"HEXAGON_M4_mpyrr_addr">;
//
// BUILTIN_INFO(HEXAGON.M4_mpyri_addr_u2,SI_ftype_SISISI,3)
//
def int_hexagon_M4_mpyri_addr_u2 :
Hexagon_si_sisisi_Intrinsic<"HEXAGON_M4_mpyri_addr_u2">;
//
// BUILTIN_INFO(HEXAGON.M4_mpyri_addr,SI_ftype_SISISI,3)
//
def int_hexagon_M4_mpyri_addr :
Hexagon_si_sisisi_Intrinsic<"HEXAGON_M4_mpyri_addr">;
//
// BUILTIN_INFO(HEXAGON.M4_mpyri_addi,SI_ftype_SISISI,3)
//
def int_hexagon_M4_mpyri_addi :
Hexagon_si_sisisi_Intrinsic<"HEXAGON_M4_mpyri_addi">;
//
// BUILTIN_INFO(HEXAGON.M4_mpyrr_addi,SI_ftype_SISISI,3)
//
def int_hexagon_M4_mpyrr_addi :
Hexagon_si_sisisi_Intrinsic<"HEXAGON_M4_mpyrr_addi">;
// //
// BUILTIN_INFO(HEXAGON.M2_vmpy2s_s0,DI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_vmpy2s_s0,DI_ftype_SISI,2)
// //
def int_hexagon_M2_vmpy2s_s0 : def int_hexagon_M2_vmpy2s_s0 :
Hexagon_di_sisi_Intrinsic<"HEXAGON.M2.vmpy2s.s0">; Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_vmpy2s_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_vmpy2s_s1,DI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_vmpy2s_s1,DI_ftype_SISI,2)
// //
def int_hexagon_M2_vmpy2s_s1 : def int_hexagon_M2_vmpy2s_s1 :
Hexagon_di_sisi_Intrinsic<"HEXAGON.M2.vmpy2s.s1">; Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_vmpy2s_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_vmac2s_s0,DI_ftype_DISISI,3) // BUILTIN_INFO(HEXAGON.M2_vmac2s_s0,DI_ftype_DISISI,3)
// //
def int_hexagon_M2_vmac2s_s0 : def int_hexagon_M2_vmac2s_s0 :
Hexagon_di_disisi_Intrinsic<"HEXAGON.M2.vmac2s.s0">; Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_vmac2s_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_vmac2s_s1,DI_ftype_DISISI,3) // BUILTIN_INFO(HEXAGON.M2_vmac2s_s1,DI_ftype_DISISI,3)
// //
def int_hexagon_M2_vmac2s_s1 : def int_hexagon_M2_vmac2s_s1 :
Hexagon_di_disisi_Intrinsic<"HEXAGON.M2.vmac2s.s1">; Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_vmac2s_s1">;
//
// BUILTIN_INFO(HEXAGON.M2_vmpy2su_s0,DI_ftype_SISI,2)
//
def int_hexagon_M2_vmpy2su_s0 :
Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_vmpy2su_s0">;
//
// BUILTIN_INFO(HEXAGON.M2_vmpy2su_s1,DI_ftype_SISI,2)
//
def int_hexagon_M2_vmpy2su_s1 :
Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_vmpy2su_s1">;
//
// BUILTIN_INFO(HEXAGON.M2_vmac2su_s0,DI_ftype_DISISI,3)
//
def int_hexagon_M2_vmac2su_s0 :
Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_vmac2su_s0">;
//
// BUILTIN_INFO(HEXAGON.M2_vmac2su_s1,DI_ftype_DISISI,3)
//
def int_hexagon_M2_vmac2su_s1 :
Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_vmac2su_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_vmpy2s_s0pack,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_vmpy2s_s0pack,SI_ftype_SISI,2)
// //
def int_hexagon_M2_vmpy2s_s0pack : def int_hexagon_M2_vmpy2s_s0pack :
Hexagon_si_sisi_Intrinsic<"HEXAGON.M2.vmpy2s.s0pack">; Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_vmpy2s_s0pack">;
// //
// BUILTIN_INFO(HEXAGON.M2_vmpy2s_s1pack,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_vmpy2s_s1pack,SI_ftype_SISI,2)
// //
def int_hexagon_M2_vmpy2s_s1pack : def int_hexagon_M2_vmpy2s_s1pack :
Hexagon_si_sisi_Intrinsic<"HEXAGON.M2.vmpy2s.s1pack">; Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_vmpy2s_s1pack">;
// //
// BUILTIN_INFO(HEXAGON.M2_vmac2,DI_ftype_DISISI,3) // BUILTIN_INFO(HEXAGON.M2_vmac2,DI_ftype_DISISI,3)
// //
def int_hexagon_M2_vmac2 : def int_hexagon_M2_vmac2 :
Hexagon_di_disisi_Intrinsic<"HEXAGON.M2.vmac2">; Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_vmac2">;
// //
// BUILTIN_INFO(HEXAGON.M2_vmpy2es_s0,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.M2_vmpy2es_s0,DI_ftype_DIDI,2)
// //
def int_hexagon_M2_vmpy2es_s0 : def int_hexagon_M2_vmpy2es_s0 :
Hexagon_di_didi_Intrinsic<"HEXAGON.M2.vmpy2es.s0">; Hexagon_di_didi_Intrinsic<"HEXAGON_M2_vmpy2es_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_vmpy2es_s1,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.M2_vmpy2es_s1,DI_ftype_DIDI,2)
// //
def int_hexagon_M2_vmpy2es_s1 : def int_hexagon_M2_vmpy2es_s1 :
Hexagon_di_didi_Intrinsic<"HEXAGON.M2.vmpy2es.s1">; Hexagon_di_didi_Intrinsic<"HEXAGON_M2_vmpy2es_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_vmac2es_s0,DI_ftype_DIDIDI,3) // BUILTIN_INFO(HEXAGON.M2_vmac2es_s0,DI_ftype_DIDIDI,3)
// //
def int_hexagon_M2_vmac2es_s0 : def int_hexagon_M2_vmac2es_s0 :
Hexagon_di_dididi_Intrinsic<"HEXAGON.M2.vmac2es.s0">; Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_vmac2es_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_vmac2es_s1,DI_ftype_DIDIDI,3) // BUILTIN_INFO(HEXAGON.M2_vmac2es_s1,DI_ftype_DIDIDI,3)
// //
def int_hexagon_M2_vmac2es_s1 : def int_hexagon_M2_vmac2es_s1 :
Hexagon_di_dididi_Intrinsic<"HEXAGON.M2.vmac2es.s1">; Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_vmac2es_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_vmac2es,DI_ftype_DIDIDI,3) // BUILTIN_INFO(HEXAGON.M2_vmac2es,DI_ftype_DIDIDI,3)
// //
def int_hexagon_M2_vmac2es : def int_hexagon_M2_vmac2es :
Hexagon_di_dididi_Intrinsic<"HEXAGON.M2.vmac2es">; Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_vmac2es">;
// //
// BUILTIN_INFO(HEXAGON.M2_vrmac_s0,DI_ftype_DIDIDI,3) // BUILTIN_INFO(HEXAGON.M2_vrmac_s0,DI_ftype_DIDIDI,3)
// //
def int_hexagon_M2_vrmac_s0 : def int_hexagon_M2_vrmac_s0 :
Hexagon_di_dididi_Intrinsic<"HEXAGON.M2.vrmac.s0">; Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_vrmac_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_vrmpy_s0,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.M2_vrmpy_s0,DI_ftype_DIDI,2)
// //
def int_hexagon_M2_vrmpy_s0 : def int_hexagon_M2_vrmpy_s0 :
Hexagon_di_didi_Intrinsic<"HEXAGON.M2.vrmpy.s0">; Hexagon_di_didi_Intrinsic<"HEXAGON_M2_vrmpy_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_vdmpyrs_s0,SI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.M2_vdmpyrs_s0,SI_ftype_DIDI,2)
// //
def int_hexagon_M2_vdmpyrs_s0 : def int_hexagon_M2_vdmpyrs_s0 :
Hexagon_si_didi_Intrinsic<"HEXAGON.M2.vdmpyrs.s0">; Hexagon_si_didi_Intrinsic<"HEXAGON_M2_vdmpyrs_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_vdmpyrs_s1,SI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.M2_vdmpyrs_s1,SI_ftype_DIDI,2)
// //
def int_hexagon_M2_vdmpyrs_s1 : def int_hexagon_M2_vdmpyrs_s1 :
Hexagon_si_didi_Intrinsic<"HEXAGON.M2.vdmpyrs.s1">; Hexagon_si_didi_Intrinsic<"HEXAGON_M2_vdmpyrs_s1">;
//
// BUILTIN_INFO(HEXAGON.M5_vrmpybuu,DI_ftype_DIDI,2)
//
def int_hexagon_M5_vrmpybuu :
Hexagon_di_didi_Intrinsic<"HEXAGON_M5_vrmpybuu">;
//
// BUILTIN_INFO(HEXAGON.M5_vrmacbuu,DI_ftype_DIDIDI,3)
//
def int_hexagon_M5_vrmacbuu :
Hexagon_di_dididi_Intrinsic<"HEXAGON_M5_vrmacbuu">;
//
// BUILTIN_INFO(HEXAGON.M5_vrmpybsu,DI_ftype_DIDI,2)
//
def int_hexagon_M5_vrmpybsu :
Hexagon_di_didi_Intrinsic<"HEXAGON_M5_vrmpybsu">;
//
// BUILTIN_INFO(HEXAGON.M5_vrmacbsu,DI_ftype_DIDIDI,3)
//
def int_hexagon_M5_vrmacbsu :
Hexagon_di_dididi_Intrinsic<"HEXAGON_M5_vrmacbsu">;
//
// BUILTIN_INFO(HEXAGON.M5_vmpybuu,DI_ftype_SISI,2)
//
def int_hexagon_M5_vmpybuu :
Hexagon_di_sisi_Intrinsic<"HEXAGON_M5_vmpybuu">;
//
// BUILTIN_INFO(HEXAGON.M5_vmpybsu,DI_ftype_SISI,2)
//
def int_hexagon_M5_vmpybsu :
Hexagon_di_sisi_Intrinsic<"HEXAGON_M5_vmpybsu">;
//
// BUILTIN_INFO(HEXAGON.M5_vmacbuu,DI_ftype_DISISI,3)
//
def int_hexagon_M5_vmacbuu :
Hexagon_di_disisi_Intrinsic<"HEXAGON_M5_vmacbuu">;
//
// BUILTIN_INFO(HEXAGON.M5_vmacbsu,DI_ftype_DISISI,3)
//
def int_hexagon_M5_vmacbsu :
Hexagon_di_disisi_Intrinsic<"HEXAGON_M5_vmacbsu">;
//
// BUILTIN_INFO(HEXAGON.M5_vdmpybsu,DI_ftype_DIDI,2)
//
def int_hexagon_M5_vdmpybsu :
Hexagon_di_didi_Intrinsic<"HEXAGON_M5_vdmpybsu">;
//
// BUILTIN_INFO(HEXAGON.M5_vdmacbsu,DI_ftype_DIDIDI,3)
//
def int_hexagon_M5_vdmacbsu :
Hexagon_di_dididi_Intrinsic<"HEXAGON_M5_vdmacbsu">;
// //
// BUILTIN_INFO(HEXAGON.M2_vdmacs_s0,DI_ftype_DIDIDI,3) // BUILTIN_INFO(HEXAGON.M2_vdmacs_s0,DI_ftype_DIDIDI,3)
// //
def int_hexagon_M2_vdmacs_s0 : def int_hexagon_M2_vdmacs_s0 :
Hexagon_di_dididi_Intrinsic<"HEXAGON.M2.vdmacs.s0">; Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_vdmacs_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_vdmacs_s1,DI_ftype_DIDIDI,3) // BUILTIN_INFO(HEXAGON.M2_vdmacs_s1,DI_ftype_DIDIDI,3)
// //
def int_hexagon_M2_vdmacs_s1 : def int_hexagon_M2_vdmacs_s1 :
Hexagon_di_dididi_Intrinsic<"HEXAGON.M2.vdmacs.s1">; Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_vdmacs_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_vdmpys_s0,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.M2_vdmpys_s0,DI_ftype_DIDI,2)
// //
def int_hexagon_M2_vdmpys_s0 : def int_hexagon_M2_vdmpys_s0 :
Hexagon_di_didi_Intrinsic<"HEXAGON.M2.vdmpys.s0">; Hexagon_di_didi_Intrinsic<"HEXAGON_M2_vdmpys_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_vdmpys_s1,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.M2_vdmpys_s1,DI_ftype_DIDI,2)
// //
def int_hexagon_M2_vdmpys_s1 : def int_hexagon_M2_vdmpys_s1 :
Hexagon_di_didi_Intrinsic<"HEXAGON.M2.vdmpys.s1">; Hexagon_di_didi_Intrinsic<"HEXAGON_M2_vdmpys_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_cmpyrs_s0,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_cmpyrs_s0,SI_ftype_SISI,2)
// //
def int_hexagon_M2_cmpyrs_s0 : def int_hexagon_M2_cmpyrs_s0 :
Hexagon_si_sisi_Intrinsic<"HEXAGON.M2.cmpyrs.s0">; Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_cmpyrs_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_cmpyrs_s1,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_cmpyrs_s1,SI_ftype_SISI,2)
// //
def int_hexagon_M2_cmpyrs_s1 : def int_hexagon_M2_cmpyrs_s1 :
Hexagon_si_sisi_Intrinsic<"HEXAGON.M2.cmpyrs.s1">; Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_cmpyrs_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_cmpyrsc_s0,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_cmpyrsc_s0,SI_ftype_SISI,2)
// //
def int_hexagon_M2_cmpyrsc_s0 : def int_hexagon_M2_cmpyrsc_s0 :
Hexagon_si_sisi_Intrinsic<"HEXAGON.M2.cmpyrsc.s0">; Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_cmpyrsc_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_cmpyrsc_s1,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_cmpyrsc_s1,SI_ftype_SISI,2)
// //
def int_hexagon_M2_cmpyrsc_s1 : def int_hexagon_M2_cmpyrsc_s1 :
Hexagon_si_sisi_Intrinsic<"HEXAGON.M2.cmpyrsc.s1">; Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_cmpyrsc_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_cmacs_s0,DI_ftype_DISISI,3) // BUILTIN_INFO(HEXAGON.M2_cmacs_s0,DI_ftype_DISISI,3)
// //
def int_hexagon_M2_cmacs_s0 : def int_hexagon_M2_cmacs_s0 :
Hexagon_di_disisi_Intrinsic<"HEXAGON.M2.cmacs.s0">; Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_cmacs_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_cmacs_s1,DI_ftype_DISISI,3) // BUILTIN_INFO(HEXAGON.M2_cmacs_s1,DI_ftype_DISISI,3)
// //
def int_hexagon_M2_cmacs_s1 : def int_hexagon_M2_cmacs_s1 :
Hexagon_di_disisi_Intrinsic<"HEXAGON.M2.cmacs.s1">; Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_cmacs_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_cmacsc_s0,DI_ftype_DISISI,3) // BUILTIN_INFO(HEXAGON.M2_cmacsc_s0,DI_ftype_DISISI,3)
// //
def int_hexagon_M2_cmacsc_s0 : def int_hexagon_M2_cmacsc_s0 :
Hexagon_di_disisi_Intrinsic<"HEXAGON.M2.cmacsc.s0">; Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_cmacsc_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_cmacsc_s1,DI_ftype_DISISI,3) // BUILTIN_INFO(HEXAGON.M2_cmacsc_s1,DI_ftype_DISISI,3)
// //
def int_hexagon_M2_cmacsc_s1 : def int_hexagon_M2_cmacsc_s1 :
Hexagon_di_disisi_Intrinsic<"HEXAGON.M2.cmacsc.s1">; Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_cmacsc_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_cmpys_s0,DI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_cmpys_s0,DI_ftype_SISI,2)
// //
def int_hexagon_M2_cmpys_s0 : def int_hexagon_M2_cmpys_s0 :
Hexagon_di_sisi_Intrinsic<"HEXAGON.M2.cmpys.s0">; Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_cmpys_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_cmpys_s1,DI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_cmpys_s1,DI_ftype_SISI,2)
// //
def int_hexagon_M2_cmpys_s1 : def int_hexagon_M2_cmpys_s1 :
Hexagon_di_sisi_Intrinsic<"HEXAGON.M2.cmpys.s1">; Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_cmpys_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_cmpysc_s0,DI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_cmpysc_s0,DI_ftype_SISI,2)
// //
def int_hexagon_M2_cmpysc_s0 : def int_hexagon_M2_cmpysc_s0 :
Hexagon_di_sisi_Intrinsic<"HEXAGON.M2.cmpysc.s0">; Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_cmpysc_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_cmpysc_s1,DI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_cmpysc_s1,DI_ftype_SISI,2)
// //
def int_hexagon_M2_cmpysc_s1 : def int_hexagon_M2_cmpysc_s1 :
Hexagon_di_sisi_Intrinsic<"HEXAGON.M2.cmpysc.s1">; Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_cmpysc_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_cnacs_s0,DI_ftype_DISISI,3) // BUILTIN_INFO(HEXAGON.M2_cnacs_s0,DI_ftype_DISISI,3)
// //
def int_hexagon_M2_cnacs_s0 : def int_hexagon_M2_cnacs_s0 :
Hexagon_di_disisi_Intrinsic<"HEXAGON.M2.cnacs.s0">; Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_cnacs_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_cnacs_s1,DI_ftype_DISISI,3) // BUILTIN_INFO(HEXAGON.M2_cnacs_s1,DI_ftype_DISISI,3)
// //
def int_hexagon_M2_cnacs_s1 : def int_hexagon_M2_cnacs_s1 :
Hexagon_di_disisi_Intrinsic<"HEXAGON.M2.cnacs.s1">; Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_cnacs_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_cnacsc_s0,DI_ftype_DISISI,3) // BUILTIN_INFO(HEXAGON.M2_cnacsc_s0,DI_ftype_DISISI,3)
// //
def int_hexagon_M2_cnacsc_s0 : def int_hexagon_M2_cnacsc_s0 :
Hexagon_di_disisi_Intrinsic<"HEXAGON.M2.cnacsc.s0">; Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_cnacsc_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_cnacsc_s1,DI_ftype_DISISI,3) // BUILTIN_INFO(HEXAGON.M2_cnacsc_s1,DI_ftype_DISISI,3)
// //
def int_hexagon_M2_cnacsc_s1 : def int_hexagon_M2_cnacsc_s1 :
Hexagon_di_disisi_Intrinsic<"HEXAGON.M2.cnacsc.s1">; Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_cnacsc_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_vrcmpys_s1,DI_ftype_DISI,2) // BUILTIN_INFO(HEXAGON.M2_vrcmpys_s1,DI_ftype_DISI,2)
// //
def int_hexagon_M2_vrcmpys_s1 : def int_hexagon_M2_vrcmpys_s1 :
Hexagon_di_disi_Intrinsic<"HEXAGON.M2.vrcmpys.s1">; Hexagon_di_disi_Intrinsic<"HEXAGON_M2_vrcmpys_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_vrcmpys_acc_s1,DI_ftype_DIDISI,3) // BUILTIN_INFO(HEXAGON.M2_vrcmpys_acc_s1,DI_ftype_DIDISI,3)
// //
def int_hexagon_M2_vrcmpys_acc_s1 : def int_hexagon_M2_vrcmpys_acc_s1 :
Hexagon_di_didisi_Intrinsic<"HEXAGON.M2.vrcmpys.acc.s1">; Hexagon_di_didisi_Intrinsic<"HEXAGON_M2_vrcmpys_acc_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_vrcmpys_s1rp,SI_ftype_DISI,2) // BUILTIN_INFO(HEXAGON.M2_vrcmpys_s1rp,SI_ftype_DISI,2)
// //
def int_hexagon_M2_vrcmpys_s1rp : def int_hexagon_M2_vrcmpys_s1rp :
Hexagon_si_disi_Intrinsic<"HEXAGON.M2.vrcmpys.s1rp">; Hexagon_si_disi_Intrinsic<"HEXAGON_M2_vrcmpys_s1rp">;
// //
// BUILTIN_INFO(HEXAGON.M2_mmacls_s0,DI_ftype_DIDIDI,3) // BUILTIN_INFO(HEXAGON.M2_mmacls_s0,DI_ftype_DIDIDI,3)
// //
def int_hexagon_M2_mmacls_s0 : def int_hexagon_M2_mmacls_s0 :
Hexagon_di_dididi_Intrinsic<"HEXAGON.M2.mmacls.s0">; Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_mmacls_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mmacls_s1,DI_ftype_DIDIDI,3) // BUILTIN_INFO(HEXAGON.M2_mmacls_s1,DI_ftype_DIDIDI,3)
// //
def int_hexagon_M2_mmacls_s1 : def int_hexagon_M2_mmacls_s1 :
Hexagon_di_dididi_Intrinsic<"HEXAGON.M2.mmacls.s1">; Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_mmacls_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mmachs_s0,DI_ftype_DIDIDI,3) // BUILTIN_INFO(HEXAGON.M2_mmachs_s0,DI_ftype_DIDIDI,3)
// //
def int_hexagon_M2_mmachs_s0 : def int_hexagon_M2_mmachs_s0 :
Hexagon_di_dididi_Intrinsic<"HEXAGON.M2.mmachs.s0">; Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_mmachs_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mmachs_s1,DI_ftype_DIDIDI,3) // BUILTIN_INFO(HEXAGON.M2_mmachs_s1,DI_ftype_DIDIDI,3)
// //
def int_hexagon_M2_mmachs_s1 : def int_hexagon_M2_mmachs_s1 :
Hexagon_di_dididi_Intrinsic<"HEXAGON.M2.mmachs.s1">; Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_mmachs_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mmpyl_s0,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.M2_mmpyl_s0,DI_ftype_DIDI,2)
// //
def int_hexagon_M2_mmpyl_s0 : def int_hexagon_M2_mmpyl_s0 :
Hexagon_di_didi_Intrinsic<"HEXAGON.M2.mmpyl.s0">; Hexagon_di_didi_Intrinsic<"HEXAGON_M2_mmpyl_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mmpyl_s1,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.M2_mmpyl_s1,DI_ftype_DIDI,2)
// //
def int_hexagon_M2_mmpyl_s1 : def int_hexagon_M2_mmpyl_s1 :
Hexagon_di_didi_Intrinsic<"HEXAGON.M2.mmpyl.s1">; Hexagon_di_didi_Intrinsic<"HEXAGON_M2_mmpyl_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mmpyh_s0,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.M2_mmpyh_s0,DI_ftype_DIDI,2)
// //
def int_hexagon_M2_mmpyh_s0 : def int_hexagon_M2_mmpyh_s0 :
Hexagon_di_didi_Intrinsic<"HEXAGON.M2.mmpyh.s0">; Hexagon_di_didi_Intrinsic<"HEXAGON_M2_mmpyh_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mmpyh_s1,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.M2_mmpyh_s1,DI_ftype_DIDI,2)
// //
def int_hexagon_M2_mmpyh_s1 : def int_hexagon_M2_mmpyh_s1 :
Hexagon_di_didi_Intrinsic<"HEXAGON.M2.mmpyh.s1">; Hexagon_di_didi_Intrinsic<"HEXAGON_M2_mmpyh_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mmacls_rs0,DI_ftype_DIDIDI,3) // BUILTIN_INFO(HEXAGON.M2_mmacls_rs0,DI_ftype_DIDIDI,3)
// //
def int_hexagon_M2_mmacls_rs0 : def int_hexagon_M2_mmacls_rs0 :
Hexagon_di_dididi_Intrinsic<"HEXAGON.M2.mmacls.rs0">; Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_mmacls_rs0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mmacls_rs1,DI_ftype_DIDIDI,3) // BUILTIN_INFO(HEXAGON.M2_mmacls_rs1,DI_ftype_DIDIDI,3)
// //
def int_hexagon_M2_mmacls_rs1 : def int_hexagon_M2_mmacls_rs1 :
Hexagon_di_dididi_Intrinsic<"HEXAGON.M2.mmacls.rs1">; Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_mmacls_rs1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mmachs_rs0,DI_ftype_DIDIDI,3) // BUILTIN_INFO(HEXAGON.M2_mmachs_rs0,DI_ftype_DIDIDI,3)
// //
def int_hexagon_M2_mmachs_rs0 : def int_hexagon_M2_mmachs_rs0 :
Hexagon_di_dididi_Intrinsic<"HEXAGON.M2.mmachs.rs0">; Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_mmachs_rs0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mmachs_rs1,DI_ftype_DIDIDI,3) // BUILTIN_INFO(HEXAGON.M2_mmachs_rs1,DI_ftype_DIDIDI,3)
// //
def int_hexagon_M2_mmachs_rs1 : def int_hexagon_M2_mmachs_rs1 :
Hexagon_di_dididi_Intrinsic<"HEXAGON.M2.mmachs.rs1">; Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_mmachs_rs1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mmpyl_rs0,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.M2_mmpyl_rs0,DI_ftype_DIDI,2)
// //
def int_hexagon_M2_mmpyl_rs0 : def int_hexagon_M2_mmpyl_rs0 :
Hexagon_di_didi_Intrinsic<"HEXAGON.M2.mmpyl.rs0">; Hexagon_di_didi_Intrinsic<"HEXAGON_M2_mmpyl_rs0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mmpyl_rs1,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.M2_mmpyl_rs1,DI_ftype_DIDI,2)
// //
def int_hexagon_M2_mmpyl_rs1 : def int_hexagon_M2_mmpyl_rs1 :
Hexagon_di_didi_Intrinsic<"HEXAGON.M2.mmpyl.rs1">; Hexagon_di_didi_Intrinsic<"HEXAGON_M2_mmpyl_rs1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mmpyh_rs0,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.M2_mmpyh_rs0,DI_ftype_DIDI,2)
// //
def int_hexagon_M2_mmpyh_rs0 : def int_hexagon_M2_mmpyh_rs0 :
Hexagon_di_didi_Intrinsic<"HEXAGON.M2.mmpyh.rs0">; Hexagon_di_didi_Intrinsic<"HEXAGON_M2_mmpyh_rs0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mmpyh_rs1,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.M2_mmpyh_rs1,DI_ftype_DIDI,2)
// //
def int_hexagon_M2_mmpyh_rs1 : def int_hexagon_M2_mmpyh_rs1 :
Hexagon_di_didi_Intrinsic<"HEXAGON.M2.mmpyh.rs1">; Hexagon_di_didi_Intrinsic<"HEXAGON_M2_mmpyh_rs1">;
//
// BUILTIN_INFO(HEXAGON.M4_vrmpyeh_s0,DI_ftype_DIDI,2)
//
def int_hexagon_M4_vrmpyeh_s0 :
Hexagon_di_didi_Intrinsic<"HEXAGON_M4_vrmpyeh_s0">;
//
// BUILTIN_INFO(HEXAGON.M4_vrmpyeh_s1,DI_ftype_DIDI,2)
//
def int_hexagon_M4_vrmpyeh_s1 :
Hexagon_di_didi_Intrinsic<"HEXAGON_M4_vrmpyeh_s1">;
//
// BUILTIN_INFO(HEXAGON.M4_vrmpyeh_acc_s0,DI_ftype_DIDIDI,3)
//
def int_hexagon_M4_vrmpyeh_acc_s0 :
Hexagon_di_dididi_Intrinsic<"HEXAGON_M4_vrmpyeh_acc_s0">;
//
// BUILTIN_INFO(HEXAGON.M4_vrmpyeh_acc_s1,DI_ftype_DIDIDI,3)
//
def int_hexagon_M4_vrmpyeh_acc_s1 :
Hexagon_di_dididi_Intrinsic<"HEXAGON_M4_vrmpyeh_acc_s1">;
//
// BUILTIN_INFO(HEXAGON.M4_vrmpyoh_s0,DI_ftype_DIDI,2)
//
def int_hexagon_M4_vrmpyoh_s0 :
Hexagon_di_didi_Intrinsic<"HEXAGON_M4_vrmpyoh_s0">;
//
// BUILTIN_INFO(HEXAGON.M4_vrmpyoh_s1,DI_ftype_DIDI,2)
//
def int_hexagon_M4_vrmpyoh_s1 :
Hexagon_di_didi_Intrinsic<"HEXAGON_M4_vrmpyoh_s1">;
//
// BUILTIN_INFO(HEXAGON.M4_vrmpyoh_acc_s0,DI_ftype_DIDIDI,3)
//
def int_hexagon_M4_vrmpyoh_acc_s0 :
Hexagon_di_dididi_Intrinsic<"HEXAGON_M4_vrmpyoh_acc_s0">;
//
// BUILTIN_INFO(HEXAGON.M4_vrmpyoh_acc_s1,DI_ftype_DIDIDI,3)
//
def int_hexagon_M4_vrmpyoh_acc_s1 :
Hexagon_di_dididi_Intrinsic<"HEXAGON_M4_vrmpyoh_acc_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_hmmpyl_rs1,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_hmmpyl_rs1,SI_ftype_SISI,2)
// //
def int_hexagon_M2_hmmpyl_rs1 : def int_hexagon_M2_hmmpyl_rs1 :
Hexagon_si_sisi_Intrinsic<"HEXAGON.M2.hmmpyl.rs1">; Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_hmmpyl_rs1">;
// //
// BUILTIN_INFO(HEXAGON.M2_hmmpyh_rs1,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_hmmpyh_rs1,SI_ftype_SISI,2)
// //
def int_hexagon_M2_hmmpyh_rs1 : def int_hexagon_M2_hmmpyh_rs1 :
Hexagon_si_sisi_Intrinsic<"HEXAGON.M2.hmmpyh.rs1">; Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_hmmpyh_rs1">;
//
// BUILTIN_INFO(HEXAGON.M2_hmmpyl_s1,SI_ftype_SISI,2)
//
def int_hexagon_M2_hmmpyl_s1 :
Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_hmmpyl_s1">;
//
// BUILTIN_INFO(HEXAGON.M2_hmmpyh_s1,SI_ftype_SISI,2)
//
def int_hexagon_M2_hmmpyh_s1 :
Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_hmmpyh_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mmaculs_s0,DI_ftype_DIDIDI,3) // BUILTIN_INFO(HEXAGON.M2_mmaculs_s0,DI_ftype_DIDIDI,3)
// //
def int_hexagon_M2_mmaculs_s0 : def int_hexagon_M2_mmaculs_s0 :
Hexagon_di_dididi_Intrinsic<"HEXAGON.M2.mmaculs.s0">; Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_mmaculs_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mmaculs_s1,DI_ftype_DIDIDI,3) // BUILTIN_INFO(HEXAGON.M2_mmaculs_s1,DI_ftype_DIDIDI,3)
// //
def int_hexagon_M2_mmaculs_s1 : def int_hexagon_M2_mmaculs_s1 :
Hexagon_di_dididi_Intrinsic<"HEXAGON.M2.mmaculs.s1">; Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_mmaculs_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mmacuhs_s0,DI_ftype_DIDIDI,3) // BUILTIN_INFO(HEXAGON.M2_mmacuhs_s0,DI_ftype_DIDIDI,3)
// //
def int_hexagon_M2_mmacuhs_s0 : def int_hexagon_M2_mmacuhs_s0 :
Hexagon_di_dididi_Intrinsic<"HEXAGON.M2.mmacuhs.s0">; Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_mmacuhs_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mmacuhs_s1,DI_ftype_DIDIDI,3) // BUILTIN_INFO(HEXAGON.M2_mmacuhs_s1,DI_ftype_DIDIDI,3)
// //
def int_hexagon_M2_mmacuhs_s1 : def int_hexagon_M2_mmacuhs_s1 :
Hexagon_di_dididi_Intrinsic<"HEXAGON.M2.mmacuhs.s1">; Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_mmacuhs_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mmpyul_s0,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.M2_mmpyul_s0,DI_ftype_DIDI,2)
// //
def int_hexagon_M2_mmpyul_s0 : def int_hexagon_M2_mmpyul_s0 :
Hexagon_di_didi_Intrinsic<"HEXAGON.M2.mmpyul.s0">; Hexagon_di_didi_Intrinsic<"HEXAGON_M2_mmpyul_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mmpyul_s1,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.M2_mmpyul_s1,DI_ftype_DIDI,2)
// //
def int_hexagon_M2_mmpyul_s1 : def int_hexagon_M2_mmpyul_s1 :
Hexagon_di_didi_Intrinsic<"HEXAGON.M2.mmpyul.s1">; Hexagon_di_didi_Intrinsic<"HEXAGON_M2_mmpyul_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mmpyuh_s0,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.M2_mmpyuh_s0,DI_ftype_DIDI,2)
// //
def int_hexagon_M2_mmpyuh_s0 : def int_hexagon_M2_mmpyuh_s0 :
Hexagon_di_didi_Intrinsic<"HEXAGON.M2.mmpyuh.s0">; Hexagon_di_didi_Intrinsic<"HEXAGON_M2_mmpyuh_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mmpyuh_s1,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.M2_mmpyuh_s1,DI_ftype_DIDI,2)
// //
def int_hexagon_M2_mmpyuh_s1 : def int_hexagon_M2_mmpyuh_s1 :
Hexagon_di_didi_Intrinsic<"HEXAGON.M2.mmpyuh.s1">; Hexagon_di_didi_Intrinsic<"HEXAGON_M2_mmpyuh_s1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mmaculs_rs0,DI_ftype_DIDIDI,3) // BUILTIN_INFO(HEXAGON.M2_mmaculs_rs0,DI_ftype_DIDIDI,3)
// //
def int_hexagon_M2_mmaculs_rs0 : def int_hexagon_M2_mmaculs_rs0 :
Hexagon_di_dididi_Intrinsic<"HEXAGON.M2.mmaculs.rs0">; Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_mmaculs_rs0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mmaculs_rs1,DI_ftype_DIDIDI,3) // BUILTIN_INFO(HEXAGON.M2_mmaculs_rs1,DI_ftype_DIDIDI,3)
// //
def int_hexagon_M2_mmaculs_rs1 : def int_hexagon_M2_mmaculs_rs1 :
Hexagon_di_dididi_Intrinsic<"HEXAGON.M2.mmaculs.rs1">; Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_mmaculs_rs1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mmacuhs_rs0,DI_ftype_DIDIDI,3) // BUILTIN_INFO(HEXAGON.M2_mmacuhs_rs0,DI_ftype_DIDIDI,3)
// //
def int_hexagon_M2_mmacuhs_rs0 : def int_hexagon_M2_mmacuhs_rs0 :
Hexagon_di_dididi_Intrinsic<"HEXAGON.M2.mmacuhs.rs0">; Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_mmacuhs_rs0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mmacuhs_rs1,DI_ftype_DIDIDI,3) // BUILTIN_INFO(HEXAGON.M2_mmacuhs_rs1,DI_ftype_DIDIDI,3)
// //
def int_hexagon_M2_mmacuhs_rs1 : def int_hexagon_M2_mmacuhs_rs1 :
Hexagon_di_dididi_Intrinsic<"HEXAGON.M2.mmacuhs.rs1">; Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_mmacuhs_rs1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mmpyul_rs0,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.M2_mmpyul_rs0,DI_ftype_DIDI,2)
// //
def int_hexagon_M2_mmpyul_rs0 : def int_hexagon_M2_mmpyul_rs0 :
Hexagon_di_didi_Intrinsic<"HEXAGON.M2.mmpyul.rs0">; Hexagon_di_didi_Intrinsic<"HEXAGON_M2_mmpyul_rs0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mmpyul_rs1,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.M2_mmpyul_rs1,DI_ftype_DIDI,2)
// //
def int_hexagon_M2_mmpyul_rs1 : def int_hexagon_M2_mmpyul_rs1 :
Hexagon_di_didi_Intrinsic<"HEXAGON.M2.mmpyul.rs1">; Hexagon_di_didi_Intrinsic<"HEXAGON_M2_mmpyul_rs1">;
// //
// BUILTIN_INFO(HEXAGON.M2_mmpyuh_rs0,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.M2_mmpyuh_rs0,DI_ftype_DIDI,2)
// //
def int_hexagon_M2_mmpyuh_rs0 : def int_hexagon_M2_mmpyuh_rs0 :
Hexagon_di_didi_Intrinsic<"HEXAGON.M2.mmpyuh.rs0">; Hexagon_di_didi_Intrinsic<"HEXAGON_M2_mmpyuh_rs0">;
// //
// BUILTIN_INFO(HEXAGON.M2_mmpyuh_rs1,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.M2_mmpyuh_rs1,DI_ftype_DIDI,2)
// //
def int_hexagon_M2_mmpyuh_rs1 : def int_hexagon_M2_mmpyuh_rs1 :
Hexagon_di_didi_Intrinsic<"HEXAGON.M2.mmpyuh.rs1">; Hexagon_di_didi_Intrinsic<"HEXAGON_M2_mmpyuh_rs1">;
// //
// BUILTIN_INFO(HEXAGON.M2_vrcmaci_s0,DI_ftype_DIDIDI,3) // BUILTIN_INFO(HEXAGON.M2_vrcmaci_s0,DI_ftype_DIDIDI,3)
// //
def int_hexagon_M2_vrcmaci_s0 : def int_hexagon_M2_vrcmaci_s0 :
Hexagon_di_dididi_Intrinsic<"HEXAGON.M2.vrcmaci.s0">; Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_vrcmaci_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_vrcmacr_s0,DI_ftype_DIDIDI,3) // BUILTIN_INFO(HEXAGON.M2_vrcmacr_s0,DI_ftype_DIDIDI,3)
// //
def int_hexagon_M2_vrcmacr_s0 : def int_hexagon_M2_vrcmacr_s0 :
Hexagon_di_dididi_Intrinsic<"HEXAGON.M2.vrcmacr.s0">; Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_vrcmacr_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_vrcmaci_s0c,DI_ftype_DIDIDI,3) // BUILTIN_INFO(HEXAGON.M2_vrcmaci_s0c,DI_ftype_DIDIDI,3)
// //
def int_hexagon_M2_vrcmaci_s0c : def int_hexagon_M2_vrcmaci_s0c :
Hexagon_di_dididi_Intrinsic<"HEXAGON.M2.vrcmaci.s0c">; Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_vrcmaci_s0c">;
// //
// BUILTIN_INFO(HEXAGON.M2_vrcmacr_s0c,DI_ftype_DIDIDI,3) // BUILTIN_INFO(HEXAGON.M2_vrcmacr_s0c,DI_ftype_DIDIDI,3)
// //
def int_hexagon_M2_vrcmacr_s0c : def int_hexagon_M2_vrcmacr_s0c :
Hexagon_di_dididi_Intrinsic<"HEXAGON.M2.vrcmacr.s0c">; Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_vrcmacr_s0c">;
// //
// BUILTIN_INFO(HEXAGON.M2_cmaci_s0,DI_ftype_DISISI,3) // BUILTIN_INFO(HEXAGON.M2_cmaci_s0,DI_ftype_DISISI,3)
// //
def int_hexagon_M2_cmaci_s0 : def int_hexagon_M2_cmaci_s0 :
Hexagon_di_disisi_Intrinsic<"HEXAGON.M2.cmaci.s0">; Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_cmaci_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_cmacr_s0,DI_ftype_DISISI,3) // BUILTIN_INFO(HEXAGON.M2_cmacr_s0,DI_ftype_DISISI,3)
// //
def int_hexagon_M2_cmacr_s0 : def int_hexagon_M2_cmacr_s0 :
Hexagon_di_disisi_Intrinsic<"HEXAGON.M2.cmacr.s0">; Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_cmacr_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_vrcmpyi_s0,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.M2_vrcmpyi_s0,DI_ftype_DIDI,2)
// //
def int_hexagon_M2_vrcmpyi_s0 : def int_hexagon_M2_vrcmpyi_s0 :
Hexagon_di_didi_Intrinsic<"HEXAGON.M2.vrcmpyi.s0">; Hexagon_di_didi_Intrinsic<"HEXAGON_M2_vrcmpyi_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_vrcmpyr_s0,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.M2_vrcmpyr_s0,DI_ftype_DIDI,2)
// //
def int_hexagon_M2_vrcmpyr_s0 : def int_hexagon_M2_vrcmpyr_s0 :
Hexagon_di_didi_Intrinsic<"HEXAGON.M2.vrcmpyr.s0">; Hexagon_di_didi_Intrinsic<"HEXAGON_M2_vrcmpyr_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_vrcmpyi_s0c,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.M2_vrcmpyi_s0c,DI_ftype_DIDI,2)
// //
def int_hexagon_M2_vrcmpyi_s0c : def int_hexagon_M2_vrcmpyi_s0c :
Hexagon_di_didi_Intrinsic<"HEXAGON.M2.vrcmpyi.s0c">; Hexagon_di_didi_Intrinsic<"HEXAGON_M2_vrcmpyi_s0c">;
// //
// BUILTIN_INFO(HEXAGON.M2_vrcmpyr_s0c,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.M2_vrcmpyr_s0c,DI_ftype_DIDI,2)
// //
def int_hexagon_M2_vrcmpyr_s0c : def int_hexagon_M2_vrcmpyr_s0c :
Hexagon_di_didi_Intrinsic<"HEXAGON.M2.vrcmpyr.s0c">; Hexagon_di_didi_Intrinsic<"HEXAGON_M2_vrcmpyr_s0c">;
// //
// BUILTIN_INFO(HEXAGON.M2_cmpyi_s0,DI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_cmpyi_s0,DI_ftype_SISI,2)
// //
def int_hexagon_M2_cmpyi_s0 : def int_hexagon_M2_cmpyi_s0 :
Hexagon_di_sisi_Intrinsic<"HEXAGON.M2.cmpyi.s0">; Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_cmpyi_s0">;
// //
// BUILTIN_INFO(HEXAGON.M2_cmpyr_s0,DI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.M2_cmpyr_s0,DI_ftype_SISI,2)
// //
def int_hexagon_M2_cmpyr_s0 : def int_hexagon_M2_cmpyr_s0 :
Hexagon_di_sisi_Intrinsic<"HEXAGON.M2.cmpyr.s0">; Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_cmpyr_s0">;
//
// BUILTIN_INFO(HEXAGON.M4_cmpyi_wh,SI_ftype_DISI,2)
//
def int_hexagon_M4_cmpyi_wh :
Hexagon_si_disi_Intrinsic<"HEXAGON_M4_cmpyi_wh">;
//
// BUILTIN_INFO(HEXAGON.M4_cmpyr_wh,SI_ftype_DISI,2)
//
def int_hexagon_M4_cmpyr_wh :
Hexagon_si_disi_Intrinsic<"HEXAGON_M4_cmpyr_wh">;
//
// BUILTIN_INFO(HEXAGON.M4_cmpyi_whc,SI_ftype_DISI,2)
//
def int_hexagon_M4_cmpyi_whc :
Hexagon_si_disi_Intrinsic<"HEXAGON_M4_cmpyi_whc">;
//
// BUILTIN_INFO(HEXAGON.M4_cmpyr_whc,SI_ftype_DISI,2)
//
def int_hexagon_M4_cmpyr_whc :
Hexagon_si_disi_Intrinsic<"HEXAGON_M4_cmpyr_whc">;
// //
// BUILTIN_INFO(HEXAGON.M2_vcmpy_s0_sat_i,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.M2_vcmpy_s0_sat_i,DI_ftype_DIDI,2)
// //
def int_hexagon_M2_vcmpy_s0_sat_i : def int_hexagon_M2_vcmpy_s0_sat_i :
Hexagon_di_didi_Intrinsic<"HEXAGON.M2.vcmpy.s0.sat.i">; Hexagon_di_didi_Intrinsic<"HEXAGON_M2_vcmpy_s0_sat_i">;
// //
// BUILTIN_INFO(HEXAGON.M2_vcmpy_s0_sat_r,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.M2_vcmpy_s0_sat_r,DI_ftype_DIDI,2)
// //
def int_hexagon_M2_vcmpy_s0_sat_r : def int_hexagon_M2_vcmpy_s0_sat_r :
Hexagon_di_didi_Intrinsic<"HEXAGON.M2.vcmpy.s0.sat.r">; Hexagon_di_didi_Intrinsic<"HEXAGON_M2_vcmpy_s0_sat_r">;
// //
// BUILTIN_INFO(HEXAGON.M2_vcmpy_s1_sat_i,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.M2_vcmpy_s1_sat_i,DI_ftype_DIDI,2)
// //
def int_hexagon_M2_vcmpy_s1_sat_i : def int_hexagon_M2_vcmpy_s1_sat_i :
Hexagon_di_didi_Intrinsic<"HEXAGON.M2.vcmpy.s1.sat.i">; Hexagon_di_didi_Intrinsic<"HEXAGON_M2_vcmpy_s1_sat_i">;
// //
// BUILTIN_INFO(HEXAGON.M2_vcmpy_s1_sat_r,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.M2_vcmpy_s1_sat_r,DI_ftype_DIDI,2)
// //
def int_hexagon_M2_vcmpy_s1_sat_r : def int_hexagon_M2_vcmpy_s1_sat_r :
Hexagon_di_didi_Intrinsic<"HEXAGON.M2.vcmpy.s1.sat.r">; Hexagon_di_didi_Intrinsic<"HEXAGON_M2_vcmpy_s1_sat_r">;
// //
// BUILTIN_INFO(HEXAGON.M2_vcmac_s0_sat_i,DI_ftype_DIDIDI,3) // BUILTIN_INFO(HEXAGON.M2_vcmac_s0_sat_i,DI_ftype_DIDIDI,3)
// //
def int_hexagon_M2_vcmac_s0_sat_i : def int_hexagon_M2_vcmac_s0_sat_i :
Hexagon_di_dididi_Intrinsic<"HEXAGON.M2.vcmac.s0.sat.i">; Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_vcmac_s0_sat_i">;
// //
// BUILTIN_INFO(HEXAGON.M2_vcmac_s0_sat_r,DI_ftype_DIDIDI,3) // BUILTIN_INFO(HEXAGON.M2_vcmac_s0_sat_r,DI_ftype_DIDIDI,3)
// //
def int_hexagon_M2_vcmac_s0_sat_r : def int_hexagon_M2_vcmac_s0_sat_r :
Hexagon_di_dididi_Intrinsic<"HEXAGON.M2.vcmac.s0.sat.r">; Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_vcmac_s0_sat_r">;
// //
// BUILTIN_INFO(HEXAGON.S2_vcrotate,DI_ftype_DISI,2) // BUILTIN_INFO(HEXAGON.S2_vcrotate,DI_ftype_DISI,2)
// //
def int_hexagon_S2_vcrotate : def int_hexagon_S2_vcrotate :
Hexagon_di_disi_Intrinsic<"HEXAGON.S2.vcrotate">; Hexagon_di_disi_Intrinsic<"HEXAGON_S2_vcrotate">;
//
// BUILTIN_INFO(HEXAGON.S4_vrcrotate_acc,DI_ftype_DIDISISI,4)
//
def int_hexagon_S4_vrcrotate_acc :
Hexagon_di_didisisi_Intrinsic<"HEXAGON_S4_vrcrotate_acc">;
//
// BUILTIN_INFO(HEXAGON.S4_vrcrotate,DI_ftype_DISISI,3)
//
def int_hexagon_S4_vrcrotate :
Hexagon_di_disisi_Intrinsic<"HEXAGON_S4_vrcrotate">;
//
// BUILTIN_INFO(HEXAGON.S2_vcnegh,DI_ftype_DISI,2)
//
def int_hexagon_S2_vcnegh :
Hexagon_di_disi_Intrinsic<"HEXAGON_S2_vcnegh">;
//
// BUILTIN_INFO(HEXAGON.S2_vrcnegh,DI_ftype_DIDISI,3)
//
def int_hexagon_S2_vrcnegh :
Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_vrcnegh">;
//
// BUILTIN_INFO(HEXAGON.M4_pmpyw,DI_ftype_SISI,2)
//
def int_hexagon_M4_pmpyw :
Hexagon_di_sisi_Intrinsic<"HEXAGON_M4_pmpyw">;
//
// BUILTIN_INFO(HEXAGON.M4_vpmpyh,DI_ftype_SISI,2)
//
def int_hexagon_M4_vpmpyh :
Hexagon_di_sisi_Intrinsic<"HEXAGON_M4_vpmpyh">;
//
// BUILTIN_INFO(HEXAGON.M4_pmpyw_acc,DI_ftype_DISISI,3)
//
def int_hexagon_M4_pmpyw_acc :
Hexagon_di_disisi_Intrinsic<"HEXAGON_M4_pmpyw_acc">;
//
// BUILTIN_INFO(HEXAGON.M4_vpmpyh_acc,DI_ftype_DISISI,3)
//
def int_hexagon_M4_vpmpyh_acc :
Hexagon_di_disisi_Intrinsic<"HEXAGON_M4_vpmpyh_acc">;
// //
// BUILTIN_INFO(HEXAGON.A2_add,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.A2_add,SI_ftype_SISI,2)
// //
def int_hexagon_A2_add : def int_hexagon_A2_add :
Hexagon_si_sisi_Intrinsic<"HEXAGON.A2.add">; Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_add">;
// //
// BUILTIN_INFO(HEXAGON.A2_sub,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.A2_sub,SI_ftype_SISI,2)
// //
def int_hexagon_A2_sub : def int_hexagon_A2_sub :
Hexagon_si_sisi_Intrinsic<"HEXAGON.A2.sub">; Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_sub">;
// //
// BUILTIN_INFO(HEXAGON.A2_addsat,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.A2_addsat,SI_ftype_SISI,2)
// //
def int_hexagon_A2_addsat : def int_hexagon_A2_addsat :
Hexagon_si_sisi_Intrinsic<"HEXAGON.A2.addsat">; Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_addsat">;
// //
// BUILTIN_INFO(HEXAGON.A2_subsat,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.A2_subsat,SI_ftype_SISI,2)
// //
def int_hexagon_A2_subsat : def int_hexagon_A2_subsat :
Hexagon_si_sisi_Intrinsic<"HEXAGON.A2.subsat">; Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_subsat">;
// //
// BUILTIN_INFO(HEXAGON.A2_addi,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.A2_addi,SI_ftype_SISI,2)
// //
def int_hexagon_A2_addi : def int_hexagon_A2_addi :
Hexagon_si_sisi_Intrinsic<"HEXAGON.A2.addi">; Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_addi">;
// //
// BUILTIN_INFO(HEXAGON.A2_addh_l16_ll,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.A2_addh_l16_ll,SI_ftype_SISI,2)
// //
def int_hexagon_A2_addh_l16_ll : def int_hexagon_A2_addh_l16_ll :
Hexagon_si_sisi_Intrinsic<"HEXAGON.A2.addh.l16.ll">; Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_addh_l16_ll">;
// //
// BUILTIN_INFO(HEXAGON.A2_addh_l16_hl,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.A2_addh_l16_hl,SI_ftype_SISI,2)
// //
def int_hexagon_A2_addh_l16_hl : def int_hexagon_A2_addh_l16_hl :
Hexagon_si_sisi_Intrinsic<"HEXAGON.A2.addh.l16.hl">; Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_addh_l16_hl">;
def int_hexagon_A2_addh_l16_lh :
Hexagon_si_sisi_Intrinsic<"HEXAGON.A2.addh.l16.lh">;
def int_hexagon_A2_addh_l16_hh :
Hexagon_si_sisi_Intrinsic<"HEXAGON.A2.addh.l16.hh">;
// //
// BUILTIN_INFO(HEXAGON.A2_addh_l16_sat_ll,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.A2_addh_l16_sat_ll,SI_ftype_SISI,2)
// //
def int_hexagon_A2_addh_l16_sat_ll : def int_hexagon_A2_addh_l16_sat_ll :
Hexagon_si_sisi_Intrinsic<"HEXAGON.A2.addh.l16.sat.ll">; Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_addh_l16_sat_ll">;
// //
// BUILTIN_INFO(HEXAGON.A2_addh_l16_sat_hl,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.A2_addh_l16_sat_hl,SI_ftype_SISI,2)
// //
def int_hexagon_A2_addh_l16_sat_hl : def int_hexagon_A2_addh_l16_sat_hl :
Hexagon_si_sisi_Intrinsic<"HEXAGON.A2.addh.l16.sat.hl">; Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_addh_l16_sat_hl">;
def int_hexagon_A2_addh_l16_sat_lh :
Hexagon_si_sisi_Intrinsic<"HEXAGON.A2.addh.l16.sat.lh">;
def int_hexagon_A2_addh_l16_sat_hh :
Hexagon_si_sisi_Intrinsic<"HEXAGON.A2.addh.l16.sat.hh">;
// //
// BUILTIN_INFO(HEXAGON.A2_subh_l16_ll,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.A2_subh_l16_ll,SI_ftype_SISI,2)
// //
def int_hexagon_A2_subh_l16_ll : def int_hexagon_A2_subh_l16_ll :
Hexagon_si_sisi_Intrinsic<"HEXAGON.A2.subh.l16.ll">; Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_subh_l16_ll">;
// //
// BUILTIN_INFO(HEXAGON.A2_subh_l16_hl,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.A2_subh_l16_hl,SI_ftype_SISI,2)
// //
def int_hexagon_A2_subh_l16_hl : def int_hexagon_A2_subh_l16_hl :
Hexagon_si_sisi_Intrinsic<"HEXAGON.A2.subh.l16.hl">; Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_subh_l16_hl">;
// //
// BUILTIN_INFO(HEXAGON.A2_subh_l16_sat_ll,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.A2_subh_l16_sat_ll,SI_ftype_SISI,2)
// //
def int_hexagon_A2_subh_l16_sat_ll : def int_hexagon_A2_subh_l16_sat_ll :
Hexagon_si_sisi_Intrinsic<"HEXAGON.A2.subh.l16.sat.ll">; Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_subh_l16_sat_ll">;
// //
// BUILTIN_INFO(HEXAGON.A2_subh_l16_sat_hl,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.A2_subh_l16_sat_hl,SI_ftype_SISI,2)
// //
def int_hexagon_A2_subh_l16_sat_hl : def int_hexagon_A2_subh_l16_sat_hl :
Hexagon_si_sisi_Intrinsic<"HEXAGON.A2.subh.l16.sat.hl">; Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_subh_l16_sat_hl">;
// //
// BUILTIN_INFO(HEXAGON.A2_addh_h16_ll,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.A2_addh_h16_ll,SI_ftype_SISI,2)
// //
def int_hexagon_A2_addh_h16_ll : def int_hexagon_A2_addh_h16_ll :
Hexagon_si_sisi_Intrinsic<"HEXAGON.A2.addh.h16.ll">; Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_addh_h16_ll">;
// //
// BUILTIN_INFO(HEXAGON.A2_addh_h16_lh,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.A2_addh_h16_lh,SI_ftype_SISI,2)
// //
def int_hexagon_A2_addh_h16_lh : def int_hexagon_A2_addh_h16_lh :
Hexagon_si_sisi_Intrinsic<"HEXAGON.A2.addh.h16.lh">; Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_addh_h16_lh">;
// //
// BUILTIN_INFO(HEXAGON.A2_addh_h16_hl,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.A2_addh_h16_hl,SI_ftype_SISI,2)
// //
def int_hexagon_A2_addh_h16_hl : def int_hexagon_A2_addh_h16_hl :
Hexagon_si_sisi_Intrinsic<"HEXAGON.A2.addh.h16.hl">; Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_addh_h16_hl">;
// //
// BUILTIN_INFO(HEXAGON.A2_addh_h16_hh,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.A2_addh_h16_hh,SI_ftype_SISI,2)
// //
def int_hexagon_A2_addh_h16_hh : def int_hexagon_A2_addh_h16_hh :
Hexagon_si_sisi_Intrinsic<"HEXAGON.A2.addh.h16.hh">; Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_addh_h16_hh">;
// //
// BUILTIN_INFO(HEXAGON.A2_addh_h16_sat_ll,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.A2_addh_h16_sat_ll,SI_ftype_SISI,2)
// //
def int_hexagon_A2_addh_h16_sat_ll : def int_hexagon_A2_addh_h16_sat_ll :
Hexagon_si_sisi_Intrinsic<"HEXAGON.A2.addh.h16.sat.ll">; Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_addh_h16_sat_ll">;
// //
// BUILTIN_INFO(HEXAGON.A2_addh_h16_sat_lh,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.A2_addh_h16_sat_lh,SI_ftype_SISI,2)
// //
def int_hexagon_A2_addh_h16_sat_lh : def int_hexagon_A2_addh_h16_sat_lh :
Hexagon_si_sisi_Intrinsic<"HEXAGON.A2.addh.h16.sat.lh">; Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_addh_h16_sat_lh">;
// //
// BUILTIN_INFO(HEXAGON.A2_addh_h16_sat_hl,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.A2_addh_h16_sat_hl,SI_ftype_SISI,2)
// //
def int_hexagon_A2_addh_h16_sat_hl : def int_hexagon_A2_addh_h16_sat_hl :
Hexagon_si_sisi_Intrinsic<"HEXAGON.A2.addh.h16.sat.hl">; Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_addh_h16_sat_hl">;
// //
// BUILTIN_INFO(HEXAGON.A2_addh_h16_sat_hh,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.A2_addh_h16_sat_hh,SI_ftype_SISI,2)
// //
def int_hexagon_A2_addh_h16_sat_hh : def int_hexagon_A2_addh_h16_sat_hh :
Hexagon_si_sisi_Intrinsic<"HEXAGON.A2.addh.h16.sat.hh">; Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_addh_h16_sat_hh">;
// //
// BUILTIN_INFO(HEXAGON.A2_subh_h16_ll,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.A2_subh_h16_ll,SI_ftype_SISI,2)
// //
def int_hexagon_A2_subh_h16_ll : def int_hexagon_A2_subh_h16_ll :
Hexagon_si_sisi_Intrinsic<"HEXAGON.A2.subh.h16.ll">; Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_subh_h16_ll">;
// //
// BUILTIN_INFO(HEXAGON.A2_subh_h16_lh,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.A2_subh_h16_lh,SI_ftype_SISI,2)
// //
def int_hexagon_A2_subh_h16_lh : def int_hexagon_A2_subh_h16_lh :
Hexagon_si_sisi_Intrinsic<"HEXAGON.A2.subh.h16.lh">; Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_subh_h16_lh">;
// //
// BUILTIN_INFO(HEXAGON.A2_subh_h16_hl,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.A2_subh_h16_hl,SI_ftype_SISI,2)
// //
def int_hexagon_A2_subh_h16_hl : def int_hexagon_A2_subh_h16_hl :
Hexagon_si_sisi_Intrinsic<"HEXAGON.A2.subh.h16.hl">; Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_subh_h16_hl">;
// //
// BUILTIN_INFO(HEXAGON.A2_subh_h16_hh,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.A2_subh_h16_hh,SI_ftype_SISI,2)
// //
def int_hexagon_A2_subh_h16_hh : def int_hexagon_A2_subh_h16_hh :
Hexagon_si_sisi_Intrinsic<"HEXAGON.A2.subh.h16.hh">; Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_subh_h16_hh">;
// //
// BUILTIN_INFO(HEXAGON.A2_subh_h16_sat_ll,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.A2_subh_h16_sat_ll,SI_ftype_SISI,2)
// //
def int_hexagon_A2_subh_h16_sat_ll : def int_hexagon_A2_subh_h16_sat_ll :
Hexagon_si_sisi_Intrinsic<"HEXAGON.A2.subh.h16.sat.ll">; Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_subh_h16_sat_ll">;
// //
// BUILTIN_INFO(HEXAGON.A2_subh_h16_sat_lh,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.A2_subh_h16_sat_lh,SI_ftype_SISI,2)
// //
def int_hexagon_A2_subh_h16_sat_lh : def int_hexagon_A2_subh_h16_sat_lh :
Hexagon_si_sisi_Intrinsic<"HEXAGON.A2.subh.h16.sat.lh">; Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_subh_h16_sat_lh">;
// //
// BUILTIN_INFO(HEXAGON.A2_subh_h16_sat_hl,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.A2_subh_h16_sat_hl,SI_ftype_SISI,2)
// //
def int_hexagon_A2_subh_h16_sat_hl : def int_hexagon_A2_subh_h16_sat_hl :
Hexagon_si_sisi_Intrinsic<"HEXAGON.A2.subh.h16.sat.hl">; Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_subh_h16_sat_hl">;
// //
// BUILTIN_INFO(HEXAGON.A2_subh_h16_sat_hh,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.A2_subh_h16_sat_hh,SI_ftype_SISI,2)
// //
def int_hexagon_A2_subh_h16_sat_hh : def int_hexagon_A2_subh_h16_sat_hh :
Hexagon_si_sisi_Intrinsic<"HEXAGON.A2.subh.h16.sat.hh">; Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_subh_h16_sat_hh">;
// //
// BUILTIN_INFO(HEXAGON.A2_aslh,SI_ftype_SI,1) // BUILTIN_INFO(HEXAGON.A2_aslh,SI_ftype_SI,1)
// //
def int_hexagon_A2_aslh : def int_hexagon_A2_aslh :
Hexagon_si_si_Intrinsic<"HEXAGON.A2.aslh">; Hexagon_si_si_Intrinsic<"HEXAGON_A2_aslh">;
// //
// BUILTIN_INFO(HEXAGON.A2_asrh,SI_ftype_SI,1) // BUILTIN_INFO(HEXAGON.A2_asrh,SI_ftype_SI,1)
// //
def int_hexagon_A2_asrh : def int_hexagon_A2_asrh :
Hexagon_si_si_Intrinsic<"HEXAGON.A2.asrh">; Hexagon_si_si_Intrinsic<"HEXAGON_A2_asrh">;
// //
// BUILTIN_INFO(HEXAGON.A2_addp,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.A2_addp,DI_ftype_DIDI,2)
// //
def int_hexagon_A2_addp : def int_hexagon_A2_addp :
Hexagon_di_didi_Intrinsic<"HEXAGON.A2.addp">; Hexagon_di_didi_Intrinsic<"HEXAGON_A2_addp">;
// //
// BUILTIN_INFO(HEXAGON.A2_addpsat,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.A2_addpsat,DI_ftype_DIDI,2)
// //
def int_hexagon_A2_addpsat : def int_hexagon_A2_addpsat :
Hexagon_di_didi_Intrinsic<"HEXAGON.A2.addpsat">; Hexagon_di_didi_Intrinsic<"HEXAGON_A2_addpsat">;
// //
// BUILTIN_INFO(HEXAGON.A2_addsp,DI_ftype_SIDI,2) // BUILTIN_INFO(HEXAGON.A2_addsp,DI_ftype_SIDI,2)
// //
def int_hexagon_A2_addsp : def int_hexagon_A2_addsp :
Hexagon_di_sidi_Intrinsic<"HEXAGON.A2.addsp">; Hexagon_di_sidi_Intrinsic<"HEXAGON_A2_addsp">;
// //
// BUILTIN_INFO(HEXAGON.A2_subp,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.A2_subp,DI_ftype_DIDI,2)
// //
def int_hexagon_A2_subp : def int_hexagon_A2_subp :
Hexagon_di_didi_Intrinsic<"HEXAGON.A2.subp">; Hexagon_di_didi_Intrinsic<"HEXAGON_A2_subp">;
// //
// BUILTIN_INFO(HEXAGON.A2_neg,SI_ftype_SI,1) // BUILTIN_INFO(HEXAGON.A2_neg,SI_ftype_SI,1)
// //
def int_hexagon_A2_neg : def int_hexagon_A2_neg :
Hexagon_si_si_Intrinsic<"HEXAGON.A2.neg">; Hexagon_si_si_Intrinsic<"HEXAGON_A2_neg">;
// //
// BUILTIN_INFO(HEXAGON.A2_negsat,SI_ftype_SI,1) // BUILTIN_INFO(HEXAGON.A2_negsat,SI_ftype_SI,1)
// //
def int_hexagon_A2_negsat : def int_hexagon_A2_negsat :
Hexagon_si_si_Intrinsic<"HEXAGON.A2.negsat">; Hexagon_si_si_Intrinsic<"HEXAGON_A2_negsat">;
// //
// BUILTIN_INFO(HEXAGON.A2_abs,SI_ftype_SI,1) // BUILTIN_INFO(HEXAGON.A2_abs,SI_ftype_SI,1)
// //
def int_hexagon_A2_abs : def int_hexagon_A2_abs :
Hexagon_si_si_Intrinsic<"HEXAGON.A2.abs">; Hexagon_si_si_Intrinsic<"HEXAGON_A2_abs">;
// //
// BUILTIN_INFO(HEXAGON.A2_abssat,SI_ftype_SI,1) // BUILTIN_INFO(HEXAGON.A2_abssat,SI_ftype_SI,1)
// //
def int_hexagon_A2_abssat : def int_hexagon_A2_abssat :
Hexagon_si_si_Intrinsic<"HEXAGON.A2.abssat">; Hexagon_si_si_Intrinsic<"HEXAGON_A2_abssat">;
// //
// BUILTIN_INFO(HEXAGON.A2_vconj,DI_ftype_DI,1) // BUILTIN_INFO(HEXAGON.A2_vconj,DI_ftype_DI,1)
// //
def int_hexagon_A2_vconj : def int_hexagon_A2_vconj :
Hexagon_di_di_Intrinsic<"HEXAGON.A2.vconj">; Hexagon_di_di_Intrinsic<"HEXAGON_A2_vconj">;
// //
// BUILTIN_INFO(HEXAGON.A2_negp,DI_ftype_DI,1) // BUILTIN_INFO(HEXAGON.A2_negp,DI_ftype_DI,1)
// //
def int_hexagon_A2_negp : def int_hexagon_A2_negp :
Hexagon_di_di_Intrinsic<"HEXAGON.A2.negp">; Hexagon_di_di_Intrinsic<"HEXAGON_A2_negp">;
// //
// BUILTIN_INFO(HEXAGON.A2_absp,DI_ftype_DI,1) // BUILTIN_INFO(HEXAGON.A2_absp,DI_ftype_DI,1)
// //
def int_hexagon_A2_absp : def int_hexagon_A2_absp :
Hexagon_di_di_Intrinsic<"HEXAGON.A2.absp">; Hexagon_di_di_Intrinsic<"HEXAGON_A2_absp">;
// //
// BUILTIN_INFO(HEXAGON.A2_max,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.A2_max,SI_ftype_SISI,2)
// //
def int_hexagon_A2_max : def int_hexagon_A2_max :
Hexagon_si_sisi_Intrinsic<"HEXAGON.A2.max">; Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_max">;
// //
// BUILTIN_INFO(HEXAGON.A2_maxu,USI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.A2_maxu,USI_ftype_SISI,2)
// //
def int_hexagon_A2_maxu : def int_hexagon_A2_maxu :
Hexagon_usi_sisi_Intrinsic<"HEXAGON.A2.maxu">; Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_maxu">;
// //
// BUILTIN_INFO(HEXAGON.A2_min,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.A2_min,SI_ftype_SISI,2)
// //
def int_hexagon_A2_min : def int_hexagon_A2_min :
Hexagon_si_sisi_Intrinsic<"HEXAGON.A2.min">; Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_min">;
// //
// BUILTIN_INFO(HEXAGON.A2_minu,USI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.A2_minu,USI_ftype_SISI,2)
// //
def int_hexagon_A2_minu : def int_hexagon_A2_minu :
Hexagon_usi_sisi_Intrinsic<"HEXAGON.A2.minu">; Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_minu">;
// //
// BUILTIN_INFO(HEXAGON.A2_maxp,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.A2_maxp,DI_ftype_DIDI,2)
// //
def int_hexagon_A2_maxp : def int_hexagon_A2_maxp :
Hexagon_di_didi_Intrinsic<"HEXAGON.A2.maxp">; Hexagon_di_didi_Intrinsic<"HEXAGON_A2_maxp">;
// //
// BUILTIN_INFO(HEXAGON.A2_maxup,UDI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.A2_maxup,UDI_ftype_DIDI,2)
// //
def int_hexagon_A2_maxup : def int_hexagon_A2_maxup :
Hexagon_udi_didi_Intrinsic<"HEXAGON.A2.maxup">; Hexagon_di_didi_Intrinsic<"HEXAGON_A2_maxup">;
// //
// BUILTIN_INFO(HEXAGON.A2_minp,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.A2_minp,DI_ftype_DIDI,2)
// //
def int_hexagon_A2_minp : def int_hexagon_A2_minp :
Hexagon_di_didi_Intrinsic<"HEXAGON.A2.minp">; Hexagon_di_didi_Intrinsic<"HEXAGON_A2_minp">;
// //
// BUILTIN_INFO(HEXAGON.A2_minup,UDI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.A2_minup,UDI_ftype_DIDI,2)
// //
def int_hexagon_A2_minup : def int_hexagon_A2_minup :
Hexagon_udi_didi_Intrinsic<"HEXAGON.A2.minup">; Hexagon_di_didi_Intrinsic<"HEXAGON_A2_minup">;
// //
// BUILTIN_INFO(HEXAGON.A2_tfr,SI_ftype_SI,1) // BUILTIN_INFO(HEXAGON.A2_tfr,SI_ftype_SI,1)
// //
def int_hexagon_A2_tfr : def int_hexagon_A2_tfr :
Hexagon_si_si_Intrinsic<"HEXAGON.A2.tfr">; Hexagon_si_si_Intrinsic<"HEXAGON_A2_tfr">;
// //
// BUILTIN_INFO(HEXAGON.A2_tfrsi,SI_ftype_SI,1) // BUILTIN_INFO(HEXAGON.A2_tfrsi,SI_ftype_SI,1)
// //
def int_hexagon_A2_tfrsi : def int_hexagon_A2_tfrsi :
Hexagon_si_si_Intrinsic<"HEXAGON.A2.tfrsi">; Hexagon_si_si_Intrinsic<"HEXAGON_A2_tfrsi">;
// //
// BUILTIN_INFO(HEXAGON.A2_tfrp,DI_ftype_DI,1) // BUILTIN_INFO(HEXAGON.A2_tfrp,DI_ftype_DI,1)
// //
def int_hexagon_A2_tfrp : def int_hexagon_A2_tfrp :
Hexagon_di_di_Intrinsic<"HEXAGON.A2.tfrp">; Hexagon_di_di_Intrinsic<"HEXAGON_A2_tfrp">;
// //
// BUILTIN_INFO(HEXAGON.A2_tfrpi,DI_ftype_SI,1) // BUILTIN_INFO(HEXAGON.A2_tfrpi,DI_ftype_SI,1)
// //
def int_hexagon_A2_tfrpi : def int_hexagon_A2_tfrpi :
Hexagon_di_si_Intrinsic<"HEXAGON.A2.tfrpi">; Hexagon_di_si_Intrinsic<"HEXAGON_A2_tfrpi">;
// //
// BUILTIN_INFO(HEXAGON.A2_zxtb,SI_ftype_SI,1) // BUILTIN_INFO(HEXAGON.A2_zxtb,SI_ftype_SI,1)
// //
def int_hexagon_A2_zxtb : def int_hexagon_A2_zxtb :
Hexagon_si_si_Intrinsic<"HEXAGON.A2.zxtb">; Hexagon_si_si_Intrinsic<"HEXAGON_A2_zxtb">;
// //
// BUILTIN_INFO(HEXAGON.A2_sxtb,SI_ftype_SI,1) // BUILTIN_INFO(HEXAGON.A2_sxtb,SI_ftype_SI,1)
// //
def int_hexagon_A2_sxtb : def int_hexagon_A2_sxtb :
Hexagon_si_si_Intrinsic<"HEXAGON.A2.sxtb">; Hexagon_si_si_Intrinsic<"HEXAGON_A2_sxtb">;
// //
// BUILTIN_INFO(HEXAGON.A2_zxth,SI_ftype_SI,1) // BUILTIN_INFO(HEXAGON.A2_zxth,SI_ftype_SI,1)
// //
def int_hexagon_A2_zxth : def int_hexagon_A2_zxth :
Hexagon_si_si_Intrinsic<"HEXAGON.A2.zxth">; Hexagon_si_si_Intrinsic<"HEXAGON_A2_zxth">;
// //
// BUILTIN_INFO(HEXAGON.A2_sxth,SI_ftype_SI,1) // BUILTIN_INFO(HEXAGON.A2_sxth,SI_ftype_SI,1)
// //
def int_hexagon_A2_sxth : def int_hexagon_A2_sxth :
Hexagon_si_si_Intrinsic<"HEXAGON.A2.sxth">; Hexagon_si_si_Intrinsic<"HEXAGON_A2_sxth">;
// //
// BUILTIN_INFO(HEXAGON.A2_combinew,DI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.A2_combinew,DI_ftype_SISI,2)
// //
def int_hexagon_A2_combinew : def int_hexagon_A2_combinew :
Hexagon_di_sisi_Intrinsic<"HEXAGON.A2.combinew">; Hexagon_di_sisi_Intrinsic<"HEXAGON_A2_combinew">;
//
// BUILTIN_INFO(HEXAGON.A4_combineri,DI_ftype_SISI,2)
//
def int_hexagon_A4_combineri :
Hexagon_di_sisi_Intrinsic<"HEXAGON_A4_combineri">;
//
// BUILTIN_INFO(HEXAGON.A4_combineir,DI_ftype_SISI,2)
//
def int_hexagon_A4_combineir :
Hexagon_di_sisi_Intrinsic<"HEXAGON_A4_combineir">;
// //
// BUILTIN_INFO(HEXAGON.A2_combineii,DI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.A2_combineii,DI_ftype_SISI,2)
// //
def int_hexagon_A2_combineii : def int_hexagon_A2_combineii :
Hexagon_di_sisi_Intrinsic<"HEXAGON.A2.combineii">; Hexagon_di_sisi_Intrinsic<"HEXAGON_A2_combineii">;
// //
// BUILTIN_INFO(HEXAGON.A2_combine_hh,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.A2_combine_hh,SI_ftype_SISI,2)
// //
def int_hexagon_A2_combine_hh : def int_hexagon_A2_combine_hh :
Hexagon_si_sisi_Intrinsic<"HEXAGON.A2.combine.hh">; Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_combine_hh">;
// //
// BUILTIN_INFO(HEXAGON.A2_combine_hl,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.A2_combine_hl,SI_ftype_SISI,2)
// //
def int_hexagon_A2_combine_hl : def int_hexagon_A2_combine_hl :
Hexagon_si_sisi_Intrinsic<"HEXAGON.A2.combine.hl">; Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_combine_hl">;
// //
// BUILTIN_INFO(HEXAGON.A2_combine_lh,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.A2_combine_lh,SI_ftype_SISI,2)
// //
def int_hexagon_A2_combine_lh : def int_hexagon_A2_combine_lh :
Hexagon_si_sisi_Intrinsic<"HEXAGON.A2.combine.lh">; Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_combine_lh">;
// //
// BUILTIN_INFO(HEXAGON.A2_combine_ll,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.A2_combine_ll,SI_ftype_SISI,2)
// //
def int_hexagon_A2_combine_ll : def int_hexagon_A2_combine_ll :
Hexagon_si_sisi_Intrinsic<"HEXAGON.A2.combine.ll">; Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_combine_ll">;
// //
// BUILTIN_INFO(HEXAGON.A2_tfril,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.A2_tfril,SI_ftype_SISI,2)
// //
def int_hexagon_A2_tfril : def int_hexagon_A2_tfril :
Hexagon_si_sisi_Intrinsic<"HEXAGON.A2.tfril">; Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_tfril">;
// //
// BUILTIN_INFO(HEXAGON.A2_tfrih,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.A2_tfrih,SI_ftype_SISI,2)
// //
def int_hexagon_A2_tfrih : def int_hexagon_A2_tfrih :
Hexagon_si_sisi_Intrinsic<"HEXAGON.A2.tfrih">; Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_tfrih">;
// //
// BUILTIN_INFO(HEXAGON.A2_and,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.A2_and,SI_ftype_SISI,2)
// //
def int_hexagon_A2_and : def int_hexagon_A2_and :
Hexagon_si_sisi_Intrinsic<"HEXAGON.A2.and">; Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_and">;
// //
// BUILTIN_INFO(HEXAGON.A2_or,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.A2_or,SI_ftype_SISI,2)
// //
def int_hexagon_A2_or : def int_hexagon_A2_or :
Hexagon_si_sisi_Intrinsic<"HEXAGON.A2.or">; Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_or">;
// //
// BUILTIN_INFO(HEXAGON.A2_xor,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.A2_xor,SI_ftype_SISI,2)
// //
def int_hexagon_A2_xor : def int_hexagon_A2_xor :
Hexagon_si_sisi_Intrinsic<"HEXAGON.A2.xor">; Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_xor">;
// //
// BUILTIN_INFO(HEXAGON.A2_not,SI_ftype_SI,1) // BUILTIN_INFO(HEXAGON.A2_not,SI_ftype_SI,1)
// //
def int_hexagon_A2_not : def int_hexagon_A2_not :
Hexagon_si_si_Intrinsic<"HEXAGON.A2.not">; Hexagon_si_si_Intrinsic<"HEXAGON_A2_not">;
// //
// BUILTIN_INFO(HEXAGON.M2_xor_xacc,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.M2_xor_xacc,SI_ftype_SISISI,3)
// //
def int_hexagon_M2_xor_xacc : def int_hexagon_M2_xor_xacc :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.M2.xor.xacc">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_xor_xacc">;
//
// BUILTIN_INFO(HEXAGON.M4_xor_xacc,DI_ftype_DIDIDI,3)
//
def int_hexagon_M4_xor_xacc :
Hexagon_di_dididi_Intrinsic<"HEXAGON_M4_xor_xacc">;
//
// BUILTIN_INFO(HEXAGON.A4_andn,SI_ftype_SISI,2)
//
def int_hexagon_A4_andn :
Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_andn">;
//
// BUILTIN_INFO(HEXAGON.A4_orn,SI_ftype_SISI,2)
//
def int_hexagon_A4_orn :
Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_orn">;
//
// BUILTIN_INFO(HEXAGON.A4_andnp,DI_ftype_DIDI,2)
//
def int_hexagon_A4_andnp :
Hexagon_di_didi_Intrinsic<"HEXAGON_A4_andnp">;
//
// BUILTIN_INFO(HEXAGON.A4_ornp,DI_ftype_DIDI,2)
//
def int_hexagon_A4_ornp :
Hexagon_di_didi_Intrinsic<"HEXAGON_A4_ornp">;
//
// BUILTIN_INFO(HEXAGON.S4_addaddi,SI_ftype_SISISI,3)
//
def int_hexagon_S4_addaddi :
Hexagon_si_sisisi_Intrinsic<"HEXAGON_S4_addaddi">;
//
// BUILTIN_INFO(HEXAGON.S4_subaddi,SI_ftype_SISISI,3)
//
def int_hexagon_S4_subaddi :
Hexagon_si_sisisi_Intrinsic<"HEXAGON_S4_subaddi">;
//
// BUILTIN_INFO(HEXAGON.M4_and_and,SI_ftype_SISISI,3)
//
def int_hexagon_M4_and_and :
Hexagon_si_sisisi_Intrinsic<"HEXAGON_M4_and_and">;
//
// BUILTIN_INFO(HEXAGON.M4_and_andn,SI_ftype_SISISI,3)
//
def int_hexagon_M4_and_andn :
Hexagon_si_sisisi_Intrinsic<"HEXAGON_M4_and_andn">;
//
// BUILTIN_INFO(HEXAGON.M4_and_or,SI_ftype_SISISI,3)
//
def int_hexagon_M4_and_or :
Hexagon_si_sisisi_Intrinsic<"HEXAGON_M4_and_or">;
//
// BUILTIN_INFO(HEXAGON.M4_and_xor,SI_ftype_SISISI,3)
//
def int_hexagon_M4_and_xor :
Hexagon_si_sisisi_Intrinsic<"HEXAGON_M4_and_xor">;
//
// BUILTIN_INFO(HEXAGON.M4_or_and,SI_ftype_SISISI,3)
//
def int_hexagon_M4_or_and :
Hexagon_si_sisisi_Intrinsic<"HEXAGON_M4_or_and">;
//
// BUILTIN_INFO(HEXAGON.M4_or_andn,SI_ftype_SISISI,3)
//
def int_hexagon_M4_or_andn :
Hexagon_si_sisisi_Intrinsic<"HEXAGON_M4_or_andn">;
//
// BUILTIN_INFO(HEXAGON.M4_or_or,SI_ftype_SISISI,3)
//
def int_hexagon_M4_or_or :
Hexagon_si_sisisi_Intrinsic<"HEXAGON_M4_or_or">;
//
// BUILTIN_INFO(HEXAGON.M4_or_xor,SI_ftype_SISISI,3)
//
def int_hexagon_M4_or_xor :
Hexagon_si_sisisi_Intrinsic<"HEXAGON_M4_or_xor">;
//
// BUILTIN_INFO(HEXAGON.S4_or_andix,SI_ftype_SISISI,3)
//
def int_hexagon_S4_or_andix :
Hexagon_si_sisisi_Intrinsic<"HEXAGON_S4_or_andix">;
//
// BUILTIN_INFO(HEXAGON.S4_or_andi,SI_ftype_SISISI,3)
//
def int_hexagon_S4_or_andi :
Hexagon_si_sisisi_Intrinsic<"HEXAGON_S4_or_andi">;
//
// BUILTIN_INFO(HEXAGON.S4_or_ori,SI_ftype_SISISI,3)
//
def int_hexagon_S4_or_ori :
Hexagon_si_sisisi_Intrinsic<"HEXAGON_S4_or_ori">;
//
// BUILTIN_INFO(HEXAGON.M4_xor_and,SI_ftype_SISISI,3)
//
def int_hexagon_M4_xor_and :
Hexagon_si_sisisi_Intrinsic<"HEXAGON_M4_xor_and">;
//
// BUILTIN_INFO(HEXAGON.M4_xor_or,SI_ftype_SISISI,3)
//
def int_hexagon_M4_xor_or :
Hexagon_si_sisisi_Intrinsic<"HEXAGON_M4_xor_or">;
//
// BUILTIN_INFO(HEXAGON.M4_xor_andn,SI_ftype_SISISI,3)
//
def int_hexagon_M4_xor_andn :
Hexagon_si_sisisi_Intrinsic<"HEXAGON_M4_xor_andn">;
// //
// BUILTIN_INFO(HEXAGON.A2_subri,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.A2_subri,SI_ftype_SISI,2)
// //
def int_hexagon_A2_subri : def int_hexagon_A2_subri :
Hexagon_si_sisi_Intrinsic<"HEXAGON.A2.subri">; Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_subri">;
// //
// BUILTIN_INFO(HEXAGON.A2_andir,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.A2_andir,SI_ftype_SISI,2)
// //
def int_hexagon_A2_andir : def int_hexagon_A2_andir :
Hexagon_si_sisi_Intrinsic<"HEXAGON.A2.andir">; Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_andir">;
// //
// BUILTIN_INFO(HEXAGON.A2_orir,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.A2_orir,SI_ftype_SISI,2)
// //
def int_hexagon_A2_orir : def int_hexagon_A2_orir :
Hexagon_si_sisi_Intrinsic<"HEXAGON.A2.orir">; Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_orir">;
// //
// BUILTIN_INFO(HEXAGON.A2_andp,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.A2_andp,DI_ftype_DIDI,2)
// //
def int_hexagon_A2_andp : def int_hexagon_A2_andp :
Hexagon_di_didi_Intrinsic<"HEXAGON.A2.andp">; Hexagon_di_didi_Intrinsic<"HEXAGON_A2_andp">;
// //
// BUILTIN_INFO(HEXAGON.A2_orp,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.A2_orp,DI_ftype_DIDI,2)
// //
def int_hexagon_A2_orp : def int_hexagon_A2_orp :
Hexagon_di_didi_Intrinsic<"HEXAGON.A2.orp">; Hexagon_di_didi_Intrinsic<"HEXAGON_A2_orp">;
// //
// BUILTIN_INFO(HEXAGON.A2_xorp,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.A2_xorp,DI_ftype_DIDI,2)
// //
def int_hexagon_A2_xorp : def int_hexagon_A2_xorp :
Hexagon_di_didi_Intrinsic<"HEXAGON.A2.xorp">; Hexagon_di_didi_Intrinsic<"HEXAGON_A2_xorp">;
// //
// BUILTIN_INFO(HEXAGON.A2_notp,DI_ftype_DI,1) // BUILTIN_INFO(HEXAGON.A2_notp,DI_ftype_DI,1)
// //
def int_hexagon_A2_notp : def int_hexagon_A2_notp :
Hexagon_di_di_Intrinsic<"HEXAGON.A2.notp">; Hexagon_di_di_Intrinsic<"HEXAGON_A2_notp">;
// //
// BUILTIN_INFO(HEXAGON.A2_sxtw,DI_ftype_SI,1) // BUILTIN_INFO(HEXAGON.A2_sxtw,DI_ftype_SI,1)
// //
def int_hexagon_A2_sxtw : def int_hexagon_A2_sxtw :
Hexagon_di_si_Intrinsic<"HEXAGON.A2.sxtw">; Hexagon_di_si_Intrinsic<"HEXAGON_A2_sxtw">;
// //
// BUILTIN_INFO(HEXAGON.A2_sat,SI_ftype_DI,1) // BUILTIN_INFO(HEXAGON.A2_sat,SI_ftype_DI,1)
// //
def int_hexagon_A2_sat : def int_hexagon_A2_sat :
Hexagon_si_di_Intrinsic<"HEXAGON.A2.sat">; Hexagon_si_di_Intrinsic<"HEXAGON_A2_sat">;
//
// BUILTIN_INFO(HEXAGON.A2_roundsat,SI_ftype_DI,1)
//
def int_hexagon_A2_roundsat :
Hexagon_si_di_Intrinsic<"HEXAGON_A2_roundsat">;
// //
// BUILTIN_INFO(HEXAGON.A2_sath,SI_ftype_SI,1) // BUILTIN_INFO(HEXAGON.A2_sath,SI_ftype_SI,1)
// //
def int_hexagon_A2_sath : def int_hexagon_A2_sath :
Hexagon_si_si_Intrinsic<"HEXAGON.A2.sath">; Hexagon_si_si_Intrinsic<"HEXAGON_A2_sath">;
// //
// BUILTIN_INFO(HEXAGON.A2_satuh,SI_ftype_SI,1) // BUILTIN_INFO(HEXAGON.A2_satuh,SI_ftype_SI,1)
// //
def int_hexagon_A2_satuh : def int_hexagon_A2_satuh :
Hexagon_si_si_Intrinsic<"HEXAGON.A2.satuh">; Hexagon_si_si_Intrinsic<"HEXAGON_A2_satuh">;
// //
// BUILTIN_INFO(HEXAGON.A2_satub,SI_ftype_SI,1) // BUILTIN_INFO(HEXAGON.A2_satub,SI_ftype_SI,1)
// //
def int_hexagon_A2_satub : def int_hexagon_A2_satub :
Hexagon_si_si_Intrinsic<"HEXAGON.A2.satub">; Hexagon_si_si_Intrinsic<"HEXAGON_A2_satub">;
// //
// BUILTIN_INFO(HEXAGON.A2_satb,SI_ftype_SI,1) // BUILTIN_INFO(HEXAGON.A2_satb,SI_ftype_SI,1)
// //
def int_hexagon_A2_satb : def int_hexagon_A2_satb :
Hexagon_si_si_Intrinsic<"HEXAGON.A2.satb">; Hexagon_si_si_Intrinsic<"HEXAGON_A2_satb">;
// //
// BUILTIN_INFO(HEXAGON.A2_vaddub,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.A2_vaddub,DI_ftype_DIDI,2)
// //
def int_hexagon_A2_vaddub : def int_hexagon_A2_vaddub :
Hexagon_di_didi_Intrinsic<"HEXAGON.A2.vaddub">; Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vaddub">;
//
// BUILTIN_INFO(HEXAGON.A2_vaddb_map,DI_ftype_DIDI,2)
//
def int_hexagon_A2_vaddb_map :
Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vaddb_map">;
// //
// BUILTIN_INFO(HEXAGON.A2_vaddubs,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.A2_vaddubs,DI_ftype_DIDI,2)
// //
def int_hexagon_A2_vaddubs : def int_hexagon_A2_vaddubs :
Hexagon_di_didi_Intrinsic<"HEXAGON.A2.vaddubs">; Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vaddubs">;
// //
// BUILTIN_INFO(HEXAGON.A2_vaddh,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.A2_vaddh,DI_ftype_DIDI,2)
// //
def int_hexagon_A2_vaddh : def int_hexagon_A2_vaddh :
Hexagon_di_didi_Intrinsic<"HEXAGON.A2.vaddh">; Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vaddh">;
// //
// BUILTIN_INFO(HEXAGON.A2_vaddhs,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.A2_vaddhs,DI_ftype_DIDI,2)
// //
def int_hexagon_A2_vaddhs : def int_hexagon_A2_vaddhs :
Hexagon_di_didi_Intrinsic<"HEXAGON.A2.vaddhs">; Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vaddhs">;
// //
// BUILTIN_INFO(HEXAGON.A2_vadduhs,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.A2_vadduhs,DI_ftype_DIDI,2)
// //
def int_hexagon_A2_vadduhs : def int_hexagon_A2_vadduhs :
Hexagon_di_didi_Intrinsic<"HEXAGON.A2.vadduhs">; Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vadduhs">;
//
// BUILTIN_INFO(HEXAGON.A5_vaddhubs,SI_ftype_DIDI,2)
//
def int_hexagon_A5_vaddhubs :
Hexagon_si_didi_Intrinsic<"HEXAGON_A5_vaddhubs">;
// //
// BUILTIN_INFO(HEXAGON.A2_vaddw,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.A2_vaddw,DI_ftype_DIDI,2)
// //
def int_hexagon_A2_vaddw : def int_hexagon_A2_vaddw :
Hexagon_di_didi_Intrinsic<"HEXAGON.A2.vaddw">; Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vaddw">;
// //
// BUILTIN_INFO(HEXAGON.A2_vaddws,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.A2_vaddws,DI_ftype_DIDI,2)
// //
def int_hexagon_A2_vaddws : def int_hexagon_A2_vaddws :
Hexagon_di_didi_Intrinsic<"HEXAGON.A2.vaddws">; Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vaddws">;
//
// BUILTIN_INFO(HEXAGON.S4_vxaddsubw,DI_ftype_DIDI,2)
//
def int_hexagon_S4_vxaddsubw :
Hexagon_di_didi_Intrinsic<"HEXAGON_S4_vxaddsubw">;
//
// BUILTIN_INFO(HEXAGON.S4_vxsubaddw,DI_ftype_DIDI,2)
//
def int_hexagon_S4_vxsubaddw :
Hexagon_di_didi_Intrinsic<"HEXAGON_S4_vxsubaddw">;
//
// BUILTIN_INFO(HEXAGON.S4_vxaddsubh,DI_ftype_DIDI,2)
//
def int_hexagon_S4_vxaddsubh :
Hexagon_di_didi_Intrinsic<"HEXAGON_S4_vxaddsubh">;
//
// BUILTIN_INFO(HEXAGON.S4_vxsubaddh,DI_ftype_DIDI,2)
//
def int_hexagon_S4_vxsubaddh :
Hexagon_di_didi_Intrinsic<"HEXAGON_S4_vxsubaddh">;
//
// BUILTIN_INFO(HEXAGON.S4_vxaddsubhr,DI_ftype_DIDI,2)
//
def int_hexagon_S4_vxaddsubhr :
Hexagon_di_didi_Intrinsic<"HEXAGON_S4_vxaddsubhr">;
//
// BUILTIN_INFO(HEXAGON.S4_vxsubaddhr,DI_ftype_DIDI,2)
//
def int_hexagon_S4_vxsubaddhr :
Hexagon_di_didi_Intrinsic<"HEXAGON_S4_vxsubaddhr">;
// //
// BUILTIN_INFO(HEXAGON.A2_svavgh,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.A2_svavgh,SI_ftype_SISI,2)
// //
def int_hexagon_A2_svavgh : def int_hexagon_A2_svavgh :
Hexagon_si_sisi_Intrinsic<"HEXAGON.A2.svavgh">; Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_svavgh">;
// //
// BUILTIN_INFO(HEXAGON.A2_svavghs,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.A2_svavghs,SI_ftype_SISI,2)
// //
def int_hexagon_A2_svavghs : def int_hexagon_A2_svavghs :
Hexagon_si_sisi_Intrinsic<"HEXAGON.A2.svavghs">; Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_svavghs">;
// //
// BUILTIN_INFO(HEXAGON.A2_svnavgh,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.A2_svnavgh,SI_ftype_SISI,2)
// //
def int_hexagon_A2_svnavgh : def int_hexagon_A2_svnavgh :
Hexagon_si_sisi_Intrinsic<"HEXAGON.A2.svnavgh">; Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_svnavgh">;
// //
// BUILTIN_INFO(HEXAGON.A2_svaddh,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.A2_svaddh,SI_ftype_SISI,2)
// //
def int_hexagon_A2_svaddh : def int_hexagon_A2_svaddh :
Hexagon_si_sisi_Intrinsic<"HEXAGON.A2.svaddh">; Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_svaddh">;
// //
// BUILTIN_INFO(HEXAGON.A2_svaddhs,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.A2_svaddhs,SI_ftype_SISI,2)
// //
def int_hexagon_A2_svaddhs : def int_hexagon_A2_svaddhs :
Hexagon_si_sisi_Intrinsic<"HEXAGON.A2.svaddhs">; Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_svaddhs">;
// //
// BUILTIN_INFO(HEXAGON.A2_svadduhs,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.A2_svadduhs,SI_ftype_SISI,2)
// //
def int_hexagon_A2_svadduhs : def int_hexagon_A2_svadduhs :
Hexagon_si_sisi_Intrinsic<"HEXAGON.A2.svadduhs">; Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_svadduhs">;
// //
// BUILTIN_INFO(HEXAGON.A2_svsubh,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.A2_svsubh,SI_ftype_SISI,2)
// //
def int_hexagon_A2_svsubh : def int_hexagon_A2_svsubh :
Hexagon_si_sisi_Intrinsic<"HEXAGON.A2.svsubh">; Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_svsubh">;
// //
// BUILTIN_INFO(HEXAGON.A2_svsubhs,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.A2_svsubhs,SI_ftype_SISI,2)
// //
def int_hexagon_A2_svsubhs : def int_hexagon_A2_svsubhs :
Hexagon_si_sisi_Intrinsic<"HEXAGON.A2.svsubhs">; Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_svsubhs">;
// //
// BUILTIN_INFO(HEXAGON.A2_svsubuhs,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.A2_svsubuhs,SI_ftype_SISI,2)
// //
def int_hexagon_A2_svsubuhs : def int_hexagon_A2_svsubuhs :
Hexagon_si_sisi_Intrinsic<"HEXAGON.A2.svsubuhs">; Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_svsubuhs">;
// //
// BUILTIN_INFO(HEXAGON.A2_vraddub,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.A2_vraddub,DI_ftype_DIDI,2)
// //
def int_hexagon_A2_vraddub : def int_hexagon_A2_vraddub :
Hexagon_di_didi_Intrinsic<"HEXAGON.A2.vraddub">; Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vraddub">;
// //
// BUILTIN_INFO(HEXAGON.A2_vraddub_acc,DI_ftype_DIDIDI,3) // BUILTIN_INFO(HEXAGON.A2_vraddub_acc,DI_ftype_DIDIDI,3)
// //
def int_hexagon_A2_vraddub_acc : def int_hexagon_A2_vraddub_acc :
Hexagon_di_dididi_Intrinsic<"HEXAGON.A2.vraddub.acc">; Hexagon_di_dididi_Intrinsic<"HEXAGON_A2_vraddub_acc">;
//
// BUILTIN_INFO(HEXAGON.M2_vraddh,SI_ftype_DIDI,2)
//
def int_hexagon_M2_vraddh :
Hexagon_si_didi_Intrinsic<"HEXAGON_M2_vraddh">;
// //
// BUILTIN_INFO(HEXAGON.M2_vradduh,SI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.M2_vradduh,SI_ftype_DIDI,2)
// //
def int_hexagon_M2_vradduh : def int_hexagon_M2_vradduh :
Hexagon_si_didi_Intrinsic<"HEXAGON.M2.vradduh">; Hexagon_si_didi_Intrinsic<"HEXAGON_M2_vradduh">;
// //
// BUILTIN_INFO(HEXAGON.A2_vsubub,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.A2_vsubub,DI_ftype_DIDI,2)
// //
def int_hexagon_A2_vsubub : def int_hexagon_A2_vsubub :
Hexagon_di_didi_Intrinsic<"HEXAGON.A2.vsubub">; Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vsubub">;
//
// BUILTIN_INFO(HEXAGON.A2_vsubb_map,DI_ftype_DIDI,2)
//
def int_hexagon_A2_vsubb_map :
Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vsubb_map">;
// //
// BUILTIN_INFO(HEXAGON.A2_vsububs,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.A2_vsububs,DI_ftype_DIDI,2)
// //
def int_hexagon_A2_vsububs : def int_hexagon_A2_vsububs :
Hexagon_di_didi_Intrinsic<"HEXAGON.A2.vsububs">; Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vsububs">;
// //
// BUILTIN_INFO(HEXAGON.A2_vsubh,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.A2_vsubh,DI_ftype_DIDI,2)
// //
def int_hexagon_A2_vsubh : def int_hexagon_A2_vsubh :
Hexagon_di_didi_Intrinsic<"HEXAGON.A2.vsubh">; Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vsubh">;
// //
// BUILTIN_INFO(HEXAGON.A2_vsubhs,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.A2_vsubhs,DI_ftype_DIDI,2)
// //
def int_hexagon_A2_vsubhs : def int_hexagon_A2_vsubhs :
Hexagon_di_didi_Intrinsic<"HEXAGON.A2.vsubhs">; Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vsubhs">;
// //
// BUILTIN_INFO(HEXAGON.A2_vsubuhs,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.A2_vsubuhs,DI_ftype_DIDI,2)
// //
def int_hexagon_A2_vsubuhs : def int_hexagon_A2_vsubuhs :
Hexagon_di_didi_Intrinsic<"HEXAGON.A2.vsubuhs">; Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vsubuhs">;
// //
// BUILTIN_INFO(HEXAGON.A2_vsubw,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.A2_vsubw,DI_ftype_DIDI,2)
// //
def int_hexagon_A2_vsubw : def int_hexagon_A2_vsubw :
Hexagon_di_didi_Intrinsic<"HEXAGON.A2.vsubw">; Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vsubw">;
// //
// BUILTIN_INFO(HEXAGON.A2_vsubws,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.A2_vsubws,DI_ftype_DIDI,2)
// //
def int_hexagon_A2_vsubws : def int_hexagon_A2_vsubws :
Hexagon_di_didi_Intrinsic<"HEXAGON.A2.vsubws">; Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vsubws">;
// //
// BUILTIN_INFO(HEXAGON.A2_vabsh,DI_ftype_DI,1) // BUILTIN_INFO(HEXAGON.A2_vabsh,DI_ftype_DI,1)
// //
def int_hexagon_A2_vabsh : def int_hexagon_A2_vabsh :
Hexagon_di_di_Intrinsic<"HEXAGON.A2.vabsh">; Hexagon_di_di_Intrinsic<"HEXAGON_A2_vabsh">;
// //
// BUILTIN_INFO(HEXAGON.A2_vabshsat,DI_ftype_DI,1) // BUILTIN_INFO(HEXAGON.A2_vabshsat,DI_ftype_DI,1)
// //
def int_hexagon_A2_vabshsat : def int_hexagon_A2_vabshsat :
Hexagon_di_di_Intrinsic<"HEXAGON.A2.vabshsat">; Hexagon_di_di_Intrinsic<"HEXAGON_A2_vabshsat">;
// //
// BUILTIN_INFO(HEXAGON.A2_vabsw,DI_ftype_DI,1) // BUILTIN_INFO(HEXAGON.A2_vabsw,DI_ftype_DI,1)
// //
def int_hexagon_A2_vabsw : def int_hexagon_A2_vabsw :
Hexagon_di_di_Intrinsic<"HEXAGON.A2.vabsw">; Hexagon_di_di_Intrinsic<"HEXAGON_A2_vabsw">;
// //
// BUILTIN_INFO(HEXAGON.A2_vabswsat,DI_ftype_DI,1) // BUILTIN_INFO(HEXAGON.A2_vabswsat,DI_ftype_DI,1)
// //
def int_hexagon_A2_vabswsat : def int_hexagon_A2_vabswsat :
Hexagon_di_di_Intrinsic<"HEXAGON.A2.vabswsat">; Hexagon_di_di_Intrinsic<"HEXAGON_A2_vabswsat">;
// //
// BUILTIN_INFO(HEXAGON.M2_vabsdiffw,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.M2_vabsdiffw,DI_ftype_DIDI,2)
// //
def int_hexagon_M2_vabsdiffw : def int_hexagon_M2_vabsdiffw :
Hexagon_di_didi_Intrinsic<"HEXAGON.M2.vabsdiffw">; Hexagon_di_didi_Intrinsic<"HEXAGON_M2_vabsdiffw">;
// //
// BUILTIN_INFO(HEXAGON.M2_vabsdiffh,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.M2_vabsdiffh,DI_ftype_DIDI,2)
// //
def int_hexagon_M2_vabsdiffh : def int_hexagon_M2_vabsdiffh :
Hexagon_di_didi_Intrinsic<"HEXAGON.M2.vabsdiffh">; Hexagon_di_didi_Intrinsic<"HEXAGON_M2_vabsdiffh">;
// //
// BUILTIN_INFO(HEXAGON.A2_vrsadub,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.A2_vrsadub,DI_ftype_DIDI,2)
// //
def int_hexagon_A2_vrsadub : def int_hexagon_A2_vrsadub :
Hexagon_di_didi_Intrinsic<"HEXAGON.A2.vrsadub">; Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vrsadub">;
// //
// BUILTIN_INFO(HEXAGON.A2_vrsadub_acc,DI_ftype_DIDIDI,3) // BUILTIN_INFO(HEXAGON.A2_vrsadub_acc,DI_ftype_DIDIDI,3)
// //
def int_hexagon_A2_vrsadub_acc : def int_hexagon_A2_vrsadub_acc :
Hexagon_di_dididi_Intrinsic<"HEXAGON.A2.vrsadub.acc">; Hexagon_di_dididi_Intrinsic<"HEXAGON_A2_vrsadub_acc">;
// //
// BUILTIN_INFO(HEXAGON.A2_vavgub,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.A2_vavgub,DI_ftype_DIDI,2)
// //
def int_hexagon_A2_vavgub : def int_hexagon_A2_vavgub :
Hexagon_di_didi_Intrinsic<"HEXAGON.A2.vavgub">; Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vavgub">;
// //
// BUILTIN_INFO(HEXAGON.A2_vavguh,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.A2_vavguh,DI_ftype_DIDI,2)
// //
def int_hexagon_A2_vavguh : def int_hexagon_A2_vavguh :
Hexagon_di_didi_Intrinsic<"HEXAGON.A2.vavguh">; Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vavguh">;
// //
// BUILTIN_INFO(HEXAGON.A2_vavgh,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.A2_vavgh,DI_ftype_DIDI,2)
// //
def int_hexagon_A2_vavgh : def int_hexagon_A2_vavgh :
Hexagon_di_didi_Intrinsic<"HEXAGON.A2.vavgh">; Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vavgh">;
// //
// BUILTIN_INFO(HEXAGON.A2_vnavgh,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.A2_vnavgh,DI_ftype_DIDI,2)
// //
def int_hexagon_A2_vnavgh : def int_hexagon_A2_vnavgh :
Hexagon_di_didi_Intrinsic<"HEXAGON.A2.vnavgh">; Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vnavgh">;
// //
// BUILTIN_INFO(HEXAGON.A2_vavgw,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.A2_vavgw,DI_ftype_DIDI,2)
// //
def int_hexagon_A2_vavgw : def int_hexagon_A2_vavgw :
Hexagon_di_didi_Intrinsic<"HEXAGON.A2.vavgw">; Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vavgw">;
// //
// BUILTIN_INFO(HEXAGON.A2_vnavgw,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.A2_vnavgw,DI_ftype_DIDI,2)
// //
def int_hexagon_A2_vnavgw : def int_hexagon_A2_vnavgw :
Hexagon_di_didi_Intrinsic<"HEXAGON.A2.vnavgw">; Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vnavgw">;
// //
// BUILTIN_INFO(HEXAGON.A2_vavgwr,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.A2_vavgwr,DI_ftype_DIDI,2)
// //
def int_hexagon_A2_vavgwr : def int_hexagon_A2_vavgwr :
Hexagon_di_didi_Intrinsic<"HEXAGON.A2.vavgwr">; Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vavgwr">;
// //
// BUILTIN_INFO(HEXAGON.A2_vnavgwr,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.A2_vnavgwr,DI_ftype_DIDI,2)
// //
def int_hexagon_A2_vnavgwr : def int_hexagon_A2_vnavgwr :
Hexagon_di_didi_Intrinsic<"HEXAGON.A2.vnavgwr">; Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vnavgwr">;
// //
// BUILTIN_INFO(HEXAGON.A2_vavgwcr,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.A2_vavgwcr,DI_ftype_DIDI,2)
// //
def int_hexagon_A2_vavgwcr : def int_hexagon_A2_vavgwcr :
Hexagon_di_didi_Intrinsic<"HEXAGON.A2.vavgwcr">; Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vavgwcr">;
// //
// BUILTIN_INFO(HEXAGON.A2_vnavgwcr,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.A2_vnavgwcr,DI_ftype_DIDI,2)
// //
def int_hexagon_A2_vnavgwcr : def int_hexagon_A2_vnavgwcr :
Hexagon_di_didi_Intrinsic<"HEXAGON.A2.vnavgwcr">; Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vnavgwcr">;
// //
// BUILTIN_INFO(HEXAGON.A2_vavghcr,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.A2_vavghcr,DI_ftype_DIDI,2)
// //
def int_hexagon_A2_vavghcr : def int_hexagon_A2_vavghcr :
Hexagon_di_didi_Intrinsic<"HEXAGON.A2.vavghcr">; Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vavghcr">;
// //
// BUILTIN_INFO(HEXAGON.A2_vnavghcr,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.A2_vnavghcr,DI_ftype_DIDI,2)
// //
def int_hexagon_A2_vnavghcr : def int_hexagon_A2_vnavghcr :
Hexagon_di_didi_Intrinsic<"HEXAGON.A2.vnavghcr">; Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vnavghcr">;
// //
// BUILTIN_INFO(HEXAGON.A2_vavguw,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.A2_vavguw,DI_ftype_DIDI,2)
// //
def int_hexagon_A2_vavguw : def int_hexagon_A2_vavguw :
Hexagon_di_didi_Intrinsic<"HEXAGON.A2.vavguw">; Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vavguw">;
// //
// BUILTIN_INFO(HEXAGON.A2_vavguwr,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.A2_vavguwr,DI_ftype_DIDI,2)
// //
def int_hexagon_A2_vavguwr : def int_hexagon_A2_vavguwr :
Hexagon_di_didi_Intrinsic<"HEXAGON.A2.vavguwr">; Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vavguwr">;
// //
// BUILTIN_INFO(HEXAGON.A2_vavgubr,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.A2_vavgubr,DI_ftype_DIDI,2)
// //
def int_hexagon_A2_vavgubr : def int_hexagon_A2_vavgubr :
Hexagon_di_didi_Intrinsic<"HEXAGON.A2.vavgubr">; Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vavgubr">;
// //
// BUILTIN_INFO(HEXAGON.A2_vavguhr,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.A2_vavguhr,DI_ftype_DIDI,2)
// //
def int_hexagon_A2_vavguhr : def int_hexagon_A2_vavguhr :
Hexagon_di_didi_Intrinsic<"HEXAGON.A2.vavguhr">; Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vavguhr">;
// //
// BUILTIN_INFO(HEXAGON.A2_vavghr,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.A2_vavghr,DI_ftype_DIDI,2)
// //
def int_hexagon_A2_vavghr : def int_hexagon_A2_vavghr :
Hexagon_di_didi_Intrinsic<"HEXAGON.A2.vavghr">; Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vavghr">;
// //
// BUILTIN_INFO(HEXAGON.A2_vnavghr,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.A2_vnavghr,DI_ftype_DIDI,2)
// //
def int_hexagon_A2_vnavghr : def int_hexagon_A2_vnavghr :
Hexagon_di_didi_Intrinsic<"HEXAGON.A2.vnavghr">; Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vnavghr">;
// //
// BUILTIN_INFO(HEXAGON.A2_vminh,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.A4_round_ri,SI_ftype_SISI,2)
// //
def int_hexagon_A2_vminh : def int_hexagon_A4_round_ri :
Hexagon_di_didi_Intrinsic<"HEXAGON.A2.vminh">; Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_round_ri">;
// //
// BUILTIN_INFO(HEXAGON.A2_vmaxh,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.A4_round_rr,SI_ftype_SISI,2)
// //
def int_hexagon_A2_vmaxh : def int_hexagon_A4_round_rr :
Hexagon_di_didi_Intrinsic<"HEXAGON.A2.vmaxh">; Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_round_rr">;
// //
// BUILTIN_INFO(HEXAGON.A2_vminub,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.A4_round_ri_sat,SI_ftype_SISI,2)
// //
def int_hexagon_A2_vminub : def int_hexagon_A4_round_ri_sat :
Hexagon_di_didi_Intrinsic<"HEXAGON.A2.vminub">; Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_round_ri_sat">;
// //
// BUILTIN_INFO(HEXAGON.A2_vmaxub,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.A4_round_rr_sat,SI_ftype_SISI,2)
// //
def int_hexagon_A2_vmaxub : def int_hexagon_A4_round_rr_sat :
Hexagon_di_didi_Intrinsic<"HEXAGON.A2.vmaxub">; Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_round_rr_sat">;
// //
// BUILTIN_INFO(HEXAGON.A2_vminuh,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.A4_cround_ri,SI_ftype_SISI,2)
// //
def int_hexagon_A2_vminuh : def int_hexagon_A4_cround_ri :
Hexagon_di_didi_Intrinsic<"HEXAGON.A2.vminuh">; Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_cround_ri">;
// //
// BUILTIN_INFO(HEXAGON.A2_vmaxuh,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.A4_cround_rr,SI_ftype_SISI,2)
// //
def int_hexagon_A2_vmaxuh : def int_hexagon_A4_cround_rr :
Hexagon_di_didi_Intrinsic<"HEXAGON.A2.vmaxuh">; Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_cround_rr">;
// //
// BUILTIN_INFO(HEXAGON.A2_vminw,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.A4_vrminh,DI_ftype_DIDISI,3)
// //
def int_hexagon_A2_vminw : def int_hexagon_A4_vrminh :
Hexagon_di_didi_Intrinsic<"HEXAGON.A2.vminw">; Hexagon_di_didisi_Intrinsic<"HEXAGON_A4_vrminh">;
// //
// BUILTIN_INFO(HEXAGON.A2_vmaxw,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.A4_vrmaxh,DI_ftype_DIDISI,3)
// //
def int_hexagon_A2_vmaxw : def int_hexagon_A4_vrmaxh :
Hexagon_di_didi_Intrinsic<"HEXAGON.A2.vmaxw">; Hexagon_di_didisi_Intrinsic<"HEXAGON_A4_vrmaxh">;
// //
// BUILTIN_INFO(HEXAGON.A2_vminuw,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.A4_vrminuh,DI_ftype_DIDISI,3)
// //
def int_hexagon_A2_vminuw : def int_hexagon_A4_vrminuh :
Hexagon_di_didi_Intrinsic<"HEXAGON.A2.vminuw">; Hexagon_di_didisi_Intrinsic<"HEXAGON_A4_vrminuh">;
// //
// BUILTIN_INFO(HEXAGON.A2_vmaxuw,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.A4_vrmaxuh,DI_ftype_DIDISI,3)
// //
def int_hexagon_A2_vmaxuw : def int_hexagon_A4_vrmaxuh :
Hexagon_di_didi_Intrinsic<"HEXAGON.A2.vmaxuw">; Hexagon_di_didisi_Intrinsic<"HEXAGON_A4_vrmaxuh">;
// //
// BUILTIN_INFO(HEXAGON.S2_asr_r_r,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.A4_vrminw,DI_ftype_DIDISI,3)
// //
def int_hexagon_S2_asr_r_r : def int_hexagon_A4_vrminw :
Hexagon_si_sisi_Intrinsic<"HEXAGON.S2.asr.r.r">; Hexagon_di_didisi_Intrinsic<"HEXAGON_A4_vrminw">;
// //
// BUILTIN_INFO(HEXAGON.S2_asl_r_r,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.A4_vrmaxw,DI_ftype_DIDISI,3)
// //
def int_hexagon_S2_asl_r_r : def int_hexagon_A4_vrmaxw :
Hexagon_si_sisi_Intrinsic<"HEXAGON.S2.asl.r.r">; Hexagon_di_didisi_Intrinsic<"HEXAGON_A4_vrmaxw">;
// //
// BUILTIN_INFO(HEXAGON.S2_lsr_r_r,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.A4_vrminuw,DI_ftype_DIDISI,3)
// //
def int_hexagon_S2_lsr_r_r : def int_hexagon_A4_vrminuw :
Hexagon_si_sisi_Intrinsic<"HEXAGON.S2.lsr.r.r">; Hexagon_di_didisi_Intrinsic<"HEXAGON_A4_vrminuw">;
// //
// BUILTIN_INFO(HEXAGON.S2_lsl_r_r,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.A4_vrmaxuw,DI_ftype_DIDISI,3)
// //
def int_hexagon_S2_lsl_r_r : def int_hexagon_A4_vrmaxuw :
Hexagon_si_sisi_Intrinsic<"HEXAGON.S2.lsl.r.r">; Hexagon_di_didisi_Intrinsic<"HEXAGON_A4_vrmaxuw">;
// //
// BUILTIN_INFO(HEXAGON.S2_asr_r_p,DI_ftype_DISI,2) // BUILTIN_INFO(HEXAGON.A2_vminb,DI_ftype_DIDI,2)
// //
def int_hexagon_S2_asr_r_p : def int_hexagon_A2_vminb :
Hexagon_di_disi_Intrinsic<"HEXAGON.S2.asr.r.p">; Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vminb">;
// //
// BUILTIN_INFO(HEXAGON.S2_asl_r_p,DI_ftype_DISI,2) // BUILTIN_INFO(HEXAGON.A2_vmaxb,DI_ftype_DIDI,2)
// //
def int_hexagon_S2_asl_r_p : def int_hexagon_A2_vmaxb :
Hexagon_di_disi_Intrinsic<"HEXAGON.S2.asl.r.p">; Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vmaxb">;
// //
// BUILTIN_INFO(HEXAGON.S2_lsr_r_p,DI_ftype_DISI,2) // BUILTIN_INFO(HEXAGON.A2_vminub,DI_ftype_DIDI,2)
// //
def int_hexagon_S2_lsr_r_p : def int_hexagon_A2_vminub :
Hexagon_di_disi_Intrinsic<"HEXAGON.S2.lsr.r.p">; Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vminub">;
// //
// BUILTIN_INFO(HEXAGON.S2_lsl_r_p,DI_ftype_DISI,2) // BUILTIN_INFO(HEXAGON.A2_vmaxub,DI_ftype_DIDI,2)
// //
def int_hexagon_S2_lsl_r_p : def int_hexagon_A2_vmaxub :
Hexagon_di_disi_Intrinsic<"HEXAGON.S2.lsl.r.p">; Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vmaxub">;
// //
// BUILTIN_INFO(HEXAGON.S2_asr_r_r_acc,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.A2_vminh,DI_ftype_DIDI,2)
//
def int_hexagon_A2_vminh :
Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vminh">;
//
// BUILTIN_INFO(HEXAGON.A2_vmaxh,DI_ftype_DIDI,2)
//
def int_hexagon_A2_vmaxh :
Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vmaxh">;
//
// BUILTIN_INFO(HEXAGON.A2_vminuh,DI_ftype_DIDI,2)
//
def int_hexagon_A2_vminuh :
Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vminuh">;
//
// BUILTIN_INFO(HEXAGON.A2_vmaxuh,DI_ftype_DIDI,2)
//
def int_hexagon_A2_vmaxuh :
Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vmaxuh">;
//
// BUILTIN_INFO(HEXAGON.A2_vminw,DI_ftype_DIDI,2)
//
def int_hexagon_A2_vminw :
Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vminw">;
//
// BUILTIN_INFO(HEXAGON.A2_vmaxw,DI_ftype_DIDI,2)
//
def int_hexagon_A2_vmaxw :
Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vmaxw">;
//
// BUILTIN_INFO(HEXAGON.A2_vminuw,DI_ftype_DIDI,2)
//
def int_hexagon_A2_vminuw :
Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vminuw">;
//
// BUILTIN_INFO(HEXAGON.A2_vmaxuw,DI_ftype_DIDI,2)
//
def int_hexagon_A2_vmaxuw :
Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vmaxuw">;
//
// BUILTIN_INFO(HEXAGON.A4_modwrapu,SI_ftype_SISI,2)
//
def int_hexagon_A4_modwrapu :
Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_modwrapu">;
//
// BUILTIN_INFO(HEXAGON.F2_sfadd,SF_ftype_SFSF,2)
//
def int_hexagon_F2_sfadd :
Hexagon_sf_sfsf_Intrinsic<"HEXAGON_F2_sfadd">;
//
// BUILTIN_INFO(HEXAGON.F2_sfsub,SF_ftype_SFSF,2)
//
def int_hexagon_F2_sfsub :
Hexagon_sf_sfsf_Intrinsic<"HEXAGON_F2_sfsub">;
//
// BUILTIN_INFO(HEXAGON.F2_sfmpy,SF_ftype_SFSF,2)
//
def int_hexagon_F2_sfmpy :
Hexagon_sf_sfsf_Intrinsic<"HEXAGON_F2_sfmpy">;
//
// BUILTIN_INFO(HEXAGON.F2_sffma,SF_ftype_SFSFSF,3)
//
def int_hexagon_F2_sffma :
Hexagon_sf_sfsfsf_Intrinsic<"HEXAGON_F2_sffma">;
//
// BUILTIN_INFO(HEXAGON.F2_sffma_sc,SF_ftype_SFSFSFQI,4)
//
def int_hexagon_F2_sffma_sc :
Hexagon_sf_sfsfsfqi_Intrinsic<"HEXAGON_F2_sffma_sc">;
//
// BUILTIN_INFO(HEXAGON.F2_sffms,SF_ftype_SFSFSF,3)
//
def int_hexagon_F2_sffms :
Hexagon_sf_sfsfsf_Intrinsic<"HEXAGON_F2_sffms">;
//
// BUILTIN_INFO(HEXAGON.F2_sffma_lib,SF_ftype_SFSFSF,3)
//
def int_hexagon_F2_sffma_lib :
Hexagon_sf_sfsfsf_Intrinsic<"HEXAGON_F2_sffma_lib">;
//
// BUILTIN_INFO(HEXAGON.F2_sffms_lib,SF_ftype_SFSFSF,3)
//
def int_hexagon_F2_sffms_lib :
Hexagon_sf_sfsfsf_Intrinsic<"HEXAGON_F2_sffms_lib">;
//
// BUILTIN_INFO(HEXAGON.F2_sfcmpeq,QI_ftype_SFSF,2)
//
def int_hexagon_F2_sfcmpeq :
Hexagon_qi_sfsf_Intrinsic<"HEXAGON_F2_sfcmpeq">;
//
// BUILTIN_INFO(HEXAGON.F2_sfcmpgt,QI_ftype_SFSF,2)
//
def int_hexagon_F2_sfcmpgt :
Hexagon_qi_sfsf_Intrinsic<"HEXAGON_F2_sfcmpgt">;
//
// BUILTIN_INFO(HEXAGON.F2_sfcmpge,QI_ftype_SFSF,2)
//
def int_hexagon_F2_sfcmpge :
Hexagon_qi_sfsf_Intrinsic<"HEXAGON_F2_sfcmpge">;
//
// BUILTIN_INFO(HEXAGON.F2_sfcmpuo,QI_ftype_SFSF,2)
//
def int_hexagon_F2_sfcmpuo :
Hexagon_qi_sfsf_Intrinsic<"HEXAGON_F2_sfcmpuo">;
//
// BUILTIN_INFO(HEXAGON.F2_sfmax,SF_ftype_SFSF,2)
//
def int_hexagon_F2_sfmax :
Hexagon_sf_sfsf_Intrinsic<"HEXAGON_F2_sfmax">;
//
// BUILTIN_INFO(HEXAGON.F2_sfmin,SF_ftype_SFSF,2)
//
def int_hexagon_F2_sfmin :
Hexagon_sf_sfsf_Intrinsic<"HEXAGON_F2_sfmin">;
//
// BUILTIN_INFO(HEXAGON.F2_sfclass,QI_ftype_SFSI,2)
//
def int_hexagon_F2_sfclass :
Hexagon_qi_sfsi_Intrinsic<"HEXAGON_F2_sfclass">;
//
// BUILTIN_INFO(HEXAGON.F2_sfimm_p,SF_ftype_SI,1)
//
def int_hexagon_F2_sfimm_p :
Hexagon_sf_si_Intrinsic<"HEXAGON_F2_sfimm_p">;
//
// BUILTIN_INFO(HEXAGON.F2_sfimm_n,SF_ftype_SI,1)
//
def int_hexagon_F2_sfimm_n :
Hexagon_sf_si_Intrinsic<"HEXAGON_F2_sfimm_n">;
//
// BUILTIN_INFO(HEXAGON.F2_sffixupn,SF_ftype_SFSF,2)
//
def int_hexagon_F2_sffixupn :
Hexagon_sf_sfsf_Intrinsic<"HEXAGON_F2_sffixupn">;
//
// BUILTIN_INFO(HEXAGON.F2_sffixupd,SF_ftype_SFSF,2)
//
def int_hexagon_F2_sffixupd :
Hexagon_sf_sfsf_Intrinsic<"HEXAGON_F2_sffixupd">;
//
// BUILTIN_INFO(HEXAGON.F2_sffixupr,SF_ftype_SF,1)
//
def int_hexagon_F2_sffixupr :
Hexagon_sf_sf_Intrinsic<"HEXAGON_F2_sffixupr">;
//
// BUILTIN_INFO(HEXAGON.F2_dfadd,DF_ftype_DFDF,2)
//
def int_hexagon_F2_dfadd :
Hexagon_df_dfdf_Intrinsic<"HEXAGON_F2_dfadd">;
//
// BUILTIN_INFO(HEXAGON.F2_dfsub,DF_ftype_DFDF,2)
//
def int_hexagon_F2_dfsub :
Hexagon_df_dfdf_Intrinsic<"HEXAGON_F2_dfsub">;
//
// BUILTIN_INFO(HEXAGON.F2_dfmpy,DF_ftype_DFDF,2)
//
def int_hexagon_F2_dfmpy :
Hexagon_df_dfdf_Intrinsic<"HEXAGON_F2_dfmpy">;
//
// BUILTIN_INFO(HEXAGON.F2_dffma,DF_ftype_DFDFDF,3)
//
def int_hexagon_F2_dffma :
Hexagon_df_dfdfdf_Intrinsic<"HEXAGON_F2_dffma">;
//
// BUILTIN_INFO(HEXAGON.F2_dffms,DF_ftype_DFDFDF,3)
//
def int_hexagon_F2_dffms :
Hexagon_df_dfdfdf_Intrinsic<"HEXAGON_F2_dffms">;
//
// BUILTIN_INFO(HEXAGON.F2_dffma_lib,DF_ftype_DFDFDF,3)
//
def int_hexagon_F2_dffma_lib :
Hexagon_df_dfdfdf_Intrinsic<"HEXAGON_F2_dffma_lib">;
//
// BUILTIN_INFO(HEXAGON.F2_dffms_lib,DF_ftype_DFDFDF,3)
//
def int_hexagon_F2_dffms_lib :
Hexagon_df_dfdfdf_Intrinsic<"HEXAGON_F2_dffms_lib">;
//
// BUILTIN_INFO(HEXAGON.F2_dffma_sc,DF_ftype_DFDFDFQI,4)
//
def int_hexagon_F2_dffma_sc :
Hexagon_df_dfdfdfqi_Intrinsic<"HEXAGON_F2_dffma_sc">;
//
// BUILTIN_INFO(HEXAGON.F2_dfmax,DF_ftype_DFDF,2)
//
def int_hexagon_F2_dfmax :
Hexagon_df_dfdf_Intrinsic<"HEXAGON_F2_dfmax">;
//
// BUILTIN_INFO(HEXAGON.F2_dfmin,DF_ftype_DFDF,2)
//
def int_hexagon_F2_dfmin :
Hexagon_df_dfdf_Intrinsic<"HEXAGON_F2_dfmin">;
//
// BUILTIN_INFO(HEXAGON.F2_dfcmpeq,QI_ftype_DFDF,2)
//
def int_hexagon_F2_dfcmpeq :
Hexagon_qi_dfdf_Intrinsic<"HEXAGON_F2_dfcmpeq">;
//
// BUILTIN_INFO(HEXAGON.F2_dfcmpgt,QI_ftype_DFDF,2)
//
def int_hexagon_F2_dfcmpgt :
Hexagon_qi_dfdf_Intrinsic<"HEXAGON_F2_dfcmpgt">;
//
// BUILTIN_INFO(HEXAGON.F2_dfcmpge,QI_ftype_DFDF,2)
//
def int_hexagon_F2_dfcmpge :
Hexagon_qi_dfdf_Intrinsic<"HEXAGON_F2_dfcmpge">;
//
// BUILTIN_INFO(HEXAGON.F2_dfcmpuo,QI_ftype_DFDF,2)
//
def int_hexagon_F2_dfcmpuo :
Hexagon_qi_dfdf_Intrinsic<"HEXAGON_F2_dfcmpuo">;
//
// BUILTIN_INFO(HEXAGON.F2_dfclass,QI_ftype_DFSI,2)
//
def int_hexagon_F2_dfclass :
Hexagon_qi_dfsi_Intrinsic<"HEXAGON_F2_dfclass">;
//
// BUILTIN_INFO(HEXAGON.F2_dfimm_p,DF_ftype_SI,1)
//
def int_hexagon_F2_dfimm_p :
Hexagon_df_si_Intrinsic<"HEXAGON_F2_dfimm_p">;
//
// BUILTIN_INFO(HEXAGON.F2_dfimm_n,DF_ftype_SI,1)
//
def int_hexagon_F2_dfimm_n :
Hexagon_df_si_Intrinsic<"HEXAGON_F2_dfimm_n">;
//
// BUILTIN_INFO(HEXAGON.F2_dffixupn,DF_ftype_DFDF,2)
//
def int_hexagon_F2_dffixupn :
Hexagon_df_dfdf_Intrinsic<"HEXAGON_F2_dffixupn">;
//
// BUILTIN_INFO(HEXAGON.F2_dffixupd,DF_ftype_DFDF,2)
//
def int_hexagon_F2_dffixupd :
Hexagon_df_dfdf_Intrinsic<"HEXAGON_F2_dffixupd">;
//
// BUILTIN_INFO(HEXAGON.F2_dffixupr,DF_ftype_DF,1)
//
def int_hexagon_F2_dffixupr :
Hexagon_df_df_Intrinsic<"HEXAGON_F2_dffixupr">;
//
// BUILTIN_INFO(HEXAGON.F2_conv_sf2df,DF_ftype_SF,1)
//
def int_hexagon_F2_conv_sf2df :
Hexagon_df_sf_Intrinsic<"HEXAGON_F2_conv_sf2df">;
//
// BUILTIN_INFO(HEXAGON.F2_conv_df2sf,SF_ftype_DF,1)
//
def int_hexagon_F2_conv_df2sf :
Hexagon_sf_df_Intrinsic<"HEXAGON_F2_conv_df2sf">;
//
// BUILTIN_INFO(HEXAGON.F2_conv_uw2sf,SF_ftype_SI,1)
//
def int_hexagon_F2_conv_uw2sf :
Hexagon_sf_si_Intrinsic<"HEXAGON_F2_conv_uw2sf">;
//
// BUILTIN_INFO(HEXAGON.F2_conv_uw2df,DF_ftype_SI,1)
//
def int_hexagon_F2_conv_uw2df :
Hexagon_df_si_Intrinsic<"HEXAGON_F2_conv_uw2df">;
//
// BUILTIN_INFO(HEXAGON.F2_conv_w2sf,SF_ftype_SI,1)
//
def int_hexagon_F2_conv_w2sf :
Hexagon_sf_si_Intrinsic<"HEXAGON_F2_conv_w2sf">;
//
// BUILTIN_INFO(HEXAGON.F2_conv_w2df,DF_ftype_SI,1)
//
def int_hexagon_F2_conv_w2df :
Hexagon_df_si_Intrinsic<"HEXAGON_F2_conv_w2df">;
//
// BUILTIN_INFO(HEXAGON.F2_conv_ud2sf,SF_ftype_DI,1)
//
def int_hexagon_F2_conv_ud2sf :
Hexagon_sf_di_Intrinsic<"HEXAGON_F2_conv_ud2sf">;
//
// BUILTIN_INFO(HEXAGON.F2_conv_ud2df,DF_ftype_DI,1)
//
def int_hexagon_F2_conv_ud2df :
Hexagon_df_di_Intrinsic<"HEXAGON_F2_conv_ud2df">;
//
// BUILTIN_INFO(HEXAGON.F2_conv_d2sf,SF_ftype_DI,1)
//
def int_hexagon_F2_conv_d2sf :
Hexagon_sf_di_Intrinsic<"HEXAGON_F2_conv_d2sf">;
//
// BUILTIN_INFO(HEXAGON.F2_conv_d2df,DF_ftype_DI,1)
//
def int_hexagon_F2_conv_d2df :
Hexagon_df_di_Intrinsic<"HEXAGON_F2_conv_d2df">;
//
// BUILTIN_INFO(HEXAGON.F2_conv_sf2uw,SI_ftype_SF,1)
//
def int_hexagon_F2_conv_sf2uw :
Hexagon_si_sf_Intrinsic<"HEXAGON_F2_conv_sf2uw">;
//
// BUILTIN_INFO(HEXAGON.F2_conv_sf2w,SI_ftype_SF,1)
//
def int_hexagon_F2_conv_sf2w :
Hexagon_si_sf_Intrinsic<"HEXAGON_F2_conv_sf2w">;
//
// BUILTIN_INFO(HEXAGON.F2_conv_sf2ud,DI_ftype_SF,1)
//
def int_hexagon_F2_conv_sf2ud :
Hexagon_di_sf_Intrinsic<"HEXAGON_F2_conv_sf2ud">;
//
// BUILTIN_INFO(HEXAGON.F2_conv_sf2d,DI_ftype_SF,1)
//
def int_hexagon_F2_conv_sf2d :
Hexagon_di_sf_Intrinsic<"HEXAGON_F2_conv_sf2d">;
//
// BUILTIN_INFO(HEXAGON.F2_conv_df2uw,SI_ftype_DF,1)
//
def int_hexagon_F2_conv_df2uw :
Hexagon_si_df_Intrinsic<"HEXAGON_F2_conv_df2uw">;
//
// BUILTIN_INFO(HEXAGON.F2_conv_df2w,SI_ftype_DF,1)
//
def int_hexagon_F2_conv_df2w :
Hexagon_si_df_Intrinsic<"HEXAGON_F2_conv_df2w">;
//
// BUILTIN_INFO(HEXAGON.F2_conv_df2ud,DI_ftype_DF,1)
//
def int_hexagon_F2_conv_df2ud :
Hexagon_di_df_Intrinsic<"HEXAGON_F2_conv_df2ud">;
//
// BUILTIN_INFO(HEXAGON.F2_conv_df2d,DI_ftype_DF,1)
//
def int_hexagon_F2_conv_df2d :
Hexagon_di_df_Intrinsic<"HEXAGON_F2_conv_df2d">;
//
// BUILTIN_INFO(HEXAGON.F2_conv_sf2uw_chop,SI_ftype_SF,1)
//
def int_hexagon_F2_conv_sf2uw_chop :
Hexagon_si_sf_Intrinsic<"HEXAGON_F2_conv_sf2uw_chop">;
//
// BUILTIN_INFO(HEXAGON.F2_conv_sf2w_chop,SI_ftype_SF,1)
//
def int_hexagon_F2_conv_sf2w_chop :
Hexagon_si_sf_Intrinsic<"HEXAGON_F2_conv_sf2w_chop">;
//
// BUILTIN_INFO(HEXAGON.F2_conv_sf2ud_chop,DI_ftype_SF,1)
//
def int_hexagon_F2_conv_sf2ud_chop :
Hexagon_di_sf_Intrinsic<"HEXAGON_F2_conv_sf2ud_chop">;
//
// BUILTIN_INFO(HEXAGON.F2_conv_sf2d_chop,DI_ftype_SF,1)
//
def int_hexagon_F2_conv_sf2d_chop :
Hexagon_di_sf_Intrinsic<"HEXAGON_F2_conv_sf2d_chop">;
//
// BUILTIN_INFO(HEXAGON.F2_conv_df2uw_chop,SI_ftype_DF,1)
//
def int_hexagon_F2_conv_df2uw_chop :
Hexagon_si_df_Intrinsic<"HEXAGON_F2_conv_df2uw_chop">;
//
// BUILTIN_INFO(HEXAGON.F2_conv_df2w_chop,SI_ftype_DF,1)
//
def int_hexagon_F2_conv_df2w_chop :
Hexagon_si_df_Intrinsic<"HEXAGON_F2_conv_df2w_chop">;
//
// BUILTIN_INFO(HEXAGON.F2_conv_df2ud_chop,DI_ftype_DF,1)
//
def int_hexagon_F2_conv_df2ud_chop :
Hexagon_di_df_Intrinsic<"HEXAGON_F2_conv_df2ud_chop">;
//
// BUILTIN_INFO(HEXAGON.F2_conv_df2d_chop,DI_ftype_DF,1)
//
def int_hexagon_F2_conv_df2d_chop :
Hexagon_di_df_Intrinsic<"HEXAGON_F2_conv_df2d_chop">;
//
// BUILTIN_INFO(HEXAGON.S2_asr_r_r,SI_ftype_SISI,2)
//
def int_hexagon_S2_asr_r_r :
Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_asr_r_r">;
//
// BUILTIN_INFO(HEXAGON.S2_asl_r_r,SI_ftype_SISI,2)
//
def int_hexagon_S2_asl_r_r :
Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_asl_r_r">;
//
// BUILTIN_INFO(HEXAGON.S2_lsr_r_r,SI_ftype_SISI,2)
//
def int_hexagon_S2_lsr_r_r :
Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_lsr_r_r">;
//
// BUILTIN_INFO(HEXAGON.S2_lsl_r_r,SI_ftype_SISI,2)
//
def int_hexagon_S2_lsl_r_r :
Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_lsl_r_r">;
//
// BUILTIN_INFO(HEXAGON.S2_asr_r_p,DI_ftype_DISI,2)
//
def int_hexagon_S2_asr_r_p :
Hexagon_di_disi_Intrinsic<"HEXAGON_S2_asr_r_p">;
//
// BUILTIN_INFO(HEXAGON.S2_asl_r_p,DI_ftype_DISI,2)
//
def int_hexagon_S2_asl_r_p :
Hexagon_di_disi_Intrinsic<"HEXAGON_S2_asl_r_p">;
//
// BUILTIN_INFO(HEXAGON.S2_lsr_r_p,DI_ftype_DISI,2)
//
def int_hexagon_S2_lsr_r_p :
Hexagon_di_disi_Intrinsic<"HEXAGON_S2_lsr_r_p">;
//
// BUILTIN_INFO(HEXAGON.S2_lsl_r_p,DI_ftype_DISI,2)
//
def int_hexagon_S2_lsl_r_p :
Hexagon_di_disi_Intrinsic<"HEXAGON_S2_lsl_r_p">;
//
// BUILTIN_INFO(HEXAGON.S2_asr_r_r_acc,SI_ftype_SISISI,3)
// //
def int_hexagon_S2_asr_r_r_acc : def int_hexagon_S2_asr_r_r_acc :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.S2.asr.r.r.acc">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_asr_r_r_acc">;
// //
// BUILTIN_INFO(HEXAGON.S2_asl_r_r_acc,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.S2_asl_r_r_acc,SI_ftype_SISISI,3)
// //
def int_hexagon_S2_asl_r_r_acc : def int_hexagon_S2_asl_r_r_acc :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.S2.asl.r.r.acc">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_asl_r_r_acc">;
// //
// BUILTIN_INFO(HEXAGON.S2_lsr_r_r_acc,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.S2_lsr_r_r_acc,SI_ftype_SISISI,3)
// //
def int_hexagon_S2_lsr_r_r_acc : def int_hexagon_S2_lsr_r_r_acc :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.S2.lsr.r.r.acc">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_lsr_r_r_acc">;
// //
// BUILTIN_INFO(HEXAGON.S2_lsl_r_r_acc,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.S2_lsl_r_r_acc,SI_ftype_SISISI,3)
// //
def int_hexagon_S2_lsl_r_r_acc : def int_hexagon_S2_lsl_r_r_acc :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.S2.lsl.r.r.acc">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_lsl_r_r_acc">;
// //
// BUILTIN_INFO(HEXAGON.S2_asr_r_p_acc,DI_ftype_DIDISI,3) // BUILTIN_INFO(HEXAGON.S2_asr_r_p_acc,DI_ftype_DIDISI,3)
// //
def int_hexagon_S2_asr_r_p_acc : def int_hexagon_S2_asr_r_p_acc :
Hexagon_di_didisi_Intrinsic<"HEXAGON.S2.asr.r.p.acc">; Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asr_r_p_acc">;
// //
// BUILTIN_INFO(HEXAGON.S2_asl_r_p_acc,DI_ftype_DIDISI,3) // BUILTIN_INFO(HEXAGON.S2_asl_r_p_acc,DI_ftype_DIDISI,3)
// //
def int_hexagon_S2_asl_r_p_acc : def int_hexagon_S2_asl_r_p_acc :
Hexagon_di_didisi_Intrinsic<"HEXAGON.S2.asl.r.p.acc">; Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asl_r_p_acc">;
// //
// BUILTIN_INFO(HEXAGON.S2_lsr_r_p_acc,DI_ftype_DIDISI,3) // BUILTIN_INFO(HEXAGON.S2_lsr_r_p_acc,DI_ftype_DIDISI,3)
// //
def int_hexagon_S2_lsr_r_p_acc : def int_hexagon_S2_lsr_r_p_acc :
Hexagon_di_didisi_Intrinsic<"HEXAGON.S2.lsr.r.p.acc">; Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_lsr_r_p_acc">;
// //
// BUILTIN_INFO(HEXAGON.S2_lsl_r_p_acc,DI_ftype_DIDISI,3) // BUILTIN_INFO(HEXAGON.S2_lsl_r_p_acc,DI_ftype_DIDISI,3)
// //
def int_hexagon_S2_lsl_r_p_acc : def int_hexagon_S2_lsl_r_p_acc :
Hexagon_di_didisi_Intrinsic<"HEXAGON.S2.lsl.r.p.acc">; Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_lsl_r_p_acc">;
// //
// BUILTIN_INFO(HEXAGON.S2_asr_r_r_nac,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.S2_asr_r_r_nac,SI_ftype_SISISI,3)
// //
def int_hexagon_S2_asr_r_r_nac : def int_hexagon_S2_asr_r_r_nac :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.S2.asr.r.r.nac">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_asr_r_r_nac">;
// //
// BUILTIN_INFO(HEXAGON.S2_asl_r_r_nac,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.S2_asl_r_r_nac,SI_ftype_SISISI,3)
// //
def int_hexagon_S2_asl_r_r_nac : def int_hexagon_S2_asl_r_r_nac :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.S2.asl.r.r.nac">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_asl_r_r_nac">;
// //
// BUILTIN_INFO(HEXAGON.S2_lsr_r_r_nac,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.S2_lsr_r_r_nac,SI_ftype_SISISI,3)
// //
def int_hexagon_S2_lsr_r_r_nac : def int_hexagon_S2_lsr_r_r_nac :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.S2.lsr.r.r.nac">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_lsr_r_r_nac">;
// //
// BUILTIN_INFO(HEXAGON.S2_lsl_r_r_nac,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.S2_lsl_r_r_nac,SI_ftype_SISISI,3)
// //
def int_hexagon_S2_lsl_r_r_nac : def int_hexagon_S2_lsl_r_r_nac :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.S2.lsl.r.r.nac">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_lsl_r_r_nac">;
// //
// BUILTIN_INFO(HEXAGON.S2_asr_r_p_nac,DI_ftype_DIDISI,3) // BUILTIN_INFO(HEXAGON.S2_asr_r_p_nac,DI_ftype_DIDISI,3)
// //
def int_hexagon_S2_asr_r_p_nac : def int_hexagon_S2_asr_r_p_nac :
Hexagon_di_didisi_Intrinsic<"HEXAGON.S2.asr.r.p.nac">; Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asr_r_p_nac">;
// //
// BUILTIN_INFO(HEXAGON.S2_asl_r_p_nac,DI_ftype_DIDISI,3) // BUILTIN_INFO(HEXAGON.S2_asl_r_p_nac,DI_ftype_DIDISI,3)
// //
def int_hexagon_S2_asl_r_p_nac : def int_hexagon_S2_asl_r_p_nac :
Hexagon_di_didisi_Intrinsic<"HEXAGON.S2.asl.r.p.nac">; Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asl_r_p_nac">;
// //
// BUILTIN_INFO(HEXAGON.S2_lsr_r_p_nac,DI_ftype_DIDISI,3) // BUILTIN_INFO(HEXAGON.S2_lsr_r_p_nac,DI_ftype_DIDISI,3)
// //
def int_hexagon_S2_lsr_r_p_nac : def int_hexagon_S2_lsr_r_p_nac :
Hexagon_di_didisi_Intrinsic<"HEXAGON.S2.lsr.r.p.nac">; Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_lsr_r_p_nac">;
// //
// BUILTIN_INFO(HEXAGON.S2_lsl_r_p_nac,DI_ftype_DIDISI,3) // BUILTIN_INFO(HEXAGON.S2_lsl_r_p_nac,DI_ftype_DIDISI,3)
// //
def int_hexagon_S2_lsl_r_p_nac : def int_hexagon_S2_lsl_r_p_nac :
Hexagon_di_didisi_Intrinsic<"HEXAGON.S2.lsl.r.p.nac">; Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_lsl_r_p_nac">;
// //
// BUILTIN_INFO(HEXAGON.S2_asr_r_r_and,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.S2_asr_r_r_and,SI_ftype_SISISI,3)
// //
def int_hexagon_S2_asr_r_r_and : def int_hexagon_S2_asr_r_r_and :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.S2.asr.r.r.and">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_asr_r_r_and">;
// //
// BUILTIN_INFO(HEXAGON.S2_asl_r_r_and,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.S2_asl_r_r_and,SI_ftype_SISISI,3)
// //
def int_hexagon_S2_asl_r_r_and : def int_hexagon_S2_asl_r_r_and :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.S2.asl.r.r.and">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_asl_r_r_and">;
// //
// BUILTIN_INFO(HEXAGON.S2_lsr_r_r_and,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.S2_lsr_r_r_and,SI_ftype_SISISI,3)
// //
def int_hexagon_S2_lsr_r_r_and : def int_hexagon_S2_lsr_r_r_and :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.S2.lsr.r.r.and">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_lsr_r_r_and">;
// //
// BUILTIN_INFO(HEXAGON.S2_lsl_r_r_and,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.S2_lsl_r_r_and,SI_ftype_SISISI,3)
// //
def int_hexagon_S2_lsl_r_r_and : def int_hexagon_S2_lsl_r_r_and :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.S2.lsl.r.r.and">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_lsl_r_r_and">;
// //
// BUILTIN_INFO(HEXAGON.S2_asr_r_r_or,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.S2_asr_r_r_or,SI_ftype_SISISI,3)
// //
def int_hexagon_S2_asr_r_r_or : def int_hexagon_S2_asr_r_r_or :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.S2.asr.r.r.or">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_asr_r_r_or">;
// //
// BUILTIN_INFO(HEXAGON.S2_asl_r_r_or,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.S2_asl_r_r_or,SI_ftype_SISISI,3)
// //
def int_hexagon_S2_asl_r_r_or : def int_hexagon_S2_asl_r_r_or :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.S2.asl.r.r.or">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_asl_r_r_or">;
// //
// BUILTIN_INFO(HEXAGON.S2_lsr_r_r_or,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.S2_lsr_r_r_or,SI_ftype_SISISI,3)
// //
def int_hexagon_S2_lsr_r_r_or : def int_hexagon_S2_lsr_r_r_or :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.S2.lsr.r.r.or">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_lsr_r_r_or">;
// //
// BUILTIN_INFO(HEXAGON.S2_lsl_r_r_or,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.S2_lsl_r_r_or,SI_ftype_SISISI,3)
// //
def int_hexagon_S2_lsl_r_r_or : def int_hexagon_S2_lsl_r_r_or :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.S2.lsl.r.r.or">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_lsl_r_r_or">;
// //
// BUILTIN_INFO(HEXAGON.S2_asr_r_p_and,DI_ftype_DIDISI,3) // BUILTIN_INFO(HEXAGON.S2_asr_r_p_and,DI_ftype_DIDISI,3)
// //
def int_hexagon_S2_asr_r_p_and : def int_hexagon_S2_asr_r_p_and :
Hexagon_di_didisi_Intrinsic<"HEXAGON.S2.asr.r.p.and">; Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asr_r_p_and">;
// //
// BUILTIN_INFO(HEXAGON.S2_asl_r_p_and,DI_ftype_DIDISI,3) // BUILTIN_INFO(HEXAGON.S2_asl_r_p_and,DI_ftype_DIDISI,3)
// //
def int_hexagon_S2_asl_r_p_and : def int_hexagon_S2_asl_r_p_and :
Hexagon_di_didisi_Intrinsic<"HEXAGON.S2.asl.r.p.and">; Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asl_r_p_and">;
// //
// BUILTIN_INFO(HEXAGON.S2_lsr_r_p_and,DI_ftype_DIDISI,3) // BUILTIN_INFO(HEXAGON.S2_lsr_r_p_and,DI_ftype_DIDISI,3)
// //
def int_hexagon_S2_lsr_r_p_and : def int_hexagon_S2_lsr_r_p_and :
Hexagon_di_didisi_Intrinsic<"HEXAGON.S2.lsr.r.p.and">; Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_lsr_r_p_and">;
// //
// BUILTIN_INFO(HEXAGON.S2_lsl_r_p_and,DI_ftype_DIDISI,3) // BUILTIN_INFO(HEXAGON.S2_lsl_r_p_and,DI_ftype_DIDISI,3)
// //
def int_hexagon_S2_lsl_r_p_and : def int_hexagon_S2_lsl_r_p_and :
Hexagon_di_didisi_Intrinsic<"HEXAGON.S2.lsl.r.p.and">; Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_lsl_r_p_and">;
// //
// BUILTIN_INFO(HEXAGON.S2_asr_r_p_or,DI_ftype_DIDISI,3) // BUILTIN_INFO(HEXAGON.S2_asr_r_p_or,DI_ftype_DIDISI,3)
// //
def int_hexagon_S2_asr_r_p_or : def int_hexagon_S2_asr_r_p_or :
Hexagon_di_didisi_Intrinsic<"HEXAGON.S2.asr.r.p.or">; Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asr_r_p_or">;
// //
// BUILTIN_INFO(HEXAGON.S2_asl_r_p_or,DI_ftype_DIDISI,3) // BUILTIN_INFO(HEXAGON.S2_asl_r_p_or,DI_ftype_DIDISI,3)
// //
def int_hexagon_S2_asl_r_p_or : def int_hexagon_S2_asl_r_p_or :
Hexagon_di_didisi_Intrinsic<"HEXAGON.S2.asl.r.p.or">; Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asl_r_p_or">;
// //
// BUILTIN_INFO(HEXAGON.S2_lsr_r_p_or,DI_ftype_DIDISI,3) // BUILTIN_INFO(HEXAGON.S2_lsr_r_p_or,DI_ftype_DIDISI,3)
// //
def int_hexagon_S2_lsr_r_p_or : def int_hexagon_S2_lsr_r_p_or :
Hexagon_di_didisi_Intrinsic<"HEXAGON.S2.lsr.r.p.or">; Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_lsr_r_p_or">;
// //
// BUILTIN_INFO(HEXAGON.S2_lsl_r_p_or,DI_ftype_DIDISI,3) // BUILTIN_INFO(HEXAGON.S2_lsl_r_p_or,DI_ftype_DIDISI,3)
// //
def int_hexagon_S2_lsl_r_p_or : def int_hexagon_S2_lsl_r_p_or :
Hexagon_di_didisi_Intrinsic<"HEXAGON.S2.lsl.r.p.or">; Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_lsl_r_p_or">;
//
// BUILTIN_INFO(HEXAGON.S2_asr_r_p_xor,DI_ftype_DIDISI,3)
//
def int_hexagon_S2_asr_r_p_xor :
Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asr_r_p_xor">;
//
// BUILTIN_INFO(HEXAGON.S2_asl_r_p_xor,DI_ftype_DIDISI,3)
//
def int_hexagon_S2_asl_r_p_xor :
Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asl_r_p_xor">;
//
// BUILTIN_INFO(HEXAGON.S2_lsr_r_p_xor,DI_ftype_DIDISI,3)
//
def int_hexagon_S2_lsr_r_p_xor :
Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_lsr_r_p_xor">;
//
// BUILTIN_INFO(HEXAGON.S2_lsl_r_p_xor,DI_ftype_DIDISI,3)
//
def int_hexagon_S2_lsl_r_p_xor :
Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_lsl_r_p_xor">;
// //
// BUILTIN_INFO(HEXAGON.S2_asr_r_r_sat,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.S2_asr_r_r_sat,SI_ftype_SISI,2)
// //
def int_hexagon_S2_asr_r_r_sat : def int_hexagon_S2_asr_r_r_sat :
Hexagon_si_sisi_Intrinsic<"HEXAGON.S2.asr.r.r.sat">; Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_asr_r_r_sat">;
// //
// BUILTIN_INFO(HEXAGON.S2_asl_r_r_sat,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.S2_asl_r_r_sat,SI_ftype_SISI,2)
// //
def int_hexagon_S2_asl_r_r_sat : def int_hexagon_S2_asl_r_r_sat :
Hexagon_si_sisi_Intrinsic<"HEXAGON.S2.asl.r.r.sat">; Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_asl_r_r_sat">;
// //
// BUILTIN_INFO(HEXAGON.S2_asr_i_r,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.S2_asr_i_r,SI_ftype_SISI,2)
// //
def int_hexagon_S2_asr_i_r : def int_hexagon_S2_asr_i_r :
Hexagon_si_sisi_Intrinsic<"HEXAGON.S2.asr.i.r">; Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_asr_i_r">;
// //
// BUILTIN_INFO(HEXAGON.S2_lsr_i_r,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.S2_lsr_i_r,SI_ftype_SISI,2)
// //
def int_hexagon_S2_lsr_i_r : def int_hexagon_S2_lsr_i_r :
Hexagon_si_sisi_Intrinsic<"HEXAGON.S2.lsr.i.r">; Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_lsr_i_r">;
// //
// BUILTIN_INFO(HEXAGON.S2_asl_i_r,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.S2_asl_i_r,SI_ftype_SISI,2)
// //
def int_hexagon_S2_asl_i_r : def int_hexagon_S2_asl_i_r :
Hexagon_si_sisi_Intrinsic<"HEXAGON.S2.asl.i.r">; Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_asl_i_r">;
// //
// BUILTIN_INFO(HEXAGON.S2_asr_i_p,DI_ftype_DISI,2) // BUILTIN_INFO(HEXAGON.S2_asr_i_p,DI_ftype_DISI,2)
// //
def int_hexagon_S2_asr_i_p : def int_hexagon_S2_asr_i_p :
Hexagon_di_disi_Intrinsic<"HEXAGON.S2.asr.i.p">; Hexagon_di_disi_Intrinsic<"HEXAGON_S2_asr_i_p">;
// //
// BUILTIN_INFO(HEXAGON.S2_lsr_i_p,DI_ftype_DISI,2) // BUILTIN_INFO(HEXAGON.S2_lsr_i_p,DI_ftype_DISI,2)
// //
def int_hexagon_S2_lsr_i_p : def int_hexagon_S2_lsr_i_p :
Hexagon_di_disi_Intrinsic<"HEXAGON.S2.lsr.i.p">; Hexagon_di_disi_Intrinsic<"HEXAGON_S2_lsr_i_p">;
// //
// BUILTIN_INFO(HEXAGON.S2_asl_i_p,DI_ftype_DISI,2) // BUILTIN_INFO(HEXAGON.S2_asl_i_p,DI_ftype_DISI,2)
// //
def int_hexagon_S2_asl_i_p : def int_hexagon_S2_asl_i_p :
Hexagon_di_disi_Intrinsic<"HEXAGON.S2.asl.i.p">; Hexagon_di_disi_Intrinsic<"HEXAGON_S2_asl_i_p">;
// //
// BUILTIN_INFO(HEXAGON.S2_asr_i_r_acc,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.S2_asr_i_r_acc,SI_ftype_SISISI,3)
// //
def int_hexagon_S2_asr_i_r_acc : def int_hexagon_S2_asr_i_r_acc :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.S2.asr.i.r.acc">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_asr_i_r_acc">;
// //
// BUILTIN_INFO(HEXAGON.S2_lsr_i_r_acc,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.S2_lsr_i_r_acc,SI_ftype_SISISI,3)
// //
def int_hexagon_S2_lsr_i_r_acc : def int_hexagon_S2_lsr_i_r_acc :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.S2.lsr.i.r.acc">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_lsr_i_r_acc">;
// //
// BUILTIN_INFO(HEXAGON.S2_asl_i_r_acc,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.S2_asl_i_r_acc,SI_ftype_SISISI,3)
// //
def int_hexagon_S2_asl_i_r_acc : def int_hexagon_S2_asl_i_r_acc :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.S2.asl.i.r.acc">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_asl_i_r_acc">;
// //
// BUILTIN_INFO(HEXAGON.S2_asr_i_p_acc,DI_ftype_DIDISI,3) // BUILTIN_INFO(HEXAGON.S2_asr_i_p_acc,DI_ftype_DIDISI,3)
// //
def int_hexagon_S2_asr_i_p_acc : def int_hexagon_S2_asr_i_p_acc :
Hexagon_di_didisi_Intrinsic<"HEXAGON.S2.asr.i.p.acc">; Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asr_i_p_acc">;
// //
// BUILTIN_INFO(HEXAGON.S2_lsr_i_p_acc,DI_ftype_DIDISI,3) // BUILTIN_INFO(HEXAGON.S2_lsr_i_p_acc,DI_ftype_DIDISI,3)
// //
def int_hexagon_S2_lsr_i_p_acc : def int_hexagon_S2_lsr_i_p_acc :
Hexagon_di_didisi_Intrinsic<"HEXAGON.S2.lsr.i.p.acc">; Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_lsr_i_p_acc">;
// //
// BUILTIN_INFO(HEXAGON.S2_asl_i_p_acc,DI_ftype_DIDISI,3) // BUILTIN_INFO(HEXAGON.S2_asl_i_p_acc,DI_ftype_DIDISI,3)
// //
def int_hexagon_S2_asl_i_p_acc : def int_hexagon_S2_asl_i_p_acc :
Hexagon_di_didisi_Intrinsic<"HEXAGON.S2.asl.i.p.acc">; Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asl_i_p_acc">;
// //
// BUILTIN_INFO(HEXAGON.S2_asr_i_r_nac,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.S2_asr_i_r_nac,SI_ftype_SISISI,3)
// //
def int_hexagon_S2_asr_i_r_nac : def int_hexagon_S2_asr_i_r_nac :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.S2.asr.i.r.nac">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_asr_i_r_nac">;
// //
// BUILTIN_INFO(HEXAGON.S2_lsr_i_r_nac,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.S2_lsr_i_r_nac,SI_ftype_SISISI,3)
// //
def int_hexagon_S2_lsr_i_r_nac : def int_hexagon_S2_lsr_i_r_nac :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.S2.lsr.i.r.nac">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_lsr_i_r_nac">;
// //
// BUILTIN_INFO(HEXAGON.S2_asl_i_r_nac,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.S2_asl_i_r_nac,SI_ftype_SISISI,3)
// //
def int_hexagon_S2_asl_i_r_nac : def int_hexagon_S2_asl_i_r_nac :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.S2.asl.i.r.nac">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_asl_i_r_nac">;
// //
// BUILTIN_INFO(HEXAGON.S2_asr_i_p_nac,DI_ftype_DIDISI,3) // BUILTIN_INFO(HEXAGON.S2_asr_i_p_nac,DI_ftype_DIDISI,3)
// //
def int_hexagon_S2_asr_i_p_nac : def int_hexagon_S2_asr_i_p_nac :
Hexagon_di_didisi_Intrinsic<"HEXAGON.S2.asr.i.p.nac">; Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asr_i_p_nac">;
// //
// BUILTIN_INFO(HEXAGON.S2_lsr_i_p_nac,DI_ftype_DIDISI,3) // BUILTIN_INFO(HEXAGON.S2_lsr_i_p_nac,DI_ftype_DIDISI,3)
// //
def int_hexagon_S2_lsr_i_p_nac : def int_hexagon_S2_lsr_i_p_nac :
Hexagon_di_didisi_Intrinsic<"HEXAGON.S2.lsr.i.p.nac">; Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_lsr_i_p_nac">;
// //
// BUILTIN_INFO(HEXAGON.S2_asl_i_p_nac,DI_ftype_DIDISI,3) // BUILTIN_INFO(HEXAGON.S2_asl_i_p_nac,DI_ftype_DIDISI,3)
// //
def int_hexagon_S2_asl_i_p_nac : def int_hexagon_S2_asl_i_p_nac :
Hexagon_di_didisi_Intrinsic<"HEXAGON.S2.asl.i.p.nac">; Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asl_i_p_nac">;
// //
// BUILTIN_INFO(HEXAGON.S2_lsr_i_r_xacc,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.S2_lsr_i_r_xacc,SI_ftype_SISISI,3)
// //
def int_hexagon_S2_lsr_i_r_xacc : def int_hexagon_S2_lsr_i_r_xacc :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.S2.lsr.i.r.xacc">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_lsr_i_r_xacc">;
// //
// BUILTIN_INFO(HEXAGON.S2_asl_i_r_xacc,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.S2_asl_i_r_xacc,SI_ftype_SISISI,3)
// //
def int_hexagon_S2_asl_i_r_xacc : def int_hexagon_S2_asl_i_r_xacc :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.S2.asl.i.r.xacc">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_asl_i_r_xacc">;
// //
// BUILTIN_INFO(HEXAGON.S2_lsr_i_p_xacc,DI_ftype_DIDISI,3) // BUILTIN_INFO(HEXAGON.S2_lsr_i_p_xacc,DI_ftype_DIDISI,3)
// //
def int_hexagon_S2_lsr_i_p_xacc : def int_hexagon_S2_lsr_i_p_xacc :
Hexagon_di_didisi_Intrinsic<"HEXAGON.S2.lsr.i.p.xacc">; Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_lsr_i_p_xacc">;
// //
// BUILTIN_INFO(HEXAGON.S2_asl_i_p_xacc,DI_ftype_DIDISI,3) // BUILTIN_INFO(HEXAGON.S2_asl_i_p_xacc,DI_ftype_DIDISI,3)
// //
def int_hexagon_S2_asl_i_p_xacc : def int_hexagon_S2_asl_i_p_xacc :
Hexagon_di_didisi_Intrinsic<"HEXAGON.S2.asl.i.p.xacc">; Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asl_i_p_xacc">;
// //
// BUILTIN_INFO(HEXAGON.S2_asr_i_r_and,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.S2_asr_i_r_and,SI_ftype_SISISI,3)
// //
def int_hexagon_S2_asr_i_r_and : def int_hexagon_S2_asr_i_r_and :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.S2.asr.i.r.and">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_asr_i_r_and">;
// //
// BUILTIN_INFO(HEXAGON.S2_lsr_i_r_and,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.S2_lsr_i_r_and,SI_ftype_SISISI,3)
// //
def int_hexagon_S2_lsr_i_r_and : def int_hexagon_S2_lsr_i_r_and :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.S2.lsr.i.r.and">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_lsr_i_r_and">;
// //
// BUILTIN_INFO(HEXAGON.S2_asl_i_r_and,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.S2_asl_i_r_and,SI_ftype_SISISI,3)
// //
def int_hexagon_S2_asl_i_r_and : def int_hexagon_S2_asl_i_r_and :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.S2.asl.i.r.and">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_asl_i_r_and">;
// //
// BUILTIN_INFO(HEXAGON.S2_asr_i_r_or,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.S2_asr_i_r_or,SI_ftype_SISISI,3)
// //
def int_hexagon_S2_asr_i_r_or : def int_hexagon_S2_asr_i_r_or :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.S2.asr.i.r.or">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_asr_i_r_or">;
// //
// BUILTIN_INFO(HEXAGON.S2_lsr_i_r_or,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.S2_lsr_i_r_or,SI_ftype_SISISI,3)
// //
def int_hexagon_S2_lsr_i_r_or : def int_hexagon_S2_lsr_i_r_or :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.S2.lsr.i.r.or">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_lsr_i_r_or">;
// //
// BUILTIN_INFO(HEXAGON.S2_asl_i_r_or,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.S2_asl_i_r_or,SI_ftype_SISISI,3)
// //
def int_hexagon_S2_asl_i_r_or : def int_hexagon_S2_asl_i_r_or :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.S2.asl.i.r.or">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_asl_i_r_or">;
// //
// BUILTIN_INFO(HEXAGON.S2_asr_i_p_and,DI_ftype_DIDISI,3) // BUILTIN_INFO(HEXAGON.S2_asr_i_p_and,DI_ftype_DIDISI,3)
// //
def int_hexagon_S2_asr_i_p_and : def int_hexagon_S2_asr_i_p_and :
Hexagon_di_didisi_Intrinsic<"HEXAGON.S2.asr.i.p.and">; Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asr_i_p_and">;
// //
// BUILTIN_INFO(HEXAGON.S2_lsr_i_p_and,DI_ftype_DIDISI,3) // BUILTIN_INFO(HEXAGON.S2_lsr_i_p_and,DI_ftype_DIDISI,3)
// //
def int_hexagon_S2_lsr_i_p_and : def int_hexagon_S2_lsr_i_p_and :
Hexagon_di_didisi_Intrinsic<"HEXAGON.S2.lsr.i.p.and">; Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_lsr_i_p_and">;
// //
// BUILTIN_INFO(HEXAGON.S2_asl_i_p_and,DI_ftype_DIDISI,3) // BUILTIN_INFO(HEXAGON.S2_asl_i_p_and,DI_ftype_DIDISI,3)
// //
def int_hexagon_S2_asl_i_p_and : def int_hexagon_S2_asl_i_p_and :
Hexagon_di_didisi_Intrinsic<"HEXAGON.S2.asl.i.p.and">; Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asl_i_p_and">;
// //
// BUILTIN_INFO(HEXAGON.S2_asr_i_p_or,DI_ftype_DIDISI,3) // BUILTIN_INFO(HEXAGON.S2_asr_i_p_or,DI_ftype_DIDISI,3)
// //
def int_hexagon_S2_asr_i_p_or : def int_hexagon_S2_asr_i_p_or :
Hexagon_di_didisi_Intrinsic<"HEXAGON.S2.asr.i.p.or">; Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asr_i_p_or">;
// //
// BUILTIN_INFO(HEXAGON.S2_lsr_i_p_or,DI_ftype_DIDISI,3) // BUILTIN_INFO(HEXAGON.S2_lsr_i_p_or,DI_ftype_DIDISI,3)
// //
def int_hexagon_S2_lsr_i_p_or : def int_hexagon_S2_lsr_i_p_or :
Hexagon_di_didisi_Intrinsic<"HEXAGON.S2.lsr.i.p.or">; Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_lsr_i_p_or">;
// //
// BUILTIN_INFO(HEXAGON.S2_asl_i_p_or,DI_ftype_DIDISI,3) // BUILTIN_INFO(HEXAGON.S2_asl_i_p_or,DI_ftype_DIDISI,3)
// //
def int_hexagon_S2_asl_i_p_or : def int_hexagon_S2_asl_i_p_or :
Hexagon_di_didisi_Intrinsic<"HEXAGON.S2.asl.i.p.or">; Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asl_i_p_or">;
// //
// BUILTIN_INFO(HEXAGON.S2_asl_i_r_sat,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.S2_asl_i_r_sat,SI_ftype_SISI,2)
// //
def int_hexagon_S2_asl_i_r_sat : def int_hexagon_S2_asl_i_r_sat :
Hexagon_si_sisi_Intrinsic<"HEXAGON.S2.asl.i.r.sat">; Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_asl_i_r_sat">;
// //
// BUILTIN_INFO(HEXAGON.S2_asr_i_r_rnd,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.S2_asr_i_r_rnd,SI_ftype_SISI,2)
// //
def int_hexagon_S2_asr_i_r_rnd : def int_hexagon_S2_asr_i_r_rnd :
Hexagon_si_sisi_Intrinsic<"HEXAGON.S2.asr.i.r.rnd">; Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_asr_i_r_rnd">;
// //
// BUILTIN_INFO(HEXAGON.S2_asr_i_r_rnd_goodsyntax,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.S2_asr_i_r_rnd_goodsyntax,SI_ftype_SISI,2)
// //
def int_hexagon_S2_asr_i_r_rnd_goodsyntax : def int_hexagon_S2_asr_i_r_rnd_goodsyntax :
Hexagon_si_sisi_Intrinsic<"HEXAGON.S2.asr.i.r.rnd.goodsyntax">; Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_asr_i_r_rnd_goodsyntax">;
//
// BUILTIN_INFO(HEXAGON.S2_asr_i_p_rnd,DI_ftype_DISI,2)
//
def int_hexagon_S2_asr_i_p_rnd :
Hexagon_di_disi_Intrinsic<"HEXAGON_S2_asr_i_p_rnd">;
//
// BUILTIN_INFO(HEXAGON.S2_asr_i_p_rnd_goodsyntax,DI_ftype_DISI,2)
//
def int_hexagon_S2_asr_i_p_rnd_goodsyntax :
Hexagon_di_disi_Intrinsic<"HEXAGON_S2_asr_i_p_rnd_goodsyntax">;
//
// BUILTIN_INFO(HEXAGON.S4_lsli,SI_ftype_SISI,2)
//
def int_hexagon_S4_lsli :
Hexagon_si_sisi_Intrinsic<"HEXAGON_S4_lsli">;
// //
// BUILTIN_INFO(HEXAGON.S2_addasl_rrri,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.S2_addasl_rrri,SI_ftype_SISISI,3)
// //
def int_hexagon_S2_addasl_rrri : def int_hexagon_S2_addasl_rrri :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.S2.addasl.rrri">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_addasl_rrri">;
//
// BUILTIN_INFO(HEXAGON.S4_andi_asl_ri,SI_ftype_SISISI,3)
//
def int_hexagon_S4_andi_asl_ri :
Hexagon_si_sisisi_Intrinsic<"HEXAGON_S4_andi_asl_ri">;
//
// BUILTIN_INFO(HEXAGON.S4_ori_asl_ri,SI_ftype_SISISI,3)
//
def int_hexagon_S4_ori_asl_ri :
Hexagon_si_sisisi_Intrinsic<"HEXAGON_S4_ori_asl_ri">;
//
// BUILTIN_INFO(HEXAGON.S4_addi_asl_ri,SI_ftype_SISISI,3)
//
def int_hexagon_S4_addi_asl_ri :
Hexagon_si_sisisi_Intrinsic<"HEXAGON_S4_addi_asl_ri">;
//
// BUILTIN_INFO(HEXAGON.S4_subi_asl_ri,SI_ftype_SISISI,3)
//
def int_hexagon_S4_subi_asl_ri :
Hexagon_si_sisisi_Intrinsic<"HEXAGON_S4_subi_asl_ri">;
//
// BUILTIN_INFO(HEXAGON.S4_andi_lsr_ri,SI_ftype_SISISI,3)
//
def int_hexagon_S4_andi_lsr_ri :
Hexagon_si_sisisi_Intrinsic<"HEXAGON_S4_andi_lsr_ri">;
//
// BUILTIN_INFO(HEXAGON.S4_ori_lsr_ri,SI_ftype_SISISI,3)
//
def int_hexagon_S4_ori_lsr_ri :
Hexagon_si_sisisi_Intrinsic<"HEXAGON_S4_ori_lsr_ri">;
//
// BUILTIN_INFO(HEXAGON.S4_addi_lsr_ri,SI_ftype_SISISI,3)
//
def int_hexagon_S4_addi_lsr_ri :
Hexagon_si_sisisi_Intrinsic<"HEXAGON_S4_addi_lsr_ri">;
//
// BUILTIN_INFO(HEXAGON.S4_subi_lsr_ri,SI_ftype_SISISI,3)
//
def int_hexagon_S4_subi_lsr_ri :
Hexagon_si_sisisi_Intrinsic<"HEXAGON_S4_subi_lsr_ri">;
// //
// BUILTIN_INFO(HEXAGON.S2_valignib,DI_ftype_DIDISI,3) // BUILTIN_INFO(HEXAGON.S2_valignib,DI_ftype_DIDISI,3)
// //
def int_hexagon_S2_valignib : def int_hexagon_S2_valignib :
Hexagon_di_didisi_Intrinsic<"HEXAGON.S2.valignib">; Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_valignib">;
// //
// BUILTIN_INFO(HEXAGON.S2_valignrb,DI_ftype_DIDIQI,3) // BUILTIN_INFO(HEXAGON.S2_valignrb,DI_ftype_DIDIQI,3)
// //
def int_hexagon_S2_valignrb : def int_hexagon_S2_valignrb :
Hexagon_di_didiqi_Intrinsic<"HEXAGON.S2.valignrb">; Hexagon_di_didiqi_Intrinsic<"HEXAGON_S2_valignrb">;
// //
// BUILTIN_INFO(HEXAGON.S2_vspliceib,DI_ftype_DIDISI,3) // BUILTIN_INFO(HEXAGON.S2_vspliceib,DI_ftype_DIDISI,3)
// //
def int_hexagon_S2_vspliceib : def int_hexagon_S2_vspliceib :
Hexagon_di_didisi_Intrinsic<"HEXAGON.S2.vspliceib">; Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_vspliceib">;
// //
// BUILTIN_INFO(HEXAGON.S2_vsplicerb,DI_ftype_DIDIQI,3) // BUILTIN_INFO(HEXAGON.S2_vsplicerb,DI_ftype_DIDIQI,3)
// //
def int_hexagon_S2_vsplicerb : def int_hexagon_S2_vsplicerb :
Hexagon_di_didiqi_Intrinsic<"HEXAGON.S2.vsplicerb">; Hexagon_di_didiqi_Intrinsic<"HEXAGON_S2_vsplicerb">;
// //
// BUILTIN_INFO(HEXAGON.S2_vsplatrh,DI_ftype_SI,1) // BUILTIN_INFO(HEXAGON.S2_vsplatrh,DI_ftype_SI,1)
// //
def int_hexagon_S2_vsplatrh : def int_hexagon_S2_vsplatrh :
Hexagon_di_si_Intrinsic<"HEXAGON.S2.vsplatrh">; Hexagon_di_si_Intrinsic<"HEXAGON_S2_vsplatrh">;
// //
// BUILTIN_INFO(HEXAGON.S2_vsplatrb,SI_ftype_SI,1) // BUILTIN_INFO(HEXAGON.S2_vsplatrb,SI_ftype_SI,1)
// //
def int_hexagon_S2_vsplatrb : def int_hexagon_S2_vsplatrb :
Hexagon_si_si_Intrinsic<"HEXAGON.S2.vsplatrb">; Hexagon_si_si_Intrinsic<"HEXAGON_S2_vsplatrb">;
// //
// BUILTIN_INFO(HEXAGON.S2_insert,SI_ftype_SISISISI,4) // BUILTIN_INFO(HEXAGON.S2_insert,SI_ftype_SISISISI,4)
// //
def int_hexagon_S2_insert : def int_hexagon_S2_insert :
Hexagon_si_sisisisi_Intrinsic<"HEXAGON.S2.insert">; Hexagon_si_sisisisi_Intrinsic<"HEXAGON_S2_insert">;
// //
// BUILTIN_INFO(HEXAGON.S2_tableidxb_goodsyntax,SI_ftype_SISISISI,4) // BUILTIN_INFO(HEXAGON.S2_tableidxb_goodsyntax,SI_ftype_SISISISI,4)
// //
def int_hexagon_S2_tableidxb_goodsyntax : def int_hexagon_S2_tableidxb_goodsyntax :
Hexagon_si_sisisisi_Intrinsic<"HEXAGON.S2.tableidxb.goodsyntax">; Hexagon_si_sisisisi_Intrinsic<"HEXAGON_S2_tableidxb_goodsyntax">;
// //
// BUILTIN_INFO(HEXAGON.S2_tableidxh_goodsyntax,SI_ftype_SISISISI,4) // BUILTIN_INFO(HEXAGON.S2_tableidxh_goodsyntax,SI_ftype_SISISISI,4)
// //
def int_hexagon_S2_tableidxh_goodsyntax : def int_hexagon_S2_tableidxh_goodsyntax :
Hexagon_si_sisisisi_Intrinsic<"HEXAGON.S2.tableidxh.goodsyntax">; Hexagon_si_sisisisi_Intrinsic<"HEXAGON_S2_tableidxh_goodsyntax">;
// //
// BUILTIN_INFO(HEXAGON.S2_tableidxw_goodsyntax,SI_ftype_SISISISI,4) // BUILTIN_INFO(HEXAGON.S2_tableidxw_goodsyntax,SI_ftype_SISISISI,4)
// //
def int_hexagon_S2_tableidxw_goodsyntax : def int_hexagon_S2_tableidxw_goodsyntax :
Hexagon_si_sisisisi_Intrinsic<"HEXAGON.S2.tableidxw.goodsyntax">; Hexagon_si_sisisisi_Intrinsic<"HEXAGON_S2_tableidxw_goodsyntax">;
// //
// BUILTIN_INFO(HEXAGON.S2_tableidxd_goodsyntax,SI_ftype_SISISISI,4) // BUILTIN_INFO(HEXAGON.S2_tableidxd_goodsyntax,SI_ftype_SISISISI,4)
// //
def int_hexagon_S2_tableidxd_goodsyntax : def int_hexagon_S2_tableidxd_goodsyntax :
Hexagon_si_sisisisi_Intrinsic<"HEXAGON.S2.tableidxd.goodsyntax">; Hexagon_si_sisisisi_Intrinsic<"HEXAGON_S2_tableidxd_goodsyntax">;
//
// BUILTIN_INFO(HEXAGON.A4_bitspliti,DI_ftype_SISI,2)
//
def int_hexagon_A4_bitspliti :
Hexagon_di_sisi_Intrinsic<"HEXAGON_A4_bitspliti">;
//
// BUILTIN_INFO(HEXAGON.A4_bitsplit,DI_ftype_SISI,2)
//
def int_hexagon_A4_bitsplit :
Hexagon_di_sisi_Intrinsic<"HEXAGON_A4_bitsplit">;
//
// BUILTIN_INFO(HEXAGON.S4_extract,SI_ftype_SISISI,3)
//
def int_hexagon_S4_extract :
Hexagon_si_sisisi_Intrinsic<"HEXAGON_S4_extract">;
// //
// BUILTIN_INFO(HEXAGON.S2_extractu,SI_ftype_SISISI,3) // BUILTIN_INFO(HEXAGON.S2_extractu,SI_ftype_SISISI,3)
// //
def int_hexagon_S2_extractu : def int_hexagon_S2_extractu :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.S2.extractu">; Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_extractu">;
// //
// BUILTIN_INFO(HEXAGON.S2_insertp,DI_ftype_DIDISISI,4) // BUILTIN_INFO(HEXAGON.S2_insertp,DI_ftype_DIDISISI,4)
// //
def int_hexagon_S2_insertp : def int_hexagon_S2_insertp :
Hexagon_di_didisisi_Intrinsic<"HEXAGON.S2.insertp">; Hexagon_di_didisisi_Intrinsic<"HEXAGON_S2_insertp">;
//
// BUILTIN_INFO(HEXAGON.S4_extractp,DI_ftype_DISISI,3)
//
def int_hexagon_S4_extractp :
Hexagon_di_disisi_Intrinsic<"HEXAGON_S4_extractp">;
// //
// BUILTIN_INFO(HEXAGON.S2_extractup,DI_ftype_DISISI,3) // BUILTIN_INFO(HEXAGON.S2_extractup,DI_ftype_DISISI,3)
// //
def int_hexagon_S2_extractup : def int_hexagon_S2_extractup :
Hexagon_di_disisi_Intrinsic<"HEXAGON.S2.extractup">; Hexagon_di_disisi_Intrinsic<"HEXAGON_S2_extractup">;
// //
// BUILTIN_INFO(HEXAGON.S2_insert_rp,SI_ftype_SISIDI,3) // BUILTIN_INFO(HEXAGON.S2_insert_rp,SI_ftype_SISIDI,3)
// //
def int_hexagon_S2_insert_rp : def int_hexagon_S2_insert_rp :
Hexagon_si_sisidi_Intrinsic<"HEXAGON.S2.insert.rp">; Hexagon_si_sisidi_Intrinsic<"HEXAGON_S2_insert_rp">;
//
// BUILTIN_INFO(HEXAGON.S4_extract_rp,SI_ftype_SIDI,2)
//
def int_hexagon_S4_extract_rp :
Hexagon_si_sidi_Intrinsic<"HEXAGON_S4_extract_rp">;
// //
// BUILTIN_INFO(HEXAGON.S2_extractu_rp,SI_ftype_SIDI,2) // BUILTIN_INFO(HEXAGON.S2_extractu_rp,SI_ftype_SIDI,2)
// //
def int_hexagon_S2_extractu_rp : def int_hexagon_S2_extractu_rp :
Hexagon_si_sidi_Intrinsic<"HEXAGON.S2.extractu.rp">; Hexagon_si_sidi_Intrinsic<"HEXAGON_S2_extractu_rp">;
// //
// BUILTIN_INFO(HEXAGON.S2_insertp_rp,DI_ftype_DIDIDI,3) // BUILTIN_INFO(HEXAGON.S2_insertp_rp,DI_ftype_DIDIDI,3)
// //
def int_hexagon_S2_insertp_rp : def int_hexagon_S2_insertp_rp :
Hexagon_di_dididi_Intrinsic<"HEXAGON.S2.insertp.rp">; Hexagon_di_dididi_Intrinsic<"HEXAGON_S2_insertp_rp">;
//
// BUILTIN_INFO(HEXAGON.S4_extractp_rp,DI_ftype_DIDI,2)
//
def int_hexagon_S4_extractp_rp :
Hexagon_di_didi_Intrinsic<"HEXAGON_S4_extractp_rp">;
// //
// BUILTIN_INFO(HEXAGON.S2_extractup_rp,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.S2_extractup_rp,DI_ftype_DIDI,2)
// //
def int_hexagon_S2_extractup_rp : def int_hexagon_S2_extractup_rp :
Hexagon_di_didi_Intrinsic<"HEXAGON.S2.extractup.rp">; Hexagon_di_didi_Intrinsic<"HEXAGON_S2_extractup_rp">;
// //
// BUILTIN_INFO(HEXAGON.S2_tstbit_i,QI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.S2_tstbit_i,QI_ftype_SISI,2)
// //
def int_hexagon_S2_tstbit_i : def int_hexagon_S2_tstbit_i :
Hexagon_qi_sisi_Intrinsic<"HEXAGON.S2.tstbit.i">; Hexagon_qi_sisi_Intrinsic<"HEXAGON_S2_tstbit_i">;
//
// BUILTIN_INFO(HEXAGON.S4_ntstbit_i,QI_ftype_SISI,2)
//
def int_hexagon_S4_ntstbit_i :
Hexagon_qi_sisi_Intrinsic<"HEXAGON_S4_ntstbit_i">;
// //
// BUILTIN_INFO(HEXAGON.S2_setbit_i,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.S2_setbit_i,SI_ftype_SISI,2)
// //
def int_hexagon_S2_setbit_i : def int_hexagon_S2_setbit_i :
Hexagon_si_sisi_Intrinsic<"HEXAGON.S2.setbit.i">; Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_setbit_i">;
// //
// BUILTIN_INFO(HEXAGON.S2_togglebit_i,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.S2_togglebit_i,SI_ftype_SISI,2)
// //
def int_hexagon_S2_togglebit_i : def int_hexagon_S2_togglebit_i :
Hexagon_si_sisi_Intrinsic<"HEXAGON.S2.togglebit.i">; Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_togglebit_i">;
// //
// BUILTIN_INFO(HEXAGON.S2_clrbit_i,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.S2_clrbit_i,SI_ftype_SISI,2)
// //
def int_hexagon_S2_clrbit_i : def int_hexagon_S2_clrbit_i :
Hexagon_si_sisi_Intrinsic<"HEXAGON.S2.clrbit.i">; Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_clrbit_i">;
// //
// BUILTIN_INFO(HEXAGON.S2_tstbit_r,QI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.S2_tstbit_r,QI_ftype_SISI,2)
// //
def int_hexagon_S2_tstbit_r : def int_hexagon_S2_tstbit_r :
Hexagon_qi_sisi_Intrinsic<"HEXAGON.S2.tstbit.r">; Hexagon_qi_sisi_Intrinsic<"HEXAGON_S2_tstbit_r">;
//
// BUILTIN_INFO(HEXAGON.S4_ntstbit_r,QI_ftype_SISI,2)
//
def int_hexagon_S4_ntstbit_r :
Hexagon_qi_sisi_Intrinsic<"HEXAGON_S4_ntstbit_r">;
// //
// BUILTIN_INFO(HEXAGON.S2_setbit_r,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.S2_setbit_r,SI_ftype_SISI,2)
// //
def int_hexagon_S2_setbit_r : def int_hexagon_S2_setbit_r :
Hexagon_si_sisi_Intrinsic<"HEXAGON.S2.setbit.r">; Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_setbit_r">;
// //
// BUILTIN_INFO(HEXAGON.S2_togglebit_r,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.S2_togglebit_r,SI_ftype_SISI,2)
// //
def int_hexagon_S2_togglebit_r : def int_hexagon_S2_togglebit_r :
Hexagon_si_sisi_Intrinsic<"HEXAGON.S2.togglebit.r">; Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_togglebit_r">;
// //
// BUILTIN_INFO(HEXAGON.S2_clrbit_r,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.S2_clrbit_r,SI_ftype_SISI,2)
// //
def int_hexagon_S2_clrbit_r : def int_hexagon_S2_clrbit_r :
Hexagon_si_sisi_Intrinsic<"HEXAGON.S2.clrbit.r">; Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_clrbit_r">;
// //
// BUILTIN_INFO(HEXAGON.S2_asr_i_vh,DI_ftype_DISI,2) // BUILTIN_INFO(HEXAGON.S2_asr_i_vh,DI_ftype_DISI,2)
// //
def int_hexagon_S2_asr_i_vh : def int_hexagon_S2_asr_i_vh :
Hexagon_di_disi_Intrinsic<"HEXAGON.S2.asr.i.vh">; Hexagon_di_disi_Intrinsic<"HEXAGON_S2_asr_i_vh">;
// //
// BUILTIN_INFO(HEXAGON.S2_lsr_i_vh,DI_ftype_DISI,2) // BUILTIN_INFO(HEXAGON.S2_lsr_i_vh,DI_ftype_DISI,2)
// //
def int_hexagon_S2_lsr_i_vh : def int_hexagon_S2_lsr_i_vh :
Hexagon_di_disi_Intrinsic<"HEXAGON.S2.lsr.i.vh">; Hexagon_di_disi_Intrinsic<"HEXAGON_S2_lsr_i_vh">;
// //
// BUILTIN_INFO(HEXAGON.S2_asl_i_vh,DI_ftype_DISI,2) // BUILTIN_INFO(HEXAGON.S2_asl_i_vh,DI_ftype_DISI,2)
// //
def int_hexagon_S2_asl_i_vh : def int_hexagon_S2_asl_i_vh :
Hexagon_di_disi_Intrinsic<"HEXAGON.S2.asl.i.vh">; Hexagon_di_disi_Intrinsic<"HEXAGON_S2_asl_i_vh">;
// //
// BUILTIN_INFO(HEXAGON.S2_asr_r_vh,DI_ftype_DISI,2) // BUILTIN_INFO(HEXAGON.S2_asr_r_vh,DI_ftype_DISI,2)
// //
def int_hexagon_S2_asr_r_vh : def int_hexagon_S2_asr_r_vh :
Hexagon_di_disi_Intrinsic<"HEXAGON.S2.asr.r.vh">; Hexagon_di_disi_Intrinsic<"HEXAGON_S2_asr_r_vh">;
//
// BUILTIN_INFO(HEXAGON.S5_asrhub_rnd_sat_goodsyntax,SI_ftype_DISI,2)
//
def int_hexagon_S5_asrhub_rnd_sat_goodsyntax :
Hexagon_si_disi_Intrinsic<"HEXAGON_S5_asrhub_rnd_sat_goodsyntax">;
//
// BUILTIN_INFO(HEXAGON.S5_asrhub_sat,SI_ftype_DISI,2)
//
def int_hexagon_S5_asrhub_sat :
Hexagon_si_disi_Intrinsic<"HEXAGON_S5_asrhub_sat">;
//
// BUILTIN_INFO(HEXAGON.S5_vasrhrnd_goodsyntax,DI_ftype_DISI,2)
//
def int_hexagon_S5_vasrhrnd_goodsyntax :
Hexagon_di_disi_Intrinsic<"HEXAGON_S5_vasrhrnd_goodsyntax">;
// //
// BUILTIN_INFO(HEXAGON.S2_asl_r_vh,DI_ftype_DISI,2) // BUILTIN_INFO(HEXAGON.S2_asl_r_vh,DI_ftype_DISI,2)
// //
def int_hexagon_S2_asl_r_vh : def int_hexagon_S2_asl_r_vh :
Hexagon_di_disi_Intrinsic<"HEXAGON.S2.asl.r.vh">; Hexagon_di_disi_Intrinsic<"HEXAGON_S2_asl_r_vh">;
// //
// BUILTIN_INFO(HEXAGON.S2_lsr_r_vh,DI_ftype_DISI,2) // BUILTIN_INFO(HEXAGON.S2_lsr_r_vh,DI_ftype_DISI,2)
// //
def int_hexagon_S2_lsr_r_vh : def int_hexagon_S2_lsr_r_vh :
Hexagon_di_disi_Intrinsic<"HEXAGON.S2.lsr.r.vh">; Hexagon_di_disi_Intrinsic<"HEXAGON_S2_lsr_r_vh">;
// //
// BUILTIN_INFO(HEXAGON.S2_lsl_r_vh,DI_ftype_DISI,2) // BUILTIN_INFO(HEXAGON.S2_lsl_r_vh,DI_ftype_DISI,2)
// //
def int_hexagon_S2_lsl_r_vh : def int_hexagon_S2_lsl_r_vh :
Hexagon_di_disi_Intrinsic<"HEXAGON.S2.lsl.r.vh">; Hexagon_di_disi_Intrinsic<"HEXAGON_S2_lsl_r_vh">;
// //
// BUILTIN_INFO(HEXAGON.S2_asr_i_vw,DI_ftype_DISI,2) // BUILTIN_INFO(HEXAGON.S2_asr_i_vw,DI_ftype_DISI,2)
// //
def int_hexagon_S2_asr_i_vw : def int_hexagon_S2_asr_i_vw :
Hexagon_di_disi_Intrinsic<"HEXAGON.S2.asr.i.vw">; Hexagon_di_disi_Intrinsic<"HEXAGON_S2_asr_i_vw">;
// //
// BUILTIN_INFO(HEXAGON.S2_asr_i_svw_trun,SI_ftype_DISI,2) // BUILTIN_INFO(HEXAGON.S2_asr_i_svw_trun,SI_ftype_DISI,2)
// //
def int_hexagon_S2_asr_i_svw_trun : def int_hexagon_S2_asr_i_svw_trun :
Hexagon_si_disi_Intrinsic<"HEXAGON.S2.asr.i.svw.trun">; Hexagon_si_disi_Intrinsic<"HEXAGON_S2_asr_i_svw_trun">;
// //
// BUILTIN_INFO(HEXAGON.S2_asr_r_svw_trun,SI_ftype_DISI,2) // BUILTIN_INFO(HEXAGON.S2_asr_r_svw_trun,SI_ftype_DISI,2)
// //
def int_hexagon_S2_asr_r_svw_trun : def int_hexagon_S2_asr_r_svw_trun :
Hexagon_si_disi_Intrinsic<"HEXAGON.S2.asr.r.svw.trun">; Hexagon_si_disi_Intrinsic<"HEXAGON_S2_asr_r_svw_trun">;
// //
// BUILTIN_INFO(HEXAGON.S2_lsr_i_vw,DI_ftype_DISI,2) // BUILTIN_INFO(HEXAGON.S2_lsr_i_vw,DI_ftype_DISI,2)
// //
def int_hexagon_S2_lsr_i_vw : def int_hexagon_S2_lsr_i_vw :
Hexagon_di_disi_Intrinsic<"HEXAGON.S2.lsr.i.vw">; Hexagon_di_disi_Intrinsic<"HEXAGON_S2_lsr_i_vw">;
// //
// BUILTIN_INFO(HEXAGON.S2_asl_i_vw,DI_ftype_DISI,2) // BUILTIN_INFO(HEXAGON.S2_asl_i_vw,DI_ftype_DISI,2)
// //
def int_hexagon_S2_asl_i_vw : def int_hexagon_S2_asl_i_vw :
Hexagon_di_disi_Intrinsic<"HEXAGON.S2.asl.i.vw">; Hexagon_di_disi_Intrinsic<"HEXAGON_S2_asl_i_vw">;
// //
// BUILTIN_INFO(HEXAGON.S2_asr_r_vw,DI_ftype_DISI,2) // BUILTIN_INFO(HEXAGON.S2_asr_r_vw,DI_ftype_DISI,2)
// //
def int_hexagon_S2_asr_r_vw : def int_hexagon_S2_asr_r_vw :
Hexagon_di_disi_Intrinsic<"HEXAGON.S2.asr.r.vw">; Hexagon_di_disi_Intrinsic<"HEXAGON_S2_asr_r_vw">;
// //
// BUILTIN_INFO(HEXAGON.S2_asl_r_vw,DI_ftype_DISI,2) // BUILTIN_INFO(HEXAGON.S2_asl_r_vw,DI_ftype_DISI,2)
// //
def int_hexagon_S2_asl_r_vw : def int_hexagon_S2_asl_r_vw :
Hexagon_di_disi_Intrinsic<"HEXAGON.S2.asl.r.vw">; Hexagon_di_disi_Intrinsic<"HEXAGON_S2_asl_r_vw">;
// //
// BUILTIN_INFO(HEXAGON.S2_lsr_r_vw,DI_ftype_DISI,2) // BUILTIN_INFO(HEXAGON.S2_lsr_r_vw,DI_ftype_DISI,2)
// //
def int_hexagon_S2_lsr_r_vw : def int_hexagon_S2_lsr_r_vw :
Hexagon_di_disi_Intrinsic<"HEXAGON.S2.lsr.r.vw">; Hexagon_di_disi_Intrinsic<"HEXAGON_S2_lsr_r_vw">;
// //
// BUILTIN_INFO(HEXAGON.S2_lsl_r_vw,DI_ftype_DISI,2) // BUILTIN_INFO(HEXAGON.S2_lsl_r_vw,DI_ftype_DISI,2)
// //
def int_hexagon_S2_lsl_r_vw : def int_hexagon_S2_lsl_r_vw :
Hexagon_di_disi_Intrinsic<"HEXAGON.S2.lsl.r.vw">; Hexagon_di_disi_Intrinsic<"HEXAGON_S2_lsl_r_vw">;
// //
// BUILTIN_INFO(HEXAGON.S2_vrndpackwh,SI_ftype_DI,1) // BUILTIN_INFO(HEXAGON.S2_vrndpackwh,SI_ftype_DI,1)
// //
def int_hexagon_S2_vrndpackwh : def int_hexagon_S2_vrndpackwh :
Hexagon_si_di_Intrinsic<"HEXAGON.S2.vrndpackwh">; Hexagon_si_di_Intrinsic<"HEXAGON_S2_vrndpackwh">;
// //
// BUILTIN_INFO(HEXAGON.S2_vrndpackwhs,SI_ftype_DI,1) // BUILTIN_INFO(HEXAGON.S2_vrndpackwhs,SI_ftype_DI,1)
// //
def int_hexagon_S2_vrndpackwhs : def int_hexagon_S2_vrndpackwhs :
Hexagon_si_di_Intrinsic<"HEXAGON.S2.vrndpackwhs">; Hexagon_si_di_Intrinsic<"HEXAGON_S2_vrndpackwhs">;
// //
// BUILTIN_INFO(HEXAGON.S2_vsxtbh,DI_ftype_SI,1) // BUILTIN_INFO(HEXAGON.S2_vsxtbh,DI_ftype_SI,1)
// //
def int_hexagon_S2_vsxtbh : def int_hexagon_S2_vsxtbh :
Hexagon_di_si_Intrinsic<"HEXAGON.S2.vsxtbh">; Hexagon_di_si_Intrinsic<"HEXAGON_S2_vsxtbh">;
// //
// BUILTIN_INFO(HEXAGON.S2_vzxtbh,DI_ftype_SI,1) // BUILTIN_INFO(HEXAGON.S2_vzxtbh,DI_ftype_SI,1)
// //
def int_hexagon_S2_vzxtbh : def int_hexagon_S2_vzxtbh :
Hexagon_di_si_Intrinsic<"HEXAGON.S2.vzxtbh">; Hexagon_di_si_Intrinsic<"HEXAGON_S2_vzxtbh">;
// //
// BUILTIN_INFO(HEXAGON.S2_vsathub,SI_ftype_DI,1) // BUILTIN_INFO(HEXAGON.S2_vsathub,SI_ftype_DI,1)
// //
def int_hexagon_S2_vsathub : def int_hexagon_S2_vsathub :
Hexagon_si_di_Intrinsic<"HEXAGON.S2.vsathub">; Hexagon_si_di_Intrinsic<"HEXAGON_S2_vsathub">;
// //
// BUILTIN_INFO(HEXAGON.S2_svsathub,SI_ftype_SI,1) // BUILTIN_INFO(HEXAGON.S2_svsathub,SI_ftype_SI,1)
// //
def int_hexagon_S2_svsathub : def int_hexagon_S2_svsathub :
Hexagon_si_si_Intrinsic<"HEXAGON.S2.svsathub">; Hexagon_si_si_Intrinsic<"HEXAGON_S2_svsathub">;
// //
// BUILTIN_INFO(HEXAGON.S2_svsathb,SI_ftype_SI,1) // BUILTIN_INFO(HEXAGON.S2_svsathb,SI_ftype_SI,1)
// //
def int_hexagon_S2_svsathb : def int_hexagon_S2_svsathb :
Hexagon_si_si_Intrinsic<"HEXAGON.S2.svsathb">; Hexagon_si_si_Intrinsic<"HEXAGON_S2_svsathb">;
// //
// BUILTIN_INFO(HEXAGON.S2_vsathb,SI_ftype_DI,1) // BUILTIN_INFO(HEXAGON.S2_vsathb,SI_ftype_DI,1)
// //
def int_hexagon_S2_vsathb : def int_hexagon_S2_vsathb :
Hexagon_si_di_Intrinsic<"HEXAGON.S2.vsathb">; Hexagon_si_di_Intrinsic<"HEXAGON_S2_vsathb">;
// //
// BUILTIN_INFO(HEXAGON.S2_vtrunohb,SI_ftype_DI,1) // BUILTIN_INFO(HEXAGON.S2_vtrunohb,SI_ftype_DI,1)
// //
def int_hexagon_S2_vtrunohb : def int_hexagon_S2_vtrunohb :
Hexagon_si_di_Intrinsic<"HEXAGON.S2.vtrunohb">; Hexagon_si_di_Intrinsic<"HEXAGON_S2_vtrunohb">;
// //
// BUILTIN_INFO(HEXAGON.S2_vtrunewh,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.S2_vtrunewh,DI_ftype_DIDI,2)
// //
def int_hexagon_S2_vtrunewh : def int_hexagon_S2_vtrunewh :
Hexagon_di_didi_Intrinsic<"HEXAGON.S2.vtrunewh">; Hexagon_di_didi_Intrinsic<"HEXAGON_S2_vtrunewh">;
// //
// BUILTIN_INFO(HEXAGON.S2_vtrunowh,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.S2_vtrunowh,DI_ftype_DIDI,2)
// //
def int_hexagon_S2_vtrunowh : def int_hexagon_S2_vtrunowh :
Hexagon_di_didi_Intrinsic<"HEXAGON.S2.vtrunowh">; Hexagon_di_didi_Intrinsic<"HEXAGON_S2_vtrunowh">;
// //
// BUILTIN_INFO(HEXAGON.S2_vtrunehb,SI_ftype_DI,1) // BUILTIN_INFO(HEXAGON.S2_vtrunehb,SI_ftype_DI,1)
// //
def int_hexagon_S2_vtrunehb : def int_hexagon_S2_vtrunehb :
Hexagon_si_di_Intrinsic<"HEXAGON.S2.vtrunehb">; Hexagon_si_di_Intrinsic<"HEXAGON_S2_vtrunehb">;
// //
// BUILTIN_INFO(HEXAGON.S2_vsxthw,DI_ftype_SI,1) // BUILTIN_INFO(HEXAGON.S2_vsxthw,DI_ftype_SI,1)
// //
def int_hexagon_S2_vsxthw : def int_hexagon_S2_vsxthw :
Hexagon_di_si_Intrinsic<"HEXAGON.S2.vsxthw">; Hexagon_di_si_Intrinsic<"HEXAGON_S2_vsxthw">;
// //
// BUILTIN_INFO(HEXAGON.S2_vzxthw,DI_ftype_SI,1) // BUILTIN_INFO(HEXAGON.S2_vzxthw,DI_ftype_SI,1)
// //
def int_hexagon_S2_vzxthw : def int_hexagon_S2_vzxthw :
Hexagon_di_si_Intrinsic<"HEXAGON.S2.vzxthw">; Hexagon_di_si_Intrinsic<"HEXAGON_S2_vzxthw">;
// //
// BUILTIN_INFO(HEXAGON.S2_vsatwh,SI_ftype_DI,1) // BUILTIN_INFO(HEXAGON.S2_vsatwh,SI_ftype_DI,1)
// //
def int_hexagon_S2_vsatwh : def int_hexagon_S2_vsatwh :
Hexagon_si_di_Intrinsic<"HEXAGON.S2.vsatwh">; Hexagon_si_di_Intrinsic<"HEXAGON_S2_vsatwh">;
// //
// BUILTIN_INFO(HEXAGON.S2_vsatwuh,SI_ftype_DI,1) // BUILTIN_INFO(HEXAGON.S2_vsatwuh,SI_ftype_DI,1)
// //
def int_hexagon_S2_vsatwuh : def int_hexagon_S2_vsatwuh :
Hexagon_si_di_Intrinsic<"HEXAGON.S2.vsatwuh">; Hexagon_si_di_Intrinsic<"HEXAGON_S2_vsatwuh">;
// //
// BUILTIN_INFO(HEXAGON.S2_packhl,DI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.S2_packhl,DI_ftype_SISI,2)
// //
def int_hexagon_S2_packhl : def int_hexagon_S2_packhl :
Hexagon_di_sisi_Intrinsic<"HEXAGON.S2.packhl">; Hexagon_di_sisi_Intrinsic<"HEXAGON_S2_packhl">;
// //
// BUILTIN_INFO(HEXAGON.A2_swiz,SI_ftype_SI,1) // BUILTIN_INFO(HEXAGON.A2_swiz,SI_ftype_SI,1)
// //
def int_hexagon_A2_swiz : def int_hexagon_A2_swiz :
Hexagon_si_si_Intrinsic<"HEXAGON.A2.swiz">; Hexagon_si_si_Intrinsic<"HEXAGON_A2_swiz">;
// //
// BUILTIN_INFO(HEXAGON.S2_vsathub_nopack,DI_ftype_DI,1) // BUILTIN_INFO(HEXAGON.S2_vsathub_nopack,DI_ftype_DI,1)
// //
def int_hexagon_S2_vsathub_nopack : def int_hexagon_S2_vsathub_nopack :
Hexagon_di_di_Intrinsic<"HEXAGON.S2.vsathub.nopack">; Hexagon_di_di_Intrinsic<"HEXAGON_S2_vsathub_nopack">;
// //
// BUILTIN_INFO(HEXAGON.S2_vsathb_nopack,DI_ftype_DI,1) // BUILTIN_INFO(HEXAGON.S2_vsathb_nopack,DI_ftype_DI,1)
// //
def int_hexagon_S2_vsathb_nopack : def int_hexagon_S2_vsathb_nopack :
Hexagon_di_di_Intrinsic<"HEXAGON.S2.vsathb.nopack">; Hexagon_di_di_Intrinsic<"HEXAGON_S2_vsathb_nopack">;
// //
// BUILTIN_INFO(HEXAGON.S2_vsatwh_nopack,DI_ftype_DI,1) // BUILTIN_INFO(HEXAGON.S2_vsatwh_nopack,DI_ftype_DI,1)
// //
def int_hexagon_S2_vsatwh_nopack : def int_hexagon_S2_vsatwh_nopack :
Hexagon_di_di_Intrinsic<"HEXAGON.S2.vsatwh.nopack">; Hexagon_di_di_Intrinsic<"HEXAGON_S2_vsatwh_nopack">;
// //
// BUILTIN_INFO(HEXAGON.S2_vsatwuh_nopack,DI_ftype_DI,1) // BUILTIN_INFO(HEXAGON.S2_vsatwuh_nopack,DI_ftype_DI,1)
// //
def int_hexagon_S2_vsatwuh_nopack : def int_hexagon_S2_vsatwuh_nopack :
Hexagon_di_di_Intrinsic<"HEXAGON.S2.vsatwuh.nopack">; Hexagon_di_di_Intrinsic<"HEXAGON_S2_vsatwuh_nopack">;
// //
// BUILTIN_INFO(HEXAGON.S2_shuffob,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.S2_shuffob,DI_ftype_DIDI,2)
// //
def int_hexagon_S2_shuffob : def int_hexagon_S2_shuffob :
Hexagon_di_didi_Intrinsic<"HEXAGON.S2.shuffob">; Hexagon_di_didi_Intrinsic<"HEXAGON_S2_shuffob">;
// //
// BUILTIN_INFO(HEXAGON.S2_shuffeb,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.S2_shuffeb,DI_ftype_DIDI,2)
// //
def int_hexagon_S2_shuffeb : def int_hexagon_S2_shuffeb :
Hexagon_di_didi_Intrinsic<"HEXAGON.S2.shuffeb">; Hexagon_di_didi_Intrinsic<"HEXAGON_S2_shuffeb">;
// //
// BUILTIN_INFO(HEXAGON.S2_shuffoh,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.S2_shuffoh,DI_ftype_DIDI,2)
// //
def int_hexagon_S2_shuffoh : def int_hexagon_S2_shuffoh :
Hexagon_di_didi_Intrinsic<"HEXAGON.S2.shuffoh">; Hexagon_di_didi_Intrinsic<"HEXAGON_S2_shuffoh">;
// //
// BUILTIN_INFO(HEXAGON.S2_shuffeh,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.S2_shuffeh,DI_ftype_DIDI,2)
// //
def int_hexagon_S2_shuffeh : def int_hexagon_S2_shuffeh :
Hexagon_di_didi_Intrinsic<"HEXAGON.S2.shuffeh">; Hexagon_di_didi_Intrinsic<"HEXAGON_S2_shuffeh">;
//
// BUILTIN_INFO(HEXAGON.S5_popcountp,SI_ftype_DI,1)
//
def int_hexagon_S5_popcountp :
Hexagon_si_di_Intrinsic<"HEXAGON_S5_popcountp">;
//
// BUILTIN_INFO(HEXAGON.S4_parity,SI_ftype_SISI,2)
//
def int_hexagon_S4_parity :
Hexagon_si_sisi_Intrinsic<"HEXAGON_S4_parity">;
// //
// BUILTIN_INFO(HEXAGON.S2_parityp,SI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.S2_parityp,SI_ftype_DIDI,2)
// //
def int_hexagon_S2_parityp : def int_hexagon_S2_parityp :
Hexagon_si_didi_Intrinsic<"HEXAGON.S2.parityp">; Hexagon_si_didi_Intrinsic<"HEXAGON_S2_parityp">;
// //
// BUILTIN_INFO(HEXAGON.S2_lfsp,DI_ftype_DIDI,2) // BUILTIN_INFO(HEXAGON.S2_lfsp,DI_ftype_DIDI,2)
// //
def int_hexagon_S2_lfsp : def int_hexagon_S2_lfsp :
Hexagon_di_didi_Intrinsic<"HEXAGON.S2.lfsp">; Hexagon_di_didi_Intrinsic<"HEXAGON_S2_lfsp">;
// //
// BUILTIN_INFO(HEXAGON.S2_clbnorm,SI_ftype_SI,1) // BUILTIN_INFO(HEXAGON.S2_clbnorm,SI_ftype_SI,1)
// //
def int_hexagon_S2_clbnorm : def int_hexagon_S2_clbnorm :
Hexagon_si_si_Intrinsic<"HEXAGON.S2.clbnorm">; Hexagon_si_si_Intrinsic<"HEXAGON_S2_clbnorm">;
//
// BUILTIN_INFO(HEXAGON.S4_clbaddi,SI_ftype_SISI,2)
//
def int_hexagon_S4_clbaddi :
Hexagon_si_sisi_Intrinsic<"HEXAGON_S4_clbaddi">;
//
// BUILTIN_INFO(HEXAGON.S4_clbpnorm,SI_ftype_DI,1)
//
def int_hexagon_S4_clbpnorm :
Hexagon_si_di_Intrinsic<"HEXAGON_S4_clbpnorm">;
//
// BUILTIN_INFO(HEXAGON.S4_clbpaddi,SI_ftype_DISI,2)
//
def int_hexagon_S4_clbpaddi :
Hexagon_si_disi_Intrinsic<"HEXAGON_S4_clbpaddi">;
// //
// BUILTIN_INFO(HEXAGON.S2_clb,SI_ftype_SI,1) // BUILTIN_INFO(HEXAGON.S2_clb,SI_ftype_SI,1)
// //
def int_hexagon_S2_clb : def int_hexagon_S2_clb :
Hexagon_si_si_Intrinsic<"HEXAGON.S2.clb">; Hexagon_si_si_Intrinsic<"HEXAGON_S2_clb">;
// //
// BUILTIN_INFO(HEXAGON.S2_cl0,SI_ftype_SI,1) // BUILTIN_INFO(HEXAGON.S2_cl0,SI_ftype_SI,1)
// //
def int_hexagon_S2_cl0 : def int_hexagon_S2_cl0 :
Hexagon_si_si_Intrinsic<"HEXAGON.S2.cl0">; Hexagon_si_si_Intrinsic<"HEXAGON_S2_cl0">;
// //
// BUILTIN_INFO(HEXAGON.S2_cl1,SI_ftype_SI,1) // BUILTIN_INFO(HEXAGON.S2_cl1,SI_ftype_SI,1)
// //
def int_hexagon_S2_cl1 : def int_hexagon_S2_cl1 :
Hexagon_si_si_Intrinsic<"HEXAGON.S2.cl1">; Hexagon_si_si_Intrinsic<"HEXAGON_S2_cl1">;
// //
// BUILTIN_INFO(HEXAGON.S2_clbp,SI_ftype_DI,1) // BUILTIN_INFO(HEXAGON.S2_clbp,SI_ftype_DI,1)
// //
def int_hexagon_S2_clbp : def int_hexagon_S2_clbp :
Hexagon_si_di_Intrinsic<"HEXAGON.S2.clbp">; Hexagon_si_di_Intrinsic<"HEXAGON_S2_clbp">;
// //
// BUILTIN_INFO(HEXAGON.S2_cl0p,SI_ftype_DI,1) // BUILTIN_INFO(HEXAGON.S2_cl0p,SI_ftype_DI,1)
// //
def int_hexagon_S2_cl0p : def int_hexagon_S2_cl0p :
Hexagon_si_di_Intrinsic<"HEXAGON.S2.cl0p">; Hexagon_si_di_Intrinsic<"HEXAGON_S2_cl0p">;
// //
// BUILTIN_INFO(HEXAGON.S2_cl1p,SI_ftype_DI,1) // BUILTIN_INFO(HEXAGON.S2_cl1p,SI_ftype_DI,1)
// //
def int_hexagon_S2_cl1p : def int_hexagon_S2_cl1p :
Hexagon_si_di_Intrinsic<"HEXAGON.S2.cl1p">; Hexagon_si_di_Intrinsic<"HEXAGON_S2_cl1p">;
// //
// BUILTIN_INFO(HEXAGON.S2_brev,SI_ftype_SI,1) // BUILTIN_INFO(HEXAGON.S2_brev,SI_ftype_SI,1)
// //
def int_hexagon_S2_brev : def int_hexagon_S2_brev :
Hexagon_si_si_Intrinsic<"HEXAGON.S2.brev">; Hexagon_si_si_Intrinsic<"HEXAGON_S2_brev">;
//
// BUILTIN_INFO(HEXAGON.S2_brevp,DI_ftype_DI,1)
//
def int_hexagon_S2_brevp :
Hexagon_di_di_Intrinsic<"HEXAGON_S2_brevp">;
// //
// BUILTIN_INFO(HEXAGON.S2_ct0,SI_ftype_SI,1) // BUILTIN_INFO(HEXAGON.S2_ct0,SI_ftype_SI,1)
// //
def int_hexagon_S2_ct0 : def int_hexagon_S2_ct0 :
Hexagon_si_si_Intrinsic<"HEXAGON.S2.ct0">; Hexagon_si_si_Intrinsic<"HEXAGON_S2_ct0">;
// //
// BUILTIN_INFO(HEXAGON.S2_ct1,SI_ftype_SI,1) // BUILTIN_INFO(HEXAGON.S2_ct1,SI_ftype_SI,1)
// //
def int_hexagon_S2_ct1 : def int_hexagon_S2_ct1 :
Hexagon_si_si_Intrinsic<"HEXAGON.S2.ct1">; Hexagon_si_si_Intrinsic<"HEXAGON_S2_ct1">;
//
// BUILTIN_INFO(HEXAGON.S2_interleave,DI_ftype_DI,1)
//
def int_hexagon_S2_interleave :
Hexagon_di_di_Intrinsic<"HEXAGON.S2.interleave">;
//
// BUILTIN_INFO(HEXAGON.S2_deinterleave,DI_ftype_DI,1)
//
def int_hexagon_S2_deinterleave :
Hexagon_di_di_Intrinsic<"HEXAGON.S2.deinterleave">;
//
// BUILTIN_INFO(SI_to_SXTHI_asrh,SI_ftype_SI,1)
//
def int_hexagon_SI_to_SXTHI_asrh :
Hexagon_si_si_Intrinsic<"SI.to.SXTHI.asrh">;
//
// BUILTIN_INFO(HEXAGON.A4_orn,SI_ftype_SISI,2)
//
def int_hexagon_A4_orn :
Hexagon_si_sisi_Intrinsic<"HEXAGON.A4.orn">;
// //
// BUILTIN_INFO(HEXAGON.A4_andn,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.S2_ct0p,SI_ftype_DI,1)
//
def int_hexagon_A4_andn :
Hexagon_si_sisi_Intrinsic<"HEXAGON.A4.andn">;
//
// BUILTIN_INFO(HEXAGON.A4_orn,DI_ftype_DIDI,2)
// //
def int_hexagon_A4_ornp : def int_hexagon_S2_ct0p :
Hexagon_di_didi_Intrinsic<"HEXAGON.A4.ornp">; Hexagon_si_di_Intrinsic<"HEXAGON_S2_ct0p">;
//
// BUILTIN_INFO(HEXAGON.A4_andn,DI_ftype_DIDI,2)
//
def int_hexagon_A4_andnp :
Hexagon_di_didi_Intrinsic<"HEXAGON.A4.andnp">;
// //
// BUILTIN_INFO(HEXAGON.A4_combineir,DI_ftype_sisi,2) // BUILTIN_INFO(HEXAGON.S2_ct1p,SI_ftype_DI,1)
//
def int_hexagon_A4_combineir :
Hexagon_di_sisi_Intrinsic<"HEXAGON.A4.combineir">;
//
// BUILTIN_INFO(HEXAGON.A4_combineir,DI_ftype_sisi,2)
//
def int_hexagon_A4_combineri :
Hexagon_di_sisi_Intrinsic<"HEXAGON.A4.combineri">;
//
// BUILTIN_INFO(HEXAGON.C4_cmpneq,QI_ftype_SISI,2)
// //
def int_hexagon_C4_cmpneq : def int_hexagon_S2_ct1p :
Hexagon_qi_sisi_Intrinsic<"HEXAGON.C4.cmpneq">; Hexagon_si_di_Intrinsic<"HEXAGON_S2_ct1p">;
//
// BUILTIN_INFO(HEXAGON.C4_cmpneqi,QI_ftype_SISI,2)
//
def int_hexagon_C4_cmpneqi :
Hexagon_qi_sisi_Intrinsic<"HEXAGON.C4.cmpneqi">;
//
// BUILTIN_INFO(HEXAGON.C4_cmplte,QI_ftype_SISI,2)
//
def int_hexagon_C4_cmplte :
Hexagon_qi_sisi_Intrinsic<"HEXAGON.C4.cmplte">;
//
// BUILTIN_INFO(HEXAGON.C4_cmpltei,QI_ftype_SISI,2)
//
def int_hexagon_C4_cmpltei :
Hexagon_qi_sisi_Intrinsic<"HEXAGON.C4.cmpltei">;
//
// BUILTIN_INFO(HEXAGON.C4_cmplteu,QI_ftype_SISI,2)
//
def int_hexagon_C4_cmplteu :
Hexagon_qi_sisi_Intrinsic<"HEXAGON.C4.cmplteu">;
//
// BUILTIN_INFO(HEXAGON.C4_cmplteui,QI_ftype_SISI,2)
//
def int_hexagon_C4_cmplteui :
Hexagon_qi_sisi_Intrinsic<"HEXAGON.C4.cmplteui">;
//
// BUILTIN_INFO(HEXAGON.A4_rcmpneq,SI_ftype_SISI,2)
//
def int_hexagon_A4_rcmpneq :
Hexagon_si_sisi_Intrinsic<"HEXAGON.A4.rcmpneq">;
//
// BUILTIN_INFO(HEXAGON.A4_rcmpneqi,SI_ftype_SISI,2)
//
def int_hexagon_A4_rcmpneqi :
Hexagon_si_sisi_Intrinsic<"HEXAGON.A4.rcmpneqi">;
//
// BUILTIN_INFO(HEXAGON.A4_rcmpeq,SI_ftype_SISI,2)
//
def int_hexagon_A4_rcmpeq :
Hexagon_si_sisi_Intrinsic<"HEXAGON.A4.rcmpeq">;
//
// BUILTIN_INFO(HEXAGON.A4_rcmpeqi,SI_ftype_SISI,2)
//
def int_hexagon_A4_rcmpeqi :
Hexagon_si_sisi_Intrinsic<"HEXAGON.A4.rcmpeqi">;
//
// BUILTIN_INFO(HEXAGON.C4_fastcorner9,QI_ftype_QIQI,2)
//
def int_hexagon_C4_fastcorner9 :
Hexagon_qi_qiqi_Intrinsic<"HEXAGON.C4.fastcorner9">;
//
// BUILTIN_INFO(HEXAGON.C4_fastcorner9_not,QI_ftype_QIQI,2)
//
def int_hexagon_C4_fastcorner9_not :
Hexagon_qi_qiqi_Intrinsic<"HEXAGON.C4.fastcorner9_not">;
//
// BUILTIN_INFO(HEXAGON.C4_and_andn,QI_ftype_QIQIQI,3)
//
def int_hexagon_C4_and_andn :
Hexagon_qi_qiqiqi_Intrinsic<"HEXAGON.C4.and_andn">;
//
// BUILTIN_INFO(HEXAGON.C4_and_and,QI_ftype_QIQIQI,3)
//
def int_hexagon_C4_and_and :
Hexagon_qi_qiqiqi_Intrinsic<"HEXAGON.C4.and_and">;
//
// BUILTIN_INFO(HEXAGON.C4_and_orn,QI_ftype_QIQIQI,3)
//
def int_hexagon_C4_and_orn :
Hexagon_qi_qiqiqi_Intrinsic<"HEXAGON.C4.and_orn">;
//
// BUILTIN_INFO(HEXAGON.C4_and_or,QI_ftype_QIQIQI,3)
// //
def int_hexagon_C4_and_or : // BUILTIN_INFO(HEXAGON.S2_interleave,DI_ftype_DI,1)
Hexagon_qi_qiqiqi_Intrinsic<"HEXAGON.C4.and_or">;
//
// BUILTIN_INFO(HEXAGON.C4_or_andn,QI_ftype_QIQIQI,3)
//
def int_hexagon_C4_or_andn :
Hexagon_qi_qiqiqi_Intrinsic<"HEXAGON.C4.or_andn">;
//
// BUILTIN_INFO(HEXAGON.C4_or_and,QI_ftype_QIQIQI,3)
//
def int_hexagon_C4_or_and :
Hexagon_qi_qiqiqi_Intrinsic<"HEXAGON.C4.or_and">;
//
// BUILTIN_INFO(HEXAGON.C4_or_orn,QI_ftype_QIQIQI,3)
//
def int_hexagon_C4_or_orn :
Hexagon_qi_qiqiqi_Intrinsic<"HEXAGON.C4.or_orn">;
//
// BUILTIN_INFO(HEXAGON.C4_or_or,QI_ftype_QIQIQI,3)
//
def int_hexagon_C4_or_or :
Hexagon_qi_qiqiqi_Intrinsic<"HEXAGON.C4.or_or">;
//
// BUILTIN_INFO(HEXAGON.S4_addaddi,SI_ftype_SISISI,3)
//
def int_hexagon_S4_addaddi :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.S4.addaddi">;
//
// BUILTIN_INFO(HEXAGON.S4_subaddi,SI_ftype_SISISI,3)
//
def int_hexagon_S4_subaddi :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.S4.subaddi">;
//
// BUILTIN_INFO(HEXAGON.S4_andnp,DI_ftype_DIDI,2)
//
def int_hexagon_S4_andnp :
Hexagon_di_didi_Intrinsic<"HEXAGON.S4.andnp">;
//
// BUILTIN_INFO(HEXAGON.S4_ornp,DI_ftype_DIDI,2)
//
def int_hexagon_S4_ornp :
Hexagon_di_didi_Intrinsic<"HEXAGON.S4.ornp">;
//
// BUILTIN_INFO(HEXAGON.M4_xor_xacc,DI_ftype_DIDIDI,3)
//
def int_hexagon_M4_xor_xacc :
Hexagon_di_dididi_Intrinsic<"HEXAGON.M4.xor_xacc">;
//
// BUILTIN_INFO(HEXAGON.M4_and_and,SI_ftype_SISISI,3)
//
def int_hexagon_M4_and_and :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.M4.and_and">;
//
// BUILTIN_INFO(HEXAGON.M4_and_andn,SI_ftype_SISISI,3)
//
def int_hexagon_M4_and_andn :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.M4.and_andn">;
//
// BUILTIN_INFO(HEXAGON.M4_and_or,SI_ftype_SISISI,3)
//
def int_hexagon_M4_and_or :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.M4.and_or">;
//
// BUILTIN_INFO(HEXAGON.M4_and_xor,SI_ftype_SISISI,3)
//
def int_hexagon_M4_and_xor :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.M4.and_xor">;
//
// BUILTIN_INFO(HEXAGON.M4_xor_and,SI_ftype_SISISI,3)
//
def int_hexagon_M4_xor_or :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.M4.xor_or">;
//
// BUILTIN_INFO(HEXAGON.M4_xor_or,SI_ftype_SISISI,3)
//
def int_hexagon_M4_xor_and :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.M4.xor_and">;
//
// BUILTIN_INFO(HEXAGON.M4_xor_andn,SI_ftype_SISISI,3)
//
def int_hexagon_M4_xor_andn :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.M4.xor_andn">;
//
// BUILTIN_INFO(HEXAGON.M4_or_and,SI_ftype_SISISI,3)
//
def int_hexagon_M4_or_and :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.M4.or_and">;
//
// BUILTIN_INFO(HEXAGON.M4_or_or,SI_ftype_SISISI,3)
//
def int_hexagon_M4_or_or :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.M4.or_or">;
//
// BUILTIN_INFO(HEXAGON.M4_or_xor,SI_ftype_SISISI,3)
//
def int_hexagon_M4_or_xor :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.M4.or_xor">;
//
// BUILTIN_INFO(HEXAGON.M4_or_andn,SI_ftype_SISISI,3)
//
def int_hexagon_M4_or_andn :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.M4.or_andn">;
//
// BUILTIN_INFO(HEXAGON.S4_or_andix,SI_ftype_SISISI,3)
//
def int_hexagon_S4_or_andix :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.S4.or_andix">;
//
// BUILTIN_INFO(HEXAGON.S4_or_andi,SI_ftype_SISISI,3)
//
def int_hexagon_S4_or_andi :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.S4.or_andi">;
//
// BUILTIN_INFO(HEXAGON.S4_or_ori,SI_ftype_SISISI,3)
//
def int_hexagon_S4_or_ori :
Hexagon_si_sisisi_Intrinsic<"HEXAGON.S4.or_ori">;
//
// BUILTIN_INFO(HEXAGON.A4_modwrapu,SI_ftype_SISI,2)
//
def int_hexagon_A4_modwrapu :
Hexagon_si_sisi_Intrinsic<"HEXAGON.A4.modwrapu">;
//
// BUILTIN_INFO(HEXAGON.A4_cround_ri,SI_ftype_SISI,2)
//
def int_hexagon_A4_cround_ri :
Hexagon_si_sisi_Intrinsic<"HEXAGON.A4.cround_ri">;
//
// BUILTIN_INFO(HEXAGON.A4_cround_rr,SI_ftype_SISI,2)
//
def int_hexagon_A4_cround_rr :
Hexagon_si_sisi_Intrinsic<"HEXAGON.A4.cround_rr">;
//
// BUILTIN_INFO(HEXAGON.A4_round_ri,SI_ftype_SISI,2)
//
def int_hexagon_A4_round_ri :
Hexagon_si_sisi_Intrinsic<"HEXAGON.A4.round_ri">;
//
// BUILTIN_INFO(HEXAGON.A4_round_rr,SI_ftype_SISI,2)
//
def int_hexagon_A4_round_rr :
Hexagon_si_sisi_Intrinsic<"HEXAGON.A4.round_rr">;
//
// BUILTIN_INFO(HEXAGON.A4_round_ri_sat,SI_ftype_SISI,2)
// //
def int_hexagon_A4_round_ri_sat : def int_hexagon_S2_interleave :
Hexagon_si_sisi_Intrinsic<"HEXAGON.A4.round_ri_sat">; Hexagon_di_di_Intrinsic<"HEXAGON_S2_interleave">;
// //
// BUILTIN_INFO(HEXAGON.A4_round_rr_sat,SI_ftype_SISI,2) // BUILTIN_INFO(HEXAGON.S2_deinterleave,DI_ftype_DI,1)
// //
def int_hexagon_A4_round_rr_sat : def int_hexagon_S2_deinterleave :
Hexagon_si_sisi_Intrinsic<"HEXAGON.A4.round_rr_sat">; Hexagon_di_di_Intrinsic<"HEXAGON_S2_deinterleave">;
 End of changes. 635 change blocks. 
935 lines changed or deleted 2127 lines changed or added


 IntrinsicsX86.td   IntrinsicsX86.td 
skipping to change at line 221 skipping to change at line 221
Intrinsic<[llvm_x86mmx_ty], [llvm_v4f32_ty], [IntrNoMem]>; Intrinsic<[llvm_x86mmx_ty], [llvm_v4f32_ty], [IntrNoMem]>;
def int_x86_sse_cvtpi2ps : GCCBuiltin<"__builtin_ia32_cvtpi2ps">, def int_x86_sse_cvtpi2ps : GCCBuiltin<"__builtin_ia32_cvtpi2ps">,
Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty,
llvm_x86mmx_ty], [IntrNoMem]>; llvm_x86mmx_ty], [IntrNoMem]>;
} }
// SIMD store ops // SIMD store ops
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_sse_storeu_ps : GCCBuiltin<"__builtin_ia32_storeups">, def int_x86_sse_storeu_ps : GCCBuiltin<"__builtin_ia32_storeups">,
Intrinsic<[], [llvm_ptr_ty, Intrinsic<[], [llvm_ptr_ty,
llvm_v4f32_ty], []>; llvm_v4f32_ty], [IntrReadWriteArgMem]>;
} }
// Cacheability support ops // Cacheability support ops
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_sse_sfence : GCCBuiltin<"__builtin_ia32_sfence">, def int_x86_sse_sfence : GCCBuiltin<"__builtin_ia32_sfence">,
Intrinsic<[], [], []>; Intrinsic<[], [], []>;
} }
// Control register. // Control register.
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
skipping to change at line 504 skipping to change at line 504
def int_x86_sse_cvttpd2pi: GCCBuiltin<"__builtin_ia32_cvttpd2pi">, def int_x86_sse_cvttpd2pi: GCCBuiltin<"__builtin_ia32_cvttpd2pi">,
Intrinsic<[llvm_x86mmx_ty], [llvm_v2f64_ty], [IntrNoMem]>; Intrinsic<[llvm_x86mmx_ty], [llvm_v2f64_ty], [IntrNoMem]>;
def int_x86_sse_cvtpi2pd : GCCBuiltin<"__builtin_ia32_cvtpi2pd">, def int_x86_sse_cvtpi2pd : GCCBuiltin<"__builtin_ia32_cvtpi2pd">,
Intrinsic<[llvm_v2f64_ty], [llvm_x86mmx_ty], [IntrNoMem]>; Intrinsic<[llvm_v2f64_ty], [llvm_x86mmx_ty], [IntrNoMem]>;
} }
// SIMD store ops // SIMD store ops
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_sse2_storeu_pd : GCCBuiltin<"__builtin_ia32_storeupd">, def int_x86_sse2_storeu_pd : GCCBuiltin<"__builtin_ia32_storeupd">,
Intrinsic<[], [llvm_ptr_ty, Intrinsic<[], [llvm_ptr_ty,
llvm_v2f64_ty], []>; llvm_v2f64_ty], [IntrReadWriteArgMem]>;
def int_x86_sse2_storeu_dq : GCCBuiltin<"__builtin_ia32_storedqu">, def int_x86_sse2_storeu_dq : GCCBuiltin<"__builtin_ia32_storedqu">,
Intrinsic<[], [llvm_ptr_ty, Intrinsic<[], [llvm_ptr_ty,
llvm_v16i8_ty], []>; llvm_v16i8_ty], [IntrReadWriteArgMem]>;
def int_x86_sse2_storel_dq : GCCBuiltin<"__builtin_ia32_storelv4si">, def int_x86_sse2_storel_dq : GCCBuiltin<"__builtin_ia32_storelv4si">,
Intrinsic<[], [llvm_ptr_ty, Intrinsic<[], [llvm_ptr_ty,
llvm_v4i32_ty], []>; llvm_v4i32_ty], [IntrReadWriteArgMem]>;
} }
// Misc. // Misc.
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_sse2_packsswb_128 : GCCBuiltin<"__builtin_ia32_packsswb128">, def int_x86_sse2_packsswb_128 : GCCBuiltin<"__builtin_ia32_packsswb128">,
Intrinsic<[llvm_v16i8_ty], [llvm_v8i16_ty, Intrinsic<[llvm_v16i8_ty], [llvm_v8i16_ty,
llvm_v8i16_ty], [IntrNoMem]>; llvm_v8i16_ty], [IntrNoMem]>;
def int_x86_sse2_packssdw_128 : GCCBuiltin<"__builtin_ia32_packssdw128">, def int_x86_sse2_packssdw_128 : GCCBuiltin<"__builtin_ia32_packssdw128">,
Intrinsic<[llvm_v8i16_ty], [llvm_v4i32_ty, Intrinsic<[llvm_v8i16_ty], [llvm_v4i32_ty,
llvm_v4i32_ty], [IntrNoMem]>; llvm_v4i32_ty], [IntrNoMem]>;
skipping to change at line 821 skipping to change at line 821
[IntrNoMem]>; [IntrNoMem]>;
def int_x86_aesni_aesdeclast : GCCBuiltin<"__builtin_ia32_aesdeclast128"> , def int_x86_aesni_aesdeclast : GCCBuiltin<"__builtin_ia32_aesdeclast128"> ,
Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty], Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
[IntrNoMem]>; [IntrNoMem]>;
def int_x86_aesni_aeskeygenassist : def int_x86_aesni_aeskeygenassist :
GCCBuiltin<"__builtin_ia32_aeskeygenassist128">, GCCBuiltin<"__builtin_ia32_aeskeygenassist128">,
Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_i8_ty], Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_i8_ty],
[IntrNoMem]>; [IntrNoMem]>;
} }
// PCLMUL instruction
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_pclmulqdq : GCCBuiltin<"__builtin_ia32_pclmulqdq128">,
Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty, llvm_i8
_ty],
[IntrNoMem]>;
}
// Vector pack // Vector pack
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_sse41_packusdw : GCCBuiltin<"__builtin_ia32_packusdw12 8">, def int_x86_sse41_packusdw : GCCBuiltin<"__builtin_ia32_packusdw12 8">,
Intrinsic<[llvm_v8i16_ty], [llvm_v4i32_ty, llvm_v4i32_ty], Intrinsic<[llvm_v8i16_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
[IntrNoMem]>; [IntrNoMem]>;
} }
// Vector multiply // Vector multiply
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_sse41_pmuldq : GCCBuiltin<"__builtin_ia32_pmuldq128" >, def int_x86_sse41_pmuldq : GCCBuiltin<"__builtin_ia32_pmuldq128" >,
skipping to change at line 1007 skipping to change at line 1014
llvm_i8_ty], llvm_i8_ty],
[IntrNoMem]>; [IntrNoMem]>;
def int_x86_sse42_pcmpestriz128 : GCCBuiltin<"__builtin_ia32_pcmpestriz12 8">, def int_x86_sse42_pcmpestriz128 : GCCBuiltin<"__builtin_ia32_pcmpestriz12 8">,
Intrinsic<[llvm_i32_ty], Intrinsic<[llvm_i32_ty],
[llvm_v16i8_ty, llvm_i32_ty, llvm_v16i8_ty, llvm_i32_ty, [llvm_v16i8_ty, llvm_i32_ty, llvm_v16i8_ty, llvm_i32_ty,
llvm_i8_ty], llvm_i8_ty],
[IntrNoMem]>; [IntrNoMem]>;
} }
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// SSE4A
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_sse4a_extrqi : GCCBuiltin<"__builtin_ia32_extrqi">,
Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_i8_ty, llvm_i8_ty],
[IntrNoMem]>;
def int_x86_sse4a_extrq : GCCBuiltin<"__builtin_ia32_extrq">,
Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v16i8_ty], [IntrNoMem]>
;
def int_x86_sse4a_insertqi : GCCBuiltin<"__builtin_ia32_insertqi">,
Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty,
llvm_i8_ty, llvm_i8_ty], [IntrNoMem]>;
def int_x86_sse4a_insertq : GCCBuiltin<"__builtin_ia32_insertq">,
Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty], [IntrNoMem]>
;
def int_x86_sse4a_movnt_ss : GCCBuiltin<"__builtin_ia32_movntss">,
Intrinsic<[], [llvm_ptr_ty, llvm_v4f32_ty], []>;
def int_x86_sse4a_movnt_sd : GCCBuiltin<"__builtin_ia32_movntsd">,
Intrinsic<[], [llvm_ptr_ty, llvm_v2f64_ty], []>;
}
//===----------------------------------------------------------------------
===//
// AVX // AVX
// Arithmetic ops // Arithmetic ops
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_avx_addsub_pd_256 : GCCBuiltin<"__builtin_ia32_addsubpd256">, def int_x86_avx_addsub_pd_256 : GCCBuiltin<"__builtin_ia32_addsubpd256">,
Intrinsic<[llvm_v4f64_ty], [llvm_v4f64_ty, Intrinsic<[llvm_v4f64_ty], [llvm_v4f64_ty,
llvm_v4f64_ty], [IntrNoMem]>; llvm_v4f64_ty], [IntrNoMem]>;
def int_x86_avx_addsub_ps_256 : GCCBuiltin<"__builtin_ia32_addsubps256">, def int_x86_avx_addsub_ps_256 : GCCBuiltin<"__builtin_ia32_addsubps256">,
Intrinsic<[llvm_v8f32_ty], [llvm_v8f32_ty, Intrinsic<[llvm_v8f32_ty], [llvm_v8f32_ty,
llvm_v8f32_ty], [IntrNoMem]>; llvm_v8f32_ty], [IntrNoMem]>;
skipping to change at line 1243 skipping to change at line 1272
def int_x86_avx_vzeroall : GCCBuiltin<"__builtin_ia32_vzeroall">, def int_x86_avx_vzeroall : GCCBuiltin<"__builtin_ia32_vzeroall">,
Intrinsic<[], [], []>; Intrinsic<[], [], []>;
def int_x86_avx_vzeroupper : GCCBuiltin<"__builtin_ia32_vzeroupper">, def int_x86_avx_vzeroupper : GCCBuiltin<"__builtin_ia32_vzeroupper">,
Intrinsic<[], [], []>; Intrinsic<[], [], []>;
} }
// Vector load with broadcast // Vector load with broadcast
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_avx_vbroadcast_ss : def int_x86_avx_vbroadcast_ss :
GCCBuiltin<"__builtin_ia32_vbroadcastss">, GCCBuiltin<"__builtin_ia32_vbroadcastss">,
Intrinsic<[llvm_v4f32_ty], [llvm_ptr_ty], [IntrReadMem]>; Intrinsic<[llvm_v4f32_ty], [llvm_ptr_ty], [IntrReadArgMem]>;
def int_x86_avx_vbroadcast_sd_256 : def int_x86_avx_vbroadcast_sd_256 :
GCCBuiltin<"__builtin_ia32_vbroadcastsd256">, GCCBuiltin<"__builtin_ia32_vbroadcastsd256">,
Intrinsic<[llvm_v4f64_ty], [llvm_ptr_ty], [IntrReadMem]>; Intrinsic<[llvm_v4f64_ty], [llvm_ptr_ty], [IntrReadArgMem]>;
def int_x86_avx_vbroadcast_ss_256 : def int_x86_avx_vbroadcast_ss_256 :
GCCBuiltin<"__builtin_ia32_vbroadcastss256">, GCCBuiltin<"__builtin_ia32_vbroadcastss256">,
Intrinsic<[llvm_v8f32_ty], [llvm_ptr_ty], [IntrReadMem]>; Intrinsic<[llvm_v8f32_ty], [llvm_ptr_ty], [IntrReadArgMem]>;
def int_x86_avx_vbroadcastf128_pd_256 : def int_x86_avx_vbroadcastf128_pd_256 :
GCCBuiltin<"__builtin_ia32_vbroadcastf128_pd256">, GCCBuiltin<"__builtin_ia32_vbroadcastf128_pd256">,
Intrinsic<[llvm_v4f64_ty], [llvm_ptr_ty], [IntrReadMem]>; Intrinsic<[llvm_v4f64_ty], [llvm_ptr_ty], [IntrReadArgMem]>;
def int_x86_avx_vbroadcastf128_ps_256 : def int_x86_avx_vbroadcastf128_ps_256 :
GCCBuiltin<"__builtin_ia32_vbroadcastf128_ps256">, GCCBuiltin<"__builtin_ia32_vbroadcastf128_ps256">,
Intrinsic<[llvm_v8f32_ty], [llvm_ptr_ty], [IntrReadMem]>; Intrinsic<[llvm_v8f32_ty], [llvm_ptr_ty], [IntrReadArgMem]>;
} }
// SIMD load ops // SIMD load ops
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_avx_ldu_dq_256 : GCCBuiltin<"__builtin_ia32_lddqu256">, def int_x86_avx_ldu_dq_256 : GCCBuiltin<"__builtin_ia32_lddqu256">,
Intrinsic<[llvm_v32i8_ty], [llvm_ptr_ty], [IntrReadMem]>; Intrinsic<[llvm_v32i8_ty], [llvm_ptr_ty], [IntrReadMem]>;
} }
// SIMD store ops // SIMD store ops
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_avx_storeu_pd_256 : GCCBuiltin<"__builtin_ia32_storeupd256">, def int_x86_avx_storeu_pd_256 : GCCBuiltin<"__builtin_ia32_storeupd256">,
Intrinsic<[], [llvm_ptr_ty, llvm_v4f64_ty], []>; Intrinsic<[], [llvm_ptr_ty, llvm_v4f64_ty], [IntrReadWriteArgMem]>;
def int_x86_avx_storeu_ps_256 : GCCBuiltin<"__builtin_ia32_storeups256">, def int_x86_avx_storeu_ps_256 : GCCBuiltin<"__builtin_ia32_storeups256">,
Intrinsic<[], [llvm_ptr_ty, llvm_v8f32_ty], []>; Intrinsic<[], [llvm_ptr_ty, llvm_v8f32_ty], [IntrReadWriteArgMem]>;
def int_x86_avx_storeu_dq_256 : GCCBuiltin<"__builtin_ia32_storedqu256">, def int_x86_avx_storeu_dq_256 : GCCBuiltin<"__builtin_ia32_storedqu256">,
Intrinsic<[], [llvm_ptr_ty, llvm_v32i8_ty], []>; Intrinsic<[], [llvm_ptr_ty, llvm_v32i8_ty], [IntrReadWriteArgMem]>;
}
// Cacheability support ops
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_avx_movnt_dq_256 : GCCBuiltin<"__builtin_ia32_movntdq256">,
Intrinsic<[], [llvm_ptr_ty, llvm_v4i64_ty], []>;
def int_x86_avx_movnt_pd_256 : GCCBuiltin<"__builtin_ia32_movntpd256">,
Intrinsic<[], [llvm_ptr_ty, llvm_v4f64_ty], []>;
def int_x86_avx_movnt_ps_256 : GCCBuiltin<"__builtin_ia32_movntps256">,
Intrinsic<[], [llvm_ptr_ty, llvm_v8f32_ty], []>;
} }
// Conditional load ops // Conditional load ops
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_avx_maskload_pd : GCCBuiltin<"__builtin_ia32_maskloadpd">, def int_x86_avx_maskload_pd : GCCBuiltin<"__builtin_ia32_maskloadpd">,
Intrinsic<[llvm_v2f64_ty], [llvm_ptr_ty, llvm_v2f64_ty], [IntrReadM Intrinsic<[llvm_v2f64_ty], [llvm_ptr_ty, llvm_v2f64_ty],
em]>; [IntrReadArgMem]>;
def int_x86_avx_maskload_ps : GCCBuiltin<"__builtin_ia32_maskloadps">, def int_x86_avx_maskload_ps : GCCBuiltin<"__builtin_ia32_maskloadps">,
Intrinsic<[llvm_v4f32_ty], [llvm_ptr_ty, llvm_v4f32_ty], [IntrReadM Intrinsic<[llvm_v4f32_ty], [llvm_ptr_ty, llvm_v4f32_ty],
em]>; [IntrReadArgMem]>;
def int_x86_avx_maskload_pd_256 : GCCBuiltin<"__builtin_ia32_maskloadpd25 6">, def int_x86_avx_maskload_pd_256 : GCCBuiltin<"__builtin_ia32_maskloadpd25 6">,
Intrinsic<[llvm_v4f64_ty], [llvm_ptr_ty, llvm_v4f64_ty], [IntrReadM Intrinsic<[llvm_v4f64_ty], [llvm_ptr_ty, llvm_v4f64_ty],
em]>; [IntrReadArgMem]>;
def int_x86_avx_maskload_ps_256 : GCCBuiltin<"__builtin_ia32_maskloadps25 6">, def int_x86_avx_maskload_ps_256 : GCCBuiltin<"__builtin_ia32_maskloadps25 6">,
Intrinsic<[llvm_v8f32_ty], [llvm_ptr_ty, llvm_v8f32_ty], [IntrReadM Intrinsic<[llvm_v8f32_ty], [llvm_ptr_ty, llvm_v8f32_ty],
em]>; [IntrReadArgMem]>;
} }
// Conditional store ops // Conditional store ops
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_avx_maskstore_pd : GCCBuiltin<"__builtin_ia32_maskstorepd">, def int_x86_avx_maskstore_pd : GCCBuiltin<"__builtin_ia32_maskstorepd">,
Intrinsic<[], [llvm_ptr_ty, Intrinsic<[], [llvm_ptr_ty,
llvm_v2f64_ty, llvm_v2f64_ty], []>; llvm_v2f64_ty, llvm_v2f64_ty], [IntrReadWriteArgMem]>;
def int_x86_avx_maskstore_ps : GCCBuiltin<"__builtin_ia32_maskstoreps">, def int_x86_avx_maskstore_ps : GCCBuiltin<"__builtin_ia32_maskstoreps">,
Intrinsic<[], [llvm_ptr_ty, Intrinsic<[], [llvm_ptr_ty,
llvm_v4f32_ty, llvm_v4f32_ty], []>; llvm_v4f32_ty, llvm_v4f32_ty], [IntrReadWriteArgMem]>;
def int_x86_avx_maskstore_pd_256 : def int_x86_avx_maskstore_pd_256 :
GCCBuiltin<"__builtin_ia32_maskstorepd256">, GCCBuiltin<"__builtin_ia32_maskstorepd256">,
Intrinsic<[], [llvm_ptr_ty, Intrinsic<[], [llvm_ptr_ty,
llvm_v4f64_ty, llvm_v4f64_ty], []>; llvm_v4f64_ty, llvm_v4f64_ty], [IntrReadWriteArgMem]>;
def int_x86_avx_maskstore_ps_256 : def int_x86_avx_maskstore_ps_256 :
GCCBuiltin<"__builtin_ia32_maskstoreps256">, GCCBuiltin<"__builtin_ia32_maskstoreps256">,
Intrinsic<[], [llvm_ptr_ty, Intrinsic<[], [llvm_ptr_ty,
llvm_v8f32_ty, llvm_v8f32_ty], []>; llvm_v8f32_ty, llvm_v8f32_ty], [IntrReadWriteArgMem]>;
} }
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// AVX2 // AVX2
// Integer arithmetic ops. // Integer arithmetic ops.
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_avx2_padds_b : GCCBuiltin<"__builtin_ia32_paddsb256">, def int_x86_avx2_padds_b : GCCBuiltin<"__builtin_ia32_paddsb256">,
Intrinsic<[llvm_v32i8_ty], [llvm_v32i8_ty, Intrinsic<[llvm_v32i8_ty], [llvm_v32i8_ty,
llvm_v32i8_ty], [IntrNoMem, Commutative]>; llvm_v32i8_ty], [IntrNoMem, Commutative]>;
skipping to change at line 1615 skipping to change at line 1638
GCCBuiltin<"__builtin_ia32_vbroadcastss_ps">, GCCBuiltin<"__builtin_ia32_vbroadcastss_ps">,
Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty], [IntrNoMem]>; Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty], [IntrNoMem]>;
def int_x86_avx2_vbroadcast_sd_pd_256 : def int_x86_avx2_vbroadcast_sd_pd_256 :
GCCBuiltin<"__builtin_ia32_vbroadcastsd_pd256">, GCCBuiltin<"__builtin_ia32_vbroadcastsd_pd256">,
Intrinsic<[llvm_v4f64_ty], [llvm_v2f64_ty], [IntrNoMem]>; Intrinsic<[llvm_v4f64_ty], [llvm_v2f64_ty], [IntrNoMem]>;
def int_x86_avx2_vbroadcast_ss_ps_256 : def int_x86_avx2_vbroadcast_ss_ps_256 :
GCCBuiltin<"__builtin_ia32_vbroadcastss_ps256">, GCCBuiltin<"__builtin_ia32_vbroadcastss_ps256">,
Intrinsic<[llvm_v8f32_ty], [llvm_v4f32_ty], [IntrNoMem]>; Intrinsic<[llvm_v8f32_ty], [llvm_v4f32_ty], [IntrNoMem]>;
def int_x86_avx2_vbroadcasti128 : def int_x86_avx2_vbroadcasti128 :
GCCBuiltin<"__builtin_ia32_vbroadcastsi256">, GCCBuiltin<"__builtin_ia32_vbroadcastsi256">,
Intrinsic<[llvm_v4i64_ty], [llvm_ptr_ty], [IntrReadMem]>; Intrinsic<[llvm_v4i64_ty], [llvm_ptr_ty], [IntrReadArgMem]>;
def int_x86_avx2_pbroadcastb_128 : def int_x86_avx2_pbroadcastb_128 :
GCCBuiltin<"__builtin_ia32_pbroadcastb128">, GCCBuiltin<"__builtin_ia32_pbroadcastb128">,
Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty], [IntrNoMem]>; Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty], [IntrNoMem]>;
def int_x86_avx2_pbroadcastb_256 : def int_x86_avx2_pbroadcastb_256 :
GCCBuiltin<"__builtin_ia32_pbroadcastb256">, GCCBuiltin<"__builtin_ia32_pbroadcastb256">,
Intrinsic<[llvm_v32i8_ty], [llvm_v16i8_ty], [IntrNoMem]>; Intrinsic<[llvm_v32i8_ty], [llvm_v16i8_ty], [IntrNoMem]>;
def int_x86_avx2_pbroadcastw_128 : def int_x86_avx2_pbroadcastw_128 :
GCCBuiltin<"__builtin_ia32_pbroadcastw128">, GCCBuiltin<"__builtin_ia32_pbroadcastw128">,
Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty], [IntrNoMem]>; Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty], [IntrNoMem]>;
def int_x86_avx2_pbroadcastw_256 : def int_x86_avx2_pbroadcastw_256 :
skipping to change at line 1668 skipping to change at line 1691
Intrinsic<[llvm_v2i64_ty], [llvm_v4i64_ty, Intrinsic<[llvm_v2i64_ty], [llvm_v4i64_ty,
llvm_i8_ty], [IntrNoMem]>; llvm_i8_ty], [IntrNoMem]>;
def int_x86_avx2_vinserti128 : GCCBuiltin<"__builtin_ia32_insert128i256"> , def int_x86_avx2_vinserti128 : GCCBuiltin<"__builtin_ia32_insert128i256"> ,
Intrinsic<[llvm_v4i64_ty], [llvm_v4i64_ty, Intrinsic<[llvm_v4i64_ty], [llvm_v4i64_ty,
llvm_v2i64_ty, llvm_i8_ty], [IntrNoMem]>; llvm_v2i64_ty, llvm_i8_ty], [IntrNoMem]>;
} }
// Conditional load ops // Conditional load ops
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_avx2_maskload_d : GCCBuiltin<"__builtin_ia32_maskloadd">, def int_x86_avx2_maskload_d : GCCBuiltin<"__builtin_ia32_maskloadd">,
Intrinsic<[llvm_v4i32_ty], [llvm_ptr_ty, llvm_v4i32_ty], [IntrReadM Intrinsic<[llvm_v4i32_ty], [llvm_ptr_ty, llvm_v4i32_ty],
em]>; [IntrReadArgMem]>;
def int_x86_avx2_maskload_q : GCCBuiltin<"__builtin_ia32_maskloadq">, def int_x86_avx2_maskload_q : GCCBuiltin<"__builtin_ia32_maskloadq">,
Intrinsic<[llvm_v2i64_ty], [llvm_ptr_ty, llvm_v2i64_ty], [IntrReadM Intrinsic<[llvm_v2i64_ty], [llvm_ptr_ty, llvm_v2i64_ty],
em]>; [IntrReadArgMem]>;
def int_x86_avx2_maskload_d_256 : GCCBuiltin<"__builtin_ia32_maskloadd256 ">, def int_x86_avx2_maskload_d_256 : GCCBuiltin<"__builtin_ia32_maskloadd256 ">,
Intrinsic<[llvm_v8i32_ty], [llvm_ptr_ty, llvm_v8i32_ty], [IntrReadM Intrinsic<[llvm_v8i32_ty], [llvm_ptr_ty, llvm_v8i32_ty],
em]>; [IntrReadArgMem]>;
def int_x86_avx2_maskload_q_256 : GCCBuiltin<"__builtin_ia32_maskloadq256 ">, def int_x86_avx2_maskload_q_256 : GCCBuiltin<"__builtin_ia32_maskloadq256 ">,
Intrinsic<[llvm_v4i64_ty], [llvm_ptr_ty, llvm_v4i64_ty], [IntrReadM Intrinsic<[llvm_v4i64_ty], [llvm_ptr_ty, llvm_v4i64_ty],
em]>; [IntrReadArgMem]>;
} }
// Conditional store ops // Conditional store ops
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_avx2_maskstore_d : GCCBuiltin<"__builtin_ia32_maskstored">, def int_x86_avx2_maskstore_d : GCCBuiltin<"__builtin_ia32_maskstored">,
Intrinsic<[], [llvm_ptr_ty, llvm_v4i32_ty, llvm_v4i32_ty], []>; Intrinsic<[], [llvm_ptr_ty, llvm_v4i32_ty, llvm_v4i32_ty],
[IntrReadWriteArgMem]>;
def int_x86_avx2_maskstore_q : GCCBuiltin<"__builtin_ia32_maskstoreq">, def int_x86_avx2_maskstore_q : GCCBuiltin<"__builtin_ia32_maskstoreq">,
Intrinsic<[], [llvm_ptr_ty, llvm_v2i64_ty, llvm_v2i64_ty], []>; Intrinsic<[], [llvm_ptr_ty, llvm_v2i64_ty, llvm_v2i64_ty],
[IntrReadWriteArgMem]>;
def int_x86_avx2_maskstore_d_256 : def int_x86_avx2_maskstore_d_256 :
GCCBuiltin<"__builtin_ia32_maskstored256">, GCCBuiltin<"__builtin_ia32_maskstored256">,
Intrinsic<[], [llvm_ptr_ty, llvm_v8i32_ty, llvm_v8i32_ty], []>; Intrinsic<[], [llvm_ptr_ty, llvm_v8i32_ty, llvm_v8i32_ty],
[IntrReadWriteArgMem]>;
def int_x86_avx2_maskstore_q_256 : def int_x86_avx2_maskstore_q_256 :
GCCBuiltin<"__builtin_ia32_maskstoreq256">, GCCBuiltin<"__builtin_ia32_maskstoreq256">,
Intrinsic<[], [llvm_ptr_ty, llvm_v4i64_ty, llvm_v4i64_ty], []>; Intrinsic<[], [llvm_ptr_ty, llvm_v4i64_ty, llvm_v4i64_ty],
[IntrReadWriteArgMem]>;
} }
// Variable bit shift ops // Variable bit shift ops
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_avx2_psllv_d : GCCBuiltin<"__builtin_ia32_psllv4si">, def int_x86_avx2_psllv_d : GCCBuiltin<"__builtin_ia32_psllv4si">,
Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
[IntrNoMem]>; [IntrNoMem]>;
def int_x86_avx2_psllv_d_256 : GCCBuiltin<"__builtin_ia32_psllv8si">, def int_x86_avx2_psllv_d_256 : GCCBuiltin<"__builtin_ia32_psllv8si">,
Intrinsic<[llvm_v8i32_ty], [llvm_v8i32_ty, llvm_v8i32_ty], Intrinsic<[llvm_v8i32_ty], [llvm_v8i32_ty, llvm_v8i32_ty],
[IntrNoMem]>; [IntrNoMem]>;
skipping to change at line 1727 skipping to change at line 1758
[IntrNoMem]>; [IntrNoMem]>;
def int_x86_avx2_psrav_d : GCCBuiltin<"__builtin_ia32_psrav4si">, def int_x86_avx2_psrav_d : GCCBuiltin<"__builtin_ia32_psrav4si">,
Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
[IntrNoMem]>; [IntrNoMem]>;
def int_x86_avx2_psrav_d_256 : GCCBuiltin<"__builtin_ia32_psrav8si">, def int_x86_avx2_psrav_d_256 : GCCBuiltin<"__builtin_ia32_psrav8si">,
Intrinsic<[llvm_v8i32_ty], [llvm_v8i32_ty, llvm_v8i32_ty], Intrinsic<[llvm_v8i32_ty], [llvm_v8i32_ty, llvm_v8i32_ty],
[IntrNoMem]>; [IntrNoMem]>;
} }
// Gather ops
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_avx2_gather_d_pd : GCCBuiltin<"__builtin_ia32_gatherd_pd">,
Intrinsic<[llvm_v2f64_ty],
[llvm_v2f64_ty, llvm_ptr_ty, llvm_v4i32_ty, llvm_v2f64_ty, llvm_i8_
ty],
[IntrReadMem]>;
def int_x86_avx2_gather_d_pd_256 : GCCBuiltin<"__builtin_ia32_gatherd_pd2
56">,
Intrinsic<[llvm_v4f64_ty],
[llvm_v4f64_ty, llvm_ptr_ty, llvm_v4i32_ty, llvm_v4f64_ty, llvm_i8_
ty],
[IntrReadMem]>;
def int_x86_avx2_gather_q_pd : GCCBuiltin<"__builtin_ia32_gatherq_pd">,
Intrinsic<[llvm_v2f64_ty],
[llvm_v2f64_ty, llvm_ptr_ty, llvm_v2i64_ty, llvm_v2f64_ty, llvm_i8_
ty],
[IntrReadMem]>;
def int_x86_avx2_gather_q_pd_256 : GCCBuiltin<"__builtin_ia32_gatherq_pd2
56">,
Intrinsic<[llvm_v4f64_ty],
[llvm_v4f64_ty, llvm_ptr_ty, llvm_v4i64_ty, llvm_v4f64_ty, llvm_i8_
ty],
[IntrReadMem]>;
def int_x86_avx2_gather_d_ps : GCCBuiltin<"__builtin_ia32_gatherd_ps">,
Intrinsic<[llvm_v4f32_ty],
[llvm_v4f32_ty, llvm_ptr_ty, llvm_v4i32_ty, llvm_v4f32_ty, llvm_i8_
ty],
[IntrReadMem]>;
def int_x86_avx2_gather_d_ps_256 : GCCBuiltin<"__builtin_ia32_gatherd_ps2
56">,
Intrinsic<[llvm_v8f32_ty],
[llvm_v8f32_ty, llvm_ptr_ty, llvm_v8i32_ty, llvm_v8f32_ty, llvm_i8_
ty],
[IntrReadMem]>;
def int_x86_avx2_gather_q_ps : GCCBuiltin<"__builtin_ia32_gatherq_ps">,
Intrinsic<[llvm_v4f32_ty],
[llvm_v4f32_ty, llvm_ptr_ty, llvm_v2i64_ty, llvm_v4f32_ty, llvm_i8_
ty],
[IntrReadMem]>;
def int_x86_avx2_gather_q_ps_256 : GCCBuiltin<"__builtin_ia32_gatherq_ps2
56">,
Intrinsic<[llvm_v4f32_ty],
[llvm_v4f32_ty, llvm_ptr_ty, llvm_v4i64_ty, llvm_v4f32_ty, llvm_i8_
ty],
[IntrReadMem]>;
def int_x86_avx2_gather_d_q : GCCBuiltin<"__builtin_ia32_gatherd_q">,
Intrinsic<[llvm_v2i64_ty],
[llvm_v2i64_ty, llvm_ptr_ty, llvm_v4i32_ty, llvm_v2i64_ty, llvm_i8_
ty],
[IntrReadMem]>;
def int_x86_avx2_gather_d_q_256 : GCCBuiltin<"__builtin_ia32_gatherd_q256
">,
Intrinsic<[llvm_v4i64_ty],
[llvm_v4i64_ty, llvm_ptr_ty, llvm_v4i32_ty, llvm_v4i64_ty, llvm_i8_
ty],
[IntrReadMem]>;
def int_x86_avx2_gather_q_q : GCCBuiltin<"__builtin_ia32_gatherq_q">,
Intrinsic<[llvm_v2i64_ty],
[llvm_v2i64_ty, llvm_ptr_ty, llvm_v2i64_ty, llvm_v2i64_ty, llvm_i8_
ty],
[IntrReadMem]>;
def int_x86_avx2_gather_q_q_256 : GCCBuiltin<"__builtin_ia32_gatherq_q256
">,
Intrinsic<[llvm_v4i64_ty],
[llvm_v4i64_ty, llvm_ptr_ty, llvm_v4i64_ty, llvm_v4i64_ty, llvm_i8_
ty],
[IntrReadMem]>;
def int_x86_avx2_gather_d_d : GCCBuiltin<"__builtin_ia32_gatherd_d">,
Intrinsic<[llvm_v4i32_ty],
[llvm_v4i32_ty, llvm_ptr_ty, llvm_v4i32_ty, llvm_v4i32_ty, llvm_i8_
ty],
[IntrReadMem]>;
def int_x86_avx2_gather_d_d_256 : GCCBuiltin<"__builtin_ia32_gatherd_d256
">,
Intrinsic<[llvm_v8i32_ty],
[llvm_v8i32_ty, llvm_ptr_ty, llvm_v8i32_ty, llvm_v8i32_ty, llvm_i8_
ty],
[IntrReadMem]>;
def int_x86_avx2_gather_q_d : GCCBuiltin<"__builtin_ia32_gatherq_d">,
Intrinsic<[llvm_v4i32_ty],
[llvm_v4i32_ty, llvm_ptr_ty, llvm_v2i64_ty, llvm_v4i32_ty, llvm_i8_
ty],
[IntrReadMem]>;
def int_x86_avx2_gather_q_d_256 : GCCBuiltin<"__builtin_ia32_gatherq_d256
">,
Intrinsic<[llvm_v4i32_ty],
[llvm_v4i32_ty, llvm_ptr_ty, llvm_v4i64_ty, llvm_v4i32_ty, llvm_i8_
ty],
[IntrReadMem]>;
}
// Misc. // Misc.
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_avx2_pmovmskb : GCCBuiltin<"__builtin_ia32_pmovmskb256">, def int_x86_avx2_pmovmskb : GCCBuiltin<"__builtin_ia32_pmovmskb256">,
Intrinsic<[llvm_i32_ty], [llvm_v32i8_ty], [IntrNoMem]>; Intrinsic<[llvm_i32_ty], [llvm_v32i8_ty], [IntrNoMem]>;
def int_x86_avx2_pshuf_b : GCCBuiltin<"__builtin_ia32_pshufb256">, def int_x86_avx2_pshuf_b : GCCBuiltin<"__builtin_ia32_pshufb256">,
Intrinsic<[llvm_v32i8_ty], [llvm_v32i8_ty, Intrinsic<[llvm_v32i8_ty], [llvm_v32i8_ty,
llvm_v32i8_ty], [IntrNoMem]>; llvm_v32i8_ty], [IntrNoMem]>;
def int_x86_avx2_mpsadbw : GCCBuiltin<"__builtin_ia32_mpsadbw256">, def int_x86_avx2_mpsadbw : GCCBuiltin<"__builtin_ia32_mpsadbw256">,
Intrinsic<[llvm_v16i16_ty], [llvm_v32i8_ty, llvm_v32i8_ty, Intrinsic<[llvm_v16i16_ty], [llvm_v32i8_ty, llvm_v32i8_ty,
llvm_i32_ty], [IntrNoMem, Commutative]>; llvm_i32_ty], [IntrNoMem, Commutative]>;
def int_x86_avx2_movntdqa : GCCBuiltin<"__builtin_ia32_movntdqa256">, def int_x86_avx2_movntdqa : GCCBuiltin<"__builtin_ia32_movntdqa256">,
Intrinsic<[llvm_v4i64_ty], [llvm_ptr_ty], [IntrReadMem]>; Intrinsic<[llvm_v4i64_ty], [llvm_ptr_ty], [IntrReadMem]>;
} }
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// FMA4 // FMA3 and FMA4
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_fma4_vfmadd_ss : GCCBuiltin<"__builtin_ia32_vfmaddss">, def int_x86_fma_vfmadd_ss : GCCBuiltin<"__builtin_ia32_vfmaddss">,
Intrinsic<[llvm_v4f32_ty], Intrinsic<[llvm_v4f32_ty],
[llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty],
[IntrNoMem]>; [IntrNoMem]>;
def int_x86_fma4_vfmadd_sd : GCCBuiltin<"__builtin_ia32_vfmaddsd">, def int_x86_fma_vfmadd_sd : GCCBuiltin<"__builtin_ia32_vfmaddsd">,
Intrinsic<[llvm_v2f64_ty], Intrinsic<[llvm_v2f64_ty],
[llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty],
[IntrNoMem]>; [IntrNoMem]>;
def int_x86_fma4_vfmadd_ps : GCCBuiltin<"__builtin_ia32_vfmaddps">, def int_x86_fma_vfmadd_ps : GCCBuiltin<"__builtin_ia32_vfmaddps">,
Intrinsic<[llvm_v4f32_ty], Intrinsic<[llvm_v4f32_ty],
[llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty],
[IntrNoMem]>; [IntrNoMem]>;
def int_x86_fma4_vfmadd_pd : GCCBuiltin<"__builtin_ia32_vfmaddpd">, def int_x86_fma_vfmadd_pd : GCCBuiltin<"__builtin_ia32_vfmaddpd">,
Intrinsic<[llvm_v2f64_ty], Intrinsic<[llvm_v2f64_ty],
[llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty],
[IntrNoMem]>; [IntrNoMem]>;
def int_x86_fma4_vfmadd_ps_256 : GCCBuiltin<"__builtin_ia32_vfmaddps256"> , def int_x86_fma_vfmadd_ps_256 : GCCBuiltin<"__builtin_ia32_vfmaddps256">,
Intrinsic<[llvm_v8f32_ty], Intrinsic<[llvm_v8f32_ty],
[llvm_v8f32_ty, llvm_v8f32_ty, llvm_v8f32_ty], [llvm_v8f32_ty, llvm_v8f32_ty, llvm_v8f32_ty],
[IntrNoMem]>; [IntrNoMem]>;
def int_x86_fma4_vfmadd_pd_256 : GCCBuiltin<"__builtin_ia32_vfmaddpd256"> , def int_x86_fma_vfmadd_pd_256 : GCCBuiltin<"__builtin_ia32_vfmaddpd256">,
Intrinsic<[llvm_v4f64_ty], Intrinsic<[llvm_v4f64_ty],
[llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4f64_ty], [llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4f64_ty],
[IntrNoMem]>; [IntrNoMem]>;
def int_x86_fma4_vfmsub_ss : GCCBuiltin<"__builtin_ia32_vfmsubss">, def int_x86_fma_vfmsub_ss : GCCBuiltin<"__builtin_ia32_vfmsubss">,
Intrinsic<[llvm_v4f32_ty], Intrinsic<[llvm_v4f32_ty],
[llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty],
[IntrNoMem]>; [IntrNoMem]>;
def int_x86_fma4_vfmsub_sd : GCCBuiltin<"__builtin_ia32_vfmsubsd">, def int_x86_fma_vfmsub_sd : GCCBuiltin<"__builtin_ia32_vfmsubsd">,
Intrinsic<[llvm_v2f64_ty], Intrinsic<[llvm_v2f64_ty],
[llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty],
[IntrNoMem]>; [IntrNoMem]>;
def int_x86_fma4_vfmsub_ps : GCCBuiltin<"__builtin_ia32_vfmsubps">, def int_x86_fma_vfmsub_ps : GCCBuiltin<"__builtin_ia32_vfmsubps">,
Intrinsic<[llvm_v4f32_ty], Intrinsic<[llvm_v4f32_ty],
[llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty],
[IntrNoMem]>; [IntrNoMem]>;
def int_x86_fma4_vfmsub_pd : GCCBuiltin<"__builtin_ia32_vfmsubpd">, def int_x86_fma_vfmsub_pd : GCCBuiltin<"__builtin_ia32_vfmsubpd">,
Intrinsic<[llvm_v2f64_ty], Intrinsic<[llvm_v2f64_ty],
[llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty],
[IntrNoMem]>; [IntrNoMem]>;
def int_x86_fma4_vfmsub_ps_256 : GCCBuiltin<"__builtin_ia32_vfmsubps256"> , def int_x86_fma_vfmsub_ps_256 : GCCBuiltin<"__builtin_ia32_vfmsubps256">,
Intrinsic<[llvm_v8f32_ty], Intrinsic<[llvm_v8f32_ty],
[llvm_v8f32_ty, llvm_v8f32_ty, llvm_v8f32_ty], [llvm_v8f32_ty, llvm_v8f32_ty, llvm_v8f32_ty],
[IntrNoMem]>; [IntrNoMem]>;
def int_x86_fma4_vfmsub_pd_256 : GCCBuiltin<"__builtin_ia32_vfmsubpd256"> , def int_x86_fma_vfmsub_pd_256 : GCCBuiltin<"__builtin_ia32_vfmsubpd256">,
Intrinsic<[llvm_v4f64_ty], Intrinsic<[llvm_v4f64_ty],
[llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4f64_ty], [llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4f64_ty],
[IntrNoMem]>; [IntrNoMem]>;
def int_x86_fma4_vfnmadd_ss : GCCBuiltin<"__builtin_ia32_vfnmaddss">, def int_x86_fma_vfnmadd_ss : GCCBuiltin<"__builtin_ia32_vfnmaddss">,
Intrinsic<[llvm_v4f32_ty], Intrinsic<[llvm_v4f32_ty],
[llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty],
[IntrNoMem]>; [IntrNoMem]>;
def int_x86_fma4_vfnmadd_sd : GCCBuiltin<"__builtin_ia32_vfnmaddsd">, def int_x86_fma_vfnmadd_sd : GCCBuiltin<"__builtin_ia32_vfnmaddsd">,
Intrinsic<[llvm_v2f64_ty], Intrinsic<[llvm_v2f64_ty],
[llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty],
[IntrNoMem]>; [IntrNoMem]>;
def int_x86_fma4_vfnmadd_ps : GCCBuiltin<"__builtin_ia32_vfnmaddps">, def int_x86_fma_vfnmadd_ps : GCCBuiltin<"__builtin_ia32_vfnmaddps">,
Intrinsic<[llvm_v4f32_ty], Intrinsic<[llvm_v4f32_ty],
[llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty],
[IntrNoMem]>; [IntrNoMem]>;
def int_x86_fma4_vfnmadd_pd : GCCBuiltin<"__builtin_ia32_vfnmaddpd">, def int_x86_fma_vfnmadd_pd : GCCBuiltin<"__builtin_ia32_vfnmaddpd">,
Intrinsic<[llvm_v2f64_ty], Intrinsic<[llvm_v2f64_ty],
[llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty],
[IntrNoMem]>; [IntrNoMem]>;
def int_x86_fma4_vfnmadd_ps_256 : GCCBuiltin<"__builtin_ia32_vfnmaddps256 ">, def int_x86_fma_vfnmadd_ps_256 : GCCBuiltin<"__builtin_ia32_vfnmaddps256" >,
Intrinsic<[llvm_v8f32_ty], Intrinsic<[llvm_v8f32_ty],
[llvm_v8f32_ty, llvm_v8f32_ty, llvm_v8f32_ty], [llvm_v8f32_ty, llvm_v8f32_ty, llvm_v8f32_ty],
[IntrNoMem]>; [IntrNoMem]>;
def int_x86_fma4_vfnmadd_pd_256 : GCCBuiltin<"__builtin_ia32_vfnmaddpd256 ">, def int_x86_fma_vfnmadd_pd_256 : GCCBuiltin<"__builtin_ia32_vfnmaddpd256" >,
Intrinsic<[llvm_v4f64_ty], Intrinsic<[llvm_v4f64_ty],
[llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4f64_ty], [llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4f64_ty],
[IntrNoMem]>; [IntrNoMem]>;
def int_x86_fma4_vfnmsub_ss : GCCBuiltin<"__builtin_ia32_vfnmsubss">, def int_x86_fma_vfnmsub_ss : GCCBuiltin<"__builtin_ia32_vfnmsubss">,
Intrinsic<[llvm_v4f32_ty], Intrinsic<[llvm_v4f32_ty],
[llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty],
[IntrNoMem]>; [IntrNoMem]>;
def int_x86_fma4_vfnmsub_sd : GCCBuiltin<"__builtin_ia32_vfnmsubsd">, def int_x86_fma_vfnmsub_sd : GCCBuiltin<"__builtin_ia32_vfnmsubsd">,
Intrinsic<[llvm_v2f64_ty], Intrinsic<[llvm_v2f64_ty],
[llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty],
[IntrNoMem]>; [IntrNoMem]>;
def int_x86_fma4_vfnmsub_ps : GCCBuiltin<"__builtin_ia32_vfnmsubps">, def int_x86_fma_vfnmsub_ps : GCCBuiltin<"__builtin_ia32_vfnmsubps">,
Intrinsic<[llvm_v4f32_ty], Intrinsic<[llvm_v4f32_ty],
[llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty],
[IntrNoMem]>; [IntrNoMem]>;
def int_x86_fma4_vfnmsub_pd : GCCBuiltin<"__builtin_ia32_vfnmsubpd">, def int_x86_fma_vfnmsub_pd : GCCBuiltin<"__builtin_ia32_vfnmsubpd">,
Intrinsic<[llvm_v2f64_ty], Intrinsic<[llvm_v2f64_ty],
[llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty],
[IntrNoMem]>; [IntrNoMem]>;
def int_x86_fma4_vfnmsub_ps_256 : GCCBuiltin<"__builtin_ia32_vfnmsubps256 ">, def int_x86_fma_vfnmsub_ps_256 : GCCBuiltin<"__builtin_ia32_vfnmsubps256" >,
Intrinsic<[llvm_v8f32_ty], Intrinsic<[llvm_v8f32_ty],
[llvm_v8f32_ty, llvm_v8f32_ty, llvm_v8f32_ty], [llvm_v8f32_ty, llvm_v8f32_ty, llvm_v8f32_ty],
[IntrNoMem]>; [IntrNoMem]>;
def int_x86_fma4_vfnmsub_pd_256 : GCCBuiltin<"__builtin_ia32_vfnmsubpd256 ">, def int_x86_fma_vfnmsub_pd_256 : GCCBuiltin<"__builtin_ia32_vfnmsubpd256" >,
Intrinsic<[llvm_v4f64_ty], Intrinsic<[llvm_v4f64_ty],
[llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4f64_ty], [llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4f64_ty],
[IntrNoMem]>; [IntrNoMem]>;
def int_x86_fma4_vfmaddsub_ps : GCCBuiltin<"__builtin_ia32_vfmaddsubps">, def int_x86_fma_vfmaddsub_ps : GCCBuiltin<"__builtin_ia32_vfmaddsubps">,
Intrinsic<[llvm_v4f32_ty], Intrinsic<[llvm_v4f32_ty],
[llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty],
[IntrNoMem]>; [IntrNoMem]>;
def int_x86_fma4_vfmaddsub_pd : GCCBuiltin<"__builtin_ia32_vfmaddsubpd">, def int_x86_fma_vfmaddsub_pd : GCCBuiltin<"__builtin_ia32_vfmaddsubpd">,
Intrinsic<[llvm_v2f64_ty], Intrinsic<[llvm_v2f64_ty],
[llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty],
[IntrNoMem]>; [IntrNoMem]>;
def int_x86_fma4_vfmaddsub_ps_256 : def int_x86_fma_vfmaddsub_ps_256 :
GCCBuiltin<"__builtin_ia32_vfmaddsubps256">, GCCBuiltin<"__builtin_ia32_vfmaddsubps256">,
Intrinsic<[llvm_v8f32_ty], Intrinsic<[llvm_v8f32_ty],
[llvm_v8f32_ty, llvm_v8f32_ty, llvm_v8f32_ty], [llvm_v8f32_ty, llvm_v8f32_ty, llvm_v8f32_ty],
[IntrNoMem]>; [IntrNoMem]>;
def int_x86_fma4_vfmaddsub_pd_256 : def int_x86_fma_vfmaddsub_pd_256 :
GCCBuiltin<"__builtin_ia32_vfmaddsubpd256">, GCCBuiltin<"__builtin_ia32_vfmaddsubpd256">,
Intrinsic<[llvm_v4f64_ty], Intrinsic<[llvm_v4f64_ty],
[llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4f64_ty], [llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4f64_ty],
[IntrNoMem]>; [IntrNoMem]>;
def int_x86_fma4_vfmsubadd_ps : GCCBuiltin<"__builtin_ia32_vfmsubaddps">, def int_x86_fma_vfmsubadd_ps : GCCBuiltin<"__builtin_ia32_vfmsubaddps">,
Intrinsic<[llvm_v4f32_ty], Intrinsic<[llvm_v4f32_ty],
[llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty],
[IntrNoMem]>; [IntrNoMem]>;
def int_x86_fma4_vfmsubadd_pd : GCCBuiltin<"__builtin_ia32_vfmsubaddpd">, def int_x86_fma_vfmsubadd_pd : GCCBuiltin<"__builtin_ia32_vfmsubaddpd">,
Intrinsic<[llvm_v2f64_ty], Intrinsic<[llvm_v2f64_ty],
[llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty],
[IntrNoMem]>; [IntrNoMem]>;
def int_x86_fma4_vfmsubadd_ps_256 : def int_x86_fma_vfmsubadd_ps_256 :
GCCBuiltin<"__builtin_ia32_vfmsubaddps256">, GCCBuiltin<"__builtin_ia32_vfmsubaddps256">,
Intrinsic<[llvm_v8f32_ty], Intrinsic<[llvm_v8f32_ty],
[llvm_v8f32_ty, llvm_v8f32_ty, llvm_v8f32_ty], [llvm_v8f32_ty, llvm_v8f32_ty, llvm_v8f32_ty],
[IntrNoMem]>; [IntrNoMem]>;
def int_x86_fma4_vfmsubadd_pd_256 : def int_x86_fma_vfmsubadd_pd_256 :
GCCBuiltin<"__builtin_ia32_vfmsubaddpd256">, GCCBuiltin<"__builtin_ia32_vfmsubaddpd256">,
Intrinsic<[llvm_v4f64_ty], Intrinsic<[llvm_v4f64_ty],
[llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4f64_ty], [llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4f64_ty],
[IntrNoMem]>; [IntrNoMem]>;
} }
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// XOP // XOP
def int_x86_xop_vpermil2pd : GCCBuiltin<"__builtin_ia32_vpermil2pd">, def int_x86_xop_vpermil2pd : GCCBuiltin<"__builtin_ia32_vpermil2pd">,
skipping to change at line 1903 skipping to change at line 2003
def int_x86_xop_vpermil2ps : GCCBuiltin<"__builtin_ia32_vpermil2ps">, def int_x86_xop_vpermil2ps : GCCBuiltin<"__builtin_ia32_vpermil2ps">,
Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty, Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty,
llvm_v4f32_ty, llvm_i8_ty], llvm_v4f32_ty, llvm_i8_ty],
[IntrNoMem]>; [IntrNoMem]>;
def int_x86_xop_vpermil2ps_256 : def int_x86_xop_vpermil2ps_256 :
GCCBuiltin<"__builtin_ia32_vpermil2ps256">, GCCBuiltin<"__builtin_ia32_vpermil2ps256">,
Intrinsic<[llvm_v8f32_ty], [llvm_v8f32_ty, llvm_v8f32_ty, Intrinsic<[llvm_v8f32_ty], [llvm_v8f32_ty, llvm_v8f32_ty,
llvm_v8f32_ty, llvm_i8_ty], llvm_v8f32_ty, llvm_i8_ty],
[IntrNoMem]>; [IntrNoMem]>;
def int_x86_xop_vfrcz_pd : def int_x86_xop_vfrcz_pd : GCCBuiltin<"__builtin_ia32_vfrczpd">,
GCCBuiltin<"__builtin_ia32_vfrczpd">,
Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty], [IntrNoMem]>; Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty], [IntrNoMem]>;
def int_x86_xop_vfrcz_ps : def int_x86_xop_vfrcz_ps : GCCBuiltin<"__builtin_ia32_vfrczps">,
GCCBuiltin<"__builtin_ia32_vfrczps">,
Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty], [IntrNoMem]>; Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty], [IntrNoMem]>;
def int_x86_xop_vfrcz_sd : def int_x86_xop_vfrcz_sd : GCCBuiltin<"__builtin_ia32_vfrczsd">,
GCCBuiltin<"__builtin_ia32_vfrczsd">, Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty], [IntrNoMem]>;
Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], def int_x86_xop_vfrcz_ss : GCCBuiltin<"__builtin_ia32_vfrczss">,
[IntrNoMem]>; Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty], [IntrNoMem]>;
def int_x86_xop_vfrcz_ss : def int_x86_xop_vfrcz_pd_256 : GCCBuiltin<"__builtin_ia32_vfrczpd256">,
GCCBuiltin<"__builtin_ia32_vfrczss">,
Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty],
[IntrNoMem]>;
def int_x86_xop_vfrcz_pd_256 :
GCCBuiltin<"__builtin_ia32_vfrczpd256">,
Intrinsic<[llvm_v4f64_ty], [llvm_v4f64_ty], [IntrNoMem]>; Intrinsic<[llvm_v4f64_ty], [llvm_v4f64_ty], [IntrNoMem]>;
def int_x86_xop_vfrcz_ps_256 : def int_x86_xop_vfrcz_ps_256 : GCCBuiltin<"__builtin_ia32_vfrczps256">,
GCCBuiltin<"__builtin_ia32_vfrczps256">,
Intrinsic<[llvm_v8f32_ty], [llvm_v8f32_ty], [IntrNoMem]>; Intrinsic<[llvm_v8f32_ty], [llvm_v8f32_ty], [IntrNoMem]>;
def int_x86_xop_vpcmov : def int_x86_xop_vpcmov :
GCCBuiltin<"__builtin_ia32_vpcmov">, GCCBuiltin<"__builtin_ia32_vpcmov">,
Intrinsic<[llvm_v2i64_ty], Intrinsic<[llvm_v2i64_ty],
[llvm_v2i64_ty, llvm_v2i64_ty, llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty, llvm_v2i64_ty],
[IntrNoMem]>; [IntrNoMem]>;
def int_x86_xop_vpcmov_256 : def int_x86_xop_vpcmov_256 :
GCCBuiltin<"__builtin_ia32_vpcmov_256">, GCCBuiltin<"__builtin_ia32_vpcmov_256">,
Intrinsic<[llvm_v4i64_ty], Intrinsic<[llvm_v4i64_ty],
[llvm_v4i64_ty, llvm_v4i64_ty, llvm_v4i64_ty], [llvm_v4i64_ty, llvm_v4i64_ty, llvm_v4i64_ty],
[IntrNoMem]>; [IntrNoMem]>;
def int_x86_xop_vpcomeqb :
GCCBuiltin<"__builtin_ia32_vpcomeqb">, def int_x86_xop_vpcomb : GCCBuiltin<"__builtin_ia32_vpcomb">,
Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty,
[IntrNoMem]>; llvm_i8_ty], [IntrNoMem]>;
def int_x86_xop_vpcomeqw : def int_x86_xop_vpcomw : GCCBuiltin<"__builtin_ia32_vpcomw">,
GCCBuiltin<"__builtin_ia32_vpcomeqw">, Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty,
Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], llvm_i8_ty], [IntrNoMem]>;
[IntrNoMem]>; def int_x86_xop_vpcomd : GCCBuiltin<"__builtin_ia32_vpcomd">,
def int_x86_xop_vpcomeqd : Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty,
GCCBuiltin<"__builtin_ia32_vpcomeqd">, llvm_i8_ty], [IntrNoMem]>;
Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], def int_x86_xop_vpcomq : GCCBuiltin<"__builtin_ia32_vpcomq">,
[IntrNoMem]>; Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty,
def int_x86_xop_vpcomeqq : llvm_i8_ty], [IntrNoMem]>;
GCCBuiltin<"__builtin_ia32_vpcomeqq">, def int_x86_xop_vpcomub : GCCBuiltin<"__builtin_ia32_vpcomub">,
Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty], Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty,
[IntrNoMem]>; llvm_i8_ty], [IntrNoMem]>;
def int_x86_xop_vpcomequb : def int_x86_xop_vpcomuw : GCCBuiltin<"__builtin_ia32_vpcomuw">,
GCCBuiltin<"__builtin_ia32_vpcomequb">, Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty,
Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], llvm_i8_ty], [IntrNoMem]>;
[IntrNoMem]>; def int_x86_xop_vpcomud : GCCBuiltin<"__builtin_ia32_vpcomud">,
def int_x86_xop_vpcomequd : Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty,
GCCBuiltin<"__builtin_ia32_vpcomequd">, llvm_i8_ty], [IntrNoMem]>;
Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], def int_x86_xop_vpcomuq : GCCBuiltin<"__builtin_ia32_vpcomuq">,
[IntrNoMem]>; Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty,
def int_x86_xop_vpcomequq : llvm_i8_ty], [IntrNoMem]>;
GCCBuiltin<"__builtin_ia32_vpcomequq">,
Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
[IntrNoMem]>;
def int_x86_xop_vpcomequw :
GCCBuiltin<"__builtin_ia32_vpcomequw">,
Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty],
[IntrNoMem]>;
def int_x86_xop_vpcomfalseb :
GCCBuiltin<"__builtin_ia32_vpcomfalseb">,
Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty],
[IntrNoMem]>;
def int_x86_xop_vpcomfalsed :
GCCBuiltin<"__builtin_ia32_vpcomfalsed">,
Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
[IntrNoMem]>;
def int_x86_xop_vpcomfalseq :
GCCBuiltin<"__builtin_ia32_vpcomfalseq">,
Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
[IntrNoMem]>;
def int_x86_xop_vpcomfalseub :
GCCBuiltin<"__builtin_ia32_vpcomfalseub">,
Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty],
[IntrNoMem]>;
def int_x86_xop_vpcomfalseud :
GCCBuiltin<"__builtin_ia32_vpcomfalseud">,
Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
[IntrNoMem]>;
def int_x86_xop_vpcomfalseuq :
GCCBuiltin<"__builtin_ia32_vpcomfalseuq">,
Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
[IntrNoMem]>;
def int_x86_xop_vpcomfalseuw :
GCCBuiltin<"__builtin_ia32_vpcomfalseuw">,
Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty],
[IntrNoMem]>;
def int_x86_xop_vpcomfalsew :
GCCBuiltin<"__builtin_ia32_vpcomfalsew">,
Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty],
[IntrNoMem]>;
def int_x86_xop_vpcomgeb :
GCCBuiltin<"__builtin_ia32_vpcomgeb">,
Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty],
[IntrNoMem]>;
def int_x86_xop_vpcomged :
GCCBuiltin<"__builtin_ia32_vpcomged">,
Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
[IntrNoMem]>;
def int_x86_xop_vpcomgeq :
GCCBuiltin<"__builtin_ia32_vpcomgeq">,
Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
[IntrNoMem]>;
def int_x86_xop_vpcomgeub :
GCCBuiltin<"__builtin_ia32_vpcomgeub">,
Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty],
[IntrNoMem]>;
def int_x86_xop_vpcomgeud :
GCCBuiltin<"__builtin_ia32_vpcomgeud">,
Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
[IntrNoMem]>;
def int_x86_xop_vpcomgeuq :
GCCBuiltin<"__builtin_ia32_vpcomgeuq">,
Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
[IntrNoMem]>;
def int_x86_xop_vpcomgeuw :
GCCBuiltin<"__builtin_ia32_vpcomgeuw">,
Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty],
[IntrNoMem]>;
def int_x86_xop_vpcomgew :
GCCBuiltin<"__builtin_ia32_vpcomgew">,
Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty],
[IntrNoMem]>;
def int_x86_xop_vpcomgtb :
GCCBuiltin<"__builtin_ia32_vpcomgtb">,
Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty],
[IntrNoMem]>;
def int_x86_xop_vpcomgtd :
GCCBuiltin<"__builtin_ia32_vpcomgtd">,
Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
[IntrNoMem]>;
def int_x86_xop_vpcomgtq :
GCCBuiltin<"__builtin_ia32_vpcomgtq">,
Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
[IntrNoMem]>;
def int_x86_xop_vpcomgtub :
GCCBuiltin<"__builtin_ia32_vpcomgtub">,
Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty],
[IntrNoMem]>;
def int_x86_xop_vpcomgtud :
GCCBuiltin<"__builtin_ia32_vpcomgtud">,
Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
[IntrNoMem]>;
def int_x86_xop_vpcomgtuq :
GCCBuiltin<"__builtin_ia32_vpcomgtuq">,
Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
[IntrNoMem]>;
def int_x86_xop_vpcomgtuw :
GCCBuiltin<"__builtin_ia32_vpcomgtuw">,
Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty],
[IntrNoMem]>;
def int_x86_xop_vpcomgtw :
GCCBuiltin<"__builtin_ia32_vpcomgtw">,
Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty],
[IntrNoMem]>;
def int_x86_xop_vpcomleb :
GCCBuiltin<"__builtin_ia32_vpcomleb">,
Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty],
[IntrNoMem]>;
def int_x86_xop_vpcomled :
GCCBuiltin<"__builtin_ia32_vpcomled">,
Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
[IntrNoMem]>;
def int_x86_xop_vpcomleq :
GCCBuiltin<"__builtin_ia32_vpcomleq">,
Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
[IntrNoMem]>;
def int_x86_xop_vpcomleub :
GCCBuiltin<"__builtin_ia32_vpcomleub">,
Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty],
[IntrNoMem]>;
def int_x86_xop_vpcomleud :
GCCBuiltin<"__builtin_ia32_vpcomleud">,
Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
[IntrNoMem]>;
def int_x86_xop_vpcomleuq :
GCCBuiltin<"__builtin_ia32_vpcomleuq">,
Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
[IntrNoMem]>;
def int_x86_xop_vpcomleuw :
GCCBuiltin<"__builtin_ia32_vpcomleuw">,
Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty],
[IntrNoMem]>;
def int_x86_xop_vpcomlew :
GCCBuiltin<"__builtin_ia32_vpcomlew">,
Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty],
[IntrNoMem]>;
def int_x86_xop_vpcomltb :
GCCBuiltin<"__builtin_ia32_vpcomltb">,
Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty],
[IntrNoMem]>;
def int_x86_xop_vpcomltd :
GCCBuiltin<"__builtin_ia32_vpcomltd">,
Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
[IntrNoMem]>;
def int_x86_xop_vpcomltq :
GCCBuiltin<"__builtin_ia32_vpcomltq">,
Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
[IntrNoMem]>;
def int_x86_xop_vpcomltub :
GCCBuiltin<"__builtin_ia32_vpcomltub">,
Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty],
[IntrNoMem]>;
def int_x86_xop_vpcomltud :
GCCBuiltin<"__builtin_ia32_vpcomltud">,
Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
[IntrNoMem]>;
def int_x86_xop_vpcomltuq :
GCCBuiltin<"__builtin_ia32_vpcomltuq">,
Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
[IntrNoMem]>;
def int_x86_xop_vpcomltuw :
GCCBuiltin<"__builtin_ia32_vpcomltuw">,
Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty],
[IntrNoMem]>;
def int_x86_xop_vpcomltw :
GCCBuiltin<"__builtin_ia32_vpcomltw">,
Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty],
[IntrNoMem]>;
def int_x86_xop_vpcomneb :
GCCBuiltin<"__builtin_ia32_vpcomneb">,
Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty],
[IntrNoMem]>;
def int_x86_xop_vpcomned :
GCCBuiltin<"__builtin_ia32_vpcomned">,
Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
[IntrNoMem]>;
def int_x86_xop_vpcomneq :
GCCBuiltin<"__builtin_ia32_vpcomneq">,
Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
[IntrNoMem]>;
def int_x86_xop_vpcomneub :
GCCBuiltin<"__builtin_ia32_vpcomneub">,
Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty],
[IntrNoMem]>;
def int_x86_xop_vpcomneud :
GCCBuiltin<"__builtin_ia32_vpcomneud">,
Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
[IntrNoMem]>;
def int_x86_xop_vpcomneuq :
GCCBuiltin<"__builtin_ia32_vpcomneuq">,
Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
[IntrNoMem]>;
def int_x86_xop_vpcomneuw :
GCCBuiltin<"__builtin_ia32_vpcomneuw">,
Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty],
[IntrNoMem]>;
def int_x86_xop_vpcomnew :
GCCBuiltin<"__builtin_ia32_vpcomnew">,
Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty],
[IntrNoMem]>;
def int_x86_xop_vpcomtrueb :
GCCBuiltin<"__builtin_ia32_vpcomtrueb">,
Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty],
[IntrNoMem]>;
def int_x86_xop_vpcomtrued :
GCCBuiltin<"__builtin_ia32_vpcomtrued">,
Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
[IntrNoMem]>;
def int_x86_xop_vpcomtrueq :
GCCBuiltin<"__builtin_ia32_vpcomtrueq">,
Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
[IntrNoMem]>;
def int_x86_xop_vpcomtrueub :
GCCBuiltin<"__builtin_ia32_vpcomtrueub">,
Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty],
[IntrNoMem]>;
def int_x86_xop_vpcomtrueud :
GCCBuiltin<"__builtin_ia32_vpcomtrueud">,
Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
[IntrNoMem]>;
def int_x86_xop_vpcomtrueuq :
GCCBuiltin<"__builtin_ia32_vpcomtrueuq">,
Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
[IntrNoMem]>;
def int_x86_xop_vpcomtrueuw :
GCCBuiltin<"__builtin_ia32_vpcomtrueuw">,
Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty],
[IntrNoMem]>;
def int_x86_xop_vpcomtruew :
GCCBuiltin<"__builtin_ia32_vpcomtruew">,
Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty],
[IntrNoMem]>;
def int_x86_xop_vphaddbd : def int_x86_xop_vphaddbd :
GCCBuiltin<"__builtin_ia32_vphaddbd">, GCCBuiltin<"__builtin_ia32_vphaddbd">,
Intrinsic<[llvm_v4i32_ty], [llvm_v16i8_ty], [IntrNoMem]>; Intrinsic<[llvm_v4i32_ty], [llvm_v16i8_ty], [IntrNoMem]>;
def int_x86_xop_vphaddbq : def int_x86_xop_vphaddbq :
GCCBuiltin<"__builtin_ia32_vphaddbq">, GCCBuiltin<"__builtin_ia32_vphaddbq">,
Intrinsic<[llvm_v2i64_ty], [llvm_v16i8_ty], [IntrNoMem]>; Intrinsic<[llvm_v2i64_ty], [llvm_v16i8_ty], [IntrNoMem]>;
def int_x86_xop_vphaddbw : def int_x86_xop_vphaddbw :
GCCBuiltin<"__builtin_ia32_vphaddbw">, GCCBuiltin<"__builtin_ia32_vphaddbw">,
Intrinsic<[llvm_v8i16_ty], [llvm_v16i8_ty], [IntrNoMem]>; Intrinsic<[llvm_v8i16_ty], [llvm_v16i8_ty], [IntrNoMem]>;
def int_x86_xop_vphadddq : def int_x86_xop_vphadddq :
skipping to change at line 2299 skipping to change at line 2162
def int_x86_xop_vpmadcswd : def int_x86_xop_vpmadcswd :
GCCBuiltin<"__builtin_ia32_vpmadcswd">, GCCBuiltin<"__builtin_ia32_vpmadcswd">,
Intrinsic<[llvm_v4i32_ty], Intrinsic<[llvm_v4i32_ty],
[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v4i32_ty], [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v4i32_ty],
[IntrNoMem]>; [IntrNoMem]>;
def int_x86_xop_vpperm : def int_x86_xop_vpperm :
GCCBuiltin<"__builtin_ia32_vpperm">, GCCBuiltin<"__builtin_ia32_vpperm">,
Intrinsic<[llvm_v16i8_ty], Intrinsic<[llvm_v16i8_ty],
[llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty],
[IntrNoMem]>; [IntrNoMem]>;
def int_x86_xop_vprotb :
GCCBuiltin<"__builtin_ia32_vprotb">, def int_x86_xop_vprotb : GCCBuiltin<"__builtin_ia32_vprotb">,
Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty],
[IntrNoMem]>; [IntrNoMem]>;
def int_x86_xop_vprotd : def int_x86_xop_vprotd : GCCBuiltin<"__builtin_ia32_vprotd">,
GCCBuiltin<"__builtin_ia32_vprotd">,
Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
[IntrNoMem]>; [IntrNoMem]>;
def int_x86_xop_vprotq : def int_x86_xop_vprotq : GCCBuiltin<"__builtin_ia32_vprotq">,
GCCBuiltin<"__builtin_ia32_vprotq">,
Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty], Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
[IntrNoMem]>; [IntrNoMem]>;
def int_x86_xop_vprotw : def int_x86_xop_vprotw : GCCBuiltin<"__builtin_ia32_vprotw">,
GCCBuiltin<"__builtin_ia32_vprotw">,
Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty],
[IntrNoMem]>; [IntrNoMem]>;
def int_x86_xop_vprotbi : GCCBuiltin<"__builtin_ia32_vprotbi">,
Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i8_ty],
[IntrNoMem]>;
def int_x86_xop_vprotdi : GCCBuiltin<"__builtin_ia32_vprotdi">,
Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_i8_ty],
[IntrNoMem]>;
def int_x86_xop_vprotqi : GCCBuiltin<"__builtin_ia32_vprotqi">,
Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_i8_ty],
[IntrNoMem]>;
def int_x86_xop_vprotwi : GCCBuiltin<"__builtin_ia32_vprotwi">,
Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_i8_ty],
[IntrNoMem]>;
def int_x86_xop_vpshab : def int_x86_xop_vpshab :
GCCBuiltin<"__builtin_ia32_vpshab">, GCCBuiltin<"__builtin_ia32_vpshab">,
Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty],
[IntrNoMem]>; [IntrNoMem]>;
def int_x86_xop_vpshad : def int_x86_xop_vpshad :
GCCBuiltin<"__builtin_ia32_vpshad">, GCCBuiltin<"__builtin_ia32_vpshad">,
Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
[IntrNoMem]>; [IntrNoMem]>;
def int_x86_xop_vpshaq : def int_x86_xop_vpshaq :
GCCBuiltin<"__builtin_ia32_vpshaq">, GCCBuiltin<"__builtin_ia32_vpshaq">,
skipping to change at line 2677 skipping to change at line 2550
Intrinsic<[llvm_v4f32_ty], [llvm_v8i16_ty], [IntrNoMem]>; Intrinsic<[llvm_v4f32_ty], [llvm_v8i16_ty], [IntrNoMem]>;
def int_x86_vcvtph2ps_256 : GCCBuiltin<"__builtin_ia32_vcvtph2ps256">, def int_x86_vcvtph2ps_256 : GCCBuiltin<"__builtin_ia32_vcvtph2ps256">,
Intrinsic<[llvm_v8f32_ty], [llvm_v8i16_ty], [IntrNoMem]>; Intrinsic<[llvm_v8f32_ty], [llvm_v8i16_ty], [IntrNoMem]>;
def int_x86_vcvtps2ph_128 : GCCBuiltin<"__builtin_ia32_vcvtps2ph">, def int_x86_vcvtps2ph_128 : GCCBuiltin<"__builtin_ia32_vcvtps2ph">,
Intrinsic<[llvm_v8i16_ty], [llvm_v4f32_ty, llvm_i32_ty], Intrinsic<[llvm_v8i16_ty], [llvm_v4f32_ty, llvm_i32_ty],
[IntrNoMem]>; [IntrNoMem]>;
def int_x86_vcvtps2ph_256 : GCCBuiltin<"__builtin_ia32_vcvtps2ph256">, def int_x86_vcvtps2ph_256 : GCCBuiltin<"__builtin_ia32_vcvtps2ph256">,
Intrinsic<[llvm_v8i16_ty], [llvm_v8f32_ty, llvm_i32_ty], Intrinsic<[llvm_v8i16_ty], [llvm_v8f32_ty, llvm_i32_ty],
[IntrNoMem]>; [IntrNoMem]>;
} }
//===----------------------------------------------------------------------
===//
// RDRAND intrinsics. Return a random value and whether it is valid.
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
// These are declared side-effecting so they don't get eliminated by CSE
or
// LICM.
def int_x86_rdrand_16 : Intrinsic<[llvm_i16_ty, llvm_i32_ty], [], []>;
def int_x86_rdrand_32 : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [], []>;
def int_x86_rdrand_64 : Intrinsic<[llvm_i64_ty, llvm_i32_ty], [], []>;
}
//===----------------------------------------------------------------------
===//
// RTM intrinsics. Transactional Memory support.
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_xbegin : GCCBuiltin<"__builtin_ia32_xbegin">,
Intrinsic<[llvm_i32_ty], [], []>;
def int_x86_xend : GCCBuiltin<"__builtin_ia32_xend">,
Intrinsic<[], [], []>;
def int_x86_xabort : GCCBuiltin<"__builtin_ia32_xabort">,
Intrinsic<[], [llvm_i8_ty], [IntrNoReturn]>;
}
 End of changes. 77 change blocks. 
360 lines changed or deleted 253 lines changed or added


 IntrusiveRefCntPtr.h   IntrusiveRefCntPtr.h 
skipping to change at line 24 skipping to change at line 24
// managed using reference counting. // managed using reference counting.
// //
// IntrusiveRefCntPtr is similar to Boost's intrusive_ptr with added // IntrusiveRefCntPtr is similar to Boost's intrusive_ptr with added
// LLVM-style casting. // LLVM-style casting.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_ADT_INTRUSIVE_REF_CNT_PTR #ifndef LLVM_ADT_INTRUSIVE_REF_CNT_PTR
#define LLVM_ADT_INTRUSIVE_REF_CNT_PTR #define LLVM_ADT_INTRUSIVE_REF_CNT_PTR
#include <cassert>
#include "llvm/Support/Casting.h" #include "llvm/Support/Casting.h"
#include "llvm/Support/Compiler.h"
#include <memory>
namespace llvm { namespace llvm {
template <class T> template <class T>
class IntrusiveRefCntPtr; class IntrusiveRefCntPtr;
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
/// RefCountedBase - A generic base class for objects that wish to /// RefCountedBase - A generic base class for objects that wish to
/// have their lifetimes managed using reference counts. Classes /// have their lifetimes managed using reference counts. Classes
/// subclass RefCountedBase to obtain such functionality, and are /// subclass RefCountedBase to obtain such functionality, and are
/// typically handled with IntrusivePtr "smart pointers" (see below) /// typically handled with IntrusiveRefCntPtr "smart pointers" (see below)
/// which automatically handle the management of reference counts. /// which automatically handle the management of reference counts.
/// Objects that subclass RefCountedBase should not be allocated on /// Objects that subclass RefCountedBase should not be allocated on
/// the stack, as invoking "delete" (which is called when the /// the stack, as invoking "delete" (which is called when the
/// reference count hits 0) on such objects is an error. /// reference count hits 0) on such objects is an error.
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
template <class Derived> template <class Derived>
class RefCountedBase { class RefCountedBase {
mutable unsigned ref_cnt; mutable unsigned ref_cnt;
public: public:
skipping to change at line 125 skipping to change at line 125
explicit IntrusiveRefCntPtr() : Obj(0) {} explicit IntrusiveRefCntPtr() : Obj(0) {}
IntrusiveRefCntPtr(T* obj) : Obj(obj) { IntrusiveRefCntPtr(T* obj) : Obj(obj) {
retain(); retain();
} }
IntrusiveRefCntPtr(const IntrusiveRefCntPtr& S) : Obj(S.Obj) { IntrusiveRefCntPtr(const IntrusiveRefCntPtr& S) : Obj(S.Obj) {
retain(); retain();
} }
template <class X> #if LLVM_USE_RVALUE_REFERENCES
IntrusiveRefCntPtr(const IntrusiveRefCntPtr<X>& S) IntrusiveRefCntPtr(IntrusiveRefCntPtr&& S) : Obj(S.Obj) {
: Obj(S.getPtr()) { S.Obj = 0;
retain();
} }
IntrusiveRefCntPtr& operator=(const IntrusiveRefCntPtr& S) { template <class X>
replace(S.getPtr()); IntrusiveRefCntPtr(IntrusiveRefCntPtr<X>&& S) : Obj(S.getPtr()) {
return *this; S.Obj = 0;
} }
#endif
template <class X> template <class X>
IntrusiveRefCntPtr& operator=(const IntrusiveRefCntPtr<X>& S) { IntrusiveRefCntPtr(const IntrusiveRefCntPtr<X>& S)
replace(S.getPtr()); : Obj(S.getPtr()) {
return *this; retain();
} }
IntrusiveRefCntPtr& operator=(T * S) { IntrusiveRefCntPtr& operator=(IntrusiveRefCntPtr S) {
replace(S); swap(S);
return *this; return *this;
} }
~IntrusiveRefCntPtr() { release(); } ~IntrusiveRefCntPtr() { release(); }
T& operator*() const { return *Obj; } T& operator*() const { return *Obj; }
T* operator->() const { return Obj; } T* operator->() const { return Obj; }
T* getPtr() const { return Obj; } T* getPtr() const { return Obj; }
skipping to change at line 178 skipping to change at line 178
Obj = 0; Obj = 0;
} }
void resetWithoutRelease() { void resetWithoutRelease() {
Obj = 0; Obj = 0;
} }
private: private:
void retain() { if (Obj) IntrusiveRefCntPtrInfo<T>::retain(Obj); } void retain() { if (Obj) IntrusiveRefCntPtrInfo<T>::retain(Obj); }
void release() { if (Obj) IntrusiveRefCntPtrInfo<T>::release(Obj); } void release() { if (Obj) IntrusiveRefCntPtrInfo<T>::release(Obj); }
void replace(T* S) {
this_type(S).swap(*this);
}
}; };
template<class T, class U> template<class T, class U>
inline bool operator==(const IntrusiveRefCntPtr<T>& A, inline bool operator==(const IntrusiveRefCntPtr<T>& A,
const IntrusiveRefCntPtr<U>& B) const IntrusiveRefCntPtr<U>& B)
{ {
return A.getPtr() == B.getPtr(); return A.getPtr() == B.getPtr();
} }
template<class T, class U> template<class T, class U>
 End of changes. 9 change blocks. 
19 lines changed or deleted 15 lines changed or added


 JIT.h   JIT.h 
skipping to change at line 26 skipping to change at line 26
#define LLVM_EXECUTION_ENGINE_JIT_H #define LLVM_EXECUTION_ENGINE_JIT_H
#include "llvm/ExecutionEngine/ExecutionEngine.h" #include "llvm/ExecutionEngine/ExecutionEngine.h"
#include <cstdlib> #include <cstdlib>
extern "C" void LLVMLinkInJIT(); extern "C" void LLVMLinkInJIT();
namespace { namespace {
struct ForceJITLinking { struct ForceJITLinking {
ForceJITLinking() { ForceJITLinking() {
// We must reference the passes in such a way that compilers will not // We must reference JIT in such a way that compilers will not
// delete it all as dead code, even with whole program optimization, // delete it all as dead code, even with whole program optimization,
// yet is effectively a NO-OP. As the compiler isn't smart enough // yet is effectively a NO-OP. As the compiler isn't smart enough
// to know that getenv() never returns -1, this will do the job. // to know that getenv() never returns -1, this will do the job.
if (std::getenv("bar") != (char*) -1) if (std::getenv("bar") != (char*) -1)
return; return;
LLVMLinkInJIT(); LLVMLinkInJIT();
} }
} ForceJITLinking; } ForceJITLinking;
} }
 End of changes. 1 change blocks. 
1 lines changed or deleted 1 lines changed or added


 JITEventListener.h   JITEventListener.h 
skipping to change at line 29 skipping to change at line 29
#include "llvm/Support/DataTypes.h" #include "llvm/Support/DataTypes.h"
#include "llvm/Support/DebugLoc.h" #include "llvm/Support/DebugLoc.h"
#include <vector> #include <vector>
namespace llvm { namespace llvm {
class Function; class Function;
class MachineFunction; class MachineFunction;
class OProfileWrapper; class OProfileWrapper;
class IntelJITEventsWrapper; class IntelJITEventsWrapper;
class ObjectImage;
/// JITEvent_EmittedFunctionDetails - Helper struct for containing informat ion /// JITEvent_EmittedFunctionDetails - Helper struct for containing informat ion
/// about a generated machine code function. /// about a generated machine code function.
struct JITEvent_EmittedFunctionDetails { struct JITEvent_EmittedFunctionDetails {
struct LineStart { struct LineStart {
/// The address at which the current line changes. /// The address at which the current line changes.
uintptr_t Address; uintptr_t Address;
/// The new location information. These can be translated to DebugLocT uples /// The new location information. These can be translated to DebugLocT uples
/// using MF->getDebugLocTuple(). /// using MF->getDebugLocTuple().
skipping to change at line 79 skipping to change at line 80
/// NotifyFreeingMachineCode - Called from freeMachineCodeForFunction(), after /// NotifyFreeingMachineCode - Called from freeMachineCodeForFunction(), after
/// the global mapping is removed, but before the machine code is returne d to /// the global mapping is removed, but before the machine code is returne d to
/// the allocator. /// the allocator.
/// ///
/// OldPtr is the address of the machine code and will be the same as the Code /// OldPtr is the address of the machine code and will be the same as the Code
/// parameter to a previous NotifyFunctionEmitted call. The Function pas sed /// parameter to a previous NotifyFunctionEmitted call. The Function pas sed
/// to NotifyFunctionEmitted may have been destroyed by the time of the /// to NotifyFunctionEmitted may have been destroyed by the time of the
/// matching NotifyFreeingMachineCode call. /// matching NotifyFreeingMachineCode call.
virtual void NotifyFreeingMachineCode(void *) {} virtual void NotifyFreeingMachineCode(void *) {}
/// NotifyObjectEmitted - Called after an object has been successfully
/// emitted to memory. NotifyFunctionEmitted will not be called for
/// individual functions in the object.
///
/// ELF-specific information
/// The ObjectImage contains the generated object image
/// with section headers updated to reflect the address at which sections
/// were loaded and with relocations performed in-place on debug sections
.
virtual void NotifyObjectEmitted(const ObjectImage &Obj) {}
/// NotifyFreeingObject - Called just before the memory associated with
/// a previously emitted object is released.
virtual void NotifyFreeingObject(const ObjectImage &Obj) {}
#if LLVM_USE_INTEL_JITEVENTS #if LLVM_USE_INTEL_JITEVENTS
// Construct an IntelJITEventListener // Construct an IntelJITEventListener
static JITEventListener *createIntelJITEventListener(); static JITEventListener *createIntelJITEventListener();
// Construct an IntelJITEventListener with a test Intel JIT API implement ation // Construct an IntelJITEventListener with a test Intel JIT API implement ation
static JITEventListener *createIntelJITEventListener( static JITEventListener *createIntelJITEventListener(
IntelJITEventsWrapper* AlternativeImp l); IntelJITEventsWrapper* AlternativeImp l);
#else #else
static JITEventListener *createIntelJITEventListener() { return 0; } static JITEventListener *createIntelJITEventListener() { return 0; }
 End of changes. 2 change blocks. 
0 lines changed or deleted 16 lines changed or added


 JITMemoryManager.h   JITMemoryManager.h 
skipping to change at line 13 skipping to change at line 13
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
// //
// This file is distributed under the University of Illinois Open Source // This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details. // License. See LICENSE.TXT for details.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_EXECUTION_ENGINE_JIT_MEMMANAGER_H #ifndef LLVM_EXECUTION_ENGINE_JIT_MEMMANAGER_H
#define LLVM_EXECUTION_ENGINE_JIT_MEMMANAGER_H #define LLVM_EXECUTION_ENGINE_JIT_MEMMANAGER_H
#include "llvm/ExecutionEngine/RuntimeDyld.h"
#include "llvm/Support/DataTypes.h" #include "llvm/Support/DataTypes.h"
#include <string> #include <string>
namespace llvm { namespace llvm {
class Function; class Function;
class GlobalValue; class GlobalValue;
/// JITMemoryManager - This interface is used by the JIT to allocate and ma nage /// JITMemoryManager - This interface is used by the JIT to allocate and ma nage
/// memory for the code generated by the JIT. This can be reimplemented by /// memory for the code generated by the JIT. This can be reimplemented by
/// clients that have a strong desire to control how the layout of JIT'd me mory /// clients that have a strong desire to control how the layout of JIT'd me mory
/// works. /// works.
class JITMemoryManager { class JITMemoryManager : public RTDyldMemoryManager {
protected: protected:
bool HasGOT; bool HasGOT;
public: public:
JITMemoryManager() : HasGOT(false) {} JITMemoryManager() : HasGOT(false) {}
virtual ~JITMemoryManager(); virtual ~JITMemoryManager();
/// CreateDefaultMemManager - This is used to create the default /// CreateDefaultMemManager - This is used to create the default
/// JIT Memory Manager if the client does not provide one to the JIT. /// JIT Memory Manager if the client does not provide one to the JIT.
static JITMemoryManager *CreateDefaultMemManager(); static JITMemoryManager *CreateDefaultMemManager();
skipping to change at line 50 skipping to change at line 52
/// setMemoryExecutable - When code generation is done and we're ready to /// setMemoryExecutable - When code generation is done and we're ready to
/// start execution, the code pages may need permissions changed. /// start execution, the code pages may need permissions changed.
virtual void setMemoryExecutable() = 0; virtual void setMemoryExecutable() = 0;
/// setPoisonMemory - Setting this flag to true makes the memory manager /// setPoisonMemory - Setting this flag to true makes the memory manager
/// garbage values over freed memory. This is useful for testing and /// garbage values over freed memory. This is useful for testing and
/// debugging, and may be turned on by default in debug mode. /// debugging, and may be turned on by default in debug mode.
virtual void setPoisonMemory(bool poison) = 0; virtual void setPoisonMemory(bool poison) = 0;
/// getPointerToNamedFunction - This method returns the address of the
/// specified function. As such it is only useful for resolving library
/// symbols, not code generated symbols.
///
/// If AbortOnFailure is false and no function with the given name is
/// found, this function silently returns a null pointer. Otherwise,
/// it prints a message to stderr and aborts.
///
virtual void *getPointerToNamedFunction(const std::string &Name,
bool AbortOnFailure = true) = 0;
//===-------------------------------------------------------------------- ===// //===-------------------------------------------------------------------- ===//
// Global Offset Table Management // Global Offset Table Management
//===-------------------------------------------------------------------- ===// //===-------------------------------------------------------------------- ===//
/// AllocateGOT - If the current table requires a Global Offset Table, th is /// AllocateGOT - If the current table requires a Global Offset Table, th is
/// method is invoked to allocate it. This method is required to set Has GOT /// method is invoked to allocate it. This method is required to set Has GOT
/// to true. /// to true.
virtual void AllocateGOT() = 0; virtual void AllocateGOT() = 0;
/// isManagingGOT - Return true if the AllocateGOT method is called. /// isManagingGOT - Return true if the AllocateGOT method is called.
skipping to change at line 115 skipping to change at line 106
/// endFunctionBody - This method is called when the JIT is done codegen' ing /// endFunctionBody - This method is called when the JIT is done codegen' ing
/// the specified function. At this point we know the size of the JIT /// the specified function. At this point we know the size of the JIT
/// compiled function. This passes in FunctionStart (which was returned by /// compiled function. This passes in FunctionStart (which was returned by
/// the startFunctionBody method) and FunctionEnd which is a pointer to t he /// the startFunctionBody method) and FunctionEnd which is a pointer to t he
/// actual end of the function. This method should mark the space alloca ted /// actual end of the function. This method should mark the space alloca ted
/// and remember where it is in case the client wants to deallocate it. /// and remember where it is in case the client wants to deallocate it.
virtual void endFunctionBody(const Function *F, uint8_t *FunctionStart, virtual void endFunctionBody(const Function *F, uint8_t *FunctionStart,
uint8_t *FunctionEnd) = 0; uint8_t *FunctionEnd) = 0;
/// allocateCodeSection - Allocate a memory block of (at least) the given
/// size suitable for executable code. The SectionID is a unique identifi
er
/// assigned by the JIT and passed through to the memory manager for
/// the instance class to use if it needs to communicate to the JIT about
/// a given section after the fact.
virtual uint8_t *allocateCodeSection(uintptr_t Size, unsigned Alignment,
unsigned SectionID) = 0;
/// allocateDataSection - Allocate a memory block of (at least) the given
/// size suitable for data. The SectionID is a unique identifier
/// assigned by the JIT and passed through to the memory manager for
/// the instance class to use if it needs to communicate to the JIT about
/// a given section after the fact.
virtual uint8_t *allocateDataSection(uintptr_t Size, unsigned Alignment,
unsigned SectionID) = 0;
/// allocateSpace - Allocate a memory block of the given size. This meth od /// allocateSpace - Allocate a memory block of the given size. This meth od
/// cannot be called between calls to startFunctionBody and endFunctionBo dy. /// cannot be called between calls to startFunctionBody and endFunctionBo dy.
virtual uint8_t *allocateSpace(intptr_t Size, unsigned Alignment) = 0; virtual uint8_t *allocateSpace(intptr_t Size, unsigned Alignment) = 0;
/// allocateGlobal - Allocate memory for a global. /// allocateGlobal - Allocate memory for a global.
virtual uint8_t *allocateGlobal(uintptr_t Size, unsigned Alignment) = 0; virtual uint8_t *allocateGlobal(uintptr_t Size, unsigned Alignment) = 0;
/// deallocateFunctionBody - Free the specified function body. The argum ent /// deallocateFunctionBody - Free the specified function body. The argum ent
/// must be the return value from a call to startFunctionBody() that hasn 't /// must be the return value from a call to startFunctionBody() that hasn 't
/// been deallocated yet. This is never called when the JIT is currently /// been deallocated yet. This is never called when the JIT is currently
 End of changes. 5 change blocks. 
29 lines changed or deleted 3 lines changed or added


 LLVMBitCodes.h   LLVMBitCodes.h 
skipping to change at line 163 skipping to change at line 163
CST_CODE_STRING = 8, // STRING: [values] CST_CODE_STRING = 8, // STRING: [values]
CST_CODE_CSTRING = 9, // CSTRING: [values] CST_CODE_CSTRING = 9, // CSTRING: [values]
CST_CODE_CE_BINOP = 10, // CE_BINOP: [opcode, opval, opval] CST_CODE_CE_BINOP = 10, // CE_BINOP: [opcode, opval, opval]
CST_CODE_CE_CAST = 11, // CE_CAST: [opcode, opty, opval] CST_CODE_CE_CAST = 11, // CE_CAST: [opcode, opty, opval]
CST_CODE_CE_GEP = 12, // CE_GEP: [n x operands] CST_CODE_CE_GEP = 12, // CE_GEP: [n x operands]
CST_CODE_CE_SELECT = 13, // CE_SELECT: [opval, opval, opval] CST_CODE_CE_SELECT = 13, // CE_SELECT: [opval, opval, opval]
CST_CODE_CE_EXTRACTELT = 14, // CE_EXTRACTELT: [opty, opval, opval] CST_CODE_CE_EXTRACTELT = 14, // CE_EXTRACTELT: [opty, opval, opval]
CST_CODE_CE_INSERTELT = 15, // CE_INSERTELT: [opval, opval, opval] CST_CODE_CE_INSERTELT = 15, // CE_INSERTELT: [opval, opval, opval]
CST_CODE_CE_SHUFFLEVEC = 16, // CE_SHUFFLEVEC: [opval, opval, opval] CST_CODE_CE_SHUFFLEVEC = 16, // CE_SHUFFLEVEC: [opval, opval, opval]
CST_CODE_CE_CMP = 17, // CE_CMP: [opty, opval, opval, pr ed] CST_CODE_CE_CMP = 17, // CE_CMP: [opty, opval, opval, pr ed]
CST_CODE_INLINEASM = 18, // INLINEASM: [sideeffect,asmstr,cons CST_CODE_INLINEASM_OLD = 18, // INLINEASM: [sideeffect|alignstack,
tstr] // asmstr,conststr]
CST_CODE_CE_SHUFVEC_EX = 19, // SHUFVEC_EX: [opty, opval, opval, op val] CST_CODE_CE_SHUFVEC_EX = 19, // SHUFVEC_EX: [opty, opval, opval, op val]
CST_CODE_CE_INBOUNDS_GEP = 20,// INBOUNDS_GEP: [n x operands] CST_CODE_CE_INBOUNDS_GEP = 20,// INBOUNDS_GEP: [n x operands]
CST_CODE_BLOCKADDRESS = 21, // CST_CODE_BLOCKADDRESS [fnty, fnval, bb #] CST_CODE_BLOCKADDRESS = 21, // CST_CODE_BLOCKADDRESS [fnty, fnval, bb #]
CST_CODE_DATA = 22 // DATA: [n x elements] CST_CODE_DATA = 22, // DATA: [n x elements]
CST_CODE_INLINEASM = 23 // INLINEASM: [sideeffect|alignstack|
// asmdialect,asmstr,cons
tstr]
}; };
/// CastOpcodes - These are values used in the bitcode files to encode wh ich /// CastOpcodes - These are values used in the bitcode files to encode wh ich
/// cast a CST_CODE_CE_CAST or a XXX refers to. The values of these enum s /// cast a CST_CODE_CE_CAST or a XXX refers to. The values of these enum s
/// have no fixed relation to the LLVM IR enum values. Changing these wi ll /// have no fixed relation to the LLVM IR enum values. Changing these wi ll
/// break compatibility with old files. /// break compatibility with old files.
enum CastOpcodes { enum CastOpcodes {
CAST_TRUNC = 0, CAST_TRUNC = 0,
CAST_ZEXT = 1, CAST_ZEXT = 1,
CAST_SEXT = 2, CAST_SEXT = 2,
 End of changes. 2 change blocks. 
3 lines changed or deleted 6 lines changed or added


 LLVMContext.h   LLVMContext.h 
skipping to change at line 18 skipping to change at line 18
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// //
// This file declares LLVMContext, a container of "global" state in LLVM, s uch // This file declares LLVMContext, a container of "global" state in LLVM, s uch
// as the global type and constant uniquing tables. // as the global type and constant uniquing tables.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_LLVMCONTEXT_H #ifndef LLVM_LLVMCONTEXT_H
#define LLVM_LLVMCONTEXT_H #define LLVM_LLVMCONTEXT_H
#include "llvm/Support/Compiler.h"
namespace llvm { namespace llvm {
class LLVMContextImpl; class LLVMContextImpl;
class StringRef; class StringRef;
class Twine; class Twine;
class Instruction; class Instruction;
class Module; class Module;
class SMDiagnostic; class SMDiagnostic;
template <typename T> class SmallVectorImpl; template <typename T> class SmallVectorImpl;
skipping to change at line 46 skipping to change at line 48
LLVMContext(); LLVMContext();
~LLVMContext(); ~LLVMContext();
// Pinned metadata names, which always have the same value. This is a // Pinned metadata names, which always have the same value. This is a
// compile-time performance optimization, not a correctness optimization. // compile-time performance optimization, not a correctness optimization.
enum { enum {
MD_dbg = 0, // "dbg" MD_dbg = 0, // "dbg"
MD_tbaa = 1, // "tbaa" MD_tbaa = 1, // "tbaa"
MD_prof = 2, // "prof" MD_prof = 2, // "prof"
MD_fpmath = 3, // "fpmath" MD_fpmath = 3, // "fpmath"
MD_range = 4 // "range" MD_range = 4, // "range"
MD_tbaa_struct = 5 // "tbaa.struct"
}; };
/// getMDKindID - Return a unique non-zero ID for the specified metadata kind. /// getMDKindID - Return a unique non-zero ID for the specified metadata kind.
/// This ID is uniqued across modules in the current LLVMContext. /// This ID is uniqued across modules in the current LLVMContext.
unsigned getMDKindID(StringRef Name) const; unsigned getMDKindID(StringRef Name) const;
/// getMDKindNames - Populate client supplied SmallVector with the name f or /// getMDKindNames - Populate client supplied SmallVector with the name f or
/// custom metadata IDs registered in this LLVMContext. /// custom metadata IDs registered in this LLVMContext.
void getMDKindNames(SmallVectorImpl<StringRef> &Result) const; void getMDKindNames(SmallVectorImpl<StringRef> &Result) const;
skipping to change at line 88 skipping to change at line 91
/// emitError - Emit an error message to the currently installed error ha ndler /// emitError - Emit an error message to the currently installed error ha ndler
/// with optional location information. This function returns, so code s hould /// with optional location information. This function returns, so code s hould
/// be prepared to drop the erroneous construct on the floor and "not cra sh". /// be prepared to drop the erroneous construct on the floor and "not cra sh".
/// The generated code need not be correct. The error message will be /// The generated code need not be correct. The error message will be
/// implicitly prefixed with "error: " and should not end with a ".". /// implicitly prefixed with "error: " and should not end with a ".".
void emitError(unsigned LocCookie, const Twine &ErrorStr); void emitError(unsigned LocCookie, const Twine &ErrorStr);
void emitError(const Instruction *I, const Twine &ErrorStr); void emitError(const Instruction *I, const Twine &ErrorStr);
void emitError(const Twine &ErrorStr); void emitError(const Twine &ErrorStr);
private: private:
// DO NOT IMPLEMENT LLVMContext(LLVMContext&) LLVM_DELETED_FUNCTION;
LLVMContext(LLVMContext&); void operator=(LLVMContext&) LLVM_DELETED_FUNCTION;
void operator=(LLVMContext&);
/// addModule - Register a module as being instantiated in this context. If /// addModule - Register a module as being instantiated in this context. If
/// the context is deleted, the module will be deleted as well. /// the context is deleted, the module will be deleted as well.
void addModule(Module*); void addModule(Module*);
/// removeModule - Unregister a module from this context. /// removeModule - Unregister a module from this context.
void removeModule(Module*); void removeModule(Module*);
// Module needs access to the add/removeModule methods. // Module needs access to the add/removeModule methods.
friend class Module; friend class Module;
 End of changes. 3 change blocks. 
4 lines changed or deleted 6 lines changed or added


 LazyValueInfo.h   LazyValueInfo.h 
skipping to change at line 22 skipping to change at line 22
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_ANALYSIS_LAZYVALUEINFO_H #ifndef LLVM_ANALYSIS_LAZYVALUEINFO_H
#define LLVM_ANALYSIS_LAZYVALUEINFO_H #define LLVM_ANALYSIS_LAZYVALUEINFO_H
#include "llvm/Pass.h" #include "llvm/Pass.h"
namespace llvm { namespace llvm {
class Constant; class Constant;
class TargetData; class DataLayout;
class TargetLibraryInfo; class TargetLibraryInfo;
class Value; class Value;
/// LazyValueInfo - This pass computes, caches, and vends lazy value constr aint /// LazyValueInfo - This pass computes, caches, and vends lazy value constr aint
/// information. /// information.
class LazyValueInfo : public FunctionPass { class LazyValueInfo : public FunctionPass {
class TargetData *TD; class DataLayout *TD;
class TargetLibraryInfo *TLI; class TargetLibraryInfo *TLI;
void *PImpl; void *PImpl;
LazyValueInfo(const LazyValueInfo&); // DO NOT IMPLEMENT. LazyValueInfo(const LazyValueInfo&) LLVM_DELETED_FUNCTION;
void operator=(const LazyValueInfo&); // DO NOT IMPLEMENT. void operator=(const LazyValueInfo&) LLVM_DELETED_FUNCTION;
public: public:
static char ID; static char ID;
LazyValueInfo() : FunctionPass(ID), PImpl(0) { LazyValueInfo() : FunctionPass(ID), PImpl(0) {
initializeLazyValueInfoPass(*PassRegistry::getPassRegistry()); initializeLazyValueInfoPass(*PassRegistry::getPassRegistry());
} }
~LazyValueInfo() { assert(PImpl == 0 && "releaseMemory not called"); } ~LazyValueInfo() { assert(PImpl == 0 && "releaseMemory not called"); }
/// Tristate - This is used to return true/false/dunno results. /// Tristate - This is used to return true/false/dunno results.
enum Tristate { enum Tristate {
Unknown = -1, False = 0, True = 1 Unknown = -1, False = 0, True = 1
 End of changes. 3 change blocks. 
4 lines changed or deleted 4 lines changed or added


 LexicalScopes.h   LexicalScopes.h 
skipping to change at line 161 skipping to change at line 161
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
/// LexicalScope - This class is used to track scope information. /// LexicalScope - This class is used to track scope information.
/// ///
class LexicalScope { class LexicalScope {
virtual void anchor(); virtual void anchor();
public: public:
LexicalScope(LexicalScope *P, const MDNode *D, const MDNode *I, bool A) LexicalScope(LexicalScope *P, const MDNode *D, const MDNode *I, bool A)
: Parent(P), Desc(D), InlinedAtLocation(I), AbstractScope(A), : Parent(P), Desc(D), InlinedAtLocation(I), AbstractScope(A),
LastInsn(0), FirstInsn(0), DFSIn(0), DFSOut(0), IndentLevel(0) { LastInsn(0), FirstInsn(0), DFSIn(0), DFSOut(0) {
#ifndef NDEBUG
IndentLevel = 0;
#endif
if (Parent) if (Parent)
Parent->addChild(this); Parent->addChild(this);
} }
virtual ~LexicalScope() {} virtual ~LexicalScope() {}
// Accessors. // Accessors.
LexicalScope *getParent() const { return Parent; } LexicalScope *getParent() const { return Parent; }
const MDNode *getDesc() const { return Desc; } const MDNode *getDesc() const { return Desc; }
const MDNode *getInlinedAt() const { return InlinedAtLocation; } const MDNode *getInlinedAt() const { return InlinedAtLocation; }
skipping to change at line 244 skipping to change at line 247
// scope is inlined. // scope is inlined.
bool AbstractScope; // Abstract Scope bool AbstractScope; // Abstract Scope
SmallVector<LexicalScope *, 4> Children; // Scopes defined in scope . SmallVector<LexicalScope *, 4> Children; // Scopes defined in scope .
// Contents not owned. // Contents not owned.
SmallVector<InsnRange, 4> Ranges; SmallVector<InsnRange, 4> Ranges;
const MachineInstr *LastInsn; // Last instruction of this scope. const MachineInstr *LastInsn; // Last instruction of this scope.
const MachineInstr *FirstInsn; // First instruction of this scope. const MachineInstr *FirstInsn; // First instruction of this scope.
unsigned DFSIn, DFSOut; // In & Out Depth use to determine unsigned DFSIn, DFSOut; // In & Out Depth use to determine
// scope nesting. // scope nesting.
#ifndef NDEBUG
mutable unsigned IndentLevel; // Private state for dump() mutable unsigned IndentLevel; // Private state for dump()
#endif
}; };
} // end llvm namespace } // end llvm namespace
#endif #endif
 End of changes. 3 change blocks. 
1 lines changed or deleted 6 lines changed or added


 LinkAllPasses.h   LinkAllPasses.h 
skipping to change at line 58 skipping to change at line 58
(void) llvm::createAAEvalPass(); (void) llvm::createAAEvalPass();
(void) llvm::createAggressiveDCEPass(); (void) llvm::createAggressiveDCEPass();
(void) llvm::createAliasAnalysisCounterPass(); (void) llvm::createAliasAnalysisCounterPass();
(void) llvm::createAliasDebugger(); (void) llvm::createAliasDebugger();
(void) llvm::createArgumentPromotionPass(); (void) llvm::createArgumentPromotionPass();
(void) llvm::createBasicAliasAnalysisPass(); (void) llvm::createBasicAliasAnalysisPass();
(void) llvm::createLibCallAliasAnalysisPass(0); (void) llvm::createLibCallAliasAnalysisPass(0);
(void) llvm::createScalarEvolutionAliasAnalysisPass(); (void) llvm::createScalarEvolutionAliasAnalysisPass();
(void) llvm::createTypeBasedAliasAnalysisPass(); (void) llvm::createTypeBasedAliasAnalysisPass();
(void) llvm::createBlockPlacementPass(); (void) llvm::createBlockPlacementPass();
(void) llvm::createBoundsCheckingPass();
(void) llvm::createBreakCriticalEdgesPass(); (void) llvm::createBreakCriticalEdgesPass();
(void) llvm::createCFGSimplificationPass(); (void) llvm::createCFGSimplificationPass();
(void) llvm::createConstantMergePass(); (void) llvm::createConstantMergePass();
(void) llvm::createConstantPropagationPass(); (void) llvm::createConstantPropagationPass();
(void) llvm::createCostModelAnalysisPass();
(void) llvm::createDeadArgEliminationPass(); (void) llvm::createDeadArgEliminationPass();
(void) llvm::createDeadCodeEliminationPass(); (void) llvm::createDeadCodeEliminationPass();
(void) llvm::createDeadInstEliminationPass(); (void) llvm::createDeadInstEliminationPass();
(void) llvm::createDeadStoreEliminationPass(); (void) llvm::createDeadStoreEliminationPass();
(void) llvm::createDependenceAnalysisPass();
(void) llvm::createDomOnlyPrinterPass(); (void) llvm::createDomOnlyPrinterPass();
(void) llvm::createDomPrinterPass(); (void) llvm::createDomPrinterPass();
(void) llvm::createDomOnlyViewerPass(); (void) llvm::createDomOnlyViewerPass();
(void) llvm::createDomViewerPass(); (void) llvm::createDomViewerPass();
(void) llvm::createEdgeProfilerPass(); (void) llvm::createEdgeProfilerPass();
(void) llvm::createOptimalEdgeProfilerPass(); (void) llvm::createOptimalEdgeProfilerPass();
(void) llvm::createPathProfilerPass(); (void) llvm::createPathProfilerPass();
(void) llvm::createGCOVProfilerPass(); (void) llvm::createGCOVProfilerPass();
(void) llvm::createFunctionInliningPass(); (void) llvm::createFunctionInliningPass();
(void) llvm::createAlwaysInlinerPass(); (void) llvm::createAlwaysInlinerPass();
(void) llvm::createGlobalDCEPass(); (void) llvm::createGlobalDCEPass();
(void) llvm::createGlobalOptimizerPass(); (void) llvm::createGlobalOptimizerPass();
(void) llvm::createGlobalsModRefPass(); (void) llvm::createGlobalsModRefPass();
(void) llvm::createIPConstantPropagationPass(); (void) llvm::createIPConstantPropagationPass();
(void) llvm::createIPSCCPPass(); (void) llvm::createIPSCCPPass();
(void) llvm::createIndVarSimplifyPass(); (void) llvm::createIndVarSimplifyPass();
(void) llvm::createInstructionCombiningPass(); (void) llvm::createInstructionCombiningPass();
(void) llvm::createInternalizePass(false); (void) llvm::createInternalizePass();
(void) llvm::createLCSSAPass(); (void) llvm::createLCSSAPass();
(void) llvm::createLICMPass(); (void) llvm::createLICMPass();
(void) llvm::createLazyValueInfoPass(); (void) llvm::createLazyValueInfoPass();
(void) llvm::createLoopDependenceAnalysisPass();
(void) llvm::createLoopExtractorPass(); (void) llvm::createLoopExtractorPass();
(void) llvm::createLoopSimplifyPass(); (void) llvm::createLoopSimplifyPass();
(void) llvm::createLoopStrengthReducePass(); (void) llvm::createLoopStrengthReducePass();
(void) llvm::createLoopUnrollPass(); (void) llvm::createLoopUnrollPass();
(void) llvm::createLoopUnswitchPass(); (void) llvm::createLoopUnswitchPass();
(void) llvm::createLoopIdiomPass(); (void) llvm::createLoopIdiomPass();
(void) llvm::createLoopRotatePass(); (void) llvm::createLoopRotatePass();
(void) llvm::createLowerExpectIntrinsicPass(); (void) llvm::createLowerExpectIntrinsicPass();
(void) llvm::createLowerInvokePass(); (void) llvm::createLowerInvokePass();
(void) llvm::createLowerSwitchPass(); (void) llvm::createLowerSwitchPass();
skipping to change at line 109 skipping to change at line 111
(void) llvm::createNoProfileInfoPass(); (void) llvm::createNoProfileInfoPass();
(void) llvm::createObjCARCAliasAnalysisPass(); (void) llvm::createObjCARCAliasAnalysisPass();
(void) llvm::createObjCARCAPElimPass(); (void) llvm::createObjCARCAPElimPass();
(void) llvm::createObjCARCExpandPass(); (void) llvm::createObjCARCExpandPass();
(void) llvm::createObjCARCContractPass(); (void) llvm::createObjCARCContractPass();
(void) llvm::createObjCARCOptPass(); (void) llvm::createObjCARCOptPass();
(void) llvm::createProfileEstimatorPass(); (void) llvm::createProfileEstimatorPass();
(void) llvm::createProfileVerifierPass(); (void) llvm::createProfileVerifierPass();
(void) llvm::createPathProfileVerifierPass(); (void) llvm::createPathProfileVerifierPass();
(void) llvm::createProfileLoaderPass(); (void) llvm::createProfileLoaderPass();
(void) llvm::createProfileMetadataLoaderPass();
(void) llvm::createPathProfileLoaderPass(); (void) llvm::createPathProfileLoaderPass();
(void) llvm::createPromoteMemoryToRegisterPass(); (void) llvm::createPromoteMemoryToRegisterPass();
(void) llvm::createDemoteRegisterToMemoryPass(); (void) llvm::createDemoteRegisterToMemoryPass();
(void) llvm::createPruneEHPass(); (void) llvm::createPruneEHPass();
(void) llvm::createPostDomOnlyPrinterPass(); (void) llvm::createPostDomOnlyPrinterPass();
(void) llvm::createPostDomPrinterPass(); (void) llvm::createPostDomPrinterPass();
(void) llvm::createPostDomOnlyViewerPass(); (void) llvm::createPostDomOnlyViewerPass();
(void) llvm::createPostDomViewerPass(); (void) llvm::createPostDomViewerPass();
(void) llvm::createReassociatePass(); (void) llvm::createReassociatePass();
(void) llvm::createRegionInfoPass(); (void) llvm::createRegionInfoPass();
skipping to change at line 142 skipping to change at line 145
(void) llvm::createJumpThreadingPass(); (void) llvm::createJumpThreadingPass();
(void) llvm::createUnifyFunctionExitNodesPass(); (void) llvm::createUnifyFunctionExitNodesPass();
(void) llvm::createInstCountPass(); (void) llvm::createInstCountPass();
(void) llvm::createCodeGenPreparePass(); (void) llvm::createCodeGenPreparePass();
(void) llvm::createEarlyCSEPass(); (void) llvm::createEarlyCSEPass();
(void) llvm::createGVNPass(); (void) llvm::createGVNPass();
(void) llvm::createMemCpyOptPass(); (void) llvm::createMemCpyOptPass();
(void) llvm::createLoopDeletionPass(); (void) llvm::createLoopDeletionPass();
(void) llvm::createPostDomTree(); (void) llvm::createPostDomTree();
(void) llvm::createInstructionNamerPass(); (void) llvm::createInstructionNamerPass();
(void) llvm::createMetaRenamerPass();
(void) llvm::createFunctionAttrsPass(); (void) llvm::createFunctionAttrsPass();
(void) llvm::createMergeFunctionsPass(); (void) llvm::createMergeFunctionsPass();
(void) llvm::createPrintModulePass(0); (void) llvm::createPrintModulePass(0);
(void) llvm::createPrintFunctionPass("", 0); (void) llvm::createPrintFunctionPass("", 0);
(void) llvm::createDbgInfoPrinterPass(); (void) llvm::createDbgInfoPrinterPass();
(void) llvm::createModuleDebugInfoPrinterPass(); (void) llvm::createModuleDebugInfoPrinterPass();
(void) llvm::createPartialInliningPass(); (void) llvm::createPartialInliningPass();
(void) llvm::createLintPass(); (void) llvm::createLintPass();
(void) llvm::createSinkingPass(); (void) llvm::createSinkingPass();
(void) llvm::createLowerAtomicPass(); (void) llvm::createLowerAtomicPass();
(void) llvm::createCorrelatedValuePropagationPass(); (void) llvm::createCorrelatedValuePropagationPass();
(void) llvm::createMemDepPrinter(); (void) llvm::createMemDepPrinter();
(void) llvm::createInstructionSimplifierPass(); (void) llvm::createInstructionSimplifierPass();
(void) llvm::createLoopVectorizePass();
(void) llvm::createBBVectorizePass(); (void) llvm::createBBVectorizePass();
(void)new llvm::IntervalPartition(); (void)new llvm::IntervalPartition();
(void)new llvm::FindUsedTypes(); (void)new llvm::FindUsedTypes();
(void)new llvm::ScalarEvolution(); (void)new llvm::ScalarEvolution();
((llvm::Function*)0)->viewCFGOnly(); ((llvm::Function*)0)->viewCFGOnly();
llvm::RGPassManager RGM; llvm::RGPassManager RGM;
((llvm::RegionPass*)0)->runOnRegion((llvm::Region*)0, RGM); ((llvm::RegionPass*)0)->runOnRegion((llvm::Region*)0, RGM);
llvm::AliasSetTracker X(*(llvm::AliasAnalysis*)0); llvm::AliasSetTracker X(*(llvm::AliasAnalysis*)0);
X.add((llvm::Value*)0, 0, 0); // for -print-alias-sets X.add((llvm::Value*)0, 0, 0); // for -print-alias-sets
 End of changes. 8 change blocks. 
2 lines changed or deleted 7 lines changed or added


 LiveInterval.h   LiveInterval.h 
skipping to change at line 32 skipping to change at line 32
#define LLVM_CODEGEN_LIVEINTERVAL_H #define LLVM_CODEGEN_LIVEINTERVAL_H
#include "llvm/ADT/IntEqClasses.h" #include "llvm/ADT/IntEqClasses.h"
#include "llvm/Support/Allocator.h" #include "llvm/Support/Allocator.h"
#include "llvm/Support/AlignOf.h" #include "llvm/Support/AlignOf.h"
#include "llvm/CodeGen/SlotIndexes.h" #include "llvm/CodeGen/SlotIndexes.h"
#include <cassert> #include <cassert>
#include <climits> #include <climits>
namespace llvm { namespace llvm {
class CoalescerPair;
class LiveIntervals; class LiveIntervals;
class MachineInstr; class MachineInstr;
class MachineRegisterInfo; class MachineRegisterInfo;
class TargetRegisterInfo; class TargetRegisterInfo;
class raw_ostream; class raw_ostream;
/// VNInfo - Value Number Information. /// VNInfo - Value Number Information.
/// This class holds information about a machine level values, including /// This class holds information about a machine level values, including
/// definition and use points. /// definition and use points.
/// ///
class VNInfo { class VNInfo {
private:
enum {
HAS_PHI_KILL = 1,
IS_PHI_DEF = 1 << 1,
IS_UNUSED = 1 << 2
};
unsigned char flags;
public: public:
typedef BumpPtrAllocator Allocator; typedef BumpPtrAllocator Allocator;
/// The ID number of this value. /// The ID number of this value.
unsigned id; unsigned id;
/// The index of the defining instruction. /// The index of the defining instruction.
SlotIndex def; SlotIndex def;
/// VNInfo constructor. /// VNInfo constructor.
VNInfo(unsigned i, SlotIndex d) VNInfo(unsigned i, SlotIndex d)
: flags(0), id(i), def(d) : id(i), def(d)
{ } { }
/// VNInfo construtor, copies values from orig, except for the value nu mber. /// VNInfo construtor, copies values from orig, except for the value nu mber.
VNInfo(unsigned i, const VNInfo &orig) VNInfo(unsigned i, const VNInfo &orig)
: flags(orig.flags), id(i), def(orig.def) : id(i), def(orig.def)
{ } { }
/// Copy from the parameter into this VNInfo. /// Copy from the parameter into this VNInfo.
void copyFrom(VNInfo &src) { void copyFrom(VNInfo &src) {
flags = src.flags;
def = src.def; def = src.def;
} }
/// Used for copying value number info.
unsigned getFlags() const { return flags; }
void setFlags(unsigned flags) { this->flags = flags; }
/// Merge flags from another VNInfo
void mergeFlags(const VNInfo *VNI) {
flags = (flags | VNI->flags) & ~IS_UNUSED;
}
/// Returns true if one or more kills are PHI nodes.
/// Obsolete, do not use!
bool hasPHIKill() const { return flags & HAS_PHI_KILL; }
/// Set the PHI kill flag on this value.
void setHasPHIKill(bool hasKill) {
if (hasKill)
flags |= HAS_PHI_KILL;
else
flags &= ~HAS_PHI_KILL;
}
/// Returns true if this value is defined by a PHI instruction (or was, /// Returns true if this value is defined by a PHI instruction (or was,
/// PHI instrucions may have been eliminated). /// PHI instrucions may have been eliminated).
bool isPHIDef() const { return flags & IS_PHI_DEF; } /// PHI-defs begin at a block boundary, all other defs begin at registe
/// Set the "phi def" flag on this value. r or
void setIsPHIDef(bool phiDef) { /// EC slots.
if (phiDef) bool isPHIDef() const { return def.isBlock(); }
flags |= IS_PHI_DEF;
else
flags &= ~IS_PHI_DEF;
}
/// Returns true if this value is unused. /// Returns true if this value is unused.
bool isUnused() const { return flags & IS_UNUSED; } bool isUnused() const { return !def.isValid(); }
/// Set the "is unused" flag on this value.
void setIsUnused(bool unused) { /// Mark this value as unused.
if (unused) void markUnused() { def = SlotIndex(); }
flags |= IS_UNUSED;
else
flags &= ~IS_UNUSED;
}
}; };
/// LiveRange structure - This represents a simple register range in the /// LiveRange structure - This represents a simple register range in the
/// program, with an inclusive start point and an exclusive end point. /// program, with an inclusive start point and an exclusive end point.
/// These ranges are rendered as [start,end). /// These ranges are rendered as [start,end).
struct LiveRange { struct LiveRange {
SlotIndex start; // Start point of the interval (inclusive) SlotIndex start; // Start point of the interval (inclusive)
SlotIndex end; // End point of the interval (exclusive) SlotIndex end; // End point of the interval (exclusive)
VNInfo *valno; // identifier for the value contained in this interval . VNInfo *valno; // identifier for the value contained in this interval .
skipping to change at line 155 skipping to change at line 117
bool operator<(const LiveRange &LR) const { bool operator<(const LiveRange &LR) const {
return start < LR.start || (start == LR.start && end < LR.end); return start < LR.start || (start == LR.start && end < LR.end);
} }
bool operator==(const LiveRange &LR) const { bool operator==(const LiveRange &LR) const {
return start == LR.start && end == LR.end; return start == LR.start && end == LR.end;
} }
void dump() const; void dump() const;
void print(raw_ostream &os) const; void print(raw_ostream &os) const;
private:
LiveRange(); // DO NOT IMPLEMENT
}; };
template <> struct isPodLike<LiveRange> { static const bool value = true; }; template <> struct isPodLike<LiveRange> { static const bool value = true; };
raw_ostream& operator<<(raw_ostream& os, const LiveRange &LR); raw_ostream& operator<<(raw_ostream& os, const LiveRange &LR);
inline bool operator<(SlotIndex V, const LiveRange &LR) { inline bool operator<(SlotIndex V, const LiveRange &LR) {
return V < LR.start; return V < LR.start;
} }
skipping to change at line 276 skipping to change at line 235
/// getNextValue - Create a new value number and return it. MIIdx spec ifies /// getNextValue - Create a new value number and return it. MIIdx spec ifies
/// the instruction that defines the value number. /// the instruction that defines the value number.
VNInfo *getNextValue(SlotIndex def, VNInfo::Allocator &VNInfoAllocator) { VNInfo *getNextValue(SlotIndex def, VNInfo::Allocator &VNInfoAllocator) {
VNInfo *VNI = VNInfo *VNI =
new (VNInfoAllocator) VNInfo((unsigned)valnos.size(), def); new (VNInfoAllocator) VNInfo((unsigned)valnos.size(), def);
valnos.push_back(VNI); valnos.push_back(VNI);
return VNI; return VNI;
} }
/// createDeadDef - Make sure the interval has a value defined at Def.
/// If one already exists, return it. Otherwise allocate a new value an
d
/// add liveness for a dead def.
VNInfo *createDeadDef(SlotIndex Def, VNInfo::Allocator &VNInfoAllocator
);
/// Create a copy of the given value. The new value will be identical e xcept /// Create a copy of the given value. The new value will be identical e xcept
/// for the Value number. /// for the Value number.
VNInfo *createValueCopy(const VNInfo *orig, VNInfo *createValueCopy(const VNInfo *orig,
VNInfo::Allocator &VNInfoAllocator) { VNInfo::Allocator &VNInfoAllocator) {
VNInfo *VNI = VNInfo *VNI =
new (VNInfoAllocator) VNInfo((unsigned)valnos.size(), *orig); new (VNInfoAllocator) VNInfo((unsigned)valnos.size(), *orig);
valnos.push_back(VNI); valnos.push_back(VNI);
return VNI; return VNI;
} }
/// RenumberValues - Renumber all values in order of appearance and rem ove /// RenumberValues - Renumber all values in order of appearance and rem ove
/// unused values. /// unused values.
void RenumberValues(LiveIntervals &lis); void RenumberValues(LiveIntervals &lis);
/// isOnlyLROfValNo - Return true if the specified live range is the on
ly
/// one defined by the its val#.
bool isOnlyLROfValNo(const LiveRange *LR) {
for (const_iterator I = begin(), E = end(); I != E; ++I) {
const LiveRange *Tmp = I;
if (Tmp != LR && Tmp->valno == LR->valno)
return false;
}
return true;
}
/// MergeValueNumberInto - This method is called when two value nubmers /// MergeValueNumberInto - This method is called when two value nubmers
/// are found to be equivalent. This eliminates V1, replacing all /// are found to be equivalent. This eliminates V1, replacing all
/// LiveRanges with the V1 value number with the V2 value number. This can /// LiveRanges with the V1 value number with the V2 value number. This can
/// cause merging of V1/V2 values numbers and compaction of the value s pace. /// cause merging of V1/V2 values numbers and compaction of the value s pace.
VNInfo* MergeValueNumberInto(VNInfo *V1, VNInfo *V2); VNInfo* MergeValueNumberInto(VNInfo *V1, VNInfo *V2);
/// MergeValueInAsValue - Merge all of the live ranges of a specific va l# /// MergeValueInAsValue - Merge all of the live ranges of a specific va l#
/// in RHS into this live interval as the specified value number. /// in RHS into this live interval as the specified value number.
/// The LiveRanges in RHS are allowed to overlap with LiveRanges in the /// The LiveRanges in RHS are allowed to overlap with LiveRanges in the
/// current interval, it will replace the value numbers of the overlape d /// current interval, it will replace the value numbers of the overlape d
skipping to change at line 322 skipping to change at line 275
void MergeRangesInAsValue(const LiveInterval &RHS, VNInfo *LHSValNo); void MergeRangesInAsValue(const LiveInterval &RHS, VNInfo *LHSValNo);
/// MergeValueInAsValue - Merge all of the live ranges of a specific va l# /// MergeValueInAsValue - Merge all of the live ranges of a specific va l#
/// in RHS into this live interval as the specified value number. /// in RHS into this live interval as the specified value number.
/// The LiveRanges in RHS are allowed to overlap with LiveRanges in the /// The LiveRanges in RHS are allowed to overlap with LiveRanges in the
/// current interval, but only if the overlapping LiveRanges have the /// current interval, but only if the overlapping LiveRanges have the
/// specified value number. /// specified value number.
void MergeValueInAsValue(const LiveInterval &RHS, void MergeValueInAsValue(const LiveInterval &RHS,
const VNInfo *RHSValNo, VNInfo *LHSValNo); const VNInfo *RHSValNo, VNInfo *LHSValNo);
/// Copy - Copy the specified live interval. This copies all the fields
/// except for the register of the interval.
void Copy(const LiveInterval &RHS, MachineRegisterInfo *MRI,
VNInfo::Allocator &VNInfoAllocator);
bool empty() const { return ranges.empty(); } bool empty() const { return ranges.empty(); }
/// beginIndex - Return the lowest numbered slot covered by interval. /// beginIndex - Return the lowest numbered slot covered by interval.
SlotIndex beginIndex() const { SlotIndex beginIndex() const {
assert(!empty() && "Call to beginIndex() on empty interval."); assert(!empty() && "Call to beginIndex() on empty interval.");
return ranges.front().start; return ranges.front().start;
} }
/// endNumber - return the maximum point of the interval of the whole, /// endNumber - return the maximum point of the interval of the whole,
/// exclusive. /// exclusive.
skipping to change at line 359 skipping to change at line 307
} }
/// killedAt - Return true if a live range ends at index. Note that the kill /// killedAt - Return true if a live range ends at index. Note that the kill
/// point is not contained in the half-open live range. It is usually t he /// point is not contained in the half-open live range. It is usually t he
/// getDefIndex() slot following its last use. /// getDefIndex() slot following its last use.
bool killedAt(SlotIndex index) const { bool killedAt(SlotIndex index) const {
const_iterator r = find(index.getRegSlot(true)); const_iterator r = find(index.getRegSlot(true));
return r != end() && r->end == index; return r != end() && r->end == index;
} }
/// killedInRange - Return true if the interval has kills in [Start,End
).
/// Note that the kill point is considered the end of a live range, so
it is
/// not contained in the live range. If a live range ends at End, it wo
n't
/// be counted as a kill by this method.
bool killedInRange(SlotIndex Start, SlotIndex End) const;
/// getLiveRangeContaining - Return the live range that contains the /// getLiveRangeContaining - Return the live range that contains the
/// specified index, or null if there is none. /// specified index, or null if there is none.
const LiveRange *getLiveRangeContaining(SlotIndex Idx) const { const LiveRange *getLiveRangeContaining(SlotIndex Idx) const {
const_iterator I = FindLiveRangeContaining(Idx); const_iterator I = FindLiveRangeContaining(Idx);
return I == end() ? 0 : &*I; return I == end() ? 0 : &*I;
} }
/// getLiveRangeContaining - Return the live range that contains the /// getLiveRangeContaining - Return the live range that contains the
/// specified index, or null if there is none. /// specified index, or null if there is none.
LiveRange *getLiveRangeContaining(SlotIndex Idx) { LiveRange *getLiveRangeContaining(SlotIndex Idx) {
iterator I = FindLiveRangeContaining(Idx); iterator I = FindLiveRangeContaining(Idx);
return I == end() ? 0 : &*I; return I == end() ? 0 : &*I;
} }
const LiveRange *getLiveRangeBefore(SlotIndex Idx) const {
return getLiveRangeContaining(Idx.getPrevSlot());
}
LiveRange *getLiveRangeBefore(SlotIndex Idx) {
return getLiveRangeContaining(Idx.getPrevSlot());
}
/// getVNInfoAt - Return the VNInfo that is live at Idx, or NULL. /// getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.
VNInfo *getVNInfoAt(SlotIndex Idx) const { VNInfo *getVNInfoAt(SlotIndex Idx) const {
const_iterator I = FindLiveRangeContaining(Idx); const_iterator I = FindLiveRangeContaining(Idx);
return I == end() ? 0 : I->valno; return I == end() ? 0 : I->valno;
} }
/// getVNInfoBefore - Return the VNInfo that is live up to but not /// getVNInfoBefore - Return the VNInfo that is live up to but not
/// necessarilly including Idx, or NULL. Use this to find the reaching def /// necessarilly including Idx, or NULL. Use this to find the reaching def
/// used by an instruction at this SlotIndex position. /// used by an instruction at this SlotIndex position.
VNInfo *getVNInfoBefore(SlotIndex Idx) const { VNInfo *getVNInfoBefore(SlotIndex Idx) const {
skipping to change at line 413 skipping to change at line 347
iterator FindLiveRangeContaining(SlotIndex Idx) { iterator FindLiveRangeContaining(SlotIndex Idx) {
iterator I = find(Idx); iterator I = find(Idx);
return I != end() && I->start <= Idx ? I : end(); return I != end() && I->start <= Idx ? I : end();
} }
const_iterator FindLiveRangeContaining(SlotIndex Idx) const { const_iterator FindLiveRangeContaining(SlotIndex Idx) const {
const_iterator I = find(Idx); const_iterator I = find(Idx);
return I != end() && I->start <= Idx ? I : end(); return I != end() && I->start <= Idx ? I : end();
} }
/// findDefinedVNInfo - Find the by the specified
/// index (register interval) or defined
VNInfo *findDefinedVNInfoForRegInt(SlotIndex Idx) const;
/// overlaps - Return true if the intersection of the two live interval s is /// overlaps - Return true if the intersection of the two live interval s is
/// not empty. /// not empty.
bool overlaps(const LiveInterval& other) const { bool overlaps(const LiveInterval& other) const {
if (other.empty()) if (other.empty())
return false; return false;
return overlapsFrom(other, other.begin()); return overlapsFrom(other, other.begin());
} }
/// overlaps - Return true if the two intervals have overlapping segmen
ts
/// that are not coalescable according to CP.
///
/// Overlapping segments where one interval is defined by a coalescable
/// copy are allowed.
bool overlaps(const LiveInterval &Other, const CoalescerPair &CP,
const SlotIndexes&) const;
/// overlaps - Return true if the live interval overlaps a range specif ied /// overlaps - Return true if the live interval overlaps a range specif ied
/// by [Start, End). /// by [Start, End).
bool overlaps(SlotIndex Start, SlotIndex End) const; bool overlaps(SlotIndex Start, SlotIndex End) const;
/// overlapsFrom - Return true if the intersection of the two live inte rvals /// overlapsFrom - Return true if the intersection of the two live inte rvals
/// is not empty. The specified iterator is a hint that we can begin /// is not empty. The specified iterator is a hint that we can begin
/// scanning the Other interval starting at I. /// scanning the Other interval starting at I.
bool overlapsFrom(const LiveInterval& other, const_iterator I) const; bool overlapsFrom(const LiveInterval& other, const_iterator I) const;
/// addRange - Add the specified LiveRange to this interval, merging /// addRange - Add the specified LiveRange to this interval, merging
skipping to change at line 499 skipping to change at line 437
/// isSpillable - Can this interval be spilled? /// isSpillable - Can this interval be spilled?
bool isSpillable() const { bool isSpillable() const {
return weight != HUGE_VALF; return weight != HUGE_VALF;
} }
/// markNotSpillable - Mark interval as not spillable /// markNotSpillable - Mark interval as not spillable
void markNotSpillable() { void markNotSpillable() {
weight = HUGE_VALF; weight = HUGE_VALF;
} }
/// ComputeJoinedWeight - Set the weight of a live interval after
/// Other has been merged into it.
void ComputeJoinedWeight(const LiveInterval &Other);
bool operator<(const LiveInterval& other) const { bool operator<(const LiveInterval& other) const {
const SlotIndex &thisIndex = beginIndex(); const SlotIndex &thisIndex = beginIndex();
const SlotIndex &otherIndex = other.beginIndex(); const SlotIndex &otherIndex = other.beginIndex();
return (thisIndex < otherIndex || return (thisIndex < otherIndex ||
(thisIndex == otherIndex && reg < other.reg)); (thisIndex == otherIndex && reg < other.reg));
} }
void print(raw_ostream &OS, const TargetRegisterInfo *TRI = 0) const; void print(raw_ostream &OS) const;
void dump() const; void dump() const;
/// \brief Walk the interval and assert if any invariants fail to hold.
///
/// Note that this is a no-op when asserts are disabled.
#ifdef NDEBUG
void verify() const {}
#else
void verify() const;
#endif
private: private:
Ranges::iterator addRangeFrom(LiveRange LR, Ranges::iterator From); Ranges::iterator addRangeFrom(LiveRange LR, Ranges::iterator From);
void extendIntervalEndTo(Ranges::iterator I, SlotIndex NewEnd); void extendIntervalEndTo(Ranges::iterator I, SlotIndex NewEnd);
Ranges::iterator extendIntervalStartTo(Ranges::iterator I, SlotIndex Ne wStr); Ranges::iterator extendIntervalStartTo(Ranges::iterator I, SlotIndex Ne wStr);
void markValNoForDeletion(VNInfo *V); void markValNoForDeletion(VNInfo *V);
void mergeIntervalRanges(const LiveInterval &RHS,
VNInfo *LHSValNo = 0,
const VNInfo *RHSValNo = 0);
LiveInterval& operator=(const LiveInterval& rhs); // DO NOT IMPLEMENT LiveInterval& operator=(const LiveInterval& rhs) LLVM_DELETED_FUNCTION;
}; };
inline raw_ostream &operator<<(raw_ostream &OS, const LiveInterval &LI) { inline raw_ostream &operator<<(raw_ostream &OS, const LiveInterval &LI) {
LI.print(OS); LI.print(OS);
return OS; return OS;
} }
/// LiveRangeQuery - Query information about a live range around a given
/// instruction. This class hides the implementation details of live rang
es,
/// and it should be used as the primary interface for examining live ran
ges
/// around instructions.
///
class LiveRangeQuery {
VNInfo *EarlyVal;
VNInfo *LateVal;
SlotIndex EndPoint;
bool Kill;
public:
/// Create a LiveRangeQuery for the given live range and instruction in
dex.
/// The sub-instruction slot of Idx doesn't matter, only the instructio
n it
/// refers to is considered.
LiveRangeQuery(const LiveInterval &LI, SlotIndex Idx)
: EarlyVal(0), LateVal(0), Kill(false) {
// Find the segment that enters the instruction.
LiveInterval::const_iterator I = LI.find(Idx.getBaseIndex());
LiveInterval::const_iterator E = LI.end();
if (I == E)
return;
// Is this an instruction live-in segment?
// If Idx is the start index of a basic block, include live-in segmen
ts
// that start at Idx.getBaseIndex().
if (I->start <= Idx.getBaseIndex()) {
EarlyVal = I->valno;
EndPoint = I->end;
// Move to the potentially live-out segment.
if (SlotIndex::isSameInstr(Idx, I->end)) {
Kill = true;
if (++I == E)
return;
}
// Special case: A PHIDef value can have its def in the middle of a
// segment if the value happens to be live out of the layout
// predecessor.
// Such a value is not live-in.
if (EarlyVal->def == Idx.getBaseIndex())
EarlyVal = 0;
}
// I now points to the segment that may be live-through, or defined b
y
// this instr. Ignore segments starting after the current instr.
if (SlotIndex::isEarlierInstr(Idx, I->start))
return;
LateVal = I->valno;
EndPoint = I->end;
}
/// Return the value that is live-in to the instruction. This is the va
lue
/// that will be read by the instruction's use operands. Return NULL if
no
/// value is live-in.
VNInfo *valueIn() const {
return EarlyVal;
}
/// Return true if the live-in value is killed by this instruction. Thi
s
/// means that either the live range ends at the instruction, or it cha
nges
/// value.
bool isKill() const {
return Kill;
}
/// Return true if this instruction has a dead def.
bool isDeadDef() const {
return EndPoint.isDead();
}
/// Return the value leaving the instruction, if any. This can be a
/// live-through value, or a live def. A dead def returns NULL.
VNInfo *valueOut() const {
return isDeadDef() ? 0 : LateVal;
}
/// Return the value defined by this instruction, if any. This includes
/// dead defs, it is the value created by the instruction's def operand
s.
VNInfo *valueDefined() const {
return EarlyVal == LateVal ? 0 : LateVal;
}
/// Return the end point of the last live range segment to interact wit
h
/// the instruction, if any.
///
/// The end point is an invalid SlotIndex only if the live range doesn'
t
/// intersect the instruction at all.
///
/// The end point may be at or past the end of the instruction's basic
/// block. That means the value was live out of the block.
SlotIndex endPoint() const {
return EndPoint;
}
};
/// ConnectedVNInfoEqClasses - Helper class that can divide VNInfos in a /// ConnectedVNInfoEqClasses - Helper class that can divide VNInfos in a
/// LiveInterval into equivalence clases of connected components. A /// LiveInterval into equivalence clases of connected components. A
/// LiveInterval that has multiple connected components can be broken int o /// LiveInterval that has multiple connected components can be broken int o
/// multiple LiveIntervals. /// multiple LiveIntervals.
/// ///
/// Given a LiveInterval that may have multiple connected components, run : /// Given a LiveInterval that may have multiple connected components, run :
/// ///
/// unsigned numComps = ConEQ.Classify(LI); /// unsigned numComps = ConEQ.Classify(LI);
/// if (numComps > 1) { /// if (numComps > 1) {
/// // allocate numComps-1 new LiveIntervals into LIS[1..] /// // allocate numComps-1 new LiveIntervals into LIS[1..]
 End of changes. 22 change blocks. 
95 lines changed or deleted 147 lines changed or added


 LiveIntervalAnalysis.h   LiveIntervalAnalysis.h 
skipping to change at line 23 skipping to change at line 23
// instruction with number j' > j such that v is live at j' and there is no // instruction with number j' > j such that v is live at j' and there is no
// instruction with number i' < i such that v is live at i'. In this // instruction with number i' < i such that v is live at i'. In this
// implementation intervals can have holes, i.e. an interval might look lik e // implementation intervals can have holes, i.e. an interval might look lik e
// [1,20), [50,65), [1000,1001). // [1,20), [50,65), [1000,1001).
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_CODEGEN_LIVEINTERVAL_ANALYSIS_H #ifndef LLVM_CODEGEN_LIVEINTERVAL_ANALYSIS_H
#define LLVM_CODEGEN_LIVEINTERVAL_ANALYSIS_H #define LLVM_CODEGEN_LIVEINTERVAL_ANALYSIS_H
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/LiveInterval.h" #include "llvm/CodeGen/LiveInterval.h"
#include "llvm/CodeGen/SlotIndexes.h" #include "llvm/CodeGen/SlotIndexes.h"
#include "llvm/ADT/BitVector.h" #include "llvm/ADT/BitVector.h"
#include "llvm/ADT/DenseMap.h" #include "llvm/ADT/IndexedMap.h"
#include "llvm/ADT/SmallPtrSet.h" #include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/SmallVector.h" #include "llvm/ADT/SmallVector.h"
#include "llvm/Support/Allocator.h" #include "llvm/Support/Allocator.h"
#include <cmath> #include <cmath>
#include <iterator> #include <iterator>
namespace llvm { namespace llvm {
class AliasAnalysis; class AliasAnalysis;
class LiveRangeCalc;
class LiveVariables; class LiveVariables;
class MachineDominatorTree;
class MachineLoopInfo; class MachineLoopInfo;
class TargetRegisterInfo; class TargetRegisterInfo;
class MachineRegisterInfo; class MachineRegisterInfo;
class TargetInstrInfo; class TargetInstrInfo;
class TargetRegisterClass; class TargetRegisterClass;
class VirtRegMap; class VirtRegMap;
class LiveIntervals : public MachineFunctionPass { class LiveIntervals : public MachineFunctionPass {
MachineFunction* mf_; MachineFunction* MF;
MachineRegisterInfo* mri_; MachineRegisterInfo* MRI;
const TargetMachine* tm_; const TargetMachine* TM;
const TargetRegisterInfo* tri_; const TargetRegisterInfo* TRI;
const TargetInstrInfo* tii_; const TargetInstrInfo* TII;
AliasAnalysis *aa_; AliasAnalysis *AA;
LiveVariables* lv_; LiveVariables* LV;
SlotIndexes* indexes_; SlotIndexes* Indexes;
MachineDominatorTree *DomTree;
LiveRangeCalc *LRCalc;
/// Special pool allocator for VNInfo's (LiveInterval val#). /// Special pool allocator for VNInfo's (LiveInterval val#).
/// ///
VNInfo::Allocator VNInfoAllocator; VNInfo::Allocator VNInfoAllocator;
typedef DenseMap<unsigned, LiveInterval*> Reg2IntervalMap; /// Live interval pointers for all the virtual registers.
Reg2IntervalMap r2iMap_; IndexedMap<LiveInterval*, VirtReg2IndexFunctor> VirtRegIntervals;
/// allocatableRegs_ - A bit vector of allocatable registers.
BitVector allocatableRegs_;
/// reservedRegs_ - A bit vector of reserved registers.
BitVector reservedRegs_;
/// RegMaskSlots - Sorted list of instructions with register mask opera nds. /// RegMaskSlots - Sorted list of instructions with register mask opera nds.
/// Always use the 'r' slot, RegMasks are normal clobbers, not early /// Always use the 'r' slot, RegMasks are normal clobbers, not early
/// clobbers. /// clobbers.
SmallVector<SlotIndex, 8> RegMaskSlots; SmallVector<SlotIndex, 8> RegMaskSlots;
/// RegMaskBits - This vector is parallel to RegMaskSlots, it holds a /// RegMaskBits - This vector is parallel to RegMaskSlots, it holds a
/// pointer to the corresponding register mask. This pointer can be /// pointer to the corresponding register mask. This pointer can be
/// recomputed as: /// recomputed as:
/// ///
skipping to change at line 95 skipping to change at line 94
/// Also see the comment in LiveInterval::find(). /// Also see the comment in LiveInterval::find().
SmallVector<const uint32_t*, 8> RegMaskBits; SmallVector<const uint32_t*, 8> RegMaskBits;
/// For each basic block number, keep (begin, size) pairs indexing into the /// For each basic block number, keep (begin, size) pairs indexing into the
/// RegMaskSlots and RegMaskBits arrays. /// RegMaskSlots and RegMaskBits arrays.
/// Note that basic block numbers may not be layout contiguous, that's why /// Note that basic block numbers may not be layout contiguous, that's why
/// we can't just keep track of the first register mask in each basic /// we can't just keep track of the first register mask in each basic
/// block. /// block.
SmallVector<std::pair<unsigned, unsigned>, 8> RegMaskBlocks; SmallVector<std::pair<unsigned, unsigned>, 8> RegMaskBlocks;
/// RegUnitIntervals - Keep a live interval for each register unit as a
way
/// of tracking fixed physreg interference.
SmallVector<LiveInterval*, 0> RegUnitIntervals;
public: public:
static char ID; // Pass identification, replacement for typeid static char ID; // Pass identification, replacement for typeid
LiveIntervals() : MachineFunctionPass(ID) { LiveIntervals();
initializeLiveIntervalsPass(*PassRegistry::getPassRegistry()); virtual ~LiveIntervals();
}
// Calculate the spill weight to assign to a single instruction. // Calculate the spill weight to assign to a single instruction.
static float getSpillWeight(bool isDef, bool isUse, unsigned loopDepth) ; static float getSpillWeight(bool isDef, bool isUse, unsigned loopDepth) ;
typedef Reg2IntervalMap::iterator iterator; LiveInterval &getInterval(unsigned Reg) {
typedef Reg2IntervalMap::const_iterator const_iterator; LiveInterval *LI = VirtRegIntervals[Reg];
const_iterator begin() const { return r2iMap_.begin(); } assert(LI && "Interval does not exist for virtual register");
const_iterator end() const { return r2iMap_.end(); } return *LI;
iterator begin() { return r2iMap_.begin(); }
iterator end() { return r2iMap_.end(); }
unsigned getNumIntervals() const { return (unsigned)r2iMap_.size(); }
LiveInterval &getInterval(unsigned reg) {
Reg2IntervalMap::iterator I = r2iMap_.find(reg);
assert(I != r2iMap_.end() && "Interval does not exist for register");
return *I->second;
}
const LiveInterval &getInterval(unsigned reg) const {
Reg2IntervalMap::const_iterator I = r2iMap_.find(reg);
assert(I != r2iMap_.end() && "Interval does not exist for register");
return *I->second;
}
bool hasInterval(unsigned reg) const {
return r2iMap_.count(reg);
} }
/// isAllocatable - is the physical register reg allocatable in the cur const LiveInterval &getInterval(unsigned Reg) const {
rent return const_cast<LiveIntervals*>(this)->getInterval(Reg);
/// function?
bool isAllocatable(unsigned reg) const {
return allocatableRegs_.test(reg);
} }
/// isReserved - is the physical register reg reserved in the current bool hasInterval(unsigned Reg) const {
/// function return VirtRegIntervals.inBounds(Reg) && VirtRegIntervals[Reg];
bool isReserved(unsigned reg) const {
return reservedRegs_.test(reg);
} }
/// getScaledIntervalSize - get the size of an interval in "units," // Interval creation.
/// where every function is composed of one thousand units. This LiveInterval &getOrCreateInterval(unsigned Reg) {
/// measure scales properly with empty index slots in the function. if (!hasInterval(Reg)) {
double getScaledIntervalSize(LiveInterval& I) { VirtRegIntervals.grow(Reg);
return (1000.0 * I.getSize()) / indexes_->getIndexesLength(); VirtRegIntervals[Reg] = createInterval(Reg);
}
return getInterval(Reg);
} }
/// getFuncInstructionCount - Return the number of instructions in the // Interval removal.
/// current function. void removeInterval(unsigned Reg) {
unsigned getFuncInstructionCount() { delete VirtRegIntervals[Reg];
return indexes_->getFunctionSize(); VirtRegIntervals[Reg] = 0;
}
/// getApproximateInstructionCount - computes an estimate of the number
/// of instructions in a given LiveInterval.
unsigned getApproximateInstructionCount(LiveInterval& I) {
double IntervalPercentage = getScaledIntervalSize(I) / 1000.0;
return (unsigned)(IntervalPercentage * indexes_->getFunctionSize());
}
// Interval creation
LiveInterval &getOrCreateInterval(unsigned reg) {
Reg2IntervalMap::iterator I = r2iMap_.find(reg);
if (I == r2iMap_.end())
I = r2iMap_.insert(std::make_pair(reg, createInterval(reg))).first;
return *I->second;
} }
/// dupInterval - Duplicate a live interval. The caller is responsible
for
/// managing the allocated memory.
LiveInterval *dupInterval(LiveInterval *li);
/// addLiveRangeToEndOfBlock - Given a register and an instruction, /// addLiveRangeToEndOfBlock - Given a register and an instruction,
/// adds a live range from that instruction to the end of its MBB. /// adds a live range from that instruction to the end of its MBB.
LiveRange addLiveRangeToEndOfBlock(unsigned reg, LiveRange addLiveRangeToEndOfBlock(unsigned reg,
MachineInstr* startInst); MachineInstr* startInst);
/// shrinkToUses - After removing some uses of a register, shrink its l ive /// shrinkToUses - After removing some uses of a register, shrink its l ive
/// range to just the remaining uses. This method does not compute reac hing /// range to just the remaining uses. This method does not compute reac hing
/// defs for new uses, and it doesn't remove dead defs. /// defs for new uses, and it doesn't remove dead defs.
/// Dead PHIDef values are marked as unused. /// Dead PHIDef values are marked as unused.
/// New dead machine instructions are added to the dead vector. /// New dead machine instructions are added to the dead vector.
/// Return true if the interval may have been separated into multiple /// Return true if the interval may have been separated into multiple
/// connected components. /// connected components.
bool shrinkToUses(LiveInterval *li, bool shrinkToUses(LiveInterval *li,
SmallVectorImpl<MachineInstr*> *dead = 0); SmallVectorImpl<MachineInstr*> *dead = 0);
// Interval removal /// extendToIndices - Extend the live range of LI to reach all points i
n
/// Indices. The points in the Indices array must be jointly dominated
by
/// existing defs in LI. PHI-defs are added as needed to maintain SSA f
orm.
///
/// If a SlotIndex in Indices is the end index of a basic block, LI wil
l be
/// extended to be live out of the basic block.
///
/// See also LiveRangeCalc::extend().
void extendToIndices(LiveInterval *LI, ArrayRef<SlotIndex> Indices);
/// pruneValue - If an LI value is live at Kill, prune its live range b
y
/// removing any liveness reachable from Kill. Add live range end point
s to
/// EndPoints such that extendToIndices(LI, EndPoints) will reconstruct
the
/// value's live range.
///
/// Calling pruneValue() and extendToIndices() can be used to reconstru
ct
/// SSA form after adding defs to a virtual register.
void pruneValue(LiveInterval *LI, SlotIndex Kill,
SmallVectorImpl<SlotIndex> *EndPoints);
void removeInterval(unsigned Reg) { SlotIndexes *getSlotIndexes() const {
DenseMap<unsigned, LiveInterval*>::iterator I = r2iMap_.find(Reg); return Indexes;
delete I->second;
r2iMap_.erase(I);
} }
SlotIndexes *getSlotIndexes() const { AliasAnalysis *getAliasAnalysis() const {
return indexes_; return AA;
} }
/// isNotInMIMap - returns true if the specified machine instr has been /// isNotInMIMap - returns true if the specified machine instr has been
/// removed or was never entered in the map. /// removed or was never entered in the map.
bool isNotInMIMap(const MachineInstr* Instr) const { bool isNotInMIMap(const MachineInstr* Instr) const {
return !indexes_->hasIndex(Instr); return !Indexes->hasIndex(Instr);
} }
/// Returns the base index of the given instruction. /// Returns the base index of the given instruction.
SlotIndex getInstructionIndex(const MachineInstr *instr) const { SlotIndex getInstructionIndex(const MachineInstr *instr) const {
return indexes_->getInstructionIndex(instr); return Indexes->getInstructionIndex(instr);
} }
/// Returns the instruction associated with the given index. /// Returns the instruction associated with the given index.
MachineInstr* getInstructionFromIndex(SlotIndex index) const { MachineInstr* getInstructionFromIndex(SlotIndex index) const {
return indexes_->getInstructionFromIndex(index); return Indexes->getInstructionFromIndex(index);
} }
/// Return the first index in the given basic block. /// Return the first index in the given basic block.
SlotIndex getMBBStartIdx(const MachineBasicBlock *mbb) const { SlotIndex getMBBStartIdx(const MachineBasicBlock *mbb) const {
return indexes_->getMBBStartIdx(mbb); return Indexes->getMBBStartIdx(mbb);
} }
/// Return the last index in the given basic block. /// Return the last index in the given basic block.
SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const { SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const {
return indexes_->getMBBEndIdx(mbb); return Indexes->getMBBEndIdx(mbb);
} }
bool isLiveInToMBB(const LiveInterval &li, bool isLiveInToMBB(const LiveInterval &li,
const MachineBasicBlock *mbb) const { const MachineBasicBlock *mbb) const {
return li.liveAt(getMBBStartIdx(mbb)); return li.liveAt(getMBBStartIdx(mbb));
} }
bool isLiveOutOfMBB(const LiveInterval &li, bool isLiveOutOfMBB(const LiveInterval &li,
const MachineBasicBlock *mbb) const { const MachineBasicBlock *mbb) const {
return li.liveAt(getMBBEndIdx(mbb).getPrevSlot()); return li.liveAt(getMBBEndIdx(mbb).getPrevSlot());
} }
MachineBasicBlock* getMBBFromIndex(SlotIndex index) const { MachineBasicBlock* getMBBFromIndex(SlotIndex index) const {
return indexes_->getMBBFromIndex(index); return Indexes->getMBBFromIndex(index);
} }
SlotIndex InsertMachineInstrInMaps(MachineInstr *MI) { SlotIndex InsertMachineInstrInMaps(MachineInstr *MI) {
return indexes_->insertMachineInstrInMaps(MI); return Indexes->insertMachineInstrInMaps(MI);
} }
void RemoveMachineInstrFromMaps(MachineInstr *MI) { void RemoveMachineInstrFromMaps(MachineInstr *MI) {
indexes_->removeMachineInstrFromMaps(MI); Indexes->removeMachineInstrFromMaps(MI);
} }
void ReplaceMachineInstrInMaps(MachineInstr *MI, MachineInstr *NewMI) { void ReplaceMachineInstrInMaps(MachineInstr *MI, MachineInstr *NewMI) {
indexes_->replaceMachineInstrInMaps(MI, NewMI); Indexes->replaceMachineInstrInMaps(MI, NewMI);
} }
bool findLiveInMBBs(SlotIndex Start, SlotIndex End, bool findLiveInMBBs(SlotIndex Start, SlotIndex End,
SmallVectorImpl<MachineBasicBlock*> &MBBs) const { SmallVectorImpl<MachineBasicBlock*> &MBBs) const {
return indexes_->findLiveInMBBs(Start, End, MBBs); return Indexes->findLiveInMBBs(Start, End, MBBs);
} }
VNInfo::Allocator& getVNInfoAllocator() { return VNInfoAllocator; } VNInfo::Allocator& getVNInfoAllocator() { return VNInfoAllocator; }
virtual void getAnalysisUsage(AnalysisUsage &AU) const; virtual void getAnalysisUsage(AnalysisUsage &AU) const;
virtual void releaseMemory(); virtual void releaseMemory();
/// runOnMachineFunction - pass entry point /// runOnMachineFunction - pass entry point
virtual bool runOnMachineFunction(MachineFunction&); virtual bool runOnMachineFunction(MachineFunction&);
/// print - Implement the dump method. /// print - Implement the dump method.
virtual void print(raw_ostream &O, const Module* = 0) const; virtual void print(raw_ostream &O, const Module* = 0) const;
/// isReMaterializable - Returns true if every definition of MI of ever
y
/// val# of the specified interval is re-materializable. Also returns t
rue
/// by reference if all of the defs are load instructions.
bool isReMaterializable(const LiveInterval &li,
const SmallVectorImpl<LiveInterval*> *SpillIs,
bool &isLoad);
/// intervalIsInOneMBB - If LI is confined to a single basic block, ret urn /// intervalIsInOneMBB - If LI is confined to a single basic block, ret urn
/// a pointer to that block. If LI is live in to or out of any block, /// a pointer to that block. If LI is live in to or out of any block,
/// return NULL. /// return NULL.
MachineBasicBlock *intervalIsInOneMBB(const LiveInterval &LI) const; MachineBasicBlock *intervalIsInOneMBB(const LiveInterval &LI) const;
/// Returns true if VNI is killed by any PHI-def values in LI.
/// This may conservatively return true to avoid expensive computations
.
bool hasPHIKill(const LiveInterval &LI, const VNInfo *VNI) const;
/// addKillFlags - Add kill flags to any instruction that kills a virtu al /// addKillFlags - Add kill flags to any instruction that kills a virtu al
/// register. /// register.
void addKillFlags(); void addKillFlags(const VirtRegMap*);
/// handleMove - call this method to notify LiveIntervals that /// handleMove - call this method to notify LiveIntervals that
/// instruction 'mi' has been moved within a basic block. This will upd ate /// instruction 'mi' has been moved within a basic block. This will upd ate
/// the live intervals for all operands of mi. Moves between basic bloc ks /// the live intervals for all operands of mi. Moves between basic bloc ks
/// are not supported. /// are not supported.
void handleMove(MachineInstr* MI); ///
/// \param UpdateFlags Update live intervals for nonallocatable physreg
s.
void handleMove(MachineInstr* MI, bool UpdateFlags = false);
/// moveIntoBundle - Update intervals for operands of MI so that they /// moveIntoBundle - Update intervals for operands of MI so that they
/// begin/end on the SlotIndex for BundleStart. /// begin/end on the SlotIndex for BundleStart.
/// ///
/// \param UpdateFlags Update live intervals for nonallocatable physreg
s.
///
/// Requires MI and BundleStart to have SlotIndexes, and assumes /// Requires MI and BundleStart to have SlotIndexes, and assumes
/// existing liveness is accurate. BundleStart should be the first /// existing liveness is accurate. BundleStart should be the first
/// instruction in the Bundle. /// instruction in the Bundle.
void handleMoveIntoBundle(MachineInstr* MI, MachineInstr* BundleStart); void handleMoveIntoBundle(MachineInstr* MI, MachineInstr* BundleStart,
bool UpdateFlags = false);
// Register mask functions. // Register mask functions.
// //
// Machine instructions may use a register mask operand to indicate tha t a // Machine instructions may use a register mask operand to indicate tha t a
// large number of registers are clobbered by the instruction. This is // large number of registers are clobbered by the instruction. This is
// typically used for calls. // typically used for calls.
// //
// For compile time performance reasons, these clobbers are not recorde d in // For compile time performance reasons, these clobbers are not recorde d in
// the live intervals for individual physical registers. Instead, // the live intervals for individual physical registers. Instead,
// LiveIntervalAnalysis maintains a sorted list of instructions with // LiveIntervalAnalysis maintains a sorted list of instructions with
skipping to change at line 340 skipping to change at line 321
/// checkRegMaskInterference - Test if LI is live across any register m ask /// checkRegMaskInterference - Test if LI is live across any register m ask
/// instructions, and compute a bit mask of physical registers that are not /// instructions, and compute a bit mask of physical registers that are not
/// clobbered by any of them. /// clobbered by any of them.
/// ///
/// Returns false if LI doesn't cross any register mask instructions. I n /// Returns false if LI doesn't cross any register mask instructions. I n
/// that case, the bit vector is not filled in. /// that case, the bit vector is not filled in.
bool checkRegMaskInterference(LiveInterval &LI, bool checkRegMaskInterference(LiveInterval &LI,
BitVector &UsableRegs); BitVector &UsableRegs);
// Register unit functions.
//
// Fixed interference occurs when MachineInstrs use physregs directly
// instead of virtual registers. This typically happens when passing
// arguments to a function call, or when instructions require operands
in
// fixed registers.
//
// Each physreg has one or more register units, see MCRegisterInfo. We
// track liveness per register unit to handle aliasing registers more
// efficiently.
/// getRegUnit - Return the live range for Unit.
/// It will be computed if it doesn't exist.
LiveInterval &getRegUnit(unsigned Unit) {
LiveInterval *LI = RegUnitIntervals[Unit];
if (!LI) {
// Compute missing ranges on demand.
RegUnitIntervals[Unit] = LI = new LiveInterval(Unit, HUGE_VALF);
computeRegUnitInterval(LI);
}
return *LI;
}
/// getCachedRegUnit - Return the live range for Unit if it has already
/// been computed, or NULL if it hasn't been computed yet.
LiveInterval *getCachedRegUnit(unsigned Unit) {
return RegUnitIntervals[Unit];
}
private: private:
/// computeIntervals - Compute live intervals. /// computeIntervals - Compute live intervals.
void computeIntervals(); void computeIntervals();
/// Compute live intervals for all virtual registers.
void computeVirtRegs();
/// Compute RegMaskSlots and RegMaskBits.
void computeRegMasks();
/// handleRegisterDef - update intervals for a register def /// handleRegisterDef - update intervals for a register def
/// (calls handlePhysicalRegisterDef and /// (calls handleVirtualRegisterDef)
/// handleVirtualRegisterDef)
void handleRegisterDef(MachineBasicBlock *MBB, void handleRegisterDef(MachineBasicBlock *MBB,
MachineBasicBlock::iterator MI, MachineBasicBlock::iterator MI,
SlotIndex MIIdx, SlotIndex MIIdx,
MachineOperand& MO, unsigned MOIdx); MachineOperand& MO, unsigned MOIdx);
/// isPartialRedef - Return true if the specified def at the specific i ndex /// isPartialRedef - Return true if the specified def at the specific i ndex
/// is partially re-defining the specified live interval. A common case of /// is partially re-defining the specified live interval. A common case of
/// this is a definition of the sub-register. /// this is a definition of the sub-register.
bool isPartialRedef(SlotIndex MIIdx, MachineOperand &MO, bool isPartialRedef(SlotIndex MIIdx, MachineOperand &MO,
LiveInterval &interval); LiveInterval &interval);
/// handleVirtualRegisterDef - update intervals for a virtual /// handleVirtualRegisterDef - update intervals for a virtual
/// register def /// register def
void handleVirtualRegisterDef(MachineBasicBlock *MBB, void handleVirtualRegisterDef(MachineBasicBlock *MBB,
MachineBasicBlock::iterator MI, MachineBasicBlock::iterator MI,
SlotIndex MIIdx, MachineOperand& MO, SlotIndex MIIdx, MachineOperand& MO,
unsigned MOIdx, unsigned MOIdx,
LiveInterval& interval); LiveInterval& interval);
/// handlePhysicalRegisterDef - update intervals for a physical registe
r
/// def.
void handlePhysicalRegisterDef(MachineBasicBlock* mbb,
MachineBasicBlock::iterator mi,
SlotIndex MIIdx, MachineOperand& MO,
LiveInterval &interval);
/// handleLiveInRegister - Create interval for a livein register.
void handleLiveInRegister(MachineBasicBlock* mbb,
SlotIndex MIIdx,
LiveInterval &interval);
/// getReMatImplicitUse - If the remat definition MI has one (for now,
we
/// only allow one) virtual register operand, then its uses are implici
tly
/// using the register. Returns the virtual register.
unsigned getReMatImplicitUse(const LiveInterval &li,
MachineInstr *MI) const;
/// isValNoAvailableAt - Return true if the val# of the specified inter
val
/// which reaches the given instruction also reaches the specified use
/// index.
bool isValNoAvailableAt(const LiveInterval &li, MachineInstr *MI,
SlotIndex UseIdx) const;
/// isReMaterializable - Returns true if the definition MI of the speci
fied
/// val# of the specified interval is re-materializable. Also returns t
rue
/// by reference if the def is a load.
bool isReMaterializable(const LiveInterval &li, const VNInfo *ValNo,
MachineInstr *MI,
const SmallVectorImpl<LiveInterval*> *SpillIs,
bool &isLoad);
static LiveInterval* createInterval(unsigned Reg); static LiveInterval* createInterval(unsigned Reg);
void printInstrs(raw_ostream &O) const; void printInstrs(raw_ostream &O) const;
void dumpInstrs() const; void dumpInstrs() const;
void computeLiveInRegUnits();
void computeRegUnitInterval(LiveInterval*);
void computeVirtRegInterval(LiveInterval*);
class HMEditor; class HMEditor;
}; };
} // End llvm namespace } // End llvm namespace
#endif #endif
 End of changes. 38 change blocks. 
149 lines changed or deleted 139 lines changed or added


 LiveRangeEdit.h   LiveRangeEdit.h 
skipping to change at line 58 skipping to change at line 58
virtual void LRE_WillShrinkVirtReg(unsigned) {} virtual void LRE_WillShrinkVirtReg(unsigned) {}
/// Called after cloning a virtual register. /// Called after cloning a virtual register.
/// This is used for new registers representing connected components of Old. /// This is used for new registers representing connected components of Old.
virtual void LRE_DidCloneVirtReg(unsigned New, unsigned Old) {} virtual void LRE_DidCloneVirtReg(unsigned New, unsigned Old) {}
virtual ~Delegate() {} virtual ~Delegate() {}
}; };
private: private:
LiveInterval &parent_; LiveInterval *Parent;
SmallVectorImpl<LiveInterval*> &newRegs_; SmallVectorImpl<LiveInterval*> &NewRegs;
MachineRegisterInfo &MRI; MachineRegisterInfo &MRI;
LiveIntervals &LIS; LiveIntervals &LIS;
VirtRegMap *VRM; VirtRegMap *VRM;
const TargetInstrInfo &TII; const TargetInstrInfo &TII;
Delegate *const delegate_; Delegate *const TheDelegate;
/// firstNew_ - Index of the first register added to newRegs_. /// FirstNew - Index of the first register added to NewRegs.
const unsigned firstNew_; const unsigned FirstNew;
/// scannedRemattable_ - true when remattable values have been identified /// ScannedRemattable - true when remattable values have been identified.
. bool ScannedRemattable;
bool scannedRemattable_;
/// remattable_ - Values defined by remattable instructions as identified by /// Remattable - Values defined by remattable instructions as identified by
/// tii.isTriviallyReMaterializable(). /// tii.isTriviallyReMaterializable().
SmallPtrSet<const VNInfo*,4> remattable_; SmallPtrSet<const VNInfo*,4> Remattable;
/// rematted_ - Values that were actually rematted, and so need to have t heir /// Rematted - Values that were actually rematted, and so need to have th eir
/// live range trimmed or entirely removed. /// live range trimmed or entirely removed.
SmallPtrSet<const VNInfo*,4> rematted_; SmallPtrSet<const VNInfo*,4> Rematted;
/// scanRemattable - Identify the parent_ values that may rematerialize. /// scanRemattable - Identify the Parent values that may rematerialize.
void scanRemattable(AliasAnalysis *aa); void scanRemattable(AliasAnalysis *aa);
/// allUsesAvailableAt - Return true if all registers used by OrigMI at /// allUsesAvailableAt - Return true if all registers used by OrigMI at
/// OrigIdx are also available with the same value at UseIdx. /// OrigIdx are also available with the same value at UseIdx.
bool allUsesAvailableAt(const MachineInstr *OrigMI, SlotIndex OrigIdx, bool allUsesAvailableAt(const MachineInstr *OrigMI, SlotIndex OrigIdx,
SlotIndex UseIdx); SlotIndex UseIdx);
/// foldAsLoad - If LI has a single use and a single def that can be fold ed as /// foldAsLoad - If LI has a single use and a single def that can be fold ed as
/// a load, eliminate the register by folding the def into the use. /// a load, eliminate the register by folding the def into the use.
bool foldAsLoad(LiveInterval *LI, SmallVectorImpl<MachineInstr*> &Dead); bool foldAsLoad(LiveInterval *LI, SmallVectorImpl<MachineInstr*> &Dead);
skipping to change at line 102 skipping to change at line 102
public: public:
/// Create a LiveRangeEdit for breaking down parent into smaller pieces. /// Create a LiveRangeEdit for breaking down parent into smaller pieces.
/// @param parent The register being spilled or split. /// @param parent The register being spilled or split.
/// @param newRegs List to receive any new registers created. This needn' t be /// @param newRegs List to receive any new registers created. This needn' t be
/// empty initially, any existing registers are ignored. /// empty initially, any existing registers are ignored.
/// @param MF The MachineFunction the live range edit is taking place in. /// @param MF The MachineFunction the live range edit is taking place in.
/// @param lis The collection of all live intervals in this function. /// @param lis The collection of all live intervals in this function.
/// @param vrm Map of virtual registers to physical registers for this /// @param vrm Map of virtual registers to physical registers for this
/// function. If NULL, no virtual register map updates will /// function. If NULL, no virtual register map updates will
/// be done. This could be the case if called before Regalloc . /// be done. This could be the case if called before Regalloc .
LiveRangeEdit(LiveInterval &parent, LiveRangeEdit(LiveInterval *parent,
SmallVectorImpl<LiveInterval*> &newRegs, SmallVectorImpl<LiveInterval*> &newRegs,
MachineFunction &MF, MachineFunction &MF,
LiveIntervals &lis, LiveIntervals &lis,
VirtRegMap *vrm, VirtRegMap *vrm,
Delegate *delegate = 0) Delegate *delegate = 0)
: parent_(parent), newRegs_(newRegs), : Parent(parent), NewRegs(newRegs),
MRI(MF.getRegInfo()), LIS(lis), VRM(vrm), MRI(MF.getRegInfo()), LIS(lis), VRM(vrm),
TII(*MF.getTarget().getInstrInfo()), TII(*MF.getTarget().getInstrInfo()),
delegate_(delegate), TheDelegate(delegate),
firstNew_(newRegs.size()), FirstNew(newRegs.size()),
scannedRemattable_(false) {} ScannedRemattable(false) {}
LiveInterval &getParent() const { return parent_; } LiveInterval &getParent() const {
unsigned getReg() const { return parent_.reg; } assert(Parent && "No parent LiveInterval");
return *Parent;
}
unsigned getReg() const { return getParent().reg; }
/// Iterator for accessing the new registers added by this edit. /// Iterator for accessing the new registers added by this edit.
typedef SmallVectorImpl<LiveInterval*>::const_iterator iterator; typedef SmallVectorImpl<LiveInterval*>::const_iterator iterator;
iterator begin() const { return newRegs_.begin()+firstNew_; } iterator begin() const { return NewRegs.begin()+FirstNew; }
iterator end() const { return newRegs_.end(); } iterator end() const { return NewRegs.end(); }
unsigned size() const { return newRegs_.size()-firstNew_; } unsigned size() const { return NewRegs.size()-FirstNew; }
bool empty() const { return size() == 0; } bool empty() const { return size() == 0; }
LiveInterval *get(unsigned idx) const { return newRegs_[idx+firstNew_]; } LiveInterval *get(unsigned idx) const { return NewRegs[idx+FirstNew]; }
ArrayRef<LiveInterval*> regs() const { ArrayRef<LiveInterval*> regs() const {
return makeArrayRef(newRegs_).slice(firstNew_); return makeArrayRef(NewRegs).slice(FirstNew);
} }
/// createFrom - Create a new virtual register based on OldReg. /// createFrom - Create a new virtual register based on OldReg.
LiveInterval &createFrom(unsigned OldReg); LiveInterval &createFrom(unsigned OldReg);
/// create - Create a new register with the same class and original slot as /// create - Create a new register with the same class and original slot as
/// parent. /// parent.
LiveInterval &create() { LiveInterval &create() {
return createFrom(getReg()); return createFrom(getReg());
} }
skipping to change at line 177 skipping to change at line 180
SlotIndex rematerializeAt(MachineBasicBlock &MBB, SlotIndex rematerializeAt(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI, MachineBasicBlock::iterator MI,
unsigned DestReg, unsigned DestReg,
const Remat &RM, const Remat &RM,
const TargetRegisterInfo&, const TargetRegisterInfo&,
bool Late = false); bool Late = false);
/// markRematerialized - explicitly mark a value as rematerialized after doing /// markRematerialized - explicitly mark a value as rematerialized after doing
/// it manually. /// it manually.
void markRematerialized(const VNInfo *ParentVNI) { void markRematerialized(const VNInfo *ParentVNI) {
rematted_.insert(ParentVNI); Rematted.insert(ParentVNI);
} }
/// didRematerialize - Return true if ParentVNI was rematerialized anywhe re. /// didRematerialize - Return true if ParentVNI was rematerialized anywhe re.
bool didRematerialize(const VNInfo *ParentVNI) const { bool didRematerialize(const VNInfo *ParentVNI) const {
return rematted_.count(ParentVNI); return Rematted.count(ParentVNI);
} }
/// eraseVirtReg - Notify the delegate that Reg is no longer in use, and try /// eraseVirtReg - Notify the delegate that Reg is no longer in use, and try
/// to erase it from LIS. /// to erase it from LIS.
void eraseVirtReg(unsigned Reg); void eraseVirtReg(unsigned Reg);
/// eliminateDeadDefs - Try to delete machine instructions that are now d ead /// eliminateDeadDefs - Try to delete machine instructions that are now d ead
/// (allDefsAreDead returns true). This may cause live intervals to be tr immed /// (allDefsAreDead returns true). This may cause live intervals to be tr immed
/// and further dead efs to be eliminated. /// and further dead efs to be eliminated.
/// RegsBeingSpilled lists registers currently being spilled by the regis ter /// RegsBeingSpilled lists registers currently being spilled by the regis ter
 End of changes. 17 change blocks. 
28 lines changed or deleted 30 lines changed or added


 LiveVariables.h   LiveVariables.h 
skipping to change at line 129 skipping to change at line 129
/// VirtRegInfo - This list is a mapping from virtual register number to /// VirtRegInfo - This list is a mapping from virtual register number to
/// variable information. /// variable information.
/// ///
IndexedMap<VarInfo, VirtReg2IndexFunctor> VirtRegInfo; IndexedMap<VarInfo, VirtReg2IndexFunctor> VirtRegInfo;
/// PHIJoins - list of virtual registers that are PHI joins. These regist ers /// PHIJoins - list of virtual registers that are PHI joins. These regist ers
/// may have multiple definitions, and they require special handling when /// may have multiple definitions, and they require special handling when
/// building live intervals. /// building live intervals.
SparseBitVector<> PHIJoins; SparseBitVector<> PHIJoins;
/// ReservedRegisters - This vector keeps track of which registers
/// are reserved register which are not allocatable by the target machine
.
/// We can not track liveness for values that are in this set.
///
BitVector ReservedRegisters;
private: // Intermediate data structures private: // Intermediate data structures
MachineFunction *MF; MachineFunction *MF;
MachineRegisterInfo* MRI; MachineRegisterInfo* MRI;
const TargetRegisterInfo *TRI; const TargetRegisterInfo *TRI;
// PhysRegInfo - Keep track of which instruction was the last def of a // PhysRegInfo - Keep track of which instruction was the last def of a
// physical register. This is a purely local property, because all physic al // physical register. This is a purely local property, because all physic al
// register references are presumed dead across basic blocks. // register references are presumed dead across basic blocks.
 End of changes. 1 change blocks. 
7 lines changed or deleted 0 lines changed or added


 Loads.h   Loads.h 
skipping to change at line 22 skipping to change at line 22
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_ANALYSIS_LOADS_H #ifndef LLVM_ANALYSIS_LOADS_H
#define LLVM_ANALYSIS_LOADS_H #define LLVM_ANALYSIS_LOADS_H
#include "llvm/BasicBlock.h" #include "llvm/BasicBlock.h"
namespace llvm { namespace llvm {
class AliasAnalysis; class AliasAnalysis;
class TargetData; class DataLayout;
class MDNode; class MDNode;
/// isSafeToLoadUnconditionally - Return true if we know that executing a l oad /// isSafeToLoadUnconditionally - Return true if we know that executing a l oad
/// from this value cannot trap. If it is not obviously safe to load from the /// from this value cannot trap. If it is not obviously safe to load from the
/// specified pointer, we do a quick local scan of the basic block containi ng /// specified pointer, we do a quick local scan of the basic block containi ng
/// ScanFrom, to determine if the address is already accessed. /// ScanFrom, to determine if the address is already accessed.
bool isSafeToLoadUnconditionally(Value *V, Instruction *ScanFrom, bool isSafeToLoadUnconditionally(Value *V, Instruction *ScanFrom,
unsigned Align, const TargetData *TD = 0); unsigned Align, const DataLayout *TD = 0);
/// FindAvailableLoadedValue - Scan the ScanBB block backwards (starting at /// FindAvailableLoadedValue - Scan the ScanBB block backwards (starting at
/// the instruction before ScanFrom) checking to see if we have the value a t /// the instruction before ScanFrom) checking to see if we have the value a t
/// the memory address *Ptr locally available within a small number of /// the memory address *Ptr locally available within a small number of
/// instructions. If the value is available, return it. /// instructions. If the value is available, return it.
/// ///
/// If not, return the iterator for the last validated instruction that the /// If not, return the iterator for the last validated instruction that the
/// value would be live through. If we scanned the entire block and didn't /// value would be live through. If we scanned the entire block and didn't
/// find something that invalidates *Ptr or provides it, ScanFrom would be /// find something that invalidates *Ptr or provides it, ScanFrom would be
/// left at begin() and this returns null. ScanFrom could also be left /// left at begin() and this returns null. ScanFrom could also be left
 End of changes. 2 change blocks. 
2 lines changed or deleted 2 lines changed or added


 Local.h   Local.h 
skipping to change at line 18 skipping to change at line 18
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// //
// This family of functions perform various local transformations to the // This family of functions perform various local transformations to the
// program. // program.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_TRANSFORMS_UTILS_LOCAL_H #ifndef LLVM_TRANSFORMS_UTILS_LOCAL_H
#define LLVM_TRANSFORMS_UTILS_LOCAL_H #define LLVM_TRANSFORMS_UTILS_LOCAL_H
#include "llvm/IRBuilder.h"
#include "llvm/Operator.h"
#include "llvm/Support/GetElementPtrTypeIterator.h"
#include "llvm/DataLayout.h"
namespace llvm { namespace llvm {
class User; class User;
class BasicBlock; class BasicBlock;
class Function; class Function;
class BranchInst; class BranchInst;
class Instruction; class Instruction;
class DbgDeclareInst; class DbgDeclareInst;
class StoreInst; class StoreInst;
class LoadInst; class LoadInst;
class Value; class Value;
class Pass; class Pass;
class PHINode; class PHINode;
class AllocaInst; class AllocaInst;
class ConstantExpr; class ConstantExpr;
class TargetData; class DataLayout;
class TargetLibraryInfo;
class TargetTransformInfo;
class DIBuilder; class DIBuilder;
template<typename T> class SmallVectorImpl; template<typename T> class SmallVectorImpl;
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// Local constant propagation. // Local constant propagation.
// //
/// ConstantFoldTerminator - If a terminator instruction is predicated on a /// ConstantFoldTerminator - If a terminator instruction is predicated on a
/// constant value, convert it into an unconditional branch to the constant /// constant value, convert it into an unconditional branch to the constant
/// destination. This is a nontrivial operation because the successors of this /// destination. This is a nontrivial operation because the successors of this
/// basic block must have their PHI nodes updated. /// basic block must have their PHI nodes updated.
/// Also calls RecursivelyDeleteTriviallyDeadInstructions() on any branch/s witch /// Also calls RecursivelyDeleteTriviallyDeadInstructions() on any branch/s witch
/// conditions and indirectbr addresses this might make dead if /// conditions and indirectbr addresses this might make dead if
/// DeleteDeadConditions is true. /// DeleteDeadConditions is true.
bool ConstantFoldTerminator(BasicBlock *BB, bool DeleteDeadConditions = fal bool ConstantFoldTerminator(BasicBlock *BB, bool DeleteDeadConditions = fal
se); se,
const TargetLibraryInfo *TLI = 0);
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// Local dead code elimination. // Local dead code elimination.
// //
/// isInstructionTriviallyDead - Return true if the result produced by the /// isInstructionTriviallyDead - Return true if the result produced by the
/// instruction is not used, and the instruction has no side effects. /// instruction is not used, and the instruction has no side effects.
/// ///
bool isInstructionTriviallyDead(Instruction *I); bool isInstructionTriviallyDead(Instruction *I, const TargetLibraryInfo *TL I=0);
/// RecursivelyDeleteTriviallyDeadInstructions - If the specified value is a /// RecursivelyDeleteTriviallyDeadInstructions - If the specified value is a
/// trivially dead instruction, delete it. If that makes any of its operan ds /// trivially dead instruction, delete it. If that makes any of its operan ds
/// trivially dead, delete them too, recursively. Return true if any /// trivially dead, delete them too, recursively. Return true if any
/// instructions were deleted. /// instructions were deleted.
bool RecursivelyDeleteTriviallyDeadInstructions(Value *V); bool RecursivelyDeleteTriviallyDeadInstructions(Value *V,
const TargetLibraryInfo *TL
I=0);
/// RecursivelyDeleteDeadPHINode - If the specified value is an effectively /// RecursivelyDeleteDeadPHINode - If the specified value is an effectively
/// dead PHI node, due to being a def-use chain of single-use nodes that /// dead PHI node, due to being a def-use chain of single-use nodes that
/// either forms a cycle or is terminated by a trivially dead instruction, /// either forms a cycle or is terminated by a trivially dead instruction,
/// delete it. If that makes any of its operands trivially dead, delete th em /// delete it. If that makes any of its operands trivially dead, delete th em
/// too, recursively. Return true if a change was made. /// too, recursively. Return true if a change was made.
bool RecursivelyDeleteDeadPHINode(PHINode *PN); bool RecursivelyDeleteDeadPHINode(PHINode *PN, const TargetLibraryInfo *TLI =0);
/// SimplifyInstructionsInBlock - Scan the specified basic block and try to /// SimplifyInstructionsInBlock - Scan the specified basic block and try to
/// simplify any instructions in it and recursively delete dead instruction s. /// simplify any instructions in it and recursively delete dead instruction s.
/// ///
/// This returns true if it changed the code, note that it can delete /// This returns true if it changed the code, note that it can delete
/// instructions in other blocks as well in this block. /// instructions in other blocks as well in this block.
bool SimplifyInstructionsInBlock(BasicBlock *BB, const TargetData *TD = 0); bool SimplifyInstructionsInBlock(BasicBlock *BB, const DataLayout *TD = 0,
const TargetLibraryInfo *TLI = 0);
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// Control Flow Graph Restructuring. // Control Flow Graph Restructuring.
// //
/// RemovePredecessorAndSimplify - Like BasicBlock::removePredecessor, this /// RemovePredecessorAndSimplify - Like BasicBlock::removePredecessor, this
/// method is called when we're about to delete Pred as a predecessor of BB . If /// method is called when we're about to delete Pred as a predecessor of BB . If
/// BB contains any PHI nodes, this drops the entries in the PHI nodes for Pred. /// BB contains any PHI nodes, this drops the entries in the PHI nodes for Pred.
/// ///
/// Unlike the removePredecessor method, this attempts to simplify uses of PHI /// Unlike the removePredecessor method, this attempts to simplify uses of PHI
/// nodes that collapse into identity values. For example, if we have: /// nodes that collapse into identity values. For example, if we have:
/// x = phi(1, 0, 0, 0) /// x = phi(1, 0, 0, 0)
/// y = and x, z /// y = and x, z
/// ///
/// .. and delete the predecessor corresponding to the '1', this will attem pt to /// .. and delete the predecessor corresponding to the '1', this will attem pt to
/// recursively fold the 'and' to 0. /// recursively fold the 'and' to 0.
void RemovePredecessorAndSimplify(BasicBlock *BB, BasicBlock *Pred, void RemovePredecessorAndSimplify(BasicBlock *BB, BasicBlock *Pred,
TargetData *TD = 0); DataLayout *TD = 0);
/// MergeBasicBlockIntoOnlyPred - BB is a block with one predecessor and it s /// MergeBasicBlockIntoOnlyPred - BB is a block with one predecessor and it s
/// predecessor is known to have one successor (BB!). Eliminate the edge /// predecessor is known to have one successor (BB!). Eliminate the edge
/// between them, moving the instructions in the predecessor into BB. This /// between them, moving the instructions in the predecessor into BB. This
/// deletes the predecessor block. /// deletes the predecessor block.
/// ///
void MergeBasicBlockIntoOnlyPred(BasicBlock *BB, Pass *P = 0); void MergeBasicBlockIntoOnlyPred(BasicBlock *BB, Pass *P = 0);
/// TryToSimplifyUncondBranchFromEmptyBlock - BB is known to contain an /// TryToSimplifyUncondBranchFromEmptyBlock - BB is known to contain an
/// unconditional branch, and contains no instructions other than PHI nodes , /// unconditional branch, and contains no instructions other than PHI nodes ,
skipping to change at line 125 skipping to change at line 135
/// orders them so it usually won't matter. /// orders them so it usually won't matter.
/// ///
bool EliminateDuplicatePHINodes(BasicBlock *BB); bool EliminateDuplicatePHINodes(BasicBlock *BB);
/// SimplifyCFG - This function is used to do simplification of a CFG. For /// SimplifyCFG - This function is used to do simplification of a CFG. For
/// example, it adjusts branches to branches to eliminate the extra hop, it /// example, it adjusts branches to branches to eliminate the extra hop, it
/// eliminates unreachable basic blocks, and does other "peephole" optimiza tion /// eliminates unreachable basic blocks, and does other "peephole" optimiza tion
/// of the CFG. It returns true if a modification was made, possibly delet ing /// of the CFG. It returns true if a modification was made, possibly delet ing
/// the basic block that was pointed to. /// the basic block that was pointed to.
/// ///
bool SimplifyCFG(BasicBlock *BB, const TargetData *TD = 0); bool SimplifyCFG(BasicBlock *BB, const DataLayout *TD = 0,
const TargetTransformInfo *TTI = 0);
/// FoldBranchToCommonDest - If this basic block is ONLY a setcc and a bran ch, /// FoldBranchToCommonDest - If this basic block is ONLY a setcc and a bran ch,
/// and if a predecessor branches to us and one of our successors, fold the /// and if a predecessor branches to us and one of our successors, fold the
/// setcc into the predecessor and use logical operations to pick the right /// setcc into the predecessor and use logical operations to pick the right
/// destination. /// destination.
bool FoldBranchToCommonDest(BranchInst *BI); bool FoldBranchToCommonDest(BranchInst *BI);
/// DemoteRegToStack - This function takes a virtual register computed by a n /// DemoteRegToStack - This function takes a virtual register computed by a n
/// Instruction and replaces it with a slot in the stack frame, allocated v ia /// Instruction and replaces it with a slot in the stack frame, allocated v ia
/// alloca. This allows the CFG to be changed around without fear of /// alloca. This allows the CFG to be changed around without fear of
skipping to change at line 153 skipping to change at line 164
/// DemotePHIToStack - This function takes a virtual register computed by a phi /// DemotePHIToStack - This function takes a virtual register computed by a phi
/// node and replaces it with a slot in the stack frame, allocated via allo ca. /// node and replaces it with a slot in the stack frame, allocated via allo ca.
/// The phi node is deleted and it returns the pointer to the alloca insert ed. /// The phi node is deleted and it returns the pointer to the alloca insert ed.
AllocaInst *DemotePHIToStack(PHINode *P, Instruction *AllocaPoint = 0); AllocaInst *DemotePHIToStack(PHINode *P, Instruction *AllocaPoint = 0);
/// getOrEnforceKnownAlignment - If the specified pointer has an alignment that /// getOrEnforceKnownAlignment - If the specified pointer has an alignment that
/// we can determine, return it, otherwise return 0. If PrefAlign is speci fied, /// we can determine, return it, otherwise return 0. If PrefAlign is speci fied,
/// and it is more than the alignment of the ultimate object, see if we can /// and it is more than the alignment of the ultimate object, see if we can
/// increase the alignment of the ultimate object, making this check succee d. /// increase the alignment of the ultimate object, making this check succee d.
unsigned getOrEnforceKnownAlignment(Value *V, unsigned PrefAlign, unsigned getOrEnforceKnownAlignment(Value *V, unsigned PrefAlign,
const TargetData *TD = 0); const DataLayout *TD = 0);
/// getKnownAlignment - Try to infer an alignment for the specified pointer . /// getKnownAlignment - Try to infer an alignment for the specified pointer .
static inline unsigned getKnownAlignment(Value *V, const TargetData *TD = 0 ) { static inline unsigned getKnownAlignment(Value *V, const DataLayout *TD = 0 ) {
return getOrEnforceKnownAlignment(V, 0, TD); return getOrEnforceKnownAlignment(V, 0, TD);
} }
/// EmitGEPOffset - Given a getelementptr instruction/constantexpr, emit th
e
/// code necessary to compute the offset from the base pointer (without add
ing
/// in the base pointer). Return the result as a signed integer of intptr
size.
/// When NoAssumptions is true, no assumptions about index computation not
/// overflowing is made.
template<typename IRBuilderTy>
Value *EmitGEPOffset(IRBuilderTy *Builder, const DataLayout &TD, User *GEP,
bool NoAssumptions = false) {
gep_type_iterator GTI = gep_type_begin(GEP);
Type *IntPtrTy = TD.getIntPtrType(GEP->getContext());
Value *Result = Constant::getNullValue(IntPtrTy);
// If the GEP is inbounds, we know that none of the addressing operations
will
// overflow in an unsigned sense.
bool isInBounds = cast<GEPOperator>(GEP)->isInBounds() && !NoAssumptions;
// Build a mask for high order bits.
unsigned IntPtrWidth = TD.getPointerSizeInBits();
uint64_t PtrSizeMask = ~0ULL >> (64-IntPtrWidth);
for (User::op_iterator i = GEP->op_begin() + 1, e = GEP->op_end(); i != e
;
++i, ++GTI) {
Value *Op = *i;
uint64_t Size = TD.getTypeAllocSize(GTI.getIndexedType()) & PtrSizeMask
;
if (ConstantInt *OpC = dyn_cast<ConstantInt>(Op)) {
if (OpC->isZero()) continue;
// Handle a struct index, which adds its field offset to the pointer.
if (StructType *STy = dyn_cast<StructType>(*GTI)) {
Size = TD.getStructLayout(STy)->getElementOffset(OpC->getZExtValue(
));
if (Size)
Result = Builder->CreateAdd(Result, ConstantInt::get(IntPtrTy, Si
ze),
GEP->getName()+".offs");
continue;
}
Constant *Scale = ConstantInt::get(IntPtrTy, Size);
Constant *OC = ConstantExpr::getIntegerCast(OpC, IntPtrTy, true /*SEx
t*/);
Scale = ConstantExpr::getMul(OC, Scale, isInBounds/*NUW*/);
// Emit an add instruction.
Result = Builder->CreateAdd(Result, Scale, GEP->getName()+".offs");
continue;
}
// Convert to correct type.
if (Op->getType() != IntPtrTy)
Op = Builder->CreateIntCast(Op, IntPtrTy, true, Op->getName()+".c");
if (Size != 1) {
// We'll let instcombine(mul) convert this to a shl if possible.
Op = Builder->CreateMul(Op, ConstantInt::get(IntPtrTy, Size),
GEP->getName()+".idx", isInBounds /*NUW*/);
}
// Emit an add instruction.
Result = Builder->CreateAdd(Op, Result, GEP->getName()+".offs");
}
return Result;
}
///===--------------------------------------------------------------------- ===// ///===--------------------------------------------------------------------- ===//
/// Dbg Intrinsic utilities /// Dbg Intrinsic utilities
/// ///
/// Inserts a llvm.dbg.value instrinsic before the stores to an alloca'd va lue /// Inserts a llvm.dbg.value instrinsic before the stores to an alloca'd va lue
/// that has an associated llvm.dbg.decl intrinsic. /// that has an associated llvm.dbg.decl intrinsic.
bool ConvertDebugDeclareToDebugValue(DbgDeclareInst *DDI, bool ConvertDebugDeclareToDebugValue(DbgDeclareInst *DDI,
StoreInst *SI, DIBuilder &Builder); StoreInst *SI, DIBuilder &Builder);
/// Inserts a llvm.dbg.value instrinsic before the stores to an alloca'd va lue /// Inserts a llvm.dbg.value instrinsic before the stores to an alloca'd va lue
 End of changes. 12 change blocks. 
11 lines changed or deleted 91 lines changed or added


 LockFileManager.h   LockFileManager.h 
skipping to change at line 50 skipping to change at line 50
LFS_Error LFS_Error
}; };
private: private:
SmallString<128> LockFileName; SmallString<128> LockFileName;
SmallString<128> UniqueLockFileName; SmallString<128> UniqueLockFileName;
Optional<std::pair<std::string, int> > Owner; Optional<std::pair<std::string, int> > Owner;
Optional<error_code> Error; Optional<error_code> Error;
LockFileManager(const LockFileManager &); LockFileManager(const LockFileManager &) LLVM_DELETED_FUNCTION;
LockFileManager &operator=(const LockFileManager &); LockFileManager &operator=(const LockFileManager &) LLVM_DELETED_FUNCTION
;
static Optional<std::pair<std::string, int> > static Optional<std::pair<std::string, int> >
readLockFile(StringRef LockFileName); readLockFile(StringRef LockFileName);
static bool processStillExecuting(StringRef Hostname, int PID); static bool processStillExecuting(StringRef Hostname, int PID);
public: public:
LockFileManager(StringRef FileName); LockFileManager(StringRef FileName);
~LockFileManager(); ~LockFileManager();
 End of changes. 1 change blocks. 
2 lines changed or deleted 3 lines changed or added


 LoopInfo.h   LoopInfo.h 
skipping to change at line 49 skipping to change at line 49
#include "llvm/ADT/STLExtras.h" #include "llvm/ADT/STLExtras.h"
#include "llvm/Analysis/Dominators.h" #include "llvm/Analysis/Dominators.h"
#include "llvm/Support/CFG.h" #include "llvm/Support/CFG.h"
#include "llvm/Support/raw_ostream.h" #include "llvm/Support/raw_ostream.h"
#include <algorithm> #include <algorithm>
#include <map> #include <map>
namespace llvm { namespace llvm {
template<typename T> template<typename T>
static void RemoveFromVector(std::vector<T*> &V, T *N) { inline void RemoveFromVector(std::vector<T*> &V, T *N) {
typename std::vector<T*>::iterator I = std::find(V.begin(), V.end(), N); typename std::vector<T*>::iterator I = std::find(V.begin(), V.end(), N);
assert(I != V.end() && "N is not in this list!"); assert(I != V.end() && "N is not in this list!");
V.erase(I); V.erase(I);
} }
class DominatorTree; class DominatorTree;
class LoopInfo; class LoopInfo;
class Loop; class Loop;
class PHINode; class PHINode;
template<class N, class M> class LoopInfoBase; template<class N, class M> class LoopInfoBase;
skipping to change at line 75 skipping to change at line 75
/// ///
template<class BlockT, class LoopT> template<class BlockT, class LoopT>
class LoopBase { class LoopBase {
LoopT *ParentLoop; LoopT *ParentLoop;
// SubLoops - Loops contained entirely within this one. // SubLoops - Loops contained entirely within this one.
std::vector<LoopT *> SubLoops; std::vector<LoopT *> SubLoops;
// Blocks - The list of blocks in this loop. First entry is the header n ode. // Blocks - The list of blocks in this loop. First entry is the header n ode.
std::vector<BlockT*> Blocks; std::vector<BlockT*> Blocks;
// DO NOT IMPLEMENT LoopBase(const LoopBase<BlockT, LoopT> &) LLVM_DELETED_FUNCTION;
LoopBase(const LoopBase<BlockT, LoopT> &); const LoopBase<BlockT, LoopT>&
// DO NOT IMPLEMENT operator=(const LoopBase<BlockT, LoopT> &) LLVM_DELETED_FUNCTION;
const LoopBase<BlockT, LoopT>&operator=(const LoopBase<BlockT, LoopT> &);
public: public:
/// Loop ctor - This creates an empty loop. /// Loop ctor - This creates an empty loop.
LoopBase() : ParentLoop(0) {} LoopBase() : ParentLoop(0) {}
~LoopBase() { ~LoopBase() {
for (size_t i = 0, e = SubLoops.size(); i != e; ++i) for (size_t i = 0, e = SubLoops.size(); i != e; ++i)
delete SubLoops[i]; delete SubLoops[i];
} }
/// getLoopDepth - Return the nesting level of this loop. An outer-most /// getLoopDepth - Return the nesting level of this loop. An outer-most
/// loop has depth 1, for consistency with loop depth values used for bas ic /// loop has depth 1, for consistency with loop depth values used for bas ic
skipping to change at line 100 skipping to change at line 99
unsigned getLoopDepth() const { unsigned getLoopDepth() const {
unsigned D = 1; unsigned D = 1;
for (const LoopT *CurLoop = ParentLoop; CurLoop; for (const LoopT *CurLoop = ParentLoop; CurLoop;
CurLoop = CurLoop->ParentLoop) CurLoop = CurLoop->ParentLoop)
++D; ++D;
return D; return D;
} }
BlockT *getHeader() const { return Blocks.front(); } BlockT *getHeader() const { return Blocks.front(); }
LoopT *getParentLoop() const { return ParentLoop; } LoopT *getParentLoop() const { return ParentLoop; }
/// setParentLoop is a raw interface for bypassing addChildLoop.
void setParentLoop(LoopT *L) { ParentLoop = L; }
/// contains - Return true if the specified loop is contained within in /// contains - Return true if the specified loop is contained within in
/// this loop. /// this loop.
/// ///
bool contains(const LoopT *L) const { bool contains(const LoopT *L) const {
if (L == this) return true; if (L == this) return true;
if (L == 0) return false; if (L == 0) return false;
return contains(L->getParentLoop()); return contains(L->getParentLoop());
} }
/// contains - Return true if the specified basic block is in this loop. /// contains - Return true if the specified basic block is in this loop.
skipping to change at line 125 skipping to change at line 127
/// contains - Return true if the specified instruction is in this loop. /// contains - Return true if the specified instruction is in this loop.
/// ///
template<class InstT> template<class InstT>
bool contains(const InstT *Inst) const { bool contains(const InstT *Inst) const {
return contains(Inst->getParent()); return contains(Inst->getParent());
} }
/// iterator/begin/end - Return the loops contained entirely within this loop. /// iterator/begin/end - Return the loops contained entirely within this loop.
/// ///
const std::vector<LoopT *> &getSubLoops() const { return SubLoops; } const std::vector<LoopT *> &getSubLoops() const { return SubLoops; }
std::vector<LoopT *> &getSubLoopsVector() { return SubLoops; }
typedef typename std::vector<LoopT *>::const_iterator iterator; typedef typename std::vector<LoopT *>::const_iterator iterator;
typedef typename std::vector<LoopT *>::const_reverse_iterator
reverse_iterator;
iterator begin() const { return SubLoops.begin(); } iterator begin() const { return SubLoops.begin(); }
iterator end() const { return SubLoops.end(); } iterator end() const { return SubLoops.end(); }
reverse_iterator rbegin() const { return SubLoops.rbegin(); }
reverse_iterator rend() const { return SubLoops.rend(); }
bool empty() const { return SubLoops.empty(); } bool empty() const { return SubLoops.empty(); }
/// getBlocks - Get a list of the basic blocks which make up this loop. /// getBlocks - Get a list of the basic blocks which make up this loop.
/// ///
const std::vector<BlockT*> &getBlocks() const { return Blocks; } const std::vector<BlockT*> &getBlocks() const { return Blocks; }
std::vector<BlockT*> &getBlocksVector() { return Blocks; }
typedef typename std::vector<BlockT*>::const_iterator block_iterator; typedef typename std::vector<BlockT*>::const_iterator block_iterator;
block_iterator block_begin() const { return Blocks.begin(); } block_iterator block_begin() const { return Blocks.begin(); }
block_iterator block_end() const { return Blocks.end(); } block_iterator block_end() const { return Blocks.end(); }
/// getNumBlocks - Get the number of blocks in this loop in constant time . /// getNumBlocks - Get the number of blocks in this loop in constant time .
unsigned getNumBlocks() const { unsigned getNumBlocks() const {
return Blocks.size(); return Blocks.size();
} }
/// isLoopExiting - True if terminator in the block can branch to another /// isLoopExiting - True if terminator in the block can branch to another
skipping to change at line 184 skipping to change at line 192
// //
// Note that all of these methods can fail on general loops (ie, there ma y not // Note that all of these methods can fail on general loops (ie, there ma y not
// be a preheader, etc). For best success, the loop simplification and // be a preheader, etc). For best success, the loop simplification and
// induction variable canonicalization pass should be used to normalize l oops // induction variable canonicalization pass should be used to normalize l oops
// for easy analysis. These methods assume canonical loops. // for easy analysis. These methods assume canonical loops.
/// getExitingBlocks - Return all blocks inside the loop that have succes sors /// getExitingBlocks - Return all blocks inside the loop that have succes sors
/// outside of the loop. These are the blocks _inside of the current loo p_ /// outside of the loop. These are the blocks _inside of the current loo p_
/// which branch out. The returned list is always unique. /// which branch out. The returned list is always unique.
/// ///
void getExitingBlocks(SmallVectorImpl<BlockT *> &ExitingBlocks) const { void getExitingBlocks(SmallVectorImpl<BlockT *> &ExitingBlocks) const;
// Sort the blocks vector so that we can use binary search to do quick
// lookups.
SmallVector<BlockT*, 128> LoopBBs(block_begin(), block_end());
std::sort(LoopBBs.begin(), LoopBBs.end());
typedef GraphTraits<BlockT*> BlockTraits;
for (block_iterator BI = block_begin(), BE = block_end(); BI != BE; ++B
I)
for (typename BlockTraits::ChildIteratorType I =
BlockTraits::child_begin(*BI), E = BlockTraits::child_end(*BI);
I != E; ++I)
if (!std::binary_search(LoopBBs.begin(), LoopBBs.end(), *I)) {
// Not in current loop? It must be an exit block.
ExitingBlocks.push_back(*BI);
break;
}
}
/// getExitingBlock - If getExitingBlocks would return exactly one block, /// getExitingBlock - If getExitingBlocks would return exactly one block,
/// return that block. Otherwise return null. /// return that block. Otherwise return null.
BlockT *getExitingBlock() const { BlockT *getExitingBlock() const;
SmallVector<BlockT*, 8> ExitingBlocks;
getExitingBlocks(ExitingBlocks);
if (ExitingBlocks.size() == 1)
return ExitingBlocks[0];
return 0;
}
/// getExitBlocks - Return all of the successor blocks of this loop. The se /// getExitBlocks - Return all of the successor blocks of this loop. The se
/// are the blocks _outside of the current loop_ which are branched to. /// are the blocks _outside of the current loop_ which are branched to.
/// ///
void getExitBlocks(SmallVectorImpl<BlockT*> &ExitBlocks) const { void getExitBlocks(SmallVectorImpl<BlockT*> &ExitBlocks) const;
// Sort the blocks vector so that we can use binary search to do quick
// lookups.
SmallVector<BlockT*, 128> LoopBBs(block_begin(), block_end());
std::sort(LoopBBs.begin(), LoopBBs.end());
typedef GraphTraits<BlockT*> BlockTraits;
for (block_iterator BI = block_begin(), BE = block_end(); BI != BE; ++B
I)
for (typename BlockTraits::ChildIteratorType I =
BlockTraits::child_begin(*BI), E = BlockTraits::child_end(*BI);
I != E; ++I)
if (!std::binary_search(LoopBBs.begin(), LoopBBs.end(), *I))
// Not in current loop? It must be an exit block.
ExitBlocks.push_back(*I);
}
/// getExitBlock - If getExitBlocks would return exactly one block, /// getExitBlock - If getExitBlocks would return exactly one block,
/// return that block. Otherwise return null. /// return that block. Otherwise return null.
BlockT *getExitBlock() const { BlockT *getExitBlock() const;
SmallVector<BlockT*, 8> ExitBlocks;
getExitBlocks(ExitBlocks);
if (ExitBlocks.size() == 1)
return ExitBlocks[0];
return 0;
}
/// Edge type. /// Edge type.
typedef std::pair<BlockT*, BlockT*> Edge; typedef std::pair<const BlockT*, const BlockT*> Edge;
/// getExitEdges - Return all pairs of (_inside_block_,_outside_block_). /// getExitEdges - Return all pairs of (_inside_block_,_outside_block_).
template <typename EdgeT> void getExitEdges(SmallVectorImpl<Edge> &ExitEdges) const;
void getExitEdges(SmallVectorImpl<EdgeT> &ExitEdges) const {
// Sort the blocks vector so that we can use binary search to do quick
// lookups.
SmallVector<BlockT*, 128> LoopBBs(block_begin(), block_end());
array_pod_sort(LoopBBs.begin(), LoopBBs.end());
typedef GraphTraits<BlockT*> BlockTraits;
for (block_iterator BI = block_begin(), BE = block_end(); BI != BE; ++B
I)
for (typename BlockTraits::ChildIteratorType I =
BlockTraits::child_begin(*BI), E = BlockTraits::child_end(*BI);
I != E; ++I)
if (!std::binary_search(LoopBBs.begin(), LoopBBs.end(), *I))
// Not in current loop? It must be an exit block.
ExitEdges.push_back(EdgeT(*BI, *I));
}
/// getLoopPreheader - If there is a preheader for this loop, return it. A /// getLoopPreheader - If there is a preheader for this loop, return it. A
/// loop has a preheader if there is only one edge to the header of the l oop /// loop has a preheader if there is only one edge to the header of the l oop
/// from outside of the loop. If this is the case, the block branching t o the /// from outside of the loop. If this is the case, the block branching t o the
/// header of the loop is the preheader node. /// header of the loop is the preheader node.
/// ///
/// This method returns null if there is no preheader for the loop. /// This method returns null if there is no preheader for the loop.
/// ///
BlockT *getLoopPreheader() const { BlockT *getLoopPreheader() const;
// Keep track of nodes outside the loop branching to the header...
BlockT *Out = getLoopPredecessor();
if (!Out) return 0;
// Make sure there is only one exit out of the preheader.
typedef GraphTraits<BlockT*> BlockTraits;
typename BlockTraits::ChildIteratorType SI = BlockTraits::child_begin(O
ut);
++SI;
if (SI != BlockTraits::child_end(Out))
return 0; // Multiple exits from the block, must not be a preheader.
// The predecessor has exactly one successor, so it is a preheader.
return Out;
}
/// getLoopPredecessor - If the given loop's header has exactly one uniqu e /// getLoopPredecessor - If the given loop's header has exactly one uniqu e
/// predecessor outside the loop, return it. Otherwise return null. /// predecessor outside the loop, return it. Otherwise return null.
/// This is less strict that the loop "preheader" concept, which requires /// This is less strict that the loop "preheader" concept, which requires
/// the predecessor to have exactly one successor. /// the predecessor to have exactly one successor.
/// ///
BlockT *getLoopPredecessor() const { BlockT *getLoopPredecessor() const;
// Keep track of nodes outside the loop branching to the header...
BlockT *Out = 0;
// Loop over the predecessors of the header node...
BlockT *Header = getHeader();
typedef GraphTraits<BlockT*> BlockTraits;
typedef GraphTraits<Inverse<BlockT*> > InvBlockTraits;
for (typename InvBlockTraits::ChildIteratorType PI =
InvBlockTraits::child_begin(Header),
PE = InvBlockTraits::child_end(Header); PI != PE; ++PI) {
typename InvBlockTraits::NodeType *N = *PI;
if (!contains(N)) { // If the block is not in the loop...
if (Out && Out != N)
return 0; // Multiple predecessors outside the loop
Out = N;
}
}
// Make sure there is only one exit out of the preheader.
assert(Out && "Header of loop has no predecessors from outside loop?");
return Out;
}
/// getLoopLatch - If there is a single latch block for this loop, return it. /// getLoopLatch - If there is a single latch block for this loop, return it.
/// A latch block is a block that contains a branch back to the header. /// A latch block is a block that contains a branch back to the header.
BlockT *getLoopLatch() const { BlockT *getLoopLatch() const;
BlockT *Header = getHeader();
typedef GraphTraits<Inverse<BlockT*> > InvBlockTraits;
typename InvBlockTraits::ChildIteratorType PI =
InvBlockTraits::child_begin(Hea
der);
typename InvBlockTraits::ChildIteratorType PE =
InvBlockTraits::child_end(Hea
der);
BlockT *Latch = 0;
for (; PI != PE; ++PI) {
typename InvBlockTraits::NodeType *N = *PI;
if (contains(N)) {
if (Latch) return 0;
Latch = N;
}
}
return Latch;
}
//===-------------------------------------------------------------------- ===// //===-------------------------------------------------------------------- ===//
// APIs for updating loop information after changing the CFG // APIs for updating loop information after changing the CFG
// //
/// addBasicBlockToLoop - This method is used by other analyses to update loop /// addBasicBlockToLoop - This method is used by other analyses to update loop
/// information. NewBB is set to be a new member of the current loop. /// information. NewBB is set to be a new member of the current loop.
/// Because of this, it is added as a member of all parent loops, and is added /// Because of this, it is added as a member of all parent loops, and is added
/// to the specified LoopInfo object as being in the current basic block. It /// to the specified LoopInfo object as being in the current basic block. It
/// is not valid to replace the loop header with this method. /// is not valid to replace the loop header with this method.
/// ///
void addBasicBlockToLoop(BlockT *NewBB, LoopInfoBase<BlockT, LoopT> &LI); void addBasicBlockToLoop(BlockT *NewBB, LoopInfoBase<BlockT, LoopT> &LI);
/// replaceChildLoopWith - This is used when splitting loops up. It repl aces /// replaceChildLoopWith - This is used when splitting loops up. It repl aces
/// the OldChild entry in our children list with NewChild, and updates th e /// the OldChild entry in our children list with NewChild, and updates th e
/// parent pointer of OldChild to be null and the NewChild to be this loo p. /// parent pointer of OldChild to be null and the NewChild to be this loo p.
/// This updates the loop depth of the new child. /// This updates the loop depth of the new child.
void replaceChildLoopWith(LoopT *OldChild, void replaceChildLoopWith(LoopT *OldChild, LoopT *NewChild);
LoopT *NewChild) {
assert(OldChild->ParentLoop == this && "This loop is already broken!");
assert(NewChild->ParentLoop == 0 && "NewChild already has a parent!");
typename std::vector<LoopT *>::iterator I =
std::find(SubLoops.begin(), SubLoops.end(), OldCh
ild);
assert(I != SubLoops.end() && "OldChild not in loop!");
*I = NewChild;
OldChild->ParentLoop = 0;
NewChild->ParentLoop = static_cast<LoopT *>(this);
}
/// addChildLoop - Add the specified loop to be a child of this loop. Th is /// addChildLoop - Add the specified loop to be a child of this loop. Th is
/// updates the loop depth of the new child. /// updates the loop depth of the new child.
/// ///
void addChildLoop(LoopT *NewChild) { void addChildLoop(LoopT *NewChild) {
assert(NewChild->ParentLoop == 0 && "NewChild already has a parent!"); assert(NewChild->ParentLoop == 0 && "NewChild already has a parent!");
NewChild->ParentLoop = static_cast<LoopT *>(this); NewChild->ParentLoop = static_cast<LoopT *>(this);
SubLoops.push_back(NewChild); SubLoops.push_back(NewChild);
} }
skipping to change at line 414 skipping to change at line 302
} }
/// removeBlockFromLoop - This removes the specified basic block from the /// removeBlockFromLoop - This removes the specified basic block from the
/// current loop, updating the Blocks as appropriate. This does not upda te /// current loop, updating the Blocks as appropriate. This does not upda te
/// the mapping in the LoopInfo class. /// the mapping in the LoopInfo class.
void removeBlockFromLoop(BlockT *BB) { void removeBlockFromLoop(BlockT *BB) {
RemoveFromVector(Blocks, BB); RemoveFromVector(Blocks, BB);
} }
/// verifyLoop - Verify loop structure /// verifyLoop - Verify loop structure
void verifyLoop() const { void verifyLoop() const;
#ifndef NDEBUG
assert(!Blocks.empty() && "Loop header is missing");
// Setup for using a depth-first iterator to visit every block in the l
oop.
SmallVector<BlockT*, 8> ExitBBs;
getExitBlocks(ExitBBs);
llvm::SmallPtrSet<BlockT*, 8> VisitSet;
VisitSet.insert(ExitBBs.begin(), ExitBBs.end());
df_ext_iterator<BlockT*, llvm::SmallPtrSet<BlockT*, 8> >
BI = df_ext_begin(getHeader(), VisitSet),
BE = df_ext_end(getHeader(), VisitSet);
// Keep track of the number of BBs visited.
unsigned NumVisited = 0;
// Sort the blocks vector so that we can use binary search to do quick
// lookups.
SmallVector<BlockT*, 128> LoopBBs(block_begin(), block_end());
std::sort(LoopBBs.begin(), LoopBBs.end());
// Check the individual blocks.
for ( ; BI != BE; ++BI) {
BlockT *BB = *BI;
bool HasInsideLoopSuccs = false;
bool HasInsideLoopPreds = false;
SmallVector<BlockT *, 2> OutsideLoopPreds;
typedef GraphTraits<BlockT*> BlockTraits;
for (typename BlockTraits::ChildIteratorType SI =
BlockTraits::child_begin(BB), SE = BlockTraits::child_end(BB);
SI != SE; ++SI)
if (std::binary_search(LoopBBs.begin(), LoopBBs.end(), *SI)) {
HasInsideLoopSuccs = true;
break;
}
typedef GraphTraits<Inverse<BlockT*> > InvBlockTraits;
for (typename InvBlockTraits::ChildIteratorType PI =
InvBlockTraits::child_begin(BB), PE = InvBlockTraits::child_end(
BB);
PI != PE; ++PI) {
BlockT *N = *PI;
if (std::binary_search(LoopBBs.begin(), LoopBBs.end(), N))
HasInsideLoopPreds = true;
else
OutsideLoopPreds.push_back(N);
}
if (BB == getHeader()) {
assert(!OutsideLoopPreds.empty() && "Loop is unreachable!");
} else if (!OutsideLoopPreds.empty()) {
// A non-header loop shouldn't be reachable from outside the loop,
// though it is permitted if the predecessor is not itself actually
// reachable.
BlockT *EntryBB = BB->getParent()->begin();
for (df_iterator<BlockT *> NI = df_begin(EntryBB),
NE = df_end(EntryBB); NI != NE; ++NI)
for (unsigned i = 0, e = OutsideLoopPreds.size(); i != e; ++i)
assert(*NI != OutsideLoopPreds[i] &&
"Loop has multiple entry points!");
}
assert(HasInsideLoopPreds && "Loop block has no in-loop predecessors!
");
assert(HasInsideLoopSuccs && "Loop block has no in-loop successors!")
;
assert(BB != getHeader()->getParent()->begin() &&
"Loop contains function entry block!");
NumVisited++;
}
assert(NumVisited == getNumBlocks() && "Unreachable block in loop");
// Check the subloops.
for (iterator I = begin(), E = end(); I != E; ++I)
// Each block in each subloop should be contained within this loop.
for (block_iterator BI = (*I)->block_begin(), BE = (*I)->block_end();
BI != BE; ++BI) {
assert(std::binary_search(LoopBBs.begin(), LoopBBs.end(), *BI) &&
"Loop does not contain all the blocks of a subloop!");
}
// Check the parent loop pointer.
if (ParentLoop) {
assert(std::find(ParentLoop->begin(), ParentLoop->end(), this) !=
ParentLoop->end() &&
"Loop is not a subloop of its parent!");
}
#endif
}
/// verifyLoop - Verify loop structure of this loop and all nested loops. /// verifyLoop - Verify loop structure of this loop and all nested loops.
void verifyLoopNest(DenseSet<const LoopT*> *Loops) const { void verifyLoopNest(DenseSet<const LoopT*> *Loops) const;
Loops->insert(static_cast<const LoopT *>(this));
// Verify this loop.
verifyLoop();
// Verify the subloops.
for (iterator I = begin(), E = end(); I != E; ++I)
(*I)->verifyLoopNest(Loops);
}
void print(raw_ostream &OS, unsigned Depth = 0) const {
OS.indent(Depth*2) << "Loop at depth " << getLoopDepth()
<< " containing: ";
for (unsigned i = 0; i < getBlocks().size(); ++i) {
if (i) OS << ",";
BlockT *BB = getBlocks()[i];
WriteAsOperand(OS, BB, false);
if (BB == getHeader()) OS << "<header>";
if (BB == getLoopLatch()) OS << "<latch>";
if (isLoopExiting(BB)) OS << "<exiting>";
}
OS << "\n";
for (iterator I = begin(), E = end(); I != E; ++I) void print(raw_ostream &OS, unsigned Depth = 0) const;
(*I)->print(OS, Depth+2);
}
protected: protected:
friend class LoopInfoBase<BlockT, LoopT>; friend class LoopInfoBase<BlockT, LoopT>;
explicit LoopBase(BlockT *BB) : ParentLoop(0) { explicit LoopBase(BlockT *BB) : ParentLoop(0) {
Blocks.push_back(BB); Blocks.push_back(BB);
} }
}; };
template<class BlockT, class LoopT> template<class BlockT, class LoopT>
raw_ostream& operator<<(raw_ostream &OS, const LoopBase<BlockT, LoopT> &Loo p) { raw_ostream& operator<<(raw_ostream &OS, const LoopBase<BlockT, LoopT> &Loo p) {
Loop.print(OS); Loop.print(OS);
return OS; return OS;
} }
// Implementation in LoopInfoImpl.h
#ifdef __GNUC__
__extension__ extern template class LoopBase<BasicBlock, Loop>;
#endif
class Loop : public LoopBase<BasicBlock, Loop> { class Loop : public LoopBase<BasicBlock, Loop> {
public: public:
Loop() {} Loop() {}
/// isLoopInvariant - Return true if the specified value is loop invarian t /// isLoopInvariant - Return true if the specified value is loop invarian t
/// ///
bool isLoopInvariant(Value *V) const; bool isLoopInvariant(Value *V) const;
/// hasLoopInvariantOperands - Return true if all the operands of the /// hasLoopInvariantOperands - Return true if all the operands of the
/// specified instruction are loop invariant. /// specified instruction are loop invariant.
skipping to change at line 634 skipping to change at line 418
/// ///
template<class BlockT, class LoopT> template<class BlockT, class LoopT>
class LoopInfoBase { class LoopInfoBase {
// BBMap - Mapping of basic blocks to the inner most loop they occur in // BBMap - Mapping of basic blocks to the inner most loop they occur in
DenseMap<BlockT *, LoopT *> BBMap; DenseMap<BlockT *, LoopT *> BBMap;
std::vector<LoopT *> TopLevelLoops; std::vector<LoopT *> TopLevelLoops;
friend class LoopBase<BlockT, LoopT>; friend class LoopBase<BlockT, LoopT>;
friend class LoopInfo; friend class LoopInfo;
void operator=(const LoopInfoBase &); // do not implement void operator=(const LoopInfoBase &) LLVM_DELETED_FUNCTION;
LoopInfoBase(const LoopInfo &); // do not implement LoopInfoBase(const LoopInfo &) LLVM_DELETED_FUNCTION;
public: public:
LoopInfoBase() { } LoopInfoBase() { }
~LoopInfoBase() { releaseMemory(); } ~LoopInfoBase() { releaseMemory(); }
void releaseMemory() { void releaseMemory() {
for (typename std::vector<LoopT *>::iterator I = for (typename std::vector<LoopT *>::iterator I =
TopLevelLoops.begin(), E = TopLevelLoops.end(); I != E; ++I) TopLevelLoops.begin(), E = TopLevelLoops.end(); I != E; ++I)
delete *I; // Delete all of the loops... delete *I; // Delete all of the loops...
BBMap.clear(); // Reset internal state of ana lysis BBMap.clear(); // Reset internal state of ana lysis
TopLevelLoops.clear(); TopLevelLoops.clear();
} }
/// iterator/begin/end - The interface to the top-level loops in the curr ent /// iterator/begin/end - The interface to the top-level loops in the curr ent
/// function. /// function.
/// ///
typedef typename std::vector<LoopT *>::const_iterator iterator; typedef typename std::vector<LoopT *>::const_iterator iterator;
typedef typename std::vector<LoopT *>::const_reverse_iterator
reverse_iterator;
iterator begin() const { return TopLevelLoops.begin(); } iterator begin() const { return TopLevelLoops.begin(); }
iterator end() const { return TopLevelLoops.end(); } iterator end() const { return TopLevelLoops.end(); }
reverse_iterator rbegin() const { return TopLevelLoops.rbegin(); }
reverse_iterator rend() const { return TopLevelLoops.rend(); }
bool empty() const { return TopLevelLoops.empty(); } bool empty() const { return TopLevelLoops.empty(); }
/// getLoopFor - Return the inner most loop that BB lives in. If a basic /// getLoopFor - Return the inner most loop that BB lives in. If a basic
/// block is in no loop (for example the entry node), null is returned. /// block is in no loop (for example the entry node), null is returned.
/// ///
LoopT *getLoopFor(const BlockT *BB) const { LoopT *getLoopFor(const BlockT *BB) const {
return BBMap.lookup(const_cast<BlockT*>(BB)); return BBMap.lookup(const_cast<BlockT*>(BB));
} }
/// operator[] - same as getLoopFor... /// operator[] - same as getLoopFor...
skipping to change at line 747 skipping to change at line 535
// Internals // Internals
static bool isNotAlreadyContainedIn(const LoopT *SubLoop, static bool isNotAlreadyContainedIn(const LoopT *SubLoop,
const LoopT *ParentLoop) { const LoopT *ParentLoop) {
if (SubLoop == 0) return true; if (SubLoop == 0) return true;
if (SubLoop == ParentLoop) return false; if (SubLoop == ParentLoop) return false;
return isNotAlreadyContainedIn(SubLoop->getParentLoop(), ParentLoop); return isNotAlreadyContainedIn(SubLoop->getParentLoop(), ParentLoop);
} }
void Calculate(DominatorTreeBase<BlockT> &DT) { /// Create the loop forest using a stable algorithm.
BlockT *RootNode = DT.getRootNode()->getBlock(); void Analyze(DominatorTreeBase<BlockT> &DomTree);
for (df_iterator<BlockT*> NI = df_begin(RootNode),
NE = df_end(RootNode); NI != NE; ++NI)
if (LoopT *L = ConsiderForLoop(*NI, DT))
TopLevelLoops.push_back(L);
}
LoopT *ConsiderForLoop(BlockT *BB, DominatorTreeBase<BlockT> &DT) {
if (BBMap.count(BB)) return 0; // Haven't processed this node?
std::vector<BlockT *> TodoStack;
// Scan the predecessors of BB, checking to see if BB dominates any of
// them. This identifies backedges which target this node...
typedef GraphTraits<Inverse<BlockT*> > InvBlockTraits;
for (typename InvBlockTraits::ChildIteratorType I =
InvBlockTraits::child_begin(BB), E = InvBlockTraits::child_end(BB)
;
I != E; ++I) {
typename InvBlockTraits::NodeType *N = *I;
// If BB dominates its predecessor...
if (DT.dominates(BB, N) && DT.isReachableFromEntry(N))
TodoStack.push_back(N);
}
if (TodoStack.empty()) return 0; // No backedges to this block...
// Create a new loop to represent this basic block...
LoopT *L = new LoopT(BB);
BBMap[BB] = L;
while (!TodoStack.empty()) { // Process all the nodes in the loop
BlockT *X = TodoStack.back();
TodoStack.pop_back();
if (!L->contains(X) && // As of yet unprocessed??
DT.isReachableFromEntry(X)) {
// Check to see if this block already belongs to a loop. If this o
ccurs
// then we have a case where a loop that is supposed to be a child
of
// the current loop was processed before the current loop. When th
is
// occurs, this child loop gets added to a part of the current loop
,
// making it a sibling to the current loop. We have to reparent th
is
// loop.
if (LoopT *SubLoop =
const_cast<LoopT *>(getLoopFor(X)))
if (SubLoop->getHeader() == X && isNotAlreadyContainedIn(SubLoop,
L)){
// Remove the subloop from its current parent...
assert(SubLoop->ParentLoop && SubLoop->ParentLoop != L);
LoopT *SLP = SubLoop->ParentLoop; // SubLoopParent
typename std::vector<LoopT *>::iterator I =
std::find(SLP->SubLoops.begin(), SLP->SubLoops.end(), SubLoop
);
assert(I != SLP->SubLoops.end() &&"SubLoop not a child of paren
t?");
SLP->SubLoops.erase(I); // Remove from parent...
// Add the subloop to THIS loop...
SubLoop->ParentLoop = L;
L->SubLoops.push_back(SubLoop);
}
// Normal case, add the block to our loop...
L->Blocks.push_back(X);
typedef GraphTraits<Inverse<BlockT*> > InvBlockTraits;
// Add all of the predecessors of X to the end of the work stack...
TodoStack.insert(TodoStack.end(), InvBlockTraits::child_begin(X),
InvBlockTraits::child_end(X));
}
}
// If there are any loops nested within this loop, create them now!
for (typename std::vector<BlockT*>::iterator I = L->Blocks.begin(),
E = L->Blocks.end(); I != E; ++I)
if (LoopT *NewLoop = ConsiderForLoop(*I, DT)) {
L->SubLoops.push_back(NewLoop);
NewLoop->ParentLoop = L;
}
// Add the basic blocks that comprise this loop to the BBMap so that th
is
// loop can be found for them.
//
for (typename std::vector<BlockT*>::iterator I = L->Blocks.begin(),
E = L->Blocks.end(); I != E; ++I)
BBMap.insert(std::make_pair(*I, L));
// Now that we have a list of all of the child loops of this loop, chec
k to
// see if any of them should actually be nested inside of each other.
We
// can accidentally pull loops our of their parents, so we must make su
re to
// organize the loop nests correctly now.
{
std::map<BlockT *, LoopT *> ContainingLoops;
for (unsigned i = 0; i != L->SubLoops.size(); ++i) {
LoopT *Child = L->SubLoops[i];
assert(Child->getParentLoop() == L && "Not proper child loop?");
if (LoopT *ContainingLoop = ContainingLoops[Child->getHeader()]) {
// If there is already a loop which contains this loop, move this
loop
// into the containing loop.
MoveSiblingLoopInto(Child, ContainingLoop);
--i; // The loop got removed from the SubLoops list.
} else {
// This is currently considered to be a top-level loop. Check to
see
// if any of the contained blocks are loop headers for subloops w
e
// have already processed.
for (unsigned b = 0, e = Child->Blocks.size(); b != e; ++b) {
LoopT *&BlockLoop = ContainingLoops[Child->Blocks[b]];
if (BlockLoop == 0) { // Child block not processed yet...
BlockLoop = Child;
} else if (BlockLoop != Child) {
LoopT *SubLoop = BlockLoop;
// Reparent all of the blocks which used to belong to BlockLo
ops
for (unsigned j = 0, f = SubLoop->Blocks.size(); j != f; ++j)
ContainingLoops[SubLoop->Blocks[j]] = Child;
// There is already a loop which contains this block, that me
ans
// that we should reparent the loop which the block is curren
tly
// considered to belong to to be a child of this loop.
MoveSiblingLoopInto(SubLoop, Child);
--i; // We just shrunk the SubLoops list.
}
}
}
}
}
return L;
}
/// MoveSiblingLoopInto - This method moves the NewChild loop to live ins
ide
/// of the NewParent Loop, instead of being a sibling of it.
void MoveSiblingLoopInto(LoopT *NewChild,
LoopT *NewParent) {
LoopT *OldParent = NewChild->getParentLoop();
assert(OldParent && OldParent == NewParent->getParentLoop() &&
NewChild != NewParent && "Not sibling loops!");
// Remove NewChild from being a child of OldParent
typename std::vector<LoopT *>::iterator I =
std::find(OldParent->SubLoops.begin(), OldParent->SubLoops.end(),
NewChild);
assert(I != OldParent->SubLoops.end() && "Parent fields incorrect??");
OldParent->SubLoops.erase(I); // Remove from parent's subloops list
NewChild->ParentLoop = 0;
InsertLoopInto(NewChild, NewParent);
}
/// InsertLoopInto - This inserts loop L into the specified parent loop.
If
/// the parent loop contains a loop which should contain L, the loop gets
/// inserted into L instead.
void InsertLoopInto(LoopT *L, LoopT *Parent) {
BlockT *LHeader = L->getHeader();
assert(Parent->contains(LHeader) &&
"This loop should not be inserted here!");
// Check to see if it belongs in a child loop...
for (unsigned i = 0, e = static_cast<unsigned>(Parent->SubLoops.size())
;
i != e; ++i)
if (Parent->SubLoops[i]->contains(LHeader)) {
InsertLoopInto(L, Parent->SubLoops[i]);
return;
}
// If not, insert it here!
Parent->SubLoops.push_back(L);
L->ParentLoop = Parent;
}
// Debugging // Debugging
void print(raw_ostream &OS) const { void print(raw_ostream &OS) const;
for (unsigned i = 0; i < TopLevelLoops.size(); ++i)
TopLevelLoops[i]->print(OS);
#if 0
for (DenseMap<BasicBlock*, LoopT*>::const_iterator I = BBMap.begin(),
E = BBMap.end(); I != E; ++I)
OS << "BB '" << I->first->getName() << "' level = "
<< I->second->getLoopDepth() << "\n";
#endif
}
}; };
// Implementation in LoopInfoImpl.h
#ifdef __GNUC__
__extension__ extern template class LoopInfoBase<BasicBlock, Loop>;
#endif
class LoopInfo : public FunctionPass { class LoopInfo : public FunctionPass {
LoopInfoBase<BasicBlock, Loop> LI; LoopInfoBase<BasicBlock, Loop> LI;
friend class LoopBase<BasicBlock, Loop>; friend class LoopBase<BasicBlock, Loop>;
void operator=(const LoopInfo &); // do not implement void operator=(const LoopInfo &) LLVM_DELETED_FUNCTION;
LoopInfo(const LoopInfo &); // do not implement LoopInfo(const LoopInfo &) LLVM_DELETED_FUNCTION;
public: public:
static char ID; // Pass identification, replacement for typeid static char ID; // Pass identification, replacement for typeid
LoopInfo() : FunctionPass(ID) { LoopInfo() : FunctionPass(ID) {
initializeLoopInfoPass(*PassRegistry::getPassRegistry()); initializeLoopInfoPass(*PassRegistry::getPassRegistry());
} }
LoopInfoBase<BasicBlock, Loop>& getBase() { return LI; } LoopInfoBase<BasicBlock, Loop>& getBase() { return LI; }
/// iterator/begin/end - The interface to the top-level loops in the curr ent /// iterator/begin/end - The interface to the top-level loops in the curr ent
/// function. /// function.
/// ///
typedef LoopInfoBase<BasicBlock, Loop>::iterator iterator; typedef LoopInfoBase<BasicBlock, Loop>::iterator iterator;
typedef LoopInfoBase<BasicBlock, Loop>::reverse_iterator reverse_iterator ;
inline iterator begin() const { return LI.begin(); } inline iterator begin() const { return LI.begin(); }
inline iterator end() const { return LI.end(); } inline iterator end() const { return LI.end(); }
inline reverse_iterator rbegin() const { return LI.rbegin(); }
inline reverse_iterator rend() const { return LI.rend(); }
bool empty() const { return LI.empty(); } bool empty() const { return LI.empty(); }
/// getLoopFor - Return the inner most loop that BB lives in. If a basic /// getLoopFor - Return the inner most loop that BB lives in. If a basic
/// block is in no loop (for example the entry node), null is returned. /// block is in no loop (for example the entry node), null is returned.
/// ///
inline Loop *getLoopFor(const BasicBlock *BB) const { inline Loop *getLoopFor(const BasicBlock *BB) const {
return LI.getLoopFor(BB); return LI.getLoopFor(BB);
} }
/// operator[] - same as getLoopFor... /// operator[] - same as getLoopFor...
skipping to change at line 1076 skipping to change at line 697
static NodeType *getEntryNode(Loop *L) { return L; } static NodeType *getEntryNode(Loop *L) { return L; }
static inline ChildIteratorType child_begin(NodeType *N) { static inline ChildIteratorType child_begin(NodeType *N) {
return N->begin(); return N->begin();
} }
static inline ChildIteratorType child_end(NodeType *N) { static inline ChildIteratorType child_end(NodeType *N) {
return N->end(); return N->end();
} }
}; };
template<class BlockT, class LoopT>
void
LoopBase<BlockT, LoopT>::addBasicBlockToLoop(BlockT *NewBB,
LoopInfoBase<BlockT, LoopT> &L
IB) {
assert((Blocks.empty() || LIB[getHeader()] == this) &&
"Incorrect LI specified for this loop!");
assert(NewBB && "Cannot add a null basic block to the loop!");
assert(LIB[NewBB] == 0 && "BasicBlock already in the loop!");
LoopT *L = static_cast<LoopT *>(this);
// Add the loop mapping to the LoopInfo object...
LIB.BBMap[NewBB] = L;
// Add the basic block to this loop and all parent loops...
while (L) {
L->Blocks.push_back(NewBB);
L = L->getParentLoop();
}
}
} // End llvm namespace } // End llvm namespace
#endif #endif
 End of changes. 31 change blocks. 
484 lines changed or deleted 50 lines changed or added


 LoopIterator.h   LoopIterator.h 
skipping to change at line 112 skipping to change at line 112
unsigned getRPO(BasicBlock *BB) const { unsigned getRPO(BasicBlock *BB) const {
return 1 + PostBlocks.size() - getPostorder(BB); return 1 + PostBlocks.size() - getPostorder(BB);
} }
void clear() { void clear() {
PostNumbers.clear(); PostNumbers.clear();
PostBlocks.clear(); PostBlocks.clear();
} }
}; };
/// Specialize po_iterator_storage to record postorder numbers.
template<> class po_iterator_storage<LoopBlocksTraversal, true> {
LoopBlocksTraversal &LBT;
public:
po_iterator_storage(LoopBlocksTraversal &lbs) : LBT(lbs) {}
// These functions are defined below.
bool insertEdge(BasicBlock *From, BasicBlock *To);
void finishPostorder(BasicBlock *BB);
};
/// Traverse the blocks in a loop using a depth-first search. /// Traverse the blocks in a loop using a depth-first search.
class LoopBlocksTraversal { class LoopBlocksTraversal {
public: public:
/// Graph traversal iterator. /// Graph traversal iterator.
typedef po_iterator<BasicBlock*, LoopBlocksTraversal, true> POTIterator; typedef po_iterator<BasicBlock*, LoopBlocksTraversal, true> POTIterator;
private: private:
LoopBlocksDFS &DFS; LoopBlocksDFS &DFS;
LoopInfo *LI; LoopInfo *LI;
skipping to change at line 158 skipping to change at line 168
return DFS.PostNumbers.insert(std::make_pair(BB, 0)).second; return DFS.PostNumbers.insert(std::make_pair(BB, 0)).second;
} }
/// Called by po_iterator each time it advances, indicating a block's /// Called by po_iterator each time it advances, indicating a block's
/// postorder. /// postorder.
void finishPostorder(BasicBlock *BB) { void finishPostorder(BasicBlock *BB) {
assert(DFS.PostNumbers.count(BB) && "Loop DFS skipped preorder"); assert(DFS.PostNumbers.count(BB) && "Loop DFS skipped preorder");
DFS.PostBlocks.push_back(BB); DFS.PostBlocks.push_back(BB);
DFS.PostNumbers[BB] = DFS.PostBlocks.size(); DFS.PostNumbers[BB] = DFS.PostBlocks.size();
} }
//===--------------------------------------------------------------------
--
// Implement part of the std::set interface for the purpose of driving th
e
// generic po_iterator.
/// Return true if the block is outside the loop or has already been visi
ted.
/// Sorry if this is counterintuitive.
bool count(BasicBlock *BB) const {
return !DFS.L->contains(LI->getLoopFor(BB)) || DFS.PostNumbers.count(BB
);
}
/// If this block is contained in the loop and has not been visited, retu
rn
/// true and assign a preorder number. This is a proxy for visitPreorder
/// called by POIterator.
bool insert(BasicBlock *BB) {
return visitPreorder(BB);
}
}; };
/// Specialize DFSetTraits to record postorder numbers. inline bool po_iterator_storage<LoopBlocksTraversal, true>::
template<> struct DFSetTraits<LoopBlocksTraversal> { insertEdge(BasicBlock *From, BasicBlock *To) {
static void finishPostorder(BasicBlock *BB, LoopBlocksTraversal& LBT) { return LBT.visitPreorder(To);
LBT.finishPostorder(BB); }
}
}; inline void po_iterator_storage<LoopBlocksTraversal, true>::
finishPostorder(BasicBlock *BB) {
LBT.finishPostorder(BB);
}
} // End namespace llvm } // End namespace llvm
#endif #endif
 End of changes. 3 change blocks. 
28 lines changed or deleted 19 lines changed or added


 MCAsmBackend.h   MCAsmBackend.h 
skipping to change at line 33 skipping to change at line 33
class MCFragment; class MCFragment;
class MCInst; class MCInst;
class MCInstFragment; class MCInstFragment;
class MCObjectWriter; class MCObjectWriter;
class MCSection; class MCSection;
class MCValue; class MCValue;
class raw_ostream; class raw_ostream;
/// MCAsmBackend - Generic interface to target specific assembler backends. /// MCAsmBackend - Generic interface to target specific assembler backends.
class MCAsmBackend { class MCAsmBackend {
MCAsmBackend(const MCAsmBackend &); // DO NOT IMPLEMENT MCAsmBackend(const MCAsmBackend &) LLVM_DELETED_FUNCTION;
void operator=(const MCAsmBackend &); // DO NOT IMPLEMENT void operator=(const MCAsmBackend &) LLVM_DELETED_FUNCTION;
protected: // Can only create subclasses. protected: // Can only create subclasses.
MCAsmBackend(); MCAsmBackend();
unsigned HasReliableSymbolDifference : 1; unsigned HasReliableSymbolDifference : 1;
unsigned HasDataInCodeSupport : 1;
public: public:
virtual ~MCAsmBackend(); virtual ~MCAsmBackend();
/// createObjectWriter - Create a new MCObjectWriter instance for use by the /// createObjectWriter - Create a new MCObjectWriter instance for use by the
/// assembler backend to emit the final object file. /// assembler backend to emit the final object file.
virtual MCObjectWriter *createObjectWriter(raw_ostream &OS) const = 0; virtual MCObjectWriter *createObjectWriter(raw_ostream &OS) const = 0;
/// createELFObjectTargetWriter - Create a new ELFObjectTargetWriter to e nable /// createELFObjectTargetWriter - Create a new ELFObjectTargetWriter to e nable
/// non-standard ELFObjectWriters. /// non-standard ELFObjectWriters.
skipping to change at line 68 skipping to change at line 69
/// reside in a different section. /// reside in a different section.
/// ///
/// This should always be true (since it results in fewer relocations wit h no /// This should always be true (since it results in fewer relocations wit h no
/// loss of functionality), but is currently supported as a way to mainta in /// loss of functionality), but is currently supported as a way to mainta in
/// exact object compatibility with Darwin 'as' (on non-x86_64). It shoul d /// exact object compatibility with Darwin 'as' (on non-x86_64). It shoul d
/// eventually should be eliminated. /// eventually should be eliminated.
bool hasReliableSymbolDifference() const { bool hasReliableSymbolDifference() const {
return HasReliableSymbolDifference; return HasReliableSymbolDifference;
} }
/// hasDataInCodeSupport - Check whether this target implements data-in-c
ode
/// markers. If not, data region directives will be ignored.
bool hasDataInCodeSupport() const {
return HasDataInCodeSupport;
}
/// doesSectionRequireSymbols - Check whether the given section requires that /// doesSectionRequireSymbols - Check whether the given section requires that
/// all symbols (even temporaries) have symbol table entries. /// all symbols (even temporaries) have symbol table entries.
virtual bool doesSectionRequireSymbols(const MCSection &Section) const { virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
return false; return false;
} }
/// isSectionAtomizable - Check whether the given section can be split in to /// isSectionAtomizable - Check whether the given section can be split in to
/// atoms. /// atoms.
/// ///
/// \see MCAssembler::isSymbolLinkerVisible(). /// \see MCAssembler::isSymbolLinkerVisible().
skipping to change at line 102 skipping to change at line 109
/// if necessary. IsResolved signals whether the caller believes a reloca tion /// if necessary. IsResolved signals whether the caller believes a reloca tion
/// is needed; the target can modify the value. The default does nothing. /// is needed; the target can modify the value. The default does nothing.
virtual void processFixupValue(const MCAssembler &Asm, virtual void processFixupValue(const MCAssembler &Asm,
const MCAsmLayout &Layout, const MCAsmLayout &Layout,
const MCFixup &Fixup, const MCFragment *DF , const MCFixup &Fixup, const MCFragment *DF ,
MCValue &Target, uint64_t &Value, MCValue &Target, uint64_t &Value,
bool &IsResolved) {} bool &IsResolved) {}
/// @} /// @}
/// applyFixup - Apply the \arg Value for given \arg Fixup into the provi ded /// applyFixup - Apply the \p Value for given \p Fixup into the provided
/// data fragment, at the offset specified by the fixup and following the /// data fragment, at the offset specified by the fixup and following the
/// fixup kind as appropriate. /// fixup kind as appropriate.
virtual void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSi ze, virtual void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSi ze,
uint64_t Value) const = 0; uint64_t Value) const = 0;
/// @} /// @}
/// @name Target Relaxation Interfaces /// @name Target Relaxation Interfaces
/// @{ /// @{
skipping to change at line 129 skipping to change at line 136
/// fixupNeedsRelaxation - Target specific predicate for whether a given /// fixupNeedsRelaxation - Target specific predicate for whether a given
/// fixup requires the associated instruction to be relaxed. /// fixup requires the associated instruction to be relaxed.
virtual bool fixupNeedsRelaxation(const MCFixup &Fixup, virtual bool fixupNeedsRelaxation(const MCFixup &Fixup,
uint64_t Value, uint64_t Value,
const MCInstFragment *DF, const MCInstFragment *DF,
const MCAsmLayout &Layout) const = 0; const MCAsmLayout &Layout) const = 0;
/// RelaxInstruction - Relax the instruction in the given fragment to the next /// RelaxInstruction - Relax the instruction in the given fragment to the next
/// wider instruction. /// wider instruction.
/// ///
/// \param Inst - The instruction to relax, which may be the same as the /// \param Inst The instruction to relax, which may be the same as the
/// output. /// output.
/// \parm Res [output] - On return, the relaxed instruction. /// \param [out] Res On return, the relaxed instruction.
virtual void relaxInstruction(const MCInst &Inst, MCInst &Res) const = 0; virtual void relaxInstruction(const MCInst &Inst, MCInst &Res) const = 0;
/// @} /// @}
/// getMinimumNopSize - Returns the minimum size of a nop in bytes on thi
s
/// target. The assembler will use this to emit excess padding in situati
ons
/// where the padding required for simple alignment would be less than th
e
/// minimum nop size.
///
virtual unsigned getMinimumNopSize() const { return 1; }
/// writeNopData - Write an (optimal) nop sequence of Count bytes to the given /// writeNopData - Write an (optimal) nop sequence of Count bytes to the given
/// output. If the target cannot generate such a sequence, it should retu rn an /// output. If the target cannot generate such a sequence, it should retu rn an
/// error. /// error.
/// ///
/// \return - True on success. /// \return - True on success.
virtual bool writeNopData(uint64_t Count, MCObjectWriter *OW) const = 0; virtual bool writeNopData(uint64_t Count, MCObjectWriter *OW) const = 0;
/// handleAssemblerFlag - Handle any target-specific assembler flags. /// handleAssemblerFlag - Handle any target-specific assembler flags.
/// By default, do nothing. /// By default, do nothing.
virtual void handleAssemblerFlag(MCAssemblerFlag Flag) {} virtual void handleAssemblerFlag(MCAssemblerFlag Flag) {}
 End of changes. 7 change blocks. 
5 lines changed or deleted 23 lines changed or added


 MCAsmInfo.h   MCAsmInfo.h 
skipping to change at line 36 skipping to change at line 36
class MCSection; class MCSection;
class MCStreamer; class MCStreamer;
class MCSymbol; class MCSymbol;
class MCContext; class MCContext;
namespace ExceptionHandling { namespace ExceptionHandling {
enum ExceptionsType { None, DwarfCFI, SjLj, ARM, Win64 }; enum ExceptionsType { None, DwarfCFI, SjLj, ARM, Win64 };
} }
namespace LCOMM { namespace LCOMM {
enum LCOMMType { None, NoAlignment, ByteAlignment }; enum LCOMMType { NoAlignment, ByteAlignment, Log2Alignment };
} }
/// MCAsmInfo - This class is intended to be used as a base class for asm /// MCAsmInfo - This class is intended to be used as a base class for asm
/// properties and features specific to the target. /// properties and features specific to the target.
class MCAsmInfo { class MCAsmInfo {
protected: protected:
//===------------------------------------------------------------------ ===// //===------------------------------------------------------------------ ===//
// Properties to be set by the target writer, used to configure asm pri nter. // Properties to be set by the target writer, used to configure asm pri nter.
// //
skipping to change at line 150 skipping to change at line 150
bool AllowNameToStartWithDigit; bool AllowNameToStartWithDigit;
/// AllowPeriodsInName - This is true if the assembler allows periods i n /// AllowPeriodsInName - This is true if the assembler allows periods i n
/// symbol names. This defaults to true. /// symbol names. This defaults to true.
bool AllowPeriodsInName; bool AllowPeriodsInName;
/// AllowUTF8 - This is true if the assembler accepts UTF-8 input. /// AllowUTF8 - This is true if the assembler accepts UTF-8 input.
// FIXME: Make this a more general encoding setting? // FIXME: Make this a more general encoding setting?
bool AllowUTF8; bool AllowUTF8;
/// UseDataRegionDirectives - This is true if data region markers shoul
d
/// be printed as ".data_region/.end_data_region" directives. If false,
/// use "$d/$a" labels instead.
bool UseDataRegionDirectives;
//===--- Data Emission Directives ------------------------------------- ===// //===--- Data Emission Directives ------------------------------------- ===//
/// ZeroDirective - this should be set to the directive used to get som e /// ZeroDirective - this should be set to the directive used to get som e
/// number of zero bytes emitted to the current section. Common cases are /// number of zero bytes emitted to the current section. Common cases are
/// "\t.zero\t" and "\t.space\t". If this is set to null, the /// "\t.zero\t" and "\t.space\t". If this is set to null, the
/// Data*bitsDirective's will be used to emit zero bytes. /// Data*bitsDirective's will be used to emit zero bytes.
const char *ZeroDirective; // Defaults to "\t.zero\t" const char *ZeroDirective; // Defaults to "\t.zero\t"
/// AsciiDirective - This directive allows emission of an ascii string with /// AsciiDirective - This directive allows emission of an ascii string with
/// the standard C escape characters embedded into it. /// the standard C escape characters embedded into it.
skipping to change at line 175 skipping to change at line 180
const char *AscizDirective; // Defaults to "\t.asciz\t" const char *AscizDirective; // Defaults to "\t.asciz\t"
/// DataDirectives - These directives are used to output some unit of /// DataDirectives - These directives are used to output some unit of
/// integer data to the current section. If a data directive is set to /// integer data to the current section. If a data directive is set to
/// null, smaller data directives will be used to emit the large sizes. /// null, smaller data directives will be used to emit the large sizes.
const char *Data8bitsDirective; // Defaults to "\t.byte\t" const char *Data8bitsDirective; // Defaults to "\t.byte\t"
const char *Data16bitsDirective; // Defaults to "\t.short\t" const char *Data16bitsDirective; // Defaults to "\t.short\t"
const char *Data32bitsDirective; // Defaults to "\t.long\t" const char *Data32bitsDirective; // Defaults to "\t.long\t"
const char *Data64bitsDirective; // Defaults to "\t.quad\t" const char *Data64bitsDirective; // Defaults to "\t.quad\t"
/// [Data|Code]Begin - These magic labels are used to marked a region a
s
/// data or code, and are used to provide additional information for
/// correct disassembly on targets that like to mix data and code withi
n
/// a segment. These labels will be implicitly suffixed by the streame
r
/// to give them unique names.
const char *DataBegin; // Defaults to "$d."
const char *CodeBegin; // Defaults to "$a."
const char *JT8Begin; // Defaults to "$a."
const char *JT16Begin; // Defaults to "$a."
const char *JT32Begin; // Defaults to "$a."
bool SupportsDataRegions;
/// GPRel64Directive - if non-null, a directive that is used to emit a word /// GPRel64Directive - if non-null, a directive that is used to emit a word
/// which should be relocated as a 64-bit GP-relative offset, e.g. .gpd word /// which should be relocated as a 64-bit GP-relative offset, e.g. .gpd word
/// on Mips. /// on Mips.
const char *GPRel64Directive; // Defaults to NULL. const char *GPRel64Directive; // Defaults to NULL.
/// GPRel32Directive - if non-null, a directive that is used to emit a word /// GPRel32Directive - if non-null, a directive that is used to emit a word
/// which should be relocated as a 32-bit GP-relative offset, e.g. .gpw ord /// which should be relocated as a 32-bit GP-relative offset, e.g. .gpw ord
/// on Mips or .gprel32 on Alpha. /// on Mips or .gprel32 on Alpha.
const char *GPRel32Directive; // Defaults to NULL. const char *GPRel32Directive; // Defaults to NULL.
skipping to change at line 257 skipping to change at line 250
/// HasSetDirective - True if the assembler supports the .set directive . /// HasSetDirective - True if the assembler supports the .set directive .
bool HasSetDirective; // Defaults to true. bool HasSetDirective; // Defaults to true.
/// HasAggressiveSymbolFolding - False if the assembler requires that w e use /// HasAggressiveSymbolFolding - False if the assembler requires that w e use
/// Lc = a - b /// Lc = a - b
/// .long Lc /// .long Lc
/// instead of /// instead of
/// .long a - b /// .long a - b
bool HasAggressiveSymbolFolding; // Defaults to true. bool HasAggressiveSymbolFolding; // Defaults to true.
/// LCOMMDirectiveType - Describes if the target supports the .lcomm /// COMMDirectiveAlignmentIsInBytes - True is .comm's and .lcomms optio
/// directive and whether it has an alignment parameter. nal
LCOMM::LCOMMType LCOMMDirectiveType; // Defaults to LCOMM::None.
/// COMMDirectiveAlignmentIsInBytes - True is COMMDirective's optional
/// alignment is to be specified in bytes instead of log2(n). /// alignment is to be specified in bytes instead of log2(n).
bool COMMDirectiveAlignmentIsInBytes; // Defaults to true; bool COMMDirectiveAlignmentIsInBytes; // Defaults to true;
/// LCOMMDirectiveAlignment - Describes if the .lcomm directive for the
/// target supports an alignment argument and how it is interpreted.
LCOMM::LCOMMType LCOMMDirectiveAlignmentType; // Defaults to NoAlignmen
t.
/// HasDotTypeDotSizeDirective - True if the target has .type and .size /// HasDotTypeDotSizeDirective - True if the target has .type and .size
/// directives, this is true for most ELF targets. /// directives, this is true for most ELF targets.
bool HasDotTypeDotSizeDirective; // Defaults to true. bool HasDotTypeDotSizeDirective; // Defaults to true.
/// HasSingleParameterDotFile - True if the target has a single paramet er /// HasSingleParameterDotFile - True if the target has a single paramet er
/// .file directive, this is true for ELF targets. /// .file directive, this is true for ELF targets.
bool HasSingleParameterDotFile; // Defaults to true. bool HasSingleParameterDotFile; // Defaults to true.
/// HasNoDeadStrip - True if this target supports the MachO .no_dead_st rip /// HasNoDeadStrip - True if this target supports the MachO .no_dead_st rip
/// directive. /// directive.
skipping to change at line 324 skipping to change at line 317
/// SupportsExceptionHandling - True if target supports exception handl ing. /// SupportsExceptionHandling - True if target supports exception handl ing.
ExceptionHandling::ExceptionsType ExceptionsType; // Defaults to None ExceptionHandling::ExceptionsType ExceptionsType; // Defaults to None
/// DwarfUsesInlineInfoSection - True if DwarfDebugInlineSection is use d to /// DwarfUsesInlineInfoSection - True if DwarfDebugInlineSection is use d to
/// encode inline subroutine information. /// encode inline subroutine information.
bool DwarfUsesInlineInfoSection; // Defaults to false. bool DwarfUsesInlineInfoSection; // Defaults to false.
/// DwarfSectionOffsetDirective - Special section offset directive. /// DwarfSectionOffsetDirective - Special section offset directive.
const char* DwarfSectionOffsetDirective; // Defaults to NULL const char* DwarfSectionOffsetDirective; // Defaults to NULL
/// DwarfRequiresRelocationForSectionOffset - True if we need to produc /// DwarfUsesRelocationsAcrossSections - True if Dwarf2 output generall
e a y
/// relocation when we want a section offset in dwarf. /// uses relocations for references to other .debug_* sections.
bool DwarfRequiresRelocationForSectionOffset; // Defaults to true; bool DwarfUsesRelocationsAcrossSections;
/// DwarfUsesLabelOffsetDifference - True if Dwarf2 output can
/// use EmitLabelOffsetDifference.
bool DwarfUsesLabelOffsetForRanges;
/// DwarfUsesRelocationsForStringPool - True if this Dwarf output must
use
/// relocations to refer to entries in the string pool.
bool DwarfUsesRelocationsForStringPool;
/// DwarfRegNumForCFI - True if dwarf register numbers are printed /// DwarfRegNumForCFI - True if dwarf register numbers are printed
/// instead of symbolic register names in .cfi_* directives. /// instead of symbolic register names in .cfi_* directives.
bool DwarfRegNumForCFI; // Defaults to false; bool DwarfRegNumForCFI; // Defaults to false;
//===--- CBE Asm Translation Table -----------------------------------=
==//
const char *const *AsmTransCBE; // Defaults to empty
//===--- Prologue State ----------------------------------------------= ==// //===--- Prologue State ----------------------------------------------= ==//
std::vector<MachineMove> InitialFrameState; std::vector<MachineMove> InitialFrameState;
public: public:
explicit MCAsmInfo(); explicit MCAsmInfo();
virtual ~MCAsmInfo(); virtual ~MCAsmInfo();
// FIXME: move these methods to DwarfPrinter when the JIT stops using t hem. // FIXME: move these methods to DwarfPrinter when the JIT stops using t hem.
static unsigned getSLEB128Size(int Value); static unsigned getSLEB128Size(int Value);
skipping to change at line 390 skipping to change at line 371
} }
const char *getData32bitsDirective(unsigned AS = 0) const { const char *getData32bitsDirective(unsigned AS = 0) const {
return AS == 0 ? Data32bitsDirective : getDataASDirective(32, AS); return AS == 0 ? Data32bitsDirective : getDataASDirective(32, AS);
} }
const char *getData64bitsDirective(unsigned AS = 0) const { const char *getData64bitsDirective(unsigned AS = 0) const {
return AS == 0 ? Data64bitsDirective : getDataASDirective(64, AS); return AS == 0 ? Data64bitsDirective : getDataASDirective(64, AS);
} }
const char *getGPRel64Directive() const { return GPRel64Directive; } const char *getGPRel64Directive() const { return GPRel64Directive; }
const char *getGPRel32Directive() const { return GPRel32Directive; } const char *getGPRel32Directive() const { return GPRel32Directive; }
/// [Code|Data]Begin label name accessors.
const char *getCodeBeginLabelName() const { return CodeBegin; }
const char *getDataBeginLabelName() const { return DataBegin; }
const char *getJumpTable8BeginLabelName() const { return JT8Begin; }
const char *getJumpTable16BeginLabelName() const { return JT16Begin; }
const char *getJumpTable32BeginLabelName() const { return JT32Begin; }
bool getSupportsDataRegions() const { return SupportsDataRegions; }
/// getNonexecutableStackSection - Targets can implement this method to /// getNonexecutableStackSection - Targets can implement this method to
/// specify a section to switch to if the translation unit doesn't have any /// specify a section to switch to if the translation unit doesn't have any
/// trampolines that require an executable stack. /// trampolines that require an executable stack.
virtual const MCSection *getNonexecutableStackSection(MCContext &Ctx) c onst{ virtual const MCSection *getNonexecutableStackSection(MCContext &Ctx) c onst{
return 0; return 0;
} }
virtual const MCExpr * virtual const MCExpr *
getExprForPersonalitySymbol(const MCSymbol *Sym, getExprForPersonalitySymbol(const MCSymbol *Sym,
unsigned Encoding, unsigned Encoding,
skipping to change at line 494 skipping to change at line 467
} }
bool doesAllowNameToStartWithDigit() const { bool doesAllowNameToStartWithDigit() const {
return AllowNameToStartWithDigit; return AllowNameToStartWithDigit;
} }
bool doesAllowPeriodsInName() const { bool doesAllowPeriodsInName() const {
return AllowPeriodsInName; return AllowPeriodsInName;
} }
bool doesAllowUTF8() const { bool doesAllowUTF8() const {
return AllowUTF8; return AllowUTF8;
} }
bool doesSupportDataRegionDirectives() const {
return UseDataRegionDirectives;
}
const char *getZeroDirective() const { const char *getZeroDirective() const {
return ZeroDirective; return ZeroDirective;
} }
const char *getAsciiDirective() const { const char *getAsciiDirective() const {
return AsciiDirective; return AsciiDirective;
} }
const char *getAscizDirective() const { const char *getAscizDirective() const {
return AscizDirective; return AscizDirective;
} }
const char *getAlignDirective() const { const char *getAlignDirective() const {
skipping to change at line 522 skipping to change at line 498
const char *getGlobalDirective() const { const char *getGlobalDirective() const {
return GlobalDirective; return GlobalDirective;
} }
const char *getExternDirective() const { const char *getExternDirective() const {
return ExternDirective; return ExternDirective;
} }
bool hasSetDirective() const { return HasSetDirective; } bool hasSetDirective() const { return HasSetDirective; }
bool hasAggressiveSymbolFolding() const { bool hasAggressiveSymbolFolding() const {
return HasAggressiveSymbolFolding; return HasAggressiveSymbolFolding;
} }
LCOMM::LCOMMType getLCOMMDirectiveType() const {
return LCOMMDirectiveType;
}
bool hasDotTypeDotSizeDirective() const {return HasDotTypeDotSizeDirect
ive;}
bool getCOMMDirectiveAlignmentIsInBytes() const { bool getCOMMDirectiveAlignmentIsInBytes() const {
return COMMDirectiveAlignmentIsInBytes; return COMMDirectiveAlignmentIsInBytes;
} }
LCOMM::LCOMMType getLCOMMDirectiveAlignmentType() const {
return LCOMMDirectiveAlignmentType;
}
bool hasDotTypeDotSizeDirective() const {return HasDotTypeDotSizeDirect
ive;}
bool hasSingleParameterDotFile() const { return HasSingleParameterDotFi le; } bool hasSingleParameterDotFile() const { return HasSingleParameterDotFi le; }
bool hasNoDeadStrip() const { return HasNoDeadStrip; } bool hasNoDeadStrip() const { return HasNoDeadStrip; }
bool hasSymbolResolver() const { return HasSymbolResolver; } bool hasSymbolResolver() const { return HasSymbolResolver; }
const char *getWeakRefDirective() const { return WeakRefDirective; } const char *getWeakRefDirective() const { return WeakRefDirective; }
const char *getWeakDefDirective() const { return WeakDefDirective; } const char *getWeakDefDirective() const { return WeakDefDirective; }
const char *getLinkOnceDirective() const { return LinkOnceDirective; } const char *getLinkOnceDirective() const { return LinkOnceDirective; }
MCSymbolAttr getHiddenVisibilityAttr() const { return HiddenVisibilityA ttr;} MCSymbolAttr getHiddenVisibilityAttr() const { return HiddenVisibilityA ttr;}
MCSymbolAttr getHiddenDeclarationVisibilityAttr() const { MCSymbolAttr getHiddenDeclarationVisibilityAttr() const {
return HiddenDeclarationVisibilityAttr; return HiddenDeclarationVisibilityAttr;
skipping to change at line 567 skipping to change at line 543
(ExceptionsType == ExceptionHandling::DwarfCFI || (ExceptionsType == ExceptionHandling::DwarfCFI ||
ExceptionsType == ExceptionHandling::ARM || ExceptionsType == ExceptionHandling::ARM ||
ExceptionsType == ExceptionHandling::Win64); ExceptionsType == ExceptionHandling::Win64);
} }
bool doesDwarfUseInlineInfoSection() const { bool doesDwarfUseInlineInfoSection() const {
return DwarfUsesInlineInfoSection; return DwarfUsesInlineInfoSection;
} }
const char *getDwarfSectionOffsetDirective() const { const char *getDwarfSectionOffsetDirective() const {
return DwarfSectionOffsetDirective; return DwarfSectionOffsetDirective;
} }
bool doesDwarfRequireRelocationForSectionOffset() const { bool doesDwarfUseRelocationsAcrossSections() const {
return DwarfRequiresRelocationForSectionOffset; return DwarfUsesRelocationsAcrossSections;
}
bool doesDwarfUseLabelOffsetForRanges() const {
return DwarfUsesLabelOffsetForRanges;
}
bool doesDwarfUseRelocationsForStringPool() const {
return DwarfUsesRelocationsForStringPool;
} }
bool useDwarfRegNumForCFI() const { bool useDwarfRegNumForCFI() const {
return DwarfRegNumForCFI; return DwarfRegNumForCFI;
} }
const char *const *getAsmCBE() const {
return AsmTransCBE;
}
void addInitialFrameState(MCSymbol *label, const MachineLocation &D, void addInitialFrameState(MCSymbol *label, const MachineLocation &D,
const MachineLocation &S) { const MachineLocation &S) {
InitialFrameState.push_back(MachineMove(label, D, S)); InitialFrameState.push_back(MachineMove(label, D, S));
} }
const std::vector<MachineMove> &getInitialFrameState() const { const std::vector<MachineMove> &getInitialFrameState() const {
return InitialFrameState; return InitialFrameState;
} }
}; };
} }
 End of changes. 13 change blocks. 
63 lines changed or deleted 28 lines changed or added


 MCAsmLexer.h   MCAsmLexer.h 
skipping to change at line 14 skipping to change at line 14
// //
// This file is distributed under the University of Illinois Open Source // This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details. // License. See LICENSE.TXT for details.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_MC_MCASMLEXER_H #ifndef LLVM_MC_MCASMLEXER_H
#define LLVM_MC_MCASMLEXER_H #define LLVM_MC_MCASMLEXER_H
#include "llvm/ADT/StringRef.h" #include "llvm/ADT/StringRef.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/DataTypes.h" #include "llvm/Support/DataTypes.h"
#include "llvm/Support/SMLoc.h" #include "llvm/Support/SMLoc.h"
namespace llvm { namespace llvm {
/// AsmToken - Target independent representation for an assembler token. /// AsmToken - Target independent representation for an assembler token.
class AsmToken { class AsmToken {
public: public:
enum TokenKind { enum TokenKind {
// Markers // Markers
skipping to change at line 42 skipping to change at line 43
// Real values. // Real values.
Real, Real,
// Register values (stored in IntVal). Only used by MCTargetAsmLexer. // Register values (stored in IntVal). Only used by MCTargetAsmLexer.
Register, Register,
// No-value. // No-value.
EndOfStatement, EndOfStatement,
Colon, Colon,
Space,
Plus, Minus, Tilde, Plus, Minus, Tilde,
Slash, // '/' Slash, // '/'
BackSlash, // '\' BackSlash, // '\'
LParen, RParen, LBrac, RBrac, LCurly, RCurly, LParen, RParen, LBrac, RBrac, LCurly, RCurly,
Star, Dot, Comma, Dollar, Equal, EqualEqual, Star, Dot, Comma, Dollar, Equal, EqualEqual,
Pipe, PipePipe, Caret, Pipe, PipePipe, Caret,
Amp, AmpAmp, Exclaim, ExclaimEqual, Percent, Hash, Amp, AmpAmp, Exclaim, ExclaimEqual, Percent, Hash,
Less, LessEqual, LessLess, LessGreater, Less, LessEqual, LessLess, LessGreater,
Greater, GreaterEqual, GreaterGreater, At Greater, GreaterEqual, GreaterGreater, At
skipping to change at line 124 skipping to change at line 126
/// MCAsmLexer - Generic assembler lexer interface, for use by target speci fic /// MCAsmLexer - Generic assembler lexer interface, for use by target speci fic
/// assembly lexers. /// assembly lexers.
class MCAsmLexer { class MCAsmLexer {
/// The current token, stored in the base class for faster access. /// The current token, stored in the base class for faster access.
AsmToken CurTok; AsmToken CurTok;
/// The location and description of the current error /// The location and description of the current error
SMLoc ErrLoc; SMLoc ErrLoc;
std::string Err; std::string Err;
MCAsmLexer(const MCAsmLexer &); // DO NOT IMPLEMENT MCAsmLexer(const MCAsmLexer &) LLVM_DELETED_FUNCTION;
void operator=(const MCAsmLexer &); // DO NOT IMPLEMENT void operator=(const MCAsmLexer &) LLVM_DELETED_FUNCTION;
protected: // Can only create subclasses. protected: // Can only create subclasses.
const char *TokStart; const char *TokStart;
bool SkipSpace;
MCAsmLexer(); MCAsmLexer();
virtual AsmToken LexToken() = 0; virtual AsmToken LexToken() = 0;
void SetError(const SMLoc &errLoc, const std::string &err) { void SetError(const SMLoc &errLoc, const std::string &err) {
ErrLoc = errLoc; ErrLoc = errLoc;
Err = err; Err = err;
} }
skipping to change at line 172 skipping to change at line 175
} }
/// getErr - Get the current error string /// getErr - Get the current error string
const std::string &getErr() { const std::string &getErr() {
return Err; return Err;
} }
/// getKind - Get the kind of current token. /// getKind - Get the kind of current token.
AsmToken::TokenKind getKind() const { return CurTok.getKind(); } AsmToken::TokenKind getKind() const { return CurTok.getKind(); }
/// is - Check if the current token has kind \arg K. /// is - Check if the current token has kind \p K.
bool is(AsmToken::TokenKind K) const { return CurTok.is(K); } bool is(AsmToken::TokenKind K) const { return CurTok.is(K); }
/// isNot - Check if the current token has kind \arg K. /// isNot - Check if the current token has kind \p K.
bool isNot(AsmToken::TokenKind K) const { return CurTok.isNot(K); } bool isNot(AsmToken::TokenKind K) const { return CurTok.isNot(K); }
/// setSkipSpace - Set whether spaces should be ignored by the lexer
void setSkipSpace(bool val) { SkipSpace = val; }
}; };
} // End llvm namespace } // End llvm namespace
#endif #endif
 End of changes. 7 change blocks. 
4 lines changed or deleted 10 lines changed or added


 MCAsmParser.h   MCAsmParser.h 
skipping to change at line 23 skipping to change at line 23
#include "llvm/Support/DataTypes.h" #include "llvm/Support/DataTypes.h"
#include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/ArrayRef.h"
namespace llvm { namespace llvm {
class AsmToken; class AsmToken;
class MCAsmInfo; class MCAsmInfo;
class MCAsmLexer; class MCAsmLexer;
class MCAsmParserExtension; class MCAsmParserExtension;
class MCContext; class MCContext;
class MCExpr; class MCExpr;
class MCInstPrinter;
class MCInstrInfo;
class MCParsedAsmOperand;
class MCStreamer; class MCStreamer;
class MCTargetAsmParser; class MCTargetAsmParser;
class SMLoc; class SMLoc;
class SMRange; class SMRange;
class SourceMgr; class SourceMgr;
class StringRef; class StringRef;
class Twine; class Twine;
/// MCAsmParserSemaCallback - Generic Sema callback for assembly parser.
class MCAsmParserSemaCallback {
public:
virtual ~MCAsmParserSemaCallback();
virtual void *LookupInlineAsmIdentifier(StringRef Name, void *Loc,
unsigned &Size) = 0;
virtual bool LookupInlineAsmField(StringRef Base, StringRef Member,
unsigned &Offset) = 0;
};
/// MCAsmParser - Generic assembler parser interface, for use by target spe cific /// MCAsmParser - Generic assembler parser interface, for use by target spe cific
/// assembly parsers. /// assembly parsers.
class MCAsmParser { class MCAsmParser {
public: public:
typedef bool (*DirectiveHandler)(MCAsmParserExtension*, StringRef, SMLoc) ; typedef bool (*DirectiveHandler)(MCAsmParserExtension*, StringRef, SMLoc) ;
private: private:
MCAsmParser(const MCAsmParser &); // DO NOT IMPLEMENT MCAsmParser(const MCAsmParser &) LLVM_DELETED_FUNCTION;
void operator=(const MCAsmParser &); // DO NOT IMPLEMENT void operator=(const MCAsmParser &) LLVM_DELETED_FUNCTION;
MCTargetAsmParser *TargetParser; MCTargetAsmParser *TargetParser;
unsigned ShowParsedOperands : 1; unsigned ShowParsedOperands : 1;
protected: // Can only create subclasses. protected: // Can only create subclasses.
MCAsmParser(); MCAsmParser();
public: public:
virtual ~MCAsmParser(); virtual ~MCAsmParser();
skipping to change at line 76 skipping to change at line 89
virtual unsigned getAssemblerDialect() { return 0;} virtual unsigned getAssemblerDialect() { return 0;}
virtual void setAssemblerDialect(unsigned i) { } virtual void setAssemblerDialect(unsigned i) { }
bool getShowParsedOperands() const { return ShowParsedOperands; } bool getShowParsedOperands() const { return ShowParsedOperands; }
void setShowParsedOperands(bool Value) { ShowParsedOperands = Value; } void setShowParsedOperands(bool Value) { ShowParsedOperands = Value; }
/// Run - Run the parser on the input source buffer. /// Run - Run the parser on the input source buffer.
virtual bool Run(bool NoInitialTextSection, bool NoFinalize = false) = 0; virtual bool Run(bool NoInitialTextSection, bool NoFinalize = false) = 0;
/// Warning - Emit a warning at the location \arg L, with the message \ar virtual void setParsingInlineAsm(bool V) = 0;
g virtual bool isParsingInlineAsm() = 0;
/// Msg.
/// ParseMSInlineAsm - Parse ms-style inline assembly.
virtual bool ParseMSInlineAsm(void *AsmLoc, std::string &AsmString,
unsigned &NumOutputs, unsigned &NumInputs,
SmallVectorImpl<std::pair<void *, bool> > &
OpDecls,
SmallVectorImpl<std::string> &Constraints,
SmallVectorImpl<std::string> &Clobbers,
const MCInstrInfo *MII,
const MCInstPrinter *IP,
MCAsmParserSemaCallback &SI) = 0;
/// Warning - Emit a warning at the location \p L, with the message \p Ms
g.
/// ///
/// \return The return value is true, if warnings are fatal. /// \return The return value is true, if warnings are fatal.
virtual bool Warning(SMLoc L, const Twine &Msg, virtual bool Warning(SMLoc L, const Twine &Msg,
ArrayRef<SMRange> Ranges = ArrayRef<SMRange>()) = 0; ArrayRef<SMRange> Ranges = ArrayRef<SMRange>()) = 0;
/// Error - Emit an error at the location \arg L, with the message \arg /// Error - Emit an error at the location \p L, with the message \p Msg.
/// Msg.
/// ///
/// \return The return value is always true, as an idiomatic convenience to /// \return The return value is always true, as an idiomatic convenience to
/// clients. /// clients.
virtual bool Error(SMLoc L, const Twine &Msg, virtual bool Error(SMLoc L, const Twine &Msg,
ArrayRef<SMRange> Ranges = ArrayRef<SMRange>()) = 0; ArrayRef<SMRange> Ranges = ArrayRef<SMRange>()) = 0;
/// Lex - Get the next AsmToken in the stream, possibly handling file /// Lex - Get the next AsmToken in the stream, possibly handling file
/// inclusion first. /// inclusion first.
virtual const AsmToken &Lex() = 0; virtual const AsmToken &Lex() = 0;
/// getTok - Get the current AsmToken from the stream. /// getTok - Get the current AsmToken from the stream.
const AsmToken &getTok(); const AsmToken &getTok();
/// \brief Report an error at the current lexer location. /// \brief Report an error at the current lexer location.
bool TokError(const Twine &Msg, bool TokError(const Twine &Msg,
ArrayRef<SMRange> Ranges = ArrayRef<SMRange>()); ArrayRef<SMRange> Ranges = ArrayRef<SMRange>());
/// ParseIdentifier - Parse an identifier or string (as a quoted identifi er) /// ParseIdentifier - Parse an identifier or string (as a quoted identifi er)
/// and set \arg Res to the identifier contents. /// and set \p Res to the identifier contents.
virtual bool ParseIdentifier(StringRef &Res) = 0; virtual bool ParseIdentifier(StringRef &Res) = 0;
/// \brief Parse up to the end of statement and return the contents from the /// \brief Parse up to the end of statement and return the contents from the
/// current token until the end of the statement; the current token on ex it /// current token until the end of the statement; the current token on ex it
/// will be either the EndOfStatement or EOF. /// will be either the EndOfStatement or EOF.
virtual StringRef ParseStringToEndOfStatement() = 0; virtual StringRef ParseStringToEndOfStatement() = 0;
/// EatToEndOfStatement - Skip to the end of the current statement, for e rror /// EatToEndOfStatement - Skip to the end of the current statement, for e rror
/// recovery. /// recovery.
virtual void EatToEndOfStatement() = 0; virtual void EatToEndOfStatement() = 0;
 End of changes. 6 change blocks. 
8 lines changed or deleted 33 lines changed or added


 MCAsmParserExtension.h   MCAsmParserExtension.h 
skipping to change at line 24 skipping to change at line 24
#include "llvm/ADT/StringRef.h" #include "llvm/ADT/StringRef.h"
#include "llvm/Support/SMLoc.h" #include "llvm/Support/SMLoc.h"
namespace llvm { namespace llvm {
class Twine; class Twine;
/// \brief Generic interface for extending the MCAsmParser, /// \brief Generic interface for extending the MCAsmParser,
/// which is implemented by target and object file assembly parser /// which is implemented by target and object file assembly parser
/// implementations. /// implementations.
class MCAsmParserExtension { class MCAsmParserExtension {
MCAsmParserExtension(const MCAsmParserExtension &); // DO NOT IMPLEMENT MCAsmParserExtension(const MCAsmParserExtension &) LLVM_DELETED_FUNCTION;
void operator=(const MCAsmParserExtension &); // DO NOT IMPLEMENT void operator=(const MCAsmParserExtension &) LLVM_DELETED_FUNCTION;
MCAsmParser *Parser; MCAsmParser *Parser;
protected: protected:
MCAsmParserExtension(); MCAsmParserExtension();
// Helper template for implementing static dispatch functions. // Helper template for implementing static dispatch functions.
template<typename T, bool (T::*Handler)(StringRef, SMLoc)> template<typename T, bool (T::*Handler)(StringRef, SMLoc)>
static bool HandleDirective(MCAsmParserExtension *Target, static bool HandleDirective(MCAsmParserExtension *Target,
StringRef Directive, StringRef Directive,
SMLoc DirectiveLoc) { SMLoc DirectiveLoc) {
T *Obj = static_cast<T*>(Target); T *Obj = static_cast<T*>(Target);
return (Obj->*Handler)(Directive, DirectiveLoc); return (Obj->*Handler)(Directive, DirectiveLoc);
} }
bool BracketExpressionsSupported; bool BracketExpressionsSupported;
public: public:
virtual ~MCAsmParserExtension(); virtual ~MCAsmParserExtension();
/// \brief Initialize the extension for parsing using the given \arg /// \brief Initialize the extension for parsing using the given \p Parser
/// Parser. The extension should use the AsmParser interfaces to register .
its /// The extension should use the AsmParser interfaces to register its
/// parsing routines. /// parsing routines.
virtual void Initialize(MCAsmParser &Parser); virtual void Initialize(MCAsmParser &Parser);
/// @name MCAsmParser Proxy Interfaces /// @name MCAsmParser Proxy Interfaces
/// @{ /// @{
MCContext &getContext() { return getParser().getContext(); } MCContext &getContext() { return getParser().getContext(); }
MCAsmLexer &getLexer() { return getParser().getLexer(); } MCAsmLexer &getLexer() { return getParser().getLexer(); }
MCAsmParser &getParser() { return *Parser; } MCAsmParser &getParser() { return *Parser; }
SourceMgr &getSourceManager() { return getParser().getSourceManager(); } SourceMgr &getSourceManager() { return getParser().getSourceManager(); }
 End of changes. 2 change blocks. 
5 lines changed or deleted 5 lines changed or added


 MCAssembler.h   MCAssembler.h 
skipping to change at line 43 skipping to change at line 43
class MCSection; class MCSection;
class MCSectionData; class MCSectionData;
class MCSymbol; class MCSymbol;
class MCSymbolData; class MCSymbolData;
class MCValue; class MCValue;
class MCAsmBackend; class MCAsmBackend;
class MCFragment : public ilist_node<MCFragment> { class MCFragment : public ilist_node<MCFragment> {
friend class MCAsmLayout; friend class MCAsmLayout;
MCFragment(const MCFragment&); // DO NOT IMPLEMENT MCFragment(const MCFragment&) LLVM_DELETED_FUNCTION;
void operator=(const MCFragment&); // DO NOT IMPLEMENT void operator=(const MCFragment&) LLVM_DELETED_FUNCTION;
public: public:
enum FragmentType { enum FragmentType {
FT_Align, FT_Align,
FT_Data, FT_Data,
FT_Fill, FT_Fill,
FT_Inst, FT_Inst,
FT_Org, FT_Org,
FT_Dwarf, FT_Dwarf,
FT_DwarfFrame, FT_DwarfFrame,
skipping to change at line 102 skipping to change at line 102
MCSectionData *getParent() const { return Parent; } MCSectionData *getParent() const { return Parent; }
void setParent(MCSectionData *Value) { Parent = Value; } void setParent(MCSectionData *Value) { Parent = Value; }
MCSymbolData *getAtom() const { return Atom; } MCSymbolData *getAtom() const { return Atom; }
void setAtom(MCSymbolData *Value) { Atom = Value; } void setAtom(MCSymbolData *Value) { Atom = Value; }
unsigned getLayoutOrder() const { return LayoutOrder; } unsigned getLayoutOrder() const { return LayoutOrder; }
void setLayoutOrder(unsigned Value) { LayoutOrder = Value; } void setLayoutOrder(unsigned Value) { LayoutOrder = Value; }
static bool classof(const MCFragment *O) { return true; }
void dump(); void dump();
}; };
class MCDataFragment : public MCFragment { class MCDataFragment : public MCFragment {
virtual void anchor(); virtual void anchor();
SmallString<32> Contents; SmallString<32> Contents;
/// Fixups - The list of fixups in this fragment. /// Fixups - The list of fixups in this fragment.
std::vector<MCFixup> Fixups; std::vector<MCFixup> Fixups;
skipping to change at line 133 skipping to change at line 131
SmallString<32> &getContents() { return Contents; } SmallString<32> &getContents() { return Contents; }
const SmallString<32> &getContents() const { return Contents; } const SmallString<32> &getContents() const { return Contents; }
/// @} /// @}
/// @name Fixup Access /// @name Fixup Access
/// @{ /// @{
void addFixup(MCFixup Fixup) { void addFixup(MCFixup Fixup) {
// Enforce invariant that fixups are in offset order. // Enforce invariant that fixups are in offset order.
assert((Fixups.empty() || Fixup.getOffset() > Fixups.back().getOffset() ) && assert((Fixups.empty() || Fixup.getOffset() >= Fixups.back().getOffset( )) &&
"Fixups must be added in order!"); "Fixups must be added in order!");
Fixups.push_back(Fixup); Fixups.push_back(Fixup);
} }
std::vector<MCFixup> &getFixups() { return Fixups; } std::vector<MCFixup> &getFixups() { return Fixups; }
const std::vector<MCFixup> &getFixups() const { return Fixups; } const std::vector<MCFixup> &getFixups() const { return Fixups; }
fixup_iterator fixup_begin() { return Fixups.begin(); } fixup_iterator fixup_begin() { return Fixups.begin(); }
const_fixup_iterator fixup_begin() const { return Fixups.begin(); } const_fixup_iterator fixup_begin() const { return Fixups.begin(); }
fixup_iterator fixup_end() {return Fixups.end();} fixup_iterator fixup_end() {return Fixups.end();}
const_fixup_iterator fixup_end() const {return Fixups.end();} const_fixup_iterator fixup_end() const {return Fixups.end();}
size_t fixup_size() const { return Fixups.size(); } size_t fixup_size() const { return Fixups.size(); }
/// @} /// @}
static bool classof(const MCFragment *F) { static bool classof(const MCFragment *F) {
return F->getKind() == MCFragment::FT_Data; return F->getKind() == MCFragment::FT_Data;
} }
static bool classof(const MCDataFragment *) { return true; }
}; };
// FIXME: This current incarnation of MCInstFragment doesn't make much sens e, as // FIXME: This current incarnation of MCInstFragment doesn't make much sens e, as
// it is almost entirely a duplicate of MCDataFragment. If we decide to sti ck // it is almost entirely a duplicate of MCDataFragment. If we decide to sti ck
// with this approach (as opposed to making MCInstFragment a very light wei ght // with this approach (as opposed to making MCInstFragment a very light wei ght
// object with just the MCInst and a code size, then we should just change // object with just the MCInst and a code size, then we should just change
// MCDataFragment to have an optional MCInst at its end. // MCDataFragment to have an optional MCInst at its end.
class MCInstFragment : public MCFragment { class MCInstFragment : public MCFragment {
virtual void anchor(); virtual void anchor();
skipping to change at line 179 skipping to change at line 176
SmallString<8> Code; SmallString<8> Code;
/// Fixups - The list of fixups in this fragment. /// Fixups - The list of fixups in this fragment.
SmallVector<MCFixup, 1> Fixups; SmallVector<MCFixup, 1> Fixups;
public: public:
typedef SmallVectorImpl<MCFixup>::const_iterator const_fixup_iterator; typedef SmallVectorImpl<MCFixup>::const_iterator const_fixup_iterator;
typedef SmallVectorImpl<MCFixup>::iterator fixup_iterator; typedef SmallVectorImpl<MCFixup>::iterator fixup_iterator;
public: public:
MCInstFragment(MCInst _Inst, MCSectionData *SD = 0) MCInstFragment(const MCInst &_Inst, MCSectionData *SD = 0)
: MCFragment(FT_Inst, SD), Inst(_Inst) { : MCFragment(FT_Inst, SD), Inst(_Inst) {
} }
/// @name Accessors /// @name Accessors
/// @{ /// @{
SmallVectorImpl<char> &getCode() { return Code; } SmallVectorImpl<char> &getCode() { return Code; }
const SmallVectorImpl<char> &getCode() const { return Code; } const SmallVectorImpl<char> &getCode() const { return Code; }
unsigned getInstSize() const { return Code.size(); } unsigned getInstSize() const { return Code.size(); }
MCInst &getInst() { return Inst; } MCInst &getInst() { return Inst; }
const MCInst &getInst() const { return Inst; } const MCInst &getInst() const { return Inst; }
void setInst(MCInst Value) { Inst = Value; } void setInst(const MCInst& Value) { Inst = Value; }
/// @} /// @}
/// @name Fixup Access /// @name Fixup Access
/// @{ /// @{
SmallVectorImpl<MCFixup> &getFixups() { return Fixups; } SmallVectorImpl<MCFixup> &getFixups() { return Fixups; }
const SmallVectorImpl<MCFixup> &getFixups() const { return Fixups; } const SmallVectorImpl<MCFixup> &getFixups() const { return Fixups; }
fixup_iterator fixup_begin() { return Fixups.begin(); } fixup_iterator fixup_begin() { return Fixups.begin(); }
const_fixup_iterator fixup_begin() const { return Fixups.begin(); } const_fixup_iterator fixup_begin() const { return Fixups.begin(); }
skipping to change at line 216 skipping to change at line 213
fixup_iterator fixup_end() {return Fixups.end();} fixup_iterator fixup_end() {return Fixups.end();}
const_fixup_iterator fixup_end() const {return Fixups.end();} const_fixup_iterator fixup_end() const {return Fixups.end();}
size_t fixup_size() const { return Fixups.size(); } size_t fixup_size() const { return Fixups.size(); }
/// @} /// @}
static bool classof(const MCFragment *F) { static bool classof(const MCFragment *F) {
return F->getKind() == MCFragment::FT_Inst; return F->getKind() == MCFragment::FT_Inst;
} }
static bool classof(const MCInstFragment *) { return true; }
}; };
class MCAlignFragment : public MCFragment { class MCAlignFragment : public MCFragment {
virtual void anchor(); virtual void anchor();
/// Alignment - The alignment to ensure, in bytes. /// Alignment - The alignment to ensure, in bytes.
unsigned Alignment; unsigned Alignment;
/// Value - Value to use for filling padding bytes. /// Value - Value to use for filling padding bytes.
int64_t Value; int64_t Value;
/// ValueSize - The size of the integer (in bytes) of \arg Value. /// ValueSize - The size of the integer (in bytes) of \p Value.
unsigned ValueSize; unsigned ValueSize;
/// MaxBytesToEmit - The maximum number of bytes to emit; if the alignmen t /// MaxBytesToEmit - The maximum number of bytes to emit; if the alignmen t
/// cannot be satisfied in this width then this fragment is ignored. /// cannot be satisfied in this width then this fragment is ignored.
unsigned MaxBytesToEmit; unsigned MaxBytesToEmit;
/// EmitNops - Flag to indicate that (optimal) NOPs should be emitted ins tead /// EmitNops - Flag to indicate that (optimal) NOPs should be emitted ins tead
/// of using the provided value. The exact interpretation of this flag is /// of using the provided value. The exact interpretation of this flag is
/// target dependent. /// target dependent.
bool EmitNops : 1; bool EmitNops : 1;
skipping to change at line 266 skipping to change at line 262
unsigned getMaxBytesToEmit() const { return MaxBytesToEmit; } unsigned getMaxBytesToEmit() const { return MaxBytesToEmit; }
bool hasEmitNops() const { return EmitNops; } bool hasEmitNops() const { return EmitNops; }
void setEmitNops(bool Value) { EmitNops = Value; } void setEmitNops(bool Value) { EmitNops = Value; }
/// @} /// @}
static bool classof(const MCFragment *F) { static bool classof(const MCFragment *F) {
return F->getKind() == MCFragment::FT_Align; return F->getKind() == MCFragment::FT_Align;
} }
static bool classof(const MCAlignFragment *) { return true; }
}; };
class MCFillFragment : public MCFragment { class MCFillFragment : public MCFragment {
virtual void anchor(); virtual void anchor();
/// Value - Value to use for filling bytes. /// Value - Value to use for filling bytes.
int64_t Value; int64_t Value;
/// ValueSize - The size (in bytes) of \arg Value to use when filling, or 0 if /// ValueSize - The size (in bytes) of \p Value to use when filling, or 0 if
/// this is a virtual fill fragment. /// this is a virtual fill fragment.
unsigned ValueSize; unsigned ValueSize;
/// Size - The number of bytes to insert. /// Size - The number of bytes to insert.
uint64_t Size; uint64_t Size;
public: public:
MCFillFragment(int64_t _Value, unsigned _ValueSize, uint64_t _Size, MCFillFragment(int64_t _Value, unsigned _ValueSize, uint64_t _Size,
MCSectionData *SD = 0) MCSectionData *SD = 0)
: MCFragment(FT_Fill, SD), : MCFragment(FT_Fill, SD),
skipping to change at line 305 skipping to change at line 300
unsigned getValueSize() const { return ValueSize; } unsigned getValueSize() const { return ValueSize; }
uint64_t getSize() const { return Size; } uint64_t getSize() const { return Size; }
/// @} /// @}
static bool classof(const MCFragment *F) { static bool classof(const MCFragment *F) {
return F->getKind() == MCFragment::FT_Fill; return F->getKind() == MCFragment::FT_Fill;
} }
static bool classof(const MCFillFragment *) { return true; }
}; };
class MCOrgFragment : public MCFragment { class MCOrgFragment : public MCFragment {
virtual void anchor(); virtual void anchor();
/// Offset - The offset this fragment should start at. /// Offset - The offset this fragment should start at.
const MCExpr *Offset; const MCExpr *Offset;
/// Value - Value to use for filling bytes. /// Value - Value to use for filling bytes.
int8_t Value; int8_t Value;
skipping to change at line 334 skipping to change at line 328
const MCExpr &getOffset() const { return *Offset; } const MCExpr &getOffset() const { return *Offset; }
uint8_t getValue() const { return Value; } uint8_t getValue() const { return Value; }
/// @} /// @}
static bool classof(const MCFragment *F) { static bool classof(const MCFragment *F) {
return F->getKind() == MCFragment::FT_Org; return F->getKind() == MCFragment::FT_Org;
} }
static bool classof(const MCOrgFragment *) { return true; }
}; };
class MCLEBFragment : public MCFragment { class MCLEBFragment : public MCFragment {
virtual void anchor(); virtual void anchor();
/// Value - The value this fragment should contain. /// Value - The value this fragment should contain.
const MCExpr *Value; const MCExpr *Value;
/// IsSigned - True if this is a sleb128, false if uleb128. /// IsSigned - True if this is a sleb128, false if uleb128.
bool IsSigned; bool IsSigned;
skipping to change at line 367 skipping to change at line 360
bool isSigned() const { return IsSigned; } bool isSigned() const { return IsSigned; }
SmallString<8> &getContents() { return Contents; } SmallString<8> &getContents() { return Contents; }
const SmallString<8> &getContents() const { return Contents; } const SmallString<8> &getContents() const { return Contents; }
/// @} /// @}
static bool classof(const MCFragment *F) { static bool classof(const MCFragment *F) {
return F->getKind() == MCFragment::FT_LEB; return F->getKind() == MCFragment::FT_LEB;
} }
static bool classof(const MCLEBFragment *) { return true; }
}; };
class MCDwarfLineAddrFragment : public MCFragment { class MCDwarfLineAddrFragment : public MCFragment {
virtual void anchor(); virtual void anchor();
/// LineDelta - the value of the difference between the two line numbers /// LineDelta - the value of the difference between the two line numbers
/// between two .loc dwarf directives. /// between two .loc dwarf directives.
int64_t LineDelta; int64_t LineDelta;
/// AddrDelta - The expression for the difference of the two symbols that /// AddrDelta - The expression for the difference of the two symbols that
skipping to change at line 404 skipping to change at line 396
const MCExpr &getAddrDelta() const { return *AddrDelta; } const MCExpr &getAddrDelta() const { return *AddrDelta; }
SmallString<8> &getContents() { return Contents; } SmallString<8> &getContents() { return Contents; }
const SmallString<8> &getContents() const { return Contents; } const SmallString<8> &getContents() const { return Contents; }
/// @} /// @}
static bool classof(const MCFragment *F) { static bool classof(const MCFragment *F) {
return F->getKind() == MCFragment::FT_Dwarf; return F->getKind() == MCFragment::FT_Dwarf;
} }
static bool classof(const MCDwarfLineAddrFragment *) { return true; }
}; };
class MCDwarfCallFrameFragment : public MCFragment { class MCDwarfCallFrameFragment : public MCFragment {
virtual void anchor(); virtual void anchor();
/// AddrDelta - The expression for the difference of the two symbols that /// AddrDelta - The expression for the difference of the two symbols that
/// make up the address delta between two .cfi_* dwarf directives. /// make up the address delta between two .cfi_* dwarf directives.
const MCExpr *AddrDelta; const MCExpr *AddrDelta;
SmallString<8> Contents; SmallString<8> Contents;
skipping to change at line 434 skipping to change at line 425
const MCExpr &getAddrDelta() const { return *AddrDelta; } const MCExpr &getAddrDelta() const { return *AddrDelta; }
SmallString<8> &getContents() { return Contents; } SmallString<8> &getContents() { return Contents; }
const SmallString<8> &getContents() const { return Contents; } const SmallString<8> &getContents() const { return Contents; }
/// @} /// @}
static bool classof(const MCFragment *F) { static bool classof(const MCFragment *F) {
return F->getKind() == MCFragment::FT_DwarfFrame; return F->getKind() == MCFragment::FT_DwarfFrame;
} }
static bool classof(const MCDwarfCallFrameFragment *) { return true; }
}; };
// FIXME: Should this be a separate class, or just merged into MCSection? S ince // FIXME: Should this be a separate class, or just merged into MCSection? S ince
// we anticipate the fast path being through an MCAssembler, the only reaso n to // we anticipate the fast path being through an MCAssembler, the only reaso n to
// keep it out is for API abstraction. // keep it out is for API abstraction.
class MCSectionData : public ilist_node<MCSectionData> { class MCSectionData : public ilist_node<MCSectionData> {
friend class MCAsmLayout; friend class MCAsmLayout;
MCSectionData(const MCSectionData&); // DO NOT IMPLEMENT MCSectionData(const MCSectionData&) LLVM_DELETED_FUNCTION;
void operator=(const MCSectionData&); // DO NOT IMPLEMENT void operator=(const MCSectionData&) LLVM_DELETED_FUNCTION;
public: public:
typedef iplist<MCFragment> FragmentListType; typedef iplist<MCFragment> FragmentListType;
typedef FragmentListType::const_iterator const_iterator; typedef FragmentListType::const_iterator const_iterator;
typedef FragmentListType::iterator iterator; typedef FragmentListType::iterator iterator;
typedef FragmentListType::const_reverse_iterator const_reverse_iterator; typedef FragmentListType::const_reverse_iterator const_reverse_iterator;
typedef FragmentListType::reverse_iterator reverse_iterator; typedef FragmentListType::reverse_iterator reverse_iterator;
skipping to change at line 653 skipping to change at line 643
void dump(); void dump();
}; };
// FIXME: This really doesn't belong here. See comments below. // FIXME: This really doesn't belong here. See comments below.
struct IndirectSymbolData { struct IndirectSymbolData {
MCSymbol *Symbol; MCSymbol *Symbol;
MCSectionData *SectionData; MCSectionData *SectionData;
}; };
// FIXME: Ditto this. Purely so the Streamer and the ObjectWriter can talk
// to one another.
struct DataRegionData {
// This enum should be kept in sync w/ the mach-o definition in
// llvm/Object/MachOFormat.h.
enum KindTy { Data = 1, JumpTable8, JumpTable16, JumpTable32 } Kind;
MCSymbol *Start;
MCSymbol *End;
};
class MCAssembler { class MCAssembler {
friend class MCAsmLayout; friend class MCAsmLayout;
public: public:
typedef iplist<MCSectionData> SectionDataListType; typedef iplist<MCSectionData> SectionDataListType;
typedef iplist<MCSymbolData> SymbolDataListType; typedef iplist<MCSymbolData> SymbolDataListType;
typedef SectionDataListType::const_iterator const_iterator; typedef SectionDataListType::const_iterator const_iterator;
typedef SectionDataListType::iterator iterator; typedef SectionDataListType::iterator iterator;
typedef SymbolDataListType::const_iterator const_symbol_iterator; typedef SymbolDataListType::const_iterator const_symbol_iterator;
typedef SymbolDataListType::iterator symbol_iterator; typedef SymbolDataListType::iterator symbol_iterator;
typedef std::vector<IndirectSymbolData>::const_iterator typedef std::vector<IndirectSymbolData>::const_iterator
const_indirect_symbol_iterator; const_indirect_symbol_iterator;
typedef std::vector<IndirectSymbolData>::iterator indirect_symbol_iterato r; typedef std::vector<IndirectSymbolData>::iterator indirect_symbol_iterato r;
typedef std::vector<DataRegionData>::const_iterator
const_data_region_iterator;
typedef std::vector<DataRegionData>::iterator data_region_iterator;
private: private:
MCAssembler(const MCAssembler&); // DO NOT IMPLEMENT MCAssembler(const MCAssembler&) LLVM_DELETED_FUNCTION;
void operator=(const MCAssembler&); // DO NOT IMPLEMENT void operator=(const MCAssembler&) LLVM_DELETED_FUNCTION;
MCContext &Context; MCContext &Context;
MCAsmBackend &Backend; MCAsmBackend &Backend;
MCCodeEmitter &Emitter; MCCodeEmitter &Emitter;
MCObjectWriter &Writer; MCObjectWriter &Writer;
raw_ostream &OS; raw_ostream &OS;
skipping to change at line 700 skipping to change at line 704
// FIXME: Avoid this indirection? // FIXME: Avoid this indirection?
DenseMap<const MCSection*, MCSectionData*> SectionMap; DenseMap<const MCSection*, MCSectionData*> SectionMap;
/// The map of symbols to their associated assembler backend data. /// The map of symbols to their associated assembler backend data.
// //
// FIXME: Avoid this indirection? // FIXME: Avoid this indirection?
DenseMap<const MCSymbol*, MCSymbolData*> SymbolMap; DenseMap<const MCSymbol*, MCSymbolData*> SymbolMap;
std::vector<IndirectSymbolData> IndirectSymbols; std::vector<IndirectSymbolData> IndirectSymbols;
std::vector<DataRegionData> DataRegions;
/// The set of function symbols for which a .thumb_func directive has /// The set of function symbols for which a .thumb_func directive has
/// been seen. /// been seen.
// //
// FIXME: We really would like this in target specific code rather than // FIXME: We really would like this in target specific code rather than
// here. Maybe when the relocation stuff moves to target specific, // here. Maybe when the relocation stuff moves to target specific,
// this can go with it? The streamer would need some target specific // this can go with it? The streamer would need some target specific
// refactoring too. // refactoring too.
SmallPtrSet<const MCSymbol*, 64> ThumbFuncs; SmallPtrSet<const MCSymbol*, 64> ThumbFuncs;
unsigned RelaxAll : 1; unsigned RelaxAll : 1;
skipping to change at line 725 skipping to change at line 730
/// placed into the fixup. /// placed into the fixup.
/// ///
/// \param Layout The layout to use for evaluation. /// \param Layout The layout to use for evaluation.
/// \param Fixup The fixup to evaluate. /// \param Fixup The fixup to evaluate.
/// \param DF The fragment the fixup is inside. /// \param DF The fragment the fixup is inside.
/// \param Target [out] On return, the relocatable expression the fixup /// \param Target [out] On return, the relocatable expression the fixup
/// evaluates to. /// evaluates to.
/// \param Value [out] On return, the value of the fixup as currently lai d /// \param Value [out] On return, the value of the fixup as currently lai d
/// out. /// out.
/// \return Whether the fixup value was fully resolved. This is true if t he /// \return Whether the fixup value was fully resolved. This is true if t he
/// \arg Value result is fixed, otherwise the value may change due to /// \p Value result is fixed, otherwise the value may change due to
/// relocation. /// relocation.
bool evaluateFixup(const MCAsmLayout &Layout, bool evaluateFixup(const MCAsmLayout &Layout,
const MCFixup &Fixup, const MCFragment *DF, const MCFixup &Fixup, const MCFragment *DF,
MCValue &Target, uint64_t &Value) const; MCValue &Target, uint64_t &Value) const;
/// Check whether a fixup can be satisfied, or whether it needs to be rel axed /// Check whether a fixup can be satisfied, or whether it needs to be rel axed
/// (increased in size, in order to hold its value correctly). /// (increased in size, in order to hold its value correctly).
bool fixupNeedsRelaxation(const MCFixup &Fixup, const MCInstFragment *DF, bool fixupNeedsRelaxation(const MCFixup &Fixup, const MCInstFragment *DF,
const MCAsmLayout &Layout) const; const MCAsmLayout &Layout) const;
skipping to change at line 762 skipping to change at line 767
MCDwarfCallFrameFragment &DF); MCDwarfCallFrameFragment &DF);
/// finishLayout - Finalize a layout, including fragment lowering. /// finishLayout - Finalize a layout, including fragment lowering.
void finishLayout(MCAsmLayout &Layout); void finishLayout(MCAsmLayout &Layout);
uint64_t handleFixup(const MCAsmLayout &Layout, uint64_t handleFixup(const MCAsmLayout &Layout,
MCFragment &F, const MCFixup &Fixup); MCFragment &F, const MCFixup &Fixup);
public: public:
/// Compute the effective fragment size assuming it is laid out at the gi ven /// Compute the effective fragment size assuming it is laid out at the gi ven
/// \arg SectionAddress and \arg FragmentOffset. /// \p SectionAddress and \p FragmentOffset.
uint64_t computeFragmentSize(const MCAsmLayout &Layout, uint64_t computeFragmentSize(const MCAsmLayout &Layout,
const MCFragment &F) const; const MCFragment &F) const;
/// Find the symbol which defines the atom containing the given symbol, o r /// Find the symbol which defines the atom containing the given symbol, o r
/// null if there is no such symbol. /// null if there is no such symbol.
const MCSymbolData *getAtom(const MCSymbolData *Symbol) const; const MCSymbolData *getAtom(const MCSymbolData *Symbol) const;
/// Check whether a particular symbol is visible to the linker and is req uired /// Check whether a particular symbol is visible to the linker and is req uired
/// in the symbol table, or whether it can be discarded by the assembler. This /// in the symbol table, or whether it can be discarded by the assembler. This
/// also effects whether the assembler treats the label as potentially /// also effects whether the assembler treats the label as potentially
skipping to change at line 791 skipping to change at line 796
bool isThumbFunc(const MCSymbol *Func) const { bool isThumbFunc(const MCSymbol *Func) const {
return ThumbFuncs.count(Func); return ThumbFuncs.count(Func);
} }
/// Flag a function symbol as the target of a .thumb_func directive. /// Flag a function symbol as the target of a .thumb_func directive.
void setIsThumbFunc(const MCSymbol *Func) { ThumbFuncs.insert(Func); } void setIsThumbFunc(const MCSymbol *Func) { ThumbFuncs.insert(Func); }
public: public:
/// Construct a new assembler instance. /// Construct a new assembler instance.
/// ///
/// \arg OS - The stream to output to. /// \param OS The stream to output to.
// //
// FIXME: How are we going to parameterize this? Two obvious options are stay // FIXME: How are we going to parameterize this? Two obvious options are stay
// concrete and require clients to pass in a target like object. The othe r // concrete and require clients to pass in a target like object. The othe r
// option is to make this abstract, and have targets provide concrete // option is to make this abstract, and have targets provide concrete
// implementations as we do with AsmParser. // implementations as we do with AsmParser.
MCAssembler(MCContext &Context_, MCAsmBackend &Backend_, MCAssembler(MCContext &Context_, MCAsmBackend &Backend_,
MCCodeEmitter &Emitter_, MCObjectWriter &Writer_, MCCodeEmitter &Emitter_, MCObjectWriter &Writer_,
raw_ostream &OS); raw_ostream &OS);
~MCAssembler(); ~MCAssembler();
MCContext &getContext() const { return Context; } MCContext &getContext() const { return Context; }
MCAsmBackend &getBackend() const { return Backend; } MCAsmBackend &getBackend() const { return Backend; }
MCCodeEmitter &getEmitter() const { return Emitter; } MCCodeEmitter &getEmitter() const { return Emitter; }
MCObjectWriter &getWriter() const { return Writer; } MCObjectWriter &getWriter() const { return Writer; }
/// Finish - Do final processing and write the object to the output strea m. /// Finish - Do final processing and write the object to the output strea m.
/// \arg Writer is used for custom object writer (as the MCJIT does), /// \p Writer is used for custom object writer (as the MCJIT does),
/// if not specified it is automatically created from backend. /// if not specified it is automatically created from backend.
void Finish(); void Finish();
// FIXME: This does not belong here. // FIXME: This does not belong here.
bool getSubsectionsViaSymbols() const { bool getSubsectionsViaSymbols() const {
return SubsectionsViaSymbols; return SubsectionsViaSymbols;
} }
void setSubsectionsViaSymbols(bool Value) { void setSubsectionsViaSymbols(bool Value) {
SubsectionsViaSymbols = Value; SubsectionsViaSymbols = Value;
} }
skipping to change at line 886 skipping to change at line 891
indirect_symbol_iterator indirect_symbol_end() { indirect_symbol_iterator indirect_symbol_end() {
return IndirectSymbols.end(); return IndirectSymbols.end();
} }
const_indirect_symbol_iterator indirect_symbol_end() const { const_indirect_symbol_iterator indirect_symbol_end() const {
return IndirectSymbols.end(); return IndirectSymbols.end();
} }
size_t indirect_symbol_size() const { return IndirectSymbols.size(); } size_t indirect_symbol_size() const { return IndirectSymbols.size(); }
/// @} /// @}
/// @name Data Region List Access
/// @{
// FIXME: This is a total hack, this should not be here. Once things are
// factored so that the streamer has direct access to the .o writer, it c
an
// disappear.
std::vector<DataRegionData> &getDataRegions() {
return DataRegions;
}
data_region_iterator data_region_begin() {
return DataRegions.begin();
}
const_data_region_iterator data_region_begin() const {
return DataRegions.begin();
}
data_region_iterator data_region_end() {
return DataRegions.end();
}
const_data_region_iterator data_region_end() const {
return DataRegions.end();
}
size_t data_region_size() const { return DataRegions.size(); }
/// @}
/// @name Backend Data Access /// @name Backend Data Access
/// @{ /// @{
MCSectionData &getSectionData(const MCSection &Section) const { MCSectionData &getSectionData(const MCSection &Section) const {
MCSectionData *Entry = SectionMap.lookup(&Section); MCSectionData *Entry = SectionMap.lookup(&Section);
assert(Entry && "Missing section data!"); assert(Entry && "Missing section data!");
return *Entry; return *Entry;
} }
MCSectionData &getOrCreateSectionData(const MCSection &Section, MCSectionData &getOrCreateSectionData(const MCSection &Section,
 End of changes. 25 change blocks. 
25 lines changed or deleted 58 lines changed or added


 MCCodeEmitter.h   MCCodeEmitter.h 
skipping to change at line 13 skipping to change at line 13
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
// //
// This file is distributed under the University of Illinois Open Source // This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details. // License. See LICENSE.TXT for details.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_MC_MCCODEEMITTER_H #ifndef LLVM_MC_MCCODEEMITTER_H
#define LLVM_MC_MCCODEEMITTER_H #define LLVM_MC_MCCODEEMITTER_H
#include "llvm/Support/Compiler.h"
namespace llvm { namespace llvm {
class MCFixup; class MCFixup;
class MCInst; class MCInst;
class raw_ostream; class raw_ostream;
template<typename T> class SmallVectorImpl; template<typename T> class SmallVectorImpl;
/// MCCodeEmitter - Generic instruction encoding interface. /// MCCodeEmitter - Generic instruction encoding interface.
class MCCodeEmitter { class MCCodeEmitter {
private: private:
MCCodeEmitter(const MCCodeEmitter &); // DO NOT IMPLEMENT MCCodeEmitter(const MCCodeEmitter &) LLVM_DELETED_FUNCTION;
void operator=(const MCCodeEmitter &); // DO NOT IMPLEMENT void operator=(const MCCodeEmitter &) LLVM_DELETED_FUNCTION;
protected: // Can only create subclasses. protected: // Can only create subclasses.
MCCodeEmitter(); MCCodeEmitter();
public: public:
virtual ~MCCodeEmitter(); virtual ~MCCodeEmitter();
/// EncodeInstruction - Encode the given \arg Inst to bytes on the output /// EncodeInstruction - Encode the given \p Inst to bytes on the output
/// stream \arg OS. /// stream \p OS.
virtual void EncodeInstruction(const MCInst &Inst, raw_ostream &OS, virtual void EncodeInstruction(const MCInst &Inst, raw_ostream &OS,
SmallVectorImpl<MCFixup> &Fixups) const = 0; SmallVectorImpl<MCFixup> &Fixups) const = 0;
}; };
} // End llvm namespace } // End llvm namespace
#endif #endif
 End of changes. 3 change blocks. 
4 lines changed or deleted 6 lines changed or added


 MCContext.h   MCContext.h 
skipping to change at line 43 skipping to change at line 43
class SMLoc; class SMLoc;
class StringRef; class StringRef;
class Twine; class Twine;
class MCSectionMachO; class MCSectionMachO;
class MCSectionELF; class MCSectionELF;
/// MCContext - Context object for machine code objects. This class owns all /// MCContext - Context object for machine code objects. This class owns all
/// of the sections that it creates. /// of the sections that it creates.
/// ///
class MCContext { class MCContext {
MCContext(const MCContext&); // DO NOT IMPLEMENT MCContext(const MCContext&) LLVM_DELETED_FUNCTION;
MCContext &operator=(const MCContext&); // DO NOT IMPLEMENT MCContext &operator=(const MCContext&) LLVM_DELETED_FUNCTION;
public: public:
typedef StringMap<MCSymbol*, BumpPtrAllocator&> SymbolTable; typedef StringMap<MCSymbol*, BumpPtrAllocator&> SymbolTable;
private: private:
/// The SourceMgr for this object, if any. /// The SourceMgr for this object, if any.
const SourceMgr *SrcMgr; const SourceMgr *SrcMgr;
/// The MCAsmInfo for this target. /// The MCAsmInfo for this target.
const MCAsmInfo &MAI; const MCAsmInfo &MAI;
/// The MCRegisterInfo for this target. /// The MCRegisterInfo for this target.
skipping to change at line 164 skipping to change at line 164
void setAllowTemporaryLabels(bool Value) { AllowTemporaryLabels = Value ; } void setAllowTemporaryLabels(bool Value) { AllowTemporaryLabels = Value ; }
/// @name Symbol Management /// @name Symbol Management
/// @{ /// @{
/// CreateTempSymbol - Create and return a new assembler temporary symb ol /// CreateTempSymbol - Create and return a new assembler temporary symb ol
/// with a unique but unspecified name. /// with a unique but unspecified name.
MCSymbol *CreateTempSymbol(); MCSymbol *CreateTempSymbol();
/// getUniqueSymbolID() - Return a unique identifier for use in constru
cting
/// symbol names.
unsigned getUniqueSymbolID() { return NextUniqueID++; }
/// CreateDirectionalLocalSymbol - Create the definition of a direction al /// CreateDirectionalLocalSymbol - Create the definition of a direction al
/// local symbol for numbered label (used for "1:" definitions). /// local symbol for numbered label (used for "1:" definitions).
MCSymbol *CreateDirectionalLocalSymbol(int64_t LocalLabelVal); MCSymbol *CreateDirectionalLocalSymbol(int64_t LocalLabelVal);
/// GetDirectionalLocalSymbol - Create and return a directional local /// GetDirectionalLocalSymbol - Create and return a directional local
/// symbol for numbered label (used for "1b" or 1f" references). /// symbol for numbered label (used for "1b" or 1f" references).
MCSymbol *GetDirectionalLocalSymbol(int64_t LocalLabelVal, int bORf); MCSymbol *GetDirectionalLocalSymbol(int64_t LocalLabelVal, int bORf);
/// GetOrCreateSymbol - Lookup the symbol inside with the specified /// GetOrCreateSymbol - Lookup the symbol inside with the specified
/// @p Name. If it exists, return it. If not, create a forward /// @p Name. If it exists, return it. If not, create a forward
/// reference and return it. /// reference and return it.
/// ///
/// @param Name - The symbol name, which must be unique across all symb ols. /// @param Name - The symbol name, which must be unique across all symb ols.
MCSymbol *GetOrCreateSymbol(StringRef Name); MCSymbol *GetOrCreateSymbol(StringRef Name);
MCSymbol *GetOrCreateSymbol(const Twine &Name); MCSymbol *GetOrCreateSymbol(const Twine &Name);
/// LookupSymbol - Get the symbol for \p Name, or null. /// LookupSymbol - Get the symbol for \p Name, or null.
MCSymbol *LookupSymbol(StringRef Name) const; MCSymbol *LookupSymbol(StringRef Name) const;
MCSymbol *LookupSymbol(const Twine &Name) const;
/// getSymbols - Get a reference for the symbol table for clients that /// getSymbols - Get a reference for the symbol table for clients that
/// want to, for example, iterate over all symbols. 'const' because we /// want to, for example, iterate over all symbols. 'const' because we
/// still want any modifications to the table itself to use the MCConte xt /// still want any modifications to the table itself to use the MCConte xt
/// APIs. /// APIs.
const SymbolTable &getSymbols() const { const SymbolTable &getSymbols() const {
return Symbols; return Symbols;
} }
/// @} /// @}
 End of changes. 3 change blocks. 
2 lines changed or deleted 8 lines changed or added


 MCDirectives.h   MCDirectives.h 
skipping to change at line 55 skipping to change at line 55
}; };
enum MCAssemblerFlag { enum MCAssemblerFlag {
MCAF_SyntaxUnified, ///< .syntax (ARM/ELF) MCAF_SyntaxUnified, ///< .syntax (ARM/ELF)
MCAF_SubsectionsViaSymbols, ///< .subsections_via_symbols (MachO) MCAF_SubsectionsViaSymbols, ///< .subsections_via_symbols (MachO)
MCAF_Code16, ///< .code16 (X86) / .code 16 (ARM) MCAF_Code16, ///< .code16 (X86) / .code 16 (ARM)
MCAF_Code32, ///< .code32 (X86) / .code 32 (ARM) MCAF_Code32, ///< .code32 (X86) / .code 32 (ARM)
MCAF_Code64 ///< .code64 (X86) MCAF_Code64 ///< .code64 (X86)
}; };
enum MCDataRegionType {
MCDR_DataRegion, ///< .data_region
MCDR_DataRegionJT8, ///< .data_region jt8
MCDR_DataRegionJT16, ///< .data_region jt16
MCDR_DataRegionJT32, ///< .data_region jt32
MCDR_DataRegionEnd ///< .end_data_region
};
} // end namespace llvm } // end namespace llvm
#endif #endif
 End of changes. 1 change blocks. 
0 lines changed or deleted 8 lines changed or added


 MCDwarf.h   MCDwarf.h 
skipping to change at line 22 skipping to change at line 22
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_MC_MCDWARF_H #ifndef LLVM_MC_MCDWARF_H
#define LLVM_MC_MCDWARF_H #define LLVM_MC_MCDWARF_H
#include "llvm/ADT/StringRef.h" #include "llvm/ADT/StringRef.h"
#include "llvm/MC/MachineLocation.h" #include "llvm/MC/MachineLocation.h"
#include "llvm/Support/raw_ostream.h" #include "llvm/Support/raw_ostream.h"
#include "llvm/Support/Dwarf.h" #include "llvm/Support/Dwarf.h"
#include "llvm/Support/Compiler.h"
#include <vector> #include <vector>
namespace llvm { namespace llvm {
class MCContext; class MCContext;
class MCObjectWriter; class MCObjectWriter;
class MCSection; class MCSection;
class MCStreamer; class MCStreamer;
class MCSymbol; class MCSymbol;
class SourceMgr; class SourceMgr;
class SMLoc; class SMLoc;
skipping to change at line 51 skipping to change at line 52
StringRef Name; StringRef Name;
// DirIndex - the index into the list of directory names for this file name. // DirIndex - the index into the list of directory names for this file name.
unsigned DirIndex; unsigned DirIndex;
private: // MCContext creates and uniques these. private: // MCContext creates and uniques these.
friend class MCContext; friend class MCContext;
MCDwarfFile(StringRef name, unsigned dirIndex) MCDwarfFile(StringRef name, unsigned dirIndex)
: Name(name), DirIndex(dirIndex) {} : Name(name), DirIndex(dirIndex) {}
MCDwarfFile(const MCDwarfFile&); // DO NOT IMPLEMENT MCDwarfFile(const MCDwarfFile&) LLVM_DELETED_FUNCTION;
void operator=(const MCDwarfFile&); // DO NOT IMPLEMENT void operator=(const MCDwarfFile&) LLVM_DELETED_FUNCTION;
public: public:
/// getName - Get the base name of this MCDwarfFile. /// getName - Get the base name of this MCDwarfFile.
StringRef getName() const { return Name; } StringRef getName() const { return Name; }
/// getDirIndex - Get the dirIndex of this MCDwarfFile. /// getDirIndex - Get the dirIndex of this MCDwarfFile.
unsigned getDirIndex() const { return DirIndex; } unsigned getDirIndex() const { return DirIndex; }
/// print - Print the value to the stream \arg OS. /// print - Print the value to the stream \p OS.
void print(raw_ostream &OS) const; void print(raw_ostream &OS) const;
/// dump - Print the value to stderr. /// dump - Print the value to stderr.
void dump() const; void dump() const;
}; };
inline raw_ostream &operator<<(raw_ostream &OS, const MCDwarfFile &DwarfF ile){ inline raw_ostream &operator<<(raw_ostream &OS, const MCDwarfFile &DwarfF ile){
DwarfFile.print(OS); DwarfFile.print(OS);
return OS; return OS;
} }
skipping to change at line 179 skipping to change at line 180
static void Make(MCStreamer *MCOS, const MCSection *Section); static void Make(MCStreamer *MCOS, const MCSection *Section);
}; };
/// MCLineSection - Instances of this class represent the line informatio n /// MCLineSection - Instances of this class represent the line informatio n
/// for a section where machine instructions have been assembled after se eing /// for a section where machine instructions have been assembled after se eing
/// .loc directives. This is the information used to build the dwarf lin e /// .loc directives. This is the information used to build the dwarf lin e
/// table for a section. /// table for a section.
class MCLineSection { class MCLineSection {
private: private:
MCLineSection(const MCLineSection&); // DO NOT IMPLEMENT MCLineSection(const MCLineSection&) LLVM_DELETED_FUNCTION;
void operator=(const MCLineSection&); // DO NOT IMPLEMENT void operator=(const MCLineSection&) LLVM_DELETED_FUNCTION;
public: public:
// Constructor to create an MCLineSection with an empty MCLineEntries // Constructor to create an MCLineSection with an empty MCLineEntries
// vector. // vector.
MCLineSection() {} MCLineSection() {}
// addLineEntry - adds an entry to this MCLineSection's line entries // addLineEntry - adds an entry to this MCLineSection's line entries
void addLineEntry(const MCLineEntry &LineEntry) { void addLineEntry(const MCLineEntry &LineEntry) {
MCLineEntries.push_back(LineEntry); MCLineEntries.push_back(LineEntry);
} }
 End of changes. 4 change blocks. 
5 lines changed or deleted 6 lines changed or added


 MCELFObjectWriter.h   MCELFObjectWriter.h 
skipping to change at line 57 skipping to change at line 57
bool operator<(const ELFRelocationEntry &RE) const { bool operator<(const ELFRelocationEntry &RE) const {
return RE.r_offset < r_offset; return RE.r_offset < r_offset;
} }
}; };
class MCELFObjectTargetWriter { class MCELFObjectTargetWriter {
const uint8_t OSABI; const uint8_t OSABI;
const uint16_t EMachine; const uint16_t EMachine;
const unsigned HasRelocationAddend : 1; const unsigned HasRelocationAddend : 1;
const unsigned Is64Bit : 1; const unsigned Is64Bit : 1;
const unsigned IsN64 : 1;
protected: protected:
MCELFObjectTargetWriter(bool Is64Bit_, uint8_t OSABI_, MCELFObjectTargetWriter(bool Is64Bit_, uint8_t OSABI_,
uint16_t EMachine_, bool HasRelocationAddend_); uint16_t EMachine_, bool HasRelocationAddend,
bool IsN64=false);
public: public:
static uint8_t getOSABI(Triple::OSType OSType) { static uint8_t getOSABI(Triple::OSType OSType) {
switch (OSType) { switch (OSType) {
case Triple::FreeBSD: case Triple::FreeBSD:
return ELF::ELFOSABI_FREEBSD; return ELF::ELFOSABI_FREEBSD;
case Triple::Linux: case Triple::Linux:
return ELF::ELFOSABI_LINUX; return ELF::ELFOSABI_LINUX;
default: default:
return ELF::ELFOSABI_NONE; return ELF::ELFOSABI_NONE;
skipping to change at line 86 skipping to change at line 88
virtual unsigned GetRelocType(const MCValue &Target, const MCFixup &Fixup , virtual unsigned GetRelocType(const MCValue &Target, const MCFixup &Fixup ,
bool IsPCRel, bool IsRelocWithSymbol, bool IsPCRel, bool IsRelocWithSymbol,
int64_t Addend) const = 0; int64_t Addend) const = 0;
virtual unsigned getEFlags() const; virtual unsigned getEFlags() const;
virtual const MCSymbol *ExplicitRelSym(const MCAssembler &Asm, virtual const MCSymbol *ExplicitRelSym(const MCAssembler &Asm,
const MCValue &Target, const MCValue &Target,
const MCFragment &F, const MCFragment &F,
const MCFixup &Fixup, const MCFixup &Fixup,
bool IsPCRel) const; bool IsPCRel) const;
virtual const MCSymbol *undefinedExplicitRelSym(const MCValue &Target,
const MCFixup &Fixup,
bool IsPCRel) const;
virtual void adjustFixupOffset(const MCFixup &Fixup, virtual void adjustFixupOffset(const MCFixup &Fixup,
uint64_t &RelocOffset); uint64_t &RelocOffset);
virtual void sortRelocs(const MCAssembler &Asm, virtual void sortRelocs(const MCAssembler &Asm,
std::vector<ELFRelocationEntry> &Relocs); std::vector<ELFRelocationEntry> &Relocs);
/// @name Accessors /// @name Accessors
/// @{ /// @{
uint8_t getOSABI() { return OSABI; } uint8_t getOSABI() const { return OSABI; }
uint16_t getEMachine() { return EMachine; } uint16_t getEMachine() const { return EMachine; }
bool hasRelocationAddend() { return HasRelocationAddend; } bool hasRelocationAddend() const { return HasRelocationAddend; }
bool is64Bit() const { return Is64Bit; } bool is64Bit() const { return Is64Bit; }
bool isN64() const { return IsN64; }
/// @} /// @}
// Instead of changing everyone's API we pack the N64 Type fields
// into the existing 32 bit data unsigned.
#define R_TYPE_SHIFT 0
#define R_TYPE_MASK 0xffffff00
#define R_TYPE2_SHIFT 8
#define R_TYPE2_MASK 0xffff00ff
#define R_TYPE3_SHIFT 16
#define R_TYPE3_MASK 0xff00ffff
#define R_SSYM_SHIFT 24
#define R_SSYM_MASK 0x00ffffff
// N64 relocation type accessors
unsigned getRType(uint32_t Type) const {
return (unsigned)((Type >> R_TYPE_SHIFT) & 0xff);
}
unsigned getRType2(uint32_t Type) const {
return (unsigned)((Type >> R_TYPE2_SHIFT) & 0xff);
}
unsigned getRType3(uint32_t Type) const {
return (unsigned)((Type >> R_TYPE3_SHIFT) & 0xff);
}
unsigned getRSsym(uint32_t Type) const {
return (unsigned)((Type >> R_SSYM_SHIFT) & 0xff);
}
// N64 relocation type setting
unsigned setRType(unsigned Value, unsigned Type) const {
return ((Type & R_TYPE_MASK) | ((Value & 0xff) << R_TYPE_SHIFT));
}
unsigned setRType2(unsigned Value, unsigned Type) const {
return (Type & R_TYPE2_MASK) | ((Value & 0xff) << R_TYPE2_SHIFT);
}
unsigned setRType3(unsigned Value, unsigned Type) const {
return (Type & R_TYPE3_MASK) | ((Value & 0xff) << R_TYPE3_SHIFT);
}
unsigned setRSsym(unsigned Value, unsigned Type) const {
return (Type & R_SSYM_MASK) | ((Value & 0xff) << R_SSYM_SHIFT);
}
}; };
/// \brief Construct a new ELF writer instance. /// \brief Construct a new ELF writer instance.
/// ///
/// \param MOTW - The target specific ELF writer subclass. /// \param MOTW - The target specific ELF writer subclass.
/// \param OS - The stream to write to. /// \param OS - The stream to write to.
/// \returns The constructed object writer. /// \returns The constructed object writer.
MCObjectWriter *createELFObjectWriter(MCELFObjectTargetWriter *MOTW, MCObjectWriter *createELFObjectWriter(MCELFObjectTargetWriter *MOTW,
raw_ostream &OS, bool IsLittleEndian) ; raw_ostream &OS, bool IsLittleEndian) ;
} // End llvm namespace } // End llvm namespace
 End of changes. 6 change blocks. 
4 lines changed or deleted 49 lines changed or added


 MCExpr.h   MCExpr.h 
skipping to change at line 44 skipping to change at line 44
Binary, ///< Binary expressions. Binary, ///< Binary expressions.
Constant, ///< Constant expressions. Constant, ///< Constant expressions.
SymbolRef, ///< References to labels and assigned expressions. SymbolRef, ///< References to labels and assigned expressions.
Unary, ///< Unary expressions. Unary, ///< Unary expressions.
Target ///< Target specific expression. Target ///< Target specific expression.
}; };
private: private:
ExprKind Kind; ExprKind Kind;
MCExpr(const MCExpr&); // DO NOT IMPLEMENT MCExpr(const MCExpr&) LLVM_DELETED_FUNCTION;
void operator=(const MCExpr&); // DO NOT IMPLEMENT void operator=(const MCExpr&) LLVM_DELETED_FUNCTION;
bool EvaluateAsAbsolute(int64_t &Res, const MCAssembler *Asm, bool EvaluateAsAbsolute(int64_t &Res, const MCAssembler *Asm,
const MCAsmLayout *Layout, const MCAsmLayout *Layout,
const SectionAddrMap *Addrs) const; const SectionAddrMap *Addrs) const;
protected: protected:
explicit MCExpr(ExprKind _Kind) : Kind(_Kind) {} explicit MCExpr(ExprKind _Kind) : Kind(_Kind) {}
bool EvaluateAsRelocatableImpl(MCValue &Res, const MCAssembler *Asm, bool EvaluateAsRelocatableImpl(MCValue &Res, const MCAssembler *Asm,
const MCAsmLayout *Layout, const MCAsmLayout *Layout,
const SectionAddrMap *Addrs, const SectionAddrMap *Addrs,
skipping to change at line 81 skipping to change at line 81
/// @name Expression Evaluation /// @name Expression Evaluation
/// @{ /// @{
/// EvaluateAsAbsolute - Try to evaluate the expression to an absolute va lue. /// EvaluateAsAbsolute - Try to evaluate the expression to an absolute va lue.
/// ///
/// @param Res - The absolute value, if evaluation succeeds. /// @param Res - The absolute value, if evaluation succeeds.
/// @param Layout - The assembler layout object to use for evaluating sym bol /// @param Layout - The assembler layout object to use for evaluating sym bol
/// values. If not given, then only non-symbolic expressions will be /// values. If not given, then only non-symbolic expressions will be
/// evaluated. /// evaluated.
/// @result - True on success. /// @result - True on success.
bool EvaluateAsAbsolute(int64_t &Res, const MCAsmLayout &Layout,
const SectionAddrMap &Addrs) const;
bool EvaluateAsAbsolute(int64_t &Res) const; bool EvaluateAsAbsolute(int64_t &Res) const;
bool EvaluateAsAbsolute(int64_t &Res, const MCAssembler &Asm) const; bool EvaluateAsAbsolute(int64_t &Res, const MCAssembler &Asm) const;
bool EvaluateAsAbsolute(int64_t &Res, const MCAsmLayout &Layout) const; bool EvaluateAsAbsolute(int64_t &Res, const MCAsmLayout &Layout) const;
bool EvaluateAsAbsolute(int64_t &Res, const MCAsmLayout &Layout,
const SectionAddrMap &Addrs) const;
/// EvaluateAsRelocatable - Try to evaluate the expression to a relocatab le /// EvaluateAsRelocatable - Try to evaluate the expression to a relocatab le
/// value, i.e. an expression of the fixed form (a - b + constant). /// value, i.e. an expression of the fixed form (a - b + constant).
/// ///
/// @param Res - The relocatable value, if evaluation succeeds. /// @param Res - The relocatable value, if evaluation succeeds.
/// @param Layout - The assembler layout object to use for evaluating val ues. /// @param Layout - The assembler layout object to use for evaluating val ues.
/// @result - True on success. /// @result - True on success.
bool EvaluateAsRelocatable(MCValue &Res, const MCAsmLayout &Layout) const ; bool EvaluateAsRelocatable(MCValue &Res, const MCAsmLayout &Layout) const ;
/// FindAssociatedSection - Find the "associated section" for this expres sion, /// FindAssociatedSection - Find the "associated section" for this expres sion,
/// which is currently defined as the absolute section for constants, or /// which is currently defined as the absolute section for constants, or
/// otherwise the section associated with the first defined symbol in the /// otherwise the section associated with the first defined symbol in the
/// expression. /// expression.
const MCSection *FindAssociatedSection() const; const MCSection *FindAssociatedSection() const;
/// @} /// @}
static bool classof(const MCExpr *) { return true; }
}; };
inline raw_ostream &operator<<(raw_ostream &OS, const MCExpr &E) { inline raw_ostream &operator<<(raw_ostream &OS, const MCExpr &E) {
E.print(OS); E.print(OS);
return OS; return OS;
} }
//// MCConstantExpr - Represent a constant integer expression. //// MCConstantExpr - Represent a constant integer expression.
class MCConstantExpr : public MCExpr { class MCConstantExpr : public MCExpr {
int64_t Value; int64_t Value;
skipping to change at line 135 skipping to change at line 133
/// @name Accessors /// @name Accessors
/// @{ /// @{
int64_t getValue() const { return Value; } int64_t getValue() const { return Value; }
/// @} /// @}
static bool classof(const MCExpr *E) { static bool classof(const MCExpr *E) {
return E->getKind() == MCExpr::Constant; return E->getKind() == MCExpr::Constant;
} }
static bool classof(const MCConstantExpr *) { return true; }
}; };
/// MCSymbolRefExpr - Represent a reference to a symbol from inside an /// MCSymbolRefExpr - Represent a reference to a symbol from inside an
/// expression. /// expression.
/// ///
/// A symbol reference in an expression may be a use of a label, a use of a n /// A symbol reference in an expression may be a use of a label, a use of a n
/// assembler variable (defined constant), or constitute an implicit defini tion /// assembler variable (defined constant), or constitute an implicit defini tion
/// of the symbol as external. /// of the symbol as external.
class MCSymbolRefExpr : public MCExpr { class MCSymbolRefExpr : public MCExpr {
public: public:
skipping to change at line 173 skipping to change at line 170
VK_TLVP, // Mach-O thread local variable relocation VK_TLVP, // Mach-O thread local variable relocation
VK_SECREL, VK_SECREL,
// FIXME: We'd really like to use the generic Kinds listed above for th ese. // FIXME: We'd really like to use the generic Kinds listed above for th ese.
VK_ARM_PLT, // ARM-style PLT references. i.e., (PLT) instead of @PLT VK_ARM_PLT, // ARM-style PLT references. i.e., (PLT) instead of @PLT
VK_ARM_TLSGD, // ditto for TLSGD, GOT, GOTOFF, TPOFF and GOTTPOFF VK_ARM_TLSGD, // ditto for TLSGD, GOT, GOTOFF, TPOFF and GOTTPOFF
VK_ARM_GOT, VK_ARM_GOT,
VK_ARM_GOTOFF, VK_ARM_GOTOFF,
VK_ARM_TPOFF, VK_ARM_TPOFF,
VK_ARM_GOTTPOFF, VK_ARM_GOTTPOFF,
VK_ARM_TARGET1, VK_ARM_TARGET1,
VK_ARM_TARGET2,
VK_PPC_TOC, VK_PPC_TOC, // TOC base
VK_PPC_TOC_ENTRY, // TOC entry
VK_PPC_DARWIN_HA16, // ha16(symbol) VK_PPC_DARWIN_HA16, // ha16(symbol)
VK_PPC_DARWIN_LO16, // lo16(symbol) VK_PPC_DARWIN_LO16, // lo16(symbol)
VK_PPC_GAS_HA16, // symbol@ha VK_PPC_GAS_HA16, // symbol@ha
VK_PPC_GAS_LO16, // symbol@l VK_PPC_GAS_LO16, // symbol@l
VK_PPC_TPREL16_HA, // symbol@tprel@ha
VK_PPC_TPREL16_LO, // symbol@tprel@l
VK_Mips_GPREL, VK_Mips_GPREL,
VK_Mips_GOT_CALL, VK_Mips_GOT_CALL,
VK_Mips_GOT16, VK_Mips_GOT16,
VK_Mips_GOT, VK_Mips_GOT,
VK_Mips_ABS_HI, VK_Mips_ABS_HI,
VK_Mips_ABS_LO, VK_Mips_ABS_LO,
VK_Mips_TLSGD, VK_Mips_TLSGD,
VK_Mips_TLSLDM, VK_Mips_TLSLDM,
VK_Mips_DTPREL_HI, VK_Mips_DTPREL_HI,
VK_Mips_DTPREL_LO, VK_Mips_DTPREL_LO,
VK_Mips_GOTTPREL, VK_Mips_GOTTPREL,
VK_Mips_TPREL_HI, VK_Mips_TPREL_HI,
VK_Mips_TPREL_LO, VK_Mips_TPREL_LO,
VK_Mips_GPOFF_HI, VK_Mips_GPOFF_HI,
VK_Mips_GPOFF_LO, VK_Mips_GPOFF_LO,
VK_Mips_GOT_DISP, VK_Mips_GOT_DISP,
VK_Mips_GOT_PAGE, VK_Mips_GOT_PAGE,
VK_Mips_GOT_OFST VK_Mips_GOT_OFST,
VK_Mips_HIGHER,
VK_Mips_HIGHEST,
VK_Mips_GOT_HI16,
VK_Mips_GOT_LO16,
VK_Mips_CALL_HI16,
VK_Mips_CALL_LO16
}; };
private: private:
/// The symbol being referenced. /// The symbol being referenced.
const MCSymbol *Symbol; const MCSymbol *Symbol;
/// The symbol reference modifier. /// The symbol reference modifier.
const VariantKind Kind; const VariantKind Kind;
explicit MCSymbolRefExpr(const MCSymbol *_Symbol, VariantKind _Kind) explicit MCSymbolRefExpr(const MCSymbol *_Symbol, VariantKind _Kind)
skipping to change at line 246 skipping to change at line 253
static StringRef getVariantKindName(VariantKind Kind); static StringRef getVariantKindName(VariantKind Kind);
static VariantKind getVariantKindForName(StringRef Name); static VariantKind getVariantKindForName(StringRef Name);
/// @} /// @}
static bool classof(const MCExpr *E) { static bool classof(const MCExpr *E) {
return E->getKind() == MCExpr::SymbolRef; return E->getKind() == MCExpr::SymbolRef;
} }
static bool classof(const MCSymbolRefExpr *) { return true; }
}; };
/// MCUnaryExpr - Unary assembler expressions. /// MCUnaryExpr - Unary assembler expressions.
class MCUnaryExpr : public MCExpr { class MCUnaryExpr : public MCExpr {
public: public:
enum Opcode { enum Opcode {
LNot, ///< Logical negation. LNot, ///< Logical negation.
Minus, ///< Unary minus. Minus, ///< Unary minus.
Not, ///< Bitwise negation. Not, ///< Bitwise negation.
Plus ///< Unary plus. Plus ///< Unary plus.
skipping to change at line 300 skipping to change at line 306
Opcode getOpcode() const { return Op; } Opcode getOpcode() const { return Op; }
/// getSubExpr - Get the child of this unary expression. /// getSubExpr - Get the child of this unary expression.
const MCExpr *getSubExpr() const { return Expr; } const MCExpr *getSubExpr() const { return Expr; }
/// @} /// @}
static bool classof(const MCExpr *E) { static bool classof(const MCExpr *E) {
return E->getKind() == MCExpr::Unary; return E->getKind() == MCExpr::Unary;
} }
static bool classof(const MCUnaryExpr *) { return true; }
}; };
/// MCBinaryExpr - Binary assembler expressions. /// MCBinaryExpr - Binary assembler expressions.
class MCBinaryExpr : public MCExpr { class MCBinaryExpr : public MCExpr {
public: public:
enum Opcode { enum Opcode {
Add, ///< Addition. Add, ///< Addition.
And, ///< Bitwise and. And, ///< Bitwise and.
Div, ///< Signed division. Div, ///< Signed division.
EQ, ///< Equality comparison. EQ, ///< Equality comparison.
skipping to change at line 435 skipping to change at line 440
const MCExpr *getLHS() const { return LHS; } const MCExpr *getLHS() const { return LHS; }
/// getRHS - Get the right-hand side expression of the binary operator. /// getRHS - Get the right-hand side expression of the binary operator.
const MCExpr *getRHS() const { return RHS; } const MCExpr *getRHS() const { return RHS; }
/// @} /// @}
static bool classof(const MCExpr *E) { static bool classof(const MCExpr *E) {
return E->getKind() == MCExpr::Binary; return E->getKind() == MCExpr::Binary;
} }
static bool classof(const MCBinaryExpr *) { return true; }
}; };
/// MCTargetExpr - This is an extension point for target-specific MCExpr /// MCTargetExpr - This is an extension point for target-specific MCExpr
/// subclasses to implement. /// subclasses to implement.
/// ///
/// NOTE: All subclasses are required to have trivial destructors because /// NOTE: All subclasses are required to have trivial destructors because
/// MCExprs are bump pointer allocated and not destructed. /// MCExprs are bump pointer allocated and not destructed.
class MCTargetExpr : public MCExpr { class MCTargetExpr : public MCExpr {
virtual void Anchor(); virtual void anchor();
protected: protected:
MCTargetExpr() : MCExpr(Target) {} MCTargetExpr() : MCExpr(Target) {}
virtual ~MCTargetExpr() {} virtual ~MCTargetExpr() {}
public: public:
virtual void PrintImpl(raw_ostream &OS) const = 0; virtual void PrintImpl(raw_ostream &OS) const = 0;
virtual bool EvaluateAsRelocatableImpl(MCValue &Res, virtual bool EvaluateAsRelocatableImpl(MCValue &Res,
const MCAsmLayout *Layout) const = 0; const MCAsmLayout *Layout) const = 0;
virtual void AddValueSymbols(MCAssembler *) const = 0; virtual void AddValueSymbols(MCAssembler *) const = 0;
virtual const MCSection *FindAssociatedSection() const = 0; virtual const MCSection *FindAssociatedSection() const = 0;
static bool classof(const MCExpr *E) { static bool classof(const MCExpr *E) {
return E->getKind() == MCExpr::Target; return E->getKind() == MCExpr::Target;
} }
static bool classof(const MCTargetExpr *) { return true; }
}; };
} // end namespace llvm } // end namespace llvm
#endif #endif
 End of changes. 14 change blocks. 
14 lines changed or deleted 17 lines changed or added


 MCInst.h   MCInst.h 
skipping to change at line 185 skipping to change at line 185
iterator begin() { return Operands.begin(); } iterator begin() { return Operands.begin(); }
iterator end() { return Operands.end(); } iterator end() { return Operands.end(); }
iterator insert(iterator I, const MCOperand &Op) { iterator insert(iterator I, const MCOperand &Op) {
return Operands.insert(I, Op); return Operands.insert(I, Op);
} }
void print(raw_ostream &OS, const MCAsmInfo *MAI) const; void print(raw_ostream &OS, const MCAsmInfo *MAI) const;
void dump() const; void dump() const;
/// \brief Dump the MCInst as prettily as possible using the additional M C /// \brief Dump the MCInst as prettily as possible using the additional M C
/// structures, if given. Operators are separated by the \arg Separator /// structures, if given. Operators are separated by the \p Separator
/// string. /// string.
void dump_pretty(raw_ostream &OS, const MCAsmInfo *MAI = 0, void dump_pretty(raw_ostream &OS, const MCAsmInfo *MAI = 0,
const MCInstPrinter *Printer = 0, const MCInstPrinter *Printer = 0,
StringRef Separator = " ") const; StringRef Separator = " ") const;
}; };
inline raw_ostream& operator<<(raw_ostream &OS, const MCOperand &MO) { inline raw_ostream& operator<<(raw_ostream &OS, const MCOperand &MO) {
MO.print(OS, 0); MO.print(OS, 0);
return OS; return OS;
} }
 End of changes. 1 change blocks. 
1 lines changed or deleted 1 lines changed or added


 MCInstPrinter.h   MCInstPrinter.h 
skipping to change at line 36 skipping to change at line 36
/// Each comment must end with a newline. This will be null if verbose /// Each comment must end with a newline. This will be null if verbose
/// assembly emission is disable. /// assembly emission is disable.
raw_ostream *CommentStream; raw_ostream *CommentStream;
const MCAsmInfo &MAI; const MCAsmInfo &MAI;
const MCInstrInfo &MII; const MCInstrInfo &MII;
const MCRegisterInfo &MRI; const MCRegisterInfo &MRI;
/// The current set of available features. /// The current set of available features.
unsigned AvailableFeatures; unsigned AvailableFeatures;
/// True if we are printing marked up assembly.
bool UseMarkup;
/// Utility function for printing annotations. /// Utility function for printing annotations.
void printAnnotation(raw_ostream &OS, StringRef Annot); void printAnnotation(raw_ostream &OS, StringRef Annot);
public: public:
MCInstPrinter(const MCAsmInfo &mai, const MCInstrInfo &mii, MCInstPrinter(const MCAsmInfo &mai, const MCInstrInfo &mii,
const MCRegisterInfo &mri) const MCRegisterInfo &mri)
: CommentStream(0), MAI(mai), MII(mii), MRI(mri), AvailableFeatures(0) : CommentStream(0), MAI(mai), MII(mii), MRI(mri), AvailableFeatures(0),
{} UseMarkup(0) {}
virtual ~MCInstPrinter(); virtual ~MCInstPrinter();
/// setCommentStream - Specify a stream to emit comments to. /// setCommentStream - Specify a stream to emit comments to.
void setCommentStream(raw_ostream &OS) { CommentStream = &OS; } void setCommentStream(raw_ostream &OS) { CommentStream = &OS; }
/// printInst - Print the specified MCInst to the specified raw_ostream. /// printInst - Print the specified MCInst to the specified raw_ostream.
/// ///
virtual void printInst(const MCInst *MI, raw_ostream &OS, virtual void printInst(const MCInst *MI, raw_ostream &OS,
StringRef Annot) = 0; StringRef Annot) = 0;
/// getOpcodeName - Return the name of the specified opcode enum (e.g. /// getOpcodeName - Return the name of the specified opcode enum (e.g.
/// "MOV32ri") or empty if we can't resolve it. /// "MOV32ri") or empty if we can't resolve it.
StringRef getOpcodeName(unsigned Opcode) const; StringRef getOpcodeName(unsigned Opcode) const;
/// printRegName - Print the assembler register name. /// printRegName - Print the assembler register name.
virtual void printRegName(raw_ostream &OS, unsigned RegNo) const; virtual void printRegName(raw_ostream &OS, unsigned RegNo) const;
unsigned getAvailableFeatures() const { return AvailableFeatures; } unsigned getAvailableFeatures() const { return AvailableFeatures; }
void setAvailableFeatures(unsigned Value) { AvailableFeatures = Value; } void setAvailableFeatures(unsigned Value) { AvailableFeatures = Value; }
bool getUseMarkup() const { return UseMarkup; }
void setUseMarkup(bool Value) { UseMarkup = Value; }
/// Utility functions to make adding mark ups simpler.
StringRef markup(StringRef s) const;
StringRef markup(StringRef a, StringRef b) const;
}; };
} // namespace llvm } // namespace llvm
#endif #endif
 End of changes. 3 change blocks. 
2 lines changed or deleted 12 lines changed or added


 MCInstrDesc.h   MCInstrDesc.h 
//===-- llvm/Mc/McInstrDesc.h - Instruction Descriptors -*- C++ -*-===// //===-- llvm/MC/MCInstrDesc.h - Instruction Descriptors -*- C++ -*-===//
// //
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
// //
// This file is distributed under the University of Illinois Open Source // This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details. // License. See LICENSE.TXT for details.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// //
// This file defines the MCOperandInfo and MCInstrDesc classes, which // This file defines the MCOperandInfo and MCInstrDesc classes, which
// are used to describe target instructions and their operands. // are used to describe target instructions and their operands.
skipping to change at line 109 skipping to change at line 109
Pseudo, Pseudo,
Return, Return,
Call, Call,
Barrier, Barrier,
Terminator, Terminator,
Branch, Branch,
IndirectBranch, IndirectBranch,
Compare, Compare,
MoveImm, MoveImm,
Bitcast, Bitcast,
Select,
DelaySlot, DelaySlot,
FoldableAsLoad, FoldableAsLoad,
MayLoad, MayLoad,
MayStore, MayStore,
Predicable, Predicable,
NotDuplicable, NotDuplicable,
UnmodeledSideEffects, UnmodeledSideEffects,
Commutable, Commutable,
ConvertibleTo3Addr, ConvertibleTo3Addr,
UsesCustomInserter, UsesCustomInserter,
skipping to change at line 284 skipping to change at line 285
bool isMoveImmediate() const { bool isMoveImmediate() const {
return Flags & (1 << MCID::MoveImm); return Flags & (1 << MCID::MoveImm);
} }
/// isBitcast - Return true if this instruction is a bitcast instruction. /// isBitcast - Return true if this instruction is a bitcast instruction.
/// ///
bool isBitcast() const { bool isBitcast() const {
return Flags & (1 << MCID::Bitcast); return Flags & (1 << MCID::Bitcast);
} }
/// isSelect - Return true if this is a select instruction.
///
bool isSelect() const {
return Flags & (1 << MCID::Select);
}
/// isNotDuplicable - Return true if this instruction cannot be safely /// isNotDuplicable - Return true if this instruction cannot be safely
/// duplicated. For example, if the instruction has a unique labels atta ched /// duplicated. For example, if the instruction has a unique labels atta ched
/// to it, duplicating it would cause multiple definition errors. /// to it, duplicating it would cause multiple definition errors.
bool isNotDuplicable() const { bool isNotDuplicable() const {
return Flags & (1 << MCID::NotDuplicable); return Flags & (1 << MCID::NotDuplicable);
} }
/// hasDelaySlot - Returns true if the specified instruction has a delay slot /// hasDelaySlot - Returns true if the specified instruction has a delay slot
/// which must be filled by the code generator. /// which must be filled by the code generator.
bool hasDelaySlot() const { bool hasDelaySlot() const {
 End of changes. 3 change blocks. 
1 lines changed or deleted 8 lines changed or added


 MCInstrItineraries.h   MCInstrItineraries.h 
skipping to change at line 19 skipping to change at line 19
// //
// This file describes the structures used for instruction // This file describes the structures used for instruction
// itineraries, stages, and operand reads/writes. This is used by // itineraries, stages, and operand reads/writes. This is used by
// schedulers to determine instruction stages and latencies. // schedulers to determine instruction stages and latencies.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_MC_MCINSTRITINERARIES_H #ifndef LLVM_MC_MCINSTRITINERARIES_H
#define LLVM_MC_MCINSTRITINERARIES_H #define LLVM_MC_MCINSTRITINERARIES_H
#include "llvm/MC/MCSchedule.h"
#include <algorithm> #include <algorithm>
namespace llvm { namespace llvm {
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
/// Instruction stage - These values represent a non-pipelined step in /// Instruction stage - These values represent a non-pipelined step in
/// the execution of an instruction. Cycles represents the number of /// the execution of an instruction. Cycles represents the number of
/// discrete time slots needed to complete the stage. Units represent /// discrete time slots needed to complete the stage. Units represent
/// the choice of functional units that can be used to complete the /// the choice of functional units that can be used to complete the
/// stage. Eg. IntUnit1, IntUnit2. NextCycles indicates how many /// stage. Eg. IntUnit1, IntUnit2. NextCycles indicates how many
skipping to change at line 97 skipping to change at line 98
} }
}; };
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
/// Instruction itinerary - An itinerary represents the scheduling /// Instruction itinerary - An itinerary represents the scheduling
/// information for an instruction. This includes a set of stages /// information for an instruction. This includes a set of stages
/// occupies by the instruction, and the pipeline cycle in which /// occupies by the instruction, and the pipeline cycle in which
/// operands are read and written. /// operands are read and written.
/// ///
struct InstrItinerary { struct InstrItinerary {
unsigned NumMicroOps; ///< # of micro-ops, 0 means it's variable int NumMicroOps; ///< # of micro-ops, -1 means it's variable
unsigned FirstStage; ///< Index of first stage in itinerary unsigned FirstStage; ///< Index of first stage in itinerary
unsigned LastStage; ///< Index of last + 1 stage in itinerary unsigned LastStage; ///< Index of last + 1 stage in itinerary
unsigned FirstOperandCycle; ///< Index of first operand rd/wr unsigned FirstOperandCycle; ///< Index of first operand rd/wr
unsigned LastOperandCycle; ///< Index of last + 1 operand rd/wr unsigned LastOperandCycle; ///< Index of last + 1 operand rd/wr
}; };
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
/// Instruction itinerary Data - Itinerary data supplied by a subtarget to be /// Instruction itinerary Data - Itinerary data supplied by a subtarget to be
/// used by a target. /// used by a target.
/// ///
class InstrItineraryData { class InstrItineraryData {
public: public:
const MCSchedModel *SchedModel; ///< Basic machine properties.
const InstrStage *Stages; ///< Array of stages selected const InstrStage *Stages; ///< Array of stages selected
const unsigned *OperandCycles; ///< Array of operand cycles select ed const unsigned *OperandCycles; ///< Array of operand cycles select ed
const unsigned *Forwardings; ///< Array of pipeline forwarding p athes const unsigned *Forwardings; ///< Array of pipeline forwarding p athes
const InstrItinerary *Itineraries; ///< Array of itineraries selected const InstrItinerary *Itineraries; ///< Array of itineraries selected
unsigned IssueWidth; ///< Max issue per cycle. 0=Unknown .
/// Ctors. /// Ctors.
/// ///
InstrItineraryData() : Stages(0), OperandCycles(0), Forwardings(0), InstrItineraryData() : SchedModel(&MCSchedModel::DefaultSchedModel),
Itineraries(0), IssueWidth(0) {} Stages(0), OperandCycles(0),
Forwardings(0), Itineraries(0) {}
InstrItineraryData(const InstrStage *S, const unsigned *OS,
const unsigned *F, const InstrItinerary *I) InstrItineraryData(const MCSchedModel *SM, const InstrStage *S,
: Stages(S), OperandCycles(OS), Forwardings(F), Itineraries(I), const unsigned *OS, const unsigned *F)
IssueWidth(0) {} : SchedModel(SM), Stages(S), OperandCycles(OS), Forwardings(F),
Itineraries(SchedModel->InstrItineraries) {}
/// isEmpty - Returns true if there are no itineraries. /// isEmpty - Returns true if there are no itineraries.
/// ///
bool isEmpty() const { return Itineraries == 0; } bool isEmpty() const { return Itineraries == 0; }
/// isEndMarker - Returns true if the index is for the end marker /// isEndMarker - Returns true if the index is for the end marker
/// itinerary. /// itinerary.
/// ///
bool isEndMarker(unsigned ItinClassIndx) const { bool isEndMarker(unsigned ItinClassIndx) const {
return ((Itineraries[ItinClassIndx].FirstStage == ~0U) && return ((Itineraries[ItinClassIndx].FirstStage == ~0U) &&
skipping to change at line 156 skipping to change at line 158
/// ///
const InstrStage *endStage(unsigned ItinClassIndx) const { const InstrStage *endStage(unsigned ItinClassIndx) const {
unsigned StageIdx = Itineraries[ItinClassIndx].LastStage; unsigned StageIdx = Itineraries[ItinClassIndx].LastStage;
return Stages + StageIdx; return Stages + StageIdx;
} }
/// getStageLatency - Return the total stage latency of the given /// getStageLatency - Return the total stage latency of the given
/// class. The latency is the maximum completion time for any stage /// class. The latency is the maximum completion time for any stage
/// in the itinerary. /// in the itinerary.
/// ///
/// InstrStages override the itinerary's MinLatency property. In fact, if
the
/// stage latencies, which may be zero, are less than MinLatency,
/// getStageLatency returns a value less than MinLatency.
///
/// If no stages exist, MinLatency is used. If MinLatency is invalid (<0)
,
/// then it defaults to one cycle.
unsigned getStageLatency(unsigned ItinClassIndx) const { unsigned getStageLatency(unsigned ItinClassIndx) const {
// If the target doesn't provide itinerary information, use a simple // If the target doesn't provide itinerary information, use a simple
// non-zero default value for all instructions. Some target's provide // non-zero default value for all instructions.
a if (isEmpty())
// dummy (Generic) itinerary which should be handled as if it's itinera return SchedModel->MinLatency < 0 ? 1 : SchedModel->MinLatency;
ry is
// empty. We identify this by looking for a reference to stage zero (in
valid
// stage). This is different from beginStage == endState != 0, which co
uld
// be used for zero-latency pseudo ops.
if (isEmpty() || Itineraries[ItinClassIndx].FirstStage == 0)
return 1;
// Calculate the maximum completion time for any stage. // Calculate the maximum completion time for any stage.
unsigned Latency = 0, StartCycle = 0; unsigned Latency = 0, StartCycle = 0;
for (const InstrStage *IS = beginStage(ItinClassIndx), for (const InstrStage *IS = beginStage(ItinClassIndx),
*E = endStage(ItinClassIndx); IS != E; ++IS) { *E = endStage(ItinClassIndx); IS != E; ++IS) {
Latency = std::max(Latency, StartCycle + IS->getCycles()); Latency = std::max(Latency, StartCycle + IS->getCycles());
StartCycle += IS->getNextCycles(); StartCycle += IS->getNextCycles();
} }
return Latency; return Latency;
skipping to change at line 239 skipping to change at line 243
return -1; return -1;
UseCycle = DefCycle - UseCycle + 1; UseCycle = DefCycle - UseCycle + 1;
if (UseCycle > 0 && if (UseCycle > 0 &&
hasPipelineForwarding(DefClass, DefIdx, UseClass, UseIdx)) hasPipelineForwarding(DefClass, DefIdx, UseClass, UseIdx))
// FIXME: This assumes one cycle benefit for every pipeline forwardin g. // FIXME: This assumes one cycle benefit for every pipeline forwardin g.
--UseCycle; --UseCycle;
return UseCycle; return UseCycle;
} }
/// isMicroCoded - Return true if the instructions in the given class dec /// getNumMicroOps - Return the number of micro-ops that the given class
ode /// decodes to. Return -1 for classes that require dynamic lookup via
/// to more than one micro-ops. /// TargetInstrInfo.
bool isMicroCoded(unsigned ItinClassIndx) const { int getNumMicroOps(unsigned ItinClassIndx) const {
if (isEmpty()) if (isEmpty())
return false; return 1;
return Itineraries[ItinClassIndx].NumMicroOps != 1; return Itineraries[ItinClassIndx].NumMicroOps;
} }
}; };
} // End llvm namespace } // End llvm namespace
#endif #endif
 End of changes. 9 change blocks. 
26 lines changed or deleted 28 lines changed or added


 MCJIT.h   MCJIT.h 
skipping to change at line 26 skipping to change at line 26
#define LLVM_EXECUTION_ENGINE_MCJIT_H #define LLVM_EXECUTION_ENGINE_MCJIT_H
#include "llvm/ExecutionEngine/ExecutionEngine.h" #include "llvm/ExecutionEngine/ExecutionEngine.h"
#include <cstdlib> #include <cstdlib>
extern "C" void LLVMLinkInMCJIT(); extern "C" void LLVMLinkInMCJIT();
namespace { namespace {
struct ForceMCJITLinking { struct ForceMCJITLinking {
ForceMCJITLinking() { ForceMCJITLinking() {
// We must reference the passes in such a way that compilers will not // We must reference MCJIT in such a way that compilers will not
// delete it all as dead code, even with whole program optimization, // delete it all as dead code, even with whole program optimization,
// yet is effectively a NO-OP. As the compiler isn't smart enough // yet is effectively a NO-OP. As the compiler isn't smart enough
// to know that getenv() never returns -1, this will do the job. // to know that getenv() never returns -1, this will do the job.
if (std::getenv("bar") != (char*) -1) if (std::getenv("bar") != (char*) -1)
return; return;
LLVMLinkInMCJIT(); LLVMLinkInMCJIT();
} }
} ForceMCJITLinking; } ForceMCJITLinking;
} }
 End of changes. 1 change blocks. 
1 lines changed or deleted 1 lines changed or added


 MCLabel.h   MCLabel.h 
skipping to change at line 17 skipping to change at line 17
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// //
// This file contains the declaration of the MCLabel class. // This file contains the declaration of the MCLabel class.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_MC_MCLABEL_H #ifndef LLVM_MC_MCLABEL_H
#define LLVM_MC_MCLABEL_H #define LLVM_MC_MCLABEL_H
#include "llvm/Support/Compiler.h"
namespace llvm { namespace llvm {
class MCContext; class MCContext;
class raw_ostream; class raw_ostream;
/// MCLabel - Instances of this class represent a label name in the MC fi le, /// MCLabel - Instances of this class represent a label name in the MC fi le,
/// and MCLabel are created and unique'd by the MCContext class. MCLabel /// and MCLabel are created and unique'd by the MCContext class. MCLabel
/// should only be constructed for valid instances in the object file. /// should only be constructed for valid instances in the object file.
class MCLabel { class MCLabel {
// Instance - the instance number of this Directional Local Label // Instance - the instance number of this Directional Local Label
unsigned Instance; unsigned Instance;
private: // MCContext creates and uniques these. private: // MCContext creates and uniques these.
friend class MCContext; friend class MCContext;
MCLabel(unsigned instance) MCLabel(unsigned instance)
: Instance(instance) {} : Instance(instance) {}
MCLabel(const MCLabel&); // DO NOT IMPLEMENT MCLabel(const MCLabel&) LLVM_DELETED_FUNCTION;
void operator=(const MCLabel&); // DO NOT IMPLEMENT void operator=(const MCLabel&) LLVM_DELETED_FUNCTION;
public: public:
/// getInstance - Get the current instance of this Directional Local La bel. /// getInstance - Get the current instance of this Directional Local La bel.
unsigned getInstance() const { return Instance; } unsigned getInstance() const { return Instance; }
/// incInstance - Increment the current instance of this Directional Lo cal /// incInstance - Increment the current instance of this Directional Lo cal
/// Label. /// Label.
unsigned incInstance() { return ++Instance; } unsigned incInstance() { return ++Instance; }
/// print - Print the value to the stream \arg OS. /// print - Print the value to the stream \p OS.
void print(raw_ostream &OS) const; void print(raw_ostream &OS) const;
/// dump - Print the value to stderr. /// dump - Print the value to stderr.
void dump() const; void dump() const;
}; };
inline raw_ostream &operator<<(raw_ostream &OS, const MCLabel &Label) { inline raw_ostream &operator<<(raw_ostream &OS, const MCLabel &Label) {
Label.print(OS); Label.print(OS);
return OS; return OS;
} }
 End of changes. 3 change blocks. 
3 lines changed or deleted 5 lines changed or added


 MCMachObjectWriter.h   MCMachObjectWriter.h 
skipping to change at line 156 skipping to change at line 156
return CPUType == object::mach::CTM_ARM; return CPUType == object::mach::CTM_ARM;
} }
/// @} /// @}
void WriteHeader(unsigned NumLoadCommands, unsigned LoadCommandsSize, void WriteHeader(unsigned NumLoadCommands, unsigned LoadCommandsSize,
bool SubsectionsViaSymbols); bool SubsectionsViaSymbols);
/// WriteSegmentLoadCommand - Write a segment load command. /// WriteSegmentLoadCommand - Write a segment load command.
/// ///
/// \arg NumSections - The number of sections in this segment. /// \param NumSections The number of sections in this segment.
/// \arg SectionDataSize - The total size of the sections. /// \param SectionDataSize The total size of the sections.
void WriteSegmentLoadCommand(unsigned NumSections, void WriteSegmentLoadCommand(unsigned NumSections,
uint64_t VMSize, uint64_t VMSize,
uint64_t SectionDataStartOffset, uint64_t SectionDataStartOffset,
uint64_t SectionDataSize); uint64_t SectionDataSize);
void WriteSection(const MCAssembler &Asm, const MCAsmLayout &Layout, void WriteSection(const MCAssembler &Asm, const MCAsmLayout &Layout,
const MCSectionData &SD, uint64_t FileOffset, const MCSectionData &SD, uint64_t FileOffset,
uint64_t RelocationsStart, unsigned NumRelocations); uint64_t RelocationsStart, unsigned NumRelocations);
void WriteSymtabLoadCommand(uint32_t SymbolOffset, uint32_t NumSymbols, void WriteSymtabLoadCommand(uint32_t SymbolOffset, uint32_t NumSymbols,
skipping to change at line 182 skipping to change at line 182
uint32_t NumLocalSymbols, uint32_t NumLocalSymbols,
uint32_t FirstExternalSymbol, uint32_t FirstExternalSymbol,
uint32_t NumExternalSymbols, uint32_t NumExternalSymbols,
uint32_t FirstUndefinedSymbol, uint32_t FirstUndefinedSymbol,
uint32_t NumUndefinedSymbols, uint32_t NumUndefinedSymbols,
uint32_t IndirectSymbolOffset, uint32_t IndirectSymbolOffset,
uint32_t NumIndirectSymbols); uint32_t NumIndirectSymbols);
void WriteNlist(MachSymbolData &MSD, const MCAsmLayout &Layout); void WriteNlist(MachSymbolData &MSD, const MCAsmLayout &Layout);
void WriteLinkeditLoadCommand(uint32_t Type, uint32_t DataOffset,
uint32_t DataSize);
// FIXME: We really need to improve the relocation validation. Basically, we // FIXME: We really need to improve the relocation validation. Basically, we
// want to implement a separate computation which evaluates the relocatio n // want to implement a separate computation which evaluates the relocatio n
// entry as the linker would, and verifies that the resultant fixup value is // entry as the linker would, and verifies that the resultant fixup value is
// exactly what the encoder wanted. This will catch several classes of // exactly what the encoder wanted. This will catch several classes of
// problems: // problems:
// //
// - Relocation entry bugs, the two algorithms are unlikely to have the same // - Relocation entry bugs, the two algorithms are unlikely to have the same
// exact bug. // exact bug.
// //
// - Relaxation issues, where we forget to relax something. // - Relaxation issues, where we forget to relax something.
skipping to change at line 233 skipping to change at line 236
/// \param StringIndexMap [out] - Map from symbol names to offsets in the /// \param StringIndexMap [out] - Map from symbol names to offsets in the
/// string table. /// string table.
void ComputeSymbolTable(MCAssembler &Asm, SmallString<256> &StringTable, void ComputeSymbolTable(MCAssembler &Asm, SmallString<256> &StringTable,
std::vector<MachSymbolData> &LocalSymbolData, std::vector<MachSymbolData> &LocalSymbolData,
std::vector<MachSymbolData> &ExternalSymbolData, std::vector<MachSymbolData> &ExternalSymbolData,
std::vector<MachSymbolData> &UndefinedSymbolData) ; std::vector<MachSymbolData> &UndefinedSymbolData) ;
void computeSectionAddresses(const MCAssembler &Asm, void computeSectionAddresses(const MCAssembler &Asm,
const MCAsmLayout &Layout); const MCAsmLayout &Layout);
void markAbsoluteVariableSymbols(MCAssembler &Asm,
const MCAsmLayout &Layout);
void ExecutePostLayoutBinding(MCAssembler &Asm, const MCAsmLayout &Layout ); void ExecutePostLayoutBinding(MCAssembler &Asm, const MCAsmLayout &Layout );
virtual bool IsSymbolRefDifferenceFullyResolvedImpl(const MCAssembler &As m, virtual bool IsSymbolRefDifferenceFullyResolvedImpl(const MCAssembler &As m,
const MCSymbolData &D ataA, const MCSymbolData &D ataA,
const MCFragment &FB, const MCFragment &FB,
bool InSet, bool InSet,
bool IsPCRel) const; bool IsPCRel) const;
void WriteObject(MCAssembler &Asm, const MCAsmLayout &Layout); void WriteObject(MCAssembler &Asm, const MCAsmLayout &Layout);
}; };
 End of changes. 3 change blocks. 
2 lines changed or deleted 7 lines changed or added


 MCObjectFileInfo.h   MCObjectFileInfo.h 
skipping to change at line 87 skipping to change at line 87
/// LSDASection - If exception handling is supported by the target, this is /// LSDASection - If exception handling is supported by the target, this is
/// the section the Language Specific Data Area information is emitted to . /// the section the Language Specific Data Area information is emitted to .
const MCSection *LSDASection; const MCSection *LSDASection;
/// CompactUnwindSection - If exception handling is supported by the targ et /// CompactUnwindSection - If exception handling is supported by the targ et
/// and the target can support a compact representation of the CIE and FD E, /// and the target can support a compact representation of the CIE and FD E,
/// this is the section to emit them into. /// this is the section to emit them into.
const MCSection *CompactUnwindSection; const MCSection *CompactUnwindSection;
/// DwarfAccelNamesSection, DwarfAccelObjCSection /// DwarfAccelNamesSection, DwarfAccelObjCSection,
/// DwarfAccelNamespaceSection, DwarfAccelTypesSection -
/// If we use the DWARF accelerated hash tables then we want toe emit the se /// If we use the DWARF accelerated hash tables then we want toe emit the se
/// sections. /// sections.
const MCSection *DwarfAccelNamesSection; const MCSection *DwarfAccelNamesSection;
const MCSection *DwarfAccelObjCSection; const MCSection *DwarfAccelObjCSection;
const MCSection *DwarfAccelNamespaceSection; const MCSection *DwarfAccelNamespaceSection;
const MCSection *DwarfAccelTypesSection; const MCSection *DwarfAccelTypesSection;
// Dwarf sections for debug info. If a target supports debug info, these must // Dwarf sections for debug info. If a target supports debug info, these must
// be set. // be set.
const MCSection *DwarfAbbrevSection; const MCSection *DwarfAbbrevSection;
 End of changes. 1 change blocks. 
1 lines changed or deleted 2 lines changed or added


 MCObjectStreamer.h   MCObjectStreamer.h 
skipping to change at line 75 skipping to change at line 75
virtual void EmitLabel(MCSymbol *Symbol); virtual void EmitLabel(MCSymbol *Symbol);
virtual void EmitValueImpl(const MCExpr *Value, unsigned Size, virtual void EmitValueImpl(const MCExpr *Value, unsigned Size,
unsigned AddrSpace); unsigned AddrSpace);
virtual void EmitULEB128Value(const MCExpr *Value); virtual void EmitULEB128Value(const MCExpr *Value);
virtual void EmitSLEB128Value(const MCExpr *Value); virtual void EmitSLEB128Value(const MCExpr *Value);
virtual void EmitWeakReference(MCSymbol *Alias, const MCSymbol *Symbol); virtual void EmitWeakReference(MCSymbol *Alias, const MCSymbol *Symbol);
virtual void ChangeSection(const MCSection *Section); virtual void ChangeSection(const MCSection *Section);
virtual void EmitInstruction(const MCInst &Inst); virtual void EmitInstruction(const MCInst &Inst);
virtual void EmitInstToFragment(const MCInst &Inst); virtual void EmitInstToFragment(const MCInst &Inst);
virtual void EmitBytes(StringRef Data, unsigned AddrSpace);
virtual void EmitValueToAlignment(unsigned ByteAlignment,
int64_t Value = 0,
unsigned ValueSize = 1,
unsigned MaxBytesToEmit = 0);
virtual void EmitCodeAlignment(unsigned ByteAlignment,
unsigned MaxBytesToEmit = 0);
virtual bool EmitValueToOffset(const MCExpr *Offset, unsigned char Value) ; virtual bool EmitValueToOffset(const MCExpr *Offset, unsigned char Value) ;
virtual void EmitDwarfAdvanceLineAddr(int64_t LineDelta, virtual void EmitDwarfAdvanceLineAddr(int64_t LineDelta,
const MCSymbol *LastLabel, const MCSymbol *LastLabel,
const MCSymbol *Label, const MCSymbol *Label,
unsigned PointerSize); unsigned PointerSize);
virtual void EmitDwarfAdvanceFrameAddr(const MCSymbol *LastLabel, virtual void EmitDwarfAdvanceFrameAddr(const MCSymbol *LastLabel,
const MCSymbol *Label); const MCSymbol *Label);
virtual void EmitGPRel32Value(const MCExpr *Value); virtual void EmitGPRel32Value(const MCExpr *Value);
virtual void EmitGPRel64Value(const MCExpr *Value);
virtual void EmitFill(uint64_t NumBytes, uint8_t FillValue,
unsigned AddrSpace);
virtual void FinishImpl(); virtual void FinishImpl();
/// @} /// @}
}; };
} // end namespace llvm } // end namespace llvm
#endif #endif
 End of changes. 2 change blocks. 
0 lines changed or deleted 10 lines changed or added


 MCObjectWriter.h   MCObjectWriter.h 
skipping to change at line 14 skipping to change at line 14
// //
// This file is distributed under the University of Illinois Open Source // This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details. // License. See LICENSE.TXT for details.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_MC_MCOBJECTWRITER_H #ifndef LLVM_MC_MCOBJECTWRITER_H
#define LLVM_MC_MCOBJECTWRITER_H #define LLVM_MC_MCOBJECTWRITER_H
#include "llvm/Support/raw_ostream.h" #include "llvm/Support/raw_ostream.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/DataTypes.h" #include "llvm/Support/DataTypes.h"
#include <cassert> #include <cassert>
namespace llvm { namespace llvm {
class MCAsmLayout; class MCAsmLayout;
class MCAssembler; class MCAssembler;
class MCFixup; class MCFixup;
class MCFragment; class MCFragment;
class MCSymbolData; class MCSymbolData;
class MCSymbolRefExpr; class MCSymbolRefExpr;
skipping to change at line 38 skipping to change at line 39
/// ///
/// The object writer contains a few callbacks used by the assembler to all ow /// The object writer contains a few callbacks used by the assembler to all ow
/// the object writer to modify the assembler data structures at appropriat e /// the object writer to modify the assembler data structures at appropriat e
/// points. Once assembly is complete, the object writer is given the /// points. Once assembly is complete, the object writer is given the
/// MCAssembler instance, which contains all the symbol and section data wh ich /// MCAssembler instance, which contains all the symbol and section data wh ich
/// should be emitted as part of WriteObject(). /// should be emitted as part of WriteObject().
/// ///
/// The object writer also contains a number of helper methods for writing /// The object writer also contains a number of helper methods for writing
/// binary data to the output stream. /// binary data to the output stream.
class MCObjectWriter { class MCObjectWriter {
MCObjectWriter(const MCObjectWriter &); // DO NOT IMPLEMENT MCObjectWriter(const MCObjectWriter &) LLVM_DELETED_FUNCTION;
void operator=(const MCObjectWriter &); // DO NOT IMPLEMENT void operator=(const MCObjectWriter &) LLVM_DELETED_FUNCTION;
protected: protected:
raw_ostream &OS; raw_ostream &OS;
unsigned IsLittleEndian : 1; unsigned IsLittleEndian : 1;
protected: // Can only create subclasses. protected: // Can only create subclasses.
MCObjectWriter(raw_ostream &_OS, bool _IsLittleEndian) MCObjectWriter(raw_ostream &_OS, bool _IsLittleEndian)
: OS(_OS), IsLittleEndian(_IsLittleEndian) {} : OS(_OS), IsLittleEndian(_IsLittleEndian) {}
skipping to change at line 184 skipping to change at line 185
void WriteBytes(StringRef Str, unsigned ZeroFillSize = 0) { void WriteBytes(StringRef Str, unsigned ZeroFillSize = 0) {
assert((ZeroFillSize == 0 || Str.size () <= ZeroFillSize) && assert((ZeroFillSize == 0 || Str.size () <= ZeroFillSize) &&
"data size greater than fill size, unexpected large write will occur" ); "data size greater than fill size, unexpected large write will occur" );
OS << Str; OS << Str;
if (ZeroFillSize) if (ZeroFillSize)
WriteZeros(ZeroFillSize - Str.size()); WriteZeros(ZeroFillSize - Str.size());
} }
/// @} /// @}
/// Utility function to encode a SLEB128 value.
static void EncodeSLEB128(int64_t Value, raw_ostream &OS);
/// Utility function to encode a ULEB128 value.
static void EncodeULEB128(uint64_t Value, raw_ostream &OS,
unsigned Padding = 0);
}; };
} // End llvm namespace } // End llvm namespace
#endif #endif
 End of changes. 3 change blocks. 
7 lines changed or deleted 3 lines changed or added


 MCParsedAsmOperand.h   MCParsedAsmOperand.h 
skipping to change at line 22 skipping to change at line 22
namespace llvm { namespace llvm {
class SMLoc; class SMLoc;
class raw_ostream; class raw_ostream;
/// MCParsedAsmOperand - This abstract class represents a source-level asse mbly /// MCParsedAsmOperand - This abstract class represents a source-level asse mbly
/// instruction operand. It should be subclassed by target-specific code. This /// instruction operand. It should be subclassed by target-specific code. This
/// base class is used by target-independent clients and is the interface /// base class is used by target-independent clients and is the interface
/// between parsing an asm instruction and recognizing it. /// between parsing an asm instruction and recognizing it.
class MCParsedAsmOperand { class MCParsedAsmOperand {
/// MCOperandNum - The corresponding MCInst operand number. Only valid w
hen
/// parsing MS-style inline assembly.
unsigned MCOperandNum;
/// Constraint - The constraint on this operand. Only valid when parsing
/// MS-style inline assembly.
std::string Constraint;
public: public:
MCParsedAsmOperand() {} MCParsedAsmOperand() {}
virtual ~MCParsedAsmOperand() {} virtual ~MCParsedAsmOperand() {}
void setConstraint(StringRef C) { Constraint = C.str(); }
StringRef getConstraint() { return Constraint; }
void setMCOperandNum (unsigned OpNum) { MCOperandNum = OpNum; }
unsigned getMCOperandNum() { return MCOperandNum; }
unsigned getNameLen() {
assert (getStartLoc().isValid() && "Invalid StartLoc!");
assert (getEndLoc().isValid() && "Invalid EndLoc!");
return getEndLoc().getPointer() - getStartLoc().getPointer();
}
StringRef getName() {
return StringRef(getStartLoc().getPointer(), getNameLen());
}
/// isToken - Is this a token operand?
virtual bool isToken() const = 0;
/// isImm - Is this an immediate operand?
virtual bool isImm() const = 0;
/// isReg - Is this a register operand?
virtual bool isReg() const = 0;
virtual unsigned getReg() const = 0;
/// isMem - Is this a memory operand?
virtual bool isMem() const = 0;
virtual unsigned getMemSize() const { return 0; }
/// getStartLoc - Get the location of the first token of this operand. /// getStartLoc - Get the location of the first token of this operand.
virtual SMLoc getStartLoc() const = 0; virtual SMLoc getStartLoc() const = 0;
/// getEndLoc - Get the location of the last token of this operand. /// getEndLoc - Get the location of the last token of this operand.
virtual SMLoc getEndLoc() const = 0; virtual SMLoc getEndLoc() const = 0;
/// needAsmRewrite - AsmRewrites happen in both the target-independent an
d
/// target-dependent parsers. The target-independent parser calls this
/// function to determine if the target-dependent parser has already take
n
/// care of the rewrites. Only valid when parsing MS-style inline assemb
ly.
virtual bool needAsmRewrite() const { return true; }
/// isOffsetOf - Do we need to emit code to get the offset of the variabl
e,
/// rather then the value of the variable? Only valid when parsing MS-s
tyle
/// inline assembly.
virtual bool isOffsetOf() const { return false; }
/// getOffsetOfLoc - Get the location of the offset operator.
virtual SMLoc getOffsetOfLoc() const { return SMLoc(); }
/// needSizeDirective - Do we need to emit a sizing directive for this
/// operand? Only valid when parsing MS-style inline assembly.
virtual bool needSizeDirective() const { return false; }
/// print - Print a debug representation of the operand to the given stre am. /// print - Print a debug representation of the operand to the given stre am.
virtual void print(raw_ostream &OS) const = 0; virtual void print(raw_ostream &OS) const = 0;
/// dump - Print to the debug stream. /// dump - Print to the debug stream.
virtual void dump() const; virtual void dump() const;
}; };
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// Debugging Support // Debugging Support
inline raw_ostream& operator<<(raw_ostream &OS, const MCParsedAsmOperand &M O) { inline raw_ostream& operator<<(raw_ostream &OS, const MCParsedAsmOperand &M O) {
 End of changes. 3 change blocks. 
0 lines changed or deleted 60 lines changed or added


 MCRegisterInfo.h   MCRegisterInfo.h 
skipping to change at line 109 skipping to change at line 109
/// a particular register. The Overlaps field contains a pointer to a zero /// a particular register. The Overlaps field contains a pointer to a zero
/// terminated array of registers that this register aliases, starting with /// terminated array of registers that this register aliases, starting with
/// itself. This is needed for architectures like X86 which have AL alias A X /// itself. This is needed for architectures like X86 which have AL alias A X
/// alias EAX. The SubRegs field is a zero terminated array of registers th at /// alias EAX. The SubRegs field is a zero terminated array of registers th at
/// are sub-registers of the specific register, e.g. AL, AH are sub-registe rs of /// are sub-registers of the specific register, e.g. AL, AH are sub-registe rs of
/// AX. The SuperRegs field is a zero terminated array of registers that ar e /// AX. The SuperRegs field is a zero terminated array of registers that ar e
/// super-registers of the specific register, e.g. RAX, EAX, are super-regi sters /// super-registers of the specific register, e.g. RAX, EAX, are super-regi sters
/// of AX. /// of AX.
/// ///
struct MCRegisterDesc { struct MCRegisterDesc {
const char *Name; // Printable name for the reg (for debugging) uint32_t Name; // Printable name for the reg (for debugging)
uint32_t Overlaps; // Overlapping registers, described above uint32_t Overlaps; // Overlapping registers, described above
uint32_t SubRegs; // Sub-register set, described above uint32_t SubRegs; // Sub-register set, described above
uint32_t SuperRegs; // Super-register set, described above uint32_t SuperRegs; // Super-register set, described above
// Offset into MCRI::SubRegIndices of a list of sub-register indices for
each
// sub-register in SubRegs.
uint32_t SubRegIndices;
// RegUnits - Points to the list of register units. The low 4 bits holds
the
// Scale, the high bits hold an offset into DiffLists. See MCRegUnitItera
tor.
uint32_t RegUnits;
}; };
/// MCRegisterInfo base class - We assume that the target defines a static /// MCRegisterInfo base class - We assume that the target defines a static
/// array of MCRegisterDesc objects that represent all of the machine /// array of MCRegisterDesc objects that represent all of the machine
/// registers that the target has. As such, we simply have to track a poin ter /// registers that the target has. As such, we simply have to track a poin ter
/// to this array so that we can turn register number into a register /// to this array so that we can turn register number into a register
/// descriptor. /// descriptor.
/// ///
/// Note this class is designed to be a base class of TargetRegisterInfo, w hich /// Note this class is designed to be a base class of TargetRegisterInfo, w hich
/// is the interface used by codegen. However, specific targets *should nev er* /// is the interface used by codegen. However, specific targets *should nev er*
skipping to change at line 145 skipping to change at line 153
unsigned ToReg; unsigned ToReg;
bool operator<(DwarfLLVMRegPair RHS) const { return FromReg < RHS.FromR eg; } bool operator<(DwarfLLVMRegPair RHS) const { return FromReg < RHS.FromR eg; }
}; };
private: private:
const MCRegisterDesc *Desc; // Pointer to the descriptor array const MCRegisterDesc *Desc; // Pointer to the descriptor array
unsigned NumRegs; // Number of entries in the a rray unsigned NumRegs; // Number of entries in the a rray
unsigned RAReg; // Return address register unsigned RAReg; // Return address register
const MCRegisterClass *Classes; // Pointer to the regclass ar ray const MCRegisterClass *Classes; // Pointer to the regclass ar ray
unsigned NumClasses; // Number of entries in the a rray unsigned NumClasses; // Number of entries in the a rray
const uint16_t *RegLists; // Pointer to the reglists ar unsigned NumRegUnits; // Number of regunits.
ray const uint16_t (*RegUnitRoots)[2]; // Pointer to regunit root ta
ble.
const uint16_t *DiffLists; // Pointer to the difflists a
rray
const char *RegStrings; // Pointer to the string tabl
e.
const uint16_t *SubRegIndices; // Pointer to the subreg look up const uint16_t *SubRegIndices; // Pointer to the subreg look up
// array. // array.
unsigned NumSubRegIndices; // Number of subreg indices. unsigned NumSubRegIndices; // Number of subreg indices.
const uint16_t *RegEncodingTable; // Pointer to array of regist
er
// encodings.
unsigned L2DwarfRegsSize; unsigned L2DwarfRegsSize;
unsigned EHL2DwarfRegsSize; unsigned EHL2DwarfRegsSize;
unsigned Dwarf2LRegsSize; unsigned Dwarf2LRegsSize;
unsigned EHDwarf2LRegsSize; unsigned EHDwarf2LRegsSize;
const DwarfLLVMRegPair *L2DwarfRegs; // LLVM to Dwarf regs mapping const DwarfLLVMRegPair *L2DwarfRegs; // LLVM to Dwarf regs mapping
const DwarfLLVMRegPair *EHL2DwarfRegs; // LLVM to Dwarf regs mapping EH const DwarfLLVMRegPair *EHL2DwarfRegs; // LLVM to Dwarf regs mapping EH
const DwarfLLVMRegPair *Dwarf2LRegs; // Dwarf to LLVM regs mapping const DwarfLLVMRegPair *Dwarf2LRegs; // Dwarf to LLVM regs mapping
const DwarfLLVMRegPair *EHDwarf2LRegs; // Dwarf to LLVM regs mapping EH const DwarfLLVMRegPair *EHDwarf2LRegs; // Dwarf to LLVM regs mapping EH
DenseMap<unsigned, int> L2SEHRegs; // LLVM to SEH regs mapping DenseMap<unsigned, int> L2SEHRegs; // LLVM to SEH regs mapping
public: public:
/// DiffListIterator - Base iterator class that can traverse the
/// differentially encoded register and regunit lists in DiffLists.
/// Don't use this class directly, use one of the specialized sub-classes
/// defined below.
class DiffListIterator {
uint16_t Val;
const uint16_t *List;
protected:
/// Create an invalid iterator. Call init() to point to something usefu
l.
DiffListIterator() : Val(0), List(0) {}
/// init - Point the iterator to InitVal, decoding subsequent values fr
om
/// DiffList. The iterator will initially point to InitVal, sub-classes
are
/// responsible for skipping the seed value if it is not part of the li
st.
void init(uint16_t InitVal, const uint16_t *DiffList) {
Val = InitVal;
List = DiffList;
}
/// advance - Move to the next list position, return the applied
/// differential. This function does not detect the end of the list, th
at
/// is the caller's responsibility (by checking for a 0 return value).
unsigned advance() {
assert(isValid() && "Cannot move off the end of the list.");
uint16_t D = *List++;
Val += D;
return D;
}
public:
/// isValid - returns true if this iterator is not yet at the end.
bool isValid() const { return List; }
/// Dereference the iterator to get the value at the current position.
unsigned operator*() const { return Val; }
/// Pre-increment to move to the next position.
void operator++() {
// The end of the list is encoded as a 0 differential.
if (!advance())
List = 0;
}
};
// These iterators are allowed to sub-class DiffListIterator and access
// internal list pointers.
friend class MCSubRegIterator;
friend class MCSuperRegIterator;
friend class MCRegAliasIterator;
friend class MCRegUnitIterator;
friend class MCRegUnitRootIterator;
/// InitMCRegisterInfo - Initialize MCRegisterInfo, called by TableGen /// InitMCRegisterInfo - Initialize MCRegisterInfo, called by TableGen
/// auto-generated routines. *DO NOT USE*. /// auto-generated routines. *DO NOT USE*.
void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA , void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA ,
const MCRegisterClass *C, unsigned NC, const MCRegisterClass *C, unsigned NC,
const uint16_t *RL, const uint16_t (*RURoots)[2],
unsigned NRU,
const uint16_t *DL,
const char *Strings,
const uint16_t *SubIndices, const uint16_t *SubIndices,
unsigned NumIndices) { unsigned NumIndices,
const uint16_t *RET) {
Desc = D; Desc = D;
NumRegs = NR; NumRegs = NR;
RAReg = RA; RAReg = RA;
Classes = C; Classes = C;
RegLists = RL; DiffLists = DL;
RegStrings = Strings;
NumClasses = NC; NumClasses = NC;
RegUnitRoots = RURoots;
NumRegUnits = NRU;
SubRegIndices = SubIndices; SubRegIndices = SubIndices;
NumSubRegIndices = NumIndices; NumSubRegIndices = NumIndices;
RegEncodingTable = RET;
} }
/// mapLLVMRegsToDwarfRegs - Used to initialize LLVM register to Dwarf /// mapLLVMRegsToDwarfRegs - Used to initialize LLVM register to Dwarf
/// register number mapping. Called by TableGen auto-generated routines. /// register number mapping. Called by TableGen auto-generated routines.
/// *DO NOT USE*. /// *DO NOT USE*.
void mapLLVMRegsToDwarfRegs(const DwarfLLVMRegPair *Map, unsigned Size, void mapLLVMRegsToDwarfRegs(const DwarfLLVMRegPair *Map, unsigned Size,
bool isEH) { bool isEH) {
if (isEH) { if (isEH) {
EHL2DwarfRegs = Map; EHL2DwarfRegs = Map;
EHL2DwarfRegsSize = Size; EHL2DwarfRegsSize = Size;
skipping to change at line 234 skipping to change at line 309
return Desc[RegNo]; return Desc[RegNo];
} }
/// Provide a get method, equivalent to [], but more useful if we have a /// Provide a get method, equivalent to [], but more useful if we have a
/// pointer to this object. /// pointer to this object.
/// ///
const MCRegisterDesc &get(unsigned RegNo) const { const MCRegisterDesc &get(unsigned RegNo) const {
return operator[](RegNo); return operator[](RegNo);
} }
/// getAliasSet - Return the set of registers aliased by the specified
/// register, or a null list of there are none. The list returned is zer
o
/// terminated.
///
const uint16_t *getAliasSet(unsigned RegNo) const {
// The Overlaps set always begins with Reg itself.
return RegLists + get(RegNo).Overlaps + 1;
}
/// getOverlaps - Return a list of registers that overlap Reg, including
/// itself. This is the same as the alias set except Reg is included in t
he
/// list.
/// These are exactly the registers in { x | regsOverlap(x, Reg) }.
///
const uint16_t *getOverlaps(unsigned RegNo) const {
return RegLists + get(RegNo).Overlaps;
}
/// getSubRegisters - Return the list of registers that are sub-registers
of
/// the specified register, or a null list of there are none. The list
/// returned is zero terminated and sorted according to super-sub registe
r
/// relations. e.g. X86::RAX's sub-register list is EAX, AX, AL, AH.
///
const uint16_t *getSubRegisters(unsigned RegNo) const {
return RegLists + get(RegNo).SubRegs;
}
/// getSubReg - Returns the physical register number of sub-register "Ind ex" /// getSubReg - Returns the physical register number of sub-register "Ind ex"
/// for physical register RegNo. Return zero if the sub-register does not /// for physical register RegNo. Return zero if the sub-register does not
/// exist. /// exist.
unsigned getSubReg(unsigned Reg, unsigned Idx) const { unsigned getSubReg(unsigned Reg, unsigned Idx) const;
return *(SubRegIndices + (Reg - 1) * NumSubRegIndices + Idx - 1);
}
/// getMatchingSuperReg - Return a super-register of the specified regist er /// getMatchingSuperReg - Return a super-register of the specified regist er
/// Reg so its sub-register of index SubIdx is Reg. /// Reg so its sub-register of index SubIdx is Reg.
unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
const MCRegisterClass *RC) const { const MCRegisterClass *RC) const;
for (const uint16_t *SRs = getSuperRegisters(Reg); unsigned SR = *SRs;+
+SRs)
if (Reg == getSubReg(SR, SubIdx) && RC->contains(SR))
return SR;
return 0;
}
/// getSubRegIndex - For a given register pair, return the sub-register i ndex /// getSubRegIndex - For a given register pair, return the sub-register i ndex
/// if the second register is a sub-register of the first. Return zero /// if the second register is a sub-register of the first. Return zero
/// otherwise. /// otherwise.
unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const { unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const;
for (unsigned I = 1; I <= NumSubRegIndices; ++I)
if (getSubReg(RegNo, I) == SubRegNo)
return I;
return 0;
}
/// getSuperRegisters - Return the list of registers that are super-regis
ters
/// of the specified register, or a null list of there are none. The list
/// returned is zero terminated and sorted according to super-sub registe
r
/// relations. e.g. X86::AL's super-register list is AX, EAX, RAX.
///
const uint16_t *getSuperRegisters(unsigned RegNo) const {
return RegLists + get(RegNo).SuperRegs;
}
/// getName - Return the human-readable symbolic target-specific name for the /// getName - Return the human-readable symbolic target-specific name for the
/// specified physical register. /// specified physical register.
const char *getName(unsigned RegNo) const { const char *getName(unsigned RegNo) const {
return get(RegNo).Name; return RegStrings + get(RegNo).Name;
} }
/// getNumRegs - Return the number of registers this target has (useful f or /// getNumRegs - Return the number of registers this target has (useful f or
/// sizing arrays holding per register information) /// sizing arrays holding per register information)
unsigned getNumRegs() const { unsigned getNumRegs() const {
return NumRegs; return NumRegs;
} }
/// getNumSubRegIndices - Return the number of sub-register indices
/// understood by the target. Index 0 is reserved for the no-op sub-regis
ter,
/// while 1 to getNumSubRegIndices() - 1 represent real sub-registers.
unsigned getNumSubRegIndices() const {
return NumSubRegIndices;
}
/// getNumRegUnits - Return the number of (native) register units in the
/// target. Register units are numbered from 0 to getNumRegUnits() - 1. T
hey
/// can be accessed through MCRegUnitIterator defined below.
unsigned getNumRegUnits() const {
return NumRegUnits;
}
/// getDwarfRegNum - Map a target register to an equivalent dwarf registe r /// getDwarfRegNum - Map a target register to an equivalent dwarf registe r
/// number. Returns -1 if there is no equivalent value. The second /// number. Returns -1 if there is no equivalent value. The second
/// parameter allows targets to use different numberings for EH info and /// parameter allows targets to use different numberings for EH info and
/// debugging info. /// debugging info.
int getDwarfRegNum(unsigned RegNum, bool isEH) const { int getDwarfRegNum(unsigned RegNum, bool isEH) const;
const DwarfLLVMRegPair *M = isEH ? EHL2DwarfRegs : L2DwarfRegs;
unsigned Size = isEH ? EHL2DwarfRegsSize : L2DwarfRegsSize;
DwarfLLVMRegPair Key = { RegNum, 0 };
const DwarfLLVMRegPair *I = std::lower_bound(M, M+Size, Key);
if (I == M+Size || I->FromReg != RegNum)
return -1;
return I->ToReg;
}
/// getLLVMRegNum - Map a dwarf register back to a target register. /// getLLVMRegNum - Map a dwarf register back to a target register.
/// ///
int getLLVMRegNum(unsigned RegNum, bool isEH) const { int getLLVMRegNum(unsigned RegNum, bool isEH) const;
const DwarfLLVMRegPair *M = isEH ? EHDwarf2LRegs : Dwarf2LRegs;
unsigned Size = isEH ? EHDwarf2LRegsSize : Dwarf2LRegsSize;
DwarfLLVMRegPair Key = { RegNum, 0 };
const DwarfLLVMRegPair *I = std::lower_bound(M, M+Size, Key);
assert(I != M+Size && I->FromReg == RegNum && "Invalid RegNum");
return I->ToReg;
}
/// getSEHRegNum - Map a target register to an equivalent SEH register /// getSEHRegNum - Map a target register to an equivalent SEH register
/// number. Returns LLVM register number if there is no equivalent value . /// number. Returns LLVM register number if there is no equivalent value .
int getSEHRegNum(unsigned RegNum) const { int getSEHRegNum(unsigned RegNum) const;
const DenseMap<unsigned, int>::const_iterator I = L2SEHRegs.find(RegNum
);
if (I == L2SEHRegs.end()) return (int)RegNum;
return I->second;
}
regclass_iterator regclass_begin() const { return Classes; } regclass_iterator regclass_begin() const { return Classes; }
regclass_iterator regclass_end() const { return Classes+NumClasses; } regclass_iterator regclass_end() const { return Classes+NumClasses; }
unsigned getNumRegClasses() const { unsigned getNumRegClasses() const {
return (unsigned)(regclass_end()-regclass_begin()); return (unsigned)(regclass_end()-regclass_begin());
} }
/// getRegClass - Returns the register class associated with the enumerat ion /// getRegClass - Returns the register class associated with the enumerat ion
/// value. See class MCOperandInfo. /// value. See class MCOperandInfo.
const MCRegisterClass getRegClass(unsigned i) const { const MCRegisterClass& getRegClass(unsigned i) const {
assert(i < getNumRegClasses() && "Register Class ID out of range"); assert(i < getNumRegClasses() && "Register Class ID out of range");
return Classes[i]; return Classes[i];
} }
/// getEncodingValue - Returns the encoding for RegNo
uint16_t getEncodingValue(unsigned RegNo) const {
assert(RegNo < NumRegs &&
"Attempting to get encoding for invalid register number!");
return RegEncodingTable[RegNo];
}
};
//===----------------------------------------------------------------------
===//
// Register List Iterators
//===----------------------------------------------------------------------
===//
// MCRegisterInfo provides lists of super-registers, sub-registers, and
// aliasing registers. Use these iterator classes to traverse the lists.
/// MCSubRegIterator enumerates all sub-registers of Reg.
class MCSubRegIterator : public MCRegisterInfo::DiffListIterator {
public:
MCSubRegIterator(unsigned Reg, const MCRegisterInfo *MCRI) {
init(Reg, MCRI->DiffLists + MCRI->get(Reg).SubRegs);
++*this;
}
};
/// MCSuperRegIterator enumerates all super-registers of Reg.
class MCSuperRegIterator : public MCRegisterInfo::DiffListIterator {
public:
MCSuperRegIterator(unsigned Reg, const MCRegisterInfo *MCRI) {
init(Reg, MCRI->DiffLists + MCRI->get(Reg).SuperRegs);
++*this;
}
};
/// MCRegAliasIterator enumerates all registers aliasing Reg.
/// If IncludeSelf is set, Reg itself is included in the list.
class MCRegAliasIterator : public MCRegisterInfo::DiffListIterator {
public:
MCRegAliasIterator(unsigned Reg, const MCRegisterInfo *MCRI,
bool IncludeSelf) {
init(Reg, MCRI->DiffLists + MCRI->get(Reg).Overlaps);
// Initially, the iterator points to Reg itself.
if (!IncludeSelf)
++*this;
}
};
//===----------------------------------------------------------------------
===//
// Register Units
//===----------------------------------------------------------------------
===//
// Register units are used to compute register aliasing. Every register has
at
// least one register unit, but it can have more. Two registers overlap if
and
// only if they have a common register unit.
//
// A target with a complicated sub-register structure will typically have m
any
// fewer register units than actual registers. MCRI::getNumRegUnits() retur
ns
// the number of register units in the target.
// MCRegUnitIterator enumerates a list of register units for Reg. The list
is
// in ascending numerical order.
class MCRegUnitIterator : public MCRegisterInfo::DiffListIterator {
public:
/// MCRegUnitIterator - Create an iterator that traverses the register un
its
/// in Reg.
MCRegUnitIterator(unsigned Reg, const MCRegisterInfo *MCRI) {
// Decode the RegUnits MCRegisterDesc field.
unsigned RU = MCRI->get(Reg).RegUnits;
unsigned Scale = RU & 15;
unsigned Offset = RU >> 4;
// Initialize the iterator to Reg * Scale, and the List pointer to
// DiffLists + Offset.
init(Reg * Scale, MCRI->DiffLists + Offset);
// That may not be a valid unit, we need to advance by one to get the r
eal
// unit number. The first differential can be 0 which would normally
// terminate the list, but since we know every register has at least on
e
// unit, we can allow a 0 differential here.
advance();
}
};
// Each register unit has one or two root registers. The complete set of
// registers containing a register unit is the union of the roots and their
// super-registers. All registers aliasing Unit can be visited like this:
//
// for (MCRegUnitRootIterator RI(Unit, MCRI); RI.isValid(); ++RI) {
// unsigned Root = *RI;
// visit(Root);
// for (MCSuperRegIterator SI(Root, MCRI); SI.isValid(); ++SI)
// visit(*SI);
// }
/// MCRegUnitRootIterator enumerates the root registers of a register unit.
class MCRegUnitRootIterator {
uint16_t Reg0;
uint16_t Reg1;
public:
MCRegUnitRootIterator(unsigned RegUnit, const MCRegisterInfo *MCRI) {
assert(RegUnit < MCRI->getNumRegUnits() && "Invalid register unit");
Reg0 = MCRI->RegUnitRoots[RegUnit][0];
Reg1 = MCRI->RegUnitRoots[RegUnit][1];
}
/// Dereference to get the current root register.
unsigned operator*() const {
return Reg0;
}
/// isValid - Check if the iterator is at the end of the list.
bool isValid() const {
return Reg0;
}
/// Preincrement to move to the next root register.
void operator++() {
assert(isValid() && "Cannot move off the end of the list.");
Reg0 = Reg1;
Reg1 = 0;
}
}; };
} // End llvm namespace } // End llvm namespace
#endif #endif
 End of changes. 20 change blocks. 
94 lines changed or deleted 253 lines changed or added


 MCSection.h   MCSection.h 
skipping to change at line 18 skipping to change at line 18
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// //
// This file declares the MCSection class. // This file declares the MCSection class.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_MC_MCSECTION_H #ifndef LLVM_MC_MCSECTION_H
#define LLVM_MC_MCSECTION_H #define LLVM_MC_MCSECTION_H
#include "llvm/MC/SectionKind.h" #include "llvm/MC/SectionKind.h"
#include "llvm/Support/Casting.h" #include "llvm/Support/Compiler.h"
namespace llvm { namespace llvm {
class MCAsmInfo; class MCAsmInfo;
class raw_ostream; class raw_ostream;
/// MCSection - Instances of this class represent a uniqued identifier fo r a /// MCSection - Instances of this class represent a uniqued identifier fo r a
/// section in the current translation unit. The MCContext class uniques and /// section in the current translation unit. The MCContext class uniques and
/// creates these. /// creates these.
class MCSection { class MCSection {
public: public:
enum SectionVariant { enum SectionVariant {
SV_COFF = 0, SV_COFF = 0,
SV_ELF, SV_ELF,
SV_MachO SV_MachO
}; };
private: private:
MCSection(const MCSection&); // DO NOT IMPLEMENT MCSection(const MCSection&) LLVM_DELETED_FUNCTION;
void operator=(const MCSection&); // DO NOT IMPLEMENT void operator=(const MCSection&) LLVM_DELETED_FUNCTION;
protected: protected:
MCSection(SectionVariant V, SectionKind K) : Variant(V), Kind(K) {} MCSection(SectionVariant V, SectionKind K) : Variant(V), Kind(K) {}
SectionVariant Variant; SectionVariant Variant;
SectionKind Kind; SectionKind Kind;
public: public:
virtual ~MCSection(); virtual ~MCSection();
SectionKind getKind() const { return Kind; } SectionKind getKind() const { return Kind; }
SectionVariant getVariant() const { return Variant; } SectionVariant getVariant() const { return Variant; }
skipping to change at line 67 skipping to change at line 67
return false; return false;
} }
// UseCodeAlign - Return true if a .align directive should use // UseCodeAlign - Return true if a .align directive should use
// "optimized nops" to fill instead of 0s. // "optimized nops" to fill instead of 0s.
virtual bool UseCodeAlign() const = 0; virtual bool UseCodeAlign() const = 0;
/// isVirtualSection - Check whether this section is "virtual", that is /// isVirtualSection - Check whether this section is "virtual", that is
/// has no actual object file contents. /// has no actual object file contents.
virtual bool isVirtualSection() const = 0; virtual bool isVirtualSection() const = 0;
static bool classof(const MCSection *) { return true; }
}; };
} // end namespace llvm } // end namespace llvm
#endif #endif
 End of changes. 3 change blocks. 
5 lines changed or deleted 3 lines changed or added


 MCSectionCOFF.h   MCSectionCOFF.h 
skipping to change at line 64 skipping to change at line 64
int getSelection () const { return Selection; } int getSelection () const { return Selection; }
virtual void PrintSwitchToSection(const MCAsmInfo &MAI, virtual void PrintSwitchToSection(const MCAsmInfo &MAI,
raw_ostream &OS) const; raw_ostream &OS) const;
virtual bool UseCodeAlign() const; virtual bool UseCodeAlign() const;
virtual bool isVirtualSection() const; virtual bool isVirtualSection() const;
static bool classof(const MCSection *S) { static bool classof(const MCSection *S) {
return S->getVariant() == SV_COFF; return S->getVariant() == SV_COFF;
} }
static bool classof(const MCSectionCOFF *) { return true; }
}; };
} // end namespace llvm } // end namespace llvm
#endif #endif
 End of changes. 1 change blocks. 
1 lines changed or deleted 0 lines changed or added


 MCSectionELF.h   MCSectionELF.h 
skipping to change at line 79 skipping to change at line 79
/// isBaseAddressKnownZero - We know that non-allocatable sections (like /// isBaseAddressKnownZero - We know that non-allocatable sections (like
/// debug info) have a base of zero. /// debug info) have a base of zero.
virtual bool isBaseAddressKnownZero() const { virtual bool isBaseAddressKnownZero() const {
return (getFlags() & ELF::SHF_ALLOC) == 0; return (getFlags() & ELF::SHF_ALLOC) == 0;
} }
static bool classof(const MCSection *S) { static bool classof(const MCSection *S) {
return S->getVariant() == SV_ELF; return S->getVariant() == SV_ELF;
} }
static bool classof(const MCSectionELF *) { return true; }
// Return the entry size for sections with fixed-width data. // Return the entry size for sections with fixed-width data.
static unsigned DetermineEntrySize(SectionKind Kind); static unsigned DetermineEntrySize(SectionKind Kind);
}; };
} // end namespace llvm } // end namespace llvm
#endif #endif
 End of changes. 1 change blocks. 
1 lines changed or deleted 0 lines changed or added


 MCSectionMachO.h   MCSectionMachO.h 
skipping to change at line 176 skipping to change at line 176
unsigned &StubSize); // Out. unsigned &StubSize); // Out.
virtual void PrintSwitchToSection(const MCAsmInfo &MAI, virtual void PrintSwitchToSection(const MCAsmInfo &MAI,
raw_ostream &OS) const; raw_ostream &OS) const;
virtual bool UseCodeAlign() const; virtual bool UseCodeAlign() const;
virtual bool isVirtualSection() const; virtual bool isVirtualSection() const;
static bool classof(const MCSection *S) { static bool classof(const MCSection *S) {
return S->getVariant() == SV_MachO; return S->getVariant() == SV_MachO;
} }
static bool classof(const MCSectionMachO *) { return true; }
}; };
} // end namespace llvm } // end namespace llvm
#endif #endif
 End of changes. 1 change blocks. 
1 lines changed or deleted 0 lines changed or added


 MCStreamer.h   MCStreamer.h 
skipping to change at line 50 skipping to change at line 50
/// level that an assembler .s file provides. It has callbacks to emit b ytes, /// level that an assembler .s file provides. It has callbacks to emit b ytes,
/// handle directives, etc. The implementation of this interface retains /// handle directives, etc. The implementation of this interface retains
/// state to know what the current section is etc. /// state to know what the current section is etc.
/// ///
/// There are multiple implementations of this interface: one for writing out /// There are multiple implementations of this interface: one for writing out
/// a .s file, and implementations that write out .o files of various for mats. /// a .s file, and implementations that write out .o files of various for mats.
/// ///
class MCStreamer { class MCStreamer {
MCContext &Context; MCContext &Context;
MCStreamer(const MCStreamer&); // DO NOT IMPLEMENT MCStreamer(const MCStreamer&) LLVM_DELETED_FUNCTION;
MCStreamer &operator=(const MCStreamer&); // DO NOT IMPLEMENT MCStreamer &operator=(const MCStreamer&) LLVM_DELETED_FUNCTION;
bool EmitEHFrame; bool EmitEHFrame;
bool EmitDebugFrame; bool EmitDebugFrame;
std::vector<MCDwarfFrameInfo> FrameInfos; std::vector<MCDwarfFrameInfo> FrameInfos;
MCDwarfFrameInfo *getCurrentFrameInfo(); MCDwarfFrameInfo *getCurrentFrameInfo();
void EnsureValidFrame(); void EnsureValidFrame();
std::vector<MCWin64EHUnwindInfo *> W64UnwindInfos; std::vector<MCWin64EHUnwindInfo *> W64UnwindInfos;
MCWin64EHUnwindInfo *CurrentW64UnwindInfo; MCWin64EHUnwindInfo *CurrentW64UnwindInfo;
void setCurrentW64UnwindInfo(MCWin64EHUnwindInfo *Frame); void setCurrentW64UnwindInfo(MCWin64EHUnwindInfo *Frame);
void EnsureValidW64UnwindInfo(); void EnsureValidW64UnwindInfo();
MCSymbol* LastSymbol; MCSymbol* LastSymbol;
/// SectionStack - This is stack of current and previous section /// SectionStack - This is stack of current and previous section
/// values saved by PushSection. /// values saved by PushSection.
SmallVector<std::pair<const MCSection *, SmallVector<std::pair<const MCSection *,
const MCSection *>, 4> SectionStack; const MCSection *>, 4> SectionStack;
unsigned UniqueCodeBeginSuffix;
unsigned UniqueDataBeginSuffix;
protected: protected:
/// Indicator of whether the previous data-or-code indicator was for
/// code or not. Used to determine when we need to emit a new indicato
r.
enum DataType {
Data,
Code,
JumpTable8,
JumpTable16,
JumpTable32
};
DataType RegionIndicator;
MCStreamer(MCContext &Ctx); MCStreamer(MCContext &Ctx);
const MCExpr *BuildSymbolDiff(MCContext &Context, const MCSymbol *A, const MCExpr *BuildSymbolDiff(MCContext &Context, const MCSymbol *A,
const MCSymbol *B); const MCSymbol *B);
const MCExpr *ForceExpAbs(const MCExpr* Expr); const MCExpr *ForceExpAbs(const MCExpr* Expr);
void RecordProcStart(MCDwarfFrameInfo &Frame); void RecordProcStart(MCDwarfFrameInfo &Frame);
virtual void EmitCFIStartProcImpl(MCDwarfFrameInfo &Frame); virtual void EmitCFIStartProcImpl(MCDwarfFrameInfo &Frame);
void RecordProcEnd(MCDwarfFrameInfo &Frame); void RecordProcEnd(MCDwarfFrameInfo &Frame);
skipping to change at line 243 skipping to change at line 229
/// EmitLabel - Emit a label for @p Symbol into the current section. /// EmitLabel - Emit a label for @p Symbol into the current section.
/// ///
/// This corresponds to an assembler statement such as: /// This corresponds to an assembler statement such as:
/// foo: /// foo:
/// ///
/// @param Symbol - The symbol to emit. A given symbol should only be /// @param Symbol - The symbol to emit. A given symbol should only be
/// emitted as a label once, and symbols emitted as a label should neve r be /// emitted as a label once, and symbols emitted as a label should neve r be
/// used in an assignment. /// used in an assignment.
virtual void EmitLabel(MCSymbol *Symbol); virtual void EmitLabel(MCSymbol *Symbol);
/// EmitDataRegion - Emit a label that marks the beginning of a data
/// region.
/// On ELF targets, this corresponds to an assembler statement such as:
/// $d.1:
virtual void EmitDataRegion();
/// EmitJumpTable8Region - Emit a label that marks the beginning of a
/// jump table composed of 8-bit offsets.
/// On ELF targets, this corresponds to an assembler statement such as:
/// $d.1:
virtual void EmitJumpTable8Region();
/// EmitJumpTable16Region - Emit a label that marks the beginning of a
/// jump table composed of 16-bit offsets.
/// On ELF targets, this corresponds to an assembler statement such as:
/// $d.1:
virtual void EmitJumpTable16Region();
/// EmitJumpTable32Region - Emit a label that marks the beginning of a
/// jump table composed of 32-bit offsets.
/// On ELF targets, this corresponds to an assembler statement such as:
/// $d.1:
virtual void EmitJumpTable32Region();
/// EmitCodeRegion - Emit a label that marks the beginning of a code
/// region.
/// On ELF targets, this corresponds to an assembler statement such as:
/// $a.1:
virtual void EmitCodeRegion();
/// ForceCodeRegion - Forcibly sets the current region mode to code. U
sed
/// at function entry points.
void ForceCodeRegion() { RegionIndicator = Code; }
virtual void EmitEHSymAttributes(const MCSymbol *Symbol, virtual void EmitEHSymAttributes(const MCSymbol *Symbol,
MCSymbol *EHSymbol); MCSymbol *EHSymbol);
/// EmitAssemblerFlag - Note in the output the specified @p Flag /// EmitAssemblerFlag - Note in the output the specified @p Flag.
virtual void EmitAssemblerFlag(MCAssemblerFlag Flag) = 0; virtual void EmitAssemblerFlag(MCAssemblerFlag Flag) = 0;
/// EmitDataRegion - Note in the output the specified region @p Kind.
virtual void EmitDataRegion(MCDataRegionType Kind) {}
/// EmitThumbFunc - Note in the output that the specified @p Func is /// EmitThumbFunc - Note in the output that the specified @p Func is
/// a Thumb mode function (ARM target only). /// a Thumb mode function (ARM target only).
virtual void EmitThumbFunc(MCSymbol *Func) = 0; virtual void EmitThumbFunc(MCSymbol *Func) = 0;
/// EmitAssignment - Emit an assignment of @p Value to @p Symbol. /// EmitAssignment - Emit an assignment of @p Value to @p Symbol.
/// ///
/// This corresponds to an assembler statement such as: /// This corresponds to an assembler statement such as:
/// symbol = value /// symbol = value
/// ///
/// The assignment generates no code, but has the side effect of bindin g the /// The assignment generates no code, but has the side effect of bindin g the
skipping to change at line 374 skipping to change at line 329
unsigned ByteAlignment) = 0; unsigned ByteAlignment) = 0;
/// EmitZerofill - Emit the zerofill section and an optional symbol. /// EmitZerofill - Emit the zerofill section and an optional symbol.
/// ///
/// @param Section - The zerofill section to create and or to put the s ymbol /// @param Section - The zerofill section to create and or to put the s ymbol
/// @param Symbol - The zerofill symbol to emit, if non-NULL. /// @param Symbol - The zerofill symbol to emit, if non-NULL.
/// @param Size - The size of the zerofill symbol. /// @param Size - The size of the zerofill symbol.
/// @param ByteAlignment - The alignment of the zerofill symbol if /// @param ByteAlignment - The alignment of the zerofill symbol if
/// non-zero. This must be a power of 2 on some targets. /// non-zero. This must be a power of 2 on some targets.
virtual void EmitZerofill(const MCSection *Section, MCSymbol *Symbol = 0, virtual void EmitZerofill(const MCSection *Section, MCSymbol *Symbol = 0,
unsigned Size = 0,unsigned ByteAlignment = 0) = 0; uint64_t Size = 0,unsigned ByteAlignment = 0) = 0;
/// EmitTBSSSymbol - Emit a thread local bss (.tbss) symbol. /// EmitTBSSSymbol - Emit a thread local bss (.tbss) symbol.
/// ///
/// @param Section - The thread local common section. /// @param Section - The thread local common section.
/// @param Symbol - The thread local common symbol to emit. /// @param Symbol - The thread local common symbol to emit.
/// @param Size - The size of the symbol. /// @param Size - The size of the symbol.
/// @param ByteAlignment - The alignment of the thread local common sym bol /// @param ByteAlignment - The alignment of the thread local common sym bol
/// if non-zero. This must be a power of 2 on some targets. /// if non-zero. This must be a power of 2 on some targets.
virtual void EmitTBSSSymbol(const MCSection *Section, MCSymbol *Symbol, virtual void EmitTBSSSymbol(const MCSection *Section, MCSymbol *Symbol,
uint64_t Size, unsigned ByteAlignment = 0) = 0; uint64_t Size, unsigned ByteAlignment = 0) = 0;
/// @} /// @}
/// @name Generating Data /// @name Generating Data
/// @{ /// @{
/// EmitBytes - Emit the bytes in \arg Data into the output. /// EmitBytes - Emit the bytes in \p Data into the output.
/// ///
/// This is used to implement assembler directives such as .byte, .asci i, /// This is used to implement assembler directives such as .byte, .asci i,
/// etc. /// etc.
virtual void EmitBytes(StringRef Data, unsigned AddrSpace) = 0; virtual void EmitBytes(StringRef Data, unsigned AddrSpace) = 0;
/// EmitValue - Emit the expression @p Value into the output as a nativ e /// EmitValue - Emit the expression @p Value into the output as a nativ e
/// integer of the given @p Size bytes. /// integer of the given @p Size bytes.
/// ///
/// This is used to implement assembler directives such as .word, .quad , /// This is used to implement assembler directives such as .word, .quad ,
/// etc. /// etc.
skipping to change at line 601 skipping to change at line 556
virtual void EmitFnStart(); virtual void EmitFnStart();
virtual void EmitFnEnd(); virtual void EmitFnEnd();
virtual void EmitCantUnwind(); virtual void EmitCantUnwind();
virtual void EmitPersonality(const MCSymbol *Personality); virtual void EmitPersonality(const MCSymbol *Personality);
virtual void EmitHandlerData(); virtual void EmitHandlerData();
virtual void EmitSetFP(unsigned FpReg, unsigned SpReg, int64_t Offset = 0); virtual void EmitSetFP(unsigned FpReg, unsigned SpReg, int64_t Offset = 0);
virtual void EmitPad(int64_t Offset); virtual void EmitPad(int64_t Offset);
virtual void EmitRegSave(const SmallVectorImpl<unsigned> &RegList, virtual void EmitRegSave(const SmallVectorImpl<unsigned> &RegList,
bool isVector); bool isVector);
/// PPC-related methods.
/// FIXME: Eventually replace it with some "target MC streamer" and mov
e
/// these methods there.
virtual void EmitTCEntry(const MCSymbol &S);
/// FinishImpl - Streamer specific finalization. /// FinishImpl - Streamer specific finalization.
virtual void FinishImpl() = 0; virtual void FinishImpl() = 0;
/// Finish - Finish emission of machine code. /// Finish - Finish emission of machine code.
void Finish(); void Finish();
}; };
/// createNullStreamer - Create a dummy machine code streamer, which does /// createNullStreamer - Create a dummy machine code streamer, which does
/// nothing. This is useful for timing the assembler front end. /// nothing. This is useful for timing the assembler front end.
MCStreamer *createNullStreamer(MCContext &Ctx); MCStreamer *createNullStreamer(MCContext &Ctx);
/// createAsmStreamer - Create a machine code streamer which will print o ut /// createAsmStreamer - Create a machine code streamer which will print o ut
/// assembly for the native target, suitable for compiling with a native /// assembly for the native target, suitable for compiling with a native
/// assembler. /// assembler.
/// ///
/// \param InstPrint - If given, the instruction printer to use. If not g iven /// \param InstPrint - If given, the instruction printer to use. If not g iven
/// the MCInst representation will be printed. This method takes ownersh ip of /// the MCInst representation will be printed. This method takes ownersh ip of
/// InstPrint. /// InstPrint.
/// ///
/// \param CE - If given, a code emitter to use to show the instruction /// \param CE - If given, a code emitter to use to show the instruction
/// encoding inline with the assembly. This method takes ownership of \ar g CE. /// encoding inline with the assembly. This method takes ownership of \p CE.
/// ///
/// \param TAB - If given, a target asm backend to use to show the fixup /// \param TAB - If given, a target asm backend to use to show the fixup
/// information in conjunction with encoding information. This method tak es /// information in conjunction with encoding information. This method tak es
/// ownership of \arg TAB. /// ownership of \p TAB.
/// ///
/// \param ShowInst - Whether to show the MCInst representation inline wi th /// \param ShowInst - Whether to show the MCInst representation inline wi th
/// the assembly. /// the assembly.
///
/// \param DecodeLSDA - If true, emit comments that translates the LSDA i
nto a
/// human readable format. Only usable with CFI.
MCStreamer *createAsmStreamer(MCContext &Ctx, formatted_raw_ostream &OS, MCStreamer *createAsmStreamer(MCContext &Ctx, formatted_raw_ostream &OS,
bool isVerboseAsm, bool isVerboseAsm,
bool useLoc, bool useLoc,
bool useCFI, bool useCFI,
bool useDwarfDirectory, bool useDwarfDirectory,
MCInstPrinter *InstPrint = 0, MCInstPrinter *InstPrint = 0,
MCCodeEmitter *CE = 0, MCCodeEmitter *CE = 0,
MCAsmBackend *TAB = 0, MCAsmBackend *TAB = 0,
bool ShowInst = false); bool ShowInst = false);
/// createMachOStreamer - Create a machine code streamer which will gener ate /// createMachOStreamer - Create a machine code streamer which will gener ate
/// Mach-O format object files. /// Mach-O format object files.
/// ///
/// Takes ownership of \arg TAB and \arg CE. /// Takes ownership of \p TAB and \p CE.
MCStreamer *createMachOStreamer(MCContext &Ctx, MCAsmBackend &TAB, MCStreamer *createMachOStreamer(MCContext &Ctx, MCAsmBackend &TAB,
raw_ostream &OS, MCCodeEmitter *CE, raw_ostream &OS, MCCodeEmitter *CE,
bool RelaxAll = false); bool RelaxAll = false);
/// createWinCOFFStreamer - Create a machine code streamer which will /// createWinCOFFStreamer - Create a machine code streamer which will
/// generate Microsoft COFF format object files. /// generate Microsoft COFF format object files.
/// ///
/// Takes ownership of \arg TAB and \arg CE. /// Takes ownership of \p TAB and \p CE.
MCStreamer *createWinCOFFStreamer(MCContext &Ctx, MCStreamer *createWinCOFFStreamer(MCContext &Ctx,
MCAsmBackend &TAB, MCAsmBackend &TAB,
MCCodeEmitter &CE, raw_ostream &OS, MCCodeEmitter &CE, raw_ostream &OS,
bool RelaxAll = false); bool RelaxAll = false);
/// createELFStreamer - Create a machine code streamer which will generat e /// createELFStreamer - Create a machine code streamer which will generat e
/// ELF format object files. /// ELF format object files.
MCStreamer *createELFStreamer(MCContext &Ctx, MCAsmBackend &TAB, MCStreamer *createELFStreamer(MCContext &Ctx, MCAsmBackend &TAB,
raw_ostream &OS, MCCodeEmitter *CE, raw_ostream &OS, MCCodeEmitter *CE,
bool RelaxAll, bool NoExecStack); bool RelaxAll, bool NoExecStack);
/// createPureStreamer - Create a machine code streamer which will genera te /// createPureStreamer - Create a machine code streamer which will genera te
/// "pure" MC object files, for use with MC-JIT and testing tools. /// "pure" MC object files, for use with MC-JIT and testing tools.
/// ///
/// Takes ownership of \arg TAB and \arg CE. /// Takes ownership of \p TAB and \p CE.
MCStreamer *createPureStreamer(MCContext &Ctx, MCAsmBackend &TAB, MCStreamer *createPureStreamer(MCContext &Ctx, MCAsmBackend &TAB,
raw_ostream &OS, MCCodeEmitter *CE); raw_ostream &OS, MCCodeEmitter *CE);
} // end namespace llvm } // end namespace llvm
#endif #endif
 End of changes. 15 change blocks. 
64 lines changed or deleted 19 lines changed or added


 MCSubtargetInfo.h   MCSubtargetInfo.h 
skipping to change at line 33 skipping to change at line 33
class StringRef; class StringRef;
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
/// ///
/// MCSubtargetInfo - Generic base class for all target subtargets. /// MCSubtargetInfo - Generic base class for all target subtargets.
/// ///
class MCSubtargetInfo { class MCSubtargetInfo {
std::string TargetTriple; // Target triple std::string TargetTriple; // Target triple
const SubtargetFeatureKV *ProcFeatures; // Processor feature list const SubtargetFeatureKV *ProcFeatures; // Processor feature list
const SubtargetFeatureKV *ProcDesc; // Processor descriptions const SubtargetFeatureKV *ProcDesc; // Processor descriptions
const SubtargetInfoKV *ProcItins; // Scheduling itineraries
const InstrStage *Stages; // Instruction stages // Scheduler machine model
const unsigned *OperandCycles; // Operand cycles const SubtargetInfoKV *ProcSchedModels;
const unsigned *ForwardingPathes; // Forwarding pathes const MCWriteProcResEntry *WriteProcResTable;
const MCWriteLatencyEntry *WriteLatencyTable;
const MCReadAdvanceEntry *ReadAdvanceTable;
const MCSchedModel *CPUSchedModel;
const InstrStage *Stages; // Instruction itinerary stages
const unsigned *OperandCycles; // Itinerary operand cycles
const unsigned *ForwardingPaths; // Forwarding paths
unsigned NumFeatures; // Number of processor features unsigned NumFeatures; // Number of processor features
unsigned NumProcs; // Number of processors unsigned NumProcs; // Number of processors
uint64_t FeatureBits; // Feature bits for current CPU + FS uint64_t FeatureBits; // Feature bits for current CPU + FS
public: public:
void InitMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS, void InitMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS,
const SubtargetFeatureKV *PF, const SubtargetFeatureKV *PF,
const SubtargetFeatureKV *PD, const SubtargetFeatureKV *PD,
const SubtargetInfoKV *PI, const InstrStage *IS, const SubtargetInfoKV *ProcSched,
const MCWriteProcResEntry *WPR,
const MCWriteLatencyEntry *WL,
const MCReadAdvanceEntry *RA,
const InstrStage *IS,
const unsigned *OC, const unsigned *FP, const unsigned *OC, const unsigned *FP,
unsigned NF, unsigned NP); unsigned NF, unsigned NP);
/// getTargetTriple - Return the target triple string. /// getTargetTriple - Return the target triple string.
StringRef getTargetTriple() const { StringRef getTargetTriple() const {
return TargetTriple; return TargetTriple;
} }
/// getFeatureBits - Return the feature bits. /// getFeatureBits - Return the feature bits.
/// ///
uint64_t getFeatureBits() const { uint64_t getFeatureBits() const {
return FeatureBits; return FeatureBits;
} }
/// ReInitMCSubtargetInfo - Change CPU (and optionally supplemented with /// InitMCProcessorInfo - Set or change the CPU (optionally supplemented
/// feature string), recompute and return feature bits. with
uint64_t ReInitMCSubtargetInfo(StringRef CPU, StringRef FS); /// feature string). Recompute feature bits and scheduling model.
void InitMCProcessorInfo(StringRef CPU, StringRef FS);
/// ToggleFeature - Toggle a feature and returns the re-computed feature /// ToggleFeature - Toggle a feature and returns the re-computed feature
/// bits. This version does not change the implied bits. /// bits. This version does not change the implied bits.
uint64_t ToggleFeature(uint64_t FB); uint64_t ToggleFeature(uint64_t FB);
/// ToggleFeature - Toggle a feature and returns the re-computed feature /// ToggleFeature - Toggle a feature and returns the re-computed feature
/// bits. This version will also change all implied bits. /// bits. This version will also change all implied bits.
uint64_t ToggleFeature(StringRef FS); uint64_t ToggleFeature(StringRef FS);
/// getSchedModelForCPU - Get the machine model of a CPU.
///
const MCSchedModel *getSchedModelForCPU(StringRef CPU) const;
/// getSchedModel - Get the machine model for this subtarget's CPU.
///
const MCSchedModel *getSchedModel() const { return CPUSchedModel; }
/// Return an iterator at the first process resource consumed by the give
n
/// scheduling class.
const MCWriteProcResEntry *getWriteProcResBegin(
const MCSchedClassDesc *SC) const {
return &WriteProcResTable[SC->WriteProcResIdx];
}
const MCWriteProcResEntry *getWriteProcResEnd(
const MCSchedClassDesc *SC) const {
return getWriteProcResBegin(SC) + SC->NumWriteProcResEntries;
}
const MCWriteLatencyEntry *getWriteLatencyEntry(const MCSchedClassDesc *S
C,
unsigned DefIdx) const {
assert(DefIdx < SC->NumWriteLatencyEntries &&
"MachineModel does not specify a WriteResource for DefIdx");
return &WriteLatencyTable[SC->WriteLatencyIdx + DefIdx];
}
int getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx,
unsigned WriteResID) const {
// TODO: The number of read advance entries in a class can be significa
nt
// (~50). Consider compressing the WriteID into a dense ID of those tha
t are
// used by ReadAdvance and representing them as a bitset.
for (const MCReadAdvanceEntry *I = &ReadAdvanceTable[SC->ReadAdvanceIdx
],
*E = I + SC->NumReadAdvanceEntries; I != E; ++I) {
if (I->UseIdx < UseIdx)
continue;
if (I->UseIdx > UseIdx)
break;
// Find the first WriteResIdx match, which has the highest cycle coun
t.
if (!I->WriteResourceID || I->WriteResourceID == WriteResID) {
return I->Cycles;
}
}
return 0;
}
/// getInstrItineraryForCPU - Get scheduling itinerary of a CPU. /// getInstrItineraryForCPU - Get scheduling itinerary of a CPU.
/// ///
InstrItineraryData getInstrItineraryForCPU(StringRef CPU) const; InstrItineraryData getInstrItineraryForCPU(StringRef CPU) const;
/// Initialize an InstrItineraryData instance.
void initInstrItins(InstrItineraryData &InstrItins) const;
}; };
} // End llvm namespace } // End llvm namespace
#endif #endif
 End of changes. 5 change blocks. 
8 lines changed or deleted 75 lines changed or added


 MCSymbol.h   MCSymbol.h 
skipping to change at line 18 skipping to change at line 18
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// //
// This file contains the declaration of the MCSymbol class. // This file contains the declaration of the MCSymbol class.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_MC_MCSYMBOL_H #ifndef LLVM_MC_MCSYMBOL_H
#define LLVM_MC_MCSYMBOL_H #define LLVM_MC_MCSYMBOL_H
#include "llvm/ADT/StringRef.h" #include "llvm/ADT/StringRef.h"
#include "llvm/Support/Compiler.h"
namespace llvm { namespace llvm {
class MCExpr; class MCExpr;
class MCSection; class MCSection;
class MCContext; class MCContext;
class raw_ostream; class raw_ostream;
/// MCSymbol - Instances of this class represent a symbol name in the MC file, /// MCSymbol - Instances of this class represent a symbol name in the MC file,
/// and MCSymbols are created and unique'd by the MCContext class. MCSym bols /// and MCSymbols are created and unique'd by the MCContext class. MCSym bols
/// should only be constructed with valid names for the object file. /// should only be constructed with valid names for the object file.
skipping to change at line 65 skipping to change at line 66
/// IsUsed - True if this symbol has been used. /// IsUsed - True if this symbol has been used.
mutable unsigned IsUsed : 1; mutable unsigned IsUsed : 1;
private: // MCContext creates and uniques these. private: // MCContext creates and uniques these.
friend class MCExpr; friend class MCExpr;
friend class MCContext; friend class MCContext;
MCSymbol(StringRef name, bool isTemporary) MCSymbol(StringRef name, bool isTemporary)
: Name(name), Section(0), Value(0), : Name(name), Section(0), Value(0),
IsTemporary(isTemporary), IsUsed(false) {} IsTemporary(isTemporary), IsUsed(false) {}
MCSymbol(const MCSymbol&); // DO NOT IMPLEMENT MCSymbol(const MCSymbol&) LLVM_DELETED_FUNCTION;
void operator=(const MCSymbol&); // DO NOT IMPLEMENT void operator=(const MCSymbol&) LLVM_DELETED_FUNCTION;
public: public:
/// getName - Get the symbol name. /// getName - Get the symbol name.
StringRef getName() const { return Name; } StringRef getName() const { return Name; }
/// @name Accessors /// @name Accessors
/// @{ /// @{
/// isTemporary - Check if this is an assembler temporary symbol. /// isTemporary - Check if this is an assembler temporary symbol.
bool isTemporary() const { return IsTemporary; } bool isTemporary() const { return IsTemporary; }
skipping to change at line 115 skipping to change at line 116
return Section == AbsolutePseudoSection; return Section == AbsolutePseudoSection;
} }
/// getSection - Get the section associated with a defined, non-absolut e /// getSection - Get the section associated with a defined, non-absolut e
/// symbol. /// symbol.
const MCSection &getSection() const { const MCSection &getSection() const {
assert(isInSection() && "Invalid accessor!"); assert(isInSection() && "Invalid accessor!");
return *Section; return *Section;
} }
/// setSection - Mark the symbol as defined in the section \arg S. /// setSection - Mark the symbol as defined in the section \p S.
void setSection(const MCSection &S) { Section = &S; } void setSection(const MCSection &S) { Section = &S; }
/// setUndefined - Mark the symbol as undefined. /// setUndefined - Mark the symbol as undefined.
void setUndefined() { void setUndefined() {
Section = 0; Section = 0;
} }
/// setAbsolute - Mark the symbol as absolute. /// setAbsolute - Mark the symbol as absolute.
void setAbsolute() { Section = AbsolutePseudoSection; } void setAbsolute() { Section = AbsolutePseudoSection; }
/// @} /// @}
/// @name Variable Symbols /// @name Variable Symbols
/// @{ /// @{
/// isVariable - Check if this is a variable symbol. /// isVariable - Check if this is a variable symbol.
bool isVariable() const { bool isVariable() const {
return Value != 0; return Value != 0;
} }
/// getValue() - Get the value for variable symbols. /// getVariableValue() - Get the value for variable symbols.
const MCExpr *getVariableValue() const { const MCExpr *getVariableValue() const {
assert(isVariable() && "Invalid accessor!"); assert(isVariable() && "Invalid accessor!");
IsUsed = true; IsUsed = true;
return Value; return Value;
} }
// AliasedSymbol() - If this is an alias (a = b), return the symbol // AliasedSymbol() - If this is an alias (a = b), return the symbol
// we ultimately point to. For a non alias, this just returns the symbo l // we ultimately point to. For a non alias, this just returns the symbo l
// itself. // itself.
const MCSymbol &AliasedSymbol() const; const MCSymbol &AliasedSymbol() const;
void setVariableValue(const MCExpr *Value); void setVariableValue(const MCExpr *Value);
/// @} /// @}
/// print - Print the value to the stream \arg OS. /// print - Print the value to the stream \p OS.
void print(raw_ostream &OS) const; void print(raw_ostream &OS) const;
/// dump - Print the value to stderr. /// dump - Print the value to stderr.
void dump() const; void dump() const;
}; };
inline raw_ostream &operator<<(raw_ostream &OS, const MCSymbol &Sym) { inline raw_ostream &operator<<(raw_ostream &OS, const MCSymbol &Sym) {
Sym.print(OS); Sym.print(OS);
return OS; return OS;
} }
 End of changes. 5 change blocks. 
5 lines changed or deleted 6 lines changed or added


 MCTargetAsmLexer.h   MCTargetAsmLexer.h 
skipping to change at line 27 skipping to change at line 27
/// MCTargetAsmLexer - Generic interface to target specific assembly lexers . /// MCTargetAsmLexer - Generic interface to target specific assembly lexers .
class MCTargetAsmLexer { class MCTargetAsmLexer {
/// The current token /// The current token
AsmToken CurTok; AsmToken CurTok;
/// The location and description of the current error /// The location and description of the current error
SMLoc ErrLoc; SMLoc ErrLoc;
std::string Err; std::string Err;
MCTargetAsmLexer(const MCTargetAsmLexer &); // DO NOT IMPLEMENT MCTargetAsmLexer(const MCTargetAsmLexer &) LLVM_DELETED_FUNCTION;
void operator=(const MCTargetAsmLexer &); // DO NOT IMPLEMENT void operator=(const MCTargetAsmLexer &) LLVM_DELETED_FUNCTION;
protected: // Can only create subclasses. protected: // Can only create subclasses.
MCTargetAsmLexer(const Target &); MCTargetAsmLexer(const Target &);
virtual AsmToken LexToken() = 0; virtual AsmToken LexToken() = 0;
void SetError(const SMLoc &errLoc, const std::string &err) { void SetError(const SMLoc &errLoc, const std::string &err) {
ErrLoc = errLoc; ErrLoc = errLoc;
Err = err; Err = err;
} }
/// TheTarget - The Target that this machine was created for. /// TheTarget - The Target that this machine was created for.
const Target &TheTarget; const Target &TheTarget;
MCAsmLexer *Lexer; MCAsmLexer *Lexer;
public: public:
virtual ~MCTargetAsmLexer(); virtual ~MCTargetAsmLexer();
const Target &getTarget() const { return TheTarget; } const Target &getTarget() const { return TheTarget; }
/// InstallLexer - Set the lexer to get tokens from lower-level lexer \ar g L. /// InstallLexer - Set the lexer to get tokens from lower-level lexer \p L.
void InstallLexer(MCAsmLexer &L) { void InstallLexer(MCAsmLexer &L) {
Lexer = &L; Lexer = &L;
} }
MCAsmLexer *getLexer() { MCAsmLexer *getLexer() {
return Lexer; return Lexer;
} }
/// Lex - Consume the next token from the input stream and return it. /// Lex - Consume the next token from the input stream and return it.
const AsmToken &Lex() { const AsmToken &Lex() {
skipping to change at line 80 skipping to change at line 80
} }
/// getErr - Get the current error string /// getErr - Get the current error string
const std::string &getErr() { const std::string &getErr() {
return Err; return Err;
} }
/// getKind - Get the kind of current token. /// getKind - Get the kind of current token.
AsmToken::TokenKind getKind() const { return CurTok.getKind(); } AsmToken::TokenKind getKind() const { return CurTok.getKind(); }
/// is - Check if the current token has kind \arg K. /// is - Check if the current token has kind \p K.
bool is(AsmToken::TokenKind K) const { return CurTok.is(K); } bool is(AsmToken::TokenKind K) const { return CurTok.is(K); }
/// isNot - Check if the current token has kind \arg K. /// isNot - Check if the current token has kind \p K.
bool isNot(AsmToken::TokenKind K) const { return CurTok.isNot(K); } bool isNot(AsmToken::TokenKind K) const { return CurTok.isNot(K); }
}; };
} // End llvm namespace } // End llvm namespace
#endif #endif
 End of changes. 4 change blocks. 
5 lines changed or deleted 5 lines changed or added


 MCTargetAsmParser.h   MCTargetAsmParser.h 
skipping to change at line 24 skipping to change at line 24
namespace llvm { namespace llvm {
class MCStreamer; class MCStreamer;
class StringRef; class StringRef;
class SMLoc; class SMLoc;
class AsmToken; class AsmToken;
class MCParsedAsmOperand; class MCParsedAsmOperand;
class MCInst; class MCInst;
template <typename T> class SmallVectorImpl; template <typename T> class SmallVectorImpl;
enum AsmRewriteKind {
AOK_DotOperator, // Rewrite a dot operator expression as an immediate.
// E.g., [eax].foo.bar -> [eax].8
AOK_Emit, // Rewrite _emit as .byte.
AOK_Imm, // Rewrite as $$N.
AOK_ImmPrefix, // Add $$ before a parsed Imm.
AOK_Input, // Rewrite in terms of $N.
AOK_Output, // Rewrite in terms of $N.
AOK_SizeDirective, // Add a sizing directive (e.g., dword ptr).
AOK_Skip // Skip emission (e.g., offset/type operators).
};
struct AsmRewrite {
AsmRewriteKind Kind;
SMLoc Loc;
unsigned Len;
unsigned Val;
public:
AsmRewrite(AsmRewriteKind kind, SMLoc loc, unsigned len = 0, unsigned val
= 0)
: Kind(kind), Loc(loc), Len(len), Val(val) {}
};
struct ParseInstructionInfo {
SmallVectorImpl<AsmRewrite> *AsmRewrites;
ParseInstructionInfo() : AsmRewrites(0) {}
ParseInstructionInfo(SmallVectorImpl<AsmRewrite> *rewrites)
: AsmRewrites(rewrites) {}
~ParseInstructionInfo() {}
};
/// MCTargetAsmParser - Generic interface to target specific assembly parse rs. /// MCTargetAsmParser - Generic interface to target specific assembly parse rs.
class MCTargetAsmParser : public MCAsmParserExtension { class MCTargetAsmParser : public MCAsmParserExtension {
public: public:
enum MatchResultTy { enum MatchResultTy {
Match_ConversionFail,
Match_InvalidOperand, Match_InvalidOperand,
Match_MissingFeature, Match_MissingFeature,
Match_MnemonicFail, Match_MnemonicFail,
Match_Success, Match_Success,
FIRST_TARGET_MATCH_RESULT_TY FIRST_TARGET_MATCH_RESULT_TY
}; };
private: private:
MCTargetAsmParser(const MCTargetAsmParser &); // DO NOT IMPLEMENT MCTargetAsmParser(const MCTargetAsmParser &) LLVM_DELETED_FUNCTION;
void operator=(const MCTargetAsmParser &); // DO NOT IMPLEMENT void operator=(const MCTargetAsmParser &) LLVM_DELETED_FUNCTION;
protected: // Can only create subclasses. protected: // Can only create subclasses.
MCTargetAsmParser(); MCTargetAsmParser();
/// AvailableFeatures - The current set of available features. /// AvailableFeatures - The current set of available features.
unsigned AvailableFeatures; unsigned AvailableFeatures;
/// ParsingInlineAsm - Are we parsing ms-style inline assembly?
bool ParsingInlineAsm;
/// SemaCallback - The Sema callback implementation. Must be set when pa
rsing
/// ms-style inline assembly.
MCAsmParserSemaCallback *SemaCallback;
public: public:
virtual ~MCTargetAsmParser(); virtual ~MCTargetAsmParser();
unsigned getAvailableFeatures() const { return AvailableFeatures; } unsigned getAvailableFeatures() const { return AvailableFeatures; }
void setAvailableFeatures(unsigned Value) { AvailableFeatures = Value; } void setAvailableFeatures(unsigned Value) { AvailableFeatures = Value; }
bool isParsingInlineAsm () { return ParsingInlineAsm; }
void setParsingInlineAsm (bool Value) { ParsingInlineAsm = Value; }
void setSemaCallback(MCAsmParserSemaCallback *Callback) {
SemaCallback = Callback;
}
virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
SMLoc &EndLoc) = 0; SMLoc &EndLoc) = 0;
/// ParseInstruction - Parse one assembly instruction. /// ParseInstruction - Parse one assembly instruction.
/// ///
/// The parser is positioned following the instruction name. The target /// The parser is positioned following the instruction name. The target
/// specific instruction parser should parse the entire instruction and /// specific instruction parser should parse the entire instruction and
/// construct the appropriate MCInst, or emit an error. On success, the e ntire /// construct the appropriate MCInst, or emit an error. On success, the e ntire
/// line should be parsed up to and including the end-of-statement token. On /// line should be parsed up to and including the end-of-statement token. On
/// failure, the parser is not required to read to the end of the line. /// failure, the parser is not required to read to the end of the line.
// //
/// \param Name - The instruction name. /// \param Name - The instruction name.
/// \param NameLoc - The source location of the name. /// \param NameLoc - The source location of the name.
/// \param Operands [out] - The list of parsed operands, this returns /// \param Operands [out] - The list of parsed operands, this returns
/// ownership of them to the caller. /// ownership of them to the caller.
/// \return True on failure. /// \return True on failure.
virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc, virtual bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
SMLoc NameLoc,
SmallVectorImpl<MCParsedAsmOperand*> &Operands) = 0; SmallVectorImpl<MCParsedAsmOperand*> &Operands) = 0;
/// ParseDirective - Parse a target specific assembler directive /// ParseDirective - Parse a target specific assembler directive
/// ///
/// The parser is positioned following the directive name. The target /// The parser is positioned following the directive name. The target
/// specific directive parser should parse the entire directive doing or /// specific directive parser should parse the entire directive doing or
/// recording any target specific work, or return true and do nothing if the /// recording any target specific work, or return true and do nothing if the
/// directive is not target specific. If the directive is specific for /// directive is not target specific. If the directive is specific for
/// the target, the entire line is parsed up to and including the /// the target, the entire line is parsed up to and including the
/// end-of-statement token and false is returned. /// end-of-statement token and false is returned.
/// ///
/// \param DirectiveID - the identifier token of the directive. /// \param DirectiveID - the identifier token of the directive.
virtual bool ParseDirective(AsmToken DirectiveID) = 0; virtual bool ParseDirective(AsmToken DirectiveID) = 0;
/// mnemonicIsValid - This returns true if this is a valid mnemonic and f
alse
/// otherwise.
virtual bool mnemonicIsValid(StringRef Mnemonic) = 0;
/// MatchAndEmitInstruction - Recognize a series of operands of a parsed /// MatchAndEmitInstruction - Recognize a series of operands of a parsed
/// instruction as an actual MCInst and emit it to the specified MCStream er. /// instruction as an actual MCInst and emit it to the specified MCStream er.
/// This returns false on success and returns true on failure to match. /// This returns false on success and returns true on failure to match.
/// ///
/// On failure, the target parser is responsible for emitting a diagnosti c /// On failure, the target parser is responsible for emitting a diagnosti c
/// explaining the match failure. /// explaining the match failure.
virtual bool virtual bool
MatchAndEmitInstruction(SMLoc IDLoc, MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
SmallVectorImpl<MCParsedAsmOperand*> &Operands, SmallVectorImpl<MCParsedAsmOperand*> &Operands,
MCStreamer &Out) = 0; MCStreamer &Out, unsigned &ErrorInfo,
bool MatchingInlineAsm) = 0;
/// checkTargetMatchPredicate - Validate the instruction match against /// checkTargetMatchPredicate - Validate the instruction match against
/// any complex target predicates not expressible via match classes. /// any complex target predicates not expressible via match classes.
virtual unsigned checkTargetMatchPredicate(MCInst &Inst) { virtual unsigned checkTargetMatchPredicate(MCInst &Inst) {
return Match_Success; return Match_Success;
} }
virtual void convertToMapAndConstraints(unsigned Kind,
const SmallVectorImpl<MCParsedAsmOperand*> &Operands)
= 0;
}; };
} // End llvm namespace } // End llvm namespace
#endif #endif
 End of changes. 10 change blocks. 
6 lines changed or deleted 64 lines changed or added


 MCValue.h   MCValue.h 
skipping to change at line 49 skipping to change at line 49
int64_t Cst; int64_t Cst;
public: public:
int64_t getConstant() const { return Cst; } int64_t getConstant() const { return Cst; }
const MCSymbolRefExpr *getSymA() const { return SymA; } const MCSymbolRefExpr *getSymA() const { return SymA; }
const MCSymbolRefExpr *getSymB() const { return SymB; } const MCSymbolRefExpr *getSymB() const { return SymB; }
/// isAbsolute - Is this an absolute (as opposed to relocatable) value. /// isAbsolute - Is this an absolute (as opposed to relocatable) value.
bool isAbsolute() const { return !SymA && !SymB; } bool isAbsolute() const { return !SymA && !SymB; }
/// print - Print the value to the stream \arg OS. /// print - Print the value to the stream \p OS.
void print(raw_ostream &OS, const MCAsmInfo *MAI) const; void print(raw_ostream &OS, const MCAsmInfo *MAI) const;
/// dump - Print the value to stderr. /// dump - Print the value to stderr.
void dump() const; void dump() const;
static MCValue get(const MCSymbolRefExpr *SymA, const MCSymbolRefExpr *Sy mB=0, static MCValue get(const MCSymbolRefExpr *SymA, const MCSymbolRefExpr *Sy mB=0,
int64_t Val = 0) { int64_t Val = 0) {
MCValue R; MCValue R;
assert((!SymB || SymA) && "Invalid relocatable MCValue!"); assert((!SymB || SymA) && "Invalid relocatable MCValue!");
R.Cst = Val; R.Cst = Val;
 End of changes. 1 change blocks. 
1 lines changed or deleted 1 lines changed or added


 MDBuilder.h   MDBuilder.h 
//===---- llvm/Support/MDBuilder.h - Builder for LLVM metadata --*- C++ -*- ===// //===---- llvm/MDBuilder.h - Builder for LLVM metadata ----------*- C++ -*- ===//
// //
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
// //
// This file is distributed under the University of Illinois Open Source // This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details. // License. See LICENSE.TXT for details.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// //
// This file defines the MDBuilder class, which is used as a convenient way to // This file defines the MDBuilder class, which is used as a convenient way to
// create LLVM metadata with a consistent and simplified interface. // create LLVM metadata with a consistent and simplified interface.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_SUPPORT_MDBUILDER_H #ifndef LLVM_MDBUILDER_H
#define LLVM_SUPPORT_MDBUILDER_H #define LLVM_MDBUILDER_H
#include "llvm/Constants.h" #include "llvm/Constants.h"
#include "llvm/DerivedTypes.h" #include "llvm/DerivedTypes.h"
#include "llvm/LLVMContext.h" #include "llvm/LLVMContext.h"
#include "llvm/Metadata.h" #include "llvm/Metadata.h"
#include "llvm/ADT/APInt.h" #include "llvm/ADT/APInt.h"
namespace llvm { namespace llvm {
class MDBuilder { class MDBuilder {
skipping to change at line 53 skipping to change at line 53
/// setting. /// setting.
MDNode *createFPMath(float Accuracy) { MDNode *createFPMath(float Accuracy) {
if (Accuracy == 0.0) if (Accuracy == 0.0)
return 0; return 0;
assert(Accuracy > 0.0 && "Invalid fpmath accuracy!"); assert(Accuracy > 0.0 && "Invalid fpmath accuracy!");
Value *Op = ConstantFP::get(Type::getFloatTy(Context), Accuracy); Value *Op = ConstantFP::get(Type::getFloatTy(Context), Accuracy);
return MDNode::get(Context, Op); return MDNode::get(Context, Op);
} }
//===------------------------------------------------------------------ ===// //===------------------------------------------------------------------ ===//
// Prof metadata.
//===------------------------------------------------------------------
===//
/// \brief Return metadata containing two branch weights.
MDNode *createBranchWeights(uint32_t TrueWeight, uint32_t FalseWeight)
{
uint32_t Weights[] = { TrueWeight, FalseWeight };
return createBranchWeights(Weights);
}
/// \brief Return metadata containing a number of branch weights.
MDNode *createBranchWeights(ArrayRef<uint32_t> Weights) {
assert(Weights.size() >= 2 && "Need at least two branch weights!");
SmallVector<Value *, 4> Vals(Weights.size()+1);
Vals[0] = createString("branch_weights");
Type *Int32Ty = Type::getInt32Ty(Context);
for (unsigned i = 0, e = Weights.size(); i != e; ++i)
Vals[i+1] = ConstantInt::get(Int32Ty, Weights[i]);
return MDNode::get(Context, Vals);
}
//===------------------------------------------------------------------
===//
// Range metadata. // Range metadata.
//===------------------------------------------------------------------ ===// //===------------------------------------------------------------------ ===//
/// \brief Return metadata describing the range [Lo, Hi). /// \brief Return metadata describing the range [Lo, Hi).
MDNode *createRange(const APInt &Lo, const APInt &Hi) { MDNode *createRange(const APInt &Lo, const APInt &Hi) {
assert(Lo.getBitWidth() == Hi.getBitWidth() && "Mismatched bitwidths! "); assert(Lo.getBitWidth() == Hi.getBitWidth() && "Mismatched bitwidths! ");
// If the range is everything then it is useless. // If the range is everything then it is useless.
if (Hi == Lo) if (Hi == Lo)
return 0; return 0;
skipping to change at line 112 skipping to change at line 136
if (isConstant) { if (isConstant) {
Constant *Flags = ConstantInt::get(Type::getInt64Ty(Context), 1); Constant *Flags = ConstantInt::get(Type::getInt64Ty(Context), 1);
Value *Ops[3] = { createString(Name), Parent, Flags }; Value *Ops[3] = { createString(Name), Parent, Flags };
return MDNode::get(Context, Ops); return MDNode::get(Context, Ops);
} else { } else {
Value *Ops[2] = { createString(Name), Parent }; Value *Ops[2] = { createString(Name), Parent };
return MDNode::get(Context, Ops); return MDNode::get(Context, Ops);
} }
} }
struct TBAAStructField {
uint64_t Offset;
uint64_t Size;
MDNode *TBAA;
TBAAStructField(uint64_t Offset, uint64_t Size, MDNode *TBAA) :
Offset(Offset), Size(Size), TBAA(TBAA) {}
};
/// \brief Return metadata for a tbaa.struct node with the given
/// struct field descriptions.
MDNode *createTBAAStructNode(ArrayRef<TBAAStructField> Fields) {
SmallVector<Value *, 4> Vals(Fields.size() * 3);
Type *Int64 = IntegerType::get(Context, 64);
for (unsigned i = 0, e = Fields.size(); i != e; ++i) {
Vals[i * 3 + 0] = ConstantInt::get(Int64, Fields[i].Offset);
Vals[i * 3 + 1] = ConstantInt::get(Int64, Fields[i].Size);
Vals[i * 3 + 2] = Fields[i].TBAA;
}
return MDNode::get(Context, Vals);
}
}; };
} // end namespace llvm } // end namespace llvm
#endif #endif
 End of changes. 4 change blocks. 
3 lines changed or deleted 51 lines changed or added


 MachO.h   MachO.h 
skipping to change at line 52 skipping to change at line 52
virtual uint8_t getBytesInAddress() const; virtual uint8_t getBytesInAddress() const;
virtual StringRef getFileFormatName() const; virtual StringRef getFileFormatName() const;
virtual unsigned getArch() const; virtual unsigned getArch() const;
virtual StringRef getLoadName() const; virtual StringRef getLoadName() const;
MachOObject *getObject() { return MachOObj; } MachOObject *getObject() { return MachOObj; }
static inline bool classof(const Binary *v) { static inline bool classof(const Binary *v) {
return v->isMachO(); return v->isMachO();
} }
static inline bool classof(const MachOObjectFile *v) { return true; }
protected: protected:
virtual error_code getSymbolNext(DataRefImpl Symb, SymbolRef &Res) const; virtual error_code getSymbolNext(DataRefImpl Symb, SymbolRef &Res) const;
virtual error_code getSymbolName(DataRefImpl Symb, StringRef &Res) const; virtual error_code getSymbolName(DataRefImpl Symb, StringRef &Res) const;
virtual error_code getSymbolFileOffset(DataRefImpl Symb, uint64_t &Res) c onst; virtual error_code getSymbolFileOffset(DataRefImpl Symb, uint64_t &Res) c onst;
virtual error_code getSymbolAddress(DataRefImpl Symb, uint64_t &Res) cons t; virtual error_code getSymbolAddress(DataRefImpl Symb, uint64_t &Res) cons t;
virtual error_code getSymbolSize(DataRefImpl Symb, uint64_t &Res) const; virtual error_code getSymbolSize(DataRefImpl Symb, uint64_t &Res) const;
virtual error_code getSymbolNMTypeChar(DataRefImpl Symb, char &Res) const ; virtual error_code getSymbolNMTypeChar(DataRefImpl Symb, char &Res) const ;
virtual error_code getSymbolFlags(DataRefImpl Symb, uint32_t &Res) const; virtual error_code getSymbolFlags(DataRefImpl Symb, uint32_t &Res) const;
virtual error_code getSymbolType(DataRefImpl Symb, SymbolRef::Type &Res) const; virtual error_code getSymbolType(DataRefImpl Symb, SymbolRef::Type &Res) const;
virtual error_code getSymbolSection(DataRefImpl Symb, virtual error_code getSymbolSection(DataRefImpl Symb,
section_iterator &Res) const; section_iterator &Res) const;
virtual error_code getSymbolValue(DataRefImpl Symb, uint64_t &Val) const;
virtual error_code getSectionNext(DataRefImpl Sec, SectionRef &Res) const ; virtual error_code getSectionNext(DataRefImpl Sec, SectionRef &Res) const ;
virtual error_code getSectionName(DataRefImpl Sec, StringRef &Res) const; virtual error_code getSectionName(DataRefImpl Sec, StringRef &Res) const;
virtual error_code getSectionAddress(DataRefImpl Sec, uint64_t &Res) cons t; virtual error_code getSectionAddress(DataRefImpl Sec, uint64_t &Res) cons t;
virtual error_code getSectionSize(DataRefImpl Sec, uint64_t &Res) const; virtual error_code getSectionSize(DataRefImpl Sec, uint64_t &Res) const;
virtual error_code getSectionContents(DataRefImpl Sec, StringRef &Res) co nst; virtual error_code getSectionContents(DataRefImpl Sec, StringRef &Res) co nst;
virtual error_code getSectionAlignment(DataRefImpl Sec, uint64_t &Res) co nst; virtual error_code getSectionAlignment(DataRefImpl Sec, uint64_t &Res) co nst;
virtual error_code isSectionText(DataRefImpl Sec, bool &Res) const; virtual error_code isSectionText(DataRefImpl Sec, bool &Res) const;
virtual error_code isSectionData(DataRefImpl Sec, bool &Res) const; virtual error_code isSectionData(DataRefImpl Sec, bool &Res) const;
virtual error_code isSectionBSS(DataRefImpl Sec, bool &Res) const; virtual error_code isSectionBSS(DataRefImpl Sec, bool &Res) const;
virtual error_code isSectionRequiredForExecution(DataRefImpl Sec, virtual error_code isSectionRequiredForExecution(DataRefImpl Sec,
bool &Res) const; bool &Res) const;
virtual error_code isSectionVirtual(DataRefImpl Sec, bool &Res) const; virtual error_code isSectionVirtual(DataRefImpl Sec, bool &Res) const;
virtual error_code isSectionZeroInit(DataRefImpl Sec, bool &Res) const; virtual error_code isSectionZeroInit(DataRefImpl Sec, bool &Res) const;
virtual error_code isSectionReadOnlyData(DataRefImpl Sec, bool &Res) cons t;
virtual error_code sectionContainsSymbol(DataRefImpl DRI, DataRefImpl S, virtual error_code sectionContainsSymbol(DataRefImpl DRI, DataRefImpl S,
bool &Result) const; bool &Result) const;
virtual relocation_iterator getSectionRelBegin(DataRefImpl Sec) const; virtual relocation_iterator getSectionRelBegin(DataRefImpl Sec) const;
virtual relocation_iterator getSectionRelEnd(DataRefImpl Sec) const; virtual relocation_iterator getSectionRelEnd(DataRefImpl Sec) const;
virtual error_code getRelocationNext(DataRefImpl Rel, virtual error_code getRelocationNext(DataRefImpl Rel,
RelocationRef &Res) const; RelocationRef &Res) const;
virtual error_code getRelocationAddress(DataRefImpl Rel, virtual error_code getRelocationAddress(DataRefImpl Rel,
uint64_t &Res) const; uint64_t &Res) const;
virtual error_code getRelocationOffset(DataRefImpl Rel, virtual error_code getRelocationOffset(DataRefImpl Rel,
 End of changes. 3 change blocks. 
1 lines changed or deleted 2 lines changed or added


 MachOFormat.h   MachOFormat.h 
skipping to change at line 64 skipping to change at line 64
CSFM_SubtypeLib64 = 0x80000000 CSFM_SubtypeLib64 = 0x80000000
}; };
/// \brief ARM Machine Subtypes. /// \brief ARM Machine Subtypes.
enum CPUSubtypeARM { enum CPUSubtypeARM {
CSARM_ALL = 0, CSARM_ALL = 0,
CSARM_V4T = 5, CSARM_V4T = 5,
CSARM_V6 = 6, CSARM_V6 = 6,
CSARM_V5TEJ = 7, CSARM_V5TEJ = 7,
CSARM_XSCALE = 8, CSARM_XSCALE = 8,
CSARM_V7 = 9 CSARM_V7 = 9,
CSARM_V7F = 10,
CSARM_V7S = 11,
CSARM_V7K = 12
}; };
/// \brief PowerPC Machine Subtypes. /// \brief PowerPC Machine Subtypes.
enum CPUSubtypePowerPC { enum CPUSubtypePowerPC {
CSPPC_ALL = 0 CSPPC_ALL = 0
}; };
/// \brief SPARC Machine Subtypes. /// \brief SPARC Machine Subtypes.
enum CPUSubtypeSPARC { enum CPUSubtypeSPARC {
CSSPARC_ALL = 0 CSSPARC_ALL = 0
skipping to change at line 100 skipping to change at line 103
Header32Size = 28, Header32Size = 28,
Header64Size = 32, Header64Size = 32,
SegmentLoadCommand32Size = 56, SegmentLoadCommand32Size = 56,
SegmentLoadCommand64Size = 72, SegmentLoadCommand64Size = 72,
Section32Size = 68, Section32Size = 68,
Section64Size = 80, Section64Size = 80,
SymtabLoadCommandSize = 24, SymtabLoadCommandSize = 24,
DysymtabLoadCommandSize = 80, DysymtabLoadCommandSize = 80,
Nlist32Size = 12, Nlist32Size = 12,
Nlist64Size = 16, Nlist64Size = 16,
RelocationInfoSize = 8 RelocationInfoSize = 8,
LinkeditLoadCommandSize = 16
}; };
/// \brief Constants for header magic field. /// \brief Constants for header magic field.
enum HeaderMagic { enum HeaderMagic {
HM_Object32 = 0xFEEDFACE, ///< 32-bit mach object file HM_Object32 = 0xFEEDFACE, ///< 32-bit mach object file
HM_Object64 = 0xFEEDFACF, ///< 64-bit mach object file HM_Object64 = 0xFEEDFACF, ///< 64-bit mach object file
HM_Universal = 0xCAFEBABE ///< Universal object file HM_Universal = 0xCAFEBABE ///< Universal object file
}; };
/// \brief Header common to all Mach object files. /// \brief Header common to all Mach object files.
skipping to change at line 143 skipping to change at line 147
}; };
enum LoadCommandType { enum LoadCommandType {
LCT_Segment = 0x1, LCT_Segment = 0x1,
LCT_Symtab = 0x2, LCT_Symtab = 0x2,
LCT_Dysymtab = 0xb, LCT_Dysymtab = 0xb,
LCT_Segment64 = 0x19, LCT_Segment64 = 0x19,
LCT_UUID = 0x1b, LCT_UUID = 0x1b,
LCT_CodeSignature = 0x1d, LCT_CodeSignature = 0x1d,
LCT_SegmentSplitInfo = 0x1e, LCT_SegmentSplitInfo = 0x1e,
LCT_FunctionStarts = 0x26 LCT_FunctionStarts = 0x26,
LCT_DataInCode = 0x29
}; };
/// \brief Load command structure. /// \brief Load command structure.
struct LoadCommand { struct LoadCommand {
uint32_t Type; uint32_t Type;
uint32_t Size; uint32_t Size;
}; };
/// @name Load Command Structures /// @name Load Command Structures
/// @{ /// @{
skipping to change at line 274 skipping to change at line 279
/// @name Symbol Table Entries /// @name Symbol Table Entries
/// @{ /// @{
struct SymbolTableEntry { struct SymbolTableEntry {
uint32_t StringIndex; uint32_t StringIndex;
uint8_t Type; uint8_t Type;
uint8_t SectionIndex; uint8_t SectionIndex;
uint16_t Flags; uint16_t Flags;
uint32_t Value; uint32_t Value;
}; };
// Despite containing a uint64_t, this structure is only 4-byte aligned w
ithin
// a MachO file.
#pragma pack(push)
#pragma pack(4)
struct Symbol64TableEntry { struct Symbol64TableEntry {
uint32_t StringIndex; uint32_t StringIndex;
uint8_t Type; uint8_t Type;
uint8_t SectionIndex; uint8_t SectionIndex;
uint16_t Flags; uint16_t Flags;
uint64_t Value; uint64_t Value;
}; };
#pragma pack(pop)
/// @}
/// @name Data-in-code Table Entry
/// @{
// See <mach-o/loader.h>.
enum DataRegionType { Data = 1, JumpTable8, JumpTable16, JumpTable32 };
struct DataInCodeTableEntry {
uint32_t Offset; /* from mach_header to start of data region */
uint16_t Length; /* number of bytes in data region */
uint16_t Kind; /* a DataRegionType value */
};
/// @} /// @}
/// @name Indirect Symbol Table /// @name Indirect Symbol Table
/// @{ /// @{
struct IndirectSymbolTableEntry { struct IndirectSymbolTableEntry {
uint32_t Index; uint32_t Index;
}; };
/// @} /// @}
 End of changes. 5 change blocks. 
3 lines changed or deleted 26 lines changed or added


 MachOObject.h   MachOObject.h 
skipping to change at line 177 skipping to change at line 177
InMemoryStruct<macho::Section64> &Res) const; InMemoryStruct<macho::Section64> &Res) const;
void ReadRelocationEntry( void ReadRelocationEntry(
uint64_t RelocationTableOffset, unsigned Index, uint64_t RelocationTableOffset, unsigned Index,
InMemoryStruct<macho::RelocationEntry> &Res) const; InMemoryStruct<macho::RelocationEntry> &Res) const;
void ReadSymbolTableEntry( void ReadSymbolTableEntry(
uint64_t SymbolTableOffset, unsigned Index, uint64_t SymbolTableOffset, unsigned Index,
InMemoryStruct<macho::SymbolTableEntry> &Res) const; InMemoryStruct<macho::SymbolTableEntry> &Res) const;
void ReadSymbol64TableEntry( void ReadSymbol64TableEntry(
uint64_t SymbolTableOffset, unsigned Index, uint64_t SymbolTableOffset, unsigned Index,
InMemoryStruct<macho::Symbol64TableEntry> &Res) const; InMemoryStruct<macho::Symbol64TableEntry> &Res) const;
void ReadDataInCodeTableEntry(
uint64_t TableOffset, unsigned Index,
InMemoryStruct<macho::DataInCodeTableEntry> &Res) const;
void ReadULEB128s(uint64_t Index, SmallVectorImpl<uint64_t> &Out) const; void ReadULEB128s(uint64_t Index, SmallVectorImpl<uint64_t> &Out) const;
/// @} /// @}
/// @name Object Dump Facilities /// @name Object Dump Facilities
/// @{ /// @{
/// dump - Support for debugging, callable in GDB: V->dump() /// dump - Support for debugging, callable in GDB: V->dump()
// //
void dump() const; void dump() const;
void dumpHeader() const; void dumpHeader() const;
 End of changes. 1 change blocks. 
0 lines changed or deleted 3 lines changed or added


 MachineBasicBlock.h   MachineBasicBlock.h 
skipping to change at line 144 skipping to change at line 144
MachineFunction *getParent() { return xParent; } MachineFunction *getParent() { return xParent; }
/// bundle_iterator - MachineBasicBlock iterator that automatically skips over /// bundle_iterator - MachineBasicBlock iterator that automatically skips over
/// MIs that are inside bundles (i.e. walk top level MIs only). /// MIs that are inside bundles (i.e. walk top level MIs only).
template<typename Ty, typename IterTy> template<typename Ty, typename IterTy>
class bundle_iterator class bundle_iterator
: public std::iterator<std::bidirectional_iterator_tag, Ty, ptrdiff_t> { : public std::iterator<std::bidirectional_iterator_tag, Ty, ptrdiff_t> {
IterTy MII; IterTy MII;
public: public:
bundle_iterator(IterTy mii) : MII(mii) { bundle_iterator(IterTy mii) : MII(mii) {}
assert(!MII->isInsideBundle() &&
"It's not legal to initialize bundle_iterator with a bundled M
I");
}
bundle_iterator(Ty &mi) : MII(mi) { bundle_iterator(Ty &mi) : MII(mi) {
assert(!mi.isInsideBundle() && assert(!mi.isInsideBundle() &&
"It's not legal to initialize bundle_iterator with a bundled M I"); "It's not legal to initialize bundle_iterator with a bundled M I");
} }
bundle_iterator(Ty *mi) : MII(mi) { bundle_iterator(Ty *mi) : MII(mi) {
assert((!mi || !mi->isInsideBundle()) && assert((!mi || !mi->isInsideBundle()) &&
"It's not legal to initialize bundle_iterator with a bundled M I"); "It's not legal to initialize bundle_iterator with a bundled M I");
} }
bundle_iterator(const bundle_iterator &I) : MII(I.MII) {} // Template allows conversion from const to nonconst.
template<class OtherTy, class OtherIterTy>
bundle_iterator(const bundle_iterator<OtherTy, OtherIterTy> &I)
: MII(I.getInstrIterator()) {}
bundle_iterator() : MII(0) {} bundle_iterator() : MII(0) {}
Ty &operator*() const { return *MII; } Ty &operator*() const { return *MII; }
Ty *operator->() const { return &operator*(); } Ty *operator->() const { return &operator*(); }
operator Ty*() const { return MII; } operator Ty*() const { return MII; }
bool operator==(const bundle_iterator &x) const { bool operator==(const bundle_iterator &x) const {
return MII == x.MII; return MII == x.MII;
} }
bool operator!=(const bundle_iterator &x) const { bool operator!=(const bundle_iterator &x) const {
return !operator==(x); return !operator==(x);
} }
// Increment and decrement operators... // Increment and decrement operators...
bundle_iterator &operator--() { // predecrement - Back up bundle_iterator &operator--() { // predecrement - Back up
do { do --MII;
--MII; while (MII->isInsideBundle());
} while (MII->isInsideBundle());
return *this; return *this;
} }
bundle_iterator &operator++() { // preincrement - Advance bundle_iterator &operator++() { // preincrement - Advance
do { IterTy E = MII->getParent()->instr_end();
++MII; do ++MII;
} while (MII->isInsideBundle()); while (MII != E && MII->isInsideBundle());
return *this; return *this;
} }
bundle_iterator operator--(int) { // postdecrement operators... bundle_iterator operator--(int) { // postdecrement operators...
bundle_iterator tmp = *this; bundle_iterator tmp = *this;
do { --*this;
--MII;
} while (MII->isInsideBundle());
return tmp; return tmp;
} }
bundle_iterator operator++(int) { // postincrement operators... bundle_iterator operator++(int) { // postincrement operators...
bundle_iterator tmp = *this; bundle_iterator tmp = *this;
do { ++*this;
++MII;
} while (MII->isInsideBundle());
return tmp; return tmp;
} }
IterTy getInstrIterator() const { IterTy getInstrIterator() const {
return MII; return MII;
} }
}; };
typedef Instructions::iterator instr_iter ator; typedef Instructions::iterator instr_iter ator;
typedef Instructions::const_iterator const_instr_iter ator; typedef Instructions::const_iterator const_instr_iter ator;
skipping to change at line 235 skipping to change at line 230
instr_iterator instr_begin() { return Insts.begin(); } instr_iterator instr_begin() { return Insts.begin(); }
const_instr_iterator instr_begin() const { return Insts.begin(); } const_instr_iterator instr_begin() const { return Insts.begin(); }
instr_iterator instr_end() { return Insts.end(); } instr_iterator instr_end() { return Insts.end(); }
const_instr_iterator instr_end() const { return Insts.end(); } const_instr_iterator instr_end() const { return Insts.end(); }
reverse_instr_iterator instr_rbegin() { return Insts.rbegin() ; } reverse_instr_iterator instr_rbegin() { return Insts.rbegin() ; }
const_reverse_instr_iterator instr_rbegin() const { return Insts.rbegin() ; } const_reverse_instr_iterator instr_rbegin() const { return Insts.rbegin() ; }
reverse_instr_iterator instr_rend () { return Insts.rend(); } reverse_instr_iterator instr_rend () { return Insts.rend(); }
const_reverse_instr_iterator instr_rend () const { return Insts.rend(); } const_reverse_instr_iterator instr_rend () const { return Insts.rend(); }
iterator begin() { return Insts.begin(); } iterator begin() { return instr_begin(); }
const_iterator begin() const { return Insts.begin(); } const_iterator begin() const { return instr_begin(); }
iterator end() { iterator end () { return instr_end(); }
instr_iterator II = instr_end(); const_iterator end () const { return instr_end(); }
if (II != instr_begin()) { reverse_iterator rbegin() { return instr_rbegin(); }
while (II->isInsideBundle()) const_reverse_iterator rbegin() const { return instr_rbegin(); }
--II; reverse_iterator rend () { return instr_rend(); }
} const_reverse_iterator rend () const { return instr_rend(); }
return II;
}
const_iterator end() const {
const_instr_iterator II = instr_end();
if (II != instr_begin()) {
while (II->isInsideBundle())
--II;
}
return II;
}
reverse_iterator rbegin() {
reverse_instr_iterator II = instr_rbegin();
if (II != instr_rend()) {
while (II->isInsideBundle())
++II;
}
return II;
}
const_reverse_iterator rbegin() const {
const_reverse_instr_iterator II = instr_rbegin();
if (II != instr_rend()) {
while (II->isInsideBundle())
++II;
}
return II;
}
reverse_iterator rend () { return Insts.rend(); }
const_reverse_iterator rend () const { return Insts.rend(); }
// Machine-CFG iterators // Machine-CFG iterators
typedef std::vector<MachineBasicBlock *>::iterator pred_iterator; typedef std::vector<MachineBasicBlock *>::iterator pred_iterator;
typedef std::vector<MachineBasicBlock *>::const_iterator const_pred_itera tor; typedef std::vector<MachineBasicBlock *>::const_iterator const_pred_itera tor;
typedef std::vector<MachineBasicBlock *>::iterator succ_iterator; typedef std::vector<MachineBasicBlock *>::iterator succ_iterator;
typedef std::vector<MachineBasicBlock *>::const_iterator const_succ_itera tor; typedef std::vector<MachineBasicBlock *>::const_iterator const_succ_itera tor;
typedef std::vector<MachineBasicBlock *>::reverse_iterator typedef std::vector<MachineBasicBlock *>::reverse_iterator
pred_reverse_itera tor; pred_reverse_itera tor;
typedef std::vector<MachineBasicBlock *>::const_reverse_iterator typedef std::vector<MachineBasicBlock *>::const_reverse_iterator
const_pred_reverse_itera tor; const_pred_reverse_itera tor;
skipping to change at line 383 skipping to change at line 350
/// be able to use a fallthrough. /// be able to use a fallthrough.
void updateTerminator(); void updateTerminator();
// Machine-CFG mutators // Machine-CFG mutators
/// addSuccessor - Add succ as a successor of this MachineBasicBlock. /// addSuccessor - Add succ as a successor of this MachineBasicBlock.
/// The Predecessors list of succ is automatically updated. WEIGHT /// The Predecessors list of succ is automatically updated. WEIGHT
/// parameter is stored in Weights list and it may be used by /// parameter is stored in Weights list and it may be used by
/// MachineBranchProbabilityInfo analysis to calculate branch probability . /// MachineBranchProbabilityInfo analysis to calculate branch probability .
/// ///
/// Note that duplicate Machine CFG edges are not allowed.
///
void addSuccessor(MachineBasicBlock *succ, uint32_t weight = 0); void addSuccessor(MachineBasicBlock *succ, uint32_t weight = 0);
/// removeSuccessor - Remove successor from the successors list of this /// removeSuccessor - Remove successor from the successors list of this
/// MachineBasicBlock. The Predecessors list of succ is automatically upd ated. /// MachineBasicBlock. The Predecessors list of succ is automatically upd ated.
/// ///
void removeSuccessor(MachineBasicBlock *succ); void removeSuccessor(MachineBasicBlock *succ);
/// removeSuccessor - Remove specified successor from the successors list of /// removeSuccessor - Remove specified successor from the successors list of
/// this MachineBasicBlock. The Predecessors list of succ is automaticall y /// this MachineBasicBlock. The Predecessors list of succ is automaticall y
/// updated. Return the iterator to the element after the one removed. /// updated. Return the iterator to the element after the one removed.
skipping to change at line 410 skipping to change at line 379
/// transferSuccessors - Transfers all the successors from MBB to this /// transferSuccessors - Transfers all the successors from MBB to this
/// machine basic block (i.e., copies all the successors fromMBB and /// machine basic block (i.e., copies all the successors fromMBB and
/// remove all the successors from fromMBB). /// remove all the successors from fromMBB).
void transferSuccessors(MachineBasicBlock *fromMBB); void transferSuccessors(MachineBasicBlock *fromMBB);
/// transferSuccessorsAndUpdatePHIs - Transfers all the successors, as /// transferSuccessorsAndUpdatePHIs - Transfers all the successors, as
/// in transferSuccessors, and update PHI operands in the successor block s /// in transferSuccessors, and update PHI operands in the successor block s
/// which refer to fromMBB to refer to this. /// which refer to fromMBB to refer to this.
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *fromMBB); void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *fromMBB);
/// isPredecessor - Return true if the specified MBB is a predecessor of
this
/// block.
bool isPredecessor(const MachineBasicBlock *MBB) const;
/// isSuccessor - Return true if the specified MBB is a successor of this /// isSuccessor - Return true if the specified MBB is a successor of this
/// block. /// block.
bool isSuccessor(const MachineBasicBlock *MBB) const; bool isSuccessor(const MachineBasicBlock *MBB) const;
/// isLayoutSuccessor - Return true if the specified MBB will be emitted /// isLayoutSuccessor - Return true if the specified MBB will be emitted
/// immediately after this block, such that if this block exits by /// immediately after this block, such that if this block exits by
/// falling through, control will transfer to the specified MBB. Note /// falling through, control will transfer to the specified MBB. Note
/// that MBB need not be a successor at all, for example if this block /// that MBB need not be a successor at all, for example if this block
/// ends with an unconditional branch to some other block. /// ends with an unconditional branch to some other block.
bool isLayoutSuccessor(const MachineBasicBlock *MBB) const; bool isLayoutSuccessor(const MachineBasicBlock *MBB) const;
skipping to change at line 572 skipping to change at line 545
MachineBasicBlock *DestB, MachineBasicBlock *DestB,
bool isCond); bool isCond);
/// findDebugLoc - find the next valid DebugLoc starting at MBBI, skippin g /// findDebugLoc - find the next valid DebugLoc starting at MBBI, skippin g
/// any DBG_VALUE instructions. Return UnknownLoc if there is none. /// any DBG_VALUE instructions. Return UnknownLoc if there is none.
DebugLoc findDebugLoc(instr_iterator MBBI); DebugLoc findDebugLoc(instr_iterator MBBI);
DebugLoc findDebugLoc(iterator MBBI) { DebugLoc findDebugLoc(iterator MBBI) {
return findDebugLoc(MBBI.getInstrIterator()); return findDebugLoc(MBBI.getInstrIterator());
} }
/// Possible outcome of a register liveness query to computeRegisterLiven
ess()
enum LivenessQueryResult {
LQR_Live, ///< Register is known to be live.
LQR_OverlappingLive, ///< Register itself is not live, but some overlap
ping
///< register is.
LQR_Dead, ///< Register is known to be dead.
LQR_Unknown ///< Register liveness not decidable from local
///< neighborhood.
};
/// computeRegisterLiveness - Return whether (physical) register \c Reg
/// has been <def>ined and not <kill>ed as of just before \c MI.
///
/// Search is localised to a neighborhood of
/// \c Neighborhood instructions before (searching for defs or kills) and
/// Neighborhood instructions after (searching just for defs) MI.
///
/// \c Reg must be a physical register.
LivenessQueryResult computeRegisterLiveness(const TargetRegisterInfo *TRI
,
unsigned Reg, MachineInstr *M
I,
unsigned Neighborhood=10);
// Debugging methods. // Debugging methods.
void dump() const; void dump() const;
void print(raw_ostream &OS, SlotIndexes* = 0) const; void print(raw_ostream &OS, SlotIndexes* = 0) const;
/// getNumber - MachineBasicBlocks are uniquely numbered at the function /// getNumber - MachineBasicBlocks are uniquely numbered at the function
/// level, unless they're not in a MachineFunction yet, in which case thi s /// level, unless they're not in a MachineFunction yet, in which case thi s
/// will return -1. /// will return -1.
/// ///
int getNumber() const { return Number; } int getNumber() const { return Number; }
void setNumber(int N) { Number = N; } void setNumber(int N) { Number = N; }
skipping to change at line 598 skipping to change at line 593
/// getWeightIterator - Return weight iterator corresponding to the I /// getWeightIterator - Return weight iterator corresponding to the I
/// successor iterator. /// successor iterator.
weight_iterator getWeightIterator(succ_iterator I); weight_iterator getWeightIterator(succ_iterator I);
const_weight_iterator getWeightIterator(const_succ_iterator I) const; const_weight_iterator getWeightIterator(const_succ_iterator I) const;
friend class MachineBranchProbabilityInfo; friend class MachineBranchProbabilityInfo;
/// getSuccWeight - Return weight of the edge from this block to MBB. Thi s /// getSuccWeight - Return weight of the edge from this block to MBB. Thi s
/// method should NOT be called directly, but by using getEdgeWeight meth od /// method should NOT be called directly, but by using getEdgeWeight meth od
/// from MachineBranchProbabilityInfo class. /// from MachineBranchProbabilityInfo class.
uint32_t getSuccWeight(const MachineBasicBlock *succ) const; uint32_t getSuccWeight(const_succ_iterator Succ) const;
// Methods used to maintain doubly linked list of blocks... // Methods used to maintain doubly linked list of blocks...
friend struct ilist_traits<MachineBasicBlock>; friend struct ilist_traits<MachineBasicBlock>;
// Machine-CFG mutators // Machine-CFG mutators
/// addPredecessor - Remove pred as a predecessor of this MachineBasicBlo ck. /// addPredecessor - Remove pred as a predecessor of this MachineBasicBlo ck.
/// Don't do this unless you know what you're doing, because it doesn't /// Don't do this unless you know what you're doing, because it doesn't
/// update pred's successors list. Use pred->addSuccessor instead. /// update pred's successors list. Use pred->addSuccessor instead.
/// ///
 End of changes. 11 change blocks. 
55 lines changed or deleted 54 lines changed or added


 MachineBranchProbabilityInfo.h   MachineBranchProbabilityInfo.h 
skipping to change at line 19 skipping to change at line 19
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// //
// This pass is used to evaluate branch probabilties on machine basic block s. // This pass is used to evaluate branch probabilties on machine basic block s.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_CODEGEN_MACHINEBRANCHPROBABILITYINFO_H #ifndef LLVM_CODEGEN_MACHINEBRANCHPROBABILITYINFO_H
#define LLVM_CODEGEN_MACHINEBRANCHPROBABILITYINFO_H #define LLVM_CODEGEN_MACHINEBRANCHPROBABILITYINFO_H
#include "llvm/Pass.h" #include "llvm/Pass.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/Support/BranchProbability.h" #include "llvm/Support/BranchProbability.h"
#include <climits> #include <climits>
namespace llvm { namespace llvm {
class raw_ostream;
class MachineBasicBlock;
class MachineBranchProbabilityInfo : public ImmutablePass { class MachineBranchProbabilityInfo : public ImmutablePass {
virtual void anchor(); virtual void anchor();
// Default weight value. Used when we don't have information about the ed ge. // Default weight value. Used when we don't have information about the ed ge.
// TODO: DEFAULT_WEIGHT makes sense during static predication, when none of // TODO: DEFAULT_WEIGHT makes sense during static predication, when none of
// the successors have a weight yet. But it doesn't make sense when provi ding // the successors have a weight yet. But it doesn't make sense when provi ding
// weight to an edge that may have siblings with non-zero weights. This c an // weight to an edge that may have siblings with non-zero weights. This c an
// be handled various ways, but it's probably fine for an edge with unkno wn // be handled various ways, but it's probably fine for an edge with unkno wn
// weight to just "inherit" the non-zero weight of an adjacent successor. // weight to just "inherit" the non-zero weight of an adjacent successor.
static const uint32_t DEFAULT_WEIGHT = 16; static const uint32_t DEFAULT_WEIGHT = 16;
skipping to change at line 55 skipping to change at line 53
void getAnalysisUsage(AnalysisUsage &AU) const { void getAnalysisUsage(AnalysisUsage &AU) const {
AU.setPreservesAll(); AU.setPreservesAll();
} }
// Return edge weight. If we don't have any informations about it - retur n // Return edge weight. If we don't have any informations about it - retur n
// DEFAULT_WEIGHT. // DEFAULT_WEIGHT.
uint32_t getEdgeWeight(const MachineBasicBlock *Src, uint32_t getEdgeWeight(const MachineBasicBlock *Src,
const MachineBasicBlock *Dst) const; const MachineBasicBlock *Dst) const;
// Same thing, but using a const_succ_iterator from Src. This is faster w
hen
// the iterator is already available.
uint32_t getEdgeWeight(const MachineBasicBlock *Src,
MachineBasicBlock::const_succ_iterator Dst) const;
// Get sum of the block successors' weights, potentially scaling them to fit // Get sum of the block successors' weights, potentially scaling them to fit
// within 32-bits. If scaling is required, sets Scale based on the necess ary // within 32-bits. If scaling is required, sets Scale based on the necess ary
// adjustment. Any edge weights used with the sum should be divided by Sc ale. // adjustment. Any edge weights used with the sum should be divided by Sc ale.
uint32_t getSumForBlock(const MachineBasicBlock *MBB, uint32_t &Scale) co nst; uint32_t getSumForBlock(const MachineBasicBlock *MBB, uint32_t &Scale) co nst;
// A 'Hot' edge is an edge which probability is >= 80%. // A 'Hot' edge is an edge which probability is >= 80%.
bool isEdgeHot(MachineBasicBlock *Src, MachineBasicBlock *Dst) const; bool isEdgeHot(MachineBasicBlock *Src, MachineBasicBlock *Dst) const;
// Return a hot successor for the block BB or null if there isn't one. // Return a hot successor for the block BB or null if there isn't one.
// NB: This routine's complexity is linear on the number of successors. // NB: This routine's complexity is linear on the number of successors.
 End of changes. 3 change blocks. 
3 lines changed or deleted 7 lines changed or added


 MachineConstantPool.h   MachineConstantPool.h 
skipping to change at line 28 skipping to change at line 28
#include "llvm/ADT/DenseSet.h" #include "llvm/ADT/DenseSet.h"
#include <cassert> #include <cassert>
#include <climits> #include <climits>
#include <vector> #include <vector>
namespace llvm { namespace llvm {
class Constant; class Constant;
class FoldingSetNodeID; class FoldingSetNodeID;
class TargetData; class DataLayout;
class TargetMachine; class TargetMachine;
class Type; class Type;
class MachineConstantPool; class MachineConstantPool;
class raw_ostream; class raw_ostream;
/// Abstract base class for all machine specific constantpool value subclas ses. /// Abstract base class for all machine specific constantpool value subclas ses.
/// ///
class MachineConstantPoolValue { class MachineConstantPoolValue {
virtual void anchor(); virtual void anchor();
Type *Ty; Type *Ty;
skipping to change at line 133 skipping to change at line 133
/// function which must be spilled to memory. This is used for constants w hich /// function which must be spilled to memory. This is used for constants w hich
/// are unable to be used directly as operands to instructions, which typic ally /// are unable to be used directly as operands to instructions, which typic ally
/// include floating point and large integer constants. /// include floating point and large integer constants.
/// ///
/// Instructions reference the address of these constant pool constants thr ough /// Instructions reference the address of these constant pool constants thr ough
/// the use of MO_ConstantPoolIndex values. When emitting assembly or mach ine /// the use of MO_ConstantPoolIndex values. When emitting assembly or mach ine
/// code, these virtual address references are converted to refer to the /// code, these virtual address references are converted to refer to the
/// address of the function constant pool values. /// address of the function constant pool values.
/// @brief The machine constant pool. /// @brief The machine constant pool.
class MachineConstantPool { class MachineConstantPool {
const TargetData *TD; ///< The machine's TargetData. const DataLayout *TD; ///< The machine's DataLayout.
unsigned PoolAlignment; ///< The alignment for the pool. unsigned PoolAlignment; ///< The alignment for the pool.
std::vector<MachineConstantPoolEntry> Constants; ///< The pool of constan ts. std::vector<MachineConstantPoolEntry> Constants; ///< The pool of constan ts.
/// MachineConstantPoolValues that use an existing MachineConstantPoolEnt ry. /// MachineConstantPoolValues that use an existing MachineConstantPoolEnt ry.
DenseSet<MachineConstantPoolValue*> MachineCPVsSharingEntries; DenseSet<MachineConstantPoolValue*> MachineCPVsSharingEntries;
public: public:
/// @brief The only constructor. /// @brief The only constructor.
explicit MachineConstantPool(const TargetData *td) explicit MachineConstantPool(const DataLayout *td)
: TD(td), PoolAlignment(1) {} : TD(td), PoolAlignment(1) {}
~MachineConstantPool(); ~MachineConstantPool();
/// getConstantPoolAlignment - Return the alignment required by /// getConstantPoolAlignment - Return the alignment required by
/// the whole constant pool, of which the first element must be aligned. /// the whole constant pool, of which the first element must be aligned.
unsigned getConstantPoolAlignment() const { return PoolAlignment; } unsigned getConstantPoolAlignment() const { return PoolAlignment; }
/// getConstantPoolIndex - Create a new entry in the constant pool or ret urn /// getConstantPoolIndex - Create a new entry in the constant pool or ret urn
/// an existing one. User must specify the minimum required alignment fo r /// an existing one. User must specify the minimum required alignment fo r
/// the object. /// the object.
 End of changes. 3 change blocks. 
3 lines changed or deleted 3 lines changed or added


 MachineFrameInfo.h   MachineFrameInfo.h 
skipping to change at line 24 skipping to change at line 24
#ifndef LLVM_CODEGEN_MACHINEFRAMEINFO_H #ifndef LLVM_CODEGEN_MACHINEFRAMEINFO_H
#define LLVM_CODEGEN_MACHINEFRAMEINFO_H #define LLVM_CODEGEN_MACHINEFRAMEINFO_H
#include "llvm/ADT/SmallVector.h" #include "llvm/ADT/SmallVector.h"
#include "llvm/Support/DataTypes.h" #include "llvm/Support/DataTypes.h"
#include <cassert> #include <cassert>
#include <vector> #include <vector>
namespace llvm { namespace llvm {
class raw_ostream; class raw_ostream;
class TargetData; class DataLayout;
class TargetRegisterClass; class TargetRegisterClass;
class Type; class Type;
class MachineFunction; class MachineFunction;
class MachineBasicBlock; class MachineBasicBlock;
class TargetFrameLowering; class TargetFrameLowering;
class BitVector; class BitVector;
class Value;
class AllocaInst;
/// The CalleeSavedInfo class tracks the information need to locate where a /// The CalleeSavedInfo class tracks the information need to locate where a
/// callee saved register is in the current frame. /// callee saved register is in the current frame.
class CalleeSavedInfo { class CalleeSavedInfo {
unsigned Reg; unsigned Reg;
int FrameIdx; int FrameIdx;
public: public:
explicit CalleeSavedInfo(unsigned R, int FI = 0) explicit CalleeSavedInfo(unsigned R, int FI = 0)
: Reg(R), FrameIdx(FI) {} : Reg(R), FrameIdx(FI) {}
skipping to change at line 106 skipping to change at line 108
// isSpillSlot - If true the stack object is used as spill slot. It // isSpillSlot - If true the stack object is used as spill slot. It
// cannot alias any other memory objects. // cannot alias any other memory objects.
bool isSpillSlot; bool isSpillSlot;
// MayNeedSP - If true the stack object triggered the creation of the s tack // MayNeedSP - If true the stack object triggered the creation of the s tack
// protector. We should allocate this object right after the stack // protector. We should allocate this object right after the stack
// protector. // protector.
bool MayNeedSP; bool MayNeedSP;
/// Alloca - If this stack object is originated from an Alloca instruct
ion
/// this value saves the original IR allocation. Can be NULL.
const AllocaInst *Alloca;
// PreAllocated - If true, the object was mapped into the local frame // PreAllocated - If true, the object was mapped into the local frame
// block and doesn't need additional handling for allocation beyond tha t. // block and doesn't need additional handling for allocation beyond tha t.
bool PreAllocated; bool PreAllocated;
StackObject(uint64_t Sz, unsigned Al, int64_t SP, bool IM, StackObject(uint64_t Sz, unsigned Al, int64_t SP, bool IM,
bool isSS, bool NSP) bool isSS, bool NSP, const AllocaInst *Val)
: SPOffset(SP), Size(Sz), Alignment(Al), isImmutable(IM), : SPOffset(SP), Size(Sz), Alignment(Al), isImmutable(IM),
isSpillSlot(isSS), MayNeedSP(NSP), PreAllocated(false) {} isSpillSlot(isSS), MayNeedSP(NSP), Alloca(Val), PreAllocated(false) {}
}; };
/// Objects - The list of stack objects allocated... /// Objects - The list of stack objects allocated...
/// ///
std::vector<StackObject> Objects; std::vector<StackObject> Objects;
/// NumFixedObjects - This contains the number of fixed objects contained on /// NumFixedObjects - This contains the number of fixed objects contained on
/// the stack. Because fixed objects are stored at a negative index in t he /// the stack. Because fixed objects are stored at a negative index in t he
/// Objects list, this is also the index to the 0th object in the list. /// Objects list, this is also the index to the 0th object in the list.
/// ///
skipping to change at line 362 skipping to change at line 368
assert(unsigned(ObjectIdx+NumFixedObjects) < Objects.size() && assert(unsigned(ObjectIdx+NumFixedObjects) < Objects.size() &&
"Invalid Object Idx!"); "Invalid Object Idx!");
return Objects[ObjectIdx+NumFixedObjects].Alignment; return Objects[ObjectIdx+NumFixedObjects].Alignment;
} }
/// setObjectAlignment - Change the alignment of the specified stack obje ct. /// setObjectAlignment - Change the alignment of the specified stack obje ct.
void setObjectAlignment(int ObjectIdx, unsigned Align) { void setObjectAlignment(int ObjectIdx, unsigned Align) {
assert(unsigned(ObjectIdx+NumFixedObjects) < Objects.size() && assert(unsigned(ObjectIdx+NumFixedObjects) < Objects.size() &&
"Invalid Object Idx!"); "Invalid Object Idx!");
Objects[ObjectIdx+NumFixedObjects].Alignment = Align; Objects[ObjectIdx+NumFixedObjects].Alignment = Align;
MaxAlignment = std::max(MaxAlignment, Align); ensureMaxAlignment(Align);
}
/// getObjectAllocation - Return the underlying Alloca of the specified
/// stack object if it exists. Returns 0 if none exists.
const AllocaInst* getObjectAllocation(int ObjectIdx) const {
assert(unsigned(ObjectIdx+NumFixedObjects) < Objects.size() &&
"Invalid Object Idx!");
return Objects[ObjectIdx+NumFixedObjects].Alloca;
} }
/// NeedsStackProtector - Returns true if the object may need stack /// NeedsStackProtector - Returns true if the object may need stack
/// protectors. /// protectors.
bool MayNeedStackProtector(int ObjectIdx) const { bool MayNeedStackProtector(int ObjectIdx) const {
assert(unsigned(ObjectIdx+NumFixedObjects) < Objects.size() && assert(unsigned(ObjectIdx+NumFixedObjects) < Objects.size() &&
"Invalid Object Idx!"); "Invalid Object Idx!");
return Objects[ObjectIdx+NumFixedObjects].MayNeedSP; return Objects[ObjectIdx+NumFixedObjects].MayNeedSP;
} }
skipping to change at line 419 skipping to change at line 433
/// setOffsetAdjustment - Set the correction for frame offsets. /// setOffsetAdjustment - Set the correction for frame offsets.
/// ///
void setOffsetAdjustment(int Adj) { OffsetAdjustment = Adj; } void setOffsetAdjustment(int Adj) { OffsetAdjustment = Adj; }
/// getMaxAlignment - Return the alignment in bytes that this function mu st be /// getMaxAlignment - Return the alignment in bytes that this function mu st be
/// aligned to, which is greater than the default stack alignment provide d by /// aligned to, which is greater than the default stack alignment provide d by
/// the target. /// the target.
/// ///
unsigned getMaxAlignment() const { return MaxAlignment; } unsigned getMaxAlignment() const { return MaxAlignment; }
/// setMaxAlignment - Set the preferred alignment. /// ensureMaxAlignment - Make sure the function is at least Align bytes
/// /// aligned.
void setMaxAlignment(unsigned Align) { MaxAlignment = Align; } void ensureMaxAlignment(unsigned Align) {
if (MaxAlignment < Align) MaxAlignment = Align;
}
/// AdjustsStack - Return true if this function adjusts the stack -- e.g. , /// AdjustsStack - Return true if this function adjusts the stack -- e.g. ,
/// when calling another function. This is only valid during and after /// when calling another function. This is only valid during and after
/// prolog/epilog code insertion. /// prolog/epilog code insertion.
bool adjustsStack() const { return AdjustsStack; } bool adjustsStack() const { return AdjustsStack; }
void setAdjustsStack(bool V) { AdjustsStack = V; } void setAdjustsStack(bool V) { AdjustsStack = V; }
/// hasCalls - Return true if the current function has any function calls . /// hasCalls - Return true if the current function has any function calls .
bool hasCalls() const { return HasCalls; } bool hasCalls() const { return HasCalls; }
void setHasCalls(bool V) { HasCalls = V; } void setHasCalls(bool V) { HasCalls = V; }
skipping to change at line 482 skipping to change at line 498
bool isDeadObjectIndex(int ObjectIdx) const { bool isDeadObjectIndex(int ObjectIdx) const {
assert(unsigned(ObjectIdx+NumFixedObjects) < Objects.size() && assert(unsigned(ObjectIdx+NumFixedObjects) < Objects.size() &&
"Invalid Object Idx!"); "Invalid Object Idx!");
return Objects[ObjectIdx+NumFixedObjects].Size == ~0ULL; return Objects[ObjectIdx+NumFixedObjects].Size == ~0ULL;
} }
/// CreateStackObject - Create a new statically sized stack object, retur ning /// CreateStackObject - Create a new statically sized stack object, retur ning
/// a nonnegative identifier to represent it. /// a nonnegative identifier to represent it.
/// ///
int CreateStackObject(uint64_t Size, unsigned Alignment, bool isSS, int CreateStackObject(uint64_t Size, unsigned Alignment, bool isSS,
bool MayNeedSP = false) { bool MayNeedSP = false, const AllocaInst *Alloca = 0) {
assert(Size != 0 && "Cannot allocate zero size stack objects!"); assert(Size != 0 && "Cannot allocate zero size stack objects!");
Objects.push_back(StackObject(Size, Alignment, 0, false, isSS, MayNeedS Objects.push_back(StackObject(Size, Alignment, 0, false, isSS, MayNeedS
P)); P,
Alloca));
int Index = (int)Objects.size() - NumFixedObjects - 1; int Index = (int)Objects.size() - NumFixedObjects - 1;
assert(Index >= 0 && "Bad frame index!"); assert(Index >= 0 && "Bad frame index!");
MaxAlignment = std::max(MaxAlignment, Alignment); ensureMaxAlignment(Alignment);
return Index; return Index;
} }
/// CreateSpillStackObject - Create a new statically sized stack object t hat /// CreateSpillStackObject - Create a new statically sized stack object t hat
/// represents a spill slot, returning a nonnegative identifier to repres ent /// represents a spill slot, returning a nonnegative identifier to repres ent
/// it. /// it.
/// ///
int CreateSpillStackObject(uint64_t Size, unsigned Alignment) { int CreateSpillStackObject(uint64_t Size, unsigned Alignment) {
CreateStackObject(Size, Alignment, true, false); CreateStackObject(Size, Alignment, true, false);
int Index = (int)Objects.size() - NumFixedObjects - 1; int Index = (int)Objects.size() - NumFixedObjects - 1;
MaxAlignment = std::max(MaxAlignment, Alignment); ensureMaxAlignment(Alignment);
return Index; return Index;
} }
/// RemoveStackObject - Remove or mark dead a statically sized stack obje ct. /// RemoveStackObject - Remove or mark dead a statically sized stack obje ct.
/// ///
void RemoveStackObject(int ObjectIdx) { void RemoveStackObject(int ObjectIdx) {
// Mark it dead. // Mark it dead.
Objects[ObjectIdx+NumFixedObjects].Size = ~0ULL; Objects[ObjectIdx+NumFixedObjects].Size = ~0ULL;
} }
/// CreateVariableSizedObject - Notify the MachineFrameInfo object that a /// CreateVariableSizedObject - Notify the MachineFrameInfo object that a
/// variable sized object has been created. This must be created wheneve r a /// variable sized object has been created. This must be created wheneve r a
/// variable sized object is created, whether or not the index returned i s /// variable sized object is created, whether or not the index returned i s
/// actually used. /// actually used.
/// ///
int CreateVariableSizedObject(unsigned Alignment) { int CreateVariableSizedObject(unsigned Alignment) {
HasVarSizedObjects = true; HasVarSizedObjects = true;
Objects.push_back(StackObject(0, Alignment, 0, false, false, true)); Objects.push_back(StackObject(0, Alignment, 0, false, false, true, 0));
MaxAlignment = std::max(MaxAlignment, Alignment); ensureMaxAlignment(Alignment);
return (int)Objects.size()-NumFixedObjects-1; return (int)Objects.size()-NumFixedObjects-1;
} }
/// getCalleeSavedInfo - Returns a reference to call saved info vector fo r the /// getCalleeSavedInfo - Returns a reference to call saved info vector fo r the
/// current function. /// current function.
const std::vector<CalleeSavedInfo> &getCalleeSavedInfo() const { const std::vector<CalleeSavedInfo> &getCalleeSavedInfo() const {
return CSInfo; return CSInfo;
} }
/// setCalleeSavedInfo - Used by prolog/epilog inserter to set the functi on's /// setCalleeSavedInfo - Used by prolog/epilog inserter to set the functi on's
 End of changes. 12 change blocks. 
14 lines changed or deleted 32 lines changed or added


 MachineFunction.h   MachineFunction.h 
skipping to change at line 130 skipping to change at line 130
/// Alignment - The alignment of the function. /// Alignment - The alignment of the function.
unsigned Alignment; unsigned Alignment;
/// ExposesReturnsTwice - True if the function calls setjmp or related /// ExposesReturnsTwice - True if the function calls setjmp or related
/// functions with attribute "returns twice", but doesn't have /// functions with attribute "returns twice", but doesn't have
/// the attribute itself. /// the attribute itself.
/// This is used to limit optimizations which cannot reason /// This is used to limit optimizations which cannot reason
/// about the control flow of such functions. /// about the control flow of such functions.
bool ExposesReturnsTwice; bool ExposesReturnsTwice;
MachineFunction(const MachineFunction &); // DO NOT IMPLEMENT MachineFunction(const MachineFunction &) LLVM_DELETED_FUNCTION;
void operator=(const MachineFunction&); // DO NOT IMPLEMENT void operator=(const MachineFunction&) LLVM_DELETED_FUNCTION;
public: public:
MachineFunction(const Function *Fn, const TargetMachine &TM, MachineFunction(const Function *Fn, const TargetMachine &TM,
unsigned FunctionNum, MachineModuleInfo &MMI, unsigned FunctionNum, MachineModuleInfo &MMI,
GCModuleInfo* GMI); GCModuleInfo* GMI);
~MachineFunction(); ~MachineFunction();
MachineModuleInfo &getMMI() const { return MMI; } MachineModuleInfo &getMMI() const { return MMI; }
GCModuleInfo *getGMI() const { return GMI; } GCModuleInfo *getGMI() const { return GMI; }
MCContext &getContext() const { return Ctx; } MCContext &getContext() const { return Ctx; }
/// getFunction - Return the LLVM function that this machine code represe nts /// getFunction - Return the LLVM function that this machine code represe nts
/// ///
const Function *getFunction() const { return Fn; } const Function *getFunction() const { return Fn; }
/// getName - Return the name of the corresponding LLVM function.
///
StringRef getName() const;
/// getFunctionNumber - Return a unique ID for the current function. /// getFunctionNumber - Return a unique ID for the current function.
/// ///
unsigned getFunctionNumber() const { return FunctionNumber; } unsigned getFunctionNumber() const { return FunctionNumber; }
/// getTarget - Return the target machine this machine code is compiled w ith /// getTarget - Return the target machine this machine code is compiled w ith
/// ///
const TargetMachine &getTarget() const { return Target; } const TargetMachine &getTarget() const { return Target; }
/// getRegInfo - Return information about the registers currently in use. /// getRegInfo - Return information about the registers currently in use.
/// ///
skipping to change at line 191 skipping to change at line 195
const MachineConstantPool *getConstantPool() const { return ConstantPool; } const MachineConstantPool *getConstantPool() const { return ConstantPool; }
/// getAlignment - Return the alignment (log2, not bytes) of the function . /// getAlignment - Return the alignment (log2, not bytes) of the function .
/// ///
unsigned getAlignment() const { return Alignment; } unsigned getAlignment() const { return Alignment; }
/// setAlignment - Set the alignment (log2, not bytes) of the function. /// setAlignment - Set the alignment (log2, not bytes) of the function.
/// ///
void setAlignment(unsigned A) { Alignment = A; } void setAlignment(unsigned A) { Alignment = A; }
/// EnsureAlignment - Make sure the function is at least 1 << A bytes ali /// ensureAlignment - Make sure the function is at least 1 << A bytes ali
gned. gned.
void EnsureAlignment(unsigned A) { void ensureAlignment(unsigned A) {
if (Alignment < A) Alignment = A; if (Alignment < A) Alignment = A;
} }
/// exposesReturnsTwice - Returns true if the function calls setjmp or /// exposesReturnsTwice - Returns true if the function calls setjmp or
/// any other similar functions with attribute "returns twice" without /// any other similar functions with attribute "returns twice" without
/// having the attribute itself. /// having the attribute itself.
bool exposesReturnsTwice() const { bool exposesReturnsTwice() const {
return ExposesReturnsTwice; return ExposesReturnsTwice;
} }
 End of changes. 3 change blocks. 
5 lines changed or deleted 9 lines changed or added


 MachineInstr.h   MachineInstr.h 
skipping to change at line 28 skipping to change at line 28
#include "llvm/CodeGen/MachineOperand.h" #include "llvm/CodeGen/MachineOperand.h"
#include "llvm/MC/MCInstrDesc.h" #include "llvm/MC/MCInstrDesc.h"
#include "llvm/Target/TargetOpcodes.h" #include "llvm/Target/TargetOpcodes.h"
#include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/ilist.h" #include "llvm/ADT/ilist.h"
#include "llvm/ADT/ilist_node.h" #include "llvm/ADT/ilist_node.h"
#include "llvm/ADT/STLExtras.h" #include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/StringRef.h" #include "llvm/ADT/StringRef.h"
#include "llvm/ADT/DenseMapInfo.h" #include "llvm/ADT/DenseMapInfo.h"
#include "llvm/InlineAsm.h"
#include "llvm/Support/DebugLoc.h" #include "llvm/Support/DebugLoc.h"
#include <vector> #include <vector>
namespace llvm { namespace llvm {
template <typename T> class SmallVectorImpl; template <typename T> class SmallVectorImpl;
class AliasAnalysis; class AliasAnalysis;
class TargetInstrInfo; class TargetInstrInfo;
class TargetRegisterClass; class TargetRegisterClass;
class TargetRegisterInfo; class TargetRegisterInfo;
skipping to change at line 84 skipping to change at line 85
// anything other than to convey co mment // anything other than to convey co mment
// information to AsmPrinter. // information to AsmPrinter.
uint16_t NumMemRefs; // information on memory references uint16_t NumMemRefs; // information on memory references
mmo_iterator MemRefs; mmo_iterator MemRefs;
std::vector<MachineOperand> Operands; // the operands std::vector<MachineOperand> Operands; // the operands
MachineBasicBlock *Parent; // Pointer to the owning basic bloc k. MachineBasicBlock *Parent; // Pointer to the owning basic bloc k.
DebugLoc debugLoc; // Source line information. DebugLoc debugLoc; // Source line information.
MachineInstr(const MachineInstr&); // DO NOT IMPLEMENT MachineInstr(const MachineInstr&) LLVM_DELETED_FUNCTION;
void operator=(const MachineInstr&); // DO NOT IMPLEMENT void operator=(const MachineInstr&) LLVM_DELETED_FUNCTION;
// Intrusive list support // Intrusive list support
friend struct ilist_traits<MachineInstr>; friend struct ilist_traits<MachineInstr>;
friend struct ilist_traits<MachineBasicBlock>; friend struct ilist_traits<MachineBasicBlock>;
void setParent(MachineBasicBlock *P) { Parent = P; } void setParent(MachineBasicBlock *P) { Parent = P; }
/// MachineInstr ctor - This constructor creates a copy of the given /// MachineInstr ctor - This constructor creates a copy of the given
/// MachineInstr in the given MachineFunction. /// MachineInstr in the given MachineFunction.
MachineInstr(MachineFunction &, const MachineInstr &); MachineInstr(MachineFunction &, const MachineInstr &);
/// MachineInstr ctor - This constructor creates a dummy MachineInstr wit h /// MachineInstr ctor - This constructor creates a dummy MachineInstr wit h
/// MCID NULL and no operands. /// MCID NULL and no operands.
MachineInstr(); MachineInstr();
// The next two constructors have DebugLoc and non-DebugLoc versions;
// over time, the non-DebugLoc versions should be phased out and eventual
ly
// removed.
/// MachineInstr ctor - This constructor creates a MachineInstr and adds
the
/// implicit operands. It reserves space for the number of operands spec
ified
/// by the MCInstrDesc. The version with a DebugLoc should be preferred.
explicit MachineInstr(const MCInstrDesc &MCID, bool NoImp = false);
/// MachineInstr ctor - Work exactly the same as the ctor above, except t
hat
/// the MachineInstr is created and added to the end of the specified bas
ic
/// block. The version with a DebugLoc should be preferred.
MachineInstr(MachineBasicBlock *MBB, const MCInstrDesc &MCID);
/// MachineInstr ctor - This constructor create a MachineInstr and add th e /// MachineInstr ctor - This constructor create a MachineInstr and add th e
/// implicit operands. It reserves space for number of operands specifie d by /// implicit operands. It reserves space for number of operands specifie d by
/// MCInstrDesc. An explicit DebugLoc is supplied. /// MCInstrDesc. An explicit DebugLoc is supplied.
explicit MachineInstr(const MCInstrDesc &MCID, const DebugLoc dl, MachineInstr(const MCInstrDesc &MCID, const DebugLoc dl, bool NoImp = fal
bool NoImp = false); se);
/// MachineInstr ctor - Work exactly the same as the ctor above, except t hat /// MachineInstr ctor - Work exactly the same as the ctor above, except t hat
/// the MachineInstr is created and added to the end of the specified bas ic /// the MachineInstr is created and added to the end of the specified bas ic
/// block. /// block.
MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl, MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl,
const MCInstrDesc &MCID); const MCInstrDesc &MCID);
~MachineInstr(); ~MachineInstr();
// MachineInstrs are pool-allocated and owned by MachineFunction. // MachineInstrs are pool-allocated and owned by MachineFunction.
skipping to change at line 423 skipping to change at line 409
bool isMoveImmediate(QueryType Type = IgnoreBundle) const { bool isMoveImmediate(QueryType Type = IgnoreBundle) const {
return hasProperty(MCID::MoveImm, Type); return hasProperty(MCID::MoveImm, Type);
} }
/// isBitcast - Return true if this instruction is a bitcast instruction. /// isBitcast - Return true if this instruction is a bitcast instruction.
/// ///
bool isBitcast(QueryType Type = IgnoreBundle) const { bool isBitcast(QueryType Type = IgnoreBundle) const {
return hasProperty(MCID::Bitcast, Type); return hasProperty(MCID::Bitcast, Type);
} }
/// isSelect - Return true if this instruction is a select instruction.
///
bool isSelect(QueryType Type = IgnoreBundle) const {
return hasProperty(MCID::Select, Type);
}
/// isNotDuplicable - Return true if this instruction cannot be safely /// isNotDuplicable - Return true if this instruction cannot be safely
/// duplicated. For example, if the instruction has a unique labels atta ched /// duplicated. For example, if the instruction has a unique labels atta ched
/// to it, duplicating it would cause multiple definition errors. /// to it, duplicating it would cause multiple definition errors.
bool isNotDuplicable(QueryType Type = AnyInBundle) const { bool isNotDuplicable(QueryType Type = AnyInBundle) const {
return hasProperty(MCID::NotDuplicable, Type); return hasProperty(MCID::NotDuplicable, Type);
} }
/// hasDelaySlot - Returns true if the specified instruction has a delay slot /// hasDelaySlot - Returns true if the specified instruction has a delay slot
/// which must be filled by the code generator. /// which must be filled by the code generator.
bool hasDelaySlot(QueryType Type = AnyInBundle) const { bool hasDelaySlot(QueryType Type = AnyInBundle) const {
skipping to change at line 456 skipping to change at line 448
} }
//===-------------------------------------------------------------------- ===// //===-------------------------------------------------------------------- ===//
// Side Effect Analysis // Side Effect Analysis
//===-------------------------------------------------------------------- ===// //===-------------------------------------------------------------------- ===//
/// mayLoad - Return true if this instruction could possibly read memory. /// mayLoad - Return true if this instruction could possibly read memory.
/// Instructions with this flag set are not necessarily simple load /// Instructions with this flag set are not necessarily simple load
/// instructions, they may load a value and modify it, for example. /// instructions, they may load a value and modify it, for example.
bool mayLoad(QueryType Type = AnyInBundle) const { bool mayLoad(QueryType Type = AnyInBundle) const {
if (isInlineAsm()) {
unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
if (ExtraInfo & InlineAsm::Extra_MayLoad)
return true;
}
return hasProperty(MCID::MayLoad, Type); return hasProperty(MCID::MayLoad, Type);
} }
/// mayStore - Return true if this instruction could possibly modify memo ry. /// mayStore - Return true if this instruction could possibly modify memo ry.
/// Instructions with this flag set are not necessarily simple store /// Instructions with this flag set are not necessarily simple store
/// instructions, they may store a modified value based on their operands , or /// instructions, they may store a modified value based on their operands , or
/// may not actually modify anything, for example. /// may not actually modify anything, for example.
bool mayStore(QueryType Type = AnyInBundle) const { bool mayStore(QueryType Type = AnyInBundle) const {
if (isInlineAsm()) {
unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
if (ExtraInfo & InlineAsm::Extra_MayStore)
return true;
}
return hasProperty(MCID::MayStore, Type); return hasProperty(MCID::MayStore, Type);
} }
//===-------------------------------------------------------------------- ===// //===-------------------------------------------------------------------- ===//
// Flags that indicate whether an instruction can be modified by a method . // Flags that indicate whether an instruction can be modified by a method .
//===-------------------------------------------------------------------- ===// //===-------------------------------------------------------------------- ===//
/// isCommutable - Return true if this may be a 2- or 3-address /// isCommutable - Return true if this may be a 2- or 3-address
/// instruction (of the form "X = op Y, Z, ..."), which produces the same /// instruction (of the form "X = op Y, Z, ..."), which produces the same
/// result if Y and Z are exchanged. If this flag is set, then the /// result if Y and Z are exchanged. If this flag is set, then the
skipping to change at line 605 skipping to change at line 607
} }
bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; } bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; } bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE ; } bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE ; }
bool isPHI() const { return getOpcode() == TargetOpcode::PHI; } bool isPHI() const { return getOpcode() == TargetOpcode::PHI; }
bool isKill() const { return getOpcode() == TargetOpcode::KILL; } bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_D EF; } bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_D EF; }
bool isInlineAsm() const { return getOpcode() == TargetOpcode::INLINEASM; } bool isInlineAsm() const { return getOpcode() == TargetOpcode::INLINEASM; }
bool isStackAligningInlineAsm() const; bool isStackAligningInlineAsm() const;
InlineAsm::AsmDialect getInlineAsmDialect() const;
bool isInsertSubreg() const { bool isInsertSubreg() const {
return getOpcode() == TargetOpcode::INSERT_SUBREG; return getOpcode() == TargetOpcode::INSERT_SUBREG;
} }
bool isSubregToReg() const { bool isSubregToReg() const {
return getOpcode() == TargetOpcode::SUBREG_TO_REG; return getOpcode() == TargetOpcode::SUBREG_TO_REG;
} }
bool isRegSequence() const { bool isRegSequence() const {
return getOpcode() == TargetOpcode::REG_SEQUENCE; return getOpcode() == TargetOpcode::REG_SEQUENCE;
} }
bool isBundle() const { bool isBundle() const {
skipping to change at line 636 skipping to change at line 639
bool isCopyLike() const { bool isCopyLike() const {
return isCopy() || isSubregToReg(); return isCopy() || isSubregToReg();
} }
/// isIdentityCopy - Return true is the instruction is an identity copy. /// isIdentityCopy - Return true is the instruction is an identity copy.
bool isIdentityCopy() const { bool isIdentityCopy() const {
return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() && return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() &&
getOperand(0).getSubReg() == getOperand(1).getSubReg(); getOperand(0).getSubReg() == getOperand(1).getSubReg();
} }
/// isTransient - Return true if this is a transient instruction that is
/// either very likely to be eliminated during register allocation (such
as
/// copy-like instructions), or if this instruction doesn't have an
/// execution-time cost.
bool isTransient() const {
switch(getOpcode()) {
default: return false;
// Copy-like instructions are usually eliminated during register alloca
tion.
case TargetOpcode::PHI:
case TargetOpcode::COPY:
case TargetOpcode::INSERT_SUBREG:
case TargetOpcode::SUBREG_TO_REG:
case TargetOpcode::REG_SEQUENCE:
// Pseudo-instructions that don't produce any real output.
case TargetOpcode::IMPLICIT_DEF:
case TargetOpcode::KILL:
case TargetOpcode::PROLOG_LABEL:
case TargetOpcode::EH_LABEL:
case TargetOpcode::GC_LABEL:
case TargetOpcode::DBG_VALUE:
return true;
}
}
/// getBundleSize - Return the number of instructions inside the MI bundl e. /// getBundleSize - Return the number of instructions inside the MI bundl e.
unsigned getBundleSize() const; unsigned getBundleSize() const;
/// readsRegister - Return true if the MachineInstr reads the specified /// readsRegister - Return true if the MachineInstr reads the specified
/// register. If TargetRegisterInfo is passed, then it also checks if the re /// register. If TargetRegisterInfo is passed, then it also checks if the re
/// is a read of a super-register. /// is a read of a super-register.
/// This does not count partial redefines of virtual registers as reads: /// This does not count partial redefines of virtual registers as reads:
/// %reg1024:6 = OP. /// %reg1024:6 = OP.
bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) co nst { bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) co nst {
return findRegisterUseOperandIdx(Reg, false, TRI) != -1; return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
skipping to change at line 753 skipping to change at line 780
/// MCInstrDesc. For inline assembly it is derived from the flag words. /// MCInstrDesc. For inline assembly it is derived from the flag words.
/// ///
/// Returns NULL if the static register classs constraint cannot be /// Returns NULL if the static register classs constraint cannot be
/// determined. /// determined.
/// ///
const TargetRegisterClass* const TargetRegisterClass*
getRegClassConstraint(unsigned OpIdx, getRegClassConstraint(unsigned OpIdx,
const TargetInstrInfo *TII, const TargetInstrInfo *TII,
const TargetRegisterInfo *TRI) const; const TargetRegisterInfo *TRI) const;
/// tieOperands - Add a tie between the register operands at DefIdx and
/// UseIdx. The tie will cause the register allocator to ensure that the
two
/// operands are assigned the same physical register.
///
/// Tied operands are managed automatically for explicit operands in the
/// MCInstrDesc. This method is for exceptional cases like inline asm.
void tieOperands(unsigned DefIdx, unsigned UseIdx);
/// findTiedOperandIdx - Given the index of a tied register operand, find
the
/// operand it is tied to. Defs are tied to uses and vice versa. Returns
the
/// index of the tied operand which must exist.
unsigned findTiedOperandIdx(unsigned OpIdx) const;
/// isRegTiedToUseOperand - Given the index of a register def operand, /// isRegTiedToUseOperand - Given the index of a register def operand,
/// check if the register def is tied to a source operand, due to either /// check if the register def is tied to a source operand, due to either
/// two-address elimination or inline assembly constraints. Returns the /// two-address elimination or inline assembly constraints. Returns the
/// first tied use operand index by reference if UseOpIdx is not null. /// first tied use operand index by reference if UseOpIdx is not null.
bool isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx = 0) con bool isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx = 0) con
st; st {
const MachineOperand &MO = getOperand(DefOpIdx);
if (!MO.isReg() || !MO.isDef() || !MO.isTied())
return false;
if (UseOpIdx)
*UseOpIdx = findTiedOperandIdx(DefOpIdx);
return true;
}
/// isRegTiedToDefOperand - Return true if the use operand of the specifi ed /// isRegTiedToDefOperand - Return true if the use operand of the specifi ed
/// index is tied to an def operand. It also returns the def operand inde x by /// index is tied to an def operand. It also returns the def operand inde x by
/// reference if DefOpIdx is not null. /// reference if DefOpIdx is not null.
bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx = 0) con bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx = 0) con
st; st {
const MachineOperand &MO = getOperand(UseOpIdx);
if (!MO.isReg() || !MO.isUse() || !MO.isTied())
return false;
if (DefOpIdx)
*DefOpIdx = findTiedOperandIdx(UseOpIdx);
return true;
}
/// clearKillInfo - Clears kill flags on all operands. /// clearKillInfo - Clears kill flags on all operands.
/// ///
void clearKillInfo(); void clearKillInfo();
/// copyKillDeadInfo - Copies kill / dead operand properties from MI. /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
/// ///
void copyKillDeadInfo(const MachineInstr *MI); void copyKillDeadInfo(const MachineInstr *MI);
/// copyPredicates - Copies predicate operand(s) from MI. /// copyPredicates - Copies predicate operand(s) from MI.
skipping to change at line 823 skipping to change at line 877
/// SawStore is set to true, it means that there is a store (or call) bet ween /// SawStore is set to true, it means that there is a store (or call) bet ween
/// the instruction's location and its intended destination. /// the instruction's location and its intended destination.
bool isSafeToMove(const TargetInstrInfo *TII, AliasAnalysis *AA, bool isSafeToMove(const TargetInstrInfo *TII, AliasAnalysis *AA,
bool &SawStore) const; bool &SawStore) const;
/// isSafeToReMat - Return true if it's safe to rematerialize the specifi ed /// isSafeToReMat - Return true if it's safe to rematerialize the specifi ed
/// instruction which defined the specified register instead of copying i t. /// instruction which defined the specified register instead of copying i t.
bool isSafeToReMat(const TargetInstrInfo *TII, AliasAnalysis *AA, bool isSafeToReMat(const TargetInstrInfo *TII, AliasAnalysis *AA,
unsigned DstReg) const; unsigned DstReg) const;
/// hasVolatileMemoryRef - Return true if this instruction may have a /// hasOrderedMemoryRef - Return true if this instruction may have an ord
/// volatile memory reference, or if the information describing the ered
/// memory reference is not available. Return false if it is known to /// or volatile memory reference, or if the information describing the me
/// have no volatile memory references. mory
bool hasVolatileMemoryRef() const; /// reference is not available. Return false if it is known to have no
/// ordered or volatile memory references.
bool hasOrderedMemoryRef() const;
/// isInvariantLoad - Return true if this instruction is loading from a /// isInvariantLoad - Return true if this instruction is loading from a
/// location whose value is invariant across the function. For example, /// location whose value is invariant across the function. For example,
/// loading a value from the constant pool or from the argument area of /// loading a value from the constant pool or from the argument area of
/// a function if it does not change. This should only return true of *a ll* /// a function if it does not change. This should only return true of *a ll*
/// loads the instruction does are invariant (if it does multiple loads). /// loads the instruction does are invariant (if it does multiple loads).
bool isInvariantLoad(AliasAnalysis *AA) const; bool isInvariantLoad(AliasAnalysis *AA) const;
/// isConstantValuePHI - If the specified instruction is a PHI that alway s /// isConstantValuePHI - If the specified instruction is a PHI that alway s
/// merges together the same virtual register, return the register, other wise /// merges together the same virtual register, return the register, other wise
skipping to change at line 906 skipping to change at line 960
MemRefs = NewMemRefs; MemRefs = NewMemRefs;
NumMemRefs = NewMemRefsEnd - NewMemRefs; NumMemRefs = NewMemRefsEnd - NewMemRefs;
} }
private: private:
/// getRegInfo - If this instruction is embedded into a MachineFunction, /// getRegInfo - If this instruction is embedded into a MachineFunction,
/// return the MachineRegisterInfo object for the current function, other wise /// return the MachineRegisterInfo object for the current function, other wise
/// return null. /// return null.
MachineRegisterInfo *getRegInfo(); MachineRegisterInfo *getRegInfo();
/// untieRegOperand - Break any tie involving OpIdx.
void untieRegOperand(unsigned OpIdx) {
MachineOperand &MO = getOperand(OpIdx);
if (MO.isReg() && MO.isTied()) {
getOperand(findTiedOperandIdx(OpIdx)).TiedTo = 0;
MO.TiedTo = 0;
}
}
/// addImplicitDefUseOperands - Add all implicit def and use operands to /// addImplicitDefUseOperands - Add all implicit def and use operands to
/// this instruction. /// this instruction.
void addImplicitDefUseOperands(); void addImplicitDefUseOperands();
/// RemoveRegOperandsFromUseLists - Unlink all of the register operands i n /// RemoveRegOperandsFromUseLists - Unlink all of the register operands i n
/// this instruction from their respective use lists. This requires that the /// this instruction from their respective use lists. This requires that the
/// operands already be on their use lists. /// operands already be on their use lists.
void RemoveRegOperandsFromUseLists(); void RemoveRegOperandsFromUseLists(MachineRegisterInfo&);
/// AddRegOperandsToUseLists - Add all of the register operands in /// AddRegOperandsToUseLists - Add all of the register operands in
/// this instruction from their respective use lists. This requires that the /// this instruction from their respective use lists. This requires that the
/// operands not be on their use lists yet. /// operands not be on their use lists yet.
void AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo); void AddRegOperandsToUseLists(MachineRegisterInfo&);
/// hasPropertyInBundle - Slow path for hasProperty when we're dealing wi th a /// hasPropertyInBundle - Slow path for hasProperty when we're dealing wi th a
/// bundle. /// bundle.
bool hasPropertyInBundle(unsigned Mask, QueryType Type) const; bool hasPropertyInBundle(unsigned Mask, QueryType Type) const;
}; };
/// MachineInstrExpressionTrait - Special DenseMapInfo traits to compare /// MachineInstrExpressionTrait - Special DenseMapInfo traits to compare
/// MachineInstr* by *value* of the instruction rather than by pointer valu e. /// MachineInstr* by *value* of the instruction rather than by pointer valu e.
/// The hashing and equality testing functions ignore definitions so this i s /// The hashing and equality testing functions ignore definitions so this i s
/// useful for CSE, etc. /// useful for CSE, etc.
 End of changes. 16 change blocks. 
34 lines changed or deleted 100 lines changed or added


 MachineInstrBuilder.h   MachineInstrBuilder.h 
skipping to change at line 37 skipping to change at line 37
namespace RegState { namespace RegState {
enum { enum {
Define = 0x2, Define = 0x2,
Implicit = 0x4, Implicit = 0x4,
Kill = 0x8, Kill = 0x8,
Dead = 0x10, Dead = 0x10,
Undef = 0x20, Undef = 0x20,
EarlyClobber = 0x40, EarlyClobber = 0x40,
Debug = 0x80, Debug = 0x80,
InternalRead = 0x100,
DefineNoRead = Define | Undef, DefineNoRead = Define | Undef,
ImplicitDefine = Implicit | Define, ImplicitDefine = Implicit | Define,
ImplicitKill = Implicit | Kill ImplicitKill = Implicit | Kill
}; };
} }
class MachineInstrBuilder { class MachineInstrBuilder {
MachineInstr *MI; MachineInstr *MI;
public: public:
MachineInstrBuilder() : MI(0) {} MachineInstrBuilder() : MI(0) {}
skipping to change at line 70 skipping to change at line 71
assert((flags & 0x1) == 0 && assert((flags & 0x1) == 0 &&
"Passing in 'true' to addReg is forbidden! Use enums instead."); "Passing in 'true' to addReg is forbidden! Use enums instead.");
MI->addOperand(MachineOperand::CreateReg(RegNo, MI->addOperand(MachineOperand::CreateReg(RegNo,
flags & RegState::Define, flags & RegState::Define,
flags & RegState::Implicit, flags & RegState::Implicit,
flags & RegState::Kill, flags & RegState::Kill,
flags & RegState::Dead, flags & RegState::Dead,
flags & RegState::Undef, flags & RegState::Undef,
flags & RegState::EarlyClobber , flags & RegState::EarlyClobber ,
SubReg, SubReg,
flags & RegState::Debug)); flags & RegState::Debug,
flags & RegState::InternalRead
));
return *this; return *this;
} }
/// addImm - Add a new immediate operand. /// addImm - Add a new immediate operand.
/// ///
const MachineInstrBuilder &addImm(int64_t Val) const { const MachineInstrBuilder &addImm(int64_t Val) const {
MI->addOperand(MachineOperand::CreateImm(Val)); MI->addOperand(MachineOperand::CreateImm(Val));
return *this; return *this;
} }
skipping to change at line 109 skipping to change at line 111
return *this; return *this;
} }
const MachineInstrBuilder &addConstantPoolIndex(unsigned Idx, const MachineInstrBuilder &addConstantPoolIndex(unsigned Idx,
int Offset = 0, int Offset = 0,
unsigned char TargetFlags = 0) co nst { unsigned char TargetFlags = 0) co nst {
MI->addOperand(MachineOperand::CreateCPI(Idx, Offset, TargetFlags)); MI->addOperand(MachineOperand::CreateCPI(Idx, Offset, TargetFlags));
return *this; return *this;
} }
const MachineInstrBuilder &addTargetIndex(unsigned Idx, int64_t Offset =
0,
unsigned char TargetFlags = 0) co
nst {
MI->addOperand(MachineOperand::CreateTargetIndex(Idx, Offset, TargetFla
gs));
return *this;
}
const MachineInstrBuilder &addJumpTableIndex(unsigned Idx, const MachineInstrBuilder &addJumpTableIndex(unsigned Idx,
unsigned char TargetFlags = 0) co nst { unsigned char TargetFlags = 0) co nst {
MI->addOperand(MachineOperand::CreateJTI(Idx, TargetFlags)); MI->addOperand(MachineOperand::CreateJTI(Idx, TargetFlags));
return *this; return *this;
} }
const MachineInstrBuilder &addGlobalAddress(const GlobalValue *GV, const MachineInstrBuilder &addGlobalAddress(const GlobalValue *GV,
int64_t Offset = 0, int64_t Offset = 0,
unsigned char TargetFlags = 0) co nst { unsigned char TargetFlags = 0) co nst {
MI->addOperand(MachineOperand::CreateGA(GV, Offset, TargetFlags)); MI->addOperand(MachineOperand::CreateGA(GV, Offset, TargetFlags));
skipping to change at line 170 skipping to change at line 178
MI->setFlags(Flags); MI->setFlags(Flags);
return *this; return *this;
} }
const MachineInstrBuilder &setMIFlag(MachineInstr::MIFlag Flag) const { const MachineInstrBuilder &setMIFlag(MachineInstr::MIFlag Flag) const {
MI->setFlag(Flag); MI->setFlag(Flag);
return *this; return *this;
} }
// Add a displacement from an existing MachineOperand with an added offse t. // Add a displacement from an existing MachineOperand with an added offse t.
const MachineInstrBuilder &addDisp(const MachineOperand &Disp, const MachineInstrBuilder &addDisp(const MachineOperand &Disp, int64_t of
int64_t off) const { f,
unsigned char TargetFlags = 0) const {
switch (Disp.getType()) { switch (Disp.getType()) {
default: default:
llvm_unreachable("Unhandled operand type in addDisp()"); llvm_unreachable("Unhandled operand type in addDisp()");
case MachineOperand::MO_Immediate: case MachineOperand::MO_Immediate:
return addImm(Disp.getImm() + off); return addImm(Disp.getImm() + off);
case MachineOperand::MO_GlobalAddress: case MachineOperand::MO_GlobalAddress: {
return addGlobalAddress(Disp.getGlobal(), Disp.getOffset() + off); // If caller specifies new TargetFlags then use it, otherwise the
// default behavior is to copy the target flags from the existing
// MachineOperand. This means if the caller wants to clear the
// target flags it needs to do so explicitly.
if (TargetFlags)
return addGlobalAddress(Disp.getGlobal(), Disp.getOffset() + off,
TargetFlags);
return addGlobalAddress(Disp.getGlobal(), Disp.getOffset() + off,
Disp.getTargetFlags());
}
} }
} }
}; };
/// BuildMI - Builder interface. Specify how to create the initial instruc tion /// BuildMI - Builder interface. Specify how to create the initial instruc tion
/// itself. /// itself.
/// ///
inline MachineInstrBuilder BuildMI(MachineFunction &MF, inline MachineInstrBuilder BuildMI(MachineFunction &MF,
DebugLoc DL, DebugLoc DL,
const MCInstrDesc &MCID) { const MCInstrDesc &MCID) {
skipping to change at line 312 skipping to change at line 329
} }
inline unsigned getKillRegState(bool B) { inline unsigned getKillRegState(bool B) {
return B ? RegState::Kill : 0; return B ? RegState::Kill : 0;
} }
inline unsigned getDeadRegState(bool B) { inline unsigned getDeadRegState(bool B) {
return B ? RegState::Dead : 0; return B ? RegState::Dead : 0;
} }
inline unsigned getUndefRegState(bool B) { inline unsigned getUndefRegState(bool B) {
return B ? RegState::Undef : 0; return B ? RegState::Undef : 0;
} }
inline unsigned getInternalReadRegState(bool B) {
return B ? RegState::InternalRead : 0;
}
} // End llvm namespace } // End llvm namespace
#endif #endif
 End of changes. 6 change blocks. 
5 lines changed or deleted 30 lines changed or added


 MachineInstrBundle.h   MachineInstrBundle.h 
skipping to change at line 46 skipping to change at line 46
/// points to the end of the bundle. /// points to the end of the bundle.
MachineBasicBlock::instr_iterator finalizeBundle(MachineBasicBlock &MBB, MachineBasicBlock::instr_iterator finalizeBundle(MachineBasicBlock &MBB,
MachineBasicBlock::instr_iterator FirstMI); MachineBasicBlock::instr_iterator FirstMI);
/// finalizeBundles - Finalize instruction bundles in the specified /// finalizeBundles - Finalize instruction bundles in the specified
/// MachineFunction. Return true if any bundles are finalized. /// MachineFunction. Return true if any bundles are finalized.
bool finalizeBundles(MachineFunction &MF); bool finalizeBundles(MachineFunction &MF);
/// getBundleStart - Returns the first instruction in the bundle containing MI. /// getBundleStart - Returns the first instruction in the bundle containing MI.
/// ///
static inline MachineInstr *getBundleStart(MachineInstr *MI) { inline MachineInstr *getBundleStart(MachineInstr *MI) {
MachineBasicBlock::instr_iterator I = MI; MachineBasicBlock::instr_iterator I = MI;
while (I->isInsideBundle()) while (I->isInsideBundle())
--I; --I;
return I; return I;
} }
static inline const MachineInstr *getBundleStart(const MachineInstr *MI) { inline const MachineInstr *getBundleStart(const MachineInstr *MI) {
MachineBasicBlock::const_instr_iterator I = MI; MachineBasicBlock::const_instr_iterator I = MI;
while (I->isInsideBundle()) while (I->isInsideBundle())
--I; --I;
return I; return I;
} }
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// MachineOperand iterator // MachineOperand iterator
// //
skipping to change at line 133 skipping to change at line 133
advance(); advance();
} }
/// getOperandNo - Returns the number of the current operand relative to its /// getOperandNo - Returns the number of the current operand relative to its
/// instruction. /// instruction.
/// ///
unsigned getOperandNo() const { unsigned getOperandNo() const {
return OpI - InstrI->operands_begin(); return OpI - InstrI->operands_begin();
} }
/// RegInfo - Information about a virtual register used by a set of opera nds. /// VirtRegInfo - Information about a virtual register used by a set of o perands.
/// ///
struct RegInfo { struct VirtRegInfo {
/// Reads - One of the operands read the virtual register. This does n ot /// Reads - One of the operands read the virtual register. This does n ot
/// include <undef> or <internal> use operands, see MO::readsReg(). /// include <undef> or <internal> use operands, see MO::readsReg().
bool Reads; bool Reads;
/// Writes - One of the operands writes the virtual register. /// Writes - One of the operands writes the virtual register.
bool Writes; bool Writes;
/// Tied - Uses and defs must use the same register. This can be becaus e of /// Tied - Uses and defs must use the same register. This can be becaus e of
/// a two-address constraint, or there may be a partial redefinition of a /// a two-address constraint, or there may be a partial redefinition of a
/// sub-register. /// sub-register.
bool Tied; bool Tied;
}; };
/// PhysRegInfo - Information about a physical register used by a set of
/// operands.
struct PhysRegInfo {
/// Clobbers - Reg or an overlapping register is defined, or a regmask
/// clobbers Reg.
bool Clobbers;
/// Defines - Reg or a super-register is defined.
bool Defines;
/// DefinesOverlap - Reg or an overlapping register is defined.
bool DefinesOverlap;
/// Reads - Read or a super-register is read.
bool Reads;
/// ReadsOverlap - Reg or an overlapping register is read.
bool ReadsOverlap;
/// DefinesDead - All defs of a Reg or a super-register are dead.
bool DefinesDead;
/// There is a kill of Reg or a super-register.
bool Kills;
};
/// analyzeVirtReg - Analyze how the current instruction or bundle uses a /// analyzeVirtReg - Analyze how the current instruction or bundle uses a
/// virtual register. This function should not be called after operator+ +(), /// virtual register. This function should not be called after operator+ +(),
/// it expects a fresh iterator. /// it expects a fresh iterator.
/// ///
/// @param Reg The virtual register to analyze. /// @param Reg The virtual register to analyze.
/// @param Ops When set, this vector will receive an (MI, OpNum) entry fo r /// @param Ops When set, this vector will receive an (MI, OpNum) entry fo r
/// each operand referring to Reg. /// each operand referring to Reg.
/// @returns A filled-in RegInfo struct. /// @returns A filled-in RegInfo struct.
RegInfo analyzeVirtReg(unsigned Reg, VirtRegInfo analyzeVirtReg(unsigned Reg,
SmallVectorImpl<std::pair<MachineInstr*, unsigned> > *Ops = 0); SmallVectorImpl<std::pair<MachineInstr*, unsigned> > *Ops = 0);
/// analyzePhysReg - Analyze how the current instruction or bundle uses a
/// physical register. This function should not be called after operator
++(),
/// it expects a fresh iterator.
///
/// @param Reg The physical register to analyze.
/// @returns A filled-in PhysRegInfo struct.
PhysRegInfo analyzePhysReg(unsigned Reg, const TargetRegisterInfo *TRI);
}; };
/// MIOperands - Iterate over operands of a single instruction. /// MIOperands - Iterate over operands of a single instruction.
/// ///
class MIOperands : public MachineOperandIteratorBase { class MIOperands : public MachineOperandIteratorBase {
public: public:
MIOperands(MachineInstr *MI) : MachineOperandIteratorBase(MI, false) {} MIOperands(MachineInstr *MI) : MachineOperandIteratorBase(MI, false) {}
MachineOperand &operator* () const { return deref(); } MachineOperand &operator* () const { return deref(); }
MachineOperand *operator->() const { return &deref(); } MachineOperand *operator->() const { return &deref(); }
}; };
 End of changes. 7 change blocks. 
5 lines changed or deleted 40 lines changed or added


 MachineJumpTableInfo.h   MachineJumpTableInfo.h 
skipping to change at line 29 skipping to change at line 29
#ifndef LLVM_CODEGEN_MACHINEJUMPTABLEINFO_H #ifndef LLVM_CODEGEN_MACHINEJUMPTABLEINFO_H
#define LLVM_CODEGEN_MACHINEJUMPTABLEINFO_H #define LLVM_CODEGEN_MACHINEJUMPTABLEINFO_H
#include <vector> #include <vector>
#include <cassert> #include <cassert>
namespace llvm { namespace llvm {
class MachineBasicBlock; class MachineBasicBlock;
class TargetData; class DataLayout;
class raw_ostream; class raw_ostream;
/// MachineJumpTableEntry - One jump table in the jump table info. /// MachineJumpTableEntry - One jump table in the jump table info.
/// ///
struct MachineJumpTableEntry { struct MachineJumpTableEntry {
/// MBBs - The vector of basic blocks from which to create the jump table . /// MBBs - The vector of basic blocks from which to create the jump table .
std::vector<MachineBasicBlock*> MBBs; std::vector<MachineBasicBlock*> MBBs;
explicit MachineJumpTableEntry(const std::vector<MachineBasicBlock*> &M) explicit MachineJumpTableEntry(const std::vector<MachineBasicBlock*> &M)
: MBBs(M) {} : MBBs(M) {}
skipping to change at line 87 skipping to change at line 87
}; };
private: private:
JTEntryKind EntryKind; JTEntryKind EntryKind;
std::vector<MachineJumpTableEntry> JumpTables; std::vector<MachineJumpTableEntry> JumpTables;
public: public:
explicit MachineJumpTableInfo(JTEntryKind Kind): EntryKind(Kind) {} explicit MachineJumpTableInfo(JTEntryKind Kind): EntryKind(Kind) {}
JTEntryKind getEntryKind() const { return EntryKind; } JTEntryKind getEntryKind() const { return EntryKind; }
/// getEntrySize - Return the size of each entry in the jump table. /// getEntrySize - Return the size of each entry in the jump table.
unsigned getEntrySize(const TargetData &TD) const; unsigned getEntrySize(const DataLayout &TD) const;
/// getEntryAlignment - Return the alignment of each entry in the jump ta ble. /// getEntryAlignment - Return the alignment of each entry in the jump ta ble.
unsigned getEntryAlignment(const TargetData &TD) const; unsigned getEntryAlignment(const DataLayout &TD) const;
/// createJumpTableIndex - Create a new jump table. /// createJumpTableIndex - Create a new jump table.
/// ///
unsigned createJumpTableIndex(const std::vector<MachineBasicBlock*> &Dest BBs); unsigned createJumpTableIndex(const std::vector<MachineBasicBlock*> &Dest BBs);
/// isEmpty - Return true if there are no jump tables. /// isEmpty - Return true if there are no jump tables.
/// ///
bool isEmpty() const { return JumpTables.empty(); } bool isEmpty() const { return JumpTables.empty(); }
const std::vector<MachineJumpTableEntry> &getJumpTables() const { const std::vector<MachineJumpTableEntry> &getJumpTables() const {
 End of changes. 3 change blocks. 
3 lines changed or deleted 3 lines changed or added


 MachineLoopInfo.h   MachineLoopInfo.h 
skipping to change at line 38 skipping to change at line 38
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_CODEGEN_MACHINE_LOOP_INFO_H #ifndef LLVM_CODEGEN_MACHINE_LOOP_INFO_H
#define LLVM_CODEGEN_MACHINE_LOOP_INFO_H #define LLVM_CODEGEN_MACHINE_LOOP_INFO_H
#include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/Analysis/LoopInfo.h" #include "llvm/Analysis/LoopInfo.h"
namespace llvm { namespace llvm {
// Implementation in LoopInfoImpl.h
#ifdef __GNUC__
class MachineLoop;
__extension__ extern template class LoopBase<MachineBasicBlock, MachineLoop
>;
#endif
class MachineLoop : public LoopBase<MachineBasicBlock, MachineLoop> { class MachineLoop : public LoopBase<MachineBasicBlock, MachineLoop> {
public: public:
MachineLoop(); MachineLoop();
/// getTopBlock - Return the "top" block in the loop, which is the first /// getTopBlock - Return the "top" block in the loop, which is the first
/// block in the linear layout, ignoring any parts of the loop not /// block in the linear layout, ignoring any parts of the loop not
/// contiguous with the part the contains the header. /// contiguous with the part the contains the header.
MachineBasicBlock *getTopBlock(); MachineBasicBlock *getTopBlock();
/// getBottomBlock - Return the "bottom" block in the loop, which is the last /// getBottomBlock - Return the "bottom" block in the loop, which is the last
skipping to change at line 60 skipping to change at line 66
MachineBasicBlock *getBottomBlock(); MachineBasicBlock *getBottomBlock();
void dump() const; void dump() const;
private: private:
friend class LoopInfoBase<MachineBasicBlock, MachineLoop>; friend class LoopInfoBase<MachineBasicBlock, MachineLoop>;
explicit MachineLoop(MachineBasicBlock *MBB) explicit MachineLoop(MachineBasicBlock *MBB)
: LoopBase<MachineBasicBlock, MachineLoop>(MBB) {} : LoopBase<MachineBasicBlock, MachineLoop>(MBB) {}
}; };
// Implementation in LoopInfoImpl.h
#ifdef __GNUC__
__extension__ extern template
class LoopInfoBase<MachineBasicBlock, MachineLoop>;
#endif
class MachineLoopInfo : public MachineFunctionPass { class MachineLoopInfo : public MachineFunctionPass {
LoopInfoBase<MachineBasicBlock, MachineLoop> LI; LoopInfoBase<MachineBasicBlock, MachineLoop> LI;
friend class LoopBase<MachineBasicBlock, MachineLoop>; friend class LoopBase<MachineBasicBlock, MachineLoop>;
void operator=(const MachineLoopInfo &); // do not implement void operator=(const MachineLoopInfo &) LLVM_DELETED_FUNCTION;
MachineLoopInfo(const MachineLoopInfo &); // do not implement MachineLoopInfo(const MachineLoopInfo &) LLVM_DELETED_FUNCTION;
public: public:
static char ID; // Pass identification, replacement for typeid static char ID; // Pass identification, replacement for typeid
MachineLoopInfo() : MachineFunctionPass(ID) { MachineLoopInfo() : MachineFunctionPass(ID) {
initializeMachineLoopInfoPass(*PassRegistry::getPassRegistry()); initializeMachineLoopInfoPass(*PassRegistry::getPassRegistry());
} }
LoopInfoBase<MachineBasicBlock, MachineLoop>& getBase() { return LI; } LoopInfoBase<MachineBasicBlock, MachineLoop>& getBase() { return LI; }
 End of changes. 3 change blocks. 
2 lines changed or deleted 15 lines changed or added


 MachineMemOperand.h   MachineMemOperand.h 
skipping to change at line 153 skipping to change at line 153
/// getRanges - Return the range tag for the memory reference. /// getRanges - Return the range tag for the memory reference.
const MDNode *getRanges() const { return Ranges; } const MDNode *getRanges() const { return Ranges; }
bool isLoad() const { return Flags & MOLoad; } bool isLoad() const { return Flags & MOLoad; }
bool isStore() const { return Flags & MOStore; } bool isStore() const { return Flags & MOStore; }
bool isVolatile() const { return Flags & MOVolatile; } bool isVolatile() const { return Flags & MOVolatile; }
bool isNonTemporal() const { return Flags & MONonTemporal; } bool isNonTemporal() const { return Flags & MONonTemporal; }
bool isInvariant() const { return Flags & MOInvariant; } bool isInvariant() const { return Flags & MOInvariant; }
/// isUnordered - Returns true if this memory operation doesn't have any
/// ordering constraints other than normal aliasing. Volatile and atomic
/// memory operations can't be reordered.
///
/// Currently, we don't model the difference between volatile and atomic
/// operations. They should retain their ordering relative to all memory
/// operations.
bool isUnordered() const { return !isVolatile(); }
/// refineAlignment - Update this MachineMemOperand to reflect the alignm ent /// refineAlignment - Update this MachineMemOperand to reflect the alignm ent
/// of MMO, if it has a greater alignment. This must only be used when th e /// of MMO, if it has a greater alignment. This must only be used when th e
/// new alignment applies to all users of this MachineMemOperand. /// new alignment applies to all users of this MachineMemOperand.
void refineAlignment(const MachineMemOperand *MMO); void refineAlignment(const MachineMemOperand *MMO);
/// setValue - Change the SourceValue for this MachineMemOperand. This /// setValue - Change the SourceValue for this MachineMemOperand. This
/// should only be used when an object is being relocated and all referen ces /// should only be used when an object is being relocated and all referen ces
/// to it are being updated. /// to it are being updated.
void setValue(const Value *NewSV) { PtrInfo.V = NewSV; } void setValue(const Value *NewSV) { PtrInfo.V = NewSV; }
void setOffset(int64_t NewOffset) { PtrInfo.Offset = NewOffset; } void setOffset(int64_t NewOffset) { PtrInfo.Offset = NewOffset; }
 End of changes. 1 change blocks. 
0 lines changed or deleted 9 lines changed or added


 MachineModuleInfoImpls.h   MachineModuleInfoImpls.h 
skipping to change at line 41 skipping to change at line 41
/// "Lfoo$non_lazy_ptr", the value is something like "_foo". The extra bit /// "Lfoo$non_lazy_ptr", the value is something like "_foo". The extra bit
/// is true if this GV is external. /// is true if this GV is external.
DenseMap<MCSymbol*, StubValueTy> GVStubs; DenseMap<MCSymbol*, StubValueTy> GVStubs;
/// HiddenGVStubs - Darwin '$non_lazy_ptr' stubs. The key is something like /// HiddenGVStubs - Darwin '$non_lazy_ptr' stubs. The key is something like
/// "Lfoo$non_lazy_ptr", the value is something like "_foo". Unlike GV Stubs /// "Lfoo$non_lazy_ptr", the value is something like "_foo". Unlike GV Stubs
/// these are for things with hidden visibility. The extra bit is true if /// these are for things with hidden visibility. The extra bit is true if
/// this GV is external. /// this GV is external.
DenseMap<MCSymbol*, StubValueTy> HiddenGVStubs; DenseMap<MCSymbol*, StubValueTy> HiddenGVStubs;
virtual void Anchor(); // Out of line virtual method. virtual void anchor(); // Out of line virtual method.
public: public:
MachineModuleInfoMachO(const MachineModuleInfo &) {} MachineModuleInfoMachO(const MachineModuleInfo &) {}
StubValueTy &getFnStubEntry(MCSymbol *Sym) { StubValueTy &getFnStubEntry(MCSymbol *Sym) {
assert(Sym && "Key cannot be null"); assert(Sym && "Key cannot be null");
return FnStubs[Sym]; return FnStubs[Sym];
} }
StubValueTy &getGVStubEntry(MCSymbol *Sym) { StubValueTy &getGVStubEntry(MCSymbol *Sym) {
assert(Sym && "Key cannot be null"); assert(Sym && "Key cannot be null");
skipping to change at line 79 skipping to change at line 79
} }
}; };
/// MachineModuleInfoELF - This is a MachineModuleInfoImpl implementation /// MachineModuleInfoELF - This is a MachineModuleInfoImpl implementation
/// for ELF targets. /// for ELF targets.
class MachineModuleInfoELF : public MachineModuleInfoImpl { class MachineModuleInfoELF : public MachineModuleInfoImpl {
/// GVStubs - These stubs are used to materialize global addresses in P IC /// GVStubs - These stubs are used to materialize global addresses in P IC
/// mode. /// mode.
DenseMap<MCSymbol*, StubValueTy> GVStubs; DenseMap<MCSymbol*, StubValueTy> GVStubs;
virtual void Anchor(); // Out of line virtual method. virtual void anchor(); // Out of line virtual method.
public: public:
MachineModuleInfoELF(const MachineModuleInfo &) {} MachineModuleInfoELF(const MachineModuleInfo &) {}
StubValueTy &getGVStubEntry(MCSymbol *Sym) { StubValueTy &getGVStubEntry(MCSymbol *Sym) {
assert(Sym && "Key cannot be null"); assert(Sym && "Key cannot be null");
return GVStubs[Sym]; return GVStubs[Sym];
} }
/// Accessor methods to return the set of stubs in sorted order. /// Accessor methods to return the set of stubs in sorted order.
 End of changes. 2 change blocks. 
2 lines changed or deleted 2 lines changed or added


 MachineOperand.h   MachineOperand.h 
skipping to change at line 32 skipping to change at line 32
class BlockAddress; class BlockAddress;
class ConstantFP; class ConstantFP;
class ConstantInt; class ConstantInt;
class GlobalValue; class GlobalValue;
class MachineBasicBlock; class MachineBasicBlock;
class MachineInstr; class MachineInstr;
class MachineRegisterInfo; class MachineRegisterInfo;
class MDNode; class MDNode;
class TargetMachine; class TargetMachine;
class TargetRegisterInfo; class TargetRegisterInfo;
class hash_code;
class raw_ostream; class raw_ostream;
class MCSymbol; class MCSymbol;
/// MachineOperand class - Representation of each machine instruction opera nd. /// MachineOperand class - Representation of each machine instruction opera nd.
/// ///
class MachineOperand { class MachineOperand {
public: public:
enum MachineOperandType { enum MachineOperandType {
MO_Register, ///< Register operand. MO_Register, ///< Register operand.
MO_Immediate, ///< Immediate operand MO_Immediate, ///< Immediate operand
MO_CImmediate, ///< Immediate >64bit operand MO_CImmediate, ///< Immediate >64bit operand
MO_FPImmediate, ///< Floating-point immediate operand MO_FPImmediate, ///< Floating-point immediate operand
MO_MachineBasicBlock, ///< MachineBasicBlock reference MO_MachineBasicBlock, ///< MachineBasicBlock reference
MO_FrameIndex, ///< Abstract Stack Frame Index MO_FrameIndex, ///< Abstract Stack Frame Index
MO_ConstantPoolIndex, ///< Address of indexed Constant in Constant Pool MO_ConstantPoolIndex, ///< Address of indexed Constant in Constant Pool
MO_TargetIndex, ///< Target-dependent index+offset operand.
MO_JumpTableIndex, ///< Address of indexed Jump Table for switc h MO_JumpTableIndex, ///< Address of indexed Jump Table for switc h
MO_ExternalSymbol, ///< Name of external global symbol MO_ExternalSymbol, ///< Name of external global symbol
MO_GlobalAddress, ///< Address of a global value MO_GlobalAddress, ///< Address of a global value
MO_BlockAddress, ///< Address of a basic block MO_BlockAddress, ///< Address of a basic block
MO_RegisterMask, ///< Mask of preserved registers. MO_RegisterMask, ///< Mask of preserved registers.
MO_Metadata, ///< Metadata reference (for debug info) MO_Metadata, ///< Metadata reference (for debug info)
MO_MCSymbol ///< MCSymbol reference (for debug/eh info) MO_MCSymbol ///< MCSymbol reference (for debug/eh info)
}; };
private: private:
/// OpKind - Specify what kind of operand this is. This discriminates th e /// OpKind - Specify what kind of operand this is. This discriminates th e
/// union. /// union.
unsigned char OpKind; // MachineOperandType unsigned char OpKind; // MachineOperandType
/// SubReg - Subregister number, only valid for MO_Register. A value of // This union is discriminated by OpKind.
0 union {
/// indicates the MO_Register has no subReg. /// SubReg - Subregister number, only valid for MO_Register. A value o
unsigned char SubReg; f 0
/// indicates the MO_Register has no subReg.
unsigned char SubReg;
/// TargetFlags - This is a set of target-specific operand flags.
unsigned char TargetFlags;
};
/// TargetFlags - This is a set of target-specific operand flags. /// TiedTo - Non-zero when this register operand is tied to another regis
unsigned char TargetFlags; ter
/// operand. The encoding of this field is described in the block comment
/// before MachineInstr::tieOperands().
unsigned char TiedTo : 4;
/// IsDef/IsImp/IsKill/IsDead flags - These are only valid for MO_Registe r /// IsDef/IsImp/IsKill/IsDead flags - These are only valid for MO_Registe r
/// operands. /// operands.
/// IsDef - True if this is a def, false if this is a use of the register . /// IsDef - True if this is a def, false if this is a use of the register .
/// ///
bool IsDef : 1; bool IsDef : 1;
/// IsImp - True if this is an implicit def or use, false if it is explic it. /// IsImp - True if this is an implicit def or use, false if it is explic it.
/// ///
skipping to change at line 151 skipping to change at line 161
MachineBasicBlock *MBB; // For MO_MachineBasicBlock. MachineBasicBlock *MBB; // For MO_MachineBasicBlock.
const ConstantFP *CFP; // For MO_FPImmediate. const ConstantFP *CFP; // For MO_FPImmediate.
const ConstantInt *CI; // For MO_CImmediate. Integers > 64bit. const ConstantInt *CI; // For MO_CImmediate. Integers > 64bit.
int64_t ImmVal; // For MO_Immediate. int64_t ImmVal; // For MO_Immediate.
const uint32_t *RegMask; // For MO_RegisterMask. const uint32_t *RegMask; // For MO_RegisterMask.
const MDNode *MD; // For MO_Metadata. const MDNode *MD; // For MO_Metadata.
MCSymbol *Sym; // For MO_MCSymbol MCSymbol *Sym; // For MO_MCSymbol
struct { // For MO_Register. struct { // For MO_Register.
// Register number is in SmallContents.RegNo. // Register number is in SmallContents.RegNo.
MachineOperand **Prev; // Access list for register. MachineOperand *Prev; // Access list for register. See MRI.
MachineOperand *Next; MachineOperand *Next;
} Reg; } Reg;
/// OffsetedInfo - This struct contains the offset and an object identi fier. /// OffsetedInfo - This struct contains the offset and an object identi fier.
/// this represent the object as with an optional offset from it. /// this represent the object as with an optional offset from it.
struct { struct {
union { union {
int Index; // For MO_*Index - The index itself. int Index; // For MO_*Index - The index itself.
const char *SymbolName; // For MO_ExternalSymbol. const char *SymbolName; // For MO_ExternalSymbol.
const GlobalValue *GV; // For MO_GlobalAddress. const GlobalValue *GV; // For MO_GlobalAddress.
skipping to change at line 177 skipping to change at line 187
} Contents; } Contents;
explicit MachineOperand(MachineOperandType K) : OpKind(K), ParentMI(0) { explicit MachineOperand(MachineOperandType K) : OpKind(K), ParentMI(0) {
TargetFlags = 0; TargetFlags = 0;
} }
public: public:
/// getType - Returns the MachineOperandType for this operand. /// getType - Returns the MachineOperandType for this operand.
/// ///
MachineOperandType getType() const { return (MachineOperandType)OpKind; } MachineOperandType getType() const { return (MachineOperandType)OpKind; }
unsigned char getTargetFlags() const { return TargetFlags; } unsigned char getTargetFlags() const {
void setTargetFlags(unsigned char F) { TargetFlags = F; } return isReg() ? 0 : TargetFlags;
void addTargetFlag(unsigned char F) { TargetFlags |= F; } }
void setTargetFlags(unsigned char F) {
assert(!isReg() && "Register operands can't have target flags");
TargetFlags = F;
}
void addTargetFlag(unsigned char F) {
assert(!isReg() && "Register operands can't have target flags");
TargetFlags |= F;
}
/// getParent - Return the instruction that this operand belongs to. /// getParent - Return the instruction that this operand belongs to.
/// ///
MachineInstr *getParent() { return ParentMI; } MachineInstr *getParent() { return ParentMI; }
const MachineInstr *getParent() const { return ParentMI; } const MachineInstr *getParent() const { return ParentMI; }
/// clearParent - Reset the parent pointer. /// clearParent - Reset the parent pointer.
/// ///
/// The MachineOperand copy constructor also copies ParentMI, expecting t he /// The MachineOperand copy constructor also copies ParentMI, expecting t he
/// original to be deleted. If a MachineOperand is ever stored outside a /// original to be deleted. If a MachineOperand is ever stored outside a
skipping to change at line 216 skipping to change at line 234
/// isCImm - Test if t his is a MO_CImmediate operand. /// isCImm - Test if t his is a MO_CImmediate operand.
bool isCImm() const { return OpKind == MO_CImmediate; } bool isCImm() const { return OpKind == MO_CImmediate; }
/// isFPImm - Tests if this is a MO_FPImmediate operand. /// isFPImm - Tests if this is a MO_FPImmediate operand.
bool isFPImm() const { return OpKind == MO_FPImmediate; } bool isFPImm() const { return OpKind == MO_FPImmediate; }
/// isMBB - Tests if this is a MO_MachineBasicBlock operand. /// isMBB - Tests if this is a MO_MachineBasicBlock operand.
bool isMBB() const { return OpKind == MO_MachineBasicBlock; } bool isMBB() const { return OpKind == MO_MachineBasicBlock; }
/// isFI - Tests if this is a MO_FrameIndex operand. /// isFI - Tests if this is a MO_FrameIndex operand.
bool isFI() const { return OpKind == MO_FrameIndex; } bool isFI() const { return OpKind == MO_FrameIndex; }
/// isCPI - Tests if this is a MO_ConstantPoolIndex operand. /// isCPI - Tests if this is a MO_ConstantPoolIndex operand.
bool isCPI() const { return OpKind == MO_ConstantPoolIndex; } bool isCPI() const { return OpKind == MO_ConstantPoolIndex; }
/// isTargetIndex - Tests if this is a MO_TargetIndex operand.
bool isTargetIndex() const { return OpKind == MO_TargetIndex; }
/// isJTI - Tests if this is a MO_JumpTableIndex operand. /// isJTI - Tests if this is a MO_JumpTableIndex operand.
bool isJTI() const { return OpKind == MO_JumpTableIndex; } bool isJTI() const { return OpKind == MO_JumpTableIndex; }
/// isGlobal - Tests if this is a MO_GlobalAddress operand. /// isGlobal - Tests if this is a MO_GlobalAddress operand.
bool isGlobal() const { return OpKind == MO_GlobalAddress; } bool isGlobal() const { return OpKind == MO_GlobalAddress; }
/// isSymbol - Tests if this is a MO_ExternalSymbol operand. /// isSymbol - Tests if this is a MO_ExternalSymbol operand.
bool isSymbol() const { return OpKind == MO_ExternalSymbol; } bool isSymbol() const { return OpKind == MO_ExternalSymbol; }
/// isBlockAddress - Tests if this is a MO_BlockAddress operand. /// isBlockAddress - Tests if this is a MO_BlockAddress operand.
bool isBlockAddress() const { return OpKind == MO_BlockAddress; } bool isBlockAddress() const { return OpKind == MO_BlockAddress; }
/// isRegMask - Tests if this is a MO_RegisterMask operand. /// isRegMask - Tests if this is a MO_RegisterMask operand.
bool isRegMask() const { return OpKind == MO_RegisterMask; } bool isRegMask() const { return OpKind == MO_RegisterMask; }
skipping to change at line 285 skipping to change at line 305
bool isInternalRead() const { bool isInternalRead() const {
assert(isReg() && "Wrong MachineOperand accessor"); assert(isReg() && "Wrong MachineOperand accessor");
return IsInternalRead; return IsInternalRead;
} }
bool isEarlyClobber() const { bool isEarlyClobber() const {
assert(isReg() && "Wrong MachineOperand accessor"); assert(isReg() && "Wrong MachineOperand accessor");
return IsEarlyClobber; return IsEarlyClobber;
} }
bool isTied() const {
assert(isReg() && "Wrong MachineOperand accessor");
return TiedTo;
}
bool isDebug() const { bool isDebug() const {
assert(isReg() && "Wrong MachineOperand accessor"); assert(isReg() && "Wrong MachineOperand accessor");
return IsDebug; return IsDebug;
} }
/// readsReg - Returns true if this operand reads the previous value of i ts /// readsReg - Returns true if this operand reads the previous value of i ts
/// register. A use operand with the <undef> flag set doesn't read its /// register. A use operand with the <undef> flag set doesn't read its
/// register. A sub-register def implicitly reads the other parts of the /// register. A sub-register def implicitly reads the other parts of the
/// register being redefined unless the <undef> flag is set. /// register being redefined unless the <undef> flag is set.
/// ///
/// This refers to reading the register value from before the current /// This refers to reading the register value from before the current
/// instruction or bundle. Internal bundle reads are not included. /// instruction or bundle. Internal bundle reads are not included.
bool readsReg() const { bool readsReg() const {
assert(isReg() && "Wrong MachineOperand accessor"); assert(isReg() && "Wrong MachineOperand accessor");
return !isUndef() && !isInternalRead() && (isUse() || getSubReg()); return !isUndef() && !isInternalRead() && (isUse() || getSubReg());
} }
/// getNextOperandForReg - Return the next MachineOperand in the function
that
/// uses or defines this register.
MachineOperand *getNextOperandForReg() const {
assert(isReg() && "This is not a register operand!");
return Contents.Reg.Next;
}
//===-------------------------------------------------------------------- ===// //===-------------------------------------------------------------------- ===//
// Mutators for Register Operands // Mutators for Register Operands
//===-------------------------------------------------------------------- ===// //===-------------------------------------------------------------------- ===//
/// Change the register this operand corresponds to. /// Change the register this operand corresponds to.
/// ///
void setReg(unsigned Reg); void setReg(unsigned Reg);
void setSubReg(unsigned subReg) { void setSubReg(unsigned subReg) {
assert(isReg() && "Wrong MachineOperand accessor"); assert(isReg() && "Wrong MachineOperand accessor");
skipping to change at line 335 skipping to change at line 353
/// Reg must be a virtual register, SubIdx can be 0. /// Reg must be a virtual register, SubIdx can be 0.
/// ///
void substVirtReg(unsigned Reg, unsigned SubIdx, const TargetRegisterInfo &); void substVirtReg(unsigned Reg, unsigned SubIdx, const TargetRegisterInfo &);
/// substPhysReg - Substitute the current register with the physical regi ster /// substPhysReg - Substitute the current register with the physical regi ster
/// Reg, taking any existing SubReg into account. For instance, /// Reg, taking any existing SubReg into account. For instance,
/// substPhysReg(%EAX) will change %reg1024:sub_8bit to %AL. /// substPhysReg(%EAX) will change %reg1024:sub_8bit to %AL.
/// ///
void substPhysReg(unsigned Reg, const TargetRegisterInfo&); void substPhysReg(unsigned Reg, const TargetRegisterInfo&);
void setIsUse(bool Val = true) { void setIsUse(bool Val = true) { setIsDef(!Val); }
assert(isReg() && "Wrong MachineOperand accessor");
assert((Val || !isDebug()) && "Marking a debug operation as def");
IsDef = !Val;
}
void setIsDef(bool Val = true) { void setIsDef(bool Val = true);
assert(isReg() && "Wrong MachineOperand accessor");
assert((!Val || !isDebug()) && "Marking a debug operation as def");
IsDef = Val;
}
void setImplicit(bool Val = true) { void setImplicit(bool Val = true) {
assert(isReg() && "Wrong MachineOperand accessor"); assert(isReg() && "Wrong MachineOperand accessor");
IsImp = Val; IsImp = Val;
} }
void setIsKill(bool Val = true) { void setIsKill(bool Val = true) {
assert(isReg() && !IsDef && "Wrong MachineOperand accessor"); assert(isReg() && !IsDef && "Wrong MachineOperand accessor");
assert((!Val || !isDebug()) && "Marking a debug operation as kill"); assert((!Val || !isDebug()) && "Marking a debug operation as kill");
IsKill = Val; IsKill = Val;
skipping to change at line 408 skipping to change at line 418
assert(isFPImm() && "Wrong MachineOperand accessor"); assert(isFPImm() && "Wrong MachineOperand accessor");
return Contents.CFP; return Contents.CFP;
} }
MachineBasicBlock *getMBB() const { MachineBasicBlock *getMBB() const {
assert(isMBB() && "Wrong MachineOperand accessor"); assert(isMBB() && "Wrong MachineOperand accessor");
return Contents.MBB; return Contents.MBB;
} }
int getIndex() const { int getIndex() const {
assert((isFI() || isCPI() || isJTI()) && assert((isFI() || isCPI() || isTargetIndex() || isJTI()) &&
"Wrong MachineOperand accessor"); "Wrong MachineOperand accessor");
return Contents.OffsetedInfo.Val.Index; return Contents.OffsetedInfo.Val.Index;
} }
const GlobalValue *getGlobal() const { const GlobalValue *getGlobal() const {
assert(isGlobal() && "Wrong MachineOperand accessor"); assert(isGlobal() && "Wrong MachineOperand accessor");
return Contents.OffsetedInfo.Val.GV; return Contents.OffsetedInfo.Val.GV;
} }
const BlockAddress *getBlockAddress() const { const BlockAddress *getBlockAddress() const {
skipping to change at line 431 skipping to change at line 441
} }
MCSymbol *getMCSymbol() const { MCSymbol *getMCSymbol() const {
assert(isMCSymbol() && "Wrong MachineOperand accessor"); assert(isMCSymbol() && "Wrong MachineOperand accessor");
return Contents.Sym; return Contents.Sym;
} }
/// getOffset - Return the offset from the symbol in this operand. This a lways /// getOffset - Return the offset from the symbol in this operand. This a lways
/// returns 0 for ExternalSymbol operands. /// returns 0 for ExternalSymbol operands.
int64_t getOffset() const { int64_t getOffset() const {
assert((isGlobal() || isSymbol() || isCPI() || isBlockAddress()) && assert((isGlobal() || isSymbol() || isCPI() || isTargetIndex() ||
"Wrong MachineOperand accessor"); isBlockAddress()) && "Wrong MachineOperand accessor");
return (int64_t(Contents.OffsetedInfo.OffsetHi) << 32) | return int64_t(uint64_t(Contents.OffsetedInfo.OffsetHi) << 32) |
SmallContents.OffsetLo; SmallContents.OffsetLo;
} }
const char *getSymbolName() const { const char *getSymbolName() const {
assert(isSymbol() && "Wrong MachineOperand accessor"); assert(isSymbol() && "Wrong MachineOperand accessor");
return Contents.OffsetedInfo.Val.SymbolName; return Contents.OffsetedInfo.Val.SymbolName;
} }
/// clobbersPhysReg - Returns true if this RegMask clobbers PhysReg. /// clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
/// It is sometimes necessary to detach the register mask pointer from it s /// It is sometimes necessary to detach the register mask pointer from it s
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//===-------------------------------------------------------------------- ===// //===-------------------------------------------------------------------- ===//
// Mutators for various operand types. // Mutators for various operand types.
//===-------------------------------------------------------------------- ===// //===-------------------------------------------------------------------- ===//
void setImm(int64_t immVal) { void setImm(int64_t immVal) {
assert(isImm() && "Wrong MachineOperand mutator"); assert(isImm() && "Wrong MachineOperand mutator");
Contents.ImmVal = immVal; Contents.ImmVal = immVal;
} }
void setOffset(int64_t Offset) { void setOffset(int64_t Offset) {
assert((isGlobal() || isSymbol() || isCPI() || isBlockAddress()) && assert((isGlobal() || isSymbol() || isCPI() || isTargetIndex() ||
"Wrong MachineOperand accessor"); isBlockAddress()) && "Wrong MachineOperand accessor");
SmallContents.OffsetLo = unsigned(Offset); SmallContents.OffsetLo = unsigned(Offset);
Contents.OffsetedInfo.OffsetHi = int(Offset >> 32); Contents.OffsetedInfo.OffsetHi = int(Offset >> 32);
} }
void setIndex(int Idx) { void setIndex(int Idx) {
assert((isFI() || isCPI() || isJTI()) && assert((isFI() || isCPI() || isTargetIndex() || isJTI()) &&
"Wrong MachineOperand accessor"); "Wrong MachineOperand accessor");
Contents.OffsetedInfo.Val.Index = Idx; Contents.OffsetedInfo.Val.Index = Idx;
} }
void setMBB(MachineBasicBlock *MBB) { void setMBB(MachineBasicBlock *MBB) {
assert(isMBB() && "Wrong MachineOperand accessor"); assert(isMBB() && "Wrong MachineOperand accessor");
Contents.MBB = MBB; Contents.MBB = MBB;
} }
//===-------------------------------------------------------------------- ===// //===-------------------------------------------------------------------- ===//
// Other methods. // Other methods.
//===-------------------------------------------------------------------- ===// //===-------------------------------------------------------------------- ===//
/// isIdenticalTo - Return true if this operand is identical to the speci fied /// isIdenticalTo - Return true if this operand is identical to the speci fied
/// operand. Note: This method ignores isKill and isDead properties. /// operand. Note: This method ignores isKill and isDead properties.
bool isIdenticalTo(const MachineOperand &Other) const; bool isIdenticalTo(const MachineOperand &Other) const;
/// \brief MachineOperand hash_value overload.
///
/// Note that this includes the same information in the hash that
/// isIdenticalTo uses for comparison. It is thus suited for use in hash
/// tables which use that function for equality comparisons only.
friend hash_code hash_value(const MachineOperand &MO);
/// ChangeToImmediate - Replace this operand with a new immediate operand of /// ChangeToImmediate - Replace this operand with a new immediate operand of
/// the specified value. If an operand is known to be an immediate alrea dy, /// the specified value. If an operand is known to be an immediate alrea dy,
/// the setImm method should be used. /// the setImm method should be used.
void ChangeToImmediate(int64_t ImmVal); void ChangeToImmediate(int64_t ImmVal);
/// ChangeToRegister - Replace this operand with a new register operand o f /// ChangeToRegister - Replace this operand with a new register operand o f
/// the specified value. If an operand is known to be an register alread y, /// the specified value. If an operand is known to be an register alread y,
/// the setReg method should be used. /// the setReg method should be used.
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp = false, void ChangeToRegister(unsigned Reg, bool isDef, bool isImp = false,
bool isKill = false, bool isDead = false, bool isKill = false, bool isDead = false,
skipping to change at line 543 skipping to change at line 560
MachineOperand Op(MachineOperand::MO_FPImmediate); MachineOperand Op(MachineOperand::MO_FPImmediate);
Op.Contents.CFP = CFP; Op.Contents.CFP = CFP;
return Op; return Op;
} }
static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp = fa lse, static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp = fa lse,
bool isKill = false, bool isDead = false, bool isKill = false, bool isDead = false,
bool isUndef = false, bool isUndef = false,
bool isEarlyClobber = false, bool isEarlyClobber = false,
unsigned SubReg = 0, unsigned SubReg = 0,
bool isDebug = false) { bool isDebug = false,
bool isInternalRead = false) {
MachineOperand Op(MachineOperand::MO_Register); MachineOperand Op(MachineOperand::MO_Register);
Op.IsDef = isDef; Op.IsDef = isDef;
Op.IsImp = isImp; Op.IsImp = isImp;
Op.IsKill = isKill; Op.IsKill = isKill;
Op.IsDead = isDead; Op.IsDead = isDead;
Op.IsUndef = isUndef; Op.IsUndef = isUndef;
Op.IsInternalRead = false; Op.IsInternalRead = isInternalRead;
Op.IsEarlyClobber = isEarlyClobber; Op.IsEarlyClobber = isEarlyClobber;
Op.TiedTo = 0;
Op.IsDebug = isDebug; Op.IsDebug = isDebug;
Op.SmallContents.RegNo = Reg; Op.SmallContents.RegNo = Reg;
Op.Contents.Reg.Prev = 0; Op.Contents.Reg.Prev = 0;
Op.Contents.Reg.Next = 0; Op.Contents.Reg.Next = 0;
Op.SubReg = SubReg; Op.SubReg = SubReg;
return Op; return Op;
} }
static MachineOperand CreateMBB(MachineBasicBlock *MBB, static MachineOperand CreateMBB(MachineBasicBlock *MBB,
unsigned char TargetFlags = 0) { unsigned char TargetFlags = 0) {
MachineOperand Op(MachineOperand::MO_MachineBasicBlock); MachineOperand Op(MachineOperand::MO_MachineBasicBlock);
skipping to change at line 579 skipping to change at line 598
return Op; return Op;
} }
static MachineOperand CreateCPI(unsigned Idx, int Offset, static MachineOperand CreateCPI(unsigned Idx, int Offset,
unsigned char TargetFlags = 0) { unsigned char TargetFlags = 0) {
MachineOperand Op(MachineOperand::MO_ConstantPoolIndex); MachineOperand Op(MachineOperand::MO_ConstantPoolIndex);
Op.setIndex(Idx); Op.setIndex(Idx);
Op.setOffset(Offset); Op.setOffset(Offset);
Op.setTargetFlags(TargetFlags); Op.setTargetFlags(TargetFlags);
return Op; return Op;
} }
static MachineOperand CreateTargetIndex(unsigned Idx, int64_t Offset,
unsigned char TargetFlags = 0) {
MachineOperand Op(MachineOperand::MO_TargetIndex);
Op.setIndex(Idx);
Op.setOffset(Offset);
Op.setTargetFlags(TargetFlags);
return Op;
}
static MachineOperand CreateJTI(unsigned Idx, static MachineOperand CreateJTI(unsigned Idx,
unsigned char TargetFlags = 0) { unsigned char TargetFlags = 0) {
MachineOperand Op(MachineOperand::MO_JumpTableIndex); MachineOperand Op(MachineOperand::MO_JumpTableIndex);
Op.setIndex(Idx); Op.setIndex(Idx);
Op.setTargetFlags(TargetFlags); Op.setTargetFlags(TargetFlags);
return Op; return Op;
} }
static MachineOperand CreateGA(const GlobalValue *GV, int64_t Offset, static MachineOperand CreateGA(const GlobalValue *GV, int64_t Offset,
unsigned char TargetFlags = 0) { unsigned char TargetFlags = 0) {
MachineOperand Op(MachineOperand::MO_GlobalAddress); MachineOperand Op(MachineOperand::MO_GlobalAddress);
skipping to change at line 602 skipping to change at line 629
return Op; return Op;
} }
static MachineOperand CreateES(const char *SymName, static MachineOperand CreateES(const char *SymName,
unsigned char TargetFlags = 0) { unsigned char TargetFlags = 0) {
MachineOperand Op(MachineOperand::MO_ExternalSymbol); MachineOperand Op(MachineOperand::MO_ExternalSymbol);
Op.Contents.OffsetedInfo.Val.SymbolName = SymName; Op.Contents.OffsetedInfo.Val.SymbolName = SymName;
Op.setOffset(0); // Offset is always 0. Op.setOffset(0); // Offset is always 0.
Op.setTargetFlags(TargetFlags); Op.setTargetFlags(TargetFlags);
return Op; return Op;
} }
static MachineOperand CreateBA(const BlockAddress *BA, static MachineOperand CreateBA(const BlockAddress *BA, int64_t Offset,
unsigned char TargetFlags = 0) { unsigned char TargetFlags = 0) {
MachineOperand Op(MachineOperand::MO_BlockAddress); MachineOperand Op(MachineOperand::MO_BlockAddress);
Op.Contents.OffsetedInfo.Val.BA = BA; Op.Contents.OffsetedInfo.Val.BA = BA;
Op.setOffset(0); // Offset is always 0. Op.setOffset(Offset);
Op.setTargetFlags(TargetFlags); Op.setTargetFlags(TargetFlags);
return Op; return Op;
} }
/// CreateRegMask - Creates a register mask operand referencing Mask. Th e /// CreateRegMask - Creates a register mask operand referencing Mask. Th e
/// operand does not take ownership of the memory referenced by Mask, it must /// operand does not take ownership of the memory referenced by Mask, it must
/// remain valid for the lifetime of the operand. /// remain valid for the lifetime of the operand.
/// ///
/// A RegMask operand represents a set of non-clobbered physical register s on /// A RegMask operand represents a set of non-clobbered physical register s on
/// an instruction that clobbers many registers, typically a call. The b it /// an instruction that clobbers many registers, typically a call. The b it
/// mask has a bit set for each physreg that is preserved by this /// mask has a bit set for each physreg that is preserved by this
skipping to change at line 654 skipping to change at line 681
// Methods for handling register use/def lists. // Methods for handling register use/def lists.
//===-------------------------------------------------------------------- ===// //===-------------------------------------------------------------------- ===//
/// isOnRegUseList - Return true if this operand is on a register use/def list /// isOnRegUseList - Return true if this operand is on a register use/def list
/// or false if not. This can only be called for register operands that are /// or false if not. This can only be called for register operands that are
/// part of a machine instruction. /// part of a machine instruction.
bool isOnRegUseList() const { bool isOnRegUseList() const {
assert(isReg() && "Can only add reg operand to use lists"); assert(isReg() && "Can only add reg operand to use lists");
return Contents.Reg.Prev != 0; return Contents.Reg.Prev != 0;
} }
/// AddRegOperandToRegInfo - Add this register operand to the specified
/// MachineRegisterInfo. If it is null, then the next/prev fields should
be
/// explicitly nulled out.
void AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo);
/// RemoveRegOperandFromRegInfo - Remove this register operand from the
/// MachineRegisterInfo it is linked with.
void RemoveRegOperandFromRegInfo();
}; };
inline raw_ostream &operator<<(raw_ostream &OS, const MachineOperand& MO) { inline raw_ostream &operator<<(raw_ostream &OS, const MachineOperand& MO) {
MO.print(OS, 0); MO.print(OS, 0);
return OS; return OS;
} }
// See friend declaration above. This additional declaration is required
in
// order to compile LLVM with IBM xlC compiler.
hash_code hash_value(const MachineOperand &MO);
} // End llvm namespace } // End llvm namespace
#endif #endif
 End of changes. 24 change blocks. 
49 lines changed or deleted 70 lines changed or added


 MachinePassRegistry.h   MachinePassRegistry.h 
skipping to change at line 99 skipping to change at line 99
public: public:
// NO CONSTRUCTOR - we don't want static constructor ordering to mess // NO CONSTRUCTOR - we don't want static constructor ordering to mess
// with the registry. // with the registry.
// Accessors. // Accessors.
// //
MachinePassRegistryNode *getList() { return List; } MachinePassRegistryNode *getList() { return List; }
MachinePassCtor getDefault() { return Default; } MachinePassCtor getDefault() { return Default; }
void setDefault(MachinePassCtor C) { Default = C; } void setDefault(MachinePassCtor C) { Default = C; }
void setDefault(StringRef Name);
void setListener(MachinePassRegistryListener *L) { Listener = L; } void setListener(MachinePassRegistryListener *L) { Listener = L; }
/// Add - Adds a function pass to the registration list. /// Add - Adds a function pass to the registration list.
/// ///
void Add(MachinePassRegistryNode *Node); void Add(MachinePassRegistryNode *Node);
/// Remove - Removes a function pass from the registration list. /// Remove - Removes a function pass from the registration list.
/// ///
void Remove(MachinePassRegistryNode *Node); void Remove(MachinePassRegistryNode *Node);
 End of changes. 1 change blocks. 
0 lines changed or deleted 1 lines changed or added


 MachineRegisterInfo.h   MachineRegisterInfo.h 
skipping to change at line 60 skipping to change at line 60
/// for the value 0 which means the second value of the pair is the prefe rred /// for the value 0 which means the second value of the pair is the prefe rred
/// register for allocation. For example, if the hint is <0, 1024>, it me ans /// register for allocation. For example, if the hint is <0, 1024>, it me ans
/// the allocator should prefer the physical register allocated to the vi rtual /// the allocator should prefer the physical register allocated to the vi rtual
/// register of the hint. /// register of the hint.
IndexedMap<std::pair<unsigned, unsigned>, VirtReg2IndexFunctor> RegAllocH ints; IndexedMap<std::pair<unsigned, unsigned>, VirtReg2IndexFunctor> RegAllocH ints;
/// PhysRegUseDefLists - This is an array of the head of the use/def list for /// PhysRegUseDefLists - This is an array of the head of the use/def list for
/// physical registers. /// physical registers.
MachineOperand **PhysRegUseDefLists; MachineOperand **PhysRegUseDefLists;
/// UsedPhysRegs - This is a bit vector that is computed and set by the /// getRegUseDefListHead - Return the head pointer for the register use/d
ef
/// list for the specified virtual or physical register.
MachineOperand *&getRegUseDefListHead(unsigned RegNo) {
if (TargetRegisterInfo::isVirtualRegister(RegNo))
return VRegInfo[RegNo].second;
return PhysRegUseDefLists[RegNo];
}
MachineOperand *getRegUseDefListHead(unsigned RegNo) const {
if (TargetRegisterInfo::isVirtualRegister(RegNo))
return VRegInfo[RegNo].second;
return PhysRegUseDefLists[RegNo];
}
/// Get the next element in the use-def chain.
static MachineOperand *getNextOperandForReg(const MachineOperand *MO) {
assert(MO && MO->isReg() && "This is not a register operand!");
return MO->Contents.Reg.Next;
}
/// UsedRegUnits - This is a bit vector that is computed and set by the
/// register allocator, and must be kept up to date by passes that run af ter /// register allocator, and must be kept up to date by passes that run af ter
/// register allocation (though most don't modify this). This is used /// register allocation (though most don't modify this). This is used
/// so that the code generator knows which callee save registers to save and /// so that the code generator knows which callee save registers to save and
/// for other target specific uses. /// for other target specific uses.
/// This vector only has bits set for registers explicitly used, not thei /// This vector has bits set for register units that are modified in the
r /// current function. It doesn't include registers clobbered by function
/// aliases. /// calls with register mask operands.
BitVector UsedPhysRegs; BitVector UsedRegUnits;
/// UsedPhysRegMask - Additional used physregs, but including aliases. /// UsedPhysRegMask - Additional used physregs including aliases.
/// This bit vector represents all the registers clobbered by function ca
lls.
/// It can model things that UsedRegUnits can't, such as function calls t
hat
/// clobber ymm7 but preserve the low half in xmm7.
BitVector UsedPhysRegMask; BitVector UsedPhysRegMask;
/// ReservedRegs - This is a bit vector of reserved registers. The targe t /// ReservedRegs - This is a bit vector of reserved registers. The targe t
/// may change its mind about which registers should be reserved. This /// may change its mind about which registers should be reserved. This
/// vector is the frozen set of reserved registers when register allocati on /// vector is the frozen set of reserved registers when register allocati on
/// started. /// started.
BitVector ReservedRegs; BitVector ReservedRegs;
/// AllocatableRegs - From TRI->getAllocatableSet.
mutable BitVector AllocatableRegs;
/// LiveIns/LiveOuts - Keep track of the physical registers that are /// LiveIns/LiveOuts - Keep track of the physical registers that are
/// livein/liveout of the function. Live in values are typically argumen ts in /// livein/liveout of the function. Live in values are typically argumen ts in
/// registers, live out values are typically return values in registers. /// registers, live out values are typically return values in registers.
/// LiveIn values are allowed to have virtual registers associated with t hem, /// LiveIn values are allowed to have virtual registers associated with t hem,
/// stored in the second element. /// stored in the second element.
std::vector<std::pair<unsigned, unsigned> > LiveIns; std::vector<std::pair<unsigned, unsigned> > LiveIns;
std::vector<unsigned> LiveOuts; std::vector<unsigned> LiveOuts;
MachineRegisterInfo(const MachineRegisterInfo&); // DO NOT IMPLEMENT MachineRegisterInfo(const MachineRegisterInfo&) LLVM_DELETED_FUNCTION;
void operator=(const MachineRegisterInfo&); // DO NOT IMPLEMENT void operator=(const MachineRegisterInfo&) LLVM_DELETED_FUNCTION;
public: public:
explicit MachineRegisterInfo(const TargetRegisterInfo &TRI); explicit MachineRegisterInfo(const TargetRegisterInfo &TRI);
~MachineRegisterInfo(); ~MachineRegisterInfo();
//===-------------------------------------------------------------------- ===// //===-------------------------------------------------------------------- ===//
// Function State // Function State
//===-------------------------------------------------------------------- ===// //===-------------------------------------------------------------------- ===//
// isSSA - Returns true when the machine function is in SSA form. Early // isSSA - Returns true when the machine function is in SSA form. Early
// passes require the machine function to be in SSA form where every virt ual // passes require the machine function to be in SSA form where every virt ual
skipping to change at line 132 skipping to change at line 153
/// tracked accurately. /// tracked accurately.
/// ///
/// This should be called by late passes that invalidate the liveness /// This should be called by late passes that invalidate the liveness
/// information. /// information.
void invalidateLiveness() { TracksLiveness = false; } void invalidateLiveness() { TracksLiveness = false; }
//===-------------------------------------------------------------------- ===// //===-------------------------------------------------------------------- ===//
// Register Info // Register Info
//===-------------------------------------------------------------------- ===// //===-------------------------------------------------------------------- ===//
// Strictly for use by MachineInstr.cpp.
void addRegOperandToUseList(MachineOperand *MO);
// Strictly for use by MachineInstr.cpp.
void removeRegOperandFromUseList(MachineOperand *MO);
/// reg_begin/reg_end - Provide iteration support to walk over all defini tions /// reg_begin/reg_end - Provide iteration support to walk over all defini tions
/// and uses of a register within the MachineFunction that corresponds to this /// and uses of a register within the MachineFunction that corresponds to this
/// MachineRegisterInfo object. /// MachineRegisterInfo object.
template<bool Uses, bool Defs, bool SkipDebug> template<bool Uses, bool Defs, bool SkipDebug>
class defusechain_iterator; class defusechain_iterator;
// Make it a friend so it can access getNextOperandForReg().
template<bool, bool, bool> friend class defusechain_iterator;
/// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specif ied /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specif ied
/// register. /// register.
typedef defusechain_iterator<true,true,false> reg_iterator; typedef defusechain_iterator<true,true,false> reg_iterator;
reg_iterator reg_begin(unsigned RegNo) const { reg_iterator reg_begin(unsigned RegNo) const {
return reg_iterator(getRegUseDefListHead(RegNo)); return reg_iterator(getRegUseDefListHead(RegNo));
} }
static reg_iterator reg_end() { return reg_iterator(0); } static reg_iterator reg_end() { return reg_iterator(0); }
/// reg_empty - Return true if there are no instructions using or definin g the /// reg_empty - Return true if there are no instructions using or definin g the
/// specified register (it may be live-in). /// specified register (it may be live-in).
skipping to change at line 175 skipping to change at line 205
typedef defusechain_iterator<false,true,false> def_iterator; typedef defusechain_iterator<false,true,false> def_iterator;
def_iterator def_begin(unsigned RegNo) const { def_iterator def_begin(unsigned RegNo) const {
return def_iterator(getRegUseDefListHead(RegNo)); return def_iterator(getRegUseDefListHead(RegNo));
} }
static def_iterator def_end() { return def_iterator(0); } static def_iterator def_end() { return def_iterator(0); }
/// def_empty - Return true if there are no instructions defining the /// def_empty - Return true if there are no instructions defining the
/// specified register (it may be live-in). /// specified register (it may be live-in).
bool def_empty(unsigned RegNo) const { return def_begin(RegNo) == def_end (); } bool def_empty(unsigned RegNo) const { return def_begin(RegNo) == def_end (); }
/// hasOneDef - Return true if there is exactly one instruction defining
the
/// specified register.
bool hasOneDef(unsigned RegNo) const {
def_iterator DI = def_begin(RegNo);
if (DI == def_end())
return false;
return ++DI == def_end();
}
/// use_iterator/use_begin/use_end - Walk all uses of the specified regis ter. /// use_iterator/use_begin/use_end - Walk all uses of the specified regis ter.
typedef defusechain_iterator<true,false,false> use_iterator; typedef defusechain_iterator<true,false,false> use_iterator;
use_iterator use_begin(unsigned RegNo) const { use_iterator use_begin(unsigned RegNo) const {
return use_iterator(getRegUseDefListHead(RegNo)); return use_iterator(getRegUseDefListHead(RegNo));
} }
static use_iterator use_end() { return use_iterator(0); } static use_iterator use_end() { return use_iterator(0); }
/// use_empty - Return true if there are no instructions using the specif ied /// use_empty - Return true if there are no instructions using the specif ied
/// register. /// register.
bool use_empty(unsigned RegNo) const { return use_begin(RegNo) == use_end (); } bool use_empty(unsigned RegNo) const { return use_begin(RegNo) == use_end (); }
/// hasOneUse - Return true if there is exactly one instruction using the /// hasOneUse - Return true if there is exactly one instruction using the
/// specified register. /// specified register.
bool hasOneUse(unsigned RegNo) const; bool hasOneUse(unsigned RegNo) const {
use_iterator UI = use_begin(RegNo);
if (UI == use_end())
return false;
return ++UI == use_end();
}
/// use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of t he /// use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of t he
/// specified register, skipping those marked as Debug. /// specified register, skipping those marked as Debug.
typedef defusechain_iterator<true,false,true> use_nodbg_iterator; typedef defusechain_iterator<true,false,true> use_nodbg_iterator;
use_nodbg_iterator use_nodbg_begin(unsigned RegNo) const { use_nodbg_iterator use_nodbg_begin(unsigned RegNo) const {
return use_nodbg_iterator(getRegUseDefListHead(RegNo)); return use_nodbg_iterator(getRegUseDefListHead(RegNo));
} }
static use_nodbg_iterator use_nodbg_end() { return use_nodbg_iterator(0); } static use_nodbg_iterator use_nodbg_end() { return use_nodbg_iterator(0); }
/// use_nodbg_empty - Return true if there are no non-Debug instructions /// use_nodbg_empty - Return true if there are no non-Debug instructions
skipping to change at line 221 skipping to change at line 265
/// ///
/// Note that it is usually necessary to first constrain ToReg's register /// Note that it is usually necessary to first constrain ToReg's register
/// class to match the FromReg constraints using: /// class to match the FromReg constraints using:
/// ///
/// constrainRegClass(ToReg, getRegClass(FromReg)) /// constrainRegClass(ToReg, getRegClass(FromReg))
/// ///
/// That function will return NULL if the virtual registers have incompat ible /// That function will return NULL if the virtual registers have incompat ible
/// constraints. /// constraints.
void replaceRegWith(unsigned FromReg, unsigned ToReg); void replaceRegWith(unsigned FromReg, unsigned ToReg);
/// getRegUseDefListHead - Return the head pointer for the register use/d
ef
/// list for the specified virtual or physical register.
MachineOperand *&getRegUseDefListHead(unsigned RegNo) {
if (TargetRegisterInfo::isVirtualRegister(RegNo))
return VRegInfo[RegNo].second;
return PhysRegUseDefLists[RegNo];
}
MachineOperand *getRegUseDefListHead(unsigned RegNo) const {
if (TargetRegisterInfo::isVirtualRegister(RegNo))
return VRegInfo[RegNo].second;
return PhysRegUseDefLists[RegNo];
}
/// getVRegDef - Return the machine instr that defines the specified virt ual /// getVRegDef - Return the machine instr that defines the specified virt ual
/// register or null if none is found. This assumes that the code is in SSA /// register or null if none is found. This assumes that the code is in SSA
/// form, so there should only be one definition. /// form, so there should only be one definition.
MachineInstr *getVRegDef(unsigned Reg) const; MachineInstr *getVRegDef(unsigned Reg) const;
/// getUniqueVRegDef - Return the unique machine instr that defines the
/// specified virtual register or null if none is found. If there are
/// multiple definitions or no definition, return null.
MachineInstr *getUniqueVRegDef(unsigned Reg) const;
/// clearKillFlags - Iterate over all the uses of the given register and /// clearKillFlags - Iterate over all the uses of the given register and
/// clear the kill flag from the MachineOperand. This function is used by /// clear the kill flag from the MachineOperand. This function is used by
/// optimization passes which extend register lifetimes and need only /// optimization passes which extend register lifetimes and need only
/// preserve conservative kill flag information. /// preserve conservative kill flag information.
void clearKillFlags(unsigned Reg) const; void clearKillFlags(unsigned Reg) const;
#ifndef NDEBUG #ifndef NDEBUG
void dumpUses(unsigned RegNo) const; void dumpUses(unsigned RegNo) const;
#endif #endif
skipping to change at line 328 skipping to change at line 363
unsigned getSimpleHint(unsigned Reg) const { unsigned getSimpleHint(unsigned Reg) const {
std::pair<unsigned, unsigned> Hint = getRegAllocationHint(Reg); std::pair<unsigned, unsigned> Hint = getRegAllocationHint(Reg);
return Hint.first ? 0 : Hint.second; return Hint.first ? 0 : Hint.second;
} }
//===-------------------------------------------------------------------- ===// //===-------------------------------------------------------------------- ===//
// Physical Register Use Info // Physical Register Use Info
//===-------------------------------------------------------------------- ===// //===-------------------------------------------------------------------- ===//
/// isPhysRegUsed - Return true if the specified register is used in this /// isPhysRegUsed - Return true if the specified register is used in this
/// function. This only works after register allocation. /// function. Also check for clobbered aliases and registers clobbered by
/// function calls with register mask operands.
///
/// This only works after register allocation. It is primarily used by
/// PrologEpilogInserter to determine which callee-saved registers need
/// spilling.
bool isPhysRegUsed(unsigned Reg) const { bool isPhysRegUsed(unsigned Reg) const {
return UsedPhysRegs.test(Reg) || UsedPhysRegMask.test(Reg);
}
/// isPhysRegOrOverlapUsed - Return true if Reg or any overlapping regist
er
/// is used in this function.
bool isPhysRegOrOverlapUsed(unsigned Reg) const {
if (UsedPhysRegMask.test(Reg)) if (UsedPhysRegMask.test(Reg))
return true; return true;
for (const uint16_t *AI = TRI->getOverlaps(Reg); *AI; ++AI) for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units)
if (UsedPhysRegs.test(*AI)) if (UsedRegUnits.test(*Units))
return true; return true;
return false; return false;
} }
/// setPhysRegUsed - Mark the specified register used in this function. /// setPhysRegUsed - Mark the specified register used in this function.
/// This should only be called during and after register allocation. /// This should only be called during and after register allocation.
void setPhysRegUsed(unsigned Reg) { UsedPhysRegs.set(Reg); } void setPhysRegUsed(unsigned Reg) {
for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units)
/// addPhysRegsUsed - Mark the specified registers used in this function. UsedRegUnits.set(*Units);
/// This should only be called during and after register allocation. }
void addPhysRegsUsed(const BitVector &Regs) { UsedPhysRegs |= Regs; }
/// addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as use d. /// addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as use d.
/// This corresponds to the bit mask attached to register mask operands. /// This corresponds to the bit mask attached to register mask operands.
void addPhysRegsUsedFromRegMask(const uint32_t *RegMask) { void addPhysRegsUsedFromRegMask(const uint32_t *RegMask) {
UsedPhysRegMask.setBitsNotInMask(RegMask); UsedPhysRegMask.setBitsNotInMask(RegMask);
} }
/// setPhysRegUnused - Mark the specified register unused in this functio n. /// setPhysRegUnused - Mark the specified register unused in this functio n.
/// This should only be called during and after register allocation. /// This should only be called during and after register allocation.
void setPhysRegUnused(unsigned Reg) { void setPhysRegUnused(unsigned Reg) {
UsedPhysRegs.reset(Reg);
UsedPhysRegMask.reset(Reg); UsedPhysRegMask.reset(Reg);
for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units)
UsedRegUnits.reset(*Units);
} }
//===-------------------------------------------------------------------- ===// //===-------------------------------------------------------------------- ===//
// Reserved Register Info // Reserved Register Info
//===-------------------------------------------------------------------- ===// //===-------------------------------------------------------------------- ===//
// //
// The set of reserved registers must be invariant during register // The set of reserved registers must be invariant during register
// allocation. For example, the target cannot suddenly decide it needs a // allocation. For example, the target cannot suddenly decide it needs a
// frame pointer when the register allocator has already used the frame // frame pointer when the register allocator has already used the frame
// pointer register for something else. // pointer register for something else.
skipping to change at line 394 skipping to change at line 428
return !ReservedRegs.empty(); return !ReservedRegs.empty();
} }
/// canReserveReg - Returns true if PhysReg can be used as a reserved /// canReserveReg - Returns true if PhysReg can be used as a reserved
/// register. Any register can be reserved before freezeReservedRegs() i s /// register. Any register can be reserved before freezeReservedRegs() i s
/// called. /// called.
bool canReserveReg(unsigned PhysReg) const { bool canReserveReg(unsigned PhysReg) const {
return !reservedRegsFrozen() || ReservedRegs.test(PhysReg); return !reservedRegsFrozen() || ReservedRegs.test(PhysReg);
} }
/// getReservedRegs - Returns a reference to the frozen set of reserved
/// registers. This method should always be preferred to calling
/// TRI::getReservedRegs() when possible.
const BitVector &getReservedRegs() const {
assert(reservedRegsFrozen() &&
"Reserved registers haven't been frozen yet. "
"Use TRI::getReservedRegs().");
return ReservedRegs;
}
/// isReserved - Returns true when PhysReg is a reserved register.
///
/// Reserved registers may belong to an allocatable register class, but t
he
/// target has explicitly requested that they are not used.
///
bool isReserved(unsigned PhysReg) const {
return getReservedRegs().test(PhysReg);
}
/// isAllocatable - Returns true when PhysReg belongs to an allocatable
/// register class and it hasn't been reserved.
///
/// Allocatable registers may show up in the allocation order of some vir
tual
/// register, so a register allocator needs to track its liveness and
/// availability.
bool isAllocatable(unsigned PhysReg) const {
return TRI->isInAllocatableClass(PhysReg) && !isReserved(PhysReg);
}
//===-------------------------------------------------------------------- ===// //===-------------------------------------------------------------------- ===//
// LiveIn/LiveOut Management // LiveIn/LiveOut Management
//===-------------------------------------------------------------------- ===// //===-------------------------------------------------------------------- ===//
/// addLiveIn/Out - Add the specified register as a live in/out. Note th at it /// addLiveIn/Out - Add the specified register as a live in/out. Note th at it
/// is an error to add the same register to the same set more than once. /// is an error to add the same register to the same set more than once.
void addLiveIn(unsigned Reg, unsigned vreg = 0) { void addLiveIn(unsigned Reg, unsigned vreg = 0) {
LiveIns.push_back(std::make_pair(Reg, vreg)); LiveIns.push_back(std::make_pair(Reg, vreg));
} }
void addLiveOut(unsigned Reg) { LiveOuts.push_back(Reg); } void addLiveOut(unsigned Reg) { LiveOuts.push_back(Reg); }
skipping to change at line 434 skipping to change at line 497
/// getLiveInVirtReg - If PReg is a live-in physical register, return the /// getLiveInVirtReg - If PReg is a live-in physical register, return the
/// corresponding live-in physical register. /// corresponding live-in physical register.
unsigned getLiveInVirtReg(unsigned PReg) const; unsigned getLiveInVirtReg(unsigned PReg) const;
/// EmitLiveInCopies - Emit copies to initialize livein virtual registers /// EmitLiveInCopies - Emit copies to initialize livein virtual registers
/// into the given entry block. /// into the given entry block.
void EmitLiveInCopies(MachineBasicBlock *EntryMBB, void EmitLiveInCopies(MachineBasicBlock *EntryMBB,
const TargetRegisterInfo &TRI, const TargetRegisterInfo &TRI,
const TargetInstrInfo &TII); const TargetInstrInfo &TII);
private:
void HandleVRegListReallocation();
public:
/// defusechain_iterator - This class provides iterator support for machi ne /// defusechain_iterator - This class provides iterator support for machi ne
/// operands in the function that use or define a specific register. If /// operands in the function that use or define a specific register. If
/// ReturnUses is true it returns uses of registers, if ReturnDefs is tru e it /// ReturnUses is true it returns uses of registers, if ReturnDefs is tru e it
/// returns defs. If neither are true then you are silly and it always /// returns defs. If neither are true then you are silly and it always
/// returns end(). If SkipDebug is true it skips uses marked Debug /// returns end(). If SkipDebug is true it skips uses marked Debug
/// when incrementing. /// when incrementing.
template<bool ReturnUses, bool ReturnDefs, bool SkipDebug> template<bool ReturnUses, bool ReturnDefs, bool SkipDebug>
class defusechain_iterator class defusechain_iterator
: public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff _t> { : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff _t> {
MachineOperand *Op; MachineOperand *Op;
skipping to change at line 481 skipping to change at line 540
bool operator!=(const defusechain_iterator &x) const { bool operator!=(const defusechain_iterator &x) const {
return !operator==(x); return !operator==(x);
} }
/// atEnd - return true if this iterator is equal to reg_end() on the v alue. /// atEnd - return true if this iterator is equal to reg_end() on the v alue.
bool atEnd() const { return Op == 0; } bool atEnd() const { return Op == 0; }
// Iterator traversal: forward iteration only // Iterator traversal: forward iteration only
defusechain_iterator &operator++() { // Preincrement defusechain_iterator &operator++() { // Preincrement
assert(Op && "Cannot increment end iterator!"); assert(Op && "Cannot increment end iterator!");
Op = Op->getNextOperandForReg(); Op = getNextOperandForReg(Op);
// If this is an operand we don't care about, skip it. // All defs come before the uses, so stop def_iterator early.
while (Op && ((!ReturnUses && Op->isUse()) || if (!ReturnUses) {
(!ReturnDefs && Op->isDef()) || if (Op) {
(SkipDebug && Op->isDebug()))) if (Op->isUse())
Op = Op->getNextOperandForReg(); Op = 0;
else
assert(!Op->isDebug() && "Can't have debug defs");
}
} else {
// If this is an operand we don't care about, skip it.
while (Op && ((!ReturnDefs && Op->isDef()) ||
(SkipDebug && Op->isDebug())))
Op = getNextOperandForReg(Op);
}
return *this; return *this;
} }
defusechain_iterator operator++(int) { // Postincrement defusechain_iterator operator++(int) { // Postincrement
defusechain_iterator tmp = *this; ++*this; return tmp; defusechain_iterator tmp = *this; ++*this; return tmp;
} }
/// skipInstruction - move forward until reaching a different instructi on. /// skipInstruction - move forward until reaching a different instructi on.
/// Return the skipped instruction that is no longer pointed to, or NUL L if /// Return the skipped instruction that is no longer pointed to, or NUL L if
/// already pointing to end(). /// already pointing to end().
 End of changes. 20 change blocks. 
54 lines changed or deleted 125 lines changed or added


 MachineSSAUpdater.h   MachineSSAUpdater.h 
skipping to change at line 17 skipping to change at line 17
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// //
// This file declares the MachineSSAUpdater class. // This file declares the MachineSSAUpdater class.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_CODEGEN_MACHINESSAUPDATER_H #ifndef LLVM_CODEGEN_MACHINESSAUPDATER_H
#define LLVM_CODEGEN_MACHINESSAUPDATER_H #define LLVM_CODEGEN_MACHINESSAUPDATER_H
#include "llvm/Support/Compiler.h"
namespace llvm { namespace llvm {
class MachineBasicBlock; class MachineBasicBlock;
class MachineFunction; class MachineFunction;
class MachineInstr; class MachineInstr;
class MachineOperand; class MachineOperand;
class MachineRegisterInfo; class MachineRegisterInfo;
class TargetInstrInfo; class TargetInstrInfo;
class TargetRegisterClass; class TargetRegisterClass;
template<typename T> class SmallVectorImpl; template<typename T> class SmallVectorImpl;
template<typename T> class SSAUpdaterTraits; template<typename T> class SSAUpdaterTraits;
skipping to change at line 109 skipping to change at line 111
/// which use their value in the corresponding predecessor. Note that th is /// which use their value in the corresponding predecessor. Note that th is
/// will not work if the use is supposed to be rewritten to a value defin ed in /// will not work if the use is supposed to be rewritten to a value defin ed in
/// the same block as the use, but above it. Any 'AddAvailableValue's ad ded /// the same block as the use, but above it. Any 'AddAvailableValue's ad ded
/// for the use's block will be considered to be below it. /// for the use's block will be considered to be below it.
void RewriteUse(MachineOperand &U); void RewriteUse(MachineOperand &U);
private: private:
void ReplaceRegWith(unsigned OldReg, unsigned NewReg); void ReplaceRegWith(unsigned OldReg, unsigned NewReg);
unsigned GetValueAtEndOfBlockInternal(MachineBasicBlock *BB); unsigned GetValueAtEndOfBlockInternal(MachineBasicBlock *BB);
void operator=(const MachineSSAUpdater&); // DO NOT IMPLEMENT void operator=(const MachineSSAUpdater&) LLVM_DELETED_FUNCTION;
MachineSSAUpdater(const MachineSSAUpdater&); // DO NOT IMPLEMENT MachineSSAUpdater(const MachineSSAUpdater&) LLVM_DELETED_FUNCTION;
}; };
} // End llvm namespace } // End llvm namespace
#endif #endif
 End of changes. 2 change blocks. 
2 lines changed or deleted 4 lines changed or added


 MachineScheduler.h   MachineScheduler.h 
skipping to change at line 22 skipping to change at line 22
// implementing the following boilerplate: // implementing the following boilerplate:
// //
// static ScheduleDAGInstrs *createCustomMachineSched(MachineSchedContext * C) { // static ScheduleDAGInstrs *createCustomMachineSched(MachineSchedContext * C) {
// return new CustomMachineScheduler(C); // return new CustomMachineScheduler(C);
// } // }
// static MachineSchedRegistry // static MachineSchedRegistry
// SchedCustomRegistry("custom", "Run my target's custom scheduler", // SchedCustomRegistry("custom", "Run my target's custom scheduler",
// createCustomMachineSched); // createCustomMachineSched);
// //
// Inside <Target>PassConfig: // Inside <Target>PassConfig:
// enablePass(MachineSchedulerID); // enablePass(&MachineSchedulerID);
// MachineSchedRegistry::setDefault(createCustomMachineSched); // MachineSchedRegistry::setDefault(createCustomMachineSched);
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef MACHINESCHEDULER_H #ifndef MACHINESCHEDULER_H
#define MACHINESCHEDULER_H #define MACHINESCHEDULER_H
#include "llvm/CodeGen/MachinePassRegistry.h" #include "llvm/CodeGen/MachinePassRegistry.h"
#include "llvm/CodeGen/RegisterPressure.h"
#include "llvm/CodeGen/ScheduleDAGInstrs.h"
#include "llvm/Target/TargetInstrInfo.h"
namespace llvm { namespace llvm {
extern cl::opt<bool> ForceTopDown;
extern cl::opt<bool> ForceBottomUp;
class AliasAnalysis; class AliasAnalysis;
class LiveIntervals; class LiveIntervals;
class MachineDominatorTree; class MachineDominatorTree;
class MachineLoopInfo; class MachineLoopInfo;
class RegisterClassInfo;
class ScheduleDAGInstrs; class ScheduleDAGInstrs;
/// MachineSchedContext provides enough context from the MachineScheduler p ass /// MachineSchedContext provides enough context from the MachineScheduler p ass
/// for the target to instantiate a scheduler. /// for the target to instantiate a scheduler.
struct MachineSchedContext { struct MachineSchedContext {
MachineFunction *MF; MachineFunction *MF;
const MachineLoopInfo *MLI; const MachineLoopInfo *MLI;
const MachineDominatorTree *MDT; const MachineDominatorTree *MDT;
const TargetPassConfig *PassConfig; const TargetPassConfig *PassConfig;
AliasAnalysis *AA; AliasAnalysis *AA;
LiveIntervals *LIS; LiveIntervals *LIS;
MachineSchedContext(): MF(0), MLI(0), MDT(0), PassConfig(0), AA(0), LIS(0 RegisterClassInfo *RegClassInfo;
) {}
MachineSchedContext();
virtual ~MachineSchedContext();
}; };
/// MachineSchedRegistry provides a selection of available machine instruct ion /// MachineSchedRegistry provides a selection of available machine instruct ion
/// schedulers. /// schedulers.
class MachineSchedRegistry : public MachinePassRegistryNode { class MachineSchedRegistry : public MachinePassRegistryNode {
public: public:
typedef ScheduleDAGInstrs *(*ScheduleDAGCtor)(MachineSchedContext *); typedef ScheduleDAGInstrs *(*ScheduleDAGCtor)(MachineSchedContext *);
// RegisterPassParser requires a (misnamed) FunctionPassCtor type. // RegisterPassParser requires a (misnamed) FunctionPassCtor type.
typedef ScheduleDAGCtor FunctionPassCtor; typedef ScheduleDAGCtor FunctionPassCtor;
skipping to change at line 84 skipping to change at line 94
} }
static MachineSchedRegistry *getList() { static MachineSchedRegistry *getList() {
return (MachineSchedRegistry *)Registry.getList(); return (MachineSchedRegistry *)Registry.getList();
} }
static ScheduleDAGCtor getDefault() { static ScheduleDAGCtor getDefault() {
return (ScheduleDAGCtor)Registry.getDefault(); return (ScheduleDAGCtor)Registry.getDefault();
} }
static void setDefault(ScheduleDAGCtor C) { static void setDefault(ScheduleDAGCtor C) {
Registry.setDefault((MachinePassCtor)C); Registry.setDefault((MachinePassCtor)C);
} }
static void setDefault(StringRef Name) {
Registry.setDefault(Name);
}
static void setListener(MachinePassRegistryListener *L) { static void setListener(MachinePassRegistryListener *L) {
Registry.setListener(L); Registry.setListener(L);
} }
}; };
class ScheduleDAGMI;
/// MachineSchedStrategy - Interface to the scheduling algorithm used by
/// ScheduleDAGMI.
class MachineSchedStrategy {
public:
virtual ~MachineSchedStrategy() {}
/// Initialize the strategy after building the DAG for a new region.
virtual void initialize(ScheduleDAGMI *DAG) = 0;
/// Notify this strategy that all roots have been released (including tho
se
/// that depend on EntrySU or ExitSU).
virtual void registerRoots() {}
/// Pick the next node to schedule, or return NULL. Set IsTopNode to true
to
/// schedule the node at the top of the unscheduled region. Otherwise it
will
/// be scheduled at the bottom.
virtual SUnit *pickNode(bool &IsTopNode) = 0;
/// Notify MachineSchedStrategy that ScheduleDAGMI has scheduled an
/// instruction and updated scheduled/remaining flags in the DAG nodes.
virtual void schedNode(SUnit *SU, bool IsTopNode) = 0;
/// When all predecessor dependencies have been resolved, free this node
for
/// top-down scheduling.
virtual void releaseTopNode(SUnit *SU) = 0;
/// When all successor dependencies have been resolved, free this node fo
r
/// bottom-up scheduling.
virtual void releaseBottomNode(SUnit *SU) = 0;
};
/// ReadyQueue encapsulates vector of "ready" SUnits with basic convenience
/// methods for pushing and removing nodes. ReadyQueue's are uniquely ident
ified
/// by an ID. SUnit::NodeQueueId is a mask of the ReadyQueues the SUnit is
in.
///
/// This is a convenience class that may be used by implementations of
/// MachineSchedStrategy.
class ReadyQueue {
unsigned ID;
std::string Name;
std::vector<SUnit*> Queue;
public:
ReadyQueue(unsigned id, const Twine &name): ID(id), Name(name.str()) {}
unsigned getID() const { return ID; }
StringRef getName() const { return Name; }
// SU is in this queue if it's NodeQueueID is a superset of this ID.
bool isInQueue(SUnit *SU) const { return (SU->NodeQueueId & ID); }
bool empty() const { return Queue.empty(); }
void clear() { Queue.clear(); }
unsigned size() const { return Queue.size(); }
typedef std::vector<SUnit*>::iterator iterator;
iterator begin() { return Queue.begin(); }
iterator end() { return Queue.end(); }
iterator find(SUnit *SU) {
return std::find(Queue.begin(), Queue.end(), SU);
}
void push(SUnit *SU) {
Queue.push_back(SU);
SU->NodeQueueId |= ID;
}
iterator remove(iterator I) {
(*I)->NodeQueueId &= ~ID;
*I = Queue.back();
unsigned idx = I - Queue.begin();
Queue.pop_back();
return Queue.begin() + idx;
}
#ifndef NDEBUG
void dump();
#endif
};
/// Mutate the DAG as a postpass after normal DAG building.
class ScheduleDAGMutation {
public:
virtual ~ScheduleDAGMutation() {}
virtual void apply(ScheduleDAGMI *DAG) = 0;
};
/// ScheduleDAGMI is an implementation of ScheduleDAGInstrs that schedules
/// machine instructions while updating LiveIntervals and tracking regpress
ure.
class ScheduleDAGMI : public ScheduleDAGInstrs {
protected:
AliasAnalysis *AA;
RegisterClassInfo *RegClassInfo;
MachineSchedStrategy *SchedImpl;
/// Ordered list of DAG postprocessing steps.
std::vector<ScheduleDAGMutation*> Mutations;
MachineBasicBlock::iterator LiveRegionEnd;
/// Register pressure in this region computed by buildSchedGraph.
IntervalPressure RegPressure;
RegPressureTracker RPTracker;
/// List of pressure sets that exceed the target's pressure limit before
/// scheduling, listed in increasing set ID order. Each pressure set is p
aired
/// with its max pressure in the currently scheduled regions.
std::vector<PressureElement> RegionCriticalPSets;
/// The top of the unscheduled zone.
MachineBasicBlock::iterator CurrentTop;
IntervalPressure TopPressure;
RegPressureTracker TopRPTracker;
/// The bottom of the unscheduled zone.
MachineBasicBlock::iterator CurrentBottom;
IntervalPressure BotPressure;
RegPressureTracker BotRPTracker;
#ifndef NDEBUG
/// The number of instructions scheduled so far. Used to cut off the
/// scheduler at the point determined by misched-cutoff.
unsigned NumInstrsScheduled;
#endif
public:
ScheduleDAGMI(MachineSchedContext *C, MachineSchedStrategy *S):
ScheduleDAGInstrs(*C->MF, *C->MLI, *C->MDT, /*IsPostRA=*/false, C->LIS)
,
AA(C->AA), RegClassInfo(C->RegClassInfo), SchedImpl(S),
RPTracker(RegPressure), CurrentTop(), TopRPTracker(TopPressure),
CurrentBottom(), BotRPTracker(BotPressure) {
#ifndef NDEBUG
NumInstrsScheduled = 0;
#endif
}
virtual ~ScheduleDAGMI() {
delete SchedImpl;
}
/// Add a postprocessing step to the DAG builder.
/// Mutations are applied in the order that they are added after normal D
AG
/// building and before MachineSchedStrategy initialization.
void addMutation(ScheduleDAGMutation *Mutation) {
Mutations.push_back(Mutation);
}
MachineBasicBlock::iterator top() const { return CurrentTop; }
MachineBasicBlock::iterator bottom() const { return CurrentBottom; }
/// Implement the ScheduleDAGInstrs interface for handling the next sched
uling
/// region. This covers all instructions in a block, while schedule() may
only
/// cover a subset.
void enterRegion(MachineBasicBlock *bb,
MachineBasicBlock::iterator begin,
MachineBasicBlock::iterator end,
unsigned endcount);
/// Implement ScheduleDAGInstrs interface for scheduling a sequence of
/// reorderable instructions.
virtual void schedule();
/// Get current register pressure for the top scheduled instructions.
const IntervalPressure &getTopPressure() const { return TopPressure; }
const RegPressureTracker &getTopRPTracker() const { return TopRPTracker;
}
/// Get current register pressure for the bottom scheduled instructions.
const IntervalPressure &getBotPressure() const { return BotPressure; }
const RegPressureTracker &getBotRPTracker() const { return BotRPTracker;
}
/// Get register pressure for the entire scheduling region before schedul
ing.
const IntervalPressure &getRegPressure() const { return RegPressure; }
const std::vector<PressureElement> &getRegionCriticalPSets() const {
return RegionCriticalPSets;
}
protected:
// Top-Level entry points for the schedule() driver...
/// Call ScheduleDAGInstrs::buildSchedGraph with register pressure tracki
ng
/// enabled. This sets up three trackers. RPTracker will cover the entire
DAG
/// region, TopTracker and BottomTracker will be initialized to the top a
nd
/// bottom of the DAG region without covereing any unscheduled instructio
n.
void buildDAGWithRegPressure();
/// Apply each ScheduleDAGMutation step in order. This allows different
/// instances of ScheduleDAGMI to perform custom DAG postprocessing.
void postprocessDAG();
/// Identify DAG roots and setup scheduler queues.
void initQueues();
/// Move an instruction and update register pressure.
void scheduleMI(SUnit *SU, bool IsTopNode);
/// Update scheduler DAG and queues after scheduling an instruction.
void updateQueues(SUnit *SU, bool IsTopNode);
/// Reinsert debug_values recorded in ScheduleDAGInstrs::DbgValues.
void placeDebugValues();
/// \brief dump the scheduled Sequence.
void dumpSchedule() const;
// Lesser helpers...
void initRegPressure();
void updateScheduledPressure(std::vector<unsigned> NewMaxPressure);
void moveInstruction(MachineInstr *MI, MachineBasicBlock::iterator Insert
Pos);
bool checkSchedLimit();
void releaseRoots();
void releaseSucc(SUnit *SU, SDep *SuccEdge);
void releaseSuccessors(SUnit *SU);
void releasePred(SUnit *SU, SDep *PredEdge);
void releasePredecessors(SUnit *SU);
};
} // namespace llvm } // namespace llvm
#endif #endif
 End of changes. 7 change blocks. 
3 lines changed or deleted 266 lines changed or added


 Main.h   Main.h 
skipping to change at line 19 skipping to change at line 19
// //
// This file declares the common entry point for tblgen tools. // This file declares the common entry point for tblgen tools.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_TABLEGEN_MAIN_H #ifndef LLVM_TABLEGEN_MAIN_H
#define LLVM_TABLEGEN_MAIN_H #define LLVM_TABLEGEN_MAIN_H
namespace llvm { namespace llvm {
class TableGenAction; class RecordKeeper;
class raw_ostream;
/// \brief Perform the action using Records, and write output to OS.
/// \returns true on error, false otherwise
typedef bool TableGenMainFn(raw_ostream &OS, RecordKeeper &Records);
/// Run the table generator, performing the specified Action on parsed reco int TableGenMain(char *argv0, TableGenMainFn *MainFn);
rds.
int TableGenMain(char *argv0, TableGenAction &Action);
} }
#endif #endif
 End of changes. 2 change blocks. 
4 lines changed or deleted 6 lines changed or added


 Mangler.h   Mangler.h 
skipping to change at line 25 skipping to change at line 25
#define LLVM_SUPPORT_MANGLER_H #define LLVM_SUPPORT_MANGLER_H
#include "llvm/ADT/DenseMap.h" #include "llvm/ADT/DenseMap.h"
namespace llvm { namespace llvm {
class Twine; class Twine;
class GlobalValue; class GlobalValue;
template <typename T> class SmallVectorImpl; template <typename T> class SmallVectorImpl;
class MCContext; class MCContext;
class MCSymbol; class MCSymbol;
class TargetData; class DataLayout;
class Mangler { class Mangler {
public: public:
enum ManglerPrefixTy { enum ManglerPrefixTy {
Default, ///< Emit default string before each symbol. Default, ///< Emit default string before each symbol.
Private, ///< Emit "private" prefix before each symbol. Private, ///< Emit "private" prefix before each symbol.
LinkerPrivate ///< Emit "linker private" prefix before each sy mbol. LinkerPrivate ///< Emit "linker private" prefix before each sy mbol.
}; };
private: private:
MCContext &Context; MCContext &Context;
const TargetData &TD; const DataLayout &TD;
/// AnonGlobalIDs - We need to give global values the same name every tim e /// AnonGlobalIDs - We need to give global values the same name every tim e
/// they are mangled. This keeps track of the number we give to anonymou s /// they are mangled. This keeps track of the number we give to anonymou s
/// ones. /// ones.
/// ///
DenseMap<const GlobalValue*, unsigned> AnonGlobalIDs; DenseMap<const GlobalValue*, unsigned> AnonGlobalIDs;
/// NextAnonGlobalID - This simple counter is used to unique value names. /// NextAnonGlobalID - This simple counter is used to unique value names.
/// ///
unsigned NextAnonGlobalID; unsigned NextAnonGlobalID;
public: public:
Mangler(MCContext &context, const TargetData &td) Mangler(MCContext &context, const DataLayout &td)
: Context(context), TD(td), NextAnonGlobalID(1) {} : Context(context), TD(td), NextAnonGlobalID(1) {}
/// getSymbol - Return the MCSymbol for the specified global value. This /// getSymbol - Return the MCSymbol for the specified global value. This
/// symbol is the main label that is the address of the global. /// symbol is the main label that is the address of the global.
MCSymbol *getSymbol(const GlobalValue *GV); MCSymbol *getSymbol(const GlobalValue *GV);
/// getNameWithPrefix - Fill OutName with the name of the appropriate pre fix /// getNameWithPrefix - Fill OutName with the name of the appropriate pre fix
/// and the specified global variable's name. If the global variable doe sn't /// and the specified global variable's name. If the global variable doe sn't
/// have a name, this fills in a unique name for the global. /// have a name, this fills in a unique name for the global.
void getNameWithPrefix(SmallVectorImpl<char> &OutName, const GlobalValue *GV, void getNameWithPrefix(SmallVectorImpl<char> &OutName, const GlobalValue *GV,
 End of changes. 3 change blocks. 
3 lines changed or deleted 3 lines changed or added


 MathExtras.h   MathExtras.h 
skipping to change at line 417 skipping to change at line 417
/// Platform-independent wrappers for the C99 isnan() function. /// Platform-independent wrappers for the C99 isnan() function.
int IsNAN(float f); int IsNAN(float f);
int IsNAN(double d); int IsNAN(double d);
/// Platform-independent wrappers for the C99 isinf() function. /// Platform-independent wrappers for the C99 isinf() function.
int IsInf(float f); int IsInf(float f);
int IsInf(double d); int IsInf(double d);
/// MinAlign - A and B are either alignments or offsets. Return the minimu m /// MinAlign - A and B are either alignments or offsets. Return the minimu m
/// alignment that may be assumed after adding the two together. /// alignment that may be assumed after adding the two together.
static inline uint64_t MinAlign(uint64_t A, uint64_t B) { inline uint64_t MinAlign(uint64_t A, uint64_t B) {
// The largest power of 2 that divides both A and B. // The largest power of 2 that divides both A and B.
return (A | B) & -(A | B); return (A | B) & -(A | B);
} }
/// NextPowerOf2 - Returns the next power of two (in 64-bits) /// NextPowerOf2 - Returns the next power of two (in 64-bits)
/// that is strictly greater than A. Returns zero on overflow. /// that is strictly greater than A. Returns zero on overflow.
static inline uint64_t NextPowerOf2(uint64_t A) { inline uint64_t NextPowerOf2(uint64_t A) {
A |= (A >> 1); A |= (A >> 1);
A |= (A >> 2); A |= (A >> 2);
A |= (A >> 4); A |= (A >> 4);
A |= (A >> 8); A |= (A >> 8);
A |= (A >> 16); A |= (A >> 16);
A |= (A >> 32); A |= (A >> 32);
return A + 1; return A + 1;
} }
/// RoundUpToAlignment - Returns the next integer (mod 2**64) that is /// Returns the next integer (mod 2**64) that is greater than or equal to
/// greater than or equal to \arg Value and is a multiple of \arg /// \p Value and is a multiple of \p Align. \p Align must be non-zero.
/// Align. Align must be non-zero.
/// ///
/// Examples: /// Examples:
/// RoundUpToAlignment(5, 8) = 8 /// \code
/// RoundUpToAlignment(17, 8) = 24 /// RoundUpToAlignment(5, 8) = 8
/// RoundUpToAlignment(~0LL, 8) = 0 /// RoundUpToAlignment(17, 8) = 24
/// RoundUpToAlignment(~0LL, 8) = 0
/// \endcode
inline uint64_t RoundUpToAlignment(uint64_t Value, uint64_t Align) { inline uint64_t RoundUpToAlignment(uint64_t Value, uint64_t Align) {
return ((Value + Align - 1) / Align) * Align; return ((Value + Align - 1) / Align) * Align;
} }
/// OffsetToAlignment - Return the offset to the next integer (mod 2**64) t /// Returns the offset to the next integer (mod 2**64) that is greater than
hat /// or equal to \p Value and is a multiple of \p Align. \p Align must be
/// is greater than or equal to \arg Value and is a multiple of \arg /// non-zero.
/// Align. Align must be non-zero.
inline uint64_t OffsetToAlignment(uint64_t Value, uint64_t Align) { inline uint64_t OffsetToAlignment(uint64_t Value, uint64_t Align) {
return RoundUpToAlignment(Value, Align) - Value; return RoundUpToAlignment(Value, Align) - Value;
} }
/// abs64 - absolute value of a 64-bit int. Not all environments support /// abs64 - absolute value of a 64-bit int. Not all environments support
/// "abs" on whatever their name for the 64-bit int type is. The absolute /// "abs" on whatever their name for the 64-bit int type is. The absolute
/// value of the largest negative number is undefined, as with "abs". /// value of the largest negative number is undefined, as with "abs".
inline int64_t abs64(int64_t x) { inline int64_t abs64(int64_t x) {
return (x < 0) ? -x : x; return (x < 0) ? -x : x;
} }
/// SignExtend32 - Sign extend B-bit number x to 32-bit int. /// SignExtend32 - Sign extend B-bit number x to 32-bit int.
/// Usage int32_t r = SignExtend32<5>(x); /// Usage int32_t r = SignExtend32<5>(x);
template <unsigned B> inline int32_t SignExtend32(uint32_t x) { template <unsigned B> inline int32_t SignExtend32(uint32_t x) {
return int32_t(x << (32 - B)) >> (32 - B); return int32_t(x << (32 - B)) >> (32 - B);
} }
/// \brief Sign extend number in the bottom B bits of X to a 32-bit int.
/// Requires 0 < B <= 32.
inline int32_t SignExtend32(uint32_t X, unsigned B) {
return int32_t(X << (32 - B)) >> (32 - B);
}
/// SignExtend64 - Sign extend B-bit number x to 64-bit int. /// SignExtend64 - Sign extend B-bit number x to 64-bit int.
/// Usage int64_t r = SignExtend64<5>(x); /// Usage int64_t r = SignExtend64<5>(x);
template <unsigned B> inline int64_t SignExtend64(uint64_t x) { template <unsigned B> inline int64_t SignExtend64(uint64_t x) {
return int64_t(x << (64 - B)) >> (64 - B); return int64_t(x << (64 - B)) >> (64 - B);
} }
/// \brief Sign extend number in the bottom B bits of X to a 64-bit int.
/// Requires 0 < B <= 64.
inline int64_t SignExtend64(uint64_t X, unsigned B) {
return int64_t(X << (64 - B)) >> (64 - B);
}
} // End llvm namespace } // End llvm namespace
#endif #endif
 End of changes. 7 change blocks. 
12 lines changed or deleted 24 lines changed or added


 Memory.h   Memory.h 
skipping to change at line 18 skipping to change at line 18
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// //
// This file declares the llvm::sys::Memory class. // This file declares the llvm::sys::Memory class.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_SYSTEM_MEMORY_H #ifndef LLVM_SYSTEM_MEMORY_H
#define LLVM_SYSTEM_MEMORY_H #define LLVM_SYSTEM_MEMORY_H
#include "llvm/Support/DataTypes.h" #include "llvm/Support/DataTypes.h"
#include "llvm/Support/system_error.h"
#include <string> #include <string>
namespace llvm { namespace llvm {
namespace sys { namespace sys {
/// This class encapsulates the notion of a memory block which has an add ress /// This class encapsulates the notion of a memory block which has an add ress
/// and a size. It is used by the Memory class (a friend) as the result o f /// and a size. It is used by the Memory class (a friend) as the result o f
/// various memory allocation operations. /// various memory allocation operations.
/// @see Memory /// @see Memory
/// @brief Memory block abstraction. /// @brief Memory block abstraction.
skipping to change at line 46 skipping to change at line 47
size_t Size; ///< Size, in bytes of the memory area size_t Size; ///< Size, in bytes of the memory area
friend class Memory; friend class Memory;
}; };
/// This class provides various memory handling functions that manipulate /// This class provides various memory handling functions that manipulate
/// MemoryBlock instances. /// MemoryBlock instances.
/// @since 1.4 /// @since 1.4
/// @brief An abstraction for memory operations. /// @brief An abstraction for memory operations.
class Memory { class Memory {
public: public:
enum ProtectionFlags {
MF_READ = 0x1000000,
MF_WRITE = 0x2000000,
MF_EXEC = 0x4000000
};
/// This method allocates a block of memory that is suitable for loadin
g
/// dynamically generated code (e.g. JIT). An attempt to allocate
/// \p NumBytes bytes of virtual memory is made.
/// \p NearBlock may point to an existing allocation in which case
/// an attempt is made to allocate more memory near the existing block.
/// The actual allocated address is not guaranteed to be near the reque
sted
/// address.
/// \p Flags is used to set the initial protection flags for the block
/// of the memory.
/// \p EC [out] returns an object describing any error that occurs.
///
/// This method may allocate more than the number of bytes requested.
The
/// actual number of bytes allocated is indicated in the returned
/// MemoryBlock.
///
/// The start of the allocated block must be aligned with the
/// system allocation granularity (64K on Windows, page size on Linux).
/// If the address following \p NearBlock is not so aligned, it will be
/// rounded up to the next allocation granularity boundary.
///
/// \r a non-null MemoryBlock if the function was successful,
/// otherwise a null MemoryBlock is with \p EC describing the error.
///
/// @brief Allocate mapped memory.
static MemoryBlock allocateMappedMemory(size_t NumBytes,
const MemoryBlock *const NearBl
ock,
unsigned Flags,
error_code &EC);
/// This method releases a block of memory that was allocated with the
/// allocateMappedMemory method. It should not be used to release any
/// memory block allocated any other way.
/// \p Block describes the memory to be released.
///
/// \r error_success if the function was successful, or an error_code
/// describing the failure if an error occurred.
///
/// @brief Release mapped memory.
static error_code releaseMappedMemory(MemoryBlock &Block);
/// This method sets the protection flags for a block of memory to the
/// state specified by /p Flags. The behavior is not specified if the
/// memory was not allocated using the allocateMappedMemory method.
/// \p Block describes the memory block to be protected.
/// \p Flags specifies the new protection state to be assigned to the b
lock.
/// \p ErrMsg [out] returns a string describing any error that occured.
///
/// If \p Flags is MF_WRITE, the actual behavior varies
/// with the operating system (i.e. MF_READ | MF_WRITE on Windows) and
the
/// target architecture (i.e. MF_WRITE -> MF_READ | MF_WRITE on i386).
///
/// \r error_success if the function was successful, or an error_code
/// describing the failure if an error occurred.
///
/// @brief Set memory protection state.
static error_code protectMappedMemory(const MemoryBlock &Block,
unsigned Flags);
/// This method allocates a block of Read/Write/Execute memory that is /// This method allocates a block of Read/Write/Execute memory that is
/// suitable for executing dynamically generated code (e.g. JIT). An /// suitable for executing dynamically generated code (e.g. JIT). An
/// attempt to allocate \p NumBytes bytes of virtual memory is made. /// attempt to allocate \p NumBytes bytes of virtual memory is made.
/// \p NearBlock may point to an existing allocation in which case /// \p NearBlock may point to an existing allocation in which case
/// an attempt is made to allocate more memory near the existing block. /// an attempt is made to allocate more memory near the existing block.
/// ///
/// On success, this returns a non-null memory block, otherwise it retu rns /// On success, this returns a non-null memory block, otherwise it retu rns
/// a null memory block and fills in *ErrMsg. /// a null memory block and fills in *ErrMsg.
/// ///
/// @brief Allocate Read/Write/Execute memory. /// @brief Allocate Read/Write/Execute memory.
 End of changes. 2 change blocks. 
0 lines changed or deleted 71 lines changed or added


 MemoryBuffer.h   MemoryBuffer.h 
skipping to change at line 18 skipping to change at line 18
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// //
// This file defines the MemoryBuffer interface. // This file defines the MemoryBuffer interface.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_SUPPORT_MEMORYBUFFER_H #ifndef LLVM_SUPPORT_MEMORYBUFFER_H
#define LLVM_SUPPORT_MEMORYBUFFER_H #define LLVM_SUPPORT_MEMORYBUFFER_H
#include "llvm/ADT/StringRef.h" #include "llvm/ADT/StringRef.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/DataTypes.h" #include "llvm/Support/DataTypes.h"
namespace llvm { namespace llvm {
class error_code; class error_code;
template<class T> class OwningPtr; template<class T> class OwningPtr;
/// MemoryBuffer - This interface provides simple read-only access to a blo ck /// MemoryBuffer - This interface provides simple read-only access to a blo ck
/// of memory, and provides simple methods for reading files and standard i nput /// of memory, and provides simple methods for reading files and standard i nput
/// into a memory buffer. In addition to basic access to the characters in the /// into a memory buffer. In addition to basic access to the characters in the
skipping to change at line 39 skipping to change at line 40
/// the file, and that this character will read as '\0'. /// the file, and that this character will read as '\0'.
/// ///
/// The '\0' guarantee is needed to support an optimization -- it's intende d to /// The '\0' guarantee is needed to support an optimization -- it's intende d to
/// be more efficient for clients which are reading all the data to stop /// be more efficient for clients which are reading all the data to stop
/// reading when they encounter a '\0' than to continually check the file /// reading when they encounter a '\0' than to continually check the file
/// position to see if it has reached the end of the file. /// position to see if it has reached the end of the file.
class MemoryBuffer { class MemoryBuffer {
const char *BufferStart; // Start of the buffer. const char *BufferStart; // Start of the buffer.
const char *BufferEnd; // End of the buffer. const char *BufferEnd; // End of the buffer.
MemoryBuffer(const MemoryBuffer &); // DO NOT IMPLEMENT MemoryBuffer(const MemoryBuffer &) LLVM_DELETED_FUNCTION;
MemoryBuffer &operator=(const MemoryBuffer &); // DO NOT IMPLEMENT MemoryBuffer &operator=(const MemoryBuffer &) LLVM_DELETED_FUNCTION;
protected: protected:
MemoryBuffer() {} MemoryBuffer() {}
void init(const char *BufStart, const char *BufEnd, void init(const char *BufStart, const char *BufEnd,
bool RequiresNullTerminator); bool RequiresNullTerminator);
public: public:
virtual ~MemoryBuffer(); virtual ~MemoryBuffer();
const char *getBufferStart() const { return BufferStart; } const char *getBufferStart() const { return BufferStart; }
const char *getBufferEnd() const { return BufferEnd; } const char *getBufferEnd() const { return BufferEnd; }
size_t getBufferSize() const { return BufferEnd-BufferStart; } size_t getBufferSize() const { return BufferEnd-BufferStart; }
 End of changes. 2 change blocks. 
2 lines changed or deleted 3 lines changed or added


 MemoryBuiltins.h   MemoryBuiltins.h 
skipping to change at line 18 skipping to change at line 18
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// //
// This family of functions identifies calls to builtin functions that allo cate // This family of functions identifies calls to builtin functions that allo cate
// or free memory. // or free memory.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_ANALYSIS_MEMORYBUILTINS_H #ifndef LLVM_ANALYSIS_MEMORYBUILTINS_H
#define LLVM_ANALYSIS_MEMORYBUILTINS_H #define LLVM_ANALYSIS_MEMORYBUILTINS_H
#include "llvm/IRBuilder.h"
#include "llvm/Operator.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/Support/DataTypes.h"
#include "llvm/Support/InstVisitor.h"
#include "llvm/Support/TargetFolder.h"
#include "llvm/Support/ValueHandle.h"
namespace llvm { namespace llvm {
class CallInst; class CallInst;
class PointerType; class PointerType;
class TargetData; class DataLayout;
class TargetLibraryInfo;
class Type; class Type;
class Value; class Value;
/// \brief Tests if a value is a call or invoke to a library function that
/// allocates or reallocates memory (either malloc, calloc, realloc, or str
dup
/// like).
bool isAllocationFn(const Value *V, const TargetLibraryInfo *TLI,
bool LookThroughBitCast = false);
/// \brief Tests if a value is a call or invoke to a function that returns
a
/// NoAlias pointer (including malloc/calloc/realloc/strdup-like functions)
.
bool isNoAliasFn(const Value *V, const TargetLibraryInfo *TLI,
bool LookThroughBitCast = false);
/// \brief Tests if a value is a call or invoke to a library function that
/// allocates uninitialized memory (such as malloc).
bool isMallocLikeFn(const Value *V, const TargetLibraryInfo *TLI,
bool LookThroughBitCast = false);
/// \brief Tests if a value is a call or invoke to a library function that
/// allocates zero-filled memory (such as calloc).
bool isCallocLikeFn(const Value *V, const TargetLibraryInfo *TLI,
bool LookThroughBitCast = false);
/// \brief Tests if a value is a call or invoke to a library function that
/// allocates memory (either malloc, calloc, or strdup like).
bool isAllocLikeFn(const Value *V, const TargetLibraryInfo *TLI,
bool LookThroughBitCast = false);
/// \brief Tests if a value is a call or invoke to a library function that
/// reallocates memory (such as realloc).
bool isReallocLikeFn(const Value *V, const TargetLibraryInfo *TLI,
bool LookThroughBitCast = false);
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// malloc Call Utility Functions. // malloc Call Utility Functions.
// //
/// isMalloc - Returns true if the value is either a malloc call or a bitca
st of
/// the result of a malloc call
bool isMalloc(const Value *I);
/// extractMallocCall - Returns the corresponding CallInst if the instructi on /// extractMallocCall - Returns the corresponding CallInst if the instructi on
/// is a malloc call. Since CallInst::CreateMalloc() only creates calls, w e /// is a malloc call. Since CallInst::CreateMalloc() only creates calls, w e
/// ignore InvokeInst here. /// ignore InvokeInst here.
const CallInst *extractMallocCall(const Value *I); const CallInst *extractMallocCall(const Value *I, const TargetLibraryInfo *
CallInst *extractMallocCall(Value *I); TLI);
static inline CallInst *extractMallocCall(Value *I,
/// extractMallocCallFromBitCast - Returns the corresponding CallInst if th const TargetLibraryInfo *TLI) {
e return const_cast<CallInst*>(extractMallocCall((const Value*)I, TLI));
/// instruction is a bitcast of the result of a malloc call. }
const CallInst *extractMallocCallFromBitCast(const Value *I);
CallInst *extractMallocCallFromBitCast(Value *I);
/// isArrayMalloc - Returns the corresponding CallInst if the instruction /// isArrayMalloc - Returns the corresponding CallInst if the instruction
/// is a call to malloc whose array size can be determined and the array si ze /// is a call to malloc whose array size can be determined and the array si ze
/// is not constant 1. Otherwise, return NULL. /// is not constant 1. Otherwise, return NULL.
const CallInst *isArrayMalloc(const Value *I, const TargetData *TD); const CallInst *isArrayMalloc(const Value *I, const DataLayout *TD,
const TargetLibraryInfo *TLI);
/// getMallocType - Returns the PointerType resulting from the malloc call. /// getMallocType - Returns the PointerType resulting from the malloc call.
/// The PointerType depends on the number of bitcast uses of the malloc cal l: /// The PointerType depends on the number of bitcast uses of the malloc cal l:
/// 0: PointerType is the malloc calls' return type. /// 0: PointerType is the malloc calls' return type.
/// 1: PointerType is the bitcast's result type. /// 1: PointerType is the bitcast's result type.
/// >1: Unique PointerType cannot be determined, return NULL. /// >1: Unique PointerType cannot be determined, return NULL.
PointerType *getMallocType(const CallInst *CI); PointerType *getMallocType(const CallInst *CI, const TargetLibraryInfo *TLI );
/// getMallocAllocatedType - Returns the Type allocated by malloc call. /// getMallocAllocatedType - Returns the Type allocated by malloc call.
/// The Type depends on the number of bitcast uses of the malloc call: /// The Type depends on the number of bitcast uses of the malloc call:
/// 0: PointerType is the malloc calls' return type. /// 0: PointerType is the malloc calls' return type.
/// 1: PointerType is the bitcast's result type. /// 1: PointerType is the bitcast's result type.
/// >1: Unique PointerType cannot be determined, return NULL. /// >1: Unique PointerType cannot be determined, return NULL.
Type *getMallocAllocatedType(const CallInst *CI); Type *getMallocAllocatedType(const CallInst *CI, const TargetLibraryInfo *T LI);
/// getMallocArraySize - Returns the array size of a malloc call. If the /// getMallocArraySize - Returns the array size of a malloc call. If the
/// argument passed to malloc is a multiple of the size of the malloced typ e, /// argument passed to malloc is a multiple of the size of the malloced typ e,
/// then return that multiple. For non-array mallocs, the multiple is /// then return that multiple. For non-array mallocs, the multiple is
/// constant 1. Otherwise, return NULL for mallocs whose array size cannot be /// constant 1. Otherwise, return NULL for mallocs whose array size cannot be
/// determined. /// determined.
Value *getMallocArraySize(CallInst *CI, const TargetData *TD, Value *getMallocArraySize(CallInst *CI, const DataLayout *TD,
const TargetLibraryInfo *TLI,
bool LookThroughSExt = false); bool LookThroughSExt = false);
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// calloc Call Utility Functions.
//
/// extractCallocCall - Returns the corresponding CallInst if the instructi
on
/// is a calloc call.
const CallInst *extractCallocCall(const Value *I, const TargetLibraryInfo *
TLI);
static inline CallInst *extractCallocCall(Value *I,
const TargetLibraryInfo *TLI) {
return const_cast<CallInst*>(extractCallocCall((const Value*)I, TLI));
}
//===----------------------------------------------------------------------
===//
// free Call Utility Functions. // free Call Utility Functions.
// //
/// isFreeCall - Returns non-null if the value is a call to the builtin fre e() /// isFreeCall - Returns non-null if the value is a call to the builtin fre e()
const CallInst *isFreeCall(const Value *I); const CallInst *isFreeCall(const Value *I, const TargetLibraryInfo *TLI);
static inline CallInst *isFreeCall(Value *I) { static inline CallInst *isFreeCall(Value *I, const TargetLibraryInfo *TLI)
return const_cast<CallInst*>(isFreeCall((const Value*)I)); {
return const_cast<CallInst*>(isFreeCall((const Value*)I, TLI));
} }
//===----------------------------------------------------------------------
===//
// Utility functions to compute size of objects.
//
/// \brief Compute the size of the object pointed by Ptr. Returns true and
the
/// object size in Size if successful, and false otherwise.
/// If RoundToAlign is true, then Size is rounded up to the aligment of all
ocas,
/// byval arguments, and global variables.
bool getObjectSize(const Value *Ptr, uint64_t &Size, const DataLayout *TD,
const TargetLibraryInfo *TLI, bool RoundToAlign = false)
;
typedef std::pair<APInt, APInt> SizeOffsetType;
/// \brief Evaluate the size and offset of an object ponted by a Value*
/// statically. Fails if size or offset are not known at compile time.
class ObjectSizeOffsetVisitor
: public InstVisitor<ObjectSizeOffsetVisitor, SizeOffsetType> {
const DataLayout *TD;
const TargetLibraryInfo *TLI;
bool RoundToAlign;
unsigned IntTyBits;
APInt Zero;
SmallPtrSet<Instruction *, 8> SeenInsts;
APInt align(APInt Size, uint64_t Align);
SizeOffsetType unknown() {
return std::make_pair(APInt(), APInt());
}
public:
ObjectSizeOffsetVisitor(const DataLayout *TD, const TargetLibraryInfo *TL
I,
LLVMContext &Context, bool RoundToAlign = false);
SizeOffsetType compute(Value *V);
bool knownSize(SizeOffsetType &SizeOffset) {
return SizeOffset.first.getBitWidth() > 1;
}
bool knownOffset(SizeOffsetType &SizeOffset) {
return SizeOffset.second.getBitWidth() > 1;
}
bool bothKnown(SizeOffsetType &SizeOffset) {
return knownSize(SizeOffset) && knownOffset(SizeOffset);
}
SizeOffsetType visitAllocaInst(AllocaInst &I);
SizeOffsetType visitArgument(Argument &A);
SizeOffsetType visitCallSite(CallSite CS);
SizeOffsetType visitConstantPointerNull(ConstantPointerNull&);
SizeOffsetType visitExtractElementInst(ExtractElementInst &I);
SizeOffsetType visitExtractValueInst(ExtractValueInst &I);
SizeOffsetType visitGEPOperator(GEPOperator &GEP);
SizeOffsetType visitGlobalVariable(GlobalVariable &GV);
SizeOffsetType visitIntToPtrInst(IntToPtrInst&);
SizeOffsetType visitLoadInst(LoadInst &I);
SizeOffsetType visitPHINode(PHINode&);
SizeOffsetType visitSelectInst(SelectInst &I);
SizeOffsetType visitUndefValue(UndefValue&);
SizeOffsetType visitInstruction(Instruction &I);
};
typedef std::pair<Value*, Value*> SizeOffsetEvalType;
/// \brief Evaluate the size and offset of an object ponted by a Value*.
/// May create code to compute the result at run-time.
class ObjectSizeOffsetEvaluator
: public InstVisitor<ObjectSizeOffsetEvaluator, SizeOffsetEvalType> {
typedef IRBuilder<true, TargetFolder> BuilderTy;
typedef std::pair<WeakVH, WeakVH> WeakEvalType;
typedef DenseMap<const Value*, WeakEvalType> CacheMapTy;
typedef SmallPtrSet<const Value*, 8> PtrSetTy;
const DataLayout *TD;
const TargetLibraryInfo *TLI;
LLVMContext &Context;
BuilderTy Builder;
IntegerType *IntTy;
Value *Zero;
CacheMapTy CacheMap;
PtrSetTy SeenVals;
SizeOffsetEvalType unknown() {
return std::make_pair((Value*)0, (Value*)0);
}
SizeOffsetEvalType compute_(Value *V);
public:
ObjectSizeOffsetEvaluator(const DataLayout *TD, const TargetLibraryInfo *
TLI,
LLVMContext &Context);
SizeOffsetEvalType compute(Value *V);
bool knownSize(SizeOffsetEvalType SizeOffset) {
return SizeOffset.first;
}
bool knownOffset(SizeOffsetEvalType SizeOffset) {
return SizeOffset.second;
}
bool anyKnown(SizeOffsetEvalType SizeOffset) {
return knownSize(SizeOffset) || knownOffset(SizeOffset);
}
bool bothKnown(SizeOffsetEvalType SizeOffset) {
return knownSize(SizeOffset) && knownOffset(SizeOffset);
}
SizeOffsetEvalType visitAllocaInst(AllocaInst &I);
SizeOffsetEvalType visitCallSite(CallSite CS);
SizeOffsetEvalType visitExtractElementInst(ExtractElementInst &I);
SizeOffsetEvalType visitExtractValueInst(ExtractValueInst &I);
SizeOffsetEvalType visitGEPOperator(GEPOperator &GEP);
SizeOffsetEvalType visitIntToPtrInst(IntToPtrInst&);
SizeOffsetEvalType visitLoadInst(LoadInst &I);
SizeOffsetEvalType visitPHINode(PHINode &PHI);
SizeOffsetEvalType visitSelectInst(SelectInst &I);
SizeOffsetEvalType visitInstruction(Instruction &I);
};
} // End llvm namespace } // End llvm namespace
#endif #endif
 End of changes. 13 change blocks. 
21 lines changed or deleted 206 lines changed or added


 MemoryDependenceAnalysis.h   MemoryDependenceAnalysis.h 
skipping to change at line 32 skipping to change at line 32
#include "llvm/ADT/SmallPtrSet.h" #include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/OwningPtr.h" #include "llvm/ADT/OwningPtr.h"
#include "llvm/ADT/PointerIntPair.h" #include "llvm/ADT/PointerIntPair.h"
namespace llvm { namespace llvm {
class Function; class Function;
class FunctionPass; class FunctionPass;
class Instruction; class Instruction;
class CallSite; class CallSite;
class AliasAnalysis; class AliasAnalysis;
class TargetData; class DataLayout;
class MemoryDependenceAnalysis; class MemoryDependenceAnalysis;
class PredIteratorCache; class PredIteratorCache;
class DominatorTree; class DominatorTree;
class PHITransAddr; class PHITransAddr;
/// MemDepResult - A memory dependence query can return one of three diff erent /// MemDepResult - A memory dependence query can return one of three diff erent
/// answers, described below. /// answers, described below.
class MemDepResult { class MemDepResult {
enum DepType { enum DepType {
/// Invalid - Clients of MemDep never see this. /// Invalid - Clients of MemDep never see this.
skipping to change at line 127 skipping to change at line 127
static MemDepResult getNonFuncLocal() { static MemDepResult getNonFuncLocal() {
return MemDepResult( return MemDepResult(
PairTy(reinterpret_cast<Instruction*>(NonFuncLocal), Other)); PairTy(reinterpret_cast<Instruction*>(NonFuncLocal), Other));
} }
static MemDepResult getUnknown() { static MemDepResult getUnknown() {
return MemDepResult( return MemDepResult(
PairTy(reinterpret_cast<Instruction*>(Unknown), Other)); PairTy(reinterpret_cast<Instruction*>(Unknown), Other));
} }
/// isClobber - Return true if this MemDepResult represents a query tha t is /// isClobber - Return true if this MemDepResult represents a query tha t is
/// a instruction clobber dependency. /// an instruction clobber dependency.
bool isClobber() const { return Value.getInt() == Clobber; } bool isClobber() const { return Value.getInt() == Clobber; }
/// isDef - Return true if this MemDepResult represents a query that is /// isDef - Return true if this MemDepResult represents a query that is
/// a instruction definition dependency. /// an instruction definition dependency.
bool isDef() const { return Value.getInt() == Def; } bool isDef() const { return Value.getInt() == Def; }
/// isNonLocal - Return true if this MemDepResult represents a query th at /// isNonLocal - Return true if this MemDepResult represents a query th at
/// is transparent to the start of the block, but where a non-local has n't /// is transparent to the start of the block, but where a non-local has n't
/// been done. /// been done.
bool isNonLocal() const { bool isNonLocal() const {
return Value.getInt() == Other return Value.getInt() == Other
&& Value.getPointer() == reinterpret_cast<Instruction*>(NonLocal); && Value.getPointer() == reinterpret_cast<Instruction*>(NonLocal);
} }
skipping to change at line 325 skipping to change at line 325
// used when removing instructions to keep the cache coherent. // used when removing instructions to keep the cache coherent.
typedef DenseMap<Instruction*, typedef DenseMap<Instruction*,
SmallPtrSet<Instruction*, 4> > ReverseDepMapType; SmallPtrSet<Instruction*, 4> > ReverseDepMapType;
ReverseDepMapType ReverseLocalDeps; ReverseDepMapType ReverseLocalDeps;
// A reverse mapping from dependencies to the non-local dependees. // A reverse mapping from dependencies to the non-local dependees.
ReverseDepMapType ReverseNonLocalDeps; ReverseDepMapType ReverseNonLocalDeps;
/// Current AA implementation, just a cache. /// Current AA implementation, just a cache.
AliasAnalysis *AA; AliasAnalysis *AA;
TargetData *TD; DataLayout *TD;
DominatorTree *DT; DominatorTree *DT;
OwningPtr<PredIteratorCache> PredCache; OwningPtr<PredIteratorCache> PredCache;
public: public:
MemoryDependenceAnalysis(); MemoryDependenceAnalysis();
~MemoryDependenceAnalysis(); ~MemoryDependenceAnalysis();
static char ID; static char ID;
/// Pass Implementation stuff. This doesn't do any analysis eagerly. /// Pass Implementation stuff. This doesn't do any analysis eagerly.
bool runOnFunction(Function &); bool runOnFunction(Function &);
skipping to change at line 412 skipping to change at line 412
/// looks at a memory location for a load (specified by MemLocBase, Off s, /// looks at a memory location for a load (specified by MemLocBase, Off s,
/// and Size) and compares it against a load. If the specified load co uld /// and Size) and compares it against a load. If the specified load co uld
/// be safely widened to a larger integer load that is 1) still efficie nt, /// be safely widened to a larger integer load that is 1) still efficie nt,
/// 2) safe for the target, and 3) would provide the specified memory /// 2) safe for the target, and 3) would provide the specified memory
/// location value, then this function returns the size in bytes of the /// location value, then this function returns the size in bytes of the
/// load width to use. If not, this returns zero. /// load width to use. If not, this returns zero.
static unsigned getLoadLoadClobberFullWidthSize(const Value *MemLocBase , static unsigned getLoadLoadClobberFullWidthSize(const Value *MemLocBase ,
int64_t MemLocOffs, int64_t MemLocOffs,
unsigned MemLocSize, unsigned MemLocSize,
const LoadInst *LI, const LoadInst *LI,
const TargetData &TD); const DataLayout &TD);
private: private:
MemDepResult getCallSiteDependencyFrom(CallSite C, bool isReadOnlyCall, MemDepResult getCallSiteDependencyFrom(CallSite C, bool isReadOnlyCall,
BasicBlock::iterator ScanIt, BasicBlock::iterator ScanIt,
BasicBlock *BB); BasicBlock *BB);
bool getNonLocalPointerDepFromBB(const PHITransAddr &Pointer, bool getNonLocalPointerDepFromBB(const PHITransAddr &Pointer,
const AliasAnalysis::Location &Loc, const AliasAnalysis::Location &Loc,
bool isLoad, BasicBlock *BB, bool isLoad, BasicBlock *BB,
SmallVectorImpl<NonLocalDepResult> &Re sult, SmallVectorImpl<NonLocalDepResult> &Re sult,
DenseMap<BasicBlock*, Value*> &Visited , DenseMap<BasicBlock*, Value*> &Visited ,
bool SkipFirstBlock = false); bool SkipFirstBlock = false);
MemDepResult GetNonLocalInfoForBlock(const AliasAnalysis::Location &Loc , MemDepResult GetNonLocalInfoForBlock(const AliasAnalysis::Location &Loc ,
bool isLoad, BasicBlock *BB, bool isLoad, BasicBlock *BB,
NonLocalDepInfo *Cache, NonLocalDepInfo *Cache,
unsigned NumSortedEntries); unsigned NumSortedEntries);
void RemoveCachedNonLocalPointerDependencies(ValueIsLoadPair P); void RemoveCachedNonLocalPointerDependencies(ValueIsLoadPair P);
AliasAnalysis::ModRefResult
getModRefInfo(const Instruction *Inst, const AliasAnalysis::Location &L
oc);
/// verifyRemoved - Verify that the specified instruction does not occu r /// verifyRemoved - Verify that the specified instruction does not occu r
/// in our internal data structures. /// in our internal data structures.
void verifyRemoved(Instruction *Inst) const; void verifyRemoved(Instruction *Inst) const;
}; };
} // End llvm namespace } // End llvm namespace
#endif #endif
 End of changes. 6 change blocks. 
9 lines changed or deleted 5 lines changed or added


 Metadata.h   Metadata.h 
skipping to change at line 39 skipping to change at line 39
template <typename T> class SmallVectorImpl; template <typename T> class SmallVectorImpl;
template<typename ValueSubClass, typename ItemParentClass> template<typename ValueSubClass, typename ItemParentClass>
class SymbolTableListTraits; class SymbolTableListTraits;
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
/// MDString - a single uniqued string. /// MDString - a single uniqued string.
/// These are used to efficiently contain a byte sequence for metadata. /// These are used to efficiently contain a byte sequence for metadata.
/// MDString is always unnamed. /// MDString is always unnamed.
class MDString : public Value { class MDString : public Value {
virtual void anchor(); virtual void anchor();
MDString(const MDString &); // DO NOT IMPLEMENT MDString(const MDString &) LLVM_DELETED_FUNCTION;
explicit MDString(LLVMContext &C); explicit MDString(LLVMContext &C);
public: public:
static MDString *get(LLVMContext &Context, StringRef Str); static MDString *get(LLVMContext &Context, StringRef Str);
static MDString *get(LLVMContext &Context, const char *Str) { static MDString *get(LLVMContext &Context, const char *Str) {
return get(Context, Str ? StringRef(Str) : StringRef()); return get(Context, Str ? StringRef(Str) : StringRef());
} }
StringRef getString() const { return getName(); } StringRef getString() const { return getName(); }
skipping to change at line 61 skipping to change at line 61
typedef StringRef::iterator iterator; typedef StringRef::iterator iterator;
/// begin() - Pointer to the first byte of the string. /// begin() - Pointer to the first byte of the string.
iterator begin() const { return getName().begin(); } iterator begin() const { return getName().begin(); }
/// end() - Pointer to one byte past the end of the string. /// end() - Pointer to one byte past the end of the string.
iterator end() const { return getName().end(); } iterator end() const { return getName().end(); }
/// Methods for support type inquiry through isa, cast, and dyn_cast: /// Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const MDString *) { return true; }
static bool classof(const Value *V) { static bool classof(const Value *V) {
return V->getValueID() == MDStringVal; return V->getValueID() == MDStringVal;
} }
}; };
class MDNodeOperand; class MDNodeOperand;
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
/// MDNode - a tuple of other values. /// MDNode - a tuple of other values.
class MDNode : public Value, public FoldingSetNode { class MDNode : public Value, public FoldingSetNode {
MDNode(const MDNode &); // DO NOT IMPLEMENT MDNode(const MDNode &) LLVM_DELETED_FUNCTION;
void operator=(const MDNode &); // DO NOT IMPLEMENT void operator=(const MDNode &) LLVM_DELETED_FUNCTION;
friend class MDNodeOperand; friend class MDNodeOperand;
friend class LLVMContextImpl; friend class LLVMContextImpl;
friend struct FoldingSetTrait<MDNode>; friend struct FoldingSetTrait<MDNode>;
/// Hash - If the MDNode is uniqued cache the hash to speed up lookup. /// Hash - If the MDNode is uniqued cache the hash to speed up lookup.
unsigned Hash; unsigned Hash;
/// NumOperands - This many 'MDNodeOperand' items are co-allocated onto t he /// NumOperands - This many 'MDNodeOperand' items are co-allocated onto t he
/// end of this MDNode. /// end of this MDNode.
unsigned NumOperands; unsigned NumOperands;
skipping to change at line 162 skipping to change at line 161
// function-local operand, return the first such operand's parent functio n. // function-local operand, return the first such operand's parent functio n.
// Otherwise, return null. getFunction() should not be used for performan ce- // Otherwise, return null. getFunction() should not be used for performan ce-
// critical code because it recursively visits all the MDNode's operands. // critical code because it recursively visits all the MDNode's operands.
const Function *getFunction() const; const Function *getFunction() const;
/// Profile - calculate a unique identifier for this MDNode to collapse /// Profile - calculate a unique identifier for this MDNode to collapse
/// duplicates /// duplicates
void Profile(FoldingSetNodeID &ID) const; void Profile(FoldingSetNodeID &ID) const;
/// Methods for support type inquiry through isa, cast, and dyn_cast: /// Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const MDNode *) { return true; }
static bool classof(const Value *V) { static bool classof(const Value *V) {
return V->getValueID() == MDNodeVal; return V->getValueID() == MDNodeVal;
} }
/// Methods for metadata merging.
static MDNode *getMostGenericTBAA(MDNode *A, MDNode *B);
static MDNode *getMostGenericFPMath(MDNode *A, MDNode *B);
static MDNode *getMostGenericRange(MDNode *A, MDNode *B);
private: private:
// destroy - Delete this node. Only when there are no uses. // destroy - Delete this node. Only when there are no uses.
void destroy(); void destroy();
bool isNotUniqued() const { bool isNotUniqued() const {
return (getSubclassDataFromValue() & NotUniquedBit) != 0; return (getSubclassDataFromValue() & NotUniquedBit) != 0;
} }
void setIsNotUniqued(); void setIsNotUniqued();
// Shadow Value::setValueSubclassData with a private forwarding method so that // Shadow Value::setValueSubclassData with a private forwarding method so that
skipping to change at line 191 skipping to change at line 194
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
/// NamedMDNode - a tuple of MDNodes. Despite its name, a NamedMDNode isn't /// NamedMDNode - a tuple of MDNodes. Despite its name, a NamedMDNode isn't
/// itself an MDNode. NamedMDNodes belong to modules, have names, and conta in /// itself an MDNode. NamedMDNodes belong to modules, have names, and conta in
/// lists of MDNodes. /// lists of MDNodes.
class NamedMDNode : public ilist_node<NamedMDNode> { class NamedMDNode : public ilist_node<NamedMDNode> {
friend class SymbolTableListTraits<NamedMDNode, Module>; friend class SymbolTableListTraits<NamedMDNode, Module>;
friend struct ilist_traits<NamedMDNode>; friend struct ilist_traits<NamedMDNode>;
friend class LLVMContextImpl; friend class LLVMContextImpl;
friend class Module; friend class Module;
NamedMDNode(const NamedMDNode &); // DO NOT IMPLEMENT NamedMDNode(const NamedMDNode &) LLVM_DELETED_FUNCTION;
std::string Name; std::string Name;
Module *Parent; Module *Parent;
void *Operands; // SmallVector<TrackingVH<MDNode>, 4> void *Operands; // SmallVector<TrackingVH<MDNode>, 4>
void setParent(Module *M) { Parent = M; } void setParent(Module *M) { Parent = M; }
explicit NamedMDNode(const Twine &N); explicit NamedMDNode(const Twine &N);
public: public:
 End of changes. 6 change blocks. 
6 lines changed or deleted 9 lines changed or added


 Module.h   Module.h 
skipping to change at line 303 skipping to change at line 303
/// This ID is uniqued across modules in the current LLVMContext. /// This ID is uniqued across modules in the current LLVMContext.
unsigned getMDKindID(StringRef Name) const; unsigned getMDKindID(StringRef Name) const;
/// getMDKindNames - Populate client supplied SmallVector with the name f or /// getMDKindNames - Populate client supplied SmallVector with the name f or
/// custom metadata IDs registered in this LLVMContext. /// custom metadata IDs registered in this LLVMContext.
void getMDKindNames(SmallVectorImpl<StringRef> &Result) const; void getMDKindNames(SmallVectorImpl<StringRef> &Result) const;
typedef DenseMap<StructType*, unsigned, DenseMapInfo<StructType*> > typedef DenseMap<StructType*, unsigned, DenseMapInfo<StructType*> >
NumeredTypesMapTy; NumeredTypesMapTy;
/// findUsedStructTypes - Walk the entire module and find all of the
/// struct types that are in use, returning them in a vector.
void findUsedStructTypes(std::vector<StructType*> &StructTypes) const;
/// getTypeByName - Return the type with the specified name, or null if t here /// getTypeByName - Return the type with the specified name, or null if t here
/// is none by that name. /// is none by that name.
StructType *getTypeByName(StringRef Name) const; StructType *getTypeByName(StringRef Name) const;
/// @} /// @}
/// @name Function Accessors /// @name Function Accessors
/// @{ /// @{
/// getOrInsertFunction - Look up the specified function in the module sy mbol /// getOrInsertFunction - Look up the specified function in the module sy mbol
/// table. Four possibilities: /// table. Four possibilities:
skipping to change at line 499 skipping to change at line 495
static iplist<Function> Module::*getSublistAccess(Function*) { static iplist<Function> Module::*getSublistAccess(Function*) {
return &Module::FunctionList; return &Module::FunctionList;
} }
/// Get the Module's list of aliases (constant). /// Get the Module's list of aliases (constant).
const AliasListType &getAliasList() const { return AliasList; } const AliasListType &getAliasList() const { return AliasList; }
/// Get the Module's list of aliases. /// Get the Module's list of aliases.
AliasListType &getAliasList() { return AliasList; } AliasListType &getAliasList() { return AliasList; }
static iplist<GlobalAlias> Module::*getSublistAccess(GlobalAlias*) { static iplist<GlobalAlias> Module::*getSublistAccess(GlobalAlias*) {
return &Module::AliasList; return &Module::AliasList;
} }
/// Get the Module's list of named metadata (constant).
const NamedMDListType &getNamedMDList() const { return NamedMDList;
}
/// Get the Module's list of named metadata.
NamedMDListType &getNamedMDList() { return NamedMDList;
}
static ilist<NamedMDNode> Module::*getSublistAccess(NamedMDNode*) {
return &Module::NamedMDList;
}
/// Get the symbol table of global variable and function identifiers /// Get the symbol table of global variable and function identifiers
const ValueSymbolTable &getValueSymbolTable() const { return *ValSymTab; } const ValueSymbolTable &getValueSymbolTable() const { return *ValSymTab; }
/// Get the Module's symbol table of global variable and function identif iers. /// Get the Module's symbol table of global variable and function identif iers.
ValueSymbolTable &getValueSymbolTable() { return *ValSymTab; } ValueSymbolTable &getValueSymbolTable() { return *ValSymTab; }
/// @} /// @}
/// @name Global Variable Iteration /// @name Global Variable Iteration
/// @{ /// @{
global_iterator global_begin() { return GlobalList.begin(); } global_iterator global_begin() { return GlobalList.begin(); }
 End of changes. 2 change blocks. 
4 lines changed or deleted 9 lines changed or added


 Mutex.h   Mutex.h 
skipping to change at line 17 skipping to change at line 17
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// //
// This file declares the llvm::sys::Mutex class. // This file declares the llvm::sys::Mutex class.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_SYSTEM_MUTEX_H #ifndef LLVM_SYSTEM_MUTEX_H
#define LLVM_SYSTEM_MUTEX_H #define LLVM_SYSTEM_MUTEX_H
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Threading.h" #include "llvm/Support/Threading.h"
#include <cassert> #include <cassert>
namespace llvm namespace llvm
{ {
namespace sys namespace sys
{ {
/// @brief Platform agnostic Mutex class. /// @brief Platform agnostic Mutex class.
class MutexImpl class MutexImpl
{ {
skipping to change at line 78 skipping to change at line 79
//@} //@}
/// @name Platform Dependent Data /// @name Platform Dependent Data
/// @{ /// @{
private: private:
void* data_; ///< We don't know what the data will be void* data_; ///< We don't know what the data will be
/// @} /// @}
/// @name Do Not Implement /// @name Do Not Implement
/// @{ /// @{
private: private:
MutexImpl(const MutexImpl & original); MutexImpl(const MutexImpl &) LLVM_DELETED_FUNCTION;
void operator=(const MutexImpl &); void operator=(const MutexImpl &) LLVM_DELETED_FUNCTION;
/// @} /// @}
}; };
/// SmartMutex - A mutex with a compile time constant parameter that /// SmartMutex - A mutex with a compile time constant parameter that
/// indicates whether this mutex should become a no-op when we're not /// indicates whether this mutex should become a no-op when we're not
/// running in multithreaded mode. /// running in multithreaded mode.
template<bool mt_only> template<bool mt_only>
class SmartMutex : public MutexImpl { class SmartMutex : public MutexImpl {
unsigned acquired; unsigned acquired;
bool recursive; bool recursive;
 End of changes. 2 change blocks. 
2 lines changed or deleted 3 lines changed or added


 MutexGuard.h   MutexGuard.h 
skipping to change at line 29 skipping to change at line 29
namespace llvm { namespace llvm {
/// Instances of this class acquire a given Mutex Lock when constructed a nd /// Instances of this class acquire a given Mutex Lock when constructed a nd
/// hold that lock until destruction. The intention is to instantiate one of /// hold that lock until destruction. The intention is to instantiate one of
/// these on the stack at the top of some scope to be assured that C++ /// these on the stack at the top of some scope to be assured that C++
/// destruction of the object will always release the Mutex and thus avoi d /// destruction of the object will always release the Mutex and thus avoi d
/// a host of nasty multi-threading problems in the face of exceptions, e tc. /// a host of nasty multi-threading problems in the face of exceptions, e tc.
/// @brief Guard a section of code with a Mutex. /// @brief Guard a section of code with a Mutex.
class MutexGuard { class MutexGuard {
sys::Mutex &M; sys::Mutex &M;
MutexGuard(const MutexGuard &); // DO NOT IMPLEMENT MutexGuard(const MutexGuard &) LLVM_DELETED_FUNCTION;
void operator=(const MutexGuard &); // DO NOT IMPLEMENT void operator=(const MutexGuard &) LLVM_DELETED_FUNCTION;
public: public:
MutexGuard(sys::Mutex &m) : M(m) { M.acquire(); } MutexGuard(sys::Mutex &m) : M(m) { M.acquire(); }
~MutexGuard() { M.release(); } ~MutexGuard() { M.release(); }
/// holds - Returns true if this locker instance holds the specified lo ck. /// holds - Returns true if this locker instance holds the specified lo ck.
/// This is mostly used in assertions to validate that the correct mute x /// This is mostly used in assertions to validate that the correct mute x
/// is held. /// is held.
bool holds(const sys::Mutex& lock) const { return &M == &lock; } bool holds(const sys::Mutex& lock) const { return &M == &lock; }
}; };
} }
 End of changes. 1 change blocks. 
2 lines changed or deleted 2 lines changed or added


 NoFolder.h   NoFolder.h 
skipping to change at line 184 skipping to change at line 184
} }
//===-------------------------------------------------------------------- ===// //===-------------------------------------------------------------------- ===//
// Memory Instructions // Memory Instructions
//===-------------------------------------------------------------------- ===// //===-------------------------------------------------------------------- ===//
Constant *CreateGetElementPtr(Constant *C, Constant *CreateGetElementPtr(Constant *C,
ArrayRef<Constant *> IdxList) const { ArrayRef<Constant *> IdxList) const {
return ConstantExpr::getGetElementPtr(C, IdxList); return ConstantExpr::getGetElementPtr(C, IdxList);
} }
Constant *CreateGetElementPtr(Constant *C, Constant *Idx) const {
// This form of the function only exists to avoid ambiguous overload
// warnings about whether to convert Idx to ArrayRef<Constant *> or
// ArrayRef<Value *>.
return ConstantExpr::getGetElementPtr(C, Idx);
}
Instruction *CreateGetElementPtr(Constant *C, Instruction *CreateGetElementPtr(Constant *C,
ArrayRef<Value *> IdxList) const { ArrayRef<Value *> IdxList) const {
return GetElementPtrInst::Create(C, IdxList); return GetElementPtrInst::Create(C, IdxList);
} }
Constant *CreateInBoundsGetElementPtr(Constant *C, Constant *CreateInBoundsGetElementPtr(Constant *C,
ArrayRef<Constant *> IdxList) const { ArrayRef<Constant *> IdxList) const {
return ConstantExpr::getInBoundsGetElementPtr(C, IdxList); return ConstantExpr::getInBoundsGetElementPtr(C, IdxList);
} }
Constant *CreateInBoundsGetElementPtr(Constant *C, Constant *Idx) const {
// This form of the function only exists to avoid ambiguous overload
// warnings about whether to convert Idx to ArrayRef<Constant *> or
// ArrayRef<Value *>.
return ConstantExpr::getInBoundsGetElementPtr(C, Idx);
}
Instruction *CreateInBoundsGetElementPtr(Constant *C, Instruction *CreateInBoundsGetElementPtr(Constant *C,
ArrayRef<Value *> IdxList) const { ArrayRef<Value *> IdxList) const {
return GetElementPtrInst::CreateInBounds(C, IdxList); return GetElementPtrInst::CreateInBounds(C, IdxList);
} }
//===-------------------------------------------------------------------- ===// //===-------------------------------------------------------------------- ===//
// Cast/Conversion Operators // Cast/Conversion Operators
//===-------------------------------------------------------------------- ===// //===-------------------------------------------------------------------- ===//
Instruction *CreateCast(Instruction::CastOps Op, Constant *C, Instruction *CreateCast(Instruction::CastOps Op, Constant *C,
 End of changes. 2 change blocks. 
0 lines changed or deleted 12 lines changed or added


 ObjectFile.h   ObjectFile.h 
skipping to change at line 79 skipping to change at line 79
content_iterator& increment(error_code &err) { content_iterator& increment(error_code &err) {
content_type next; content_type next;
if (error_code ec = Current.getNext(next)) if (error_code ec = Current.getNext(next))
err = ec; err = ec;
else else
Current = next; Current = next;
return *this; return *this;
} }
}; };
static bool operator ==(const DataRefImpl &a, const DataRefImpl &b) { inline bool operator==(const DataRefImpl &a, const DataRefImpl &b) {
// Check bitwise identical. This is the only legal way to compare a union w/o // Check bitwise identical. This is the only legal way to compare a union w/o
// knowing which member is in use. // knowing which member is in use.
return std::memcmp(&a, &b, sizeof(DataRefImpl)) == 0; return std::memcmp(&a, &b, sizeof(DataRefImpl)) == 0;
} }
static bool operator <(const DataRefImpl &a, const DataRefImpl &b) { inline bool operator<(const DataRefImpl &a, const DataRefImpl &b) {
// Check bitwise identical. This is the only legal way to compare a union w/o // Check bitwise identical. This is the only legal way to compare a union w/o
// knowing which member is in use. // knowing which member is in use.
return std::memcmp(&a, &b, sizeof(DataRefImpl)) < 0; return std::memcmp(&a, &b, sizeof(DataRefImpl)) < 0;
} }
class SymbolRef; class SymbolRef;
/// RelocationRef - This is a value type class that represents a single /// RelocationRef - This is a value type class that represents a single
/// relocation in the list of relocations in the object file. /// relocation in the list of relocations in the object file.
class RelocationRef { class RelocationRef {
skipping to change at line 129 skipping to change at line 129
/// ///
/// This is for display purposes only. /// This is for display purposes only.
error_code getTypeName(SmallVectorImpl<char> &Result) const; error_code getTypeName(SmallVectorImpl<char> &Result) const;
error_code getAdditionalInfo(int64_t &Result) const; error_code getAdditionalInfo(int64_t &Result) const;
/// @brief Get a string that represents the calculation of the value of t his /// @brief Get a string that represents the calculation of the value of t his
/// relocation. /// relocation.
/// ///
/// This is for display purposes only. /// This is for display purposes only.
error_code getValueString(SmallVectorImpl<char> &Result) const; error_code getValueString(SmallVectorImpl<char> &Result) const;
DataRefImpl getRawDataRefImpl() const;
}; };
typedef content_iterator<RelocationRef> relocation_iterator; typedef content_iterator<RelocationRef> relocation_iterator;
/// SectionRef - This is a value type class that represents a single sectio n in /// SectionRef - This is a value type class that represents a single sectio n in
/// the list of sections in the object file. /// the list of sections in the object file.
class SectionRef { class SectionRef {
friend class SymbolRef; friend class SymbolRef;
DataRefImpl SectionPimpl; DataRefImpl SectionPimpl;
const ObjectFile *OwningObject; const ObjectFile *OwningObject;
public: public:
SectionRef() : OwningObject(NULL) { } SectionRef() : OwningObject(NULL) { }
SectionRef(DataRefImpl SectionP, const ObjectFile *Owner); SectionRef(DataRefImpl SectionP, const ObjectFile *Owner);
bool operator==(const SectionRef &Other) const; bool operator==(const SectionRef &Other) const;
bool operator <(const SectionRef &Other) const; bool operator<(const SectionRef &Other) const;
error_code getNext(SectionRef &Result) const; error_code getNext(SectionRef &Result) const;
error_code getName(StringRef &Result) const; error_code getName(StringRef &Result) const;
error_code getAddress(uint64_t &Result) const; error_code getAddress(uint64_t &Result) const;
error_code getSize(uint64_t &Result) const; error_code getSize(uint64_t &Result) const;
error_code getContents(StringRef &Result) const; error_code getContents(StringRef &Result) const;
/// @brief Get the alignment of this section as the actual value (not log 2). /// @brief Get the alignment of this section as the actual value (not log 2).
error_code getAlignment(uint64_t &Result) const; error_code getAlignment(uint64_t &Result) const;
// FIXME: Move to the normalization layer when it's created. // FIXME: Move to the normalization layer when it's created.
error_code isText(bool &Result) const; error_code isText(bool &Result) const;
error_code isData(bool &Result) const; error_code isData(bool &Result) const;
error_code isBSS(bool &Result) const; error_code isBSS(bool &Result) const;
error_code isRequiredForExecution(bool &Result) const; error_code isRequiredForExecution(bool &Result) const;
error_code isVirtual(bool &Result) const; error_code isVirtual(bool &Result) const;
error_code isZeroInit(bool &Result) const; error_code isZeroInit(bool &Result) const;
error_code isReadOnlyData(bool &Result) const;
error_code containsSymbol(SymbolRef S, bool &Result) const; error_code containsSymbol(SymbolRef S, bool &Result) const;
relocation_iterator begin_relocations() const; relocation_iterator begin_relocations() const;
relocation_iterator end_relocations() const; relocation_iterator end_relocations() const;
DataRefImpl getRawDataRefImpl() const; DataRefImpl getRawDataRefImpl() const;
}; };
typedef content_iterator<SectionRef> section_iterator; typedef content_iterator<SectionRef> section_iterator;
skipping to change at line 208 skipping to change at line 211
SF_Absolute = 1U << 3, // Absolute symbol SF_Absolute = 1U << 3, // Absolute symbol
SF_ThreadLocal = 1U << 4, // Thread local symbol SF_ThreadLocal = 1U << 4, // Thread local symbol
SF_Common = 1U << 5, // Symbol has common linkage SF_Common = 1U << 5, // Symbol has common linkage
SF_FormatSpecific = 1U << 31 // Specific to the object file format SF_FormatSpecific = 1U << 31 // Specific to the object file format
// (e.g. section symbols) // (e.g. section symbols)
}; };
SymbolRef(DataRefImpl SymbolP, const ObjectFile *Owner); SymbolRef(DataRefImpl SymbolP, const ObjectFile *Owner);
bool operator==(const SymbolRef &Other) const; bool operator==(const SymbolRef &Other) const;
bool operator <(const SymbolRef &Other) const; bool operator<(const SymbolRef &Other) const;
error_code getNext(SymbolRef &Result) const; error_code getNext(SymbolRef &Result) const;
error_code getName(StringRef &Result) const; error_code getName(StringRef &Result) const;
/// Returns the symbol virtual address (i.e. address at which it will be
/// mapped).
error_code getAddress(uint64_t &Result) const; error_code getAddress(uint64_t &Result) const;
error_code getFileOffset(uint64_t &Result) const; error_code getFileOffset(uint64_t &Result) const;
error_code getSize(uint64_t &Result) const; error_code getSize(uint64_t &Result) const;
error_code getType(SymbolRef::Type &Result) const; error_code getType(SymbolRef::Type &Result) const;
/// Returns the ascii char that should be displayed in a symbol table dum p via /// Returns the ascii char that should be displayed in a symbol table dum p via
/// nm for this symbol. /// nm for this symbol.
error_code getNMTypeChar(char &Result) const; error_code getNMTypeChar(char &Result) const;
/// Get symbol flags (bitwise OR of SymbolRef::Flags) /// Get symbol flags (bitwise OR of SymbolRef::Flags)
error_code getFlags(uint32_t &Result) const; error_code getFlags(uint32_t &Result) const;
/// @brief Return true for common symbols such as uninitialized globals /// @brief Return true for common symbols such as uninitialized globals
error_code isCommon(bool &Result) const; error_code isCommon(bool &Result) const;
/// @brief Get section this symbol is defined in reference to. Result is /// @brief Get section this symbol is defined in reference to. Result is
/// end_sections() if it is undefined or is an absolute symbol. /// end_sections() if it is undefined or is an absolute symbol.
error_code getSection(section_iterator &Result) const; error_code getSection(section_iterator &Result) const;
/// @brief Get value of the symbol in the symbol table.
error_code getValue(uint64_t &Val) const;
DataRefImpl getRawDataRefImpl() const; DataRefImpl getRawDataRefImpl() const;
}; };
typedef content_iterator<SymbolRef> symbol_iterator; typedef content_iterator<SymbolRef> symbol_iterator;
/// LibraryRef - This is a value type class that represents a single librar y in /// LibraryRef - This is a value type class that represents a single librar y in
/// the list of libraries needed by a shared or dynamic object. /// the list of libraries needed by a shared or dynamic object.
class LibraryRef { class LibraryRef {
friend class SectionRef; friend class SectionRef;
DataRefImpl LibraryPimpl; DataRefImpl LibraryPimpl;
const ObjectFile *OwningObject; const ObjectFile *OwningObject;
public: public:
LibraryRef() : OwningObject(NULL) { } LibraryRef() : OwningObject(NULL) { }
LibraryRef(DataRefImpl LibraryP, const ObjectFile *Owner); LibraryRef(DataRefImpl LibraryP, const ObjectFile *Owner);
bool operator==(const LibraryRef &Other) const; bool operator==(const LibraryRef &Other) const;
bool operator <(const LibraryRef &Other) const; bool operator<(const LibraryRef &Other) const;
error_code getNext(LibraryRef &Result) const; error_code getNext(LibraryRef &Result) const;
// Get the path to this library, as stored in the object file. // Get the path to this library, as stored in the object file.
error_code getPath(StringRef &Result) const; error_code getPath(StringRef &Result) const;
DataRefImpl getRawDataRefImpl() const; DataRefImpl getRawDataRefImpl() const;
}; };
typedef content_iterator<LibraryRef> library_iterator; typedef content_iterator<LibraryRef> library_iterator;
const uint64_t UnknownAddressOrSize = ~0ULL; const uint64_t UnknownAddressOrSize = ~0ULL;
/// ObjectFile - This class is the base class for all object file types. /// ObjectFile - This class is the base class for all object file types.
/// Concrete instances of this object are created by createObjectFile, whic h /// Concrete instances of this object are created by createObjectFile, whic h
/// figure out which type to create. /// figures out which type to create.
class ObjectFile : public Binary { class ObjectFile : public Binary {
virtual void anchor(); virtual void anchor();
ObjectFile(); // = delete ObjectFile() LLVM_DELETED_FUNCTION;
ObjectFile(const ObjectFile &other); // = delete ObjectFile(const ObjectFile &other) LLVM_DELETED_FUNCTION;
protected: protected:
ObjectFile(unsigned int Type, MemoryBuffer *source, error_code &ec); ObjectFile(unsigned int Type, MemoryBuffer *source, error_code &ec);
const uint8_t *base() const { const uint8_t *base() const {
return reinterpret_cast<const uint8_t *>(Data->getBufferStart()); return reinterpret_cast<const uint8_t *>(Data->getBufferStart());
} }
// These functions are for SymbolRef to call internally. The main goal of // These functions are for SymbolRef to call internally. The main goal of
// this is to allow SymbolRef::SymbolPimpl to point directly to the symbo l // this is to allow SymbolRef::SymbolPimpl to point directly to the symbo l
// entry in the memory mapped object file. SymbolPimpl cannot contain any // entry in the memory mapped object file. SymbolPimpl cannot contain any
// virtual functions because then it could not point into the memory mapp ed // virtual functions because then it could not point into the memory mapp ed
// file. // file.
// //
// Implementations assume that the DataRefImpl is valid and has not been // Implementations assume that the DataRefImpl is valid and has not been
// modified externally. It's UB otherwise. // modified externally. It's UB otherwise.
friend class SymbolRef; friend class SymbolRef;
virtual error_code getSymbolNext(DataRefImpl Symb, SymbolRef &Res) const = 0; virtual error_code getSymbolNext(DataRefImpl Symb, SymbolRef &Res) const = 0;
virtual error_code getSymbolName(DataRefImpl Symb, StringRef &Res) const = 0; virtual error_code getSymbolName(DataRefImpl Symb, StringRef &Res) const = 0;
virtual error_code getSymbolAddress(DataRefImpl Symb, uint64_t &Res) cons virtual error_code getSymbolAddress(DataRefImpl Symb, uint64_t &Res) cons
t =0; t = 0;
virtual error_code getSymbolFileOffset(DataRefImpl Symb, uint64_t &Res) c virtual error_code getSymbolFileOffset(DataRefImpl Symb, uint64_t &Res)co
onst =0; nst=0;
virtual error_code getSymbolSize(DataRefImpl Symb, uint64_t &Res) const = 0; virtual error_code getSymbolSize(DataRefImpl Symb, uint64_t &Res) const = 0;
virtual error_code getSymbolType(DataRefImpl Symb, virtual error_code getSymbolType(DataRefImpl Symb,
SymbolRef::Type &Res) const = 0; SymbolRef::Type &Res) const = 0;
virtual error_code getSymbolNMTypeChar(DataRefImpl Symb, char &Res) const = 0; virtual error_code getSymbolNMTypeChar(DataRefImpl Symb, char &Res) const = 0;
virtual error_code getSymbolFlags(DataRefImpl Symb, virtual error_code getSymbolFlags(DataRefImpl Symb,
uint32_t &Res) const = 0; uint32_t &Res) const = 0;
virtual error_code getSymbolSection(DataRefImpl Symb, virtual error_code getSymbolSection(DataRefImpl Symb,
section_iterator &Res) const = 0; section_iterator &Res) const = 0;
virtual error_code getSymbolValue(DataRefImpl Symb, uint64_t &Val) const = 0;
// Same as above for SectionRef. // Same as above for SectionRef.
friend class SectionRef; friend class SectionRef;
virtual error_code getSectionNext(DataRefImpl Sec, SectionRef &Res) const = 0; virtual error_code getSectionNext(DataRefImpl Sec, SectionRef &Res) const = 0;
virtual error_code getSectionName(DataRefImpl Sec, StringRef &Res) const = 0; virtual error_code getSectionName(DataRefImpl Sec, StringRef &Res) const = 0;
virtual error_code getSectionAddress(DataRefImpl Sec, uint64_t &Res) cons t =0; virtual error_code getSectionAddress(DataRefImpl Sec, uint64_t &Res) cons t =0;
virtual error_code getSectionSize(DataRefImpl Sec, uint64_t &Res) const = 0; virtual error_code getSectionSize(DataRefImpl Sec, uint64_t &Res) const = 0;
virtual error_code getSectionContents(DataRefImpl Sec, StringRef &Res)con st=0; virtual error_code getSectionContents(DataRefImpl Sec, StringRef &Res)con st=0;
virtual error_code getSectionAlignment(DataRefImpl Sec, uint64_t &Res)con st=0; virtual error_code getSectionAlignment(DataRefImpl Sec, uint64_t &Res)con st=0;
virtual error_code isSectionText(DataRefImpl Sec, bool &Res) const = 0; virtual error_code isSectionText(DataRefImpl Sec, bool &Res) const = 0;
virtual error_code isSectionData(DataRefImpl Sec, bool &Res) const = 0; virtual error_code isSectionData(DataRefImpl Sec, bool &Res) const = 0;
virtual error_code isSectionBSS(DataRefImpl Sec, bool &Res) const = 0; virtual error_code isSectionBSS(DataRefImpl Sec, bool &Res) const = 0;
virtual error_code isSectionRequiredForExecution(DataRefImpl Sec, virtual error_code isSectionRequiredForExecution(DataRefImpl Sec,
bool &Res) const = 0; bool &Res) const = 0;
// A section is 'virtual' if its contents aren't present in the object im age. // A section is 'virtual' if its contents aren't present in the object im age.
virtual error_code isSectionVirtual(DataRefImpl Sec, bool &Res) const = 0 ; virtual error_code isSectionVirtual(DataRefImpl Sec, bool &Res) const = 0 ;
virtual error_code isSectionZeroInit(DataRefImpl Sec, bool &Res) const = 0; virtual error_code isSectionZeroInit(DataRefImpl Sec, bool &Res) const = 0;
virtual error_code isSectionReadOnlyData(DataRefImpl Sec, bool &Res) cons t =0;
virtual error_code sectionContainsSymbol(DataRefImpl Sec, DataRefImpl Sym b, virtual error_code sectionContainsSymbol(DataRefImpl Sec, DataRefImpl Sym b,
bool &Result) const = 0; bool &Result) const = 0;
virtual relocation_iterator getSectionRelBegin(DataRefImpl Sec) const = 0 ; virtual relocation_iterator getSectionRelBegin(DataRefImpl Sec) const = 0 ;
virtual relocation_iterator getSectionRelEnd(DataRefImpl Sec) const = 0; virtual relocation_iterator getSectionRelEnd(DataRefImpl Sec) const = 0;
// Same as above for RelocationRef. // Same as above for RelocationRef.
friend class RelocationRef; friend class RelocationRef;
virtual error_code getRelocationNext(DataRefImpl Rel, virtual error_code getRelocationNext(DataRefImpl Rel,
RelocationRef &Res) const = 0; RelocationRef &Res) const = 0;
virtual error_code getRelocationAddress(DataRefImpl Rel, virtual error_code getRelocationAddress(DataRefImpl Rel,
skipping to change at line 384 skipping to change at line 394
/// @returns Pointer to ObjectFile subclass to handle this type of object . /// @returns Pointer to ObjectFile subclass to handle this type of object .
/// @param ObjectPath The path to the object file. ObjectPath.isObject mu st /// @param ObjectPath The path to the object file. ObjectPath.isObject mu st
/// return true. /// return true.
/// @brief Create ObjectFile from path. /// @brief Create ObjectFile from path.
static ObjectFile *createObjectFile(StringRef ObjectPath); static ObjectFile *createObjectFile(StringRef ObjectPath);
static ObjectFile *createObjectFile(MemoryBuffer *Object); static ObjectFile *createObjectFile(MemoryBuffer *Object);
static inline bool classof(const Binary *v) { static inline bool classof(const Binary *v) {
return v->isObject(); return v->isObject();
} }
static inline bool classof(const ObjectFile *v) { return true; }
public: public:
static ObjectFile *createCOFFObjectFile(MemoryBuffer *Object); static ObjectFile *createCOFFObjectFile(MemoryBuffer *Object);
static ObjectFile *createELFObjectFile(MemoryBuffer *Object); static ObjectFile *createELFObjectFile(MemoryBuffer *Object);
static ObjectFile *createMachOObjectFile(MemoryBuffer *Object); static ObjectFile *createMachOObjectFile(MemoryBuffer *Object);
}; };
// Inline function definitions. // Inline function definitions.
inline SymbolRef::SymbolRef(DataRefImpl SymbolP, const ObjectFile *Owner) inline SymbolRef::SymbolRef(DataRefImpl SymbolP, const ObjectFile *Owner)
: SymbolPimpl(SymbolP) : SymbolPimpl(SymbolP)
, OwningObject(Owner) {} , OwningObject(Owner) {}
inline bool SymbolRef::operator==(const SymbolRef &Other) const { inline bool SymbolRef::operator==(const SymbolRef &Other) const {
return SymbolPimpl == Other.SymbolPimpl; return SymbolPimpl == Other.SymbolPimpl;
} }
inline bool SymbolRef::operator <(const SymbolRef &Other) const { inline bool SymbolRef::operator<(const SymbolRef &Other) const {
return SymbolPimpl < Other.SymbolPimpl; return SymbolPimpl < Other.SymbolPimpl;
} }
inline error_code SymbolRef::getNext(SymbolRef &Result) const { inline error_code SymbolRef::getNext(SymbolRef &Result) const {
return OwningObject->getSymbolNext(SymbolPimpl, Result); return OwningObject->getSymbolNext(SymbolPimpl, Result);
} }
inline error_code SymbolRef::getName(StringRef &Result) const { inline error_code SymbolRef::getName(StringRef &Result) const {
return OwningObject->getSymbolName(SymbolPimpl, Result); return OwningObject->getSymbolName(SymbolPimpl, Result);
} }
skipping to change at line 441 skipping to change at line 450
} }
inline error_code SymbolRef::getSection(section_iterator &Result) const { inline error_code SymbolRef::getSection(section_iterator &Result) const {
return OwningObject->getSymbolSection(SymbolPimpl, Result); return OwningObject->getSymbolSection(SymbolPimpl, Result);
} }
inline error_code SymbolRef::getType(SymbolRef::Type &Result) const { inline error_code SymbolRef::getType(SymbolRef::Type &Result) const {
return OwningObject->getSymbolType(SymbolPimpl, Result); return OwningObject->getSymbolType(SymbolPimpl, Result);
} }
inline error_code SymbolRef::getValue(uint64_t &Val) const {
return OwningObject->getSymbolValue(SymbolPimpl, Val);
}
inline DataRefImpl SymbolRef::getRawDataRefImpl() const { inline DataRefImpl SymbolRef::getRawDataRefImpl() const {
return SymbolPimpl; return SymbolPimpl;
} }
/// SectionRef /// SectionRef
inline SectionRef::SectionRef(DataRefImpl SectionP, inline SectionRef::SectionRef(DataRefImpl SectionP,
const ObjectFile *Owner) const ObjectFile *Owner)
: SectionPimpl(SectionP) : SectionPimpl(SectionP)
, OwningObject(Owner) {} , OwningObject(Owner) {}
inline bool SectionRef::operator==(const SectionRef &Other) const { inline bool SectionRef::operator==(const SectionRef &Other) const {
return SectionPimpl == Other.SectionPimpl; return SectionPimpl == Other.SectionPimpl;
} }
inline bool SectionRef::operator <(const SectionRef &Other) const { inline bool SectionRef::operator<(const SectionRef &Other) const {
return SectionPimpl < Other.SectionPimpl; return SectionPimpl < Other.SectionPimpl;
} }
inline error_code SectionRef::getNext(SectionRef &Result) const { inline error_code SectionRef::getNext(SectionRef &Result) const {
return OwningObject->getSectionNext(SectionPimpl, Result); return OwningObject->getSectionNext(SectionPimpl, Result);
} }
inline error_code SectionRef::getName(StringRef &Result) const { inline error_code SectionRef::getName(StringRef &Result) const {
return OwningObject->getSectionName(SectionPimpl, Result); return OwningObject->getSectionName(SectionPimpl, Result);
} }
skipping to change at line 507 skipping to change at line 520
} }
inline error_code SectionRef::isVirtual(bool &Result) const { inline error_code SectionRef::isVirtual(bool &Result) const {
return OwningObject->isSectionVirtual(SectionPimpl, Result); return OwningObject->isSectionVirtual(SectionPimpl, Result);
} }
inline error_code SectionRef::isZeroInit(bool &Result) const { inline error_code SectionRef::isZeroInit(bool &Result) const {
return OwningObject->isSectionZeroInit(SectionPimpl, Result); return OwningObject->isSectionZeroInit(SectionPimpl, Result);
} }
inline error_code SectionRef::isReadOnlyData(bool &Result) const {
return OwningObject->isSectionReadOnlyData(SectionPimpl, Result);
}
inline error_code SectionRef::containsSymbol(SymbolRef S, bool &Result) con st { inline error_code SectionRef::containsSymbol(SymbolRef S, bool &Result) con st {
return OwningObject->sectionContainsSymbol(SectionPimpl, S.SymbolPimpl, return OwningObject->sectionContainsSymbol(SectionPimpl, S.SymbolPimpl,
Result); Result);
} }
inline relocation_iterator SectionRef::begin_relocations() const { inline relocation_iterator SectionRef::begin_relocations() const {
return OwningObject->getSectionRelBegin(SectionPimpl); return OwningObject->getSectionRelBegin(SectionPimpl);
} }
inline relocation_iterator SectionRef::end_relocations() const { inline relocation_iterator SectionRef::end_relocations() const {
skipping to change at line 571 skipping to change at line 588
} }
inline error_code RelocationRef::getValueString(SmallVectorImpl<char> &Resu lt) inline error_code RelocationRef::getValueString(SmallVectorImpl<char> &Resu lt)
const { const {
return OwningObject->getRelocationValueString(RelocationPimpl, Result); return OwningObject->getRelocationValueString(RelocationPimpl, Result);
} }
inline error_code RelocationRef::getHidden(bool &Result) const { inline error_code RelocationRef::getHidden(bool &Result) const {
return OwningObject->getRelocationHidden(RelocationPimpl, Result); return OwningObject->getRelocationHidden(RelocationPimpl, Result);
} }
inline DataRefImpl RelocationRef::getRawDataRefImpl() const {
return RelocationPimpl;
}
// Inline function definitions. // Inline function definitions.
inline LibraryRef::LibraryRef(DataRefImpl LibraryP, const ObjectFile *Owner ) inline LibraryRef::LibraryRef(DataRefImpl LibraryP, const ObjectFile *Owner )
: LibraryPimpl(LibraryP) : LibraryPimpl(LibraryP)
, OwningObject(Owner) {} , OwningObject(Owner) {}
inline bool LibraryRef::operator==(const LibraryRef &Other) const { inline bool LibraryRef::operator==(const LibraryRef &Other) const {
return LibraryPimpl == Other.LibraryPimpl; return LibraryPimpl == Other.LibraryPimpl;
} }
inline bool LibraryRef::operator <(const LibraryRef &Other) const { inline bool LibraryRef::operator<(const LibraryRef &Other) const {
return LibraryPimpl < Other.LibraryPimpl; return LibraryPimpl < Other.LibraryPimpl;
} }
inline error_code LibraryRef::getNext(LibraryRef &Result) const { inline error_code LibraryRef::getNext(LibraryRef &Result) const {
return OwningObject->getLibraryNext(LibraryPimpl, Result); return OwningObject->getLibraryNext(LibraryPimpl, Result);
} }
inline error_code LibraryRef::getPath(StringRef &Result) const { inline error_code LibraryRef::getPath(StringRef &Result) const {
return OwningObject->getLibraryPath(LibraryPimpl, Result); return OwningObject->getLibraryPath(LibraryPimpl, Result);
} }
 End of changes. 21 change blocks. 
16 lines changed or deleted 38 lines changed or added


 Operator.h   Operator.h 
skipping to change at line 19 skipping to change at line 19
// //
// This file defines various classes for working with Instructions and // This file defines various classes for working with Instructions and
// ConstantExprs. // ConstantExprs.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_OPERATOR_H #ifndef LLVM_OPERATOR_H
#define LLVM_OPERATOR_H #define LLVM_OPERATOR_H
#include "llvm/Constants.h" #include "llvm/Constants.h"
#include "llvm/DerivedTypes.h"
#include "llvm/Instruction.h" #include "llvm/Instruction.h"
#include "llvm/Type.h" #include "llvm/Type.h"
namespace llvm { namespace llvm {
class GetElementPtrInst; class GetElementPtrInst;
class BinaryOperator; class BinaryOperator;
class ConstantExpr; class ConstantExpr;
/// Operator - This is a utility class that provides an abstraction for the /// Operator - This is a utility class that provides an abstraction for the
/// common functionality between Instructions and ConstantExprs. /// common functionality between Instructions and ConstantExprs.
/// ///
class Operator : public User { class Operator : public User {
private: private:
// Do not implement any of these. The Operator class is intended to be us ed // Do not implement any of these. The Operator class is intended to be us ed
// as a utility, and is never itself instantiated. // as a utility, and is never itself instantiated.
void *operator new(size_t, unsigned); void *operator new(size_t, unsigned) LLVM_DELETED_FUNCTION;
void *operator new(size_t s); void *operator new(size_t s) LLVM_DELETED_FUNCTION;
Operator(); Operator() LLVM_DELETED_FUNCTION;
protected:
// NOTE: Cannot use LLVM_DELETED_FUNCTION because it's not legal to delet
e
// an overridden method that's not deleted in the base class. Cannot leav
e
// this unimplemented because that leads to an ODR-violation.
~Operator(); ~Operator();
public: public:
/// getOpcode - Return the opcode for this Instruction or ConstantExpr. /// getOpcode - Return the opcode for this Instruction or ConstantExpr.
/// ///
unsigned getOpcode() const { unsigned getOpcode() const {
if (const Instruction *I = dyn_cast<Instruction>(this)) if (const Instruction *I = dyn_cast<Instruction>(this))
return I->getOpcode(); return I->getOpcode();
return cast<ConstantExpr>(this)->getOpcode(); return cast<ConstantExpr>(this)->getOpcode();
} }
skipping to change at line 60 skipping to change at line 66
/// opcode. Otherwise return UserOp1. /// opcode. Otherwise return UserOp1.
/// ///
static unsigned getOpcode(const Value *V) { static unsigned getOpcode(const Value *V) {
if (const Instruction *I = dyn_cast<Instruction>(V)) if (const Instruction *I = dyn_cast<Instruction>(V))
return I->getOpcode(); return I->getOpcode();
if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(V)) if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(V))
return CE->getOpcode(); return CE->getOpcode();
return Instruction::UserOp1; return Instruction::UserOp1;
} }
static inline bool classof(const Operator *) { return true; }
static inline bool classof(const Instruction *) { return true; } static inline bool classof(const Instruction *) { return true; }
static inline bool classof(const ConstantExpr *) { return true; } static inline bool classof(const ConstantExpr *) { return true; }
static inline bool classof(const Value *V) { static inline bool classof(const Value *V) {
return isa<Instruction>(V) || isa<ConstantExpr>(V); return isa<Instruction>(V) || isa<ConstantExpr>(V);
} }
}; };
/// OverflowingBinaryOperator - Utility class for integer arithmetic operat ors /// OverflowingBinaryOperator - Utility class for integer arithmetic operat ors
/// which may exhibit overflow - Add, Sub, and Mul. It does not include SDi v, /// which may exhibit overflow - Add, Sub, and Mul. It does not include SDi v,
/// despite that operator having the potential for overflow. /// despite that operator having the potential for overflow.
/// ///
class OverflowingBinaryOperator : public Operator { class OverflowingBinaryOperator : public Operator {
public: public:
enum { enum {
NoUnsignedWrap = (1 << 0), NoUnsignedWrap = (1 << 0),
NoSignedWrap = (1 << 1) NoSignedWrap = (1 << 1)
}; };
private: private:
~OverflowingBinaryOperator(); // do not implement
friend class BinaryOperator; friend class BinaryOperator;
friend class ConstantExpr; friend class ConstantExpr;
void setHasNoUnsignedWrap(bool B) { void setHasNoUnsignedWrap(bool B) {
SubclassOptionalData = SubclassOptionalData =
(SubclassOptionalData & ~NoUnsignedWrap) | (B * NoUnsignedWrap); (SubclassOptionalData & ~NoUnsignedWrap) | (B * NoUnsignedWrap);
} }
void setHasNoSignedWrap(bool B) { void setHasNoSignedWrap(bool B) {
SubclassOptionalData = SubclassOptionalData =
(SubclassOptionalData & ~NoSignedWrap) | (B * NoSignedWrap); (SubclassOptionalData & ~NoSignedWrap) | (B * NoSignedWrap);
} }
skipping to change at line 106 skipping to change at line 109
bool hasNoUnsignedWrap() const { bool hasNoUnsignedWrap() const {
return SubclassOptionalData & NoUnsignedWrap; return SubclassOptionalData & NoUnsignedWrap;
} }
/// hasNoSignedWrap - Test whether this operation is known to never /// hasNoSignedWrap - Test whether this operation is known to never
/// undergo signed overflow, aka the nsw property. /// undergo signed overflow, aka the nsw property.
bool hasNoSignedWrap() const { bool hasNoSignedWrap() const {
return (SubclassOptionalData & NoSignedWrap) != 0; return (SubclassOptionalData & NoSignedWrap) != 0;
} }
static inline bool classof(const OverflowingBinaryOperator *) { return tr ue; }
static inline bool classof(const Instruction *I) { static inline bool classof(const Instruction *I) {
return I->getOpcode() == Instruction::Add || return I->getOpcode() == Instruction::Add ||
I->getOpcode() == Instruction::Sub || I->getOpcode() == Instruction::Sub ||
I->getOpcode() == Instruction::Mul || I->getOpcode() == Instruction::Mul ||
I->getOpcode() == Instruction::Shl; I->getOpcode() == Instruction::Shl;
} }
static inline bool classof(const ConstantExpr *CE) { static inline bool classof(const ConstantExpr *CE) {
return CE->getOpcode() == Instruction::Add || return CE->getOpcode() == Instruction::Add ||
CE->getOpcode() == Instruction::Sub || CE->getOpcode() == Instruction::Sub ||
CE->getOpcode() == Instruction::Mul || CE->getOpcode() == Instruction::Mul ||
skipping to change at line 134 skipping to change at line 136
/// PossiblyExactOperator - A udiv or sdiv instruction, which can be marked as /// PossiblyExactOperator - A udiv or sdiv instruction, which can be marked as
/// "exact", indicating that no bits are destroyed. /// "exact", indicating that no bits are destroyed.
class PossiblyExactOperator : public Operator { class PossiblyExactOperator : public Operator {
public: public:
enum { enum {
IsExact = (1 << 0) IsExact = (1 << 0)
}; };
private: private:
~PossiblyExactOperator(); // do not implement
friend class BinaryOperator; friend class BinaryOperator;
friend class ConstantExpr; friend class ConstantExpr;
void setIsExact(bool B) { void setIsExact(bool B) {
SubclassOptionalData = (SubclassOptionalData & ~IsExact) | (B * IsExact ); SubclassOptionalData = (SubclassOptionalData & ~IsExact) | (B * IsExact );
} }
public: public:
/// isExact - Test whether this division is known to be exact, with /// isExact - Test whether this division is known to be exact, with
/// zero remainder. /// zero remainder.
bool isExact() const { bool isExact() const {
skipping to change at line 170 skipping to change at line 170
} }
static inline bool classof(const Value *V) { static inline bool classof(const Value *V) {
return (isa<Instruction>(V) && classof(cast<Instruction>(V))) || return (isa<Instruction>(V) && classof(cast<Instruction>(V))) ||
(isa<ConstantExpr>(V) && classof(cast<ConstantExpr>(V))); (isa<ConstantExpr>(V) && classof(cast<ConstantExpr>(V)));
} }
}; };
/// FPMathOperator - Utility class for floating point operations which can have /// FPMathOperator - Utility class for floating point operations which can have
/// information about relaxed accuracy requirements attached to them. /// information about relaxed accuracy requirements attached to them.
class FPMathOperator : public Operator { class FPMathOperator : public Operator {
private:
~FPMathOperator(); // do not implement
public: public:
/// \brief Get the maximum error permitted by this operation in ULPs. An /// \brief Get the maximum error permitted by this operation in ULPs. An
/// accuracy of 0.0 means that the operation should be performed with the /// accuracy of 0.0 means that the operation should be performed with the
/// default precision. /// default precision.
float getFPAccuracy() const; float getFPAccuracy() const;
static inline bool classof(const FPMathOperator *) { return true; }
static inline bool classof(const Instruction *I) { static inline bool classof(const Instruction *I) {
return I->getType()->isFPOrFPVectorTy(); return I->getType()->isFPOrFPVectorTy();
} }
static inline bool classof(const Value *V) { static inline bool classof(const Value *V) {
return isa<Instruction>(V) && classof(cast<Instruction>(V)); return isa<Instruction>(V) && classof(cast<Instruction>(V));
} }
}; };
/// ConcreteOperator - A helper template for defining operators for individ ual /// ConcreteOperator - A helper template for defining operators for individ ual
/// opcodes. /// opcodes.
template<typename SuperClass, unsigned Opc> template<typename SuperClass, unsigned Opc>
class ConcreteOperator : public SuperClass { class ConcreteOperator : public SuperClass {
~ConcreteOperator(); // DO NOT IMPLEMENT
public: public:
static inline bool classof(const ConcreteOperator<SuperClass, Opc> *) {
return true;
}
static inline bool classof(const Instruction *I) { static inline bool classof(const Instruction *I) {
return I->getOpcode() == Opc; return I->getOpcode() == Opc;
} }
static inline bool classof(const ConstantExpr *CE) { static inline bool classof(const ConstantExpr *CE) {
return CE->getOpcode() == Opc; return CE->getOpcode() == Opc;
} }
static inline bool classof(const Value *V) { static inline bool classof(const Value *V) {
return (isa<Instruction>(V) && classof(cast<Instruction>(V))) || return (isa<Instruction>(V) && classof(cast<Instruction>(V))) ||
(isa<ConstantExpr>(V) && classof(cast<ConstantExpr>(V))); (isa<ConstantExpr>(V) && classof(cast<ConstantExpr>(V)));
} }
}; };
class AddOperator class AddOperator
: public ConcreteOperator<OverflowingBinaryOperator, Instruction::Add> { : public ConcreteOperator<OverflowingBinaryOperator, Instruction::Add> {
~AddOperator(); // DO NOT IMPLEMENT
}; };
class SubOperator class SubOperator
: public ConcreteOperator<OverflowingBinaryOperator, Instruction::Sub> { : public ConcreteOperator<OverflowingBinaryOperator, Instruction::Sub> {
~SubOperator(); // DO NOT IMPLEMENT
}; };
class MulOperator class MulOperator
: public ConcreteOperator<OverflowingBinaryOperator, Instruction::Mul> { : public ConcreteOperator<OverflowingBinaryOperator, Instruction::Mul> {
~MulOperator(); // DO NOT IMPLEMENT
}; };
class ShlOperator class ShlOperator
: public ConcreteOperator<OverflowingBinaryOperator, Instruction::Shl> { : public ConcreteOperator<OverflowingBinaryOperator, Instruction::Shl> {
~ShlOperator(); // DO NOT IMPLEMENT
}; };
class SDivOperator class SDivOperator
: public ConcreteOperator<PossiblyExactOperator, Instruction::SDiv> { : public ConcreteOperator<PossiblyExactOperator, Instruction::SDiv> {
~SDivOperator(); // DO NOT IMPLEMENT
}; };
class UDivOperator class UDivOperator
: public ConcreteOperator<PossiblyExactOperator, Instruction::UDiv> { : public ConcreteOperator<PossiblyExactOperator, Instruction::UDiv> {
~UDivOperator(); // DO NOT IMPLEMENT
}; };
class AShrOperator class AShrOperator
: public ConcreteOperator<PossiblyExactOperator, Instruction::AShr> { : public ConcreteOperator<PossiblyExactOperator, Instruction::AShr> {
~AShrOperator(); // DO NOT IMPLEMENT
}; };
class LShrOperator class LShrOperator
: public ConcreteOperator<PossiblyExactOperator, Instruction::LShr> { : public ConcreteOperator<PossiblyExactOperator, Instruction::LShr> {
~LShrOperator(); // DO NOT IMPLEMENT
}; };
class GEPOperator class GEPOperator
: public ConcreteOperator<Operator, Instruction::GetElementPtr> { : public ConcreteOperator<Operator, Instruction::GetElementPtr> {
~GEPOperator(); // DO NOT IMPLEMENT
enum { enum {
IsInBounds = (1 << 0) IsInBounds = (1 << 0)
}; };
friend class GetElementPtrInst; friend class GetElementPtrInst;
friend class ConstantExpr; friend class ConstantExpr;
void setIsInBounds(bool B) { void setIsInBounds(bool B) {
SubclassOptionalData = SubclassOptionalData =
(SubclassOptionalData & ~IsInBounds) | (B * IsInBounds); (SubclassOptionalData & ~IsInBounds) | (B * IsInBounds);
} }
skipping to change at line 287 skipping to change at line 269
static unsigned getPointerOperandIndex() { static unsigned getPointerOperandIndex() {
return 0U; // get index for modifying correct oper and return 0U; // get index for modifying correct oper and
} }
/// getPointerOperandType - Method to return the pointer operand as a /// getPointerOperandType - Method to return the pointer operand as a
/// PointerType. /// PointerType.
Type *getPointerOperandType() const { Type *getPointerOperandType() const {
return getPointerOperand()->getType(); return getPointerOperand()->getType();
} }
/// getPointerAddressSpace - Method to return the address space of the
/// pointer operand.
unsigned getPointerAddressSpace() const {
return cast<PointerType>(getPointerOperandType())->getAddressSpace();
}
unsigned getNumIndices() const { // Note: always non-negative unsigned getNumIndices() const { // Note: always non-negative
return getNumOperands() - 1; return getNumOperands() - 1;
} }
bool hasIndices() const { bool hasIndices() const {
return getNumOperands() > 1; return getNumOperands() > 1;
} }
/// hasAllZeroIndices - Return true if all of the indices of this GEP are /// hasAllZeroIndices - Return true if all of the indices of this GEP are
/// zeros. If so, the result pointer and the first operand have the same /// zeros. If so, the result pointer and the first operand have the same
 End of changes. 20 change blocks. 
27 lines changed or deleted 17 lines changed or added


 Optional.h   Optional.h 
skipping to change at line 19 skipping to change at line 19
// //
// This file provides Optional, a template class modeled in the spirit of // This file provides Optional, a template class modeled in the spirit of
// OCaml's 'opt' variant. The idea is to strongly type whether or not // OCaml's 'opt' variant. The idea is to strongly type whether or not
// a value can be optional. // a value can be optional.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_ADT_OPTIONAL #ifndef LLVM_ADT_OPTIONAL
#define LLVM_ADT_OPTIONAL #define LLVM_ADT_OPTIONAL
#include "llvm/Support/Compiler.h"
#include <cassert> #include <cassert>
#if LLVM_USE_RVALUE_REFERENCES
#include <utility>
#endif
namespace llvm { namespace llvm {
template<typename T> template<typename T>
class Optional { class Optional {
T x; T x;
unsigned hasVal : 1; unsigned hasVal : 1;
public: public:
explicit Optional() : x(), hasVal(false) {} explicit Optional() : x(), hasVal(false) {}
Optional(const T &y) : x(y), hasVal(true) {} Optional(const T &y) : x(y), hasVal(true) {}
#if LLVM_USE_RVALUE_REFERENCES
Optional(T &&y) : x(std::forward<T>(y)), hasVal(true) {}
#endif
static inline Optional create(const T* y) { static inline Optional create(const T* y) {
return y ? Optional(*y) : Optional(); return y ? Optional(*y) : Optional();
} }
Optional &operator=(const T &y) { Optional &operator=(const T &y) {
x = y; x = y;
hasVal = true; hasVal = true;
return *this; return *this;
} }
 End of changes. 3 change blocks. 
0 lines changed or deleted 9 lines changed or added


 OwningPtr.h   OwningPtr.h 
skipping to change at line 17 skipping to change at line 17
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// //
// This file defines and implements the OwningPtr class. // This file defines and implements the OwningPtr class.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_ADT_OWNING_PTR_H #ifndef LLVM_ADT_OWNING_PTR_H
#define LLVM_ADT_OWNING_PTR_H #define LLVM_ADT_OWNING_PTR_H
#include "llvm/Support/Compiler.h"
#include <cassert> #include <cassert>
#include <cstddef> #include <cstddef>
namespace llvm { namespace llvm {
/// OwningPtr smart pointer - OwningPtr mimics a built-in pointer except th at it /// OwningPtr smart pointer - OwningPtr mimics a built-in pointer except th at it
/// guarantees deletion of the object pointed to, either on destruction of the /// guarantees deletion of the object pointed to, either on destruction of the
/// OwningPtr or via an explicit reset(). Once created, ownership of the /// OwningPtr or via an explicit reset(). Once created, ownership of the
/// pointee object can be taken away from OwningPtr by using the take metho d. /// pointee object can be taken away from OwningPtr by using the take metho d.
template<class T> template<class T>
class OwningPtr { class OwningPtr {
OwningPtr(OwningPtr const &); // DO NOT IMPLEMENT OwningPtr(OwningPtr const &) LLVM_DELETED_FUNCTION;
OwningPtr &operator=(OwningPtr const &); // DO NOT IMPLEMENT OwningPtr &operator=(OwningPtr const &) LLVM_DELETED_FUNCTION;
T *Ptr; T *Ptr;
public: public:
explicit OwningPtr(T *P = 0) : Ptr(P) {} explicit OwningPtr(T *P = 0) : Ptr(P) {}
#if LLVM_USE_RVALUE_REFERENCES
OwningPtr(OwningPtr &&Other) : Ptr(Other.take()) {}
OwningPtr &operator=(OwningPtr &&Other) {
reset(Other.take());
return *this;
}
#endif
~OwningPtr() { ~OwningPtr() {
delete Ptr; delete Ptr;
} }
/// reset - Change the current pointee to the specified pointer. Note th at /// reset - Change the current pointee to the specified pointer. Note th at
/// calling this with any pointer (including a null pointer) deletes the /// calling this with any pointer (including a null pointer) deletes the
/// current pointer. /// current pointer.
void reset(T *P = 0) { void reset(T *P = 0) {
if (P == Ptr) return; if (P == Ptr) return;
T *Tmp = Ptr; T *Tmp = Ptr;
skipping to change at line 82 skipping to change at line 92
template<class T> template<class T>
inline void swap(OwningPtr<T> &a, OwningPtr<T> &b) { inline void swap(OwningPtr<T> &a, OwningPtr<T> &b) {
a.swap(b); a.swap(b);
} }
/// OwningArrayPtr smart pointer - OwningArrayPtr provides the same /// OwningArrayPtr smart pointer - OwningArrayPtr provides the same
/// functionality as OwningPtr, except that it works for array types. /// functionality as OwningPtr, except that it works for array types.
template<class T> template<class T>
class OwningArrayPtr { class OwningArrayPtr {
OwningArrayPtr(OwningArrayPtr const &); // DO NOT IMPLEMENT OwningArrayPtr(OwningArrayPtr const &) LLVM_DELETED_FUNCTION;
OwningArrayPtr &operator=(OwningArrayPtr const &); // DO NOT IMPLEMENT OwningArrayPtr &operator=(OwningArrayPtr const &) LLVM_DELETED_FUNCTION;
T *Ptr; T *Ptr;
public: public:
explicit OwningArrayPtr(T *P = 0) : Ptr(P) {} explicit OwningArrayPtr(T *P = 0) : Ptr(P) {}
#if LLVM_USE_RVALUE_REFERENCES
OwningArrayPtr(OwningArrayPtr &&Other) : Ptr(Other.take()) {}
OwningArrayPtr &operator=(OwningArrayPtr &&Other) {
reset(Other.take());
return *this;
}
#endif
~OwningArrayPtr() { ~OwningArrayPtr() {
delete [] Ptr; delete [] Ptr;
} }
/// reset - Change the current pointee to the specified pointer. Note th at /// reset - Change the current pointee to the specified pointer. Note th at
/// calling this with any pointer (including a null pointer) deletes the /// calling this with any pointer (including a null pointer) deletes the
/// current pointer. /// current pointer.
void reset(T *P = 0) { void reset(T *P = 0) {
if (P == Ptr) return; if (P == Ptr) return;
T *Tmp = Ptr; T *Tmp = Ptr;
 End of changes. 5 change blocks. 
4 lines changed or deleted 23 lines changed or added


 PHITransAddr.h   PHITransAddr.h 
skipping to change at line 22 skipping to change at line 22
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_ANALYSIS_PHITRANSADDR_H #ifndef LLVM_ANALYSIS_PHITRANSADDR_H
#define LLVM_ANALYSIS_PHITRANSADDR_H #define LLVM_ANALYSIS_PHITRANSADDR_H
#include "llvm/Instruction.h" #include "llvm/Instruction.h"
#include "llvm/ADT/SmallVector.h" #include "llvm/ADT/SmallVector.h"
namespace llvm { namespace llvm {
class DominatorTree; class DominatorTree;
class TargetData; class DataLayout;
class TargetLibraryInfo; class TargetLibraryInfo;
/// PHITransAddr - An address value which tracks and handles phi translatio n. /// PHITransAddr - An address value which tracks and handles phi translatio n.
/// As we walk "up" the CFG through predecessors, we need to ensure that th e /// As we walk "up" the CFG through predecessors, we need to ensure that th e
/// address we're tracking is kept up to date. For example, if we're analy zing /// address we're tracking is kept up to date. For example, if we're analy zing
/// an address of "&A[i]" and walk through the definition of 'i' which is a PHI /// an address of "&A[i]" and walk through the definition of 'i' which is a PHI
/// node, we *must* phi translate i to get "&A[j]" or else we will analyze an /// node, we *must* phi translate i to get "&A[j]" or else we will analyze an
/// incorrect pointer in the predecessor block. /// incorrect pointer in the predecessor block.
/// ///
/// This is designed to be a relatively small object that lives on the stac k and /// This is designed to be a relatively small object that lives on the stac k and
/// is copyable. /// is copyable.
/// ///
class PHITransAddr { class PHITransAddr {
/// Addr - The actual address we're analyzing. /// Addr - The actual address we're analyzing.
Value *Addr; Value *Addr;
/// TD - The target data we are playing with if known, otherwise null. /// TD - The target data we are playing with if known, otherwise null.
const TargetData *TD; const DataLayout *TD;
/// TLI - The target library info if known, otherwise null. /// TLI - The target library info if known, otherwise null.
const TargetLibraryInfo *TLI; const TargetLibraryInfo *TLI;
/// InstInputs - The inputs for our symbolic address. /// InstInputs - The inputs for our symbolic address.
SmallVector<Instruction*, 4> InstInputs; SmallVector<Instruction*, 4> InstInputs;
public: public:
PHITransAddr(Value *addr, const TargetData *td) : Addr(addr), TD(td), TLI (0) { PHITransAddr(Value *addr, const DataLayout *td) : Addr(addr), TD(td), TLI (0) {
// If the address is an instruction, the whole thing is considered an i nput. // If the address is an instruction, the whole thing is considered an i nput.
if (Instruction *I = dyn_cast<Instruction>(Addr)) if (Instruction *I = dyn_cast<Instruction>(Addr))
InstInputs.push_back(I); InstInputs.push_back(I);
} }
Value *getAddr() const { return Addr; } Value *getAddr() const { return Addr; }
/// NeedsPHITranslationFromBlock - Return true if moving from the specifi ed /// NeedsPHITranslationFromBlock - Return true if moving from the specifi ed
/// BasicBlock to its predecessors requires PHI translation. /// BasicBlock to its predecessors requires PHI translation.
bool NeedsPHITranslationFromBlock(BasicBlock *BB) const { bool NeedsPHITranslationFromBlock(BasicBlock *BB) const {
 End of changes. 3 change blocks. 
3 lines changed or deleted 3 lines changed or added


 PackedVector.h   PackedVector.h 
skipping to change at line 22 skipping to change at line 22
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_ADT_PACKEDVECTOR_H #ifndef LLVM_ADT_PACKEDVECTOR_H
#define LLVM_ADT_PACKEDVECTOR_H #define LLVM_ADT_PACKEDVECTOR_H
#include "llvm/ADT/BitVector.h" #include "llvm/ADT/BitVector.h"
#include <limits> #include <limits>
namespace llvm { namespace llvm {
template <typename T, unsigned BitNum, bool isSigned> template <typename T, unsigned BitNum, typename BitVectorTy, bool isSigned>
class PackedVectorBase; class PackedVectorBase;
// This won't be necessary if we can specialize members without specializin g // This won't be necessary if we can specialize members without specializin g
// the parent template. // the parent template.
template <typename T, unsigned BitNum> template <typename T, unsigned BitNum, typename BitVectorTy>
class PackedVectorBase<T, BitNum, false> { class PackedVectorBase<T, BitNum, BitVectorTy, false> {
protected: protected:
static T getValue(const llvm::BitVector &Bits, unsigned Idx) { static T getValue(const BitVectorTy &Bits, unsigned Idx) {
T val = T(); T val = T();
for (unsigned i = 0; i != BitNum; ++i) for (unsigned i = 0; i != BitNum; ++i)
val = T(val | ((Bits[(Idx << (BitNum-1)) + i] ? 1UL : 0UL) << i)); val = T(val | ((Bits[(Idx << (BitNum-1)) + i] ? 1UL : 0UL) << i));
return val; return val;
} }
static void setValue(llvm::BitVector &Bits, unsigned Idx, T val) { static void setValue(BitVectorTy &Bits, unsigned Idx, T val) {
assert((val >> BitNum) == 0 && "value is too big"); assert((val >> BitNum) == 0 && "value is too big");
for (unsigned i = 0; i != BitNum; ++i) for (unsigned i = 0; i != BitNum; ++i)
Bits[(Idx << (BitNum-1)) + i] = val & (T(1) << i); Bits[(Idx << (BitNum-1)) + i] = val & (T(1) << i);
} }
}; };
template <typename T, unsigned BitNum> template <typename T, unsigned BitNum, typename BitVectorTy>
class PackedVectorBase<T, BitNum, true> { class PackedVectorBase<T, BitNum, BitVectorTy, true> {
protected: protected:
static T getValue(const llvm::BitVector &Bits, unsigned Idx) { static T getValue(const BitVectorTy &Bits, unsigned Idx) {
T val = T(); T val = T();
for (unsigned i = 0; i != BitNum-1; ++i) for (unsigned i = 0; i != BitNum-1; ++i)
val = T(val | ((Bits[(Idx << (BitNum-1)) + i] ? 1UL : 0UL) << i)); val = T(val | ((Bits[(Idx << (BitNum-1)) + i] ? 1UL : 0UL) << i));
if (Bits[(Idx << (BitNum-1)) + BitNum-1]) if (Bits[(Idx << (BitNum-1)) + BitNum-1])
val = ~val; val = ~val;
return val; return val;
} }
static void setValue(llvm::BitVector &Bits, unsigned Idx, T val) { static void setValue(BitVectorTy &Bits, unsigned Idx, T val) {
if (val < 0) { if (val < 0) {
val = ~val; val = ~val;
Bits.set((Idx << (BitNum-1)) + BitNum-1); Bits.set((Idx << (BitNum-1)) + BitNum-1);
} }
assert((val >> (BitNum-1)) == 0 && "value is too big"); assert((val >> (BitNum-1)) == 0 && "value is too big");
for (unsigned i = 0; i != BitNum-1; ++i) for (unsigned i = 0; i != BitNum-1; ++i)
Bits[(Idx << (BitNum-1)) + i] = val & (T(1) << i); Bits[(Idx << (BitNum-1)) + i] = val & (T(1) << i);
} }
}; };
/// \brief Store a vector of values using a specific number of bits for eac h /// \brief Store a vector of values using a specific number of bits for eac h
/// value. Both signed and unsigned types can be used, e.g /// value. Both signed and unsigned types can be used, e.g
/// @code /// @code
/// PackedVector<signed, 2> vec; /// PackedVector<signed, 2> vec;
/// @endcode /// @endcode
/// will create a vector accepting values -2, -1, 0, 1. Any other value wil l hit /// will create a vector accepting values -2, -1, 0, 1. Any other value wil l hit
/// an assertion. /// an assertion.
template <typename T, unsigned BitNum> template <typename T, unsigned BitNum, typename BitVectorTy = BitVector>
class PackedVector : public PackedVectorBase<T, BitNum, class PackedVector : public PackedVectorBase<T, BitNum, BitVectorTy,
std::numeric_limits<T>::is_sign ed> { std::numeric_limits<T>::is_sign ed> {
llvm::BitVector Bits; BitVectorTy Bits;
typedef PackedVectorBase<T, BitNum, std::numeric_limits<T>::is_signed> ba typedef PackedVectorBase<T, BitNum, BitVectorTy,
se; std::numeric_limits<T>::is_signed> base;
public: public:
class reference { class reference {
PackedVector &Vec; PackedVector &Vec;
const unsigned Idx; const unsigned Idx;
reference(); // Undefined reference(); // Undefined
public: public:
reference(PackedVector &vec, unsigned idx) : Vec(vec), Idx(idx) { } reference(PackedVector &vec, unsigned idx) : Vec(vec), Idx(idx) { }
 End of changes. 9 change blocks. 
14 lines changed or deleted 14 lines changed or added


 Pass.h   Pass.h 
skipping to change at line 32 skipping to change at line 32
// //
// Note that this file #includes PassSupport.h and PassAnalysisSupport.h (a t the // Note that this file #includes PassSupport.h and PassAnalysisSupport.h (a t the
// bottom), so the APIs exposed by these files are also automatically avail able // bottom), so the APIs exposed by these files are also automatically avail able
// to all users of this file. // to all users of this file.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_PASS_H #ifndef LLVM_PASS_H
#define LLVM_PASS_H #define LLVM_PASS_H
#include "llvm/Support/Compiler.h"
#include <string> #include <string>
namespace llvm { namespace llvm {
class BasicBlock; class BasicBlock;
class Function; class Function;
class Module; class Module;
class AnalysisUsage; class AnalysisUsage;
class PassInfo; class PassInfo;
class ImmutablePass; class ImmutablePass;
skipping to change at line 85 skipping to change at line 86
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
/// Pass interface - Implemented by all 'passes'. Subclass this if you are an /// Pass interface - Implemented by all 'passes'. Subclass this if you are an
/// interprocedural optimization or you do not fit into any of the more /// interprocedural optimization or you do not fit into any of the more
/// constrained passes described below. /// constrained passes described below.
/// ///
class Pass { class Pass {
AnalysisResolver *Resolver; // Used to resolve analysis AnalysisResolver *Resolver; // Used to resolve analysis
const void *PassID; const void *PassID;
PassKind Kind; PassKind Kind;
void operator=(const Pass&); // DO NOT IMPLEMENT void operator=(const Pass&) LLVM_DELETED_FUNCTION;
Pass(const Pass &); // DO NOT IMPLEMENT Pass(const Pass &) LLVM_DELETED_FUNCTION;
public: public:
explicit Pass(PassKind K, char &pid) : Resolver(0), PassID(&pid), Kind(K) { } explicit Pass(PassKind K, char &pid) : Resolver(0), PassID(&pid), Kind(K) { }
virtual ~Pass(); virtual ~Pass();
PassKind getPassKind() const { return Kind; } PassKind getPassKind() const { return Kind; }
/// getPassName - Return a nice clean name for a pass. This usually /// getPassName - Return a nice clean name for a pass. This usually
/// implemented in terms of the name that is registered by one of the /// implemented in terms of the name that is registered by one of the
/// Registration templates, but can be overloaded directly. /// Registration templates, but can be overloaded directly.
 End of changes. 2 change blocks. 
2 lines changed or deleted 3 lines changed or added


 PassAnalysisSupport.h   PassAnalysisSupport.h 
skipping to change at line 123 skipping to change at line 123
}; };
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// AnalysisResolver - Simple interface used by Pass objects to pull all // AnalysisResolver - Simple interface used by Pass objects to pull all
// analysis information out of pass manager that is responsible to manage // analysis information out of pass manager that is responsible to manage
// the pass. // the pass.
// //
class PMDataManager; class PMDataManager;
class AnalysisResolver { class AnalysisResolver {
private: private:
AnalysisResolver(); // DO NOT IMPLEMENT AnalysisResolver() LLVM_DELETED_FUNCTION;
public: public:
explicit AnalysisResolver(PMDataManager &P) : PM(P) { } explicit AnalysisResolver(PMDataManager &P) : PM(P) { }
inline PMDataManager &getPMDataManager() { return PM; } inline PMDataManager &getPMDataManager() { return PM; }
// Find pass that is implementing PI. // Find pass that is implementing PI.
Pass *findImplPass(AnalysisID PI) { Pass *findImplPass(AnalysisID PI) {
Pass *ResultPass = 0; Pass *ResultPass = 0;
for (unsigned i = 0; i < AnalysisImpls.size() ; ++i) { for (unsigned i = 0; i < AnalysisImpls.size() ; ++i) {
 End of changes. 1 change blocks. 
1 lines changed or deleted 1 lines changed or added


 PassManagers.h   PassManagers.h 
skipping to change at line 18 skipping to change at line 18
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// //
// This file declares the LLVM Pass Manager infrastructure. // This file declares the LLVM Pass Manager infrastructure.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_PASSMANAGERS_H #ifndef LLVM_PASSMANAGERS_H
#define LLVM_PASSMANAGERS_H #define LLVM_PASSMANAGERS_H
#include "llvm/Pass.h" #include "llvm/Pass.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/SmallVector.h" #include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/SmallPtrSet.h" #include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/DenseMap.h" #include "llvm/ADT/DenseMap.h"
#include <vector> #include <vector>
#include <map> #include <map>
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// Overview: // Overview:
// The Pass Manager Infrastructure manages passes. It's responsibilities ar e: // The Pass Manager Infrastructure manages passes. It's responsibilities ar e:
// //
skipping to change at line 185 skipping to change at line 186
virtual PMDataManager *getAsPMDataManager() = 0; virtual PMDataManager *getAsPMDataManager() = 0;
virtual PassManagerType getTopLevelPassManagerType() = 0; virtual PassManagerType getTopLevelPassManagerType() = 0;
public: public:
/// Schedule pass P for execution. Make sure that passes required by /// Schedule pass P for execution. Make sure that passes required by
/// P are run before P is run. Update analysis info maintained by /// P are run before P is run. Update analysis info maintained by
/// the manager. Remove dead passes. This is a recursive function. /// the manager. Remove dead passes. This is a recursive function.
void schedulePass(Pass *P); void schedulePass(Pass *P);
/// Set pass P as the last user of the given analysis passes. /// Set pass P as the last user of the given analysis passes.
void setLastUser(const SmallVectorImpl<Pass *> &AnalysisPasses, Pass *P); void setLastUser(ArrayRef<Pass*> AnalysisPasses, Pass *P);
/// Collect passes whose last user is P /// Collect passes whose last user is P
void collectLastUses(SmallVectorImpl<Pass *> &LastUses, Pass *P); void collectLastUses(SmallVectorImpl<Pass *> &LastUses, Pass *P);
/// Find the pass that implements Analysis AID. Search immutable /// Find the pass that implements Analysis AID. Search immutable
/// passes and all pass managers. If desired pass is not found /// passes and all pass managers. If desired pass is not found
/// then return NULL. /// then return NULL.
Pass *findAnalysisPass(AnalysisID AID); Pass *findAnalysisPass(AnalysisID AID);
/// Find analysis usage information for the pass P. /// Find analysis usage information for the pass P.
 End of changes. 2 change blocks. 
1 lines changed or deleted 2 lines changed or added


 PassSupport.h   PassSupport.h 
skipping to change at line 129 skipping to change at line 129
} }
/// getInterfacesImplemented - Return a list of all of the analysis group /// getInterfacesImplemented - Return a list of all of the analysis group
/// interfaces implemented by this pass. /// interfaces implemented by this pass.
/// ///
const std::vector<const PassInfo*> &getInterfacesImplemented() const { const std::vector<const PassInfo*> &getInterfacesImplemented() const {
return ItfImpl; return ItfImpl;
} }
private: private:
void operator=(const PassInfo &); // do not implement void operator=(const PassInfo &) LLVM_DELETED_FUNCTION;
PassInfo(const PassInfo &); // do not implement PassInfo(const PassInfo &) LLVM_DELETED_FUNCTION;
}; };
#define CALL_ONCE_INITIALIZATION(function) \ #define CALL_ONCE_INITIALIZATION(function) \
static volatile sys::cas_flag initialized = 0; \ static volatile sys::cas_flag initialized = 0; \
sys::cas_flag old_val = sys::CompareAndSwap(&initialized, 1, 0); \ sys::cas_flag old_val = sys::CompareAndSwap(&initialized, 1, 0); \
if (old_val == 0) { \ if (old_val == 0) { \
function(Registry); \ function(Registry); \
sys::MemoryFence(); \ sys::MemoryFence(); \
TsanIgnoreWritesBegin(); \ TsanIgnoreWritesBegin(); \
TsanHappensBefore(&initialized); \ TsanHappensBefore(&initialized); \
 End of changes. 1 change blocks. 
2 lines changed or deleted 2 lines changed or added


 Passes.h   Passes.h 
skipping to change at line 27 skipping to change at line 27
#include "llvm/Pass.h" #include "llvm/Pass.h"
#include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetMachine.h"
#include <string> #include <string>
namespace llvm { namespace llvm {
class FunctionPass; class FunctionPass;
class MachineFunctionPass; class MachineFunctionPass;
class PassInfo; class PassInfo;
class PassManagerBase;
class TargetLowering; class TargetLowering;
class TargetRegisterClass; class TargetRegisterClass;
class raw_ostream; class raw_ostream;
} }
namespace llvm { namespace llvm {
extern char &NoPassID; // Allow targets to choose not to run a pass.
class PassConfigImpl; class PassConfigImpl;
/// Target-Independent Code Generator Pass Configuration Options. /// Target-Independent Code Generator Pass Configuration Options.
/// ///
/// This is an ImmutablePass solely for the purpose of exposing CodeGen opt ions /// This is an ImmutablePass solely for the purpose of exposing CodeGen opt ions
/// to the internals of other CodeGen passes. /// to the internals of other CodeGen passes.
class TargetPassConfig : public ImmutablePass { class TargetPassConfig : public ImmutablePass {
public: public:
/// Pseudo Pass IDs. These are defined within TargetPassConfig because th ey /// Pseudo Pass IDs. These are defined within TargetPassConfig because th ey
/// are unregistered pass IDs. They are only useful for use with /// are unregistered pass IDs. They are only useful for use with
skipping to change at line 57 skipping to change at line 56
/// ///
/// EarlyTailDuplicate - A clone of the TailDuplicate pass that runs earl y /// EarlyTailDuplicate - A clone of the TailDuplicate pass that runs earl y
/// during codegen, on SSA form. /// during codegen, on SSA form.
static char EarlyTailDuplicateID; static char EarlyTailDuplicateID;
/// PostRAMachineLICM - A clone of the LICM pass that runs during late ma chine /// PostRAMachineLICM - A clone of the LICM pass that runs during late ma chine
/// optimization after regalloc. /// optimization after regalloc.
static char PostRAMachineLICMID; static char PostRAMachineLICMID;
private:
PassManagerBase *PM;
AnalysisID StartAfter;
AnalysisID StopAfter;
bool Started;
bool Stopped;
protected: protected:
TargetMachine *TM; TargetMachine *TM;
PassManagerBase *PM;
PassConfigImpl *Impl; // Internal data structures PassConfigImpl *Impl; // Internal data structures
bool Initialized; // Flagged after all passes are configured. bool Initialized; // Flagged after all passes are configured.
// Target Pass Options // Target Pass Options
// Targets provide a default setting, user flags override. // Targets provide a default setting, user flags override.
// //
bool DisableVerify; bool DisableVerify;
/// Default setting for -enable-tail-merge on this target. /// Default setting for -enable-tail-merge on this target.
bool EnableTailMerge; bool EnableTailMerge;
skipping to change at line 94 skipping to change at line 99
const TargetLowering *getTargetLowering() const { const TargetLowering *getTargetLowering() const {
return TM->getTargetLowering(); return TM->getTargetLowering();
} }
// //
void setInitialized() { Initialized = true; } void setInitialized() { Initialized = true; }
CodeGenOpt::Level getOptLevel() const { return TM->getOptLevel(); } CodeGenOpt::Level getOptLevel() const { return TM->getOptLevel(); }
/// setStartStopPasses - Set the StartAfter and StopAfter passes to allow
/// running only a portion of the normal code-gen pass sequence. If the
/// Start pass ID is zero, then compilation will begin at the normal poin
t;
/// otherwise, clear the Started flag to indicate that passes should not
be
/// added until the starting pass is seen. If the Stop pass ID is zero,
/// then compilation will continue to the end.
void setStartStopPasses(AnalysisID Start, AnalysisID Stop) {
StartAfter = Start;
StopAfter = Stop;
Started = (StartAfter == 0);
}
void setDisableVerify(bool Disable) { setOpt(DisableVerify, Disable); } void setDisableVerify(bool Disable) { setOpt(DisableVerify, Disable); }
bool getEnableTailMerge() const { return EnableTailMerge; } bool getEnableTailMerge() const { return EnableTailMerge; }
void setEnableTailMerge(bool Enable) { setOpt(EnableTailMerge, Enable); } void setEnableTailMerge(bool Enable) { setOpt(EnableTailMerge, Enable); }
/// Allow the target to override a specific pass without overriding the p ass /// Allow the target to override a specific pass without overriding the p ass
/// pipeline. When passes are added to the standard pipeline at the /// pipeline. When passes are added to the standard pipeline at the
/// point where StadardID is expected, add TargetID in its place. /// point where StandardID is expected, add TargetID in its place.
void substitutePass(char &StandardID, char &TargetID); void substitutePass(AnalysisID StandardID, AnalysisID TargetID);
/// Insert InsertedPassID pass after TargetPassID pass.
void insertPass(AnalysisID TargetPassID, AnalysisID InsertedPassID);
/// Allow the target to enable a specific standard pass by default. /// Allow the target to enable a specific standard pass by default.
void enablePass(char &ID) { substitutePass(ID, ID); } void enablePass(AnalysisID PassID) { substitutePass(PassID, PassID); }
/// Allow the target to disable a specific standard pass by default. /// Allow the target to disable a specific standard pass by default.
void disablePass(char &ID) { substitutePass(ID, NoPassID); } void disablePass(AnalysisID PassID) { substitutePass(PassID, 0); }
/// Return the pass ssubtituted for StandardID by the target. /// Return the pass substituted for StandardID by the target.
/// If no substitution exists, return StandardID. /// If no substitution exists, return StandardID.
AnalysisID getPassSubstitution(AnalysisID StandardID) const; AnalysisID getPassSubstitution(AnalysisID StandardID) const;
/// Return true if the optimized regalloc pipeline is enabled. /// Return true if the optimized regalloc pipeline is enabled.
bool getOptimizeRegAlloc() const; bool getOptimizeRegAlloc() const;
/// Add common target configurable passes that perform LLVM IR to IR /// Add common target configurable passes that perform LLVM IR to IR
/// transforms following machine independent optimization. /// transforms following machine independent optimization.
virtual void addIRPasses(); virtual void addIRPasses();
/// Add passes to lower exception handling for the code generator.
void addPassesToHandleExceptions();
/// Add common passes that perform LLVM IR to IR transforms in preparatio n for /// Add common passes that perform LLVM IR to IR transforms in preparatio n for
/// instruction selection. /// instruction selection.
virtual void addISelPrepare(); virtual void addISelPrepare();
/// addInstSelector - This method should install an instruction selector pass, /// addInstSelector - This method should install an instruction selector pass,
/// which converts from LLVM code to machine instructions. /// which converts from LLVM code to machine instructions.
virtual bool addInstSelector() { virtual bool addInstSelector() {
return true; return true;
} }
skipping to change at line 175 skipping to change at line 198
virtual FunctionPass *createTargetRegisterAllocator(bool Optimized); virtual FunctionPass *createTargetRegisterAllocator(bool Optimized);
/// addFastRegAlloc - Add the minimum set of target-independent passes th at /// addFastRegAlloc - Add the minimum set of target-independent passes th at
/// are required for fast register allocation. /// are required for fast register allocation.
virtual void addFastRegAlloc(FunctionPass *RegAllocPass); virtual void addFastRegAlloc(FunctionPass *RegAllocPass);
/// addOptimizedRegAlloc - Add passes related to register allocation. /// addOptimizedRegAlloc - Add passes related to register allocation.
/// LLVMTargetMachine provides standard regalloc passes for most targets. /// LLVMTargetMachine provides standard regalloc passes for most targets.
virtual void addOptimizedRegAlloc(FunctionPass *RegAllocPass); virtual void addOptimizedRegAlloc(FunctionPass *RegAllocPass);
/// addPreRewrite - Add passes to the optimized register allocation pipel
ine
/// after register allocation is complete, but before virtual registers a
re
/// rewritten to physical registers.
///
/// These passes must preserve VirtRegMap and LiveIntervals, and when run
ning
/// after RABasic or RAGreedy, they should take advantage of LiveRegMatri
x.
/// When these passes run, VirtRegMap contains legal physreg assignments
for
/// all virtual registers.
virtual bool addPreRewrite() {
return false;
}
/// addFinalizeRegAlloc - This method may be implemented by targets that want /// addFinalizeRegAlloc - This method may be implemented by targets that want
/// to run passes within the regalloc pipeline, immediately after the reg ister /// to run passes within the regalloc pipeline, immediately after the reg ister
/// allocation pass itself. These passes run as soon as virtual regisiter s /// allocation pass itself. These passes run as soon as virtual regisiter s
/// have been rewritten to physical registers but before and other postRA /// have been rewritten to physical registers but before and other postRA
/// optimization happens. Targets that have marked instructions for bundl ing /// optimization happens. Targets that have marked instructions for bundl ing
/// must have finalized those bundles by the time these passes have run, /// must have finalized those bundles by the time these passes have run,
/// because subsequent passes are not guaranteed to be bundle-aware. /// because subsequent passes are not guaranteed to be bundle-aware.
virtual bool addFinalizeRegAlloc() { virtual bool addFinalizeRegAlloc() {
return false; return false;
} }
skipping to change at line 219 skipping to change at line 254
/// passes immediately before machine code is emitted. This should retur n /// passes immediately before machine code is emitted. This should retur n
/// true if -print-machineinstrs should print out the code after the pass es. /// true if -print-machineinstrs should print out the code after the pass es.
virtual bool addPreEmitPass() { virtual bool addPreEmitPass() {
return false; return false;
} }
/// Utilities for targets to add passes to the pass manager. /// Utilities for targets to add passes to the pass manager.
/// ///
/// Add a CodeGen pass at this point in the pipeline after checking overr ides. /// Add a CodeGen pass at this point in the pipeline after checking overr ides.
/// Return the pass that was added, or NoPassID. /// Return the pass that was added, or zero if no pass was added.
AnalysisID addPass(char &ID); AnalysisID addPass(AnalysisID PassID);
/// Add a pass to the PassManager if that pass is supposed to be run, as
/// determined by the StartAfter and StopAfter options.
void addPass(Pass *P);
/// addMachinePasses helper to create the target-selected or overriden /// addMachinePasses helper to create the target-selected or overriden
/// regalloc pass. /// regalloc pass.
FunctionPass *createRegAllocPass(bool Optimized); FunctionPass *createRegAllocPass(bool Optimized);
/// printAndVerify - Add a pass to dump then verify the machine function, if /// printAndVerify - Add a pass to dump then verify the machine function, if
/// those steps are enabled. /// those steps are enabled.
/// ///
void printAndVerify(const char *Banner) const; void printAndVerify(const char *Banner);
}; };
} // namespace llvm } // namespace llvm
/// List of target independent CodeGen pass IDs. /// List of target independent CodeGen pass IDs.
namespace llvm { namespace llvm {
/// createUnreachableBlockEliminationPass - The LLVM code generator does not /// createUnreachableBlockEliminationPass - The LLVM code generator does not
/// work well with unreachable basic blocks (what live ranges make sense for a /// work well with unreachable basic blocks (what live ranges make sense for a
/// block that cannot be reached?). As such, a code generator should eit her /// block that cannot be reached?). As such, a code generator should eit her
/// not instruction select unreachable blocks, or run this pass as its /// not instruction select unreachable blocks, or run this pass as its
/// last LLVM modifying pass to clean up blocks that are not reachable fr om /// last LLVM modifying pass to clean up blocks that are not reachable fr om
skipping to change at line 279 skipping to change at line 318
extern char &PHIEliminationID; extern char &PHIEliminationID;
/// StrongPHIElimination - This pass eliminates machine instruction PHI /// StrongPHIElimination - This pass eliminates machine instruction PHI
/// nodes by inserting copy instructions. This destroys SSA information, but /// nodes by inserting copy instructions. This destroys SSA information, but
/// is the desired input for some register allocators. This pass is /// is the desired input for some register allocators. This pass is
/// "required" by these register allocator like this: /// "required" by these register allocator like this:
/// AU.addRequiredID(PHIEliminationID); /// AU.addRequiredID(PHIEliminationID);
/// This pass is still in development /// This pass is still in development
extern char &StrongPHIEliminationID; extern char &StrongPHIEliminationID;
/// LiveIntervals - This analysis keeps track of the live ranges of virtu
al
/// and physical registers.
extern char &LiveIntervalsID;
/// LiveStacks pass. An analysis keeping track of the liveness of stack s lots. /// LiveStacks pass. An analysis keeping track of the liveness of stack s lots.
extern char &LiveStacksID; extern char &LiveStacksID;
/// TwoAddressInstruction - This pass reduces two-address instructions to /// TwoAddressInstruction - This pass reduces two-address instructions to
/// use two operands. This destroys SSA information but it is desired by /// use two operands. This destroys SSA information but it is desired by
/// register allocators. /// register allocators.
extern char &TwoAddressInstructionPassID; extern char &TwoAddressInstructionPassID;
/// ProcessImpicitDefs pass - This pass removes IMPLICIT_DEFs. /// ProcessImpicitDefs pass - This pass removes IMPLICIT_DEFs.
extern char &ProcessImplicitDefsID; extern char &ProcessImplicitDefsID;
skipping to change at line 300 skipping to change at line 343
/// RegisterCoalescer - This pass merges live ranges to eliminate copies. /// RegisterCoalescer - This pass merges live ranges to eliminate copies.
extern char &RegisterCoalescerID; extern char &RegisterCoalescerID;
/// MachineScheduler - This pass schedules machine instructions. /// MachineScheduler - This pass schedules machine instructions.
extern char &MachineSchedulerID; extern char &MachineSchedulerID;
/// SpillPlacement analysis. Suggest optimal placement of spill code betw een /// SpillPlacement analysis. Suggest optimal placement of spill code betw een
/// basic blocks. /// basic blocks.
extern char &SpillPlacementID; extern char &SpillPlacementID;
/// VirtRegRewriter pass. Rewrite virtual registers to physical registers
as
/// assigned in VirtRegMap.
extern char &VirtRegRewriterID;
/// UnreachableMachineBlockElimination - This pass removes unreachable /// UnreachableMachineBlockElimination - This pass removes unreachable
/// machine basic blocks. /// machine basic blocks.
extern char &UnreachableMachineBlockElimID; extern char &UnreachableMachineBlockElimID;
/// DeadMachineInstructionElim - This pass removes dead machine instructi ons. /// DeadMachineInstructionElim - This pass removes dead machine instructi ons.
extern char &DeadMachineInstructionElimID; extern char &DeadMachineInstructionElimID;
/// FastRegisterAllocation Pass - This pass register allocates as fast as /// FastRegisterAllocation Pass - This pass register allocates as fast as
/// possible. It is best suited for debug code where live ranges are shor t. /// possible. It is best suited for debug code where live ranges are shor t.
/// ///
skipping to change at line 345 skipping to change at line 392
/// createPostRAScheduler - This pass performs post register allocation /// createPostRAScheduler - This pass performs post register allocation
/// scheduling. /// scheduling.
extern char &PostRASchedulerID; extern char &PostRASchedulerID;
/// BranchFolding - This pass performs machine code CFG based /// BranchFolding - This pass performs machine code CFG based
/// optimizations to delete branches to branches, eliminate branches to /// optimizations to delete branches to branches, eliminate branches to
/// successor blocks (creating fall throughs), and eliminating branches o ver /// successor blocks (creating fall throughs), and eliminating branches o ver
/// branches. /// branches.
extern char &BranchFolderPassID; extern char &BranchFolderPassID;
/// MachineFunctionPrinterPass - This pass prints out MachineInstr's.
extern char &MachineFunctionPrinterPassID;
/// TailDuplicate - Duplicate blocks with unconditional branches /// TailDuplicate - Duplicate blocks with unconditional branches
/// into tails of their predecessors. /// into tails of their predecessors.
extern char &TailDuplicateID; extern char &TailDuplicateID;
/// MachineTraceMetrics - This pass computes critical path and CPU resour
ce
/// usage in an ensemble of traces.
extern char &MachineTraceMetricsID;
/// EarlyIfConverter - This pass performs if-conversion on SSA form by
/// inserting cmov instructions.
extern char &EarlyIfConverterID;
/// StackSlotColoring - This pass performs stack coloring and merging.
/// It merges disjoint allocas to reduce the stack size.
extern char &StackColoringID;
/// IfConverter - This pass performs machine code if conversion. /// IfConverter - This pass performs machine code if conversion.
extern char &IfConverterID; extern char &IfConverterID;
/// MachineBlockPlacement - This pass places basic blocks based on branch /// MachineBlockPlacement - This pass places basic blocks based on branch
/// probabilities. /// probabilities.
extern char &MachineBlockPlacementID; extern char &MachineBlockPlacementID;
/// MachineBlockPlacementStats - This pass collects statistics about the /// MachineBlockPlacementStats - This pass collects statistics about the
/// basic block placement using branch probabilities and block frequency /// basic block placement using branch probabilities and block frequency
/// information. /// information.
 End of changes. 17 change blocks. 
11 lines changed or deleted 83 lines changed or added


 PathV1.h   PathV1.h 
skipping to change at line 683 skipping to change at line 683
return *this; return *this;
} }
/// @} /// @}
/// @name Methods /// @name Methods
/// @{ /// @{
public: public:
/// This function returns status information about the file. The type of /// This function returns status information about the file. The type of
/// path (file or directory) is updated to reflect the actual content s /// path (file or directory) is updated to reflect the actual content s
/// of the file system. /// of the file system.
/// @returns 0 on failure, with Error explaining why (if non-zero) /// @returns 0 on failure, with Error explaining why (if non-zero),
/// @returns a pointer to a FileStatus structure on success. /// otherwise returns a pointer to a FileStatus structure on success.
/// @brief Get file status. /// @brief Get file status.
const FileStatus *getFileStatus( const FileStatus *getFileStatus(
bool forceUpdate = false, ///< Force an update from the file system bool forceUpdate = false, ///< Force an update from the file system
std::string *Error = 0 ///< Optional place to return an error ms g. std::string *Error = 0 ///< Optional place to return an error ms g.
) const; ) const;
/// @} /// @}
/// @name Data /// @name Data
/// @{ /// @{
private: private:
 End of changes. 1 change blocks. 
2 lines changed or deleted 2 lines changed or added


 PathV2.h   PathV2.h 
skipping to change at line 42 skipping to change at line 42
/// ///
/// This is a bidirectional iterator that iterates over the individual /// This is a bidirectional iterator that iterates over the individual
/// components in \a path. The forward traversal order is as follows: /// components in \a path. The forward traversal order is as follows:
/// * The root-name element, if present. /// * The root-name element, if present.
/// * The root-directory element, if present. /// * The root-directory element, if present.
/// * Each successive filename element, if present. /// * Each successive filename element, if present.
/// * Dot, if one or more trailing non-root slash characters are present. /// * Dot, if one or more trailing non-root slash characters are present.
/// The backwards traversal order is the reverse of forward traversal. /// The backwards traversal order is the reverse of forward traversal.
/// ///
/// Iteration examples. Each component is separated by ',': /// Iteration examples. Each component is separated by ',':
/// / => / /// @code
/// /foo => /,foo /// / => /
/// foo/ => foo,. /// /foo => /,foo
/// /foo/bar => /,foo,bar /// foo/ => foo,.
/// ../ => ..,. /// /foo/bar => /,foo,bar
/// C:\foo\bar => C:,/,foo,bar /// ../ => ..,.
/// /// C:\foo\bar => C:,/,foo,bar
/// @endcode
class const_iterator { class const_iterator {
StringRef Path; //< The entire path. StringRef Path; ///< The entire path.
StringRef Component; //< The current component. Not necessarily in Path. StringRef Component; ///< The current component. Not necessarily in Path.
size_t Position; //< The iterators current position within Path. size_t Position; ///< The iterators current position within Path.
// An end iterator has Position = Path.size() + 1. // An end iterator has Position = Path.size() + 1.
friend const_iterator begin(StringRef path); friend const_iterator begin(StringRef path);
friend const_iterator end(StringRef path); friend const_iterator end(StringRef path);
public: public:
typedef const StringRef value_type; typedef const StringRef value_type;
typedef ptrdiff_t difference_type; typedef ptrdiff_t difference_type;
typedef value_type &reference; typedef value_type &reference;
typedef value_type *pointer; typedef value_type *pointer;
skipping to change at line 110 skipping to change at line 111
inline reverse_iterator rend(StringRef path) { inline reverse_iterator rend(StringRef path) {
return reverse_iterator(begin(path)); return reverse_iterator(begin(path));
} }
/// @} /// @}
/// @name Lexical Modifiers /// @name Lexical Modifiers
/// @{ /// @{
/// @brief Remove the last component from \a path unless it is the root dir . /// @brief Remove the last component from \a path unless it is the root dir .
/// ///
/// directory/filename.cpp => directory/ /// @code
/// directory/ => directory /// directory/filename.cpp => directory/
/// / => / /// directory/ => directory
/// / => /
/// @endcode
/// ///
/// @param path A path that is modified to not have a file component. /// @param path A path that is modified to not have a file component.
void remove_filename(SmallVectorImpl<char> &path); void remove_filename(SmallVectorImpl<char> &path);
/// @brief Replace the file extension of \a path with \a extension. /// @brief Replace the file extension of \a path with \a extension.
/// ///
/// ./filename.cpp => ./filename.extension /// @code
/// ./filename => ./filename.extension /// ./filename.cpp => ./filename.extension
/// ./ => ./.extension /// ./filename => ./filename.extension
/// ./ => ./.extension
/// @endcode
/// ///
/// @param path A path that has its extension replaced with \a extension. /// @param path A path that has its extension replaced with \a extension.
/// @param extension The extension to be added. It may be empty. It may als o /// @param extension The extension to be added. It may be empty. It may als o
/// optionally start with a '.', if it does not, one will be /// optionally start with a '.', if it does not, one will be
/// prepended. /// prepended.
void replace_extension(SmallVectorImpl<char> &path, const Twine &extension) ; void replace_extension(SmallVectorImpl<char> &path, const Twine &extension) ;
/// @brief Append to path. /// @brief Append to path.
/// ///
/// /foo + bar/f => /foo/bar/f /// @code
/// /foo/ + bar/f => /foo/bar/f /// /foo + bar/f => /foo/bar/f
/// foo + bar/f => foo/bar/f /// /foo/ + bar/f => /foo/bar/f
/// foo + bar/f => foo/bar/f
/// @endcode
/// ///
/// @param path Set to \a path + \a component. /// @param path Set to \a path + \a component.
/// @param component The component to be appended to \a path. /// @param a The component to be appended to \a path.
void append(SmallVectorImpl<char> &path, const Twine &a, void append(SmallVectorImpl<char> &path, const Twine &a,
const Twine &b = "", const Twine &b = "",
const Twine &c = "", const Twine &c = "",
const Twine &d = ""); const Twine &d = "");
/// @brief Append to path. /// @brief Append to path.
/// ///
/// /foo + [bar,f] => /foo/bar/f /// @code
/// /foo/ + [bar,f] => /foo/bar/f /// /foo + [bar,f] => /foo/bar/f
/// foo + [bar,f] => foo/bar/f /// /foo/ + [bar,f] => /foo/bar/f
/// foo + [bar,f] => foo/bar/f
/// @endcode
/// ///
/// @param path Set to \a path + [\a begin, \a end). /// @param path Set to \a path + [\a begin, \a end).
/// @param begin Start of components to append. /// @param begin Start of components to append.
/// @param end One past the end of components to append. /// @param end One past the end of components to append.
void append(SmallVectorImpl<char> &path, void append(SmallVectorImpl<char> &path,
const_iterator begin, const_iterator end); const_iterator begin, const_iterator end);
/// @} /// @}
/// @name Transforms (or some other better name) /// @name Transforms (or some other better name)
/// @{ /// @{
skipping to change at line 172 skipping to change at line 181
/// @param path A path that is transformed to native format. /// @param path A path that is transformed to native format.
/// @param result Holds the result of the transformation. /// @param result Holds the result of the transformation.
void native(const Twine &path, SmallVectorImpl<char> &result); void native(const Twine &path, SmallVectorImpl<char> &result);
/// @} /// @}
/// @name Lexical Observers /// @name Lexical Observers
/// @{ /// @{
/// @brief Get root name. /// @brief Get root name.
/// ///
/// //net/hello => //net /// @code
/// c:/hello => c: (on Windows, on other platforms nothing) /// //net/hello => //net
/// /hello => <empty> /// c:/hello => c: (on Windows, on other platforms nothing)
/// /hello => <empty>
/// @endcode
/// ///
/// @param path Input path. /// @param path Input path.
/// @result The root name of \a path if it has one, otherwise "". /// @result The root name of \a path if it has one, otherwise "".
const StringRef root_name(StringRef path); const StringRef root_name(StringRef path);
/// @brief Get root directory. /// @brief Get root directory.
/// ///
/// /goo/hello => / /// @code
/// c:/hello => / /// /goo/hello => /
/// d/file.txt => <empty> /// c:/hello => /
/// d/file.txt => <empty>
/// @endcode
/// ///
/// @param path Input path. /// @param path Input path.
/// @result The root directory of \a path if it has one, otherwise /// @result The root directory of \a path if it has one, otherwise
/// "". /// "".
const StringRef root_directory(StringRef path); const StringRef root_directory(StringRef path);
/// @brief Get root path. /// @brief Get root path.
/// ///
/// Equivalent to root_name + root_directory. /// Equivalent to root_name + root_directory.
/// ///
/// @param path Input path. /// @param path Input path.
/// @result The root path of \a path if it has one, otherwise "". /// @result The root path of \a path if it has one, otherwise "".
const StringRef root_path(StringRef path); const StringRef root_path(StringRef path);
/// @brief Get relative path. /// @brief Get relative path.
/// ///
/// C:\hello\world => hello\world /// @code
/// foo/bar => foo/bar /// C:\hello\world => hello\world
/// /foo/bar => foo/bar /// foo/bar => foo/bar
/// /foo/bar => foo/bar
/// @endcode
/// ///
/// @param path Input path. /// @param path Input path.
/// @result The path starting after root_path if one exists, otherwise "". /// @result The path starting after root_path if one exists, otherwise "".
const StringRef relative_path(StringRef path); const StringRef relative_path(StringRef path);
/// @brief Get parent path. /// @brief Get parent path.
/// ///
/// / => <empty> /// @code
/// /foo => / /// / => <empty>
/// foo/../bar => foo/.. /// /foo => /
/// foo/../bar => foo/..
/// @endcode
/// ///
/// @param path Input path. /// @param path Input path.
/// @result The parent path of \a path if one exists, otherwise "". /// @result The parent path of \a path if one exists, otherwise "".
const StringRef parent_path(StringRef path); const StringRef parent_path(StringRef path);
/// @brief Get filename. /// @brief Get filename.
/// ///
/// /foo.txt => foo.txt /// @code
/// . => . /// /foo.txt => foo.txt
/// .. => .. /// . => .
/// / => / /// .. => ..
/// / => /
/// @endcode
/// ///
/// @param path Input path. /// @param path Input path.
/// @result The filename part of \a path. This is defined as the last compo nent /// @result The filename part of \a path. This is defined as the last compo nent
/// of \a path. /// of \a path.
const StringRef filename(StringRef path); const StringRef filename(StringRef path);
/// @brief Get stem. /// @brief Get stem.
/// ///
/// If filename contains a dot but not solely one or two dots, result is th e /// If filename contains a dot but not solely one or two dots, result is th e
/// substring of filename ending at (but not including) the last dot. Other wise /// substring of filename ending at (but not including) the last dot. Other wise
/// it is filename. /// it is filename.
/// ///
/// /foo/bar.txt => bar /// @code
/// /foo/bar => bar /// /foo/bar.txt => bar
/// /foo/.txt => <empty> /// /foo/bar => bar
/// /foo/. => . /// /foo/.txt => <empty>
/// /foo/.. => .. /// /foo/. => .
/// /foo/.. => ..
/// @endcode
/// ///
/// @param path Input path. /// @param path Input path.
/// @result The stem of \a path. /// @result The stem of \a path.
const StringRef stem(StringRef path); const StringRef stem(StringRef path);
/// @brief Get extension. /// @brief Get extension.
/// ///
/// If filename contains a dot but not solely one or two dots, result is th e /// If filename contains a dot but not solely one or two dots, result is th e
/// substring of filename starting at (and including) the last dot, and end ing /// substring of filename starting at (and including) the last dot, and end ing
/// at the end of \a path. Otherwise "". /// at the end of \a path. Otherwise "".
/// ///
/// /foo/bar.txt => .txt /// @code
/// /foo/bar => <empty> /// /foo/bar.txt => .txt
/// /foo/.txt => .txt /// /foo/bar => <empty>
/// /foo/.txt => .txt
/// @endcode
/// ///
/// @param path Input path. /// @param path Input path.
/// @result The extension of \a path. /// @result The extension of \a path.
const StringRef extension(StringRef path); const StringRef extension(StringRef path);
/// @brief Check whether the given char is a path separator on the host OS. /// @brief Check whether the given char is a path separator on the host OS.
/// ///
/// @param value a character /// @param value a character
/// @result true if \a value is a path separator character on the host OS /// @result true if \a value is a path separator character on the host OS
bool is_separator(char value); bool is_separator(char value);
/// @brief Get the typical temporary directory for the system, e.g., /// @brief Get the typical temporary directory for the system, e.g.,
/// "/var/tmp" or "C:/TEMP" /// "/var/tmp" or "C:/TEMP"
/// ///
/// @param erasedOnReboot Whether to favor a path that is erased on reboot /// @param erasedOnReboot Whether to favor a path that is erased on reboot
/// rather than one that potentially persists longer. This parameter will b e /// rather than one that potentially persists longer. This parameter will b e
/// ignored if the user or system has set the typical environment variable /// ignored if the user or system has set the typical environment variable
/// (e.g., TEMP on Windows, TMPDIR on *nix) to specify a temporary director y. /// (e.g., TEMP on Windows, TMPDIR on *nix) to specify a temporary director y.
/// ///
/// @param Result Holds the resulting path name. /// @param result Holds the resulting path name.
void system_temp_directory(bool erasedOnReboot, SmallVectorImpl<char> &resu lt); void system_temp_directory(bool erasedOnReboot, SmallVectorImpl<char> &resu lt);
/// @brief Has root name? /// @brief Has root name?
/// ///
/// root_name != "" /// root_name != ""
/// ///
/// @param path Input path. /// @param path Input path.
/// @result True if the path has a root name, false otherwise. /// @result True if the path has a root name, false otherwise.
bool has_root_name(const Twine &path); bool has_root_name(const Twine &path);
 End of changes. 15 change blocks. 
48 lines changed or deleted 71 lines changed or added


 PointerIntPair.h   PointerIntPair.h 
skipping to change at line 112 skipping to change at line 112
return reinterpret_cast<PointerTy *>(&Value); return reinterpret_cast<PointerTy *>(&Value);
} }
void *getOpaqueValue() const { return reinterpret_cast<void*>(Value); } void *getOpaqueValue() const { return reinterpret_cast<void*>(Value); }
void setFromOpaqueValue(void *Val) { Value = reinterpret_cast<intptr_t>(V al);} void setFromOpaqueValue(void *Val) { Value = reinterpret_cast<intptr_t>(V al);}
static PointerIntPair getFromOpaqueValue(void *V) { static PointerIntPair getFromOpaqueValue(void *V) {
PointerIntPair P; P.setFromOpaqueValue(V); return P; PointerIntPair P; P.setFromOpaqueValue(V); return P;
} }
// Allow PointerIntPairs to be created from const void * if and only if t
he
// pointer type could be created from a const void *.
static PointerIntPair getFromOpaqueValue(const void *V) {
(void)PtrTraits::getFromVoidPointer(V);
return getFromOpaqueValue(const_cast<void *>(V));
}
bool operator==(const PointerIntPair &RHS) const {return Value == RHS.Val ue;} bool operator==(const PointerIntPair &RHS) const {return Value == RHS.Val ue;}
bool operator!=(const PointerIntPair &RHS) const {return Value != RHS.Val ue;} bool operator!=(const PointerIntPair &RHS) const {return Value != RHS.Val ue;}
bool operator<(const PointerIntPair &RHS) const {return Value < RHS.Value ;} bool operator<(const PointerIntPair &RHS) const {return Value < RHS.Value ;}
bool operator>(const PointerIntPair &RHS) const {return Value > RHS.Value ;} bool operator>(const PointerIntPair &RHS) const {return Value > RHS.Value ;}
bool operator<=(const PointerIntPair &RHS) const {return Value <= RHS.Val ue;} bool operator<=(const PointerIntPair &RHS) const {return Value <= RHS.Val ue;}
bool operator>=(const PointerIntPair &RHS) const {return Value >= RHS.Val ue;} bool operator>=(const PointerIntPair &RHS) const {return Value >= RHS.Val ue;}
}; };
template <typename T> struct isPodLike; template <typename T> struct isPodLike;
template<typename PointerTy, unsigned IntBits, typename IntType> template<typename PointerTy, unsigned IntBits, typename IntType>
struct isPodLike<PointerIntPair<PointerTy, IntBits, IntType> > { struct isPodLike<PointerIntPair<PointerTy, IntBits, IntType> > {
static const bool value = true; static const bool value = true;
}; };
// Provide specialization of DenseMapInfo for PointerIntPair. // Provide specialization of DenseMapInfo for PointerIntPair.
template<typename PointerTy, unsigned IntBits, typename IntType> template<typename PointerTy, unsigned IntBits, typename IntType>
struct DenseMapInfo<PointerIntPair<PointerTy, IntBits, IntType> > { struct DenseMapInfo<PointerIntPair<PointerTy, IntBits, IntType> > {
typedef PointerIntPair<PointerTy, IntBits, IntType> Ty; typedef PointerIntPair<PointerTy, IntBits, IntType> Ty;
static Ty getEmptyKey() { static Ty getEmptyKey() {
intptr_t Val = -1; uintptr_t Val = static_cast<uintptr_t>(-1);
Val <<= PointerLikeTypeTraits<PointerTy>::NumLowBitsAvailable; Val <<= PointerLikeTypeTraits<PointerTy>::NumLowBitsAvailable;
return Ty(reinterpret_cast<PointerTy>(Val), IntType((1 << IntBits)-1)); return Ty(reinterpret_cast<PointerTy>(Val), IntType((1 << IntBits)-1));
} }
static Ty getTombstoneKey() { static Ty getTombstoneKey() {
intptr_t Val = -2; uintptr_t Val = static_cast<uintptr_t>(-2);
Val <<= PointerLikeTypeTraits<PointerTy>::NumLowBitsAvailable; Val <<= PointerLikeTypeTraits<PointerTy>::NumLowBitsAvailable;
return Ty(reinterpret_cast<PointerTy>(Val), IntType(0)); return Ty(reinterpret_cast<PointerTy>(Val), IntType(0));
} }
static unsigned getHashValue(Ty V) { static unsigned getHashValue(Ty V) {
uintptr_t IV = reinterpret_cast<uintptr_t>(V.getOpaqueValue()); uintptr_t IV = reinterpret_cast<uintptr_t>(V.getOpaqueValue());
return unsigned(IV) ^ unsigned(IV >> 9); return unsigned(IV) ^ unsigned(IV >> 9);
} }
static bool isEqual(const Ty &LHS, const Ty &RHS) { return LHS == RHS; } static bool isEqual(const Ty &LHS, const Ty &RHS) { return LHS == RHS; }
}; };
skipping to change at line 161 skipping to change at line 168
PtrTraits> > { PtrTraits> > {
public: public:
static inline void * static inline void *
getAsVoidPointer(const PointerIntPair<PointerTy, IntBits, IntType> &P) { getAsVoidPointer(const PointerIntPair<PointerTy, IntBits, IntType> &P) {
return P.getOpaqueValue(); return P.getOpaqueValue();
} }
static inline PointerIntPair<PointerTy, IntBits, IntType> static inline PointerIntPair<PointerTy, IntBits, IntType>
getFromVoidPointer(void *P) { getFromVoidPointer(void *P) {
return PointerIntPair<PointerTy, IntBits, IntType>::getFromOpaqueValue( P); return PointerIntPair<PointerTy, IntBits, IntType>::getFromOpaqueValue( P);
} }
static inline PointerIntPair<PointerTy, IntBits, IntType>
getFromVoidPointer(const void *P) {
return PointerIntPair<PointerTy, IntBits, IntType>::getFromOpaqueValue(
P);
}
enum { enum {
NumLowBitsAvailable = PtrTraits::NumLowBitsAvailable - IntBits NumLowBitsAvailable = PtrTraits::NumLowBitsAvailable - IntBits
}; };
}; };
} // end namespace llvm } // end namespace llvm
#endif #endif
 End of changes. 4 change blocks. 
2 lines changed or deleted 15 lines changed or added


 PointerUnion.h   PointerUnion.h 
skipping to change at line 57 skipping to change at line 57
}; };
/// Provide PointerLikeTypeTraits for void* that is used by PointerUnion /// Provide PointerLikeTypeTraits for void* that is used by PointerUnion
/// for the two template arguments. /// for the two template arguments.
template <typename PT1, typename PT2> template <typename PT1, typename PT2>
class PointerUnionUIntTraits { class PointerUnionUIntTraits {
public: public:
static inline void *getAsVoidPointer(void *P) { return P; } static inline void *getAsVoidPointer(void *P) { return P; }
static inline void *getFromVoidPointer(void *P) { return P; } static inline void *getFromVoidPointer(void *P) { return P; }
enum { enum {
PT1BitsAv = PointerLikeTypeTraits<PT1>::NumLowBitsAvailable, PT1BitsAv = (int)(PointerLikeTypeTraits<PT1>::NumLowBitsAvailable),
PT2BitsAv = PointerLikeTypeTraits<PT2>::NumLowBitsAvailable, PT2BitsAv = (int)(PointerLikeTypeTraits<PT2>::NumLowBitsAvailable),
NumLowBitsAvailable = PT1BitsAv < PT2BitsAv ? PT1BitsAv : PT2BitsAv NumLowBitsAvailable = PT1BitsAv < PT2BitsAv ? PT1BitsAv : PT2BitsAv
}; };
}; };
/// PointerUnion - This implements a discriminated union of two pointer t ypes, /// PointerUnion - This implements a discriminated union of two pointer t ypes,
/// and keeps the discriminator bit-mangled into the low bits of the poin ter. /// and keeps the discriminator bit-mangled into the low bits of the poin ter.
/// This allows the implementation to be extremely efficient in space, bu t /// This allows the implementation to be extremely efficient in space, bu t
/// permits a very natural and type-safe API. /// permits a very natural and type-safe API.
/// ///
/// Common use patterns would be something like this: /// Common use patterns would be something like this:
 End of changes. 1 change blocks. 
2 lines changed or deleted 2 lines changed or added


 PostOrderIterator.h   PostOrderIterator.h 
skipping to change at line 26 skipping to change at line 26
#ifndef LLVM_ADT_POSTORDERITERATOR_H #ifndef LLVM_ADT_POSTORDERITERATOR_H
#define LLVM_ADT_POSTORDERITERATOR_H #define LLVM_ADT_POSTORDERITERATOR_H
#include "llvm/ADT/GraphTraits.h" #include "llvm/ADT/GraphTraits.h"
#include "llvm/ADT/SmallPtrSet.h" #include "llvm/ADT/SmallPtrSet.h"
#include <set> #include <set>
#include <vector> #include <vector>
namespace llvm { namespace llvm {
template<class SetType, bool External> // Non-external set // The po_iterator_storage template provides access to the set of already
// visited nodes during the po_iterator's depth-first traversal.
//
// The default implementation simply contains a set of visited nodes, while
// the Extended=true version uses a reference to an external set.
//
// It is possible to prune the depth-first traversal in several ways:
//
// - When providing an external set that already contains some graph nodes,
// those nodes won't be visited again. This is useful for restarting a
// post-order traversal on a graph with nodes that aren't dominated by a
// single node.
//
// - By providing a custom SetType class, unwanted graph nodes can be exclu
ded
// by having the insert() function return false. This could for example
// confine a CFG traversal to blocks in a specific loop.
//
// - Finally, by specializing the po_iterator_storage template itself, grap
h
// edges can be pruned by returning false in the insertEdge() function. T
his
// could be used to remove loop back-edges from the CFG seen by po_iterat
or.
//
// A specialized po_iterator_storage class can observe both the pre-order a
nd
// the post-order. The insertEdge() function is called in a pre-order, whil
e
// the finishPostorder() function is called just before the po_iterator mov
es
// on to the next node.
/// Default po_iterator_storage implementation with an internal set object.
template<class SetType, bool External>
class po_iterator_storage { class po_iterator_storage {
public:
SetType Visited; SetType Visited;
}; public:
// Return true if edge destination should be visited.
template<typename NodeType>
bool insertEdge(NodeType *From, NodeType *To) {
return Visited.insert(To);
}
/// DFSetTraits - Allow the SetType used to record depth-first search resul // Called after all children of BB have been visited.
ts to template<typename NodeType>
/// optionally record node postorder. void finishPostorder(NodeType *BB) {}
template<class SetType>
struct DFSetTraits {
static void finishPostorder(
typename SetType::iterator::value_type, SetType &) {}
}; };
/// Specialization of po_iterator_storage that references an external set.
template<class SetType> template<class SetType>
class po_iterator_storage<SetType, true> { class po_iterator_storage<SetType, true> {
SetType &Visited;
public: public:
po_iterator_storage(SetType &VSet) : Visited(VSet) {} po_iterator_storage(SetType &VSet) : Visited(VSet) {}
po_iterator_storage(const po_iterator_storage &S) : Visited(S.Visited) {} po_iterator_storage(const po_iterator_storage &S) : Visited(S.Visited) {}
SetType &Visited;
// Return true if edge destination should be visited, called with From =
0 for
// the root node.
// Graph edges can be pruned by specializing this function.
template<class NodeType>
bool insertEdge(NodeType *From, NodeType *To) { return Visited.insert(To)
; }
// Called after all children of BB have been visited.
template<class NodeType>
void finishPostorder(NodeType *BB) {}
}; };
template<class GraphT, template<class GraphT,
class SetType = llvm::SmallPtrSet<typename GraphTraits<GraphT>::NodeType* , 8>, class SetType = llvm::SmallPtrSet<typename GraphTraits<GraphT>::NodeType* , 8>,
bool ExtStorage = false, bool ExtStorage = false,
class GT = GraphTraits<GraphT> > class GT = GraphTraits<GraphT> >
class po_iterator : public std::iterator<std::forward_iterator_tag, class po_iterator : public std::iterator<std::forward_iterator_tag,
typename GT::NodeType, ptrdiff_t>, typename GT::NodeType, ptrdiff_t>,
public po_iterator_storage<SetType, ExtStorage> { public po_iterator_storage<SetType, ExtStorage> {
typedef std::iterator<std::forward_iterator_tag, typedef std::iterator<std::forward_iterator_tag,
skipping to change at line 67 skipping to change at line 106
typedef typename GT::NodeType NodeType; typedef typename GT::NodeType NodeType;
typedef typename GT::ChildIteratorType ChildItTy; typedef typename GT::ChildIteratorType ChildItTy;
// VisitStack - Used to maintain the ordering. Top = current block // VisitStack - Used to maintain the ordering. Top = current block
// First element is basic block pointer, second is the 'next child' to vi sit // First element is basic block pointer, second is the 'next child' to vi sit
std::vector<std::pair<NodeType *, ChildItTy> > VisitStack; std::vector<std::pair<NodeType *, ChildItTy> > VisitStack;
void traverseChild() { void traverseChild() {
while (VisitStack.back().second != GT::child_end(VisitStack.back().firs t)) { while (VisitStack.back().second != GT::child_end(VisitStack.back().firs t)) {
NodeType *BB = *VisitStack.back().second++; NodeType *BB = *VisitStack.back().second++;
if (this->Visited.insert(BB)) { // If the block is not visited... if (this->insertEdge(VisitStack.back().first, BB)) {
// If the block is not visited...
VisitStack.push_back(std::make_pair(BB, GT::child_begin(BB))); VisitStack.push_back(std::make_pair(BB, GT::child_begin(BB)));
} }
} }
} }
inline po_iterator(NodeType *BB) { inline po_iterator(NodeType *BB) {
this->Visited.insert(BB); this->insertEdge((NodeType*)0, BB);
VisitStack.push_back(std::make_pair(BB, GT::child_begin(BB))); VisitStack.push_back(std::make_pair(BB, GT::child_begin(BB)));
traverseChild(); traverseChild();
} }
inline po_iterator() {} // End is when stack is empty. inline po_iterator() {} // End is when stack is empty.
inline po_iterator(NodeType *BB, SetType &S) : inline po_iterator(NodeType *BB, SetType &S) :
po_iterator_storage<SetType, ExtStorage>(S) { po_iterator_storage<SetType, ExtStorage>(S) {
if (this->Visited.insert(BB)) { if (this->insertEdge((NodeType*)0, BB)) {
VisitStack.push_back(std::make_pair(BB, GT::child_begin(BB))); VisitStack.push_back(std::make_pair(BB, GT::child_begin(BB)));
traverseChild(); traverseChild();
} }
} }
inline po_iterator(SetType &S) : inline po_iterator(SetType &S) :
po_iterator_storage<SetType, ExtStorage>(S) { po_iterator_storage<SetType, ExtStorage>(S) {
} // End is when stack is empty. } // End is when stack is empty.
public: public:
typedef typename super::pointer pointer; typedef typename super::pointer pointer;
skipping to change at line 120 skipping to change at line 160
return VisitStack.back().first; return VisitStack.back().first;
} }
// This is a nonstandard operator-> that dereferences the pointer an extr a // This is a nonstandard operator-> that dereferences the pointer an extr a
// time... so that you can actually call methods ON the BasicBlock, becau se // time... so that you can actually call methods ON the BasicBlock, becau se
// the contained type is a pointer. This allows BBIt->getTerminator() f. e. // the contained type is a pointer. This allows BBIt->getTerminator() f. e.
// //
inline NodeType *operator->() const { return operator*(); } inline NodeType *operator->() const { return operator*(); }
inline _Self& operator++() { // Preincrement inline _Self& operator++() { // Preincrement
DFSetTraits<SetType>::finishPostorder(VisitStack.back().first, this->finishPostorder(VisitStack.back().first);
this->Visited);
VisitStack.pop_back(); VisitStack.pop_back();
if (!VisitStack.empty()) if (!VisitStack.empty())
traverseChild(); traverseChild();
return *this; return *this;
} }
inline _Self operator++(int) { // Postincrement inline _Self operator++(int) { // Postincrement
_Self tmp = *this; ++*this; return tmp; _Self tmp = *this; ++*this; return tmp;
} }
}; };
skipping to change at line 176 skipping to change at line 215
template <class T> template <class T>
ipo_iterator<T> ipo_begin(T G, bool Reverse = false) { ipo_iterator<T> ipo_begin(T G, bool Reverse = false) {
return ipo_iterator<T>::begin(G, Reverse); return ipo_iterator<T>::begin(G, Reverse);
} }
template <class T> template <class T>
ipo_iterator<T> ipo_end(T G){ ipo_iterator<T> ipo_end(T G){
return ipo_iterator<T>::end(G); return ipo_iterator<T>::end(G);
} }
//Provide global definitions of external inverse postorder iterators... // Provide global definitions of external inverse postorder iterators...
template <class T, template <class T,
class SetType = std::set<typename GraphTraits<T>::NodeType*> > class SetType = std::set<typename GraphTraits<T>::NodeType*> >
struct ipo_ext_iterator : public ipo_iterator<T, SetType, true> { struct ipo_ext_iterator : public ipo_iterator<T, SetType, true> {
ipo_ext_iterator(const ipo_iterator<T, SetType, true> &V) : ipo_ext_iterator(const ipo_iterator<T, SetType, true> &V) :
ipo_iterator<T, SetType, true>(&V) {} ipo_iterator<T, SetType, true>(V) {}
ipo_ext_iterator(const po_iterator<Inverse<T>, SetType, true> &V) : ipo_ext_iterator(const po_iterator<Inverse<T>, SetType, true> &V) :
ipo_iterator<T, SetType, true>(&V) {} ipo_iterator<T, SetType, true>(V) {}
}; };
template <class T, class SetType> template <class T, class SetType>
ipo_ext_iterator<T, SetType> ipo_ext_begin(T G, SetType &S) { ipo_ext_iterator<T, SetType> ipo_ext_begin(T G, SetType &S) {
return ipo_ext_iterator<T, SetType>::begin(G, S); return ipo_ext_iterator<T, SetType>::begin(G, S);
} }
template <class T, class SetType> template <class T, class SetType>
ipo_ext_iterator<T, SetType> ipo_ext_end(T G, SetType &S) { ipo_ext_iterator<T, SetType> ipo_ext_end(T G, SetType &S) {
return ipo_ext_iterator<T, SetType>::end(G, S); return ipo_ext_iterator<T, SetType>::end(G, S);
 End of changes. 14 change blocks. 
19 lines changed or deleted 66 lines changed or added


 PrettyStackTrace.h   PrettyStackTrace.h 
skipping to change at line 19 skipping to change at line 19
// //
// This file defines the PrettyStackTraceEntry class, which is used to make // This file defines the PrettyStackTraceEntry class, which is used to make
// crashes give more contextual information about what the program was doin g // crashes give more contextual information about what the program was doin g
// when it crashed. // when it crashed.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_SUPPORT_PRETTYSTACKTRACE_H #ifndef LLVM_SUPPORT_PRETTYSTACKTRACE_H
#define LLVM_SUPPORT_PRETTYSTACKTRACE_H #define LLVM_SUPPORT_PRETTYSTACKTRACE_H
#include "llvm/Support/Compiler.h"
namespace llvm { namespace llvm {
class raw_ostream; class raw_ostream;
/// DisablePrettyStackTrace - Set this to true to disable this module. Th is /// DisablePrettyStackTrace - Set this to true to disable this module. Th is
/// might be necessary if the host application installs its own signal /// might be necessary if the host application installs its own signal
/// handlers which conflict with the ones installed by this module. /// handlers which conflict with the ones installed by this module.
/// Defaults to false. /// Defaults to false.
extern bool DisablePrettyStackTrace; extern bool DisablePrettyStackTrace;
/// PrettyStackTraceEntry - This class is used to represent a frame of th e /// PrettyStackTraceEntry - This class is used to represent a frame of th e
/// "pretty" stack trace that is dumped when a program crashes. You can d efine /// "pretty" stack trace that is dumped when a program crashes. You can d efine
/// subclasses of this and declare them on the program stack: when they a re /// subclasses of this and declare them on the program stack: when they a re
/// constructed and destructed, they will add their symbolic frames to a /// constructed and destructed, they will add their symbolic frames to a
/// virtual stack trace. This gets dumped out if the program crashes. /// virtual stack trace. This gets dumped out if the program crashes.
class PrettyStackTraceEntry { class PrettyStackTraceEntry {
const PrettyStackTraceEntry *NextEntry; const PrettyStackTraceEntry *NextEntry;
PrettyStackTraceEntry(const PrettyStackTraceEntry &); // DO NOT IMPLEME PrettyStackTraceEntry(const PrettyStackTraceEntry &) LLVM_DELETED_FUNCT
NT ION;
void operator=(const PrettyStackTraceEntry&); // DO NOT IMPLEME void operator=(const PrettyStackTraceEntry&) LLVM_DELETED_FUNCTION;
NT
public: public:
PrettyStackTraceEntry(); PrettyStackTraceEntry();
virtual ~PrettyStackTraceEntry(); virtual ~PrettyStackTraceEntry();
/// print - Emit information about this stack frame to OS. /// print - Emit information about this stack frame to OS.
virtual void print(raw_ostream &OS) const = 0; virtual void print(raw_ostream &OS) const = 0;
/// getNextEntry - Return the next entry in the list of frames. /// getNextEntry - Return the next entry in the list of frames.
const PrettyStackTraceEntry *getNextEntry() const { return NextEntry; } const PrettyStackTraceEntry *getNextEntry() const { return NextEntry; }
}; };
/// PrettyStackTraceString - This object prints a specified string (which /// PrettyStackTraceString - This object prints a specified string (which
/// should not contain newlines) to the stream as the stack trace when a crash /// should not contain newlines) to the stream as the stack trace when a crash
/// occurs. /// occurs.
class PrettyStackTraceString : public PrettyStackTraceEntry { class PrettyStackTraceString : public PrettyStackTraceEntry {
const char *Str; const char *Str;
public: public:
PrettyStackTraceString(const char *str) : Str(str) {} PrettyStackTraceString(const char *str) : Str(str) {}
virtual void print(raw_ostream &OS) const; virtual void print(raw_ostream &OS) const LLVM_OVERRIDE;
}; };
/// PrettyStackTraceProgram - This object prints a specified program argu ments /// PrettyStackTraceProgram - This object prints a specified program argu ments
/// to the stream as the stack trace when a crash occurs. /// to the stream as the stack trace when a crash occurs.
class PrettyStackTraceProgram : public PrettyStackTraceEntry { class PrettyStackTraceProgram : public PrettyStackTraceEntry {
int ArgC; int ArgC;
const char *const *ArgV; const char *const *ArgV;
public: public:
PrettyStackTraceProgram(int argc, const char * const*argv) PrettyStackTraceProgram(int argc, const char * const*argv)
: ArgC(argc), ArgV(argv) {} : ArgC(argc), ArgV(argv) {}
virtual void print(raw_ostream &OS) const; virtual void print(raw_ostream &OS) const LLVM_OVERRIDE;
}; };
} // end namespace llvm } // end namespace llvm
#endif #endif
 End of changes. 4 change blocks. 
6 lines changed or deleted 7 lines changed or added


 Process.h   Process.h 
//===- llvm/Support/Process.h ------------------------------------*- C++ -* -===// //===- llvm/Support/Process.h -----------------------------------*- C++ -*- ===//
// //
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
// //
// This file is distributed under the University of Illinois Open Source // This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details. // License. See LICENSE.TXT for details.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// //
// This file declares the llvm::sys::Process class. // This file declares the llvm::sys::Process class.
// //
skipping to change at line 100 skipping to change at line 100
/// This function determines if the standard error is connected to a /// This function determines if the standard error is connected to a
/// "tty" or "console" window. That is, the output would be displayed to /// "tty" or "console" window. That is, the output would be displayed to
/// the user rather than being put on a pipe or stored in a file. /// the user rather than being put on a pipe or stored in a file.
static bool StandardErrIsDisplayed(); static bool StandardErrIsDisplayed();
/// This function determines if the given file descriptor is connecte d to /// This function determines if the given file descriptor is connecte d to
/// a "tty" or "console" window. That is, the output would be display ed to /// a "tty" or "console" window. That is, the output would be display ed to
/// the user rather than being put on a pipe or stored in a file. /// the user rather than being put on a pipe or stored in a file.
static bool FileDescriptorIsDisplayed(int fd); static bool FileDescriptorIsDisplayed(int fd);
/// This function determines if the given file descriptor is displayd
and
/// supports colors.
static bool FileDescriptorHasColors(int fd);
/// This function determines the number of columns in the window /// This function determines the number of columns in the window
/// if standard output is connected to a "tty" or "console" /// if standard output is connected to a "tty" or "console"
/// window. If standard output is not connected to a tty or /// window. If standard output is not connected to a tty or
/// console, or if the number of columns cannot be determined, /// console, or if the number of columns cannot be determined,
/// this routine returns zero. /// this routine returns zero.
static unsigned StandardOutColumns(); static unsigned StandardOutColumns();
/// This function determines the number of columns in the window /// This function determines the number of columns in the window
/// if standard error is connected to a "tty" or "console" /// if standard error is connected to a "tty" or "console"
/// window. If standard error is not connected to a tty or /// window. If standard error is not connected to a tty or
skipping to change at line 145 skipping to change at line 149
/// Same as OutputColor, but only enables the bold attribute. /// Same as OutputColor, but only enables the bold attribute.
static const char *OutputBold(bool bg); static const char *OutputBold(bool bg);
/// This function returns the escape sequence to reverse forground an d /// This function returns the escape sequence to reverse forground an d
/// background colors. /// background colors.
static const char *OutputReverse(); static const char *OutputReverse();
/// Resets the terminals colors, or returns an escape sequence to do so. /// Resets the terminals colors, or returns an escape sequence to do so.
static const char *ResetColor(); static const char *ResetColor();
/// Get the result of a process wide random number generator. The
/// generator will be automatically seeded in non-deterministic fashi
on.
static unsigned GetRandomNumber();
/// @} /// @}
}; };
} }
} }
#endif #endif
 End of changes. 3 change blocks. 
1 lines changed or deleted 11 lines changed or added


 ProfileInfoLoader.h   ProfileInfoLoader.h 
skipping to change at line 31 skipping to change at line 31
#include <utility> #include <utility>
namespace llvm { namespace llvm {
class Module; class Module;
class Function; class Function;
class BasicBlock; class BasicBlock;
class ProfileInfoLoader { class ProfileInfoLoader {
const std::string &Filename; const std::string &Filename;
Module &M;
std::vector<std::string> CommandLines; std::vector<std::string> CommandLines;
std::vector<unsigned> FunctionCounts; std::vector<unsigned> FunctionCounts;
std::vector<unsigned> BlockCounts; std::vector<unsigned> BlockCounts;
std::vector<unsigned> EdgeCounts; std::vector<unsigned> EdgeCounts;
std::vector<unsigned> OptimalEdgeCounts; std::vector<unsigned> OptimalEdgeCounts;
std::vector<unsigned> BBTrace; std::vector<unsigned> BBTrace;
bool Warned;
public: public:
// ProfileInfoLoader ctor - Read the specified profiling data file, exiti ng // ProfileInfoLoader ctor - Read the specified profiling data file, exiti ng
// the program if the file is invalid or broken. // the program if the file is invalid or broken.
ProfileInfoLoader(const char *ToolName, const std::string &Filename, ProfileInfoLoader(const char *ToolName, const std::string &Filename);
Module &M);
static const unsigned Uncounted; static const unsigned Uncounted;
unsigned getNumExecutions() const { return CommandLines.size(); } unsigned getNumExecutions() const { return CommandLines.size(); }
const std::string &getExecution(unsigned i) const { return CommandLines[i ]; } const std::string &getExecution(unsigned i) const { return CommandLines[i ]; }
const std::string &getFileName() const { return Filename; } const std::string &getFileName() const { return Filename; }
// getRawFunctionCounts - This method is used by consumers of function // getRawFunctionCounts - This method is used by consumers of function
// counting information. // counting information.
 End of changes. 3 change blocks. 
4 lines changed or deleted 1 lines changed or added


 ProfileInfoTypes.h   ProfileInfoTypes.h 
skipping to change at line 30 skipping to change at line 30
#if defined(__cplusplus) #if defined(__cplusplus)
extern "C" { extern "C" {
#endif #endif
/* IDs to distinguish between those path counters stored in hashses vs arra ys */ /* IDs to distinguish between those path counters stored in hashses vs arra ys */
enum ProfilingStorageType { enum ProfilingStorageType {
ProfilingArray = 1, ProfilingArray = 1,
ProfilingHash = 2 ProfilingHash = 2
}; };
enum ProfilingType { #include "llvm/Analysis/ProfileDataTypes.h"
ArgumentInfo = 1, /* The command line argument block */
FunctionInfo = 2, /* Function profiling information */
BlockInfo = 3, /* Block profiling information */
EdgeInfo = 4, /* Edge profiling information */
PathInfo = 5, /* Path profiling information */
BBTraceInfo = 6, /* Basic block trace information */
OptEdgeInfo = 7 /* Edge profiling information, optimal version */
};
/* /*
* The header for tables that map path numbers to path counters. * The header for tables that map path numbers to path counters.
*/ */
typedef struct { typedef struct {
unsigned fnNumber; /* function number for these counters */ unsigned fnNumber; /* function number for these counters */
unsigned numEntries; /* number of entries stored */ unsigned numEntries; /* number of entries stored */
} PathProfileHeader; } PathProfileHeader;
/* /*
 End of changes. 1 change blocks. 
9 lines changed or deleted 1 lines changed or added


 Program.h   Program.h 
skipping to change at line 37 skipping to change at line 37
/// operating system. It provides a platform generic way to find executab le /// operating system. It provides a platform generic way to find executab le
/// programs from the path and to execute them in various ways. The sys:: Path /// programs from the path and to execute them in various ways. The sys:: Path
/// class is used to specify the location of the Program. /// class is used to specify the location of the Program.
/// @since 1.4 /// @since 1.4
/// @brief An abstraction for finding and executing programs. /// @brief An abstraction for finding and executing programs.
class Program { class Program {
/// Opaque handle for target specific data. /// Opaque handle for target specific data.
void *Data_; void *Data_;
// Noncopyable. // Noncopyable.
Program(const Program& other); Program(const Program& other) LLVM_DELETED_FUNCTION;
Program& operator=(const Program& other); Program& operator=(const Program& other) LLVM_DELETED_FUNCTION;
/// @name Methods /// @name Methods
/// @{ /// @{
public: public:
Program(); Program();
~Program(); ~Program();
/// Return process ID of this program. /// Return process ID of this program.
unsigned GetPid() const; unsigned GetPid() const;
 End of changes. 1 change blocks. 
2 lines changed or deleted 2 lines changed or added


 PromoteMemToReg.h   PromoteMemToReg.h 
skipping to change at line 24 skipping to change at line 24
#ifndef TRANSFORMS_UTILS_PROMOTEMEMTOREG_H #ifndef TRANSFORMS_UTILS_PROMOTEMEMTOREG_H
#define TRANSFORMS_UTILS_PROMOTEMEMTOREG_H #define TRANSFORMS_UTILS_PROMOTEMEMTOREG_H
#include <vector> #include <vector>
namespace llvm { namespace llvm {
class AllocaInst; class AllocaInst;
class DominatorTree; class DominatorTree;
class DominanceFrontier;
class AliasSetTracker; class AliasSetTracker;
/// isAllocaPromotable - Return true if this alloca is legal for promotion. /// isAllocaPromotable - Return true if this alloca is legal for promotion.
/// This is true if there are only loads and stores to the alloca... /// This is true if there are only loads and stores to the alloca...
/// ///
bool isAllocaPromotable(const AllocaInst *AI); bool isAllocaPromotable(const AllocaInst *AI);
/// PromoteMemToReg - Promote the specified list of alloca instructions int o /// PromoteMemToReg - Promote the specified list of alloca instructions int o
/// scalar registers, inserting PHI nodes as appropriate. This function ma kes /// scalar registers, inserting PHI nodes as appropriate. This function ma kes
/// use of DominanceFrontier information. This function does not modify th e CFG /// use of DominanceFrontier information. This function does not modify th e CFG
 End of changes. 1 change blocks. 
1 lines changed or deleted 0 lines changed or added


 PseudoSourceValue.h   PseudoSourceValue.h 
skipping to change at line 53 skipping to change at line 53
/// PseudoSourceValue may also be pointed to by an LLVM IR Value. /// PseudoSourceValue may also be pointed to by an LLVM IR Value.
virtual bool isAliased(const MachineFrameInfo *) const; virtual bool isAliased(const MachineFrameInfo *) const;
/// mayAlias - Return true if the memory pointed to by this /// mayAlias - Return true if the memory pointed to by this
/// PseudoSourceValue can ever alias a LLVM IR Value. /// PseudoSourceValue can ever alias a LLVM IR Value.
virtual bool mayAlias(const MachineFrameInfo *) const; virtual bool mayAlias(const MachineFrameInfo *) const;
/// classof - Methods for support type inquiry through isa, cast, and /// classof - Methods for support type inquiry through isa, cast, and
/// dyn_cast: /// dyn_cast:
/// ///
static inline bool classof(const PseudoSourceValue *) { return true; }
static inline bool classof(const Value *V) { static inline bool classof(const Value *V) {
return V->getValueID() == PseudoSourceValueVal || return V->getValueID() == PseudoSourceValueVal ||
V->getValueID() == FixedStackPseudoSourceValueVal; V->getValueID() == FixedStackPseudoSourceValueVal;
} }
/// A pseudo source value referencing a fixed stack frame entry, /// A pseudo source value referencing a fixed stack frame entry,
/// e.g., a spill slot. /// e.g., a spill slot.
static const PseudoSourceValue *getFixedStack(int FI); static const PseudoSourceValue *getFixedStack(int FI);
/// A pseudo source value referencing the area below the stack frame of /// A pseudo source value referencing the area below the stack frame of
skipping to change at line 93 skipping to change at line 92
/// index. /// index.
class FixedStackPseudoSourceValue : public PseudoSourceValue { class FixedStackPseudoSourceValue : public PseudoSourceValue {
const int FI; const int FI;
public: public:
explicit FixedStackPseudoSourceValue(int fi) : explicit FixedStackPseudoSourceValue(int fi) :
PseudoSourceValue(FixedStackPseudoSourceValueVal), FI(fi) {} PseudoSourceValue(FixedStackPseudoSourceValueVal), FI(fi) {}
/// classof - Methods for support type inquiry through isa, cast, and /// classof - Methods for support type inquiry through isa, cast, and
/// dyn_cast: /// dyn_cast:
/// ///
static inline bool classof(const FixedStackPseudoSourceValue *) {
return true;
}
static inline bool classof(const Value *V) { static inline bool classof(const Value *V) {
return V->getValueID() == FixedStackPseudoSourceValueVal; return V->getValueID() == FixedStackPseudoSourceValueVal;
} }
virtual bool isConstant(const MachineFrameInfo *MFI) const; virtual bool isConstant(const MachineFrameInfo *MFI) const;
virtual bool isAliased(const MachineFrameInfo *MFI) const; virtual bool isAliased(const MachineFrameInfo *MFI) const;
virtual bool mayAlias(const MachineFrameInfo *) const; virtual bool mayAlias(const MachineFrameInfo *) const;
 End of changes. 2 change blocks. 
4 lines changed or deleted 0 lines changed or added


 RWMutex.h   RWMutex.h 
skipping to change at line 17 skipping to change at line 17
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// //
// This file declares the llvm::sys::RWMutex class. // This file declares the llvm::sys::RWMutex class.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_SYSTEM_RWMUTEX_H #ifndef LLVM_SYSTEM_RWMUTEX_H
#define LLVM_SYSTEM_RWMUTEX_H #define LLVM_SYSTEM_RWMUTEX_H
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Threading.h" #include "llvm/Support/Threading.h"
#include <cassert> #include <cassert>
namespace llvm namespace llvm
{ {
namespace sys namespace sys
{ {
/// @brief Platform agnostic RWMutex class. /// @brief Platform agnostic RWMutex class.
class RWMutexImpl class RWMutexImpl
{ {
skipping to change at line 78 skipping to change at line 79
//@} //@}
/// @name Platform Dependent Data /// @name Platform Dependent Data
/// @{ /// @{
private: private:
void* data_; ///< We don't know what the data will be void* data_; ///< We don't know what the data will be
/// @} /// @}
/// @name Do Not Implement /// @name Do Not Implement
/// @{ /// @{
private: private:
RWMutexImpl(const RWMutexImpl & original); RWMutexImpl(const RWMutexImpl & original) LLVM_DELETED_FUNCTION;
void operator=(const RWMutexImpl &); void operator=(const RWMutexImpl &) LLVM_DELETED_FUNCTION;
/// @} /// @}
}; };
/// SmartMutex - An R/W mutex with a compile time constant parameter th at /// SmartMutex - An R/W mutex with a compile time constant parameter th at
/// indicates whether this mutex should become a no-op when we're not /// indicates whether this mutex should become a no-op when we're not
/// running in multithreaded mode. /// running in multithreaded mode.
template<bool mt_only> template<bool mt_only>
class SmartRWMutex : public RWMutexImpl { class SmartRWMutex : public RWMutexImpl {
unsigned readers, writers; unsigned readers, writers;
public: public:
 End of changes. 2 change blocks. 
2 lines changed or deleted 3 lines changed or added


 ReaderWriter.h   ReaderWriter.h 
skipping to change at line 73 skipping to change at line 73
/// should be in "binary" mode. /// should be in "binary" mode.
void WriteBitcodeToFile(const Module *M, raw_ostream &Out); void WriteBitcodeToFile(const Module *M, raw_ostream &Out);
/// createBitcodeWriterPass - Create and return a pass that writes the mo dule /// createBitcodeWriterPass - Create and return a pass that writes the mo dule
/// to the specified ostream. /// to the specified ostream.
ModulePass *createBitcodeWriterPass(raw_ostream &Str); ModulePass *createBitcodeWriterPass(raw_ostream &Str);
/// isBitcodeWrapper - Return true if the given bytes are the magic bytes /// isBitcodeWrapper - Return true if the given bytes are the magic bytes
/// for an LLVM IR bitcode wrapper. /// for an LLVM IR bitcode wrapper.
/// ///
static inline bool isBitcodeWrapper(const unsigned char *BufPtr, inline bool isBitcodeWrapper(const unsigned char *BufPtr,
const unsigned char *BufEnd) { const unsigned char *BufEnd) {
// See if you can find the hidden message in the magic bytes :-). // See if you can find the hidden message in the magic bytes :-).
// (Hint: it's a little-endian encoding.) // (Hint: it's a little-endian encoding.)
return BufPtr != BufEnd && return BufPtr != BufEnd &&
BufPtr[0] == 0xDE && BufPtr[0] == 0xDE &&
BufPtr[1] == 0xC0 && BufPtr[1] == 0xC0 &&
BufPtr[2] == 0x17 && BufPtr[2] == 0x17 &&
BufPtr[3] == 0x0B; BufPtr[3] == 0x0B;
} }
/// isRawBitcode - Return true if the given bytes are the magic bytes for /// isRawBitcode - Return true if the given bytes are the magic bytes for
/// raw LLVM IR bitcode (without a wrapper). /// raw LLVM IR bitcode (without a wrapper).
/// ///
static inline bool isRawBitcode(const unsigned char *BufPtr, inline bool isRawBitcode(const unsigned char *BufPtr,
const unsigned char *BufEnd) { const unsigned char *BufEnd) {
// These bytes sort of have a hidden message, but it's not in // These bytes sort of have a hidden message, but it's not in
// little-endian this time, and it's a little redundant. // little-endian this time, and it's a little redundant.
return BufPtr != BufEnd && return BufPtr != BufEnd &&
BufPtr[0] == 'B' && BufPtr[0] == 'B' &&
BufPtr[1] == 'C' && BufPtr[1] == 'C' &&
BufPtr[2] == 0xc0 && BufPtr[2] == 0xc0 &&
BufPtr[3] == 0xde; BufPtr[3] == 0xde;
} }
/// isBitcode - Return true if the given bytes are the magic bytes for /// isBitcode - Return true if the given bytes are the magic bytes for
/// LLVM IR bitcode, either with or without a wrapper. /// LLVM IR bitcode, either with or without a wrapper.
/// ///
static bool inline isBitcode(const unsigned char *BufPtr, inline bool isBitcode(const unsigned char *BufPtr,
const unsigned char *BufEnd) { const unsigned char *BufEnd) {
return isBitcodeWrapper(BufPtr, BufEnd) || return isBitcodeWrapper(BufPtr, BufEnd) ||
isRawBitcode(BufPtr, BufEnd); isRawBitcode(BufPtr, BufEnd);
} }
/// SkipBitcodeWrapperHeader - Some systems wrap bc files with a special /// SkipBitcodeWrapperHeader - Some systems wrap bc files with a special
/// header for padding or other reasons. The format of this header is: /// header for padding or other reasons. The format of this header is:
/// ///
/// struct bc_header { /// struct bc_header {
/// uint32_t Magic; // 0x0B17C0DE /// uint32_t Magic; // 0x0B17C0DE
/// uint32_t Version; // Version, currently always 0. /// uint32_t Version; // Version, currently always 0.
/// uint32_t BitcodeOffset; // Offset to traditional bitcode file. /// uint32_t BitcodeOffset; // Offset to traditional bitcode file.
/// uint32_t BitcodeSize; // Size of traditional bitcode file. /// uint32_t BitcodeSize; // Size of traditional bitcode file.
/// ... potentially other gunk ... /// ... potentially other gunk ...
/// }; /// };
/// ///
/// This function is called when we find a file with a matching magic num ber. /// This function is called when we find a file with a matching magic num ber.
/// In this case, skip down to the subsection of the file that is actuall y a /// In this case, skip down to the subsection of the file that is actuall y a
/// BC file. /// BC file.
/// If 'VerifyBufferSize' is true, check that the buffer is large enough to /// If 'VerifyBufferSize' is true, check that the buffer is large enough to
/// contain the whole bitcode file. /// contain the whole bitcode file.
static inline bool SkipBitcodeWrapperHeader(const unsigned char *&BufPtr, inline bool SkipBitcodeWrapperHeader(const unsigned char *&BufPtr,
const unsigned char *&BufEnd, const unsigned char *&BufEnd,
bool VerifyBufferSize) { bool VerifyBufferSize) {
enum { enum {
KnownHeaderSize = 4*4, // Size of header we read. KnownHeaderSize = 4*4, // Size of header we read.
OffsetField = 2*4, // Offset in bytes to Offset field. OffsetField = 2*4, // Offset in bytes to Offset field.
SizeField = 3*4 // Offset in bytes to Size field. SizeField = 3*4 // Offset in bytes to Size field.
}; };
// Must contain the header! // Must contain the header!
if (BufEnd-BufPtr < KnownHeaderSize) return true; if (BufEnd-BufPtr < KnownHeaderSize) return true;
unsigned Offset = ( BufPtr[OffsetField ] | unsigned Offset = ( BufPtr[OffsetField ] |
 End of changes. 4 change blocks. 
9 lines changed or deleted 9 lines changed or added


 Record.h   Record.h 
skipping to change at line 21 skipping to change at line 21
// types, values, and high-level data structures. // types, values, and high-level data structures.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_TABLEGEN_RECORD_H #ifndef LLVM_TABLEGEN_RECORD_H
#define LLVM_TABLEGEN_RECORD_H #define LLVM_TABLEGEN_RECORD_H
#include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/FoldingSet.h" #include "llvm/ADT/FoldingSet.h"
#include "llvm/Support/Allocator.h" #include "llvm/Support/Allocator.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/SourceMgr.h" #include "llvm/Support/SourceMgr.h"
#include "llvm/Support/DataTypes.h" #include "llvm/Support/DataTypes.h"
#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h" #include "llvm/Support/raw_ostream.h"
#include <map> #include <map>
namespace llvm { namespace llvm {
class raw_ostream; class raw_ostream;
// RecTy subclasses. // RecTy subclasses.
skipping to change at line 69 skipping to change at line 70
class Record; class Record;
class RecordVal; class RecordVal;
struct MultiClass; struct MultiClass;
class RecordKeeper; class RecordKeeper;
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// Type Classes // Type Classes
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
class RecTy { class RecTy {
public:
/// \brief Subclass discriminator (for dyn_cast<> et al.)
enum RecTyKind {
BitRecTyKind,
BitsRecTyKind,
IntRecTyKind,
StringRecTyKind,
ListRecTyKind,
DagRecTyKind,
RecordRecTyKind
};
private:
RecTyKind Kind;
ListRecTy *ListTy; ListRecTy *ListTy;
virtual void anchor(); virtual void anchor();
public: public:
RecTy() : ListTy(0) {} RecTyKind getRecTyKind() const { return Kind; }
RecTy(RecTyKind K) : Kind(K), ListTy(0) {}
virtual ~RecTy() {} virtual ~RecTy() {}
virtual std::string getAsString() const = 0; virtual std::string getAsString() const = 0;
void print(raw_ostream &OS) const { OS << getAsString(); } void print(raw_ostream &OS) const { OS << getAsString(); }
void dump() const; void dump() const;
/// typeIsConvertibleTo - Return true if all values of 'this' type can be /// typeIsConvertibleTo - Return true if all values of 'this' type can be
/// converted to the specified type. /// converted to the specified type.
virtual bool typeIsConvertibleTo(const RecTy *RHS) const = 0; virtual bool typeIsConvertibleTo(const RecTy *RHS) const = 0;
skipping to change at line 134 skipping to change at line 152
inline raw_ostream &operator<<(raw_ostream &OS, const RecTy &Ty) { inline raw_ostream &operator<<(raw_ostream &OS, const RecTy &Ty) {
Ty.print(OS); Ty.print(OS);
return OS; return OS;
} }
/// BitRecTy - 'bit' - Represent a single bit /// BitRecTy - 'bit' - Represent a single bit
/// ///
class BitRecTy : public RecTy { class BitRecTy : public RecTy {
static BitRecTy Shared; static BitRecTy Shared;
BitRecTy() {} BitRecTy() : RecTy(BitRecTyKind) {}
public: public:
static bool classof(const RecTy *RT) {
return RT->getRecTyKind() == BitRecTyKind;
}
static BitRecTy *get() { return &Shared; } static BitRecTy *get() { return &Shared; }
virtual Init *convertValue( UnsetInit *UI) { return (Init*)UI; } virtual Init *convertValue( UnsetInit *UI) { return (Init*)UI; }
virtual Init *convertValue( BitInit *BI) { return (Init*)BI; } virtual Init *convertValue( BitInit *BI) { return (Init*)BI; }
virtual Init *convertValue( BitsInit *BI); virtual Init *convertValue( BitsInit *BI);
virtual Init *convertValue( IntInit *II); virtual Init *convertValue( IntInit *II);
virtual Init *convertValue(StringInit *SI) { return 0; } virtual Init *convertValue(StringInit *SI) { return 0; }
virtual Init *convertValue( ListInit *LI) { return 0; } virtual Init *convertValue( ListInit *LI) { return 0; }
virtual Init *convertValue(VarBitInit *VB) { return (Init*)VB; } virtual Init *convertValue(VarBitInit *VB) { return (Init*)VB; }
virtual Init *convertValue( DefInit *DI) { return 0; } virtual Init *convertValue( DefInit *DI) { return 0; }
virtual Init *convertValue( DagInit *DI) { return 0; } virtual Init *convertValue( DagInit *DI) { return 0; }
virtual Init *convertValue( UnOpInit *UI) { return RecTy::convertValue(UI );} virtual Init *convertValue( UnOpInit *UI) { return RecTy::convertValue(UI );}
virtual Init *convertValue( BinOpInit *UI) { return RecTy::convertValue(U I);} virtual Init *convertValue( BinOpInit *UI) { return RecTy::convertValue(U I);}
virtual Init *convertValue( TernOpInit *UI) { return RecTy::convertValue( UI);} virtual Init *convertValue( TernOpInit *UI) { return RecTy::convertValue( UI);}
virtual Init *convertValue( TypedInit *TI); virtual Init *convertValue( TypedInit *TI);
virtual Init *convertValue( VarInit *VI) { return RecTy::convertValue(V I);} virtual Init *convertValue( VarInit *VI) { return RecTy::convertValue(V I);}
virtual Init *convertValue( FieldInit *FI) { return RecTy::convertValue(F I);} virtual Init *convertValue( FieldInit *FI) { return RecTy::convertValue(F I);}
std::string getAsString() const { return "bit"; } virtual std::string getAsString() const { return "bit"; }
bool typeIsConvertibleTo(const RecTy *RHS) const { virtual bool typeIsConvertibleTo(const RecTy *RHS) const {
return RHS->baseClassOf(this); return RHS->baseClassOf(this);
} }
virtual bool baseClassOf(const BitRecTy *RHS) const { return true; } virtual bool baseClassOf(const BitRecTy *RHS) const { return true; }
virtual bool baseClassOf(const BitsRecTy *RHS) const; virtual bool baseClassOf(const BitsRecTy *RHS) const;
virtual bool baseClassOf(const IntRecTy *RHS) const { return true; } virtual bool baseClassOf(const IntRecTy *RHS) const { return true; }
virtual bool baseClassOf(const StringRecTy *RHS) const { return false; } virtual bool baseClassOf(const StringRecTy *RHS) const { return false; }
virtual bool baseClassOf(const ListRecTy *RHS) const { return false; } virtual bool baseClassOf(const ListRecTy *RHS) const { return false; }
virtual bool baseClassOf(const DagRecTy *RHS) const { return false; } virtual bool baseClassOf(const DagRecTy *RHS) const { return false; }
virtual bool baseClassOf(const RecordRecTy *RHS) const { return false; } virtual bool baseClassOf(const RecordRecTy *RHS) const { return false; }
}; };
// BitsRecTy - 'bits<n>' - Represent a fixed number of bits // BitsRecTy - 'bits<n>' - Represent a fixed number of bits
/// BitsRecTy - 'bits&lt;n&gt;' - Represent a fixed number of bits /// BitsRecTy - 'bits&lt;n&gt;' - Represent a fixed number of bits
/// ///
class BitsRecTy : public RecTy { class BitsRecTy : public RecTy {
unsigned Size; unsigned Size;
explicit BitsRecTy(unsigned Sz) : Size(Sz) {} explicit BitsRecTy(unsigned Sz) : RecTy(BitsRecTyKind), Size(Sz) {}
public: public:
static bool classof(const RecTy *RT) {
return RT->getRecTyKind() == BitsRecTyKind;
}
static BitsRecTy *get(unsigned Sz); static BitsRecTy *get(unsigned Sz);
unsigned getNumBits() const { return Size; } unsigned getNumBits() const { return Size; }
virtual Init *convertValue( UnsetInit *UI); virtual Init *convertValue( UnsetInit *UI);
virtual Init *convertValue( BitInit *UI); virtual Init *convertValue( BitInit *UI);
virtual Init *convertValue( BitsInit *BI); virtual Init *convertValue( BitsInit *BI);
virtual Init *convertValue( IntInit *II); virtual Init *convertValue( IntInit *II);
virtual Init *convertValue(StringInit *SI) { return 0; } virtual Init *convertValue(StringInit *SI) { return 0; }
virtual Init *convertValue( ListInit *LI) { return 0; } virtual Init *convertValue( ListInit *LI) { return 0; }
virtual Init *convertValue(VarBitInit *VB) { return 0; } virtual Init *convertValue(VarBitInit *VB) { return 0; }
virtual Init *convertValue( DefInit *DI) { return 0; } virtual Init *convertValue( DefInit *DI) { return 0; }
virtual Init *convertValue( DagInit *DI) { return 0; } virtual Init *convertValue( DagInit *DI) { return 0; }
virtual Init *convertValue( UnOpInit *UI) { return RecTy::convertValue(UI );} virtual Init *convertValue( UnOpInit *UI) { return RecTy::convertValue(UI );}
virtual Init *convertValue( BinOpInit *UI) { return RecTy::convertValue(U I);} virtual Init *convertValue( BinOpInit *UI) { return RecTy::convertValue(U I);}
virtual Init *convertValue( TernOpInit *UI) { return RecTy::convertValue( UI);} virtual Init *convertValue( TernOpInit *UI) { return RecTy::convertValue( UI);}
virtual Init *convertValue( TypedInit *TI); virtual Init *convertValue( TypedInit *TI);
virtual Init *convertValue( VarInit *VI) { return RecTy::convertValue(V I);} virtual Init *convertValue( VarInit *VI) { return RecTy::convertValue(V I);}
virtual Init *convertValue( FieldInit *FI) { return RecTy::convertValue(F I);} virtual Init *convertValue( FieldInit *FI) { return RecTy::convertValue(F I);}
std::string getAsString() const; virtual std::string getAsString() const;
bool typeIsConvertibleTo(const RecTy *RHS) const { virtual bool typeIsConvertibleTo(const RecTy *RHS) const {
return RHS->baseClassOf(this); return RHS->baseClassOf(this);
} }
virtual bool baseClassOf(const BitRecTy *RHS) const { return Size == 1 ; } virtual bool baseClassOf(const BitRecTy *RHS) const { return Size == 1 ; }
virtual bool baseClassOf(const BitsRecTy *RHS) const { virtual bool baseClassOf(const BitsRecTy *RHS) const {
return RHS->Size == Size; return RHS->Size == Size;
} }
virtual bool baseClassOf(const IntRecTy *RHS) const { return true; } virtual bool baseClassOf(const IntRecTy *RHS) const { return true; }
virtual bool baseClassOf(const StringRecTy *RHS) const { return false; } virtual bool baseClassOf(const StringRecTy *RHS) const { return false; }
virtual bool baseClassOf(const ListRecTy *RHS) const { return false; } virtual bool baseClassOf(const ListRecTy *RHS) const { return false; }
virtual bool baseClassOf(const DagRecTy *RHS) const { return false; } virtual bool baseClassOf(const DagRecTy *RHS) const { return false; }
virtual bool baseClassOf(const RecordRecTy *RHS) const { return false; } virtual bool baseClassOf(const RecordRecTy *RHS) const { return false; }
}; };
/// IntRecTy - 'int' - Represent an integer value of no particular size /// IntRecTy - 'int' - Represent an integer value of no particular size
/// ///
class IntRecTy : public RecTy { class IntRecTy : public RecTy {
static IntRecTy Shared; static IntRecTy Shared;
IntRecTy() {} IntRecTy() : RecTy(IntRecTyKind) {}
public: public:
static bool classof(const RecTy *RT) {
return RT->getRecTyKind() == IntRecTyKind;
}
static IntRecTy *get() { return &Shared; } static IntRecTy *get() { return &Shared; }
virtual Init *convertValue( UnsetInit *UI) { return (Init*)UI; } virtual Init *convertValue( UnsetInit *UI) { return (Init*)UI; }
virtual Init *convertValue( BitInit *BI); virtual Init *convertValue( BitInit *BI);
virtual Init *convertValue( BitsInit *BI); virtual Init *convertValue( BitsInit *BI);
virtual Init *convertValue( IntInit *II) { return (Init*)II; } virtual Init *convertValue( IntInit *II) { return (Init*)II; }
virtual Init *convertValue(StringInit *SI) { return 0; } virtual Init *convertValue(StringInit *SI) { return 0; }
virtual Init *convertValue( ListInit *LI) { return 0; } virtual Init *convertValue( ListInit *LI) { return 0; }
virtual Init *convertValue(VarBitInit *VB) { return 0; } virtual Init *convertValue(VarBitInit *VB) { return 0; }
virtual Init *convertValue( DefInit *DI) { return 0; } virtual Init *convertValue( DefInit *DI) { return 0; }
virtual Init *convertValue( DagInit *DI) { return 0; } virtual Init *convertValue( DagInit *DI) { return 0; }
virtual Init *convertValue( UnOpInit *UI) { return RecTy::convertValue(UI );} virtual Init *convertValue( UnOpInit *UI) { return RecTy::convertValue(UI );}
virtual Init *convertValue( BinOpInit *UI) { return RecTy::convertValue(U I);} virtual Init *convertValue( BinOpInit *UI) { return RecTy::convertValue(U I);}
virtual Init *convertValue( TernOpInit *UI) { return RecTy::convertValue( UI);} virtual Init *convertValue( TernOpInit *UI) { return RecTy::convertValue( UI);}
virtual Init *convertValue( TypedInit *TI); virtual Init *convertValue( TypedInit *TI);
virtual Init *convertValue( VarInit *VI) { return RecTy::convertValue(V I);} virtual Init *convertValue( VarInit *VI) { return RecTy::convertValue(V I);}
virtual Init *convertValue( FieldInit *FI) { return RecTy::convertValue(F I);} virtual Init *convertValue( FieldInit *FI) { return RecTy::convertValue(F I);}
std::string getAsString() const { return "int"; } virtual std::string getAsString() const { return "int"; }
bool typeIsConvertibleTo(const RecTy *RHS) const { virtual bool typeIsConvertibleTo(const RecTy *RHS) const {
return RHS->baseClassOf(this); return RHS->baseClassOf(this);
} }
virtual bool baseClassOf(const BitRecTy *RHS) const { return true; } virtual bool baseClassOf(const BitRecTy *RHS) const { return true; }
virtual bool baseClassOf(const BitsRecTy *RHS) const { return true; } virtual bool baseClassOf(const BitsRecTy *RHS) const { return true; }
virtual bool baseClassOf(const IntRecTy *RHS) const { return true; } virtual bool baseClassOf(const IntRecTy *RHS) const { return true; }
virtual bool baseClassOf(const StringRecTy *RHS) const { return false; } virtual bool baseClassOf(const StringRecTy *RHS) const { return false; }
virtual bool baseClassOf(const ListRecTy *RHS) const { return false; } virtual bool baseClassOf(const ListRecTy *RHS) const { return false; }
virtual bool baseClassOf(const DagRecTy *RHS) const { return false; } virtual bool baseClassOf(const DagRecTy *RHS) const { return false; }
virtual bool baseClassOf(const RecordRecTy *RHS) const { return false; } virtual bool baseClassOf(const RecordRecTy *RHS) const { return false; }
}; };
/// StringRecTy - 'string' - Represent an string value /// StringRecTy - 'string' - Represent an string value
/// ///
class StringRecTy : public RecTy { class StringRecTy : public RecTy {
static StringRecTy Shared; static StringRecTy Shared;
StringRecTy() {} StringRecTy() : RecTy(StringRecTyKind) {}
public: public:
static bool classof(const RecTy *RT) {
return RT->getRecTyKind() == StringRecTyKind;
}
static StringRecTy *get() { return &Shared; } static StringRecTy *get() { return &Shared; }
virtual Init *convertValue( UnsetInit *UI) { return (Init*)UI; } virtual Init *convertValue( UnsetInit *UI) { return (Init*)UI; }
virtual Init *convertValue( BitInit *BI) { return 0; } virtual Init *convertValue( BitInit *BI) { return 0; }
virtual Init *convertValue( BitsInit *BI) { return 0; } virtual Init *convertValue( BitsInit *BI) { return 0; }
virtual Init *convertValue( IntInit *II) { return 0; } virtual Init *convertValue( IntInit *II) { return 0; }
virtual Init *convertValue(StringInit *SI) { return (Init*)SI; } virtual Init *convertValue(StringInit *SI) { return (Init*)SI; }
virtual Init *convertValue( ListInit *LI) { return 0; } virtual Init *convertValue( ListInit *LI) { return 0; }
virtual Init *convertValue( UnOpInit *BO); virtual Init *convertValue( UnOpInit *BO);
virtual Init *convertValue( BinOpInit *BO); virtual Init *convertValue( BinOpInit *BO);
virtual Init *convertValue( TernOpInit *BO) { return RecTy::convertValue( BO);} virtual Init *convertValue( TernOpInit *BO) { return RecTy::convertValue( BO);}
virtual Init *convertValue(VarBitInit *VB) { return 0; } virtual Init *convertValue(VarBitInit *VB) { return 0; }
virtual Init *convertValue( DefInit *DI) { return 0; } virtual Init *convertValue( DefInit *DI) { return 0; }
virtual Init *convertValue( DagInit *DI) { return 0; } virtual Init *convertValue( DagInit *DI) { return 0; }
virtual Init *convertValue( TypedInit *TI); virtual Init *convertValue( TypedInit *TI);
virtual Init *convertValue( VarInit *VI) { return RecTy::convertValue(V I);} virtual Init *convertValue( VarInit *VI) { return RecTy::convertValue(V I);}
virtual Init *convertValue( FieldInit *FI) { return RecTy::convertValue(F I);} virtual Init *convertValue( FieldInit *FI) { return RecTy::convertValue(F I);}
std::string getAsString() const { return "string"; } virtual std::string getAsString() const { return "string"; }
bool typeIsConvertibleTo(const RecTy *RHS) const { virtual bool typeIsConvertibleTo(const RecTy *RHS) const {
return RHS->baseClassOf(this); return RHS->baseClassOf(this);
} }
virtual bool baseClassOf(const BitRecTy *RHS) const { return false; } virtual bool baseClassOf(const BitRecTy *RHS) const { return false; }
virtual bool baseClassOf(const BitsRecTy *RHS) const { return false; } virtual bool baseClassOf(const BitsRecTy *RHS) const { return false; }
virtual bool baseClassOf(const IntRecTy *RHS) const { return false; } virtual bool baseClassOf(const IntRecTy *RHS) const { return false; }
virtual bool baseClassOf(const StringRecTy *RHS) const { return true; } virtual bool baseClassOf(const StringRecTy *RHS) const { return true; }
virtual bool baseClassOf(const ListRecTy *RHS) const { return false; } virtual bool baseClassOf(const ListRecTy *RHS) const { return false; }
virtual bool baseClassOf(const DagRecTy *RHS) const { return false; } virtual bool baseClassOf(const DagRecTy *RHS) const { return false; }
virtual bool baseClassOf(const RecordRecTy *RHS) const { return false; } virtual bool baseClassOf(const RecordRecTy *RHS) const { return false; }
}; };
// ListRecTy - 'list<Ty>' - Represent a list of values, all of which must b e of // ListRecTy - 'list<Ty>' - Represent a list of values, all of which must b e of
// the specified type. // the specified type.
/// ListRecTy - 'list&lt;Ty&gt;' - Represent a list of values, all of which must /// ListRecTy - 'list&lt;Ty&gt;' - Represent a list of values, all of which must
/// be of the specified type. /// be of the specified type.
/// ///
class ListRecTy : public RecTy { class ListRecTy : public RecTy {
RecTy *Ty; RecTy *Ty;
explicit ListRecTy(RecTy *T) : Ty(T) {} explicit ListRecTy(RecTy *T) : RecTy(ListRecTyKind), Ty(T) {}
friend ListRecTy *RecTy::getListTy(); friend ListRecTy *RecTy::getListTy();
public: public:
static bool classof(const RecTy *RT) {
return RT->getRecTyKind() == ListRecTyKind;
}
static ListRecTy *get(RecTy *T) { return T->getListTy(); } static ListRecTy *get(RecTy *T) { return T->getListTy(); }
RecTy *getElementType() const { return Ty; } RecTy *getElementType() const { return Ty; }
virtual Init *convertValue( UnsetInit *UI) { return (Init*)UI; } virtual Init *convertValue( UnsetInit *UI) { return (Init*)UI; }
virtual Init *convertValue( BitInit *BI) { return 0; } virtual Init *convertValue( BitInit *BI) { return 0; }
virtual Init *convertValue( BitsInit *BI) { return 0; } virtual Init *convertValue( BitsInit *BI) { return 0; }
virtual Init *convertValue( IntInit *II) { return 0; } virtual Init *convertValue( IntInit *II) { return 0; }
virtual Init *convertValue(StringInit *SI) { return 0; } virtual Init *convertValue(StringInit *SI) { return 0; }
virtual Init *convertValue( ListInit *LI); virtual Init *convertValue( ListInit *LI);
virtual Init *convertValue(VarBitInit *VB) { return 0; } virtual Init *convertValue(VarBitInit *VB) { return 0; }
virtual Init *convertValue( DefInit *DI) { return 0; } virtual Init *convertValue( DefInit *DI) { return 0; }
virtual Init *convertValue( DagInit *DI) { return 0; } virtual Init *convertValue( DagInit *DI) { return 0; }
virtual Init *convertValue( UnOpInit *UI) { return RecTy::convertValue(UI );} virtual Init *convertValue( UnOpInit *UI) { return RecTy::convertValue(UI );}
virtual Init *convertValue( BinOpInit *UI) { return RecTy::convertValue(U I);} virtual Init *convertValue( BinOpInit *UI) { return RecTy::convertValue(U I);}
virtual Init *convertValue( TernOpInit *UI) { return RecTy::convertValue( UI);} virtual Init *convertValue( TernOpInit *UI) { return RecTy::convertValue( UI);}
virtual Init *convertValue( TypedInit *TI); virtual Init *convertValue( TypedInit *TI);
virtual Init *convertValue( VarInit *VI) { return RecTy::convertValue(V I);} virtual Init *convertValue( VarInit *VI) { return RecTy::convertValue(V I);}
virtual Init *convertValue( FieldInit *FI) { return RecTy::convertValue(F I);} virtual Init *convertValue( FieldInit *FI) { return RecTy::convertValue(F I);}
std::string getAsString() const; virtual std::string getAsString() const;
bool typeIsConvertibleTo(const RecTy *RHS) const { virtual bool typeIsConvertibleTo(const RecTy *RHS) const {
return RHS->baseClassOf(this); return RHS->baseClassOf(this);
} }
virtual bool baseClassOf(const BitRecTy *RHS) const { return false; } virtual bool baseClassOf(const BitRecTy *RHS) const { return false; }
virtual bool baseClassOf(const BitsRecTy *RHS) const { return false; } virtual bool baseClassOf(const BitsRecTy *RHS) const { return false; }
virtual bool baseClassOf(const IntRecTy *RHS) const { return false; } virtual bool baseClassOf(const IntRecTy *RHS) const { return false; }
virtual bool baseClassOf(const StringRecTy *RHS) const { return false; } virtual bool baseClassOf(const StringRecTy *RHS) const { return false; }
virtual bool baseClassOf(const ListRecTy *RHS) const { virtual bool baseClassOf(const ListRecTy *RHS) const {
return RHS->getElementType()->typeIsConvertibleTo(Ty); return RHS->getElementType()->typeIsConvertibleTo(Ty);
} }
virtual bool baseClassOf(const DagRecTy *RHS) const { return false; } virtual bool baseClassOf(const DagRecTy *RHS) const { return false; }
virtual bool baseClassOf(const RecordRecTy *RHS) const { return false; } virtual bool baseClassOf(const RecordRecTy *RHS) const { return false; }
}; };
/// DagRecTy - 'dag' - Represent a dag fragment /// DagRecTy - 'dag' - Represent a dag fragment
/// ///
class DagRecTy : public RecTy { class DagRecTy : public RecTy {
static DagRecTy Shared; static DagRecTy Shared;
DagRecTy() {} DagRecTy() : RecTy(DagRecTyKind) {}
public: public:
static bool classof(const RecTy *RT) {
return RT->getRecTyKind() == DagRecTyKind;
}
static DagRecTy *get() { return &Shared; } static DagRecTy *get() { return &Shared; }
virtual Init *convertValue( UnsetInit *UI) { return (Init*)UI; } virtual Init *convertValue( UnsetInit *UI) { return (Init*)UI; }
virtual Init *convertValue( BitInit *BI) { return 0; } virtual Init *convertValue( BitInit *BI) { return 0; }
virtual Init *convertValue( BitsInit *BI) { return 0; } virtual Init *convertValue( BitsInit *BI) { return 0; }
virtual Init *convertValue( IntInit *II) { return 0; } virtual Init *convertValue( IntInit *II) { return 0; }
virtual Init *convertValue(StringInit *SI) { return 0; } virtual Init *convertValue(StringInit *SI) { return 0; }
virtual Init *convertValue( ListInit *LI) { return 0; } virtual Init *convertValue( ListInit *LI) { return 0; }
virtual Init *convertValue(VarBitInit *VB) { return 0; } virtual Init *convertValue(VarBitInit *VB) { return 0; }
virtual Init *convertValue( DefInit *DI) { return 0; } virtual Init *convertValue( DefInit *DI) { return 0; }
virtual Init *convertValue( UnOpInit *BO); virtual Init *convertValue( UnOpInit *BO);
virtual Init *convertValue( BinOpInit *BO); virtual Init *convertValue( BinOpInit *BO);
virtual Init *convertValue( TernOpInit *BO) { return RecTy::convertValue( BO);} virtual Init *convertValue( TernOpInit *BO) { return RecTy::convertValue( BO);}
virtual Init *convertValue( DagInit *CI) { return (Init*)CI; } virtual Init *convertValue( DagInit *CI) { return (Init*)CI; }
virtual Init *convertValue( TypedInit *TI); virtual Init *convertValue( TypedInit *TI);
virtual Init *convertValue( VarInit *VI) { return RecTy::convertValue(V I);} virtual Init *convertValue( VarInit *VI) { return RecTy::convertValue(V I);}
virtual Init *convertValue( FieldInit *FI) { return RecTy::convertValue(F I);} virtual Init *convertValue( FieldInit *FI) { return RecTy::convertValue(F I);}
std::string getAsString() const { return "dag"; } virtual std::string getAsString() const { return "dag"; }
bool typeIsConvertibleTo(const RecTy *RHS) const { virtual bool typeIsConvertibleTo(const RecTy *RHS) const {
return RHS->baseClassOf(this); return RHS->baseClassOf(this);
} }
virtual bool baseClassOf(const BitRecTy *RHS) const { return false; } virtual bool baseClassOf(const BitRecTy *RHS) const { return false; }
virtual bool baseClassOf(const BitsRecTy *RHS) const { return false; } virtual bool baseClassOf(const BitsRecTy *RHS) const { return false; }
virtual bool baseClassOf(const IntRecTy *RHS) const { return false; } virtual bool baseClassOf(const IntRecTy *RHS) const { return false; }
virtual bool baseClassOf(const StringRecTy *RHS) const { return false; } virtual bool baseClassOf(const StringRecTy *RHS) const { return false; }
virtual bool baseClassOf(const ListRecTy *RHS) const { return false; } virtual bool baseClassOf(const ListRecTy *RHS) const { return false; }
virtual bool baseClassOf(const DagRecTy *RHS) const { return true; } virtual bool baseClassOf(const DagRecTy *RHS) const { return true; }
virtual bool baseClassOf(const RecordRecTy *RHS) const { return false; } virtual bool baseClassOf(const RecordRecTy *RHS) const { return false; }
}; };
/// RecordRecTy - '[classname]' - Represent an instance of a class, such as : /// RecordRecTy - '[classname]' - Represent an instance of a class, such as :
/// (R32 X = EAX). /// (R32 X = EAX).
/// ///
class RecordRecTy : public RecTy { class RecordRecTy : public RecTy {
Record *Rec; Record *Rec;
explicit RecordRecTy(Record *R) : Rec(R) {} explicit RecordRecTy(Record *R) : RecTy(RecordRecTyKind), Rec(R) {}
friend class Record; friend class Record;
public: public:
static bool classof(const RecTy *RT) {
return RT->getRecTyKind() == RecordRecTyKind;
}
static RecordRecTy *get(Record *R); static RecordRecTy *get(Record *R);
Record *getRecord() const { return Rec; } Record *getRecord() const { return Rec; }
virtual Init *convertValue( UnsetInit *UI) { return (Init*)UI; } virtual Init *convertValue( UnsetInit *UI) { return (Init*)UI; }
virtual Init *convertValue( BitInit *BI) { return 0; } virtual Init *convertValue( BitInit *BI) { return 0; }
virtual Init *convertValue( BitsInit *BI) { return 0; } virtual Init *convertValue( BitsInit *BI) { return 0; }
virtual Init *convertValue( IntInit *II) { return 0; } virtual Init *convertValue( IntInit *II) { return 0; }
virtual Init *convertValue(StringInit *SI) { return 0; } virtual Init *convertValue(StringInit *SI) { return 0; }
virtual Init *convertValue( ListInit *LI) { return 0; } virtual Init *convertValue( ListInit *LI) { return 0; }
virtual Init *convertValue(VarBitInit *VB) { return 0; } virtual Init *convertValue(VarBitInit *VB) { return 0; }
virtual Init *convertValue( UnOpInit *UI) { return RecTy::convertValue(UI );} virtual Init *convertValue( UnOpInit *UI) { return RecTy::convertValue(UI );}
virtual Init *convertValue( BinOpInit *UI) { return RecTy::convertValue(U I);} virtual Init *convertValue( BinOpInit *UI) { return RecTy::convertValue(U I);}
virtual Init *convertValue( TernOpInit *UI) { return RecTy::convertValue( UI);} virtual Init *convertValue( TernOpInit *UI) { return RecTy::convertValue( UI);}
virtual Init *convertValue( DefInit *DI); virtual Init *convertValue( DefInit *DI);
virtual Init *convertValue( DagInit *DI) { return 0; } virtual Init *convertValue( DagInit *DI) { return 0; }
virtual Init *convertValue( TypedInit *VI); virtual Init *convertValue( TypedInit *VI);
virtual Init *convertValue( VarInit *VI) { return RecTy::convertValue(V I);} virtual Init *convertValue( VarInit *VI) { return RecTy::convertValue(V I);}
virtual Init *convertValue( FieldInit *FI) { return RecTy::convertValue(F I);} virtual Init *convertValue( FieldInit *FI) { return RecTy::convertValue(F I);}
std::string getAsString() const; virtual std::string getAsString() const;
bool typeIsConvertibleTo(const RecTy *RHS) const { virtual bool typeIsConvertibleTo(const RecTy *RHS) const {
return RHS->baseClassOf(this); return RHS->baseClassOf(this);
} }
virtual bool baseClassOf(const BitRecTy *RHS) const { return false; } virtual bool baseClassOf(const BitRecTy *RHS) const { return false; }
virtual bool baseClassOf(const BitsRecTy *RHS) const { return false; } virtual bool baseClassOf(const BitsRecTy *RHS) const { return false; }
virtual bool baseClassOf(const IntRecTy *RHS) const { return false; } virtual bool baseClassOf(const IntRecTy *RHS) const { return false; }
virtual bool baseClassOf(const StringRecTy *RHS) const { return false; } virtual bool baseClassOf(const StringRecTy *RHS) const { return false; }
virtual bool baseClassOf(const ListRecTy *RHS) const { return false; } virtual bool baseClassOf(const ListRecTy *RHS) const { return false; }
virtual bool baseClassOf(const DagRecTy *RHS) const { return false; } virtual bool baseClassOf(const DagRecTy *RHS) const { return false; }
virtual bool baseClassOf(const RecordRecTy *RHS) const; virtual bool baseClassOf(const RecordRecTy *RHS) const;
}; };
skipping to change at line 430 skipping to change at line 476
/// resolveTypes - Find a common type that T1 and T2 convert to. /// resolveTypes - Find a common type that T1 and T2 convert to.
/// Return 0 if no such type exists. /// Return 0 if no such type exists.
/// ///
RecTy *resolveTypes(RecTy *T1, RecTy *T2); RecTy *resolveTypes(RecTy *T1, RecTy *T2);
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// Initializer Classes // Initializer Classes
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
class Init { class Init {
Init(const Init &); // Do not define. protected:
Init &operator=(const Init &); // Do not define. /// \brief Discriminator enum (for isa<>, dyn_cast<>, et al.)
///
/// This enum is laid out by a preorder traversal of the inheritance
/// hierarchy, and does not contain an entry for abstract classes, as per
/// the recommendation in docs/HowToSetUpLLVMStyleRTTI.rst.
///
/// We also explicitly include "first" and "last" values for each
/// interior node of the inheritance tree, to make it easier to read the
/// corresponding classof().
///
/// We could pack these a bit tighter by not having the IK_FirstXXXInit
/// and IK_LastXXXInit be their own values, but that would degrade
/// readability for really no benefit.
enum InitKind {
IK_BitInit,
IK_BitsInit,
IK_FirstTypedInit,
IK_DagInit,
IK_DefInit,
IK_FieldInit,
IK_IntInit,
IK_ListInit,
IK_FirstOpInit,
IK_BinOpInit,
IK_TernOpInit,
IK_UnOpInit,
IK_LastOpInit,
IK_StringInit,
IK_VarInit,
IK_VarListElementInit,
IK_LastTypedInit,
IK_UnsetInit,
IK_VarBitInit
};
private:
const InitKind Kind;
Init(const Init &) LLVM_DELETED_FUNCTION;
Init &operator=(const Init &) LLVM_DELETED_FUNCTION;
virtual void anchor(); virtual void anchor();
public:
InitKind getKind() const { return Kind; }
protected: protected:
Init(void) {} explicit Init(InitKind K) : Kind(K) {}
public: public:
virtual ~Init() {} virtual ~Init() {}
/// isComplete - This virtual method should be overridden by values that may /// isComplete - This virtual method should be overridden by values that may
/// not be completely specified yet. /// not be completely specified yet.
virtual bool isComplete() const { return true; } virtual bool isComplete() const { return true; }
/// print - Print out this value. /// print - Print out this value.
void print(raw_ostream &OS) const { OS << getAsString(); } void print(raw_ostream &OS) const { OS << getAsString(); }
skipping to change at line 508 skipping to change at line 595
} }
/// resolveReferences - This method is used by classes that refer to othe r /// resolveReferences - This method is used by classes that refer to othe r
/// variables which may not be defined at the time the expression is form ed. /// variables which may not be defined at the time the expression is form ed.
/// If a value is set for the variable later, this method will be called on /// If a value is set for the variable later, this method will be called on
/// users of the value to allow the value to propagate out. /// users of the value to allow the value to propagate out.
/// ///
virtual Init *resolveReferences(Record &R, const RecordVal *RV) const { virtual Init *resolveReferences(Record &R, const RecordVal *RV) const {
return const_cast<Init *>(this); return const_cast<Init *>(this);
} }
/// getBit - This method is used to return the initializer for the specif
ied
/// bit.
virtual Init *getBit(unsigned Bit) const = 0;
/// getBitVar - This method is used to retrieve the initializer for bit
/// reference. For non-VarBitInit, it simply returns itself.
virtual Init *getBitVar() const { return const_cast<Init*>(this); }
/// getBitNum - This method is used to retrieve the bit number of a bit
/// reference. For non-VarBitInit, it simply returns 0.
virtual unsigned getBitNum() const { return 0; }
}; };
inline raw_ostream &operator<<(raw_ostream &OS, const Init &I) { inline raw_ostream &operator<<(raw_ostream &OS, const Init &I) {
I.print(OS); return OS; I.print(OS); return OS;
} }
/// TypedInit - This is the common super-class of types that have a specifi c, /// TypedInit - This is the common super-class of types that have a specifi c,
/// explicit, type. /// explicit, type.
/// ///
class TypedInit : public Init { class TypedInit : public Init {
RecTy *Ty; RecTy *Ty;
TypedInit(const TypedInit &Other); // Do not define. TypedInit(const TypedInit &Other) LLVM_DELETED_FUNCTION;
TypedInit &operator=(const TypedInit &Other); // Do not define. TypedInit &operator=(const TypedInit &Other) LLVM_DELETED_FUNCTION;
protected: protected:
explicit TypedInit(RecTy *T) : Ty(T) {} explicit TypedInit(InitKind K, RecTy *T) : Init(K), Ty(T) {}
public: public:
static bool classof(const Init *I) {
return I->getKind() >= IK_FirstTypedInit &&
I->getKind() <= IK_LastTypedInit;
}
RecTy *getType() const { return Ty; } RecTy *getType() const { return Ty; }
virtual Init * virtual Init *
convertInitializerBitRange(const std::vector<unsigned> &Bits) const; convertInitializerBitRange(const std::vector<unsigned> &Bits) const;
virtual Init * virtual Init *
convertInitListSlice(const std::vector<unsigned> &Elements) const; convertInitListSlice(const std::vector<unsigned> &Elements) const;
/// getFieldType - This method is used to implement the FieldInit class. /// getFieldType - This method is used to implement the FieldInit class.
/// Implementors of this method should return the type of the named field if /// Implementors of this method should return the type of the named field if
/// they are of record type. /// they are of record type.
/// ///
virtual RecTy *getFieldType(const std::string &FieldName) const; virtual RecTy *getFieldType(const std::string &FieldName) const;
/// resolveBitReference - This method is used to implement
/// VarBitInit::resolveReferences. If the bit is able to be resolved, we
/// simply return the resolved value, otherwise we return null.
///
virtual Init *resolveBitReference(Record &R, const RecordVal *RV,
unsigned Bit) const = 0;
/// resolveListElementReference - This method is used to implement /// resolveListElementReference - This method is used to implement
/// VarListElementInit::resolveReferences. If the list element is resolv able /// VarListElementInit::resolveReferences. If the list element is resolv able
/// now, we return the resolved value, otherwise we return null. /// now, we return the resolved value, otherwise we return null.
virtual Init *resolveListElementReference(Record &R, const RecordVal *RV, virtual Init *resolveListElementReference(Record &R, const RecordVal *RV,
unsigned Elt) const = 0; unsigned Elt) const = 0;
}; };
/// UnsetInit - ? - Represents an uninitialized value /// UnsetInit - ? - Represents an uninitialized value
/// ///
class UnsetInit : public Init { class UnsetInit : public Init {
UnsetInit() : Init() {} UnsetInit() : Init(IK_UnsetInit) {}
UnsetInit(const UnsetInit &); // Do not define. UnsetInit(const UnsetInit &) LLVM_DELETED_FUNCTION;
UnsetInit &operator=(const UnsetInit &Other); // Do not define. UnsetInit &operator=(const UnsetInit &Other) LLVM_DELETED_FUNCTION;
virtual void anchor(); virtual void anchor();
public: public:
static bool classof(const Init *I) {
return I->getKind() == IK_UnsetInit;
}
static UnsetInit *get(); static UnsetInit *get();
virtual Init *convertInitializerTo(RecTy *Ty) const { virtual Init *convertInitializerTo(RecTy *Ty) const {
return Ty->convertValue(const_cast<UnsetInit *>(this)); return Ty->convertValue(const_cast<UnsetInit *>(this));
} }
virtual Init *getBit(unsigned Bit) const {
return const_cast<UnsetInit*>(this);
}
virtual bool isComplete() const { return false; } virtual bool isComplete() const { return false; }
virtual std::string getAsString() const { return "?"; } virtual std::string getAsString() const { return "?"; }
}; };
/// BitInit - true/false - Represent a concrete initializer for a bit. /// BitInit - true/false - Represent a concrete initializer for a bit.
/// ///
class BitInit : public Init { class BitInit : public Init {
bool Value; bool Value;
explicit BitInit(bool V) : Value(V) {} explicit BitInit(bool V) : Init(IK_BitInit), Value(V) {}
BitInit(const BitInit &Other); // Do not define. BitInit(const BitInit &Other) LLVM_DELETED_FUNCTION;
BitInit &operator=(BitInit &Other); // Do not define. BitInit &operator=(BitInit &Other) LLVM_DELETED_FUNCTION;
virtual void anchor(); virtual void anchor();
public: public:
static bool classof(const Init *I) {
return I->getKind() == IK_BitInit;
}
static BitInit *get(bool V); static BitInit *get(bool V);
bool getValue() const { return Value; } bool getValue() const { return Value; }
virtual Init *convertInitializerTo(RecTy *Ty) const { virtual Init *convertInitializerTo(RecTy *Ty) const {
return Ty->convertValue(const_cast<BitInit *>(this)); return Ty->convertValue(const_cast<BitInit *>(this));
} }
virtual Init *getBit(unsigned Bit) const {
assert(Bit < 1 && "Bit index out of range!");
return const_cast<BitInit*>(this);
}
virtual std::string getAsString() const { return Value ? "1" : "0"; } virtual std::string getAsString() const { return Value ? "1" : "0"; }
}; };
/// BitsInit - { a, b, c } - Represents an initializer for a BitsRecTy valu e. /// BitsInit - { a, b, c } - Represents an initializer for a BitsRecTy valu e.
/// It contains a vector of bits, whose size is determined by the type. /// It contains a vector of bits, whose size is determined by the type.
/// ///
class BitsInit : public Init, public FoldingSetNode { class BitsInit : public Init, public FoldingSetNode {
std::vector<Init*> Bits; std::vector<Init*> Bits;
BitsInit(ArrayRef<Init *> Range) : Bits(Range.begin(), Range.end()) {} BitsInit(ArrayRef<Init *> Range)
: Init(IK_BitsInit), Bits(Range.begin(), Range.end()) {}
BitsInit(const BitsInit &Other); // Do not define. BitsInit(const BitsInit &Other) LLVM_DELETED_FUNCTION;
BitsInit &operator=(const BitsInit &Other); // Do not define. BitsInit &operator=(const BitsInit &Other) LLVM_DELETED_FUNCTION;
public: public:
static bool classof(const Init *I) {
return I->getKind() == IK_BitsInit;
}
static BitsInit *get(ArrayRef<Init *> Range); static BitsInit *get(ArrayRef<Init *> Range);
void Profile(FoldingSetNodeID &ID) const; void Profile(FoldingSetNodeID &ID) const;
unsigned getNumBits() const { return Bits.size(); } unsigned getNumBits() const { return Bits.size(); }
Init *getBit(unsigned Bit) const {
assert(Bit < Bits.size() && "Bit index out of range!");
return Bits[Bit];
}
virtual Init *convertInitializerTo(RecTy *Ty) const { virtual Init *convertInitializerTo(RecTy *Ty) const {
return Ty->convertValue(const_cast<BitsInit *>(this)); return Ty->convertValue(const_cast<BitsInit *>(this));
} }
virtual Init * virtual Init *
convertInitializerBitRange(const std::vector<unsigned> &Bits) const; convertInitializerBitRange(const std::vector<unsigned> &Bits) const;
virtual bool isComplete() const { virtual bool isComplete() const {
for (unsigned i = 0; i != getNumBits(); ++i) for (unsigned i = 0; i != getNumBits(); ++i)
if (!getBit(i)->isComplete()) return false; if (!getBit(i)->isComplete()) return false;
return true; return true;
} }
bool allInComplete() const { bool allInComplete() const {
for (unsigned i = 0; i != getNumBits(); ++i) for (unsigned i = 0; i != getNumBits(); ++i)
if (getBit(i)->isComplete()) return false; if (getBit(i)->isComplete()) return false;
return true; return true;
} }
virtual std::string getAsString() const; virtual std::string getAsString() const;
virtual Init *resolveReferences(Record &R, const RecordVal *RV) const; virtual Init *resolveReferences(Record &R, const RecordVal *RV) const;
virtual Init *getBit(unsigned Bit) const {
assert(Bit < Bits.size() && "Bit index out of range!");
return Bits[Bit];
}
}; };
/// IntInit - 7 - Represent an initalization by a literal integer value. /// IntInit - 7 - Represent an initalization by a literal integer value.
/// ///
class IntInit : public TypedInit { class IntInit : public TypedInit {
int64_t Value; int64_t Value;
explicit IntInit(int64_t V) : TypedInit(IntRecTy::get()), Value(V) {} explicit IntInit(int64_t V)
: TypedInit(IK_IntInit, IntRecTy::get()), Value(V) {}
IntInit(const IntInit &Other); // Do not define. IntInit(const IntInit &Other) LLVM_DELETED_FUNCTION;
IntInit &operator=(const IntInit &Other); // Do note define. IntInit &operator=(const IntInit &Other) LLVM_DELETED_FUNCTION;
public: public:
static bool classof(const Init *I) {
return I->getKind() == IK_IntInit;
}
static IntInit *get(int64_t V); static IntInit *get(int64_t V);
int64_t getValue() const { return Value; } int64_t getValue() const { return Value; }
virtual Init *convertInitializerTo(RecTy *Ty) const { virtual Init *convertInitializerTo(RecTy *Ty) const {
return Ty->convertValue(const_cast<IntInit *>(this)); return Ty->convertValue(const_cast<IntInit *>(this));
} }
virtual Init * virtual Init *
convertInitializerBitRange(const std::vector<unsigned> &Bits) const; convertInitializerBitRange(const std::vector<unsigned> &Bits) const;
virtual std::string getAsString() const; virtual std::string getAsString() const;
/// resolveBitReference - This method is used to implement
/// VarBitInit::resolveReferences. If the bit is able to be resolved, we
/// simply return the resolved value, otherwise we return null.
///
virtual Init *resolveBitReference(Record &R, const RecordVal *RV,
unsigned Bit) const {
llvm_unreachable("Illegal bit reference off int");
}
/// resolveListElementReference - This method is used to implement /// resolveListElementReference - This method is used to implement
/// VarListElementInit::resolveReferences. If the list element is resolv able /// VarListElementInit::resolveReferences. If the list element is resolv able
/// now, we return the resolved value, otherwise we return null. /// now, we return the resolved value, otherwise we return null.
virtual Init *resolveListElementReference(Record &R, const RecordVal *RV, virtual Init *resolveListElementReference(Record &R, const RecordVal *RV,
unsigned Elt) const { unsigned Elt) const {
llvm_unreachable("Illegal element reference off int"); llvm_unreachable("Illegal element reference off int");
} }
virtual Init *getBit(unsigned Bit) const {
return BitInit::get((Value & (1ULL << Bit)) != 0);
}
}; };
/// StringInit - "foo" - Represent an initialization by a string value. /// StringInit - "foo" - Represent an initialization by a string value.
/// ///
class StringInit : public TypedInit { class StringInit : public TypedInit {
std::string Value; std::string Value;
explicit StringInit(const std::string &V) explicit StringInit(const std::string &V)
: TypedInit(StringRecTy::get()), Value(V) {} : TypedInit(IK_StringInit, StringRecTy::get()), Value(V) {}
StringInit(const StringInit &Other); // Do not define. StringInit(const StringInit &Other) LLVM_DELETED_FUNCTION;
StringInit &operator=(const StringInit &Other); // Do not define. StringInit &operator=(const StringInit &Other) LLVM_DELETED_FUNCTION;
virtual void anchor(); virtual void anchor();
public: public:
static bool classof(const Init *I) {
return I->getKind() == IK_StringInit;
}
static StringInit *get(StringRef); static StringInit *get(StringRef);
const std::string &getValue() const { return Value; } const std::string &getValue() const { return Value; }
virtual Init *convertInitializerTo(RecTy *Ty) const { virtual Init *convertInitializerTo(RecTy *Ty) const {
return Ty->convertValue(const_cast<StringInit *>(this)); return Ty->convertValue(const_cast<StringInit *>(this));
} }
virtual std::string getAsString() const { return "\"" + Value + "\""; } virtual std::string getAsString() const { return "\"" + Value + "\""; }
virtual std::string getAsUnquotedString() const { return Value; } virtual std::string getAsUnquotedString() const { return Value; }
/// resolveBitReference - This method is used to implement
/// VarBitInit::resolveReferences. If the bit is able to be resolved, we
/// simply return the resolved value, otherwise we return null.
///
virtual Init *resolveBitReference(Record &R, const RecordVal *RV,
unsigned Bit) const {
llvm_unreachable("Illegal bit reference off string");
}
/// resolveListElementReference - This method is used to implement /// resolveListElementReference - This method is used to implement
/// VarListElementInit::resolveReferences. If the list element is resolv able /// VarListElementInit::resolveReferences. If the list element is resolv able
/// now, we return the resolved value, otherwise we return null. /// now, we return the resolved value, otherwise we return null.
virtual Init *resolveListElementReference(Record &R, const RecordVal *RV, virtual Init *resolveListElementReference(Record &R, const RecordVal *RV,
unsigned Elt) const { unsigned Elt) const {
llvm_unreachable("Illegal element reference off string"); llvm_unreachable("Illegal element reference off string");
} }
virtual Init *getBit(unsigned Bit) const {
llvm_unreachable("Illegal bit reference off string");
}
}; };
/// ListInit - [AL, AH, CL] - Represent a list of defs /// ListInit - [AL, AH, CL] - Represent a list of defs
/// ///
class ListInit : public TypedInit, public FoldingSetNode { class ListInit : public TypedInit, public FoldingSetNode {
std::vector<Init*> Values; std::vector<Init*> Values;
public: public:
typedef std::vector<Init*>::const_iterator const_iterator; typedef std::vector<Init*>::const_iterator const_iterator;
private: private:
explicit ListInit(ArrayRef<Init *> Range, RecTy *EltTy) explicit ListInit(ArrayRef<Init *> Range, RecTy *EltTy)
: TypedInit(ListRecTy::get(EltTy)), Values(Range.begin(), Range.end() : TypedInit(IK_ListInit, ListRecTy::get(EltTy)),
) {} Values(Range.begin(), Range.end()) {}
ListInit(const ListInit &Other); // Do not define. ListInit(const ListInit &Other) LLVM_DELETED_FUNCTION;
ListInit &operator=(const ListInit &Other); // Do not define. ListInit &operator=(const ListInit &Other) LLVM_DELETED_FUNCTION;
public: public:
static bool classof(const Init *I) {
return I->getKind() == IK_ListInit;
}
static ListInit *get(ArrayRef<Init *> Range, RecTy *EltTy); static ListInit *get(ArrayRef<Init *> Range, RecTy *EltTy);
void Profile(FoldingSetNodeID &ID) const; void Profile(FoldingSetNodeID &ID) const;
unsigned getSize() const { return Values.size(); } unsigned getSize() const { return Values.size(); }
Init *getElement(unsigned i) const { Init *getElement(unsigned i) const {
assert(i < Values.size() && "List element index out of range!"); assert(i < Values.size() && "List element index out of range!");
return Values[i]; return Values[i];
} }
Record *getElementAsRecord(unsigned i) const; Record *getElementAsRecord(unsigned i) const;
Init *convertInitListSlice(const std::vector<unsigned> &Elements) const; virtual Init *
convertInitListSlice(const std::vector<unsigned> &Elements) const;
virtual Init *convertInitializerTo(RecTy *Ty) const { virtual Init *convertInitializerTo(RecTy *Ty) const {
return Ty->convertValue(const_cast<ListInit *>(this)); return Ty->convertValue(const_cast<ListInit *>(this));
} }
/// resolveReferences - This method is used by classes that refer to othe r /// resolveReferences - This method is used by classes that refer to othe r
/// variables which may not be defined at the time they expression is for med. /// variables which may not be defined at the time they expression is for med.
/// If a value is set for the variable later, this method will be called on /// If a value is set for the variable later, this method will be called on
/// users of the value to allow the value to propagate out. /// users of the value to allow the value to propagate out.
/// ///
skipping to change at line 772 skipping to change at line 889
virtual std::string getAsString() const; virtual std::string getAsString() const;
ArrayRef<Init*> getValues() const { return Values; } ArrayRef<Init*> getValues() const { return Values; }
inline const_iterator begin() const { return Values.begin(); } inline const_iterator begin() const { return Values.begin(); }
inline const_iterator end () const { return Values.end(); } inline const_iterator end () const { return Values.end(); }
inline size_t size () const { return Values.size(); } inline size_t size () const { return Values.size(); }
inline bool empty() const { return Values.empty(); } inline bool empty() const { return Values.empty(); }
/// resolveBitReference - This method is used to implement
/// VarBitInit::resolveReferences. If the bit is able to be resolved, we
/// simply return the resolved value, otherwise we return null.
///
virtual Init *resolveBitReference(Record &R, const RecordVal *RV,
unsigned Bit) const {
llvm_unreachable("Illegal bit reference off list");
}
/// resolveListElementReference - This method is used to implement /// resolveListElementReference - This method is used to implement
/// VarListElementInit::resolveReferences. If the list element is resolv able /// VarListElementInit::resolveReferences. If the list element is resolv able
/// now, we return the resolved value, otherwise we return null. /// now, we return the resolved value, otherwise we return null.
virtual Init *resolveListElementReference(Record &R, const RecordVal *RV, virtual Init *resolveListElementReference(Record &R, const RecordVal *RV,
unsigned Elt) const; unsigned Elt) const;
virtual Init *getBit(unsigned Bit) const {
llvm_unreachable("Illegal bit reference off list");
}
}; };
/// OpInit - Base class for operators /// OpInit - Base class for operators
/// ///
class OpInit : public TypedInit { class OpInit : public TypedInit {
OpInit(const OpInit &Other); // Do not define. OpInit(const OpInit &Other) LLVM_DELETED_FUNCTION;
OpInit &operator=(OpInit &Other); // Do not define. OpInit &operator=(OpInit &Other) LLVM_DELETED_FUNCTION;
protected: protected:
explicit OpInit(RecTy *Type) : TypedInit(Type) {} explicit OpInit(InitKind K, RecTy *Type) : TypedInit(K, Type) {}
public: public:
static bool classof(const Init *I) {
return I->getKind() >= IK_FirstOpInit &&
I->getKind() <= IK_LastOpInit;
}
// Clone - Clone this operator, replacing arguments with the new list // Clone - Clone this operator, replacing arguments with the new list
virtual OpInit *clone(std::vector<Init *> &Operands) const = 0; virtual OpInit *clone(std::vector<Init *> &Operands) const = 0;
virtual int getNumOperands() const = 0; virtual int getNumOperands() const = 0;
virtual Init *getOperand(int i) const = 0; virtual Init *getOperand(int i) const = 0;
// Fold - If possible, fold this to a simpler init. Return this if not // Fold - If possible, fold this to a simpler init. Return this if not
// possible to fold. // possible to fold.
virtual Init *Fold(Record *CurRec, MultiClass *CurMultiClass) const = 0; virtual Init *Fold(Record *CurRec, MultiClass *CurMultiClass) const = 0;
virtual Init *convertInitializerTo(RecTy *Ty) const { virtual Init *convertInitializerTo(RecTy *Ty) const {
return Ty->convertValue(const_cast<OpInit *>(this)); return Ty->convertValue(const_cast<OpInit *>(this));
} }
virtual Init *resolveBitReference(Record &R, const RecordVal *RV,
unsigned Bit) const;
virtual Init *resolveListElementReference(Record &R, const RecordVal *RV, virtual Init *resolveListElementReference(Record &R, const RecordVal *RV,
unsigned Elt) const; unsigned Elt) const;
virtual Init *getBit(unsigned Bit) const;
}; };
/// UnOpInit - !op (X) - Transform an init. /// UnOpInit - !op (X) - Transform an init.
/// ///
class UnOpInit : public OpInit { class UnOpInit : public OpInit {
public: public:
enum UnaryOp { CAST, HEAD, TAIL, EMPTY }; enum UnaryOp { CAST, HEAD, TAIL, EMPTY };
private: private:
UnaryOp Opc; UnaryOp Opc;
Init *LHS; Init *LHS;
UnOpInit(UnaryOp opc, Init *lhs, RecTy *Type) UnOpInit(UnaryOp opc, Init *lhs, RecTy *Type)
: OpInit(Type), Opc(opc), LHS(lhs) {} : OpInit(IK_UnOpInit, Type), Opc(opc), LHS(lhs) {}
UnOpInit(const UnOpInit &Other); // Do not define. UnOpInit(const UnOpInit &Other) LLVM_DELETED_FUNCTION;
UnOpInit &operator=(const UnOpInit &Other); // Do not define. UnOpInit &operator=(const UnOpInit &Other) LLVM_DELETED_FUNCTION;
public: public:
static bool classof(const Init *I) {
return I->getKind() == IK_UnOpInit;
}
static UnOpInit *get(UnaryOp opc, Init *lhs, RecTy *Type); static UnOpInit *get(UnaryOp opc, Init *lhs, RecTy *Type);
// Clone - Clone this operator, replacing arguments with the new list // Clone - Clone this operator, replacing arguments with the new list
virtual OpInit *clone(std::vector<Init *> &Operands) const { virtual OpInit *clone(std::vector<Init *> &Operands) const {
assert(Operands.size() == 1 && assert(Operands.size() == 1 &&
"Wrong number of operands for unary operation"); "Wrong number of operands for unary operation");
return UnOpInit::get(getOpcode(), *Operands.begin(), getType()); return UnOpInit::get(getOpcode(), *Operands.begin(), getType());
} }
int getNumOperands() const { return 1; } virtual int getNumOperands() const { return 1; }
Init *getOperand(int i) const { virtual Init *getOperand(int i) const {
assert(i == 0 && "Invalid operand id for unary operator"); assert(i == 0 && "Invalid operand id for unary operator");
return getOperand(); return getOperand();
} }
UnaryOp getOpcode() const { return Opc; } UnaryOp getOpcode() const { return Opc; }
Init *getOperand() const { return LHS; } Init *getOperand() const { return LHS; }
// Fold - If possible, fold this to a simpler init. Return this if not // Fold - If possible, fold this to a simpler init. Return this if not
// possible to fold. // possible to fold.
Init *Fold(Record *CurRec, MultiClass *CurMultiClass) const; virtual Init *Fold(Record *CurRec, MultiClass *CurMultiClass) const;
virtual Init *resolveReferences(Record &R, const RecordVal *RV) const; virtual Init *resolveReferences(Record &R, const RecordVal *RV) const;
virtual std::string getAsString() const; virtual std::string getAsString() const;
}; };
/// BinOpInit - !op (X, Y) - Combine two inits. /// BinOpInit - !op (X, Y) - Combine two inits.
/// ///
class BinOpInit : public OpInit { class BinOpInit : public OpInit {
public: public:
enum BinaryOp { SHL, SRA, SRL, STRCONCAT, CONCAT, EQ }; enum BinaryOp { SHL, SRA, SRL, STRCONCAT, CONCAT, EQ };
private: private:
BinaryOp Opc; BinaryOp Opc;
Init *LHS, *RHS; Init *LHS, *RHS;
BinOpInit(BinaryOp opc, Init *lhs, Init *rhs, RecTy *Type) : BinOpInit(BinaryOp opc, Init *lhs, Init *rhs, RecTy *Type) :
OpInit(Type), Opc(opc), LHS(lhs), RHS(rhs) {} OpInit(IK_BinOpInit, Type), Opc(opc), LHS(lhs), RHS(rhs) {}
BinOpInit(const BinOpInit &Other); // Do not define. BinOpInit(const BinOpInit &Other) LLVM_DELETED_FUNCTION;
BinOpInit &operator=(const BinOpInit &Other); // Do not define. BinOpInit &operator=(const BinOpInit &Other) LLVM_DELETED_FUNCTION;
public: public:
static bool classof(const Init *I) {
return I->getKind() == IK_BinOpInit;
}
static BinOpInit *get(BinaryOp opc, Init *lhs, Init *rhs, static BinOpInit *get(BinaryOp opc, Init *lhs, Init *rhs,
RecTy *Type); RecTy *Type);
// Clone - Clone this operator, replacing arguments with the new list // Clone - Clone this operator, replacing arguments with the new list
virtual OpInit *clone(std::vector<Init *> &Operands) const { virtual OpInit *clone(std::vector<Init *> &Operands) const {
assert(Operands.size() == 2 && assert(Operands.size() == 2 &&
"Wrong number of operands for binary operation"); "Wrong number of operands for binary operation");
return BinOpInit::get(getOpcode(), Operands[0], Operands[1], getType()) ; return BinOpInit::get(getOpcode(), Operands[0], Operands[1], getType()) ;
} }
int getNumOperands() const { return 2; } virtual int getNumOperands() const { return 2; }
Init *getOperand(int i) const { virtual Init *getOperand(int i) const {
assert((i == 0 || i == 1) && "Invalid operand id for binary operator"); assert((i == 0 || i == 1) && "Invalid operand id for binary operator");
if (i == 0) { if (i == 0) {
return getLHS(); return getLHS();
} else { } else {
return getRHS(); return getRHS();
} }
} }
BinaryOp getOpcode() const { return Opc; } BinaryOp getOpcode() const { return Opc; }
Init *getLHS() const { return LHS; } Init *getLHS() const { return LHS; }
Init *getRHS() const { return RHS; } Init *getRHS() const { return RHS; }
// Fold - If possible, fold this to a simpler init. Return this if not // Fold - If possible, fold this to a simpler init. Return this if not
// possible to fold. // possible to fold.
Init *Fold(Record *CurRec, MultiClass *CurMultiClass) const; virtual Init *Fold(Record *CurRec, MultiClass *CurMultiClass) const;
virtual Init *resolveReferences(Record &R, const RecordVal *RV) const; virtual Init *resolveReferences(Record &R, const RecordVal *RV) const;
virtual std::string getAsString() const; virtual std::string getAsString() const;
}; };
/// TernOpInit - !op (X, Y, Z) - Combine two inits. /// TernOpInit - !op (X, Y, Z) - Combine two inits.
/// ///
class TernOpInit : public OpInit { class TernOpInit : public OpInit {
public: public:
enum TernaryOp { SUBST, FOREACH, IF }; enum TernaryOp { SUBST, FOREACH, IF };
private: private:
TernaryOp Opc; TernaryOp Opc;
Init *LHS, *MHS, *RHS; Init *LHS, *MHS, *RHS;
TernOpInit(TernaryOp opc, Init *lhs, Init *mhs, Init *rhs, TernOpInit(TernaryOp opc, Init *lhs, Init *mhs, Init *rhs,
RecTy *Type) : RecTy *Type) :
OpInit(Type), Opc(opc), LHS(lhs), MHS(mhs), RHS(rhs) {} OpInit(IK_TernOpInit, Type), Opc(opc), LHS(lhs), MHS(mhs), RHS(rhs) { }
TernOpInit(const TernOpInit &Other); // Do not define. TernOpInit(const TernOpInit &Other) LLVM_DELETED_FUNCTION;
TernOpInit &operator=(const TernOpInit &Other); // Do not define. TernOpInit &operator=(const TernOpInit &Other) LLVM_DELETED_FUNCTION;
public: public:
static bool classof(const Init *I) {
return I->getKind() == IK_TernOpInit;
}
static TernOpInit *get(TernaryOp opc, Init *lhs, static TernOpInit *get(TernaryOp opc, Init *lhs,
Init *mhs, Init *rhs, Init *mhs, Init *rhs,
RecTy *Type); RecTy *Type);
// Clone - Clone this operator, replacing arguments with the new list // Clone - Clone this operator, replacing arguments with the new list
virtual OpInit *clone(std::vector<Init *> &Operands) const { virtual OpInit *clone(std::vector<Init *> &Operands) const {
assert(Operands.size() == 3 && assert(Operands.size() == 3 &&
"Wrong number of operands for ternary operation"); "Wrong number of operands for ternary operation");
return TernOpInit::get(getOpcode(), Operands[0], Operands[1], Operands[ 2], return TernOpInit::get(getOpcode(), Operands[0], Operands[1], Operands[ 2],
getType()); getType());
} }
int getNumOperands() const { return 3; } virtual int getNumOperands() const { return 3; }
Init *getOperand(int i) const { virtual Init *getOperand(int i) const {
assert((i == 0 || i == 1 || i == 2) && assert((i == 0 || i == 1 || i == 2) &&
"Invalid operand id for ternary operator"); "Invalid operand id for ternary operator");
if (i == 0) { if (i == 0) {
return getLHS(); return getLHS();
} else if (i == 1) { } else if (i == 1) {
return getMHS(); return getMHS();
} else { } else {
return getRHS(); return getRHS();
} }
} }
TernaryOp getOpcode() const { return Opc; } TernaryOp getOpcode() const { return Opc; }
Init *getLHS() const { return LHS; } Init *getLHS() const { return LHS; }
Init *getMHS() const { return MHS; } Init *getMHS() const { return MHS; }
Init *getRHS() const { return RHS; } Init *getRHS() const { return RHS; }
// Fold - If possible, fold this to a simpler init. Return this if not // Fold - If possible, fold this to a simpler init. Return this if not
// possible to fold. // possible to fold.
Init *Fold(Record *CurRec, MultiClass *CurMultiClass) const; virtual Init *Fold(Record *CurRec, MultiClass *CurMultiClass) const;
virtual bool isComplete() const { return false; } virtual bool isComplete() const { return false; }
virtual Init *resolveReferences(Record &R, const RecordVal *RV) const; virtual Init *resolveReferences(Record &R, const RecordVal *RV) const;
virtual std::string getAsString() const; virtual std::string getAsString() const;
}; };
/// VarInit - 'Opcode' - Represent a reference to an entire variable object . /// VarInit - 'Opcode' - Represent a reference to an entire variable object .
/// ///
class VarInit : public TypedInit { class VarInit : public TypedInit {
Init *VarName; Init *VarName;
explicit VarInit(const std::string &VN, RecTy *T) explicit VarInit(const std::string &VN, RecTy *T)
: TypedInit(T), VarName(StringInit::get(VN)) {} : TypedInit(IK_VarInit, T), VarName(StringInit::get(VN)) {}
explicit VarInit(Init *VN, RecTy *T) explicit VarInit(Init *VN, RecTy *T)
: TypedInit(T), VarName(VN) {} : TypedInit(IK_VarInit, T), VarName(VN) {}
VarInit(const VarInit &Other); // Do not define. VarInit(const VarInit &Other) LLVM_DELETED_FUNCTION;
VarInit &operator=(const VarInit &Other); // Do not define. VarInit &operator=(const VarInit &Other) LLVM_DELETED_FUNCTION;
public: public:
static bool classof(const Init *I) {
return I->getKind() == IK_VarInit;
}
static VarInit *get(const std::string &VN, RecTy *T); static VarInit *get(const std::string &VN, RecTy *T);
static VarInit *get(Init *VN, RecTy *T); static VarInit *get(Init *VN, RecTy *T);
virtual Init *convertInitializerTo(RecTy *Ty) const { virtual Init *convertInitializerTo(RecTy *Ty) const {
return Ty->convertValue(const_cast<VarInit *>(this)); return Ty->convertValue(const_cast<VarInit *>(this));
} }
const std::string &getName() const; const std::string &getName() const;
Init *getNameInit() const { return VarName; } Init *getNameInit() const { return VarName; }
std::string getNameInitAsString() const { std::string getNameInitAsString() const {
return getNameInit()->getAsUnquotedString(); return getNameInit()->getAsUnquotedString();
} }
virtual Init *resolveBitReference(Record &R, const RecordVal *RV,
unsigned Bit) const;
virtual Init *resolveListElementReference(Record &R, const RecordVal *RV, virtual Init *resolveListElementReference(Record &R, const RecordVal *RV,
unsigned Elt) const; unsigned Elt) const;
virtual RecTy *getFieldType(const std::string &FieldName) const; virtual RecTy *getFieldType(const std::string &FieldName) const;
virtual Init *getFieldInit(Record &R, const RecordVal *RV, virtual Init *getFieldInit(Record &R, const RecordVal *RV,
const std::string &FieldName) const; const std::string &FieldName) const;
/// resolveReferences - This method is used by classes that refer to othe r /// resolveReferences - This method is used by classes that refer to othe r
/// variables which may not be defined at the time they expression is for med. /// variables which may not be defined at the time they expression is for med.
/// If a value is set for the variable later, this method will be called on /// If a value is set for the variable later, this method will be called on
/// users of the value to allow the value to propagate out. /// users of the value to allow the value to propagate out.
/// ///
virtual Init *resolveReferences(Record &R, const RecordVal *RV) const; virtual Init *resolveReferences(Record &R, const RecordVal *RV) const;
virtual Init *getBit(unsigned Bit) const;
virtual std::string getAsString() const { return getName(); } virtual std::string getAsString() const { return getName(); }
}; };
/// VarBitInit - Opcode{0} - Represent access to one bit of a variable or f ield. /// VarBitInit - Opcode{0} - Represent access to one bit of a variable or f ield.
/// ///
class VarBitInit : public Init { class VarBitInit : public Init {
TypedInit *TI; TypedInit *TI;
unsigned Bit; unsigned Bit;
VarBitInit(TypedInit *T, unsigned B) : TI(T), Bit(B) { VarBitInit(TypedInit *T, unsigned B) : Init(IK_VarBitInit), TI(T), Bit(B)
assert(T->getType() && dynamic_cast<BitsRecTy*>(T->getType()) && {
((BitsRecTy*)T->getType())->getNumBits() > B && assert(T->getType() &&
(isa<IntRecTy>(T->getType()) ||
(isa<BitsRecTy>(T->getType()) &&
cast<BitsRecTy>(T->getType())->getNumBits() > B)) &&
"Illegal VarBitInit expression!"); "Illegal VarBitInit expression!");
} }
VarBitInit(const VarBitInit &Other); // Do not define. VarBitInit(const VarBitInit &Other) LLVM_DELETED_FUNCTION;
VarBitInit &operator=(const VarBitInit &Other); // Do not define. VarBitInit &operator=(const VarBitInit &Other) LLVM_DELETED_FUNCTION;
public: public:
static bool classof(const Init *I) {
return I->getKind() == IK_VarBitInit;
}
static VarBitInit *get(TypedInit *T, unsigned B); static VarBitInit *get(TypedInit *T, unsigned B);
virtual Init *convertInitializerTo(RecTy *Ty) const { virtual Init *convertInitializerTo(RecTy *Ty) const {
return Ty->convertValue(const_cast<VarBitInit *>(this)); return Ty->convertValue(const_cast<VarBitInit *>(this));
} }
TypedInit *getVariable() const { return TI; } virtual Init *getBitVar() const { return TI; }
unsigned getBitNum() const { return Bit; } virtual unsigned getBitNum() const { return Bit; }
virtual std::string getAsString() const; virtual std::string getAsString() const;
virtual Init *resolveReferences(Record &R, const RecordVal *RV) const; virtual Init *resolveReferences(Record &R, const RecordVal *RV) const;
virtual Init *getBit(unsigned B) const {
assert(B < 1 && "Bit index out of range!");
return const_cast<VarBitInit*>(this);
}
}; };
/// VarListElementInit - List[4] - Represent access to one element of a var or /// VarListElementInit - List[4] - Represent access to one element of a var or
/// field. /// field.
class VarListElementInit : public TypedInit { class VarListElementInit : public TypedInit {
TypedInit *TI; TypedInit *TI;
unsigned Element; unsigned Element;
VarListElementInit(TypedInit *T, unsigned E) VarListElementInit(TypedInit *T, unsigned E)
: TypedInit(dynamic_cast<ListRecTy*>(T->getType())->getElementType()) : TypedInit(IK_VarListElementInit,
, cast<ListRecTy>(T->getType())->getElementType()),
TI(T), Element(E) { TI(T), Element(E) {
assert(T->getType() && dynamic_cast<ListRecTy*>(T->getType()) && assert(T->getType() && isa<ListRecTy>(T->getType()) &&
"Illegal VarBitInit expression!"); "Illegal VarBitInit expression!");
} }
VarListElementInit(const VarListElementInit &Other); // Do not define. VarListElementInit(const VarListElementInit &Other) LLVM_DELETED_FUNCTION
VarListElementInit &operator=(const VarListElementInit &Other); // Do ;
// not void operator=(const VarListElementInit &Other) LLVM_DELETED_FUNCTION;
// defin
e.
public: public:
static bool classof(const Init *I) {
return I->getKind() == IK_VarListElementInit;
}
static VarListElementInit *get(TypedInit *T, unsigned E); static VarListElementInit *get(TypedInit *T, unsigned E);
virtual Init *convertInitializerTo(RecTy *Ty) const { virtual Init *convertInitializerTo(RecTy *Ty) const {
return Ty->convertValue(const_cast<VarListElementInit *>(this)); return Ty->convertValue(const_cast<VarListElementInit *>(this));
} }
TypedInit *getVariable() const { return TI; } TypedInit *getVariable() const { return TI; }
unsigned getElementNum() const { return Element; } unsigned getElementNum() const { return Element; }
virtual Init *resolveBitReference(Record &R, const RecordVal *RV,
unsigned Bit) const;
/// resolveListElementReference - This method is used to implement /// resolveListElementReference - This method is used to implement
/// VarListElementInit::resolveReferences. If the list element is resolv able /// VarListElementInit::resolveReferences. If the list element is resolv able
/// now, we return the resolved value, otherwise we return null. /// now, we return the resolved value, otherwise we return null.
virtual Init *resolveListElementReference(Record &R, virtual Init *resolveListElementReference(Record &R,
const RecordVal *RV, const RecordVal *RV,
unsigned Elt) const; unsigned Elt) const;
virtual std::string getAsString() const; virtual std::string getAsString() const;
virtual Init *resolveReferences(Record &R, const RecordVal *RV) const; virtual Init *resolveReferences(Record &R, const RecordVal *RV) const;
virtual Init *getBit(unsigned Bit) const;
}; };
/// DefInit - AL - Represent a reference to a 'def' in the description /// DefInit - AL - Represent a reference to a 'def' in the description
/// ///
class DefInit : public TypedInit { class DefInit : public TypedInit {
Record *Def; Record *Def;
DefInit(Record *D, RecordRecTy *T) : TypedInit(T), Def(D) {} DefInit(Record *D, RecordRecTy *T) : TypedInit(IK_DefInit, T), Def(D) {}
friend class Record; friend class Record;
DefInit(const DefInit &Other); // Do not define. DefInit(const DefInit &Other) LLVM_DELETED_FUNCTION;
DefInit &operator=(const DefInit &Other); // Do not define. DefInit &operator=(const DefInit &Other) LLVM_DELETED_FUNCTION;
public: public:
static bool classof(const Init *I) {
return I->getKind() == IK_DefInit;
}
static DefInit *get(Record*); static DefInit *get(Record*);
virtual Init *convertInitializerTo(RecTy *Ty) const { virtual Init *convertInitializerTo(RecTy *Ty) const {
return Ty->convertValue(const_cast<DefInit *>(this)); return Ty->convertValue(const_cast<DefInit *>(this));
} }
Record *getDef() const { return Def; } Record *getDef() const { return Def; }
//virtual Init *convertInitializerBitRange(const std::vector<unsigned> &B its); //virtual Init *convertInitializerBitRange(const std::vector<unsigned> &B its);
virtual RecTy *getFieldType(const std::string &FieldName) const; virtual RecTy *getFieldType(const std::string &FieldName) const;
virtual Init *getFieldInit(Record &R, const RecordVal *RV, virtual Init *getFieldInit(Record &R, const RecordVal *RV,
const std::string &FieldName) const; const std::string &FieldName) const;
virtual std::string getAsString() const; virtual std::string getAsString() const;
/// resolveBitReference - This method is used to implement virtual Init *getBit(unsigned Bit) const {
/// VarBitInit::resolveReferences. If the bit is able to be resolved, we
/// simply return the resolved value, otherwise we return null.
///
virtual Init *resolveBitReference(Record &R, const RecordVal *RV,
unsigned Bit) const {
llvm_unreachable("Illegal bit reference off def"); llvm_unreachable("Illegal bit reference off def");
} }
/// resolveListElementReference - This method is used to implement /// resolveListElementReference - This method is used to implement
/// VarListElementInit::resolveReferences. If the list element is resolv able /// VarListElementInit::resolveReferences. If the list element is resolv able
/// now, we return the resolved value, otherwise we return null. /// now, we return the resolved value, otherwise we return null.
virtual Init *resolveListElementReference(Record &R, const RecordVal *RV, virtual Init *resolveListElementReference(Record &R, const RecordVal *RV,
unsigned Elt) const { unsigned Elt) const {
llvm_unreachable("Illegal element reference off def"); llvm_unreachable("Illegal element reference off def");
} }
}; };
/// FieldInit - X.Y - Represent a reference to a subfield of a variable /// FieldInit - X.Y - Represent a reference to a subfield of a variable
/// ///
class FieldInit : public TypedInit { class FieldInit : public TypedInit {
Init *Rec; // Record we are referring to Init *Rec; // Record we are referring to
std::string FieldName; // Field we are accessing std::string FieldName; // Field we are accessing
FieldInit(Init *R, const std::string &FN) FieldInit(Init *R, const std::string &FN)
: TypedInit(R->getFieldType(FN)), Rec(R), FieldName(FN) { : TypedInit(IK_FieldInit, R->getFieldType(FN)), Rec(R), FieldName(FN) {
assert(getType() && "FieldInit with non-record type!"); assert(getType() && "FieldInit with non-record type!");
} }
FieldInit(const FieldInit &Other); // Do not define. FieldInit(const FieldInit &Other) LLVM_DELETED_FUNCTION;
FieldInit &operator=(const FieldInit &Other); // Do not define. FieldInit &operator=(const FieldInit &Other) LLVM_DELETED_FUNCTION;
public: public:
static bool classof(const Init *I) {
return I->getKind() == IK_FieldInit;
}
static FieldInit *get(Init *R, const std::string &FN); static FieldInit *get(Init *R, const std::string &FN);
static FieldInit *get(Init *R, const Init *FN); static FieldInit *get(Init *R, const Init *FN);
virtual Init *convertInitializerTo(RecTy *Ty) const { virtual Init *convertInitializerTo(RecTy *Ty) const {
return Ty->convertValue(const_cast<FieldInit *>(this)); return Ty->convertValue(const_cast<FieldInit *>(this));
} }
virtual Init *resolveBitReference(Record &R, const RecordVal *RV, virtual Init *getBit(unsigned Bit) const;
unsigned Bit) const;
virtual Init *resolveListElementReference(Record &R, virtual Init *resolveListElementReference(Record &R,
const RecordVal *RV, const RecordVal *RV,
unsigned Elt) const; unsigned Elt) const;
virtual Init *resolveReferences(Record &R, const RecordVal *RV) const; virtual Init *resolveReferences(Record &R, const RecordVal *RV) const;
virtual std::string getAsString() const { virtual std::string getAsString() const {
return Rec->getAsString() + "." + FieldName; return Rec->getAsString() + "." + FieldName;
} }
}; };
skipping to change at line 1179 skipping to change at line 1319
/// ///
class DagInit : public TypedInit, public FoldingSetNode { class DagInit : public TypedInit, public FoldingSetNode {
Init *Val; Init *Val;
std::string ValName; std::string ValName;
std::vector<Init*> Args; std::vector<Init*> Args;
std::vector<std::string> ArgNames; std::vector<std::string> ArgNames;
DagInit(Init *V, const std::string &VN, DagInit(Init *V, const std::string &VN,
ArrayRef<Init *> ArgRange, ArrayRef<Init *> ArgRange,
ArrayRef<std::string> NameRange) ArrayRef<std::string> NameRange)
: TypedInit(DagRecTy::get()), Val(V), ValName(VN), : TypedInit(IK_DagInit, DagRecTy::get()), Val(V), ValName(VN),
Args(ArgRange.begin(), ArgRange.end()), Args(ArgRange.begin(), ArgRange.end()),
ArgNames(NameRange.begin(), NameRange.end()) {} ArgNames(NameRange.begin(), NameRange.end()) {}
DagInit(const DagInit &Other); // Do not define. DagInit(const DagInit &Other) LLVM_DELETED_FUNCTION;
DagInit &operator=(const DagInit &Other); // Do not define. DagInit &operator=(const DagInit &Other) LLVM_DELETED_FUNCTION;
public: public:
static bool classof(const Init *I) {
return I->getKind() == IK_DagInit;
}
static DagInit *get(Init *V, const std::string &VN, static DagInit *get(Init *V, const std::string &VN,
ArrayRef<Init *> ArgRange, ArrayRef<Init *> ArgRange,
ArrayRef<std::string> NameRange); ArrayRef<std::string> NameRange);
static DagInit *get(Init *V, const std::string &VN, static DagInit *get(Init *V, const std::string &VN,
const std::vector< const std::vector<
std::pair<Init*, std::string> > &args); std::pair<Init*, std::string> > &args);
void Profile(FoldingSetNodeID &ID) const; void Profile(FoldingSetNodeID &ID) const;
virtual Init *convertInitializerTo(RecTy *Ty) const { virtual Init *convertInitializerTo(RecTy *Ty) const {
skipping to change at line 1233 skipping to change at line 1376
inline size_t arg_size () const { return Args.size(); } inline size_t arg_size () const { return Args.size(); }
inline bool arg_empty() const { return Args.empty(); } inline bool arg_empty() const { return Args.empty(); }
inline const_name_iterator name_begin() const { return ArgNames.begin(); } inline const_name_iterator name_begin() const { return ArgNames.begin(); }
inline const_name_iterator name_end () const { return ArgNames.end(); } inline const_name_iterator name_end () const { return ArgNames.end(); }
inline size_t name_size () const { return ArgNames.size(); } inline size_t name_size () const { return ArgNames.size(); }
inline bool name_empty() const { return ArgNames.empty(); } inline bool name_empty() const { return ArgNames.empty(); }
virtual Init *resolveBitReference(Record &R, const RecordVal *RV, virtual Init *getBit(unsigned Bit) const {
unsigned Bit) const {
llvm_unreachable("Illegal bit reference off dag"); llvm_unreachable("Illegal bit reference off dag");
} }
virtual Init *resolveListElementReference(Record &R, const RecordVal *RV, virtual Init *resolveListElementReference(Record &R, const RecordVal *RV,
unsigned Elt) const { unsigned Elt) const {
llvm_unreachable("Illegal element reference off dag"); llvm_unreachable("Illegal element reference off dag");
} }
}; };
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
skipping to change at line 1291 skipping to change at line 1433
RV.print(OS << " "); RV.print(OS << " ");
return OS; return OS;
} }
class Record { class Record {
static unsigned LastID; static unsigned LastID;
// Unique record ID. // Unique record ID.
unsigned ID; unsigned ID;
Init *Name; Init *Name;
SMLoc Loc; // Location where record was instantiated, followed by the location of
// multiclass prototypes used.
SmallVector<SMLoc, 4> Locs;
std::vector<Init *> TemplateArgs; std::vector<Init *> TemplateArgs;
std::vector<RecordVal> Values; std::vector<RecordVal> Values;
std::vector<Record*> SuperClasses; std::vector<Record*> SuperClasses;
// Tracks Record instances. Not owned by Record. // Tracks Record instances. Not owned by Record.
RecordKeeper &TrackedRecords; RecordKeeper &TrackedRecords;
DefInit *TheInit; DefInit *TheInit;
void init(); void init();
void checkName(); void checkName();
public: public:
// Constructs a record. // Constructs a record.
explicit Record(const std::string &N, SMLoc loc, RecordKeeper &records) : explicit Record(const std::string &N, ArrayRef<SMLoc> locs,
ID(LastID++), Name(StringInit::get(N)), Loc(loc), TrackedRecords(record RecordKeeper &records) :
s), ID(LastID++), Name(StringInit::get(N)), Locs(locs.begin(), locs.end()),
TheInit(0) { TrackedRecords(records), TheInit(0) {
init(); init();
} }
explicit Record(Init *N, SMLoc loc, RecordKeeper &records) : explicit Record(Init *N, ArrayRef<SMLoc> locs, RecordKeeper &records) :
ID(LastID++), Name(N), Loc(loc), TrackedRecords(records), TheInit(0) { ID(LastID++), Name(N), Locs(locs.begin(), locs.end()),
TrackedRecords(records), TheInit(0) {
init(); init();
} }
// When copy-constructing a Record, we must still guarantee a globally un
ique
// ID number. All other fields can be copied normally.
Record(const Record &O) :
ID(LastID++), Name(O.Name), Locs(O.Locs), TemplateArgs(O.TemplateArgs),
Values(O.Values), SuperClasses(O.SuperClasses),
TrackedRecords(O.TrackedRecords), TheInit(O.TheInit) { }
~Record() {} ~Record() {}
static unsigned getNewUID() { return LastID++; } static unsigned getNewUID() { return LastID++; }
unsigned getID() const { return ID; } unsigned getID() const { return ID; }
const std::string &getName() const; const std::string &getName() const;
Init *getNameInit() const { Init *getNameInit() const {
return Name; return Name;
} }
const std::string getNameInitAsString() const { const std::string getNameInitAsString() const {
return getNameInit()->getAsUnquotedString(); return getNameInit()->getAsUnquotedString();
} }
void setName(Init *Name); // Also updates RecordKeeper. void setName(Init *Name); // Also updates RecordKeeper.
void setName(const std::string &Name); // Also updates RecordKeeper. void setName(const std::string &Name); // Also updates RecordKeeper.
SMLoc getLoc() const { return Loc; } ArrayRef<SMLoc> getLoc() const { return Locs; }
/// get the corresponding DefInit. /// get the corresponding DefInit.
DefInit *getDefInit(); DefInit *getDefInit();
const std::vector<Init *> &getTemplateArgs() const { const std::vector<Init *> &getTemplateArgs() const {
return TemplateArgs; return TemplateArgs;
} }
const std::vector<RecordVal> &getValues() const { return Values; } const std::vector<RecordVal> &getValues() const { return Values; }
const std::vector<Record*> &getSuperClasses() const { return SuperClass es; } const std::vector<Record*> &getSuperClasses() const { return SuperClass es; }
skipping to change at line 1495 skipping to change at line 1649
/// the value is not the right type. /// the value is not the right type.
/// ///
Record *getValueAsDef(StringRef FieldName) const; Record *getValueAsDef(StringRef FieldName) const;
/// getValueAsBit - This method looks up the specified field and returns its /// getValueAsBit - This method looks up the specified field and returns its
/// value as a bit, throwing an exception if the field does not exist or if /// value as a bit, throwing an exception if the field does not exist or if
/// the value is not the right type. /// the value is not the right type.
/// ///
bool getValueAsBit(StringRef FieldName) const; bool getValueAsBit(StringRef FieldName) const;
/// getValueAsBitOrUnset - This method looks up the specified field and
/// returns its value as a bit. If the field is unset, sets Unset to true
and
/// retunrs false.
///
bool getValueAsBitOrUnset(StringRef FieldName, bool &Unset) const;
/// getValueAsInt - This method looks up the specified field and returns its /// getValueAsInt - This method looks up the specified field and returns its
/// value as an int64_t, throwing an exception if the field does not exis t or /// value as an int64_t, throwing an exception if the field does not exis t or
/// if the value is not the right type. /// if the value is not the right type.
/// ///
int64_t getValueAsInt(StringRef FieldName) const; int64_t getValueAsInt(StringRef FieldName) const;
/// getValueAsDag - This method looks up the specified field and returns its /// getValueAsDag - This method looks up the specified field and returns its
/// value as an Dag, throwing an exception if the field does not exist or if /// value as an Dag, throwing an exception if the field does not exist or if
/// the value is not the right type. /// the value is not the right type.
/// ///
skipping to change at line 1546 skipping to change at line 1706
Record *getClass(const std::string &Name) const { Record *getClass(const std::string &Name) const {
std::map<std::string, Record*>::const_iterator I = Classes.find(Name); std::map<std::string, Record*>::const_iterator I = Classes.find(Name);
return I == Classes.end() ? 0 : I->second; return I == Classes.end() ? 0 : I->second;
} }
Record *getDef(const std::string &Name) const { Record *getDef(const std::string &Name) const {
std::map<std::string, Record*>::const_iterator I = Defs.find(Name); std::map<std::string, Record*>::const_iterator I = Defs.find(Name);
return I == Defs.end() ? 0 : I->second; return I == Defs.end() ? 0 : I->second;
} }
void addClass(Record *R) { void addClass(Record *R) {
assert(getClass(R->getNameInitAsString()) == 0 && "Class already exists bool Ins = Classes.insert(std::make_pair(R->getName(), R)).second;
!"); (void)Ins;
Classes.insert(std::make_pair(R->getNameInitAsString(), R)); assert(Ins && "Class already exists");
} }
void addDef(Record *R) { void addDef(Record *R) {
assert(getDef(R->getNameInitAsString()) == 0 && "Def already exists!"); bool Ins = Defs.insert(std::make_pair(R->getName(), R)).second;
Defs.insert(std::make_pair(R->getNameInitAsString(), R)); (void)Ins;
assert(Ins && "Record already exists");
} }
/// removeClass - Remove, but do not delete, the specified record. /// removeClass - Remove, but do not delete, the specified record.
/// ///
void removeClass(const std::string &Name) { void removeClass(const std::string &Name) {
assert(Classes.count(Name) && "Class does not exist!"); assert(Classes.count(Name) && "Class does not exist!");
Classes.erase(Name); Classes.erase(Name);
} }
/// removeDef - Remove, but do not delete, the specified record. /// removeDef - Remove, but do not delete, the specified record.
/// ///
skipping to change at line 1587 skipping to change at line 1749
}; };
/// LessRecord - Sorting predicate to sort record pointers by name. /// LessRecord - Sorting predicate to sort record pointers by name.
/// ///
struct LessRecord { struct LessRecord {
bool operator()(const Record *Rec1, const Record *Rec2) const { bool operator()(const Record *Rec1, const Record *Rec2) const {
return StringRef(Rec1->getName()).compare_numeric(Rec2->getName()) < 0; return StringRef(Rec1->getName()).compare_numeric(Rec2->getName()) < 0;
} }
}; };
/// LessRecordByID - Sorting predicate to sort record pointers by their
/// unique ID. If you just need a deterministic order, use this, since it
/// just compares two `unsigned`; the other sorting predicates require
/// string manipulation.
struct LessRecordByID {
bool operator()(const Record *LHS, const Record *RHS) const {
return LHS->getID() < RHS->getID();
}
};
/// LessRecordFieldName - Sorting predicate to sort record pointers by thei r /// LessRecordFieldName - Sorting predicate to sort record pointers by thei r
/// name field. /// name field.
/// ///
struct LessRecordFieldName { struct LessRecordFieldName {
bool operator()(const Record *Rec1, const Record *Rec2) const { bool operator()(const Record *Rec1, const Record *Rec2) const {
return Rec1->getValueAsString("Name") < Rec2->getValueAsString("Name"); return Rec1->getValueAsString("Name") < Rec2->getValueAsString("Name");
} }
}; };
raw_ostream &operator<<(raw_ostream &OS, const RecordKeeper &RK); raw_ostream &operator<<(raw_ostream &OS, const RecordKeeper &RK);
 End of changes. 124 change blocks. 
167 lines changed or deleted 339 lines changed or added


 RegAllocPBQP.h   RegAllocPBQP.h 
skipping to change at line 112 skipping to change at line 112
AllowedSetMap allowedSets; AllowedSetMap allowedSets;
}; };
/// Builds PBQP instances to represent register allocation problems. Incl udes /// Builds PBQP instances to represent register allocation problems. Incl udes
/// spill, interference and coalescing costs by default. You can extend t his /// spill, interference and coalescing costs by default. You can extend t his
/// class to support additional constraints for your architecture. /// class to support additional constraints for your architecture.
class PBQPBuilder { class PBQPBuilder {
private: private:
PBQPBuilder(const PBQPBuilder&) {} PBQPBuilder(const PBQPBuilder&) LLVM_DELETED_FUNCTION;
void operator=(const PBQPBuilder&) {} void operator=(const PBQPBuilder&) LLVM_DELETED_FUNCTION;
public: public:
typedef std::set<unsigned> RegSet; typedef std::set<unsigned> RegSet;
/// Default constructor. /// Default constructor.
PBQPBuilder() {} PBQPBuilder() {}
/// Clean up a PBQPBuilder. /// Clean up a PBQPBuilder.
virtual ~PBQPBuilder() {} virtual ~PBQPBuilder() {}
 End of changes. 1 change blocks. 
2 lines changed or deleted 2 lines changed or added


 Regex.h   Regex.h 
skipping to change at line 39 skipping to change at line 39
/// Compile for matching that ignores upper/lower case distinctions. /// Compile for matching that ignores upper/lower case distinctions.
IgnoreCase=1, IgnoreCase=1,
/// Compile for newline-sensitive matching. With this flag '[^' brack et /// Compile for newline-sensitive matching. With this flag '[^' brack et
/// expressions and '.' never match newline. A ^ anchor matches the /// expressions and '.' never match newline. A ^ anchor matches the
/// null string after any newline in the string in addition to its no rmal /// null string after any newline in the string in addition to its no rmal
/// function, and the $ anchor matches the null string before any /// function, and the $ anchor matches the null string before any
/// newline in the string in addition to its normal function. /// newline in the string in addition to its normal function.
Newline=2 Newline=2
}; };
/// Compiles the given POSIX Extended Regular Expression \arg Regex. /// Compiles the given POSIX Extended Regular Expression \p Regex.
/// This implementation supports regexes and matching strings with embe dded /// This implementation supports regexes and matching strings with embe dded
/// NUL characters. /// NUL characters.
Regex(StringRef Regex, unsigned Flags = NoFlags); Regex(StringRef Regex, unsigned Flags = NoFlags);
~Regex(); ~Regex();
/// isValid - returns the error encountered during regex compilation, o r /// isValid - returns the error encountered during regex compilation, o r
/// matching, if any. /// matching, if any.
bool isValid(std::string &Error); bool isValid(std::string &Error);
/// getNumMatches - In a valid regex, return the number of parenthesize d /// getNumMatches - In a valid regex, return the number of parenthesize d
/// matches it contains. The number filled in by match will include th is /// matches it contains. The number filled in by match will include th is
/// many entries plus one for the whole regex (as element 0). /// many entries plus one for the whole regex (as element 0).
unsigned getNumMatches() const; unsigned getNumMatches() const;
/// matches - Match the regex against a given \arg String. /// matches - Match the regex against a given \p String.
/// ///
/// \param Matches - If given, on a successful match this will be fille d in /// \param Matches - If given, on a successful match this will be fille d in
/// with references to the matched group expressions (inside \arg Strin g), /// with references to the matched group expressions (inside \p String) ,
/// the first group is always the entire pattern. /// the first group is always the entire pattern.
/// ///
/// This returns true on a successful match. /// This returns true on a successful match.
bool match(StringRef String, SmallVectorImpl<StringRef> *Matches = 0); bool match(StringRef String, SmallVectorImpl<StringRef> *Matches = 0);
/// sub - Return the result of replacing the first match of the regex i n /// sub - Return the result of replacing the first match of the regex i n
/// \arg String with the \arg Repl string. Backreferences like "\0" in the /// \p String with the \p Repl string. Backreferences like "\0" in the
/// replacement string are replaced with the appropriate match substrin g. /// replacement string are replaced with the appropriate match substrin g.
/// ///
/// Note that the replacement string has backslash escaping performed o n /// Note that the replacement string has backslash escaping performed o n
/// it. Invalid backreferences are ignored (replaced by empty strings). /// it. Invalid backreferences are ignored (replaced by empty strings).
/// ///
/// \param Error If non-null, any errors in the substitution (invalid /// \param Error If non-null, any errors in the substitution (invalid
/// backreferences, trailing backslashes) will be recorded as a non-emp ty /// backreferences, trailing backslashes) will be recorded as a non-emp ty
/// string. /// string.
std::string sub(StringRef Repl, StringRef String, std::string *Error = 0); std::string sub(StringRef Repl, StringRef String, std::string *Error = 0);
 End of changes. 4 change blocks. 
4 lines changed or deleted 4 lines changed or added


 RegionInfo.h   RegionInfo.h 
skipping to change at line 57 skipping to change at line 57
/// iterate in Flat mode. During a Flat mode iteration all Regions are ent ered /// iterate in Flat mode. During a Flat mode iteration all Regions are ent ered
/// and the iteration returns every BasicBlock. If the Flat mode is not /// and the iteration returns every BasicBlock. If the Flat mode is not
/// selected for SubRegions just one RegionNode containing the subregion is /// selected for SubRegions just one RegionNode containing the subregion is
/// returned. /// returned.
template <class GraphType> template <class GraphType>
class FlatIt {}; class FlatIt {};
/// @brief A RegionNode represents a subregion or a BasicBlock that is part of a /// @brief A RegionNode represents a subregion or a BasicBlock that is part of a
/// Region. /// Region.
class RegionNode { class RegionNode {
// DO NOT IMPLEMENT RegionNode(const RegionNode &) LLVM_DELETED_FUNCTION;
RegionNode(const RegionNode &); const RegionNode &operator=(const RegionNode &) LLVM_DELETED_FUNCTION;
// DO NOT IMPLEMENT
const RegionNode &operator=(const RegionNode &);
protected: protected:
/// This is the entry basic block that starts this region node. If this is a /// This is the entry basic block that starts this region node. If this is a
/// BasicBlock RegionNode, then entry is just the basic block, that this /// BasicBlock RegionNode, then entry is just the basic block, that this
/// RegionNode represents. Otherwise it is the entry of this (Sub)Region Node. /// RegionNode represents. Otherwise it is the entry of this (Sub)Region Node.
/// ///
/// In the BBtoRegionNode map of the parent of this node, BB will always map /// In the BBtoRegionNode map of the parent of this node, BB will always map
/// to this node no matter which kind of node this one is. /// to this node no matter which kind of node this one is.
/// ///
/// The node can hold either a Region or a BasicBlock. /// The node can hold either a Region or a BasicBlock.
skipping to change at line 206 skipping to change at line 204
/// <tt> "opt -regions -analyze anyprogram.ll" </tt> /// <tt> "opt -regions -analyze anyprogram.ll" </tt>
/// or /// or
/// <tt> "opt -view-regions-only anyprogram.ll" </tt> /// <tt> "opt -view-regions-only anyprogram.ll" </tt>
/// ///
/// on any LLVM file you are interested in. /// on any LLVM file you are interested in.
/// ///
/// The first call returns a textual representation of the program structur e /// The first call returns a textual representation of the program structur e
/// tree, the second one creates a graphical representation using graphviz. /// tree, the second one creates a graphical representation using graphviz.
class Region : public RegionNode { class Region : public RegionNode {
friend class RegionInfo; friend class RegionInfo;
// DO NOT IMPLEMENT Region(const Region &) LLVM_DELETED_FUNCTION;
Region(const Region &); const Region &operator=(const Region &) LLVM_DELETED_FUNCTION;
// DO NOT IMPLEMENT
const Region &operator=(const Region &);
// Information necessary to manage this Region. // Information necessary to manage this Region.
RegionInfo* RI; RegionInfo* RI;
DominatorTree *DT; DominatorTree *DT;
// The exit BasicBlock of this region. // The exit BasicBlock of this region.
// (The entry BasicBlock is part of RegionNode) // (The entry BasicBlock is part of RegionNode)
BasicBlock *exit; BasicBlock *exit;
typedef std::vector<Region*> RegionSet; typedef std::vector<Region*> RegionSet;
skipping to change at line 478 skipping to change at line 474
iterator begin() { return children.begin(); } iterator begin() { return children.begin(); }
iterator end() { return children.end(); } iterator end() { return children.end(); }
const_iterator begin() const { return children.begin(); } const_iterator begin() const { return children.begin(); }
const_iterator end() const { return children.end(); } const_iterator end() const { return children.end(); }
//@} //@}
/// @name BasicBlock Iterators /// @name BasicBlock Iterators
/// ///
/// These iterators iterate over all BasicBlock RegionNodes that are /// These iterators iterate over all BasicBlocks that are contained in th
/// contained in this Region. The iterator also iterates over BasicBlocks is
/// that are elements of a subregion of this Region. It is therefore call /// Region. The iterator also iterates over BasicBlocks that are elements
ed a of
/// flat iterator. /// a subregion of this Region. It is therefore called a flat iterator.
//@{ //@{
typedef df_iterator<RegionNode*, SmallPtrSet<RegionNode*, 8>, false, template <bool IsConst>
GraphTraits<FlatIt<RegionNode*> > > block_iterator; class block_iterator_wrapper
: public df_iterator<typename conditional<IsConst,
const BasicBlock,
BasicBlock>::type*> {
typedef df_iterator<typename conditional<IsConst,
const BasicBlock,
BasicBlock>::type*>
super;
public:
typedef block_iterator_wrapper<IsConst> Self;
typedef typename super::pointer pointer;
// Construct the begin iterator.
block_iterator_wrapper(pointer Entry, pointer Exit) : super(df_begin(En
try))
{
// Mark the exit of the region as visited, so that the children of th
e
// exit and the exit itself, i.e. the block outside the region will n
ever
// be visited.
super::Visited.insert(Exit);
}
// Construct the end iterator.
block_iterator_wrapper() : super(df_end<pointer>((BasicBlock *)0)) {}
/*implicit*/ block_iterator_wrapper(super I) : super(I) {}
// FIXME: Even a const_iterator returns a non-const BasicBlock pointer.
// This was introduced for backwards compatibility, but should
// be removed as soon as all users are fixed.
BasicBlock *operator*() const {
return const_cast<BasicBlock*>(super::operator*());
}
};
typedef df_iterator<const RegionNode*, SmallPtrSet<const RegionNode*, 8>, typedef block_iterator_wrapper<false> block_iterator;
false, GraphTraits<FlatIt<const RegionNode*> > > typedef block_iterator_wrapper<true> const_block_iterator;
const_block_iterator;
block_iterator block_begin(); block_iterator block_begin() {
block_iterator block_end(); return block_iterator(getEntry(), getExit());
}
const_block_iterator block_begin() const; block_iterator block_end() {
const_block_iterator block_end() const; return block_iterator();
}
const_block_iterator block_begin() const {
return const_block_iterator(getEntry(), getExit());
}
const_block_iterator block_end() const {
return const_block_iterator();
}
//@} //@}
/// @name Element Iterators /// @name Element Iterators
/// ///
/// These iterators iterate over all BasicBlock and subregion RegionNodes that /// These iterators iterate over all BasicBlock and subregion RegionNodes that
/// are direct children of this Region. It does not iterate over any /// are direct children of this Region. It does not iterate over any
/// RegionNodes that are also element of a subregion of this Region. /// RegionNodes that are also element of a subregion of this Region.
//@{ //@{
typedef df_iterator<RegionNode*, SmallPtrSet<RegionNode*, 8>, false, typedef df_iterator<RegionNode*, SmallPtrSet<RegionNode*, 8>, false,
GraphTraits<RegionNode*> > element_iterator; GraphTraits<RegionNode*> > element_iterator;
skipping to change at line 529 skipping to change at line 564
/// @brief Analysis that detects all canonical Regions. /// @brief Analysis that detects all canonical Regions.
/// ///
/// The RegionInfo pass detects all canonical regions in a function. The Re gions /// The RegionInfo pass detects all canonical regions in a function. The Re gions
/// are connected using the parent relation. This builds a Program Structur e /// are connected using the parent relation. This builds a Program Structur e
/// Tree. /// Tree.
class RegionInfo : public FunctionPass { class RegionInfo : public FunctionPass {
typedef DenseMap<BasicBlock*,BasicBlock*> BBtoBBMap; typedef DenseMap<BasicBlock*,BasicBlock*> BBtoBBMap;
typedef DenseMap<BasicBlock*, Region*> BBtoRegionMap; typedef DenseMap<BasicBlock*, Region*> BBtoRegionMap;
typedef SmallPtrSet<Region*, 4> RegionSet; typedef SmallPtrSet<Region*, 4> RegionSet;
// DO NOT IMPLEMENT RegionInfo(const RegionInfo &) LLVM_DELETED_FUNCTION;
RegionInfo(const RegionInfo &); const RegionInfo &operator=(const RegionInfo &) LLVM_DELETED_FUNCTION;
// DO NOT IMPLEMENT
const RegionInfo &operator=(const RegionInfo &);
DominatorTree *DT; DominatorTree *DT;
PostDominatorTree *PDT; PostDominatorTree *PDT;
DominanceFrontier *DF; DominanceFrontier *DF;
/// The top level region. /// The top level region.
Region *TopLevelRegion; Region *TopLevelRegion;
/// Map every BB to the smallest region, that contains BB. /// Map every BB to the smallest region, that contains BB.
BBtoRegionMap BBtoRegion; BBtoRegionMap BBtoRegion;
 End of changes. 8 change blocks. 
26 lines changed or deleted 63 lines changed or added


 RegisterScavenging.h   RegisterScavenging.h 
skipping to change at line 21 skipping to change at line 21
// information such as unused register at any point in a machine basic bloc k. // information such as unused register at any point in a machine basic bloc k.
// It also provides a mechanism to make registers availbale by evicting the m // It also provides a mechanism to make registers availbale by evicting the m
// to spill slots. // to spill slots.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_CODEGEN_REGISTER_SCAVENGING_H #ifndef LLVM_CODEGEN_REGISTER_SCAVENGING_H
#define LLVM_CODEGEN_REGISTER_SCAVENGING_H #define LLVM_CODEGEN_REGISTER_SCAVENGING_H
#include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/ADT/BitVector.h" #include "llvm/ADT/BitVector.h"
namespace llvm { namespace llvm {
class MachineRegisterInfo; class MachineRegisterInfo;
class TargetRegisterInfo; class TargetRegisterInfo;
class TargetInstrInfo; class TargetInstrInfo;
class TargetRegisterClass; class TargetRegisterClass;
class RegScavenger { class RegScavenger {
skipping to change at line 62 skipping to change at line 63
const TargetRegisterClass *ScavengedRC; const TargetRegisterClass *ScavengedRC;
/// ScavengeRestore - Instruction that restores the scavenged register fr om /// ScavengeRestore - Instruction that restores the scavenged register fr om
/// stack. /// stack.
const MachineInstr *ScavengeRestore; const MachineInstr *ScavengeRestore;
/// CalleeSavedrRegs - A bitvector of callee saved registers for the targ et. /// CalleeSavedrRegs - A bitvector of callee saved registers for the targ et.
/// ///
BitVector CalleeSavedRegs; BitVector CalleeSavedRegs;
/// ReservedRegs - A bitvector of reserved registers.
///
BitVector ReservedRegs;
/// RegsAvailable - The current state of all the physical registers immed iately /// RegsAvailable - The current state of all the physical registers immed iately
/// before MBBI. One bit per physical register. If bit is set that means it's /// before MBBI. One bit per physical register. If bit is set that means it's
/// available, unset means the register is currently being used. /// available, unset means the register is currently being used.
BitVector RegsAvailable; BitVector RegsAvailable;
// These BitVectors are only used internally to forward(). They are membe rs // These BitVectors are only used internally to forward(). They are membe rs
// to avoid frequent reallocations. // to avoid frequent reallocations.
BitVector KillRegs, DefRegs; BitVector KillRegs, DefRegs;
public: public:
skipping to change at line 133 skipping to change at line 130
MachineBasicBlock::iterator I, int SPAdj); MachineBasicBlock::iterator I, int SPAdj);
unsigned scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj) { unsigned scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj) {
return scavengeRegister(RegClass, MBBI, SPAdj); return scavengeRegister(RegClass, MBBI, SPAdj);
} }
/// setUsed - Tell the scavenger a register is used. /// setUsed - Tell the scavenger a register is used.
/// ///
void setUsed(unsigned Reg); void setUsed(unsigned Reg);
private: private:
/// isReserved - Returns true if a register is reserved. It is never "unu sed". /// isReserved - Returns true if a register is reserved. It is never "unu sed".
bool isReserved(unsigned Reg) const { return ReservedRegs.test(Reg); } bool isReserved(unsigned Reg) const { return MRI->isReserved(Reg); }
/// isUsed / isUnused - Test if a register is currently being used. /// isUsed / isUnused - Test if a register is currently being used.
/// ///
bool isUsed(unsigned Reg) const { bool isUsed(unsigned Reg) const {
return !RegsAvailable.test(Reg) || ReservedRegs.test(Reg); return !RegsAvailable.test(Reg) || isReserved(Reg);
} }
/// isAliasUsed - Is Reg or an alias currently in use? /// isAliasUsed - Is Reg or an alias currently in use?
bool isAliasUsed(unsigned Reg) const; bool isAliasUsed(unsigned Reg) const;
/// setUsed / setUnused - Mark the state of one or a number of registers. /// setUsed / setUnused - Mark the state of one or a number of registers.
/// ///
void setUsed(BitVector &Regs) { void setUsed(BitVector &Regs) {
RegsAvailable.reset(Regs); RegsAvailable.reset(Regs);
} }
 End of changes. 4 change blocks. 
6 lines changed or deleted 3 lines changed or added


 Registry.h   Registry.h 
skipping to change at line 39 skipping to change at line 39
const char *getName() const { return Name; } const char *getName() const { return Name; }
const char *getDesc() const { return Desc; } const char *getDesc() const { return Desc; }
T *instantiate() const { return Ctor(); } T *instantiate() const { return Ctor(); }
}; };
/// Traits for registry entries. If using other than SimpleRegistryEntry, it /// Traits for registry entries. If using other than SimpleRegistryEntry, it
/// is necessary to define an alternate traits class. /// is necessary to define an alternate traits class.
template <typename T> template <typename T>
class RegistryTraits { class RegistryTraits {
RegistryTraits(); // Do not implement. RegistryTraits() LLVM_DELETED_FUNCTION;
public: public:
typedef SimpleRegistryEntry<T> entry; typedef SimpleRegistryEntry<T> entry;
/// nameof/descof - Accessors for name and description of entries. Thes e are /// nameof/descof - Accessors for name and description of entries. Thes e are
// used to generate help for command-line options. // used to generate help for command-line options.
static const char *nameof(const entry &Entry) { return Entry.getName(); } static const char *nameof(const entry &Entry) { return Entry.getName(); }
static const char *descof(const entry &Entry) { return Entry.getDesc(); } static const char *descof(const entry &Entry) { return Entry.getDesc(); }
}; };
skipping to change at line 64 skipping to change at line 64
class Registry { class Registry {
public: public:
typedef U traits; typedef U traits;
typedef typename U::entry entry; typedef typename U::entry entry;
class node; class node;
class listener; class listener;
class iterator; class iterator;
private: private:
Registry(); // Do not implement. Registry() LLVM_DELETED_FUNCTION;
static void Announce(const entry &E) { static void Announce(const entry &E) {
for (listener *Cur = ListenerHead; Cur; Cur = Cur->Next) for (listener *Cur = ListenerHead; Cur; Cur = Cur->Next)
Cur->registered(E); Cur->registered(E);
} }
friend class node; friend class node;
static node *Head, *Tail; static node *Head, *Tail;
friend class listener; friend class listener;
skipping to change at line 119 skipping to change at line 119
const entry &operator*() const { return Cur->Val; } const entry &operator*() const { return Cur->Val; }
const entry *operator->() const { return &Cur->Val; } const entry *operator->() const { return &Cur->Val; }
}; };
static iterator begin() { return iterator(Head); } static iterator begin() { return iterator(Head); }
static iterator end() { return iterator(0); } static iterator end() { return iterator(0); }
/// Abstract base class for registry listeners, which are informed when new /// Abstract base class for registry listeners, which are informed when new
/// entries are added to the registry. Simply subclass and instantiate: /// entries are added to the registry. Simply subclass and instantiate:
/// ///
/// \code
/// class CollectorPrinter : public Registry<Collector>::listener { /// class CollectorPrinter : public Registry<Collector>::listener {
/// protected: /// protected:
/// void registered(const Registry<Collector>::entry &e) { /// void registered(const Registry<Collector>::entry &e) {
/// cerr << "collector now available: " << e->getName() << "\n"; /// cerr << "collector now available: " << e->getName() << "\n";
/// } /// }
/// ///
/// public: /// public:
/// CollectorPrinter() { init(); } // Print those already register ed. /// CollectorPrinter() { init(); } // Print those already register ed.
/// }; /// };
/// ///
/// CollectorPrinter Printer; /// CollectorPrinter Printer;
/// /// \endcode
class listener { class listener {
listener *Prev, *Next; listener *Prev, *Next;
friend void Registry::Announce(const entry &E); friend void Registry::Announce(const entry &E);
protected: protected:
/// Called when an entry is added to the registry. /// Called when an entry is added to the registry.
/// ///
virtual void registered(const entry &) = 0; virtual void registered(const entry &) = 0;
 End of changes. 4 change blocks. 
3 lines changed or deleted 4 lines changed or added


 RuntimeDyld.h   RuntimeDyld.h 
skipping to change at line 18 skipping to change at line 18
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// //
// Interface for the runtime dynamic linker facilities of the MC-JIT. // Interface for the runtime dynamic linker facilities of the MC-JIT.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_RUNTIME_DYLD_H #ifndef LLVM_RUNTIME_DYLD_H
#define LLVM_RUNTIME_DYLD_H #define LLVM_RUNTIME_DYLD_H
#include "llvm/ADT/StringRef.h" #include "llvm/ADT/StringRef.h"
#include "llvm/ExecutionEngine/ObjectBuffer.h"
#include "llvm/Support/Memory.h" #include "llvm/Support/Memory.h"
namespace llvm { namespace llvm {
class RuntimeDyldImpl; class RuntimeDyldImpl;
class MemoryBuffer; class ObjectImage;
// RuntimeDyld clients often want to handle the memory management of // RuntimeDyld clients often want to handle the memory management of
// what gets placed where. For JIT clients, this is an abstraction layer // what gets placed where. For JIT clients, this is the subset of
// over the JITMemoryManager, which references objects by their source // JITMemoryManager required for dynamic loading of binaries.
// representations in LLVM IR. //
// FIXME: As the RuntimeDyld fills out, additional routines will be needed // FIXME: As the RuntimeDyld fills out, additional routines will be needed
// for the varying types of objects to be allocated. // for the varying types of objects to be allocated.
class RTDyldMemoryManager { class RTDyldMemoryManager {
RTDyldMemoryManager(const RTDyldMemoryManager&); // DO NOT IMPLEMENT RTDyldMemoryManager(const RTDyldMemoryManager&) LLVM_DELETED_FUNCTION;
void operator=(const RTDyldMemoryManager&); // DO NOT IMPLEMENT void operator=(const RTDyldMemoryManager&) LLVM_DELETED_FUNCTION;
public: public:
RTDyldMemoryManager() {} RTDyldMemoryManager() {}
virtual ~RTDyldMemoryManager(); virtual ~RTDyldMemoryManager();
/// allocateCodeSection - Allocate a memory block of (at least) the given /// allocateCodeSection - Allocate a memory block of (at least) the given
/// size suitable for executable code. /// size suitable for executable code. The SectionID is a unique identifi
er
/// assigned by the JIT engine, and optionally recorded by the memory man
ager
/// to access a loaded section.
virtual uint8_t *allocateCodeSection(uintptr_t Size, unsigned Alignment, virtual uint8_t *allocateCodeSection(uintptr_t Size, unsigned Alignment,
unsigned SectionID) = 0; unsigned SectionID) = 0;
/// allocateDataSection - Allocate a memory block of (at least) the given /// allocateDataSection - Allocate a memory block of (at least) the given
/// size suitable for data. /// size suitable for data. The SectionID is a unique identifier
/// assigned by the JIT engine, and optionally recorded by the memory man
ager
/// to access a loaded section.
virtual uint8_t *allocateDataSection(uintptr_t Size, unsigned Alignment, virtual uint8_t *allocateDataSection(uintptr_t Size, unsigned Alignment,
unsigned SectionID) = 0; unsigned SectionID) = 0;
/// getPointerToNamedFunction - This method returns the address of the
/// specified function. As such it is only useful for resolving library
/// symbols, not code generated symbols.
///
/// If AbortOnFailure is false and no function with the given name is
/// found, this function returns a null pointer. Otherwise, it prints a
/// message to stderr and aborts.
virtual void *getPointerToNamedFunction(const std::string &Name, virtual void *getPointerToNamedFunction(const std::string &Name,
bool AbortOnFailure = true) = 0; bool AbortOnFailure = true) = 0;
}; };
class RuntimeDyld { class RuntimeDyld {
RuntimeDyld(const RuntimeDyld &); // DO NOT IMPLEMENT RuntimeDyld(const RuntimeDyld &) LLVM_DELETED_FUNCTION;
void operator=(const RuntimeDyld &); // DO NOT IMPLEMENT void operator=(const RuntimeDyld &) LLVM_DELETED_FUNCTION;
// RuntimeDyldImpl is the actual class. RuntimeDyld is just the public // RuntimeDyldImpl is the actual class. RuntimeDyld is just the public
// interface. // interface.
RuntimeDyldImpl *Dyld; RuntimeDyldImpl *Dyld;
RTDyldMemoryManager *MM; RTDyldMemoryManager *MM;
protected: protected:
// Change the address associated with a section when resolving relocation s. // Change the address associated with a section when resolving relocation s.
// Any relocations already associated with the symbol will be re-resolved . // Any relocations already associated with the symbol will be re-resolved .
void reassignSectionAddress(unsigned SectionID, uint64_t Addr); void reassignSectionAddress(unsigned SectionID, uint64_t Addr);
public: public:
RuntimeDyld(RTDyldMemoryManager*); RuntimeDyld(RTDyldMemoryManager *);
~RuntimeDyld(); ~RuntimeDyld();
bool loadObject(MemoryBuffer *InputBuffer); /// loadObject - prepare the object contained in the input buffer for
// Get the address of our local copy of the symbol. This may or may not /// execution. Ownership of the input buffer is transferred to the
// be the address used for relocation (clients can copy the data around /// ObjectImage instance returned from this function if successful.
// and resolve relocatons based on where they put it). /// In the case of load failure, the input buffer will be deleted.
ObjectImage *loadObject(ObjectBuffer *InputBuffer);
/// Get the address of our local copy of the symbol. This may or may not
/// be the address used for relocation (clients can copy the data around
/// and resolve relocatons based on where they put it).
void *getSymbolAddress(StringRef Name); void *getSymbolAddress(StringRef Name);
// Resolve the relocations for all symbols we currently know about.
/// Get the address of the target copy of the symbol. This is the address
/// used for relocation.
uint64_t getSymbolLoadAddress(StringRef Name);
/// Resolve the relocations for all symbols we currently know about.
void resolveRelocations(); void resolveRelocations();
/// mapSectionAddress - map a section to its target address space value. /// mapSectionAddress - map a section to its target address space value.
/// Map the address of a JIT section as returned from the memory manager /// Map the address of a JIT section as returned from the memory manager
/// to the address in the target process as the running code will see it. /// to the address in the target process as the running code will see it.
/// This is the address which will be used for relocation resolution. /// This is the address which will be used for relocation resolution.
void mapSectionAddress(void *LocalAddress, uint64_t TargetAddress); void mapSectionAddress(const void *LocalAddress, uint64_t TargetAddress);
StringRef getErrorString(); StringRef getErrorString();
}; };
} // end namespace llvm } // end namespace llvm
#endif #endif
 End of changes. 12 change blocks. 
17 lines changed or deleted 42 lines changed or added


 SMLoc.h   SMLoc.h 
skipping to change at line 27 skipping to change at line 27
#include <cassert> #include <cassert>
namespace llvm { namespace llvm {
/// SMLoc - Represents a location in source code. /// SMLoc - Represents a location in source code.
class SMLoc { class SMLoc {
const char *Ptr; const char *Ptr;
public: public:
SMLoc() : Ptr(0) {} SMLoc() : Ptr(0) {}
SMLoc(const SMLoc &RHS) : Ptr(RHS.Ptr) {}
bool isValid() const { return Ptr != 0; } bool isValid() const { return Ptr != 0; }
bool operator==(const SMLoc &RHS) const { return RHS.Ptr == Ptr; } bool operator==(const SMLoc &RHS) const { return RHS.Ptr == Ptr; }
bool operator!=(const SMLoc &RHS) const { return RHS.Ptr != Ptr; } bool operator!=(const SMLoc &RHS) const { return RHS.Ptr != Ptr; }
const char *getPointer() const { return Ptr; } const char *getPointer() const { return Ptr; }
static SMLoc getFromPointer(const char *Ptr) { static SMLoc getFromPointer(const char *Ptr) {
SMLoc L; SMLoc L;
skipping to change at line 51 skipping to change at line 50
}; };
/// SMRange - Represents a range in source code. Note that unlike standard STL /// SMRange - Represents a range in source code. Note that unlike standard STL
/// ranges, the locations specified are considered to be *inclusive*. For /// ranges, the locations specified are considered to be *inclusive*. For
/// example, [X,X] *does* include X, it isn't an empty range. /// example, [X,X] *does* include X, it isn't an empty range.
class SMRange { class SMRange {
public: public:
SMLoc Start, End; SMLoc Start, End;
SMRange() {} SMRange() {}
SMRange(SMLoc Start, SMLoc End) : Start(Start), End(End) { SMRange(SMLoc St, SMLoc En) : Start(St), End(En) {
assert(Start.isValid() == End.isValid() && assert(Start.isValid() == End.isValid() &&
"Start and end should either both be valid or both be invalid!") ; "Start and end should either both be valid or both be invalid!") ;
} }
bool isValid() const { return Start.isValid(); } bool isValid() const { return Start.isValid(); }
}; };
} // end namespace llvm } // end namespace llvm
#endif #endif
 End of changes. 2 change blocks. 
2 lines changed or deleted 1 lines changed or added


 SSAUpdater.h   SSAUpdater.h 
skipping to change at line 112 skipping to change at line 112
/// RewriteUseAfterInsertions - Rewrite a use, just like RewriteUse. How ever, /// RewriteUseAfterInsertions - Rewrite a use, just like RewriteUse. How ever,
/// this version of the method can rewrite uses in the same block as a /// this version of the method can rewrite uses in the same block as a
/// definition, because it assumes that all uses of a value are below any /// definition, because it assumes that all uses of a value are below any
/// inserted values. /// inserted values.
void RewriteUseAfterInsertions(Use &U); void RewriteUseAfterInsertions(Use &U);
private: private:
Value *GetValueAtEndOfBlockInternal(BasicBlock *BB); Value *GetValueAtEndOfBlockInternal(BasicBlock *BB);
void operator=(const SSAUpdater&); // DO NOT IMPLEMENT void operator=(const SSAUpdater&) LLVM_DELETED_FUNCTION;
SSAUpdater(const SSAUpdater&); // DO NOT IMPLEMENT SSAUpdater(const SSAUpdater&) LLVM_DELETED_FUNCTION;
}; };
/// LoadAndStorePromoter - This little helper class provides a convenient w ay to /// LoadAndStorePromoter - This little helper class provides a convenient w ay to
/// promote a collection of loads and stores into SSA Form using the SSAUpd ater. /// promote a collection of loads and stores into SSA Form using the SSAUpd ater.
/// This handles complexities that SSAUpdater doesn't, such as multiple loa ds /// This handles complexities that SSAUpdater doesn't, such as multiple loa ds
/// and stores in one block. /// and stores in one block.
/// ///
/// Clients of this class are expected to subclass this and implement the /// Clients of this class are expected to subclass this and implement the
/// virtual methods. /// virtual methods.
/// ///
 End of changes. 1 change blocks. 
2 lines changed or deleted 2 lines changed or added


 STLExtras.h   STLExtras.h 
skipping to change at line 33 skipping to change at line 33
#include <iterator> #include <iterator>
#include <utility> // for std::pair #include <utility> // for std::pair
namespace llvm { namespace llvm {
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// Extra additions to <functional> // Extra additions to <functional>
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
template<class Ty> template<class Ty>
struct identity : public std::unary_function<Ty, Ty> {
Ty &operator()(Ty &self) const {
return self;
}
const Ty &operator()(const Ty &self) const {
return self;
}
};
template<class Ty>
struct less_ptr : public std::binary_function<Ty, Ty, bool> { struct less_ptr : public std::binary_function<Ty, Ty, bool> {
bool operator()(const Ty* left, const Ty* right) const { bool operator()(const Ty* left, const Ty* right) const {
return *left < *right; return *left < *right;
} }
}; };
template<class Ty> template<class Ty>
struct greater_ptr : public std::binary_function<Ty, Ty, bool> { struct greater_ptr : public std::binary_function<Ty, Ty, bool> {
bool operator()(const Ty* left, const Ty* right) const { bool operator()(const Ty* left, const Ty* right) const {
return *right < *left; return *right < *left;
} }
}; };
// deleter - Very very very simple method that is used to invoke operator // deleter - Very very very simple method that is used to invoke operator
// delete on something. It is used like this: // delete on something. It is used like this:
// //
// for_each(V.begin(), B.end(), deleter<Interval>); // for_each(V.begin(), B.end(), deleter<Interval>);
// //
template <class T> template <class T>
static inline void deleter(T *Ptr) { inline void deleter(T *Ptr) {
delete Ptr; delete Ptr;
} }
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// Extra additions to <iterator> // Extra additions to <iterator>
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// mapped_iterator - This is a simple iterator adapter that causes a functi on to // mapped_iterator - This is a simple iterator adapter that causes a functi on to
// be dereferenced whenever operator* is invoked on the iterator. // be dereferenced whenever operator* is invoked on the iterator.
// //
skipping to change at line 227 skipping to change at line 237
/// Find the length of an array. /// Find the length of an array.
template<class T, std::size_t N> template<class T, std::size_t N>
inline size_t array_lengthof(T (&)[N]) { inline size_t array_lengthof(T (&)[N]) {
return N; return N;
} }
/// array_pod_sort_comparator - This is helper function for array_pod_sort, /// array_pod_sort_comparator - This is helper function for array_pod_sort,
/// which just uses operator< on T. /// which just uses operator< on T.
template<typename T> template<typename T>
static inline int array_pod_sort_comparator(const void *P1, const void *P2) { inline int array_pod_sort_comparator(const void *P1, const void *P2) {
if (*reinterpret_cast<const T*>(P1) < *reinterpret_cast<const T*>(P2)) if (*reinterpret_cast<const T*>(P1) < *reinterpret_cast<const T*>(P2))
return -1; return -1;
if (*reinterpret_cast<const T*>(P2) < *reinterpret_cast<const T*>(P1)) if (*reinterpret_cast<const T*>(P2) < *reinterpret_cast<const T*>(P1))
return 1; return 1;
return 0; return 0;
} }
/// get_array_pad_sort_comparator - This is an internal helper function use d to /// get_array_pad_sort_comparator - This is an internal helper function use d to
/// get type deduction of T right. /// get type deduction of T right.
template<typename T> template<typename T>
static int (*get_array_pad_sort_comparator(const T &)) inline int (*get_array_pad_sort_comparator(const T &))
(const void*, const void*) { (const void*, const void*) {
return array_pod_sort_comparator<T>; return array_pod_sort_comparator<T>;
} }
/// array_pod_sort - This sorts an array with the specified start and end /// array_pod_sort - This sorts an array with the specified start and end
/// extent. This is just like std::sort, except that it calls qsort instea d of /// extent. This is just like std::sort, except that it calls qsort instea d of
/// using an inlined template. qsort is slightly slower than std::sort, bu t /// using an inlined template. qsort is slightly slower than std::sort, bu t
/// most sorts are not performance critical in LLVM and std::sort has to be /// most sorts are not performance critical in LLVM and std::sort has to be
/// template instantiated for each type, leading to significant measured co de /// template instantiated for each type, leading to significant measured co de
/// bloat. This function should generally be used instead of std::sort whe re /// bloat. This function should generally be used instead of std::sort whe re
/// possible. /// possible.
/// ///
/// This function assumes that you have simple POD-like types that can be /// This function assumes that you have simple POD-like types that can be
/// compared with operator< and can be moved with memcpy. If this isn't tr ue, /// compared with operator< and can be moved with memcpy. If this isn't tr ue,
/// you should use std::sort. /// you should use std::sort.
/// ///
/// NOTE: If qsort_r were portable, we could allow a custom comparator and /// NOTE: If qsort_r were portable, we could allow a custom comparator and
/// default to std::less. /// default to std::less.
template<class IteratorTy> template<class IteratorTy>
static inline void array_pod_sort(IteratorTy Start, IteratorTy End) { inline void array_pod_sort(IteratorTy Start, IteratorTy End) {
// Don't dereference start iterator of empty sequence. // Don't dereference start iterator of empty sequence.
if (Start == End) return; if (Start == End) return;
qsort(&*Start, End-Start, sizeof(*Start), qsort(&*Start, End-Start, sizeof(*Start),
get_array_pad_sort_comparator(*Start)); get_array_pad_sort_comparator(*Start));
} }
template<class IteratorTy> template<class IteratorTy>
static inline void array_pod_sort(IteratorTy Start, IteratorTy End, inline void array_pod_sort(IteratorTy Start, IteratorTy End,
int (*Compare)(const void*, const void*)) { int (*Compare)(const void*, const void*)) {
// Don't dereference start iterator of empty sequence. // Don't dereference start iterator of empty sequence.
if (Start == End) return; if (Start == End) return;
qsort(&*Start, End-Start, sizeof(*Start), Compare); qsort(&*Start, End-Start, sizeof(*Start), Compare);
} }
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// Extra additions to <algorithm> // Extra additions to <algorithm>
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
 End of changes. 6 change blocks. 
5 lines changed or deleted 15 lines changed or added


 Scalar.h   Scalar.h 
skipping to change at line 73 skipping to change at line 73
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// //
// AggressiveDCE - This pass uses the SSA based Aggressive DCE algorithm. This // AggressiveDCE - This pass uses the SSA based Aggressive DCE algorithm. This
// algorithm assumes instructions are dead until proven otherwise, which ma kes // algorithm assumes instructions are dead until proven otherwise, which ma kes
// it more successful are removing non-obviously dead instructions. // it more successful are removing non-obviously dead instructions.
// //
FunctionPass *createAggressiveDCEPass(); FunctionPass *createAggressiveDCEPass();
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// //
// SROA - Replace aggregates or pieces of aggregates with scalar SSA values
.
//
FunctionPass *createSROAPass(bool RequiresDomTree = true);
//===----------------------------------------------------------------------
===//
//
// ScalarReplAggregates - Break up alloca's of aggregates into multiple all ocas // ScalarReplAggregates - Break up alloca's of aggregates into multiple all ocas
// if possible. // if possible.
// //
FunctionPass *createScalarReplAggregatesPass(signed Threshold = -1, FunctionPass *createScalarReplAggregatesPass(signed Threshold = -1,
bool UseDomTree = true); bool UseDomTree = true,
signed StructMemberThreshold =
-1,
signed ArrayElementThreshold =
-1,
signed ScalarLoadThreshold = -
1);
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// //
// InductionVariableSimplify - Transform induction variables in a program t o all // InductionVariableSimplify - Transform induction variables in a program t o all
// use a single canonical induction variable per loop. // use a single canonical induction variable per loop.
// //
Pass *createIndVarSimplifyPass(); Pass *createIndVarSimplifyPass();
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// //
 End of changes. 2 change blocks. 
1 lines changed or deleted 15 lines changed or added


 ScalarEvolution.h   ScalarEvolution.h 
skipping to change at line 33 skipping to change at line 33
#include "llvm/Pass.h" #include "llvm/Pass.h"
#include "llvm/Instructions.h" #include "llvm/Instructions.h"
#include "llvm/Function.h" #include "llvm/Function.h"
#include "llvm/Operator.h" #include "llvm/Operator.h"
#include "llvm/Support/DataTypes.h" #include "llvm/Support/DataTypes.h"
#include "llvm/Support/ValueHandle.h" #include "llvm/Support/ValueHandle.h"
#include "llvm/Support/Allocator.h" #include "llvm/Support/Allocator.h"
#include "llvm/Support/ConstantRange.h" #include "llvm/Support/ConstantRange.h"
#include "llvm/ADT/FoldingSet.h" #include "llvm/ADT/FoldingSet.h"
#include "llvm/ADT/DenseMap.h" #include "llvm/ADT/DenseSet.h"
#include <map> #include <map>
namespace llvm { namespace llvm {
class APInt; class APInt;
class Constant; class Constant;
class ConstantInt; class ConstantInt;
class DominatorTree; class DominatorTree;
class Type; class Type;
class ScalarEvolution; class ScalarEvolution;
class TargetData; class DataLayout;
class TargetLibraryInfo; class TargetLibraryInfo;
class LLVMContext; class LLVMContext;
class Loop; class Loop;
class LoopInfo; class LoopInfo;
class Operator; class Operator;
class SCEVUnknown; class SCEVUnknown;
class SCEV; class SCEV;
template<> struct FoldingSetTrait<SCEV>; template<> struct FoldingSetTrait<SCEV>;
/// SCEV - This class represents an analyzed expression in the program. These /// SCEV - This class represents an analyzed expression in the program. These
skipping to change at line 73 skipping to change at line 73
// The SCEV baseclass this node corresponds to // The SCEV baseclass this node corresponds to
const unsigned short SCEVType; const unsigned short SCEVType;
protected: protected:
/// SubclassData - This field is initialized to zero and may be used in /// SubclassData - This field is initialized to zero and may be used in
/// subclasses to store miscellaneous information. /// subclasses to store miscellaneous information.
unsigned short SubclassData; unsigned short SubclassData;
private: private:
SCEV(const SCEV &); // DO NOT IMPLEMENT SCEV(const SCEV &) LLVM_DELETED_FUNCTION;
void operator=(const SCEV &); // DO NOT IMPLEMENT void operator=(const SCEV &) LLVM_DELETED_FUNCTION;
public: public:
/// NoWrapFlags are bitfield indices into SubclassData. /// NoWrapFlags are bitfield indices into SubclassData.
/// ///
/// Add and Mul expressions may have no-unsigned-wrap <NUW> or /// Add and Mul expressions may have no-unsigned-wrap <NUW> or
/// no-signed-wrap <NSW> properties, which are derived from the IR /// no-signed-wrap <NSW> properties, which are derived from the IR
/// operator. NSW is a misnomer that we use to mean no signed overflow or /// operator. NSW is a misnomer that we use to mean no signed overflow or
/// underflow. /// underflow.
/// ///
/// AddRec expression may have a no-self-wraparound <NW> property if th e /// AddRec expression may have a no-self-wraparound <NW> property if th e
skipping to change at line 165 skipping to change at line 165
/// SCEVCouldNotCompute - An object of this class is returned by queries that /// SCEVCouldNotCompute - An object of this class is returned by queries that
/// could not be answered. For example, if you ask for the number of /// could not be answered. For example, if you ask for the number of
/// iterations of a linked-list traversal loop, you will get one of these . /// iterations of a linked-list traversal loop, you will get one of these .
/// None of the standard SCEV operations are valid on this class, it is j ust a /// None of the standard SCEV operations are valid on this class, it is j ust a
/// marker. /// marker.
struct SCEVCouldNotCompute : public SCEV { struct SCEVCouldNotCompute : public SCEV {
SCEVCouldNotCompute(); SCEVCouldNotCompute();
/// Methods for support type inquiry through isa, cast, and dyn_cast: /// Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const SCEVCouldNotCompute *S) { return true; }
static bool classof(const SCEV *S); static bool classof(const SCEV *S);
}; };
/// ScalarEvolution - This class is the main scalar evolution driver. Be cause /// ScalarEvolution - This class is the main scalar evolution driver. Be cause
/// client code (intentionally) can't do much with the SCEV objects direc tly, /// client code (intentionally) can't do much with the SCEV objects direc tly,
/// they must ask this class for services. /// they must ask this class for services.
/// ///
class ScalarEvolution : public FunctionPass { class ScalarEvolution : public FunctionPass {
public: public:
/// LoopDisposition - An enum describing the relationship between a /// LoopDisposition - An enum describing the relationship between a
skipping to change at line 230 skipping to change at line 229
/// F - The function we are analyzing. /// F - The function we are analyzing.
/// ///
Function *F; Function *F;
/// LI - The loop information for the function we are currently analyzi ng. /// LI - The loop information for the function we are currently analyzi ng.
/// ///
LoopInfo *LI; LoopInfo *LI;
/// TD - The target data information for the target we are targeting. /// TD - The target data information for the target we are targeting.
/// ///
TargetData *TD; DataLayout *TD;
/// TLI - The target library information for the target we are targetin g. /// TLI - The target library information for the target we are targetin g.
/// ///
TargetLibraryInfo *TLI; TargetLibraryInfo *TLI;
/// DT - The dominator tree. /// DT - The dominator tree.
/// ///
DominatorTree *DT; DominatorTree *DT;
/// CouldNotCompute - This SCEV is used to represent unknown trip /// CouldNotCompute - This SCEV is used to represent unknown trip
skipping to change at line 253 skipping to change at line 252
/// ValueExprMapType - The typedef for ValueExprMap. /// ValueExprMapType - The typedef for ValueExprMap.
/// ///
typedef DenseMap<SCEVCallbackVH, const SCEV *, DenseMapInfo<Value *> > typedef DenseMap<SCEVCallbackVH, const SCEV *, DenseMapInfo<Value *> >
ValueExprMapType; ValueExprMapType;
/// ValueExprMap - This is a cache of the values we have analyzed so fa r. /// ValueExprMap - This is a cache of the values we have analyzed so fa r.
/// ///
ValueExprMapType ValueExprMap; ValueExprMapType ValueExprMap;
/// Mark predicate values currently being processed by isImpliedCond.
DenseSet<Value*> PendingLoopPredicates;
/// ExitLimit - Information about the number of loop iterations for /// ExitLimit - Information about the number of loop iterations for
/// which a loop exit's branch condition evaluates to the not-taken pat h. /// which a loop exit's branch condition evaluates to the not-taken pat h.
/// This is a temporary pair of exact and max expressions that are /// This is a temporary pair of exact and max expressions that are
/// eventually summarized in ExitNotTakenInfo and BackedgeTakenInfo. /// eventually summarized in ExitNotTakenInfo and BackedgeTakenInfo.
struct ExitLimit { struct ExitLimit {
const SCEV *Exact; const SCEV *Exact;
const SCEV *Max; const SCEV *Max;
/*implicit*/ ExitLimit(const SCEV *E) : Exact(E), Max(E) {} /*implicit*/ ExitLimit(const SCEV *E) : Exact(E), Max(E) {}
skipping to change at line 837 skipping to change at line 839
bool isKnownPredicate(ICmpInst::Predicate Pred, bool isKnownPredicate(ICmpInst::Predicate Pred,
const SCEV *LHS, const SCEV *RHS); const SCEV *LHS, const SCEV *RHS);
/// SimplifyICmpOperands - Simplify LHS and RHS in a comparison with /// SimplifyICmpOperands - Simplify LHS and RHS in a comparison with
/// predicate Pred. Return true iff any changes were made. If the /// predicate Pred. Return true iff any changes were made. If the
/// operands are provably equal or inequal, LHS and RHS are set to /// operands are provably equal or inequal, LHS and RHS are set to
/// the same value and Pred is set to either ICMP_EQ or ICMP_NE. /// the same value and Pred is set to either ICMP_EQ or ICMP_NE.
/// ///
bool SimplifyICmpOperands(ICmpInst::Predicate &Pred, bool SimplifyICmpOperands(ICmpInst::Predicate &Pred,
const SCEV *&LHS, const SCEV *&LHS,
const SCEV *&RHS); const SCEV *&RHS,
unsigned Depth = 0);
/// getLoopDisposition - Return the "disposition" of the given SCEV wit h /// getLoopDisposition - Return the "disposition" of the given SCEV wit h
/// respect to the given loop. /// respect to the given loop.
LoopDisposition getLoopDisposition(const SCEV *S, const Loop *L); LoopDisposition getLoopDisposition(const SCEV *S, const Loop *L);
/// isLoopInvariant - Return true if the value of the given SCEV is /// isLoopInvariant - Return true if the value of the given SCEV is
/// unchanging in the specified loop. /// unchanging in the specified loop.
bool isLoopInvariant(const SCEV *S, const Loop *L); bool isLoopInvariant(const SCEV *S, const Loop *L);
/// hasComputableLoopEvolution - Return true if the given SCEV changes value /// hasComputableLoopEvolution - Return true if the given SCEV changes value
skipping to change at line 873 skipping to change at line 876
bool properlyDominates(const SCEV *S, const BasicBlock *BB); bool properlyDominates(const SCEV *S, const BasicBlock *BB);
/// hasOperand - Test whether the given SCEV has Op as a direct or /// hasOperand - Test whether the given SCEV has Op as a direct or
/// indirect operand. /// indirect operand.
bool hasOperand(const SCEV *S, const SCEV *Op) const; bool hasOperand(const SCEV *S, const SCEV *Op) const;
virtual bool runOnFunction(Function &F); virtual bool runOnFunction(Function &F);
virtual void releaseMemory(); virtual void releaseMemory();
virtual void getAnalysisUsage(AnalysisUsage &AU) const; virtual void getAnalysisUsage(AnalysisUsage &AU) const;
virtual void print(raw_ostream &OS, const Module* = 0) const; virtual void print(raw_ostream &OS, const Module* = 0) const;
virtual void verifyAnalysis() const;
private: private:
FoldingSet<SCEV> UniqueSCEVs; FoldingSet<SCEV> UniqueSCEVs;
BumpPtrAllocator SCEVAllocator; BumpPtrAllocator SCEVAllocator;
/// FirstUnknown - The head of a linked list of all SCEVUnknown /// FirstUnknown - The head of a linked list of all SCEVUnknown
/// values that have been allocated. This is used by releaseMemory /// values that have been allocated. This is used by releaseMemory
/// to locate them all and call their destructors. /// to locate them all and call their destructors.
SCEVUnknown *FirstUnknown; SCEVUnknown *FirstUnknown;
}; };
 End of changes. 8 change blocks. 
7 lines changed or deleted 11 lines changed or added


 ScalarEvolutionExpander.h   ScalarEvolutionExpander.h 
skipping to change at line 17 skipping to change at line 17
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// //
// This file defines the classes used to generate code from scalar expressi ons. // This file defines the classes used to generate code from scalar expressi ons.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_ANALYSIS_SCALAREVOLUTION_EXPANDER_H #ifndef LLVM_ANALYSIS_SCALAREVOLUTION_EXPANDER_H
#define LLVM_ANALYSIS_SCALAREVOLUTION_EXPANDER_H #define LLVM_ANALYSIS_SCALAREVOLUTION_EXPANDER_H
#include "llvm/IRBuilder.h"
#include "llvm/Analysis/ScalarEvolutionExpressions.h" #include "llvm/Analysis/ScalarEvolutionExpressions.h"
#include "llvm/Analysis/ScalarEvolutionNormalization.h" #include "llvm/Analysis/ScalarEvolutionNormalization.h"
#include "llvm/Support/IRBuilder.h"
#include "llvm/Support/TargetFolder.h" #include "llvm/Support/TargetFolder.h"
#include "llvm/Support/ValueHandle.h" #include "llvm/Support/ValueHandle.h"
#include <set> #include <set>
namespace llvm { namespace llvm {
class TargetLowering; class TargetLowering;
/// Return true if the given expression is safe to expand in the sense th
at
/// all materialized values are safe to speculate.
bool isSafeToExpand(const SCEV *S);
/// SCEVExpander - This class uses information about analyze scalars to /// SCEVExpander - This class uses information about analyze scalars to
/// rewrite expressions in canonical form. /// rewrite expressions in canonical form.
/// ///
/// Clients should create an instance of this class when rewriting is nee ded, /// Clients should create an instance of this class when rewriting is nee ded,
/// and destroy it when finished to allow the release of the associated /// and destroy it when finished to allow the release of the associated
/// memory. /// memory.
class SCEVExpander : public SCEVVisitor<SCEVExpander, Value*> { class SCEVExpander : public SCEVVisitor<SCEVExpander, Value*> {
ScalarEvolution &SE; ScalarEvolution &SE;
// New instructions receive a name to identifies them with the current pass. // New instructions receive a name to identifies them with the current pass.
 End of changes. 3 change blocks. 
1 lines changed or deleted 6 lines changed or added


 ScalarEvolutionExpressions.h   ScalarEvolutionExpressions.h 
skipping to change at line 18 skipping to change at line 18
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// //
// This file defines the classes used to represent and build scalar express ions. // This file defines the classes used to represent and build scalar express ions.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_ANALYSIS_SCALAREVOLUTION_EXPRESSIONS_H #ifndef LLVM_ANALYSIS_SCALAREVOLUTION_EXPRESSIONS_H
#define LLVM_ANALYSIS_SCALAREVOLUTION_EXPRESSIONS_H #define LLVM_ANALYSIS_SCALAREVOLUTION_EXPRESSIONS_H
#include "llvm/Analysis/ScalarEvolution.h" #include "llvm/Analysis/ScalarEvolution.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/ErrorHandling.h"
namespace llvm { namespace llvm {
class ConstantInt; class ConstantInt;
class ConstantRange; class ConstantRange;
class DominatorTree; class DominatorTree;
enum SCEVTypes { enum SCEVTypes {
// These should be ordered in terms of increasing complexity to make th e // These should be ordered in terms of increasing complexity to make th e
// folders simpler. // folders simpler.
skipping to change at line 48 skipping to change at line 49
ConstantInt *V; ConstantInt *V;
SCEVConstant(const FoldingSetNodeIDRef ID, ConstantInt *v) : SCEVConstant(const FoldingSetNodeIDRef ID, ConstantInt *v) :
SCEV(ID, scConstant), V(v) {} SCEV(ID, scConstant), V(v) {}
public: public:
ConstantInt *getValue() const { return V; } ConstantInt *getValue() const { return V; }
Type *getType() const { return V->getType(); } Type *getType() const { return V->getType(); }
/// Methods for support type inquiry through isa, cast, and dyn_cast: /// Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const SCEVConstant *S) { return true; }
static inline bool classof(const SCEV *S) { static inline bool classof(const SCEV *S) {
return S->getSCEVType() == scConstant; return S->getSCEVType() == scConstant;
} }
}; };
//===-------------------------------------------------------------------- ===// //===-------------------------------------------------------------------- ===//
/// SCEVCastExpr - This is the base class for unary cast operator classes . /// SCEVCastExpr - This is the base class for unary cast operator classes .
/// ///
class SCEVCastExpr : public SCEV { class SCEVCastExpr : public SCEV {
protected: protected:
skipping to change at line 70 skipping to change at line 70
Type *Ty; Type *Ty;
SCEVCastExpr(const FoldingSetNodeIDRef ID, SCEVCastExpr(const FoldingSetNodeIDRef ID,
unsigned SCEVTy, const SCEV *op, Type *ty); unsigned SCEVTy, const SCEV *op, Type *ty);
public: public:
const SCEV *getOperand() const { return Op; } const SCEV *getOperand() const { return Op; }
Type *getType() const { return Ty; } Type *getType() const { return Ty; }
/// Methods for support type inquiry through isa, cast, and dyn_cast: /// Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const SCEVCastExpr *S) { return true; }
static inline bool classof(const SCEV *S) { static inline bool classof(const SCEV *S) {
return S->getSCEVType() == scTruncate || return S->getSCEVType() == scTruncate ||
S->getSCEVType() == scZeroExtend || S->getSCEVType() == scZeroExtend ||
S->getSCEVType() == scSignExtend; S->getSCEVType() == scSignExtend;
} }
}; };
//===-------------------------------------------------------------------- ===// //===-------------------------------------------------------------------- ===//
/// SCEVTruncateExpr - This class represents a truncation of an integer v alue /// SCEVTruncateExpr - This class represents a truncation of an integer v alue
/// to a smaller integer value. /// to a smaller integer value.
/// ///
class SCEVTruncateExpr : public SCEVCastExpr { class SCEVTruncateExpr : public SCEVCastExpr {
friend class ScalarEvolution; friend class ScalarEvolution;
SCEVTruncateExpr(const FoldingSetNodeIDRef ID, SCEVTruncateExpr(const FoldingSetNodeIDRef ID,
const SCEV *op, Type *ty); const SCEV *op, Type *ty);
public: public:
/// Methods for support type inquiry through isa, cast, and dyn_cast: /// Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const SCEVTruncateExpr *S) { return true; }
static inline bool classof(const SCEV *S) { static inline bool classof(const SCEV *S) {
return S->getSCEVType() == scTruncate; return S->getSCEVType() == scTruncate;
} }
}; };
//===-------------------------------------------------------------------- ===// //===-------------------------------------------------------------------- ===//
/// SCEVZeroExtendExpr - This class represents a zero extension of a smal l /// SCEVZeroExtendExpr - This class represents a zero extension of a smal l
/// integer value to a larger integer value. /// integer value to a larger integer value.
/// ///
class SCEVZeroExtendExpr : public SCEVCastExpr { class SCEVZeroExtendExpr : public SCEVCastExpr {
friend class ScalarEvolution; friend class ScalarEvolution;
SCEVZeroExtendExpr(const FoldingSetNodeIDRef ID, SCEVZeroExtendExpr(const FoldingSetNodeIDRef ID,
const SCEV *op, Type *ty); const SCEV *op, Type *ty);
public: public:
/// Methods for support type inquiry through isa, cast, and dyn_cast: /// Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const SCEVZeroExtendExpr *S) { return true; }
static inline bool classof(const SCEV *S) { static inline bool classof(const SCEV *S) {
return S->getSCEVType() == scZeroExtend; return S->getSCEVType() == scZeroExtend;
} }
}; };
//===-------------------------------------------------------------------- ===// //===-------------------------------------------------------------------- ===//
/// SCEVSignExtendExpr - This class represents a sign extension of a smal l /// SCEVSignExtendExpr - This class represents a sign extension of a smal l
/// integer value to a larger integer value. /// integer value to a larger integer value.
/// ///
class SCEVSignExtendExpr : public SCEVCastExpr { class SCEVSignExtendExpr : public SCEVCastExpr {
friend class ScalarEvolution; friend class ScalarEvolution;
SCEVSignExtendExpr(const FoldingSetNodeIDRef ID, SCEVSignExtendExpr(const FoldingSetNodeIDRef ID,
const SCEV *op, Type *ty); const SCEV *op, Type *ty);
public: public:
/// Methods for support type inquiry through isa, cast, and dyn_cast: /// Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const SCEVSignExtendExpr *S) { return true; }
static inline bool classof(const SCEV *S) { static inline bool classof(const SCEV *S) {
return S->getSCEVType() == scSignExtend; return S->getSCEVType() == scSignExtend;
} }
}; };
//===-------------------------------------------------------------------- ===// //===-------------------------------------------------------------------- ===//
/// SCEVNAryExpr - This node is a base class providing common /// SCEVNAryExpr - This node is a base class providing common
/// functionality for n'ary operators. /// functionality for n'ary operators.
/// ///
class SCEVNAryExpr : public SCEV { class SCEVNAryExpr : public SCEV {
skipping to change at line 167 skipping to change at line 163
op_iterator op_begin() const { return Operands; } op_iterator op_begin() const { return Operands; }
op_iterator op_end() const { return Operands + NumOperands; } op_iterator op_end() const { return Operands + NumOperands; }
Type *getType() const { return getOperand(0)->getType(); } Type *getType() const { return getOperand(0)->getType(); }
NoWrapFlags getNoWrapFlags(NoWrapFlags Mask = NoWrapMask) const { NoWrapFlags getNoWrapFlags(NoWrapFlags Mask = NoWrapMask) const {
return (NoWrapFlags)(SubclassData & Mask); return (NoWrapFlags)(SubclassData & Mask);
} }
/// Methods for support type inquiry through isa, cast, and dyn_cast: /// Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const SCEVNAryExpr *S) { return true; }
static inline bool classof(const SCEV *S) { static inline bool classof(const SCEV *S) {
return S->getSCEVType() == scAddExpr || return S->getSCEVType() == scAddExpr ||
S->getSCEVType() == scMulExpr || S->getSCEVType() == scMulExpr ||
S->getSCEVType() == scSMaxExpr || S->getSCEVType() == scSMaxExpr ||
S->getSCEVType() == scUMaxExpr || S->getSCEVType() == scUMaxExpr ||
S->getSCEVType() == scAddRecExpr; S->getSCEVType() == scAddRecExpr;
} }
}; };
//===-------------------------------------------------------------------- ===// //===-------------------------------------------------------------------- ===//
skipping to change at line 189 skipping to change at line 184
/// operators. /// operators.
/// ///
class SCEVCommutativeExpr : public SCEVNAryExpr { class SCEVCommutativeExpr : public SCEVNAryExpr {
protected: protected:
SCEVCommutativeExpr(const FoldingSetNodeIDRef ID, SCEVCommutativeExpr(const FoldingSetNodeIDRef ID,
enum SCEVTypes T, const SCEV *const *O, size_t N) enum SCEVTypes T, const SCEV *const *O, size_t N)
: SCEVNAryExpr(ID, T, O, N) {} : SCEVNAryExpr(ID, T, O, N) {}
public: public:
/// Methods for support type inquiry through isa, cast, and dyn_cast: /// Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const SCEVCommutativeExpr *S) { return true; }
static inline bool classof(const SCEV *S) { static inline bool classof(const SCEV *S) {
return S->getSCEVType() == scAddExpr || return S->getSCEVType() == scAddExpr ||
S->getSCEVType() == scMulExpr || S->getSCEVType() == scMulExpr ||
S->getSCEVType() == scSMaxExpr || S->getSCEVType() == scSMaxExpr ||
S->getSCEVType() == scUMaxExpr; S->getSCEVType() == scUMaxExpr;
} }
/// Set flags for a non-recurrence without clearing previously set flag s. /// Set flags for a non-recurrence without clearing previously set flag s.
void setNoWrapFlags(NoWrapFlags Flags) { void setNoWrapFlags(NoWrapFlags Flags) {
SubclassData |= Flags; SubclassData |= Flags;
skipping to change at line 223 skipping to change at line 217
public: public:
Type *getType() const { Type *getType() const {
// Use the type of the last operand, which is likely to be a pointer // Use the type of the last operand, which is likely to be a pointer
// type, if there is one. This doesn't usually matter, but it can hel p // type, if there is one. This doesn't usually matter, but it can hel p
// reduce casts when the expressions are expanded. // reduce casts when the expressions are expanded.
return getOperand(getNumOperands() - 1)->getType(); return getOperand(getNumOperands() - 1)->getType();
} }
/// Methods for support type inquiry through isa, cast, and dyn_cast: /// Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const SCEVAddExpr *S) { return true; }
static inline bool classof(const SCEV *S) { static inline bool classof(const SCEV *S) {
return S->getSCEVType() == scAddExpr; return S->getSCEVType() == scAddExpr;
} }
}; };
//===-------------------------------------------------------------------- ===// //===-------------------------------------------------------------------- ===//
/// SCEVMulExpr - This node represents multiplication of some number of S CEVs. /// SCEVMulExpr - This node represents multiplication of some number of S CEVs.
/// ///
class SCEVMulExpr : public SCEVCommutativeExpr { class SCEVMulExpr : public SCEVCommutativeExpr {
friend class ScalarEvolution; friend class ScalarEvolution;
SCEVMulExpr(const FoldingSetNodeIDRef ID, SCEVMulExpr(const FoldingSetNodeIDRef ID,
const SCEV *const *O, size_t N) const SCEV *const *O, size_t N)
: SCEVCommutativeExpr(ID, scMulExpr, O, N) { : SCEVCommutativeExpr(ID, scMulExpr, O, N) {
} }
public: public:
/// Methods for support type inquiry through isa, cast, and dyn_cast: /// Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const SCEVMulExpr *S) { return true; }
static inline bool classof(const SCEV *S) { static inline bool classof(const SCEV *S) {
return S->getSCEVType() == scMulExpr; return S->getSCEVType() == scMulExpr;
} }
}; };
//===-------------------------------------------------------------------- ===// //===-------------------------------------------------------------------- ===//
/// SCEVUDivExpr - This class represents a binary unsigned division opera tion. /// SCEVUDivExpr - This class represents a binary unsigned division opera tion.
/// ///
class SCEVUDivExpr : public SCEV { class SCEVUDivExpr : public SCEV {
friend class ScalarEvolution; friend class ScalarEvolution;
skipping to change at line 273 skipping to change at line 265
Type *getType() const { Type *getType() const {
// In most cases the types of LHS and RHS will be the same, but in so me // In most cases the types of LHS and RHS will be the same, but in so me
// crazy cases one or the other may be a pointer. ScalarEvolution doe sn't // crazy cases one or the other may be a pointer. ScalarEvolution doe sn't
// depend on the type for correctness, but handling types carefully c an // depend on the type for correctness, but handling types carefully c an
// avoid extra casts in the SCEVExpander. The LHS is more likely to b e // avoid extra casts in the SCEVExpander. The LHS is more likely to b e
// a pointer type than the RHS, so use the RHS' type here. // a pointer type than the RHS, so use the RHS' type here.
return getRHS()->getType(); return getRHS()->getType();
} }
/// Methods for support type inquiry through isa, cast, and dyn_cast: /// Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const SCEVUDivExpr *S) { return true; }
static inline bool classof(const SCEV *S) { static inline bool classof(const SCEV *S) {
return S->getSCEVType() == scUDivExpr; return S->getSCEVType() == scUDivExpr;
} }
}; };
//===-------------------------------------------------------------------- ===// //===-------------------------------------------------------------------- ===//
/// SCEVAddRecExpr - This node represents a polynomial recurrence on the trip /// SCEVAddRecExpr - This node represents a polynomial recurrence on the trip
/// count of the specified loop. This is the primary focus of the /// count of the specified loop. This is the primary focus of the
/// ScalarEvolution framework; all the other SCEV subclasses are mostly j ust /// ScalarEvolution framework; all the other SCEV subclasses are mostly j ust
/// supporting infrastructure to allow SCEVAddRecExpr expressions to be /// supporting infrastructure to allow SCEVAddRecExpr expressions to be
skipping to change at line 356 skipping to change at line 347
const SCEV *getNumIterationsInRange(ConstantRange Range, const SCEV *getNumIterationsInRange(ConstantRange Range,
ScalarEvolution &SE) const; ScalarEvolution &SE) const;
/// getPostIncExpr - Return an expression representing the value of /// getPostIncExpr - Return an expression representing the value of
/// this expression one iteration of the loop ahead. /// this expression one iteration of the loop ahead.
const SCEVAddRecExpr *getPostIncExpr(ScalarEvolution &SE) const { const SCEVAddRecExpr *getPostIncExpr(ScalarEvolution &SE) const {
return cast<SCEVAddRecExpr>(SE.getAddExpr(this, getStepRecurrence(SE) )); return cast<SCEVAddRecExpr>(SE.getAddExpr(this, getStepRecurrence(SE) ));
} }
/// Methods for support type inquiry through isa, cast, and dyn_cast: /// Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const SCEVAddRecExpr *S) { return true; }
static inline bool classof(const SCEV *S) { static inline bool classof(const SCEV *S) {
return S->getSCEVType() == scAddRecExpr; return S->getSCEVType() == scAddRecExpr;
} }
}; };
//===-------------------------------------------------------------------- ===// //===-------------------------------------------------------------------- ===//
/// SCEVSMaxExpr - This class represents a signed maximum selection. /// SCEVSMaxExpr - This class represents a signed maximum selection.
/// ///
class SCEVSMaxExpr : public SCEVCommutativeExpr { class SCEVSMaxExpr : public SCEVCommutativeExpr {
friend class ScalarEvolution; friend class ScalarEvolution;
SCEVSMaxExpr(const FoldingSetNodeIDRef ID, SCEVSMaxExpr(const FoldingSetNodeIDRef ID,
const SCEV *const *O, size_t N) const SCEV *const *O, size_t N)
: SCEVCommutativeExpr(ID, scSMaxExpr, O, N) { : SCEVCommutativeExpr(ID, scSMaxExpr, O, N) {
// Max never overflows. // Max never overflows.
setNoWrapFlags((NoWrapFlags)(FlagNUW | FlagNSW)); setNoWrapFlags((NoWrapFlags)(FlagNUW | FlagNSW));
} }
public: public:
/// Methods for support type inquiry through isa, cast, and dyn_cast: /// Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const SCEVSMaxExpr *S) { return true; }
static inline bool classof(const SCEV *S) { static inline bool classof(const SCEV *S) {
return S->getSCEVType() == scSMaxExpr; return S->getSCEVType() == scSMaxExpr;
} }
}; };
//===-------------------------------------------------------------------- ===// //===-------------------------------------------------------------------- ===//
/// SCEVUMaxExpr - This class represents an unsigned maximum selection. /// SCEVUMaxExpr - This class represents an unsigned maximum selection.
/// ///
class SCEVUMaxExpr : public SCEVCommutativeExpr { class SCEVUMaxExpr : public SCEVCommutativeExpr {
friend class ScalarEvolution; friend class ScalarEvolution;
SCEVUMaxExpr(const FoldingSetNodeIDRef ID, SCEVUMaxExpr(const FoldingSetNodeIDRef ID,
const SCEV *const *O, size_t N) const SCEV *const *O, size_t N)
: SCEVCommutativeExpr(ID, scUMaxExpr, O, N) { : SCEVCommutativeExpr(ID, scUMaxExpr, O, N) {
// Max never overflows. // Max never overflows.
setNoWrapFlags((NoWrapFlags)(FlagNUW | FlagNSW)); setNoWrapFlags((NoWrapFlags)(FlagNUW | FlagNSW));
} }
public: public:
/// Methods for support type inquiry through isa, cast, and dyn_cast: /// Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const SCEVUMaxExpr *S) { return true; }
static inline bool classof(const SCEV *S) { static inline bool classof(const SCEV *S) {
return S->getSCEVType() == scUMaxExpr; return S->getSCEVType() == scUMaxExpr;
} }
}; };
//===-------------------------------------------------------------------- ===// //===-------------------------------------------------------------------- ===//
/// SCEVUnknown - This means that we are dealing with an entirely unknown SCEV /// SCEVUnknown - This means that we are dealing with an entirely unknown SCEV
/// value, and only represent it as its LLVM Value. This is the "bottom" /// value, and only represent it as its LLVM Value. This is the "bottom"
/// value for the analysis. /// value for the analysis.
/// ///
skipping to change at line 445 skipping to change at line 433
/// folded with other operations into something unrecognizable. This /// folded with other operations into something unrecognizable. This
/// is mainly only useful for pretty-printing and other situations /// is mainly only useful for pretty-printing and other situations
/// where it isn't absolutely required for these to succeed. /// where it isn't absolutely required for these to succeed.
bool isSizeOf(Type *&AllocTy) const; bool isSizeOf(Type *&AllocTy) const;
bool isAlignOf(Type *&AllocTy) const; bool isAlignOf(Type *&AllocTy) const;
bool isOffsetOf(Type *&STy, Constant *&FieldNo) const; bool isOffsetOf(Type *&STy, Constant *&FieldNo) const;
Type *getType() const { return getValPtr()->getType(); } Type *getType() const { return getValPtr()->getType(); }
/// Methods for support type inquiry through isa, cast, and dyn_cast: /// Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const SCEVUnknown *S) { return true; }
static inline bool classof(const SCEV *S) { static inline bool classof(const SCEV *S) {
return S->getSCEVType() == scUnknown; return S->getSCEVType() == scUnknown;
} }
}; };
/// SCEVVisitor - This class defines a simple visitor class that may be u sed /// SCEVVisitor - This class defines a simple visitor class that may be u sed
/// for various SCEV analysis purposes. /// for various SCEV analysis purposes.
template<typename SC, typename RetVal=void> template<typename SC, typename RetVal=void>
struct SCEVVisitor { struct SCEVVisitor {
RetVal visit(const SCEV *S) { RetVal visit(const SCEV *S) {
skipping to change at line 490 skipping to change at line 477
return ((SC*)this)->visitCouldNotCompute((const SCEVCouldNotCompute *)S); return ((SC*)this)->visitCouldNotCompute((const SCEVCouldNotCompute *)S);
default: default:
llvm_unreachable("Unknown SCEV type!"); llvm_unreachable("Unknown SCEV type!");
} }
} }
RetVal visitCouldNotCompute(const SCEVCouldNotCompute *S) { RetVal visitCouldNotCompute(const SCEVCouldNotCompute *S) {
llvm_unreachable("Invalid use of SCEVCouldNotCompute!"); llvm_unreachable("Invalid use of SCEVCouldNotCompute!");
} }
}; };
/// Visit all nodes in the expression tree using worklist traversal.
///
/// Visitor implements:
/// // return true to follow this node.
/// bool follow(const SCEV *S);
/// // return true to terminate the search.
/// bool isDone();
template<typename SV>
class SCEVTraversal {
SV &Visitor;
SmallVector<const SCEV *, 8> Worklist;
SmallPtrSet<const SCEV *, 8> Visited;
void push(const SCEV *S) {
if (Visited.insert(S) && Visitor.follow(S))
Worklist.push_back(S);
}
public:
SCEVTraversal(SV& V): Visitor(V) {}
void visitAll(const SCEV *Root) {
push(Root);
while (!Worklist.empty() && !Visitor.isDone()) {
const SCEV *S = Worklist.pop_back_val();
switch (S->getSCEVType()) {
case scConstant:
case scUnknown:
break;
case scTruncate:
case scZeroExtend:
case scSignExtend:
push(cast<SCEVCastExpr>(S)->getOperand());
break;
case scAddExpr:
case scMulExpr:
case scSMaxExpr:
case scUMaxExpr:
case scAddRecExpr: {
const SCEVNAryExpr *NAry = cast<SCEVNAryExpr>(S);
for (SCEVNAryExpr::op_iterator I = NAry->op_begin(),
E = NAry->op_end(); I != E; ++I) {
push(*I);
}
break;
}
case scUDivExpr: {
const SCEVUDivExpr *UDiv = cast<SCEVUDivExpr>(S);
push(UDiv->getLHS());
push(UDiv->getRHS());
break;
}
case scCouldNotCompute:
llvm_unreachable("Attempt to use a SCEVCouldNotCompute object!");
default:
llvm_unreachable("Unknown SCEV kind!");
}
}
}
};
/// Use SCEVTraversal to visit all nodes in the givien expression tree.
template<typename SV>
void visitAll(const SCEV *Root, SV& Visitor) {
SCEVTraversal<SV> T(Visitor);
T.visitAll(Root);
}
} }
#endif #endif
 End of changes. 16 change blocks. 
14 lines changed or deleted 69 lines changed or added


 ScheduleDAG.h   ScheduleDAG.h 
skipping to change at line 34 skipping to change at line 34
#include "llvm/ADT/SmallVector.h" #include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/PointerIntPair.h" #include "llvm/ADT/PointerIntPair.h"
namespace llvm { namespace llvm {
class AliasAnalysis; class AliasAnalysis;
class SUnit; class SUnit;
class MachineConstantPool; class MachineConstantPool;
class MachineFunction; class MachineFunction;
class MachineRegisterInfo; class MachineRegisterInfo;
class MachineInstr; class MachineInstr;
struct MCSchedClassDesc;
class TargetRegisterInfo; class TargetRegisterInfo;
class ScheduleDAG; class ScheduleDAG;
class SDNode; class SDNode;
class TargetInstrInfo; class TargetInstrInfo;
class MCInstrDesc; class MCInstrDesc;
class TargetMachine; class TargetMachine;
class TargetRegisterClass; class TargetRegisterClass;
template<class Graph> class GraphWriter; template<class Graph> class GraphWriter;
/// SDep - Scheduling dependency. This represents one direction of an /// SDep - Scheduling dependency. This represents one direction of an
skipping to change at line 55 skipping to change at line 56
class SDep { class SDep {
public: public:
/// Kind - These are the different kinds of scheduling dependencies. /// Kind - These are the different kinds of scheduling dependencies.
enum Kind { enum Kind {
Data, ///< Regular data dependence (aka true-dependence). Data, ///< Regular data dependence (aka true-dependence).
Anti, ///< A register anti-dependedence (aka WAR). Anti, ///< A register anti-dependedence (aka WAR).
Output, ///< A register output-dependence (aka WAW). Output, ///< A register output-dependence (aka WAW).
Order ///< Any other ordering dependency. Order ///< Any other ordering dependency.
}; };
enum OrderKind {
Barrier, ///< An unknown scheduling barrier.
MayAliasMem, ///< Nonvolatile load/Store instructions that may alias
.
MustAliasMem, ///< Nonvolatile load/Store instructions that must alia
s.
Artificial ///< Arbitrary weak DAG edge (no actual dependence).
};
private: private:
/// Dep - A pointer to the depending/depended-on SUnit, and an enum /// Dep - A pointer to the depending/depended-on SUnit, and an enum
/// indicating the kind of the dependency. /// indicating the kind of the dependency.
PointerIntPair<SUnit *, 2, Kind> Dep; PointerIntPair<SUnit *, 2, Kind> Dep;
/// Contents - A union discriminated by the dependence kind. /// Contents - A union discriminated by the dependence kind.
union { union {
/// Reg - For Data, Anti, and Output dependencies, the associated /// Reg - For Data, Anti, and Output dependencies, the associated
/// register. For Data dependencies that don't currently have a regis ter /// register. For Data dependencies that don't currently have a regis ter
/// assigned, this is set to zero. /// assigned, this is set to zero.
unsigned Reg; unsigned Reg;
/// Order - Additional information about Order dependencies. /// Order - Additional information about Order dependencies.
struct { unsigned OrdKind; // enum OrderKind
/// isNormalMemory - True if both sides of the dependence
/// access memory in non-volatile and fully modeled ways.
bool isNormalMemory : 1;
/// isMustAlias - True if both sides of the dependence are known to
/// access the same memory.
bool isMustAlias : 1;
/// isArtificial - True if this is an artificial dependency, meanin
g
/// it is not necessary for program correctness, and may be safely
/// deleted if necessary.
bool isArtificial : 1;
} Order;
} Contents; } Contents;
/// Latency - The time associated with this edge. Often this is just /// Latency - The time associated with this edge. Often this is just
/// the value of the Latency field of the predecessor, however advanced /// the value of the Latency field of the predecessor, however advanced
/// models may provide additional information about specific edges. /// models may provide additional information about specific edges.
unsigned Latency; unsigned Latency;
/// Record MinLatency seperately from "expected" Latency.
///
/// FIXME: this field is not packed on LP64. Convert to 16-bit DAG edge
/// latency after introducing saturating truncation.
unsigned MinLatency;
public: public:
/// SDep - Construct a null SDep. This is only for use by container /// SDep - Construct a null SDep. This is only for use by container
/// classes which require default constructors. SUnits may not /// classes which require default constructors. SUnits may not
/// have null SDep edges. /// have null SDep edges.
SDep() : Dep(0, Data) {} SDep() : Dep(0, Data) {}
/// SDep - Construct an SDep with the specified values. /// SDep - Construct an SDep with the specified values.
SDep(SUnit *S, Kind kind, unsigned latency = 1, unsigned Reg = 0, SDep(SUnit *S, Kind kind, unsigned Reg)
bool isNormalMemory = false, bool isMustAlias = false, : Dep(S, kind), Contents() {
bool isArtificial = false)
: Dep(S, kind), Contents(), Latency(latency) {
switch (kind) { switch (kind) {
default:
llvm_unreachable("Reg given for non-register dependence!");
case Anti: case Anti:
case Output: case Output:
assert(Reg != 0 && assert(Reg != 0 &&
"SDep::Anti and SDep::Output must use a non-zero Reg!"); "SDep::Anti and SDep::Output must use a non-zero Reg!");
// fall through
case Data:
assert(!isMustAlias && "isMustAlias only applies with SDep::Order!"
);
assert(!isArtificial && "isArtificial only applies with SDep::Order
!");
Contents.Reg = Reg; Contents.Reg = Reg;
Latency = 0;
break; break;
case Order: case Data:
assert(Reg == 0 && "Reg given for non-register dependence!"); Contents.Reg = Reg;
Contents.Order.isNormalMemory = isNormalMemory; Latency = 1;
Contents.Order.isMustAlias = isMustAlias;
Contents.Order.isArtificial = isArtificial;
break; break;
} }
MinLatency = Latency;
}
SDep(SUnit *S, OrderKind kind)
: Dep(S, Order), Contents(), Latency(0), MinLatency(0) {
Contents.OrdKind = kind;
} }
bool operator==(const SDep &Other) const { /// Return true if the specified SDep is equivalent except for latency.
if (Dep != Other.Dep || Latency != Other.Latency) return false; bool overlaps(const SDep &Other) const {
if (Dep != Other.Dep) return false;
switch (Dep.getInt()) { switch (Dep.getInt()) {
case Data: case Data:
case Anti: case Anti:
case Output: case Output:
return Contents.Reg == Other.Contents.Reg; return Contents.Reg == Other.Contents.Reg;
case Order: case Order:
return Contents.Order.isNormalMemory == return Contents.OrdKind == Other.Contents.OrdKind;
Other.Contents.Order.isNormalMemory &&
Contents.Order.isMustAlias == Other.Contents.Order.isMustAli
as &&
Contents.Order.isArtificial == Other.Contents.Order.isArtifi
cial;
} }
llvm_unreachable("Invalid dependency kind!"); llvm_unreachable("Invalid dependency kind!");
} }
bool operator==(const SDep &Other) const {
return overlaps(Other)
&& Latency == Other.Latency && MinLatency == Other.MinLatency;
}
bool operator!=(const SDep &Other) const { bool operator!=(const SDep &Other) const {
return !operator==(Other); return !operator==(Other);
} }
/// getLatency - Return the latency value for this edge, which roughly /// getLatency - Return the latency value for this edge, which roughly
/// means the minimum number of cycles that must elapse between the /// means the minimum number of cycles that must elapse between the
/// predecessor and the successor, given that they have this edge /// predecessor and the successor, given that they have this edge
/// between them. /// between them.
unsigned getLatency() const { unsigned getLatency() const {
return Latency; return Latency;
} }
/// setLatency - Set the latency for this edge. /// setLatency - Set the latency for this edge.
void setLatency(unsigned Lat) { void setLatency(unsigned Lat) {
Latency = Lat; Latency = Lat;
} }
/// getMinLatency - Return the minimum latency for this edge. Minimum
/// latency is used for scheduling groups, while normal (expected) late
ncy
/// is for instruction cost and critical path.
unsigned getMinLatency() const {
return MinLatency;
}
/// setMinLatency - Set the minimum latency for this edge.
void setMinLatency(unsigned Lat) {
MinLatency = Lat;
}
//// getSUnit - Return the SUnit to which this edge points. //// getSUnit - Return the SUnit to which this edge points.
SUnit *getSUnit() const { SUnit *getSUnit() const {
return Dep.getPointer(); return Dep.getPointer();
} }
//// setSUnit - Assign the SUnit to which this edge points. //// setSUnit - Assign the SUnit to which this edge points.
void setSUnit(SUnit *SU) { void setSUnit(SUnit *SU) {
Dep.setPointer(SU); Dep.setPointer(SU);
} }
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/// isCtrl - Shorthand for getKind() != SDep::Data. /// isCtrl - Shorthand for getKind() != SDep::Data.
bool isCtrl() const { bool isCtrl() const {
return getKind() != Data; return getKind() != Data;
} }
/// isNormalMemory - Test if this is an Order dependence between two /// isNormalMemory - Test if this is an Order dependence between two
/// memory accesses where both sides of the dependence access memory /// memory accesses where both sides of the dependence access memory
/// in non-volatile and fully modeled ways. /// in non-volatile and fully modeled ways.
bool isNormalMemory() const { bool isNormalMemory() const {
return getKind() == Order && Contents.Order.isNormalMemory; return getKind() == Order && (Contents.OrdKind == MayAliasMem
|| Contents.OrdKind == MustAliasMem);
} }
/// isMustAlias - Test if this is an Order dependence that is marked /// isMustAlias - Test if this is an Order dependence that is marked
/// as "must alias", meaning that the SUnits at either end of the edge /// as "must alias", meaning that the SUnits at either end of the edge
/// have a memory dependence on a known memory location. /// have a memory dependence on a known memory location.
bool isMustAlias() const { bool isMustAlias() const {
return getKind() == Order && Contents.Order.isMustAlias; return getKind() == Order && Contents.OrdKind == MustAliasMem;
} }
/// isArtificial - Test if this is an Order dependence that is marked /// isArtificial - Test if this is an Order dependence that is marked
/// as "artificial", meaning it isn't necessary for correctness. /// as "artificial", meaning it isn't necessary for correctness.
bool isArtificial() const { bool isArtificial() const {
return getKind() == Order && Contents.Order.isArtificial; return getKind() == Order && Contents.OrdKind == Artificial;
} }
/// isAssignedRegDep - Test if this is a Data dependence that is /// isAssignedRegDep - Test if this is a Data dependence that is
/// associated with a register. /// associated with a register.
bool isAssignedRegDep() const { bool isAssignedRegDep() const {
return getKind() == Data && Contents.Reg != 0; return getKind() == Data && Contents.Reg != 0;
} }
/// getReg - Return the register associated with this edge. This is /// getReg - Return the register associated with this edge. This is
/// only valid on Data, Anti, and Output edges. On Data edges, this /// only valid on Data, Anti, and Output edges. On Data edges, this
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/// SUnit - Scheduling unit. This is a node in the scheduling DAG. /// SUnit - Scheduling unit. This is a node in the scheduling DAG.
class SUnit { class SUnit {
private: private:
SDNode *Node; // Representative node. SDNode *Node; // Representative node.
MachineInstr *Instr; // Alternatively, a MachineInstr. MachineInstr *Instr; // Alternatively, a MachineInstr.
public: public:
SUnit *OrigNode; // If not this, the node from which SUnit *OrigNode; // If not this, the node from which
// this node was cloned. // this node was cloned.
// (SD scheduling only) // (SD scheduling only)
const MCSchedClassDesc *SchedClass; // NULL or resolved SchedClass.
// Preds/Succs - The SUnits before/after us in the graph. // Preds/Succs - The SUnits before/after us in the graph.
SmallVector<SDep, 4> Preds; // All sunit predecessors. SmallVector<SDep, 4> Preds; // All sunit predecessors.
SmallVector<SDep, 4> Succs; // All sunit successors. SmallVector<SDep, 4> Succs; // All sunit successors.
typedef SmallVector<SDep, 4>::iterator pred_iterator; typedef SmallVector<SDep, 4>::iterator pred_iterator;
typedef SmallVector<SDep, 4>::iterator succ_iterator; typedef SmallVector<SDep, 4>::iterator succ_iterator;
typedef SmallVector<SDep, 4>::const_iterator const_pred_iterator; typedef SmallVector<SDep, 4>::const_iterator const_pred_iterator;
typedef SmallVector<SDep, 4>::const_iterator const_succ_iterator; typedef SmallVector<SDep, 4>::const_iterator const_succ_iterator;
unsigned NodeNum; // Entry # of node in the node vect or. unsigned NodeNum; // Entry # of node in the node vect or.
skipping to change at line 275 skipping to change at line 293
bool isScheduleLow : 1; // True if preferable to schedule l ow. bool isScheduleLow : 1; // True if preferable to schedule l ow.
bool isCloned : 1; // True if this node has been clone d. bool isCloned : 1; // True if this node has been clone d.
Sched::Preference SchedulingPref; // Scheduling preference. Sched::Preference SchedulingPref; // Scheduling preference.
private: private:
bool isDepthCurrent : 1; // True if Depth is current. bool isDepthCurrent : 1; // True if Depth is current.
bool isHeightCurrent : 1; // True if Height is current. bool isHeightCurrent : 1; // True if Height is current.
unsigned Depth; // Node depth. unsigned Depth; // Node depth.
unsigned Height; // Node height. unsigned Height; // Node height.
public: public:
unsigned TopReadyCycle; // Cycle relative to start when node is ready.
unsigned BotReadyCycle; // Cycle relative to end when node is ready.
const TargetRegisterClass *CopyDstRC; // Is a special copy node if not null. const TargetRegisterClass *CopyDstRC; // Is a special copy node if not null.
const TargetRegisterClass *CopySrcRC; const TargetRegisterClass *CopySrcRC;
/// SUnit - Construct an SUnit for pre-regalloc scheduling to represent /// SUnit - Construct an SUnit for pre-regalloc scheduling to represent
/// an SDNode and any nodes flagged to it. /// an SDNode and any nodes flagged to it.
SUnit(SDNode *node, unsigned nodenum) SUnit(SDNode *node, unsigned nodenum)
: Node(node), Instr(0), OrigNode(0), NodeNum(nodenum), : Node(node), Instr(0), OrigNode(0), SchedClass(0), NodeNum(nodenum),
NodeQueueId(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0), NodeQueueId(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0),
NumSuccsLeft(0), NumRegDefsLeft(0), Latency(0), NumSuccsLeft(0), NumRegDefsLeft(0), Latency(0),
isVRegCycle(false), isCall(false), isCallOp(false), isTwoAddress(fa lse), isVRegCycle(false), isCall(false), isCallOp(false), isTwoAddress(fa lse),
isCommutable(false), hasPhysRegDefs(false), hasPhysRegClobbers(fals e), isCommutable(false), hasPhysRegDefs(false), hasPhysRegClobbers(fals e),
isPending(false), isAvailable(false), isScheduled(false), isPending(false), isAvailable(false), isScheduled(false),
isScheduleHigh(false), isScheduleLow(false), isCloned(false), isScheduleHigh(false), isScheduleLow(false), isCloned(false),
SchedulingPref(Sched::None), SchedulingPref(Sched::None),
isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0), isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0),
CopyDstRC(NULL), CopySrcRC(NULL) {} TopReadyCycle(0), BotReadyCycle(0), CopyDstRC(NULL), CopySrcRC(NULL ) {}
/// SUnit - Construct an SUnit for post-regalloc scheduling to represen t /// SUnit - Construct an SUnit for post-regalloc scheduling to represen t
/// a MachineInstr. /// a MachineInstr.
SUnit(MachineInstr *instr, unsigned nodenum) SUnit(MachineInstr *instr, unsigned nodenum)
: Node(0), Instr(instr), OrigNode(0), NodeNum(nodenum), : Node(0), Instr(instr), OrigNode(0), SchedClass(0), NodeNum(nodenum) ,
NodeQueueId(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0), NodeQueueId(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0),
NumSuccsLeft(0), NumRegDefsLeft(0), Latency(0), NumSuccsLeft(0), NumRegDefsLeft(0), Latency(0),
isVRegCycle(false), isCall(false), isCallOp(false), isTwoAddress(fa lse), isVRegCycle(false), isCall(false), isCallOp(false), isTwoAddress(fa lse),
isCommutable(false), hasPhysRegDefs(false), hasPhysRegClobbers(fals e), isCommutable(false), hasPhysRegDefs(false), hasPhysRegClobbers(fals e),
isPending(false), isAvailable(false), isScheduled(false), isPending(false), isAvailable(false), isScheduled(false),
isScheduleHigh(false), isScheduleLow(false), isCloned(false), isScheduleHigh(false), isScheduleLow(false), isCloned(false),
SchedulingPref(Sched::None), SchedulingPref(Sched::None),
isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0), isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0),
CopyDstRC(NULL), CopySrcRC(NULL) {} TopReadyCycle(0), BotReadyCycle(0), CopyDstRC(NULL), CopySrcRC(NULL ) {}
/// SUnit - Construct a placeholder SUnit. /// SUnit - Construct a placeholder SUnit.
SUnit() SUnit()
: Node(0), Instr(0), OrigNode(0), NodeNum(~0u), : Node(0), Instr(0), OrigNode(0), SchedClass(0), NodeNum(~0u),
NodeQueueId(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0), NodeQueueId(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0),
NumSuccsLeft(0), NumRegDefsLeft(0), Latency(0), NumSuccsLeft(0), NumRegDefsLeft(0), Latency(0),
isVRegCycle(false), isCall(false), isCallOp(false), isTwoAddress(fa lse), isVRegCycle(false), isCall(false), isCallOp(false), isTwoAddress(fa lse),
isCommutable(false), hasPhysRegDefs(false), hasPhysRegClobbers(fals e), isCommutable(false), hasPhysRegDefs(false), hasPhysRegClobbers(fals e),
isPending(false), isAvailable(false), isScheduled(false), isPending(false), isAvailable(false), isScheduled(false),
isScheduleHigh(false), isScheduleLow(false), isCloned(false), isScheduleHigh(false), isScheduleLow(false), isCloned(false),
SchedulingPref(Sched::None), SchedulingPref(Sched::None),
isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0), isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0),
CopyDstRC(NULL), CopySrcRC(NULL) {} TopReadyCycle(0), BotReadyCycle(0), CopyDstRC(NULL), CopySrcRC(NULL ) {}
/// setNode - Assign the representative SDNode for this SUnit. /// setNode - Assign the representative SDNode for this SUnit.
/// This may be used during pre-regalloc scheduling. /// This may be used during pre-regalloc scheduling.
void setNode(SDNode *N) { void setNode(SDNode *N) {
assert(!Instr && "Setting SDNode of SUnit with MachineInstr!"); assert(!Instr && "Setting SDNode of SUnit with MachineInstr!");
Node = N; Node = N;
} }
/// getNode - Return the representative SDNode for this SUnit. /// getNode - Return the representative SDNode for this SUnit.
/// This may be used during pre-regalloc scheduling. /// This may be used during pre-regalloc scheduling.
skipping to change at line 550 skipping to change at line 571
/// addCustomGraphFeatures - Add custom features for a visualization of /// addCustomGraphFeatures - Add custom features for a visualization of
/// the ScheduleDAG. /// the ScheduleDAG.
virtual void addCustomGraphFeatures(GraphWriter<ScheduleDAG*> &) const {} virtual void addCustomGraphFeatures(GraphWriter<ScheduleDAG*> &) const {}
#ifndef NDEBUG #ifndef NDEBUG
/// VerifyScheduledDAG - Verify that all SUnits were scheduled and that /// VerifyScheduledDAG - Verify that all SUnits were scheduled and that
/// their state is consistent. Return the number of scheduled SUnits. /// their state is consistent. Return the number of scheduled SUnits.
unsigned VerifyScheduledDAG(bool isBottomUp); unsigned VerifyScheduledDAG(bool isBottomUp);
#endif #endif
protected:
/// ComputeLatency - Compute node latency.
///
virtual void computeLatency(SUnit *SU) = 0;
/// ComputeOperandLatency - Override dependence edge latency using
/// operand use/def information
///
virtual void computeOperandLatency(SUnit *, SUnit *,
SDep&) const { }
/// ForceUnitLatencies - Return true if all scheduling edges should be
given
/// a latency value of one. The default is to return false; schedulers
may
/// override this as needed.
virtual bool forceUnitLatencies() const { return false; }
private: private:
// Return the MCInstrDesc of this SDNode or NULL. // Return the MCInstrDesc of this SDNode or NULL.
const MCInstrDesc *getNodeDesc(const SDNode *Node) const; const MCInstrDesc *getNodeDesc(const SDNode *Node) const;
}; };
class SUnitIterator : public std::iterator<std::forward_iterator_tag, class SUnitIterator : public std::iterator<std::forward_iterator_tag,
SUnit, ptrdiff_t> { SUnit, ptrdiff_t> {
SUnit *Node; SUnit *Node;
unsigned Operand; unsigned Operand;
 End of changes. 26 change blocks. 
65 lines changed or deleted 66 lines changed or added


 ScheduleDAGInstrs.h   ScheduleDAGInstrs.h 
skipping to change at line 21 skipping to change at line 21
// scheduling for a MachineInstr-based dependency graph. // scheduling for a MachineInstr-based dependency graph.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef SCHEDULEDAGINSTRS_H #ifndef SCHEDULEDAGINSTRS_H
#define SCHEDULEDAGINSTRS_H #define SCHEDULEDAGINSTRS_H
#include "llvm/CodeGen/MachineDominators.h" #include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineLoopInfo.h" #include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/ScheduleDAG.h" #include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/CodeGen/TargetSchedule.h"
#include "llvm/Support/Compiler.h" #include "llvm/Support/Compiler.h"
#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/ADT/SmallSet.h" #include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/SparseSet.h" #include "llvm/ADT/SparseSet.h"
#include <map> #include <map>
namespace llvm { namespace llvm {
class MachineLoopInfo; class MachineLoopInfo;
class MachineDominatorTree; class MachineDominatorTree;
class LiveIntervals; class LiveIntervals;
class RegPressureTracker;
/// LoopDependencies - This class analyzes loop-oriented register
/// dependencies, which are used to guide scheduling decisions.
/// For example, loop induction variable increments should be
/// scheduled as soon as possible after the variable's last use.
///
class LoopDependencies {
const MachineLoopInfo &MLI;
const MachineDominatorTree &MDT;
public:
typedef std::map<unsigned, std::pair<const MachineOperand *, unsigned>
>
LoopDeps;
LoopDeps Deps;
LoopDependencies(const MachineLoopInfo &mli,
const MachineDominatorTree &mdt) :
MLI(mli), MDT(mdt) {}
/// VisitLoop - Clear out any previous state and analyze the given loop
.
///
void VisitLoop(const MachineLoop *Loop) {
assert(Deps.empty() && "stale loop dependencies");
MachineBasicBlock *Header = Loop->getHeader();
SmallSet<unsigned, 8> LoopLiveIns;
for (MachineBasicBlock::livein_iterator LI = Header->livein_begin(),
LE = Header->livein_end(); LI != LE; ++LI)
LoopLiveIns.insert(*LI);
const MachineDomTreeNode *Node = MDT.getNode(Header);
const MachineBasicBlock *MBB = Node->getBlock();
assert(Loop->contains(MBB) &&
"Loop does not contain header!");
VisitRegion(Node, MBB, Loop, LoopLiveIns);
}
private:
void VisitRegion(const MachineDomTreeNode *Node,
const MachineBasicBlock *MBB,
const MachineLoop *Loop,
const SmallSet<unsigned, 8> &LoopLiveIns) {
unsigned Count = 0;
for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end
();
I != E; ++I) {
const MachineInstr *MI = I;
if (MI->isDebugValue())
continue;
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
if (!MO.isReg() || !MO.isUse())
continue;
unsigned MOReg = MO.getReg();
if (LoopLiveIns.count(MOReg))
Deps.insert(std::make_pair(MOReg, std::make_pair(&MO, Count)));
}
++Count; // Not every iteration due to dbg_value above.
}
const std::vector<MachineDomTreeNode*> &Children = Node->getChildren(
);
for (std::vector<MachineDomTreeNode*>::const_iterator I =
Children.begin(), E = Children.end(); I != E; ++I) {
const MachineDomTreeNode *ChildNode = *I;
MachineBasicBlock *ChildBlock = ChildNode->getBlock();
if (Loop->contains(ChildBlock))
VisitRegion(ChildNode, ChildBlock, Loop, LoopLiveIns);
}
}
};
/// An individual mapping from virtual register number to SUnit. /// An individual mapping from virtual register number to SUnit.
struct VReg2SUnit { struct VReg2SUnit {
unsigned VirtReg; unsigned VirtReg;
SUnit *SU; SUnit *SU;
VReg2SUnit(unsigned reg, SUnit *su): VirtReg(reg), SU(su) {} VReg2SUnit(unsigned reg, SUnit *su): VirtReg(reg), SU(su) {}
unsigned getSparseSetKey() const { unsigned getSparseSetIndex() const {
return TargetRegisterInfo::virtReg2Index(VirtReg); return TargetRegisterInfo::virtReg2Index(VirtReg);
} }
}; };
/// Record a physical register access.
/// For non data-dependent uses, OpIdx == -1.
struct PhysRegSUOper {
SUnit *SU;
int OpIdx;
PhysRegSUOper(SUnit *su, int op): SU(su), OpIdx(op) {}
};
/// Combine a SparseSet with a 1x1 vector to track physical registers. /// Combine a SparseSet with a 1x1 vector to track physical registers.
/// The SparseSet allows iterating over the (few) live registers for quic kly /// The SparseSet allows iterating over the (few) live registers for quic kly
/// comparing against a regmask or clearing the set. /// comparing against a regmask or clearing the set.
/// ///
/// Storage for the map is allocated once for the pass. The map can be /// Storage for the map is allocated once for the pass. The map can be
/// cleared between scheduling regions without freeing unused entries. /// cleared between scheduling regions without freeing unused entries.
class Reg2SUnitsMap { class Reg2SUnitsMap {
SparseSet<unsigned> PhysRegSet; SparseSet<unsigned> PhysRegSet;
std::vector<std::vector<SUnit*> > SUnits; std::vector<std::vector<PhysRegSUOper> > SUnits;
public: public:
typedef SparseSet<unsigned>::const_iterator const_iterator; typedef SparseSet<unsigned>::const_iterator const_iterator;
// Allow iteration over register numbers (keys) in the map. If needed, we // Allow iteration over register numbers (keys) in the map. If needed, we
// can provide an iterator over SUnits (values) as well. // can provide an iterator over SUnits (values) as well.
const_iterator reg_begin() const { return PhysRegSet.begin(); } const_iterator reg_begin() const { return PhysRegSet.begin(); }
const_iterator reg_end() const { return PhysRegSet.end(); } const_iterator reg_end() const { return PhysRegSet.end(); }
/// Initialize the map with the number of registers. /// Initialize the map with the number of registers.
/// If the map is already large enough, no allocation occurs. /// If the map is already large enough, no allocation occurs.
skipping to change at line 145 skipping to change at line 87
/// Returns true if the map is empty. /// Returns true if the map is empty.
bool empty() const { return PhysRegSet.empty(); } bool empty() const { return PhysRegSet.empty(); }
/// Clear the map without deallocating storage. /// Clear the map without deallocating storage.
void clear(); void clear();
bool contains(unsigned Reg) const { return PhysRegSet.count(Reg); } bool contains(unsigned Reg) const { return PhysRegSet.count(Reg); }
/// If this register is mapped, return its existing SUnits vector. /// If this register is mapped, return its existing SUnits vector.
/// Otherwise map the register and return an empty SUnits vector. /// Otherwise map the register and return an empty SUnits vector.
std::vector<SUnit *> &operator[](unsigned Reg) { std::vector<PhysRegSUOper> &operator[](unsigned Reg) {
bool New = PhysRegSet.insert(Reg).second; bool New = PhysRegSet.insert(Reg).second;
assert((!New || SUnits[Reg].empty()) && "stale SUnits vector"); assert((!New || SUnits[Reg].empty()) && "stale SUnits vector");
(void)New; (void)New;
return SUnits[Reg]; return SUnits[Reg];
} }
/// Erase an existing element without freeing memory. /// Erase an existing element without freeing memory.
void erase(unsigned Reg) { void erase(unsigned Reg) {
PhysRegSet.erase(Reg); PhysRegSet.erase(Reg);
SUnits[Reg].clear(); SUnits[Reg].clear();
} }
}; };
/// Use SparseSet as a SparseMap by relying on the fact that it never /// Use SparseSet as a SparseMap by relying on the fact that it never
/// compares ValueT's, only unsigned keys. This allows the set to be clea red /// compares ValueT's, only unsigned keys. This allows the set to be clea red
/// between scheduling regions in constant time as long as ValueT does no t /// between scheduling regions in constant time as long as ValueT does no t
/// require a destructor. /// require a destructor.
typedef SparseSet<VReg2SUnit> VReg2SUnitMap; typedef SparseSet<VReg2SUnit, VirtReg2IndexFunctor> VReg2SUnitMap;
/// ScheduleDAGInstrs - A ScheduleDAG subclass for scheduling lists of /// ScheduleDAGInstrs - A ScheduleDAG subclass for scheduling lists of
/// MachineInstrs. /// MachineInstrs.
class ScheduleDAGInstrs : public ScheduleDAG { class ScheduleDAGInstrs : public ScheduleDAG {
protected: protected:
const MachineLoopInfo &MLI; const MachineLoopInfo &MLI;
const MachineDominatorTree &MDT; const MachineDominatorTree &MDT;
const MachineFrameInfo *MFI; const MachineFrameInfo *MFI;
const InstrItineraryData *InstrItins;
/// Live Intervals provides reaching defs in preRA scheduling. /// Live Intervals provides reaching defs in preRA scheduling.
LiveIntervals *LIS; LiveIntervals *LIS;
/// TargetSchedModel provides an interface to the machine model.
TargetSchedModel SchedModel;
/// isPostRA flag indicates vregs cannot be present. /// isPostRA flag indicates vregs cannot be present.
bool IsPostRA; bool IsPostRA;
/// UnitLatencies (misnamed) flag avoids computing def-use latencies, u sing /// UnitLatencies (misnamed) flag avoids computing def-use latencies, u sing
/// the def-side latency only. /// the def-side latency only.
bool UnitLatencies; bool UnitLatencies;
/// The standard DAG builder does not normally include terminators as D AG /// The standard DAG builder does not normally include terminators as D AG
/// nodes because it does not create the necessary dependencies to prev ent /// nodes because it does not create the necessary dependencies to prev ent
/// reordering. A specialized scheduler can overide /// reordering. A specialized scheduler can overide
skipping to change at line 228 skipping to change at line 172
Reg2SUnitsMap Uses; Reg2SUnitsMap Uses;
/// Track the last instructon in this region defining each virtual regi ster. /// Track the last instructon in this region defining each virtual regi ster.
VReg2SUnitMap VRegDefs; VReg2SUnitMap VRegDefs;
/// PendingLoads - Remember where unknown loads are after the most rece nt /// PendingLoads - Remember where unknown loads are after the most rece nt
/// unknown store, as we iterate. As with Defs and Uses, this is here /// unknown store, as we iterate. As with Defs and Uses, this is here
/// to minimize construction/destruction. /// to minimize construction/destruction.
std::vector<SUnit *> PendingLoads; std::vector<SUnit *> PendingLoads;
/// LoopRegs - Track which registers are used for loop-carried dependen /// DbgValues - Remember instruction that precedes DBG_VALUE.
cies.
///
LoopDependencies LoopRegs;
/// DbgValues - Remember instruction that preceeds DBG_VALUE.
/// These are generated by buildSchedGraph but persist so they can be /// These are generated by buildSchedGraph but persist so they can be
/// referenced when emitting the final schedule. /// referenced when emitting the final schedule.
typedef std::vector<std::pair<MachineInstr *, MachineInstr *> > typedef std::vector<std::pair<MachineInstr *, MachineInstr *> >
DbgValueVector; DbgValueVector;
DbgValueVector DbgValues; DbgValueVector DbgValues;
MachineInstr *FirstDbgValue; MachineInstr *FirstDbgValue;
public: public:
explicit ScheduleDAGInstrs(MachineFunction &mf, explicit ScheduleDAGInstrs(MachineFunction &mf,
const MachineLoopInfo &mli, const MachineLoopInfo &mli,
const MachineDominatorTree &mdt, const MachineDominatorTree &mdt,
bool IsPostRAFlag, bool IsPostRAFlag,
LiveIntervals *LIS = 0); LiveIntervals *LIS = 0);
virtual ~ScheduleDAGInstrs() {} virtual ~ScheduleDAGInstrs() {}
/// \brief Get the machine model for instruction scheduling.
const TargetSchedModel *getSchedModel() const { return &SchedModel; }
/// \brief Resolve and cache a resolved scheduling class for an SUnit.
const MCSchedClassDesc *getSchedClass(SUnit *SU) const {
if (!SU->SchedClass)
SU->SchedClass = SchedModel.resolveSchedClass(SU->getInstr());
return SU->SchedClass;
}
/// begin - Return an iterator to the top of the current scheduling reg ion. /// begin - Return an iterator to the top of the current scheduling reg ion.
MachineBasicBlock::iterator begin() const { return RegionBegin; } MachineBasicBlock::iterator begin() const { return RegionBegin; }
/// end - Return an iterator to the bottom of the current scheduling re gion. /// end - Return an iterator to the bottom of the current scheduling re gion.
MachineBasicBlock::iterator end() const { return RegionEnd; } MachineBasicBlock::iterator end() const { return RegionEnd; }
/// newSUnit - Creates a new SUnit and return a ptr to it. /// newSUnit - Creates a new SUnit and return a ptr to it.
SUnit *newSUnit(MachineInstr *MI); SUnit *newSUnit(MachineInstr *MI);
/// getSUnit - Return an existing SUnit for this MI, or NULL. /// getSUnit - Return an existing SUnit for this MI, or NULL.
skipping to change at line 278 skipping to change at line 228
virtual void enterRegion(MachineBasicBlock *bb, virtual void enterRegion(MachineBasicBlock *bb,
MachineBasicBlock::iterator begin, MachineBasicBlock::iterator begin,
MachineBasicBlock::iterator end, MachineBasicBlock::iterator end,
unsigned endcount); unsigned endcount);
/// Notify that the scheduler has finished scheduling the current regio n. /// Notify that the scheduler has finished scheduling the current regio n.
virtual void exitRegion(); virtual void exitRegion();
/// buildSchedGraph - Build SUnits from the MachineBasicBlock that we a re /// buildSchedGraph - Build SUnits from the MachineBasicBlock that we a re
/// input. /// input.
void buildSchedGraph(AliasAnalysis *AA); void buildSchedGraph(AliasAnalysis *AA, RegPressureTracker *RPTracker = 0);
/// addSchedBarrierDeps - Add dependencies from instructions in the cur rent /// addSchedBarrierDeps - Add dependencies from instructions in the cur rent
/// list of instructions being scheduled to scheduling barrier. We want to /// list of instructions being scheduled to scheduling barrier. We want to
/// make sure instructions which define registers that are either used by /// make sure instructions which define registers that are either used by
/// the terminator or are live-out are properly scheduled. This is /// the terminator or are live-out are properly scheduled. This is
/// especially important when the definition latency of the return valu e(s) /// especially important when the definition latency of the return valu e(s)
/// are too high to be hidden by the branch or when the liveout registe rs /// are too high to be hidden by the branch or when the liveout registe rs
/// used by instructions in the fallthrough block. /// used by instructions in the fallthrough block.
void addSchedBarrierDeps(); void addSchedBarrierDeps();
/// computeLatency - Compute node latency.
///
virtual void computeLatency(SUnit *SU);
/// computeOperandLatency - Override dependence edge latency using
/// operand use/def information
///
virtual void computeOperandLatency(SUnit *Def, SUnit *Use,
SDep& dep) const;
/// schedule - Order nodes according to selected style, filling /// schedule - Order nodes according to selected style, filling
/// in the Sequence member. /// in the Sequence member.
/// ///
/// Typically, a scheduling algorithm will implement schedule() without /// Typically, a scheduling algorithm will implement schedule() without
/// overriding enterRegion() or exitRegion(). /// overriding enterRegion() or exitRegion().
virtual void schedule() = 0; virtual void schedule() = 0;
/// finalizeSchedule - Allow targets to perform final scheduling action s at /// finalizeSchedule - Allow targets to perform final scheduling action s at
/// the level of the whole MachineFunction. By default does nothing. /// the level of the whole MachineFunction. By default does nothing.
virtual void finalizeSchedule() {} virtual void finalizeSchedule() {}
skipping to change at line 320 skipping to change at line 260
virtual void dumpNode(const SUnit *SU) const; virtual void dumpNode(const SUnit *SU) const;
/// Return a label for a DAG node that points to an instruction. /// Return a label for a DAG node that points to an instruction.
virtual std::string getGraphNodeLabel(const SUnit *SU) const; virtual std::string getGraphNodeLabel(const SUnit *SU) const;
/// Return a label for the region of code covered by the DAG. /// Return a label for the region of code covered by the DAG.
virtual std::string getDAGName() const; virtual std::string getDAGName() const;
protected: protected:
void initSUnits(); void initSUnits();
void addPhysRegDataDeps(SUnit *SU, const MachineOperand &MO); void addPhysRegDataDeps(SUnit *SU, unsigned OperIdx);
void addPhysRegDeps(SUnit *SU, unsigned OperIdx); void addPhysRegDeps(SUnit *SU, unsigned OperIdx);
void addVRegDefDeps(SUnit *SU, unsigned OperIdx); void addVRegDefDeps(SUnit *SU, unsigned OperIdx);
void addVRegUseDeps(SUnit *SU, unsigned OperIdx); void addVRegUseDeps(SUnit *SU, unsigned OperIdx);
VReg2SUnitMap::iterator findVRegDef(unsigned VirtReg) {
return VRegDefs.find(TargetRegisterInfo::virtReg2Index(VirtReg));
}
}; };
/// newSUnit - Creates a new SUnit and return a ptr to it. /// newSUnit - Creates a new SUnit and return a ptr to it.
inline SUnit *ScheduleDAGInstrs::newSUnit(MachineInstr *MI) { inline SUnit *ScheduleDAGInstrs::newSUnit(MachineInstr *MI) {
#ifndef NDEBUG #ifndef NDEBUG
const SUnit *Addr = SUnits.empty() ? 0 : &SUnits[0]; const SUnit *Addr = SUnits.empty() ? 0 : &SUnits[0];
#endif #endif
SUnits.push_back(SUnit(MI, (unsigned)SUnits.size())); SUnits.push_back(SUnit(MI, (unsigned)SUnits.size()));
assert((Addr == 0 || Addr == &SUnits[0]) && assert((Addr == 0 || Addr == &SUnits[0]) &&
"SUnits std::vector reallocated on the fly!"); "SUnits std::vector reallocated on the fly!");
 End of changes. 15 change blocks. 
100 lines changed or deleted 31 lines changed or added


 ScheduleHazardRecognizer.h   ScheduleHazardRecognizer.h 
skipping to change at line 49 skipping to change at line 49
Hazard, // This instruction can't be emitted at this cycle. Hazard, // This instruction can't be emitted at this cycle.
NoopHazard // This instruction can't be emitted, and needs noops. NoopHazard // This instruction can't be emitted, and needs noops.
}; };
unsigned getMaxLookAhead() const { return MaxLookAhead; } unsigned getMaxLookAhead() const { return MaxLookAhead; }
bool isEnabled() const { return MaxLookAhead != 0; } bool isEnabled() const { return MaxLookAhead != 0; }
/// atIssueLimit - Return true if no more instructions may be issued in t his /// atIssueLimit - Return true if no more instructions may be issued in t his
/// cycle. /// cycle.
///
/// FIXME: remove this once MachineScheduler is the only client.
virtual bool atIssueLimit() const { return false; } virtual bool atIssueLimit() const { return false; }
/// getHazardType - Return the hazard type of emitting this node. There are /// getHazardType - Return the hazard type of emitting this node. There are
/// three possible results. Either: /// three possible results. Either:
/// * NoHazard: it is legal to issue this instruction on this cycle. /// * NoHazard: it is legal to issue this instruction on this cycle.
/// * Hazard: issuing this instruction would stall the machine. If some /// * Hazard: issuing this instruction would stall the machine. If some
/// other instruction is available, issue it first. /// other instruction is available, issue it first.
/// * NoopHazard: issuing this instruction would break the program. If /// * NoopHazard: issuing this instruction would break the program. If
/// some other instruction can be issued, do so, otherwise issue a no op. /// some other instruction can be issued, do so, otherwise issue a no op.
virtual HazardType getHazardType(SUnit *m, int Stalls) { virtual HazardType getHazardType(SUnit *m, int Stalls = 0) {
return NoHazard; return NoHazard;
} }
/// Reset - This callback is invoked when a new block of /// Reset - This callback is invoked when a new block of
/// instructions is about to be schedule. The hazard state should be /// instructions is about to be schedule. The hazard state should be
/// set to an initialized state. /// set to an initialized state.
virtual void Reset() {} virtual void Reset() {}
/// EmitInstruction - This callback is invoked when an instruction is /// EmitInstruction - This callback is invoked when an instruction is
/// emitted, to advance the hazard state. /// emitted, to advance the hazard state.
 End of changes. 2 change blocks. 
1 lines changed or deleted 3 lines changed or added


 SchedulerRegistry.h   SchedulerRegistry.h 
skipping to change at line 104 skipping to change at line 104
/// createVLIWDAGScheduler - Scheduler for VLIW targets. This creates top d own /// createVLIWDAGScheduler - Scheduler for VLIW targets. This creates top d own
/// DFA driven list scheduler with clustering heuristic to control /// DFA driven list scheduler with clustering heuristic to control
/// register pressure. /// register pressure.
ScheduleDAGSDNodes *createVLIWDAGScheduler(SelectionDAGISel *IS, ScheduleDAGSDNodes *createVLIWDAGScheduler(SelectionDAGISel *IS,
CodeGenOpt::Level OptLevel); CodeGenOpt::Level OptLevel);
/// createDefaultScheduler - This creates an instruction scheduler appropri ate /// createDefaultScheduler - This creates an instruction scheduler appropri ate
/// for the target. /// for the target.
ScheduleDAGSDNodes *createDefaultScheduler(SelectionDAGISel *IS, ScheduleDAGSDNodes *createDefaultScheduler(SelectionDAGISel *IS,
CodeGenOpt::Level OptLevel); CodeGenOpt::Level OptLevel);
/// createDAGLinearizer - This creates a "no-scheduling" scheduler which
/// linearize the DAG using topological order.
ScheduleDAGSDNodes *createDAGLinearizer(SelectionDAGISel *IS,
CodeGenOpt::Level OptLevel);
} // end namespace llvm } // end namespace llvm
#endif #endif
 End of changes. 1 change blocks. 
0 lines changed or deleted 5 lines changed or added


 ScopedHashTable.h   ScopedHashTable.h 
skipping to change at line 93 skipping to change at line 93
class ScopedHashTableScope { class ScopedHashTableScope {
/// HT - The hashtable that we are active for. /// HT - The hashtable that we are active for.
ScopedHashTable<K, V, KInfo, AllocatorTy> &HT; ScopedHashTable<K, V, KInfo, AllocatorTy> &HT;
/// PrevScope - This is the scope that we are shadowing in HT. /// PrevScope - This is the scope that we are shadowing in HT.
ScopedHashTableScope *PrevScope; ScopedHashTableScope *PrevScope;
/// LastValInScope - This is the last value that was inserted for this sc ope /// LastValInScope - This is the last value that was inserted for this sc ope
/// or null if none have been inserted yet. /// or null if none have been inserted yet.
ScopedHashTableVal<K, V> *LastValInScope; ScopedHashTableVal<K, V> *LastValInScope;
void operator=(ScopedHashTableScope&); // DO NOT IMPLEMENT void operator=(ScopedHashTableScope&) LLVM_DELETED_FUNCTION;
ScopedHashTableScope(ScopedHashTableScope&); // DO NOT IMPLEMENT ScopedHashTableScope(ScopedHashTableScope&) LLVM_DELETED_FUNCTION;
public: public:
ScopedHashTableScope(ScopedHashTable<K, V, KInfo, AllocatorTy> &HT); ScopedHashTableScope(ScopedHashTable<K, V, KInfo, AllocatorTy> &HT);
~ScopedHashTableScope(); ~ScopedHashTableScope();
ScopedHashTableScope *getParentScope() { return PrevScope; } ScopedHashTableScope *getParentScope() { return PrevScope; }
const ScopedHashTableScope *getParentScope() const { return PrevScope; } const ScopedHashTableScope *getParentScope() const { return PrevScope; }
private: private:
friend class ScopedHashTable<K, V, KInfo, AllocatorTy>; friend class ScopedHashTable<K, V, KInfo, AllocatorTy>;
ScopedHashTableVal<K, V> *getLastValInScope() { ScopedHashTableVal<K, V> *getLastValInScope() {
 End of changes. 1 change blocks. 
2 lines changed or deleted 2 lines changed or added


 SelectionDAG.h   SelectionDAG.h 
skipping to change at line 76 skipping to change at line 76
/// which busts the normal mechanism. There is good reason for handling al l /// which busts the normal mechanism. There is good reason for handling al l
/// parameters separately: they may not have code generated for them, they /// parameters separately: they may not have code generated for them, they
/// should always go at the beginning of the function regardless of other c ode /// should always go at the beginning of the function regardless of other c ode
/// motion, and debug info for them is potentially useful even if the param eter /// motion, and debug info for them is potentially useful even if the param eter
/// is unused. Right now only byval parameters are handled separately. /// is unused. Right now only byval parameters are handled separately.
class SDDbgInfo { class SDDbgInfo {
SmallVector<SDDbgValue*, 32> DbgValues; SmallVector<SDDbgValue*, 32> DbgValues;
SmallVector<SDDbgValue*, 32> ByvalParmDbgValues; SmallVector<SDDbgValue*, 32> ByvalParmDbgValues;
DenseMap<const SDNode*, SmallVector<SDDbgValue*, 2> > DbgValMap; DenseMap<const SDNode*, SmallVector<SDDbgValue*, 2> > DbgValMap;
void operator=(const SDDbgInfo&); // Do not implement. void operator=(const SDDbgInfo&) LLVM_DELETED_FUNCTION;
SDDbgInfo(const SDDbgInfo&); // Do not implement. SDDbgInfo(const SDDbgInfo&) LLVM_DELETED_FUNCTION;
public: public:
SDDbgInfo() {} SDDbgInfo() {}
void add(SDDbgValue *V, const SDNode *Node, bool isParameter) { void add(SDDbgValue *V, const SDNode *Node, bool isParameter) {
if (isParameter) { if (isParameter) {
ByvalParmDbgValues.push_back(V); ByvalParmDbgValues.push_back(V);
} else DbgValues.push_back(V); } else DbgValues.push_back(V);
if (Node) if (Node)
DbgValMap[Node].push_back(V); DbgValMap[Node].push_back(V);
} }
skipping to change at line 180 skipping to change at line 180
/// SelectionDAG. /// SelectionDAG.
BumpPtrAllocator Allocator; BumpPtrAllocator Allocator;
/// SDNodeOrdering - The ordering of the SDNodes. It roughly corresponds to /// SDNodeOrdering - The ordering of the SDNodes. It roughly corresponds to
/// the ordering of the original LLVM instructions. /// the ordering of the original LLVM instructions.
SDNodeOrdering *Ordering; SDNodeOrdering *Ordering;
/// DbgInfo - Tracks dbg_value information through SDISel. /// DbgInfo - Tracks dbg_value information through SDISel.
SDDbgInfo *DbgInfo; SDDbgInfo *DbgInfo;
public:
/// DAGUpdateListener - Clients of various APIs that cause global effects
on
/// the DAG can optionally implement this interface. This allows the cli
ents
/// to handle the various sorts of updates that happen.
///
/// A DAGUpdateListener automatically registers itself with DAG when it i
s
/// constructed, and removes itself when destroyed in RAII fashion.
struct DAGUpdateListener {
DAGUpdateListener *const Next;
SelectionDAG &DAG;
explicit DAGUpdateListener(SelectionDAG &D)
: Next(D.UpdateListeners), DAG(D) {
DAG.UpdateListeners = this;
}
virtual ~DAGUpdateListener() {
assert(DAG.UpdateListeners == this &&
"DAGUpdateListeners must be destroyed in LIFO order");
DAG.UpdateListeners = Next;
}
/// NodeDeleted - The node N that was deleted and, if E is not null, an
/// equivalent node E that replaced it.
virtual void NodeDeleted(SDNode *N, SDNode *E);
/// NodeUpdated - The node N that was updated.
virtual void NodeUpdated(SDNode *N);
};
private:
/// DAGUpdateListener is a friend so it can manipulate the listener stack
.
friend struct DAGUpdateListener;
/// UpdateListeners - Linked list of registered DAGUpdateListener instanc
es.
/// This stack is maintained by DAGUpdateListener RAII.
DAGUpdateListener *UpdateListeners;
/// setGraphColorHelper - Implementation of setSubgraphColor. /// setGraphColorHelper - Implementation of setSubgraphColor.
/// Return whether we had to truncate the search. /// Return whether we had to truncate the search.
/// ///
bool setSubgraphColorHelper(SDNode *N, const char *Color, bool setSubgraphColorHelper(SDNode *N, const char *Color,
DenseSet<SDNode *> &visited, DenseSet<SDNode *> &visited,
int level, bool &printed); int level, bool &printed);
void operator=(const SelectionDAG&); // Do not implement. void operator=(const SelectionDAG&) LLVM_DELETED_FUNCTION;
SelectionDAG(const SelectionDAG&); // Do not implement. SelectionDAG(const SelectionDAG&) LLVM_DELETED_FUNCTION;
public: public:
explicit SelectionDAG(const TargetMachine &TM, llvm::CodeGenOpt::Level); explicit SelectionDAG(const TargetMachine &TM, llvm::CodeGenOpt::Level);
~SelectionDAG(); ~SelectionDAG();
/// init - Prepare this SelectionDAG to process code in the given /// init - Prepare this SelectionDAG to process code in the given
/// MachineFunction. /// MachineFunction.
/// ///
void init(MachineFunction &mf); void init(MachineFunction &mf);
skipping to change at line 387 skipping to change at line 425
return getConstantPool(C, VT, Align, Offset, true, TargetFlags); return getConstantPool(C, VT, Align, Offset, true, TargetFlags);
} }
SDValue getConstantPool(MachineConstantPoolValue *C, EVT VT, SDValue getConstantPool(MachineConstantPoolValue *C, EVT VT,
unsigned Align = 0, int Offs = 0, bool isT=false, unsigned Align = 0, int Offs = 0, bool isT=false,
unsigned char TargetFlags = 0); unsigned char TargetFlags = 0);
SDValue getTargetConstantPool(MachineConstantPoolValue *C, SDValue getTargetConstantPool(MachineConstantPoolValue *C,
EVT VT, unsigned Align = 0, EVT VT, unsigned Align = 0,
int Offset = 0, unsigned char TargetFlags =0) { int Offset = 0, unsigned char TargetFlags =0) {
return getConstantPool(C, VT, Align, Offset, true, TargetFlags); return getConstantPool(C, VT, Align, Offset, true, TargetFlags);
} }
SDValue getTargetIndex(int Index, EVT VT, int64_t Offset = 0,
unsigned char TargetFlags = 0);
// When generating a branch to a BB, we don't in general know enough // When generating a branch to a BB, we don't in general know enough
// to provide debug info for the BB at that time, so keep this one around . // to provide debug info for the BB at that time, so keep this one around .
SDValue getBasicBlock(MachineBasicBlock *MBB); SDValue getBasicBlock(MachineBasicBlock *MBB);
SDValue getBasicBlock(MachineBasicBlock *MBB, DebugLoc dl); SDValue getBasicBlock(MachineBasicBlock *MBB, DebugLoc dl);
SDValue getExternalSymbol(const char *Sym, EVT VT); SDValue getExternalSymbol(const char *Sym, EVT VT);
SDValue getExternalSymbol(const char *Sym, DebugLoc dl, EVT VT); SDValue getExternalSymbol(const char *Sym, DebugLoc dl, EVT VT);
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, SDValue getTargetExternalSymbol(const char *Sym, EVT VT,
unsigned char TargetFlags = 0); unsigned char TargetFlags = 0);
SDValue getValueType(EVT); SDValue getValueType(EVT);
SDValue getRegister(unsigned Reg, EVT VT); SDValue getRegister(unsigned Reg, EVT VT);
SDValue getRegisterMask(const uint32_t *RegMask); SDValue getRegisterMask(const uint32_t *RegMask);
SDValue getEHLabel(DebugLoc dl, SDValue Root, MCSymbol *Label); SDValue getEHLabel(DebugLoc dl, SDValue Root, MCSymbol *Label);
SDValue getBlockAddress(const BlockAddress *BA, EVT VT, SDValue getBlockAddress(const BlockAddress *BA, EVT VT,
bool isTarget = false, unsigned char TargetFlags int64_t Offset = 0, bool isTarget = false,
= 0); unsigned char TargetFlags = 0);
SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT,
int64_t Offset = 0,
unsigned char TargetFlags = 0) {
return getBlockAddress(BA, VT, Offset, true, TargetFlags);
}
SDValue getCopyToReg(SDValue Chain, DebugLoc dl, unsigned Reg, SDValue N) { SDValue getCopyToReg(SDValue Chain, DebugLoc dl, unsigned Reg, SDValue N) {
return getNode(ISD::CopyToReg, dl, MVT::Other, Chain, return getNode(ISD::CopyToReg, dl, MVT::Other, Chain,
getRegister(Reg, N.getValueType()), N); getRegister(Reg, N.getValueType()), N);
} }
// This version of the getCopyToReg method takes an extra operand, which // This version of the getCopyToReg method takes an extra operand, which
// indicates that there is potentially an incoming glue value (if Glue is not // indicates that there is potentially an incoming glue value (if Glue is not
// null) and that there should be a glue result. // null) and that there should be a glue result.
SDValue getCopyToReg(SDValue Chain, DebugLoc dl, unsigned Reg, SDValue N, SDValue getCopyToReg(SDValue Chain, DebugLoc dl, unsigned Reg, SDValue N,
skipping to change at line 820 skipping to change at line 866
/// getDbgValue - Creates a SDDbgValue node. /// getDbgValue - Creates a SDDbgValue node.
/// ///
SDDbgValue *getDbgValue(MDNode *MDPtr, SDNode *N, unsigned R, uint64_t Of f, SDDbgValue *getDbgValue(MDNode *MDPtr, SDNode *N, unsigned R, uint64_t Of f,
DebugLoc DL, unsigned O); DebugLoc DL, unsigned O);
SDDbgValue *getDbgValue(MDNode *MDPtr, const Value *C, uint64_t Off, SDDbgValue *getDbgValue(MDNode *MDPtr, const Value *C, uint64_t Off,
DebugLoc DL, unsigned O); DebugLoc DL, unsigned O);
SDDbgValue *getDbgValue(MDNode *MDPtr, unsigned FI, uint64_t Off, SDDbgValue *getDbgValue(MDNode *MDPtr, unsigned FI, uint64_t Off,
DebugLoc DL, unsigned O); DebugLoc DL, unsigned O);
/// DAGUpdateListener - Clients of various APIs that cause global effects
on
/// the DAG can optionally implement this interface. This allows the cli
ents
/// to handle the various sorts of updates that happen.
class DAGUpdateListener {
public:
virtual ~DAGUpdateListener();
/// NodeDeleted - The node N that was deleted and, if E is not null, an
/// equivalent node E that replaced it.
virtual void NodeDeleted(SDNode *N, SDNode *E) = 0;
/// NodeUpdated - The node N that was updated.
virtual void NodeUpdated(SDNode *N) = 0;
};
/// RemoveDeadNode - Remove the specified node from the system. If any of its /// RemoveDeadNode - Remove the specified node from the system. If any of its
/// operands then becomes dead, remove them as well. Inform UpdateListene r /// operands then becomes dead, remove them as well. Inform UpdateListene r
/// for each node deleted. /// for each node deleted.
void RemoveDeadNode(SDNode *N, DAGUpdateListener *UpdateListener = 0); void RemoveDeadNode(SDNode *N);
/// RemoveDeadNodes - This method deletes the unreachable nodes in the /// RemoveDeadNodes - This method deletes the unreachable nodes in the
/// given list, and any nodes that become unreachable as a result. /// given list, and any nodes that become unreachable as a result.
void RemoveDeadNodes(SmallVectorImpl<SDNode *> &DeadNodes, void RemoveDeadNodes(SmallVectorImpl<SDNode *> &DeadNodes);
DAGUpdateListener *UpdateListener = 0);
/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead . /// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead .
/// This can cause recursive merging of nodes in the DAG. Use the first /// This can cause recursive merging of nodes in the DAG. Use the first
/// version if 'From' is known to have a single result, use the second /// version if 'From' is known to have a single result, use the second
/// if you have two nodes with identical results (or if 'To' has a supers et /// if you have two nodes with identical results (or if 'To' has a supers et
/// of the results of 'From'), use the third otherwise. /// of the results of 'From'), use the third otherwise.
/// ///
/// These methods all take an optional UpdateListener, which (if not null ) is /// These methods all take an optional UpdateListener, which (if not null ) is
/// informed about nodes that are deleted and modified due to recursive /// informed about nodes that are deleted and modified due to recursive
/// changes in the dag. /// changes in the dag.
/// ///
/// These functions only replace all existing uses. It's possible that as /// These functions only replace all existing uses. It's possible that as
/// these replacements are being performed, CSE may cause the From node /// these replacements are being performed, CSE may cause the From node
/// to be given new uses. These new uses of From are left in place, and /// to be given new uses. These new uses of From are left in place, and
/// not automatically transferred to To. /// not automatically transferred to To.
/// ///
void ReplaceAllUsesWith(SDValue From, SDValue Op, void ReplaceAllUsesWith(SDValue From, SDValue Op);
DAGUpdateListener *UpdateListener = 0); void ReplaceAllUsesWith(SDNode *From, SDNode *To);
void ReplaceAllUsesWith(SDNode *From, SDNode *To, void ReplaceAllUsesWith(SDNode *From, const SDValue *To);
DAGUpdateListener *UpdateListener = 0);
void ReplaceAllUsesWith(SDNode *From, const SDValue *To,
DAGUpdateListener *UpdateListener = 0);
/// ReplaceAllUsesOfValueWith - Replace any uses of From with To, leaving /// ReplaceAllUsesOfValueWith - Replace any uses of From with To, leaving
/// uses of other values produced by From.Val alone. /// uses of other values produced by From.Val alone.
void ReplaceAllUsesOfValueWith(SDValue From, SDValue To, void ReplaceAllUsesOfValueWith(SDValue From, SDValue To);
DAGUpdateListener *UpdateListener = 0);
/// ReplaceAllUsesOfValuesWith - Like ReplaceAllUsesOfValueWith, but /// ReplaceAllUsesOfValuesWith - Like ReplaceAllUsesOfValueWith, but
/// for multiple values at once. This correctly handles the case where /// for multiple values at once. This correctly handles the case where
/// there is an overlap between the From values and the To values. /// there is an overlap between the From values and the To values.
void ReplaceAllUsesOfValuesWith(const SDValue *From, const SDValue *To, void ReplaceAllUsesOfValuesWith(const SDValue *From, const SDValue *To,
unsigned Num, unsigned Num);
DAGUpdateListener *UpdateListener = 0);
/// AssignTopologicalOrder - Topological-sort the AllNodes list and a /// AssignTopologicalOrder - Topological-sort the AllNodes list and a
/// assign a unique node id for each node in the DAG based on their /// assign a unique node id for each node in the DAG based on their
/// topological order. Returns the number of nodes. /// topological order. Returns the number of nodes.
unsigned AssignTopologicalOrder(); unsigned AssignTopologicalOrder();
/// RepositionNode - Move node N in the AllNodes list to be immediately /// RepositionNode - Move node N in the AllNodes list to be immediately
/// before the given iterator Position. This may be used to update the /// before the given iterator Position. This may be used to update the
/// topological ordering when the list of nodes is modified. /// topological ordering when the list of nodes is modified.
void RepositionNode(allnodes_iterator Position, SDNode *N) { void RepositionNode(allnodes_iterator Position, SDNode *N) {
skipping to change at line 1034 skipping to change at line 1059
/// is loading from. /// is loading from.
bool isConsecutiveLoad(LoadSDNode *LD, LoadSDNode *Base, bool isConsecutiveLoad(LoadSDNode *LD, LoadSDNode *Base,
unsigned Bytes, int Dist) const; unsigned Bytes, int Dist) const;
/// InferPtrAlignment - Infer alignment of a load / store address. Return 0 if /// InferPtrAlignment - Infer alignment of a load / store address. Return 0 if
/// it cannot be inferred. /// it cannot be inferred.
unsigned InferPtrAlignment(SDValue Ptr) const; unsigned InferPtrAlignment(SDValue Ptr) const;
private: private:
bool RemoveNodeFromCSEMaps(SDNode *N); bool RemoveNodeFromCSEMaps(SDNode *N);
void AddModifiedNodeToCSEMaps(SDNode *N, DAGUpdateListener *UpdateListene r); void AddModifiedNodeToCSEMaps(SDNode *N);
SDNode *FindModifiedNodeSlot(SDNode *N, SDValue Op, void *&InsertPos); SDNode *FindModifiedNodeSlot(SDNode *N, SDValue Op, void *&InsertPos);
SDNode *FindModifiedNodeSlot(SDNode *N, SDValue Op1, SDValue Op2, SDNode *FindModifiedNodeSlot(SDNode *N, SDValue Op1, SDValue Op2,
void *&InsertPos); void *&InsertPos);
SDNode *FindModifiedNodeSlot(SDNode *N, const SDValue *Ops, unsigned NumO ps, SDNode *FindModifiedNodeSlot(SDNode *N, const SDValue *Ops, unsigned NumO ps,
void *&InsertPos); void *&InsertPos);
SDNode *UpdadeDebugLocOnMergedSDNode(SDNode *N, DebugLoc loc); SDNode *UpdadeDebugLocOnMergedSDNode(SDNode *N, DebugLoc loc);
void DeleteNodeNotInCSEMaps(SDNode *N); void DeleteNodeNotInCSEMaps(SDNode *N);
void DeallocateNode(SDNode *N); void DeallocateNode(SDNode *N);
 End of changes. 12 change blocks. 
37 lines changed or deleted 64 lines changed or added


 SelectionDAGISel.h   SelectionDAGISel.h 
skipping to change at line 174 skipping to change at line 174
/// root. /// root.
static inline int getNumFixedFromVariadicInfo(unsigned Flags) { static inline int getNumFixedFromVariadicInfo(unsigned Flags) {
return ((Flags&OPFL_VariadicInfo) >> 4)-1; return ((Flags&OPFL_VariadicInfo) >> 4)-1;
} }
protected: protected:
/// DAGSize - Size of DAG being instruction selected. /// DAGSize - Size of DAG being instruction selected.
/// ///
unsigned DAGSize; unsigned DAGSize;
/// ISelPosition - Node iterator marking the current position of
/// instruction selection as it procedes through the topologically-sorted
/// node list.
SelectionDAG::allnodes_iterator ISelPosition;
/// ISelUpdater - helper class to handle updates of the
/// instruction selection graph.
class ISelUpdater : public SelectionDAG::DAGUpdateListener {
virtual void anchor();
SelectionDAG::allnodes_iterator &ISelPosition;
public:
explicit ISelUpdater(SelectionDAG::allnodes_iterator &isp)
: ISelPosition(isp) {}
/// NodeDeleted - Handle nodes deleted from the graph. If the
/// node being deleted is the current ISelPosition node, update
/// ISelPosition.
///
virtual void NodeDeleted(SDNode *N, SDNode *E) {
if (ISelPosition == SelectionDAG::allnodes_iterator(N))
++ISelPosition;
}
/// NodeUpdated - Ignore updates for now.
virtual void NodeUpdated(SDNode *N) {}
};
/// ReplaceUses - replace all uses of the old node F with the use /// ReplaceUses - replace all uses of the old node F with the use
/// of the new node T. /// of the new node T.
void ReplaceUses(SDValue F, SDValue T) { void ReplaceUses(SDValue F, SDValue T) {
ISelUpdater ISU(ISelPosition); CurDAG->ReplaceAllUsesOfValueWith(F, T);
CurDAG->ReplaceAllUsesOfValueWith(F, T, &ISU);
} }
/// ReplaceUses - replace all uses of the old nodes F with the use /// ReplaceUses - replace all uses of the old nodes F with the use
/// of the new nodes T. /// of the new nodes T.
void ReplaceUses(const SDValue *F, const SDValue *T, unsigned Num) { void ReplaceUses(const SDValue *F, const SDValue *T, unsigned Num) {
ISelUpdater ISU(ISelPosition); CurDAG->ReplaceAllUsesOfValuesWith(F, T, Num);
CurDAG->ReplaceAllUsesOfValuesWith(F, T, Num, &ISU);
} }
/// ReplaceUses - replace all uses of the old node F with the use /// ReplaceUses - replace all uses of the old node F with the use
/// of the new node T. /// of the new node T.
void ReplaceUses(SDNode *F, SDNode *T) { void ReplaceUses(SDNode *F, SDNode *T) {
ISelUpdater ISU(ISelPosition); CurDAG->ReplaceAllUsesWith(F, T);
CurDAG->ReplaceAllUsesWith(F, T, &ISU);
} }
/// SelectInlineAsmMemoryOperands - Calls to this are automatically gener ated /// SelectInlineAsmMemoryOperands - Calls to this are automatically gener ated
/// by tblgen. Others should not call it. /// by tblgen. Others should not call it.
void SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops); void SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops);
public: public:
// Calls to these predicates are generated by tblgen. // Calls to these predicates are generated by tblgen.
bool CheckAndMask(SDValue LHS, ConstantSDNode *RHS, bool CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
int64_t DesiredMaskS) const; int64_t DesiredMaskS) const;
 End of changes. 4 change blocks. 
33 lines changed or deleted 3 lines changed or added


 SelectionDAGNodes.h   SelectionDAGNodes.h 
skipping to change at line 77 skipping to change at line 77
bool isBuildVectorAllOnes(const SDNode *N); bool isBuildVectorAllOnes(const SDNode *N);
/// isBuildVectorAllZeros - Return true if the specified node is a /// isBuildVectorAllZeros - Return true if the specified node is a
/// BUILD_VECTOR where all of the elements are 0 or undef. /// BUILD_VECTOR where all of the elements are 0 or undef.
bool isBuildVectorAllZeros(const SDNode *N); bool isBuildVectorAllZeros(const SDNode *N);
/// isScalarToVector - Return true if the specified node is a /// isScalarToVector - Return true if the specified node is a
/// ISD::SCALAR_TO_VECTOR node or a BUILD_VECTOR node where only the low /// ISD::SCALAR_TO_VECTOR node or a BUILD_VECTOR node where only the low
/// element is not an undef. /// element is not an undef.
bool isScalarToVector(const SDNode *N); bool isScalarToVector(const SDNode *N);
/// allOperandsUndef - Return true if the node has at least one operand
/// and all operands of the specified node are ISD::UNDEF.
bool allOperandsUndef(const SDNode *N);
} // end llvm:ISD namespace } // end llvm:ISD namespace
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
/// SDValue - Unlike LLVM values, Selection DAG nodes may return multiple /// SDValue - Unlike LLVM values, Selection DAG nodes may return multiple
/// values as the result of a computation. Many nodes return multiple valu es, /// values as the result of a computation. Many nodes return multiple valu es,
/// from loads (which define a token and a return value) to ADDC (which ret urns /// from loads (which define a token and a return value) to ADDC (which ret urns
/// a result and a carry value), to calls (which may return an arbitrary nu mber /// a result and a carry value), to calls (which may return an arbitrary nu mber
/// of values). /// of values).
/// ///
/// As such, each use of a SelectionDAG computation must indicate the node that /// As such, each use of a SelectionDAG computation must indicate the node that
skipping to change at line 145 skipping to change at line 149
// Forwarding methods - These forward to the corresponding methods in SDN ode. // Forwarding methods - These forward to the corresponding methods in SDN ode.
inline unsigned getOpcode() const; inline unsigned getOpcode() const;
inline unsigned getNumOperands() const; inline unsigned getNumOperands() const;
inline const SDValue &getOperand(unsigned i) const; inline const SDValue &getOperand(unsigned i) const;
inline uint64_t getConstantOperandVal(unsigned i) const; inline uint64_t getConstantOperandVal(unsigned i) const;
inline bool isTargetMemoryOpcode() const; inline bool isTargetMemoryOpcode() const;
inline bool isTargetOpcode() const; inline bool isTargetOpcode() const;
inline bool isMachineOpcode() const; inline bool isMachineOpcode() const;
inline unsigned getMachineOpcode() const; inline unsigned getMachineOpcode() const;
inline const DebugLoc getDebugLoc() const; inline const DebugLoc getDebugLoc() const;
inline void dump() const;
inline void dumpr() const;
/// reachesChainWithoutSideEffects - Return true if this operand (which m ust /// reachesChainWithoutSideEffects - Return true if this operand (which m ust
/// be a chain) reaches the specified operand without crossing any /// be a chain) reaches the specified operand without crossing any
/// side-effecting instructions. In practice, this looks through token /// side-effecting instructions. In practice, this looks through token
/// factors and non-volatile loads. In order to remain efficient, this o nly /// factors and non-volatile loads. In order to remain efficient, this o nly
/// looks a couple of nodes in, it does not do an exhaustive search. /// looks a couple of nodes in, it does not do an exhaustive search.
bool reachesChainWithoutSideEffects(SDValue Dest, bool reachesChainWithoutSideEffects(SDValue Dest,
unsigned Depth = 2) const; unsigned Depth = 2) const;
/// use_empty - Return true if there are no nodes using value ResNo /// use_empty - Return true if there are no nodes using value ResNo
skipping to change at line 211 skipping to change at line 217
/// ///
class SDUse { class SDUse {
/// Val - The value being used. /// Val - The value being used.
SDValue Val; SDValue Val;
/// User - The user of this value. /// User - The user of this value.
SDNode *User; SDNode *User;
/// Prev, Next - Pointers to the uses list of the SDNode referred by /// Prev, Next - Pointers to the uses list of the SDNode referred by
/// this operand. /// this operand.
SDUse **Prev, *Next; SDUse **Prev, *Next;
SDUse(const SDUse &U); // Do not implement SDUse(const SDUse &U) LLVM_DELETED_FUNCTION;
void operator=(const SDUse &U); // Do not implement void operator=(const SDUse &U) LLVM_DELETED_FUNCTION;
public: public:
SDUse() : Val(), User(NULL), Prev(NULL), Next(NULL) {} SDUse() : Val(), User(NULL), Prev(NULL), Next(NULL) {}
/// Normally SDUse will just implicitly convert to an SDValue that it hol ds. /// Normally SDUse will just implicitly convert to an SDValue that it hol ds.
operator const SDValue&() const { return Val; } operator const SDValue&() const { return Val; }
/// If implicit conversion to SDValue doesn't work, the get() method retu rns /// If implicit conversion to SDValue doesn't work, the get() method retu rns
/// the SDValue. /// the SDValue.
const SDValue &get() const { return Val; } const SDValue &get() const { return Val; }
skipping to change at line 654 skipping to change at line 660
/// ///
void dumprFull(const SelectionDAG *G = 0) const; void dumprFull(const SelectionDAG *G = 0) const;
/// dumprWithDepth - printrWithDepth to dbgs(). The given /// dumprWithDepth - printrWithDepth to dbgs(). The given
/// SelectionDAG allows target-specific nodes to be printed in /// SelectionDAG allows target-specific nodes to be printed in
/// human-readable form. Unlike dumpr, this will print children /// human-readable form. Unlike dumpr, this will print children
/// that appear multiple times wherever they are used. /// that appear multiple times wherever they are used.
/// ///
void dumprWithDepth(const SelectionDAG *G = 0, unsigned depth = 100) cons t; void dumprWithDepth(const SelectionDAG *G = 0, unsigned depth = 100) cons t;
static bool classof(const SDNode *) { return true; }
/// Profile - Gather unique data for the node. /// Profile - Gather unique data for the node.
/// ///
void Profile(FoldingSetNodeID &ID) const; void Profile(FoldingSetNodeID &ID) const;
/// addUse - This method should only be used by the SDUse class. /// addUse - This method should only be used by the SDUse class.
/// ///
void addUse(SDUse &U) { U.addToList(&UseList); } void addUse(SDUse &U) { U.addToList(&UseList); }
protected: protected:
static SDVTList getSDVTList(EVT VT) { static SDVTList getSDVTList(EVT VT) {
skipping to change at line 797 skipping to change at line 801
} }
inline bool SDValue::use_empty() const { inline bool SDValue::use_empty() const {
return !Node->hasAnyUseOfValue(ResNo); return !Node->hasAnyUseOfValue(ResNo);
} }
inline bool SDValue::hasOneUse() const { inline bool SDValue::hasOneUse() const {
return Node->hasNUsesOfValue(1, ResNo); return Node->hasNUsesOfValue(1, ResNo);
} }
inline const DebugLoc SDValue::getDebugLoc() const { inline const DebugLoc SDValue::getDebugLoc() const {
return Node->getDebugLoc(); return Node->getDebugLoc();
} }
inline void SDValue::dump() const {
return Node->dump();
}
inline void SDValue::dumpr() const {
return Node->dumpr();
}
// Define inline functions from the SDUse class. // Define inline functions from the SDUse class.
inline void SDUse::set(const SDValue &V) { inline void SDUse::set(const SDValue &V) {
if (Val.getNode()) removeFromList(); if (Val.getNode()) removeFromList();
Val = V; Val = V;
if (V.getNode()) V.getNode()->addUse(*this); if (V.getNode()) V.getNode()->addUse(*this);
} }
inline void SDUse::setInitial(const SDValue &V) { inline void SDUse::setInitial(const SDValue &V) {
Val = V; Val = V;
skipping to change at line 941 skipping to change at line 950
EVT getMemoryVT() const { return MemoryVT; } EVT getMemoryVT() const { return MemoryVT; }
/// getMemOperand - Return a MachineMemOperand object describing the memo ry /// getMemOperand - Return a MachineMemOperand object describing the memo ry
/// reference performed by operation. /// reference performed by operation.
MachineMemOperand *getMemOperand() const { return MMO; } MachineMemOperand *getMemOperand() const { return MMO; }
const MachinePointerInfo &getPointerInfo() const { const MachinePointerInfo &getPointerInfo() const {
return MMO->getPointerInfo(); return MMO->getPointerInfo();
} }
/// getAddressSpace - Return the address space for the associated pointer
unsigned getAddressSpace() const {
return getPointerInfo().getAddrSpace();
}
/// refineAlignment - Update this MemSDNode's MachineMemOperand informati on /// refineAlignment - Update this MemSDNode's MachineMemOperand informati on
/// to reflect the alignment of NewMMO, if it has a greater alignment. /// to reflect the alignment of NewMMO, if it has a greater alignment.
/// This must only be used when the new alignment applies to all users of /// This must only be used when the new alignment applies to all users of
/// this MachineMemOperand. /// this MachineMemOperand.
void refineAlignment(const MachineMemOperand *NewMMO) { void refineAlignment(const MachineMemOperand *NewMMO) {
MMO->refineAlignment(NewMMO); MMO->refineAlignment(NewMMO);
} }
const SDValue &getChain() const { return getOperand(0); } const SDValue &getChain() const { return getOperand(0); }
const SDValue &getBasePtr() const { const SDValue &getBasePtr() const {
return getOperand(getOpcode() == ISD::STORE ? 2 : 1); return getOperand(getOpcode() == ISD::STORE ? 2 : 1);
} }
// Methods to support isa and dyn_cast // Methods to support isa and dyn_cast
static bool classof(const MemSDNode *) { return true; }
static bool classof(const SDNode *N) { static bool classof(const SDNode *N) {
// For some targets, we lower some target intrinsics to a MemIntrinsicN ode // For some targets, we lower some target intrinsics to a MemIntrinsicN ode
// with either an intrinsic or a target opcode. // with either an intrinsic or a target opcode.
return N->getOpcode() == ISD::LOAD || return N->getOpcode() == ISD::LOAD ||
N->getOpcode() == ISD::STORE || N->getOpcode() == ISD::STORE ||
N->getOpcode() == ISD::PREFETCH || N->getOpcode() == ISD::PREFETCH ||
N->getOpcode() == ISD::ATOMIC_CMP_SWAP || N->getOpcode() == ISD::ATOMIC_CMP_SWAP ||
N->getOpcode() == ISD::ATOMIC_SWAP || N->getOpcode() == ISD::ATOMIC_SWAP ||
N->getOpcode() == ISD::ATOMIC_LOAD_ADD || N->getOpcode() == ISD::ATOMIC_LOAD_ADD ||
N->getOpcode() == ISD::ATOMIC_LOAD_SUB || N->getOpcode() == ISD::ATOMIC_LOAD_SUB ||
skipping to change at line 995 skipping to change at line 1008
void InitAtomic(AtomicOrdering Ordering, SynchronizationScope SynchScope) { void InitAtomic(AtomicOrdering Ordering, SynchronizationScope SynchScope) {
// This must match encodeMemSDNodeFlags() in SelectionDAG.cpp. // This must match encodeMemSDNodeFlags() in SelectionDAG.cpp.
assert((Ordering & 15) == Ordering && assert((Ordering & 15) == Ordering &&
"Ordering may not require more than 4 bits!"); "Ordering may not require more than 4 bits!");
assert((SynchScope & 1) == SynchScope && assert((SynchScope & 1) == SynchScope &&
"SynchScope may not require more than 1 bit!"); "SynchScope may not require more than 1 bit!");
SubclassData |= Ordering << 8; SubclassData |= Ordering << 8;
SubclassData |= SynchScope << 12; SubclassData |= SynchScope << 12;
assert(getOrdering() == Ordering && "Ordering encoding error!"); assert(getOrdering() == Ordering && "Ordering encoding error!");
assert(getSynchScope() == SynchScope && "Synch-scope encoding error!"); assert(getSynchScope() == SynchScope && "Synch-scope encoding error!");
assert((readMem() || getOrdering() <= Monotonic) &&
"Acquire/Release MachineMemOperand must be a load!");
assert((writeMem() || getOrdering() <= Monotonic) &&
"Acquire/Release MachineMemOperand must be a store!");
} }
public: public:
// Opc: opcode for atomic // Opc: opcode for atomic
// VTL: value type list // VTL: value type list
// Chain: memory chain for operaand // Chain: memory chain for operaand
// Ptr: address to update as a SDValue // Ptr: address to update as a SDValue
// Cmp: compare value // Cmp: compare value
// Swp: swap value // Swp: swap value
// SrcVal: address to update as a Value (used for MemOperand) // SrcVal: address to update as a Value (used for MemOperand)
skipping to change at line 1045 skipping to change at line 1053
const SDValue &getBasePtr() const { return getOperand(1); } const SDValue &getBasePtr() const { return getOperand(1); }
const SDValue &getVal() const { return getOperand(2); } const SDValue &getVal() const { return getOperand(2); }
bool isCompareAndSwap() const { bool isCompareAndSwap() const {
unsigned Op = getOpcode(); unsigned Op = getOpcode();
return Op == ISD::ATOMIC_CMP_SWAP; return Op == ISD::ATOMIC_CMP_SWAP;
} }
// Methods to support isa and dyn_cast // Methods to support isa and dyn_cast
static bool classof(const AtomicSDNode *) { return true; }
static bool classof(const SDNode *N) { static bool classof(const SDNode *N) {
return N->getOpcode() == ISD::ATOMIC_CMP_SWAP || return N->getOpcode() == ISD::ATOMIC_CMP_SWAP ||
N->getOpcode() == ISD::ATOMIC_SWAP || N->getOpcode() == ISD::ATOMIC_SWAP ||
N->getOpcode() == ISD::ATOMIC_LOAD_ADD || N->getOpcode() == ISD::ATOMIC_LOAD_ADD ||
N->getOpcode() == ISD::ATOMIC_LOAD_SUB || N->getOpcode() == ISD::ATOMIC_LOAD_SUB ||
N->getOpcode() == ISD::ATOMIC_LOAD_AND || N->getOpcode() == ISD::ATOMIC_LOAD_AND ||
N->getOpcode() == ISD::ATOMIC_LOAD_OR || N->getOpcode() == ISD::ATOMIC_LOAD_OR ||
N->getOpcode() == ISD::ATOMIC_LOAD_XOR || N->getOpcode() == ISD::ATOMIC_LOAD_XOR ||
N->getOpcode() == ISD::ATOMIC_LOAD_NAND || N->getOpcode() == ISD::ATOMIC_LOAD_NAND ||
N->getOpcode() == ISD::ATOMIC_LOAD_MIN || N->getOpcode() == ISD::ATOMIC_LOAD_MIN ||
skipping to change at line 1077 skipping to change at line 1084
/// with a value not less than FIRST_TARGET_MEMORY_OPCODE. /// with a value not less than FIRST_TARGET_MEMORY_OPCODE.
class MemIntrinsicSDNode : public MemSDNode { class MemIntrinsicSDNode : public MemSDNode {
public: public:
MemIntrinsicSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, MemIntrinsicSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs,
const SDValue *Ops, unsigned NumOps, const SDValue *Ops, unsigned NumOps,
EVT MemoryVT, MachineMemOperand *MMO) EVT MemoryVT, MachineMemOperand *MMO)
: MemSDNode(Opc, dl, VTs, Ops, NumOps, MemoryVT, MMO) { : MemSDNode(Opc, dl, VTs, Ops, NumOps, MemoryVT, MMO) {
} }
// Methods to support isa and dyn_cast // Methods to support isa and dyn_cast
static bool classof(const MemIntrinsicSDNode *) { return true; }
static bool classof(const SDNode *N) { static bool classof(const SDNode *N) {
// We lower some target intrinsics to their target opcode // We lower some target intrinsics to their target opcode
// early a node with a target opcode can be of this class // early a node with a target opcode can be of this class
return N->getOpcode() == ISD::INTRINSIC_W_CHAIN || return N->getOpcode() == ISD::INTRINSIC_W_CHAIN ||
N->getOpcode() == ISD::INTRINSIC_VOID || N->getOpcode() == ISD::INTRINSIC_VOID ||
N->getOpcode() == ISD::PREFETCH || N->getOpcode() == ISD::PREFETCH ||
N->isTargetMemoryOpcode(); N->isTargetMemoryOpcode();
} }
}; };
skipping to change at line 1132 skipping to change at line 1138
assert(isSplat() && "Cannot get splat index for non-splat!"); assert(isSplat() && "Cannot get splat index for non-splat!");
EVT VT = getValueType(0); EVT VT = getValueType(0);
for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) { for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
if (Mask[i] != -1) if (Mask[i] != -1)
return Mask[i]; return Mask[i];
} }
return -1; return -1;
} }
static bool isSplatMask(const int *Mask, EVT VT); static bool isSplatMask(const int *Mask, EVT VT);
static bool classof(const ShuffleVectorSDNode *) { return true; }
static bool classof(const SDNode *N) { static bool classof(const SDNode *N) {
return N->getOpcode() == ISD::VECTOR_SHUFFLE; return N->getOpcode() == ISD::VECTOR_SHUFFLE;
} }
}; };
class ConstantSDNode : public SDNode { class ConstantSDNode : public SDNode {
const ConstantInt *Value; const ConstantInt *Value;
friend class SelectionDAG; friend class SelectionDAG;
ConstantSDNode(bool isTarget, const ConstantInt *val, EVT VT) ConstantSDNode(bool isTarget, const ConstantInt *val, EVT VT)
: SDNode(isTarget ? ISD::TargetConstant : ISD::Constant, : SDNode(isTarget ? ISD::TargetConstant : ISD::Constant,
skipping to change at line 1156 skipping to change at line 1161
const ConstantInt *getConstantIntValue() const { return Value; } const ConstantInt *getConstantIntValue() const { return Value; }
const APInt &getAPIntValue() const { return Value->getValue(); } const APInt &getAPIntValue() const { return Value->getValue(); }
uint64_t getZExtValue() const { return Value->getZExtValue(); } uint64_t getZExtValue() const { return Value->getZExtValue(); }
int64_t getSExtValue() const { return Value->getSExtValue(); } int64_t getSExtValue() const { return Value->getSExtValue(); }
bool isOne() const { return Value->isOne(); } bool isOne() const { return Value->isOne(); }
bool isNullValue() const { return Value->isNullValue(); } bool isNullValue() const { return Value->isNullValue(); }
bool isAllOnesValue() const { return Value->isAllOnesValue(); } bool isAllOnesValue() const { return Value->isAllOnesValue(); }
static bool classof(const ConstantSDNode *) { return true; }
static bool classof(const SDNode *N) { static bool classof(const SDNode *N) {
return N->getOpcode() == ISD::Constant || return N->getOpcode() == ISD::Constant ||
N->getOpcode() == ISD::TargetConstant; N->getOpcode() == ISD::TargetConstant;
} }
}; };
class ConstantFPSDNode : public SDNode { class ConstantFPSDNode : public SDNode {
const ConstantFP *Value; const ConstantFP *Value;
friend class SelectionDAG; friend class SelectionDAG;
ConstantFPSDNode(bool isTarget, const ConstantFP *val, EVT VT) ConstantFPSDNode(bool isTarget, const ConstantFP *val, EVT VT)
skipping to change at line 1191 skipping to change at line 1195
/// isExactlyValue - We don't rely on operator== working on double values , as /// isExactlyValue - We don't rely on operator== working on double values , as
/// it returns true for things that are clearly not equal, like -0.0 and 0.0. /// it returns true for things that are clearly not equal, like -0.0 and 0.0.
/// As such, this method can be used to do an exact bit-for-bit compariso n of /// As such, this method can be used to do an exact bit-for-bit compariso n of
/// two floating point values. /// two floating point values.
/// We leave the version with the double argument here because it's just so /// We leave the version with the double argument here because it's just so
/// convenient to write "2.0" and the like. Without this function we'd /// convenient to write "2.0" and the like. Without this function we'd
/// have to duplicate its logic everywhere it's called. /// have to duplicate its logic everywhere it's called.
bool isExactlyValue(double V) const { bool isExactlyValue(double V) const {
bool ignored; bool ignored;
// convert is not supported on this type
if (&Value->getValueAPF().getSemantics() == &APFloat::PPCDoubleDouble)
return false;
APFloat Tmp(V); APFloat Tmp(V);
Tmp.convert(Value->getValueAPF().getSemantics(), Tmp.convert(Value->getValueAPF().getSemantics(),
APFloat::rmNearestTiesToEven, &ignored); APFloat::rmNearestTiesToEven, &ignored);
return isExactlyValue(Tmp); return isExactlyValue(Tmp);
} }
bool isExactlyValue(const APFloat& V) const; bool isExactlyValue(const APFloat& V) const;
static bool isValueValidForType(EVT VT, const APFloat& Val); static bool isValueValidForType(EVT VT, const APFloat& Val);
static bool classof(const ConstantFPSDNode *) { return true; }
static bool classof(const SDNode *N) { static bool classof(const SDNode *N) {
return N->getOpcode() == ISD::ConstantFP || return N->getOpcode() == ISD::ConstantFP ||
N->getOpcode() == ISD::TargetConstantFP; N->getOpcode() == ISD::TargetConstantFP;
} }
}; };
class GlobalAddressSDNode : public SDNode { class GlobalAddressSDNode : public SDNode {
const GlobalValue *TheGlobal; const GlobalValue *TheGlobal;
int64_t Offset; int64_t Offset;
unsigned char TargetFlags; unsigned char TargetFlags;
skipping to change at line 1225 skipping to change at line 1225
GlobalAddressSDNode(unsigned Opc, DebugLoc DL, const GlobalValue *GA, EVT VT, GlobalAddressSDNode(unsigned Opc, DebugLoc DL, const GlobalValue *GA, EVT VT,
int64_t o, unsigned char TargetFlags); int64_t o, unsigned char TargetFlags);
public: public:
const GlobalValue *getGlobal() const { return TheGlobal; } const GlobalValue *getGlobal() const { return TheGlobal; }
int64_t getOffset() const { return Offset; } int64_t getOffset() const { return Offset; }
unsigned char getTargetFlags() const { return TargetFlags; } unsigned char getTargetFlags() const { return TargetFlags; }
// Return the address space this GlobalAddress belongs to. // Return the address space this GlobalAddress belongs to.
unsigned getAddressSpace() const; unsigned getAddressSpace() const;
static bool classof(const GlobalAddressSDNode *) { return true; }
static bool classof(const SDNode *N) { static bool classof(const SDNode *N) {
return N->getOpcode() == ISD::GlobalAddress || return N->getOpcode() == ISD::GlobalAddress ||
N->getOpcode() == ISD::TargetGlobalAddress || N->getOpcode() == ISD::TargetGlobalAddress ||
N->getOpcode() == ISD::GlobalTLSAddress || N->getOpcode() == ISD::GlobalTLSAddress ||
N->getOpcode() == ISD::TargetGlobalTLSAddress; N->getOpcode() == ISD::TargetGlobalTLSAddress;
} }
}; };
class FrameIndexSDNode : public SDNode { class FrameIndexSDNode : public SDNode {
int FI; int FI;
friend class SelectionDAG; friend class SelectionDAG;
FrameIndexSDNode(int fi, EVT VT, bool isTarg) FrameIndexSDNode(int fi, EVT VT, bool isTarg)
: SDNode(isTarg ? ISD::TargetFrameIndex : ISD::FrameIndex, : SDNode(isTarg ? ISD::TargetFrameIndex : ISD::FrameIndex,
DebugLoc(), getSDVTList(VT)), FI(fi) { DebugLoc(), getSDVTList(VT)), FI(fi) {
} }
public: public:
int getIndex() const { return FI; } int getIndex() const { return FI; }
static bool classof(const FrameIndexSDNode *) { return true; }
static bool classof(const SDNode *N) { static bool classof(const SDNode *N) {
return N->getOpcode() == ISD::FrameIndex || return N->getOpcode() == ISD::FrameIndex ||
N->getOpcode() == ISD::TargetFrameIndex; N->getOpcode() == ISD::TargetFrameIndex;
} }
}; };
class JumpTableSDNode : public SDNode { class JumpTableSDNode : public SDNode {
int JTI; int JTI;
unsigned char TargetFlags; unsigned char TargetFlags;
friend class SelectionDAG; friend class SelectionDAG;
JumpTableSDNode(int jti, EVT VT, bool isTarg, unsigned char TF) JumpTableSDNode(int jti, EVT VT, bool isTarg, unsigned char TF)
: SDNode(isTarg ? ISD::TargetJumpTable : ISD::JumpTable, : SDNode(isTarg ? ISD::TargetJumpTable : ISD::JumpTable,
DebugLoc(), getSDVTList(VT)), JTI(jti), TargetFlags(TF) { DebugLoc(), getSDVTList(VT)), JTI(jti), TargetFlags(TF) {
} }
public: public:
int getIndex() const { return JTI; } int getIndex() const { return JTI; }
unsigned char getTargetFlags() const { return TargetFlags; } unsigned char getTargetFlags() const { return TargetFlags; }
static bool classof(const JumpTableSDNode *) { return true; }
static bool classof(const SDNode *N) { static bool classof(const SDNode *N) {
return N->getOpcode() == ISD::JumpTable || return N->getOpcode() == ISD::JumpTable ||
N->getOpcode() == ISD::TargetJumpTable; N->getOpcode() == ISD::TargetJumpTable;
} }
}; };
class ConstantPoolSDNode : public SDNode { class ConstantPoolSDNode : public SDNode {
union { union {
const Constant *ConstVal; const Constant *ConstVal;
MachineConstantPoolValue *MachineCPVal; MachineConstantPoolValue *MachineCPVal;
skipping to change at line 1325 skipping to change at line 1322
return Offset & ~(1 << (sizeof(unsigned)*CHAR_BIT-1)); return Offset & ~(1 << (sizeof(unsigned)*CHAR_BIT-1));
} }
// Return the alignment of this constant pool object, which is either 0 ( for // Return the alignment of this constant pool object, which is either 0 ( for
// default alignment) or the desired value. // default alignment) or the desired value.
unsigned getAlignment() const { return Alignment; } unsigned getAlignment() const { return Alignment; }
unsigned char getTargetFlags() const { return TargetFlags; } unsigned char getTargetFlags() const { return TargetFlags; }
Type *getType() const; Type *getType() const;
static bool classof(const ConstantPoolSDNode *) { return true; }
static bool classof(const SDNode *N) { static bool classof(const SDNode *N) {
return N->getOpcode() == ISD::ConstantPool || return N->getOpcode() == ISD::ConstantPool ||
N->getOpcode() == ISD::TargetConstantPool; N->getOpcode() == ISD::TargetConstantPool;
} }
}; };
/// Completely target-dependent object reference.
class TargetIndexSDNode : public SDNode {
unsigned char TargetFlags;
int Index;
int64_t Offset;
friend class SelectionDAG;
public:
TargetIndexSDNode(int Idx, EVT VT, int64_t Ofs, unsigned char TF)
: SDNode(ISD::TargetIndex, DebugLoc(), getSDVTList(VT)),
TargetFlags(TF), Index(Idx), Offset(Ofs) {}
public:
unsigned char getTargetFlags() const { return TargetFlags; }
int getIndex() const { return Index; }
int64_t getOffset() const { return Offset; }
static bool classof(const SDNode *N) {
return N->getOpcode() == ISD::TargetIndex;
}
};
class BasicBlockSDNode : public SDNode { class BasicBlockSDNode : public SDNode {
MachineBasicBlock *MBB; MachineBasicBlock *MBB;
friend class SelectionDAG; friend class SelectionDAG;
/// Debug info is meaningful and potentially useful here, but we create /// Debug info is meaningful and potentially useful here, but we create
/// blocks out of order when they're jumped to, which makes it a bit /// blocks out of order when they're jumped to, which makes it a bit
/// harder. Let's see if we need it first. /// harder. Let's see if we need it first.
explicit BasicBlockSDNode(MachineBasicBlock *mbb) explicit BasicBlockSDNode(MachineBasicBlock *mbb)
: SDNode(ISD::BasicBlock, DebugLoc(), getSDVTList(MVT::Other)), MBB(mbb ) { : SDNode(ISD::BasicBlock, DebugLoc(), getSDVTList(MVT::Other)), MBB(mbb ) {
} }
public: public:
MachineBasicBlock *getBasicBlock() const { return MBB; } MachineBasicBlock *getBasicBlock() const { return MBB; }
static bool classof(const BasicBlockSDNode *) { return true; }
static bool classof(const SDNode *N) { static bool classof(const SDNode *N) {
return N->getOpcode() == ISD::BasicBlock; return N->getOpcode() == ISD::BasicBlock;
} }
}; };
/// BuildVectorSDNode - A "pseudo-class" with methods for operating on /// BuildVectorSDNode - A "pseudo-class" with methods for operating on
/// BUILD_VECTORs. /// BUILD_VECTORs.
class BuildVectorSDNode : public SDNode { class BuildVectorSDNode : public SDNode {
// These are constructed as SDNodes and then cast to BuildVectorSDNodes. // These are constructed as SDNodes and then cast to BuildVectorSDNodes.
explicit BuildVectorSDNode(); // Do not implement explicit BuildVectorSDNode() LLVM_DELETED_FUNCTION;
public: public:
/// isConstantSplat - Check if this is a constant splat, and if so, find the /// isConstantSplat - Check if this is a constant splat, and if so, find the
/// smallest element size that splats the vector. If MinSplatBits is /// smallest element size that splats the vector. If MinSplatBits is
/// nonzero, the element size must be at least that large. Note that the /// nonzero, the element size must be at least that large. Note that the
/// splat element may be the entire vector (i.e., a one element vector). /// splat element may be the entire vector (i.e., a one element vector).
/// Returns the splat element value in SplatValue. Any undefined bits in /// Returns the splat element value in SplatValue. Any undefined bits in
/// that value are zero, and the corresponding bits in the SplatUndef mas k /// that value are zero, and the corresponding bits in the SplatUndef mas k
/// are set. The SplatBitSize value is set to the splat element size in /// are set. The SplatBitSize value is set to the splat element size in
/// bits. HasAnyUndefs is set to true if any bits in the vector are /// bits. HasAnyUndefs is set to true if any bits in the vector are
/// undefined. isBigEndian describes the endianness of the target. /// undefined. isBigEndian describes the endianness of the target.
bool isConstantSplat(APInt &SplatValue, APInt &SplatUndef, bool isConstantSplat(APInt &SplatValue, APInt &SplatUndef,
unsigned &SplatBitSize, bool &HasAnyUndefs, unsigned &SplatBitSize, bool &HasAnyUndefs,
unsigned MinSplatBits = 0, bool isBigEndian = false) ; unsigned MinSplatBits = 0, bool isBigEndian = false) ;
static inline bool classof(const BuildVectorSDNode *) { return true; }
static inline bool classof(const SDNode *N) { static inline bool classof(const SDNode *N) {
return N->getOpcode() == ISD::BUILD_VECTOR; return N->getOpcode() == ISD::BUILD_VECTOR;
} }
}; };
/// SrcValueSDNode - An SDNode that holds an arbitrary LLVM IR Value. This is /// SrcValueSDNode - An SDNode that holds an arbitrary LLVM IR Value. This is
/// used when the SelectionDAG needs to make a simple reference to somethin g /// used when the SelectionDAG needs to make a simple reference to somethin g
/// in the LLVM IR representation. /// in the LLVM IR representation.
/// ///
class SrcValueSDNode : public SDNode { class SrcValueSDNode : public SDNode {
const Value *V; const Value *V;
friend class SelectionDAG; friend class SelectionDAG;
/// Create a SrcValue for a general value. /// Create a SrcValue for a general value.
explicit SrcValueSDNode(const Value *v) explicit SrcValueSDNode(const Value *v)
: SDNode(ISD::SRCVALUE, DebugLoc(), getSDVTList(MVT::Other)), V(v) {} : SDNode(ISD::SRCVALUE, DebugLoc(), getSDVTList(MVT::Other)), V(v) {}
public: public:
/// getValue - return the contained Value. /// getValue - return the contained Value.
const Value *getValue() const { return V; } const Value *getValue() const { return V; }
static bool classof(const SrcValueSDNode *) { return true; }
static bool classof(const SDNode *N) { static bool classof(const SDNode *N) {
return N->getOpcode() == ISD::SRCVALUE; return N->getOpcode() == ISD::SRCVALUE;
} }
}; };
class MDNodeSDNode : public SDNode { class MDNodeSDNode : public SDNode {
const MDNode *MD; const MDNode *MD;
friend class SelectionDAG; friend class SelectionDAG;
explicit MDNodeSDNode(const MDNode *md) explicit MDNodeSDNode(const MDNode *md)
: SDNode(ISD::MDNODE_SDNODE, DebugLoc(), getSDVTList(MVT::Other)), MD(md) {} : SDNode(ISD::MDNODE_SDNODE, DebugLoc(), getSDVTList(MVT::Other)), MD(md) {}
public: public:
const MDNode *getMD() const { return MD; } const MDNode *getMD() const { return MD; }
static bool classof(const MDNodeSDNode *) { return true; }
static bool classof(const SDNode *N) { static bool classof(const SDNode *N) {
return N->getOpcode() == ISD::MDNODE_SDNODE; return N->getOpcode() == ISD::MDNODE_SDNODE;
} }
}; };
class RegisterSDNode : public SDNode { class RegisterSDNode : public SDNode {
unsigned Reg; unsigned Reg;
friend class SelectionDAG; friend class SelectionDAG;
RegisterSDNode(unsigned reg, EVT VT) RegisterSDNode(unsigned reg, EVT VT)
: SDNode(ISD::Register, DebugLoc(), getSDVTList(VT)), Reg(reg) { : SDNode(ISD::Register, DebugLoc(), getSDVTList(VT)), Reg(reg) {
} }
public: public:
unsigned getReg() const { return Reg; } unsigned getReg() const { return Reg; }
static bool classof(const RegisterSDNode *) { return true; }
static bool classof(const SDNode *N) { static bool classof(const SDNode *N) {
return N->getOpcode() == ISD::Register; return N->getOpcode() == ISD::Register;
} }
}; };
class RegisterMaskSDNode : public SDNode { class RegisterMaskSDNode : public SDNode {
// The memory for RegMask is not owned by the node. // The memory for RegMask is not owned by the node.
const uint32_t *RegMask; const uint32_t *RegMask;
friend class SelectionDAG; friend class SelectionDAG;
RegisterMaskSDNode(const uint32_t *mask) RegisterMaskSDNode(const uint32_t *mask)
: SDNode(ISD::RegisterMask, DebugLoc(), getSDVTList(MVT::Untyped)), : SDNode(ISD::RegisterMask, DebugLoc(), getSDVTList(MVT::Untyped)),
RegMask(mask) {} RegMask(mask) {}
public: public:
const uint32_t *getRegMask() const { return RegMask; } const uint32_t *getRegMask() const { return RegMask; }
static bool classof(const RegisterMaskSDNode *) { return true; }
static bool classof(const SDNode *N) { static bool classof(const SDNode *N) {
return N->getOpcode() == ISD::RegisterMask; return N->getOpcode() == ISD::RegisterMask;
} }
}; };
class BlockAddressSDNode : public SDNode { class BlockAddressSDNode : public SDNode {
const BlockAddress *BA; const BlockAddress *BA;
int64_t Offset;
unsigned char TargetFlags; unsigned char TargetFlags;
friend class SelectionDAG; friend class SelectionDAG;
BlockAddressSDNode(unsigned NodeTy, EVT VT, const BlockAddress *ba, BlockAddressSDNode(unsigned NodeTy, EVT VT, const BlockAddress *ba,
unsigned char Flags) int64_t o, unsigned char Flags)
: SDNode(NodeTy, DebugLoc(), getSDVTList(VT)), : SDNode(NodeTy, DebugLoc(), getSDVTList(VT)),
BA(ba), TargetFlags(Flags) { BA(ba), Offset(o), TargetFlags(Flags) {
} }
public: public:
const BlockAddress *getBlockAddress() const { return BA; } const BlockAddress *getBlockAddress() const { return BA; }
int64_t getOffset() const { return Offset; }
unsigned char getTargetFlags() const { return TargetFlags; } unsigned char getTargetFlags() const { return TargetFlags; }
static bool classof(const BlockAddressSDNode *) { return true; }
static bool classof(const SDNode *N) { static bool classof(const SDNode *N) {
return N->getOpcode() == ISD::BlockAddress || return N->getOpcode() == ISD::BlockAddress ||
N->getOpcode() == ISD::TargetBlockAddress; N->getOpcode() == ISD::TargetBlockAddress;
} }
}; };
class EHLabelSDNode : public SDNode { class EHLabelSDNode : public SDNode {
SDUse Chain; SDUse Chain;
MCSymbol *Label; MCSymbol *Label;
friend class SelectionDAG; friend class SelectionDAG;
EHLabelSDNode(DebugLoc dl, SDValue ch, MCSymbol *L) EHLabelSDNode(DebugLoc dl, SDValue ch, MCSymbol *L)
: SDNode(ISD::EH_LABEL, dl, getSDVTList(MVT::Other)), Label(L) { : SDNode(ISD::EH_LABEL, dl, getSDVTList(MVT::Other)), Label(L) {
InitOperands(&Chain, ch); InitOperands(&Chain, ch);
} }
public: public:
MCSymbol *getLabel() const { return Label; } MCSymbol *getLabel() const { return Label; }
static bool classof(const EHLabelSDNode *) { return true; }
static bool classof(const SDNode *N) { static bool classof(const SDNode *N) {
return N->getOpcode() == ISD::EH_LABEL; return N->getOpcode() == ISD::EH_LABEL;
} }
}; };
class ExternalSymbolSDNode : public SDNode { class ExternalSymbolSDNode : public SDNode {
const char *Symbol; const char *Symbol;
unsigned char TargetFlags; unsigned char TargetFlags;
friend class SelectionDAG; friend class SelectionDAG;
ExternalSymbolSDNode(bool isTarget, const char *Sym, unsigned char TF, EV T VT) ExternalSymbolSDNode(bool isTarget, const char *Sym, unsigned char TF, EV T VT)
: SDNode(isTarget ? ISD::TargetExternalSymbol : ISD::ExternalSymbol, : SDNode(isTarget ? ISD::TargetExternalSymbol : ISD::ExternalSymbol,
DebugLoc(), getSDVTList(VT)), Symbol(Sym), TargetFlags(TF) { DebugLoc(), getSDVTList(VT)), Symbol(Sym), TargetFlags(TF) {
} }
public: public:
const char *getSymbol() const { return Symbol; } const char *getSymbol() const { return Symbol; }
unsigned char getTargetFlags() const { return TargetFlags; } unsigned char getTargetFlags() const { return TargetFlags; }
static bool classof(const ExternalSymbolSDNode *) { return true; }
static bool classof(const SDNode *N) { static bool classof(const SDNode *N) {
return N->getOpcode() == ISD::ExternalSymbol || return N->getOpcode() == ISD::ExternalSymbol ||
N->getOpcode() == ISD::TargetExternalSymbol; N->getOpcode() == ISD::TargetExternalSymbol;
} }
}; };
class CondCodeSDNode : public SDNode { class CondCodeSDNode : public SDNode {
ISD::CondCode Condition; ISD::CondCode Condition;
friend class SelectionDAG; friend class SelectionDAG;
explicit CondCodeSDNode(ISD::CondCode Cond) explicit CondCodeSDNode(ISD::CondCode Cond)
: SDNode(ISD::CONDCODE, DebugLoc(), getSDVTList(MVT::Other)), : SDNode(ISD::CONDCODE, DebugLoc(), getSDVTList(MVT::Other)),
Condition(Cond) { Condition(Cond) {
} }
public: public:
ISD::CondCode get() const { return Condition; } ISD::CondCode get() const { return Condition; }
static bool classof(const CondCodeSDNode *) { return true; }
static bool classof(const SDNode *N) { static bool classof(const SDNode *N) {
return N->getOpcode() == ISD::CONDCODE; return N->getOpcode() == ISD::CONDCODE;
} }
}; };
/// CvtRndSatSDNode - NOTE: avoid using this node as this may disappear in the /// CvtRndSatSDNode - NOTE: avoid using this node as this may disappear in the
/// future and most targets don't support it. /// future and most targets don't support it.
class CvtRndSatSDNode : public SDNode { class CvtRndSatSDNode : public SDNode {
ISD::CvtCode CvtCode; ISD::CvtCode CvtCode;
friend class SelectionDAG; friend class SelectionDAG;
explicit CvtRndSatSDNode(EVT VT, DebugLoc dl, const SDValue *Ops, explicit CvtRndSatSDNode(EVT VT, DebugLoc dl, const SDValue *Ops,
unsigned NumOps, ISD::CvtCode Code) unsigned NumOps, ISD::CvtCode Code)
: SDNode(ISD::CONVERT_RNDSAT, dl, getSDVTList(VT), Ops, NumOps), : SDNode(ISD::CONVERT_RNDSAT, dl, getSDVTList(VT), Ops, NumOps),
CvtCode(Code) { CvtCode(Code) {
assert(NumOps == 5 && "wrong number of operations"); assert(NumOps == 5 && "wrong number of operations");
} }
public: public:
ISD::CvtCode getCvtCode() const { return CvtCode; } ISD::CvtCode getCvtCode() const { return CvtCode; }
static bool classof(const CvtRndSatSDNode *) { return true; }
static bool classof(const SDNode *N) { static bool classof(const SDNode *N) {
return N->getOpcode() == ISD::CONVERT_RNDSAT; return N->getOpcode() == ISD::CONVERT_RNDSAT;
} }
}; };
/// VTSDNode - This class is used to represent EVT's, which are used /// VTSDNode - This class is used to represent EVT's, which are used
/// to parameterize some operations. /// to parameterize some operations.
class VTSDNode : public SDNode { class VTSDNode : public SDNode {
EVT ValueType; EVT ValueType;
friend class SelectionDAG; friend class SelectionDAG;
explicit VTSDNode(EVT VT) explicit VTSDNode(EVT VT)
: SDNode(ISD::VALUETYPE, DebugLoc(), getSDVTList(MVT::Other)), : SDNode(ISD::VALUETYPE, DebugLoc(), getSDVTList(MVT::Other)),
ValueType(VT) { ValueType(VT) {
} }
public: public:
EVT getVT() const { return ValueType; } EVT getVT() const { return ValueType; }
static bool classof(const VTSDNode *) { return true; }
static bool classof(const SDNode *N) { static bool classof(const SDNode *N) {
return N->getOpcode() == ISD::VALUETYPE; return N->getOpcode() == ISD::VALUETYPE;
} }
}; };
/// LSBaseSDNode - Base class for LoadSDNode and StoreSDNode /// LSBaseSDNode - Base class for LoadSDNode and StoreSDNode
/// ///
class LSBaseSDNode : public MemSDNode { class LSBaseSDNode : public MemSDNode {
//! Operand array for load and store //! Operand array for load and store
/*! /*!
skipping to change at line 1597 skipping to change at line 1605
ISD::MemIndexedMode getAddressingMode() const { ISD::MemIndexedMode getAddressingMode() const {
return ISD::MemIndexedMode((SubclassData >> 2) & 7); return ISD::MemIndexedMode((SubclassData >> 2) & 7);
} }
/// isIndexed - Return true if this is a pre/post inc/dec load/store. /// isIndexed - Return true if this is a pre/post inc/dec load/store.
bool isIndexed() const { return getAddressingMode() != ISD::UNINDEXED; } bool isIndexed() const { return getAddressingMode() != ISD::UNINDEXED; }
/// isUnindexed - Return true if this is NOT a pre/post inc/dec load/stor e. /// isUnindexed - Return true if this is NOT a pre/post inc/dec load/stor e.
bool isUnindexed() const { return getAddressingMode() == ISD::UNINDEXED; } bool isUnindexed() const { return getAddressingMode() == ISD::UNINDEXED; }
static bool classof(const LSBaseSDNode *) { return true; }
static bool classof(const SDNode *N) { static bool classof(const SDNode *N) {
return N->getOpcode() == ISD::LOAD || return N->getOpcode() == ISD::LOAD ||
N->getOpcode() == ISD::STORE; N->getOpcode() == ISD::STORE;
} }
}; };
/// LoadSDNode - This class is used to represent ISD::LOAD nodes. /// LoadSDNode - This class is used to represent ISD::LOAD nodes.
/// ///
class LoadSDNode : public LSBaseSDNode { class LoadSDNode : public LSBaseSDNode {
friend class SelectionDAG; friend class SelectionDAG;
skipping to change at line 1629 skipping to change at line 1636
/// getExtensionType - Return whether this is a plain node, /// getExtensionType - Return whether this is a plain node,
/// or one of the varieties of value-extending loads. /// or one of the varieties of value-extending loads.
ISD::LoadExtType getExtensionType() const { ISD::LoadExtType getExtensionType() const {
return ISD::LoadExtType(SubclassData & 3); return ISD::LoadExtType(SubclassData & 3);
} }
const SDValue &getBasePtr() const { return getOperand(1); } const SDValue &getBasePtr() const { return getOperand(1); }
const SDValue &getOffset() const { return getOperand(2); } const SDValue &getOffset() const { return getOperand(2); }
static bool classof(const LoadSDNode *) { return true; }
static bool classof(const SDNode *N) { static bool classof(const SDNode *N) {
return N->getOpcode() == ISD::LOAD; return N->getOpcode() == ISD::LOAD;
} }
}; };
/// StoreSDNode - This class is used to represent ISD::STORE nodes. /// StoreSDNode - This class is used to represent ISD::STORE nodes.
/// ///
class StoreSDNode : public LSBaseSDNode { class StoreSDNode : public LSBaseSDNode {
friend class SelectionDAG; friend class SelectionDAG;
StoreSDNode(SDValue *ChainValuePtrOff, DebugLoc dl, SDVTList VTs, StoreSDNode(SDValue *ChainValuePtrOff, DebugLoc dl, SDVTList VTs,
skipping to change at line 1660 skipping to change at line 1666
/// isTruncatingStore - Return true if the op does a truncation before st ore. /// isTruncatingStore - Return true if the op does a truncation before st ore.
/// For integers this is the same as doing a TRUNCATE and storing the res ult. /// For integers this is the same as doing a TRUNCATE and storing the res ult.
/// For floats, it is the same as doing an FP_ROUND and storing the resul t. /// For floats, it is the same as doing an FP_ROUND and storing the resul t.
bool isTruncatingStore() const { return SubclassData & 1; } bool isTruncatingStore() const { return SubclassData & 1; }
const SDValue &getValue() const { return getOperand(1); } const SDValue &getValue() const { return getOperand(1); }
const SDValue &getBasePtr() const { return getOperand(2); } const SDValue &getBasePtr() const { return getOperand(2); }
const SDValue &getOffset() const { return getOperand(3); } const SDValue &getOffset() const { return getOperand(3); }
static bool classof(const StoreSDNode *) { return true; }
static bool classof(const SDNode *N) { static bool classof(const SDNode *N) {
return N->getOpcode() == ISD::STORE; return N->getOpcode() == ISD::STORE;
} }
}; };
/// MachineSDNode - An SDNode that represents everything that will be neede d /// MachineSDNode - An SDNode that represents everything that will be neede d
/// to construct a MachineInstr. These nodes are created during the /// to construct a MachineInstr. These nodes are created during the
/// instruction selection proper phase. /// instruction selection proper phase.
/// ///
class MachineSDNode : public SDNode { class MachineSDNode : public SDNode {
skipping to change at line 1701 skipping to change at line 1706
/// setMemRefs - Assign this MachineSDNodes's memory reference descriptor /// setMemRefs - Assign this MachineSDNodes's memory reference descriptor
/// list. This does not transfer ownership. /// list. This does not transfer ownership.
void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd) { void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd) {
for (mmo_iterator MMI = NewMemRefs, MME = NewMemRefsEnd; MMI != MME; ++ MMI) for (mmo_iterator MMI = NewMemRefs, MME = NewMemRefsEnd; MMI != MME; ++ MMI)
assert(*MMI && "Null mem ref detected!"); assert(*MMI && "Null mem ref detected!");
MemRefs = NewMemRefs; MemRefs = NewMemRefs;
MemRefsEnd = NewMemRefsEnd; MemRefsEnd = NewMemRefsEnd;
} }
static bool classof(const MachineSDNode *) { return true; }
static bool classof(const SDNode *N) { static bool classof(const SDNode *N) {
return N->isMachineOpcode(); return N->isMachineOpcode();
} }
}; };
class SDNodeIterator : public std::iterator<std::forward_iterator_tag, class SDNodeIterator : public std::iterator<std::forward_iterator_tag,
SDNode, ptrdiff_t> { SDNode, ptrdiff_t> {
SDNode *Node; const SDNode *Node;
unsigned Operand; unsigned Operand;
SDNodeIterator(SDNode *N, unsigned Op) : Node(N), Operand(Op) {} SDNodeIterator(const SDNode *N, unsigned Op) : Node(N), Operand(Op) {}
public: public:
bool operator==(const SDNodeIterator& x) const { bool operator==(const SDNodeIterator& x) const {
return Operand == x.Operand; return Operand == x.Operand;
} }
bool operator!=(const SDNodeIterator& x) const { return !operator==(x); } bool operator!=(const SDNodeIterator& x) const { return !operator==(x); }
const SDNodeIterator &operator=(const SDNodeIterator &I) { const SDNodeIterator &operator=(const SDNodeIterator &I) {
assert(I.Node == Node && "Cannot assign iterators to two different node s!"); assert(I.Node == Node && "Cannot assign iterators to two different node s!");
Operand = I.Operand; Operand = I.Operand;
return *this; return *this;
skipping to change at line 1743 skipping to change at line 1747
} }
SDNodeIterator operator++(int) { // Postincrement SDNodeIterator operator++(int) { // Postincrement
SDNodeIterator tmp = *this; ++*this; return tmp; SDNodeIterator tmp = *this; ++*this; return tmp;
} }
size_t operator-(SDNodeIterator Other) const { size_t operator-(SDNodeIterator Other) const {
assert(Node == Other.Node && assert(Node == Other.Node &&
"Cannot compare iterators of two different nodes!"); "Cannot compare iterators of two different nodes!");
return Operand - Other.Operand; return Operand - Other.Operand;
} }
static SDNodeIterator begin(SDNode *N) { return SDNodeIterator(N, 0); } static SDNodeIterator begin(const SDNode *N) { return SDNodeIterator(N, 0
static SDNodeIterator end (SDNode *N) { ); }
static SDNodeIterator end (const SDNode *N) {
return SDNodeIterator(N, N->getNumOperands()); return SDNodeIterator(N, N->getNumOperands());
} }
unsigned getOperand() const { return Operand; } unsigned getOperand() const { return Operand; }
const SDNode *getNode() const { return Node; } const SDNode *getNode() const { return Node; }
}; };
template <> struct GraphTraits<SDNode*> { template <> struct GraphTraits<SDNode*> {
typedef SDNode NodeType; typedef SDNode NodeType;
typedef SDNodeIterator ChildIteratorType; typedef SDNodeIterator ChildIteratorType;
 End of changes. 43 change blocks. 
46 lines changed or deleted 51 lines changed or added


 SetVector.h   SetVector.h 
skipping to change at line 30 skipping to change at line 30
#ifndef LLVM_ADT_SETVECTOR_H #ifndef LLVM_ADT_SETVECTOR_H
#define LLVM_ADT_SETVECTOR_H #define LLVM_ADT_SETVECTOR_H
#include "llvm/ADT/SmallSet.h" #include "llvm/ADT/SmallSet.h"
#include <algorithm> #include <algorithm>
#include <cassert> #include <cassert>
#include <vector> #include <vector>
namespace llvm { namespace llvm {
/// \brief A vector that has set insertion semantics.
///
/// This adapter class provides a way to keep a set of things that also has the /// This adapter class provides a way to keep a set of things that also has the
/// property of a deterministic iteration order. The order of iteration is the /// property of a deterministic iteration order. The order of iteration is the
/// order of insertion. /// order of insertion.
/// @brief A vector that has set insertion semantics.
template <typename T, typename Vector = std::vector<T>, template <typename T, typename Vector = std::vector<T>,
typename Set = SmallSet<T, 16> > typename Set = SmallSet<T, 16> >
class SetVector { class SetVector {
public: public:
typedef T value_type; typedef T value_type;
typedef T key_type; typedef T key_type;
typedef T& reference; typedef T& reference;
typedef const T& const_reference; typedef const T& const_reference;
typedef Set set_type; typedef Set set_type;
typedef Vector vector_type; typedef Vector vector_type;
typedef typename vector_type::const_iterator iterator; typedef typename vector_type::const_iterator iterator;
typedef typename vector_type::const_iterator const_iterator; typedef typename vector_type::const_iterator const_iterator;
typedef typename vector_type::size_type size_type; typedef typename vector_type::size_type size_type;
/// @brief Construct an empty SetVector /// \brief Construct an empty SetVector
SetVector() {} SetVector() {}
/// @brief Initialize a SetVector with a range of elements /// \brief Initialize a SetVector with a range of elements
template<typename It> template<typename It>
SetVector(It Start, It End) { SetVector(It Start, It End) {
insert(Start, End); insert(Start, End);
} }
/// @brief Determine if the SetVector is empty or not. /// \brief Determine if the SetVector is empty or not.
bool empty() const { bool empty() const {
return vector_.empty(); return vector_.empty();
} }
/// @brief Determine the number of elements in the SetVector. /// \brief Determine the number of elements in the SetVector.
size_type size() const { size_type size() const {
return vector_.size(); return vector_.size();
} }
/// @brief Get an iterator to the beginning of the SetVector. /// \brief Get an iterator to the beginning of the SetVector.
iterator begin() { iterator begin() {
return vector_.begin(); return vector_.begin();
} }
/// @brief Get a const_iterator to the beginning of the SetVector. /// \brief Get a const_iterator to the beginning of the SetVector.
const_iterator begin() const { const_iterator begin() const {
return vector_.begin(); return vector_.begin();
} }
/// @brief Get an iterator to the end of the SetVector. /// \brief Get an iterator to the end of the SetVector.
iterator end() { iterator end() {
return vector_.end(); return vector_.end();
} }
/// @brief Get a const_iterator to the end of the SetVector. /// \brief Get a const_iterator to the end of the SetVector.
const_iterator end() const { const_iterator end() const {
return vector_.end(); return vector_.end();
} }
/// @brief Return the last element of the SetVector. /// \brief Return the last element of the SetVector.
const T &back() const { const T &back() const {
assert(!empty() && "Cannot call back() on empty SetVector!"); assert(!empty() && "Cannot call back() on empty SetVector!");
return vector_.back(); return vector_.back();
} }
/// @brief Index into the SetVector. /// \brief Index into the SetVector.
const_reference operator[](size_type n) const { const_reference operator[](size_type n) const {
assert(n < vector_.size() && "SetVector access out of range!"); assert(n < vector_.size() && "SetVector access out of range!");
return vector_[n]; return vector_[n];
} }
/// @returns true iff the element was inserted into the SetVector. /// \brief Insert a new element into the SetVector.
/// @brief Insert a new element into the SetVector. /// \returns true iff the element was inserted into the SetVector.
bool insert(const value_type &X) { bool insert(const value_type &X) {
bool result = set_.insert(X); bool result = set_.insert(X);
if (result) if (result)
vector_.push_back(X); vector_.push_back(X);
return result; return result;
} }
/// @brief Insert a range of elements into the SetVector. /// \brief Insert a range of elements into the SetVector.
template<typename It> template<typename It>
void insert(It Start, It End) { void insert(It Start, It End) {
for (; Start != End; ++Start) for (; Start != End; ++Start)
if (set_.insert(*Start)) if (set_.insert(*Start))
vector_.push_back(*Start); vector_.push_back(*Start);
} }
/// @brief Remove an item from the set vector. /// \brief Remove an item from the set vector.
bool remove(const value_type& X) { bool remove(const value_type& X) {
if (set_.erase(X)) { if (set_.erase(X)) {
typename vector_type::iterator I = typename vector_type::iterator I =
std::find(vector_.begin(), vector_.end(), X); std::find(vector_.begin(), vector_.end(), X);
assert(I != vector_.end() && "Corrupted SetVector instances!"); assert(I != vector_.end() && "Corrupted SetVector instances!");
vector_.erase(I); vector_.erase(I);
return true; return true;
} }
return false; return false;
} }
/// @returns 0 if the element is not in the SetVector, 1 if it is. /// \brief Remove items from the set vector based on a predicate function
/// @brief Count the number of elements of a given key in the SetVector. .
///
/// This is intended to be equivalent to the following code, if we could
/// write it:
///
/// \code
/// V.erase(std::remove_if(V.begin(), V.end(), P), V.end());
/// \endcode
///
/// However, SetVector doesn't expose non-const iterators, making any
/// algorithm like remove_if impossible to use.
///
/// \returns true if any element is removed.
template <typename UnaryPredicate>
bool remove_if(UnaryPredicate P) {
typename vector_type::iterator I
= std::remove_if(vector_.begin(), vector_.end(),
TestAndEraseFromSet<UnaryPredicate>(P, set_));
if (I == vector_.end())
return false;
vector_.erase(I, vector_.end());
return true;
}
/// \brief Count the number of elements of a given key in the SetVector.
/// \returns 0 if the element is not in the SetVector, 1 if it is.
size_type count(const key_type &key) const { size_type count(const key_type &key) const {
return set_.count(key); return set_.count(key);
} }
/// @brief Completely clear the SetVector /// \brief Completely clear the SetVector
void clear() { void clear() {
set_.clear(); set_.clear();
vector_.clear(); vector_.clear();
} }
/// @brief Remove the last element of the SetVector. /// \brief Remove the last element of the SetVector.
void pop_back() { void pop_back() {
assert(!empty() && "Cannot remove an element from an empty SetVector!") ; assert(!empty() && "Cannot remove an element from an empty SetVector!") ;
set_.erase(back()); set_.erase(back());
vector_.pop_back(); vector_.pop_back();
} }
T pop_back_val() { T pop_back_val() {
T Ret = back(); T Ret = back();
pop_back(); pop_back();
return Ret; return Ret;
skipping to change at line 162 skipping to change at line 187
bool operator==(const SetVector &that) const { bool operator==(const SetVector &that) const {
return vector_ == that.vector_; return vector_ == that.vector_;
} }
bool operator!=(const SetVector &that) const { bool operator!=(const SetVector &that) const {
return vector_ != that.vector_; return vector_ != that.vector_;
} }
private: private:
/// \brief A wrapper predicate designed for use with std::remove_if.
///
/// This predicate wraps a predicate suitable for use with std::remove_if
to
/// call set_.erase(x) on each element which is slated for removal.
template <typename UnaryPredicate>
class TestAndEraseFromSet {
UnaryPredicate P;
set_type &set_;
public:
typedef typename UnaryPredicate::argument_type argument_type;
TestAndEraseFromSet(UnaryPredicate P, set_type &set_) : P(P), set_(set_
) {}
bool operator()(argument_type Arg) {
if (P(Arg)) {
set_.erase(Arg);
return true;
}
return false;
}
};
set_type set_; ///< The set. set_type set_; ///< The set.
vector_type vector_; ///< The vector. vector_type vector_; ///< The vector.
}; };
/// SmallSetVector - A SetVector that performs no allocations if smaller th an /// \brief A SetVector that performs no allocations if smaller than
/// a certain size. /// a certain size.
template <typename T, unsigned N> template <typename T, unsigned N>
class SmallSetVector : public SetVector<T, SmallVector<T, N>, SmallSet<T, N > > { class SmallSetVector : public SetVector<T, SmallVector<T, N>, SmallSet<T, N > > {
public: public:
SmallSetVector() {} SmallSetVector() {}
/// @brief Initialize a SmallSetVector with a range of elements /// \brief Initialize a SmallSetVector with a range of elements
template<typename It> template<typename It>
SmallSetVector(It Start, It End) { SmallSetVector(It Start, It End) {
this->insert(Start, End); this->insert(Start, End);
} }
}; };
} // End llvm namespace } // End llvm namespace
// vim: sw=2 ai // vim: sw=2 ai
#endif #endif
 End of changes. 21 change blocks. 
21 lines changed or deleted 72 lines changed or added


 SimplifyIndVar.h   SimplifyIndVar.h 
skipping to change at line 24 skipping to change at line 24
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_TRANSFORMS_UTILS_SIMPLIFYINDVAR_H #ifndef LLVM_TRANSFORMS_UTILS_SIMPLIFYINDVAR_H
#define LLVM_TRANSFORMS_UTILS_SIMPLIFYINDVAR_H #define LLVM_TRANSFORMS_UTILS_SIMPLIFYINDVAR_H
#include "llvm/Support/CommandLine.h" #include "llvm/Support/CommandLine.h"
#include "llvm/Support/ValueHandle.h" #include "llvm/Support/ValueHandle.h"
namespace llvm { namespace llvm {
extern cl::opt<bool> DisableIVRewrite;
class CastInst; class CastInst;
class IVUsers; class IVUsers;
class Loop; class Loop;
class LPPassManager; class LPPassManager;
class PHINode; class PHINode;
class ScalarEvolution; class ScalarEvolution;
/// Interface for visiting interesting IV users that are recognized but not /// Interface for visiting interesting IV users that are recognized but not
/// simplified by this utility. /// simplified by this utility.
class IVVisitor { class IVVisitor {
 End of changes. 1 change blocks. 
2 lines changed or deleted 0 lines changed or added


 SlotIndexes.h   SlotIndexes.h 
skipping to change at line 79 skipping to change at line 79
static void noteHead(IndexListEntry*, IndexListEntry*) {} static void noteHead(IndexListEntry*, IndexListEntry*) {}
void deleteNode(IndexListEntry *N) {} void deleteNode(IndexListEntry *N) {}
private: private:
void createNode(const IndexListEntry &); void createNode(const IndexListEntry &);
}; };
/// SlotIndex - An opaque wrapper around machine indexes. /// SlotIndex - An opaque wrapper around machine indexes.
class SlotIndex { class SlotIndex {
friend class SlotIndexes; friend class SlotIndexes;
friend struct DenseMapInfo<SlotIndex>;
enum Slot { enum Slot {
/// Basic block boundary. Used for live ranges entering and leaving a /// Basic block boundary. Used for live ranges entering and leaving a
/// block without being live in the layout neighbor. Also used as th e /// block without being live in the layout neighbor. Also used as th e
/// def slot of PHI-defs. /// def slot of PHI-defs.
Slot_Block, Slot_Block,
/// Early-clobber register use/def slot. A live range defined at /// Early-clobber register use/def slot. A live range defined at
/// Slot_EarlyCLobber interferes with normal live ranges killed at /// Slot_EarlyCLobber interferes with normal live ranges killed at
/// Slot_Register. Also used as the kill slot for live ranges tied t o an /// Slot_Register. Also used as the kill slot for live ranges tied t o an
skipping to change at line 124 skipping to change at line 123
int getIndex() const { int getIndex() const {
return listEntry()->getIndex() | getSlot(); return listEntry()->getIndex() | getSlot();
} }
/// Returns the slot for this SlotIndex. /// Returns the slot for this SlotIndex.
Slot getSlot() const { Slot getSlot() const {
return static_cast<Slot>(lie.getInt()); return static_cast<Slot>(lie.getInt());
} }
static inline unsigned getHashValue(const SlotIndex &v) {
void *ptrVal = v.lie.getOpaqueValue();
return (unsigned((intptr_t)ptrVal)) ^ (unsigned((intptr_t)ptrVal) >>
9);
}
public: public:
enum { enum {
/// The default distance between instructions as returned by distance (). /// The default distance between instructions as returned by distance ().
/// This may vary as instructions are inserted and removed. /// This may vary as instructions are inserted and removed.
InstrDist = 4 * Slot_Count InstrDist = 4 * Slot_Count
}; };
static inline SlotIndex getEmptyKey() {
return SlotIndex(0, 1);
}
static inline SlotIndex getTombstoneKey() {
return SlotIndex(0, 2);
}
/// Construct an invalid index. /// Construct an invalid index.
SlotIndex() : lie(0, 0) {} SlotIndex() : lie(0, 0) {}
// Construct a new slot index from the given one, and set the slot. // Construct a new slot index from the given one, and set the slot.
SlotIndex(const SlotIndex &li, Slot s) : lie(li.listEntry(), unsigned(s )) { SlotIndex(const SlotIndex &li, Slot s) : lie(li.listEntry(), unsigned(s )) {
assert(lie.getPointer() != 0 && assert(lie.getPointer() != 0 &&
"Attempt to construct index with 0 pointer."); "Attempt to construct index with 0 pointer.");
} }
/// Returns true if this is a valid index. Invalid indicies do /// Returns true if this is a valid index. Invalid indicies do
skipping to change at line 296 skipping to change at line 282
} }
/// Returns the previous index. This is the index corresponding to this /// Returns the previous index. This is the index corresponding to this
/// index's slot, but for the previous instruction. /// index's slot, but for the previous instruction.
SlotIndex getPrevIndex() const { SlotIndex getPrevIndex() const {
return SlotIndex(listEntry()->getPrevNode(), getSlot()); return SlotIndex(listEntry()->getPrevNode(), getSlot());
} }
}; };
/// DenseMapInfo specialization for SlotIndex.
template <>
struct DenseMapInfo<SlotIndex> {
static inline SlotIndex getEmptyKey() {
return SlotIndex::getEmptyKey();
}
static inline SlotIndex getTombstoneKey() {
return SlotIndex::getTombstoneKey();
}
static inline unsigned getHashValue(const SlotIndex &v) {
return SlotIndex::getHashValue(v);
}
static inline bool isEqual(const SlotIndex &LHS, const SlotIndex &RHS)
{
return (LHS == RHS);
}
};
template <> struct isPodLike<SlotIndex> { static const bool value = true; }; template <> struct isPodLike<SlotIndex> { static const bool value = true; };
inline raw_ostream& operator<<(raw_ostream &os, SlotIndex li) { inline raw_ostream& operator<<(raw_ostream &os, SlotIndex li) {
li.print(os); li.print(os);
return os; return os;
} }
typedef std::pair<SlotIndex, MachineBasicBlock*> IdxMBBPair; typedef std::pair<SlotIndex, MachineBasicBlock*> IdxMBBPair;
inline bool operator<(SlotIndex V, const IdxMBBPair &IM) { inline bool operator<(SlotIndex V, const IdxMBBPair &IM) {
skipping to change at line 346 skipping to change at line 315
/// SlotIndexes pass. /// SlotIndexes pass.
/// ///
/// This pass assigns indexes to each instruction. /// This pass assigns indexes to each instruction.
class SlotIndexes : public MachineFunctionPass { class SlotIndexes : public MachineFunctionPass {
private: private:
typedef ilist<IndexListEntry> IndexList; typedef ilist<IndexListEntry> IndexList;
IndexList indexList; IndexList indexList;
MachineFunction *mf; MachineFunction *mf;
unsigned functionSize;
typedef DenseMap<const MachineInstr*, SlotIndex> Mi2IndexMap; typedef DenseMap<const MachineInstr*, SlotIndex> Mi2IndexMap;
Mi2IndexMap mi2iMap; Mi2IndexMap mi2iMap;
/// MBBRanges - Map MBB number to (start, stop) indexes. /// MBBRanges - Map MBB number to (start, stop) indexes.
SmallVector<std::pair<SlotIndex, SlotIndex>, 8> MBBRanges; SmallVector<std::pair<SlotIndex, SlotIndex>, 8> MBBRanges;
/// Idx2MBBMap - Sorted list of pairs of index of first instruction /// Idx2MBBMap - Sorted list of pairs of index of first instruction
/// and MBB id. /// and MBB id.
SmallVector<IdxMBBPair, 8> idx2MBBMap; SmallVector<IdxMBBPair, 8> idx2MBBMap;
skipping to change at line 404 skipping to change at line 372
SlotIndex getZeroIndex() { SlotIndex getZeroIndex() {
assert(indexList.front().getIndex() == 0 && "First index is not 0?"); assert(indexList.front().getIndex() == 0 && "First index is not 0?");
return SlotIndex(&indexList.front(), 0); return SlotIndex(&indexList.front(), 0);
} }
/// Returns the base index of the last slot in this analysis. /// Returns the base index of the last slot in this analysis.
SlotIndex getLastIndex() { SlotIndex getLastIndex() {
return SlotIndex(&indexList.back(), 0); return SlotIndex(&indexList.back(), 0);
} }
/// Returns the distance between the highest and lowest indexes allocat
ed
/// so far.
unsigned getIndexesLength() const {
assert(indexList.front().getIndex() == 0 &&
"Initial index isn't zero?");
return indexList.back().getIndex();
}
/// Returns the number of instructions in the function.
unsigned getFunctionSize() const {
return functionSize;
}
/// Returns true if the given machine instr is mapped to an index, /// Returns true if the given machine instr is mapped to an index,
/// otherwise returns false. /// otherwise returns false.
bool hasIndex(const MachineInstr *instr) const { bool hasIndex(const MachineInstr *instr) const {
return mi2iMap.count(instr); return mi2iMap.count(instr);
} }
/// Returns the base index for the given instruction. /// Returns the base index for the given instruction.
SlotIndex getInstructionIndex(const MachineInstr *MI) const { SlotIndex getInstructionIndex(const MachineInstr *MI) const {
// Instructions inside a bundle have the same number as the bundle it self. // Instructions inside a bundle have the same number as the bundle it self.
Mi2IndexMap::const_iterator itr = mi2iMap.find(getBundleStart(MI)); Mi2IndexMap::const_iterator itr = mi2iMap.find(getBundleStart(MI));
skipping to change at line 446 skipping to change at line 401
/// Returns the next non-null index. /// Returns the next non-null index.
SlotIndex getNextNonNullIndex(SlotIndex index) { SlotIndex getNextNonNullIndex(SlotIndex index) {
IndexList::iterator itr(index.listEntry()); IndexList::iterator itr(index.listEntry());
++itr; ++itr;
while (itr != indexList.end() && itr->getInstr() == 0) { ++itr; } while (itr != indexList.end() && itr->getInstr() == 0) { ++itr; }
return SlotIndex(itr, index.getSlot()); return SlotIndex(itr, index.getSlot());
} }
/// getIndexBefore - Returns the index of the last indexed instruction /// getIndexBefore - Returns the index of the last indexed instruction
/// before MI, or the the start index of its basic block. /// before MI, or the start index of its basic block.
/// MI is not required to have an index. /// MI is not required to have an index.
SlotIndex getIndexBefore(const MachineInstr *MI) const { SlotIndex getIndexBefore(const MachineInstr *MI) const {
const MachineBasicBlock *MBB = MI->getParent(); const MachineBasicBlock *MBB = MI->getParent();
assert(MBB && "MI must be inserted inna basic block"); assert(MBB && "MI must be inserted inna basic block");
MachineBasicBlock::const_iterator I = MI, B = MBB->begin(); MachineBasicBlock::const_iterator I = MI, B = MBB->begin();
for (;;) { for (;;) {
if (I == B) if (I == B)
return getMBBStartIdx(MBB); return getMBBStartIdx(MBB);
--I; --I;
Mi2IndexMap::const_iterator MapItr = mi2iMap.find(I); Mi2IndexMap::const_iterator MapItr = mi2iMap.find(I);
skipping to change at line 592 skipping to change at line 547
assert(mi->getParent() != 0 && "Instr must be added to function."); assert(mi->getParent() != 0 && "Instr must be added to function.");
// Get the entries where mi should be inserted. // Get the entries where mi should be inserted.
IndexList::iterator prevItr, nextItr; IndexList::iterator prevItr, nextItr;
if (Late) { if (Late) {
// Insert mi's index immediately before the following instruction. // Insert mi's index immediately before the following instruction.
nextItr = getIndexAfter(mi).listEntry(); nextItr = getIndexAfter(mi).listEntry();
prevItr = prior(nextItr); prevItr = prior(nextItr);
} else { } else {
// Insert mi's index immediately after the preceeding instruction. // Insert mi's index immediately after the preceding instruction.
prevItr = getIndexBefore(mi).listEntry(); prevItr = getIndexBefore(mi).listEntry();
nextItr = llvm::next(prevItr); nextItr = llvm::next(prevItr);
} }
// Get a number for the new instr, or 0 if there's no room currently. // Get a number for the new instr, or 0 if there's no room currently.
// In the latter case we'll force a renumber later. // In the latter case we'll force a renumber later.
unsigned dist = ((nextItr->getIndex() - prevItr->getIndex())/2) & ~3u ; unsigned dist = ((nextItr->getIndex() - prevItr->getIndex())/2) & ~3u ;
unsigned newNumber = prevItr->getIndex() + dist; unsigned newNumber = prevItr->getIndex() + dist;
// Insert a new list entry for mi. // Insert a new list entry for mi.
 End of changes. 8 change blocks. 
50 lines changed or deleted 2 lines changed or added


 SmallBitVector.h   SmallBitVector.h 
skipping to change at line 18 skipping to change at line 18
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// //
// This file implements the SmallBitVector class. // This file implements the SmallBitVector class.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_ADT_SMALLBITVECTOR_H #ifndef LLVM_ADT_SMALLBITVECTOR_H
#define LLVM_ADT_SMALLBITVECTOR_H #define LLVM_ADT_SMALLBITVECTOR_H
#include "llvm/ADT/BitVector.h" #include "llvm/ADT/BitVector.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/MathExtras.h" #include "llvm/Support/MathExtras.h"
#include <cassert> #include <cassert>
namespace llvm { namespace llvm {
/// SmallBitVector - This is a 'bitvector' (really, a variable-sized bit ar ray), /// SmallBitVector - This is a 'bitvector' (really, a variable-sized bit ar ray),
/// optimized for the case when the array is small. It contains one /// optimized for the case when the array is small. It contains one
/// pointer-sized field, which is directly used as a plain collection of bi ts /// pointer-sized field, which is directly used as a plain collection of bi ts
/// when possible, or as a pointer to a larger heap-allocated array when /// when possible, or as a pointer to a larger heap-allocated array when
/// necessary. This allows normal "small" cases to be fast without losing /// necessary. This allows normal "small" cases to be fast without losing
skipping to change at line 155 skipping to change at line 156
} }
/// SmallBitVector copy ctor. /// SmallBitVector copy ctor.
SmallBitVector(const SmallBitVector &RHS) { SmallBitVector(const SmallBitVector &RHS) {
if (RHS.isSmall()) if (RHS.isSmall())
X = RHS.X; X = RHS.X;
else else
switchToLarge(new BitVector(*RHS.getPointer())); switchToLarge(new BitVector(*RHS.getPointer()));
} }
#if LLVM_USE_RVALUE_REFERENCES
SmallBitVector(SmallBitVector &&RHS) : X(RHS.X) {
RHS.X = 1;
}
#endif
~SmallBitVector() { ~SmallBitVector() {
if (!isSmall()) if (!isSmall())
delete getPointer(); delete getPointer();
} }
/// empty - Tests whether there are no bits in this bitvector. /// empty - Tests whether there are no bits in this bitvector.
bool empty() const { bool empty() const {
return isSmall() ? getSmallSize() == 0 : getPointer()->empty(); return isSmall() ? getSmallSize() == 0 : getPointer()->empty();
} }
skipping to change at line 296 skipping to change at line 303
} }
SmallBitVector &set(unsigned Idx) { SmallBitVector &set(unsigned Idx) {
if (isSmall()) if (isSmall())
setSmallBits(getSmallBits() | (uintptr_t(1) << Idx)); setSmallBits(getSmallBits() | (uintptr_t(1) << Idx));
else else
getPointer()->set(Idx); getPointer()->set(Idx);
return *this; return *this;
} }
/// set - Efficiently set a range of bits in [I, E)
SmallBitVector &set(unsigned I, unsigned E) {
assert(I <= E && "Attempted to set backwards range!");
assert(E <= size() && "Attempted to set out-of-bounds range!");
if (I == E) return *this;
if (isSmall()) {
uintptr_t EMask = ((uintptr_t)1) << E;
uintptr_t IMask = ((uintptr_t)1) << I;
uintptr_t Mask = EMask - IMask;
setSmallBits(getSmallBits() | Mask);
} else
getPointer()->set(I, E);
return *this;
}
SmallBitVector &reset() { SmallBitVector &reset() {
if (isSmall()) if (isSmall())
setSmallBits(0); setSmallBits(0);
else else
getPointer()->reset(); getPointer()->reset();
return *this; return *this;
} }
SmallBitVector &reset(unsigned Idx) { SmallBitVector &reset(unsigned Idx) {
if (isSmall()) if (isSmall())
setSmallBits(getSmallBits() & ~(uintptr_t(1) << Idx)); setSmallBits(getSmallBits() & ~(uintptr_t(1) << Idx));
else else
getPointer()->reset(Idx); getPointer()->reset(Idx);
return *this; return *this;
} }
/// reset - Efficiently reset a range of bits in [I, E)
SmallBitVector &reset(unsigned I, unsigned E) {
assert(I <= E && "Attempted to reset backwards range!");
assert(E <= size() && "Attempted to reset out-of-bounds range!");
if (I == E) return *this;
if (isSmall()) {
uintptr_t EMask = ((uintptr_t)1) << E;
uintptr_t IMask = ((uintptr_t)1) << I;
uintptr_t Mask = EMask - IMask;
setSmallBits(getSmallBits() & ~Mask);
} else
getPointer()->reset(I, E);
return *this;
}
SmallBitVector &flip() { SmallBitVector &flip() {
if (isSmall()) if (isSmall())
setSmallBits(~getSmallBits()); setSmallBits(~getSmallBits());
else else
getPointer()->flip(); getPointer()->flip();
return *this; return *this;
} }
SmallBitVector &flip(unsigned Idx) { SmallBitVector &flip(unsigned Idx) {
if (isSmall()) if (isSmall())
skipping to change at line 350 skipping to change at line 387
assert(Idx < size() && "Out-of-bounds Bit access."); assert(Idx < size() && "Out-of-bounds Bit access.");
if (isSmall()) if (isSmall())
return ((getSmallBits() >> Idx) & 1) != 0; return ((getSmallBits() >> Idx) & 1) != 0;
return getPointer()->operator[](Idx); return getPointer()->operator[](Idx);
} }
bool test(unsigned Idx) const { bool test(unsigned Idx) const {
return (*this)[Idx]; return (*this)[Idx];
} }
/// Test if any common bits are set.
bool anyCommon(const SmallBitVector &RHS) const {
if (isSmall() && RHS.isSmall())
return (getSmallBits() & RHS.getSmallBits()) != 0;
if (!isSmall() && !RHS.isSmall())
return getPointer()->anyCommon(*RHS.getPointer());
for (unsigned i = 0, e = std::min(size(), RHS.size()); i != e; ++i)
if (test(i) && RHS.test(i))
return true;
return false;
}
// Comparison operators. // Comparison operators.
bool operator==(const SmallBitVector &RHS) const { bool operator==(const SmallBitVector &RHS) const {
if (size() != RHS.size()) if (size() != RHS.size())
return false; return false;
if (isSmall()) if (isSmall())
return getSmallBits() == RHS.getSmallBits(); return getSmallBits() == RHS.getSmallBits();
else else
return *getPointer() == *RHS.getPointer(); return *getPointer() == *RHS.getPointer();
} }
skipping to change at line 425 skipping to change at line 475
if (!RHS.isSmall()) if (!RHS.isSmall())
*getPointer() = *RHS.getPointer(); *getPointer() = *RHS.getPointer();
else { else {
delete getPointer(); delete getPointer();
X = RHS.X; X = RHS.X;
} }
} }
return *this; return *this;
} }
#if LLVM_USE_RVALUE_REFERENCES
const SmallBitVector &operator=(SmallBitVector &&RHS) {
if (this != &RHS) {
clear();
swap(RHS);
}
return *this;
}
#endif
void swap(SmallBitVector &RHS) { void swap(SmallBitVector &RHS) {
std::swap(X, RHS.X); std::swap(X, RHS.X);
} }
/// setBitsInMask - Add '1' bits from Mask to this vector. Don't resize.
/// This computes "*this |= Mask".
void setBitsInMask(const uint32_t *Mask, unsigned MaskWords = ~0u) {
if (isSmall())
applyMask<true, false>(Mask, MaskWords);
else
getPointer()->setBitsInMask(Mask, MaskWords);
}
/// clearBitsInMask - Clear any bits in this vector that are set in Mask.
/// Don't resize. This computes "*this &= ~Mask".
void clearBitsInMask(const uint32_t *Mask, unsigned MaskWords = ~0u) {
if (isSmall())
applyMask<false, false>(Mask, MaskWords);
else
getPointer()->clearBitsInMask(Mask, MaskWords);
}
/// setBitsNotInMask - Add a bit to this vector for every '0' bit in Mask
.
/// Don't resize. This computes "*this |= ~Mask".
void setBitsNotInMask(const uint32_t *Mask, unsigned MaskWords = ~0u) {
if (isSmall())
applyMask<true, true>(Mask, MaskWords);
else
getPointer()->setBitsNotInMask(Mask, MaskWords);
}
/// clearBitsNotInMask - Clear a bit in this vector for every '0' bit in
Mask.
/// Don't resize. This computes "*this &= Mask".
void clearBitsNotInMask(const uint32_t *Mask, unsigned MaskWords = ~0u) {
if (isSmall())
applyMask<false, true>(Mask, MaskWords);
else
getPointer()->clearBitsNotInMask(Mask, MaskWords);
}
private:
template<bool AddBits, bool InvertMask>
void applyMask(const uint32_t *Mask, unsigned MaskWords) {
assert((NumBaseBits == 64 || NumBaseBits == 32) && "Unsupported word si
ze");
if (NumBaseBits == 64 && MaskWords >= 2) {
uint64_t M = Mask[0] | (uint64_t(Mask[1]) << 32);
if (InvertMask) M = ~M;
if (AddBits) setSmallBits(getSmallBits() | M);
else setSmallBits(getSmallBits() & ~M);
} else {
uint32_t M = Mask[0];
if (InvertMask) M = ~M;
if (AddBits) setSmallBits(getSmallBits() | M);
else setSmallBits(getSmallBits() & ~M);
}
}
}; };
inline SmallBitVector inline SmallBitVector
operator&(const SmallBitVector &LHS, const SmallBitVector &RHS) { operator&(const SmallBitVector &LHS, const SmallBitVector &RHS) {
SmallBitVector Result(LHS); SmallBitVector Result(LHS);
Result &= RHS; Result &= RHS;
return Result; return Result;
} }
inline SmallBitVector inline SmallBitVector
 End of changes. 7 change blocks. 
0 lines changed or deleted 116 lines changed or added


 SmallPtrSet.h   SmallPtrSet.h 
skipping to change at line 18 skipping to change at line 18
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// //
// This file defines the SmallPtrSet class. See the doxygen comment for // This file defines the SmallPtrSet class. See the doxygen comment for
// SmallPtrSetImpl for more details on the algorithm used. // SmallPtrSetImpl for more details on the algorithm used.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_ADT_SMALLPTRSET_H #ifndef LLVM_ADT_SMALLPTRSET_H
#define LLVM_ADT_SMALLPTRSET_H #define LLVM_ADT_SMALLPTRSET_H
#include "llvm/Support/Compiler.h"
#include "llvm/Support/DataTypes.h"
#include "llvm/Support/PointerLikeTypeTraits.h"
#include <cassert> #include <cassert>
#include <cstddef> #include <cstddef>
#include <cstring> #include <cstring>
#include <iterator> #include <iterator>
#include "llvm/Support/DataTypes.h"
#include "llvm/Support/PointerLikeTypeTraits.h"
namespace llvm { namespace llvm {
class SmallPtrSetIteratorImpl; class SmallPtrSetIteratorImpl;
/// SmallPtrSetImpl - This is the common code shared among all the /// SmallPtrSetImpl - This is the common code shared among all the
/// SmallPtrSet<>'s, which is almost everything. SmallPtrSet has two modes , one /// SmallPtrSet<>'s, which is almost everything. SmallPtrSet has two modes , one
/// for small and one for large sets. /// for small and one for large sets.
/// ///
/// Small sets use an array of pointers allocated in the SmallPtrSet object , /// Small sets use an array of pointers allocated in the SmallPtrSet object ,
skipping to change at line 135 skipping to change at line 136
private: private:
bool isSmall() const { return CurArray == SmallArray; } bool isSmall() const { return CurArray == SmallArray; }
const void * const *FindBucketFor(const void *Ptr) const; const void * const *FindBucketFor(const void *Ptr) const;
void shrink_and_clear(); void shrink_and_clear();
/// Grow - Allocate a larger backing store for the buckets and move it ov er. /// Grow - Allocate a larger backing store for the buckets and move it ov er.
void Grow(unsigned NewSize); void Grow(unsigned NewSize);
void operator=(const SmallPtrSetImpl &RHS); // DO NOT IMPLEMENT. void operator=(const SmallPtrSetImpl &RHS) LLVM_DELETED_FUNCTION;
protected: protected:
/// swap - Swaps the elements of two sets. /// swap - Swaps the elements of two sets.
/// Note: This method assumes that both sets have the same small size. /// Note: This method assumes that both sets have the same small size.
void swap(SmallPtrSetImpl &RHS); void swap(SmallPtrSetImpl &RHS);
void CopyFrom(const SmallPtrSetImpl &RHS); void CopyFrom(const SmallPtrSetImpl &RHS);
}; };
/// SmallPtrSetIteratorImpl - This is the common base class shared between all /// SmallPtrSetIteratorImpl - This is the common base class shared between all
/// instances of SmallPtrSetIterator. /// instances of SmallPtrSetIterator.
 End of changes. 3 change blocks. 
3 lines changed or deleted 4 lines changed or added


 SmallString.h   SmallString.h 
skipping to change at line 47 skipping to change at line 47
/// Copy ctor. /// Copy ctor.
SmallString(const SmallString &RHS) : SmallVector<char, InternalLen>(RHS) {} SmallString(const SmallString &RHS) : SmallVector<char, InternalLen>(RHS) {}
// Note that in order to add new overloads for append & assign, we have t o // Note that in order to add new overloads for append & assign, we have t o
// duplicate the inherited versions so as not to inadvertently hide them. // duplicate the inherited versions so as not to inadvertently hide them.
/// @} /// @}
/// @name String Assignment /// @name String Assignment
/// @{ /// @{
/// Assign from a repeated element /// Assign from a repeated element.
void assign(unsigned NumElts, char Elt) { void assign(size_t NumElts, char Elt) {
this->SmallVectorImpl<char>::assign(NumElts, Elt); this->SmallVectorImpl<char>::assign(NumElts, Elt);
} }
/// Assign from an iterator pair /// Assign from an iterator pair.
template<typename in_iter> template<typename in_iter>
void assign(in_iter S, in_iter E) { void assign(in_iter S, in_iter E) {
this->clear(); this->clear();
SmallVectorImpl<char>::append(S, E); SmallVectorImpl<char>::append(S, E);
} }
/// Assign from a StringRef /// Assign from a StringRef.
void assign(StringRef RHS) { void assign(StringRef RHS) {
this->clear(); this->clear();
SmallVectorImpl<char>::append(RHS.begin(), RHS.end()); SmallVectorImpl<char>::append(RHS.begin(), RHS.end());
} }
/// Assign from a SmallVector /// Assign from a SmallVector.
void assign(const SmallVectorImpl<char> &RHS) { void assign(const SmallVectorImpl<char> &RHS) {
this->clear(); this->clear();
SmallVectorImpl<char>::append(RHS.begin(), RHS.end()); SmallVectorImpl<char>::append(RHS.begin(), RHS.end());
} }
/// @} /// @}
/// @name String Concatenation /// @name String Concatenation
/// @{ /// @{
/// Append from an iterator pair /// Append from an iterator pair.
template<typename in_iter> template<typename in_iter>
void append(in_iter S, in_iter E) { void append(in_iter S, in_iter E) {
SmallVectorImpl<char>::append(S, E); SmallVectorImpl<char>::append(S, E);
} }
/// Append from a StringRef void append(size_t NumInputs, char Elt) {
SmallVectorImpl<char>::append(NumInputs, Elt);
}
/// Append from a StringRef.
void append(StringRef RHS) { void append(StringRef RHS) {
SmallVectorImpl<char>::append(RHS.begin(), RHS.end()); SmallVectorImpl<char>::append(RHS.begin(), RHS.end());
} }
/// Append from a SmallVector /// Append from a SmallVector.
void append(const SmallVectorImpl<char> &RHS) { void append(const SmallVectorImpl<char> &RHS) {
SmallVectorImpl<char>::append(RHS.begin(), RHS.end()); SmallVectorImpl<char>::append(RHS.begin(), RHS.end());
} }
/// @} /// @}
/// @name String Comparison /// @name String Comparison
/// @{ /// @{
/// equals - Check for string equality, this is more efficient than /// Check for string equality. This is more efficient than compare() whe
/// compare() when the relative ordering of inequal strings isn't needed. n
/// the relative ordering of inequal strings isn't needed.
bool equals(StringRef RHS) const { bool equals(StringRef RHS) const {
return str().equals(RHS); return str().equals(RHS);
} }
/// equals_lower - Check for string equality, ignoring case. /// Check for string equality, ignoring case.
bool equals_lower(StringRef RHS) const { bool equals_lower(StringRef RHS) const {
return str().equals_lower(RHS); return str().equals_lower(RHS);
} }
/// compare - Compare two strings; the result is -1, 0, or 1 if this stri /// Compare two strings; the result is -1, 0, or 1 if this string is
ng /// lexicographically less than, equal to, or greater than the \p RHS.
/// is lexicographically less than, equal to, or greater than the \arg RH
S.
int compare(StringRef RHS) const { int compare(StringRef RHS) const {
return str().compare(RHS); return str().compare(RHS);
} }
/// compare_lower - Compare two strings, ignoring case. /// compare_lower - Compare two strings, ignoring case.
int compare_lower(StringRef RHS) const { int compare_lower(StringRef RHS) const {
return str().compare_lower(RHS); return str().compare_lower(RHS);
} }
/// compare_numeric - Compare two strings, treating sequences of digits a s /// compare_numeric - Compare two strings, treating sequences of digits a s
/// numbers. /// numbers.
int compare_numeric(StringRef RHS) const { int compare_numeric(StringRef RHS) const {
return str().compare_numeric(RHS); return str().compare_numeric(RHS);
} }
/// @} /// @}
/// @name String Predicates /// @name String Predicates
/// @{ /// @{
/// startswith - Check if this string starts with the given \arg Prefix. /// startswith - Check if this string starts with the given \p Prefix.
bool startswith(StringRef Prefix) const { bool startswith(StringRef Prefix) const {
return str().startswith(Prefix); return str().startswith(Prefix);
} }
/// endswith - Check if this string ends with the given \arg Suffix. /// endswith - Check if this string ends with the given \p Suffix.
bool endswith(StringRef Suffix) const { bool endswith(StringRef Suffix) const {
return str().endswith(Suffix); return str().endswith(Suffix);
} }
/// @} /// @}
/// @name String Searching /// @name String Searching
/// @{ /// @{
/// find - Search for the first character \arg C in the string. /// find - Search for the first character \p C in the string.
/// ///
/// \return - The index of the first occurrence of \arg C, or npos if not /// \return - The index of the first occurrence of \p C, or npos if not
/// found. /// found.
size_t find(char C, size_t From = 0) const { size_t find(char C, size_t From = 0) const {
return str().find(C, From); return str().find(C, From);
} }
/// find - Search for the first string \arg Str in the string. /// Search for the first string \p Str in the string.
/// ///
/// \return - The index of the first occurrence of \arg Str, or npos if n ot /// \returns The index of the first occurrence of \p Str, or npos if not
/// found. /// found.
size_t find(StringRef Str, size_t From = 0) const { size_t find(StringRef Str, size_t From = 0) const {
return str().find(Str, From); return str().find(Str, From);
} }
/// rfind - Search for the last character \arg C in the string. /// Search for the last character \p C in the string.
/// ///
/// \return - The index of the last occurrence of \arg C, or npos if not /// \returns The index of the last occurrence of \p C, or npos if not
/// found. /// found.
size_t rfind(char C, size_t From = StringRef::npos) const { size_t rfind(char C, size_t From = StringRef::npos) const {
return str().rfind(C, From); return str().rfind(C, From);
} }
/// rfind - Search for the last string \arg Str in the string. /// Search for the last string \p Str in the string.
/// ///
/// \return - The index of the last occurrence of \arg Str, or npos if no t /// \returns The index of the last occurrence of \p Str, or npos if not
/// found. /// found.
size_t rfind(StringRef Str) const { size_t rfind(StringRef Str) const {
return str().rfind(Str); return str().rfind(Str);
} }
/// find_first_of - Find the first character in the string that is \arg C /// Find the first character in the string that is \p C, or npos if not
, /// found. Same as find.
/// or npos if not found. Same as find.
size_t find_first_of(char C, size_t From = 0) const { size_t find_first_of(char C, size_t From = 0) const {
return str().find_first_of(C, From); return str().find_first_of(C, From);
} }
/// find_first_of - Find the first character in the string that is in \ar /// Find the first character in the string that is in \p Chars, or npos i
g f
/// Chars, or npos if not found. /// not found.
/// ///
/// Note: O(size() + Chars.size()) /// Complexity: O(size() + Chars.size())
size_t find_first_of(StringRef Chars, size_t From = 0) const { size_t find_first_of(StringRef Chars, size_t From = 0) const {
return str().find_first_of(Chars, From); return str().find_first_of(Chars, From);
} }
/// find_first_not_of - Find the first character in the string that is no /// Find the first character in the string that is not \p C or npos if no
t t
/// \arg C or npos if not found. /// found.
size_t find_first_not_of(char C, size_t From = 0) const { size_t find_first_not_of(char C, size_t From = 0) const {
return str().find_first_not_of(C, From); return str().find_first_not_of(C, From);
} }
/// find_first_not_of - Find the first character in the string that is no /// Find the first character in the string that is not in the string
t /// \p Chars, or npos if not found.
/// in the string \arg Chars, or npos if not found.
/// ///
/// Note: O(size() + Chars.size()) /// Complexity: O(size() + Chars.size())
size_t find_first_not_of(StringRef Chars, size_t From = 0) const { size_t find_first_not_of(StringRef Chars, size_t From = 0) const {
return str().find_first_not_of(Chars, From); return str().find_first_not_of(Chars, From);
} }
/// find_last_of - Find the last character in the string that is \arg C, /// Find the last character in the string that is \p C, or npos if not
or /// found.
/// npos if not found.
size_t find_last_of(char C, size_t From = StringRef::npos) const { size_t find_last_of(char C, size_t From = StringRef::npos) const {
return str().find_last_of(C, From); return str().find_last_of(C, From);
} }
/// find_last_of - Find the last character in the string that is in \arg /// Find the last character in the string that is in \p C, or npos if not
C, /// found.
/// or npos if not found.
/// ///
/// Note: O(size() + Chars.size()) /// Complexity: O(size() + Chars.size())
size_t find_last_of( size_t find_last_of(
StringRef Chars, size_t From = StringRef::npos) const { StringRef Chars, size_t From = StringRef::npos) const {
return str().find_last_of(Chars, From); return str().find_last_of(Chars, From);
} }
/// @} /// @}
/// @name Helpful Algorithms /// @name Helpful Algorithms
/// @{ /// @{
/// count - Return the number of occurrences of \arg C in the string. /// Return the number of occurrences of \p C in the string.
size_t count(char C) const { size_t count(char C) const {
return str().count(C); return str().count(C);
} }
/// count - Return the number of non-overlapped occurrences of \arg Str i /// Return the number of non-overlapped occurrences of \p Str in the
n /// string.
/// the string.
size_t count(StringRef Str) const { size_t count(StringRef Str) const {
return str().count(Str); return str().count(Str);
} }
/// @} /// @}
/// @name Substring Operations /// @name Substring Operations
/// @{ /// @{
/// substr - Return a reference to the substring from [Start, Start + N). /// Return a reference to the substring from [Start, Start + N).
/// ///
/// \param Start - The index of the starting character in the substring; if /// \param Start The index of the starting character in the substring; if
/// the index is npos or greater than the length of the string then the /// the index is npos or greater than the length of the string then the
/// empty substring will be returned. /// empty substring will be returned.
/// ///
/// \param N - The number of characters to included in the substring. If N /// \param N The number of characters to included in the substring. If \p N
/// exceeds the number of characters remaining in the string, the string /// exceeds the number of characters remaining in the string, the string
/// suffix (starting with \arg Start) will be returned. /// suffix (starting with \p Start) will be returned.
StringRef substr(size_t Start, size_t N = StringRef::npos) const { StringRef substr(size_t Start, size_t N = StringRef::npos) const {
return str().substr(Start, N); return str().substr(Start, N);
} }
/// slice - Return a reference to the substring from [Start, End). /// Return a reference to the substring from [Start, End).
/// ///
/// \param Start - The index of the starting character in the substring; if /// \param Start The index of the starting character in the substring; if
/// the index is npos or greater than the length of the string then the /// the index is npos or greater than the length of the string then the
/// empty substring will be returned. /// empty substring will be returned.
/// ///
/// \param End - The index following the last character to include in the /// \param End The index following the last character to include in the
/// substring. If this is npos, or less than \arg Start, or exceeds the /// substring. If this is npos, or less than \p Start, or exceeds the
/// number of characters remaining in the string, the string suffix /// number of characters remaining in the string, the string suffix
/// (starting with \arg Start) will be returned. /// (starting with \p Start) will be returned.
StringRef slice(size_t Start, size_t End) const { StringRef slice(size_t Start, size_t End) const {
return str().slice(Start, End); return str().slice(Start, End);
} }
// Extra methods. // Extra methods.
/// Explicit conversion to StringRef /// Explicit conversion to StringRef.
StringRef str() const { return StringRef(this->begin(), this->size()); } StringRef str() const { return StringRef(this->begin(), this->size()); }
// TODO: Make this const, if it's safe... // TODO: Make this const, if it's safe...
const char* c_str() { const char* c_str() {
this->push_back(0); this->push_back(0);
this->pop_back(); this->pop_back();
return this->data(); return this->data();
} }
/// Implicit conversion to StringRef. /// Implicit conversion to StringRef.
 End of changes. 40 change blocks. 
60 lines changed or deleted 58 lines changed or added


 SmallVector.h   SmallVector.h 
skipping to change at line 17 skipping to change at line 17
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// //
// This file defines the SmallVector class. // This file defines the SmallVector class.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_ADT_SMALLVECTOR_H #ifndef LLVM_ADT_SMALLVECTOR_H
#define LLVM_ADT_SMALLVECTOR_H #define LLVM_ADT_SMALLVECTOR_H
#include "llvm/Support/AlignOf.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/type_traits.h" #include "llvm/Support/type_traits.h"
#include <algorithm> #include <algorithm>
#include <cassert> #include <cassert>
#include <cstddef> #include <cstddef>
#include <cstdlib> #include <cstdlib>
#include <cstring> #include <cstring>
#include <iterator> #include <iterator>
#include <memory> #include <memory>
namespace llvm { namespace llvm {
/// SmallVectorBase - This is all the non-templated stuff common to all /// SmallVectorBase - This is all the non-templated stuff common to all
/// SmallVectors. /// SmallVectors.
class SmallVectorBase { class SmallVectorBase {
protected: protected:
void *BeginX, *EndX, *CapacityX; void *BeginX, *EndX, *CapacityX;
// Allocate raw space for N elements of type T. If T has a ctor or dtor,
we
// don't want it to be automatically run, so we need to represent the spa
ce as
// something else. An array of char would work great, but might not be
// aligned sufficiently. Instead we use some number of union instances f
or
// the space, which guarantee maximal alignment.
union U {
double D;
long double LD;
long long L;
void *P;
} FirstEl;
// Space after 'FirstEl' is clobbered, do not add any instance vars after
it.
protected: protected:
SmallVectorBase(size_t Size) SmallVectorBase(void *FirstEl, size_t Size)
: BeginX(&FirstEl), EndX(&FirstEl), CapacityX((char*)&FirstEl+Size) {} : BeginX(FirstEl), EndX(FirstEl), CapacityX((char*)FirstEl+Size) {}
/// isSmall - Return true if this is a smallvector which has not had dyna
mic
/// memory allocated for it.
bool isSmall() const {
return BeginX == static_cast<const void*>(&FirstEl);
}
/// grow_pod - This is an implementation of the grow() method which only works /// grow_pod - This is an implementation of the grow() method which only works
/// on POD-like data types and is out of line to reduce code duplication. /// on POD-like data types and is out of line to reduce code duplication.
void grow_pod(size_t MinSizeInBytes, size_t TSize); void grow_pod(void *FirstEl, size_t MinSizeInBytes, size_t TSize);
public: public:
/// size_in_bytes - This returns size()*sizeof(T). /// size_in_bytes - This returns size()*sizeof(T).
size_t size_in_bytes() const { size_t size_in_bytes() const {
return size_t((char*)EndX - (char*)BeginX); return size_t((char*)EndX - (char*)BeginX);
} }
/// capacity_in_bytes - This returns capacity()*sizeof(T). /// capacity_in_bytes - This returns capacity()*sizeof(T).
size_t capacity_in_bytes() const { size_t capacity_in_bytes() const {
return size_t((char*)CapacityX - (char*)BeginX); return size_t((char*)CapacityX - (char*)BeginX);
} }
bool empty() const { return BeginX == EndX; } bool empty() const { return BeginX == EndX; }
}; };
template <typename T> template <typename T, unsigned N> struct SmallVectorStorage;
/// SmallVectorTemplateCommon - This is the part of SmallVectorTemplateBase
/// which does not depend on whether the type T is a POD. The extra dummy
/// template argument is used by ArrayRef to avoid unnecessarily requiring
T
/// to be complete.
template <typename T, typename = void>
class SmallVectorTemplateCommon : public SmallVectorBase { class SmallVectorTemplateCommon : public SmallVectorBase {
private:
template <typename, unsigned> friend struct SmallVectorStorage;
// Allocate raw space for N elements of type T. If T has a ctor or dtor,
we
// don't want it to be automatically run, so we need to represent the spa
ce as
// something else. Use an array of char of sufficient alignment.
typedef llvm::AlignedCharArrayUnion<T> U;
U FirstEl;
// Space after 'FirstEl' is clobbered, do not add any instance vars after
it.
protected: protected:
SmallVectorTemplateCommon(size_t Size) : SmallVectorBase(Size) {} SmallVectorTemplateCommon(size_t Size) : SmallVectorBase(&FirstEl, Size)
{}
void grow_pod(size_t MinSizeInBytes, size_t TSize) {
SmallVectorBase::grow_pod(&FirstEl, MinSizeInBytes, TSize);
}
/// isSmall - Return true if this is a smallvector which has not had dyna
mic
/// memory allocated for it.
bool isSmall() const {
return BeginX == static_cast<const void*>(&FirstEl);
}
/// resetToSmall - Put this vector in a state of being small.
void resetToSmall() {
BeginX = EndX = CapacityX = &FirstEl;
}
void setEnd(T *P) { this->EndX = P; } void setEnd(T *P) { this->EndX = P; }
public: public:
typedef size_t size_type; typedef size_t size_type;
typedef ptrdiff_t difference_type; typedef ptrdiff_t difference_type;
typedef T value_type; typedef T value_type;
typedef T *iterator; typedef T *iterator;
typedef const T *const_iterator; typedef const T *const_iterator;
typedef std::reverse_iterator<const_iterator> const_reverse_iterator; typedef std::reverse_iterator<const_iterator> const_reverse_iterator;
skipping to change at line 162 skipping to change at line 176
protected: protected:
SmallVectorTemplateBase(size_t Size) : SmallVectorTemplateCommon<T>(Size) {} SmallVectorTemplateBase(size_t Size) : SmallVectorTemplateCommon<T>(Size) {}
static void destroy_range(T *S, T *E) { static void destroy_range(T *S, T *E) {
while (S != E) { while (S != E) {
--E; --E;
E->~T(); E->~T();
} }
} }
/// uninitialized_copy - Copy the range [I, E) onto the uninitialized mem /// move - Use move-assignment to move the range [I, E) onto the
ory /// objects starting with "Dest". This is just <memory>'s
/// starting with "Dest", constructing elements into it as needed. /// std::move, but not all stdlibs actually provide that.
template<typename It1, typename It2>
static It2 move(It1 I, It1 E, It2 Dest) {
#if LLVM_USE_RVALUE_REFERENCES
for (; I != E; ++I, ++Dest)
*Dest = ::std::move(*I);
return Dest;
#else
return ::std::copy(I, E, Dest);
#endif
}
/// move_backward - Use move-assignment to move the range
/// [I, E) onto the objects ending at "Dest", moving objects
/// in reverse order. This is just <algorithm>'s
/// std::move_backward, but not all stdlibs actually provide that.
template<typename It1, typename It2>
static It2 move_backward(It1 I, It1 E, It2 Dest) {
#if LLVM_USE_RVALUE_REFERENCES
while (I != E)
*--Dest = ::std::move(*--E);
return Dest;
#else
return ::std::copy_backward(I, E, Dest);
#endif
}
/// uninitialized_move - Move the range [I, E) into the uninitialized
/// memory starting with "Dest", constructing elements as needed.
template<typename It1, typename It2>
static void uninitialized_move(It1 I, It1 E, It2 Dest) {
#if LLVM_USE_RVALUE_REFERENCES
for (; I != E; ++I, ++Dest)
::new ((void*) &*Dest) T(::std::move(*I));
#else
::std::uninitialized_copy(I, E, Dest);
#endif
}
/// uninitialized_copy - Copy the range [I, E) onto the uninitialized
/// memory starting with "Dest", constructing elements as needed.
template<typename It1, typename It2> template<typename It1, typename It2>
static void uninitialized_copy(It1 I, It1 E, It2 Dest) { static void uninitialized_copy(It1 I, It1 E, It2 Dest) {
std::uninitialized_copy(I, E, Dest); std::uninitialized_copy(I, E, Dest);
} }
/// grow - double the size of the allocated memory, guaranteeing space fo /// grow - Grow the allocated memory (without initializing new
r at /// elements), doubling the size of the allocated memory.
/// least one more element or MinSize if specified. /// Guarantees space for at least one more element, or MinSize more
/// elements if specified.
void grow(size_t MinSize = 0); void grow(size_t MinSize = 0);
public: public:
void push_back(const T &Elt) { void push_back(const T &Elt) {
if (this->EndX < this->CapacityX) { if (this->EndX < this->CapacityX) {
Retry: Retry:
new (this->end()) T(Elt); ::new ((void*) this->end()) T(Elt);
this->setEnd(this->end()+1); this->setEnd(this->end()+1);
return; return;
} }
this->grow(); this->grow();
goto Retry; goto Retry;
} }
#if LLVM_USE_RVALUE_REFERENCES
void push_back(T &&Elt) {
if (this->EndX < this->CapacityX) {
Retry:
::new ((void*) this->end()) T(::std::move(Elt));
this->setEnd(this->end()+1);
return;
}
this->grow();
goto Retry;
}
#endif
void pop_back() { void pop_back() {
this->setEnd(this->end()-1); this->setEnd(this->end()-1);
this->end()->~T(); this->end()->~T();
} }
}; };
// Define this out-of-line to dissuade the C++ compiler from inlining it. // Define this out-of-line to dissuade the C++ compiler from inlining it.
template <typename T, bool isPodLike> template <typename T, bool isPodLike>
void SmallVectorTemplateBase<T, isPodLike>::grow(size_t MinSize) { void SmallVectorTemplateBase<T, isPodLike>::grow(size_t MinSize) {
size_t CurCapacity = this->capacity(); size_t CurCapacity = this->capacity();
size_t CurSize = this->size(); size_t CurSize = this->size();
size_t NewCapacity = 2*CurCapacity + 1; // Always grow, even from zero. size_t NewCapacity = 2*CurCapacity + 1; // Always grow, even from zero.
if (NewCapacity < MinSize) if (NewCapacity < MinSize)
NewCapacity = MinSize; NewCapacity = MinSize;
T *NewElts = static_cast<T*>(malloc(NewCapacity*sizeof(T))); T *NewElts = static_cast<T*>(malloc(NewCapacity*sizeof(T)));
// Copy the elements over. // Move the elements over.
this->uninitialized_copy(this->begin(), this->end(), NewElts); this->uninitialized_move(this->begin(), this->end(), NewElts);
// Destroy the original elements. // Destroy the original elements.
destroy_range(this->begin(), this->end()); destroy_range(this->begin(), this->end());
// If this wasn't grown from the inline copy, deallocate the old space. // If this wasn't grown from the inline copy, deallocate the old space.
if (!this->isSmall()) if (!this->isSmall())
free(this->begin()); free(this->begin());
this->setEnd(NewElts+CurSize); this->setEnd(NewElts+CurSize);
this->BeginX = NewElts; this->BeginX = NewElts;
skipping to change at line 226 skipping to change at line 296
/// SmallVectorTemplateBase<isPodLike = true> - This is where we put method /// SmallVectorTemplateBase<isPodLike = true> - This is where we put method
/// implementations that are designed to work with POD-like T's. /// implementations that are designed to work with POD-like T's.
template <typename T> template <typename T>
class SmallVectorTemplateBase<T, true> : public SmallVectorTemplateCommon<T > { class SmallVectorTemplateBase<T, true> : public SmallVectorTemplateCommon<T > {
protected: protected:
SmallVectorTemplateBase(size_t Size) : SmallVectorTemplateCommon<T>(Size) {} SmallVectorTemplateBase(size_t Size) : SmallVectorTemplateCommon<T>(Size) {}
// No need to do a destroy loop for POD's. // No need to do a destroy loop for POD's.
static void destroy_range(T *, T *) {} static void destroy_range(T *, T *) {}
/// move - Use move-assignment to move the range [I, E) onto the
/// objects starting with "Dest". For PODs, this is just memcpy.
template<typename It1, typename It2>
static It2 move(It1 I, It1 E, It2 Dest) {
return ::std::copy(I, E, Dest);
}
/// move_backward - Use move-assignment to move the range
/// [I, E) onto the objects ending at "Dest", moving objects
/// in reverse order.
template<typename It1, typename It2>
static It2 move_backward(It1 I, It1 E, It2 Dest) {
return ::std::copy_backward(I, E, Dest);
}
/// uninitialized_move - Move the range [I, E) onto the uninitialized mem
ory
/// starting with "Dest", constructing elements into it as needed.
template<typename It1, typename It2>
static void uninitialized_move(It1 I, It1 E, It2 Dest) {
// Just do a copy.
uninitialized_copy(I, E, Dest);
}
/// uninitialized_copy - Copy the range [I, E) onto the uninitialized mem ory /// uninitialized_copy - Copy the range [I, E) onto the uninitialized mem ory
/// starting with "Dest", constructing elements into it as needed. /// starting with "Dest", constructing elements into it as needed.
template<typename It1, typename It2> template<typename It1, typename It2>
static void uninitialized_copy(It1 I, It1 E, It2 Dest) { static void uninitialized_copy(It1 I, It1 E, It2 Dest) {
// Arbitrary iterator types; just use the basic implementation. // Arbitrary iterator types; just use the basic implementation.
std::uninitialized_copy(I, E, Dest); std::uninitialized_copy(I, E, Dest);
} }
/// uninitialized_copy - Copy the range [I, E) onto the uninitialized mem ory /// uninitialized_copy - Copy the range [I, E) onto the uninitialized mem ory
/// starting with "Dest", constructing elements into it as needed. /// starting with "Dest", constructing elements into it as needed.
skipping to change at line 253 skipping to change at line 346
/// grow - double the size of the allocated memory, guaranteeing space fo r at /// grow - double the size of the allocated memory, guaranteeing space fo r at
/// least one more element or MinSize if specified. /// least one more element or MinSize if specified.
void grow(size_t MinSize = 0) { void grow(size_t MinSize = 0) {
this->grow_pod(MinSize*sizeof(T), sizeof(T)); this->grow_pod(MinSize*sizeof(T), sizeof(T));
} }
public: public:
void push_back(const T &Elt) { void push_back(const T &Elt) {
if (this->EndX < this->CapacityX) { if (this->EndX < this->CapacityX) {
Retry: Retry:
*this->end() = Elt; memcpy(this->end(), &Elt, sizeof(T));
this->setEnd(this->end()+1); this->setEnd(this->end()+1);
return; return;
} }
this->grow(); this->grow();
goto Retry; goto Retry;
} }
void pop_back() { void pop_back() {
this->setEnd(this->end()-1); this->setEnd(this->end()-1);
} }
skipping to change at line 329 skipping to change at line 422
this->setEnd(this->begin()+N); this->setEnd(this->begin()+N);
} }
} }
void reserve(unsigned N) { void reserve(unsigned N) {
if (this->capacity() < N) if (this->capacity() < N)
this->grow(N); this->grow(N);
} }
T pop_back_val() { T pop_back_val() {
#if LLVM_USE_RVALUE_REFERENCES
T Result = ::std::move(this->back());
#else
T Result = this->back(); T Result = this->back();
#endif
this->pop_back(); this->pop_back();
return Result; return Result;
} }
void swap(SmallVectorImpl &RHS); void swap(SmallVectorImpl &RHS);
/// append - Add the specified range to the end of the SmallVector. /// append - Add the specified range to the end of the SmallVector.
/// ///
template<typename in_iter> template<typename in_iter>
void append(in_iter in_start, in_iter in_end) { void append(in_iter in_start, in_iter in_end) {
skipping to change at line 373 skipping to change at line 470
void assign(unsigned NumElts, const T &Elt) { void assign(unsigned NumElts, const T &Elt) {
clear(); clear();
if (this->capacity() < NumElts) if (this->capacity() < NumElts)
this->grow(NumElts); this->grow(NumElts);
this->setEnd(this->begin()+NumElts); this->setEnd(this->begin()+NumElts);
std::uninitialized_fill(this->begin(), this->end(), Elt); std::uninitialized_fill(this->begin(), this->end(), Elt);
} }
iterator erase(iterator I) { iterator erase(iterator I) {
assert(I >= this->begin() && "Iterator to erase is out of bounds.");
assert(I < this->end() && "Erasing at past-the-end iterator.");
iterator N = I; iterator N = I;
// Shift all elts down one. // Shift all elts down one.
std::copy(I+1, this->end(), I); this->move(I+1, this->end(), I);
// Drop the last elt. // Drop the last elt.
this->pop_back(); this->pop_back();
return(N); return(N);
} }
iterator erase(iterator S, iterator E) { iterator erase(iterator S, iterator E) {
assert(S >= this->begin() && "Range to erase is out of bounds.");
assert(S <= E && "Trying to erase invalid range.");
assert(E <= this->end() && "Trying to erase past the end.");
iterator N = S; iterator N = S;
// Shift all elts down. // Shift all elts down.
iterator I = std::copy(E, this->end(), S); iterator I = this->move(E, this->end(), S);
// Drop the last elts. // Drop the last elts.
this->destroy_range(I, this->end()); this->destroy_range(I, this->end());
this->setEnd(I); this->setEnd(I);
return(N); return(N);
} }
#if LLVM_USE_RVALUE_REFERENCES
iterator insert(iterator I, T &&Elt) {
if (I == this->end()) { // Important special case for empty vector.
this->push_back(::std::move(Elt));
return this->end()-1;
}
assert(I >= this->begin() && "Insertion iterator is out of bounds.");
assert(I <= this->end() && "Inserting past the end of the vector.");
if (this->EndX < this->CapacityX) {
Retry:
::new ((void*) this->end()) T(::std::move(this->back()));
this->setEnd(this->end()+1);
// Push everything else over.
this->move_backward(I, this->end()-1, this->end());
// If we just moved the element we're inserting, be sure to update
// the reference.
T *EltPtr = &Elt;
if (I <= EltPtr && EltPtr < this->EndX)
++EltPtr;
*I = ::std::move(*EltPtr);
return I;
}
size_t EltNo = I-this->begin();
this->grow();
I = this->begin()+EltNo;
goto Retry;
}
#endif
iterator insert(iterator I, const T &Elt) { iterator insert(iterator I, const T &Elt) {
if (I == this->end()) { // Important special case for empty vector. if (I == this->end()) { // Important special case for empty vector.
this->push_back(Elt); this->push_back(Elt);
return this->end()-1; return this->end()-1;
} }
assert(I >= this->begin() && "Insertion iterator is out of bounds.");
assert(I <= this->end() && "Inserting past the end of the vector.");
if (this->EndX < this->CapacityX) { if (this->EndX < this->CapacityX) {
Retry: Retry:
new (this->end()) T(this->back()); ::new ((void*) this->end()) T(this->back());
this->setEnd(this->end()+1); this->setEnd(this->end()+1);
// Push everything else over. // Push everything else over.
std::copy_backward(I, this->end()-1, this->end()); this->move_backward(I, this->end()-1, this->end());
// If we just moved the element we're inserting, be sure to update // If we just moved the element we're inserting, be sure to update
// the reference. // the reference.
const T *EltPtr = &Elt; const T *EltPtr = &Elt;
if (I <= EltPtr && EltPtr < this->EndX) if (I <= EltPtr && EltPtr < this->EndX)
++EltPtr; ++EltPtr;
*I = *EltPtr; *I = *EltPtr;
return I; return I;
} }
size_t EltNo = I-this->begin(); size_t EltNo = I-this->begin();
this->grow(); this->grow();
I = this->begin()+EltNo; I = this->begin()+EltNo;
goto Retry; goto Retry;
} }
iterator insert(iterator I, size_type NumToInsert, const T &Elt) { iterator insert(iterator I, size_type NumToInsert, const T &Elt) {
// Convert iterator to elt# to avoid invalidating iterator when we rese
rve()
size_t InsertElt = I - this->begin();
if (I == this->end()) { // Important special case for empty vector. if (I == this->end()) { // Important special case for empty vector.
append(NumToInsert, Elt); append(NumToInsert, Elt);
return this->end()-1; return this->begin()+InsertElt;
} }
// Convert iterator to elt# to avoid invalidating iterator when we rese assert(I >= this->begin() && "Insertion iterator is out of bounds.");
rve() assert(I <= this->end() && "Inserting past the end of the vector.");
size_t InsertElt = I - this->begin();
// Ensure there is enough space. // Ensure there is enough space.
reserve(static_cast<unsigned>(this->size() + NumToInsert)); reserve(static_cast<unsigned>(this->size() + NumToInsert));
// Uninvalidate the iterator. // Uninvalidate the iterator.
I = this->begin()+InsertElt; I = this->begin()+InsertElt;
// If there are more elements between the insertion point and the end o f the // If there are more elements between the insertion point and the end o f the
// range than there are being inserted, we can use a simple approach to // range than there are being inserted, we can use a simple approach to
// insertion. Since we already reserved space, we know that this won't // insertion. Since we already reserved space, we know that this won't
// reallocate the vector. // reallocate the vector.
if (size_t(this->end()-I) >= NumToInsert) { if (size_t(this->end()-I) >= NumToInsert) {
T *OldEnd = this->end(); T *OldEnd = this->end();
append(this->end()-NumToInsert, this->end()); append(this->end()-NumToInsert, this->end());
// Copy the existing elements that get replaced. // Copy the existing elements that get replaced.
std::copy_backward(I, OldEnd-NumToInsert, OldEnd); this->move_backward(I, OldEnd-NumToInsert, OldEnd);
std::fill_n(I, NumToInsert, Elt); std::fill_n(I, NumToInsert, Elt);
return I; return I;
} }
// Otherwise, we're inserting more elements than exist already, and we' re // Otherwise, we're inserting more elements than exist already, and we' re
// not inserting at the end. // not inserting at the end.
// Copy over the elements that we're about to overwrite. // Move over the elements that we're about to overwrite.
T *OldEnd = this->end(); T *OldEnd = this->end();
this->setEnd(this->end() + NumToInsert); this->setEnd(this->end() + NumToInsert);
size_t NumOverwritten = OldEnd-I; size_t NumOverwritten = OldEnd-I;
this->uninitialized_copy(I, OldEnd, this->end()-NumOverwritten); this->uninitialized_move(I, OldEnd, this->end()-NumOverwritten);
// Replace the overwritten part. // Replace the overwritten part.
std::fill_n(I, NumOverwritten, Elt); std::fill_n(I, NumOverwritten, Elt);
// Insert the non-overwritten middle part. // Insert the non-overwritten middle part.
std::uninitialized_fill_n(OldEnd, NumToInsert-NumOverwritten, Elt); std::uninitialized_fill_n(OldEnd, NumToInsert-NumOverwritten, Elt);
return I; return I;
} }
template<typename ItTy> template<typename ItTy>
iterator insert(iterator I, ItTy From, ItTy To) { iterator insert(iterator I, ItTy From, ItTy To) {
// Convert iterator to elt# to avoid invalidating iterator when we rese
rve()
size_t InsertElt = I - this->begin();
if (I == this->end()) { // Important special case for empty vector. if (I == this->end()) { // Important special case for empty vector.
append(From, To); append(From, To);
return this->end()-1; return this->begin()+InsertElt;
} }
assert(I >= this->begin() && "Insertion iterator is out of bounds.");
assert(I <= this->end() && "Inserting past the end of the vector.");
size_t NumToInsert = std::distance(From, To); size_t NumToInsert = std::distance(From, To);
// Convert iterator to elt# to avoid invalidating iterator when we rese
rve()
size_t InsertElt = I - this->begin();
// Ensure there is enough space. // Ensure there is enough space.
reserve(static_cast<unsigned>(this->size() + NumToInsert)); reserve(static_cast<unsigned>(this->size() + NumToInsert));
// Uninvalidate the iterator. // Uninvalidate the iterator.
I = this->begin()+InsertElt; I = this->begin()+InsertElt;
// If there are more elements between the insertion point and the end o f the // If there are more elements between the insertion point and the end o f the
// range than there are being inserted, we can use a simple approach to // range than there are being inserted, we can use a simple approach to
// insertion. Since we already reserved space, we know that this won't // insertion. Since we already reserved space, we know that this won't
// reallocate the vector. // reallocate the vector.
if (size_t(this->end()-I) >= NumToInsert) { if (size_t(this->end()-I) >= NumToInsert) {
T *OldEnd = this->end(); T *OldEnd = this->end();
append(this->end()-NumToInsert, this->end()); append(this->end()-NumToInsert, this->end());
// Copy the existing elements that get replaced. // Copy the existing elements that get replaced.
std::copy_backward(I, OldEnd-NumToInsert, OldEnd); this->move_backward(I, OldEnd-NumToInsert, OldEnd);
std::copy(From, To, I); std::copy(From, To, I);
return I; return I;
} }
// Otherwise, we're inserting more elements than exist already, and we' re // Otherwise, we're inserting more elements than exist already, and we' re
// not inserting at the end. // not inserting at the end.
// Copy over the elements that we're about to overwrite. // Move over the elements that we're about to overwrite.
T *OldEnd = this->end(); T *OldEnd = this->end();
this->setEnd(this->end() + NumToInsert); this->setEnd(this->end() + NumToInsert);
size_t NumOverwritten = OldEnd-I; size_t NumOverwritten = OldEnd-I;
this->uninitialized_copy(I, OldEnd, this->end()-NumOverwritten); this->uninitialized_move(I, OldEnd, this->end()-NumOverwritten);
// Replace the overwritten part. // Replace the overwritten part.
for (; NumOverwritten > 0; --NumOverwritten) { for (T *J = I; NumOverwritten > 0; --NumOverwritten) {
*I = *From; *J = *From;
++I; ++From; ++J; ++From;
} }
// Insert the non-overwritten middle part. // Insert the non-overwritten middle part.
this->uninitialized_copy(From, To, OldEnd); this->uninitialized_copy(From, To, OldEnd);
return I; return I;
} }
const SmallVectorImpl SmallVectorImpl &operator=(const SmallVectorImpl &RHS);
&operator=(const SmallVectorImpl &RHS);
#if LLVM_USE_RVALUE_REFERENCES
SmallVectorImpl &operator=(SmallVectorImpl &&RHS);
#endif
bool operator==(const SmallVectorImpl &RHS) const { bool operator==(const SmallVectorImpl &RHS) const {
if (this->size() != RHS.size()) return false; if (this->size() != RHS.size()) return false;
return std::equal(this->begin(), this->end(), RHS.begin()); return std::equal(this->begin(), this->end(), RHS.begin());
} }
bool operator!=(const SmallVectorImpl &RHS) const { bool operator!=(const SmallVectorImpl &RHS) const {
return !(*this == RHS); return !(*this == RHS);
} }
bool operator<(const SmallVectorImpl &RHS) const { bool operator<(const SmallVectorImpl &RHS) const {
return std::lexicographical_compare(this->begin(), this->end(), return std::lexicographical_compare(this->begin(), this->end(),
RHS.begin(), RHS.end()); RHS.begin(), RHS.end());
} }
/// set_size - Set the array size to \arg N, which the current array must /// Set the array size to \p N, which the current array must have enough
have /// capacity for.
/// enough capacity for.
/// ///
/// This does not construct or destroy any elements in the vector. /// This does not construct or destroy any elements in the vector.
/// ///
/// Clients can use this in conjunction with capacity() to write past the end /// Clients can use this in conjunction with capacity() to write past the end
/// of the buffer when they know that more elements are available, and on ly /// of the buffer when they know that more elements are available, and on ly
/// update the size later. This avoids the cost of value initializing ele ments /// update the size later. This avoids the cost of value initializing ele ments
/// which will only be overwritten. /// which will only be overwritten.
void set_size(unsigned N) { void set_size(unsigned N) {
assert(N <= this->capacity()); assert(N <= this->capacity());
this->setEnd(this->begin() + N); this->setEnd(this->begin() + N);
skipping to change at line 588 skipping to change at line 738
} else if (RHS.size() > this->size()) { } else if (RHS.size() > this->size()) {
size_t EltDiff = RHS.size() - this->size(); size_t EltDiff = RHS.size() - this->size();
this->uninitialized_copy(RHS.begin()+NumShared, RHS.end(), this->end()) ; this->uninitialized_copy(RHS.begin()+NumShared, RHS.end(), this->end()) ;
this->setEnd(this->end() + EltDiff); this->setEnd(this->end() + EltDiff);
this->destroy_range(RHS.begin()+NumShared, RHS.end()); this->destroy_range(RHS.begin()+NumShared, RHS.end());
RHS.setEnd(RHS.begin()+NumShared); RHS.setEnd(RHS.begin()+NumShared);
} }
} }
template <typename T> template <typename T>
const SmallVectorImpl<T> &SmallVectorImpl<T>:: SmallVectorImpl<T> &SmallVectorImpl<T>::
operator=(const SmallVectorImpl<T> &RHS) { operator=(const SmallVectorImpl<T> &RHS) {
// Avoid self-assignment. // Avoid self-assignment.
if (this == &RHS) return *this; if (this == &RHS) return *this;
// If we already have sufficient space, assign the common elements, then // If we already have sufficient space, assign the common elements, then
// destroy any excess. // destroy any excess.
size_t RHSSize = RHS.size(); size_t RHSSize = RHS.size();
size_t CurSize = this->size(); size_t CurSize = this->size();
if (CurSize >= RHSSize) { if (CurSize >= RHSSize) {
// Assign common elements. // Assign common elements.
skipping to change at line 615 skipping to change at line 765
// Destroy excess elements. // Destroy excess elements.
this->destroy_range(NewEnd, this->end()); this->destroy_range(NewEnd, this->end());
// Trim. // Trim.
this->setEnd(NewEnd); this->setEnd(NewEnd);
return *this; return *this;
} }
// If we have to grow to have enough elements, destroy the current elemen ts. // If we have to grow to have enough elements, destroy the current elemen ts.
// This allows us to avoid copying them during the grow. // This allows us to avoid copying them during the grow.
// FIXME: don't do this if they're efficiently moveable.
if (this->capacity() < RHSSize) { if (this->capacity() < RHSSize) {
// Destroy current elements. // Destroy current elements.
this->destroy_range(this->begin(), this->end()); this->destroy_range(this->begin(), this->end());
this->setEnd(this->begin()); this->setEnd(this->begin());
CurSize = 0; CurSize = 0;
this->grow(RHSSize); this->grow(RHSSize);
} else if (CurSize) { } else if (CurSize) {
// Otherwise, use assignment for the already-constructed elements. // Otherwise, use assignment for the already-constructed elements.
std::copy(RHS.begin(), RHS.begin()+CurSize, this->begin()); std::copy(RHS.begin(), RHS.begin()+CurSize, this->begin());
} }
// Copy construct the new elements in place. // Copy construct the new elements in place.
this->uninitialized_copy(RHS.begin()+CurSize, RHS.end(), this->uninitialized_copy(RHS.begin()+CurSize, RHS.end(),
this->begin()+CurSize); this->begin()+CurSize);
// Set end. // Set end.
this->setEnd(this->begin()+RHSSize); this->setEnd(this->begin()+RHSSize);
return *this; return *this;
} }
#if LLVM_USE_RVALUE_REFERENCES
template <typename T>
SmallVectorImpl<T> &SmallVectorImpl<T>::operator=(SmallVectorImpl<T> &&RHS)
{
// Avoid self-assignment.
if (this == &RHS) return *this;
// If the RHS isn't small, clear this vector and then steal its buffer.
if (!RHS.isSmall()) {
this->destroy_range(this->begin(), this->end());
if (!this->isSmall()) free(this->begin());
this->BeginX = RHS.BeginX;
this->EndX = RHS.EndX;
this->CapacityX = RHS.CapacityX;
RHS.resetToSmall();
return *this;
}
// If we already have sufficient space, assign the common elements, then
// destroy any excess.
size_t RHSSize = RHS.size();
size_t CurSize = this->size();
if (CurSize >= RHSSize) {
// Assign common elements.
iterator NewEnd = this->begin();
if (RHSSize)
NewEnd = this->move(RHS.begin(), RHS.end(), NewEnd);
// Destroy excess elements and trim the bounds.
this->destroy_range(NewEnd, this->end());
this->setEnd(NewEnd);
// Clear the RHS.
RHS.clear();
return *this;
}
// If we have to grow to have enough elements, destroy the current elemen
ts.
// This allows us to avoid copying them during the grow.
// FIXME: this may not actually make any sense if we can efficiently move
// elements.
if (this->capacity() < RHSSize) {
// Destroy current elements.
this->destroy_range(this->begin(), this->end());
this->setEnd(this->begin());
CurSize = 0;
this->grow(RHSSize);
} else if (CurSize) {
// Otherwise, use assignment for the already-constructed elements.
this->move(RHS.begin(), RHS.end(), this->begin());
}
// Move-construct the new elements in place.
this->uninitialized_move(RHS.begin()+CurSize, RHS.end(),
this->begin()+CurSize);
// Set end.
this->setEnd(this->begin()+RHSSize);
RHS.clear();
return *this;
}
#endif
/// Storage for the SmallVector elements which aren't contained in
/// SmallVectorTemplateCommon. There are 'N-1' elements here. The remaining
'1'
/// element is in the base class. This is specialized for the N=1 and N=0 c
ases
/// to avoid allocating unnecessary storage.
template <typename T, unsigned N>
struct SmallVectorStorage {
typename SmallVectorTemplateCommon<T>::U InlineElts[N - 1];
};
template <typename T> struct SmallVectorStorage<T, 1> {};
template <typename T> struct SmallVectorStorage<T, 0> {};
/// SmallVector - This is a 'vector' (really, a variable-sized array), opti mized /// SmallVector - This is a 'vector' (really, a variable-sized array), opti mized
/// for the case when the array is small. It contains some number of eleme nts /// for the case when the array is small. It contains some number of eleme nts
/// in-place, which allows it to avoid heap allocation when the actual numb er of /// in-place, which allows it to avoid heap allocation when the actual numb er of
/// elements is below that threshold. This allows normal "small" cases to be /// elements is below that threshold. This allows normal "small" cases to be
/// fast without losing generality for large inputs. /// fast without losing generality for large inputs.
/// ///
/// Note that this does not attempt to be exception safe. /// Note that this does not attempt to be exception safe.
/// ///
template <typename T, unsigned N> template <typename T, unsigned N>
class SmallVector : public SmallVectorImpl<T> { class SmallVector : public SmallVectorImpl<T> {
/// InlineElts - These are 'N-1' elements that are stored inline in the b /// Storage - Inline space for elements which aren't stored in the base c
ody lass.
/// of the vector. The extra '1' element is stored in SmallVectorImpl. SmallVectorStorage<T, N> Storage;
typedef typename SmallVectorImpl<T>::U U;
enum {
// MinUs - The number of U's require to cover N T's.
MinUs = (static_cast<unsigned int>(sizeof(T))*N +
static_cast<unsigned int>(sizeof(U)) - 1) /
static_cast<unsigned int>(sizeof(U)),
// NumInlineEltsElts - The number of elements actually in this array.
There
// is already one in the parent class, and we have to round up to avoid
// having a zero-element array.
NumInlineEltsElts = MinUs > 1 ? (MinUs - 1) : 1,
// NumTsAvailable - The number of T's we actually have space for, which
may
// be more than N due to rounding.
NumTsAvailable = (NumInlineEltsElts+1)*static_cast<unsigned int>(sizeof
(U))/
static_cast<unsigned int>(sizeof(T))
};
U InlineElts[NumInlineEltsElts];
public: public:
SmallVector() : SmallVectorImpl<T>(NumTsAvailable) { SmallVector() : SmallVectorImpl<T>(N) {
} }
explicit SmallVector(unsigned Size, const T &Value = T()) explicit SmallVector(unsigned Size, const T &Value = T())
: SmallVectorImpl<T>(NumTsAvailable) { : SmallVectorImpl<T>(N) {
this->assign(Size, Value); this->assign(Size, Value);
} }
template<typename ItTy> template<typename ItTy>
SmallVector(ItTy S, ItTy E) : SmallVectorImpl<T>(NumTsAvailable) { SmallVector(ItTy S, ItTy E) : SmallVectorImpl<T>(N) {
this->append(S, E); this->append(S, E);
} }
SmallVector(const SmallVector &RHS) : SmallVectorImpl<T>(NumTsAvailable) { SmallVector(const SmallVector &RHS) : SmallVectorImpl<T>(N) {
if (!RHS.empty()) if (!RHS.empty())
SmallVectorImpl<T>::operator=(RHS); SmallVectorImpl<T>::operator=(RHS);
} }
const SmallVector &operator=(const SmallVector &RHS) { const SmallVector &operator=(const SmallVector &RHS) {
SmallVectorImpl<T>::operator=(RHS); SmallVectorImpl<T>::operator=(RHS);
return *this; return *this;
} }
}; #if LLVM_USE_RVALUE_REFERENCES
SmallVector(SmallVector &&RHS) : SmallVectorImpl<T>(N) {
/// Specialize SmallVector at N=0. This specialization guarantees if (!RHS.empty())
/// that it can be instantiated at an incomplete T if none of its SmallVectorImpl<T>::operator=(::std::move(RHS));
/// members are required.
template <typename T>
class SmallVector<T,0> : public SmallVectorImpl<T> {
public:
SmallVector() : SmallVectorImpl<T>(0) {}
explicit SmallVector(unsigned Size, const T &Value = T())
: SmallVectorImpl<T>(0) {
this->assign(Size, Value);
}
template<typename ItTy>
SmallVector(ItTy S, ItTy E) : SmallVectorImpl<T>(0) {
this->append(S, E);
}
SmallVector(const SmallVector &RHS) : SmallVectorImpl<T>(0) {
SmallVectorImpl<T>::operator=(RHS);
} }
SmallVector &operator=(const SmallVectorImpl<T> &RHS) { const SmallVector &operator=(SmallVector &&RHS) {
return SmallVectorImpl<T>::operator=(RHS); SmallVectorImpl<T>::operator=(::std::move(RHS));
return *this;
} }
#endif
}; };
template<typename T, unsigned N> template<typename T, unsigned N>
static inline size_t capacity_in_bytes(const SmallVector<T, N> &X) { static inline size_t capacity_in_bytes(const SmallVector<T, N> &X) {
return X.capacity_in_bytes(); return X.capacity_in_bytes();
} }
} // End llvm namespace } // End llvm namespace
 End of changes. 51 change blocks. 
118 lines changed or deleted 310 lines changed or added


 SourceMgr.h   SourceMgr.h 
skipping to change at line 68 skipping to change at line 68
// include files in. // include files in.
std::vector<std::string> IncludeDirectories; std::vector<std::string> IncludeDirectories;
/// LineNoCache - This is a cache for line number queries, its implementa tion /// LineNoCache - This is a cache for line number queries, its implementa tion
/// is really private to SourceMgr.cpp. /// is really private to SourceMgr.cpp.
mutable void *LineNoCache; mutable void *LineNoCache;
DiagHandlerTy DiagHandler; DiagHandlerTy DiagHandler;
void *DiagContext; void *DiagContext;
SourceMgr(const SourceMgr&); // DO NOT IMPLEMENT SourceMgr(const SourceMgr&) LLVM_DELETED_FUNCTION;
void operator=(const SourceMgr&); // DO NOT IMPLEMENT void operator=(const SourceMgr&) LLVM_DELETED_FUNCTION;
public: public:
SourceMgr() : LineNoCache(0), DiagHandler(0), DiagContext(0) {} SourceMgr() : LineNoCache(0), DiagHandler(0), DiagContext(0) {}
~SourceMgr(); ~SourceMgr();
void setIncludeDirs(const std::vector<std::string> &Dirs) { void setIncludeDirs(const std::vector<std::string> &Dirs) {
IncludeDirectories = Dirs; IncludeDirectories = Dirs;
} }
/// setDiagHandler - Specify a diagnostic handler to be invoked every tim e /// setDiagHandler - Specify a diagnostic handler to be invoked every tim e
/// PrintMessage is called. Ctx is passed into the handler when it is inv oked. /// PrintMessage is called. Ctx is passed into the handler when it is inv oked.
skipping to change at line 126 skipping to change at line 126
/// The full path to the included file can be found in IncludedFile. /// The full path to the included file can be found in IncludedFile.
unsigned AddIncludeFile(const std::string &Filename, SMLoc IncludeLoc, unsigned AddIncludeFile(const std::string &Filename, SMLoc IncludeLoc,
std::string &IncludedFile); std::string &IncludedFile);
/// FindBufferContainingLoc - Return the ID of the buffer containing the /// FindBufferContainingLoc - Return the ID of the buffer containing the
/// specified location, returning -1 if not found. /// specified location, returning -1 if not found.
int FindBufferContainingLoc(SMLoc Loc) const; int FindBufferContainingLoc(SMLoc Loc) const;
/// FindLineNumber - Find the line number for the specified location in t he /// FindLineNumber - Find the line number for the specified location in t he
/// specified file. This is not a fast method. /// specified file. This is not a fast method.
unsigned FindLineNumber(SMLoc Loc, int BufferID = -1) const; unsigned FindLineNumber(SMLoc Loc, int BufferID = -1) const {
return getLineAndColumn(Loc, BufferID).first;
}
/// getLineAndColumn - Find the line and column number for the specified
/// location in the specified file. This is not a fast method.
std::pair<unsigned, unsigned>
getLineAndColumn(SMLoc Loc, int BufferID = -1) const;
/// PrintMessage - Emit a message about the specified location with the /// PrintMessage - Emit a message about the specified location with the
/// specified string. /// specified string.
/// ///
/// @param ShowColors - Display colored messages if output is a terminal and /// @param ShowColors - Display colored messages if output is a terminal and
/// the default error handler is used. /// the default error handler is used.
void PrintMessage(SMLoc Loc, DiagKind Kind, const Twine &Msg, void PrintMessage(SMLoc Loc, DiagKind Kind, const Twine &Msg,
ArrayRef<SMRange> Ranges = ArrayRef<SMRange>(), ArrayRef<SMRange> Ranges = ArrayRef<SMRange>(),
bool ShowColors = true) const; bool ShowColors = true) const;
/// GetMessage - Return an SMDiagnostic at the specified location with th e /// GetMessage - Return an SMDiagnostic at the specified location with th e
/// specified string. /// specified string.
/// ///
/// @param Type - If non-null, the kind of message (e.g., "error") which is /// @param Msg If non-null, the kind of message (e.g., "error") which is
/// prefixed to the message. /// prefixed to the message.
SMDiagnostic GetMessage(SMLoc Loc, DiagKind Kind, const Twine &Msg, SMDiagnostic GetMessage(SMLoc Loc, DiagKind Kind, const Twine &Msg,
ArrayRef<SMRange> Ranges = ArrayRef<SMRange>()) c onst; ArrayRef<SMRange> Ranges = ArrayRef<SMRange>()) c onst;
/// PrintIncludeStack - Prints the names of included files and the line o f the /// PrintIncludeStack - Prints the names of included files and the line o f the
/// file they were included from. A diagnostic handler can use this befo re /// file they were included from. A diagnostic handler can use this befo re
/// printing its custom formatted message. /// printing its custom formatted message.
/// ///
/// @param IncludeLoc - The line of the include. /// @param IncludeLoc - The line of the include.
/// @param OS the raw_ostream to print on. /// @param OS the raw_ostream to print on.
skipping to change at line 170 skipping to change at line 177
int LineNo, ColumnNo; int LineNo, ColumnNo;
SourceMgr::DiagKind Kind; SourceMgr::DiagKind Kind;
std::string Message, LineContents; std::string Message, LineContents;
std::vector<std::pair<unsigned, unsigned> > Ranges; std::vector<std::pair<unsigned, unsigned> > Ranges;
public: public:
// Null diagnostic. // Null diagnostic.
SMDiagnostic() SMDiagnostic()
: SM(0), LineNo(0), ColumnNo(0), Kind(SourceMgr::DK_Error) {} : SM(0), LineNo(0), ColumnNo(0), Kind(SourceMgr::DK_Error) {}
// Diagnostic with no location (e.g. file not found, command line arg err or). // Diagnostic with no location (e.g. file not found, command line arg err or).
SMDiagnostic(const std::string &filename, SourceMgr::DiagKind Kind, SMDiagnostic(const std::string &filename, SourceMgr::DiagKind Knd,
const std::string &Msg) const std::string &Msg)
: SM(0), Filename(filename), LineNo(-1), ColumnNo(-1), Kind(Kind), : SM(0), Filename(filename), LineNo(-1), ColumnNo(-1), Kind(Knd),
Message(Msg) {} Message(Msg) {}
// Diagnostic with a location. // Diagnostic with a location.
SMDiagnostic(const SourceMgr &sm, SMLoc L, const std::string &FN, SMDiagnostic(const SourceMgr &sm, SMLoc L, const std::string &FN,
int Line, int Col, SourceMgr::DiagKind Kind, int Line, int Col, SourceMgr::DiagKind Kind,
const std::string &Msg, const std::string &LineStr, const std::string &Msg, const std::string &LineStr,
ArrayRef<std::pair<unsigned,unsigned> > Ranges); ArrayRef<std::pair<unsigned,unsigned> > Ranges);
const SourceMgr *getSourceMgr() const { return SM; } const SourceMgr *getSourceMgr() const { return SM; }
SMLoc getLoc() const { return Loc; } SMLoc getLoc() const { return Loc; }
 End of changes. 5 change blocks. 
6 lines changed or deleted 13 lines changed or added


 SparseBitVector.h   SparseBitVector.h 
skipping to change at line 160 skipping to change at line 160
if (Curr >= BITS_PER_ELEMENT) if (Curr >= BITS_PER_ELEMENT)
return -1; return -1;
unsigned WordPos = Curr / BITWORD_SIZE; unsigned WordPos = Curr / BITWORD_SIZE;
unsigned BitPos = Curr % BITWORD_SIZE; unsigned BitPos = Curr % BITWORD_SIZE;
BitWord Copy = Bits[WordPos]; BitWord Copy = Bits[WordPos];
assert (WordPos <= BITWORDS_PER_ELEMENT assert (WordPos <= BITWORDS_PER_ELEMENT
&& "Word Position outside of element"); && "Word Position outside of element");
// Mask off previous bits. // Mask off previous bits.
Copy &= ~0L << BitPos; Copy &= ~0UL << BitPos;
if (Copy != 0) { if (Copy != 0) {
if (sizeof(BitWord) == 4) if (sizeof(BitWord) == 4)
return WordPos * BITWORD_SIZE + CountTrailingZeros_32(Copy); return WordPos * BITWORD_SIZE + CountTrailingZeros_32(Copy);
if (sizeof(BitWord) == 8) if (sizeof(BitWord) == 8)
return WordPos * BITWORD_SIZE + CountTrailingZeros_64(Copy); return WordPos * BITWORD_SIZE + CountTrailingZeros_64(Copy);
llvm_unreachable("Unsupported!"); llvm_unreachable("Unsupported!");
} }
// Check subsequent words. // Check subsequent words.
skipping to change at line 264 skipping to change at line 264
BecameZero = false; BecameZero = false;
for (unsigned i = 0; i < BITWORDS_PER_ELEMENT; ++i) { for (unsigned i = 0; i < BITWORDS_PER_ELEMENT; ++i) {
Bits[i] = RHS1.Bits[i] & ~RHS2.Bits[i]; Bits[i] = RHS1.Bits[i] & ~RHS2.Bits[i];
if (Bits[i] != 0) if (Bits[i] != 0)
allzero = false; allzero = false;
} }
BecameZero = allzero; BecameZero = allzero;
} }
}; };
template <unsigned ElementSize>
struct ilist_traits<SparseBitVectorElement<ElementSize> >
: public ilist_default_traits<SparseBitVectorElement<ElementSize> > {
typedef SparseBitVectorElement<ElementSize> Element;
Element *createSentinel() const { return static_cast<Element *>(&Sentinel
); }
static void destroySentinel(Element *) {}
Element *provideInitialHead() const { return createSentinel(); }
Element *ensureHead(Element *) const { return createSentinel(); }
static void noteHead(Element *, Element *) {}
private:
mutable ilist_half_node<Element> Sentinel;
};
template <unsigned ElementSize = 128> template <unsigned ElementSize = 128>
class SparseBitVector { class SparseBitVector {
typedef ilist<SparseBitVectorElement<ElementSize> > ElementList; typedef ilist<SparseBitVectorElement<ElementSize> > ElementList;
typedef typename ElementList::iterator ElementListIter; typedef typename ElementList::iterator ElementListIter;
typedef typename ElementList::const_iterator ElementListConstIter; typedef typename ElementList::const_iterator ElementListConstIter;
enum { enum {
BITWORD_SIZE = SparseBitVectorElement<ElementSize>::BITWORD_SIZE BITWORD_SIZE = SparseBitVectorElement<ElementSize>::BITWORD_SIZE
}; };
// Pointer to our current Element. // Pointer to our current Element.
 End of changes. 2 change blocks. 
1 lines changed or deleted 18 lines changed or added


 SparsePropagation.h   SparsePropagation.h 
skipping to change at line 133 skipping to change at line 133
std::vector<Instruction*> InstWorkList; // Worklist of insts to process . std::vector<Instruction*> InstWorkList; // Worklist of insts to process .
std::vector<BasicBlock*> BBWorkList; // The BasicBlock work list std::vector<BasicBlock*> BBWorkList; // The BasicBlock work list
/// KnownFeasibleEdges - Entries in this set are edges which have already had /// KnownFeasibleEdges - Entries in this set are edges which have already had
/// PHI nodes retriggered. /// PHI nodes retriggered.
typedef std::pair<BasicBlock*,BasicBlock*> Edge; typedef std::pair<BasicBlock*,BasicBlock*> Edge;
std::set<Edge> KnownFeasibleEdges; std::set<Edge> KnownFeasibleEdges;
SparseSolver(const SparseSolver&); // DO NOT IMPLEMENT SparseSolver(const SparseSolver&) LLVM_DELETED_FUNCTION;
void operator=(const SparseSolver&); // DO NOT IMPLEMENT void operator=(const SparseSolver&) LLVM_DELETED_FUNCTION;
public: public:
explicit SparseSolver(AbstractLatticeFunction *Lattice) explicit SparseSolver(AbstractLatticeFunction *Lattice)
: LatticeFunc(Lattice) {} : LatticeFunc(Lattice) {}
~SparseSolver() { ~SparseSolver() {
delete LatticeFunc; delete LatticeFunc;
} }
/// Solve - Solve for constants and executable blocks. /// Solve - Solve for constants and executable blocks.
/// ///
void Solve(Function &F); void Solve(Function &F);
 End of changes. 1 change blocks. 
2 lines changed or deleted 2 lines changed or added


 SparseSet.h   SparseSet.h 
skipping to change at line 24 skipping to change at line 24
// A sparse set holds a small number of objects identified by integer keys from // A sparse set holds a small number of objects identified by integer keys from
// a moderately sized universe. The sparse set uses more memory than other // a moderately sized universe. The sparse set uses more memory than other
// containers in order to provide faster operations. // containers in order to provide faster operations.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_ADT_SPARSESET_H #ifndef LLVM_ADT_SPARSESET_H
#define LLVM_ADT_SPARSESET_H #define LLVM_ADT_SPARSESET_H
#include "llvm/ADT/SmallVector.h" #include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/Support/DataTypes.h" #include "llvm/Support/DataTypes.h"
#include <limits> #include <limits>
namespace llvm { namespace llvm {
/// SparseSetFunctor - Objects in a SparseSet are identified by small integ /// SparseSetValTraits - Objects in a SparseSet are identified by keys that
er can
/// keys. A functor object is used to compute the key of an object. The /// be uniquely converted to a small integer less than the set's universe.
/// functor's operator() must return an unsigned smaller than the universe. This
/// class allows the set to hold values that differ from the set's key type
as
/// long as an index can still be derived from the value. SparseSet never
/// directly compares ValueT, only their indices, so it can map keys to
/// arbitrary values. SparseSetValTraits computes the index from the value
/// object. To compute the index from a key, SparseSet uses a separate
/// KeyFunctorT template argument.
///
/// A simple type declaration, SparseSet<Type>, handles these cases:
/// - unsigned key, identity index, identity value
/// - unsigned key, identity index, fat value providing getSparseSetIndex()
///
/// The type declaration SparseSet<Type, UnaryFunction> handles:
/// - unsigned key, remapped index, identity value (virtual registers)
/// - pointer key, pointer-derived index, identity value (node+ID)
/// - pointer key, pointer-derived index, fat value with getSparseSetIndex(
)
/// ///
/// The default functor implementation forwards to a getSparseSetKey() meth /// Only other, unexpected cases require specializing SparseSetValTraits.
od ///
/// on the object. It is intended for sparse sets holding ad-hoc structs. /// For best results, ValueT should not require a destructor.
/// ///
template<typename ValueT> template<typename ValueT>
struct SparseSetFunctor { struct SparseSetValTraits {
unsigned operator()(const ValueT &Val) { static unsigned getValIndex(const ValueT &Val) {
return Val.getSparseSetKey(); return Val.getSparseSetIndex();
} }
}; };
/// SparseSetFunctor<unsigned> - Provide a trivial identity functor for /// SparseSetValFunctor - Helper class for selecting SparseSetValTraits. Th
/// SparseSet<unsigned>. e
/// /// generic implementation handles ValueT classes which either provide
template<> struct SparseSetFunctor<unsigned> { /// getSparseSetIndex() or specialize SparseSetValTraits<>.
unsigned operator()(unsigned Val) { return Val; } ///
template<typename KeyT, typename ValueT, typename KeyFunctorT>
struct SparseSetValFunctor {
unsigned operator()(const ValueT &Val) const {
return SparseSetValTraits<ValueT>::getValIndex(Val);
}
};
/// SparseSetValFunctor<KeyT, KeyT> - Helper class for the common case of
/// identity key/value sets.
template<typename KeyT, typename KeyFunctorT>
struct SparseSetValFunctor<KeyT, KeyT, KeyFunctorT> {
unsigned operator()(const KeyT &Key) const {
return KeyFunctorT()(Key);
}
}; };
/// SparseSet - Fast set implementation for objects that can be identified by /// SparseSet - Fast set implmentation for objects that can be identified b y
/// small unsigned keys. /// small unsigned keys.
/// ///
/// SparseSet allocates memory proportional to the size of the key universe , so /// SparseSet allocates memory proportional to the size of the key universe , so
/// it is not recommended for building composite data structures. It is us eful /// it is not recommended for building composite data structures. It is us eful
/// for algorithms that require a single set with fast operations. /// for algorithms that require a single set with fast operations.
/// ///
/// Compared to DenseSet and DenseMap, SparseSet provides constant-time fas t /// Compared to DenseSet and DenseMap, SparseSet provides constant-time fas t
/// clear() and iteration as fast as a vector. The find(), insert(), and /// clear() and iteration as fast as a vector. The find(), insert(), and
/// erase() operations are all constant time, and typically faster than a h ash /// erase() operations are all constant time, and typically faster than a h ash
/// table. The iteration order doesn't depend on numerical key values, it only /// table. The iteration order doesn't depend on numerical key values, it only
skipping to change at line 84 skipping to change at line 113
/// When SparseT is uint32_t, find() only touches 2 cache lines, but the sp arse /// When SparseT is uint32_t, find() only touches 2 cache lines, but the sp arse
/// array uses 4 x Universe bytes. /// array uses 4 x Universe bytes.
/// ///
/// When SparseT is uint8_t (the default), find() touches up to 2+[N/256] c ache /// When SparseT is uint8_t (the default), find() touches up to 2+[N/256] c ache
/// lines, but the sparse array is 4x smaller. N is the number of elements in /// lines, but the sparse array is 4x smaller. N is the number of elements in
/// the set. /// the set.
/// ///
/// For sets that may grow to thousands of elements, SparseT should be set to /// For sets that may grow to thousands of elements, SparseT should be set to
/// uint16_t or uint32_t. /// uint16_t or uint32_t.
/// ///
/// @param ValueT The type of objects in the set. /// @tparam ValueT The type of objects in the set.
/// @param SparseT An unsigned integer type. See above. /// @tparam KeyFunctorT A functor that computes an unsigned index from KeyT
/// @param KeyFunctorT A functor that computes the unsigned key of a ValueT .
. /// @tparam SparseT An unsigned integer type. See above.
/// ///
template<typename ValueT, template<typename ValueT,
typename SparseT = uint8_t, typename KeyFunctorT = llvm::identity<unsigned>,
typename KeyFunctorT = SparseSetFunctor<ValueT> > typename SparseT = uint8_t>
class SparseSet { class SparseSet {
typedef typename KeyFunctorT::argument_type KeyT;
typedef SmallVector<ValueT, 8> DenseT; typedef SmallVector<ValueT, 8> DenseT;
DenseT Dense; DenseT Dense;
SparseT *Sparse; SparseT *Sparse;
unsigned Universe; unsigned Universe;
KeyFunctorT KeyOf; KeyFunctorT KeyIndexOf;
SparseSetValFunctor<KeyT, ValueT, KeyFunctorT> ValIndexOf;
// Disable copy construction and assignment. // Disable copy construction and assignment.
// This data structure is not meant to be used that way. // This data structure is not meant to be used that way.
SparseSet(const SparseSet&); // DO NOT IMPLEMENT. SparseSet(const SparseSet&) LLVM_DELETED_FUNCTION;
SparseSet &operator=(const SparseSet&); // DO NOT IMPLEMENT. SparseSet &operator=(const SparseSet&) LLVM_DELETED_FUNCTION;
public: public:
typedef ValueT value_type; typedef ValueT value_type;
typedef ValueT &reference; typedef ValueT &reference;
typedef const ValueT &const_reference; typedef const ValueT &const_reference;
typedef ValueT *pointer; typedef ValueT *pointer;
typedef const ValueT *const_pointer; typedef const ValueT *const_pointer;
SparseSet() : Sparse(0), Universe(0) {} SparseSet() : Sparse(0), Universe(0) {}
~SparseSet() { free(Sparse); } ~SparseSet() { free(Sparse); }
skipping to change at line 163 skipping to change at line 194
/// ///
unsigned size() const { return Dense.size(); } unsigned size() const { return Dense.size(); }
/// clear - Clears the set. This is a very fast constant time operation. /// clear - Clears the set. This is a very fast constant time operation.
/// ///
void clear() { void clear() {
// Sparse does not need to be cleared, see find(). // Sparse does not need to be cleared, see find().
Dense.clear(); Dense.clear();
} }
/// find - Find an element by its key. /// findIndex - Find an element by its index.
/// ///
/// @param Key A valid key to find. /// @param Idx A valid index to find.
/// @returns An iterator to the element identified by key, or end(). /// @returns An iterator to the element identified by key, or end().
/// ///
iterator find(unsigned Key) { iterator findIndex(unsigned Idx) {
assert(Key < Universe && "Key out of range"); assert(Idx < Universe && "Key out of range");
assert(std::numeric_limits<SparseT>::is_integer && assert(std::numeric_limits<SparseT>::is_integer &&
!std::numeric_limits<SparseT>::is_signed && !std::numeric_limits<SparseT>::is_signed &&
"SparseT must be an unsigned integer type"); "SparseT must be an unsigned integer type");
const unsigned Stride = std::numeric_limits<SparseT>::max() + 1u; const unsigned Stride = std::numeric_limits<SparseT>::max() + 1u;
for (unsigned i = Sparse[Key], e = size(); i < e; i += Stride) { for (unsigned i = Sparse[Idx], e = size(); i < e; i += Stride) {
const unsigned FoundKey = KeyOf(Dense[i]); const unsigned FoundIdx = ValIndexOf(Dense[i]);
assert(FoundKey < Universe && "Invalid key in set. Did object mutate? assert(FoundIdx < Universe && "Invalid key in set. Did object mutate?
"); ");
if (Key == FoundKey) if (Idx == FoundIdx)
return begin() + i; return begin() + i;
// Stride is 0 when SparseT >= unsigned. We don't need to loop. // Stride is 0 when SparseT >= unsigned. We don't need to loop.
if (!Stride) if (!Stride)
break; break;
} }
return end(); return end();
} }
const_iterator find(unsigned Key) const { /// find - Find an element by its key.
return const_cast<SparseSet*>(this)->find(Key); ///
/// @param Key A valid key to find.
/// @returns An iterator to the element identified by key, or end().
///
iterator find(const KeyT &Key) {
return findIndex(KeyIndexOf(Key));
}
const_iterator find(const KeyT &Key) const {
return const_cast<SparseSet*>(this)->findIndex(KeyIndexOf(Key));
} }
/// count - Returns true if this set contains an element identified by Ke y. /// count - Returns true if this set contains an element identified by Ke y.
/// ///
bool count(unsigned Key) const { bool count(const KeyT &Key) const {
return find(Key) != end(); return find(Key) != end();
} }
/// insert - Attempts to insert a new element. /// insert - Attempts to insert a new element.
/// ///
/// If Val is successfully inserted, return (I, true), where I is an iter ator /// If Val is successfully inserted, return (I, true), where I is an iter ator
/// pointing to the newly inserted element. /// pointing to the newly inserted element.
/// ///
/// If the set already contains an element with the same key as Val, retu rn /// If the set already contains an element with the same key as Val, retu rn
/// (I, false), where I is an iterator pointing to the existing element. /// (I, false), where I is an iterator pointing to the existing element.
/// ///
/// Insertion invalidates all iterators. /// Insertion invalidates all iterators.
/// ///
std::pair<iterator, bool> insert(const ValueT &Val) { std::pair<iterator, bool> insert(const ValueT &Val) {
unsigned Key = KeyOf(Val); unsigned Idx = ValIndexOf(Val);
iterator I = find(Key); iterator I = findIndex(Idx);
if (I != end()) if (I != end())
return std::make_pair(I, false); return std::make_pair(I, false);
Sparse[Key] = size(); Sparse[Idx] = size();
Dense.push_back(Val); Dense.push_back(Val);
return std::make_pair(end() - 1, true); return std::make_pair(end() - 1, true);
} }
/// array subscript - If an element already exists with this key, return it. /// array subscript - If an element already exists with this key, return it.
/// Otherwise, automatically construct a new value from Key, insert it, /// Otherwise, automatically construct a new value from Key, insert it,
/// and return the newly inserted element. /// and return the newly inserted element.
ValueT &operator[](unsigned Key) { ValueT &operator[](const KeyT &Key) {
return *insert(ValueT(Key)).first; return *insert(ValueT(Key)).first;
} }
/// erase - Erases an existing element identified by a valid iterator. /// erase - Erases an existing element identified by a valid iterator.
/// ///
/// This invalidates all iterators, but erase() returns an iterator point ing /// This invalidates all iterators, but erase() returns an iterator point ing
/// to the next element. This makes it possible to erase selected elemen ts /// to the next element. This makes it possible to erase selected elemen ts
/// while iterating over the set: /// while iterating over the set:
/// ///
/// for (SparseSet::iterator I = Set.begin(); I != Set.end();) /// for (SparseSet::iterator I = Set.begin(); I != Set.end();)
skipping to change at line 241 skipping to change at line 281
/// I = Set.erase(I); /// I = Set.erase(I);
/// else /// else
/// ++I; /// ++I;
/// ///
/// Note that end() changes when elements are erased, unlike std::list. /// Note that end() changes when elements are erased, unlike std::list.
/// ///
iterator erase(iterator I) { iterator erase(iterator I) {
assert(unsigned(I - begin()) < size() && "Invalid iterator"); assert(unsigned(I - begin()) < size() && "Invalid iterator");
if (I != end() - 1) { if (I != end() - 1) {
*I = Dense.back(); *I = Dense.back();
unsigned BackKey = KeyOf(Dense.back()); unsigned BackIdx = ValIndexOf(Dense.back());
assert(BackKey < Universe && "Invalid key in set. Did object mutate?" assert(BackIdx < Universe && "Invalid key in set. Did object mutate?"
); );
Sparse[BackKey] = I - begin(); Sparse[BackIdx] = I - begin();
} }
// This depends on SmallVector::pop_back() not invalidating iterators. // This depends on SmallVector::pop_back() not invalidating iterators.
// std::vector::pop_back() doesn't give that guarantee. // std::vector::pop_back() doesn't give that guarantee.
Dense.pop_back(); Dense.pop_back();
return I; return I;
} }
/// erase - Erases an element identified by Key, if it exists. /// erase - Erases an element identified by Key, if it exists.
/// ///
/// @param Key The key identifying the element to erase. /// @param Key The key identifying the element to erase.
/// @returns True when an element was erased, false if no element was fou nd. /// @returns True when an element was erased, false if no element was fou nd.
/// ///
bool erase(unsigned Key) { bool erase(const KeyT &Key) {
iterator I = find(Key); iterator I = find(Key);
if (I == end()) if (I == end())
return false; return false;
erase(I); erase(I);
return true; return true;
} }
}; };
} // end namespace llvm } // end namespace llvm
 End of changes. 22 change blocks. 
46 lines changed or deleted 89 lines changed or added


 StreamableMemoryObject.h   StreamableMemoryObject.h 
skipping to change at line 14 skipping to change at line 14
// //
// This file is distributed under the University of Illinois Open Source // This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details. // License. See LICENSE.TXT for details.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef STREAMABLEMEMORYOBJECT_H_ #ifndef STREAMABLEMEMORYOBJECT_H_
#define STREAMABLEMEMORYOBJECT_H_ #define STREAMABLEMEMORYOBJECT_H_
#include "llvm/ADT/OwningPtr.h" #include "llvm/ADT/OwningPtr.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/MemoryObject.h" #include "llvm/Support/MemoryObject.h"
#include "llvm/Support/DataStream.h" #include "llvm/Support/DataStream.h"
#include <vector> #include <vector>
namespace llvm { namespace llvm {
/// StreamableMemoryObject - Interface to data which might be streamed. /// StreamableMemoryObject - Interface to data which might be streamed.
/// Streamability has 2 important implications/restrictions. First, the dat a /// Streamability has 2 important implications/restrictions. First, the dat a
/// might not yet exist in memory when the request is made. This just means /// might not yet exist in memory when the request is made. This just means
/// that readByte/readBytes might have to block or do some work to get it. /// that readByte/readBytes might have to block or do some work to get it.
skipping to change at line 109 skipping to change at line 110
virtual bool isObjectEnd(uint64_t address) const = 0; virtual bool isObjectEnd(uint64_t address) const = 0;
}; };
/// StreamingMemoryObject - interface to data which is actually streamed fr om /// StreamingMemoryObject - interface to data which is actually streamed fr om
/// a DataStreamer. In addition to inherited members, it has the /// a DataStreamer. In addition to inherited members, it has the
/// dropLeadingBytes and setKnownObjectSize methods which are not applicabl e /// dropLeadingBytes and setKnownObjectSize methods which are not applicabl e
/// to non-streamed objects. /// to non-streamed objects.
class StreamingMemoryObject : public StreamableMemoryObject { class StreamingMemoryObject : public StreamableMemoryObject {
public: public:
StreamingMemoryObject(DataStreamer *streamer); StreamingMemoryObject(DataStreamer *streamer);
virtual uint64_t getBase() const { return 0; } virtual uint64_t getBase() const LLVM_OVERRIDE { return 0; }
virtual uint64_t getExtent() const; virtual uint64_t getExtent() const LLVM_OVERRIDE;
virtual int readByte(uint64_t address, uint8_t* ptr) const; virtual int readByte(uint64_t address, uint8_t* ptr) const LLVM_OVERRIDE;
virtual int readBytes(uint64_t address, virtual int readBytes(uint64_t address,
uint64_t size, uint64_t size,
uint8_t* buf, uint8_t* buf,
uint64_t* copied) const ; uint64_t* copied) const LLVM_OVERRIDE;
virtual const uint8_t *getPointer(uint64_t address, uint64_t size) const virtual const uint8_t *getPointer(uint64_t address,
{ uint64_t size) const LLVM_OVERRIDE {
// This could be fixed by ensuring the bytes are fetched and making a c opy, // This could be fixed by ensuring the bytes are fetched and making a c opy,
// requiring that the bitcode size be known, or otherwise ensuring that // requiring that the bitcode size be known, or otherwise ensuring that
// the memory doesn't go away/get reallocated, but it's // the memory doesn't go away/get reallocated, but it's
// not currently necessary. Users that need the pointer don't stream. // not currently necessary. Users that need the pointer don't stream.
assert(0 && "getPointer in streaming memory objects not allowed"); assert(0 && "getPointer in streaming memory objects not allowed");
return NULL; return NULL;
} }
virtual bool isValidAddress(uint64_t address) const; virtual bool isValidAddress(uint64_t address) const LLVM_OVERRIDE;
virtual bool isObjectEnd(uint64_t address) const; virtual bool isObjectEnd(uint64_t address) const LLVM_OVERRIDE;
/// Drop s bytes from the front of the stream, pushing the positions of t he /// Drop s bytes from the front of the stream, pushing the positions of t he
/// remaining bytes down by s. This is used to skip past the bitcode head er, /// remaining bytes down by s. This is used to skip past the bitcode head er,
/// since we don't know a priori if it's present, and we can't put bytes /// since we don't know a priori if it's present, and we can't put bytes
/// back into the stream once we've read them. /// back into the stream once we've read them.
bool dropLeadingBytes(size_t s); bool dropLeadingBytes(size_t s);
/// If the data object size is known in advance, many of the operations c an /// If the data object size is known in advance, many of the operations c an
/// be made more efficient, so this method should be called before readin g /// be made more efficient, so this method should be called before readin g
/// starts (although it can be called anytime). /// starts (although it can be called anytime).
skipping to change at line 172 skipping to change at line 174
if (BytesRead <= Pos) { // reached EOF/ran out of bytes if (BytesRead <= Pos) { // reached EOF/ran out of bytes
ObjectSize = BytesRead; ObjectSize = BytesRead;
EOFReached = true; EOFReached = true;
return false; return false;
} }
} }
} }
return true; return true;
} }
StreamingMemoryObject(const StreamingMemoryObject&); // DO NOT IMPLEMENT StreamingMemoryObject(const StreamingMemoryObject&) LLVM_DELETED_FUNCTION
void operator=(const StreamingMemoryObject&); // DO NOT IMPLEMENT ;
void operator=(const StreamingMemoryObject&) LLVM_DELETED_FUNCTION;
}; };
StreamableMemoryObject *getNonStreamedMemoryObject( StreamableMemoryObject *getNonStreamedMemoryObject(
const unsigned char *Start, const unsigned char *End); const unsigned char *Start, const unsigned char *End);
} }
#endif // STREAMABLEMEMORYOBJECT_H_ #endif // STREAMABLEMEMORYOBJECT_H_
 End of changes. 5 change blocks. 
10 lines changed or deleted 12 lines changed or added


 StringExtras.h   StringExtras.h 
skipping to change at line 24 skipping to change at line 24
#ifndef LLVM_ADT_STRINGEXTRAS_H #ifndef LLVM_ADT_STRINGEXTRAS_H
#define LLVM_ADT_STRINGEXTRAS_H #define LLVM_ADT_STRINGEXTRAS_H
#include "llvm/Support/DataTypes.h" #include "llvm/Support/DataTypes.h"
#include "llvm/ADT/StringRef.h" #include "llvm/ADT/StringRef.h"
namespace llvm { namespace llvm {
template<typename T> class SmallVectorImpl; template<typename T> class SmallVectorImpl;
/// hexdigit - Return the hexadecimal character for the /// hexdigit - Return the hexadecimal character for the
/// given number \arg X (which should be less than 16). /// given number \p X (which should be less than 16).
static inline char hexdigit(unsigned X, bool LowerCase = false) { static inline char hexdigit(unsigned X, bool LowerCase = false) {
const char HexChar = LowerCase ? 'a' : 'A'; const char HexChar = LowerCase ? 'a' : 'A';
return X < 10 ? '0' + X : HexChar + X - 10; return X < 10 ? '0' + X : HexChar + X - 10;
} }
/// utohex_buffer - Emit the specified number into the buffer specified by /// utohex_buffer - Emit the specified number into the buffer specified by
/// BufferEnd, returning a pointer to the start of the string. This can be used /// BufferEnd, returning a pointer to the start of the string. This can be used
/// like this: (note that the buffer must be large enough to handle any num ber): /// like this: (note that the buffer must be large enough to handle any num ber):
/// char Buffer[40]; /// char Buffer[40];
/// printf("0x%s", utohex_buffer(X, Buffer+40)); /// printf("0x%s", utohex_buffer(X, Buffer+40));
skipping to change at line 127 skipping to change at line 127
/// HashString - Hash function for strings. /// HashString - Hash function for strings.
/// ///
/// This is the Bernstein hash function. /// This is the Bernstein hash function.
// //
// FIXME: Investigate whether a modified bernstein hash function performs // FIXME: Investigate whether a modified bernstein hash function performs
// better: http://eternallyconfuzzled.com/tuts/algorithms/jsw_tut_hashing.a spx // better: http://eternallyconfuzzled.com/tuts/algorithms/jsw_tut_hashing.a spx
// X*33+c -> X*33^c // X*33+c -> X*33^c
static inline unsigned HashString(StringRef Str, unsigned Result = 0) { static inline unsigned HashString(StringRef Str, unsigned Result = 0) {
for (unsigned i = 0, e = Str.size(); i != e; ++i) for (unsigned i = 0, e = Str.size(); i != e; ++i)
Result = Result * 33 + Str[i]; Result = Result * 33 + (unsigned char)Str[i];
return Result; return Result;
} }
/// Returns the English suffix for an ordinal integer (-st, -nd, -rd, -th).
static inline StringRef getOrdinalSuffix(unsigned Val) {
// It is critically important that we do this perfectly for
// user-written sequences with over 100 elements.
switch (Val % 100) {
case 11:
case 12:
case 13:
return "th";
default:
switch (Val % 10) {
case 1: return "st";
case 2: return "nd";
case 3: return "rd";
default: return "th";
}
}
}
} // End llvm namespace } // End llvm namespace
#endif #endif
 End of changes. 3 change blocks. 
2 lines changed or deleted 21 lines changed or added


 StringRef.h   StringRef.h 
skipping to change at line 15 skipping to change at line 15
// This file is distributed under the University of Illinois Open Source // This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details. // License. See LICENSE.TXT for details.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_ADT_STRINGREF_H #ifndef LLVM_ADT_STRINGREF_H
#define LLVM_ADT_STRINGREF_H #define LLVM_ADT_STRINGREF_H
#include "llvm/Support/type_traits.h" #include "llvm/Support/type_traits.h"
#include <algorithm>
#include <cassert> #include <cassert>
#include <cstring> #include <cstring>
#include <limits> #include <limits>
#include <string> #include <string>
#include <utility> #include <utility>
namespace llvm { namespace llvm {
template<typename T> template<typename T>
class SmallVectorImpl; class SmallVectorImpl;
class APInt; class APInt;
skipping to change at line 140 skipping to change at line 141
return (Length == RHS.Length && return (Length == RHS.Length &&
compareMemory(Data, RHS.Data, RHS.Length) == 0); compareMemory(Data, RHS.Data, RHS.Length) == 0);
} }
/// equals_lower - Check for string equality, ignoring case. /// equals_lower - Check for string equality, ignoring case.
bool equals_lower(StringRef RHS) const { bool equals_lower(StringRef RHS) const {
return Length == RHS.Length && compare_lower(RHS) == 0; return Length == RHS.Length && compare_lower(RHS) == 0;
} }
/// compare - Compare two strings; the result is -1, 0, or 1 if this st ring /// compare - Compare two strings; the result is -1, 0, or 1 if this st ring
/// is lexicographically less than, equal to, or greater than the \arg RHS. /// is lexicographically less than, equal to, or greater than the \p RH S.
int compare(StringRef RHS) const { int compare(StringRef RHS) const {
// Check the prefix for a mismatch. // Check the prefix for a mismatch.
if (int Res = compareMemory(Data, RHS.Data, min(Length, RHS.Length))) if (int Res = compareMemory(Data, RHS.Data, min(Length, RHS.Length)))
return Res < 0 ? -1 : 1; return Res < 0 ? -1 : 1;
// Otherwise the prefixes match, so we only need to check the lengths . // Otherwise the prefixes match, so we only need to check the lengths .
if (Length == RHS.Length) if (Length == RHS.Length)
return 0; return 0;
return Length < RHS.Length ? -1 : 1; return Length < RHS.Length ? -1 : 1;
} }
skipping to change at line 207 skipping to change at line 208
/// @{ /// @{
operator std::string() const { operator std::string() const {
return str(); return str();
} }
/// @} /// @}
/// @name String Predicates /// @name String Predicates
/// @{ /// @{
/// startswith - Check if this string starts with the given \arg Prefix . /// Check if this string starts with the given \p Prefix.
bool startswith(StringRef Prefix) const { bool startswith(StringRef Prefix) const {
return Length >= Prefix.Length && return Length >= Prefix.Length &&
compareMemory(Data, Prefix.Data, Prefix.Length) == 0; compareMemory(Data, Prefix.Data, Prefix.Length) == 0;
} }
/// endswith - Check if this string ends with the given \arg Suffix. /// Check if this string ends with the given \p Suffix.
bool endswith(StringRef Suffix) const { bool endswith(StringRef Suffix) const {
return Length >= Suffix.Length && return Length >= Suffix.Length &&
compareMemory(end() - Suffix.Length, Suffix.Data, Suffix.Length) == 0; compareMemory(end() - Suffix.Length, Suffix.Data, Suffix.Length) == 0;
} }
/// @} /// @}
/// @name String Searching /// @name String Searching
/// @{ /// @{
/// find - Search for the first character \arg C in the string. /// Search for the first character \p C in the string.
/// ///
/// \return - The index of the first occurrence of \arg C, or npos if n ot /// \returns The index of the first occurrence of \p C, or npos if not
/// found. /// found.
size_t find(char C, size_t From = 0) const { size_t find(char C, size_t From = 0) const {
for (size_t i = min(From, Length), e = Length; i != e; ++i) for (size_t i = min(From, Length), e = Length; i != e; ++i)
if (Data[i] == C) if (Data[i] == C)
return i; return i;
return npos; return npos;
} }
/// find - Search for the first string \arg Str in the string. /// Search for the first string \p Str in the string.
/// ///
/// \return - The index of the first occurrence of \arg Str, or npos if not /// \returns The index of the first occurrence of \p Str, or npos if no t
/// found. /// found.
size_t find(StringRef Str, size_t From = 0) const; size_t find(StringRef Str, size_t From = 0) const;
/// rfind - Search for the last character \arg C in the string. /// Search for the last character \p C in the string.
/// ///
/// \return - The index of the last occurrence of \arg C, or npos if no t /// \returns The index of the last occurrence of \p C, or npos if not
/// found. /// found.
size_t rfind(char C, size_t From = npos) const { size_t rfind(char C, size_t From = npos) const {
From = min(From, Length); From = min(From, Length);
size_t i = From; size_t i = From;
while (i != 0) { while (i != 0) {
--i; --i;
if (Data[i] == C) if (Data[i] == C)
return i; return i;
} }
return npos; return npos;
} }
/// rfind - Search for the last string \arg Str in the string. /// Search for the last string \p Str in the string.
/// ///
/// \return - The index of the last occurrence of \arg Str, or npos if not /// \returns The index of the last occurrence of \p Str, or npos if not
/// found. /// found.
size_t rfind(StringRef Str) const; size_t rfind(StringRef Str) const;
/// find_first_of - Find the first character in the string that is \arg /// Find the first character in the string that is \p C, or npos if not
C, /// found. Same as find.
/// or npos if not found. Same as find.
size_type find_first_of(char C, size_t From = 0) const { size_type find_first_of(char C, size_t From = 0) const {
return find(C, From); return find(C, From);
} }
/// find_first_of - Find the first character in the string that is in \ /// Find the first character in the string that is in \p Chars, or npos
arg if
/// Chars, or npos if not found. /// not found.
/// ///
/// Note: O(size() + Chars.size()) /// Complexity: O(size() + Chars.size())
size_type find_first_of(StringRef Chars, size_t From = 0) const; size_type find_first_of(StringRef Chars, size_t From = 0) const;
/// find_first_not_of - Find the first character in the string that is /// Find the first character in the string that is not \p C or npos if
not not
/// \arg C or npos if not found. /// found.
size_type find_first_not_of(char C, size_t From = 0) const; size_type find_first_not_of(char C, size_t From = 0) const;
/// find_first_not_of - Find the first character in the string that is /// Find the first character in the string that is not in the string
not /// \p Chars, or npos if not found.
/// in the string \arg Chars, or npos if not found.
/// ///
/// Note: O(size() + Chars.size()) /// Complexity: O(size() + Chars.size())
size_type find_first_not_of(StringRef Chars, size_t From = 0) const; size_type find_first_not_of(StringRef Chars, size_t From = 0) const;
/// find_last_of - Find the last character in the string that is \arg C /// Find the last character in the string that is \p C, or npos if not
, or /// found.
/// npos if not found.
size_type find_last_of(char C, size_t From = npos) const { size_type find_last_of(char C, size_t From = npos) const {
return rfind(C, From); return rfind(C, From);
} }
/// find_last_of - Find the last character in the string that is in \ar /// Find the last character in the string that is in \p C, or npos if n
g C, ot
/// or npos if not found. /// found.
/// ///
/// Note: O(size() + Chars.size()) /// Complexity: O(size() + Chars.size())
size_type find_last_of(StringRef Chars, size_t From = npos) const; size_type find_last_of(StringRef Chars, size_t From = npos) const;
/// Find the last character in the string that is not \p C, or npos if
not
/// found.
size_type find_last_not_of(char C, size_t From = npos) const;
/// Find the last character in the string that is not in \p Chars, or
/// npos if not found.
///
/// Complexity: O(size() + Chars.size())
size_type find_last_not_of(StringRef Chars, size_t From = npos) const;
/// @} /// @}
/// @name Helpful Algorithms /// @name Helpful Algorithms
/// @{ /// @{
/// count - Return the number of occurrences of \arg C in the string. /// Return the number of occurrences of \p C in the string.
size_t count(char C) const { size_t count(char C) const {
size_t Count = 0; size_t Count = 0;
for (size_t i = 0, e = Length; i != e; ++i) for (size_t i = 0, e = Length; i != e; ++i)
if (Data[i] == C) if (Data[i] == C)
++Count; ++Count;
return Count; return Count;
} }
/// count - Return the number of non-overlapped occurrences of \arg Str in /// Return the number of non-overlapped occurrences of \p Str in
/// the string. /// the string.
size_t count(StringRef Str) const; size_t count(StringRef Str) const;
/// getAsInteger - Parse the current string as an integer of the specif /// Parse the current string as an integer of the specified radix. If
ied /// \p Radix is specified as zero, this does radix autosensing using
/// radix. If Radix is specified as zero, this does radix autosensing
using
/// extended C rules: 0 is octal, 0x is hex, 0b is binary. /// extended C rules: 0 is octal, 0x is hex, 0b is binary.
/// ///
/// If the string is invalid or if only a subset of the string is valid , /// If the string is invalid or if only a subset of the string is valid ,
/// this returns true to signify the error. The string is considered /// this returns true to signify the error. The string is considered
/// erroneous if empty or if it overflows T. /// erroneous if empty or if it overflows T.
///
template <typename T> template <typename T>
typename enable_if_c<std::numeric_limits<T>::is_signed, bool>::type typename enable_if_c<std::numeric_limits<T>::is_signed, bool>::type
getAsInteger(unsigned Radix, T &Result) const { getAsInteger(unsigned Radix, T &Result) const {
long long LLVal; long long LLVal;
if (getAsSignedInteger(*this, Radix, LLVal) || if (getAsSignedInteger(*this, Radix, LLVal) ||
static_cast<T>(LLVal) != LLVal) static_cast<T>(LLVal) != LLVal)
return true; return true;
Result = LLVal; Result = LLVal;
return false; return false;
} }
skipping to change at line 342 skipping to change at line 352
typename enable_if_c<!std::numeric_limits<T>::is_signed, bool>::type typename enable_if_c<!std::numeric_limits<T>::is_signed, bool>::type
getAsInteger(unsigned Radix, T &Result) const { getAsInteger(unsigned Radix, T &Result) const {
unsigned long long ULLVal; unsigned long long ULLVal;
if (getAsUnsignedInteger(*this, Radix, ULLVal) || if (getAsUnsignedInteger(*this, Radix, ULLVal) ||
static_cast<T>(ULLVal) != ULLVal) static_cast<T>(ULLVal) != ULLVal)
return true; return true;
Result = ULLVal; Result = ULLVal;
return false; return false;
} }
/// getAsInteger - Parse the current string as an integer of the /// Parse the current string as an integer of the specified \p Radix, o
/// specified radix, or of an autosensed radix if the radix given r of
/// is 0. The current value in Result is discarded, and the /// an autosensed radix if the \p Radix given is 0. The current value
/// storage is changed to be wide enough to store the parsed in
/// integer. /// \p Result is discarded, and the storage is changed to be wide enoug
h to
/// store the parsed integer.
/// ///
/// Returns true if the string does not solely consist of a valid /// \returns true if the string does not solely consist of a valid
/// non-empty number in the appropriate base. /// non-empty number in the appropriate base.
/// ///
/// APInt::fromString is superficially similar but assumes the /// APInt::fromString is superficially similar but assumes the
/// string is well-formed in the given radix. /// string is well-formed in the given radix.
bool getAsInteger(unsigned Radix, APInt &Result) const; bool getAsInteger(unsigned Radix, APInt &Result) const;
/// @} /// @}
/// @name String Operations /// @name String Operations
/// @{ /// @{
// lower - Convert the given ASCII string to lowercase. // Convert the given ASCII string to lowercase.
std::string lower() const; std::string lower() const;
/// upper - Convert the given ASCII string to uppercase. /// Convert the given ASCII string to uppercase.
std::string upper() const; std::string upper() const;
/// @} /// @}
/// @name Substring Operations /// @name Substring Operations
/// @{ /// @{
/// substr - Return a reference to the substring from [Start, Start + N ). /// Return a reference to the substring from [Start, Start + N).
/// ///
/// \param Start - The index of the starting character in the substring ; if /// \param Start The index of the starting character in the substring; if
/// the index is npos or greater than the length of the string then the /// the index is npos or greater than the length of the string then the
/// empty substring will be returned. /// empty substring will be returned.
/// ///
/// \param N - The number of characters to included in the substring. I f N /// \param N The number of characters to included in the substring. If N
/// exceeds the number of characters remaining in the string, the strin g /// exceeds the number of characters remaining in the string, the strin g
/// suffix (starting with \arg Start) will be returned. /// suffix (starting with \p Start) will be returned.
StringRef substr(size_t Start, size_t N = npos) const { StringRef substr(size_t Start, size_t N = npos) const {
Start = min(Start, Length); Start = min(Start, Length);
return StringRef(Data + Start, min(N, Length - Start)); return StringRef(Data + Start, min(N, Length - Start));
} }
/// drop_front - Return a StringRef equal to 'this' but with the first /// Return a StringRef equal to 'this' but with the first \p N elements
/// elements dropped. /// dropped.
StringRef drop_front(unsigned N = 1) const { StringRef drop_front(unsigned N = 1) const {
assert(size() >= N && "Dropping more elements than exist"); assert(size() >= N && "Dropping more elements than exist");
return substr(N); return substr(N);
} }
/// drop_back - Return a StringRef equal to 'this' but with the last /// Return a StringRef equal to 'this' but with the last \p N elements
/// elements dropped. /// dropped.
StringRef drop_back(unsigned N = 1) const { StringRef drop_back(unsigned N = 1) const {
assert(size() >= N && "Dropping more elements than exist"); assert(size() >= N && "Dropping more elements than exist");
return substr(0, size()-N); return substr(0, size()-N);
} }
/// slice - Return a reference to the substring from [Start, End). /// Return a reference to the substring from [Start, End).
/// ///
/// \param Start - The index of the starting character in the substring ; if /// \param Start The index of the starting character in the substring; if
/// the index is npos or greater than the length of the string then the /// the index is npos or greater than the length of the string then the
/// empty substring will be returned. /// empty substring will be returned.
/// ///
/// \param End - The index following the last character to include in t /// \param End The index following the last character to include in the
he /// substring. If this is npos, or less than \p Start, or exceeds the
/// substring. If this is npos, or less than \arg Start, or exceeds the
/// number of characters remaining in the string, the string suffix /// number of characters remaining in the string, the string suffix
/// (starting with \arg Start) will be returned. /// (starting with \p Start) will be returned.
StringRef slice(size_t Start, size_t End) const { StringRef slice(size_t Start, size_t End) const {
Start = min(Start, Length); Start = min(Start, Length);
End = min(max(Start, End), Length); End = min(max(Start, End), Length);
return StringRef(Data + Start, End - Start); return StringRef(Data + Start, End - Start);
} }
/// split - Split into two substrings around the first occurrence of a /// Split into two substrings around the first occurrence of a separato
/// separator character. r
/// character.
/// ///
/// If \arg Separator is in the string, then the result is a pair (LHS, RHS) /// If \p Separator is in the string, then the result is a pair (LHS, R HS)
/// such that (*this == LHS + Separator + RHS) is true and RHS is /// such that (*this == LHS + Separator + RHS) is true and RHS is
/// maximal. If \arg Separator is not in the string, then the result is a /// maximal. If \p Separator is not in the string, then the result is a
/// pair (LHS, RHS) where (*this == LHS) and (RHS == ""). /// pair (LHS, RHS) where (*this == LHS) and (RHS == "").
/// ///
/// \param Separator - The character to split on. /// \param Separator The character to split on.
/// \return - The split substrings. /// \returns The split substrings.
std::pair<StringRef, StringRef> split(char Separator) const { std::pair<StringRef, StringRef> split(char Separator) const {
size_t Idx = find(Separator); size_t Idx = find(Separator);
if (Idx == npos) if (Idx == npos)
return std::make_pair(*this, StringRef()); return std::make_pair(*this, StringRef());
return std::make_pair(slice(0, Idx), slice(Idx+1, npos)); return std::make_pair(slice(0, Idx), slice(Idx+1, npos));
} }
/// split - Split into two substrings around the first occurrence of a /// Split into two substrings around the first occurrence of a separato
/// separator string. r
/// string.
/// ///
/// If \arg Separator is in the string, then the result is a pair (LHS, RHS) /// If \p Separator is in the string, then the result is a pair (LHS, R HS)
/// such that (*this == LHS + Separator + RHS) is true and RHS is /// such that (*this == LHS + Separator + RHS) is true and RHS is
/// maximal. If \arg Separator is not in the string, then the result is a /// maximal. If \p Separator is not in the string, then the result is a
/// pair (LHS, RHS) where (*this == LHS) and (RHS == ""). /// pair (LHS, RHS) where (*this == LHS) and (RHS == "").
/// ///
/// \param Separator - The string to split on. /// \param Separator - The string to split on.
/// \return - The split substrings. /// \return - The split substrings.
std::pair<StringRef, StringRef> split(StringRef Separator) const { std::pair<StringRef, StringRef> split(StringRef Separator) const {
size_t Idx = find(Separator); size_t Idx = find(Separator);
if (Idx == npos) if (Idx == npos)
return std::make_pair(*this, StringRef()); return std::make_pair(*this, StringRef());
return std::make_pair(slice(0, Idx), slice(Idx + Separator.size(), np os)); return std::make_pair(slice(0, Idx), slice(Idx + Separator.size(), np os));
} }
/// split - Split into substrings around the occurrences of a separator /// Split into substrings around the occurrences of a separator string.
/// string.
/// ///
/// Each substring is stored in \arg A. If \arg MaxSplit is >= 0, at mo /// Each substring is stored in \p A. If \p MaxSplit is >= 0, at most
st /// \p MaxSplit splits are done and consequently <= \p MaxSplit
/// \arg MaxSplit splits are done and consequently <= \arg MaxSplit
/// elements are added to A. /// elements are added to A.
/// If \arg KeepEmpty is false, empty strings are not added to \arg A. /// If \p KeepEmpty is false, empty strings are not added to \p A. They
They /// still count when considering \p MaxSplit
/// still count when considering \arg MaxSplit
/// An useful invariant is that /// An useful invariant is that
/// Separator.join(A) == *this if MaxSplit == -1 and KeepEmpty == true /// Separator.join(A) == *this if MaxSplit == -1 and KeepEmpty == true
/// ///
/// \param A - Where to put the substrings. /// \param A - Where to put the substrings.
/// \param Separator - The string to split on. /// \param Separator - The string to split on.
/// \param MaxSplit - The maximum number of times the string is split. /// \param MaxSplit - The maximum number of times the string is split.
/// \param KeepEmpty - True if empty substring should be added. /// \param KeepEmpty - True if empty substring should be added.
void split(SmallVectorImpl<StringRef> &A, void split(SmallVectorImpl<StringRef> &A,
StringRef Separator, int MaxSplit = -1, StringRef Separator, int MaxSplit = -1,
bool KeepEmpty = true) const; bool KeepEmpty = true) const;
/// rsplit - Split into two substrings around the last occurrence of a /// Split into two substrings around the last occurrence of a separator
/// separator character. /// character.
/// ///
/// If \arg Separator is in the string, then the result is a pair (LHS, RHS) /// If \p Separator is in the string, then the result is a pair (LHS, R HS)
/// such that (*this == LHS + Separator + RHS) is true and RHS is /// such that (*this == LHS + Separator + RHS) is true and RHS is
/// minimal. If \arg Separator is not in the string, then the result is a /// minimal. If \p Separator is not in the string, then the result is a
/// pair (LHS, RHS) where (*this == LHS) and (RHS == ""). /// pair (LHS, RHS) where (*this == LHS) and (RHS == "").
/// ///
/// \param Separator - The character to split on. /// \param Separator - The character to split on.
/// \return - The split substrings. /// \return - The split substrings.
std::pair<StringRef, StringRef> rsplit(char Separator) const { std::pair<StringRef, StringRef> rsplit(char Separator) const {
size_t Idx = rfind(Separator); size_t Idx = rfind(Separator);
if (Idx == npos) if (Idx == npos)
return std::make_pair(*this, StringRef()); return std::make_pair(*this, StringRef());
return std::make_pair(slice(0, Idx), slice(Idx+1, npos)); return std::make_pair(slice(0, Idx), slice(Idx+1, npos));
} }
/// Return string with consecutive characters in \p Chars starting from
/// the left removed.
StringRef ltrim(StringRef Chars = " \t\n\v\f\r") const {
return drop_front(std::min(Length, find_first_not_of(Chars)));
}
/// Return string with consecutive characters in \p Chars starting from
/// the right removed.
StringRef rtrim(StringRef Chars = " \t\n\v\f\r") const {
return drop_back(Length - std::min(Length, find_last_not_of(Chars) +
1));
}
/// Return string with consecutive characters in \p Chars starting from
/// the left and right removed.
StringRef trim(StringRef Chars = " \t\n\v\f\r") const {
return ltrim(Chars).rtrim(Chars);
}
/// @} /// @}
}; };
/// @name StringRef Comparison Operators /// @name StringRef Comparison Operators
/// @{ /// @{
inline bool operator==(StringRef LHS, StringRef RHS) { inline bool operator==(StringRef LHS, StringRef RHS) {
return LHS.equals(RHS); return LHS.equals(RHS);
} }
 End of changes. 54 change blocks. 
83 lines changed or deleted 108 lines changed or added


 StringSet.h   StringSet.h 
skipping to change at line 32 skipping to change at line 32
/// functionality. Only insert() and count() methods are used by my /// functionality. Only insert() and count() methods are used by my
/// code. /// code.
template <class AllocatorTy = llvm::MallocAllocator> template <class AllocatorTy = llvm::MallocAllocator>
class StringSet : public llvm::StringMap<char, AllocatorTy> { class StringSet : public llvm::StringMap<char, AllocatorTy> {
typedef llvm::StringMap<char, AllocatorTy> base; typedef llvm::StringMap<char, AllocatorTy> base;
public: public:
bool insert(StringRef InLang) { bool insert(StringRef InLang) {
assert(!InLang.empty()); assert(!InLang.empty());
const char *KeyStart = InLang.data(); const char *KeyStart = InLang.data();
const char *KeyEnd = KeyStart + InLang.size(); const char *KeyEnd = KeyStart + InLang.size();
return base::insert(llvm::StringMapEntry<char>:: llvm::StringMapEntry<char> *Entry = llvm::StringMapEntry<char>::
Create(KeyStart, KeyEnd, base::getAllocator(), '+ Create(KeyStart, KeyEnd, base::getAllocator(),
')); '+');
if (!base::insert(Entry)) {
Entry->Destroy(base::getAllocator());
return false;
}
return true;
} }
}; };
} }
#endif // LLVM_ADT_STRINGSET_H #endif // LLVM_ADT_STRINGSET_H
 End of changes. 1 change blocks. 
3 lines changed or deleted 8 lines changed or added


 StringSwitch.h   StringSwitch.h 
skipping to change at line 51 skipping to change at line 51
template<typename T, typename R = T> template<typename T, typename R = T>
class StringSwitch { class StringSwitch {
/// \brief The string we are matching. /// \brief The string we are matching.
StringRef Str; StringRef Str;
/// \brief The pointer to the result of this switch statement, once known , /// \brief The pointer to the result of this switch statement, once known ,
/// null before that. /// null before that.
const T *Result; const T *Result;
public: public:
explicit StringSwitch(StringRef Str) explicit StringSwitch(StringRef S)
: Str(Str), Result(0) { } : Str(S), Result(0) { }
template<unsigned N> template<unsigned N>
StringSwitch& Case(const char (&S)[N], const T& Value) { StringSwitch& Case(const char (&S)[N], const T& Value) {
if (!Result && N-1 == Str.size() && if (!Result && N-1 == Str.size() &&
(std::memcmp(S, Str.data(), N-1) == 0)) { (std::memcmp(S, Str.data(), N-1) == 0)) {
Result = &Value; Result = &Value;
} }
return *this; return *this;
} }
 End of changes. 1 change blocks. 
2 lines changed or deleted 2 lines changed or added


 SubtargetFeature.h   SubtargetFeature.h 
skipping to change at line 53 skipping to change at line 53
} }
}; };
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
/// ///
/// SubtargetInfoKV - Used to provide key value pairs for CPU and arbitrary /// SubtargetInfoKV - Used to provide key value pairs for CPU and arbitrary
/// pointers. /// pointers.
// //
struct SubtargetInfoKV { struct SubtargetInfoKV {
const char *Key; // K-V key string const char *Key; // K-V key string
void *Value; // K-V pointer value const void *Value; // K-V pointer value
// Compare routine for std binary search // Compare routine for std binary search
bool operator<(const SubtargetInfoKV &S) const { bool operator<(const SubtargetInfoKV &S) const {
return strcmp(Key, S.Key) < 0; return strcmp(Key, S.Key) < 0;
} }
}; };
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
/// ///
/// SubtargetFeatures - Manages the enabling and disabling of subtarget /// SubtargetFeatures - Manages the enabling and disabling of subtarget
skipping to change at line 98 skipping to change at line 98
const SubtargetFeatureKV *FeatureTable, const SubtargetFeatureKV *FeatureTable,
size_t FeatureTableSize); size_t FeatureTableSize);
/// Get feature bits of a CPU. /// Get feature bits of a CPU.
uint64_t getFeatureBits(const StringRef CPU, uint64_t getFeatureBits(const StringRef CPU,
const SubtargetFeatureKV *CPUTable, const SubtargetFeatureKV *CPUTable,
size_t CPUTableSize, size_t CPUTableSize,
const SubtargetFeatureKV *FeatureTable, const SubtargetFeatureKV *FeatureTable,
size_t FeatureTableSize); size_t FeatureTableSize);
/// Get scheduling itinerary of a CPU.
void *getItinerary(const StringRef CPU,
const SubtargetInfoKV *Table, size_t TableSize);
/// Print feature string. /// Print feature string.
void print(raw_ostream &OS) const; void print(raw_ostream &OS) const;
// Dump feature info. // Dump feature info.
void dump() const; void dump() const;
/// Retrieve a formatted string of the default features for the specified /// Retrieve a formatted string of the default features for the specified
/// target triple. /// target triple.
void getDefaultSubtargetFeatures(const Triple& Triple); void getDefaultSubtargetFeatures(const Triple& Triple);
}; };
 End of changes. 2 change blocks. 
5 lines changed or deleted 1 lines changed or added


 SymbolTableListTraits.h   SymbolTableListTraits.h 
skipping to change at line 49 skipping to change at line 49
// //
template<typename ValueSubClass, typename ItemParentClass> template<typename ValueSubClass, typename ItemParentClass>
class SymbolTableListTraits : public ilist_default_traits<ValueSubClass> { class SymbolTableListTraits : public ilist_default_traits<ValueSubClass> {
typedef ilist_traits<ValueSubClass> TraitsClass; typedef ilist_traits<ValueSubClass> TraitsClass;
public: public:
SymbolTableListTraits() {} SymbolTableListTraits() {}
/// getListOwner - Return the object that owns this list. If this is a l ist /// getListOwner - Return the object that owns this list. If this is a l ist
/// of instructions, it returns the BasicBlock that owns them. /// of instructions, it returns the BasicBlock that owns them.
ItemParentClass *getListOwner() { ItemParentClass *getListOwner() {
typedef iplist<ValueSubClass> ItemParentClass::*Sublist;
size_t Offset(size_t(&((ItemParentClass*)0->*ItemParentClass:: size_t Offset(size_t(&((ItemParentClass*)0->*ItemParentClass::
getSublistAccess(static_cast<ValueSubClass*>(0)) ))); getSublistAccess(static_cast<ValueSubClass*>(0)) )));
iplist<ValueSubClass>* Anchor(static_cast<iplist<ValueSubClass>*>(this) ); iplist<ValueSubClass>* Anchor(static_cast<iplist<ValueSubClass>*>(this) );
return reinterpret_cast<ItemParentClass*>(reinterpret_cast<char*>(Ancho r)- return reinterpret_cast<ItemParentClass*>(reinterpret_cast<char*>(Ancho r)-
Offset); Offset);
} }
static iplist<ValueSubClass> &getList(ItemParentClass *Par) { static iplist<ValueSubClass> &getList(ItemParentClass *Par) {
return Par->*(Par->getSublistAccess((ValueSubClass*)0)); return Par->*(Par->getSublistAccess((ValueSubClass*)0));
} }
 End of changes. 1 change blocks. 
1 lines changed or deleted 0 lines changed or added


 TableGenBackend.h   TableGenBackend.h 
//===- llvm/TableGen/TableGenBackend.h - Backend base class -----*- C++ -*- ===// //===- llvm/TableGen/TableGenBackend.h - Backend utilities ------*- C++ -*- ===//
// //
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
// //
// This file is distributed under the University of Illinois Open Source // This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details. // License. See LICENSE.TXT for details.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// //
// The TableGenBackend class is provided as a common interface for all Tabl // Useful utilities for TableGen backends.
eGen
// backends. It provides useful services and an standardized interface.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_TABLEGEN_TABLEGENBACKEND_H #ifndef LLVM_TABLEGEN_TABLEGENBACKEND_H
#define LLVM_TABLEGEN_TABLEGENBACKEND_H #define LLVM_TABLEGEN_TABLEGENBACKEND_H
#include "llvm/Support/raw_ostream.h" #include "llvm/ADT/StringRef.h"
namespace llvm { namespace llvm {
class Record; class raw_ostream;
class RecordKeeper;
struct TableGenBackend { /// emitSourceFileHeader - Output a LLVM style file header to the specified
virtual void anchor(); /// raw_ostream.
virtual ~TableGenBackend() {} void emitSourceFileHeader(StringRef Desc, raw_ostream &OS);
// run - All TableGen backends should implement the run method, which sho
uld
// be the main entry point.
virtual void run(raw_ostream &OS) = 0;
public: // Useful helper routines...
/// EmitSourceFileHeader - Output a LLVM style file header to the specifi
ed
/// ostream.
void EmitSourceFileHeader(StringRef Desc, raw_ostream &OS) const;
};
} // End llvm namespace } // End llvm namespace
#endif #endif
 End of changes. 5 change blocks. 
23 lines changed or deleted 7 lines changed or added


 Target.h   Target.h 
skipping to change at line 59 skipping to change at line 59
#include "llvm/Config/Targets.def" #include "llvm/Config/Targets.def"
#undef LLVM_TARGET /* Explicit undef to make SWIG happier */ #undef LLVM_TARGET /* Explicit undef to make SWIG happier */
#define LLVM_TARGET(TargetName) \ #define LLVM_TARGET(TargetName) \
void LLVMInitialize##TargetName##TargetMC(void); void LLVMInitialize##TargetName##TargetMC(void);
#include "llvm/Config/Targets.def" #include "llvm/Config/Targets.def"
#undef LLVM_TARGET /* Explicit undef to make SWIG happier */ #undef LLVM_TARGET /* Explicit undef to make SWIG happier */
/* Declare all of the available assembly printer initialization functions. */ /* Declare all of the available assembly printer initialization functions. */
#define LLVM_ASM_PRINTER(TargetName) \ #define LLVM_ASM_PRINTER(TargetName) \
void LLVMInitialize##TargetName##AsmPrinter(); void LLVMInitialize##TargetName##AsmPrinter(void);
#include "llvm/Config/AsmPrinters.def" #include "llvm/Config/AsmPrinters.def"
#undef LLVM_ASM_PRINTER /* Explicit undef to make SWIG happier */ #undef LLVM_ASM_PRINTER /* Explicit undef to make SWIG happier */
/* Declare all of the available assembly parser initialization functions. * / /* Declare all of the available assembly parser initialization functions. * /
#define LLVM_ASM_PARSER(TargetName) \ #define LLVM_ASM_PARSER(TargetName) \
void LLVMInitialize##TargetName##AsmParser(); void LLVMInitialize##TargetName##AsmParser(void);
#include "llvm/Config/AsmParsers.def" #include "llvm/Config/AsmParsers.def"
#undef LLVM_ASM_PARSER /* Explicit undef to make SWIG happier */ #undef LLVM_ASM_PARSER /* Explicit undef to make SWIG happier */
/* Declare all of the available disassembler initialization functions. */ /* Declare all of the available disassembler initialization functions. */
#define LLVM_DISASSEMBLER(TargetName) \ #define LLVM_DISASSEMBLER(TargetName) \
void LLVMInitialize##TargetName##Disassembler(); void LLVMInitialize##TargetName##Disassembler(void);
#include "llvm/Config/Disassemblers.def" #include "llvm/Config/Disassemblers.def"
#undef LLVM_DISASSEMBLER /* Explicit undef to make SWIG happier */ #undef LLVM_DISASSEMBLER /* Explicit undef to make SWIG happier */
/** LLVMInitializeAllTargetInfos - The main program should call this functi on if /** LLVMInitializeAllTargetInfos - The main program should call this functi on if
it wants access to all available targets that LLVM is configured to it wants access to all available targets that LLVM is configured to
support. */ support. */
static inline void LLVMInitializeAllTargetInfos(void) { static inline void LLVMInitializeAllTargetInfos(void) {
#define LLVM_TARGET(TargetName) LLVMInitialize##TargetName##TargetInfo(); #define LLVM_TARGET(TargetName) LLVMInitialize##TargetName##TargetInfo();
#include "llvm/Config/Targets.def" #include "llvm/Config/Targets.def"
#undef LLVM_TARGET /* Explicit undef to make SWIG happier */ #undef LLVM_TARGET /* Explicit undef to make SWIG happier */
skipping to change at line 105 skipping to change at line 105
support. */ support. */
static inline void LLVMInitializeAllTargetMCs(void) { static inline void LLVMInitializeAllTargetMCs(void) {
#define LLVM_TARGET(TargetName) LLVMInitialize##TargetName##TargetMC(); #define LLVM_TARGET(TargetName) LLVMInitialize##TargetName##TargetMC();
#include "llvm/Config/Targets.def" #include "llvm/Config/Targets.def"
#undef LLVM_TARGET /* Explicit undef to make SWIG happier */ #undef LLVM_TARGET /* Explicit undef to make SWIG happier */
} }
/** LLVMInitializeAllAsmPrinters - The main program should call this functi on if /** LLVMInitializeAllAsmPrinters - The main program should call this functi on if
it wants all asm printers that LLVM is configured to support, to make t hem it wants all asm printers that LLVM is configured to support, to make t hem
available via the TargetRegistry. */ available via the TargetRegistry. */
static inline void LLVMInitializeAllAsmPrinters() { static inline void LLVMInitializeAllAsmPrinters(void) {
#define LLVM_ASM_PRINTER(TargetName) LLVMInitialize##TargetName##AsmPrinter (); #define LLVM_ASM_PRINTER(TargetName) LLVMInitialize##TargetName##AsmPrinter ();
#include "llvm/Config/AsmPrinters.def" #include "llvm/Config/AsmPrinters.def"
#undef LLVM_ASM_PRINTER /* Explicit undef to make SWIG happier */ #undef LLVM_ASM_PRINTER /* Explicit undef to make SWIG happier */
} }
/** LLVMInitializeAllAsmParsers - The main program should call this functio n if /** LLVMInitializeAllAsmParsers - The main program should call this functio n if
it wants all asm parsers that LLVM is configured to support, to make th em it wants all asm parsers that LLVM is configured to support, to make th em
available via the TargetRegistry. */ available via the TargetRegistry. */
static inline void LLVMInitializeAllAsmParsers() { static inline void LLVMInitializeAllAsmParsers(void) {
#define LLVM_ASM_PARSER(TargetName) LLVMInitialize##TargetName##AsmParser() ; #define LLVM_ASM_PARSER(TargetName) LLVMInitialize##TargetName##AsmParser() ;
#include "llvm/Config/AsmParsers.def" #include "llvm/Config/AsmParsers.def"
#undef LLVM_ASM_PARSER /* Explicit undef to make SWIG happier */ #undef LLVM_ASM_PARSER /* Explicit undef to make SWIG happier */
} }
/** LLVMInitializeAllDisassemblers - The main program should call this func tion /** LLVMInitializeAllDisassemblers - The main program should call this func tion
if it wants all disassemblers that LLVM is configured to support, to ma ke if it wants all disassemblers that LLVM is configured to support, to ma ke
them available via the TargetRegistry. */ them available via the TargetRegistry. */
static inline void LLVMInitializeAllDisassemblers() { static inline void LLVMInitializeAllDisassemblers(void) {
#define LLVM_DISASSEMBLER(TargetName) \ #define LLVM_DISASSEMBLER(TargetName) \
LLVMInitialize##TargetName##Disassembler(); LLVMInitialize##TargetName##Disassembler();
#include "llvm/Config/Disassemblers.def" #include "llvm/Config/Disassemblers.def"
#undef LLVM_DISASSEMBLER /* Explicit undef to make SWIG happier */ #undef LLVM_DISASSEMBLER /* Explicit undef to make SWIG happier */
} }
/** LLVMInitializeNativeTarget - The main program should call this function to /** LLVMInitializeNativeTarget - The main program should call this function to
initialize the native target corresponding to the host. This is useful initialize the native target corresponding to the host. This is useful
for JIT applications to ensure that the target gets linked in correctly . */ for JIT applications to ensure that the target gets linked in correctly . */
static inline LLVMBool LLVMInitializeNativeTarget(void) { static inline LLVMBool LLVMInitializeNativeTarget(void) {
skipping to change at line 148 skipping to change at line 148
LLVM_NATIVE_TARGETMC(); LLVM_NATIVE_TARGETMC();
return 0; return 0;
#else #else
return 1; return 1;
#endif #endif
} }
/*===-- Target Data ------------------------------------------------------- ===*/ /*===-- Target Data ------------------------------------------------------- ===*/
/** Creates target data from a target layout string. /** Creates target data from a target layout string.
See the constructor llvm::TargetData::TargetData. */ See the constructor llvm::DataLayout::DataLayout. */
LLVMTargetDataRef LLVMCreateTargetData(const char *StringRep); LLVMTargetDataRef LLVMCreateTargetData(const char *StringRep);
/** Adds target data information to a pass manager. This does not take owne rship /** Adds target data information to a pass manager. This does not take owne rship
of the target data. of the target data.
See the method llvm::PassManagerBase::add. */ See the method llvm::PassManagerBase::add. */
void LLVMAddTargetData(LLVMTargetDataRef, LLVMPassManagerRef); void LLVMAddTargetData(LLVMTargetDataRef, LLVMPassManagerRef);
/** Adds target library information to a pass manager. This does not take /** Adds target library information to a pass manager. This does not take
ownership of the target library info. ownership of the target library info.
See the method llvm::PassManagerBase::add. */ See the method llvm::PassManagerBase::add. */
void LLVMAddTargetLibraryInfo(LLVMTargetLibraryInfoRef, LLVMPassManagerRef) ; void LLVMAddTargetLibraryInfo(LLVMTargetLibraryInfoRef, LLVMPassManagerRef) ;
/** Converts target data to a target layout string. The string must be disp osed /** Converts target data to a target layout string. The string must be disp osed
with LLVMDisposeMessage. with LLVMDisposeMessage.
See the constructor llvm::TargetData::TargetData. */ See the constructor llvm::DataLayout::DataLayout. */
char *LLVMCopyStringRepOfTargetData(LLVMTargetDataRef); char *LLVMCopyStringRepOfTargetData(LLVMTargetDataRef);
/** Returns the byte order of a target, either LLVMBigEndian or /** Returns the byte order of a target, either LLVMBigEndian or
LLVMLittleEndian. LLVMLittleEndian.
See the method llvm::TargetData::isLittleEndian. */ See the method llvm::DataLayout::isLittleEndian. */
enum LLVMByteOrdering LLVMByteOrder(LLVMTargetDataRef); enum LLVMByteOrdering LLVMByteOrder(LLVMTargetDataRef);
/** Returns the pointer size in bytes for a target. /** Returns the pointer size in bytes for a target.
See the method llvm::TargetData::getPointerSize. */ See the method llvm::DataLayout::getPointerSize. */
unsigned LLVMPointerSize(LLVMTargetDataRef); unsigned LLVMPointerSize(LLVMTargetDataRef);
/** Returns the pointer size in bytes for a target for a specified
address space.
See the method llvm::DataLayout::getPointerSize. */
unsigned LLVMPointerSizeForAS(LLVMTargetDataRef, unsigned AS);
/** Returns the integer type that is the same size as a pointer on a target . /** Returns the integer type that is the same size as a pointer on a target .
See the method llvm::TargetData::getIntPtrType. */ See the method llvm::DataLayout::getIntPtrType. */
LLVMTypeRef LLVMIntPtrType(LLVMTargetDataRef); LLVMTypeRef LLVMIntPtrType(LLVMTargetDataRef);
/** Returns the integer type that is the same size as a pointer on a target
.
This version allows the address space to be specified.
See the method llvm::DataLayout::getIntPtrType. */
LLVMTypeRef LLVMIntPtrTypeForAS(LLVMTargetDataRef, unsigned AS);
/** Computes the size of a type in bytes for a target. /** Computes the size of a type in bytes for a target.
See the method llvm::TargetData::getTypeSizeInBits. */ See the method llvm::DataLayout::getTypeSizeInBits. */
unsigned long long LLVMSizeOfTypeInBits(LLVMTargetDataRef, LLVMTypeRef); unsigned long long LLVMSizeOfTypeInBits(LLVMTargetDataRef, LLVMTypeRef);
/** Computes the storage size of a type in bytes for a target. /** Computes the storage size of a type in bytes for a target.
See the method llvm::TargetData::getTypeStoreSize. */ See the method llvm::DataLayout::getTypeStoreSize. */
unsigned long long LLVMStoreSizeOfType(LLVMTargetDataRef, LLVMTypeRef); unsigned long long LLVMStoreSizeOfType(LLVMTargetDataRef, LLVMTypeRef);
/** Computes the ABI size of a type in bytes for a target. /** Computes the ABI size of a type in bytes for a target.
See the method llvm::TargetData::getTypeAllocSize. */ See the method llvm::DataLayout::getTypeAllocSize. */
unsigned long long LLVMABISizeOfType(LLVMTargetDataRef, LLVMTypeRef); unsigned long long LLVMABISizeOfType(LLVMTargetDataRef, LLVMTypeRef);
/** Computes the ABI alignment of a type in bytes for a target. /** Computes the ABI alignment of a type in bytes for a target.
See the method llvm::TargetData::getTypeABISize. */ See the method llvm::DataLayout::getTypeABISize. */
unsigned LLVMABIAlignmentOfType(LLVMTargetDataRef, LLVMTypeRef); unsigned LLVMABIAlignmentOfType(LLVMTargetDataRef, LLVMTypeRef);
/** Computes the call frame alignment of a type in bytes for a target. /** Computes the call frame alignment of a type in bytes for a target.
See the method llvm::TargetData::getTypeABISize. */ See the method llvm::DataLayout::getTypeABISize. */
unsigned LLVMCallFrameAlignmentOfType(LLVMTargetDataRef, LLVMTypeRef); unsigned LLVMCallFrameAlignmentOfType(LLVMTargetDataRef, LLVMTypeRef);
/** Computes the preferred alignment of a type in bytes for a target. /** Computes the preferred alignment of a type in bytes for a target.
See the method llvm::TargetData::getTypeABISize. */ See the method llvm::DataLayout::getTypeABISize. */
unsigned LLVMPreferredAlignmentOfType(LLVMTargetDataRef, LLVMTypeRef); unsigned LLVMPreferredAlignmentOfType(LLVMTargetDataRef, LLVMTypeRef);
/** Computes the preferred alignment of a global variable in bytes for a ta rget. /** Computes the preferred alignment of a global variable in bytes for a ta rget.
See the method llvm::TargetData::getPreferredAlignment. */ See the method llvm::DataLayout::getPreferredAlignment. */
unsigned LLVMPreferredAlignmentOfGlobal(LLVMTargetDataRef, unsigned LLVMPreferredAlignmentOfGlobal(LLVMTargetDataRef,
LLVMValueRef GlobalVar); LLVMValueRef GlobalVar);
/** Computes the structure element that contains the byte offset for a targ et. /** Computes the structure element that contains the byte offset for a targ et.
See the method llvm::StructLayout::getElementContainingOffset. */ See the method llvm::StructLayout::getElementContainingOffset. */
unsigned LLVMElementAtOffset(LLVMTargetDataRef, LLVMTypeRef StructTy, unsigned LLVMElementAtOffset(LLVMTargetDataRef, LLVMTypeRef StructTy,
unsigned long long Offset); unsigned long long Offset);
/** Computes the byte offset of the indexed struct element for a target. /** Computes the byte offset of the indexed struct element for a target.
See the method llvm::StructLayout::getElementContainingOffset. */ See the method llvm::StructLayout::getElementContainingOffset. */
unsigned long long LLVMOffsetOfElement(LLVMTargetDataRef, LLVMTypeRef Struc tTy, unsigned long long LLVMOffsetOfElement(LLVMTargetDataRef, LLVMTypeRef Struc tTy,
unsigned Element); unsigned Element);
/** Deallocates a TargetData. /** Deallocates a TargetData.
See the destructor llvm::TargetData::~TargetData. */ See the destructor llvm::DataLayout::~DataLayout. */
void LLVMDisposeTargetData(LLVMTargetDataRef); void LLVMDisposeTargetData(LLVMTargetDataRef);
/** /**
* @} * @}
*/ */
#ifdef __cplusplus #ifdef __cplusplus
} }
namespace llvm { namespace llvm {
class TargetData; class DataLayout;
class TargetLibraryInfo; class TargetLibraryInfo;
inline TargetData *unwrap(LLVMTargetDataRef P) { inline DataLayout *unwrap(LLVMTargetDataRef P) {
return reinterpret_cast<TargetData*>(P); return reinterpret_cast<DataLayout*>(P);
} }
inline LLVMTargetDataRef wrap(const TargetData *P) { inline LLVMTargetDataRef wrap(const DataLayout *P) {
return reinterpret_cast<LLVMTargetDataRef>(const_cast<TargetData*>(P)); return reinterpret_cast<LLVMTargetDataRef>(const_cast<DataLayout*>(P));
} }
inline TargetLibraryInfo *unwrap(LLVMTargetLibraryInfoRef P) { inline TargetLibraryInfo *unwrap(LLVMTargetLibraryInfoRef P) {
return reinterpret_cast<TargetLibraryInfo*>(P); return reinterpret_cast<TargetLibraryInfo*>(P);
} }
inline LLVMTargetLibraryInfoRef wrap(const TargetLibraryInfo *P) { inline LLVMTargetLibraryInfoRef wrap(const TargetLibraryInfo *P) {
TargetLibraryInfo *X = const_cast<TargetLibraryInfo*>(P); TargetLibraryInfo *X = const_cast<TargetLibraryInfo*>(P);
return reinterpret_cast<LLVMTargetLibraryInfoRef>(X); return reinterpret_cast<LLVMTargetLibraryInfoRef>(X);
} }
 End of changes. 24 change blocks. 
24 lines changed or deleted 35 lines changed or added


 Target.td   Target.td 
skipping to change at line 31 skipping to change at line 31
class RegisterClass; // Forward def class RegisterClass; // Forward def
// SubRegIndex - Use instances of SubRegIndex to identify subregisters. // SubRegIndex - Use instances of SubRegIndex to identify subregisters.
class SubRegIndex<list<SubRegIndex> comps = []> { class SubRegIndex<list<SubRegIndex> comps = []> {
string Namespace = ""; string Namespace = "";
// ComposedOf - A list of two SubRegIndex instances, [A, B]. // ComposedOf - A list of two SubRegIndex instances, [A, B].
// This indicates that this SubRegIndex is the result of composing A and B. // This indicates that this SubRegIndex is the result of composing A and B.
list<SubRegIndex> ComposedOf = comps; list<SubRegIndex> ComposedOf = comps;
// CoveringSubRegIndices - A list of two or more sub-register indexes tha
t
// cover this sub-register.
//
// This field should normally be left blank as TableGen can infer it.
//
// TableGen automatically detects sub-registers that straddle the registe
rs
// in the SubRegs field of a Register definition. For example:
//
// Q0 = dsub_0 -> D0, dsub_1 -> D1
// Q1 = dsub_0 -> D2, dsub_1 -> D3
// D1_D2 = dsub_0 -> D1, dsub_1 -> D2
// QQ0 = qsub_0 -> Q0, qsub_1 -> Q1
//
// TableGen will infer that D1_D2 is a sub-register of QQ0. It will be gi
ven
// the synthetic index dsub_1_dsub_2 unless some SubRegIndex is defined w
ith
// CoveringSubRegIndices = [dsub_1, dsub_2].
list<SubRegIndex> CoveringSubRegIndices = [];
} }
// RegAltNameIndex - The alternate name set to use for register operands of // RegAltNameIndex - The alternate name set to use for register operands of
// this register class when printing. // this register class when printing.
class RegAltNameIndex { class RegAltNameIndex {
string Namespace = ""; string Namespace = "";
} }
def NoRegAltName : RegAltNameIndex; def NoRegAltName : RegAltNameIndex;
// Register - You should define one instance of this class for each registe r // Register - You should define one instance of this class for each registe r
skipping to change at line 67 skipping to change at line 85
// SubRegIndices - For each register in SubRegs, specify the SubRegIndex used // SubRegIndices - For each register in SubRegs, specify the SubRegIndex used
// to address it. Sub-sub-register indices are automatically inherited fr om // to address it. Sub-sub-register indices are automatically inherited fr om
// SubRegs. // SubRegs.
list<SubRegIndex> SubRegIndices = []; list<SubRegIndex> SubRegIndices = [];
// RegAltNameIndices - The alternate name indices which are valid for thi s // RegAltNameIndices - The alternate name indices which are valid for thi s
// register. // register.
list<RegAltNameIndex> RegAltNameIndices = []; list<RegAltNameIndex> RegAltNameIndices = [];
// CompositeIndices - Specify subreg indices that don't correspond direct
ly to
// a register in SubRegs and are not inherited. The following formats are
// supported:
//
// (a) Identity - Reg:a == Reg
// (a b) Alias - Reg:a == Reg:b
// (a b,c) Composite - Reg:a == (Reg:b):c
//
// This can be used to disambiguate a sub-sub-register that exists in mor
e
// than one subregister and other weird stuff.
list<dag> CompositeIndices = [];
// DwarfNumbers - Numbers used internally by gcc/gdb to identify the regi ster. // DwarfNumbers - Numbers used internally by gcc/gdb to identify the regi ster.
// These values can be determined by locating the <target>.h file in the // These values can be determined by locating the <target>.h file in the
// directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
// order of these names correspond to the enumeration used by gcc. A val ue of // order of these names correspond to the enumeration used by gcc. A val ue of
// -1 indicates that the gcc number is undefined and -2 that register num ber // -1 indicates that the gcc number is undefined and -2 that register num ber
// is invalid for this mode/flavour. // is invalid for this mode/flavour.
list<int> DwarfNumbers = []; list<int> DwarfNumbers = [];
// CostPerUse - Additional cost of instructions using this register compa red // CostPerUse - Additional cost of instructions using this register compa red
// to other registers in its class. The register allocator will try to // to other registers in its class. The register allocator will try to
// minimize the number of instructions using a register with a CostPerUse . // minimize the number of instructions using a register with a CostPerUse .
// This is used by the x86-64 and ARM Thumb targets where some registers // This is used by the x86-64 and ARM Thumb targets where some registers
// require larger instruction encodings. // require larger instruction encodings.
int CostPerUse = 0; int CostPerUse = 0;
// CoveredBySubRegs - When this bit is set, the value of this register is // CoveredBySubRegs - When this bit is set, the value of this register is
// completely determined by the value of its sub-registers. For example, the // completely determined by the value of its sub-registers. For example, the
// x86 register AX is covered by its sub-registers AL and AH, but EAX is not // x86 register AX is covered by its sub-registers AL and AH, but EAX is not
// covered by its sub-register AX. // covered by its sub-register AX.
bit CoveredBySubRegs = 0; bit CoveredBySubRegs = 0;
// HWEncoding - The target specific hardware encoding for this register.
bits<16> HWEncoding = 0;
} }
// RegisterWithSubRegs - This can be used to define instances of Register w hich // RegisterWithSubRegs - This can be used to define instances of Register w hich
// need to specify sub-registers. // need to specify sub-registers.
// List "subregs" specifies which registers are sub-registers to this one. This // List "subregs" specifies which registers are sub-registers to this one. This
// is used to populate the SubRegs and AliasSet fields of TargetRegisterDes c. // is used to populate the SubRegs and AliasSet fields of TargetRegisterDes c.
// This allows the code generator to be careful not to put two values with // This allows the code generator to be careful not to put two values with
// overlapping live ranges into registers which alias. // overlapping live ranges into registers which alias.
class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> { class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> {
let SubRegs = subregs; let SubRegs = subregs;
} }
// DAGOperand - An empty base class that unifies RegisterClass's and other
forms
// of Operand's that are legal as type qualifiers in DAG patterns. This sh
ould
// only ever be used for defining multiclasses that are polymorphic over bo
th
// RegisterClass's and other Operand's.
class DAGOperand { }
// RegisterClass - Now that all of the registers are defined, and aliases // RegisterClass - Now that all of the registers are defined, and aliases
// between registers are defined, specify which registers belong to which // between registers are defined, specify which registers belong to which
// register classes. This also defines the default allocation order of // register classes. This also defines the default allocation order of
// registers by register allocators. // registers by register allocators.
// //
class RegisterClass<string namespace, list<ValueType> regTypes, int alignme nt, class RegisterClass<string namespace, list<ValueType> regTypes, int alignme nt,
dag regList, RegAltNameIndex idx = NoRegAltName> { dag regList, RegAltNameIndex idx = NoRegAltName>
: DAGOperand {
string Namespace = namespace; string Namespace = namespace;
// RegType - Specify the list ValueType of the registers in this register // RegType - Specify the list ValueType of the registers in this register
// class. Note that all registers in a register class must have the same // class. Note that all registers in a register class must have the same
// ValueTypes. This is a list because some targets permit storing differ ent // ValueTypes. This is a list because some targets permit storing differ ent
// types in same register, for example vector values with 128-bit total s ize, // types in same register, for example vector values with 128-bit total s ize,
// but different count/size of items, like SSE on x86. // but different count/size of items, like SSE on x86.
// //
list<ValueType> RegTypes = regTypes; list<ValueType> RegTypes = regTypes;
skipping to change at line 154 skipping to change at line 170
// allocation_order_* method are not specified, this also defines the ord er of // allocation_order_* method are not specified, this also defines the ord er of
// allocation used by the register allocator. // allocation used by the register allocator.
// //
dag MemberList = regList; dag MemberList = regList;
// AltNameIndex - The alternate register name to use when printing operan ds // AltNameIndex - The alternate register name to use when printing operan ds
// of this register class. Every register in the register class must have // of this register class. Every register in the register class must have
// a valid alternate name for the given index. // a valid alternate name for the given index.
RegAltNameIndex altNameIndex = idx; RegAltNameIndex altNameIndex = idx;
// SubRegClasses - Specify the register class of subregisters as a list o
f
// dags: (RegClass SubRegIndex, SubRegindex, ...)
list<dag> SubRegClasses = [];
// isAllocatable - Specify that the register class can be used for virtua l // isAllocatable - Specify that the register class can be used for virtua l
// registers and register allocation. Some register classes are only use d to // registers and register allocation. Some register classes are only use d to
// model instruction operand constraints, and should have isAllocatable = 0. // model instruction operand constraints, and should have isAllocatable = 0.
bit isAllocatable = 1; bit isAllocatable = 1;
// AltOrders - List of alternative allocation orders. The default order i s // AltOrders - List of alternative allocation orders. The default order i s
// MemberList itself, and that is good enough for most targets since the // MemberList itself, and that is good enough for most targets since the
// register allocators automatically remove reserved registers and move // register allocators automatically remove reserved registers and move
// callee-saved registers to the end. // callee-saved registers to the end.
list<dag> AltOrders = []; list<dag> AltOrders = [];
skipping to change at line 195 skipping to change at line 207
// (add R0, R1, R2) - Set Union. Each argument can be an individual registe r, a // (add R0, R1, R2) - Set Union. Each argument can be an individual registe r, a
// register class, or a sub-expression. This is also the way to simply list // register class, or a sub-expression. This is also the way to simply list
// registers. // registers.
// //
// (sub GPR, SP) - Set difference. Subtract the last arguments from the fir st. // (sub GPR, SP) - Set difference. Subtract the last arguments from the fir st.
// //
// (and GPR, CSR) - Set intersection. All registers from the first set that are // (and GPR, CSR) - Set intersection. All registers from the first set that are
// also in the second set. // also in the second set.
// //
// (sequence "R%u", 0, 15) -> [R0, R1, ..., R15]. Generate a sequence of // (sequence "R%u", 0, 15) -> [R0, R1, ..., R15]. Generate a sequence of
// numbered registers. // numbered registers. Takes an optional 4th operand which is a stride to
use
// when generating the sequence.
// //
// (shl GPR, 4) - Remove the first N elements. // (shl GPR, 4) - Remove the first N elements.
// //
// (trunc GPR, 4) - Truncate after the first N elements. // (trunc GPR, 4) - Truncate after the first N elements.
// //
// (rotl GPR, 1) - Rotate N places to the left. // (rotl GPR, 1) - Rotate N places to the left.
// //
// (rotr GPR, 1) - Rotate N places to the right. // (rotr GPR, 1) - Rotate N places to the right.
// //
// (decimate GPR, 2) - Pick every N'th element, starting with the first. // (decimate GPR, 2) - Pick every N'th element, starting with the first.
skipping to change at line 248 skipping to change at line 261
// registers. // registers.
class RegisterTuples<list<SubRegIndex> Indices, list<dag> Regs> { class RegisterTuples<list<SubRegIndex> Indices, list<dag> Regs> {
// SubRegs - N lists of registers to be zipped up. Super-registers are // SubRegs - N lists of registers to be zipped up. Super-registers are
// synthesized from the first element of each SubRegs list, the second // synthesized from the first element of each SubRegs list, the second
// element and so on. // element and so on.
list<dag> SubRegs = Regs; list<dag> SubRegs = Regs;
// SubRegIndices - N SubRegIndex instances. This provides the names of th e // SubRegIndices - N SubRegIndex instances. This provides the names of th e
// sub-registers in the synthesized super-registers. // sub-registers in the synthesized super-registers.
list<SubRegIndex> SubRegIndices = Indices; list<SubRegIndex> SubRegIndices = Indices;
// Compose sub-register indices like in a normal Register.
list<dag> CompositeIndices = [];
} }
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// DwarfRegNum - This class provides a mapping of the llvm register enumera tion // DwarfRegNum - This class provides a mapping of the llvm register enumera tion
// to the register numbering used by gcc and gdb. These values are used by a // to the register numbering used by gcc and gdb. These values are used by a
// debug information writer to describe where values may be located during // debug information writer to describe where values may be located during
// execution. // execution.
class DwarfRegNum<list<int> Numbers> { class DwarfRegNum<list<int> Numbers> {
// DwarfNumbers - Numbers used internally by gcc/gdb to identify the regi ster. // DwarfNumbers - Numbers used internally by gcc/gdb to identify the regi ster.
// These values can be determined by locating the <target>.h file in the // These values can be determined by locating the <target>.h file in the
skipping to change at line 331 skipping to change at line 341
int AddedComplexity = 0; int AddedComplexity = 0;
// These bits capture information about the high-level semantics of the // These bits capture information about the high-level semantics of the
// instruction. // instruction.
bit isReturn = 0; // Is this instruction a return instruction? bit isReturn = 0; // Is this instruction a return instruction?
bit isBranch = 0; // Is this instruction a branch instruction? bit isBranch = 0; // Is this instruction a branch instruction?
bit isIndirectBranch = 0; // Is this instruction an indirect branch? bit isIndirectBranch = 0; // Is this instruction an indirect branch?
bit isCompare = 0; // Is this instruction a comparison instruction ? bit isCompare = 0; // Is this instruction a comparison instruction ?
bit isMoveImm = 0; // Is this instruction a move immediate instruc tion? bit isMoveImm = 0; // Is this instruction a move immediate instruc tion?
bit isBitcast = 0; // Is this instruction a bitcast instruction? bit isBitcast = 0; // Is this instruction a bitcast instruction?
bit isSelect = 0; // Is this instruction a select instruction?
bit isBarrier = 0; // Can control flow fall through this instructi on? bit isBarrier = 0; // Can control flow fall through this instructi on?
bit isCall = 0; // Is this instruction a call instruction? bit isCall = 0; // Is this instruction a call instruction?
bit canFoldAsLoad = 0; // Can this be folded as a simple memory operan d? bit canFoldAsLoad = 0; // Can this be folded as a simple memory operan d?
bit mayLoad = 0; // Is it possible for this inst to read memory? bit mayLoad = ?; // Is it possible for this inst to read memory?
bit mayStore = 0; // Is it possible for this inst to write memory bit mayStore = ?; // Is it possible for this inst to write memory
? ?
bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction prom ote? bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction prom ote?
bit isCommutable = 0; // Is this 3 operand instruction commutable? bit isCommutable = 0; // Is this 3 operand instruction commutable?
bit isTerminator = 0; // Is this part of the terminator for a basic b lock? bit isTerminator = 0; // Is this part of the terminator for a basic b lock?
bit isReMaterializable = 0; // Is this instruction re-materializable? bit isReMaterializable = 0; // Is this instruction re-materializable?
bit isPredicable = 0; // Is this instruction predicable? bit isPredicable = 0; // Is this instruction predicable?
bit hasDelaySlot = 0; // Does this instruction have an delay slot? bit hasDelaySlot = 0; // Does this instruction have an delay slot?
bit usesCustomInserter = 0; // Pseudo instr needing special help. bit usesCustomInserter = 0; // Pseudo instr needing special help.
bit hasPostISelHook = 0; // To be *adjusted* after isel by target hook. bit hasPostISelHook = 0; // To be *adjusted* after isel by target hook.
bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains? bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains?
bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction? bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction?
skipping to change at line 360 skipping to change at line 371
// If so, won't have encoding information for // If so, won't have encoding information for
// the [MC]CodeEmitter stuff. // the [MC]CodeEmitter stuff.
// Side effect flags - When set, the flags have these meanings: // Side effect flags - When set, the flags have these meanings:
// //
// hasSideEffects - The instruction has side effects that are not // hasSideEffects - The instruction has side effects that are not
// captured by any operands of the instruction or other flags. // captured by any operands of the instruction or other flags.
// //
// neverHasSideEffects - Set on an instruction with no pattern if it has no // neverHasSideEffects - Set on an instruction with no pattern if it has no
// side effects. // side effects.
bit hasSideEffects = 0; bit hasSideEffects = ?;
bit neverHasSideEffects = 0; bit neverHasSideEffects = 0;
// Is this instruction a "real" instruction (with a distinct machine // Is this instruction a "real" instruction (with a distinct machine
// encoding), or is it a pseudo instruction used for codegen modeling // encoding), or is it a pseudo instruction used for codegen modeling
// purposes. // purposes.
// FIXME: For now this is distinct from isPseudo, above, as code-gen-only // FIXME: For now this is distinct from isPseudo, above, as code-gen-only
// instructions can (and often do) still have encoding information // instructions can (and often do) still have encoding information
// associated with them. Once we've migrated all of them over to true // associated with them. Once we've migrated all of them over to true
// pseudo-instructions that are lowered to real instructions prior to // pseudo-instructions that are lowered to real instructions prior to
// the printer/emitter, we can remove this attribute and just use isPseud o. // the printer/emitter, we can remove this attribute and just use isPseud o.
skipping to change at line 404 skipping to change at line 415
string DecoderMethod = ""; string DecoderMethod = "";
/// Target-specific flags. This becomes the TSFlags field in TargetInstrD esc. /// Target-specific flags. This becomes the TSFlags field in TargetInstrD esc.
bits<64> TSFlags = 0; bits<64> TSFlags = 0;
///@name Assembler Parser Support ///@name Assembler Parser Support
///@{ ///@{
string AsmMatchConverter = ""; string AsmMatchConverter = "";
/// TwoOperandAliasConstraint - Enable TableGen to auto-generate a
/// two-operand matcher inst-alias for a three operand instruction.
/// For example, the arm instruction "add r3, r3, r5" can be written
/// as "add r3, r5". The constraint is of the same form as a tied-operand
/// constraint. For example, "$Rn = $Rd".
string TwoOperandAliasConstraint = "";
///@} ///@}
} }
/// PseudoInstExpansion - Expansion information for a pseudo-instruction. /// PseudoInstExpansion - Expansion information for a pseudo-instruction.
/// Which instruction it expands to and how the operands map from the /// Which instruction it expands to and how the operands map from the
/// pseudo. /// pseudo.
class PseudoInstExpansion<dag Result> { class PseudoInstExpansion<dag Result> {
dag ResultInst = Result; // The instruction to generate. dag ResultInst = Result; // The instruction to generate.
bit isPseudo = 1; bit isPseudo = 1;
} }
skipping to change at line 433 skipping to change at line 451
bit AssemblerMatcherPredicate = 0; bit AssemblerMatcherPredicate = 0;
/// AssemblerCondString - Name of the subtarget feature being tested used /// AssemblerCondString - Name of the subtarget feature being tested used
/// as alternative condition string used for assembler matcher. /// as alternative condition string used for assembler matcher.
/// e.g. "ModeThumb" is translated to "(Bits & ModeThumb) != 0". /// e.g. "ModeThumb" is translated to "(Bits & ModeThumb) != 0".
/// "!ModeThumb" is translated to "(Bits & ModeThumb) == 0". /// "!ModeThumb" is translated to "(Bits & ModeThumb) == 0".
/// It can also list multiple features separated by ",". /// It can also list multiple features separated by ",".
/// e.g. "ModeThumb,FeatureThumb2" is translated to /// e.g. "ModeThumb,FeatureThumb2" is translated to
/// "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0". /// "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0".
string AssemblerCondString = ""; string AssemblerCondString = "";
/// PredicateName - User-level name to use for the predicate. Mainly for
use
/// in diagnostics such as missing feature errors in the asm matcher.
string PredicateName = "";
} }
/// NoHonorSignDependentRounding - This predicate is true if support for /// NoHonorSignDependentRounding - This predicate is true if support for
/// sign-dependent-rounding is not enabled. /// sign-dependent-rounding is not enabled.
def NoHonorSignDependentRounding def NoHonorSignDependentRounding
: Predicate<"!TM.Options.HonorSignDependentRoundingFPMath()">; : Predicate<"!TM.Options.HonorSignDependentRoundingFPMath()">;
class Requires<list<Predicate> preds> { class Requires<list<Predicate> preds> {
list<Predicate> Predicates = preds; list<Predicate> Predicates = preds;
} }
skipping to change at line 473 skipping to change at line 495
} }
/// ptr_rc definition - Mark this operand as being a pointer value whose /// ptr_rc definition - Mark this operand as being a pointer value whose
/// register class is resolved dynamically via a callback to TargetInstrInf o. /// register class is resolved dynamically via a callback to TargetInstrInf o.
/// FIXME: We should probably change this to a class which contain a list o f /// FIXME: We should probably change this to a class which contain a list o f
/// flags. But currently we have but one flag. /// flags. But currently we have but one flag.
def ptr_rc : PointerLikeRegClass<0>; def ptr_rc : PointerLikeRegClass<0>;
/// unknown definition - Mark this operand as being of unknown type, causin g /// unknown definition - Mark this operand as being of unknown type, causin g
/// it to be resolved by inference in the context it is used. /// it to be resolved by inference in the context it is used.
def unknown; class unknown_class;
def unknown : unknown_class;
/// AsmOperandClass - Representation for the kinds of operands which the ta rget /// AsmOperandClass - Representation for the kinds of operands which the ta rget
/// specific parser can create and the assembly matcher may need to disting uish. /// specific parser can create and the assembly matcher may need to disting uish.
/// ///
/// Operand classes are used to define the order in which instructions are /// Operand classes are used to define the order in which instructions are
/// matched, to ensure that the instruction which gets matched for any /// matched, to ensure that the instruction which gets matched for any
/// particular list of operands is deterministic. /// particular list of operands is deterministic.
/// ///
/// The target specific parser must be able to classify a parsed operand in to a /// The target specific parser must be able to classify a parsed operand in to a
/// unique class which does not partially overlap with any other classes. I t can /// unique class which does not partially overlap with any other classes. I t can
skipping to change at line 512 skipping to change at line 535
/// "addFooOperands", where Foo is the AsmOperandClass name. The method /// "addFooOperands", where Foo is the AsmOperandClass name. The method
/// signature should be: /// signature should be:
/// void addFooOperands(MCInst &Inst, unsigned N) const; /// void addFooOperands(MCInst &Inst, unsigned N) const;
string RenderMethod = ?; string RenderMethod = ?;
/// The name of the method on the target specific operand to call to cust om /// The name of the method on the target specific operand to call to cust om
/// handle the operand parsing. This is useful when the operands do not r elate /// handle the operand parsing. This is useful when the operands do not r elate
/// to immediates or registers and are very instruction specific (as flag s to /// to immediates or registers and are very instruction specific (as flag s to
/// set in a processor register, coprocessor number, ...). /// set in a processor register, coprocessor number, ...).
string ParserMethod = ?; string ParserMethod = ?;
// The diagnostic type to present when referencing this operand in a
// match failure error message. By default, use a generic "invalid operan
d"
// diagnostic. The target AsmParser maps these codes to text.
string DiagnosticType = "";
} }
def ImmAsmOperand : AsmOperandClass { def ImmAsmOperand : AsmOperandClass {
let Name = "Imm"; let Name = "Imm";
} }
/// Operand Types - These provide the built-in operand types that may be us ed /// Operand Types - These provide the built-in operand types that may be us ed
/// by a target. Targets can optionally provide their own operand types as /// by a target. Targets can optionally provide their own operand types as
/// needed, though this should not be needed for RISC targets. /// needed, though this should not be needed for RISC targets.
class Operand<ValueType ty> { class Operand<ValueType ty> : DAGOperand {
ValueType Type = ty; ValueType Type = ty;
string PrintMethod = "printOperand"; string PrintMethod = "printOperand";
string EncoderMethod = ""; string EncoderMethod = "";
string DecoderMethod = ""; string DecoderMethod = "";
string AsmOperandLowerMethod = ?; string AsmOperandLowerMethod = ?;
string OperandType = "OPERAND_UNKNOWN"; string OperandType = "OPERAND_UNKNOWN";
dag MIOperandInfo = (ops); dag MIOperandInfo = (ops);
// ParserMatchClass - The "match class" that operands of this type fit // ParserMatchClass - The "match class" that operands of this type fit
// in. Match classes are used to define the order in which instructions a re // in. Match classes are used to define the order in which instructions a re
// match, to ensure that which instructions gets matched is deterministic . // match, to ensure that which instructions gets matched is deterministic .
// //
// The target specific parser must be able to classify an parsed operand into // The target specific parser must be able to classify an parsed operand into
// a unique class, which does not partially overlap with any other classe s. It // a unique class, which does not partially overlap with any other classe s. It
// can match a subset of some other class, in which case the AsmOperandCl ass // can match a subset of some other class, in which case the AsmOperandCl ass
// should declare the other operand as one of its super classes. // should declare the other operand as one of its super classes.
AsmOperandClass ParserMatchClass = ImmAsmOperand; AsmOperandClass ParserMatchClass = ImmAsmOperand;
} }
class RegisterOperand<RegisterClass regclass, string pm = "printOperand"> { class RegisterOperand<RegisterClass regclass, string pm = "printOperand">
: DAGOperand {
// RegClass - The register class of the operand. // RegClass - The register class of the operand.
RegisterClass RegClass = regclass; RegisterClass RegClass = regclass;
// PrintMethod - The target method to call to print register operands of // PrintMethod - The target method to call to print register operands of
// this type. The method normally will just use an alt-name index to look // this type. The method normally will just use an alt-name index to look
// up the name to print. Default to the generic printOperand(). // up the name to print. Default to the generic printOperand().
string PrintMethod = pm; string PrintMethod = pm;
// ParserMatchClass - The "match class" that operands of this type fit // ParserMatchClass - The "match class" that operands of this type fit
// in. Match classes are used to define the order in which instructions a re // in. Match classes are used to define the order in which instructions a re
// match, to ensure that which instructions gets matched is deterministic . // match, to ensure that which instructions gets matched is deterministic .
// //
skipping to change at line 574 skipping to change at line 603
def i64imm : Operand<i64>; def i64imm : Operand<i64>;
def f32imm : Operand<f32>; def f32imm : Operand<f32>;
def f64imm : Operand<f64>; def f64imm : Operand<f64>;
} }
/// zero_reg definition - Special node to stand for the zero register. /// zero_reg definition - Special node to stand for the zero register.
/// ///
def zero_reg; def zero_reg;
/// OperandWithDefaultOps - This Operand class can be used as the parent cl
ass
/// for an Operand that needs to be initialized with a default value if
/// no value is supplied in a pattern. This class can be used to simplify
the
/// pattern definitions for instructions that have target specific flags
/// encoded as immediate operands.
class OperandWithDefaultOps<ValueType ty, dag defaultops>
: Operand<ty> {
dag DefaultOps = defaultops;
}
/// PredicateOperand - This can be used to define a predicate operand for a n /// PredicateOperand - This can be used to define a predicate operand for a n
/// instruction. OpTypes specifies the MIOperandInfo for the operand, and /// instruction. OpTypes specifies the MIOperandInfo for the operand, and
/// AlwaysVal specifies the value of this predicate when set to "always /// AlwaysVal specifies the value of this predicate when set to "always
/// execute". /// execute".
class PredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal> class PredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal>
: Operand<ty> { : OperandWithDefaultOps<ty, AlwaysVal> {
let MIOperandInfo = OpTypes; let MIOperandInfo = OpTypes;
dag DefaultOps = AlwaysVal;
} }
/// OptionalDefOperand - This is used to define a optional definition opera nd /// OptionalDefOperand - This is used to define a optional definition opera nd
/// for an instruction. DefaultOps is the register the operand represents i f /// for an instruction. DefaultOps is the register the operand represents i f
/// none is supplied, e.g. zero_reg. /// none is supplied, e.g. zero_reg.
class OptionalDefOperand<ValueType ty, dag OpTypes, dag defaultops> class OptionalDefOperand<ValueType ty, dag OpTypes, dag defaultops>
: Operand<ty> { : OperandWithDefaultOps<ty, defaultops> {
let MIOperandInfo = OpTypes; let MIOperandInfo = OpTypes;
dag DefaultOps = defaultops;
} }
// InstrInfo - This class should only be instantiated once to provide param eters // InstrInfo - This class should only be instantiated once to provide param eters
// which are global to the target machine. // which are global to the target machine.
// //
class InstrInfo { class InstrInfo {
// Target can specify its instructions in either big or little-endian for mats. // Target can specify its instructions in either big or little-endian for mats.
// For instance, while both Sparc and PowerPC are big-endian platforms, t he // For instance, while both Sparc and PowerPC are big-endian platforms, t he
// Sparc manual specifies its instructions in the format [31..0] (big), w hile // Sparc manual specifies its instructions in the format [31..0] (big), w hile
// PowerPC specifies them using the format [0..31] (little). // PowerPC specifies them using the format [0..31] (little).
bit isLittleEndianEncoding = 0; bit isLittleEndianEncoding = 0;
// The instruction properties mayLoad, mayStore, and hasSideEffects are u
nset
// by default, and TableGen will infer their value from the instruction
// pattern when possible.
//
// Normally, TableGen will issue an error it it can't infer the value of
a
// property that hasn't been set explicitly. When guessInstructionPropert
ies
// is set, it will guess a safe value instead.
//
// This option is a temporary migration help. It will go away.
bit guessInstructionProperties = 1;
} }
// Standard Pseudo Instructions. // Standard Pseudo Instructions.
// This list must match TargetOpcodes.h and CodeGenTarget.cpp. // This list must match TargetOpcodes.h and CodeGenTarget.cpp.
// Only these instructions are allowed in the TargetOpcode namespace. // Only these instructions are allowed in the TargetOpcode namespace.
let isCodeGenOnly = 1, isPseudo = 1, Namespace = "TargetOpcode" in { let isCodeGenOnly = 1, isPseudo = 1, Namespace = "TargetOpcode" in {
def PHI : Instruction { def PHI : Instruction {
let OutOperandList = (outs); let OutOperandList = (outs);
let InOperandList = (ins variable_ops); let InOperandList = (ins variable_ops);
let AsmString = "PHINODE"; let AsmString = "PHINODE";
skipping to change at line 705 skipping to change at line 753
let InOperandList = (ins unknown:$src); let InOperandList = (ins unknown:$src);
let AsmString = ""; let AsmString = "";
let neverHasSideEffects = 1; let neverHasSideEffects = 1;
let isAsCheapAsAMove = 1; let isAsCheapAsAMove = 1;
} }
def BUNDLE : Instruction { def BUNDLE : Instruction {
let OutOperandList = (outs); let OutOperandList = (outs);
let InOperandList = (ins variable_ops); let InOperandList = (ins variable_ops);
let AsmString = "BUNDLE"; let AsmString = "BUNDLE";
} }
def LIFETIME_START : Instruction {
let OutOperandList = (outs);
let InOperandList = (ins i32imm:$id);
let AsmString = "LIFETIME_START";
let neverHasSideEffects = 1;
}
def LIFETIME_END : Instruction {
let OutOperandList = (outs);
let InOperandList = (ins i32imm:$id);
let AsmString = "LIFETIME_END";
let neverHasSideEffects = 1;
}
} }
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// AsmParser - This class can be implemented by targets that wish to implem ent // AsmParser - This class can be implemented by targets that wish to implem ent
// .s file parsing. // .s file parsing.
// //
// Subtargets can have multiple different assembly parsers (e.g. AT&T vs In tel // Subtargets can have multiple different assembly parsers (e.g. AT&T vs In tel
// syntax on X86 for example). // syntax on X86 for example).
// //
class AsmParser { class AsmParser {
// AsmParserClassName - This specifies the suffix to use for the asmparse r // AsmParserClassName - This specifies the suffix to use for the asmparse r
// class. Generated AsmParser classes are always prefixed with the targe t // class. Generated AsmParser classes are always prefixed with the targe t
// name. // name.
string AsmParserClassName = "AsmParser"; string AsmParserClassName = "AsmParser";
// AsmParserInstCleanup - If non-empty, this is the name of a custom memb er // AsmParserInstCleanup - If non-empty, this is the name of a custom memb er
// function of the AsmParser class to call on every matched instruction. // function of the AsmParser class to call on every matched instruction.
// This can be used to perform target specific instruction post-processin g. // This can be used to perform target specific instruction post-processin g.
string AsmParserInstCleanup = ""; string AsmParserInstCleanup = "";
//ShouldEmitMatchRegisterName - Set to false if the target needs a hand
//written register name matcher
bit ShouldEmitMatchRegisterName = 1;
} }
def DefaultAsmParser : AsmParser; def DefaultAsmParser : AsmParser;
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// AsmParserVariant - Subtargets can have multiple different assembly parse rs // AsmParserVariant - Subtargets can have multiple different assembly parse rs
// (e.g. AT&T vs Intel syntax on X86 for example). This class can be // (e.g. AT&T vs Intel syntax on X86 for example). This class can be
// implemented by targets to describe such variants. // implemented by targets to describe such variants.
// //
class AsmParserVariant { class AsmParserVariant {
// Variant - AsmParsers can be of multiple different variants. Variants are // Variant - AsmParsers can be of multiple different variants. Variants are
skipping to change at line 753 skipping to change at line 817
// RegisterPrefix - If given, the token prefix which indicates a register // RegisterPrefix - If given, the token prefix which indicates a register
// token. This is used by the matcher to automatically recognize hard cod ed // token. This is used by the matcher to automatically recognize hard cod ed
// register tokens as constrained registers, instead of tokens, for the // register tokens as constrained registers, instead of tokens, for the
// purposes of matching. // purposes of matching.
string RegisterPrefix = ""; string RegisterPrefix = "";
} }
def DefaultAsmParserVariant : AsmParserVariant; def DefaultAsmParserVariant : AsmParserVariant;
/// AssemblerPredicate - This is a Predicate that can be used when the asse mbler /// AssemblerPredicate - This is a Predicate that can be used when the asse mbler
/// matches instructions and aliases. /// matches instructions and aliases.
class AssemblerPredicate<string cond> { class AssemblerPredicate<string cond, string name = ""> {
bit AssemblerMatcherPredicate = 1; bit AssemblerMatcherPredicate = 1;
string AssemblerCondString = cond; string AssemblerCondString = cond;
string PredicateName = name;
} }
/// TokenAlias - This class allows targets to define assembler token /// TokenAlias - This class allows targets to define assembler token
/// operand aliases. That is, a token literal operand which is equivalent /// operand aliases. That is, a token literal operand which is equivalent
/// to another, canonical, token literal. For example, ARM allows: /// to another, canonical, token literal. For example, ARM allows:
/// vmov.u32 s4, #0 -> vmov.i32, #0 /// vmov.u32 s4, #0 -> vmov.i32, #0
/// 'u32' is a more specific designator for the 32-bit integer type specifi er /// 'u32' is a more specific designator for the 32-bit integer type specifi er
/// and is legal for any instruction which accepts 'i32' as a datatype suff ix. /// and is legal for any instruction which accepts 'i32' as a datatype suff ix.
/// def : TokenAlias<".u32", ".i32">; /// def : TokenAlias<".u32", ".i32">;
/// ///
skipping to change at line 906 skipping to change at line 971
// Processor chip sets - These values represent each of the chip sets suppo rted // Processor chip sets - These values represent each of the chip sets suppo rted
// by the scheduler. Each Processor definition requires corresponding // by the scheduler. Each Processor definition requires corresponding
// instruction itineraries. // instruction itineraries.
// //
class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f > { class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f > {
// Name - Chip set name. Used by command line (-mcpu=) to determine the // Name - Chip set name. Used by command line (-mcpu=) to determine the
// appropriate target chip. // appropriate target chip.
// //
string Name = n; string Name = n;
// SchedModel - The machine model for scheduling and instruction cost.
//
SchedMachineModel SchedModel = NoSchedModel;
// ProcItin - The scheduling information for the target processor. // ProcItin - The scheduling information for the target processor.
// //
ProcessorItineraries ProcItin = pi; ProcessorItineraries ProcItin = pi;
// Features - list of // Features - list of
list<SubtargetFeature> Features = f; list<SubtargetFeature> Features = f;
} }
// ProcessorModel allows subtargets to specify the more general
// SchedMachineModel instead if a ProcessorItinerary. Subtargets will
// gradually move to this newer form.
//
// Although this class always passes NoItineraries to the Processor
// class, the SchedMachineModel may still define valid Itineraries.
class ProcessorModel<string n, SchedMachineModel m, list<SubtargetFeature>
f>
: Processor<n, NoItineraries, f> {
let SchedModel = m;
}
//===----------------------------------------------------------------------
===//
// InstrMapping - This class is used to create mapping tables to relate
// instructions with each other based on the values specified in RowFields,
// ColFields, KeyCol and ValueCols.
//
class InstrMapping {
// FilterClass - Used to limit search space only to the instructions that
// define the relationship modeled by this InstrMapping record.
string FilterClass;
// RowFields - List of fields/attributes that should be same for all the
// instructions in a row of the relation table. Think of this as a set of
// properties shared by all the instructions related by this relationship
// model and is used to categorize instructions into subgroups. For insta
nce,
// if we want to define a relation that maps 'Add' instruction to its
// predicated forms, we can define RowFields like this:
//
// let RowFields = BaseOp
// All add instruction predicated/non-predicated will have to set their B
aseOp
// to the same value.
//
// def Add: { let BaseOp = 'ADD'; let predSense = 'nopred' }
// def Add_predtrue: { let BaseOp = 'ADD'; let predSense = 'true' }
// def Add_predfalse: { let BaseOp = 'ADD'; let predSense = 'false' }
list<string> RowFields = [];
// List of fields/attributes that are same for all the instructions
// in a column of the relation table.
// Ex: let ColFields = 'predSense' -- It means that the columns are arran
ged
// based on the 'predSense' values. All the instruction in a specific
// column have the same value and it is fixed for the column according
// to the values set in 'ValueCols'.
list<string> ColFields = [];
// Values for the fields/attributes listed in 'ColFields'.
// Ex: let KeyCol = 'nopred' -- It means that the key instruction (instru
ction
// that models this relation) should be non-predicated.
// In the example above, 'Add' is the key instruction.
list<string> KeyCol = [];
// List of values for the fields/attributes listed in 'ColFields', one fo
r
// each column in the relation table.
//
// Ex: let ValueCols = [['true'],['false']] -- It adds two columns in the
// table. First column requires all the instructions to have predSense
// set to 'true' and second column requires it to be 'false'.
list<list<string> > ValueCols = [];
}
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// Pull in the common support for calling conventions. // Pull in the common support for calling conventions.
// //
include "llvm/Target/TargetCallingConv.td" include "llvm/Target/TargetCallingConv.td"
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// Pull in the common support for DAG isel generation. // Pull in the common support for DAG isel generation.
// //
include "llvm/Target/TargetSelectionDAG.td" include "llvm/Target/TargetSelectionDAG.td"
 End of changes. 29 change blocks. 
36 lines changed or deleted 184 lines changed or added


 TargetCallingConv.h   TargetCallingConv.h 
skipping to change at line 39 skipping to change at line 39
static const uint64_t SExt = 1ULL<<1; ///< Sign extended static const uint64_t SExt = 1ULL<<1; ///< Sign extended
static const uint64_t SExtOffs = 1; static const uint64_t SExtOffs = 1;
static const uint64_t InReg = 1ULL<<2; ///< Passed in registe r static const uint64_t InReg = 1ULL<<2; ///< Passed in registe r
static const uint64_t InRegOffs = 2; static const uint64_t InRegOffs = 2;
static const uint64_t SRet = 1ULL<<3; ///< Hidden struct-ret ptr static const uint64_t SRet = 1ULL<<3; ///< Hidden struct-ret ptr
static const uint64_t SRetOffs = 3; static const uint64_t SRetOffs = 3;
static const uint64_t ByVal = 1ULL<<4; ///< Struct passed by value static const uint64_t ByVal = 1ULL<<4; ///< Struct passed by value
static const uint64_t ByValOffs = 4; static const uint64_t ByValOffs = 4;
static const uint64_t Nest = 1ULL<<5; ///< Nested fn static chain static const uint64_t Nest = 1ULL<<5; ///< Nested fn static chain
static const uint64_t NestOffs = 5; static const uint64_t NestOffs = 5;
static const uint64_t ByValAlign = 0xFULL << 6; //< Struct alignmen t static const uint64_t ByValAlign = 0xFULL << 6; ///< Struct alignme nt
static const uint64_t ByValAlignOffs = 6; static const uint64_t ByValAlignOffs = 6;
static const uint64_t Split = 1ULL << 10; static const uint64_t Split = 1ULL << 10;
static const uint64_t SplitOffs = 10; static const uint64_t SplitOffs = 10;
static const uint64_t OrigAlign = 0x1FULL<<27; static const uint64_t OrigAlign = 0x1FULL<<27;
static const uint64_t OrigAlignOffs = 27; static const uint64_t OrigAlignOffs = 27;
static const uint64_t ByValSize = 0xffffffffULL << 32; //< Struct size static const uint64_t ByValSize = 0xffffffffULL << 32; ///< Struct size
static const uint64_t ByValSizeOffs = 32; static const uint64_t ByValSizeOffs = 32;
static const uint64_t One = 1ULL; //< 1 of this type, for sh ifts static const uint64_t One = 1ULL; ///< 1 of this type, for s hifts
uint64_t Flags; uint64_t Flags;
public: public:
ArgFlagsTy() : Flags(0) { } ArgFlagsTy() : Flags(0) { }
bool isZExt() const { return Flags & ZExt; } bool isZExt() const { return Flags & ZExt; }
void setZExt() { Flags |= One << ZExtOffs; } void setZExt() { Flags |= One << ZExtOffs; }
bool isSExt() const { return Flags & SExt; } bool isSExt() const { return Flags & SExt; }
void setSExt() { Flags |= One << SExtOffs; } void setSExt() { Flags |= One << SExtOffs; }
skipping to change at line 116 skipping to change at line 116
/// InputArg - This struct carries flags and type information about a /// InputArg - This struct carries flags and type information about a
/// single incoming (formal) argument or incoming (from the perspective /// single incoming (formal) argument or incoming (from the perspective
/// of the caller) return value virtual register. /// of the caller) return value virtual register.
/// ///
struct InputArg { struct InputArg {
ArgFlagsTy Flags; ArgFlagsTy Flags;
MVT VT; MVT VT;
bool Used; bool Used;
/// Index original Function's argument.
unsigned OrigArgIndex;
/// Offset in bytes of current input value relative to the beginning of
/// original argument. E.g. if argument was splitted into four 32 bit
/// registers, we got 4 InputArgs with PartOffsets 0, 4, 8 and 12.
unsigned PartOffset;
InputArg() : VT(MVT::Other), Used(false) {} InputArg() : VT(MVT::Other), Used(false) {}
InputArg(ArgFlagsTy flags, EVT vt, bool used) InputArg(ArgFlagsTy flags, EVT vt, bool used,
: Flags(flags), Used(used) { unsigned origIdx, unsigned partOffs)
: Flags(flags), Used(used), OrigArgIndex(origIdx), PartOffset(partOff
s) {
VT = vt.getSimpleVT(); VT = vt.getSimpleVT();
} }
}; };
/// OutputArg - This struct carries flags and a value for a /// OutputArg - This struct carries flags and a value for a
/// single outgoing (actual) argument or outgoing (from the perspective /// single outgoing (actual) argument or outgoing (from the perspective
/// of the caller) return value virtual register. /// of the caller) return value virtual register.
/// ///
struct OutputArg { struct OutputArg {
ArgFlagsTy Flags; ArgFlagsTy Flags;
MVT VT; MVT VT;
/// IsFixed - Is this a "fixed" value, ie not passed through a vararg " ...". /// IsFixed - Is this a "fixed" value, ie not passed through a vararg " ...".
bool IsFixed; bool IsFixed;
/// Index original Function's argument.
unsigned OrigArgIndex;
/// Offset in bytes of current output value relative to the beginning o
f
/// original argument. E.g. if argument was splitted into four 32 bit
/// registers, we got 4 OutputArgs with PartOffsets 0, 4, 8 and 12.
unsigned PartOffset;
OutputArg() : IsFixed(false) {} OutputArg() : IsFixed(false) {}
OutputArg(ArgFlagsTy flags, EVT vt, bool isfixed) OutputArg(ArgFlagsTy flags, EVT vt, bool isfixed,
: Flags(flags), IsFixed(isfixed) { unsigned origIdx, unsigned partOffs)
: Flags(flags), IsFixed(isfixed), OrigArgIndex(origIdx),
PartOffset(partOffs) {
VT = vt.getSimpleVT(); VT = vt.getSimpleVT();
} }
}; };
} }
} // end llvm namespace } // end llvm namespace
#endif #endif
 End of changes. 7 change blocks. 
7 lines changed or deleted 28 lines changed or added


 TargetFolder.h   TargetFolder.h 
skipping to change at line 29 skipping to change at line 29
#ifndef LLVM_SUPPORT_TARGETFOLDER_H #ifndef LLVM_SUPPORT_TARGETFOLDER_H
#define LLVM_SUPPORT_TARGETFOLDER_H #define LLVM_SUPPORT_TARGETFOLDER_H
#include "llvm/Constants.h" #include "llvm/Constants.h"
#include "llvm/InstrTypes.h" #include "llvm/InstrTypes.h"
#include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/ArrayRef.h"
#include "llvm/Analysis/ConstantFolding.h" #include "llvm/Analysis/ConstantFolding.h"
namespace llvm { namespace llvm {
class TargetData; class DataLayout;
/// TargetFolder - Create constants with target dependent folding. /// TargetFolder - Create constants with target dependent folding.
class TargetFolder { class TargetFolder {
const TargetData *TD; const DataLayout *TD;
/// Fold - Fold the constant using target specific information. /// Fold - Fold the constant using target specific information.
Constant *Fold(Constant *C) const { Constant *Fold(Constant *C) const {
if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C))
if (Constant *CF = ConstantFoldConstantExpression(CE, TD)) if (Constant *CF = ConstantFoldConstantExpression(CE, TD))
return CF; return CF;
return C; return C;
} }
public: public:
explicit TargetFolder(const TargetData *TheTD) : TD(TheTD) {} explicit TargetFolder(const DataLayout *TheTD) : TD(TheTD) {}
//===-------------------------------------------------------------------- ===// //===-------------------------------------------------------------------- ===//
// Binary Operators // Binary Operators
//===-------------------------------------------------------------------- ===// //===-------------------------------------------------------------------- ===//
Constant *CreateAdd(Constant *LHS, Constant *RHS, Constant *CreateAdd(Constant *LHS, Constant *RHS,
bool HasNUW = false, bool HasNSW = false) const { bool HasNUW = false, bool HasNSW = false) const {
return Fold(ConstantExpr::getAdd(LHS, RHS, HasNUW, HasNSW)); return Fold(ConstantExpr::getAdd(LHS, RHS, HasNUW, HasNSW));
} }
Constant *CreateFAdd(Constant *LHS, Constant *RHS) const { Constant *CreateFAdd(Constant *LHS, Constant *RHS) const {
skipping to change at line 180 skipping to change at line 180
return C; // avoid calling Fold return C; // avoid calling Fold
return Fold(ConstantExpr::getCast(Op, C, DestTy)); return Fold(ConstantExpr::getCast(Op, C, DestTy));
} }
Constant *CreateIntCast(Constant *C, Type *DestTy, Constant *CreateIntCast(Constant *C, Type *DestTy,
bool isSigned) const { bool isSigned) const {
if (C->getType() == DestTy) if (C->getType() == DestTy)
return C; // avoid calling Fold return C; // avoid calling Fold
return Fold(ConstantExpr::getIntegerCast(C, DestTy, isSigned)); return Fold(ConstantExpr::getIntegerCast(C, DestTy, isSigned));
} }
Constant *CreatePointerCast(Constant *C, Type *DestTy) const { Constant *CreatePointerCast(Constant *C, Type *DestTy) const {
return ConstantExpr::getPointerCast(C, DestTy); if (C->getType() == DestTy)
return C; // avoid calling Fold
return Fold(ConstantExpr::getPointerCast(C, DestTy));
}
Constant *CreateFPCast(Constant *C, Type *DestTy) const {
if (C->getType() == DestTy)
return C; // avoid calling Fold
return Fold(ConstantExpr::getFPCast(C, DestTy));
} }
Constant *CreateBitCast(Constant *C, Type *DestTy) const { Constant *CreateBitCast(Constant *C, Type *DestTy) const {
return CreateCast(Instruction::BitCast, C, DestTy); return CreateCast(Instruction::BitCast, C, DestTy);
} }
Constant *CreateIntToPtr(Constant *C, Type *DestTy) const { Constant *CreateIntToPtr(Constant *C, Type *DestTy) const {
return CreateCast(Instruction::IntToPtr, C, DestTy); return CreateCast(Instruction::IntToPtr, C, DestTy);
} }
Constant *CreatePtrToInt(Constant *C, Type *DestTy) const { Constant *CreatePtrToInt(Constant *C, Type *DestTy) const {
return CreateCast(Instruction::PtrToInt, C, DestTy); return CreateCast(Instruction::PtrToInt, C, DestTy);
} }
 End of changes. 4 change blocks. 
4 lines changed or deleted 11 lines changed or added


 TargetInstrInfo.h   TargetInstrInfo.h 
skipping to change at line 17 skipping to change at line 17
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// //
// This file describes the target machine instruction set to the code gener ator. // This file describes the target machine instruction set to the code gener ator.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_TARGET_TARGETINSTRINFO_H #ifndef LLVM_TARGET_TARGETINSTRINFO_H
#define LLVM_TARGET_TARGETINSTRINFO_H #define LLVM_TARGET_TARGETINSTRINFO_H
#include "llvm/ADT/SmallSet.h"
#include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCInstrInfo.h"
#include "llvm/CodeGen/DFAPacketizer.h" #include "llvm/CodeGen/DFAPacketizer.h"
#include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFunction.h"
namespace llvm { namespace llvm {
class InstrItineraryData; class InstrItineraryData;
class LiveVariables; class LiveVariables;
class MCAsmInfo; class MCAsmInfo;
class MachineMemOperand; class MachineMemOperand;
class MachineRegisterInfo; class MachineRegisterInfo;
class MDNode; class MDNode;
class MCInst; class MCInst;
class MCSchedModel;
class SDNode; class SDNode;
class ScheduleHazardRecognizer; class ScheduleHazardRecognizer;
class SelectionDAG; class SelectionDAG;
class ScheduleDAG; class ScheduleDAG;
class TargetRegisterClass; class TargetRegisterClass;
class TargetRegisterInfo; class TargetRegisterInfo;
class BranchProbability; class BranchProbability;
template<class T> class SmallVectorImpl; template<class T> class SmallVectorImpl;
//------------------------------------------------------------------------- -- //------------------------------------------------------------------------- --
/// ///
/// TargetInstrInfo - Interface to description of machine instruction set /// TargetInstrInfo - Interface to description of machine instruction set
/// ///
class TargetInstrInfo : public MCInstrInfo { class TargetInstrInfo : public MCInstrInfo {
TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT TargetInstrInfo(const TargetInstrInfo &) LLVM_DELETED_FUNCTION;
void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT void operator=(const TargetInstrInfo &) LLVM_DELETED_FUNCTION;
public: public:
TargetInstrInfo(int CFSetupOpcode = -1, int CFDestroyOpcode = -1) TargetInstrInfo(int CFSetupOpcode = -1, int CFDestroyOpcode = -1)
: CallFrameSetupOpcode(CFSetupOpcode), : CallFrameSetupOpcode(CFSetupOpcode),
CallFrameDestroyOpcode(CFDestroyOpcode) { CallFrameDestroyOpcode(CFDestroyOpcode) {
} }
virtual ~TargetInstrInfo(); virtual ~TargetInstrInfo();
/// getRegClass - Givem a machine instruction descriptor, returns the reg ister /// getRegClass - Givem a machine instruction descriptor, returns the reg ister
/// class constraint for OpNum, or NULL. /// class constraint for OpNum, or NULL.
const TargetRegisterClass *getRegClass(const MCInstrDesc &TID, const TargetRegisterClass *getRegClass(const MCInstrDesc &TID,
unsigned OpNum, unsigned OpNum,
const TargetRegisterInfo *TRI) con const TargetRegisterInfo *TRI,
st; const MachineFunction &MF) const;
/// isTriviallyReMaterializable - Return true if the instruction is trivi ally /// isTriviallyReMaterializable - Return true if the instruction is trivi ally
/// rematerializable, meaning it has no side effects and requires no oper ands /// rematerializable, meaning it has no side effects and requires no oper ands
/// that aren't always available. /// that aren't always available.
bool isTriviallyReMaterializable(const MachineInstr *MI, bool isTriviallyReMaterializable(const MachineInstr *MI,
AliasAnalysis *AA = 0) const { AliasAnalysis *AA = 0) const {
return MI->getOpcode() == TargetOpcode::IMPLICIT_DEF || return MI->getOpcode() == TargetOpcode::IMPLICIT_DEF ||
(MI->getDesc().isRematerializable() && (MI->getDesc().isRematerializable() &&
(isReallyTriviallyReMaterializable(MI, AA) || (isReallyTriviallyReMaterializable(MI, AA) ||
isReallyTriviallyReMaterializableGeneric(MI, AA))); isReallyTriviallyReMaterializableGeneric(MI, AA)));
skipping to change at line 187 skipping to change at line 190
/// specific location targeting a new destination register. /// specific location targeting a new destination register.
/// The register in Orig->getOperand(0).getReg() will be substituted by /// The register in Orig->getOperand(0).getReg() will be substituted by
/// DestReg:SubIdx. Any existing subreg index is preserved or composed wi th /// DestReg:SubIdx. Any existing subreg index is preserved or composed wi th
/// SubIdx. /// SubIdx.
virtual void reMaterialize(MachineBasicBlock &MBB, virtual void reMaterialize(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI, MachineBasicBlock::iterator MI,
unsigned DestReg, unsigned SubIdx, unsigned DestReg, unsigned SubIdx,
const MachineInstr *Orig, const MachineInstr *Orig,
const TargetRegisterInfo &TRI) const = 0; const TargetRegisterInfo &TRI) const = 0;
/// scheduleTwoAddrSource - Schedule the copy / re-mat of the source of t
he
/// two-addrss instruction inserted by two-address pass.
virtual void scheduleTwoAddrSource(MachineInstr *SrcMI,
MachineInstr *UseMI,
const TargetRegisterInfo &TRI) const {
// Do nothing.
}
/// duplicate - Create a duplicate of the Orig instruction in MF. This is like /// duplicate - Create a duplicate of the Orig instruction in MF. This is like
/// MachineFunction::CloneMachineInstr(), but the target may update opera nds /// MachineFunction::CloneMachineInstr(), but the target may update opera nds
/// that are required to be unique. /// that are required to be unique.
/// ///
/// The instruction must be duplicable as indicated by isNotDuplicable(). /// The instruction must be duplicable as indicated by isNotDuplicable().
virtual MachineInstr *duplicate(MachineInstr *Orig, virtual MachineInstr *duplicate(MachineInstr *Orig,
MachineFunction &MF) const = 0; MachineFunction &MF) const = 0;
/// convertToThreeAddress - This method must be implemented by targets th at /// convertToThreeAddress - This method must be implemented by targets th at
/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the tar get /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the tar get
skipping to change at line 321 skipping to change at line 316
MachineBasicBlock::iterator MBBI) const { MachineBasicBlock::iterator MBBI) const {
return true; return true;
} }
/// isProfitableToIfCvt - Return true if it's profitable to predicate /// isProfitableToIfCvt - Return true if it's profitable to predicate
/// instructions with accumulated instruction latency of "NumCycles" /// instructions with accumulated instruction latency of "NumCycles"
/// of the specified basic block, where the probability of the instructio ns /// of the specified basic block, where the probability of the instructio ns
/// being executed is given by Probability, and Confidence is a measure /// being executed is given by Probability, and Confidence is a measure
/// of our confidence that it will be properly predicted. /// of our confidence that it will be properly predicted.
virtual virtual
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCyles, bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
unsigned ExtraPredCycles, unsigned ExtraPredCycles,
const BranchProbability &Probability) const { const BranchProbability &Probability) const {
return false; return false;
} }
/// isProfitableToIfCvt - Second variant of isProfitableToIfCvt, this one /// isProfitableToIfCvt - Second variant of isProfitableToIfCvt, this one
/// checks for the case where two basic blocks from true and false path /// checks for the case where two basic blocks from true and false path
/// of a if-then-else (diamond) are predicated on mutally exclusive /// of a if-then-else (diamond) are predicated on mutally exclusive
/// predicates, where the probability of the true path being taken is giv en /// predicates, where the probability of the true path being taken is giv en
/// by Probability, and Confidence is a measure of our confidence that it /// by Probability, and Confidence is a measure of our confidence that it
skipping to change at line 349 skipping to change at line 344
return false; return false;
} }
/// isProfitableToDupForIfCvt - Return true if it's profitable for /// isProfitableToDupForIfCvt - Return true if it's profitable for
/// if-converter to duplicate instructions of specified accumulated /// if-converter to duplicate instructions of specified accumulated
/// instruction latencies in the specified MBB to enable if-conversion. /// instruction latencies in the specified MBB to enable if-conversion.
/// The probability of the instructions being executed is given by /// The probability of the instructions being executed is given by
/// Probability, and Confidence is a measure of our confidence that it /// Probability, and Confidence is a measure of our confidence that it
/// will be properly predicted. /// will be properly predicted.
virtual bool virtual bool
isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCyles, isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
const BranchProbability &Probability) const { const BranchProbability &Probability) const {
return false; return false;
} }
/// isProfitableToUnpredicate - Return true if it's profitable to unpredi cate /// isProfitableToUnpredicate - Return true if it's profitable to unpredi cate
/// one side of a 'diamond', i.e. two sides of if-else predicated on mutu ally /// one side of a 'diamond', i.e. two sides of if-else predicated on mutu ally
/// exclusive predicates. /// exclusive predicates.
/// e.g. /// e.g.
/// subeq r0, r1, #1 /// subeq r0, r1, #1
/// addne r0, r1, #1 /// addne r0, r1, #1
/// => /// =>
/// sub r0, r1, #1 /// sub r0, r1, #1
/// addne r0, r1, #1 /// addne r0, r1, #1
/// ///
/// This may be profitable is conditional instructions are always execute d. /// This may be profitable is conditional instructions are always execute d.
virtual bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, virtual bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
MachineBasicBlock &FMBB) const { MachineBasicBlock &FMBB) const {
return false; return false;
} }
/// canInsertSelect - Return true if it is possible to insert a select
/// instruction that chooses between TrueReg and FalseReg based on the
/// condition code in Cond.
///
/// When successful, also return the latency in cycles from TrueReg,
/// FalseReg, and Cond to the destination register. The Cond latency shou
ld
/// compensate for a conditional branch being removed. For example, if a
/// conditional branch has a 3 cycle latency from the condition code read
,
/// and a cmov instruction has a 2 cycle latency from the condition code
/// read, CondCycles should be returned as -1.
///
/// @param MBB Block where select instruction would be inserted.
/// @param Cond Condition returned by AnalyzeBranch.
/// @param TrueReg Virtual register to select when Cond is true.
/// @param FalseReg Virtual register to select when Cond is false.
/// @param CondCycles Latency from Cond+Branch to select output.
/// @param TrueCycles Latency from TrueReg to select output.
/// @param FalseCycles Latency from FalseReg to select output.
virtual bool canInsertSelect(const MachineBasicBlock &MBB,
const SmallVectorImpl<MachineOperand> &Cond,
unsigned TrueReg, unsigned FalseReg,
int &CondCycles,
int &TrueCycles, int &FalseCycles) const {
return false;
}
/// insertSelect - Insert a select instruction into MBB before I that wil
l
/// copy TrueReg to DstReg when Cond is true, and FalseReg to DstReg when
/// Cond is false.
///
/// This function can only be called after canInsertSelect() returned tru
e.
/// The condition in Cond comes from AnalyzeBranch, and it can be assumed
/// that the same flags or registers required by Cond are available at th
e
/// insertion point.
///
/// @param MBB Block where select instruction should be inserted.
/// @param I Insertion point.
/// @param DL Source location for debugging.
/// @param DstReg Virtual register to be defined by select instruction.
/// @param Cond Condition as computed by AnalyzeBranch.
/// @param TrueReg Virtual register to copy when Cond is true.
/// @param FalseReg Virtual register to copy when Cons is false.
virtual void insertSelect(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I, DebugLoc DL,
unsigned DstReg,
const SmallVectorImpl<MachineOperand> &Cond,
unsigned TrueReg, unsigned FalseReg) const {
llvm_unreachable("Target didn't implement TargetInstrInfo::insertSelect
!");
}
/// analyzeSelect - Analyze the given select instruction, returning true
if
/// it cannot be understood. It is assumed that MI->isSelect() is true.
///
/// When successful, return the controlling condition and the operands th
at
/// determine the true and false result values.
///
/// Result = SELECT Cond, TrueOp, FalseOp
///
/// Some targets can optimize select instructions, for example by predica
ting
/// the instruction defining one of the operands. Such targets should set
/// Optimizable.
///
/// @param MI Select instruction to analyze.
/// @param Cond Condition controlling the select.
/// @param TrueOp Operand number of the value selected when Cond is true
.
/// @param FalseOp Operand number of the value selected when Cond is fals
e.
/// @param Optimizable Returned as true if MI is optimizable.
/// @returns False on success.
virtual bool analyzeSelect(const MachineInstr *MI,
SmallVectorImpl<MachineOperand> &Cond,
unsigned &TrueOp, unsigned &FalseOp,
bool &Optimizable) const {
assert(MI && MI->isSelect() && "MI must be a select instruction");
return true;
}
/// optimizeSelect - Given a select instruction that was understood by
/// analyzeSelect and returned Optimizable = true, attempt to optimize MI
by
/// merging it with one of its operands. Returns NULL on failure.
///
/// When successful, returns the new select instruction. The client is
/// responsible for deleting MI.
///
/// If both sides of the select can be optimized, PreferFalse is used to
pick
/// a side.
///
/// @param MI Optimizable select instruction.
/// @param PreferFalse Try to optimize FalseOp instead of TrueOp.
/// @returns Optimized instruction or NULL.
virtual MachineInstr *optimizeSelect(MachineInstr *MI,
bool PreferFalse = false) const {
// This function must be implemented if Optimizable is ever set.
llvm_unreachable("Target must implement TargetInstrInfo::optimizeSelect
!");
}
/// copyPhysReg - Emit instructions to copy a pair of physical registers. /// copyPhysReg - Emit instructions to copy a pair of physical registers.
///
/// This function should support copies within any legal register class a
s
/// well as any cross-class copies created during instruction selection.
///
/// The source and destination registers may overlap, which may require a
/// careful implementation when multiple copy instructions are required f
or
/// large registers. See for example the ARM target.
virtual void copyPhysReg(MachineBasicBlock &MBB, virtual void copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI, DebugLoc DL, MachineBasicBlock::iterator MI, DebugLoc DL,
unsigned DestReg, unsigned SrcReg, unsigned DestReg, unsigned SrcReg,
bool KillSrc) const { bool KillSrc) const {
llvm_unreachable("Target didn't implement TargetInstrInfo::copyPhysReg! "); llvm_unreachable("Target didn't implement TargetInstrInfo::copyPhysReg! ");
} }
/// storeRegToStackSlot - Store the specified register of the given regis ter /// storeRegToStackSlot - Store the specified register of the given regis ter
/// class to the specified stack frame index. The store instruction is to be /// class to the specified stack frame index. The store instruction is to be
/// added to the given machine basic block before the specified machine /// added to the given machine basic block before the specified machine
skipping to change at line 608 skipping to change at line 705
virtual unsigned getInlineAsmLength(const char *Str, virtual unsigned getInlineAsmLength(const char *Str,
const MCAsmInfo &MAI) const; const MCAsmInfo &MAI) const;
/// CreateTargetHazardRecognizer - Allocate and return a hazard recognize r to /// CreateTargetHazardRecognizer - Allocate and return a hazard recognize r to
/// use for this target when scheduling the machine instructions before /// use for this target when scheduling the machine instructions before
/// register allocation. /// register allocation.
virtual ScheduleHazardRecognizer* virtual ScheduleHazardRecognizer*
CreateTargetHazardRecognizer(const TargetMachine *TM, CreateTargetHazardRecognizer(const TargetMachine *TM,
const ScheduleDAG *DAG) const = 0; const ScheduleDAG *DAG) const = 0;
/// CreateTargetMIHazardRecognizer - Allocate and return a hazard recogni
zer
/// to use for this target when scheduling the machine instructions befor
e
/// register allocation.
virtual ScheduleHazardRecognizer*
CreateTargetMIHazardRecognizer(const InstrItineraryData*,
const ScheduleDAG *DAG) const = 0;
/// CreateTargetPostRAHazardRecognizer - Allocate and return a hazard /// CreateTargetPostRAHazardRecognizer - Allocate and return a hazard
/// recognizer to use for this target when scheduling the machine instruc tions /// recognizer to use for this target when scheduling the machine instruc tions
/// after register allocation. /// after register allocation.
virtual ScheduleHazardRecognizer* virtual ScheduleHazardRecognizer*
CreateTargetPostRAHazardRecognizer(const InstrItineraryData*, CreateTargetPostRAHazardRecognizer(const InstrItineraryData*,
const ScheduleDAG *DAG) const = 0; const ScheduleDAG *DAG) const = 0;
/// AnalyzeCompare - For a comparison instruction, return the source regi /// analyzeCompare - For a comparison instruction, return the source regi
ster sters
/// in SrcReg and the value it compares against in CmpValue. Return true /// in SrcReg and SrcReg2 if having two register operands, and the value
if it
/// the comparison instruction can be analyzed. /// compares against in CmpValue. Return true if the comparison instructi
virtual bool AnalyzeCompare(const MachineInstr *MI, on
unsigned &SrcReg, int &Mask, int &Value) cons /// can be analyzed.
t { virtual bool analyzeCompare(const MachineInstr *MI,
unsigned &SrcReg, unsigned &SrcReg2,
int &Mask, int &Value) const {
return false; return false;
} }
/// OptimizeCompareInstr - See if the comparison instruction can be conve rted /// optimizeCompareInstr - See if the comparison instruction can be conve rted
/// into something more efficient. E.g., on ARM most instructions can set the /// into something more efficient. E.g., on ARM most instructions can set the
/// flags register, obviating the need for a separate CMP. /// flags register, obviating the need for a separate CMP.
virtual bool OptimizeCompareInstr(MachineInstr *CmpInstr, virtual bool optimizeCompareInstr(MachineInstr *CmpInstr,
unsigned SrcReg, int Mask, int Value, unsigned SrcReg, unsigned SrcReg2,
int Mask, int Value,
const MachineRegisterInfo *MRI) const { const MachineRegisterInfo *MRI) const {
return false; return false;
} }
/// optimizeLoadInstr - Try to remove the load by folding it to a registe
r
/// operand at the use. We fold the load instructions if and only if the
/// def and use are in the same BB. We only look at one load and see
/// whether it can be folded into MI. FoldAsLoadDefReg is the virtual reg
ister
/// defined by the load we are trying to fold. DefMI returns the machine
/// instruction that defines FoldAsLoadDefReg, and the function returns
/// the machine instruction generated due to folding.
virtual MachineInstr* optimizeLoadInstr(MachineInstr *MI,
const MachineRegisterInfo *MRI,
unsigned &FoldAsLoadDefReg,
MachineInstr *&DefMI) const {
return 0;
}
/// FoldImmediate - 'Reg' is known to be defined by a move immediate /// FoldImmediate - 'Reg' is known to be defined by a move immediate
/// instruction, try to fold the immediate into the use instruction. /// instruction, try to fold the immediate into the use instruction.
virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
unsigned Reg, MachineRegisterInfo *MRI) const { unsigned Reg, MachineRegisterInfo *MRI) const {
return false; return false;
} }
/// getNumMicroOps - Return the number of u-operations the given machine /// getNumMicroOps - Return the number of u-operations the given machine
/// instruction will be decoded to on the target cpu. /// instruction will be decoded to on the target cpu. The itinerary's
/// IssueWidth is the number of microops that can be dispatched each
/// cycle. An instruction with zero microops takes no dispatch resources.
virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData, virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
const MachineInstr *MI) const; const MachineInstr *MI) const = 0;
/// isZeroCost - Return true for pseudo instructions that don't consume a ny /// isZeroCost - Return true for pseudo instructions that don't consume a ny
/// machine resources in their current form. These are common cases that the /// machine resources in their current form. These are common cases that the
/// scheduler should consider free, rather than conservatively handling t hem /// scheduler should consider free, rather than conservatively handling t hem
/// as instructions with no itinerary. /// as instructions with no itinerary.
bool isZeroCost(unsigned Opcode) const { bool isZeroCost(unsigned Opcode) const {
return Opcode <= TargetOpcode::COPY; return Opcode <= TargetOpcode::COPY;
} }
virtual int getOperandLatency(const InstrItineraryData *ItinData,
SDNode *DefNode, unsigned DefIdx,
SDNode *UseNode, unsigned UseIdx) const = 0
;
/// getOperandLatency - Compute and return the use operand latency of a g iven /// getOperandLatency - Compute and return the use operand latency of a g iven
/// pair of def and use. /// pair of def and use.
/// In most cases, the static scheduling itinerary was enough to determin e the /// In most cases, the static scheduling itinerary was enough to determin e the
/// operand latency. But it may not be possible for instructions with var iable /// operand latency. But it may not be possible for instructions with var iable
/// number of defs / uses. /// number of defs / uses.
///
/// This is a raw interface to the itinerary that may be directly overrid
en by
/// a target. Use computeOperandLatency to get the best estimate of laten
cy.
virtual int getOperandLatency(const InstrItineraryData *ItinData, virtual int getOperandLatency(const InstrItineraryData *ItinData,
const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *DefMI, unsigned DefIdx,
const MachineInstr *UseMI, unsigned UseIdx) c const MachineInstr *UseMI,
onst; unsigned UseIdx) const = 0;
virtual int getOperandLatency(const InstrItineraryData *ItinData, /// computeOperandLatency - Compute and return the latency of the given d
SDNode *DefNode, unsigned DefIdx, ata
SDNode *UseNode, unsigned UseIdx) const = 0 /// dependent def and use when the operand indices are already known.
; ///
/// FindMin may be set to get the minimum vs. expected latency.
/// getOutputLatency - Compute and return the output dependency latency o unsigned computeOperandLatency(const InstrItineraryData *ItinData,
f a const MachineInstr *DefMI, unsigned DefIdx
/// a given pair of defs which both target the same register. This is usu ,
ally const MachineInstr *UseMI, unsigned UseIdx
/// one. ,
virtual unsigned getOutputLatency(const InstrItineraryData *ItinData, bool FindMin = false) const;
const MachineInstr *DefMI, unsigned Def
Idx,
const MachineInstr *DepMI) const {
return 1;
}
/// getInstrLatency - Compute the instruction latency of a given instruct ion. /// getInstrLatency - Compute the instruction latency of a given instruct ion.
/// If the instruction has higher cost when predicated, it's returned via /// If the instruction has higher cost when predicated, it's returned via
/// PredCost. /// PredCost.
virtual int getInstrLatency(const InstrItineraryData *ItinData, virtual unsigned getInstrLatency(const InstrItineraryData *ItinData,
const MachineInstr *MI, const MachineInstr *MI,
unsigned *PredCost = 0) const; unsigned *PredCost = 0) const = 0;
virtual int getInstrLatency(const InstrItineraryData *ItinData, virtual int getInstrLatency(const InstrItineraryData *ItinData,
SDNode *Node) const = 0; SDNode *Node) const = 0;
/// Return the default expected latency for a def based on it's opcode.
unsigned defaultDefLatency(const MCSchedModel *SchedModel,
const MachineInstr *DefMI) const;
int computeDefOperandLatency(const InstrItineraryData *ItinData,
const MachineInstr *DefMI, bool FindMin) con
st;
/// isHighLatencyDef - Return true if this opcode has high latency to its /// isHighLatencyDef - Return true if this opcode has high latency to its
/// result. /// result.
virtual bool isHighLatencyDef(int opc) const { return false; } virtual bool isHighLatencyDef(int opc) const { return false; }
/// hasHighOperandLatency - Compute operand latency between a def of 'Reg ' /// hasHighOperandLatency - Compute operand latency between a def of 'Reg '
/// and an use in the current loop, return true if the target considered /// and an use in the current loop, return true if the target considered
/// it 'high'. This is used by optimization passes such as machine LICM t o /// it 'high'. This is used by optimization passes such as machine LICM t o
/// determine whether it makes sense to hoist an instruction out even in /// determine whether it makes sense to hoist an instruction out even in
/// high register pressure situation. /// high register pressure situation.
virtual virtual
skipping to change at line 705 skipping to change at line 839
const MachineRegisterInfo *MRI, const MachineRegisterInfo *MRI,
const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *DefMI, unsigned DefIdx,
const MachineInstr *UseMI, unsigned UseIdx) co nst { const MachineInstr *UseMI, unsigned UseIdx) co nst {
return false; return false;
} }
/// hasLowDefLatency - Compute operand latency of a def of 'Reg', return true /// hasLowDefLatency - Compute operand latency of a def of 'Reg', return true
/// if the target considered it 'low'. /// if the target considered it 'low'.
virtual virtual
bool hasLowDefLatency(const InstrItineraryData *ItinData, bool hasLowDefLatency(const InstrItineraryData *ItinData,
const MachineInstr *DefMI, unsigned DefIdx) const; const MachineInstr *DefMI, unsigned DefIdx) const = 0;
/// verifyInstruction - Perform target specific instruction verification. /// verifyInstruction - Perform target specific instruction verification.
virtual virtual
bool verifyInstruction(const MachineInstr *MI, StringRef &ErrInfo) const { bool verifyInstruction(const MachineInstr *MI, StringRef &ErrInfo) const {
return true; return true;
} }
/// getExecutionDomain - Return the current execution domain and bit mask of /// getExecutionDomain - Return the current execution domain and bit mask of
/// possible domains for instruction. /// possible domains for instruction.
/// ///
skipping to change at line 861 skipping to change at line 995
const MachineInstr *Orig, const MachineInstr *Orig,
const TargetRegisterInfo &TRI) const; const TargetRegisterInfo &TRI) const;
virtual MachineInstr *duplicate(MachineInstr *Orig, virtual MachineInstr *duplicate(MachineInstr *Orig,
MachineFunction &MF) const; MachineFunction &MF) const;
virtual bool produceSameValue(const MachineInstr *MI0, virtual bool produceSameValue(const MachineInstr *MI0,
const MachineInstr *MI1, const MachineInstr *MI1,
const MachineRegisterInfo *MRI) const; const MachineRegisterInfo *MRI) const;
virtual bool isSchedulingBoundary(const MachineInstr *MI, virtual bool isSchedulingBoundary(const MachineInstr *MI,
const MachineBasicBlock *MBB, const MachineBasicBlock *MBB,
const MachineFunction &MF) const; const MachineFunction &MF) const;
using TargetInstrInfo::getOperandLatency;
virtual int getOperandLatency(const InstrItineraryData *ItinData, virtual int getOperandLatency(const InstrItineraryData *ItinData,
SDNode *DefNode, unsigned DefIdx, SDNode *DefNode, unsigned DefIdx,
SDNode *UseNode, unsigned UseIdx) const; SDNode *UseNode, unsigned UseIdx) const;
using TargetInstrInfo::getInstrLatency;
virtual int getInstrLatency(const InstrItineraryData *ItinData, virtual int getInstrLatency(const InstrItineraryData *ItinData,
SDNode *Node) const; SDNode *Node) const;
virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
const MachineInstr *MI) const;
virtual unsigned getInstrLatency(const InstrItineraryData *ItinData,
const MachineInstr *MI,
unsigned *PredCost = 0) const;
virtual
bool hasLowDefLatency(const InstrItineraryData *ItinData,
const MachineInstr *DefMI, unsigned DefIdx) const;
virtual int getOperandLatency(const InstrItineraryData *ItinData,
const MachineInstr *DefMI, unsigned DefIdx,
const MachineInstr *UseMI,
unsigned UseIdx) const;
bool usePreRAHazardRecognizer() const; bool usePreRAHazardRecognizer() const;
virtual ScheduleHazardRecognizer * virtual ScheduleHazardRecognizer *
CreateTargetHazardRecognizer(const TargetMachine*, const ScheduleDAG*) co nst; CreateTargetHazardRecognizer(const TargetMachine*, const ScheduleDAG*) co nst;
virtual ScheduleHazardRecognizer * virtual ScheduleHazardRecognizer *
CreateTargetMIHazardRecognizer(const InstrItineraryData*,
const ScheduleDAG*) const;
virtual ScheduleHazardRecognizer *
CreateTargetPostRAHazardRecognizer(const InstrItineraryData*, CreateTargetPostRAHazardRecognizer(const InstrItineraryData*,
const ScheduleDAG*) const; const ScheduleDAG*) const;
}; };
} // End llvm namespace } // End llvm namespace
#endif #endif
 End of changes. 26 change blocks. 
54 lines changed or deleted 228 lines changed or added


 TargetIntrinsicInfo.h   TargetIntrinsicInfo.h 
skipping to change at line 17 skipping to change at line 17
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// //
// This file describes the target intrinsic instructions to the code genera tor. // This file describes the target intrinsic instructions to the code genera tor.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_TARGET_TARGETINTRINSICINFO_H #ifndef LLVM_TARGET_TARGETINTRINSICINFO_H
#define LLVM_TARGET_TARGETINTRINSICINFO_H #define LLVM_TARGET_TARGETINTRINSICINFO_H
#include "llvm/Support/Compiler.h"
#include <string> #include <string>
namespace llvm { namespace llvm {
class Function; class Function;
class Module; class Module;
class Type; class Type;
//------------------------------------------------------------------------- -- //------------------------------------------------------------------------- --
/// ///
/// TargetIntrinsicInfo - Interface to description of machine instruction s et /// TargetIntrinsicInfo - Interface to description of machine instruction s et
/// ///
class TargetIntrinsicInfo { class TargetIntrinsicInfo {
TargetIntrinsicInfo(const TargetIntrinsicInfo &); // DO NOT IMPLEMENT TargetIntrinsicInfo(const TargetIntrinsicInfo &) LLVM_DELETED_FUNCTION;
void operator=(const TargetIntrinsicInfo &); // DO NOT IMPLEMENT void operator=(const TargetIntrinsicInfo &) LLVM_DELETED_FUNCTION;
public: public:
TargetIntrinsicInfo(); TargetIntrinsicInfo();
virtual ~TargetIntrinsicInfo(); virtual ~TargetIntrinsicInfo();
/// Return the name of a target intrinsic, e.g. "llvm.bfin.ssync". /// Return the name of a target intrinsic, e.g. "llvm.bfin.ssync".
/// The Tys and numTys parameters are for intrinsics with overloaded type s /// The Tys and numTys parameters are for intrinsics with overloaded type s
/// (e.g., those using iAny or fAny). For a declaration for an overloaded /// (e.g., those using iAny or fAny). For a declaration for an overloaded
/// intrinsic, Tys should point to an array of numTys pointers to Type, /// intrinsic, Tys should point to an array of numTys pointers to Type,
/// and must provide exactly one type for each overloaded type in the /// and must provide exactly one type for each overloaded type in the
/// intrinsic. /// intrinsic.
 End of changes. 2 change blocks. 
2 lines changed or deleted 3 lines changed or added


 TargetLibraryInfo.h   TargetLibraryInfo.h 
skipping to change at line 21 skipping to change at line 21
#define LLVM_TARGET_TARGETLIBRARYINFO_H #define LLVM_TARGET_TARGETLIBRARYINFO_H
#include "llvm/Pass.h" #include "llvm/Pass.h"
#include "llvm/ADT/DenseMap.h" #include "llvm/ADT/DenseMap.h"
namespace llvm { namespace llvm {
class Triple; class Triple;
namespace LibFunc { namespace LibFunc {
enum Func { enum Func {
/// void operator delete[](void*);
ZdaPv,
/// void operator delete(void*);
ZdlPv,
/// void *new[](unsigned int);
Znaj,
/// void *new[](unsigned int, nothrow);
ZnajRKSt9nothrow_t,
/// void *new[](unsigned long);
Znam,
/// void *new[](unsigned long, nothrow);
ZnamRKSt9nothrow_t,
/// void *new(unsigned int);
Znwj,
/// void *new(unsigned int, nothrow);
ZnwjRKSt9nothrow_t,
/// void *new(unsigned long);
Znwm,
/// void *new(unsigned long, nothrow);
ZnwmRKSt9nothrow_t,
/// int __cxa_atexit(void (*f)(void *), void *p, void *d);
cxa_atexit,
/// void __cxa_guard_abort(guard_t *guard);
/// guard_t is int64_t in Itanium ABI or int32_t on ARM eabi.
cxa_guard_abort,
/// int __cxa_guard_acquire(guard_t *guard);
cxa_guard_acquire,
/// void __cxa_guard_release(guard_t *guard);
cxa_guard_release,
/// void *__memcpy_chk(void *s1, const void *s2, size_t n, size_t s1s
ize);
memcpy_chk,
/// double acos(double x); /// double acos(double x);
acos, acos,
/// long double acosl(long double x);
acosl,
/// float acosf(float x); /// float acosf(float x);
acosf, acosf,
/// double acosh(double x);
acosh,
/// float acoshf(float x);
acoshf,
/// long double acoshl(long double x);
acoshl,
/// long double acosl(long double x);
acosl,
/// double asin(double x); /// double asin(double x);
asin, asin,
/// long double asinl(long double x);
asinl,
/// float asinf(float x); /// float asinf(float x);
asinf, asinf,
/// double asinh(double x);
asinh,
/// float asinhf(float x);
asinhf,
/// long double asinhl(long double x);
asinhl,
/// long double asinl(long double x);
asinl,
/// double atan(double x); /// double atan(double x);
atan, atan,
/// long double atanl(long double x);
atanl,
/// float atanf(float x);
atanf,
/// double atan2(double y, double x); /// double atan2(double y, double x);
atan2, atan2,
/// long double atan2l(long double y, long double x);
atan2l,
/// float atan2f(float y, float x); /// float atan2f(float y, float x);
atan2f, atan2f,
/// long double atan2l(long double y, long double x);
atan2l,
/// float atanf(float x);
atanf,
/// double atanh(double x);
atanh,
/// float atanhf(float x);
atanhf,
/// long double atanhl(long double x);
atanhl,
/// long double atanl(long double x);
atanl,
/// void *calloc(size_t count, size_t size);
calloc,
/// double cbrt(double x);
cbrt,
/// float cbrtf(float x);
cbrtf,
/// long double cbrtl(long double x);
cbrtl,
/// double ceil(double x); /// double ceil(double x);
ceil, ceil,
/// long double ceill(long double x);
ceill,
/// float ceilf(float x); /// float ceilf(float x);
ceilf, ceilf,
/// long double ceill(long double x);
ceill,
/// double copysign(double x, double y); /// double copysign(double x, double y);
copysign, copysign,
/// float copysignf(float x, float y); /// float copysignf(float x, float y);
copysignf, copysignf,
/// long double copysignl(long double x, long double y); /// long double copysignl(long double x, long double y);
copysignl, copysignl,
/// double cos(double x); /// double cos(double x);
cos, cos,
/// long double cosl(long double x);
cosl,
/// float cosf(float x); /// float cosf(float x);
cosf, cosf,
/// double cosh(double x); /// double cosh(double x);
cosh, cosh,
/// long double coshl(long double x);
coshl,
/// float coshf(float x); /// float coshf(float x);
coshf, coshf,
/// long double coshl(long double x);
coshl,
/// long double cosl(long double x);
cosl,
/// double exp(double x); /// double exp(double x);
exp, exp,
/// long double expl(long double x); /// double exp10(double x);
expl, exp10,
/// float expf(float x); /// float exp10f(float x);
expf, exp10f,
/// long double exp10l(long double x);
exp10l,
/// double exp2(double x); /// double exp2(double x);
exp2, exp2,
/// long double exp2l(long double x);
exp2l,
/// float exp2f(float x); /// float exp2f(float x);
exp2f, exp2f,
/// long double exp2l(long double x);
exp2l,
/// float expf(float x);
expf,
/// long double expl(long double x);
expl,
/// double expm1(double x); /// double expm1(double x);
expm1, expm1,
/// long double expm1l(long double x);
expm1l,
/// float expm1f(float x); /// float expm1f(float x);
expm1f, expm1f,
/// long double expm1l(long double x);
expm1l,
/// double fabs(double x); /// double fabs(double x);
fabs, fabs,
/// long double fabsl(long double x);
fabsl,
/// float fabsf(float x); /// float fabsf(float x);
fabsf, fabsf,
/// long double fabsl(long double x);
fabsl,
/// int fiprintf(FILE *stream, const char *format, ...);
fiprintf,
/// double floor(double x); /// double floor(double x);
floor, floor,
/// long double floorl(long double x);
floorl,
/// float floorf(float x); /// float floorf(float x);
floorf, floorf,
/// int fiprintf(FILE *stream, const char *format, ...); /// long double floorl(long double x);
fiprintf, floorl,
/// double fmod(double x, double y); /// double fmod(double x, double y);
fmod, fmod,
/// long double fmodl(long double x, long double y);
fmodl,
/// float fmodf(float x, float y); /// float fmodf(float x, float y);
fmodf, fmodf,
/// long double fmodl(long double x, long double y);
fmodl,
/// int fputc(int c, FILE *stream);
fputc,
/// int fputs(const char *s, FILE *stream); /// int fputs(const char *s, FILE *stream);
fputs, fputs,
/// void free(void *ptr);
free,
/// size_t fwrite(const void *ptr, size_t size, size_t nitems, /// size_t fwrite(const void *ptr, size_t size, size_t nitems,
/// FILE *stream); /// FILE *stream);
fwrite, fwrite,
/// int iprintf(const char *format, ...); /// int iprintf(const char *format, ...);
iprintf, iprintf,
/// double log(double x); /// double log(double x);
log, log,
/// long double logl(long double x);
logl,
/// float logf(float x);
logf,
/// double log2(double x);
log2,
/// double long double log2l(long double x);
log2l,
/// float log2f(float x);
log2f,
/// double log10(double x); /// double log10(double x);
log10, log10,
/// long double log10l(long double x);
log10l,
/// float log10f(float x); /// float log10f(float x);
log10f, log10f,
/// long double log10l(long double x);
log10l,
/// double log1p(double x); /// double log1p(double x);
log1p, log1p,
/// long double log1pl(long double x);
log1pl,
/// float log1pf(float x); /// float log1pf(float x);
log1pf, log1pf,
/// long double log1pl(long double x);
log1pl,
/// double log2(double x);
log2,
/// float log2f(float x);
log2f,
/// double long double log2l(long double x);
log2l,
/// double logb(double x);
logb,
/// float logbf(float x);
logbf,
/// long double logbl(long double x);
logbl,
/// float logf(float x);
logf,
/// long double logl(long double x);
logl,
/// void *malloc(size_t size);
malloc,
/// void *memchr(const void *s, int c, size_t n);
memchr,
/// int memcmp(const void *s1, const void *s2, size_t n);
memcmp,
/// void *memcpy(void *s1, const void *s2, size_t n); /// void *memcpy(void *s1, const void *s2, size_t n);
memcpy, memcpy,
/// void *memmove(void *s1, const void *s2, size_t n); /// void *memmove(void *s1, const void *s2, size_t n);
memmove, memmove,
/// void *memset(void *b, int c, size_t len); /// void *memset(void *b, int c, size_t len);
memset, memset,
/// void memset_pattern16(void *b, const void *pattern16, size_t len) ; /// void memset_pattern16(void *b, const void *pattern16, size_t len) ;
memset_pattern16, memset_pattern16,
/// double nearbyint(double x); /// double nearbyint(double x);
nearbyint, nearbyint,
/// float nearbyintf(float x); /// float nearbyintf(float x);
nearbyintf, nearbyintf,
/// long double nearbyintl(long double x); /// long double nearbyintl(long double x);
nearbyintl, nearbyintl,
/// int posix_memalign(void **memptr, size_t alignment, size_t size);
posix_memalign,
/// double pow(double x, double y); /// double pow(double x, double y);
pow, pow,
/// float powf(float x, float y); /// float powf(float x, float y);
powf, powf,
/// long double powl(long double x, long double y); /// long double powl(long double x, long double y);
powl, powl,
/// int putchar(int c);
putchar,
/// int puts(const char *s);
puts,
/// void *realloc(void *ptr, size_t size);
realloc,
/// void *reallocf(void *ptr, size_t size);
reallocf,
/// double rint(double x); /// double rint(double x);
rint, rint,
/// float rintf(float x); /// float rintf(float x);
rintf, rintf,
/// long double rintl(long double x); /// long double rintl(long double x);
rintl, rintl,
/// double round(double x); /// double round(double x);
round, round,
/// float roundf(float x); /// float roundf(float x);
roundf, roundf,
/// long double roundl(long double x); /// long double roundl(long double x);
roundl, roundl,
/// double sin(double x); /// double sin(double x);
sin, sin,
/// long double sinl(long double x);
sinl,
/// float sinf(float x); /// float sinf(float x);
sinf, sinf,
/// double sinh(double x); /// double sinh(double x);
sinh, sinh,
/// long double sinhl(long double x);
sinhl,
/// float sinhf(float x); /// float sinhf(float x);
sinhf, sinhf,
/// long double sinhl(long double x);
sinhl,
/// long double sinl(long double x);
sinl,
/// int siprintf(char *str, const char *format, ...); /// int siprintf(char *str, const char *format, ...);
siprintf, siprintf,
/// double sqrt(double x); /// double sqrt(double x);
sqrt, sqrt,
/// long double sqrtl(long double x);
sqrtl,
/// float sqrtf(float x); /// float sqrtf(float x);
sqrtf, sqrtf,
/// long double sqrtl(long double x);
sqrtl,
/// char *stpcpy(char *s1, const char *s2);
stpcpy,
/// char *strcat(char *s1, const char *s2);
strcat,
/// char *strchr(const char *s, int c);
strchr,
/// int strcmp(const char *s1, const char *s2);
strcmp,
/// char *strcpy(char *s1, const char *s2);
strcpy,
/// size_t strcspn(const char *s1, const char *s2);
strcspn,
/// char *strdup(const char *s1);
strdup,
/// size_t strlen(const char *s);
strlen,
/// char *strncat(char *s1, const char *s2, size_t n);
strncat,
/// int strncmp(const char *s1, const char *s2, size_t n);
strncmp,
/// char *strncpy(char *s1, const char *s2, size_t n);
strncpy,
/// char *strndup(const char *s1, size_t n);
strndup,
/// size_t strnlen(const char *s, size_t maxlen);
strnlen,
/// char *strpbrk(const char *s1, const char *s2);
strpbrk,
/// char *strrchr(const char *s, int c);
strrchr,
/// size_t strspn(const char *s1, const char *s2);
strspn,
/// char *strstr(const char *s1, const char *s2);
strstr,
/// double strtod(const char *nptr, char **endptr);
strtod,
/// float strtof(const char *nptr, char **endptr);
strtof,
/// long int strtol(const char *nptr, char **endptr, int base);
strtol,
/// long double strtold(const char *nptr, char **endptr);
strtold,
/// long long int strtoll(const char *nptr, char **endptr, int base);
strtoll,
/// unsigned long int strtoul(const char *nptr, char **endptr, int ba
se);
strtoul,
/// unsigned long long int strtoull(const char *nptr, char **endptr,
/// int base);
strtoull,
/// double tan(double x); /// double tan(double x);
tan, tan,
/// long double tanl(long double x);
tanl,
/// float tanf(float x); /// float tanf(float x);
tanf, tanf,
/// double tanh(double x); /// double tanh(double x);
tanh, tanh,
/// long double tanhl(long double x);
tanhl,
/// float tanhf(float x); /// float tanhf(float x);
tanhf, tanhf,
/// long double tanhl(long double x);
tanhl,
/// long double tanl(long double x);
tanl,
/// double trunc(double x); /// double trunc(double x);
trunc, trunc,
/// float truncf(float x); /// float truncf(float x);
truncf, truncf,
/// long double truncl(long double x); /// long double truncl(long double x);
truncl, truncl,
/// int __cxa_atexit(void (*f)(void *), void *p, void *d); /// void *valloc(size_t size);
cxa_atexit, valloc,
/// void __cxa_guard_abort(guard_t *guard);
/// guard_t is int64_t in Itanium ABI or int32_t on ARM eabi.
cxa_guard_abort,
/// int __cxa_guard_acquire(guard_t *guard);
cxa_guard_acquire,
/// void __cxa_guard_release(guard_t *guard);
cxa_guard_release,
NumLibFuncs NumLibFuncs
}; };
} }
/// TargetLibraryInfo - This immutable pass captures information about what /// TargetLibraryInfo - This immutable pass captures information about what
/// library functions are available for the current target, and allows a /// library functions are available for the current target, and allows a
/// frontend to disable optimizations through -fno-builtin etc. /// frontend to disable optimizations through -fno-builtin etc.
class TargetLibraryInfo : public ImmutablePass { class TargetLibraryInfo : public ImmutablePass {
virtual void anchor(); virtual void anchor();
skipping to change at line 250 skipping to change at line 381
AvailabilityState getState(LibFunc::Func F) const { AvailabilityState getState(LibFunc::Func F) const {
return static_cast<AvailabilityState>((AvailableArray[F/4] >> 2*(F&3)) & 3); return static_cast<AvailabilityState>((AvailableArray[F/4] >> 2*(F&3)) & 3);
} }
public: public:
static char ID; static char ID;
TargetLibraryInfo(); TargetLibraryInfo();
TargetLibraryInfo(const Triple &T); TargetLibraryInfo(const Triple &T);
explicit TargetLibraryInfo(const TargetLibraryInfo &TLI); explicit TargetLibraryInfo(const TargetLibraryInfo &TLI);
/// getLibFunc - Search for a particular function name. If it is one of
the
/// known library functions, return true and set F to the corresponding v
alue.
bool getLibFunc(StringRef funcName, LibFunc::Func &F) const;
/// has - This function is used by optimizations that want to match on or form /// has - This function is used by optimizations that want to match on or form
/// a given library function. /// a given library function.
bool has(LibFunc::Func F) const { bool has(LibFunc::Func F) const {
return getState(F) != Unavailable; return getState(F) != Unavailable;
} }
/// hasOptimizedCodeGen - Return true if the function is both available a
s
/// a builtin and a candidate for optimized code generation.
bool hasOptimizedCodeGen(LibFunc::Func F) const {
if (getState(F) == Unavailable)
return false;
switch (F) {
default: break;
case LibFunc::copysign: case LibFunc::copysignf: case LibFunc::copysi
gnl:
case LibFunc::fabs: case LibFunc::fabsf: case LibFunc::fabsl:
case LibFunc::sin: case LibFunc::sinf: case LibFunc::sinl:
case LibFunc::cos: case LibFunc::cosf: case LibFunc::cosl:
case LibFunc::sqrt: case LibFunc::sqrtf: case LibFunc::sqrtl:
case LibFunc::floor: case LibFunc::floorf: case LibFunc::floorl
:
case LibFunc::nearbyint: case LibFunc::nearbyintf: case LibFunc::nearby
intl:
case LibFunc::ceil: case LibFunc::ceilf: case LibFunc::ceill:
case LibFunc::rint: case LibFunc::rintf: case LibFunc::rintl:
case LibFunc::trunc: case LibFunc::truncf: case LibFunc::truncl
:
case LibFunc::log2: case LibFunc::log2f: case LibFunc::log2l:
case LibFunc::exp2: case LibFunc::exp2f: case LibFunc::exp2l:
case LibFunc::memcmp:
return true;
}
return false;
}
StringRef getName(LibFunc::Func F) const { StringRef getName(LibFunc::Func F) const {
AvailabilityState State = getState(F); AvailabilityState State = getState(F);
if (State == Unavailable) if (State == Unavailable)
return StringRef(); return StringRef();
if (State == StandardName) if (State == StandardName)
return StandardNames[F]; return StandardNames[F];
assert(State == CustomName); assert(State == CustomName);
return CustomNames.find(F)->second; return CustomNames.find(F)->second;
} }
 End of changes. 43 change blocks. 
65 lines changed or deleted 234 lines changed or added


 TargetLowering.h   TargetLowering.h 
skipping to change at line 25 skipping to change at line 25
// 3. Cost thresholds for alternative implementations of certain operation s. // 3. Cost thresholds for alternative implementations of certain operation s.
// //
// In addition it has a few other components, like information about FP // In addition it has a few other components, like information about FP
// immediates. // immediates.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_TARGET_TARGETLOWERING_H #ifndef LLVM_TARGET_TARGETLOWERING_H
#define LLVM_TARGET_TARGETLOWERING_H #define LLVM_TARGET_TARGETLOWERING_H
#include "llvm/AddressingMode.h"
#include "llvm/CallingConv.h" #include "llvm/CallingConv.h"
#include "llvm/InlineAsm.h" #include "llvm/InlineAsm.h"
#include "llvm/Attributes.h" #include "llvm/Attributes.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/Support/CallSite.h"
#include "llvm/CodeGen/SelectionDAGNodes.h" #include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/CodeGen/RuntimeLibcalls.h" #include "llvm/CodeGen/RuntimeLibcalls.h"
#include "llvm/Support/DebugLoc.h" #include "llvm/Support/DebugLoc.h"
#include "llvm/Target/TargetCallingConv.h" #include "llvm/Target/TargetCallingConv.h"
#include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetMachine.h"
#include <climits> #include <climits>
#include <map> #include <map>
#include <vector> #include <vector>
namespace llvm { namespace llvm {
skipping to change at line 51 skipping to change at line 54
class FunctionLoweringInfo; class FunctionLoweringInfo;
class ImmutableCallSite; class ImmutableCallSite;
class IntrinsicInst; class IntrinsicInst;
class MachineBasicBlock; class MachineBasicBlock;
class MachineFunction; class MachineFunction;
class MachineInstr; class MachineInstr;
class MachineJumpTableInfo; class MachineJumpTableInfo;
class MCContext; class MCContext;
class MCExpr; class MCExpr;
template<typename T> class SmallVectorImpl; template<typename T> class SmallVectorImpl;
class TargetData; class DataLayout;
class TargetRegisterClass; class TargetRegisterClass;
class TargetLibraryInfo;
class TargetLoweringObjectFile; class TargetLoweringObjectFile;
class Value; class Value;
namespace Sched { namespace Sched {
enum Preference { enum Preference {
None, // No preference None, // No preference
Source, // Follow source order. Source, // Follow source order.
RegPressure, // Scheduling for lowest register pressure. RegPressure, // Scheduling for lowest register pressure.
Hybrid, // Scheduling for both latency and register pressur e. Hybrid, // Scheduling for both latency and register pressur e.
ILP, // Scheduling for ILP in low register pressure mode . ILP, // Scheduling for ILP in low register pressure mode .
skipping to change at line 76 skipping to change at line 80
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
/// TargetLowering - This class defines information used to lower LLVM code to /// TargetLowering - This class defines information used to lower LLVM code to
/// legal SelectionDAG operators that the target instruction selector can a ccept /// legal SelectionDAG operators that the target instruction selector can a ccept
/// natively. /// natively.
/// ///
/// This class also defines callbacks that targets must implement to lower /// This class also defines callbacks that targets must implement to lower
/// target-specific constructs to SelectionDAG operators. /// target-specific constructs to SelectionDAG operators.
/// ///
class TargetLowering { class TargetLowering {
TargetLowering(const TargetLowering&); // DO NOT IMPLEMENT TargetLowering(const TargetLowering&) LLVM_DELETED_FUNCTION;
void operator=(const TargetLowering&); // DO NOT IMPLEMENT void operator=(const TargetLowering&) LLVM_DELETED_FUNCTION;
public: public:
/// LegalizeAction - This enum indicates whether operations are valid for a /// LegalizeAction - This enum indicates whether operations are valid for a
/// target, and if not, what action should be used to make them valid. /// target, and if not, what action should be used to make them valid.
enum LegalizeAction { enum LegalizeAction {
Legal, // The target natively supports this operation. Legal, // The target natively supports this operation.
Promote, // This operation should be executed in a larger type. Promote, // This operation should be executed in a larger type.
Expand, // Try to expand this to other ops, otherwise use a libcall . Expand, // Try to expand this to other ops, otherwise use a libcall .
Custom // Use the LowerOperation hook to implement custom lowering . Custom // Use the LowerOperation hook to implement custom lowering .
}; };
skipping to change at line 101 skipping to change at line 105
TypeLegal, // The target natively supports this type. TypeLegal, // The target natively supports this type.
TypePromoteInteger, // Replace this integer with a larger one. TypePromoteInteger, // Replace this integer with a larger one.
TypeExpandInteger, // Split this integer into two of half the size. TypeExpandInteger, // Split this integer into two of half the size.
TypeSoftenFloat, // Convert this float to a same size integer type. TypeSoftenFloat, // Convert this float to a same size integer type.
TypeExpandFloat, // Split this float into two of half the size. TypeExpandFloat, // Split this float into two of half the size.
TypeScalarizeVector, // Replace this one-element vector with its elemen t. TypeScalarizeVector, // Replace this one-element vector with its elemen t.
TypeSplitVector, // Split this vector into two of half the size. TypeSplitVector, // Split this vector into two of half the size.
TypeWidenVector // This vector should be widened into a larger vec tor. TypeWidenVector // This vector should be widened into a larger vec tor.
}; };
/// LegalizeKind holds the legalization kind that needs to happen to EVT
/// in order to type-legalize it.
typedef std::pair<LegalizeTypeAction, EVT> LegalizeKind;
enum BooleanContent { // How the target represents true/false values. enum BooleanContent { // How the target represents true/false values.
UndefinedBooleanContent, // Only bit 0 counts, the rest can hold gar bage. UndefinedBooleanContent, // Only bit 0 counts, the rest can hold gar bage.
ZeroOrOneBooleanContent, // All bits zero except for bit 0. ZeroOrOneBooleanContent, // All bits zero except for bit 0.
ZeroOrNegativeOneBooleanContent // All bits equal to bit 0. ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
}; };
enum SelectSupportKind {
ScalarValSelect, // The target supports scalar selects (ex: cmov).
ScalarCondVectorVal, // The target supports selects with a scalar cond
ition
// and vector values (ex: cmov).
VectorMaskSelect // The target supports vector selects with a vect
or
// mask (ex: x86 blends).
};
static ISD::NodeType getExtendForContent(BooleanContent Content) { static ISD::NodeType getExtendForContent(BooleanContent Content) {
switch (Content) { switch (Content) {
case UndefinedBooleanContent: case UndefinedBooleanContent:
// Extend by adding rubbish bits. // Extend by adding rubbish bits.
return ISD::ANY_EXTEND; return ISD::ANY_EXTEND;
case ZeroOrOneBooleanContent: case ZeroOrOneBooleanContent:
// Extend by adding zero bits. // Extend by adding zero bits.
return ISD::ZERO_EXTEND; return ISD::ZERO_EXTEND;
case ZeroOrNegativeOneBooleanContent: case ZeroOrNegativeOneBooleanContent:
// Extend by copying the sign bit. // Extend by copying the sign bit.
skipping to change at line 128 skipping to change at line 144
} }
llvm_unreachable("Invalid content kind"); llvm_unreachable("Invalid content kind");
} }
/// NOTE: The constructor takes ownership of TLOF. /// NOTE: The constructor takes ownership of TLOF.
explicit TargetLowering(const TargetMachine &TM, explicit TargetLowering(const TargetMachine &TM,
const TargetLoweringObjectFile *TLOF); const TargetLoweringObjectFile *TLOF);
virtual ~TargetLowering(); virtual ~TargetLowering();
const TargetMachine &getTargetMachine() const { return TM; } const TargetMachine &getTargetMachine() const { return TM; }
const TargetData *getTargetData() const { return TD; } const DataLayout *getDataLayout() const { return TD; }
const TargetLoweringObjectFile &getObjFileLowering() const { return TLOF; } const TargetLoweringObjectFile &getObjFileLowering() const { return TLOF; }
bool isBigEndian() const { return !IsLittleEndian; } bool isBigEndian() const { return !IsLittleEndian; }
bool isLittleEndian() const { return IsLittleEndian; } bool isLittleEndian() const { return IsLittleEndian; }
MVT getPointerTy() const { return PointerTy; } // Return the pointer type for the given address space, defaults to
// the pointer type from the data layout.
// FIXME: The default needs to be removed once all the code is updated.
virtual MVT getPointerTy(uint32_t AS = 0) const { return PointerTy; }
virtual MVT getShiftAmountTy(EVT LHSTy) const; virtual MVT getShiftAmountTy(EVT LHSTy) const;
/// isSelectExpensive - Return true if the select operation is expensive for /// isSelectExpensive - Return true if the select operation is expensive for
/// this target. /// this target.
bool isSelectExpensive() const { return SelectIsExpensive; } bool isSelectExpensive() const { return SelectIsExpensive; }
virtual bool isSelectSupported(SelectSupportKind kind) const { return tru
e; }
/// isIntDivCheap() - Return true if integer divide is usually cheaper th an /// isIntDivCheap() - Return true if integer divide is usually cheaper th an
/// a sequence of several shifts, adds, and multiplies for this target. /// a sequence of several shifts, adds, and multiplies for this target.
bool isIntDivCheap() const { return IntDivIsCheap; } bool isIntDivCheap() const { return IntDivIsCheap; }
/// isSlowDivBypassed - Returns true if target has indicated at least one
/// type should be bypassed.
bool isSlowDivBypassed() const { return !BypassSlowDivWidths.empty(); }
/// getBypassSlowDivTypes - Returns map of slow types for division or
/// remainder with corresponding fast types
const DenseMap<unsigned int, unsigned int> &getBypassSlowDivWidths() cons
t {
return BypassSlowDivWidths;
}
/// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of
/// srl/add/sra. /// srl/add/sra.
bool isPow2DivCheap() const { return Pow2DivIsCheap; } bool isPow2DivCheap() const { return Pow2DivIsCheap; }
/// isJumpExpensive() - Return true if Flow Control is an expensive opera tion /// isJumpExpensive() - Return true if Flow Control is an expensive opera tion
/// that should be avoided. /// that should be avoided.
bool isJumpExpensive() const { return JumpIsExpensive; } bool isJumpExpensive() const { return JumpIsExpensive; }
/// isPredictableSelectExpensive - Return true if selects are only cheape
r
/// than branches if the branch is unlikely to be predicted right.
bool isPredictableSelectExpensive() const {
return predictableSelectIsExpensive;
}
/// getSetCCResultType - Return the ValueType of the result of SETCC /// getSetCCResultType - Return the ValueType of the result of SETCC
/// operations. Also used to obtain the target's preferred type for /// operations. Also used to obtain the target's preferred type for
/// the condition operand of SELECT and BRCOND nodes. In the case of /// the condition operand of SELECT and BRCOND nodes. In the case of
/// BRCOND the argument passed is MVT::Other since there are no other /// BRCOND the argument passed is MVT::Other since there are no other
/// operands to get a type hint from. /// operands to get a type hint from.
virtual EVT getSetCCResultType(EVT VT) const; virtual EVT getSetCCResultType(EVT VT) const;
/// getCmpLibcallReturnType - Return the ValueType for comparison /// getCmpLibcallReturnType - Return the ValueType for comparison
/// libcalls. Comparions libcalls include floating point comparion calls, /// libcalls. Comparions libcalls include floating point comparion calls,
/// and Ordered/Unordered check calls on floating point numbers. /// and Ordered/Unordered check calls on floating point numbers.
skipping to change at line 360 skipping to change at line 397
EVT /*VT*/) const { EVT /*VT*/) const {
return false; return false;
} }
/// getOperationAction - Return how this operation should be treated: eit her /// getOperationAction - Return how this operation should be treated: eit her
/// it is legal, needs to be promoted to a larger size, needs to be /// it is legal, needs to be promoted to a larger size, needs to be
/// expanded to some other code sequence, or the target has a custom expa nder /// expanded to some other code sequence, or the target has a custom expa nder
/// for it. /// for it.
LegalizeAction getOperationAction(unsigned Op, EVT VT) const { LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
if (VT.isExtended()) return Expand; if (VT.isExtended()) return Expand;
assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!"); // If a target-specific SDNode requires legalization, require the targe
t
// to provide custom legalization for it.
if (Op > array_lengthof(OpActions[0])) return Custom;
unsigned I = (unsigned) VT.getSimpleVT().SimpleTy; unsigned I = (unsigned) VT.getSimpleVT().SimpleTy;
return (LegalizeAction)OpActions[I][Op]; return (LegalizeAction)OpActions[I][Op];
} }
/// isOperationLegalOrCustom - Return true if the specified operation is /// isOperationLegalOrCustom - Return true if the specified operation is
/// legal on this target or can be made legal with custom lowering. This /// legal on this target or can be made legal with custom lowering. This
/// is used to help guide high-level lowering decisions. /// is used to help guide high-level lowering decisions.
bool isOperationLegalOrCustom(unsigned Op, EVT VT) const { bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
return (VT == MVT::Other || isTypeLegal(VT)) && return (VT == MVT::Other || isTypeLegal(VT)) &&
(getOperationAction(Op, VT) == Legal || (getOperationAction(Op, VT) == Legal ||
getOperationAction(Op, VT) == Custom); getOperationAction(Op, VT) == Custom);
} }
/// isOperationExpand - Return true if the specified operation is illegal
on
/// this target or unlikely to be made legal with custom lowering. This i
s
/// used to help guide high-level lowering decisions.
bool isOperationExpand(unsigned Op, EVT VT) const {
return (!isTypeLegal(VT) || getOperationAction(Op, VT) == Expand);
}
/// isOperationLegal - Return true if the specified operation is legal on this /// isOperationLegal - Return true if the specified operation is legal on this
/// target. /// target.
bool isOperationLegal(unsigned Op, EVT VT) const { bool isOperationLegal(unsigned Op, EVT VT) const {
return (VT == MVT::Other || isTypeLegal(VT)) && return (VT == MVT::Other || isTypeLegal(VT)) &&
getOperationAction(Op, VT) == Legal; getOperationAction(Op, VT) == Legal;
} }
/// getLoadExtAction - Return how this load with extension should be trea ted: /// getLoadExtAction - Return how this load with extension should be trea ted:
/// either it is legal, needs to be promoted to a larger size, needs to b e /// either it is legal, needs to be promoted to a larger size, needs to b e
/// expanded to some other code sequence, or the target has a custom expa nder /// expanded to some other code sequence, or the target has a custom expa nder
skipping to change at line 467 skipping to change at line 513
} }
/// getCondCodeAction - Return how the condition code should be treated: /// getCondCodeAction - Return how the condition code should be treated:
/// either it is legal, needs to be expanded to some other code sequence, /// either it is legal, needs to be expanded to some other code sequence,
/// or the target has a custom expander for it. /// or the target has a custom expander for it.
LegalizeAction LegalizeAction
getCondCodeAction(ISD::CondCode CC, EVT VT) const { getCondCodeAction(ISD::CondCode CC, EVT VT) const {
assert((unsigned)CC < array_lengthof(CondCodeActions) && assert((unsigned)CC < array_lengthof(CondCodeActions) &&
(unsigned)VT.getSimpleVT().SimpleTy < sizeof(CondCodeActions[0]) *4 && (unsigned)VT.getSimpleVT().SimpleTy < sizeof(CondCodeActions[0]) *4 &&
"Table isn't big enough!"); "Table isn't big enough!");
/// The lower 5 bits of the SimpleTy index into Nth 2bit set from the 6
4bit
/// value and the upper 27 bits index into the second dimension of the
/// array to select what 64bit value to use.
LegalizeAction Action = (LegalizeAction) LegalizeAction Action = (LegalizeAction)
((CondCodeActions[CC] >> (2*VT.getSimpleVT().SimpleTy)) & 3); ((CondCodeActions[CC][VT.getSimpleVT().SimpleTy >> 5]
>> (2*(VT.getSimpleVT().SimpleTy & 0x1F))) & 3);
assert(Action != Promote && "Can't promote condition code!"); assert(Action != Promote && "Can't promote condition code!");
return Action; return Action;
} }
/// isCondCodeLegal - Return true if the specified condition code is lega l /// isCondCodeLegal - Return true if the specified condition code is lega l
/// on this target. /// on this target.
bool isCondCodeLegal(ISD::CondCode CC, EVT VT) const { bool isCondCodeLegal(ISD::CondCode CC, EVT VT) const {
return getCondCodeAction(CC, VT) == Legal || return getCondCodeAction(CC, VT) == Legal ||
getCondCodeAction(CC, VT) == Custom; getCondCodeAction(CC, VT) == Custom;
} }
skipping to change at line 671 skipping to change at line 721
bool usesUnderscoreSetJmp() const { bool usesUnderscoreSetJmp() const {
return UseUnderscoreSetJmp; return UseUnderscoreSetJmp;
} }
/// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjm p /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjm p
/// to implement llvm.longjmp. /// to implement llvm.longjmp.
bool usesUnderscoreLongJmp() const { bool usesUnderscoreLongJmp() const {
return UseUnderscoreLongJmp; return UseUnderscoreLongJmp;
} }
/// supportJumpTables - return whether the target can generate code for
/// jump tables.
bool supportJumpTables() const {
return SupportJumpTables;
}
/// getMinimumJumpTableEntries - return integer threshold on number of
/// blocks to use jump tables rather than if sequence.
int getMinimumJumpTableEntries() const {
return MinimumJumpTableEntries;
}
/// getStackPointerRegisterToSaveRestore - If a physical register, this /// getStackPointerRegisterToSaveRestore - If a physical register, this
/// specifies the register that llvm.savestack/llvm.restorestack should s ave /// specifies the register that llvm.savestack/llvm.restorestack should s ave
/// and restore. /// and restore.
unsigned getStackPointerRegisterToSaveRestore() const { unsigned getStackPointerRegisterToSaveRestore() const {
return StackPointerRegisterToSaveRestore; return StackPointerRegisterToSaveRestore;
} }
/// getExceptionPointerRegister - If a physical register, this returns /// getExceptionPointerRegister - If a physical register, this returns
/// the register that receives the exception address on entry to a landin g /// the register that receives the exception address on entry to a landin g
/// pad. /// pad.
skipping to change at line 985 skipping to change at line 1047
UseUnderscoreSetJmp = Val; UseUnderscoreSetJmp = Val;
} }
/// setUseUnderscoreLongJmp - Indicate whether this target prefers to /// setUseUnderscoreLongJmp - Indicate whether this target prefers to
/// use _longjmp to implement llvm.longjmp or the non _ version. /// use _longjmp to implement llvm.longjmp or the non _ version.
/// Defaults to false. /// Defaults to false.
void setUseUnderscoreLongJmp(bool Val) { void setUseUnderscoreLongJmp(bool Val) {
UseUnderscoreLongJmp = Val; UseUnderscoreLongJmp = Val;
} }
/// setSupportJumpTables - Indicate whether the target can generate code
for
/// jump tables.
void setSupportJumpTables(bool Val) {
SupportJumpTables = Val;
}
/// setMinimumJumpTableEntries - Indicate the number of blocks to generat
e
/// jump tables rather than if sequence.
void setMinimumJumpTableEntries(int Val) {
MinimumJumpTableEntries = Val;
}
/// setStackPointerRegisterToSaveRestore - If set to a physical register, this /// setStackPointerRegisterToSaveRestore - If set to a physical register, this
/// specifies the register that llvm.savestack/llvm.restorestack should s ave /// specifies the register that llvm.savestack/llvm.restorestack should s ave
/// and restore. /// and restore.
void setStackPointerRegisterToSaveRestore(unsigned R) { void setStackPointerRegisterToSaveRestore(unsigned R) {
StackPointerRegisterToSaveRestore = R; StackPointerRegisterToSaveRestore = R;
} }
/// setExceptionPointerRegister - If set to a physical register, this set s /// setExceptionPointerRegister - If set to a physical register, this set s
/// the register that receives the exception address on entry to a landin g /// the register that receives the exception address on entry to a landin g
/// pad. /// pad.
skipping to change at line 1024 skipping to change at line 1098
/// flow control. /// flow control.
void setJumpIsExpensive(bool isExpensive = true) { void setJumpIsExpensive(bool isExpensive = true) {
JumpIsExpensive = isExpensive; JumpIsExpensive = isExpensive;
} }
/// setIntDivIsCheap - Tells the code generator that integer divide is /// setIntDivIsCheap - Tells the code generator that integer divide is
/// expensive, and if possible, should be replaced by an alternate sequen ce /// expensive, and if possible, should be replaced by an alternate sequen ce
/// of instructions not containing an integer divide. /// of instructions not containing an integer divide.
void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; } void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; }
/// addBypassSlowDiv - Tells the code generator which bitwidths to bypass
.
void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidt
h) {
BypassSlowDivWidths[SlowBitWidth] = FastBitWidth;
}
/// setPow2DivIsCheap - Tells the code generator that it shouldn't genera te /// setPow2DivIsCheap - Tells the code generator that it shouldn't genera te
/// srl/add/sra for a signed divide by power of two, and let the target h andle /// srl/add/sra for a signed divide by power of two, and let the target h andle
/// it. /// it.
void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; } void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; }
/// addRegisterClass - Add the specified register class as an available /// addRegisterClass - Add the specified register class as an available
/// regclass for the specified value type. This indicates the selector c an /// regclass for the specified value type. This indicates the selector c an
/// handle values of that class natively. /// handle values of that class natively.
void addRegisterClass(EVT VT, const TargetRegisterClass *RC) { void addRegisterClass(EVT VT, const TargetRegisterClass *RC) {
assert((unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassFor VT)); assert((unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassFor VT));
skipping to change at line 1106 skipping to change at line 1185
IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) ; IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) ;
} }
/// setCondCodeAction - Indicate that the specified condition code is or isn't /// setCondCodeAction - Indicate that the specified condition code is or isn't
/// supported on the target and indicate what to do about it. /// supported on the target and indicate what to do about it.
void setCondCodeAction(ISD::CondCode CC, MVT VT, void setCondCodeAction(ISD::CondCode CC, MVT VT,
LegalizeAction Action) { LegalizeAction Action) {
assert(VT < MVT::LAST_VALUETYPE && assert(VT < MVT::LAST_VALUETYPE &&
(unsigned)CC < array_lengthof(CondCodeActions) && (unsigned)CC < array_lengthof(CondCodeActions) &&
"Table isn't big enough!"); "Table isn't big enough!");
CondCodeActions[(unsigned)CC] &= ~(uint64_t(3UL) << VT.SimpleTy*2); /// The lower 5 bits of the SimpleTy index into Nth 2bit set from the 6
CondCodeActions[(unsigned)CC] |= (uint64_t)Action << VT.SimpleTy*2; 4bit
/// value and the upper 27 bits index into the second dimension of the
/// array to select what 64bit value to use.
CondCodeActions[(unsigned)CC][VT.SimpleTy >> 5]
&= ~(uint64_t(3UL) << (VT.SimpleTy & 0x1F)*2);
CondCodeActions[(unsigned)CC][VT.SimpleTy >> 5]
|= (uint64_t)Action << (VT.SimpleTy & 0x1F)*2;
} }
/// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the
/// promotion code defaults to trying a larger integer/fp until it can fi nd /// promotion code defaults to trying a larger integer/fp until it can fi nd
/// one that works. If that default is insufficient, this method can be used /// one that works. If that default is insufficient, this method can be used
/// by the target to override the default. /// by the target to override the default.
void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) { void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy; PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
} }
skipping to change at line 1170 skipping to change at line 1254
void setMinStackArgumentAlignment(unsigned Align) { void setMinStackArgumentAlignment(unsigned Align) {
MinStackArgumentAlignment = Align; MinStackArgumentAlignment = Align;
} }
/// setShouldFoldAtomicFences - Set if the target's implementation of the /// setShouldFoldAtomicFences - Set if the target's implementation of the
/// atomic operation intrinsics includes locking. Default is false. /// atomic operation intrinsics includes locking. Default is false.
void setShouldFoldAtomicFences(bool fold) { void setShouldFoldAtomicFences(bool fold) {
ShouldFoldAtomicFences = fold; ShouldFoldAtomicFences = fold;
} }
/// setInsertFencesForAtomic - Set if the the DAG builder should /// setInsertFencesForAtomic - Set if the DAG builder should
/// automatically insert fences and reduce the order of atomic memory /// automatically insert fences and reduce the order of atomic memory
/// operations to Monotonic. /// operations to Monotonic.
void setInsertFencesForAtomic(bool fence) { void setInsertFencesForAtomic(bool fence) {
InsertFencesForAtomic = fence; InsertFencesForAtomic = fence;
} }
public: public:
//===-------------------------------------------------------------------- ===// //===-------------------------------------------------------------------- ===//
// Lowering methods - These methods must be implemented by targets so tha t // Lowering methods - These methods must be implemented by targets so tha t
// the SelectionDAGLowering code knows how to lower these. // the SelectionDAGBuilder code knows how to lower these.
// //
/// LowerFormalArguments - This hook must be implemented to lower the /// LowerFormalArguments - This hook must be implemented to lower the
/// incoming (formal) arguments, described by the Ins array, into the /// incoming (formal) arguments, described by the Ins array, into the
/// specified DAG. The implementation should fill in the InVals array /// specified DAG. The implementation should fill in the InVals array
/// with legal-type argument values, and return the resulting token /// with legal-type argument values, and return the resulting token
/// chain value. /// chain value.
/// ///
virtual SDValue virtual SDValue
LowerFormalArguments(SDValue /*Chain*/, CallingConv::ID /*CallConv*/, LowerFormalArguments(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
bool /*isVarArg*/, bool /*isVarArg*/,
const SmallVectorImpl<ISD::InputArg> &/*Ins*/, const SmallVectorImpl<ISD::InputArg> &/*Ins*/,
DebugLoc /*dl*/, SelectionDAG &/*DAG*/, DebugLoc /*dl*/, SelectionDAG &/*DAG*/,
SmallVectorImpl<SDValue> &/*InVals*/) const { SmallVectorImpl<SDValue> &/*InVals*/) const {
llvm_unreachable("Not Implemented"); llvm_unreachable("Not Implemented");
} }
/// LowerCallTo - This function lowers an abstract call to a function int
o an
/// actual call. This returns a pair of operands. The first element is
the
/// return value for the function (if RetTy is not VoidTy). The second
/// element is the outgoing token chain. It calls LowerCall to do the act
ual
/// lowering.
struct ArgListEntry { struct ArgListEntry {
SDValue Node; SDValue Node;
Type* Ty; Type* Ty;
bool isSExt : 1; bool isSExt : 1;
bool isZExt : 1; bool isZExt : 1;
bool isInReg : 1; bool isInReg : 1;
bool isSRet : 1; bool isSRet : 1;
bool isNest : 1; bool isNest : 1;
bool isByVal : 1; bool isByVal : 1;
uint16_t Alignment; uint16_t Alignment;
ArgListEntry() : isSExt(false), isZExt(false), isInReg(false), ArgListEntry() : isSExt(false), isZExt(false), isInReg(false),
isSRet(false), isNest(false), isByVal(false), Alignment(0) { } isSRet(false), isNest(false), isByVal(false), Alignment(0) { }
}; };
typedef std::vector<ArgListEntry> ArgListTy; typedef std::vector<ArgListEntry> ArgListTy;
std::pair<SDValue, SDValue>
LowerCallTo(SDValue Chain, Type *RetTy, bool RetSExt, bool RetZExt, /// CallLoweringInfo - This structure contains all information that is
bool isVarArg, bool isInreg, unsigned NumFixedArgs, /// necessary for lowering calls. It is passed to TLI::LowerCallTo when t
CallingConv::ID CallConv, bool isTailCall, he
bool doesNotRet, bool isReturnValueUsed, /// SelectionDAG builder needs to lower a call, and targets will see this
SDValue Callee, ArgListTy &Args, /// struct in their LowerCall implementation.
SelectionDAG &DAG, DebugLoc dl) const; struct CallLoweringInfo {
SDValue Chain;
Type *RetTy;
bool RetSExt : 1;
bool RetZExt : 1;
bool IsVarArg : 1;
bool IsInReg : 1;
bool DoesNotReturn : 1;
bool IsReturnValueUsed : 1;
// IsTailCall should be modified by implementations of
// TargetLowering::LowerCall that perform tail call conversions.
bool IsTailCall;
unsigned NumFixedArgs;
CallingConv::ID CallConv;
SDValue Callee;
ArgListTy &Args;
SelectionDAG &DAG;
DebugLoc DL;
ImmutableCallSite *CS;
SmallVector<ISD::OutputArg, 32> Outs;
SmallVector<SDValue, 32> OutVals;
SmallVector<ISD::InputArg, 32> Ins;
/// CallLoweringInfo - Constructs a call lowering context based on the
/// ImmutableCallSite \p cs.
CallLoweringInfo(SDValue chain, Type *retTy,
FunctionType *FTy, bool isTailCall, SDValue callee,
ArgListTy &args, SelectionDAG &dag, DebugLoc dl,
ImmutableCallSite &cs)
: Chain(chain), RetTy(retTy), RetSExt(cs.paramHasAttr(0, Attributes::SE
xt)),
RetZExt(cs.paramHasAttr(0, Attributes::ZExt)), IsVarArg(FTy->isVarArg
()),
IsInReg(cs.paramHasAttr(0, Attributes::InReg)),
DoesNotReturn(cs.doesNotReturn()),
IsReturnValueUsed(!cs.getInstruction()->use_empty()),
IsTailCall(isTailCall), NumFixedArgs(FTy->getNumParams()),
CallConv(cs.getCallingConv()), Callee(callee), Args(args), DAG(dag),
DL(dl), CS(&cs) {}
/// CallLoweringInfo - Constructs a call lowering context based on the
/// provided call information.
CallLoweringInfo(SDValue chain, Type *retTy, bool retSExt, bool retZExt
,
bool isVarArg, bool isInReg, unsigned numFixedArgs,
CallingConv::ID callConv, bool isTailCall,
bool doesNotReturn, bool isReturnValueUsed, SDValue ca
llee,
ArgListTy &args, SelectionDAG &dag, DebugLoc dl)
: Chain(chain), RetTy(retTy), RetSExt(retSExt), RetZExt(retZExt),
IsVarArg(isVarArg), IsInReg(isInReg), DoesNotReturn(doesNotReturn),
IsReturnValueUsed(isReturnValueUsed), IsTailCall(isTailCall),
NumFixedArgs(numFixedArgs), CallConv(callConv), Callee(callee),
Args(args), DAG(dag), DL(dl), CS(NULL) {}
};
/// LowerCallTo - This function lowers an abstract call to a function int
o an
/// actual call. This returns a pair of operands. The first element is
the
/// return value for the function (if RetTy is not VoidTy). The second
/// element is the outgoing token chain. It calls LowerCall to do the act
ual
/// lowering.
std::pair<SDValue, SDValue> LowerCallTo(CallLoweringInfo &CLI) const;
/// LowerCall - This hook must be implemented to lower calls into the /// LowerCall - This hook must be implemented to lower calls into the
/// the specified DAG. The outgoing arguments to the call are described /// the specified DAG. The outgoing arguments to the call are described
/// by the Outs array, and the values to be returned by the call are /// by the Outs array, and the values to be returned by the call are
/// described by the Ins array. The implementation should fill in the /// described by the Ins array. The implementation should fill in the
/// InVals array with legal-type return values from the call, and return /// InVals array with legal-type return values from the call, and return
/// the resulting token chain value. /// the resulting token chain value.
virtual SDValue virtual SDValue
LowerCall(SDValue /*Chain*/, SDValue /*Callee*/, LowerCall(CallLoweringInfo &/*CLI*/,
CallingConv::ID /*CallConv*/, bool /*isVarArg*/,
bool /*doesNotRet*/, bool &/*isTailCall*/,
const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
const SmallVectorImpl<SDValue> &/*OutVals*/,
const SmallVectorImpl<ISD::InputArg> &/*Ins*/,
DebugLoc /*dl*/, SelectionDAG &/*DAG*/,
SmallVectorImpl<SDValue> &/*InVals*/) const { SmallVectorImpl<SDValue> &/*InVals*/) const {
llvm_unreachable("Not Implemented"); llvm_unreachable("Not Implemented");
} }
/// HandleByVal - Target-specific cleanup for formal ByVal parameters. /// HandleByVal - Target-specific cleanup for formal ByVal parameters.
virtual void HandleByVal(CCState *, unsigned &) const {} virtual void HandleByVal(CCState *, unsigned &, unsigned) const {}
/// CanLowerReturn - This hook should be implemented to check whether the /// CanLowerReturn - This hook should be implemented to check whether the
/// return values described by the Outs array can fit into the return /// return values described by the Outs array can fit into the return
/// registers. If false is returned, an sret-demotion is performed. /// registers. If false is returned, an sret-demotion is performed.
/// ///
virtual bool CanLowerReturn(CallingConv::ID /*CallConv*/, virtual bool CanLowerReturn(CallingConv::ID /*CallConv*/,
MachineFunction &/*MF*/, bool /*isVarArg*/, MachineFunction &/*MF*/, bool /*isVarArg*/,
const SmallVectorImpl<ISD::OutputArg> &/*Outs*/, const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
LLVMContext &/*Context*/) const LLVMContext &/*Context*/) const
{ {
// Return true by default to get preexisting behavior. // Return true by default to get preexisting behavior.
return true; return true;
} }
/// LowerReturn - This hook must be implemented to lower outgoing /// LowerReturn - This hook must be implemented to lower outgoing
/// return values, described by the Outs array, into the specified /// return values, described by the Outs array, into the specified
/// DAG. The implementation should return the resulting token chain /// DAG. The implementation should return the resulting token chain
skipping to change at line 1347 skipping to change at line 1478
SelectionDAG &/*DAG*/) const { SelectionDAG &/*DAG*/) const {
llvm_unreachable("ReplaceNodeResults not implemented for this target!") ; llvm_unreachable("ReplaceNodeResults not implemented for this target!") ;
} }
/// getTargetNodeName() - This method returns the name of a target specif ic /// getTargetNodeName() - This method returns the name of a target specif ic
/// DAG node. /// DAG node.
virtual const char *getTargetNodeName(unsigned Opcode) const; virtual const char *getTargetNodeName(unsigned Opcode) const;
/// createFastISel - This method returns a target specific FastISel objec t, /// createFastISel - This method returns a target specific FastISel objec t,
/// or null if the target does not support "fast" ISel. /// or null if the target does not support "fast" ISel.
virtual FastISel *createFastISel(FunctionLoweringInfo &) const { virtual FastISel *createFastISel(FunctionLoweringInfo &,
const TargetLibraryInfo *) const {
return 0; return 0;
} }
//===-------------------------------------------------------------------- ===// //===-------------------------------------------------------------------- ===//
// Inline Asm Support hooks // Inline Asm Support hooks
// //
/// ExpandInlineAsm - This hook allows the target to expand an inline asm /// ExpandInlineAsm - This hook allows the target to expand an inline asm
/// call to be explicit llvm code if it wants to. This is useful for /// call to be explicit llvm code if it wants to. This is useful for
/// turning simple inline asms into LLVM intrinsics, which gives the /// turning simple inline asms into LLVM intrinsics, which gives the
skipping to change at line 1514 skipping to change at line 1646
/// targets that mark instructions with the 'hasPostISelHook' flag. These /// targets that mark instructions with the 'hasPostISelHook' flag. These
/// instructions must be adjusted after instruction selection by target h ooks. /// instructions must be adjusted after instruction selection by target h ooks.
/// e.g. To fill in optional defs for ARM 's' setting instructions. /// e.g. To fill in optional defs for ARM 's' setting instructions.
virtual void virtual void
AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const; AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const;
//===-------------------------------------------------------------------- ===// //===-------------------------------------------------------------------- ===//
// Addressing mode description hooks (used by LSR etc). // Addressing mode description hooks (used by LSR etc).
// //
/// AddrMode - This represents an addressing mode of:
/// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
/// If BaseGV is null, there is no BaseGV.
/// If BaseOffs is zero, there is no base offset.
/// If HasBaseReg is false, there is no base register.
/// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg w
ith
/// no scale.
///
struct AddrMode {
GlobalValue *BaseGV;
int64_t BaseOffs;
bool HasBaseReg;
int64_t Scale;
AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {}
};
/// GetAddrModeArguments - CodeGenPrepare sinks address calculations into the /// GetAddrModeArguments - CodeGenPrepare sinks address calculations into the
/// same BB as Load/Store instructions reading the address. This allows as /// same BB as Load/Store instructions reading the address. This allows as
/// much computation as possible to be done in the address mode for that /// much computation as possible to be done in the address mode for that
/// operand. This hook lets targets also pass back when this should be d one /// operand. This hook lets targets also pass back when this should be d one
/// on intrinsics which load/store. /// on intrinsics which load/store.
virtual bool GetAddrModeArguments(IntrinsicInst *I, virtual bool GetAddrModeArguments(IntrinsicInst *I,
SmallVectorImpl<Value*> &Ops, SmallVectorImpl<Value*> &Ops,
Type *&AccessTy) const { Type *&AccessTy) const {
return false; return false;
} }
skipping to change at line 1603 skipping to change at line 1719
virtual bool isFNegFree(EVT) const { virtual bool isFNegFree(EVT) const {
return false; return false;
} }
/// isFAbsFree - Return true if an fneg operation is free to the point wh ere /// isFAbsFree - Return true if an fneg operation is free to the point wh ere
/// it is never worthwhile to replace it with a bitwise operation. /// it is never worthwhile to replace it with a bitwise operation.
virtual bool isFAbsFree(EVT) const { virtual bool isFAbsFree(EVT) const {
return false; return false;
} }
/// isFMAFasterThanMulAndAdd - Return true if an FMA operation is faster
than
/// a pair of mul and add instructions. fmuladd intrinsics will be expand
ed to
/// FMAs when this method returns true (and FMAs are legal), otherwise fm
uladd
/// is expanded to mul + add.
virtual bool isFMAFasterThanMulAndAdd(EVT) const {
return false;
}
/// isNarrowingProfitable - Return true if it's profitable to narrow /// isNarrowingProfitable - Return true if it's profitable to narrow
/// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
/// from i32 to i8 but not from i32 to i16. /// from i32 to i8 but not from i32 to i16.
virtual bool isNarrowingProfitable(EVT /*VT1*/, EVT /*VT2*/) const { virtual bool isNarrowingProfitable(EVT /*VT1*/, EVT /*VT2*/) const {
return false; return false;
} }
//===-------------------------------------------------------------------- ===// //===-------------------------------------------------------------------- ===//
// Div utility functions // Div utility functions
// //
skipping to change at line 1662 skipping to change at line 1786
} }
/// getLibcallCallingConv - Get the CallingConv that should be used for t he /// getLibcallCallingConv - Get the CallingConv that should be used for t he
/// specified libcall. /// specified libcall.
CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const { CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const {
return LibcallCallingConvs[Call]; return LibcallCallingConvs[Call];
} }
private: private:
const TargetMachine &TM; const TargetMachine &TM;
const TargetData *TD; const DataLayout *TD;
const TargetLoweringObjectFile &TLOF; const TargetLoweringObjectFile &TLOF;
/// We are in the process of implementing a new TypeLegalization action /// PointerTy - The type to use for pointers for the default address spac
/// which is the promotion of vector elements. This feature is under e,
/// development. Until this feature is complete, it is only enabled using /// usually i32 or i64.
a
/// flag. We pass this flag using a member because of circular dep issues
.
/// This member will be removed with the flag once we complete the transi
tion.
bool mayPromoteElements;
/// PointerTy - The type to use for pointers, usually i32 or i64.
/// ///
MVT PointerTy; MVT PointerTy;
/// IsLittleEndian - True if this is a little endian target. /// IsLittleEndian - True if this is a little endian target.
/// ///
bool IsLittleEndian; bool IsLittleEndian;
/// SelectIsExpensive - Tells the code generator not to expand operations /// SelectIsExpensive - Tells the code generator not to expand operations
/// into sequences that use the select operations if possible. /// into sequences that use the select operations if possible.
bool SelectIsExpensive; bool SelectIsExpensive;
/// IntDivIsCheap - Tells the code generator not to expand integer divide s by /// IntDivIsCheap - Tells the code generator not to expand integer divide s by
/// constants into a sequence of muls, adds, and shifts. This is a hack until /// constants into a sequence of muls, adds, and shifts. This is a hack until
/// a real cost model is in place. If we ever optimize for size, this wi ll be /// a real cost model is in place. If we ever optimize for size, this wi ll be
/// set to true unconditionally. /// set to true unconditionally.
bool IntDivIsCheap; bool IntDivIsCheap;
/// BypassSlowDivMap - Tells the code generator to bypass slow divide or
/// remainder instructions. For example, BypassSlowDivWidths[32,8] tells
the
/// code generator to bypass 32-bit integer div/rem with an 8-bit unsigne
d
/// integer div/rem when the operands are positive and less than 256.
DenseMap <unsigned int, unsigned int> BypassSlowDivWidths;
/// Pow2DivIsCheap - Tells the code generator that it shouldn't generate /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate
/// srl/add/sra for a signed divide by power of two, and let the target h andle /// srl/add/sra for a signed divide by power of two, and let the target h andle
/// it. /// it.
bool Pow2DivIsCheap; bool Pow2DivIsCheap;
/// JumpIsExpensive - Tells the code generator that it shouldn't generate /// JumpIsExpensive - Tells the code generator that it shouldn't generate
/// extra flow control instructions and should attempt to combine flow /// extra flow control instructions and should attempt to combine flow
/// control instructions via predication. /// control instructions via predication.
bool JumpIsExpensive; bool JumpIsExpensive;
/// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement
/// llvm.setjmp. Defaults to false. /// llvm.setjmp. Defaults to false.
bool UseUnderscoreSetJmp; bool UseUnderscoreSetJmp;
/// UseUnderscoreLongJmp - This target prefers to use _longjmp to impleme nt /// UseUnderscoreLongJmp - This target prefers to use _longjmp to impleme nt
/// llvm.longjmp. Defaults to false. /// llvm.longjmp. Defaults to false.
bool UseUnderscoreLongJmp; bool UseUnderscoreLongJmp;
/// SupportJumpTables - Whether the target can generate code for jumptabl
es.
/// If it's not true, then each jumptable must be lowered into if-then-el
se's.
bool SupportJumpTables;
/// MinimumJumpTableEntries - Number of blocks threshold to use jump tabl
es.
int MinimumJumpTableEntries;
/// BooleanContents - Information about the contents of the high-bits in /// BooleanContents - Information about the contents of the high-bits in
/// boolean values held in a type wider than i1. See getBooleanContents. /// boolean values held in a type wider than i1. See getBooleanContents.
BooleanContent BooleanContents; BooleanContent BooleanContents;
/// BooleanVectorContents - Information about the contents of the high-bi ts /// BooleanVectorContents - Information about the contents of the high-bi ts
/// in boolean vector values when the element type is wider than i1. See /// in boolean vector values when the element type is wider than i1. See
/// getBooleanContents. /// getBooleanContents.
BooleanContent BooleanVectorContents; BooleanContent BooleanVectorContents;
/// SchedPreferenceInfo - The target scheduling preference: shortest poss ible /// SchedPreferenceInfo - The target scheduling preference: shortest poss ible
/// total cycles or lowest register usage. /// total cycles or lowest register usage.
skipping to change at line 1825 skipping to change at line 1956
/// IndexedModeActions - For each indexed mode and each value type, /// IndexedModeActions - For each indexed mode and each value type,
/// keep a pair of LegalizeAction that indicates how instruction /// keep a pair of LegalizeAction that indicates how instruction
/// selection should deal with the load / store. The first dimension is the /// selection should deal with the load / store. The first dimension is the
/// value_type for the reference. The second dimension represents the var ious /// value_type for the reference. The second dimension represents the var ious
/// modes for load store. /// modes for load store.
uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE]; uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE];
/// CondCodeActions - For each condition code (ISD::CondCode) keep a /// CondCodeActions - For each condition code (ISD::CondCode) keep a
/// LegalizeAction that indicates how instruction selection should /// LegalizeAction that indicates how instruction selection should
/// deal with the condition code. /// deal with the condition code.
uint64_t CondCodeActions[ISD::SETCC_INVALID]; /// Because each CC action takes up 2 bits, we need to have the array siz
e
/// be large enough to fit all of the value types. This can be done by
/// dividing the MVT::LAST_VALUETYPE by 32 and adding one.
uint64_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE / 32) +
1];
ValueTypeActionImpl ValueTypeActions; ValueTypeActionImpl ValueTypeActions;
typedef std::pair<LegalizeTypeAction, EVT> LegalizeKind; public:
LegalizeKind LegalizeKind
getTypeConversion(LLVMContext &Context, EVT VT) const { getTypeConversion(LLVMContext &Context, EVT VT) const {
// If this is a simple type, use the ComputeRegisterProp mechanism. // If this is a simple type, use the ComputeRegisterProp mechanism.
if (VT.isSimple()) { if (VT.isSimple()) {
assert((unsigned)VT.getSimpleVT().SimpleTy < assert((unsigned)VT.getSimpleVT().SimpleTy <
array_lengthof(TransformToType)); array_lengthof(TransformToType));
EVT NVT = TransformToType[VT.getSimpleVT().SimpleTy]; EVT NVT = TransformToType[VT.getSimpleVT().SimpleTy];
LegalizeTypeAction LA = ValueTypeActions.getTypeAction(VT.getSimpleVT ()); LegalizeTypeAction LA = ValueTypeActions.getTypeAction(VT.getSimpleVT ());
assert( assert(
(!(NVT.isSimple() && LA != TypeLegal) || (!(NVT.isSimple() && LA != TypeLegal) ||
ValueTypeActions.getTypeAction(NVT.getSimpleVT()) != TypePromoteIn teger) ValueTypeActions.getTypeAction(NVT.getSimpleVT()) != TypePromoteIn teger)
&& "Promote may not follow Expand or Promote"); && "Promote may not follow Expand or Promote");
if (LA == TypeSplitVector)
NVT = EVT::getVectorVT(Context, VT.getVectorElementType(),
VT.getVectorNumElements() / 2);
return LegalizeKind(LA, NVT); return LegalizeKind(LA, NVT);
} }
// Handle Extended Scalar Types. // Handle Extended Scalar Types.
if (!VT.isVector()) { if (!VT.isVector()) {
assert(VT.isInteger() && "Float types must be simple"); assert(VT.isInteger() && "Float types must be simple");
unsigned BitSize = VT.getSizeInBits(); unsigned BitSize = VT.getSizeInBits();
// First promote to a power-of-two size, then expand if necessary. // First promote to a power-of-two size, then expand if necessary.
if (BitSize < 8 || !isPowerOf2_32(BitSize)) { if (BitSize < 8 || !isPowerOf2_32(BitSize)) {
EVT NVT = VT.getRoundIntegerType(Context); EVT NVT = VT.getRoundIntegerType(Context);
skipping to change at line 1875 skipping to change at line 2011
} }
// Handle vector types. // Handle vector types.
unsigned NumElts = VT.getVectorNumElements(); unsigned NumElts = VT.getVectorNumElements();
EVT EltVT = VT.getVectorElementType(); EVT EltVT = VT.getVectorElementType();
// Vectors with only one element are always scalarized. // Vectors with only one element are always scalarized.
if (NumElts == 1) if (NumElts == 1)
return LegalizeKind(TypeScalarizeVector, EltVT); return LegalizeKind(TypeScalarizeVector, EltVT);
// If we allow the promotion of vector elements using a flag, // Try to widen vector elements until a legal type is found.
// then try to widen vector elements until a legal type is found. if (EltVT.isInteger()) {
if (mayPromoteElements && EltVT.isInteger()) {
// Vectors with a number of elements that is not a power of two are a lways // Vectors with a number of elements that is not a power of two are a lways
// widened, for example <3 x float> -> <4 x float>. // widened, for example <3 x float> -> <4 x float>.
if (!VT.isPow2VectorType()) { if (!VT.isPow2VectorType()) {
NumElts = (unsigned)NextPowerOf2(NumElts); NumElts = (unsigned)NextPowerOf2(NumElts);
EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts); EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts);
return LegalizeKind(TypeWidenVector, NVT); return LegalizeKind(TypeWidenVector, NVT);
} }
// Examine the element type. // Examine the element type.
LegalizeKind LK = getTypeConversion(Context, EltVT); LegalizeKind LK = getTypeConversion(Context, EltVT);
skipping to change at line 1948 skipping to change at line 2083
if (!VT.isPow2VectorType()) { if (!VT.isPow2VectorType()) {
EVT NVT = VT.getPow2VectorType(Context); EVT NVT = VT.getPow2VectorType(Context);
return LegalizeKind(TypeWidenVector, NVT); return LegalizeKind(TypeWidenVector, NVT);
} }
// Vectors with illegal element types are expanded. // Vectors with illegal element types are expanded.
EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorNumElements() / 2); EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorNumElements() / 2);
return LegalizeKind(TypeSplitVector, NVT); return LegalizeKind(TypeSplitVector, NVT);
} }
private:
std::vector<std::pair<EVT, const TargetRegisterClass*> > AvailableRegClas ses; std::vector<std::pair<EVT, const TargetRegisterClass*> > AvailableRegClas ses;
/// TargetDAGCombineArray - Targets can specify ISD nodes that they would /// TargetDAGCombineArray - Targets can specify ISD nodes that they would
/// like PerformDAGCombine callbacks for by calling setTargetDAGCombine() , /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine() ,
/// which sets a bit in this array. /// which sets a bit in this array.
unsigned char unsigned char
TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT]; TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
/// PromoteToType - For operations that must be promoted to a specific ty pe, /// PromoteToType - For operations that must be promoted to a specific ty pe,
/// this holds the destination type. This map should be sparse, so don't hold /// this holds the destination type. This map should be sparse, so don't hold
skipping to change at line 2028 skipping to change at line 2164
unsigned maxStoresPerMemmove; unsigned maxStoresPerMemmove;
/// Maximum number of store instructions that may be substituted for a ca ll /// Maximum number of store instructions that may be substituted for a ca ll
/// to memmove, used for functions with OpSize attribute. /// to memmove, used for functions with OpSize attribute.
unsigned maxStoresPerMemmoveOptSize; unsigned maxStoresPerMemmoveOptSize;
/// This field specifies whether the target can benefit from code placeme nt /// This field specifies whether the target can benefit from code placeme nt
/// optimization. /// optimization.
bool benefitFromCodePlacementOpt; bool benefitFromCodePlacementOpt;
/// predictableSelectIsExpensive - Tells the code generator that select i
s
/// more expensive than a branch if the branch is usually predicted right
.
bool predictableSelectIsExpensive;
private: private:
/// isLegalRC - Return true if the value types that can be represented by the /// isLegalRC - Return true if the value types that can be represented by the
/// specified register class are all legal. /// specified register class are all legal.
bool isLegalRC(const TargetRegisterClass *RC) const; bool isLegalRC(const TargetRegisterClass *RC) const;
/// hasLegalSuperRegRegClasses - Return true if the specified register cl
ass
/// has one or more super-reg register classes that are legal.
bool hasLegalSuperRegRegClasses(const TargetRegisterClass *RC) const;
}; };
/// GetReturnInfo - Given an LLVM IR type and return type attributes, /// GetReturnInfo - Given an LLVM IR type and return type attributes,
/// compute the return value EVTs and flags, and optionally also /// compute the return value EVTs and flags, and optionally also
/// the offsets, if the return value is being lowered to memory. /// the offsets, if the return value is being lowered to memory.
void GetReturnInfo(Type* ReturnType, Attributes attr, void GetReturnInfo(Type* ReturnType, Attributes attr,
SmallVectorImpl<ISD::OutputArg> &Outs, SmallVectorImpl<ISD::OutputArg> &Outs,
const TargetLowering &TLI, const TargetLowering &TLI);
SmallVectorImpl<uint64_t> *Offsets = 0);
} // end llvm namespace } // end llvm namespace
#endif #endif
 End of changes. 42 change blocks. 
78 lines changed or deleted 240 lines changed or added


 TargetLoweringObjectFile.h   TargetLoweringObjectFile.h 
skipping to change at line 37 skipping to change at line 37
class MCExpr; class MCExpr;
class MCSection; class MCSection;
class MCSymbol; class MCSymbol;
class MCStreamer; class MCStreamer;
class GlobalValue; class GlobalValue;
class TargetMachine; class TargetMachine;
class TargetLoweringObjectFile : public MCObjectFileInfo { class TargetLoweringObjectFile : public MCObjectFileInfo {
MCContext *Ctx; MCContext *Ctx;
TargetLoweringObjectFile(const TargetLoweringObjectFile&); // DO NOT IMPL TargetLoweringObjectFile(
EMENT const TargetLoweringObjectFile&) LLVM_DELETED_FUNCTION;
void operator=(const TargetLoweringObjectFile&); // DO NOT IMPL void operator=(const TargetLoweringObjectFile&) LLVM_DELETED_FUNCTION;
EMENT
public: public:
MCContext &getContext() const { return *Ctx; } MCContext &getContext() const { return *Ctx; }
TargetLoweringObjectFile() : MCObjectFileInfo(), Ctx(0) {} TargetLoweringObjectFile() : MCObjectFileInfo(), Ctx(0) {}
virtual ~TargetLoweringObjectFile(); virtual ~TargetLoweringObjectFile();
/// Initialize - this method must be called before any actual lowering is /// Initialize - this method must be called before any actual lowering is
/// done. This specifies the current context for codegen, and gives the /// done. This specifies the current context for codegen, and gives the
 End of changes. 1 change blocks. 
4 lines changed or deleted 3 lines changed or added


 TargetLoweringObjectFileImpl.h   TargetLoweringObjectFileImpl.h 
skipping to change at line 35 skipping to change at line 35
class MCAsmInfo; class MCAsmInfo;
class MCExpr; class MCExpr;
class MCSection; class MCSection;
class MCSectionMachO; class MCSectionMachO;
class MCSymbol; class MCSymbol;
class MCContext; class MCContext;
class GlobalValue; class GlobalValue;
class TargetMachine; class TargetMachine;
class TargetLoweringObjectFileELF : public TargetLoweringObjectFile { class TargetLoweringObjectFileELF : public TargetLoweringObjectFile {
bool UseInitArray;
public: public:
virtual ~TargetLoweringObjectFileELF() {} virtual ~TargetLoweringObjectFileELF() {}
virtual void emitPersonalityValue(MCStreamer &Streamer, virtual void emitPersonalityValue(MCStreamer &Streamer,
const TargetMachine &TM, const TargetMachine &TM,
const MCSymbol *Sym) const; const MCSymbol *Sym) const;
/// getSectionForConstant - Given a constant with the SectionKind, return a /// getSectionForConstant - Given a constant with the SectionKind, return a
/// section that it should be placed in. /// section that it should be placed in.
virtual const MCSection *getSectionForConstant(SectionKind Kind) const; virtual const MCSection *getSectionForConstant(SectionKind Kind) const;
skipping to change at line 67 skipping to change at line 69
virtual const MCExpr * virtual const MCExpr *
getExprForDwarfGlobalReference(const GlobalValue *GV, Mangler *Mang, getExprForDwarfGlobalReference(const GlobalValue *GV, Mangler *Mang,
MachineModuleInfo *MMI, unsigned Encoding, MachineModuleInfo *MMI, unsigned Encoding,
MCStreamer &Streamer) const; MCStreamer &Streamer) const;
// getCFIPersonalitySymbol - The symbol that gets passed to .cfi_personal ity. // getCFIPersonalitySymbol - The symbol that gets passed to .cfi_personal ity.
virtual MCSymbol * virtual MCSymbol *
getCFIPersonalitySymbol(const GlobalValue *GV, Mangler *Mang, getCFIPersonalitySymbol(const GlobalValue *GV, Mangler *Mang,
MachineModuleInfo *MMI) const; MachineModuleInfo *MMI) const;
void InitializeELF(bool UseInitArray_);
virtual const MCSection * virtual const MCSection *
getStaticCtorSection(unsigned Priority = 65535) const; getStaticCtorSection(unsigned Priority = 65535) const;
virtual const MCSection * virtual const MCSection *
getStaticDtorSection(unsigned Priority = 65535) const; getStaticDtorSection(unsigned Priority = 65535) const;
}; };
class TargetLoweringObjectFileMachO : public TargetLoweringObjectFile { class TargetLoweringObjectFileMachO : public TargetLoweringObjectFile {
public: public:
virtual ~TargetLoweringObjectFileMachO() {} virtual ~TargetLoweringObjectFileMachO() {}
 End of changes. 2 change blocks. 
0 lines changed or deleted 3 lines changed or added


 TargetMachine.h   TargetMachine.h 
skipping to change at line 107 skipping to change at line 107
/** Returns the cpu used creating this target machine. See /** Returns the cpu used creating this target machine. See
llvm::TargetMachine::getCPU. The result needs to be disposed with llvm::TargetMachine::getCPU. The result needs to be disposed with
LLVMDisposeMessage. */ LLVMDisposeMessage. */
char *LLVMGetTargetMachineCPU(LLVMTargetMachineRef T); char *LLVMGetTargetMachineCPU(LLVMTargetMachineRef T);
/** Returns the feature string used creating this target machine. See /** Returns the feature string used creating this target machine. See
llvm::TargetMachine::getFeatureString. The result needs to be disposed wi th llvm::TargetMachine::getFeatureString. The result needs to be disposed wi th
LLVMDisposeMessage. */ LLVMDisposeMessage. */
char *LLVMGetTargetMachineFeatureString(LLVMTargetMachineRef T); char *LLVMGetTargetMachineFeatureString(LLVMTargetMachineRef T);
/** Returns the llvm::TargetData used for this llvm:TargetMachine. */ /** Returns the llvm::DataLayout used for this llvm:TargetMachine. */
LLVMTargetDataRef LLVMGetTargetMachineData(LLVMTargetMachineRef T); LLVMTargetDataRef LLVMGetTargetMachineData(LLVMTargetMachineRef T);
/** Emits an asm or object file for the given module to the filename. This /** Emits an asm or object file for the given module to the filename. This
wraps several c++ only classes (among them a file stream). Returns any wraps several c++ only classes (among them a file stream). Returns any
error in ErrorMessage. Use LLVMDisposeMessage to dispose the message. */ error in ErrorMessage. Use LLVMDisposeMessage to dispose the message. */
LLVMBool LLVMTargetMachineEmitToFile(LLVMTargetMachineRef T, LLVMModuleRef M, LLVMBool LLVMTargetMachineEmitToFile(LLVMTargetMachineRef T, LLVMModuleRef M,
char *Filename, LLVMCodeGenFileType codegen, char **ErrorMessage); char *Filename, LLVMCodeGenFileType codegen, char **ErrorMessage);
#ifdef __cplusplus #ifdef __cplusplus
} }
 End of changes. 1 change blocks. 
1 lines changed or deleted 1 lines changed or added


 TargetOpcodes.h   TargetOpcodes.h 
skipping to change at line 90 skipping to change at line 90
/// v1027:3, v1025 with v1027:4, etc. /// v1027:3, v1025 with v1027:4, etc.
REG_SEQUENCE = 12, REG_SEQUENCE = 12,
/// COPY - Target-independent register copy. This instruction can also be /// COPY - Target-independent register copy. This instruction can also be
/// used to copy between subregisters of virtual registers. /// used to copy between subregisters of virtual registers.
COPY = 13, COPY = 13,
/// BUNDLE - This instruction represents an instruction bundle. Instruc tions /// BUNDLE - This instruction represents an instruction bundle. Instruc tions
/// which immediately follow a BUNDLE instruction which are marked with /// which immediately follow a BUNDLE instruction which are marked with
/// 'InsideBundle' flag are inside the bundle. /// 'InsideBundle' flag are inside the bundle.
BUNDLE BUNDLE = 14,
/// Lifetime markers.
LIFETIME_START = 15,
LIFETIME_END = 16
}; };
} // end namespace TargetOpcode } // end namespace TargetOpcode
} // end namespace llvm } // end namespace llvm
#endif #endif
 End of changes. 1 change blocks. 
1 lines changed or deleted 5 lines changed or added


 TargetOptions.h   TargetOptions.h 
skipping to change at line 33 skipping to change at line 33
// Possible float ABI settings. Used with FloatABIType in TargetOptions.h . // Possible float ABI settings. Used with FloatABIType in TargetOptions.h .
namespace FloatABI { namespace FloatABI {
enum ABIType { enum ABIType {
Default, // Target-specific (either soft or hard depending on triple, etc). Default, // Target-specific (either soft or hard depending on triple, etc).
Soft, // Soft float. Soft, // Soft float.
Hard // Hard float. Hard // Hard float.
}; };
} }
namespace FPOpFusion {
enum FPOpFusionMode {
Fast, // Enable fusion of FP ops wherever it's profitable.
Standard, // Only allow fusion of 'blessed' ops (currently just fmula
dd).
Strict // Never fuse FP-ops.
};
}
class TargetOptions { class TargetOptions {
public: public:
TargetOptions() TargetOptions()
: PrintMachineCode(false), NoFramePointerElim(false), : PrintMachineCode(false), NoFramePointerElim(false),
NoFramePointerElimNonLeaf(false), LessPreciseFPMADOption(false), NoFramePointerElimNonLeaf(false), LessPreciseFPMADOption(false),
NoExcessFPPrecision(false), UnsafeFPMath(false), NoInfsFPMath(fal se), UnsafeFPMath(false), NoInfsFPMath(false),
NoNaNsFPMath(false), HonorSignDependentRoundingFPMathOption(false ), NoNaNsFPMath(false), HonorSignDependentRoundingFPMathOption(false ),
UseSoftFloat(false), NoZerosInBSS(false), JITExceptionHandling(fa lse), UseSoftFloat(false), NoZerosInBSS(false), JITExceptionHandling(fa lse),
JITEmitDebugInfo(false), JITEmitDebugInfoToDisk(false), JITEmitDebugInfo(false), JITEmitDebugInfoToDisk(false),
GuaranteedTailCallOpt(false), DisableTailCalls(false), GuaranteedTailCallOpt(false), DisableTailCalls(false),
StackAlignmentOverride(0), RealignStack(true), StackAlignmentOverride(0), RealignStack(true), EnableFastISel(fal
DisableJumpTables(false), EnableFastISel(false), se),
PositionIndependentExecutable(false), EnableSegmentedStacks(false ), PositionIndependentExecutable(false), EnableSegmentedStacks(false ),
TrapFuncName(""), FloatABIType(FloatABI::Default) UseInitArray(false), TrapFuncName(""), FloatABIType(FloatABI::Def
ault),
AllowFPOpFusion(FPOpFusion::Standard)
{} {}
/// PrintMachineCode - This flag is enabled when the -print-machineinst rs /// PrintMachineCode - This flag is enabled when the -print-machineinst rs
/// option is specified on the command line, and should enable debuggin g /// option is specified on the command line, and should enable debuggin g
/// output from the code generator. /// output from the code generator.
unsigned PrintMachineCode : 1; unsigned PrintMachineCode : 1;
/// NoFramePointerElim - This flag is enabled when the -disable-fp-elim is /// NoFramePointerElim - This flag is enabled when the -disable-fp-elim is
/// specified on the command line. If the target supports the frame po inter /// specified on the command line. If the target supports the frame po inter
/// elimination optimization, this option should disable it. /// elimination optimization, this option should disable it.
skipping to change at line 77 skipping to change at line 85
bool DisableFramePointerElim(const MachineFunction &MF) const; bool DisableFramePointerElim(const MachineFunction &MF) const;
/// LessPreciseFPMAD - This flag is enabled when the /// LessPreciseFPMAD - This flag is enabled when the
/// -enable-fp-mad is specified on the command line. When this flag is off /// -enable-fp-mad is specified on the command line. When this flag is off
/// (the default), the code generator is not allowed to generate mad /// (the default), the code generator is not allowed to generate mad
/// (multiply add) if the result is "less precise" than doing those /// (multiply add) if the result is "less precise" than doing those
/// operations individually. /// operations individually.
unsigned LessPreciseFPMADOption : 1; unsigned LessPreciseFPMADOption : 1;
bool LessPreciseFPMAD() const; bool LessPreciseFPMAD() const;
/// NoExcessFPPrecision - This flag is enabled when the
/// -disable-excess-fp-precision flag is specified on the command line.
/// When this flag is off (the default), the code generator is allowed
to
/// produce results that are "more precise" than IEEE allows. This inc
ludes
/// use of FMA-like operations and use of the X86 FP registers without
/// rounding all over the place.
unsigned NoExcessFPPrecision : 1;
/// UnsafeFPMath - This flag is enabled when the /// UnsafeFPMath - This flag is enabled when the
/// -enable-unsafe-fp-math flag is specified on the command line. When /// -enable-unsafe-fp-math flag is specified on the command line. When
/// this flag is off (the default), the code generator is not allowed t o /// this flag is off (the default), the code generator is not allowed t o
/// produce results that are "less precise" than IEEE allows. This inc ludes /// produce results that are "less precise" than IEEE allows. This inc ludes
/// use of X86 instructions like FSIN and FCOS instead of libcalls. /// use of X86 instructions like FSIN and FCOS instead of libcalls.
/// UnsafeFPMath implies LessPreciseFPMAD. /// UnsafeFPMath implies LessPreciseFPMAD.
unsigned UnsafeFPMath : 1; unsigned UnsafeFPMath : 1;
/// NoInfsFPMath - This flag is enabled when the /// NoInfsFPMath - This flag is enabled when the
/// -enable-no-infs-fp-math flag is specified on the command line. When /// -enable-no-infs-fp-math flag is specified on the command line. When
skipping to change at line 158 skipping to change at line 158
/// Disabling them may be useful to maintain a correct call stack. /// Disabling them may be useful to maintain a correct call stack.
unsigned DisableTailCalls : 1; unsigned DisableTailCalls : 1;
/// StackAlignmentOverride - Override default stack alignment for targe t. /// StackAlignmentOverride - Override default stack alignment for targe t.
unsigned StackAlignmentOverride; unsigned StackAlignmentOverride;
/// RealignStack - This flag indicates whether the stack should be /// RealignStack - This flag indicates whether the stack should be
/// automatically realigned, if needed. /// automatically realigned, if needed.
unsigned RealignStack : 1; unsigned RealignStack : 1;
/// DisableJumpTables - This flag indicates jump tables should not be /// SSPBufferSize - The minimum size of buffers that will receive stack
/// generated. /// smashing protection when -fstack-protection is used.
unsigned DisableJumpTables : 1; unsigned SSPBufferSize;
/// EnableFastISel - This flag enables fast-path instruction selection /// EnableFastISel - This flag enables fast-path instruction selection
/// which trades away generated code quality in favor of reducing /// which trades away generated code quality in favor of reducing
/// compile time. /// compile time.
unsigned EnableFastISel : 1; unsigned EnableFastISel : 1;
/// PositionIndependentExecutable - This flag indicates whether the cod e /// PositionIndependentExecutable - This flag indicates whether the cod e
/// will eventually be linked into a single executable, despite the PIC /// will eventually be linked into a single executable, despite the PIC
/// relocation model being in use. It's value is undefined (and irrelev ant) /// relocation model being in use. It's value is undefined (and irrelev ant)
/// if the relocation model is anything other than PIC. /// if the relocation model is anything other than PIC.
unsigned PositionIndependentExecutable : 1; unsigned PositionIndependentExecutable : 1;
unsigned EnableSegmentedStacks : 1; unsigned EnableSegmentedStacks : 1;
/// UseInitArray - Use .init_array instead of .ctors for static
/// constructors.
unsigned UseInitArray : 1;
/// getTrapFunctionName - If this returns a non-empty string, this mean s /// getTrapFunctionName - If this returns a non-empty string, this mean s
/// isel should lower Intrinsic::trap to a call to the specified functi on /// isel should lower Intrinsic::trap to a call to the specified functi on
/// name instead of an ISD::TRAP node. /// name instead of an ISD::TRAP node.
std::string TrapFuncName; std::string TrapFuncName;
StringRef getTrapFunctionName() const; StringRef getTrapFunctionName() const;
/// FloatABIType - This setting is set by -float-abi=xxx option is spec fied /// FloatABIType - This setting is set by -float-abi=xxx option is spec fied
/// on the command line. This setting may either be Default, Soft, or H ard. /// on the command line. This setting may either be Default, Soft, or H ard.
/// Default selects the target's default behavior. Soft selects the ABI for /// Default selects the target's default behavior. Soft selects the ABI for
/// UseSoftFloat, but does not indicate that FP hardware may not be use d. /// UseSoftFloat, but does not indicate that FP hardware may not be use d.
/// Such a combination is unfortunately popular (e.g. arm-apple-darwin) . /// Such a combination is unfortunately popular (e.g. arm-apple-darwin) .
/// Hard presumes that the normal FP ABI is used. /// Hard presumes that the normal FP ABI is used.
FloatABI::ABIType FloatABIType; FloatABI::ABIType FloatABIType;
/// AllowFPOpFusion - This flag is set by the -fuse-fp-ops=xxx option.
/// This controls the creation of fused FP ops that store intermediate
/// results in higher precision than IEEE allows (E.g. FMAs).
///
/// Fast mode - allows formation of fused FP ops whenever they're
/// profitable.
/// Standard mode - allow fusion only for 'blessed' FP ops. At present
the
/// only blessed op is the fmuladd intrinsic. In the future more blesse
d ops
/// may be added.
/// Strict mode - allow fusion only if/when it can be proven that the e
xcess
/// precision won't effect the result.
///
/// Note: This option only controls formation of fused ops by the optim
izers.
/// Fused operations that are explicitly specified (e.g. FMA via the
/// llvm.fma.* intrinsic) will always be honored, regardless of the val
ue of
/// this option.
FPOpFusion::FPOpFusionMode AllowFPOpFusion;
}; };
} // End llvm namespace } // End llvm namespace
#endif #endif
 End of changes. 8 change blocks. 
17 lines changed or deleted 46 lines changed or added


 TargetRegisterInfo.h   TargetRegisterInfo.h 
skipping to change at line 45 skipping to change at line 45
class TargetRegisterClass { class TargetRegisterClass {
public: public:
typedef const uint16_t* iterator; typedef const uint16_t* iterator;
typedef const uint16_t* const_iterator; typedef const uint16_t* const_iterator;
typedef const MVT::SimpleValueType* vt_iterator; typedef const MVT::SimpleValueType* vt_iterator;
typedef const TargetRegisterClass* const * sc_iterator; typedef const TargetRegisterClass* const * sc_iterator;
// Instance variables filled by tablegen, do not use! // Instance variables filled by tablegen, do not use!
const MCRegisterClass *MC; const MCRegisterClass *MC;
const vt_iterator VTs; const vt_iterator VTs;
const unsigned *SubClassMask; const uint32_t *SubClassMask;
const uint16_t *SuperRegIndices;
const sc_iterator SuperClasses; const sc_iterator SuperClasses;
const sc_iterator SuperRegClasses;
ArrayRef<uint16_t> (*OrderFunc)(const MachineFunction&); ArrayRef<uint16_t> (*OrderFunc)(const MachineFunction&);
/// getID() - Return the register class ID number. /// getID() - Return the register class ID number.
/// ///
unsigned getID() const { return MC->getID(); } unsigned getID() const { return MC->getID(); }
/// getName() - Return the register class name for debugging. /// getName() - Return the register class name for debugging.
/// ///
const char *getName() const { return MC->getName(); } const char *getName() const { return MC->getName(); }
skipping to change at line 122 skipping to change at line 122
vt_iterator vt_begin() const { vt_iterator vt_begin() const {
return VTs; return VTs;
} }
vt_iterator vt_end() const { vt_iterator vt_end() const {
vt_iterator I = VTs; vt_iterator I = VTs;
while (*I != MVT::Other) ++I; while (*I != MVT::Other) ++I;
return I; return I;
} }
/// superregclasses_begin / superregclasses_end - Loop over all of
/// the superreg register classes of this register class.
sc_iterator superregclasses_begin() const {
return SuperRegClasses;
}
sc_iterator superregclasses_end() const {
sc_iterator I = SuperRegClasses;
while (*I != NULL) ++I;
return I;
}
/// hasSubClass - return true if the specified TargetRegisterClass /// hasSubClass - return true if the specified TargetRegisterClass
/// is a proper sub-class of this TargetRegisterClass. /// is a proper sub-class of this TargetRegisterClass.
bool hasSubClass(const TargetRegisterClass *RC) const { bool hasSubClass(const TargetRegisterClass *RC) const {
return RC != this && hasSubClassEq(RC); return RC != this && hasSubClassEq(RC);
} }
/// hasSubClassEq - Returns true if RC is a sub-class of or equal to this /// hasSubClassEq - Returns true if RC is a sub-class of or equal to this
/// class. /// class.
bool hasSubClassEq(const TargetRegisterClass *RC) const { bool hasSubClassEq(const TargetRegisterClass *RC) const {
unsigned ID = RC->getID(); unsigned ID = RC->getID();
skipping to change at line 166 skipping to change at line 154
return RC->hasSubClassEq(this); return RC->hasSubClassEq(this);
} }
/// getSubClassMask - Returns a bit vector of subclasses, including this one. /// getSubClassMask - Returns a bit vector of subclasses, including this one.
/// The vector is indexed by class IDs, see hasSubClassEq() above for how to /// The vector is indexed by class IDs, see hasSubClassEq() above for how to
/// use it. /// use it.
const uint32_t *getSubClassMask() const { const uint32_t *getSubClassMask() const {
return SubClassMask; return SubClassMask;
} }
/// getSuperRegIndices - Returns a 0-terminated list of sub-register indi
ces
/// that project some super-register class into this register class. The
list
/// has an entry for each Idx such that:
///
/// There exists SuperRC where:
/// For all Reg in SuperRC:
/// this->contains(Reg:Idx)
///
const uint16_t *getSuperRegIndices() const {
return SuperRegIndices;
}
/// getSuperClasses - Returns a NULL terminated list of super-classes. T he /// getSuperClasses - Returns a NULL terminated list of super-classes. T he
/// classes are ordered by ID which is also a topological ordering from l arge /// classes are ordered by ID which is also a topological ordering from l arge
/// to small classes. The list does NOT include the current class. /// to small classes. The list does NOT include the current class.
sc_iterator getSuperClasses() const { sc_iterator getSuperClasses() const {
return SuperClasses; return SuperClasses;
} }
/// isASubClass - return true if this TargetRegisterClass is a subset /// isASubClass - return true if this TargetRegisterClass is a subset
/// class of at least one other TargetRegisterClass. /// class of at least one other TargetRegisterClass.
bool isASubClass() const { bool isASubClass() const {
skipping to change at line 224 skipping to change at line 224
/// registers that the target has. As such, we simply have to track a poin ter /// registers that the target has. As such, we simply have to track a poin ter
/// to this array so that we can turn register number into a register /// to this array so that we can turn register number into a register
/// descriptor. /// descriptor.
/// ///
class TargetRegisterInfo : public MCRegisterInfo { class TargetRegisterInfo : public MCRegisterInfo {
public: public:
typedef const TargetRegisterClass * const * regclass_iterator; typedef const TargetRegisterClass * const * regclass_iterator;
private: private:
const TargetRegisterInfoDesc *InfoDesc; // Extra desc array for codeg en const TargetRegisterInfoDesc *InfoDesc; // Extra desc array for codeg en
const char *const *SubRegIndexNames; // Names of subreg indexes. const char *const *SubRegIndexNames; // Names of subreg indexes.
// Pointer to array of lane masks, one per sub-reg index.
const unsigned *SubRegIndexLaneMasks;
regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
protected: protected:
TargetRegisterInfo(const TargetRegisterInfoDesc *ID, TargetRegisterInfo(const TargetRegisterInfoDesc *ID,
regclass_iterator RegClassBegin, regclass_iterator RegClassBegin,
regclass_iterator RegClassEnd, regclass_iterator RegClassEnd,
const char *const *subregindexnames); const char *const *SRINames,
const unsigned *SRILaneMasks);
virtual ~TargetRegisterInfo(); virtual ~TargetRegisterInfo();
public: public:
// Register numbers can represent physical registers, virtual registers, and // Register numbers can represent physical registers, virtual registers, and
// sometimes stack slots. The unsigned values are divided into these rang es: // sometimes stack slots. The unsigned values are divided into these rang es:
// //
// 0 Not a register, can be used as a sentinel. // 0 Not a register, can be used as a sentinel.
// [1;2^30) Physical registers assigned by TableGen. // [1;2^30) Physical registers assigned by TableGen.
// [2^30;2^31) Stack slots. (Rarely used.) // [2^30;2^31) Stack slots. (Rarely used.)
// [2^31;2^32) Virtual registers assigned by MachineRegisterInfo. // [2^31;2^32) Virtual registers assigned by MachineRegisterInfo.
skipping to change at line 304 skipping to change at line 308
static unsigned index2VirtReg(unsigned Index) { static unsigned index2VirtReg(unsigned Index) {
return Index | (1u << 31); return Index | (1u << 31);
} }
/// getMinimalPhysRegClass - Returns the Register Class of a physical /// getMinimalPhysRegClass - Returns the Register Class of a physical
/// register of the given type, picking the most sub register class of /// register of the given type, picking the most sub register class of
/// the right type that contains this physreg. /// the right type that contains this physreg.
const TargetRegisterClass * const TargetRegisterClass *
getMinimalPhysRegClass(unsigned Reg, EVT VT = MVT::Other) const; getMinimalPhysRegClass(unsigned Reg, EVT VT = MVT::Other) const;
/// getAllocatableClass - Return the maximal subclass of the given regist
er
/// class that is alloctable, or NULL.
const TargetRegisterClass *
getAllocatableClass(const TargetRegisterClass *RC) const;
/// getAllocatableSet - Returns a bitset indexed by register number /// getAllocatableSet - Returns a bitset indexed by register number
/// indicating if a register is allocatable or not. If a register class i s /// indicating if a register is allocatable or not. If a register class i s
/// specified, returns the subset for the class. /// specified, returns the subset for the class.
BitVector getAllocatableSet(const MachineFunction &MF, BitVector getAllocatableSet(const MachineFunction &MF,
const TargetRegisterClass *RC = NULL) const; const TargetRegisterClass *RC = NULL) const;
/// getCostPerUse - Return the additional cost of using this register ins tead /// getCostPerUse - Return the additional cost of using this register ins tead
/// of other registers in its class. /// of other registers in its class.
unsigned getCostPerUse(unsigned RegNo) const { unsigned getCostPerUse(unsigned RegNo) const {
return InfoDesc[RegNo].CostPerUse; return InfoDesc[RegNo].CostPerUse;
skipping to change at line 325 skipping to change at line 334
/// isInAllocatableClass - Return true if the register is in the allocati on /// isInAllocatableClass - Return true if the register is in the allocati on
/// of any register class. /// of any register class.
bool isInAllocatableClass(unsigned RegNo) const { bool isInAllocatableClass(unsigned RegNo) const {
return InfoDesc[RegNo].inAllocatableClass; return InfoDesc[RegNo].inAllocatableClass;
} }
/// getSubRegIndexName - Return the human-readable symbolic target-specif ic /// getSubRegIndexName - Return the human-readable symbolic target-specif ic
/// name for the specified SubRegIndex. /// name for the specified SubRegIndex.
const char *getSubRegIndexName(unsigned SubIdx) const { const char *getSubRegIndexName(unsigned SubIdx) const {
assert(SubIdx && "This is not a subregister index"); assert(SubIdx && SubIdx < getNumSubRegIndices() &&
"This is not a subregister index");
return SubRegIndexNames[SubIdx-1]; return SubRegIndexNames[SubIdx-1];
} }
/// getSubRegIndexLaneMask - Return a bitmask representing the parts of a
/// register that are covered by SubIdx.
///
/// Lane masks for sub-register indices are similar to register units for
/// physical registers. The individual bits in a lane mask can't be assig
ned
/// any specific meaning. They can be used to check if two sub-register
/// indices overlap.
///
/// If the target has a register such that:
///
/// getSubReg(Reg, A) overlaps getSubReg(Reg, B)
///
/// then:
///
/// getSubRegIndexLaneMask(A) & getSubRegIndexLaneMask(B) != 0
///
/// The converse is not necessarily true. If two lane masks have a common
/// bit, the corresponding sub-registers may not overlap, but it can be
/// assumed that they usually will.
unsigned getSubRegIndexLaneMask(unsigned SubIdx) const {
// SubIdx == 0 is allowed, it has the lane mask ~0u.
assert(SubIdx < getNumSubRegIndices() && "This is not a subregister ind
ex");
return SubRegIndexLaneMasks[SubIdx];
}
/// regsOverlap - Returns true if the two registers are equal or alias ea ch /// regsOverlap - Returns true if the two registers are equal or alias ea ch
/// other. The registers may be virtual register. /// other. The registers may be virtual register.
bool regsOverlap(unsigned regA, unsigned regB) const { bool regsOverlap(unsigned regA, unsigned regB) const {
if (regA == regB) return true; if (regA == regB) return true;
if (isVirtualRegister(regA) || isVirtualRegister(regB)) if (isVirtualRegister(regA) || isVirtualRegister(regB))
return false; return false;
for (const uint16_t *regList = getOverlaps(regA)+1; *regList; ++regList
) { // Regunits are numerically ordered. Find a common unit.
if (*regList == regB) return true; MCRegUnitIterator RUA(regA, this);
} MCRegUnitIterator RUB(regB, this);
do {
if (*RUA == *RUB) return true;
if (*RUA < *RUB) ++RUA;
else ++RUB;
} while (RUA.isValid() && RUB.isValid());
return false;
}
/// hasRegUnit - Returns true if Reg contains RegUnit.
bool hasRegUnit(unsigned Reg, unsigned RegUnit) const {
for (MCRegUnitIterator Units(Reg, this); Units.isValid(); ++Units)
if (*Units == RegUnit)
return true;
return false; return false;
} }
/// isSubRegister - Returns true if regB is a sub-register of regA. /// isSubRegister - Returns true if regB is a sub-register of regA.
/// ///
bool isSubRegister(unsigned regA, unsigned regB) const { bool isSubRegister(unsigned regA, unsigned regB) const {
return isSuperRegister(regB, regA); return isSuperRegister(regB, regA);
} }
/// isSuperRegister - Returns true if regB is a super-register of regA. /// isSuperRegister - Returns true if regB is a super-register of regA.
/// ///
bool isSuperRegister(unsigned regA, unsigned regB) const { bool isSuperRegister(unsigned RegA, unsigned RegB) const {
for (const uint16_t *regList = getSuperRegisters(regA); *regList;++regL for (MCSuperRegIterator I(RegA, this); I.isValid(); ++I)
ist){ if (*I == RegB)
if (*regList == regB) return true; return true;
}
return false; return false;
} }
/// getCalleeSavedRegs - Return a null-terminated list of all of the /// getCalleeSavedRegs - Return a null-terminated list of all of the
/// callee saved registers on this target. The register should be in the /// callee saved registers on this target. The register should be in the
/// order of desired callee-save stack frame offset. The first register i s /// order of desired callee-save stack frame offset. The first register i s
/// closest to the incoming stack pointer if stack grows down, and vice v ersa. /// closest to the incoming stack pointer if stack grows down, and vice v ersa.
/// ///
virtual const uint16_t* getCalleeSavedRegs(const MachineFunction *MF = 0) virtual const uint16_t* getCalleeSavedRegs(const MachineFunction *MF = 0)
const = 0; const = 0;
skipping to change at line 400 skipping to change at line 449
/// used by register scavenger to determine what registers are free. /// used by register scavenger to determine what registers are free.
virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0; virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
/// getMatchingSuperReg - Return a super-register of the specified regist er /// getMatchingSuperReg - Return a super-register of the specified regist er
/// Reg so its sub-register of index SubIdx is Reg. /// Reg so its sub-register of index SubIdx is Reg.
unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
const TargetRegisterClass *RC) const { const TargetRegisterClass *RC) const {
return MCRegisterInfo::getMatchingSuperReg(Reg, SubIdx, RC->MC); return MCRegisterInfo::getMatchingSuperReg(Reg, SubIdx, RC->MC);
} }
/// canCombineSubRegIndices - Given a register class and a list of
/// subregister indices, return true if it's possible to combine the
/// subregister indices into one that corresponds to a larger
/// subregister. Return the new subregister index by reference. Note the
/// new index may be zero if the given subregisters can be combined to
/// form the whole register.
virtual bool canCombineSubRegIndices(const TargetRegisterClass *RC,
SmallVectorImpl<unsigned> &SubIndice
s,
unsigned &NewSubIdx) const {
return 0;
}
/// getMatchingSuperRegClass - Return a subclass of the specified registe r /// getMatchingSuperRegClass - Return a subclass of the specified registe r
/// class A so that each register in it has a sub-register of the /// class A so that each register in it has a sub-register of the
/// specified sub-register index which is in the specified register class B. /// specified sub-register index which is in the specified register class B.
/// ///
/// TableGen will synthesize missing A sub-classes. /// TableGen will synthesize missing A sub-classes.
virtual const TargetRegisterClass * virtual const TargetRegisterClass *
getMatchingSuperRegClass(const TargetRegisterClass *A, getMatchingSuperRegClass(const TargetRegisterClass *A,
const TargetRegisterClass *B, unsigned Idx) cons t =0; const TargetRegisterClass *B, unsigned Idx) cons t;
/// getSubClassWithSubReg - Returns the largest legal sub-class of RC tha t /// getSubClassWithSubReg - Returns the largest legal sub-class of RC tha t
/// supports the sub-register index Idx. /// supports the sub-register index Idx.
/// If no such sub-class exists, return NULL. /// If no such sub-class exists, return NULL.
/// If all registers in RC already have an Idx sub-register, return RC. /// If all registers in RC already have an Idx sub-register, return RC.
/// ///
/// TableGen generates a version of this function that is good enough in most /// TableGen generates a version of this function that is good enough in most
/// cases. Targets can override if they have constraints that TableGen /// cases. Targets can override if they have constraints that TableGen
/// doesn't understand. For example, the x86 sub_8bit sub-register index is /// doesn't understand. For example, the x86 sub_8bit sub-register index is
/// supported by the full GR32 register class in 64-bit mode, but only by the /// supported by the full GR32 register class in 64-bit mode, but only by the
/// GR32_ABCD regiister class in 32-bit mode. /// GR32_ABCD regiister class in 32-bit mode.
/// ///
/// TableGen will synthesize missing RC sub-classes. /// TableGen will synthesize missing RC sub-classes.
virtual const TargetRegisterClass * virtual const TargetRegisterClass *
getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const
=0; {
assert(Idx == 0 && "Target has no sub-registers");
return RC;
}
/// composeSubRegIndices - Return the subregister index you get from comp osing /// composeSubRegIndices - Return the subregister index you get from comp osing
/// two subregister indices. /// two subregister indices.
/// ///
/// The special null sub-register index composes as the identity.
///
/// If R:a:b is the same register as R:c, then composeSubRegIndices(a, b) /// If R:a:b is the same register as R:c, then composeSubRegIndices(a, b)
/// returns c. Note that composeSubRegIndices does not tell you about ill egal /// returns c. Note that composeSubRegIndices does not tell you about ill egal
/// compositions. If R does not have a subreg a, or R:a does not have a s ubreg /// compositions. If R does not have a subreg a, or R:a does not have a s ubreg
/// b, composeSubRegIndices doesn't tell you. /// b, composeSubRegIndices doesn't tell you.
/// ///
/// The ARM register Q0 has two D subregs dsub_0:D0 and dsub_1:D1. It als o has /// The ARM register Q0 has two D subregs dsub_0:D0 and dsub_1:D1. It als o has
/// ssub_0:S0 - ssub_3:S3 subregs. /// ssub_0:S0 - ssub_3:S3 subregs.
/// If you compose subreg indices dsub_1, ssub_0 you get ssub_2. /// If you compose subreg indices dsub_1, ssub_0 you get ssub_2.
/// ///
virtual unsigned composeSubRegIndices(unsigned a, unsigned b) const { unsigned composeSubRegIndices(unsigned a, unsigned b) const {
// This default implementation is correct for most targets. if (!a) return b;
return b; if (!b) return a;
return composeSubRegIndicesImpl(a, b);
}
protected:
/// Overridden by TableGen in targets that have sub-registers.
virtual unsigned composeSubRegIndicesImpl(unsigned, unsigned) const {
llvm_unreachable("Target has no sub-registers");
} }
public:
/// getCommonSuperRegClass - Find a common super-register class if it exi
sts.
///
/// Find a register class, SuperRC and two sub-register indices, PreA and
/// PreB, such that:
///
/// 1. PreA + SubA == PreB + SubB (using composeSubRegIndices()), and
///
/// 2. For all Reg in SuperRC: Reg:PreA in RCA and Reg:PreB in RCB, and
///
/// 3. SuperRC->getSize() >= max(RCA->getSize(), RCB->getSize()).
///
/// SuperRC will be chosen such that no super-class of SuperRC satisfies
the
/// requirements, and there is no register class with a smaller spill siz
e
/// that satisfies the requirements.
///
/// SubA and SubB must not be 0. Use getMatchingSuperRegClass() instead.
///
/// Either of the PreA and PreB sub-register indices may be returned as 0
. In
/// that case, the returned register class will be a sub-class of the
/// corresponding argument register class.
///
/// The function returns NULL if no register class can be found.
///
const TargetRegisterClass*
getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA,
const TargetRegisterClass *RCB, unsigned SubB,
unsigned &PreA, unsigned &PreB) const;
//===-------------------------------------------------------------------- ===// //===-------------------------------------------------------------------- ===//
// Register Class Information // Register Class Information
// //
/// Register class iterators /// Register class iterators
/// ///
regclass_iterator regclass_begin() const { return RegClassBegin; } regclass_iterator regclass_begin() const { return RegClassBegin; }
regclass_iterator regclass_end() const { return RegClassEnd; } regclass_iterator regclass_end() const { return RegClassEnd; }
unsigned getNumRegClasses() const { unsigned getNumRegClasses() const {
skipping to change at line 482 skipping to change at line 560
/// getCommonSubClass - find the largest common subclass of A and B. Retu rn /// getCommonSubClass - find the largest common subclass of A and B. Retu rn
/// NULL if there is no common subclass. /// NULL if there is no common subclass.
const TargetRegisterClass * const TargetRegisterClass *
getCommonSubClass(const TargetRegisterClass *A, getCommonSubClass(const TargetRegisterClass *A,
const TargetRegisterClass *B) const; const TargetRegisterClass *B) const;
/// getPointerRegClass - Returns a TargetRegisterClass used for pointer /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
/// values. If a target supports multiple different pointer register cla sses, /// values. If a target supports multiple different pointer register cla sses,
/// kind specifies which one is indicated. /// kind specifies which one is indicated.
virtual const TargetRegisterClass *getPointerRegClass(unsigned Kind=0) co virtual const TargetRegisterClass *
nst { getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const {
llvm_unreachable("Target didn't implement getPointerRegClass!"); llvm_unreachable("Target didn't implement getPointerRegClass!");
} }
/// getCrossCopyRegClass - Returns a legal register class to copy a regis ter /// getCrossCopyRegClass - Returns a legal register class to copy a regis ter
/// in the specified class to or from. If it is possible to copy the regi ster /// in the specified class to or from. If it is possible to copy the regi ster
/// directly without using a cross register class copy, return the specif ied /// directly without using a cross register class copy, return the specif ied
/// RC. Returns NULL if it is not possible to copy between a two register s of /// RC. Returns NULL if it is not possible to copy between a two register s of
/// the specified class. /// the specified class.
virtual const TargetRegisterClass * virtual const TargetRegisterClass *
getCrossCopyRegClass(const TargetRegisterClass *RC) const { getCrossCopyRegClass(const TargetRegisterClass *RC) const {
skipping to change at line 518 skipping to change at line 597
/// the specific register class. The scheduler is in high register pressu re /// the specific register class. The scheduler is in high register pressu re
/// mode (for the specific register class) if it goes over the limit. /// mode (for the specific register class) if it goes over the limit.
/// ///
/// Note: this is the old register pressure model that relies on a manual ly /// Note: this is the old register pressure model that relies on a manual ly
/// specified representative register class per value type. /// specified representative register class per value type.
virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC, virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC,
MachineFunction &MF) const { MachineFunction &MF) const {
return 0; return 0;
} }
/// Get the weight in units of pressure for this register class. // Get the weight in units of pressure for this register class.
virtual const RegClassWeight &getRegClassWeight( virtual const RegClassWeight &getRegClassWeight(
const TargetRegisterClass *RC) const = 0; const TargetRegisterClass *RC) const = 0;
/// Get the number of dimensions of register pressure. /// Get the number of dimensions of register pressure.
virtual unsigned getNumRegPressureSets() const = 0; virtual unsigned getNumRegPressureSets() const = 0;
/// Get the name of this register unit pressure set.
virtual const char *getRegPressureSetName(unsigned Idx) const = 0;
/// Get the register unit pressure limit for this dimension. /// Get the register unit pressure limit for this dimension.
/// This limit must be adjusted dynamically for reserved registers. /// This limit must be adjusted dynamically for reserved registers.
virtual unsigned getRegPressureSetLimit(unsigned Idx) const = 0; virtual unsigned getRegPressureSetLimit(unsigned Idx) const = 0;
/// Get the dimensions of register pressure impacted by this register cla ss. /// Get the dimensions of register pressure impacted by this register cla ss.
/// Returns a -1 terminated array of pressure set IDs. /// Returns a -1 terminated array of pressure set IDs.
virtual const int *getRegClassPressureSets( virtual const int *getRegClassPressureSets(
const TargetRegisterClass *RC) const = 0; const TargetRegisterClass *RC) const = 0;
/// getRawAllocationOrder - Returns the register allocation order for a /// getRawAllocationOrder - Returns the register allocation order for a
skipping to change at line 612 skipping to change at line 694
/// the stack frame of the given function for the specified register. e.g . On /// the stack frame of the given function for the specified register. e.g . On
/// x86, if the frame register is required, the first fixed stack object is /// x86, if the frame register is required, the first fixed stack object is
/// reserved as its spill slot. This tells PEI not to create a new stack frame /// reserved as its spill slot. This tells PEI not to create a new stack frame
/// object for the given register. It should be called only after /// object for the given register. It should be called only after
/// processFunctionBeforeCalleeSavedScan(). /// processFunctionBeforeCalleeSavedScan().
virtual bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg , virtual bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg ,
int &FrameIdx) const { int &FrameIdx) const {
return false; return false;
} }
/// trackLivenessAfterRegAlloc - returns true if the live-ins should be t
racked
/// after register allocation.
virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const
{
return false;
}
/// needsStackRealignment - true if storage within the function requires the /// needsStackRealignment - true if storage within the function requires the
/// stack pointer to be aligned more than the normal calling convention c alls /// stack pointer to be aligned more than the normal calling convention c alls
/// for. /// for.
virtual bool needsStackRealignment(const MachineFunction &MF) const { virtual bool needsStackRealignment(const MachineFunction &MF) const {
return false; return false;
} }
/// getFrameIndexInstrOffset - Get the offset from the referenced frame /// getFrameIndexInstrOffset - Get the offset from the referenced frame
/// index in the instruction, if there is one. /// index in the instruction, if there is one.
virtual int64_t getFrameIndexInstrOffset(const MachineInstr *MI, virtual int64_t getFrameIndexInstrOffset(const MachineInstr *MI,
skipping to change at line 709 skipping to change at line 797
/// for values allocated in the current stack frame. /// for values allocated in the current stack frame.
virtual unsigned getFrameRegister(const MachineFunction &MF) const = 0; virtual unsigned getFrameRegister(const MachineFunction &MF) const = 0;
/// getCompactUnwindRegNum - This function maps the register to the numbe r for /// getCompactUnwindRegNum - This function maps the register to the numbe r for
/// compact unwind encoding. Return -1 if the register isn't valid. /// compact unwind encoding. Return -1 if the register isn't valid.
virtual int getCompactUnwindRegNum(unsigned, bool) const { virtual int getCompactUnwindRegNum(unsigned, bool) const {
return -1; return -1;
} }
}; };
//===----------------------------------------------------------------------
===//
// SuperRegClassIterator
//===----------------------------------------------------------------------
===//
//
// Iterate over the possible super-registers for a given register class. Th
e
// iterator will visit a list of pairs (Idx, Mask) corresponding to the
// possible classes of super-registers.
//
// Each bit mask will have at least one set bit, and each set bit in Mask
// corresponds to a SuperRC such that:
//
// For all Reg in SuperRC: Reg:Idx is in RC.
//
// The iterator can include (O, RC->getSubClassMask()) as the first entry w
hich
// also satisfies the above requirement, assuming Reg:0 == Reg.
//
class SuperRegClassIterator {
const unsigned RCMaskWords;
unsigned SubReg;
const uint16_t *Idx;
const uint32_t *Mask;
public:
/// Create a SuperRegClassIterator that visits all the super-register cla
sses
/// of RC. When IncludeSelf is set, also include the (0, sub-classes) ent
ry.
SuperRegClassIterator(const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI,
bool IncludeSelf = false)
: RCMaskWords((TRI->getNumRegClasses() + 31) / 32),
SubReg(0),
Idx(RC->getSuperRegIndices()),
Mask(RC->getSubClassMask()) {
if (!IncludeSelf)
++*this;
}
/// Returns true if this iterator is still pointing at a valid entry.
bool isValid() const { return Idx; }
/// Returns the current sub-register index.
unsigned getSubReg() const { return SubReg; }
/// Returns the bit mask if register classes that getSubReg() projects in
to
/// RC.
const uint32_t *getMask() const { return Mask; }
/// Advance iterator to the next entry.
void operator++() {
assert(isValid() && "Cannot move iterator past end.");
Mask += RCMaskWords;
SubReg = *Idx++;
if (!SubReg)
Idx = 0;
}
};
// This is useful when building IndexedMaps keyed on virtual registers // This is useful when building IndexedMaps keyed on virtual registers
struct VirtReg2IndexFunctor : public std::unary_function<unsigned, unsigned > { struct VirtReg2IndexFunctor : public std::unary_function<unsigned, unsigned > {
unsigned operator()(unsigned Reg) const { unsigned operator()(unsigned Reg) const {
return TargetRegisterInfo::virtReg2Index(Reg); return TargetRegisterInfo::virtReg2Index(Reg);
} }
}; };
/// PrintReg - Helper class for printing registers on a raw_ostream. /// PrintReg - Helper class for printing registers on a raw_ostream.
/// Prints virtual and physical registers with or without a TRI instance. /// Prints virtual and physical registers with or without a TRI instance.
/// ///
skipping to change at line 743 skipping to change at line 887
PrintReg(unsigned reg, const TargetRegisterInfo *tri = 0, unsigned subidx = 0) PrintReg(unsigned reg, const TargetRegisterInfo *tri = 0, unsigned subidx = 0)
: TRI(tri), Reg(reg), SubIdx(subidx) {} : TRI(tri), Reg(reg), SubIdx(subidx) {}
void print(raw_ostream&) const; void print(raw_ostream&) const;
}; };
static inline raw_ostream &operator<<(raw_ostream &OS, const PrintReg &PR) { static inline raw_ostream &operator<<(raw_ostream &OS, const PrintReg &PR) {
PR.print(OS); PR.print(OS);
return OS; return OS;
} }
/// PrintRegUnit - Helper class for printing register units on a raw_ostrea
m.
///
/// Register units are named after their root registers:
///
/// AL - Single root.
/// FP0~ST7 - Dual roots.
///
/// Usage: OS << PrintRegUnit(Unit, TRI) << '\n';
///
class PrintRegUnit {
const TargetRegisterInfo *TRI;
unsigned Unit;
public:
PrintRegUnit(unsigned unit, const TargetRegisterInfo *tri)
: TRI(tri), Unit(unit) {}
void print(raw_ostream&) const;
};
static inline raw_ostream &operator<<(raw_ostream &OS, const PrintRegUnit &
PR) {
PR.print(OS);
return OS;
}
} // End llvm namespace } // End llvm namespace
#endif #endif
 End of changes. 23 change blocks. 
47 lines changed or deleted 230 lines changed or added


 TargetRegistry.h   TargetRegistry.h 
skipping to change at line 96 skipping to change at line 96
typedef TargetMachine *(*TargetMachineCtorTy)(const Target &T, typedef TargetMachine *(*TargetMachineCtorTy)(const Target &T,
StringRef TT, StringRef TT,
StringRef CPU, StringRef CPU,
StringRef Features, StringRef Features,
const TargetOptions &Opti ons, const TargetOptions &Opti ons,
Reloc::Model RM, Reloc::Model RM,
CodeModel::Model CM, CodeModel::Model CM,
CodeGenOpt::Level OL); CodeGenOpt::Level OL);
typedef AsmPrinter *(*AsmPrinterCtorTy)(TargetMachine &TM, typedef AsmPrinter *(*AsmPrinterCtorTy)(TargetMachine &TM,
MCStreamer &Streamer); MCStreamer &Streamer);
typedef MCAsmBackend *(*MCAsmBackendCtorTy)(const Target &T, StringRef typedef MCAsmBackend *(*MCAsmBackendCtorTy)(const Target &T,
TT); StringRef TT,
StringRef CPU);
typedef MCTargetAsmLexer *(*MCAsmLexerCtorTy)(const Target &T, typedef MCTargetAsmLexer *(*MCAsmLexerCtorTy)(const Target &T,
const MCRegisterInfo &MRI , const MCRegisterInfo &MRI ,
const MCAsmInfo &MAI); const MCAsmInfo &MAI);
typedef MCTargetAsmParser *(*MCAsmParserCtorTy)(MCSubtargetInfo &STI, typedef MCTargetAsmParser *(*MCAsmParserCtorTy)(MCSubtargetInfo &STI,
MCAsmParser &P); MCAsmParser &P);
typedef MCDisassembler *(*MCDisassemblerCtorTy)(const Target &T, typedef MCDisassembler *(*MCDisassemblerCtorTy)(const Target &T,
const MCSubtargetInfo & STI); const MCSubtargetInfo & STI);
typedef MCInstPrinter *(*MCInstPrinterCtorTy)(const Target &T, typedef MCInstPrinter *(*MCInstPrinterCtorTy)(const Target &T,
unsigned SyntaxVariant, unsigned SyntaxVariant,
const MCAsmInfo &MAI, const MCAsmInfo &MAI,
const MCInstrInfo &MII, const MCInstrInfo &MII,
const MCRegisterInfo &MRI , const MCRegisterInfo &MRI ,
const MCSubtargetInfo &ST I); const MCSubtargetInfo &ST I);
typedef MCCodeEmitter *(*MCCodeEmitterCtorTy)(const MCInstrInfo &II, typedef MCCodeEmitter *(*MCCodeEmitterCtorTy)(const MCInstrInfo &II,
const MCRegisterInfo &MRI ,
const MCSubtargetInfo &ST I, const MCSubtargetInfo &ST I,
MCContext &Ctx); MCContext &Ctx);
typedef MCStreamer *(*MCObjectStreamerCtorTy)(const Target &T, typedef MCStreamer *(*MCObjectStreamerCtorTy)(const Target &T,
StringRef TT, StringRef TT,
MCContext &Ctx, MCContext &Ctx,
MCAsmBackend &TAB, MCAsmBackend &TAB,
raw_ostream &_OS, raw_ostream &_OS,
MCCodeEmitter *_Emitter, MCCodeEmitter *_Emitter,
bool RelaxAll, bool RelaxAll,
bool NoExecStack); bool NoExecStack);
skipping to change at line 273 skipping to change at line 276
/// hasAsmStreamer - Check if this target supports streaming to files. /// hasAsmStreamer - Check if this target supports streaming to files.
bool hasAsmStreamer() const { return AsmStreamerCtorFn != 0; } bool hasAsmStreamer() const { return AsmStreamerCtorFn != 0; }
/// @} /// @}
/// @name Feature Constructors /// @name Feature Constructors
/// @{ /// @{
/// createMCAsmInfo - Create a MCAsmInfo implementation for the specifi ed /// createMCAsmInfo - Create a MCAsmInfo implementation for the specifi ed
/// target triple. /// target triple.
/// ///
/// \arg Triple - This argument is used to determine the target machine /// \param Triple This argument is used to determine the target machine
/// feature set; it should always be provided. Generally this should be /// feature set; it should always be provided. Generally this should be
/// either the target triple from the module, or the target triple of t he /// either the target triple from the module, or the target triple of t he
/// host if that does not exist. /// host if that does not exist.
MCAsmInfo *createMCAsmInfo(StringRef Triple) const { MCAsmInfo *createMCAsmInfo(StringRef Triple) const {
if (!MCAsmInfoCtorFn) if (!MCAsmInfoCtorFn)
return 0; return 0;
return MCAsmInfoCtorFn(*this, Triple); return MCAsmInfoCtorFn(*this, Triple);
} }
/// createMCCodeGenInfo - Create a MCCodeGenInfo implementation. /// createMCCodeGenInfo - Create a MCCodeGenInfo implementation.
skipping to change at line 319 skipping to change at line 322
/// createMCRegInfo - Create a MCRegisterInfo implementation. /// createMCRegInfo - Create a MCRegisterInfo implementation.
/// ///
MCRegisterInfo *createMCRegInfo(StringRef Triple) const { MCRegisterInfo *createMCRegInfo(StringRef Triple) const {
if (!MCRegInfoCtorFn) if (!MCRegInfoCtorFn)
return 0; return 0;
return MCRegInfoCtorFn(Triple); return MCRegInfoCtorFn(Triple);
} }
/// createMCSubtargetInfo - Create a MCSubtargetInfo implementation. /// createMCSubtargetInfo - Create a MCSubtargetInfo implementation.
/// ///
/// \arg Triple - This argument is used to determine the target machine /// \param Triple This argument is used to determine the target machine
/// feature set; it should always be provided. Generally this should be /// feature set; it should always be provided. Generally this should be
/// either the target triple from the module, or the target triple of t he /// either the target triple from the module, or the target triple of t he
/// host if that does not exist. /// host if that does not exist.
/// \arg CPU - This specifies the name of the target CPU. /// \param CPU This specifies the name of the target CPU.
/// \arg Features - This specifies the string representation of the /// \param Features This specifies the string representation of the
/// additional target features. /// additional target features.
MCSubtargetInfo *createMCSubtargetInfo(StringRef Triple, StringRef CPU, MCSubtargetInfo *createMCSubtargetInfo(StringRef Triple, StringRef CPU,
StringRef Features) const { StringRef Features) const {
if (!MCSubtargetInfoCtorFn) if (!MCSubtargetInfoCtorFn)
return 0; return 0;
return MCSubtargetInfoCtorFn(Triple, CPU, Features); return MCSubtargetInfoCtorFn(Triple, CPU, Features);
} }
/// createTargetMachine - Create a target specific machine implementati on /// createTargetMachine - Create a target specific machine implementati on
/// for the specified \arg Triple. /// for the specified \p Triple.
/// ///
/// \arg Triple - This argument is used to determine the target machine /// \param Triple This argument is used to determine the target machine
/// feature set; it should always be provided. Generally this should be /// feature set; it should always be provided. Generally this should be
/// either the target triple from the module, or the target triple of t he /// either the target triple from the module, or the target triple of t he
/// host if that does not exist. /// host if that does not exist.
TargetMachine *createTargetMachine(StringRef Triple, StringRef CPU, TargetMachine *createTargetMachine(StringRef Triple, StringRef CPU,
StringRef Features, const TargetOptions &Optio ns, StringRef Features, const TargetOptions &Optio ns,
Reloc::Model RM = Reloc::Default, Reloc::Model RM = Reloc::Default,
CodeModel::Model CM = CodeModel::Default, CodeModel::Model CM = CodeModel::Default,
CodeGenOpt::Level OL = CodeGenOpt::Default) co nst { CodeGenOpt::Level OL = CodeGenOpt::Default) co nst {
if (!TargetMachineCtorFn) if (!TargetMachineCtorFn)
return 0; return 0;
return TargetMachineCtorFn(*this, Triple, CPU, Features, Options, return TargetMachineCtorFn(*this, Triple, CPU, Features, Options,
RM, CM, OL); RM, CM, OL);
} }
/// createMCAsmBackend - Create a target specific assembly parser. /// createMCAsmBackend - Create a target specific assembly parser.
/// ///
/// \arg Triple - The target triple string. /// \param Triple The target triple string.
/// \arg Backend - The target independent assembler object. MCAsmBackend *createMCAsmBackend(StringRef Triple, StringRef CPU) const
MCAsmBackend *createMCAsmBackend(StringRef Triple) const { {
if (!MCAsmBackendCtorFn) if (!MCAsmBackendCtorFn)
return 0; return 0;
return MCAsmBackendCtorFn(*this, Triple); return MCAsmBackendCtorFn(*this, Triple, CPU);
} }
/// createMCAsmLexer - Create a target specific assembly lexer. /// createMCAsmLexer - Create a target specific assembly lexer.
/// ///
MCTargetAsmLexer *createMCAsmLexer(const MCRegisterInfo &MRI, MCTargetAsmLexer *createMCAsmLexer(const MCRegisterInfo &MRI,
const MCAsmInfo &MAI) const { const MCAsmInfo &MAI) const {
if (!MCAsmLexerCtorFn) if (!MCAsmLexerCtorFn)
return 0; return 0;
return MCAsmLexerCtorFn(*this, MRI, MAI); return MCAsmLexerCtorFn(*this, MRI, MAI);
} }
/// createMCAsmParser - Create a target specific assembly parser. /// createMCAsmParser - Create a target specific assembly parser.
/// ///
/// \arg Parser - The target independent parser implementation to use f or /// \param Parser The target independent parser implementation to use f or
/// parsing and lexing. /// parsing and lexing.
MCTargetAsmParser *createMCAsmParser(MCSubtargetInfo &STI, MCTargetAsmParser *createMCAsmParser(MCSubtargetInfo &STI,
MCAsmParser &Parser) const { MCAsmParser &Parser) const {
if (!MCAsmParserCtorFn) if (!MCAsmParserCtorFn)
return 0; return 0;
return MCAsmParserCtorFn(STI, Parser); return MCAsmParserCtorFn(STI, Parser);
} }
/// createAsmPrinter - Create a target specific assembly printer pass. This /// createAsmPrinter - Create a target specific assembly printer pass. This
/// takes ownership of the MCStreamer object. /// takes ownership of the MCStreamer object.
skipping to change at line 407 skipping to change at line 409
const MCInstrInfo &MII, const MCInstrInfo &MII,
const MCRegisterInfo &MRI, const MCRegisterInfo &MRI,
const MCSubtargetInfo &STI) const { const MCSubtargetInfo &STI) const {
if (!MCInstPrinterCtorFn) if (!MCInstPrinterCtorFn)
return 0; return 0;
return MCInstPrinterCtorFn(*this, SyntaxVariant, MAI, MII, MRI, STI); return MCInstPrinterCtorFn(*this, SyntaxVariant, MAI, MII, MRI, STI);
} }
/// createMCCodeEmitter - Create a target specific code emitter. /// createMCCodeEmitter - Create a target specific code emitter.
MCCodeEmitter *createMCCodeEmitter(const MCInstrInfo &II, MCCodeEmitter *createMCCodeEmitter(const MCInstrInfo &II,
const MCRegisterInfo &MRI,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
MCContext &Ctx) const { MCContext &Ctx) const {
if (!MCCodeEmitterCtorFn) if (!MCCodeEmitterCtorFn)
return 0; return 0;
return MCCodeEmitterCtorFn(II, STI, Ctx); return MCCodeEmitterCtorFn(II, MRI, STI, Ctx);
} }
/// createMCObjectStreamer - Create a target specific MCStreamer. /// createMCObjectStreamer - Create a target specific MCStreamer.
/// ///
/// \arg TT - The target triple. /// \param TT The target triple.
/// \arg Ctx - The target context. /// \param Ctx The target context.
/// \arg TAB - The target assembler backend object. Takes ownership. /// \param TAB The target assembler backend object. Takes ownership.
/// \arg _OS - The stream object. /// \param _OS The stream object.
/// \arg _Emitter - The target independent assembler object.Takes owner /// \param _Emitter The target independent assembler object.Takes owner
ship. ship.
/// \arg RelaxAll - Relax all fixups? /// \param RelaxAll Relax all fixups?
/// \arg NoExecStack - Mark file as not needing a executable stack. /// \param NoExecStack Mark file as not needing a executable stack.
MCStreamer *createMCObjectStreamer(StringRef TT, MCContext &Ctx, MCStreamer *createMCObjectStreamer(StringRef TT, MCContext &Ctx,
MCAsmBackend &TAB, MCAsmBackend &TAB,
raw_ostream &_OS, raw_ostream &_OS,
MCCodeEmitter *_Emitter, MCCodeEmitter *_Emitter,
bool RelaxAll, bool RelaxAll,
bool NoExecStack) const { bool NoExecStack) const {
if (!MCObjectStreamerCtorFn) if (!MCObjectStreamerCtorFn)
return 0; return 0;
return MCObjectStreamerCtorFn(*this, TT, Ctx, TAB, _OS, _Emitter, return MCObjectStreamerCtorFn(*this, TT, Ctx, TAB, _OS, _Emitter,
RelaxAll, NoExecStack); RelaxAll, NoExecStack);
skipping to change at line 512 skipping to change at line 515
static iterator end() { return iterator(); } static iterator end() { return iterator(); }
/// lookupTarget - Lookup a target based on a target triple. /// lookupTarget - Lookup a target based on a target triple.
/// ///
/// \param Triple - The triple to use for finding a target. /// \param Triple - The triple to use for finding a target.
/// \param Error - On failure, an error string describing why no target was /// \param Error - On failure, an error string describing why no target was
/// found. /// found.
static const Target *lookupTarget(const std::string &Triple, static const Target *lookupTarget(const std::string &Triple,
std::string &Error); std::string &Error);
/// lookupTarget - Lookup a target based on an architecture name
/// and a target triple. If the architecture name is non-empty,
/// then the lookup is done by architecture. Otherwise, the target
/// triple is used.
///
/// \param ArchName - The architecture to use for finding a target.
/// \param TheTriple - The triple to use for finding a target. The
/// triple is updated with canonical architecture name if a lookup
/// by architecture is done.
/// \param Error - On failure, an error string describing why no target
was
/// found.
static const Target *lookupTarget(const std::string &ArchName,
Triple &TheTriple,
std::string &Error);
/// getClosestTargetForJIT - Pick the best target that is compatible wi th /// getClosestTargetForJIT - Pick the best target that is compatible wi th
/// the current host. If no close target can be found, this returns nu ll /// the current host. If no close target can be found, this returns nu ll
/// and sets the Error string to a reason. /// and sets the Error string to a reason.
/// ///
/// Maintained for compatibility through 2.6. /// Maintained for compatibility through 2.6.
static const Target *getClosestTargetForJIT(std::string &Error); static const Target *getClosestTargetForJIT(std::string &Error);
/// @} /// @}
/// @name Target Registration /// @name Target Registration
/// @{ /// @{
skipping to change at line 1047 skipping to change at line 1065
/// extern Target TheFooTarget; /// extern Target TheFooTarget;
/// RegisterMCAsmBackend<FooAsmLexer> X(TheFooTarget); /// RegisterMCAsmBackend<FooAsmLexer> X(TheFooTarget);
/// } /// }
template<class MCAsmBackendImpl> template<class MCAsmBackendImpl>
struct RegisterMCAsmBackend { struct RegisterMCAsmBackend {
RegisterMCAsmBackend(Target &T) { RegisterMCAsmBackend(Target &T) {
TargetRegistry::RegisterMCAsmBackend(T, &Allocator); TargetRegistry::RegisterMCAsmBackend(T, &Allocator);
} }
private: private:
static MCAsmBackend *Allocator(const Target &T, StringRef Triple) { static MCAsmBackend *Allocator(const Target &T, StringRef Triple,
return new MCAsmBackendImpl(T, Triple); StringRef CPU) {
return new MCAsmBackendImpl(T, Triple, CPU);
} }
}; };
/// RegisterMCAsmLexer - Helper template for registering a target specifi c /// RegisterMCAsmLexer - Helper template for registering a target specifi c
/// assembly lexer, for use in the target machine initialization /// assembly lexer, for use in the target machine initialization
/// function. Usage: /// function. Usage:
/// ///
/// extern "C" void LLVMInitializeFooMCAsmLexer() { /// extern "C" void LLVMInitializeFooMCAsmLexer() {
/// extern Target TheFooTarget; /// extern Target TheFooTarget;
/// RegisterMCAsmLexer<FooMCAsmLexer> X(TheFooTarget); /// RegisterMCAsmLexer<FooMCAsmLexer> X(TheFooTarget);
skipping to change at line 1130 skipping to change at line 1149
/// RegisterMCCodeEmitter<FooCodeEmitter> X(TheFooTarget); /// RegisterMCCodeEmitter<FooCodeEmitter> X(TheFooTarget);
/// } /// }
template<class MCCodeEmitterImpl> template<class MCCodeEmitterImpl>
struct RegisterMCCodeEmitter { struct RegisterMCCodeEmitter {
RegisterMCCodeEmitter(Target &T) { RegisterMCCodeEmitter(Target &T) {
TargetRegistry::RegisterMCCodeEmitter(T, &Allocator); TargetRegistry::RegisterMCCodeEmitter(T, &Allocator);
} }
private: private:
static MCCodeEmitter *Allocator(const MCInstrInfo &II, static MCCodeEmitter *Allocator(const MCInstrInfo &II,
const MCRegisterInfo &MRI,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
MCContext &Ctx) { MCContext &Ctx) {
return new MCCodeEmitterImpl(); return new MCCodeEmitterImpl();
} }
}; };
} }
#endif #endif
 End of changes. 16 change blocks. 
24 lines changed or deleted 45 lines changed or added


 TargetSchedule.td   TargetSchedule.td 
skipping to change at line 13 skipping to change at line 13
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
// //
// This file is distributed under the University of Illinois Open Source // This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details. // License. See LICENSE.TXT for details.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// //
// This file defines the target-independent scheduling interfaces which sho uld // This file defines the target-independent scheduling interfaces which sho uld
// be implemented by each target which is using TableGen based scheduling. // be implemented by each target which is using TableGen based scheduling.
// //
// The SchedMachineModel is defined by subtargets for three categories of d
ata:
// 1. Basic properties for coarse grained instruction cost model.
// 2. Scheduler Read/Write resources for simple per-opcode cost model.
// 3. Instruction itineraties for detailed reservation tables.
//
// (1) Basic properties are defined by the SchedMachineModel
// class. Target hooks allow subtargets to associate opcodes with
// those properties.
//
// (2) A per-operand machine model can be implemented in any
// combination of the following ways:
//
// A. Associate per-operand SchedReadWrite types with Instructions by
// modifying the Instruction definition to inherit from Sched. For
// each subtarget, define WriteRes and ReadAdvance to associate
// processor resources and latency with each SchedReadWrite type.
//
// B. In each instruction definition, name an ItineraryClass. For each
// subtarget, define ItinRW entries to map ItineraryClass to
// per-operand SchedReadWrite types. Unlike method A, these types may
// be subtarget specific and can be directly associated with resources
// by defining SchedWriteRes and SchedReadAdvance.
//
// C. In the subtarget, map SchedReadWrite types to specific
// opcodes. This overrides any SchedReadWrite types or
// ItineraryClasses defined by the Instruction. As in method B, the
// subtarget can directly associate resources with SchedReadWrite
// types by defining SchedWriteRes and SchedReadAdvance.
//
// D. In either the target or subtarget, define SchedWriteVariant or
// SchedReadVariant to map one SchedReadWrite type onto another
// sequence of SchedReadWrite types. This allows dynamic selection of
// an instruction's machine model via custom C++ code. It also allows
// a machine-independent SchedReadWrite type to map to a sequence of
// machine-dependent types.
//
// (3) A per-pipeline-stage machine model can be implemented by providing
// Itineraries in addition to mapping instructions to ItineraryClasses.
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
//===---------------------------------------------------------------------- // Include legacy support for instruction itineraries.
===// include "llvm/Target/TargetItinerary.td"
// Processor functional unit - These values represent the function units
// available across all chip sets for the target. Eg., IntUnit, FPUnit, ..
.
// These may be independent values for each chip set or may be shared acros
s
// all chip sets of the target. Each functional unit is treated as a resou
rce
// during scheduling and has an affect instruction order based on availabil
ity
// during a time interval.
//
class FuncUnit;
//===---------------------------------------------------------------------- class Instruction; // Forward def
===//
// Pipeline bypass / forwarding - These values specifies the symbolic names // DAG operator that interprets the DAG args as Instruction defs.
of def instrs;
// pipeline bypasses which can be used to forward results of instructions
// that are forwarded to uses.
class Bypass;
def NoBypass : Bypass;
class ReservationKind<bits<1> val> { // DAG operator that interprets each DAG arg as a regex pattern for
int Value = val; // matching Instruction opcode names.
// The regex must match the beginning of the opcode (as in Python re.match)
.
// To avoid matching prefixes, append '$' to the pattern.
def instregex;
// Define the SchedMachineModel and provide basic properties for
// coarse grained instruction cost model. Default values for the
// properties are defined in MCSchedModel. A value of "-1" in the
// target description's SchedMachineModel indicates that the property
// is not overriden by the target.
//
// Target hooks allow subtargets to associate LoadLatency and
// HighLatency with groups of opcodes.
class SchedMachineModel {
int IssueWidth = -1; // Max micro-ops that may be scheduled per cycle.
int MinLatency = -1; // Determines which instrucions are allowed in a gro
up.
// (-1) inorder (0) ooo, (1): inorder +var latencies
.
int LoadLatency = -1; // Cycles for loads to access the cache.
int HighLatency = -1; // Approximation of cycles for "high latency" ops.
int MispredictPenalty = -1; // Extra cycles for a mispredicted branch.
// Per-cycle resources tables.
ProcessorItineraries Itineraries = NoItineraries;
bit NoModel = 0; // Special tag to indicate missing machine model.
} }
def Required : ReservationKind<0>; def NoSchedModel : SchedMachineModel {
def Reserved : ReservationKind<1>; let NoModel = 1;
}
//===---------------------------------------------------------------------- // Define a kind of processor resource that may be common across
===// // similar subtargets.
// Instruction stage - These values represent a non-pipelined step in class ProcResourceKind;
// the execution of an instruction. Cycles represents the number of
// discrete time slots needed to complete the stage. Units represent // Define a number of interchangeable processor resources. NumUnits
// the choice of functional units that can be used to complete the // determines the throughput of instructions that require the resource.
// stage. Eg. IntUnit1, IntUnit2. NextCycles indicates how many //
// cycles should elapse from the start of this stage to the start of // An optional Super resource may be given to model these resources as
// the next stage in the itinerary. For example: // a subset of the more general super resources. Using one of these
// // resources implies using one of the super resoruces.
// A stage is specified in one of two ways: //
// // ProcResourceUnits normally model a few buffered resources within an
// InstrStage<1, [FU_x, FU_y]> - TimeInc defaults to Cycles // out-of-order engine that the compiler attempts to conserve.
// InstrStage<1, [FU_x, FU_y], 0> - TimeInc explicit // Buffered resources may be held for multiple clock cycles, but the
// // scheduler does not pin them to a particular clock cycle relative to
// instruction dispatch. Setting Buffered=0 changes this to an
class InstrStage<int cycles, list<FuncUnit> units, // in-order resource. In this case, the scheduler counts down from the
int timeinc = -1, // cycle that the instruction issues in-order, forcing an interlock
ReservationKind kind = Required> { // with subsequent instructions that require the same resource until
int Cycles = cycles; // length of stage in machine cycles // the number of ResourceCyles specified in WriteRes expire.
list<FuncUnit> Units = units; // choice of functional units //
int TimeInc = timeinc; // cycles till start of next stage // SchedModel ties these units to a processor for any stand-alone defs
int Kind = kind.Value; // kind of FU reservation // of this class. Instances of subclass ProcResource will be automatically
// attached to a processor, so SchedModel is not needed.
class ProcResourceUnits<ProcResourceKind kind, int num> {
ProcResourceKind Kind = kind;
int NumUnits = num;
ProcResourceKind Super = ?;
bit Buffered = 1;
SchedMachineModel SchedModel = ?;
} }
//===---------------------------------------------------------------------- // EponymousProcResourceKind helps implement ProcResourceUnits by
===// // allowing a ProcResourceUnits definition to reference itself. It
// Instruction itinerary - An itinerary represents a sequential series of s // should not be referenced anywhere else.
teps def EponymousProcResourceKind : ProcResourceKind;
// required to complete an instruction. Itineraries are represented as lis
ts of // Subtargets typically define processor resource kind and number of
// instruction stages. // units in one place.
class ProcResource<int num> : ProcResourceKind,
ProcResourceUnits<EponymousProcResourceKind, num>;
// A target architecture may define SchedReadWrite types and associate
// them with instruction operands.
class SchedReadWrite;
// List the per-operand types that map to the machine model of an
// instruction. One SchedWrite type must be listed for each explicit
// def operand in order. Additional SchedWrite types may optionally be
// listed for implicit def operands. SchedRead types may optionally
// be listed for use operands in order. The order of defs relative to
// uses is insignificant. This way, the same SchedReadWrite list may
// be used for multiple forms of an operation. For example, a
// two-address instruction could have two tied operands or single
// operand that both reads and writes a reg. In both cases we have a
// single SchedWrite and single SchedRead in any order.
class Sched<list<SchedReadWrite> schedrw> {
list<SchedReadWrite> SchedRW = schedrw;
}
// Define a scheduler resource associated with a def operand.
class SchedWrite : SchedReadWrite;
def NoWrite : SchedWrite;
// Define a scheduler resource associated with a use operand.
class SchedRead : SchedReadWrite;
// Define a SchedWrite that is modeled as a sequence of other
// SchedWrites with additive latency. This allows a single operand to
// be mapped the resources composed from a set of previously defined
// SchedWrites.
//
// If the final write in this sequence is a SchedWriteVariant marked
// Variadic, then the list of prior writes are distributed across all
// operands after resolving the predicate for the final write.
//
// SchedModel silences warnings but is ignored.
class WriteSequence<list<SchedWrite> writes, int rep = 1> : SchedWrite {
list<SchedWrite> Writes = writes;
int Repeat = rep;
SchedMachineModel SchedModel = ?;
}
// Define values common to WriteRes and SchedWriteRes.
// //
// SchedModel ties these resources to a processor.
class ProcWriteResources<list<ProcResourceKind> resources> {
list<ProcResourceKind> ProcResources = resources;
list<int> ResourceCycles = [];
int Latency = 1;
int NumMicroOps = 1;
bit BeginGroup = 0;
bit EndGroup = 0;
// Allow a processor to mark some scheduling classes as unsupported
// for stronger verification.
bit Unsupported = 0;
SchedMachineModel SchedModel = ?;
}
//===---------------------------------------------------------------------- // Define the resources and latency of a SchedWrite. This will be used
===// // directly by targets that have no itinerary classes. In this case,
// Instruction itinerary classes - These values represent 'named' instructi // SchedWrite is defined by the target, while WriteResources is
on // defined by the subtarget, and maps the SchedWrite to processor
// itinerary. Using named itineraries simplifies managing groups of // resources.
// instructions across chip sets. An instruction uses the same itinerary c //
lass // If a target already has itinerary classes, SchedWriteResources can
// across all chip sets. Thus a new chip set can be added without modifyin // be used instead to define subtarget specific SchedWrites and map
g // them to processor resources in one place. Then ItinRW can map
// instruction information. // itinerary classes to the subtarget's SchedWrites.
// //
// NumMicroOps represents the number of micro-operations that each instruct // ProcResources indicates the set of resources consumed by the write.
ion // Optionally, ResourceCycles indicates the number of cycles the
// in the class are decoded to. If the number is zero, then it means the // resource is consumed. Each ResourceCycles item is paired with the
// instruction can decode into variable number of micro-ops and it must be // ProcResource item at the same position in its list. Since
// determined dynamically. // ResourceCycles are rarely specialized, the list may be
// incomplete. By default, resources are consumed for a single cycle,
// regardless of latency, which models a fully pipelined processing
// unit. A value of 0 for ResourceCycles means that the resource must
// be available but is not consumed, which is only relevant for
// unbuffered resources.
//
// By default, each SchedWrite takes one micro-op, which is counted
// against the processor's IssueWidth limit. If an instruction can
// write multiple registers with a single micro-op, the subtarget
// should define one of the writes to be zero micro-ops. If a
// subtarget requires multiple micro-ops to write a single result, it
// should either override the write's NumMicroOps to be greater than 1
// or require additional writes. Extra writes can be required either
// by defining a WriteSequence, or simply listing extra writes in the
// instruction's list of writers beyond the number of "def"
// operands. The scheduler assumes that all micro-ops must be
// dispatched in the same cycle. These micro-ops may be required to
// begin or end the current dispatch group.
class WriteRes<SchedWrite write, list<ProcResourceKind> resources>
: ProcWriteResources<resources> {
SchedWrite WriteType = write;
}
// Directly name a set of WriteResources defining a new SchedWrite
// type at the same time. This class is unaware of its SchedModel so
// must be referenced by InstRW or ItinRW.
class SchedWriteRes<list<ProcResourceKind> resources> : SchedWrite,
ProcWriteResources<resources>;
// Define values common to ReadAdvance and SchedReadAdvance.
//
// SchedModel ties these resources to a processor.
class ProcReadAdvance<int cycles, list<SchedWrite> writes = []> {
int Cycles = cycles;
list<SchedWrite> ValidWrites = writes;
// Allow a processor to mark some scheduling classes as unsupported
// for stronger verification.
bit Unsupported = 0;
SchedMachineModel SchedModel = ?;
}
// A processor may define a ReadAdvance associated with a SchedRead
// to reduce latency of a prior write by N cycles. A negative advance
// effectively increases latency, which may be used for cross-domain
// stalls.
//
// A ReadAdvance may be associated with a list of SchedWrites
// to implement pipeline bypass. The Writes list may be empty to
// indicate operands that are always read this number of Cycles later
// than a normal register read, allowing the read's parent instruction
// to issue earlier relative to the writer.
class ReadAdvance<SchedRead read, int cycles, list<SchedWrite> writes = []>
: ProcReadAdvance<cycles, writes> {
SchedRead ReadType = read;
}
// Directly associate a new SchedRead type with a delay and optional
// pipeline bypess. For use with InstRW or ItinRW.
class SchedReadAdvance<int cycles, list<SchedWrite> writes = []> : SchedRea
d,
ProcReadAdvance<cycles, writes>;
// Define SchedRead defaults. Reads seldom need special treatment.
def ReadDefault : SchedRead;
def NoReadAdvance : SchedReadAdvance<0>;
// Define shared code that will be in the same scope as all
// SchedPredicates. Available variables are:
// (const MachineInstr *MI, const TargetSchedModel *SchedModel)
class PredicateProlog<code c> {
code Code = c;
}
// Define a predicate to determine which SchedVariant applies to a
// particular MachineInstr. The code snippet is used as an
// if-statement's expression. Available variables are MI, SchedModel,
// and anything defined in a PredicateProlog.
//
// SchedModel silences warnings but is ignored.
class SchedPredicate<code pred> {
SchedMachineModel SchedModel = ?;
code Predicate = pred;
}
def NoSchedPred : SchedPredicate<[{true}]>;
// Associate a predicate with a list of SchedReadWrites. By default,
// the selected SchedReadWrites are still associated with a single
// operand and assumed to execute sequentially with additive
// latency. However, if the parent SchedWriteVariant or
// SchedReadVariant is marked "Variadic", then each Selected
// SchedReadWrite is mapped in place to the instruction's variadic
// operands. In this case, latency is not additive. If the current Variant
// is already part of a Sequence, then that entire chain leading up to
// the Variant is distributed over the variadic operands.
class SchedVar<SchedPredicate pred, list<SchedReadWrite> selected> {
SchedPredicate Predicate = pred;
list<SchedReadWrite> Selected = selected;
}
// SchedModel silences warnings but is ignored.
class SchedVariant<list<SchedVar> variants> {
list<SchedVar> Variants = variants;
bit Variadic = 0;
SchedMachineModel SchedModel = ?;
}
// A SchedWriteVariant is a single SchedWrite type that maps to a list
// of SchedWrite types under the conditions defined by its predicates.
// //
class InstrItinClass<int ops = 1> { // A Variadic write is expanded to cover multiple "def" operands. The
int NumMicroOps = ops; // SchedVariant's Expansion list is then interpreted as one write
// per-operand instead of the usual sequential writes feeding a single
// operand.
class SchedWriteVariant<list<SchedVar> variants> : SchedWrite,
SchedVariant<variants> {
} }
def NoItinerary : InstrItinClass;
//===---------------------------------------------------------------------- // A SchedReadVariant is a single SchedRead type that maps to a list
===// // of SchedRead types under the conditions defined by its predicates.
// Instruction itinerary data - These values provide a runtime map of an
// instruction itinerary class (name) to its itinerary data.
// //
// OperandCycles are optional "cycle counts". They specify the cycle after // A Variadic write is expanded to cover multiple "readsReg" operands as
// instruction issue the values which correspond to specific operand indice // explained above.
s class SchedReadVariant<list<SchedVar> variants> : SchedRead,
// are defined or read. Bypasses are optional "pipeline forwarding pathes", SchedVariant<variants> {
if
// a def by an instruction is available on a specific bypass and the use ca
n
// read from the same bypass, then the operand use latency is reduced by on
e.
//
// InstrItinData<IIC_iLoad_i , [InstrStage<1, [A9_Pipe1]>,
// InstrStage<1, [A9_AGU]>],
// [3, 1], [A9_LdBypass]>,
// InstrItinData<IIC_iMVNr , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>],
// [1, 1], [NoBypass, A9_LdBypass]>,
//
// In this example, the instruction of IIC_iLoadi reads its input on cycle
1
// (after issue) and the result of the load is available on cycle 3. The re
sult
// is available via forwarding path A9_LdBypass. If it's used by the first
// source operand of instructions of IIC_iMVNr class, then the operand late
ncy
// is reduced by 1.
class InstrItinData<InstrItinClass Class, list<InstrStage> stages,
list<int> operandcycles = [],
list<Bypass> bypasses = []> {
InstrItinClass TheClass = Class;
list<InstrStage> Stages = stages;
list<int> OperandCycles = operandcycles;
list<Bypass> Bypasses = bypasses;
} }
//===---------------------------------------------------------------------- // Map a set of opcodes to a list of SchedReadWrite types. This allows
===// // the subtarget to easily override specific operations.
// Processor itineraries - These values represent the set of all itinerary
// classes for a given chip set.
// //
class ProcessorItineraries<list<FuncUnit> fu, list<Bypass> bp, // SchedModel ties this opcode mapping to a processor.
list<InstrItinData> iid> { class InstRW<list<SchedReadWrite> rw, dag instrlist> {
list<FuncUnit> FU = fu; list<SchedReadWrite> OperandReadWrites = rw;
list<Bypass> BP = bp; dag Instrs = instrlist;
list<InstrItinData> IID = iid; SchedMachineModel SchedModel = ?;
}
// Map a set of itinerary classes to SchedReadWrite resources. This is
// used to bootstrap a target (e.g. ARM) when itineraries already
// exist and changing InstrInfo is undesirable.
//
// SchedModel ties this ItineraryClass mapping to a processor.
class ItinRW<list<SchedReadWrite> rw, list<InstrItinClass> iic> {
list<InstrItinClass> MatchedItinClasses = iic;
list<SchedReadWrite> OperandReadWrites = rw;
SchedMachineModel SchedModel = ?;
} }
// NoItineraries - A marker that can be used by processors without schedule // Alias a target-defined SchedReadWrite to a processor specific
// info. // SchedReadWrite. This allows a subtarget to easily map a
def NoItineraries : ProcessorItineraries<[], [], []>; // SchedReadWrite type onto a WriteSequence, SchedWriteVariant, or
// SchedReadVariant.
//
// SchedModel will usually be provided by surrounding let statement
// and ties this SchedAlias mapping to a processor.
class SchedAlias<SchedReadWrite match, SchedReadWrite alias> {
SchedReadWrite MatchRW = match;
SchedReadWrite AliasRW = alias;
SchedMachineModel SchedModel = ?;
}
 End of changes. 16 change blocks. 
119 lines changed or deleted 326 lines changed or added


 TargetSelectionDAG.td   TargetSelectionDAG.td 
skipping to change at line 406 skipping to change at line 406
def setcc : SDNode<"ISD::SETCC" , SDTSetCC>; def setcc : SDNode<"ISD::SETCC" , SDTSetCC>;
def select : SDNode<"ISD::SELECT" , SDTSelect>; def select : SDNode<"ISD::SELECT" , SDTSelect>;
def vselect : SDNode<"ISD::VSELECT" , SDTVSelect>; def vselect : SDNode<"ISD::VSELECT" , SDTVSelect>;
def selectcc : SDNode<"ISD::SELECT_CC" , SDTSelectCC>; def selectcc : SDNode<"ISD::SELECT_CC" , SDTSelectCC>;
def brcond : SDNode<"ISD::BRCOND" , SDTBrcond, [SDNPHasChain]>; def brcond : SDNode<"ISD::BRCOND" , SDTBrcond, [SDNPHasChain]>;
def brind : SDNode<"ISD::BRIND" , SDTBrind, [SDNPHasChain]>; def brind : SDNode<"ISD::BRIND" , SDTBrind, [SDNPHasChain]>;
def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>; def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>;
def trap : SDNode<"ISD::TRAP" , SDTNone, def trap : SDNode<"ISD::TRAP" , SDTNone,
[SDNPHasChain, SDNPSideEffect]>; [SDNPHasChain, SDNPSideEffect]>;
def debugtrap : SDNode<"ISD::DEBUGTRAP" , SDTNone,
[SDNPHasChain, SDNPSideEffect]>;
def prefetch : SDNode<"ISD::PREFETCH" , SDTPrefetch, def prefetch : SDNode<"ISD::PREFETCH" , SDTPrefetch,
[SDNPHasChain, SDNPMayLoad, SDNPMayStore, [SDNPHasChain, SDNPMayLoad, SDNPMayStore,
SDNPMemOperand]>; SDNPMemOperand]>;
def readcyclecounter : SDNode<"ISD::READCYCLECOUNTER", SDTIntLeaf,
[SDNPHasChain, SDNPSideEffect]>;
def membarrier : SDNode<"ISD::MEMBARRIER" , SDTMemBarrier, def membarrier : SDNode<"ISD::MEMBARRIER" , SDTMemBarrier,
[SDNPHasChain, SDNPSideEffect]>; [SDNPHasChain, SDNPSideEffect]>;
def atomic_fence : SDNode<"ISD::ATOMIC_FENCE" , SDTAtomicFence, def atomic_fence : SDNode<"ISD::ATOMIC_FENCE" , SDTAtomicFence,
[SDNPHasChain, SDNPSideEffect]>; [SDNPHasChain, SDNPSideEffect]>;
def atomic_cmp_swap : SDNode<"ISD::ATOMIC_CMP_SWAP" , SDTAtomic3, def atomic_cmp_swap : SDNode<"ISD::ATOMIC_CMP_SWAP" , SDTAtomic3,
[SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperan d]>; [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperan d]>;
def atomic_load_add : SDNode<"ISD::ATOMIC_LOAD_ADD" , SDTAtomic2, def atomic_load_add : SDNode<"ISD::ATOMIC_LOAD_ADD" , SDTAtomic2,
[SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperan d]>; [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperan d]>;
skipping to change at line 442 skipping to change at line 447
[SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperan d]>; [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperan d]>;
def atomic_load_min : SDNode<"ISD::ATOMIC_LOAD_MIN", SDTAtomic2, def atomic_load_min : SDNode<"ISD::ATOMIC_LOAD_MIN", SDTAtomic2,
[SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperan d]>; [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperan d]>;
def atomic_load_max : SDNode<"ISD::ATOMIC_LOAD_MAX", SDTAtomic2, def atomic_load_max : SDNode<"ISD::ATOMIC_LOAD_MAX", SDTAtomic2,
[SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperan d]>; [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperan d]>;
def atomic_load_umin : SDNode<"ISD::ATOMIC_LOAD_UMIN", SDTAtomic2, def atomic_load_umin : SDNode<"ISD::ATOMIC_LOAD_UMIN", SDTAtomic2,
[SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperan d]>; [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperan d]>;
def atomic_load_umax : SDNode<"ISD::ATOMIC_LOAD_UMAX", SDTAtomic2, def atomic_load_umax : SDNode<"ISD::ATOMIC_LOAD_UMAX", SDTAtomic2,
[SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperan d]>; [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperan d]>;
def atomic_load : SDNode<"ISD::ATOMIC_LOAD", SDTAtomicLoad, def atomic_load : SDNode<"ISD::ATOMIC_LOAD", SDTAtomicLoad,
[SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperan d]>; [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
def atomic_store : SDNode<"ISD::ATOMIC_STORE", SDTAtomicStore, def atomic_store : SDNode<"ISD::ATOMIC_STORE", SDTAtomicStore,
[SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperan d]>; [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
// Do not use ld, st directly. Use load, extload, sextload, zextload, store , // Do not use ld, st directly. Use load, extload, sextload, zextload, store ,
// and truncst (see below). // and truncst (see below).
def ld : SDNode<"ISD::LOAD" , SDTLoad, def ld : SDNode<"ISD::LOAD" , SDTLoad,
[SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
def st : SDNode<"ISD::STORE" , SDTStore, def st : SDNode<"ISD::STORE" , SDTStore,
[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
def ist : SDNode<"ISD::STORE" , SDTIStore, def ist : SDNode<"ISD::STORE" , SDTIStore,
[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
skipping to change at line 589 skipping to change at line 594
}]>; }]>;
def immAllZerosV: PatLeaf<(build_vector), [{ def immAllZerosV: PatLeaf<(build_vector), [{
return ISD::isBuildVectorAllZeros(N); return ISD::isBuildVectorAllZeros(N);
}]>; }]>;
// Other helper fragments. // Other helper fragments.
def not : PatFrag<(ops node:$in), (xor node:$in, -1)>; def not : PatFrag<(ops node:$in), (xor node:$in, -1)>;
def vnot : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV)>; def vnot : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV)>;
def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>; def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>;
// null_frag - The null pattern operator is used in multiclass instantiatio
ns
// which accept an SDPatternOperator for use in matching patterns for inter
nal
// definitions. When expanding a pattern, if the null fragment is reference
d
// in the expansion, the pattern is discarded and it is as-if '[]' had been
// specified. This allows multiclasses to have the isel patterns be optiona
l.
def null_frag : SDPatternOperator;
// load fragments. // load fragments.
def unindexedload : PatFrag<(ops node:$ptr), (ld node:$ptr), [{ def unindexedload : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
return cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED; return cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
}]>; }]>;
def load : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ def load : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
return cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD; return cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD;
}]>; }]>;
// extending load fragments. // extending load fragments.
def extload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ def extload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
 End of changes. 5 change blocks. 
2 lines changed or deleted 18 lines changed or added


 TargetSelectionDAGInfo.h   TargetSelectionDAGInfo.h 
skipping to change at line 23 skipping to change at line 23
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_TARGET_TARGETSELECTIONDAGINFO_H #ifndef LLVM_TARGET_TARGETSELECTIONDAGINFO_H
#define LLVM_TARGET_TARGETSELECTIONDAGINFO_H #define LLVM_TARGET_TARGETSELECTIONDAGINFO_H
#include "llvm/CodeGen/SelectionDAGNodes.h" #include "llvm/CodeGen/SelectionDAGNodes.h"
namespace llvm { namespace llvm {
class TargetData; class DataLayout;
class TargetMachine; class TargetMachine;
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
/// TargetSelectionDAGInfo - Targets can subclass this to parameterize the /// TargetSelectionDAGInfo - Targets can subclass this to parameterize the
/// SelectionDAG lowering and instruction selection process. /// SelectionDAG lowering and instruction selection process.
/// ///
class TargetSelectionDAGInfo { class TargetSelectionDAGInfo {
TargetSelectionDAGInfo(const TargetSelectionDAGInfo &); // DO NOT IMPLEME TargetSelectionDAGInfo(const TargetSelectionDAGInfo &) LLVM_DELETED_FUNCT
NT ION;
void operator=(const TargetSelectionDAGInfo &); // DO NOT IMPLEME void operator=(const TargetSelectionDAGInfo &) LLVM_DELETED_FUNCTION;
NT
const TargetData *TD; const DataLayout *TD;
protected: protected:
const TargetData *getTargetData() const { return TD; } const DataLayout *getDataLayout() const { return TD; }
public: public:
explicit TargetSelectionDAGInfo(const TargetMachine &TM); explicit TargetSelectionDAGInfo(const TargetMachine &TM);
virtual ~TargetSelectionDAGInfo(); virtual ~TargetSelectionDAGInfo();
/// EmitTargetCodeForMemcpy - Emit target-specific code that performs a /// EmitTargetCodeForMemcpy - Emit target-specific code that performs a
/// memcpy. This can be used by targets to provide code sequences for cas es /// memcpy. This can be used by targets to provide code sequences for cas es
/// that don't fit the target's parameters for simple loads/stores and ca n be /// that don't fit the target's parameters for simple loads/stores and ca n be
/// more efficient than using a library call. This function can return a null /// more efficient than using a library call. This function can return a null
/// SDValue if the target declines to use custom code and a different /// SDValue if the target declines to use custom code and a different
 End of changes. 4 change blocks. 
7 lines changed or deleted 6 lines changed or added


 TargetSubtargetInfo.h   TargetSubtargetInfo.h 
skipping to change at line 22 skipping to change at line 22
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_TARGET_TARGETSUBTARGETINFO_H #ifndef LLVM_TARGET_TARGETSUBTARGETINFO_H
#define LLVM_TARGET_TARGETSUBTARGETINFO_H #define LLVM_TARGET_TARGETSUBTARGETINFO_H
#include "llvm/MC/MCSubtargetInfo.h" #include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/Support/CodeGen.h" #include "llvm/Support/CodeGen.h"
namespace llvm { namespace llvm {
class MachineInstr;
class SDep; class SDep;
class SUnit; class SUnit;
class TargetRegisterClass; class TargetRegisterClass;
class TargetSchedModel;
template <typename T> class SmallVectorImpl; template <typename T> class SmallVectorImpl;
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
/// ///
/// TargetSubtargetInfo - Generic base class for all target subtargets. Al l /// TargetSubtargetInfo - Generic base class for all target subtargets. Al l
/// Target-specific options that control code generation and printing shoul d /// Target-specific options that control code generation and printing shoul d
/// be exposed through a TargetSubtargetInfo-derived class. /// be exposed through a TargetSubtargetInfo-derived class.
/// ///
class TargetSubtargetInfo : public MCSubtargetInfo { class TargetSubtargetInfo : public MCSubtargetInfo {
TargetSubtargetInfo(const TargetSubtargetInfo&); // DO NOT IMPLEMENT TargetSubtargetInfo(const TargetSubtargetInfo&) LLVM_DELETED_FUNCTION;
void operator=(const TargetSubtargetInfo&); // DO NOT IMPLEMENT void operator=(const TargetSubtargetInfo&) LLVM_DELETED_FUNCTION;
protected: // Can only create subclasses... protected: // Can only create subclasses...
TargetSubtargetInfo(); TargetSubtargetInfo();
public: public:
// AntiDepBreakMode - Type of anti-dependence breaking that should // AntiDepBreakMode - Type of anti-dependence breaking that should
// be performed before post-RA scheduling. // be performed before post-RA scheduling.
typedef enum { ANTIDEP_NONE, ANTIDEP_CRITICAL, ANTIDEP_ALL } AntiDepBreak Mode; typedef enum { ANTIDEP_NONE, ANTIDEP_CRITICAL, ANTIDEP_ALL } AntiDepBreak Mode;
typedef SmallVectorImpl<const TargetRegisterClass*> RegClassVector; typedef SmallVectorImpl<const TargetRegisterClass*> RegClassVector;
virtual ~TargetSubtargetInfo(); virtual ~TargetSubtargetInfo();
/// getSpecialAddressLatency - For targets where it is beneficial to /// Resolve a SchedClass at runtime, where SchedClass identifies an
/// backschedule instructions that compute addresses, return a value /// MCSchedClassDesc with the isVariant property. This may return the ID
/// indicating the number of scheduling cycles of backscheduling that of
/// should be attempted. /// another variant SchedClass, but repeated invocation must quickly term
virtual unsigned getSpecialAddressLatency() const { return 0; } inate
/// in a nonvariant SchedClass.
virtual unsigned resolveSchedClass(unsigned SchedClass, const MachineInst
r *MI,
const TargetSchedModel* SchedModel) co
nst {
return 0;
}
// enablePostRAScheduler - If the target can benefit from post-regalloc // enablePostRAScheduler - If the target can benefit from post-regalloc
// scheduling and the specified optimization level meets the requirement // scheduling and the specified optimization level meets the requirement
// return true to enable post-register-allocation scheduling. In // return true to enable post-register-allocation scheduling. In
// CriticalPathRCs return any register classes that should only be broken // CriticalPathRCs return any register classes that should only be broken
// if on the critical path. // if on the critical path.
virtual bool enablePostRAScheduler(CodeGenOpt::Level OptLevel, virtual bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
AntiDepBreakMode& Mode, AntiDepBreakMode& Mode,
RegClassVector& CriticalPathRCs) const ; RegClassVector& CriticalPathRCs) const ;
// adjustSchedDependency - Perform target specific adjustments to // adjustSchedDependency - Perform target specific adjustments to
 End of changes. 4 change blocks. 
7 lines changed or deleted 16 lines changed or added


 Targets.def   Targets.def 
skipping to change at line 26 skipping to change at line 26
|* The set of targets supported by LLVM is generated at configuration *| |* The set of targets supported by LLVM is generated at configuration *|
|* time, at which point this header is generated. Do not modify this *| |* time, at which point this header is generated. Do not modify this *|
|* header directly. *| |* header directly. *|
|* *| |* *|
\*===---------------------------------------------------------------------- ===*/ \*===---------------------------------------------------------------------- ===*/
#ifndef LLVM_TARGET #ifndef LLVM_TARGET
# error Please define the macro LLVM_TARGET(TargetName) # error Please define the macro LLVM_TARGET(TargetName)
#endif #endif
LLVM_TARGET(Hexagon) LLVM_TARGET(PTX) LLVM_TARGET(MBlaze) LLVM_TARGET(CppBa ckend) LLVM_TARGET(MSP430) LLVM_TARGET(XCore) LLVM_TARGET(CellSPU) LLVM_TAR GET(Mips) LLVM_TARGET(ARM) LLVM_TARGET(PowerPC) LLVM_TARGET(Sparc) LLVM_TAR GET(X86) LLVM_TARGET(Hexagon) LLVM_TARGET(NVPTX) LLVM_TARGET(MBlaze) LLVM_TARGET(Cpp Backend) LLVM_TARGET(MSP430) LLVM_TARGET(XCore) LLVM_TARGET(CellSPU) LLVM_T ARGET(Mips) LLVM_TARGET(ARM) LLVM_TARGET(PowerPC) LLVM_TARGET(Sparc) LLVM_T ARGET(X86)
#undef LLVM_TARGET #undef LLVM_TARGET
 End of changes. 1 change blocks. 
1 lines changed or deleted 1 lines changed or added


 ThreadLocal.h   ThreadLocal.h 
skipping to change at line 18 skipping to change at line 18
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// //
// This file declares the llvm::sys::ThreadLocal class. // This file declares the llvm::sys::ThreadLocal class.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_SYSTEM_THREAD_LOCAL_H #ifndef LLVM_SYSTEM_THREAD_LOCAL_H
#define LLVM_SYSTEM_THREAD_LOCAL_H #define LLVM_SYSTEM_THREAD_LOCAL_H
#include "llvm/Support/Threading.h" #include "llvm/Support/Threading.h"
#include "llvm/Support/DataTypes.h"
#include <cassert> #include <cassert>
namespace llvm { namespace llvm {
namespace sys { namespace sys {
// ThreadLocalImpl - Common base class of all ThreadLocal instantiation s. // ThreadLocalImpl - Common base class of all ThreadLocal instantiation s.
// YOU SHOULD NEVER USE THIS DIRECTLY. // YOU SHOULD NEVER USE THIS DIRECTLY.
class ThreadLocalImpl { class ThreadLocalImpl {
void* data; typedef uint64_t ThreadLocalDataTy;
/// \brief Platform-specific thread local data.
///
/// This is embedded in the class and we avoid malloc'ing/free'ing it
,
/// to make this class more safe for use along with CrashRecoveryCont
ext.
union {
char data[sizeof(ThreadLocalDataTy)];
ThreadLocalDataTy align_data;
};
public: public:
ThreadLocalImpl(); ThreadLocalImpl();
virtual ~ThreadLocalImpl(); virtual ~ThreadLocalImpl();
void setInstance(const void* d); void setInstance(const void* d);
const void* getInstance(); const void* getInstance();
void removeInstance(); void removeInstance();
}; };
/// ThreadLocal - A class used to abstract thread-local storage. It ho lds, /// ThreadLocal - A class used to abstract thread-local storage. It ho lds,
/// for each thread, a pointer a single object of type T. /// for each thread, a pointer a single object of type T.
 End of changes. 2 change blocks. 
1 lines changed or deleted 12 lines changed or added


 Threading.h   Threading.h 
skipping to change at line 44 skipping to change at line 44
bool llvm_is_multithreaded(); bool llvm_is_multithreaded();
/// acquire_global_lock - Acquire the global lock. This is a no-op if ca lled /// acquire_global_lock - Acquire the global lock. This is a no-op if ca lled
/// before llvm_start_multithreaded(). /// before llvm_start_multithreaded().
void llvm_acquire_global_lock(); void llvm_acquire_global_lock();
/// release_global_lock - Release the global lock. This is a no-op if ca lled /// release_global_lock - Release the global lock. This is a no-op if ca lled
/// before llvm_start_multithreaded(). /// before llvm_start_multithreaded().
void llvm_release_global_lock(); void llvm_release_global_lock();
/// llvm_execute_on_thread - Execute the given \arg UserFn on a separate /// llvm_execute_on_thread - Execute the given \p UserFn on a separate
/// thread, passing it the provided \arg UserData. /// thread, passing it the provided \p UserData.
/// ///
/// This function does not guarantee that the code will actually be execu ted /// This function does not guarantee that the code will actually be execu ted
/// on a separate thread or honoring the requested stack size, but tries to do /// on a separate thread or honoring the requested stack size, but tries to do
/// so where system support is available. /// so where system support is available.
/// ///
/// \param UserFn - The callback to execute. /// \param UserFn - The callback to execute.
/// \param UserData - An argument to pass to the callback function. /// \param UserData - An argument to pass to the callback function.
/// \param RequestedStackSize - If non-zero, a requested size (in bytes) for /// \param RequestedStackSize - If non-zero, a requested size (in bytes) for
/// the thread stack. /// the thread stack.
void llvm_execute_on_thread(void (*UserFn)(void*), void *UserData, void llvm_execute_on_thread(void (*UserFn)(void*), void *UserData,
 End of changes. 1 change blocks. 
2 lines changed or deleted 2 lines changed or added


 TimeValue.h   TimeValue.h 
skipping to change at line 156 skipping to change at line 156
return 0; return 0;
} }
/// Determine if \p this is less than or equal to \p that. /// Determine if \p this is less than or equal to \p that.
/// @returns True iff *this <= that. /// @returns True iff *this <= that.
/// @brief True if this <= that. /// @brief True if this <= that.
int operator <= (const TimeValue &that) const { return that >= *this; } int operator <= (const TimeValue &that) const { return that >= *this; }
/// Determine if \p this is greater than or equal to \p that. /// Determine if \p this is greater than or equal to \p that.
/// @returns True iff *this >= that. /// @returns True iff *this >= that.
/// @brief True if this >= that.
int operator >= (const TimeValue &that) const { int operator >= (const TimeValue &that) const {
if ( this->seconds_ > that.seconds_ ) { if ( this->seconds_ > that.seconds_ ) {
return 1; return 1;
} else if ( this->seconds_ == that.seconds_ ) { } else if ( this->seconds_ == that.seconds_ ) {
if ( this->nanos_ >= that.nanos_ ) return 1; if ( this->nanos_ >= that.nanos_ ) return 1;
} }
return 0; return 0;
} }
/// Determines if two TimeValue objects represent the same moment in ti me. /// Determines if two TimeValue objects represent the same moment in ti me.
/// @brief True iff *this == that. /// @returns True iff *this == that.
/// @brief True if this == that.
int operator == (const TimeValue &that) const { int operator == (const TimeValue &that) const {
return (this->seconds_ == that.seconds_) && return (this->seconds_ == that.seconds_) &&
(this->nanos_ == that.nanos_); (this->nanos_ == that.nanos_);
} }
/// Determines if two TimeValue objects represent times that are not th e /// Determines if two TimeValue objects represent times that are not th e
/// same. /// same.
/// @return True iff *this != that. /// @returns True iff *this != that.
/// @brief True if this != that.
int operator != (const TimeValue &that) const { return !(*this == that) ; } int operator != (const TimeValue &that) const { return !(*this == that) ; }
/// Adds two TimeValue objects together. /// Adds two TimeValue objects together.
/// @returns The sum of the two operands as a new TimeValue /// @returns The sum of the two operands as a new TimeValue
/// @brief Addition operator. /// @brief Addition operator.
friend TimeValue operator + (const TimeValue &tv1, const TimeValue &tv2 ); friend TimeValue operator + (const TimeValue &tv1, const TimeValue &tv2 );
/// Subtracts two TimeValue objects. /// Subtracts two TimeValue objects.
/// @returns The difference of the two operands as a new TimeValue /// @returns The difference of the two operands as a new TimeValue
/// @brief Subtraction operator. /// @brief Subtraction operator.
 End of changes. 3 change blocks. 
5 lines changed or deleted 2 lines changed or added


 Timer.h   Timer.h 
skipping to change at line 18 skipping to change at line 18
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// //
// This file defines three classes: Timer, TimeRegion, and TimerGroup, // This file defines three classes: Timer, TimeRegion, and TimerGroup,
// documented below. // documented below.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_SUPPORT_TIMER_H #ifndef LLVM_SUPPORT_TIMER_H
#define LLVM_SUPPORT_TIMER_H #define LLVM_SUPPORT_TIMER_H
#include "llvm/Support/Compiler.h"
#include "llvm/Support/DataTypes.h" #include "llvm/Support/DataTypes.h"
#include "llvm/ADT/StringRef.h" #include "llvm/ADT/StringRef.h"
#include <cassert> #include <cassert>
#include <string> #include <string>
#include <vector> #include <vector>
#include <utility> #include <utility>
namespace llvm { namespace llvm {
class Timer; class Timer;
skipping to change at line 131 skipping to change at line 132
friend class TimerGroup; friend class TimerGroup;
}; };
/// The TimeRegion class is used as a helper class to call the startTimer() and /// The TimeRegion class is used as a helper class to call the startTimer() and
/// stopTimer() methods of the Timer class. When the object is constructed , it /// stopTimer() methods of the Timer class. When the object is constructed , it
/// starts the timer specified as it's argument. When it is destroyed, it stops /// starts the timer specified as it's argument. When it is destroyed, it stops
/// the relevant timer. This makes it easy to time a region of code. /// the relevant timer. This makes it easy to time a region of code.
/// ///
class TimeRegion { class TimeRegion {
Timer *T; Timer *T;
TimeRegion(const TimeRegion &); // DO NOT IMPLEMENT TimeRegion(const TimeRegion &) LLVM_DELETED_FUNCTION;
public: public:
explicit TimeRegion(Timer &t) : T(&t) { explicit TimeRegion(Timer &t) : T(&t) {
T->startTimer(); T->startTimer();
} }
explicit TimeRegion(Timer *t) : T(t) { explicit TimeRegion(Timer *t) : T(t) {
if (T) T->startTimer(); if (T) T->startTimer();
} }
~TimeRegion() { ~TimeRegion() {
if (T) T->stopTimer(); if (T) T->stopTimer();
} }
skipping to change at line 167 skipping to change at line 168
/// report that is printed when the TimerGroup is destroyed. It is illegal to /// report that is printed when the TimerGroup is destroyed. It is illegal to
/// destroy a TimerGroup object before all of the Timers in it are gone. A /// destroy a TimerGroup object before all of the Timers in it are gone. A
/// TimerGroup can be specified for a newly created timer in its constructo r. /// TimerGroup can be specified for a newly created timer in its constructo r.
/// ///
class TimerGroup { class TimerGroup {
std::string Name; std::string Name;
Timer *FirstTimer; // First timer in the group. Timer *FirstTimer; // First timer in the group.
std::vector<std::pair<TimeRecord, std::string> > TimersToPrint; std::vector<std::pair<TimeRecord, std::string> > TimersToPrint;
TimerGroup **Prev, *Next; // Doubly linked list of TimerGroup's. TimerGroup **Prev, *Next; // Doubly linked list of TimerGroup's.
TimerGroup(const TimerGroup &TG); // DO NOT IMPLEMENT TimerGroup(const TimerGroup &TG) LLVM_DELETED_FUNCTION;
void operator=(const TimerGroup &TG); // DO NOT IMPLEMENT void operator=(const TimerGroup &TG) LLVM_DELETED_FUNCTION;
public: public:
explicit TimerGroup(StringRef name); explicit TimerGroup(StringRef name);
~TimerGroup(); ~TimerGroup();
void setName(StringRef name) { Name.assign(name.begin(), name.end()); } void setName(StringRef name) { Name.assign(name.begin(), name.end()); }
/// print - Print any started timers in this group and zero them. /// print - Print any started timers in this group and zero them.
void print(raw_ostream &OS); void print(raw_ostream &OS);
/// printAll - This static method prints all timers and clears them all o ut. /// printAll - This static method prints all timers and clears them all o ut.
 End of changes. 3 change blocks. 
3 lines changed or deleted 4 lines changed or added


 TinyPtrVector.h   TinyPtrVector.h 
skipping to change at line 13 skipping to change at line 13
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
// //
// This file is distributed under the University of Illinois Open Source // This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details. // License. See LICENSE.TXT for details.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_ADT_TINYPTRVECTOR_H #ifndef LLVM_ADT_TINYPTRVECTOR_H
#define LLVM_ADT_TINYPTRVECTOR_H #define LLVM_ADT_TINYPTRVECTOR_H
#include "llvm/ADT/SmallVector.h" #include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/PointerUnion.h" #include "llvm/ADT/PointerUnion.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/Support/Compiler.h"
namespace llvm { namespace llvm {
/// TinyPtrVector - This class is specialized for cases where there are /// TinyPtrVector - This class is specialized for cases where there are
/// normally 0 or 1 element in a vector, but is general enough to go beyond that /// normally 0 or 1 element in a vector, but is general enough to go beyond that
/// when required. /// when required.
/// ///
/// NOTE: This container doesn't allow you to store a null pointer into it. /// NOTE: This container doesn't allow you to store a null pointer into it.
/// ///
template <typename EltTy> template <typename EltTy>
class TinyPtrVector { class TinyPtrVector {
public: public:
typedef llvm::SmallVector<EltTy, 4> VecTy; typedef llvm::SmallVector<EltTy, 4> VecTy;
typedef typename VecTy::value_type value_type;
llvm::PointerUnion<EltTy, VecTy*> Val; llvm::PointerUnion<EltTy, VecTy*> Val;
TinyPtrVector() {} TinyPtrVector() {}
~TinyPtrVector() {
if (VecTy *V = Val.template dyn_cast<VecTy*>())
delete V;
}
TinyPtrVector(const TinyPtrVector &RHS) : Val(RHS.Val) { TinyPtrVector(const TinyPtrVector &RHS) : Val(RHS.Val) {
if (VecTy *V = Val.template dyn_cast<VecTy*>()) if (VecTy *V = Val.template dyn_cast<VecTy*>())
Val = new VecTy(*V); Val = new VecTy(*V);
} }
~TinyPtrVector() { TinyPtrVector &operator=(const TinyPtrVector &RHS) {
if (VecTy *V = Val.template dyn_cast<VecTy*>()) if (this == &RHS)
return *this;
if (RHS.empty()) {
this->clear();
return *this;
}
// Try to squeeze into the single slot. If it won't fit, allocate a cop
ied
// vector.
if (Val.template is<EltTy>()) {
if (RHS.size() == 1)
Val = RHS.front();
else
Val = new VecTy(*RHS.Val.template get<VecTy*>());
return *this;
}
// If we have a full vector allocated, try to re-use it.
if (RHS.Val.template is<EltTy>()) {
Val.template get<VecTy*>()->clear();
Val.template get<VecTy*>()->push_back(RHS.front());
} else {
*Val.template get<VecTy*>() = *RHS.Val.template get<VecTy*>();
}
return *this;
}
#if LLVM_USE_RVALUE_REFERENCES
TinyPtrVector(TinyPtrVector &&RHS) : Val(RHS.Val) {
RHS.Val = (EltTy)0;
}
TinyPtrVector &operator=(TinyPtrVector &&RHS) {
if (this == &RHS)
return *this;
if (RHS.empty()) {
this->clear();
return *this;
}
// If this vector has been allocated on the heap, re-use it if cheap. I
f it
// would require more copying, just delete it and we'll steal the other
// side.
if (VecTy *V = Val.template dyn_cast<VecTy*>()) {
if (RHS.Val.template is<EltTy>()) {
V->clear();
V->push_back(RHS.front());
return *this;
}
delete V; delete V;
}
Val = RHS.Val;
RHS.Val = (EltTy)0;
return *this;
} }
#endif
// implicit conversion operator to ArrayRef. // implicit conversion operator to ArrayRef.
operator ArrayRef<EltTy>() const { operator ArrayRef<EltTy>() const {
if (Val.isNull()) if (Val.isNull())
return ArrayRef<EltTy>(); return ArrayRef<EltTy>();
if (Val.template is<EltTy>()) if (Val.template is<EltTy>())
return *Val.getAddrOfPtr1(); return *Val.getAddrOfPtr1();
return *Val.template get<VecTy*>(); return *Val.template get<VecTy*>();
} }
skipping to change at line 70 skipping to change at line 133
return 0; return 0;
if (Val.template is<EltTy>()) if (Val.template is<EltTy>())
return 1; return 1;
return Val.template get<VecTy*>()->size(); return Val.template get<VecTy*>()->size();
} }
typedef const EltTy *const_iterator; typedef const EltTy *const_iterator;
typedef EltTy *iterator; typedef EltTy *iterator;
iterator begin() { iterator begin() {
if (empty())
return 0;
if (Val.template is<EltTy>()) if (Val.template is<EltTy>())
return Val.getAddrOfPtr1(); return Val.getAddrOfPtr1();
return Val.template get<VecTy *>()->begin(); return Val.template get<VecTy *>()->begin();
} }
iterator end() { iterator end() {
if (empty())
return 0;
if (Val.template is<EltTy>()) if (Val.template is<EltTy>())
return begin() + 1; return begin() + (Val.isNull() ? 0 : 1);
return Val.template get<VecTy *>()->end(); return Val.template get<VecTy *>()->end();
} }
const_iterator begin() const { const_iterator begin() const {
return (const_iterator)const_cast<TinyPtrVector*>(this)->begin(); return (const_iterator)const_cast<TinyPtrVector*>(this)->begin();
} }
const_iterator end() const { const_iterator end() const {
return (const_iterator)const_cast<TinyPtrVector*>(this)->end(); return (const_iterator)const_cast<TinyPtrVector*>(this)->end();
skipping to change at line 116 skipping to change at line 173
return (*Val.template get<VecTy*>())[i]; return (*Val.template get<VecTy*>())[i];
} }
EltTy front() const { EltTy front() const {
assert(!empty() && "vector empty"); assert(!empty() && "vector empty");
if (EltTy V = Val.template dyn_cast<EltTy>()) if (EltTy V = Val.template dyn_cast<EltTy>())
return V; return V;
return Val.template get<VecTy*>()->front(); return Val.template get<VecTy*>()->front();
} }
EltTy back() const {
assert(!empty() && "vector empty");
if (EltTy V = Val.template dyn_cast<EltTy>())
return V;
return Val.template get<VecTy*>()->back();
}
void push_back(EltTy NewVal) { void push_back(EltTy NewVal) {
assert(NewVal != 0 && "Can't add a null value"); assert(NewVal != 0 && "Can't add a null value");
// If we have nothing, add something. // If we have nothing, add something.
if (Val.isNull()) { if (Val.isNull()) {
Val = NewVal; Val = NewVal;
return; return;
} }
// If we have a single value, convert to a vector. // If we have a single value, convert to a vector.
if (EltTy V = Val.template dyn_cast<EltTy>()) { if (EltTy V = Val.template dyn_cast<EltTy>()) {
Val = new VecTy(); Val = new VecTy();
Val.template get<VecTy*>()->push_back(V); Val.template get<VecTy*>()->push_back(V);
} }
// Add the new value, we know we have a vector. // Add the new value, we know we have a vector.
Val.template get<VecTy*>()->push_back(NewVal); Val.template get<VecTy*>()->push_back(NewVal);
} }
void pop_back() {
// If we have a single value, convert to empty.
if (Val.template is<EltTy>())
Val = (EltTy)0;
else if (VecTy *Vec = Val.template get<VecTy*>())
Vec->pop_back();
}
void clear() { void clear() {
// If we have a single value, convert to empty. // If we have a single value, convert to empty.
if (Val.template is<EltTy>()) { if (Val.template is<EltTy>()) {
Val = (EltTy)0; Val = (EltTy)0;
} else if (VecTy *Vec = Val.template dyn_cast<VecTy*>()) { } else if (VecTy *Vec = Val.template dyn_cast<VecTy*>()) {
// If we have a vector form, just clear it. // If we have a vector form, just clear it.
Vec->clear(); Vec->clear();
} }
// Otherwise, we're already empty. // Otherwise, we're already empty.
} }
iterator erase(iterator I) { iterator erase(iterator I) {
assert(I >= begin() && "Iterator to erase is out of bounds.");
assert(I < end() && "Erasing at past-the-end iterator.");
// If we have a single value, convert to empty. // If we have a single value, convert to empty.
if (Val.template is<EltTy>()) { if (Val.template is<EltTy>()) {
if (I == begin()) if (I == begin())
Val = (EltTy)0; Val = (EltTy)0;
} else if (VecTy *Vec = Val.template dyn_cast<VecTy*>()) { } else if (VecTy *Vec = Val.template dyn_cast<VecTy*>()) {
// multiple items in a vector; just do the erase, there is no // multiple items in a vector; just do the erase, there is no
// benefit to collapsing back to a pointer // benefit to collapsing back to a pointer
return Vec->erase(I); return Vec->erase(I);
} }
return end();
}
iterator erase(iterator S, iterator E) {
assert(S >= begin() && "Range to erase is out of bounds.");
assert(S <= E && "Trying to erase invalid range.");
assert(E <= end() && "Trying to erase past the end.");
if (Val.template is<EltTy>()) {
if (S == begin() && S != E)
Val = (EltTy)0;
} else if (VecTy *Vec = Val.template dyn_cast<VecTy*>()) {
return Vec->erase(S, E);
}
return end();
}
iterator insert(iterator I, const EltTy &Elt) {
assert(I >= this->begin() && "Insertion iterator is out of bounds.");
assert(I <= this->end() && "Inserting past the end of the vector.");
if (I == end()) {
push_back(Elt);
return llvm::prior(end());
}
assert(!Val.isNull() && "Null value with non-end insert iterator.");
if (EltTy V = Val.template dyn_cast<EltTy>()) {
assert(I == begin());
Val = Elt;
push_back(V);
return begin();
}
return 0; return Val.template get<VecTy*>()->insert(I, Elt);
} }
private: template<typename ItTy>
void operator=(const TinyPtrVector&); // NOT IMPLEMENTED YET. iterator insert(iterator I, ItTy From, ItTy To) {
assert(I >= this->begin() && "Insertion iterator is out of bounds.");
assert(I <= this->end() && "Inserting past the end of the vector.");
if (From == To)
return I;
// If we have a single value, convert to a vector.
ptrdiff_t Offset = I - begin();
if (Val.isNull()) {
if (llvm::next(From) == To) {
Val = *From;
return begin();
}
Val = new VecTy();
} else if (EltTy V = Val.template dyn_cast<EltTy>()) {
Val = new VecTy();
Val.template get<VecTy*>()->push_back(V);
}
return Val.template get<VecTy*>()->insert(begin() + Offset, From, To);
}
}; };
} // end namespace llvm } // end namespace llvm
#endif #endif
 End of changes. 16 change blocks. 
13 lines changed or deleted 141 lines changed or added


 Triple.h   Triple.h 
skipping to change at line 65 skipping to change at line 65
ppc64, // PPC64: powerpc64, ppu ppc64, // PPC64: powerpc64, ppu
r600, // R600: AMD GPUs HD2XXX - HD6XXX r600, // R600: AMD GPUs HD2XXX - HD6XXX
sparc, // Sparc: sparc sparc, // Sparc: sparc
sparcv9, // Sparcv9: Sparcv9 sparcv9, // Sparcv9: Sparcv9
tce, // TCE (http://tce.cs.tut.fi/): tce tce, // TCE (http://tce.cs.tut.fi/): tce
thumb, // Thumb: thumb, thumbv.* thumb, // Thumb: thumb, thumbv.*
x86, // X86: i[3-9]86 x86, // X86: i[3-9]86
x86_64, // X86-64: amd64, x86_64 x86_64, // X86-64: amd64, x86_64
xcore, // XCore: xcore xcore, // XCore: xcore
mblaze, // MBlaze: mblaze mblaze, // MBlaze: mblaze
ptx32, // PTX: ptx (32-bit) nvptx, // NVPTX: 32-bit
ptx64, // PTX: ptx (64-bit) nvptx64, // NVPTX: 64-bit
le32, // le32: generic little-endian 32-bit CPU (PNaCl / Emscripten) le32, // le32: generic little-endian 32-bit CPU (PNaCl / Emscripten)
amdil // amdil: amd IL amdil, // amdil: amd IL
spir, // SPIR: standard portable IR for OpenCL 32-bit version
spir64 // SPIR: standard portable IR for OpenCL 64-bit version
}; };
enum VendorType { enum VendorType {
UnknownVendor, UnknownVendor,
Apple, Apple,
PC, PC,
SCEI, SCEI,
BGP, BGP,
BGQ BGQ,
Freescale,
IBM
}; };
enum OSType { enum OSType {
UnknownOS, UnknownOS,
AuroraUX, AuroraUX,
Cygwin, Cygwin,
Darwin, Darwin,
DragonFly, DragonFly,
FreeBSD, FreeBSD,
IOS, IOS,
skipping to change at line 101 skipping to change at line 105
MacOSX, MacOSX,
MinGW32, // i*86-pc-mingw32, *-w64-mingw32 MinGW32, // i*86-pc-mingw32, *-w64-mingw32
NetBSD, NetBSD,
OpenBSD, OpenBSD,
Solaris, Solaris,
Win32, Win32,
Haiku, Haiku,
Minix, Minix,
RTEMS, RTEMS,
NativeClient, NativeClient,
CNK // BG/P Compute-Node Kernel CNK, // BG/P Compute-Node Kernel
Bitrig,
AIX
}; };
enum EnvironmentType { enum EnvironmentType {
UnknownEnvironment, UnknownEnvironment,
GNU, GNU,
GNUEABI, GNUEABI,
GNUEABIHF, GNUEABIHF,
EABI, EABI,
MachO, MachO,
ANDROIDEABI Android,
ELF
}; };
private: private:
std::string Data; std::string Data;
/// The parsed arch type. /// The parsed arch type.
ArchType Arch; ArchType Arch;
/// The parsed vendor type. /// The parsed vendor type.
VendorType Vendor; VendorType Vendor;
skipping to change at line 197 skipping to change at line 204
return Maj; return Maj;
} }
/// getMacOSXVersion - Parse the version number as with getOSVersion and then /// getMacOSXVersion - Parse the version number as with getOSVersion and then
/// translate generic "darwin" versions to the corresponding OS X version s. /// translate generic "darwin" versions to the corresponding OS X version s.
/// This may also be called with IOS triples but the OS X version number is /// This may also be called with IOS triples but the OS X version number is
/// just set to a constant 10.4.0 in that case. Returns true if successf ul. /// just set to a constant 10.4.0 in that case. Returns true if successf ul.
bool getMacOSXVersion(unsigned &Major, unsigned &Minor, bool getMacOSXVersion(unsigned &Major, unsigned &Minor,
unsigned &Micro) const; unsigned &Micro) const;
/// getiOSVersion - Parse the version number as with getOSVersion. This
should
/// only be called with IOS triples.
void getiOSVersion(unsigned &Major, unsigned &Minor,
unsigned &Micro) const;
/// @} /// @}
/// @name Direct Component Access /// @name Direct Component Access
/// @{ /// @{
const std::string &str() const { return Data; } const std::string &str() const { return Data; }
const std::string &getTriple() const { return Data; } const std::string &getTriple() const { return Data; }
/// getArchName - Get the architecture (first) component of the /// getArchName - Get the architecture (first) component of the
/// triple. /// triple.
skipping to change at line 269 skipping to change at line 281
if (LHS[2] != Micro) if (LHS[2] != Micro)
return LHS[1] < Micro; return LHS[1] < Micro;
return false; return false;
} }
/// isMacOSXVersionLT - Comparison function for checking OS X version /// isMacOSXVersionLT - Comparison function for checking OS X version
/// compatibility, which handles supporting skewed version numbering sche mes /// compatibility, which handles supporting skewed version numbering sche mes
/// used by the "darwin" triples. /// used by the "darwin" triples.
unsigned isMacOSXVersionLT(unsigned Major, unsigned Minor = 0, unsigned isMacOSXVersionLT(unsigned Major, unsigned Minor = 0,
unsigned Micro = 0) const { unsigned Micro = 0) const {
assert(isMacOSX() && "Not an OS X triple!"); assert(isMacOSX() && "Not an OS X triple!");
// If this is OS X, expect a sane version number. // If this is OS X, expect a sane version number.
if (getOS() == Triple::MacOSX) if (getOS() == Triple::MacOSX)
return isOSVersionLT(Major, Minor, Micro); return isOSVersionLT(Major, Minor, Micro);
// Otherwise, compare to the "Darwin" number. // Otherwise, compare to the "Darwin" number.
assert(Major == 10 && "Unexpected major version"); assert(Major == 10 && "Unexpected major version");
return isOSVersionLT(Minor + 4, Micro, 0); return isOSVersionLT(Minor + 4, Micro, 0);
} }
skipping to change at line 338 skipping to change at line 350
void setVendor(VendorType Kind); void setVendor(VendorType Kind);
/// setOS - Set the operating system (third) component of the triple /// setOS - Set the operating system (third) component of the triple
/// to a known type. /// to a known type.
void setOS(OSType Kind); void setOS(OSType Kind);
/// setEnvironment - Set the environment (fourth) component of the triple /// setEnvironment - Set the environment (fourth) component of the triple
/// to a known type. /// to a known type.
void setEnvironment(EnvironmentType Kind); void setEnvironment(EnvironmentType Kind);
/// setTriple - Set all components to the new triple \arg Str. /// setTriple - Set all components to the new triple \p Str.
void setTriple(const Twine &Str); void setTriple(const Twine &Str);
/// setArchName - Set the architecture (first) component of the /// setArchName - Set the architecture (first) component of the
/// triple by name. /// triple by name.
void setArchName(StringRef Str); void setArchName(StringRef Str);
/// setVendorName - Set the vendor (second) component of the triple /// setVendorName - Set the vendor (second) component of the triple
/// by name. /// by name.
void setVendorName(StringRef Str); void setVendorName(StringRef Str);
skipping to change at line 389 skipping to change at line 401
/// This can be used to move across "families" of architectures where use ful. /// This can be used to move across "families" of architectures where use ful.
/// ///
/// \returns A new triple with a 64-bit architecture or an unknown /// \returns A new triple with a 64-bit architecture or an unknown
/// architecture if no such variant can be found. /// architecture if no such variant can be found.
llvm::Triple get64BitArchVariant() const; llvm::Triple get64BitArchVariant() const;
/// @} /// @}
/// @name Static helpers for IDs. /// @name Static helpers for IDs.
/// @{ /// @{
/// getArchTypeName - Get the canonical name for the \arg Kind /// getArchTypeName - Get the canonical name for the \p Kind architecture
/// architecture. .
static const char *getArchTypeName(ArchType Kind); static const char *getArchTypeName(ArchType Kind);
/// getArchTypePrefix - Get the "prefix" canonical name for the \arg Kind /// getArchTypePrefix - Get the "prefix" canonical name for the \p Kind
/// architecture. This is the prefix used by the architecture specific /// architecture. This is the prefix used by the architecture specific
/// builtins, and is suitable for passing to \see /// builtins, and is suitable for passing to \see
/// Intrinsic::getIntrinsicForGCCBuiltin(). /// Intrinsic::getIntrinsicForGCCBuiltin().
/// ///
/// \return - The architecture prefix, or 0 if none is defined. /// \return - The architecture prefix, or 0 if none is defined.
static const char *getArchTypePrefix(ArchType Kind); static const char *getArchTypePrefix(ArchType Kind);
/// getVendorTypeName - Get the canonical name for the \arg Kind /// getVendorTypeName - Get the canonical name for the \p Kind vendor.
/// vendor.
static const char *getVendorTypeName(VendorType Kind); static const char *getVendorTypeName(VendorType Kind);
/// getOSTypeName - Get the canonical name for the \arg Kind operating /// getOSTypeName - Get the canonical name for the \p Kind operating syst
/// system. em.
static const char *getOSTypeName(OSType Kind); static const char *getOSTypeName(OSType Kind);
/// getEnvironmentTypeName - Get the canonical name for the \arg Kind /// getEnvironmentTypeName - Get the canonical name for the \p Kind
/// environment. /// environment.
static const char *getEnvironmentTypeName(EnvironmentType Kind); static const char *getEnvironmentTypeName(EnvironmentType Kind);
/// @} /// @}
/// @name Static helpers for converting alternate architecture names. /// @name Static helpers for converting alternate architecture names.
/// @{ /// @{
/// getArchTypeForLLVMName - The canonical type for the given LLVM /// getArchTypeForLLVMName - The canonical type for the given LLVM
/// architecture name (e.g., "x86"). /// architecture name (e.g., "x86").
static ArchType getArchTypeForLLVMName(StringRef Str); static ArchType getArchTypeForLLVMName(StringRef Str);
/// getArchTypeForDarwinArchName - Get the architecture type for a "Darwi
n"
/// architecture name, for example as accepted by "gcc -arch" (see also
/// arch(3)).
static ArchType getArchTypeForDarwinArchName(StringRef Str);
/// @} /// @}
}; };
} // End llvm namespace } // End llvm namespace
#endif #endif
 End of changes. 14 change blocks. 
22 lines changed or deleted 28 lines changed or added


 Twine.h   Twine.h 
skipping to change at line 47 skipping to change at line 47
/// A Twine is not intended for use directly and should not be stored, it s /// A Twine is not intended for use directly and should not be stored, it s
/// implementation relies on the ability to store pointers to temporary s tack /// implementation relies on the ability to store pointers to temporary s tack
/// objects which may be deallocated at the end of a statement. Twines sh ould /// objects which may be deallocated at the end of a statement. Twines sh ould
/// only be used accepted as const references in arguments, when an API w ishes /// only be used accepted as const references in arguments, when an API w ishes
/// to accept possibly-concatenated strings. /// to accept possibly-concatenated strings.
/// ///
/// Twines support a special 'null' value, which always concatenates to f orm /// Twines support a special 'null' value, which always concatenates to f orm
/// itself, and renders as an empty string. This can be returned from API s to /// itself, and renders as an empty string. This can be returned from API s to
/// effectively nullify any concatenations performed on the result. /// effectively nullify any concatenations performed on the result.
/// ///
/// \b Implementation \n /// \b Implementation
/// ///
/// Given the nature of a Twine, it is not possible for the Twine's /// Given the nature of a Twine, it is not possible for the Twine's
/// concatenation method to construct interior nodes; the result must be /// concatenation method to construct interior nodes; the result must be
/// represented inside the returned value. For this reason a Twine object /// represented inside the returned value. For this reason a Twine object
/// actually holds two values, the left- and right-hand sides of a /// actually holds two values, the left- and right-hand sides of a
/// concatenation. We also have nullary Twine objects, which are effectiv ely /// concatenation. We also have nullary Twine objects, which are effectiv ely
/// sentinel values that represent empty strings. /// sentinel values that represent empty strings.
/// ///
/// Thus, a Twine can effectively have zero, one, or two children. The \s ee /// Thus, a Twine can effectively have zero, one, or two children. The \s ee
/// isNullary(), \see isUnary(), and \see isBinary() predicates exist for /// isNullary(), \see isUnary(), and \see isBinary() predicates exist for
skipping to change at line 70 skipping to change at line 70
/// We maintain a number of invariants on Twine objects (FIXME: Why): /// We maintain a number of invariants on Twine objects (FIXME: Why):
/// - Nullary twines are always represented with their Kind on the left- hand /// - Nullary twines are always represented with their Kind on the left- hand
/// side, and the Empty kind on the right-hand side. /// side, and the Empty kind on the right-hand side.
/// - Unary twines are always represented with the value on the left-han d /// - Unary twines are always represented with the value on the left-han d
/// side, and the Empty kind on the right-hand side. /// side, and the Empty kind on the right-hand side.
/// - If a Twine has another Twine as a child, that child should always be /// - If a Twine has another Twine as a child, that child should always be
/// binary (otherwise it could have been folded into the parent). /// binary (otherwise it could have been folded into the parent).
/// ///
/// These invariants are check by \see isValid(). /// These invariants are check by \see isValid().
/// ///
/// \b Efficiency Considerations \n /// \b Efficiency Considerations
/// ///
/// The Twine is designed to yield efficient and small code for common /// The Twine is designed to yield efficient and small code for common
/// situations. For this reason, the concat() method is inlined so that /// situations. For this reason, the concat() method is inlined so that
/// concatenations of leaf nodes can be optimized into stores directly in to a /// concatenations of leaf nodes can be optimized into stores directly in to a
/// single stack allocated object. /// single stack allocated object.
/// ///
/// In practice, not all compilers can be trusted to optimize concat() fu lly, /// In practice, not all compilers can be trusted to optimize concat() fu lly,
/// so we provide two additional methods (and accompanying operator+ /// so we provide two additional methods (and accompanying operator+
/// overloads) to guarantee that particularly important cases (cstring pl us /// overloads) to guarantee that particularly important cases (cstring pl us
/// StringRef) codegen as desired. /// StringRef) codegen as desired.
skipping to change at line 306 skipping to change at line 306
: LHSKind(CharKind), RHSKind(EmptyKind) { : LHSKind(CharKind), RHSKind(EmptyKind) {
LHS.character = static_cast<char>(Val); LHS.character = static_cast<char>(Val);
} }
/// Construct from an unsigned char. /// Construct from an unsigned char.
explicit Twine(unsigned char Val) explicit Twine(unsigned char Val)
: LHSKind(CharKind), RHSKind(EmptyKind) { : LHSKind(CharKind), RHSKind(EmptyKind) {
LHS.character = static_cast<char>(Val); LHS.character = static_cast<char>(Val);
} }
/// Construct a twine to print \arg Val as an unsigned decimal integer. /// Construct a twine to print \p Val as an unsigned decimal integer.
explicit Twine(unsigned Val) explicit Twine(unsigned Val)
: LHSKind(DecUIKind), RHSKind(EmptyKind) { : LHSKind(DecUIKind), RHSKind(EmptyKind) {
LHS.decUI = Val; LHS.decUI = Val;
} }
/// Construct a twine to print \arg Val as a signed decimal integer. /// Construct a twine to print \p Val as a signed decimal integer.
explicit Twine(int Val) explicit Twine(int Val)
: LHSKind(DecIKind), RHSKind(EmptyKind) { : LHSKind(DecIKind), RHSKind(EmptyKind) {
LHS.decI = Val; LHS.decI = Val;
} }
/// Construct a twine to print \arg Val as an unsigned decimal integer. /// Construct a twine to print \p Val as an unsigned decimal integer.
explicit Twine(const unsigned long &Val) explicit Twine(const unsigned long &Val)
: LHSKind(DecULKind), RHSKind(EmptyKind) { : LHSKind(DecULKind), RHSKind(EmptyKind) {
LHS.decUL = &Val; LHS.decUL = &Val;
} }
/// Construct a twine to print \arg Val as a signed decimal integer. /// Construct a twine to print \p Val as a signed decimal integer.
explicit Twine(const long &Val) explicit Twine(const long &Val)
: LHSKind(DecLKind), RHSKind(EmptyKind) { : LHSKind(DecLKind), RHSKind(EmptyKind) {
LHS.decL = &Val; LHS.decL = &Val;
} }
/// Construct a twine to print \arg Val as an unsigned decimal integer. /// Construct a twine to print \p Val as an unsigned decimal integer.
explicit Twine(const unsigned long long &Val) explicit Twine(const unsigned long long &Val)
: LHSKind(DecULLKind), RHSKind(EmptyKind) { : LHSKind(DecULLKind), RHSKind(EmptyKind) {
LHS.decULL = &Val; LHS.decULL = &Val;
} }
/// Construct a twine to print \arg Val as a signed decimal integer. /// Construct a twine to print \p Val as a signed decimal integer.
explicit Twine(const long long &Val) explicit Twine(const long long &Val)
: LHSKind(DecLLKind), RHSKind(EmptyKind) { : LHSKind(DecLLKind), RHSKind(EmptyKind) {
LHS.decLL = &Val; LHS.decLL = &Val;
} }
// FIXME: Unfortunately, to make sure this is as efficient as possible we // FIXME: Unfortunately, to make sure this is as efficient as possible we
// need extra binary constructors from particular types. We can't rely on // need extra binary constructors from particular types. We can't rely on
// the compiler to be smart enough to fold operator+()/concat() down to the // the compiler to be smart enough to fold operator+()/concat() down to the
// right thing. Yet. // right thing. Yet.
skipping to change at line 373 skipping to change at line 373
/// Create a 'null' string, which is an empty string that always /// Create a 'null' string, which is an empty string that always
/// concatenates to form another empty string. /// concatenates to form another empty string.
static Twine createNull() { static Twine createNull() {
return Twine(NullKind); return Twine(NullKind);
} }
/// @} /// @}
/// @name Numeric Conversions /// @name Numeric Conversions
/// @{ /// @{
// Construct a twine to print \arg Val as an unsigned hexadecimal integ er. // Construct a twine to print \p Val as an unsigned hexadecimal integer .
static Twine utohexstr(const uint64_t &Val) { static Twine utohexstr(const uint64_t &Val) {
Child LHS, RHS; Child LHS, RHS;
LHS.uHex = &Val; LHS.uHex = &Val;
RHS.twine = 0; RHS.twine = 0;
return Twine(LHS, UHexKind, RHS, EmptyKind); return Twine(LHS, UHexKind, RHS, EmptyKind);
} }
/// @} /// @}
/// @name Predicate Operations /// @name Predicate Operations
/// @{ /// @{
skipping to change at line 450 skipping to change at line 450
StringRef toStringRef(SmallVectorImpl<char> &Out) const; StringRef toStringRef(SmallVectorImpl<char> &Out) const;
/// toNullTerminatedStringRef - This returns the twine as a single null /// toNullTerminatedStringRef - This returns the twine as a single null
/// terminated StringRef if it can be represented as such. Otherwise th e /// terminated StringRef if it can be represented as such. Otherwise th e
/// twine is written into the given SmallVector and a StringRef to the /// twine is written into the given SmallVector and a StringRef to the
/// SmallVector's data is returned. /// SmallVector's data is returned.
/// ///
/// The returned StringRef's size does not include the null terminator. /// The returned StringRef's size does not include the null terminator.
StringRef toNullTerminatedStringRef(SmallVectorImpl<char> &Out) const; StringRef toNullTerminatedStringRef(SmallVectorImpl<char> &Out) const;
/// print - Write the concatenated string represented by this twine to /// Write the concatenated string represented by this twine to the
the /// stream \p OS.
/// stream \arg OS.
void print(raw_ostream &OS) const; void print(raw_ostream &OS) const;
/// dump - Dump the concatenated string represented by this twine to st derr. /// Dump the concatenated string represented by this twine to stderr.
void dump() const; void dump() const;
/// print - Write the representation of this twine to the stream \arg O S. /// Write the representation of this twine to the stream \p OS.
void printRepr(raw_ostream &OS) const; void printRepr(raw_ostream &OS) const;
/// dumpRepr - Dump the representation of this twine to stderr. /// Dump the representation of this twine to stderr.
void dumpRepr() const; void dumpRepr() const;
/// @} /// @}
}; };
/// @name Twine Inline Implementations /// @name Twine Inline Implementations
/// @{ /// @{
inline Twine Twine::concat(const Twine &Suffix) const { inline Twine Twine::concat(const Twine &Suffix) const {
// Concatenation with null is null. // Concatenation with null is null.
 End of changes. 13 change blocks. 
15 lines changed or deleted 14 lines changed or added


 Type.h   Type.h 
skipping to change at line 156 skipping to change at line 156
/// isX86_FP80Ty - Return true if this is x86 long double. /// isX86_FP80Ty - Return true if this is x86 long double.
bool isX86_FP80Ty() const { return getTypeID() == X86_FP80TyID; } bool isX86_FP80Ty() const { return getTypeID() == X86_FP80TyID; }
/// isFP128Ty - Return true if this is 'fp128'. /// isFP128Ty - Return true if this is 'fp128'.
bool isFP128Ty() const { return getTypeID() == FP128TyID; } bool isFP128Ty() const { return getTypeID() == FP128TyID; }
/// isPPC_FP128Ty - Return true if this is powerpc long double. /// isPPC_FP128Ty - Return true if this is powerpc long double.
bool isPPC_FP128Ty() const { return getTypeID() == PPC_FP128TyID; } bool isPPC_FP128Ty() const { return getTypeID() == PPC_FP128TyID; }
/// isFloatingPointTy - Return true if this is one of the five floating p oint /// isFloatingPointTy - Return true if this is one of the six floating po int
/// types /// types
bool isFloatingPointTy() const { bool isFloatingPointTy() const {
return getTypeID() == HalfTyID || getTypeID() == FloatTyID || return getTypeID() == HalfTyID || getTypeID() == FloatTyID ||
getTypeID() == DoubleTyID || getTypeID() == DoubleTyID ||
getTypeID() == X86_FP80TyID || getTypeID() == FP128TyID || getTypeID() == X86_FP80TyID || getTypeID() == FP128TyID ||
getTypeID() == PPC_FP128TyID; getTypeID() == PPC_FP128TyID;
} }
/// isX86_MMXTy - Return true if this is X86 MMX. /// isX86_MMXTy - Return true if this is X86 MMX.
bool isX86_MMXTy() const { return getTypeID() == X86_MMXTyID; } bool isX86_MMXTy() const { return getTypeID() == X86_MMXTyID; }
/// isFPOrFPVectorTy - Return true if this is a FP type or a vector of FP . /// isFPOrFPVectorTy - Return true if this is a FP type or a vector of FP .
/// ///
bool isFPOrFPVectorTy() const; bool isFPOrFPVectorTy() const { return getScalarType()->isFloatingPointTy (); }
/// isLabelTy - Return true if this is 'label'. /// isLabelTy - Return true if this is 'label'.
bool isLabelTy() const { return getTypeID() == LabelTyID; } bool isLabelTy() const { return getTypeID() == LabelTyID; }
/// isMetadataTy - Return true if this is 'metadata'. /// isMetadataTy - Return true if this is 'metadata'.
bool isMetadataTy() const { return getTypeID() == MetadataTyID; } bool isMetadataTy() const { return getTypeID() == MetadataTyID; }
/// isIntegerTy - True if this is an instance of IntegerType. /// isIntegerTy - True if this is an instance of IntegerType.
/// ///
bool isIntegerTy() const { return getTypeID() == IntegerTyID; } bool isIntegerTy() const { return getTypeID() == IntegerTyID; }
/// isIntegerTy - Return true if this is an IntegerType of the given widt h. /// isIntegerTy - Return true if this is an IntegerType of the given widt h.
bool isIntegerTy(unsigned Bitwidth) const; bool isIntegerTy(unsigned Bitwidth) const;
/// isIntOrIntVectorTy - Return true if this is an integer type or a vect or of /// isIntOrIntVectorTy - Return true if this is an integer type or a vect or of
/// integer types. /// integer types.
/// ///
bool isIntOrIntVectorTy() const; bool isIntOrIntVectorTy() const { return getScalarType()->isIntegerTy(); }
/// isFunctionTy - True if this is an instance of FunctionType. /// isFunctionTy - True if this is an instance of FunctionType.
/// ///
bool isFunctionTy() const { return getTypeID() == FunctionTyID; } bool isFunctionTy() const { return getTypeID() == FunctionTyID; }
/// isStructTy - True if this is an instance of StructType. /// isStructTy - True if this is an instance of StructType.
/// ///
bool isStructTy() const { return getTypeID() == StructTyID; } bool isStructTy() const { return getTypeID() == StructTyID; }
/// isArrayTy - True if this is an instance of ArrayType. /// isArrayTy - True if this is an instance of ArrayType.
/// ///
bool isArrayTy() const { return getTypeID() == ArrayTyID; } bool isArrayTy() const { return getTypeID() == ArrayTyID; }
/// isPointerTy - True if this is an instance of PointerType. /// isPointerTy - True if this is an instance of PointerType.
/// ///
bool isPointerTy() const { return getTypeID() == PointerTyID; } bool isPointerTy() const { return getTypeID() == PointerTyID; }
/// isPtrOrPtrVectorTy - Return true if this is a pointer type or a vecto
r of
/// pointer types.
///
bool isPtrOrPtrVectorTy() const { return getScalarType()->isPointerTy();
}
/// isVectorTy - True if this is an instance of VectorType. /// isVectorTy - True if this is an instance of VectorType.
/// ///
bool isVectorTy() const { return getTypeID() == VectorTyID; } bool isVectorTy() const { return getTypeID() == VectorTyID; }
/// canLosslesslyBitCastTo - Return true if this type could be converted /// canLosslesslyBitCastTo - Return true if this type could be converted
/// with a lossless BitCast to type 'Ty'. For example, i8* to i32*. BitCa sts /// with a lossless BitCast to type 'Ty'. For example, i8* to i32*. BitCa sts
/// are valid for types of the same size only where no re-interpretation of /// are valid for types of the same size only where no re-interpretation of
/// the bits is done. /// the bits is done.
/// @brief Determine if this type could be losslessly bitcast to Ty /// @brief Determine if this type could be losslessly bitcast to Ty
bool canLosslesslyBitCastTo(Type *Ty) const; bool canLosslesslyBitCastTo(Type *Ty) const;
skipping to change at line 255 skipping to change at line 260
/// means it is valid as the first operand of an insertvalue or /// means it is valid as the first operand of an insertvalue or
/// extractvalue instruction. This includes struct and array types, but /// extractvalue instruction. This includes struct and array types, but
/// does not include vector types. /// does not include vector types.
/// ///
bool isAggregateType() const { bool isAggregateType() const {
return getTypeID() == StructTyID || getTypeID() == ArrayTyID; return getTypeID() == StructTyID || getTypeID() == ArrayTyID;
} }
/// isSized - Return true if it makes sense to take the size of this type . To /// isSized - Return true if it makes sense to take the size of this type . To
/// get the actual size for a particular target, it is reasonable to use the /// get the actual size for a particular target, it is reasonable to use the
/// TargetData subsystem to do this. /// DataLayout subsystem to do this.
/// ///
bool isSized() const { bool isSized() const {
// If it's a primitive, it is always sized. // If it's a primitive, it is always sized.
if (getTypeID() == IntegerTyID || isFloatingPointTy() || if (getTypeID() == IntegerTyID || isFloatingPointTy() ||
getTypeID() == PointerTyID || getTypeID() == PointerTyID ||
getTypeID() == X86_MMXTyID) getTypeID() == X86_MMXTyID)
return true; return true;
// If it is not something that can have a size (e.g. a function or labe l), // If it is not something that can have a size (e.g. a function or labe l),
// it doesn't have a size. // it doesn't have a size.
if (getTypeID() != StructTyID && getTypeID() != ArrayTyID && if (getTypeID() != StructTyID && getTypeID() != ArrayTyID &&
skipping to change at line 279 skipping to change at line 284
return isSizedDerivedType(); return isSizedDerivedType();
} }
/// getPrimitiveSizeInBits - Return the basic size of this type if it is a /// getPrimitiveSizeInBits - Return the basic size of this type if it is a
/// primitive type. These are fixed by LLVM and are not target dependent . /// primitive type. These are fixed by LLVM and are not target dependent .
/// This will return zero if the type does not have a size or is not a /// This will return zero if the type does not have a size or is not a
/// primitive type. /// primitive type.
/// ///
/// Note that this may not reflect the size of memory allocated for an /// Note that this may not reflect the size of memory allocated for an
/// instance of the type or the number of bytes that are written when an /// instance of the type or the number of bytes that are written when an
/// instance of the type is stored to memory. The TargetData class provid es /// instance of the type is stored to memory. The DataLayout class provid es
/// additional query functions to provide this information. /// additional query functions to provide this information.
/// ///
unsigned getPrimitiveSizeInBits() const; unsigned getPrimitiveSizeInBits() const;
/// getScalarSizeInBits - If this is a vector type, return the /// getScalarSizeInBits - If this is a vector type, return the
/// getPrimitiveSizeInBits value for the element type. Otherwise return t he /// getPrimitiveSizeInBits value for the element type. Otherwise return t he
/// getPrimitiveSizeInBits value for this type. /// getPrimitiveSizeInBits value for this type.
unsigned getScalarSizeInBits(); unsigned getScalarSizeInBits();
/// getFPMantissaWidth - Return the width of the mantissa of this type. This /// getFPMantissaWidth - Return the width of the mantissa of this type. This
/// is only valid on floating point types. If the FP type does not /// is only valid on floating point types. If the FP type does not
/// have a stable mantissa (e.g. ppc long double), this method returns -1 . /// have a stable mantissa (e.g. ppc long double), this method returns -1 .
int getFPMantissaWidth() const; int getFPMantissaWidth() const;
/// getScalarType - If this is a vector type, return the element type, /// getScalarType - If this is a vector type, return the element type,
/// otherwise return 'this'. /// otherwise return 'this'.
const Type *getScalarType() const;
Type *getScalarType(); Type *getScalarType();
//===-------------------------------------------------------------------- ===// //===-------------------------------------------------------------------- ===//
// Type Iteration support. // Type Iteration support.
// //
typedef Type * const *subtype_iterator; typedef Type * const *subtype_iterator;
subtype_iterator subtype_begin() const { return ContainedTys; } subtype_iterator subtype_begin() const { return ContainedTys; }
subtype_iterator subtype_end() const { return &ContainedTys[NumContainedT ys];} subtype_iterator subtype_end() const { return &ContainedTys[NumContainedT ys];}
/// getContainedType - This method is used to implement the type iterator /// getContainedType - This method is used to implement the type iterator
skipping to change at line 343 skipping to change at line 349
Type *getStructElementType(unsigned N) const; Type *getStructElementType(unsigned N) const;
Type *getSequentialElementType() const; Type *getSequentialElementType() const;
uint64_t getArrayNumElements() const; uint64_t getArrayNumElements() const;
Type *getArrayElementType() const { return getSequentialElementType(); } Type *getArrayElementType() const { return getSequentialElementType(); }
unsigned getVectorNumElements() const; unsigned getVectorNumElements() const;
Type *getVectorElementType() const { return getSequentialElementType(); } Type *getVectorElementType() const { return getSequentialElementType(); }
unsigned getPointerAddressSpace() const;
Type *getPointerElementType() const { return getSequentialElementType(); } Type *getPointerElementType() const { return getSequentialElementType(); }
/// \brief Get the address space of this pointer or pointer vector type.
unsigned getPointerAddressSpace() const;
//===-------------------------------------------------------------------- ===// //===-------------------------------------------------------------------- ===//
// Static members exported by the Type class itself. Useful for getting // Static members exported by the Type class itself. Useful for getting
// instances of Type. // instances of Type.
// //
/// getPrimitiveType - Return a type based on an identifier. /// getPrimitiveType - Return a type based on an identifier.
static Type *getPrimitiveType(LLVMContext &C, TypeID IDNumber); static Type *getPrimitiveType(LLVMContext &C, TypeID IDNumber);
//===-------------------------------------------------------------------- ===// //===-------------------------------------------------------------------- ===//
// These are the builtin types that are always available. // These are the builtin types that are always available.
skipping to change at line 392 skipping to change at line 400
static PointerType *getFP128PtrTy(LLVMContext &C, unsigned AS = 0); static PointerType *getFP128PtrTy(LLVMContext &C, unsigned AS = 0);
static PointerType *getPPC_FP128PtrTy(LLVMContext &C, unsigned AS = 0); static PointerType *getPPC_FP128PtrTy(LLVMContext &C, unsigned AS = 0);
static PointerType *getX86_MMXPtrTy(LLVMContext &C, unsigned AS = 0); static PointerType *getX86_MMXPtrTy(LLVMContext &C, unsigned AS = 0);
static PointerType *getIntNPtrTy(LLVMContext &C, unsigned N, unsigned AS = 0); static PointerType *getIntNPtrTy(LLVMContext &C, unsigned N, unsigned AS = 0);
static PointerType *getInt1PtrTy(LLVMContext &C, unsigned AS = 0); static PointerType *getInt1PtrTy(LLVMContext &C, unsigned AS = 0);
static PointerType *getInt8PtrTy(LLVMContext &C, unsigned AS = 0); static PointerType *getInt8PtrTy(LLVMContext &C, unsigned AS = 0);
static PointerType *getInt16PtrTy(LLVMContext &C, unsigned AS = 0); static PointerType *getInt16PtrTy(LLVMContext &C, unsigned AS = 0);
static PointerType *getInt32PtrTy(LLVMContext &C, unsigned AS = 0); static PointerType *getInt32PtrTy(LLVMContext &C, unsigned AS = 0);
static PointerType *getInt64PtrTy(LLVMContext &C, unsigned AS = 0); static PointerType *getInt64PtrTy(LLVMContext &C, unsigned AS = 0);
/// Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const Type *) { return true; }
/// getPointerTo - Return a pointer to the current type. This is equival ent /// getPointerTo - Return a pointer to the current type. This is equival ent
/// to PointerType::get(Foo, AddrSpace). /// to PointerType::get(Foo, AddrSpace).
PointerType *getPointerTo(unsigned AddrSpace = 0); PointerType *getPointerTo(unsigned AddrSpace = 0);
private: private:
/// isSizedDerivedType - Derived types like structures and arrays are siz ed /// isSizedDerivedType - Derived types like structures and arrays are siz ed
/// iff all of the members of the type are sized as well. Since asking f or /// iff all of the members of the type are sized as well. Since asking f or
/// their size is relatively uncommon, move this operation out of line. /// their size is relatively uncommon, move this operation out of line.
bool isSizedDerivedType() const; bool isSizedDerivedType() const;
}; };
 End of changes. 10 change blocks. 
9 lines changed or deleted 16 lines changed or added


 TypeBuilder.h   TypeBuilder.h 
//===---- llvm/Support/TypeBuilder.h - Builder for LLVM types ---*- C++ -*- ===// //===---- llvm/TypeBuilder.h - Builder for LLVM types -----------*- C++ -*- ===//
// //
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
// //
// This file is distributed under the University of Illinois Open Source // This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details. // License. See LICENSE.TXT for details.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// //
// This file defines the TypeBuilder class, which is used as a convenient w ay to // This file defines the TypeBuilder class, which is used as a convenient w ay to
// create LLVM types with a consistent and simplified interface. // create LLVM types with a consistent and simplified interface.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_SUPPORT_TYPEBUILDER_H #ifndef LLVM_TYPEBUILDER_H
#define LLVM_SUPPORT_TYPEBUILDER_H #define LLVM_TYPEBUILDER_H
#include "llvm/DerivedTypes.h" #include "llvm/DerivedTypes.h"
#include "llvm/LLVMContext.h" #include "llvm/LLVMContext.h"
#include <limits.h> #include <limits.h>
namespace llvm { namespace llvm {
/// TypeBuilder - This provides a uniform API for looking up types /// TypeBuilder - This provides a uniform API for looking up types
/// known at compile time. To support cross-compilation, we define a /// known at compile time. To support cross-compilation, we define a
/// series of tag types in the llvm::types namespace, like i<N>, /// series of tag types in the llvm::types namespace, like i<N>,
 End of changes. 2 change blocks. 
3 lines changed or deleted 3 lines changed or added


 Use.h   Use.h 
skipping to change at line 29 skipping to change at line 29
// a pointer to any Use. For details, see: // a pointer to any Use. For details, see:
// //
// http://www.llvm.org/docs/ProgrammersManual.html#UserLayout // http://www.llvm.org/docs/ProgrammersManual.html#UserLayout
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_USE_H #ifndef LLVM_USE_H
#define LLVM_USE_H #define LLVM_USE_H
#include "llvm/ADT/PointerIntPair.h" #include "llvm/ADT/PointerIntPair.h"
#include "llvm/Support/Compiler.h"
#include <cstddef> #include <cstddef>
#include <iterator> #include <iterator>
namespace llvm { namespace llvm {
class Value; class Value;
class User; class User;
class Use; class Use;
template<typename> template<typename>
struct simplify_type; struct simplify_type;
skipping to change at line 69 skipping to change at line 70
/// swap - provide a fast substitute to std::swap<Use> /// swap - provide a fast substitute to std::swap<Use>
/// that also works with less standard-compliant compilers /// that also works with less standard-compliant compilers
void swap(Use &RHS); void swap(Use &RHS);
// A type for the word following an array of hung-off Uses in memory, whi ch is // A type for the word following an array of hung-off Uses in memory, whi ch is
// a pointer back to their User with the bottom bit set. // a pointer back to their User with the bottom bit set.
typedef PointerIntPair<User*, 1, unsigned> UserRef; typedef PointerIntPair<User*, 1, unsigned> UserRef;
private: private:
/// Copy ctor - do not implement /// Copy ctor - do not implement
Use(const Use &U); Use(const Use &U) LLVM_DELETED_FUNCTION;
/// Destructor - Only for zap() /// Destructor - Only for zap()
~Use() { ~Use() {
if (Val) removeFromList(); if (Val) removeFromList();
} }
enum PrevPtrTag { zeroDigitTag enum PrevPtrTag { zeroDigitTag
, oneDigitTag , oneDigitTag
, stopTag , stopTag
, fullStopTag }; , fullStopTag };
 End of changes. 2 change blocks. 
1 lines changed or deleted 2 lines changed or added


 User.h   User.h 
//===-- llvm/User.h - User class definition ---------------------*- C++ -*- ===// //===-- llvm/User.h - User class definition ---------------------*- C++ -*- ===//
// //
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
// //
// This file is distributed under the University of Illinois Open Source // This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details. // License. See LICENSE.TXT for details.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// //
// This class defines the interface that one who 'use's a Value must implem ent. // This class defines the interface that one who uses a Value must implemen t.
// Each instance of the Value class keeps track of what User's have handles // Each instance of the Value class keeps track of what User's have handles
// to it. // to it.
// //
// * Instructions are the largest class of User's. // * Instructions are the largest class of Users.
// * Constants may be users of other constants (think arrays and stuff) // * Constants may be users of other constants (think arrays and stuff)
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_USER_H #ifndef LLVM_USER_H
#define LLVM_USER_H #define LLVM_USER_H
#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/ErrorHandling.h"
#include "llvm/Value.h" #include "llvm/Value.h"
namespace llvm { namespace llvm {
/// OperandTraits - Compile-time customization of /// OperandTraits - Compile-time customization of
/// operand-related allocators and accessors /// operand-related allocators and accessors
/// for use of the User class /// for use of the User class
template <class> template <class>
struct OperandTraits; struct OperandTraits;
class User : public Value { class User : public Value {
User(const User &); // Do not implement User(const User &) LLVM_DELETED_FUNCTION;
void *operator new(size_t); // Do not implement void *operator new(size_t) LLVM_DELETED_FUNCTION;
template <unsigned> template <unsigned>
friend struct HungoffOperandTraits; friend struct HungoffOperandTraits;
virtual void anchor(); virtual void anchor();
protected: protected:
/// OperandList - This is a pointer to the array of Uses for this User. /// OperandList - This is a pointer to the array of Uses for this User.
/// For nodes of fixed arity (e.g. a binary operator) this array will liv e /// For nodes of fixed arity (e.g. a binary operator) this array will liv e
/// prefixed to some derived class instance. For nodes of resizable vari able /// prefixed to some derived class instance. For nodes of resizable vari able
/// arity (e.g. PHINodes, SwitchInst etc.), this memory will be dynamical ly /// arity (e.g. PHINodes, SwitchInst etc.), this memory will be dynamical ly
/// allocated and should be destroyed by the classes' virtual dtor. /// allocated and should be destroyed by the classes' virtual dtor.
Use *OperandList; Use *OperandList;
skipping to change at line 121 skipping to change at line 121
// Operand Iterator interface... // Operand Iterator interface...
// //
typedef Use* op_iterator; typedef Use* op_iterator;
typedef const Use* const_op_iterator; typedef const Use* const_op_iterator;
inline op_iterator op_begin() { return OperandList; } inline op_iterator op_begin() { return OperandList; }
inline const_op_iterator op_begin() const { return OperandList; } inline const_op_iterator op_begin() const { return OperandList; }
inline op_iterator op_end() { return OperandList+NumOperand s; } inline op_iterator op_end() { return OperandList+NumOperand s; }
inline const_op_iterator op_end() const { return OperandList+NumOperand s; } inline const_op_iterator op_end() const { return OperandList+NumOperand s; }
/// Convenience iterator for directly iterating over the Values in the
/// OperandList
class value_op_iterator : public std::iterator<std::forward_iterator_tag,
Value*> {
op_iterator OI;
public:
explicit value_op_iterator(Use *U) : OI(U) {}
bool operator==(const value_op_iterator &x) const {
return OI == x.OI;
}
bool operator!=(const value_op_iterator &x) const {
return !operator==(x);
}
/// Iterator traversal: forward iteration only
value_op_iterator &operator++() { // Preincrement
++OI;
return *this;
}
value_op_iterator operator++(int) { // Postincrement
value_op_iterator tmp = *this; ++*this; return tmp;
}
/// Retrieve a pointer to the current Value.
Value *operator*() const {
return *OI;
}
Value *operator->() const { return operator*(); }
};
inline value_op_iterator value_op_begin() {
return value_op_iterator(op_begin());
}
inline value_op_iterator value_op_end() {
return value_op_iterator(op_end());
}
// dropAllReferences() - This function is in charge of "letting go" of al l // dropAllReferences() - This function is in charge of "letting go" of al l
// objects that this User refers to. This allows one to // objects that this User refers to. This allows one to
// 'delete' a whole class at a time, even though there may be circular // 'delete' a whole class at a time, even though there may be circular
// references... First all references are dropped, and all use counts go to // references... First all references are dropped, and all use counts go to
// zero. Then everything is deleted for real. Note that no operations a re // zero. Then everything is deleted for real. Note that no operations a re
// valid on an object that has "dropped all references", except operator // valid on an object that has "dropped all references", except operator
// delete. // delete.
// //
void dropAllReferences() { void dropAllReferences() {
for (op_iterator i = op_begin(), e = op_end(); i != e; ++i) for (op_iterator i = op_begin(), e = op_end(); i != e; ++i)
i->set(0); i->set(0);
} }
/// replaceUsesOfWith - Replaces all references to the "From" definition with /// replaceUsesOfWith - Replaces all references to the "From" definition with
/// references to the "To" definition. /// references to the "To" definition.
/// ///
void replaceUsesOfWith(Value *From, Value *To); void replaceUsesOfWith(Value *From, Value *To);
// Methods for support type inquiry through isa, cast, and dyn_cast: // Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const User *) { return true; }
static inline bool classof(const Value *V) { static inline bool classof(const Value *V) {
return isa<Instruction>(V) || isa<Constant>(V); return isa<Instruction>(V) || isa<Constant>(V);
} }
}; };
template<> struct simplify_type<User::op_iterator> { template<> struct simplify_type<User::op_iterator> {
typedef Value* SimpleType; typedef Value* SimpleType;
static SimpleType getSimplifiedValue(const User::op_iterator &Val) { static SimpleType getSimplifiedValue(const User::op_iterator &Val) {
return static_cast<SimpleType>(Val->get()); return static_cast<SimpleType>(Val->get());
 End of changes. 5 change blocks. 
5 lines changed or deleted 43 lines changed or added


 Value.h   Value.h 
skipping to change at line 19 skipping to change at line 19
// //
// This file declares the Value class. // This file declares the Value class.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_VALUE_H #ifndef LLVM_VALUE_H
#define LLVM_VALUE_H #define LLVM_VALUE_H
#include "llvm/Use.h" #include "llvm/Use.h"
#include "llvm/Support/Casting.h" #include "llvm/Support/Casting.h"
#include "llvm/Support/Compiler.h"
namespace llvm { namespace llvm {
class Constant; class Constant;
class Argument; class Argument;
class Instruction; class Instruction;
class BasicBlock; class BasicBlock;
class GlobalValue; class GlobalValue;
class Function; class Function;
class GlobalVariable; class GlobalVariable;
skipping to change at line 83 skipping to change at line 84
/// This field is initialized to zero by the ctor. /// This field is initialized to zero by the ctor.
unsigned short SubclassData; unsigned short SubclassData;
Type *VTy; Type *VTy;
Use *UseList; Use *UseList;
friend class ValueSymbolTable; // Allow ValueSymbolTable to directly mod Name. friend class ValueSymbolTable; // Allow ValueSymbolTable to directly mod Name.
friend class ValueHandleBase; friend class ValueHandleBase;
ValueName *Name; ValueName *Name;
void operator=(const Value &); // Do not implement void operator=(const Value &) LLVM_DELETED_FUNCTION;
Value(const Value &); // Do not implement Value(const Value &) LLVM_DELETED_FUNCTION;
protected: protected:
/// printCustom - Value subclasses can override this to implement custom /// printCustom - Value subclasses can override this to implement custom
/// printing behavior. /// printing behavior.
virtual void printCustom(raw_ostream &O) const; virtual void printCustom(raw_ostream &O) const;
Value(Type *Ty, unsigned scid); Value(Type *Ty, unsigned scid);
public: public:
virtual ~Value(); virtual ~Value();
skipping to change at line 123 skipping to change at line 124
void setValueName(ValueName *VN) { Name = VN; } void setValueName(ValueName *VN) { Name = VN; }
/// getName() - Return a constant reference to the value's name. This is cheap /// getName() - Return a constant reference to the value's name. This is cheap
/// and guaranteed to return the same reference as long as the value is n ot /// and guaranteed to return the same reference as long as the value is n ot
/// modified. /// modified.
StringRef getName() const; StringRef getName() const;
/// setName() - Change the name of the value, choosing a new unique name if /// setName() - Change the name of the value, choosing a new unique name if
/// the provided name is taken. /// the provided name is taken.
/// ///
/// \arg Name - The new name; or "" if the value's name should be removed . /// \param Name The new name; or "" if the value's name should be removed .
void setName(const Twine &Name); void setName(const Twine &Name);
/// takeName - transfer the name from V to this value, setting V's name t o /// takeName - transfer the name from V to this value, setting V's name t o
/// empty. It is an error to call V->takeName(V). /// empty. It is an error to call V->takeName(V).
void takeName(Value *V); void takeName(Value *V);
/// replaceAllUsesWith - Go through the uses list for this definition and make /// replaceAllUsesWith - Go through the uses list for this definition and make
/// each use point to "V" instead of "this". After this completes, 'this 's /// each use point to "V" instead of "this". After this completes, 'this 's
/// use list is guaranteed to be empty. /// use list is guaranteed to be empty.
/// ///
skipping to change at line 259 skipping to change at line 260
/// intersectOptionalDataWith - Clear any optional flags in this value /// intersectOptionalDataWith - Clear any optional flags in this value
/// that are not also set in the given value. /// that are not also set in the given value.
void intersectOptionalDataWith(const Value *V) { void intersectOptionalDataWith(const Value *V) {
SubclassOptionalData &= V->SubclassOptionalData; SubclassOptionalData &= V->SubclassOptionalData;
} }
/// hasValueHandle - Return true if there is a value handle associated wi th /// hasValueHandle - Return true if there is a value handle associated wi th
/// this value. /// this value.
bool hasValueHandle() const { return HasValueHandle; } bool hasValueHandle() const { return HasValueHandle; }
// Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const Value *) {
return true; // Values are always values.
}
/// stripPointerCasts - This method strips off any unneeded pointer casts and /// stripPointerCasts - This method strips off any unneeded pointer casts and
/// all-zero GEPs from the specified value, returning the original uncast ed /// all-zero GEPs from the specified value, returning the original uncast ed
/// value. If this is called on a non-pointer value, it returns 'this'. /// value. If this is called on a non-pointer value, it returns 'this'.
Value *stripPointerCasts(); Value *stripPointerCasts();
const Value *stripPointerCasts() const { const Value *stripPointerCasts() const {
return const_cast<Value*>(this)->stripPointerCasts(); return const_cast<Value*>(this)->stripPointerCasts();
} }
/// stripInBoundsConstantOffsets - This method strips off unneeded pointe r casts and /// stripInBoundsConstantOffsets - This method strips off unneeded pointe r casts and
/// all-constant GEPs from the specified value, returning the original /// all-constant GEPs from the specified value, returning the original
 End of changes. 4 change blocks. 
8 lines changed or deleted 4 lines changed or added


 ValueHandle.h   ValueHandle.h 
skipping to change at line 63 skipping to change at line 63
private: private:
PointerIntPair<ValueHandleBase**, 2, HandleBaseKind> PrevPair; PointerIntPair<ValueHandleBase**, 2, HandleBaseKind> PrevPair;
ValueHandleBase *Next; ValueHandleBase *Next;
// A subclass may want to store some information along with the value // A subclass may want to store some information along with the value
// pointer. Allow them to do this by making the value pointer a pointer-i nt // pointer. Allow them to do this by making the value pointer a pointer-i nt
// pair. The 'setValPtrInt' and 'getValPtrInt' methods below give them th is // pair. The 'setValPtrInt' and 'getValPtrInt' methods below give them th is
// access. // access.
PointerIntPair<Value*, 2> VP; PointerIntPair<Value*, 2> VP;
explicit ValueHandleBase(const ValueHandleBase&); // DO NOT IMPLEMENT. ValueHandleBase(const ValueHandleBase&) LLVM_DELETED_FUNCTION;
public: public:
explicit ValueHandleBase(HandleBaseKind Kind) explicit ValueHandleBase(HandleBaseKind Kind)
: PrevPair(0, Kind), Next(0), VP(0, 0) {} : PrevPair(0, Kind), Next(0), VP(0, 0) {}
ValueHandleBase(HandleBaseKind Kind, Value *V) ValueHandleBase(HandleBaseKind Kind, Value *V)
: PrevPair(0, Kind), Next(0), VP(V, 0) { : PrevPair(0, Kind), Next(0), VP(V, 0) {
if (isValid(VP.getPointer())) if (isValid(VP.getPointer()))
AddToUseList(); AddToUseList();
} }
ValueHandleBase(HandleBaseKind Kind, const ValueHandleBase &RHS) ValueHandleBase(HandleBaseKind Kind, const ValueHandleBase &RHS)
: PrevPair(0, Kind), Next(0), VP(RHS.VP) { : PrevPair(0, Kind), Next(0), VP(RHS.VP) {
skipping to change at line 113 skipping to change at line 113
void setValPtrInt(unsigned K) { VP.setInt(K); } void setValPtrInt(unsigned K) { VP.setInt(K); }
unsigned getValPtrInt() const { return VP.getInt(); } unsigned getValPtrInt() const { return VP.getInt(); }
static bool isValid(Value *V) { static bool isValid(Value *V) {
return V && return V &&
V != DenseMapInfo<Value *>::getEmptyKey() && V != DenseMapInfo<Value *>::getEmptyKey() &&
V != DenseMapInfo<Value *>::getTombstoneKey(); V != DenseMapInfo<Value *>::getTombstoneKey();
} }
private: public:
// Callbacks made from Value. // Callbacks made from Value.
static void ValueIsDeleted(Value *V); static void ValueIsDeleted(Value *V);
static void ValueIsRAUWd(Value *Old, Value *New); static void ValueIsRAUWd(Value *Old, Value *New);
private:
// Internal implementation details. // Internal implementation details.
ValueHandleBase **getPrevPtr() const { return PrevPair.getPointer(); } ValueHandleBase **getPrevPtr() const { return PrevPair.getPointer(); }
HandleBaseKind getKind() const { return PrevPair.getInt(); } HandleBaseKind getKind() const { return PrevPair.getInt(); }
void setPrevPtr(ValueHandleBase **Ptr) { PrevPair.setPointer(Ptr); } void setPrevPtr(ValueHandleBase **Ptr) { PrevPair.setPointer(Ptr); }
/// AddToExistingUseList - Add this ValueHandle to the use list for VP, w here /// AddToExistingUseList - Add this ValueHandle to the use list for VP, w here
/// List is the address of either the head of the list or a Next node wit hin /// List is the address of either the head of the list or a Next node wit hin
/// the existing use list. /// the existing use list.
void AddToExistingUseList(ValueHandleBase **List); void AddToExistingUseList(ValueHandleBase **List);
skipping to change at line 369 skipping to change at line 370
/// callbacks that run when the underlying Value has RAUW called on it or i s /// callbacks that run when the underlying Value has RAUW called on it or i s
/// destroyed. This class can be used as the key of a map, as long as the user /// destroyed. This class can be used as the key of a map, as long as the user
/// takes it out of the map before calling setValPtr() (since the map has t o /// takes it out of the map before calling setValPtr() (since the map has t o
/// rearrange itself when the pointer changes). Unlike ValueHandleBase, th is /// rearrange itself when the pointer changes). Unlike ValueHandleBase, th is
/// class has a vtable and a virtual destructor. /// class has a vtable and a virtual destructor.
class CallbackVH : public ValueHandleBase { class CallbackVH : public ValueHandleBase {
protected: protected:
CallbackVH(const CallbackVH &RHS) CallbackVH(const CallbackVH &RHS)
: ValueHandleBase(Callback, RHS) {} : ValueHandleBase(Callback, RHS) {}
virtual ~CallbackVH(); virtual ~CallbackVH() {}
void setValPtr(Value *P) { void setValPtr(Value *P) {
ValueHandleBase::operator=(P); ValueHandleBase::operator=(P);
} }
public: public:
CallbackVH() : ValueHandleBase(Callback) {} CallbackVH() : ValueHandleBase(Callback) {}
CallbackVH(Value *P) : ValueHandleBase(Callback, P) {} CallbackVH(Value *P) : ValueHandleBase(Callback, P) {}
operator Value*() const { operator Value*() const {
skipping to change at line 391 skipping to change at line 392
} }
/// Called when this->getValPtr() is destroyed, inside ~Value(), so you m ay /// Called when this->getValPtr() is destroyed, inside ~Value(), so you m ay
/// call any non-virtual Value method on getValPtr(), but no subclass met hods. /// call any non-virtual Value method on getValPtr(), but no subclass met hods.
/// If WeakVH were implemented as a CallbackVH, it would use this method to /// If WeakVH were implemented as a CallbackVH, it would use this method to
/// call setValPtr(NULL). AssertingVH would use this method to cause an /// call setValPtr(NULL). AssertingVH would use this method to cause an
/// assertion failure. /// assertion failure.
/// ///
/// All implementations must remove the reference from this object to the /// All implementations must remove the reference from this object to the
/// Value that's being destroyed. /// Value that's being destroyed.
virtual void deleted() { virtual void deleted();
setValPtr(NULL);
}
/// Called when this->getValPtr()->replaceAllUsesWith(new_value) is calle d, /// Called when this->getValPtr()->replaceAllUsesWith(new_value) is calle d,
/// _before_ any of the uses have actually been replaced. If WeakVH were /// _before_ any of the uses have actually been replaced. If WeakVH were
/// implemented as a CallbackVH, it would use this method to call /// implemented as a CallbackVH, it would use this method to call
/// setValPtr(new_value). AssertingVH would do nothing in this method. /// setValPtr(new_value). AssertingVH would do nothing in this method.
virtual void allUsesReplacedWith(Value *) {} virtual void allUsesReplacedWith(Value *);
}; };
// Specialize simplify_type to allow CallbackVH to participate in // Specialize simplify_type to allow CallbackVH to participate in
// dyn_cast, isa, etc. // dyn_cast, isa, etc.
template<typename From> struct simplify_type; template<typename From> struct simplify_type;
template<> struct simplify_type<const CallbackVH> { template<> struct simplify_type<const CallbackVH> {
typedef Value* SimpleType; typedef Value* SimpleType;
static SimpleType getSimplifiedValue(const CallbackVH &CVH) { static SimpleType getSimplifiedValue(const CallbackVH &CVH) {
return static_cast<Value *>(CVH); return static_cast<Value *>(CVH);
} }
 End of changes. 6 change blocks. 
7 lines changed or deleted 6 lines changed or added


 ValueMap.h   ValueMap.h 
skipping to change at line 83 skipping to change at line 83
/// See the file comment. /// See the file comment.
template<typename KeyT, typename ValueT, typename Config =ValueMapConfig<Ke yT> > template<typename KeyT, typename ValueT, typename Config =ValueMapConfig<Ke yT> >
class ValueMap { class ValueMap {
friend class ValueMapCallbackVH<KeyT, ValueT, Config>; friend class ValueMapCallbackVH<KeyT, ValueT, Config>;
typedef ValueMapCallbackVH<KeyT, ValueT, Config> ValueMapCVH; typedef ValueMapCallbackVH<KeyT, ValueT, Config> ValueMapCVH;
typedef DenseMap<ValueMapCVH, ValueT, DenseMapInfo<ValueMapCVH> > MapT; typedef DenseMap<ValueMapCVH, ValueT, DenseMapInfo<ValueMapCVH> > MapT;
typedef typename Config::ExtraData ExtraData; typedef typename Config::ExtraData ExtraData;
MapT Map; MapT Map;
ExtraData Data; ExtraData Data;
ValueMap(const ValueMap&); // DO NOT IMPLEMENT ValueMap(const ValueMap&) LLVM_DELETED_FUNCTION;
ValueMap& operator=(const ValueMap&); // DO NOT IMPLEMENT ValueMap& operator=(const ValueMap&) LLVM_DELETED_FUNCTION;
public: public:
typedef KeyT key_type; typedef KeyT key_type;
typedef ValueT mapped_type; typedef ValueT mapped_type;
typedef std::pair<KeyT, ValueT> value_type; typedef std::pair<KeyT, ValueT> value_type;
explicit ValueMap(unsigned NumInitBuckets = 64) explicit ValueMap(unsigned NumInitBuckets = 64)
: Map(NumInitBuckets), Data() {} : Map(NumInitBuckets), Data() {}
explicit ValueMap(const ExtraData &Data, unsigned NumInitBuckets = 64) explicit ValueMap(const ExtraData &Data, unsigned NumInitBuckets = 64)
: Map(NumInitBuckets), Data(Data) {} : Map(NumInitBuckets), Data(Data) {}
skipping to change at line 114 skipping to change at line 114
bool empty() const { return Map.empty(); } bool empty() const { return Map.empty(); }
unsigned size() const { return Map.size(); } unsigned size() const { return Map.size(); }
/// Grow the map so that it has at least Size buckets. Does not shrink /// Grow the map so that it has at least Size buckets. Does not shrink
void resize(size_t Size) { Map.resize(Size); } void resize(size_t Size) { Map.resize(Size); }
void clear() { Map.clear(); } void clear() { Map.clear(); }
/// count - Return true if the specified key is in the map. /// count - Return true if the specified key is in the map.
bool count(const KeyT &Val) const { bool count(const KeyT &Val) const {
return Map.count(Wrap(Val)); return Map.find_as(Val) != Map.end();
} }
iterator find(const KeyT &Val) { iterator find(const KeyT &Val) {
return iterator(Map.find(Wrap(Val))); return iterator(Map.find_as(Val));
} }
const_iterator find(const KeyT &Val) const { const_iterator find(const KeyT &Val) const {
return const_iterator(Map.find(Wrap(Val))); return const_iterator(Map.find_as(Val));
} }
/// lookup - Return the entry for the specified key, or a default /// lookup - Return the entry for the specified key, or a default
/// constructed value if no such entry exists. /// constructed value if no such entry exists.
ValueT lookup(const KeyT &Val) const { ValueT lookup(const KeyT &Val) const {
return Map.lookup(Wrap(Val)); typename MapT::const_iterator I = Map.find_as(Val);
return I != Map.end() ? I->second : ValueT();
} }
// Inserts key,value pair into the map if the key isn't already in the ma p. // Inserts key,value pair into the map if the key isn't already in the ma p.
// If the key is already in the map, it returns false and doesn't update the // If the key is already in the map, it returns false and doesn't update the
// value. // value.
std::pair<iterator, bool> insert(const std::pair<KeyT, ValueT> &KV) { std::pair<iterator, bool> insert(const std::pair<KeyT, ValueT> &KV) {
std::pair<typename MapT::iterator, bool> map_result= std::pair<typename MapT::iterator, bool> map_result=
Map.insert(std::make_pair(Wrap(KV.first), KV.second)); Map.insert(std::make_pair(Wrap(KV.first), KV.second));
return std::make_pair(iterator(map_result.first), map_result.second); return std::make_pair(iterator(map_result.first), map_result.second);
} }
/// insert - Range insertion of pairs. /// insert - Range insertion of pairs.
template<typename InputIt> template<typename InputIt>
void insert(InputIt I, InputIt E) { void insert(InputIt I, InputIt E) {
for (; I != E; ++I) for (; I != E; ++I)
insert(*I); insert(*I);
} }
bool erase(const KeyT &Val) { bool erase(const KeyT &Val) {
return Map.erase(Wrap(Val)); typename MapT::iterator I = Map.find_as(Val);
if (I == Map.end())
return false;
Map.erase(I);
return true;
} }
void erase(iterator I) { void erase(iterator I) {
return Map.erase(I.base()); return Map.erase(I.base());
} }
value_type& FindAndConstruct(const KeyT &Key) { value_type& FindAndConstruct(const KeyT &Key) {
return Map.FindAndConstruct(Wrap(Key)); return Map.FindAndConstruct(Wrap(Key));
} }
ValueT &operator[](const KeyT &Key) { ValueT &operator[](const KeyT &Key) {
skipping to change at line 258 skipping to change at line 264
static inline VH getEmptyKey() { static inline VH getEmptyKey() {
return VH(PointerInfo::getEmptyKey(), NULL); return VH(PointerInfo::getEmptyKey(), NULL);
} }
static inline VH getTombstoneKey() { static inline VH getTombstoneKey() {
return VH(PointerInfo::getTombstoneKey(), NULL); return VH(PointerInfo::getTombstoneKey(), NULL);
} }
static unsigned getHashValue(const VH &Val) { static unsigned getHashValue(const VH &Val) {
return PointerInfo::getHashValue(Val.Unwrap()); return PointerInfo::getHashValue(Val.Unwrap());
} }
static unsigned getHashValue(const KeyT &Val) {
return PointerInfo::getHashValue(Val);
}
static bool isEqual(const VH &LHS, const VH &RHS) { static bool isEqual(const VH &LHS, const VH &RHS) {
return LHS == RHS; return LHS == RHS;
} }
static bool isEqual(const KeyT &LHS, const VH &RHS) {
return LHS == RHS.getValPtr();
}
}; };
template<typename DenseMapT, typename KeyT> template<typename DenseMapT, typename KeyT>
class ValueMapIterator : class ValueMapIterator :
public std::iterator<std::forward_iterator_tag, public std::iterator<std::forward_iterator_tag,
std::pair<KeyT, typename DenseMapT::mapped_type>, std::pair<KeyT, typename DenseMapT::mapped_type>,
ptrdiff_t> { ptrdiff_t> {
typedef typename DenseMapT::iterator BaseT; typedef typename DenseMapT::iterator BaseT;
typedef typename DenseMapT::mapped_type ValueT; typedef typename DenseMapT::mapped_type ValueT;
BaseT I; BaseT I;
 End of changes. 8 change blocks. 
7 lines changed or deleted 19 lines changed or added


 ValueMapper.h   ValueMapper.h 
skipping to change at line 28 skipping to change at line 28
#include "llvm/ADT/ValueMap.h" #include "llvm/ADT/ValueMap.h"
namespace llvm { namespace llvm {
class Value; class Value;
class Instruction; class Instruction;
typedef ValueMap<const Value *, WeakVH> ValueToValueMapTy; typedef ValueMap<const Value *, WeakVH> ValueToValueMapTy;
/// ValueMapTypeRemapper - This is a class that can be implemented by cli ents /// ValueMapTypeRemapper - This is a class that can be implemented by cli ents
/// to remap types when cloning constants and instructions. /// to remap types when cloning constants and instructions.
class ValueMapTypeRemapper { class ValueMapTypeRemapper {
virtual void Anchor(); // Out of line method. virtual void anchor(); // Out of line method.
public: public:
virtual ~ValueMapTypeRemapper() {} virtual ~ValueMapTypeRemapper() {}
/// remapType - The client should implement this method if they want to /// remapType - The client should implement this method if they want to
/// remap types while mapping values. /// remap types while mapping values.
virtual Type *remapType(Type *SrcTy) = 0; virtual Type *remapType(Type *SrcTy) = 0;
}; };
/// RemapFlags - These are flags that the value mapping APIs allow. /// RemapFlags - These are flags that the value mapping APIs allow.
enum RemapFlags { enum RemapFlags {
 End of changes. 1 change blocks. 
1 lines changed or deleted 1 lines changed or added


 ValueTracking.h   ValueTracking.h 
skipping to change at line 25 skipping to change at line 25
#ifndef LLVM_ANALYSIS_VALUETRACKING_H #ifndef LLVM_ANALYSIS_VALUETRACKING_H
#define LLVM_ANALYSIS_VALUETRACKING_H #define LLVM_ANALYSIS_VALUETRACKING_H
#include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/ArrayRef.h"
#include "llvm/Support/DataTypes.h" #include "llvm/Support/DataTypes.h"
namespace llvm { namespace llvm {
class Value; class Value;
class Instruction; class Instruction;
class APInt; class APInt;
class TargetData; class DataLayout;
class StringRef; class StringRef;
class MDNode; class MDNode;
/// ComputeMaskedBits - Determine which of the bits specified in Mask are /// ComputeMaskedBits - Determine which of the bits specified in Mask are
/// known to be either zero or one and return them in the KnownZero/Known One /// known to be either zero or one and return them in the KnownZero/Known One
/// bit sets. This code only analyzes bits in Mask, in order to short-ci rcuit /// bit sets. This code only analyzes bits in Mask, in order to short-ci rcuit
/// processing. /// processing.
/// ///
/// This function is defined on values with integer type, values with poi nter /// This function is defined on values with integer type, values with poi nter
/// type (but only if TD is non-null), and vectors of integers. In the c ase /// type (but only if TD is non-null), and vectors of integers. In the c ase
/// where V is a vector, the mask, known zero, and known one values are t he /// where V is a vector, the mask, known zero, and known one values are t he
/// same width as the vector element, and the bit is set only if it is tr ue /// same width as the vector element, and the bit is set only if it is tr ue
/// for all of the elements in the vector. /// for all of the elements in the vector.
void ComputeMaskedBits(Value *V, APInt &KnownZero, APInt &KnownOne, void ComputeMaskedBits(Value *V, APInt &KnownZero, APInt &KnownOne,
const TargetData *TD = 0, unsigned Depth = 0); const DataLayout *TD = 0, unsigned Depth = 0);
void computeMaskedBitsLoad(const MDNode &Ranges, APInt &KnownZero); void computeMaskedBitsLoad(const MDNode &Ranges, APInt &KnownZero);
/// ComputeSignBit - Determine whether the sign bit is known to be zero o r /// ComputeSignBit - Determine whether the sign bit is known to be zero o r
/// one. Convenience wrapper around ComputeMaskedBits. /// one. Convenience wrapper around ComputeMaskedBits.
void ComputeSignBit(Value *V, bool &KnownZero, bool &KnownOne, void ComputeSignBit(Value *V, bool &KnownZero, bool &KnownOne,
const TargetData *TD = 0, unsigned Depth = 0); const DataLayout *TD = 0, unsigned Depth = 0);
/// isPowerOfTwo - Return true if the given value is known to have exactl y one /// isPowerOfTwo - Return true if the given value is known to have exactl y one
/// bit set when defined. For vectors return true if every element is kno wn to /// bit set when defined. For vectors return true if every element is kno wn to
/// be a power of two when defined. Supports values with integer or poin ter /// be a power of two when defined. Supports values with integer or poin ter
/// type and vectors of integers. If 'OrZero' is set then returns true i f the /// type and vectors of integers. If 'OrZero' is set then returns true i f the
/// given value is either a power of two or zero. /// given value is either a power of two or zero.
bool isPowerOfTwo(Value *V, const TargetData *TD = 0, bool OrZero = false , bool isPowerOfTwo(Value *V, const DataLayout *TD = 0, bool OrZero = false ,
unsigned Depth = 0); unsigned Depth = 0);
/// isKnownNonZero - Return true if the given value is known to be non-ze ro /// isKnownNonZero - Return true if the given value is known to be non-ze ro
/// when defined. For vectors return true if every element is known to b e /// when defined. For vectors return true if every element is known to b e
/// non-zero when defined. Supports values with integer or pointer type and /// non-zero when defined. Supports values with integer or pointer type and
/// vectors of integers. /// vectors of integers.
bool isKnownNonZero(Value *V, const TargetData *TD = 0, unsigned Depth = 0); bool isKnownNonZero(Value *V, const DataLayout *TD = 0, unsigned Depth = 0);
/// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. W e use /// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. W e use
/// this predicate to simplify operations downstream. Mask is known to b e /// this predicate to simplify operations downstream. Mask is known to b e
/// zero for bits that V cannot have. /// zero for bits that V cannot have.
/// ///
/// This function is defined on values with integer type, values with poi nter /// This function is defined on values with integer type, values with poi nter
/// type (but only if TD is non-null), and vectors of integers. In the c ase /// type (but only if TD is non-null), and vectors of integers. In the c ase
/// where V is a vector, the mask, known zero, and known one values are t he /// where V is a vector, the mask, known zero, and known one values are t he
/// same width as the vector element, and the bit is set only if it is tr ue /// same width as the vector element, and the bit is set only if it is tr ue
/// for all of the elements in the vector. /// for all of the elements in the vector.
bool MaskedValueIsZero(Value *V, const APInt &Mask, bool MaskedValueIsZero(Value *V, const APInt &Mask,
const TargetData *TD = 0, unsigned Depth = 0); const DataLayout *TD = 0, unsigned Depth = 0);
/// ComputeNumSignBits - Return the number of times the sign bit of the /// ComputeNumSignBits - Return the number of times the sign bit of the
/// register is replicated into the other bits. We know that at least 1 bit /// register is replicated into the other bits. We know that at least 1 bit
/// is always equal to the sign bit (itself), but other cases can give us /// is always equal to the sign bit (itself), but other cases can give us
/// information. For example, immediately after an "ashr X, 2", we know that /// information. For example, immediately after an "ashr X, 2", we know that
/// the top 3 bits are all equal to each other, so we return 3. /// the top 3 bits are all equal to each other, so we return 3.
/// ///
/// 'Op' must have a scalar integer type. /// 'Op' must have a scalar integer type.
/// ///
unsigned ComputeNumSignBits(Value *Op, const TargetData *TD = 0, unsigned ComputeNumSignBits(Value *Op, const DataLayout *TD = 0,
unsigned Depth = 0); unsigned Depth = 0);
/// ComputeMultiple - This function computes the integer multiple of Base that /// ComputeMultiple - This function computes the integer multiple of Base that
/// equals V. If successful, it returns true and returns the multiple in /// equals V. If successful, it returns true and returns the multiple in
/// Multiple. If unsuccessful, it returns false. Also, if V can be /// Multiple. If unsuccessful, it returns false. Also, if V can be
/// simplified to an integer, then the simplified V is returned in Val. Look /// simplified to an integer, then the simplified V is returned in Val. Look
/// through sext only if LookThroughSExt=true. /// through sext only if LookThroughSExt=true.
bool ComputeMultiple(Value *V, unsigned Base, Value *&Multiple, bool ComputeMultiple(Value *V, unsigned Base, Value *&Multiple,
bool LookThroughSExt = false, bool LookThroughSExt = false,
unsigned Depth = 0); unsigned Depth = 0);
skipping to change at line 120 skipping to change at line 120
/// If InsertBefore is not null, this function will duplicate (modified) /// If InsertBefore is not null, this function will duplicate (modified)
/// insertvalues when a part of a nested struct is extracted. /// insertvalues when a part of a nested struct is extracted.
Value *FindInsertedValue(Value *V, Value *FindInsertedValue(Value *V,
ArrayRef<unsigned> idx_range, ArrayRef<unsigned> idx_range,
Instruction *InsertBefore = 0); Instruction *InsertBefore = 0);
/// GetPointerBaseWithConstantOffset - Analyze the specified pointer to s ee if /// GetPointerBaseWithConstantOffset - Analyze the specified pointer to s ee if
/// it can be expressed as a base pointer plus a constant offset. Return the /// it can be expressed as a base pointer plus a constant offset. Return the
/// base and offset to the caller. /// base and offset to the caller.
Value *GetPointerBaseWithConstantOffset(Value *Ptr, int64_t &Offset, Value *GetPointerBaseWithConstantOffset(Value *Ptr, int64_t &Offset,
const TargetData &TD); const DataLayout &TD);
static inline const Value * static inline const Value *
GetPointerBaseWithConstantOffset(const Value *Ptr, int64_t &Offset, GetPointerBaseWithConstantOffset(const Value *Ptr, int64_t &Offset,
const TargetData &TD) { const DataLayout &TD) {
return GetPointerBaseWithConstantOffset(const_cast<Value*>(Ptr), Offset ,TD); return GetPointerBaseWithConstantOffset(const_cast<Value*>(Ptr), Offset ,TD);
} }
/// getConstantStringInfo - This function computes the length of a /// getConstantStringInfo - This function computes the length of a
/// null-terminated C string pointed to by V. If successful, it returns true /// null-terminated C string pointed to by V. If successful, it returns true
/// and returns the string in Str. If unsuccessful, it returns false. T his /// and returns the string in Str. If unsuccessful, it returns false. T his
/// does not include the trailing nul character by default. If TrimAtNul is /// does not include the trailing nul character by default. If TrimAtNul is
/// set to false, then this returns any trailing nul characters as well a s any /// set to false, then this returns any trailing nul characters as well a s any
/// other characters that come after it. /// other characters that come after it.
bool getConstantStringInfo(const Value *V, StringRef &Str, bool getConstantStringInfo(const Value *V, StringRef &Str,
skipping to change at line 145 skipping to change at line 145
/// GetStringLength - If we can compute the length of the string pointed to by /// GetStringLength - If we can compute the length of the string pointed to by
/// the specified pointer, return 'len+1'. If we can't, return 0. /// the specified pointer, return 'len+1'. If we can't, return 0.
uint64_t GetStringLength(Value *V); uint64_t GetStringLength(Value *V);
/// GetUnderlyingObject - This method strips off any GEP address adjustme nts /// GetUnderlyingObject - This method strips off any GEP address adjustme nts
/// and pointer casts from the specified value, returning the original ob ject /// and pointer casts from the specified value, returning the original ob ject
/// being addressed. Note that the returned value has pointer type if th e /// being addressed. Note that the returned value has pointer type if th e
/// specified value does. If the MaxLookup value is non-zero, it limits the /// specified value does. If the MaxLookup value is non-zero, it limits the
/// number of instructions to be stripped off. /// number of instructions to be stripped off.
Value *GetUnderlyingObject(Value *V, const TargetData *TD = 0, Value *GetUnderlyingObject(Value *V, const DataLayout *TD = 0,
unsigned MaxLookup = 6); unsigned MaxLookup = 6);
static inline const Value * static inline const Value *
GetUnderlyingObject(const Value *V, const TargetData *TD = 0, GetUnderlyingObject(const Value *V, const DataLayout *TD = 0,
unsigned MaxLookup = 6) { unsigned MaxLookup = 6) {
return GetUnderlyingObject(const_cast<Value *>(V), TD, MaxLookup); return GetUnderlyingObject(const_cast<Value *>(V), TD, MaxLookup);
} }
/// GetUnderlyingObjects - This method is similar to GetUnderlyingObject
/// except that it can look through phi and select instructions and retur
n
/// multiple objects.
void GetUnderlyingObjects(Value *V,
SmallVectorImpl<Value *> &Objects,
const DataLayout *TD = 0,
unsigned MaxLookup = 6);
/// onlyUsedByLifetimeMarkers - Return true if the only users of this poi nter /// onlyUsedByLifetimeMarkers - Return true if the only users of this poi nter
/// are lifetime markers. /// are lifetime markers.
bool onlyUsedByLifetimeMarkers(const Value *V); bool onlyUsedByLifetimeMarkers(const Value *V);
/// isSafeToSpeculativelyExecute - Return true if the instruction does no t /// isSafeToSpeculativelyExecute - Return true if the instruction does no t
/// have any effects besides calculating the result and does not have /// have any effects besides calculating the result and does not have
/// undefined behavior. /// undefined behavior.
/// ///
/// This method never returns true for an instruction that returns true f or /// This method never returns true for an instruction that returns true f or
/// mayHaveSideEffects; however, this method also does some other checks in /// mayHaveSideEffects; however, this method also does some other checks in
skipping to change at line 176 skipping to change at line 184
/// for malloc and alloca because speculatively executing them might caus e a /// for malloc and alloca because speculatively executing them might caus e a
/// memory leak. It also returns false for instructions related to contro l /// memory leak. It also returns false for instructions related to contro l
/// flow, specifically terminators and PHI nodes. /// flow, specifically terminators and PHI nodes.
/// ///
/// This method only looks at the instruction itself and its operands, so if /// This method only looks at the instruction itself and its operands, so if
/// this method returns true, it is safe to move the instruction as long as /// this method returns true, it is safe to move the instruction as long as
/// the correct dominance relationships for the operands and users hold. /// the correct dominance relationships for the operands and users hold.
/// However, this method can return true for instructions that read memor y; /// However, this method can return true for instructions that read memor y;
/// for such instructions, moving them may change the resulting value. /// for such instructions, moving them may change the resulting value.
bool isSafeToSpeculativelyExecute(const Value *V, bool isSafeToSpeculativelyExecute(const Value *V,
const TargetData *TD = 0); const DataLayout *TD = 0);
} // end namespace llvm } // end namespace llvm
#endif #endif
 End of changes. 13 change blocks. 
12 lines changed or deleted 21 lines changed or added


 ValueTypes.h   ValueTypes.h 
skipping to change at line 59 skipping to change at line 59
f16 = 7, // This is a 16 bit floating point value f16 = 7, // This is a 16 bit floating point value
f32 = 8, // This is a 32 bit floating point value f32 = 8, // This is a 32 bit floating point value
f64 = 9, // This is a 64 bit floating point value f64 = 9, // This is a 64 bit floating point value
f80 = 10, // This is a 80 bit floating point value f80 = 10, // This is a 80 bit floating point value
f128 = 11, // This is a 128 bit floating point value f128 = 11, // This is a 128 bit floating point value
ppcf128 = 12, // This is a PPC 128-bit floating point value ppcf128 = 12, // This is a PPC 128-bit floating point value
FIRST_FP_VALUETYPE = f16, FIRST_FP_VALUETYPE = f16,
LAST_FP_VALUETYPE = ppcf128, LAST_FP_VALUETYPE = ppcf128,
v2i8 = 13, // 2 x i8 v2i1 = 13, // 2 x i1
v4i8 = 14, // 4 x i8 v4i1 = 14, // 4 x i1
v8i8 = 15, // 8 x i8 v8i1 = 15, // 8 x i1
v16i8 = 16, // 16 x i8 v16i1 = 16, // 16 x i1
v32i8 = 17, // 32 x i8 v2i8 = 17, // 2 x i8
v2i16 = 18, // 2 x i16 v4i8 = 18, // 4 x i8
v4i16 = 19, // 4 x i16 v8i8 = 19, // 8 x i8
v8i16 = 20, // 8 x i16 v16i8 = 20, // 16 x i8
v16i16 = 21, // 16 x i16 v32i8 = 21, // 32 x i8
v2i32 = 22, // 2 x i32 v1i16 = 22, // 1 x i16
v4i32 = 23, // 4 x i32 v2i16 = 23, // 2 x i16
v8i32 = 24, // 8 x i32 v4i16 = 24, // 4 x i16
v1i64 = 25, // 1 x i64 v8i16 = 25, // 8 x i16
v2i64 = 26, // 2 x i64 v16i16 = 26, // 16 x i16
v4i64 = 27, // 4 x i64 v1i32 = 27, // 1 x i32
v8i64 = 28, // 8 x i64 v2i32 = 28, // 2 x i32
v4i32 = 29, // 4 x i32
v2f16 = 29, // 2 x f16 v8i32 = 30, // 8 x i32
v2f32 = 30, // 2 x f32 v16i32 = 31, // 16 x i32
v4f32 = 31, // 4 x f32 v1i64 = 32, // 1 x i64
v8f32 = 32, // 8 x f32 v2i64 = 33, // 2 x i64
v2f64 = 33, // 2 x f64 v4i64 = 34, // 4 x i64
v4f64 = 34, // 4 x f64 v8i64 = 35, // 8 x i64
v16i64 = 36, // 16 x i64
v2f16 = 37, // 2 x f16
v2f32 = 38, // 2 x f32
v4f32 = 39, // 4 x f32
v8f32 = 40, // 8 x f32
v2f64 = 41, // 2 x f64
v4f64 = 42, // 4 x f64
FIRST_VECTOR_VALUETYPE = v2i8, FIRST_VECTOR_VALUETYPE = v2i1,
LAST_VECTOR_VALUETYPE = v4f64, LAST_VECTOR_VALUETYPE = v4f64,
FIRST_INTEGER_VECTOR_VALUETYPE = v2i1,
LAST_INTEGER_VECTOR_VALUETYPE = v16i64,
FIRST_FP_VECTOR_VALUETYPE = v2f16, FIRST_FP_VECTOR_VALUETYPE = v2f16,
LAST_FP_VECTOR_VALUETYPE = v4f64, LAST_FP_VECTOR_VALUETYPE = v4f64,
x86mmx = 35, // This is an X86 MMX value x86mmx = 43, // This is an X86 MMX value
Glue = 36, // This glues nodes together during pre-RA sc hed Glue = 44, // This glues nodes together during pre-RA sc hed
isVoid = 37, // This has no value isVoid = 45, // This has no value
Untyped = 38, // This value takes a register, but has Untyped = 46, // This value takes a register, but has
// unspecified type. The register class // unspecified type. The register class
// will be determined by the opcode. // will be determined by the opcode.
LAST_VALUETYPE = 39, // This always remains at the end of the list . LAST_VALUETYPE = 47, // This always remains at the end of the list .
// This is the current maximum for LAST_VALUETYPE. // This is the current maximum for LAST_VALUETYPE.
// MVT::MAX_ALLOWED_VALUETYPE is used for asserts and to size bit vec tors // MVT::MAX_ALLOWED_VALUETYPE is used for asserts and to size bit vec tors
// This value must be a multiple of 32. // This value must be a multiple of 32.
MAX_ALLOWED_VALUETYPE = 64, MAX_ALLOWED_VALUETYPE = 64,
// Metadata - This is MDNode or MDString. // Metadata - This is MDNode or MDString.
Metadata = 250, Metadata = 250,
// iPTRAny - An int value the size of the pointer of the current // iPTRAny - An int value the size of the pointer of the current
skipping to change at line 156 skipping to change at line 166
bool operator<(const MVT& S) const { return SimpleTy < S.SimpleTy; } bool operator<(const MVT& S) const { return SimpleTy < S.SimpleTy; }
bool operator==(const MVT& S) const { return SimpleTy == S.SimpleTy; } bool operator==(const MVT& S) const { return SimpleTy == S.SimpleTy; }
bool operator!=(const MVT& S) const { return SimpleTy != S.SimpleTy; } bool operator!=(const MVT& S) const { return SimpleTy != S.SimpleTy; }
bool operator>=(const MVT& S) const { return SimpleTy >= S.SimpleTy; } bool operator>=(const MVT& S) const { return SimpleTy >= S.SimpleTy; }
bool operator<=(const MVT& S) const { return SimpleTy <= S.SimpleTy; } bool operator<=(const MVT& S) const { return SimpleTy <= S.SimpleTy; }
/// isFloatingPoint - Return true if this is a FP, or a vector FP type. /// isFloatingPoint - Return true if this is a FP, or a vector FP type.
bool isFloatingPoint() const { bool isFloatingPoint() const {
return ((SimpleTy >= MVT::FIRST_FP_VALUETYPE && return ((SimpleTy >= MVT::FIRST_FP_VALUETYPE &&
SimpleTy <= MVT::LAST_FP_VALUETYPE) || SimpleTy <= MVT::LAST_FP_VALUETYPE) ||
(SimpleTy >= MVT::FIRST_FP_VECTOR_VALUETYPE && (SimpleTy >= MVT::FIRST_FP_VECTOR_VALUETYPE &&
SimpleTy <= MVT::LAST_FP_VECTOR_VALUETYPE)); SimpleTy <= MVT::LAST_FP_VECTOR_VALUETYPE));
} }
/// isInteger - Return true if this is an integer, or a vector integer type. /// isInteger - Return true if this is an integer, or a vector integer type.
bool isInteger() const { bool isInteger() const {
return ((SimpleTy >= MVT::FIRST_INTEGER_VALUETYPE && return ((SimpleTy >= MVT::FIRST_INTEGER_VALUETYPE &&
SimpleTy <= MVT::LAST_INTEGER_VALUETYPE) || SimpleTy <= MVT::LAST_INTEGER_VALUETYPE) ||
(SimpleTy >= MVT::v2i8 && SimpleTy <= MVT::v8i64)); (SimpleTy >= MVT::FIRST_INTEGER_VECTOR_VALUETYPE &&
SimpleTy <= MVT::LAST_INTEGER_VECTOR_VALUETYPE));
} }
/// isVector - Return true if this is a vector value type. /// isVector - Return true if this is a vector value type.
bool isVector() const { bool isVector() const {
return (SimpleTy >= MVT::FIRST_VECTOR_VALUETYPE && return (SimpleTy >= MVT::FIRST_VECTOR_VALUETYPE &&
SimpleTy <= MVT::LAST_VECTOR_VALUETYPE); SimpleTy <= MVT::LAST_VECTOR_VALUETYPE);
} }
/// is16BitVector - Return true if this is a 16-bit vector type.
bool is16BitVector() const {
return (SimpleTy == MVT::v2i8 || SimpleTy == MVT::v1i16 ||
SimpleTy == MVT::v16i1);
}
/// is32BitVector - Return true if this is a 32-bit vector type.
bool is32BitVector() const {
return (SimpleTy == MVT::v4i8 || SimpleTy == MVT::v2i16 ||
SimpleTy == MVT::v1i32);
}
/// is64BitVector - Return true if this is a 64-bit vector type.
bool is64BitVector() const {
return (SimpleTy == MVT::v8i8 || SimpleTy == MVT::v4i16 ||
SimpleTy == MVT::v2i32 || SimpleTy == MVT::v1i64 ||
SimpleTy == MVT::v2f32);
}
/// is128BitVector - Return true if this is a 128-bit vector type.
bool is128BitVector() const {
return (SimpleTy == MVT::v16i8 || SimpleTy == MVT::v8i16 ||
SimpleTy == MVT::v4i32 || SimpleTy == MVT::v2i64 ||
SimpleTy == MVT::v4f32 || SimpleTy == MVT::v2f64);
}
/// is256BitVector - Return true if this is a 256-bit vector type.
bool is256BitVector() const {
return (SimpleTy == MVT::v8f32 || SimpleTy == MVT::v4f64 ||
SimpleTy == MVT::v32i8 || SimpleTy == MVT::v16i16 ||
SimpleTy == MVT::v8i32 || SimpleTy == MVT::v4i64);
}
/// is512BitVector - Return true if this is a 512-bit vector type.
bool is512BitVector() const {
return (SimpleTy == MVT::v8i64 || SimpleTy == MVT::v16i32);
}
/// is1024BitVector - Return true if this is a 1024-bit vector type.
bool is1024BitVector() const {
return (SimpleTy == MVT::v16i64);
}
/// isPow2VectorType - Returns true if the given vector is a power of 2 . /// isPow2VectorType - Returns true if the given vector is a power of 2 .
bool isPow2VectorType() const { bool isPow2VectorType() const {
unsigned NElts = getVectorNumElements(); unsigned NElts = getVectorNumElements();
return !(NElts & (NElts - 1)); return !(NElts & (NElts - 1));
} }
/// getPow2VectorType - Widens the length of the given vector MVT up to /// getPow2VectorType - Widens the length of the given vector MVT up to
/// the nearest power of 2 and returns that type. /// the nearest power of 2 and returns that type.
MVT getPow2VectorType() const { MVT getPow2VectorType() const {
if (isPow2VectorType()) if (isPow2VectorType())
skipping to change at line 199 skipping to change at line 253
/// getScalarType - If this is a vector type, return the element type, /// getScalarType - If this is a vector type, return the element type,
/// otherwise return this. /// otherwise return this.
MVT getScalarType() const { MVT getScalarType() const {
return isVector() ? getVectorElementType() : *this; return isVector() ? getVectorElementType() : *this;
} }
MVT getVectorElementType() const { MVT getVectorElementType() const {
switch (SimpleTy) { switch (SimpleTy) {
default: default:
return (MVT::SimpleValueType)(MVT::INVALID_SIMPLE_VALUE_TYPE); llvm_unreachable("Not a vector MVT!");
case v2i1 :
case v4i1 :
case v8i1 :
case v16i1: return i1;
case v2i8 : case v2i8 :
case v4i8 : case v4i8 :
case v8i8 : case v8i8 :
case v16i8: case v16i8:
case v32i8: return i8; case v32i8: return i8;
case v1i16:
case v2i16: case v2i16:
case v4i16: case v4i16:
case v8i16: case v8i16:
case v16i16: return i16; case v16i16: return i16;
case v1i32:
case v2i32: case v2i32:
case v4i32: case v4i32:
case v8i32: return i32; case v8i32:
case v16i32: return i32;
case v1i64: case v1i64:
case v2i64: case v2i64:
case v4i64: case v4i64:
case v8i64: return i64; case v8i64:
case v16i64: return i64;
case v2f16: return f16; case v2f16: return f16;
case v2f32: case v2f32:
case v4f32: case v4f32:
case v8f32: return f32; case v8f32: return f32;
case v2f64: case v2f64:
case v4f64: return f64; case v4f64: return f64;
} }
} }
unsigned getVectorNumElements() const { unsigned getVectorNumElements() const {
switch (SimpleTy) { switch (SimpleTy) {
default: default:
return ~0U; llvm_unreachable("Not a vector MVT!");
case v32i8: return 32; case v32i8: return 32;
case v16i1:
case v16i8: case v16i8:
case v16i16: return 16; case v16i16:
case v16i32:
case v16i64:return 16;
case v8i1:
case v8i8 : case v8i8 :
case v8i16: case v8i16:
case v8i32: case v8i32:
case v8i64: case v8i64:
case v8f32: return 8; case v8f32: return 8;
case v4i1:
case v4i8: case v4i8:
case v4i16: case v4i16:
case v4i32: case v4i32:
case v4i64: case v4i64:
case v4f32: case v4f32:
case v4f64: return 4; case v4f64: return 4;
case v2i1:
case v2i8: case v2i8:
case v2i16: case v2i16:
case v2i32: case v2i32:
case v2i64: case v2i64:
case v2f16: case v2f16:
case v2f32: case v2f32:
case v2f64: return 2; case v2f64: return 2;
case v1i16:
case v1i32:
case v1i64: return 1; case v1i64: return 1;
} }
} }
unsigned getSizeInBits() const { unsigned getSizeInBits() const {
switch (SimpleTy) { switch (SimpleTy) {
case iPTR: case iPTR:
llvm_unreachable("Value type size is target-dependent. Ask TLI."); llvm_unreachable("Value type size is target-dependent. Ask TLI.");
case iPTRAny: case iPTRAny:
case iAny: case iAny:
case fAny: case fAny:
llvm_unreachable("Value type is overloaded."); llvm_unreachable("Value type is overloaded.");
default: default:
llvm_unreachable("getSizeInBits called on extended MVT."); llvm_unreachable("getSizeInBits called on extended MVT.");
case i1 : return 1; case i1 : return 1;
case i8 : return 8; case v2i1: return 2;
case v4i1: return 4;
case i8 :
case v8i1: return 8;
case i16 : case i16 :
case f16: case f16:
case v2i8: return 16; case v16i1:
case v2i8:
case v1i16: return 16;
case f32 : case f32 :
case i32 : case i32 :
case v4i8: case v4i8:
case v2i16: case v2i16:
case v2f16: return 32; case v2f16:
case v1i32: return 32;
case x86mmx: case x86mmx:
case f64 : case f64 :
case i64 : case i64 :
case v8i8: case v8i8:
case v4i16: case v4i16:
case v2i32: case v2i32:
case v1i64: case v1i64:
case v2f32: return 64; case v2f32: return 64;
case f80 : return 80; case f80 : return 80;
case f128: case f128:
skipping to change at line 298 skipping to change at line 374
case v4i32: case v4i32:
case v2i64: case v2i64:
case v4f32: case v4f32:
case v2f64: return 128; case v2f64: return 128;
case v32i8: case v32i8:
case v16i16: case v16i16:
case v8i32: case v8i32:
case v4i64: case v4i64:
case v8f32: case v8f32:
case v4f64: return 256; case v4f64: return 256;
case v16i32:
case v8i64: return 512; case v8i64: return 512;
case v16i64:return 1024;
} }
} }
/// getStoreSize - Return the number of bytes overwritten by a store /// getStoreSize - Return the number of bytes overwritten by a store
/// of the specified value type. /// of the specified value type.
unsigned getStoreSize() const { unsigned getStoreSize() const {
return (getSizeInBits() + 7) / 8; return (getSizeInBits() + 7) / 8;
} }
/// getStoreSizeInBits - Return the number of bits overwritten by a sto re /// getStoreSizeInBits - Return the number of bits overwritten by a sto re
skipping to change at line 354 skipping to change at line 432
return MVT::i64; return MVT::i64;
case 128: case 128:
return MVT::i128; return MVT::i128;
} }
} }
static MVT getVectorVT(MVT VT, unsigned NumElements) { static MVT getVectorVT(MVT VT, unsigned NumElements) {
switch (VT.SimpleTy) { switch (VT.SimpleTy) {
default: default:
break; break;
case MVT::i1:
if (NumElements == 2) return MVT::v2i1;
if (NumElements == 4) return MVT::v4i1;
if (NumElements == 8) return MVT::v8i1;
if (NumElements == 16) return MVT::v16i1;
break;
case MVT::i8: case MVT::i8:
if (NumElements == 2) return MVT::v2i8; if (NumElements == 2) return MVT::v2i8;
if (NumElements == 4) return MVT::v4i8; if (NumElements == 4) return MVT::v4i8;
if (NumElements == 8) return MVT::v8i8; if (NumElements == 8) return MVT::v8i8;
if (NumElements == 16) return MVT::v16i8; if (NumElements == 16) return MVT::v16i8;
if (NumElements == 32) return MVT::v32i8; if (NumElements == 32) return MVT::v32i8;
break; break;
case MVT::i16: case MVT::i16:
if (NumElements == 1) return MVT::v1i16;
if (NumElements == 2) return MVT::v2i16; if (NumElements == 2) return MVT::v2i16;
if (NumElements == 4) return MVT::v4i16; if (NumElements == 4) return MVT::v4i16;
if (NumElements == 8) return MVT::v8i16; if (NumElements == 8) return MVT::v8i16;
if (NumElements == 16) return MVT::v16i16; if (NumElements == 16) return MVT::v16i16;
break; break;
case MVT::i32: case MVT::i32:
if (NumElements == 1) return MVT::v1i32;
if (NumElements == 2) return MVT::v2i32; if (NumElements == 2) return MVT::v2i32;
if (NumElements == 4) return MVT::v4i32; if (NumElements == 4) return MVT::v4i32;
if (NumElements == 8) return MVT::v8i32; if (NumElements == 8) return MVT::v8i32;
if (NumElements == 16) return MVT::v16i32;
break; break;
case MVT::i64: case MVT::i64:
if (NumElements == 1) return MVT::v1i64; if (NumElements == 1) return MVT::v1i64;
if (NumElements == 2) return MVT::v2i64; if (NumElements == 2) return MVT::v2i64;
if (NumElements == 4) return MVT::v4i64; if (NumElements == 4) return MVT::v4i64;
if (NumElements == 8) return MVT::v8i64; if (NumElements == 8) return MVT::v8i64;
if (NumElements == 16) return MVT::v16i64;
break; break;
case MVT::f16: case MVT::f16:
if (NumElements == 2) return MVT::v2f16; if (NumElements == 2) return MVT::v2f16;
break; break;
case MVT::f32: case MVT::f32:
if (NumElements == 2) return MVT::v2f32; if (NumElements == 2) return MVT::v2f32;
if (NumElements == 4) return MVT::v4f32; if (NumElements == 4) return MVT::v4f32;
if (NumElements == 8) return MVT::v8f32; if (NumElements == 8) return MVT::v8f32;
break; break;
case MVT::f64: case MVT::f64:
skipping to change at line 487 skipping to change at line 575
/// isInteger - Return true if this is an integer, or a vector integer type. /// isInteger - Return true if this is an integer, or a vector integer type.
bool isInteger() const { bool isInteger() const {
return isSimple() ? V.isInteger() : isExtendedInteger(); return isSimple() ? V.isInteger() : isExtendedInteger();
} }
/// isVector - Return true if this is a vector value type. /// isVector - Return true if this is a vector value type.
bool isVector() const { bool isVector() const {
return isSimple() ? V.isVector() : isExtendedVector(); return isSimple() ? V.isVector() : isExtendedVector();
} }
/// is16BitVector - Return true if this is a 16-bit vector type.
bool is16BitVector() const {
return isSimple() ? V.is16BitVector() : isExtended16BitVector();
}
/// is32BitVector - Return true if this is a 32-bit vector type.
bool is32BitVector() const {
return isSimple() ? V.is32BitVector() : isExtended32BitVector();
}
/// is64BitVector - Return true if this is a 64-bit vector type. /// is64BitVector - Return true if this is a 64-bit vector type.
bool is64BitVector() const { bool is64BitVector() const {
if (!isSimple()) return isSimple() ? V.is64BitVector() : isExtended64BitVector();
return isExtended64BitVector();
return (V == MVT::v8i8 || V==MVT::v4i16 || V==MVT::v2i32 ||
V == MVT::v1i64 || V==MVT::v2f32);
} }
/// is128BitVector - Return true if this is a 128-bit vector type. /// is128BitVector - Return true if this is a 128-bit vector type.
bool is128BitVector() const { bool is128BitVector() const {
if (!isSimple()) return isSimple() ? V.is128BitVector() : isExtended128BitVector();
return isExtended128BitVector();
return (V==MVT::v16i8 || V==MVT::v8i16 || V==MVT::v4i32 ||
V==MVT::v2i64 || V==MVT::v4f32 || V==MVT::v2f64);
} }
/// is256BitVector - Return true if this is a 256-bit vector type. /// is256BitVector - Return true if this is a 256-bit vector type.
inline bool is256BitVector() const { bool is256BitVector() const {
if (!isSimple()) return isSimple() ? V.is256BitVector() : isExtended256BitVector();
return isExtended256BitVector();
return (V == MVT::v8f32 || V == MVT::v4f64 || V == MVT::v32i8 ||
V == MVT::v16i16 || V == MVT::v8i32 || V == MVT::v4i64);
} }
/// is512BitVector - Return true if this is a 512-bit vector type. /// is512BitVector - Return true if this is a 512-bit vector type.
inline bool is512BitVector() const { bool is512BitVector() const {
return isSimple() ? (V == MVT::v8i64) : isExtended512BitVector(); return isSimple() ? V.is512BitVector() : isExtended512BitVector();
}
/// is1024BitVector - Return true if this is a 1024-bit vector type.
bool is1024BitVector() const {
return isSimple() ? V.is1024BitVector() : isExtended1024BitVector();
} }
/// isOverloaded - Return true if this is an overloaded type for TableG en. /// isOverloaded - Return true if this is an overloaded type for TableG en.
bool isOverloaded() const { bool isOverloaded() const {
return (V==MVT::iAny || V==MVT::fAny || V==MVT::vAny || V==MVT::iPTRA ny); return (V==MVT::iAny || V==MVT::fAny || V==MVT::vAny || V==MVT::iPTRA ny);
} }
/// isByteSized - Return true if the bit size is a multiple of 8. /// isByteSized - Return true if the bit size is a multiple of 8.
bool isByteSized() const { bool isByteSized() const {
return (getSizeInBits() & 7) == 0; return (getSizeInBits() & 7) == 0;
skipping to change at line 702 skipping to change at line 795
// Methods for handling the Extended-type case in functions above. // Methods for handling the Extended-type case in functions above.
// These are all out-of-line to prevent users of this header file // These are all out-of-line to prevent users of this header file
// from having a dependency on Type.h. // from having a dependency on Type.h.
EVT changeExtendedVectorElementTypeToInteger() const; EVT changeExtendedVectorElementTypeToInteger() const;
static EVT getExtendedIntegerVT(LLVMContext &C, unsigned BitWidth); static EVT getExtendedIntegerVT(LLVMContext &C, unsigned BitWidth);
static EVT getExtendedVectorVT(LLVMContext &C, EVT VT, static EVT getExtendedVectorVT(LLVMContext &C, EVT VT,
unsigned NumElements); unsigned NumElements);
bool isExtendedFloatingPoint() const; bool isExtendedFloatingPoint() const;
bool isExtendedInteger() const; bool isExtendedInteger() const;
bool isExtendedVector() const; bool isExtendedVector() const;
bool isExtended16BitVector() const;
bool isExtended32BitVector() const;
bool isExtended64BitVector() const; bool isExtended64BitVector() const;
bool isExtended128BitVector() const; bool isExtended128BitVector() const;
bool isExtended256BitVector() const; bool isExtended256BitVector() const;
bool isExtended512BitVector() const; bool isExtended512BitVector() const;
bool isExtended1024BitVector() const;
EVT getExtendedVectorElementType() const; EVT getExtendedVectorElementType() const;
unsigned getExtendedVectorNumElements() const; unsigned getExtendedVectorNumElements() const;
unsigned getExtendedSizeInBits() const; unsigned getExtendedSizeInBits() const;
}; };
} // End llvm namespace } // End llvm namespace
#endif #endif
 End of changes. 39 change blocks. 
56 lines changed or deleted 152 lines changed or added


 ValueTypes.td   ValueTypes.td 
skipping to change at line 36 skipping to change at line 36
def i32 : ValueType<32 , 4>; // 32-bit integer value def i32 : ValueType<32 , 4>; // 32-bit integer value
def i64 : ValueType<64 , 5>; // 64-bit integer value def i64 : ValueType<64 , 5>; // 64-bit integer value
def i128 : ValueType<128, 6>; // 128-bit integer value def i128 : ValueType<128, 6>; // 128-bit integer value
def f16 : ValueType<16 , 7>; // 32-bit floating point value def f16 : ValueType<16 , 7>; // 32-bit floating point value
def f32 : ValueType<32 , 8>; // 32-bit floating point value def f32 : ValueType<32 , 8>; // 32-bit floating point value
def f64 : ValueType<64 , 9>; // 64-bit floating point value def f64 : ValueType<64 , 9>; // 64-bit floating point value
def f80 : ValueType<80 , 10>; // 80-bit floating point value def f80 : ValueType<80 , 10>; // 80-bit floating point value
def f128 : ValueType<128, 11>; // 128-bit floating point value def f128 : ValueType<128, 11>; // 128-bit floating point value
def ppcf128: ValueType<128, 12>; // PPC 128-bit floating point value def ppcf128: ValueType<128, 12>; // PPC 128-bit floating point value
def v2i8 : ValueType<16 , 13>; // 2 x i8 vector value def v2i1 : ValueType<2 , 13>; // 2 x i1 vector value
def v4i8 : ValueType<32 , 14>; // 4 x i8 vector value def v4i1 : ValueType<4 , 14>; // 4 x i1 vector value
def v8i8 : ValueType<64 , 15>; // 8 x i8 vector value def v8i1 : ValueType<8 , 15>; // 8 x i1 vector value
def v16i8 : ValueType<128, 16>; // 16 x i8 vector value def v16i1 : ValueType<16, 16>; // 16 x i1 vector value
def v32i8 : ValueType<256, 17>; // 32 x i8 vector value def v2i8 : ValueType<16 , 17>; // 2 x i8 vector value
def v2i16 : ValueType<32 , 18>; // 2 x i16 vector value def v4i8 : ValueType<32 , 18>; // 4 x i8 vector value
def v4i16 : ValueType<64 , 19>; // 4 x i16 vector value def v8i8 : ValueType<64 , 19>; // 8 x i8 vector value
def v8i16 : ValueType<128, 20>; // 8 x i16 vector value def v16i8 : ValueType<128, 20>; // 16 x i8 vector value
def v16i16 : ValueType<256, 21>; // 16 x i16 vector value def v32i8 : ValueType<256, 21>; // 32 x i8 vector value
def v2i32 : ValueType<64 , 22>; // 2 x i32 vector value def v1i16 : ValueType<16 , 22>; // 1 x i16 vector value
def v4i32 : ValueType<128, 23>; // 4 x i32 vector value def v2i16 : ValueType<32 , 23>; // 2 x i16 vector value
def v8i32 : ValueType<256, 24>; // 8 x i32 vector value def v4i16 : ValueType<64 , 24>; // 4 x i16 vector value
def v1i64 : ValueType<64 , 25>; // 1 x i64 vector value def v8i16 : ValueType<128, 25>; // 8 x i16 vector value
def v2i64 : ValueType<128, 26>; // 2 x i64 vector value def v16i16 : ValueType<256, 26>; // 16 x i16 vector value
def v4i64 : ValueType<256, 27>; // 4 x i64 vector value def v1i32 : ValueType<32 , 27>; // 1 x i32 vector value
def v8i64 : ValueType<512, 28>; // 8 x i64 vector value def v2i32 : ValueType<64 , 28>; // 2 x i32 vector value
def v4i32 : ValueType<128, 29>; // 4 x i32 vector value
def v2f16 : ValueType<32 , 29>; // 2 x f16 vector value def v8i32 : ValueType<256, 30>; // 8 x i32 vector value
def v2f32 : ValueType<64 , 30>; // 2 x f32 vector value def v16i32 : ValueType<512, 31>; // 16 x i32 vector value
def v4f32 : ValueType<128, 31>; // 4 x f32 vector value def v1i64 : ValueType<64 , 32>; // 1 x i64 vector value
def v8f32 : ValueType<256, 32>; // 8 x f32 vector value def v2i64 : ValueType<128, 33>; // 2 x i64 vector value
def v2f64 : ValueType<128, 33>; // 2 x f64 vector value def v4i64 : ValueType<256, 34>; // 4 x i64 vector value
def v4f64 : ValueType<256, 34>; // 4 x f64 vector value def v8i64 : ValueType<512, 35>; // 8 x i64 vector value
def v16i64 : ValueType<1024,36>; // 16 x i64 vector value
def x86mmx : ValueType<64 , 35>; // X86 MMX value
def FlagVT : ValueType<0 , 36>; // Pre-RA sched glue def v2f16 : ValueType<32 , 37>; // 2 x f16 vector value
def isVoid : ValueType<0 , 37>; // Produces no value def v2f32 : ValueType<64 , 38>; // 2 x f32 vector value
def untyped: ValueType<8 , 38>; // Produces an untyped value def v4f32 : ValueType<128, 39>; // 4 x f32 vector value
def v8f32 : ValueType<256, 40>; // 8 x f32 vector value
def v2f64 : ValueType<128, 41>; // 2 x f64 vector value
def v4f64 : ValueType<256, 42>; // 4 x f64 vector value
def x86mmx : ValueType<64 , 43>; // X86 MMX value
def FlagVT : ValueType<0 , 44>; // Pre-RA sched glue
def isVoid : ValueType<0 , 45>; // Produces no value
def untyped: ValueType<8 , 46>; // Produces an untyped value
def MetadataVT: ValueType<0, 250>; // Metadata def MetadataVT: ValueType<0, 250>; // Metadata
// Pseudo valuetype mapped to the current pointer size to any address space . // Pseudo valuetype mapped to the current pointer size to any address space .
// Should only be used in TableGen. // Should only be used in TableGen.
def iPTRAny : ValueType<0, 251>; def iPTRAny : ValueType<0, 251>;
// Pseudo valuetype to represent "vector of any size" // Pseudo valuetype to represent "vector of any size"
def vAny : ValueType<0 , 252>; def vAny : ValueType<0 , 252>;
 End of changes. 1 change blocks. 
28 lines changed or deleted 36 lines changed or added


 VariadicFunction.h   VariadicFunction.h 
skipping to change at line 209 skipping to change at line 209
ResultT (*Func)(Param0T, Param1T, ArrayRef<const ArgT *>)> ResultT (*Func)(Param0T, Param1T, ArrayRef<const ArgT *>)>
struct VariadicFunction2 { struct VariadicFunction2 {
ResultT operator()(Param0T P0, Param1T P1) const { ResultT operator()(Param0T P0, Param1T P1) const {
return Func(P0, P1, ArrayRef<const ArgT *>()); return Func(P0, P1, ArrayRef<const ArgT *>());
} }
#define LLVM_DEFINE_OVERLOAD(N) \ #define LLVM_DEFINE_OVERLOAD(N) \
ResultT operator()(Param0T P0, Param1T P1, \ ResultT operator()(Param0T P0, Param1T P1, \
LLVM_COMMA_JOIN ## N(const ArgT &A)) const { \ LLVM_COMMA_JOIN ## N(const ArgT &A)) const { \
const ArgT *const Args[] = { LLVM_COMMA_JOIN ## N(&A) }; \ const ArgT *const Args[] = { LLVM_COMMA_JOIN ## N(&A) }; \
return Func(P0, P1, makeAraryRef(Args)); \ return Func(P0, P1, makeArrayRef(Args)); \
} }
LLVM_DEFINE_OVERLOAD(1) LLVM_DEFINE_OVERLOAD(1)
LLVM_DEFINE_OVERLOAD(2) LLVM_DEFINE_OVERLOAD(2)
LLVM_DEFINE_OVERLOAD(3) LLVM_DEFINE_OVERLOAD(3)
LLVM_DEFINE_OVERLOAD(4) LLVM_DEFINE_OVERLOAD(4)
LLVM_DEFINE_OVERLOAD(5) LLVM_DEFINE_OVERLOAD(5)
LLVM_DEFINE_OVERLOAD(6) LLVM_DEFINE_OVERLOAD(6)
LLVM_DEFINE_OVERLOAD(7) LLVM_DEFINE_OVERLOAD(7)
LLVM_DEFINE_OVERLOAD(8) LLVM_DEFINE_OVERLOAD(8)
LLVM_DEFINE_OVERLOAD(9) LLVM_DEFINE_OVERLOAD(9)
 End of changes. 1 change blocks. 
1 lines changed or deleted 1 lines changed or added


 Vectorize.h   Vectorize.h 
skipping to change at line 31 skipping to change at line 31
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
/// @brief Vectorize configuration. /// @brief Vectorize configuration.
struct VectorizeConfig { struct VectorizeConfig {
//===-------------------------------------------------------------------- ===// //===-------------------------------------------------------------------- ===//
// Target architecture related parameters // Target architecture related parameters
/// @brief The size of the native vector registers. /// @brief The size of the native vector registers.
unsigned VectorBits; unsigned VectorBits;
/// @brief Vectorize boolean values.
bool VectorizeBools;
/// @brief Vectorize integer values. /// @brief Vectorize integer values.
bool VectorizeInts; bool VectorizeInts;
/// @brief Vectorize floating-point values. /// @brief Vectorize floating-point values.
bool VectorizeFloats; bool VectorizeFloats;
/// @brief Vectorize pointer values. /// @brief Vectorize pointer values.
bool VectorizePointers; bool VectorizePointers;
/// @brief Vectorize casting (conversion) operations. /// @brief Vectorize casting (conversion) operations.
skipping to change at line 52 skipping to change at line 55
/// @brief Vectorize floating-point math intrinsics. /// @brief Vectorize floating-point math intrinsics.
bool VectorizeMath; bool VectorizeMath;
/// @brief Vectorize the fused-multiply-add intrinsic. /// @brief Vectorize the fused-multiply-add intrinsic.
bool VectorizeFMA; bool VectorizeFMA;
/// @brief Vectorize select instructions. /// @brief Vectorize select instructions.
bool VectorizeSelect; bool VectorizeSelect;
/// @brief Vectorize comparison instructions.
bool VectorizeCmp;
/// @brief Vectorize getelementptr instructions. /// @brief Vectorize getelementptr instructions.
bool VectorizeGEP; bool VectorizeGEP;
/// @brief Vectorize loads and stores. /// @brief Vectorize loads and stores.
bool VectorizeMemOps; bool VectorizeMemOps;
/// @brief Only generate aligned loads and stores. /// @brief Only generate aligned loads and stores.
bool AlignedOnly; bool AlignedOnly;
//===-------------------------------------------------------------------- ===// //===-------------------------------------------------------------------- ===//
skipping to change at line 83 skipping to change at line 89
/// @brief Replicating one element to a pair breaks the chain. /// @brief Replicating one element to a pair breaks the chain.
bool SplatBreaksChain; bool SplatBreaksChain;
/// @brief The maximum number of pairable instructions per group. /// @brief The maximum number of pairable instructions per group.
unsigned MaxInsts; unsigned MaxInsts;
/// @brief The maximum number of pairing iterations. /// @brief The maximum number of pairing iterations.
unsigned MaxIter; unsigned MaxIter;
/// @brief Don't try to form odd-length vectors.
bool Pow2LenOnly;
/// @brief Don't boost the chain-depth contribution of loads and stores. /// @brief Don't boost the chain-depth contribution of loads and stores.
bool NoMemOpBoost; bool NoMemOpBoost;
/// @brief Use a fast instruction dependency analysis. /// @brief Use a fast instruction dependency analysis.
bool FastDep; bool FastDep;
/// @brief Initialize the VectorizeConfig from command line options. /// @brief Initialize the VectorizeConfig from command line options.
VectorizeConfig(); VectorizeConfig();
}; };
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// //
// BBVectorize - A basic-block vectorization pass. // BBVectorize - A basic-block vectorization pass.
// //
BasicBlockPass * BasicBlockPass *
createBBVectorizePass(const VectorizeConfig &C = VectorizeConfig()); createBBVectorizePass(const VectorizeConfig &C = VectorizeConfig());
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
//
// LoopVectorize - Create a loop vectorization pass.
//
Pass * createLoopVectorizePass();
//===----------------------------------------------------------------------
===//
/// @brief Vectorize the BasicBlock. /// @brief Vectorize the BasicBlock.
/// ///
/// @param BB The BasicBlock to be vectorized /// @param BB The BasicBlock to be vectorized
/// @param P The current running pass, should require AliasAnalysis and /// @param P The current running pass, should require AliasAnalysis and
/// ScalarEvolution. After the vectorization, AliasAnalysis, /// ScalarEvolution. After the vectorization, AliasAnalysis,
/// ScalarEvolution and CFG are preserved. /// ScalarEvolution and CFG are preserved.
/// ///
/// @return True if the BB is changed, false otherwise. /// @return True if the BB is changed, false otherwise.
/// ///
bool vectorizeBasicBlock(Pass *P, BasicBlock &BB, bool vectorizeBasicBlock(Pass *P, BasicBlock &BB,
 End of changes. 4 change blocks. 
0 lines changed or deleted 16 lines changed or added


 YAMLParser.h   YAMLParser.h 
skipping to change at line 133 skipping to change at line 133
void setSourceRange(SMRange SR) { SourceRange = SR; } void setSourceRange(SMRange SR) { SourceRange = SR; }
// These functions forward to Document and Scanner. // These functions forward to Document and Scanner.
Token &peekNext(); Token &peekNext();
Token getNext(); Token getNext();
Node *parseBlockNode(); Node *parseBlockNode();
BumpPtrAllocator &getAllocator(); BumpPtrAllocator &getAllocator();
void setError(const Twine &Message, Token &Location) const; void setError(const Twine &Message, Token &Location) const;
bool failed() const; bool failed() const;
virtual void skip() {}; virtual void skip() {}
unsigned int getType() const { return TypeID; } unsigned int getType() const { return TypeID; }
static inline bool classof(const Node *) { return true; }
void *operator new ( size_t Size void *operator new ( size_t Size
, BumpPtrAllocator &Alloc , BumpPtrAllocator &Alloc
, size_t Alignment = 16) throw() { , size_t Alignment = 16) throw() {
return Alloc.Allocate(Size, Alignment); return Alloc.Allocate(Size, Alignment);
} }
void operator delete(void *Ptr, BumpPtrAllocator &Alloc, size_t) throw() { void operator delete(void *Ptr, BumpPtrAllocator &Alloc, size_t) throw() {
Alloc.Deallocate(Ptr); Alloc.Deallocate(Ptr);
} }
skipping to change at line 169 skipping to change at line 168
}; };
/// @brief A null value. /// @brief A null value.
/// ///
/// Example: /// Example:
/// !!null null /// !!null null
class NullNode : public Node { class NullNode : public Node {
public: public:
NullNode(OwningPtr<Document> &D) : Node(NK_Null, D, StringRef()) {} NullNode(OwningPtr<Document> &D) : Node(NK_Null, D, StringRef()) {}
static inline bool classof(const NullNode *) { return true; }
static inline bool classof(const Node *N) { static inline bool classof(const Node *N) {
return N->getType() == NK_Null; return N->getType() == NK_Null;
} }
}; };
/// @brief A scalar node is an opaque datum that can be presented as a /// @brief A scalar node is an opaque datum that can be presented as a
/// series of zero or more Unicode scalar values. /// series of zero or more Unicode scalar values.
/// ///
/// Example: /// Example:
/// Adena /// Adena
skipping to change at line 202 skipping to change at line 200
// utf8). // utf8).
StringRef getRawValue() const { return Value; } StringRef getRawValue() const { return Value; }
/// @brief Gets the value of this node as a StringRef. /// @brief Gets the value of this node as a StringRef.
/// ///
/// @param Storage is used to store the content of the returned StringRef iff /// @param Storage is used to store the content of the returned StringRef iff
/// it requires any modification from how it appeared in the sourc e. /// it requires any modification from how it appeared in the sourc e.
/// This happens with escaped characters and multi-line literals. /// This happens with escaped characters and multi-line literals.
StringRef getValue(SmallVectorImpl<char> &Storage) const; StringRef getValue(SmallVectorImpl<char> &Storage) const;
static inline bool classof(const ScalarNode *) { return true; }
static inline bool classof(const Node *N) { static inline bool classof(const Node *N) {
return N->getType() == NK_Scalar; return N->getType() == NK_Scalar;
} }
private: private:
StringRef Value; StringRef Value;
StringRef unescapeDoubleQuoted( StringRef UnquotedValue StringRef unescapeDoubleQuoted( StringRef UnquotedValue
, StringRef::size_type Start , StringRef::size_type Start
, SmallVectorImpl<char> &Storage) const; , SmallVectorImpl<char> &Storage) const;
skipping to change at line 244 skipping to change at line 241
/// @returns The key, or nullptr if failed() == true. /// @returns The key, or nullptr if failed() == true.
Node *getKey(); Node *getKey();
/// @brief Parse and return the value. /// @brief Parse and return the value.
/// ///
/// This may be called multiple times. /// This may be called multiple times.
/// ///
/// @returns The value, or nullptr if failed() == true. /// @returns The value, or nullptr if failed() == true.
Node *getValue(); Node *getValue();
virtual void skip() { virtual void skip() LLVM_OVERRIDE {
getKey()->skip(); getKey()->skip();
getValue()->skip(); getValue()->skip();
} }
static inline bool classof(const KeyValueNode *) { return true; }
static inline bool classof(const Node *N) { static inline bool classof(const Node *N) {
return N->getType() == NK_KeyValue; return N->getType() == NK_KeyValue;
} }
private: private:
Node *Key; Node *Key;
Node *Value; Node *Value;
}; };
/// @brief This is an iterator abstraction over YAML collections shared by both /// @brief This is an iterator abstraction over YAML collections shared by both
skipping to change at line 339 skipping to change at line 335
/// This parses the YAML stream as increment() is called. /// This parses the YAML stream as increment() is called.
/// ///
/// Example: /// Example:
/// Name: _main /// Name: _main
/// Scope: Global /// Scope: Global
class MappingNode : public Node { class MappingNode : public Node {
public: public:
enum MappingType { enum MappingType {
MT_Block, MT_Block,
MT_Flow, MT_Flow,
MT_Inline //< An inline mapping node is used for "[key: value]". MT_Inline ///< An inline mapping node is used for "[key: value]".
}; };
MappingNode(OwningPtr<Document> &D, StringRef Anchor, MappingType MT) MappingNode(OwningPtr<Document> &D, StringRef Anchor, MappingType MT)
: Node(NK_Mapping, D, Anchor) : Node(NK_Mapping, D, Anchor)
, Type(MT) , Type(MT)
, IsAtBeginning(true) , IsAtBeginning(true)
, IsAtEnd(false) , IsAtEnd(false)
, CurrentEntry(0) , CurrentEntry(0)
{} {}
skipping to change at line 361 skipping to change at line 357
typedef basic_collection_iterator<MappingNode, KeyValueNode> iterator; typedef basic_collection_iterator<MappingNode, KeyValueNode> iterator;
template <class T> friend typename T::iterator yaml::begin(T &); template <class T> friend typename T::iterator yaml::begin(T &);
template <class T> friend void yaml::skip(T &); template <class T> friend void yaml::skip(T &);
iterator begin() { iterator begin() {
return yaml::begin(*this); return yaml::begin(*this);
} }
iterator end() { return iterator(); } iterator end() { return iterator(); }
virtual void skip() { virtual void skip() LLVM_OVERRIDE {
yaml::skip(*this); yaml::skip(*this);
} }
static inline bool classof(const MappingNode *) { return true; }
static inline bool classof(const Node *N) { static inline bool classof(const Node *N) {
return N->getType() == NK_Mapping; return N->getType() == NK_Mapping;
} }
private: private:
MappingType Type; MappingType Type;
bool IsAtBeginning; bool IsAtBeginning;
bool IsAtEnd; bool IsAtEnd;
KeyValueNode *CurrentEntry; KeyValueNode *CurrentEntry;
skipping to change at line 424 skipping to change at line 419
template <class T> friend void yaml::skip(T &); template <class T> friend void yaml::skip(T &);
void increment(); void increment();
iterator begin() { iterator begin() {
return yaml::begin(*this); return yaml::begin(*this);
} }
iterator end() { return iterator(); } iterator end() { return iterator(); }
virtual void skip() { virtual void skip() LLVM_OVERRIDE {
yaml::skip(*this); yaml::skip(*this);
} }
static inline bool classof(const SequenceNode *) { return true; }
static inline bool classof(const Node *N) { static inline bool classof(const Node *N) {
return N->getType() == NK_Sequence; return N->getType() == NK_Sequence;
} }
private: private:
SequenceType SeqType; SequenceType SeqType;
bool IsAtBeginning; bool IsAtBeginning;
bool IsAtEnd; bool IsAtEnd;
bool WasPreviousTokenFlowEntry; bool WasPreviousTokenFlowEntry;
Node *CurrentEntry; Node *CurrentEntry;
skipping to change at line 453 skipping to change at line 447
/// Example: /// Example:
/// *AnchorName /// *AnchorName
class AliasNode : public Node { class AliasNode : public Node {
public: public:
AliasNode(OwningPtr<Document> &D, StringRef Val) AliasNode(OwningPtr<Document> &D, StringRef Val)
: Node(NK_Alias, D, StringRef()), Name(Val) {} : Node(NK_Alias, D, StringRef()), Name(Val) {}
StringRef getName() const { return Name; } StringRef getName() const { return Name; }
Node *getTarget(); Node *getTarget();
static inline bool classof(const ScalarNode *) { return true; }
static inline bool classof(const Node *N) { static inline bool classof(const Node *N) {
return N->getType() == NK_Alias; return N->getType() == NK_Alias;
} }
private: private:
StringRef Name; StringRef Name;
}; };
/// @brief A YAML Stream is a sequence of Documents. A document contains a root /// @brief A YAML Stream is a sequence of Documents. A document contains a root
/// node. /// node.
skipping to change at line 516 skipping to change at line 509
/// @brief Parse %BLAH directives and return true if any were encountered . /// @brief Parse %BLAH directives and return true if any were encountered .
bool parseDirectives(); bool parseDirectives();
/// @brief Consume the next token and error if it is not \a TK. /// @brief Consume the next token and error if it is not \a TK.
bool expectToken(int TK); bool expectToken(int TK);
}; };
/// @brief Iterator abstraction for Documents over a Stream. /// @brief Iterator abstraction for Documents over a Stream.
class document_iterator { class document_iterator {
public: public:
document_iterator() : Doc(NullDoc) {} document_iterator() : Doc(0) {}
document_iterator(OwningPtr<Document> &D) : Doc(D) {} document_iterator(OwningPtr<Document> &D) : Doc(&D) {}
bool operator ==(const document_iterator &Other) { bool operator ==(const document_iterator &Other) {
return Doc == Other.Doc; if (isAtEnd() || Other.isAtEnd())
return isAtEnd() && Other.isAtEnd();
return *Doc == *Other.Doc;
} }
bool operator !=(const document_iterator &Other) { bool operator !=(const document_iterator &Other) {
return !(*this == Other); return !(*this == Other);
} }
document_iterator operator ++() { document_iterator operator ++() {
if (!Doc->skip()) { assert(Doc != 0 && "incrementing iterator past the end.");
Doc.reset(0); if (!(*Doc)->skip()) {
Doc->reset(0);
} else { } else {
Stream &S = Doc->stream; Stream &S = (*Doc)->stream;
Doc.reset(new Document(S)); Doc->reset(new Document(S));
} }
return *this; return *this;
} }
Document &operator *() { Document &operator *() {
return *Doc; return *Doc->get();
} }
OwningPtr<Document> &operator ->() { OwningPtr<Document> &operator ->() {
return Doc; return *Doc;
} }
private: private:
static OwningPtr<Document> NullDoc; bool isAtEnd() const {
OwningPtr<Document> &Doc; return Doc == 0 || *Doc == 0;
}
OwningPtr<Document> *Doc;
}; };
} }
} }
#endif #endif
 End of changes. 19 change blocks. 
23 lines changed or deleted 23 lines changed or added


 circular_raw_ostream.h   circular_raw_ostream.h 
skipping to change at line 84 skipping to change at line 84
void flushBuffer(void) { void flushBuffer(void) {
if (Filled) if (Filled)
// Write the older portion of the buffer. // Write the older portion of the buffer.
TheStream->write(Cur, BufferArray + BufferSize - Cur); TheStream->write(Cur, BufferArray + BufferSize - Cur);
// Write the newer portion of the buffer. // Write the newer portion of the buffer.
TheStream->write(BufferArray, Cur - BufferArray); TheStream->write(BufferArray, Cur - BufferArray);
Cur = BufferArray; Cur = BufferArray;
Filled = false; Filled = false;
} }
virtual void write_impl(const char *Ptr, size_t Size); virtual void write_impl(const char *Ptr, size_t Size) LLVM_OVERRIDE;
/// current_pos - Return the current position within the stream, /// current_pos - Return the current position within the stream,
/// not counting the bytes currently in the buffer. /// not counting the bytes currently in the buffer.
/// ///
virtual uint64_t current_pos() const { virtual uint64_t current_pos() const LLVM_OVERRIDE {
// This has the same effect as calling TheStream.current_pos(), // This has the same effect as calling TheStream.current_pos(),
// but that interface is private. // but that interface is private.
return TheStream->tell() - TheStream->GetNumBytesInBuffer(); return TheStream->tell() - TheStream->GetNumBytesInBuffer();
} }
public: public:
/// circular_raw_ostream - Construct an optionally /// circular_raw_ostream - Construct an optionally
/// circular-buffered stream, handing it an underlying stream to /// circular-buffered stream, handing it an underlying stream to
/// do the "real" output. /// do the "real" output.
/// ///
 End of changes. 2 change blocks. 
2 lines changed or deleted 2 lines changed or added


 config.h   config.h 
/* include/llvm/Config/config.h. Generated from config.h.in by configure. */ /* include/llvm/Config/config.h. Generated from config.h.in by configure. */
/* include/llvm/Config/config.h.in. Generated from autoconf/configure.ac b y autoheader. */ /* include/llvm/Config/config.h.in. Generated from autoconf/configure.ac b y autoheader. */
#ifndef CONFIG_H #ifndef CONFIG_H
#define CONFIG_H #define CONFIG_H
/* Bug report URL. */ /* Bug report URL. */
#define BUG_REPORT_URL "http://llvm.org/bugs/" #define BUG_REPORT_URL "http://llvm.org/bugs/"
/* Define if we have libxml2 */
#define CLANG_HAVE_LIBXML 1
/* Relative directory for resource files */ /* Relative directory for resource files */
#define CLANG_RESOURCE_DIR "" #define CLANG_RESOURCE_DIR ""
/* Directories clang will search for headers */ /* Directories clang will search for headers */
#define C_INCLUDE_DIRS "" #define C_INCLUDE_DIRS ""
/* Default <path> to all compiler invocations for --sysroot=<path>. */ /* Default <path> to all compiler invocations for --sysroot=<path>. */
#define DEFAULT_SYSROOT "" #define DEFAULT_SYSROOT ""
/* Define if you want backtraces on crash */
#define ENABLE_BACKTRACES 1
/* Define if position independent code is enabled */ /* Define if position independent code is enabled */
#define ENABLE_PIC 1 #define ENABLE_PIC 1
/* Define if timestamp information (e.g., __DATE___) is allowed */ /* Define if timestamp information (e.g., __DATE__) is allowed */
#define ENABLE_TIMESTAMPS 1 #define ENABLE_TIMESTAMPS 1
/* Directory where gcc is installed. */ /* Directory where gcc is installed. */
#define GCC_INSTALL_PREFIX "" #define GCC_INSTALL_PREFIX ""
/* Define to 1 if you have the `arc4random' function. */
/* #undef HAVE_ARC4RANDOM */
/* Define to 1 if you have the `argz_append' function. */ /* Define to 1 if you have the `argz_append' function. */
#define HAVE_ARGZ_APPEND 1 #define HAVE_ARGZ_APPEND 1
/* Define to 1 if you have the `argz_create_sep' function. */ /* Define to 1 if you have the `argz_create_sep' function. */
#define HAVE_ARGZ_CREATE_SEP 1 #define HAVE_ARGZ_CREATE_SEP 1
/* Define to 1 if you have the <argz.h> header file. */ /* Define to 1 if you have the <argz.h> header file. */
#define HAVE_ARGZ_H 1 #define HAVE_ARGZ_H 1
/* Define to 1 if you have the `argz_insert' function. */ /* Define to 1 if you have the `argz_insert' function. */
skipping to change at line 530 skipping to change at line 539
/* Have host's __umoddi3 */ /* Have host's __umoddi3 */
/* #undef HAVE___UMODDI3 */ /* #undef HAVE___UMODDI3 */
/* Have host's ___chkstk */ /* Have host's ___chkstk */
/* #undef HAVE____CHKSTK */ /* #undef HAVE____CHKSTK */
/* Linker version detected at compile time. */ /* Linker version detected at compile time. */
#define HOST_LINK_VERSION "2.21.52.0.2.20110610" #define HOST_LINK_VERSION "2.21.52.0.2.20110610"
/* Installation directory for binary executables */ /* Installation directory for binary executables */
#define LLVM_BINDIR "/home/ut/testing/llvm/3.1/bin" #define LLVM_BINDIR "/home/ut/testing/llvm/3.2/bin"
/* Time at which LLVM was configured */ /* Time at which LLVM was configured */
#define LLVM_CONFIGTIME "Wed Jan 9 15:19:52 MSK 2013" #define LLVM_CONFIGTIME "Wed Jan 9 12:07:05 MSK 2013"
/* Installation directory for data files */ /* Installation directory for data files */
#define LLVM_DATADIR "/home/ut/testing/llvm/3.1/share/llvm" #define LLVM_DATADIR "/home/ut/testing/llvm/3.2/share/llvm"
/* Target triple LLVM will generate code for by default */ /* Target triple LLVM will generate code for by default */
#define LLVM_DEFAULT_TARGET_TRIPLE "i686-pc-linux-gnu" #define LLVM_DEFAULT_TARGET_TRIPLE "i686-pc-linux-gnu"
/* Installation directory for documentation */ /* Installation directory for documentation */
#define LLVM_DOCSDIR "/home/ut/testing/llvm/3.1/share/doc/llvm" #define LLVM_DOCSDIR "/home/ut/testing/llvm/3.2/share/doc/llvm"
/* Define if threads enabled */ /* Define if threads enabled */
#define LLVM_ENABLE_THREADS 1 #define LLVM_ENABLE_THREADS 1
/* Installation directory for config files */ /* Installation directory for config files */
#define LLVM_ETCDIR "/home/ut/testing/llvm/3.1/etc/llvm" #define LLVM_ETCDIR "/home/ut/testing/llvm/3.2/etc/llvm"
/* Has gcc/MSVC atomic intrinsics */ /* Has gcc/MSVC atomic intrinsics */
#define LLVM_HAS_ATOMICS 1 #define LLVM_HAS_ATOMICS 1
/* Host triple LLVM will be executed on */
#define LLVM_HOSTTRIPLE "i686-pc-linux-gnu"
/* Installation directory for include files */ /* Installation directory for include files */
#define LLVM_INCLUDEDIR "/home/ut/testing/llvm/3.1/include" #define LLVM_INCLUDEDIR "/home/ut/testing/llvm/3.2/include"
/* Installation directory for .info files */ /* Installation directory for .info files */
#define LLVM_INFODIR "/home/ut/testing/llvm/3.1/info" #define LLVM_INFODIR "/home/ut/testing/llvm/3.2/info"
/* Installation directory for libraries */ /* Installation directory for libraries */
#define LLVM_LIBDIR "/home/ut/testing/llvm/3.1/lib" #define LLVM_LIBDIR "/home/ut/testing/llvm/3.2/lib"
/* Installation directory for man pages */ /* Installation directory for man pages */
#define LLVM_MANDIR "/home/ut/testing/llvm/3.1/man" #define LLVM_MANDIR "/home/ut/testing/llvm/3.2/man"
/* LLVM architecture name for the native architecture, if available */ /* LLVM architecture name for the native architecture, if available */
#define LLVM_NATIVE_ARCH X86 #define LLVM_NATIVE_ARCH X86
/* LLVM name for the native AsmParser init function, if available */ /* LLVM name for the native AsmParser init function, if available */
#define LLVM_NATIVE_ASMPARSER LLVMInitializeX86AsmParser #define LLVM_NATIVE_ASMPARSER LLVMInitializeX86AsmParser
/* LLVM name for the native AsmPrinter init function, if available */ /* LLVM name for the native AsmPrinter init function, if available */
#define LLVM_NATIVE_ASMPRINTER LLVMInitializeX86AsmPrinter #define LLVM_NATIVE_ASMPRINTER LLVMInitializeX86AsmPrinter
skipping to change at line 620 skipping to change at line 632
/* Define to path to neato program if found or 'echo neato' otherwise */ /* Define to path to neato program if found or 'echo neato' otherwise */
#define LLVM_PATH_NEATO "/usr/bin/neato" #define LLVM_PATH_NEATO "/usr/bin/neato"
/* Define to path to twopi program if found or 'echo twopi' otherwise */ /* Define to path to twopi program if found or 'echo twopi' otherwise */
#define LLVM_PATH_TWOPI "/usr/bin/twopi" #define LLVM_PATH_TWOPI "/usr/bin/twopi"
/* Define to path to xdot.py program if found or 'echo xdot.py' otherwise * / /* Define to path to xdot.py program if found or 'echo xdot.py' otherwise * /
/* #undef LLVM_PATH_XDOT_PY */ /* #undef LLVM_PATH_XDOT_PY */
/* Installation prefix directory */ /* Installation prefix directory */
#define LLVM_PREFIX "/home/ut/testing/llvm/3.1" #define LLVM_PREFIX "/home/ut/testing/llvm/3.2"
/* Define if we have the Intel JIT API runtime support library */ /* Define if we have the Intel JIT API runtime support library */
#define LLVM_USE_INTEL_JITEVENTS 0 #define LLVM_USE_INTEL_JITEVENTS 0
/* Define if we have the oprofile JIT-support library */ /* Define if we have the oprofile JIT-support library */
#define LLVM_USE_OPROFILE 0 #define LLVM_USE_OPROFILE 0
/* Major version of the LLVM API */ /* Major version of the LLVM API */
#define LLVM_VERSION_MAJOR 3 #define LLVM_VERSION_MAJOR 3
/* Minor version of the LLVM API */ /* Minor version of the LLVM API */
#define LLVM_VERSION_MINOR 1 #define LLVM_VERSION_MINOR 2
/* Define if the OS needs help to load dependent libraries for dlopen(). */ /* Define if the OS needs help to load dependent libraries for dlopen(). */
/* #undef LTDL_DLOPEN_DEPLIBS */ /* #undef LTDL_DLOPEN_DEPLIBS */
/* Define to the sub-directory in which libtool stores uninstalled librarie s. /* Define to the sub-directory in which libtool stores uninstalled librarie s.
*/ */
#define LTDL_OBJDIR ".libs/" #define LTDL_OBJDIR ".libs/"
/* Define to the name of the environment variable that determines the dynam ic /* Define to the name of the environment variable that determines the dynam ic
library search path. */ library search path. */
skipping to change at line 665 skipping to change at line 677
/* Define if dlsym() requires a leading underscore in symbol names. */ /* Define if dlsym() requires a leading underscore in symbol names. */
/* #undef NEED_USCORE */ /* #undef NEED_USCORE */
/* Define to the address where bug reports for this package should be sent. */ /* Define to the address where bug reports for this package should be sent. */
#define PACKAGE_BUGREPORT "http://llvm.org/bugs/" #define PACKAGE_BUGREPORT "http://llvm.org/bugs/"
/* Define to the full name of this package. */ /* Define to the full name of this package. */
#define PACKAGE_NAME "LLVM" #define PACKAGE_NAME "LLVM"
/* Define to the full name and version of this package. */ /* Define to the full name and version of this package. */
#define PACKAGE_STRING "LLVM 3.1" #define PACKAGE_STRING "LLVM 3.2svn"
/* Define to the one symbol short name of this package. */ /* Define to the one symbol short name of this package. */
#define PACKAGE_TARNAME "llvm" #define PACKAGE_TARNAME "llvm"
/* Define to the version of this package. */ /* Define to the version of this package. */
#define PACKAGE_VERSION "3.1" #define PACKAGE_VERSION "3.2svn"
/* Define as the return type of signal handlers (`int' or `void'). */ /* Define as the return type of signal handlers (`int' or `void'). */
#define RETSIGTYPE void #define RETSIGTYPE void
/* Define to 1 if the `S_IS*' macros in <sys/stat.h> do not work properly. */ /* Define to 1 if the `S_IS*' macros in <sys/stat.h> do not work properly. */
/* #undef STAT_MACROS_BROKEN */ /* #undef STAT_MACROS_BROKEN */
/* Define to 1 if you have the ANSI C header files. */ /* Define to 1 if you have the ANSI C header files. */
#define STDC_HEADERS 1 #define STDC_HEADERS 1
 End of changes. 18 change blocks. 
14 lines changed or deleted 26 lines changed or added


 ilist.h   ilist.h 
skipping to change at line 41 skipping to change at line 41
// //
// 1. The user must provide {g|s}et{Next|Prev} methods, or specialize // 1. The user must provide {g|s}et{Next|Prev} methods, or specialize
// ilist_traits to provide an alternate way of getting and setting nex t and // ilist_traits to provide an alternate way of getting and setting nex t and
// prev links. // prev links.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_ADT_ILIST_H #ifndef LLVM_ADT_ILIST_H
#define LLVM_ADT_ILIST_H #define LLVM_ADT_ILIST_H
#include "llvm/Support/Compiler.h"
#include <algorithm> #include <algorithm>
#include <cassert> #include <cassert>
#include <cstddef> #include <cstddef>
#include <iterator> #include <iterator>
namespace llvm { namespace llvm {
template<typename NodeTy, typename Traits> class iplist; template<typename NodeTy, typename Traits> class iplist;
template<typename NodeTy> class ilist_iterator; template<typename NodeTy> class ilist_iterator;
skipping to change at line 332 skipping to change at line 333
/// list has been created and lazily makes it if not. /// list has been created and lazily makes it if not.
void CreateLazySentinel() const { void CreateLazySentinel() const {
this->ensureHead(Head); this->ensureHead(Head);
} }
static bool op_less(NodeTy &L, NodeTy &R) { return L < R; } static bool op_less(NodeTy &L, NodeTy &R) { return L < R; }
static bool op_equal(NodeTy &L, NodeTy &R) { return L == R; } static bool op_equal(NodeTy &L, NodeTy &R) { return L == R; }
// No fundamental reason why iplist can't be copyable, but the default // No fundamental reason why iplist can't be copyable, but the default
// copy/copy-assign won't do. // copy/copy-assign won't do.
iplist(const iplist &); // do not implement iplist(const iplist &) LLVM_DELETED_FUNCTION;
void operator=(const iplist &); // do not implement void operator=(const iplist &) LLVM_DELETED_FUNCTION;
public: public:
typedef NodeTy *pointer; typedef NodeTy *pointer;
typedef const NodeTy *const_pointer; typedef const NodeTy *const_pointer;
typedef NodeTy &reference; typedef NodeTy &reference;
typedef const NodeTy &const_reference; typedef const NodeTy &const_reference;
typedef NodeTy value_type; typedef NodeTy value_type;
typedef ilist_iterator<NodeTy> iterator; typedef ilist_iterator<NodeTy> iterator;
typedef ilist_iterator<const NodeTy> const_iterator; typedef ilist_iterator<const NodeTy> const_iterator;
typedef size_t size_type; typedef size_t size_type;
 End of changes. 2 change blocks. 
2 lines changed or deleted 3 lines changed or added


 llvm-config.h   llvm-config.h 
skipping to change at line 21 skipping to change at line 21
/* This file enumerates all of the llvm variables from configure so that /* This file enumerates all of the llvm variables from configure so that
they can be in exported headers and won't override package specific they can be in exported headers and won't override package specific
directives. This is a C file so we can include it in the llvm-c headers . */ directives. This is a C file so we can include it in the llvm-c headers . */
/* To avoid multiple inclusions of these variables when we include the expo rted /* To avoid multiple inclusions of these variables when we include the expo rted
headers and config.h, conditionally include these. */ headers and config.h, conditionally include these. */
/* TODO: This is a bit of a hack. */ /* TODO: This is a bit of a hack. */
#ifndef CONFIG_H #ifndef CONFIG_H
/* Installation directory for binary executables */ /* Installation directory for binary executables */
#define LLVM_BINDIR "/home/ut/testing/llvm/3.1/bin" #define LLVM_BINDIR "/home/ut/testing/llvm/3.2/bin"
/* Time at which LLVM was configured */ /* Time at which LLVM was configured */
#define LLVM_CONFIGTIME "Wed Jan 9 15:19:52 MSK 2013" #define LLVM_CONFIGTIME "Wed Jan 9 12:07:05 MSK 2013"
/* Installation directory for data files */ /* Installation directory for data files */
#define LLVM_DATADIR "/home/ut/testing/llvm/3.1/share/llvm" #define LLVM_DATADIR "/home/ut/testing/llvm/3.2/share/llvm"
/* Target triple LLVM will generate code for by default */ /* Target triple LLVM will generate code for by default */
#define LLVM_DEFAULT_TARGET_TRIPLE "i686-pc-linux-gnu" #define LLVM_DEFAULT_TARGET_TRIPLE "i686-pc-linux-gnu"
/* Installation directory for documentation */ /* Installation directory for documentation */
#define LLVM_DOCSDIR "/home/ut/testing/llvm/3.1/share/doc/llvm" #define LLVM_DOCSDIR "/home/ut/testing/llvm/3.2/share/doc/llvm"
/* Define if threads enabled */ /* Define if threads enabled */
#define LLVM_ENABLE_THREADS 1 #define LLVM_ENABLE_THREADS 1
/* Installation directory for config files */ /* Installation directory for config files */
#define LLVM_ETCDIR "/home/ut/testing/llvm/3.1/etc/llvm" #define LLVM_ETCDIR "/home/ut/testing/llvm/3.2/etc/llvm"
/* Has gcc/MSVC atomic intrinsics */ /* Has gcc/MSVC atomic intrinsics */
#define LLVM_HAS_ATOMICS 1 #define LLVM_HAS_ATOMICS 1
/* Host triple LLVM will be executed on */
#define LLVM_HOSTTRIPLE "i686-pc-linux-gnu"
/* Installation directory for include files */ /* Installation directory for include files */
#define LLVM_INCLUDEDIR "/home/ut/testing/llvm/3.1/include" #define LLVM_INCLUDEDIR "/home/ut/testing/llvm/3.2/include"
/* Installation directory for .info files */ /* Installation directory for .info files */
#define LLVM_INFODIR "/home/ut/testing/llvm/3.1/info" #define LLVM_INFODIR "/home/ut/testing/llvm/3.2/info"
/* Installation directory for libraries */ /* Installation directory for libraries */
#define LLVM_LIBDIR "/home/ut/testing/llvm/3.1/lib" #define LLVM_LIBDIR "/home/ut/testing/llvm/3.2/lib"
/* Installation directory for man pages */ /* Installation directory for man pages */
#define LLVM_MANDIR "/home/ut/testing/llvm/3.1/man" #define LLVM_MANDIR "/home/ut/testing/llvm/3.2/man"
/* LLVM architecture name for the native architecture, if available */ /* LLVM architecture name for the native architecture, if available */
#define LLVM_NATIVE_ARCH X86 #define LLVM_NATIVE_ARCH X86
/* LLVM name for the native AsmParser init function, if available */ /* LLVM name for the native AsmParser init function, if available */
#define LLVM_NATIVE_ASMPARSER LLVMInitializeX86AsmParser #define LLVM_NATIVE_ASMPARSER LLVMInitializeX86AsmParser
/* LLVM name for the native AsmPrinter init function, if available */ /* LLVM name for the native AsmPrinter init function, if available */
#define LLVM_NATIVE_ASMPRINTER LLVMInitializeX86AsmPrinter #define LLVM_NATIVE_ASMPRINTER LLVMInitializeX86AsmPrinter
skipping to change at line 111 skipping to change at line 114
/* Define to path to neato program if found or 'echo neato' otherwise */ /* Define to path to neato program if found or 'echo neato' otherwise */
#define LLVM_PATH_NEATO "/usr/bin/neato" #define LLVM_PATH_NEATO "/usr/bin/neato"
/* Define to path to twopi program if found or 'echo twopi' otherwise */ /* Define to path to twopi program if found or 'echo twopi' otherwise */
#define LLVM_PATH_TWOPI "/usr/bin/twopi" #define LLVM_PATH_TWOPI "/usr/bin/twopi"
/* Define to path to xdot.py program if found or 'echo xdot.py' otherwise * / /* Define to path to xdot.py program if found or 'echo xdot.py' otherwise * /
/* #undef LLVM_PATH_XDOT_PY */ /* #undef LLVM_PATH_XDOT_PY */
/* Installation prefix directory */ /* Installation prefix directory */
#define LLVM_PREFIX "/home/ut/testing/llvm/3.1" #define LLVM_PREFIX "/home/ut/testing/llvm/3.2"
/* Major version of the LLVM API */ /* Major version of the LLVM API */
#define LLVM_VERSION_MAJOR 3 #define LLVM_VERSION_MAJOR 3
/* Minor version of the LLVM API */ /* Minor version of the LLVM API */
#define LLVM_VERSION_MINOR 1 #define LLVM_VERSION_MINOR 2
#endif #endif
 End of changes. 12 change blocks. 
11 lines changed or deleted 14 lines changed or added


 raw_os_ostream.h   raw_os_ostream.h 
skipping to change at line 29 skipping to change at line 29
namespace llvm { namespace llvm {
/// raw_os_ostream - A raw_ostream that writes to an std::ostream. This is a /// raw_os_ostream - A raw_ostream that writes to an std::ostream. This is a
/// simple adaptor class. It does not check for output errors; clients sho uld /// simple adaptor class. It does not check for output errors; clients sho uld
/// use the underlying stream to detect errors. /// use the underlying stream to detect errors.
class raw_os_ostream : public raw_ostream { class raw_os_ostream : public raw_ostream {
std::ostream &OS; std::ostream &OS;
/// write_impl - See raw_ostream::write_impl. /// write_impl - See raw_ostream::write_impl.
virtual void write_impl(const char *Ptr, size_t Size); virtual void write_impl(const char *Ptr, size_t Size) LLVM_OVERRIDE;
/// current_pos - Return the current position within the stream, not /// current_pos - Return the current position within the stream, not
/// counting the bytes currently in the buffer. /// counting the bytes currently in the buffer.
virtual uint64_t current_pos() const; virtual uint64_t current_pos() const LLVM_OVERRIDE;
public: public:
raw_os_ostream(std::ostream &O) : OS(O) {} raw_os_ostream(std::ostream &O) : OS(O) {}
~raw_os_ostream(); ~raw_os_ostream();
}; };
} // end llvm namespace } // end llvm namespace
#endif #endif
 End of changes. 2 change blocks. 
2 lines changed or deleted 2 lines changed or added


 raw_ostream.h   raw_ostream.h 
skipping to change at line 18 skipping to change at line 18
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// //
// This file defines the raw_ostream class. // This file defines the raw_ostream class.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_SUPPORT_RAW_OSTREAM_H #ifndef LLVM_SUPPORT_RAW_OSTREAM_H
#define LLVM_SUPPORT_RAW_OSTREAM_H #define LLVM_SUPPORT_RAW_OSTREAM_H
#include "llvm/ADT/StringRef.h" #include "llvm/ADT/StringRef.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/DataTypes.h" #include "llvm/Support/DataTypes.h"
namespace llvm { namespace llvm {
class format_object_base; class format_object_base;
template <typename T> template <typename T>
class SmallVectorImpl; class SmallVectorImpl;
/// raw_ostream - This class implements an extremely fast bulk output strea m /// raw_ostream - This class implements an extremely fast bulk output strea m
/// that can *only* output to a stream. It does not support seeking, reope ning, /// that can *only* output to a stream. It does not support seeking, reope ning,
/// rewinding, line buffered disciplines etc. It is a simple buffer that ou tputs /// rewinding, line buffered disciplines etc. It is a simple buffer that ou tputs
/// a chunk at a time. /// a chunk at a time.
class raw_ostream { class raw_ostream {
private: private:
// Do not implement. raw_ostream is noncopyable. // Do not implement. raw_ostream is noncopyable.
void operator=(const raw_ostream &); void operator=(const raw_ostream &) LLVM_DELETED_FUNCTION;
raw_ostream(const raw_ostream &); raw_ostream(const raw_ostream &) LLVM_DELETED_FUNCTION;
/// The buffer is handled in such a way that the buffer is /// The buffer is handled in such a way that the buffer is
/// uninitialized, unbuffered, or out of space when OutBufCur >= /// uninitialized, unbuffered, or out of space when OutBufCur >=
/// OutBufEnd. Thus a single comparison suffices to determine if we /// OutBufEnd. Thus a single comparison suffices to determine if we
/// need to take the slow path to write a single character. /// need to take the slow path to write a single character.
/// ///
/// The buffer is in one of three states: /// The buffer is in one of three states:
/// 1. Unbuffered (BufferMode == Unbuffered) /// 1. Unbuffered (BufferMode == Unbuffered)
/// 1. Uninitialized (BufferMode != Unbuffered && OutBufStart == 0). /// 1. Uninitialized (BufferMode != Unbuffered && OutBufStart == 0).
/// 2. Buffered (BufferMode != Unbuffered && OutBufStart != 0 && /// 2. Buffered (BufferMode != Unbuffered && OutBufStart != 0 &&
skipping to change at line 194 skipping to change at line 195
raw_ostream &operator<<(unsigned int N) { raw_ostream &operator<<(unsigned int N) {
return this->operator<<(static_cast<unsigned long>(N)); return this->operator<<(static_cast<unsigned long>(N));
} }
raw_ostream &operator<<(int N) { raw_ostream &operator<<(int N) {
return this->operator<<(static_cast<long>(N)); return this->operator<<(static_cast<long>(N));
} }
raw_ostream &operator<<(double N); raw_ostream &operator<<(double N);
/// write_hex - Output \arg N in hexadecimal, without any prefix or paddi ng. /// write_hex - Output \p N in hexadecimal, without any prefix or padding .
raw_ostream &write_hex(unsigned long long N); raw_ostream &write_hex(unsigned long long N);
/// write_escaped - Output \arg Str, turning '\\', '\t', '\n', '"', and /// write_escaped - Output \p Str, turning '\\', '\t', '\n', '"', and
/// anything that doesn't satisfy std::isprint into an escape sequence. /// anything that doesn't satisfy std::isprint into an escape sequence.
raw_ostream &write_escaped(StringRef Str, bool UseHexEscapes = false); raw_ostream &write_escaped(StringRef Str, bool UseHexEscapes = false);
raw_ostream &write(unsigned char C); raw_ostream &write(unsigned char C);
raw_ostream &write(const char *Ptr, size_t Size); raw_ostream &write(const char *Ptr, size_t Size);
// Formatted output, see the format() function in Support/Format.h. // Formatted output, see the format() function in Support/Format.h.
raw_ostream &operator<<(const format_object_base &Fmt); raw_ostream &operator<<(const format_object_base &Fmt);
/// indent - Insert 'NumSpaces' spaces. /// indent - Insert 'NumSpaces' spaces.
raw_ostream &indent(unsigned NumSpaces); raw_ostream &indent(unsigned NumSpaces);
/// Changes the foreground color of text that will be output from this po int /// Changes the foreground color of text that will be output from this po int
/// forward. /// forward.
/// @param colors ANSI color to use, the special SAVEDCOLOR can be used t o /// @param Color ANSI color to use, the special SAVEDCOLOR can be used to
/// change only the bold attribute, and keep colors untouched /// change only the bold attribute, and keep colors untouched
/// @param bold bold/brighter text, default false /// @param Bold bold/brighter text, default false
/// @param bg if true change the background, default: change foreground /// @param BG if true change the background, default: change foreground
/// @returns itself so it can be used within << invocations /// @returns itself so it can be used within << invocations
virtual raw_ostream &changeColor(enum Colors, bool = false, bool = false) virtual raw_ostream &changeColor(enum Colors Color,
{ bool Bold = false,
return *this; } bool BG = false) {
(void)Color;
(void)Bold;
(void)BG;
return *this;
}
/// Resets the colors to terminal defaults. Call this when you are done /// Resets the colors to terminal defaults. Call this when you are done
/// outputting colored text, or before program exit. /// outputting colored text, or before program exit.
virtual raw_ostream &resetColor() { return *this; } virtual raw_ostream &resetColor() { return *this; }
/// Reverses the forground and background colors. /// Reverses the forground and background colors.
virtual raw_ostream &reverseColor() { return *this; } virtual raw_ostream &reverseColor() { return *this; }
/// This function determines if this stream is connected to a "tty" or /// This function determines if this stream is connected to a "tty" or
/// "console" window. That is, the output would be displayed to the user /// "console" window. That is, the output would be displayed to the user
/// rather than being put on a pipe or stored in a file. /// rather than being put on a pipe or stored in a file.
virtual bool is_displayed() const { return false; } virtual bool is_displayed() const { return false; }
/// This function determines if this stream is displayed and supports col
ors.
virtual bool has_colors() const { return is_displayed(); }
//===-------------------------------------------------------------------- ===// //===-------------------------------------------------------------------- ===//
// Subclass Interface // Subclass Interface
//===-------------------------------------------------------------------- ===// //===-------------------------------------------------------------------- ===//
private: private:
/// write_impl - The is the piece of the class that is implemented /// write_impl - The is the piece of the class that is implemented
/// by subclasses. This writes the \args Size bytes starting at /// by subclasses. This writes the \p Size bytes starting at
/// \arg Ptr to the underlying stream. /// \p Ptr to the underlying stream.
/// ///
/// This function is guaranteed to only be called at a point at which it is /// This function is guaranteed to only be called at a point at which it is
/// safe for the subclass to install a new buffer via SetBuffer. /// safe for the subclass to install a new buffer via SetBuffer.
/// ///
/// \arg Ptr - The start of the data to be written. For buffered streams this /// \param Ptr The start of the data to be written. For buffered streams this
/// is guaranteed to be the start of the buffer. /// is guaranteed to be the start of the buffer.
/// \arg Size - The number of bytes to be written. ///
/// \param Size The number of bytes to be written.
/// ///
/// \invariant { Size > 0 } /// \invariant { Size > 0 }
virtual void write_impl(const char *Ptr, size_t Size) = 0; virtual void write_impl(const char *Ptr, size_t Size) = 0;
// An out of line virtual method to provide a home for the class vtable. // An out of line virtual method to provide a home for the class vtable.
virtual void handle(); virtual void handle();
/// current_pos - Return the current position within the stream, not /// current_pos - Return the current position within the stream, not
/// counting the bytes currently in the buffer. /// counting the bytes currently in the buffer.
virtual uint64_t current_pos() const = 0; virtual uint64_t current_pos() const = 0;
skipping to change at line 313 skipping to change at line 324
/// ///
bool Error; bool Error;
/// Controls whether the stream should attempt to use atomic writes, when /// Controls whether the stream should attempt to use atomic writes, when
/// possible. /// possible.
bool UseAtomicWrites; bool UseAtomicWrites;
uint64_t pos; uint64_t pos;
/// write_impl - See raw_ostream::write_impl. /// write_impl - See raw_ostream::write_impl.
virtual void write_impl(const char *Ptr, size_t Size); virtual void write_impl(const char *Ptr, size_t Size) LLVM_OVERRIDE;
/// current_pos - Return the current position within the stream, not /// current_pos - Return the current position within the stream, not
/// counting the bytes currently in the buffer. /// counting the bytes currently in the buffer.
virtual uint64_t current_pos() const { return pos; } virtual uint64_t current_pos() const LLVM_OVERRIDE { return pos; }
/// preferred_buffer_size - Determine an efficient buffer size. /// preferred_buffer_size - Determine an efficient buffer size.
virtual size_t preferred_buffer_size() const; virtual size_t preferred_buffer_size() const LLVM_OVERRIDE;
/// error_detected - Set the flag indicating that an output error has /// error_detected - Set the flag indicating that an output error has
/// been encountered. /// been encountered.
void error_detected() { Error = true; } void error_detected() { Error = true; }
public: public:
enum { enum {
/// F_Excl - When opening a file, this flag makes raw_fd_ostream /// F_Excl - When opening a file, this flag makes raw_fd_ostream
/// report an error if the file already exists. /// report an error if the file already exists.
skipping to change at line 381 skipping to change at line 392
/// individual output routines where possible. /// individual output routines where possible.
/// ///
/// Note that because raw_ostream's are typically buffered, this flag is only /// Note that because raw_ostream's are typically buffered, this flag is only
/// sensible when used on unbuffered streams which will flush their outpu t /// sensible when used on unbuffered streams which will flush their outpu t
/// immediately. /// immediately.
void SetUseAtomicWrites(bool Value) { void SetUseAtomicWrites(bool Value) {
UseAtomicWrites = Value; UseAtomicWrites = Value;
} }
virtual raw_ostream &changeColor(enum Colors colors, bool bold=false, virtual raw_ostream &changeColor(enum Colors colors, bool bold=false,
bool bg=false); bool bg=false) LLVM_OVERRIDE;
virtual raw_ostream &resetColor(); virtual raw_ostream &resetColor() LLVM_OVERRIDE;
virtual raw_ostream &reverseColor() LLVM_OVERRIDE;
virtual raw_ostream &reverseColor(); virtual bool is_displayed() const LLVM_OVERRIDE;
virtual bool is_displayed() const; virtual bool has_colors() const LLVM_OVERRIDE;
/// has_error - Return the value of the flag in this raw_fd_ostream indic ating /// has_error - Return the value of the flag in this raw_fd_ostream indic ating
/// whether an output error has been encountered. /// whether an output error has been encountered.
/// This doesn't implicitly flush any pending output. Also, it doesn't /// This doesn't implicitly flush any pending output. Also, it doesn't
/// guarantee to detect all errors unless the the stream has been closed. /// guarantee to detect all errors unless the stream has been closed.
bool has_error() const { bool has_error() const {
return Error; return Error;
} }
/// clear_error - Set the flag read by has_error() to false. If the error /// clear_error - Set the flag read by has_error() to false. If the error
/// flag is set at the time when this raw_ostream's destructor is called, /// flag is set at the time when this raw_ostream's destructor is called,
/// report_fatal_error is called to report the error. Use clear_error() /// report_fatal_error is called to report the error. Use clear_error()
/// after handling the error to avoid this behavior. /// after handling the error to avoid this behavior.
/// ///
/// "Errors should never pass silently. /// "Errors should never pass silently.
skipping to change at line 432 skipping to change at line 445
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
// Output Stream Adaptors // Output Stream Adaptors
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
/// raw_string_ostream - A raw_ostream that writes to an std::string. This is a /// raw_string_ostream - A raw_ostream that writes to an std::string. This is a
/// simple adaptor class. This class does not encounter output errors. /// simple adaptor class. This class does not encounter output errors.
class raw_string_ostream : public raw_ostream { class raw_string_ostream : public raw_ostream {
std::string &OS; std::string &OS;
/// write_impl - See raw_ostream::write_impl. /// write_impl - See raw_ostream::write_impl.
virtual void write_impl(const char *Ptr, size_t Size); virtual void write_impl(const char *Ptr, size_t Size) LLVM_OVERRIDE;
/// current_pos - Return the current position within the stream, not /// current_pos - Return the current position within the stream, not
/// counting the bytes currently in the buffer. /// counting the bytes currently in the buffer.
virtual uint64_t current_pos() const { return OS.size(); } virtual uint64_t current_pos() const LLVM_OVERRIDE { return OS.size(); }
public: public:
explicit raw_string_ostream(std::string &O) : OS(O) {} explicit raw_string_ostream(std::string &O) : OS(O) {}
~raw_string_ostream(); ~raw_string_ostream();
/// str - Flushes the stream contents to the target string and returns /// str - Flushes the stream contents to the target string and returns
/// the string's reference. /// the string's reference.
std::string& str() { std::string& str() {
flush(); flush();
return OS; return OS;
} }
}; };
/// raw_svector_ostream - A raw_ostream that writes to an SmallVector or /// raw_svector_ostream - A raw_ostream that writes to an SmallVector or
/// SmallString. This is a simple adaptor class. This class does not /// SmallString. This is a simple adaptor class. This class does not
/// encounter output errors. /// encounter output errors.
class raw_svector_ostream : public raw_ostream { class raw_svector_ostream : public raw_ostream {
SmallVectorImpl<char> &OS; SmallVectorImpl<char> &OS;
/// write_impl - See raw_ostream::write_impl. /// write_impl - See raw_ostream::write_impl.
virtual void write_impl(const char *Ptr, size_t Size); virtual void write_impl(const char *Ptr, size_t Size) LLVM_OVERRIDE;
/// current_pos - Return the current position within the stream, not /// current_pos - Return the current position within the stream, not
/// counting the bytes currently in the buffer. /// counting the bytes currently in the buffer.
virtual uint64_t current_pos() const; virtual uint64_t current_pos() const LLVM_OVERRIDE;
public: public:
/// Construct a new raw_svector_ostream. /// Construct a new raw_svector_ostream.
/// ///
/// \arg O - The vector to write to; this should generally have at least 128 /// \param O The vector to write to; this should generally have at least 128
/// bytes free to avoid any extraneous memory overhead. /// bytes free to avoid any extraneous memory overhead.
explicit raw_svector_ostream(SmallVectorImpl<char> &O); explicit raw_svector_ostream(SmallVectorImpl<char> &O);
~raw_svector_ostream(); ~raw_svector_ostream();
/// resync - This is called when the SmallVector we're appending to is ch anged /// resync - This is called when the SmallVector we're appending to is ch anged
/// outside of the raw_svector_ostream's control. It is only safe to do this /// outside of the raw_svector_ostream's control. It is only safe to do this
/// if the raw_svector_ostream has previously been flushed. /// if the raw_svector_ostream has previously been flushed.
void resync(); void resync();
/// str - Flushes the stream contents to the target vector and return a /// str - Flushes the stream contents to the target vector and return a
/// StringRef for the vector contents. /// StringRef for the vector contents.
StringRef str(); StringRef str();
}; };
/// raw_null_ostream - A raw_ostream that discards all output. /// raw_null_ostream - A raw_ostream that discards all output.
class raw_null_ostream : public raw_ostream { class raw_null_ostream : public raw_ostream {
/// write_impl - See raw_ostream::write_impl. /// write_impl - See raw_ostream::write_impl.
virtual void write_impl(const char *Ptr, size_t size); virtual void write_impl(const char *Ptr, size_t size) LLVM_OVERRIDE;
/// current_pos - Return the current position within the stream, not /// current_pos - Return the current position within the stream, not
/// counting the bytes currently in the buffer. /// counting the bytes currently in the buffer.
virtual uint64_t current_pos() const; virtual uint64_t current_pos() const LLVM_OVERRIDE;
public: public:
explicit raw_null_ostream() {} explicit raw_null_ostream() {}
~raw_null_ostream(); ~raw_null_ostream();
}; };
} // end llvm namespace } // end llvm namespace
#endif #endif
 End of changes. 25 change blocks. 
29 lines changed or deleted 42 lines changed or added


 system_error.h   system_error.h 
skipping to change at line 20 skipping to change at line 20
// This was lifted from libc++ and modified for C++03. This is called // This was lifted from libc++ and modified for C++03. This is called
// system_error even though it does not define that class because that's wh at // system_error even though it does not define that class because that's wh at
// it's called in C++0x. We don't define system_error because it is only us ed // it's called in C++0x. We don't define system_error because it is only us ed
// for exception handling, which we don't use in LLVM. // for exception handling, which we don't use in LLVM.
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_SYSTEM_SYSTEM_ERROR_H #ifndef LLVM_SYSTEM_SYSTEM_ERROR_H
#define LLVM_SYSTEM_SYSTEM_ERROR_H #define LLVM_SYSTEM_SYSTEM_ERROR_H
#include "llvm/Support/Compiler.h"
/* /*
system_error synopsis system_error synopsis
namespace std namespace std
{ {
class error_category class error_category
{ {
public: public:
virtual ~error_category(); virtual ~error_category();
skipping to change at line 632 skipping to change at line 634
class _do_message; class _do_message;
class error_category class error_category
{ {
public: public:
virtual ~error_category(); virtual ~error_category();
private: private:
error_category(); error_category();
error_category(const error_category&);// = delete; error_category(const error_category&) LLVM_DELETED_FUNCTION;
error_category& operator=(const error_category&);// = delete; error_category& operator=(const error_category&) LLVM_DELETED_FUNCTION;
public: public:
virtual const char* name() const = 0; virtual const char* name() const = 0;
virtual error_condition default_error_condition(int _ev) const; virtual error_condition default_error_condition(int _ev) const;
virtual bool equivalent(int _code, const error_condition& _condition) con st; virtual bool equivalent(int _code, const error_condition& _condition) con st;
virtual bool equivalent(const error_code& _code, int _condition) const; virtual bool equivalent(const error_code& _code, int _condition) const;
virtual std::string message(int _ev) const = 0; virtual std::string message(int _ev) const = 0;
bool operator==(const error_category& _rhs) const {return this == &_rhs;} bool operator==(const error_category& _rhs) const {return this == &_rhs;}
bool operator!=(const error_category& _rhs) const {return !(*this == _rhs );} bool operator!=(const error_category& _rhs) const {return !(*this == _rhs );}
bool operator< (const error_category& _rhs) const {return this < &_rhs;} bool operator< (const error_category& _rhs) const {return this < &_rhs;}
friend class _do_message; friend class _do_message;
}; };
class _do_message : public error_category class _do_message : public error_category
{ {
public: public:
virtual std::string message(int ev) const; virtual std::string message(int ev) const LLVM_OVERRIDE;
}; };
const error_category& generic_category(); const error_category& generic_category();
const error_category& system_category(); const error_category& system_category();
/// Get the error_category used for errno values from POSIX functions. This is /// Get the error_category used for errno values from POSIX functions. This is
/// the same as the system_category on POSIX systems, but is the same as th e /// the same as the system_category on POSIX systems, but is the same as th e
/// generic_category on Windows. /// generic_category on Windows.
const error_category& posix_category(); const error_category& posix_category();
 End of changes. 3 change blocks. 
3 lines changed or deleted 5 lines changed or added


 type_traits.h   type_traits.h 
skipping to change at line 24 skipping to change at line 24
// //
//===---------------------------------------------------------------------- ===// //===---------------------------------------------------------------------- ===//
#ifndef LLVM_SUPPORT_TYPE_TRAITS_H #ifndef LLVM_SUPPORT_TYPE_TRAITS_H
#define LLVM_SUPPORT_TYPE_TRAITS_H #define LLVM_SUPPORT_TYPE_TRAITS_H
#include "llvm/Support/DataTypes.h" #include "llvm/Support/DataTypes.h"
#include <cstddef> #include <cstddef>
#include <utility> #include <utility>
#ifndef __has_feature
#define LLVM_DEFINED_HAS_FEATURE
#define __has_feature(x) 0
#endif
// This is actually the conforming implementation which works with abstract // This is actually the conforming implementation which works with abstract
// classes. However, enough compilers have trouble with it that most will use // classes. However, enough compilers have trouble with it that most will use
// the one in boost/type_traits/object_traits.hpp. This implementation actu ally // the one in boost/type_traits/object_traits.hpp. This implementation actu ally
// works with VC7.0, but other interactions seem to fail when we use it. // works with VC7.0, but other interactions seem to fail when we use it.
namespace llvm { namespace llvm {
namespace dont_use namespace dont_use
{ {
// These two functions should never be used. They are helpers to // These two functions should never be used. They are helpers to
skipping to change at line 52 skipping to change at line 57
template<typename T> char is_class_helper(void(T::*)()); template<typename T> char is_class_helper(void(T::*)());
template<typename T> double is_class_helper(...); template<typename T> double is_class_helper(...);
} }
template <typename T> template <typename T>
struct is_class struct is_class
{ {
// is_class<> metafunction due to Paul Mensonides (leavings@attbi.com). F or // is_class<> metafunction due to Paul Mensonides (leavings@attbi.com). F or
// more details: // more details:
// http://groups.google.com/groups?hl=en&selm=000001c1cc83%24e154d5e0%247 772e50c%40c161550a&rnum=1 // http://groups.google.com/groups?hl=en&selm=000001c1cc83%24e154d5e0%247 772e50c%40c161550a&rnum=1
public: public:
enum { value = sizeof(char) == sizeof(dont_use::is_class_helper<T>(0)) static const bool value =
}; sizeof(char) == sizeof(dont_use::is_class_helper<T>(0));
}; };
/// isPodLike - This is a type trait that is used to determine whether a gi ven /// isPodLike - This is a type trait that is used to determine whether a gi ven
/// type can be copied around with memcpy instead of running ctors etc. /// type can be copied around with memcpy instead of running ctors etc.
template <typename T> template <typename T>
struct isPodLike { struct isPodLike {
#if __has_feature(is_trivially_copyable)
// If the compiler supports the is_trivially_copyable trait use it, as it
// matches the definition of isPodLike closely.
static const bool value = __is_trivially_copyable(T);
#else
// If we don't know anything else, we can (at least) assume that all non- class // If we don't know anything else, we can (at least) assume that all non- class
// types are PODs. // types are PODs.
static const bool value = !is_class<T>::value; static const bool value = !is_class<T>::value;
#endif
}; };
// std::pair's are pod-like if their elements are. // std::pair's are pod-like if their elements are.
template<typename T, typename U> template<typename T, typename U>
struct isPodLike<std::pair<T, U> > { struct isPodLike<std::pair<T, U> > {
static const bool value = isPodLike<T>::value && isPodLike<U>::value; static const bool value = isPodLike<T>::value && isPodLike<U>::value;
}; };
template <class T, T v> template <class T, T v>
struct integral_constant { struct integral_constant {
skipping to change at line 152 skipping to change at line 164
// convertible to an unsigned long long. This should catch integer types and // convertible to an unsigned long long. This should catch integer types and
// enumeration types at least. We blacklist classes with conversion opera tors // enumeration types at least. We blacklist classes with conversion opera tors
// below. // below.
static double check_int_convertible(unsigned long long); static double check_int_convertible(unsigned long long);
static char check_int_convertible(...); static char check_int_convertible(...);
typedef typename remove_reference<T>::type UnderlyingT; typedef typename remove_reference<T>::type UnderlyingT;
static UnderlyingT &nonce_instance; static UnderlyingT &nonce_instance;
public: public:
enum { static const bool
value = (!is_class<UnderlyingT>::value && !is_pointer<UnderlyingT>::val ue && value = (!is_class<UnderlyingT>::value && !is_pointer<UnderlyingT>::val ue &&
!is_same<UnderlyingT, float>::value && !is_same<UnderlyingT, float>::value &&
!is_same<UnderlyingT, double>::value && !is_same<UnderlyingT, double>::value &&
sizeof(char) != sizeof(check_int_convertible(nonce_instance))) sizeof(char) != sizeof(check_int_convertible(nonce_instance)))
}; ;
}; };
// enable_if_c - Enable/disable a template based on a metafunction // enable_if_c - Enable/disable a template based on a metafunction
template<bool Cond, typename T = void> template<bool Cond, typename T = void>
struct enable_if_c { struct enable_if_c {
typedef T type; typedef T type;
}; };
template<typename T> struct enable_if_c<false, T> { }; template<typename T> struct enable_if_c<false, T> { };
skipping to change at line 203 skipping to change at line 214
typedef T type; }; typedef T type; };
template <bool, typename T, typename F> template <bool, typename T, typename F>
struct conditional { typedef T type; }; struct conditional { typedef T type; };
template <typename T, typename F> template <typename T, typename F>
struct conditional<false, T, F> { typedef F type; }; struct conditional<false, T, F> { typedef F type; };
} }
#ifdef LLVM_DEFINED_HAS_FEATURE
#undef __has_feature
#endif
#endif #endif
 End of changes. 7 change blocks. 
6 lines changed or deleted 21 lines changed or added

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